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`timescale 1 ns / 1 ns
//////////////////////////////////////////////////////////////////////////////////
// Company: Rehkopf
// Engineer: Rehkopf
//
// Create Date: 01:13:46 05/09/2009
// Design Name:
// Module Name: main
// Project Name:
// Target Devices:
// Tool versions:
// Description: Master Control FSM
//
// Dependencies: address
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`include "config.vh"
module main(
`ifdef MK2
/* Bus 1: PSRAM, 128Mbit, 16bit, 70ns */
output [22:0] ROM_ADDR,
output ROM_CE,
input MCU_OVR,
/* debug */
output p113_out,
`endif
`ifdef MK3
input SNES_CIC_CLK,
/* Bus 1: 2x PSRAM, 64Mbit, 16bit, 70ns */
output [21:0] ROM_ADDR,
output ROM_1CE,
output ROM_2CE,
output ROM_ZZ,
/* debug */
output PM6_out,
output PN6_out,
input PT5_in,
`endif
/* input clock */
input CLKIN,
/* SNES signals */
input [23:0] SNES_ADDR_IN,
input SNES_READ_IN,
input SNES_WRITE_IN,
input SNES_ROMSEL_IN,
inout [7:0] SNES_DATA,
input SNES_CPU_CLK_IN,
input SNES_REFRESH,
output SNES_IRQ,
output SNES_DATABUS_OE,
output SNES_DATABUS_DIR,
input SNES_SYSCLK,
input [7:0] SNES_PA_IN,
input SNES_PARD_IN,
input SNES_PAWR_IN,
/* SRAM signals */
inout [15:0] ROM_DATA,
output ROM_OE,
output ROM_WE,
output ROM_BHE,
output ROM_BLE,
/* Bus 2: SRAM, 4Mbit, 8bit, 45ns */
inout [7:0] RAM_DATA,
output [18:0] RAM_ADDR,
output RAM_OE,
output RAM_WE,
/* MCU signals */
input SPI_MOSI,
inout SPI_MISO,
input SPI_SS,
input SPI_SCK,
output MCU_RDY,
output DAC_MCLK,
output DAC_LRCK,
output DAC_SDOUT,
/* SD signals */
input [3:0] SD_DAT,
inout SD_CMD,
inout SD_CLK
);
wire CLK2;
wire MCU_ROM;
wire MCU_RAM;
wire MCU_RRQ;
wire MCU_WRQ;
wire [7:0] MCU_DOUT;
wire [7:0] spi_cmd_data;
wire [7:0] spi_param_data;
wire [7:0] spi_input_data;
wire [31:0] spi_byte_cnt;
wire [2:0] spi_bit_cnt;
wire [23:0] MCU_ADDR;
wire [3:0] MAPPER;
wire [23:0] SAVERAM_MASK;
wire [23:0] ROM_MASK;
wire [7:0] SD_DMA_SRAM_DATA;
wire [1:0] SD_DMA_TGT;
wire [10:0] SD_DMA_PARTIAL_START;
wire [10:0] SD_DMA_PARTIAL_END;
wire [10:0] dac_addr;
wire [2:0] dac_vol_select_out;
wire [8:0] dac_ptr_addr;
//wire [7:0] dac_volume;
wire [7:0] msu_volumerq_out;
wire [7:0] msu_status_out;
wire [31:0] msu_addressrq_out;
wire [15:0] msu_trackrq_out;
wire [13:0] msu_write_addr;
wire [13:0] msu_ptr_addr;
wire [7:0] MSU_SNES_DATA_IN;
wire [7:0] MSU_SNES_DATA_OUT;
wire [5:0] msu_status_reset_bits;
wire [5:0] msu_status_set_bits;
wire [7:0] SGB_SNES_DATA_IN;
wire [7:0] SGB_SNES_DATA_OUT;
wire [19:0] SGB_APU_DAT;
wire [55:0] SGB_RTC_DAT;
wire [55:0] MCU_RTC_DAT;
wire MCU_RTC_WE;
wire MCU_RTC_RD;
wire SGB_ROM_RRQ;
wire SGB_ROM_WRQ;
wire sgb_enable;
wire [15:0] sgb_feat;
wire [15:0] featurebits;
wire feat_cmd_unlock = featurebits[5];
wire [23:0] MAPPED_SNES_ADDR;
wire ROM_ADDR0;
wire [13:0] DBG_msu_address;
wire DBG_msu_reg_oe_rising;
wire DBG_msu_reg_oe_falling;
wire DBG_msu_reg_we_rising;
wire [2:0] SD_DMA_DBG_clkcnt;
wire [10:0] SD_DMA_DBG_cyclecnt;
wire [15:0] dsp_feat;
wire [8:0] snescmd_addr_mcu;
wire [7:0] snescmd_data_out_mcu;
wire [7:0] snescmd_data_in_mcu;
// config
wire [7:0] reg_group;
wire [7:0] reg_index;
wire [7:0] reg_value;
wire [7:0] reg_invmask;
wire reg_we;
wire [7:0] reg_read;
// unit level configuration output
wire [7:0] sgb_config_data;
reg [7:0] SNES_PARDr = 8'b11111111;
reg [7:0] SNES_PAWRr = 8'b11111111;
reg [7:0] SNES_READr = 8'b11111111;
reg [7:0] SNES_WRITEr = 8'b11111111;
reg [7:0] SNES_CPU_CLKr = 8'b00000000;
reg [7:0] SNES_ROMSELr = 8'b11111111;
reg [7:0] SNES_PULSEr = 8'b11111111;
reg [23:0] SNES_ADDRr [6:0];
reg [7:0] SNES_PAr [6:0];
reg [7:0] SNES_DATAr [4:0];
reg SNES_DEADr = 1;
reg SNES_reset_strobe = 0;
reg free_strobe = 0;
reg ram_free_strobe = 0;
wire [23:0] SNES_ADDR = (SNES_ADDRr[6] & SNES_ADDRr[5]);
wire [7:0] SNES_PA = (SNES_PAr[6] & SNES_PAr[5]);
wire [7:0] SNES_DATA_IN = (SNES_DATAr[3] & SNES_DATAr[2]);
wire SNES_PULSE_IN = SNES_READ_IN & SNES_WRITE_IN & ~SNES_CPU_CLK_IN;
wire SNES_PULSE_end = (SNES_PULSEr[6:1] == 6'b000011);
wire SNES_PARD_start = (SNES_PARDr[6:1] == 6'b111110);
wire SNES_PARD_end = (SNES_PARDr[6:1] == 6'b000001);
// Sample PAWR data earlier on CPU accesses, later on DMA accesses...
wire SNES_PAWR_start = (SNES_PAWRr[7:1] == (({SNES_ADDR[22], SNES_ADDR[15:0]} == 17'h02100) ? 7'b1110000 : 7'b1000000));
wire SNES_PAWR_end = (SNES_PAWRr[6:1] == 6'b000001);
wire SNES_RD_start = (SNES_READr[6:1] == 6'b111110);
wire SNES_RD_end = (SNES_READr[6:1] == 6'b000001);
wire SNES_WR_end = (SNES_WRITEr[6:1] == 6'b000001);
wire SNES_cycle_start = (SNES_CPU_CLKr[6:1] == 6'b000001);
wire SNES_cycle_end = (SNES_CPU_CLKr[6:1] == 6'b111110);
wire SNES_WRITE = SNES_WRITEr[2] & SNES_WRITEr[1];
wire SNES_READ = SNES_READr[2] & SNES_READr[1];
wire SNES_READ_late = SNES_READr[5] & SNES_READr[4];
wire SNES_READ_narrow = SNES_READ | SNES_READ_late;
wire SNES_CPU_CLK = SNES_CPU_CLKr[2] & SNES_CPU_CLKr[1];
wire SNES_PARD = SNES_PARDr[2] & SNES_PARDr[1];
wire SNES_PAWR = SNES_PAWRr[2] & SNES_PAWRr[1];
wire SNES_ROMSEL = (SNES_ROMSELr[5] & SNES_ROMSELr[4]);
reg [7:0] BUS_DATA;
always @(posedge CLK2) begin
if(~SNES_READ) BUS_DATA <= SNES_DATA;
else if(~SNES_WRITE) BUS_DATA <= SNES_DATA_IN;
end
wire SGB_FREE_SLOT;
wire free_slot = SGB_FREE_SLOT;
wire ram_free_slot;
wire ROM_HIT;
wire IS_ROM;
assign DCM_RST=0;
wire IS_SAVERAM;
always @(posedge CLK2) begin
SNES_PULSEr <= {SNES_PULSEr[6:0], SNES_PULSE_IN};
SNES_PARDr <= {SNES_PARDr[6:0], SNES_PARD_IN};
SNES_PAWRr <= {SNES_PAWRr[6:0], SNES_PAWR_IN};
SNES_READr <= {SNES_READr[6:0], SNES_READ_IN};
SNES_WRITEr <= {SNES_WRITEr[6:0], SNES_WRITE_IN};
SNES_CPU_CLKr <= {SNES_CPU_CLKr[6:0], SNES_CPU_CLK_IN};
SNES_ROMSELr <= {SNES_ROMSELr[6:0], SNES_ROMSEL_IN};
SNES_ADDRr[6] <= SNES_ADDRr[5];
SNES_ADDRr[5] <= SNES_ADDRr[4];
SNES_ADDRr[4] <= SNES_ADDRr[3];
SNES_ADDRr[3] <= SNES_ADDRr[2];
SNES_ADDRr[2] <= SNES_ADDRr[1];
SNES_ADDRr[1] <= SNES_ADDRr[0];
SNES_ADDRr[0] <= SNES_ADDR_IN;
SNES_PAr[6] <= SNES_PAr[5];
SNES_PAr[5] <= SNES_PAr[4];
SNES_PAr[4] <= SNES_PAr[3];
SNES_PAr[3] <= SNES_PAr[2];
SNES_PAr[2] <= SNES_PAr[1];
SNES_PAr[1] <= SNES_PAr[0];
SNES_PAr[0] <= SNES_PA_IN;
SNES_DATAr[4] <= SNES_DATAr[3];
SNES_DATAr[3] <= SNES_DATAr[2];
SNES_DATAr[2] <= SNES_DATAr[1];
SNES_DATAr[1] <= SNES_DATAr[0];
SNES_DATAr[0] <= SNES_DATA;
end
parameter ST_IDLE = 9'b000000001;
parameter ST_MCU_RD_ADDR = 9'b000000010;
parameter ST_MCU_RD_END = 9'b000000100;
parameter ST_MCU_WR_ADDR = 9'b000001000;
parameter ST_MCU_WR_END = 9'b000010000;
parameter ST_SGB_ROM_RD_ADDR = 9'b000100000;
parameter ST_SGB_ROM_RD_END = 9'b001000000;
parameter ST_SGB_ROM_WR_ADDR = 9'b010000000;
parameter ST_SGB_ROM_WR_END = 9'b100000000;
parameter SNES_DEAD_TIMEOUT = 17'd84000; // 1ms
parameter ROM_CYCLE_LEN = 4'd7;
reg [8:0] STATE;
initial STATE = ST_IDLE;
assign MSU_SNES_DATA_IN = BUS_DATA;
assign SGB_SNES_DATA_IN = BUS_DATA;
sd_dma snes_sd_dma(
.CLK(CLK2),
.SD_DAT(SD_DAT),
.SD_CLK(SD_CLK),
.SD_DMA_EN(SD_DMA_EN),
.SD_DMA_STATUS(SD_DMA_STATUS),
.SD_DMA_SRAM_WE(SD_DMA_SRAM_WE),
.SD_DMA_SRAM_DATA(SD_DMA_SRAM_DATA),
.SD_DMA_NEXTADDR(SD_DMA_NEXTADDR),
.SD_DMA_PARTIAL(SD_DMA_PARTIAL),
.SD_DMA_PARTIAL_START(SD_DMA_PARTIAL_START),
.SD_DMA_PARTIAL_END(SD_DMA_PARTIAL_END),
.SD_DMA_START_MID_BLOCK(SD_DMA_START_MID_BLOCK),
.SD_DMA_END_MID_BLOCK(SD_DMA_END_MID_BLOCK),
.DBG_cyclecnt(SD_DMA_DBG_cyclecnt),
.DBG_clkcnt(SD_DMA_DBG_clkcnt)
);
wire SD_DMA_TO_ROM = (SD_DMA_STATUS && (SD_DMA_TGT == 2'b00)) && MCU_ROM;
wire SD_DMA_TO_RAM = (SD_DMA_STATUS && (SD_DMA_TGT == 2'b00)) && MCU_RAM;
dac snes_dac(
.clkin(CLK2),
.sysclk(SNES_SYSCLK),
.mclk_out(DAC_MCLK),
.lrck_out(DAC_LRCK),
.sdout(DAC_SDOUT),
.we(SD_DMA_TGT==2'b01 ? SD_DMA_SRAM_WE : 1'b1),
.pgm_address(dac_addr),
.pgm_data(SD_DMA_SRAM_DATA),
.DAC_STATUS(DAC_STATUS),
.volume(msu_volumerq_out),
.sgb_apu_dat(SGB_APU_DAT),
.sgb_apu_clk_edge(SGB_APU_CLK_EDGE),
.vol_latch(msu_volume_latch_out),
.vol_select(dac_vol_select_out),
.sgb_vol_select(sgb_feat[`SGB_FEAT_VOL_BOOST]),
.palmode(dac_palmode_out),
.play(dac_play),
.reset(dac_reset),
.dac_address_ext(dac_ptr_addr)
);
msu snes_msu (
.clkin(CLK2),
.enable(msu_enable),
.pgm_address(msu_write_addr),
.pgm_data(SD_DMA_SRAM_DATA),
.pgm_we(SD_DMA_TGT==2'b10 ? SD_DMA_SRAM_WE : 1'b1),
.reg_addr(SNES_ADDR[2:0]),
.reg_data_in(MSU_SNES_DATA_IN),
.reg_data_out(MSU_SNES_DATA_OUT),
.reg_oe_falling(SNES_RD_start),
.reg_oe_rising(SNES_RD_end),
.reg_we_rising(SNES_WR_end),
.status_out(msu_status_out),
.volume_out(msu_volumerq_out),
.volume_latch_out(msu_volume_latch_out),
.addr_out(msu_addressrq_out),
.track_out(msu_trackrq_out),
.status_reset_bits(msu_status_reset_bits),
.status_set_bits(msu_status_set_bits),
.status_reset_we(msu_status_reset_we),
.msu_address_ext(msu_ptr_addr),
.msu_address_ext_write(msu_addr_reset),
.DBG_msu_reg_oe_rising(DBG_msu_reg_oe_rising),
.DBG_msu_reg_oe_falling(DBG_msu_reg_oe_falling),
.DBG_msu_reg_we_rising(DBG_msu_reg_we_rising),
.DBG_msu_address(DBG_msu_address),
.DBG_msu_address_ext_write_rising(DBG_msu_address_ext_write_rising)
);
spi snes_spi(
.clk(CLK2),
.MOSI(SPI_MOSI),
.MISO(SPI_MISO),
.SSEL(SPI_SS),
.SCK(SPI_SCK),
.cmd_ready(spi_cmd_ready),
.param_ready(spi_param_ready),
.cmd_data(spi_cmd_data),
.param_data(spi_param_data),
.endmessage(spi_endmessage),
.startmessage(spi_startmessage),
.input_data(spi_input_data),
.byte_cnt(spi_byte_cnt),
.bit_cnt(spi_bit_cnt)
);
// RAM contains the SNES ROM and is memory mapped to 880000-8FFFFF
assign MCU_RAM = MCU_ADDR[23:19] == {4'h8,1'b1};
`ifdef SGB_MCU_ACCESS
// 800000-8FFFFF is owned by RAM and SGB except for WRAM at 80C000-80DFFF. Any MCU accesses to mirrored SRAM needs to instead access Exxxxx directly and not 80A000.
assign MCU_ROM = (MCU_ADDR[23:20] != 4'h8 || {MCU_ADDR[19:13],1'b0} == 8'h0C || MCU_ADDR[23:8] == 16'h8000);
`else
assign MCU_ROM = ~MCU_RAM;
`endif
reg [7:0] SGB_ROM_DINr;
wire [23:0] SGB_ROM_ADDR;
wire SGB_ROM_WORD;
wire [7:0] SGB_ROM_DATA;
wire SGB_MCU_RSP;
wire [7:0] SGB_MCU_DIN;
// MCU accesses to SGB state
reg RQ_SGB_MCU_RDYr = 1;
reg MCU_SGB_RD_PENDr = 0;
reg MCU_SGB_WR_PENDr = 0;
reg [18:0] SGB_ADDRr;
always @(posedge CLK2) begin
if(MCU_RRQ & ~(MCU_ROM | MCU_RAM)) begin
MCU_SGB_RD_PENDr <= 1'b1;
RQ_SGB_MCU_RDYr <= 1'b0;
SGB_ADDRr <= MCU_ADDR[18:0];
end else if(MCU_WRQ & ~(MCU_ROM | MCU_RAM)) begin
MCU_SGB_WR_PENDr <= 1'b1;
RQ_SGB_MCU_RDYr <= 1'b0;
SGB_ADDRr <= MCU_ADDR[18:0];
end else if(SGB_MCU_RSP) begin
MCU_SGB_RD_PENDr <= 1'b0;
MCU_SGB_WR_PENDr <= 1'b0;
RQ_SGB_MCU_RDYr <= 1'b1;
end
end
//-------------------------------------------------------------------
// SGB
//-------------------------------------------------------------------
// CTX saves and restores architectural visible (and other state).
// When enabled, the SaveRAM portion of the PSRAM is used
// capture up to 64KB of additional state covering one saved image.
parameter
ST_CTX_IDLE = 4'b0001,
ST_CTX_HALT = 4'b0010,
ST_CTX_READ = 4'b0100,
ST_CTX_WRITE = 4'b1000;
reg [3:0] ctx_state_r = ST_CTX_IDLE;
reg ctx_mode_r;
reg ctx_req_r;
reg [15:0] ctx_addr_r;
reg [7:0] ctx_data_r;
wire button_ctx_valid;
wire button_ctx_mode;
wire SGB_reset;
wire ctx_active = |(ctx_state_r & (ST_CTX_READ | ST_CTX_WRITE));
wire ctx_rrq = ctx_req_r & |(ctx_state_r & ST_CTX_READ);
wire ctx_wrq = ctx_req_r & |(ctx_state_r & ST_CTX_WRITE);
// Use the lower 32KB (normally ROM) for SaveRAM. State is located in second 64KB of PSRAM's SaveRAM region.
wire [23:0] ctx_addr = (|(ctx_state_r & ST_CTX_READ) ^ ctx_mode_r) ? {(ctx_addr_r[15] ? 8'h80 : 8'hE0),ctx_addr_r} : {8'hE1,ctx_addr_r};
wire mcu_rdy_int;
wire mcu_rrq_int;
wire mcu_wrq_int;
wire [23:0] mcu_addr_int;
wire [7:0] mcu_dout_int;
wire HLT_REQ = ~|(ctx_state_r & ST_CTX_IDLE);
wire HLT_RSP;
wire [11:0] DBG_ADDR;
wire [7:0] DBG_CHEAT_DATA_OUT;
wire [7:0] CTX_DINr;
// MCU mux
assign MCU_RDY = ctx_active ? 0 : mcu_rdy_int;
assign MCU_RRQ = ctx_active ? ctx_rrq : mcu_rrq_int;
assign MCU_WRQ = ctx_active ? ctx_wrq : mcu_wrq_int;
assign MCU_ADDR = ctx_active ? ctx_addr : mcu_addr_int;
assign MCU_DOUT = ctx_active ? ctx_data_r : mcu_dout_int;
`ifdef SGB_SAVE_STATES
always @(posedge CLK2) begin
if (SNES_reset_strobe | SGB_reset) begin
ctx_state_r <= ST_CTX_IDLE;
ctx_addr_r <= 0;
end
else begin
ctx_req_r <= 0;
case (ctx_state_r)
ST_CTX_IDLE: begin
ctx_mode_r <= button_ctx_mode;
if (button_ctx_valid & ~HLT_RSP) ctx_state_r <= ST_CTX_HALT;
end
ST_CTX_HALT: begin
if (HLT_RSP & ~(mcu_rrq_int| mcu_wrq_int) & mcu_rdy_int) begin
ctx_req_r <= 1;
ctx_state_r <= ST_CTX_READ;
end
end
ST_CTX_READ: begin
ctx_data_r <= CTX_DINr;
if (~ctx_req_r & mcu_rdy_int) begin
ctx_req_r <= 1;
ctx_state_r <= ST_CTX_WRITE;
end
end
ST_CTX_WRITE: begin
if (~ctx_req_r & mcu_rdy_int) begin
ctx_req_r <= 1;
ctx_addr_r <= ctx_addr_r + 1;
// TODO: decide if making save states a little faster is worth the extra logic (and bugs?)
//ctx_addr_r <= ( (~ctx_addr_r[15] && ctx_addr_r[14:0] == SAVERAM_MASK[14:0]) ? 16'h8000
// : (ctx_addr_r == 16'h9FFF) ? 16'hC000
// : ctx_addr_r + 1
// );
ctx_state_r <= &ctx_addr_r ? ST_CTX_IDLE : ST_CTX_READ;
end
end
endcase
end
end
`endif
reg [7:0] dbg_data_r;
always @(posedge CLK2) begin
casez(DBG_ADDR[3:0])
4'h0: dbg_data_r <= ctx_state_r;
4'h1: dbg_data_r <= ctx_mode_r;
4'h2: dbg_data_r <= ctx_req_r;
4'h3: dbg_data_r <= ctx_data_r;
4'h4: dbg_data_r <= ctx_addr_r[7:0];
4'h5: dbg_data_r <= ctx_addr_r[15:8];
4'h6: dbg_data_r <= HLT_REQ;
4'h7: dbg_data_r <= HLT_RSP;
default: dbg_data_r <= 0;
endcase
end
sgb snes_sgb (
.RST(SNES_reset_strobe),
.CPU_RST(SGB_reset),
.CLK(CLK2),
.CLK_SYSCLK(SNES_SYSCLK),
// MMIO interface
.SNES_RD_start(SNES_RD_start),
.SNES_WR_end(SNES_WR_end),
.SNES_ADDR(SNES_ADDR),
.DATA_IN(SGB_SNES_DATA_IN),
.DATA_OUT(SGB_SNES_DATA_OUT),
// ROM interface
.ROM_BUS_RDY(SGB_ROM_RDY),
.ROM_BUS_RRQ(SGB_ROM_RRQ),
.ROM_BUS_WRQ(SGB_ROM_WRQ),
.ROM_BUS_WORD(SGB_ROM_WORD),
.ROM_BUS_ADDR(SGB_ROM_ADDR),
.ROM_BUS_WRDATA(SGB_ROM_DATA),
.ROM_BUS_RDDATA(SGB_ROM_DINr),
.ROM_FREE_SLOT(SGB_FREE_SLOT),
// Audio interface
.APU_DAT(SGB_APU_DAT),
.APU_CLK_EDGE(SGB_APU_CLK_EDGE),
// RTC interface
.RTC_DAT(SGB_RTC_DAT),
.RTC_DAT_IN(MCU_RTC_DAT),
.RTC_DAT_WE(MCU_RTC_WE),
.RTC_DAT_RD(MCU_RTC_RD),
// MBC interface
.MAPPER(MAPPER),
.SAVERAM_MASK(SAVERAM_MASK),
.ROM_MASK(ROM_MASK),
// Halt interface
.HLT_REQ(HLT_REQ),
.HLT_RSP(HLT_RSP),
// State debug read interface
.MCU_RRQ(MCU_SGB_RD_PENDr),
.MCU_WRQ(MCU_SGB_WR_PENDr),
.MCU_ADDR(SGB_ADDRr[18:0]),
.MCU_DATA_IN(MCU_DOUT),
.MCU_RSP(SGB_MCU_RSP),
.MCU_DATA_OUT(SGB_MCU_DIN),
// features
.FEAT(sgb_feat),
// config
.reg_group_in(reg_group),
.reg_index_in(reg_index),
.reg_value_in(reg_value),
.reg_invmask_in(reg_invmask),
.reg_we_in(reg_we),
.reg_read_in(reg_read),
.config_data_out(sgb_config_data),
.DBG_ADDR(DBG_ADDR),
.DBG_CHEAT_DATA_IN(DBG_CHEAT_DATA_OUT),
.DBG_MAIN_DATA_IN(dbg_data_r)
);
reg [7:0] MCU_DINr;
assign CTX_DINr = MCU_DINr;
reg [7:0] MCU_ROM_DINr;
reg [7:0] MCU_RAM_DINr;
wire [31:0] cheat_pgm_data;
wire [7:0] cheat_data_out;
wire [2:0] cheat_pgm_idx;
mcu_cmd snes_mcu_cmd(
.clk(CLK2),
.snes_sysclk(SNES_SYSCLK),
.cmd_ready(spi_cmd_ready),
.param_ready(spi_param_ready),
.cmd_data(spi_cmd_data),
.param_data(spi_param_data),
.mcu_mapper(MAPPER),
.mcu_write(MCU_WRITE),
.mcu_data_in(MCU_DINr),
.mcu_data_out(mcu_dout_int),
.spi_byte_cnt(spi_byte_cnt),
.spi_bit_cnt(spi_bit_cnt),
.spi_data_out(spi_input_data),
.addr_out(mcu_addr_int),
.saveram_mask_out(SAVERAM_MASK),
.rom_mask_out(ROM_MASK),
.SD_DMA_EN(SD_DMA_EN),
.SD_DMA_STATUS(SD_DMA_STATUS),
.SD_DMA_NEXTADDR(SD_DMA_NEXTADDR),
.SD_DMA_SRAM_DATA(SD_DMA_SRAM_DATA),
.SD_DMA_SRAM_WE(SD_DMA_SRAM_WE),
.SD_DMA_TGT(SD_DMA_TGT),
.SD_DMA_PARTIAL(SD_DMA_PARTIAL),
.SD_DMA_PARTIAL_START(SD_DMA_PARTIAL_START),
.SD_DMA_PARTIAL_END(SD_DMA_PARTIAL_END),
.SD_DMA_START_MID_BLOCK(SD_DMA_START_MID_BLOCK),
.SD_DMA_END_MID_BLOCK(SD_DMA_END_MID_BLOCK),
.dac_addr_out(dac_addr),
.DAC_STATUS(DAC_STATUS),
.dac_play_out(dac_play),
.dac_reset_out(dac_reset),
.dac_vol_select_out(dac_vol_select_out),
.dac_palmode_out(dac_palmode_out),
.dac_ptr_out(dac_ptr_addr),
.msu_addr_out(msu_write_addr),
.MSU_STATUS(msu_status_out),
.msu_status_reset_out(msu_status_reset_bits),
.msu_status_set_out(msu_status_set_bits),
.msu_status_reset_we(msu_status_reset_we),
.msu_volumerq(msu_volumerq_out),
.msu_addressrq(msu_addressrq_out),
.msu_trackrq(msu_trackrq_out),
.msu_ptr_out(msu_ptr_addr),
.msu_reset_out(msu_addr_reset),
.rtc_data_in(SGB_RTC_DAT),
.rtc_data_out(MCU_RTC_DAT),
.rtc_pgm_we(MCU_RTC_WE),
.rtc_pgm_rd(MCU_RTC_RD),
.sgb_feat_out(sgb_feat),
// config
.reg_group_out(reg_group),
.reg_index_out(reg_index),
.reg_value_out(reg_value),
.reg_invmask_out(reg_invmask),
.reg_we_out(reg_we),
.reg_read_out(reg_read),
// vv config data in vv
.sgb_config_data_in(sgb_config_data),
// ^^ config data in ^^
.featurebits_out(featurebits),
.mcu_rrq(mcu_rrq_int),
.mcu_wrq(mcu_wrq_int),
.mcu_rq_rdy(MCU_RDY),
.region_out(mcu_region),
.snescmd_addr_out(snescmd_addr_mcu),
.snescmd_we_out(snescmd_we_mcu),
.snescmd_data_out(snescmd_data_out_mcu),
.snescmd_data_in(snescmd_data_in_mcu),
.cheat_pgm_idx_out(cheat_pgm_idx),
.cheat_pgm_data_out(cheat_pgm_data),
.cheat_pgm_we_out(cheat_pgm_we),
.dsp_feat_out(dsp_feat)
);
wire button_enable;
wire button_addr;
address snes_addr(
.CLK(CLK2),
//.MAPPER(MAPPER),
.featurebits(featurebits),
.SNES_ADDR(SNES_ADDR), // requested address from SNES
.SNES_PA(SNES_PA),
.SNES_ROMSEL(SNES_ROMSEL),
.ROM_ADDR(MAPPED_SNES_ADDR), // Address to request from SRAM (active low)
.ROM_HIT(ROM_HIT), // want to access RAM0
.IS_SAVERAM(IS_SAVERAM),
.IS_ROM(IS_ROM),
.IS_WRITABLE(IS_WRITABLE),
//.SAVERAM_MASK(SAVERAM_MASK),
//.ROM_MASK(ROM_MASK),
//MSU-1
.msu_enable(msu_enable),
.sgb_enable(sgb_enable),
.r213f_enable(r213f_enable),
.r2100_hit(r2100_hit),
.snescmd_enable(snescmd_enable),
.button_enable(button_enable),
.button_addr(button_addr)
);
reg pad_latch = 0;
reg [4:0] pad_cnt = 0;
reg snes_ajr = 0;
wire snescmd_we_cheat;
wire [8:0] snescmd_addr_cheat;
wire [7:0] snescmd_data_cheat;
cheat snes_cheat(
.clk(CLK2),
.SNES_ADDR(SNES_ADDR),
.SNES_PA(SNES_PA),
.SNES_DATA(SNES_DATA),
.SNES_reset_strobe(SNES_reset_strobe),
.SNES_wr_strobe(SNES_WR_end),
.SNES_rd_strobe(SNES_RD_start),
.snescmd_enable(snescmd_enable),
.button_enable(button_enable),
.button_addr(button_addr),
.snescmd_rdy(ram_free_slot),
.snescmd_we_cheat(snescmd_we_cheat),
.snescmd_addr_cheat(snescmd_addr_cheat),
.snescmd_data_cheat(snescmd_data_cheat),
.button_ctx_valid(button_ctx_valid),
.button_ctx_mode(button_ctx_mode),
.DBG_ADDR(DBG_ADDR),
.DBG_DATA_OUT(DBG_CHEAT_DATA_OUT),
.pad_latch(pad_latch),
.snes_ajr(snes_ajr),
.SNES_cycle_start(SNES_cycle_start),
.pgm_idx(cheat_pgm_idx),
.pgm_we(cheat_pgm_we),
.pgm_in(cheat_pgm_data),
.data_out(cheat_data_out),
.cheat_hit(cheat_hit),
.snescmd_unlock(snescmd_unlock)
);
wire [7:0] snescmd_dout;
parameter ST_R213F_ARMED = 4'b0001;
parameter ST_R213F_WAITBUS = 4'b0010;
parameter ST_R213F_OVERRIDE = 4'b0100;
parameter ST_R213F_HOLD = 4'b1000;
reg [7:0] r213fr;
reg r213f_forceread;
reg [2:0] r213f_delay;
reg [1:0] r213f_state;
initial r213fr = 8'h55;
initial r213f_forceread = 0;
initial r213f_state = 2'b01;
initial r213f_delay = 3'b000;
reg [7:0] r2100r = 0;
reg r2100_forcewrite = 0;
reg r2100_forcewrite_pre = 0;
`ifdef BRIGHTNESS_LIMIT
wire [3:0] r2100_limit = featurebits[10:7];
`else
wire [3:0] r2100_limit = 4'hF;
`endif
wire [3:0] r2100_limited = (SNES_DATA[3:0] > r2100_limit) ? r2100_limit : SNES_DATA[3:0];
`ifdef BRIGHTNESS_PATCH
wire r2100_patch = featurebits[6];
`else
wire r2100_patch = 0;
`endif
wire r2100_enable = r2100_hit & (r2100_patch | ~(&r2100_limit));
wire snoop_4200_enable = {SNES_ADDR[22], SNES_ADDR[15:0]} == 17'h04200;
wire r4016_enable = {SNES_ADDR[22], SNES_ADDR[15:0]} == 17'h04016;
always @(posedge CLK2) begin
r2100_forcewrite <= r2100_forcewrite_pre;
end
always @(posedge CLK2) begin
if(SNES_WR_end & snoop_4200_enable) begin
snes_ajr <= SNES_DATA[0];
end
end
always @(posedge CLK2) begin
if(SNES_WR_end & r4016_enable) begin
pad_latch <= 1'b1;
pad_cnt <= 5'h0;
end
if(SNES_RD_start & r4016_enable) begin
pad_cnt <= pad_cnt + 1;
if(&pad_cnt[3:0]) begin
pad_latch <= 1'b0;
end
end
end
reg nmi_match; initial nmi_match = 0;
reg irq_match; initial irq_match = 0;
always @(posedge CLK2) nmi_match <= {SNES_ADDR[23:1],1'b0} == 24'h00FFEA;
always @(posedge CLK2) irq_match <= {SNES_ADDR[23:1],1'b0} == 24'h00FFEE;
assign SNES_DATA = (r213f_enable & ~SNES_PARD & ~r213f_forceread) ? r213fr
:(r2100_enable & ~SNES_PAWR & r2100_forcewrite) ? r2100r
:((~SNES_READ ^ (r213f_forceread & r213f_enable & ~SNES_PARD))
& ~(r2100_enable & ~SNES_PAWR & ~r2100_forcewrite & ~IS_ROM & ~IS_WRITABLE & ~sgb_enable))
? ( msu_enable ? MSU_SNES_DATA_OUT
: sgb_enable ? SGB_SNES_DATA_OUT // SGB MMIO read
: (cheat_hit & ~feat_cmd_unlock) ? cheat_data_out
: ((snescmd_unlock | feat_cmd_unlock) & snescmd_enable) ? snescmd_dout
: RAM_DATA // the RAM module holds up to 512KB
) : 8'bZ;
reg [3:0] ST_MEM_DELAYr;
// MCU
reg MCU_RD_PENDr = 0;
reg MCU_WR_PENDr = 0;
reg [23:0] ROM_ADDRr;
reg RQ_MCU_RDYr;
initial RQ_MCU_RDYr = 1'b1;
wire MCU_WE_HIT = |(STATE & ST_MCU_WR_ADDR);
wire MCU_WR_HIT = |(STATE & (ST_MCU_WR_ADDR | ST_MCU_WR_END));
wire MCU_RD_HIT = |(STATE & (ST_MCU_RD_ADDR | ST_MCU_RD_END));
wire MCU_HIT = MCU_WR_HIT | MCU_RD_HIT;
// SGB ROM
reg SGB_ROM_RD_PENDr; initial SGB_ROM_RD_PENDr = 0;
reg SGB_ROM_WR_PENDr; initial SGB_ROM_WR_PENDr = 0;
reg [23:0] SGB_ROM_ADDRr;
reg [7:0] SGB_ROM_DATAr;
reg SGB_ROM_WORDr;
reg RQ_SGB_ROM_RDYr; initial RQ_SGB_ROM_RDYr = 1;
assign SGB_ROM_RDY = RQ_SGB_ROM_RDYr;
wire SGB_WE_HIT = |(STATE & ST_SGB_ROM_WR_ADDR);
wire SGB_ROM_RD_HIT = |(STATE & (ST_SGB_ROM_RD_ADDR | ST_SGB_ROM_RD_END));
wire SGB_ROM_WR_HIT = |(STATE & (ST_SGB_ROM_WR_ADDR | ST_SGB_ROM_WR_END));
wire SGB_ROM_HIT = SGB_ROM_RD_HIT | SGB_ROM_WR_HIT;
`ifdef MK2
my_dcm snes_dcm(
.CLKIN(CLKIN),
.CLKFX(CLK2),
.LOCKED(DCM_LOCKED),
.RST(DCM_RST)
);
assign ROM_ADDR = (SD_DMA_TO_ROM) ? MCU_ADDR[23:1] : MCU_HIT ? ROM_ADDRr[23:1] : /*SGB_ROM_HIT ?*/ SGB_ROM_ADDRr[23:1];
assign ROM_ADDR0 = (SD_DMA_TO_ROM) ? MCU_ADDR[0] : MCU_HIT ? ROM_ADDRr[0] : /*SGB_ROM_HIT ?*/ SGB_ROM_ADDRr[0];
assign ROM_CE = 1'b0;
assign p113_out = 1'b0;
snescmd_buf snescmd (
.clka(CLK2), // input clka
.wea(snescmd_we_cheat | (SNES_WR_end & ((snescmd_unlock | feat_cmd_unlock) & snescmd_enable))), // input [0 : 0] wea
.addra(snescmd_we_cheat ? snescmd_addr_cheat : SNES_ADDR[8:0]), // input [8 : 0] addra
.dina(snescmd_we_cheat ? snescmd_data_cheat : SNES_DATA), // input [7 : 0] dina
.douta(snescmd_dout), // output [7 : 0] douta
.clkb(CLK2), // input clkb
.web(snescmd_we_mcu), // input [0 : 0] web
.addrb(snescmd_addr_mcu), // input [8 : 0] addrb
.dinb(snescmd_data_out_mcu), // input [7 : 0] dinb
.doutb(snescmd_data_in_mcu) // output [7 : 0] doutb
);
`endif
`ifdef MK3
pll snes_pll(
.inclk0(CLKIN),
.c0(CLK2),
.locked(DCM_LOCKED),
.areset(DCM_RST)
);
wire ROM_ADDR22;
assign ROM_ADDR22 = (SD_DMA_TO_ROM) ? MCU_ADDR[1] : MCU_HIT ? ROM_ADDRr[1] : SGB_ROM_ADDRr[1];
assign ROM_ADDR = (SD_DMA_TO_ROM) ? MCU_ADDR[23:2] : MCU_HIT ? ROM_ADDRr[23:2] : SGB_ROM_ADDRr[23:2];
assign ROM_ADDR0 = (SD_DMA_TO_ROM) ? MCU_ADDR[0] : MCU_HIT ? ROM_ADDRr[0] : SGB_ROM_ADDRr[0];
assign ROM_ZZ = 1'b1;
assign ROM_1CE = ROM_ADDR22;
assign ROM_2CE = ~ROM_ADDR22;
snescmd_buf snescmd (
.clock(CLK2), // input clka
.wren_a(snescmd_we_cheat | (SNES_WR_end & ((snescmd_unlock | feat_cmd_unlock) & snescmd_enable))), // input [0 : 0] wea
.address_a(snescmd_we_cheat ? snescmd_addr_cheat : SNES_ADDR[8:0]), // input [8 : 0] addra
.data_a(snescmd_we_cheat ? snescmd_data_cheat : SNES_DATA), // input [7 : 0] dina
.q_a(snescmd_dout), // output [7 : 0] douta
.wren_b(snescmd_we_mcu), // input [0 : 0] web
.address_b(snescmd_addr_mcu), // input [8 : 0] addrb
.data_b(snescmd_data_out_mcu), // input [7 : 0] dinb
.q_b(snescmd_data_in_mcu) // output [7 : 0] doutb
);
`endif
// OE always active. Overridden by WE when needed.
assign ROM_OE = 1'b0;
reg[17:0] SNES_DEAD_CNTr;
initial SNES_DEAD_CNTr = 0;
// MCU r/w request
always @(posedge CLK2) begin
if(MCU_RRQ & MCU_ROM) begin
MCU_RD_PENDr <= 1'b1;
RQ_MCU_RDYr <= 1'b0;
ROM_ADDRr <= MCU_ADDR;
end else if(MCU_WRQ & MCU_ROM) begin
MCU_WR_PENDr <= 1'b1;
RQ_MCU_RDYr <= 1'b0;
ROM_ADDRr <= MCU_ADDR;
end else if(STATE & (ST_MCU_RD_END | ST_MCU_WR_END)) begin
MCU_RD_PENDr <= 1'b0;
MCU_WR_PENDr <= 1'b0;
RQ_MCU_RDYr <= 1'b1;
end
end
// SGB ROM r/w request
always @(posedge CLK2) begin
if(SGB_ROM_RRQ) begin
SGB_ROM_RD_PENDr <= 1'b1;
RQ_SGB_ROM_RDYr <= 1'b0;
SGB_ROM_ADDRr <= SGB_ROM_ADDR;
SGB_ROM_WORDr <= SGB_ROM_WORD;
end else if(SGB_ROM_WRQ) begin
SGB_ROM_WR_PENDr <= 1'b1;
RQ_SGB_ROM_RDYr <= 1'b0;
SGB_ROM_ADDRr <= SGB_ROM_ADDR;
SGB_ROM_WORDr <= SGB_ROM_WORD;
SGB_ROM_DATAr <= SGB_ROM_DATA;
end else if(|(STATE & (ST_SGB_ROM_RD_ADDR)) & ~|ST_MEM_DELAYr) begin
// enable rdy/response 1 cycle earlier
RQ_SGB_ROM_RDYr <= 1'b1;
end else if(STATE & (ST_SGB_ROM_RD_END | ST_SGB_ROM_WR_END)) begin
SGB_ROM_RD_PENDr <= 1'b0;
SGB_ROM_WR_PENDr <= 1'b0;
RQ_SGB_ROM_RDYr <= 1'b1;
end
end
always @(posedge CLK2) begin
if(~SNES_CPU_CLKr[1]) SNES_DEAD_CNTr <= SNES_DEAD_CNTr + 1;
else SNES_DEAD_CNTr <= 17'h0;
end
always @(posedge CLK2) begin
SNES_reset_strobe <= 1'b0;
if(SNES_CPU_CLKr[1]) begin
SNES_DEADr <= 1'b0;
if(SNES_DEADr) SNES_reset_strobe <= 1'b1;
end
else if(SNES_DEAD_CNTr > SNES_DEAD_TIMEOUT) SNES_DEADr <= 1'b1;
end
always @(posedge CLK2) begin
if(SNES_DEADr & SNES_CPU_CLKr[1]) STATE <= ST_IDLE; // interrupt+restart an ongoing MCU access when the SNES comes alive
else
case(STATE)
ST_IDLE: begin
STATE <= ST_IDLE;
if (SGB_ROM_RD_PENDr) begin
STATE <= ST_SGB_ROM_RD_ADDR;
ST_MEM_DELAYr <= ROM_CYCLE_LEN;
end
else if (SGB_ROM_WR_PENDr) begin
STATE <= ST_SGB_ROM_WR_ADDR;
ST_MEM_DELAYr <= ROM_CYCLE_LEN;
end
else if (free_slot | SNES_DEADr) begin
if(MCU_RD_PENDr) begin
STATE <= ST_MCU_RD_ADDR;
ST_MEM_DELAYr <= ROM_CYCLE_LEN;
end else if(MCU_WR_PENDr) begin
STATE <= ST_MCU_WR_ADDR;
ST_MEM_DELAYr <= ROM_CYCLE_LEN;
end
end
end
ST_MCU_RD_ADDR: begin
STATE <= ST_MCU_RD_ADDR;
ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
if(ST_MEM_DELAYr == 0) STATE <= ST_MCU_RD_END;
MCU_ROM_DINr <= (ROM_ADDR0 ? ROM_DATA[7:0] : ROM_DATA[15:8]);
end
ST_MCU_WR_ADDR: begin
STATE <= ST_MCU_WR_ADDR;
ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
if(ST_MEM_DELAYr == 0) STATE <= ST_MCU_WR_END;
end
ST_SGB_ROM_RD_ADDR: begin
STATE <= ST_SGB_ROM_RD_ADDR;
ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
if(ST_MEM_DELAYr == 0) STATE <= ST_SGB_ROM_RD_END;
SGB_ROM_DINr <= (ROM_ADDR0 ? ROM_DATA[7:0] : ROM_DATA[15:8]);
end
ST_SGB_ROM_WR_ADDR: begin
STATE <= ST_SGB_ROM_WR_ADDR;
ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
if(ST_MEM_DELAYr == 0) STATE <= ST_SGB_ROM_WR_END;
end
ST_MCU_RD_END, ST_MCU_WR_END, ST_SGB_ROM_RD_END, ST_SGB_ROM_WR_END: begin
STATE <= ST_IDLE;
end
endcase
end
/***********************
* R213F read patching *
***********************/
always @(posedge CLK2) begin
case(r213f_state)
ST_R213F_HOLD: begin
r213f_state <= ST_R213F_HOLD;
if(SNES_PULSE_end) begin
r213f_forceread <= 1'b1;
r213f_state <= ST_R213F_ARMED;
end
end
ST_R213F_ARMED: begin
r213f_state <= ST_R213F_ARMED;
if(SNES_PARD_start & r213f_enable) begin
r213f_delay <= 3'b001;
r213f_state <= ST_R213F_WAITBUS;
end
end
ST_R213F_WAITBUS: begin
r213f_state <= ST_R213F_WAITBUS;
r213f_delay <= r213f_delay - 1;
if(r213f_delay == 3'b000) begin
r213f_state <= ST_R213F_OVERRIDE;
r213fr <= {SNES_DATA[7:5], mcu_region, SNES_DATA[3:0]};
end
end
ST_R213F_OVERRIDE: begin
r213f_state <= ST_R213F_HOLD;
r213f_forceread <= 1'b0;
end
endcase
end
/*********************************
* R2100 patching (experimental) *
*********************************/
reg [3:0] r2100_bright = 0;
reg [3:0] r2100_bright_orig = 0;
always @(posedge CLK2) begin
if(SNES_PULSE_end) r2100_forcewrite_pre <= 1'b0;
else if(SNES_PAWR_start & r2100_hit) begin
if(r2100_patch & SNES_DATA[7]) begin
// keep previous brightness during forced blanking so there is no DAC step
r2100_forcewrite_pre <= 1'b1;
r2100r <= {SNES_DATA[7], 3'b010, r2100_bright}; // 0xAx
end else if (r2100_patch && SNES_DATA == 8'h00 && r2100r[7]) begin
// extend forced blanking when game goes from blanking to brightness 0 (Star Fox top of screen)
r2100_forcewrite_pre <= 1'b1;
r2100r <= {1'b1, 3'b111, r2100_bright}; // 0xFx
end else if (r2100_patch && SNES_DATA[3:0] < 4'h8 && r2100_bright_orig > 4'hd) begin
// substitute big brightness changes with brightness 0 (so it is visible on 1CHIP)
r2100_forcewrite_pre <= 1'b1;
r2100r <= {SNES_DATA[7], 3'b011, 4'h0}; // 0x3x / 0xBx(!)
end else if (r2100_patch | ~(&r2100_limit)) begin
// save brightness, limit brightness
r2100_bright <= r2100_limited;
r2100_bright_orig <= SNES_DATA[3:0];
if (~(&r2100_limit) && SNES_DATA[3:0] > r2100_limit) begin
r2100_forcewrite_pre <= 1'b1;
r2100r <= {SNES_DATA[7], 3'b100, r2100_limited}; // 0x4x / 0xCx
end
end
end
end
reg MCU_WRITE_1;
always @(posedge CLK2) MCU_WRITE_1<= MCU_WRITE;
// odd addresses xxx1
assign ROM_DATA[7:0] = ROM_ADDR0
?(SD_DMA_TO_ROM ? (!MCU_WRITE_1 ? MCU_DOUT : 8'bZ)
: SGB_ROM_WR_HIT ? SGB_ROM_DATAr
: MCU_WR_HIT ? MCU_DOUT : 8'bZ
)
:8'bZ;
// even addresses xxx0
assign ROM_DATA[15:8] = ROM_ADDR0
? 8'bZ
:(SD_DMA_TO_ROM ? (!MCU_WRITE_1 ? MCU_DOUT : 8'bZ)
: SGB_ROM_WR_HIT ? SGB_ROM_DATAr
: MCU_WR_HIT ? MCU_DOUT
: 8'bZ
);
assign ROM_WE = SD_DMA_TO_ROM
?MCU_WRITE
: SGB_WE_HIT ? 1'b0
: MCU_WE_HIT ? 1'b0
: 1'b1;
assign ROM_BHE = ROM_ADDR0 && !(!SD_DMA_TO_ROM && SGB_ROM_HIT && SGB_ROM_WORDr);
assign ROM_BLE = !ROM_ADDR0 && !(!SD_DMA_TO_ROM && SGB_ROM_HIT && SGB_ROM_WORDr);
//--------------
// RAM Pipeline
//--------------
parameter ST_RAM_IDLE = 5'b00001;
parameter ST_RAM_MCU_RD_ADDR = 5'b00010;
parameter ST_RAM_MCU_RD_END = 5'b00100;
parameter ST_RAM_MCU_WR_ADDR = 5'b01000;
parameter ST_RAM_MCU_WR_END = 5'b10000;
parameter RAM_CYCLE_LEN = 4'd5;
reg [4:0] RAM_STATE; initial RAM_STATE = ST_RAM_IDLE;
reg [3:0] ST_RAM_DELAYr;
assign ram_free_slot = SNES_PULSE_end | ram_free_strobe;
// Provide full bandwidth if snes is not accessing the bus.
always @(posedge CLK2) begin
ram_free_strobe <= 1'b0;
if (SNES_cycle_start) ram_free_strobe <= ~ROM_HIT;
end
// MCU state machine
reg MCU_RAM_RD_PENDr = 0;
reg MCU_RAM_WR_PENDr = 0;
reg [18:0] RAM_ADDRr;
reg RQ_RAM_MCU_RDYr;
initial RQ_RAM_MCU_RDYr = 1'b1;
wire MCU_RAM_WE_HIT = |(RAM_STATE & ST_RAM_MCU_WR_ADDR);
wire MCU_RAM_WR_HIT = |(RAM_STATE & (ST_RAM_MCU_WR_ADDR | ST_RAM_MCU_WR_END));
wire MCU_RAM_RD_HIT = |(RAM_STATE & (ST_RAM_MCU_RD_ADDR | ST_RAM_MCU_RD_END));
wire MCU_RAM_HIT = MCU_RAM_WR_HIT | MCU_RAM_RD_HIT;
// MCU RAM1 r/w request
always @(posedge CLK2) begin
if(MCU_RRQ & MCU_RAM) begin
MCU_RAM_RD_PENDr <= 1'b1;
RQ_RAM_MCU_RDYr <= 1'b0;
RAM_ADDRr <= MCU_ADDR;
end else if(MCU_WRQ & MCU_RAM) begin
MCU_RAM_WR_PENDr <= 1'b1;
RQ_RAM_MCU_RDYr <= 1'b0;
RAM_ADDRr <= MCU_ADDR;
end else if(RAM_STATE & (ST_RAM_MCU_RD_END | ST_RAM_MCU_WR_END)) begin
MCU_RAM_RD_PENDr <= 1'b0;
MCU_RAM_WR_PENDr <= 1'b0;
RQ_RAM_MCU_RDYr <= 1'b1;
end
end
// RAM state machine
always @(posedge CLK2) begin
if(SNES_DEADr & SNES_CPU_CLKr[1]) RAM_STATE <= ST_RAM_IDLE; // interrupt+restart an ongoing MCU access when the SNES comes alive
else
case(RAM_STATE)
ST_RAM_IDLE: begin
if(ram_free_slot | SNES_DEADr) begin
if(MCU_RAM_RD_PENDr) begin
RAM_STATE <= ST_RAM_MCU_RD_ADDR;
ST_RAM_DELAYr <= RAM_CYCLE_LEN;
end
else if(MCU_RAM_WR_PENDr) begin
RAM_STATE <= ST_RAM_MCU_WR_ADDR;
ST_RAM_DELAYr <= RAM_CYCLE_LEN;
end
end
end
ST_RAM_MCU_RD_ADDR: begin
ST_RAM_DELAYr <= ST_RAM_DELAYr - 1;
if(ST_RAM_DELAYr == 0) RAM_STATE <= ST_RAM_MCU_RD_END;
MCU_RAM_DINr <= RAM_DATA;
end
ST_RAM_MCU_WR_ADDR: begin
ST_RAM_DELAYr <= ST_RAM_DELAYr - 1;
if(ST_RAM_DELAYr == 0) RAM_STATE <= ST_RAM_MCU_WR_END;
end
ST_RAM_MCU_RD_END, ST_RAM_MCU_WR_END: begin
RAM_STATE <= ST_RAM_IDLE;
end
endcase
end
assign RAM_ADDR = (SD_DMA_TO_RAM) ? MCU_ADDR[18:0] : MCU_RAM_HIT ? RAM_ADDRr[18:0] : MAPPED_SNES_ADDR[18:0];
assign RAM_DATA[7:0] = (SD_DMA_TO_RAM ? (!MCU_WRITE_1 ? MCU_DOUT : 8'bZ)
: (ROM_HIT & ~SNES_WRITE) ? SNES_DATA
: MCU_RAM_WR_HIT ? MCU_DOUT
: 8'bZ
);
// NOTE: IS_SAVERAM should never assert
assign RAM_WE = (SD_DMA_TO_RAM ? MCU_WRITE
: (ROM_HIT & IS_SAVERAM & SNES_CPU_CLK) ? SNES_WRITE
: MCU_RAM_WE_HIT ? 1'b0
: 1'b1
);
assign RAM_OE = 1'b0;
always @(posedge CLK2) begin
// flop data based on source
if (STATE & ST_MCU_RD_END) begin
MCU_DINr <= MCU_ROM_DINr;
end
else if (RAM_STATE & ST_RAM_MCU_RD_END) begin
MCU_DINr <= MCU_RAM_DINr;
end
else if (MCU_SGB_RD_PENDr & SGB_MCU_RSP) begin
MCU_DINr <= SGB_MCU_DIN;
end
end
assign mcu_rdy_int = RQ_MCU_RDYr & RQ_RAM_MCU_RDYr & RQ_SGB_MCU_RDYr;
//--------------
assign SNES_DATABUS_OE = msu_enable & ~(SNES_READ_narrow & SNES_WRITE) ? 1'b0 :
// cover open bus to write-only registers (6000/6002 and 7XXX are the exceptions)
sgb_enable & (~SNES_WRITE | (SNES_ADDR[12] | ~|{SNES_ADDR[3:2],SNES_ADDR[0]})) ? 1'b0 :
snescmd_enable & ~(SNES_READ_narrow & SNES_WRITE) ? ~(snescmd_unlock | feat_cmd_unlock) :
(r213f_enable & ~SNES_PARD) ? 1'b0 :
(r2100_enable & ~SNES_PAWR) ? 1'b0 :
snoop_4200_enable & ~SNES_WRITE ? 1'b0 :
button_enable & ~SNES_WRITE ? 1'b0 :
( (IS_ROM & SNES_ROMSEL)
| (!IS_ROM & !IS_SAVERAM & !IS_WRITABLE)
| (SNES_READ_narrow & SNES_WRITE)
);
/* data bus direction: 0 = SNES -> FPGA; 1 = FPGA -> SNES
* data bus is always SNES -> FPGA to avoid fighting except when:
* a) the SNES wants to read
* b) we want to force a value on the bus
*/
assign SNES_DATABUS_DIR = (~SNES_READ | (~SNES_PARD & (r213f_enable)))
? (1'b1 ^ (r213f_forceread & r213f_enable & ~SNES_PARD)
^ (r2100_enable & ~SNES_PAWR & ~r2100_forcewrite & ~IS_ROM & ~IS_WRITABLE & ~sgb_enable))
: ((~SNES_PAWR & r2100_enable) ? r2100_forcewrite
: 1'b0);
assign SNES_IRQ = 1'b0;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NAND3_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__NAND3_FUNCTIONAL_PP_V
/**
* nand3: 3-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__nand3 (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y , B, A, C );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NAND3_FUNCTIONAL_PP_V |
/*
* NAME
*
* cpu_tb.v - generic cpu test bench
*
* DESCRIPTION
*
* This generic cpu test bench can be used to run a program, which is in
* ASCII hex format, and output the results.
*
* Configuration is done by setting preprocessor defines at compile
* time. The result is an executable for that specific test.
*
* iverilog -DIM_DATA_FILE="\"t0001-no_hazard.hex\"" \
* -DNUM_IM_DATA=`wc -l t0001-no_hazard.hex | awk {'print $$1'}` \
* -DDUMP_FILE="\"t0001-no_hazard.vcd\"" \
* -I../ -g2005 \
* -o t0001-no_hazard \
* cpu_tb.v
*
* Then it can be run in the usual manner. $monitor variables will be
* output to STDOUT and a .vcd for use with Gtkwave will be output to
* 'DUMP_FILE'.
*
* ./t0001-no_hazard > t0001-no_hazard.out
*/
//`include "cpu.v"
module cpu_tb;
integer i = 0;
reg clk;
cpu #(.NMEM(12))
mips1(.clk(clk));
always begin
clk <= ~clk;
#5;
end
initial begin
// $dumpfile(`DUMP_FILE);
// $dumpvars(0, cpu_tb);
clk <= 1'b0;
/* cpu will $display output when `DEBUG_CPU_STAGES is on */
// Run all the lines, plus 5 extra to finish off the pipeline.
for (i = 0; i < 12 + 5; i = i + 1) begin
@(posedge clk);
end
$finish;
end
endmodule
|
/*
* Copyright (c) 2000 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This sample tests that the supply0 and supply1 nets take on
* the proper initial value.
*/
module test;
supply0 gnd;
supply1 vdd;
initial begin
#1;
if (gnd !== 0) begin
$display("FAILED -- gnd == %b", gnd);
$finish;
end
if (vdd !== 1) begin
$display("FAILED -- vdd == %b", vdd);
$finish;
end
$display("PASSED");
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O41AI_4_V
`define SKY130_FD_SC_MS__O41AI_4_V
/**
* o41ai: 4-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3 | A4) & B1)
*
* Verilog wrapper for o41ai with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o41ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o41ai_4 (
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__o41ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o41ai_4 (
Y ,
A1,
A2,
A3,
A4,
B1
);
output Y ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__o41ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__O41AI_4_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__FAHCON_1_V
`define SKY130_FD_SC_HS__FAHCON_1_V
/**
* fahcon: Full adder, inverted carry in, inverted carry out.
*
* Verilog wrapper for fahcon with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__fahcon.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__fahcon_1 (
COUT_N,
SUM ,
A ,
B ,
CI ,
VPWR ,
VGND
);
output COUT_N;
output SUM ;
input A ;
input B ;
input CI ;
input VPWR ;
input VGND ;
sky130_fd_sc_hs__fahcon base (
.COUT_N(COUT_N),
.SUM(SUM),
.A(A),
.B(B),
.CI(CI),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__fahcon_1 (
COUT_N,
SUM ,
A ,
B ,
CI
);
output COUT_N;
output SUM ;
input A ;
input B ;
input CI ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__fahcon base (
.COUT_N(COUT_N),
.SUM(SUM),
.A(A),
.B(B),
.CI(CI)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__FAHCON_1_V
|
//////////////////////////////////////////////////////////////////////
//// ////
//// raminfr.v ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// Inferrable Distributed RAM for FIFOs ////
//// ////
//// Known problems (limits): ////
//// None . ////
//// ////
//// To Do: ////
//// Nothing so far. ////
//// ////
//// Author(s): ////
//// - [email protected] ////
//// - Jacob Gorban ////
//// ////
//// Created: 2002/07/22 ////
//// Last Updated: 2002/07/22 ////
//// (See log for the revision history) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000, 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2002/07/22 23:02:23 gorban
// Bug Fixes:
// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
// Problem reported by Kenny.Tung.
// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
//
// Improvements:
// * Made FIFO's as general inferrable memory where possible.
// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
//
// * Added optional baudrate output (baud_o).
// This is identical to BAUDOUT* signal on 16550 chip.
// It outputs 16xbit_clock_rate - the divided clock.
// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
//
//Following is the Verilog code for a dual-port RAM with asynchronous read.
module raminfr
(clk, we, a, dpra, di, dpo);
parameter addr_width = 4;
parameter data_width = 8;
parameter depth = 16;
input clk;
input we;
input [addr_width-1:0] a;
input [addr_width-1:0] dpra;
input [data_width-1:0] di;
//output [data_width-1:0] spo;
output [data_width-1:0] dpo;
reg [data_width-1:0] ram [depth-1:0];
wire [data_width-1:0] dpo;
wire [data_width-1:0] di;
wire [addr_width-1:0] a;
wire [addr_width-1:0] dpra;
always @(posedge clk) begin
if (we)
ram[a] <= di;
end
// assign spo = ram[a];
assign dpo = ram[dpra];
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DIODE_2_V
`define SKY130_FD_SC_HVL__DIODE_2_V
/**
* diode: Antenna tie-down diode.
*
* Verilog wrapper for diode with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__diode.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__diode_2 (
DIODE,
VPWR ,
VGND ,
VPB ,
VNB
);
input DIODE;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__diode base (
.DIODE(DIODE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__diode_2 (
DIODE
);
input DIODE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__diode base (
.DIODE(DIODE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DIODE_2_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Fri Jan 13 17:31:20 2017
// Host : KLight-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// D:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/pikachu_down_pixel/pikachu_down_pixel_sim_netlist.v
// Design : pikachu_down_pixel
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "pikachu_down_pixel,blk_mem_gen_v8_3_5,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "blk_mem_gen_v8_3_5,Vivado 2016.4" *)
(* NotValidForBitStream *)
module pikachu_down_pixel
(clka,
wea,
addra,
dina,
douta);
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) input clka;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *) input [0:0]wea;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *) input [12:0]addra;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *) input [11:0]dina;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *) output [11:0]douta;
wire [12:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
wire NLW_U0_dbiterr_UNCONNECTED;
wire NLW_U0_rsta_busy_UNCONNECTED;
wire NLW_U0_rstb_busy_UNCONNECTED;
wire NLW_U0_s_axi_arready_UNCONNECTED;
wire NLW_U0_s_axi_awready_UNCONNECTED;
wire NLW_U0_s_axi_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_dbiterr_UNCONNECTED;
wire NLW_U0_s_axi_rlast_UNCONNECTED;
wire NLW_U0_s_axi_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_sbiterr_UNCONNECTED;
wire NLW_U0_s_axi_wready_UNCONNECTED;
wire NLW_U0_sbiterr_UNCONNECTED;
wire [11:0]NLW_U0_doutb_UNCONNECTED;
wire [12:0]NLW_U0_rdaddrecc_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_bid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
wire [12:0]NLW_U0_s_axi_rdaddrecc_UNCONNECTED;
wire [11:0]NLW_U0_s_axi_rdata_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_rid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
(* C_ADDRA_WIDTH = "13" *)
(* C_ADDRB_WIDTH = "13" *)
(* C_ALGORITHM = "1" *)
(* C_AXI_ID_WIDTH = "4" *)
(* C_AXI_SLAVE_TYPE = "0" *)
(* C_AXI_TYPE = "1" *)
(* C_BYTE_SIZE = "9" *)
(* C_COMMON_CLK = "0" *)
(* C_COUNT_18K_BRAM = "1" *)
(* C_COUNT_36K_BRAM = "2" *)
(* C_CTRL_ECC_ALGO = "NONE" *)
(* C_DEFAULT_DATA = "0" *)
(* C_DISABLE_WARN_BHV_COLL = "0" *)
(* C_DISABLE_WARN_BHV_RANGE = "0" *)
(* C_ELABORATION_DIR = "./" *)
(* C_ENABLE_32BIT_ADDRESS = "0" *)
(* C_EN_DEEPSLEEP_PIN = "0" *)
(* C_EN_ECC_PIPE = "0" *)
(* C_EN_RDADDRA_CHG = "0" *)
(* C_EN_RDADDRB_CHG = "0" *)
(* C_EN_SAFETY_CKT = "0" *)
(* C_EN_SHUTDOWN_PIN = "0" *)
(* C_EN_SLEEP_PIN = "0" *)
(* C_EST_POWER_SUMMARY = "Estimated Power for IP : 4.681258 mW" *)
(* C_FAMILY = "artix7" *)
(* C_HAS_AXI_ID = "0" *)
(* C_HAS_ENA = "0" *)
(* C_HAS_ENB = "0" *)
(* C_HAS_INJECTERR = "0" *)
(* C_HAS_MEM_OUTPUT_REGS_A = "1" *)
(* C_HAS_MEM_OUTPUT_REGS_B = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_A = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
(* C_HAS_REGCEA = "0" *)
(* C_HAS_REGCEB = "0" *)
(* C_HAS_RSTA = "0" *)
(* C_HAS_RSTB = "0" *)
(* C_HAS_SOFTECC_INPUT_REGS_A = "0" *)
(* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
(* C_INITA_VAL = "0" *)
(* C_INITB_VAL = "0" *)
(* C_INIT_FILE = "pikachu_down_pixel.mem" *)
(* C_INIT_FILE_NAME = "pikachu_down_pixel.mif" *)
(* C_INTERFACE_TYPE = "0" *)
(* C_LOAD_INIT_FILE = "1" *)
(* C_MEM_TYPE = "0" *)
(* C_MUX_PIPELINE_STAGES = "0" *)
(* C_PRIM_TYPE = "1" *)
(* C_READ_DEPTH_A = "5589" *)
(* C_READ_DEPTH_B = "5589" *)
(* C_READ_WIDTH_A = "12" *)
(* C_READ_WIDTH_B = "12" *)
(* C_RSTRAM_A = "0" *)
(* C_RSTRAM_B = "0" *)
(* C_RST_PRIORITY_A = "CE" *)
(* C_RST_PRIORITY_B = "CE" *)
(* C_SIM_COLLISION_CHECK = "ALL" *)
(* C_USE_BRAM_BLOCK = "0" *)
(* C_USE_BYTE_WEA = "0" *)
(* C_USE_BYTE_WEB = "0" *)
(* C_USE_DEFAULT_DATA = "0" *)
(* C_USE_ECC = "0" *)
(* C_USE_SOFTECC = "0" *)
(* C_USE_URAM = "0" *)
(* C_WEA_WIDTH = "1" *)
(* C_WEB_WIDTH = "1" *)
(* C_WRITE_DEPTH_A = "5589" *)
(* C_WRITE_DEPTH_B = "5589" *)
(* C_WRITE_MODE_A = "WRITE_FIRST" *)
(* C_WRITE_MODE_B = "WRITE_FIRST" *)
(* C_WRITE_WIDTH_A = "12" *)
(* C_WRITE_WIDTH_B = "12" *)
(* C_XDEVICEFAMILY = "artix7" *)
(* downgradeipidentifiedwarnings = "yes" *)
pikachu_down_pixel_blk_mem_gen_v8_3_5 U0
(.addra(addra),
.addrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.clka(clka),
.clkb(1'b0),
.dbiterr(NLW_U0_dbiterr_UNCONNECTED),
.deepsleep(1'b0),
.dina(dina),
.dinb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.douta(douta),
.doutb(NLW_U0_doutb_UNCONNECTED[11:0]),
.eccpipece(1'b0),
.ena(1'b0),
.enb(1'b0),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.rdaddrecc(NLW_U0_rdaddrecc_UNCONNECTED[12:0]),
.regcea(1'b0),
.regceb(1'b0),
.rsta(1'b0),
.rsta_busy(NLW_U0_rsta_busy_UNCONNECTED),
.rstb(1'b0),
.rstb_busy(NLW_U0_rstb_busy_UNCONNECTED),
.s_aclk(1'b0),
.s_aresetn(1'b0),
.s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arburst({1'b0,1'b0}),
.s_axi_arid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
.s_axi_arsize({1'b0,1'b0,1'b0}),
.s_axi_arvalid(1'b0),
.s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awburst({1'b0,1'b0}),
.s_axi_awid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
.s_axi_awsize({1'b0,1'b0,1'b0}),
.s_axi_awvalid(1'b0),
.s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[3:0]),
.s_axi_bready(1'b0),
.s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
.s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
.s_axi_dbiterr(NLW_U0_s_axi_dbiterr_UNCONNECTED),
.s_axi_injectdbiterr(1'b0),
.s_axi_injectsbiterr(1'b0),
.s_axi_rdaddrecc(NLW_U0_s_axi_rdaddrecc_UNCONNECTED[12:0]),
.s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[11:0]),
.s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[3:0]),
.s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
.s_axi_rready(1'b0),
.s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
.s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
.s_axi_sbiterr(NLW_U0_s_axi_sbiterr_UNCONNECTED),
.s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wlast(1'b0),
.s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
.s_axi_wstrb(1'b0),
.s_axi_wvalid(1'b0),
.sbiterr(NLW_U0_sbiterr_UNCONNECTED),
.shutdown(1'b0),
.sleep(1'b0),
.wea(wea),
.web(1'b0));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *)
module pikachu_down_pixel_blk_mem_gen_generic_cstr
(douta,
addra,
clka,
dina,
wea);
output [11:0]douta;
input [12:0]addra;
input clka;
input [11:0]dina;
input [0:0]wea;
wire [12:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [8:0]p_7_out;
wire [8:0]ram_douta;
wire [0:0]wea;
pikachu_down_pixel_blk_mem_gen_mux \has_mux_a.A
(.addra(addra[12:11]),
.clka(clka),
.douta(douta[8:0]),
.p_7_out(p_7_out),
.ram_douta(ram_douta));
pikachu_down_pixel_blk_mem_gen_prim_width \ramloop[0].ram.r
(.addra(addra),
.clka(clka),
.dina(dina[8:0]),
.ram_douta(ram_douta),
.wea(wea));
pikachu_down_pixel_blk_mem_gen_prim_width__parameterized0 \ramloop[1].ram.r
(.addra(addra),
.clka(clka),
.dina(dina[8:0]),
.p_7_out(p_7_out),
.wea(wea));
pikachu_down_pixel_blk_mem_gen_prim_width__parameterized1 \ramloop[2].ram.r
(.addra(addra),
.clka(clka),
.dina(dina[11:9]),
.douta(douta[11:9]),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_mux" *)
module pikachu_down_pixel_blk_mem_gen_mux
(douta,
addra,
clka,
p_7_out,
ram_douta);
output [8:0]douta;
input [1:0]addra;
input clka;
input [8:0]p_7_out;
input [8:0]ram_douta;
wire [1:0]addra;
wire clka;
wire [8:0]douta;
wire [8:0]p_7_out;
wire [8:0]ram_douta;
wire [1:0]sel_pipe;
wire [1:0]sel_pipe_d1;
LUT4 #(
.INIT(16'h2F20))
\douta[0]_INST_0
(.I0(p_7_out[0]),
.I1(sel_pipe_d1[0]),
.I2(sel_pipe_d1[1]),
.I3(ram_douta[0]),
.O(douta[0]));
LUT4 #(
.INIT(16'h2F20))
\douta[1]_INST_0
(.I0(p_7_out[1]),
.I1(sel_pipe_d1[0]),
.I2(sel_pipe_d1[1]),
.I3(ram_douta[1]),
.O(douta[1]));
LUT4 #(
.INIT(16'h2F20))
\douta[2]_INST_0
(.I0(p_7_out[2]),
.I1(sel_pipe_d1[0]),
.I2(sel_pipe_d1[1]),
.I3(ram_douta[2]),
.O(douta[2]));
LUT4 #(
.INIT(16'h2F20))
\douta[3]_INST_0
(.I0(p_7_out[3]),
.I1(sel_pipe_d1[0]),
.I2(sel_pipe_d1[1]),
.I3(ram_douta[3]),
.O(douta[3]));
LUT4 #(
.INIT(16'h2F20))
\douta[4]_INST_0
(.I0(p_7_out[4]),
.I1(sel_pipe_d1[0]),
.I2(sel_pipe_d1[1]),
.I3(ram_douta[4]),
.O(douta[4]));
LUT4 #(
.INIT(16'h2F20))
\douta[5]_INST_0
(.I0(p_7_out[5]),
.I1(sel_pipe_d1[0]),
.I2(sel_pipe_d1[1]),
.I3(ram_douta[5]),
.O(douta[5]));
LUT4 #(
.INIT(16'h2F20))
\douta[6]_INST_0
(.I0(p_7_out[6]),
.I1(sel_pipe_d1[0]),
.I2(sel_pipe_d1[1]),
.I3(ram_douta[6]),
.O(douta[6]));
LUT4 #(
.INIT(16'h2F20))
\douta[7]_INST_0
(.I0(p_7_out[7]),
.I1(sel_pipe_d1[0]),
.I2(sel_pipe_d1[1]),
.I3(ram_douta[7]),
.O(douta[7]));
LUT4 #(
.INIT(16'h2F20))
\douta[8]_INST_0
(.I0(p_7_out[8]),
.I1(sel_pipe_d1[0]),
.I2(sel_pipe_d1[1]),
.I3(ram_douta[8]),
.O(douta[8]));
FDRE #(
.INIT(1'b0))
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[0]
(.C(clka),
.CE(1'b1),
.D(sel_pipe[0]),
.Q(sel_pipe_d1[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[1]
(.C(clka),
.CE(1'b1),
.D(sel_pipe[1]),
.Q(sel_pipe_d1[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]
(.C(clka),
.CE(1'b1),
.D(addra[0]),
.Q(sel_pipe[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[1]
(.C(clka),
.CE(1'b1),
.D(addra[1]),
.Q(sel_pipe[1]),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module pikachu_down_pixel_blk_mem_gen_prim_width
(ram_douta,
clka,
addra,
dina,
wea);
output [8:0]ram_douta;
input clka;
input [12:0]addra;
input [8:0]dina;
input [0:0]wea;
wire [12:0]addra;
wire clka;
wire [8:0]dina;
wire [8:0]ram_douta;
wire [0:0]wea;
pikachu_down_pixel_blk_mem_gen_prim_wrapper_init \prim_init.ram
(.addra(addra),
.clka(clka),
.dina(dina),
.ram_douta(ram_douta),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module pikachu_down_pixel_blk_mem_gen_prim_width__parameterized0
(p_7_out,
clka,
addra,
dina,
wea);
output [8:0]p_7_out;
input clka;
input [12:0]addra;
input [8:0]dina;
input [0:0]wea;
wire [12:0]addra;
wire clka;
wire [8:0]dina;
wire [8:0]p_7_out;
wire [0:0]wea;
pikachu_down_pixel_blk_mem_gen_prim_wrapper_init__parameterized0 \prim_init.ram
(.addra(addra),
.clka(clka),
.dina(dina),
.p_7_out(p_7_out),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module pikachu_down_pixel_blk_mem_gen_prim_width__parameterized1
(douta,
clka,
addra,
dina,
wea);
output [2:0]douta;
input clka;
input [12:0]addra;
input [2:0]dina;
input [0:0]wea;
wire [12:0]addra;
wire clka;
wire [2:0]dina;
wire [2:0]douta;
wire [0:0]wea;
pikachu_down_pixel_blk_mem_gen_prim_wrapper_init__parameterized1 \prim_init.ram
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module pikachu_down_pixel_blk_mem_gen_prim_wrapper_init
(ram_douta,
clka,
addra,
dina,
wea);
output [8:0]ram_douta;
input clka;
input [12:0]addra;
input [8:0]dina;
input [0:0]wea;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1_n_0 ;
wire [12:0]addra;
wire clka;
wire [8:0]dina;
wire [8:0]ram_douta;
wire [0:0]wea;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000380000000000000000000400000000000000000000000000),
.INITP_01(256'h0000000000000000003F0000000000000000003F8000000000000000000FA000),
.INITP_02(256'hFFE000000000000000001FE0000000000000000007F8000000000000000000FA),
.INITP_03(256'h1FFFF8000000000000000E0FF8000000000000000305FC000000000000000200),
.INITP_04(256'h0001FFFE0000000000000001FFFFC000000000000000FFFFD000000000000000),
.INITP_05(256'h000000821E00000000000000004E81E00000000000000011BF6C000000000000),
.INITP_06(256'h000000005A023FFC0FF8000000001881BFFE0000000000000030F87000000000),
.INITP_07(256'hFFFF00000023002C777FFFFC00000007801E3F83FFF9000000009C043FFBDFFC),
.INITP_08(256'hFFFFFD3A0010C1800FFFFFFFFD7E0000009007C01FFFFFFC0000001000E00FFF),
.INITP_09(256'hD3FFFFFFE4E8000E077FFBFFFFFFF07800830B0F95FFFFFFFC38001F8FFDFDFF),
.INITP_0A(256'hFBFF47FFFFFFE7F03FFFFD99B3FFFFFFE3FC07EFFDFFF9FFFFFF83F603EBFFFE),
.INITP_0B(256'hFFFFF3FEFFFFFFFFFF8FFFFFFFE71FFFFFFFFFC1FFFFF7FECFFFFFFFDFE0FFFF),
.INITP_0C(256'hF807FFFFFFEFFFFFFFFFFA79FFFFFFF7FFFFFFFFFF1CFFFFEFFBFFFFFFFFFF1E),
.INITP_0D(256'hFFFC803FFFFFFF8FFFFFFFFF001FFFFFFF8FFFFFFFFFE00FFFFFFFFFFFFFFFFF),
.INITP_0E(256'hFFFFFFF001FFFFFFFFBFFFFFFFFA00FFFFFFFE7FFFFFFFFE007FFFFFFF9FFFFF),
.INITP_0F(256'hFFFFFFFFFC000FFFFFFFFFFFFFFFFF0007FFFFFFFFFFFFFFFFC003FFFFFFFFFF),
.INIT_00(256'hF0F0F00000000102F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_01(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_02(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_03(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F00000010080A0A0B02000F0F0F0F0F0F0F0F0),
.INIT_04(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_05(256'h60E0F0F0B02000F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_06(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F000406061),
.INIT_07(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_08(256'hF0F0F0F0F0F0F0F0F0F00120B0F0F0F0F0E0B000F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_09(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_0A(256'h9000F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_0B(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F00101D0F0F0F0F0F0),
.INIT_0C(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_0D(256'hF0F0F0F0F0F0F00000E0F0F0F0F0F09000F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_0E(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_0F(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_10(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0042280F0F0F0F0F0A05000),
.INIT_11(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_12(256'hF0F000012372F0F0F0F0F0F03000F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_13(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F000F0F0F0F0F0F0),
.INIT_14(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_15(256'hF0F0F0F0F0F0F00000F0F0F0F0F0F0F000000190F0F0F0F0F0F0F04000F0F0F0),
.INIT_16(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_17(256'hD0D0F0F0F0F0F0F0F03010F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_18(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F00251C00102F0F0F0F00020),
.INIT_19(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_1A(256'hF0F0F00060C0F090200000000150A0F0F0F0F0F0F0F0C06000F0F0F0F0F0F0F0),
.INIT_1B(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
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.IS_ENARDEN_INVERTED(1'b0),
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\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra[11:0],1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
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.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
LUT1 #(
.INIT(2'h1))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1
(.I0(addra[12]),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1_n_0 ));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module pikachu_down_pixel_blk_mem_gen_prim_wrapper_init__parameterized0
(p_7_out,
clka,
addra,
dina,
wea);
output [8:0]p_7_out;
input clka;
input [12:0]addra;
input [8:0]dina;
input [0:0]wea;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_i_1_n_0 ;
wire [12:0]addra;
wire clka;
wire [8:0]dina;
wire [8:0]p_7_out;
wire [0:0]wea;
wire [15:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED ;
wire [15:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED ;
wire [1:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED ;
wire [1:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB18E1 #(
.DOA_REG(1),
.DOB_REG(0),
.INITP_00(256'hFFFFFFFFFFFE80005FFFFFFFFFFFFFFF88003FFFFFFFFFFFFFFFF8001FFFFFFF),
.INITP_01(256'hFFFFFFFFF0FFFF8000013FFFFFFFFCFFFFE00000FFFFFFFFFBFFFFF800003FFF),
.INITP_02(256'h00001FFFFFFFFFBFE84000006FFFFFFFFF1FFD000000BFFFFFFFE1FFFE800001),
.INITP_03(256'h020000000FFFFF03FF4F3F0000001FFFFFFFFEA7FF8000001FFFFFFFFF0F8F80),
.INITP_04(256'h20E200000000001FFF902FF80000000001FFFFF81FE00000000008FFFF040FE0),
.INITP_05(256'h0000000000000000000000000000000000000000000001E40000000000100000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'hF0F00070F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_01(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F02000F0F0F0F0F0F0F0F0F0),
.INIT_02(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_03(256'hF0A0202010F0F0F0F0F0F0F0F0F0F0F0F00070F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_04(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_05(256'hF01040F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_06(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F080300000F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_07(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_08(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F00020F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_09(256'hF0F0F0F0F0C0B0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0A02000),
.INIT_0A(256'h30F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_0B(256'hF0F0F0F0F0F0F0F0F0F0F0C00000F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F000),
.INIT_0C(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F05030E0E0F0F0F0F0F0F0F0F0),
.INIT_0D(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F00030E0E0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_0E(256'hF0F0F0F0A00000A0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0A000F0F0F0F0F0),
.INIT_0F(256'h1090F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_10(256'hF0F0F0F0F0F0F0801000F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F00010),
.INIT_11(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0E0A0A0603050F0F0F0F0F0F0F0),
.INIT_12(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F000003080F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_13(256'hF0F0F0F0F09050508080C0F0F0F0F0F0F0F0F0F0F09060300000F0F0F0F0F0F0),
.INIT_14(256'h209090E0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_15(256'hF0F0F0C010C0C0202010F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F000),
.INIT_16(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0101060D0D0F0F0F0F0),
.INIT_17(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F000000080D0D0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_18(256'hF0F0F0F0F0F0F0F0800000C0F0F0F0F0F0A000E0F0F0F0F03000F0F0F0F0F0F0),
.INIT_19(256'hF0000010F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_1A(256'h50D0F0F0F0F0F0D07000F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_1B(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0E09000102060F0F070),
.INIT_1C(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F00000303090F0F0F0F0F0F0F0F0F0F0),
.INIT_1D(256'hF0F0F0F0F0F0F0F08070200070701010808070B0F0F0F09000F0F0F0F0F0F0F0),
.INIT_1E(256'hF0F000003090F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F080606060606090F0),
.INIT_1F(256'h000040C0C0C07000F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_20(256'hF0F0F0F0F0F0F050202020202050C0C0C0C0C0C0F0F0F0F0F090302000000000),
.INIT_21(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F00010C0C0C0D0F0F0F0F0F0F0F0),
.INIT_22(256'h000000B0F0F0F0F0F0F0F0200000F0F0F00000000000F0F0F0F0F0F0F0F0F0F0),
.INIT_23(256'hF0F0F0F000000030F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0B0000000),
.INIT_24(256'hF0F0F00000F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_25(256'hF0F0F0F0F0F0F0F0F04020100000000000001080F0F0F0F0F0F0D0D090000000),
.INIT_26(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0000000002020202030F0F0F0F0),
.INIT_27(256'h0000306060606080F0F0F0C0000000F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_28(256'hF0F0F0F0F0F0000000000050606060606060606060606060000000F0F0F000F0),
.INIT_29(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_2A(256'h00000000000000F00000F0F0F0F0F0F0F0000000000020B0B0B070000000F0F0),
.INIT_2B(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0000000000000),
.INIT_2C(256'hF0F0F0F0F0000000000000F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_2D(256'hF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_2E(256'h0000000000000000000000F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(18'h00000),
.INIT_B(18'h00000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(18'h00000),
.SRVAL_B(18'h00000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram
(.ADDRARDADDR({addra[10:0],1'b0,1'b0,1'b0}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,dina[8]}),
.DIPBDIP({1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED [15:8],p_7_out[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED [15:0]),
.DOPADOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED [1],p_7_out[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED [1:0]),
.ENARDEN(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_i_1_n_0 ),
.ENBWREN(1'b0),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.WEA({wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0}));
LUT2 #(
.INIT(4'h2))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_i_1
(.I0(addra[12]),
.I1(addra[11]),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_i_1_n_0 ));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module pikachu_down_pixel_blk_mem_gen_prim_wrapper_init__parameterized1
(douta,
clka,
addra,
dina,
wea);
output [2:0]douta;
input clka;
input [12:0]addra;
input [2:0]dina;
input [0:0]wea;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_49 ;
wire [12:0]addra;
wire clka;
wire [2:0]dina;
wire [2:0]douta;
wire [0:0]wea;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:4]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h2222222222222222222222222222222222200000222222222222222222222222),
.INIT_01(256'h2222222222222200004555102222222222222222222222222222222222222222),
.INIT_02(256'h3777510222222222222222222222222222222222222222222222222222222222),
.INIT_03(256'h2222222222222222222222222222222222222222222222222222222222220233),
.INIT_04(256'h2222222222222222222222222222222222222222220157777750222222222222),
.INIT_05(256'h2222222222222222222222220067777740222222222222222222222222222222),
.INIT_06(256'h2222222007777774022222222222222222222222222222222222222222222222),
.INIT_07(256'h2222222222222222222222222222222222222222222222222222222222222222),
.INIT_08(256'h2222222222222222222222222222222222222222222222222222201477777520),
.INIT_09(256'h2222222222222222222222222022222222001377777710222222222222222222),
.INIT_0A(256'h2222222002222222000477777772022222222222222222222222222222222222),
.INIT_0B(256'h6677777771022222222222222222222222222222222222222222222222222222),
.INIT_0C(256'h2222222222222222222222222222222222222222222222222222202600222201),
.INIT_0D(256'h2222222222222222222222222222222222203674100002577777776302222222),
.INIT_0E(256'h2222222222222222220577742222577777777502222222222222222222222222),
.INIT_0F(256'h2057777777777777777740222222222222222222222222222222222222222222),
.INIT_10(256'h7730222222222222222222222222222222222222222222222222222222222222),
.INIT_11(256'h2222222222222222222222222222222222222222222222006777777777777777),
.INIT_12(256'h2222222222222222222222222222000777777777777777777202222222222222),
.INIT_13(256'h2222222222000267777777777777777520222222222222222222222222222222),
.INIT_14(256'h7766666677776600222222222222222222222222222222222222222222222222),
.INIT_15(256'h2222222222222222222222222222222222222222222222222222222220015577),
.INIT_16(256'h2222222222222222222222222222222222222220025577770000000177300222),
.INIT_17(256'h2222222222222222222222034556321000055541100000222222222222222222),
.INIT_18(256'h2200004555400000147777333333100022222000000000022222222222222222),
.INIT_19(256'h6677777777731111000011111111110022222222222222222222222222222222),
.INIT_1A(256'h0004777777774000222222222222222222222222222222222000045542200013),
.INIT_1B(256'h0222222222222222222222222222222001444542220006400677777777777720),
.INIT_1C(256'h2222222222222203455100222200676614777777775000266677777777776610),
.INIT_1D(256'h4200020000015775347776222344467777777777777775430222222222222222),
.INIT_1E(256'h0555411147777777777777777777777202222222222222222222222222200245),
.INIT_1F(256'h7777777777777771022222222222222222222222200255420000000002135562),
.INIT_20(256'h0222222222222222222222220254520022000001774000000002777777777777),
.INIT_21(256'h0022222015510022222002777777777777777777777777777777777777777773),
.INIT_22(256'h0000037777777777777777777777777777777762267777302222222222222000),
.INIT_23(256'h7777777777777777777774024677752022222222220055554002202441000000),
.INIT_24(256'h7777407237777602222222220247777700201442211111002111147777777777),
.INIT_25(256'h2222222037777770000442176555512755540477777777777777777777777777),
.INIT_26(256'h0000377764444577544403777777777777777777777777777774006417775022),
.INIT_27(256'h4455327777777777777777777777777777400111777750002222200000002700),
.INIT_28(256'h7777777777777777763000177777432022220455555415555556777644445776),
.INIT_29(256'h7710017777777502220377777763777777777764444577544475247777777777),
.INIT_2A(256'h0277777777777777777776544567765447760677777777777777777777777777),
.INIT_2B(256'h7777774467777644776067777777777777777777777777777710177777775022),
.INIT_2C(256'h7606777777777777777777777777777776667777777502037777777777777777),
.INIT_2D(256'h7777777777777777777777777750047777777777777777777777744677776447),
.INIT_2E(256'h7777777775005777777777777777777777776467777766753477777777777777),
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.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(4),
.READ_WIDTH_B(4),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(4),
.WRITE_WIDTH_B(4))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:4],\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_49 ,douta}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_top" *)
module pikachu_down_pixel_blk_mem_gen_top
(douta,
addra,
clka,
dina,
wea);
output [11:0]douta;
input [12:0]addra;
input clka;
input [11:0]dina;
input [0:0]wea;
wire [12:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
pikachu_down_pixel_blk_mem_gen_generic_cstr \valid.cstr
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule
(* C_ADDRA_WIDTH = "13" *) (* C_ADDRB_WIDTH = "13" *) (* C_ALGORITHM = "1" *)
(* C_AXI_ID_WIDTH = "4" *) (* C_AXI_SLAVE_TYPE = "0" *) (* C_AXI_TYPE = "1" *)
(* C_BYTE_SIZE = "9" *) (* C_COMMON_CLK = "0" *) (* C_COUNT_18K_BRAM = "1" *)
(* C_COUNT_36K_BRAM = "2" *) (* C_CTRL_ECC_ALGO = "NONE" *) (* C_DEFAULT_DATA = "0" *)
(* C_DISABLE_WARN_BHV_COLL = "0" *) (* C_DISABLE_WARN_BHV_RANGE = "0" *) (* C_ELABORATION_DIR = "./" *)
(* C_ENABLE_32BIT_ADDRESS = "0" *) (* C_EN_DEEPSLEEP_PIN = "0" *) (* C_EN_ECC_PIPE = "0" *)
(* C_EN_RDADDRA_CHG = "0" *) (* C_EN_RDADDRB_CHG = "0" *) (* C_EN_SAFETY_CKT = "0" *)
(* C_EN_SHUTDOWN_PIN = "0" *) (* C_EN_SLEEP_PIN = "0" *) (* C_EST_POWER_SUMMARY = "Estimated Power for IP : 4.681258 mW" *)
(* C_FAMILY = "artix7" *) (* C_HAS_AXI_ID = "0" *) (* C_HAS_ENA = "0" *)
(* C_HAS_ENB = "0" *) (* C_HAS_INJECTERR = "0" *) (* C_HAS_MEM_OUTPUT_REGS_A = "1" *)
(* C_HAS_MEM_OUTPUT_REGS_B = "0" *) (* C_HAS_MUX_OUTPUT_REGS_A = "0" *) (* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
(* C_HAS_REGCEA = "0" *) (* C_HAS_REGCEB = "0" *) (* C_HAS_RSTA = "0" *)
(* C_HAS_RSTB = "0" *) (* C_HAS_SOFTECC_INPUT_REGS_A = "0" *) (* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
(* C_INITA_VAL = "0" *) (* C_INITB_VAL = "0" *) (* C_INIT_FILE = "pikachu_down_pixel.mem" *)
(* C_INIT_FILE_NAME = "pikachu_down_pixel.mif" *) (* C_INTERFACE_TYPE = "0" *) (* C_LOAD_INIT_FILE = "1" *)
(* C_MEM_TYPE = "0" *) (* C_MUX_PIPELINE_STAGES = "0" *) (* C_PRIM_TYPE = "1" *)
(* C_READ_DEPTH_A = "5589" *) (* C_READ_DEPTH_B = "5589" *) (* C_READ_WIDTH_A = "12" *)
(* C_READ_WIDTH_B = "12" *) (* C_RSTRAM_A = "0" *) (* C_RSTRAM_B = "0" *)
(* C_RST_PRIORITY_A = "CE" *) (* C_RST_PRIORITY_B = "CE" *) (* C_SIM_COLLISION_CHECK = "ALL" *)
(* C_USE_BRAM_BLOCK = "0" *) (* C_USE_BYTE_WEA = "0" *) (* C_USE_BYTE_WEB = "0" *)
(* C_USE_DEFAULT_DATA = "0" *) (* C_USE_ECC = "0" *) (* C_USE_SOFTECC = "0" *)
(* C_USE_URAM = "0" *) (* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *)
(* C_WRITE_DEPTH_A = "5589" *) (* C_WRITE_DEPTH_B = "5589" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *)
(* C_WRITE_MODE_B = "WRITE_FIRST" *) (* C_WRITE_WIDTH_A = "12" *) (* C_WRITE_WIDTH_B = "12" *)
(* C_XDEVICEFAMILY = "artix7" *) (* ORIG_REF_NAME = "blk_mem_gen_v8_3_5" *) (* downgradeipidentifiedwarnings = "yes" *)
module pikachu_down_pixel_blk_mem_gen_v8_3_5
(clka,
rsta,
ena,
regcea,
wea,
addra,
dina,
douta,
clkb,
rstb,
enb,
regceb,
web,
addrb,
dinb,
doutb,
injectsbiterr,
injectdbiterr,
eccpipece,
sbiterr,
dbiterr,
rdaddrecc,
sleep,
deepsleep,
shutdown,
rsta_busy,
rstb_busy,
s_aclk,
s_aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
s_axi_injectsbiterr,
s_axi_injectdbiterr,
s_axi_sbiterr,
s_axi_dbiterr,
s_axi_rdaddrecc);
input clka;
input rsta;
input ena;
input regcea;
input [0:0]wea;
input [12:0]addra;
input [11:0]dina;
output [11:0]douta;
input clkb;
input rstb;
input enb;
input regceb;
input [0:0]web;
input [12:0]addrb;
input [11:0]dinb;
output [11:0]doutb;
input injectsbiterr;
input injectdbiterr;
input eccpipece;
output sbiterr;
output dbiterr;
output [12:0]rdaddrecc;
input sleep;
input deepsleep;
input shutdown;
output rsta_busy;
output rstb_busy;
input s_aclk;
input s_aresetn;
input [3:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input s_axi_awvalid;
output s_axi_awready;
input [11:0]s_axi_wdata;
input [0:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [3:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [3:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input s_axi_arvalid;
output s_axi_arready;
output [3:0]s_axi_rid;
output [11:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
input s_axi_injectsbiterr;
input s_axi_injectdbiterr;
output s_axi_sbiterr;
output s_axi_dbiterr;
output [12:0]s_axi_rdaddrecc;
wire \<const0> ;
wire [12:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
assign dbiterr = \<const0> ;
assign doutb[11] = \<const0> ;
assign doutb[10] = \<const0> ;
assign doutb[9] = \<const0> ;
assign doutb[8] = \<const0> ;
assign doutb[7] = \<const0> ;
assign doutb[6] = \<const0> ;
assign doutb[5] = \<const0> ;
assign doutb[4] = \<const0> ;
assign doutb[3] = \<const0> ;
assign doutb[2] = \<const0> ;
assign doutb[1] = \<const0> ;
assign doutb[0] = \<const0> ;
assign rdaddrecc[12] = \<const0> ;
assign rdaddrecc[11] = \<const0> ;
assign rdaddrecc[10] = \<const0> ;
assign rdaddrecc[9] = \<const0> ;
assign rdaddrecc[8] = \<const0> ;
assign rdaddrecc[7] = \<const0> ;
assign rdaddrecc[6] = \<const0> ;
assign rdaddrecc[5] = \<const0> ;
assign rdaddrecc[4] = \<const0> ;
assign rdaddrecc[3] = \<const0> ;
assign rdaddrecc[2] = \<const0> ;
assign rdaddrecc[1] = \<const0> ;
assign rdaddrecc[0] = \<const0> ;
assign rsta_busy = \<const0> ;
assign rstb_busy = \<const0> ;
assign s_axi_arready = \<const0> ;
assign s_axi_awready = \<const0> ;
assign s_axi_bid[3] = \<const0> ;
assign s_axi_bid[2] = \<const0> ;
assign s_axi_bid[1] = \<const0> ;
assign s_axi_bid[0] = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_bvalid = \<const0> ;
assign s_axi_dbiterr = \<const0> ;
assign s_axi_rdaddrecc[12] = \<const0> ;
assign s_axi_rdaddrecc[11] = \<const0> ;
assign s_axi_rdaddrecc[10] = \<const0> ;
assign s_axi_rdaddrecc[9] = \<const0> ;
assign s_axi_rdaddrecc[8] = \<const0> ;
assign s_axi_rdaddrecc[7] = \<const0> ;
assign s_axi_rdaddrecc[6] = \<const0> ;
assign s_axi_rdaddrecc[5] = \<const0> ;
assign s_axi_rdaddrecc[4] = \<const0> ;
assign s_axi_rdaddrecc[3] = \<const0> ;
assign s_axi_rdaddrecc[2] = \<const0> ;
assign s_axi_rdaddrecc[1] = \<const0> ;
assign s_axi_rdaddrecc[0] = \<const0> ;
assign s_axi_rdata[11] = \<const0> ;
assign s_axi_rdata[10] = \<const0> ;
assign s_axi_rdata[9] = \<const0> ;
assign s_axi_rdata[8] = \<const0> ;
assign s_axi_rdata[7] = \<const0> ;
assign s_axi_rdata[6] = \<const0> ;
assign s_axi_rdata[5] = \<const0> ;
assign s_axi_rdata[4] = \<const0> ;
assign s_axi_rdata[3] = \<const0> ;
assign s_axi_rdata[2] = \<const0> ;
assign s_axi_rdata[1] = \<const0> ;
assign s_axi_rdata[0] = \<const0> ;
assign s_axi_rid[3] = \<const0> ;
assign s_axi_rid[2] = \<const0> ;
assign s_axi_rid[1] = \<const0> ;
assign s_axi_rid[0] = \<const0> ;
assign s_axi_rlast = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
assign s_axi_rvalid = \<const0> ;
assign s_axi_sbiterr = \<const0> ;
assign s_axi_wready = \<const0> ;
assign sbiterr = \<const0> ;
GND GND
(.G(\<const0> ));
pikachu_down_pixel_blk_mem_gen_v8_3_5_synth inst_blk_mem_gen
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_3_5_synth" *)
module pikachu_down_pixel_blk_mem_gen_v8_3_5_synth
(douta,
addra,
clka,
dina,
wea);
output [11:0]douta;
input [12:0]addra;
input clka;
input [11:0]dina;
input [0:0]wea;
wire [12:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
pikachu_down_pixel_blk_mem_gen_top \gnbram.gnativebmg.native_blk_mem_gen
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
module register (clk, we, d, q);
input [31:0] d;
input clk;
input we;
output [31:0] q;
wire clk;
wire we;
wire [31:0] d;
reg [31:0] q;
always @ (posedge clk)
if (we) q <= d;
endmodule // register
module fibfast (clk, n, start, fibn, done);
input [31:0] n;
input clk;
input start;
output [31:0] fibn;
output done;
wire start;
wire [31:0] n;
wire clk;
reg [31:0] fibn;
reg [31:0] in_n;
reg done;
reg [2:0] state;
reg [2:0] nextstate;
reg [31:0] b;
reg [31:0] h;
reg [31:0] d;
reg [31:0] f;
wire [31:0] nextn;
wire [31:0] nextb;
wire [31:0] nexth;
wire [31:0] nextd;
wire [31:0] nextf;
assign nextn = in_n / 2;
assign nextb = (b * f) + (d * f) + (b * h);
assign nexth = (f * f) + (h * h);
assign nextd = (b * f) + (d * h);
assign nextf = (f * f) + (2 * f * h);
initial begin
done = 1;
state = 0;
in_n = n;
end
always @ (posedge clk)
state = nextstate;
always @ (posedge clk)
if (state == 0 && start) begin
nextstate = 1;
end else if (state == 1) begin
done = 0;
b = 0;
h = 0;
d = 1;
f = 1;
nextstate = 2;
end else if (state == 2) begin
if (n <= 0) begin
nextstate = 0;
fibn = b;
done = 1;
end else begin
nextstate = 3;
end
end else if (state == 3) begin
if (n & 1 == 1) begin
b = nextb;
d = nextd;
end
f = nextf;
h = nexth;
in_n = nextn;
nextstate = 2;
end
endmodule // fibfast
module testbench;
reg clk;
reg [31:0] n;
reg start;
wire [31:0] fibn;
wire done;
fibfast ff (clk, n, start, fibn, done);
initial begin
clk = 0;
n = 10;
start = 1;
$monitor($time,, "%b %d %b %d %b", clk, n, start, fibn, done);
#100 $finish();
end
always
#10 clk = ~clk;
endmodule // testbench
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Thu May 25 15:29:01 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// C:/ZyboIP/examples/zed_dual_camera_test/zed_dual_camera_test.srcs/sources_1/bd/system/ip/system_inverter_0_0/system_inverter_0_0_sim_netlist.v
// Design : system_inverter_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_inverter_0_0,inverter,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "inverter,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_inverter_0_0
(x,
x_not);
input x;
output x_not;
wire x;
wire x_not;
LUT1 #(
.INIT(2'h1))
x_not_INST_0
(.I0(x),
.O(x_not));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
// Date : Tue Sep 19 00:30:00 2017
// Host : DarkCube running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zynq_design_1_axi_bram_ctrl_0_1_sim_netlist.v
// Design : zynq_design_1_axi_bram_ctrl_0_1
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_SRL_FIFO
(E,
bid_gets_fifo_load,
bvalid_cnt_inc,
bid_gets_fifo_load_d1_reg,
D,
axi_wdata_full_cmb114_out,
SR,
s_axi_aclk,
\bvalid_cnt_reg[2] ,
wr_addr_sm_cs,
\bvalid_cnt_reg[2]_0 ,
\GEN_AWREADY.axi_aresetn_d2_reg ,
axi_awaddr_full,
bram_addr_ld_en,
bid_gets_fifo_load_d1,
s_axi_bready,
axi_bvalid_int_reg,
bvalid_cnt,
Q,
s_axi_awid,
\bvalid_cnt_reg[1] ,
aw_active,
s_axi_awready,
s_axi_awvalid,
curr_awlen_reg_1_or_2,
axi_awlen_pipe_1_or_2,
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg ,
last_data_ack_mod,
out,
axi_wr_burst,
s_axi_wvalid,
s_axi_wlast);
output [0:0]E;
output bid_gets_fifo_load;
output bvalid_cnt_inc;
output bid_gets_fifo_load_d1_reg;
output [11:0]D;
output axi_wdata_full_cmb114_out;
input [0:0]SR;
input s_axi_aclk;
input \bvalid_cnt_reg[2] ;
input wr_addr_sm_cs;
input \bvalid_cnt_reg[2]_0 ;
input \GEN_AWREADY.axi_aresetn_d2_reg ;
input axi_awaddr_full;
input bram_addr_ld_en;
input bid_gets_fifo_load_d1;
input s_axi_bready;
input axi_bvalid_int_reg;
input [2:0]bvalid_cnt;
input [11:0]Q;
input [11:0]s_axi_awid;
input \bvalid_cnt_reg[1] ;
input aw_active;
input s_axi_awready;
input s_axi_awvalid;
input curr_awlen_reg_1_or_2;
input axi_awlen_pipe_1_or_2;
input \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg ;
input last_data_ack_mod;
input [2:0]out;
input axi_wr_burst;
input s_axi_wvalid;
input s_axi_wlast;
wire \Addr_Counters[0].FDRE_I_n_0 ;
wire \Addr_Counters[1].FDRE_I_n_0 ;
wire \Addr_Counters[2].FDRE_I_n_0 ;
wire \Addr_Counters[3].FDRE_I_n_0 ;
wire \Addr_Counters[3].XORCY_I_i_1_n_0 ;
wire CI;
wire [11:0]D;
wire D_0;
wire Data_Exists_DFF_i_2_n_0;
wire Data_Exists_DFF_i_3_n_0;
wire [0:0]E;
wire \GEN_AWREADY.axi_aresetn_d2_reg ;
wire \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg ;
wire [11:0]Q;
wire S;
wire S0_out;
wire S1_out;
wire [0:0]SR;
wire addr_cy_1;
wire addr_cy_2;
wire addr_cy_3;
wire aw_active;
wire axi_awaddr_full;
wire axi_awlen_pipe_1_or_2;
wire \axi_bid_int[11]_i_3_n_0 ;
wire axi_bvalid_int_i_4_n_0;
wire axi_bvalid_int_i_5_n_0;
wire axi_bvalid_int_i_6_n_0;
wire axi_bvalid_int_reg;
wire axi_wdata_full_cmb114_out;
wire axi_wr_burst;
wire [11:0]bid_fifo_ld;
wire bid_fifo_not_empty;
wire [11:0]bid_fifo_rd;
wire bid_gets_fifo_load;
wire bid_gets_fifo_load_d1;
wire bid_gets_fifo_load_d1_i_3_n_0;
wire bid_gets_fifo_load_d1_reg;
wire bram_addr_ld_en;
wire [2:0]bvalid_cnt;
wire bvalid_cnt_inc;
wire \bvalid_cnt_reg[1] ;
wire \bvalid_cnt_reg[2] ;
wire \bvalid_cnt_reg[2]_0 ;
wire curr_awlen_reg_1_or_2;
wire last_data_ack_mod;
wire [2:0]out;
wire s_axi_aclk;
wire [11:0]s_axi_awid;
wire s_axi_awready;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_wlast;
wire s_axi_wvalid;
wire sum_A_0;
wire sum_A_1;
wire sum_A_2;
wire sum_A_3;
wire wr_addr_sm_cs;
wire [3:3]\NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_CO_UNCONNECTED ;
wire [3:3]\NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_DI_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\Addr_Counters[0].FDRE_I
(.C(s_axi_aclk),
.CE(bid_fifo_not_empty),
.D(sum_A_3),
.Q(\Addr_Counters[0].FDRE_I_n_0 ),
.R(SR));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* XILINX_TRANSFORM_PINMAP = "LO:O" *)
CARRY4 \Addr_Counters[0].MUXCY_L_I_CARRY4
(.CI(1'b0),
.CO({\NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_CO_UNCONNECTED [3],addr_cy_1,addr_cy_2,addr_cy_3}),
.CYINIT(CI),
.DI({\NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_DI_UNCONNECTED [3],\Addr_Counters[2].FDRE_I_n_0 ,\Addr_Counters[1].FDRE_I_n_0 ,\Addr_Counters[0].FDRE_I_n_0 }),
.O({sum_A_0,sum_A_1,sum_A_2,sum_A_3}),
.S({\Addr_Counters[3].XORCY_I_i_1_n_0 ,S0_out,S1_out,S}));
LUT6 #(
.INIT(64'h0000FFFFFFFE0000))
\Addr_Counters[0].MUXCY_L_I_i_1
(.I0(\Addr_Counters[1].FDRE_I_n_0 ),
.I1(\Addr_Counters[3].FDRE_I_n_0 ),
.I2(\Addr_Counters[2].FDRE_I_n_0 ),
.I3(bram_addr_ld_en),
.I4(\axi_bid_int[11]_i_3_n_0 ),
.I5(\Addr_Counters[0].FDRE_I_n_0 ),
.O(S));
LUT6 #(
.INIT(64'h8AAAAAAAAAAAAAAA))
\Addr_Counters[0].MUXCY_L_I_i_2
(.I0(bram_addr_ld_en),
.I1(\axi_bid_int[11]_i_3_n_0 ),
.I2(\Addr_Counters[0].FDRE_I_n_0 ),
.I3(\Addr_Counters[1].FDRE_I_n_0 ),
.I4(\Addr_Counters[3].FDRE_I_n_0 ),
.I5(\Addr_Counters[2].FDRE_I_n_0 ),
.O(CI));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\Addr_Counters[1].FDRE_I
(.C(s_axi_aclk),
.CE(bid_fifo_not_empty),
.D(sum_A_2),
.Q(\Addr_Counters[1].FDRE_I_n_0 ),
.R(SR));
LUT6 #(
.INIT(64'h0000FFFFFFFE0000))
\Addr_Counters[1].MUXCY_L_I_i_1
(.I0(\Addr_Counters[0].FDRE_I_n_0 ),
.I1(\Addr_Counters[3].FDRE_I_n_0 ),
.I2(\Addr_Counters[2].FDRE_I_n_0 ),
.I3(bram_addr_ld_en),
.I4(\axi_bid_int[11]_i_3_n_0 ),
.I5(\Addr_Counters[1].FDRE_I_n_0 ),
.O(S1_out));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\Addr_Counters[2].FDRE_I
(.C(s_axi_aclk),
.CE(bid_fifo_not_empty),
.D(sum_A_1),
.Q(\Addr_Counters[2].FDRE_I_n_0 ),
.R(SR));
LUT6 #(
.INIT(64'h0000FFFFFFFE0000))
\Addr_Counters[2].MUXCY_L_I_i_1
(.I0(\Addr_Counters[0].FDRE_I_n_0 ),
.I1(\Addr_Counters[1].FDRE_I_n_0 ),
.I2(\Addr_Counters[3].FDRE_I_n_0 ),
.I3(bram_addr_ld_en),
.I4(\axi_bid_int[11]_i_3_n_0 ),
.I5(\Addr_Counters[2].FDRE_I_n_0 ),
.O(S0_out));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\Addr_Counters[3].FDRE_I
(.C(s_axi_aclk),
.CE(bid_fifo_not_empty),
.D(sum_A_0),
.Q(\Addr_Counters[3].FDRE_I_n_0 ),
.R(SR));
LUT6 #(
.INIT(64'h0000FFFFFFFE0000))
\Addr_Counters[3].XORCY_I_i_1
(.I0(\Addr_Counters[0].FDRE_I_n_0 ),
.I1(\Addr_Counters[1].FDRE_I_n_0 ),
.I2(\Addr_Counters[2].FDRE_I_n_0 ),
.I3(bram_addr_ld_en),
.I4(\axi_bid_int[11]_i_3_n_0 ),
.I5(\Addr_Counters[3].FDRE_I_n_0 ),
.O(\Addr_Counters[3].XORCY_I_i_1_n_0 ));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
Data_Exists_DFF
(.C(s_axi_aclk),
.CE(1'b1),
.D(D_0),
.Q(bid_fifo_not_empty),
.R(SR));
LUT4 #(
.INIT(16'hFE0A))
Data_Exists_DFF_i_1
(.I0(bram_addr_ld_en),
.I1(Data_Exists_DFF_i_2_n_0),
.I2(Data_Exists_DFF_i_3_n_0),
.I3(bid_fifo_not_empty),
.O(D_0));
LUT6 #(
.INIT(64'h000000000000FFFD))
Data_Exists_DFF_i_2
(.I0(bvalid_cnt_inc),
.I1(bvalid_cnt[2]),
.I2(bvalid_cnt[0]),
.I3(bvalid_cnt[1]),
.I4(bid_gets_fifo_load_d1_reg),
.I5(bid_gets_fifo_load_d1),
.O(Data_Exists_DFF_i_2_n_0));
LUT4 #(
.INIT(16'hFFFE))
Data_Exists_DFF_i_3
(.I0(\Addr_Counters[0].FDRE_I_n_0 ),
.I1(\Addr_Counters[1].FDRE_I_n_0 ),
.I2(\Addr_Counters[3].FDRE_I_n_0 ),
.I3(\Addr_Counters[2].FDRE_I_n_0 ),
.O(Data_Exists_DFF_i_3_n_0));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_bus_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM " *)
(* srl_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[0].SRL16E_I " *)
SRL16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\FIFO_RAM[0].SRL16E_I
(.A0(\Addr_Counters[0].FDRE_I_n_0 ),
.A1(\Addr_Counters[1].FDRE_I_n_0 ),
.A2(\Addr_Counters[2].FDRE_I_n_0 ),
.A3(\Addr_Counters[3].FDRE_I_n_0 ),
.CE(CI),
.CLK(s_axi_aclk),
.D(bid_fifo_ld[11]),
.Q(bid_fifo_rd[11]));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT3 #(
.INIT(8'hB8))
\FIFO_RAM[0].SRL16E_I_i_1
(.I0(Q[11]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[11]),
.O(bid_fifo_ld[11]));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_bus_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM " *)
(* srl_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[10].SRL16E_I " *)
SRL16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\FIFO_RAM[10].SRL16E_I
(.A0(\Addr_Counters[0].FDRE_I_n_0 ),
.A1(\Addr_Counters[1].FDRE_I_n_0 ),
.A2(\Addr_Counters[2].FDRE_I_n_0 ),
.A3(\Addr_Counters[3].FDRE_I_n_0 ),
.CE(CI),
.CLK(s_axi_aclk),
.D(bid_fifo_ld[1]),
.Q(bid_fifo_rd[1]));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT3 #(
.INIT(8'hB8))
\FIFO_RAM[10].SRL16E_I_i_1
(.I0(Q[1]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[1]),
.O(bid_fifo_ld[1]));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_bus_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM " *)
(* srl_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[11].SRL16E_I " *)
SRL16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\FIFO_RAM[11].SRL16E_I
(.A0(\Addr_Counters[0].FDRE_I_n_0 ),
.A1(\Addr_Counters[1].FDRE_I_n_0 ),
.A2(\Addr_Counters[2].FDRE_I_n_0 ),
.A3(\Addr_Counters[3].FDRE_I_n_0 ),
.CE(CI),
.CLK(s_axi_aclk),
.D(bid_fifo_ld[0]),
.Q(bid_fifo_rd[0]));
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT3 #(
.INIT(8'hB8))
\FIFO_RAM[11].SRL16E_I_i_1
(.I0(Q[0]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[0]),
.O(bid_fifo_ld[0]));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_bus_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM " *)
(* srl_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[1].SRL16E_I " *)
SRL16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\FIFO_RAM[1].SRL16E_I
(.A0(\Addr_Counters[0].FDRE_I_n_0 ),
.A1(\Addr_Counters[1].FDRE_I_n_0 ),
.A2(\Addr_Counters[2].FDRE_I_n_0 ),
.A3(\Addr_Counters[3].FDRE_I_n_0 ),
.CE(CI),
.CLK(s_axi_aclk),
.D(bid_fifo_ld[10]),
.Q(bid_fifo_rd[10]));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT3 #(
.INIT(8'hB8))
\FIFO_RAM[1].SRL16E_I_i_1
(.I0(Q[10]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[10]),
.O(bid_fifo_ld[10]));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_bus_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM " *)
(* srl_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[2].SRL16E_I " *)
SRL16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\FIFO_RAM[2].SRL16E_I
(.A0(\Addr_Counters[0].FDRE_I_n_0 ),
.A1(\Addr_Counters[1].FDRE_I_n_0 ),
.A2(\Addr_Counters[2].FDRE_I_n_0 ),
.A3(\Addr_Counters[3].FDRE_I_n_0 ),
.CE(CI),
.CLK(s_axi_aclk),
.D(bid_fifo_ld[9]),
.Q(bid_fifo_rd[9]));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT3 #(
.INIT(8'hB8))
\FIFO_RAM[2].SRL16E_I_i_1
(.I0(Q[9]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[9]),
.O(bid_fifo_ld[9]));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_bus_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM " *)
(* srl_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[3].SRL16E_I " *)
SRL16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\FIFO_RAM[3].SRL16E_I
(.A0(\Addr_Counters[0].FDRE_I_n_0 ),
.A1(\Addr_Counters[1].FDRE_I_n_0 ),
.A2(\Addr_Counters[2].FDRE_I_n_0 ),
.A3(\Addr_Counters[3].FDRE_I_n_0 ),
.CE(CI),
.CLK(s_axi_aclk),
.D(bid_fifo_ld[8]),
.Q(bid_fifo_rd[8]));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT3 #(
.INIT(8'hB8))
\FIFO_RAM[3].SRL16E_I_i_1
(.I0(Q[8]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[8]),
.O(bid_fifo_ld[8]));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_bus_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM " *)
(* srl_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[4].SRL16E_I " *)
SRL16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\FIFO_RAM[4].SRL16E_I
(.A0(\Addr_Counters[0].FDRE_I_n_0 ),
.A1(\Addr_Counters[1].FDRE_I_n_0 ),
.A2(\Addr_Counters[2].FDRE_I_n_0 ),
.A3(\Addr_Counters[3].FDRE_I_n_0 ),
.CE(CI),
.CLK(s_axi_aclk),
.D(bid_fifo_ld[7]),
.Q(bid_fifo_rd[7]));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT3 #(
.INIT(8'hB8))
\FIFO_RAM[4].SRL16E_I_i_1
(.I0(Q[7]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[7]),
.O(bid_fifo_ld[7]));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_bus_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM " *)
(* srl_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[5].SRL16E_I " *)
SRL16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\FIFO_RAM[5].SRL16E_I
(.A0(\Addr_Counters[0].FDRE_I_n_0 ),
.A1(\Addr_Counters[1].FDRE_I_n_0 ),
.A2(\Addr_Counters[2].FDRE_I_n_0 ),
.A3(\Addr_Counters[3].FDRE_I_n_0 ),
.CE(CI),
.CLK(s_axi_aclk),
.D(bid_fifo_ld[6]),
.Q(bid_fifo_rd[6]));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT3 #(
.INIT(8'hB8))
\FIFO_RAM[5].SRL16E_I_i_1
(.I0(Q[6]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[6]),
.O(bid_fifo_ld[6]));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_bus_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM " *)
(* srl_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[6].SRL16E_I " *)
SRL16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\FIFO_RAM[6].SRL16E_I
(.A0(\Addr_Counters[0].FDRE_I_n_0 ),
.A1(\Addr_Counters[1].FDRE_I_n_0 ),
.A2(\Addr_Counters[2].FDRE_I_n_0 ),
.A3(\Addr_Counters[3].FDRE_I_n_0 ),
.CE(CI),
.CLK(s_axi_aclk),
.D(bid_fifo_ld[5]),
.Q(bid_fifo_rd[5]));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT3 #(
.INIT(8'hB8))
\FIFO_RAM[6].SRL16E_I_i_1
(.I0(Q[5]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[5]),
.O(bid_fifo_ld[5]));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_bus_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM " *)
(* srl_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[7].SRL16E_I " *)
SRL16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\FIFO_RAM[7].SRL16E_I
(.A0(\Addr_Counters[0].FDRE_I_n_0 ),
.A1(\Addr_Counters[1].FDRE_I_n_0 ),
.A2(\Addr_Counters[2].FDRE_I_n_0 ),
.A3(\Addr_Counters[3].FDRE_I_n_0 ),
.CE(CI),
.CLK(s_axi_aclk),
.D(bid_fifo_ld[4]),
.Q(bid_fifo_rd[4]));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT3 #(
.INIT(8'hB8))
\FIFO_RAM[7].SRL16E_I_i_1
(.I0(Q[4]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[4]),
.O(bid_fifo_ld[4]));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_bus_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM " *)
(* srl_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[8].SRL16E_I " *)
SRL16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\FIFO_RAM[8].SRL16E_I
(.A0(\Addr_Counters[0].FDRE_I_n_0 ),
.A1(\Addr_Counters[1].FDRE_I_n_0 ),
.A2(\Addr_Counters[2].FDRE_I_n_0 ),
.A3(\Addr_Counters[3].FDRE_I_n_0 ),
.CE(CI),
.CLK(s_axi_aclk),
.D(bid_fifo_ld[3]),
.Q(bid_fifo_rd[3]));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT3 #(
.INIT(8'hB8))
\FIFO_RAM[8].SRL16E_I_i_1
(.I0(Q[3]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[3]),
.O(bid_fifo_ld[3]));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_bus_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM " *)
(* srl_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[9].SRL16E_I " *)
SRL16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\FIFO_RAM[9].SRL16E_I
(.A0(\Addr_Counters[0].FDRE_I_n_0 ),
.A1(\Addr_Counters[1].FDRE_I_n_0 ),
.A2(\Addr_Counters[2].FDRE_I_n_0 ),
.A3(\Addr_Counters[3].FDRE_I_n_0 ),
.CE(CI),
.CLK(s_axi_aclk),
.D(bid_fifo_ld[2]),
.Q(bid_fifo_rd[2]));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT3 #(
.INIT(8'hB8))
\FIFO_RAM[9].SRL16E_I_i_1
(.I0(Q[2]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[2]),
.O(bid_fifo_ld[2]));
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT5 #(
.INIT(32'hB8FFB800))
\axi_bid_int[0]_i_1
(.I0(Q[0]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[0]),
.I3(bid_gets_fifo_load),
.I4(bid_fifo_rd[0]),
.O(D[0]));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT5 #(
.INIT(32'hB8FFB800))
\axi_bid_int[10]_i_1
(.I0(Q[10]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[10]),
.I3(bid_gets_fifo_load),
.I4(bid_fifo_rd[10]),
.O(D[10]));
LUT2 #(
.INIT(4'hE))
\axi_bid_int[11]_i_1
(.I0(bid_gets_fifo_load),
.I1(\axi_bid_int[11]_i_3_n_0 ),
.O(E));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT5 #(
.INIT(32'hB8FFB800))
\axi_bid_int[11]_i_2
(.I0(Q[11]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[11]),
.I3(bid_gets_fifo_load),
.I4(bid_fifo_rd[11]),
.O(D[11]));
LUT6 #(
.INIT(64'hA888AAAAA8888888))
\axi_bid_int[11]_i_3
(.I0(bid_fifo_not_empty),
.I1(bid_gets_fifo_load_d1),
.I2(s_axi_bready),
.I3(axi_bvalid_int_reg),
.I4(bid_gets_fifo_load_d1_i_3_n_0),
.I5(bvalid_cnt_inc),
.O(\axi_bid_int[11]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT5 #(
.INIT(32'hB8FFB800))
\axi_bid_int[1]_i_1
(.I0(Q[1]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[1]),
.I3(bid_gets_fifo_load),
.I4(bid_fifo_rd[1]),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT5 #(
.INIT(32'hB8FFB800))
\axi_bid_int[2]_i_1
(.I0(Q[2]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[2]),
.I3(bid_gets_fifo_load),
.I4(bid_fifo_rd[2]),
.O(D[2]));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT5 #(
.INIT(32'hB8FFB800))
\axi_bid_int[3]_i_1
(.I0(Q[3]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[3]),
.I3(bid_gets_fifo_load),
.I4(bid_fifo_rd[3]),
.O(D[3]));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT5 #(
.INIT(32'hB8FFB800))
\axi_bid_int[4]_i_1
(.I0(Q[4]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[4]),
.I3(bid_gets_fifo_load),
.I4(bid_fifo_rd[4]),
.O(D[4]));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT5 #(
.INIT(32'hB8FFB800))
\axi_bid_int[5]_i_1
(.I0(Q[5]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[5]),
.I3(bid_gets_fifo_load),
.I4(bid_fifo_rd[5]),
.O(D[5]));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT5 #(
.INIT(32'hB8FFB800))
\axi_bid_int[6]_i_1
(.I0(Q[6]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[6]),
.I3(bid_gets_fifo_load),
.I4(bid_fifo_rd[6]),
.O(D[6]));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT5 #(
.INIT(32'hB8FFB800))
\axi_bid_int[7]_i_1
(.I0(Q[7]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[7]),
.I3(bid_gets_fifo_load),
.I4(bid_fifo_rd[7]),
.O(D[7]));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT5 #(
.INIT(32'hB8FFB800))
\axi_bid_int[8]_i_1
(.I0(Q[8]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[8]),
.I3(bid_gets_fifo_load),
.I4(bid_fifo_rd[8]),
.O(D[8]));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT5 #(
.INIT(32'hB8FFB800))
\axi_bid_int[9]_i_1
(.I0(Q[9]),
.I1(axi_awaddr_full),
.I2(s_axi_awid[9]),
.I3(bid_gets_fifo_load),
.I4(bid_fifo_rd[9]),
.O(D[9]));
LUT6 #(
.INIT(64'h000055FD00000000))
axi_bvalid_int_i_2
(.I0(out[2]),
.I1(axi_wdata_full_cmb114_out),
.I2(axi_bvalid_int_i_4_n_0),
.I3(axi_wr_burst),
.I4(out[1]),
.I5(axi_bvalid_int_i_5_n_0),
.O(bvalid_cnt_inc));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT5 #(
.INIT(32'hFE000000))
axi_bvalid_int_i_3
(.I0(bvalid_cnt[1]),
.I1(bvalid_cnt[0]),
.I2(bvalid_cnt[2]),
.I3(axi_bvalid_int_reg),
.I4(s_axi_bready),
.O(bid_gets_fifo_load_d1_reg));
LUT6 #(
.INIT(64'h1F11000000000000))
axi_bvalid_int_i_4
(.I0(axi_bvalid_int_i_6_n_0),
.I1(\bvalid_cnt_reg[2] ),
.I2(wr_addr_sm_cs),
.I3(\bvalid_cnt_reg[2]_0 ),
.I4(\GEN_AWREADY.axi_aresetn_d2_reg ),
.I5(axi_awaddr_full),
.O(axi_bvalid_int_i_4_n_0));
LUT5 #(
.INIT(32'h74446444))
axi_bvalid_int_i_5
(.I0(out[0]),
.I1(out[2]),
.I2(s_axi_wvalid),
.I3(s_axi_wlast),
.I4(axi_wdata_full_cmb114_out),
.O(axi_bvalid_int_i_5_n_0));
LUT5 #(
.INIT(32'hFEFFFFFF))
axi_bvalid_int_i_6
(.I0(curr_awlen_reg_1_or_2),
.I1(axi_awlen_pipe_1_or_2),
.I2(\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg ),
.I3(axi_awaddr_full),
.I4(last_data_ack_mod),
.O(axi_bvalid_int_i_6_n_0));
LUT6 #(
.INIT(64'h7F7F7F007F007F00))
axi_wready_int_mod_i_2
(.I0(bvalid_cnt[1]),
.I1(bvalid_cnt[0]),
.I2(bvalid_cnt[2]),
.I3(aw_active),
.I4(s_axi_awready),
.I5(s_axi_awvalid),
.O(axi_wdata_full_cmb114_out));
LUT6 #(
.INIT(64'h00000800AA00AA00))
bid_gets_fifo_load_d1_i_1
(.I0(bram_addr_ld_en),
.I1(bid_gets_fifo_load_d1_reg),
.I2(bid_fifo_not_empty),
.I3(bvalid_cnt_inc),
.I4(\bvalid_cnt_reg[1] ),
.I5(bid_gets_fifo_load_d1_i_3_n_0),
.O(bid_gets_fifo_load));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT3 #(
.INIT(8'hFE))
bid_gets_fifo_load_d1_i_3
(.I0(bvalid_cnt[2]),
.I1(bvalid_cnt[0]),
.I2(bvalid_cnt[1]),
.O(bid_gets_fifo_load_d1_i_3_n_0));
endmodule
(* C_BRAM_ADDR_WIDTH = "14" *) (* C_BRAM_INST_MODE = "EXTERNAL" *) (* C_ECC = "0" *)
(* C_ECC_ONOFF_RESET_VALUE = "0" *) (* C_ECC_TYPE = "0" *) (* C_FAMILY = "zynq" *)
(* C_FAULT_INJECT = "0" *) (* C_MEMORY_DEPTH = "16384" *) (* C_SELECT_XPM = "0" *)
(* C_SINGLE_PORT_BRAM = "0" *) (* C_S_AXI_ADDR_WIDTH = "16" *) (* C_S_AXI_CTRL_ADDR_WIDTH = "32" *)
(* C_S_AXI_CTRL_DATA_WIDTH = "32" *) (* C_S_AXI_DATA_WIDTH = "32" *) (* C_S_AXI_ID_WIDTH = "12" *)
(* C_S_AXI_PROTOCOL = "AXI4" *) (* C_S_AXI_SUPPORTS_NARROW_BURST = "0" *) (* downgradeipidentifiedwarnings = "yes" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl
(s_axi_aclk,
s_axi_aresetn,
ecc_interrupt,
ecc_ue,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
s_axi_ctrl_awvalid,
s_axi_ctrl_awready,
s_axi_ctrl_awaddr,
s_axi_ctrl_wdata,
s_axi_ctrl_wvalid,
s_axi_ctrl_wready,
s_axi_ctrl_bresp,
s_axi_ctrl_bvalid,
s_axi_ctrl_bready,
s_axi_ctrl_araddr,
s_axi_ctrl_arvalid,
s_axi_ctrl_arready,
s_axi_ctrl_rdata,
s_axi_ctrl_rresp,
s_axi_ctrl_rvalid,
s_axi_ctrl_rready,
bram_rst_a,
bram_clk_a,
bram_en_a,
bram_we_a,
bram_addr_a,
bram_wrdata_a,
bram_rddata_a,
bram_rst_b,
bram_clk_b,
bram_en_b,
bram_we_b,
bram_addr_b,
bram_wrdata_b,
bram_rddata_b);
input s_axi_aclk;
input s_axi_aresetn;
output ecc_interrupt;
output ecc_ue;
input [11:0]s_axi_awid;
input [15:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [11:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [11:0]s_axi_arid;
input [15:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input s_axi_arvalid;
output s_axi_arready;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
input s_axi_ctrl_awvalid;
output s_axi_ctrl_awready;
input [31:0]s_axi_ctrl_awaddr;
input [31:0]s_axi_ctrl_wdata;
input s_axi_ctrl_wvalid;
output s_axi_ctrl_wready;
output [1:0]s_axi_ctrl_bresp;
output s_axi_ctrl_bvalid;
input s_axi_ctrl_bready;
input [31:0]s_axi_ctrl_araddr;
input s_axi_ctrl_arvalid;
output s_axi_ctrl_arready;
output [31:0]s_axi_ctrl_rdata;
output [1:0]s_axi_ctrl_rresp;
output s_axi_ctrl_rvalid;
input s_axi_ctrl_rready;
output bram_rst_a;
output bram_clk_a;
output bram_en_a;
output [3:0]bram_we_a;
output [15:0]bram_addr_a;
output [31:0]bram_wrdata_a;
input [31:0]bram_rddata_a;
output bram_rst_b;
output bram_clk_b;
output bram_en_b;
output [3:0]bram_we_b;
output [15:0]bram_addr_b;
output [31:0]bram_wrdata_b;
input [31:0]bram_rddata_b;
wire \<const0> ;
wire [15:2]\^bram_addr_a ;
wire [15:2]\^bram_addr_b ;
wire bram_en_a;
wire bram_en_b;
wire [31:0]bram_rddata_b;
wire bram_rst_a;
wire [3:0]bram_we_a;
wire [31:0]bram_wrdata_a;
wire s_axi_aclk;
wire [15:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire s_axi_aresetn;
wire [11:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire s_axi_arready;
wire s_axi_arvalid;
wire [15:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [11:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire s_axi_awready;
wire s_axi_awvalid;
wire [11:0]s_axi_bid;
wire s_axi_bready;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire [11:0]s_axi_rid;
wire s_axi_rlast;
wire s_axi_rready;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wlast;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
assign bram_addr_a[15:2] = \^bram_addr_a [15:2];
assign bram_addr_a[1] = \<const0> ;
assign bram_addr_a[0] = \<const0> ;
assign bram_addr_b[15:2] = \^bram_addr_b [15:2];
assign bram_addr_b[1] = \<const0> ;
assign bram_addr_b[0] = \<const0> ;
assign bram_clk_a = s_axi_aclk;
assign bram_clk_b = s_axi_aclk;
assign bram_rst_b = bram_rst_a;
assign bram_we_b[3] = \<const0> ;
assign bram_we_b[2] = \<const0> ;
assign bram_we_b[1] = \<const0> ;
assign bram_we_b[0] = \<const0> ;
assign bram_wrdata_b[31] = \<const0> ;
assign bram_wrdata_b[30] = \<const0> ;
assign bram_wrdata_b[29] = \<const0> ;
assign bram_wrdata_b[28] = \<const0> ;
assign bram_wrdata_b[27] = \<const0> ;
assign bram_wrdata_b[26] = \<const0> ;
assign bram_wrdata_b[25] = \<const0> ;
assign bram_wrdata_b[24] = \<const0> ;
assign bram_wrdata_b[23] = \<const0> ;
assign bram_wrdata_b[22] = \<const0> ;
assign bram_wrdata_b[21] = \<const0> ;
assign bram_wrdata_b[20] = \<const0> ;
assign bram_wrdata_b[19] = \<const0> ;
assign bram_wrdata_b[18] = \<const0> ;
assign bram_wrdata_b[17] = \<const0> ;
assign bram_wrdata_b[16] = \<const0> ;
assign bram_wrdata_b[15] = \<const0> ;
assign bram_wrdata_b[14] = \<const0> ;
assign bram_wrdata_b[13] = \<const0> ;
assign bram_wrdata_b[12] = \<const0> ;
assign bram_wrdata_b[11] = \<const0> ;
assign bram_wrdata_b[10] = \<const0> ;
assign bram_wrdata_b[9] = \<const0> ;
assign bram_wrdata_b[8] = \<const0> ;
assign bram_wrdata_b[7] = \<const0> ;
assign bram_wrdata_b[6] = \<const0> ;
assign bram_wrdata_b[5] = \<const0> ;
assign bram_wrdata_b[4] = \<const0> ;
assign bram_wrdata_b[3] = \<const0> ;
assign bram_wrdata_b[2] = \<const0> ;
assign bram_wrdata_b[1] = \<const0> ;
assign bram_wrdata_b[0] = \<const0> ;
assign ecc_interrupt = \<const0> ;
assign ecc_ue = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_ctrl_arready = \<const0> ;
assign s_axi_ctrl_awready = \<const0> ;
assign s_axi_ctrl_bresp[1] = \<const0> ;
assign s_axi_ctrl_bresp[0] = \<const0> ;
assign s_axi_ctrl_bvalid = \<const0> ;
assign s_axi_ctrl_rdata[31] = \<const0> ;
assign s_axi_ctrl_rdata[30] = \<const0> ;
assign s_axi_ctrl_rdata[29] = \<const0> ;
assign s_axi_ctrl_rdata[28] = \<const0> ;
assign s_axi_ctrl_rdata[27] = \<const0> ;
assign s_axi_ctrl_rdata[26] = \<const0> ;
assign s_axi_ctrl_rdata[25] = \<const0> ;
assign s_axi_ctrl_rdata[24] = \<const0> ;
assign s_axi_ctrl_rdata[23] = \<const0> ;
assign s_axi_ctrl_rdata[22] = \<const0> ;
assign s_axi_ctrl_rdata[21] = \<const0> ;
assign s_axi_ctrl_rdata[20] = \<const0> ;
assign s_axi_ctrl_rdata[19] = \<const0> ;
assign s_axi_ctrl_rdata[18] = \<const0> ;
assign s_axi_ctrl_rdata[17] = \<const0> ;
assign s_axi_ctrl_rdata[16] = \<const0> ;
assign s_axi_ctrl_rdata[15] = \<const0> ;
assign s_axi_ctrl_rdata[14] = \<const0> ;
assign s_axi_ctrl_rdata[13] = \<const0> ;
assign s_axi_ctrl_rdata[12] = \<const0> ;
assign s_axi_ctrl_rdata[11] = \<const0> ;
assign s_axi_ctrl_rdata[10] = \<const0> ;
assign s_axi_ctrl_rdata[9] = \<const0> ;
assign s_axi_ctrl_rdata[8] = \<const0> ;
assign s_axi_ctrl_rdata[7] = \<const0> ;
assign s_axi_ctrl_rdata[6] = \<const0> ;
assign s_axi_ctrl_rdata[5] = \<const0> ;
assign s_axi_ctrl_rdata[4] = \<const0> ;
assign s_axi_ctrl_rdata[3] = \<const0> ;
assign s_axi_ctrl_rdata[2] = \<const0> ;
assign s_axi_ctrl_rdata[1] = \<const0> ;
assign s_axi_ctrl_rdata[0] = \<const0> ;
assign s_axi_ctrl_rresp[1] = \<const0> ;
assign s_axi_ctrl_rresp[0] = \<const0> ;
assign s_axi_ctrl_rvalid = \<const0> ;
assign s_axi_ctrl_wready = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
GND GND
(.G(\<const0> ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl_top \gext_inst.abcv4_0_ext_inst
(.bram_addr_a(\^bram_addr_a ),
.bram_addr_b(\^bram_addr_b ),
.bram_en_a(bram_en_a),
.bram_en_b(bram_en_b),
.bram_rddata_b(bram_rddata_b),
.bram_rst_a(bram_rst_a),
.bram_we_a(bram_we_a),
.bram_wrdata_a(bram_wrdata_a),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr[15:2]),
.s_axi_arburst(s_axi_arburst),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr[15:2]),
.s_axi_awburst(s_axi_awburst),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bid(s_axi_bid),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rid(s_axi_rid),
.s_axi_rlast(s_axi_rlast),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wlast(s_axi_wlast),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wvalid(s_axi_wvalid));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl_top
(s_axi_rvalid,
s_axi_rlast,
s_axi_bvalid,
s_axi_awready,
bram_rst_a,
bram_addr_a,
s_axi_bid,
bram_en_a,
bram_we_a,
bram_wrdata_a,
bram_addr_b,
s_axi_rid,
s_axi_rdata,
s_axi_wready,
s_axi_arready,
bram_en_b,
s_axi_aresetn,
s_axi_wvalid,
s_axi_wlast,
s_axi_rready,
s_axi_bready,
s_axi_awburst,
s_axi_aclk,
s_axi_awlen,
s_axi_awaddr,
s_axi_awid,
s_axi_wstrb,
s_axi_wdata,
s_axi_arlen,
s_axi_araddr,
s_axi_arid,
bram_rddata_b,
s_axi_arburst,
s_axi_awvalid,
s_axi_arvalid);
output s_axi_rvalid;
output s_axi_rlast;
output s_axi_bvalid;
output s_axi_awready;
output bram_rst_a;
output [13:0]bram_addr_a;
output [11:0]s_axi_bid;
output bram_en_a;
output [3:0]bram_we_a;
output [31:0]bram_wrdata_a;
output [13:0]bram_addr_b;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output s_axi_wready;
output s_axi_arready;
output bram_en_b;
input s_axi_aresetn;
input s_axi_wvalid;
input s_axi_wlast;
input s_axi_rready;
input s_axi_bready;
input [1:0]s_axi_awburst;
input s_axi_aclk;
input [7:0]s_axi_awlen;
input [13:0]s_axi_awaddr;
input [11:0]s_axi_awid;
input [3:0]s_axi_wstrb;
input [31:0]s_axi_wdata;
input [7:0]s_axi_arlen;
input [13:0]s_axi_araddr;
input [11:0]s_axi_arid;
input [31:0]bram_rddata_b;
input [1:0]s_axi_arburst;
input s_axi_awvalid;
input s_axi_arvalid;
wire [13:0]bram_addr_a;
wire [13:0]bram_addr_b;
wire bram_en_a;
wire bram_en_b;
wire [31:0]bram_rddata_b;
wire bram_rst_a;
wire [3:0]bram_we_a;
wire [31:0]bram_wrdata_a;
wire s_axi_aclk;
wire [13:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire s_axi_aresetn;
wire [11:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire s_axi_arready;
wire s_axi_arvalid;
wire [13:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [11:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire s_axi_awready;
wire s_axi_awvalid;
wire [11:0]s_axi_bid;
wire s_axi_bready;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire [11:0]s_axi_rid;
wire s_axi_rlast;
wire s_axi_rready;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wlast;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_full_axi \GEN_AXI4.I_FULL_AXI
(.bram_addr_a(bram_addr_a),
.bram_addr_b(bram_addr_b),
.bram_en_a(bram_en_a),
.bram_en_b(bram_en_b),
.bram_rddata_b(bram_rddata_b),
.bram_rst_a(bram_rst_a),
.bram_we_a(bram_we_a),
.bram_wrdata_a(bram_wrdata_a),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bid(s_axi_bid),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rid(s_axi_rid),
.s_axi_rlast(s_axi_rlast),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wlast(s_axi_wlast),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wvalid(s_axi_wvalid));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_full_axi
(s_axi_rvalid,
s_axi_rlast,
s_axi_bvalid,
s_axi_awready,
bram_rst_a,
bram_addr_a,
s_axi_bid,
bram_en_a,
bram_we_a,
bram_wrdata_a,
bram_addr_b,
s_axi_rid,
s_axi_rdata,
s_axi_wready,
s_axi_arready,
bram_en_b,
s_axi_aresetn,
s_axi_wvalid,
s_axi_wlast,
s_axi_rready,
s_axi_bready,
s_axi_awburst,
s_axi_aclk,
s_axi_awlen,
s_axi_awaddr,
s_axi_awid,
s_axi_wstrb,
s_axi_wdata,
s_axi_arlen,
s_axi_araddr,
s_axi_arid,
bram_rddata_b,
s_axi_arburst,
s_axi_awvalid,
s_axi_arvalid);
output s_axi_rvalid;
output s_axi_rlast;
output s_axi_bvalid;
output s_axi_awready;
output bram_rst_a;
output [13:0]bram_addr_a;
output [11:0]s_axi_bid;
output bram_en_a;
output [3:0]bram_we_a;
output [31:0]bram_wrdata_a;
output [13:0]bram_addr_b;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output s_axi_wready;
output s_axi_arready;
output bram_en_b;
input s_axi_aresetn;
input s_axi_wvalid;
input s_axi_wlast;
input s_axi_rready;
input s_axi_bready;
input [1:0]s_axi_awburst;
input s_axi_aclk;
input [7:0]s_axi_awlen;
input [13:0]s_axi_awaddr;
input [11:0]s_axi_awid;
input [3:0]s_axi_wstrb;
input [31:0]s_axi_wdata;
input [7:0]s_axi_arlen;
input [13:0]s_axi_araddr;
input [11:0]s_axi_arid;
input [31:0]bram_rddata_b;
input [1:0]s_axi_arburst;
input s_axi_awvalid;
input s_axi_arvalid;
wire I_WR_CHNL_n_36;
wire axi_aresetn_d2;
wire axi_aresetn_re_reg;
wire [13:0]bram_addr_a;
wire [13:0]bram_addr_b;
wire bram_en_a;
wire bram_en_b;
wire [31:0]bram_rddata_b;
wire bram_rst_a;
wire [3:0]bram_we_a;
wire [31:0]bram_wrdata_a;
wire s_axi_aclk;
wire [13:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire s_axi_aresetn;
wire [11:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire s_axi_arready;
wire s_axi_arvalid;
wire [13:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [11:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire s_axi_awready;
wire s_axi_awvalid;
wire [11:0]s_axi_bid;
wire s_axi_bready;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire [11:0]s_axi_rid;
wire s_axi_rlast;
wire s_axi_rready;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wlast;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_chnl I_RD_CHNL
(.\GEN_AWREADY.axi_aresetn_d2_reg (I_WR_CHNL_n_36),
.Q(bram_addr_b),
.axi_aresetn_d2(axi_aresetn_d2),
.axi_aresetn_re_reg(axi_aresetn_re_reg),
.bram_en_b(bram_en_b),
.bram_rddata_b(bram_rddata_b),
.bram_rst_a(bram_rst_a),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rid(s_axi_rid),
.s_axi_rlast(s_axi_rlast),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_chnl I_WR_CHNL
(.\GEN_AW_DUAL.aw_active_reg_0 (I_WR_CHNL_n_36),
.SR(bram_rst_a),
.axi_aresetn_d2(axi_aresetn_d2),
.axi_aresetn_re_reg(axi_aresetn_re_reg),
.bram_addr_a(bram_addr_a),
.bram_en_a(bram_en_a),
.bram_we_a(bram_we_a),
.bram_wrdata_a(bram_wrdata_a),
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bid(s_axi_bid),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wlast(s_axi_wlast),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wvalid(s_axi_wvalid));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_chnl
(bram_rst_a,
s_axi_rdata,
s_axi_rlast,
s_axi_rvalid,
bram_en_b,
Q,
s_axi_arready,
s_axi_rid,
s_axi_araddr,
s_axi_aclk,
\GEN_AWREADY.axi_aresetn_d2_reg ,
s_axi_rready,
s_axi_aresetn,
s_axi_arlen,
axi_aresetn_d2,
s_axi_arvalid,
axi_aresetn_re_reg,
s_axi_arid,
s_axi_arburst,
bram_rddata_b);
output bram_rst_a;
output [31:0]s_axi_rdata;
output s_axi_rlast;
output s_axi_rvalid;
output bram_en_b;
output [13:0]Q;
output s_axi_arready;
output [11:0]s_axi_rid;
input [13:0]s_axi_araddr;
input s_axi_aclk;
input \GEN_AWREADY.axi_aresetn_d2_reg ;
input s_axi_rready;
input s_axi_aresetn;
input [7:0]s_axi_arlen;
input axi_aresetn_d2;
input s_axi_arvalid;
input axi_aresetn_re_reg;
input [11:0]s_axi_arid;
input [1:0]s_axi_arburst;
input [31:0]bram_rddata_b;
wire \/FSM_sequential_rlast_sm_cs[0]_i_2_n_0 ;
wire \/FSM_sequential_rlast_sm_cs[1]_i_2_n_0 ;
wire \/i__n_0 ;
wire \FSM_sequential_rlast_sm_cs[0]_i_1_n_0 ;
wire \FSM_sequential_rlast_sm_cs[1]_i_1_n_0 ;
wire \FSM_sequential_rlast_sm_cs[2]_i_1_n_0 ;
wire \GEN_ARREADY.axi_arready_int_i_1_n_0 ;
wire \GEN_ARREADY.axi_early_arready_int_i_2_n_0 ;
wire \GEN_ARREADY.axi_early_arready_int_i_3_n_0 ;
wire \GEN_AR_DUAL.ar_active_i_1_n_0 ;
wire \GEN_AR_DUAL.ar_active_i_2_n_0 ;
wire \GEN_AR_DUAL.ar_active_i_3_n_0 ;
wire \GEN_AR_DUAL.ar_active_i_4_n_0 ;
wire \GEN_AR_DUAL.rd_addr_sm_cs_i_1_n_0 ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.axi_araddr_full_i_1_n_0 ;
wire \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_i_1_n_0 ;
wire \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg_n_0 ;
wire \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2_n_0 ;
wire \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3_n_0 ;
wire \GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_2_n_0 ;
wire \GEN_AWREADY.axi_aresetn_d2_reg ;
wire \GEN_BRST_MAX_WO_NARROW.brst_cnt_max_i_1_n_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2_n_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1_n_0 ;
wire \GEN_RID.axi_rid_int[11]_i_1_n_0 ;
wire \GEN_RID.axi_rid_temp2_full_i_1_n_0 ;
wire \GEN_RID.axi_rid_temp[0]_i_1_n_0 ;
wire \GEN_RID.axi_rid_temp[10]_i_1_n_0 ;
wire \GEN_RID.axi_rid_temp[11]_i_1_n_0 ;
wire \GEN_RID.axi_rid_temp[11]_i_2_n_0 ;
wire \GEN_RID.axi_rid_temp[1]_i_1_n_0 ;
wire \GEN_RID.axi_rid_temp[2]_i_1_n_0 ;
wire \GEN_RID.axi_rid_temp[3]_i_1_n_0 ;
wire \GEN_RID.axi_rid_temp[4]_i_1_n_0 ;
wire \GEN_RID.axi_rid_temp[5]_i_1_n_0 ;
wire \GEN_RID.axi_rid_temp[6]_i_1_n_0 ;
wire \GEN_RID.axi_rid_temp[7]_i_1_n_0 ;
wire \GEN_RID.axi_rid_temp[8]_i_1_n_0 ;
wire \GEN_RID.axi_rid_temp[9]_i_1_n_0 ;
wire \GEN_RID.axi_rid_temp_full_i_1_n_0 ;
wire I_WRAP_BRST_n_1;
wire I_WRAP_BRST_n_10;
wire I_WRAP_BRST_n_11;
wire I_WRAP_BRST_n_12;
wire I_WRAP_BRST_n_13;
wire I_WRAP_BRST_n_14;
wire I_WRAP_BRST_n_15;
wire I_WRAP_BRST_n_16;
wire I_WRAP_BRST_n_17;
wire I_WRAP_BRST_n_18;
wire I_WRAP_BRST_n_19;
wire I_WRAP_BRST_n_2;
wire I_WRAP_BRST_n_20;
wire I_WRAP_BRST_n_21;
wire I_WRAP_BRST_n_23;
wire I_WRAP_BRST_n_24;
wire I_WRAP_BRST_n_25;
wire I_WRAP_BRST_n_26;
wire I_WRAP_BRST_n_27;
wire I_WRAP_BRST_n_28;
wire I_WRAP_BRST_n_3;
wire I_WRAP_BRST_n_4;
wire I_WRAP_BRST_n_6;
wire I_WRAP_BRST_n_7;
wire I_WRAP_BRST_n_8;
wire I_WRAP_BRST_n_9;
wire [13:0]Q;
wire act_rd_burst;
wire act_rd_burst_i_1_n_0;
wire act_rd_burst_i_3_n_0;
wire act_rd_burst_i_4_n_0;
wire act_rd_burst_set;
wire act_rd_burst_two;
wire act_rd_burst_two_i_1_n_0;
wire ar_active;
wire araddr_pipe_ld43_out;
wire axi_araddr_full;
wire [1:0]axi_arburst_pipe;
wire axi_aresetn_d2;
wire axi_aresetn_re_reg;
wire [11:0]axi_arid_pipe;
wire [7:0]axi_arlen_pipe;
wire axi_arlen_pipe_1_or_2;
wire axi_arready_int;
wire [1:1]axi_arsize_pipe;
wire axi_arsize_pipe_max;
wire axi_arsize_pipe_max_i_1_n_0;
wire axi_b2b_brst;
wire axi_b2b_brst_i_1_n_0;
wire axi_b2b_brst_i_3_n_0;
wire axi_early_arready_int;
wire axi_rd_burst;
wire axi_rd_burst_i_1_n_0;
wire axi_rd_burst_i_2_n_0;
wire axi_rd_burst_i_3_n_0;
wire axi_rd_burst_two;
wire axi_rd_burst_two_i_1_n_0;
wire axi_rd_burst_two_reg_n_0;
wire [11:0]axi_rid_temp;
wire [11:0]axi_rid_temp2;
wire [11:0]axi_rid_temp20_in;
wire axi_rid_temp2_full;
wire axi_rid_temp_full;
wire axi_rid_temp_full_d1;
wire axi_rlast_int_i_1_n_0;
wire axi_rlast_set;
wire axi_rvalid_clr_ok;
wire axi_rvalid_clr_ok_i_1_n_0;
wire axi_rvalid_clr_ok_i_2_n_0;
wire axi_rvalid_clr_ok_i_3_n_0;
wire axi_rvalid_int_i_1_n_0;
wire axi_rvalid_set;
wire axi_rvalid_set_cmb;
wire bram_addr_ld_en;
wire bram_addr_ld_en_mod;
wire bram_en_b;
wire bram_en_int_i_10_n_0;
wire bram_en_int_i_11_n_0;
wire bram_en_int_i_1_n_0;
wire bram_en_int_i_2_n_0;
wire bram_en_int_i_3_n_0;
wire bram_en_int_i_4_n_0;
wire bram_en_int_i_6_n_0;
wire bram_en_int_i_7_n_0;
wire bram_en_int_i_9_n_0;
wire [31:0]bram_rddata_b;
wire bram_rst_a;
wire [7:0]brst_cnt;
wire \brst_cnt[0]_i_1_n_0 ;
wire \brst_cnt[1]_i_1_n_0 ;
wire \brst_cnt[2]_i_1_n_0 ;
wire \brst_cnt[3]_i_1_n_0 ;
wire \brst_cnt[4]_i_1_n_0 ;
wire \brst_cnt[4]_i_2_n_0 ;
wire \brst_cnt[5]_i_1_n_0 ;
wire \brst_cnt[6]_i_1_n_0 ;
wire \brst_cnt[6]_i_2_n_0 ;
wire \brst_cnt[7]_i_1_n_0 ;
wire \brst_cnt[7]_i_2_n_0 ;
wire \brst_cnt[7]_i_3_n_0 ;
wire \brst_cnt[7]_i_4_n_0 ;
wire brst_cnt_max;
wire brst_cnt_max_d1;
wire brst_one;
wire brst_one0;
wire brst_one_i_1_n_0;
wire brst_zero;
wire brst_zero_i_1_n_0;
wire brst_zero_i_2_n_0;
wire curr_fixed_burst;
wire curr_fixed_burst_reg;
wire curr_wrap_burst;
wire curr_wrap_burst_reg;
wire disable_b2b_brst;
wire disable_b2b_brst_cmb;
wire disable_b2b_brst_i_2_n_0;
wire disable_b2b_brst_i_3_n_0;
wire disable_b2b_brst_i_4_n_0;
wire end_brst_rd;
wire end_brst_rd_clr;
wire end_brst_rd_clr_i_1_n_0;
wire end_brst_rd_i_1_n_0;
wire last_bram_addr;
wire last_bram_addr0;
wire last_bram_addr_i_2_n_0;
wire last_bram_addr_i_3_n_0;
wire last_bram_addr_i_4_n_0;
wire last_bram_addr_i_5_n_0;
wire last_bram_addr_i_6_n_0;
wire last_bram_addr_i_7_n_0;
wire last_bram_addr_i_8_n_0;
wire last_bram_addr_i_9_n_0;
wire no_ar_ack;
wire no_ar_ack_i_1_n_0;
wire p_0_in13_in;
wire p_13_out;
wire p_26_out;
wire p_48_out;
wire p_4_out;
wire p_9_out;
wire pend_rd_op;
wire pend_rd_op_i_1_n_0;
wire pend_rd_op_i_2_n_0;
wire pend_rd_op_i_3_n_0;
wire pend_rd_op_i_4_n_0;
wire pend_rd_op_i_5_n_0;
wire pend_rd_op_i_6_n_0;
wire pend_rd_op_i_7_n_0;
wire pend_rd_op_i_8_n_0;
wire pend_rd_op_i_9_n_0;
wire rd_addr_sm_cs;
wire rd_adv_buf67_out;
wire [3:0]rd_data_sm_cs;
wire \rd_data_sm_cs[0]_i_1_n_0 ;
wire \rd_data_sm_cs[0]_i_2_n_0 ;
wire \rd_data_sm_cs[0]_i_3_n_0 ;
wire \rd_data_sm_cs[0]_i_4_n_0 ;
wire \rd_data_sm_cs[1]_i_1_n_0 ;
wire \rd_data_sm_cs[1]_i_3_n_0 ;
wire \rd_data_sm_cs[2]_i_1_n_0 ;
wire \rd_data_sm_cs[2]_i_2_n_0 ;
wire \rd_data_sm_cs[2]_i_3_n_0 ;
wire \rd_data_sm_cs[2]_i_4_n_0 ;
wire \rd_data_sm_cs[2]_i_5_n_0 ;
wire \rd_data_sm_cs[3]_i_2_n_0 ;
wire \rd_data_sm_cs[3]_i_3_n_0 ;
wire \rd_data_sm_cs[3]_i_4_n_0 ;
wire \rd_data_sm_cs[3]_i_5_n_0 ;
wire \rd_data_sm_cs[3]_i_6_n_0 ;
wire \rd_data_sm_cs[3]_i_7_n_0 ;
wire rd_data_sm_ns;
wire [31:0]rd_skid_buf;
wire rd_skid_buf_ld;
wire rd_skid_buf_ld_cmb;
wire rd_skid_buf_ld_reg;
wire rddata_mux_sel;
wire rddata_mux_sel_cmb;
wire rddata_mux_sel_i_1_n_0;
wire rddata_mux_sel_i_3_n_0;
(* RTL_KEEP = "yes" *) wire [2:0]rlast_sm_cs;
wire s_axi_aclk;
wire [13:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire s_axi_aresetn;
wire [11:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire s_axi_arready;
wire s_axi_arvalid;
wire [31:0]s_axi_rdata;
wire [11:0]s_axi_rid;
wire s_axi_rlast;
wire s_axi_rready;
wire s_axi_rvalid;
LUT6 #(
.INIT(64'h0011001300130013))
\/FSM_sequential_rlast_sm_cs[0]_i_2
(.I0(axi_rd_burst),
.I1(rlast_sm_cs[1]),
.I2(act_rd_burst_two),
.I3(axi_rd_burst_two_reg_n_0),
.I4(s_axi_rvalid),
.I5(s_axi_rready),
.O(\/FSM_sequential_rlast_sm_cs[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'h003F007F003F0055))
\/FSM_sequential_rlast_sm_cs[1]_i_2
(.I0(axi_rd_burst),
.I1(s_axi_rready),
.I2(s_axi_rvalid),
.I3(rlast_sm_cs[1]),
.I4(axi_rd_burst_two_reg_n_0),
.I5(act_rd_burst_two),
.O(\/FSM_sequential_rlast_sm_cs[1]_i_2_n_0 ));
LUT6 #(
.INIT(64'hF000F111F000E000))
\/i_
(.I0(rlast_sm_cs[2]),
.I1(rlast_sm_cs[1]),
.I2(s_axi_rvalid),
.I3(s_axi_rready),
.I4(rlast_sm_cs[0]),
.I5(last_bram_addr),
.O(\/i__n_0 ));
LUT6 #(
.INIT(64'h00008080000F8080))
\/i___0
(.I0(s_axi_rready),
.I1(s_axi_rvalid),
.I2(rlast_sm_cs[0]),
.I3(rlast_sm_cs[1]),
.I4(rlast_sm_cs[2]),
.I5(s_axi_rlast),
.O(axi_rlast_set));
LUT5 #(
.INIT(32'h01FF0100))
\FSM_sequential_rlast_sm_cs[0]_i_1
(.I0(rlast_sm_cs[2]),
.I1(rlast_sm_cs[0]),
.I2(\/FSM_sequential_rlast_sm_cs[0]_i_2_n_0 ),
.I3(\/i__n_0 ),
.I4(rlast_sm_cs[0]),
.O(\FSM_sequential_rlast_sm_cs[0]_i_1_n_0 ));
LUT5 #(
.INIT(32'h01FF0100))
\FSM_sequential_rlast_sm_cs[1]_i_1
(.I0(rlast_sm_cs[2]),
.I1(rlast_sm_cs[0]),
.I2(\/FSM_sequential_rlast_sm_cs[1]_i_2_n_0 ),
.I3(\/i__n_0 ),
.I4(rlast_sm_cs[1]),
.O(\FSM_sequential_rlast_sm_cs[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'h00A4FFFF00A40000))
\FSM_sequential_rlast_sm_cs[2]_i_1
(.I0(rlast_sm_cs[1]),
.I1(p_0_in13_in),
.I2(rlast_sm_cs[0]),
.I3(rlast_sm_cs[2]),
.I4(\/i__n_0 ),
.I5(rlast_sm_cs[2]),
.O(\FSM_sequential_rlast_sm_cs[2]_i_1_n_0 ));
LUT2 #(
.INIT(4'h1))
\FSM_sequential_rlast_sm_cs[2]_i_2
(.I0(axi_rd_burst_two_reg_n_0),
.I1(axi_rd_burst),
.O(p_0_in13_in));
(* KEEP = "yes" *)
FDRE \FSM_sequential_rlast_sm_cs_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\FSM_sequential_rlast_sm_cs[0]_i_1_n_0 ),
.Q(rlast_sm_cs[0]),
.R(bram_rst_a));
(* KEEP = "yes" *)
FDRE \FSM_sequential_rlast_sm_cs_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\FSM_sequential_rlast_sm_cs[1]_i_1_n_0 ),
.Q(rlast_sm_cs[1]),
.R(bram_rst_a));
(* KEEP = "yes" *)
FDRE \FSM_sequential_rlast_sm_cs_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\FSM_sequential_rlast_sm_cs[2]_i_1_n_0 ),
.Q(rlast_sm_cs[2]),
.R(bram_rst_a));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT5 #(
.INIT(32'hAAAAAEEE))
\GEN_ARREADY.axi_arready_int_i_1
(.I0(p_9_out),
.I1(axi_arready_int),
.I2(s_axi_arvalid),
.I3(axi_araddr_full),
.I4(araddr_pipe_ld43_out),
.O(\GEN_ARREADY.axi_arready_int_i_1_n_0 ));
LUT4 #(
.INIT(16'hBAAA))
\GEN_ARREADY.axi_arready_int_i_2
(.I0(axi_aresetn_re_reg),
.I1(axi_early_arready_int),
.I2(axi_araddr_full),
.I3(bram_addr_ld_en),
.O(p_9_out));
FDRE #(
.INIT(1'b0))
\GEN_ARREADY.axi_arready_int_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_ARREADY.axi_arready_int_i_1_n_0 ),
.Q(axi_arready_int),
.R(bram_rst_a));
LUT6 #(
.INIT(64'h0000000000000200))
\GEN_ARREADY.axi_early_arready_int_i_1
(.I0(\GEN_ARREADY.axi_early_arready_int_i_2_n_0 ),
.I1(\GEN_ARREADY.axi_early_arready_int_i_3_n_0 ),
.I2(rd_data_sm_cs[3]),
.I3(brst_one),
.I4(axi_arready_int),
.I5(I_WRAP_BRST_n_26),
.O(p_48_out));
LUT6 #(
.INIT(64'h00CC304400000044))
\GEN_ARREADY.axi_early_arready_int_i_2
(.I0(axi_rd_burst_two_reg_n_0),
.I1(rd_data_sm_cs[1]),
.I2(\rd_data_sm_cs[2]_i_5_n_0 ),
.I3(rd_data_sm_cs[2]),
.I4(rd_data_sm_cs[0]),
.I5(rd_adv_buf67_out),
.O(\GEN_ARREADY.axi_early_arready_int_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT2 #(
.INIT(4'h7))
\GEN_ARREADY.axi_early_arready_int_i_3
(.I0(axi_araddr_full),
.I1(s_axi_arvalid),
.O(\GEN_ARREADY.axi_early_arready_int_i_3_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_ARREADY.axi_early_arready_int_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(p_48_out),
.Q(axi_early_arready_int),
.R(bram_rst_a));
LUT6 #(
.INIT(64'hCDCDCDDDCCCCCCCC))
\GEN_AR_DUAL.ar_active_i_1
(.I0(\GEN_AR_DUAL.ar_active_i_2_n_0 ),
.I1(bram_addr_ld_en),
.I2(\GEN_AR_DUAL.ar_active_i_3_n_0 ),
.I3(end_brst_rd),
.I4(brst_zero),
.I5(ar_active),
.O(\GEN_AR_DUAL.ar_active_i_1_n_0 ));
LUT6 #(
.INIT(64'h808880808088A280))
\GEN_AR_DUAL.ar_active_i_2
(.I0(pend_rd_op_i_6_n_0),
.I1(rd_data_sm_cs[1]),
.I2(\GEN_AR_DUAL.ar_active_i_4_n_0 ),
.I3(rd_data_sm_cs[0]),
.I4(axi_rd_burst_two_reg_n_0),
.I5(axi_rd_burst),
.O(\GEN_AR_DUAL.ar_active_i_2_n_0 ));
LUT6 #(
.INIT(64'h0010000000000000))
\GEN_AR_DUAL.ar_active_i_3
(.I0(rd_data_sm_cs[3]),
.I1(rd_data_sm_cs[1]),
.I2(rd_data_sm_cs[2]),
.I3(rd_data_sm_cs[0]),
.I4(s_axi_rvalid),
.I5(s_axi_rready),
.O(\GEN_AR_DUAL.ar_active_i_3_n_0 ));
LUT6 #(
.INIT(64'h8A88000000000000))
\GEN_AR_DUAL.ar_active_i_4
(.I0(I_WRAP_BRST_n_27),
.I1(brst_zero),
.I2(axi_b2b_brst),
.I3(end_brst_rd),
.I4(rd_adv_buf67_out),
.I5(rd_data_sm_cs[0]),
.O(\GEN_AR_DUAL.ar_active_i_4_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_AR_DUAL.ar_active_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_AR_DUAL.ar_active_i_1_n_0 ),
.Q(ar_active),
.R(\GEN_AWREADY.axi_aresetn_d2_reg ));
LUT6 #(
.INIT(64'h10001000F0F01000))
\GEN_AR_DUAL.rd_addr_sm_cs_i_1
(.I0(rd_addr_sm_cs),
.I1(axi_araddr_full),
.I2(s_axi_arvalid),
.I3(\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3_n_0 ),
.I4(last_bram_addr),
.I5(I_WRAP_BRST_n_26),
.O(\GEN_AR_DUAL.rd_addr_sm_cs_i_1_n_0 ));
FDRE \GEN_AR_DUAL.rd_addr_sm_cs_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_AR_DUAL.rd_addr_sm_cs_i_1_n_0 ),
.Q(rd_addr_sm_cs),
.R(\GEN_AWREADY.axi_aresetn_d2_reg ));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg[10]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[8]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg[11]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[9]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg[12]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[10]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg[13]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[11]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg[14]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[12]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg[15]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[13]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg[2]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[0]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg[3]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[1]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg[4]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[2]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg[5]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[3]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg[6]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[4]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg[7]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[5]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg[8]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[6]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg[9]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[7]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg ),
.R(1'b0));
LUT6 #(
.INIT(64'h00C08888CCCC8888))
\GEN_AR_PIPE_DUAL.axi_araddr_full_i_1
(.I0(araddr_pipe_ld43_out),
.I1(s_axi_aresetn),
.I2(s_axi_arvalid),
.I3(\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2_n_0 ),
.I4(axi_araddr_full),
.I5(bram_addr_ld_en),
.O(\GEN_AR_PIPE_DUAL.axi_araddr_full_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_araddr_full_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_AR_PIPE_DUAL.axi_araddr_full_i_1_n_0 ),
.Q(axi_araddr_full),
.R(1'b0));
LUT4 #(
.INIT(16'h03AA))
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_i_1
(.I0(\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg_n_0 ),
.I1(s_axi_arburst[0]),
.I2(s_axi_arburst[1]),
.I3(araddr_pipe_ld43_out),
.O(\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_i_1_n_0 ),
.Q(\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg_n_0 ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_reg[0]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arburst[0]),
.Q(axi_arburst_pipe[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_reg[1]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arburst[1]),
.Q(axi_arburst_pipe[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[0]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arid[0]),
.Q(axi_arid_pipe[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[10]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arid[10]),
.Q(axi_arid_pipe[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[11]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arid[11]),
.Q(axi_arid_pipe[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[1]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arid[1]),
.Q(axi_arid_pipe[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[2]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arid[2]),
.Q(axi_arid_pipe[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[3]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arid[3]),
.Q(axi_arid_pipe[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[4]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arid[4]),
.Q(axi_arid_pipe[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[5]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arid[5]),
.Q(axi_arid_pipe[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[6]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arid[6]),
.Q(axi_arid_pipe[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[7]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arid[7]),
.Q(axi_arid_pipe[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[8]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arid[8]),
.Q(axi_arid_pipe[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[9]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arid[9]),
.Q(axi_arid_pipe[9]),
.R(1'b0));
LUT6 #(
.INIT(64'h220022002A002200))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_1
(.I0(axi_aresetn_d2),
.I1(\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2_n_0 ),
.I2(rd_addr_sm_cs),
.I3(s_axi_arvalid),
.I4(\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3_n_0 ),
.I5(axi_araddr_full),
.O(araddr_pipe_ld43_out));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT2 #(
.INIT(4'hB))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2
(.I0(I_WRAP_BRST_n_26),
.I1(last_bram_addr),
.O(\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2_n_0 ));
LUT3 #(
.INIT(8'hFE))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3
(.I0(no_ar_ack),
.I1(pend_rd_op),
.I2(ar_active),
.O(\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3_n_0 ));
LUT4 #(
.INIT(16'h0001))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_1
(.I0(s_axi_arlen[7]),
.I1(s_axi_arlen[1]),
.I2(s_axi_arlen[3]),
.I3(\GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_2_n_0 ),
.O(p_13_out));
LUT4 #(
.INIT(16'hFFFE))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_2
(.I0(s_axi_arlen[5]),
.I1(s_axi_arlen[4]),
.I2(s_axi_arlen[2]),
.I3(s_axi_arlen[6]),
.O(\GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_reg
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(p_13_out),
.Q(axi_arlen_pipe_1_or_2),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[0]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arlen[0]),
.Q(axi_arlen_pipe[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[1]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arlen[1]),
.Q(axi_arlen_pipe[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[2]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arlen[2]),
.Q(axi_arlen_pipe[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arlen[3]),
.Q(axi_arlen_pipe[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[4]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arlen[4]),
.Q(axi_arlen_pipe[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[5]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arlen[5]),
.Q(axi_arlen_pipe[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[6]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arlen[6]),
.Q(axi_arlen_pipe[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[7]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arlen[7]),
.Q(axi_arlen_pipe[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arsize_pipe_reg[1]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(1'b1),
.Q(axi_arsize_pipe),
.R(1'b0));
LUT6 #(
.INIT(64'h00000000BAAA0000))
\GEN_BRST_MAX_WO_NARROW.brst_cnt_max_i_1
(.I0(brst_cnt_max),
.I1(pend_rd_op),
.I2(ar_active),
.I3(brst_zero),
.I4(s_axi_aresetn),
.I5(bram_addr_ld_en),
.O(\GEN_BRST_MAX_WO_NARROW.brst_cnt_max_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_BRST_MAX_WO_NARROW.brst_cnt_max_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_BRST_MAX_WO_NARROW.brst_cnt_max_i_1_n_0 ),
.Q(brst_cnt_max),
.R(1'b0));
LUT6 #(
.INIT(64'h7FFFFFFFFFFFFFFF))
\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2
(.I0(Q[4]),
.I1(Q[1]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[3]),
.I5(Q[5]),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2_n_0 ));
LUT5 #(
.INIT(32'hF7FFFFFF))
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4
(.I0(Q[6]),
.I1(Q[4]),
.I2(I_WRAP_BRST_n_23),
.I3(Q[5]),
.I4(Q[7]),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[10]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_6),
.D(I_WRAP_BRST_n_13),
.Q(Q[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_6),
.D(I_WRAP_BRST_n_12),
.Q(Q[9]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[12]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en_mod),
.D(I_WRAP_BRST_n_11),
.Q(Q[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[13]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en_mod),
.D(I_WRAP_BRST_n_10),
.Q(Q[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[14]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en_mod),
.D(I_WRAP_BRST_n_9),
.Q(Q[12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[15]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en_mod),
.D(I_WRAP_BRST_n_8),
.Q(Q[13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[2]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_6),
.D(I_WRAP_BRST_n_21),
.Q(Q[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[3]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_6),
.D(I_WRAP_BRST_n_20),
.Q(Q[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[4]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_6),
.D(I_WRAP_BRST_n_19),
.Q(Q[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[5]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_6),
.D(I_WRAP_BRST_n_18),
.Q(Q[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_6),
.D(I_WRAP_BRST_n_17),
.Q(Q[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[7]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_6),
.D(I_WRAP_BRST_n_16),
.Q(Q[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_6),
.D(I_WRAP_BRST_n_15),
.Q(Q[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[9]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_6),
.D(I_WRAP_BRST_n_14),
.Q(Q[7]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1
(.I0(rd_skid_buf[0]),
.I1(bram_rddata_b[0]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int_reg[0]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1_n_0 ),
.Q(s_axi_rdata[0]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1
(.I0(rd_skid_buf[10]),
.I1(bram_rddata_b[10]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int_reg[10]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1_n_0 ),
.Q(s_axi_rdata[10]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1
(.I0(rd_skid_buf[11]),
.I1(bram_rddata_b[11]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int_reg[11]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1_n_0 ),
.Q(s_axi_rdata[11]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1
(.I0(rd_skid_buf[12]),
.I1(bram_rddata_b[12]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int_reg[12]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1_n_0 ),
.Q(s_axi_rdata[12]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1
(.I0(rd_skid_buf[13]),
.I1(bram_rddata_b[13]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int_reg[13]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1_n_0 ),
.Q(s_axi_rdata[13]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1
(.I0(rd_skid_buf[14]),
.I1(bram_rddata_b[14]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int_reg[14]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1_n_0 ),
.Q(s_axi_rdata[14]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1
(.I0(rd_skid_buf[15]),
.I1(bram_rddata_b[15]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int_reg[15]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1_n_0 ),
.Q(s_axi_rdata[15]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1
(.I0(rd_skid_buf[16]),
.I1(bram_rddata_b[16]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int_reg[16]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1_n_0 ),
.Q(s_axi_rdata[16]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1
(.I0(rd_skid_buf[17]),
.I1(bram_rddata_b[17]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int_reg[17]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1_n_0 ),
.Q(s_axi_rdata[17]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1
(.I0(rd_skid_buf[18]),
.I1(bram_rddata_b[18]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int_reg[18]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1_n_0 ),
.Q(s_axi_rdata[18]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1
(.I0(rd_skid_buf[19]),
.I1(bram_rddata_b[19]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int_reg[19]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1_n_0 ),
.Q(s_axi_rdata[19]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1
(.I0(rd_skid_buf[1]),
.I1(bram_rddata_b[1]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int_reg[1]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1_n_0 ),
.Q(s_axi_rdata[1]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1
(.I0(rd_skid_buf[20]),
.I1(bram_rddata_b[20]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int_reg[20]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1_n_0 ),
.Q(s_axi_rdata[20]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1
(.I0(rd_skid_buf[21]),
.I1(bram_rddata_b[21]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int_reg[21]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1_n_0 ),
.Q(s_axi_rdata[21]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1
(.I0(rd_skid_buf[22]),
.I1(bram_rddata_b[22]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int_reg[22]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1_n_0 ),
.Q(s_axi_rdata[22]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1
(.I0(rd_skid_buf[23]),
.I1(bram_rddata_b[23]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int_reg[23]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1_n_0 ),
.Q(s_axi_rdata[23]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1
(.I0(rd_skid_buf[24]),
.I1(bram_rddata_b[24]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int_reg[24]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1_n_0 ),
.Q(s_axi_rdata[24]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1
(.I0(rd_skid_buf[25]),
.I1(bram_rddata_b[25]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int_reg[25]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1_n_0 ),
.Q(s_axi_rdata[25]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1
(.I0(rd_skid_buf[26]),
.I1(bram_rddata_b[26]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int_reg[26]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1_n_0 ),
.Q(s_axi_rdata[26]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1
(.I0(rd_skid_buf[27]),
.I1(bram_rddata_b[27]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int_reg[27]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1_n_0 ),
.Q(s_axi_rdata[27]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1
(.I0(rd_skid_buf[28]),
.I1(bram_rddata_b[28]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int_reg[28]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1_n_0 ),
.Q(s_axi_rdata[28]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1
(.I0(rd_skid_buf[29]),
.I1(bram_rddata_b[29]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int_reg[29]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1_n_0 ),
.Q(s_axi_rdata[29]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1
(.I0(rd_skid_buf[2]),
.I1(bram_rddata_b[2]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int_reg[2]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1_n_0 ),
.Q(s_axi_rdata[2]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1
(.I0(rd_skid_buf[30]),
.I1(bram_rddata_b[30]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int_reg[30]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1_n_0 ),
.Q(s_axi_rdata[30]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
LUT6 #(
.INIT(64'h1414545410000404))
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1
(.I0(rd_data_sm_cs[3]),
.I1(rd_data_sm_cs[1]),
.I2(rd_data_sm_cs[2]),
.I3(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3_n_0 ),
.I4(rd_data_sm_cs[0]),
.I5(rd_adv_buf67_out),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2
(.I0(rd_skid_buf[31]),
.I1(bram_rddata_b[31]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT2 #(
.INIT(4'h1))
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3
(.I0(act_rd_burst),
.I1(act_rd_burst_two),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int_reg[31]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0 ),
.Q(s_axi_rdata[31]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1
(.I0(rd_skid_buf[3]),
.I1(bram_rddata_b[3]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int_reg[3]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1_n_0 ),
.Q(s_axi_rdata[3]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1
(.I0(rd_skid_buf[4]),
.I1(bram_rddata_b[4]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int_reg[4]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1_n_0 ),
.Q(s_axi_rdata[4]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1
(.I0(rd_skid_buf[5]),
.I1(bram_rddata_b[5]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int_reg[5]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1_n_0 ),
.Q(s_axi_rdata[5]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1
(.I0(rd_skid_buf[6]),
.I1(bram_rddata_b[6]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int_reg[6]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1_n_0 ),
.Q(s_axi_rdata[6]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1
(.I0(rd_skid_buf[7]),
.I1(bram_rddata_b[7]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int_reg[7]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1_n_0 ),
.Q(s_axi_rdata[7]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1
(.I0(rd_skid_buf[8]),
.I1(bram_rddata_b[8]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int_reg[8]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1_n_0 ),
.Q(s_axi_rdata[8]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1
(.I0(rd_skid_buf[9]),
.I1(bram_rddata_b[9]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int_reg[9]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1_n_0 ),
.Q(s_axi_rdata[9]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAAAAAAAAAAAAAEAA))
\GEN_RDATA_NO_ECC.rd_skid_buf[31]_i_1
(.I0(rd_skid_buf_ld_reg),
.I1(rd_adv_buf67_out),
.I2(rd_data_sm_cs[0]),
.I3(rd_data_sm_cs[2]),
.I4(rd_data_sm_cs[1]),
.I5(rd_data_sm_cs[3]),
.O(rd_skid_buf_ld));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[0]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[0]),
.Q(rd_skid_buf[0]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[10]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[10]),
.Q(rd_skid_buf[10]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[11]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[11]),
.Q(rd_skid_buf[11]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[12]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[12]),
.Q(rd_skid_buf[12]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[13]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[13]),
.Q(rd_skid_buf[13]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[14]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[14]),
.Q(rd_skid_buf[14]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[15]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[15]),
.Q(rd_skid_buf[15]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[16]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[16]),
.Q(rd_skid_buf[16]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[17]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[17]),
.Q(rd_skid_buf[17]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[18]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[18]),
.Q(rd_skid_buf[18]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[19]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[19]),
.Q(rd_skid_buf[19]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[1]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[1]),
.Q(rd_skid_buf[1]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[20]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[20]),
.Q(rd_skid_buf[20]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[21]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[21]),
.Q(rd_skid_buf[21]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[22]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[22]),
.Q(rd_skid_buf[22]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[23]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[23]),
.Q(rd_skid_buf[23]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[24]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[24]),
.Q(rd_skid_buf[24]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[25]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[25]),
.Q(rd_skid_buf[25]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[26]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[26]),
.Q(rd_skid_buf[26]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[27]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[27]),
.Q(rd_skid_buf[27]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[28]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[28]),
.Q(rd_skid_buf[28]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[29]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[29]),
.Q(rd_skid_buf[29]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[2]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[2]),
.Q(rd_skid_buf[2]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[30]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[30]),
.Q(rd_skid_buf[30]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[31]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[31]),
.Q(rd_skid_buf[31]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[3]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[3]),
.Q(rd_skid_buf[3]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[4]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[4]),
.Q(rd_skid_buf[4]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[5]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[5]),
.Q(rd_skid_buf[5]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[6]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[6]),
.Q(rd_skid_buf[6]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[7]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[7]),
.Q(rd_skid_buf[7]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[8]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[8]),
.Q(rd_skid_buf[8]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[9]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[9]),
.Q(rd_skid_buf[9]),
.R(bram_rst_a));
LUT4 #(
.INIT(16'h08FF))
\GEN_RID.axi_rid_int[11]_i_1
(.I0(s_axi_rready),
.I1(s_axi_rlast),
.I2(axi_b2b_brst),
.I3(s_axi_aresetn),
.O(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
LUT4 #(
.INIT(16'hEAAA))
\GEN_RID.axi_rid_int[11]_i_2
(.I0(axi_rvalid_set),
.I1(s_axi_rready),
.I2(s_axi_rlast),
.I3(axi_b2b_brst),
.O(p_4_out));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_int_reg[0]
(.C(s_axi_aclk),
.CE(p_4_out),
.D(axi_rid_temp[0]),
.Q(s_axi_rid[0]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_int_reg[10]
(.C(s_axi_aclk),
.CE(p_4_out),
.D(axi_rid_temp[10]),
.Q(s_axi_rid[10]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_int_reg[11]
(.C(s_axi_aclk),
.CE(p_4_out),
.D(axi_rid_temp[11]),
.Q(s_axi_rid[11]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_int_reg[1]
(.C(s_axi_aclk),
.CE(p_4_out),
.D(axi_rid_temp[1]),
.Q(s_axi_rid[1]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_int_reg[2]
(.C(s_axi_aclk),
.CE(p_4_out),
.D(axi_rid_temp[2]),
.Q(s_axi_rid[2]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_int_reg[3]
(.C(s_axi_aclk),
.CE(p_4_out),
.D(axi_rid_temp[3]),
.Q(s_axi_rid[3]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_int_reg[4]
(.C(s_axi_aclk),
.CE(p_4_out),
.D(axi_rid_temp[4]),
.Q(s_axi_rid[4]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_int_reg[5]
(.C(s_axi_aclk),
.CE(p_4_out),
.D(axi_rid_temp[5]),
.Q(s_axi_rid[5]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_int_reg[6]
(.C(s_axi_aclk),
.CE(p_4_out),
.D(axi_rid_temp[6]),
.Q(s_axi_rid[6]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_int_reg[7]
(.C(s_axi_aclk),
.CE(p_4_out),
.D(axi_rid_temp[7]),
.Q(s_axi_rid[7]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_int_reg[8]
(.C(s_axi_aclk),
.CE(p_4_out),
.D(axi_rid_temp[8]),
.Q(s_axi_rid[8]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_int_reg[9]
(.C(s_axi_aclk),
.CE(p_4_out),
.D(axi_rid_temp[9]),
.Q(s_axi_rid[9]),
.R(\GEN_RID.axi_rid_int[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hB8))
\GEN_RID.axi_rid_temp2[0]_i_1
(.I0(axi_arid_pipe[0]),
.I1(axi_araddr_full),
.I2(s_axi_arid[0]),
.O(axi_rid_temp20_in[0]));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hB8))
\GEN_RID.axi_rid_temp2[10]_i_1
(.I0(axi_arid_pipe[10]),
.I1(axi_araddr_full),
.I2(s_axi_arid[10]),
.O(axi_rid_temp20_in[10]));
LUT2 #(
.INIT(4'h8))
\GEN_RID.axi_rid_temp2[11]_i_1
(.I0(axi_rid_temp_full),
.I1(bram_addr_ld_en),
.O(p_26_out));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hB8))
\GEN_RID.axi_rid_temp2[11]_i_2
(.I0(axi_arid_pipe[11]),
.I1(axi_araddr_full),
.I2(s_axi_arid[11]),
.O(axi_rid_temp20_in[11]));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hB8))
\GEN_RID.axi_rid_temp2[1]_i_1
(.I0(axi_arid_pipe[1]),
.I1(axi_araddr_full),
.I2(s_axi_arid[1]),
.O(axi_rid_temp20_in[1]));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'hB8))
\GEN_RID.axi_rid_temp2[2]_i_1
(.I0(axi_arid_pipe[2]),
.I1(axi_araddr_full),
.I2(s_axi_arid[2]),
.O(axi_rid_temp20_in[2]));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'hB8))
\GEN_RID.axi_rid_temp2[3]_i_1
(.I0(axi_arid_pipe[3]),
.I1(axi_araddr_full),
.I2(s_axi_arid[3]),
.O(axi_rid_temp20_in[3]));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hB8))
\GEN_RID.axi_rid_temp2[4]_i_1
(.I0(axi_arid_pipe[4]),
.I1(axi_araddr_full),
.I2(s_axi_arid[4]),
.O(axi_rid_temp20_in[4]));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hB8))
\GEN_RID.axi_rid_temp2[5]_i_1
(.I0(axi_arid_pipe[5]),
.I1(axi_araddr_full),
.I2(s_axi_arid[5]),
.O(axi_rid_temp20_in[5]));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hB8))
\GEN_RID.axi_rid_temp2[6]_i_1
(.I0(axi_arid_pipe[6]),
.I1(axi_araddr_full),
.I2(s_axi_arid[6]),
.O(axi_rid_temp20_in[6]));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hB8))
\GEN_RID.axi_rid_temp2[7]_i_1
(.I0(axi_arid_pipe[7]),
.I1(axi_araddr_full),
.I2(s_axi_arid[7]),
.O(axi_rid_temp20_in[7]));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hB8))
\GEN_RID.axi_rid_temp2[8]_i_1
(.I0(axi_arid_pipe[8]),
.I1(axi_araddr_full),
.I2(s_axi_arid[8]),
.O(axi_rid_temp20_in[8]));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hB8))
\GEN_RID.axi_rid_temp2[9]_i_1
(.I0(axi_arid_pipe[9]),
.I1(axi_araddr_full),
.I2(s_axi_arid[9]),
.O(axi_rid_temp20_in[9]));
LUT6 #(
.INIT(64'h08080000C8C800C0))
\GEN_RID.axi_rid_temp2_full_i_1
(.I0(bram_addr_ld_en),
.I1(s_axi_aresetn),
.I2(axi_rid_temp2_full),
.I3(axi_rid_temp_full_d1),
.I4(axi_rid_temp_full),
.I5(p_4_out),
.O(\GEN_RID.axi_rid_temp2_full_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp2_full_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_RID.axi_rid_temp2_full_i_1_n_0 ),
.Q(axi_rid_temp2_full),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp2_reg[0]
(.C(s_axi_aclk),
.CE(p_26_out),
.D(axi_rid_temp20_in[0]),
.Q(axi_rid_temp2[0]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp2_reg[10]
(.C(s_axi_aclk),
.CE(p_26_out),
.D(axi_rid_temp20_in[10]),
.Q(axi_rid_temp2[10]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp2_reg[11]
(.C(s_axi_aclk),
.CE(p_26_out),
.D(axi_rid_temp20_in[11]),
.Q(axi_rid_temp2[11]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp2_reg[1]
(.C(s_axi_aclk),
.CE(p_26_out),
.D(axi_rid_temp20_in[1]),
.Q(axi_rid_temp2[1]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp2_reg[2]
(.C(s_axi_aclk),
.CE(p_26_out),
.D(axi_rid_temp20_in[2]),
.Q(axi_rid_temp2[2]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp2_reg[3]
(.C(s_axi_aclk),
.CE(p_26_out),
.D(axi_rid_temp20_in[3]),
.Q(axi_rid_temp2[3]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp2_reg[4]
(.C(s_axi_aclk),
.CE(p_26_out),
.D(axi_rid_temp20_in[4]),
.Q(axi_rid_temp2[4]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp2_reg[5]
(.C(s_axi_aclk),
.CE(p_26_out),
.D(axi_rid_temp20_in[5]),
.Q(axi_rid_temp2[5]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp2_reg[6]
(.C(s_axi_aclk),
.CE(p_26_out),
.D(axi_rid_temp20_in[6]),
.Q(axi_rid_temp2[6]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp2_reg[7]
(.C(s_axi_aclk),
.CE(p_26_out),
.D(axi_rid_temp20_in[7]),
.Q(axi_rid_temp2[7]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp2_reg[8]
(.C(s_axi_aclk),
.CE(p_26_out),
.D(axi_rid_temp20_in[8]),
.Q(axi_rid_temp2[8]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp2_reg[9]
(.C(s_axi_aclk),
.CE(p_26_out),
.D(axi_rid_temp20_in[9]),
.Q(axi_rid_temp2[9]),
.R(bram_rst_a));
LUT6 #(
.INIT(64'hFFFFB8FF0000B800))
\GEN_RID.axi_rid_temp[0]_i_1
(.I0(axi_arid_pipe[0]),
.I1(axi_araddr_full),
.I2(s_axi_arid[0]),
.I3(bram_addr_ld_en),
.I4(axi_rid_temp_full),
.I5(axi_rid_temp2[0]),
.O(\GEN_RID.axi_rid_temp[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFB8FF0000B800))
\GEN_RID.axi_rid_temp[10]_i_1
(.I0(axi_arid_pipe[10]),
.I1(axi_araddr_full),
.I2(s_axi_arid[10]),
.I3(bram_addr_ld_en),
.I4(axi_rid_temp_full),
.I5(axi_rid_temp2[10]),
.O(\GEN_RID.axi_rid_temp[10]_i_1_n_0 ));
LUT5 #(
.INIT(32'hA0FFA0E0))
\GEN_RID.axi_rid_temp[11]_i_1
(.I0(p_4_out),
.I1(axi_rid_temp_full_d1),
.I2(axi_rid_temp2_full),
.I3(axi_rid_temp_full),
.I4(bram_addr_ld_en),
.O(\GEN_RID.axi_rid_temp[11]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFB8FF0000B800))
\GEN_RID.axi_rid_temp[11]_i_2
(.I0(axi_arid_pipe[11]),
.I1(axi_araddr_full),
.I2(s_axi_arid[11]),
.I3(bram_addr_ld_en),
.I4(axi_rid_temp_full),
.I5(axi_rid_temp2[11]),
.O(\GEN_RID.axi_rid_temp[11]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFB8FF0000B800))
\GEN_RID.axi_rid_temp[1]_i_1
(.I0(axi_arid_pipe[1]),
.I1(axi_araddr_full),
.I2(s_axi_arid[1]),
.I3(bram_addr_ld_en),
.I4(axi_rid_temp_full),
.I5(axi_rid_temp2[1]),
.O(\GEN_RID.axi_rid_temp[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFB8FF0000B800))
\GEN_RID.axi_rid_temp[2]_i_1
(.I0(axi_arid_pipe[2]),
.I1(axi_araddr_full),
.I2(s_axi_arid[2]),
.I3(bram_addr_ld_en),
.I4(axi_rid_temp_full),
.I5(axi_rid_temp2[2]),
.O(\GEN_RID.axi_rid_temp[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFB8FF0000B800))
\GEN_RID.axi_rid_temp[3]_i_1
(.I0(axi_arid_pipe[3]),
.I1(axi_araddr_full),
.I2(s_axi_arid[3]),
.I3(bram_addr_ld_en),
.I4(axi_rid_temp_full),
.I5(axi_rid_temp2[3]),
.O(\GEN_RID.axi_rid_temp[3]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFB8FF0000B800))
\GEN_RID.axi_rid_temp[4]_i_1
(.I0(axi_arid_pipe[4]),
.I1(axi_araddr_full),
.I2(s_axi_arid[4]),
.I3(bram_addr_ld_en),
.I4(axi_rid_temp_full),
.I5(axi_rid_temp2[4]),
.O(\GEN_RID.axi_rid_temp[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFB8FF0000B800))
\GEN_RID.axi_rid_temp[5]_i_1
(.I0(axi_arid_pipe[5]),
.I1(axi_araddr_full),
.I2(s_axi_arid[5]),
.I3(bram_addr_ld_en),
.I4(axi_rid_temp_full),
.I5(axi_rid_temp2[5]),
.O(\GEN_RID.axi_rid_temp[5]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFB8FF0000B800))
\GEN_RID.axi_rid_temp[6]_i_1
(.I0(axi_arid_pipe[6]),
.I1(axi_araddr_full),
.I2(s_axi_arid[6]),
.I3(bram_addr_ld_en),
.I4(axi_rid_temp_full),
.I5(axi_rid_temp2[6]),
.O(\GEN_RID.axi_rid_temp[6]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFB8FF0000B800))
\GEN_RID.axi_rid_temp[7]_i_1
(.I0(axi_arid_pipe[7]),
.I1(axi_araddr_full),
.I2(s_axi_arid[7]),
.I3(bram_addr_ld_en),
.I4(axi_rid_temp_full),
.I5(axi_rid_temp2[7]),
.O(\GEN_RID.axi_rid_temp[7]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFB8FF0000B800))
\GEN_RID.axi_rid_temp[8]_i_1
(.I0(axi_arid_pipe[8]),
.I1(axi_araddr_full),
.I2(s_axi_arid[8]),
.I3(bram_addr_ld_en),
.I4(axi_rid_temp_full),
.I5(axi_rid_temp2[8]),
.O(\GEN_RID.axi_rid_temp[8]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFB8FF0000B800))
\GEN_RID.axi_rid_temp[9]_i_1
(.I0(axi_arid_pipe[9]),
.I1(axi_araddr_full),
.I2(s_axi_arid[9]),
.I3(bram_addr_ld_en),
.I4(axi_rid_temp_full),
.I5(axi_rid_temp2[9]),
.O(\GEN_RID.axi_rid_temp[9]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp_full_d1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_rid_temp_full),
.Q(axi_rid_temp_full_d1),
.R(bram_rst_a));
LUT6 #(
.INIT(64'hF0F0F0E000F0A0A0))
\GEN_RID.axi_rid_temp_full_i_1
(.I0(bram_addr_ld_en),
.I1(axi_rid_temp_full_d1),
.I2(s_axi_aresetn),
.I3(p_4_out),
.I4(axi_rid_temp_full),
.I5(axi_rid_temp2_full),
.O(\GEN_RID.axi_rid_temp_full_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp_full_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_RID.axi_rid_temp_full_i_1_n_0 ),
.Q(axi_rid_temp_full),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp_reg[0]
(.C(s_axi_aclk),
.CE(\GEN_RID.axi_rid_temp[11]_i_1_n_0 ),
.D(\GEN_RID.axi_rid_temp[0]_i_1_n_0 ),
.Q(axi_rid_temp[0]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp_reg[10]
(.C(s_axi_aclk),
.CE(\GEN_RID.axi_rid_temp[11]_i_1_n_0 ),
.D(\GEN_RID.axi_rid_temp[10]_i_1_n_0 ),
.Q(axi_rid_temp[10]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp_reg[11]
(.C(s_axi_aclk),
.CE(\GEN_RID.axi_rid_temp[11]_i_1_n_0 ),
.D(\GEN_RID.axi_rid_temp[11]_i_2_n_0 ),
.Q(axi_rid_temp[11]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp_reg[1]
(.C(s_axi_aclk),
.CE(\GEN_RID.axi_rid_temp[11]_i_1_n_0 ),
.D(\GEN_RID.axi_rid_temp[1]_i_1_n_0 ),
.Q(axi_rid_temp[1]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp_reg[2]
(.C(s_axi_aclk),
.CE(\GEN_RID.axi_rid_temp[11]_i_1_n_0 ),
.D(\GEN_RID.axi_rid_temp[2]_i_1_n_0 ),
.Q(axi_rid_temp[2]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp_reg[3]
(.C(s_axi_aclk),
.CE(\GEN_RID.axi_rid_temp[11]_i_1_n_0 ),
.D(\GEN_RID.axi_rid_temp[3]_i_1_n_0 ),
.Q(axi_rid_temp[3]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp_reg[4]
(.C(s_axi_aclk),
.CE(\GEN_RID.axi_rid_temp[11]_i_1_n_0 ),
.D(\GEN_RID.axi_rid_temp[4]_i_1_n_0 ),
.Q(axi_rid_temp[4]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp_reg[5]
(.C(s_axi_aclk),
.CE(\GEN_RID.axi_rid_temp[11]_i_1_n_0 ),
.D(\GEN_RID.axi_rid_temp[5]_i_1_n_0 ),
.Q(axi_rid_temp[5]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp_reg[6]
(.C(s_axi_aclk),
.CE(\GEN_RID.axi_rid_temp[11]_i_1_n_0 ),
.D(\GEN_RID.axi_rid_temp[6]_i_1_n_0 ),
.Q(axi_rid_temp[6]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp_reg[7]
(.C(s_axi_aclk),
.CE(\GEN_RID.axi_rid_temp[11]_i_1_n_0 ),
.D(\GEN_RID.axi_rid_temp[7]_i_1_n_0 ),
.Q(axi_rid_temp[7]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp_reg[8]
(.C(s_axi_aclk),
.CE(\GEN_RID.axi_rid_temp[11]_i_1_n_0 ),
.D(\GEN_RID.axi_rid_temp[8]_i_1_n_0 ),
.Q(axi_rid_temp[8]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp_reg[9]
(.C(s_axi_aclk),
.CE(\GEN_RID.axi_rid_temp[11]_i_1_n_0 ),
.D(\GEN_RID.axi_rid_temp[9]_i_1_n_0 ),
.Q(axi_rid_temp[9]),
.R(bram_rst_a));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wrap_brst_0 I_WRAP_BRST
(.D({I_WRAP_BRST_n_8,I_WRAP_BRST_n_9,I_WRAP_BRST_n_10,I_WRAP_BRST_n_11,I_WRAP_BRST_n_12,I_WRAP_BRST_n_13,I_WRAP_BRST_n_14,I_WRAP_BRST_n_15,I_WRAP_BRST_n_16,I_WRAP_BRST_n_17,I_WRAP_BRST_n_18,I_WRAP_BRST_n_19,I_WRAP_BRST_n_20,I_WRAP_BRST_n_21}),
.E({bram_addr_ld_en_mod,I_WRAP_BRST_n_6}),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg (\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg_n_0 ),
.\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11] (I_WRAP_BRST_n_7),
.\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0 (I_WRAP_BRST_n_25),
.\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 (Q[9:0]),
.\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] (I_WRAP_BRST_n_23),
.\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0 (\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2_n_0 ),
.\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] (\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4_n_0 ),
.Q(axi_arlen_pipe[3:0]),
.SR(bram_rst_a),
.ar_active(ar_active),
.axi_araddr_full(axi_araddr_full),
.axi_aresetn_d2(axi_aresetn_d2),
.axi_arlen_pipe_1_or_2(axi_arlen_pipe_1_or_2),
.axi_arsize_pipe(axi_arsize_pipe),
.axi_arsize_pipe_max(axi_arsize_pipe_max),
.axi_b2b_brst(axi_b2b_brst),
.axi_b2b_brst_reg(I_WRAP_BRST_n_27),
.axi_rd_burst(axi_rd_burst),
.axi_rd_burst_two_reg(axi_rd_burst_two_reg_n_0),
.axi_rvalid_int_reg(s_axi_rvalid),
.bram_addr_ld_en(bram_addr_ld_en),
.brst_zero(brst_zero),
.curr_fixed_burst_reg(curr_fixed_burst_reg),
.curr_wrap_burst_reg(curr_wrap_burst_reg),
.disable_b2b_brst(disable_b2b_brst),
.end_brst_rd(end_brst_rd),
.last_bram_addr(last_bram_addr),
.no_ar_ack(no_ar_ack),
.pend_rd_op(pend_rd_op),
.rd_addr_sm_cs(rd_addr_sm_cs),
.rd_adv_buf67_out(rd_adv_buf67_out),
.\rd_data_sm_cs_reg[1] (I_WRAP_BRST_n_24),
.\rd_data_sm_cs_reg[3] (I_WRAP_BRST_n_28),
.\rd_data_sm_cs_reg[3]_0 (rd_data_sm_cs),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arlen(s_axi_arlen[3:0]),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_rready(s_axi_rready),
.\save_init_bram_addr_ld_reg[15]_0 (I_WRAP_BRST_n_26),
.\wrap_burst_total_reg[0]_0 (I_WRAP_BRST_n_1),
.\wrap_burst_total_reg[0]_1 (I_WRAP_BRST_n_2),
.\wrap_burst_total_reg[0]_2 (I_WRAP_BRST_n_3),
.\wrap_burst_total_reg[0]_3 (I_WRAP_BRST_n_4));
LUT6 #(
.INIT(64'h000000002EEE22E2))
act_rd_burst_i_1
(.I0(act_rd_burst),
.I1(act_rd_burst_set),
.I2(bram_addr_ld_en),
.I3(axi_rd_burst_two),
.I4(axi_rd_burst),
.I5(act_rd_burst_i_3_n_0),
.O(act_rd_burst_i_1_n_0));
LUT6 #(
.INIT(64'hA8A8AAA8A8A8A8A8))
act_rd_burst_i_2
(.I0(pend_rd_op_i_6_n_0),
.I1(act_rd_burst_i_4_n_0),
.I2(axi_b2b_brst_i_3_n_0),
.I3(\rd_data_sm_cs[2]_i_4_n_0 ),
.I4(last_bram_addr_i_7_n_0),
.I5(bram_addr_ld_en),
.O(act_rd_burst_set));
LUT6 #(
.INIT(64'h04000010FFFFFFFF))
act_rd_burst_i_3
(.I0(\rd_data_sm_cs[3]_i_6_n_0 ),
.I1(rd_data_sm_cs[2]),
.I2(rd_data_sm_cs[3]),
.I3(rd_data_sm_cs[1]),
.I4(rd_data_sm_cs[0]),
.I5(s_axi_aresetn),
.O(act_rd_burst_i_3_n_0));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT4 #(
.INIT(16'h4440))
act_rd_burst_i_4
(.I0(rd_data_sm_cs[1]),
.I1(rd_data_sm_cs[0]),
.I2(axi_rd_burst),
.I3(axi_rd_burst_two_reg_n_0),
.O(act_rd_burst_i_4_n_0));
FDRE #(
.INIT(1'b0))
act_rd_burst_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(act_rd_burst_i_1_n_0),
.Q(act_rd_burst),
.R(1'b0));
LUT6 #(
.INIT(64'h00000000E2EEE222))
act_rd_burst_two_i_1
(.I0(act_rd_burst_two),
.I1(act_rd_burst_set),
.I2(axi_rd_burst_two),
.I3(bram_addr_ld_en),
.I4(axi_rd_burst_two_reg_n_0),
.I5(act_rd_burst_i_3_n_0),
.O(act_rd_burst_two_i_1_n_0));
FDRE #(
.INIT(1'b0))
act_rd_burst_two_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(act_rd_burst_two_i_1_n_0),
.Q(act_rd_burst_two),
.R(1'b0));
LUT2 #(
.INIT(4'hE))
axi_arsize_pipe_max_i_1
(.I0(araddr_pipe_ld43_out),
.I1(axi_arsize_pipe_max),
.O(axi_arsize_pipe_max_i_1_n_0));
FDRE #(
.INIT(1'b0))
axi_arsize_pipe_max_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_arsize_pipe_max_i_1_n_0),
.Q(axi_arsize_pipe_max),
.R(bram_rst_a));
LUT6 #(
.INIT(64'hCC0CCC55CC0CCCCC))
axi_b2b_brst_i_1
(.I0(I_WRAP_BRST_n_27),
.I1(axi_b2b_brst),
.I2(disable_b2b_brst_i_2_n_0),
.I3(rd_data_sm_cs[3]),
.I4(rd_data_sm_cs[2]),
.I5(axi_b2b_brst_i_3_n_0),
.O(axi_b2b_brst_i_1_n_0));
LUT6 #(
.INIT(64'h0000000088880080))
axi_b2b_brst_i_3
(.I0(\rd_data_sm_cs[0]_i_3_n_0 ),
.I1(rd_adv_buf67_out),
.I2(end_brst_rd),
.I3(axi_b2b_brst),
.I4(brst_zero),
.I5(I_WRAP_BRST_n_27),
.O(axi_b2b_brst_i_3_n_0));
FDRE #(
.INIT(1'b0))
axi_b2b_brst_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_b2b_brst_i_1_n_0),
.Q(axi_b2b_brst),
.R(bram_rst_a));
LUT5 #(
.INIT(32'h303000A0))
axi_rd_burst_i_1
(.I0(axi_rd_burst),
.I1(axi_rd_burst_i_2_n_0),
.I2(s_axi_aresetn),
.I3(brst_zero),
.I4(bram_addr_ld_en),
.O(axi_rd_burst_i_1_n_0));
LUT6 #(
.INIT(64'h0000000000000004))
axi_rd_burst_i_2
(.I0(\brst_cnt[6]_i_2_n_0 ),
.I1(axi_rd_burst_i_3_n_0),
.I2(I_WRAP_BRST_n_3),
.I3(\brst_cnt[7]_i_3_n_0 ),
.I4(I_WRAP_BRST_n_2),
.I5(I_WRAP_BRST_n_1),
.O(axi_rd_burst_i_2_n_0));
LUT5 #(
.INIT(32'h00053305))
axi_rd_burst_i_3
(.I0(s_axi_arlen[5]),
.I1(axi_arlen_pipe[5]),
.I2(s_axi_arlen[4]),
.I3(axi_araddr_full),
.I4(axi_arlen_pipe[4]),
.O(axi_rd_burst_i_3_n_0));
FDRE #(
.INIT(1'b0))
axi_rd_burst_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_rd_burst_i_1_n_0),
.Q(axi_rd_burst),
.R(1'b0));
LUT5 #(
.INIT(32'hC0C000A0))
axi_rd_burst_two_i_1
(.I0(axi_rd_burst_two_reg_n_0),
.I1(axi_rd_burst_two),
.I2(s_axi_aresetn),
.I3(brst_zero),
.I4(bram_addr_ld_en),
.O(axi_rd_burst_two_i_1_n_0));
LUT4 #(
.INIT(16'hA808))
axi_rd_burst_two_i_2
(.I0(axi_rd_burst_i_2_n_0),
.I1(s_axi_arlen[0]),
.I2(axi_araddr_full),
.I3(axi_arlen_pipe[0]),
.O(axi_rd_burst_two));
FDRE #(
.INIT(1'b0))
axi_rd_burst_two_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_rd_burst_two_i_1_n_0),
.Q(axi_rd_burst_two_reg_n_0),
.R(1'b0));
LUT4 #(
.INIT(16'h88A8))
axi_rlast_int_i_1
(.I0(s_axi_aresetn),
.I1(axi_rlast_set),
.I2(s_axi_rlast),
.I3(s_axi_rready),
.O(axi_rlast_int_i_1_n_0));
FDRE #(
.INIT(1'b0))
axi_rlast_int_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_rlast_int_i_1_n_0),
.Q(s_axi_rlast),
.R(1'b0));
LUT6 #(
.INIT(64'h00000000FFFFEEEA))
axi_rvalid_clr_ok_i_1
(.I0(axi_rvalid_clr_ok),
.I1(last_bram_addr),
.I2(disable_b2b_brst),
.I3(disable_b2b_brst_cmb),
.I4(axi_rvalid_clr_ok_i_2_n_0),
.I5(axi_rvalid_clr_ok_i_3_n_0),
.O(axi_rvalid_clr_ok_i_1_n_0));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT5 #(
.INIT(32'hAAAABAAA))
axi_rvalid_clr_ok_i_2
(.I0(bram_addr_ld_en),
.I1(rd_data_sm_cs[3]),
.I2(rd_data_sm_cs[2]),
.I3(rd_data_sm_cs[0]),
.I4(rd_data_sm_cs[1]),
.O(axi_rvalid_clr_ok_i_2_n_0));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT3 #(
.INIT(8'h4F))
axi_rvalid_clr_ok_i_3
(.I0(I_WRAP_BRST_n_26),
.I1(bram_addr_ld_en),
.I2(s_axi_aresetn),
.O(axi_rvalid_clr_ok_i_3_n_0));
FDRE #(
.INIT(1'b0))
axi_rvalid_clr_ok_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_rvalid_clr_ok_i_1_n_0),
.Q(axi_rvalid_clr_ok),
.R(1'b0));
LUT6 #(
.INIT(64'h00E0E0E0E0E0E0E0))
axi_rvalid_int_i_1
(.I0(s_axi_rvalid),
.I1(axi_rvalid_set),
.I2(s_axi_aresetn),
.I3(axi_rvalid_clr_ok),
.I4(s_axi_rlast),
.I5(s_axi_rready),
.O(axi_rvalid_int_i_1_n_0));
FDRE #(
.INIT(1'b0))
axi_rvalid_int_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_rvalid_int_i_1_n_0),
.Q(s_axi_rvalid),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT4 #(
.INIT(16'h0100))
axi_rvalid_set_i_1
(.I0(rd_data_sm_cs[2]),
.I1(rd_data_sm_cs[3]),
.I2(rd_data_sm_cs[1]),
.I3(rd_data_sm_cs[0]),
.O(axi_rvalid_set_cmb));
FDRE #(
.INIT(1'b0))
axi_rvalid_set_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_rvalid_set_cmb),
.Q(axi_rvalid_set),
.R(bram_rst_a));
LUT6 #(
.INIT(64'hEEEEFFFEEEEE000E))
bram_en_int_i_1
(.I0(bram_en_int_i_2_n_0),
.I1(bram_en_int_i_3_n_0),
.I2(bram_en_int_i_4_n_0),
.I3(I_WRAP_BRST_n_28),
.I4(bram_en_int_i_6_n_0),
.I5(bram_en_b),
.O(bram_en_int_i_1_n_0));
LUT6 #(
.INIT(64'hFFFF777FFFFFFFFF))
bram_en_int_i_10
(.I0(s_axi_rvalid),
.I1(s_axi_rready),
.I2(act_rd_burst),
.I3(act_rd_burst_two),
.I4(rd_data_sm_cs[1]),
.I5(rd_data_sm_cs[0]),
.O(bram_en_int_i_10_n_0));
LUT6 #(
.INIT(64'hD0D000F0D0D0F0F0))
bram_en_int_i_11
(.I0(\rd_data_sm_cs[3]_i_7_n_0 ),
.I1(I_WRAP_BRST_n_27),
.I2(rd_data_sm_cs[1]),
.I3(brst_one),
.I4(rd_adv_buf67_out),
.I5(\rd_data_sm_cs[2]_i_5_n_0 ),
.O(bram_en_int_i_11_n_0));
LUT6 #(
.INIT(64'h00000000FDF50000))
bram_en_int_i_2
(.I0(rd_data_sm_cs[2]),
.I1(pend_rd_op),
.I2(bram_addr_ld_en),
.I3(rd_adv_buf67_out),
.I4(rd_data_sm_cs[1]),
.I5(bram_en_int_i_7_n_0),
.O(bram_en_int_i_2_n_0));
LUT6 #(
.INIT(64'hAAAAEEAFAAAAAAEE))
bram_en_int_i_3
(.I0(I_WRAP_BRST_n_25),
.I1(bram_addr_ld_en),
.I2(p_0_in13_in),
.I3(rd_data_sm_cs[2]),
.I4(rd_data_sm_cs[1]),
.I5(rd_data_sm_cs[0]),
.O(bram_en_int_i_3_n_0));
LUT6 #(
.INIT(64'h000F007F0000007F))
bram_en_int_i_4
(.I0(pend_rd_op),
.I1(rd_adv_buf67_out),
.I2(\rd_data_sm_cs[0]_i_3_n_0 ),
.I3(bram_en_int_i_9_n_0),
.I4(bram_addr_ld_en),
.I5(bram_en_int_i_10_n_0),
.O(bram_en_int_i_4_n_0));
LUT6 #(
.INIT(64'h1010111111111110))
bram_en_int_i_6
(.I0(rd_data_sm_cs[2]),
.I1(rd_data_sm_cs[3]),
.I2(bram_en_int_i_11_n_0),
.I3(bram_addr_ld_en),
.I4(rd_data_sm_cs[1]),
.I5(rd_data_sm_cs[0]),
.O(bram_en_int_i_6_n_0));
LUT6 #(
.INIT(64'h5500050544444444))
bram_en_int_i_7
(.I0(rd_data_sm_cs[2]),
.I1(axi_rd_burst_two_reg_n_0),
.I2(\rd_data_sm_cs[2]_i_5_n_0 ),
.I3(\rd_data_sm_cs[3]_i_7_n_0 ),
.I4(rd_adv_buf67_out),
.I5(rd_data_sm_cs[0]),
.O(bram_en_int_i_7_n_0));
LUT6 #(
.INIT(64'h1111111111111000))
bram_en_int_i_9
(.I0(rd_data_sm_cs[0]),
.I1(rd_data_sm_cs[1]),
.I2(s_axi_rvalid),
.I3(s_axi_rready),
.I4(brst_zero),
.I5(end_brst_rd),
.O(bram_en_int_i_9_n_0));
FDRE #(
.INIT(1'b0))
bram_en_int_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(bram_en_int_i_1_n_0),
.Q(bram_en_b),
.R(bram_rst_a));
LUT5 #(
.INIT(32'hD1DDD111))
\brst_cnt[0]_i_1
(.I0(brst_cnt[0]),
.I1(bram_addr_ld_en),
.I2(axi_arlen_pipe[0]),
.I3(axi_araddr_full),
.I4(s_axi_arlen[0]),
.O(\brst_cnt[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hB8FFB800B800B8FF))
\brst_cnt[1]_i_1
(.I0(axi_arlen_pipe[1]),
.I1(axi_araddr_full),
.I2(s_axi_arlen[1]),
.I3(bram_addr_ld_en),
.I4(brst_cnt[0]),
.I5(brst_cnt[1]),
.O(\brst_cnt[1]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8B8B88B))
\brst_cnt[2]_i_1
(.I0(I_WRAP_BRST_n_1),
.I1(bram_addr_ld_en),
.I2(brst_cnt[2]),
.I3(brst_cnt[1]),
.I4(brst_cnt[0]),
.O(\brst_cnt[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'hB8B8B8B8B8B8B88B))
\brst_cnt[3]_i_1
(.I0(I_WRAP_BRST_n_2),
.I1(bram_addr_ld_en),
.I2(brst_cnt[3]),
.I3(brst_cnt[2]),
.I4(brst_cnt[0]),
.I5(brst_cnt[1]),
.O(\brst_cnt[3]_i_1_n_0 ));
LUT6 #(
.INIT(64'hB800B8FFB8FFB800))
\brst_cnt[4]_i_1
(.I0(axi_arlen_pipe[4]),
.I1(axi_araddr_full),
.I2(s_axi_arlen[4]),
.I3(bram_addr_ld_en),
.I4(brst_cnt[4]),
.I5(\brst_cnt[4]_i_2_n_0 ),
.O(\brst_cnt[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT4 #(
.INIT(16'h0001))
\brst_cnt[4]_i_2
(.I0(brst_cnt[2]),
.I1(brst_cnt[0]),
.I2(brst_cnt[1]),
.I3(brst_cnt[3]),
.O(\brst_cnt[4]_i_2_n_0 ));
LUT6 #(
.INIT(64'hB800B8FFB8FFB800))
\brst_cnt[5]_i_1
(.I0(axi_arlen_pipe[5]),
.I1(axi_araddr_full),
.I2(s_axi_arlen[5]),
.I3(bram_addr_ld_en),
.I4(brst_cnt[5]),
.I5(\brst_cnt[7]_i_4_n_0 ),
.O(\brst_cnt[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT5 #(
.INIT(32'hB88BB8B8))
\brst_cnt[6]_i_1
(.I0(\brst_cnt[6]_i_2_n_0 ),
.I1(bram_addr_ld_en),
.I2(brst_cnt[6]),
.I3(brst_cnt[5]),
.I4(\brst_cnt[7]_i_4_n_0 ),
.O(\brst_cnt[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'hB8))
\brst_cnt[6]_i_2
(.I0(axi_arlen_pipe[6]),
.I1(axi_araddr_full),
.I2(s_axi_arlen[6]),
.O(\brst_cnt[6]_i_2_n_0 ));
LUT2 #(
.INIT(4'hE))
\brst_cnt[7]_i_1
(.I0(bram_addr_ld_en),
.I1(I_WRAP_BRST_n_7),
.O(\brst_cnt[7]_i_1_n_0 ));
LUT6 #(
.INIT(64'hB8B8B88BB8B8B8B8))
\brst_cnt[7]_i_2
(.I0(\brst_cnt[7]_i_3_n_0 ),
.I1(bram_addr_ld_en),
.I2(brst_cnt[7]),
.I3(brst_cnt[6]),
.I4(brst_cnt[5]),
.I5(\brst_cnt[7]_i_4_n_0 ),
.O(\brst_cnt[7]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'hB8))
\brst_cnt[7]_i_3
(.I0(axi_arlen_pipe[7]),
.I1(axi_araddr_full),
.I2(s_axi_arlen[7]),
.O(\brst_cnt[7]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT5 #(
.INIT(32'h00000001))
\brst_cnt[7]_i_4
(.I0(brst_cnt[3]),
.I1(brst_cnt[1]),
.I2(brst_cnt[0]),
.I3(brst_cnt[2]),
.I4(brst_cnt[4]),
.O(\brst_cnt[7]_i_4_n_0 ));
FDRE #(
.INIT(1'b0))
brst_cnt_max_d1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(brst_cnt_max),
.Q(brst_cnt_max_d1),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\brst_cnt_reg[0]
(.C(s_axi_aclk),
.CE(\brst_cnt[7]_i_1_n_0 ),
.D(\brst_cnt[0]_i_1_n_0 ),
.Q(brst_cnt[0]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\brst_cnt_reg[1]
(.C(s_axi_aclk),
.CE(\brst_cnt[7]_i_1_n_0 ),
.D(\brst_cnt[1]_i_1_n_0 ),
.Q(brst_cnt[1]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\brst_cnt_reg[2]
(.C(s_axi_aclk),
.CE(\brst_cnt[7]_i_1_n_0 ),
.D(\brst_cnt[2]_i_1_n_0 ),
.Q(brst_cnt[2]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\brst_cnt_reg[3]
(.C(s_axi_aclk),
.CE(\brst_cnt[7]_i_1_n_0 ),
.D(\brst_cnt[3]_i_1_n_0 ),
.Q(brst_cnt[3]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\brst_cnt_reg[4]
(.C(s_axi_aclk),
.CE(\brst_cnt[7]_i_1_n_0 ),
.D(\brst_cnt[4]_i_1_n_0 ),
.Q(brst_cnt[4]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\brst_cnt_reg[5]
(.C(s_axi_aclk),
.CE(\brst_cnt[7]_i_1_n_0 ),
.D(\brst_cnt[5]_i_1_n_0 ),
.Q(brst_cnt[5]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\brst_cnt_reg[6]
(.C(s_axi_aclk),
.CE(\brst_cnt[7]_i_1_n_0 ),
.D(\brst_cnt[6]_i_1_n_0 ),
.Q(brst_cnt[6]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\brst_cnt_reg[7]
(.C(s_axi_aclk),
.CE(\brst_cnt[7]_i_1_n_0 ),
.D(\brst_cnt[7]_i_2_n_0 ),
.Q(brst_cnt[7]),
.R(bram_rst_a));
LUT6 #(
.INIT(64'h00000000E0EE0000))
brst_one_i_1
(.I0(brst_one),
.I1(brst_one0),
.I2(axi_rd_burst_two),
.I3(bram_addr_ld_en),
.I4(s_axi_aresetn),
.I5(last_bram_addr_i_6_n_0),
.O(brst_one_i_1_n_0));
LUT6 #(
.INIT(64'h80FF808080808080))
brst_one_i_2
(.I0(bram_addr_ld_en),
.I1(I_WRAP_BRST_n_4),
.I2(axi_rd_burst_i_2_n_0),
.I3(brst_cnt[0]),
.I4(brst_cnt[1]),
.I5(last_bram_addr_i_8_n_0),
.O(brst_one0));
FDRE #(
.INIT(1'b0))
brst_one_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(brst_one_i_1_n_0),
.Q(brst_one),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT4 #(
.INIT(16'h00E0))
brst_zero_i_1
(.I0(brst_zero),
.I1(last_bram_addr_i_6_n_0),
.I2(s_axi_aresetn),
.I3(brst_zero_i_2_n_0),
.O(brst_zero_i_1_n_0));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT5 #(
.INIT(32'h8A80AAAA))
brst_zero_i_2
(.I0(bram_addr_ld_en),
.I1(axi_arlen_pipe[0]),
.I2(axi_araddr_full),
.I3(s_axi_arlen[0]),
.I4(axi_rd_burst_i_2_n_0),
.O(brst_zero_i_2_n_0));
FDRE #(
.INIT(1'b0))
brst_zero_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(brst_zero_i_1_n_0),
.Q(brst_zero),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT5 #(
.INIT(32'h00053305))
curr_fixed_burst_reg_i_1
(.I0(s_axi_arburst[0]),
.I1(axi_arburst_pipe[0]),
.I2(s_axi_arburst[1]),
.I3(axi_araddr_full),
.I4(axi_arburst_pipe[1]),
.O(curr_fixed_burst));
FDRE #(
.INIT(1'b0))
curr_fixed_burst_reg_reg
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(curr_fixed_burst),
.Q(curr_fixed_burst_reg),
.R(bram_rst_a));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT5 #(
.INIT(32'h000ACC0A))
curr_wrap_burst_reg_i_1
(.I0(s_axi_arburst[1]),
.I1(axi_arburst_pipe[1]),
.I2(s_axi_arburst[0]),
.I3(axi_araddr_full),
.I4(axi_arburst_pipe[0]),
.O(curr_wrap_burst));
FDRE #(
.INIT(1'b0))
curr_wrap_burst_reg_reg
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(curr_wrap_burst),
.Q(curr_wrap_burst_reg),
.R(bram_rst_a));
LUT6 #(
.INIT(64'hFFFFFFFF000D0000))
disable_b2b_brst_i_1
(.I0(axi_rd_burst),
.I1(axi_rd_burst_two_reg_n_0),
.I2(rd_data_sm_cs[2]),
.I3(rd_data_sm_cs[3]),
.I4(disable_b2b_brst_i_2_n_0),
.I5(disable_b2b_brst_i_3_n_0),
.O(disable_b2b_brst_cmb));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT2 #(
.INIT(4'h2))
disable_b2b_brst_i_2
(.I0(rd_data_sm_cs[0]),
.I1(rd_data_sm_cs[1]),
.O(disable_b2b_brst_i_2_n_0));
LUT6 #(
.INIT(64'hF6EF0000F6EFF6EF))
disable_b2b_brst_i_3
(.I0(rd_data_sm_cs[2]),
.I1(rd_data_sm_cs[1]),
.I2(rd_data_sm_cs[3]),
.I3(rd_data_sm_cs[0]),
.I4(disable_b2b_brst),
.I5(disable_b2b_brst_i_4_n_0),
.O(disable_b2b_brst_i_3_n_0));
LUT6 #(
.INIT(64'hDFDFDFDFDFDFDFFF))
disable_b2b_brst_i_4
(.I0(pend_rd_op_i_6_n_0),
.I1(rd_adv_buf67_out),
.I2(rd_data_sm_cs[0]),
.I3(brst_zero),
.I4(end_brst_rd),
.I5(brst_one),
.O(disable_b2b_brst_i_4_n_0));
FDRE #(
.INIT(1'b0))
disable_b2b_brst_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(disable_b2b_brst_cmb),
.Q(disable_b2b_brst),
.R(bram_rst_a));
LUT6 #(
.INIT(64'hFEFEFEFF10100000))
end_brst_rd_clr_i_1
(.I0(rd_data_sm_cs[3]),
.I1(rd_data_sm_cs[1]),
.I2(rd_data_sm_cs[2]),
.I3(bram_addr_ld_en),
.I4(rd_data_sm_cs[0]),
.I5(end_brst_rd_clr),
.O(end_brst_rd_clr_i_1_n_0));
FDRE #(
.INIT(1'b0))
end_brst_rd_clr_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(end_brst_rd_clr_i_1_n_0),
.Q(end_brst_rd_clr),
.R(bram_rst_a));
LUT5 #(
.INIT(32'h0020F020))
end_brst_rd_i_1
(.I0(brst_cnt_max),
.I1(brst_cnt_max_d1),
.I2(s_axi_aresetn),
.I3(end_brst_rd),
.I4(end_brst_rd_clr),
.O(end_brst_rd_i_1_n_0));
FDRE #(
.INIT(1'b0))
end_brst_rd_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(end_brst_rd_i_1_n_0),
.Q(end_brst_rd),
.R(1'b0));
LUT6 #(
.INIT(64'hFFFFFFFF1F110000))
last_bram_addr_i_1
(.I0(last_bram_addr_i_2_n_0),
.I1(rd_data_sm_cs[2]),
.I2(last_bram_addr_i_3_n_0),
.I3(last_bram_addr_i_4_n_0),
.I4(last_bram_addr_i_5_n_0),
.I5(last_bram_addr_i_6_n_0),
.O(last_bram_addr0));
LUT6 #(
.INIT(64'hEF00EFFFEFFFEFFF))
last_bram_addr_i_2
(.I0(axi_rd_burst),
.I1(axi_rd_burst_two_reg_n_0),
.I2(rd_adv_buf67_out),
.I3(rd_data_sm_cs[3]),
.I4(bram_addr_ld_en),
.I5(last_bram_addr_i_7_n_0),
.O(last_bram_addr_i_2_n_0));
LUT6 #(
.INIT(64'hDDDDDDDDFFFCFFFF))
last_bram_addr_i_3
(.I0(last_bram_addr_i_7_n_0),
.I1(I_WRAP_BRST_n_28),
.I2(axi_rd_burst),
.I3(axi_rd_burst_two_reg_n_0),
.I4(pend_rd_op),
.I5(bram_addr_ld_en),
.O(last_bram_addr_i_3_n_0));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT4 #(
.INIT(16'h8880))
last_bram_addr_i_4
(.I0(s_axi_rready),
.I1(s_axi_rvalid),
.I2(bram_addr_ld_en),
.I3(pend_rd_op),
.O(last_bram_addr_i_4_n_0));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT3 #(
.INIT(8'h81))
last_bram_addr_i_5
(.I0(rd_data_sm_cs[2]),
.I1(rd_data_sm_cs[1]),
.I2(rd_data_sm_cs[0]),
.O(last_bram_addr_i_5_n_0));
LUT3 #(
.INIT(8'h08))
last_bram_addr_i_6
(.I0(last_bram_addr_i_8_n_0),
.I1(brst_cnt[0]),
.I2(brst_cnt[1]),
.O(last_bram_addr_i_6_n_0));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT4 #(
.INIT(16'h02A2))
last_bram_addr_i_7
(.I0(axi_rd_burst_i_2_n_0),
.I1(s_axi_arlen[0]),
.I2(axi_araddr_full),
.I3(axi_arlen_pipe[0]),
.O(last_bram_addr_i_7_n_0));
LUT6 #(
.INIT(64'h0000000000000002))
last_bram_addr_i_8
(.I0(I_WRAP_BRST_n_7),
.I1(last_bram_addr_i_9_n_0),
.I2(brst_cnt[3]),
.I3(brst_cnt[2]),
.I4(brst_cnt[4]),
.I5(brst_cnt[7]),
.O(last_bram_addr_i_8_n_0));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT2 #(
.INIT(4'hE))
last_bram_addr_i_9
(.I0(brst_cnt[6]),
.I1(brst_cnt[5]),
.O(last_bram_addr_i_9_n_0));
FDRE #(
.INIT(1'b0))
last_bram_addr_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(last_bram_addr0),
.Q(last_bram_addr),
.R(bram_rst_a));
LUT6 #(
.INIT(64'hAAAAAAAA88C8AAAA))
no_ar_ack_i_1
(.I0(no_ar_ack),
.I1(rd_data_sm_cs[1]),
.I2(bram_addr_ld_en),
.I3(rd_adv_buf67_out),
.I4(rd_data_sm_cs[0]),
.I5(I_WRAP_BRST_n_28),
.O(no_ar_ack_i_1_n_0));
FDRE #(
.INIT(1'b0))
no_ar_ack_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(no_ar_ack_i_1_n_0),
.Q(no_ar_ack),
.R(bram_rst_a));
LUT6 #(
.INIT(64'hEFAAEFEF20AA2020))
pend_rd_op_i_1
(.I0(pend_rd_op_i_2_n_0),
.I1(pend_rd_op_i_3_n_0),
.I2(pend_rd_op_i_4_n_0),
.I3(pend_rd_op_i_5_n_0),
.I4(pend_rd_op_i_6_n_0),
.I5(pend_rd_op),
.O(pend_rd_op_i_1_n_0));
LUT6 #(
.INIT(64'h0FFCC8C80CCCC8C8))
pend_rd_op_i_2
(.I0(p_0_in13_in),
.I1(bram_addr_ld_en),
.I2(rd_data_sm_cs[1]),
.I3(rd_data_sm_cs[0]),
.I4(rd_data_sm_cs[2]),
.I5(pend_rd_op_i_7_n_0),
.O(pend_rd_op_i_2_n_0));
LUT6 #(
.INIT(64'hFFFFFFFF00030005))
pend_rd_op_i_3
(.I0(pend_rd_op_i_8_n_0),
.I1(pend_rd_op_i_7_n_0),
.I2(bram_addr_ld_en),
.I3(rd_data_sm_cs[1]),
.I4(rd_data_sm_cs[0]),
.I5(I_WRAP_BRST_n_28),
.O(pend_rd_op_i_3_n_0));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT5 #(
.INIT(32'hFFFF00EA))
pend_rd_op_i_4
(.I0(bram_addr_ld_en),
.I1(end_brst_rd),
.I2(ar_active),
.I3(rd_data_sm_cs[0]),
.I4(pend_rd_op_i_9_n_0),
.O(pend_rd_op_i_4_n_0));
LUT6 #(
.INIT(64'h0303070733F3FFFF))
pend_rd_op_i_5
(.I0(p_0_in13_in),
.I1(rd_data_sm_cs[0]),
.I2(rd_data_sm_cs[1]),
.I3(s_axi_rlast),
.I4(pend_rd_op),
.I5(bram_addr_ld_en),
.O(pend_rd_op_i_5_n_0));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT2 #(
.INIT(4'h1))
pend_rd_op_i_6
(.I0(rd_data_sm_cs[3]),
.I1(rd_data_sm_cs[2]),
.O(pend_rd_op_i_6_n_0));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h8))
pend_rd_op_i_7
(.I0(ar_active),
.I1(end_brst_rd),
.O(pend_rd_op_i_7_n_0));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT2 #(
.INIT(4'h8))
pend_rd_op_i_8
(.I0(pend_rd_op),
.I1(s_axi_rlast),
.O(pend_rd_op_i_8_n_0));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT5 #(
.INIT(32'h8000FFFF))
pend_rd_op_i_9
(.I0(pend_rd_op),
.I1(s_axi_rready),
.I2(s_axi_rvalid),
.I3(rd_data_sm_cs[0]),
.I4(rd_data_sm_cs[1]),
.O(pend_rd_op_i_9_n_0));
FDRE #(
.INIT(1'b0))
pend_rd_op_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(pend_rd_op_i_1_n_0),
.Q(pend_rd_op),
.R(bram_rst_a));
LUT6 #(
.INIT(64'hFFFFFFFF54005555))
\rd_data_sm_cs[0]_i_1
(.I0(\rd_data_sm_cs[0]_i_2_n_0 ),
.I1(pend_rd_op),
.I2(bram_addr_ld_en),
.I3(rd_adv_buf67_out),
.I4(\rd_data_sm_cs[0]_i_3_n_0 ),
.I5(\rd_data_sm_cs[0]_i_4_n_0 ),
.O(\rd_data_sm_cs[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFEAAAAAAFEAAFEAA))
\rd_data_sm_cs[0]_i_2
(.I0(I_WRAP_BRST_n_28),
.I1(act_rd_burst_two),
.I2(act_rd_burst),
.I3(disable_b2b_brst_i_2_n_0),
.I4(bram_addr_ld_en),
.I5(rd_adv_buf67_out),
.O(\rd_data_sm_cs[0]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT2 #(
.INIT(4'h8))
\rd_data_sm_cs[0]_i_3
(.I0(rd_data_sm_cs[1]),
.I1(rd_data_sm_cs[0]),
.O(\rd_data_sm_cs[0]_i_3_n_0 ));
LUT6 #(
.INIT(64'h000300BF0003008F))
\rd_data_sm_cs[0]_i_4
(.I0(rd_adv_buf67_out),
.I1(rd_data_sm_cs[1]),
.I2(rd_data_sm_cs[0]),
.I3(rd_data_sm_cs[2]),
.I4(rd_data_sm_cs[3]),
.I5(p_0_in13_in),
.O(\rd_data_sm_cs[0]_i_4_n_0 ));
LUT6 #(
.INIT(64'hAABAAABAFFFFAABA))
\rd_data_sm_cs[1]_i_1
(.I0(\rd_data_sm_cs[2]_i_2_n_0 ),
.I1(I_WRAP_BRST_n_28),
.I2(\rd_data_sm_cs[2]_i_5_n_0 ),
.I3(rd_data_sm_cs[0]),
.I4(I_WRAP_BRST_n_24),
.I5(\rd_data_sm_cs[1]_i_3_n_0 ),
.O(\rd_data_sm_cs[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'hC0CCCCCC88888888))
\rd_data_sm_cs[1]_i_3
(.I0(axi_rd_burst_two_reg_n_0),
.I1(rd_data_sm_cs[1]),
.I2(I_WRAP_BRST_n_27),
.I3(s_axi_rready),
.I4(s_axi_rvalid),
.I5(rd_data_sm_cs[0]),
.O(\rd_data_sm_cs[1]_i_3_n_0 ));
LUT6 #(
.INIT(64'hAAABAAABAEAFAAAB))
\rd_data_sm_cs[2]_i_1
(.I0(\rd_data_sm_cs[2]_i_2_n_0 ),
.I1(rd_data_sm_cs[2]),
.I2(rd_data_sm_cs[3]),
.I3(\rd_data_sm_cs[2]_i_3_n_0 ),
.I4(\rd_data_sm_cs[2]_i_4_n_0 ),
.I5(\rd_data_sm_cs[2]_i_5_n_0 ),
.O(\rd_data_sm_cs[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'h000000000DF00000))
\rd_data_sm_cs[2]_i_2
(.I0(bram_addr_ld_en),
.I1(\rd_data_sm_cs[3]_i_6_n_0 ),
.I2(rd_data_sm_cs[1]),
.I3(rd_data_sm_cs[0]),
.I4(rd_data_sm_cs[2]),
.I5(rd_data_sm_cs[3]),
.O(\rd_data_sm_cs[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'h00C0FFFF33F3BBBB))
\rd_data_sm_cs[2]_i_3
(.I0(axi_rd_burst),
.I1(rd_data_sm_cs[0]),
.I2(rd_adv_buf67_out),
.I3(I_WRAP_BRST_n_27),
.I4(rd_data_sm_cs[1]),
.I5(axi_rd_burst_two_reg_n_0),
.O(\rd_data_sm_cs[2]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT2 #(
.INIT(4'h1))
\rd_data_sm_cs[2]_i_4
(.I0(rd_data_sm_cs[1]),
.I1(rd_data_sm_cs[0]),
.O(\rd_data_sm_cs[2]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT2 #(
.INIT(4'h1))
\rd_data_sm_cs[2]_i_5
(.I0(brst_zero),
.I1(end_brst_rd),
.O(\rd_data_sm_cs[2]_i_5_n_0 ));
LUT6 #(
.INIT(64'h8F80FF8F8F80F080))
\rd_data_sm_cs[3]_i_1
(.I0(s_axi_rready),
.I1(s_axi_rvalid),
.I2(\rd_data_sm_cs[3]_i_3_n_0 ),
.I3(bram_addr_ld_en),
.I4(\rd_data_sm_cs[3]_i_4_n_0 ),
.I5(\rd_data_sm_cs[3]_i_5_n_0 ),
.O(rd_data_sm_ns));
LUT6 #(
.INIT(64'h0000004050005040))
\rd_data_sm_cs[3]_i_2
(.I0(I_WRAP_BRST_n_28),
.I1(bram_addr_ld_en),
.I2(rd_data_sm_cs[0]),
.I3(rd_data_sm_cs[1]),
.I4(\rd_data_sm_cs[3]_i_6_n_0 ),
.I5(rd_adv_buf67_out),
.O(\rd_data_sm_cs[3]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT4 #(
.INIT(16'h4052))
\rd_data_sm_cs[3]_i_3
(.I0(rd_data_sm_cs[3]),
.I1(rd_data_sm_cs[1]),
.I2(rd_data_sm_cs[2]),
.I3(rd_data_sm_cs[0]),
.O(\rd_data_sm_cs[3]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT4 #(
.INIT(16'h0035))
\rd_data_sm_cs[3]_i_4
(.I0(rd_data_sm_cs[1]),
.I1(rd_data_sm_cs[3]),
.I2(rd_data_sm_cs[2]),
.I3(rd_data_sm_cs[0]),
.O(\rd_data_sm_cs[3]_i_4_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFF5EFFFF))
\rd_data_sm_cs[3]_i_5
(.I0(rd_data_sm_cs[0]),
.I1(rd_data_sm_cs[2]),
.I2(rd_data_sm_cs[1]),
.I3(rd_data_sm_cs[3]),
.I4(rd_adv_buf67_out),
.I5(\rd_data_sm_cs[3]_i_7_n_0 ),
.O(\rd_data_sm_cs[3]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT4 #(
.INIT(16'h1FFF))
\rd_data_sm_cs[3]_i_6
(.I0(act_rd_burst_two),
.I1(act_rd_burst),
.I2(s_axi_rready),
.I3(s_axi_rvalid),
.O(\rd_data_sm_cs[3]_i_6_n_0 ));
LUT3 #(
.INIT(8'hBA))
\rd_data_sm_cs[3]_i_7
(.I0(brst_zero),
.I1(axi_b2b_brst),
.I2(end_brst_rd),
.O(\rd_data_sm_cs[3]_i_7_n_0 ));
FDRE \rd_data_sm_cs_reg[0]
(.C(s_axi_aclk),
.CE(rd_data_sm_ns),
.D(\rd_data_sm_cs[0]_i_1_n_0 ),
.Q(rd_data_sm_cs[0]),
.R(bram_rst_a));
FDRE \rd_data_sm_cs_reg[1]
(.C(s_axi_aclk),
.CE(rd_data_sm_ns),
.D(\rd_data_sm_cs[1]_i_1_n_0 ),
.Q(rd_data_sm_cs[1]),
.R(bram_rst_a));
FDRE \rd_data_sm_cs_reg[2]
(.C(s_axi_aclk),
.CE(rd_data_sm_ns),
.D(\rd_data_sm_cs[2]_i_1_n_0 ),
.Q(rd_data_sm_cs[2]),
.R(bram_rst_a));
FDRE \rd_data_sm_cs_reg[3]
(.C(s_axi_aclk),
.CE(rd_data_sm_ns),
.D(\rd_data_sm_cs[3]_i_2_n_0 ),
.Q(rd_data_sm_cs[3]),
.R(bram_rst_a));
LUT6 #(
.INIT(64'h1110011001100110))
rd_skid_buf_ld_reg_i_1
(.I0(rd_data_sm_cs[3]),
.I1(rd_data_sm_cs[2]),
.I2(rd_data_sm_cs[0]),
.I3(rd_data_sm_cs[1]),
.I4(s_axi_rready),
.I5(s_axi_rvalid),
.O(rd_skid_buf_ld_cmb));
FDRE #(
.INIT(1'b0))
rd_skid_buf_ld_reg_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(rd_skid_buf_ld_cmb),
.Q(rd_skid_buf_ld_reg),
.R(bram_rst_a));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT4 #(
.INIT(16'hFE02))
rddata_mux_sel_i_1
(.I0(rddata_mux_sel_cmb),
.I1(rd_data_sm_cs[3]),
.I2(rddata_mux_sel_i_3_n_0),
.I3(rddata_mux_sel),
.O(rddata_mux_sel_i_1_n_0));
LUT6 #(
.INIT(64'hF0F010F00F00F000))
rddata_mux_sel_i_2
(.I0(act_rd_burst),
.I1(act_rd_burst_two),
.I2(rd_data_sm_cs[2]),
.I3(rd_data_sm_cs[0]),
.I4(rd_data_sm_cs[1]),
.I5(rd_adv_buf67_out),
.O(rddata_mux_sel_cmb));
LUT6 #(
.INIT(64'hF700070FF70F070F))
rddata_mux_sel_i_3
(.I0(s_axi_rvalid),
.I1(s_axi_rready),
.I2(rd_data_sm_cs[0]),
.I3(rd_data_sm_cs[2]),
.I4(rd_data_sm_cs[1]),
.I5(axi_rd_burst_two_reg_n_0),
.O(rddata_mux_sel_i_3_n_0));
FDRE #(
.INIT(1'b0))
rddata_mux_sel_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(rddata_mux_sel_i_1_n_0),
.Q(rddata_mux_sel),
.R(bram_rst_a));
LUT4 #(
.INIT(16'hEAAA))
s_axi_arready_INST_0
(.I0(axi_arready_int),
.I1(s_axi_rvalid),
.I2(s_axi_rready),
.I3(axi_early_arready_int),
.O(s_axi_arready));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_chnl
(axi_aresetn_d2,
axi_aresetn_re_reg,
bram_en_a,
bram_wrdata_a,
s_axi_bvalid,
\GEN_AW_DUAL.aw_active_reg_0 ,
s_axi_wready,
s_axi_awready,
bram_addr_a,
s_axi_bid,
bram_we_a,
SR,
s_axi_aclk,
s_axi_awaddr,
s_axi_aresetn,
s_axi_wdata,
s_axi_wvalid,
s_axi_wlast,
s_axi_bready,
s_axi_awburst,
s_axi_awid,
s_axi_awvalid,
s_axi_awlen,
s_axi_wstrb);
output axi_aresetn_d2;
output axi_aresetn_re_reg;
output bram_en_a;
output [31:0]bram_wrdata_a;
output s_axi_bvalid;
output \GEN_AW_DUAL.aw_active_reg_0 ;
output s_axi_wready;
output s_axi_awready;
output [13:0]bram_addr_a;
output [11:0]s_axi_bid;
output [3:0]bram_we_a;
input [0:0]SR;
input s_axi_aclk;
input [13:0]s_axi_awaddr;
input s_axi_aresetn;
input [31:0]s_axi_wdata;
input s_axi_wvalid;
input s_axi_wlast;
input s_axi_bready;
input [1:0]s_axi_awburst;
input [11:0]s_axi_awid;
input s_axi_awvalid;
input [7:0]s_axi_awlen;
input [3:0]s_axi_wstrb;
wire BID_FIFO_n_0;
wire BID_FIFO_n_10;
wire BID_FIFO_n_11;
wire BID_FIFO_n_12;
wire BID_FIFO_n_13;
wire BID_FIFO_n_14;
wire BID_FIFO_n_15;
wire BID_FIFO_n_3;
wire BID_FIFO_n_4;
wire BID_FIFO_n_5;
wire BID_FIFO_n_6;
wire BID_FIFO_n_7;
wire BID_FIFO_n_8;
wire BID_FIFO_n_9;
wire \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1_n_0 ;
wire \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_2_n_0 ;
wire \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_1_n_0 ;
wire \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_2_n_0 ;
wire \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1_n_0 ;
wire \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_2_n_0 ;
wire \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0 ;
wire \GEN_AWREADY.axi_awready_int_i_1_n_0 ;
wire \GEN_AWREADY.axi_awready_int_i_2_n_0 ;
wire \GEN_AWREADY.axi_awready_int_i_3_n_0 ;
wire \GEN_AW_DUAL.aw_active_i_2_n_0 ;
wire \GEN_AW_DUAL.aw_active_reg_0 ;
wire \GEN_AW_DUAL.wr_addr_sm_cs_i_1_n_0 ;
wire \GEN_AW_DUAL.wr_addr_sm_cs_i_2_n_0 ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.axi_awaddr_full_i_1_n_0 ;
wire \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_i_1_n_0 ;
wire \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0 ;
wire \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ;
wire \GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2_n_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2__0_n_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3__0_n_0 ;
wire \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0 ;
wire \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2_n_0 ;
wire \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_1_n_0 ;
wire \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_2_n_0 ;
wire \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_3_n_0 ;
wire \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0 ;
wire \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ;
wire \I_RD_CHNL/axi_aresetn_d1 ;
wire I_WRAP_BRST_n_0;
wire I_WRAP_BRST_n_10;
wire I_WRAP_BRST_n_11;
wire I_WRAP_BRST_n_12;
wire I_WRAP_BRST_n_13;
wire I_WRAP_BRST_n_14;
wire I_WRAP_BRST_n_15;
wire I_WRAP_BRST_n_16;
wire I_WRAP_BRST_n_17;
wire I_WRAP_BRST_n_19;
wire I_WRAP_BRST_n_2;
wire I_WRAP_BRST_n_20;
wire I_WRAP_BRST_n_21;
wire I_WRAP_BRST_n_22;
wire I_WRAP_BRST_n_23;
wire I_WRAP_BRST_n_7;
wire I_WRAP_BRST_n_8;
wire I_WRAP_BRST_n_9;
wire [0:0]SR;
wire aw_active;
wire axi_aresetn_d2;
wire axi_aresetn_re;
wire axi_aresetn_re_reg;
wire axi_awaddr_full;
wire [1:0]axi_awburst_pipe;
wire [11:0]axi_awid_pipe;
wire [7:0]axi_awlen_pipe;
wire axi_awlen_pipe_1_or_2;
wire [1:1]axi_awsize_pipe;
wire axi_bvalid_int_i_1_n_0;
wire axi_wdata_full_cmb;
wire axi_wdata_full_cmb114_out;
wire axi_wdata_full_reg;
wire axi_wr_burst;
wire axi_wr_burst_cmb;
wire axi_wr_burst_cmb0;
wire axi_wr_burst_i_1_n_0;
wire axi_wr_burst_i_3_n_0;
wire axi_wready_int_mod_i_1_n_0;
wire axi_wready_int_mod_i_3_n_0;
wire bid_gets_fifo_load;
wire bid_gets_fifo_load_d1;
wire bid_gets_fifo_load_d1_i_2_n_0;
wire [13:0]bram_addr_a;
wire bram_addr_inc;
wire [13:10]bram_addr_ld;
wire bram_addr_ld_en;
wire bram_addr_ld_en_mod;
wire bram_addr_rst_cmb;
wire bram_en_a;
wire bram_en_cmb;
wire [3:0]bram_we_a;
wire [31:0]bram_wrdata_a;
wire [2:0]bvalid_cnt;
wire \bvalid_cnt[0]_i_1_n_0 ;
wire \bvalid_cnt[1]_i_1_n_0 ;
wire \bvalid_cnt[2]_i_1_n_0 ;
wire bvalid_cnt_inc;
wire bvalid_cnt_inc11_out;
wire clr_bram_we;
wire clr_bram_we_cmb;
wire curr_awlen_reg_1_or_2;
wire curr_awlen_reg_1_or_20;
wire curr_awlen_reg_1_or_2_i_2_n_0;
wire curr_awlen_reg_1_or_2_i_3_n_0;
wire curr_fixed_burst;
wire curr_fixed_burst_reg;
wire curr_wrap_burst;
wire curr_wrap_burst_reg;
wire delay_aw_active_clr;
wire last_data_ack_mod;
wire p_18_out;
wire p_9_out;
wire s_axi_aclk;
wire s_axi_aresetn;
wire [13:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [11:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire s_axi_awready;
wire s_axi_awvalid;
wire [11:0]s_axi_bid;
wire s_axi_bready;
wire s_axi_bvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wlast;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
wire wr_addr_sm_cs;
(* RTL_KEEP = "yes" *) wire [2:0]wr_data_sm_cs;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_SRL_FIFO BID_FIFO
(.D({BID_FIFO_n_4,BID_FIFO_n_5,BID_FIFO_n_6,BID_FIFO_n_7,BID_FIFO_n_8,BID_FIFO_n_9,BID_FIFO_n_10,BID_FIFO_n_11,BID_FIFO_n_12,BID_FIFO_n_13,BID_FIFO_n_14,BID_FIFO_n_15}),
.E(BID_FIFO_n_0),
.\GEN_AWREADY.axi_aresetn_d2_reg (axi_aresetn_d2),
.\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg (\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0 ),
.Q(axi_awid_pipe),
.SR(SR),
.aw_active(aw_active),
.axi_awaddr_full(axi_awaddr_full),
.axi_awlen_pipe_1_or_2(axi_awlen_pipe_1_or_2),
.axi_bvalid_int_reg(s_axi_bvalid),
.axi_wdata_full_cmb114_out(axi_wdata_full_cmb114_out),
.axi_wr_burst(axi_wr_burst),
.bid_gets_fifo_load(bid_gets_fifo_load),
.bid_gets_fifo_load_d1(bid_gets_fifo_load_d1),
.bid_gets_fifo_load_d1_reg(BID_FIFO_n_3),
.bram_addr_ld_en(bram_addr_ld_en),
.bvalid_cnt(bvalid_cnt),
.bvalid_cnt_inc(bvalid_cnt_inc),
.\bvalid_cnt_reg[1] (bid_gets_fifo_load_d1_i_2_n_0),
.\bvalid_cnt_reg[2] (I_WRAP_BRST_n_20),
.\bvalid_cnt_reg[2]_0 (I_WRAP_BRST_n_19),
.curr_awlen_reg_1_or_2(curr_awlen_reg_1_or_2),
.last_data_ack_mod(last_data_ack_mod),
.out(wr_data_sm_cs),
.s_axi_aclk(s_axi_aclk),
.s_axi_awid(s_axi_awid),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_wlast(s_axi_wlast),
.s_axi_wvalid(s_axi_wvalid),
.wr_addr_sm_cs(wr_addr_sm_cs));
(* SOFT_HLUTNM = "soft_lutpair65" *)
LUT3 #(
.INIT(8'hB8))
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1
(.I0(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_2_n_0 ),
.I1(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0 ),
.I2(wr_data_sm_cs[0]),
.O(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1_n_0 ));
LUT5 #(
.INIT(32'h05051F1A))
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_2
(.I0(wr_data_sm_cs[1]),
.I1(axi_wr_burst_cmb0),
.I2(wr_data_sm_cs[0]),
.I3(axi_wdata_full_cmb114_out),
.I4(wr_data_sm_cs[2]),
.O(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair63" *)
LUT4 #(
.INIT(16'h5515))
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_3
(.I0(I_WRAP_BRST_n_21),
.I1(bvalid_cnt[2]),
.I2(bvalid_cnt[1]),
.I3(bvalid_cnt[0]),
.O(axi_wr_burst_cmb0));
LUT3 #(
.INIT(8'hB8))
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_1
(.I0(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_2_n_0 ),
.I1(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0 ),
.I2(wr_data_sm_cs[1]),
.O(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0000554000555540))
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_2
(.I0(wr_data_sm_cs[1]),
.I1(s_axi_wlast),
.I2(axi_wdata_full_cmb114_out),
.I3(wr_data_sm_cs[0]),
.I4(wr_data_sm_cs[2]),
.I5(axi_wr_burst),
.O(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair65" *)
LUT3 #(
.INIT(8'hB8))
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1
(.I0(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_2_n_0 ),
.I1(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0 ),
.I2(wr_data_sm_cs[2]),
.O(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1_n_0 ));
LUT5 #(
.INIT(32'h44010001))
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_2
(.I0(wr_data_sm_cs[2]),
.I1(wr_data_sm_cs[1]),
.I2(axi_wdata_full_cmb114_out),
.I3(wr_data_sm_cs[0]),
.I4(s_axi_wvalid),
.O(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'h7774777774744444))
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3
(.I0(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0 ),
.I1(wr_data_sm_cs[2]),
.I2(wr_data_sm_cs[1]),
.I3(s_axi_wlast),
.I4(wr_data_sm_cs[0]),
.I5(s_axi_wvalid),
.O(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0 ));
(* KEEP = "yes" *)
FDRE \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1_n_0 ),
.Q(wr_data_sm_cs[0]),
.R(SR));
(* KEEP = "yes" *)
FDRE \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_1_n_0 ),
.Q(wr_data_sm_cs[1]),
.R(SR));
(* KEEP = "yes" *)
FDRE \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1_n_0 ),
.Q(wr_data_sm_cs[2]),
.R(SR));
FDRE #(
.INIT(1'b0))
\GEN_AWREADY.axi_aresetn_d1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_axi_aresetn),
.Q(\I_RD_CHNL/axi_aresetn_d1 ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AWREADY.axi_aresetn_d2_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\I_RD_CHNL/axi_aresetn_d1 ),
.Q(axi_aresetn_d2),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\GEN_AWREADY.axi_aresetn_re_reg_i_1
(.I0(s_axi_aresetn),
.I1(\I_RD_CHNL/axi_aresetn_d1 ),
.O(axi_aresetn_re));
FDRE #(
.INIT(1'b0))
\GEN_AWREADY.axi_aresetn_re_reg_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_aresetn_re),
.Q(axi_aresetn_re_reg),
.R(1'b0));
LUT6 #(
.INIT(64'hFFFFBFBFFFFFAA00))
\GEN_AWREADY.axi_awready_int_i_1
(.I0(axi_awaddr_full),
.I1(\GEN_AWREADY.axi_awready_int_i_2_n_0 ),
.I2(axi_aresetn_d2),
.I3(bram_addr_ld_en),
.I4(axi_aresetn_re_reg),
.I5(s_axi_awready),
.O(\GEN_AWREADY.axi_awready_int_i_1_n_0 ));
LUT6 #(
.INIT(64'h5444444400000000))
\GEN_AWREADY.axi_awready_int_i_2
(.I0(\GEN_AWREADY.axi_awready_int_i_3_n_0 ),
.I1(aw_active),
.I2(bvalid_cnt[1]),
.I3(bvalid_cnt[0]),
.I4(bvalid_cnt[2]),
.I5(s_axi_awvalid),
.O(\GEN_AWREADY.axi_awready_int_i_2_n_0 ));
LUT6 #(
.INIT(64'hAABABABABABABABA))
\GEN_AWREADY.axi_awready_int_i_3
(.I0(wr_addr_sm_cs),
.I1(I_WRAP_BRST_n_21),
.I2(last_data_ack_mod),
.I3(bvalid_cnt[2]),
.I4(bvalid_cnt[0]),
.I5(bvalid_cnt[1]),
.O(\GEN_AWREADY.axi_awready_int_i_3_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_AWREADY.axi_awready_int_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_AWREADY.axi_awready_int_i_1_n_0 ),
.Q(s_axi_awready),
.R(SR));
LUT1 #(
.INIT(2'h1))
\GEN_AW_DUAL.aw_active_i_1
(.I0(axi_aresetn_d2),
.O(\GEN_AW_DUAL.aw_active_reg_0 ));
LUT6 #(
.INIT(64'hFFFFF7FFFFFF0000))
\GEN_AW_DUAL.aw_active_i_2
(.I0(wr_data_sm_cs[1]),
.I1(wr_data_sm_cs[0]),
.I2(wr_data_sm_cs[2]),
.I3(delay_aw_active_clr),
.I4(bram_addr_ld_en),
.I5(aw_active),
.O(\GEN_AW_DUAL.aw_active_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_AW_DUAL.aw_active_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_AW_DUAL.aw_active_i_2_n_0 ),
.Q(aw_active),
.R(\GEN_AW_DUAL.aw_active_reg_0 ));
(* SOFT_HLUTNM = "soft_lutpair64" *)
LUT3 #(
.INIT(8'h80))
\GEN_AW_DUAL.last_data_ack_mod_i_1
(.I0(s_axi_wready),
.I1(s_axi_wlast),
.I2(s_axi_wvalid),
.O(p_18_out));
FDRE #(
.INIT(1'b0))
\GEN_AW_DUAL.last_data_ack_mod_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(p_18_out),
.Q(last_data_ack_mod),
.R(SR));
LUT6 #(
.INIT(64'h0010001000100000))
\GEN_AW_DUAL.wr_addr_sm_cs_i_1
(.I0(\GEN_AW_DUAL.wr_addr_sm_cs_i_2_n_0 ),
.I1(wr_addr_sm_cs),
.I2(s_axi_awvalid),
.I3(axi_awaddr_full),
.I4(I_WRAP_BRST_n_20),
.I5(aw_active),
.O(\GEN_AW_DUAL.wr_addr_sm_cs_i_1_n_0 ));
LUT6 #(
.INIT(64'h0000000000000040))
\GEN_AW_DUAL.wr_addr_sm_cs_i_2
(.I0(I_WRAP_BRST_n_20),
.I1(last_data_ack_mod),
.I2(axi_awaddr_full),
.I3(\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0 ),
.I4(axi_awlen_pipe_1_or_2),
.I5(curr_awlen_reg_1_or_2),
.O(\GEN_AW_DUAL.wr_addr_sm_cs_i_2_n_0 ));
FDRE \GEN_AW_DUAL.wr_addr_sm_cs_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_AW_DUAL.wr_addr_sm_cs_i_1_n_0 ),
.Q(wr_addr_sm_cs),
.R(\GEN_AW_DUAL.aw_active_reg_0 ));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg[10]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[8]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg[11]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[9]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg[12]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[10]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg[13]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[11]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg[14]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[12]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg[15]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[13]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg[2]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[0]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg[3]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[1]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg[4]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[2]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg[5]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[3]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg[6]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[4]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg[7]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[5]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg[8]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[6]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg[9]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[7]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg ),
.R(1'b0));
LUT5 #(
.INIT(32'h4000EA00))
\GEN_AW_PIPE_DUAL.axi_awaddr_full_i_1
(.I0(axi_awaddr_full),
.I1(\GEN_AWREADY.axi_awready_int_i_2_n_0 ),
.I2(axi_aresetn_d2),
.I3(s_axi_aresetn),
.I4(bram_addr_ld_en),
.O(\GEN_AW_PIPE_DUAL.axi_awaddr_full_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awaddr_full_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_AW_PIPE_DUAL.axi_awaddr_full_i_1_n_0 ),
.Q(axi_awaddr_full),
.R(1'b0));
LUT6 #(
.INIT(64'hBF00BF00BF00FF40))
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_i_1
(.I0(axi_awaddr_full),
.I1(\GEN_AWREADY.axi_awready_int_i_2_n_0 ),
.I2(axi_aresetn_d2),
.I3(\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0 ),
.I4(s_axi_awburst[0]),
.I5(s_axi_awburst[1]),
.O(\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_i_1_n_0 ),
.Q(\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0 ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_reg[0]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awburst[0]),
.Q(axi_awburst_pipe[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_reg[1]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awburst[1]),
.Q(axi_awburst_pipe[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[0]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awid[0]),
.Q(axi_awid_pipe[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[10]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awid[10]),
.Q(axi_awid_pipe[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[11]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awid[11]),
.Q(axi_awid_pipe[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[1]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awid[1]),
.Q(axi_awid_pipe[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[2]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awid[2]),
.Q(axi_awid_pipe[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[3]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awid[3]),
.Q(axi_awid_pipe[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[4]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awid[4]),
.Q(axi_awid_pipe[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[5]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awid[5]),
.Q(axi_awid_pipe[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[6]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awid[6]),
.Q(axi_awid_pipe[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[7]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awid[7]),
.Q(axi_awid_pipe[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[8]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awid[8]),
.Q(axi_awid_pipe[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[9]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awid[9]),
.Q(axi_awid_pipe[9]),
.R(1'b0));
LUT3 #(
.INIT(8'h40))
\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1
(.I0(axi_awaddr_full),
.I1(\GEN_AWREADY.axi_awready_int_i_2_n_0 ),
.I2(axi_aresetn_d2),
.O(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ));
LUT4 #(
.INIT(16'h0002))
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_1
(.I0(\GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2_n_0 ),
.I1(s_axi_awlen[3]),
.I2(s_axi_awlen[2]),
.I3(s_axi_awlen[1]),
.O(p_9_out));
LUT4 #(
.INIT(16'h0001))
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2
(.I0(s_axi_awlen[4]),
.I1(s_axi_awlen[6]),
.I2(s_axi_awlen[7]),
.I3(s_axi_awlen[5]),
.O(\GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_reg
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(p_9_out),
.Q(axi_awlen_pipe_1_or_2),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[0]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awlen[0]),
.Q(axi_awlen_pipe[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[1]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awlen[1]),
.Q(axi_awlen_pipe[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[2]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awlen[2]),
.Q(axi_awlen_pipe[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[3]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awlen[3]),
.Q(axi_awlen_pipe[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[4]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awlen[4]),
.Q(axi_awlen_pipe[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[5]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awlen[5]),
.Q(axi_awlen_pipe[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[6]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awlen[6]),
.Q(axi_awlen_pipe[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[7]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awlen[7]),
.Q(axi_awlen_pipe[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awsize_pipe_reg[1]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(1'b1),
.Q(axi_awsize_pipe),
.R(1'b0));
LUT6 #(
.INIT(64'h7FFFFFFFFFFFFFFF))
\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2__0
(.I0(bram_addr_a[4]),
.I1(bram_addr_a[1]),
.I2(bram_addr_a[0]),
.I3(bram_addr_a[2]),
.I4(bram_addr_a[3]),
.I5(bram_addr_a[5]),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2__0_n_0 ));
LUT5 #(
.INIT(32'hF7FFFFFF))
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3__0
(.I0(bram_addr_a[6]),
.I1(bram_addr_a[4]),
.I2(I_WRAP_BRST_n_17),
.I3(bram_addr_a[5]),
.I4(bram_addr_a[7]),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3__0_n_0 ));
LUT4 #(
.INIT(16'h1000))
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4
(.I0(wr_data_sm_cs[1]),
.I1(wr_data_sm_cs[2]),
.I2(wr_data_sm_cs[0]),
.I3(s_axi_wvalid),
.O(bram_addr_inc));
LUT4 #(
.INIT(16'h1000))
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_5
(.I0(s_axi_wvalid),
.I1(wr_data_sm_cs[2]),
.I2(wr_data_sm_cs[0]),
.I3(wr_data_sm_cs[1]),
.O(bram_addr_rst_cmb));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[10]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_2),
.D(I_WRAP_BRST_n_8),
.Q(bram_addr_a[8]),
.R(I_WRAP_BRST_n_0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_2),
.D(I_WRAP_BRST_n_7),
.Q(bram_addr_a[9]),
.R(I_WRAP_BRST_n_0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[12]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en_mod),
.D(bram_addr_ld[10]),
.Q(bram_addr_a[10]),
.R(I_WRAP_BRST_n_0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[13]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en_mod),
.D(bram_addr_ld[11]),
.Q(bram_addr_a[11]),
.R(I_WRAP_BRST_n_0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[14]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en_mod),
.D(bram_addr_ld[12]),
.Q(bram_addr_a[12]),
.R(I_WRAP_BRST_n_0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[15]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en_mod),
.D(bram_addr_ld[13]),
.Q(bram_addr_a[13]),
.R(I_WRAP_BRST_n_0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[2]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_2),
.D(I_WRAP_BRST_n_16),
.Q(bram_addr_a[0]),
.R(I_WRAP_BRST_n_0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[3]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_2),
.D(I_WRAP_BRST_n_15),
.Q(bram_addr_a[1]),
.R(I_WRAP_BRST_n_0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[4]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_2),
.D(I_WRAP_BRST_n_14),
.Q(bram_addr_a[2]),
.R(I_WRAP_BRST_n_0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[5]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_2),
.D(I_WRAP_BRST_n_13),
.Q(bram_addr_a[3]),
.R(I_WRAP_BRST_n_0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_2),
.D(I_WRAP_BRST_n_12),
.Q(bram_addr_a[4]),
.R(I_WRAP_BRST_n_0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[7]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_2),
.D(I_WRAP_BRST_n_11),
.Q(bram_addr_a[5]),
.R(I_WRAP_BRST_n_0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_2),
.D(I_WRAP_BRST_n_10),
.Q(bram_addr_a[6]),
.R(I_WRAP_BRST_n_0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[9]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_2),
.D(I_WRAP_BRST_n_9),
.Q(bram_addr_a[7]),
.R(I_WRAP_BRST_n_0));
LUT5 #(
.INIT(32'h15FF1500))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.axi_wdata_full_reg_i_1
(.I0(axi_wdata_full_cmb114_out),
.I1(axi_awaddr_full),
.I2(bram_addr_ld_en),
.I3(wr_data_sm_cs[2]),
.I4(axi_wready_int_mod_i_3_n_0),
.O(axi_wdata_full_cmb));
FDRE #(
.INIT(1'b0))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.axi_wdata_full_reg_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_wdata_full_cmb),
.Q(axi_wdata_full_reg),
.R(SR));
LUT6 #(
.INIT(64'h4777477444444444))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_1
(.I0(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0 ),
.I1(wr_data_sm_cs[2]),
.I2(wr_data_sm_cs[1]),
.I3(wr_data_sm_cs[0]),
.I4(axi_wdata_full_cmb114_out),
.I5(s_axi_wvalid),
.O(bram_en_cmb));
LUT3 #(
.INIT(8'h15))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2
(.I0(axi_wdata_full_cmb114_out),
.I1(axi_awaddr_full),
.I2(bram_addr_ld_en),
.O(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(bram_en_cmb),
.Q(bram_en_a),
.R(SR));
LUT6 #(
.INIT(64'h0010001000101110))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_1
(.I0(wr_data_sm_cs[0]),
.I1(wr_data_sm_cs[1]),
.I2(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2_n_0 ),
.I3(wr_data_sm_cs[2]),
.I4(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0 ),
.I5(axi_wr_burst),
.O(clr_bram_we_cmb));
(* SOFT_HLUTNM = "soft_lutpair64" *)
LUT3 #(
.INIT(8'h80))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2
(.I0(axi_wdata_full_cmb114_out),
.I1(s_axi_wlast),
.I2(s_axi_wvalid),
.O(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(clr_bram_we_cmb),
.Q(clr_bram_we),
.R(SR));
LUT6 #(
.INIT(64'hFEAAFEFF02AA0200))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_1
(.I0(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_2_n_0 ),
.I1(axi_wr_burst),
.I2(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0 ),
.I3(wr_data_sm_cs[2]),
.I4(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_3_n_0 ),
.I5(delay_aw_active_clr),
.O(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_1_n_0 ));
LUT5 #(
.INIT(32'h0000222E))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_2
(.I0(s_axi_wlast),
.I1(wr_data_sm_cs[2]),
.I2(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0 ),
.I3(wr_data_sm_cs[0]),
.I4(wr_data_sm_cs[1]),
.O(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_2_n_0 ));
LUT6 #(
.INIT(64'h8B338B0088008800))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_3
(.I0(delay_aw_active_clr),
.I1(wr_data_sm_cs[1]),
.I2(axi_wr_burst_cmb0),
.I3(wr_data_sm_cs[0]),
.I4(axi_wdata_full_cmb114_out),
.I5(bvalid_cnt_inc11_out),
.O(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_3_n_0 ));
LUT2 #(
.INIT(4'h8))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_4
(.I0(s_axi_wvalid),
.I1(s_axi_wlast),
.O(bvalid_cnt_inc11_out));
FDRE #(
.INIT(1'b0))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_1_n_0 ),
.Q(delay_aw_active_clr),
.R(SR));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[0].bram_wrdata_int_reg[0]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[0]),
.Q(bram_wrdata_a[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[10].bram_wrdata_int_reg[10]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[10]),
.Q(bram_wrdata_a[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[11].bram_wrdata_int_reg[11]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[11]),
.Q(bram_wrdata_a[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[12].bram_wrdata_int_reg[12]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[12]),
.Q(bram_wrdata_a[12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[13].bram_wrdata_int_reg[13]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[13]),
.Q(bram_wrdata_a[13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[14].bram_wrdata_int_reg[14]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[14]),
.Q(bram_wrdata_a[14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[15].bram_wrdata_int_reg[15]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[15]),
.Q(bram_wrdata_a[15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[16].bram_wrdata_int_reg[16]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[16]),
.Q(bram_wrdata_a[16]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[17].bram_wrdata_int_reg[17]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[17]),
.Q(bram_wrdata_a[17]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[18].bram_wrdata_int_reg[18]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[18]),
.Q(bram_wrdata_a[18]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[19].bram_wrdata_int_reg[19]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[19]),
.Q(bram_wrdata_a[19]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[1].bram_wrdata_int_reg[1]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[1]),
.Q(bram_wrdata_a[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[20].bram_wrdata_int_reg[20]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[20]),
.Q(bram_wrdata_a[20]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[21].bram_wrdata_int_reg[21]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[21]),
.Q(bram_wrdata_a[21]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[22].bram_wrdata_int_reg[22]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[22]),
.Q(bram_wrdata_a[22]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[23].bram_wrdata_int_reg[23]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[23]),
.Q(bram_wrdata_a[23]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[24].bram_wrdata_int_reg[24]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[24]),
.Q(bram_wrdata_a[24]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[25].bram_wrdata_int_reg[25]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[25]),
.Q(bram_wrdata_a[25]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[26].bram_wrdata_int_reg[26]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[26]),
.Q(bram_wrdata_a[26]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[27].bram_wrdata_int_reg[27]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[27]),
.Q(bram_wrdata_a[27]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[28].bram_wrdata_int_reg[28]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[28]),
.Q(bram_wrdata_a[28]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[29].bram_wrdata_int_reg[29]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[29]),
.Q(bram_wrdata_a[29]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[2].bram_wrdata_int_reg[2]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[2]),
.Q(bram_wrdata_a[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[30].bram_wrdata_int_reg[30]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[30]),
.Q(bram_wrdata_a[30]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[31].bram_wrdata_int_reg[31]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[31]),
.Q(bram_wrdata_a[31]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[3].bram_wrdata_int_reg[3]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[3]),
.Q(bram_wrdata_a[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[4].bram_wrdata_int_reg[4]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[4]),
.Q(bram_wrdata_a[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[5].bram_wrdata_int_reg[5]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[5]),
.Q(bram_wrdata_a[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[6].bram_wrdata_int_reg[6]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[6]),
.Q(bram_wrdata_a[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[7].bram_wrdata_int_reg[7]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[7]),
.Q(bram_wrdata_a[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[8].bram_wrdata_int_reg[8]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[8]),
.Q(bram_wrdata_a[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[9].bram_wrdata_int_reg[9]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[9]),
.Q(bram_wrdata_a[9]),
.R(1'b0));
LUT4 #(
.INIT(16'hD0FF))
\GEN_WR_NO_ECC.bram_we_int[3]_i_1
(.I0(s_axi_wvalid),
.I1(wr_data_sm_cs[2]),
.I2(clr_bram_we),
.I3(s_axi_aresetn),
.O(\GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0 ));
LUT2 #(
.INIT(4'h2))
\GEN_WR_NO_ECC.bram_we_int[3]_i_2
(.I0(s_axi_wvalid),
.I1(wr_data_sm_cs[2]),
.O(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_WR_NO_ECC.bram_we_int_reg[0]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wstrb[0]),
.Q(bram_we_a[0]),
.R(\GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_WR_NO_ECC.bram_we_int_reg[1]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wstrb[1]),
.Q(bram_we_a[1]),
.R(\GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_WR_NO_ECC.bram_we_int_reg[2]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wstrb[2]),
.Q(bram_we_a[2]),
.R(\GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_WR_NO_ECC.bram_we_int_reg[3]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wstrb[3]),
.Q(bram_we_a[3]),
.R(\GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0 ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wrap_brst I_WRAP_BRST
(.D({bram_addr_ld,I_WRAP_BRST_n_7,I_WRAP_BRST_n_8,I_WRAP_BRST_n_9,I_WRAP_BRST_n_10,I_WRAP_BRST_n_11,I_WRAP_BRST_n_12,I_WRAP_BRST_n_13,I_WRAP_BRST_n_14,I_WRAP_BRST_n_15,I_WRAP_BRST_n_16}),
.E(I_WRAP_BRST_n_2),
.\GEN_AWREADY.axi_aresetn_d2_reg (axi_aresetn_d2),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg (\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0 ),
.\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] (\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2__0_n_0 ),
.\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] (I_WRAP_BRST_n_17),
.\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]_0 (\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3__0_n_0 ),
.Q(axi_awlen_pipe[3:0]),
.SR(I_WRAP_BRST_n_0),
.aw_active(aw_active),
.axi_awaddr_full(axi_awaddr_full),
.axi_awlen_pipe_1_or_2(axi_awlen_pipe_1_or_2),
.axi_awsize_pipe(axi_awsize_pipe),
.bram_addr_a(bram_addr_a[9:0]),
.bram_addr_inc(bram_addr_inc),
.bram_addr_ld_en(bram_addr_ld_en),
.bram_addr_ld_en_mod(bram_addr_ld_en_mod),
.bram_addr_rst_cmb(bram_addr_rst_cmb),
.bvalid_cnt(bvalid_cnt),
.curr_awlen_reg_1_or_2(curr_awlen_reg_1_or_2),
.curr_fixed_burst(curr_fixed_burst),
.curr_fixed_burst_reg(curr_fixed_burst_reg),
.curr_fixed_burst_reg_reg(I_WRAP_BRST_n_22),
.curr_wrap_burst(curr_wrap_burst),
.curr_wrap_burst_reg(curr_wrap_burst_reg),
.curr_wrap_burst_reg_reg(I_WRAP_BRST_n_23),
.last_data_ack_mod(last_data_ack_mod),
.out(wr_data_sm_cs),
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_aresetn_0(SR),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen[3:0]),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_wvalid(s_axi_wvalid),
.\save_init_bram_addr_ld_reg[15]_0 (I_WRAP_BRST_n_19),
.\save_init_bram_addr_ld_reg[15]_1 (I_WRAP_BRST_n_20),
.\save_init_bram_addr_ld_reg[15]_2 (I_WRAP_BRST_n_21),
.wr_addr_sm_cs(wr_addr_sm_cs));
FDRE #(
.INIT(1'b0))
\axi_bid_int_reg[0]
(.C(s_axi_aclk),
.CE(BID_FIFO_n_0),
.D(BID_FIFO_n_15),
.Q(s_axi_bid[0]),
.R(SR));
FDRE #(
.INIT(1'b0))
\axi_bid_int_reg[10]
(.C(s_axi_aclk),
.CE(BID_FIFO_n_0),
.D(BID_FIFO_n_5),
.Q(s_axi_bid[10]),
.R(SR));
FDRE #(
.INIT(1'b0))
\axi_bid_int_reg[11]
(.C(s_axi_aclk),
.CE(BID_FIFO_n_0),
.D(BID_FIFO_n_4),
.Q(s_axi_bid[11]),
.R(SR));
FDRE #(
.INIT(1'b0))
\axi_bid_int_reg[1]
(.C(s_axi_aclk),
.CE(BID_FIFO_n_0),
.D(BID_FIFO_n_14),
.Q(s_axi_bid[1]),
.R(SR));
FDRE #(
.INIT(1'b0))
\axi_bid_int_reg[2]
(.C(s_axi_aclk),
.CE(BID_FIFO_n_0),
.D(BID_FIFO_n_13),
.Q(s_axi_bid[2]),
.R(SR));
FDRE #(
.INIT(1'b0))
\axi_bid_int_reg[3]
(.C(s_axi_aclk),
.CE(BID_FIFO_n_0),
.D(BID_FIFO_n_12),
.Q(s_axi_bid[3]),
.R(SR));
FDRE #(
.INIT(1'b0))
\axi_bid_int_reg[4]
(.C(s_axi_aclk),
.CE(BID_FIFO_n_0),
.D(BID_FIFO_n_11),
.Q(s_axi_bid[4]),
.R(SR));
FDRE #(
.INIT(1'b0))
\axi_bid_int_reg[5]
(.C(s_axi_aclk),
.CE(BID_FIFO_n_0),
.D(BID_FIFO_n_10),
.Q(s_axi_bid[5]),
.R(SR));
FDRE #(
.INIT(1'b0))
\axi_bid_int_reg[6]
(.C(s_axi_aclk),
.CE(BID_FIFO_n_0),
.D(BID_FIFO_n_9),
.Q(s_axi_bid[6]),
.R(SR));
FDRE #(
.INIT(1'b0))
\axi_bid_int_reg[7]
(.C(s_axi_aclk),
.CE(BID_FIFO_n_0),
.D(BID_FIFO_n_8),
.Q(s_axi_bid[7]),
.R(SR));
FDRE #(
.INIT(1'b0))
\axi_bid_int_reg[8]
(.C(s_axi_aclk),
.CE(BID_FIFO_n_0),
.D(BID_FIFO_n_7),
.Q(s_axi_bid[8]),
.R(SR));
FDRE #(
.INIT(1'b0))
\axi_bid_int_reg[9]
(.C(s_axi_aclk),
.CE(BID_FIFO_n_0),
.D(BID_FIFO_n_6),
.Q(s_axi_bid[9]),
.R(SR));
LUT6 #(
.INIT(64'hAAAAAAAAAAAA8A88))
axi_bvalid_int_i_1
(.I0(s_axi_aresetn),
.I1(bvalid_cnt_inc),
.I2(BID_FIFO_n_3),
.I3(bvalid_cnt[0]),
.I4(bvalid_cnt[2]),
.I5(bvalid_cnt[1]),
.O(axi_bvalid_int_i_1_n_0));
FDRE #(
.INIT(1'b0))
axi_bvalid_int_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_bvalid_int_i_1_n_0),
.Q(s_axi_bvalid),
.R(1'b0));
LUT3 #(
.INIT(8'hB8))
axi_wr_burst_i_1
(.I0(axi_wr_burst_cmb),
.I1(axi_wr_burst_i_3_n_0),
.I2(axi_wr_burst),
.O(axi_wr_burst_i_1_n_0));
LUT5 #(
.INIT(32'h3088FCBB))
axi_wr_burst_i_2
(.I0(s_axi_wvalid),
.I1(wr_data_sm_cs[1]),
.I2(axi_wr_burst_cmb0),
.I3(wr_data_sm_cs[0]),
.I4(s_axi_wlast),
.O(axi_wr_burst_cmb));
LUT6 #(
.INIT(64'h00000000AAAAA222))
axi_wr_burst_i_3
(.I0(s_axi_wvalid),
.I1(wr_data_sm_cs[0]),
.I2(axi_wr_burst_cmb0),
.I3(s_axi_wlast),
.I4(wr_data_sm_cs[1]),
.I5(wr_data_sm_cs[2]),
.O(axi_wr_burst_i_3_n_0));
FDRE #(
.INIT(1'b0))
axi_wr_burst_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_wr_burst_i_1_n_0),
.Q(axi_wr_burst),
.R(SR));
LUT6 #(
.INIT(64'hEA00EAFF00000000))
axi_wready_int_mod_i_1
(.I0(axi_wdata_full_cmb114_out),
.I1(axi_awaddr_full),
.I2(bram_addr_ld_en),
.I3(wr_data_sm_cs[2]),
.I4(axi_wready_int_mod_i_3_n_0),
.I5(s_axi_aresetn),
.O(axi_wready_int_mod_i_1_n_0));
LUT5 #(
.INIT(32'hF8F9F0F0))
axi_wready_int_mod_i_3
(.I0(wr_data_sm_cs[1]),
.I1(wr_data_sm_cs[0]),
.I2(axi_wdata_full_reg),
.I3(axi_wdata_full_cmb114_out),
.I4(s_axi_wvalid),
.O(axi_wready_int_mod_i_3_n_0));
FDRE #(
.INIT(1'b0))
axi_wready_int_mod_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_wready_int_mod_i_1_n_0),
.Q(s_axi_wready),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair63" *)
LUT3 #(
.INIT(8'hEF))
bid_gets_fifo_load_d1_i_2
(.I0(bvalid_cnt[1]),
.I1(bvalid_cnt[2]),
.I2(bvalid_cnt[0]),
.O(bid_gets_fifo_load_d1_i_2_n_0));
FDRE #(
.INIT(1'b0))
bid_gets_fifo_load_d1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(bid_gets_fifo_load),
.Q(bid_gets_fifo_load_d1),
.R(SR));
LUT6 #(
.INIT(64'h95956A6A95956AAA))
\bvalid_cnt[0]_i_1
(.I0(bvalid_cnt_inc),
.I1(s_axi_bready),
.I2(s_axi_bvalid),
.I3(bvalid_cnt[2]),
.I4(bvalid_cnt[0]),
.I5(bvalid_cnt[1]),
.O(\bvalid_cnt[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hD5D5BFBF2A2A4000))
\bvalid_cnt[1]_i_1
(.I0(bvalid_cnt_inc),
.I1(s_axi_bready),
.I2(s_axi_bvalid),
.I3(bvalid_cnt[2]),
.I4(bvalid_cnt[0]),
.I5(bvalid_cnt[1]),
.O(\bvalid_cnt[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'hD52AFF00FF00BF00))
\bvalid_cnt[2]_i_1
(.I0(bvalid_cnt_inc),
.I1(s_axi_bready),
.I2(s_axi_bvalid),
.I3(bvalid_cnt[2]),
.I4(bvalid_cnt[0]),
.I5(bvalid_cnt[1]),
.O(\bvalid_cnt[2]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\bvalid_cnt_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\bvalid_cnt[0]_i_1_n_0 ),
.Q(bvalid_cnt[0]),
.R(SR));
FDRE #(
.INIT(1'b0))
\bvalid_cnt_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\bvalid_cnt[1]_i_1_n_0 ),
.Q(bvalid_cnt[1]),
.R(SR));
FDRE #(
.INIT(1'b0))
\bvalid_cnt_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\bvalid_cnt[2]_i_1_n_0 ),
.Q(bvalid_cnt[2]),
.R(SR));
LUT6 #(
.INIT(64'h00A0000000A0E0E0))
curr_awlen_reg_1_or_2_i_1
(.I0(curr_awlen_reg_1_or_2_i_2_n_0),
.I1(\GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2_n_0 ),
.I2(curr_awlen_reg_1_or_2_i_3_n_0),
.I3(axi_awlen_pipe[3]),
.I4(axi_awaddr_full),
.I5(s_axi_awlen[3]),
.O(curr_awlen_reg_1_or_20));
LUT5 #(
.INIT(32'h00000004))
curr_awlen_reg_1_or_2_i_2
(.I0(axi_awlen_pipe[7]),
.I1(axi_awaddr_full),
.I2(axi_awlen_pipe[5]),
.I3(axi_awlen_pipe[4]),
.I4(axi_awlen_pipe[6]),
.O(curr_awlen_reg_1_or_2_i_2_n_0));
LUT5 #(
.INIT(32'h00053305))
curr_awlen_reg_1_or_2_i_3
(.I0(s_axi_awlen[2]),
.I1(axi_awlen_pipe[2]),
.I2(s_axi_awlen[1]),
.I3(axi_awaddr_full),
.I4(axi_awlen_pipe[1]),
.O(curr_awlen_reg_1_or_2_i_3_n_0));
FDRE #(
.INIT(1'b0))
curr_awlen_reg_1_or_2_reg
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(curr_awlen_reg_1_or_20),
.Q(curr_awlen_reg_1_or_2),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair62" *)
LUT5 #(
.INIT(32'h00053305))
curr_fixed_burst_reg_i_2
(.I0(s_axi_awburst[1]),
.I1(axi_awburst_pipe[1]),
.I2(s_axi_awburst[0]),
.I3(axi_awaddr_full),
.I4(axi_awburst_pipe[0]),
.O(curr_fixed_burst));
FDRE #(
.INIT(1'b0))
curr_fixed_burst_reg_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(I_WRAP_BRST_n_22),
.Q(curr_fixed_burst_reg),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair62" *)
LUT5 #(
.INIT(32'h000ACC0A))
curr_wrap_burst_reg_i_2
(.I0(s_axi_awburst[1]),
.I1(axi_awburst_pipe[1]),
.I2(s_axi_awburst[0]),
.I3(axi_awaddr_full),
.I4(axi_awburst_pipe[0]),
.O(curr_wrap_burst));
FDRE #(
.INIT(1'b0))
curr_wrap_burst_reg_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(I_WRAP_BRST_n_23),
.Q(curr_wrap_burst_reg),
.R(1'b0));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wrap_brst
(SR,
bram_addr_ld_en_mod,
E,
D,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] ,
bram_addr_ld_en,
\save_init_bram_addr_ld_reg[15]_0 ,
\save_init_bram_addr_ld_reg[15]_1 ,
\save_init_bram_addr_ld_reg[15]_2 ,
curr_fixed_burst_reg_reg,
curr_wrap_burst_reg_reg,
curr_fixed_burst_reg,
bram_addr_inc,
bram_addr_rst_cmb,
s_axi_aresetn,
out,
s_axi_wvalid,
bram_addr_a,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]_0 ,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg ,
axi_awaddr_full,
s_axi_awaddr,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg ,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg ,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg ,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg ,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg ,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg ,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg ,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg ,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg ,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg ,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg ,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg ,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg ,
\GEN_AWREADY.axi_aresetn_d2_reg ,
wr_addr_sm_cs,
last_data_ack_mod,
bvalid_cnt,
aw_active,
s_axi_awvalid,
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg ,
axi_awlen_pipe_1_or_2,
curr_awlen_reg_1_or_2,
curr_wrap_burst_reg,
Q,
s_axi_awlen,
axi_awsize_pipe,
curr_fixed_burst,
curr_wrap_burst,
s_axi_aresetn_0,
s_axi_aclk);
output [0:0]SR;
output bram_addr_ld_en_mod;
output [0:0]E;
output [13:0]D;
output \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] ;
output bram_addr_ld_en;
output \save_init_bram_addr_ld_reg[15]_0 ;
output \save_init_bram_addr_ld_reg[15]_1 ;
output \save_init_bram_addr_ld_reg[15]_2 ;
output curr_fixed_burst_reg_reg;
output curr_wrap_burst_reg_reg;
input curr_fixed_burst_reg;
input bram_addr_inc;
input bram_addr_rst_cmb;
input s_axi_aresetn;
input [2:0]out;
input s_axi_wvalid;
input [9:0]bram_addr_a;
input \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]_0 ;
input \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg ;
input axi_awaddr_full;
input [13:0]s_axi_awaddr;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg ;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg ;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg ;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg ;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg ;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg ;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg ;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg ;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg ;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg ;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg ;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg ;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg ;
input \GEN_AWREADY.axi_aresetn_d2_reg ;
input wr_addr_sm_cs;
input last_data_ack_mod;
input [2:0]bvalid_cnt;
input aw_active;
input s_axi_awvalid;
input \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg ;
input axi_awlen_pipe_1_or_2;
input curr_awlen_reg_1_or_2;
input curr_wrap_burst_reg;
input [3:0]Q;
input [3:0]s_axi_awlen;
input [0:0]axi_awsize_pipe;
input curr_fixed_burst;
input curr_wrap_burst;
input [0:0]s_axi_aresetn_0;
input s_axi_aclk;
wire [13:0]D;
wire [0:0]E;
wire \GEN_AWREADY.axi_aresetn_d2_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_6_n_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_8_n_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]_0 ;
wire [3:0]Q;
wire [0:0]SR;
wire aw_active;
wire axi_awaddr_full;
wire axi_awlen_pipe_1_or_2;
wire [0:0]axi_awsize_pipe;
wire [9:0]bram_addr_a;
wire bram_addr_inc;
wire [9:1]bram_addr_ld;
wire bram_addr_ld_en;
wire bram_addr_ld_en_mod;
wire bram_addr_rst_cmb;
wire [2:0]bvalid_cnt;
wire curr_awlen_reg_1_or_2;
wire curr_fixed_burst;
wire curr_fixed_burst_reg;
wire curr_fixed_burst_reg_reg;
wire curr_wrap_burst;
wire curr_wrap_burst_reg;
wire curr_wrap_burst_reg_reg;
wire last_data_ack_mod;
wire [2:0]out;
wire s_axi_aclk;
wire s_axi_aresetn;
wire [0:0]s_axi_aresetn_0;
wire [13:0]s_axi_awaddr;
wire [3:0]s_axi_awlen;
wire s_axi_awvalid;
wire s_axi_wvalid;
wire [15:3]save_init_bram_addr_ld;
wire \save_init_bram_addr_ld[3]_i_2__0_n_0 ;
wire \save_init_bram_addr_ld[4]_i_2__0_n_0 ;
wire \save_init_bram_addr_ld[5]_i_2__0_n_0 ;
wire \save_init_bram_addr_ld_reg[15]_0 ;
wire \save_init_bram_addr_ld_reg[15]_1 ;
wire \save_init_bram_addr_ld_reg[15]_2 ;
wire wr_addr_sm_cs;
wire [2:0]wrap_burst_total;
wire \wrap_burst_total[0]_i_1__0_n_0 ;
wire \wrap_burst_total[0]_i_2__0_n_0 ;
wire \wrap_burst_total[0]_i_3_n_0 ;
wire \wrap_burst_total[1]_i_1__0_n_0 ;
wire \wrap_burst_total[1]_i_2_n_0 ;
wire \wrap_burst_total[1]_i_3_n_0 ;
wire \wrap_burst_total[2]_i_1__0_n_0 ;
wire \wrap_burst_total[2]_i_2__0_n_0 ;
wire \wrap_burst_total[2]_i_3__0_n_0 ;
LUT6 #(
.INIT(64'hBB8BBBBB88B88888))
\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_1
(.I0(bram_addr_ld[8]),
.I1(bram_addr_ld_en_mod),
.I2(bram_addr_a[6]),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ),
.I4(bram_addr_a[7]),
.I5(bram_addr_a[8]),
.O(D[8]));
LUT6 #(
.INIT(64'hAAABAAAAAAAAAAAA))
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_1
(.I0(bram_addr_ld_en_mod),
.I1(curr_fixed_burst_reg),
.I2(out[1]),
.I3(out[2]),
.I4(out[0]),
.I5(s_axi_wvalid),
.O(E));
LUT5 #(
.INIT(32'hB88BB8B8))
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_2
(.I0(bram_addr_ld[9]),
.I1(bram_addr_ld_en_mod),
.I2(bram_addr_a[9]),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]_0 ),
.I4(bram_addr_a[8]),
.O(D[9]));
LUT5 #(
.INIT(32'hB8BBB888))
\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_1
(.I0(save_init_bram_addr_ld[12]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0 ),
.I2(\GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg ),
.I3(axi_awaddr_full),
.I4(s_axi_awaddr[10]),
.O(D[10]));
LUT5 #(
.INIT(32'hB8BBB888))
\GEN_DUAL_ADDR_CNT.bram_addr_int[13]_i_1
(.I0(save_init_bram_addr_ld[13]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0 ),
.I2(\GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg ),
.I3(axi_awaddr_full),
.I4(s_axi_awaddr[11]),
.O(D[11]));
LUT5 #(
.INIT(32'hB8BBB888))
\GEN_DUAL_ADDR_CNT.bram_addr_int[14]_i_1
(.I0(save_init_bram_addr_ld[14]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0 ),
.I2(\GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg ),
.I3(axi_awaddr_full),
.I4(s_axi_awaddr[12]),
.O(D[12]));
LUT5 #(
.INIT(32'h4500FFFF))
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_1__0
(.I0(bram_addr_ld_en_mod),
.I1(curr_fixed_burst_reg),
.I2(bram_addr_inc),
.I3(bram_addr_rst_cmb),
.I4(s_axi_aresetn),
.O(SR));
LUT6 #(
.INIT(64'hAAABAAAAAAAAAAAA))
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_2
(.I0(bram_addr_ld_en),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_6_n_0 ),
.I2(out[1]),
.I3(out[2]),
.I4(out[0]),
.I5(s_axi_wvalid),
.O(bram_addr_ld_en_mod));
LUT5 #(
.INIT(32'hB8BBB888))
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3
(.I0(save_init_bram_addr_ld[15]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0 ),
.I2(\GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg ),
.I3(axi_awaddr_full),
.I4(s_axi_awaddr[13]),
.O(D[13]));
LUT6 #(
.INIT(64'h55555555FFFFFFDF))
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_6
(.I0(curr_wrap_burst_reg),
.I1(wrap_burst_total[1]),
.I2(wrap_burst_total[2]),
.I3(wrap_burst_total[0]),
.I4(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] ),
.I5(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_8_n_0 ),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT2 #(
.INIT(4'h1))
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7
(.I0(bram_addr_ld_en),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_6_n_0 ),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0 ));
LUT6 #(
.INIT(64'h000000008F00C000))
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_8
(.I0(bram_addr_a[2]),
.I1(bram_addr_a[1]),
.I2(wrap_burst_total[1]),
.I3(bram_addr_a[0]),
.I4(wrap_burst_total[0]),
.I5(wrap_burst_total[2]),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_8_n_0 ));
LUT6 #(
.INIT(64'hB800B800B800FFFF))
\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_1
(.I0(\GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg ),
.I1(axi_awaddr_full),
.I2(s_axi_awaddr[0]),
.I3(bram_addr_ld_en),
.I4(bram_addr_ld_en_mod),
.I5(bram_addr_a[0]),
.O(D[0]));
LUT4 #(
.INIT(16'h8BB8))
\GEN_DUAL_ADDR_CNT.bram_addr_int[3]_i_1
(.I0(bram_addr_ld[1]),
.I1(bram_addr_ld_en_mod),
.I2(bram_addr_a[1]),
.I3(bram_addr_a[0]),
.O(D[1]));
LUT5 #(
.INIT(32'h8BB8B8B8))
\GEN_DUAL_ADDR_CNT.bram_addr_int[4]_i_1
(.I0(bram_addr_ld[2]),
.I1(bram_addr_ld_en_mod),
.I2(bram_addr_a[2]),
.I3(bram_addr_a[0]),
.I4(bram_addr_a[1]),
.O(D[2]));
LUT6 #(
.INIT(64'h8BB8B8B8B8B8B8B8))
\GEN_DUAL_ADDR_CNT.bram_addr_int[5]_i_1
(.I0(bram_addr_ld[3]),
.I1(bram_addr_ld_en_mod),
.I2(bram_addr_a[3]),
.I3(bram_addr_a[2]),
.I4(bram_addr_a[0]),
.I5(bram_addr_a[1]),
.O(D[3]));
LUT4 #(
.INIT(16'hB88B))
\GEN_DUAL_ADDR_CNT.bram_addr_int[6]_i_1
(.I0(bram_addr_ld[4]),
.I1(bram_addr_ld_en_mod),
.I2(bram_addr_a[4]),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] ),
.O(D[4]));
LUT5 #(
.INIT(32'hB88BB8B8))
\GEN_DUAL_ADDR_CNT.bram_addr_int[7]_i_1
(.I0(bram_addr_ld[5]),
.I1(bram_addr_ld_en_mod),
.I2(bram_addr_a[5]),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] ),
.I4(bram_addr_a[4]),
.O(D[5]));
LUT6 #(
.INIT(64'hB8B88BB8B8B8B8B8))
\GEN_DUAL_ADDR_CNT.bram_addr_int[8]_i_1
(.I0(bram_addr_ld[6]),
.I1(bram_addr_ld_en_mod),
.I2(bram_addr_a[6]),
.I3(bram_addr_a[4]),
.I4(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] ),
.I5(bram_addr_a[5]),
.O(D[6]));
LUT4 #(
.INIT(16'h7FFF))
\GEN_DUAL_ADDR_CNT.bram_addr_int[8]_i_2__0
(.I0(bram_addr_a[1]),
.I1(bram_addr_a[0]),
.I2(bram_addr_a[2]),
.I3(bram_addr_a[3]),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] ));
LUT5 #(
.INIT(32'hB88BB8B8))
\GEN_DUAL_ADDR_CNT.bram_addr_int[9]_i_1
(.I0(bram_addr_ld[7]),
.I1(bram_addr_ld_en_mod),
.I2(bram_addr_a[7]),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ),
.I4(bram_addr_a[6]),
.O(D[7]));
LUT4 #(
.INIT(16'h00E2))
curr_fixed_burst_reg_i_1__0
(.I0(curr_fixed_burst_reg),
.I1(bram_addr_ld_en),
.I2(curr_fixed_burst),
.I3(SR),
.O(curr_fixed_burst_reg_reg));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT4 #(
.INIT(16'h00E2))
curr_wrap_burst_reg_i_1__0
(.I0(curr_wrap_burst_reg),
.I1(bram_addr_ld_en),
.I2(curr_wrap_burst),
.I3(SR),
.O(curr_wrap_burst_reg_reg));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[10]_i_1
(.I0(save_init_bram_addr_ld[10]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0 ),
.I2(\GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg ),
.I3(axi_awaddr_full),
.I4(s_axi_awaddr[8]),
.O(bram_addr_ld[8]));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[11]_i_1
(.I0(save_init_bram_addr_ld[11]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0 ),
.I2(\GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg ),
.I3(axi_awaddr_full),
.I4(s_axi_awaddr[9]),
.O(bram_addr_ld[9]));
LUT6 #(
.INIT(64'h0808080808AA0808))
\save_init_bram_addr_ld[15]_i_1
(.I0(\GEN_AWREADY.axi_aresetn_d2_reg ),
.I1(\save_init_bram_addr_ld_reg[15]_0 ),
.I2(wr_addr_sm_cs),
.I3(\save_init_bram_addr_ld_reg[15]_1 ),
.I4(last_data_ack_mod),
.I5(\save_init_bram_addr_ld_reg[15]_2 ),
.O(bram_addr_ld_en));
LUT6 #(
.INIT(64'h007F007F007F0000))
\save_init_bram_addr_ld[15]_i_2
(.I0(bvalid_cnt[2]),
.I1(bvalid_cnt[0]),
.I2(bvalid_cnt[1]),
.I3(aw_active),
.I4(axi_awaddr_full),
.I5(s_axi_awvalid),
.O(\save_init_bram_addr_ld_reg[15]_0 ));
LUT3 #(
.INIT(8'h80))
\save_init_bram_addr_ld[15]_i_3
(.I0(bvalid_cnt[2]),
.I1(bvalid_cnt[0]),
.I2(bvalid_cnt[1]),
.O(\save_init_bram_addr_ld_reg[15]_1 ));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT4 #(
.INIT(16'hFFFD))
\save_init_bram_addr_ld[15]_i_4
(.I0(axi_awaddr_full),
.I1(\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg ),
.I2(axi_awlen_pipe_1_or_2),
.I3(curr_awlen_reg_1_or_2),
.O(\save_init_bram_addr_ld_reg[15]_2 ));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[3]_i_1
(.I0(\save_init_bram_addr_ld[3]_i_2__0_n_0 ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0 ),
.I2(\GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg ),
.I3(axi_awaddr_full),
.I4(s_axi_awaddr[1]),
.O(bram_addr_ld[1]));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT4 #(
.INIT(16'hC80C))
\save_init_bram_addr_ld[3]_i_2__0
(.I0(wrap_burst_total[0]),
.I1(save_init_bram_addr_ld[3]),
.I2(wrap_burst_total[1]),
.I3(wrap_burst_total[2]),
.O(\save_init_bram_addr_ld[3]_i_2__0_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[4]_i_1
(.I0(\save_init_bram_addr_ld[4]_i_2__0_n_0 ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0 ),
.I2(\GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg ),
.I3(axi_awaddr_full),
.I4(s_axi_awaddr[2]),
.O(bram_addr_ld[2]));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT4 #(
.INIT(16'hA28A))
\save_init_bram_addr_ld[4]_i_2__0
(.I0(save_init_bram_addr_ld[4]),
.I1(wrap_burst_total[0]),
.I2(wrap_burst_total[2]),
.I3(wrap_burst_total[1]),
.O(\save_init_bram_addr_ld[4]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'h8F808F8F8F808080))
\save_init_bram_addr_ld[5]_i_1
(.I0(save_init_bram_addr_ld[5]),
.I1(\save_init_bram_addr_ld[5]_i_2__0_n_0 ),
.I2(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0 ),
.I3(\GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg ),
.I4(axi_awaddr_full),
.I5(s_axi_awaddr[3]),
.O(bram_addr_ld[3]));
LUT3 #(
.INIT(8'hFB))
\save_init_bram_addr_ld[5]_i_2__0
(.I0(wrap_burst_total[0]),
.I1(wrap_burst_total[2]),
.I2(wrap_burst_total[1]),
.O(\save_init_bram_addr_ld[5]_i_2__0_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[6]_i_1
(.I0(save_init_bram_addr_ld[6]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0 ),
.I2(\GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg ),
.I3(axi_awaddr_full),
.I4(s_axi_awaddr[4]),
.O(bram_addr_ld[4]));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[7]_i_1
(.I0(save_init_bram_addr_ld[7]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0 ),
.I2(\GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg ),
.I3(axi_awaddr_full),
.I4(s_axi_awaddr[5]),
.O(bram_addr_ld[5]));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[8]_i_1
(.I0(save_init_bram_addr_ld[8]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0 ),
.I2(\GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg ),
.I3(axi_awaddr_full),
.I4(s_axi_awaddr[6]),
.O(bram_addr_ld[6]));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[9]_i_1
(.I0(save_init_bram_addr_ld[9]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0 ),
.I2(\GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg ),
.I3(axi_awaddr_full),
.I4(s_axi_awaddr[7]),
.O(bram_addr_ld[7]));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[10]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(bram_addr_ld[8]),
.Q(save_init_bram_addr_ld[10]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[11]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(bram_addr_ld[9]),
.Q(save_init_bram_addr_ld[11]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[12]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(D[10]),
.Q(save_init_bram_addr_ld[12]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[13]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(D[11]),
.Q(save_init_bram_addr_ld[13]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[14]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(D[12]),
.Q(save_init_bram_addr_ld[14]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[15]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(D[13]),
.Q(save_init_bram_addr_ld[15]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[3]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(bram_addr_ld[1]),
.Q(save_init_bram_addr_ld[3]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[4]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(bram_addr_ld[2]),
.Q(save_init_bram_addr_ld[4]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[5]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(bram_addr_ld[3]),
.Q(save_init_bram_addr_ld[5]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[6]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(bram_addr_ld[4]),
.Q(save_init_bram_addr_ld[6]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[7]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(bram_addr_ld[5]),
.Q(save_init_bram_addr_ld[7]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[8]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(bram_addr_ld[6]),
.Q(save_init_bram_addr_ld[8]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[9]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(bram_addr_ld[7]),
.Q(save_init_bram_addr_ld[9]),
.R(s_axi_aresetn_0));
LUT6 #(
.INIT(64'h0000A22200000000))
\wrap_burst_total[0]_i_1__0
(.I0(\wrap_burst_total[0]_i_2__0_n_0 ),
.I1(\wrap_burst_total[0]_i_3_n_0 ),
.I2(Q[1]),
.I3(Q[2]),
.I4(\wrap_burst_total[2]_i_2__0_n_0 ),
.I5(\wrap_burst_total[1]_i_2_n_0 ),
.O(\wrap_burst_total[0]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hCCA533A5FFA5FFA5))
\wrap_burst_total[0]_i_2__0
(.I0(s_axi_awlen[2]),
.I1(Q[2]),
.I2(s_axi_awlen[1]),
.I3(axi_awaddr_full),
.I4(Q[1]),
.I5(axi_awsize_pipe),
.O(\wrap_burst_total[0]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT2 #(
.INIT(4'h2))
\wrap_burst_total[0]_i_3
(.I0(axi_awaddr_full),
.I1(axi_awsize_pipe),
.O(\wrap_burst_total[0]_i_3_n_0 ));
LUT6 #(
.INIT(64'h08000800F3000000))
\wrap_burst_total[1]_i_1__0
(.I0(\wrap_burst_total[2]_i_3__0_n_0 ),
.I1(axi_awaddr_full),
.I2(axi_awsize_pipe),
.I3(\wrap_burst_total[1]_i_2_n_0 ),
.I4(\wrap_burst_total[1]_i_3_n_0 ),
.I5(\wrap_burst_total[2]_i_2__0_n_0 ),
.O(\wrap_burst_total[1]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair61" *)
LUT3 #(
.INIT(8'hB8))
\wrap_burst_total[1]_i_2
(.I0(Q[0]),
.I1(axi_awaddr_full),
.I2(s_axi_awlen[0]),
.O(\wrap_burst_total[1]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT3 #(
.INIT(8'hB8))
\wrap_burst_total[1]_i_3
(.I0(Q[1]),
.I1(axi_awaddr_full),
.I2(s_axi_awlen[1]),
.O(\wrap_burst_total[1]_i_3_n_0 ));
LUT6 #(
.INIT(64'hA000000088008800))
\wrap_burst_total[2]_i_1__0
(.I0(\wrap_burst_total[2]_i_2__0_n_0 ),
.I1(s_axi_awlen[0]),
.I2(Q[0]),
.I3(\wrap_burst_total[2]_i_3__0_n_0 ),
.I4(axi_awsize_pipe),
.I5(axi_awaddr_full),
.O(\wrap_burst_total[2]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair61" *)
LUT3 #(
.INIT(8'hB8))
\wrap_burst_total[2]_i_2__0
(.I0(Q[3]),
.I1(axi_awaddr_full),
.I2(s_axi_awlen[3]),
.O(\wrap_burst_total[2]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT5 #(
.INIT(32'hCCA000A0))
\wrap_burst_total[2]_i_3__0
(.I0(s_axi_awlen[2]),
.I1(Q[2]),
.I2(s_axi_awlen[1]),
.I3(axi_awaddr_full),
.I4(Q[1]),
.O(\wrap_burst_total[2]_i_3__0_n_0 ));
FDRE #(
.INIT(1'b0))
\wrap_burst_total_reg[0]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\wrap_burst_total[0]_i_1__0_n_0 ),
.Q(wrap_burst_total[0]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\wrap_burst_total_reg[1]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\wrap_burst_total[1]_i_1__0_n_0 ),
.Q(wrap_burst_total[1]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\wrap_burst_total_reg[2]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\wrap_burst_total[2]_i_1__0_n_0 ),
.Q(wrap_burst_total[2]),
.R(s_axi_aresetn_0));
endmodule
(* ORIG_REF_NAME = "wrap_brst" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wrap_brst_0
(SR,
\wrap_burst_total_reg[0]_0 ,
\wrap_burst_total_reg[0]_1 ,
\wrap_burst_total_reg[0]_2 ,
\wrap_burst_total_reg[0]_3 ,
E,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11] ,
D,
bram_addr_ld_en,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ,
\rd_data_sm_cs_reg[1] ,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0 ,
\save_init_bram_addr_ld_reg[15]_0 ,
axi_b2b_brst_reg,
\rd_data_sm_cs_reg[3] ,
rd_adv_buf67_out,
s_axi_aresetn,
Q,
axi_arsize_pipe,
s_axi_arlen,
axi_araddr_full,
curr_fixed_burst_reg,
s_axi_araddr,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg ,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 ,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg ,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg ,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg ,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg ,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg ,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg ,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0 ,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg ,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg ,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] ,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg ,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg ,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg ,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg ,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg ,
curr_wrap_burst_reg,
\rd_data_sm_cs_reg[3]_0 ,
axi_rd_burst_two_reg,
axi_rd_burst,
axi_aresetn_d2,
rd_addr_sm_cs,
last_bram_addr,
ar_active,
pend_rd_op,
no_ar_ack,
s_axi_arvalid,
brst_zero,
axi_rvalid_int_reg,
s_axi_rready,
end_brst_rd,
axi_b2b_brst,
axi_arsize_pipe_max,
disable_b2b_brst,
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg ,
axi_arlen_pipe_1_or_2,
s_axi_aclk);
output [0:0]SR;
output \wrap_burst_total_reg[0]_0 ;
output \wrap_burst_total_reg[0]_1 ;
output \wrap_burst_total_reg[0]_2 ;
output \wrap_burst_total_reg[0]_3 ;
output [1:0]E;
output \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11] ;
output [13:0]D;
output bram_addr_ld_en;
output \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ;
output \rd_data_sm_cs_reg[1] ;
output \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0 ;
output \save_init_bram_addr_ld_reg[15]_0 ;
output axi_b2b_brst_reg;
output \rd_data_sm_cs_reg[3] ;
output rd_adv_buf67_out;
input s_axi_aresetn;
input [3:0]Q;
input [0:0]axi_arsize_pipe;
input [3:0]s_axi_arlen;
input axi_araddr_full;
input curr_fixed_burst_reg;
input [13:0]s_axi_araddr;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg ;
input [9:0]\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 ;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg ;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg ;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg ;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg ;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg ;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg ;
input \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0 ;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg ;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg ;
input \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] ;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg ;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg ;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg ;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg ;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg ;
input curr_wrap_burst_reg;
input [3:0]\rd_data_sm_cs_reg[3]_0 ;
input axi_rd_burst_two_reg;
input axi_rd_burst;
input axi_aresetn_d2;
input rd_addr_sm_cs;
input last_bram_addr;
input ar_active;
input pend_rd_op;
input no_ar_ack;
input s_axi_arvalid;
input brst_zero;
input axi_rvalid_int_reg;
input s_axi_rready;
input end_brst_rd;
input axi_b2b_brst;
input axi_arsize_pipe_max;
input disable_b2b_brst;
input \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg ;
input axi_arlen_pipe_1_or_2;
input s_axi_aclk;
wire [13:0]D;
wire [1:0]E;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5_n_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6_n_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_5__0_n_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11] ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0 ;
wire [9:0]\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] ;
wire [3:0]Q;
wire [0:0]SR;
wire ar_active;
wire axi_araddr_full;
wire axi_aresetn_d2;
wire axi_arlen_pipe_1_or_2;
wire [0:0]axi_arsize_pipe;
wire axi_arsize_pipe_max;
wire axi_b2b_brst;
wire axi_b2b_brst_reg;
wire axi_rd_burst;
wire axi_rd_burst_two_reg;
wire axi_rvalid_int_reg;
wire bram_addr_ld_en;
wire brst_zero;
wire curr_fixed_burst_reg;
wire curr_wrap_burst_reg;
wire disable_b2b_brst;
wire end_brst_rd;
wire last_bram_addr;
wire no_ar_ack;
wire pend_rd_op;
wire rd_addr_sm_cs;
wire rd_adv_buf67_out;
wire \rd_data_sm_cs_reg[1] ;
wire \rd_data_sm_cs_reg[3] ;
wire [3:0]\rd_data_sm_cs_reg[3]_0 ;
wire s_axi_aclk;
wire [13:0]s_axi_araddr;
wire s_axi_aresetn;
wire [3:0]s_axi_arlen;
wire s_axi_arvalid;
wire s_axi_rready;
wire \save_init_bram_addr_ld[10]_i_1__0_n_0 ;
wire \save_init_bram_addr_ld[11]_i_1__0_n_0 ;
wire \save_init_bram_addr_ld[15]_i_2__0_n_0 ;
wire \save_init_bram_addr_ld[3]_i_1__0_n_0 ;
wire \save_init_bram_addr_ld[3]_i_2_n_0 ;
wire \save_init_bram_addr_ld[4]_i_1__0_n_0 ;
wire \save_init_bram_addr_ld[4]_i_2_n_0 ;
wire \save_init_bram_addr_ld[5]_i_1__0_n_0 ;
wire \save_init_bram_addr_ld[5]_i_2_n_0 ;
wire \save_init_bram_addr_ld[6]_i_1__0_n_0 ;
wire \save_init_bram_addr_ld[7]_i_1__0_n_0 ;
wire \save_init_bram_addr_ld[8]_i_1__0_n_0 ;
wire \save_init_bram_addr_ld[9]_i_1__0_n_0 ;
wire \save_init_bram_addr_ld_reg[15]_0 ;
wire \save_init_bram_addr_ld_reg_n_0_[10] ;
wire \save_init_bram_addr_ld_reg_n_0_[11] ;
wire \save_init_bram_addr_ld_reg_n_0_[12] ;
wire \save_init_bram_addr_ld_reg_n_0_[13] ;
wire \save_init_bram_addr_ld_reg_n_0_[14] ;
wire \save_init_bram_addr_ld_reg_n_0_[15] ;
wire \save_init_bram_addr_ld_reg_n_0_[3] ;
wire \save_init_bram_addr_ld_reg_n_0_[4] ;
wire \save_init_bram_addr_ld_reg_n_0_[5] ;
wire \save_init_bram_addr_ld_reg_n_0_[6] ;
wire \save_init_bram_addr_ld_reg_n_0_[7] ;
wire \save_init_bram_addr_ld_reg_n_0_[8] ;
wire \save_init_bram_addr_ld_reg_n_0_[9] ;
wire \wrap_burst_total[0]_i_1_n_0 ;
wire \wrap_burst_total[0]_i_3__0_n_0 ;
wire \wrap_burst_total[1]_i_1_n_0 ;
wire \wrap_burst_total[2]_i_1_n_0 ;
wire \wrap_burst_total[2]_i_2_n_0 ;
wire \wrap_burst_total_reg[0]_0 ;
wire \wrap_burst_total_reg[0]_1 ;
wire \wrap_burst_total_reg[0]_2 ;
wire \wrap_burst_total_reg[0]_3 ;
wire \wrap_burst_total_reg_n_0_[0] ;
wire \wrap_burst_total_reg_n_0_[1] ;
wire \wrap_burst_total_reg_n_0_[2] ;
LUT6 #(
.INIT(64'hDF20FFFFDF200000))
\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_1__0
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [6]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0 ),
.I2(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [7]),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [8]),
.I4(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0 ),
.I5(\save_init_bram_addr_ld[10]_i_1__0_n_0 ),
.O(D[8]));
LUT3 #(
.INIT(8'h5D))
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_1__0
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0 ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11] ),
.I2(curr_fixed_burst_reg),
.O(E[0]));
LUT5 #(
.INIT(32'h9AFF9A00))
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_2__0
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [9]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] ),
.I2(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [8]),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0 ),
.I4(\save_init_bram_addr_ld[11]_i_1__0_n_0 ),
.O(D[9]));
LUT6 #(
.INIT(64'hE0E0F0F0E0E0FFF0))
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5_n_0 ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6_n_0 ),
.I2(\rd_data_sm_cs_reg[1] ),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0 ),
.I4(\rd_data_sm_cs_reg[3]_0 [1]),
.I5(\rd_data_sm_cs_reg[3]_0 [3]),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11] ));
LUT2 #(
.INIT(4'h1))
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5
(.I0(axi_rd_burst_two_reg),
.I1(\rd_data_sm_cs_reg[3]_0 [0]),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5_n_0 ));
LUT6 #(
.INIT(64'h0000000080800080))
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6
(.I0(\rd_data_sm_cs_reg[3]_0 [0]),
.I1(axi_rvalid_int_reg),
.I2(s_axi_rready),
.I3(end_brst_rd),
.I4(axi_b2b_brst),
.I5(brst_zero),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_1__0
(.I0(\save_init_bram_addr_ld_reg_n_0_[12] ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0 ),
.I2(\GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg ),
.I3(axi_araddr_full),
.I4(s_axi_araddr[10]),
.O(D[10]));
LUT5 #(
.INIT(32'hB8BBB888))
\GEN_DUAL_ADDR_CNT.bram_addr_int[13]_i_1__0
(.I0(\save_init_bram_addr_ld_reg_n_0_[13] ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0 ),
.I2(\GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg ),
.I3(axi_araddr_full),
.I4(s_axi_araddr[11]),
.O(D[11]));
LUT5 #(
.INIT(32'hB8BBB888))
\GEN_DUAL_ADDR_CNT.bram_addr_int[14]_i_1__0
(.I0(\save_init_bram_addr_ld_reg_n_0_[14] ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0 ),
.I2(\GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg ),
.I3(axi_araddr_full),
.I4(s_axi_araddr[12]),
.O(D[12]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT1 #(
.INIT(2'h1))
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_1
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0 ),
.O(E[1]));
LUT5 #(
.INIT(32'hB8BBB888))
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_2__0
(.I0(\save_init_bram_addr_ld_reg_n_0_[15] ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0 ),
.I2(\GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg ),
.I3(axi_araddr_full),
.I4(s_axi_araddr[13]),
.O(D[13]));
LUT2 #(
.INIT(4'h1))
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0
(.I0(bram_addr_ld_en),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0 ),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0 ));
LUT5 #(
.INIT(32'h88A80000))
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11] ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_5__0_n_0 ),
.I2(\save_init_bram_addr_ld[5]_i_2_n_0 ),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ),
.I4(curr_wrap_burst_reg),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0 ));
LUT6 #(
.INIT(64'h000000008F00A000))
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_5__0
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [1]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [2]),
.I2(\wrap_burst_total_reg_n_0_[1] ),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [0]),
.I4(\wrap_burst_total_reg_n_0_[0] ),
.I5(\wrap_burst_total_reg_n_0_[2] ),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_5__0_n_0 ));
LUT6 #(
.INIT(64'h00000000A808FD5D))
\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_1__0
(.I0(bram_addr_ld_en),
.I1(s_axi_araddr[0]),
.I2(axi_araddr_full),
.I3(\GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg ),
.I4(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [0]),
.I5(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0 ),
.O(D[0]));
LUT4 #(
.INIT(16'h6F60))
\GEN_DUAL_ADDR_CNT.bram_addr_int[3]_i_1__0
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [1]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [0]),
.I2(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0 ),
.I3(\save_init_bram_addr_ld[3]_i_1__0_n_0 ),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h6AFF6A00))
\GEN_DUAL_ADDR_CNT.bram_addr_int[4]_i_1__0
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [2]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [0]),
.I2(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [1]),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0 ),
.I4(\save_init_bram_addr_ld[4]_i_1__0_n_0 ),
.O(D[2]));
LUT6 #(
.INIT(64'h6AAAFFFF6AAA0000))
\GEN_DUAL_ADDR_CNT.bram_addr_int[5]_i_1__0
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [3]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [2]),
.I2(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [0]),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [1]),
.I4(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0 ),
.I5(\save_init_bram_addr_ld[5]_i_1__0_n_0 ),
.O(D[3]));
LUT4 #(
.INIT(16'h9F90))
\GEN_DUAL_ADDR_CNT.bram_addr_int[6]_i_1__0
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [4]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ),
.I2(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0 ),
.I3(\save_init_bram_addr_ld[6]_i_1__0_n_0 ),
.O(D[4]));
LUT5 #(
.INIT(32'h9AFF9A00))
\GEN_DUAL_ADDR_CNT.bram_addr_int[7]_i_1__0
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [5]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ),
.I2(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [4]),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0 ),
.I4(\save_init_bram_addr_ld[7]_i_1__0_n_0 ),
.O(D[5]));
LUT6 #(
.INIT(64'hA6AAFFFFA6AA0000))
\GEN_DUAL_ADDR_CNT.bram_addr_int[8]_i_1__0
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [6]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [4]),
.I2(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [5]),
.I4(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0 ),
.I5(\save_init_bram_addr_ld[8]_i_1__0_n_0 ),
.O(D[6]));
LUT4 #(
.INIT(16'h7FFF))
\GEN_DUAL_ADDR_CNT.bram_addr_int[8]_i_2
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [1]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [0]),
.I2(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [2]),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [3]),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ));
LUT5 #(
.INIT(32'h9AFF9A00))
\GEN_DUAL_ADDR_CNT.bram_addr_int[9]_i_1__0
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [7]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0 ),
.I2(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [6]),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0 ),
.I4(\save_init_bram_addr_ld[9]_i_1__0_n_0 ),
.O(D[7]));
LUT2 #(
.INIT(4'h8))
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_4
(.I0(axi_rvalid_int_reg),
.I1(s_axi_rready),
.O(rd_adv_buf67_out));
LUT5 #(
.INIT(32'hFFFDFFFF))
axi_b2b_brst_i_2
(.I0(axi_arsize_pipe_max),
.I1(disable_b2b_brst),
.I2(\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg ),
.I3(axi_arlen_pipe_1_or_2),
.I4(axi_araddr_full),
.O(axi_b2b_brst_reg));
LUT2 #(
.INIT(4'hB))
bram_en_int_i_5
(.I0(\rd_data_sm_cs_reg[3]_0 [3]),
.I1(\rd_data_sm_cs_reg[3]_0 [2]),
.O(\rd_data_sm_cs_reg[3] ));
LUT6 #(
.INIT(64'h0010000000000000))
bram_en_int_i_8
(.I0(end_brst_rd),
.I1(brst_zero),
.I2(\rd_data_sm_cs_reg[3]_0 [2]),
.I3(\rd_data_sm_cs_reg[3]_0 [0]),
.I4(axi_rvalid_int_reg),
.I5(s_axi_rready),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0 ));
LUT1 #(
.INIT(2'h1))
bram_rst_b_INST_0
(.I0(s_axi_aresetn),
.O(SR));
LUT6 #(
.INIT(64'h000F000E000F0000))
\rd_data_sm_cs[1]_i_2
(.I0(axi_rd_burst_two_reg),
.I1(axi_rd_burst),
.I2(\rd_data_sm_cs_reg[3]_0 [3]),
.I3(\rd_data_sm_cs_reg[3]_0 [2]),
.I4(\rd_data_sm_cs_reg[3]_0 [1]),
.I5(\rd_data_sm_cs_reg[3]_0 [0]),
.O(\rd_data_sm_cs_reg[1] ));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[10]_i_1__0
(.I0(\save_init_bram_addr_ld_reg_n_0_[10] ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0 ),
.I2(\GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg ),
.I3(axi_araddr_full),
.I4(s_axi_araddr[8]),
.O(\save_init_bram_addr_ld[10]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[11]_i_1__0
(.I0(\save_init_bram_addr_ld_reg_n_0_[11] ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0 ),
.I2(\GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg ),
.I3(axi_araddr_full),
.I4(s_axi_araddr[9]),
.O(\save_init_bram_addr_ld[11]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'h02AA0202))
\save_init_bram_addr_ld[15]_i_1__0
(.I0(axi_aresetn_d2),
.I1(rd_addr_sm_cs),
.I2(\save_init_bram_addr_ld[15]_i_2__0_n_0 ),
.I3(\save_init_bram_addr_ld_reg[15]_0 ),
.I4(last_bram_addr),
.O(bram_addr_ld_en));
LUT5 #(
.INIT(32'hFEFEFEFF))
\save_init_bram_addr_ld[15]_i_2__0
(.I0(ar_active),
.I1(pend_rd_op),
.I2(no_ar_ack),
.I3(s_axi_arvalid),
.I4(axi_araddr_full),
.O(\save_init_bram_addr_ld[15]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hAABAAABAFFFFAABA))
\save_init_bram_addr_ld[15]_i_3__0
(.I0(axi_b2b_brst_reg),
.I1(\rd_data_sm_cs_reg[3]_0 [0]),
.I2(\rd_data_sm_cs_reg[3]_0 [1]),
.I3(\rd_data_sm_cs_reg[3] ),
.I4(brst_zero),
.I5(rd_adv_buf67_out),
.O(\save_init_bram_addr_ld_reg[15]_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[3]_i_1__0
(.I0(\save_init_bram_addr_ld[3]_i_2_n_0 ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0 ),
.I2(\GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg ),
.I3(axi_araddr_full),
.I4(s_axi_araddr[1]),
.O(\save_init_bram_addr_ld[3]_i_1__0_n_0 ));
LUT4 #(
.INIT(16'hA282))
\save_init_bram_addr_ld[3]_i_2
(.I0(\save_init_bram_addr_ld_reg_n_0_[3] ),
.I1(\wrap_burst_total_reg_n_0_[1] ),
.I2(\wrap_burst_total_reg_n_0_[2] ),
.I3(\wrap_burst_total_reg_n_0_[0] ),
.O(\save_init_bram_addr_ld[3]_i_2_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[4]_i_1__0
(.I0(\save_init_bram_addr_ld[4]_i_2_n_0 ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0 ),
.I2(\GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg ),
.I3(axi_araddr_full),
.I4(s_axi_araddr[2]),
.O(\save_init_bram_addr_ld[4]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'hA28A))
\save_init_bram_addr_ld[4]_i_2
(.I0(\save_init_bram_addr_ld_reg_n_0_[4] ),
.I1(\wrap_burst_total_reg_n_0_[0] ),
.I2(\wrap_burst_total_reg_n_0_[2] ),
.I3(\wrap_burst_total_reg_n_0_[1] ),
.O(\save_init_bram_addr_ld[4]_i_2_n_0 ));
LUT6 #(
.INIT(64'h2F202F2F2F202020))
\save_init_bram_addr_ld[5]_i_1__0
(.I0(\save_init_bram_addr_ld_reg_n_0_[5] ),
.I1(\save_init_bram_addr_ld[5]_i_2_n_0 ),
.I2(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0 ),
.I3(\GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg ),
.I4(axi_araddr_full),
.I5(s_axi_araddr[3]),
.O(\save_init_bram_addr_ld[5]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'h04))
\save_init_bram_addr_ld[5]_i_2
(.I0(\wrap_burst_total_reg_n_0_[0] ),
.I1(\wrap_burst_total_reg_n_0_[2] ),
.I2(\wrap_burst_total_reg_n_0_[1] ),
.O(\save_init_bram_addr_ld[5]_i_2_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[6]_i_1__0
(.I0(\save_init_bram_addr_ld_reg_n_0_[6] ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0 ),
.I2(\GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg ),
.I3(axi_araddr_full),
.I4(s_axi_araddr[4]),
.O(\save_init_bram_addr_ld[6]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[7]_i_1__0
(.I0(\save_init_bram_addr_ld_reg_n_0_[7] ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0 ),
.I2(\GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg ),
.I3(axi_araddr_full),
.I4(s_axi_araddr[5]),
.O(\save_init_bram_addr_ld[7]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[8]_i_1__0
(.I0(\save_init_bram_addr_ld_reg_n_0_[8] ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0 ),
.I2(\GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg ),
.I3(axi_araddr_full),
.I4(s_axi_araddr[6]),
.O(\save_init_bram_addr_ld[8]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[9]_i_1__0
(.I0(\save_init_bram_addr_ld_reg_n_0_[9] ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0 ),
.I2(\GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg ),
.I3(axi_araddr_full),
.I4(s_axi_araddr[7]),
.O(\save_init_bram_addr_ld[9]_i_1__0_n_0 ));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[10]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\save_init_bram_addr_ld[10]_i_1__0_n_0 ),
.Q(\save_init_bram_addr_ld_reg_n_0_[10] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[11]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\save_init_bram_addr_ld[11]_i_1__0_n_0 ),
.Q(\save_init_bram_addr_ld_reg_n_0_[11] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[12]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(D[10]),
.Q(\save_init_bram_addr_ld_reg_n_0_[12] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[13]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(D[11]),
.Q(\save_init_bram_addr_ld_reg_n_0_[13] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[14]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(D[12]),
.Q(\save_init_bram_addr_ld_reg_n_0_[14] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[15]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(D[13]),
.Q(\save_init_bram_addr_ld_reg_n_0_[15] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[3]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\save_init_bram_addr_ld[3]_i_1__0_n_0 ),
.Q(\save_init_bram_addr_ld_reg_n_0_[3] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[4]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\save_init_bram_addr_ld[4]_i_1__0_n_0 ),
.Q(\save_init_bram_addr_ld_reg_n_0_[4] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[5]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\save_init_bram_addr_ld[5]_i_1__0_n_0 ),
.Q(\save_init_bram_addr_ld_reg_n_0_[5] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[6]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\save_init_bram_addr_ld[6]_i_1__0_n_0 ),
.Q(\save_init_bram_addr_ld_reg_n_0_[6] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[7]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\save_init_bram_addr_ld[7]_i_1__0_n_0 ),
.Q(\save_init_bram_addr_ld_reg_n_0_[7] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[8]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\save_init_bram_addr_ld[8]_i_1__0_n_0 ),
.Q(\save_init_bram_addr_ld_reg_n_0_[8] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[9]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\save_init_bram_addr_ld[9]_i_1__0_n_0 ),
.Q(\save_init_bram_addr_ld_reg_n_0_[9] ),
.R(SR));
LUT6 #(
.INIT(64'h3202010100000000))
\wrap_burst_total[0]_i_1
(.I0(\wrap_burst_total_reg[0]_0 ),
.I1(\wrap_burst_total_reg[0]_1 ),
.I2(\wrap_burst_total[0]_i_3__0_n_0 ),
.I3(Q[2]),
.I4(\wrap_burst_total_reg[0]_2 ),
.I5(\wrap_burst_total_reg[0]_3 ),
.O(\wrap_burst_total[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8'hB8))
\wrap_burst_total[0]_i_2
(.I0(Q[2]),
.I1(axi_araddr_full),
.I2(s_axi_arlen[2]),
.O(\wrap_burst_total_reg[0]_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT2 #(
.INIT(4'h2))
\wrap_burst_total[0]_i_3__0
(.I0(axi_araddr_full),
.I1(axi_arsize_pipe),
.O(\wrap_burst_total[0]_i_3__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT3 #(
.INIT(8'hB8))
\wrap_burst_total[0]_i_4
(.I0(Q[1]),
.I1(axi_araddr_full),
.I2(s_axi_arlen[1]),
.O(\wrap_burst_total_reg[0]_2 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT3 #(
.INIT(8'hB8))
\wrap_burst_total[0]_i_5
(.I0(Q[0]),
.I1(axi_araddr_full),
.I2(s_axi_arlen[0]),
.O(\wrap_burst_total_reg[0]_3 ));
LUT6 #(
.INIT(64'h220A880A000A880A))
\wrap_burst_total[1]_i_1
(.I0(\wrap_burst_total[2]_i_2_n_0 ),
.I1(axi_arsize_pipe),
.I2(s_axi_arlen[3]),
.I3(axi_araddr_full),
.I4(Q[3]),
.I5(Q[2]),
.O(\wrap_burst_total[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'h8088008880000000))
\wrap_burst_total[2]_i_1
(.I0(\wrap_burst_total[2]_i_2_n_0 ),
.I1(\wrap_burst_total_reg[0]_1 ),
.I2(axi_arsize_pipe),
.I3(axi_araddr_full),
.I4(Q[2]),
.I5(s_axi_arlen[2]),
.O(\wrap_burst_total[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'hCCA000A0))
\wrap_burst_total[2]_i_2
(.I0(s_axi_arlen[1]),
.I1(Q[1]),
.I2(s_axi_arlen[0]),
.I3(axi_araddr_full),
.I4(Q[0]),
.O(\wrap_burst_total[2]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8'hB8))
\wrap_burst_total[2]_i_3
(.I0(Q[3]),
.I1(axi_araddr_full),
.I2(s_axi_arlen[3]),
.O(\wrap_burst_total_reg[0]_1 ));
FDRE #(
.INIT(1'b0))
\wrap_burst_total_reg[0]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\wrap_burst_total[0]_i_1_n_0 ),
.Q(\wrap_burst_total_reg_n_0_[0] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\wrap_burst_total_reg[1]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\wrap_burst_total[1]_i_1_n_0 ),
.Q(\wrap_burst_total_reg_n_0_[1] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\wrap_burst_total_reg[2]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\wrap_burst_total[2]_i_1_n_0 ),
.Q(\wrap_burst_total_reg_n_0_[2] ),
.R(SR));
endmodule
(* CHECK_LICENSE_TYPE = "zynq_design_1_axi_bram_ctrl_0_1,axi_bram_ctrl,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "axi_bram_ctrl,Vivado 2017.2" *)
(* NotValidForBitStream *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(s_axi_aclk,
s_axi_aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
bram_rst_a,
bram_clk_a,
bram_en_a,
bram_we_a,
bram_addr_a,
bram_wrdata_a,
bram_rddata_a,
bram_rst_b,
bram_clk_b,
bram_en_b,
bram_we_b,
bram_addr_b,
bram_wrdata_b,
bram_rddata_b);
(* x_interface_info = "xilinx.com:signal:clock:1.0 CLKIF CLK" *) input s_axi_aclk;
(* x_interface_info = "xilinx.com:signal:reset:1.0 RSTIF RST" *) input s_axi_aresetn;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *) input [11:0]s_axi_awid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *) input [15:0]s_axi_awaddr;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *) input [7:0]s_axi_awlen;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *) input [2:0]s_axi_awsize;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *) input [1:0]s_axi_awburst;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *) input s_axi_awlock;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *) input [3:0]s_axi_awcache;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *) input [2:0]s_axi_awprot;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *) input s_axi_awvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *) output s_axi_awready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *) input [31:0]s_axi_wdata;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *) input [3:0]s_axi_wstrb;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *) input s_axi_wlast;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *) input s_axi_wvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *) output s_axi_wready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BID" *) output [11:0]s_axi_bid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *) output [1:0]s_axi_bresp;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *) output s_axi_bvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *) input s_axi_bready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *) input [11:0]s_axi_arid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *) input [15:0]s_axi_araddr;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *) input [7:0]s_axi_arlen;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *) input [2:0]s_axi_arsize;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *) input [1:0]s_axi_arburst;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *) input s_axi_arlock;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *) input [3:0]s_axi_arcache;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *) input [2:0]s_axi_arprot;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *) input s_axi_arvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *) output s_axi_arready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RID" *) output [11:0]s_axi_rid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *) output [31:0]s_axi_rdata;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *) output [1:0]s_axi_rresp;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *) output s_axi_rlast;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *) output s_axi_rvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *) input s_axi_rready;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA RST" *) output bram_rst_a;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) output bram_clk_a;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *) output bram_en_a;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *) output [3:0]bram_we_a;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *) output [15:0]bram_addr_a;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *) output [31:0]bram_wrdata_a;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *) input [31:0]bram_rddata_a;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB RST" *) output bram_rst_b;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK" *) output bram_clk_b;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB EN" *) output bram_en_b;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB WE" *) output [3:0]bram_we_b;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR" *) output [15:0]bram_addr_b;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN" *) output [31:0]bram_wrdata_b;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT" *) input [31:0]bram_rddata_b;
wire [15:0]bram_addr_a;
wire [15:0]bram_addr_b;
wire bram_clk_a;
wire bram_clk_b;
wire bram_en_a;
wire bram_en_b;
wire [31:0]bram_rddata_a;
wire [31:0]bram_rddata_b;
wire bram_rst_a;
wire bram_rst_b;
wire [3:0]bram_we_a;
wire [3:0]bram_we_b;
wire [31:0]bram_wrdata_a;
wire [31:0]bram_wrdata_b;
wire s_axi_aclk;
wire [15:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [3:0]s_axi_arcache;
wire s_axi_aresetn;
wire [11:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire s_axi_arlock;
wire [2:0]s_axi_arprot;
wire s_axi_arready;
wire [2:0]s_axi_arsize;
wire s_axi_arvalid;
wire [15:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [3:0]s_axi_awcache;
wire [11:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire s_axi_awlock;
wire [2:0]s_axi_awprot;
wire s_axi_awready;
wire [2:0]s_axi_awsize;
wire s_axi_awvalid;
wire [11:0]s_axi_bid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire [11:0]s_axi_rid;
wire s_axi_rlast;
wire s_axi_rready;
wire [1:0]s_axi_rresp;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wlast;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
wire NLW_U0_ecc_interrupt_UNCONNECTED;
wire NLW_U0_ecc_ue_UNCONNECTED;
wire NLW_U0_s_axi_ctrl_arready_UNCONNECTED;
wire NLW_U0_s_axi_ctrl_awready_UNCONNECTED;
wire NLW_U0_s_axi_ctrl_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_ctrl_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_ctrl_wready_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_ctrl_bresp_UNCONNECTED;
wire [31:0]NLW_U0_s_axi_ctrl_rdata_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_ctrl_rresp_UNCONNECTED;
(* C_BRAM_ADDR_WIDTH = "14" *)
(* C_BRAM_INST_MODE = "EXTERNAL" *)
(* C_ECC = "0" *)
(* C_ECC_ONOFF_RESET_VALUE = "0" *)
(* C_ECC_TYPE = "0" *)
(* C_FAMILY = "zynq" *)
(* C_FAULT_INJECT = "0" *)
(* C_MEMORY_DEPTH = "16384" *)
(* C_SELECT_XPM = "0" *)
(* C_SINGLE_PORT_BRAM = "0" *)
(* C_S_AXI_ADDR_WIDTH = "16" *)
(* C_S_AXI_CTRL_ADDR_WIDTH = "32" *)
(* C_S_AXI_CTRL_DATA_WIDTH = "32" *)
(* C_S_AXI_DATA_WIDTH = "32" *)
(* C_S_AXI_ID_WIDTH = "12" *)
(* C_S_AXI_PROTOCOL = "AXI4" *)
(* C_S_AXI_SUPPORTS_NARROW_BURST = "0" *)
(* downgradeipidentifiedwarnings = "yes" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl U0
(.bram_addr_a(bram_addr_a),
.bram_addr_b(bram_addr_b),
.bram_clk_a(bram_clk_a),
.bram_clk_b(bram_clk_b),
.bram_en_a(bram_en_a),
.bram_en_b(bram_en_b),
.bram_rddata_a(bram_rddata_a),
.bram_rddata_b(bram_rddata_b),
.bram_rst_a(bram_rst_a),
.bram_rst_b(bram_rst_b),
.bram_we_a(bram_we_a),
.bram_we_b(bram_we_b),
.bram_wrdata_a(bram_wrdata_a),
.bram_wrdata_b(bram_wrdata_b),
.ecc_interrupt(NLW_U0_ecc_interrupt_UNCONNECTED),
.ecc_ue(NLW_U0_ecc_ue_UNCONNECTED),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_arcache(s_axi_arcache),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arlock(s_axi_arlock),
.s_axi_arprot(s_axi_arprot),
.s_axi_arready(s_axi_arready),
.s_axi_arsize(s_axi_arsize),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awcache(s_axi_awcache),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awlock(s_axi_awlock),
.s_axi_awprot(s_axi_awprot),
.s_axi_awready(s_axi_awready),
.s_axi_awsize(s_axi_awsize),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bid(s_axi_bid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_ctrl_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_ctrl_arready(NLW_U0_s_axi_ctrl_arready_UNCONNECTED),
.s_axi_ctrl_arvalid(1'b0),
.s_axi_ctrl_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_ctrl_awready(NLW_U0_s_axi_ctrl_awready_UNCONNECTED),
.s_axi_ctrl_awvalid(1'b0),
.s_axi_ctrl_bready(1'b0),
.s_axi_ctrl_bresp(NLW_U0_s_axi_ctrl_bresp_UNCONNECTED[1:0]),
.s_axi_ctrl_bvalid(NLW_U0_s_axi_ctrl_bvalid_UNCONNECTED),
.s_axi_ctrl_rdata(NLW_U0_s_axi_ctrl_rdata_UNCONNECTED[31:0]),
.s_axi_ctrl_rready(1'b0),
.s_axi_ctrl_rresp(NLW_U0_s_axi_ctrl_rresp_UNCONNECTED[1:0]),
.s_axi_ctrl_rvalid(NLW_U0_s_axi_ctrl_rvalid_UNCONNECTED),
.s_axi_ctrl_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_ctrl_wready(NLW_U0_s_axi_ctrl_wready_UNCONNECTED),
.s_axi_ctrl_wvalid(1'b0),
.s_axi_rdata(s_axi_rdata),
.s_axi_rid(s_axi_rid),
.s_axi_rlast(s_axi_rlast),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wlast(s_axi_wlast),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wvalid(s_axi_wvalid));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : ecc_dec_fix.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v4_0_ecc_dec_fix
#(
parameter TCQ = 100,
parameter PAYLOAD_WIDTH = 64,
parameter CODE_WIDTH = 72,
parameter DATA_WIDTH = 64,
parameter DQ_WIDTH = 72,
parameter ECC_WIDTH = 8,
parameter nCK_PER_CLK = 4
)
(
/*AUTOARG*/
// Outputs
rd_data, ecc_single, ecc_multiple,
// Inputs
clk, rst, h_rows, phy_rddata, correct_en, ecc_status_valid
);
input clk;
input rst;
// Compute syndromes.
input [CODE_WIDTH*ECC_WIDTH-1:0] h_rows;
input [2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_rddata;
wire [2*nCK_PER_CLK*ECC_WIDTH-1:0] syndrome_ns;
genvar k;
genvar m;
generate
for (k=0; k<2*nCK_PER_CLK; k=k+1) begin : ecc_word
for (m=0; m<ECC_WIDTH; m=m+1) begin : ecc_bit
assign syndrome_ns[k*ECC_WIDTH+m] =
^(phy_rddata[k*DQ_WIDTH+:CODE_WIDTH] & h_rows[m*CODE_WIDTH+:CODE_WIDTH]);
end
end
endgenerate
reg [2*nCK_PER_CLK*ECC_WIDTH-1:0] syndrome_r;
always @(posedge clk) syndrome_r <= #TCQ syndrome_ns;
// Extract payload bits from raw DRAM bits and register.
wire [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] ecc_rddata_ns;
genvar i;
generate
for (i=0; i<2*nCK_PER_CLK; i=i+1) begin : extract_payload
assign ecc_rddata_ns[i*PAYLOAD_WIDTH+:PAYLOAD_WIDTH] =
phy_rddata[i*DQ_WIDTH+:PAYLOAD_WIDTH];
end
endgenerate
reg [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] ecc_rddata_r;
always @(posedge clk) ecc_rddata_r <= #TCQ ecc_rddata_ns;
// Regenerate h_matrix from h_rows leaving out the identity part
// since we're not going to correct the ECC bits themselves.
genvar n;
genvar p;
wire [ECC_WIDTH-1:0] h_matrix [DATA_WIDTH-1:0];
generate
for (n=0; n<DATA_WIDTH; n=n+1) begin : h_col
for (p=0; p<ECC_WIDTH; p=p+1) begin : h_bit
assign h_matrix [n][p] = h_rows [p*CODE_WIDTH+n];
end
end
endgenerate
// Compute flip bits.
wire [2*nCK_PER_CLK*DATA_WIDTH-1:0] flip_bits;
genvar q;
genvar r;
generate
for (q=0; q<2*nCK_PER_CLK; q=q+1) begin : flip_word
for (r=0; r<DATA_WIDTH; r=r+1) begin : flip_bit
assign flip_bits[q*DATA_WIDTH+r] =
h_matrix[r] == syndrome_r[q*ECC_WIDTH+:ECC_WIDTH];
end
end
endgenerate
// Correct data.
output reg [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] rd_data;
input correct_en;
integer s;
always @(/*AS*/correct_en or ecc_rddata_r or flip_bits)
for (s=0; s<2*nCK_PER_CLK; s=s+1)
if (correct_en)
rd_data[s*PAYLOAD_WIDTH+:DATA_WIDTH] =
ecc_rddata_r[s*PAYLOAD_WIDTH+:DATA_WIDTH] ^
flip_bits[s*DATA_WIDTH+:DATA_WIDTH];
else rd_data[s*PAYLOAD_WIDTH+:DATA_WIDTH] =
ecc_rddata_r[s*PAYLOAD_WIDTH+:DATA_WIDTH];
// Copy raw payload bits if ECC_TEST is ON.
localparam RAW_BIT_WIDTH = PAYLOAD_WIDTH - DATA_WIDTH;
genvar t;
generate
if (RAW_BIT_WIDTH > 0)
for (t=0; t<2*nCK_PER_CLK; t=t+1) begin : copy_raw_bits
always @(/*AS*/ecc_rddata_r)
rd_data[(t+1)*PAYLOAD_WIDTH-1-:RAW_BIT_WIDTH] =
ecc_rddata_r[(t+1)*PAYLOAD_WIDTH-1-:RAW_BIT_WIDTH];
end
endgenerate
// Generate status information.
input ecc_status_valid;
output wire [2*nCK_PER_CLK-1:0] ecc_single;
output wire [2*nCK_PER_CLK-1:0] ecc_multiple;
genvar v;
generate
for (v=0; v<2*nCK_PER_CLK; v=v+1) begin : compute_status
wire zero = ~|syndrome_r[v*ECC_WIDTH+:ECC_WIDTH];
wire odd = ^syndrome_r[v*ECC_WIDTH+:ECC_WIDTH];
assign ecc_single[v] = ecc_status_valid && ~zero && odd;
assign ecc_multiple[v] = ecc_status_valid && ~zero && ~odd;
end
endgenerate
endmodule
|
// -- (c) Copyright 2008 - 2014 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: This is a generic n-deep SRL instantiation
// Verilog-standard: Verilog 2001
// $Revision:
// $Date:
//
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_data_fifo_v2_1_ndeep_srl #
(
parameter C_FAMILY = "rtl", // FPGA Family
parameter C_A_WIDTH = 1 // Address Width (>= 1)
)
(
input wire CLK, // Clock
input wire [C_A_WIDTH-1:0] A, // Address
input wire CE, // Clock Enable
input wire D, // Input Data
output wire Q // Output Data
);
localparam integer P_SRLASIZE = 5;
localparam integer P_SRLDEPTH = 32;
localparam integer P_NUMSRLS = (C_A_WIDTH>P_SRLASIZE) ? (2**(C_A_WIDTH-P_SRLASIZE)) : 1;
localparam integer P_SHIFT_DEPTH = 2**C_A_WIDTH;
wire [P_NUMSRLS:0] d_i;
wire [P_NUMSRLS-1:0] q_i;
wire [(C_A_WIDTH>P_SRLASIZE) ? (C_A_WIDTH-1) : (P_SRLASIZE-1) : 0] a_i;
genvar i;
// Instantiate SRLs in carry chain format
assign d_i[0] = D;
assign a_i = A;
generate
if (C_FAMILY == "rtl") begin : gen_rtl_shifter
if (C_A_WIDTH <= P_SRLASIZE) begin : gen_inferred_srl
reg [P_SRLDEPTH-1:0] shift_reg = {P_SRLDEPTH{1'b0}};
always @(posedge CLK)
if (CE)
shift_reg <= {shift_reg[P_SRLDEPTH-2:0], D};
assign Q = shift_reg[a_i];
end else begin : gen_logic_shifter // Very wasteful
reg [P_SHIFT_DEPTH-1:0] shift_reg = {P_SHIFT_DEPTH{1'b0}};
always @(posedge CLK)
if (CE)
shift_reg <= {shift_reg[P_SHIFT_DEPTH-2:0], D};
assign Q = shift_reg[a_i];
end
end else begin : gen_primitive_shifter
for (i=0;i<P_NUMSRLS;i=i+1) begin : gen_srls
SRLC32E
srl_inst
(
.CLK (CLK),
.A (a_i[P_SRLASIZE-1:0]),
.CE (CE),
.D (d_i[i]),
.Q (q_i[i]),
.Q31 (d_i[i+1])
);
end
if (C_A_WIDTH>P_SRLASIZE) begin : gen_srl_mux
generic_baseblocks_v2_1_nto1_mux #
(
.C_RATIO (2**(C_A_WIDTH-P_SRLASIZE)),
.C_SEL_WIDTH (C_A_WIDTH-P_SRLASIZE),
.C_DATAOUT_WIDTH (1),
.C_ONEHOT (0)
)
srl_q_mux_inst
(
.SEL_ONEHOT ({2**(C_A_WIDTH-P_SRLASIZE){1'b0}}),
.SEL (a_i[C_A_WIDTH-1:P_SRLASIZE]),
.IN (q_i),
.OUT (Q)
);
end else begin : gen_no_srl_mux
assign Q = q_i[0];
end
end
endgenerate
endmodule
`default_nettype wire
|
//dispatch: read p_rs, p_rt, write new p_rd and reset this valid bit, read p_old, use p_rs, p_rt, p_rd_old to index valid array getting valid bit
//complete: set valid bit of the completed physical register number
//recovery: inedxed by recover_rd, if RegDest_ROB = 1, write the p_rd_flush to that entry, and restore the valid bit
module map_table(
output [5:0] p_rs, p_rt,
output p_rs_v, p_rt_v,
output [5:0] PR_old_rd,
input clk, rst,
input hazard_stall, //from hazard detection logic
//from dispatch stage
input isDispatch,
input [4:0] l_rs, l_rt, l_rd,
input RegDest,
input [5:0] p_rd_new,
//from recovery
input [4:0] recover_rd,
input [5:0] p_rd_flush,
input recover,
input RegDest_ROB,
//from complete stage
input [5:0] p_rd_compl,
input complete,
input RegDest_compl
);
reg [5:0] mt [0:31];
reg [63:0] PR_valid; //logically separate with map table
/////////////////////////////////writing/reading map table////////////////////////////
wire write_new_rd;
integer i;
assign write_new_rd = isDispatch && RegDest && !hazard_stall && !recover;
always @(posedge clk or negedge rst) begin
if (!rst) begin //initial begin
for (i = 0; i < 32; i = i + 1) begin
mt[i] <= i;
end
end
else if (write_new_rd)
mt[l_rd] <= p_rd_new;
else if (RegDest_ROB && recover)
mt[recover_rd] <= p_rd_flush;
end
assign p_rs = mt[l_rs];
assign p_rt = mt[l_rt];
assign PR_old_rd = mt[l_rd];
/////////////////////////////valid array/////////////////////////////////
always @(posedge clk or negedge rst) begin
if (!rst) begin
PR_valid <= 64'hFFFFFFFFFFFFFFFF;
end
else begin
if (write_new_rd)
PR_valid[p_rd_new] <= 1'b0;
if (complete && RegDest_compl) //it should be ok during recovery because if complete is 1, the valid will be set to 1 several times, finally it will
PR_valid[p_rd_compl] <= 1'b1; //be 1
end
end
assign p_rs_v = PR_valid[p_rs];
assign p_rt_v = PR_valid[p_rt];
endmodule
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module tmu2_geninterp18(
input sys_clk,
input load,
input next_point,
input signed [17:0] init,
input positive,
input [16:0] q,
input [16:0] r,
input [16:0] divisor,
output signed [17:0] o
);
reg positive_r;
reg [16:0] q_r;
reg [16:0] r_r;
reg [16:0] divisor_r;
always @(posedge sys_clk) begin
if(load) begin
positive_r <= positive;
q_r <= q;
r_r <= r;
divisor_r <= divisor;
end
end
reg [17:0] err;
reg correct;
reg signed [17:0] o_r;
assign o = o_r;
always @(posedge sys_clk) begin
if(load) begin
err = 18'd0;
o_r = init;
end else if(next_point) begin
err = err + r_r;
correct = (err[16:0] > {1'b0, divisor_r[16:1]}) & ~err[17];
if(positive_r) begin
o_r = o_r + {1'b0, q_r};
if(correct)
o_r = o_r + 18'd1;
end else begin
o_r = o_r - {1'b0, q_r};
if(correct)
o_r = o_r - 18'd1;
end
if(correct)
err = err - {1'b0, divisor_r};
end
end
endmodule
|
//
// Generated by Bluespec Compiler, version 2011.03.beta1 (build 23381, 2011-03-08)
//
// On Tue Apr 26 10:52:10 EDT 2011
//
//
// Ports:
// Name I/O size props
// pcie_tx O 4
// led O 8
// p200clk O 1
// CLK_GATE_p200clk O 1 const
// p200rst O 1
// sys0_clk I 1
// sys0_rstn I 1
// pcie_clk I 1 clock
// pcie_rstn I 1 reset
// pcie_rx_i I 4
// usr_sw_i I 8 reg
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
module mkFTop_htgs4(sys0_clk,
sys0_rstn,
pcie_clk,
pcie_rstn,
pcie_rx_i,
pcie_tx,
usr_sw_i,
led,
p200clk,
CLK_GATE_p200clk,
p200rst);
input sys0_clk;
input sys0_rstn;
input pcie_clk;
input pcie_rstn;
// action method pcie_rx
input [3 : 0] pcie_rx_i;
// value method pcie_tx
output [3 : 0] pcie_tx;
// action method usr_sw
input [7 : 0] usr_sw_i;
// value method led
output [7 : 0] led;
// oscillator and gates for output clock p200clk
output p200clk;
output CLK_GATE_p200clk;
// output resets
output p200rst;
// signals for module outputs
wire [7 : 0] led;
wire [3 : 0] pcie_tx;
wire CLK_GATE_p200clk, p200clk, p200rst;
// register freeCnt
reg [31 : 0] freeCnt;
wire [31 : 0] freeCnt$D_IN;
wire freeCnt$EN;
// register swReg
reg [7 : 0] swReg;
wire [7 : 0] swReg$D_IN;
wire swReg$EN;
// ports of submodule aliveLed_sb
wire aliveLed_sb$dD_OUT, aliveLed_sb$sD_IN, aliveLed_sb$sEN;
// ports of submodule linkLed_sb
wire linkLed_sb$dD_OUT, linkLed_sb$sD_IN, linkLed_sb$sEN;
// ports of submodule pciw_pcie_ep
wire [127 : 0] pciw_pcie_ep$tx_st_data0;
wire [3 : 0] pciw_pcie_ep$pcie_rx_in, pciw_pcie_ep$pcie_tx_out;
wire pciw_pcie_ep$ava_alive,
pciw_pcie_ep$ava_core_clk_out,
pciw_pcie_ep$ava_lnk_up,
pciw_pcie_ep$ava_srstn,
pciw_pcie_ep$rx_st_mask0,
pciw_pcie_ep$rx_st_ready0,
pciw_pcie_ep$tx_st_empty0,
pciw_pcie_ep$tx_st_eop0,
pciw_pcie_ep$tx_st_err0,
pciw_pcie_ep$tx_st_sop0,
pciw_pcie_ep$tx_st_valid0;
// remaining internal signals
wire swParity__h135, z__h559, z__h566, z__h573, z__h580, z__h587, z__h594;
// oscillator and gates for output clock p200clk
assign p200clk = sys0_clk ;
assign CLK_GATE_p200clk = 1'd1 ;
// output resets
assign p200rst = sys0_rstn ;
// value method pcie_tx
assign pcie_tx = pciw_pcie_ep$pcie_tx_out ;
// value method led
assign led =
{ ~swParity__h135,
swParity__h135,
aliveLed_sb$dD_OUT,
linkLed_sb$dD_OUT,
freeCnt[29:26] } ;
// submodule aliveLed_sb
SyncBit #(.init(1'd0)) aliveLed_sb(.sCLK(pciw_pcie_ep$ava_core_clk_out),
.dCLK(sys0_clk),
.sRST_N(pciw_pcie_ep$ava_srstn),
.sD_IN(aliveLed_sb$sD_IN),
.sEN(aliveLed_sb$sEN),
.dD_OUT(aliveLed_sb$dD_OUT));
// submodule linkLed_sb
SyncBit #(.init(1'd0)) linkLed_sb(.sCLK(pciw_pcie_ep$ava_core_clk_out),
.dCLK(sys0_clk),
.sRST_N(pciw_pcie_ep$ava_srstn),
.sD_IN(linkLed_sb$sD_IN),
.sEN(linkLed_sb$sEN),
.dD_OUT(linkLed_sb$dD_OUT));
// submodule pciw_pcie_ep
pcie_hip_s4gx_gen2_x4_128_wrapper pciw_pcie_ep(.sys0_clk(sys0_clk),
.sys0_rstn(sys0_rstn),
.pcie_clk(pcie_clk),
.pcie_rstn(pcie_rstn),
.pcie_rx_in(pciw_pcie_ep$pcie_rx_in),
.rx_st_mask0(pciw_pcie_ep$rx_st_mask0),
.rx_st_ready0(pciw_pcie_ep$rx_st_ready0),
.tx_st_data0(pciw_pcie_ep$tx_st_data0),
.tx_st_empty0(pciw_pcie_ep$tx_st_empty0),
.tx_st_eop0(pciw_pcie_ep$tx_st_eop0),
.tx_st_err0(pciw_pcie_ep$tx_st_err0),
.tx_st_sop0(pciw_pcie_ep$tx_st_sop0),
.tx_st_valid0(pciw_pcie_ep$tx_st_valid0),
.pcie_tx_out(pciw_pcie_ep$pcie_tx_out),
.ava_alive(pciw_pcie_ep$ava_alive),
.ava_lnk_up(pciw_pcie_ep$ava_lnk_up),
.rx_st_valid0(),
.rx_st_bardec0(),
.rx_st_be0(),
.rx_st_data0(),
.rx_st_sop0(),
.rx_st_eop0(),
.rx_st_empty0(),
.rx_st_err0(),
.tx_cred0(),
.tx_fifo_empty0(),
.ava_core_clk_out(pciw_pcie_ep$ava_core_clk_out),
.ava_srstn(pciw_pcie_ep$ava_srstn));
// register freeCnt
assign freeCnt$D_IN = freeCnt + 32'd1 ;
assign freeCnt$EN = 1'd1 ;
// register swReg
assign swReg$D_IN = usr_sw_i ;
assign swReg$EN = 1'd1 ;
// submodule aliveLed_sb
assign aliveLed_sb$sD_IN = pciw_pcie_ep$ava_alive ;
assign aliveLed_sb$sEN = 1'd1 ;
// submodule linkLed_sb
assign linkLed_sb$sD_IN = pciw_pcie_ep$ava_lnk_up ;
assign linkLed_sb$sEN = 1'd1 ;
// submodule pciw_pcie_ep
assign pciw_pcie_ep$pcie_rx_in = pcie_rx_i ;
assign pciw_pcie_ep$rx_st_mask0 = 1'b0 ;
assign pciw_pcie_ep$rx_st_ready0 = 1'b0 ;
assign pciw_pcie_ep$tx_st_data0 = 128'h0 ;
assign pciw_pcie_ep$tx_st_empty0 = 1'b0 ;
assign pciw_pcie_ep$tx_st_eop0 = 1'b0 ;
assign pciw_pcie_ep$tx_st_err0 = 1'b0 ;
assign pciw_pcie_ep$tx_st_sop0 = 1'b0 ;
assign pciw_pcie_ep$tx_st_valid0 = 1'b0 ;
// remaining internal signals
assign swParity__h135 = z__h594 ^ swReg[7] ;
assign z__h559 = swReg[0] ^ swReg[1] ;
assign z__h566 = z__h559 ^ swReg[2] ;
assign z__h573 = z__h566 ^ swReg[3] ;
assign z__h580 = z__h573 ^ swReg[4] ;
assign z__h587 = z__h580 ^ swReg[5] ;
assign z__h594 = z__h587 ^ swReg[6] ;
// handling of inlined registers
always@(posedge sys0_clk)
begin
if (!sys0_rstn)
begin
freeCnt <= `BSV_ASSIGNMENT_DELAY 32'd0;
swReg <= `BSV_ASSIGNMENT_DELAY 8'd0;
end
else
begin
if (freeCnt$EN) freeCnt <= `BSV_ASSIGNMENT_DELAY freeCnt$D_IN;
if (swReg$EN) swReg <= `BSV_ASSIGNMENT_DELAY swReg$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
freeCnt = 32'hAAAAAAAA;
swReg = 8'hAA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
endmodule // mkFTop_htgs4
|
/*
* VGA top level file
* Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module vga (
// Wishbone signals
input wb_clk_i, // 25 Mhz VDU clock
input wb_rst_i,
input [15:0] wb_dat_i,
output [15:0] wb_dat_o,
input [16:1] wb_adr_i,
input wb_we_i,
input wb_tga_i,
input [ 1:0] wb_sel_i,
input wb_stb_i,
input wb_cyc_i,
output wb_ack_o,
// VGA pad signals
output [ 3:0] vga_red_o,
output [ 3:0] vga_green_o,
output [ 3:0] vga_blue_o,
output horiz_sync,
output vert_sync,
// CSR SRAM master interface
output [17:1] csrm_adr_o,
output [ 1:0] csrm_sel_o,
output csrm_we_o,
output [15:0] csrm_dat_o,
input [15:0] csrm_dat_i
);
// Registers and nets
//
// csr address
reg [17:1] csr_adr_i;
reg csr_stb_i;
// Config wires
wire [15:0] conf_wb_dat_o;
wire conf_wb_ack_o;
// Mem wires
wire [15:0] mem_wb_dat_o;
wire mem_wb_ack_o;
// LCD wires
wire [17:1] csr_adr_o;
wire [15:0] csr_dat_i;
wire csr_stb_o;
wire v_retrace;
wire vh_retrace;
wire w_vert_sync;
// VGA configuration registers
wire shift_reg1;
wire graphics_alpha;
wire memory_mapping1;
wire [ 1:0] write_mode;
wire [ 1:0] raster_op;
wire read_mode;
wire [ 7:0] bitmask;
wire [ 3:0] set_reset;
wire [ 3:0] enable_set_reset;
wire [ 3:0] map_mask;
wire x_dotclockdiv2;
wire chain_four;
wire [ 1:0] read_map_select;
wire [ 3:0] color_compare;
wire [ 3:0] color_dont_care;
// Wishbone master to SRAM
wire [17:1] wbm_adr_o;
wire [ 1:0] wbm_sel_o;
wire wbm_we_o;
wire [15:0] wbm_dat_o;
wire [15:0] wbm_dat_i;
wire wbm_stb_o;
wire wbm_ack_i;
wire stb;
// CRT wires
wire [ 5:0] cur_start;
wire [ 5:0] cur_end;
wire [15:0] start_addr;
wire [ 4:0] vcursor;
wire [ 6:0] hcursor;
wire [ 6:0] horiz_total;
wire [ 6:0] end_horiz;
wire [ 6:0] st_hor_retr;
wire [ 4:0] end_hor_retr;
wire [ 9:0] vert_total;
wire [ 9:0] end_vert;
wire [ 9:0] st_ver_retr;
wire [ 3:0] end_ver_retr;
// attribute_ctrl wires
wire [3:0] pal_addr;
wire pal_we;
wire [7:0] pal_read;
wire [7:0] pal_write;
// dac_regs wires
wire dac_we;
wire [1:0] dac_read_data_cycle;
wire [7:0] dac_read_data_register;
wire [3:0] dac_read_data;
wire [1:0] dac_write_data_cycle;
wire [7:0] dac_write_data_register;
wire [3:0] dac_write_data;
// Module instances
//
vga_config_iface config_iface (
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wb_dat_i (wb_dat_i),
.wb_dat_o (conf_wb_dat_o),
.wb_adr_i (wb_adr_i[4:1]),
.wb_we_i (wb_we_i),
.wb_sel_i (wb_sel_i),
.wb_stb_i (stb & wb_tga_i),
.wb_ack_o (conf_wb_ack_o),
.shift_reg1 (shift_reg1),
.graphics_alpha (graphics_alpha),
.memory_mapping1 (memory_mapping1),
.write_mode (write_mode),
.raster_op (raster_op),
.read_mode (read_mode),
.bitmask (bitmask),
.set_reset (set_reset),
.enable_set_reset (enable_set_reset),
.map_mask (map_mask),
.x_dotclockdiv2 (x_dotclockdiv2),
.chain_four (chain_four),
.read_map_select (read_map_select),
.color_compare (color_compare),
.color_dont_care (color_dont_care),
.pal_addr (pal_addr),
.pal_we (pal_we),
.pal_read (pal_read),
.pal_write (pal_write),
.dac_we (dac_we),
.dac_read_data_cycle (dac_read_data_cycle),
.dac_read_data_register (dac_read_data_register),
.dac_read_data (dac_read_data),
.dac_write_data_cycle (dac_write_data_cycle),
.dac_write_data_register (dac_write_data_register),
.dac_write_data (dac_write_data),
.cur_start (cur_start),
.cur_end (cur_end),
.start_addr (start_addr),
.vcursor (vcursor),
.hcursor (hcursor),
.horiz_total (horiz_total),
.end_horiz (end_horiz),
.st_hor_retr (st_hor_retr),
.end_hor_retr (end_hor_retr),
.vert_total (vert_total),
.end_vert (end_vert),
.st_ver_retr (st_ver_retr),
.end_ver_retr (end_ver_retr),
.v_retrace (v_retrace),
.vh_retrace (vh_retrace)
);
vga_lcd lcd (
.clk (wb_clk_i),
.rst (wb_rst_i),
.shift_reg1 (shift_reg1),
.graphics_alpha (graphics_alpha),
.pal_addr (pal_addr),
.pal_we (pal_we),
.pal_read (pal_read),
.pal_write (pal_write),
.dac_we (dac_we),
.dac_read_data_cycle (dac_read_data_cycle),
.dac_read_data_register (dac_read_data_register),
.dac_read_data (dac_read_data),
.dac_write_data_cycle (dac_write_data_cycle),
.dac_write_data_register (dac_write_data_register),
.dac_write_data (dac_write_data),
.csr_adr_o (csr_adr_o),
.csr_dat_i (csr_dat_i),
.csr_stb_o (csr_stb_o),
.vga_red_o (vga_red_o),
.vga_green_o (vga_green_o),
.vga_blue_o (vga_blue_o),
.horiz_sync (horiz_sync),
.vert_sync (w_vert_sync),
.cur_start (cur_start),
.cur_end (cur_end),
.vcursor (vcursor),
.hcursor (hcursor),
.horiz_total (horiz_total),
.end_horiz (end_horiz),
.st_hor_retr (st_hor_retr),
.end_hor_retr (end_hor_retr),
.vert_total (vert_total),
.end_vert (end_vert),
.st_ver_retr (st_ver_retr),
.end_ver_retr (end_ver_retr),
.x_dotclockdiv2 (x_dotclockdiv2),
.v_retrace (v_retrace),
.vh_retrace (vh_retrace)
);
vga_cpu_mem_iface cpu_mem_iface (
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wbs_adr_i (wb_adr_i),
.wbs_sel_i (wb_sel_i),
.wbs_we_i (wb_we_i),
.wbs_dat_i (wb_dat_i),
.wbs_dat_o (mem_wb_dat_o),
.wbs_stb_i (stb & !wb_tga_i),
.wbs_ack_o (mem_wb_ack_o),
.wbm_adr_o (wbm_adr_o),
.wbm_sel_o (wbm_sel_o),
.wbm_we_o (wbm_we_o),
.wbm_dat_o (wbm_dat_o),
.wbm_dat_i (wbm_dat_i),
.wbm_stb_o (wbm_stb_o),
.wbm_ack_i (wbm_ack_i),
.chain_four (chain_four),
.memory_mapping1 (memory_mapping1),
.write_mode (write_mode),
.raster_op (raster_op),
.read_mode (read_mode),
.bitmask (bitmask),
.set_reset (set_reset),
.enable_set_reset (enable_set_reset),
.map_mask (map_mask),
.read_map_select (read_map_select),
.color_compare (color_compare),
.color_dont_care (color_dont_care)
);
vga_mem_arbitrer mem_arbitrer (
.clk_i (wb_clk_i),
.rst_i (wb_rst_i),
.wb_adr_i (wbm_adr_o),
.wb_sel_i (wbm_sel_o),
.wb_we_i (wbm_we_o),
.wb_dat_i (wbm_dat_o),
.wb_dat_o (wbm_dat_i),
.wb_stb_i (wbm_stb_o),
.wb_ack_o (wbm_ack_i),
.csr_adr_i (csr_adr_i),
.csr_dat_o (csr_dat_i),
.csr_stb_i (csr_stb_i),
.csrm_adr_o (csrm_adr_o),
.csrm_sel_o (csrm_sel_o),
.csrm_we_o (csrm_we_o),
.csrm_dat_o (csrm_dat_o),
.csrm_dat_i (csrm_dat_i)
);
// Continous assignments
assign wb_dat_o = wb_tga_i ? conf_wb_dat_o : mem_wb_dat_o;
assign wb_ack_o = wb_tga_i ? conf_wb_ack_o : mem_wb_ack_o;
assign stb = wb_stb_i & wb_cyc_i;
assign vert_sync = ~graphics_alpha ^ w_vert_sync;
// Behaviour
// csr_adr_i
always @(posedge wb_clk_i)
csr_adr_i <= wb_rst_i ? 17'h0 : csr_adr_o + start_addr[15:1];
// csr_stb_i
always @(posedge wb_clk_i)
csr_stb_i <= wb_rst_i ? 1'b0 : csr_stb_o;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2004 by Jie Xu.
//
// The test was added together with the concat optimization.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg [31:0] in_a;
reg [31:0] in_b;
reg [31:0] in_c;
reg [31:0] in_d;
reg [31:0] in_e;
reg [15:0] in_f;
wire [31:0] in_g;
assign in_g = in_a << 4;
reg [31:0] out_x;
reg [31:0] out_y;
reg [31:0] out_z;
reg [31:0] out_o;
reg [31:0] out_p;
reg [31:0] out_q;
assign out_x = {in_a[31:16] & in_f, in_a[15:0] & in_f};
assign out_y = {in_a[31:18] & in_b[31:18], in_a[17:0] & in_b[17:0]};
assign out_z = {in_c[31:14] & in_d[31:14] & in_e[31:14], in_c[13:0] & in_d[13:0] & in_e[13:0]};
assign out_o = out_z | out_y;
assign out_p = {in_a[31:16] & in_f | in_e[31:16], in_a[15:0] & in_f | in_e[15:0]};
assign out_q = {{in_a[31:25] ^ in_g[31:25], in_a[24:16] ^ in_g[24:16]}, {in_a[15:5] ^ in_g[15:5], in_a[4:0] ^ in_g[4:0]}};
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
in_a <= cyc;
in_b <= cyc + 1;
in_c <= cyc + 3;
in_d <= cyc + 8;
in_e <= cyc;
in_f <= cyc[15:0];
if (out_x != (in_a & {2{in_f}}))
$stop;
if (out_y != (in_a&in_b))
$stop;
if (out_z != (in_e&in_d&in_c))
$stop;
if (out_o != (((in_a&in_b)|(in_c&in_e&in_d))))
$stop;
if (out_p != (in_a & {2{in_f}} | in_e))
$stop;
if (out_q != (in_a ^ in_g))
$stop;
if (cyc==100) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
(* This program is free software; you can redistribute it and/or *)
(* modify it under the terms of the GNU Lesser General Public License *)
(* as published by the Free Software Foundation; either version 2.1 *)
(* of the License, or (at your option) any later version. *)
(* *)
(* This program is distributed in the hope that it will be useful, *)
(* but WITHOUT ANY WARRANTY; without even the implied warranty of *)
(* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *)
(* GNU General Public License for more details. *)
(* *)
(* You should have received a copy of the GNU Lesser General Public *)
(* License along with this program; if not, write to the Free *)
(* Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA *)
(* 02110-1301 USA *)
(** This file includes random facts about Integers (and natural numbers) which are not found in the standard library. Some of the lemma here are not used in the QArith developement but are rather useful.
*)
Require Export ZArith.
Require Export ZArithRing.
Tactic Notation "ElimCompare" constr(c) constr(d) := elim_compare c d.
Ltac Flip :=
apply Zgt_lt || apply Zlt_gt || apply Zle_ge || apply Zge_le; assumption.
Ltac Falsum :=
try intro; apply False_ind;
repeat
match goal with
| id1:(~ ?X1) |- ?X2 =>
(apply id1; assumption || reflexivity) || clear id1
end.
Ltac Step_l a :=
match goal with
| |- (?X1 < ?X2)%Z => replace X1 with a; [ idtac | try ring ]
end.
Ltac Step_r a :=
match goal with
| |- (?X1 < ?X2)%Z => replace X2 with a; [ idtac | try ring ]
end.
Ltac CaseEq formula :=
generalize (refl_equal formula); pattern formula at -1 in |- *;
case formula.
Lemma pair_1 : forall (A B : Set) (H : A * B), H = pair (fst H) (snd H).
Proof.
intros.
case H.
intros.
simpl in |- *.
reflexivity.
Qed.
Lemma pair_2 :
forall (A B : Set) (H1 H2 : A * B),
fst H1 = fst H2 -> snd H1 = snd H2 -> H1 = H2.
Proof.
intros A B H1 H2.
case H1.
case H2.
simpl in |- *.
intros.
rewrite H.
rewrite H0.
reflexivity.
Qed.
Section projection.
Variable A : Set.
Variable P : A -> Prop.
Definition projP1 (H : sig P) := let (x, h) := H in x.
Definition projP2 (H : sig P) :=
let (x, h) as H return (P (projP1 H)) := H in h.
End projection.
(*###########################################################################*)
(* Declaring some realtions on natural numbers for stepl and stepr tactics. *)
(*###########################################################################*)
Lemma le_stepl: forall x y z, le x y -> x=z -> le z y.
Proof.
intros x y z H_le H_eq; subst z; trivial.
Qed.
Lemma le_stepr: forall x y z, le x y -> y=z -> le x z.
Proof.
intros x y z H_le H_eq; subst z; trivial.
Qed.
Lemma lt_stepl: forall x y z, lt x y -> x=z -> lt z y.
Proof.
intros x y z H_lt H_eq; subst z; trivial.
Qed.
Lemma lt_stepr: forall x y z, lt x y -> y=z -> lt x z.
Proof.
intros x y z H_lt H_eq; subst z; trivial.
Qed.
Lemma neq_stepl:forall (x y z:nat), x<>y -> x=z -> z<>y.
Proof.
intros x y z H_lt H_eq; subst; assumption.
Qed.
Lemma neq_stepr:forall (x y z:nat), x<>y -> y=z -> x<>z.
Proof.
intros x y z H_lt H_eq; subst; assumption.
Qed.
Declare Left Step le_stepl.
Declare Right Step le_stepr.
Declare Left Step lt_stepl.
Declare Right Step lt_stepr.
Declare Left Step neq_stepl.
Declare Right Step neq_stepr.
(*###########################################################################*)
(** Some random facts about natural numbers, positive numbers and integers *)
(*###########################################################################*)
Lemma not_O_S : forall n : nat, n <> 0 -> {p : nat | n = S p}.
Proof.
intros [| np] Hn; [ exists 0; apply False_ind; apply Hn | exists np ];
reflexivity.
Qed.
Lemma lt_minus_neq : forall m n : nat, m < n -> n - m <> 0.
Proof.
intros.
omega.
Qed.
Lemma lt_minus_eq_0 : forall m n : nat, m < n -> m - n = 0.
Proof.
intros.
omega.
Qed.
Lemma le_plus_Sn_1_SSn : forall n : nat, S n + 1 <= S (S n).
Proof.
intros.
omega.
Qed.
Lemma le_plus_O_l : forall p q : nat, p + q <= 0 -> p = 0.
Proof.
intros; omega.
Qed.
Lemma le_plus_O_r : forall p q : nat, p + q <= 0 -> q = 0.
Proof.
intros; omega.
Qed.
Lemma minus_pred : forall m n : nat, 0 < n -> pred m - pred n = m - n.
Proof.
intros.
omega.
Qed.
(*###########################################################################*)
(* Declaring some realtions on integers for stepl and stepr tactics. *)
(*###########################################################################*)
Lemma Zle_stepl: forall x y z, (x<=y)%Z -> x=z -> (z<=y)%Z.
Proof.
intros x y z H_le H_eq; subst z; trivial.
Qed.
Lemma Zle_stepr: forall x y z, (x<=y)%Z -> y=z -> (x<=z)%Z.
Proof.
intros x y z H_le H_eq; subst z; trivial.
Qed.
Lemma Zlt_stepl: forall x y z, (x<y)%Z -> x=z -> (z<y)%Z.
Proof.
intros x y z H_lt H_eq; subst z; trivial.
Qed.
Lemma Zlt_stepr: forall x y z, (x<y)%Z -> y=z -> (x<z)%Z.
Proof.
intros x y z H_lt H_eq; subst z; trivial.
Qed.
Lemma Zneq_stepl:forall (x y z:Z), (x<>y)%Z -> x=z -> (z<>y)%Z.
Proof.
intros x y z H_lt H_eq; subst; assumption.
Qed.
Lemma Zneq_stepr:forall (x y z:Z), (x<>y)%Z -> y=z -> (x<>z)%Z.
Proof.
intros x y z H_lt H_eq; subst; assumption.
Qed.
Declare Left Step Zle_stepl.
Declare Right Step Zle_stepr.
Declare Left Step Zlt_stepl.
Declare Right Step Zlt_stepr.
Declare Left Step Zneq_stepl.
Declare Right Step Zneq_stepr.
(*###########################################################################*)
(** Informative case analysis *)
(*###########################################################################*)
Lemma Zlt_cotrans :
forall x y : Z, (x < y)%Z -> forall z : Z, {(x < z)%Z} + {(z < y)%Z}.
Proof.
intros.
case (Z_lt_ge_dec x z).
intro.
left.
assumption.
intro.
right.
apply Zle_lt_trans with (m := x).
apply Zge_le.
assumption.
assumption.
Qed.
Lemma Zlt_cotrans_pos :
forall x y : Z, (0 < x + y)%Z -> {(0 < x)%Z} + {(0 < y)%Z}.
Proof.
intros.
case (Zlt_cotrans 0 (x + y) H x).
intro.
left.
assumption.
intro.
right.
apply Zplus_lt_reg_l with (p := x).
rewrite Zplus_0_r.
assumption.
Qed.
Lemma Zlt_cotrans_neg :
forall x y : Z, (x + y < 0)%Z -> {(x < 0)%Z} + {(y < 0)%Z}.
Proof.
intros x y H; case (Zlt_cotrans (x + y) 0 H x); intro Hxy;
[ right; apply Zplus_lt_reg_l with (p := x); rewrite Zplus_0_r | left ];
assumption.
Qed.
Lemma not_Zeq_inf : forall x y : Z, x <> y -> {(x < y)%Z} + {(y < x)%Z}.
Proof.
intros.
case Z_lt_ge_dec with x y.
intro.
left.
assumption.
intro H0.
generalize (Zge_le _ _ H0).
intro.
case (Z_le_lt_eq_dec _ _ H1).
intro.
right.
assumption.
intro.
apply False_rec.
apply H.
symmetry in |- *.
assumption.
Qed.
Lemma Z_dec : forall x y : Z, {(x < y)%Z} + {(x > y)%Z} + {x = y}.
Proof.
intros.
case (Z_lt_ge_dec x y).
intro H.
left.
left.
assumption.
intro H.
generalize (Zge_le _ _ H).
intro H0.
case (Z_le_lt_eq_dec y x H0).
intro H1.
left.
right.
apply Zlt_gt.
assumption.
intro.
right.
symmetry in |- *.
assumption.
Qed.
Lemma Z_dec' : forall x y : Z, {(x < y)%Z} + {(y < x)%Z} + {x = y}.
Proof.
intros x y.
case (Z_eq_dec x y); intro H;
[ right; assumption | left; apply (not_Zeq_inf _ _ H) ].
Qed.
Lemma Z_lt_le_dec : forall x y : Z, {(x < y)%Z} + {(y <= x)%Z}.
Proof.
intros.
case (Z_lt_ge_dec x y).
intro.
left.
assumption.
intro.
right.
apply Zge_le.
assumption.
Qed.
Lemma Z_le_lt_dec : forall x y : Z, {(x <= y)%Z} + {(y < x)%Z}.
Proof.
intros; case (Z_lt_le_dec y x); [ right | left ]; assumption.
Qed.
Lemma Z_lt_lt_S_eq_dec :
forall x y : Z, (x < y)%Z -> {(x + 1 < y)%Z} + {(x + 1)%Z = y}.
Proof.
intros.
generalize (Zlt_le_succ _ _ H).
unfold Zsucc in |- *.
apply Z_le_lt_eq_dec.
Qed.
Lemma quadro_leq_inf :
forall a b c d : Z,
{(c <= a)%Z /\ (d <= b)%Z} + {~ ((c <= a)%Z /\ (d <= b)%Z)}.
Proof.
intros.
case (Z_lt_le_dec a c).
intro z.
right.
intro.
elim H.
intros.
generalize z.
apply Zle_not_lt.
assumption.
intro.
case (Z_lt_le_dec b d).
intro z0.
right.
intro.
elim H.
intros.
generalize z0.
apply Zle_not_lt.
assumption.
intro.
left.
split.
assumption.
assumption.
Qed.
(*###########################################################################*)
(** General auxiliary lemmata *)
(*###########################################################################*)
Lemma Zminus_eq : forall x y : Z, (x - y)%Z = 0%Z -> x = y.
Proof.
intros.
apply Zplus_reg_l with (- y)%Z.
rewrite Zplus_opp_l.
unfold Zminus in H.
rewrite Zplus_comm.
assumption.
Qed.
Lemma Zlt_minus : forall a b : Z, (b < a)%Z -> (0 < a - b)%Z.
Proof.
intros a b.
intros.
apply Zplus_lt_reg_l with b.
unfold Zminus in |- *.
rewrite (Zplus_comm a).
rewrite (Zplus_assoc b (- b)).
rewrite Zplus_opp_r.
simpl in |- *.
rewrite <- Zplus_0_r_reverse.
assumption.
Qed.
Lemma Zle_minus : forall a b : Z, (b <= a)%Z -> (0 <= a - b)%Z.
Proof.
intros a b.
intros.
apply Zplus_le_reg_l with b.
unfold Zminus in |- *.
rewrite (Zplus_comm a).
rewrite (Zplus_assoc b (- b)).
rewrite Zplus_opp_r.
simpl in |- *.
rewrite <- Zplus_0_r_reverse.
assumption.
Qed.
Lemma Zlt_plus_plus :
forall m n p q : Z, (m < n)%Z -> (p < q)%Z -> (m + p < n + q)%Z.
Proof.
intros.
apply Zlt_trans with (m := (n + p)%Z).
rewrite Zplus_comm.
rewrite Zplus_comm with (n := n).
apply Zplus_lt_compat_l.
assumption.
apply Zplus_lt_compat_l.
assumption.
Qed.
Lemma Zgt_plus_plus :
forall m n p q : Z, (m > n)%Z -> (p > q)%Z -> (m + p > n + q)%Z.
intros.
apply Zgt_trans with (m := (n + p)%Z).
rewrite Zplus_comm.
rewrite Zplus_comm with (n := n).
apply Zplus_gt_compat_l.
assumption.
apply Zplus_gt_compat_l.
assumption.
Qed.
Lemma Zle_lt_plus_plus :
forall m n p q : Z, (m <= n)%Z -> (p < q)%Z -> (m + p < n + q)%Z.
Proof.
intros.
case (Zle_lt_or_eq m n).
assumption.
intro.
apply Zlt_plus_plus.
assumption.
assumption.
intro.
rewrite H1.
apply Zplus_lt_compat_l.
assumption.
Qed.
Lemma Zge_gt_plus_plus :
forall m n p q : Z, (m >= n)%Z -> (p > q)%Z -> (m + p > n + q)%Z.
Proof.
intros.
case (Zle_lt_or_eq n m).
apply Zge_le.
assumption.
intro.
apply Zgt_plus_plus.
apply Zlt_gt.
assumption.
assumption.
intro.
rewrite H1.
apply Zplus_gt_compat_l.
assumption.
Qed.
Lemma Zgt_ge_plus_plus :
forall m n p q : Z, (m > n)%Z -> (p >= q)%Z -> (m + p > n + q)%Z.
Proof.
intros.
rewrite Zplus_comm.
replace (n + q)%Z with (q + n)%Z.
apply Zge_gt_plus_plus.
assumption.
assumption.
apply Zplus_comm.
Qed.
Lemma Zlt_resp_pos : forall x y : Z, (0 < x)%Z -> (0 < y)%Z -> (0 < x + y)%Z.
Proof.
intros.
rewrite <- Zplus_0_r with 0%Z.
apply Zlt_plus_plus; assumption.
Qed.
Lemma Zle_resp_neg :
forall x y : Z, (x <= 0)%Z -> (y <= 0)%Z -> (x + y <= 0)%Z.
Proof.
intros.
rewrite <- Zplus_0_r with 0%Z.
apply Zplus_le_compat; assumption.
Qed.
Lemma Zlt_pos_opp : forall x : Z, (0 < x)%Z -> (- x < 0)%Z.
Proof.
intros.
apply Zplus_lt_reg_l with x.
rewrite Zplus_opp_r.
rewrite Zplus_0_r.
assumption.
Qed.
Lemma Zlt_neg_opp : forall x : Z, (x < 0)%Z -> (0 < - x)%Z.
Proof.
intros.
apply Zplus_lt_reg_l with x.
rewrite Zplus_opp_r.
rewrite Zplus_0_r.
assumption.
Qed.
Lemma Zle_neg_opp : forall x : Z, (x <= 0)%Z -> (0 <= - x)%Z.
Proof.
intros.
apply Zplus_le_reg_l with x.
rewrite Zplus_opp_r.
rewrite Zplus_0_r.
assumption.
Qed.
Lemma Zle_pos_opp : forall x : Z, (0 <= x)%Z -> (- x <= 0)%Z.
Proof.
intros.
apply Zplus_le_reg_l with x.
rewrite Zplus_opp_r.
rewrite Zplus_0_r.
assumption.
Qed.
Lemma Zge_opp : forall x y : Z, (x <= y)%Z -> (- x >= - y)%Z.
Proof.
intros.
apply Zle_ge.
apply Zplus_le_reg_l with (p := (x + y)%Z).
ring_simplify (x + y + - y)%Z (x + y + - x)%Z.
assumption.
Qed.
(* Omega can't solve this *)
Lemma Zmult_pos_pos : forall x y : Z, (0 < x)%Z -> (0 < y)%Z -> (0 < x * y)%Z.
Proof.
intros [| px| px] [| py| py] Hx Hy; trivial || constructor.
Qed.
Lemma Zmult_neg_neg : forall x y : Z, (x < 0)%Z -> (y < 0)%Z -> (0 < x * y)%Z.
Proof.
intros [| px| px] [| py| py] Hx Hy; trivial || constructor.
Qed.
Lemma Zmult_neg_pos : forall x y : Z, (x < 0)%Z -> (0 < y)%Z -> (x * y < 0)%Z.
Proof.
intros [| px| px] [| py| py] Hx Hy; trivial || constructor.
Qed.
Lemma Zmult_pos_neg : forall x y : Z, (0 < x)%Z -> (y < 0)%Z -> (x * y < 0)%Z.
Proof.
intros [| px| px] [| py| py] Hx Hy; trivial || constructor.
Qed.
Hint Resolve Zmult_pos_pos Zmult_neg_neg Zmult_neg_pos Zmult_pos_neg: zarith.
Lemma Zle_reg_mult_l :
forall x y a : Z, (0 < a)%Z -> (x <= y)%Z -> (a * x <= a * y)%Z.
Proof.
intros.
apply Zplus_le_reg_l with (p := (- a * x)%Z).
ring_simplify (- a * x + a * x)%Z.
replace (- a * x + a * y)%Z with ((y - x) * a)%Z.
apply Zmult_gt_0_le_0_compat.
apply Zlt_gt.
assumption.
unfold Zminus in |- *.
apply Zle_left.
assumption.
ring.
Qed.
Lemma Zsimpl_plus_l_dep :
forall x y m n : Z, (x + m)%Z = (y + n)%Z -> x = y -> m = n.
Proof.
intros.
apply Zplus_reg_l with x.
rewrite <- H0 in H.
assumption.
Qed.
Lemma Zsimpl_plus_r_dep :
forall x y m n : Z, (m + x)%Z = (n + y)%Z -> x = y -> m = n.
Proof.
intros.
apply Zplus_reg_l with x.
rewrite Zplus_comm.
rewrite Zplus_comm with x n.
rewrite <- H0 in H.
assumption.
Qed.
Lemma Zmult_simpl :
forall n m p q : Z, n = m -> p = q -> (n * p)%Z = (m * q)%Z.
Proof.
intros.
rewrite H.
rewrite H0.
reflexivity.
Qed.
Lemma Zsimpl_mult_l :
forall n m p : Z, n <> 0%Z -> (n * m)%Z = (n * p)%Z -> m = p.
Proof.
intros.
apply Zplus_reg_l with (n := (- p)%Z).
replace (- p + p)%Z with 0%Z.
apply Zmult_integral_l with (n := n).
assumption.
replace ((- p + m) * n)%Z with (n * m + - (n * p))%Z.
apply Zegal_left.
assumption.
ring.
ring.
Qed.
Lemma Zlt_reg_mult_l :
forall x y z : Z, (x > 0)%Z -> (y < z)%Z -> (x * y < x * z)%Z. (*QA*)
Proof.
intros.
case (Zcompare_Gt_spec x 0).
unfold Zgt in H.
assumption.
intros.
cut (x = Zpos x0).
intro.
rewrite H2.
unfold Zlt in H0.
unfold Zlt in |- *.
cut ((Zpos x0 * y ?= Zpos x0 * z)%Z = (y ?= z)%Z).
intro.
exact (trans_eq H3 H0).
apply Zcompare_mult_compat.
cut (x = (x + - (0))%Z).
intro.
exact (trans_eq H2 H1).
simpl in |- *.
apply (sym_eq (A:=Z)).
exact (Zplus_0_r x).
Qed.
Lemma Zlt_opp : forall x y : Z, (x < y)%Z -> (- x > - y)%Z. (*QA*)
Proof.
intros.
red in |- *.
apply sym_eq.
cut (Datatypes.Gt = (y ?= x)%Z).
intro.
cut ((y ?= x)%Z = (- x ?= - y)%Z).
intro.
exact (trans_eq H0 H1).
exact (Zcompare_opp y x).
apply sym_eq.
exact (Zlt_gt x y H).
Qed.
Lemma Zlt_conv_mult_l :
forall x y z : Z, (x < 0)%Z -> (y < z)%Z -> (x * y > x * z)%Z. (*QA*)
Proof.
intros.
cut (- x > 0)%Z.
intro.
cut (- x * y < - x * z)%Z.
intro.
cut (- (- x * y) > - (- x * z))%Z.
intro.
cut (- - (x * y) > - - (x * z))%Z.
intro.
cut ((- - (x * y))%Z = (x * y)%Z).
intro.
rewrite H5 in H4.
cut ((- - (x * z))%Z = (x * z)%Z).
intro.
rewrite H6 in H4.
assumption.
exact (Zopp_involutive (x * z)).
exact (Zopp_involutive (x * y)).
cut ((- (- x * y))%Z = (- - (x * y))%Z).
intro.
rewrite H4 in H3.
cut ((- (- x * z))%Z = (- - (x * z))%Z).
intro.
rewrite H5 in H3.
assumption.
cut ((- x * z)%Z = (- (x * z))%Z).
intro.
exact (f_equal Zopp H5).
exact (Zopp_mult_distr_l_reverse x z).
cut ((- x * y)%Z = (- (x * y))%Z).
intro.
exact (f_equal Zopp H4).
exact (Zopp_mult_distr_l_reverse x y).
exact (Zlt_opp (- x * y) (- x * z) H2).
exact (Zlt_reg_mult_l (- x) y z H1 H0).
exact (Zlt_opp x 0 H).
Qed.
Lemma Zgt_not_eq : forall x y : Z, (x > y)%Z -> x <> y. (*QA*)
Proof.
intros.
cut (y < x)%Z.
intro.
cut (y <> x).
intro.
red in |- *.
intros.
cut (y = x).
intros.
apply H1.
assumption.
exact (sym_eq H2).
exact (Zorder.Zlt_not_eq y x H0).
exact (Zgt_lt x y H).
Qed.
Lemma Zmult_resp_nonzero :
forall x y : Z, x <> 0%Z -> y <> 0%Z -> (x * y)%Z <> 0%Z.
Proof.
intros x y Hx Hy Hxy.
apply Hx.
apply Zmult_integral_l with y; assumption.
Qed.
Lemma Zopp_app : forall y : Z, y <> 0%Z -> (- y)%Z <> 0%Z.
Proof.
intros.
intro.
apply H.
apply Zplus_reg_l with (- y)%Z.
rewrite Zplus_opp_l.
rewrite H0.
simpl in |- *.
reflexivity.
Qed.
Lemma Zle_neq_Zlt : forall a b : Z, (a <= b)%Z -> b <> a -> (a < b)%Z.
Proof.
intros a b H H0.
case (Z_le_lt_eq_dec _ _ H); trivial.
intro; apply False_ind; apply H0; symmetry in |- *; assumption.
Qed.
Lemma not_Zle_lt : forall x y : Z, ~ (y <= x)%Z -> (x < y)%Z.
Proof.
intros; apply Zgt_lt; apply Znot_le_gt; assumption.
Qed.
Lemma not_Zlt : forall x y : Z, ~ (y < x)%Z -> (x <= y)%Z.
Proof.
intros x y H1 H2; apply H1; apply Zgt_lt; assumption.
Qed.
Lemma Zmult_absorb :
forall x y z : Z, x <> 0%Z -> (x * y)%Z = (x * z)%Z -> y = z. (*QA*)
Proof.
intros.
case (dec_eq y z).
intro.
assumption.
intro.
case (not_Zeq y z).
assumption.
intro.
case (not_Zeq x 0).
assumption.
intro.
apply False_ind.
cut (x * y > x * z)%Z.
intro.
cut ((x * y)%Z <> (x * z)%Z).
intro.
apply H5.
assumption.
exact (Zgt_not_eq (x * y) (x * z) H4).
exact (Zlt_conv_mult_l x y z H3 H2).
intro.
apply False_ind.
cut (x * y < x * z)%Z.
intro.
cut ((x * y)%Z <> (x * z)%Z).
intro.
apply H5.
assumption.
exact (Zorder.Zlt_not_eq (x * y) (x * z) H4).
cut (x > 0)%Z.
intro.
exact (Zlt_reg_mult_l x y z H4 H2).
exact (Zlt_gt 0 x H3).
intro.
apply False_ind.
cut (x * z < x * y)%Z.
intro.
cut ((x * z)%Z <> (x * y)%Z).
intro.
apply H4.
apply (sym_eq (A:=Z)).
assumption.
exact (Zorder.Zlt_not_eq (x * z) (x * y) H3).
apply False_ind.
case (not_Zeq x 0).
assumption.
intro.
cut (x * z > x * y)%Z.
intro.
cut ((x * z)%Z <> (x * y)%Z).
intro.
apply H5.
apply (sym_eq (A:=Z)).
assumption.
exact (Zgt_not_eq (x * z) (x * y) H4).
exact (Zlt_conv_mult_l x z y H3 H2).
intro.
cut (x * z < x * y)%Z.
intro.
cut ((x * z)%Z <> (x * y)%Z).
intro.
apply H5.
apply (sym_eq (A:=Z)).
assumption.
exact (Zorder.Zlt_not_eq (x * z) (x * y) H4).
cut (x > 0)%Z.
intro.
exact (Zlt_reg_mult_l x z y H4 H2).
exact (Zlt_gt 0 x H3).
Qed.
Lemma Zlt_mult_mult :
forall a b c d : Z,
(0 < a)%Z -> (0 < d)%Z -> (a < b)%Z -> (c < d)%Z -> (a * c < b * d)%Z.
Proof.
intros.
apply Zlt_trans with (a * d)%Z.
apply Zlt_reg_mult_l.
Flip.
assumption.
rewrite Zmult_comm.
rewrite Zmult_comm with b d.
apply Zlt_reg_mult_l.
Flip.
assumption.
Qed.
Lemma Zgt_mult_conv_absorb_l :
forall a x y : Z, (a < 0)%Z -> (a * x > a * y)%Z -> (x < y)%Z. (*QC*)
Proof.
intros.
case (dec_eq x y).
intro.
apply False_ind.
rewrite H1 in H0.
cut ((a * y)%Z = (a * y)%Z).
change ((a * y)%Z <> (a * y)%Z) in |- *.
apply Zgt_not_eq.
assumption.
trivial.
intro.
case (not_Zeq x y H1).
trivial.
intro.
apply False_ind.
cut (a * y > a * x)%Z.
apply Zgt_asym with (m := (a * y)%Z) (n := (a * x)%Z).
assumption.
apply Zlt_conv_mult_l.
assumption.
assumption.
Qed.
Lemma Zgt_mult_reg_absorb_l :
forall a x y : Z, (a > 0)%Z -> (a * x > a * y)%Z -> (x > y)%Z. (*QC*)
Proof.
intros.
cut (- - a > - - (0))%Z.
intro.
cut (- a < - (0))%Z.
simpl in |- *.
intro.
replace x with (- - x)%Z.
replace y with (- - y)%Z.
apply Zlt_opp.
apply Zgt_mult_conv_absorb_l with (a := (- a)%Z) (x := (- x)%Z).
assumption.
rewrite Zmult_opp_opp.
rewrite Zmult_opp_opp.
assumption.
apply Zopp_involutive.
apply Zopp_involutive.
apply Zgt_lt.
apply Zlt_opp.
apply Zgt_lt.
assumption.
simpl in |- *.
rewrite Zopp_involutive.
assumption.
Qed.
Lemma Zopp_Zlt : forall x y : Z, (y < x)%Z -> (- x < - y)%Z.
Proof.
intros x y Hyx.
apply Zgt_mult_conv_absorb_l with (a := (-1)%Z).
constructor.
replace (-1 * - y)%Z with y.
replace (-1 * - x)%Z with x.
Flip.
ring.
ring.
Qed.
Lemma Zmin_cancel_Zlt : forall x y : Z, (- x < - y)%Z -> (y < x)%Z.
Proof.
intros.
apply Zgt_mult_conv_absorb_l with (a := (-1)%Z).
constructor.
replace (-1 * y)%Z with (- y)%Z.
replace (-1 * x)%Z with (- x)%Z.
apply Zlt_gt.
assumption.
ring.
ring.
Qed.
Lemma Zmult_cancel_Zle :
forall a x y : Z, (a < 0)%Z -> (a * x <= a * y)%Z -> (y <= x)%Z.
Proof.
intros.
case (Z_le_gt_dec y x).
trivial.
intro.
apply False_ind.
apply (Zlt_irrefl (a * x)).
apply Zle_lt_trans with (m := (a * y)%Z).
assumption.
apply Zgt_lt.
apply Zlt_conv_mult_l.
assumption.
apply Zgt_lt.
assumption.
Qed.
Lemma Zlt_mult_cancel_l :
forall x y z : Z, (0 < x)%Z -> (x * y < x * z)%Z -> (y < z)%Z.
Proof.
intros.
apply Zgt_lt.
apply Zgt_mult_reg_absorb_l with x.
apply Zlt_gt.
assumption.
apply Zlt_gt.
assumption.
Qed.
Lemma Zmin_cancel_Zle : forall x y : Z, (- x <= - y)%Z -> (y <= x)%Z.
Proof.
intros.
apply Zmult_cancel_Zle with (a := (-1)%Z).
constructor.
replace (-1 * y)%Z with (- y)%Z.
replace (-1 * x)%Z with (- x)%Z.
assumption.
ring.
ring.
Qed.
Lemma Zmult_resp_Zle :
forall a x y : Z, (0 < a)%Z -> (a * y <= a * x)%Z -> (y <= x)%Z.
Proof.
intros.
case (Z_le_gt_dec y x).
trivial.
intro.
apply False_ind.
apply (Zlt_irrefl (a * y)).
apply Zle_lt_trans with (m := (a * x)%Z).
assumption.
apply Zlt_reg_mult_l.
apply Zlt_gt.
assumption.
apply Zgt_lt.
assumption.
Qed.
Lemma Zopp_Zle : forall x y : Z, (y <= x)%Z -> (- x <= - y)%Z.
Proof.
intros.
apply Zmult_cancel_Zle with (a := (-1)%Z).
constructor.
replace (-1 * - y)%Z with y.
replace (-1 * - x)%Z with x.
assumption.
clear y H; ring.
clear x H; ring.
Qed.
Lemma Zle_lt_eq_S : forall x y : Z, (x <= y)%Z -> (y < x + 1)%Z -> y = x.
Proof.
intros.
case (Z_le_lt_eq_dec x y H).
intro H1.
apply False_ind.
generalize (Zlt_le_succ x y H1).
intro.
apply (Zlt_not_le y (x + 1) H0).
replace (x + 1)%Z with (Zsucc x).
assumption.
reflexivity.
intro H1.
symmetry in |- *.
assumption.
Qed.
Lemma Zlt_le_eq_S :
forall x y : Z, (x < y)%Z -> (y <= x + 1)%Z -> y = (x + 1)%Z.
Proof.
intros.
case (Z_le_lt_eq_dec y (x + 1) H0).
intro H1.
apply False_ind.
generalize (Zlt_le_succ x y H).
intro.
apply (Zlt_not_le y (x + 1) H1).
replace (x + 1)%Z with (Zsucc x).
assumption.
reflexivity.
trivial.
Qed.
Lemma double_not_equal_zero :
forall c d : Z, ~ (c = 0%Z /\ d = 0%Z) -> c <> d \/ c <> 0%Z.
Proof.
intros.
case (Z_zerop c).
intro.
rewrite e.
left.
apply sym_not_eq.
intro.
apply H; repeat split; assumption.
intro; right; assumption.
Qed.
Lemma triple_not_equal_zero :
forall a b c : Z,
~ (a = 0%Z /\ b = 0%Z /\ c = 0%Z) -> a <> 0%Z \/ b <> 0%Z \/ c <> 0%Z.
Proof.
intros a b c H; case (Z_zerop a); intro Ha;
[ case (Z_zerop b); intro Hb;
[ case (Z_zerop c); intro Hc;
[ apply False_ind; apply H; repeat split | right; right ]
| right; left ]
| left ]; assumption.
Qed.
Lemma mediant_1 :
forall m n m' n' : Z, (m' * n < m * n')%Z -> ((m + m') * n < m * (n + n'))%Z.
Proof.
intros.
rewrite Zmult_plus_distr_r.
rewrite Zmult_plus_distr_l.
apply Zplus_lt_compat_l.
assumption.
Qed.
Lemma mediant_2 :
forall m n m' n' : Z,
(m' * n < m * n')%Z -> (m' * (n + n') < (m + m') * n')%Z.
Proof.
intros.
rewrite Zmult_plus_distr_l.
rewrite Zmult_plus_distr_r.
apply Zplus_lt_compat_r.
assumption.
Qed.
Lemma mediant_3 :
forall a b m n m' n' : Z,
(0 <= a * m + b * n)%Z ->
(0 <= a * m' + b * n')%Z -> (0 <= a * (m + m') + b * (n + n'))%Z.
Proof.
intros.
replace (a * (m + m') + b * (n + n'))%Z with
(a * m + b * n + (a * m' + b * n'))%Z.
apply Zplus_le_0_compat.
assumption.
assumption.
ring.
Qed.
Lemma fraction_lt_trans :
forall a b c d e f : Z,
(0 < b)%Z ->
(0 < d)%Z ->
(0 < f)%Z -> (a * d < c * b)%Z -> (c * f < e * d)%Z -> (a * f < e * b)%Z.
Proof.
intros.
apply Zgt_lt.
apply Zgt_mult_reg_absorb_l with d.
Flip.
apply Zgt_trans with (c * b * f)%Z.
replace (d * (e * b))%Z with (b * (e * d))%Z.
replace (c * b * f)%Z with (b * (c * f))%Z.
apply Zlt_gt.
apply Zlt_reg_mult_l.
Flip.
assumption.
ring.
ring.
replace (c * b * f)%Z with (f * (c * b))%Z.
replace (d * (a * f))%Z with (f * (a * d))%Z.
apply Zlt_gt.
apply Zlt_reg_mult_l.
Flip.
assumption.
ring.
ring.
Qed.
Lemma square_pos : forall a : Z, a <> 0%Z -> (0 < a * a)%Z.
Proof.
intros [| p| p]; intros; [ Falsum | constructor | constructor ].
Qed.
Hint Resolve square_pos: zarith.
(*###########################################################################*)
(** Properties of positive numbers, mapping between Z and nat *)
(*###########################################################################*)
Definition Z2positive (z : Z) :=
match z with
| Zpos p => p
| Zneg p => p
| Z0 => 1%positive
end.
Lemma ZL9 : forall p : positive, Z_of_nat (nat_of_P p) = Zpos p. (*QF*)
Proof.
intro.
cut (exists h : nat, nat_of_P p = S h).
intro.
case H.
intros.
unfold Z_of_nat in |- *.
rewrite H0.
apply f_equal with (A := positive) (B := Z) (f := Zpos).
cut (P_of_succ_nat (nat_of_P p) = P_of_succ_nat (S x)).
intro.
rewrite P_of_succ_nat_o_nat_of_P_eq_succ in H1.
cut (Ppred (Psucc p) = Ppred (P_of_succ_nat (S x))).
intro.
rewrite Ppred_succ in H2.
simpl in H2.
rewrite Ppred_succ in H2.
apply sym_eq.
assumption.
apply f_equal with (A := positive) (B := positive) (f := Ppred).
assumption.
apply f_equal with (f := P_of_succ_nat).
assumption.
apply ZL4.
Qed.
Coercion Z_of_nat : nat >-> Z.
Lemma ZERO_lt_POS : forall p : positive, (0 < Zpos p)%Z.
Proof.
intros.
constructor.
Qed.
Lemma POS_neq_ZERO : forall p : positive, Zpos p <> 0%Z.
Proof.
intros.
apply sym_not_eq.
apply Zorder.Zlt_not_eq.
apply ZERO_lt_POS.
Qed.
Lemma NEG_neq_ZERO : forall p : positive, Zneg p <> 0%Z.
Proof.
intros.
apply Zorder.Zlt_not_eq.
unfold Zlt in |- *.
constructor.
Qed.
Lemma POS_resp_eq : forall p0 p1 : positive, Zpos p0 = Zpos p1 -> p0 = p1.
Proof.
intros.
injection H.
trivial.
Qed.
Lemma nat_nat_pos : forall m n : nat, ((m + 1) * (n + 1) > 0)%Z. (*QF*)
Proof.
intros.
apply Zlt_gt.
cut (Z_of_nat m + 1 > 0)%Z.
intro.
cut (0 < Z_of_nat n + 1)%Z.
intro.
cut ((Z_of_nat m + 1) * 0 < (Z_of_nat m + 1) * (Z_of_nat n + 1))%Z.
rewrite Zmult_0_r.
intro.
assumption.
apply Zlt_reg_mult_l.
assumption.
assumption.
change (0 < Zsucc (Z_of_nat n))%Z in |- *.
apply Zle_lt_succ.
change (Z_of_nat 0 <= Z_of_nat n)%Z in |- *.
apply Znat.inj_le.
apply le_O_n.
apply Zlt_gt.
change (0 < Zsucc (Z_of_nat m))%Z in |- *.
apply Zle_lt_succ.
change (Z_of_nat 0 <= Z_of_nat m)%Z in |- *.
apply Znat.inj_le.
apply le_O_n.
Qed.
Theorem S_predn : forall m : nat, m <> 0 -> S (pred m) = m. (*QF*)
Proof.
intros.
case (O_or_S m).
intro.
case s.
intros.
rewrite <- e.
rewrite <- pred_Sn with (n := x).
trivial.
intro.
apply False_ind.
apply H.
apply sym_eq.
assumption.
Qed.
Lemma absolu_1 : forall x : Z, Zabs_nat x = 0 -> x = 0%Z. (*QF*)
Proof.
intros.
case (dec_eq x 0).
intro.
assumption.
intro.
apply False_ind.
cut ((x < 0)%Z \/ (x > 0)%Z).
intro.
ElimCompare x 0%Z.
intro.
cut (x = 0%Z).
assumption.
cut ((x ?= 0)%Z = Datatypes.Eq -> x = 0%Z).
intro.
apply H3.
assumption.
apply proj1 with (B := x = 0%Z -> (x ?= 0)%Z = Datatypes.Eq).
change ((x ?= 0)%Z = Datatypes.Eq <-> x = 0%Z) in |- *.
apply Zcompare_Eq_iff_eq.
(***)
intro.
cut (exists h : nat, Zabs_nat x = S h).
intro.
case H3.
rewrite H.
exact O_S.
change (x < 0)%Z in H2.
cut (0 > x)%Z.
intro.
cut (exists p : positive, (0 + - x)%Z = Zpos p).
simpl in |- *.
intro.
case H4.
intros.
cut (exists q : positive, x = Zneg q).
intro.
case H6.
intros.
rewrite H7.
unfold Zabs_nat in |- *.
generalize x1.
exact ZL4.
cut (x = (- Zpos x0)%Z).
simpl in |- *.
intro.
exists x0.
assumption.
cut ((- - x)%Z = x).
intro.
rewrite <- H6.
exact (f_equal Zopp H5).
apply Zopp_involutive.
apply Zcompare_Gt_spec.
assumption.
apply Zlt_gt.
assumption.
(***)
intro.
cut (exists h : nat, Zabs_nat x = S h).
intro.
case H3.
rewrite H.
exact O_S.
cut (exists p : positive, (x + - (0))%Z = Zpos p).
simpl in |- *.
rewrite Zplus_0_r.
intro.
case H3.
intros.
rewrite H4.
unfold Zabs_nat in |- *.
generalize x0.
exact ZL4.
apply Zcompare_Gt_spec.
assumption.
(***)
cut ((x < 0)%Z \/ (0 < x)%Z).
intro.
apply
or_ind with (A := (x < 0)%Z) (B := (0 < x)%Z) (P := (x < 0)%Z \/ (x > 0)%Z).
intro.
left.
assumption.
intro.
right.
apply Zlt_gt.
assumption.
assumption.
apply not_Zeq.
assumption.
Qed.
Lemma absolu_2 : forall x : Z, x <> 0%Z -> Zabs_nat x <> 0. (*QF*)
Proof.
intros.
intro.
apply H.
apply absolu_1.
assumption.
Qed.
Lemma absolu_inject_nat : forall n : nat, Zabs_nat (Z_of_nat n) = n.
Proof.
simple induction n; simpl in |- *.
reflexivity.
intros.
apply nat_of_P_o_P_of_succ_nat_eq_succ.
Qed.
Lemma eq_inj : forall m n : nat, m = n :>Z -> m = n.
Proof.
intros.
generalize (f_equal Zabs_nat H).
intro.
rewrite (absolu_inject_nat m) in H0.
rewrite (absolu_inject_nat n) in H0.
assumption.
Qed.
Lemma lt_inj : forall m n : nat, (m < n)%Z -> m < n.
Proof.
intros.
omega.
Qed.
Lemma le_inj : forall m n : nat, (m <= n)%Z -> m <= n.
Proof.
intros.
omega.
Qed.
Lemma inject_nat_S_inf : forall x : Z, (0 < x)%Z -> {n : nat | x = S n}.
Proof.
intros [| p| p] Hp; try discriminate Hp.
exists (pred (nat_of_P p)).
rewrite S_predn.
symmetry in |- *; apply ZL9.
clear Hp;
apply sym_not_equal; apply lt_O_neq; apply lt_O_nat_of_P.
Qed.
Lemma le_absolu :
forall x y : Z,
(0 <= x)%Z -> (0 <= y)%Z -> (x <= y)%Z -> Zabs_nat x <= Zabs_nat y.
Proof.
intros [| x| x] [| y| y] Hx Hy Hxy;
apply le_O_n ||
(try
match goal with
| id1:(0 <= Zneg _)%Z |- _ =>
apply False_ind; apply id1; constructor
| id1:(Zpos _ <= 0)%Z |- _ =>
apply False_ind; apply id1; constructor
| id1:(Zpos _ <= Zneg _)%Z |- _ =>
apply False_ind; apply id1; constructor
end).
simpl in |- *.
apply le_inj.
do 2 rewrite ZL9.
assumption.
Qed.
Lemma lt_absolu :
forall x y : Z,
(0 <= x)%Z -> (0 <= y)%Z -> (x < y)%Z -> Zabs_nat x < Zabs_nat y.
Proof.
intros [| x| x] [| y| y] Hx Hy Hxy; inversion Hxy;
try
match goal with
| id1:(0 <= Zneg _)%Z |- _ =>
apply False_ind; apply id1; constructor
| id1:(Zpos _ <= 0)%Z |- _ =>
apply False_ind; apply id1; constructor
| id1:(Zpos _ <= Zneg _)%Z |- _ =>
apply False_ind; apply id1; constructor
end; simpl in |- *; apply lt_inj; repeat rewrite ZL9;
assumption.
Qed.
Lemma absolu_plus :
forall x y : Z,
(0 <= x)%Z -> (0 <= y)%Z -> Zabs_nat (x + y) = Zabs_nat x + Zabs_nat y.
Proof.
intros [| x| x] [| y| y] Hx Hy; trivial;
try
match goal with
| id1:(0 <= Zneg _)%Z |- _ =>
apply False_ind; apply id1; constructor
| id1:(Zpos _ <= 0)%Z |- _ =>
apply False_ind; apply id1; constructor
| id1:(Zpos _ <= Zneg _)%Z |- _ =>
apply False_ind; apply id1; constructor
end.
rewrite <- BinInt.Zpos_plus_distr.
unfold Zabs_nat in |- *.
apply nat_of_P_plus_morphism.
Qed.
Lemma pred_absolu :
forall x : Z, (0 < x)%Z -> pred (Zabs_nat x) = Zabs_nat (x - 1).
Proof.
intros x Hx.
generalize (Z_lt_lt_S_eq_dec 0 x Hx); simpl in |- *; intros [H1| H1];
[ replace (Zabs_nat x) with (Zabs_nat (x - 1 + 1));
[ idtac | apply f_equal with Z; auto with zarith ];
rewrite absolu_plus;
[ unfold Zabs_nat at 2, nat_of_P, Piter_op in |- *; omega
| auto with zarith
| intro; discriminate ]
| rewrite <- H1; reflexivity ].
Qed.
Definition pred_nat : forall (x : Z) (Hx : (0 < x)%Z), nat.
intros [| px| px] Hx; try abstract (discriminate Hx).
exact (pred (nat_of_P px)).
Defined.
Lemma pred_nat_equal :
forall (x : Z) (Hx1 Hx2 : (0 < x)%Z), pred_nat x Hx1 = pred_nat x Hx2.
Proof.
intros [| px| px] Hx1 Hx2; try (discriminate Hx1); trivial.
Qed.
Let pred_nat_unfolded_subproof px :
Pos.to_nat px <> 0.
Proof.
apply sym_not_equal; apply lt_O_neq; apply lt_O_nat_of_P.
Qed.
Lemma pred_nat_unfolded :
forall (x : Z) (Hx : (0 < x)%Z), x = S (pred_nat x Hx).
Proof.
intros [| px| px] Hx; try discriminate Hx.
unfold pred_nat in |- *.
rewrite S_predn.
symmetry in |- *; apply ZL9.
clear Hx; apply pred_nat_unfolded_subproof.
Qed.
Lemma absolu_pred_nat :
forall (m : Z) (Hm : (0 < m)%Z), S (pred_nat m Hm) = Zabs_nat m.
Proof.
intros [| px| px] Hx; try discriminate Hx.
unfold pred_nat in |- *.
rewrite S_predn.
reflexivity.
apply pred_nat_unfolded_subproof.
Qed.
Lemma pred_nat_absolu :
forall (m : Z) (Hm : (0 < m)%Z), pred_nat m Hm = Zabs_nat (m - 1).
Proof.
intros [| px| px] Hx; try discriminate Hx.
unfold pred_nat in |- *.
rewrite <- pred_absolu; reflexivity || assumption.
Qed.
Lemma minus_pred_nat :
forall (n m : Z) (Hn : (0 < n)%Z) (Hm : (0 < m)%Z) (Hnm : (0 < n - m)%Z),
S (pred_nat n Hn) - S (pred_nat m Hm) = S (pred_nat (n - m) Hnm).
Proof.
intros.
simpl in |- *.
destruct n; try discriminate Hn.
destruct m; try discriminate Hm.
unfold pred_nat at 1 2 in |- *.
rewrite minus_pred; try apply lt_O_nat_of_P.
apply eq_inj.
rewrite <- pred_nat_unfolded.
rewrite Znat.inj_minus1.
repeat rewrite ZL9.
reflexivity.
apply le_inj.
apply Zlt_le_weak.
repeat rewrite ZL9.
apply Zlt_O_minus_lt.
assumption.
Qed.
(*###########################################################################*)
(** Properties of Zsgn *)
(*###########################################################################*)
Lemma Zsgn_1 :
forall x : Z, {Zsgn x = 0%Z} + {Zsgn x = 1%Z} + {Zsgn x = (-1)%Z}. (*QF*)
Proof.
intros.
case x.
left.
left.
unfold Zsgn in |- *.
reflexivity.
intro.
simpl in |- *.
left.
right.
reflexivity.
intro.
right.
simpl in |- *.
reflexivity.
Qed.
Lemma Zsgn_2 : forall x : Z, Zsgn x = 0%Z -> x = 0%Z. (*QF*)
Proof.
intros [| p1| p1]; simpl in |- *; intro H; constructor || discriminate H.
Qed.
Lemma Zsgn_3 : forall x : Z, x <> 0%Z -> Zsgn x <> 0%Z. (*QF*)
Proof.
intro.
case x.
intros.
apply False_ind.
apply H.
reflexivity.
intros.
simpl in |- *.
discriminate.
intros.
simpl in |- *.
discriminate.
Qed.
Theorem Zsgn_4 : forall a : Z, a = (Zsgn a * Zabs_nat a)%Z. (*QF*)
Proof.
intro.
case a.
simpl in |- *.
reflexivity.
intro.
unfold Zsgn in |- *.
unfold Zabs_nat in |- *.
rewrite Zmult_1_l.
symmetry in |- *.
apply ZL9.
intros.
unfold Zsgn in |- *.
unfold Zabs_nat in |- *.
rewrite ZL9.
constructor.
Qed.
Theorem Zsgn_5 :
forall a b x y : Z,
x <> 0%Z ->
y <> 0%Z ->
(Zsgn a * x)%Z = (Zsgn b * y)%Z -> (Zsgn a * y)%Z = (Zsgn b * x)%Z. (*QF*)
Proof.
intros a b x y H H0.
case a.
case b.
simpl in |- *.
trivial.
intro.
unfold Zsgn in |- *.
intro.
rewrite Zmult_1_l in H1.
simpl in H1.
apply False_ind.
apply H0.
symmetry in |- *.
assumption.
intro.
unfold Zsgn in |- *.
intro.
apply False_ind.
apply H0.
apply Zopp_inj.
simpl in |- *.
transitivity (-1 * y)%Z.
constructor.
transitivity (0 * x)%Z.
symmetry in |- *.
assumption.
simpl in |- *.
reflexivity.
intro.
unfold Zsgn at 1 in |- *.
unfold Zsgn at 2 in |- *.
intro.
transitivity y.
rewrite Zmult_1_l.
reflexivity.
transitivity (Zsgn b * (Zsgn b * y))%Z.
case (Zsgn_1 b).
intro.
case s.
intro.
apply False_ind.
apply H.
rewrite e in H1.
change ((1 * x)%Z = 0%Z) in H1.
rewrite Zmult_1_l in H1.
assumption.
intro.
rewrite e.
rewrite Zmult_1_l.
rewrite Zmult_1_l.
reflexivity.
intro.
rewrite e.
ring.
rewrite Zmult_1_l in H1.
rewrite H1.
reflexivity.
intro.
unfold Zsgn at 1 in |- *.
unfold Zsgn at 2 in |- *.
intro.
transitivity (Zsgn b * (-1 * (Zsgn b * y)))%Z.
case (Zsgn_1 b).
intros.
case s.
intro.
apply False_ind.
apply H.
apply Zopp_inj.
transitivity (-1 * x)%Z.
ring.
unfold Zopp in |- *.
rewrite e in H1.
transitivity (0 * y)%Z.
assumption.
simpl in |- *.
reflexivity.
intro.
rewrite e.
ring.
intro.
rewrite e.
ring.
rewrite <- H1.
ring.
Qed.
Lemma Zsgn_6 : forall x : Z, x = 0%Z -> Zsgn x = 0%Z.
Proof.
intros.
rewrite H.
simpl in |- *.
reflexivity.
Qed.
Lemma Zsgn_7 : forall x : Z, (x > 0)%Z -> Zsgn x = 1%Z.
Proof.
intro.
case x.
intro.
apply False_ind.
apply (Zlt_irrefl 0).
Flip.
intros.
simpl in |- *.
reflexivity.
intros.
apply False_ind.
apply (Zlt_irrefl (Zneg p)).
apply Zlt_trans with 0%Z.
constructor.
Flip.
Qed.
Lemma Zsgn_7' : forall x : Z, (0 < x)%Z -> Zsgn x = 1%Z.
Proof.
intros; apply Zsgn_7; Flip.
Qed.
Lemma Zsgn_8 : forall x : Z, (x < 0)%Z -> Zsgn x = (-1)%Z.
Proof.
intro.
case x.
intro.
apply False_ind.
apply (Zlt_irrefl 0).
assumption.
intros.
apply False_ind.
apply (Zlt_irrefl 0).
apply Zlt_trans with (Zpos p).
constructor.
assumption.
intros.
simpl in |- *.
reflexivity.
Qed.
Lemma Zsgn_9 : forall x : Z, Zsgn x = 1%Z -> (0 < x)%Z.
Proof.
intro.
case x.
intro.
apply False_ind.
simpl in H.
discriminate.
intros.
constructor.
intros.
apply False_ind.
discriminate.
Qed.
Lemma Zsgn_10 : forall x : Z, Zsgn x = (-1)%Z -> (x < 0)%Z.
Proof.
intro.
case x.
intro.
apply False_ind.
discriminate.
intros.
apply False_ind.
discriminate.
intros.
constructor.
Qed.
Lemma Zsgn_11 : forall x : Z, (Zsgn x < 0)%Z -> (x < 0)%Z.
Proof.
intros.
apply Zsgn_10.
case (Zsgn_1 x).
intro.
apply False_ind.
case s.
intro.
generalize (Zorder.Zlt_not_eq _ _ H).
intro.
apply (H0 e).
intro.
rewrite e in H.
generalize (Zorder.Zlt_not_eq _ _ H).
intro.
discriminate.
trivial.
Qed.
Lemma Zsgn_12 : forall x : Z, (0 < Zsgn x)%Z -> (0 < x)%Z.
Proof.
intros.
apply Zsgn_9.
case (Zsgn_1 x).
intro.
case s.
intro.
generalize (Zorder.Zlt_not_eq _ _ H).
intro.
generalize (sym_eq e).
intro.
apply False_ind.
apply (H0 H1).
trivial.
intro.
rewrite e in H.
generalize (Zorder.Zlt_not_eq _ _ H).
intro.
apply False_ind.
discriminate.
Qed.
Lemma Zsgn_13 : forall x : Z, (0 <= Zsgn x)%Z -> (0 <= x)%Z.
Proof.
intros.
case (Z_le_lt_eq_dec 0 (Zsgn x) H).
intro.
apply Zlt_le_weak.
apply Zsgn_12.
assumption.
intro.
assert (x = 0%Z).
apply Zsgn_2.
symmetry in |- *.
assumption.
rewrite H0.
apply Zle_refl.
Qed.
Lemma Zsgn_14 : forall x : Z, (Zsgn x <= 0)%Z -> (x <= 0)%Z.
Proof.
intros.
case (Z_le_lt_eq_dec (Zsgn x) 0 H).
intro.
apply Zlt_le_weak.
apply Zsgn_11.
assumption.
intro.
assert (x = 0%Z).
apply Zsgn_2.
assumption.
rewrite H0.
apply Zle_refl.
Qed.
Lemma Zsgn_15 : forall x y : Z, Zsgn (x * y) = (Zsgn x * Zsgn y)%Z.
Proof.
intros [y| p1 [| p2| p2]| p1 [| p2| p2]]; simpl in |- *; constructor.
Qed.
Lemma Zsgn_16 :
forall x y : Z,
Zsgn (x * y) = 1%Z -> {(0 < x)%Z /\ (0 < y)%Z} + {(x < 0)%Z /\ (y < 0)%Z}.
Proof.
intros [y| p1 [| p2| p2]| p1 [| p2| p2]]; simpl in |- *; intro H;
try discriminate H; [ left | right ]; repeat split.
Qed.
Lemma Zsgn_17 :
forall x y : Z,
Zsgn (x * y) = (-1)%Z -> {(0 < x)%Z /\ (y < 0)%Z} + {(x < 0)%Z /\ (0 < y)%Z}.
Proof.
intros [y| p1 [| p2| p2]| p1 [| p2| p2]]; simpl in |- *; intro H;
try discriminate H; [ left | right ]; repeat split.
Qed.
Lemma Zsgn_18 : forall x y : Z, Zsgn (x * y) = 0%Z -> {x = 0%Z} + {y = 0%Z}.
Proof.
intros [y| p1 [| p2| p2]| p1 [| p2| p2]]; simpl in |- *; intro H;
try discriminate H; [ left | right | right ]; constructor.
Qed.
Lemma Zsgn_19 : forall x y : Z, (0 < Zsgn x + Zsgn y)%Z -> (0 < x + y)%Z.
Proof.
Proof.
intros [y| p1 [| p2| p2]| p1 [| p2| p2]]; simpl in |- *; intro H;
discriminate H || (constructor || apply Zsgn_12; assumption).
Qed.
Lemma Zsgn_20 : forall x y : Z, (Zsgn x + Zsgn y < 0)%Z -> (x + y < 0)%Z.
Proof.
Proof.
intros [y| p1 [| p2| p2]| p1 [| p2| p2]]; simpl in |- *; intro H;
discriminate H || (constructor || apply Zsgn_11; assumption).
Qed.
Lemma Zsgn_21 : forall x y : Z, (0 < Zsgn x + Zsgn y)%Z -> (0 <= x)%Z.
Proof.
intros [y| p1 [| p2| p2]| p1 [| p2| p2]]; simpl in |- *; intros H H0;
discriminate H || discriminate H0.
Qed.
Lemma Zsgn_22 : forall x y : Z, (Zsgn x + Zsgn y < 0)%Z -> (x <= 0)%Z.
Proof.
Proof.
intros [y| p1 [| p2| p2]| p1 [| p2| p2]]; simpl in |- *; intros H H0;
discriminate H || discriminate H0.
Qed.
Lemma Zsgn_23 : forall x y : Z, (0 < Zsgn x + Zsgn y)%Z -> (0 <= y)%Z.
Proof.
intros [[| p2| p2]| p1 [| p2| p2]| p1 [| p2| p2]]; simpl in |- *;
intros H H0; discriminate H || discriminate H0.
Qed.
Lemma Zsgn_24 : forall x y : Z, (Zsgn x + Zsgn y < 0)%Z -> (y <= 0)%Z.
Proof.
intros [[| p2| p2]| p1 [| p2| p2]| p1 [| p2| p2]]; simpl in |- *;
intros H H0; discriminate H || discriminate H0.
Qed.
Lemma Zsgn_25 : forall x : Z, Zsgn (- x) = (- Zsgn x)%Z.
Proof.
intros [| p1| p1]; simpl in |- *; reflexivity.
Qed.
Lemma Zsgn_26 : forall x : Z, (0 < x)%Z -> (0 < Zsgn x)%Z.
Proof.
intros [| p| p] Hp; trivial.
Qed.
Lemma Zsgn_27 : forall x : Z, (x < 0)%Z -> (Zsgn x < 0)%Z.
Proof.
intros [| p| p] Hp; trivial.
Qed.
Hint Resolve Zsgn_1 Zsgn_2 Zsgn_3 Zsgn_4 Zsgn_5 Zsgn_6 Zsgn_7 Zsgn_7' Zsgn_8
Zsgn_9 Zsgn_10 Zsgn_11 Zsgn_12 Zsgn_13 Zsgn_14 Zsgn_15 Zsgn_16 Zsgn_17
Zsgn_18 Zsgn_19 Zsgn_20 Zsgn_21 Zsgn_22 Zsgn_23 Zsgn_24 Zsgn_25 Zsgn_26
Zsgn_27: zarith.
(*###########################################################################*)
(** Properties of Zabs *)
(*###########################################################################*)
Lemma Zabs_1 : forall z p : Z, (Zabs z < p)%Z -> (z < p)%Z /\ (- p < z)%Z.
Proof.
intros z p.
case z.
intros.
simpl in H.
split.
assumption.
apply Zgt_mult_conv_absorb_l with (a := (-1)%Z).
replace (-1)%Z with (Zpred 0).
apply Zlt_pred.
simpl; trivial.
ring_simplify (-1 * - p)%Z (-1 * 0)%Z.
apply Zlt_gt.
assumption.
intros.
simpl in H.
split.
assumption.
apply Zlt_trans with (m := 0%Z).
apply Zgt_mult_conv_absorb_l with (a := (-1)%Z).
replace (-1)%Z with (Zpred 0).
apply Zlt_pred.
simpl; trivial.
ring_simplify (-1 * - p)%Z (-1 * 0)%Z.
apply Zlt_gt.
apply Zlt_trans with (m := Zpos p0).
constructor.
assumption.
constructor.
intros.
simpl in H.
split.
apply Zlt_trans with (m := Zpos p0).
constructor.
assumption.
apply Zgt_mult_conv_absorb_l with (a := (-1)%Z).
replace (-1)%Z with (Zpred 0).
apply Zlt_pred.
simpl;trivial.
ring_simplify (-1 * - p)%Z.
replace (-1 * Zneg p0)%Z with (- Zneg p0)%Z.
replace (- Zneg p0)%Z with (Zpos p0).
apply Zlt_gt.
assumption.
symmetry in |- *.
apply Zopp_neg.
rewrite Zopp_mult_distr_l_reverse with (n := 1%Z).
simpl in |- *.
constructor.
Qed.
Lemma Zabs_2 : forall z p : Z, (Zabs z > p)%Z -> (z > p)%Z \/ (- p > z)%Z.
Proof.
intros z p.
case z.
intros.
simpl in H.
left.
assumption.
intros.
simpl in H.
left.
assumption.
intros.
simpl in H.
right.
apply Zlt_gt.
apply Zgt_mult_conv_absorb_l with (a := (-1)%Z).
constructor.
ring_simplify (-1 * - p)%Z.
replace (-1 * Zneg p0)%Z with (Zpos p0).
assumption.
reflexivity.
Qed.
Lemma Zabs_3 : forall z p : Z, (z < p)%Z /\ (- p < z)%Z -> (Zabs z < p)%Z.
Proof.
intros z p.
case z.
intro.
simpl in |- *.
elim H.
intros.
assumption.
intros.
elim H.
intros.
simpl in |- *.
assumption.
intros.
elim H.
intros.
simpl in |- *.
apply Zgt_mult_conv_absorb_l with (a := (-1)%Z).
constructor.
replace (-1 * Zpos p0)%Z with (Zneg p0).
replace (-1 * p)%Z with (- p)%Z.
apply Zlt_gt.
assumption.
ring.
simpl in |- *.
reflexivity.
Qed.
Lemma Zabs_4 : forall z p : Z, (Zabs z < p)%Z -> (- p < z < p)%Z.
Proof.
intros.
split.
apply proj2 with (A := (z < p)%Z).
apply Zabs_1.
assumption.
apply proj1 with (B := (- p < z)%Z).
apply Zabs_1.
assumption.
Qed.
Lemma Zabs_5 : forall z p : Z, (Zabs z <= p)%Z -> (- p <= z <= p)%Z.
Proof.
intros.
split.
replace (- p)%Z with (Zsucc (- Zsucc p)).
apply Zlt_le_succ.
apply proj2 with (A := (z < Zsucc p)%Z).
apply Zabs_1.
apply Zle_lt_succ.
assumption.
unfold Zsucc in |- *.
ring.
apply Zlt_succ_le.
apply proj1 with (B := (- Zsucc p < z)%Z).
apply Zabs_1.
apply Zle_lt_succ.
assumption.
Qed.
Lemma Zabs_6 : forall z p : Z, (Zabs z <= p)%Z -> (z <= p)%Z.
Proof.
intros.
apply proj2 with (A := (- p <= z)%Z).
apply Zabs_5.
assumption.
Qed.
Lemma Zabs_7 : forall z p : Z, (Zabs z <= p)%Z -> (- p <= z)%Z.
Proof.
intros.
apply proj1 with (B := (z <= p)%Z).
apply Zabs_5.
assumption.
Qed.
Lemma Zabs_8 : forall z p : Z, (- p <= z <= p)%Z -> (Zabs z <= p)%Z.
Proof.
intros.
apply Zlt_succ_le.
apply Zabs_3.
elim H.
intros.
split.
apply Zle_lt_succ.
assumption.
apply Zlt_le_trans with (m := (- p)%Z).
apply Zgt_lt.
apply Zlt_opp.
apply Zlt_succ.
assumption.
Qed.
Lemma Zabs_min : forall z : Z, Zabs z = Zabs (- z).
Proof.
intro.
case z.
simpl in |- *.
reflexivity.
intro.
simpl in |- *.
reflexivity.
intro.
simpl in |- *.
reflexivity.
Qed.
Lemma Zabs_9 :
forall z p : Z, (0 <= p)%Z -> (p < z)%Z \/ (z < - p)%Z -> (p < Zabs z)%Z.
Proof.
intros.
case H0.
intro.
replace (Zabs z) with z.
assumption.
symmetry in |- *.
apply Zabs_eq.
apply Zlt_le_weak.
apply Zle_lt_trans with (m := p).
assumption.
assumption.
intro.
cut (Zabs z = (- z)%Z).
intro.
rewrite H2.
apply Zmin_cancel_Zlt.
ring_simplify (- - z)%Z.
assumption.
rewrite Zabs_min.
apply Zabs_eq.
apply Zlt_le_weak.
apply Zle_lt_trans with (m := p).
assumption.
apply Zmin_cancel_Zlt.
ring_simplify (- - z)%Z.
assumption.
Qed.
Lemma Zabs_10 : forall z : Z, (0 <= Zabs z)%Z.
Proof.
intro.
case (Z_zerop z).
intro.
rewrite e.
simpl in |- *.
apply Zle_refl.
intro.
case (not_Zeq z 0 n).
intro.
apply Zlt_le_weak.
apply Zabs_9.
apply Zle_refl.
simpl in |- *.
right.
assumption.
intro.
apply Zlt_le_weak.
apply Zabs_9.
apply Zle_refl.
simpl in |- *.
left.
assumption.
Qed.
Lemma Zabs_11 : forall z : Z, z <> 0%Z -> (0 < Zabs z)%Z.
Proof.
intros.
apply Zabs_9.
apply Zle_refl.
simpl in |- *.
apply not_Zeq.
intro.
apply H.
symmetry in |- *.
assumption.
Qed.
Lemma Zabs_12 : forall z m : Z, (m < Zabs z)%Z -> {(m < z)%Z} + {(z < - m)%Z}.
Proof.
intros [| p| p] m; simpl in |- *; intros H;
[ left | left | right; apply Zmin_cancel_Zlt; rewrite Zopp_involutive ];
assumption.
Qed.
Lemma Zabs_mult : forall z p : Z, Zabs (z * p) = (Zabs z * Zabs p)%Z.
Proof.
intros.
case z.
simpl in |- *.
reflexivity.
case p.
simpl in |- *.
reflexivity.
intros.
simpl in |- *.
reflexivity.
intros.
simpl in |- *.
reflexivity.
case p.
intro.
simpl in |- *.
reflexivity.
intros.
simpl in |- *.
reflexivity.
intros.
simpl in |- *.
reflexivity.
Qed.
Lemma Zabs_plus : forall z p : Z, (Zabs (z + p) <= Zabs z + Zabs p)%Z.
Proof.
intros.
case z.
simpl in |- *.
apply Zle_refl.
case p.
intro.
simpl in |- *.
apply Zle_refl.
intros.
simpl in |- *.
apply Zle_refl.
intros.
unfold Zabs at 2 in |- *.
unfold Zabs at 2 in |- *.
apply Zabs_8.
split.
apply Zplus_le_reg_l with (Zpos p1 - Zneg p0)%Z.
replace (Zpos p1 - Zneg p0 + - (Zpos p1 + Zpos p0))%Z with
(- (Zpos p0 + Zneg p0))%Z.
replace (Zpos p1 - Zneg p0 + (Zpos p1 + Zneg p0))%Z with (2 * Zpos p1)%Z.
replace (- (Zpos p0 + Zneg p0))%Z with 0%Z.
apply Zmult_gt_0_le_0_compat.
constructor.
apply Zlt_le_weak.
constructor.
rewrite <- Zopp_neg with p0.
ring.
ring.
ring.
apply Zplus_le_compat.
apply Zle_refl.
apply Zlt_le_weak.
constructor.
case p.
simpl in |- *.
intro.
apply Zle_refl.
intros.
unfold Zabs at 2 in |- *.
unfold Zabs at 2 in |- *.
apply Zabs_8.
split.
apply Zplus_le_reg_l with (Zpos p1 + Zneg p0)%Z.
replace (Zpos p1 + Zneg p0 + - (Zpos p1 + Zpos p0))%Z with
(Zneg p0 - Zpos p0)%Z.
replace (Zpos p1 + Zneg p0 + (Zneg p1 + Zpos p0))%Z with 0%Z.
apply Zplus_le_reg_l with (Zpos p0).
replace (Zpos p0 + (Zneg p0 - Zpos p0))%Z with (Zneg p0).
simpl in |- *.
apply Zlt_le_weak.
constructor.
ring.
replace (Zpos p1 + Zneg p0 + (Zneg p1 + Zpos p0))%Z with
(Zpos p1 + Zneg p1 + (Zpos p0 + Zneg p0))%Z.
replace 0%Z with (0 + 0)%Z.
apply Zplus_eq_compat.
rewrite <- Zopp_neg with p1.
ring.
rewrite <- Zopp_neg with p0.
ring.
simpl in |- *.
constructor.
ring.
ring.
apply Zplus_le_compat.
apply Zlt_le_weak.
constructor.
apply Zle_refl.
intros.
simpl in |- *.
apply Zle_refl.
Qed.
Lemma Zabs_neg : forall z : Z, (z <= 0)%Z -> Zabs z = (- z)%Z.
Proof.
intro.
case z.
simpl in |- *.
intro.
reflexivity.
intros.
apply False_ind.
apply H.
simpl in |- *.
reflexivity.
intros.
simpl in |- *.
reflexivity.
Qed.
Lemma Zle_Zabs: forall z, (z <= Zabs z)%Z.
Proof.
intros [|z|z]; simpl; auto with zarith; apply Zle_neg_pos.
Qed.
Hint Resolve Zabs_1 Zabs_2 Zabs_3 Zabs_4 Zabs_5 Zabs_6 Zabs_7 Zabs_8 Zabs_9
Zabs_10 Zabs_11 Zabs_12 Zabs_min Zabs_neg Zabs_mult Zabs_plus Zle_Zabs: zarith.
(*###########################################################################*)
(** Induction on Z *)
(*###########################################################################*)
Lemma Zind :
forall (P : Z -> Prop) (p : Z),
P p ->
(forall q : Z, (p <= q)%Z -> P q -> P (q + 1)%Z) ->
forall q : Z, (p <= q)%Z -> P q.
Proof.
intros P p.
intro.
intro.
cut (forall q : Z, (p <= q)%Z -> exists k : nat, q = (p + k)%Z).
intro.
cut (forall k : nat, P (p + k)%Z).
intro.
intros.
cut (exists k : nat, q = (p + Z_of_nat k)%Z).
intro.
case H4.
intros.
rewrite H5.
apply H2.
apply H1.
assumption.
intro.
induction k as [| k Hreck].
simpl in |- *.
ring_simplify (p + 0)%Z.
assumption.
replace (p + Z_of_nat (S k))%Z with (p + k + 1)%Z.
apply H0.
apply Zplus_le_reg_l with (p := (- p)%Z).
replace (- p + p)%Z with (Z_of_nat 0).
ring_simplify (- p + (p + Z_of_nat k))%Z.
apply Znat.inj_le.
apply le_O_n.
ring_simplify; auto with arith.
assumption.
rewrite (Znat.inj_S k).
unfold Zsucc in |- *.
ring.
intros.
cut (exists k : nat, (q - p)%Z = Z_of_nat k).
intro.
case H2.
intro k.
intros.
exists k.
apply Zplus_reg_l with (n := (- p)%Z).
replace (- p + q)%Z with (q - p)%Z.
rewrite H3.
ring.
ring.
apply Z_of_nat_complete.
unfold Zminus in |- *.
apply Zle_left.
assumption.
Qed.
Lemma Zrec :
forall (P : Z -> Set) (p : Z),
P p ->
(forall q : Z, (p <= q)%Z -> P q -> P (q + 1)%Z) ->
forall q : Z, (p <= q)%Z -> P q.
Proof.
intros F p.
intro.
intro.
cut (forall q : Z, (p <= q)%Z -> {k : nat | q = (p + k)%Z}).
intro.
cut (forall k : nat, F (p + k)%Z).
intro.
intros.
cut {k : nat | q = (p + Z_of_nat k)%Z}.
intro.
case H4.
intros.
rewrite e.
apply H2.
apply H1.
assumption.
intro.
induction k as [| k Hreck].
simpl in |- *.
rewrite Zplus_0_r.
assumption.
replace (p + Z_of_nat (S k))%Z with (p + k + 1)%Z.
apply H0.
apply Zplus_le_reg_l with (p := (- p)%Z).
replace (- p + p)%Z with (Z_of_nat 0).
replace (- p + (p + Z_of_nat k))%Z with (Z_of_nat k).
apply Znat.inj_le.
apply le_O_n.
rewrite Zplus_assoc; rewrite Zplus_opp_l; reflexivity.
rewrite Zplus_opp_l; reflexivity.
assumption.
rewrite (Znat.inj_S k).
unfold Zsucc in |- *.
apply Zplus_assoc_reverse.
intros.
cut {k : nat | (q - p)%Z = Z_of_nat k}.
intro H2.
case H2.
intro k.
intros.
exists k.
apply Zplus_reg_l with (n := (- p)%Z).
replace (- p + q)%Z with (q - p)%Z.
rewrite e.
rewrite Zplus_assoc; rewrite Zplus_opp_l; reflexivity.
unfold Zminus in |- *.
apply Zplus_comm.
apply Z_of_nat_complete_inf.
unfold Zminus in |- *.
apply Zle_left.
assumption.
Qed.
Lemma Zrec_down :
forall (P : Z -> Set) (p : Z),
P p ->
(forall q : Z, (q <= p)%Z -> P q -> P (q - 1)%Z) ->
forall q : Z, (q <= p)%Z -> P q.
Proof.
intros F p.
intro.
intro.
cut (forall q : Z, (q <= p)%Z -> {k : nat | q = (p - k)%Z}).
intro.
cut (forall k : nat, F (p - k)%Z).
intro.
intros.
cut {k : nat | q = (p - Z_of_nat k)%Z}.
intro.
case H4.
intros.
rewrite e.
apply H2.
apply H1.
assumption.
intro.
induction k as [| k Hreck].
simpl in |- *.
replace (p - 0)%Z with p.
assumption.
unfold Zminus in |- *.
unfold Zopp in |- *.
rewrite Zplus_0_r; reflexivity.
replace (p - Z_of_nat (S k))%Z with (p - k - 1)%Z.
apply H0.
apply Zplus_le_reg_l with (p := (- p)%Z).
replace (- p + p)%Z with (- Z_of_nat 0)%Z.
replace (- p + (p - Z_of_nat k))%Z with (- Z_of_nat k)%Z.
apply Zge_le.
apply Zge_opp.
apply Znat.inj_le.
apply le_O_n.
unfold Zminus in |- *; rewrite Zplus_assoc; rewrite Zplus_opp_l; reflexivity.
rewrite Zplus_opp_l; reflexivity.
assumption.
rewrite (Znat.inj_S k).
unfold Zsucc in |- *.
unfold Zminus at 1 2 in |- *.
rewrite Zplus_assoc_reverse.
rewrite <- Zopp_plus_distr.
reflexivity.
intros.
cut {k : nat | (p - q)%Z = Z_of_nat k}.
intro.
case H2.
intro k.
intros.
exists k.
apply Zopp_inj.
apply Zplus_reg_l with (n := p).
replace (p + - (p - Z_of_nat k))%Z with (Z_of_nat k).
rewrite <- e.
reflexivity.
unfold Zminus in |- *.
rewrite Zopp_plus_distr.
rewrite Zplus_assoc.
rewrite Zplus_opp_r.
rewrite Zopp_involutive.
reflexivity.
apply Z_of_nat_complete_inf.
unfold Zminus in |- *.
apply Zle_left.
assumption.
Qed.
Lemma Zind_down :
forall (P : Z -> Prop) (p : Z),
P p ->
(forall q : Z, (q <= p)%Z -> P q -> P (q - 1)%Z) ->
forall q : Z, (q <= p)%Z -> P q.
Proof.
intros F p.
intro.
intro.
cut (forall q : Z, (q <= p)%Z -> exists k : nat, q = (p - k)%Z).
intro.
cut (forall k : nat, F (p - k)%Z).
intro.
intros.
cut (exists k : nat, q = (p - Z_of_nat k)%Z).
intro.
case H4.
intros x e.
rewrite e.
apply H2.
apply H1.
assumption.
intro.
induction k as [| k Hreck].
simpl in |- *.
replace (p - 0)%Z with p.
assumption.
ring.
replace (p - Z_of_nat (S k))%Z with (p - k - 1)%Z.
apply H0.
apply Zplus_le_reg_l with (p := (- p)%Z).
replace (- p + p)%Z with (- Z_of_nat 0)%Z.
replace (- p + (p - Z_of_nat k))%Z with (- Z_of_nat k)%Z.
apply Zge_le.
apply Zge_opp.
apply Znat.inj_le.
apply le_O_n.
ring.
ring_simplify; auto with arith.
assumption.
rewrite (Znat.inj_S k).
unfold Zsucc in |- *.
ring.
intros.
cut (exists k : nat, (p - q)%Z = Z_of_nat k).
intro.
case H2.
intro k.
intros.
exists k.
apply Zopp_inj.
apply Zplus_reg_l with (n := p).
replace (p + - (p - Z_of_nat k))%Z with (Z_of_nat k).
rewrite <- H3.
ring.
ring.
apply Z_of_nat_complete.
unfold Zminus in |- *.
apply Zle_left.
assumption.
Qed.
Lemma Zrec_wf :
forall (P : Z -> Set) (p : Z),
(forall q : Z, (forall r : Z, (p <= r < q)%Z -> P r) -> P q) ->
forall q : Z, (p <= q)%Z -> P q.
Proof.
intros P p WF_ind_step q Hq.
cut (forall x : Z, (p <= x)%Z -> forall y : Z, (p <= y < x)%Z -> P y).
intro.
apply (H (Zsucc q)).
apply Zle_le_succ.
assumption.
split; [ assumption | exact (Zlt_succ q) ].
intros x0 Hx0; generalize Hx0; pattern x0 in |- *.
apply Zrec with (p := p).
intros.
absurd (p <= p)%Z.
apply Zgt_not_le.
apply Zgt_le_trans with (m := y).
apply Zlt_gt.
elim H.
intros.
assumption.
elim H.
intros.
assumption.
apply Zle_refl.
intros.
apply WF_ind_step.
intros.
apply (H0 H).
split.
elim H2.
intros.
assumption.
apply Zlt_le_trans with y.
elim H2.
intros.
assumption.
apply Zgt_succ_le.
apply Zlt_gt.
elim H1.
intros.
unfold Zsucc in |- *.
assumption.
assumption.
Qed.
Lemma Zrec_wf2 :
forall (q : Z) (P : Z -> Set) (p : Z),
(forall q : Z, (forall r : Z, (p <= r < q)%Z -> P r) -> P q) ->
(p <= q)%Z -> P q.
Proof.
intros.
apply Zrec_wf with (p := p).
assumption.
assumption.
Qed.
Lemma Zrec_wf_double :
forall (P : Z -> Z -> Set) (p0 q0 : Z),
(forall n m : Z,
(forall p q : Z, (q0 <= q)%Z -> (p0 <= p < n)%Z -> P p q) ->
(forall p : Z, (q0 <= p < m)%Z -> P n p) -> P n m) ->
forall p q : Z, (q0 <= q)%Z -> (p0 <= p)%Z -> P p q.
Proof.
intros P p0 q0 Hrec p.
intros.
generalize q H.
pattern p in |- *.
apply Zrec_wf with (p := p0).
intros p1 H1.
intros.
pattern q1 in |- *.
apply Zrec_wf with (p := q0).
intros q2 H3.
apply Hrec.
intros.
apply H1.
assumption.
assumption.
intros.
apply H3.
assumption.
assumption.
assumption.
Qed.
Lemma Zind_wf :
forall (P : Z -> Prop) (p : Z),
(forall q : Z, (forall r : Z, (p <= r < q)%Z -> P r) -> P q) ->
forall q : Z, (p <= q)%Z -> P q.
Proof.
intros P p WF_ind_step q Hq.
cut (forall x : Z, (p <= x)%Z -> forall y : Z, (p <= y < x)%Z -> P y).
intro.
apply (H (Zsucc q)).
apply Zle_le_succ.
assumption.
split; [ assumption | exact (Zlt_succ q) ].
intros x0 Hx0; generalize Hx0; pattern x0 in |- *.
apply Zind with (p := p).
intros.
absurd (p <= p)%Z.
apply Zgt_not_le.
apply Zgt_le_trans with (m := y).
apply Zlt_gt.
elim H.
intros.
assumption.
elim H.
intros.
assumption.
apply Zle_refl.
intros.
apply WF_ind_step.
intros.
apply (H0 H).
split.
elim H2.
intros.
assumption.
apply Zlt_le_trans with y.
elim H2.
intros.
assumption.
apply Zgt_succ_le.
apply Zlt_gt.
elim H1.
intros.
unfold Zsucc in |- *.
assumption.
assumption.
Qed.
Lemma Zind_wf2 :
forall (q : Z) (P : Z -> Prop) (p : Z),
(forall q : Z, (forall r : Z, (p <= r < q)%Z -> P r) -> P q) ->
(p <= q)%Z -> P q.
Proof.
intros.
apply Zind_wf with (p := p).
assumption.
assumption.
Qed.
Lemma Zind_wf_double :
forall (P : Z -> Z -> Prop) (p0 q0 : Z),
(forall n m : Z,
(forall p q : Z, (q0 <= q)%Z -> (p0 <= p < n)%Z -> P p q) ->
(forall p : Z, (q0 <= p < m)%Z -> P n p) -> P n m) ->
forall p q : Z, (q0 <= q)%Z -> (p0 <= p)%Z -> P p q.
Proof.
intros P p0 q0 Hrec p.
intros.
generalize q H.
pattern p in |- *.
apply Zind_wf with (p := p0).
intros p1 H1.
intros.
pattern q1 in |- *.
apply Zind_wf with (p := q0).
intros q2 H3.
apply Hrec.
intros.
apply H1.
assumption.
assumption.
intros.
apply H3.
assumption.
assumption.
assumption.
Qed.
(*###########################################################################*)
(** Properties of Zmax *)
(*###########################################################################*)
Definition Zmax (n m : Z) := (n + m - Zmin n m)%Z.
Lemma ZmaxSS : forall n m : Z, (Zmax n m + 1)%Z = Zmax (n + 1) (m + 1).
Proof.
intros.
unfold Zmax in |- *.
replace (Zmin (n + 1) (m + 1)) with (Zmin n m + 1)%Z.
ring.
symmetry in |- *.
change (Zmin (Zsucc n) (Zsucc m) = Zsucc (Zmin n m)) in |- *.
symmetry in |- *.
apply Zmin_SS.
Qed.
Lemma Zle_max_l : forall n m : Z, (n <= Zmax n m)%Z.
Proof.
intros.
unfold Zmax in |- *.
apply Zplus_le_reg_l with (p := (- n + Zmin n m)%Z).
ring_simplify (- n + Zmin n m + n)%Z.
ring_simplify (- n + Zmin n m + (n + m - Zmin n m))%Z.
apply Zle_min_r.
Qed.
Lemma Zle_max_r : forall n m : Z, (m <= Zmax n m)%Z.
Proof.
intros.
unfold Zmax in |- *.
apply Zplus_le_reg_l with (p := (- m + Zmin n m)%Z).
ring_simplify (- m + Zmin n m + m)%Z.
ring_simplify (- m + Zmin n m + (n + m - Zmin n m))%Z.
apply Zle_min_l.
Qed.
Lemma Zmin_or_informative : forall n m : Z, {Zmin n m = n} + {Zmin n m = m}.
Proof.
intros.
case (Z_lt_ge_dec n m).
unfold Zmin in |- *.
unfold Zlt in |- *.
intro z.
rewrite z.
left.
reflexivity.
intro.
cut ({(n > m)%Z} + {n = m :>Z}).
intro.
case H.
intros z0.
unfold Zmin in |- *.
unfold Zgt in z0.
rewrite z0.
right.
reflexivity.
intro.
rewrite e.
right.
apply Zmin_n_n.
cut ({(m < n)%Z} + {m = n :>Z}).
intro.
elim H.
intro.
left.
apply Zlt_gt.
assumption.
intro.
right.
symmetry in |- *.
assumption.
apply Z_le_lt_eq_dec.
apply Zge_le.
assumption.
Qed.
Lemma Zmax_case : forall (n m : Z) (P : Z -> Set), P n -> P m -> P (Zmax n m).
Proof.
intros.
unfold Zmax in |- *.
case Zmin_or_informative with (n := n) (m := m).
intro.
rewrite e.
cut ((n + m - n)%Z = m).
intro.
rewrite H1.
assumption.
ring.
intro.
rewrite e.
cut ((n + m - m)%Z = n).
intro.
rewrite H1.
assumption.
ring.
Qed.
Lemma Zmax_or_informative : forall n m : Z, {Zmax n m = n} + {Zmax n m = m}.
Proof.
intros.
unfold Zmax in |- *.
case Zmin_or_informative with (n := n) (m := m).
intro.
rewrite e.
right.
ring.
intro.
rewrite e.
left.
ring.
Qed.
Lemma Zmax_n_n : forall n : Z, Zmax n n = n.
Proof.
intros.
unfold Zmax in |- *.
rewrite (Zmin_n_n n).
ring.
Qed.
Hint Resolve ZmaxSS Zle_max_r Zle_max_l Zmax_n_n: zarith.
(*###########################################################################*)
(** Properties of Arity *)
(*###########################################################################*)
Lemma Zeven_S : forall x : Z, Zeven.Zodd x -> Zeven.Zeven (x + 1).
Proof.
exact Zeven.Zeven_Sn.
Qed.
Lemma Zeven_pred : forall x : Z, Zeven.Zodd x -> Zeven.Zeven (x - 1).
Proof.
exact Zeven.Zeven_pred.
Qed.
(* This lemma used to be useful since it was mentioned with an unnecessary premise
`x>=0` as Z_modulo_2 in ZArith, but the ZArith version has been fixed. *)
Definition Z_modulo_2_always :
forall x : Z, {y : Z | x = (2 * y)%Z} + {y : Z | x = (2 * y + 1)%Z} :=
Zeven.Z_modulo_2.
(*###########################################################################*)
(** Properties of Zdiv *)
(*###########################################################################*)
Lemma Z_div_mod_eq_2 :
forall a b : Z, (0 < b)%Z -> (b * (a / b))%Z = (a - a mod b)%Z.
Proof.
intros.
apply Zplus_minus_eq.
rewrite Zplus_comm.
apply Z_div_mod_eq.
Flip.
Qed.
Lemma Z_div_le :
forall a b c : Z, (0 < c)%Z -> (b <= a)%Z -> (b / c <= a / c)%Z.
Proof.
intros.
apply Zge_le.
apply Z_div_ge; Flip; assumption.
Qed.
Lemma Z_div_nonneg :
forall a b : Z, (0 < b)%Z -> (0 <= a)%Z -> (0 <= a / b)%Z.
Proof.
intros.
apply Zge_le.
apply Z_div_ge0; Flip; assumption.
Qed.
Lemma Z_div_neg : forall a b : Z, (0 < b)%Z -> (a < 0)%Z -> (a / b < 0)%Z.
Proof.
intros.
rewrite (Z_div_mod_eq a b) in H0.
elim (Z_mod_lt a b).
intros H1 _.
apply Znot_ge_lt.
intro.
apply (Zlt_not_le (b * (a / b) + a mod b) 0 H0).
apply Zplus_le_0_compat.
apply Zmult_le_0_compat.
apply Zlt_le_weak; assumption.
Flip.
assumption.
Flip.
Flip.
Qed.
Hint Resolve Z_div_mod_eq_2 Z_div_le Z_div_nonneg Z_div_neg: zarith.
(*###########################################################################*)
(** Properties of Zpower *)
(*###########################################################################*)
Lemma Zpower_1 : forall a : Z, (a ^ 1)%Z = a.
Proof.
intros; unfold Zpower in |- *; unfold Zpower_pos in |- *; simpl in |- *;
auto with zarith.
Qed.
Lemma Zpower_2 : forall a : Z, (a ^ 2)%Z = (a * a)%Z.
Proof.
intros; unfold Zpower in |- *; unfold Zpower_pos in |- *; simpl in |- *;
ring.
Qed.
Hint Resolve Zpower_1 Zpower_2: zarith.
|
(* -*- coding: utf-8 -*- *)
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2012 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
(** * Euclidean Division *)
(** Initial Contribution by Claude Marché and Xavier Urbain *)
Require Export ZArith_base.
Require Import Zbool Omega ZArithRing Zcomplements Setoid Morphisms.
Local Open Scope Z_scope.
(** The definition of the division is now in [BinIntDef], the initial
specifications and properties are in [BinInt]. *)
Notation Zdiv_eucl_POS := Z.pos_div_eucl (compat "8.3").
Notation Zdiv_eucl := Z.div_eucl (compat "8.3").
Notation Zdiv := Z.div (compat "8.3").
Notation Zmod := Z.modulo (compat "8.3").
Notation Zdiv_eucl_eq := Z.div_eucl_eq (compat "8.3").
Notation Z_div_mod_eq_full := Z.div_mod (compat "8.3").
Notation Zmod_POS_bound := Z.pos_div_eucl_bound (compat "8.3").
Notation Zmod_pos_bound := Z.mod_pos_bound (compat "8.3").
Notation Zmod_neg_bound := Z.mod_neg_bound (compat "8.3").
(** * Main division theorems *)
(** NB: many things are stated twice for compatibility reasons *)
Lemma Z_div_mod_POS :
forall b:Z,
b > 0 ->
forall a:positive,
let (q, r) := Z.pos_div_eucl a b in Zpos a = b * q + r /\ 0 <= r < b.
Proof.
intros b Hb a. Z.swap_greater.
generalize (Z.pos_div_eucl_eq a b Hb) (Z.pos_div_eucl_bound a b Hb).
destruct Z.pos_div_eucl. rewrite Z.mul_comm. auto.
Qed.
Theorem Z_div_mod a b :
b > 0 ->
let (q, r) := Z.div_eucl a b in a = b * q + r /\ 0 <= r < b.
Proof.
Z.swap_greater. intros Hb.
assert (Hb' : b<>0) by (now destruct b).
generalize (Z.div_eucl_eq a b Hb') (Z.mod_pos_bound a b Hb).
unfold Z.modulo. destruct Z.div_eucl. auto.
Qed.
(** For stating the fully general result, let's give a short name
to the condition on the remainder. *)
Definition Remainder r b := 0 <= r < b \/ b < r <= 0.
(** Another equivalent formulation: *)
Definition Remainder_alt r b := Z.abs r < Z.abs b /\ Z.sgn r <> - Z.sgn b.
(* In the last formulation, [ Z.sgn r <> - Z.sgn b ] is less nice than saying
[ Z.sgn r = Z.sgn b ], but at least it works even when [r] is null. *)
Lemma Remainder_equiv : forall r b, Remainder r b <-> Remainder_alt r b.
Proof.
intros; unfold Remainder, Remainder_alt; omega with *.
Qed.
Hint Unfold Remainder.
(** Now comes the fully general result about Euclidean division. *)
Theorem Z_div_mod_full a b :
b <> 0 ->
let (q, r) := Z.div_eucl a b in a = b * q + r /\ Remainder r b.
Proof.
intros Hb.
generalize (Z.div_eucl_eq a b Hb)
(Z.mod_pos_bound a b) (Z.mod_neg_bound a b).
unfold Z.modulo. destruct Z.div_eucl as (q,r).
intros EQ POS NEG.
split; auto.
red; destruct b.
now destruct Hb. left; now apply POS. right; now apply NEG.
Qed.
(** The same results as before, stated separately in terms of Z.div and Z.modulo *)
Lemma Z_mod_remainder a b : b<>0 -> Remainder (a mod b) b.
Proof.
unfold Z.modulo; intros Hb; generalize (Z_div_mod_full a b Hb); auto.
destruct Z.div_eucl; tauto.
Qed.
Lemma Z_mod_lt a b : b > 0 -> 0 <= a mod b < b.
Proof (fun Hb => Z.mod_pos_bound a b (Z.gt_lt _ _ Hb)).
Lemma Z_mod_neg a b : b < 0 -> b < a mod b <= 0.
Proof (Z.mod_neg_bound a b).
Lemma Z_div_mod_eq a b : b > 0 -> a = b*(a/b) + (a mod b).
Proof.
intros Hb; apply Z.div_mod; auto with zarith.
Qed.
Lemma Zmod_eq_full a b : b<>0 -> a mod b = a - (a/b)*b.
Proof. intros. rewrite Z.mul_comm. now apply Z.mod_eq. Qed.
Lemma Zmod_eq a b : b>0 -> a mod b = a - (a/b)*b.
Proof. intros. apply Zmod_eq_full. now destruct b. Qed.
(** Existence theorem *)
Theorem Zdiv_eucl_exist : forall (b:Z)(Hb:b>0)(a:Z),
{qr : Z * Z | let (q, r) := qr in a = b * q + r /\ 0 <= r < b}.
Proof.
intros b Hb a.
exists (Z.div_eucl a b).
exact (Z_div_mod a b Hb).
Qed.
Arguments Zdiv_eucl_exist : default implicits.
(** Uniqueness theorems *)
Theorem Zdiv_mod_unique b q1 q2 r1 r2 :
0 <= r1 < Z.abs b -> 0 <= r2 < Z.abs b ->
b*q1+r1 = b*q2+r2 -> q1=q2 /\ r1=r2.
Proof.
intros Hr1 Hr2 H. rewrite <- (Z.abs_sgn b), <- !Z.mul_assoc in H.
destruct (Z.div_mod_unique (Z.abs b) (Z.sgn b * q1) (Z.sgn b * q2) r1 r2); auto.
split; trivial.
apply Z.mul_cancel_l with (Z.sgn b); trivial.
rewrite Z.sgn_null_iff, <- Z.abs_0_iff. destruct Hr1; Z.order.
Qed.
Theorem Zdiv_mod_unique_2 :
forall b q1 q2 r1 r2:Z,
Remainder r1 b -> Remainder r2 b ->
b*q1+r1 = b*q2+r2 -> q1=q2 /\ r1=r2.
Proof Z.div_mod_unique.
Theorem Zdiv_unique_full:
forall a b q r, Remainder r b ->
a = b*q + r -> q = a/b.
Proof Z.div_unique.
Theorem Zdiv_unique:
forall a b q r, 0 <= r < b ->
a = b*q + r -> q = a/b.
Proof. intros; eapply Zdiv_unique_full; eauto. Qed.
Theorem Zmod_unique_full:
forall a b q r, Remainder r b ->
a = b*q + r -> r = a mod b.
Proof Z.mod_unique.
Theorem Zmod_unique:
forall a b q r, 0 <= r < b ->
a = b*q + r -> r = a mod b.
Proof. intros; eapply Zmod_unique_full; eauto. Qed.
(** * Basic values of divisions and modulo. *)
Lemma Zmod_0_l: forall a, 0 mod a = 0.
Proof.
destruct a; simpl; auto.
Qed.
Lemma Zmod_0_r: forall a, a mod 0 = 0.
Proof.
destruct a; simpl; auto.
Qed.
Lemma Zdiv_0_l: forall a, 0/a = 0.
Proof.
destruct a; simpl; auto.
Qed.
Lemma Zdiv_0_r: forall a, a/0 = 0.
Proof.
destruct a; simpl; auto.
Qed.
Ltac zero_or_not a :=
destruct (Z.eq_dec a 0);
[subst; rewrite ?Zmod_0_l, ?Zdiv_0_l, ?Zmod_0_r, ?Zdiv_0_r;
auto with zarith|].
Lemma Zmod_1_r: forall a, a mod 1 = 0.
Proof. intros. zero_or_not a. apply Z.mod_1_r. Qed.
Lemma Zdiv_1_r: forall a, a/1 = a.
Proof. intros. zero_or_not a. apply Z.div_1_r. Qed.
Hint Resolve Zmod_0_l Zmod_0_r Zdiv_0_l Zdiv_0_r Zdiv_1_r Zmod_1_r
: zarith.
Lemma Zdiv_1_l: forall a, 1 < a -> 1/a = 0.
Proof Z.div_1_l.
Lemma Zmod_1_l: forall a, 1 < a -> 1 mod a = 1.
Proof Z.mod_1_l.
Lemma Z_div_same_full : forall a:Z, a<>0 -> a/a = 1.
Proof Z.div_same.
Lemma Z_mod_same_full : forall a, a mod a = 0.
Proof. intros. zero_or_not a. apply Z.mod_same; auto. Qed.
Lemma Z_mod_mult : forall a b, (a*b) mod b = 0.
Proof. intros. zero_or_not b. apply Z.mod_mul. auto. Qed.
Lemma Z_div_mult_full : forall a b:Z, b <> 0 -> (a*b)/b = a.
Proof Z.div_mul.
(** * Order results about Z.modulo and Z.div *)
(* Division of positive numbers is positive. *)
Lemma Z_div_pos: forall a b, b > 0 -> 0 <= a -> 0 <= a/b.
Proof. intros. apply Z.div_pos; auto with zarith. Qed.
Lemma Z_div_ge0: forall a b, b > 0 -> a >= 0 -> a/b >=0.
Proof.
intros; generalize (Z_div_pos a b H); auto with zarith.
Qed.
(** As soon as the divisor is greater or equal than 2,
the division is strictly decreasing. *)
Lemma Z_div_lt : forall a b:Z, b >= 2 -> a > 0 -> a/b < a.
Proof. intros. apply Z.div_lt; auto with zarith. Qed.
(** A division of a small number by a bigger one yields zero. *)
Theorem Zdiv_small: forall a b, 0 <= a < b -> a/b = 0.
Proof Z.div_small.
(** Same situation, in term of modulo: *)
Theorem Zmod_small: forall a n, 0 <= a < n -> a mod n = a.
Proof Z.mod_small.
(** [Z.ge] is compatible with a positive division. *)
Lemma Z_div_ge : forall a b c:Z, c > 0 -> a >= b -> a/c >= b/c.
Proof. intros. apply Z.le_ge. apply Z.div_le_mono; auto with zarith. Qed.
(** Same, with [Z.le]. *)
Lemma Z_div_le : forall a b c:Z, c > 0 -> a <= b -> a/c <= b/c.
Proof. intros. apply Z.div_le_mono; auto with zarith. Qed.
(** With our choice of division, rounding of (a/b) is always done toward bottom: *)
Lemma Z_mult_div_ge : forall a b:Z, b > 0 -> b*(a/b) <= a.
Proof. intros. apply Z.mul_div_le; auto with zarith. Qed.
Lemma Z_mult_div_ge_neg : forall a b:Z, b < 0 -> b*(a/b) >= a.
Proof. intros. apply Z.le_ge. apply Z.mul_div_ge; auto with zarith. Qed.
(** The previous inequalities are exact iff the modulo is zero. *)
Lemma Z_div_exact_full_1 : forall a b:Z, a = b*(a/b) -> a mod b = 0.
Proof. intros a b. zero_or_not b. rewrite Z.div_exact; auto. Qed.
Lemma Z_div_exact_full_2 : forall a b:Z, b <> 0 -> a mod b = 0 -> a = b*(a/b).
Proof. intros; rewrite Z.div_exact; auto. Qed.
(** A modulo cannot grow beyond its starting point. *)
Theorem Zmod_le: forall a b, 0 < b -> 0 <= a -> a mod b <= a.
Proof. intros. apply Z.mod_le; auto. Qed.
(** Some additionnal inequalities about Z.div. *)
Theorem Zdiv_lt_upper_bound:
forall a b q, 0 < b -> a < q*b -> a/b < q.
Proof. intros a b q; rewrite Z.mul_comm; apply Z.div_lt_upper_bound. Qed.
Theorem Zdiv_le_upper_bound:
forall a b q, 0 < b -> a <= q*b -> a/b <= q.
Proof. intros a b q; rewrite Z.mul_comm; apply Z.div_le_upper_bound. Qed.
Theorem Zdiv_le_lower_bound:
forall a b q, 0 < b -> q*b <= a -> q <= a/b.
Proof. intros a b q; rewrite Z.mul_comm; apply Z.div_le_lower_bound. Qed.
(** A division of respect opposite monotonicity for the divisor *)
Lemma Zdiv_le_compat_l: forall p q r, 0 <= p -> 0 < q < r ->
p / r <= p / q.
Proof. intros; apply Z.div_le_compat_l; auto with zarith. Qed.
Theorem Zdiv_sgn: forall a b,
0 <= Z.sgn (a/b) * Z.sgn a * Z.sgn b.
Proof.
destruct a as [ |a|a]; destruct b as [ |b|b]; simpl; auto with zarith;
generalize (Z.div_pos (Zpos a) (Zpos b)); unfold Z.div, Z.div_eucl;
destruct Z.pos_div_eucl as (q,r); destruct r; omega with *.
Qed.
(** * Relations between usual operations and Z.modulo and Z.div *)
Lemma Z_mod_plus_full : forall a b c:Z, (a + b * c) mod c = a mod c.
Proof. intros. zero_or_not c. apply Z.mod_add; auto. Qed.
Lemma Z_div_plus_full : forall a b c:Z, c <> 0 -> (a + b * c) / c = a / c + b.
Proof Z.div_add.
Theorem Z_div_plus_full_l: forall a b c : Z, b <> 0 -> (a * b + c) / b = a + c / b.
Proof Z.div_add_l.
(** [Z.opp] and [Z.div], [Z.modulo].
Due to the choice of convention for our Euclidean division,
some of the relations about [Z.opp] and divisions are rather complex. *)
Lemma Zdiv_opp_opp : forall a b:Z, (-a)/(-b) = a/b.
Proof. intros. zero_or_not b. apply Z.div_opp_opp; auto. Qed.
Lemma Zmod_opp_opp : forall a b:Z, (-a) mod (-b) = - (a mod b).
Proof. intros. zero_or_not b. apply Z.mod_opp_opp; auto. Qed.
Lemma Z_mod_zero_opp_full : forall a b:Z, a mod b = 0 -> (-a) mod b = 0.
Proof. intros. zero_or_not b. apply Z.mod_opp_l_z; auto. Qed.
Lemma Z_mod_nz_opp_full : forall a b:Z, a mod b <> 0 ->
(-a) mod b = b - (a mod b).
Proof. intros. zero_or_not b. apply Z.mod_opp_l_nz; auto. Qed.
Lemma Z_mod_zero_opp_r : forall a b:Z, a mod b = 0 -> a mod (-b) = 0.
Proof. intros. zero_or_not b. apply Z.mod_opp_r_z; auto. Qed.
Lemma Z_mod_nz_opp_r : forall a b:Z, a mod b <> 0 ->
a mod (-b) = (a mod b) - b.
Proof. intros. zero_or_not b. apply Z.mod_opp_r_nz; auto. Qed.
Lemma Z_div_zero_opp_full : forall a b:Z, a mod b = 0 -> (-a)/b = -(a/b).
Proof. intros. zero_or_not b. apply Z.div_opp_l_z; auto. Qed.
Lemma Z_div_nz_opp_full : forall a b:Z, a mod b <> 0 ->
(-a)/b = -(a/b)-1.
Proof. intros a b. zero_or_not b. intros; rewrite Z.div_opp_l_nz; auto. Qed.
Lemma Z_div_zero_opp_r : forall a b:Z, a mod b = 0 -> a/(-b) = -(a/b).
Proof. intros. zero_or_not b. apply Z.div_opp_r_z; auto. Qed.
Lemma Z_div_nz_opp_r : forall a b:Z, a mod b <> 0 ->
a/(-b) = -(a/b)-1.
Proof. intros a b. zero_or_not b. intros; rewrite Z.div_opp_r_nz; auto. Qed.
(** Cancellations. *)
Lemma Zdiv_mult_cancel_r : forall a b c:Z,
c <> 0 -> (a*c)/(b*c) = a/b.
Proof. intros. zero_or_not b. apply Z.div_mul_cancel_r; auto. Qed.
Lemma Zdiv_mult_cancel_l : forall a b c:Z,
c<>0 -> (c*a)/(c*b) = a/b.
Proof.
intros. rewrite (Z.mul_comm c b); zero_or_not b.
rewrite (Z.mul_comm b c). apply Z.div_mul_cancel_l; auto.
Qed.
Lemma Zmult_mod_distr_l: forall a b c,
(c*a) mod (c*b) = c * (a mod b).
Proof.
intros. zero_or_not c. rewrite (Z.mul_comm c b); zero_or_not b.
rewrite (Z.mul_comm b c). apply Z.mul_mod_distr_l; auto.
Qed.
Lemma Zmult_mod_distr_r: forall a b c,
(a*c) mod (b*c) = (a mod b) * c.
Proof.
intros. zero_or_not b. rewrite (Z.mul_comm b c); zero_or_not c.
rewrite (Z.mul_comm c b). apply Z.mul_mod_distr_r; auto.
Qed.
(** Operations modulo. *)
Theorem Zmod_mod: forall a n, (a mod n) mod n = a mod n.
Proof. intros. zero_or_not n. apply Z.mod_mod; auto. Qed.
Theorem Zmult_mod: forall a b n,
(a * b) mod n = ((a mod n) * (b mod n)) mod n.
Proof. intros. zero_or_not n. apply Z.mul_mod; auto. Qed.
Theorem Zplus_mod: forall a b n,
(a + b) mod n = (a mod n + b mod n) mod n.
Proof. intros. zero_or_not n. apply Z.add_mod; auto. Qed.
Theorem Zminus_mod: forall a b n,
(a - b) mod n = (a mod n - b mod n) mod n.
Proof.
intros.
replace (a - b) with (a + (-1) * b); auto with zarith.
replace (a mod n - b mod n) with (a mod n + (-1) * (b mod n)); auto with zarith.
rewrite Zplus_mod.
rewrite Zmult_mod.
rewrite Zplus_mod with (b:=(-1) * (b mod n)).
rewrite Zmult_mod.
rewrite Zmult_mod with (b:= b mod n).
repeat rewrite Zmod_mod; auto.
Qed.
Lemma Zplus_mod_idemp_l: forall a b n, (a mod n + b) mod n = (a + b) mod n.
Proof.
intros; rewrite Zplus_mod, Zmod_mod, <- Zplus_mod; auto.
Qed.
Lemma Zplus_mod_idemp_r: forall a b n, (b + a mod n) mod n = (b + a) mod n.
Proof.
intros; rewrite Zplus_mod, Zmod_mod, <- Zplus_mod; auto.
Qed.
Lemma Zminus_mod_idemp_l: forall a b n, (a mod n - b) mod n = (a - b) mod n.
Proof.
intros; rewrite Zminus_mod, Zmod_mod, <- Zminus_mod; auto.
Qed.
Lemma Zminus_mod_idemp_r: forall a b n, (a - b mod n) mod n = (a - b) mod n.
Proof.
intros; rewrite Zminus_mod, Zmod_mod, <- Zminus_mod; auto.
Qed.
Lemma Zmult_mod_idemp_l: forall a b n, (a mod n * b) mod n = (a * b) mod n.
Proof.
intros; rewrite Zmult_mod, Zmod_mod, <- Zmult_mod; auto.
Qed.
Lemma Zmult_mod_idemp_r: forall a b n, (b * (a mod n)) mod n = (b * a) mod n.
Proof.
intros; rewrite Zmult_mod, Zmod_mod, <- Zmult_mod; auto.
Qed.
(** For a specific number N, equality modulo N is hence a nice setoid
equivalence, compatible with [+], [-] and [*]. *)
Section EqualityModulo.
Variable N:Z.
Definition eqm a b := (a mod N = b mod N).
Infix "==" := eqm (at level 70).
Lemma eqm_refl : forall a, a == a.
Proof. unfold eqm; auto. Qed.
Lemma eqm_sym : forall a b, a == b -> b == a.
Proof. unfold eqm; auto. Qed.
Lemma eqm_trans : forall a b c,
a == b -> b == c -> a == c.
Proof. unfold eqm; eauto with *. Qed.
Instance eqm_setoid : Equivalence eqm.
Proof.
constructor; [exact eqm_refl | exact eqm_sym | exact eqm_trans].
Qed.
Instance Zplus_eqm : Proper (eqm ==> eqm ==> eqm) Z.add.
Proof.
unfold eqm; repeat red; intros. rewrite Zplus_mod, H, H0, <- Zplus_mod; auto.
Qed.
Instance Zminus_eqm : Proper (eqm ==> eqm ==> eqm) Z.sub.
Proof.
unfold eqm; repeat red; intros. rewrite Zminus_mod, H, H0, <- Zminus_mod; auto.
Qed.
Instance Zmult_eqm : Proper (eqm ==> eqm ==> eqm) Z.mul.
Proof.
unfold eqm; repeat red; intros. rewrite Zmult_mod, H, H0, <- Zmult_mod; auto.
Qed.
Instance Zopp_eqm : Proper (eqm ==> eqm) Z.opp.
Proof.
intros x y H. change ((-x)==(-y)) with ((0-x)==(0-y)). now rewrite H.
Qed.
Lemma Zmod_eqm : forall a, (a mod N) == a.
Proof.
intros; exact (Zmod_mod a N).
Qed.
(* NB: Z.modulo and Z.div are not morphisms with respect to eqm.
For instance, let (==) be (eqm 2). Then we have (3 == 1) but:
~ (3 mod 3 == 1 mod 3)
~ (1 mod 3 == 1 mod 1)
~ (3/3 == 1/3)
~ (1/3 == 1/1)
*)
End EqualityModulo.
Lemma Zdiv_Zdiv : forall a b c, 0<=b -> 0<=c -> (a/b)/c = a/(b*c).
Proof.
intros. zero_or_not b. rewrite Z.mul_comm. zero_or_not c.
rewrite Z.mul_comm. apply Z.div_div; auto with zarith.
Qed.
(** Unfortunately, the previous result isn't always true on negative numbers.
For instance: 3/(-2)/(-2) = 1 <> 0 = 3 / (-2*-2) *)
(** A last inequality: *)
Theorem Zdiv_mult_le:
forall a b c, 0<=a -> 0<=b -> 0<=c -> c*(a/b) <= (c*a)/b.
Proof.
intros. zero_or_not b. apply Z.div_mul_le; auto with zarith. Qed.
(** Z.modulo is related to divisibility (see more in Znumtheory) *)
Lemma Zmod_divides : forall a b, b<>0 ->
(a mod b = 0 <-> exists c, a = b*c).
Proof.
intros. rewrite Z.mod_divide; trivial.
split; intros (c,Hc); exists c; subst; auto with zarith.
Qed.
(** Particular case : dividing by 2 is related with parity *)
Lemma Zdiv2_div : forall a, Z.div2 a = a/2.
Proof Z.div2_div.
Lemma Zmod_odd : forall a, a mod 2 = if Z.odd a then 1 else 0.
Proof.
intros a. now rewrite <- Z.bit0_odd, <- Z.bit0_mod.
Qed.
Lemma Zmod_even : forall a, a mod 2 = if Z.even a then 0 else 1.
Proof.
intros a. rewrite Zmod_odd, Zodd_even_bool. now destruct Z.even.
Qed.
Lemma Zodd_mod : forall a, Z.odd a = Zeq_bool (a mod 2) 1.
Proof.
intros a. rewrite Zmod_odd. now destruct Z.odd.
Qed.
Lemma Zeven_mod : forall a, Z.even a = Zeq_bool (a mod 2) 0.
Proof.
intros a. rewrite Zmod_even. now destruct Z.even.
Qed.
(** * Compatibility *)
(** Weaker results kept only for compatibility *)
Lemma Z_mod_same : forall a, a > 0 -> a mod a = 0.
Proof.
intros; apply Z_mod_same_full.
Qed.
Lemma Z_div_same : forall a, a > 0 -> a/a = 1.
Proof.
intros; apply Z_div_same_full; auto with zarith.
Qed.
Lemma Z_div_plus : forall a b c:Z, c > 0 -> (a + b * c) / c = a / c + b.
Proof.
intros; apply Z_div_plus_full; auto with zarith.
Qed.
Lemma Z_div_mult : forall a b:Z, b > 0 -> (a*b)/b = a.
Proof.
intros; apply Z_div_mult_full; auto with zarith.
Qed.
Lemma Z_mod_plus : forall a b c:Z, c > 0 -> (a + b * c) mod c = a mod c.
Proof.
intros; apply Z_mod_plus_full; auto with zarith.
Qed.
Lemma Z_div_exact_1 : forall a b:Z, b > 0 -> a = b*(a/b) -> a mod b = 0.
Proof.
intros; apply Z_div_exact_full_1; auto with zarith.
Qed.
Lemma Z_div_exact_2 : forall a b:Z, b > 0 -> a mod b = 0 -> a = b*(a/b).
Proof.
intros; apply Z_div_exact_full_2; auto with zarith.
Qed.
Lemma Z_mod_zero_opp : forall a b:Z, b > 0 -> a mod b = 0 -> (-a) mod b = 0.
Proof.
intros; apply Z_mod_zero_opp_full; auto with zarith.
Qed.
(** * A direct way to compute Z.modulo *)
Fixpoint Zmod_POS (a : positive) (b : Z) : Z :=
match a with
| xI a' =>
let r := Zmod_POS a' b in
let r' := (2 * r + 1) in
if r' <? b then r' else (r' - b)
| xO a' =>
let r := Zmod_POS a' b in
let r' := (2 * r) in
if r' <? b then r' else (r' - b)
| xH => if 2 <=? b then 1 else 0
end.
Definition Zmod' a b :=
match a with
| Z0 => 0
| Zpos a' =>
match b with
| Z0 => 0
| Zpos _ => Zmod_POS a' b
| Zneg b' =>
let r := Zmod_POS a' (Zpos b') in
match r with Z0 => 0 | _ => b + r end
end
| Zneg a' =>
match b with
| Z0 => 0
| Zpos _ =>
let r := Zmod_POS a' b in
match r with Z0 => 0 | _ => b - r end
| Zneg b' => - (Zmod_POS a' (Zpos b'))
end
end.
Theorem Zmod_POS_correct a b : Zmod_POS a b = snd (Z.pos_div_eucl a b).
Proof.
induction a as [a IH|a IH| ]; simpl; rewrite ?IH.
destruct (Z.pos_div_eucl a b) as (p,q); simpl;
case Z.ltb_spec; reflexivity.
destruct (Z.pos_div_eucl a b) as (p,q); simpl;
case Z.ltb_spec; reflexivity.
case Z.leb_spec; trivial.
Qed.
Theorem Zmod'_correct: forall a b, Zmod' a b = a mod b.
Proof.
intros a b; unfold Z.modulo; case a; simpl; auto.
intros p; case b; simpl; auto.
intros p1; refine (Zmod_POS_correct _ _); auto.
intros p1; rewrite Zmod_POS_correct; auto.
case (Z.pos_div_eucl p (Zpos p1)); simpl; intros z1 z2; case z2; auto.
intros p; case b; simpl; auto.
intros p1; rewrite Zmod_POS_correct; auto.
case (Z.pos_div_eucl p (Zpos p1)); simpl; intros z1 z2; case z2; auto.
intros p1; rewrite Zmod_POS_correct; simpl; auto.
case (Z.pos_div_eucl p (Zpos p1)); auto.
Qed.
(** Another convention is possible for division by negative numbers:
* quotient is always the biggest integer smaller than or equal to a/b
* remainder is hence always positive or null. *)
Theorem Zdiv_eucl_extended :
forall b:Z,
b <> 0 ->
forall a:Z,
{qr : Z * Z | let (q, r) := qr in a = b * q + r /\ 0 <= r < Z.abs b}.
Proof.
intros b Hb a.
elim (Z_le_gt_dec 0 b); intro Hb'.
cut (b > 0); [ intro Hb'' | omega ].
rewrite Z.abs_eq; [ apply Zdiv_eucl_exist; assumption | assumption ].
cut (- b > 0); [ intro Hb'' | omega ].
elim (Zdiv_eucl_exist Hb'' a); intros qr.
elim qr; intros q r Hqr.
exists (- q, r).
elim Hqr; intros.
split.
rewrite <- Z.mul_opp_comm; assumption.
rewrite Z.abs_neq; [ assumption | omega ].
Qed.
Arguments Zdiv_eucl_extended : default implicits.
(** * Division and modulo in Z agree with same in nat: *)
Require Import NPeano.
Lemma div_Zdiv (n m: nat): m <> O ->
Z.of_nat (n / m) = Z.of_nat n / Z.of_nat m.
Proof.
intros.
apply (Zdiv_unique _ _ _ (Z.of_nat (n mod m))).
split. auto with zarith.
now apply inj_lt, Nat.mod_upper_bound.
rewrite <- Nat2Z.inj_mul, <- Nat2Z.inj_add.
now apply inj_eq, Nat.div_mod.
Qed.
Lemma mod_Zmod (n m: nat): m <> O ->
Z.of_nat (n mod m) = (Z.of_nat n) mod (Z.of_nat m).
Proof.
intros.
apply (Zmod_unique _ _ (Z.of_nat n / Z.of_nat m)).
split. auto with zarith.
now apply inj_lt, Nat.mod_upper_bound.
rewrite <- div_Zdiv, <- Nat2Z.inj_mul, <- Nat2Z.inj_add by trivial.
now apply inj_eq, Nat.div_mod.
Qed.
|
`timescale 1 ps / 1 ps
module onetswitch_top(
inout [14:0]DDR_addr,
inout [2:0]DDR_ba,
inout DDR_cas_n,
inout DDR_ck_n,
inout DDR_ck_p,
inout DDR_cke,
inout DDR_cs_n,
inout [3:0]DDR_dm,
inout [31:0]DDR_dq,
inout [3:0]DDR_dqs_n,
inout [3:0]DDR_dqs_p,
inout DDR_odt,
inout DDR_ras_n,
inout DDR_reset_n,
inout DDR_we_n,
inout FIXED_IO_ddr_vrn,
inout FIXED_IO_ddr_vrp,
inout [53:0]FIXED_IO_mio,
inout FIXED_IO_ps_clk,
inout FIXED_IO_ps_porb,
inout FIXED_IO_ps_srstb,
output phy_rst_n_0,
inout mdio_0_io,
output mdio_0_mdc,
inout mdio_1_io,
output mdio_1_mdc,
inout mdio_2_io,
output mdio_2_mdc,
inout mdio_3_io,
output mdio_3_mdc,
input [3:0]rgmii_0_rd,
input rgmii_0_rx_ctl,
input rgmii_0_rxc,
output [3:0]rgmii_0_td,
output rgmii_0_tx_ctl,
output rgmii_0_txc,
input [3:0]rgmii_1_rd,
input rgmii_1_rx_ctl,
input rgmii_1_rxc,
output [3:0]rgmii_1_td,
output rgmii_1_tx_ctl,
output rgmii_1_txc,
input [3:0]rgmii_2_rd,
input rgmii_2_rx_ctl,
input rgmii_2_rxc,
output [3:0]rgmii_2_td,
output rgmii_2_tx_ctl,
output rgmii_2_txc,
input [3:0]rgmii_3_rd,
input rgmii_3_rx_ctl,
input rgmii_3_rxc,
output [3:0]rgmii_3_td,
output rgmii_3_tx_ctl,
output rgmii_3_txc,
output [1:0] pl_led,
output [1:0] pl_pmod
);
wire bd_fclk0_125m ;
wire bd_fclk1_75m ;
wire bd_fclk2_200m ;
reg [23:0] cnt_0;
reg [23:0] cnt_1;
reg [23:0] cnt_2;
reg [23:0] cnt_3;
always @(posedge bd_fclk0_125m) begin
cnt_0 <= cnt_0 + 1'b1;
end
always @(posedge bd_fclk1_75m) begin
cnt_1 <= cnt_1 + 1'b1;
end
always @(posedge bd_fclk2_200m) begin
cnt_2 <= cnt_2 + 1'b1;
end
always @(posedge bd_fclk2_200m) begin
cnt_3 <= cnt_3 + 1'b1;
end
assign pl_led[0] = cnt_0[23];
assign pl_led[1] = cnt_1[23];
assign pl_pmod[0] = cnt_2[23];
assign pl_pmod[1] = cnt_3[23];
onets_bd_wrapper i_onets_bd_wrapper(
.DDR_addr(DDR_addr),
.DDR_ba(DDR_ba),
.DDR_cas_n(DDR_cas_n),
.DDR_ck_n(DDR_ck_n),
.DDR_ck_p(DDR_ck_p),
.DDR_cke(DDR_cke),
.DDR_cs_n(DDR_cs_n),
.DDR_dm(DDR_dm),
.DDR_dq(DDR_dq),
.DDR_dqs_n(DDR_dqs_n),
.DDR_dqs_p(DDR_dqs_p),
.DDR_odt(DDR_odt),
.DDR_ras_n(DDR_ras_n),
.DDR_reset_n(DDR_reset_n),
.DDR_we_n(DDR_we_n),
.FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
.FIXED_IO_mio(FIXED_IO_mio),
.FIXED_IO_ps_clk(FIXED_IO_ps_clk),
.FIXED_IO_ps_porb(FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb(FIXED_IO_ps_srstb),
.mdio_0_io (mdio_0_io ),
.mdio_0_mdc (mdio_0_mdc ),
.mdio_1_io (mdio_1_io ),
.mdio_1_mdc (mdio_1_mdc ),
.mdio_2_io (mdio_2_io ),
.mdio_2_mdc (mdio_2_mdc ),
.mdio_3_io (mdio_3_io ),
.mdio_3_mdc (mdio_3_mdc ),
.phy_rst_n_0 (phy_rst_n_0),
.phy_rst_n_1 (),
.phy_rst_n_2 (),
.phy_rst_n_3 (),
.rgmii_0_rd (rgmii_0_rd ),
.rgmii_0_rx_ctl (rgmii_0_rx_ctl ),
.rgmii_0_rxc (rgmii_0_rxc ),
.rgmii_0_td (rgmii_0_td ),
.rgmii_0_tx_ctl (rgmii_0_tx_ctl ),
.rgmii_0_txc (rgmii_0_txc ),
.rgmii_1_rd (rgmii_1_rd ),
.rgmii_1_rx_ctl (rgmii_1_rx_ctl ),
.rgmii_1_rxc (rgmii_1_rxc ),
.rgmii_1_td (rgmii_1_td ),
.rgmii_1_tx_ctl (rgmii_1_tx_ctl ),
.rgmii_1_txc (rgmii_1_txc ),
.rgmii_2_rd (rgmii_2_rd ),
.rgmii_2_rx_ctl (rgmii_2_rx_ctl ),
.rgmii_2_rxc (rgmii_2_rxc ),
.rgmii_2_td (rgmii_2_td ),
.rgmii_2_tx_ctl (rgmii_2_tx_ctl ),
.rgmii_2_txc (rgmii_2_txc ),
.rgmii_3_rd (rgmii_3_rd ),
.rgmii_3_rx_ctl (rgmii_3_rx_ctl ),
.rgmii_3_rxc (rgmii_3_rxc ),
.rgmii_3_td (rgmii_3_td ),
.rgmii_3_tx_ctl (rgmii_3_tx_ctl ),
.rgmii_3_txc (rgmii_3_txc ),
.bd_fclk0_125m ( bd_fclk0_125m ),
.bd_fclk1_75m ( bd_fclk1_75m ),
.bd_fclk2_200m ( bd_fclk2_200m ),
.ext_rst (1'b0)
);
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__OR4BB_TB_V
`define SKY130_FD_SC_MS__OR4BB_TB_V
/**
* or4bb: 4-input OR, first two inputs inverted.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__or4bb.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C_N;
reg D_N;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C_N = 1'bX;
D_N = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C_N = 1'b0;
#80 D_N = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A = 1'b1;
#200 B = 1'b1;
#220 C_N = 1'b1;
#240 D_N = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A = 1'b0;
#360 B = 1'b0;
#380 C_N = 1'b0;
#400 D_N = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 D_N = 1'b1;
#600 C_N = 1'b1;
#620 B = 1'b1;
#640 A = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 D_N = 1'bx;
#760 C_N = 1'bx;
#780 B = 1'bx;
#800 A = 1'bx;
end
sky130_fd_sc_ms__or4bb dut (.A(A), .B(B), .C_N(C_N), .D_N(D_N), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__OR4BB_TB_V
|
//----------------------------------------------------------------------------
//-- Prueba de tranmision 2. Se transmite el caracter "A" cada 100ms
//------------------------------------------
//-- (C) BQ. September 2015. Written by Juan Gonzalez (Obijuan)
//-- GPL license
//--
//----------------------------------------------------------------------------
//-- Comprobado su funcionamiento a todas las velocidades estandares:
//-- 300, 600, 1200, 2400, 9600, 19200, 57600, 115200
//----------------------------------------------------------------------------
//-- Although this transmitter has been written from the scratch, it has been
//-- inspired by the one developed in the swapforth proyect by James Bowman
//--
//-- https://github.com/jamesbowman/swapforth
//--
//----------------------------------------------------------------------------
`default_nettype none
`include "baudgen.vh"
`include "divider.vh"
//--- Modulo que envia un caracter cuando load esta a 1
//--- La salida tx ESTA REGISTRADA
module fsmtx2 (input wire clk, //-- Reloj del sistema (12MHz en ICEstick)
output reg tx //-- Salida de datos serie (hacia el PC)
);
//-- Parametro: velocidad de transmision
parameter BAUD = `B115200;
//-- Caracter a enviar
parameter CAR = "A";
//- Tiempo de envio
parameter DELAY = `T_100ms;
//-- Registro de 10 bits para almacenar la trama a enviar:
//-- 1 bit start + 8 bits datos + 1 bit stop
reg [9:0] shifter;
wire start;
//-- Señal de start registrada
reg start_r;
//-- Reloj para la transmision
wire clk_baud;
//-- Reset
reg rstn = 0;
//-- Bitcounter
reg [3:0] bitc;
//--------- Microordenes
wire load; //-- Carga del registro de desplazamiento. Puesta a 0 del
//-- contador de bits
wire baud_en; //-- Habilitar el generador de baudios para la transmision
//-------------------------------------
//-- RUTA DE DATOS
//-------------------------------------
//-- Registrar la entrada start
//-- (para cumplir con las reglas de diseño sincrono)
always @(posedge clk)
start_r <= start;
//-- Registro de desplazamiento, con carga paralela
//-- Cuando load_r es 0, se carga la trama
//-- Cuando load_r es 1 y el reloj de baudios esta a 1 se desplaza hacia
//-- la derecha, enviando el siguiente bit
//-- Se introducen '1's por la izquierda
always @(posedge clk)
//-- Reset
if (rstn == 0)
shifter <= 10'b11_1111_1111;
//-- Modo carga
else if (load == 1)
shifter <= {CAR,2'b01};
//-- Modo desplazamiento
else if (load == 0 && clk_baud == 1)
shifter <= {1'b1, shifter[9:1]};
always @(posedge clk)
if (load == 1)
bitc <= 0;
else if (load == 0 && clk_baud == 1)
bitc <= bitc + 1;
//-- Sacar por tx el bit menos significativo del registros de desplazamiento
//-- Cuando estamos en modo carga (load_r == 0), se saca siempre un 1 para
//-- que la linea este siempre a un estado de reposo. De esta forma en el
//-- inicio tx esta en reposo, aunque el valor del registro de desplazamiento
//-- sea desconocido
//-- ES UNA SALIDA REGISTRADA, puesto que tx se conecta a un bus sincrono
//-- y hay que evitar que salgan pulsos espureos (glitches)
always @(posedge clk)
tx <= shifter[0];
//-- Divisor para obtener el reloj de transmision
baudgen #(BAUD)
BAUD0 (
.clk(clk),
.clk_ena(baud_en),
.clk_out(clk_baud)
);
//---------------------------
//-- Temporizador
//---------------------------
dividerp1 #(.M(DELAY))
DIV0 ( .clk(clk),
.clk_out(start)
);
//------------------------------
//-- CONTROLADOR
//------------------------------
//-- Estados del automata finito del controlador
localparam IDLE = 0;
localparam START = 1;
localparam TRANS = 2;
//-- Estados del autómata del controlador
reg [1:0] state;
//-- Transiciones entre los estados
always @(posedge clk)
//-- Reset del automata. Al estado inicial
if (rstn == 0)
state <= IDLE;
else
//-- Transiciones a los siguientes estados
case (state)
//-- Estado de reposo. Se sale cuando la señal
//-- de start se pone a 1
IDLE:
if (start_r == 1)
state <= START;
else
state <= IDLE;
//-- Estado de comienzo. Prepararse para empezar
//-- a transmitir. Duracion: 1 ciclo de reloj
START:
state <= TRANS;
//-- Transmitiendo. Se esta en este estado hasta
//-- que se hayan transmitido todos los bits pendientes
TRANS:
if (bitc == 11)
state <= IDLE;
else
state <= TRANS;
//-- Por defecto. NO USADO. Puesto para
//-- cubrir todos los casos y que no se generen latches
default:
state <= IDLE;
endcase
//-- Generacion de las microordenes
assign load = (state == START) ? 1 : 0;
assign baud_en = (state == IDLE) ? 0 : 1;
//-- Inicializador
always @(posedge clk)
rstn <= 1;
endmodule
|
//-----------------------------------------------------------------------------
//-- Reproductor de melodias almacenadas en memoria rom
//-- Los 5 bits menos significativos de la nota se sacan por los leds
//-----------------------------------------------------------------------------
//-- (C) BQ. October 2015. Written by Juan Gonzalez
//-----------------------------------------------------------------------------
//-- GPL license
//-----------------------------------------------------------------------------
//-- Incluir las constantes del modulo del divisor
`include "divider.vh"
//-- Parameteros:
//-- clk: Reloj de entrada de la placa iCEstick
//-- ch_out: Canal de salida
module romnotes(input wire clk,
output wire [4:0] leds,
output wire ch_out);
//-- Parametros
//-- Duracion de las notas
parameter DUR = `T_200ms;
//-- Fichero con las notas para cargar en la rom
parameter ROMFILE = "imperial.list";
//-- Tamaño del bus de direcciones de la rom
parameter AW = 6;
//-- Tamaño de las notas
parameter DW = 16;
//-- Cables de salida de los canales
wire ch0, ch1, ch2;
//-- Selección del canal del multiplexor
reg [AW-1: 0] addr = 0;
//-- Reloj con la duracion de la nota
wire clk_dur;
reg rstn = 0;
wire [DW-1: 0] note;
//-- Instanciar la memoria rom
genrom
#( .ROMFILE(ROMFILE),
.AW(AW),
.DW(DW))
ROM (
.clk(clk),
.addr(addr),
.data(note)
);
//-- Generador de notas
notegen
CH0 (
.clk(clk),
.rstn(rstn),
.note(note),
.clk_out(ch_out)
);
//-- Sacar los 5 bits menos significativos de la nota por los leds
assign leds = note[4:0];
//-- Inicializador
always @(posedge clk)
rstn <= 1;
//-- Contador para seleccion de nota
always @(posedge clk)
if (clk_dur)
addr <= addr + 1;
//-- Divisor para marcar la duración de cada nota
dividerp1 #(DUR)
TIMER0 (
.clk(clk),
.clk_out(clk_dur)
);
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sctag_tagdp_ctl.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
//%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
// Description:
// This module contains the control required for detecting
// a parity error in a tag read.
//%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
`include "iop.h"
`include "sctag.h"
module sctag_tagdp_ctl( /*AUTOARG*/
// Outputs
triad0_muxsel_c3, triad1_muxsel_c3, triad2_muxsel_c3,
triad3_muxsel_c3, tag_quad_muxsel_c3, bist_vuad_wr_data,
bist_vuad_index, bist_vuad_vd, bist_vuad_write,
vuad_dp_diag_data_c7_buf, tagdp_mbctl_par_err_c3,
tagdp_tagctl_par_err_c3, tagdp_arbctl_par_err_c3, tag_error_c8,
so, lru_way_sel_c3, evict_c3, invalid_evict_c3,
// Inputs
vuad_dp_valid_c2, tag_parity_c2, tag_way_sel_c2,
vuad_tagdp_sel_c2_d1, bist_way_px, bist_enable_px,
arbdp_diag_wr_way_c2, arbctl_tecc_way_c2, arbctl_normal_tagacc_c2,
arbctl_tagdp_tecc_c2, arbctl_tagdp_perr_vld_c2, mbctl_hit_c3,
l2_dir_map_on, arbctl_l2tag_vld_c4, rst_tri_en, mbist_write_data,
mbist_l2v_index, mbist_l2v_vd, mbist_l2v_write,
vuad_dp_diag_data_c7, rclk, si, se, grst_l, arst_l, dbginit_l,
vuad_dp_used_c2, vuad_dp_alloc_c2, arbctl_evict_vld_c2
);
input [11:0] vuad_dp_valid_c2;
input [11:0] tag_parity_c2; // from tagdp.needs to be mapped
// @ the top level.
input [11:0] tag_way_sel_c2; // This can be a delayed version of the way selects.POST_3.0
input vuad_tagdp_sel_c2_d1; //POST_3.0
// Adding all the mux control logic for tagdp and tagl_dp into
// this block.
// All bist inputs come from a PX2 flop in the bist controller.
input [3:0] bist_way_px; // from tagbist
input bist_enable_px; // from tagbist
// calculations.
output [2:0] triad0_muxsel_c3;
output [2:0] triad1_muxsel_c3;
output [2:0] triad2_muxsel_c3;
output [2:0] triad3_muxsel_c3;
output [3:0] tag_quad_muxsel_c3 ; // to tagdp
input [3:0] arbdp_diag_wr_way_c2 ; // Wr or read way for tag Diagnostic Accesses.
input [3:0] arbctl_tecc_way_c2;
input arbctl_normal_tagacc_c2 ; // indicates that lru way from vuad is used for
// tag selection
input arbctl_tagdp_tecc_c2; // NEW_PIN . sel tecc way
input arbctl_tagdp_perr_vld_c2; // POST_2.0 PIN
input mbctl_hit_c3; // POST_2.0 PIN
input l2_dir_map_on; // NEW_PIN from csr
input arbctl_l2tag_vld_c4; // from tagctl
input rst_tri_en;
input [7:0] mbist_write_data; // POST_4.2 signals
output [7:0] bist_vuad_wr_data ; // POST_4.2 signals.
input [9:0] mbist_l2v_index; // POST_4.2 signals
input mbist_l2v_vd; // POST_4.2 signals
input mbist_l2v_write; // POST_4.2 signals
output [9:0] bist_vuad_index; // POST_4.2 signals
output bist_vuad_vd; // POST_4.2 signals
output bist_vuad_write; // POST_4.2 signals
input [25:0] vuad_dp_diag_data_c7 ; // POST_4.2 signals
output [25:0] vuad_dp_diag_data_c7_buf; // POST_4.2 signals
input rclk;
input si, se;
input grst_l;
input arst_l;
input dbginit_l;
output tagdp_mbctl_par_err_c3 ; // can be made a C3 signal.
output tagdp_tagctl_par_err_c3; // used to gate off eviction way
output tagdp_arbctl_par_err_c3; // used to gate off an eviction signal
output tag_error_c8; // to fbctl and csr.
output so;
input [11:0] vuad_dp_used_c2 ;
input [11:0] vuad_dp_alloc_c2 ;
output [11:0] lru_way_sel_c3;
// to tagdp
// All outputs are xmitted in C2 and used in C3.
// Buffer the following so that they can transmit to tagdp.
input arbctl_evict_vld_c2;
output evict_c3;
output invalid_evict_c3;
wire par_err_c2, par_err_c3;
wire tagdp_par_err_c4, tagdp_par_err_c5;
wire tag_error_c6, tag_error_c7 ;
wire [2:0] lru_triad0_muxsel_c2 ;
wire [2:0] lru_triad1_muxsel_c2 ;
wire [2:0] lru_triad2_muxsel_c2 ;
wire [2:0] lru_triad3_muxsel_c2 ;
wire [3:0] diag_wr_way_c3;
wire [3:0] diag_wr_way_c4;
wire [3:0] dec_lower_tag_way_c2;
wire [3:0] dec_high_tag_way_c2;
wire [3:0] bist_way_c1;
wire [3:0] bist_way_c2;
wire bist_enable_c1;
wire bist_enable_c2;
wire [3:0] lru_quad_muxsel_c2;
wire [3:0] lru_quad_muxsel_c3;
wire [2:0] tag_triad0_muxsel_c2 ;
wire [2:0] tag_triad1_muxsel_c2 ;
wire [2:0] tag_triad2_muxsel_c2 ;
wire [2:0] tag_triad3_muxsel_c2 ;
wire [2:0] dir_triad0_way_c2, dir_triad1_way_c2 ;
wire [2:0] dir_triad2_way_c2, dir_triad3_way_c2 ;
wire [2:0] tag_triad0_muxsel_c3;
wire [2:0] tag_triad1_muxsel_c3;
wire [2:0] tag_triad2_muxsel_c3;
wire [2:0] tag_triad3_muxsel_c3;
wire [3:0] dir_quad_way_c2;
wire [3:0] dir_quad_way_c3;
wire sel_bist_way_c2 ;
wire sel_diag_way_c4 ;
wire sel_tecc_way_c2 ;
wire [1:0] enc_high_tag_way_c2;
wire [1:0] enc_lower_tag_way_c2;
wire use_dec_sel_c2;
wire use_dec_sel_c3;
wire l2_dir_map_on_d1;
wire sel_dir_way_c2; // pick way indicated by addr<21:18>
wire [2:0] muxsel_triad0_way_c2 ;
wire [2:0] muxsel_triad1_way_c2 ;
wire [2:0] muxsel_triad2_way_c2 ;
wire [2:0] muxsel_triad3_way_c2 ;
wire nondep_tagdp_par_err_c3;
wire evict_vld_c3_1, evict_vld_c3_2;
wire evict_c3_1;
wire dbb_rst_l;
wire par_err_c3_2;
wire [11:0] lru_way_sel_c3_1;
wire [11:0] valid_c3;
// ----------------------\/ POST 4.2 repeater addition \/-------------------------
assign bist_vuad_wr_data = mbist_write_data ;
assign bist_vuad_write = mbist_l2v_write ;
assign bist_vuad_vd = mbist_l2v_vd ;
assign bist_vuad_index = mbist_l2v_index ;
assign vuad_dp_diag_data_c7_buf = vuad_dp_diag_data_c7 ;
// ----------------------\/ POST 4.2 repeater addition \/-------------------------
///////////////////////////////////////////////////////////////////
// Reset flop
///////////////////////////////////////////////////////////////////
dffrl_async #(1) reset_flop (.q(dbb_rst_l),
.clk(rclk),
.rst_l(arst_l),
.din(grst_l),
.se(se), .si(), .so());
dff_s #(1) ff_evict_c3_1
(.q (evict_vld_c3_1),
.din (arbctl_evict_vld_c2),
.clk (rclk),
.se(se), .si (), .so ()
) ;
dff_s #(1) ff_evict_c3_2
(.q (evict_vld_c3_2),
.din (arbctl_evict_vld_c2),
.clk (rclk),
.se(se), .si (), .so ()
) ;
assign evict_c3 = evict_vld_c3_1 & ~par_err_c3 ;
assign evict_c3_1 = evict_vld_c3_2 & ~par_err_c3_2 ;
// evict qualification is performed in arbctl.
assign invalid_evict_c3 = |(lru_way_sel_c3_1 & ~valid_c3) ;
////////////////////////////////////////////
// The tag compare operation is a 27 bit
// compare. The overall Parity bit is
// not part of the compare.
//
// An error in any bit of the tag will cause
// the lkup operation to fail except for
// that in the overall parity bit.
// In case of an error in P, we need to
// turn off signalling a parity error.
//
// That is done using the not_hit_way_c2 signal
//assign tagdp_par_err_c2 = arbctl_tagdp_perr_vld_c2 & // inst vld from arbctl
// (|( tag_parity_c2 & not_hit_way_c2 )) ;
////////////////////////////////////////////
////////////////////////////////////////////
// An eviction is turned off if
// par_err_c3 is asserted. This is becuase
// the eviction could very well pick a way
// with a corrupted tag and this would end
// up in memory corruption.
////////////////////////////////////////////
// the following signal is used for reporting purposes only
assign par_err_c2 = arbctl_tagdp_perr_vld_c2 & |(tag_parity_c2 & vuad_dp_valid_c2);
// the following signals are used for control in the pipeline.
// In mbctl, tagctl, vuad, arbctl this par err signal is used
// for different purposes. In all cases it is used only for
// an EVICT instruction or for a miss.
// In mbctl, it is used in the insertion expression provided
// the instruction also misses the $ and FB.
dff_s #(1) ff_tagdp_par_err_c3 (.din(par_err_c2), .clk(rclk),
.q(par_err_c3), .se(se), .si(), .so());
dff_s #(1) ff_tagdp_par_err_c3_2 (.din(par_err_c2), .clk(rclk),
.q(par_err_c3_2), .se(se), .si(), .so());
dff_s #(1) ff_tagdp_mbctl_par_err_c3 (.din(par_err_c2), .clk(rclk),
.q(tagdp_mbctl_par_err_c3), .se(se), .si(), .so());
dff_s #(1) ff_tagdp_tagctl_par_err_c3 (.din(par_err_c2), .clk(rclk),
.q(tagdp_tagctl_par_err_c3), .se(se), .si(), .so());
dff_s #(1) ff_tagdp_arbctl_par_err_c3 (.din(par_err_c2), .clk(rclk),
.q(tagdp_arbctl_par_err_c3), .se(se), .si(), .so());
// In all the destination blocks, vuad, tagctl, mbctl and arbctl, this
// par_err signal is used only for a non-dep instruction.
// Dependents will not report a parity error at all.
// Hovewer, reporting is enabled for all hit cases that encounter a
// tag corruption.
assign nondep_tagdp_par_err_c3 = par_err_c3 & ~mbctl_hit_c3;
dff_s #(1) ff_tagdp_par_err_c4 (.din(nondep_tagdp_par_err_c3), .clk(rclk),
.q(tagdp_par_err_c4), .se(se), .si(), .so());
dff_s #(1) ff_tagdp_par_err_c5 (.din(tagdp_par_err_c4), .clk(rclk),
.q(tagdp_par_err_c5), .se(se), .si(), .so());
dff_s #(1) ff_tag_error_c6 (.din(tagdp_par_err_c5), .clk(rclk),
.q(tag_error_c6), .se(se), .si(), .so());
dff_s #(1) ff_tag_error_c7 (.din(tag_error_c6), .clk(rclk),
.q(tag_error_c7), .se(se), .si(), .so());
dff_s #(1) ff_tag_error_c8 (.din(tag_error_c7), .clk(rclk),
.q(tag_error_c8), .se(se), .si(), .so());
/////////////////////////////////////////////
// Mux select generation to read
// out the evicted tag &
// 16:1 muxing of the tag read
//
// In C2 we generate the muxselects for all the
// 4 triads.
// These mux selects are generated for the following
// 2 categories of accesses.
// I)Normal accesses: sels generated by vuad_dp
// II) Direct Accesses: Diagnostic/direct mapped, BIST, tecc
//
// In C3 we generate the mux selects for the 4-1 mux in
// this block.
/////////////////////////////////////////////
dff_s #(1) ff_l2_dir_map_on_d1 (.din(l2_dir_map_on), .clk(rclk),
.q(l2_dir_map_on_d1), .se(se), .si(), .so());
dff_s #(4) ff_diag_way_c3 (.din(arbdp_diag_wr_way_c2[3:0]), .clk(rclk),
.q(diag_wr_way_c3[3:0]), .se(se), .si(), .so());
dff_s #(4) ff_diag_way_c4 (.din(diag_wr_way_c3[3:0]), .clk(rclk),
.q(diag_wr_way_c4[3:0]), .se(se), .si(), .so());
dff_s #(4) ff_lru_quad_muxsel_c2 (.din(lru_quad_muxsel_c2[3:0]), .clk(rclk),
.q(lru_quad_muxsel_c3[3:0]), .se(se), .si(), .so());
dff_s #(4) ff_bist_way_c1 (.din(bist_way_px[3:0]), .clk(rclk),
.q(bist_way_c1[3:0]), .se(se), .si(), .so());
dff_s #(4) ff_bist_way_c2 (.din(bist_way_c1[3:0]), .clk(rclk),
.q(bist_way_c2[3:0]), .se(se), .si(), .so());
dff_s #(1) ff_bist_enable_c1 (.din(bist_enable_px), .clk(rclk),
.q(bist_enable_c1), .se(se), .si(), .so());
dff_s #(1) ff_bist_enable_c2 (.din(bist_enable_c1), .clk(rclk),
.q(bist_enable_c2), .se(se), .si(), .so());
assign sel_bist_way_c2 = bist_enable_c2 ;
assign sel_diag_way_c4 = ~bist_enable_c2 & arbctl_l2tag_vld_c4;
assign sel_tecc_way_c2 = ~bist_enable_c2 & ~arbctl_l2tag_vld_c4 &
arbctl_tagdp_tecc_c2 ;
assign sel_dir_way_c2 = ~arbctl_tagdp_tecc_c2 & ~bist_enable_c2 &
~arbctl_l2tag_vld_c4 ;
mux4ds #(2) mux_way_low ( .dout (enc_lower_tag_way_c2[1:0]),
.in0(bist_way_c2[1:0]), // bist way c2
.in1(diag_wr_way_c4[1:0]), // diag way c4
.in2(arbctl_tecc_way_c2[1:0]),// tecc way c2( from a counter in arbdec)
.in3(arbdp_diag_wr_way_c2[1:0]),// addr_c2<19:18>
.sel0(sel_bist_way_c2), // bist way sel
.sel1(sel_diag_way_c4), // no bist way sel and diag sel.
.sel2(sel_tecc_way_c2), // tecc way
.sel3(sel_dir_way_c2)); // default is dir mapped way.
assign dec_lower_tag_way_c2[0] =(enc_lower_tag_way_c2 == 2'd0 ) ;
assign dec_lower_tag_way_c2[1] =(enc_lower_tag_way_c2 == 2'd1 ) ;
assign dec_lower_tag_way_c2[2] =(enc_lower_tag_way_c2 == 2'd2 ) ;
assign dec_lower_tag_way_c2[3] =(enc_lower_tag_way_c2 == 2'd3 ) ;
mux4ds #(2) mux_way_high (.dout (enc_high_tag_way_c2[1:0]),
.in0(bist_way_c2[3:2]), // bist way c2
.in1(diag_wr_way_c4[3:2]), // diag way c4
.in2(arbctl_tecc_way_c2[3:2]), // tecc way c2( from a counter in arbdec)
.in3(arbdp_diag_wr_way_c2[3:2]),// addr_c2<21:20>
.sel0(sel_bist_way_c2), // bist way sel
.sel1(sel_diag_way_c4), // no bist way sel and diag sel.
.sel2(sel_tecc_way_c2), // tecc
.sel3(sel_dir_way_c2)); // default is dir mapped way.
assign dec_high_tag_way_c2[0] = (enc_high_tag_way_c2 == 2'd0 ) ;
assign dec_high_tag_way_c2[1] = (enc_high_tag_way_c2 == 2'd1 ) ;
assign dec_high_tag_way_c2[2] = (enc_high_tag_way_c2 == 2'd2 ) ;
assign dec_high_tag_way_c2[3] = (enc_high_tag_way_c2 == 2'd3 ) ;
// Triad0 muxselects
// Tags in Triad0 correspond to way=0,1,2
assign dir_triad0_way_c2[0] = dec_high_tag_way_c2[0] &
dec_lower_tag_way_c2[0] ; // 0000
assign dir_triad0_way_c2[1] = dec_high_tag_way_c2[0] &
dec_lower_tag_way_c2[1] ; // 0001
assign dir_triad0_way_c2[2] = dec_high_tag_way_c2[0] &
dec_lower_tag_way_c2[2] ; // 0010
assign dir_quad_way_c2[0] = |( dir_triad0_way_c2 ) ;
assign muxsel_triad0_way_c2[1:0] = dir_triad0_way_c2[1:0];
assign muxsel_triad0_way_c2[2] = ~( dir_triad0_way_c2[1] |
dir_triad0_way_c2[0] ) ;
// Triad1 muxselects
// Tags in Triad1 correspond to way=3,4 or 12,5 or 13
assign dir_triad1_way_c2[0] = dec_high_tag_way_c2[0] &
dec_lower_tag_way_c2[3] ; // 0011
assign dir_triad1_way_c2[1] = ( dec_high_tag_way_c2[1] |
dec_high_tag_way_c2[3] ) &
dec_lower_tag_way_c2[0] ; // 0100 or 1100
assign dir_triad1_way_c2[2] = ( dec_high_tag_way_c2[1] |
dec_high_tag_way_c2[3] ) &
dec_lower_tag_way_c2[1] ; // 0101 or 1101
assign dir_quad_way_c2[1] = |( dir_triad1_way_c2 ) ;
assign muxsel_triad1_way_c2[1:0] = dir_triad1_way_c2[1:0];
assign muxsel_triad1_way_c2[2] = ~( dir_triad1_way_c2[1] |
dir_triad1_way_c2[0] ) ;
// Triad2 muxselects
// Tags in Triad2 correspond to way=6 or 14,7 or 15,8
assign dir_triad2_way_c2[0] = ( dec_high_tag_way_c2[1] |
dec_high_tag_way_c2[3] ) &
dec_lower_tag_way_c2[2] ; // 0110 or 1110
assign dir_triad2_way_c2[1] = ( dec_high_tag_way_c2[1] |
dec_high_tag_way_c2[3] ) &
dec_lower_tag_way_c2[3] ; // 0111 or 1111
assign dir_triad2_way_c2[2] = dec_high_tag_way_c2[2] &
dec_lower_tag_way_c2[0] ; // 1000
assign dir_quad_way_c2[2] = |( dir_triad2_way_c2 ) ;
assign muxsel_triad2_way_c2[1:0] = dir_triad2_way_c2[1:0];
assign muxsel_triad2_way_c2[2] = ~( dir_triad2_way_c2[1] |
dir_triad2_way_c2[0] ) ;
// Triad3 muxselects
// Tags in Triad3 correspond to way=9, 10, 11
assign dir_triad3_way_c2[0] = dec_high_tag_way_c2[2] &
dec_lower_tag_way_c2[1] ; // 1001
assign dir_triad3_way_c2[1] = dec_high_tag_way_c2[2] &
dec_lower_tag_way_c2[2] ; // 1010
assign dir_triad3_way_c2[2] = dec_high_tag_way_c2[2] &
dec_lower_tag_way_c2[3] ; // 1011
assign dir_quad_way_c2[3] = |( dir_triad3_way_c2 ) ;
assign use_dec_sel_c2 = ( ~arbctl_normal_tagacc_c2 |
bist_enable_c2 |
l2_dir_map_on_d1 ) ;
dff_s #(1) ff_use_dec_sel_c3 (.din(use_dec_sel_c2), .clk(rclk),
.q(use_dec_sel_c3), .se(se), .si(), .so());
assign muxsel_triad3_way_c2[1:0] = dir_triad3_way_c2[1:0];
assign muxsel_triad3_way_c2[2] = ~( dir_triad3_way_c2[1] |
dir_triad3_way_c2[0] ) ;
/////////
// TRIAD0
/////////
// Use a mux flop for the following to reduce the setup on lru_triad0_muxsel_c2
mux2ds #(3) mux_tag_triad0_muxsel_c2 ( .dout (tag_triad0_muxsel_c2[2:0]),
.in0(muxsel_triad0_way_c2[2:0]),
.in1(lru_triad0_muxsel_c2[2:0]),
.sel0(use_dec_sel_c2),
.sel1(~use_dec_sel_c2));
dff_s #(3) ff_tag_triad0_muxsel_c2 (.din(tag_triad0_muxsel_c2[2:0]), .clk(rclk),
.q(tag_triad0_muxsel_c3[2:0]), .se(se), .si(), .so());
// rst_tri_en required for mux ex
assign triad0_muxsel_c3[2:1] = tag_triad0_muxsel_c3[2:1] & ~{2{rst_tri_en}} ;
assign triad0_muxsel_c3[0] = tag_triad0_muxsel_c3[0] | rst_tri_en ;
/////////
// TRIAD1
/////////
// Use a mux flop for the following to reduce the setup on lru_triad1_muxsel_c2
mux2ds #(3) mux_tag_triad1_muxsel_c2 ( .dout (tag_triad1_muxsel_c2[2:0]),
.in0(muxsel_triad1_way_c2[2:0]),
.in1(lru_triad1_muxsel_c2[2:0]),
.sel0(use_dec_sel_c2),
.sel1(~use_dec_sel_c2));
dff_s #(3) ff_tag_triad1_muxsel_c2 (.din(tag_triad1_muxsel_c2[2:0]), .clk(rclk),
.q(tag_triad1_muxsel_c3[2:0]), .se(se), .si(), .so());
// rst_tri_en required for mux ex
assign triad1_muxsel_c3[2:1] = tag_triad1_muxsel_c3[2:1] & ~{2{rst_tri_en}} ;
assign triad1_muxsel_c3[0] = tag_triad1_muxsel_c3[0] | rst_tri_en ;
/////////
// TRIAD2
/////////
// Use a mux flop for the following to reduce the setup on lru_triad2_muxsel_c2
mux2ds #(3) mux_tag_triad2_muxsel_c2 ( .dout (tag_triad2_muxsel_c2[2:0]),
.in0(muxsel_triad2_way_c2[2:0]),
.in1(lru_triad2_muxsel_c2[2:0]),
.sel0(use_dec_sel_c2),
.sel1(~use_dec_sel_c2));
dff_s #(3) ff_tag_triad2_muxsel_c2 (.din(tag_triad2_muxsel_c2[2:0]), .clk(rclk),
.q(tag_triad2_muxsel_c3[2:0]), .se(se), .si(), .so());
// rst_tri_en required for mux ex
assign triad2_muxsel_c3[2:1] = tag_triad2_muxsel_c3[2:1] & ~{2{rst_tri_en}} ;
assign triad2_muxsel_c3[0] = tag_triad2_muxsel_c3[0] | rst_tri_en ;
/////////
// TRIAD3
/////////
// Use a mux flop for the following to reduce the setup on lru_triad3_muxsel_c2
mux2ds #(3) mux_tag_triad3_muxsel_c2 ( .dout (tag_triad3_muxsel_c2[2:0]),
.in0(muxsel_triad3_way_c2[2:0]),
.in1(lru_triad3_muxsel_c2[2:0]),
.sel0(use_dec_sel_c2),
.sel1(~use_dec_sel_c2));
dff_s #(3) ff_tag_triad3_muxsel_c2 (.din(tag_triad3_muxsel_c2[2:0]), .clk(rclk),
.q(tag_triad3_muxsel_c3[2:0]), .se(se), .si(), .so());
// rst_tri_en required for mux ex
assign triad3_muxsel_c3[2:1] = tag_triad3_muxsel_c3[2:1] & ~{2{rst_tri_en}} ;
assign triad3_muxsel_c3[0] = tag_triad3_muxsel_c3[0] | rst_tri_en ;
dff_s #(4) ff_dir_quad_way_c3 (.din(dir_quad_way_c2[3:0]), .clk(rclk),
.q(dir_quad_way_c3[3:0]), .se(se), .si(), .so());
/////////
// QUAD
/////////
// Use the C5 select from the diagnostic read/BIST or the C3 select from Lru.
assign tag_quad_muxsel_c3[0] = (( dir_quad_way_c3[0] & use_dec_sel_c3 )
| ( ~use_dec_sel_c3 & lru_quad_muxsel_c3[0] ))
& ~rst_tri_en ;
assign tag_quad_muxsel_c3[1] = (( dir_quad_way_c3[1] & use_dec_sel_c3 )
| ( ~use_dec_sel_c3 & lru_quad_muxsel_c3[1] ))
& ~rst_tri_en ;
assign tag_quad_muxsel_c3[2] = (( dir_quad_way_c3[2] & use_dec_sel_c3 )
| ( ~use_dec_sel_c3 & lru_quad_muxsel_c3[2] ))
& ~rst_tri_en ;
assign tag_quad_muxsel_c3[3] = (( dir_quad_way_c3[3] & use_dec_sel_c3 )
| ( ~use_dec_sel_c3 & lru_quad_muxsel_c3[3] ))
| rst_tri_en ;
//*****************************************************************************
// LRU state flop.
// * initialized to 1 on reset.
// * left shifted ( rotate) on every eviction.
// * else maintains its state.
//*****************************************************************************
wire lshift_lru_triad0;
wire no_lshift_lru_triad0;
wire [2:0] lru_state_lshift_triad0;
wire [2:0] lru_state_triad0 ;
wire [2:0] lru_state_triad0_p ;
wire lshift_lru_triad1;
wire no_lshift_lru_triad1;
wire [2:0] lru_state_lshift_triad1;
wire [2:0] lru_state_triad1 ;
wire [2:0] lru_state_triad1_p ;
wire lshift_lru_triad2;
wire no_lshift_lru_triad2;
wire [2:0] lru_state_lshift_triad2;
wire [2:0] lru_state_triad2 ;
wire [2:0] lru_state_triad2_p ;
wire lshift_lru_triad3;
wire no_lshift_lru_triad3;
wire [2:0] lru_state_lshift_triad3;
wire [2:0] lru_state_triad3 ;
wire [2:0] lru_state_triad3_p ;
wire pick_triad0;
wire pick_triad1;
wire pick_triad2;
wire pick_triad3;
wire [11:0] vec_unvuad_dp_used_c2;
wire [11:0] vec_unvuad_dp_alloc_c2;
wire sel_unvuad_dp_used_c2;
//wire vuad_dp_way_avail_c2;
wire vec_unalloc0to2_c2;
wire vec_unalloc3to5_c2;
wire vec_unalloc6to8_c2;
wire vec_unalloc9to11_c2;
wire vec_unused0to2_c2;
wire vec_unused3to5_c2;
wire vec_unused6to8_c2;
wire vec_unused9to11_c2;
wire [3:0] used_lru_quad_c2;
wire [2:0] used_lru_triad0_c2;
wire [2:0] used_lru_triad1_c2;
wire [2:0] used_lru_triad2_c2;
wire [2:0] used_lru_triad3_c2;
wire [3:0] alloc_lru_quad_c2;
wire [2:0] alloc_lru_triad0_c2;
wire [2:0] alloc_lru_triad1_c2;
wire [2:0] alloc_lru_triad2_c2;
wire [2:0] alloc_lru_triad3_c2;
wire [2:0] used_triad0_tagsel_c2;
wire [2:0] alloc_triad0_tagsel_c2;
wire [2:0] lru_triad0_tagsel_c2;
wire [2:0] used_triad1_tagsel_c2;
wire [2:0] alloc_triad1_tagsel_c2;
wire [2:0] lru_triad1_tagsel_c2;
wire [2:0] used_triad2_tagsel_c2;
wire [2:0] alloc_triad2_tagsel_c2;
wire [2:0] lru_triad2_tagsel_c2;
wire [2:0] used_triad3_tagsel_c2;
wire [2:0] alloc_triad3_tagsel_c2;
wire [2:0] lru_triad3_tagsel_c2;
wire [3:0] used_quad_sel_c2;
wire [3:0] alloc_quad_sel_c2;
wire [3:0] lru_quad_sel_c2;
wire [11:0] lru_way_sel_c2;
wire lshift_lru;
wire no_lshift_lru;
wire [3:0] lru_state_lshift;
wire [3:0] lru_state_p;
wire [3:0] lru_state;
wire init_lru_state;
wire [3:0] dec_lo_dir_way_c2;
wire [3:0] dec_hi_dir_way_c2;
wire [11:0] dec_dir_way_c2;
wire [11:0] evict_way_sel_c2;
wire [11:0] spec_alloc_c2, spec_alloc_c3;
wire [11:0] mod_alloc_c2;
////////////////////////////////////////////////////////////////////////////////
// LRU algorithm is used to select a way, out of 16 ways, to be evicted out of
// the L2 Cache. The algorithm used for the way select is not a tru LRU (Least
// Recently Used) algorithm but Round Robin arbitration. Round Robin arbitration
// is done in two stages by dividing 12 ways in 4 triads of 3 ways each
// Triad0[3:0] = Way[2:0],
// Triad1[3:0] = Way[5:3],
// Triad2[3:0] = Way[8:6],
// Triad3[3:0] = Way[11:9].
//
// First Round Robin is done within each quads to select one of the 3 ways
// and then Round Robin is done to select one of the four quads.
// A 4 bit one hot shift register maintains the state of the arbiter. An one
// at the bit location corresponding to a way represents highest priority for
// that way. Everytime an eviction takes place, state register is updated by
// shifting it left by one bit otherwise state of the register does not change.
// State register is used in C2 for the way selection and it is updated in the
// C3. On reset state rtegister is initialized to a state such that way0 has the
// highest priority.
//
// Way selection algorithm depends on the Used and Allocate bit of the VUAD
// array, read during C1, for the way selection. First priority is given to the
// ways that has not been Used and has not been Allocated for the eviction in
// the previous cycle. If there is no Unused and Unallocated way then a way that
// has not been previously Allocated is given preference.
// Note : Invalid bit is not used for the way selection as if a way is Invalid
// then its Used bit will not be set, so checking Invalid bit is
// redundant.
////////////////////////////////////////////////////////////////////////////////
// QUAD ANCHOR
assign init_lru_state = ~dbb_rst_l | ~dbginit_l ;
assign lshift_lru = evict_c3_1 & ~init_lru_state;
assign no_lshift_lru = ~evict_c3_1 & ~init_lru_state ;
assign lru_state_lshift = { lru_state[2:0], lru_state[3] } ;
mux3ds #(4) mux_lru_st (.dout (lru_state_p[3:0]),
.in0(4'b0001),
.in1(lru_state_lshift[3:0]),
.in2(lru_state[3:0]),
.sel0(init_lru_state),
.sel1(lshift_lru),
.sel2(no_lshift_lru));
dff_s #(4) ff_lru_state (.din(lru_state_p[3:0]),
.clk(rclk),
.q(lru_state[3:0]),
.se(se),
.si(),
.so());
// Triad0 ANCHOR
assign lshift_lru_triad0 = evict_c3_1 & pick_triad0 & ~init_lru_state;
assign no_lshift_lru_triad0 = ~( evict_c3_1 & pick_triad0 ) & ~init_lru_state ;
assign lru_state_lshift_triad0 = { lru_state_triad0[1:0], lru_state_triad0[2] } ;
mux3ds #(3) mux_lru_st_triad0 (.dout (lru_state_triad0_p[2:0]),
.in0(3'b001),
.in1(lru_state_lshift_triad0[2:0]),
.in2(lru_state_triad0[2:0]),
.sel0(init_lru_state),
.sel1(lshift_lru_triad0),
.sel2(no_lshift_lru_triad0));
dff_s #(3) ff_lru_state_triad0 (.din(lru_state_triad0_p[2:0]),
.clk(rclk),
.q(lru_state_triad0[2:0]),
.se(se),
.si(),
.so());
// Triad1 ANCHOR
assign lshift_lru_triad1 = evict_c3_1 & pick_triad1 & ~init_lru_state;
assign no_lshift_lru_triad1 = ~( evict_c3_1 & pick_triad1 ) & ~init_lru_state ;
assign lru_state_lshift_triad1 = { lru_state_triad1[1:0], lru_state_triad1[2] } ;
mux3ds #(3) mux_lru_st_triad1 (.dout (lru_state_triad1_p[2:0]),
.in0(3'b001),
.in1(lru_state_lshift_triad1[2:0]),
.in2(lru_state_triad1[2:0]),
.sel0(init_lru_state),
.sel1(lshift_lru_triad1),
.sel2(no_lshift_lru_triad1));
dff_s #(3) ff_lru_state_triad1 (.din(lru_state_triad1_p[2:0]),
.clk(rclk),
.q(lru_state_triad1[2:0]),
.se(se),
.si(),
.so());
// Triad2 ANCHOR
assign lshift_lru_triad2 = evict_c3_1 & pick_triad2 & ~init_lru_state;
assign no_lshift_lru_triad2 = ~( evict_c3_1 & pick_triad2 ) & ~init_lru_state ;
assign lru_state_lshift_triad2 = { lru_state_triad2[1:0], lru_state_triad2[2] } ;
mux3ds #(3) mux_lru_st_triad2 (.dout (lru_state_triad2_p[2:0]),
.in0(3'b001),
.in1(lru_state_lshift_triad2[2:0]),
.in2(lru_state_triad2[2:0]),
.sel0(init_lru_state),
.sel1(lshift_lru_triad2),
.sel2(no_lshift_lru_triad2));
dff_s #(3) ff_lru_state_triad2 (.din(lru_state_triad2_p[2:0]),
.clk(rclk),
.q(lru_state_triad2[2:0]),
.se(se),
.si(),
.so());
// Triad2 ANCHOR
assign lshift_lru_triad3 = evict_c3_1 & pick_triad3 & ~init_lru_state;
assign no_lshift_lru_triad3 = ~( evict_c3_1 & pick_triad3 ) & ~init_lru_state ;
assign lru_state_lshift_triad3 = { lru_state_triad3[1:0], lru_state_triad3[2] } ;
mux3ds #(3) mux_lru_st_triad3 (.dout (lru_state_triad3_p[2:0]),
.in0(3'b001),
.in1(lru_state_lshift_triad3[2:0]),
.in2(lru_state_triad3[2:0]),
.sel0(init_lru_state),
.sel1(lshift_lru_triad3),
.sel2(no_lshift_lru_triad3));
dff_s #(3) ff_lru_state_triad3 (.din(lru_state_triad3_p[2:0]),
.clk(rclk),
.q(lru_state_triad3[2:0]),
.se(se),
.si(),
.so());
//************************************************************************************
// LRU algorithm
// * 3 vectors are computed ( Invalid[15:0], Unused[15:0], Unallocated[15:0] )
// * On vector is selected based on the 3 select bits read out of the array in C1,
// invalid, unused, unallocated
// * A state register is used to decide which quadrant to pick.
// * The same state register picks a way in each of the 4 quadrants.
//************************************************************************************
//
// If an instruction in C2 sets the alloc bit, it needs to be bypassed
// to the instruction that immediately follows it. This is done speculatively
// using the spec_alloc_c3 signal if the instruction in C2 is to the same index
// as an instruction in C3.
assign spec_alloc_c2 = ( tag_way_sel_c2 & vuad_dp_valid_c2 ) ;
dff_s #(12) ff_spec_alloc_c3 (.din(spec_alloc_c2[11:0]),
.clk(rclk), .q(spec_alloc_c3[11:0]),
.se(se), .si(), .so());
assign mod_alloc_c2 = ( vuad_dp_alloc_c2 |
( spec_alloc_c3 & {12{vuad_tagdp_sel_c2_d1}} ) );
// 2-3 gates.
assign vec_unvuad_dp_used_c2 = ~vuad_dp_used_c2 & ~mod_alloc_c2 ;
assign vec_unvuad_dp_alloc_c2 = ~mod_alloc_c2 ;
assign sel_unvuad_dp_used_c2 = |( vec_unvuad_dp_used_c2) ; // WAY lock will be ORED to this
// 2-3 gates.
assign vec_unused0to2_c2 = |(vec_unvuad_dp_used_c2[2:0]);
assign vec_unused3to5_c2 = |(vec_unvuad_dp_used_c2[5:3]);
assign vec_unused6to8_c2 = |(vec_unvuad_dp_used_c2[8:6]);
assign vec_unused9to11_c2 = |(vec_unvuad_dp_used_c2[11:9]);
// vec_unallocxtoxc2 is used to select one of the four quads.
assign vec_unalloc0to2_c2 = |(vec_unvuad_dp_alloc_c2[2:0]);
assign vec_unalloc3to5_c2 = |(vec_unvuad_dp_alloc_c2[5:3]);
assign vec_unalloc6to8_c2 = |(vec_unvuad_dp_alloc_c2[8:6]);
assign vec_unalloc9to11_c2 = |(vec_unvuad_dp_alloc_c2[11:9]);
/////////////////////////////
//UNUSED ROUND ROBIN PICK
/////////////////////////////
assign used_lru_quad_c2 = { vec_unused9to11_c2,
vec_unused6to8_c2,
vec_unused3to5_c2,
vec_unused0to2_c2 } ;
assign used_lru_triad0_c2 = vec_unvuad_dp_used_c2[2:0] ;
assign used_lru_triad1_c2 = vec_unvuad_dp_used_c2[5:3] ;
assign used_lru_triad2_c2 = vec_unvuad_dp_used_c2[8:6] ;
assign used_lru_triad3_c2 = vec_unvuad_dp_used_c2[11:9] ;
/////////////////////////////
//UNALLOC ROUND ROBIN PICK
/////////////////////////////
assign alloc_lru_quad_c2 = { vec_unalloc9to11_c2,
vec_unalloc6to8_c2,
vec_unalloc3to5_c2,
vec_unalloc0to2_c2 } ;
assign alloc_lru_triad0_c2 = vec_unvuad_dp_alloc_c2[2:0] ;
assign alloc_lru_triad1_c2 = vec_unvuad_dp_alloc_c2[5:3] ;
assign alloc_lru_triad2_c2 = vec_unvuad_dp_alloc_c2[8:6] ;
assign alloc_lru_triad3_c2 = vec_unvuad_dp_alloc_c2[11:9] ;
/************ LRU way within triad0 ************************/
assign used_triad0_tagsel_c2[0] = used_lru_triad0_c2[0] &
( lru_state_triad0[0] |
( lru_state_triad0[1] & ~( used_lru_triad0_c2[1] |
used_lru_triad0_c2[2] ) ) |
( lru_state_triad0[2] & ~used_lru_triad0_c2[2] ) ) ;
assign used_triad0_tagsel_c2[1] = used_lru_triad0_c2[1] &
( lru_state_triad0[1] |
( lru_state_triad0[2] & ~( used_lru_triad0_c2[2] |
used_lru_triad0_c2[0] )) |
( lru_state_triad0[0] & ~used_lru_triad0_c2[0]) ) ;
assign used_triad0_tagsel_c2[2] = used_lru_triad0_c2[2] &
( lru_state_triad0[2] |
( lru_state_triad0[0] & ~(used_lru_triad0_c2[0] |
used_lru_triad0_c2[1])) |
( lru_state_triad0[1] & ~used_lru_triad0_c2[1] ) ) ;
assign alloc_triad0_tagsel_c2[0] = alloc_lru_triad0_c2[0] &
( lru_state_triad0[0] |
( lru_state_triad0[1] & ~( alloc_lru_triad0_c2[1] |
alloc_lru_triad0_c2[2] ) ) |
( lru_state_triad0[2] & ~alloc_lru_triad0_c2[2] ) ) ;
assign alloc_triad0_tagsel_c2[1] = alloc_lru_triad0_c2[1] &
( lru_state_triad0[1] |
( lru_state_triad0[2] & ~( alloc_lru_triad0_c2[2] |
alloc_lru_triad0_c2[0] )) |
( lru_state_triad0[0] & ~alloc_lru_triad0_c2[0]) ) ;
assign alloc_triad0_tagsel_c2[2] = alloc_lru_triad0_c2[2] &
( lru_state_triad0[2] |
( lru_state_triad0[0] & ~(alloc_lru_triad0_c2[0] |
alloc_lru_triad0_c2[1])) |
( lru_state_triad0[1] & ~alloc_lru_triad0_c2[1] ) ) ;
mux2ds #(3) mux_used_lru_triad0 (.dout (lru_triad0_tagsel_c2[2:0]),
.in0(used_triad0_tagsel_c2[2:0]),
.in1(alloc_triad0_tagsel_c2[2:0]),
.sel0(sel_unvuad_dp_used_c2),
.sel1(~sel_unvuad_dp_used_c2));
assign lru_triad0_muxsel_c2[1:0] = lru_triad0_tagsel_c2[1:0] ;
assign lru_triad0_muxsel_c2[2] = ~( lru_triad0_tagsel_c2[1] | lru_triad0_tagsel_c2[0] ) ;
/************ LRU way within triad1 ************************/
assign used_triad1_tagsel_c2[0] = used_lru_triad1_c2[0] &
( lru_state_triad1[0] |
( lru_state_triad1[1] & ~( used_lru_triad1_c2[1] |
used_lru_triad1_c2[2] ) ) |
( lru_state_triad1[2] & ~used_lru_triad1_c2[2] ) ) ;
assign used_triad1_tagsel_c2[1] = used_lru_triad1_c2[1] &
( lru_state_triad1[1] |
( lru_state_triad1[2] & ~( used_lru_triad1_c2[2] |
used_lru_triad1_c2[0] )) |
( lru_state_triad1[0] & ~used_lru_triad1_c2[0]) ) ;
assign used_triad1_tagsel_c2[2] = used_lru_triad1_c2[2] &
( lru_state_triad1[2] |
( lru_state_triad1[0] & ~(used_lru_triad1_c2[0] |
used_lru_triad1_c2[1])) |
( lru_state_triad1[1] & ~used_lru_triad1_c2[1] ) ) ;
assign alloc_triad1_tagsel_c2[0] = alloc_lru_triad1_c2[0] &
( lru_state_triad1[0] |
( lru_state_triad1[1] & ~( alloc_lru_triad1_c2[1] |
alloc_lru_triad1_c2[2] ) ) |
( lru_state_triad1[2] & ~alloc_lru_triad1_c2[2] ) ) ;
assign alloc_triad1_tagsel_c2[1] = alloc_lru_triad1_c2[1] &
( lru_state_triad1[1] |
( lru_state_triad1[2] & ~( alloc_lru_triad1_c2[2] |
alloc_lru_triad1_c2[0] )) |
( lru_state_triad1[0] & ~alloc_lru_triad1_c2[0]) ) ;
assign alloc_triad1_tagsel_c2[2] = alloc_lru_triad1_c2[2] &
( lru_state_triad1[2] |
( lru_state_triad1[0] & ~(alloc_lru_triad1_c2[0] |
alloc_lru_triad1_c2[1])) |
( lru_state_triad1[1] & ~alloc_lru_triad1_c2[1] ) ) ;
mux2ds #(3) mux_used_lru_triad1 (.dout (lru_triad1_tagsel_c2[2:0]),
.in0(used_triad1_tagsel_c2[2:0]),
.in1(alloc_triad1_tagsel_c2[2:0]),
.sel0(sel_unvuad_dp_used_c2),
.sel1(~sel_unvuad_dp_used_c2));
assign lru_triad1_muxsel_c2[1:0] = lru_triad1_tagsel_c2[1:0] ;
assign lru_triad1_muxsel_c2[2] = ~( lru_triad1_tagsel_c2[1] | lru_triad1_tagsel_c2[0] ) ;
/************ LRU way within triad2 ************************/
assign used_triad2_tagsel_c2[0] = used_lru_triad2_c2[0] &
( lru_state_triad2[0] |
( lru_state_triad2[1] & ~( used_lru_triad2_c2[1] |
used_lru_triad2_c2[2] ) ) |
( lru_state_triad2[2] & ~used_lru_triad2_c2[2] ) ) ;
assign used_triad2_tagsel_c2[1] = used_lru_triad2_c2[1] &
( lru_state_triad2[1] |
( lru_state_triad2[2] & ~( used_lru_triad2_c2[2] |
used_lru_triad2_c2[0] )) |
( lru_state_triad2[0] & ~used_lru_triad2_c2[0]) ) ;
assign used_triad2_tagsel_c2[2] = used_lru_triad2_c2[2] &
( lru_state_triad2[2] |
( lru_state_triad2[0] & ~(used_lru_triad2_c2[0] |
used_lru_triad2_c2[1])) |
( lru_state_triad2[1] & ~used_lru_triad2_c2[1] ) ) ;
assign alloc_triad2_tagsel_c2[0] = alloc_lru_triad2_c2[0] &
( lru_state_triad2[0] |
( lru_state_triad2[1] & ~( alloc_lru_triad2_c2[1] |
alloc_lru_triad2_c2[2] ) ) |
( lru_state_triad2[2] & ~alloc_lru_triad2_c2[2] ) ) ;
assign alloc_triad2_tagsel_c2[1] = alloc_lru_triad2_c2[1] &
( lru_state_triad2[1] |
( lru_state_triad2[2] & ~( alloc_lru_triad2_c2[2] |
alloc_lru_triad2_c2[0] )) |
( lru_state_triad2[0] & ~alloc_lru_triad2_c2[0]) ) ;
assign alloc_triad2_tagsel_c2[2] = alloc_lru_triad2_c2[2] &
( lru_state_triad2[2] |
( lru_state_triad2[0] & ~(alloc_lru_triad2_c2[0] |
alloc_lru_triad2_c2[1])) |
( lru_state_triad2[1] & ~alloc_lru_triad2_c2[1] ) ) ;
mux2ds #(3) mux_used_lru_triad2 (.dout (lru_triad2_tagsel_c2[2:0]),
.in0(used_triad2_tagsel_c2[2:0]),
.in1(alloc_triad2_tagsel_c2[2:0]),
.sel0(sel_unvuad_dp_used_c2),
.sel1(~sel_unvuad_dp_used_c2));
assign lru_triad2_muxsel_c2[1:0] = lru_triad2_tagsel_c2[1:0] ;
assign lru_triad2_muxsel_c2[2] = ~( lru_triad2_tagsel_c2[1] | lru_triad2_tagsel_c2[0] ) ;
/************ LRU way within triad3 ************************/
assign used_triad3_tagsel_c2[0] = used_lru_triad3_c2[0] &
( lru_state_triad3[0] |
( lru_state_triad3[1] & ~( used_lru_triad3_c2[1] |
used_lru_triad3_c2[2] ) ) |
( lru_state_triad3[2] & ~used_lru_triad3_c2[2] ) ) ;
assign used_triad3_tagsel_c2[1] = used_lru_triad3_c2[1] &
( lru_state_triad3[1] |
( lru_state_triad3[2] & ~( used_lru_triad3_c2[2] |
used_lru_triad3_c2[0] )) |
( lru_state_triad3[0] & ~used_lru_triad3_c2[0]) ) ;
assign used_triad3_tagsel_c2[2] = used_lru_triad3_c2[2] &
( lru_state_triad3[2] |
( lru_state_triad3[0] & ~(used_lru_triad3_c2[0] |
used_lru_triad3_c2[1])) |
( lru_state_triad3[1] & ~used_lru_triad3_c2[1] ) ) ;
assign alloc_triad3_tagsel_c2[0] = alloc_lru_triad3_c2[0] &
( lru_state_triad3[0] |
( lru_state_triad3[1] & ~( alloc_lru_triad3_c2[1] |
alloc_lru_triad3_c2[2] ) ) |
( lru_state_triad3[2] & ~alloc_lru_triad3_c2[2] ) ) ;
assign alloc_triad3_tagsel_c2[1] = alloc_lru_triad3_c2[1] &
( lru_state_triad3[1] |
( lru_state_triad3[2] & ~( alloc_lru_triad3_c2[2] |
alloc_lru_triad3_c2[0] )) |
( lru_state_triad3[0] & ~alloc_lru_triad3_c2[0]) ) ;
assign alloc_triad3_tagsel_c2[2] = alloc_lru_triad3_c2[2] &
( lru_state_triad3[2] |
( lru_state_triad3[0] & ~(alloc_lru_triad3_c2[0] |
alloc_lru_triad3_c2[1])) |
( lru_state_triad3[1] & ~alloc_lru_triad3_c2[1] ) ) ;
mux2ds #(3) mux_used_lru_triad3 (.dout (lru_triad3_tagsel_c2[2:0]),
.in0(used_triad3_tagsel_c2[2:0]),
.in1(alloc_triad3_tagsel_c2[2:0]),
.sel0(sel_unvuad_dp_used_c2),
.sel1(~sel_unvuad_dp_used_c2));
assign lru_triad3_muxsel_c2[1:0] = lru_triad3_tagsel_c2[1:0] ;
assign lru_triad3_muxsel_c2[2] = ~( lru_triad3_tagsel_c2[1] | lru_triad3_tagsel_c2[0] ) ;
/************ LRU quad ************************/
assign used_quad_sel_c2[0] = used_lru_quad_c2[0] &
( lru_state[0] |
( lru_state[1] & ~( used_lru_quad_c2[1] |
used_lru_quad_c2[2] | used_lru_quad_c2[3] )) |
( lru_state[2] & ~( used_lru_quad_c2[2] | used_lru_quad_c2[3] )) |
( lru_state[3] & ~(used_lru_quad_c2[3] )) ) ;
assign used_quad_sel_c2[1] = used_lru_quad_c2[1] &
( lru_state[1] |
( lru_state[2] & ~( used_lru_quad_c2[0] |
used_lru_quad_c2[2] | used_lru_quad_c2[3] )) |
( lru_state[3] & ~( used_lru_quad_c2[3] | used_lru_quad_c2[0] )) |
( lru_state[0] & ~(used_lru_quad_c2[0] )) ) ;
assign used_quad_sel_c2[2] = used_lru_quad_c2[2] &
( lru_state[2] |
( lru_state[3] & ~( used_lru_quad_c2[0] |
used_lru_quad_c2[1] | used_lru_quad_c2[3] )) |
( lru_state[0] & ~( used_lru_quad_c2[0] | used_lru_quad_c2[1] )) |
( lru_state[1] & ~(used_lru_quad_c2[1] )) ) ;
assign used_quad_sel_c2[3] = used_lru_quad_c2[3] &
( lru_state[3] |
( lru_state[0] & ~( used_lru_quad_c2[0] |
used_lru_quad_c2[1] | used_lru_quad_c2[2] )) |
( lru_state[1] & ~( used_lru_quad_c2[2] | used_lru_quad_c2[1] )) |
( lru_state[2] & ~(used_lru_quad_c2[2] )) ) ;
assign alloc_quad_sel_c2[0] = alloc_lru_quad_c2[0] &
( lru_state[0] |
( lru_state[1] & ~( alloc_lru_quad_c2[1] |
alloc_lru_quad_c2[2] | alloc_lru_quad_c2[3] )) |
( lru_state[2] & ~( alloc_lru_quad_c2[2] | alloc_lru_quad_c2[3] )) |
( lru_state[3] & ~(alloc_lru_quad_c2[3] )) ) ;
assign alloc_quad_sel_c2[1] = alloc_lru_quad_c2[1] &
( lru_state[1] |
( lru_state[2] & ~( alloc_lru_quad_c2[0] |
alloc_lru_quad_c2[2] | alloc_lru_quad_c2[3] )) |
( lru_state[3] & ~( alloc_lru_quad_c2[3] | alloc_lru_quad_c2[0] )) |
( lru_state[0] & ~(alloc_lru_quad_c2[0] )) ) ;
assign alloc_quad_sel_c2[2] = alloc_lru_quad_c2[2] &
( lru_state[2] |
( lru_state[3] & ~( alloc_lru_quad_c2[0] |
alloc_lru_quad_c2[1] | alloc_lru_quad_c2[3] )) |
( lru_state[0] & ~( alloc_lru_quad_c2[0] | alloc_lru_quad_c2[1] )) |
( lru_state[1] & ~(alloc_lru_quad_c2[1] )) ) ;
assign alloc_quad_sel_c2[3] = alloc_lru_quad_c2[3] &
( lru_state[3] |
( lru_state[0] & ~( alloc_lru_quad_c2[0] |
alloc_lru_quad_c2[1] | alloc_lru_quad_c2[2] )) |
( lru_state[1] & ~( alloc_lru_quad_c2[2] | alloc_lru_quad_c2[1] )) |
( lru_state[2] & ~(alloc_lru_quad_c2[2] )) ) ;
mux2ds #(4) mux_used_lru_quad (.dout (lru_quad_sel_c2[3:0]),
.in0(used_quad_sel_c2[3:0]),
.in1(alloc_quad_sel_c2[3:0]),
.sel0(sel_unvuad_dp_used_c2),
.sel1(~sel_unvuad_dp_used_c2));
assign lru_quad_muxsel_c2[2:0] = lru_quad_sel_c2[2:0] ;
assign lru_quad_muxsel_c2[3] = ~( lru_quad_sel_c2[2] | lru_quad_sel_c2[1] | lru_quad_sel_c2[0] ) ;
// lru_way_sel_c2 takes 14-15 gates to compute.
assign lru_way_sel_c2[2:0] = lru_triad0_tagsel_c2 & {3{lru_quad_sel_c2[0]}} ;
assign lru_way_sel_c2[5:3] = lru_triad1_tagsel_c2 & {3{lru_quad_sel_c2[1]}} ;
assign lru_way_sel_c2[8:6] = lru_triad2_tagsel_c2 & {3{lru_quad_sel_c2[2]}} ;
assign lru_way_sel_c2[11:9] = lru_triad3_tagsel_c2 & {3{lru_quad_sel_c2[3]}} ;
assign dec_lo_dir_way_c2[0] = ( arbdp_diag_wr_way_c2[1:0]==2'd0 ) ;
assign dec_lo_dir_way_c2[1] = ( arbdp_diag_wr_way_c2[1:0]==2'd1 ) ;
assign dec_lo_dir_way_c2[2] = ( arbdp_diag_wr_way_c2[1:0]==2'd2 ) ;
assign dec_lo_dir_way_c2[3] = ( arbdp_diag_wr_way_c2[1:0]==2'd3 ) ;
assign dec_hi_dir_way_c2[0] = ( arbdp_diag_wr_way_c2[3:2]==2'd0 ) ;
assign dec_hi_dir_way_c2[1] = ( arbdp_diag_wr_way_c2[3:2]==2'd1 ) ;
assign dec_hi_dir_way_c2[2] = ( arbdp_diag_wr_way_c2[3:2]==2'd2 ) ;
assign dec_hi_dir_way_c2[3] = ( arbdp_diag_wr_way_c2[3:2]==2'd3 ) ;
assign dec_dir_way_c2[0] = dec_hi_dir_way_c2[0] &
dec_lo_dir_way_c2[0] ; // 0000
assign dec_dir_way_c2[1] = dec_hi_dir_way_c2[0] &
dec_lo_dir_way_c2[1] ; // 0001
assign dec_dir_way_c2[2] = dec_hi_dir_way_c2[0] &
dec_lo_dir_way_c2[2] ; // 0010
assign dec_dir_way_c2[3] = dec_hi_dir_way_c2[0] &
dec_lo_dir_way_c2[3] ; // 0011
assign dec_dir_way_c2[4] = ( dec_hi_dir_way_c2[1] |
dec_hi_dir_way_c2[3] ) &
dec_lo_dir_way_c2[0] ; // 0100 or 1100
assign dec_dir_way_c2[5] = ( dec_hi_dir_way_c2[1] |
dec_hi_dir_way_c2[3] ) &
dec_lo_dir_way_c2[1] ; // 0101 or 1101
assign dec_dir_way_c2[6] = ( dec_hi_dir_way_c2[1] |
dec_hi_dir_way_c2[3] ) &
dec_lo_dir_way_c2[2] ; // 0110 or 1110
assign dec_dir_way_c2[7] = ( dec_hi_dir_way_c2[1] |
dec_hi_dir_way_c2[3] ) &
dec_lo_dir_way_c2[3] ; // 0111 or 1111
assign dec_dir_way_c2[8] = dec_hi_dir_way_c2[2] &
dec_lo_dir_way_c2[0] ; // 1000
assign dec_dir_way_c2[9] = dec_hi_dir_way_c2[2] &
dec_lo_dir_way_c2[1] ; // 1001
assign dec_dir_way_c2[10] = dec_hi_dir_way_c2[2] &
dec_lo_dir_way_c2[2] ; // 1010
assign dec_dir_way_c2[11] = dec_hi_dir_way_c2[2] &
dec_lo_dir_way_c2[3] ; // 1011
mux2ds #(12) mux_evict_way_sel_c2
(.dout (evict_way_sel_c2[11:0]),
.in0 (dec_dir_way_c2[11:0]), .sel0 (l2_dir_map_on_d1),
.in1 (lru_way_sel_c2[11:0]), .sel1 (~l2_dir_map_on_d1)
) ;
dff_s #(12) ff_lru_way_c3 (.din(evict_way_sel_c2[11:0]),
.clk(rclk),
.q(lru_way_sel_c3[11:0]),
.se(se),
.si(),
.so());
dff_s #(12) ff_lru_way_c3_1 (.din(evict_way_sel_c2[11:0]),
.clk(rclk),
.q(lru_way_sel_c3_1[11:0]),
.se(se),
.si(),
.so());
dff_s #(12) ff_valid_c3 (.din(vuad_dp_valid_c2[11:0]),
.clk(rclk),
.q(valid_c3[11:0]),
.se(se),
.si(),
.so());
assign pick_triad0 = |(lru_way_sel_c3_1[2:0] ) ;
assign pick_triad1 = |(lru_way_sel_c3_1[5:3] ) ;
assign pick_triad2 = |(lru_way_sel_c3_1[8:6] ) ;
assign pick_triad3 = |(lru_way_sel_c3_1[11:9]) ;
endmodule
|
// ******************************************************************************* //
// ** General Information ** //
// ******************************************************************************* //
// ** Module : firdecim_m5_n15.v ** //
// ** Project : ISAAC Newton ** //
// ** Author : Kayla Nguyen ** //
// ** First Release Date : August 13, 2008 ** //
// ** Description : Polyphase Decimation Filter ** //
// ** M = 5, L = 15 ** //
// ******************************************************************************* //
// ** Revision History ** //
// ******************************************************************************* //
// ** ** //
// ** File : firdecim_m5_n15.v ** //
// ** Revision : 1 ** //
// ** Author : kaylangu ** //
// ** Date : August 13, 2008 ** //
// ** FileName : ** //
// ** Notes : Initial Release for ISAAC demo ** //
// ** ** //
// ** File : firdecim_m5_n15.v ** //
// ** Revision : 2 ** //
// ** Author : kaylangu ** //
// ** Date : October 23, 2008 ** //
// ** FileName : ** //
// ** Notes : Add Sync signal to synchronize filter with LkupTbl ** //
// ** ** //
// ** File : firdecim_m5_n15.v ** //
// ** Revision : 3 ** //
// ** Author : kaylangu ** //
// ** Date : January 28, 2009 ** //
// ** FileName : ** //
// ** Notes : Remove Sync signal ** //
// ** ** //
// ** File : firdecim_m5_n15.v ** //
// ** Revision : 4 ** //
// ** Author : kaylangu ** //
// ** Date : February 9, 2009 ** //
// ** FileName : ** //
// ** Notes : Remove shift registers for coefficients and replace with ** //
// ** distrubited ROMs ** //
// ** ** //
// ******************************************************************************* //
`timescale 1 ns / 100 ps
module firdecim_m5_n15
(/*AUTOARG*/
// Outputs
SigOut, DataValid,
// Inputs
CLK, ARST, InputValid, SigIn
);
//**************************************************************************//
//* Declarations *//
//**************************************************************************//
// DATA TYPE - PARAMETERS
parameter IWIDTH = 16;
parameter OWIDTH = 32;
parameter ACCUMWIDTH = 32;
// DATA TYPE - INPUTS AND OUTPUTS
output reg signed [(OWIDTH-1):0] SigOut;
output reg DataValid;
input CLK; // 60MHz Clock
input ARST;
input InputValid;
input signed [(IWIDTH-1):0] SigIn;
// DATA TYPE - REGISTERS
reg signed [15:0] coe10;
reg signed [15:0] coe5;
reg signed [15:0] coe0;
reg [3:0] count;
// DATA TYPE - WIRES
wire signed [(ACCUMWIDTH-1):0] SigOut1;
wire signed [(ACCUMWIDTH-1):0] SigOut2;
wire signed [(ACCUMWIDTH-1):0] SigOut3;
wire initialize1;
wire initialize2;
wire initialize3;
wire DataValid1;
wire DataValid2;
wire DataValid3;
wire [3:0] coe0_cnt;
wire [3:0] coe5_cnt;
wire [3:0] coe10_cnt;
//**************************************************************************//
//* Coefficient Rotation *//
//**************************************************************************//
always @ (posedge CLK or posedge ARST)
if (ARST)
begin
coe0[15:0] <= 16'd0;
end
else
begin
case (coe0_cnt[3:0])
4'b0000: coe0[15:0] <= 16'sb1111111111001010;//0000_0000_0001_1111
4'b0001: coe0[15:0] <= 16'sb1111111111011001;//0000_0000_1000_1101
4'b0010: coe0[15:0] <= 16'sb0000000001111110;//0000_0001_1000_0010
4'b0011: coe0[15:0] <= 16'sb0000001000101101;//0000_0011_0001_1110
4'b0100: coe0[15:0] <= 16'sb0000010011101110;//0000_0101_0011_1111
4'b0101: coe0[15:0] <= 16'sb0000100000100111;//0000_0111_0111_1000
4'b0110: coe0[15:0] <= 16'sb0000101011001010;//0000_1001_0010_1011
4'b0111: coe0[15:0] <= 16'sb0000101111001111;//0000_1001_1100_1111
4'b1000: coe0[15:0] <= 16'sb0000101011001010;//0000_1001_0010_1011
4'b1001: coe0[15:0] <= 16'sb0000100000100111;//0000_0111_0111_1000
4'b1010: coe0[15:0] <= 16'sb0000010011101110;//0000_0101_0011_1111
4'b1011: coe0[15:0] <= 16'sb0000001000101101;//0000_0011_0001_1110
4'b1100: coe0[15:0] <= 16'sb0000000001111110;//0000_0001_1000_0010
4'b1101: coe0[15:0] <= 16'sb1111111111011001;//0000_0000_1000_1101
4'b1110: coe0[15:0] <= 16'sb1111111111001010;//0000_0000_0001_1111
default: coe0[15:0] <= 16'sb1111111111001010;//0000_0000_0001_1111;
endcase
end
always @ (posedge CLK or posedge ARST)
if (ARST)
begin
coe5[15:0] <= 16'd0;
end
else
begin
case (coe5_cnt[3:0])
4'b0000: coe5[15:0] <= 16'sb0000_0000_0001_1111;
4'b0001: coe5[15:0] <= 16'sb0000_0000_1000_1101;
4'b0010: coe5[15:0] <= 16'sb0000_0001_1000_0010;
4'b0011: coe5[15:0] <= 16'sb0000_0011_0001_1110;
4'b0100: coe5[15:0] <= 16'sb0000_0101_0011_1111;
4'b0101: coe5[15:0] <= 16'sb0000_0111_0111_1000;
4'b0110: coe5[15:0] <= 16'sb0000_1001_0010_1011;
4'b0111: coe5[15:0] <= 16'sb0000_1001_1100_1111;
4'b1000: coe5[15:0] <= 16'sb0000_1001_0010_1011;
4'b1001: coe5[15:0] <= 16'sb0000_0111_0111_1000;
4'b1010: coe5[15:0] <= 16'sb0000_0101_0011_1111;
4'b1011: coe5[15:0] <= 16'sb0000_0011_0001_1110;
4'b1100: coe5[15:0] <= 16'sb0000_0001_1000_0010;
4'b1101: coe5[15:0] <= 16'sb0000_0000_1000_1101;
4'b1110: coe5[15:0] <= 16'sb0000_0000_0001_1111;
default: coe5[15:0] <= 16'sb0000_0000_0001_1111;
endcase
end
always @ (posedge CLK or posedge ARST)
if (ARST)
begin
coe10[15:0] <= 16'd0;
end
else
begin
case (coe10_cnt[3:0])
4'b0000: coe10[15:0] <= 16'sb0000_0000_0001_1111;
4'b0001: coe10[15:0] <= 16'sb0000_0000_1000_1101;
4'b0010: coe10[15:0] <= 16'sb0000_0001_1000_0010;
4'b0011: coe10[15:0] <= 16'sb0000_0011_0001_1110;
4'b0100: coe10[15:0] <= 16'sb0000_0101_0011_1111;
4'b0101: coe10[15:0] <= 16'sb0000_0111_0111_1000;
4'b0110: coe10[15:0] <= 16'sb0000_1001_0010_1011;
4'b0111: coe10[15:0] <= 16'sb0000_1001_1100_1111;
4'b1000: coe10[15:0] <= 16'sb0000_1001_0010_1011;
4'b1001: coe10[15:0] <= 16'sb0000_0111_0111_1000;
4'b1010: coe10[15:0] <= 16'sb0000_0101_0011_1111;
4'b1011: coe10[15:0] <= 16'sb0000_0011_0001_1110;
4'b1100: coe10[15:0] <= 16'sb0000_0001_1000_0010;
4'b1101: coe10[15:0] <= 16'sb0000_0000_1000_1101;
4'b1110: coe10[15:0] <= 16'sb0000_0000_0001_1111;
default: coe10[15:0] <= 16'sb0000_0000_0001_1111;
endcase
end
//**************************************************************************//
//* Counter *//
//**************************************************************************//
always @ (posedge CLK or posedge ARST)
if (ARST)
begin
count[3:0] <= {(4){1'b0}} ;
end
else if (InputValid)
begin
count[3:0] <= (count[3:0] == (14)) ? 0 : count[3:0] + 1 ;
end
assign coe0_cnt[3:0] = count[3:0] == 14 ? 0 :
count[3:0] + 1;
assign coe5_cnt[3:0] = (count[3:0] + 6 ) > 14 ? count[3:0] - 9 :
count[3:0] + 6 ;
assign coe10_cnt[3:0] = (count[3:0] + 11 ) > 14 ? count[3:0] - 4 :
count[3:0] + 11 ;
//**************************************************************************//
//* Reset each MAC *//
//**************************************************************************//
assign initialize1 = (count == 0) ;
assign initialize2 = (count == 5) ;
assign initialize3 = (count == 10) ;
//**************************************************************************//
//* Output Buffers *//
//**************************************************************************//
always @ (posedge CLK or posedge ARST)
if (ARST)
begin
SigOut[(OWIDTH-1):0] <= {(OWIDTH){1'b0}};
end
else if (DataValid1 | DataValid2 | DataValid3)
begin
SigOut[(OWIDTH-1):0] <= {(OWIDTH){DataValid1}} & SigOut1 |
{(OWIDTH){DataValid2}} & SigOut2 |
{(OWIDTH){DataValid3}} & SigOut3 ;
end
always @ (posedge CLK or posedge ARST)
if (ARST)
begin
DataValid <= 1'b0 ;
end
else
begin
DataValid <= (DataValid1 | DataValid2 | DataValid3) ;
end
//**************************************************************************//
//* Submodules *//
//**************************************************************************//
//First MAC
MAC1 MAC1_a
(// Inputs
.CLK (CLK), // CLK
.ARST (ARST), // ARST
.filterCoef (coe0), // Filter Coeficients
.InData (SigIn), // Input Data
.input_Valid (InputValid), // Input Valid
.initialize (initialize1), // Initialize
//Outputs
.OutData (SigOut1), // Output Data
.output_Valid (DataValid1) // Output Valid
);
// Second MAC
MAC1 MAC1_b
(// Inputs
.CLK (CLK), // CLK
.ARST (ARST), // ARST
.filterCoef (coe10), // Filter Coeficients
.InData (SigIn), // Input Data
.input_Valid (InputValid), // Input Valid
.initialize (initialize2), // Initialize
//Outputs
.OutData (SigOut2), // Output Data
.output_Valid (DataValid2) // Output Valid
);
// Third MAC
MAC1 MAC1_c
(// Inputs
.CLK (CLK), // CLK
.ARST (ARST), // ARST
.filterCoef (coe5), // Filter Coeficients
.InData (SigIn), // Input Data
.input_Valid (InputValid), // Input Valid
.initialize (initialize3), // Initialize
//Outputs
.OutData (SigOut3), // Output Data
.output_Valid (DataValid3) // Output Valid
);
endmodule // firdecim_m5_n15 |
/*****************************************************************************
* File : processing_system7_bfm_v2_0_5_unused_ports.v
*
* Date : 2012-11
*
* Description : Semantic checks for unused ports.
*
*****************************************************************************/
/* CAN */
assign CAN0_PHY_TX = 0;
assign CAN1_PHY_TX = 0;
always @(CAN0_PHY_RX or CAN1_PHY_RX)
begin
if(CAN0_PHY_RX | CAN1_PHY_RX)
$display("[%0d] : %0s : CAN Interface is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* ETHERNET */
/* ------------------------------------------- */
assign ENET0_GMII_TX_EN = 0;
assign ENET0_GMII_TX_ER = 0;
assign ENET0_MDIO_MDC = 0;
assign ENET0_MDIO_O = 0; /// confirm
assign ENET0_MDIO_T = 0;
assign ENET0_PTP_DELAY_REQ_RX = 0;
assign ENET0_PTP_DELAY_REQ_TX = 0;
assign ENET0_PTP_PDELAY_REQ_RX = 0;
assign ENET0_PTP_PDELAY_REQ_TX = 0;
assign ENET0_PTP_PDELAY_RESP_RX = 0;
assign ENET0_PTP_PDELAY_RESP_TX = 0;
assign ENET0_PTP_SYNC_FRAME_RX = 0;
assign ENET0_PTP_SYNC_FRAME_TX = 0;
assign ENET0_SOF_RX = 0;
assign ENET0_SOF_TX = 0;
assign ENET0_GMII_TXD = 0;
always@(ENET0_GMII_COL or ENET0_GMII_CRS or ENET0_EXT_INTIN or
ENET0_GMII_RX_CLK or ENET0_GMII_RX_DV or ENET0_GMII_RX_ER or
ENET0_GMII_TX_CLK or ENET0_MDIO_I or ENET0_GMII_RXD)
begin
if(ENET0_GMII_COL | ENET0_GMII_CRS | ENET0_EXT_INTIN |
ENET0_GMII_RX_CLK | ENET0_GMII_RX_DV | ENET0_GMII_RX_ER |
ENET0_GMII_TX_CLK | ENET0_MDIO_I )
$display("[%0d] : %0s : ETHERNET Interface is not supported.",$time, DISP_ERR);
end
assign ENET1_GMII_TX_EN = 0;
assign ENET1_GMII_TX_ER = 0;
assign ENET1_MDIO_MDC = 0;
assign ENET1_MDIO_O = 0;/// confirm
assign ENET1_MDIO_T = 0;
assign ENET1_PTP_DELAY_REQ_RX = 0;
assign ENET1_PTP_DELAY_REQ_TX = 0;
assign ENET1_PTP_PDELAY_REQ_RX = 0;
assign ENET1_PTP_PDELAY_REQ_TX = 0;
assign ENET1_PTP_PDELAY_RESP_RX = 0;
assign ENET1_PTP_PDELAY_RESP_TX = 0;
assign ENET1_PTP_SYNC_FRAME_RX = 0;
assign ENET1_PTP_SYNC_FRAME_TX = 0;
assign ENET1_SOF_RX = 0;
assign ENET1_SOF_TX = 0;
assign ENET1_GMII_TXD = 0;
always@(ENET1_GMII_COL or ENET1_GMII_CRS or ENET1_EXT_INTIN or
ENET1_GMII_RX_CLK or ENET1_GMII_RX_DV or ENET1_GMII_RX_ER or
ENET1_GMII_TX_CLK or ENET1_MDIO_I or ENET1_GMII_RXD)
begin
if(ENET1_GMII_COL | ENET1_GMII_CRS | ENET1_EXT_INTIN |
ENET1_GMII_RX_CLK | ENET1_GMII_RX_DV | ENET1_GMII_RX_ER |
ENET1_GMII_TX_CLK | ENET1_MDIO_I )
$display("[%0d] : %0s : ETHERNET Interface is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* GPIO */
/* ------------------------------------------- */
assign GPIO_O = 0;
assign GPIO_T = 0;
always@(GPIO_I)
begin
if(GPIO_I !== 0)
$display("[%0d] : %0s : GPIO Interface is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* I2C */
/* ------------------------------------------- */
assign I2C0_SDA_O = 0;
assign I2C0_SDA_T = 0;
assign I2C0_SCL_O = 0;
assign I2C0_SCL_T = 0;
assign I2C1_SDA_O = 0;
assign I2C1_SDA_T = 0;
assign I2C1_SCL_O = 0;
assign I2C1_SCL_T = 0;
always@(I2C0_SDA_I or I2C0_SCL_I or I2C1_SDA_I or I2C1_SCL_I )
begin
if(I2C0_SDA_I | I2C0_SCL_I | I2C1_SDA_I | I2C1_SCL_I)
$display("[%0d] : %0s : I2C Interface is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* JTAG */
/* ------------------------------------------- */
assign PJTAG_TD_T = 0;
assign PJTAG_TD_O = 0;
always@(PJTAG_TCK or PJTAG_TMS or PJTAG_TD_I)
begin
if(PJTAG_TCK | PJTAG_TMS | PJTAG_TD_I)
$display("[%0d] : %0s : JTAG Interface is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* SDIO */
/* ------------------------------------------- */
assign SDIO0_CLK = 0;
assign SDIO0_CMD_O = 0;
assign SDIO0_CMD_T = 0;
assign SDIO0_DATA_O = 0;
assign SDIO0_DATA_T = 0;
assign SDIO0_LED = 0;
assign SDIO0_BUSPOW = 0;
assign SDIO0_BUSVOLT = 0;
always@(SDIO0_CLK_FB or SDIO0_CMD_I or SDIO0_DATA_I or SDIO0_CDN or SDIO0_WP )
begin
if(SDIO0_CLK_FB | SDIO0_CMD_I | SDIO0_CDN | SDIO0_WP )
$display("[%0d] : %0s : SDIO Interface is not supported.",$time, DISP_ERR);
end
assign SDIO1_CLK = 0;
assign SDIO1_CMD_O = 0;
assign SDIO1_CMD_T = 0;
assign SDIO1_DATA_O = 0;
assign SDIO1_DATA_T = 0;
assign SDIO1_LED = 0;
assign SDIO1_BUSPOW = 0;
assign SDIO1_BUSVOLT = 0;
always@(SDIO1_CLK_FB or SDIO1_CMD_I or SDIO1_DATA_I or SDIO1_CDN or SDIO1_WP )
begin
if(SDIO1_CLK_FB | SDIO1_CMD_I | SDIO1_CDN | SDIO1_WP )
$display("[%0d] : %0s : SDIO Interface is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* SPI */
/* ------------------------------------------- */
assign SPI0_SCLK_O = 0;
assign SPI0_SCLK_T = 0;
assign SPI0_MOSI_O = 0;
assign SPI0_MOSI_T = 0;
assign SPI0_MISO_O = 0;
assign SPI0_MISO_T = 0;
assign SPI0_SS_O = 0; /// confirm
assign SPI0_SS1_O = 0;/// confirm
assign SPI0_SS2_O = 0;/// confirm
assign SPI0_SS_T = 0;
always@(SPI0_SCLK_I or SPI0_MOSI_I or SPI0_MISO_I or SPI0_SS_I)
begin
if(SPI0_SCLK_I | SPI0_MOSI_I | SPI0_MISO_I | SPI0_SS_I)
$display("[%0d] : %0s : SPI Interface is not supported.",$time, DISP_ERR);
end
assign SPI1_SCLK_O = 0;
assign SPI1_SCLK_T = 0;
assign SPI1_MOSI_O = 0;
assign SPI1_MOSI_T = 0;
assign SPI1_MISO_O = 0;
assign SPI1_MISO_T = 0;
assign SPI1_SS_O = 0;
assign SPI1_SS1_O = 0;
assign SPI1_SS2_O = 0;
assign SPI1_SS_T = 0;
always@(SPI1_SCLK_I or SPI1_MOSI_I or SPI1_MISO_I or SPI1_SS_I)
begin
if(SPI1_SCLK_I | SPI1_MOSI_I | SPI1_MISO_I | SPI1_SS_I)
$display("[%0d] : %0s : SPI Interface is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* UART */
/* ------------------------------------------- */
/// confirm
assign UART0_DTRN = 0;
assign UART0_RTSN = 0;
assign UART0_TX = 0;
always@(UART0_CTSN or UART0_DCDN or UART0_DSRN or UART0_RIN or UART0_RX)
begin
if(UART0_CTSN | UART0_DCDN | UART0_DSRN | UART0_RIN | UART0_RX)
$display("[%0d] : %0s : UART Interface is not supported.",$time, DISP_ERR);
end
assign UART1_DTRN = 0;
assign UART1_RTSN = 0;
assign UART1_TX = 0;
always@(UART1_CTSN or UART1_DCDN or UART1_DSRN or UART1_RIN or UART1_RX)
begin
if(UART1_CTSN | UART1_DCDN | UART1_DSRN | UART1_RIN | UART1_RX)
$display("[%0d] : %0s : UART Interface is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* TTC */
/* ------------------------------------------- */
assign TTC0_WAVE0_OUT = 0;
assign TTC0_WAVE1_OUT = 0;
assign TTC0_WAVE2_OUT = 0;
always@(TTC0_CLK0_IN or TTC0_CLK1_IN or TTC0_CLK2_IN)
begin
if(TTC0_CLK0_IN | TTC0_CLK1_IN | TTC0_CLK2_IN)
$display("[%0d] : %0s : TTC Interface is not supported.",$time, DISP_ERR);
end
assign TTC1_WAVE0_OUT = 0;
assign TTC1_WAVE1_OUT = 0;
assign TTC1_WAVE2_OUT = 0;
always@(TTC1_CLK0_IN or TTC1_CLK1_IN or TTC1_CLK2_IN)
begin
if(TTC1_CLK0_IN | TTC1_CLK1_IN | TTC1_CLK2_IN)
$display("[%0d] : %0s : TTC Interface is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* WDT */
/* ------------------------------------------- */
assign WDT_RST_OUT = 0;
always@(WDT_CLK_IN)
begin
if(WDT_CLK_IN)
$display("[%0d] : %0s : WDT Interface is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* TRACE */
/* ------------------------------------------- */
assign TRACE_CTL = 0;
assign TRACE_DATA = 0;
always@(TRACE_CLK)
begin
if(TRACE_CLK)
$display("[%0d] : %0s : TRACE Interface is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* USB */
/* ------------------------------------------- */
assign USB0_PORT_INDCTL = 0;
assign USB0_VBUS_PWRSELECT = 0;
always@(USB0_VBUS_PWRFAULT)
begin
if(USB0_VBUS_PWRFAULT)
$display("[%0d] : %0s : USB Interface is not supported.",$time, DISP_ERR);
end
assign USB1_PORT_INDCTL = 0;
assign USB1_VBUS_PWRSELECT = 0;
always@(USB1_VBUS_PWRFAULT)
begin
if(USB1_VBUS_PWRFAULT)
$display("[%0d] : %0s : USB Interface is not supported.",$time, DISP_ERR);
end
always@(SRAM_INTIN)
begin
if(SRAM_INTIN)
$display("[%0d] : %0s : SRAM_INTIN is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* DMA */
/* ------------------------------------------- */
assign DMA0_DATYPE = 0;
assign DMA0_DAVALID = 0;
assign DMA0_DRREADY = 0;
assign DMA0_RSTN = 0;
always@(DMA0_ACLK or DMA0_DAREADY or DMA0_DRLAST or DMA0_DRVALID or DMA0_DRTYPE)
begin
if(DMA0_ACLK | DMA0_DAREADY | DMA0_DRLAST | DMA0_DRVALID | DMA0_DRTYPE)
$display("[%0d] : %0s : DMA Interface is not supported.",$time, DISP_ERR);
end
assign DMA1_DATYPE = 0;
assign DMA1_DAVALID = 0;
assign DMA1_DRREADY = 0;
assign DMA1_RSTN = 0;
always@(DMA1_ACLK or DMA1_DAREADY or DMA1_DRLAST or DMA1_DRVALID or DMA1_DRTYPE)
begin
if(DMA1_ACLK | DMA1_DAREADY | DMA1_DRLAST | DMA1_DRVALID | DMA1_DRTYPE)
$display("[%0d] : %0s : DMA Interface is not supported.",$time, DISP_ERR);
end
assign DMA2_DATYPE = 0;
assign DMA2_DAVALID = 0;
assign DMA2_DRREADY = 0;
assign DMA2_RSTN = 0;
always@(DMA2_ACLK or DMA2_DAREADY or DMA2_DRLAST or DMA2_DRVALID or DMA2_DRTYPE)
begin
if(DMA2_ACLK | DMA2_DAREADY | DMA2_DRLAST | DMA2_DRVALID | DMA2_DRTYPE)
$display("[%0d] : %0s : DMA Interface is not supported.",$time, DISP_ERR);
end
assign DMA3_DATYPE = 0;
assign DMA3_DAVALID = 0;
assign DMA3_DRREADY = 0;
assign DMA3_RSTN = 0;
always@(DMA3_ACLK or DMA3_DAREADY or DMA3_DRLAST or DMA3_DRVALID or DMA3_DRTYPE)
begin
if(DMA3_ACLK | DMA3_DAREADY | DMA3_DRLAST | DMA3_DRVALID | DMA3_DRTYPE)
$display("[%0d] : %0s : DMA Interface is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* FTM */
/* ------------------------------------------- */
assign FTMT_F2P_TRIGACK = 0;
assign FTMT_P2F_TRIG = 0;
assign FTMT_P2F_DEBUG = 0;
always@(FTMD_TRACEIN_DATA or FTMD_TRACEIN_VALID or FTMD_TRACEIN_CLK or
FTMD_TRACEIN_ATID or FTMT_F2P_TRIG or FTMT_F2P_DEBUG or FTMT_P2F_TRIGACK)
begin
if(FTMD_TRACEIN_DATA | FTMD_TRACEIN_VALID | FTMD_TRACEIN_CLK | FTMD_TRACEIN_ATID | FTMT_F2P_TRIG | FTMT_F2P_DEBUG | FTMT_P2F_TRIGACK)
$display("[%0d] : %0s : FTM Interface is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* EVENT */
/* ------------------------------------------- */
assign EVENT_EVENTO = 0;
assign EVENT_STANDBYWFE = 0;
assign EVENT_STANDBYWFI = 0;
always@(EVENT_EVENTI)
begin
if(EVENT_EVENTI)
$display("[%0d] : %0s : EVENT Interface is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* MIO */
/* ------------------------------------------- */
always@(MIO)
begin
if(MIO !== 0)
$display("[%0d] : %0s : MIO is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* FCLK_TRIG */
/* ------------------------------------------- */
always@(FCLK_CLKTRIG3_N or FCLK_CLKTRIG2_N or FCLK_CLKTRIG1_N or FCLK_CLKTRIG0_N )
begin
if(FCLK_CLKTRIG3_N | FCLK_CLKTRIG2_N | FCLK_CLKTRIG1_N | FCLK_CLKTRIG0_N )
$display("[%0d] : %0s : FCLK_TRIG is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* MISC */
/* ------------------------------------------- */
always@(FPGA_IDLE_N)
begin
if(FPGA_IDLE_N)
$display("[%0d] : %0s : FPGA_IDLE_N is not supported.",$time, DISP_ERR);
end
always@(DDR_ARB)
begin
if(DDR_ARB !== 0)
$display("[%0d] : %0s : DDR_ARB is not supported.",$time, DISP_ERR);
end
always@(Core0_nFIQ or Core0_nIRQ or Core1_nFIQ or Core1_nIRQ )
begin
if(Core0_nFIQ | Core0_nIRQ | Core1_nFIQ | Core1_nIRQ)
$display("[%0d] : %0s : CORE FIQ,IRQ is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* DDR */
/* ------------------------------------------- */
assign DDR_WEB = 0;
always@(DDR_Clk or DDR_CS_n)
begin
if(!DDR_CS_n)
$display("[%0d] : %0s : EXTERNAL DDR is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* IRQ_P2F */
/* ------------------------------------------- */
assign IRQ_P2F_DMAC_ABORT = 0;
assign IRQ_P2F_DMAC0 = 0;
assign IRQ_P2F_DMAC1 = 0;
assign IRQ_P2F_DMAC2 = 0;
assign IRQ_P2F_DMAC3 = 0;
assign IRQ_P2F_DMAC4 = 0;
assign IRQ_P2F_DMAC5 = 0;
assign IRQ_P2F_DMAC6 = 0;
assign IRQ_P2F_DMAC7 = 0;
assign IRQ_P2F_SMC = 0;
assign IRQ_P2F_QSPI = 0;
assign IRQ_P2F_CTI = 0;
assign IRQ_P2F_GPIO = 0;
assign IRQ_P2F_USB0 = 0;
assign IRQ_P2F_ENET0 = 0;
assign IRQ_P2F_ENET_WAKE0 = 0;
assign IRQ_P2F_SDIO0 = 0;
assign IRQ_P2F_I2C0 = 0;
assign IRQ_P2F_SPI0 = 0;
assign IRQ_P2F_UART0 = 0;
assign IRQ_P2F_CAN0 = 0;
assign IRQ_P2F_USB1 = 0;
assign IRQ_P2F_ENET1 = 0;
assign IRQ_P2F_ENET_WAKE1 = 0;
assign IRQ_P2F_SDIO1 = 0;
assign IRQ_P2F_I2C1 = 0;
assign IRQ_P2F_SPI1 = 0;
assign IRQ_P2F_UART1 = 0;
assign IRQ_P2F_CAN1 = 0;
|
// megafunction wizard: %ALTMULT_ADD%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: ALTMULT_ADD
// ============================================================
// File Name: sv_mult27.v
// Megafunction Name(s):
// ALTMULT_ADD
//
// Simulation Library Files(s):
// altera_lnsim
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.1 Build 177 11/07/2012 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//altmult_add ACCUM_SLOAD_REGISTER="UNREGISTERED" ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1="UNREGISTERED" ADDNSUB_MULTIPLIER_REGISTER1="CLOCK0" CBX_AUTO_BLACKBOX="ALL" COEF0_0=0 COEF0_1=0 COEF0_2=0 COEF0_3=0 COEF0_4=0 COEF0_5=0 COEF0_6=0 COEF0_7=0 COEF1_0=0 COEF1_1=0 COEF1_2=0 COEF1_3=0 COEF1_4=0 COEF1_5=0 COEF1_6=0 COEF1_7=0 COEF2_0=0 COEF2_1=0 COEF2_2=0 COEF2_3=0 COEF2_4=0 COEF2_5=0 COEF2_6=0 COEF2_7=0 COEF3_0=0 COEF3_1=0 COEF3_2=0 COEF3_3=0 COEF3_4=0 COEF3_5=0 COEF3_6=0 COEF3_7=0 COEFSEL0_REGISTER="UNREGISTERED" DEDICATED_MULTIPLIER_CIRCUITRY="AUTO" DEVICE_FAMILY="Stratix V" INPUT_REGISTER_A0="CLOCK0" INPUT_REGISTER_B0="CLOCK0" INPUT_REGISTER_C0="UNREGISTERED" INPUT_SOURCE_A0="DATAA" INPUT_SOURCE_B0="DATAB" LOADCONST_VALUE=64 MULTIPLIER1_DIRECTION="ADD" MULTIPLIER_REGISTER0="UNREGISTERED" NUMBER_OF_MULTIPLIERS=1 OUTPUT_REGISTER="CLOCK0" port_addnsub1="PORT_UNUSED" port_signa="PORT_UNUSED" port_signb="PORT_UNUSED" PREADDER_DIRECTION_0="ADD" PREADDER_DIRECTION_1="ADD" PREADDER_DIRECTION_2="ADD" PREADDER_DIRECTION_3="ADD" PREADDER_MODE="SIMPLE" REPRESENTATION_A="UNSIGNED" REPRESENTATION_B="UNSIGNED" SIGNED_PIPELINE_REGISTER_A="UNREGISTERED" SIGNED_PIPELINE_REGISTER_B="UNREGISTERED" SIGNED_REGISTER_A="CLOCK0" SIGNED_REGISTER_B="CLOCK0" SYSTOLIC_DELAY1="UNREGISTERED" SYSTOLIC_DELAY3="UNREGISTERED" WIDTH_A=27 WIDTH_B=27 WIDTH_RESULT=54 clock0 dataa datab result
//VERSION_BEGIN 12.1 cbx_alt_ded_mult_y 2012:11:07:18:03:20:SJ cbx_altera_mult_add 2012:11:07:18:03:20:SJ cbx_altmult_add 2012:11:07:18:03:20:SJ cbx_cycloneii 2012:11:07:18:03:20:SJ cbx_lpm_add_sub 2012:11:07:18:03:20:SJ cbx_lpm_mult 2012:11:07:18:03:20:SJ cbx_mgl 2012:11:07:18:50:05:SJ cbx_padd 2012:11:07:18:03:20:SJ cbx_parallel_add 2012:11:07:18:03:20:SJ cbx_stratix 2012:11:07:18:03:20:SJ cbx_stratixii 2012:11:07:18:03:20:SJ cbx_util_mgl 2012:11:07:18:03:20:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//synthesis_resources = altera_mult_add 1 dsp_mac 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module sv_mult27_mult_add_cfq3
(
clock0,
ena0,
dataa,
datab,
result) ;
input clock0;
input ena0;
input [26:0] dataa;
input [26:0] datab;
output [53:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock0;
tri0 [26:0] dataa;
tri0 [26:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [53:0] wire_altera_mult_add1_result;
wire ena1;
wire ena2;
wire ena3;
altera_mult_add altera_mult_add1
(
.chainout_sat_overflow(),
.clock0(clock0),
.dataa(dataa),
.datab(datab),
.ena0(ena0),
.ena1(ena1),
.ena2(ena2),
.ena3(ena3),
.mult0_is_saturated(),
.mult1_is_saturated(),
.mult2_is_saturated(),
.mult3_is_saturated(),
.overflow(),
.result(wire_altera_mult_add1_result),
.scanouta(),
.scanoutb(),
.accum_sload(1'b0),
.aclr0(1'b0),
.aclr1(1'b0),
.aclr2(1'b0),
.aclr3(1'b0),
.addnsub1(1'b1),
.addnsub1_round(1'b0),
.addnsub3(1'b1),
.addnsub3_round(1'b0),
.chainin({1{1'b0}}),
.chainout_round(1'b0),
.chainout_saturate(1'b0),
.clock1(1'b1),
.clock2(1'b1),
.clock3(1'b1),
.coefsel0({3{1'b0}}),
.coefsel1({3{1'b0}}),
.coefsel2({3{1'b0}}),
.coefsel3({3{1'b0}}),
.datac({22{1'b0}}),
.mult01_round(1'b0),
.mult01_saturation(1'b0),
.mult23_round(1'b0),
.mult23_saturation(1'b0),
.output_round(1'b0),
.output_saturate(1'b0),
.rotate(1'b0),
.scanina({27{1'b0}}),
.scaninb({27{1'b0}}),
.shift_right(1'b0),
.signa(1'b0),
.signb(1'b0),
.sourcea({1{1'b0}}),
.sourceb({1{1'b0}}),
.zero_chainout(1'b0),
.zero_loopback(1'b0)
);
defparam
altera_mult_add1.accum_direction = "ADD",
altera_mult_add1.accum_sload_aclr = "ACLR0",
altera_mult_add1.accum_sload_pipeline_aclr = "ACLR0",
altera_mult_add1.accum_sload_pipeline_register = "CLOCK0",
altera_mult_add1.accum_sload_register = "UNREGISTERED",
altera_mult_add1.accumulator = "NO",
altera_mult_add1.adder1_rounding = "NO",
altera_mult_add1.adder3_rounding = "NO",
altera_mult_add1.addnsub1_round_aclr = "ACLR0",
altera_mult_add1.addnsub1_round_pipeline_aclr = "ACLR0",
altera_mult_add1.addnsub1_round_pipeline_register = "CLOCK0",
altera_mult_add1.addnsub1_round_register = "CLOCK0",
altera_mult_add1.addnsub3_round_aclr = "ACLR0",
altera_mult_add1.addnsub3_round_pipeline_aclr = "ACLR0",
altera_mult_add1.addnsub3_round_pipeline_register = "CLOCK0",
altera_mult_add1.addnsub3_round_register = "CLOCK0",
altera_mult_add1.addnsub_multiplier_aclr1 = "ACLR0",
altera_mult_add1.addnsub_multiplier_aclr3 = "ACLR0",
altera_mult_add1.addnsub_multiplier_pipeline_aclr1 = "ACLR0",
altera_mult_add1.addnsub_multiplier_pipeline_aclr3 = "ACLR0",
altera_mult_add1.addnsub_multiplier_pipeline_register1 = "UNREGISTERED",
altera_mult_add1.addnsub_multiplier_pipeline_register3 = "CLOCK0",
altera_mult_add1.addnsub_multiplier_register1 = "CLOCK0",
altera_mult_add1.addnsub_multiplier_register3 = "CLOCK0",
altera_mult_add1.chainout_aclr = "ACLR0",
altera_mult_add1.chainout_adder = "NO",
altera_mult_add1.chainout_register = "CLOCK0",
altera_mult_add1.chainout_round_aclr = "ACLR0",
altera_mult_add1.chainout_round_output_aclr = "ACLR0",
altera_mult_add1.chainout_round_output_register = "CLOCK0",
altera_mult_add1.chainout_round_pipeline_aclr = "ACLR0",
altera_mult_add1.chainout_round_pipeline_register = "CLOCK0",
altera_mult_add1.chainout_round_register = "CLOCK0",
altera_mult_add1.chainout_rounding = "NO",
altera_mult_add1.chainout_saturate_aclr = "ACLR0",
altera_mult_add1.chainout_saturate_output_aclr = "ACLR0",
altera_mult_add1.chainout_saturate_output_register = "CLOCK0",
altera_mult_add1.chainout_saturate_pipeline_aclr = "ACLR0",
altera_mult_add1.chainout_saturate_pipeline_register = "CLOCK0",
altera_mult_add1.chainout_saturate_register = "CLOCK0",
altera_mult_add1.chainout_saturation = "NO",
altera_mult_add1.coef0_0 = 0,
altera_mult_add1.coef0_1 = 0,
altera_mult_add1.coef0_2 = 0,
altera_mult_add1.coef0_3 = 0,
altera_mult_add1.coef0_4 = 0,
altera_mult_add1.coef0_5 = 0,
altera_mult_add1.coef0_6 = 0,
altera_mult_add1.coef0_7 = 0,
altera_mult_add1.coef1_0 = 0,
altera_mult_add1.coef1_1 = 0,
altera_mult_add1.coef1_2 = 0,
altera_mult_add1.coef1_3 = 0,
altera_mult_add1.coef1_4 = 0,
altera_mult_add1.coef1_5 = 0,
altera_mult_add1.coef1_6 = 0,
altera_mult_add1.coef1_7 = 0,
altera_mult_add1.coef2_0 = 0,
altera_mult_add1.coef2_1 = 0,
altera_mult_add1.coef2_2 = 0,
altera_mult_add1.coef2_3 = 0,
altera_mult_add1.coef2_4 = 0,
altera_mult_add1.coef2_5 = 0,
altera_mult_add1.coef2_6 = 0,
altera_mult_add1.coef2_7 = 0,
altera_mult_add1.coef3_0 = 0,
altera_mult_add1.coef3_1 = 0,
altera_mult_add1.coef3_2 = 0,
altera_mult_add1.coef3_3 = 0,
altera_mult_add1.coef3_4 = 0,
altera_mult_add1.coef3_5 = 0,
altera_mult_add1.coef3_6 = 0,
altera_mult_add1.coef3_7 = 0,
altera_mult_add1.coefsel0_aclr = "ACLR0",
altera_mult_add1.coefsel0_register = "UNREGISTERED",
altera_mult_add1.coefsel1_aclr = "ACLR0",
altera_mult_add1.coefsel1_register = "CLOCK0",
altera_mult_add1.coefsel2_aclr = "ACLR0",
altera_mult_add1.coefsel2_register = "CLOCK0",
altera_mult_add1.coefsel3_aclr = "ACLR0",
altera_mult_add1.coefsel3_register = "CLOCK0",
altera_mult_add1.dedicated_multiplier_circuitry = "AUTO",
altera_mult_add1.double_accum = "NO",
altera_mult_add1.dsp_block_balancing = "Auto",
altera_mult_add1.extra_latency = 0,
altera_mult_add1.input_aclr_a0 = "ACLR0",
altera_mult_add1.input_aclr_a1 = "ACLR0",
altera_mult_add1.input_aclr_a2 = "ACLR0",
altera_mult_add1.input_aclr_a3 = "ACLR0",
altera_mult_add1.input_aclr_b0 = "ACLR0",
altera_mult_add1.input_aclr_b1 = "ACLR0",
altera_mult_add1.input_aclr_b2 = "ACLR0",
altera_mult_add1.input_aclr_b3 = "ACLR0",
altera_mult_add1.input_aclr_c0 = "ACLR0",
altera_mult_add1.input_aclr_c1 = "ACLR0",
altera_mult_add1.input_aclr_c2 = "ACLR0",
altera_mult_add1.input_aclr_c3 = "ACLR0",
altera_mult_add1.input_register_a0 = "CLOCK0",
altera_mult_add1.input_register_a1 = "CLOCK0",
altera_mult_add1.input_register_a2 = "CLOCK0",
altera_mult_add1.input_register_a3 = "CLOCK0",
altera_mult_add1.input_register_b0 = "CLOCK0",
altera_mult_add1.input_register_b1 = "CLOCK0",
altera_mult_add1.input_register_b2 = "CLOCK0",
altera_mult_add1.input_register_b3 = "CLOCK0",
altera_mult_add1.input_register_c0 = "UNREGISTERED",
altera_mult_add1.input_register_c1 = "CLOCK0",
altera_mult_add1.input_register_c2 = "CLOCK0",
altera_mult_add1.input_register_c3 = "CLOCK0",
altera_mult_add1.input_source_a0 = "DATAA",
altera_mult_add1.input_source_a1 = "DATAA",
altera_mult_add1.input_source_a2 = "DATAA",
altera_mult_add1.input_source_a3 = "DATAA",
altera_mult_add1.input_source_b0 = "DATAB",
altera_mult_add1.input_source_b1 = "DATAB",
altera_mult_add1.input_source_b2 = "DATAB",
altera_mult_add1.input_source_b3 = "DATAB",
altera_mult_add1.loadconst_control_aclr = "ACLR0",
altera_mult_add1.loadconst_control_register = "CLOCK0",
altera_mult_add1.loadconst_value = 64,
altera_mult_add1.mult01_round_aclr = "ACLR0",
altera_mult_add1.mult01_round_register = "CLOCK0",
altera_mult_add1.mult01_saturation_aclr = "ACLR1",
altera_mult_add1.mult01_saturation_register = "CLOCK0",
altera_mult_add1.mult23_round_aclr = "ACLR0",
altera_mult_add1.mult23_round_register = "CLOCK0",
altera_mult_add1.mult23_saturation_aclr = "ACLR0",
altera_mult_add1.mult23_saturation_register = "CLOCK0",
altera_mult_add1.multiplier01_rounding = "NO",
altera_mult_add1.multiplier01_saturation = "NO",
altera_mult_add1.multiplier1_direction = "ADD",
altera_mult_add1.multiplier23_rounding = "NO",
altera_mult_add1.multiplier23_saturation = "NO",
altera_mult_add1.multiplier3_direction = "ADD",
altera_mult_add1.multiplier_aclr0 = "ACLR0",
altera_mult_add1.multiplier_aclr1 = "ACLR0",
altera_mult_add1.multiplier_aclr2 = "ACLR0",
altera_mult_add1.multiplier_aclr3 = "ACLR0",
altera_mult_add1.multiplier_register0 = "UNREGISTERED",
altera_mult_add1.multiplier_register1 = "CLOCK0",
altera_mult_add1.multiplier_register2 = "CLOCK0",
altera_mult_add1.multiplier_register3 = "CLOCK0",
altera_mult_add1.number_of_multipliers = 1,
altera_mult_add1.output_aclr = "ACLR0",
altera_mult_add1.output_register = "CLOCK0",
altera_mult_add1.output_round_aclr = "ACLR0",
altera_mult_add1.output_round_pipeline_aclr = "ACLR0",
altera_mult_add1.output_round_pipeline_register = "CLOCK0",
altera_mult_add1.output_round_register = "CLOCK0",
altera_mult_add1.output_round_type = "NEAREST_INTEGER",
altera_mult_add1.output_rounding = "NO",
altera_mult_add1.output_saturate_aclr = "ACLR0",
altera_mult_add1.output_saturate_pipeline_aclr = "ACLR0",
altera_mult_add1.output_saturate_pipeline_register = "CLOCK0",
altera_mult_add1.output_saturate_register = "CLOCK0",
altera_mult_add1.output_saturate_type = "ASYMMETRIC",
altera_mult_add1.output_saturation = "NO",
altera_mult_add1.port_addnsub1 = "PORT_UNUSED",
altera_mult_add1.port_addnsub3 = "PORT_UNUSED",
altera_mult_add1.port_chainout_sat_is_overflow = "PORT_UNUSED",
altera_mult_add1.port_output_is_overflow = "PORT_UNUSED",
altera_mult_add1.port_signa = "PORT_UNUSED",
altera_mult_add1.port_signb = "PORT_UNUSED",
altera_mult_add1.preadder_direction_0 = "ADD",
altera_mult_add1.preadder_direction_1 = "ADD",
altera_mult_add1.preadder_direction_2 = "ADD",
altera_mult_add1.preadder_direction_3 = "ADD",
altera_mult_add1.preadder_mode = "SIMPLE",
altera_mult_add1.representation_a = "UNSIGNED",
altera_mult_add1.representation_b = "UNSIGNED",
altera_mult_add1.rotate_aclr = "ACLR0",
altera_mult_add1.rotate_output_aclr = "ACLR0",
altera_mult_add1.rotate_output_register = "CLOCK0",
altera_mult_add1.rotate_pipeline_aclr = "ACLR0",
altera_mult_add1.rotate_pipeline_register = "CLOCK0",
altera_mult_add1.rotate_register = "CLOCK0",
altera_mult_add1.scanouta_aclr = "ACLR0",
altera_mult_add1.scanouta_register = "UNREGISTERED",
altera_mult_add1.selected_device_family = "Stratix V",
altera_mult_add1.shift_mode = "NO",
altera_mult_add1.shift_right_aclr = "ACLR0",
altera_mult_add1.shift_right_output_aclr = "ACLR0",
altera_mult_add1.shift_right_output_register = "CLOCK0",
altera_mult_add1.shift_right_pipeline_aclr = "ACLR0",
altera_mult_add1.shift_right_pipeline_register = "CLOCK0",
altera_mult_add1.shift_right_register = "CLOCK0",
altera_mult_add1.signed_aclr_a = "ACLR0",
altera_mult_add1.signed_aclr_b = "ACLR0",
altera_mult_add1.signed_pipeline_aclr_a = "ACLR0",
altera_mult_add1.signed_pipeline_aclr_b = "ACLR0",
altera_mult_add1.signed_pipeline_register_a = "UNREGISTERED",
altera_mult_add1.signed_pipeline_register_b = "UNREGISTERED",
altera_mult_add1.signed_register_a = "CLOCK0",
altera_mult_add1.signed_register_b = "CLOCK0",
altera_mult_add1.systolic_aclr1 = "ACLR0",
altera_mult_add1.systolic_aclr3 = "ACLR0",
altera_mult_add1.systolic_delay1 = "UNREGISTERED",
altera_mult_add1.systolic_delay3 = "UNREGISTERED",
altera_mult_add1.width_a = 27,
altera_mult_add1.width_b = 27,
altera_mult_add1.width_c = 22,
altera_mult_add1.width_chainin = 1,
altera_mult_add1.width_coef = 18,
altera_mult_add1.width_msb = 17,
altera_mult_add1.width_result = 54,
altera_mult_add1.width_saturate_sign = 1,
altera_mult_add1.zero_chainout_output_aclr = "ACLR0",
altera_mult_add1.zero_chainout_output_register = "CLOCK0",
altera_mult_add1.zero_loopback_aclr = "ACLR0",
altera_mult_add1.zero_loopback_output_aclr = "ACLR0",
altera_mult_add1.zero_loopback_output_register = "CLOCK0",
altera_mult_add1.zero_loopback_pipeline_aclr = "ACLR0",
altera_mult_add1.zero_loopback_pipeline_register = "CLOCK0",
altera_mult_add1.zero_loopback_register = "CLOCK0",
altera_mult_add1.lpm_type = "altera_mult_add";
assign
ena1 = 1'b1,
ena2 = 1'b1,
ena3 = 1'b1,
result = wire_altera_mult_add1_result;
endmodule //sv_mult27_mult_add_cfq3
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module sv_mult27 (
clock0,
ena0,
dataa_0,
datab_0,
result);
input clock0;
input ena0;
input [26:0] dataa_0;
input [26:0] datab_0;
output [53:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock0;
tri0 [26:0] dataa_0;
tri0 [26:0] datab_0;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [53:0] sub_wire0;
wire [53:0] result = sub_wire0[53:0];
sv_mult27_mult_add_cfq3 sv_mult27_mult_add_cfq3_component (
.clock0 (clock0),
.ena0(ena0),
.dataa (dataa_0),
.datab (datab_0),
.result (sub_wire0));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACCUM_SLOAD_ACLR_SRC_MULT0 NUMERIC "3"
// Retrieval info: PRIVATE: ACCUM_SLOAD_CLK_SRC_MULT0 NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB1_ACLR_SRC NUMERIC "2"
// Retrieval info: PRIVATE: ADDNSUB1_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB1_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ADDNSUB1_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB1_PIPE_REG STRING "0"
// Retrieval info: PRIVATE: ADDNSUB1_REG STRING "1"
// Retrieval info: PRIVATE: ADDNSUB3_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ADDNSUB3_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB3_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: ADDNSUB3_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: ADDNSUB3_PIPE_REG STRING "0"
// Retrieval info: PRIVATE: ADDNSUB3_REG STRING "1"
// Retrieval info: PRIVATE: ADD_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: ALL_REG_ACLR NUMERIC "0"
// Retrieval info: PRIVATE: A_ACLR_SRC_MULT0 NUMERIC "2"
// Retrieval info: PRIVATE: A_CLK_SRC_MULT0 NUMERIC "0"
// Retrieval info: PRIVATE: B_ACLR_SRC_MULT0 NUMERIC "3"
// Retrieval info: PRIVATE: B_CLK_SRC_MULT0 NUMERIC "0"
// Retrieval info: PRIVATE: C_ACLR_SRC_MULT0 NUMERIC "3"
// Retrieval info: PRIVATE: C_CLK_SRC_MULT0 NUMERIC "0"
// Retrieval info: PRIVATE: ENABLE_PRELOAD_CONSTANT NUMERIC "0"
// Retrieval info: PRIVATE: HAS_MAC STRING "0"
// Retrieval info: PRIVATE: HAS_SAT_ROUND STRING "0"
// Retrieval info: PRIVATE: IMPL_STYLE_DEDICATED NUMERIC "0"
// Retrieval info: PRIVATE: IMPL_STYLE_DEFAULT NUMERIC "1"
// Retrieval info: PRIVATE: IMPL_STYLE_LCELL NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix V"
// Retrieval info: PRIVATE: MULT_COEFSEL STRING "0"
// Retrieval info: PRIVATE: MULT_REGA0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_REGB0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_REGC NUMERIC "0"
// Retrieval info: PRIVATE: MULT_REGOUT0 NUMERIC "0"
// Retrieval info: PRIVATE: MULT_REG_ACCUM_SLOAD NUMERIC "0"
// Retrieval info: PRIVATE: MULT_REG_SYSTOLIC_DELAY NUMERIC "0"
// Retrieval info: PRIVATE: NUM_MULT STRING "1"
// Retrieval info: PRIVATE: OP1 STRING "Add"
// Retrieval info: PRIVATE: OP3 STRING "Add"
// Retrieval info: PRIVATE: OUTPUT_EXTRA_LAT NUMERIC "0"
// Retrieval info: PRIVATE: OUTPUT_REG_ACLR_SRC NUMERIC "2"
// Retrieval info: PRIVATE: OUTPUT_REG_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: Q_ACLR_SRC_MULT0 NUMERIC "3"
// Retrieval info: PRIVATE: Q_CLK_SRC_MULT0 NUMERIC "0"
// Retrieval info: PRIVATE: REG_OUT NUMERIC "1"
// Retrieval info: PRIVATE: RNFORMAT STRING "54"
// Retrieval info: PRIVATE: RQFORMAT STRING "Q1.15"
// Retrieval info: PRIVATE: RTS_WIDTH STRING "54"
// Retrieval info: PRIVATE: SAME_CONFIG NUMERIC "1"
// Retrieval info: PRIVATE: SAME_CONTROL_SRC_A0 NUMERIC "1"
// Retrieval info: PRIVATE: SAME_CONTROL_SRC_B0 NUMERIC "1"
// Retrieval info: PRIVATE: SCANOUTA NUMERIC "0"
// Retrieval info: PRIVATE: SCANOUTB NUMERIC "0"
// Retrieval info: PRIVATE: SHIFTOUTA_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SHIFTOUTA_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SHIFTOUTA_REG STRING "0"
// Retrieval info: PRIVATE: SIGNA STRING "UNSIGNED"
// Retrieval info: PRIVATE: SIGNA_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SIGNA_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SIGNA_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SIGNA_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SIGNA_PIPE_REG STRING "0"
// Retrieval info: PRIVATE: SIGNA_REG STRING "1"
// Retrieval info: PRIVATE: SIGNB STRING "UNSIGNED"
// Retrieval info: PRIVATE: SIGNB_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SIGNB_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SIGNB_PIPE_ACLR_SRC NUMERIC "3"
// Retrieval info: PRIVATE: SIGNB_PIPE_CLK_SRC NUMERIC "0"
// Retrieval info: PRIVATE: SIGNB_PIPE_REG STRING "0"
// Retrieval info: PRIVATE: SIGNB_REG STRING "1"
// Retrieval info: PRIVATE: SRCA0 STRING "Multiplier input"
// Retrieval info: PRIVATE: SRCB0 STRING "Multiplier input"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SYSTOLIC_ACLR_SRC_MULT0 NUMERIC "3"
// Retrieval info: PRIVATE: SYSTOLIC_CLK_SRC_MULT0 NUMERIC "0"
// Retrieval info: PRIVATE: WIDTHA STRING "27"
// Retrieval info: PRIVATE: WIDTHB STRING "27"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ACCUM_SLOAD_REGISTER STRING "UNREGISTERED"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_ACLR1 STRING "UNUSED"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1 STRING "UNREGISTERED"
// Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_REGISTER1 STRING "CLOCK0"
// Retrieval info: CONSTANT: COEF0_0 NUMERIC "0"
// Retrieval info: CONSTANT: COEF0_1 NUMERIC "0"
// Retrieval info: CONSTANT: COEF0_2 NUMERIC "0"
// Retrieval info: CONSTANT: COEF0_3 NUMERIC "0"
// Retrieval info: CONSTANT: COEF0_4 NUMERIC "0"
// Retrieval info: CONSTANT: COEF0_5 NUMERIC "0"
// Retrieval info: CONSTANT: COEF0_6 NUMERIC "0"
// Retrieval info: CONSTANT: COEF0_7 NUMERIC "0"
// Retrieval info: CONSTANT: COEF1_0 NUMERIC "0"
// Retrieval info: CONSTANT: COEF1_1 NUMERIC "0"
// Retrieval info: CONSTANT: COEF1_2 NUMERIC "0"
// Retrieval info: CONSTANT: COEF1_3 NUMERIC "0"
// Retrieval info: CONSTANT: COEF1_4 NUMERIC "0"
// Retrieval info: CONSTANT: COEF1_5 NUMERIC "0"
// Retrieval info: CONSTANT: COEF1_6 NUMERIC "0"
// Retrieval info: CONSTANT: COEF1_7 NUMERIC "0"
// Retrieval info: CONSTANT: COEF2_0 NUMERIC "0"
// Retrieval info: CONSTANT: COEF2_1 NUMERIC "0"
// Retrieval info: CONSTANT: COEF2_2 NUMERIC "0"
// Retrieval info: CONSTANT: COEF2_3 NUMERIC "0"
// Retrieval info: CONSTANT: COEF2_4 NUMERIC "0"
// Retrieval info: CONSTANT: COEF2_5 NUMERIC "0"
// Retrieval info: CONSTANT: COEF2_6 NUMERIC "0"
// Retrieval info: CONSTANT: COEF2_7 NUMERIC "0"
// Retrieval info: CONSTANT: COEF3_0 NUMERIC "0"
// Retrieval info: CONSTANT: COEF3_1 NUMERIC "0"
// Retrieval info: CONSTANT: COEF3_2 NUMERIC "0"
// Retrieval info: CONSTANT: COEF3_3 NUMERIC "0"
// Retrieval info: CONSTANT: COEF3_4 NUMERIC "0"
// Retrieval info: CONSTANT: COEF3_5 NUMERIC "0"
// Retrieval info: CONSTANT: COEF3_6 NUMERIC "0"
// Retrieval info: CONSTANT: COEF3_7 NUMERIC "0"
// Retrieval info: CONSTANT: COEFSEL0_REGISTER STRING "UNREGISTERED"
// Retrieval info: CONSTANT: DEDICATED_MULTIPLIER_CIRCUITRY STRING "AUTO"
// Retrieval info: CONSTANT: INPUT_ACLR_A0 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_ACLR_B0 STRING "UNUSED"
// Retrieval info: CONSTANT: INPUT_REGISTER_A0 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_REGISTER_B0 STRING "CLOCK0"
// Retrieval info: CONSTANT: INPUT_REGISTER_C0 STRING "UNREGISTERED"
// Retrieval info: CONSTANT: INPUT_SOURCE_A0 STRING "DATAA"
// Retrieval info: CONSTANT: INPUT_SOURCE_B0 STRING "DATAB"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix V"
// Retrieval info: CONSTANT: LOADCONST_VALUE NUMERIC "64"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altmult_add"
// Retrieval info: CONSTANT: MULTIPLIER1_DIRECTION STRING "ADD"
// Retrieval info: CONSTANT: MULTIPLIER_ACLR0 STRING "UNUSED"
// Retrieval info: CONSTANT: MULTIPLIER_REGISTER0 STRING "UNREGISTERED"
// Retrieval info: CONSTANT: NUMBER_OF_MULTIPLIERS NUMERIC "1"
// Retrieval info: CONSTANT: OUTPUT_ACLR STRING "UNUSED"
// Retrieval info: CONSTANT: OUTPUT_REGISTER STRING "CLOCK0"
// Retrieval info: CONSTANT: PORT_ADDNSUB1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SIGNA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SIGNB STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PREADDER_DIRECTION_0 STRING "ADD"
// Retrieval info: CONSTANT: PREADDER_DIRECTION_1 STRING "ADD"
// Retrieval info: CONSTANT: PREADDER_DIRECTION_2 STRING "ADD"
// Retrieval info: CONSTANT: PREADDER_DIRECTION_3 STRING "ADD"
// Retrieval info: CONSTANT: PREADDER_MODE STRING "SIMPLE"
// Retrieval info: CONSTANT: REPRESENTATION_A STRING "UNSIGNED"
// Retrieval info: CONSTANT: REPRESENTATION_B STRING "UNSIGNED"
// Retrieval info: CONSTANT: SIGNED_ACLR_A STRING "UNUSED"
// Retrieval info: CONSTANT: SIGNED_ACLR_B STRING "UNUSED"
// Retrieval info: CONSTANT: SIGNED_PIPELINE_REGISTER_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: SIGNED_PIPELINE_REGISTER_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: SIGNED_REGISTER_A STRING "CLOCK0"
// Retrieval info: CONSTANT: SIGNED_REGISTER_B STRING "CLOCK0"
// Retrieval info: CONSTANT: SYSTOLIC_DELAY1 STRING "UNREGISTERED"
// Retrieval info: CONSTANT: SYSTOLIC_DELAY3 STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "27"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "27"
// Retrieval info: CONSTANT: WIDTH_RESULT NUMERIC "54"
// Retrieval info: USED_PORT: clock0 0 0 0 0 INPUT VCC "clock0"
// Retrieval info: USED_PORT: dataa_0 0 0 27 0 INPUT GND "dataa_0[26..0]"
// Retrieval info: USED_PORT: datab_0 0 0 27 0 INPUT GND "datab_0[26..0]"
// Retrieval info: USED_PORT: result 0 0 54 0 OUTPUT GND "result[53..0]"
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock0 0 0 0 0
// Retrieval info: CONNECT: @dataa 0 0 27 0 dataa_0 0 0 27 0
// Retrieval info: CONNECT: @datab 0 0 27 0 datab_0 0 0 27 0
// Retrieval info: CONNECT: result 0 0 54 0 @result 0 0 54 0
// Retrieval info: GEN_FILE: TYPE_NORMAL sv_mult27.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sv_mult27.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sv_mult27.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sv_mult27.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sv_mult27_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sv_mult27_bb.v TRUE
// Retrieval info: LIB_FILE: altera_lnsim
|
`timescale 1ns / 1ps
module arbiter(
// I-Port
input [63:0] idat_i,
input [63:0] iadr_i,
input iwe_i,
input icyc_i,
input istb_i,
input [1:0] isiz_i,
input isigned_i,
output iack_o,
output [63:0] idat_o,
// D-Port
input [63:0] ddat_i,
input [63:0] dadr_i,
input dwe_i,
input dcyc_i,
input dstb_i,
input [1:0] dsiz_i,
input dsigned_i,
output dack_o,
output [63:0] ddat_o,
// X-Port
output [63:0] xdat_o,
output [63:0] xadr_o,
output xwe_o,
output xcyc_o,
output xstb_o,
output [1:0] xsiz_o,
output xsigned_o,
input xack_i,
input [63:0] xdat_i,
// Miscellaneous
input clk_i,
input reset_i
);
reg reserve_i, reserve_d;
wire en_i = (~reset_i & icyc_i & ~dcyc_i) |
(~reset_i & icyc_i & dcyc_i & reserve_i & ~reserve_d);
wire en_d = (~reset_i & ~icyc_i & dcyc_i) |
(~reset_i & icyc_i & dcyc_i & ~reserve_i) |
(~reset_i & icyc_i & dcyc_i & reserve_i & reserve_d);
assign xdat_o = (en_i ? idat_i : 64'd0) | (en_d ? ddat_i : 64'd0);
assign xadr_o = (en_i ? iadr_i : 64'd0) | (en_d ? dadr_i : 64'd0);
assign xwe_o = (en_i & iwe_i) | (en_d & dwe_i);
assign xcyc_o = (en_i & icyc_i) | (en_d & dcyc_i);
assign xstb_o = (en_i & istb_i) | (en_d & dstb_i);
assign xsiz_o = (en_i ? isiz_i : 2'd0) | (en_d ? dsiz_i : 2'd0);
assign xsigned_o = (en_i & isigned_i) | (en_d & dsigned_i);
assign iack_o = (en_i & xack_i);
assign dack_o = (en_d & xack_i);
assign idat_o = (en_i ? xdat_i : 64'd0);
assign ddat_o = (en_d ? xdat_i : 64'd0);
always @(posedge clk_i) begin
reserve_i <= en_i;
reserve_d <= en_d;
end
endmodule
|
//Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2015.4 (win64) Build 1412921 Wed Nov 18 09:43:45 MST 2015
//Date : Tue Feb 02 21:37:26 2016
//Host : running 64-bit Service Pack 1 (build 7601)
//Command : generate_target zc702_wrapper.bd
//Design : zc702_wrapper
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module zc702_wrapper
(DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb);
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
wire [14:0]DDR_addr;
wire [2:0]DDR_ba;
wire DDR_cas_n;
wire DDR_ck_n;
wire DDR_ck_p;
wire DDR_cke;
wire DDR_cs_n;
wire [3:0]DDR_dm;
wire [31:0]DDR_dq;
wire [3:0]DDR_dqs_n;
wire [3:0]DDR_dqs_p;
wire DDR_odt;
wire DDR_ras_n;
wire DDR_reset_n;
wire DDR_we_n;
wire FIXED_IO_ddr_vrn;
wire FIXED_IO_ddr_vrp;
wire [53:0]FIXED_IO_mio;
wire FIXED_IO_ps_clk;
wire FIXED_IO_ps_porb;
wire FIXED_IO_ps_srstb;
zc702 zc702_i
(.DDR_addr(DDR_addr),
.DDR_ba(DDR_ba),
.DDR_cas_n(DDR_cas_n),
.DDR_ck_n(DDR_ck_n),
.DDR_ck_p(DDR_ck_p),
.DDR_cke(DDR_cke),
.DDR_cs_n(DDR_cs_n),
.DDR_dm(DDR_dm),
.DDR_dq(DDR_dq),
.DDR_dqs_n(DDR_dqs_n),
.DDR_dqs_p(DDR_dqs_p),
.DDR_odt(DDR_odt),
.DDR_ras_n(DDR_ras_n),
.DDR_reset_n(DDR_reset_n),
.DDR_we_n(DDR_we_n),
.FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
.FIXED_IO_mio(FIXED_IO_mio),
.FIXED_IO_ps_clk(FIXED_IO_ps_clk),
.FIXED_IO_ps_porb(FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb(FIXED_IO_ps_srstb));
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2012 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
bit a_finished;
bit b_finished;
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
wire [31:0] o;
wire si = 1'b0;
ExampInst i
(// Outputs
.o (o[31:0]),
// Inputs
.i (1'b0)
/*AUTOINST*/);
Prog p (/*AUTOINST*/
// Inputs
.si (si));
always @ (posedge clk) begin
if (!a_finished) $stop;
if (!b_finished) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
module InstModule (
output logic [31:0] so,
input si
);
assign so = {32{si}};
endmodule
program Prog (input si);
initial a_finished = 1'b1;
endprogram
module ExampInst (o,i);
output logic [31:0] o;
input i;
InstModule instName
(// Outputs
.so (o[31:0]),
// Inputs
.si (i)
/*AUTOINST*/);
//bind InstModule Prog instProg
// (.si(si));
// Note is based on context of caller
bind InstModule Prog instProg
(/*AUTOBIND*/
.si (si));
endmodule
// Check bind at top level
bind InstModule Prog2 instProg2
(/*AUTOBIND*/
.si (si));
// Check program declared after bind
program Prog2 (input si);
initial b_finished = 1'b1;
endprogram
|
/*!
btcminer -- BTCMiner for ZTEX USB-FPGA Modules: HDL code for ZTEX USB-FPGA Module 1.15b (one double hash pipe)
Copyright (C) 2012 ZTEX GmbH
http://www.ztex.de
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License version 3 as
published by the Free Software Foundation.
This program is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, see http://www.gnu.org/licenses/.
!*/
module ztex_ufm1_15y1 (fxclk_in, reset, select, clk_reset, pll_stop, dcm_progclk, dcm_progdata, dcm_progen, rd_clk, wr_clk, wr_start, read, write);
input fxclk_in, select, reset, clk_reset, pll_stop, dcm_progclk, dcm_progdata, dcm_progen, rd_clk, wr_clk, wr_start;
input [7:0] read;
output [7:0] write;
function integer clog2; // Courtesy of razorfishsl, replaces $clog2()
input integer value;
begin
value = value-1;
for (clog2=0; value>0; clog2=clog2+1)
value = value>>1;
end
endfunction
// Configure cores here since using `ifdef rather than generate (lazy)
//`define DUALCORE // Comment out for single core (actually performs better)
//`define PROTOCOL80 // Select 80 or 76 byte protocol (NB use 76 for current cgminer)
`ifdef DUALCORE
localparam LOCAL_MINERS = 2; // One or two cores (configures ADDRBITS automatically)
`else
localparam LOCAL_MINERS = 1; // One or two cores (configures ADDRBITS automatically)
`endif
localparam ADDRBITS = 12 - clog2(LOCAL_MINERS); // Automatically selects largest RAM that will fit LX150
localparam SBITS = 8; // Shift data path width
`ifdef DUALCORE
reg phase = 1'b0;
`endif
reg [3:0] rd_clk_b, wr_clk_b;
reg wr_start_b1 = 0, wr_start_b2 = 0, reset_buf = 0, reset_buf_d = 0, clk_reset_buf = 1, pll_stop_buf = 1, select_buf = 0;
reg dcm_progclk_buf, dcm_progdata_buf, dcm_progen_buf;
reg [4:0] wr_delay;
reg [127:0] outbuf;
reg [7:0] read_buf, write_buf;
reg [31:0] golden_nonce_a = 32'd0, golden_nonce_b = 32'd0;
wire fxclk, clk, dcm_clk, pll_fb, pll_clk0, dcm_locked, pll_reset;
wire [2:1] dcm_status;
wire [31:0] golden_nonce_1, hash_1;
wire [31:0] golden_nonce_2, hash_2;
wire [31:0] golden_nonce, nonce_a, hash_a;
wire gn_match_1, gn_match_2;
`define NOPLL // PLL does not route so workaround uses DCM only
`ifndef SIM
IBUFG bufg_fxclk (
.I(fxclk_in),
.O(fxclk)
);
`ifndef NOPLL
BUFG bufg_clk (
.I(pll_clk0),
.O(clk)
);
`else
BUFGCE bufg_clk (
.I(dcm_clk),
.CE(~pll_reset),
.O(clk)
);
`endif
DCM_CLKGEN #(
.CLKFX_DIVIDE(4),
.CLKFX_MULTIPLY(16), // Will be 32 or higher when set dynamically
// .CLKFXDV_DIVIDE(8), // NB using CLKFXDV output (original version up to v03)
.CLKFXDV_DIVIDE(4), // Single core can run faster, but firmware limit is 248Mhz so double it at v04
// CARE cgminer clock now needs to be 124MHz or thereabouts instead of 248MHz
.CLKIN_PERIOD(20.8333) // 48MHz input
)
dcm0 (
.CLKIN(fxclk),
.CLKFXDV(dcm_clk),
.FREEZEDCM(1'b0),
.PROGCLK(dcm_progclk_buf),
.PROGDATA(dcm_progdata_buf),
.PROGEN(dcm_progen_buf),
.LOCKED(dcm_locked),
.STATUS(dcm_status),
.RST(clk_reset_buf)
);
`ifndef NOPLL
PLL_BASE #(
.BANDWIDTH("LOW"),
.CLKFBOUT_MULT(4),
.CLKOUT0_DIVIDE(4),
.CLKOUT0_DUTY_CYCLE(0.5),
.CLK_FEEDBACK("CLKFBOUT"),
.COMPENSATION("INTERNAL"),
.DIVCLK_DIVIDE(1),
.REF_JITTER(0.10),
.CLKIN_PERIOD(5.2), // Needed since UCF now constrains clk rather than fxclk
.RESET_ON_LOSS_OF_LOCK("FALSE")
)
pll0 (
.CLKFBOUT(pll_fb),
.CLKOUT0(pll_clk0),
.CLKFBIN(pll_fb),
.CLKIN(dcm_clk),
.RST(pll_reset)
);
`endif
`else
assign clk = fxclk_in; // SIM
`endif
assign write = select ? write_buf : 8'bz; // This actually does tristate the outputs
assign pll_reset = pll_stop_buf | ~dcm_locked | clk_reset_buf | dcm_status[2];
`ifdef SIM
// Test hash - final hash at 672,780ns
`ifdef PROTOCOL80
// 80 byte protocol includes nonce
reg [639:0] inbuf_tmp = {
128'h0000318f7e71441b141fe951b2b0c7df,
256'hc791d4646240fc2a2d1b80900020a24dc501ef1599fc48ed6cbac920af755756,
256'h18e7b1e8eaf0b62a90d1942ea64d250357e9a09c063a47827c57b44e01000000
};
`else
// 76 byte protocol excludes nonce
reg [607:0] inbuf_tmp = {
96'h7e71441b141fe951b2b0c7df,
256'hc791d4646240fc2a2d1b80900020a24dc501ef1599fc48ed6cbac920af755756,
256'h18e7b1e8eaf0b62a90d1942ea64d250357e9a09c063a47827c57b44e01000000
};
`endif
`else // SIM
`ifdef PROTOCOL80
reg [639:0] inbuf_tmp;
`else
reg [639:0] inbuf_tmp;
`endif
`endif // SIM
`ifdef PROTOCOL80
reg [639:0] inbuf; // 80 byte protocol
`else
reg [607:0] inbuf; // 76 byte protocol
`endif
wire [31:0] mod_target = 32'h00007fff; // Hard coded for diff=2
wire [255:0] data1 = inbuf[255:0];
wire [255:0] data2 = inbuf[511:256];
`ifdef PROTOCOL80
wire [127:0] data3 = inbuf[639:512];
`else
`ifdef SIM
wire [127:0] data3 = { 32'h0000318f, inbuf[607:512] };
`else
wire [127:0] data3 = { 32'd0, inbuf[607:512] };
`endif
`endif
// Generate loadnonce strobe for new work (NB this initiates a full engine reset)
reg loadnonce = 1'b0; // Strobe generated loading work
reg loadnonce_d = 1'b0; // Delay by one since extra register stage inbuf
// NB For now using same clk for both P and S
wire [31:0] nonce_out_1;
wire salsa_busy_1, salsa_result_1, salsa_reset_1, salsa_start_1, salsa_shift_1;
wire [SBITS-1:0] salsa_din_1;
wire [SBITS-1:0] salsa_dout_1;
pbkdfengine #(.SBITS(SBITS)) P1
(.hash_clk(clk), .pbkdf_clk(clk), .data1(data1), .data2(data2), .data3(data3), .target(mod_target),
.nonce_msb( 4'd0 ), .nonce_out(nonce_out_1), .golden_nonce_out(golden_nonce_1),
.golden_nonce_match(gn_match_1), .loadnonce(loadnonce_d),
.salsa_din(salsa_din_1), .salsa_dout(salsa_dout_1), .salsa_busy(salsa_busy_1), .salsa_result(salsa_result_1),
.salsa_reset(salsa_reset_1), .salsa_start(salsa_start_1), .salsa_shift(salsa_shift_1), .hash_out(hash_1));
salsaengine #(.ADDRBITS(ADDRBITS), .SBITS(SBITS)) S1
(.hash_clk(clk), .reset(salsa_reset_1), .din(salsa_din_1), .dout(salsa_dout_1),
.shift(salsa_shift_1), .start(salsa_start_1), .busy(salsa_busy_1), .result(salsa_result_1) );
`ifdef DUALCORE
wire [31:0] nonce_out_2;
wire salsa_busy_2, salsa_result_2, salsa_reset_2, salsa_start_2, salsa_shift_2;
wire [SBITS-1:0] salsa_din_2;
wire [SBITS-1:0] salsa_dout_2;
pbkdfengine #(.SBITS(SBITS)) P2
(.hash_clk(clk), .pbkdf_clk(clk), .data1(data1), .data2(data2), .data3(data3), .target(mod_target),
.nonce_msb( 4'd8 ), .nonce_out(nonce_out_2), .golden_nonce_out(golden_nonce_2),
.golden_nonce_match(gn_match_2), .loadnonce(loadnonce_d),
.salsa_din(salsa_din_2), .salsa_dout(salsa_dout_2), .salsa_busy(salsa_busy_2), .salsa_result(salsa_result_2),
.salsa_reset(salsa_reset_2), .salsa_start(salsa_start_2), .salsa_shift(salsa_shift_2), .hash_out(hash_2));
salsaengine #(.ADDRBITS(ADDRBITS), .SBITS(SBITS)) S2
(.hash_clk(clk), .reset(salsa_reset_2), .din(salsa_din_2), .dout(salsa_dout_2),
.shift(salsa_shift_2), .start(salsa_start_2), .busy(salsa_busy_2), .result(salsa_result_2) );
// Need to alternate between cores to ensure HW error monitoring works correctly in driver_ztex
// Phase toggles on reset which occurs prior to each new work
assign nonce_a = phase ? nonce_out_2 : nonce_out_1;
assign hash_a = phase ? hash_2 : hash_1;
assign gn_match = gn_match_1 | gn_match_2;
assign golden_nonce = gn_match_1 ? golden_nonce_1 : golden_nonce_2;
`else
// Single core
assign nonce_a = nonce_out_1;
assign hash_a = hash_1;
assign gn_match = gn_match_1;
assign golden_nonce = golden_nonce_1;
`endif
always @ (posedge clk)
begin
loadnonce <= 1'b0; // For pbkdfengine
loadnonce_d <= loadnonce; // Delay by one since extra register stage inbuf
// KRAMBLE not sure I understand this, it does not seem to be conventional clock-crossing as the comparison is the wrong
// end of the shift register, so perhaps its a de-bounce on the rd_clk (which is sort of clock-crossing too) ??
if ( (rd_clk_b[3] == rd_clk_b[2]) && (rd_clk_b[2] == rd_clk_b[1]) && (rd_clk_b[1] != rd_clk_b[0]) && select_buf )
begin
`ifdef PROTOCOL80
inbuf_tmp[639:632] <= read_buf;
inbuf_tmp[631:0] <= inbuf_tmp[639:8];
`else
inbuf_tmp[607:600] <= read_buf;
inbuf_tmp[599:0] <= inbuf_tmp[607:8];
`endif
// Nonce will be loaded (or reset to 0 in 76 byte protocol) every byte since there is no signal
// that indicates when work is completely loaded (this means hashes generated during loading
// are invalid, so we also reset golden_nonce_a/b below)
loadnonce <= 1'b1; // For pbkdfengine (single clock cycle strobe)
end
inbuf <= inbuf_tmp; // due to TIG's
if ( wr_start_b1 && wr_start_b2 )
begin
wr_delay <= 5'd0;
end else
begin
wr_delay[0] <= 1'b1;
wr_delay[4:1] <= wr_delay[3:0];
end
if ( ! wr_delay[4] )
begin
outbuf <= { golden_nonce_b, hash_a, nonce_a, golden_nonce_a };
end else
begin
// KRAMBLE see note above for rd_clk
if ( (wr_clk_b[3] == wr_clk_b[2]) && (wr_clk_b[2] == wr_clk_b[1]) && (wr_clk_b[1] != wr_clk_b[0]) )
outbuf[119:0] <= outbuf[127:8];
end
if ( reset_buf | loadnonce ) // Also reset on loadnonce since hashes are invalid
begin
golden_nonce_a <= 32'd0;
golden_nonce_b <= 32'd0;
end else if ( gn_match )
begin
golden_nonce_b <= golden_nonce_a;
golden_nonce_a <= golden_nonce;
end
read_buf <= read;
write_buf <= outbuf[7:0];
rd_clk_b[0] <= rd_clk;
rd_clk_b[3:1] <= rd_clk_b[2:0];
wr_clk_b[0] <= wr_clk;
wr_clk_b[3:1] <= wr_clk_b[2:0];
wr_start_b1 <= wr_start;
wr_start_b2 <= wr_start_b1;
select_buf <= select;
if ( select )
begin
reset_buf <= reset;
end
reset_buf_d <= reset_buf;
if (reset_buf_d & ~reset_buf) // Executes on trailing edge of reset
begin
`ifdef DUALCORE
phase <= ~phase;
`endif
end
end
always @ (posedge fxclk)
begin
dcm_progclk_buf <= dcm_progclk;
dcm_progdata_buf <= dcm_progdata;
dcm_progen_buf <= dcm_progen & select;
if ( select )
begin
clk_reset_buf <= clk_reset;
pll_stop_buf <= pll_stop;
end
end
endmodule
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog-2001
`resetall
`timescale 1 ns / 1 ps
`default_nettype none
/*
* Synchronizes an asyncronous signal to a given clock by using a pipeline of
* two registers.
*/
module sync_signal #(
parameter WIDTH=1, // width of the input and output signals
parameter N=2 // depth of synchronizer
)(
input wire clk,
input wire [WIDTH-1:0] in,
output wire [WIDTH-1:0] out
);
reg [WIDTH-1:0] sync_reg[N-1:0];
/*
* The synchronized output is the last register in the pipeline.
*/
assign out = sync_reg[N-1];
integer k;
always @(posedge clk) begin
sync_reg[0] <= in;
for (k = 1; k < N; k = k + 1) begin
sync_reg[k] <= sync_reg[k-1];
end
end
endmodule
`resetall
|
// DESCRIPTION: Verilator: Verilog Test module
//
// A test of the export parameter used with modport
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2013 by Jeremy Bennett.
interface test_if;
// Pre-declare function
extern function myfunc (input logic val);
// Interface variable
logic data;
// Modport
modport mp_e(
export myfunc,
output data
);
// Modport
modport mp_i(
import myfunc,
output data
);
endinterface // test_if
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
test_if i ();
testmod_callee testmod_callee_i (.ie (i.mp_e));
testmod_caller testmod_caller_i (.clk (clk),
.ii (i.mp_i));
endmodule
module testmod_callee
(
test_if.mp_e ie
);
function automatic logic ie.myfunc (input logic val);
begin
myfunc = (val == 1'b0);
end
endfunction
endmodule // testmod_caller
module testmod_caller
(
input clk,
test_if.mp_i ii
);
always @(posedge clk) begin
ii.data = 1'b0;
if (ii.myfunc (1'b0)) begin
$write("*-* All Finished *-*\n");
$finish;
end
else begin
$stop;
end
end
endmodule
|
//***************************************************--
//
// COPYRIGHT (C) 2011, VIPcore Group, Fudan UniYVERsity
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact : [email protected]
//*****************************************************
// Filename : db_controller.v
// AutYHOR : Chewein
// Created : 2014-04-18
// Description : generate the top controller signals
//*****************************************************
module db_controller(
clk ,
rst_n ,
start_i ,
//output
done_o ,
cnt_r ,
state
);
//***********************************************************************************************************************************************
//
// INPUT / OUTPUT DECLARATION
//
//***********************************************************************************************************************************************
input clk ;
input rst_n ;
input start_i ;
output reg done_o ;
output reg [8:0] cnt_r ;
output reg [2:0] state ;
//***********************************************************************************************************************************************
//
// TOP Controller signals
//
//***********************************************************************************************************************************************
parameter IDLE = 3'b000, LOAD = 3'b001, YVER = 3'b011,YHOR =3'b010;
parameter CVER = 3'b110, CHOR = 3'b111, OUTLT = 3'b101,OUT =3'b100;
reg [2:0] next ;
reg [8:0] cycles ;
reg isluma ;
reg isver ;
always@* begin
case(state)
LOAD :cycles = 'd384 ;
YVER :cycles = 'd132 ;
YHOR :cycles = 'd140 ;
CVER :cycles = 'd68 ;
CHOR :cycles = 'd76 ;
OUTLT :cycles = 'd67 ;
OUT :cycles = 'd384 ;
default :cycles = 'd0 ;
endcase
end
always @(posedge clk or negedge rst_n) begin
if(!(rst_n))
cnt_r <= 8'd0;
else if(!state)
cnt_r <= 8'd0;
else if(cnt_r == cycles)
cnt_r <= 8'd0;
else
cnt_r <= cnt_r + 1'b1;
end
always @* begin
case(state)
IDLE:begin
if(start_i)
next = LOAD ;
else
next = IDLE ;
end
LOAD:begin
if(cnt_r == cycles)
next = YVER ;
else
next = LOAD ;
end
YVER:begin
if(cnt_r == cycles)
next = YHOR ;
else
next = YVER ;
end
YHOR:begin
if(cnt_r == cycles)
next = CVER ;
else
next = YHOR ;
end
CVER:begin
if(cnt_r == cycles)
next = CHOR ;
else
next = CVER ;
end
CHOR:begin
if(cnt_r == cycles)
next = OUTLT ;
else
next = CHOR ;
end
OUTLT:begin
if(cnt_r == cycles)
next = OUT ;
else
next = OUTLT ;
end
OUT:begin
if(cnt_r == cycles)
next = IDLE ;
else
next = OUT ;
end
endcase
end
always @(posedge clk or negedge rst_n)begin
if(!rst_n)
state <= IDLE ;
else
state <= next ;
end
wire done_w = (state==OUT)?1'b1:1'b0;
always@(posedge clk or negedge rst_n)begin
if(!rst_n)
done_o <= 1'b0 ;
else if(next==IDLE)
done_o <= done_w ;
else
done_o <= 1'b0 ;
end
always @* begin
case(state)
YVER,
YHOR:isluma = 1'b1;
default:isluma = 1'b0;
endcase
end
always @* begin
case(state)
YVER,
CVER:isver = 1'b1;
default:isver = 1'b0;
endcase
end
endmodule |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:36:03 05/26/2014
// Design Name: mccomp
// Module Name: E:/3120101980/muti_cpu/test.v
// Project Name: muti_cpu
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: mccomp
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test;
// Inputs
reg clock;
reg resetn;
reg mem_clk;
// Outputs
wire [2:0] q;
wire [31:0] a;
wire [31:0] b;
wire [31:0] alu;
wire [31:0] adr;
wire [31:0] tom;
wire [31:0] fromm;
wire [31:0] pc;
wire [31:0] ir;
// Instantiate the Unit Under Test (UUT)
mccomp uut (
.clock(clock),
.resetn(resetn),
.q(q),
.a(a),
.b(b),
.alu(alu),
.adr(adr),
.tom(tom),
.fromm(fromm),
.pc(pc),
.ir(ir),
.mem_clk(mem_clk)
);
initial begin
// Initialize Inputs
clock = 0;
resetn = 0;
mem_clk = 0;
// Wait 100 ns for global reset to finish
#11; resetn = 1;
// Add stimulus here
end
initial forever begin
#1; mem_clk=~mem_clk;
#1; mem_clk=~mem_clk;clock=~clock;
end
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized COMPARATOR with generic_baseblocks_v2_1_0_carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_0_comparator #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] B,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar bit_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 3;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = B;
end
// Instantiate one generic_baseblocks_v2_1_0_carry and per level.
for (bit_cnt = 0; bit_cnt < C_NUM_LUT ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[bit_cnt] = ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] );
// Instantiate each LUT level.
generic_baseblocks_v2_1_0_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[bit_cnt+1]),
.CIN (carry_local[bit_cnt]),
.S (sel[bit_cnt])
);
end // end for bit_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule
|
// Quick negation of single-precision floating-point number
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_fp_negate
#(
// Bit width of a single precision float
parameter WIDTH=32
)
(
input [WIDTH-1:0] data,
output [WIDTH-1:0] result
);
// Negating the most-significant bit
assign result = { ~data[WIDTH-1], data[WIDTH-2:0] };
endmodule
|
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
module sirv_gpio(
input clock,
input reset,
output io_interrupts_0_0,
output io_interrupts_0_1,
output io_interrupts_0_2,
output io_interrupts_0_3,
output io_interrupts_0_4,
output io_interrupts_0_5,
output io_interrupts_0_6,
output io_interrupts_0_7,
output io_interrupts_0_8,
output io_interrupts_0_9,
output io_interrupts_0_10,
output io_interrupts_0_11,
output io_interrupts_0_12,
output io_interrupts_0_13,
output io_interrupts_0_14,
output io_interrupts_0_15,
output io_interrupts_0_16,
output io_interrupts_0_17,
output io_interrupts_0_18,
output io_interrupts_0_19,
output io_interrupts_0_20,
output io_interrupts_0_21,
output io_interrupts_0_22,
output io_interrupts_0_23,
output io_interrupts_0_24,
output io_interrupts_0_25,
output io_interrupts_0_26,
output io_interrupts_0_27,
output io_interrupts_0_28,
output io_interrupts_0_29,
output io_interrupts_0_30,
output io_interrupts_0_31,
output io_in_0_a_ready,
input io_in_0_a_valid,
input [2:0] io_in_0_a_bits_opcode,
input [2:0] io_in_0_a_bits_param,
input [2:0] io_in_0_a_bits_size,
input [4:0] io_in_0_a_bits_source,
input [28:0] io_in_0_a_bits_address,
input [3:0] io_in_0_a_bits_mask,
input [31:0] io_in_0_a_bits_data,
input io_in_0_b_ready,
output io_in_0_b_valid,
output [2:0] io_in_0_b_bits_opcode,
output [1:0] io_in_0_b_bits_param,
output [2:0] io_in_0_b_bits_size,
output [4:0] io_in_0_b_bits_source,
output [28:0] io_in_0_b_bits_address,
output [3:0] io_in_0_b_bits_mask,
output [31:0] io_in_0_b_bits_data,
output io_in_0_c_ready,
input io_in_0_c_valid,
input [2:0] io_in_0_c_bits_opcode,
input [2:0] io_in_0_c_bits_param,
input [2:0] io_in_0_c_bits_size,
input [4:0] io_in_0_c_bits_source,
input [28:0] io_in_0_c_bits_address,
input [31:0] io_in_0_c_bits_data,
input io_in_0_c_bits_error,
input io_in_0_d_ready,
output io_in_0_d_valid,
output [2:0] io_in_0_d_bits_opcode,
output [1:0] io_in_0_d_bits_param,
output [2:0] io_in_0_d_bits_size,
output [4:0] io_in_0_d_bits_source,
output io_in_0_d_bits_sink,
output [1:0] io_in_0_d_bits_addr_lo,
output [31:0] io_in_0_d_bits_data,
output io_in_0_d_bits_error,
output io_in_0_e_ready,
input io_in_0_e_valid,
input io_in_0_e_bits_sink,
input io_port_pins_0_i_ival,
output io_port_pins_0_o_oval,
output io_port_pins_0_o_oe,
output io_port_pins_0_o_ie,
output io_port_pins_0_o_pue,
output io_port_pins_0_o_ds,
input io_port_pins_1_i_ival,
output io_port_pins_1_o_oval,
output io_port_pins_1_o_oe,
output io_port_pins_1_o_ie,
output io_port_pins_1_o_pue,
output io_port_pins_1_o_ds,
input io_port_pins_2_i_ival,
output io_port_pins_2_o_oval,
output io_port_pins_2_o_oe,
output io_port_pins_2_o_ie,
output io_port_pins_2_o_pue,
output io_port_pins_2_o_ds,
input io_port_pins_3_i_ival,
output io_port_pins_3_o_oval,
output io_port_pins_3_o_oe,
output io_port_pins_3_o_ie,
output io_port_pins_3_o_pue,
output io_port_pins_3_o_ds,
input io_port_pins_4_i_ival,
output io_port_pins_4_o_oval,
output io_port_pins_4_o_oe,
output io_port_pins_4_o_ie,
output io_port_pins_4_o_pue,
output io_port_pins_4_o_ds,
input io_port_pins_5_i_ival,
output io_port_pins_5_o_oval,
output io_port_pins_5_o_oe,
output io_port_pins_5_o_ie,
output io_port_pins_5_o_pue,
output io_port_pins_5_o_ds,
input io_port_pins_6_i_ival,
output io_port_pins_6_o_oval,
output io_port_pins_6_o_oe,
output io_port_pins_6_o_ie,
output io_port_pins_6_o_pue,
output io_port_pins_6_o_ds,
input io_port_pins_7_i_ival,
output io_port_pins_7_o_oval,
output io_port_pins_7_o_oe,
output io_port_pins_7_o_ie,
output io_port_pins_7_o_pue,
output io_port_pins_7_o_ds,
input io_port_pins_8_i_ival,
output io_port_pins_8_o_oval,
output io_port_pins_8_o_oe,
output io_port_pins_8_o_ie,
output io_port_pins_8_o_pue,
output io_port_pins_8_o_ds,
input io_port_pins_9_i_ival,
output io_port_pins_9_o_oval,
output io_port_pins_9_o_oe,
output io_port_pins_9_o_ie,
output io_port_pins_9_o_pue,
output io_port_pins_9_o_ds,
input io_port_pins_10_i_ival,
output io_port_pins_10_o_oval,
output io_port_pins_10_o_oe,
output io_port_pins_10_o_ie,
output io_port_pins_10_o_pue,
output io_port_pins_10_o_ds,
input io_port_pins_11_i_ival,
output io_port_pins_11_o_oval,
output io_port_pins_11_o_oe,
output io_port_pins_11_o_ie,
output io_port_pins_11_o_pue,
output io_port_pins_11_o_ds,
input io_port_pins_12_i_ival,
output io_port_pins_12_o_oval,
output io_port_pins_12_o_oe,
output io_port_pins_12_o_ie,
output io_port_pins_12_o_pue,
output io_port_pins_12_o_ds,
input io_port_pins_13_i_ival,
output io_port_pins_13_o_oval,
output io_port_pins_13_o_oe,
output io_port_pins_13_o_ie,
output io_port_pins_13_o_pue,
output io_port_pins_13_o_ds,
input io_port_pins_14_i_ival,
output io_port_pins_14_o_oval,
output io_port_pins_14_o_oe,
output io_port_pins_14_o_ie,
output io_port_pins_14_o_pue,
output io_port_pins_14_o_ds,
input io_port_pins_15_i_ival,
output io_port_pins_15_o_oval,
output io_port_pins_15_o_oe,
output io_port_pins_15_o_ie,
output io_port_pins_15_o_pue,
output io_port_pins_15_o_ds,
input io_port_pins_16_i_ival,
output io_port_pins_16_o_oval,
output io_port_pins_16_o_oe,
output io_port_pins_16_o_ie,
output io_port_pins_16_o_pue,
output io_port_pins_16_o_ds,
input io_port_pins_17_i_ival,
output io_port_pins_17_o_oval,
output io_port_pins_17_o_oe,
output io_port_pins_17_o_ie,
output io_port_pins_17_o_pue,
output io_port_pins_17_o_ds,
input io_port_pins_18_i_ival,
output io_port_pins_18_o_oval,
output io_port_pins_18_o_oe,
output io_port_pins_18_o_ie,
output io_port_pins_18_o_pue,
output io_port_pins_18_o_ds,
input io_port_pins_19_i_ival,
output io_port_pins_19_o_oval,
output io_port_pins_19_o_oe,
output io_port_pins_19_o_ie,
output io_port_pins_19_o_pue,
output io_port_pins_19_o_ds,
input io_port_pins_20_i_ival,
output io_port_pins_20_o_oval,
output io_port_pins_20_o_oe,
output io_port_pins_20_o_ie,
output io_port_pins_20_o_pue,
output io_port_pins_20_o_ds,
input io_port_pins_21_i_ival,
output io_port_pins_21_o_oval,
output io_port_pins_21_o_oe,
output io_port_pins_21_o_ie,
output io_port_pins_21_o_pue,
output io_port_pins_21_o_ds,
input io_port_pins_22_i_ival,
output io_port_pins_22_o_oval,
output io_port_pins_22_o_oe,
output io_port_pins_22_o_ie,
output io_port_pins_22_o_pue,
output io_port_pins_22_o_ds,
input io_port_pins_23_i_ival,
output io_port_pins_23_o_oval,
output io_port_pins_23_o_oe,
output io_port_pins_23_o_ie,
output io_port_pins_23_o_pue,
output io_port_pins_23_o_ds,
input io_port_pins_24_i_ival,
output io_port_pins_24_o_oval,
output io_port_pins_24_o_oe,
output io_port_pins_24_o_ie,
output io_port_pins_24_o_pue,
output io_port_pins_24_o_ds,
input io_port_pins_25_i_ival,
output io_port_pins_25_o_oval,
output io_port_pins_25_o_oe,
output io_port_pins_25_o_ie,
output io_port_pins_25_o_pue,
output io_port_pins_25_o_ds,
input io_port_pins_26_i_ival,
output io_port_pins_26_o_oval,
output io_port_pins_26_o_oe,
output io_port_pins_26_o_ie,
output io_port_pins_26_o_pue,
output io_port_pins_26_o_ds,
input io_port_pins_27_i_ival,
output io_port_pins_27_o_oval,
output io_port_pins_27_o_oe,
output io_port_pins_27_o_ie,
output io_port_pins_27_o_pue,
output io_port_pins_27_o_ds,
input io_port_pins_28_i_ival,
output io_port_pins_28_o_oval,
output io_port_pins_28_o_oe,
output io_port_pins_28_o_ie,
output io_port_pins_28_o_pue,
output io_port_pins_28_o_ds,
input io_port_pins_29_i_ival,
output io_port_pins_29_o_oval,
output io_port_pins_29_o_oe,
output io_port_pins_29_o_ie,
output io_port_pins_29_o_pue,
output io_port_pins_29_o_ds,
input io_port_pins_30_i_ival,
output io_port_pins_30_o_oval,
output io_port_pins_30_o_oe,
output io_port_pins_30_o_ie,
output io_port_pins_30_o_pue,
output io_port_pins_30_o_ds,
input io_port_pins_31_i_ival,
output io_port_pins_31_o_oval,
output io_port_pins_31_o_oe,
output io_port_pins_31_o_ie,
output io_port_pins_31_o_pue,
output io_port_pins_31_o_ds,
output io_port_iof_0_0_i_ival,
input io_port_iof_0_0_o_oval,
input io_port_iof_0_0_o_oe,
input io_port_iof_0_0_o_ie,
input io_port_iof_0_0_o_valid,
output io_port_iof_0_1_i_ival,
input io_port_iof_0_1_o_oval,
input io_port_iof_0_1_o_oe,
input io_port_iof_0_1_o_ie,
input io_port_iof_0_1_o_valid,
output io_port_iof_0_2_i_ival,
input io_port_iof_0_2_o_oval,
input io_port_iof_0_2_o_oe,
input io_port_iof_0_2_o_ie,
input io_port_iof_0_2_o_valid,
output io_port_iof_0_3_i_ival,
input io_port_iof_0_3_o_oval,
input io_port_iof_0_3_o_oe,
input io_port_iof_0_3_o_ie,
input io_port_iof_0_3_o_valid,
output io_port_iof_0_4_i_ival,
input io_port_iof_0_4_o_oval,
input io_port_iof_0_4_o_oe,
input io_port_iof_0_4_o_ie,
input io_port_iof_0_4_o_valid,
output io_port_iof_0_5_i_ival,
input io_port_iof_0_5_o_oval,
input io_port_iof_0_5_o_oe,
input io_port_iof_0_5_o_ie,
input io_port_iof_0_5_o_valid,
output io_port_iof_0_6_i_ival,
input io_port_iof_0_6_o_oval,
input io_port_iof_0_6_o_oe,
input io_port_iof_0_6_o_ie,
input io_port_iof_0_6_o_valid,
output io_port_iof_0_7_i_ival,
input io_port_iof_0_7_o_oval,
input io_port_iof_0_7_o_oe,
input io_port_iof_0_7_o_ie,
input io_port_iof_0_7_o_valid,
output io_port_iof_0_8_i_ival,
input io_port_iof_0_8_o_oval,
input io_port_iof_0_8_o_oe,
input io_port_iof_0_8_o_ie,
input io_port_iof_0_8_o_valid,
output io_port_iof_0_9_i_ival,
input io_port_iof_0_9_o_oval,
input io_port_iof_0_9_o_oe,
input io_port_iof_0_9_o_ie,
input io_port_iof_0_9_o_valid,
output io_port_iof_0_10_i_ival,
input io_port_iof_0_10_o_oval,
input io_port_iof_0_10_o_oe,
input io_port_iof_0_10_o_ie,
input io_port_iof_0_10_o_valid,
output io_port_iof_0_11_i_ival,
input io_port_iof_0_11_o_oval,
input io_port_iof_0_11_o_oe,
input io_port_iof_0_11_o_ie,
input io_port_iof_0_11_o_valid,
output io_port_iof_0_12_i_ival,
input io_port_iof_0_12_o_oval,
input io_port_iof_0_12_o_oe,
input io_port_iof_0_12_o_ie,
input io_port_iof_0_12_o_valid,
output io_port_iof_0_13_i_ival,
input io_port_iof_0_13_o_oval,
input io_port_iof_0_13_o_oe,
input io_port_iof_0_13_o_ie,
input io_port_iof_0_13_o_valid,
output io_port_iof_0_14_i_ival,
input io_port_iof_0_14_o_oval,
input io_port_iof_0_14_o_oe,
input io_port_iof_0_14_o_ie,
input io_port_iof_0_14_o_valid,
output io_port_iof_0_15_i_ival,
input io_port_iof_0_15_o_oval,
input io_port_iof_0_15_o_oe,
input io_port_iof_0_15_o_ie,
input io_port_iof_0_15_o_valid,
output io_port_iof_0_16_i_ival,
input io_port_iof_0_16_o_oval,
input io_port_iof_0_16_o_oe,
input io_port_iof_0_16_o_ie,
input io_port_iof_0_16_o_valid,
output io_port_iof_0_17_i_ival,
input io_port_iof_0_17_o_oval,
input io_port_iof_0_17_o_oe,
input io_port_iof_0_17_o_ie,
input io_port_iof_0_17_o_valid,
output io_port_iof_0_18_i_ival,
input io_port_iof_0_18_o_oval,
input io_port_iof_0_18_o_oe,
input io_port_iof_0_18_o_ie,
input io_port_iof_0_18_o_valid,
output io_port_iof_0_19_i_ival,
input io_port_iof_0_19_o_oval,
input io_port_iof_0_19_o_oe,
input io_port_iof_0_19_o_ie,
input io_port_iof_0_19_o_valid,
output io_port_iof_0_20_i_ival,
input io_port_iof_0_20_o_oval,
input io_port_iof_0_20_o_oe,
input io_port_iof_0_20_o_ie,
input io_port_iof_0_20_o_valid,
output io_port_iof_0_21_i_ival,
input io_port_iof_0_21_o_oval,
input io_port_iof_0_21_o_oe,
input io_port_iof_0_21_o_ie,
input io_port_iof_0_21_o_valid,
output io_port_iof_0_22_i_ival,
input io_port_iof_0_22_o_oval,
input io_port_iof_0_22_o_oe,
input io_port_iof_0_22_o_ie,
input io_port_iof_0_22_o_valid,
output io_port_iof_0_23_i_ival,
input io_port_iof_0_23_o_oval,
input io_port_iof_0_23_o_oe,
input io_port_iof_0_23_o_ie,
input io_port_iof_0_23_o_valid,
output io_port_iof_0_24_i_ival,
input io_port_iof_0_24_o_oval,
input io_port_iof_0_24_o_oe,
input io_port_iof_0_24_o_ie,
input io_port_iof_0_24_o_valid,
output io_port_iof_0_25_i_ival,
input io_port_iof_0_25_o_oval,
input io_port_iof_0_25_o_oe,
input io_port_iof_0_25_o_ie,
input io_port_iof_0_25_o_valid,
output io_port_iof_0_26_i_ival,
input io_port_iof_0_26_o_oval,
input io_port_iof_0_26_o_oe,
input io_port_iof_0_26_o_ie,
input io_port_iof_0_26_o_valid,
output io_port_iof_0_27_i_ival,
input io_port_iof_0_27_o_oval,
input io_port_iof_0_27_o_oe,
input io_port_iof_0_27_o_ie,
input io_port_iof_0_27_o_valid,
output io_port_iof_0_28_i_ival,
input io_port_iof_0_28_o_oval,
input io_port_iof_0_28_o_oe,
input io_port_iof_0_28_o_ie,
input io_port_iof_0_28_o_valid,
output io_port_iof_0_29_i_ival,
input io_port_iof_0_29_o_oval,
input io_port_iof_0_29_o_oe,
input io_port_iof_0_29_o_ie,
input io_port_iof_0_29_o_valid,
output io_port_iof_0_30_i_ival,
input io_port_iof_0_30_o_oval,
input io_port_iof_0_30_o_oe,
input io_port_iof_0_30_o_ie,
input io_port_iof_0_30_o_valid,
output io_port_iof_0_31_i_ival,
input io_port_iof_0_31_o_oval,
input io_port_iof_0_31_o_oe,
input io_port_iof_0_31_o_ie,
input io_port_iof_0_31_o_valid,
output io_port_iof_1_0_i_ival,
input io_port_iof_1_0_o_oval,
input io_port_iof_1_0_o_oe,
input io_port_iof_1_0_o_ie,
input io_port_iof_1_0_o_valid,
output io_port_iof_1_1_i_ival,
input io_port_iof_1_1_o_oval,
input io_port_iof_1_1_o_oe,
input io_port_iof_1_1_o_ie,
input io_port_iof_1_1_o_valid,
output io_port_iof_1_2_i_ival,
input io_port_iof_1_2_o_oval,
input io_port_iof_1_2_o_oe,
input io_port_iof_1_2_o_ie,
input io_port_iof_1_2_o_valid,
output io_port_iof_1_3_i_ival,
input io_port_iof_1_3_o_oval,
input io_port_iof_1_3_o_oe,
input io_port_iof_1_3_o_ie,
input io_port_iof_1_3_o_valid,
output io_port_iof_1_4_i_ival,
input io_port_iof_1_4_o_oval,
input io_port_iof_1_4_o_oe,
input io_port_iof_1_4_o_ie,
input io_port_iof_1_4_o_valid,
output io_port_iof_1_5_i_ival,
input io_port_iof_1_5_o_oval,
input io_port_iof_1_5_o_oe,
input io_port_iof_1_5_o_ie,
input io_port_iof_1_5_o_valid,
output io_port_iof_1_6_i_ival,
input io_port_iof_1_6_o_oval,
input io_port_iof_1_6_o_oe,
input io_port_iof_1_6_o_ie,
input io_port_iof_1_6_o_valid,
output io_port_iof_1_7_i_ival,
input io_port_iof_1_7_o_oval,
input io_port_iof_1_7_o_oe,
input io_port_iof_1_7_o_ie,
input io_port_iof_1_7_o_valid,
output io_port_iof_1_8_i_ival,
input io_port_iof_1_8_o_oval,
input io_port_iof_1_8_o_oe,
input io_port_iof_1_8_o_ie,
input io_port_iof_1_8_o_valid,
output io_port_iof_1_9_i_ival,
input io_port_iof_1_9_o_oval,
input io_port_iof_1_9_o_oe,
input io_port_iof_1_9_o_ie,
input io_port_iof_1_9_o_valid,
output io_port_iof_1_10_i_ival,
input io_port_iof_1_10_o_oval,
input io_port_iof_1_10_o_oe,
input io_port_iof_1_10_o_ie,
input io_port_iof_1_10_o_valid,
output io_port_iof_1_11_i_ival,
input io_port_iof_1_11_o_oval,
input io_port_iof_1_11_o_oe,
input io_port_iof_1_11_o_ie,
input io_port_iof_1_11_o_valid,
output io_port_iof_1_12_i_ival,
input io_port_iof_1_12_o_oval,
input io_port_iof_1_12_o_oe,
input io_port_iof_1_12_o_ie,
input io_port_iof_1_12_o_valid,
output io_port_iof_1_13_i_ival,
input io_port_iof_1_13_o_oval,
input io_port_iof_1_13_o_oe,
input io_port_iof_1_13_o_ie,
input io_port_iof_1_13_o_valid,
output io_port_iof_1_14_i_ival,
input io_port_iof_1_14_o_oval,
input io_port_iof_1_14_o_oe,
input io_port_iof_1_14_o_ie,
input io_port_iof_1_14_o_valid,
output io_port_iof_1_15_i_ival,
input io_port_iof_1_15_o_oval,
input io_port_iof_1_15_o_oe,
input io_port_iof_1_15_o_ie,
input io_port_iof_1_15_o_valid,
output io_port_iof_1_16_i_ival,
input io_port_iof_1_16_o_oval,
input io_port_iof_1_16_o_oe,
input io_port_iof_1_16_o_ie,
input io_port_iof_1_16_o_valid,
output io_port_iof_1_17_i_ival,
input io_port_iof_1_17_o_oval,
input io_port_iof_1_17_o_oe,
input io_port_iof_1_17_o_ie,
input io_port_iof_1_17_o_valid,
output io_port_iof_1_18_i_ival,
input io_port_iof_1_18_o_oval,
input io_port_iof_1_18_o_oe,
input io_port_iof_1_18_o_ie,
input io_port_iof_1_18_o_valid,
output io_port_iof_1_19_i_ival,
input io_port_iof_1_19_o_oval,
input io_port_iof_1_19_o_oe,
input io_port_iof_1_19_o_ie,
input io_port_iof_1_19_o_valid,
output io_port_iof_1_20_i_ival,
input io_port_iof_1_20_o_oval,
input io_port_iof_1_20_o_oe,
input io_port_iof_1_20_o_ie,
input io_port_iof_1_20_o_valid,
output io_port_iof_1_21_i_ival,
input io_port_iof_1_21_o_oval,
input io_port_iof_1_21_o_oe,
input io_port_iof_1_21_o_ie,
input io_port_iof_1_21_o_valid,
output io_port_iof_1_22_i_ival,
input io_port_iof_1_22_o_oval,
input io_port_iof_1_22_o_oe,
input io_port_iof_1_22_o_ie,
input io_port_iof_1_22_o_valid,
output io_port_iof_1_23_i_ival,
input io_port_iof_1_23_o_oval,
input io_port_iof_1_23_o_oe,
input io_port_iof_1_23_o_ie,
input io_port_iof_1_23_o_valid,
output io_port_iof_1_24_i_ival,
input io_port_iof_1_24_o_oval,
input io_port_iof_1_24_o_oe,
input io_port_iof_1_24_o_ie,
input io_port_iof_1_24_o_valid,
output io_port_iof_1_25_i_ival,
input io_port_iof_1_25_o_oval,
input io_port_iof_1_25_o_oe,
input io_port_iof_1_25_o_ie,
input io_port_iof_1_25_o_valid,
output io_port_iof_1_26_i_ival,
input io_port_iof_1_26_o_oval,
input io_port_iof_1_26_o_oe,
input io_port_iof_1_26_o_ie,
input io_port_iof_1_26_o_valid,
output io_port_iof_1_27_i_ival,
input io_port_iof_1_27_o_oval,
input io_port_iof_1_27_o_oe,
input io_port_iof_1_27_o_ie,
input io_port_iof_1_27_o_valid,
output io_port_iof_1_28_i_ival,
input io_port_iof_1_28_o_oval,
input io_port_iof_1_28_o_oe,
input io_port_iof_1_28_o_ie,
input io_port_iof_1_28_o_valid,
output io_port_iof_1_29_i_ival,
input io_port_iof_1_29_o_oval,
input io_port_iof_1_29_o_oe,
input io_port_iof_1_29_o_ie,
input io_port_iof_1_29_o_valid,
output io_port_iof_1_30_i_ival,
input io_port_iof_1_30_o_oval,
input io_port_iof_1_30_o_oe,
input io_port_iof_1_30_o_ie,
input io_port_iof_1_30_o_valid,
output io_port_iof_1_31_i_ival,
input io_port_iof_1_31_o_oval,
input io_port_iof_1_31_o_oe,
input io_port_iof_1_31_o_ie,
input io_port_iof_1_31_o_valid
);
reg [31:0] portReg;
reg [31:0] GEN_399;
wire oeReg_clock;
wire oeReg_reset;
wire [31:0] oeReg_io_d;
wire [31:0] oeReg_io_q;
wire oeReg_io_en;
wire pueReg_clock;
wire pueReg_reset;
wire [31:0] pueReg_io_d;
wire [31:0] pueReg_io_q;
wire pueReg_io_en;
reg [31:0] dsReg;
reg [31:0] GEN_400;
wire ieReg_clock;
wire ieReg_reset;
wire [31:0] ieReg_io_d;
wire [31:0] ieReg_io_q;
wire ieReg_io_en;
wire [31:0] inVal;
wire T_3188_0;
wire T_3188_1;
wire T_3188_2;
wire T_3188_3;
wire T_3188_4;
wire T_3188_5;
wire T_3188_6;
wire T_3188_7;
wire T_3188_8;
wire T_3188_9;
wire T_3188_10;
wire T_3188_11;
wire T_3188_12;
wire T_3188_13;
wire T_3188_14;
wire T_3188_15;
wire T_3188_16;
wire T_3188_17;
wire T_3188_18;
wire T_3188_19;
wire T_3188_20;
wire T_3188_21;
wire T_3188_22;
wire T_3188_23;
wire T_3188_24;
wire T_3188_25;
wire T_3188_26;
wire T_3188_27;
wire T_3188_28;
wire T_3188_29;
wire T_3188_30;
wire T_3188_31;
wire [1:0] T_3223;
wire [1:0] T_3224;
wire [3:0] T_3225;
wire [1:0] T_3226;
wire [1:0] T_3227;
wire [3:0] T_3228;
wire [7:0] T_3229;
wire [1:0] T_3230;
wire [1:0] T_3231;
wire [3:0] T_3232;
wire [1:0] T_3233;
wire [1:0] T_3234;
wire [3:0] T_3235;
wire [7:0] T_3236;
wire [15:0] T_3237;
wire [1:0] T_3238;
wire [1:0] T_3239;
wire [3:0] T_3240;
wire [1:0] T_3241;
wire [1:0] T_3242;
wire [3:0] T_3243;
wire [7:0] T_3244;
wire [1:0] T_3245;
wire [1:0] T_3246;
wire [3:0] T_3247;
wire [1:0] T_3248;
wire [1:0] T_3249;
wire [3:0] T_3250;
wire [7:0] T_3251;
wire [15:0] T_3252;
wire [31:0] T_3253;
reg [31:0] T_3256;
reg [31:0] GEN_401;
reg [31:0] T_3257;
reg [31:0] GEN_402;
reg [31:0] inSyncReg;
reg [31:0] GEN_403;
reg [31:0] valueReg;
reg [31:0] GEN_404;
reg [31:0] highIeReg;
reg [31:0] GEN_405;
reg [31:0] lowIeReg;
reg [31:0] GEN_406;
reg [31:0] riseIeReg;
reg [31:0] GEN_407;
reg [31:0] fallIeReg;
reg [31:0] GEN_408;
reg [31:0] highIpReg;
reg [31:0] GEN_409;
reg [31:0] lowIpReg;
reg [31:0] GEN_410;
reg [31:0] riseIpReg;
reg [31:0] GEN_411;
reg [31:0] fallIpReg;
reg [31:0] GEN_412;
wire iofEnReg_clock;
wire iofEnReg_reset;
wire [31:0] iofEnReg_io_d;
wire [31:0] iofEnReg_io_q;
wire iofEnReg_io_en;
reg [31:0] iofSelReg;
reg [31:0] GEN_413;
reg [31:0] xorReg;
reg [31:0] GEN_414;
wire [31:0] T_3269;
wire [31:0] rise;
wire [31:0] T_3270;
wire [31:0] fall;
wire T_3295_ready;
wire T_3295_valid;
wire T_3295_bits_read;
wire [9:0] T_3295_bits_index;
wire [31:0] T_3295_bits_data;
wire [3:0] T_3295_bits_mask;
wire [9:0] T_3295_bits_extra;
wire T_3312;
wire [26:0] T_3313;
wire [1:0] T_3314;
wire [6:0] T_3315;
wire [9:0] T_3316;
wire T_3334_ready;
wire T_3334_valid;
wire T_3334_bits_read;
wire [31:0] T_3334_bits_data;
wire [9:0] T_3334_bits_extra;
wire T_3370_ready;
wire T_3370_valid;
wire T_3370_bits_read;
wire [9:0] T_3370_bits_index;
wire [31:0] T_3370_bits_data;
wire [3:0] T_3370_bits_mask;
wire [9:0] T_3370_bits_extra;
wire [9:0] T_3455;
wire T_3457;
wire [9:0] T_3463;
wire [9:0] T_3464;
wire T_3466;
wire [9:0] T_3472;
wire [9:0] T_3473;
wire T_3475;
wire [9:0] T_3481;
wire [9:0] T_3482;
wire T_3484;
wire [9:0] T_3490;
wire [9:0] T_3491;
wire T_3493;
wire [9:0] T_3499;
wire [9:0] T_3500;
wire T_3502;
wire [9:0] T_3508;
wire [9:0] T_3509;
wire T_3511;
wire [9:0] T_3517;
wire [9:0] T_3518;
wire T_3520;
wire [9:0] T_3526;
wire [9:0] T_3527;
wire T_3529;
wire [9:0] T_3535;
wire [9:0] T_3536;
wire T_3538;
wire [9:0] T_3544;
wire [9:0] T_3545;
wire T_3547;
wire [9:0] T_3553;
wire [9:0] T_3554;
wire T_3556;
wire [9:0] T_3562;
wire [9:0] T_3563;
wire T_3565;
wire [9:0] T_3571;
wire [9:0] T_3572;
wire T_3574;
wire [9:0] T_3580;
wire [9:0] T_3581;
wire T_3583;
wire [9:0] T_3589;
wire [9:0] T_3590;
wire T_3592;
wire [9:0] T_3598;
wire [9:0] T_3599;
wire T_3601;
wire T_3609_0;
wire T_3609_1;
wire T_3609_2;
wire T_3609_3;
wire T_3609_4;
wire T_3609_5;
wire T_3609_6;
wire T_3609_7;
wire T_3609_8;
wire T_3609_9;
wire T_3609_10;
wire T_3609_11;
wire T_3609_12;
wire T_3609_13;
wire T_3609_14;
wire T_3609_15;
wire T_3609_16;
wire T_3614_0;
wire T_3614_1;
wire T_3614_2;
wire T_3614_3;
wire T_3614_4;
wire T_3614_5;
wire T_3614_6;
wire T_3614_7;
wire T_3614_8;
wire T_3614_9;
wire T_3614_10;
wire T_3614_11;
wire T_3614_12;
wire T_3614_13;
wire T_3614_14;
wire T_3614_15;
wire T_3614_16;
wire T_3619_0;
wire T_3619_1;
wire T_3619_2;
wire T_3619_3;
wire T_3619_4;
wire T_3619_5;
wire T_3619_6;
wire T_3619_7;
wire T_3619_8;
wire T_3619_9;
wire T_3619_10;
wire T_3619_11;
wire T_3619_12;
wire T_3619_13;
wire T_3619_14;
wire T_3619_15;
wire T_3619_16;
wire T_3624_0;
wire T_3624_1;
wire T_3624_2;
wire T_3624_3;
wire T_3624_4;
wire T_3624_5;
wire T_3624_6;
wire T_3624_7;
wire T_3624_8;
wire T_3624_9;
wire T_3624_10;
wire T_3624_11;
wire T_3624_12;
wire T_3624_13;
wire T_3624_14;
wire T_3624_15;
wire T_3624_16;
wire T_3629_0;
wire T_3629_1;
wire T_3629_2;
wire T_3629_3;
wire T_3629_4;
wire T_3629_5;
wire T_3629_6;
wire T_3629_7;
wire T_3629_8;
wire T_3629_9;
wire T_3629_10;
wire T_3629_11;
wire T_3629_12;
wire T_3629_13;
wire T_3629_14;
wire T_3629_15;
wire T_3629_16;
wire T_3634_0;
wire T_3634_1;
wire T_3634_2;
wire T_3634_3;
wire T_3634_4;
wire T_3634_5;
wire T_3634_6;
wire T_3634_7;
wire T_3634_8;
wire T_3634_9;
wire T_3634_10;
wire T_3634_11;
wire T_3634_12;
wire T_3634_13;
wire T_3634_14;
wire T_3634_15;
wire T_3634_16;
wire T_3639_0;
wire T_3639_1;
wire T_3639_2;
wire T_3639_3;
wire T_3639_4;
wire T_3639_5;
wire T_3639_6;
wire T_3639_7;
wire T_3639_8;
wire T_3639_9;
wire T_3639_10;
wire T_3639_11;
wire T_3639_12;
wire T_3639_13;
wire T_3639_14;
wire T_3639_15;
wire T_3639_16;
wire T_3644_0;
wire T_3644_1;
wire T_3644_2;
wire T_3644_3;
wire T_3644_4;
wire T_3644_5;
wire T_3644_6;
wire T_3644_7;
wire T_3644_8;
wire T_3644_9;
wire T_3644_10;
wire T_3644_11;
wire T_3644_12;
wire T_3644_13;
wire T_3644_14;
wire T_3644_15;
wire T_3644_16;
wire T_3806;
wire T_3807;
wire T_3808;
wire T_3809;
wire [7:0] T_3813;
wire [7:0] T_3817;
wire [7:0] T_3821;
wire [7:0] T_3825;
wire [15:0] T_3826;
wire [15:0] T_3827;
wire [31:0] T_3828;
wire [31:0] T_3856;
wire T_3858;
wire T_3911;
wire [31:0] GEN_7;
wire T_3951;
wire [31:0] GEN_8;
wire T_3991;
wire [31:0] T_4007;
wire T_4031;
wire [31:0] T_4047;
wire T_4071;
wire [31:0] GEN_9;
wire T_4111;
wire [31:0] T_4114;
wire [31:0] T_4116;
wire [31:0] T_4117;
wire [31:0] T_4118;
wire [31:0] T_4119;
wire T_4157;
wire [31:0] T_4160;
wire [31:0] T_4162;
wire [31:0] T_4163;
wire [31:0] T_4164;
wire [31:0] T_4165;
wire T_4203;
wire [31:0] T_4219;
wire T_4243;
wire [31:0] GEN_10;
wire T_4283;
wire [31:0] T_4286;
wire [31:0] T_4288;
wire [31:0] T_4289;
wire [31:0] T_4290;
wire [31:0] T_4291;
wire T_4329;
wire [31:0] GEN_11;
wire T_4369;
wire [31:0] GEN_12;
wire T_4409;
wire [31:0] T_4412;
wire [31:0] T_4414;
wire [31:0] T_4415;
wire [31:0] T_4416;
wire [31:0] T_4417;
wire T_4455;
wire [31:0] GEN_13;
wire T_4495;
wire [31:0] T_4511;
wire T_4535;
wire [31:0] GEN_14;
wire T_4557;
wire T_4559;
wire T_4561;
wire T_4563;
wire T_4565;
wire T_4567;
wire T_4569;
wire T_4571;
wire T_4573;
wire T_4575;
wire T_4577;
wire T_4579;
wire T_4581;
wire T_4583;
wire T_4585;
wire T_4587;
wire T_4589;
wire T_4591;
wire T_4593;
wire T_4595;
wire T_4597;
wire T_4599;
wire T_4601;
wire T_4603;
wire T_4605;
wire T_4607;
wire T_4609;
wire T_4611;
wire T_4613;
wire T_4615;
wire T_4617;
wire T_4619;
wire T_4621;
wire T_4623;
wire T_4704_0;
wire T_4704_1;
wire T_4704_2;
wire T_4704_3;
wire T_4704_4;
wire T_4704_5;
wire T_4704_6;
wire T_4704_7;
wire T_4704_8;
wire T_4704_9;
wire T_4704_10;
wire T_4704_11;
wire T_4704_12;
wire T_4704_13;
wire T_4704_14;
wire T_4704_15;
wire T_4704_16;
wire T_4704_17;
wire T_4704_18;
wire T_4704_19;
wire T_4704_20;
wire T_4704_21;
wire T_4704_22;
wire T_4704_23;
wire T_4704_24;
wire T_4704_25;
wire T_4704_26;
wire T_4704_27;
wire T_4704_28;
wire T_4704_29;
wire T_4704_30;
wire T_4704_31;
wire T_4742;
wire T_4746;
wire T_4750;
wire T_4754;
wire T_4758;
wire T_4762;
wire T_4766;
wire T_4770;
wire T_4774;
wire T_4778;
wire T_4782;
wire T_4786;
wire T_4790;
wire T_4794;
wire T_4798;
wire T_4802;
wire T_4806;
wire T_4887_0;
wire T_4887_1;
wire T_4887_2;
wire T_4887_3;
wire T_4887_4;
wire T_4887_5;
wire T_4887_6;
wire T_4887_7;
wire T_4887_8;
wire T_4887_9;
wire T_4887_10;
wire T_4887_11;
wire T_4887_12;
wire T_4887_13;
wire T_4887_14;
wire T_4887_15;
wire T_4887_16;
wire T_4887_17;
wire T_4887_18;
wire T_4887_19;
wire T_4887_20;
wire T_4887_21;
wire T_4887_22;
wire T_4887_23;
wire T_4887_24;
wire T_4887_25;
wire T_4887_26;
wire T_4887_27;
wire T_4887_28;
wire T_4887_29;
wire T_4887_30;
wire T_4887_31;
wire T_4925;
wire T_4929;
wire T_4933;
wire T_4937;
wire T_4941;
wire T_4945;
wire T_4949;
wire T_4953;
wire T_4957;
wire T_4961;
wire T_4965;
wire T_4969;
wire T_4973;
wire T_4977;
wire T_4981;
wire T_4985;
wire T_4989;
wire T_5070_0;
wire T_5070_1;
wire T_5070_2;
wire T_5070_3;
wire T_5070_4;
wire T_5070_5;
wire T_5070_6;
wire T_5070_7;
wire T_5070_8;
wire T_5070_9;
wire T_5070_10;
wire T_5070_11;
wire T_5070_12;
wire T_5070_13;
wire T_5070_14;
wire T_5070_15;
wire T_5070_16;
wire T_5070_17;
wire T_5070_18;
wire T_5070_19;
wire T_5070_20;
wire T_5070_21;
wire T_5070_22;
wire T_5070_23;
wire T_5070_24;
wire T_5070_25;
wire T_5070_26;
wire T_5070_27;
wire T_5070_28;
wire T_5070_29;
wire T_5070_30;
wire T_5070_31;
wire T_5108;
wire T_5112;
wire T_5116;
wire T_5120;
wire T_5124;
wire T_5128;
wire T_5132;
wire T_5136;
wire T_5140;
wire T_5144;
wire T_5148;
wire T_5152;
wire T_5156;
wire T_5160;
wire T_5164;
wire T_5168;
wire T_5172;
wire T_5253_0;
wire T_5253_1;
wire T_5253_2;
wire T_5253_3;
wire T_5253_4;
wire T_5253_5;
wire T_5253_6;
wire T_5253_7;
wire T_5253_8;
wire T_5253_9;
wire T_5253_10;
wire T_5253_11;
wire T_5253_12;
wire T_5253_13;
wire T_5253_14;
wire T_5253_15;
wire T_5253_16;
wire T_5253_17;
wire T_5253_18;
wire T_5253_19;
wire T_5253_20;
wire T_5253_21;
wire T_5253_22;
wire T_5253_23;
wire T_5253_24;
wire T_5253_25;
wire T_5253_26;
wire T_5253_27;
wire T_5253_28;
wire T_5253_29;
wire T_5253_30;
wire T_5253_31;
wire T_5288;
wire T_5289;
wire T_5290;
wire T_5291;
wire T_5292;
wire [1:0] T_5298;
wire [1:0] T_5299;
wire [2:0] T_5300;
wire [4:0] T_5301;
wire GEN_0;
wire GEN_15;
wire GEN_16;
wire GEN_17;
wire GEN_18;
wire GEN_19;
wire GEN_20;
wire GEN_21;
wire GEN_22;
wire GEN_23;
wire GEN_24;
wire GEN_25;
wire GEN_26;
wire GEN_27;
wire GEN_28;
wire GEN_29;
wire GEN_30;
wire GEN_31;
wire GEN_32;
wire GEN_33;
wire GEN_34;
wire GEN_35;
wire GEN_36;
wire GEN_37;
wire GEN_38;
wire GEN_39;
wire GEN_40;
wire GEN_41;
wire GEN_42;
wire GEN_43;
wire GEN_44;
wire GEN_45;
wire GEN_1;
wire GEN_46;
wire GEN_47;
wire GEN_48;
wire GEN_49;
wire GEN_50;
wire GEN_51;
wire GEN_52;
wire GEN_53;
wire GEN_54;
wire GEN_55;
wire GEN_56;
wire GEN_57;
wire GEN_58;
wire GEN_59;
wire GEN_60;
wire GEN_61;
wire GEN_62;
wire GEN_63;
wire GEN_64;
wire GEN_65;
wire GEN_66;
wire GEN_67;
wire GEN_68;
wire GEN_69;
wire GEN_70;
wire GEN_71;
wire GEN_72;
wire GEN_73;
wire GEN_74;
wire GEN_75;
wire GEN_76;
wire T_5318;
wire GEN_2;
wire GEN_77;
wire GEN_78;
wire GEN_79;
wire GEN_80;
wire GEN_81;
wire GEN_82;
wire GEN_83;
wire GEN_84;
wire GEN_85;
wire GEN_86;
wire GEN_87;
wire GEN_88;
wire GEN_89;
wire GEN_90;
wire GEN_91;
wire GEN_92;
wire GEN_93;
wire GEN_94;
wire GEN_95;
wire GEN_96;
wire GEN_97;
wire GEN_98;
wire GEN_99;
wire GEN_100;
wire GEN_101;
wire GEN_102;
wire GEN_103;
wire GEN_104;
wire GEN_105;
wire GEN_106;
wire GEN_107;
wire GEN_3;
wire GEN_108;
wire GEN_109;
wire GEN_110;
wire GEN_111;
wire GEN_112;
wire GEN_113;
wire GEN_114;
wire GEN_115;
wire GEN_116;
wire GEN_117;
wire GEN_118;
wire GEN_119;
wire GEN_120;
wire GEN_121;
wire GEN_122;
wire GEN_123;
wire GEN_124;
wire GEN_125;
wire GEN_126;
wire GEN_127;
wire GEN_128;
wire GEN_129;
wire GEN_130;
wire GEN_131;
wire GEN_132;
wire GEN_133;
wire GEN_134;
wire GEN_135;
wire GEN_136;
wire GEN_137;
wire GEN_138;
wire T_5321;
wire T_5322;
wire T_5323;
wire T_5324;
wire T_5325;
wire [31:0] T_5327;
wire [1:0] T_5328;
wire [1:0] T_5329;
wire [3:0] T_5330;
wire [1:0] T_5331;
wire [1:0] T_5332;
wire [3:0] T_5333;
wire [7:0] T_5334;
wire [1:0] T_5335;
wire [1:0] T_5336;
wire [3:0] T_5337;
wire [1:0] T_5338;
wire [1:0] T_5339;
wire [3:0] T_5340;
wire [7:0] T_5341;
wire [15:0] T_5342;
wire [1:0] T_5343;
wire [3:0] T_5345;
wire [7:0] T_5349;
wire [15:0] T_5357;
wire [31:0] T_5358;
wire [31:0] T_5359;
wire T_5394;
wire T_5395;
wire T_5396;
wire T_5397;
wire T_5400;
wire T_5401;
wire T_5403;
wire T_5404;
wire T_5405;
wire T_5407;
wire T_5411;
wire T_5413;
wire T_5416;
wire T_5417;
wire T_5423;
wire T_5427;
wire T_5433;
wire T_5436;
wire T_5437;
wire T_5443;
wire T_5447;
wire T_5453;
wire T_5456;
wire T_5457;
wire T_5463;
wire T_5467;
wire T_5473;
wire T_5476;
wire T_5477;
wire T_5483;
wire T_5487;
wire T_5493;
wire T_5496;
wire T_5497;
wire T_5503;
wire T_5507;
wire T_5513;
wire T_5516;
wire T_5517;
wire T_5523;
wire T_5527;
wire T_5533;
wire T_5536;
wire T_5537;
wire T_5543;
wire T_5547;
wire T_5553;
wire T_5556;
wire T_5557;
wire T_5563;
wire T_5567;
wire T_5573;
wire T_5576;
wire T_5577;
wire T_5583;
wire T_5587;
wire T_5593;
wire T_5596;
wire T_5597;
wire T_5603;
wire T_5607;
wire T_5613;
wire T_5616;
wire T_5617;
wire T_5623;
wire T_5627;
wire T_5633;
wire T_5636;
wire T_5637;
wire T_5643;
wire T_5647;
wire T_5653;
wire T_5656;
wire T_5657;
wire T_5663;
wire T_5667;
wire T_5673;
wire T_5676;
wire T_5677;
wire T_5683;
wire T_5687;
wire T_5693;
wire T_5696;
wire T_5697;
wire T_5703;
wire T_5707;
wire T_5713;
wire T_5716;
wire T_5717;
wire T_5723;
wire T_5727;
wire T_5733;
wire T_6137_0;
wire T_6137_1;
wire T_6137_2;
wire T_6137_3;
wire T_6137_4;
wire T_6137_5;
wire T_6137_6;
wire T_6137_7;
wire T_6137_8;
wire T_6137_9;
wire T_6137_10;
wire T_6137_11;
wire T_6137_12;
wire T_6137_13;
wire T_6137_14;
wire T_6137_15;
wire T_6137_16;
wire T_6137_17;
wire T_6137_18;
wire T_6137_19;
wire T_6137_20;
wire T_6137_21;
wire T_6137_22;
wire T_6137_23;
wire T_6137_24;
wire T_6137_25;
wire T_6137_26;
wire T_6137_27;
wire T_6137_28;
wire T_6137_29;
wire T_6137_30;
wire T_6137_31;
wire [31:0] T_6208_0;
wire [31:0] T_6208_1;
wire [31:0] T_6208_2;
wire [31:0] T_6208_3;
wire [31:0] T_6208_4;
wire [31:0] T_6208_5;
wire [31:0] T_6208_6;
wire [31:0] T_6208_7;
wire [31:0] T_6208_8;
wire [31:0] T_6208_9;
wire [31:0] T_6208_10;
wire [31:0] T_6208_11;
wire [31:0] T_6208_12;
wire [31:0] T_6208_13;
wire [31:0] T_6208_14;
wire [31:0] T_6208_15;
wire [31:0] T_6208_16;
wire [31:0] T_6208_17;
wire [31:0] T_6208_18;
wire [31:0] T_6208_19;
wire [31:0] T_6208_20;
wire [31:0] T_6208_21;
wire [31:0] T_6208_22;
wire [31:0] T_6208_23;
wire [31:0] T_6208_24;
wire [31:0] T_6208_25;
wire [31:0] T_6208_26;
wire [31:0] T_6208_27;
wire [31:0] T_6208_28;
wire [31:0] T_6208_29;
wire [31:0] T_6208_30;
wire [31:0] T_6208_31;
wire GEN_4;
wire GEN_139;
wire GEN_140;
wire GEN_141;
wire GEN_142;
wire GEN_143;
wire GEN_144;
wire GEN_145;
wire GEN_146;
wire GEN_147;
wire GEN_148;
wire GEN_149;
wire GEN_150;
wire GEN_151;
wire GEN_152;
wire GEN_153;
wire GEN_154;
wire GEN_155;
wire GEN_156;
wire GEN_157;
wire GEN_158;
wire GEN_159;
wire GEN_160;
wire GEN_161;
wire GEN_162;
wire GEN_163;
wire GEN_164;
wire GEN_165;
wire GEN_166;
wire GEN_167;
wire GEN_168;
wire GEN_169;
wire [31:0] GEN_5;
wire [31:0] GEN_170;
wire [31:0] GEN_171;
wire [31:0] GEN_172;
wire [31:0] GEN_173;
wire [31:0] GEN_174;
wire [31:0] GEN_175;
wire [31:0] GEN_176;
wire [31:0] GEN_177;
wire [31:0] GEN_178;
wire [31:0] GEN_179;
wire [31:0] GEN_180;
wire [31:0] GEN_181;
wire [31:0] GEN_182;
wire [31:0] GEN_183;
wire [31:0] GEN_184;
wire [31:0] GEN_185;
wire [31:0] GEN_186;
wire [31:0] GEN_187;
wire [31:0] GEN_188;
wire [31:0] GEN_189;
wire [31:0] GEN_190;
wire [31:0] GEN_191;
wire [31:0] GEN_192;
wire [31:0] GEN_193;
wire [31:0] GEN_194;
wire [31:0] GEN_195;
wire [31:0] GEN_196;
wire [31:0] GEN_197;
wire [31:0] GEN_198;
wire [31:0] GEN_199;
wire [31:0] GEN_200;
wire [31:0] T_6245;
wire [1:0] T_6246;
wire [4:0] T_6248;
wire [2:0] T_6249;
wire [2:0] T_6260_opcode;
wire [1:0] T_6260_param;
wire [2:0] T_6260_size;
wire [4:0] T_6260_source;
wire T_6260_sink;
wire [1:0] T_6260_addr_lo;
wire [31:0] T_6260_data;
wire T_6260_error;
wire swPinCtrl_0_oval;
wire swPinCtrl_0_oe;
wire swPinCtrl_0_ie;
wire swPinCtrl_0_pue;
wire swPinCtrl_0_ds;
wire swPinCtrl_1_oval;
wire swPinCtrl_1_oe;
wire swPinCtrl_1_ie;
wire swPinCtrl_1_pue;
wire swPinCtrl_1_ds;
wire swPinCtrl_2_oval;
wire swPinCtrl_2_oe;
wire swPinCtrl_2_ie;
wire swPinCtrl_2_pue;
wire swPinCtrl_2_ds;
wire swPinCtrl_3_oval;
wire swPinCtrl_3_oe;
wire swPinCtrl_3_ie;
wire swPinCtrl_3_pue;
wire swPinCtrl_3_ds;
wire swPinCtrl_4_oval;
wire swPinCtrl_4_oe;
wire swPinCtrl_4_ie;
wire swPinCtrl_4_pue;
wire swPinCtrl_4_ds;
wire swPinCtrl_5_oval;
wire swPinCtrl_5_oe;
wire swPinCtrl_5_ie;
wire swPinCtrl_5_pue;
wire swPinCtrl_5_ds;
wire swPinCtrl_6_oval;
wire swPinCtrl_6_oe;
wire swPinCtrl_6_ie;
wire swPinCtrl_6_pue;
wire swPinCtrl_6_ds;
wire swPinCtrl_7_oval;
wire swPinCtrl_7_oe;
wire swPinCtrl_7_ie;
wire swPinCtrl_7_pue;
wire swPinCtrl_7_ds;
wire swPinCtrl_8_oval;
wire swPinCtrl_8_oe;
wire swPinCtrl_8_ie;
wire swPinCtrl_8_pue;
wire swPinCtrl_8_ds;
wire swPinCtrl_9_oval;
wire swPinCtrl_9_oe;
wire swPinCtrl_9_ie;
wire swPinCtrl_9_pue;
wire swPinCtrl_9_ds;
wire swPinCtrl_10_oval;
wire swPinCtrl_10_oe;
wire swPinCtrl_10_ie;
wire swPinCtrl_10_pue;
wire swPinCtrl_10_ds;
wire swPinCtrl_11_oval;
wire swPinCtrl_11_oe;
wire swPinCtrl_11_ie;
wire swPinCtrl_11_pue;
wire swPinCtrl_11_ds;
wire swPinCtrl_12_oval;
wire swPinCtrl_12_oe;
wire swPinCtrl_12_ie;
wire swPinCtrl_12_pue;
wire swPinCtrl_12_ds;
wire swPinCtrl_13_oval;
wire swPinCtrl_13_oe;
wire swPinCtrl_13_ie;
wire swPinCtrl_13_pue;
wire swPinCtrl_13_ds;
wire swPinCtrl_14_oval;
wire swPinCtrl_14_oe;
wire swPinCtrl_14_ie;
wire swPinCtrl_14_pue;
wire swPinCtrl_14_ds;
wire swPinCtrl_15_oval;
wire swPinCtrl_15_oe;
wire swPinCtrl_15_ie;
wire swPinCtrl_15_pue;
wire swPinCtrl_15_ds;
wire swPinCtrl_16_oval;
wire swPinCtrl_16_oe;
wire swPinCtrl_16_ie;
wire swPinCtrl_16_pue;
wire swPinCtrl_16_ds;
wire swPinCtrl_17_oval;
wire swPinCtrl_17_oe;
wire swPinCtrl_17_ie;
wire swPinCtrl_17_pue;
wire swPinCtrl_17_ds;
wire swPinCtrl_18_oval;
wire swPinCtrl_18_oe;
wire swPinCtrl_18_ie;
wire swPinCtrl_18_pue;
wire swPinCtrl_18_ds;
wire swPinCtrl_19_oval;
wire swPinCtrl_19_oe;
wire swPinCtrl_19_ie;
wire swPinCtrl_19_pue;
wire swPinCtrl_19_ds;
wire swPinCtrl_20_oval;
wire swPinCtrl_20_oe;
wire swPinCtrl_20_ie;
wire swPinCtrl_20_pue;
wire swPinCtrl_20_ds;
wire swPinCtrl_21_oval;
wire swPinCtrl_21_oe;
wire swPinCtrl_21_ie;
wire swPinCtrl_21_pue;
wire swPinCtrl_21_ds;
wire swPinCtrl_22_oval;
wire swPinCtrl_22_oe;
wire swPinCtrl_22_ie;
wire swPinCtrl_22_pue;
wire swPinCtrl_22_ds;
wire swPinCtrl_23_oval;
wire swPinCtrl_23_oe;
wire swPinCtrl_23_ie;
wire swPinCtrl_23_pue;
wire swPinCtrl_23_ds;
wire swPinCtrl_24_oval;
wire swPinCtrl_24_oe;
wire swPinCtrl_24_ie;
wire swPinCtrl_24_pue;
wire swPinCtrl_24_ds;
wire swPinCtrl_25_oval;
wire swPinCtrl_25_oe;
wire swPinCtrl_25_ie;
wire swPinCtrl_25_pue;
wire swPinCtrl_25_ds;
wire swPinCtrl_26_oval;
wire swPinCtrl_26_oe;
wire swPinCtrl_26_ie;
wire swPinCtrl_26_pue;
wire swPinCtrl_26_ds;
wire swPinCtrl_27_oval;
wire swPinCtrl_27_oe;
wire swPinCtrl_27_ie;
wire swPinCtrl_27_pue;
wire swPinCtrl_27_ds;
wire swPinCtrl_28_oval;
wire swPinCtrl_28_oe;
wire swPinCtrl_28_ie;
wire swPinCtrl_28_pue;
wire swPinCtrl_28_ds;
wire swPinCtrl_29_oval;
wire swPinCtrl_29_oe;
wire swPinCtrl_29_ie;
wire swPinCtrl_29_pue;
wire swPinCtrl_29_ds;
wire swPinCtrl_30_oval;
wire swPinCtrl_30_oe;
wire swPinCtrl_30_ie;
wire swPinCtrl_30_pue;
wire swPinCtrl_30_ds;
wire swPinCtrl_31_oval;
wire swPinCtrl_31_oe;
wire swPinCtrl_31_ie;
wire swPinCtrl_31_pue;
wire swPinCtrl_31_ds;
wire iof0Ctrl_0_oval;
wire iof0Ctrl_0_oe;
wire iof0Ctrl_0_ie;
wire iof0Ctrl_1_oval;
wire iof0Ctrl_1_oe;
wire iof0Ctrl_1_ie;
wire iof0Ctrl_2_oval;
wire iof0Ctrl_2_oe;
wire iof0Ctrl_2_ie;
wire iof0Ctrl_3_oval;
wire iof0Ctrl_3_oe;
wire iof0Ctrl_3_ie;
wire iof0Ctrl_4_oval;
wire iof0Ctrl_4_oe;
wire iof0Ctrl_4_ie;
wire iof0Ctrl_5_oval;
wire iof0Ctrl_5_oe;
wire iof0Ctrl_5_ie;
wire iof0Ctrl_6_oval;
wire iof0Ctrl_6_oe;
wire iof0Ctrl_6_ie;
wire iof0Ctrl_7_oval;
wire iof0Ctrl_7_oe;
wire iof0Ctrl_7_ie;
wire iof0Ctrl_8_oval;
wire iof0Ctrl_8_oe;
wire iof0Ctrl_8_ie;
wire iof0Ctrl_9_oval;
wire iof0Ctrl_9_oe;
wire iof0Ctrl_9_ie;
wire iof0Ctrl_10_oval;
wire iof0Ctrl_10_oe;
wire iof0Ctrl_10_ie;
wire iof0Ctrl_11_oval;
wire iof0Ctrl_11_oe;
wire iof0Ctrl_11_ie;
wire iof0Ctrl_12_oval;
wire iof0Ctrl_12_oe;
wire iof0Ctrl_12_ie;
wire iof0Ctrl_13_oval;
wire iof0Ctrl_13_oe;
wire iof0Ctrl_13_ie;
wire iof0Ctrl_14_oval;
wire iof0Ctrl_14_oe;
wire iof0Ctrl_14_ie;
wire iof0Ctrl_15_oval;
wire iof0Ctrl_15_oe;
wire iof0Ctrl_15_ie;
wire iof0Ctrl_16_oval;
wire iof0Ctrl_16_oe;
wire iof0Ctrl_16_ie;
wire iof0Ctrl_17_oval;
wire iof0Ctrl_17_oe;
wire iof0Ctrl_17_ie;
wire iof0Ctrl_18_oval;
wire iof0Ctrl_18_oe;
wire iof0Ctrl_18_ie;
wire iof0Ctrl_19_oval;
wire iof0Ctrl_19_oe;
wire iof0Ctrl_19_ie;
wire iof0Ctrl_20_oval;
wire iof0Ctrl_20_oe;
wire iof0Ctrl_20_ie;
wire iof0Ctrl_21_oval;
wire iof0Ctrl_21_oe;
wire iof0Ctrl_21_ie;
wire iof0Ctrl_22_oval;
wire iof0Ctrl_22_oe;
wire iof0Ctrl_22_ie;
wire iof0Ctrl_23_oval;
wire iof0Ctrl_23_oe;
wire iof0Ctrl_23_ie;
wire iof0Ctrl_24_oval;
wire iof0Ctrl_24_oe;
wire iof0Ctrl_24_ie;
wire iof0Ctrl_25_oval;
wire iof0Ctrl_25_oe;
wire iof0Ctrl_25_ie;
wire iof0Ctrl_26_oval;
wire iof0Ctrl_26_oe;
wire iof0Ctrl_26_ie;
wire iof0Ctrl_27_oval;
wire iof0Ctrl_27_oe;
wire iof0Ctrl_27_ie;
wire iof0Ctrl_28_oval;
wire iof0Ctrl_28_oe;
wire iof0Ctrl_28_ie;
wire iof0Ctrl_29_oval;
wire iof0Ctrl_29_oe;
wire iof0Ctrl_29_ie;
wire iof0Ctrl_30_oval;
wire iof0Ctrl_30_oe;
wire iof0Ctrl_30_ie;
wire iof0Ctrl_31_oval;
wire iof0Ctrl_31_oe;
wire iof0Ctrl_31_ie;
wire iof1Ctrl_0_oval;
wire iof1Ctrl_0_oe;
wire iof1Ctrl_0_ie;
wire iof1Ctrl_1_oval;
wire iof1Ctrl_1_oe;
wire iof1Ctrl_1_ie;
wire iof1Ctrl_2_oval;
wire iof1Ctrl_2_oe;
wire iof1Ctrl_2_ie;
wire iof1Ctrl_3_oval;
wire iof1Ctrl_3_oe;
wire iof1Ctrl_3_ie;
wire iof1Ctrl_4_oval;
wire iof1Ctrl_4_oe;
wire iof1Ctrl_4_ie;
wire iof1Ctrl_5_oval;
wire iof1Ctrl_5_oe;
wire iof1Ctrl_5_ie;
wire iof1Ctrl_6_oval;
wire iof1Ctrl_6_oe;
wire iof1Ctrl_6_ie;
wire iof1Ctrl_7_oval;
wire iof1Ctrl_7_oe;
wire iof1Ctrl_7_ie;
wire iof1Ctrl_8_oval;
wire iof1Ctrl_8_oe;
wire iof1Ctrl_8_ie;
wire iof1Ctrl_9_oval;
wire iof1Ctrl_9_oe;
wire iof1Ctrl_9_ie;
wire iof1Ctrl_10_oval;
wire iof1Ctrl_10_oe;
wire iof1Ctrl_10_ie;
wire iof1Ctrl_11_oval;
wire iof1Ctrl_11_oe;
wire iof1Ctrl_11_ie;
wire iof1Ctrl_12_oval;
wire iof1Ctrl_12_oe;
wire iof1Ctrl_12_ie;
wire iof1Ctrl_13_oval;
wire iof1Ctrl_13_oe;
wire iof1Ctrl_13_ie;
wire iof1Ctrl_14_oval;
wire iof1Ctrl_14_oe;
wire iof1Ctrl_14_ie;
wire iof1Ctrl_15_oval;
wire iof1Ctrl_15_oe;
wire iof1Ctrl_15_ie;
wire iof1Ctrl_16_oval;
wire iof1Ctrl_16_oe;
wire iof1Ctrl_16_ie;
wire iof1Ctrl_17_oval;
wire iof1Ctrl_17_oe;
wire iof1Ctrl_17_ie;
wire iof1Ctrl_18_oval;
wire iof1Ctrl_18_oe;
wire iof1Ctrl_18_ie;
wire iof1Ctrl_19_oval;
wire iof1Ctrl_19_oe;
wire iof1Ctrl_19_ie;
wire iof1Ctrl_20_oval;
wire iof1Ctrl_20_oe;
wire iof1Ctrl_20_ie;
wire iof1Ctrl_21_oval;
wire iof1Ctrl_21_oe;
wire iof1Ctrl_21_ie;
wire iof1Ctrl_22_oval;
wire iof1Ctrl_22_oe;
wire iof1Ctrl_22_ie;
wire iof1Ctrl_23_oval;
wire iof1Ctrl_23_oe;
wire iof1Ctrl_23_ie;
wire iof1Ctrl_24_oval;
wire iof1Ctrl_24_oe;
wire iof1Ctrl_24_ie;
wire iof1Ctrl_25_oval;
wire iof1Ctrl_25_oe;
wire iof1Ctrl_25_ie;
wire iof1Ctrl_26_oval;
wire iof1Ctrl_26_oe;
wire iof1Ctrl_26_ie;
wire iof1Ctrl_27_oval;
wire iof1Ctrl_27_oe;
wire iof1Ctrl_27_ie;
wire iof1Ctrl_28_oval;
wire iof1Ctrl_28_oe;
wire iof1Ctrl_28_ie;
wire iof1Ctrl_29_oval;
wire iof1Ctrl_29_oe;
wire iof1Ctrl_29_ie;
wire iof1Ctrl_30_oval;
wire iof1Ctrl_30_oe;
wire iof1Ctrl_30_ie;
wire iof1Ctrl_31_oval;
wire iof1Ctrl_31_oe;
wire iof1Ctrl_31_ie;
wire iofCtrl_0_oval;
wire iofCtrl_0_oe;
wire iofCtrl_0_ie;
wire iofCtrl_1_oval;
wire iofCtrl_1_oe;
wire iofCtrl_1_ie;
wire iofCtrl_2_oval;
wire iofCtrl_2_oe;
wire iofCtrl_2_ie;
wire iofCtrl_3_oval;
wire iofCtrl_3_oe;
wire iofCtrl_3_ie;
wire iofCtrl_4_oval;
wire iofCtrl_4_oe;
wire iofCtrl_4_ie;
wire iofCtrl_5_oval;
wire iofCtrl_5_oe;
wire iofCtrl_5_ie;
wire iofCtrl_6_oval;
wire iofCtrl_6_oe;
wire iofCtrl_6_ie;
wire iofCtrl_7_oval;
wire iofCtrl_7_oe;
wire iofCtrl_7_ie;
wire iofCtrl_8_oval;
wire iofCtrl_8_oe;
wire iofCtrl_8_ie;
wire iofCtrl_9_oval;
wire iofCtrl_9_oe;
wire iofCtrl_9_ie;
wire iofCtrl_10_oval;
wire iofCtrl_10_oe;
wire iofCtrl_10_ie;
wire iofCtrl_11_oval;
wire iofCtrl_11_oe;
wire iofCtrl_11_ie;
wire iofCtrl_12_oval;
wire iofCtrl_12_oe;
wire iofCtrl_12_ie;
wire iofCtrl_13_oval;
wire iofCtrl_13_oe;
wire iofCtrl_13_ie;
wire iofCtrl_14_oval;
wire iofCtrl_14_oe;
wire iofCtrl_14_ie;
wire iofCtrl_15_oval;
wire iofCtrl_15_oe;
wire iofCtrl_15_ie;
wire iofCtrl_16_oval;
wire iofCtrl_16_oe;
wire iofCtrl_16_ie;
wire iofCtrl_17_oval;
wire iofCtrl_17_oe;
wire iofCtrl_17_ie;
wire iofCtrl_18_oval;
wire iofCtrl_18_oe;
wire iofCtrl_18_ie;
wire iofCtrl_19_oval;
wire iofCtrl_19_oe;
wire iofCtrl_19_ie;
wire iofCtrl_20_oval;
wire iofCtrl_20_oe;
wire iofCtrl_20_ie;
wire iofCtrl_21_oval;
wire iofCtrl_21_oe;
wire iofCtrl_21_ie;
wire iofCtrl_22_oval;
wire iofCtrl_22_oe;
wire iofCtrl_22_ie;
wire iofCtrl_23_oval;
wire iofCtrl_23_oe;
wire iofCtrl_23_ie;
wire iofCtrl_24_oval;
wire iofCtrl_24_oe;
wire iofCtrl_24_ie;
wire iofCtrl_25_oval;
wire iofCtrl_25_oe;
wire iofCtrl_25_ie;
wire iofCtrl_26_oval;
wire iofCtrl_26_oe;
wire iofCtrl_26_ie;
wire iofCtrl_27_oval;
wire iofCtrl_27_oe;
wire iofCtrl_27_ie;
wire iofCtrl_28_oval;
wire iofCtrl_28_oe;
wire iofCtrl_28_ie;
wire iofCtrl_29_oval;
wire iofCtrl_29_oe;
wire iofCtrl_29_ie;
wire iofCtrl_30_oval;
wire iofCtrl_30_oe;
wire iofCtrl_30_ie;
wire iofCtrl_31_oval;
wire iofCtrl_31_oe;
wire iofCtrl_31_ie;
wire iofPlusSwPinCtrl_0_oval;
wire iofPlusSwPinCtrl_0_oe;
wire iofPlusSwPinCtrl_0_ie;
wire iofPlusSwPinCtrl_0_pue;
wire iofPlusSwPinCtrl_0_ds;
wire iofPlusSwPinCtrl_1_oval;
wire iofPlusSwPinCtrl_1_oe;
wire iofPlusSwPinCtrl_1_ie;
wire iofPlusSwPinCtrl_1_pue;
wire iofPlusSwPinCtrl_1_ds;
wire iofPlusSwPinCtrl_2_oval;
wire iofPlusSwPinCtrl_2_oe;
wire iofPlusSwPinCtrl_2_ie;
wire iofPlusSwPinCtrl_2_pue;
wire iofPlusSwPinCtrl_2_ds;
wire iofPlusSwPinCtrl_3_oval;
wire iofPlusSwPinCtrl_3_oe;
wire iofPlusSwPinCtrl_3_ie;
wire iofPlusSwPinCtrl_3_pue;
wire iofPlusSwPinCtrl_3_ds;
wire iofPlusSwPinCtrl_4_oval;
wire iofPlusSwPinCtrl_4_oe;
wire iofPlusSwPinCtrl_4_ie;
wire iofPlusSwPinCtrl_4_pue;
wire iofPlusSwPinCtrl_4_ds;
wire iofPlusSwPinCtrl_5_oval;
wire iofPlusSwPinCtrl_5_oe;
wire iofPlusSwPinCtrl_5_ie;
wire iofPlusSwPinCtrl_5_pue;
wire iofPlusSwPinCtrl_5_ds;
wire iofPlusSwPinCtrl_6_oval;
wire iofPlusSwPinCtrl_6_oe;
wire iofPlusSwPinCtrl_6_ie;
wire iofPlusSwPinCtrl_6_pue;
wire iofPlusSwPinCtrl_6_ds;
wire iofPlusSwPinCtrl_7_oval;
wire iofPlusSwPinCtrl_7_oe;
wire iofPlusSwPinCtrl_7_ie;
wire iofPlusSwPinCtrl_7_pue;
wire iofPlusSwPinCtrl_7_ds;
wire iofPlusSwPinCtrl_8_oval;
wire iofPlusSwPinCtrl_8_oe;
wire iofPlusSwPinCtrl_8_ie;
wire iofPlusSwPinCtrl_8_pue;
wire iofPlusSwPinCtrl_8_ds;
wire iofPlusSwPinCtrl_9_oval;
wire iofPlusSwPinCtrl_9_oe;
wire iofPlusSwPinCtrl_9_ie;
wire iofPlusSwPinCtrl_9_pue;
wire iofPlusSwPinCtrl_9_ds;
wire iofPlusSwPinCtrl_10_oval;
wire iofPlusSwPinCtrl_10_oe;
wire iofPlusSwPinCtrl_10_ie;
wire iofPlusSwPinCtrl_10_pue;
wire iofPlusSwPinCtrl_10_ds;
wire iofPlusSwPinCtrl_11_oval;
wire iofPlusSwPinCtrl_11_oe;
wire iofPlusSwPinCtrl_11_ie;
wire iofPlusSwPinCtrl_11_pue;
wire iofPlusSwPinCtrl_11_ds;
wire iofPlusSwPinCtrl_12_oval;
wire iofPlusSwPinCtrl_12_oe;
wire iofPlusSwPinCtrl_12_ie;
wire iofPlusSwPinCtrl_12_pue;
wire iofPlusSwPinCtrl_12_ds;
wire iofPlusSwPinCtrl_13_oval;
wire iofPlusSwPinCtrl_13_oe;
wire iofPlusSwPinCtrl_13_ie;
wire iofPlusSwPinCtrl_13_pue;
wire iofPlusSwPinCtrl_13_ds;
wire iofPlusSwPinCtrl_14_oval;
wire iofPlusSwPinCtrl_14_oe;
wire iofPlusSwPinCtrl_14_ie;
wire iofPlusSwPinCtrl_14_pue;
wire iofPlusSwPinCtrl_14_ds;
wire iofPlusSwPinCtrl_15_oval;
wire iofPlusSwPinCtrl_15_oe;
wire iofPlusSwPinCtrl_15_ie;
wire iofPlusSwPinCtrl_15_pue;
wire iofPlusSwPinCtrl_15_ds;
wire iofPlusSwPinCtrl_16_oval;
wire iofPlusSwPinCtrl_16_oe;
wire iofPlusSwPinCtrl_16_ie;
wire iofPlusSwPinCtrl_16_pue;
wire iofPlusSwPinCtrl_16_ds;
wire iofPlusSwPinCtrl_17_oval;
wire iofPlusSwPinCtrl_17_oe;
wire iofPlusSwPinCtrl_17_ie;
wire iofPlusSwPinCtrl_17_pue;
wire iofPlusSwPinCtrl_17_ds;
wire iofPlusSwPinCtrl_18_oval;
wire iofPlusSwPinCtrl_18_oe;
wire iofPlusSwPinCtrl_18_ie;
wire iofPlusSwPinCtrl_18_pue;
wire iofPlusSwPinCtrl_18_ds;
wire iofPlusSwPinCtrl_19_oval;
wire iofPlusSwPinCtrl_19_oe;
wire iofPlusSwPinCtrl_19_ie;
wire iofPlusSwPinCtrl_19_pue;
wire iofPlusSwPinCtrl_19_ds;
wire iofPlusSwPinCtrl_20_oval;
wire iofPlusSwPinCtrl_20_oe;
wire iofPlusSwPinCtrl_20_ie;
wire iofPlusSwPinCtrl_20_pue;
wire iofPlusSwPinCtrl_20_ds;
wire iofPlusSwPinCtrl_21_oval;
wire iofPlusSwPinCtrl_21_oe;
wire iofPlusSwPinCtrl_21_ie;
wire iofPlusSwPinCtrl_21_pue;
wire iofPlusSwPinCtrl_21_ds;
wire iofPlusSwPinCtrl_22_oval;
wire iofPlusSwPinCtrl_22_oe;
wire iofPlusSwPinCtrl_22_ie;
wire iofPlusSwPinCtrl_22_pue;
wire iofPlusSwPinCtrl_22_ds;
wire iofPlusSwPinCtrl_23_oval;
wire iofPlusSwPinCtrl_23_oe;
wire iofPlusSwPinCtrl_23_ie;
wire iofPlusSwPinCtrl_23_pue;
wire iofPlusSwPinCtrl_23_ds;
wire iofPlusSwPinCtrl_24_oval;
wire iofPlusSwPinCtrl_24_oe;
wire iofPlusSwPinCtrl_24_ie;
wire iofPlusSwPinCtrl_24_pue;
wire iofPlusSwPinCtrl_24_ds;
wire iofPlusSwPinCtrl_25_oval;
wire iofPlusSwPinCtrl_25_oe;
wire iofPlusSwPinCtrl_25_ie;
wire iofPlusSwPinCtrl_25_pue;
wire iofPlusSwPinCtrl_25_ds;
wire iofPlusSwPinCtrl_26_oval;
wire iofPlusSwPinCtrl_26_oe;
wire iofPlusSwPinCtrl_26_ie;
wire iofPlusSwPinCtrl_26_pue;
wire iofPlusSwPinCtrl_26_ds;
wire iofPlusSwPinCtrl_27_oval;
wire iofPlusSwPinCtrl_27_oe;
wire iofPlusSwPinCtrl_27_ie;
wire iofPlusSwPinCtrl_27_pue;
wire iofPlusSwPinCtrl_27_ds;
wire iofPlusSwPinCtrl_28_oval;
wire iofPlusSwPinCtrl_28_oe;
wire iofPlusSwPinCtrl_28_ie;
wire iofPlusSwPinCtrl_28_pue;
wire iofPlusSwPinCtrl_28_ds;
wire iofPlusSwPinCtrl_29_oval;
wire iofPlusSwPinCtrl_29_oe;
wire iofPlusSwPinCtrl_29_ie;
wire iofPlusSwPinCtrl_29_pue;
wire iofPlusSwPinCtrl_29_ds;
wire iofPlusSwPinCtrl_30_oval;
wire iofPlusSwPinCtrl_30_oe;
wire iofPlusSwPinCtrl_30_ie;
wire iofPlusSwPinCtrl_30_pue;
wire iofPlusSwPinCtrl_30_ds;
wire iofPlusSwPinCtrl_31_oval;
wire iofPlusSwPinCtrl_31_oe;
wire iofPlusSwPinCtrl_31_ie;
wire iofPlusSwPinCtrl_31_pue;
wire iofPlusSwPinCtrl_31_ds;
wire T_7569;
wire T_7570;
wire T_7571;
wire T_7572;
wire T_7573;
wire GEN_201;
wire GEN_202;
wire GEN_203;
wire GEN_204;
wire GEN_205;
wire GEN_206;
wire T_7574;
wire T_7575_oval;
wire T_7575_oe;
wire T_7575_ie;
wire T_7579;
wire T_7580_oval;
wire T_7580_oe;
wire T_7580_ie;
wire T_7580_pue;
wire T_7580_ds;
wire T_7586;
wire T_7587;
wire T_7588;
wire T_7589;
wire T_7590;
wire T_7591;
wire T_7592;
wire T_7593;
wire T_7594;
wire T_7595;
wire T_7596;
wire T_7597;
wire T_7598;
wire T_7599;
wire T_7600;
wire T_7601;
wire T_7602;
wire T_7603;
wire T_7605;
wire T_7606;
wire T_7607;
wire T_7608;
wire T_7609;
wire GEN_207;
wire GEN_208;
wire GEN_209;
wire GEN_210;
wire GEN_211;
wire GEN_212;
wire T_7610;
wire T_7611_oval;
wire T_7611_oe;
wire T_7611_ie;
wire T_7615;
wire T_7616_oval;
wire T_7616_oe;
wire T_7616_ie;
wire T_7616_pue;
wire T_7616_ds;
wire T_7622;
wire T_7623;
wire T_7624;
wire T_7625;
wire T_7626;
wire T_7627;
wire T_7628;
wire T_7629;
wire T_7630;
wire T_7631;
wire T_7632;
wire T_7633;
wire T_7634;
wire T_7635;
wire T_7636;
wire T_7637;
wire T_7638;
wire T_7639;
wire T_7641;
wire T_7642;
wire T_7643;
wire T_7644;
wire T_7645;
wire GEN_213;
wire GEN_214;
wire GEN_215;
wire GEN_216;
wire GEN_217;
wire GEN_218;
wire T_7646;
wire T_7647_oval;
wire T_7647_oe;
wire T_7647_ie;
wire T_7651;
wire T_7652_oval;
wire T_7652_oe;
wire T_7652_ie;
wire T_7652_pue;
wire T_7652_ds;
wire T_7658;
wire T_7659;
wire T_7660;
wire T_7661;
wire T_7662;
wire T_7663;
wire T_7664;
wire T_7665;
wire T_7666;
wire T_7667;
wire T_7668;
wire T_7669;
wire T_7670;
wire T_7671;
wire T_7672;
wire T_7673;
wire T_7674;
wire T_7675;
wire T_7677;
wire T_7678;
wire T_7679;
wire T_7680;
wire T_7681;
wire GEN_219;
wire GEN_220;
wire GEN_221;
wire GEN_222;
wire GEN_223;
wire GEN_224;
wire T_7682;
wire T_7683_oval;
wire T_7683_oe;
wire T_7683_ie;
wire T_7687;
wire T_7688_oval;
wire T_7688_oe;
wire T_7688_ie;
wire T_7688_pue;
wire T_7688_ds;
wire T_7694;
wire T_7695;
wire T_7696;
wire T_7697;
wire T_7698;
wire T_7699;
wire T_7700;
wire T_7701;
wire T_7702;
wire T_7703;
wire T_7704;
wire T_7705;
wire T_7706;
wire T_7707;
wire T_7708;
wire T_7709;
wire T_7710;
wire T_7711;
wire T_7713;
wire T_7714;
wire T_7715;
wire T_7716;
wire T_7717;
wire GEN_225;
wire GEN_226;
wire GEN_227;
wire GEN_228;
wire GEN_229;
wire GEN_230;
wire T_7718;
wire T_7719_oval;
wire T_7719_oe;
wire T_7719_ie;
wire T_7723;
wire T_7724_oval;
wire T_7724_oe;
wire T_7724_ie;
wire T_7724_pue;
wire T_7724_ds;
wire T_7730;
wire T_7731;
wire T_7732;
wire T_7733;
wire T_7734;
wire T_7735;
wire T_7736;
wire T_7737;
wire T_7738;
wire T_7739;
wire T_7740;
wire T_7741;
wire T_7742;
wire T_7743;
wire T_7744;
wire T_7745;
wire T_7746;
wire T_7747;
wire T_7749;
wire T_7750;
wire T_7751;
wire T_7752;
wire T_7753;
wire GEN_231;
wire GEN_232;
wire GEN_233;
wire GEN_234;
wire GEN_235;
wire GEN_236;
wire T_7754;
wire T_7755_oval;
wire T_7755_oe;
wire T_7755_ie;
wire T_7759;
wire T_7760_oval;
wire T_7760_oe;
wire T_7760_ie;
wire T_7760_pue;
wire T_7760_ds;
wire T_7766;
wire T_7767;
wire T_7768;
wire T_7769;
wire T_7770;
wire T_7771;
wire T_7772;
wire T_7773;
wire T_7774;
wire T_7775;
wire T_7776;
wire T_7777;
wire T_7778;
wire T_7779;
wire T_7780;
wire T_7781;
wire T_7782;
wire T_7783;
wire T_7785;
wire T_7786;
wire T_7787;
wire T_7788;
wire T_7789;
wire GEN_237;
wire GEN_238;
wire GEN_239;
wire GEN_240;
wire GEN_241;
wire GEN_242;
wire T_7790;
wire T_7791_oval;
wire T_7791_oe;
wire T_7791_ie;
wire T_7795;
wire T_7796_oval;
wire T_7796_oe;
wire T_7796_ie;
wire T_7796_pue;
wire T_7796_ds;
wire T_7802;
wire T_7803;
wire T_7804;
wire T_7805;
wire T_7806;
wire T_7807;
wire T_7808;
wire T_7809;
wire T_7810;
wire T_7811;
wire T_7812;
wire T_7813;
wire T_7814;
wire T_7815;
wire T_7816;
wire T_7817;
wire T_7818;
wire T_7819;
wire T_7821;
wire T_7822;
wire T_7823;
wire T_7824;
wire T_7825;
wire GEN_243;
wire GEN_244;
wire GEN_245;
wire GEN_246;
wire GEN_247;
wire GEN_248;
wire T_7826;
wire T_7827_oval;
wire T_7827_oe;
wire T_7827_ie;
wire T_7831;
wire T_7832_oval;
wire T_7832_oe;
wire T_7832_ie;
wire T_7832_pue;
wire T_7832_ds;
wire T_7838;
wire T_7839;
wire T_7840;
wire T_7841;
wire T_7842;
wire T_7843;
wire T_7844;
wire T_7845;
wire T_7846;
wire T_7847;
wire T_7848;
wire T_7849;
wire T_7850;
wire T_7851;
wire T_7852;
wire T_7853;
wire T_7854;
wire T_7855;
wire T_7857;
wire T_7858;
wire T_7859;
wire T_7860;
wire T_7861;
wire GEN_249;
wire GEN_250;
wire GEN_251;
wire GEN_252;
wire GEN_253;
wire GEN_254;
wire T_7862;
wire T_7863_oval;
wire T_7863_oe;
wire T_7863_ie;
wire T_7867;
wire T_7868_oval;
wire T_7868_oe;
wire T_7868_ie;
wire T_7868_pue;
wire T_7868_ds;
wire T_7874;
wire T_7875;
wire T_7876;
wire T_7877;
wire T_7878;
wire T_7879;
wire T_7880;
wire T_7881;
wire T_7882;
wire T_7883;
wire T_7884;
wire T_7885;
wire T_7886;
wire T_7887;
wire T_7888;
wire T_7889;
wire T_7890;
wire T_7891;
wire T_7893;
wire T_7894;
wire T_7895;
wire T_7896;
wire T_7897;
wire GEN_255;
wire GEN_256;
wire GEN_257;
wire GEN_258;
wire GEN_259;
wire GEN_260;
wire T_7898;
wire T_7899_oval;
wire T_7899_oe;
wire T_7899_ie;
wire T_7903;
wire T_7904_oval;
wire T_7904_oe;
wire T_7904_ie;
wire T_7904_pue;
wire T_7904_ds;
wire T_7910;
wire T_7911;
wire T_7912;
wire T_7913;
wire T_7914;
wire T_7915;
wire T_7916;
wire T_7917;
wire T_7918;
wire T_7919;
wire T_7920;
wire T_7921;
wire T_7922;
wire T_7923;
wire T_7924;
wire T_7925;
wire T_7926;
wire T_7927;
wire T_7929;
wire T_7930;
wire T_7931;
wire T_7932;
wire T_7933;
wire GEN_261;
wire GEN_262;
wire GEN_263;
wire GEN_264;
wire GEN_265;
wire GEN_266;
wire T_7934;
wire T_7935_oval;
wire T_7935_oe;
wire T_7935_ie;
wire T_7939;
wire T_7940_oval;
wire T_7940_oe;
wire T_7940_ie;
wire T_7940_pue;
wire T_7940_ds;
wire T_7946;
wire T_7947;
wire T_7948;
wire T_7949;
wire T_7950;
wire T_7951;
wire T_7952;
wire T_7953;
wire T_7954;
wire T_7955;
wire T_7956;
wire T_7957;
wire T_7958;
wire T_7959;
wire T_7960;
wire T_7961;
wire T_7962;
wire T_7963;
wire T_7965;
wire T_7966;
wire T_7967;
wire T_7968;
wire T_7969;
wire GEN_267;
wire GEN_268;
wire GEN_269;
wire GEN_270;
wire GEN_271;
wire GEN_272;
wire T_7970;
wire T_7971_oval;
wire T_7971_oe;
wire T_7971_ie;
wire T_7975;
wire T_7976_oval;
wire T_7976_oe;
wire T_7976_ie;
wire T_7976_pue;
wire T_7976_ds;
wire T_7982;
wire T_7983;
wire T_7984;
wire T_7985;
wire T_7986;
wire T_7987;
wire T_7988;
wire T_7989;
wire T_7990;
wire T_7991;
wire T_7992;
wire T_7993;
wire T_7994;
wire T_7995;
wire T_7996;
wire T_7997;
wire T_7998;
wire T_7999;
wire T_8001;
wire T_8002;
wire T_8003;
wire T_8004;
wire T_8005;
wire GEN_273;
wire GEN_274;
wire GEN_275;
wire GEN_276;
wire GEN_277;
wire GEN_278;
wire T_8006;
wire T_8007_oval;
wire T_8007_oe;
wire T_8007_ie;
wire T_8011;
wire T_8012_oval;
wire T_8012_oe;
wire T_8012_ie;
wire T_8012_pue;
wire T_8012_ds;
wire T_8018;
wire T_8019;
wire T_8020;
wire T_8021;
wire T_8022;
wire T_8023;
wire T_8024;
wire T_8025;
wire T_8026;
wire T_8027;
wire T_8028;
wire T_8029;
wire T_8030;
wire T_8031;
wire T_8032;
wire T_8033;
wire T_8034;
wire T_8035;
wire T_8037;
wire T_8038;
wire T_8039;
wire T_8040;
wire T_8041;
wire GEN_279;
wire GEN_280;
wire GEN_281;
wire GEN_282;
wire GEN_283;
wire GEN_284;
wire T_8042;
wire T_8043_oval;
wire T_8043_oe;
wire T_8043_ie;
wire T_8047;
wire T_8048_oval;
wire T_8048_oe;
wire T_8048_ie;
wire T_8048_pue;
wire T_8048_ds;
wire T_8054;
wire T_8055;
wire T_8056;
wire T_8057;
wire T_8058;
wire T_8059;
wire T_8060;
wire T_8061;
wire T_8062;
wire T_8063;
wire T_8064;
wire T_8065;
wire T_8066;
wire T_8067;
wire T_8068;
wire T_8069;
wire T_8070;
wire T_8071;
wire T_8073;
wire T_8074;
wire T_8075;
wire T_8076;
wire T_8077;
wire GEN_285;
wire GEN_286;
wire GEN_287;
wire GEN_288;
wire GEN_289;
wire GEN_290;
wire T_8078;
wire T_8079_oval;
wire T_8079_oe;
wire T_8079_ie;
wire T_8083;
wire T_8084_oval;
wire T_8084_oe;
wire T_8084_ie;
wire T_8084_pue;
wire T_8084_ds;
wire T_8090;
wire T_8091;
wire T_8092;
wire T_8093;
wire T_8094;
wire T_8095;
wire T_8096;
wire T_8097;
wire T_8098;
wire T_8099;
wire T_8100;
wire T_8101;
wire T_8102;
wire T_8103;
wire T_8104;
wire T_8105;
wire T_8106;
wire T_8107;
wire T_8109;
wire T_8110;
wire T_8111;
wire T_8112;
wire T_8113;
wire GEN_291;
wire GEN_292;
wire GEN_293;
wire GEN_294;
wire GEN_295;
wire GEN_296;
wire T_8114;
wire T_8115_oval;
wire T_8115_oe;
wire T_8115_ie;
wire T_8119;
wire T_8120_oval;
wire T_8120_oe;
wire T_8120_ie;
wire T_8120_pue;
wire T_8120_ds;
wire T_8126;
wire T_8127;
wire T_8128;
wire T_8129;
wire T_8130;
wire T_8131;
wire T_8132;
wire T_8133;
wire T_8134;
wire T_8135;
wire T_8136;
wire T_8137;
wire T_8138;
wire T_8139;
wire T_8140;
wire T_8141;
wire T_8142;
wire T_8143;
wire T_8145;
wire T_8146;
wire T_8147;
wire T_8148;
wire T_8149;
wire GEN_297;
wire GEN_298;
wire GEN_299;
wire GEN_300;
wire GEN_301;
wire GEN_302;
wire T_8150;
wire T_8151_oval;
wire T_8151_oe;
wire T_8151_ie;
wire T_8155;
wire T_8156_oval;
wire T_8156_oe;
wire T_8156_ie;
wire T_8156_pue;
wire T_8156_ds;
wire T_8162;
wire T_8163;
wire T_8164;
wire T_8165;
wire T_8166;
wire T_8167;
wire T_8168;
wire T_8169;
wire T_8170;
wire T_8171;
wire T_8172;
wire T_8173;
wire T_8174;
wire T_8175;
wire T_8176;
wire T_8177;
wire T_8178;
wire T_8179;
wire T_8181;
wire T_8182;
wire T_8183;
wire T_8184;
wire T_8185;
wire GEN_303;
wire GEN_304;
wire GEN_305;
wire GEN_306;
wire GEN_307;
wire GEN_308;
wire T_8186;
wire T_8187_oval;
wire T_8187_oe;
wire T_8187_ie;
wire T_8191;
wire T_8192_oval;
wire T_8192_oe;
wire T_8192_ie;
wire T_8192_pue;
wire T_8192_ds;
wire T_8198;
wire T_8199;
wire T_8200;
wire T_8201;
wire T_8202;
wire T_8203;
wire T_8204;
wire T_8205;
wire T_8206;
wire T_8207;
wire T_8208;
wire T_8209;
wire T_8210;
wire T_8211;
wire T_8212;
wire T_8213;
wire T_8214;
wire T_8215;
wire T_8217;
wire T_8218;
wire T_8219;
wire T_8220;
wire T_8221;
wire GEN_309;
wire GEN_310;
wire GEN_311;
wire GEN_312;
wire GEN_313;
wire GEN_314;
wire T_8222;
wire T_8223_oval;
wire T_8223_oe;
wire T_8223_ie;
wire T_8227;
wire T_8228_oval;
wire T_8228_oe;
wire T_8228_ie;
wire T_8228_pue;
wire T_8228_ds;
wire T_8234;
wire T_8235;
wire T_8236;
wire T_8237;
wire T_8238;
wire T_8239;
wire T_8240;
wire T_8241;
wire T_8242;
wire T_8243;
wire T_8244;
wire T_8245;
wire T_8246;
wire T_8247;
wire T_8248;
wire T_8249;
wire T_8250;
wire T_8251;
wire T_8253;
wire T_8254;
wire T_8255;
wire T_8256;
wire T_8257;
wire GEN_315;
wire GEN_316;
wire GEN_317;
wire GEN_318;
wire GEN_319;
wire GEN_320;
wire T_8258;
wire T_8259_oval;
wire T_8259_oe;
wire T_8259_ie;
wire T_8263;
wire T_8264_oval;
wire T_8264_oe;
wire T_8264_ie;
wire T_8264_pue;
wire T_8264_ds;
wire T_8270;
wire T_8271;
wire T_8272;
wire T_8273;
wire T_8274;
wire T_8275;
wire T_8276;
wire T_8277;
wire T_8278;
wire T_8279;
wire T_8280;
wire T_8281;
wire T_8282;
wire T_8283;
wire T_8284;
wire T_8285;
wire T_8286;
wire T_8287;
wire T_8289;
wire T_8290;
wire T_8291;
wire T_8292;
wire T_8293;
wire GEN_321;
wire GEN_322;
wire GEN_323;
wire GEN_324;
wire GEN_325;
wire GEN_326;
wire T_8294;
wire T_8295_oval;
wire T_8295_oe;
wire T_8295_ie;
wire T_8299;
wire T_8300_oval;
wire T_8300_oe;
wire T_8300_ie;
wire T_8300_pue;
wire T_8300_ds;
wire T_8306;
wire T_8307;
wire T_8308;
wire T_8309;
wire T_8310;
wire T_8311;
wire T_8312;
wire T_8313;
wire T_8314;
wire T_8315;
wire T_8316;
wire T_8317;
wire T_8318;
wire T_8319;
wire T_8320;
wire T_8321;
wire T_8322;
wire T_8323;
wire T_8325;
wire T_8326;
wire T_8327;
wire T_8328;
wire T_8329;
wire GEN_327;
wire GEN_328;
wire GEN_329;
wire GEN_330;
wire GEN_331;
wire GEN_332;
wire T_8330;
wire T_8331_oval;
wire T_8331_oe;
wire T_8331_ie;
wire T_8335;
wire T_8336_oval;
wire T_8336_oe;
wire T_8336_ie;
wire T_8336_pue;
wire T_8336_ds;
wire T_8342;
wire T_8343;
wire T_8344;
wire T_8345;
wire T_8346;
wire T_8347;
wire T_8348;
wire T_8349;
wire T_8350;
wire T_8351;
wire T_8352;
wire T_8353;
wire T_8354;
wire T_8355;
wire T_8356;
wire T_8357;
wire T_8358;
wire T_8359;
wire T_8361;
wire T_8362;
wire T_8363;
wire T_8364;
wire T_8365;
wire GEN_333;
wire GEN_334;
wire GEN_335;
wire GEN_336;
wire GEN_337;
wire GEN_338;
wire T_8366;
wire T_8367_oval;
wire T_8367_oe;
wire T_8367_ie;
wire T_8371;
wire T_8372_oval;
wire T_8372_oe;
wire T_8372_ie;
wire T_8372_pue;
wire T_8372_ds;
wire T_8378;
wire T_8379;
wire T_8380;
wire T_8381;
wire T_8382;
wire T_8383;
wire T_8384;
wire T_8385;
wire T_8386;
wire T_8387;
wire T_8388;
wire T_8389;
wire T_8390;
wire T_8391;
wire T_8392;
wire T_8393;
wire T_8394;
wire T_8395;
wire T_8397;
wire T_8398;
wire T_8399;
wire T_8400;
wire T_8401;
wire GEN_339;
wire GEN_340;
wire GEN_341;
wire GEN_342;
wire GEN_343;
wire GEN_344;
wire T_8402;
wire T_8403_oval;
wire T_8403_oe;
wire T_8403_ie;
wire T_8407;
wire T_8408_oval;
wire T_8408_oe;
wire T_8408_ie;
wire T_8408_pue;
wire T_8408_ds;
wire T_8414;
wire T_8415;
wire T_8416;
wire T_8417;
wire T_8418;
wire T_8419;
wire T_8420;
wire T_8421;
wire T_8422;
wire T_8423;
wire T_8424;
wire T_8425;
wire T_8426;
wire T_8427;
wire T_8428;
wire T_8429;
wire T_8430;
wire T_8431;
wire T_8433;
wire T_8434;
wire T_8435;
wire T_8436;
wire T_8437;
wire GEN_345;
wire GEN_346;
wire GEN_347;
wire GEN_348;
wire GEN_349;
wire GEN_350;
wire T_8438;
wire T_8439_oval;
wire T_8439_oe;
wire T_8439_ie;
wire T_8443;
wire T_8444_oval;
wire T_8444_oe;
wire T_8444_ie;
wire T_8444_pue;
wire T_8444_ds;
wire T_8450;
wire T_8451;
wire T_8452;
wire T_8453;
wire T_8454;
wire T_8455;
wire T_8456;
wire T_8457;
wire T_8458;
wire T_8459;
wire T_8460;
wire T_8461;
wire T_8462;
wire T_8463;
wire T_8464;
wire T_8465;
wire T_8466;
wire T_8467;
wire T_8469;
wire T_8470;
wire T_8471;
wire T_8472;
wire T_8473;
wire GEN_351;
wire GEN_352;
wire GEN_353;
wire GEN_354;
wire GEN_355;
wire GEN_356;
wire T_8474;
wire T_8475_oval;
wire T_8475_oe;
wire T_8475_ie;
wire T_8479;
wire T_8480_oval;
wire T_8480_oe;
wire T_8480_ie;
wire T_8480_pue;
wire T_8480_ds;
wire T_8486;
wire T_8487;
wire T_8488;
wire T_8489;
wire T_8490;
wire T_8491;
wire T_8492;
wire T_8493;
wire T_8494;
wire T_8495;
wire T_8496;
wire T_8497;
wire T_8498;
wire T_8499;
wire T_8500;
wire T_8501;
wire T_8502;
wire T_8503;
wire T_8505;
wire T_8506;
wire T_8507;
wire T_8508;
wire T_8509;
wire GEN_357;
wire GEN_358;
wire GEN_359;
wire GEN_360;
wire GEN_361;
wire GEN_362;
wire T_8510;
wire T_8511_oval;
wire T_8511_oe;
wire T_8511_ie;
wire T_8515;
wire T_8516_oval;
wire T_8516_oe;
wire T_8516_ie;
wire T_8516_pue;
wire T_8516_ds;
wire T_8522;
wire T_8523;
wire T_8524;
wire T_8525;
wire T_8526;
wire T_8527;
wire T_8528;
wire T_8529;
wire T_8530;
wire T_8531;
wire T_8532;
wire T_8533;
wire T_8534;
wire T_8535;
wire T_8536;
wire T_8537;
wire T_8538;
wire T_8539;
wire T_8541;
wire T_8542;
wire T_8543;
wire T_8544;
wire T_8545;
wire GEN_363;
wire GEN_364;
wire GEN_365;
wire GEN_366;
wire GEN_367;
wire GEN_368;
wire T_8546;
wire T_8547_oval;
wire T_8547_oe;
wire T_8547_ie;
wire T_8551;
wire T_8552_oval;
wire T_8552_oe;
wire T_8552_ie;
wire T_8552_pue;
wire T_8552_ds;
wire T_8558;
wire T_8559;
wire T_8560;
wire T_8561;
wire T_8562;
wire T_8563;
wire T_8564;
wire T_8565;
wire T_8566;
wire T_8567;
wire T_8568;
wire T_8569;
wire T_8570;
wire T_8571;
wire T_8572;
wire T_8573;
wire T_8574;
wire T_8575;
wire T_8577;
wire T_8578;
wire T_8579;
wire T_8580;
wire T_8581;
wire GEN_369;
wire GEN_370;
wire GEN_371;
wire GEN_372;
wire GEN_373;
wire GEN_374;
wire T_8582;
wire T_8583_oval;
wire T_8583_oe;
wire T_8583_ie;
wire T_8587;
wire T_8588_oval;
wire T_8588_oe;
wire T_8588_ie;
wire T_8588_pue;
wire T_8588_ds;
wire T_8594;
wire T_8595;
wire T_8596;
wire T_8597;
wire T_8598;
wire T_8599;
wire T_8600;
wire T_8601;
wire T_8602;
wire T_8603;
wire T_8604;
wire T_8605;
wire T_8606;
wire T_8607;
wire T_8608;
wire T_8609;
wire T_8610;
wire T_8611;
wire T_8613;
wire T_8614;
wire T_8615;
wire T_8616;
wire T_8617;
wire GEN_375;
wire GEN_376;
wire GEN_377;
wire GEN_378;
wire GEN_379;
wire GEN_380;
wire T_8618;
wire T_8619_oval;
wire T_8619_oe;
wire T_8619_ie;
wire T_8623;
wire T_8624_oval;
wire T_8624_oe;
wire T_8624_ie;
wire T_8624_pue;
wire T_8624_ds;
wire T_8630;
wire T_8631;
wire T_8632;
wire T_8633;
wire T_8634;
wire T_8635;
wire T_8636;
wire T_8637;
wire T_8638;
wire T_8639;
wire T_8640;
wire T_8641;
wire T_8642;
wire T_8643;
wire T_8644;
wire T_8645;
wire T_8646;
wire T_8647;
wire T_8649;
wire T_8650;
wire T_8651;
wire T_8652;
wire T_8653;
wire GEN_381;
wire GEN_382;
wire GEN_383;
wire GEN_384;
wire GEN_385;
wire GEN_386;
wire T_8654;
wire T_8655_oval;
wire T_8655_oe;
wire T_8655_ie;
wire T_8659;
wire T_8660_oval;
wire T_8660_oe;
wire T_8660_ie;
wire T_8660_pue;
wire T_8660_ds;
wire T_8666;
wire T_8667;
wire T_8668;
wire T_8669;
wire T_8670;
wire T_8671;
wire T_8672;
wire T_8673;
wire T_8674;
wire T_8675;
wire T_8676;
wire T_8677;
wire T_8678;
wire T_8679;
wire T_8680;
wire T_8681;
wire T_8682;
wire T_8683;
wire T_8685;
wire T_8686;
wire T_8687;
wire T_8688;
wire T_8689;
wire GEN_387;
wire GEN_388;
wire GEN_389;
wire GEN_390;
wire GEN_391;
wire GEN_392;
wire T_8690;
wire T_8691_oval;
wire T_8691_oe;
wire T_8691_ie;
wire T_8695;
wire T_8696_oval;
wire T_8696_oe;
wire T_8696_ie;
wire T_8696_pue;
wire T_8696_ds;
wire T_8702;
wire T_8703;
wire T_8704;
wire T_8705;
wire T_8706;
wire T_8707;
wire T_8708;
wire T_8709;
wire T_8710;
wire T_8711;
wire T_8712;
wire T_8713;
wire T_8714;
wire T_8715;
wire T_8716;
wire T_8717;
wire T_8718;
wire T_8719;
wire [2:0] GEN_6 = 3'b0;
wire [1:0] GEN_393 = 2'b0;
wire [2:0] GEN_394 = 3'b0;
wire [4:0] GEN_395 = 5'b0;
wire [28:0] GEN_396 = 29'b0;
wire [3:0] GEN_397 = 4'b0;
wire [31:0] GEN_398 = 32'b0;
sirv_AsyncResetRegVec_67 u_oeReg (
.clock(oeReg_clock),
.reset(oeReg_reset),
.io_d(oeReg_io_d),
.io_q(oeReg_io_q),
.io_en(oeReg_io_en)
);
sirv_AsyncResetRegVec_67 u_pueReg (
.clock(pueReg_clock),
.reset(pueReg_reset),
.io_d(pueReg_io_d),
.io_q(pueReg_io_q),
.io_en(pueReg_io_en)
);
sirv_AsyncResetRegVec_67 u_ieReg (
.clock(ieReg_clock),
.reset(ieReg_reset),
.io_d(ieReg_io_d),
.io_q(ieReg_io_q),
.io_en(ieReg_io_en)
);
sirv_AsyncResetRegVec_67 u_iofEnReg (
.clock(iofEnReg_clock),
.reset(iofEnReg_reset),
.io_d(iofEnReg_io_d),
.io_q(iofEnReg_io_q),
.io_en(iofEnReg_io_en)
);
assign io_interrupts_0_0 = T_7602;
assign io_interrupts_0_1 = T_7638;
assign io_interrupts_0_2 = T_7674;
assign io_interrupts_0_3 = T_7710;
assign io_interrupts_0_4 = T_7746;
assign io_interrupts_0_5 = T_7782;
assign io_interrupts_0_6 = T_7818;
assign io_interrupts_0_7 = T_7854;
assign io_interrupts_0_8 = T_7890;
assign io_interrupts_0_9 = T_7926;
assign io_interrupts_0_10 = T_7962;
assign io_interrupts_0_11 = T_7998;
assign io_interrupts_0_12 = T_8034;
assign io_interrupts_0_13 = T_8070;
assign io_interrupts_0_14 = T_8106;
assign io_interrupts_0_15 = T_8142;
assign io_interrupts_0_16 = T_8178;
assign io_interrupts_0_17 = T_8214;
assign io_interrupts_0_18 = T_8250;
assign io_interrupts_0_19 = T_8286;
assign io_interrupts_0_20 = T_8322;
assign io_interrupts_0_21 = T_8358;
assign io_interrupts_0_22 = T_8394;
assign io_interrupts_0_23 = T_8430;
assign io_interrupts_0_24 = T_8466;
assign io_interrupts_0_25 = T_8502;
assign io_interrupts_0_26 = T_8538;
assign io_interrupts_0_27 = T_8574;
assign io_interrupts_0_28 = T_8610;
assign io_interrupts_0_29 = T_8646;
assign io_interrupts_0_30 = T_8682;
assign io_interrupts_0_31 = T_8718;
assign io_in_0_a_ready = T_3295_ready;
assign io_in_0_b_valid = 1'h0;
assign io_in_0_b_bits_opcode = GEN_6;
assign io_in_0_b_bits_param = GEN_393;
assign io_in_0_b_bits_size = GEN_394;
assign io_in_0_b_bits_source = GEN_395;
assign io_in_0_b_bits_address = GEN_396;
assign io_in_0_b_bits_mask = GEN_397;
assign io_in_0_b_bits_data = GEN_398;
assign io_in_0_c_ready = 1'h1;
assign io_in_0_d_valid = T_3334_valid;
assign io_in_0_d_bits_opcode = {{2'd0}, T_3334_bits_read};
assign io_in_0_d_bits_param = T_6260_param;
assign io_in_0_d_bits_size = T_6260_size;
assign io_in_0_d_bits_source = T_6260_source;
assign io_in_0_d_bits_sink = T_6260_sink;
assign io_in_0_d_bits_addr_lo = T_6260_addr_lo;
assign io_in_0_d_bits_data = T_3334_bits_data;
assign io_in_0_d_bits_error = T_6260_error;
assign io_in_0_e_ready = 1'h1;
assign io_port_pins_0_o_oval = T_7587;
assign io_port_pins_0_o_oe = T_7580_oe;
assign io_port_pins_0_o_ie = T_7580_ie;
assign io_port_pins_0_o_pue = T_7580_pue;
assign io_port_pins_0_o_ds = T_7580_ds;
assign io_port_pins_1_o_oval = T_7623;
assign io_port_pins_1_o_oe = T_7616_oe;
assign io_port_pins_1_o_ie = T_7616_ie;
assign io_port_pins_1_o_pue = T_7616_pue;
assign io_port_pins_1_o_ds = T_7616_ds;
assign io_port_pins_2_o_oval = T_7659;
assign io_port_pins_2_o_oe = T_7652_oe;
assign io_port_pins_2_o_ie = T_7652_ie;
assign io_port_pins_2_o_pue = T_7652_pue;
assign io_port_pins_2_o_ds = T_7652_ds;
assign io_port_pins_3_o_oval = T_7695;
assign io_port_pins_3_o_oe = T_7688_oe;
assign io_port_pins_3_o_ie = T_7688_ie;
assign io_port_pins_3_o_pue = T_7688_pue;
assign io_port_pins_3_o_ds = T_7688_ds;
assign io_port_pins_4_o_oval = T_7731;
assign io_port_pins_4_o_oe = T_7724_oe;
assign io_port_pins_4_o_ie = T_7724_ie;
assign io_port_pins_4_o_pue = T_7724_pue;
assign io_port_pins_4_o_ds = T_7724_ds;
assign io_port_pins_5_o_oval = T_7767;
assign io_port_pins_5_o_oe = T_7760_oe;
assign io_port_pins_5_o_ie = T_7760_ie;
assign io_port_pins_5_o_pue = T_7760_pue;
assign io_port_pins_5_o_ds = T_7760_ds;
assign io_port_pins_6_o_oval = T_7803;
assign io_port_pins_6_o_oe = T_7796_oe;
assign io_port_pins_6_o_ie = T_7796_ie;
assign io_port_pins_6_o_pue = T_7796_pue;
assign io_port_pins_6_o_ds = T_7796_ds;
assign io_port_pins_7_o_oval = T_7839;
assign io_port_pins_7_o_oe = T_7832_oe;
assign io_port_pins_7_o_ie = T_7832_ie;
assign io_port_pins_7_o_pue = T_7832_pue;
assign io_port_pins_7_o_ds = T_7832_ds;
assign io_port_pins_8_o_oval = T_7875;
assign io_port_pins_8_o_oe = T_7868_oe;
assign io_port_pins_8_o_ie = T_7868_ie;
assign io_port_pins_8_o_pue = T_7868_pue;
assign io_port_pins_8_o_ds = T_7868_ds;
assign io_port_pins_9_o_oval = T_7911;
assign io_port_pins_9_o_oe = T_7904_oe;
assign io_port_pins_9_o_ie = T_7904_ie;
assign io_port_pins_9_o_pue = T_7904_pue;
assign io_port_pins_9_o_ds = T_7904_ds;
assign io_port_pins_10_o_oval = T_7947;
assign io_port_pins_10_o_oe = T_7940_oe;
assign io_port_pins_10_o_ie = T_7940_ie;
assign io_port_pins_10_o_pue = T_7940_pue;
assign io_port_pins_10_o_ds = T_7940_ds;
assign io_port_pins_11_o_oval = T_7983;
assign io_port_pins_11_o_oe = T_7976_oe;
assign io_port_pins_11_o_ie = T_7976_ie;
assign io_port_pins_11_o_pue = T_7976_pue;
assign io_port_pins_11_o_ds = T_7976_ds;
assign io_port_pins_12_o_oval = T_8019;
assign io_port_pins_12_o_oe = T_8012_oe;
assign io_port_pins_12_o_ie = T_8012_ie;
assign io_port_pins_12_o_pue = T_8012_pue;
assign io_port_pins_12_o_ds = T_8012_ds;
assign io_port_pins_13_o_oval = T_8055;
assign io_port_pins_13_o_oe = T_8048_oe;
assign io_port_pins_13_o_ie = T_8048_ie;
assign io_port_pins_13_o_pue = T_8048_pue;
assign io_port_pins_13_o_ds = T_8048_ds;
assign io_port_pins_14_o_oval = T_8091;
assign io_port_pins_14_o_oe = T_8084_oe;
assign io_port_pins_14_o_ie = T_8084_ie;
assign io_port_pins_14_o_pue = T_8084_pue;
assign io_port_pins_14_o_ds = T_8084_ds;
assign io_port_pins_15_o_oval = T_8127;
assign io_port_pins_15_o_oe = T_8120_oe;
assign io_port_pins_15_o_ie = T_8120_ie;
assign io_port_pins_15_o_pue = T_8120_pue;
assign io_port_pins_15_o_ds = T_8120_ds;
assign io_port_pins_16_o_oval = T_8163;
assign io_port_pins_16_o_oe = T_8156_oe;
assign io_port_pins_16_o_ie = T_8156_ie;
assign io_port_pins_16_o_pue = T_8156_pue;
assign io_port_pins_16_o_ds = T_8156_ds;
assign io_port_pins_17_o_oval = T_8199;
assign io_port_pins_17_o_oe = T_8192_oe;
assign io_port_pins_17_o_ie = T_8192_ie;
assign io_port_pins_17_o_pue = T_8192_pue;
assign io_port_pins_17_o_ds = T_8192_ds;
assign io_port_pins_18_o_oval = T_8235;
assign io_port_pins_18_o_oe = T_8228_oe;
assign io_port_pins_18_o_ie = T_8228_ie;
assign io_port_pins_18_o_pue = T_8228_pue;
assign io_port_pins_18_o_ds = T_8228_ds;
assign io_port_pins_19_o_oval = T_8271;
assign io_port_pins_19_o_oe = T_8264_oe;
assign io_port_pins_19_o_ie = T_8264_ie;
assign io_port_pins_19_o_pue = T_8264_pue;
assign io_port_pins_19_o_ds = T_8264_ds;
assign io_port_pins_20_o_oval = T_8307;
assign io_port_pins_20_o_oe = T_8300_oe;
assign io_port_pins_20_o_ie = T_8300_ie;
assign io_port_pins_20_o_pue = T_8300_pue;
assign io_port_pins_20_o_ds = T_8300_ds;
assign io_port_pins_21_o_oval = T_8343;
assign io_port_pins_21_o_oe = T_8336_oe;
assign io_port_pins_21_o_ie = T_8336_ie;
assign io_port_pins_21_o_pue = T_8336_pue;
assign io_port_pins_21_o_ds = T_8336_ds;
assign io_port_pins_22_o_oval = T_8379;
assign io_port_pins_22_o_oe = T_8372_oe;
assign io_port_pins_22_o_ie = T_8372_ie;
assign io_port_pins_22_o_pue = T_8372_pue;
assign io_port_pins_22_o_ds = T_8372_ds;
assign io_port_pins_23_o_oval = T_8415;
assign io_port_pins_23_o_oe = T_8408_oe;
assign io_port_pins_23_o_ie = T_8408_ie;
assign io_port_pins_23_o_pue = T_8408_pue;
assign io_port_pins_23_o_ds = T_8408_ds;
assign io_port_pins_24_o_oval = T_8451;
assign io_port_pins_24_o_oe = T_8444_oe;
assign io_port_pins_24_o_ie = T_8444_ie;
assign io_port_pins_24_o_pue = T_8444_pue;
assign io_port_pins_24_o_ds = T_8444_ds;
assign io_port_pins_25_o_oval = T_8487;
assign io_port_pins_25_o_oe = T_8480_oe;
assign io_port_pins_25_o_ie = T_8480_ie;
assign io_port_pins_25_o_pue = T_8480_pue;
assign io_port_pins_25_o_ds = T_8480_ds;
assign io_port_pins_26_o_oval = T_8523;
assign io_port_pins_26_o_oe = T_8516_oe;
assign io_port_pins_26_o_ie = T_8516_ie;
assign io_port_pins_26_o_pue = T_8516_pue;
assign io_port_pins_26_o_ds = T_8516_ds;
assign io_port_pins_27_o_oval = T_8559;
assign io_port_pins_27_o_oe = T_8552_oe;
assign io_port_pins_27_o_ie = T_8552_ie;
assign io_port_pins_27_o_pue = T_8552_pue;
assign io_port_pins_27_o_ds = T_8552_ds;
assign io_port_pins_28_o_oval = T_8595;
assign io_port_pins_28_o_oe = T_8588_oe;
assign io_port_pins_28_o_ie = T_8588_ie;
assign io_port_pins_28_o_pue = T_8588_pue;
assign io_port_pins_28_o_ds = T_8588_ds;
assign io_port_pins_29_o_oval = T_8631;
assign io_port_pins_29_o_oe = T_8624_oe;
assign io_port_pins_29_o_ie = T_8624_ie;
assign io_port_pins_29_o_pue = T_8624_pue;
assign io_port_pins_29_o_ds = T_8624_ds;
assign io_port_pins_30_o_oval = T_8667;
assign io_port_pins_30_o_oe = T_8660_oe;
assign io_port_pins_30_o_ie = T_8660_ie;
assign io_port_pins_30_o_pue = T_8660_pue;
assign io_port_pins_30_o_ds = T_8660_ds;
assign io_port_pins_31_o_oval = T_8703;
assign io_port_pins_31_o_oe = T_8696_oe;
assign io_port_pins_31_o_ie = T_8696_ie;
assign io_port_pins_31_o_pue = T_8696_pue;
assign io_port_pins_31_o_ds = T_8696_ds;
assign io_port_iof_0_0_i_ival = T_7603;
assign io_port_iof_0_1_i_ival = T_7639;
assign io_port_iof_0_2_i_ival = T_7675;
assign io_port_iof_0_3_i_ival = T_7711;
assign io_port_iof_0_4_i_ival = T_7747;
assign io_port_iof_0_5_i_ival = T_7783;
assign io_port_iof_0_6_i_ival = T_7819;
assign io_port_iof_0_7_i_ival = T_7855;
assign io_port_iof_0_8_i_ival = T_7891;
assign io_port_iof_0_9_i_ival = T_7927;
assign io_port_iof_0_10_i_ival = T_7963;
assign io_port_iof_0_11_i_ival = T_7999;
assign io_port_iof_0_12_i_ival = T_8035;
assign io_port_iof_0_13_i_ival = T_8071;
assign io_port_iof_0_14_i_ival = T_8107;
assign io_port_iof_0_15_i_ival = T_8143;
assign io_port_iof_0_16_i_ival = T_8179;
assign io_port_iof_0_17_i_ival = T_8215;
assign io_port_iof_0_18_i_ival = T_8251;
assign io_port_iof_0_19_i_ival = T_8287;
assign io_port_iof_0_20_i_ival = T_8323;
assign io_port_iof_0_21_i_ival = T_8359;
assign io_port_iof_0_22_i_ival = T_8395;
assign io_port_iof_0_23_i_ival = T_8431;
assign io_port_iof_0_24_i_ival = T_8467;
assign io_port_iof_0_25_i_ival = T_8503;
assign io_port_iof_0_26_i_ival = T_8539;
assign io_port_iof_0_27_i_ival = T_8575;
assign io_port_iof_0_28_i_ival = T_8611;
assign io_port_iof_0_29_i_ival = T_8647;
assign io_port_iof_0_30_i_ival = T_8683;
assign io_port_iof_0_31_i_ival = T_8719;
assign io_port_iof_1_0_i_ival = T_7603;
assign io_port_iof_1_1_i_ival = T_7639;
assign io_port_iof_1_2_i_ival = T_7675;
assign io_port_iof_1_3_i_ival = T_7711;
assign io_port_iof_1_4_i_ival = T_7747;
assign io_port_iof_1_5_i_ival = T_7783;
assign io_port_iof_1_6_i_ival = T_7819;
assign io_port_iof_1_7_i_ival = T_7855;
assign io_port_iof_1_8_i_ival = T_7891;
assign io_port_iof_1_9_i_ival = T_7927;
assign io_port_iof_1_10_i_ival = T_7963;
assign io_port_iof_1_11_i_ival = T_7999;
assign io_port_iof_1_12_i_ival = T_8035;
assign io_port_iof_1_13_i_ival = T_8071;
assign io_port_iof_1_14_i_ival = T_8107;
assign io_port_iof_1_15_i_ival = T_8143;
assign io_port_iof_1_16_i_ival = T_8179;
assign io_port_iof_1_17_i_ival = T_8215;
assign io_port_iof_1_18_i_ival = T_8251;
assign io_port_iof_1_19_i_ival = T_8287;
assign io_port_iof_1_20_i_ival = T_8323;
assign io_port_iof_1_21_i_ival = T_8359;
assign io_port_iof_1_22_i_ival = T_8395;
assign io_port_iof_1_23_i_ival = T_8431;
assign io_port_iof_1_24_i_ival = T_8467;
assign io_port_iof_1_25_i_ival = T_8503;
assign io_port_iof_1_26_i_ival = T_8539;
assign io_port_iof_1_27_i_ival = T_8575;
assign io_port_iof_1_28_i_ival = T_8611;
assign io_port_iof_1_29_i_ival = T_8647;
assign io_port_iof_1_30_i_ival = T_8683;
assign io_port_iof_1_31_i_ival = T_8719;
assign oeReg_clock = clock;
assign oeReg_reset = reset;
assign oeReg_io_d = T_3370_bits_data;
assign oeReg_io_en = T_4203;
assign pueReg_clock = clock;
assign pueReg_reset = reset;
assign pueReg_io_d = T_3370_bits_data;
assign pueReg_io_en = T_4495;
assign ieReg_clock = clock;
assign ieReg_reset = reset;
assign ieReg_io_d = T_3370_bits_data;
assign ieReg_io_en = T_4031;
assign inVal = T_3253;
assign T_3188_0 = io_port_pins_0_i_ival;
assign T_3188_1 = io_port_pins_1_i_ival;
assign T_3188_2 = io_port_pins_2_i_ival;
assign T_3188_3 = io_port_pins_3_i_ival;
assign T_3188_4 = io_port_pins_4_i_ival;
assign T_3188_5 = io_port_pins_5_i_ival;
assign T_3188_6 = io_port_pins_6_i_ival;
assign T_3188_7 = io_port_pins_7_i_ival;
assign T_3188_8 = io_port_pins_8_i_ival;
assign T_3188_9 = io_port_pins_9_i_ival;
assign T_3188_10 = io_port_pins_10_i_ival;
assign T_3188_11 = io_port_pins_11_i_ival;
assign T_3188_12 = io_port_pins_12_i_ival;
assign T_3188_13 = io_port_pins_13_i_ival;
assign T_3188_14 = io_port_pins_14_i_ival;
assign T_3188_15 = io_port_pins_15_i_ival;
assign T_3188_16 = io_port_pins_16_i_ival;
assign T_3188_17 = io_port_pins_17_i_ival;
assign T_3188_18 = io_port_pins_18_i_ival;
assign T_3188_19 = io_port_pins_19_i_ival;
assign T_3188_20 = io_port_pins_20_i_ival;
assign T_3188_21 = io_port_pins_21_i_ival;
assign T_3188_22 = io_port_pins_22_i_ival;
assign T_3188_23 = io_port_pins_23_i_ival;
assign T_3188_24 = io_port_pins_24_i_ival;
assign T_3188_25 = io_port_pins_25_i_ival;
assign T_3188_26 = io_port_pins_26_i_ival;
assign T_3188_27 = io_port_pins_27_i_ival;
assign T_3188_28 = io_port_pins_28_i_ival;
assign T_3188_29 = io_port_pins_29_i_ival;
assign T_3188_30 = io_port_pins_30_i_ival;
assign T_3188_31 = io_port_pins_31_i_ival;
assign T_3223 = {T_3188_1,T_3188_0};
assign T_3224 = {T_3188_3,T_3188_2};
assign T_3225 = {T_3224,T_3223};
assign T_3226 = {T_3188_5,T_3188_4};
assign T_3227 = {T_3188_7,T_3188_6};
assign T_3228 = {T_3227,T_3226};
assign T_3229 = {T_3228,T_3225};
assign T_3230 = {T_3188_9,T_3188_8};
assign T_3231 = {T_3188_11,T_3188_10};
assign T_3232 = {T_3231,T_3230};
assign T_3233 = {T_3188_13,T_3188_12};
assign T_3234 = {T_3188_15,T_3188_14};
assign T_3235 = {T_3234,T_3233};
assign T_3236 = {T_3235,T_3232};
assign T_3237 = {T_3236,T_3229};
assign T_3238 = {T_3188_17,T_3188_16};
assign T_3239 = {T_3188_19,T_3188_18};
assign T_3240 = {T_3239,T_3238};
assign T_3241 = {T_3188_21,T_3188_20};
assign T_3242 = {T_3188_23,T_3188_22};
assign T_3243 = {T_3242,T_3241};
assign T_3244 = {T_3243,T_3240};
assign T_3245 = {T_3188_25,T_3188_24};
assign T_3246 = {T_3188_27,T_3188_26};
assign T_3247 = {T_3246,T_3245};
assign T_3248 = {T_3188_29,T_3188_28};
assign T_3249 = {T_3188_31,T_3188_30};
assign T_3250 = {T_3249,T_3248};
assign T_3251 = {T_3250,T_3247};
assign T_3252 = {T_3251,T_3244};
assign T_3253 = {T_3252,T_3237};
assign iofEnReg_clock = clock;
assign iofEnReg_reset = reset;
assign iofEnReg_io_d = T_3370_bits_data;
assign iofEnReg_io_en = T_3991;
assign T_3269 = ~ valueReg;
assign rise = T_3269 & inSyncReg;
assign T_3270 = ~ inSyncReg;
assign fall = valueReg & T_3270;
assign T_3295_ready = T_5322;
assign T_3295_valid = io_in_0_a_valid;
assign T_3295_bits_read = T_3312;
assign T_3295_bits_index = T_3313[9:0];
assign T_3295_bits_data = io_in_0_a_bits_data;
assign T_3295_bits_mask = io_in_0_a_bits_mask;
assign T_3295_bits_extra = T_3316;
assign T_3312 = io_in_0_a_bits_opcode == 3'h4;
assign T_3313 = io_in_0_a_bits_address[28:2];
assign T_3314 = io_in_0_a_bits_address[1:0];
assign T_3315 = {T_3314,io_in_0_a_bits_source};
assign T_3316 = {T_3315,io_in_0_a_bits_size};
assign T_3334_ready = io_in_0_d_ready;
assign T_3334_valid = T_5325;
assign T_3334_bits_read = T_3370_bits_read;
assign T_3334_bits_data = T_6245;
assign T_3334_bits_extra = T_3370_bits_extra;
assign T_3370_ready = T_5324;
assign T_3370_valid = T_5323;
assign T_3370_bits_read = T_3295_bits_read;
assign T_3370_bits_index = T_3295_bits_index;
assign T_3370_bits_data = T_3295_bits_data;
assign T_3370_bits_mask = T_3295_bits_mask;
assign T_3370_bits_extra = T_3295_bits_extra;
assign T_3455 = T_3370_bits_index & 10'h3e0;
assign T_3457 = T_3455 == 10'h0;
assign T_3463 = T_3370_bits_index ^ 10'h5;
assign T_3464 = T_3463 & 10'h3e0;
assign T_3466 = T_3464 == 10'h0;
assign T_3472 = T_3370_bits_index ^ 10'ha;
assign T_3473 = T_3472 & 10'h3e0;
assign T_3475 = T_3473 == 10'h0;
assign T_3481 = T_3370_bits_index ^ 10'he;
assign T_3482 = T_3481 & 10'h3e0;
assign T_3484 = T_3482 == 10'h0;
assign T_3490 = T_3370_bits_index ^ 10'h1;
assign T_3491 = T_3490 & 10'h3e0;
assign T_3493 = T_3491 == 10'h0;
assign T_3499 = T_3370_bits_index ^ 10'h6;
assign T_3500 = T_3499 & 10'h3e0;
assign T_3502 = T_3500 == 10'h0;
assign T_3508 = T_3370_bits_index ^ 10'h9;
assign T_3509 = T_3508 & 10'h3e0;
assign T_3511 = T_3509 == 10'h0;
assign T_3517 = T_3370_bits_index ^ 10'hd;
assign T_3518 = T_3517 & 10'h3e0;
assign T_3520 = T_3518 == 10'h0;
assign T_3526 = T_3370_bits_index ^ 10'h2;
assign T_3527 = T_3526 & 10'h3e0;
assign T_3529 = T_3527 == 10'h0;
assign T_3535 = T_3370_bits_index ^ 10'hc;
assign T_3536 = T_3535 & 10'h3e0;
assign T_3538 = T_3536 == 10'h0;
assign T_3544 = T_3370_bits_index ^ 10'h7;
assign T_3545 = T_3544 & 10'h3e0;
assign T_3547 = T_3545 == 10'h0;
assign T_3553 = T_3370_bits_index ^ 10'h3;
assign T_3554 = T_3553 & 10'h3e0;
assign T_3556 = T_3554 == 10'h0;
assign T_3562 = T_3370_bits_index ^ 10'h10;
assign T_3563 = T_3562 & 10'h3e0;
assign T_3565 = T_3563 == 10'h0;
assign T_3571 = T_3370_bits_index ^ 10'hb;
assign T_3572 = T_3571 & 10'h3e0;
assign T_3574 = T_3572 == 10'h0;
assign T_3580 = T_3370_bits_index ^ 10'h8;
assign T_3581 = T_3580 & 10'h3e0;
assign T_3583 = T_3581 == 10'h0;
assign T_3589 = T_3370_bits_index ^ 10'h4;
assign T_3590 = T_3589 & 10'h3e0;
assign T_3592 = T_3590 == 10'h0;
assign T_3598 = T_3370_bits_index ^ 10'hf;
assign T_3599 = T_3598 & 10'h3e0;
assign T_3601 = T_3599 == 10'h0;
assign T_3609_0 = T_5397;
assign T_3609_1 = T_5497;
assign T_3609_2 = T_5597;
assign T_3609_3 = T_5677;
assign T_3609_4 = T_5417;
assign T_3609_5 = T_5517;
assign T_3609_6 = T_5577;
assign T_3609_7 = T_5657;
assign T_3609_8 = T_5437;
assign T_3609_9 = T_5637;
assign T_3609_10 = T_5537;
assign T_3609_11 = T_5457;
assign T_3609_12 = T_5717;
assign T_3609_13 = T_5617;
assign T_3609_14 = T_5557;
assign T_3609_15 = T_5477;
assign T_3609_16 = T_5697;
assign T_3614_0 = T_5403;
assign T_3614_1 = T_5503;
assign T_3614_2 = T_5603;
assign T_3614_3 = T_5683;
assign T_3614_4 = T_5423;
assign T_3614_5 = T_5523;
assign T_3614_6 = T_5583;
assign T_3614_7 = T_5663;
assign T_3614_8 = T_5443;
assign T_3614_9 = T_5643;
assign T_3614_10 = T_5543;
assign T_3614_11 = T_5463;
assign T_3614_12 = T_5723;
assign T_3614_13 = T_5623;
assign T_3614_14 = T_5563;
assign T_3614_15 = T_5483;
assign T_3614_16 = T_5703;
assign T_3619_0 = 1'h1;
assign T_3619_1 = 1'h1;
assign T_3619_2 = 1'h1;
assign T_3619_3 = 1'h1;
assign T_3619_4 = 1'h1;
assign T_3619_5 = 1'h1;
assign T_3619_6 = 1'h1;
assign T_3619_7 = 1'h1;
assign T_3619_8 = 1'h1;
assign T_3619_9 = 1'h1;
assign T_3619_10 = 1'h1;
assign T_3619_11 = 1'h1;
assign T_3619_12 = 1'h1;
assign T_3619_13 = 1'h1;
assign T_3619_14 = 1'h1;
assign T_3619_15 = 1'h1;
assign T_3619_16 = 1'h1;
assign T_3624_0 = 1'h1;
assign T_3624_1 = 1'h1;
assign T_3624_2 = 1'h1;
assign T_3624_3 = 1'h1;
assign T_3624_4 = 1'h1;
assign T_3624_5 = 1'h1;
assign T_3624_6 = 1'h1;
assign T_3624_7 = 1'h1;
assign T_3624_8 = 1'h1;
assign T_3624_9 = 1'h1;
assign T_3624_10 = 1'h1;
assign T_3624_11 = 1'h1;
assign T_3624_12 = 1'h1;
assign T_3624_13 = 1'h1;
assign T_3624_14 = 1'h1;
assign T_3624_15 = 1'h1;
assign T_3624_16 = 1'h1;
assign T_3629_0 = 1'h1;
assign T_3629_1 = 1'h1;
assign T_3629_2 = 1'h1;
assign T_3629_3 = 1'h1;
assign T_3629_4 = 1'h1;
assign T_3629_5 = 1'h1;
assign T_3629_6 = 1'h1;
assign T_3629_7 = 1'h1;
assign T_3629_8 = 1'h1;
assign T_3629_9 = 1'h1;
assign T_3629_10 = 1'h1;
assign T_3629_11 = 1'h1;
assign T_3629_12 = 1'h1;
assign T_3629_13 = 1'h1;
assign T_3629_14 = 1'h1;
assign T_3629_15 = 1'h1;
assign T_3629_16 = 1'h1;
assign T_3634_0 = 1'h1;
assign T_3634_1 = 1'h1;
assign T_3634_2 = 1'h1;
assign T_3634_3 = 1'h1;
assign T_3634_4 = 1'h1;
assign T_3634_5 = 1'h1;
assign T_3634_6 = 1'h1;
assign T_3634_7 = 1'h1;
assign T_3634_8 = 1'h1;
assign T_3634_9 = 1'h1;
assign T_3634_10 = 1'h1;
assign T_3634_11 = 1'h1;
assign T_3634_12 = 1'h1;
assign T_3634_13 = 1'h1;
assign T_3634_14 = 1'h1;
assign T_3634_15 = 1'h1;
assign T_3634_16 = 1'h1;
assign T_3639_0 = T_5407;
assign T_3639_1 = T_5507;
assign T_3639_2 = T_5607;
assign T_3639_3 = T_5687;
assign T_3639_4 = T_5427;
assign T_3639_5 = T_5527;
assign T_3639_6 = T_5587;
assign T_3639_7 = T_5667;
assign T_3639_8 = T_5447;
assign T_3639_9 = T_5647;
assign T_3639_10 = T_5547;
assign T_3639_11 = T_5467;
assign T_3639_12 = T_5727;
assign T_3639_13 = T_5627;
assign T_3639_14 = T_5567;
assign T_3639_15 = T_5487;
assign T_3639_16 = T_5707;
assign T_3644_0 = T_5413;
assign T_3644_1 = T_5513;
assign T_3644_2 = T_5613;
assign T_3644_3 = T_5693;
assign T_3644_4 = T_5433;
assign T_3644_5 = T_5533;
assign T_3644_6 = T_5593;
assign T_3644_7 = T_5673;
assign T_3644_8 = T_5453;
assign T_3644_9 = T_5653;
assign T_3644_10 = T_5553;
assign T_3644_11 = T_5473;
assign T_3644_12 = T_5733;
assign T_3644_13 = T_5633;
assign T_3644_14 = T_5573;
assign T_3644_15 = T_5493;
assign T_3644_16 = T_5713;
assign T_3806 = T_3370_bits_mask[0];
assign T_3807 = T_3370_bits_mask[1];
assign T_3808 = T_3370_bits_mask[2];
assign T_3809 = T_3370_bits_mask[3];
assign T_3813 = T_3806 ? 8'hff : 8'h0;
assign T_3817 = T_3807 ? 8'hff : 8'h0;
assign T_3821 = T_3808 ? 8'hff : 8'h0;
assign T_3825 = T_3809 ? 8'hff : 8'h0;
assign T_3826 = {T_3817,T_3813};
assign T_3827 = {T_3825,T_3821};
assign T_3828 = {T_3827,T_3826};
assign T_3856 = ~ T_3828;
assign T_3858 = T_3856 == 32'h0;
assign T_3911 = T_3644_1 & T_3858;
assign GEN_7 = T_3911 ? T_3370_bits_data : dsReg;
assign T_3951 = T_3644_2 & T_3858;
assign GEN_8 = T_3951 ? T_3370_bits_data : highIeReg;
assign T_3991 = T_3644_3 & T_3858;
assign T_4007 = iofEnReg_io_q;
assign T_4031 = T_3644_4 & T_3858;
assign T_4047 = ieReg_io_q;
assign T_4071 = T_3644_5 & T_3858;
assign GEN_9 = T_4071 ? T_3370_bits_data : riseIeReg;
assign T_4111 = T_3644_6 & T_3858;
assign T_4114 = ~ fallIpReg;
assign T_4116 = T_4111 ? T_3370_bits_data : 32'h0;
assign T_4117 = T_4114 | T_4116;
assign T_4118 = ~ T_4117;
assign T_4119 = T_4118 | fall;
assign T_4157 = T_3644_7 & T_3858;
assign T_4160 = ~ lowIpReg;
assign T_4162 = T_4157 ? T_3370_bits_data : 32'h0;
assign T_4163 = T_4160 | T_4162;
assign T_4164 = ~ T_4163;
assign T_4165 = T_4164 | T_3269;
assign T_4203 = T_3644_8 & T_3858;
assign T_4219 = oeReg_io_q;
assign T_4243 = T_3644_9 & T_3858;
assign GEN_10 = T_4243 ? T_3370_bits_data : lowIeReg;
assign T_4283 = T_3644_10 & T_3858;
assign T_4286 = ~ riseIpReg;
assign T_4288 = T_4283 ? T_3370_bits_data : 32'h0;
assign T_4289 = T_4286 | T_4288;
assign T_4290 = ~ T_4289;
assign T_4291 = T_4290 | rise;
assign T_4329 = T_3644_11 & T_3858;
assign GEN_11 = T_4329 ? T_3370_bits_data : portReg;
assign T_4369 = T_3644_12 & T_3858;
assign GEN_12 = T_4369 ? T_3370_bits_data : xorReg;
assign T_4409 = T_3644_13 & T_3858;
assign T_4412 = ~ highIpReg;
assign T_4414 = T_4409 ? T_3370_bits_data : 32'h0;
assign T_4415 = T_4412 | T_4414;
assign T_4416 = ~ T_4415;
assign T_4417 = T_4416 | valueReg;
assign T_4455 = T_3644_14 & T_3858;
assign GEN_13 = T_4455 ? T_3370_bits_data : fallIeReg;
assign T_4495 = T_3644_15 & T_3858;
assign T_4511 = pueReg_io_q;
assign T_4535 = T_3644_16 & T_3858;
assign GEN_14 = T_4535 ? T_3370_bits_data : iofSelReg;
assign T_4557 = T_3457 == 1'h0;
assign T_4559 = T_4557 | T_3619_0;
assign T_4561 = T_3493 == 1'h0;
assign T_4563 = T_4561 | T_3619_4;
assign T_4565 = T_3529 == 1'h0;
assign T_4567 = T_4565 | T_3619_8;
assign T_4569 = T_3556 == 1'h0;
assign T_4571 = T_4569 | T_3619_11;
assign T_4573 = T_3592 == 1'h0;
assign T_4575 = T_4573 | T_3619_15;
assign T_4577 = T_3466 == 1'h0;
assign T_4579 = T_4577 | T_3619_1;
assign T_4581 = T_3502 == 1'h0;
assign T_4583 = T_4581 | T_3619_5;
assign T_4585 = T_3547 == 1'h0;
assign T_4587 = T_4585 | T_3619_10;
assign T_4589 = T_3583 == 1'h0;
assign T_4591 = T_4589 | T_3619_14;
assign T_4593 = T_3511 == 1'h0;
assign T_4595 = T_4593 | T_3619_6;
assign T_4597 = T_3475 == 1'h0;
assign T_4599 = T_4597 | T_3619_2;
assign T_4601 = T_3574 == 1'h0;
assign T_4603 = T_4601 | T_3619_13;
assign T_4605 = T_3538 == 1'h0;
assign T_4607 = T_4605 | T_3619_9;
assign T_4609 = T_3520 == 1'h0;
assign T_4611 = T_4609 | T_3619_7;
assign T_4613 = T_3484 == 1'h0;
assign T_4615 = T_4613 | T_3619_3;
assign T_4617 = T_3601 == 1'h0;
assign T_4619 = T_4617 | T_3619_16;
assign T_4621 = T_3565 == 1'h0;
assign T_4623 = T_4621 | T_3619_12;
assign T_4704_0 = T_4559;
assign T_4704_1 = T_4563;
assign T_4704_2 = T_4567;
assign T_4704_3 = T_4571;
assign T_4704_4 = T_4575;
assign T_4704_5 = T_4579;
assign T_4704_6 = T_4583;
assign T_4704_7 = T_4587;
assign T_4704_8 = T_4591;
assign T_4704_9 = T_4595;
assign T_4704_10 = T_4599;
assign T_4704_11 = T_4603;
assign T_4704_12 = T_4607;
assign T_4704_13 = T_4611;
assign T_4704_14 = T_4615;
assign T_4704_15 = T_4619;
assign T_4704_16 = T_4623;
assign T_4704_17 = 1'h1;
assign T_4704_18 = 1'h1;
assign T_4704_19 = 1'h1;
assign T_4704_20 = 1'h1;
assign T_4704_21 = 1'h1;
assign T_4704_22 = 1'h1;
assign T_4704_23 = 1'h1;
assign T_4704_24 = 1'h1;
assign T_4704_25 = 1'h1;
assign T_4704_26 = 1'h1;
assign T_4704_27 = 1'h1;
assign T_4704_28 = 1'h1;
assign T_4704_29 = 1'h1;
assign T_4704_30 = 1'h1;
assign T_4704_31 = 1'h1;
assign T_4742 = T_4557 | T_3624_0;
assign T_4746 = T_4561 | T_3624_4;
assign T_4750 = T_4565 | T_3624_8;
assign T_4754 = T_4569 | T_3624_11;
assign T_4758 = T_4573 | T_3624_15;
assign T_4762 = T_4577 | T_3624_1;
assign T_4766 = T_4581 | T_3624_5;
assign T_4770 = T_4585 | T_3624_10;
assign T_4774 = T_4589 | T_3624_14;
assign T_4778 = T_4593 | T_3624_6;
assign T_4782 = T_4597 | T_3624_2;
assign T_4786 = T_4601 | T_3624_13;
assign T_4790 = T_4605 | T_3624_9;
assign T_4794 = T_4609 | T_3624_7;
assign T_4798 = T_4613 | T_3624_3;
assign T_4802 = T_4617 | T_3624_16;
assign T_4806 = T_4621 | T_3624_12;
assign T_4887_0 = T_4742;
assign T_4887_1 = T_4746;
assign T_4887_2 = T_4750;
assign T_4887_3 = T_4754;
assign T_4887_4 = T_4758;
assign T_4887_5 = T_4762;
assign T_4887_6 = T_4766;
assign T_4887_7 = T_4770;
assign T_4887_8 = T_4774;
assign T_4887_9 = T_4778;
assign T_4887_10 = T_4782;
assign T_4887_11 = T_4786;
assign T_4887_12 = T_4790;
assign T_4887_13 = T_4794;
assign T_4887_14 = T_4798;
assign T_4887_15 = T_4802;
assign T_4887_16 = T_4806;
assign T_4887_17 = 1'h1;
assign T_4887_18 = 1'h1;
assign T_4887_19 = 1'h1;
assign T_4887_20 = 1'h1;
assign T_4887_21 = 1'h1;
assign T_4887_22 = 1'h1;
assign T_4887_23 = 1'h1;
assign T_4887_24 = 1'h1;
assign T_4887_25 = 1'h1;
assign T_4887_26 = 1'h1;
assign T_4887_27 = 1'h1;
assign T_4887_28 = 1'h1;
assign T_4887_29 = 1'h1;
assign T_4887_30 = 1'h1;
assign T_4887_31 = 1'h1;
assign T_4925 = T_4557 | T_3629_0;
assign T_4929 = T_4561 | T_3629_4;
assign T_4933 = T_4565 | T_3629_8;
assign T_4937 = T_4569 | T_3629_11;
assign T_4941 = T_4573 | T_3629_15;
assign T_4945 = T_4577 | T_3629_1;
assign T_4949 = T_4581 | T_3629_5;
assign T_4953 = T_4585 | T_3629_10;
assign T_4957 = T_4589 | T_3629_14;
assign T_4961 = T_4593 | T_3629_6;
assign T_4965 = T_4597 | T_3629_2;
assign T_4969 = T_4601 | T_3629_13;
assign T_4973 = T_4605 | T_3629_9;
assign T_4977 = T_4609 | T_3629_7;
assign T_4981 = T_4613 | T_3629_3;
assign T_4985 = T_4617 | T_3629_16;
assign T_4989 = T_4621 | T_3629_12;
assign T_5070_0 = T_4925;
assign T_5070_1 = T_4929;
assign T_5070_2 = T_4933;
assign T_5070_3 = T_4937;
assign T_5070_4 = T_4941;
assign T_5070_5 = T_4945;
assign T_5070_6 = T_4949;
assign T_5070_7 = T_4953;
assign T_5070_8 = T_4957;
assign T_5070_9 = T_4961;
assign T_5070_10 = T_4965;
assign T_5070_11 = T_4969;
assign T_5070_12 = T_4973;
assign T_5070_13 = T_4977;
assign T_5070_14 = T_4981;
assign T_5070_15 = T_4985;
assign T_5070_16 = T_4989;
assign T_5070_17 = 1'h1;
assign T_5070_18 = 1'h1;
assign T_5070_19 = 1'h1;
assign T_5070_20 = 1'h1;
assign T_5070_21 = 1'h1;
assign T_5070_22 = 1'h1;
assign T_5070_23 = 1'h1;
assign T_5070_24 = 1'h1;
assign T_5070_25 = 1'h1;
assign T_5070_26 = 1'h1;
assign T_5070_27 = 1'h1;
assign T_5070_28 = 1'h1;
assign T_5070_29 = 1'h1;
assign T_5070_30 = 1'h1;
assign T_5070_31 = 1'h1;
assign T_5108 = T_4557 | T_3634_0;
assign T_5112 = T_4561 | T_3634_4;
assign T_5116 = T_4565 | T_3634_8;
assign T_5120 = T_4569 | T_3634_11;
assign T_5124 = T_4573 | T_3634_15;
assign T_5128 = T_4577 | T_3634_1;
assign T_5132 = T_4581 | T_3634_5;
assign T_5136 = T_4585 | T_3634_10;
assign T_5140 = T_4589 | T_3634_14;
assign T_5144 = T_4593 | T_3634_6;
assign T_5148 = T_4597 | T_3634_2;
assign T_5152 = T_4601 | T_3634_13;
assign T_5156 = T_4605 | T_3634_9;
assign T_5160 = T_4609 | T_3634_7;
assign T_5164 = T_4613 | T_3634_3;
assign T_5168 = T_4617 | T_3634_16;
assign T_5172 = T_4621 | T_3634_12;
assign T_5253_0 = T_5108;
assign T_5253_1 = T_5112;
assign T_5253_2 = T_5116;
assign T_5253_3 = T_5120;
assign T_5253_4 = T_5124;
assign T_5253_5 = T_5128;
assign T_5253_6 = T_5132;
assign T_5253_7 = T_5136;
assign T_5253_8 = T_5140;
assign T_5253_9 = T_5144;
assign T_5253_10 = T_5148;
assign T_5253_11 = T_5152;
assign T_5253_12 = T_5156;
assign T_5253_13 = T_5160;
assign T_5253_14 = T_5164;
assign T_5253_15 = T_5168;
assign T_5253_16 = T_5172;
assign T_5253_17 = 1'h1;
assign T_5253_18 = 1'h1;
assign T_5253_19 = 1'h1;
assign T_5253_20 = 1'h1;
assign T_5253_21 = 1'h1;
assign T_5253_22 = 1'h1;
assign T_5253_23 = 1'h1;
assign T_5253_24 = 1'h1;
assign T_5253_25 = 1'h1;
assign T_5253_26 = 1'h1;
assign T_5253_27 = 1'h1;
assign T_5253_28 = 1'h1;
assign T_5253_29 = 1'h1;
assign T_5253_30 = 1'h1;
assign T_5253_31 = 1'h1;
assign T_5288 = T_3370_bits_index[0];
assign T_5289 = T_3370_bits_index[1];
assign T_5290 = T_3370_bits_index[2];
assign T_5291 = T_3370_bits_index[3];
assign T_5292 = T_3370_bits_index[4];
assign T_5298 = {T_5289,T_5288};
assign T_5299 = {T_5292,T_5291};
assign T_5300 = {T_5299,T_5290};
assign T_5301 = {T_5300,T_5298};
assign GEN_0 = GEN_45;
assign GEN_15 = 5'h1 == T_5301 ? T_4704_1 : T_4704_0;
assign GEN_16 = 5'h2 == T_5301 ? T_4704_2 : GEN_15;
assign GEN_17 = 5'h3 == T_5301 ? T_4704_3 : GEN_16;
assign GEN_18 = 5'h4 == T_5301 ? T_4704_4 : GEN_17;
assign GEN_19 = 5'h5 == T_5301 ? T_4704_5 : GEN_18;
assign GEN_20 = 5'h6 == T_5301 ? T_4704_6 : GEN_19;
assign GEN_21 = 5'h7 == T_5301 ? T_4704_7 : GEN_20;
assign GEN_22 = 5'h8 == T_5301 ? T_4704_8 : GEN_21;
assign GEN_23 = 5'h9 == T_5301 ? T_4704_9 : GEN_22;
assign GEN_24 = 5'ha == T_5301 ? T_4704_10 : GEN_23;
assign GEN_25 = 5'hb == T_5301 ? T_4704_11 : GEN_24;
assign GEN_26 = 5'hc == T_5301 ? T_4704_12 : GEN_25;
assign GEN_27 = 5'hd == T_5301 ? T_4704_13 : GEN_26;
assign GEN_28 = 5'he == T_5301 ? T_4704_14 : GEN_27;
assign GEN_29 = 5'hf == T_5301 ? T_4704_15 : GEN_28;
assign GEN_30 = 5'h10 == T_5301 ? T_4704_16 : GEN_29;
assign GEN_31 = 5'h11 == T_5301 ? T_4704_17 : GEN_30;
assign GEN_32 = 5'h12 == T_5301 ? T_4704_18 : GEN_31;
assign GEN_33 = 5'h13 == T_5301 ? T_4704_19 : GEN_32;
assign GEN_34 = 5'h14 == T_5301 ? T_4704_20 : GEN_33;
assign GEN_35 = 5'h15 == T_5301 ? T_4704_21 : GEN_34;
assign GEN_36 = 5'h16 == T_5301 ? T_4704_22 : GEN_35;
assign GEN_37 = 5'h17 == T_5301 ? T_4704_23 : GEN_36;
assign GEN_38 = 5'h18 == T_5301 ? T_4704_24 : GEN_37;
assign GEN_39 = 5'h19 == T_5301 ? T_4704_25 : GEN_38;
assign GEN_40 = 5'h1a == T_5301 ? T_4704_26 : GEN_39;
assign GEN_41 = 5'h1b == T_5301 ? T_4704_27 : GEN_40;
assign GEN_42 = 5'h1c == T_5301 ? T_4704_28 : GEN_41;
assign GEN_43 = 5'h1d == T_5301 ? T_4704_29 : GEN_42;
assign GEN_44 = 5'h1e == T_5301 ? T_4704_30 : GEN_43;
assign GEN_45 = 5'h1f == T_5301 ? T_4704_31 : GEN_44;
assign GEN_1 = GEN_76;
assign GEN_46 = 5'h1 == T_5301 ? T_4887_1 : T_4887_0;
assign GEN_47 = 5'h2 == T_5301 ? T_4887_2 : GEN_46;
assign GEN_48 = 5'h3 == T_5301 ? T_4887_3 : GEN_47;
assign GEN_49 = 5'h4 == T_5301 ? T_4887_4 : GEN_48;
assign GEN_50 = 5'h5 == T_5301 ? T_4887_5 : GEN_49;
assign GEN_51 = 5'h6 == T_5301 ? T_4887_6 : GEN_50;
assign GEN_52 = 5'h7 == T_5301 ? T_4887_7 : GEN_51;
assign GEN_53 = 5'h8 == T_5301 ? T_4887_8 : GEN_52;
assign GEN_54 = 5'h9 == T_5301 ? T_4887_9 : GEN_53;
assign GEN_55 = 5'ha == T_5301 ? T_4887_10 : GEN_54;
assign GEN_56 = 5'hb == T_5301 ? T_4887_11 : GEN_55;
assign GEN_57 = 5'hc == T_5301 ? T_4887_12 : GEN_56;
assign GEN_58 = 5'hd == T_5301 ? T_4887_13 : GEN_57;
assign GEN_59 = 5'he == T_5301 ? T_4887_14 : GEN_58;
assign GEN_60 = 5'hf == T_5301 ? T_4887_15 : GEN_59;
assign GEN_61 = 5'h10 == T_5301 ? T_4887_16 : GEN_60;
assign GEN_62 = 5'h11 == T_5301 ? T_4887_17 : GEN_61;
assign GEN_63 = 5'h12 == T_5301 ? T_4887_18 : GEN_62;
assign GEN_64 = 5'h13 == T_5301 ? T_4887_19 : GEN_63;
assign GEN_65 = 5'h14 == T_5301 ? T_4887_20 : GEN_64;
assign GEN_66 = 5'h15 == T_5301 ? T_4887_21 : GEN_65;
assign GEN_67 = 5'h16 == T_5301 ? T_4887_22 : GEN_66;
assign GEN_68 = 5'h17 == T_5301 ? T_4887_23 : GEN_67;
assign GEN_69 = 5'h18 == T_5301 ? T_4887_24 : GEN_68;
assign GEN_70 = 5'h19 == T_5301 ? T_4887_25 : GEN_69;
assign GEN_71 = 5'h1a == T_5301 ? T_4887_26 : GEN_70;
assign GEN_72 = 5'h1b == T_5301 ? T_4887_27 : GEN_71;
assign GEN_73 = 5'h1c == T_5301 ? T_4887_28 : GEN_72;
assign GEN_74 = 5'h1d == T_5301 ? T_4887_29 : GEN_73;
assign GEN_75 = 5'h1e == T_5301 ? T_4887_30 : GEN_74;
assign GEN_76 = 5'h1f == T_5301 ? T_4887_31 : GEN_75;
assign T_5318 = T_3370_bits_read ? GEN_0 : GEN_1;
assign GEN_2 = GEN_107;
assign GEN_77 = 5'h1 == T_5301 ? T_5070_1 : T_5070_0;
assign GEN_78 = 5'h2 == T_5301 ? T_5070_2 : GEN_77;
assign GEN_79 = 5'h3 == T_5301 ? T_5070_3 : GEN_78;
assign GEN_80 = 5'h4 == T_5301 ? T_5070_4 : GEN_79;
assign GEN_81 = 5'h5 == T_5301 ? T_5070_5 : GEN_80;
assign GEN_82 = 5'h6 == T_5301 ? T_5070_6 : GEN_81;
assign GEN_83 = 5'h7 == T_5301 ? T_5070_7 : GEN_82;
assign GEN_84 = 5'h8 == T_5301 ? T_5070_8 : GEN_83;
assign GEN_85 = 5'h9 == T_5301 ? T_5070_9 : GEN_84;
assign GEN_86 = 5'ha == T_5301 ? T_5070_10 : GEN_85;
assign GEN_87 = 5'hb == T_5301 ? T_5070_11 : GEN_86;
assign GEN_88 = 5'hc == T_5301 ? T_5070_12 : GEN_87;
assign GEN_89 = 5'hd == T_5301 ? T_5070_13 : GEN_88;
assign GEN_90 = 5'he == T_5301 ? T_5070_14 : GEN_89;
assign GEN_91 = 5'hf == T_5301 ? T_5070_15 : GEN_90;
assign GEN_92 = 5'h10 == T_5301 ? T_5070_16 : GEN_91;
assign GEN_93 = 5'h11 == T_5301 ? T_5070_17 : GEN_92;
assign GEN_94 = 5'h12 == T_5301 ? T_5070_18 : GEN_93;
assign GEN_95 = 5'h13 == T_5301 ? T_5070_19 : GEN_94;
assign GEN_96 = 5'h14 == T_5301 ? T_5070_20 : GEN_95;
assign GEN_97 = 5'h15 == T_5301 ? T_5070_21 : GEN_96;
assign GEN_98 = 5'h16 == T_5301 ? T_5070_22 : GEN_97;
assign GEN_99 = 5'h17 == T_5301 ? T_5070_23 : GEN_98;
assign GEN_100 = 5'h18 == T_5301 ? T_5070_24 : GEN_99;
assign GEN_101 = 5'h19 == T_5301 ? T_5070_25 : GEN_100;
assign GEN_102 = 5'h1a == T_5301 ? T_5070_26 : GEN_101;
assign GEN_103 = 5'h1b == T_5301 ? T_5070_27 : GEN_102;
assign GEN_104 = 5'h1c == T_5301 ? T_5070_28 : GEN_103;
assign GEN_105 = 5'h1d == T_5301 ? T_5070_29 : GEN_104;
assign GEN_106 = 5'h1e == T_5301 ? T_5070_30 : GEN_105;
assign GEN_107 = 5'h1f == T_5301 ? T_5070_31 : GEN_106;
assign GEN_3 = GEN_138;
assign GEN_108 = 5'h1 == T_5301 ? T_5253_1 : T_5253_0;
assign GEN_109 = 5'h2 == T_5301 ? T_5253_2 : GEN_108;
assign GEN_110 = 5'h3 == T_5301 ? T_5253_3 : GEN_109;
assign GEN_111 = 5'h4 == T_5301 ? T_5253_4 : GEN_110;
assign GEN_112 = 5'h5 == T_5301 ? T_5253_5 : GEN_111;
assign GEN_113 = 5'h6 == T_5301 ? T_5253_6 : GEN_112;
assign GEN_114 = 5'h7 == T_5301 ? T_5253_7 : GEN_113;
assign GEN_115 = 5'h8 == T_5301 ? T_5253_8 : GEN_114;
assign GEN_116 = 5'h9 == T_5301 ? T_5253_9 : GEN_115;
assign GEN_117 = 5'ha == T_5301 ? T_5253_10 : GEN_116;
assign GEN_118 = 5'hb == T_5301 ? T_5253_11 : GEN_117;
assign GEN_119 = 5'hc == T_5301 ? T_5253_12 : GEN_118;
assign GEN_120 = 5'hd == T_5301 ? T_5253_13 : GEN_119;
assign GEN_121 = 5'he == T_5301 ? T_5253_14 : GEN_120;
assign GEN_122 = 5'hf == T_5301 ? T_5253_15 : GEN_121;
assign GEN_123 = 5'h10 == T_5301 ? T_5253_16 : GEN_122;
assign GEN_124 = 5'h11 == T_5301 ? T_5253_17 : GEN_123;
assign GEN_125 = 5'h12 == T_5301 ? T_5253_18 : GEN_124;
assign GEN_126 = 5'h13 == T_5301 ? T_5253_19 : GEN_125;
assign GEN_127 = 5'h14 == T_5301 ? T_5253_20 : GEN_126;
assign GEN_128 = 5'h15 == T_5301 ? T_5253_21 : GEN_127;
assign GEN_129 = 5'h16 == T_5301 ? T_5253_22 : GEN_128;
assign GEN_130 = 5'h17 == T_5301 ? T_5253_23 : GEN_129;
assign GEN_131 = 5'h18 == T_5301 ? T_5253_24 : GEN_130;
assign GEN_132 = 5'h19 == T_5301 ? T_5253_25 : GEN_131;
assign GEN_133 = 5'h1a == T_5301 ? T_5253_26 : GEN_132;
assign GEN_134 = 5'h1b == T_5301 ? T_5253_27 : GEN_133;
assign GEN_135 = 5'h1c == T_5301 ? T_5253_28 : GEN_134;
assign GEN_136 = 5'h1d == T_5301 ? T_5253_29 : GEN_135;
assign GEN_137 = 5'h1e == T_5301 ? T_5253_30 : GEN_136;
assign GEN_138 = 5'h1f == T_5301 ? T_5253_31 : GEN_137;
assign T_5321 = T_3370_bits_read ? GEN_2 : GEN_3;
assign T_5322 = T_3370_ready & T_5318;
assign T_5323 = T_3295_valid & T_5318;
assign T_5324 = T_3334_ready & T_5321;
assign T_5325 = T_3370_valid & T_5321;
assign T_5327 = 32'h1 << T_5301;
assign T_5328 = {T_3493,T_3457};
assign T_5329 = {T_3556,T_3529};
assign T_5330 = {T_5329,T_5328};
assign T_5331 = {T_3466,T_3592};
assign T_5332 = {T_3547,T_3502};
assign T_5333 = {T_5332,T_5331};
assign T_5334 = {T_5333,T_5330};
assign T_5335 = {T_3511,T_3583};
assign T_5336 = {T_3574,T_3475};
assign T_5337 = {T_5336,T_5335};
assign T_5338 = {T_3520,T_3538};
assign T_5339 = {T_3601,T_3484};
assign T_5340 = {T_5339,T_5338};
assign T_5341 = {T_5340,T_5337};
assign T_5342 = {T_5341,T_5334};
assign T_5343 = {1'h1,T_3565};
assign T_5345 = {2'h3,T_5343};
assign T_5349 = {4'hf,T_5345};
assign T_5357 = {8'hff,T_5349};
assign T_5358 = {T_5357,T_5342};
assign T_5359 = T_5327 & T_5358;
assign T_5394 = T_3295_valid & T_3370_ready;
assign T_5395 = T_5394 & T_3370_bits_read;
assign T_5396 = T_5359[0];
assign T_5397 = T_5395 & T_5396;
assign T_5400 = T_3370_bits_read == 1'h0;
assign T_5401 = T_5394 & T_5400;
assign T_5403 = T_5401 & T_5396;
assign T_5404 = T_3370_valid & T_3334_ready;
assign T_5405 = T_5404 & T_3370_bits_read;
assign T_5407 = T_5405 & T_5396;
assign T_5411 = T_5404 & T_5400;
assign T_5413 = T_5411 & T_5396;
assign T_5416 = T_5359[1];
assign T_5417 = T_5395 & T_5416;
assign T_5423 = T_5401 & T_5416;
assign T_5427 = T_5405 & T_5416;
assign T_5433 = T_5411 & T_5416;
assign T_5436 = T_5359[2];
assign T_5437 = T_5395 & T_5436;
assign T_5443 = T_5401 & T_5436;
assign T_5447 = T_5405 & T_5436;
assign T_5453 = T_5411 & T_5436;
assign T_5456 = T_5359[3];
assign T_5457 = T_5395 & T_5456;
assign T_5463 = T_5401 & T_5456;
assign T_5467 = T_5405 & T_5456;
assign T_5473 = T_5411 & T_5456;
assign T_5476 = T_5359[4];
assign T_5477 = T_5395 & T_5476;
assign T_5483 = T_5401 & T_5476;
assign T_5487 = T_5405 & T_5476;
assign T_5493 = T_5411 & T_5476;
assign T_5496 = T_5359[5];
assign T_5497 = T_5395 & T_5496;
assign T_5503 = T_5401 & T_5496;
assign T_5507 = T_5405 & T_5496;
assign T_5513 = T_5411 & T_5496;
assign T_5516 = T_5359[6];
assign T_5517 = T_5395 & T_5516;
assign T_5523 = T_5401 & T_5516;
assign T_5527 = T_5405 & T_5516;
assign T_5533 = T_5411 & T_5516;
assign T_5536 = T_5359[7];
assign T_5537 = T_5395 & T_5536;
assign T_5543 = T_5401 & T_5536;
assign T_5547 = T_5405 & T_5536;
assign T_5553 = T_5411 & T_5536;
assign T_5556 = T_5359[8];
assign T_5557 = T_5395 & T_5556;
assign T_5563 = T_5401 & T_5556;
assign T_5567 = T_5405 & T_5556;
assign T_5573 = T_5411 & T_5556;
assign T_5576 = T_5359[9];
assign T_5577 = T_5395 & T_5576;
assign T_5583 = T_5401 & T_5576;
assign T_5587 = T_5405 & T_5576;
assign T_5593 = T_5411 & T_5576;
assign T_5596 = T_5359[10];
assign T_5597 = T_5395 & T_5596;
assign T_5603 = T_5401 & T_5596;
assign T_5607 = T_5405 & T_5596;
assign T_5613 = T_5411 & T_5596;
assign T_5616 = T_5359[11];
assign T_5617 = T_5395 & T_5616;
assign T_5623 = T_5401 & T_5616;
assign T_5627 = T_5405 & T_5616;
assign T_5633 = T_5411 & T_5616;
assign T_5636 = T_5359[12];
assign T_5637 = T_5395 & T_5636;
assign T_5643 = T_5401 & T_5636;
assign T_5647 = T_5405 & T_5636;
assign T_5653 = T_5411 & T_5636;
assign T_5656 = T_5359[13];
assign T_5657 = T_5395 & T_5656;
assign T_5663 = T_5401 & T_5656;
assign T_5667 = T_5405 & T_5656;
assign T_5673 = T_5411 & T_5656;
assign T_5676 = T_5359[14];
assign T_5677 = T_5395 & T_5676;
assign T_5683 = T_5401 & T_5676;
assign T_5687 = T_5405 & T_5676;
assign T_5693 = T_5411 & T_5676;
assign T_5696 = T_5359[15];
assign T_5697 = T_5395 & T_5696;
assign T_5703 = T_5401 & T_5696;
assign T_5707 = T_5405 & T_5696;
assign T_5713 = T_5411 & T_5696;
assign T_5716 = T_5359[16];
assign T_5717 = T_5395 & T_5716;
assign T_5723 = T_5401 & T_5716;
assign T_5727 = T_5405 & T_5716;
assign T_5733 = T_5411 & T_5716;
assign T_6137_0 = T_3457;
assign T_6137_1 = T_3493;
assign T_6137_2 = T_3529;
assign T_6137_3 = T_3556;
assign T_6137_4 = T_3592;
assign T_6137_5 = T_3466;
assign T_6137_6 = T_3502;
assign T_6137_7 = T_3547;
assign T_6137_8 = T_3583;
assign T_6137_9 = T_3511;
assign T_6137_10 = T_3475;
assign T_6137_11 = T_3574;
assign T_6137_12 = T_3538;
assign T_6137_13 = T_3520;
assign T_6137_14 = T_3484;
assign T_6137_15 = T_3601;
assign T_6137_16 = T_3565;
assign T_6137_17 = 1'h1;
assign T_6137_18 = 1'h1;
assign T_6137_19 = 1'h1;
assign T_6137_20 = 1'h1;
assign T_6137_21 = 1'h1;
assign T_6137_22 = 1'h1;
assign T_6137_23 = 1'h1;
assign T_6137_24 = 1'h1;
assign T_6137_25 = 1'h1;
assign T_6137_26 = 1'h1;
assign T_6137_27 = 1'h1;
assign T_6137_28 = 1'h1;
assign T_6137_29 = 1'h1;
assign T_6137_30 = 1'h1;
assign T_6137_31 = 1'h1;
assign T_6208_0 = valueReg;
assign T_6208_1 = T_4047;
assign T_6208_2 = T_4219;
assign T_6208_3 = portReg;
assign T_6208_4 = T_4511;
assign T_6208_5 = dsReg;
assign T_6208_6 = riseIeReg;
assign T_6208_7 = riseIpReg;
assign T_6208_8 = fallIeReg;
assign T_6208_9 = fallIpReg;
assign T_6208_10 = highIeReg;
assign T_6208_11 = highIpReg;
assign T_6208_12 = lowIeReg;
assign T_6208_13 = lowIpReg;
assign T_6208_14 = T_4007;
assign T_6208_15 = iofSelReg;
assign T_6208_16 = xorReg;
assign T_6208_17 = 32'h0;
assign T_6208_18 = 32'h0;
assign T_6208_19 = 32'h0;
assign T_6208_20 = 32'h0;
assign T_6208_21 = 32'h0;
assign T_6208_22 = 32'h0;
assign T_6208_23 = 32'h0;
assign T_6208_24 = 32'h0;
assign T_6208_25 = 32'h0;
assign T_6208_26 = 32'h0;
assign T_6208_27 = 32'h0;
assign T_6208_28 = 32'h0;
assign T_6208_29 = 32'h0;
assign T_6208_30 = 32'h0;
assign T_6208_31 = 32'h0;
assign GEN_4 = GEN_169;
assign GEN_139 = 5'h1 == T_5301 ? T_6137_1 : T_6137_0;
assign GEN_140 = 5'h2 == T_5301 ? T_6137_2 : GEN_139;
assign GEN_141 = 5'h3 == T_5301 ? T_6137_3 : GEN_140;
assign GEN_142 = 5'h4 == T_5301 ? T_6137_4 : GEN_141;
assign GEN_143 = 5'h5 == T_5301 ? T_6137_5 : GEN_142;
assign GEN_144 = 5'h6 == T_5301 ? T_6137_6 : GEN_143;
assign GEN_145 = 5'h7 == T_5301 ? T_6137_7 : GEN_144;
assign GEN_146 = 5'h8 == T_5301 ? T_6137_8 : GEN_145;
assign GEN_147 = 5'h9 == T_5301 ? T_6137_9 : GEN_146;
assign GEN_148 = 5'ha == T_5301 ? T_6137_10 : GEN_147;
assign GEN_149 = 5'hb == T_5301 ? T_6137_11 : GEN_148;
assign GEN_150 = 5'hc == T_5301 ? T_6137_12 : GEN_149;
assign GEN_151 = 5'hd == T_5301 ? T_6137_13 : GEN_150;
assign GEN_152 = 5'he == T_5301 ? T_6137_14 : GEN_151;
assign GEN_153 = 5'hf == T_5301 ? T_6137_15 : GEN_152;
assign GEN_154 = 5'h10 == T_5301 ? T_6137_16 : GEN_153;
assign GEN_155 = 5'h11 == T_5301 ? T_6137_17 : GEN_154;
assign GEN_156 = 5'h12 == T_5301 ? T_6137_18 : GEN_155;
assign GEN_157 = 5'h13 == T_5301 ? T_6137_19 : GEN_156;
assign GEN_158 = 5'h14 == T_5301 ? T_6137_20 : GEN_157;
assign GEN_159 = 5'h15 == T_5301 ? T_6137_21 : GEN_158;
assign GEN_160 = 5'h16 == T_5301 ? T_6137_22 : GEN_159;
assign GEN_161 = 5'h17 == T_5301 ? T_6137_23 : GEN_160;
assign GEN_162 = 5'h18 == T_5301 ? T_6137_24 : GEN_161;
assign GEN_163 = 5'h19 == T_5301 ? T_6137_25 : GEN_162;
assign GEN_164 = 5'h1a == T_5301 ? T_6137_26 : GEN_163;
assign GEN_165 = 5'h1b == T_5301 ? T_6137_27 : GEN_164;
assign GEN_166 = 5'h1c == T_5301 ? T_6137_28 : GEN_165;
assign GEN_167 = 5'h1d == T_5301 ? T_6137_29 : GEN_166;
assign GEN_168 = 5'h1e == T_5301 ? T_6137_30 : GEN_167;
assign GEN_169 = 5'h1f == T_5301 ? T_6137_31 : GEN_168;
assign GEN_5 = GEN_200;
assign GEN_170 = 5'h1 == T_5301 ? T_6208_1 : T_6208_0;
assign GEN_171 = 5'h2 == T_5301 ? T_6208_2 : GEN_170;
assign GEN_172 = 5'h3 == T_5301 ? T_6208_3 : GEN_171;
assign GEN_173 = 5'h4 == T_5301 ? T_6208_4 : GEN_172;
assign GEN_174 = 5'h5 == T_5301 ? T_6208_5 : GEN_173;
assign GEN_175 = 5'h6 == T_5301 ? T_6208_6 : GEN_174;
assign GEN_176 = 5'h7 == T_5301 ? T_6208_7 : GEN_175;
assign GEN_177 = 5'h8 == T_5301 ? T_6208_8 : GEN_176;
assign GEN_178 = 5'h9 == T_5301 ? T_6208_9 : GEN_177;
assign GEN_179 = 5'ha == T_5301 ? T_6208_10 : GEN_178;
assign GEN_180 = 5'hb == T_5301 ? T_6208_11 : GEN_179;
assign GEN_181 = 5'hc == T_5301 ? T_6208_12 : GEN_180;
assign GEN_182 = 5'hd == T_5301 ? T_6208_13 : GEN_181;
assign GEN_183 = 5'he == T_5301 ? T_6208_14 : GEN_182;
assign GEN_184 = 5'hf == T_5301 ? T_6208_15 : GEN_183;
assign GEN_185 = 5'h10 == T_5301 ? T_6208_16 : GEN_184;
assign GEN_186 = 5'h11 == T_5301 ? T_6208_17 : GEN_185;
assign GEN_187 = 5'h12 == T_5301 ? T_6208_18 : GEN_186;
assign GEN_188 = 5'h13 == T_5301 ? T_6208_19 : GEN_187;
assign GEN_189 = 5'h14 == T_5301 ? T_6208_20 : GEN_188;
assign GEN_190 = 5'h15 == T_5301 ? T_6208_21 : GEN_189;
assign GEN_191 = 5'h16 == T_5301 ? T_6208_22 : GEN_190;
assign GEN_192 = 5'h17 == T_5301 ? T_6208_23 : GEN_191;
assign GEN_193 = 5'h18 == T_5301 ? T_6208_24 : GEN_192;
assign GEN_194 = 5'h19 == T_5301 ? T_6208_25 : GEN_193;
assign GEN_195 = 5'h1a == T_5301 ? T_6208_26 : GEN_194;
assign GEN_196 = 5'h1b == T_5301 ? T_6208_27 : GEN_195;
assign GEN_197 = 5'h1c == T_5301 ? T_6208_28 : GEN_196;
assign GEN_198 = 5'h1d == T_5301 ? T_6208_29 : GEN_197;
assign GEN_199 = 5'h1e == T_5301 ? T_6208_30 : GEN_198;
assign GEN_200 = 5'h1f == T_5301 ? T_6208_31 : GEN_199;
assign T_6245 = GEN_4 ? GEN_5 : 32'h0;
assign T_6246 = T_3334_bits_extra[9:8];
assign T_6248 = T_3334_bits_extra[7:3];
assign T_6249 = T_3334_bits_extra[2:0];
assign T_6260_opcode = 3'h0;
assign T_6260_param = 2'h0;
assign T_6260_size = T_6249;
assign T_6260_source = T_6248;
assign T_6260_sink = 1'h0;
assign T_6260_addr_lo = T_6246;
assign T_6260_data = 32'h0;
assign T_6260_error = 1'h0;
assign swPinCtrl_0_oval = T_7570;
assign swPinCtrl_0_oe = T_7571;
assign swPinCtrl_0_ie = T_7573;
assign swPinCtrl_0_pue = T_7569;
assign swPinCtrl_0_ds = T_7572;
assign swPinCtrl_1_oval = T_7606;
assign swPinCtrl_1_oe = T_7607;
assign swPinCtrl_1_ie = T_7609;
assign swPinCtrl_1_pue = T_7605;
assign swPinCtrl_1_ds = T_7608;
assign swPinCtrl_2_oval = T_7642;
assign swPinCtrl_2_oe = T_7643;
assign swPinCtrl_2_ie = T_7645;
assign swPinCtrl_2_pue = T_7641;
assign swPinCtrl_2_ds = T_7644;
assign swPinCtrl_3_oval = T_7678;
assign swPinCtrl_3_oe = T_7679;
assign swPinCtrl_3_ie = T_7681;
assign swPinCtrl_3_pue = T_7677;
assign swPinCtrl_3_ds = T_7680;
assign swPinCtrl_4_oval = T_7714;
assign swPinCtrl_4_oe = T_7715;
assign swPinCtrl_4_ie = T_7717;
assign swPinCtrl_4_pue = T_7713;
assign swPinCtrl_4_ds = T_7716;
assign swPinCtrl_5_oval = T_7750;
assign swPinCtrl_5_oe = T_7751;
assign swPinCtrl_5_ie = T_7753;
assign swPinCtrl_5_pue = T_7749;
assign swPinCtrl_5_ds = T_7752;
assign swPinCtrl_6_oval = T_7786;
assign swPinCtrl_6_oe = T_7787;
assign swPinCtrl_6_ie = T_7789;
assign swPinCtrl_6_pue = T_7785;
assign swPinCtrl_6_ds = T_7788;
assign swPinCtrl_7_oval = T_7822;
assign swPinCtrl_7_oe = T_7823;
assign swPinCtrl_7_ie = T_7825;
assign swPinCtrl_7_pue = T_7821;
assign swPinCtrl_7_ds = T_7824;
assign swPinCtrl_8_oval = T_7858;
assign swPinCtrl_8_oe = T_7859;
assign swPinCtrl_8_ie = T_7861;
assign swPinCtrl_8_pue = T_7857;
assign swPinCtrl_8_ds = T_7860;
assign swPinCtrl_9_oval = T_7894;
assign swPinCtrl_9_oe = T_7895;
assign swPinCtrl_9_ie = T_7897;
assign swPinCtrl_9_pue = T_7893;
assign swPinCtrl_9_ds = T_7896;
assign swPinCtrl_10_oval = T_7930;
assign swPinCtrl_10_oe = T_7931;
assign swPinCtrl_10_ie = T_7933;
assign swPinCtrl_10_pue = T_7929;
assign swPinCtrl_10_ds = T_7932;
assign swPinCtrl_11_oval = T_7966;
assign swPinCtrl_11_oe = T_7967;
assign swPinCtrl_11_ie = T_7969;
assign swPinCtrl_11_pue = T_7965;
assign swPinCtrl_11_ds = T_7968;
assign swPinCtrl_12_oval = T_8002;
assign swPinCtrl_12_oe = T_8003;
assign swPinCtrl_12_ie = T_8005;
assign swPinCtrl_12_pue = T_8001;
assign swPinCtrl_12_ds = T_8004;
assign swPinCtrl_13_oval = T_8038;
assign swPinCtrl_13_oe = T_8039;
assign swPinCtrl_13_ie = T_8041;
assign swPinCtrl_13_pue = T_8037;
assign swPinCtrl_13_ds = T_8040;
assign swPinCtrl_14_oval = T_8074;
assign swPinCtrl_14_oe = T_8075;
assign swPinCtrl_14_ie = T_8077;
assign swPinCtrl_14_pue = T_8073;
assign swPinCtrl_14_ds = T_8076;
assign swPinCtrl_15_oval = T_8110;
assign swPinCtrl_15_oe = T_8111;
assign swPinCtrl_15_ie = T_8113;
assign swPinCtrl_15_pue = T_8109;
assign swPinCtrl_15_ds = T_8112;
assign swPinCtrl_16_oval = T_8146;
assign swPinCtrl_16_oe = T_8147;
assign swPinCtrl_16_ie = T_8149;
assign swPinCtrl_16_pue = T_8145;
assign swPinCtrl_16_ds = T_8148;
assign swPinCtrl_17_oval = T_8182;
assign swPinCtrl_17_oe = T_8183;
assign swPinCtrl_17_ie = T_8185;
assign swPinCtrl_17_pue = T_8181;
assign swPinCtrl_17_ds = T_8184;
assign swPinCtrl_18_oval = T_8218;
assign swPinCtrl_18_oe = T_8219;
assign swPinCtrl_18_ie = T_8221;
assign swPinCtrl_18_pue = T_8217;
assign swPinCtrl_18_ds = T_8220;
assign swPinCtrl_19_oval = T_8254;
assign swPinCtrl_19_oe = T_8255;
assign swPinCtrl_19_ie = T_8257;
assign swPinCtrl_19_pue = T_8253;
assign swPinCtrl_19_ds = T_8256;
assign swPinCtrl_20_oval = T_8290;
assign swPinCtrl_20_oe = T_8291;
assign swPinCtrl_20_ie = T_8293;
assign swPinCtrl_20_pue = T_8289;
assign swPinCtrl_20_ds = T_8292;
assign swPinCtrl_21_oval = T_8326;
assign swPinCtrl_21_oe = T_8327;
assign swPinCtrl_21_ie = T_8329;
assign swPinCtrl_21_pue = T_8325;
assign swPinCtrl_21_ds = T_8328;
assign swPinCtrl_22_oval = T_8362;
assign swPinCtrl_22_oe = T_8363;
assign swPinCtrl_22_ie = T_8365;
assign swPinCtrl_22_pue = T_8361;
assign swPinCtrl_22_ds = T_8364;
assign swPinCtrl_23_oval = T_8398;
assign swPinCtrl_23_oe = T_8399;
assign swPinCtrl_23_ie = T_8401;
assign swPinCtrl_23_pue = T_8397;
assign swPinCtrl_23_ds = T_8400;
assign swPinCtrl_24_oval = T_8434;
assign swPinCtrl_24_oe = T_8435;
assign swPinCtrl_24_ie = T_8437;
assign swPinCtrl_24_pue = T_8433;
assign swPinCtrl_24_ds = T_8436;
assign swPinCtrl_25_oval = T_8470;
assign swPinCtrl_25_oe = T_8471;
assign swPinCtrl_25_ie = T_8473;
assign swPinCtrl_25_pue = T_8469;
assign swPinCtrl_25_ds = T_8472;
assign swPinCtrl_26_oval = T_8506;
assign swPinCtrl_26_oe = T_8507;
assign swPinCtrl_26_ie = T_8509;
assign swPinCtrl_26_pue = T_8505;
assign swPinCtrl_26_ds = T_8508;
assign swPinCtrl_27_oval = T_8542;
assign swPinCtrl_27_oe = T_8543;
assign swPinCtrl_27_ie = T_8545;
assign swPinCtrl_27_pue = T_8541;
assign swPinCtrl_27_ds = T_8544;
assign swPinCtrl_28_oval = T_8578;
assign swPinCtrl_28_oe = T_8579;
assign swPinCtrl_28_ie = T_8581;
assign swPinCtrl_28_pue = T_8577;
assign swPinCtrl_28_ds = T_8580;
assign swPinCtrl_29_oval = T_8614;
assign swPinCtrl_29_oe = T_8615;
assign swPinCtrl_29_ie = T_8617;
assign swPinCtrl_29_pue = T_8613;
assign swPinCtrl_29_ds = T_8616;
assign swPinCtrl_30_oval = T_8650;
assign swPinCtrl_30_oe = T_8651;
assign swPinCtrl_30_ie = T_8653;
assign swPinCtrl_30_pue = T_8649;
assign swPinCtrl_30_ds = T_8652;
assign swPinCtrl_31_oval = T_8686;
assign swPinCtrl_31_oe = T_8687;
assign swPinCtrl_31_ie = T_8689;
assign swPinCtrl_31_pue = T_8685;
assign swPinCtrl_31_ds = T_8688;
assign iof0Ctrl_0_oval = GEN_201;
assign iof0Ctrl_0_oe = GEN_202;
assign iof0Ctrl_0_ie = GEN_203;
assign iof0Ctrl_1_oval = GEN_207;
assign iof0Ctrl_1_oe = GEN_208;
assign iof0Ctrl_1_ie = GEN_209;
assign iof0Ctrl_2_oval = GEN_213;
assign iof0Ctrl_2_oe = GEN_214;
assign iof0Ctrl_2_ie = GEN_215;
assign iof0Ctrl_3_oval = GEN_219;
assign iof0Ctrl_3_oe = GEN_220;
assign iof0Ctrl_3_ie = GEN_221;
assign iof0Ctrl_4_oval = GEN_225;
assign iof0Ctrl_4_oe = GEN_226;
assign iof0Ctrl_4_ie = GEN_227;
assign iof0Ctrl_5_oval = GEN_231;
assign iof0Ctrl_5_oe = GEN_232;
assign iof0Ctrl_5_ie = GEN_233;
assign iof0Ctrl_6_oval = GEN_237;
assign iof0Ctrl_6_oe = GEN_238;
assign iof0Ctrl_6_ie = GEN_239;
assign iof0Ctrl_7_oval = GEN_243;
assign iof0Ctrl_7_oe = GEN_244;
assign iof0Ctrl_7_ie = GEN_245;
assign iof0Ctrl_8_oval = GEN_249;
assign iof0Ctrl_8_oe = GEN_250;
assign iof0Ctrl_8_ie = GEN_251;
assign iof0Ctrl_9_oval = GEN_255;
assign iof0Ctrl_9_oe = GEN_256;
assign iof0Ctrl_9_ie = GEN_257;
assign iof0Ctrl_10_oval = GEN_261;
assign iof0Ctrl_10_oe = GEN_262;
assign iof0Ctrl_10_ie = GEN_263;
assign iof0Ctrl_11_oval = GEN_267;
assign iof0Ctrl_11_oe = GEN_268;
assign iof0Ctrl_11_ie = GEN_269;
assign iof0Ctrl_12_oval = GEN_273;
assign iof0Ctrl_12_oe = GEN_274;
assign iof0Ctrl_12_ie = GEN_275;
assign iof0Ctrl_13_oval = GEN_279;
assign iof0Ctrl_13_oe = GEN_280;
assign iof0Ctrl_13_ie = GEN_281;
assign iof0Ctrl_14_oval = GEN_285;
assign iof0Ctrl_14_oe = GEN_286;
assign iof0Ctrl_14_ie = GEN_287;
assign iof0Ctrl_15_oval = GEN_291;
assign iof0Ctrl_15_oe = GEN_292;
assign iof0Ctrl_15_ie = GEN_293;
assign iof0Ctrl_16_oval = GEN_297;
assign iof0Ctrl_16_oe = GEN_298;
assign iof0Ctrl_16_ie = GEN_299;
assign iof0Ctrl_17_oval = GEN_303;
assign iof0Ctrl_17_oe = GEN_304;
assign iof0Ctrl_17_ie = GEN_305;
assign iof0Ctrl_18_oval = GEN_309;
assign iof0Ctrl_18_oe = GEN_310;
assign iof0Ctrl_18_ie = GEN_311;
assign iof0Ctrl_19_oval = GEN_315;
assign iof0Ctrl_19_oe = GEN_316;
assign iof0Ctrl_19_ie = GEN_317;
assign iof0Ctrl_20_oval = GEN_321;
assign iof0Ctrl_20_oe = GEN_322;
assign iof0Ctrl_20_ie = GEN_323;
assign iof0Ctrl_21_oval = GEN_327;
assign iof0Ctrl_21_oe = GEN_328;
assign iof0Ctrl_21_ie = GEN_329;
assign iof0Ctrl_22_oval = GEN_333;
assign iof0Ctrl_22_oe = GEN_334;
assign iof0Ctrl_22_ie = GEN_335;
assign iof0Ctrl_23_oval = GEN_339;
assign iof0Ctrl_23_oe = GEN_340;
assign iof0Ctrl_23_ie = GEN_341;
assign iof0Ctrl_24_oval = GEN_345;
assign iof0Ctrl_24_oe = GEN_346;
assign iof0Ctrl_24_ie = GEN_347;
assign iof0Ctrl_25_oval = GEN_351;
assign iof0Ctrl_25_oe = GEN_352;
assign iof0Ctrl_25_ie = GEN_353;
assign iof0Ctrl_26_oval = GEN_357;
assign iof0Ctrl_26_oe = GEN_358;
assign iof0Ctrl_26_ie = GEN_359;
assign iof0Ctrl_27_oval = GEN_363;
assign iof0Ctrl_27_oe = GEN_364;
assign iof0Ctrl_27_ie = GEN_365;
assign iof0Ctrl_28_oval = GEN_369;
assign iof0Ctrl_28_oe = GEN_370;
assign iof0Ctrl_28_ie = GEN_371;
assign iof0Ctrl_29_oval = GEN_375;
assign iof0Ctrl_29_oe = GEN_376;
assign iof0Ctrl_29_ie = GEN_377;
assign iof0Ctrl_30_oval = GEN_381;
assign iof0Ctrl_30_oe = GEN_382;
assign iof0Ctrl_30_ie = GEN_383;
assign iof0Ctrl_31_oval = GEN_387;
assign iof0Ctrl_31_oe = GEN_388;
assign iof0Ctrl_31_ie = GEN_389;
assign iof1Ctrl_0_oval = GEN_204;
assign iof1Ctrl_0_oe = GEN_205;
assign iof1Ctrl_0_ie = GEN_206;
assign iof1Ctrl_1_oval = GEN_210;
assign iof1Ctrl_1_oe = GEN_211;
assign iof1Ctrl_1_ie = GEN_212;
assign iof1Ctrl_2_oval = GEN_216;
assign iof1Ctrl_2_oe = GEN_217;
assign iof1Ctrl_2_ie = GEN_218;
assign iof1Ctrl_3_oval = GEN_222;
assign iof1Ctrl_3_oe = GEN_223;
assign iof1Ctrl_3_ie = GEN_224;
assign iof1Ctrl_4_oval = GEN_228;
assign iof1Ctrl_4_oe = GEN_229;
assign iof1Ctrl_4_ie = GEN_230;
assign iof1Ctrl_5_oval = GEN_234;
assign iof1Ctrl_5_oe = GEN_235;
assign iof1Ctrl_5_ie = GEN_236;
assign iof1Ctrl_6_oval = GEN_240;
assign iof1Ctrl_6_oe = GEN_241;
assign iof1Ctrl_6_ie = GEN_242;
assign iof1Ctrl_7_oval = GEN_246;
assign iof1Ctrl_7_oe = GEN_247;
assign iof1Ctrl_7_ie = GEN_248;
assign iof1Ctrl_8_oval = GEN_252;
assign iof1Ctrl_8_oe = GEN_253;
assign iof1Ctrl_8_ie = GEN_254;
assign iof1Ctrl_9_oval = GEN_258;
assign iof1Ctrl_9_oe = GEN_259;
assign iof1Ctrl_9_ie = GEN_260;
assign iof1Ctrl_10_oval = GEN_264;
assign iof1Ctrl_10_oe = GEN_265;
assign iof1Ctrl_10_ie = GEN_266;
assign iof1Ctrl_11_oval = GEN_270;
assign iof1Ctrl_11_oe = GEN_271;
assign iof1Ctrl_11_ie = GEN_272;
assign iof1Ctrl_12_oval = GEN_276;
assign iof1Ctrl_12_oe = GEN_277;
assign iof1Ctrl_12_ie = GEN_278;
assign iof1Ctrl_13_oval = GEN_282;
assign iof1Ctrl_13_oe = GEN_283;
assign iof1Ctrl_13_ie = GEN_284;
assign iof1Ctrl_14_oval = GEN_288;
assign iof1Ctrl_14_oe = GEN_289;
assign iof1Ctrl_14_ie = GEN_290;
assign iof1Ctrl_15_oval = GEN_294;
assign iof1Ctrl_15_oe = GEN_295;
assign iof1Ctrl_15_ie = GEN_296;
assign iof1Ctrl_16_oval = GEN_300;
assign iof1Ctrl_16_oe = GEN_301;
assign iof1Ctrl_16_ie = GEN_302;
assign iof1Ctrl_17_oval = GEN_306;
assign iof1Ctrl_17_oe = GEN_307;
assign iof1Ctrl_17_ie = GEN_308;
assign iof1Ctrl_18_oval = GEN_312;
assign iof1Ctrl_18_oe = GEN_313;
assign iof1Ctrl_18_ie = GEN_314;
assign iof1Ctrl_19_oval = GEN_318;
assign iof1Ctrl_19_oe = GEN_319;
assign iof1Ctrl_19_ie = GEN_320;
assign iof1Ctrl_20_oval = GEN_324;
assign iof1Ctrl_20_oe = GEN_325;
assign iof1Ctrl_20_ie = GEN_326;
assign iof1Ctrl_21_oval = GEN_330;
assign iof1Ctrl_21_oe = GEN_331;
assign iof1Ctrl_21_ie = GEN_332;
assign iof1Ctrl_22_oval = GEN_336;
assign iof1Ctrl_22_oe = GEN_337;
assign iof1Ctrl_22_ie = GEN_338;
assign iof1Ctrl_23_oval = GEN_342;
assign iof1Ctrl_23_oe = GEN_343;
assign iof1Ctrl_23_ie = GEN_344;
assign iof1Ctrl_24_oval = GEN_348;
assign iof1Ctrl_24_oe = GEN_349;
assign iof1Ctrl_24_ie = GEN_350;
assign iof1Ctrl_25_oval = GEN_354;
assign iof1Ctrl_25_oe = GEN_355;
assign iof1Ctrl_25_ie = GEN_356;
assign iof1Ctrl_26_oval = GEN_360;
assign iof1Ctrl_26_oe = GEN_361;
assign iof1Ctrl_26_ie = GEN_362;
assign iof1Ctrl_27_oval = GEN_366;
assign iof1Ctrl_27_oe = GEN_367;
assign iof1Ctrl_27_ie = GEN_368;
assign iof1Ctrl_28_oval = GEN_372;
assign iof1Ctrl_28_oe = GEN_373;
assign iof1Ctrl_28_ie = GEN_374;
assign iof1Ctrl_29_oval = GEN_378;
assign iof1Ctrl_29_oe = GEN_379;
assign iof1Ctrl_29_ie = GEN_380;
assign iof1Ctrl_30_oval = GEN_384;
assign iof1Ctrl_30_oe = GEN_385;
assign iof1Ctrl_30_ie = GEN_386;
assign iof1Ctrl_31_oval = GEN_390;
assign iof1Ctrl_31_oe = GEN_391;
assign iof1Ctrl_31_ie = GEN_392;
assign iofCtrl_0_oval = T_7575_oval;
assign iofCtrl_0_oe = T_7575_oe;
assign iofCtrl_0_ie = T_7575_ie;
assign iofCtrl_1_oval = T_7611_oval;
assign iofCtrl_1_oe = T_7611_oe;
assign iofCtrl_1_ie = T_7611_ie;
assign iofCtrl_2_oval = T_7647_oval;
assign iofCtrl_2_oe = T_7647_oe;
assign iofCtrl_2_ie = T_7647_ie;
assign iofCtrl_3_oval = T_7683_oval;
assign iofCtrl_3_oe = T_7683_oe;
assign iofCtrl_3_ie = T_7683_ie;
assign iofCtrl_4_oval = T_7719_oval;
assign iofCtrl_4_oe = T_7719_oe;
assign iofCtrl_4_ie = T_7719_ie;
assign iofCtrl_5_oval = T_7755_oval;
assign iofCtrl_5_oe = T_7755_oe;
assign iofCtrl_5_ie = T_7755_ie;
assign iofCtrl_6_oval = T_7791_oval;
assign iofCtrl_6_oe = T_7791_oe;
assign iofCtrl_6_ie = T_7791_ie;
assign iofCtrl_7_oval = T_7827_oval;
assign iofCtrl_7_oe = T_7827_oe;
assign iofCtrl_7_ie = T_7827_ie;
assign iofCtrl_8_oval = T_7863_oval;
assign iofCtrl_8_oe = T_7863_oe;
assign iofCtrl_8_ie = T_7863_ie;
assign iofCtrl_9_oval = T_7899_oval;
assign iofCtrl_9_oe = T_7899_oe;
assign iofCtrl_9_ie = T_7899_ie;
assign iofCtrl_10_oval = T_7935_oval;
assign iofCtrl_10_oe = T_7935_oe;
assign iofCtrl_10_ie = T_7935_ie;
assign iofCtrl_11_oval = T_7971_oval;
assign iofCtrl_11_oe = T_7971_oe;
assign iofCtrl_11_ie = T_7971_ie;
assign iofCtrl_12_oval = T_8007_oval;
assign iofCtrl_12_oe = T_8007_oe;
assign iofCtrl_12_ie = T_8007_ie;
assign iofCtrl_13_oval = T_8043_oval;
assign iofCtrl_13_oe = T_8043_oe;
assign iofCtrl_13_ie = T_8043_ie;
assign iofCtrl_14_oval = T_8079_oval;
assign iofCtrl_14_oe = T_8079_oe;
assign iofCtrl_14_ie = T_8079_ie;
assign iofCtrl_15_oval = T_8115_oval;
assign iofCtrl_15_oe = T_8115_oe;
assign iofCtrl_15_ie = T_8115_ie;
assign iofCtrl_16_oval = T_8151_oval;
assign iofCtrl_16_oe = T_8151_oe;
assign iofCtrl_16_ie = T_8151_ie;
assign iofCtrl_17_oval = T_8187_oval;
assign iofCtrl_17_oe = T_8187_oe;
assign iofCtrl_17_ie = T_8187_ie;
assign iofCtrl_18_oval = T_8223_oval;
assign iofCtrl_18_oe = T_8223_oe;
assign iofCtrl_18_ie = T_8223_ie;
assign iofCtrl_19_oval = T_8259_oval;
assign iofCtrl_19_oe = T_8259_oe;
assign iofCtrl_19_ie = T_8259_ie;
assign iofCtrl_20_oval = T_8295_oval;
assign iofCtrl_20_oe = T_8295_oe;
assign iofCtrl_20_ie = T_8295_ie;
assign iofCtrl_21_oval = T_8331_oval;
assign iofCtrl_21_oe = T_8331_oe;
assign iofCtrl_21_ie = T_8331_ie;
assign iofCtrl_22_oval = T_8367_oval;
assign iofCtrl_22_oe = T_8367_oe;
assign iofCtrl_22_ie = T_8367_ie;
assign iofCtrl_23_oval = T_8403_oval;
assign iofCtrl_23_oe = T_8403_oe;
assign iofCtrl_23_ie = T_8403_ie;
assign iofCtrl_24_oval = T_8439_oval;
assign iofCtrl_24_oe = T_8439_oe;
assign iofCtrl_24_ie = T_8439_ie;
assign iofCtrl_25_oval = T_8475_oval;
assign iofCtrl_25_oe = T_8475_oe;
assign iofCtrl_25_ie = T_8475_ie;
assign iofCtrl_26_oval = T_8511_oval;
assign iofCtrl_26_oe = T_8511_oe;
assign iofCtrl_26_ie = T_8511_ie;
assign iofCtrl_27_oval = T_8547_oval;
assign iofCtrl_27_oe = T_8547_oe;
assign iofCtrl_27_ie = T_8547_ie;
assign iofCtrl_28_oval = T_8583_oval;
assign iofCtrl_28_oe = T_8583_oe;
assign iofCtrl_28_ie = T_8583_ie;
assign iofCtrl_29_oval = T_8619_oval;
assign iofCtrl_29_oe = T_8619_oe;
assign iofCtrl_29_ie = T_8619_ie;
assign iofCtrl_30_oval = T_8655_oval;
assign iofCtrl_30_oe = T_8655_oe;
assign iofCtrl_30_ie = T_8655_ie;
assign iofCtrl_31_oval = T_8691_oval;
assign iofCtrl_31_oe = T_8691_oe;
assign iofCtrl_31_ie = T_8691_ie;
assign iofPlusSwPinCtrl_0_oval = iofCtrl_0_oval;
assign iofPlusSwPinCtrl_0_oe = iofCtrl_0_oe;
assign iofPlusSwPinCtrl_0_ie = iofCtrl_0_ie;
assign iofPlusSwPinCtrl_0_pue = swPinCtrl_0_pue;
assign iofPlusSwPinCtrl_0_ds = swPinCtrl_0_ds;
assign iofPlusSwPinCtrl_1_oval = iofCtrl_1_oval;
assign iofPlusSwPinCtrl_1_oe = iofCtrl_1_oe;
assign iofPlusSwPinCtrl_1_ie = iofCtrl_1_ie;
assign iofPlusSwPinCtrl_1_pue = swPinCtrl_1_pue;
assign iofPlusSwPinCtrl_1_ds = swPinCtrl_1_ds;
assign iofPlusSwPinCtrl_2_oval = iofCtrl_2_oval;
assign iofPlusSwPinCtrl_2_oe = iofCtrl_2_oe;
assign iofPlusSwPinCtrl_2_ie = iofCtrl_2_ie;
assign iofPlusSwPinCtrl_2_pue = swPinCtrl_2_pue;
assign iofPlusSwPinCtrl_2_ds = swPinCtrl_2_ds;
assign iofPlusSwPinCtrl_3_oval = iofCtrl_3_oval;
assign iofPlusSwPinCtrl_3_oe = iofCtrl_3_oe;
assign iofPlusSwPinCtrl_3_ie = iofCtrl_3_ie;
assign iofPlusSwPinCtrl_3_pue = swPinCtrl_3_pue;
assign iofPlusSwPinCtrl_3_ds = swPinCtrl_3_ds;
assign iofPlusSwPinCtrl_4_oval = iofCtrl_4_oval;
assign iofPlusSwPinCtrl_4_oe = iofCtrl_4_oe;
assign iofPlusSwPinCtrl_4_ie = iofCtrl_4_ie;
assign iofPlusSwPinCtrl_4_pue = swPinCtrl_4_pue;
assign iofPlusSwPinCtrl_4_ds = swPinCtrl_4_ds;
assign iofPlusSwPinCtrl_5_oval = iofCtrl_5_oval;
assign iofPlusSwPinCtrl_5_oe = iofCtrl_5_oe;
assign iofPlusSwPinCtrl_5_ie = iofCtrl_5_ie;
assign iofPlusSwPinCtrl_5_pue = swPinCtrl_5_pue;
assign iofPlusSwPinCtrl_5_ds = swPinCtrl_5_ds;
assign iofPlusSwPinCtrl_6_oval = iofCtrl_6_oval;
assign iofPlusSwPinCtrl_6_oe = iofCtrl_6_oe;
assign iofPlusSwPinCtrl_6_ie = iofCtrl_6_ie;
assign iofPlusSwPinCtrl_6_pue = swPinCtrl_6_pue;
assign iofPlusSwPinCtrl_6_ds = swPinCtrl_6_ds;
assign iofPlusSwPinCtrl_7_oval = iofCtrl_7_oval;
assign iofPlusSwPinCtrl_7_oe = iofCtrl_7_oe;
assign iofPlusSwPinCtrl_7_ie = iofCtrl_7_ie;
assign iofPlusSwPinCtrl_7_pue = swPinCtrl_7_pue;
assign iofPlusSwPinCtrl_7_ds = swPinCtrl_7_ds;
assign iofPlusSwPinCtrl_8_oval = iofCtrl_8_oval;
assign iofPlusSwPinCtrl_8_oe = iofCtrl_8_oe;
assign iofPlusSwPinCtrl_8_ie = iofCtrl_8_ie;
assign iofPlusSwPinCtrl_8_pue = swPinCtrl_8_pue;
assign iofPlusSwPinCtrl_8_ds = swPinCtrl_8_ds;
assign iofPlusSwPinCtrl_9_oval = iofCtrl_9_oval;
assign iofPlusSwPinCtrl_9_oe = iofCtrl_9_oe;
assign iofPlusSwPinCtrl_9_ie = iofCtrl_9_ie;
assign iofPlusSwPinCtrl_9_pue = swPinCtrl_9_pue;
assign iofPlusSwPinCtrl_9_ds = swPinCtrl_9_ds;
assign iofPlusSwPinCtrl_10_oval = iofCtrl_10_oval;
assign iofPlusSwPinCtrl_10_oe = iofCtrl_10_oe;
assign iofPlusSwPinCtrl_10_ie = iofCtrl_10_ie;
assign iofPlusSwPinCtrl_10_pue = swPinCtrl_10_pue;
assign iofPlusSwPinCtrl_10_ds = swPinCtrl_10_ds;
assign iofPlusSwPinCtrl_11_oval = iofCtrl_11_oval;
assign iofPlusSwPinCtrl_11_oe = iofCtrl_11_oe;
assign iofPlusSwPinCtrl_11_ie = iofCtrl_11_ie;
assign iofPlusSwPinCtrl_11_pue = swPinCtrl_11_pue;
assign iofPlusSwPinCtrl_11_ds = swPinCtrl_11_ds;
assign iofPlusSwPinCtrl_12_oval = iofCtrl_12_oval;
assign iofPlusSwPinCtrl_12_oe = iofCtrl_12_oe;
assign iofPlusSwPinCtrl_12_ie = iofCtrl_12_ie;
assign iofPlusSwPinCtrl_12_pue = swPinCtrl_12_pue;
assign iofPlusSwPinCtrl_12_ds = swPinCtrl_12_ds;
assign iofPlusSwPinCtrl_13_oval = iofCtrl_13_oval;
assign iofPlusSwPinCtrl_13_oe = iofCtrl_13_oe;
assign iofPlusSwPinCtrl_13_ie = iofCtrl_13_ie;
assign iofPlusSwPinCtrl_13_pue = swPinCtrl_13_pue;
assign iofPlusSwPinCtrl_13_ds = swPinCtrl_13_ds;
assign iofPlusSwPinCtrl_14_oval = iofCtrl_14_oval;
assign iofPlusSwPinCtrl_14_oe = iofCtrl_14_oe;
assign iofPlusSwPinCtrl_14_ie = iofCtrl_14_ie;
assign iofPlusSwPinCtrl_14_pue = swPinCtrl_14_pue;
assign iofPlusSwPinCtrl_14_ds = swPinCtrl_14_ds;
assign iofPlusSwPinCtrl_15_oval = iofCtrl_15_oval;
assign iofPlusSwPinCtrl_15_oe = iofCtrl_15_oe;
assign iofPlusSwPinCtrl_15_ie = iofCtrl_15_ie;
assign iofPlusSwPinCtrl_15_pue = swPinCtrl_15_pue;
assign iofPlusSwPinCtrl_15_ds = swPinCtrl_15_ds;
assign iofPlusSwPinCtrl_16_oval = iofCtrl_16_oval;
assign iofPlusSwPinCtrl_16_oe = iofCtrl_16_oe;
assign iofPlusSwPinCtrl_16_ie = iofCtrl_16_ie;
assign iofPlusSwPinCtrl_16_pue = swPinCtrl_16_pue;
assign iofPlusSwPinCtrl_16_ds = swPinCtrl_16_ds;
assign iofPlusSwPinCtrl_17_oval = iofCtrl_17_oval;
assign iofPlusSwPinCtrl_17_oe = iofCtrl_17_oe;
assign iofPlusSwPinCtrl_17_ie = iofCtrl_17_ie;
assign iofPlusSwPinCtrl_17_pue = swPinCtrl_17_pue;
assign iofPlusSwPinCtrl_17_ds = swPinCtrl_17_ds;
assign iofPlusSwPinCtrl_18_oval = iofCtrl_18_oval;
assign iofPlusSwPinCtrl_18_oe = iofCtrl_18_oe;
assign iofPlusSwPinCtrl_18_ie = iofCtrl_18_ie;
assign iofPlusSwPinCtrl_18_pue = swPinCtrl_18_pue;
assign iofPlusSwPinCtrl_18_ds = swPinCtrl_18_ds;
assign iofPlusSwPinCtrl_19_oval = iofCtrl_19_oval;
assign iofPlusSwPinCtrl_19_oe = iofCtrl_19_oe;
assign iofPlusSwPinCtrl_19_ie = iofCtrl_19_ie;
assign iofPlusSwPinCtrl_19_pue = swPinCtrl_19_pue;
assign iofPlusSwPinCtrl_19_ds = swPinCtrl_19_ds;
assign iofPlusSwPinCtrl_20_oval = iofCtrl_20_oval;
assign iofPlusSwPinCtrl_20_oe = iofCtrl_20_oe;
assign iofPlusSwPinCtrl_20_ie = iofCtrl_20_ie;
assign iofPlusSwPinCtrl_20_pue = swPinCtrl_20_pue;
assign iofPlusSwPinCtrl_20_ds = swPinCtrl_20_ds;
assign iofPlusSwPinCtrl_21_oval = iofCtrl_21_oval;
assign iofPlusSwPinCtrl_21_oe = iofCtrl_21_oe;
assign iofPlusSwPinCtrl_21_ie = iofCtrl_21_ie;
assign iofPlusSwPinCtrl_21_pue = swPinCtrl_21_pue;
assign iofPlusSwPinCtrl_21_ds = swPinCtrl_21_ds;
assign iofPlusSwPinCtrl_22_oval = iofCtrl_22_oval;
assign iofPlusSwPinCtrl_22_oe = iofCtrl_22_oe;
assign iofPlusSwPinCtrl_22_ie = iofCtrl_22_ie;
assign iofPlusSwPinCtrl_22_pue = swPinCtrl_22_pue;
assign iofPlusSwPinCtrl_22_ds = swPinCtrl_22_ds;
assign iofPlusSwPinCtrl_23_oval = iofCtrl_23_oval;
assign iofPlusSwPinCtrl_23_oe = iofCtrl_23_oe;
assign iofPlusSwPinCtrl_23_ie = iofCtrl_23_ie;
assign iofPlusSwPinCtrl_23_pue = swPinCtrl_23_pue;
assign iofPlusSwPinCtrl_23_ds = swPinCtrl_23_ds;
assign iofPlusSwPinCtrl_24_oval = iofCtrl_24_oval;
assign iofPlusSwPinCtrl_24_oe = iofCtrl_24_oe;
assign iofPlusSwPinCtrl_24_ie = iofCtrl_24_ie;
assign iofPlusSwPinCtrl_24_pue = swPinCtrl_24_pue;
assign iofPlusSwPinCtrl_24_ds = swPinCtrl_24_ds;
assign iofPlusSwPinCtrl_25_oval = iofCtrl_25_oval;
assign iofPlusSwPinCtrl_25_oe = iofCtrl_25_oe;
assign iofPlusSwPinCtrl_25_ie = iofCtrl_25_ie;
assign iofPlusSwPinCtrl_25_pue = swPinCtrl_25_pue;
assign iofPlusSwPinCtrl_25_ds = swPinCtrl_25_ds;
assign iofPlusSwPinCtrl_26_oval = iofCtrl_26_oval;
assign iofPlusSwPinCtrl_26_oe = iofCtrl_26_oe;
assign iofPlusSwPinCtrl_26_ie = iofCtrl_26_ie;
assign iofPlusSwPinCtrl_26_pue = swPinCtrl_26_pue;
assign iofPlusSwPinCtrl_26_ds = swPinCtrl_26_ds;
assign iofPlusSwPinCtrl_27_oval = iofCtrl_27_oval;
assign iofPlusSwPinCtrl_27_oe = iofCtrl_27_oe;
assign iofPlusSwPinCtrl_27_ie = iofCtrl_27_ie;
assign iofPlusSwPinCtrl_27_pue = swPinCtrl_27_pue;
assign iofPlusSwPinCtrl_27_ds = swPinCtrl_27_ds;
assign iofPlusSwPinCtrl_28_oval = iofCtrl_28_oval;
assign iofPlusSwPinCtrl_28_oe = iofCtrl_28_oe;
assign iofPlusSwPinCtrl_28_ie = iofCtrl_28_ie;
assign iofPlusSwPinCtrl_28_pue = swPinCtrl_28_pue;
assign iofPlusSwPinCtrl_28_ds = swPinCtrl_28_ds;
assign iofPlusSwPinCtrl_29_oval = iofCtrl_29_oval;
assign iofPlusSwPinCtrl_29_oe = iofCtrl_29_oe;
assign iofPlusSwPinCtrl_29_ie = iofCtrl_29_ie;
assign iofPlusSwPinCtrl_29_pue = swPinCtrl_29_pue;
assign iofPlusSwPinCtrl_29_ds = swPinCtrl_29_ds;
assign iofPlusSwPinCtrl_30_oval = iofCtrl_30_oval;
assign iofPlusSwPinCtrl_30_oe = iofCtrl_30_oe;
assign iofPlusSwPinCtrl_30_ie = iofCtrl_30_ie;
assign iofPlusSwPinCtrl_30_pue = swPinCtrl_30_pue;
assign iofPlusSwPinCtrl_30_ds = swPinCtrl_30_ds;
assign iofPlusSwPinCtrl_31_oval = iofCtrl_31_oval;
assign iofPlusSwPinCtrl_31_oe = iofCtrl_31_oe;
assign iofPlusSwPinCtrl_31_ie = iofCtrl_31_ie;
assign iofPlusSwPinCtrl_31_pue = swPinCtrl_31_pue;
assign iofPlusSwPinCtrl_31_ds = swPinCtrl_31_ds;
assign T_7569 = pueReg_io_q[0];
assign T_7570 = portReg[0];
assign T_7571 = oeReg_io_q[0];
assign T_7572 = dsReg[0];
assign T_7573 = ieReg_io_q[0];
assign GEN_201 = io_port_iof_0_0_o_valid ? io_port_iof_0_0_o_oval : swPinCtrl_0_oval;
assign GEN_202 = io_port_iof_0_0_o_valid ? io_port_iof_0_0_o_oe : swPinCtrl_0_oe;
assign GEN_203 = io_port_iof_0_0_o_valid ? io_port_iof_0_0_o_ie : swPinCtrl_0_ie;
assign GEN_204 = io_port_iof_1_0_o_valid ? io_port_iof_1_0_o_oval : swPinCtrl_0_oval;
assign GEN_205 = io_port_iof_1_0_o_valid ? io_port_iof_1_0_o_oe : swPinCtrl_0_oe;
assign GEN_206 = io_port_iof_1_0_o_valid ? io_port_iof_1_0_o_ie : swPinCtrl_0_ie;
assign T_7574 = iofSelReg[0];
assign T_7575_oval = T_7574 ? iof1Ctrl_0_oval : iof0Ctrl_0_oval;
assign T_7575_oe = T_7574 ? iof1Ctrl_0_oe : iof0Ctrl_0_oe;
assign T_7575_ie = T_7574 ? iof1Ctrl_0_ie : iof0Ctrl_0_ie;
assign T_7579 = iofEnReg_io_q[0];
assign T_7580_oval = T_7579 ? iofPlusSwPinCtrl_0_oval : swPinCtrl_0_oval;
assign T_7580_oe = T_7579 ? iofPlusSwPinCtrl_0_oe : swPinCtrl_0_oe;
assign T_7580_ie = T_7579 ? iofPlusSwPinCtrl_0_ie : swPinCtrl_0_ie;
assign T_7580_pue = T_7579 ? iofPlusSwPinCtrl_0_pue : swPinCtrl_0_pue;
assign T_7580_ds = T_7579 ? iofPlusSwPinCtrl_0_ds : swPinCtrl_0_ds;
assign T_7586 = xorReg[0];
assign T_7587 = T_7580_oval ^ T_7586;
assign T_7588 = riseIpReg[0];
assign T_7589 = riseIeReg[0];
assign T_7590 = T_7588 & T_7589;
assign T_7591 = fallIpReg[0];
assign T_7592 = fallIeReg[0];
assign T_7593 = T_7591 & T_7592;
assign T_7594 = T_7590 | T_7593;
assign T_7595 = highIpReg[0];
assign T_7596 = highIeReg[0];
assign T_7597 = T_7595 & T_7596;
assign T_7598 = T_7594 | T_7597;
assign T_7599 = lowIpReg[0];
assign T_7600 = lowIeReg[0];
assign T_7601 = T_7599 & T_7600;
assign T_7602 = T_7598 | T_7601;
assign T_7603 = inSyncReg[0];
assign T_7605 = pueReg_io_q[1];
assign T_7606 = portReg[1];
assign T_7607 = oeReg_io_q[1];
assign T_7608 = dsReg[1];
assign T_7609 = ieReg_io_q[1];
assign GEN_207 = io_port_iof_0_1_o_valid ? io_port_iof_0_1_o_oval : swPinCtrl_1_oval;
assign GEN_208 = io_port_iof_0_1_o_valid ? io_port_iof_0_1_o_oe : swPinCtrl_1_oe;
assign GEN_209 = io_port_iof_0_1_o_valid ? io_port_iof_0_1_o_ie : swPinCtrl_1_ie;
assign GEN_210 = io_port_iof_1_1_o_valid ? io_port_iof_1_1_o_oval : swPinCtrl_1_oval;
assign GEN_211 = io_port_iof_1_1_o_valid ? io_port_iof_1_1_o_oe : swPinCtrl_1_oe;
assign GEN_212 = io_port_iof_1_1_o_valid ? io_port_iof_1_1_o_ie : swPinCtrl_1_ie;
assign T_7610 = iofSelReg[1];
assign T_7611_oval = T_7610 ? iof1Ctrl_1_oval : iof0Ctrl_1_oval;
assign T_7611_oe = T_7610 ? iof1Ctrl_1_oe : iof0Ctrl_1_oe;
assign T_7611_ie = T_7610 ? iof1Ctrl_1_ie : iof0Ctrl_1_ie;
assign T_7615 = iofEnReg_io_q[1];
assign T_7616_oval = T_7615 ? iofPlusSwPinCtrl_1_oval : swPinCtrl_1_oval;
assign T_7616_oe = T_7615 ? iofPlusSwPinCtrl_1_oe : swPinCtrl_1_oe;
assign T_7616_ie = T_7615 ? iofPlusSwPinCtrl_1_ie : swPinCtrl_1_ie;
assign T_7616_pue = T_7615 ? iofPlusSwPinCtrl_1_pue : swPinCtrl_1_pue;
assign T_7616_ds = T_7615 ? iofPlusSwPinCtrl_1_ds : swPinCtrl_1_ds;
assign T_7622 = xorReg[1];
assign T_7623 = T_7616_oval ^ T_7622;
assign T_7624 = riseIpReg[1];
assign T_7625 = riseIeReg[1];
assign T_7626 = T_7624 & T_7625;
assign T_7627 = fallIpReg[1];
assign T_7628 = fallIeReg[1];
assign T_7629 = T_7627 & T_7628;
assign T_7630 = T_7626 | T_7629;
assign T_7631 = highIpReg[1];
assign T_7632 = highIeReg[1];
assign T_7633 = T_7631 & T_7632;
assign T_7634 = T_7630 | T_7633;
assign T_7635 = lowIpReg[1];
assign T_7636 = lowIeReg[1];
assign T_7637 = T_7635 & T_7636;
assign T_7638 = T_7634 | T_7637;
assign T_7639 = inSyncReg[1];
assign T_7641 = pueReg_io_q[2];
assign T_7642 = portReg[2];
assign T_7643 = oeReg_io_q[2];
assign T_7644 = dsReg[2];
assign T_7645 = ieReg_io_q[2];
assign GEN_213 = io_port_iof_0_2_o_valid ? io_port_iof_0_2_o_oval : swPinCtrl_2_oval;
assign GEN_214 = io_port_iof_0_2_o_valid ? io_port_iof_0_2_o_oe : swPinCtrl_2_oe;
assign GEN_215 = io_port_iof_0_2_o_valid ? io_port_iof_0_2_o_ie : swPinCtrl_2_ie;
assign GEN_216 = io_port_iof_1_2_o_valid ? io_port_iof_1_2_o_oval : swPinCtrl_2_oval;
assign GEN_217 = io_port_iof_1_2_o_valid ? io_port_iof_1_2_o_oe : swPinCtrl_2_oe;
assign GEN_218 = io_port_iof_1_2_o_valid ? io_port_iof_1_2_o_ie : swPinCtrl_2_ie;
assign T_7646 = iofSelReg[2];
assign T_7647_oval = T_7646 ? iof1Ctrl_2_oval : iof0Ctrl_2_oval;
assign T_7647_oe = T_7646 ? iof1Ctrl_2_oe : iof0Ctrl_2_oe;
assign T_7647_ie = T_7646 ? iof1Ctrl_2_ie : iof0Ctrl_2_ie;
assign T_7651 = iofEnReg_io_q[2];
assign T_7652_oval = T_7651 ? iofPlusSwPinCtrl_2_oval : swPinCtrl_2_oval;
assign T_7652_oe = T_7651 ? iofPlusSwPinCtrl_2_oe : swPinCtrl_2_oe;
assign T_7652_ie = T_7651 ? iofPlusSwPinCtrl_2_ie : swPinCtrl_2_ie;
assign T_7652_pue = T_7651 ? iofPlusSwPinCtrl_2_pue : swPinCtrl_2_pue;
assign T_7652_ds = T_7651 ? iofPlusSwPinCtrl_2_ds : swPinCtrl_2_ds;
assign T_7658 = xorReg[2];
assign T_7659 = T_7652_oval ^ T_7658;
assign T_7660 = riseIpReg[2];
assign T_7661 = riseIeReg[2];
assign T_7662 = T_7660 & T_7661;
assign T_7663 = fallIpReg[2];
assign T_7664 = fallIeReg[2];
assign T_7665 = T_7663 & T_7664;
assign T_7666 = T_7662 | T_7665;
assign T_7667 = highIpReg[2];
assign T_7668 = highIeReg[2];
assign T_7669 = T_7667 & T_7668;
assign T_7670 = T_7666 | T_7669;
assign T_7671 = lowIpReg[2];
assign T_7672 = lowIeReg[2];
assign T_7673 = T_7671 & T_7672;
assign T_7674 = T_7670 | T_7673;
assign T_7675 = inSyncReg[2];
assign T_7677 = pueReg_io_q[3];
assign T_7678 = portReg[3];
assign T_7679 = oeReg_io_q[3];
assign T_7680 = dsReg[3];
assign T_7681 = ieReg_io_q[3];
assign GEN_219 = io_port_iof_0_3_o_valid ? io_port_iof_0_3_o_oval : swPinCtrl_3_oval;
assign GEN_220 = io_port_iof_0_3_o_valid ? io_port_iof_0_3_o_oe : swPinCtrl_3_oe;
assign GEN_221 = io_port_iof_0_3_o_valid ? io_port_iof_0_3_o_ie : swPinCtrl_3_ie;
assign GEN_222 = io_port_iof_1_3_o_valid ? io_port_iof_1_3_o_oval : swPinCtrl_3_oval;
assign GEN_223 = io_port_iof_1_3_o_valid ? io_port_iof_1_3_o_oe : swPinCtrl_3_oe;
assign GEN_224 = io_port_iof_1_3_o_valid ? io_port_iof_1_3_o_ie : swPinCtrl_3_ie;
assign T_7682 = iofSelReg[3];
assign T_7683_oval = T_7682 ? iof1Ctrl_3_oval : iof0Ctrl_3_oval;
assign T_7683_oe = T_7682 ? iof1Ctrl_3_oe : iof0Ctrl_3_oe;
assign T_7683_ie = T_7682 ? iof1Ctrl_3_ie : iof0Ctrl_3_ie;
assign T_7687 = iofEnReg_io_q[3];
assign T_7688_oval = T_7687 ? iofPlusSwPinCtrl_3_oval : swPinCtrl_3_oval;
assign T_7688_oe = T_7687 ? iofPlusSwPinCtrl_3_oe : swPinCtrl_3_oe;
assign T_7688_ie = T_7687 ? iofPlusSwPinCtrl_3_ie : swPinCtrl_3_ie;
assign T_7688_pue = T_7687 ? iofPlusSwPinCtrl_3_pue : swPinCtrl_3_pue;
assign T_7688_ds = T_7687 ? iofPlusSwPinCtrl_3_ds : swPinCtrl_3_ds;
assign T_7694 = xorReg[3];
assign T_7695 = T_7688_oval ^ T_7694;
assign T_7696 = riseIpReg[3];
assign T_7697 = riseIeReg[3];
assign T_7698 = T_7696 & T_7697;
assign T_7699 = fallIpReg[3];
assign T_7700 = fallIeReg[3];
assign T_7701 = T_7699 & T_7700;
assign T_7702 = T_7698 | T_7701;
assign T_7703 = highIpReg[3];
assign T_7704 = highIeReg[3];
assign T_7705 = T_7703 & T_7704;
assign T_7706 = T_7702 | T_7705;
assign T_7707 = lowIpReg[3];
assign T_7708 = lowIeReg[3];
assign T_7709 = T_7707 & T_7708;
assign T_7710 = T_7706 | T_7709;
assign T_7711 = inSyncReg[3];
assign T_7713 = pueReg_io_q[4];
assign T_7714 = portReg[4];
assign T_7715 = oeReg_io_q[4];
assign T_7716 = dsReg[4];
assign T_7717 = ieReg_io_q[4];
assign GEN_225 = io_port_iof_0_4_o_valid ? io_port_iof_0_4_o_oval : swPinCtrl_4_oval;
assign GEN_226 = io_port_iof_0_4_o_valid ? io_port_iof_0_4_o_oe : swPinCtrl_4_oe;
assign GEN_227 = io_port_iof_0_4_o_valid ? io_port_iof_0_4_o_ie : swPinCtrl_4_ie;
assign GEN_228 = io_port_iof_1_4_o_valid ? io_port_iof_1_4_o_oval : swPinCtrl_4_oval;
assign GEN_229 = io_port_iof_1_4_o_valid ? io_port_iof_1_4_o_oe : swPinCtrl_4_oe;
assign GEN_230 = io_port_iof_1_4_o_valid ? io_port_iof_1_4_o_ie : swPinCtrl_4_ie;
assign T_7718 = iofSelReg[4];
assign T_7719_oval = T_7718 ? iof1Ctrl_4_oval : iof0Ctrl_4_oval;
assign T_7719_oe = T_7718 ? iof1Ctrl_4_oe : iof0Ctrl_4_oe;
assign T_7719_ie = T_7718 ? iof1Ctrl_4_ie : iof0Ctrl_4_ie;
assign T_7723 = iofEnReg_io_q[4];
assign T_7724_oval = T_7723 ? iofPlusSwPinCtrl_4_oval : swPinCtrl_4_oval;
assign T_7724_oe = T_7723 ? iofPlusSwPinCtrl_4_oe : swPinCtrl_4_oe;
assign T_7724_ie = T_7723 ? iofPlusSwPinCtrl_4_ie : swPinCtrl_4_ie;
assign T_7724_pue = T_7723 ? iofPlusSwPinCtrl_4_pue : swPinCtrl_4_pue;
assign T_7724_ds = T_7723 ? iofPlusSwPinCtrl_4_ds : swPinCtrl_4_ds;
assign T_7730 = xorReg[4];
assign T_7731 = T_7724_oval ^ T_7730;
assign T_7732 = riseIpReg[4];
assign T_7733 = riseIeReg[4];
assign T_7734 = T_7732 & T_7733;
assign T_7735 = fallIpReg[4];
assign T_7736 = fallIeReg[4];
assign T_7737 = T_7735 & T_7736;
assign T_7738 = T_7734 | T_7737;
assign T_7739 = highIpReg[4];
assign T_7740 = highIeReg[4];
assign T_7741 = T_7739 & T_7740;
assign T_7742 = T_7738 | T_7741;
assign T_7743 = lowIpReg[4];
assign T_7744 = lowIeReg[4];
assign T_7745 = T_7743 & T_7744;
assign T_7746 = T_7742 | T_7745;
assign T_7747 = inSyncReg[4];
assign T_7749 = pueReg_io_q[5];
assign T_7750 = portReg[5];
assign T_7751 = oeReg_io_q[5];
assign T_7752 = dsReg[5];
assign T_7753 = ieReg_io_q[5];
assign GEN_231 = io_port_iof_0_5_o_valid ? io_port_iof_0_5_o_oval : swPinCtrl_5_oval;
assign GEN_232 = io_port_iof_0_5_o_valid ? io_port_iof_0_5_o_oe : swPinCtrl_5_oe;
assign GEN_233 = io_port_iof_0_5_o_valid ? io_port_iof_0_5_o_ie : swPinCtrl_5_ie;
assign GEN_234 = io_port_iof_1_5_o_valid ? io_port_iof_1_5_o_oval : swPinCtrl_5_oval;
assign GEN_235 = io_port_iof_1_5_o_valid ? io_port_iof_1_5_o_oe : swPinCtrl_5_oe;
assign GEN_236 = io_port_iof_1_5_o_valid ? io_port_iof_1_5_o_ie : swPinCtrl_5_ie;
assign T_7754 = iofSelReg[5];
assign T_7755_oval = T_7754 ? iof1Ctrl_5_oval : iof0Ctrl_5_oval;
assign T_7755_oe = T_7754 ? iof1Ctrl_5_oe : iof0Ctrl_5_oe;
assign T_7755_ie = T_7754 ? iof1Ctrl_5_ie : iof0Ctrl_5_ie;
assign T_7759 = iofEnReg_io_q[5];
assign T_7760_oval = T_7759 ? iofPlusSwPinCtrl_5_oval : swPinCtrl_5_oval;
assign T_7760_oe = T_7759 ? iofPlusSwPinCtrl_5_oe : swPinCtrl_5_oe;
assign T_7760_ie = T_7759 ? iofPlusSwPinCtrl_5_ie : swPinCtrl_5_ie;
assign T_7760_pue = T_7759 ? iofPlusSwPinCtrl_5_pue : swPinCtrl_5_pue;
assign T_7760_ds = T_7759 ? iofPlusSwPinCtrl_5_ds : swPinCtrl_5_ds;
assign T_7766 = xorReg[5];
assign T_7767 = T_7760_oval ^ T_7766;
assign T_7768 = riseIpReg[5];
assign T_7769 = riseIeReg[5];
assign T_7770 = T_7768 & T_7769;
assign T_7771 = fallIpReg[5];
assign T_7772 = fallIeReg[5];
assign T_7773 = T_7771 & T_7772;
assign T_7774 = T_7770 | T_7773;
assign T_7775 = highIpReg[5];
assign T_7776 = highIeReg[5];
assign T_7777 = T_7775 & T_7776;
assign T_7778 = T_7774 | T_7777;
assign T_7779 = lowIpReg[5];
assign T_7780 = lowIeReg[5];
assign T_7781 = T_7779 & T_7780;
assign T_7782 = T_7778 | T_7781;
assign T_7783 = inSyncReg[5];
assign T_7785 = pueReg_io_q[6];
assign T_7786 = portReg[6];
assign T_7787 = oeReg_io_q[6];
assign T_7788 = dsReg[6];
assign T_7789 = ieReg_io_q[6];
assign GEN_237 = io_port_iof_0_6_o_valid ? io_port_iof_0_6_o_oval : swPinCtrl_6_oval;
assign GEN_238 = io_port_iof_0_6_o_valid ? io_port_iof_0_6_o_oe : swPinCtrl_6_oe;
assign GEN_239 = io_port_iof_0_6_o_valid ? io_port_iof_0_6_o_ie : swPinCtrl_6_ie;
assign GEN_240 = io_port_iof_1_6_o_valid ? io_port_iof_1_6_o_oval : swPinCtrl_6_oval;
assign GEN_241 = io_port_iof_1_6_o_valid ? io_port_iof_1_6_o_oe : swPinCtrl_6_oe;
assign GEN_242 = io_port_iof_1_6_o_valid ? io_port_iof_1_6_o_ie : swPinCtrl_6_ie;
assign T_7790 = iofSelReg[6];
assign T_7791_oval = T_7790 ? iof1Ctrl_6_oval : iof0Ctrl_6_oval;
assign T_7791_oe = T_7790 ? iof1Ctrl_6_oe : iof0Ctrl_6_oe;
assign T_7791_ie = T_7790 ? iof1Ctrl_6_ie : iof0Ctrl_6_ie;
assign T_7795 = iofEnReg_io_q[6];
assign T_7796_oval = T_7795 ? iofPlusSwPinCtrl_6_oval : swPinCtrl_6_oval;
assign T_7796_oe = T_7795 ? iofPlusSwPinCtrl_6_oe : swPinCtrl_6_oe;
assign T_7796_ie = T_7795 ? iofPlusSwPinCtrl_6_ie : swPinCtrl_6_ie;
assign T_7796_pue = T_7795 ? iofPlusSwPinCtrl_6_pue : swPinCtrl_6_pue;
assign T_7796_ds = T_7795 ? iofPlusSwPinCtrl_6_ds : swPinCtrl_6_ds;
assign T_7802 = xorReg[6];
assign T_7803 = T_7796_oval ^ T_7802;
assign T_7804 = riseIpReg[6];
assign T_7805 = riseIeReg[6];
assign T_7806 = T_7804 & T_7805;
assign T_7807 = fallIpReg[6];
assign T_7808 = fallIeReg[6];
assign T_7809 = T_7807 & T_7808;
assign T_7810 = T_7806 | T_7809;
assign T_7811 = highIpReg[6];
assign T_7812 = highIeReg[6];
assign T_7813 = T_7811 & T_7812;
assign T_7814 = T_7810 | T_7813;
assign T_7815 = lowIpReg[6];
assign T_7816 = lowIeReg[6];
assign T_7817 = T_7815 & T_7816;
assign T_7818 = T_7814 | T_7817;
assign T_7819 = inSyncReg[6];
assign T_7821 = pueReg_io_q[7];
assign T_7822 = portReg[7];
assign T_7823 = oeReg_io_q[7];
assign T_7824 = dsReg[7];
assign T_7825 = ieReg_io_q[7];
assign GEN_243 = io_port_iof_0_7_o_valid ? io_port_iof_0_7_o_oval : swPinCtrl_7_oval;
assign GEN_244 = io_port_iof_0_7_o_valid ? io_port_iof_0_7_o_oe : swPinCtrl_7_oe;
assign GEN_245 = io_port_iof_0_7_o_valid ? io_port_iof_0_7_o_ie : swPinCtrl_7_ie;
assign GEN_246 = io_port_iof_1_7_o_valid ? io_port_iof_1_7_o_oval : swPinCtrl_7_oval;
assign GEN_247 = io_port_iof_1_7_o_valid ? io_port_iof_1_7_o_oe : swPinCtrl_7_oe;
assign GEN_248 = io_port_iof_1_7_o_valid ? io_port_iof_1_7_o_ie : swPinCtrl_7_ie;
assign T_7826 = iofSelReg[7];
assign T_7827_oval = T_7826 ? iof1Ctrl_7_oval : iof0Ctrl_7_oval;
assign T_7827_oe = T_7826 ? iof1Ctrl_7_oe : iof0Ctrl_7_oe;
assign T_7827_ie = T_7826 ? iof1Ctrl_7_ie : iof0Ctrl_7_ie;
assign T_7831 = iofEnReg_io_q[7];
assign T_7832_oval = T_7831 ? iofPlusSwPinCtrl_7_oval : swPinCtrl_7_oval;
assign T_7832_oe = T_7831 ? iofPlusSwPinCtrl_7_oe : swPinCtrl_7_oe;
assign T_7832_ie = T_7831 ? iofPlusSwPinCtrl_7_ie : swPinCtrl_7_ie;
assign T_7832_pue = T_7831 ? iofPlusSwPinCtrl_7_pue : swPinCtrl_7_pue;
assign T_7832_ds = T_7831 ? iofPlusSwPinCtrl_7_ds : swPinCtrl_7_ds;
assign T_7838 = xorReg[7];
assign T_7839 = T_7832_oval ^ T_7838;
assign T_7840 = riseIpReg[7];
assign T_7841 = riseIeReg[7];
assign T_7842 = T_7840 & T_7841;
assign T_7843 = fallIpReg[7];
assign T_7844 = fallIeReg[7];
assign T_7845 = T_7843 & T_7844;
assign T_7846 = T_7842 | T_7845;
assign T_7847 = highIpReg[7];
assign T_7848 = highIeReg[7];
assign T_7849 = T_7847 & T_7848;
assign T_7850 = T_7846 | T_7849;
assign T_7851 = lowIpReg[7];
assign T_7852 = lowIeReg[7];
assign T_7853 = T_7851 & T_7852;
assign T_7854 = T_7850 | T_7853;
assign T_7855 = inSyncReg[7];
assign T_7857 = pueReg_io_q[8];
assign T_7858 = portReg[8];
assign T_7859 = oeReg_io_q[8];
assign T_7860 = dsReg[8];
assign T_7861 = ieReg_io_q[8];
assign GEN_249 = io_port_iof_0_8_o_valid ? io_port_iof_0_8_o_oval : swPinCtrl_8_oval;
assign GEN_250 = io_port_iof_0_8_o_valid ? io_port_iof_0_8_o_oe : swPinCtrl_8_oe;
assign GEN_251 = io_port_iof_0_8_o_valid ? io_port_iof_0_8_o_ie : swPinCtrl_8_ie;
assign GEN_252 = io_port_iof_1_8_o_valid ? io_port_iof_1_8_o_oval : swPinCtrl_8_oval;
assign GEN_253 = io_port_iof_1_8_o_valid ? io_port_iof_1_8_o_oe : swPinCtrl_8_oe;
assign GEN_254 = io_port_iof_1_8_o_valid ? io_port_iof_1_8_o_ie : swPinCtrl_8_ie;
assign T_7862 = iofSelReg[8];
assign T_7863_oval = T_7862 ? iof1Ctrl_8_oval : iof0Ctrl_8_oval;
assign T_7863_oe = T_7862 ? iof1Ctrl_8_oe : iof0Ctrl_8_oe;
assign T_7863_ie = T_7862 ? iof1Ctrl_8_ie : iof0Ctrl_8_ie;
assign T_7867 = iofEnReg_io_q[8];
assign T_7868_oval = T_7867 ? iofPlusSwPinCtrl_8_oval : swPinCtrl_8_oval;
assign T_7868_oe = T_7867 ? iofPlusSwPinCtrl_8_oe : swPinCtrl_8_oe;
assign T_7868_ie = T_7867 ? iofPlusSwPinCtrl_8_ie : swPinCtrl_8_ie;
assign T_7868_pue = T_7867 ? iofPlusSwPinCtrl_8_pue : swPinCtrl_8_pue;
assign T_7868_ds = T_7867 ? iofPlusSwPinCtrl_8_ds : swPinCtrl_8_ds;
assign T_7874 = xorReg[8];
assign T_7875 = T_7868_oval ^ T_7874;
assign T_7876 = riseIpReg[8];
assign T_7877 = riseIeReg[8];
assign T_7878 = T_7876 & T_7877;
assign T_7879 = fallIpReg[8];
assign T_7880 = fallIeReg[8];
assign T_7881 = T_7879 & T_7880;
assign T_7882 = T_7878 | T_7881;
assign T_7883 = highIpReg[8];
assign T_7884 = highIeReg[8];
assign T_7885 = T_7883 & T_7884;
assign T_7886 = T_7882 | T_7885;
assign T_7887 = lowIpReg[8];
assign T_7888 = lowIeReg[8];
assign T_7889 = T_7887 & T_7888;
assign T_7890 = T_7886 | T_7889;
assign T_7891 = inSyncReg[8];
assign T_7893 = pueReg_io_q[9];
assign T_7894 = portReg[9];
assign T_7895 = oeReg_io_q[9];
assign T_7896 = dsReg[9];
assign T_7897 = ieReg_io_q[9];
assign GEN_255 = io_port_iof_0_9_o_valid ? io_port_iof_0_9_o_oval : swPinCtrl_9_oval;
assign GEN_256 = io_port_iof_0_9_o_valid ? io_port_iof_0_9_o_oe : swPinCtrl_9_oe;
assign GEN_257 = io_port_iof_0_9_o_valid ? io_port_iof_0_9_o_ie : swPinCtrl_9_ie;
assign GEN_258 = io_port_iof_1_9_o_valid ? io_port_iof_1_9_o_oval : swPinCtrl_9_oval;
assign GEN_259 = io_port_iof_1_9_o_valid ? io_port_iof_1_9_o_oe : swPinCtrl_9_oe;
assign GEN_260 = io_port_iof_1_9_o_valid ? io_port_iof_1_9_o_ie : swPinCtrl_9_ie;
assign T_7898 = iofSelReg[9];
assign T_7899_oval = T_7898 ? iof1Ctrl_9_oval : iof0Ctrl_9_oval;
assign T_7899_oe = T_7898 ? iof1Ctrl_9_oe : iof0Ctrl_9_oe;
assign T_7899_ie = T_7898 ? iof1Ctrl_9_ie : iof0Ctrl_9_ie;
assign T_7903 = iofEnReg_io_q[9];
assign T_7904_oval = T_7903 ? iofPlusSwPinCtrl_9_oval : swPinCtrl_9_oval;
assign T_7904_oe = T_7903 ? iofPlusSwPinCtrl_9_oe : swPinCtrl_9_oe;
assign T_7904_ie = T_7903 ? iofPlusSwPinCtrl_9_ie : swPinCtrl_9_ie;
assign T_7904_pue = T_7903 ? iofPlusSwPinCtrl_9_pue : swPinCtrl_9_pue;
assign T_7904_ds = T_7903 ? iofPlusSwPinCtrl_9_ds : swPinCtrl_9_ds;
assign T_7910 = xorReg[9];
assign T_7911 = T_7904_oval ^ T_7910;
assign T_7912 = riseIpReg[9];
assign T_7913 = riseIeReg[9];
assign T_7914 = T_7912 & T_7913;
assign T_7915 = fallIpReg[9];
assign T_7916 = fallIeReg[9];
assign T_7917 = T_7915 & T_7916;
assign T_7918 = T_7914 | T_7917;
assign T_7919 = highIpReg[9];
assign T_7920 = highIeReg[9];
assign T_7921 = T_7919 & T_7920;
assign T_7922 = T_7918 | T_7921;
assign T_7923 = lowIpReg[9];
assign T_7924 = lowIeReg[9];
assign T_7925 = T_7923 & T_7924;
assign T_7926 = T_7922 | T_7925;
assign T_7927 = inSyncReg[9];
assign T_7929 = pueReg_io_q[10];
assign T_7930 = portReg[10];
assign T_7931 = oeReg_io_q[10];
assign T_7932 = dsReg[10];
assign T_7933 = ieReg_io_q[10];
assign GEN_261 = io_port_iof_0_10_o_valid ? io_port_iof_0_10_o_oval : swPinCtrl_10_oval;
assign GEN_262 = io_port_iof_0_10_o_valid ? io_port_iof_0_10_o_oe : swPinCtrl_10_oe;
assign GEN_263 = io_port_iof_0_10_o_valid ? io_port_iof_0_10_o_ie : swPinCtrl_10_ie;
assign GEN_264 = io_port_iof_1_10_o_valid ? io_port_iof_1_10_o_oval : swPinCtrl_10_oval;
assign GEN_265 = io_port_iof_1_10_o_valid ? io_port_iof_1_10_o_oe : swPinCtrl_10_oe;
assign GEN_266 = io_port_iof_1_10_o_valid ? io_port_iof_1_10_o_ie : swPinCtrl_10_ie;
assign T_7934 = iofSelReg[10];
assign T_7935_oval = T_7934 ? iof1Ctrl_10_oval : iof0Ctrl_10_oval;
assign T_7935_oe = T_7934 ? iof1Ctrl_10_oe : iof0Ctrl_10_oe;
assign T_7935_ie = T_7934 ? iof1Ctrl_10_ie : iof0Ctrl_10_ie;
assign T_7939 = iofEnReg_io_q[10];
assign T_7940_oval = T_7939 ? iofPlusSwPinCtrl_10_oval : swPinCtrl_10_oval;
assign T_7940_oe = T_7939 ? iofPlusSwPinCtrl_10_oe : swPinCtrl_10_oe;
assign T_7940_ie = T_7939 ? iofPlusSwPinCtrl_10_ie : swPinCtrl_10_ie;
assign T_7940_pue = T_7939 ? iofPlusSwPinCtrl_10_pue : swPinCtrl_10_pue;
assign T_7940_ds = T_7939 ? iofPlusSwPinCtrl_10_ds : swPinCtrl_10_ds;
assign T_7946 = xorReg[10];
assign T_7947 = T_7940_oval ^ T_7946;
assign T_7948 = riseIpReg[10];
assign T_7949 = riseIeReg[10];
assign T_7950 = T_7948 & T_7949;
assign T_7951 = fallIpReg[10];
assign T_7952 = fallIeReg[10];
assign T_7953 = T_7951 & T_7952;
assign T_7954 = T_7950 | T_7953;
assign T_7955 = highIpReg[10];
assign T_7956 = highIeReg[10];
assign T_7957 = T_7955 & T_7956;
assign T_7958 = T_7954 | T_7957;
assign T_7959 = lowIpReg[10];
assign T_7960 = lowIeReg[10];
assign T_7961 = T_7959 & T_7960;
assign T_7962 = T_7958 | T_7961;
assign T_7963 = inSyncReg[10];
assign T_7965 = pueReg_io_q[11];
assign T_7966 = portReg[11];
assign T_7967 = oeReg_io_q[11];
assign T_7968 = dsReg[11];
assign T_7969 = ieReg_io_q[11];
assign GEN_267 = io_port_iof_0_11_o_valid ? io_port_iof_0_11_o_oval : swPinCtrl_11_oval;
assign GEN_268 = io_port_iof_0_11_o_valid ? io_port_iof_0_11_o_oe : swPinCtrl_11_oe;
assign GEN_269 = io_port_iof_0_11_o_valid ? io_port_iof_0_11_o_ie : swPinCtrl_11_ie;
assign GEN_270 = io_port_iof_1_11_o_valid ? io_port_iof_1_11_o_oval : swPinCtrl_11_oval;
assign GEN_271 = io_port_iof_1_11_o_valid ? io_port_iof_1_11_o_oe : swPinCtrl_11_oe;
assign GEN_272 = io_port_iof_1_11_o_valid ? io_port_iof_1_11_o_ie : swPinCtrl_11_ie;
assign T_7970 = iofSelReg[11];
assign T_7971_oval = T_7970 ? iof1Ctrl_11_oval : iof0Ctrl_11_oval;
assign T_7971_oe = T_7970 ? iof1Ctrl_11_oe : iof0Ctrl_11_oe;
assign T_7971_ie = T_7970 ? iof1Ctrl_11_ie : iof0Ctrl_11_ie;
assign T_7975 = iofEnReg_io_q[11];
assign T_7976_oval = T_7975 ? iofPlusSwPinCtrl_11_oval : swPinCtrl_11_oval;
assign T_7976_oe = T_7975 ? iofPlusSwPinCtrl_11_oe : swPinCtrl_11_oe;
assign T_7976_ie = T_7975 ? iofPlusSwPinCtrl_11_ie : swPinCtrl_11_ie;
assign T_7976_pue = T_7975 ? iofPlusSwPinCtrl_11_pue : swPinCtrl_11_pue;
assign T_7976_ds = T_7975 ? iofPlusSwPinCtrl_11_ds : swPinCtrl_11_ds;
assign T_7982 = xorReg[11];
assign T_7983 = T_7976_oval ^ T_7982;
assign T_7984 = riseIpReg[11];
assign T_7985 = riseIeReg[11];
assign T_7986 = T_7984 & T_7985;
assign T_7987 = fallIpReg[11];
assign T_7988 = fallIeReg[11];
assign T_7989 = T_7987 & T_7988;
assign T_7990 = T_7986 | T_7989;
assign T_7991 = highIpReg[11];
assign T_7992 = highIeReg[11];
assign T_7993 = T_7991 & T_7992;
assign T_7994 = T_7990 | T_7993;
assign T_7995 = lowIpReg[11];
assign T_7996 = lowIeReg[11];
assign T_7997 = T_7995 & T_7996;
assign T_7998 = T_7994 | T_7997;
assign T_7999 = inSyncReg[11];
assign T_8001 = pueReg_io_q[12];
assign T_8002 = portReg[12];
assign T_8003 = oeReg_io_q[12];
assign T_8004 = dsReg[12];
assign T_8005 = ieReg_io_q[12];
assign GEN_273 = io_port_iof_0_12_o_valid ? io_port_iof_0_12_o_oval : swPinCtrl_12_oval;
assign GEN_274 = io_port_iof_0_12_o_valid ? io_port_iof_0_12_o_oe : swPinCtrl_12_oe;
assign GEN_275 = io_port_iof_0_12_o_valid ? io_port_iof_0_12_o_ie : swPinCtrl_12_ie;
assign GEN_276 = io_port_iof_1_12_o_valid ? io_port_iof_1_12_o_oval : swPinCtrl_12_oval;
assign GEN_277 = io_port_iof_1_12_o_valid ? io_port_iof_1_12_o_oe : swPinCtrl_12_oe;
assign GEN_278 = io_port_iof_1_12_o_valid ? io_port_iof_1_12_o_ie : swPinCtrl_12_ie;
assign T_8006 = iofSelReg[12];
assign T_8007_oval = T_8006 ? iof1Ctrl_12_oval : iof0Ctrl_12_oval;
assign T_8007_oe = T_8006 ? iof1Ctrl_12_oe : iof0Ctrl_12_oe;
assign T_8007_ie = T_8006 ? iof1Ctrl_12_ie : iof0Ctrl_12_ie;
assign T_8011 = iofEnReg_io_q[12];
assign T_8012_oval = T_8011 ? iofPlusSwPinCtrl_12_oval : swPinCtrl_12_oval;
assign T_8012_oe = T_8011 ? iofPlusSwPinCtrl_12_oe : swPinCtrl_12_oe;
assign T_8012_ie = T_8011 ? iofPlusSwPinCtrl_12_ie : swPinCtrl_12_ie;
assign T_8012_pue = T_8011 ? iofPlusSwPinCtrl_12_pue : swPinCtrl_12_pue;
assign T_8012_ds = T_8011 ? iofPlusSwPinCtrl_12_ds : swPinCtrl_12_ds;
assign T_8018 = xorReg[12];
assign T_8019 = T_8012_oval ^ T_8018;
assign T_8020 = riseIpReg[12];
assign T_8021 = riseIeReg[12];
assign T_8022 = T_8020 & T_8021;
assign T_8023 = fallIpReg[12];
assign T_8024 = fallIeReg[12];
assign T_8025 = T_8023 & T_8024;
assign T_8026 = T_8022 | T_8025;
assign T_8027 = highIpReg[12];
assign T_8028 = highIeReg[12];
assign T_8029 = T_8027 & T_8028;
assign T_8030 = T_8026 | T_8029;
assign T_8031 = lowIpReg[12];
assign T_8032 = lowIeReg[12];
assign T_8033 = T_8031 & T_8032;
assign T_8034 = T_8030 | T_8033;
assign T_8035 = inSyncReg[12];
assign T_8037 = pueReg_io_q[13];
assign T_8038 = portReg[13];
assign T_8039 = oeReg_io_q[13];
assign T_8040 = dsReg[13];
assign T_8041 = ieReg_io_q[13];
assign GEN_279 = io_port_iof_0_13_o_valid ? io_port_iof_0_13_o_oval : swPinCtrl_13_oval;
assign GEN_280 = io_port_iof_0_13_o_valid ? io_port_iof_0_13_o_oe : swPinCtrl_13_oe;
assign GEN_281 = io_port_iof_0_13_o_valid ? io_port_iof_0_13_o_ie : swPinCtrl_13_ie;
assign GEN_282 = io_port_iof_1_13_o_valid ? io_port_iof_1_13_o_oval : swPinCtrl_13_oval;
assign GEN_283 = io_port_iof_1_13_o_valid ? io_port_iof_1_13_o_oe : swPinCtrl_13_oe;
assign GEN_284 = io_port_iof_1_13_o_valid ? io_port_iof_1_13_o_ie : swPinCtrl_13_ie;
assign T_8042 = iofSelReg[13];
assign T_8043_oval = T_8042 ? iof1Ctrl_13_oval : iof0Ctrl_13_oval;
assign T_8043_oe = T_8042 ? iof1Ctrl_13_oe : iof0Ctrl_13_oe;
assign T_8043_ie = T_8042 ? iof1Ctrl_13_ie : iof0Ctrl_13_ie;
assign T_8047 = iofEnReg_io_q[13];
assign T_8048_oval = T_8047 ? iofPlusSwPinCtrl_13_oval : swPinCtrl_13_oval;
assign T_8048_oe = T_8047 ? iofPlusSwPinCtrl_13_oe : swPinCtrl_13_oe;
assign T_8048_ie = T_8047 ? iofPlusSwPinCtrl_13_ie : swPinCtrl_13_ie;
assign T_8048_pue = T_8047 ? iofPlusSwPinCtrl_13_pue : swPinCtrl_13_pue;
assign T_8048_ds = T_8047 ? iofPlusSwPinCtrl_13_ds : swPinCtrl_13_ds;
assign T_8054 = xorReg[13];
assign T_8055 = T_8048_oval ^ T_8054;
assign T_8056 = riseIpReg[13];
assign T_8057 = riseIeReg[13];
assign T_8058 = T_8056 & T_8057;
assign T_8059 = fallIpReg[13];
assign T_8060 = fallIeReg[13];
assign T_8061 = T_8059 & T_8060;
assign T_8062 = T_8058 | T_8061;
assign T_8063 = highIpReg[13];
assign T_8064 = highIeReg[13];
assign T_8065 = T_8063 & T_8064;
assign T_8066 = T_8062 | T_8065;
assign T_8067 = lowIpReg[13];
assign T_8068 = lowIeReg[13];
assign T_8069 = T_8067 & T_8068;
assign T_8070 = T_8066 | T_8069;
assign T_8071 = inSyncReg[13];
assign T_8073 = pueReg_io_q[14];
assign T_8074 = portReg[14];
assign T_8075 = oeReg_io_q[14];
assign T_8076 = dsReg[14];
assign T_8077 = ieReg_io_q[14];
assign GEN_285 = io_port_iof_0_14_o_valid ? io_port_iof_0_14_o_oval : swPinCtrl_14_oval;
assign GEN_286 = io_port_iof_0_14_o_valid ? io_port_iof_0_14_o_oe : swPinCtrl_14_oe;
assign GEN_287 = io_port_iof_0_14_o_valid ? io_port_iof_0_14_o_ie : swPinCtrl_14_ie;
assign GEN_288 = io_port_iof_1_14_o_valid ? io_port_iof_1_14_o_oval : swPinCtrl_14_oval;
assign GEN_289 = io_port_iof_1_14_o_valid ? io_port_iof_1_14_o_oe : swPinCtrl_14_oe;
assign GEN_290 = io_port_iof_1_14_o_valid ? io_port_iof_1_14_o_ie : swPinCtrl_14_ie;
assign T_8078 = iofSelReg[14];
assign T_8079_oval = T_8078 ? iof1Ctrl_14_oval : iof0Ctrl_14_oval;
assign T_8079_oe = T_8078 ? iof1Ctrl_14_oe : iof0Ctrl_14_oe;
assign T_8079_ie = T_8078 ? iof1Ctrl_14_ie : iof0Ctrl_14_ie;
assign T_8083 = iofEnReg_io_q[14];
assign T_8084_oval = T_8083 ? iofPlusSwPinCtrl_14_oval : swPinCtrl_14_oval;
assign T_8084_oe = T_8083 ? iofPlusSwPinCtrl_14_oe : swPinCtrl_14_oe;
assign T_8084_ie = T_8083 ? iofPlusSwPinCtrl_14_ie : swPinCtrl_14_ie;
assign T_8084_pue = T_8083 ? iofPlusSwPinCtrl_14_pue : swPinCtrl_14_pue;
assign T_8084_ds = T_8083 ? iofPlusSwPinCtrl_14_ds : swPinCtrl_14_ds;
assign T_8090 = xorReg[14];
assign T_8091 = T_8084_oval ^ T_8090;
assign T_8092 = riseIpReg[14];
assign T_8093 = riseIeReg[14];
assign T_8094 = T_8092 & T_8093;
assign T_8095 = fallIpReg[14];
assign T_8096 = fallIeReg[14];
assign T_8097 = T_8095 & T_8096;
assign T_8098 = T_8094 | T_8097;
assign T_8099 = highIpReg[14];
assign T_8100 = highIeReg[14];
assign T_8101 = T_8099 & T_8100;
assign T_8102 = T_8098 | T_8101;
assign T_8103 = lowIpReg[14];
assign T_8104 = lowIeReg[14];
assign T_8105 = T_8103 & T_8104;
assign T_8106 = T_8102 | T_8105;
assign T_8107 = inSyncReg[14];
assign T_8109 = pueReg_io_q[15];
assign T_8110 = portReg[15];
assign T_8111 = oeReg_io_q[15];
assign T_8112 = dsReg[15];
assign T_8113 = ieReg_io_q[15];
assign GEN_291 = io_port_iof_0_15_o_valid ? io_port_iof_0_15_o_oval : swPinCtrl_15_oval;
assign GEN_292 = io_port_iof_0_15_o_valid ? io_port_iof_0_15_o_oe : swPinCtrl_15_oe;
assign GEN_293 = io_port_iof_0_15_o_valid ? io_port_iof_0_15_o_ie : swPinCtrl_15_ie;
assign GEN_294 = io_port_iof_1_15_o_valid ? io_port_iof_1_15_o_oval : swPinCtrl_15_oval;
assign GEN_295 = io_port_iof_1_15_o_valid ? io_port_iof_1_15_o_oe : swPinCtrl_15_oe;
assign GEN_296 = io_port_iof_1_15_o_valid ? io_port_iof_1_15_o_ie : swPinCtrl_15_ie;
assign T_8114 = iofSelReg[15];
assign T_8115_oval = T_8114 ? iof1Ctrl_15_oval : iof0Ctrl_15_oval;
assign T_8115_oe = T_8114 ? iof1Ctrl_15_oe : iof0Ctrl_15_oe;
assign T_8115_ie = T_8114 ? iof1Ctrl_15_ie : iof0Ctrl_15_ie;
assign T_8119 = iofEnReg_io_q[15];
assign T_8120_oval = T_8119 ? iofPlusSwPinCtrl_15_oval : swPinCtrl_15_oval;
assign T_8120_oe = T_8119 ? iofPlusSwPinCtrl_15_oe : swPinCtrl_15_oe;
assign T_8120_ie = T_8119 ? iofPlusSwPinCtrl_15_ie : swPinCtrl_15_ie;
assign T_8120_pue = T_8119 ? iofPlusSwPinCtrl_15_pue : swPinCtrl_15_pue;
assign T_8120_ds = T_8119 ? iofPlusSwPinCtrl_15_ds : swPinCtrl_15_ds;
assign T_8126 = xorReg[15];
assign T_8127 = T_8120_oval ^ T_8126;
assign T_8128 = riseIpReg[15];
assign T_8129 = riseIeReg[15];
assign T_8130 = T_8128 & T_8129;
assign T_8131 = fallIpReg[15];
assign T_8132 = fallIeReg[15];
assign T_8133 = T_8131 & T_8132;
assign T_8134 = T_8130 | T_8133;
assign T_8135 = highIpReg[15];
assign T_8136 = highIeReg[15];
assign T_8137 = T_8135 & T_8136;
assign T_8138 = T_8134 | T_8137;
assign T_8139 = lowIpReg[15];
assign T_8140 = lowIeReg[15];
assign T_8141 = T_8139 & T_8140;
assign T_8142 = T_8138 | T_8141;
assign T_8143 = inSyncReg[15];
assign T_8145 = pueReg_io_q[16];
assign T_8146 = portReg[16];
assign T_8147 = oeReg_io_q[16];
assign T_8148 = dsReg[16];
assign T_8149 = ieReg_io_q[16];
assign GEN_297 = io_port_iof_0_16_o_valid ? io_port_iof_0_16_o_oval : swPinCtrl_16_oval;
assign GEN_298 = io_port_iof_0_16_o_valid ? io_port_iof_0_16_o_oe : swPinCtrl_16_oe;
assign GEN_299 = io_port_iof_0_16_o_valid ? io_port_iof_0_16_o_ie : swPinCtrl_16_ie;
assign GEN_300 = io_port_iof_1_16_o_valid ? io_port_iof_1_16_o_oval : swPinCtrl_16_oval;
assign GEN_301 = io_port_iof_1_16_o_valid ? io_port_iof_1_16_o_oe : swPinCtrl_16_oe;
assign GEN_302 = io_port_iof_1_16_o_valid ? io_port_iof_1_16_o_ie : swPinCtrl_16_ie;
assign T_8150 = iofSelReg[16];
assign T_8151_oval = T_8150 ? iof1Ctrl_16_oval : iof0Ctrl_16_oval;
assign T_8151_oe = T_8150 ? iof1Ctrl_16_oe : iof0Ctrl_16_oe;
assign T_8151_ie = T_8150 ? iof1Ctrl_16_ie : iof0Ctrl_16_ie;
assign T_8155 = iofEnReg_io_q[16];
assign T_8156_oval = T_8155 ? iofPlusSwPinCtrl_16_oval : swPinCtrl_16_oval;
assign T_8156_oe = T_8155 ? iofPlusSwPinCtrl_16_oe : swPinCtrl_16_oe;
assign T_8156_ie = T_8155 ? iofPlusSwPinCtrl_16_ie : swPinCtrl_16_ie;
assign T_8156_pue = T_8155 ? iofPlusSwPinCtrl_16_pue : swPinCtrl_16_pue;
assign T_8156_ds = T_8155 ? iofPlusSwPinCtrl_16_ds : swPinCtrl_16_ds;
assign T_8162 = xorReg[16];
assign T_8163 = T_8156_oval ^ T_8162;
assign T_8164 = riseIpReg[16];
assign T_8165 = riseIeReg[16];
assign T_8166 = T_8164 & T_8165;
assign T_8167 = fallIpReg[16];
assign T_8168 = fallIeReg[16];
assign T_8169 = T_8167 & T_8168;
assign T_8170 = T_8166 | T_8169;
assign T_8171 = highIpReg[16];
assign T_8172 = highIeReg[16];
assign T_8173 = T_8171 & T_8172;
assign T_8174 = T_8170 | T_8173;
assign T_8175 = lowIpReg[16];
assign T_8176 = lowIeReg[16];
assign T_8177 = T_8175 & T_8176;
assign T_8178 = T_8174 | T_8177;
assign T_8179 = inSyncReg[16];
assign T_8181 = pueReg_io_q[17];
assign T_8182 = portReg[17];
assign T_8183 = oeReg_io_q[17];
assign T_8184 = dsReg[17];
assign T_8185 = ieReg_io_q[17];
assign GEN_303 = io_port_iof_0_17_o_valid ? io_port_iof_0_17_o_oval : swPinCtrl_17_oval;
assign GEN_304 = io_port_iof_0_17_o_valid ? io_port_iof_0_17_o_oe : swPinCtrl_17_oe;
assign GEN_305 = io_port_iof_0_17_o_valid ? io_port_iof_0_17_o_ie : swPinCtrl_17_ie;
assign GEN_306 = io_port_iof_1_17_o_valid ? io_port_iof_1_17_o_oval : swPinCtrl_17_oval;
assign GEN_307 = io_port_iof_1_17_o_valid ? io_port_iof_1_17_o_oe : swPinCtrl_17_oe;
assign GEN_308 = io_port_iof_1_17_o_valid ? io_port_iof_1_17_o_ie : swPinCtrl_17_ie;
assign T_8186 = iofSelReg[17];
assign T_8187_oval = T_8186 ? iof1Ctrl_17_oval : iof0Ctrl_17_oval;
assign T_8187_oe = T_8186 ? iof1Ctrl_17_oe : iof0Ctrl_17_oe;
assign T_8187_ie = T_8186 ? iof1Ctrl_17_ie : iof0Ctrl_17_ie;
assign T_8191 = iofEnReg_io_q[17];
assign T_8192_oval = T_8191 ? iofPlusSwPinCtrl_17_oval : swPinCtrl_17_oval;
assign T_8192_oe = T_8191 ? iofPlusSwPinCtrl_17_oe : swPinCtrl_17_oe;
assign T_8192_ie = T_8191 ? iofPlusSwPinCtrl_17_ie : swPinCtrl_17_ie;
assign T_8192_pue = T_8191 ? iofPlusSwPinCtrl_17_pue : swPinCtrl_17_pue;
assign T_8192_ds = T_8191 ? iofPlusSwPinCtrl_17_ds : swPinCtrl_17_ds;
assign T_8198 = xorReg[17];
assign T_8199 = T_8192_oval ^ T_8198;
assign T_8200 = riseIpReg[17];
assign T_8201 = riseIeReg[17];
assign T_8202 = T_8200 & T_8201;
assign T_8203 = fallIpReg[17];
assign T_8204 = fallIeReg[17];
assign T_8205 = T_8203 & T_8204;
assign T_8206 = T_8202 | T_8205;
assign T_8207 = highIpReg[17];
assign T_8208 = highIeReg[17];
assign T_8209 = T_8207 & T_8208;
assign T_8210 = T_8206 | T_8209;
assign T_8211 = lowIpReg[17];
assign T_8212 = lowIeReg[17];
assign T_8213 = T_8211 & T_8212;
assign T_8214 = T_8210 | T_8213;
assign T_8215 = inSyncReg[17];
assign T_8217 = pueReg_io_q[18];
assign T_8218 = portReg[18];
assign T_8219 = oeReg_io_q[18];
assign T_8220 = dsReg[18];
assign T_8221 = ieReg_io_q[18];
assign GEN_309 = io_port_iof_0_18_o_valid ? io_port_iof_0_18_o_oval : swPinCtrl_18_oval;
assign GEN_310 = io_port_iof_0_18_o_valid ? io_port_iof_0_18_o_oe : swPinCtrl_18_oe;
assign GEN_311 = io_port_iof_0_18_o_valid ? io_port_iof_0_18_o_ie : swPinCtrl_18_ie;
assign GEN_312 = io_port_iof_1_18_o_valid ? io_port_iof_1_18_o_oval : swPinCtrl_18_oval;
assign GEN_313 = io_port_iof_1_18_o_valid ? io_port_iof_1_18_o_oe : swPinCtrl_18_oe;
assign GEN_314 = io_port_iof_1_18_o_valid ? io_port_iof_1_18_o_ie : swPinCtrl_18_ie;
assign T_8222 = iofSelReg[18];
assign T_8223_oval = T_8222 ? iof1Ctrl_18_oval : iof0Ctrl_18_oval;
assign T_8223_oe = T_8222 ? iof1Ctrl_18_oe : iof0Ctrl_18_oe;
assign T_8223_ie = T_8222 ? iof1Ctrl_18_ie : iof0Ctrl_18_ie;
assign T_8227 = iofEnReg_io_q[18];
assign T_8228_oval = T_8227 ? iofPlusSwPinCtrl_18_oval : swPinCtrl_18_oval;
assign T_8228_oe = T_8227 ? iofPlusSwPinCtrl_18_oe : swPinCtrl_18_oe;
assign T_8228_ie = T_8227 ? iofPlusSwPinCtrl_18_ie : swPinCtrl_18_ie;
assign T_8228_pue = T_8227 ? iofPlusSwPinCtrl_18_pue : swPinCtrl_18_pue;
assign T_8228_ds = T_8227 ? iofPlusSwPinCtrl_18_ds : swPinCtrl_18_ds;
assign T_8234 = xorReg[18];
assign T_8235 = T_8228_oval ^ T_8234;
assign T_8236 = riseIpReg[18];
assign T_8237 = riseIeReg[18];
assign T_8238 = T_8236 & T_8237;
assign T_8239 = fallIpReg[18];
assign T_8240 = fallIeReg[18];
assign T_8241 = T_8239 & T_8240;
assign T_8242 = T_8238 | T_8241;
assign T_8243 = highIpReg[18];
assign T_8244 = highIeReg[18];
assign T_8245 = T_8243 & T_8244;
assign T_8246 = T_8242 | T_8245;
assign T_8247 = lowIpReg[18];
assign T_8248 = lowIeReg[18];
assign T_8249 = T_8247 & T_8248;
assign T_8250 = T_8246 | T_8249;
assign T_8251 = inSyncReg[18];
assign T_8253 = pueReg_io_q[19];
assign T_8254 = portReg[19];
assign T_8255 = oeReg_io_q[19];
assign T_8256 = dsReg[19];
assign T_8257 = ieReg_io_q[19];
assign GEN_315 = io_port_iof_0_19_o_valid ? io_port_iof_0_19_o_oval : swPinCtrl_19_oval;
assign GEN_316 = io_port_iof_0_19_o_valid ? io_port_iof_0_19_o_oe : swPinCtrl_19_oe;
assign GEN_317 = io_port_iof_0_19_o_valid ? io_port_iof_0_19_o_ie : swPinCtrl_19_ie;
assign GEN_318 = io_port_iof_1_19_o_valid ? io_port_iof_1_19_o_oval : swPinCtrl_19_oval;
assign GEN_319 = io_port_iof_1_19_o_valid ? io_port_iof_1_19_o_oe : swPinCtrl_19_oe;
assign GEN_320 = io_port_iof_1_19_o_valid ? io_port_iof_1_19_o_ie : swPinCtrl_19_ie;
assign T_8258 = iofSelReg[19];
assign T_8259_oval = T_8258 ? iof1Ctrl_19_oval : iof0Ctrl_19_oval;
assign T_8259_oe = T_8258 ? iof1Ctrl_19_oe : iof0Ctrl_19_oe;
assign T_8259_ie = T_8258 ? iof1Ctrl_19_ie : iof0Ctrl_19_ie;
assign T_8263 = iofEnReg_io_q[19];
assign T_8264_oval = T_8263 ? iofPlusSwPinCtrl_19_oval : swPinCtrl_19_oval;
assign T_8264_oe = T_8263 ? iofPlusSwPinCtrl_19_oe : swPinCtrl_19_oe;
assign T_8264_ie = T_8263 ? iofPlusSwPinCtrl_19_ie : swPinCtrl_19_ie;
assign T_8264_pue = T_8263 ? iofPlusSwPinCtrl_19_pue : swPinCtrl_19_pue;
assign T_8264_ds = T_8263 ? iofPlusSwPinCtrl_19_ds : swPinCtrl_19_ds;
assign T_8270 = xorReg[19];
assign T_8271 = T_8264_oval ^ T_8270;
assign T_8272 = riseIpReg[19];
assign T_8273 = riseIeReg[19];
assign T_8274 = T_8272 & T_8273;
assign T_8275 = fallIpReg[19];
assign T_8276 = fallIeReg[19];
assign T_8277 = T_8275 & T_8276;
assign T_8278 = T_8274 | T_8277;
assign T_8279 = highIpReg[19];
assign T_8280 = highIeReg[19];
assign T_8281 = T_8279 & T_8280;
assign T_8282 = T_8278 | T_8281;
assign T_8283 = lowIpReg[19];
assign T_8284 = lowIeReg[19];
assign T_8285 = T_8283 & T_8284;
assign T_8286 = T_8282 | T_8285;
assign T_8287 = inSyncReg[19];
assign T_8289 = pueReg_io_q[20];
assign T_8290 = portReg[20];
assign T_8291 = oeReg_io_q[20];
assign T_8292 = dsReg[20];
assign T_8293 = ieReg_io_q[20];
assign GEN_321 = io_port_iof_0_20_o_valid ? io_port_iof_0_20_o_oval : swPinCtrl_20_oval;
assign GEN_322 = io_port_iof_0_20_o_valid ? io_port_iof_0_20_o_oe : swPinCtrl_20_oe;
assign GEN_323 = io_port_iof_0_20_o_valid ? io_port_iof_0_20_o_ie : swPinCtrl_20_ie;
assign GEN_324 = io_port_iof_1_20_o_valid ? io_port_iof_1_20_o_oval : swPinCtrl_20_oval;
assign GEN_325 = io_port_iof_1_20_o_valid ? io_port_iof_1_20_o_oe : swPinCtrl_20_oe;
assign GEN_326 = io_port_iof_1_20_o_valid ? io_port_iof_1_20_o_ie : swPinCtrl_20_ie;
assign T_8294 = iofSelReg[20];
assign T_8295_oval = T_8294 ? iof1Ctrl_20_oval : iof0Ctrl_20_oval;
assign T_8295_oe = T_8294 ? iof1Ctrl_20_oe : iof0Ctrl_20_oe;
assign T_8295_ie = T_8294 ? iof1Ctrl_20_ie : iof0Ctrl_20_ie;
assign T_8299 = iofEnReg_io_q[20];
assign T_8300_oval = T_8299 ? iofPlusSwPinCtrl_20_oval : swPinCtrl_20_oval;
assign T_8300_oe = T_8299 ? iofPlusSwPinCtrl_20_oe : swPinCtrl_20_oe;
assign T_8300_ie = T_8299 ? iofPlusSwPinCtrl_20_ie : swPinCtrl_20_ie;
assign T_8300_pue = T_8299 ? iofPlusSwPinCtrl_20_pue : swPinCtrl_20_pue;
assign T_8300_ds = T_8299 ? iofPlusSwPinCtrl_20_ds : swPinCtrl_20_ds;
assign T_8306 = xorReg[20];
assign T_8307 = T_8300_oval ^ T_8306;
assign T_8308 = riseIpReg[20];
assign T_8309 = riseIeReg[20];
assign T_8310 = T_8308 & T_8309;
assign T_8311 = fallIpReg[20];
assign T_8312 = fallIeReg[20];
assign T_8313 = T_8311 & T_8312;
assign T_8314 = T_8310 | T_8313;
assign T_8315 = highIpReg[20];
assign T_8316 = highIeReg[20];
assign T_8317 = T_8315 & T_8316;
assign T_8318 = T_8314 | T_8317;
assign T_8319 = lowIpReg[20];
assign T_8320 = lowIeReg[20];
assign T_8321 = T_8319 & T_8320;
assign T_8322 = T_8318 | T_8321;
assign T_8323 = inSyncReg[20];
assign T_8325 = pueReg_io_q[21];
assign T_8326 = portReg[21];
assign T_8327 = oeReg_io_q[21];
assign T_8328 = dsReg[21];
assign T_8329 = ieReg_io_q[21];
assign GEN_327 = io_port_iof_0_21_o_valid ? io_port_iof_0_21_o_oval : swPinCtrl_21_oval;
assign GEN_328 = io_port_iof_0_21_o_valid ? io_port_iof_0_21_o_oe : swPinCtrl_21_oe;
assign GEN_329 = io_port_iof_0_21_o_valid ? io_port_iof_0_21_o_ie : swPinCtrl_21_ie;
assign GEN_330 = io_port_iof_1_21_o_valid ? io_port_iof_1_21_o_oval : swPinCtrl_21_oval;
assign GEN_331 = io_port_iof_1_21_o_valid ? io_port_iof_1_21_o_oe : swPinCtrl_21_oe;
assign GEN_332 = io_port_iof_1_21_o_valid ? io_port_iof_1_21_o_ie : swPinCtrl_21_ie;
assign T_8330 = iofSelReg[21];
assign T_8331_oval = T_8330 ? iof1Ctrl_21_oval : iof0Ctrl_21_oval;
assign T_8331_oe = T_8330 ? iof1Ctrl_21_oe : iof0Ctrl_21_oe;
assign T_8331_ie = T_8330 ? iof1Ctrl_21_ie : iof0Ctrl_21_ie;
assign T_8335 = iofEnReg_io_q[21];
assign T_8336_oval = T_8335 ? iofPlusSwPinCtrl_21_oval : swPinCtrl_21_oval;
assign T_8336_oe = T_8335 ? iofPlusSwPinCtrl_21_oe : swPinCtrl_21_oe;
assign T_8336_ie = T_8335 ? iofPlusSwPinCtrl_21_ie : swPinCtrl_21_ie;
assign T_8336_pue = T_8335 ? iofPlusSwPinCtrl_21_pue : swPinCtrl_21_pue;
assign T_8336_ds = T_8335 ? iofPlusSwPinCtrl_21_ds : swPinCtrl_21_ds;
assign T_8342 = xorReg[21];
assign T_8343 = T_8336_oval ^ T_8342;
assign T_8344 = riseIpReg[21];
assign T_8345 = riseIeReg[21];
assign T_8346 = T_8344 & T_8345;
assign T_8347 = fallIpReg[21];
assign T_8348 = fallIeReg[21];
assign T_8349 = T_8347 & T_8348;
assign T_8350 = T_8346 | T_8349;
assign T_8351 = highIpReg[21];
assign T_8352 = highIeReg[21];
assign T_8353 = T_8351 & T_8352;
assign T_8354 = T_8350 | T_8353;
assign T_8355 = lowIpReg[21];
assign T_8356 = lowIeReg[21];
assign T_8357 = T_8355 & T_8356;
assign T_8358 = T_8354 | T_8357;
assign T_8359 = inSyncReg[21];
assign T_8361 = pueReg_io_q[22];
assign T_8362 = portReg[22];
assign T_8363 = oeReg_io_q[22];
assign T_8364 = dsReg[22];
assign T_8365 = ieReg_io_q[22];
assign GEN_333 = io_port_iof_0_22_o_valid ? io_port_iof_0_22_o_oval : swPinCtrl_22_oval;
assign GEN_334 = io_port_iof_0_22_o_valid ? io_port_iof_0_22_o_oe : swPinCtrl_22_oe;
assign GEN_335 = io_port_iof_0_22_o_valid ? io_port_iof_0_22_o_ie : swPinCtrl_22_ie;
assign GEN_336 = io_port_iof_1_22_o_valid ? io_port_iof_1_22_o_oval : swPinCtrl_22_oval;
assign GEN_337 = io_port_iof_1_22_o_valid ? io_port_iof_1_22_o_oe : swPinCtrl_22_oe;
assign GEN_338 = io_port_iof_1_22_o_valid ? io_port_iof_1_22_o_ie : swPinCtrl_22_ie;
assign T_8366 = iofSelReg[22];
assign T_8367_oval = T_8366 ? iof1Ctrl_22_oval : iof0Ctrl_22_oval;
assign T_8367_oe = T_8366 ? iof1Ctrl_22_oe : iof0Ctrl_22_oe;
assign T_8367_ie = T_8366 ? iof1Ctrl_22_ie : iof0Ctrl_22_ie;
assign T_8371 = iofEnReg_io_q[22];
assign T_8372_oval = T_8371 ? iofPlusSwPinCtrl_22_oval : swPinCtrl_22_oval;
assign T_8372_oe = T_8371 ? iofPlusSwPinCtrl_22_oe : swPinCtrl_22_oe;
assign T_8372_ie = T_8371 ? iofPlusSwPinCtrl_22_ie : swPinCtrl_22_ie;
assign T_8372_pue = T_8371 ? iofPlusSwPinCtrl_22_pue : swPinCtrl_22_pue;
assign T_8372_ds = T_8371 ? iofPlusSwPinCtrl_22_ds : swPinCtrl_22_ds;
assign T_8378 = xorReg[22];
assign T_8379 = T_8372_oval ^ T_8378;
assign T_8380 = riseIpReg[22];
assign T_8381 = riseIeReg[22];
assign T_8382 = T_8380 & T_8381;
assign T_8383 = fallIpReg[22];
assign T_8384 = fallIeReg[22];
assign T_8385 = T_8383 & T_8384;
assign T_8386 = T_8382 | T_8385;
assign T_8387 = highIpReg[22];
assign T_8388 = highIeReg[22];
assign T_8389 = T_8387 & T_8388;
assign T_8390 = T_8386 | T_8389;
assign T_8391 = lowIpReg[22];
assign T_8392 = lowIeReg[22];
assign T_8393 = T_8391 & T_8392;
assign T_8394 = T_8390 | T_8393;
assign T_8395 = inSyncReg[22];
assign T_8397 = pueReg_io_q[23];
assign T_8398 = portReg[23];
assign T_8399 = oeReg_io_q[23];
assign T_8400 = dsReg[23];
assign T_8401 = ieReg_io_q[23];
assign GEN_339 = io_port_iof_0_23_o_valid ? io_port_iof_0_23_o_oval : swPinCtrl_23_oval;
assign GEN_340 = io_port_iof_0_23_o_valid ? io_port_iof_0_23_o_oe : swPinCtrl_23_oe;
assign GEN_341 = io_port_iof_0_23_o_valid ? io_port_iof_0_23_o_ie : swPinCtrl_23_ie;
assign GEN_342 = io_port_iof_1_23_o_valid ? io_port_iof_1_23_o_oval : swPinCtrl_23_oval;
assign GEN_343 = io_port_iof_1_23_o_valid ? io_port_iof_1_23_o_oe : swPinCtrl_23_oe;
assign GEN_344 = io_port_iof_1_23_o_valid ? io_port_iof_1_23_o_ie : swPinCtrl_23_ie;
assign T_8402 = iofSelReg[23];
assign T_8403_oval = T_8402 ? iof1Ctrl_23_oval : iof0Ctrl_23_oval;
assign T_8403_oe = T_8402 ? iof1Ctrl_23_oe : iof0Ctrl_23_oe;
assign T_8403_ie = T_8402 ? iof1Ctrl_23_ie : iof0Ctrl_23_ie;
assign T_8407 = iofEnReg_io_q[23];
assign T_8408_oval = T_8407 ? iofPlusSwPinCtrl_23_oval : swPinCtrl_23_oval;
assign T_8408_oe = T_8407 ? iofPlusSwPinCtrl_23_oe : swPinCtrl_23_oe;
assign T_8408_ie = T_8407 ? iofPlusSwPinCtrl_23_ie : swPinCtrl_23_ie;
assign T_8408_pue = T_8407 ? iofPlusSwPinCtrl_23_pue : swPinCtrl_23_pue;
assign T_8408_ds = T_8407 ? iofPlusSwPinCtrl_23_ds : swPinCtrl_23_ds;
assign T_8414 = xorReg[23];
assign T_8415 = T_8408_oval ^ T_8414;
assign T_8416 = riseIpReg[23];
assign T_8417 = riseIeReg[23];
assign T_8418 = T_8416 & T_8417;
assign T_8419 = fallIpReg[23];
assign T_8420 = fallIeReg[23];
assign T_8421 = T_8419 & T_8420;
assign T_8422 = T_8418 | T_8421;
assign T_8423 = highIpReg[23];
assign T_8424 = highIeReg[23];
assign T_8425 = T_8423 & T_8424;
assign T_8426 = T_8422 | T_8425;
assign T_8427 = lowIpReg[23];
assign T_8428 = lowIeReg[23];
assign T_8429 = T_8427 & T_8428;
assign T_8430 = T_8426 | T_8429;
assign T_8431 = inSyncReg[23];
assign T_8433 = pueReg_io_q[24];
assign T_8434 = portReg[24];
assign T_8435 = oeReg_io_q[24];
assign T_8436 = dsReg[24];
assign T_8437 = ieReg_io_q[24];
assign GEN_345 = io_port_iof_0_24_o_valid ? io_port_iof_0_24_o_oval : swPinCtrl_24_oval;
assign GEN_346 = io_port_iof_0_24_o_valid ? io_port_iof_0_24_o_oe : swPinCtrl_24_oe;
assign GEN_347 = io_port_iof_0_24_o_valid ? io_port_iof_0_24_o_ie : swPinCtrl_24_ie;
assign GEN_348 = io_port_iof_1_24_o_valid ? io_port_iof_1_24_o_oval : swPinCtrl_24_oval;
assign GEN_349 = io_port_iof_1_24_o_valid ? io_port_iof_1_24_o_oe : swPinCtrl_24_oe;
assign GEN_350 = io_port_iof_1_24_o_valid ? io_port_iof_1_24_o_ie : swPinCtrl_24_ie;
assign T_8438 = iofSelReg[24];
assign T_8439_oval = T_8438 ? iof1Ctrl_24_oval : iof0Ctrl_24_oval;
assign T_8439_oe = T_8438 ? iof1Ctrl_24_oe : iof0Ctrl_24_oe;
assign T_8439_ie = T_8438 ? iof1Ctrl_24_ie : iof0Ctrl_24_ie;
assign T_8443 = iofEnReg_io_q[24];
assign T_8444_oval = T_8443 ? iofPlusSwPinCtrl_24_oval : swPinCtrl_24_oval;
assign T_8444_oe = T_8443 ? iofPlusSwPinCtrl_24_oe : swPinCtrl_24_oe;
assign T_8444_ie = T_8443 ? iofPlusSwPinCtrl_24_ie : swPinCtrl_24_ie;
assign T_8444_pue = T_8443 ? iofPlusSwPinCtrl_24_pue : swPinCtrl_24_pue;
assign T_8444_ds = T_8443 ? iofPlusSwPinCtrl_24_ds : swPinCtrl_24_ds;
assign T_8450 = xorReg[24];
assign T_8451 = T_8444_oval ^ T_8450;
assign T_8452 = riseIpReg[24];
assign T_8453 = riseIeReg[24];
assign T_8454 = T_8452 & T_8453;
assign T_8455 = fallIpReg[24];
assign T_8456 = fallIeReg[24];
assign T_8457 = T_8455 & T_8456;
assign T_8458 = T_8454 | T_8457;
assign T_8459 = highIpReg[24];
assign T_8460 = highIeReg[24];
assign T_8461 = T_8459 & T_8460;
assign T_8462 = T_8458 | T_8461;
assign T_8463 = lowIpReg[24];
assign T_8464 = lowIeReg[24];
assign T_8465 = T_8463 & T_8464;
assign T_8466 = T_8462 | T_8465;
assign T_8467 = inSyncReg[24];
assign T_8469 = pueReg_io_q[25];
assign T_8470 = portReg[25];
assign T_8471 = oeReg_io_q[25];
assign T_8472 = dsReg[25];
assign T_8473 = ieReg_io_q[25];
assign GEN_351 = io_port_iof_0_25_o_valid ? io_port_iof_0_25_o_oval : swPinCtrl_25_oval;
assign GEN_352 = io_port_iof_0_25_o_valid ? io_port_iof_0_25_o_oe : swPinCtrl_25_oe;
assign GEN_353 = io_port_iof_0_25_o_valid ? io_port_iof_0_25_o_ie : swPinCtrl_25_ie;
assign GEN_354 = io_port_iof_1_25_o_valid ? io_port_iof_1_25_o_oval : swPinCtrl_25_oval;
assign GEN_355 = io_port_iof_1_25_o_valid ? io_port_iof_1_25_o_oe : swPinCtrl_25_oe;
assign GEN_356 = io_port_iof_1_25_o_valid ? io_port_iof_1_25_o_ie : swPinCtrl_25_ie;
assign T_8474 = iofSelReg[25];
assign T_8475_oval = T_8474 ? iof1Ctrl_25_oval : iof0Ctrl_25_oval;
assign T_8475_oe = T_8474 ? iof1Ctrl_25_oe : iof0Ctrl_25_oe;
assign T_8475_ie = T_8474 ? iof1Ctrl_25_ie : iof0Ctrl_25_ie;
assign T_8479 = iofEnReg_io_q[25];
assign T_8480_oval = T_8479 ? iofPlusSwPinCtrl_25_oval : swPinCtrl_25_oval;
assign T_8480_oe = T_8479 ? iofPlusSwPinCtrl_25_oe : swPinCtrl_25_oe;
assign T_8480_ie = T_8479 ? iofPlusSwPinCtrl_25_ie : swPinCtrl_25_ie;
assign T_8480_pue = T_8479 ? iofPlusSwPinCtrl_25_pue : swPinCtrl_25_pue;
assign T_8480_ds = T_8479 ? iofPlusSwPinCtrl_25_ds : swPinCtrl_25_ds;
assign T_8486 = xorReg[25];
assign T_8487 = T_8480_oval ^ T_8486;
assign T_8488 = riseIpReg[25];
assign T_8489 = riseIeReg[25];
assign T_8490 = T_8488 & T_8489;
assign T_8491 = fallIpReg[25];
assign T_8492 = fallIeReg[25];
assign T_8493 = T_8491 & T_8492;
assign T_8494 = T_8490 | T_8493;
assign T_8495 = highIpReg[25];
assign T_8496 = highIeReg[25];
assign T_8497 = T_8495 & T_8496;
assign T_8498 = T_8494 | T_8497;
assign T_8499 = lowIpReg[25];
assign T_8500 = lowIeReg[25];
assign T_8501 = T_8499 & T_8500;
assign T_8502 = T_8498 | T_8501;
assign T_8503 = inSyncReg[25];
assign T_8505 = pueReg_io_q[26];
assign T_8506 = portReg[26];
assign T_8507 = oeReg_io_q[26];
assign T_8508 = dsReg[26];
assign T_8509 = ieReg_io_q[26];
assign GEN_357 = io_port_iof_0_26_o_valid ? io_port_iof_0_26_o_oval : swPinCtrl_26_oval;
assign GEN_358 = io_port_iof_0_26_o_valid ? io_port_iof_0_26_o_oe : swPinCtrl_26_oe;
assign GEN_359 = io_port_iof_0_26_o_valid ? io_port_iof_0_26_o_ie : swPinCtrl_26_ie;
assign GEN_360 = io_port_iof_1_26_o_valid ? io_port_iof_1_26_o_oval : swPinCtrl_26_oval;
assign GEN_361 = io_port_iof_1_26_o_valid ? io_port_iof_1_26_o_oe : swPinCtrl_26_oe;
assign GEN_362 = io_port_iof_1_26_o_valid ? io_port_iof_1_26_o_ie : swPinCtrl_26_ie;
assign T_8510 = iofSelReg[26];
assign T_8511_oval = T_8510 ? iof1Ctrl_26_oval : iof0Ctrl_26_oval;
assign T_8511_oe = T_8510 ? iof1Ctrl_26_oe : iof0Ctrl_26_oe;
assign T_8511_ie = T_8510 ? iof1Ctrl_26_ie : iof0Ctrl_26_ie;
assign T_8515 = iofEnReg_io_q[26];
assign T_8516_oval = T_8515 ? iofPlusSwPinCtrl_26_oval : swPinCtrl_26_oval;
assign T_8516_oe = T_8515 ? iofPlusSwPinCtrl_26_oe : swPinCtrl_26_oe;
assign T_8516_ie = T_8515 ? iofPlusSwPinCtrl_26_ie : swPinCtrl_26_ie;
assign T_8516_pue = T_8515 ? iofPlusSwPinCtrl_26_pue : swPinCtrl_26_pue;
assign T_8516_ds = T_8515 ? iofPlusSwPinCtrl_26_ds : swPinCtrl_26_ds;
assign T_8522 = xorReg[26];
assign T_8523 = T_8516_oval ^ T_8522;
assign T_8524 = riseIpReg[26];
assign T_8525 = riseIeReg[26];
assign T_8526 = T_8524 & T_8525;
assign T_8527 = fallIpReg[26];
assign T_8528 = fallIeReg[26];
assign T_8529 = T_8527 & T_8528;
assign T_8530 = T_8526 | T_8529;
assign T_8531 = highIpReg[26];
assign T_8532 = highIeReg[26];
assign T_8533 = T_8531 & T_8532;
assign T_8534 = T_8530 | T_8533;
assign T_8535 = lowIpReg[26];
assign T_8536 = lowIeReg[26];
assign T_8537 = T_8535 & T_8536;
assign T_8538 = T_8534 | T_8537;
assign T_8539 = inSyncReg[26];
assign T_8541 = pueReg_io_q[27];
assign T_8542 = portReg[27];
assign T_8543 = oeReg_io_q[27];
assign T_8544 = dsReg[27];
assign T_8545 = ieReg_io_q[27];
assign GEN_363 = io_port_iof_0_27_o_valid ? io_port_iof_0_27_o_oval : swPinCtrl_27_oval;
assign GEN_364 = io_port_iof_0_27_o_valid ? io_port_iof_0_27_o_oe : swPinCtrl_27_oe;
assign GEN_365 = io_port_iof_0_27_o_valid ? io_port_iof_0_27_o_ie : swPinCtrl_27_ie;
assign GEN_366 = io_port_iof_1_27_o_valid ? io_port_iof_1_27_o_oval : swPinCtrl_27_oval;
assign GEN_367 = io_port_iof_1_27_o_valid ? io_port_iof_1_27_o_oe : swPinCtrl_27_oe;
assign GEN_368 = io_port_iof_1_27_o_valid ? io_port_iof_1_27_o_ie : swPinCtrl_27_ie;
assign T_8546 = iofSelReg[27];
assign T_8547_oval = T_8546 ? iof1Ctrl_27_oval : iof0Ctrl_27_oval;
assign T_8547_oe = T_8546 ? iof1Ctrl_27_oe : iof0Ctrl_27_oe;
assign T_8547_ie = T_8546 ? iof1Ctrl_27_ie : iof0Ctrl_27_ie;
assign T_8551 = iofEnReg_io_q[27];
assign T_8552_oval = T_8551 ? iofPlusSwPinCtrl_27_oval : swPinCtrl_27_oval;
assign T_8552_oe = T_8551 ? iofPlusSwPinCtrl_27_oe : swPinCtrl_27_oe;
assign T_8552_ie = T_8551 ? iofPlusSwPinCtrl_27_ie : swPinCtrl_27_ie;
assign T_8552_pue = T_8551 ? iofPlusSwPinCtrl_27_pue : swPinCtrl_27_pue;
assign T_8552_ds = T_8551 ? iofPlusSwPinCtrl_27_ds : swPinCtrl_27_ds;
assign T_8558 = xorReg[27];
assign T_8559 = T_8552_oval ^ T_8558;
assign T_8560 = riseIpReg[27];
assign T_8561 = riseIeReg[27];
assign T_8562 = T_8560 & T_8561;
assign T_8563 = fallIpReg[27];
assign T_8564 = fallIeReg[27];
assign T_8565 = T_8563 & T_8564;
assign T_8566 = T_8562 | T_8565;
assign T_8567 = highIpReg[27];
assign T_8568 = highIeReg[27];
assign T_8569 = T_8567 & T_8568;
assign T_8570 = T_8566 | T_8569;
assign T_8571 = lowIpReg[27];
assign T_8572 = lowIeReg[27];
assign T_8573 = T_8571 & T_8572;
assign T_8574 = T_8570 | T_8573;
assign T_8575 = inSyncReg[27];
assign T_8577 = pueReg_io_q[28];
assign T_8578 = portReg[28];
assign T_8579 = oeReg_io_q[28];
assign T_8580 = dsReg[28];
assign T_8581 = ieReg_io_q[28];
assign GEN_369 = io_port_iof_0_28_o_valid ? io_port_iof_0_28_o_oval : swPinCtrl_28_oval;
assign GEN_370 = io_port_iof_0_28_o_valid ? io_port_iof_0_28_o_oe : swPinCtrl_28_oe;
assign GEN_371 = io_port_iof_0_28_o_valid ? io_port_iof_0_28_o_ie : swPinCtrl_28_ie;
assign GEN_372 = io_port_iof_1_28_o_valid ? io_port_iof_1_28_o_oval : swPinCtrl_28_oval;
assign GEN_373 = io_port_iof_1_28_o_valid ? io_port_iof_1_28_o_oe : swPinCtrl_28_oe;
assign GEN_374 = io_port_iof_1_28_o_valid ? io_port_iof_1_28_o_ie : swPinCtrl_28_ie;
assign T_8582 = iofSelReg[28];
assign T_8583_oval = T_8582 ? iof1Ctrl_28_oval : iof0Ctrl_28_oval;
assign T_8583_oe = T_8582 ? iof1Ctrl_28_oe : iof0Ctrl_28_oe;
assign T_8583_ie = T_8582 ? iof1Ctrl_28_ie : iof0Ctrl_28_ie;
assign T_8587 = iofEnReg_io_q[28];
assign T_8588_oval = T_8587 ? iofPlusSwPinCtrl_28_oval : swPinCtrl_28_oval;
assign T_8588_oe = T_8587 ? iofPlusSwPinCtrl_28_oe : swPinCtrl_28_oe;
assign T_8588_ie = T_8587 ? iofPlusSwPinCtrl_28_ie : swPinCtrl_28_ie;
assign T_8588_pue = T_8587 ? iofPlusSwPinCtrl_28_pue : swPinCtrl_28_pue;
assign T_8588_ds = T_8587 ? iofPlusSwPinCtrl_28_ds : swPinCtrl_28_ds;
assign T_8594 = xorReg[28];
assign T_8595 = T_8588_oval ^ T_8594;
assign T_8596 = riseIpReg[28];
assign T_8597 = riseIeReg[28];
assign T_8598 = T_8596 & T_8597;
assign T_8599 = fallIpReg[28];
assign T_8600 = fallIeReg[28];
assign T_8601 = T_8599 & T_8600;
assign T_8602 = T_8598 | T_8601;
assign T_8603 = highIpReg[28];
assign T_8604 = highIeReg[28];
assign T_8605 = T_8603 & T_8604;
assign T_8606 = T_8602 | T_8605;
assign T_8607 = lowIpReg[28];
assign T_8608 = lowIeReg[28];
assign T_8609 = T_8607 & T_8608;
assign T_8610 = T_8606 | T_8609;
assign T_8611 = inSyncReg[28];
assign T_8613 = pueReg_io_q[29];
assign T_8614 = portReg[29];
assign T_8615 = oeReg_io_q[29];
assign T_8616 = dsReg[29];
assign T_8617 = ieReg_io_q[29];
assign GEN_375 = io_port_iof_0_29_o_valid ? io_port_iof_0_29_o_oval : swPinCtrl_29_oval;
assign GEN_376 = io_port_iof_0_29_o_valid ? io_port_iof_0_29_o_oe : swPinCtrl_29_oe;
assign GEN_377 = io_port_iof_0_29_o_valid ? io_port_iof_0_29_o_ie : swPinCtrl_29_ie;
assign GEN_378 = io_port_iof_1_29_o_valid ? io_port_iof_1_29_o_oval : swPinCtrl_29_oval;
assign GEN_379 = io_port_iof_1_29_o_valid ? io_port_iof_1_29_o_oe : swPinCtrl_29_oe;
assign GEN_380 = io_port_iof_1_29_o_valid ? io_port_iof_1_29_o_ie : swPinCtrl_29_ie;
assign T_8618 = iofSelReg[29];
assign T_8619_oval = T_8618 ? iof1Ctrl_29_oval : iof0Ctrl_29_oval;
assign T_8619_oe = T_8618 ? iof1Ctrl_29_oe : iof0Ctrl_29_oe;
assign T_8619_ie = T_8618 ? iof1Ctrl_29_ie : iof0Ctrl_29_ie;
assign T_8623 = iofEnReg_io_q[29];
assign T_8624_oval = T_8623 ? iofPlusSwPinCtrl_29_oval : swPinCtrl_29_oval;
assign T_8624_oe = T_8623 ? iofPlusSwPinCtrl_29_oe : swPinCtrl_29_oe;
assign T_8624_ie = T_8623 ? iofPlusSwPinCtrl_29_ie : swPinCtrl_29_ie;
assign T_8624_pue = T_8623 ? iofPlusSwPinCtrl_29_pue : swPinCtrl_29_pue;
assign T_8624_ds = T_8623 ? iofPlusSwPinCtrl_29_ds : swPinCtrl_29_ds;
assign T_8630 = xorReg[29];
assign T_8631 = T_8624_oval ^ T_8630;
assign T_8632 = riseIpReg[29];
assign T_8633 = riseIeReg[29];
assign T_8634 = T_8632 & T_8633;
assign T_8635 = fallIpReg[29];
assign T_8636 = fallIeReg[29];
assign T_8637 = T_8635 & T_8636;
assign T_8638 = T_8634 | T_8637;
assign T_8639 = highIpReg[29];
assign T_8640 = highIeReg[29];
assign T_8641 = T_8639 & T_8640;
assign T_8642 = T_8638 | T_8641;
assign T_8643 = lowIpReg[29];
assign T_8644 = lowIeReg[29];
assign T_8645 = T_8643 & T_8644;
assign T_8646 = T_8642 | T_8645;
assign T_8647 = inSyncReg[29];
assign T_8649 = pueReg_io_q[30];
assign T_8650 = portReg[30];
assign T_8651 = oeReg_io_q[30];
assign T_8652 = dsReg[30];
assign T_8653 = ieReg_io_q[30];
assign GEN_381 = io_port_iof_0_30_o_valid ? io_port_iof_0_30_o_oval : swPinCtrl_30_oval;
assign GEN_382 = io_port_iof_0_30_o_valid ? io_port_iof_0_30_o_oe : swPinCtrl_30_oe;
assign GEN_383 = io_port_iof_0_30_o_valid ? io_port_iof_0_30_o_ie : swPinCtrl_30_ie;
assign GEN_384 = io_port_iof_1_30_o_valid ? io_port_iof_1_30_o_oval : swPinCtrl_30_oval;
assign GEN_385 = io_port_iof_1_30_o_valid ? io_port_iof_1_30_o_oe : swPinCtrl_30_oe;
assign GEN_386 = io_port_iof_1_30_o_valid ? io_port_iof_1_30_o_ie : swPinCtrl_30_ie;
assign T_8654 = iofSelReg[30];
assign T_8655_oval = T_8654 ? iof1Ctrl_30_oval : iof0Ctrl_30_oval;
assign T_8655_oe = T_8654 ? iof1Ctrl_30_oe : iof0Ctrl_30_oe;
assign T_8655_ie = T_8654 ? iof1Ctrl_30_ie : iof0Ctrl_30_ie;
assign T_8659 = iofEnReg_io_q[30];
assign T_8660_oval = T_8659 ? iofPlusSwPinCtrl_30_oval : swPinCtrl_30_oval;
assign T_8660_oe = T_8659 ? iofPlusSwPinCtrl_30_oe : swPinCtrl_30_oe;
assign T_8660_ie = T_8659 ? iofPlusSwPinCtrl_30_ie : swPinCtrl_30_ie;
assign T_8660_pue = T_8659 ? iofPlusSwPinCtrl_30_pue : swPinCtrl_30_pue;
assign T_8660_ds = T_8659 ? iofPlusSwPinCtrl_30_ds : swPinCtrl_30_ds;
assign T_8666 = xorReg[30];
assign T_8667 = T_8660_oval ^ T_8666;
assign T_8668 = riseIpReg[30];
assign T_8669 = riseIeReg[30];
assign T_8670 = T_8668 & T_8669;
assign T_8671 = fallIpReg[30];
assign T_8672 = fallIeReg[30];
assign T_8673 = T_8671 & T_8672;
assign T_8674 = T_8670 | T_8673;
assign T_8675 = highIpReg[30];
assign T_8676 = highIeReg[30];
assign T_8677 = T_8675 & T_8676;
assign T_8678 = T_8674 | T_8677;
assign T_8679 = lowIpReg[30];
assign T_8680 = lowIeReg[30];
assign T_8681 = T_8679 & T_8680;
assign T_8682 = T_8678 | T_8681;
assign T_8683 = inSyncReg[30];
assign T_8685 = pueReg_io_q[31];
assign T_8686 = portReg[31];
assign T_8687 = oeReg_io_q[31];
assign T_8688 = dsReg[31];
assign T_8689 = ieReg_io_q[31];
assign GEN_387 = io_port_iof_0_31_o_valid ? io_port_iof_0_31_o_oval : swPinCtrl_31_oval;
assign GEN_388 = io_port_iof_0_31_o_valid ? io_port_iof_0_31_o_oe : swPinCtrl_31_oe;
assign GEN_389 = io_port_iof_0_31_o_valid ? io_port_iof_0_31_o_ie : swPinCtrl_31_ie;
assign GEN_390 = io_port_iof_1_31_o_valid ? io_port_iof_1_31_o_oval : swPinCtrl_31_oval;
assign GEN_391 = io_port_iof_1_31_o_valid ? io_port_iof_1_31_o_oe : swPinCtrl_31_oe;
assign GEN_392 = io_port_iof_1_31_o_valid ? io_port_iof_1_31_o_ie : swPinCtrl_31_ie;
assign T_8690 = iofSelReg[31];
assign T_8691_oval = T_8690 ? iof1Ctrl_31_oval : iof0Ctrl_31_oval;
assign T_8691_oe = T_8690 ? iof1Ctrl_31_oe : iof0Ctrl_31_oe;
assign T_8691_ie = T_8690 ? iof1Ctrl_31_ie : iof0Ctrl_31_ie;
assign T_8695 = iofEnReg_io_q[31];
assign T_8696_oval = T_8695 ? iofPlusSwPinCtrl_31_oval : swPinCtrl_31_oval;
assign T_8696_oe = T_8695 ? iofPlusSwPinCtrl_31_oe : swPinCtrl_31_oe;
assign T_8696_ie = T_8695 ? iofPlusSwPinCtrl_31_ie : swPinCtrl_31_ie;
assign T_8696_pue = T_8695 ? iofPlusSwPinCtrl_31_pue : swPinCtrl_31_pue;
assign T_8696_ds = T_8695 ? iofPlusSwPinCtrl_31_ds : swPinCtrl_31_ds;
assign T_8702 = xorReg[31];
assign T_8703 = T_8696_oval ^ T_8702;
assign T_8704 = riseIpReg[31];
assign T_8705 = riseIeReg[31];
assign T_8706 = T_8704 & T_8705;
assign T_8707 = fallIpReg[31];
assign T_8708 = fallIeReg[31];
assign T_8709 = T_8707 & T_8708;
assign T_8710 = T_8706 | T_8709;
assign T_8711 = highIpReg[31];
assign T_8712 = highIeReg[31];
assign T_8713 = T_8711 & T_8712;
assign T_8714 = T_8710 | T_8713;
assign T_8715 = lowIpReg[31];
assign T_8716 = lowIeReg[31];
assign T_8717 = T_8715 & T_8716;
assign T_8718 = T_8714 | T_8717;
assign T_8719 = inSyncReg[31];
always @(posedge clock or posedge reset)
if(reset) begin
T_3256 <= 32'b0;
T_3257 <= 32'b0;
inSyncReg <= 32'b0;
end
else begin
T_3256 <= inVal;
T_3257 <= T_3256;
inSyncReg <= T_3257;
end
always @(posedge clock or posedge reset)
if (reset) begin
portReg <= 32'h0;
end else begin
if (T_4329) begin
portReg <= T_3370_bits_data;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
dsReg <= 32'h0;
end else begin
if (T_3911) begin
dsReg <= T_3370_bits_data;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
valueReg <= 32'h0;
end else begin
valueReg <= inSyncReg;
end
always @(posedge clock or posedge reset)
if (reset) begin
highIeReg <= 32'h0;
end else begin
if (T_3951) begin
highIeReg <= T_3370_bits_data;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
lowIeReg <= 32'h0;
end else begin
if (T_4243) begin
lowIeReg <= T_3370_bits_data;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
riseIeReg <= 32'h0;
end else begin
if (T_4071) begin
riseIeReg <= T_3370_bits_data;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
fallIeReg <= 32'h0;
end else begin
if (T_4455) begin
fallIeReg <= T_3370_bits_data;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
highIpReg <= 32'h0;
end else begin
highIpReg <= T_4417;
end
always @(posedge clock or posedge reset)
if (reset) begin
lowIpReg <= 32'h0;
end else begin
lowIpReg <= T_4165;
end
always @(posedge clock or posedge reset)
if (reset) begin
riseIpReg <= 32'h0;
end else begin
riseIpReg <= T_4291;
end
always @(posedge clock or posedge reset)
if (reset) begin
fallIpReg <= 32'h0;
end else begin
fallIpReg <= T_4119;
end
always @(posedge clock or posedge reset)
if (reset) begin
iofSelReg <= 32'h0;
end else begin
if (T_4535) begin
iofSelReg <= T_3370_bits_data;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
xorReg <= 32'h0;
end else begin
if (T_4369) begin
xorReg <= T_3370_bits_data;
end
end
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Fri Jan 13 17:33:47 2017
// Host : KLight-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// D:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/bg_pole/bg_pole_sim_netlist.v
// Design : bg_pole
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "bg_pole,blk_mem_gen_v8_3_5,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "blk_mem_gen_v8_3_5,Vivado 2016.4" *)
(* NotValidForBitStream *)
module bg_pole
(clka,
wea,
addra,
dina,
douta);
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) input clka;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *) input [0:0]wea;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *) input [6:0]addra;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *) input [11:0]dina;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *) output [11:0]douta;
wire [6:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
wire NLW_U0_dbiterr_UNCONNECTED;
wire NLW_U0_rsta_busy_UNCONNECTED;
wire NLW_U0_rstb_busy_UNCONNECTED;
wire NLW_U0_s_axi_arready_UNCONNECTED;
wire NLW_U0_s_axi_awready_UNCONNECTED;
wire NLW_U0_s_axi_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_dbiterr_UNCONNECTED;
wire NLW_U0_s_axi_rlast_UNCONNECTED;
wire NLW_U0_s_axi_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_sbiterr_UNCONNECTED;
wire NLW_U0_s_axi_wready_UNCONNECTED;
wire NLW_U0_sbiterr_UNCONNECTED;
wire [11:0]NLW_U0_doutb_UNCONNECTED;
wire [6:0]NLW_U0_rdaddrecc_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_bid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
wire [6:0]NLW_U0_s_axi_rdaddrecc_UNCONNECTED;
wire [11:0]NLW_U0_s_axi_rdata_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_rid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
(* C_ADDRA_WIDTH = "7" *)
(* C_ADDRB_WIDTH = "7" *)
(* C_ALGORITHM = "1" *)
(* C_AXI_ID_WIDTH = "4" *)
(* C_AXI_SLAVE_TYPE = "0" *)
(* C_AXI_TYPE = "1" *)
(* C_BYTE_SIZE = "9" *)
(* C_COMMON_CLK = "0" *)
(* C_COUNT_18K_BRAM = "1" *)
(* C_COUNT_36K_BRAM = "0" *)
(* C_CTRL_ECC_ALGO = "NONE" *)
(* C_DEFAULT_DATA = "0" *)
(* C_DISABLE_WARN_BHV_COLL = "0" *)
(* C_DISABLE_WARN_BHV_RANGE = "0" *)
(* C_ELABORATION_DIR = "./" *)
(* C_ENABLE_32BIT_ADDRESS = "0" *)
(* C_EN_DEEPSLEEP_PIN = "0" *)
(* C_EN_ECC_PIPE = "0" *)
(* C_EN_RDADDRA_CHG = "0" *)
(* C_EN_RDADDRB_CHG = "0" *)
(* C_EN_SAFETY_CKT = "0" *)
(* C_EN_SHUTDOWN_PIN = "0" *)
(* C_EN_SLEEP_PIN = "0" *)
(* C_EST_POWER_SUMMARY = "Estimated Power for IP : 2.7064499999999998 mW" *)
(* C_FAMILY = "artix7" *)
(* C_HAS_AXI_ID = "0" *)
(* C_HAS_ENA = "0" *)
(* C_HAS_ENB = "0" *)
(* C_HAS_INJECTERR = "0" *)
(* C_HAS_MEM_OUTPUT_REGS_A = "1" *)
(* C_HAS_MEM_OUTPUT_REGS_B = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_A = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
(* C_HAS_REGCEA = "0" *)
(* C_HAS_REGCEB = "0" *)
(* C_HAS_RSTA = "0" *)
(* C_HAS_RSTB = "0" *)
(* C_HAS_SOFTECC_INPUT_REGS_A = "0" *)
(* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
(* C_INITA_VAL = "0" *)
(* C_INITB_VAL = "0" *)
(* C_INIT_FILE = "bg_pole.mem" *)
(* C_INIT_FILE_NAME = "bg_pole.mif" *)
(* C_INTERFACE_TYPE = "0" *)
(* C_LOAD_INIT_FILE = "1" *)
(* C_MEM_TYPE = "0" *)
(* C_MUX_PIPELINE_STAGES = "0" *)
(* C_PRIM_TYPE = "1" *)
(* C_READ_DEPTH_A = "104" *)
(* C_READ_DEPTH_B = "104" *)
(* C_READ_WIDTH_A = "12" *)
(* C_READ_WIDTH_B = "12" *)
(* C_RSTRAM_A = "0" *)
(* C_RSTRAM_B = "0" *)
(* C_RST_PRIORITY_A = "CE" *)
(* C_RST_PRIORITY_B = "CE" *)
(* C_SIM_COLLISION_CHECK = "ALL" *)
(* C_USE_BRAM_BLOCK = "0" *)
(* C_USE_BYTE_WEA = "0" *)
(* C_USE_BYTE_WEB = "0" *)
(* C_USE_DEFAULT_DATA = "0" *)
(* C_USE_ECC = "0" *)
(* C_USE_SOFTECC = "0" *)
(* C_USE_URAM = "0" *)
(* C_WEA_WIDTH = "1" *)
(* C_WEB_WIDTH = "1" *)
(* C_WRITE_DEPTH_A = "104" *)
(* C_WRITE_DEPTH_B = "104" *)
(* C_WRITE_MODE_A = "WRITE_FIRST" *)
(* C_WRITE_MODE_B = "WRITE_FIRST" *)
(* C_WRITE_WIDTH_A = "12" *)
(* C_WRITE_WIDTH_B = "12" *)
(* C_XDEVICEFAMILY = "artix7" *)
(* downgradeipidentifiedwarnings = "yes" *)
bg_pole_blk_mem_gen_v8_3_5 U0
(.addra(addra),
.addrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.clka(clka),
.clkb(1'b0),
.dbiterr(NLW_U0_dbiterr_UNCONNECTED),
.deepsleep(1'b0),
.dina(dina),
.dinb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.douta(douta),
.doutb(NLW_U0_doutb_UNCONNECTED[11:0]),
.eccpipece(1'b0),
.ena(1'b0),
.enb(1'b0),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.rdaddrecc(NLW_U0_rdaddrecc_UNCONNECTED[6:0]),
.regcea(1'b0),
.regceb(1'b0),
.rsta(1'b0),
.rsta_busy(NLW_U0_rsta_busy_UNCONNECTED),
.rstb(1'b0),
.rstb_busy(NLW_U0_rstb_busy_UNCONNECTED),
.s_aclk(1'b0),
.s_aresetn(1'b0),
.s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arburst({1'b0,1'b0}),
.s_axi_arid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
.s_axi_arsize({1'b0,1'b0,1'b0}),
.s_axi_arvalid(1'b0),
.s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awburst({1'b0,1'b0}),
.s_axi_awid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
.s_axi_awsize({1'b0,1'b0,1'b0}),
.s_axi_awvalid(1'b0),
.s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[3:0]),
.s_axi_bready(1'b0),
.s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
.s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
.s_axi_dbiterr(NLW_U0_s_axi_dbiterr_UNCONNECTED),
.s_axi_injectdbiterr(1'b0),
.s_axi_injectsbiterr(1'b0),
.s_axi_rdaddrecc(NLW_U0_s_axi_rdaddrecc_UNCONNECTED[6:0]),
.s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[11:0]),
.s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[3:0]),
.s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
.s_axi_rready(1'b0),
.s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
.s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
.s_axi_sbiterr(NLW_U0_s_axi_sbiterr_UNCONNECTED),
.s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wlast(1'b0),
.s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
.s_axi_wstrb(1'b0),
.s_axi_wvalid(1'b0),
.sbiterr(NLW_U0_sbiterr_UNCONNECTED),
.shutdown(1'b0),
.sleep(1'b0),
.wea(wea),
.web(1'b0));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *)
module bg_pole_blk_mem_gen_generic_cstr
(douta,
clka,
addra,
dina,
wea);
output [11:0]douta;
input clka;
input [6:0]addra;
input [11:0]dina;
input [0:0]wea;
wire [6:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
bg_pole_blk_mem_gen_prim_width \ramloop[0].ram.r
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module bg_pole_blk_mem_gen_prim_width
(douta,
clka,
addra,
dina,
wea);
output [11:0]douta;
input clka;
input [6:0]addra;
input [11:0]dina;
input [0:0]wea;
wire [6:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
bg_pole_blk_mem_gen_prim_wrapper_init \prim_init.ram
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module bg_pole_blk_mem_gen_prim_wrapper_init
(douta,
clka,
addra,
dina,
wea);
output [11:0]douta;
input clka;
input [6:0]addra;
input [11:0]dina;
input [0:0]wea;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_1 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_10 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_11 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_12 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_16 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_17 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_18 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_19 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_2 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_20 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_24 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_25 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_26 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_27 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_28 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_3 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_32 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_33 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_34 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_35 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_4 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_8 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_9 ;
wire [6:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB18E1 #(
.DOA_REG(1),
.DOB_REG(1),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000006050607040603010000000000000000030506070706010000000000),
.INIT_01(256'h0000020007060100040603010000000000000000060506070706010000000000),
.INIT_02(256'h0000000004060301070601000004000000000000060506070406030100000000),
.INIT_03(256'h0000000006050607040603010000000000000000030506070706010000000000),
.INIT_04(256'h0000000006050607070601000000000000000000050606060406030100040000),
.INIT_05(256'h0000000004060301070601000004000000000000060506070406030100000000),
.INIT_06(256'h0000000003050607070601000000000000000000060506070406030100040000),
.INIT_07(256'h0000000006050607070601000000000000000000050606060406030100040000),
.INIT_08(256'h0000000006050607040603010000000000000200070601000406030100000000),
.INIT_09(256'h0000000003050607070601000000000000000000060506070406030100040000),
.INIT_0A(256'h0000000005060606040603010004000000000000060506070406030100000000),
.INIT_0B(256'h0000000006050607040603010000000000000200070601000406030100000000),
.INIT_0C(256'h0000000006050607040603010004000000000000040603010706010000040000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(18'h00000),
.INIT_B(18'h00000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(18),
.READ_WIDTH_B(18),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(18'h00000),
.SRVAL_B(18'h00000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(18),
.WRITE_WIDTH_B(18))
\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram
(.ADDRARDADDR({1'b0,1'b0,addra,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ADDRBWRADDR({1'b0,1'b0,addra,1'b1,1'b0,1'b0,1'b0,1'b0}),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,dina[5:3],1'b0,1'b0,1'b0,1'b0,1'b0,dina[2:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,dina[11:9],1'b0,1'b0,1'b0,1'b0,1'b0,dina[8:6]}),
.DIPADIP({1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0}),
.DOADO({\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_0 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_1 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_2 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_3 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_4 ,douta[5:3],\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_8 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_9 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_10 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_11 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_12 ,douta[2:0]}),
.DOBDO({\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_16 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_17 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_18 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_19 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_20 ,douta[11:9],\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_24 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_25 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_26 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_27 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_28 ,douta[8:6]}),
.DOPADOP({\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_32 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_33 }),
.DOPBDOP({\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_34 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_35 }),
.ENARDEN(1'b1),
.ENBWREN(1'b1),
.REGCEAREGCE(1'b1),
.REGCEB(1'b1),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.WEA({wea,wea}),
.WEBWE({1'b0,1'b0,wea,wea}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_top" *)
module bg_pole_blk_mem_gen_top
(douta,
clka,
addra,
dina,
wea);
output [11:0]douta;
input clka;
input [6:0]addra;
input [11:0]dina;
input [0:0]wea;
wire [6:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
bg_pole_blk_mem_gen_generic_cstr \valid.cstr
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule
(* C_ADDRA_WIDTH = "7" *) (* C_ADDRB_WIDTH = "7" *) (* C_ALGORITHM = "1" *)
(* C_AXI_ID_WIDTH = "4" *) (* C_AXI_SLAVE_TYPE = "0" *) (* C_AXI_TYPE = "1" *)
(* C_BYTE_SIZE = "9" *) (* C_COMMON_CLK = "0" *) (* C_COUNT_18K_BRAM = "1" *)
(* C_COUNT_36K_BRAM = "0" *) (* C_CTRL_ECC_ALGO = "NONE" *) (* C_DEFAULT_DATA = "0" *)
(* C_DISABLE_WARN_BHV_COLL = "0" *) (* C_DISABLE_WARN_BHV_RANGE = "0" *) (* C_ELABORATION_DIR = "./" *)
(* C_ENABLE_32BIT_ADDRESS = "0" *) (* C_EN_DEEPSLEEP_PIN = "0" *) (* C_EN_ECC_PIPE = "0" *)
(* C_EN_RDADDRA_CHG = "0" *) (* C_EN_RDADDRB_CHG = "0" *) (* C_EN_SAFETY_CKT = "0" *)
(* C_EN_SHUTDOWN_PIN = "0" *) (* C_EN_SLEEP_PIN = "0" *) (* C_EST_POWER_SUMMARY = "Estimated Power for IP : 2.7064499999999998 mW" *)
(* C_FAMILY = "artix7" *) (* C_HAS_AXI_ID = "0" *) (* C_HAS_ENA = "0" *)
(* C_HAS_ENB = "0" *) (* C_HAS_INJECTERR = "0" *) (* C_HAS_MEM_OUTPUT_REGS_A = "1" *)
(* C_HAS_MEM_OUTPUT_REGS_B = "0" *) (* C_HAS_MUX_OUTPUT_REGS_A = "0" *) (* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
(* C_HAS_REGCEA = "0" *) (* C_HAS_REGCEB = "0" *) (* C_HAS_RSTA = "0" *)
(* C_HAS_RSTB = "0" *) (* C_HAS_SOFTECC_INPUT_REGS_A = "0" *) (* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
(* C_INITA_VAL = "0" *) (* C_INITB_VAL = "0" *) (* C_INIT_FILE = "bg_pole.mem" *)
(* C_INIT_FILE_NAME = "bg_pole.mif" *) (* C_INTERFACE_TYPE = "0" *) (* C_LOAD_INIT_FILE = "1" *)
(* C_MEM_TYPE = "0" *) (* C_MUX_PIPELINE_STAGES = "0" *) (* C_PRIM_TYPE = "1" *)
(* C_READ_DEPTH_A = "104" *) (* C_READ_DEPTH_B = "104" *) (* C_READ_WIDTH_A = "12" *)
(* C_READ_WIDTH_B = "12" *) (* C_RSTRAM_A = "0" *) (* C_RSTRAM_B = "0" *)
(* C_RST_PRIORITY_A = "CE" *) (* C_RST_PRIORITY_B = "CE" *) (* C_SIM_COLLISION_CHECK = "ALL" *)
(* C_USE_BRAM_BLOCK = "0" *) (* C_USE_BYTE_WEA = "0" *) (* C_USE_BYTE_WEB = "0" *)
(* C_USE_DEFAULT_DATA = "0" *) (* C_USE_ECC = "0" *) (* C_USE_SOFTECC = "0" *)
(* C_USE_URAM = "0" *) (* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *)
(* C_WRITE_DEPTH_A = "104" *) (* C_WRITE_DEPTH_B = "104" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *)
(* C_WRITE_MODE_B = "WRITE_FIRST" *) (* C_WRITE_WIDTH_A = "12" *) (* C_WRITE_WIDTH_B = "12" *)
(* C_XDEVICEFAMILY = "artix7" *) (* ORIG_REF_NAME = "blk_mem_gen_v8_3_5" *) (* downgradeipidentifiedwarnings = "yes" *)
module bg_pole_blk_mem_gen_v8_3_5
(clka,
rsta,
ena,
regcea,
wea,
addra,
dina,
douta,
clkb,
rstb,
enb,
regceb,
web,
addrb,
dinb,
doutb,
injectsbiterr,
injectdbiterr,
eccpipece,
sbiterr,
dbiterr,
rdaddrecc,
sleep,
deepsleep,
shutdown,
rsta_busy,
rstb_busy,
s_aclk,
s_aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
s_axi_injectsbiterr,
s_axi_injectdbiterr,
s_axi_sbiterr,
s_axi_dbiterr,
s_axi_rdaddrecc);
input clka;
input rsta;
input ena;
input regcea;
input [0:0]wea;
input [6:0]addra;
input [11:0]dina;
output [11:0]douta;
input clkb;
input rstb;
input enb;
input regceb;
input [0:0]web;
input [6:0]addrb;
input [11:0]dinb;
output [11:0]doutb;
input injectsbiterr;
input injectdbiterr;
input eccpipece;
output sbiterr;
output dbiterr;
output [6:0]rdaddrecc;
input sleep;
input deepsleep;
input shutdown;
output rsta_busy;
output rstb_busy;
input s_aclk;
input s_aresetn;
input [3:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input s_axi_awvalid;
output s_axi_awready;
input [11:0]s_axi_wdata;
input [0:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [3:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [3:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input s_axi_arvalid;
output s_axi_arready;
output [3:0]s_axi_rid;
output [11:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
input s_axi_injectsbiterr;
input s_axi_injectdbiterr;
output s_axi_sbiterr;
output s_axi_dbiterr;
output [6:0]s_axi_rdaddrecc;
wire \<const0> ;
wire [6:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
assign dbiterr = \<const0> ;
assign doutb[11] = \<const0> ;
assign doutb[10] = \<const0> ;
assign doutb[9] = \<const0> ;
assign doutb[8] = \<const0> ;
assign doutb[7] = \<const0> ;
assign doutb[6] = \<const0> ;
assign doutb[5] = \<const0> ;
assign doutb[4] = \<const0> ;
assign doutb[3] = \<const0> ;
assign doutb[2] = \<const0> ;
assign doutb[1] = \<const0> ;
assign doutb[0] = \<const0> ;
assign rdaddrecc[6] = \<const0> ;
assign rdaddrecc[5] = \<const0> ;
assign rdaddrecc[4] = \<const0> ;
assign rdaddrecc[3] = \<const0> ;
assign rdaddrecc[2] = \<const0> ;
assign rdaddrecc[1] = \<const0> ;
assign rdaddrecc[0] = \<const0> ;
assign rsta_busy = \<const0> ;
assign rstb_busy = \<const0> ;
assign s_axi_arready = \<const0> ;
assign s_axi_awready = \<const0> ;
assign s_axi_bid[3] = \<const0> ;
assign s_axi_bid[2] = \<const0> ;
assign s_axi_bid[1] = \<const0> ;
assign s_axi_bid[0] = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_bvalid = \<const0> ;
assign s_axi_dbiterr = \<const0> ;
assign s_axi_rdaddrecc[6] = \<const0> ;
assign s_axi_rdaddrecc[5] = \<const0> ;
assign s_axi_rdaddrecc[4] = \<const0> ;
assign s_axi_rdaddrecc[3] = \<const0> ;
assign s_axi_rdaddrecc[2] = \<const0> ;
assign s_axi_rdaddrecc[1] = \<const0> ;
assign s_axi_rdaddrecc[0] = \<const0> ;
assign s_axi_rdata[11] = \<const0> ;
assign s_axi_rdata[10] = \<const0> ;
assign s_axi_rdata[9] = \<const0> ;
assign s_axi_rdata[8] = \<const0> ;
assign s_axi_rdata[7] = \<const0> ;
assign s_axi_rdata[6] = \<const0> ;
assign s_axi_rdata[5] = \<const0> ;
assign s_axi_rdata[4] = \<const0> ;
assign s_axi_rdata[3] = \<const0> ;
assign s_axi_rdata[2] = \<const0> ;
assign s_axi_rdata[1] = \<const0> ;
assign s_axi_rdata[0] = \<const0> ;
assign s_axi_rid[3] = \<const0> ;
assign s_axi_rid[2] = \<const0> ;
assign s_axi_rid[1] = \<const0> ;
assign s_axi_rid[0] = \<const0> ;
assign s_axi_rlast = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
assign s_axi_rvalid = \<const0> ;
assign s_axi_sbiterr = \<const0> ;
assign s_axi_wready = \<const0> ;
assign sbiterr = \<const0> ;
GND GND
(.G(\<const0> ));
bg_pole_blk_mem_gen_v8_3_5_synth inst_blk_mem_gen
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_3_5_synth" *)
module bg_pole_blk_mem_gen_v8_3_5_synth
(douta,
clka,
addra,
dina,
wea);
output [11:0]douta;
input clka;
input [6:0]addra;
input [11:0]dina;
input [0:0]wea;
wire [6:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
bg_pole_blk_mem_gen_top \gnbram.gnativebmg.native_blk_mem_gen
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:26:17 03/17/2015
// Design Name:
// Module Name: alt_ctl
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module alt_ctl(op,func,aluc
);
input [5:0] op,func;
output reg [4:0] aluc;
always @*
begin
case(op)
6'b000000 : begin //R type
case(func)//Same op, distinguished by function code. 17 instructions
6'b100000 : aluc = 0; //add
6'b100001 : aluc = 1; //addu
6'b100010 : aluc = 2; //sub
6'b100011 : aluc = 3; //subu
6'b100100 : aluc = 4; //and
6'b100101 : aluc = 5; //or
6'b100110 : aluc = 6; //xor
6'b100111 : aluc = 7; //nor
6'b101010 : aluc = 8; //slt
6'b101011 : aluc = 9; //sltu
6'b000000 : aluc = 10; //sll
6'b000010 : aluc = 11; //srl
6'b000011 : aluc = 12; //sra
6'b000100 : aluc = 10; //sllv
6'b000110 : aluc = 11; //srlv
6'b000111 : aluc = 12; //srav
6'b000001 : aluc = 13; //slc?
6'b000010 : aluc = 13; //slcv?
default : aluc = 0;
endcase
end // I type
6'b001000 : aluc = 0; //addi
6'b001001 : aluc = 1; //addiu
6'b001100 : aluc = 4; //andi
6'b001101 : aluc = 5; //ori
6'b001110 : aluc = 6; //xori
6'b001010 : aluc = 8; //slti
6'b001011 : aluc = 9; //sltiu
6'b001111 : aluc = 14;//lui
default : aluc = 0;
endcase
end
endmodule
|
/*
* Copyright (C) 2016 Harmon Instruments, LLC
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/
*
* One wire UART least significant bit and byte first
*
* Set baud rate: write with a=0, wd = cpb | 0x80000000
* where cpb = (16 * clock) / baud
*
* Send 4 bytes: wd = data, a = 3
* Send 3 bytes: wd[23:0] = data, a = 2
* Send 2 bytes: wd[16:0] = data, a = 1
* Send 1 byte : wd[ 7:0] = data, a = 0, wd[31:30] must be 0
* Send break : wd = 0x40000000, a = 0
*
*/
`timescale 1ns / 1ps
module uart_1wire
(
input c, // clock
input w, // write enable
input [1:0] a, // address
input [31:0] wd, // write data
output reg [31:0] rd = 0, // read data
inout uart // IO pin
);
reg [3:0] rx_state = 0;
reg [6:0] rx_cur_time = 0;
reg [6:0] rx_next_event = 0;
reg [6:0] cpb = 100; // clocks per bit
reg ireg = 1;
reg oe = 0;
reg od = 0;
reg [5:0] tx_bits = 0; // tx bits remaining
reg [6:0] tx_cur_time = 0;
reg [6:0] tx_next_event = 0;
reg [38:0] tx_sr = 39'h7FFFFFFFF;
assign uart = oe ? od : 1'bz;
always @ (posedge c)
begin
// receive
ireg <= uart;
if(rx_state == 0)
begin
rx_cur_time <= 1'b0;
if (!ireg)
begin
rx_state <= 1'b1;
rx_next_event <= cpb[6:1];
end
end
else
begin
rx_cur_time <= rx_cur_time + 1'b1;
if(rx_next_event == rx_cur_time)
begin
rx_next_event <= rx_next_event + cpb;
rx_state <= rx_state == 10 ? 1'b0 : rx_state + 1'b1;
if((rx_state > 1) && (rx_state < 10))
rd <= {ireg, rd[31:1]};
end
end
// transmit
od <= tx_sr[0];
oe <= tx_bits != 0;
if(w)
begin
if((a == 0) && wd[31])
cpb <= wd[6:0];
oe <= 1'b1;
tx_bits <= 6'd40;
tx_cur_time <= 1'b0;
tx_next_event <= cpb;
tx_sr[38:30] <= a > 2 ? {wd[31:24], 1'b0} : 9'h1FF;
tx_sr[29:20] <= a > 1 ? {1'b1, wd[23:16], 1'b0} : 10'h3FF;
tx_sr[19:10] <= a > 0 ? {1'b1, wd[15: 8], 1'b0} : 10'h3FF;
tx_sr[ 9: 0] <= (a > 0) || (wd[31:30] == 0) ? {1'b1, wd[ 7: 0], 1'b0} :
wd[30] == 1 ? 10'h000 : 10'h3FF;
end
else
begin
tx_cur_time <= tx_cur_time + 1'b1;
if(tx_next_event == tx_cur_time)
begin
tx_next_event <= tx_next_event + cpb;
tx_sr <= {1'b1, tx_sr[38:1]};
tx_bits <= tx_bits == 0 ? 1'b0 : tx_bits - 1'b1;
end
end
end
endmodule
`ifdef SIM
module tb (input c);
reg w = 0;
reg [2:0] a = 0;
reg [31:0] wd = 0;
wand uart = 1;
wire [31:0] rd0, rd1;
uart_1wire uart0 (.c(c), .w(w & ~a[2]), .a(a[1:0]), .wd(wd), .rd(rd0), .uart(uart));
uart_1wire uart1 (.c(c), .w(w & a[2]), .a(a[1:0]), .wd(wd), .rd(rd1), .uart(uart));
initial
begin
$dumpfile("dump.vcd");
$dumpvars(0);
end
endmodule
`endif
|
///////////////////////////////////////////////////////////////////////////////
//
// File name: axi_protocol_converter_v2_1_b2s_b_channel.v
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_b2s_b_channel #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of ID signals.
// Range: >= 1.
parameter integer C_ID_WIDTH = 4
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire clk,
input wire reset,
// AXI signals
output wire [C_ID_WIDTH-1:0] s_bid,
output wire [1:0] s_bresp,
output wire s_bvalid,
input wire s_bready,
input wire [1:0] m_bresp,
input wire m_bvalid,
output wire m_bready,
// Signals to/from the axi_protocol_converter_v2_1_b2s_aw_channel modules
input wire b_push,
input wire [C_ID_WIDTH-1:0] b_awid,
input wire [7:0] b_awlen,
input wire b_resp_rdy,
output wire b_full
);
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
// AXI protocol responses:
localparam [1:0] LP_RESP_OKAY = 2'b00;
localparam [1:0] LP_RESP_EXOKAY = 2'b01;
localparam [1:0] LP_RESP_SLVERROR = 2'b10;
localparam [1:0] LP_RESP_DECERR = 2'b11;
// FIFO settings
localparam P_WIDTH = C_ID_WIDTH + 8;
localparam P_DEPTH = 4;
localparam P_AWIDTH = 2;
localparam P_RWIDTH = 2;
localparam P_RDEPTH = 4;
localparam P_RAWIDTH = 2;
////////////////////////////////////////////////////////////////////////////////
// Wire and register declarations
////////////////////////////////////////////////////////////////////////////////
reg bvalid_i;
wire [C_ID_WIDTH-1:0] bid_i;
wire shandshake;
reg shandshake_r;
wire mhandshake;
reg mhandshake_r;
wire b_empty;
wire bresp_full;
wire bresp_empty;
wire [7:0] b_awlen_i;
reg [7:0] bresp_cnt;
reg [1:0] s_bresp_acc;
wire [1:0] s_bresp_acc_r;
reg [1:0] s_bresp_i;
wire need_to_update_bresp;
wire bresp_push;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// assign AXI outputs
assign s_bid = bid_i;
assign s_bresp = s_bresp_acc_r;
assign s_bvalid = bvalid_i;
assign shandshake = s_bvalid & s_bready;
assign mhandshake = m_bvalid & m_bready;
always @(posedge clk) begin
if (reset | shandshake) begin
bvalid_i <= 1'b0;
end else if (~b_empty & ~shandshake_r & ~bresp_empty) begin
bvalid_i <= 1'b1;
end
end
always @(posedge clk) begin
shandshake_r <= shandshake;
mhandshake_r <= mhandshake;
end
axi_protocol_converter_v2_1_b2s_simple_fifo #(
.C_WIDTH (P_WIDTH),
.C_AWIDTH (P_AWIDTH),
.C_DEPTH (P_DEPTH)
)
bid_fifo_0
(
.clk ( clk ) ,
.rst ( reset ) ,
.wr_en ( b_push ) ,
.rd_en ( shandshake_r ) ,
.din ( {b_awid, b_awlen} ) ,
.dout ( {bid_i, b_awlen_i}) ,
.a_full ( ) ,
.full ( b_full ) ,
.a_empty ( ) ,
.empty ( b_empty )
);
assign m_bready = ~mhandshake_r & bresp_empty;
/////////////////////////////////////////////////////////////////////////////
// Update if more critical.
assign need_to_update_bresp = ( m_bresp > s_bresp_acc );
// Select accumultated or direct depending on setting.
always @( * ) begin
if ( need_to_update_bresp ) begin
s_bresp_i = m_bresp;
end else begin
s_bresp_i = s_bresp_acc;
end
end
/////////////////////////////////////////////////////////////////////////////
// Accumulate MI-side BRESP.
always @ (posedge clk) begin
if (reset | bresp_push ) begin
s_bresp_acc <= LP_RESP_OKAY;
end else if ( mhandshake ) begin
s_bresp_acc <= s_bresp_i;
end
end
assign bresp_push = ( mhandshake_r ) & (bresp_cnt == b_awlen_i) & ~b_empty;
always @ (posedge clk) begin
if (reset | bresp_push ) begin
bresp_cnt <= 8'h00;
end else if ( mhandshake_r ) begin
bresp_cnt <= bresp_cnt + 1'b1;
end
end
axi_protocol_converter_v2_1_b2s_simple_fifo #(
.C_WIDTH (P_RWIDTH),
.C_AWIDTH (P_RAWIDTH),
.C_DEPTH (P_RDEPTH)
)
bresp_fifo_0
(
.clk ( clk ) ,
.rst ( reset ) ,
.wr_en ( bresp_push ) ,
.rd_en ( shandshake_r ) ,
.din ( s_bresp_acc ) ,
.dout ( s_bresp_acc_r) ,
.a_full ( ) ,
.full ( bresp_full ) ,
.a_empty ( ) ,
.empty ( bresp_empty )
);
endmodule
`default_nettype wire
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_tx_req # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
input pcie_user_clk,
input pcie_user_rst_n,
input [2:0] pcie_max_payload_size,
output pcie_tx_cmd_rd_en,
input [33:0] pcie_tx_cmd_rd_data,
input pcie_tx_cmd_empty_n,
output pcie_tx_fifo_free_en,
output [9:4] pcie_tx_fifo_free_len,
input pcie_tx_fifo_empty_n,
output tx_dma_mwr_req,
output [7:0] tx_dma_mwr_tag,
output [11:2] tx_dma_mwr_len,
output [C_PCIE_ADDR_WIDTH-1:2] tx_dma_mwr_addr,
input tx_dma_mwr_req_ack,
input tx_dma_mwr_data_last,
output dma_tx_done_wr_en,
output [20:0] dma_tx_done_wr_data,
input dma_tx_done_wr_rdy_n
);
localparam S_IDLE = 10'b0000000001;
localparam S_PCIE_TX_CMD_0 = 10'b0000000010;
localparam S_PCIE_TX_CMD_1 = 10'b0000000100;
localparam S_PCIE_CHK_FIFO = 10'b0000001000;
localparam S_PCIE_MWR_REQ = 10'b0000010000;
localparam S_PCIE_MWR_ACK = 10'b0000100000;
localparam S_PCIE_MWR_DONE = 10'b0001000000;
localparam S_PCIE_MWR_NEXT = 10'b0010000000;
localparam S_PCIE_DMA_DONE_WR_WAIT = 10'b0100000000;
localparam S_PCIE_DMA_DONE_WR = 10'b1000000000;
reg [9:0] cur_state;
reg [9:0] next_state;
reg [2:0] r_pcie_max_payload_size;
reg r_pcie_tx_cmd_rd_en;
reg r_pcie_tx_fifo_free_en;
reg r_tx_dma_mwr_req;
reg r_dma_cmd_type;
reg r_dma_done_check;
reg [6:0] r_hcmd_slot_tag;
reg [12:2] r_pcie_tx_len;
reg [12:2] r_pcie_orig_len;
reg [9:2] r_pcie_tx_cur_len;
reg [C_PCIE_ADDR_WIDTH-1:2] r_pcie_addr;
reg r_dma_tx_done_wr_en;
assign pcie_tx_cmd_rd_en = r_pcie_tx_cmd_rd_en;
assign pcie_tx_fifo_free_en = r_pcie_tx_fifo_free_en;
assign pcie_tx_fifo_free_len = r_pcie_tx_cur_len[9:4];
assign tx_dma_mwr_req = r_tx_dma_mwr_req;
assign tx_dma_mwr_tag = 8'b0;
assign tx_dma_mwr_len = {2'b0, r_pcie_tx_cur_len};
assign tx_dma_mwr_addr = r_pcie_addr;
assign dma_tx_done_wr_en = r_dma_tx_done_wr_en;
assign dma_tx_done_wr_data = {r_dma_cmd_type, r_dma_done_check, 1'b1, r_hcmd_slot_tag, r_pcie_orig_len};
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0)
cur_state <= S_IDLE;
else
cur_state <= next_state;
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
if(pcie_tx_cmd_empty_n == 1)
next_state <= S_PCIE_TX_CMD_0;
else
next_state <= S_IDLE;
end
S_PCIE_TX_CMD_0: begin
next_state <= S_PCIE_TX_CMD_1;
end
S_PCIE_TX_CMD_1: begin
next_state <= S_PCIE_CHK_FIFO;
end
S_PCIE_CHK_FIFO: begin
if(pcie_tx_fifo_empty_n == 1)
next_state <= S_PCIE_MWR_REQ;
else
next_state <= S_PCIE_CHK_FIFO;
end
S_PCIE_MWR_REQ: begin
next_state <= S_PCIE_MWR_ACK;
end
S_PCIE_MWR_ACK: begin
if(tx_dma_mwr_req_ack == 1)
next_state <= S_PCIE_MWR_DONE;
else
next_state <= S_PCIE_MWR_ACK;
end
S_PCIE_MWR_DONE: begin
next_state <= S_PCIE_MWR_NEXT;
end
S_PCIE_MWR_NEXT: begin
if(r_pcie_tx_len == 0)
next_state <= S_PCIE_DMA_DONE_WR_WAIT;
else
next_state <= S_PCIE_CHK_FIFO;
end
S_PCIE_DMA_DONE_WR_WAIT: begin
if(dma_tx_done_wr_rdy_n == 1)
next_state <= S_PCIE_DMA_DONE_WR_WAIT;
else
next_state <= S_PCIE_DMA_DONE_WR;
end
S_PCIE_DMA_DONE_WR: begin
next_state <= S_IDLE;
end
default: begin
next_state <= S_IDLE;
end
endcase
end
always @ (posedge pcie_user_clk)
begin
r_pcie_max_payload_size <= pcie_max_payload_size;
end
always @ (posedge pcie_user_clk)
begin
case(cur_state)
S_IDLE: begin
end
S_PCIE_TX_CMD_0: begin
r_dma_cmd_type <= pcie_tx_cmd_rd_data[19];
r_dma_done_check <= pcie_tx_cmd_rd_data[18];
r_hcmd_slot_tag <= pcie_tx_cmd_rd_data[17:11];
r_pcie_tx_len <= {pcie_tx_cmd_rd_data[10:2], 2'b0};
end
S_PCIE_TX_CMD_1: begin
r_pcie_orig_len <= r_pcie_tx_len;
case(r_pcie_max_payload_size)
3'b010: begin
if(r_pcie_tx_len[8:7] == 0 && r_pcie_tx_len[6:2] == 0)
r_pcie_tx_cur_len[9:7] <= 3'b100;
else
r_pcie_tx_cur_len[9:7] <= {1'b0, r_pcie_tx_len[8:7]};
end
3'b001: begin
if(r_pcie_tx_len[7] == 0 && r_pcie_tx_len[6:2] == 0)
r_pcie_tx_cur_len[9:7] <= 3'b010;
else
r_pcie_tx_cur_len[9:7] <= {2'b0, r_pcie_tx_len[7]};
end
default: begin
if(r_pcie_tx_len[6:2] == 0)
r_pcie_tx_cur_len[9:7] <= 3'b001;
else
r_pcie_tx_cur_len[9:7] <= 3'b000;
end
endcase
r_pcie_tx_cur_len[6:2] <= r_pcie_tx_len[6:2];
r_pcie_addr <= {pcie_tx_cmd_rd_data[33:2], 2'b0};
end
S_PCIE_CHK_FIFO: begin
end
S_PCIE_MWR_REQ: begin
end
S_PCIE_MWR_ACK: begin
end
S_PCIE_MWR_DONE: begin
r_pcie_addr <= r_pcie_addr + r_pcie_tx_cur_len;
r_pcie_tx_len <= r_pcie_tx_len - r_pcie_tx_cur_len;
case(r_pcie_max_payload_size)
3'b010: r_pcie_tx_cur_len <= 8'h80;
3'b001: r_pcie_tx_cur_len <= 8'h40;
default: r_pcie_tx_cur_len <= 8'h20;
endcase
end
S_PCIE_MWR_NEXT: begin
end
S_PCIE_DMA_DONE_WR_WAIT: begin
end
S_PCIE_DMA_DONE_WR: begin
end
default: begin
end
endcase
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
r_pcie_tx_cmd_rd_en <= 0;
r_pcie_tx_fifo_free_en <= 0;
r_tx_dma_mwr_req <= 0;
r_dma_tx_done_wr_en <= 0;
end
S_PCIE_TX_CMD_0: begin
r_pcie_tx_cmd_rd_en <= 1;
r_pcie_tx_fifo_free_en <= 0;
r_tx_dma_mwr_req <= 0;
r_dma_tx_done_wr_en <= 0;
end
S_PCIE_TX_CMD_1: begin
r_pcie_tx_cmd_rd_en <= 1;
r_pcie_tx_fifo_free_en <= 0;
r_tx_dma_mwr_req <= 0;
r_dma_tx_done_wr_en <= 0;
end
S_PCIE_CHK_FIFO: begin
r_pcie_tx_cmd_rd_en <= 0;
r_pcie_tx_fifo_free_en <= 0;
r_tx_dma_mwr_req <= 0;
r_dma_tx_done_wr_en <= 0;
end
S_PCIE_MWR_REQ: begin
r_pcie_tx_cmd_rd_en <= 0;
r_pcie_tx_fifo_free_en <= 1;
r_tx_dma_mwr_req <= 1;
r_dma_tx_done_wr_en <= 0;
end
S_PCIE_MWR_ACK: begin
r_pcie_tx_cmd_rd_en <= 0;
r_pcie_tx_fifo_free_en <= 0;
r_tx_dma_mwr_req <= 0;
r_dma_tx_done_wr_en <= 0;
end
S_PCIE_MWR_DONE: begin
r_pcie_tx_cmd_rd_en <= 0;
r_pcie_tx_fifo_free_en <= 0;
r_tx_dma_mwr_req <= 0;
r_dma_tx_done_wr_en <= 0;
end
S_PCIE_MWR_NEXT: begin
r_pcie_tx_cmd_rd_en <= 0;
r_pcie_tx_fifo_free_en <= 0;
r_tx_dma_mwr_req <= 0;
r_dma_tx_done_wr_en <= 0;
end
S_PCIE_DMA_DONE_WR_WAIT: begin
r_pcie_tx_cmd_rd_en <= 0;
r_pcie_tx_fifo_free_en <= 0;
r_tx_dma_mwr_req <= 0;
r_dma_tx_done_wr_en <= 0;
end
S_PCIE_DMA_DONE_WR: begin
r_pcie_tx_cmd_rd_en <= 0;
r_pcie_tx_fifo_free_en <= 0;
r_tx_dma_mwr_req <= 0;
r_dma_tx_done_wr_en <= 1;
end
default: begin
r_pcie_tx_cmd_rd_en <= 0;
r_pcie_tx_fifo_free_en <= 0;
r_tx_dma_mwr_req <= 0;
r_dma_tx_done_wr_en <= 0;
end
endcase
end
endmodule
|
// Copyright (c) 2000-2009 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 24080 $
// $Date: 2011-05-18 19:32:52 +0000 (Wed, 18 May 2011) $
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
module RWire(WGET, WHAS, WVAL, WSET);
parameter width = 1;
input [width - 1 : 0] WVAL;
input WSET;
output [width - 1 : 0] WGET;
output WHAS;
assign WGET = WVAL;
assign WHAS = WSET;
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// A simple chipscope based monitor
`timescale 1ns/100ps
module axi_fft_mon (
clk,
// adc interface
adc_valid,
adc_data,
adc_last,
adc_ready,
// window interface
win_valid,
win_data,
win_last,
win_ready,
// fft magnitude interface
fft_mag_valid,
fft_mag_data,
fft_mag_last,
// monitor outputs for chipscope
fft_mon_sync,
fft_mon_data);
// parameter to control the memory size
parameter PCORE_FFT_MON_ADDR_WIDTH = 0;
localparam AW = PCORE_FFT_MON_ADDR_WIDTH - 1;
input clk;
// adc interface
input adc_valid;
input [15:0] adc_data;
input adc_last;
input adc_ready;
// window interface
input win_valid;
input [15:0] win_data;
input win_last;
input win_ready;
// fft magnitude interface
input fft_mag_valid;
input [31:0] fft_mag_data;
input fft_mag_last;
// monitor outputs for chipscope
output fft_mon_sync;
output [63:0] fft_mon_data;
// internal registers
reg adc_clrn = 'd0;
reg adc_wr = 'd0;
reg [AW:0] adc_waddr = 'd0;
reg [15:0] adc_wdata = 'd0;
reg win_clrn = 'd0;
reg win_wr = 'd0;
reg [AW:0] win_waddr = 'd0;
reg [15:0] win_wdata = 'd0;
reg fft_mag_clrn = 'd0;
reg fft_mag_wr = 'd0;
reg [AW:0] fft_mag_waddr = 'd0;
reg [31:0] fft_mag_wdata = 'd0;
reg [AW:0] fft_mon_raddr = 'd0;
reg fft_mon_sync = 'd0;
reg [63:0] fft_mon_data = 'd0;
// internal signals
wire [63:0] fft_mon_rdata_s;
// samples
always @(posedge clk) begin
if (adc_last == 1'b1) begin
adc_clrn <= 1'b0;
end else if ((adc_valid == 1'b1) && (adc_ready == 1'b1)) begin
adc_clrn <= 1'b1;
end
adc_wr <= adc_valid & adc_ready;
if (adc_wr == 1'b1) begin
adc_waddr <= adc_waddr + 1'b1;
end else if (adc_clrn == 1'b0) begin
adc_waddr <= 'd0;
end
adc_wdata <= adc_data;
end
// windowing controls. again, clear is used to reset the write address
always @(posedge clk) begin
if (win_last == 1'b1) begin
win_clrn <= 1'b0;
end else if ((win_valid == 1'b1) && (win_ready == 1'b1)) begin
win_clrn <= 1'b1;
end
win_wr <= win_valid & win_ready;
if (win_wr == 1'b1) begin
win_waddr <= win_waddr + 1'b1;
end else if (win_clrn == 1'b0) begin
win_waddr <= 'd0;
end
win_wdata <= win_data;
end
// FFT data. once again, clear is used to reset the write address
always @(posedge clk) begin
if (fft_mag_last == 1'b1) begin
fft_mag_clrn <= 1'b0;
end else if (fft_mag_valid == 1'b1) begin
fft_mag_clrn <= 1'b1;
end
fft_mag_wr <= fft_mag_valid;
if (fft_mag_wr == 1'b1) begin
fft_mag_waddr <= fft_mag_waddr + 1'b1;
end else if (fft_mag_clrn == 1'b0) begin
fft_mag_waddr <= 'd0;
end
fft_mag_wdata <= fft_mag_data;
end
// monitor read interface, the resets of write addresses above guarantees that
// sync is always at address 0 (0x1 here to make it trigger out of reset)
always @(posedge clk) begin
fft_mon_raddr <= fft_mon_raddr + 1'b1;
fft_mon_sync <= (fft_mon_raddr == 'd1) ? 1'b1 : 1'b0;
fft_mon_data <= fft_mon_rdata_s;
end
// samples
mem #(.ADDR_WIDTH(PCORE_FFT_MON_ADDR_WIDTH), .DATA_WIDTH(16)) i_mem_adc (
.clka (clk),
.wea (adc_wr),
.addra (adc_waddr),
.dina (adc_wdata),
.clkb (clk),
.addrb (fft_mon_raddr),
.doutb (fft_mon_rdata_s[15:0]));
// window
mem #(.ADDR_WIDTH(PCORE_FFT_MON_ADDR_WIDTH), .DATA_WIDTH(16)) i_mem_win (
.clka (clk),
.wea (win_wr),
.addra (win_waddr),
.dina (win_wdata),
.clkb (clk),
.addrb (fft_mon_raddr),
.doutb (fft_mon_rdata_s[31:16]));
// fft mag.
mem #(.ADDR_WIDTH(PCORE_FFT_MON_ADDR_WIDTH), .DATA_WIDTH(32)) i_mem_fft_mag (
.clka (clk),
.wea (fft_mag_wr),
.addra (fft_mag_waddr),
.dina (fft_mag_wdata),
.clkb (clk),
.addrb (fft_mon_raddr),
.doutb (fft_mon_rdata_s[63:32]));
endmodule
// ***************************************************************************
// ***************************************************************************
|
// ==================================================================
// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
// ------------------------------------------------------------------
// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// ------------------------------------------------------------------
//
// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
//
// Permission:
//
// Lattice Semiconductor grants permission to use this code
// pursuant to the terms of the Lattice Semiconductor Corporation
// Open Source License Agreement.
//
// Disclaimer:
//
// Lattice Semiconductor provides no warranty regarding the use or
// functionality of this code. It is the user's responsibility to
// verify the user's design for consistency and functionality through
// the use of formal verification methods.
//
// --------------------------------------------------------------------
//
// Lattice Semiconductor Corporation
// 5555 NE Moore Court
// Hillsboro, OR 97214
// U.S.A
//
// TEL: 1-800-Lattice (USA and Canada)
// 503-286-8001 (other locations)
//
// web: http://www.latticesemi.com/
// email: [email protected]
//
// --------------------------------------------------------------------
// FILE DETAILS
// Project : LatticeMico32
// File : lm32_jtag.v
// Title : JTAG interface
// Dependencies : lm32_include.v
// Version : 6.1.17
// : Initial Release
// Version : 7.0SP2, 3.0
// : No Change
// Version : 3.1
// : No Change
// =============================================================================
`include "lm32_include.v"
`ifdef CFG_JTAG_ENABLED
`define LM32_DP 3'b000
`define LM32_TX 3'b001
`define LM32_RX 3'b010
// LM32 Debug Protocol commands IDs
`define LM32_DP_RNG 3:0
`define LM32_DP_READ_MEMORY 4'b0001
`define LM32_DP_WRITE_MEMORY 4'b0010
`define LM32_DP_READ_SEQUENTIAL 4'b0011
`define LM32_DP_WRITE_SEQUENTIAL 4'b0100
`define LM32_DP_WRITE_CSR 4'b0101
`define LM32_DP_BREAK 4'b0110
`define LM32_DP_RESET 4'b0111
// States for FSM
`define LM32_JTAG_STATE_RNG 3:0
`define LM32_JTAG_STATE_READ_COMMAND 4'h0
`define LM32_JTAG_STATE_READ_BYTE_0 4'h1
`define LM32_JTAG_STATE_READ_BYTE_1 4'h2
`define LM32_JTAG_STATE_READ_BYTE_2 4'h3
`define LM32_JTAG_STATE_READ_BYTE_3 4'h4
`define LM32_JTAG_STATE_READ_BYTE_4 4'h5
`define LM32_JTAG_STATE_PROCESS_COMMAND 4'h6
`define LM32_JTAG_STATE_WAIT_FOR_MEMORY 4'h7
`define LM32_JTAG_STATE_WAIT_FOR_CSR 4'h8
/////////////////////////////////////////////////////
// Module interface
/////////////////////////////////////////////////////
module lm32_jtag (
// ----- Inputs -------
clk_i,
rst_i,
jtag_clk,
jtag_update,
jtag_reg_q,
jtag_reg_addr_q,
`ifdef CFG_JTAG_UART_ENABLED
csr,
csr_write_enable,
csr_write_data,
stall_x,
`endif
`ifdef CFG_HW_DEBUG_ENABLED
jtag_read_data,
jtag_access_complete,
`endif
`ifdef CFG_DEBUG_ENABLED
exception_q_w,
`endif
// ----- Outputs -------
`ifdef CFG_JTAG_UART_ENABLED
jtx_csr_read_data,
jrx_csr_read_data,
`endif
`ifdef CFG_HW_DEBUG_ENABLED
jtag_csr_write_enable,
jtag_csr_write_data,
jtag_csr,
jtag_read_enable,
jtag_write_enable,
jtag_write_data,
jtag_address,
`endif
`ifdef CFG_DEBUG_ENABLED
jtag_break,
jtag_reset,
`endif
jtag_reg_d,
jtag_reg_addr_d
);
/////////////////////////////////////////////////////
// Inputs
/////////////////////////////////////////////////////
input clk_i; // Clock
input rst_i; // Reset
input jtag_clk; // JTAG clock
input jtag_update; // JTAG data register has been updated
input [`LM32_BYTE_RNG] jtag_reg_q; // JTAG data register
input [2:0] jtag_reg_addr_q; // JTAG data register
`ifdef CFG_JTAG_UART_ENABLED
input [`LM32_CSR_RNG] csr; // CSR to write
input csr_write_enable; // CSR write enable
input [`LM32_WORD_RNG] csr_write_data; // Data to write to specified CSR
input stall_x; // Stall instruction in X stage
`endif
`ifdef CFG_HW_DEBUG_ENABLED
input [`LM32_BYTE_RNG] jtag_read_data; // Data read from requested address
input jtag_access_complete; // Memory access if complete
`endif
`ifdef CFG_DEBUG_ENABLED
input exception_q_w; // Indicates an exception has occured in W stage
`endif
/////////////////////////////////////////////////////
// Outputs
/////////////////////////////////////////////////////
`ifdef CFG_JTAG_UART_ENABLED
output [`LM32_WORD_RNG] jtx_csr_read_data; // Value of JTX CSR for rcsr instructions
wire [`LM32_WORD_RNG] jtx_csr_read_data;
output [`LM32_WORD_RNG] jrx_csr_read_data; // Value of JRX CSR for rcsr instructions
wire [`LM32_WORD_RNG] jrx_csr_read_data;
`endif
`ifdef CFG_HW_DEBUG_ENABLED
output jtag_csr_write_enable; // CSR write enable
reg jtag_csr_write_enable;
output [`LM32_WORD_RNG] jtag_csr_write_data; // Data to write to specified CSR
wire [`LM32_WORD_RNG] jtag_csr_write_data;
output [`LM32_CSR_RNG] jtag_csr; // CSR to write
wire [`LM32_CSR_RNG] jtag_csr;
output jtag_read_enable; // Memory read enable
reg jtag_read_enable;
output jtag_write_enable; // Memory write enable
reg jtag_write_enable;
output [`LM32_BYTE_RNG] jtag_write_data; // Data to write to specified address
wire [`LM32_BYTE_RNG] jtag_write_data;
output [`LM32_WORD_RNG] jtag_address; // Memory read/write address
wire [`LM32_WORD_RNG] jtag_address;
`endif
`ifdef CFG_DEBUG_ENABLED
output jtag_break; // Request to raise a breakpoint exception
reg jtag_break;
output jtag_reset; // Request to raise a reset exception
reg jtag_reset;
`endif
output [`LM32_BYTE_RNG] jtag_reg_d;
reg [`LM32_BYTE_RNG] jtag_reg_d;
output [2:0] jtag_reg_addr_d;
wire [2:0] jtag_reg_addr_d;
/////////////////////////////////////////////////////
// Internal nets and registers
/////////////////////////////////////////////////////
reg rx_toggle; // Clock-domain crossing registers
reg rx_toggle_r; // Registered version of rx_toggle
reg rx_toggle_r_r; // Registered version of rx_toggle_r
reg rx_toggle_r_r_r; // Registered version of rx_toggle_r_r
reg [`LM32_BYTE_RNG] rx_byte;
reg [2:0] rx_addr;
`ifdef CFG_JTAG_UART_ENABLED
reg [`LM32_BYTE_RNG] uart_tx_byte; // UART TX data
reg uart_tx_valid; // TX data is valid
reg [`LM32_BYTE_RNG] uart_rx_byte; // UART RX data
reg uart_rx_valid; // RX data is valid
`endif
reg [`LM32_DP_RNG] command; // The last received command
`ifdef CFG_HW_DEBUG_ENABLED
reg [`LM32_BYTE_RNG] jtag_byte_0; // Registers to hold command paramaters
reg [`LM32_BYTE_RNG] jtag_byte_1;
reg [`LM32_BYTE_RNG] jtag_byte_2;
reg [`LM32_BYTE_RNG] jtag_byte_3;
reg [`LM32_BYTE_RNG] jtag_byte_4;
reg processing; // Indicates if we're still processing a memory read/write
`endif
reg [`LM32_JTAG_STATE_RNG] state; // Current state of FSM
/////////////////////////////////////////////////////
// Combinational Logic
/////////////////////////////////////////////////////
`ifdef CFG_HW_DEBUG_ENABLED
assign jtag_csr_write_data = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3};
assign jtag_csr = jtag_byte_4[`LM32_CSR_RNG];
assign jtag_address = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3};
assign jtag_write_data = jtag_byte_4;
`endif
// Generate status flags for reading via the JTAG interface
`ifdef CFG_JTAG_UART_ENABLED
assign jtag_reg_addr_d[1:0] = {uart_rx_valid, uart_tx_valid};
`else
assign jtag_reg_addr_d[1:0] = 2'b00;
`endif
`ifdef CFG_HW_DEBUG_ENABLED
assign jtag_reg_addr_d[2] = processing;
`else
assign jtag_reg_addr_d[2] = 1'b0;
`endif
`ifdef CFG_JTAG_UART_ENABLED
assign jtx_csr_read_data = {{`LM32_WORD_WIDTH-9{1'b0}}, uart_tx_valid, 8'h00};
assign jrx_csr_read_data = {{`LM32_WORD_WIDTH-9{1'b0}}, uart_rx_valid, uart_rx_byte};
`endif
/////////////////////////////////////////////////////
// Sequential Logic
/////////////////////////////////////////////////////
// Toggle a flag when a JTAG write occurs
always @(negedge jtag_update `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
rx_toggle <= 1'b0;
else
rx_toggle <= ~rx_toggle;
end
always @(*)
begin
rx_byte = jtag_reg_q;
rx_addr = jtag_reg_addr_q;
end
// Clock domain crossing from JTAG clock domain to CPU clock domain
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
begin
rx_toggle_r <= 1'b0;
rx_toggle_r_r <= 1'b0;
rx_toggle_r_r_r <= 1'b0;
end
else
begin
rx_toggle_r <= rx_toggle;
rx_toggle_r_r <= rx_toggle_r;
rx_toggle_r_r_r <= rx_toggle_r_r;
end
end
// LM32 debug protocol state machine
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
begin
state <= `LM32_JTAG_STATE_READ_COMMAND;
command <= 4'b0000;
jtag_reg_d <= 8'h00;
`ifdef CFG_HW_DEBUG_ENABLED
processing <= `FALSE;
jtag_csr_write_enable <= `FALSE;
jtag_read_enable <= `FALSE;
jtag_write_enable <= `FALSE;
`endif
`ifdef CFG_DEBUG_ENABLED
jtag_break <= `FALSE;
jtag_reset <= `FALSE;
`endif
`ifdef CFG_JTAG_UART_ENABLED
uart_tx_byte <= 8'h00;
uart_tx_valid <= `FALSE;
uart_rx_byte <= 8'h00;
uart_rx_valid <= `FALSE;
`endif
end
else
begin
`ifdef CFG_JTAG_UART_ENABLED
if ((csr_write_enable == `TRUE) && (stall_x == `FALSE))
begin
case (csr)
`LM32_CSR_JTX:
begin
// Set flag indicating data is available
uart_tx_byte <= csr_write_data[`LM32_BYTE_0_RNG];
uart_tx_valid <= `TRUE;
end
`LM32_CSR_JRX:
begin
// Clear flag indidicating data has been received
uart_rx_valid <= `FALSE;
end
endcase
end
`endif
`ifdef CFG_DEBUG_ENABLED
// When an exception has occured, clear the requests
if (exception_q_w == `TRUE)
begin
jtag_break <= `FALSE;
jtag_reset <= `FALSE;
end
`endif
case (state)
`LM32_JTAG_STATE_READ_COMMAND:
begin
// Wait for rx register to toggle which indicates new data is available
if (rx_toggle_r_r != rx_toggle_r_r_r)
begin
command <= rx_byte[7:4];
case (rx_addr)
`ifdef CFG_DEBUG_ENABLED
`LM32_DP:
begin
case (rx_byte[7:4])
`ifdef CFG_HW_DEBUG_ENABLED
`LM32_DP_READ_MEMORY:
state <= `LM32_JTAG_STATE_READ_BYTE_0;
`LM32_DP_READ_SEQUENTIAL:
begin
{jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1;
state <= `LM32_JTAG_STATE_PROCESS_COMMAND;
end
`LM32_DP_WRITE_MEMORY:
state <= `LM32_JTAG_STATE_READ_BYTE_0;
`LM32_DP_WRITE_SEQUENTIAL:
begin
{jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1;
state <= 5;
end
`LM32_DP_WRITE_CSR:
state <= `LM32_JTAG_STATE_READ_BYTE_0;
`endif
`LM32_DP_BREAK:
begin
`ifdef CFG_JTAG_UART_ENABLED
uart_rx_valid <= `FALSE;
uart_tx_valid <= `FALSE;
`endif
jtag_break <= `TRUE;
end
`LM32_DP_RESET:
begin
`ifdef CFG_JTAG_UART_ENABLED
uart_rx_valid <= `FALSE;
uart_tx_valid <= `FALSE;
`endif
jtag_reset <= `TRUE;
end
endcase
end
`endif
`ifdef CFG_JTAG_UART_ENABLED
`LM32_TX:
begin
uart_rx_byte <= rx_byte;
uart_rx_valid <= `TRUE;
end
`LM32_RX:
begin
jtag_reg_d <= uart_tx_byte;
uart_tx_valid <= `FALSE;
end
`endif
default:
;
endcase
end
end
`ifdef CFG_HW_DEBUG_ENABLED
`LM32_JTAG_STATE_READ_BYTE_0:
begin
if (rx_toggle_r_r != rx_toggle_r_r_r)
begin
jtag_byte_0 <= rx_byte;
state <= `LM32_JTAG_STATE_READ_BYTE_1;
end
end
`LM32_JTAG_STATE_READ_BYTE_1:
begin
if (rx_toggle_r_r != rx_toggle_r_r_r)
begin
jtag_byte_1 <= rx_byte;
state <= `LM32_JTAG_STATE_READ_BYTE_2;
end
end
`LM32_JTAG_STATE_READ_BYTE_2:
begin
if (rx_toggle_r_r != rx_toggle_r_r_r)
begin
jtag_byte_2 <= rx_byte;
state <= `LM32_JTAG_STATE_READ_BYTE_3;
end
end
`LM32_JTAG_STATE_READ_BYTE_3:
begin
if (rx_toggle_r_r != rx_toggle_r_r_r)
begin
jtag_byte_3 <= rx_byte;
if (command == `LM32_DP_READ_MEMORY)
state <= `LM32_JTAG_STATE_PROCESS_COMMAND;
else
state <= `LM32_JTAG_STATE_READ_BYTE_4;
end
end
`LM32_JTAG_STATE_READ_BYTE_4:
begin
if (rx_toggle_r_r != rx_toggle_r_r_r)
begin
jtag_byte_4 <= rx_byte;
state <= `LM32_JTAG_STATE_PROCESS_COMMAND;
end
end
`LM32_JTAG_STATE_PROCESS_COMMAND:
begin
case (command)
`LM32_DP_READ_MEMORY,
`LM32_DP_READ_SEQUENTIAL:
begin
jtag_read_enable <= `TRUE;
processing <= `TRUE;
state <= `LM32_JTAG_STATE_WAIT_FOR_MEMORY;
end
`LM32_DP_WRITE_MEMORY,
`LM32_DP_WRITE_SEQUENTIAL:
begin
jtag_write_enable <= `TRUE;
processing <= `TRUE;
state <= `LM32_JTAG_STATE_WAIT_FOR_MEMORY;
end
`LM32_DP_WRITE_CSR:
begin
jtag_csr_write_enable <= `TRUE;
processing <= `TRUE;
state <= `LM32_JTAG_STATE_WAIT_FOR_CSR;
end
endcase
end
`LM32_JTAG_STATE_WAIT_FOR_MEMORY:
begin
if (jtag_access_complete == `TRUE)
begin
jtag_read_enable <= `FALSE;
jtag_reg_d <= jtag_read_data;
jtag_write_enable <= `FALSE;
processing <= `FALSE;
state <= `LM32_JTAG_STATE_READ_COMMAND;
end
end
`LM32_JTAG_STATE_WAIT_FOR_CSR:
begin
jtag_csr_write_enable <= `FALSE;
processing <= `FALSE;
state <= `LM32_JTAG_STATE_READ_COMMAND;
end
`endif
endcase
end
end
endmodule
`endif
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconstant:1.1
// IP Revision: 3
(* X_CORE_INFO = "xlconstant_v1_1_3_xlconstant,Vivado 2017.2" *)
(* CHECK_LICENSE_TYPE = "fmrv32im_artya7_xlconstant_0_0,xlconstant_v1_1_3_xlconstant,{}" *)
(* CORE_GENERATION_INFO = "fmrv32im_artya7_xlconstant_0_0,xlconstant_v1_1_3_xlconstant,{x_ipProduct=Vivado 2017.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconstant,x_ipVersion=1.1,x_ipCoreRevision=3,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,CONST_WIDTH=1,CONST_VAL=0x1}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module fmrv32im_artya7_xlconstant_0_0 (
dout
);
output wire [0 : 0] dout;
xlconstant_v1_1_3_xlconstant #(
.CONST_WIDTH(1),
.CONST_VAL('H1)
) inst (
.dout(dout)
);
endmodule
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
//======================================================================
//
// fltcpu_alu.v
// ----------------
// Arithmetic and Logic Unit (ALU) in the cpu. This is where the
// operations are performed.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2015 Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module fltcpu_alu(
input wire clk,
input wire reset_n,
input wire [5 : 0] opcode,
input wire [31 : 0] src0_data,
input wire [31 : 0] src1_data,
output wire [31 : 0] dst_data,
output wire eq_data
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
localparam OPCODE_AND = 6'h04;
localparam OPCODE_OR = 6'h05;
localparam OPCODE_XOR = 6'h06;
localparam OPCODE_NOT = 6'h07;
localparam OPCODE_ADD = 6'h08;
localparam OPCODE_ADDI = 6'h09;
localparam OPCODE_SUB = 6'h0a;
localparam OPCODE_SUBI = 6'h0b;
localparam OPCODE_MUL = 6'h0c;
localparam OPCODE_MULI = 6'h0d;
localparam OPCODE_ASL = 6'h10;
localparam OPCODE_ROL = 6'h11;
localparam OPCODE_ASR = 6'h12;
localparam OPCODE_ROR = 6'h13;
localparam OPCODE_CMP = 6'h30;
localparam OPCODE_CMPI = 6'h31;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg [31 : 0] tmp_dst_data;
reg tmp_eq_data;
wire [4 : 0] shamt;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign dst_data = tmp_dst_data;
assign eq_data = tmp_eq_data;
assign shamt = src1_data[4 : 0];
//----------------------------------------------------------------
// alu
//
// The alu logic.
//----------------------------------------------------------------
always @*
begin : alu
// Default assignments
tmp_dst_data = 32'h0;
tmp_eq_data = 0;
case (opcode)
OPCODE_AND:
tmp_dst_data = src0_data & src1_data;
OPCODE_OR:
tmp_dst_data = src0_data | src1_data;
OPCODE_XOR:
tmp_dst_data = src0_data ^ src1_data;
OPCODE_NOT:
tmp_dst_data = ~src0_data;
OPCODE_ADD, OPCODE_ADDI:
tmp_dst_data = src0_data + src1_data;
OPCODE_SUB, OPCODE_SUBI:
tmp_dst_data = src0_data - src1_data;
OPCODE_MUL:
tmp_dst_data = src0_data * src1_data;
OPCODE_ASL:
tmp_dst_data = src0_data <<< shamt;
OPCODE_ROL:
tmp_dst_data = {(src0_data <<< shamt),
(src0_data >>> (32 - shamt))};
OPCODE_ASR:
tmp_dst_data = src0_data >>> shamt;
OPCODE_ROR:
tmp_dst_data = {(src0_data >>> shamt),
(src0_data <<< (32 - shamt))};
OPCODE_CMP, OPCODE_CMPI:
tmp_eq_data = src0_data == src1_data;
default:
begin
end
endcase // case (opcode)
end // alu
endmodule // fltcpu_alu
//======================================================================
// EOF fltcpu_alu.v
//======================================================================
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NOR4BB_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__NOR4BB_FUNCTIONAL_PP_V
/**
* nor4bb: 4-input NOR, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__nor4bb (
VPWR,
VGND,
Y ,
A ,
B ,
C_N ,
D_N
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A ;
input B ;
input C_N ;
input D_N ;
// Local signals
wire DN nor0_out ;
wire and0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A, B );
and and0 (and0_out_Y , nor0_out, C_N, D_N );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__NOR4BB_FUNCTIONAL_PP_V |
/*
00: Set master reset
01: Shift register
10: Storage register
11: Output Enable
*/
module shift(
input clk ,
input rst ,
input vld ,
input [1:0] cmd ,
input cmd_oen ,
input [7:0] din ,
output done ,
output sft_shcp ,
output sft_ds ,
output sft_stcp ,
output sft_mr_n ,
output sft_oe_n
);
reg sft_mr_n ;
reg sft_oe_n ;
always @ ( posedge clk or posedge rst ) begin
if( rst )
sft_mr_n <= 1'b1 ;
else if( vld && cmd == 2'b00 )
sft_mr_n <= 1'b0 ;
else
sft_mr_n <= 1'b1 ;
end
always @ ( posedge clk or posedge rst ) begin
if( rst )
sft_oe_n <= 1'b1 ;
else if( vld && cmd == 2'b11 )
sft_oe_n <= cmd_oen ;
end
//--------------------------------------------------
// shcp counter
//--------------------------------------------------
reg [5:0] shcp_cnt ;
always @ ( posedge clk ) begin
if( rst )
shcp_cnt <= 0 ;
else if( vld && cmd == 2'b01 )
shcp_cnt <= 1 ;
else if( |shcp_cnt )
shcp_cnt <= shcp_cnt + 1 ;
end
assign sft_shcp = shcp_cnt[2] ;
reg [7:0] data ;
always @ ( posedge clk ) begin
if( vld && cmd == 2'b01 )
data <= din ;
else if( &shcp_cnt[2:0] )
data <= data >> 1 ;
end
assign sft_ds = (vld&&cmd==2'b01) ? din[0] : data[0] ;
//--------------------------------------------------
// sft_stcp
//--------------------------------------------------
reg [5:0] stcp_cnt ;
always @ ( posedge clk ) begin
if( rst )
stcp_cnt <= 0 ;
else if( vld && cmd == 2'b10 )
stcp_cnt <= 1 ;
else if( |stcp_cnt )
stcp_cnt <= stcp_cnt + 1 ;
end
assign sft_stcp = stcp_cnt[2] ;
//--------------------------------------------------
// done
//--------------------------------------------------
assign done = (stcp_cnt == 63) || (shcp_cnt == 63) ;
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version:
// \ \ Application: MIG
// / / Filename: ddr_phy_prbs_rdlvl.v
// /___/ /\ Date Last Modified: $Date: 2011/06/24 14:49:00 $
// \ \ / \ Date Created:
// \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose:
// PRBS Read leveling calibration logic
// NOTES:
// 1. Window detection with PRBS pattern.
//Reference:
//Revision History:
//*****************************************************************************
/******************************************************************************
**$Id: ddr_phy_prbs_rdlvl.v,v 1.2 2011/06/24 14:49:00 mgeorge Exp $
**$Date: 2011/06/24 14:49:00 $
**$Author: mgeorge $
**$Revision: 1.2 $
**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/ddr_phy_prbs_rdlvl.v,v $
******************************************************************************/
`timescale 1ps/1ps
module mig_7series_v2_3_ddr_phy_prbs_rdlvl #
(
parameter TCQ = 100, // clk->out delay (sim only)
parameter nCK_PER_CLK = 2, // # of memory clocks per CLK
parameter DQ_WIDTH = 64, // # of DQ (data)
parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH))
parameter DQS_WIDTH = 8, // # of DQS (strobe)
parameter DRAM_WIDTH = 8, // # of DQ per DQS
parameter RANKS = 1, // # of DRAM ranks
parameter SIM_CAL_OPTION = "NONE", // Skip various calibration steps
parameter PRBS_WIDTH = 8, // PRBS generator output width
parameter FIXED_VICTIM = "TRUE", // No victim rotation when "TRUE"
parameter FINE_PER_BIT = "ON",
parameter CENTER_COMP_MODE = "ON",
parameter PI_VAL_ADJ = "ON"
)
(
input clk,
input rst,
// Calibration status, control signals
input prbs_rdlvl_start,
(* max_fanout = 100 *) output reg prbs_rdlvl_done,
output reg prbs_last_byte_done,
output reg prbs_rdlvl_prech_req,
input complex_sample_cnt_inc,
input prech_done,
input phy_if_empty,
// Captured data in fabric clock domain
input [2*nCK_PER_CLK*DQ_WIDTH-1:0] rd_data,
//Expected data from PRBS generator
input [2*nCK_PER_CLK*DQ_WIDTH-1:0] compare_data,
// Decrement initial Phaser_IN Fine tap delay
input [5:0] pi_counter_read_val,
// Stage 1 calibration outputs
output reg pi_en_stg2_f,
output reg pi_stg2_f_incdec,
output [255:0] dbg_prbs_rdlvl,
output [DQS_CNT_WIDTH:0] pi_stg2_prbs_rdlvl_cnt,
output reg [2:0] rd_victim_sel,
output reg complex_victim_inc,
output reg reset_rd_addr,
output reg read_pause,
output reg [6*DQS_WIDTH*RANKS-1:0] prbs_final_dqs_tap_cnt_r,
output reg [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_first_edge_taps,
output reg [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_second_edge_taps,
output reg [DRAM_WIDTH-1:0] fine_delay_incdec_pb, //fine_delay decreament per bit
output reg fine_delay_sel //fine delay selection - actual update of fine delay
);
localparam [5:0] PRBS_IDLE = 6'h00;
localparam [5:0] PRBS_NEW_DQS_WAIT = 6'h01;
localparam [5:0] PRBS_PAT_COMPARE = 6'h02;
localparam [5:0] PRBS_DEC_DQS = 6'h03;
localparam [5:0] PRBS_DEC_DQS_WAIT = 6'h04;
localparam [5:0] PRBS_INC_DQS = 6'h05;
localparam [5:0] PRBS_INC_DQS_WAIT = 6'h06;
localparam [5:0] PRBS_CALC_TAPS = 6'h07;
localparam [5:0] PRBS_NEXT_DQS = 6'h08;
localparam [5:0] PRBS_NEW_DQS_PREWAIT = 6'h09;
localparam [5:0] PRBS_DONE = 6'h0A;
localparam [5:0] PRBS_CALC_TAPS_PRE = 6'h0B;
localparam [5:0] PRBS_CALC_TAPS_WAIT = 6'h0C;
localparam [5:0] FINE_PI_DEC = 6'h0D; //go back to all fail or back to center
localparam [5:0] FINE_PI_DEC_WAIT = 6'h0E; //wait for PI tap dec settle
localparam [5:0] FINE_PI_INC = 6'h0F; //increse up to 1 fail
localparam [5:0] FINE_PI_INC_WAIT = 6'h10; //wait for PI tap int settle
localparam [5:0] FINE_PAT_COMPARE_PER_BIT = 6'h11; //compare per bit error and check left/right/gain/loss
localparam [5:0] FINE_CALC_TAPS = 6'h12; //setup fine_delay_incdec_pb for better window size
localparam [5:0] FINE_CALC_TAPS_WAIT = 6'h13; //wait for ROM value for dec cnt
localparam [11:0] NUM_SAMPLES_CNT = (SIM_CAL_OPTION == "NONE") ? 'd50 : 12'h001;
localparam [11:0] NUM_SAMPLES_CNT1 = (SIM_CAL_OPTION == "NONE") ? 'd20 : 12'h001;
localparam [11:0] NUM_SAMPLES_CNT2 = (SIM_CAL_OPTION == "NONE") ? 'd10 : 12'h001;
wire [DQS_CNT_WIDTH+2:0]prbs_dqs_cnt_timing;
reg [DQS_CNT_WIDTH+2:0] prbs_dqs_cnt_timing_r;
reg [DQS_CNT_WIDTH:0] prbs_dqs_cnt_r;
reg prbs_prech_req_r;
reg [5:0] prbs_state_r;
reg [5:0] prbs_state_r1;
reg wait_state_cnt_en_r;
reg [3:0] wait_state_cnt_r;
reg cnt_wait_state;
reg err_chk_invalid;
// reg found_edge_r;
reg prbs_found_1st_edge_r;
reg prbs_found_2nd_edge_r;
reg [5:0] prbs_1st_edge_taps_r;
// reg found_stable_eye_r;
reg [5:0] prbs_dqs_tap_cnt_r;
reg [5:0] prbs_dec_tap_calc_plus_3;
reg [5:0] prbs_dec_tap_calc_minus_3;
reg prbs_dqs_tap_limit_r;
reg [5:0] prbs_inc_tap_cnt;
reg [5:0] prbs_dec_tap_cnt;
reg [DRAM_WIDTH-1:0] mux_rd_fall0_r1;
reg [DRAM_WIDTH-1:0] mux_rd_fall1_r1;
reg [DRAM_WIDTH-1:0] mux_rd_rise0_r1;
reg [DRAM_WIDTH-1:0] mux_rd_rise1_r1;
reg [DRAM_WIDTH-1:0] mux_rd_fall2_r1;
reg [DRAM_WIDTH-1:0] mux_rd_fall3_r1;
reg [DRAM_WIDTH-1:0] mux_rd_rise2_r1;
reg [DRAM_WIDTH-1:0] mux_rd_rise3_r1;
reg [DRAM_WIDTH-1:0] mux_rd_fall0_r2;
reg [DRAM_WIDTH-1:0] mux_rd_fall1_r2;
reg [DRAM_WIDTH-1:0] mux_rd_rise0_r2;
reg [DRAM_WIDTH-1:0] mux_rd_rise1_r2;
reg [DRAM_WIDTH-1:0] mux_rd_fall2_r2;
reg [DRAM_WIDTH-1:0] mux_rd_fall3_r2;
reg [DRAM_WIDTH-1:0] mux_rd_rise2_r2;
reg [DRAM_WIDTH-1:0] mux_rd_rise3_r2;
reg [DRAM_WIDTH-1:0] mux_rd_fall0_r3;
reg [DRAM_WIDTH-1:0] mux_rd_fall1_r3;
reg [DRAM_WIDTH-1:0] mux_rd_rise0_r3;
reg [DRAM_WIDTH-1:0] mux_rd_rise1_r3;
reg [DRAM_WIDTH-1:0] mux_rd_fall2_r3;
reg [DRAM_WIDTH-1:0] mux_rd_fall3_r3;
reg [DRAM_WIDTH-1:0] mux_rd_rise2_r3;
reg [DRAM_WIDTH-1:0] mux_rd_rise3_r3;
reg [DRAM_WIDTH-1:0] mux_rd_fall0_r4;
reg [DRAM_WIDTH-1:0] mux_rd_fall1_r4;
reg [DRAM_WIDTH-1:0] mux_rd_rise0_r4;
reg [DRAM_WIDTH-1:0] mux_rd_rise1_r4;
reg [DRAM_WIDTH-1:0] mux_rd_fall2_r4;
reg [DRAM_WIDTH-1:0] mux_rd_fall3_r4;
reg [DRAM_WIDTH-1:0] mux_rd_rise2_r4;
reg [DRAM_WIDTH-1:0] mux_rd_rise3_r4;
reg mux_rd_valid_r;
reg rd_valid_r1;
reg rd_valid_r2;
reg rd_valid_r3;
reg new_cnt_dqs_r;
reg prbs_tap_en_r;
reg prbs_tap_inc_r;
reg pi_en_stg2_f_timing;
reg pi_stg2_f_incdec_timing;
wire [DQ_WIDTH-1:0] rd_data_rise0;
wire [DQ_WIDTH-1:0] rd_data_fall0;
wire [DQ_WIDTH-1:0] rd_data_rise1;
wire [DQ_WIDTH-1:0] rd_data_fall1;
wire [DQ_WIDTH-1:0] rd_data_rise2;
wire [DQ_WIDTH-1:0] rd_data_fall2;
wire [DQ_WIDTH-1:0] rd_data_rise3;
wire [DQ_WIDTH-1:0] rd_data_fall3;
wire [DQ_WIDTH-1:0] compare_data_r0;
wire [DQ_WIDTH-1:0] compare_data_f0;
wire [DQ_WIDTH-1:0] compare_data_r1;
wire [DQ_WIDTH-1:0] compare_data_f1;
wire [DQ_WIDTH-1:0] compare_data_r2;
wire [DQ_WIDTH-1:0] compare_data_f2;
wire [DQ_WIDTH-1:0] compare_data_r3;
wire [DQ_WIDTH-1:0] compare_data_f3;
reg [DRAM_WIDTH-1:0] compare_data_rise0_r1;
reg [DRAM_WIDTH-1:0] compare_data_fall0_r1;
reg [DRAM_WIDTH-1:0] compare_data_rise1_r1;
reg [DRAM_WIDTH-1:0] compare_data_fall1_r1;
reg [DRAM_WIDTH-1:0] compare_data_rise2_r1;
reg [DRAM_WIDTH-1:0] compare_data_fall2_r1;
reg [DRAM_WIDTH-1:0] compare_data_rise3_r1;
reg [DRAM_WIDTH-1:0] compare_data_fall3_r1;
reg [DQS_CNT_WIDTH:0] rd_mux_sel_r;
reg [5:0] prbs_2nd_edge_taps_r;
// reg [6*DQS_WIDTH*RANKS-1:0] prbs_final_dqs_tap_cnt_r;
reg [5:0] rdlvl_cpt_tap_cnt;
reg prbs_rdlvl_start_r;
reg compare_err;
reg compare_err_r0;
reg compare_err_f0;
reg compare_err_r1;
reg compare_err_f1;
reg compare_err_r2;
reg compare_err_f2;
reg compare_err_r3;
reg compare_err_f3;
reg samples_cnt1_en_r;
reg samples_cnt2_en_r;
reg [11:0] samples_cnt_r;
reg num_samples_done_r;
reg num_samples_done_ind; //indicate num_samples_done_r is set in FINE_PAT_COMPARE_PER_BIT to prevent victim_sel_rd out of sync
reg [DQS_WIDTH-1:0] prbs_tap_mod;
//reg [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_first_edge_taps;
//reg [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_second_edge_taps;
//**************************************************************************
// signals for per-bit algorithm of fine_delay calculations
//**************************************************************************
reg [6*DRAM_WIDTH-1:0] left_edge_pb; //left edge value per bit
reg [6*DRAM_WIDTH-1:0] right_edge_pb; //right edge value per bit
reg [5*DRAM_WIDTH-1:0] match_flag_pb; //5 consecutive match flag per bit
reg [4:0] match_flag_and; //5 consecute match flag of all bits (1: all bit fail)
reg [DRAM_WIDTH-1:0] left_edge_found_pb; //left_edge found per bit - use for loss calculation
reg [DRAM_WIDTH-1:0] left_edge_updated; //left edge was updated for this PI tap - used for largest left edge /ref bit update
reg [DRAM_WIDTH-1:0] right_edge_found_pb; //right_edge found per bit - use for gail calulation and smallest right edge update
reg right_edge_found; //smallest right_edge found
reg [DRAM_WIDTH*6-1:0] left_loss_pb; //left_edge loss per bit
reg [DRAM_WIDTH*6-1:0] right_gain_pb; //right_edge gain per bit
reg [DRAM_WIDTH-1:0] ref_bit; //bit number which has largest left edge (with smaller right edge)
reg [DRAM_WIDTH-1:0] bit_cnt; //bit number used to calculate ref bit
reg [DRAM_WIDTH-1:0] ref_bit_per_bit; //bit flags which have largest left edge
reg [5:0] ref_right_edge; //ref_bit right edge - keep the smallest edge of ref bits
reg [5:0] largest_left_edge; //biggest left edge of per bit - will be left edge of byte
reg [5:0] smallest_right_edge; //smallest right edge of per bit - will be right edge of byte
reg [5:0] fine_pi_dec_cnt; //Phase In tap decrement count (to go back to '0' or center)
reg [6:0] center_calc; //used for calculate the dec tap for centering
reg [5:0] right_edge_ref; //ref_bit right edge
reg [5:0] left_edge_ref; //ref_bit left edge
reg [DRAM_WIDTH-1:0] compare_err_pb; //compare error per bit
reg [DRAM_WIDTH-1:0] compare_err_pb_latch_r; //sticky compare error per bit used for left/right edge
reg compare_err_pb_and; //indicate all bit fail
reg fine_inc_stage; //fine_inc_stage (1: increment all except ref_bit, 0: only inc for gain bit)
reg [1:0] stage_cnt; //stage cnt (0,1: fine delay inc stage, 2: fine delay dec stage)
wire fine_calib; //turn on/off fine delay calibration
reg [5:0] mem_out_dec;
reg [5:0] dec_cnt;
reg fine_dly_error; //indicate it has wrong left/right edge
wire center_comp;
wire pi_adj;
//**************************************************************************
// DQS count to hard PHY during write calibration using Phaser_OUT Stage2
// coarse delay
//**************************************************************************
assign pi_stg2_prbs_rdlvl_cnt = prbs_dqs_cnt_r;
//fine delay turn on
assign fine_calib = (FINE_PER_BIT=="ON")? 1:0;
assign center_comp = (CENTER_COMP_MODE == "ON")? 1: 0;
assign pi_adj = (PI_VAL_ADJ == "ON")?1:0;
assign dbg_prbs_rdlvl[0+:6] = left_edge_pb[0+:6];
assign dbg_prbs_rdlvl[7:6] = left_loss_pb[0+:2];
assign dbg_prbs_rdlvl[8+:6] = left_edge_pb[6+:6];
assign dbg_prbs_rdlvl[15:14] = left_loss_pb[6+:2];
assign dbg_prbs_rdlvl[16+:6] = left_edge_pb[12+:6] ;
assign dbg_prbs_rdlvl[23:22] = left_loss_pb[12+:2];
assign dbg_prbs_rdlvl[24+:6] = left_edge_pb[18+:6] ;
assign dbg_prbs_rdlvl[31:30] = left_loss_pb[18+:2];
assign dbg_prbs_rdlvl[32+:6] = left_edge_pb[24+:6];
assign dbg_prbs_rdlvl[39:38] = left_loss_pb[24+:2];
assign dbg_prbs_rdlvl[40+:6] = left_edge_pb[30+:6];
assign dbg_prbs_rdlvl[47:46] = left_loss_pb[30+:2];
assign dbg_prbs_rdlvl[48+:6] = left_edge_pb[36+:6];
assign dbg_prbs_rdlvl[55:54] = left_loss_pb[36+:2];
assign dbg_prbs_rdlvl[56+:6] = left_edge_pb[42+:6];
assign dbg_prbs_rdlvl[63:62] = left_loss_pb[42+:2];
assign dbg_prbs_rdlvl[64+:6] = right_edge_pb[0+:6];
assign dbg_prbs_rdlvl[71:70] = right_gain_pb[0+:2];
assign dbg_prbs_rdlvl[72+:6] = right_edge_pb[6+:6] ;
assign dbg_prbs_rdlvl[79:78] = right_gain_pb[6+:2];
assign dbg_prbs_rdlvl[80+:6] = right_edge_pb[12+:6];
assign dbg_prbs_rdlvl[87:86] = right_gain_pb[12+:2];
assign dbg_prbs_rdlvl[88+:6] = right_edge_pb[18+:6];
assign dbg_prbs_rdlvl[95:94] = right_gain_pb[18+:2];
assign dbg_prbs_rdlvl[96+:6] = right_edge_pb[24+:6];
assign dbg_prbs_rdlvl[103:102] = right_gain_pb[24+:2];
assign dbg_prbs_rdlvl[104+:6] = right_edge_pb[30+:6];
assign dbg_prbs_rdlvl[111:110] = right_gain_pb[30+:2];
assign dbg_prbs_rdlvl[112+:6] = right_edge_pb[36+:6];
assign dbg_prbs_rdlvl[119:118] = right_gain_pb[36+:2];
assign dbg_prbs_rdlvl[120+:6] = right_edge_pb[42+:6];
assign dbg_prbs_rdlvl[127:126] = right_gain_pb[42+:2];
assign dbg_prbs_rdlvl[128+:6] = pi_counter_read_val;
assign dbg_prbs_rdlvl[134+:6] = prbs_dqs_tap_cnt_r;
assign dbg_prbs_rdlvl[140] = prbs_found_1st_edge_r;
assign dbg_prbs_rdlvl[141] = prbs_found_2nd_edge_r;
assign dbg_prbs_rdlvl[142] = compare_err;
assign dbg_prbs_rdlvl[143] = phy_if_empty;
assign dbg_prbs_rdlvl[144] = prbs_rdlvl_start;
assign dbg_prbs_rdlvl[145] = prbs_rdlvl_done;
assign dbg_prbs_rdlvl[146+:5] = prbs_dqs_cnt_r;
assign dbg_prbs_rdlvl[151+:6] = left_edge_pb[prbs_dqs_cnt_r*6+:6] ;
assign dbg_prbs_rdlvl[157+:6] = right_edge_pb[prbs_dqs_cnt_r*6+:6];
assign dbg_prbs_rdlvl[163+:6] = {2'h0,complex_victim_inc, rd_victim_sel[2:0]};
assign dbg_prbs_rdlvl[169+:6] =right_gain_pb[prbs_dqs_cnt_r*6+:6] ;
assign dbg_prbs_rdlvl[177:175] = ref_bit[2:0];
assign dbg_prbs_rdlvl[178+:6] = prbs_state_r1[5:0];
assign dbg_prbs_rdlvl[184] = rd_valid_r2;
assign dbg_prbs_rdlvl[185] = compare_err_r0;
assign dbg_prbs_rdlvl[186] = compare_err_f0;
assign dbg_prbs_rdlvl[187] = compare_err_r1;
assign dbg_prbs_rdlvl[188] = compare_err_f1;
assign dbg_prbs_rdlvl[189] = compare_err_r2;
assign dbg_prbs_rdlvl[190] = compare_err_f2;
assign dbg_prbs_rdlvl[191] = compare_err_r3;
assign dbg_prbs_rdlvl[192] = compare_err_f3;
assign dbg_prbs_rdlvl[193+:8] = left_edge_found_pb;
assign dbg_prbs_rdlvl[201+:8] = right_edge_found_pb;
assign dbg_prbs_rdlvl[209+:6] =largest_left_edge ;
assign dbg_prbs_rdlvl[215+:6] =smallest_right_edge ;
assign dbg_prbs_rdlvl[221+:8] = fine_delay_incdec_pb;
assign dbg_prbs_rdlvl[229] = fine_delay_sel;
assign dbg_prbs_rdlvl[230+:8] = compare_err_pb_latch_r;
assign dbg_prbs_rdlvl[238+:6] = fine_pi_dec_cnt;
assign dbg_prbs_rdlvl[244+:5] = match_flag_and ;
assign dbg_prbs_rdlvl[249+:2] =stage_cnt ;
assign dbg_prbs_rdlvl[251] = fine_inc_stage ;
assign dbg_prbs_rdlvl[252] = compare_err_pb_and ;
assign dbg_prbs_rdlvl[253] = right_edge_found ;
assign dbg_prbs_rdlvl[254] = fine_dly_error ;
assign dbg_prbs_rdlvl[255]= 'b0;//reserved
//**************************************************************************
// Record first and second edges found during calibration
//**************************************************************************
generate
always @(posedge clk)
if (rst) begin
dbg_prbs_first_edge_taps <= #TCQ 'b0;
dbg_prbs_second_edge_taps <= #TCQ 'b0;
end else if (prbs_state_r == PRBS_CALC_TAPS) begin
// Record tap counts of first and second edge edges during
// calibration for each DQS group. If neither edge has
// been found, then those taps will remain 0
if (prbs_found_1st_edge_r)
dbg_prbs_first_edge_taps[(prbs_dqs_cnt_timing_r*6)+:6]
<= #TCQ prbs_1st_edge_taps_r;
if (prbs_found_2nd_edge_r)
dbg_prbs_second_edge_taps[(prbs_dqs_cnt_timing_r*6)+:6]
<= #TCQ prbs_2nd_edge_taps_r;
end else if (prbs_state_r == FINE_CALC_TAPS) begin
if(stage_cnt == 'd2) begin
dbg_prbs_first_edge_taps[(prbs_dqs_cnt_timing_r*6)+:6]
<= #TCQ largest_left_edge;
dbg_prbs_second_edge_taps[(prbs_dqs_cnt_timing_r*6)+:6]
<= #TCQ smallest_right_edge;
end
end
endgenerate
//padded calculation
always @ (smallest_right_edge or largest_left_edge)
center_calc <= {1'b0, smallest_right_edge} + {1'b0,largest_left_edge};
//***************************************************************************
//***************************************************************************
// Data mux to route appropriate bit to calibration logic - i.e. calibration
// is done sequentially, one bit (or DQS group) at a time
//***************************************************************************
generate
if (nCK_PER_CLK == 4) begin: rd_data_div4_logic_clk
assign rd_data_rise0 = rd_data[DQ_WIDTH-1:0];
assign rd_data_fall0 = rd_data[2*DQ_WIDTH-1:DQ_WIDTH];
assign rd_data_rise1 = rd_data[3*DQ_WIDTH-1:2*DQ_WIDTH];
assign rd_data_fall1 = rd_data[4*DQ_WIDTH-1:3*DQ_WIDTH];
assign rd_data_rise2 = rd_data[5*DQ_WIDTH-1:4*DQ_WIDTH];
assign rd_data_fall2 = rd_data[6*DQ_WIDTH-1:5*DQ_WIDTH];
assign rd_data_rise3 = rd_data[7*DQ_WIDTH-1:6*DQ_WIDTH];
assign rd_data_fall3 = rd_data[8*DQ_WIDTH-1:7*DQ_WIDTH];
assign compare_data_r0 = compare_data[DQ_WIDTH-1:0];
assign compare_data_f0 = compare_data[2*DQ_WIDTH-1:DQ_WIDTH];
assign compare_data_r1 = compare_data[3*DQ_WIDTH-1:2*DQ_WIDTH];
assign compare_data_f1 = compare_data[4*DQ_WIDTH-1:3*DQ_WIDTH];
assign compare_data_r2 = compare_data[5*DQ_WIDTH-1:4*DQ_WIDTH];
assign compare_data_f2 = compare_data[6*DQ_WIDTH-1:5*DQ_WIDTH];
assign compare_data_r3 = compare_data[7*DQ_WIDTH-1:6*DQ_WIDTH];
assign compare_data_f3 = compare_data[8*DQ_WIDTH-1:7*DQ_WIDTH];
end else begin: rd_data_div2_logic_clk
assign rd_data_rise0 = rd_data[DQ_WIDTH-1:0];
assign rd_data_fall0 = rd_data[2*DQ_WIDTH-1:DQ_WIDTH];
assign rd_data_rise1 = rd_data[3*DQ_WIDTH-1:2*DQ_WIDTH];
assign rd_data_fall1 = rd_data[4*DQ_WIDTH-1:3*DQ_WIDTH];
assign compare_data_r0 = compare_data[DQ_WIDTH-1:0];
assign compare_data_f0 = compare_data[2*DQ_WIDTH-1:DQ_WIDTH];
assign compare_data_r1 = compare_data[3*DQ_WIDTH-1:2*DQ_WIDTH];
assign compare_data_f1 = compare_data[4*DQ_WIDTH-1:3*DQ_WIDTH];
assign compare_data_r2 = 'h0;
assign compare_data_f2 = 'h0;
assign compare_data_r3 = 'h0;
assign compare_data_f3 = 'h0;
end
endgenerate
always @(posedge clk) begin
rd_mux_sel_r <= #TCQ prbs_dqs_cnt_r;
end
// Register outputs for improved timing.
// NOTE: Will need to change when per-bit DQ deskew is supported.
// Currenly all bits in DQS group are checked in aggregate
generate
genvar mux_i;
for (mux_i = 0; mux_i < DRAM_WIDTH; mux_i = mux_i + 1) begin: gen_mux_rd
always @(posedge clk) begin
mux_rd_rise0_r1[mux_i] <= #TCQ rd_data_rise0[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_fall0_r1[mux_i] <= #TCQ rd_data_fall0[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_rise1_r1[mux_i] <= #TCQ rd_data_rise1[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_fall1_r1[mux_i] <= #TCQ rd_data_fall1[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_rise2_r1[mux_i] <= #TCQ rd_data_rise2[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_fall2_r1[mux_i] <= #TCQ rd_data_fall2[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_rise3_r1[mux_i] <= #TCQ rd_data_rise3[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_fall3_r1[mux_i] <= #TCQ rd_data_fall3[DRAM_WIDTH*rd_mux_sel_r + mux_i];
//Compare data
compare_data_rise0_r1[mux_i] <= #TCQ compare_data_r0[DRAM_WIDTH*rd_mux_sel_r + mux_i];
compare_data_fall0_r1[mux_i] <= #TCQ compare_data_f0[DRAM_WIDTH*rd_mux_sel_r + mux_i];
compare_data_rise1_r1[mux_i] <= #TCQ compare_data_r1[DRAM_WIDTH*rd_mux_sel_r + mux_i];
compare_data_fall1_r1[mux_i] <= #TCQ compare_data_f1[DRAM_WIDTH*rd_mux_sel_r + mux_i];
compare_data_rise2_r1[mux_i] <= #TCQ compare_data_r2[DRAM_WIDTH*rd_mux_sel_r + mux_i];
compare_data_fall2_r1[mux_i] <= #TCQ compare_data_f2[DRAM_WIDTH*rd_mux_sel_r + mux_i];
compare_data_rise3_r1[mux_i] <= #TCQ compare_data_r3[DRAM_WIDTH*rd_mux_sel_r + mux_i];
compare_data_fall3_r1[mux_i] <= #TCQ compare_data_f3[DRAM_WIDTH*rd_mux_sel_r + mux_i];
end
end
endgenerate
generate
genvar muxr2_i;
if (nCK_PER_CLK == 4) begin: gen_mux_div4
for (muxr2_i = 0; muxr2_i < DRAM_WIDTH; muxr2_i = muxr2_i + 1) begin: gen_rd_4
always @(posedge clk) begin
if (mux_rd_valid_r) begin
mux_rd_rise0_r2[muxr2_i] <= #TCQ mux_rd_rise0_r1[muxr2_i];
mux_rd_fall0_r2[muxr2_i] <= #TCQ mux_rd_fall0_r1[muxr2_i];
mux_rd_rise1_r2[muxr2_i] <= #TCQ mux_rd_rise1_r1[muxr2_i];
mux_rd_fall1_r2[muxr2_i] <= #TCQ mux_rd_fall1_r1[muxr2_i];
mux_rd_rise2_r2[muxr2_i] <= #TCQ mux_rd_rise2_r1[muxr2_i];
mux_rd_fall2_r2[muxr2_i] <= #TCQ mux_rd_fall2_r1[muxr2_i];
mux_rd_rise3_r2[muxr2_i] <= #TCQ mux_rd_rise3_r1[muxr2_i];
mux_rd_fall3_r2[muxr2_i] <= #TCQ mux_rd_fall3_r1[muxr2_i];
end
//pipeline stage
mux_rd_rise0_r3[muxr2_i] <= #TCQ mux_rd_rise0_r2[muxr2_i];
mux_rd_fall0_r3[muxr2_i] <= #TCQ mux_rd_fall0_r2[muxr2_i];
mux_rd_rise1_r3[muxr2_i] <= #TCQ mux_rd_rise1_r2[muxr2_i];
mux_rd_fall1_r3[muxr2_i] <= #TCQ mux_rd_fall1_r2[muxr2_i];
mux_rd_rise2_r3[muxr2_i] <= #TCQ mux_rd_rise2_r2[muxr2_i];
mux_rd_fall2_r3[muxr2_i] <= #TCQ mux_rd_fall2_r2[muxr2_i];
mux_rd_rise3_r3[muxr2_i] <= #TCQ mux_rd_rise3_r2[muxr2_i];
mux_rd_fall3_r3[muxr2_i] <= #TCQ mux_rd_fall3_r2[muxr2_i];
//pipeline stage
mux_rd_rise0_r4[muxr2_i] <= #TCQ mux_rd_rise0_r3[muxr2_i];
mux_rd_fall0_r4[muxr2_i] <= #TCQ mux_rd_fall0_r3[muxr2_i];
mux_rd_rise1_r4[muxr2_i] <= #TCQ mux_rd_rise1_r3[muxr2_i];
mux_rd_fall1_r4[muxr2_i] <= #TCQ mux_rd_fall1_r3[muxr2_i];
mux_rd_rise2_r4[muxr2_i] <= #TCQ mux_rd_rise2_r3[muxr2_i];
mux_rd_fall2_r4[muxr2_i] <= #TCQ mux_rd_fall2_r3[muxr2_i];
mux_rd_rise3_r4[muxr2_i] <= #TCQ mux_rd_rise3_r3[muxr2_i];
mux_rd_fall3_r4[muxr2_i] <= #TCQ mux_rd_fall3_r3[muxr2_i];
end
end
end else if (nCK_PER_CLK == 2) begin: gen_mux_div2
for (muxr2_i = 0; muxr2_i < DRAM_WIDTH; muxr2_i = muxr2_i + 1) begin: gen_rd_2
always @(posedge clk) begin
if (mux_rd_valid_r) begin
mux_rd_rise0_r2[muxr2_i] <= #TCQ mux_rd_rise0_r1[muxr2_i];
mux_rd_fall0_r2[muxr2_i] <= #TCQ mux_rd_fall0_r1[muxr2_i];
mux_rd_rise1_r2[muxr2_i] <= #TCQ mux_rd_rise1_r1[muxr2_i];
mux_rd_fall1_r2[muxr2_i] <= #TCQ mux_rd_fall1_r1[muxr2_i];
mux_rd_rise2_r2[muxr2_i] <= 'h0;
mux_rd_fall2_r2[muxr2_i] <= 'h0;
mux_rd_rise3_r2[muxr2_i] <= 'h0;
mux_rd_fall3_r2[muxr2_i] <= 'h0;
end
mux_rd_rise0_r3[muxr2_i] <= #TCQ mux_rd_rise0_r2[muxr2_i];
mux_rd_fall0_r3[muxr2_i] <= #TCQ mux_rd_fall0_r2[muxr2_i];
mux_rd_rise1_r3[muxr2_i] <= #TCQ mux_rd_rise1_r2[muxr2_i];
mux_rd_fall1_r3[muxr2_i] <= #TCQ mux_rd_fall1_r2[muxr2_i];
mux_rd_rise2_r3[muxr2_i] <= 'h0;
mux_rd_fall2_r3[muxr2_i] <= 'h0;
mux_rd_rise3_r3[muxr2_i] <= 'h0;
mux_rd_fall3_r3[muxr2_i] <= 'h0;
//pipeline stage
mux_rd_rise0_r4[muxr2_i] <= #TCQ mux_rd_rise0_r3[muxr2_i];
mux_rd_fall0_r4[muxr2_i] <= #TCQ mux_rd_fall0_r3[muxr2_i];
mux_rd_rise1_r4[muxr2_i] <= #TCQ mux_rd_rise1_r3[muxr2_i];
mux_rd_fall1_r4[muxr2_i] <= #TCQ mux_rd_fall1_r3[muxr2_i];
mux_rd_rise2_r4[muxr2_i] <= 'h0;
mux_rd_fall2_r4[muxr2_i] <= 'h0;
mux_rd_rise3_r4[muxr2_i] <= 'h0;
mux_rd_fall3_r4[muxr2_i] <= 'h0;
end
end
end
endgenerate
// Registered signal indicates when mux_rd_rise/fall_r is valid
always @(posedge clk) begin
mux_rd_valid_r <= #TCQ ~phy_if_empty && prbs_rdlvl_start;
rd_valid_r1 <= #TCQ mux_rd_valid_r;
rd_valid_r2 <= #TCQ rd_valid_r1;
rd_valid_r3 <= #TCQ rd_valid_r2;
end
// Counter counts # of samples compared
// Reset sample counter when not "sampling"
// Otherwise, count # of samples compared
// Same counter is shared for three samples checked
always @(posedge clk)
if (rst)
samples_cnt_r <= #TCQ 'b0;
else if (samples_cnt_r == NUM_SAMPLES_CNT) begin
samples_cnt_r <= #TCQ 'b0;
end else if (complex_sample_cnt_inc) begin
samples_cnt_r <= #TCQ samples_cnt_r + 1;
/*if (!rd_valid_r1 ||
(prbs_state_r == PRBS_DEC_DQS_WAIT) ||
(prbs_state_r == PRBS_INC_DQS_WAIT) ||
(prbs_state_r == PRBS_DEC_DQS) ||
(prbs_state_r == PRBS_INC_DQS) ||
(samples_cnt_r == NUM_SAMPLES_CNT) ||
(samples_cnt_r == NUM_SAMPLES_CNT1))
samples_cnt_r <= #TCQ 'b0;
else if (rd_valid_r1 &&
(((samples_cnt_r < NUM_SAMPLES_CNT) && ~samples_cnt1_en_r) ||
((samples_cnt_r < NUM_SAMPLES_CNT1) && ~samples_cnt2_en_r) ||
((samples_cnt_r < NUM_SAMPLES_CNT2) && samples_cnt2_en_r)))
samples_cnt_r <= #TCQ samples_cnt_r + 1;*/
end
// Count #2 enable generation
// Assert when correct number of samples compared
always @(posedge clk)
if (rst)
samples_cnt1_en_r <= #TCQ 1'b0;
else begin
if ((prbs_state_r == PRBS_IDLE) ||
(prbs_state_r == PRBS_DEC_DQS) ||
(prbs_state_r == PRBS_INC_DQS) ||
(prbs_state_r == FINE_PI_INC) ||
(prbs_state_r == PRBS_NEW_DQS_PREWAIT))
samples_cnt1_en_r <= #TCQ 1'b0;
else if ((samples_cnt_r == NUM_SAMPLES_CNT) && rd_valid_r1)
samples_cnt1_en_r <= #TCQ 1'b1;
end
// Counter #3 enable generation
// Assert when correct number of samples compared
always @(posedge clk)
if (rst)
samples_cnt2_en_r <= #TCQ 1'b0;
else begin
if ((prbs_state_r == PRBS_IDLE) ||
(prbs_state_r == PRBS_DEC_DQS) ||
(prbs_state_r == PRBS_INC_DQS) ||
(prbs_state_r == FINE_PI_INC) ||
(prbs_state_r == PRBS_NEW_DQS_PREWAIT))
samples_cnt2_en_r <= #TCQ 1'b0;
else if ((samples_cnt_r == NUM_SAMPLES_CNT1) && rd_valid_r1 && samples_cnt1_en_r)
samples_cnt2_en_r <= #TCQ 1'b1;
end
// Victim selection logic
always @(posedge clk)
if (rst)
rd_victim_sel <= #TCQ 'd0;
else if (num_samples_done_r)
rd_victim_sel <= #TCQ 'd0;
else if (samples_cnt_r == NUM_SAMPLES_CNT) begin
if (rd_victim_sel < 'd7)
rd_victim_sel <= #TCQ rd_victim_sel + 1;
end
// Output row count increment pulse to phy_init
always @(posedge clk)
if (rst)
complex_victim_inc <= #TCQ 1'b0;
else if (samples_cnt_r == NUM_SAMPLES_CNT)
complex_victim_inc <= #TCQ 1'b1;
else
complex_victim_inc <= #TCQ 1'b0;
generate
if (FIXED_VICTIM == "TRUE") begin: victim_fixed
always @(posedge clk)
if (rst)
num_samples_done_r <= #TCQ 1'b0;
else if ((prbs_state_r == PRBS_DEC_DQS) ||
(prbs_state_r == PRBS_INC_DQS)||
(prbs_state_r == FINE_PI_INC) ||
(prbs_state_r == FINE_PI_DEC))
num_samples_done_r <= #TCQ 'b0;
else if (samples_cnt_r == NUM_SAMPLES_CNT)
num_samples_done_r <= #TCQ 1'b1;
end else begin: victim_not_fixed
always @(posedge clk)
if (rst)
num_samples_done_r <= #TCQ 1'b0;
else if ((prbs_state_r == PRBS_DEC_DQS) ||
(prbs_state_r == PRBS_INC_DQS)||
(prbs_state_r == FINE_PI_INC) ||
(prbs_state_r == FINE_PI_DEC))
num_samples_done_r <= #TCQ 'b0;
else if ((samples_cnt_r == NUM_SAMPLES_CNT) && (rd_victim_sel == 'd7))
num_samples_done_r <= #TCQ 1'b1;
end
endgenerate
//***************************************************************************
// Compare Read Data for the byte being Leveled with Expected data from PRBS
// generator. Resulting compare_err signal used to determine read data valid
// edge.
//***************************************************************************
generate
if (nCK_PER_CLK == 4) begin: cmp_err_4to1
always @ (posedge clk) begin
if (rst || new_cnt_dqs_r) begin
compare_err <= #TCQ 1'b0;
compare_err_r0 <= #TCQ 1'b0;
compare_err_f0 <= #TCQ 1'b0;
compare_err_r1 <= #TCQ 1'b0;
compare_err_f1 <= #TCQ 1'b0;
compare_err_r2 <= #TCQ 1'b0;
compare_err_f2 <= #TCQ 1'b0;
compare_err_r3 <= #TCQ 1'b0;
compare_err_f3 <= #TCQ 1'b0;
end else if (rd_valid_r2) begin
compare_err_r0 <= #TCQ (mux_rd_rise0_r3 != compare_data_rise0_r1);
compare_err_f0 <= #TCQ (mux_rd_fall0_r3 != compare_data_fall0_r1);
compare_err_r1 <= #TCQ (mux_rd_rise1_r3 != compare_data_rise1_r1);
compare_err_f1 <= #TCQ (mux_rd_fall1_r3 != compare_data_fall1_r1);
compare_err_r2 <= #TCQ (mux_rd_rise2_r3 != compare_data_rise2_r1);
compare_err_f2 <= #TCQ (mux_rd_fall2_r3 != compare_data_fall2_r1);
compare_err_r3 <= #TCQ (mux_rd_rise3_r3 != compare_data_rise3_r1);
compare_err_f3 <= #TCQ (mux_rd_fall3_r3 != compare_data_fall3_r1);
compare_err <= #TCQ (compare_err_r0 | compare_err_f0 |
compare_err_r1 | compare_err_f1 |
compare_err_r2 | compare_err_f2 |
compare_err_r3 | compare_err_f3);
end
end
end else begin: cmp_err_2to1
always @ (posedge clk) begin
if (rst || new_cnt_dqs_r) begin
compare_err <= #TCQ 1'b0;
compare_err_r0 <= #TCQ 1'b0;
compare_err_f0 <= #TCQ 1'b0;
compare_err_r1 <= #TCQ 1'b0;
compare_err_f1 <= #TCQ 1'b0;
end else if (rd_valid_r2) begin
compare_err_r0 <= #TCQ (mux_rd_rise0_r3 != compare_data_rise0_r1);
compare_err_f0 <= #TCQ (mux_rd_fall0_r3 != compare_data_fall0_r1);
compare_err_r1 <= #TCQ (mux_rd_rise1_r3 != compare_data_rise1_r1);
compare_err_f1 <= #TCQ (mux_rd_fall1_r3 != compare_data_fall1_r1);
compare_err <= #TCQ (compare_err_r0 | compare_err_f0 |
compare_err_r1 | compare_err_f1);
end
end
end
endgenerate
//***************************************************************************
// Decrement initial Phaser_IN fine delay value before proceeding with
// read calibration
//***************************************************************************
//***************************************************************************
// Demultiplexor to control Phaser_IN delay values
//***************************************************************************
// Read DQS
always @(posedge clk) begin
if (rst) begin
pi_en_stg2_f_timing <= #TCQ 'b0;
pi_stg2_f_incdec_timing <= #TCQ 'b0;
end else if (prbs_tap_en_r) begin
// Change only specified DQS
pi_en_stg2_f_timing <= #TCQ 1'b1;
pi_stg2_f_incdec_timing <= #TCQ prbs_tap_inc_r;
end else begin
pi_en_stg2_f_timing <= #TCQ 'b0;
pi_stg2_f_incdec_timing <= #TCQ 'b0;
end
end
// registered for timing
always @(posedge clk) begin
pi_en_stg2_f <= #TCQ pi_en_stg2_f_timing;
pi_stg2_f_incdec <= #TCQ pi_stg2_f_incdec_timing;
end
//***************************************************************************
// generate request to PHY_INIT logic to issue precharged. Required when
// calibration can take a long time (during which there are only constant
// reads present on this bus). In this case need to issue perioidic
// precharges to avoid tRAS violation. This signal must meet the following
// requirements: (1) only transition from 0->1 when prech is first needed,
// (2) stay at 1 and only transition 1->0 when RDLVL_PRECH_DONE asserted
//***************************************************************************
always @(posedge clk)
if (rst)
prbs_rdlvl_prech_req <= #TCQ 1'b0;
else
prbs_rdlvl_prech_req <= #TCQ prbs_prech_req_r;
//*****************************************************************
// keep track of edge tap counts found, and current capture clock
// tap count
//*****************************************************************
always @(posedge clk)
if (rst) begin
prbs_dqs_tap_cnt_r <= #TCQ 'b0;
rdlvl_cpt_tap_cnt <= #TCQ 'b0;
end else if (new_cnt_dqs_r) begin
prbs_dqs_tap_cnt_r <= #TCQ pi_counter_read_val;
rdlvl_cpt_tap_cnt <= #TCQ pi_counter_read_val;
end else if (prbs_tap_en_r) begin
if (prbs_tap_inc_r)
prbs_dqs_tap_cnt_r <= #TCQ prbs_dqs_tap_cnt_r + 1;
else if (prbs_dqs_tap_cnt_r != 'd0)
prbs_dqs_tap_cnt_r <= #TCQ prbs_dqs_tap_cnt_r - 1;
end
always @(posedge clk)
if (rst) begin
prbs_dec_tap_calc_plus_3 <= #TCQ 'b0;
prbs_dec_tap_calc_minus_3 <= #TCQ 'b0;
end else if (new_cnt_dqs_r) begin
prbs_dec_tap_calc_plus_3 <= #TCQ 'b000011;
prbs_dec_tap_calc_minus_3 <= #TCQ 'b111100;
end else begin
prbs_dec_tap_calc_plus_3 <= #TCQ (prbs_dqs_tap_cnt_r - rdlvl_cpt_tap_cnt + 3);
prbs_dec_tap_calc_minus_3 <= #TCQ (prbs_dqs_tap_cnt_r - rdlvl_cpt_tap_cnt - 3);
end
always @(posedge clk)
if (rst || new_cnt_dqs_r)
prbs_dqs_tap_limit_r <= #TCQ 1'b0;
else if (prbs_dqs_tap_cnt_r == 6'd63)
prbs_dqs_tap_limit_r <= #TCQ 1'b1;
else
prbs_dqs_tap_limit_r <= #TCQ 1'b0;
// Temp wire for timing.
// The following in the always block below causes timing issues
// due to DSP block inference
// 6*prbs_dqs_cnt_r.
// replacing this with two left shifts + one left shift to avoid
// DSP multiplier.
assign prbs_dqs_cnt_timing = {2'd0, prbs_dqs_cnt_r};
always @(posedge clk)
prbs_dqs_cnt_timing_r <= #TCQ prbs_dqs_cnt_timing;
// Storing DQS tap values at the end of each DQS read leveling
always @(posedge clk) begin
if (rst) begin
prbs_final_dqs_tap_cnt_r <= #TCQ 'b0;
end else if ((prbs_state_r == PRBS_NEXT_DQS) && (prbs_state_r1 != PRBS_NEXT_DQS)) begin
prbs_final_dqs_tap_cnt_r[(prbs_dqs_cnt_timing_r*6)+:6]
<= #TCQ prbs_dqs_tap_cnt_r;
end
end
//*****************************************************************
always @(posedge clk) begin
prbs_state_r1 <= #TCQ prbs_state_r;
prbs_rdlvl_start_r <= #TCQ prbs_rdlvl_start;
end
// Wait counter for wait states
always @(posedge clk)
if ((prbs_state_r == PRBS_NEW_DQS_WAIT) ||
(prbs_state_r == PRBS_INC_DQS_WAIT) ||
(prbs_state_r == PRBS_DEC_DQS_WAIT) ||
(prbs_state_r == FINE_PI_DEC_WAIT) ||
(prbs_state_r == FINE_PI_INC_WAIT) ||
(prbs_state_r == PRBS_NEW_DQS_PREWAIT))
wait_state_cnt_en_r <= #TCQ 1'b1;
else
wait_state_cnt_en_r <= #TCQ 1'b0;
always @(posedge clk)
if (!wait_state_cnt_en_r) begin
wait_state_cnt_r <= #TCQ 'b0;
cnt_wait_state <= #TCQ 1'b0;
end else begin
if (wait_state_cnt_r < 'd15) begin
wait_state_cnt_r <= #TCQ wait_state_cnt_r + 1;
cnt_wait_state <= #TCQ 1'b0;
end else begin
// Need to reset to 0 to handle the case when there are two
// different WAIT states back-to-back
wait_state_cnt_r <= #TCQ 'b0;
cnt_wait_state <= #TCQ 1'b1;
end
end
always @ (posedge clk)
err_chk_invalid <= #TCQ (wait_state_cnt_r < 'd14);
//*****************************************************************
// compare error checking per-bit
//****************************************************************
generate
genvar pb_i;
if (nCK_PER_CLK == 4) begin: cmp_err_pb_4to1
for(pb_i=0 ; pb_i<DRAM_WIDTH; pb_i=pb_i+1) begin
always @ (posedge clk) begin
//prevent error check during PI inc/dec and wait
if (rst || new_cnt_dqs_r || (prbs_state_r == FINE_PI_INC) || (prbs_state_r == FINE_PI_DEC) ||
(err_chk_invalid && ((prbs_state_r == FINE_PI_DEC_WAIT)||(prbs_state_r == FINE_PI_INC_WAIT))))
compare_err_pb[pb_i] <= #TCQ 1'b0;
else if (rd_valid_r2)
compare_err_pb[pb_i] <= #TCQ (mux_rd_rise0_r3[pb_i] != compare_data_rise0_r1[pb_i]) |
(mux_rd_fall0_r3[pb_i] != compare_data_fall0_r1[pb_i]) |
(mux_rd_rise1_r3[pb_i] != compare_data_rise1_r1[pb_i]) |
(mux_rd_fall1_r3[pb_i] != compare_data_fall1_r1[pb_i]) |
(mux_rd_rise2_r3[pb_i] != compare_data_rise2_r1[pb_i]) |
(mux_rd_fall2_r3[pb_i] != compare_data_fall2_r1[pb_i]) |
(mux_rd_rise3_r3[pb_i] != compare_data_rise3_r1[pb_i]) |
(mux_rd_fall3_r3[pb_i] != compare_data_fall3_r1[pb_i]) ;
end //always
end //for
end else begin: cmp_err_pb_2to1
for(pb_i=0 ; pb_i<DRAM_WIDTH; pb_i=pb_i+1) begin
always @ (posedge clk) begin
if (rst || new_cnt_dqs_r || (prbs_state_r == FINE_PI_INC) || (prbs_state_r == FINE_PI_DEC) ||
(err_chk_invalid && ((prbs_state_r == FINE_PI_DEC_WAIT)||(prbs_state_r == FINE_PI_INC_WAIT))))
compare_err_pb[pb_i] <= #TCQ 1'b0;
else if (rd_valid_r2)
compare_err_pb[pb_i] <= #TCQ (mux_rd_rise0_r3[pb_i] != compare_data_rise0_r1[pb_i]) |
(mux_rd_fall0_r3[pb_i] != compare_data_fall0_r1[pb_i]) |
(mux_rd_rise1_r3[pb_i] != compare_data_rise1_r1[pb_i]) |
(mux_rd_fall1_r3[pb_i] != compare_data_fall1_r1[pb_i]) ;
end //always
end //for
end //if
endgenerate
//checking all bit has error
always @ (posedge clk) begin
if(rst || new_cnt_dqs_r) begin
compare_err_pb_and <= #TCQ 1'b0;
end else begin
compare_err_pb_and <= #TCQ &compare_err_pb;
end
end
//generate stick error bit - left/right edge
generate
genvar pb_r;
for(pb_r=0; pb_r<DRAM_WIDTH; pb_r=pb_r+1) begin
always @ (posedge clk) begin
if((prbs_state_r == FINE_PI_INC) | (prbs_state_r == FINE_PI_DEC) |
(~cnt_wait_state && ((prbs_state_r == FINE_PI_INC_WAIT)|(prbs_state_r == FINE_PI_DEC_WAIT))))
compare_err_pb_latch_r[pb_r] <= #TCQ 1'b0;
else
compare_err_pb_latch_r[pb_r] <= #TCQ compare_err_pb[pb_r]? 1'b1:compare_err_pb_latch_r[pb_r];
end
end
endgenerate
//in stage 0, if left edge found, update ref_bit (one hot)
always @ (posedge clk) begin
if (rst | (prbs_state_r == PRBS_NEW_DQS_WAIT)) begin
ref_bit_per_bit <= #TCQ 'd0;
end else if ((prbs_state_r == FINE_PI_INC) && (stage_cnt=='b0)) begin
if(|left_edge_updated) ref_bit_per_bit <= #TCQ left_edge_updated;
end
end
//ref bit with samllest right edge
//if bit 1 and 3 are set to ref_bit_per_bit but bit 1 has smaller right edge, bit is selected as ref_bit
always @ (posedge clk) begin
if(rst | (prbs_state_r == PRBS_NEW_DQS_WAIT)) begin
bit_cnt <= #TCQ 'd0;
ref_right_edge <= #TCQ 6'h3f;
ref_bit <= #TCQ 'd0;
end else if ((prbs_state_r == FINE_CALC_TAPS_WAIT) && (stage_cnt == 'b0) && (bit_cnt < DRAM_WIDTH)) begin
bit_cnt <= #TCQ bit_cnt +'b1;
if ((ref_bit_per_bit[bit_cnt]==1'b1) && (right_edge_pb[bit_cnt*6+:6]<= ref_right_edge)) begin
ref_bit <= #TCQ bit_cnt;
ref_right_edge <= #TCQ right_edge_pb[bit_cnt*6+:6];
end
end
end
//pipe lining for reference bit left/right edge
always @ (posedge clk) begin
left_edge_ref <= #TCQ left_edge_pb[ref_bit*6+:6];
right_edge_ref <= #TCQ right_edge_pb[ref_bit*6+:6];
end
//left_edge/right_edge/left_loss/right_gain update
generate
genvar eg;
for(eg=0; eg<DRAM_WIDTH; eg = eg+1) begin
always @ (posedge clk) begin
if(rst | (prbs_state_r == PRBS_NEW_DQS_WAIT)) begin
match_flag_pb[eg*5+:5] <= #TCQ 5'h1f;
left_edge_pb[eg*6+:6] <= #TCQ 'b0;
right_edge_pb[eg*6+:6] <= #TCQ 6'h3f;
left_edge_found_pb[eg] <= #TCQ 1'b0;
right_edge_found_pb[eg] <= #TCQ 1'b0;
left_loss_pb[eg*6+:6] <= #TCQ 'b0;
right_gain_pb[eg*6+:6] <= #TCQ 'b0;
left_edge_updated[eg] <= #TCQ 'b0;
end else begin
if((prbs_state_r == FINE_PAT_COMPARE_PER_BIT) && (num_samples_done_r || compare_err_pb_and)) begin
//left edge is updated when match flag becomes 100000 (1 fail , 5 success)
if(match_flag_pb[eg*5+:5]==5'b10000 && compare_err_pb_latch_r[eg]==0) begin
left_edge_pb[eg*6+:6] <= #TCQ prbs_dqs_tap_cnt_r-4;
left_edge_found_pb[eg] <= #TCQ 1'b1; //used for update largest_left_edge
left_edge_updated[eg] <= #TCQ 1'b1;
//check the loss of bit - update only for left edge found
if(~left_edge_found_pb[eg])
left_loss_pb[eg*6+:6] <= #TCQ (left_edge_ref > prbs_dqs_tap_cnt_r - 4)? 'd0
: prbs_dqs_tap_cnt_r-4-left_edge_ref;
//right edge is updated when match flag becomes 000001 (5 success, 1 fail)
end else if (match_flag_pb[eg*5+:5]==5'b00000 && compare_err_pb_latch_r[eg]) begin
right_edge_pb[eg*6+:6] <= #TCQ prbs_dqs_tap_cnt_r-1;
right_edge_found_pb[eg] <= #TCQ 1'b1;
//check the gain of bit - update only for right edge found
if(~right_edge_found_pb[eg])
right_gain_pb[eg*6+:6] <= #TCQ (right_edge_ref > prbs_dqs_tap_cnt_r-1)?
((right_edge_pb[eg*6 +:6] > prbs_dqs_tap_cnt_r-1)? 0: prbs_dqs_tap_cnt_r-1- right_edge_pb[eg*6+:6]):
((right_edge_pb[eg*6+:6] > right_edge_ref)? 0 : right_edge_ref - right_edge_pb[eg*6+:6]);
//no right edge found
end else if (prbs_dqs_tap_cnt_r == 6'h3f && ~right_edge_found_pb[eg]) begin
right_edge_pb[eg*6+:6] <= #TCQ 6'h3f;
right_edge_found_pb[eg] <= #TCQ 1'b1;
//right edge at 63. gain = max(0, ref_bit_right_tap - prev_right_edge)
right_gain_pb[eg*6+:6] <= #TCQ (right_edge_ref > right_edge_pb[eg*6+:6])?
(right_edge_ref - right_edge_pb[eg*6+:6]) : 0;
end
//update match flag - shift and update
match_flag_pb[eg*5+:5] <= #TCQ {match_flag_pb[(eg*5)+:4],compare_err_pb_latch_r[eg]};
end else if (prbs_state_r == FINE_PI_DEC) begin
left_edge_found_pb[eg] <= #TCQ 1'b0;
right_edge_found_pb[eg] <= #TCQ 1'b0;
left_loss_pb[eg*6+:6] <= #TCQ 'b0;
right_gain_pb[eg*6+:6] <= #TCQ 'b0;
match_flag_pb[eg*5+:5] <= #TCQ 5'h1f; //new fix
end else if (prbs_state_r == FINE_PI_INC) begin
left_edge_updated[eg] <= #TCQ 'b0; //used only for update largest ref_bit and largest_left_edge
end
end
end //always
end //for
endgenerate
//update fine_delay according to loss/gain value per bit
generate
genvar f_pb;
for(f_pb=0; f_pb<DRAM_WIDTH; f_pb=f_pb+1) begin
always @ (posedge clk) begin
if(rst | prbs_state_r == PRBS_NEW_DQS_WAIT ) begin
fine_delay_incdec_pb[f_pb] <= #TCQ 1'b0;
end else if((prbs_state_r == FINE_CALC_TAPS_WAIT) && (bit_cnt == DRAM_WIDTH)) begin
if(stage_cnt == 'd0) fine_delay_incdec_pb[f_pb] <= #TCQ (f_pb==ref_bit)? 1'b0:1'b1; //only for initial stage
else if(stage_cnt == 'd1) fine_delay_incdec_pb[f_pb] <= #TCQ (right_gain_pb[f_pb*6+:6]>left_loss_pb[f_pb*6+:6])?1'b1:1'b0;
end
end
end
endgenerate
//fine inc stage (stage cnt 0,1,2), fine dec stage (stage cnt 3)
always @ (posedge clk) begin
if (rst)
fine_inc_stage <= #TCQ 'b1;
else
fine_inc_stage <= #TCQ (stage_cnt!='d3);
end
//*****************************************************************
always @(posedge clk)
if (rst) begin
prbs_dqs_cnt_r <= #TCQ 'b0;
prbs_tap_en_r <= #TCQ 1'b0;
prbs_tap_inc_r <= #TCQ 1'b0;
prbs_prech_req_r <= #TCQ 1'b0;
prbs_state_r <= #TCQ PRBS_IDLE;
prbs_found_1st_edge_r <= #TCQ 1'b0;
prbs_found_2nd_edge_r <= #TCQ 1'b0;
prbs_1st_edge_taps_r <= #TCQ 6'bxxxxxx;
prbs_inc_tap_cnt <= #TCQ 'b0;
prbs_dec_tap_cnt <= #TCQ 'b0;
new_cnt_dqs_r <= #TCQ 1'b0;
if (SIM_CAL_OPTION == "FAST_CAL")
prbs_rdlvl_done <= #TCQ 1'b1;
else
prbs_rdlvl_done <= #TCQ 1'b0;
prbs_2nd_edge_taps_r <= #TCQ 6'bxxxxxx;
prbs_last_byte_done <= #TCQ 1'b0;
prbs_tap_mod <= #TCQ 'd0;
reset_rd_addr <= #TCQ 'b0;
read_pause <= #TCQ 'b0;
fine_pi_dec_cnt <= #TCQ 'b0;
match_flag_and <= #TCQ 5'h1f;
stage_cnt <= #TCQ 2'b00;
right_edge_found <= #TCQ 1'b0;
largest_left_edge <= #TCQ 6'b000000;
smallest_right_edge <= #TCQ 6'b111111;
num_samples_done_ind <= #TCQ 'b0;
fine_delay_sel <= #TCQ 'b0;
fine_dly_error <= #TCQ 'b0;
end else begin
case (prbs_state_r)
PRBS_IDLE: begin
prbs_last_byte_done <= #TCQ 1'b0;
prbs_prech_req_r <= #TCQ 1'b0;
if (prbs_rdlvl_start && ~prbs_rdlvl_start_r) begin
if (SIM_CAL_OPTION == "SKIP_CAL" || SIM_CAL_OPTION == "FAST_CAL") begin
prbs_state_r <= #TCQ PRBS_DONE;
reset_rd_addr <= #TCQ 1'b1;
end else begin
new_cnt_dqs_r <= #TCQ 1'b1;
prbs_state_r <= #TCQ PRBS_NEW_DQS_WAIT;
fine_pi_dec_cnt <= #TCQ pi_counter_read_val;//.
end
end
end
// Wait for the new DQS group to change
// also gives time for the read data IN_FIFO to
// output the updated data for the new DQS group
PRBS_NEW_DQS_WAIT: begin
reset_rd_addr <= #TCQ 'b0;
prbs_last_byte_done <= #TCQ 1'b0;
prbs_prech_req_r <= #TCQ 1'b0;
//fine_inc_stage <= #TCQ 1'b1;
stage_cnt <= #TCQ 2'b0;
match_flag_and <= #TCQ 5'h1f;
if (cnt_wait_state) begin
new_cnt_dqs_r <= #TCQ 1'b0;
prbs_state_r <= #TCQ fine_calib? FINE_PI_DEC:PRBS_PAT_COMPARE;
end
end
// Check for presence of data eye edge. During this state, we
// sample the read data multiple times, and look for changes
// in the read data, specifically:
// 1. A change in the read data compared with the value of
// read data from the previous delay tap. This indicates
// that the most recent tap delay increment has moved us
// into either a new window, or moved/kept us in the
// transition/jitter region between windows. Note that this
// condition only needs to be checked for once, and for
// logistical purposes, we check this soon after entering
// this state (see comment in PRBS_PAT_COMPARE below for
// why this is done)
// 2. A change in the read data while we are in this state
// (i.e. in the absence of a tap delay increment). This
// indicates that we're close enough to a window edge that
// jitter will cause the read data to change even in the
// absence of a tap delay change
PRBS_PAT_COMPARE: begin
// Continue to sample read data and look for edges until the
// appropriate time interval (shorter for simulation-only,
// much, much longer for actual h/w) has elapsed
if (num_samples_done_r || compare_err) begin
if (prbs_dqs_tap_limit_r)
// Only one edge detected and ran out of taps since only one
// bit time worth of taps available for window detection. This
// can happen if at tap 0 DQS is in previous window which results
// in only left edge being detected. Or at tap 0 DQS is in the
// current window resulting in only right edge being detected.
// Depending on the frequency this case can also happen if at
// tap 0 DQS is in the left noise region resulting in only left
// edge being detected.
prbs_state_r <= #TCQ PRBS_CALC_TAPS_PRE;
else if (compare_err || (prbs_dqs_tap_cnt_r == 'd0)) begin
// Sticky bit - asserted after we encounter an edge, although
// the current edge may not be considered the "first edge" this
// just means we found at least one edge
prbs_found_1st_edge_r <= #TCQ 1'b1;
// Both edges of data valid window found:
// If we've found a second edge after a region of stability
// then we must have just passed the second ("right" edge of
// the window. Record this second_edge_taps = current tap-1,
// because we're one past the actual second edge tap, where
// the edge taps represent the extremes of the data valid
// window (i.e. smallest & largest taps where data still valid
if (prbs_found_1st_edge_r) begin
prbs_found_2nd_edge_r <= #TCQ 1'b1;
prbs_2nd_edge_taps_r <= #TCQ prbs_dqs_tap_cnt_r - 1;
prbs_state_r <= #TCQ PRBS_CALC_TAPS_PRE;
end else begin
// Otherwise, an edge was found (just not the "second" edge)
// Assuming DQS is in the correct window at tap 0 of Phaser IN
// fine tap. The first edge found is the right edge of the valid
// window and is the beginning of the jitter region hence done!
if (compare_err)
prbs_1st_edge_taps_r <= #TCQ prbs_dqs_tap_cnt_r + 1;
else
prbs_1st_edge_taps_r <= #TCQ 'd0;
prbs_inc_tap_cnt <= #TCQ rdlvl_cpt_tap_cnt - prbs_dqs_tap_cnt_r;
prbs_state_r <= #TCQ PRBS_INC_DQS;
end
end else begin
// Otherwise, if we haven't found an edge....
// If we still have taps left to use, then keep incrementing
if (prbs_found_1st_edge_r)
prbs_state_r <= #TCQ PRBS_INC_DQS;
else
prbs_state_r <= #TCQ PRBS_DEC_DQS;
end
end
end
// Increment Phaser_IN delay for DQS
PRBS_INC_DQS: begin
prbs_state_r <= #TCQ PRBS_INC_DQS_WAIT;
if (prbs_inc_tap_cnt > 'd0)
prbs_inc_tap_cnt <= #TCQ prbs_inc_tap_cnt - 1;
if (~prbs_dqs_tap_limit_r) begin
prbs_tap_en_r <= #TCQ 1'b1;
prbs_tap_inc_r <= #TCQ 1'b1;
end
end
// Wait for Phaser_In to settle, before checking again for an edge
PRBS_INC_DQS_WAIT: begin
prbs_tap_en_r <= #TCQ 1'b0;
prbs_tap_inc_r <= #TCQ 1'b0;
if (cnt_wait_state) begin
if (prbs_inc_tap_cnt > 'd0)
prbs_state_r <= #TCQ PRBS_INC_DQS;
else
prbs_state_r <= #TCQ PRBS_PAT_COMPARE;
end
end
// Calculate final value of Phaser_IN taps. At this point, one or both
// edges of data eye have been found, and/or all taps have been
// exhausted looking for the edges
// NOTE: The amount to be decrement by is calculated, not the
// absolute setting for DQS.
// CENTER compensation with shift by 1
PRBS_CALC_TAPS: begin
if (center_comp) begin
prbs_dec_tap_cnt <= #TCQ (dec_cnt[5] & dec_cnt[0])? 'd32: dec_cnt + pi_adj;
fine_dly_error <= #TCQ (dec_cnt[5] & dec_cnt[0])? 1'b1: fine_dly_error; //sticky bit
read_pause <= #TCQ 'b1;
prbs_state_r <= #TCQ PRBS_DEC_DQS;
end else begin //No center compensation
if (prbs_found_2nd_edge_r && prbs_found_1st_edge_r)
// Both edges detected
prbs_dec_tap_cnt
<= #TCQ ((prbs_2nd_edge_taps_r -
prbs_1st_edge_taps_r)>>1) + 1 + pi_adj;
else if (~prbs_found_2nd_edge_r && prbs_found_1st_edge_r)
// Only left edge detected
prbs_dec_tap_cnt
<= #TCQ ((prbs_dqs_tap_cnt_r - prbs_1st_edge_taps_r)>>1) + pi_adj;
else
// No edges detected
prbs_dec_tap_cnt
<= #TCQ (prbs_dqs_tap_cnt_r>>1) + pi_adj;
// Now use the value we just calculated to decrement CPT taps
// to the desired calibration point
read_pause <= #TCQ 'b1;
prbs_state_r <= #TCQ PRBS_DEC_DQS;
end
end
// decrement capture clock for final adjustment - center
// capture clock in middle of data eye. This adjustment will occur
// only when both the edges are found usign CPT taps. Must do this
// incrementally to avoid clock glitching (since CPT drives clock
// divider within each ISERDES)
PRBS_DEC_DQS: begin
prbs_tap_en_r <= #TCQ 1'b1;
prbs_tap_inc_r <= #TCQ 1'b0;
// once adjustment is complete, we're done with calibration for
// this DQS, repeat for next DQS
if (prbs_dec_tap_cnt > 'd0)
prbs_dec_tap_cnt <= #TCQ prbs_dec_tap_cnt - 1;
if (prbs_dec_tap_cnt == 6'b000001)
prbs_state_r <= #TCQ PRBS_NEXT_DQS;
else
prbs_state_r <= #TCQ PRBS_DEC_DQS_WAIT;
end
PRBS_DEC_DQS_WAIT: begin
prbs_tap_en_r <= #TCQ 1'b0;
prbs_tap_inc_r <= #TCQ 1'b0;
if (cnt_wait_state) begin
if (prbs_dec_tap_cnt > 'd0)
prbs_state_r <= #TCQ PRBS_DEC_DQS;
else
prbs_state_r <= #TCQ PRBS_PAT_COMPARE;
end
end
// Determine whether we're done, or have more DQS's to calibrate
// Also request precharge after every byte, as appropriate
PRBS_NEXT_DQS: begin
read_pause <= #TCQ 'b0;
reset_rd_addr <= #TCQ 'b1;
prbs_prech_req_r <= #TCQ 1'b1;
prbs_tap_en_r <= #TCQ 1'b0;
prbs_tap_inc_r <= #TCQ 1'b0;
// Prepare for another iteration with next DQS group
prbs_found_1st_edge_r <= #TCQ 1'b0;
prbs_found_2nd_edge_r <= #TCQ 1'b0;
prbs_1st_edge_taps_r <= #TCQ 'd0;
prbs_2nd_edge_taps_r <= #TCQ 'd0;
largest_left_edge <= #TCQ 6'b000000;
smallest_right_edge <= #TCQ 6'b111111;
if (prbs_dqs_cnt_r >= DQS_WIDTH-1) begin
prbs_last_byte_done <= #TCQ 1'b1;
end
// Wait until precharge that occurs in between calibration of
// DQS groups is finished
if (prech_done) begin
prbs_prech_req_r <= #TCQ 1'b0;
if (prbs_dqs_cnt_r >= DQS_WIDTH-1) begin
// All DQS groups done
prbs_state_r <= #TCQ PRBS_DONE;
end else begin
// Process next DQS group
new_cnt_dqs_r <= #TCQ 1'b1;
//fine_pi_dec_cnt <= #TCQ pi_counter_read_val;//.
prbs_dqs_cnt_r <= #TCQ prbs_dqs_cnt_r + 1;
prbs_state_r <= #TCQ PRBS_NEW_DQS_PREWAIT;
end
end
end
PRBS_NEW_DQS_PREWAIT: begin
if (cnt_wait_state) begin
prbs_state_r <= #TCQ PRBS_NEW_DQS_WAIT;
fine_pi_dec_cnt <= #TCQ pi_counter_read_val;//.
end
end
PRBS_CALC_TAPS_PRE:
begin
if(num_samples_done_r) begin
prbs_state_r <= #TCQ fine_calib? PRBS_NEXT_DQS:PRBS_CALC_TAPS_WAIT;
if(center_comp && ~fine_calib) begin
if(prbs_found_1st_edge_r) largest_left_edge <= #TCQ prbs_1st_edge_taps_r;
else largest_left_edge <= #TCQ 6'd0;
if(prbs_found_2nd_edge_r) smallest_right_edge <= #TCQ prbs_2nd_edge_taps_r;
else smallest_right_edge <= #TCQ 6'd63;
end
end
end
//wait for center compensation
PRBS_CALC_TAPS_WAIT:
begin
prbs_state_r <= #TCQ PRBS_CALC_TAPS;
end
//if it is fine_inc stage (first/second stage): dec to 0
//if it is fine_dec stage (third stage): dec to center
FINE_PI_DEC: begin
fine_delay_sel <= #TCQ 'b0;
if(fine_pi_dec_cnt > 0) begin
prbs_tap_en_r <= #TCQ 1'b1;
prbs_tap_inc_r <= #TCQ 1'b0;
fine_pi_dec_cnt <= #TCQ fine_pi_dec_cnt - 'd1;
end
prbs_state_r <= #TCQ FINE_PI_DEC_WAIT;
end
//wait for phaser_in tap decrement.
//if first/second stage is done, goes to FINE_PI_INC
//if last stage is done, goes to NEXT_DQS
FINE_PI_DEC_WAIT: begin
prbs_tap_en_r <= #TCQ 1'b0;
prbs_tap_inc_r <= #TCQ 1'b0;
if(cnt_wait_state) begin
if(fine_pi_dec_cnt >0)
prbs_state_r <= #TCQ FINE_PI_DEC;
else
if(fine_inc_stage)
// prbs_state_r <= #TCQ FINE_PI_INC; //for temp change
prbs_state_r <= #TCQ FINE_PAT_COMPARE_PER_BIT; //start from pi tap "0"
else
prbs_state_r <= #TCQ PRBS_CALC_TAPS_PRE; //finish the process and go to the next DQS
end
end
FINE_PI_INC: begin
if(|left_edge_updated) largest_left_edge <= #TCQ prbs_dqs_tap_cnt_r-4;
if(|right_edge_found_pb && ~right_edge_found) begin
smallest_right_edge <= #TCQ prbs_dqs_tap_cnt_r -1 ;
right_edge_found <= #TCQ 'b1;
end
//left_edge_found_pb <= #TCQ {DRAM_WIDTH{1'b0}};
prbs_state_r <= #TCQ FINE_PI_INC_WAIT;
if(~prbs_dqs_tap_limit_r) begin
prbs_tap_en_r <= #TCQ 1'b1;
prbs_tap_inc_r <= #TCQ 1'b1;
end
end
//wait for phase_in tap increment
//need to do pattern compare for every bit
FINE_PI_INC_WAIT: begin
prbs_tap_en_r <= #TCQ 1'b0;
prbs_tap_inc_r <= #TCQ 1'b0;
if (cnt_wait_state) begin
prbs_state_r <= #TCQ FINE_PAT_COMPARE_PER_BIT;
end
end
//compare per bit data and update flags,left/right edge
FINE_PAT_COMPARE_PER_BIT: begin
if(num_samples_done_r || compare_err_pb_and) begin
//update and_flag - shift and add
match_flag_and <= #TCQ {match_flag_and[3:0],compare_err_pb_and};
//if it is consecutive 5 passing taps followed by fail or tap limit (finish the search)
//don't go to fine_FINE_CALC_TAPS to prevent to skip whole stage
//Or if all right edge are found
if((match_flag_and == 5'b00000 && compare_err_pb_and && (prbs_dqs_tap_cnt_r > 5)) || prbs_dqs_tap_limit_r || (&right_edge_found_pb)) begin
prbs_state_r <= #TCQ FINE_CALC_TAPS;
//if all right edge are alined (all right edge found at the same time), update smallest right edge in here
//doesnt need to set right_edge_found to 1 since it is not used after this stage
if(!right_edge_found) smallest_right_edge <= #TCQ prbs_dqs_tap_cnt_r-1;
end else begin
prbs_state_r <= #TCQ FINE_PI_INC; //keep increase until all fail
end
num_samples_done_ind <= num_samples_done_r;
end
end
//for fine_inc stage, inc all fine delay
//for fine_dec stage, apply dec fine delay for specific bits (by calculating the loss/gain)
// put phaser_in taps to the center
FINE_CALC_TAPS: begin
if(num_samples_done_ind || num_samples_done_r) begin
num_samples_done_ind <= #TCQ 'b0; //indicate num_samples_done_r is set
right_edge_found <= #TCQ 1'b0; //reset right edge found
match_flag_and <= #TCQ 5'h1f; //reset match flag for all bits
prbs_state_r <= #TCQ FINE_CALC_TAPS_WAIT;
end
end
FINE_CALC_TAPS_WAIT: begin //wait for ROM read out
if(stage_cnt == 'd2) begin //last stage : back to center
if(center_comp) begin
fine_pi_dec_cnt <= #TCQ (dec_cnt[5]&dec_cnt[0])? 'd32: prbs_dqs_tap_cnt_r - smallest_right_edge + dec_cnt - 1 + pi_adj ; //going to the center value & shift by 1
fine_dly_error <= #TCQ (dec_cnt[5]&dec_cnt[0]) ? 1'b1: fine_dly_error;
end else begin
fine_pi_dec_cnt <= #TCQ prbs_dqs_tap_cnt_r - center_calc[6:1] - center_calc[0] + pi_adj; //going to the center value & shift left by 1
fine_dly_error <= #TCQ 1'b0;
end
end else begin
fine_pi_dec_cnt <= #TCQ prbs_dqs_tap_cnt_r;
end
if (bit_cnt == DRAM_WIDTH) begin
fine_delay_sel <= #TCQ 'b1;
stage_cnt <= #TCQ stage_cnt + 1;
prbs_state_r <= #TCQ FINE_PI_DEC;
end
end
// Done with this stage of calibration
PRBS_DONE: begin
prbs_prech_req_r <= #TCQ 1'b0;
prbs_last_byte_done <= #TCQ 1'b0;
prbs_rdlvl_done <= #TCQ 1'b1;
reset_rd_addr <= #TCQ 1'b0;
end
endcase
end
//ROM generation for dec counter
always @ (largest_left_edge or smallest_right_edge) begin
case ({largest_left_edge, smallest_right_edge})
12'd0 : mem_out_dec = 6'b111111;
12'd1 : mem_out_dec = 6'b111111;
12'd2 : mem_out_dec = 6'b111111;
12'd3 : mem_out_dec = 6'b111111;
12'd4 : mem_out_dec = 6'b111111;
12'd5 : mem_out_dec = 6'b111111;
12'd6 : mem_out_dec = 6'b000100;
12'd7 : mem_out_dec = 6'b000101;
12'd8 : mem_out_dec = 6'b000101;
12'd9 : mem_out_dec = 6'b000110;
12'd10 : mem_out_dec = 6'b000110;
12'd11 : mem_out_dec = 6'b000111;
12'd12 : mem_out_dec = 6'b001000;
12'd13 : mem_out_dec = 6'b001000;
12'd14 : mem_out_dec = 6'b001001;
12'd15 : mem_out_dec = 6'b001010;
12'd16 : mem_out_dec = 6'b001010;
12'd17 : mem_out_dec = 6'b001011;
12'd18 : mem_out_dec = 6'b001011;
12'd19 : mem_out_dec = 6'b001100;
12'd20 : mem_out_dec = 6'b001100;
12'd21 : mem_out_dec = 6'b001100;
12'd22 : mem_out_dec = 6'b001100;
12'd23 : mem_out_dec = 6'b001101;
12'd24 : mem_out_dec = 6'b001100;
12'd25 : mem_out_dec = 6'b001100;
12'd26 : mem_out_dec = 6'b001101;
12'd27 : mem_out_dec = 6'b001110;
12'd28 : mem_out_dec = 6'b001110;
12'd29 : mem_out_dec = 6'b001111;
12'd30 : mem_out_dec = 6'b010000;
12'd31 : mem_out_dec = 6'b010001;
12'd32 : mem_out_dec = 6'b010001;
12'd33 : mem_out_dec = 6'b010010;
12'd34 : mem_out_dec = 6'b010010;
12'd35 : mem_out_dec = 6'b010010;
12'd36 : mem_out_dec = 6'b010011;
12'd37 : mem_out_dec = 6'b010100;
12'd38 : mem_out_dec = 6'b010100;
12'd39 : mem_out_dec = 6'b010101;
12'd40 : mem_out_dec = 6'b010101;
12'd41 : mem_out_dec = 6'b010110;
12'd42 : mem_out_dec = 6'b010110;
12'd43 : mem_out_dec = 6'b010111;
12'd44 : mem_out_dec = 6'b011000;
12'd45 : mem_out_dec = 6'b011001;
12'd46 : mem_out_dec = 6'b011001;
12'd47 : mem_out_dec = 6'b011010;
12'd48 : mem_out_dec = 6'b011010;
12'd49 : mem_out_dec = 6'b011011;
12'd50 : mem_out_dec = 6'b011011;
12'd51 : mem_out_dec = 6'b011100;
12'd52 : mem_out_dec = 6'b011100;
12'd53 : mem_out_dec = 6'b011100;
12'd54 : mem_out_dec = 6'b011100;
12'd55 : mem_out_dec = 6'b011100;
12'd56 : mem_out_dec = 6'b011100;
12'd57 : mem_out_dec = 6'b011100;
12'd58 : mem_out_dec = 6'b011100;
12'd59 : mem_out_dec = 6'b011101;
12'd60 : mem_out_dec = 6'b011110;
12'd61 : mem_out_dec = 6'b011111;
12'd62 : mem_out_dec = 6'b100000;
12'd63 : mem_out_dec = 6'b100000;
12'd64 : mem_out_dec = 6'b111111;
12'd65 : mem_out_dec = 6'b111111;
12'd66 : mem_out_dec = 6'b111111;
12'd67 : mem_out_dec = 6'b111111;
12'd68 : mem_out_dec = 6'b111111;
12'd69 : mem_out_dec = 6'b111111;
12'd70 : mem_out_dec = 6'b111111;
12'd71 : mem_out_dec = 6'b000100;
12'd72 : mem_out_dec = 6'b000100;
12'd73 : mem_out_dec = 6'b000101;
12'd74 : mem_out_dec = 6'b000110;
12'd75 : mem_out_dec = 6'b000111;
12'd76 : mem_out_dec = 6'b000111;
12'd77 : mem_out_dec = 6'b001000;
12'd78 : mem_out_dec = 6'b001001;
12'd79 : mem_out_dec = 6'b001001;
12'd80 : mem_out_dec = 6'b001010;
12'd81 : mem_out_dec = 6'b001010;
12'd82 : mem_out_dec = 6'b001011;
12'd83 : mem_out_dec = 6'b001011;
12'd84 : mem_out_dec = 6'b001011;
12'd85 : mem_out_dec = 6'b001011;
12'd86 : mem_out_dec = 6'b001011;
12'd87 : mem_out_dec = 6'b001100;
12'd88 : mem_out_dec = 6'b001011;
12'd89 : mem_out_dec = 6'b001100;
12'd90 : mem_out_dec = 6'b001100;
12'd91 : mem_out_dec = 6'b001101;
12'd92 : mem_out_dec = 6'b001110;
12'd93 : mem_out_dec = 6'b001111;
12'd94 : mem_out_dec = 6'b001111;
12'd95 : mem_out_dec = 6'b010000;
12'd96 : mem_out_dec = 6'b010001;
12'd97 : mem_out_dec = 6'b010001;
12'd98 : mem_out_dec = 6'b010010;
12'd99 : mem_out_dec = 6'b010010;
12'd100 : mem_out_dec = 6'b010011;
12'd101 : mem_out_dec = 6'b010011;
12'd102 : mem_out_dec = 6'b010100;
12'd103 : mem_out_dec = 6'b010100;
12'd104 : mem_out_dec = 6'b010100;
12'd105 : mem_out_dec = 6'b010101;
12'd106 : mem_out_dec = 6'b010110;
12'd107 : mem_out_dec = 6'b010111;
12'd108 : mem_out_dec = 6'b010111;
12'd109 : mem_out_dec = 6'b011000;
12'd110 : mem_out_dec = 6'b011001;
12'd111 : mem_out_dec = 6'b011001;
12'd112 : mem_out_dec = 6'b011010;
12'd113 : mem_out_dec = 6'b011010;
12'd114 : mem_out_dec = 6'b011011;
12'd115 : mem_out_dec = 6'b011011;
12'd116 : mem_out_dec = 6'b011011;
12'd117 : mem_out_dec = 6'b011011;
12'd118 : mem_out_dec = 6'b011011;
12'd119 : mem_out_dec = 6'b011011;
12'd120 : mem_out_dec = 6'b011011;
12'd121 : mem_out_dec = 6'b011011;
12'd122 : mem_out_dec = 6'b011100;
12'd123 : mem_out_dec = 6'b011101;
12'd124 : mem_out_dec = 6'b011110;
12'd125 : mem_out_dec = 6'b011110;
12'd126 : mem_out_dec = 6'b011111;
12'd127 : mem_out_dec = 6'b100000;
12'd128 : mem_out_dec = 6'b111111;
12'd129 : mem_out_dec = 6'b111111;
12'd130 : mem_out_dec = 6'b111111;
12'd131 : mem_out_dec = 6'b111111;
12'd132 : mem_out_dec = 6'b111111;
12'd133 : mem_out_dec = 6'b111111;
12'd134 : mem_out_dec = 6'b111111;
12'd135 : mem_out_dec = 6'b111111;
12'd136 : mem_out_dec = 6'b000100;
12'd137 : mem_out_dec = 6'b000101;
12'd138 : mem_out_dec = 6'b000101;
12'd139 : mem_out_dec = 6'b000110;
12'd140 : mem_out_dec = 6'b000110;
12'd141 : mem_out_dec = 6'b000111;
12'd142 : mem_out_dec = 6'b001000;
12'd143 : mem_out_dec = 6'b001001;
12'd144 : mem_out_dec = 6'b001001;
12'd145 : mem_out_dec = 6'b001010;
12'd146 : mem_out_dec = 6'b001010;
12'd147 : mem_out_dec = 6'b001010;
12'd148 : mem_out_dec = 6'b001010;
12'd149 : mem_out_dec = 6'b001010;
12'd150 : mem_out_dec = 6'b001010;
12'd151 : mem_out_dec = 6'b001011;
12'd152 : mem_out_dec = 6'b001010;
12'd153 : mem_out_dec = 6'b001011;
12'd154 : mem_out_dec = 6'b001100;
12'd155 : mem_out_dec = 6'b001101;
12'd156 : mem_out_dec = 6'b001101;
12'd157 : mem_out_dec = 6'b001110;
12'd158 : mem_out_dec = 6'b001111;
12'd159 : mem_out_dec = 6'b010000;
12'd160 : mem_out_dec = 6'b010000;
12'd161 : mem_out_dec = 6'b010001;
12'd162 : mem_out_dec = 6'b010001;
12'd163 : mem_out_dec = 6'b010010;
12'd164 : mem_out_dec = 6'b010010;
12'd165 : mem_out_dec = 6'b010011;
12'd166 : mem_out_dec = 6'b010011;
12'd167 : mem_out_dec = 6'b010100;
12'd168 : mem_out_dec = 6'b010100;
12'd169 : mem_out_dec = 6'b010101;
12'd170 : mem_out_dec = 6'b010101;
12'd171 : mem_out_dec = 6'b010110;
12'd172 : mem_out_dec = 6'b010111;
12'd173 : mem_out_dec = 6'b010111;
12'd174 : mem_out_dec = 6'b011000;
12'd175 : mem_out_dec = 6'b011001;
12'd176 : mem_out_dec = 6'b011001;
12'd177 : mem_out_dec = 6'b011010;
12'd178 : mem_out_dec = 6'b011010;
12'd179 : mem_out_dec = 6'b011010;
12'd180 : mem_out_dec = 6'b011010;
12'd181 : mem_out_dec = 6'b011010;
12'd182 : mem_out_dec = 6'b011010;
12'd183 : mem_out_dec = 6'b011010;
12'd184 : mem_out_dec = 6'b011010;
12'd185 : mem_out_dec = 6'b011011;
12'd186 : mem_out_dec = 6'b011100;
12'd187 : mem_out_dec = 6'b011100;
12'd188 : mem_out_dec = 6'b011101;
12'd189 : mem_out_dec = 6'b011110;
12'd190 : mem_out_dec = 6'b011111;
12'd191 : mem_out_dec = 6'b100000;
12'd192 : mem_out_dec = 6'b111111;
12'd193 : mem_out_dec = 6'b111111;
12'd194 : mem_out_dec = 6'b111111;
12'd195 : mem_out_dec = 6'b111111;
12'd196 : mem_out_dec = 6'b111111;
12'd197 : mem_out_dec = 6'b111111;
12'd198 : mem_out_dec = 6'b111111;
12'd199 : mem_out_dec = 6'b111111;
12'd200 : mem_out_dec = 6'b111111;
12'd201 : mem_out_dec = 6'b000100;
12'd202 : mem_out_dec = 6'b000100;
12'd203 : mem_out_dec = 6'b000101;
12'd204 : mem_out_dec = 6'b000110;
12'd205 : mem_out_dec = 6'b000111;
12'd206 : mem_out_dec = 6'b001000;
12'd207 : mem_out_dec = 6'b001000;
12'd208 : mem_out_dec = 6'b001001;
12'd209 : mem_out_dec = 6'b001001;
12'd210 : mem_out_dec = 6'b001001;
12'd211 : mem_out_dec = 6'b001001;
12'd212 : mem_out_dec = 6'b001001;
12'd213 : mem_out_dec = 6'b001001;
12'd214 : mem_out_dec = 6'b001001;
12'd215 : mem_out_dec = 6'b001010;
12'd216 : mem_out_dec = 6'b001010;
12'd217 : mem_out_dec = 6'b001011;
12'd218 : mem_out_dec = 6'b001011;
12'd219 : mem_out_dec = 6'b001100;
12'd220 : mem_out_dec = 6'b001101;
12'd221 : mem_out_dec = 6'b001110;
12'd222 : mem_out_dec = 6'b001111;
12'd223 : mem_out_dec = 6'b001111;
12'd224 : mem_out_dec = 6'b010000;
12'd225 : mem_out_dec = 6'b010000;
12'd226 : mem_out_dec = 6'b010001;
12'd227 : mem_out_dec = 6'b010001;
12'd228 : mem_out_dec = 6'b010010;
12'd229 : mem_out_dec = 6'b010010;
12'd230 : mem_out_dec = 6'b010011;
12'd231 : mem_out_dec = 6'b010011;
12'd232 : mem_out_dec = 6'b010011;
12'd233 : mem_out_dec = 6'b010100;
12'd234 : mem_out_dec = 6'b010100;
12'd235 : mem_out_dec = 6'b010101;
12'd236 : mem_out_dec = 6'b010110;
12'd237 : mem_out_dec = 6'b010111;
12'd238 : mem_out_dec = 6'b011000;
12'd239 : mem_out_dec = 6'b011000;
12'd240 : mem_out_dec = 6'b011001;
12'd241 : mem_out_dec = 6'b011001;
12'd242 : mem_out_dec = 6'b011001;
12'd243 : mem_out_dec = 6'b011001;
12'd244 : mem_out_dec = 6'b011001;
12'd245 : mem_out_dec = 6'b011001;
12'd246 : mem_out_dec = 6'b011001;
12'd247 : mem_out_dec = 6'b011001;
12'd248 : mem_out_dec = 6'b011010;
12'd249 : mem_out_dec = 6'b011010;
12'd250 : mem_out_dec = 6'b011011;
12'd251 : mem_out_dec = 6'b011100;
12'd252 : mem_out_dec = 6'b011101;
12'd253 : mem_out_dec = 6'b011110;
12'd254 : mem_out_dec = 6'b011110;
12'd255 : mem_out_dec = 6'b011111;
12'd256 : mem_out_dec = 6'b111111;
12'd257 : mem_out_dec = 6'b111111;
12'd258 : mem_out_dec = 6'b111111;
12'd259 : mem_out_dec = 6'b111111;
12'd260 : mem_out_dec = 6'b111111;
12'd261 : mem_out_dec = 6'b111111;
12'd262 : mem_out_dec = 6'b111111;
12'd263 : mem_out_dec = 6'b111111;
12'd264 : mem_out_dec = 6'b111111;
12'd265 : mem_out_dec = 6'b111111;
12'd266 : mem_out_dec = 6'b000100;
12'd267 : mem_out_dec = 6'b000101;
12'd268 : mem_out_dec = 6'b000110;
12'd269 : mem_out_dec = 6'b000110;
12'd270 : mem_out_dec = 6'b000111;
12'd271 : mem_out_dec = 6'b001000;
12'd272 : mem_out_dec = 6'b001000;
12'd273 : mem_out_dec = 6'b001000;
12'd274 : mem_out_dec = 6'b001000;
12'd275 : mem_out_dec = 6'b001000;
12'd276 : mem_out_dec = 6'b001000;
12'd277 : mem_out_dec = 6'b001000;
12'd278 : mem_out_dec = 6'b001000;
12'd279 : mem_out_dec = 6'b001001;
12'd280 : mem_out_dec = 6'b001001;
12'd281 : mem_out_dec = 6'b001010;
12'd282 : mem_out_dec = 6'b001011;
12'd283 : mem_out_dec = 6'b001100;
12'd284 : mem_out_dec = 6'b001101;
12'd285 : mem_out_dec = 6'b001101;
12'd286 : mem_out_dec = 6'b001110;
12'd287 : mem_out_dec = 6'b001111;
12'd288 : mem_out_dec = 6'b001111;
12'd289 : mem_out_dec = 6'b010000;
12'd290 : mem_out_dec = 6'b010000;
12'd291 : mem_out_dec = 6'b010001;
12'd292 : mem_out_dec = 6'b010001;
12'd293 : mem_out_dec = 6'b010010;
12'd294 : mem_out_dec = 6'b010010;
12'd295 : mem_out_dec = 6'b010011;
12'd296 : mem_out_dec = 6'b010010;
12'd297 : mem_out_dec = 6'b010011;
12'd298 : mem_out_dec = 6'b010100;
12'd299 : mem_out_dec = 6'b010101;
12'd300 : mem_out_dec = 6'b010110;
12'd301 : mem_out_dec = 6'b010110;
12'd302 : mem_out_dec = 6'b010111;
12'd303 : mem_out_dec = 6'b011000;
12'd304 : mem_out_dec = 6'b011000;
12'd305 : mem_out_dec = 6'b011000;
12'd306 : mem_out_dec = 6'b011000;
12'd307 : mem_out_dec = 6'b011000;
12'd308 : mem_out_dec = 6'b011000;
12'd309 : mem_out_dec = 6'b011000;
12'd310 : mem_out_dec = 6'b011000;
12'd311 : mem_out_dec = 6'b011001;
12'd312 : mem_out_dec = 6'b011001;
12'd313 : mem_out_dec = 6'b011010;
12'd314 : mem_out_dec = 6'b011011;
12'd315 : mem_out_dec = 6'b011100;
12'd316 : mem_out_dec = 6'b011100;
12'd317 : mem_out_dec = 6'b011101;
12'd318 : mem_out_dec = 6'b011110;
12'd319 : mem_out_dec = 6'b011111;
12'd320 : mem_out_dec = 6'b111111;
12'd321 : mem_out_dec = 6'b111111;
12'd322 : mem_out_dec = 6'b111111;
12'd323 : mem_out_dec = 6'b111111;
12'd324 : mem_out_dec = 6'b111111;
12'd325 : mem_out_dec = 6'b111111;
12'd326 : mem_out_dec = 6'b111111;
12'd327 : mem_out_dec = 6'b111111;
12'd328 : mem_out_dec = 6'b111111;
12'd329 : mem_out_dec = 6'b111111;
12'd330 : mem_out_dec = 6'b111111;
12'd331 : mem_out_dec = 6'b000100;
12'd332 : mem_out_dec = 6'b000101;
12'd333 : mem_out_dec = 6'b000110;
12'd334 : mem_out_dec = 6'b000111;
12'd335 : mem_out_dec = 6'b001000;
12'd336 : mem_out_dec = 6'b000111;
12'd337 : mem_out_dec = 6'b000111;
12'd338 : mem_out_dec = 6'b000111;
12'd339 : mem_out_dec = 6'b000111;
12'd340 : mem_out_dec = 6'b000111;
12'd341 : mem_out_dec = 6'b000111;
12'd342 : mem_out_dec = 6'b001000;
12'd343 : mem_out_dec = 6'b001001;
12'd344 : mem_out_dec = 6'b001001;
12'd345 : mem_out_dec = 6'b001010;
12'd346 : mem_out_dec = 6'b001011;
12'd347 : mem_out_dec = 6'b001011;
12'd348 : mem_out_dec = 6'b001100;
12'd349 : mem_out_dec = 6'b001101;
12'd350 : mem_out_dec = 6'b001110;
12'd351 : mem_out_dec = 6'b001110;
12'd352 : mem_out_dec = 6'b001111;
12'd353 : mem_out_dec = 6'b001111;
12'd354 : mem_out_dec = 6'b010000;
12'd355 : mem_out_dec = 6'b010000;
12'd356 : mem_out_dec = 6'b010001;
12'd357 : mem_out_dec = 6'b010001;
12'd358 : mem_out_dec = 6'b010001;
12'd359 : mem_out_dec = 6'b010010;
12'd360 : mem_out_dec = 6'b010010;
12'd361 : mem_out_dec = 6'b010011;
12'd362 : mem_out_dec = 6'b010100;
12'd363 : mem_out_dec = 6'b010100;
12'd364 : mem_out_dec = 6'b010101;
12'd365 : mem_out_dec = 6'b010110;
12'd366 : mem_out_dec = 6'b010111;
12'd367 : mem_out_dec = 6'b011000;
12'd368 : mem_out_dec = 6'b010111;
12'd369 : mem_out_dec = 6'b010111;
12'd370 : mem_out_dec = 6'b010111;
12'd371 : mem_out_dec = 6'b010111;
12'd372 : mem_out_dec = 6'b010111;
12'd373 : mem_out_dec = 6'b010111;
12'd374 : mem_out_dec = 6'b011000;
12'd375 : mem_out_dec = 6'b011001;
12'd376 : mem_out_dec = 6'b011001;
12'd377 : mem_out_dec = 6'b011010;
12'd378 : mem_out_dec = 6'b011010;
12'd379 : mem_out_dec = 6'b011011;
12'd380 : mem_out_dec = 6'b011100;
12'd381 : mem_out_dec = 6'b011101;
12'd382 : mem_out_dec = 6'b011101;
12'd383 : mem_out_dec = 6'b011110;
12'd384 : mem_out_dec = 6'b111111;
12'd385 : mem_out_dec = 6'b111111;
12'd386 : mem_out_dec = 6'b111111;
12'd387 : mem_out_dec = 6'b111111;
12'd388 : mem_out_dec = 6'b111111;
12'd389 : mem_out_dec = 6'b111111;
12'd390 : mem_out_dec = 6'b111111;
12'd391 : mem_out_dec = 6'b111111;
12'd392 : mem_out_dec = 6'b111111;
12'd393 : mem_out_dec = 6'b111111;
12'd394 : mem_out_dec = 6'b111111;
12'd395 : mem_out_dec = 6'b111111;
12'd396 : mem_out_dec = 6'b000101;
12'd397 : mem_out_dec = 6'b000110;
12'd398 : mem_out_dec = 6'b000110;
12'd399 : mem_out_dec = 6'b000111;
12'd400 : mem_out_dec = 6'b000110;
12'd401 : mem_out_dec = 6'b000110;
12'd402 : mem_out_dec = 6'b000110;
12'd403 : mem_out_dec = 6'b000110;
12'd404 : mem_out_dec = 6'b000110;
12'd405 : mem_out_dec = 6'b000111;
12'd406 : mem_out_dec = 6'b001000;
12'd407 : mem_out_dec = 6'b001000;
12'd408 : mem_out_dec = 6'b001001;
12'd409 : mem_out_dec = 6'b001001;
12'd410 : mem_out_dec = 6'b001010;
12'd411 : mem_out_dec = 6'b001011;
12'd412 : mem_out_dec = 6'b001100;
12'd413 : mem_out_dec = 6'b001100;
12'd414 : mem_out_dec = 6'b001101;
12'd415 : mem_out_dec = 6'b001110;
12'd416 : mem_out_dec = 6'b001110;
12'd417 : mem_out_dec = 6'b001111;
12'd418 : mem_out_dec = 6'b001111;
12'd419 : mem_out_dec = 6'b010000;
12'd420 : mem_out_dec = 6'b010000;
12'd421 : mem_out_dec = 6'b010000;
12'd422 : mem_out_dec = 6'b010001;
12'd423 : mem_out_dec = 6'b010001;
12'd424 : mem_out_dec = 6'b010010;
12'd425 : mem_out_dec = 6'b010011;
12'd426 : mem_out_dec = 6'b010011;
12'd427 : mem_out_dec = 6'b010100;
12'd428 : mem_out_dec = 6'b010101;
12'd429 : mem_out_dec = 6'b010110;
12'd430 : mem_out_dec = 6'b010111;
12'd431 : mem_out_dec = 6'b010111;
12'd432 : mem_out_dec = 6'b010110;
12'd433 : mem_out_dec = 6'b010110;
12'd434 : mem_out_dec = 6'b010110;
12'd435 : mem_out_dec = 6'b010110;
12'd436 : mem_out_dec = 6'b010110;
12'd437 : mem_out_dec = 6'b010111;
12'd438 : mem_out_dec = 6'b010111;
12'd439 : mem_out_dec = 6'b011000;
12'd440 : mem_out_dec = 6'b011001;
12'd441 : mem_out_dec = 6'b011001;
12'd442 : mem_out_dec = 6'b011010;
12'd443 : mem_out_dec = 6'b011011;
12'd444 : mem_out_dec = 6'b011011;
12'd445 : mem_out_dec = 6'b011100;
12'd446 : mem_out_dec = 6'b011101;
12'd447 : mem_out_dec = 6'b011110;
12'd448 : mem_out_dec = 6'b111111;
12'd449 : mem_out_dec = 6'b111111;
12'd450 : mem_out_dec = 6'b111111;
12'd451 : mem_out_dec = 6'b111111;
12'd452 : mem_out_dec = 6'b111111;
12'd453 : mem_out_dec = 6'b111111;
12'd454 : mem_out_dec = 6'b111111;
12'd455 : mem_out_dec = 6'b111111;
12'd456 : mem_out_dec = 6'b111111;
12'd457 : mem_out_dec = 6'b111111;
12'd458 : mem_out_dec = 6'b111111;
12'd459 : mem_out_dec = 6'b111111;
12'd460 : mem_out_dec = 6'b111111;
12'd461 : mem_out_dec = 6'b000101;
12'd462 : mem_out_dec = 6'b000110;
12'd463 : mem_out_dec = 6'b000110;
12'd464 : mem_out_dec = 6'b000110;
12'd465 : mem_out_dec = 6'b000110;
12'd466 : mem_out_dec = 6'b000110;
12'd467 : mem_out_dec = 6'b000110;
12'd468 : mem_out_dec = 6'b000110;
12'd469 : mem_out_dec = 6'b000111;
12'd470 : mem_out_dec = 6'b000111;
12'd471 : mem_out_dec = 6'b001000;
12'd472 : mem_out_dec = 6'b001000;
12'd473 : mem_out_dec = 6'b001001;
12'd474 : mem_out_dec = 6'b001010;
12'd475 : mem_out_dec = 6'b001011;
12'd476 : mem_out_dec = 6'b001011;
12'd477 : mem_out_dec = 6'b001100;
12'd478 : mem_out_dec = 6'b001101;
12'd479 : mem_out_dec = 6'b001110;
12'd480 : mem_out_dec = 6'b001110;
12'd481 : mem_out_dec = 6'b001110;
12'd482 : mem_out_dec = 6'b001111;
12'd483 : mem_out_dec = 6'b001111;
12'd484 : mem_out_dec = 6'b010000;
12'd485 : mem_out_dec = 6'b010000;
12'd486 : mem_out_dec = 6'b010000;
12'd487 : mem_out_dec = 6'b010001;
12'd488 : mem_out_dec = 6'b010001;
12'd489 : mem_out_dec = 6'b010010;
12'd490 : mem_out_dec = 6'b010011;
12'd491 : mem_out_dec = 6'b010100;
12'd492 : mem_out_dec = 6'b010101;
12'd493 : mem_out_dec = 6'b010101;
12'd494 : mem_out_dec = 6'b010110;
12'd495 : mem_out_dec = 6'b010110;
12'd496 : mem_out_dec = 6'b010110;
12'd497 : mem_out_dec = 6'b010110;
12'd498 : mem_out_dec = 6'b010101;
12'd499 : mem_out_dec = 6'b010101;
12'd500 : mem_out_dec = 6'b010110;
12'd501 : mem_out_dec = 6'b010111;
12'd502 : mem_out_dec = 6'b010111;
12'd503 : mem_out_dec = 6'b011000;
12'd504 : mem_out_dec = 6'b011000;
12'd505 : mem_out_dec = 6'b011001;
12'd506 : mem_out_dec = 6'b011010;
12'd507 : mem_out_dec = 6'b011010;
12'd508 : mem_out_dec = 6'b011011;
12'd509 : mem_out_dec = 6'b011100;
12'd510 : mem_out_dec = 6'b011101;
12'd511 : mem_out_dec = 6'b011101;
12'd512 : mem_out_dec = 6'b111111;
12'd513 : mem_out_dec = 6'b111111;
12'd514 : mem_out_dec = 6'b111111;
12'd515 : mem_out_dec = 6'b111111;
12'd516 : mem_out_dec = 6'b111111;
12'd517 : mem_out_dec = 6'b111111;
12'd518 : mem_out_dec = 6'b111111;
12'd519 : mem_out_dec = 6'b111111;
12'd520 : mem_out_dec = 6'b111111;
12'd521 : mem_out_dec = 6'b111111;
12'd522 : mem_out_dec = 6'b111111;
12'd523 : mem_out_dec = 6'b111111;
12'd524 : mem_out_dec = 6'b111111;
12'd525 : mem_out_dec = 6'b111111;
12'd526 : mem_out_dec = 6'b000100;
12'd527 : mem_out_dec = 6'b000101;
12'd528 : mem_out_dec = 6'b000100;
12'd529 : mem_out_dec = 6'b000100;
12'd530 : mem_out_dec = 6'b000100;
12'd531 : mem_out_dec = 6'b000101;
12'd532 : mem_out_dec = 6'b000101;
12'd533 : mem_out_dec = 6'b000110;
12'd534 : mem_out_dec = 6'b000111;
12'd535 : mem_out_dec = 6'b000111;
12'd536 : mem_out_dec = 6'b000111;
12'd537 : mem_out_dec = 6'b001000;
12'd538 : mem_out_dec = 6'b001001;
12'd539 : mem_out_dec = 6'b001010;
12'd540 : mem_out_dec = 6'b001011;
12'd541 : mem_out_dec = 6'b001011;
12'd542 : mem_out_dec = 6'b001100;
12'd543 : mem_out_dec = 6'b001101;
12'd544 : mem_out_dec = 6'b001101;
12'd545 : mem_out_dec = 6'b001101;
12'd546 : mem_out_dec = 6'b001110;
12'd547 : mem_out_dec = 6'b001110;
12'd548 : mem_out_dec = 6'b001110;
12'd549 : mem_out_dec = 6'b001111;
12'd550 : mem_out_dec = 6'b010000;
12'd551 : mem_out_dec = 6'b010000;
12'd552 : mem_out_dec = 6'b010001;
12'd553 : mem_out_dec = 6'b010001;
12'd554 : mem_out_dec = 6'b010010;
12'd555 : mem_out_dec = 6'b010010;
12'd556 : mem_out_dec = 6'b010011;
12'd557 : mem_out_dec = 6'b010100;
12'd558 : mem_out_dec = 6'b010100;
12'd559 : mem_out_dec = 6'b010100;
12'd560 : mem_out_dec = 6'b010100;
12'd561 : mem_out_dec = 6'b010100;
12'd562 : mem_out_dec = 6'b010100;
12'd563 : mem_out_dec = 6'b010101;
12'd564 : mem_out_dec = 6'b010101;
12'd565 : mem_out_dec = 6'b010110;
12'd566 : mem_out_dec = 6'b010111;
12'd567 : mem_out_dec = 6'b010111;
12'd568 : mem_out_dec = 6'b010111;
12'd569 : mem_out_dec = 6'b011000;
12'd570 : mem_out_dec = 6'b011001;
12'd571 : mem_out_dec = 6'b011010;
12'd572 : mem_out_dec = 6'b011010;
12'd573 : mem_out_dec = 6'b011011;
12'd574 : mem_out_dec = 6'b011100;
12'd575 : mem_out_dec = 6'b011101;
12'd576 : mem_out_dec = 6'b111111;
12'd577 : mem_out_dec = 6'b111111;
12'd578 : mem_out_dec = 6'b111111;
12'd579 : mem_out_dec = 6'b111111;
12'd580 : mem_out_dec = 6'b111111;
12'd581 : mem_out_dec = 6'b111111;
12'd582 : mem_out_dec = 6'b111111;
12'd583 : mem_out_dec = 6'b111111;
12'd584 : mem_out_dec = 6'b111111;
12'd585 : mem_out_dec = 6'b111111;
12'd586 : mem_out_dec = 6'b111111;
12'd587 : mem_out_dec = 6'b111111;
12'd588 : mem_out_dec = 6'b111111;
12'd589 : mem_out_dec = 6'b111111;
12'd590 : mem_out_dec = 6'b111111;
12'd591 : mem_out_dec = 6'b000100;
12'd592 : mem_out_dec = 6'b000011;
12'd593 : mem_out_dec = 6'b000011;
12'd594 : mem_out_dec = 6'b000100;
12'd595 : mem_out_dec = 6'b000101;
12'd596 : mem_out_dec = 6'b000101;
12'd597 : mem_out_dec = 6'b000110;
12'd598 : mem_out_dec = 6'b000110;
12'd599 : mem_out_dec = 6'b000111;
12'd600 : mem_out_dec = 6'b000111;
12'd601 : mem_out_dec = 6'b001000;
12'd602 : mem_out_dec = 6'b001001;
12'd603 : mem_out_dec = 6'b001010;
12'd604 : mem_out_dec = 6'b001010;
12'd605 : mem_out_dec = 6'b001011;
12'd606 : mem_out_dec = 6'b001100;
12'd607 : mem_out_dec = 6'b001101;
12'd608 : mem_out_dec = 6'b001101;
12'd609 : mem_out_dec = 6'b001101;
12'd610 : mem_out_dec = 6'b001110;
12'd611 : mem_out_dec = 6'b001110;
12'd612 : mem_out_dec = 6'b001110;
12'd613 : mem_out_dec = 6'b001111;
12'd614 : mem_out_dec = 6'b010000;
12'd615 : mem_out_dec = 6'b010000;
12'd616 : mem_out_dec = 6'b010000;
12'd617 : mem_out_dec = 6'b010001;
12'd618 : mem_out_dec = 6'b010001;
12'd619 : mem_out_dec = 6'b010010;
12'd620 : mem_out_dec = 6'b010010;
12'd621 : mem_out_dec = 6'b010011;
12'd622 : mem_out_dec = 6'b010011;
12'd623 : mem_out_dec = 6'b010100;
12'd624 : mem_out_dec = 6'b010011;
12'd625 : mem_out_dec = 6'b010011;
12'd626 : mem_out_dec = 6'b010100;
12'd627 : mem_out_dec = 6'b010100;
12'd628 : mem_out_dec = 6'b010101;
12'd629 : mem_out_dec = 6'b010110;
12'd630 : mem_out_dec = 6'b010110;
12'd631 : mem_out_dec = 6'b010111;
12'd632 : mem_out_dec = 6'b010111;
12'd633 : mem_out_dec = 6'b011000;
12'd634 : mem_out_dec = 6'b011001;
12'd635 : mem_out_dec = 6'b011001;
12'd636 : mem_out_dec = 6'b011010;
12'd637 : mem_out_dec = 6'b011011;
12'd638 : mem_out_dec = 6'b011100;
12'd639 : mem_out_dec = 6'b011100;
12'd640 : mem_out_dec = 6'b111111;
12'd641 : mem_out_dec = 6'b111111;
12'd642 : mem_out_dec = 6'b111111;
12'd643 : mem_out_dec = 6'b111111;
12'd644 : mem_out_dec = 6'b111111;
12'd645 : mem_out_dec = 6'b111111;
12'd646 : mem_out_dec = 6'b111111;
12'd647 : mem_out_dec = 6'b111111;
12'd648 : mem_out_dec = 6'b111111;
12'd649 : mem_out_dec = 6'b111111;
12'd650 : mem_out_dec = 6'b111111;
12'd651 : mem_out_dec = 6'b111111;
12'd652 : mem_out_dec = 6'b111111;
12'd653 : mem_out_dec = 6'b111111;
12'd654 : mem_out_dec = 6'b111111;
12'd655 : mem_out_dec = 6'b111111;
12'd656 : mem_out_dec = 6'b000011;
12'd657 : mem_out_dec = 6'b000011;
12'd658 : mem_out_dec = 6'b000100;
12'd659 : mem_out_dec = 6'b000100;
12'd660 : mem_out_dec = 6'b000101;
12'd661 : mem_out_dec = 6'b000110;
12'd662 : mem_out_dec = 6'b000110;
12'd663 : mem_out_dec = 6'b000111;
12'd664 : mem_out_dec = 6'b000111;
12'd665 : mem_out_dec = 6'b001000;
12'd666 : mem_out_dec = 6'b001001;
12'd667 : mem_out_dec = 6'b001001;
12'd668 : mem_out_dec = 6'b001010;
12'd669 : mem_out_dec = 6'b001011;
12'd670 : mem_out_dec = 6'b001100;
12'd671 : mem_out_dec = 6'b001100;
12'd672 : mem_out_dec = 6'b001100;
12'd673 : mem_out_dec = 6'b001101;
12'd674 : mem_out_dec = 6'b001101;
12'd675 : mem_out_dec = 6'b001101;
12'd676 : mem_out_dec = 6'b001110;
12'd677 : mem_out_dec = 6'b001111;
12'd678 : mem_out_dec = 6'b001111;
12'd679 : mem_out_dec = 6'b010000;
12'd680 : mem_out_dec = 6'b010000;
12'd681 : mem_out_dec = 6'b010000;
12'd682 : mem_out_dec = 6'b010001;
12'd683 : mem_out_dec = 6'b010001;
12'd684 : mem_out_dec = 6'b010010;
12'd685 : mem_out_dec = 6'b010010;
12'd686 : mem_out_dec = 6'b010011;
12'd687 : mem_out_dec = 6'b010011;
12'd688 : mem_out_dec = 6'b010011;
12'd689 : mem_out_dec = 6'b010011;
12'd690 : mem_out_dec = 6'b010100;
12'd691 : mem_out_dec = 6'b010100;
12'd692 : mem_out_dec = 6'b010101;
12'd693 : mem_out_dec = 6'b010101;
12'd694 : mem_out_dec = 6'b010110;
12'd695 : mem_out_dec = 6'b010111;
12'd696 : mem_out_dec = 6'b010111;
12'd697 : mem_out_dec = 6'b011000;
12'd698 : mem_out_dec = 6'b011000;
12'd699 : mem_out_dec = 6'b011001;
12'd700 : mem_out_dec = 6'b011010;
12'd701 : mem_out_dec = 6'b011011;
12'd702 : mem_out_dec = 6'b011011;
12'd703 : mem_out_dec = 6'b011100;
12'd704 : mem_out_dec = 6'b111111;
12'd705 : mem_out_dec = 6'b111111;
12'd706 : mem_out_dec = 6'b111111;
12'd707 : mem_out_dec = 6'b111111;
12'd708 : mem_out_dec = 6'b111111;
12'd709 : mem_out_dec = 6'b111111;
12'd710 : mem_out_dec = 6'b111111;
12'd711 : mem_out_dec = 6'b111111;
12'd712 : mem_out_dec = 6'b111111;
12'd713 : mem_out_dec = 6'b111111;
12'd714 : mem_out_dec = 6'b111111;
12'd715 : mem_out_dec = 6'b111111;
12'd716 : mem_out_dec = 6'b111111;
12'd717 : mem_out_dec = 6'b111111;
12'd718 : mem_out_dec = 6'b111111;
12'd719 : mem_out_dec = 6'b111111;
12'd720 : mem_out_dec = 6'b111111;
12'd721 : mem_out_dec = 6'b000011;
12'd722 : mem_out_dec = 6'b000100;
12'd723 : mem_out_dec = 6'b000100;
12'd724 : mem_out_dec = 6'b000101;
12'd725 : mem_out_dec = 6'b000101;
12'd726 : mem_out_dec = 6'b000110;
12'd727 : mem_out_dec = 6'b000111;
12'd728 : mem_out_dec = 6'b000111;
12'd729 : mem_out_dec = 6'b000111;
12'd730 : mem_out_dec = 6'b001000;
12'd731 : mem_out_dec = 6'b001001;
12'd732 : mem_out_dec = 6'b001010;
12'd733 : mem_out_dec = 6'b001011;
12'd734 : mem_out_dec = 6'b001011;
12'd735 : mem_out_dec = 6'b001100;
12'd736 : mem_out_dec = 6'b001100;
12'd737 : mem_out_dec = 6'b001101;
12'd738 : mem_out_dec = 6'b001101;
12'd739 : mem_out_dec = 6'b001101;
12'd740 : mem_out_dec = 6'b001110;
12'd741 : mem_out_dec = 6'b001110;
12'd742 : mem_out_dec = 6'b001111;
12'd743 : mem_out_dec = 6'b010000;
12'd744 : mem_out_dec = 6'b001111;
12'd745 : mem_out_dec = 6'b010000;
12'd746 : mem_out_dec = 6'b010000;
12'd747 : mem_out_dec = 6'b010001;
12'd748 : mem_out_dec = 6'b010001;
12'd749 : mem_out_dec = 6'b010010;
12'd750 : mem_out_dec = 6'b010010;
12'd751 : mem_out_dec = 6'b010011;
12'd752 : mem_out_dec = 6'b010010;
12'd753 : mem_out_dec = 6'b010011;
12'd754 : mem_out_dec = 6'b010011;
12'd755 : mem_out_dec = 6'b010100;
12'd756 : mem_out_dec = 6'b010101;
12'd757 : mem_out_dec = 6'b010101;
12'd758 : mem_out_dec = 6'b010110;
12'd759 : mem_out_dec = 6'b010110;
12'd760 : mem_out_dec = 6'b010111;
12'd761 : mem_out_dec = 6'b010111;
12'd762 : mem_out_dec = 6'b011000;
12'd763 : mem_out_dec = 6'b011001;
12'd764 : mem_out_dec = 6'b011010;
12'd765 : mem_out_dec = 6'b011010;
12'd766 : mem_out_dec = 6'b011011;
12'd767 : mem_out_dec = 6'b011100;
12'd768 : mem_out_dec = 6'b111111;
12'd769 : mem_out_dec = 6'b111111;
12'd770 : mem_out_dec = 6'b111111;
12'd771 : mem_out_dec = 6'b111111;
12'd772 : mem_out_dec = 6'b111111;
12'd773 : mem_out_dec = 6'b111111;
12'd774 : mem_out_dec = 6'b111111;
12'd775 : mem_out_dec = 6'b111111;
12'd776 : mem_out_dec = 6'b111111;
12'd777 : mem_out_dec = 6'b111111;
12'd778 : mem_out_dec = 6'b111111;
12'd779 : mem_out_dec = 6'b111111;
12'd780 : mem_out_dec = 6'b111111;
12'd781 : mem_out_dec = 6'b111111;
12'd782 : mem_out_dec = 6'b111111;
12'd783 : mem_out_dec = 6'b111111;
12'd784 : mem_out_dec = 6'b111111;
12'd785 : mem_out_dec = 6'b111111;
12'd786 : mem_out_dec = 6'b000011;
12'd787 : mem_out_dec = 6'b000100;
12'd788 : mem_out_dec = 6'b000101;
12'd789 : mem_out_dec = 6'b000101;
12'd790 : mem_out_dec = 6'b000110;
12'd791 : mem_out_dec = 6'b000110;
12'd792 : mem_out_dec = 6'b000110;
12'd793 : mem_out_dec = 6'b000111;
12'd794 : mem_out_dec = 6'b001000;
12'd795 : mem_out_dec = 6'b001001;
12'd796 : mem_out_dec = 6'b001010;
12'd797 : mem_out_dec = 6'b001010;
12'd798 : mem_out_dec = 6'b001011;
12'd799 : mem_out_dec = 6'b001100;
12'd800 : mem_out_dec = 6'b001100;
12'd801 : mem_out_dec = 6'b001100;
12'd802 : mem_out_dec = 6'b001101;
12'd803 : mem_out_dec = 6'b001101;
12'd804 : mem_out_dec = 6'b001110;
12'd805 : mem_out_dec = 6'b001110;
12'd806 : mem_out_dec = 6'b001111;
12'd807 : mem_out_dec = 6'b010000;
12'd808 : mem_out_dec = 6'b001111;
12'd809 : mem_out_dec = 6'b001111;
12'd810 : mem_out_dec = 6'b010000;
12'd811 : mem_out_dec = 6'b010000;
12'd812 : mem_out_dec = 6'b010001;
12'd813 : mem_out_dec = 6'b010001;
12'd814 : mem_out_dec = 6'b010010;
12'd815 : mem_out_dec = 6'b010010;
12'd816 : mem_out_dec = 6'b010010;
12'd817 : mem_out_dec = 6'b010011;
12'd818 : mem_out_dec = 6'b010011;
12'd819 : mem_out_dec = 6'b010100;
12'd820 : mem_out_dec = 6'b010100;
12'd821 : mem_out_dec = 6'b010101;
12'd822 : mem_out_dec = 6'b010110;
12'd823 : mem_out_dec = 6'b010110;
12'd824 : mem_out_dec = 6'b010110;
12'd825 : mem_out_dec = 6'b010111;
12'd826 : mem_out_dec = 6'b011000;
12'd827 : mem_out_dec = 6'b011001;
12'd828 : mem_out_dec = 6'b011001;
12'd829 : mem_out_dec = 6'b011010;
12'd830 : mem_out_dec = 6'b011011;
12'd831 : mem_out_dec = 6'b011100;
12'd832 : mem_out_dec = 6'b111111;
12'd833 : mem_out_dec = 6'b111111;
12'd834 : mem_out_dec = 6'b111111;
12'd835 : mem_out_dec = 6'b111111;
12'd836 : mem_out_dec = 6'b111111;
12'd837 : mem_out_dec = 6'b111111;
12'd838 : mem_out_dec = 6'b111111;
12'd839 : mem_out_dec = 6'b111111;
12'd840 : mem_out_dec = 6'b111111;
12'd841 : mem_out_dec = 6'b111111;
12'd842 : mem_out_dec = 6'b111111;
12'd843 : mem_out_dec = 6'b111111;
12'd844 : mem_out_dec = 6'b111111;
12'd845 : mem_out_dec = 6'b111111;
12'd846 : mem_out_dec = 6'b111111;
12'd847 : mem_out_dec = 6'b111111;
12'd848 : mem_out_dec = 6'b111111;
12'd849 : mem_out_dec = 6'b111111;
12'd850 : mem_out_dec = 6'b111111;
12'd851 : mem_out_dec = 6'b000100;
12'd852 : mem_out_dec = 6'b000100;
12'd853 : mem_out_dec = 6'b000101;
12'd854 : mem_out_dec = 6'b000101;
12'd855 : mem_out_dec = 6'b000110;
12'd856 : mem_out_dec = 6'b000110;
12'd857 : mem_out_dec = 6'b000111;
12'd858 : mem_out_dec = 6'b001000;
12'd859 : mem_out_dec = 6'b001001;
12'd860 : mem_out_dec = 6'b001001;
12'd861 : mem_out_dec = 6'b001010;
12'd862 : mem_out_dec = 6'b001011;
12'd863 : mem_out_dec = 6'b001100;
12'd864 : mem_out_dec = 6'b001100;
12'd865 : mem_out_dec = 6'b001100;
12'd866 : mem_out_dec = 6'b001100;
12'd867 : mem_out_dec = 6'b001101;
12'd868 : mem_out_dec = 6'b001101;
12'd869 : mem_out_dec = 6'b001110;
12'd870 : mem_out_dec = 6'b001111;
12'd871 : mem_out_dec = 6'b001111;
12'd872 : mem_out_dec = 6'b001110;
12'd873 : mem_out_dec = 6'b001111;
12'd874 : mem_out_dec = 6'b001111;
12'd875 : mem_out_dec = 6'b010000;
12'd876 : mem_out_dec = 6'b010000;
12'd877 : mem_out_dec = 6'b010001;
12'd878 : mem_out_dec = 6'b010001;
12'd879 : mem_out_dec = 6'b010010;
12'd880 : mem_out_dec = 6'b010010;
12'd881 : mem_out_dec = 6'b010010;
12'd882 : mem_out_dec = 6'b010011;
12'd883 : mem_out_dec = 6'b010100;
12'd884 : mem_out_dec = 6'b010100;
12'd885 : mem_out_dec = 6'b010101;
12'd886 : mem_out_dec = 6'b010101;
12'd887 : mem_out_dec = 6'b010110;
12'd888 : mem_out_dec = 6'b010110;
12'd889 : mem_out_dec = 6'b010111;
12'd890 : mem_out_dec = 6'b011000;
12'd891 : mem_out_dec = 6'b011000;
12'd892 : mem_out_dec = 6'b011001;
12'd893 : mem_out_dec = 6'b011010;
12'd894 : mem_out_dec = 6'b011011;
12'd895 : mem_out_dec = 6'b011011;
12'd896 : mem_out_dec = 6'b111111;
12'd897 : mem_out_dec = 6'b111111;
12'd898 : mem_out_dec = 6'b111111;
12'd899 : mem_out_dec = 6'b111111;
12'd900 : mem_out_dec = 6'b111111;
12'd901 : mem_out_dec = 6'b111111;
12'd902 : mem_out_dec = 6'b111111;
12'd903 : mem_out_dec = 6'b111111;
12'd904 : mem_out_dec = 6'b111111;
12'd905 : mem_out_dec = 6'b111111;
12'd906 : mem_out_dec = 6'b111111;
12'd907 : mem_out_dec = 6'b111111;
12'd908 : mem_out_dec = 6'b111111;
12'd909 : mem_out_dec = 6'b111111;
12'd910 : mem_out_dec = 6'b111111;
12'd911 : mem_out_dec = 6'b111111;
12'd912 : mem_out_dec = 6'b111111;
12'd913 : mem_out_dec = 6'b111111;
12'd914 : mem_out_dec = 6'b111111;
12'd915 : mem_out_dec = 6'b111111;
12'd916 : mem_out_dec = 6'b000100;
12'd917 : mem_out_dec = 6'b000101;
12'd918 : mem_out_dec = 6'b000101;
12'd919 : mem_out_dec = 6'b000110;
12'd920 : mem_out_dec = 6'b000110;
12'd921 : mem_out_dec = 6'b000111;
12'd922 : mem_out_dec = 6'b001000;
12'd923 : mem_out_dec = 6'b001000;
12'd924 : mem_out_dec = 6'b001001;
12'd925 : mem_out_dec = 6'b001010;
12'd926 : mem_out_dec = 6'b001011;
12'd927 : mem_out_dec = 6'b001011;
12'd928 : mem_out_dec = 6'b001011;
12'd929 : mem_out_dec = 6'b001100;
12'd930 : mem_out_dec = 6'b001100;
12'd931 : mem_out_dec = 6'b001101;
12'd932 : mem_out_dec = 6'b001101;
12'd933 : mem_out_dec = 6'b001110;
12'd934 : mem_out_dec = 6'b001110;
12'd935 : mem_out_dec = 6'b001111;
12'd936 : mem_out_dec = 6'b001110;
12'd937 : mem_out_dec = 6'b001110;
12'd938 : mem_out_dec = 6'b001111;
12'd939 : mem_out_dec = 6'b001111;
12'd940 : mem_out_dec = 6'b010000;
12'd941 : mem_out_dec = 6'b010000;
12'd942 : mem_out_dec = 6'b010001;
12'd943 : mem_out_dec = 6'b010001;
12'd944 : mem_out_dec = 6'b010010;
12'd945 : mem_out_dec = 6'b010010;
12'd946 : mem_out_dec = 6'b010011;
12'd947 : mem_out_dec = 6'b010011;
12'd948 : mem_out_dec = 6'b010100;
12'd949 : mem_out_dec = 6'b010100;
12'd950 : mem_out_dec = 6'b010101;
12'd951 : mem_out_dec = 6'b010110;
12'd952 : mem_out_dec = 6'b010110;
12'd953 : mem_out_dec = 6'b010111;
12'd954 : mem_out_dec = 6'b010111;
12'd955 : mem_out_dec = 6'b011000;
12'd956 : mem_out_dec = 6'b011001;
12'd957 : mem_out_dec = 6'b011010;
12'd958 : mem_out_dec = 6'b011010;
12'd959 : mem_out_dec = 6'b011011;
12'd960 : mem_out_dec = 6'b111111;
12'd961 : mem_out_dec = 6'b111111;
12'd962 : mem_out_dec = 6'b111111;
12'd963 : mem_out_dec = 6'b111111;
12'd964 : mem_out_dec = 6'b111111;
12'd965 : mem_out_dec = 6'b111111;
12'd966 : mem_out_dec = 6'b111111;
12'd967 : mem_out_dec = 6'b111111;
12'd968 : mem_out_dec = 6'b111111;
12'd969 : mem_out_dec = 6'b111111;
12'd970 : mem_out_dec = 6'b111111;
12'd971 : mem_out_dec = 6'b111111;
12'd972 : mem_out_dec = 6'b111111;
12'd973 : mem_out_dec = 6'b111111;
12'd974 : mem_out_dec = 6'b111111;
12'd975 : mem_out_dec = 6'b111111;
12'd976 : mem_out_dec = 6'b111111;
12'd977 : mem_out_dec = 6'b111111;
12'd978 : mem_out_dec = 6'b111111;
12'd979 : mem_out_dec = 6'b111111;
12'd980 : mem_out_dec = 6'b111111;
12'd981 : mem_out_dec = 6'b000100;
12'd982 : mem_out_dec = 6'b000101;
12'd983 : mem_out_dec = 6'b000110;
12'd984 : mem_out_dec = 6'b000110;
12'd985 : mem_out_dec = 6'b000111;
12'd986 : mem_out_dec = 6'b000111;
12'd987 : mem_out_dec = 6'b001000;
12'd988 : mem_out_dec = 6'b001001;
12'd989 : mem_out_dec = 6'b001010;
12'd990 : mem_out_dec = 6'b001010;
12'd991 : mem_out_dec = 6'b001011;
12'd992 : mem_out_dec = 6'b001011;
12'd993 : mem_out_dec = 6'b001011;
12'd994 : mem_out_dec = 6'b001100;
12'd995 : mem_out_dec = 6'b001100;
12'd996 : mem_out_dec = 6'b001101;
12'd997 : mem_out_dec = 6'b001110;
12'd998 : mem_out_dec = 6'b001110;
12'd999 : mem_out_dec = 6'b001110;
12'd1000 : mem_out_dec = 6'b001101;
12'd1001 : mem_out_dec = 6'b001110;
12'd1002 : mem_out_dec = 6'b001110;
12'd1003 : mem_out_dec = 6'b001111;
12'd1004 : mem_out_dec = 6'b001111;
12'd1005 : mem_out_dec = 6'b010000;
12'd1006 : mem_out_dec = 6'b010000;
12'd1007 : mem_out_dec = 6'b010001;
12'd1008 : mem_out_dec = 6'b010001;
12'd1009 : mem_out_dec = 6'b010010;
12'd1010 : mem_out_dec = 6'b010011;
12'd1011 : mem_out_dec = 6'b010011;
12'd1012 : mem_out_dec = 6'b010100;
12'd1013 : mem_out_dec = 6'b010100;
12'd1014 : mem_out_dec = 6'b010101;
12'd1015 : mem_out_dec = 6'b010110;
12'd1016 : mem_out_dec = 6'b010110;
12'd1017 : mem_out_dec = 6'b010110;
12'd1018 : mem_out_dec = 6'b010111;
12'd1019 : mem_out_dec = 6'b011000;
12'd1020 : mem_out_dec = 6'b011001;
12'd1021 : mem_out_dec = 6'b011001;
12'd1022 : mem_out_dec = 6'b011010;
12'd1023 : mem_out_dec = 6'b011011;
12'd1024 : mem_out_dec = 6'b111111;
12'd1025 : mem_out_dec = 6'b111111;
12'd1026 : mem_out_dec = 6'b111111;
12'd1027 : mem_out_dec = 6'b111111;
12'd1028 : mem_out_dec = 6'b111111;
12'd1029 : mem_out_dec = 6'b111111;
12'd1030 : mem_out_dec = 6'b111111;
12'd1031 : mem_out_dec = 6'b111111;
12'd1032 : mem_out_dec = 6'b111111;
12'd1033 : mem_out_dec = 6'b111111;
12'd1034 : mem_out_dec = 6'b111111;
12'd1035 : mem_out_dec = 6'b111111;
12'd1036 : mem_out_dec = 6'b111111;
12'd1037 : mem_out_dec = 6'b111111;
12'd1038 : mem_out_dec = 6'b111111;
12'd1039 : mem_out_dec = 6'b111111;
12'd1040 : mem_out_dec = 6'b111111;
12'd1041 : mem_out_dec = 6'b111111;
12'd1042 : mem_out_dec = 6'b111111;
12'd1043 : mem_out_dec = 6'b111111;
12'd1044 : mem_out_dec = 6'b111111;
12'd1045 : mem_out_dec = 6'b111111;
12'd1046 : mem_out_dec = 6'b000100;
12'd1047 : mem_out_dec = 6'b000101;
12'd1048 : mem_out_dec = 6'b000101;
12'd1049 : mem_out_dec = 6'b000110;
12'd1050 : mem_out_dec = 6'b000110;
12'd1051 : mem_out_dec = 6'b000111;
12'd1052 : mem_out_dec = 6'b001000;
12'd1053 : mem_out_dec = 6'b001001;
12'd1054 : mem_out_dec = 6'b001001;
12'd1055 : mem_out_dec = 6'b001010;
12'd1056 : mem_out_dec = 6'b001010;
12'd1057 : mem_out_dec = 6'b001011;
12'd1058 : mem_out_dec = 6'b001011;
12'd1059 : mem_out_dec = 6'b001100;
12'd1060 : mem_out_dec = 6'b001100;
12'd1061 : mem_out_dec = 6'b001100;
12'd1062 : mem_out_dec = 6'b001100;
12'd1063 : mem_out_dec = 6'b001100;
12'd1064 : mem_out_dec = 6'b001100;
12'd1065 : mem_out_dec = 6'b001100;
12'd1066 : mem_out_dec = 6'b001101;
12'd1067 : mem_out_dec = 6'b001101;
12'd1068 : mem_out_dec = 6'b001110;
12'd1069 : mem_out_dec = 6'b001111;
12'd1070 : mem_out_dec = 6'b010000;
12'd1071 : mem_out_dec = 6'b010000;
12'd1072 : mem_out_dec = 6'b010001;
12'd1073 : mem_out_dec = 6'b010001;
12'd1074 : mem_out_dec = 6'b010010;
12'd1075 : mem_out_dec = 6'b010010;
12'd1076 : mem_out_dec = 6'b010011;
12'd1077 : mem_out_dec = 6'b010011;
12'd1078 : mem_out_dec = 6'b010100;
12'd1079 : mem_out_dec = 6'b010101;
12'd1080 : mem_out_dec = 6'b010101;
12'd1081 : mem_out_dec = 6'b010110;
12'd1082 : mem_out_dec = 6'b010110;
12'd1083 : mem_out_dec = 6'b010111;
12'd1084 : mem_out_dec = 6'b011000;
12'd1085 : mem_out_dec = 6'b011000;
12'd1086 : mem_out_dec = 6'b011001;
12'd1087 : mem_out_dec = 6'b011010;
12'd1088 : mem_out_dec = 6'b111111;
12'd1089 : mem_out_dec = 6'b111111;
12'd1090 : mem_out_dec = 6'b111111;
12'd1091 : mem_out_dec = 6'b111111;
12'd1092 : mem_out_dec = 6'b111111;
12'd1093 : mem_out_dec = 6'b111111;
12'd1094 : mem_out_dec = 6'b111111;
12'd1095 : mem_out_dec = 6'b111111;
12'd1096 : mem_out_dec = 6'b111111;
12'd1097 : mem_out_dec = 6'b111111;
12'd1098 : mem_out_dec = 6'b111111;
12'd1099 : mem_out_dec = 6'b111111;
12'd1100 : mem_out_dec = 6'b111111;
12'd1101 : mem_out_dec = 6'b111111;
12'd1102 : mem_out_dec = 6'b111111;
12'd1103 : mem_out_dec = 6'b111111;
12'd1104 : mem_out_dec = 6'b111111;
12'd1105 : mem_out_dec = 6'b111111;
12'd1106 : mem_out_dec = 6'b111111;
12'd1107 : mem_out_dec = 6'b111111;
12'd1108 : mem_out_dec = 6'b111111;
12'd1109 : mem_out_dec = 6'b111111;
12'd1110 : mem_out_dec = 6'b111111;
12'd1111 : mem_out_dec = 6'b000100;
12'd1112 : mem_out_dec = 6'b000100;
12'd1113 : mem_out_dec = 6'b000101;
12'd1114 : mem_out_dec = 6'b000110;
12'd1115 : mem_out_dec = 6'b000111;
12'd1116 : mem_out_dec = 6'b000111;
12'd1117 : mem_out_dec = 6'b001000;
12'd1118 : mem_out_dec = 6'b001001;
12'd1119 : mem_out_dec = 6'b001001;
12'd1120 : mem_out_dec = 6'b001010;
12'd1121 : mem_out_dec = 6'b001010;
12'd1122 : mem_out_dec = 6'b001011;
12'd1123 : mem_out_dec = 6'b001011;
12'd1124 : mem_out_dec = 6'b001011;
12'd1125 : mem_out_dec = 6'b001011;
12'd1126 : mem_out_dec = 6'b001011;
12'd1127 : mem_out_dec = 6'b001011;
12'd1128 : mem_out_dec = 6'b001011;
12'd1129 : mem_out_dec = 6'b001011;
12'd1130 : mem_out_dec = 6'b001100;
12'd1131 : mem_out_dec = 6'b001101;
12'd1132 : mem_out_dec = 6'b001110;
12'd1133 : mem_out_dec = 6'b001110;
12'd1134 : mem_out_dec = 6'b001111;
12'd1135 : mem_out_dec = 6'b010000;
12'd1136 : mem_out_dec = 6'b010000;
12'd1137 : mem_out_dec = 6'b010001;
12'd1138 : mem_out_dec = 6'b010001;
12'd1139 : mem_out_dec = 6'b010010;
12'd1140 : mem_out_dec = 6'b010010;
12'd1141 : mem_out_dec = 6'b010011;
12'd1142 : mem_out_dec = 6'b010100;
12'd1143 : mem_out_dec = 6'b010100;
12'd1144 : mem_out_dec = 6'b010100;
12'd1145 : mem_out_dec = 6'b010101;
12'd1146 : mem_out_dec = 6'b010110;
12'd1147 : mem_out_dec = 6'b010110;
12'd1148 : mem_out_dec = 6'b010111;
12'd1149 : mem_out_dec = 6'b011000;
12'd1150 : mem_out_dec = 6'b011000;
12'd1151 : mem_out_dec = 6'b011001;
12'd1152 : mem_out_dec = 6'b111111;
12'd1153 : mem_out_dec = 6'b111111;
12'd1154 : mem_out_dec = 6'b111111;
12'd1155 : mem_out_dec = 6'b111111;
12'd1156 : mem_out_dec = 6'b111111;
12'd1157 : mem_out_dec = 6'b111111;
12'd1158 : mem_out_dec = 6'b111111;
12'd1159 : mem_out_dec = 6'b111111;
12'd1160 : mem_out_dec = 6'b111111;
12'd1161 : mem_out_dec = 6'b111111;
12'd1162 : mem_out_dec = 6'b111111;
12'd1163 : mem_out_dec = 6'b111111;
12'd1164 : mem_out_dec = 6'b111111;
12'd1165 : mem_out_dec = 6'b111111;
12'd1166 : mem_out_dec = 6'b111111;
12'd1167 : mem_out_dec = 6'b111111;
12'd1168 : mem_out_dec = 6'b111111;
12'd1169 : mem_out_dec = 6'b111111;
12'd1170 : mem_out_dec = 6'b111111;
12'd1171 : mem_out_dec = 6'b111111;
12'd1172 : mem_out_dec = 6'b111111;
12'd1173 : mem_out_dec = 6'b111111;
12'd1174 : mem_out_dec = 6'b111111;
12'd1175 : mem_out_dec = 6'b111111;
12'd1176 : mem_out_dec = 6'b000100;
12'd1177 : mem_out_dec = 6'b000101;
12'd1178 : mem_out_dec = 6'b000101;
12'd1179 : mem_out_dec = 6'b000110;
12'd1180 : mem_out_dec = 6'b000111;
12'd1181 : mem_out_dec = 6'b000111;
12'd1182 : mem_out_dec = 6'b001000;
12'd1183 : mem_out_dec = 6'b001001;
12'd1184 : mem_out_dec = 6'b001001;
12'd1185 : mem_out_dec = 6'b001010;
12'd1186 : mem_out_dec = 6'b001010;
12'd1187 : mem_out_dec = 6'b001010;
12'd1188 : mem_out_dec = 6'b001010;
12'd1189 : mem_out_dec = 6'b001010;
12'd1190 : mem_out_dec = 6'b001010;
12'd1191 : mem_out_dec = 6'b001010;
12'd1192 : mem_out_dec = 6'b001010;
12'd1193 : mem_out_dec = 6'b001011;
12'd1194 : mem_out_dec = 6'b001100;
12'd1195 : mem_out_dec = 6'b001100;
12'd1196 : mem_out_dec = 6'b001101;
12'd1197 : mem_out_dec = 6'b001110;
12'd1198 : mem_out_dec = 6'b001111;
12'd1199 : mem_out_dec = 6'b010000;
12'd1200 : mem_out_dec = 6'b010000;
12'd1201 : mem_out_dec = 6'b010000;
12'd1202 : mem_out_dec = 6'b010001;
12'd1203 : mem_out_dec = 6'b010001;
12'd1204 : mem_out_dec = 6'b010010;
12'd1205 : mem_out_dec = 6'b010011;
12'd1206 : mem_out_dec = 6'b010011;
12'd1207 : mem_out_dec = 6'b010100;
12'd1208 : mem_out_dec = 6'b010100;
12'd1209 : mem_out_dec = 6'b010100;
12'd1210 : mem_out_dec = 6'b010101;
12'd1211 : mem_out_dec = 6'b010110;
12'd1212 : mem_out_dec = 6'b010110;
12'd1213 : mem_out_dec = 6'b010111;
12'd1214 : mem_out_dec = 6'b011000;
12'd1215 : mem_out_dec = 6'b011001;
12'd1216 : mem_out_dec = 6'b111111;
12'd1217 : mem_out_dec = 6'b111111;
12'd1218 : mem_out_dec = 6'b111111;
12'd1219 : mem_out_dec = 6'b111111;
12'd1220 : mem_out_dec = 6'b111111;
12'd1221 : mem_out_dec = 6'b111111;
12'd1222 : mem_out_dec = 6'b111111;
12'd1223 : mem_out_dec = 6'b111111;
12'd1224 : mem_out_dec = 6'b111111;
12'd1225 : mem_out_dec = 6'b111111;
12'd1226 : mem_out_dec = 6'b111111;
12'd1227 : mem_out_dec = 6'b111111;
12'd1228 : mem_out_dec = 6'b111111;
12'd1229 : mem_out_dec = 6'b111111;
12'd1230 : mem_out_dec = 6'b111111;
12'd1231 : mem_out_dec = 6'b111111;
12'd1232 : mem_out_dec = 6'b111111;
12'd1233 : mem_out_dec = 6'b111111;
12'd1234 : mem_out_dec = 6'b111111;
12'd1235 : mem_out_dec = 6'b111111;
12'd1236 : mem_out_dec = 6'b111111;
12'd1237 : mem_out_dec = 6'b111111;
12'd1238 : mem_out_dec = 6'b111111;
12'd1239 : mem_out_dec = 6'b111111;
12'd1240 : mem_out_dec = 6'b111111;
12'd1241 : mem_out_dec = 6'b000100;
12'd1242 : mem_out_dec = 6'b000100;
12'd1243 : mem_out_dec = 6'b000101;
12'd1244 : mem_out_dec = 6'b000110;
12'd1245 : mem_out_dec = 6'b000111;
12'd1246 : mem_out_dec = 6'b001000;
12'd1247 : mem_out_dec = 6'b001000;
12'd1248 : mem_out_dec = 6'b001001;
12'd1249 : mem_out_dec = 6'b001001;
12'd1250 : mem_out_dec = 6'b001001;
12'd1251 : mem_out_dec = 6'b001001;
12'd1252 : mem_out_dec = 6'b001001;
12'd1253 : mem_out_dec = 6'b001001;
12'd1254 : mem_out_dec = 6'b001001;
12'd1255 : mem_out_dec = 6'b001001;
12'd1256 : mem_out_dec = 6'b001010;
12'd1257 : mem_out_dec = 6'b001010;
12'd1258 : mem_out_dec = 6'b001011;
12'd1259 : mem_out_dec = 6'b001100;
12'd1260 : mem_out_dec = 6'b001101;
12'd1261 : mem_out_dec = 6'b001110;
12'd1262 : mem_out_dec = 6'b001110;
12'd1263 : mem_out_dec = 6'b001111;
12'd1264 : mem_out_dec = 6'b001111;
12'd1265 : mem_out_dec = 6'b010000;
12'd1266 : mem_out_dec = 6'b010000;
12'd1267 : mem_out_dec = 6'b010001;
12'd1268 : mem_out_dec = 6'b010001;
12'd1269 : mem_out_dec = 6'b010010;
12'd1270 : mem_out_dec = 6'b010011;
12'd1271 : mem_out_dec = 6'b010011;
12'd1272 : mem_out_dec = 6'b010011;
12'd1273 : mem_out_dec = 6'b010100;
12'd1274 : mem_out_dec = 6'b010100;
12'd1275 : mem_out_dec = 6'b010101;
12'd1276 : mem_out_dec = 6'b010110;
12'd1277 : mem_out_dec = 6'b010111;
12'd1278 : mem_out_dec = 6'b011000;
12'd1279 : mem_out_dec = 6'b011000;
12'd1280 : mem_out_dec = 6'b111111;
12'd1281 : mem_out_dec = 6'b111111;
12'd1282 : mem_out_dec = 6'b111111;
12'd1283 : mem_out_dec = 6'b111111;
12'd1284 : mem_out_dec = 6'b111111;
12'd1285 : mem_out_dec = 6'b111111;
12'd1286 : mem_out_dec = 6'b111111;
12'd1287 : mem_out_dec = 6'b111111;
12'd1288 : mem_out_dec = 6'b111111;
12'd1289 : mem_out_dec = 6'b111111;
12'd1290 : mem_out_dec = 6'b111111;
12'd1291 : mem_out_dec = 6'b111111;
12'd1292 : mem_out_dec = 6'b111111;
12'd1293 : mem_out_dec = 6'b111111;
12'd1294 : mem_out_dec = 6'b111111;
12'd1295 : mem_out_dec = 6'b111111;
12'd1296 : mem_out_dec = 6'b111111;
12'd1297 : mem_out_dec = 6'b111111;
12'd1298 : mem_out_dec = 6'b111111;
12'd1299 : mem_out_dec = 6'b111111;
12'd1300 : mem_out_dec = 6'b111111;
12'd1301 : mem_out_dec = 6'b111111;
12'd1302 : mem_out_dec = 6'b111111;
12'd1303 : mem_out_dec = 6'b111111;
12'd1304 : mem_out_dec = 6'b111111;
12'd1305 : mem_out_dec = 6'b111111;
12'd1306 : mem_out_dec = 6'b000100;
12'd1307 : mem_out_dec = 6'b000101;
12'd1308 : mem_out_dec = 6'b000110;
12'd1309 : mem_out_dec = 6'b000110;
12'd1310 : mem_out_dec = 6'b000111;
12'd1311 : mem_out_dec = 6'b001000;
12'd1312 : mem_out_dec = 6'b001000;
12'd1313 : mem_out_dec = 6'b001000;
12'd1314 : mem_out_dec = 6'b001000;
12'd1315 : mem_out_dec = 6'b001000;
12'd1316 : mem_out_dec = 6'b001000;
12'd1317 : mem_out_dec = 6'b001000;
12'd1318 : mem_out_dec = 6'b001000;
12'd1319 : mem_out_dec = 6'b001001;
12'd1320 : mem_out_dec = 6'b001001;
12'd1321 : mem_out_dec = 6'b001010;
12'd1322 : mem_out_dec = 6'b001011;
12'd1323 : mem_out_dec = 6'b001100;
12'd1324 : mem_out_dec = 6'b001100;
12'd1325 : mem_out_dec = 6'b001101;
12'd1326 : mem_out_dec = 6'b001110;
12'd1327 : mem_out_dec = 6'b001111;
12'd1328 : mem_out_dec = 6'b001111;
12'd1329 : mem_out_dec = 6'b001111;
12'd1330 : mem_out_dec = 6'b010000;
12'd1331 : mem_out_dec = 6'b010000;
12'd1332 : mem_out_dec = 6'b010001;
12'd1333 : mem_out_dec = 6'b010001;
12'd1334 : mem_out_dec = 6'b010010;
12'd1335 : mem_out_dec = 6'b010011;
12'd1336 : mem_out_dec = 6'b010010;
12'd1337 : mem_out_dec = 6'b010011;
12'd1338 : mem_out_dec = 6'b010100;
12'd1339 : mem_out_dec = 6'b010101;
12'd1340 : mem_out_dec = 6'b010110;
12'd1341 : mem_out_dec = 6'b010110;
12'd1342 : mem_out_dec = 6'b010111;
12'd1343 : mem_out_dec = 6'b011000;
12'd1344 : mem_out_dec = 6'b111111;
12'd1345 : mem_out_dec = 6'b111111;
12'd1346 : mem_out_dec = 6'b111111;
12'd1347 : mem_out_dec = 6'b111111;
12'd1348 : mem_out_dec = 6'b111111;
12'd1349 : mem_out_dec = 6'b111111;
12'd1350 : mem_out_dec = 6'b111111;
12'd1351 : mem_out_dec = 6'b111111;
12'd1352 : mem_out_dec = 6'b111111;
12'd1353 : mem_out_dec = 6'b111111;
12'd1354 : mem_out_dec = 6'b111111;
12'd1355 : mem_out_dec = 6'b111111;
12'd1356 : mem_out_dec = 6'b111111;
12'd1357 : mem_out_dec = 6'b111111;
12'd1358 : mem_out_dec = 6'b111111;
12'd1359 : mem_out_dec = 6'b111111;
12'd1360 : mem_out_dec = 6'b111111;
12'd1361 : mem_out_dec = 6'b111111;
12'd1362 : mem_out_dec = 6'b111111;
12'd1363 : mem_out_dec = 6'b111111;
12'd1364 : mem_out_dec = 6'b111111;
12'd1365 : mem_out_dec = 6'b111111;
12'd1366 : mem_out_dec = 6'b111111;
12'd1367 : mem_out_dec = 6'b111111;
12'd1368 : mem_out_dec = 6'b111111;
12'd1369 : mem_out_dec = 6'b111111;
12'd1370 : mem_out_dec = 6'b111111;
12'd1371 : mem_out_dec = 6'b000101;
12'd1372 : mem_out_dec = 6'b000101;
12'd1373 : mem_out_dec = 6'b000110;
12'd1374 : mem_out_dec = 6'b000111;
12'd1375 : mem_out_dec = 6'b001000;
12'd1376 : mem_out_dec = 6'b000111;
12'd1377 : mem_out_dec = 6'b000111;
12'd1378 : mem_out_dec = 6'b000111;
12'd1379 : mem_out_dec = 6'b000111;
12'd1380 : mem_out_dec = 6'b000111;
12'd1381 : mem_out_dec = 6'b000111;
12'd1382 : mem_out_dec = 6'b001000;
12'd1383 : mem_out_dec = 6'b001001;
12'd1384 : mem_out_dec = 6'b001001;
12'd1385 : mem_out_dec = 6'b001010;
12'd1386 : mem_out_dec = 6'b001010;
12'd1387 : mem_out_dec = 6'b001011;
12'd1388 : mem_out_dec = 6'b001100;
12'd1389 : mem_out_dec = 6'b001101;
12'd1390 : mem_out_dec = 6'b001110;
12'd1391 : mem_out_dec = 6'b001110;
12'd1392 : mem_out_dec = 6'b001111;
12'd1393 : mem_out_dec = 6'b001111;
12'd1394 : mem_out_dec = 6'b010000;
12'd1395 : mem_out_dec = 6'b010000;
12'd1396 : mem_out_dec = 6'b010001;
12'd1397 : mem_out_dec = 6'b010001;
12'd1398 : mem_out_dec = 6'b010010;
12'd1399 : mem_out_dec = 6'b010010;
12'd1400 : mem_out_dec = 6'b010010;
12'd1401 : mem_out_dec = 6'b010011;
12'd1402 : mem_out_dec = 6'b010100;
12'd1403 : mem_out_dec = 6'b010100;
12'd1404 : mem_out_dec = 6'b010101;
12'd1405 : mem_out_dec = 6'b010110;
12'd1406 : mem_out_dec = 6'b010111;
12'd1407 : mem_out_dec = 6'b010111;
12'd1408 : mem_out_dec = 6'b111111;
12'd1409 : mem_out_dec = 6'b111111;
12'd1410 : mem_out_dec = 6'b111111;
12'd1411 : mem_out_dec = 6'b111111;
12'd1412 : mem_out_dec = 6'b111111;
12'd1413 : mem_out_dec = 6'b111111;
12'd1414 : mem_out_dec = 6'b111111;
12'd1415 : mem_out_dec = 6'b111111;
12'd1416 : mem_out_dec = 6'b111111;
12'd1417 : mem_out_dec = 6'b111111;
12'd1418 : mem_out_dec = 6'b111111;
12'd1419 : mem_out_dec = 6'b111111;
12'd1420 : mem_out_dec = 6'b111111;
12'd1421 : mem_out_dec = 6'b111111;
12'd1422 : mem_out_dec = 6'b111111;
12'd1423 : mem_out_dec = 6'b111111;
12'd1424 : mem_out_dec = 6'b111111;
12'd1425 : mem_out_dec = 6'b111111;
12'd1426 : mem_out_dec = 6'b111111;
12'd1427 : mem_out_dec = 6'b111111;
12'd1428 : mem_out_dec = 6'b111111;
12'd1429 : mem_out_dec = 6'b111111;
12'd1430 : mem_out_dec = 6'b111111;
12'd1431 : mem_out_dec = 6'b111111;
12'd1432 : mem_out_dec = 6'b111111;
12'd1433 : mem_out_dec = 6'b111111;
12'd1434 : mem_out_dec = 6'b111111;
12'd1435 : mem_out_dec = 6'b111111;
12'd1436 : mem_out_dec = 6'b000101;
12'd1437 : mem_out_dec = 6'b000110;
12'd1438 : mem_out_dec = 6'b000111;
12'd1439 : mem_out_dec = 6'b000111;
12'd1440 : mem_out_dec = 6'b000110;
12'd1441 : mem_out_dec = 6'b000110;
12'd1442 : mem_out_dec = 6'b000110;
12'd1443 : mem_out_dec = 6'b000110;
12'd1444 : mem_out_dec = 6'b000110;
12'd1445 : mem_out_dec = 6'b000111;
12'd1446 : mem_out_dec = 6'b000111;
12'd1447 : mem_out_dec = 6'b001000;
12'd1448 : mem_out_dec = 6'b001001;
12'd1449 : mem_out_dec = 6'b001001;
12'd1450 : mem_out_dec = 6'b001010;
12'd1451 : mem_out_dec = 6'b001011;
12'd1452 : mem_out_dec = 6'b001100;
12'd1453 : mem_out_dec = 6'b001100;
12'd1454 : mem_out_dec = 6'b001101;
12'd1455 : mem_out_dec = 6'b001110;
12'd1456 : mem_out_dec = 6'b001110;
12'd1457 : mem_out_dec = 6'b001111;
12'd1458 : mem_out_dec = 6'b001111;
12'd1459 : mem_out_dec = 6'b010000;
12'd1460 : mem_out_dec = 6'b010000;
12'd1461 : mem_out_dec = 6'b010001;
12'd1462 : mem_out_dec = 6'b010001;
12'd1463 : mem_out_dec = 6'b010010;
12'd1464 : mem_out_dec = 6'b010010;
12'd1465 : mem_out_dec = 6'b010011;
12'd1466 : mem_out_dec = 6'b010011;
12'd1467 : mem_out_dec = 6'b010100;
12'd1468 : mem_out_dec = 6'b010101;
12'd1469 : mem_out_dec = 6'b010110;
12'd1470 : mem_out_dec = 6'b010110;
12'd1471 : mem_out_dec = 6'b010111;
12'd1472 : mem_out_dec = 6'b111111;
12'd1473 : mem_out_dec = 6'b111111;
12'd1474 : mem_out_dec = 6'b111111;
12'd1475 : mem_out_dec = 6'b111111;
12'd1476 : mem_out_dec = 6'b111111;
12'd1477 : mem_out_dec = 6'b111111;
12'd1478 : mem_out_dec = 6'b111111;
12'd1479 : mem_out_dec = 6'b111111;
12'd1480 : mem_out_dec = 6'b111111;
12'd1481 : mem_out_dec = 6'b111111;
12'd1482 : mem_out_dec = 6'b111111;
12'd1483 : mem_out_dec = 6'b111111;
12'd1484 : mem_out_dec = 6'b111111;
12'd1485 : mem_out_dec = 6'b111111;
12'd1486 : mem_out_dec = 6'b111111;
12'd1487 : mem_out_dec = 6'b111111;
12'd1488 : mem_out_dec = 6'b111111;
12'd1489 : mem_out_dec = 6'b111111;
12'd1490 : mem_out_dec = 6'b111111;
12'd1491 : mem_out_dec = 6'b111111;
12'd1492 : mem_out_dec = 6'b111111;
12'd1493 : mem_out_dec = 6'b111111;
12'd1494 : mem_out_dec = 6'b111111;
12'd1495 : mem_out_dec = 6'b111111;
12'd1496 : mem_out_dec = 6'b111111;
12'd1497 : mem_out_dec = 6'b111111;
12'd1498 : mem_out_dec = 6'b111111;
12'd1499 : mem_out_dec = 6'b111111;
12'd1500 : mem_out_dec = 6'b111111;
12'd1501 : mem_out_dec = 6'b000101;
12'd1502 : mem_out_dec = 6'b000110;
12'd1503 : mem_out_dec = 6'b000110;
12'd1504 : mem_out_dec = 6'b000110;
12'd1505 : mem_out_dec = 6'b000110;
12'd1506 : mem_out_dec = 6'b000101;
12'd1507 : mem_out_dec = 6'b000101;
12'd1508 : mem_out_dec = 6'b000110;
12'd1509 : mem_out_dec = 6'b000111;
12'd1510 : mem_out_dec = 6'b000111;
12'd1511 : mem_out_dec = 6'b001000;
12'd1512 : mem_out_dec = 6'b001000;
12'd1513 : mem_out_dec = 6'b001001;
12'd1514 : mem_out_dec = 6'b001010;
12'd1515 : mem_out_dec = 6'b001011;
12'd1516 : mem_out_dec = 6'b001011;
12'd1517 : mem_out_dec = 6'b001100;
12'd1518 : mem_out_dec = 6'b001101;
12'd1519 : mem_out_dec = 6'b001110;
12'd1520 : mem_out_dec = 6'b001110;
12'd1521 : mem_out_dec = 6'b001110;
12'd1522 : mem_out_dec = 6'b001111;
12'd1523 : mem_out_dec = 6'b001111;
12'd1524 : mem_out_dec = 6'b010000;
12'd1525 : mem_out_dec = 6'b010000;
12'd1526 : mem_out_dec = 6'b010001;
12'd1527 : mem_out_dec = 6'b010001;
12'd1528 : mem_out_dec = 6'b010001;
12'd1529 : mem_out_dec = 6'b010010;
12'd1530 : mem_out_dec = 6'b010011;
12'd1531 : mem_out_dec = 6'b010100;
12'd1532 : mem_out_dec = 6'b010101;
12'd1533 : mem_out_dec = 6'b010101;
12'd1534 : mem_out_dec = 6'b010110;
12'd1535 : mem_out_dec = 6'b010110;
12'd1536 : mem_out_dec = 6'b111111;
12'd1537 : mem_out_dec = 6'b111111;
12'd1538 : mem_out_dec = 6'b111111;
12'd1539 : mem_out_dec = 6'b111111;
12'd1540 : mem_out_dec = 6'b111111;
12'd1541 : mem_out_dec = 6'b111111;
12'd1542 : mem_out_dec = 6'b111111;
12'd1543 : mem_out_dec = 6'b111111;
12'd1544 : mem_out_dec = 6'b111111;
12'd1545 : mem_out_dec = 6'b111111;
12'd1546 : mem_out_dec = 6'b111111;
12'd1547 : mem_out_dec = 6'b111111;
12'd1548 : mem_out_dec = 6'b111111;
12'd1549 : mem_out_dec = 6'b111111;
12'd1550 : mem_out_dec = 6'b111111;
12'd1551 : mem_out_dec = 6'b111111;
12'd1552 : mem_out_dec = 6'b111111;
12'd1553 : mem_out_dec = 6'b111111;
12'd1554 : mem_out_dec = 6'b111111;
12'd1555 : mem_out_dec = 6'b111111;
12'd1556 : mem_out_dec = 6'b111111;
12'd1557 : mem_out_dec = 6'b111111;
12'd1558 : mem_out_dec = 6'b111111;
12'd1559 : mem_out_dec = 6'b111111;
12'd1560 : mem_out_dec = 6'b111111;
12'd1561 : mem_out_dec = 6'b111111;
12'd1562 : mem_out_dec = 6'b111111;
12'd1563 : mem_out_dec = 6'b111111;
12'd1564 : mem_out_dec = 6'b111111;
12'd1565 : mem_out_dec = 6'b111111;
12'd1566 : mem_out_dec = 6'b000100;
12'd1567 : mem_out_dec = 6'b000100;
12'd1568 : mem_out_dec = 6'b000100;
12'd1569 : mem_out_dec = 6'b000100;
12'd1570 : mem_out_dec = 6'b000100;
12'd1571 : mem_out_dec = 6'b000101;
12'd1572 : mem_out_dec = 6'b000101;
12'd1573 : mem_out_dec = 6'b000110;
12'd1574 : mem_out_dec = 6'b000111;
12'd1575 : mem_out_dec = 6'b000111;
12'd1576 : mem_out_dec = 6'b000111;
12'd1577 : mem_out_dec = 6'b001000;
12'd1578 : mem_out_dec = 6'b001001;
12'd1579 : mem_out_dec = 6'b001010;
12'd1580 : mem_out_dec = 6'b001010;
12'd1581 : mem_out_dec = 6'b001011;
12'd1582 : mem_out_dec = 6'b001100;
12'd1583 : mem_out_dec = 6'b001101;
12'd1584 : mem_out_dec = 6'b001101;
12'd1585 : mem_out_dec = 6'b001101;
12'd1586 : mem_out_dec = 6'b001110;
12'd1587 : mem_out_dec = 6'b001110;
12'd1588 : mem_out_dec = 6'b001111;
12'd1589 : mem_out_dec = 6'b001111;
12'd1590 : mem_out_dec = 6'b010000;
12'd1591 : mem_out_dec = 6'b010001;
12'd1592 : mem_out_dec = 6'b010001;
12'd1593 : mem_out_dec = 6'b010001;
12'd1594 : mem_out_dec = 6'b010010;
12'd1595 : mem_out_dec = 6'b010010;
12'd1596 : mem_out_dec = 6'b010011;
12'd1597 : mem_out_dec = 6'b010011;
12'd1598 : mem_out_dec = 6'b010100;
12'd1599 : mem_out_dec = 6'b010100;
12'd1600 : mem_out_dec = 6'b111111;
12'd1601 : mem_out_dec = 6'b111111;
12'd1602 : mem_out_dec = 6'b111111;
12'd1603 : mem_out_dec = 6'b111111;
12'd1604 : mem_out_dec = 6'b111111;
12'd1605 : mem_out_dec = 6'b111111;
12'd1606 : mem_out_dec = 6'b111111;
12'd1607 : mem_out_dec = 6'b111111;
12'd1608 : mem_out_dec = 6'b111111;
12'd1609 : mem_out_dec = 6'b111111;
12'd1610 : mem_out_dec = 6'b111111;
12'd1611 : mem_out_dec = 6'b111111;
12'd1612 : mem_out_dec = 6'b111111;
12'd1613 : mem_out_dec = 6'b111111;
12'd1614 : mem_out_dec = 6'b111111;
12'd1615 : mem_out_dec = 6'b111111;
12'd1616 : mem_out_dec = 6'b111111;
12'd1617 : mem_out_dec = 6'b111111;
12'd1618 : mem_out_dec = 6'b111111;
12'd1619 : mem_out_dec = 6'b111111;
12'd1620 : mem_out_dec = 6'b111111;
12'd1621 : mem_out_dec = 6'b111111;
12'd1622 : mem_out_dec = 6'b111111;
12'd1623 : mem_out_dec = 6'b111111;
12'd1624 : mem_out_dec = 6'b111111;
12'd1625 : mem_out_dec = 6'b111111;
12'd1626 : mem_out_dec = 6'b111111;
12'd1627 : mem_out_dec = 6'b111111;
12'd1628 : mem_out_dec = 6'b111111;
12'd1629 : mem_out_dec = 6'b111111;
12'd1630 : mem_out_dec = 6'b111111;
12'd1631 : mem_out_dec = 6'b000100;
12'd1632 : mem_out_dec = 6'b000011;
12'd1633 : mem_out_dec = 6'b000011;
12'd1634 : mem_out_dec = 6'b000100;
12'd1635 : mem_out_dec = 6'b000100;
12'd1636 : mem_out_dec = 6'b000101;
12'd1637 : mem_out_dec = 6'b000110;
12'd1638 : mem_out_dec = 6'b000110;
12'd1639 : mem_out_dec = 6'b000111;
12'd1640 : mem_out_dec = 6'b000111;
12'd1641 : mem_out_dec = 6'b001000;
12'd1642 : mem_out_dec = 6'b001001;
12'd1643 : mem_out_dec = 6'b001001;
12'd1644 : mem_out_dec = 6'b001010;
12'd1645 : mem_out_dec = 6'b001011;
12'd1646 : mem_out_dec = 6'b001100;
12'd1647 : mem_out_dec = 6'b001101;
12'd1648 : mem_out_dec = 6'b001101;
12'd1649 : mem_out_dec = 6'b001101;
12'd1650 : mem_out_dec = 6'b001110;
12'd1651 : mem_out_dec = 6'b001110;
12'd1652 : mem_out_dec = 6'b001110;
12'd1653 : mem_out_dec = 6'b001111;
12'd1654 : mem_out_dec = 6'b010000;
12'd1655 : mem_out_dec = 6'b010000;
12'd1656 : mem_out_dec = 6'b010001;
12'd1657 : mem_out_dec = 6'b010001;
12'd1658 : mem_out_dec = 6'b010001;
12'd1659 : mem_out_dec = 6'b010010;
12'd1660 : mem_out_dec = 6'b010010;
12'd1661 : mem_out_dec = 6'b010011;
12'd1662 : mem_out_dec = 6'b010011;
12'd1663 : mem_out_dec = 6'b010100;
12'd1664 : mem_out_dec = 6'b111111;
12'd1665 : mem_out_dec = 6'b111111;
12'd1666 : mem_out_dec = 6'b111111;
12'd1667 : mem_out_dec = 6'b111111;
12'd1668 : mem_out_dec = 6'b111111;
12'd1669 : mem_out_dec = 6'b111111;
12'd1670 : mem_out_dec = 6'b111111;
12'd1671 : mem_out_dec = 6'b111111;
12'd1672 : mem_out_dec = 6'b111111;
12'd1673 : mem_out_dec = 6'b111111;
12'd1674 : mem_out_dec = 6'b111111;
12'd1675 : mem_out_dec = 6'b111111;
12'd1676 : mem_out_dec = 6'b111111;
12'd1677 : mem_out_dec = 6'b111111;
12'd1678 : mem_out_dec = 6'b111111;
12'd1679 : mem_out_dec = 6'b111111;
12'd1680 : mem_out_dec = 6'b111111;
12'd1681 : mem_out_dec = 6'b111111;
12'd1682 : mem_out_dec = 6'b111111;
12'd1683 : mem_out_dec = 6'b111111;
12'd1684 : mem_out_dec = 6'b111111;
12'd1685 : mem_out_dec = 6'b111111;
12'd1686 : mem_out_dec = 6'b111111;
12'd1687 : mem_out_dec = 6'b111111;
12'd1688 : mem_out_dec = 6'b111111;
12'd1689 : mem_out_dec = 6'b111111;
12'd1690 : mem_out_dec = 6'b111111;
12'd1691 : mem_out_dec = 6'b111111;
12'd1692 : mem_out_dec = 6'b111111;
12'd1693 : mem_out_dec = 6'b111111;
12'd1694 : mem_out_dec = 6'b111111;
12'd1695 : mem_out_dec = 6'b111111;
12'd1696 : mem_out_dec = 6'b000011;
12'd1697 : mem_out_dec = 6'b000011;
12'd1698 : mem_out_dec = 6'b000100;
12'd1699 : mem_out_dec = 6'b000100;
12'd1700 : mem_out_dec = 6'b000101;
12'd1701 : mem_out_dec = 6'b000101;
12'd1702 : mem_out_dec = 6'b000110;
12'd1703 : mem_out_dec = 6'b000111;
12'd1704 : mem_out_dec = 6'b000111;
12'd1705 : mem_out_dec = 6'b001000;
12'd1706 : mem_out_dec = 6'b001000;
12'd1707 : mem_out_dec = 6'b001001;
12'd1708 : mem_out_dec = 6'b001010;
12'd1709 : mem_out_dec = 6'b001011;
12'd1710 : mem_out_dec = 6'b001100;
12'd1711 : mem_out_dec = 6'b001100;
12'd1712 : mem_out_dec = 6'b001100;
12'd1713 : mem_out_dec = 6'b001101;
12'd1714 : mem_out_dec = 6'b001101;
12'd1715 : mem_out_dec = 6'b001110;
12'd1716 : mem_out_dec = 6'b001110;
12'd1717 : mem_out_dec = 6'b001111;
12'd1718 : mem_out_dec = 6'b001111;
12'd1719 : mem_out_dec = 6'b010000;
12'd1720 : mem_out_dec = 6'b010000;
12'd1721 : mem_out_dec = 6'b010000;
12'd1722 : mem_out_dec = 6'b010001;
12'd1723 : mem_out_dec = 6'b010001;
12'd1724 : mem_out_dec = 6'b010010;
12'd1725 : mem_out_dec = 6'b010010;
12'd1726 : mem_out_dec = 6'b010011;
12'd1727 : mem_out_dec = 6'b010011;
12'd1728 : mem_out_dec = 6'b111111;
12'd1729 : mem_out_dec = 6'b111111;
12'd1730 : mem_out_dec = 6'b111111;
12'd1731 : mem_out_dec = 6'b111111;
12'd1732 : mem_out_dec = 6'b111111;
12'd1733 : mem_out_dec = 6'b111111;
12'd1734 : mem_out_dec = 6'b111111;
12'd1735 : mem_out_dec = 6'b111111;
12'd1736 : mem_out_dec = 6'b111111;
12'd1737 : mem_out_dec = 6'b111111;
12'd1738 : mem_out_dec = 6'b111111;
12'd1739 : mem_out_dec = 6'b111111;
12'd1740 : mem_out_dec = 6'b111111;
12'd1741 : mem_out_dec = 6'b111111;
12'd1742 : mem_out_dec = 6'b111111;
12'd1743 : mem_out_dec = 6'b111111;
12'd1744 : mem_out_dec = 6'b111111;
12'd1745 : mem_out_dec = 6'b111111;
12'd1746 : mem_out_dec = 6'b111111;
12'd1747 : mem_out_dec = 6'b111111;
12'd1748 : mem_out_dec = 6'b111111;
12'd1749 : mem_out_dec = 6'b111111;
12'd1750 : mem_out_dec = 6'b111111;
12'd1751 : mem_out_dec = 6'b111111;
12'd1752 : mem_out_dec = 6'b111111;
12'd1753 : mem_out_dec = 6'b111111;
12'd1754 : mem_out_dec = 6'b111111;
12'd1755 : mem_out_dec = 6'b111111;
12'd1756 : mem_out_dec = 6'b111111;
12'd1757 : mem_out_dec = 6'b111111;
12'd1758 : mem_out_dec = 6'b111111;
12'd1759 : mem_out_dec = 6'b111111;
12'd1760 : mem_out_dec = 6'b111111;
12'd1761 : mem_out_dec = 6'b000011;
12'd1762 : mem_out_dec = 6'b000011;
12'd1763 : mem_out_dec = 6'b000100;
12'd1764 : mem_out_dec = 6'b000101;
12'd1765 : mem_out_dec = 6'b000101;
12'd1766 : mem_out_dec = 6'b000110;
12'd1767 : mem_out_dec = 6'b000111;
12'd1768 : mem_out_dec = 6'b000111;
12'd1769 : mem_out_dec = 6'b000111;
12'd1770 : mem_out_dec = 6'b001000;
12'd1771 : mem_out_dec = 6'b001001;
12'd1772 : mem_out_dec = 6'b001010;
12'd1773 : mem_out_dec = 6'b001011;
12'd1774 : mem_out_dec = 6'b001011;
12'd1775 : mem_out_dec = 6'b001100;
12'd1776 : mem_out_dec = 6'b001100;
12'd1777 : mem_out_dec = 6'b001101;
12'd1778 : mem_out_dec = 6'b001101;
12'd1779 : mem_out_dec = 6'b001101;
12'd1780 : mem_out_dec = 6'b001110;
12'd1781 : mem_out_dec = 6'b001111;
12'd1782 : mem_out_dec = 6'b001111;
12'd1783 : mem_out_dec = 6'b010000;
12'd1784 : mem_out_dec = 6'b010000;
12'd1785 : mem_out_dec = 6'b010000;
12'd1786 : mem_out_dec = 6'b010000;
12'd1787 : mem_out_dec = 6'b010001;
12'd1788 : mem_out_dec = 6'b010001;
12'd1789 : mem_out_dec = 6'b010010;
12'd1790 : mem_out_dec = 6'b010010;
12'd1791 : mem_out_dec = 6'b010011;
12'd1792 : mem_out_dec = 6'b111111;
12'd1793 : mem_out_dec = 6'b111111;
12'd1794 : mem_out_dec = 6'b111111;
12'd1795 : mem_out_dec = 6'b111111;
12'd1796 : mem_out_dec = 6'b111111;
12'd1797 : mem_out_dec = 6'b111111;
12'd1798 : mem_out_dec = 6'b111111;
12'd1799 : mem_out_dec = 6'b111111;
12'd1800 : mem_out_dec = 6'b111111;
12'd1801 : mem_out_dec = 6'b111111;
12'd1802 : mem_out_dec = 6'b111111;
12'd1803 : mem_out_dec = 6'b111111;
12'd1804 : mem_out_dec = 6'b111111;
12'd1805 : mem_out_dec = 6'b111111;
12'd1806 : mem_out_dec = 6'b111111;
12'd1807 : mem_out_dec = 6'b111111;
12'd1808 : mem_out_dec = 6'b111111;
12'd1809 : mem_out_dec = 6'b111111;
12'd1810 : mem_out_dec = 6'b111111;
12'd1811 : mem_out_dec = 6'b111111;
12'd1812 : mem_out_dec = 6'b111111;
12'd1813 : mem_out_dec = 6'b111111;
12'd1814 : mem_out_dec = 6'b111111;
12'd1815 : mem_out_dec = 6'b111111;
12'd1816 : mem_out_dec = 6'b111111;
12'd1817 : mem_out_dec = 6'b111111;
12'd1818 : mem_out_dec = 6'b111111;
12'd1819 : mem_out_dec = 6'b111111;
12'd1820 : mem_out_dec = 6'b111111;
12'd1821 : mem_out_dec = 6'b111111;
12'd1822 : mem_out_dec = 6'b111111;
12'd1823 : mem_out_dec = 6'b111111;
12'd1824 : mem_out_dec = 6'b111111;
12'd1825 : mem_out_dec = 6'b111111;
12'd1826 : mem_out_dec = 6'b000011;
12'd1827 : mem_out_dec = 6'b000100;
12'd1828 : mem_out_dec = 6'b000100;
12'd1829 : mem_out_dec = 6'b000101;
12'd1830 : mem_out_dec = 6'b000110;
12'd1831 : mem_out_dec = 6'b000110;
12'd1832 : mem_out_dec = 6'b000110;
12'd1833 : mem_out_dec = 6'b000111;
12'd1834 : mem_out_dec = 6'b001000;
12'd1835 : mem_out_dec = 6'b001001;
12'd1836 : mem_out_dec = 6'b001010;
12'd1837 : mem_out_dec = 6'b001010;
12'd1838 : mem_out_dec = 6'b001011;
12'd1839 : mem_out_dec = 6'b001100;
12'd1840 : mem_out_dec = 6'b001100;
12'd1841 : mem_out_dec = 6'b001100;
12'd1842 : mem_out_dec = 6'b001101;
12'd1843 : mem_out_dec = 6'b001101;
12'd1844 : mem_out_dec = 6'b001110;
12'd1845 : mem_out_dec = 6'b001110;
12'd1846 : mem_out_dec = 6'b001111;
12'd1847 : mem_out_dec = 6'b010000;
12'd1848 : mem_out_dec = 6'b001111;
12'd1849 : mem_out_dec = 6'b001111;
12'd1850 : mem_out_dec = 6'b010000;
12'd1851 : mem_out_dec = 6'b010000;
12'd1852 : mem_out_dec = 6'b010001;
12'd1853 : mem_out_dec = 6'b010001;
12'd1854 : mem_out_dec = 6'b010010;
12'd1855 : mem_out_dec = 6'b010010;
12'd1856 : mem_out_dec = 6'b111111;
12'd1857 : mem_out_dec = 6'b111111;
12'd1858 : mem_out_dec = 6'b111111;
12'd1859 : mem_out_dec = 6'b111111;
12'd1860 : mem_out_dec = 6'b111111;
12'd1861 : mem_out_dec = 6'b111111;
12'd1862 : mem_out_dec = 6'b111111;
12'd1863 : mem_out_dec = 6'b111111;
12'd1864 : mem_out_dec = 6'b111111;
12'd1865 : mem_out_dec = 6'b111111;
12'd1866 : mem_out_dec = 6'b111111;
12'd1867 : mem_out_dec = 6'b111111;
12'd1868 : mem_out_dec = 6'b111111;
12'd1869 : mem_out_dec = 6'b111111;
12'd1870 : mem_out_dec = 6'b111111;
12'd1871 : mem_out_dec = 6'b111111;
12'd1872 : mem_out_dec = 6'b111111;
12'd1873 : mem_out_dec = 6'b111111;
12'd1874 : mem_out_dec = 6'b111111;
12'd1875 : mem_out_dec = 6'b111111;
12'd1876 : mem_out_dec = 6'b111111;
12'd1877 : mem_out_dec = 6'b111111;
12'd1878 : mem_out_dec = 6'b111111;
12'd1879 : mem_out_dec = 6'b111111;
12'd1880 : mem_out_dec = 6'b111111;
12'd1881 : mem_out_dec = 6'b111111;
12'd1882 : mem_out_dec = 6'b111111;
12'd1883 : mem_out_dec = 6'b111111;
12'd1884 : mem_out_dec = 6'b111111;
12'd1885 : mem_out_dec = 6'b111111;
12'd1886 : mem_out_dec = 6'b111111;
12'd1887 : mem_out_dec = 6'b111111;
12'd1888 : mem_out_dec = 6'b111111;
12'd1889 : mem_out_dec = 6'b111111;
12'd1890 : mem_out_dec = 6'b111111;
12'd1891 : mem_out_dec = 6'b000100;
12'd1892 : mem_out_dec = 6'b000100;
12'd1893 : mem_out_dec = 6'b000101;
12'd1894 : mem_out_dec = 6'b000101;
12'd1895 : mem_out_dec = 6'b000110;
12'd1896 : mem_out_dec = 6'b000110;
12'd1897 : mem_out_dec = 6'b000111;
12'd1898 : mem_out_dec = 6'b001000;
12'd1899 : mem_out_dec = 6'b001001;
12'd1900 : mem_out_dec = 6'b001001;
12'd1901 : mem_out_dec = 6'b001010;
12'd1902 : mem_out_dec = 6'b001011;
12'd1903 : mem_out_dec = 6'b001100;
12'd1904 : mem_out_dec = 6'b001100;
12'd1905 : mem_out_dec = 6'b001100;
12'd1906 : mem_out_dec = 6'b001100;
12'd1907 : mem_out_dec = 6'b001101;
12'd1908 : mem_out_dec = 6'b001110;
12'd1909 : mem_out_dec = 6'b001110;
12'd1910 : mem_out_dec = 6'b001111;
12'd1911 : mem_out_dec = 6'b001111;
12'd1912 : mem_out_dec = 6'b001111;
12'd1913 : mem_out_dec = 6'b001111;
12'd1914 : mem_out_dec = 6'b001111;
12'd1915 : mem_out_dec = 6'b010000;
12'd1916 : mem_out_dec = 6'b010000;
12'd1917 : mem_out_dec = 6'b010001;
12'd1918 : mem_out_dec = 6'b010001;
12'd1919 : mem_out_dec = 6'b010010;
12'd1920 : mem_out_dec = 6'b111111;
12'd1921 : mem_out_dec = 6'b111111;
12'd1922 : mem_out_dec = 6'b111111;
12'd1923 : mem_out_dec = 6'b111111;
12'd1924 : mem_out_dec = 6'b111111;
12'd1925 : mem_out_dec = 6'b111111;
12'd1926 : mem_out_dec = 6'b111111;
12'd1927 : mem_out_dec = 6'b111111;
12'd1928 : mem_out_dec = 6'b111111;
12'd1929 : mem_out_dec = 6'b111111;
12'd1930 : mem_out_dec = 6'b111111;
12'd1931 : mem_out_dec = 6'b111111;
12'd1932 : mem_out_dec = 6'b111111;
12'd1933 : mem_out_dec = 6'b111111;
12'd1934 : mem_out_dec = 6'b111111;
12'd1935 : mem_out_dec = 6'b111111;
12'd1936 : mem_out_dec = 6'b111111;
12'd1937 : mem_out_dec = 6'b111111;
12'd1938 : mem_out_dec = 6'b111111;
12'd1939 : mem_out_dec = 6'b111111;
12'd1940 : mem_out_dec = 6'b111111;
12'd1941 : mem_out_dec = 6'b111111;
12'd1942 : mem_out_dec = 6'b111111;
12'd1943 : mem_out_dec = 6'b111111;
12'd1944 : mem_out_dec = 6'b111111;
12'd1945 : mem_out_dec = 6'b111111;
12'd1946 : mem_out_dec = 6'b111111;
12'd1947 : mem_out_dec = 6'b111111;
12'd1948 : mem_out_dec = 6'b111111;
12'd1949 : mem_out_dec = 6'b111111;
12'd1950 : mem_out_dec = 6'b111111;
12'd1951 : mem_out_dec = 6'b111111;
12'd1952 : mem_out_dec = 6'b111111;
12'd1953 : mem_out_dec = 6'b111111;
12'd1954 : mem_out_dec = 6'b111111;
12'd1955 : mem_out_dec = 6'b111111;
12'd1956 : mem_out_dec = 6'b000100;
12'd1957 : mem_out_dec = 6'b000101;
12'd1958 : mem_out_dec = 6'b000101;
12'd1959 : mem_out_dec = 6'b000110;
12'd1960 : mem_out_dec = 6'b000110;
12'd1961 : mem_out_dec = 6'b000111;
12'd1962 : mem_out_dec = 6'b001000;
12'd1963 : mem_out_dec = 6'b001000;
12'd1964 : mem_out_dec = 6'b001001;
12'd1965 : mem_out_dec = 6'b001010;
12'd1966 : mem_out_dec = 6'b001011;
12'd1967 : mem_out_dec = 6'b001011;
12'd1968 : mem_out_dec = 6'b001011;
12'd1969 : mem_out_dec = 6'b001100;
12'd1970 : mem_out_dec = 6'b001100;
12'd1971 : mem_out_dec = 6'b001101;
12'd1972 : mem_out_dec = 6'b001101;
12'd1973 : mem_out_dec = 6'b001110;
12'd1974 : mem_out_dec = 6'b001111;
12'd1975 : mem_out_dec = 6'b001111;
12'd1976 : mem_out_dec = 6'b001110;
12'd1977 : mem_out_dec = 6'b001110;
12'd1978 : mem_out_dec = 6'b001111;
12'd1979 : mem_out_dec = 6'b001111;
12'd1980 : mem_out_dec = 6'b010000;
12'd1981 : mem_out_dec = 6'b010000;
12'd1982 : mem_out_dec = 6'b010001;
12'd1983 : mem_out_dec = 6'b010001;
12'd1984 : mem_out_dec = 6'b111111;
12'd1985 : mem_out_dec = 6'b111111;
12'd1986 : mem_out_dec = 6'b111111;
12'd1987 : mem_out_dec = 6'b111111;
12'd1988 : mem_out_dec = 6'b111111;
12'd1989 : mem_out_dec = 6'b111111;
12'd1990 : mem_out_dec = 6'b111111;
12'd1991 : mem_out_dec = 6'b111111;
12'd1992 : mem_out_dec = 6'b111111;
12'd1993 : mem_out_dec = 6'b111111;
12'd1994 : mem_out_dec = 6'b111111;
12'd1995 : mem_out_dec = 6'b111111;
12'd1996 : mem_out_dec = 6'b111111;
12'd1997 : mem_out_dec = 6'b111111;
12'd1998 : mem_out_dec = 6'b111111;
12'd1999 : mem_out_dec = 6'b111111;
12'd2000 : mem_out_dec = 6'b111111;
12'd2001 : mem_out_dec = 6'b111111;
12'd2002 : mem_out_dec = 6'b111111;
12'd2003 : mem_out_dec = 6'b111111;
12'd2004 : mem_out_dec = 6'b111111;
12'd2005 : mem_out_dec = 6'b111111;
12'd2006 : mem_out_dec = 6'b111111;
12'd2007 : mem_out_dec = 6'b111111;
12'd2008 : mem_out_dec = 6'b111111;
12'd2009 : mem_out_dec = 6'b111111;
12'd2010 : mem_out_dec = 6'b111111;
12'd2011 : mem_out_dec = 6'b111111;
12'd2012 : mem_out_dec = 6'b111111;
12'd2013 : mem_out_dec = 6'b111111;
12'd2014 : mem_out_dec = 6'b111111;
12'd2015 : mem_out_dec = 6'b111111;
12'd2016 : mem_out_dec = 6'b111111;
12'd2017 : mem_out_dec = 6'b111111;
12'd2018 : mem_out_dec = 6'b111111;
12'd2019 : mem_out_dec = 6'b111111;
12'd2020 : mem_out_dec = 6'b111111;
12'd2021 : mem_out_dec = 6'b000100;
12'd2022 : mem_out_dec = 6'b000101;
12'd2023 : mem_out_dec = 6'b000110;
12'd2024 : mem_out_dec = 6'b000110;
12'd2025 : mem_out_dec = 6'b000111;
12'd2026 : mem_out_dec = 6'b000111;
12'd2027 : mem_out_dec = 6'b001000;
12'd2028 : mem_out_dec = 6'b001001;
12'd2029 : mem_out_dec = 6'b001010;
12'd2030 : mem_out_dec = 6'b001010;
12'd2031 : mem_out_dec = 6'b001011;
12'd2032 : mem_out_dec = 6'b001011;
12'd2033 : mem_out_dec = 6'b001011;
12'd2034 : mem_out_dec = 6'b001100;
12'd2035 : mem_out_dec = 6'b001101;
12'd2036 : mem_out_dec = 6'b001101;
12'd2037 : mem_out_dec = 6'b001110;
12'd2038 : mem_out_dec = 6'b001110;
12'd2039 : mem_out_dec = 6'b001110;
12'd2040 : mem_out_dec = 6'b001101;
12'd2041 : mem_out_dec = 6'b001110;
12'd2042 : mem_out_dec = 6'b001110;
12'd2043 : mem_out_dec = 6'b001111;
12'd2044 : mem_out_dec = 6'b001111;
12'd2045 : mem_out_dec = 6'b010000;
12'd2046 : mem_out_dec = 6'b010000;
12'd2047 : mem_out_dec = 6'b010001;
12'd2048 : mem_out_dec = 6'b111111;
12'd2049 : mem_out_dec = 6'b111111;
12'd2050 : mem_out_dec = 6'b111111;
12'd2051 : mem_out_dec = 6'b111111;
12'd2052 : mem_out_dec = 6'b111111;
12'd2053 : mem_out_dec = 6'b111111;
12'd2054 : mem_out_dec = 6'b111111;
12'd2055 : mem_out_dec = 6'b111111;
12'd2056 : mem_out_dec = 6'b111111;
12'd2057 : mem_out_dec = 6'b111111;
12'd2058 : mem_out_dec = 6'b111111;
12'd2059 : mem_out_dec = 6'b111111;
12'd2060 : mem_out_dec = 6'b111111;
12'd2061 : mem_out_dec = 6'b111111;
12'd2062 : mem_out_dec = 6'b111111;
12'd2063 : mem_out_dec = 6'b111111;
12'd2064 : mem_out_dec = 6'b111111;
12'd2065 : mem_out_dec = 6'b111111;
12'd2066 : mem_out_dec = 6'b111111;
12'd2067 : mem_out_dec = 6'b111111;
12'd2068 : mem_out_dec = 6'b111111;
12'd2069 : mem_out_dec = 6'b111111;
12'd2070 : mem_out_dec = 6'b111111;
12'd2071 : mem_out_dec = 6'b111111;
12'd2072 : mem_out_dec = 6'b111111;
12'd2073 : mem_out_dec = 6'b111111;
12'd2074 : mem_out_dec = 6'b111111;
12'd2075 : mem_out_dec = 6'b111111;
12'd2076 : mem_out_dec = 6'b111111;
12'd2077 : mem_out_dec = 6'b111111;
12'd2078 : mem_out_dec = 6'b111111;
12'd2079 : mem_out_dec = 6'b111111;
12'd2080 : mem_out_dec = 6'b111111;
12'd2081 : mem_out_dec = 6'b111111;
12'd2082 : mem_out_dec = 6'b111111;
12'd2083 : mem_out_dec = 6'b111111;
12'd2084 : mem_out_dec = 6'b111111;
12'd2085 : mem_out_dec = 6'b111111;
12'd2086 : mem_out_dec = 6'b000100;
12'd2087 : mem_out_dec = 6'b000101;
12'd2088 : mem_out_dec = 6'b000101;
12'd2089 : mem_out_dec = 6'b000110;
12'd2090 : mem_out_dec = 6'b000110;
12'd2091 : mem_out_dec = 6'b000111;
12'd2092 : mem_out_dec = 6'b001000;
12'd2093 : mem_out_dec = 6'b001001;
12'd2094 : mem_out_dec = 6'b001001;
12'd2095 : mem_out_dec = 6'b001010;
12'd2096 : mem_out_dec = 6'b001010;
12'd2097 : mem_out_dec = 6'b001011;
12'd2098 : mem_out_dec = 6'b001011;
12'd2099 : mem_out_dec = 6'b001100;
12'd2100 : mem_out_dec = 6'b001100;
12'd2101 : mem_out_dec = 6'b001100;
12'd2102 : mem_out_dec = 6'b001100;
12'd2103 : mem_out_dec = 6'b001101;
12'd2104 : mem_out_dec = 6'b001100;
12'd2105 : mem_out_dec = 6'b001100;
12'd2106 : mem_out_dec = 6'b001101;
12'd2107 : mem_out_dec = 6'b001101;
12'd2108 : mem_out_dec = 6'b001110;
12'd2109 : mem_out_dec = 6'b001111;
12'd2110 : mem_out_dec = 6'b010000;
12'd2111 : mem_out_dec = 6'b010000;
12'd2112 : mem_out_dec = 6'b111111;
12'd2113 : mem_out_dec = 6'b111111;
12'd2114 : mem_out_dec = 6'b111111;
12'd2115 : mem_out_dec = 6'b111111;
12'd2116 : mem_out_dec = 6'b111111;
12'd2117 : mem_out_dec = 6'b111111;
12'd2118 : mem_out_dec = 6'b111111;
12'd2119 : mem_out_dec = 6'b111111;
12'd2120 : mem_out_dec = 6'b111111;
12'd2121 : mem_out_dec = 6'b111111;
12'd2122 : mem_out_dec = 6'b111111;
12'd2123 : mem_out_dec = 6'b111111;
12'd2124 : mem_out_dec = 6'b111111;
12'd2125 : mem_out_dec = 6'b111111;
12'd2126 : mem_out_dec = 6'b111111;
12'd2127 : mem_out_dec = 6'b111111;
12'd2128 : mem_out_dec = 6'b111111;
12'd2129 : mem_out_dec = 6'b111111;
12'd2130 : mem_out_dec = 6'b111111;
12'd2131 : mem_out_dec = 6'b111111;
12'd2132 : mem_out_dec = 6'b111111;
12'd2133 : mem_out_dec = 6'b111111;
12'd2134 : mem_out_dec = 6'b111111;
12'd2135 : mem_out_dec = 6'b111111;
12'd2136 : mem_out_dec = 6'b111111;
12'd2137 : mem_out_dec = 6'b111111;
12'd2138 : mem_out_dec = 6'b111111;
12'd2139 : mem_out_dec = 6'b111111;
12'd2140 : mem_out_dec = 6'b111111;
12'd2141 : mem_out_dec = 6'b111111;
12'd2142 : mem_out_dec = 6'b111111;
12'd2143 : mem_out_dec = 6'b111111;
12'd2144 : mem_out_dec = 6'b111111;
12'd2145 : mem_out_dec = 6'b111111;
12'd2146 : mem_out_dec = 6'b111111;
12'd2147 : mem_out_dec = 6'b111111;
12'd2148 : mem_out_dec = 6'b111111;
12'd2149 : mem_out_dec = 6'b111111;
12'd2150 : mem_out_dec = 6'b111111;
12'd2151 : mem_out_dec = 6'b000100;
12'd2152 : mem_out_dec = 6'b000100;
12'd2153 : mem_out_dec = 6'b000101;
12'd2154 : mem_out_dec = 6'b000110;
12'd2155 : mem_out_dec = 6'b000111;
12'd2156 : mem_out_dec = 6'b000111;
12'd2157 : mem_out_dec = 6'b001000;
12'd2158 : mem_out_dec = 6'b001001;
12'd2159 : mem_out_dec = 6'b001001;
12'd2160 : mem_out_dec = 6'b001010;
12'd2161 : mem_out_dec = 6'b001010;
12'd2162 : mem_out_dec = 6'b001011;
12'd2163 : mem_out_dec = 6'b001011;
12'd2164 : mem_out_dec = 6'b001011;
12'd2165 : mem_out_dec = 6'b001011;
12'd2166 : mem_out_dec = 6'b001011;
12'd2167 : mem_out_dec = 6'b001100;
12'd2168 : mem_out_dec = 6'b001011;
12'd2169 : mem_out_dec = 6'b001011;
12'd2170 : mem_out_dec = 6'b001100;
12'd2171 : mem_out_dec = 6'b001101;
12'd2172 : mem_out_dec = 6'b001110;
12'd2173 : mem_out_dec = 6'b001110;
12'd2174 : mem_out_dec = 6'b001111;
12'd2175 : mem_out_dec = 6'b010000;
12'd2176 : mem_out_dec = 6'b111111;
12'd2177 : mem_out_dec = 6'b111111;
12'd2178 : mem_out_dec = 6'b111111;
12'd2179 : mem_out_dec = 6'b111111;
12'd2180 : mem_out_dec = 6'b111111;
12'd2181 : mem_out_dec = 6'b111111;
12'd2182 : mem_out_dec = 6'b111111;
12'd2183 : mem_out_dec = 6'b111111;
12'd2184 : mem_out_dec = 6'b111111;
12'd2185 : mem_out_dec = 6'b111111;
12'd2186 : mem_out_dec = 6'b111111;
12'd2187 : mem_out_dec = 6'b111111;
12'd2188 : mem_out_dec = 6'b111111;
12'd2189 : mem_out_dec = 6'b111111;
12'd2190 : mem_out_dec = 6'b111111;
12'd2191 : mem_out_dec = 6'b111111;
12'd2192 : mem_out_dec = 6'b111111;
12'd2193 : mem_out_dec = 6'b111111;
12'd2194 : mem_out_dec = 6'b111111;
12'd2195 : mem_out_dec = 6'b111111;
12'd2196 : mem_out_dec = 6'b111111;
12'd2197 : mem_out_dec = 6'b111111;
12'd2198 : mem_out_dec = 6'b111111;
12'd2199 : mem_out_dec = 6'b111111;
12'd2200 : mem_out_dec = 6'b111111;
12'd2201 : mem_out_dec = 6'b111111;
12'd2202 : mem_out_dec = 6'b111111;
12'd2203 : mem_out_dec = 6'b111111;
12'd2204 : mem_out_dec = 6'b111111;
12'd2205 : mem_out_dec = 6'b111111;
12'd2206 : mem_out_dec = 6'b111111;
12'd2207 : mem_out_dec = 6'b111111;
12'd2208 : mem_out_dec = 6'b111111;
12'd2209 : mem_out_dec = 6'b111111;
12'd2210 : mem_out_dec = 6'b111111;
12'd2211 : mem_out_dec = 6'b111111;
12'd2212 : mem_out_dec = 6'b111111;
12'd2213 : mem_out_dec = 6'b111111;
12'd2214 : mem_out_dec = 6'b111111;
12'd2215 : mem_out_dec = 6'b111111;
12'd2216 : mem_out_dec = 6'b000100;
12'd2217 : mem_out_dec = 6'b000101;
12'd2218 : mem_out_dec = 6'b000101;
12'd2219 : mem_out_dec = 6'b000110;
12'd2220 : mem_out_dec = 6'b000111;
12'd2221 : mem_out_dec = 6'b000111;
12'd2222 : mem_out_dec = 6'b001000;
12'd2223 : mem_out_dec = 6'b001001;
12'd2224 : mem_out_dec = 6'b001001;
12'd2225 : mem_out_dec = 6'b001010;
12'd2226 : mem_out_dec = 6'b001010;
12'd2227 : mem_out_dec = 6'b001010;
12'd2228 : mem_out_dec = 6'b001010;
12'd2229 : mem_out_dec = 6'b001010;
12'd2230 : mem_out_dec = 6'b001010;
12'd2231 : mem_out_dec = 6'b001010;
12'd2232 : mem_out_dec = 6'b001010;
12'd2233 : mem_out_dec = 6'b001011;
12'd2234 : mem_out_dec = 6'b001100;
12'd2235 : mem_out_dec = 6'b001100;
12'd2236 : mem_out_dec = 6'b001101;
12'd2237 : mem_out_dec = 6'b001110;
12'd2238 : mem_out_dec = 6'b001111;
12'd2239 : mem_out_dec = 6'b010000;
12'd2240 : mem_out_dec = 6'b111111;
12'd2241 : mem_out_dec = 6'b111111;
12'd2242 : mem_out_dec = 6'b111111;
12'd2243 : mem_out_dec = 6'b111111;
12'd2244 : mem_out_dec = 6'b111111;
12'd2245 : mem_out_dec = 6'b111111;
12'd2246 : mem_out_dec = 6'b111111;
12'd2247 : mem_out_dec = 6'b111111;
12'd2248 : mem_out_dec = 6'b111111;
12'd2249 : mem_out_dec = 6'b111111;
12'd2250 : mem_out_dec = 6'b111111;
12'd2251 : mem_out_dec = 6'b111111;
12'd2252 : mem_out_dec = 6'b111111;
12'd2253 : mem_out_dec = 6'b111111;
12'd2254 : mem_out_dec = 6'b111111;
12'd2255 : mem_out_dec = 6'b111111;
12'd2256 : mem_out_dec = 6'b111111;
12'd2257 : mem_out_dec = 6'b111111;
12'd2258 : mem_out_dec = 6'b111111;
12'd2259 : mem_out_dec = 6'b111111;
12'd2260 : mem_out_dec = 6'b111111;
12'd2261 : mem_out_dec = 6'b111111;
12'd2262 : mem_out_dec = 6'b111111;
12'd2263 : mem_out_dec = 6'b111111;
12'd2264 : mem_out_dec = 6'b111111;
12'd2265 : mem_out_dec = 6'b111111;
12'd2266 : mem_out_dec = 6'b111111;
12'd2267 : mem_out_dec = 6'b111111;
12'd2268 : mem_out_dec = 6'b111111;
12'd2269 : mem_out_dec = 6'b111111;
12'd2270 : mem_out_dec = 6'b111111;
12'd2271 : mem_out_dec = 6'b111111;
12'd2272 : mem_out_dec = 6'b111111;
12'd2273 : mem_out_dec = 6'b111111;
12'd2274 : mem_out_dec = 6'b111111;
12'd2275 : mem_out_dec = 6'b111111;
12'd2276 : mem_out_dec = 6'b111111;
12'd2277 : mem_out_dec = 6'b111111;
12'd2278 : mem_out_dec = 6'b111111;
12'd2279 : mem_out_dec = 6'b111111;
12'd2280 : mem_out_dec = 6'b111111;
12'd2281 : mem_out_dec = 6'b000100;
12'd2282 : mem_out_dec = 6'b000101;
12'd2283 : mem_out_dec = 6'b000101;
12'd2284 : mem_out_dec = 6'b000110;
12'd2285 : mem_out_dec = 6'b000111;
12'd2286 : mem_out_dec = 6'b001000;
12'd2287 : mem_out_dec = 6'b001001;
12'd2288 : mem_out_dec = 6'b001001;
12'd2289 : mem_out_dec = 6'b001001;
12'd2290 : mem_out_dec = 6'b001001;
12'd2291 : mem_out_dec = 6'b001001;
12'd2292 : mem_out_dec = 6'b001001;
12'd2293 : mem_out_dec = 6'b001001;
12'd2294 : mem_out_dec = 6'b001001;
12'd2295 : mem_out_dec = 6'b001001;
12'd2296 : mem_out_dec = 6'b001010;
12'd2297 : mem_out_dec = 6'b001010;
12'd2298 : mem_out_dec = 6'b001011;
12'd2299 : mem_out_dec = 6'b001100;
12'd2300 : mem_out_dec = 6'b001101;
12'd2301 : mem_out_dec = 6'b001110;
12'd2302 : mem_out_dec = 6'b001110;
12'd2303 : mem_out_dec = 6'b001111;
12'd2304 : mem_out_dec = 6'b111111;
12'd2305 : mem_out_dec = 6'b111111;
12'd2306 : mem_out_dec = 6'b111111;
12'd2307 : mem_out_dec = 6'b111111;
12'd2308 : mem_out_dec = 6'b111111;
12'd2309 : mem_out_dec = 6'b111111;
12'd2310 : mem_out_dec = 6'b111111;
12'd2311 : mem_out_dec = 6'b111111;
12'd2312 : mem_out_dec = 6'b111111;
12'd2313 : mem_out_dec = 6'b111111;
12'd2314 : mem_out_dec = 6'b111111;
12'd2315 : mem_out_dec = 6'b111111;
12'd2316 : mem_out_dec = 6'b111111;
12'd2317 : mem_out_dec = 6'b111111;
12'd2318 : mem_out_dec = 6'b111111;
12'd2319 : mem_out_dec = 6'b111111;
12'd2320 : mem_out_dec = 6'b111111;
12'd2321 : mem_out_dec = 6'b111111;
12'd2322 : mem_out_dec = 6'b111111;
12'd2323 : mem_out_dec = 6'b111111;
12'd2324 : mem_out_dec = 6'b111111;
12'd2325 : mem_out_dec = 6'b111111;
12'd2326 : mem_out_dec = 6'b111111;
12'd2327 : mem_out_dec = 6'b111111;
12'd2328 : mem_out_dec = 6'b111111;
12'd2329 : mem_out_dec = 6'b111111;
12'd2330 : mem_out_dec = 6'b111111;
12'd2331 : mem_out_dec = 6'b111111;
12'd2332 : mem_out_dec = 6'b111111;
12'd2333 : mem_out_dec = 6'b111111;
12'd2334 : mem_out_dec = 6'b111111;
12'd2335 : mem_out_dec = 6'b111111;
12'd2336 : mem_out_dec = 6'b111111;
12'd2337 : mem_out_dec = 6'b111111;
12'd2338 : mem_out_dec = 6'b111111;
12'd2339 : mem_out_dec = 6'b111111;
12'd2340 : mem_out_dec = 6'b111111;
12'd2341 : mem_out_dec = 6'b111111;
12'd2342 : mem_out_dec = 6'b111111;
12'd2343 : mem_out_dec = 6'b111111;
12'd2344 : mem_out_dec = 6'b111111;
12'd2345 : mem_out_dec = 6'b111111;
12'd2346 : mem_out_dec = 6'b000100;
12'd2347 : mem_out_dec = 6'b000101;
12'd2348 : mem_out_dec = 6'b000110;
12'd2349 : mem_out_dec = 6'b000111;
12'd2350 : mem_out_dec = 6'b000111;
12'd2351 : mem_out_dec = 6'b001000;
12'd2352 : mem_out_dec = 6'b001000;
12'd2353 : mem_out_dec = 6'b001000;
12'd2354 : mem_out_dec = 6'b001000;
12'd2355 : mem_out_dec = 6'b001000;
12'd2356 : mem_out_dec = 6'b001000;
12'd2357 : mem_out_dec = 6'b001000;
12'd2358 : mem_out_dec = 6'b001000;
12'd2359 : mem_out_dec = 6'b001001;
12'd2360 : mem_out_dec = 6'b001001;
12'd2361 : mem_out_dec = 6'b001010;
12'd2362 : mem_out_dec = 6'b001011;
12'd2363 : mem_out_dec = 6'b001100;
12'd2364 : mem_out_dec = 6'b001100;
12'd2365 : mem_out_dec = 6'b001101;
12'd2366 : mem_out_dec = 6'b001110;
12'd2367 : mem_out_dec = 6'b001111;
12'd2368 : mem_out_dec = 6'b111111;
12'd2369 : mem_out_dec = 6'b111111;
12'd2370 : mem_out_dec = 6'b111111;
12'd2371 : mem_out_dec = 6'b111111;
12'd2372 : mem_out_dec = 6'b111111;
12'd2373 : mem_out_dec = 6'b111111;
12'd2374 : mem_out_dec = 6'b111111;
12'd2375 : mem_out_dec = 6'b111111;
12'd2376 : mem_out_dec = 6'b111111;
12'd2377 : mem_out_dec = 6'b111111;
12'd2378 : mem_out_dec = 6'b111111;
12'd2379 : mem_out_dec = 6'b111111;
12'd2380 : mem_out_dec = 6'b111111;
12'd2381 : mem_out_dec = 6'b111111;
12'd2382 : mem_out_dec = 6'b111111;
12'd2383 : mem_out_dec = 6'b111111;
12'd2384 : mem_out_dec = 6'b111111;
12'd2385 : mem_out_dec = 6'b111111;
12'd2386 : mem_out_dec = 6'b111111;
12'd2387 : mem_out_dec = 6'b111111;
12'd2388 : mem_out_dec = 6'b111111;
12'd2389 : mem_out_dec = 6'b111111;
12'd2390 : mem_out_dec = 6'b111111;
12'd2391 : mem_out_dec = 6'b111111;
12'd2392 : mem_out_dec = 6'b111111;
12'd2393 : mem_out_dec = 6'b111111;
12'd2394 : mem_out_dec = 6'b111111;
12'd2395 : mem_out_dec = 6'b111111;
12'd2396 : mem_out_dec = 6'b111111;
12'd2397 : mem_out_dec = 6'b111111;
12'd2398 : mem_out_dec = 6'b111111;
12'd2399 : mem_out_dec = 6'b111111;
12'd2400 : mem_out_dec = 6'b111111;
12'd2401 : mem_out_dec = 6'b111111;
12'd2402 : mem_out_dec = 6'b111111;
12'd2403 : mem_out_dec = 6'b111111;
12'd2404 : mem_out_dec = 6'b111111;
12'd2405 : mem_out_dec = 6'b111111;
12'd2406 : mem_out_dec = 6'b111111;
12'd2407 : mem_out_dec = 6'b111111;
12'd2408 : mem_out_dec = 6'b111111;
12'd2409 : mem_out_dec = 6'b111111;
12'd2410 : mem_out_dec = 6'b111111;
12'd2411 : mem_out_dec = 6'b000101;
12'd2412 : mem_out_dec = 6'b000101;
12'd2413 : mem_out_dec = 6'b000110;
12'd2414 : mem_out_dec = 6'b000111;
12'd2415 : mem_out_dec = 6'b001000;
12'd2416 : mem_out_dec = 6'b000111;
12'd2417 : mem_out_dec = 6'b000111;
12'd2418 : mem_out_dec = 6'b000111;
12'd2419 : mem_out_dec = 6'b000111;
12'd2420 : mem_out_dec = 6'b000111;
12'd2421 : mem_out_dec = 6'b000111;
12'd2422 : mem_out_dec = 6'b001000;
12'd2423 : mem_out_dec = 6'b001001;
12'd2424 : mem_out_dec = 6'b001001;
12'd2425 : mem_out_dec = 6'b001010;
12'd2426 : mem_out_dec = 6'b001010;
12'd2427 : mem_out_dec = 6'b001011;
12'd2428 : mem_out_dec = 6'b001100;
12'd2429 : mem_out_dec = 6'b001101;
12'd2430 : mem_out_dec = 6'b001101;
12'd2431 : mem_out_dec = 6'b001110;
12'd2432 : mem_out_dec = 6'b111111;
12'd2433 : mem_out_dec = 6'b111111;
12'd2434 : mem_out_dec = 6'b111111;
12'd2435 : mem_out_dec = 6'b111111;
12'd2436 : mem_out_dec = 6'b111111;
12'd2437 : mem_out_dec = 6'b111111;
12'd2438 : mem_out_dec = 6'b111111;
12'd2439 : mem_out_dec = 6'b111111;
12'd2440 : mem_out_dec = 6'b111111;
12'd2441 : mem_out_dec = 6'b111111;
12'd2442 : mem_out_dec = 6'b111111;
12'd2443 : mem_out_dec = 6'b111111;
12'd2444 : mem_out_dec = 6'b111111;
12'd2445 : mem_out_dec = 6'b111111;
12'd2446 : mem_out_dec = 6'b111111;
12'd2447 : mem_out_dec = 6'b111111;
12'd2448 : mem_out_dec = 6'b111111;
12'd2449 : mem_out_dec = 6'b111111;
12'd2450 : mem_out_dec = 6'b111111;
12'd2451 : mem_out_dec = 6'b111111;
12'd2452 : mem_out_dec = 6'b111111;
12'd2453 : mem_out_dec = 6'b111111;
12'd2454 : mem_out_dec = 6'b111111;
12'd2455 : mem_out_dec = 6'b111111;
12'd2456 : mem_out_dec = 6'b111111;
12'd2457 : mem_out_dec = 6'b111111;
12'd2458 : mem_out_dec = 6'b111111;
12'd2459 : mem_out_dec = 6'b111111;
12'd2460 : mem_out_dec = 6'b111111;
12'd2461 : mem_out_dec = 6'b111111;
12'd2462 : mem_out_dec = 6'b111111;
12'd2463 : mem_out_dec = 6'b111111;
12'd2464 : mem_out_dec = 6'b111111;
12'd2465 : mem_out_dec = 6'b111111;
12'd2466 : mem_out_dec = 6'b111111;
12'd2467 : mem_out_dec = 6'b111111;
12'd2468 : mem_out_dec = 6'b111111;
12'd2469 : mem_out_dec = 6'b111111;
12'd2470 : mem_out_dec = 6'b111111;
12'd2471 : mem_out_dec = 6'b111111;
12'd2472 : mem_out_dec = 6'b111111;
12'd2473 : mem_out_dec = 6'b111111;
12'd2474 : mem_out_dec = 6'b111111;
12'd2475 : mem_out_dec = 6'b111111;
12'd2476 : mem_out_dec = 6'b000101;
12'd2477 : mem_out_dec = 6'b000110;
12'd2478 : mem_out_dec = 6'b000111;
12'd2479 : mem_out_dec = 6'b000111;
12'd2480 : mem_out_dec = 6'b000110;
12'd2481 : mem_out_dec = 6'b000110;
12'd2482 : mem_out_dec = 6'b000110;
12'd2483 : mem_out_dec = 6'b000110;
12'd2484 : mem_out_dec = 6'b000110;
12'd2485 : mem_out_dec = 6'b000111;
12'd2486 : mem_out_dec = 6'b000111;
12'd2487 : mem_out_dec = 6'b001000;
12'd2488 : mem_out_dec = 6'b001001;
12'd2489 : mem_out_dec = 6'b001001;
12'd2490 : mem_out_dec = 6'b001010;
12'd2491 : mem_out_dec = 6'b001011;
12'd2492 : mem_out_dec = 6'b001011;
12'd2493 : mem_out_dec = 6'b001100;
12'd2494 : mem_out_dec = 6'b001101;
12'd2495 : mem_out_dec = 6'b001110;
12'd2496 : mem_out_dec = 6'b111111;
12'd2497 : mem_out_dec = 6'b111111;
12'd2498 : mem_out_dec = 6'b111111;
12'd2499 : mem_out_dec = 6'b111111;
12'd2500 : mem_out_dec = 6'b111111;
12'd2501 : mem_out_dec = 6'b111111;
12'd2502 : mem_out_dec = 6'b111111;
12'd2503 : mem_out_dec = 6'b111111;
12'd2504 : mem_out_dec = 6'b111111;
12'd2505 : mem_out_dec = 6'b111111;
12'd2506 : mem_out_dec = 6'b111111;
12'd2507 : mem_out_dec = 6'b111111;
12'd2508 : mem_out_dec = 6'b111111;
12'd2509 : mem_out_dec = 6'b111111;
12'd2510 : mem_out_dec = 6'b111111;
12'd2511 : mem_out_dec = 6'b111111;
12'd2512 : mem_out_dec = 6'b111111;
12'd2513 : mem_out_dec = 6'b111111;
12'd2514 : mem_out_dec = 6'b111111;
12'd2515 : mem_out_dec = 6'b111111;
12'd2516 : mem_out_dec = 6'b111111;
12'd2517 : mem_out_dec = 6'b111111;
12'd2518 : mem_out_dec = 6'b111111;
12'd2519 : mem_out_dec = 6'b111111;
12'd2520 : mem_out_dec = 6'b111111;
12'd2521 : mem_out_dec = 6'b111111;
12'd2522 : mem_out_dec = 6'b111111;
12'd2523 : mem_out_dec = 6'b111111;
12'd2524 : mem_out_dec = 6'b111111;
12'd2525 : mem_out_dec = 6'b111111;
12'd2526 : mem_out_dec = 6'b111111;
12'd2527 : mem_out_dec = 6'b111111;
12'd2528 : mem_out_dec = 6'b111111;
12'd2529 : mem_out_dec = 6'b111111;
12'd2530 : mem_out_dec = 6'b111111;
12'd2531 : mem_out_dec = 6'b111111;
12'd2532 : mem_out_dec = 6'b111111;
12'd2533 : mem_out_dec = 6'b111111;
12'd2534 : mem_out_dec = 6'b111111;
12'd2535 : mem_out_dec = 6'b111111;
12'd2536 : mem_out_dec = 6'b111111;
12'd2537 : mem_out_dec = 6'b111111;
12'd2538 : mem_out_dec = 6'b111111;
12'd2539 : mem_out_dec = 6'b111111;
12'd2540 : mem_out_dec = 6'b111111;
12'd2541 : mem_out_dec = 6'b000101;
12'd2542 : mem_out_dec = 6'b000110;
12'd2543 : mem_out_dec = 6'b000110;
12'd2544 : mem_out_dec = 6'b000110;
12'd2545 : mem_out_dec = 6'b000110;
12'd2546 : mem_out_dec = 6'b000101;
12'd2547 : mem_out_dec = 6'b000101;
12'd2548 : mem_out_dec = 6'b000110;
12'd2549 : mem_out_dec = 6'b000111;
12'd2550 : mem_out_dec = 6'b000111;
12'd2551 : mem_out_dec = 6'b001000;
12'd2552 : mem_out_dec = 6'b001000;
12'd2553 : mem_out_dec = 6'b001001;
12'd2554 : mem_out_dec = 6'b001010;
12'd2555 : mem_out_dec = 6'b001010;
12'd2556 : mem_out_dec = 6'b001011;
12'd2557 : mem_out_dec = 6'b001100;
12'd2558 : mem_out_dec = 6'b001101;
12'd2559 : mem_out_dec = 6'b001101;
12'd2560 : mem_out_dec = 6'b111111;
12'd2561 : mem_out_dec = 6'b111111;
12'd2562 : mem_out_dec = 6'b111111;
12'd2563 : mem_out_dec = 6'b111111;
12'd2564 : mem_out_dec = 6'b111111;
12'd2565 : mem_out_dec = 6'b111111;
12'd2566 : mem_out_dec = 6'b111111;
12'd2567 : mem_out_dec = 6'b111111;
12'd2568 : mem_out_dec = 6'b111111;
12'd2569 : mem_out_dec = 6'b111111;
12'd2570 : mem_out_dec = 6'b111111;
12'd2571 : mem_out_dec = 6'b111111;
12'd2572 : mem_out_dec = 6'b111111;
12'd2573 : mem_out_dec = 6'b111111;
12'd2574 : mem_out_dec = 6'b111111;
12'd2575 : mem_out_dec = 6'b111111;
12'd2576 : mem_out_dec = 6'b111111;
12'd2577 : mem_out_dec = 6'b111111;
12'd2578 : mem_out_dec = 6'b111111;
12'd2579 : mem_out_dec = 6'b111111;
12'd2580 : mem_out_dec = 6'b111111;
12'd2581 : mem_out_dec = 6'b111111;
12'd2582 : mem_out_dec = 6'b111111;
12'd2583 : mem_out_dec = 6'b111111;
12'd2584 : mem_out_dec = 6'b111111;
12'd2585 : mem_out_dec = 6'b111111;
12'd2586 : mem_out_dec = 6'b111111;
12'd2587 : mem_out_dec = 6'b111111;
12'd2588 : mem_out_dec = 6'b111111;
12'd2589 : mem_out_dec = 6'b111111;
12'd2590 : mem_out_dec = 6'b111111;
12'd2591 : mem_out_dec = 6'b111111;
12'd2592 : mem_out_dec = 6'b111111;
12'd2593 : mem_out_dec = 6'b111111;
12'd2594 : mem_out_dec = 6'b111111;
12'd2595 : mem_out_dec = 6'b111111;
12'd2596 : mem_out_dec = 6'b111111;
12'd2597 : mem_out_dec = 6'b111111;
12'd2598 : mem_out_dec = 6'b111111;
12'd2599 : mem_out_dec = 6'b111111;
12'd2600 : mem_out_dec = 6'b111111;
12'd2601 : mem_out_dec = 6'b111111;
12'd2602 : mem_out_dec = 6'b111111;
12'd2603 : mem_out_dec = 6'b111111;
12'd2604 : mem_out_dec = 6'b111111;
12'd2605 : mem_out_dec = 6'b111111;
12'd2606 : mem_out_dec = 6'b000100;
12'd2607 : mem_out_dec = 6'b000101;
12'd2608 : mem_out_dec = 6'b000100;
12'd2609 : mem_out_dec = 6'b000100;
12'd2610 : mem_out_dec = 6'b000100;
12'd2611 : mem_out_dec = 6'b000101;
12'd2612 : mem_out_dec = 6'b000101;
12'd2613 : mem_out_dec = 6'b000110;
12'd2614 : mem_out_dec = 6'b000111;
12'd2615 : mem_out_dec = 6'b000111;
12'd2616 : mem_out_dec = 6'b000111;
12'd2617 : mem_out_dec = 6'b001000;
12'd2618 : mem_out_dec = 6'b001001;
12'd2619 : mem_out_dec = 6'b001010;
12'd2620 : mem_out_dec = 6'b001010;
12'd2621 : mem_out_dec = 6'b001011;
12'd2622 : mem_out_dec = 6'b001100;
12'd2623 : mem_out_dec = 6'b001101;
12'd2624 : mem_out_dec = 6'b111111;
12'd2625 : mem_out_dec = 6'b111111;
12'd2626 : mem_out_dec = 6'b111111;
12'd2627 : mem_out_dec = 6'b111111;
12'd2628 : mem_out_dec = 6'b111111;
12'd2629 : mem_out_dec = 6'b111111;
12'd2630 : mem_out_dec = 6'b111111;
12'd2631 : mem_out_dec = 6'b111111;
12'd2632 : mem_out_dec = 6'b111111;
12'd2633 : mem_out_dec = 6'b111111;
12'd2634 : mem_out_dec = 6'b111111;
12'd2635 : mem_out_dec = 6'b111111;
12'd2636 : mem_out_dec = 6'b111111;
12'd2637 : mem_out_dec = 6'b111111;
12'd2638 : mem_out_dec = 6'b111111;
12'd2639 : mem_out_dec = 6'b111111;
12'd2640 : mem_out_dec = 6'b111111;
12'd2641 : mem_out_dec = 6'b111111;
12'd2642 : mem_out_dec = 6'b111111;
12'd2643 : mem_out_dec = 6'b111111;
12'd2644 : mem_out_dec = 6'b111111;
12'd2645 : mem_out_dec = 6'b111111;
12'd2646 : mem_out_dec = 6'b111111;
12'd2647 : mem_out_dec = 6'b111111;
12'd2648 : mem_out_dec = 6'b111111;
12'd2649 : mem_out_dec = 6'b111111;
12'd2650 : mem_out_dec = 6'b111111;
12'd2651 : mem_out_dec = 6'b111111;
12'd2652 : mem_out_dec = 6'b111111;
12'd2653 : mem_out_dec = 6'b111111;
12'd2654 : mem_out_dec = 6'b111111;
12'd2655 : mem_out_dec = 6'b111111;
12'd2656 : mem_out_dec = 6'b111111;
12'd2657 : mem_out_dec = 6'b111111;
12'd2658 : mem_out_dec = 6'b111111;
12'd2659 : mem_out_dec = 6'b111111;
12'd2660 : mem_out_dec = 6'b111111;
12'd2661 : mem_out_dec = 6'b111111;
12'd2662 : mem_out_dec = 6'b111111;
12'd2663 : mem_out_dec = 6'b111111;
12'd2664 : mem_out_dec = 6'b111111;
12'd2665 : mem_out_dec = 6'b111111;
12'd2666 : mem_out_dec = 6'b111111;
12'd2667 : mem_out_dec = 6'b111111;
12'd2668 : mem_out_dec = 6'b111111;
12'd2669 : mem_out_dec = 6'b111111;
12'd2670 : mem_out_dec = 6'b111111;
12'd2671 : mem_out_dec = 6'b000100;
12'd2672 : mem_out_dec = 6'b000011;
12'd2673 : mem_out_dec = 6'b000011;
12'd2674 : mem_out_dec = 6'b000100;
12'd2675 : mem_out_dec = 6'b000100;
12'd2676 : mem_out_dec = 6'b000101;
12'd2677 : mem_out_dec = 6'b000110;
12'd2678 : mem_out_dec = 6'b000110;
12'd2679 : mem_out_dec = 6'b000111;
12'd2680 : mem_out_dec = 6'b000111;
12'd2681 : mem_out_dec = 6'b001000;
12'd2682 : mem_out_dec = 6'b001001;
12'd2683 : mem_out_dec = 6'b001001;
12'd2684 : mem_out_dec = 6'b001010;
12'd2685 : mem_out_dec = 6'b001011;
12'd2686 : mem_out_dec = 6'b001100;
12'd2687 : mem_out_dec = 6'b001100;
12'd2688 : mem_out_dec = 6'b111111;
12'd2689 : mem_out_dec = 6'b111111;
12'd2690 : mem_out_dec = 6'b111111;
12'd2691 : mem_out_dec = 6'b111111;
12'd2692 : mem_out_dec = 6'b111111;
12'd2693 : mem_out_dec = 6'b111111;
12'd2694 : mem_out_dec = 6'b111111;
12'd2695 : mem_out_dec = 6'b111111;
12'd2696 : mem_out_dec = 6'b111111;
12'd2697 : mem_out_dec = 6'b111111;
12'd2698 : mem_out_dec = 6'b111111;
12'd2699 : mem_out_dec = 6'b111111;
12'd2700 : mem_out_dec = 6'b111111;
12'd2701 : mem_out_dec = 6'b111111;
12'd2702 : mem_out_dec = 6'b111111;
12'd2703 : mem_out_dec = 6'b111111;
12'd2704 : mem_out_dec = 6'b111111;
12'd2705 : mem_out_dec = 6'b111111;
12'd2706 : mem_out_dec = 6'b111111;
12'd2707 : mem_out_dec = 6'b111111;
12'd2708 : mem_out_dec = 6'b111111;
12'd2709 : mem_out_dec = 6'b111111;
12'd2710 : mem_out_dec = 6'b111111;
12'd2711 : mem_out_dec = 6'b111111;
12'd2712 : mem_out_dec = 6'b111111;
12'd2713 : mem_out_dec = 6'b111111;
12'd2714 : mem_out_dec = 6'b111111;
12'd2715 : mem_out_dec = 6'b111111;
12'd2716 : mem_out_dec = 6'b111111;
12'd2717 : mem_out_dec = 6'b111111;
12'd2718 : mem_out_dec = 6'b111111;
12'd2719 : mem_out_dec = 6'b111111;
12'd2720 : mem_out_dec = 6'b111111;
12'd2721 : mem_out_dec = 6'b111111;
12'd2722 : mem_out_dec = 6'b111111;
12'd2723 : mem_out_dec = 6'b111111;
12'd2724 : mem_out_dec = 6'b111111;
12'd2725 : mem_out_dec = 6'b111111;
12'd2726 : mem_out_dec = 6'b111111;
12'd2727 : mem_out_dec = 6'b111111;
12'd2728 : mem_out_dec = 6'b111111;
12'd2729 : mem_out_dec = 6'b111111;
12'd2730 : mem_out_dec = 6'b111111;
12'd2731 : mem_out_dec = 6'b111111;
12'd2732 : mem_out_dec = 6'b111111;
12'd2733 : mem_out_dec = 6'b111111;
12'd2734 : mem_out_dec = 6'b111111;
12'd2735 : mem_out_dec = 6'b111111;
12'd2736 : mem_out_dec = 6'b000011;
12'd2737 : mem_out_dec = 6'b000011;
12'd2738 : mem_out_dec = 6'b000100;
12'd2739 : mem_out_dec = 6'b000100;
12'd2740 : mem_out_dec = 6'b000101;
12'd2741 : mem_out_dec = 6'b000101;
12'd2742 : mem_out_dec = 6'b000110;
12'd2743 : mem_out_dec = 6'b000111;
12'd2744 : mem_out_dec = 6'b000111;
12'd2745 : mem_out_dec = 6'b001000;
12'd2746 : mem_out_dec = 6'b001000;
12'd2747 : mem_out_dec = 6'b001001;
12'd2748 : mem_out_dec = 6'b001010;
12'd2749 : mem_out_dec = 6'b001011;
12'd2750 : mem_out_dec = 6'b001011;
12'd2751 : mem_out_dec = 6'b001100;
12'd2752 : mem_out_dec = 6'b111111;
12'd2753 : mem_out_dec = 6'b111111;
12'd2754 : mem_out_dec = 6'b111111;
12'd2755 : mem_out_dec = 6'b111111;
12'd2756 : mem_out_dec = 6'b111111;
12'd2757 : mem_out_dec = 6'b111111;
12'd2758 : mem_out_dec = 6'b111111;
12'd2759 : mem_out_dec = 6'b111111;
12'd2760 : mem_out_dec = 6'b111111;
12'd2761 : mem_out_dec = 6'b111111;
12'd2762 : mem_out_dec = 6'b111111;
12'd2763 : mem_out_dec = 6'b111111;
12'd2764 : mem_out_dec = 6'b111111;
12'd2765 : mem_out_dec = 6'b111111;
12'd2766 : mem_out_dec = 6'b111111;
12'd2767 : mem_out_dec = 6'b111111;
12'd2768 : mem_out_dec = 6'b111111;
12'd2769 : mem_out_dec = 6'b111111;
12'd2770 : mem_out_dec = 6'b111111;
12'd2771 : mem_out_dec = 6'b111111;
12'd2772 : mem_out_dec = 6'b111111;
12'd2773 : mem_out_dec = 6'b111111;
12'd2774 : mem_out_dec = 6'b111111;
12'd2775 : mem_out_dec = 6'b111111;
12'd2776 : mem_out_dec = 6'b111111;
12'd2777 : mem_out_dec = 6'b111111;
12'd2778 : mem_out_dec = 6'b111111;
12'd2779 : mem_out_dec = 6'b111111;
12'd2780 : mem_out_dec = 6'b111111;
12'd2781 : mem_out_dec = 6'b111111;
12'd2782 : mem_out_dec = 6'b111111;
12'd2783 : mem_out_dec = 6'b111111;
12'd2784 : mem_out_dec = 6'b111111;
12'd2785 : mem_out_dec = 6'b111111;
12'd2786 : mem_out_dec = 6'b111111;
12'd2787 : mem_out_dec = 6'b111111;
12'd2788 : mem_out_dec = 6'b111111;
12'd2789 : mem_out_dec = 6'b111111;
12'd2790 : mem_out_dec = 6'b111111;
12'd2791 : mem_out_dec = 6'b111111;
12'd2792 : mem_out_dec = 6'b111111;
12'd2793 : mem_out_dec = 6'b111111;
12'd2794 : mem_out_dec = 6'b111111;
12'd2795 : mem_out_dec = 6'b111111;
12'd2796 : mem_out_dec = 6'b111111;
12'd2797 : mem_out_dec = 6'b111111;
12'd2798 : mem_out_dec = 6'b111111;
12'd2799 : mem_out_dec = 6'b111111;
12'd2800 : mem_out_dec = 6'b111111;
12'd2801 : mem_out_dec = 6'b000011;
12'd2802 : mem_out_dec = 6'b000011;
12'd2803 : mem_out_dec = 6'b000100;
12'd2804 : mem_out_dec = 6'b000101;
12'd2805 : mem_out_dec = 6'b000101;
12'd2806 : mem_out_dec = 6'b000110;
12'd2807 : mem_out_dec = 6'b000111;
12'd2808 : mem_out_dec = 6'b000111;
12'd2809 : mem_out_dec = 6'b000111;
12'd2810 : mem_out_dec = 6'b001000;
12'd2811 : mem_out_dec = 6'b001001;
12'd2812 : mem_out_dec = 6'b001010;
12'd2813 : mem_out_dec = 6'b001010;
12'd2814 : mem_out_dec = 6'b001011;
12'd2815 : mem_out_dec = 6'b001100;
12'd2816 : mem_out_dec = 6'b111111;
12'd2817 : mem_out_dec = 6'b111111;
12'd2818 : mem_out_dec = 6'b111111;
12'd2819 : mem_out_dec = 6'b111111;
12'd2820 : mem_out_dec = 6'b111111;
12'd2821 : mem_out_dec = 6'b111111;
12'd2822 : mem_out_dec = 6'b111111;
12'd2823 : mem_out_dec = 6'b111111;
12'd2824 : mem_out_dec = 6'b111111;
12'd2825 : mem_out_dec = 6'b111111;
12'd2826 : mem_out_dec = 6'b111111;
12'd2827 : mem_out_dec = 6'b111111;
12'd2828 : mem_out_dec = 6'b111111;
12'd2829 : mem_out_dec = 6'b111111;
12'd2830 : mem_out_dec = 6'b111111;
12'd2831 : mem_out_dec = 6'b111111;
12'd2832 : mem_out_dec = 6'b111111;
12'd2833 : mem_out_dec = 6'b111111;
12'd2834 : mem_out_dec = 6'b111111;
12'd2835 : mem_out_dec = 6'b111111;
12'd2836 : mem_out_dec = 6'b111111;
12'd2837 : mem_out_dec = 6'b111111;
12'd2838 : mem_out_dec = 6'b111111;
12'd2839 : mem_out_dec = 6'b111111;
12'd2840 : mem_out_dec = 6'b111111;
12'd2841 : mem_out_dec = 6'b111111;
12'd2842 : mem_out_dec = 6'b111111;
12'd2843 : mem_out_dec = 6'b111111;
12'd2844 : mem_out_dec = 6'b111111;
12'd2845 : mem_out_dec = 6'b111111;
12'd2846 : mem_out_dec = 6'b111111;
12'd2847 : mem_out_dec = 6'b111111;
12'd2848 : mem_out_dec = 6'b111111;
12'd2849 : mem_out_dec = 6'b111111;
12'd2850 : mem_out_dec = 6'b111111;
12'd2851 : mem_out_dec = 6'b111111;
12'd2852 : mem_out_dec = 6'b111111;
12'd2853 : mem_out_dec = 6'b111111;
12'd2854 : mem_out_dec = 6'b111111;
12'd2855 : mem_out_dec = 6'b111111;
12'd2856 : mem_out_dec = 6'b111111;
12'd2857 : mem_out_dec = 6'b111111;
12'd2858 : mem_out_dec = 6'b111111;
12'd2859 : mem_out_dec = 6'b111111;
12'd2860 : mem_out_dec = 6'b111111;
12'd2861 : mem_out_dec = 6'b111111;
12'd2862 : mem_out_dec = 6'b111111;
12'd2863 : mem_out_dec = 6'b111111;
12'd2864 : mem_out_dec = 6'b111111;
12'd2865 : mem_out_dec = 6'b111111;
12'd2866 : mem_out_dec = 6'b000011;
12'd2867 : mem_out_dec = 6'b000100;
12'd2868 : mem_out_dec = 6'b000100;
12'd2869 : mem_out_dec = 6'b000101;
12'd2870 : mem_out_dec = 6'b000110;
12'd2871 : mem_out_dec = 6'b000110;
12'd2872 : mem_out_dec = 6'b000110;
12'd2873 : mem_out_dec = 6'b000111;
12'd2874 : mem_out_dec = 6'b001000;
12'd2875 : mem_out_dec = 6'b001001;
12'd2876 : mem_out_dec = 6'b001001;
12'd2877 : mem_out_dec = 6'b001010;
12'd2878 : mem_out_dec = 6'b001011;
12'd2879 : mem_out_dec = 6'b001100;
12'd2880 : mem_out_dec = 6'b111111;
12'd2881 : mem_out_dec = 6'b111111;
12'd2882 : mem_out_dec = 6'b111111;
12'd2883 : mem_out_dec = 6'b111111;
12'd2884 : mem_out_dec = 6'b111111;
12'd2885 : mem_out_dec = 6'b111111;
12'd2886 : mem_out_dec = 6'b111111;
12'd2887 : mem_out_dec = 6'b111111;
12'd2888 : mem_out_dec = 6'b111111;
12'd2889 : mem_out_dec = 6'b111111;
12'd2890 : mem_out_dec = 6'b111111;
12'd2891 : mem_out_dec = 6'b111111;
12'd2892 : mem_out_dec = 6'b111111;
12'd2893 : mem_out_dec = 6'b111111;
12'd2894 : mem_out_dec = 6'b111111;
12'd2895 : mem_out_dec = 6'b111111;
12'd2896 : mem_out_dec = 6'b111111;
12'd2897 : mem_out_dec = 6'b111111;
12'd2898 : mem_out_dec = 6'b111111;
12'd2899 : mem_out_dec = 6'b111111;
12'd2900 : mem_out_dec = 6'b111111;
12'd2901 : mem_out_dec = 6'b111111;
12'd2902 : mem_out_dec = 6'b111111;
12'd2903 : mem_out_dec = 6'b111111;
12'd2904 : mem_out_dec = 6'b111111;
12'd2905 : mem_out_dec = 6'b111111;
12'd2906 : mem_out_dec = 6'b111111;
12'd2907 : mem_out_dec = 6'b111111;
12'd2908 : mem_out_dec = 6'b111111;
12'd2909 : mem_out_dec = 6'b111111;
12'd2910 : mem_out_dec = 6'b111111;
12'd2911 : mem_out_dec = 6'b111111;
12'd2912 : mem_out_dec = 6'b111111;
12'd2913 : mem_out_dec = 6'b111111;
12'd2914 : mem_out_dec = 6'b111111;
12'd2915 : mem_out_dec = 6'b111111;
12'd2916 : mem_out_dec = 6'b111111;
12'd2917 : mem_out_dec = 6'b111111;
12'd2918 : mem_out_dec = 6'b111111;
12'd2919 : mem_out_dec = 6'b111111;
12'd2920 : mem_out_dec = 6'b111111;
12'd2921 : mem_out_dec = 6'b111111;
12'd2922 : mem_out_dec = 6'b111111;
12'd2923 : mem_out_dec = 6'b111111;
12'd2924 : mem_out_dec = 6'b111111;
12'd2925 : mem_out_dec = 6'b111111;
12'd2926 : mem_out_dec = 6'b111111;
12'd2927 : mem_out_dec = 6'b111111;
12'd2928 : mem_out_dec = 6'b111111;
12'd2929 : mem_out_dec = 6'b111111;
12'd2930 : mem_out_dec = 6'b111111;
12'd2931 : mem_out_dec = 6'b000100;
12'd2932 : mem_out_dec = 6'b000100;
12'd2933 : mem_out_dec = 6'b000101;
12'd2934 : mem_out_dec = 6'b000101;
12'd2935 : mem_out_dec = 6'b000110;
12'd2936 : mem_out_dec = 6'b000110;
12'd2937 : mem_out_dec = 6'b000111;
12'd2938 : mem_out_dec = 6'b001000;
12'd2939 : mem_out_dec = 6'b001000;
12'd2940 : mem_out_dec = 6'b001001;
12'd2941 : mem_out_dec = 6'b001010;
12'd2942 : mem_out_dec = 6'b001011;
12'd2943 : mem_out_dec = 6'b001011;
12'd2944 : mem_out_dec = 6'b111111;
12'd2945 : mem_out_dec = 6'b111111;
12'd2946 : mem_out_dec = 6'b111111;
12'd2947 : mem_out_dec = 6'b111111;
12'd2948 : mem_out_dec = 6'b111111;
12'd2949 : mem_out_dec = 6'b111111;
12'd2950 : mem_out_dec = 6'b111111;
12'd2951 : mem_out_dec = 6'b111111;
12'd2952 : mem_out_dec = 6'b111111;
12'd2953 : mem_out_dec = 6'b111111;
12'd2954 : mem_out_dec = 6'b111111;
12'd2955 : mem_out_dec = 6'b111111;
12'd2956 : mem_out_dec = 6'b111111;
12'd2957 : mem_out_dec = 6'b111111;
12'd2958 : mem_out_dec = 6'b111111;
12'd2959 : mem_out_dec = 6'b111111;
12'd2960 : mem_out_dec = 6'b111111;
12'd2961 : mem_out_dec = 6'b111111;
12'd2962 : mem_out_dec = 6'b111111;
12'd2963 : mem_out_dec = 6'b111111;
12'd2964 : mem_out_dec = 6'b111111;
12'd2965 : mem_out_dec = 6'b111111;
12'd2966 : mem_out_dec = 6'b111111;
12'd2967 : mem_out_dec = 6'b111111;
12'd2968 : mem_out_dec = 6'b111111;
12'd2969 : mem_out_dec = 6'b111111;
12'd2970 : mem_out_dec = 6'b111111;
12'd2971 : mem_out_dec = 6'b111111;
12'd2972 : mem_out_dec = 6'b111111;
12'd2973 : mem_out_dec = 6'b111111;
12'd2974 : mem_out_dec = 6'b111111;
12'd2975 : mem_out_dec = 6'b111111;
12'd2976 : mem_out_dec = 6'b111111;
12'd2977 : mem_out_dec = 6'b111111;
12'd2978 : mem_out_dec = 6'b111111;
12'd2979 : mem_out_dec = 6'b111111;
12'd2980 : mem_out_dec = 6'b111111;
12'd2981 : mem_out_dec = 6'b111111;
12'd2982 : mem_out_dec = 6'b111111;
12'd2983 : mem_out_dec = 6'b111111;
12'd2984 : mem_out_dec = 6'b111111;
12'd2985 : mem_out_dec = 6'b111111;
12'd2986 : mem_out_dec = 6'b111111;
12'd2987 : mem_out_dec = 6'b111111;
12'd2988 : mem_out_dec = 6'b111111;
12'd2989 : mem_out_dec = 6'b111111;
12'd2990 : mem_out_dec = 6'b111111;
12'd2991 : mem_out_dec = 6'b111111;
12'd2992 : mem_out_dec = 6'b111111;
12'd2993 : mem_out_dec = 6'b111111;
12'd2994 : mem_out_dec = 6'b111111;
12'd2995 : mem_out_dec = 6'b111111;
12'd2996 : mem_out_dec = 6'b000100;
12'd2997 : mem_out_dec = 6'b000101;
12'd2998 : mem_out_dec = 6'b000101;
12'd2999 : mem_out_dec = 6'b000110;
12'd3000 : mem_out_dec = 6'b000110;
12'd3001 : mem_out_dec = 6'b000111;
12'd3002 : mem_out_dec = 6'b000111;
12'd3003 : mem_out_dec = 6'b001000;
12'd3004 : mem_out_dec = 6'b001001;
12'd3005 : mem_out_dec = 6'b001010;
12'd3006 : mem_out_dec = 6'b001010;
12'd3007 : mem_out_dec = 6'b001011;
12'd3008 : mem_out_dec = 6'b111111;
12'd3009 : mem_out_dec = 6'b111111;
12'd3010 : mem_out_dec = 6'b111111;
12'd3011 : mem_out_dec = 6'b111111;
12'd3012 : mem_out_dec = 6'b111111;
12'd3013 : mem_out_dec = 6'b111111;
12'd3014 : mem_out_dec = 6'b111111;
12'd3015 : mem_out_dec = 6'b111111;
12'd3016 : mem_out_dec = 6'b111111;
12'd3017 : mem_out_dec = 6'b111111;
12'd3018 : mem_out_dec = 6'b111111;
12'd3019 : mem_out_dec = 6'b111111;
12'd3020 : mem_out_dec = 6'b111111;
12'd3021 : mem_out_dec = 6'b111111;
12'd3022 : mem_out_dec = 6'b111111;
12'd3023 : mem_out_dec = 6'b111111;
12'd3024 : mem_out_dec = 6'b111111;
12'd3025 : mem_out_dec = 6'b111111;
12'd3026 : mem_out_dec = 6'b111111;
12'd3027 : mem_out_dec = 6'b111111;
12'd3028 : mem_out_dec = 6'b111111;
12'd3029 : mem_out_dec = 6'b111111;
12'd3030 : mem_out_dec = 6'b111111;
12'd3031 : mem_out_dec = 6'b111111;
12'd3032 : mem_out_dec = 6'b111111;
12'd3033 : mem_out_dec = 6'b111111;
12'd3034 : mem_out_dec = 6'b111111;
12'd3035 : mem_out_dec = 6'b111111;
12'd3036 : mem_out_dec = 6'b111111;
12'd3037 : mem_out_dec = 6'b111111;
12'd3038 : mem_out_dec = 6'b111111;
12'd3039 : mem_out_dec = 6'b111111;
12'd3040 : mem_out_dec = 6'b111111;
12'd3041 : mem_out_dec = 6'b111111;
12'd3042 : mem_out_dec = 6'b111111;
12'd3043 : mem_out_dec = 6'b111111;
12'd3044 : mem_out_dec = 6'b111111;
12'd3045 : mem_out_dec = 6'b111111;
12'd3046 : mem_out_dec = 6'b111111;
12'd3047 : mem_out_dec = 6'b111111;
12'd3048 : mem_out_dec = 6'b111111;
12'd3049 : mem_out_dec = 6'b111111;
12'd3050 : mem_out_dec = 6'b111111;
12'd3051 : mem_out_dec = 6'b111111;
12'd3052 : mem_out_dec = 6'b111111;
12'd3053 : mem_out_dec = 6'b111111;
12'd3054 : mem_out_dec = 6'b111111;
12'd3055 : mem_out_dec = 6'b111111;
12'd3056 : mem_out_dec = 6'b111111;
12'd3057 : mem_out_dec = 6'b111111;
12'd3058 : mem_out_dec = 6'b111111;
12'd3059 : mem_out_dec = 6'b111111;
12'd3060 : mem_out_dec = 6'b111111;
12'd3061 : mem_out_dec = 6'b000100;
12'd3062 : mem_out_dec = 6'b000101;
12'd3063 : mem_out_dec = 6'b000110;
12'd3064 : mem_out_dec = 6'b000110;
12'd3065 : mem_out_dec = 6'b000111;
12'd3066 : mem_out_dec = 6'b000111;
12'd3067 : mem_out_dec = 6'b001000;
12'd3068 : mem_out_dec = 6'b001001;
12'd3069 : mem_out_dec = 6'b001001;
12'd3070 : mem_out_dec = 6'b001010;
12'd3071 : mem_out_dec = 6'b001011;
12'd3072 : mem_out_dec = 6'b111111;
12'd3073 : mem_out_dec = 6'b111111;
12'd3074 : mem_out_dec = 6'b111111;
12'd3075 : mem_out_dec = 6'b111111;
12'd3076 : mem_out_dec = 6'b111111;
12'd3077 : mem_out_dec = 6'b111111;
12'd3078 : mem_out_dec = 6'b111111;
12'd3079 : mem_out_dec = 6'b111111;
12'd3080 : mem_out_dec = 6'b111111;
12'd3081 : mem_out_dec = 6'b111111;
12'd3082 : mem_out_dec = 6'b111111;
12'd3083 : mem_out_dec = 6'b111111;
12'd3084 : mem_out_dec = 6'b111111;
12'd3085 : mem_out_dec = 6'b111111;
12'd3086 : mem_out_dec = 6'b111111;
12'd3087 : mem_out_dec = 6'b111111;
12'd3088 : mem_out_dec = 6'b111111;
12'd3089 : mem_out_dec = 6'b111111;
12'd3090 : mem_out_dec = 6'b111111;
12'd3091 : mem_out_dec = 6'b111111;
12'd3092 : mem_out_dec = 6'b111111;
12'd3093 : mem_out_dec = 6'b111111;
12'd3094 : mem_out_dec = 6'b111111;
12'd3095 : mem_out_dec = 6'b111111;
12'd3096 : mem_out_dec = 6'b111111;
12'd3097 : mem_out_dec = 6'b111111;
12'd3098 : mem_out_dec = 6'b111111;
12'd3099 : mem_out_dec = 6'b111111;
12'd3100 : mem_out_dec = 6'b111111;
12'd3101 : mem_out_dec = 6'b111111;
12'd3102 : mem_out_dec = 6'b111111;
12'd3103 : mem_out_dec = 6'b111111;
12'd3104 : mem_out_dec = 6'b111111;
12'd3105 : mem_out_dec = 6'b111111;
12'd3106 : mem_out_dec = 6'b111111;
12'd3107 : mem_out_dec = 6'b111111;
12'd3108 : mem_out_dec = 6'b111111;
12'd3109 : mem_out_dec = 6'b111111;
12'd3110 : mem_out_dec = 6'b111111;
12'd3111 : mem_out_dec = 6'b111111;
12'd3112 : mem_out_dec = 6'b111111;
12'd3113 : mem_out_dec = 6'b111111;
12'd3114 : mem_out_dec = 6'b111111;
12'd3115 : mem_out_dec = 6'b111111;
12'd3116 : mem_out_dec = 6'b111111;
12'd3117 : mem_out_dec = 6'b111111;
12'd3118 : mem_out_dec = 6'b111111;
12'd3119 : mem_out_dec = 6'b111111;
12'd3120 : mem_out_dec = 6'b111111;
12'd3121 : mem_out_dec = 6'b111111;
12'd3122 : mem_out_dec = 6'b111111;
12'd3123 : mem_out_dec = 6'b111111;
12'd3124 : mem_out_dec = 6'b111111;
12'd3125 : mem_out_dec = 6'b111111;
12'd3126 : mem_out_dec = 6'b000100;
12'd3127 : mem_out_dec = 6'b000101;
12'd3128 : mem_out_dec = 6'b000101;
12'd3129 : mem_out_dec = 6'b000110;
12'd3130 : mem_out_dec = 6'b000110;
12'd3131 : mem_out_dec = 6'b000111;
12'd3132 : mem_out_dec = 6'b001000;
12'd3133 : mem_out_dec = 6'b001000;
12'd3134 : mem_out_dec = 6'b001001;
12'd3135 : mem_out_dec = 6'b001010;
12'd3136 : mem_out_dec = 6'b111111;
12'd3137 : mem_out_dec = 6'b111111;
12'd3138 : mem_out_dec = 6'b111111;
12'd3139 : mem_out_dec = 6'b111111;
12'd3140 : mem_out_dec = 6'b111111;
12'd3141 : mem_out_dec = 6'b111111;
12'd3142 : mem_out_dec = 6'b111111;
12'd3143 : mem_out_dec = 6'b111111;
12'd3144 : mem_out_dec = 6'b111111;
12'd3145 : mem_out_dec = 6'b111111;
12'd3146 : mem_out_dec = 6'b111111;
12'd3147 : mem_out_dec = 6'b111111;
12'd3148 : mem_out_dec = 6'b111111;
12'd3149 : mem_out_dec = 6'b111111;
12'd3150 : mem_out_dec = 6'b111111;
12'd3151 : mem_out_dec = 6'b111111;
12'd3152 : mem_out_dec = 6'b111111;
12'd3153 : mem_out_dec = 6'b111111;
12'd3154 : mem_out_dec = 6'b111111;
12'd3155 : mem_out_dec = 6'b111111;
12'd3156 : mem_out_dec = 6'b111111;
12'd3157 : mem_out_dec = 6'b111111;
12'd3158 : mem_out_dec = 6'b111111;
12'd3159 : mem_out_dec = 6'b111111;
12'd3160 : mem_out_dec = 6'b111111;
12'd3161 : mem_out_dec = 6'b111111;
12'd3162 : mem_out_dec = 6'b111111;
12'd3163 : mem_out_dec = 6'b111111;
12'd3164 : mem_out_dec = 6'b111111;
12'd3165 : mem_out_dec = 6'b111111;
12'd3166 : mem_out_dec = 6'b111111;
12'd3167 : mem_out_dec = 6'b111111;
12'd3168 : mem_out_dec = 6'b111111;
12'd3169 : mem_out_dec = 6'b111111;
12'd3170 : mem_out_dec = 6'b111111;
12'd3171 : mem_out_dec = 6'b111111;
12'd3172 : mem_out_dec = 6'b111111;
12'd3173 : mem_out_dec = 6'b111111;
12'd3174 : mem_out_dec = 6'b111111;
12'd3175 : mem_out_dec = 6'b111111;
12'd3176 : mem_out_dec = 6'b111111;
12'd3177 : mem_out_dec = 6'b111111;
12'd3178 : mem_out_dec = 6'b111111;
12'd3179 : mem_out_dec = 6'b111111;
12'd3180 : mem_out_dec = 6'b111111;
12'd3181 : mem_out_dec = 6'b111111;
12'd3182 : mem_out_dec = 6'b111111;
12'd3183 : mem_out_dec = 6'b111111;
12'd3184 : mem_out_dec = 6'b111111;
12'd3185 : mem_out_dec = 6'b111111;
12'd3186 : mem_out_dec = 6'b111111;
12'd3187 : mem_out_dec = 6'b111111;
12'd3188 : mem_out_dec = 6'b111111;
12'd3189 : mem_out_dec = 6'b111111;
12'd3190 : mem_out_dec = 6'b111111;
12'd3191 : mem_out_dec = 6'b000100;
12'd3192 : mem_out_dec = 6'b000100;
12'd3193 : mem_out_dec = 6'b000101;
12'd3194 : mem_out_dec = 6'b000110;
12'd3195 : mem_out_dec = 6'b000110;
12'd3196 : mem_out_dec = 6'b000111;
12'd3197 : mem_out_dec = 6'b001000;
12'd3198 : mem_out_dec = 6'b001000;
12'd3199 : mem_out_dec = 6'b001001;
12'd3200 : mem_out_dec = 6'b111111;
12'd3201 : mem_out_dec = 6'b111111;
12'd3202 : mem_out_dec = 6'b111111;
12'd3203 : mem_out_dec = 6'b111111;
12'd3204 : mem_out_dec = 6'b111111;
12'd3205 : mem_out_dec = 6'b111111;
12'd3206 : mem_out_dec = 6'b111111;
12'd3207 : mem_out_dec = 6'b111111;
12'd3208 : mem_out_dec = 6'b111111;
12'd3209 : mem_out_dec = 6'b111111;
12'd3210 : mem_out_dec = 6'b111111;
12'd3211 : mem_out_dec = 6'b111111;
12'd3212 : mem_out_dec = 6'b111111;
12'd3213 : mem_out_dec = 6'b111111;
12'd3214 : mem_out_dec = 6'b111111;
12'd3215 : mem_out_dec = 6'b111111;
12'd3216 : mem_out_dec = 6'b111111;
12'd3217 : mem_out_dec = 6'b111111;
12'd3218 : mem_out_dec = 6'b111111;
12'd3219 : mem_out_dec = 6'b111111;
12'd3220 : mem_out_dec = 6'b111111;
12'd3221 : mem_out_dec = 6'b111111;
12'd3222 : mem_out_dec = 6'b111111;
12'd3223 : mem_out_dec = 6'b111111;
12'd3224 : mem_out_dec = 6'b111111;
12'd3225 : mem_out_dec = 6'b111111;
12'd3226 : mem_out_dec = 6'b111111;
12'd3227 : mem_out_dec = 6'b111111;
12'd3228 : mem_out_dec = 6'b111111;
12'd3229 : mem_out_dec = 6'b111111;
12'd3230 : mem_out_dec = 6'b111111;
12'd3231 : mem_out_dec = 6'b111111;
12'd3232 : mem_out_dec = 6'b111111;
12'd3233 : mem_out_dec = 6'b111111;
12'd3234 : mem_out_dec = 6'b111111;
12'd3235 : mem_out_dec = 6'b111111;
12'd3236 : mem_out_dec = 6'b111111;
12'd3237 : mem_out_dec = 6'b111111;
12'd3238 : mem_out_dec = 6'b111111;
12'd3239 : mem_out_dec = 6'b111111;
12'd3240 : mem_out_dec = 6'b111111;
12'd3241 : mem_out_dec = 6'b111111;
12'd3242 : mem_out_dec = 6'b111111;
12'd3243 : mem_out_dec = 6'b111111;
12'd3244 : mem_out_dec = 6'b111111;
12'd3245 : mem_out_dec = 6'b111111;
12'd3246 : mem_out_dec = 6'b111111;
12'd3247 : mem_out_dec = 6'b111111;
12'd3248 : mem_out_dec = 6'b111111;
12'd3249 : mem_out_dec = 6'b111111;
12'd3250 : mem_out_dec = 6'b111111;
12'd3251 : mem_out_dec = 6'b111111;
12'd3252 : mem_out_dec = 6'b111111;
12'd3253 : mem_out_dec = 6'b111111;
12'd3254 : mem_out_dec = 6'b111111;
12'd3255 : mem_out_dec = 6'b111111;
12'd3256 : mem_out_dec = 6'b000100;
12'd3257 : mem_out_dec = 6'b000100;
12'd3258 : mem_out_dec = 6'b000101;
12'd3259 : mem_out_dec = 6'b000110;
12'd3260 : mem_out_dec = 6'b000110;
12'd3261 : mem_out_dec = 6'b000111;
12'd3262 : mem_out_dec = 6'b001000;
12'd3263 : mem_out_dec = 6'b001001;
12'd3264 : mem_out_dec = 6'b111111;
12'd3265 : mem_out_dec = 6'b111111;
12'd3266 : mem_out_dec = 6'b111111;
12'd3267 : mem_out_dec = 6'b111111;
12'd3268 : mem_out_dec = 6'b111111;
12'd3269 : mem_out_dec = 6'b111111;
12'd3270 : mem_out_dec = 6'b111111;
12'd3271 : mem_out_dec = 6'b111111;
12'd3272 : mem_out_dec = 6'b111111;
12'd3273 : mem_out_dec = 6'b111111;
12'd3274 : mem_out_dec = 6'b111111;
12'd3275 : mem_out_dec = 6'b111111;
12'd3276 : mem_out_dec = 6'b111111;
12'd3277 : mem_out_dec = 6'b111111;
12'd3278 : mem_out_dec = 6'b111111;
12'd3279 : mem_out_dec = 6'b111111;
12'd3280 : mem_out_dec = 6'b111111;
12'd3281 : mem_out_dec = 6'b111111;
12'd3282 : mem_out_dec = 6'b111111;
12'd3283 : mem_out_dec = 6'b111111;
12'd3284 : mem_out_dec = 6'b111111;
12'd3285 : mem_out_dec = 6'b111111;
12'd3286 : mem_out_dec = 6'b111111;
12'd3287 : mem_out_dec = 6'b111111;
12'd3288 : mem_out_dec = 6'b111111;
12'd3289 : mem_out_dec = 6'b111111;
12'd3290 : mem_out_dec = 6'b111111;
12'd3291 : mem_out_dec = 6'b111111;
12'd3292 : mem_out_dec = 6'b111111;
12'd3293 : mem_out_dec = 6'b111111;
12'd3294 : mem_out_dec = 6'b111111;
12'd3295 : mem_out_dec = 6'b111111;
12'd3296 : mem_out_dec = 6'b111111;
12'd3297 : mem_out_dec = 6'b111111;
12'd3298 : mem_out_dec = 6'b111111;
12'd3299 : mem_out_dec = 6'b111111;
12'd3300 : mem_out_dec = 6'b111111;
12'd3301 : mem_out_dec = 6'b111111;
12'd3302 : mem_out_dec = 6'b111111;
12'd3303 : mem_out_dec = 6'b111111;
12'd3304 : mem_out_dec = 6'b111111;
12'd3305 : mem_out_dec = 6'b111111;
12'd3306 : mem_out_dec = 6'b111111;
12'd3307 : mem_out_dec = 6'b111111;
12'd3308 : mem_out_dec = 6'b111111;
12'd3309 : mem_out_dec = 6'b111111;
12'd3310 : mem_out_dec = 6'b111111;
12'd3311 : mem_out_dec = 6'b111111;
12'd3312 : mem_out_dec = 6'b111111;
12'd3313 : mem_out_dec = 6'b111111;
12'd3314 : mem_out_dec = 6'b111111;
12'd3315 : mem_out_dec = 6'b111111;
12'd3316 : mem_out_dec = 6'b111111;
12'd3317 : mem_out_dec = 6'b111111;
12'd3318 : mem_out_dec = 6'b111111;
12'd3319 : mem_out_dec = 6'b111111;
12'd3320 : mem_out_dec = 6'b111111;
12'd3321 : mem_out_dec = 6'b000100;
12'd3322 : mem_out_dec = 6'b000100;
12'd3323 : mem_out_dec = 6'b000101;
12'd3324 : mem_out_dec = 6'b000110;
12'd3325 : mem_out_dec = 6'b000111;
12'd3326 : mem_out_dec = 6'b001000;
12'd3327 : mem_out_dec = 6'b001000;
12'd3328 : mem_out_dec = 6'b111111;
12'd3329 : mem_out_dec = 6'b111111;
12'd3330 : mem_out_dec = 6'b111111;
12'd3331 : mem_out_dec = 6'b111111;
12'd3332 : mem_out_dec = 6'b111111;
12'd3333 : mem_out_dec = 6'b111111;
12'd3334 : mem_out_dec = 6'b111111;
12'd3335 : mem_out_dec = 6'b111111;
12'd3336 : mem_out_dec = 6'b111111;
12'd3337 : mem_out_dec = 6'b111111;
12'd3338 : mem_out_dec = 6'b111111;
12'd3339 : mem_out_dec = 6'b111111;
12'd3340 : mem_out_dec = 6'b111111;
12'd3341 : mem_out_dec = 6'b111111;
12'd3342 : mem_out_dec = 6'b111111;
12'd3343 : mem_out_dec = 6'b111111;
12'd3344 : mem_out_dec = 6'b111111;
12'd3345 : mem_out_dec = 6'b111111;
12'd3346 : mem_out_dec = 6'b111111;
12'd3347 : mem_out_dec = 6'b111111;
12'd3348 : mem_out_dec = 6'b111111;
12'd3349 : mem_out_dec = 6'b111111;
12'd3350 : mem_out_dec = 6'b111111;
12'd3351 : mem_out_dec = 6'b111111;
12'd3352 : mem_out_dec = 6'b111111;
12'd3353 : mem_out_dec = 6'b111111;
12'd3354 : mem_out_dec = 6'b111111;
12'd3355 : mem_out_dec = 6'b111111;
12'd3356 : mem_out_dec = 6'b111111;
12'd3357 : mem_out_dec = 6'b111111;
12'd3358 : mem_out_dec = 6'b111111;
12'd3359 : mem_out_dec = 6'b111111;
12'd3360 : mem_out_dec = 6'b111111;
12'd3361 : mem_out_dec = 6'b111111;
12'd3362 : mem_out_dec = 6'b111111;
12'd3363 : mem_out_dec = 6'b111111;
12'd3364 : mem_out_dec = 6'b111111;
12'd3365 : mem_out_dec = 6'b111111;
12'd3366 : mem_out_dec = 6'b111111;
12'd3367 : mem_out_dec = 6'b111111;
12'd3368 : mem_out_dec = 6'b111111;
12'd3369 : mem_out_dec = 6'b111111;
12'd3370 : mem_out_dec = 6'b111111;
12'd3371 : mem_out_dec = 6'b111111;
12'd3372 : mem_out_dec = 6'b111111;
12'd3373 : mem_out_dec = 6'b111111;
12'd3374 : mem_out_dec = 6'b111111;
12'd3375 : mem_out_dec = 6'b111111;
12'd3376 : mem_out_dec = 6'b111111;
12'd3377 : mem_out_dec = 6'b111111;
12'd3378 : mem_out_dec = 6'b111111;
12'd3379 : mem_out_dec = 6'b111111;
12'd3380 : mem_out_dec = 6'b111111;
12'd3381 : mem_out_dec = 6'b111111;
12'd3382 : mem_out_dec = 6'b111111;
12'd3383 : mem_out_dec = 6'b111111;
12'd3384 : mem_out_dec = 6'b111111;
12'd3385 : mem_out_dec = 6'b111111;
12'd3386 : mem_out_dec = 6'b000100;
12'd3387 : mem_out_dec = 6'b000101;
12'd3388 : mem_out_dec = 6'b000110;
12'd3389 : mem_out_dec = 6'b000110;
12'd3390 : mem_out_dec = 6'b000111;
12'd3391 : mem_out_dec = 6'b001000;
12'd3392 : mem_out_dec = 6'b111111;
12'd3393 : mem_out_dec = 6'b111111;
12'd3394 : mem_out_dec = 6'b111111;
12'd3395 : mem_out_dec = 6'b111111;
12'd3396 : mem_out_dec = 6'b111111;
12'd3397 : mem_out_dec = 6'b111111;
12'd3398 : mem_out_dec = 6'b111111;
12'd3399 : mem_out_dec = 6'b111111;
12'd3400 : mem_out_dec = 6'b111111;
12'd3401 : mem_out_dec = 6'b111111;
12'd3402 : mem_out_dec = 6'b111111;
12'd3403 : mem_out_dec = 6'b111111;
12'd3404 : mem_out_dec = 6'b111111;
12'd3405 : mem_out_dec = 6'b111111;
12'd3406 : mem_out_dec = 6'b111111;
12'd3407 : mem_out_dec = 6'b111111;
12'd3408 : mem_out_dec = 6'b111111;
12'd3409 : mem_out_dec = 6'b111111;
12'd3410 : mem_out_dec = 6'b111111;
12'd3411 : mem_out_dec = 6'b111111;
12'd3412 : mem_out_dec = 6'b111111;
12'd3413 : mem_out_dec = 6'b111111;
12'd3414 : mem_out_dec = 6'b111111;
12'd3415 : mem_out_dec = 6'b111111;
12'd3416 : mem_out_dec = 6'b111111;
12'd3417 : mem_out_dec = 6'b111111;
12'd3418 : mem_out_dec = 6'b111111;
12'd3419 : mem_out_dec = 6'b111111;
12'd3420 : mem_out_dec = 6'b111111;
12'd3421 : mem_out_dec = 6'b111111;
12'd3422 : mem_out_dec = 6'b111111;
12'd3423 : mem_out_dec = 6'b111111;
12'd3424 : mem_out_dec = 6'b111111;
12'd3425 : mem_out_dec = 6'b111111;
12'd3426 : mem_out_dec = 6'b111111;
12'd3427 : mem_out_dec = 6'b111111;
12'd3428 : mem_out_dec = 6'b111111;
12'd3429 : mem_out_dec = 6'b111111;
12'd3430 : mem_out_dec = 6'b111111;
12'd3431 : mem_out_dec = 6'b111111;
12'd3432 : mem_out_dec = 6'b111111;
12'd3433 : mem_out_dec = 6'b111111;
12'd3434 : mem_out_dec = 6'b111111;
12'd3435 : mem_out_dec = 6'b111111;
12'd3436 : mem_out_dec = 6'b111111;
12'd3437 : mem_out_dec = 6'b111111;
12'd3438 : mem_out_dec = 6'b111111;
12'd3439 : mem_out_dec = 6'b111111;
12'd3440 : mem_out_dec = 6'b111111;
12'd3441 : mem_out_dec = 6'b111111;
12'd3442 : mem_out_dec = 6'b111111;
12'd3443 : mem_out_dec = 6'b111111;
12'd3444 : mem_out_dec = 6'b111111;
12'd3445 : mem_out_dec = 6'b111111;
12'd3446 : mem_out_dec = 6'b111111;
12'd3447 : mem_out_dec = 6'b111111;
12'd3448 : mem_out_dec = 6'b111111;
12'd3449 : mem_out_dec = 6'b111111;
12'd3450 : mem_out_dec = 6'b111111;
12'd3451 : mem_out_dec = 6'b000100;
12'd3452 : mem_out_dec = 6'b000101;
12'd3453 : mem_out_dec = 6'b000110;
12'd3454 : mem_out_dec = 6'b000111;
12'd3455 : mem_out_dec = 6'b001000;
12'd3456 : mem_out_dec = 6'b111111;
12'd3457 : mem_out_dec = 6'b111111;
12'd3458 : mem_out_dec = 6'b111111;
12'd3459 : mem_out_dec = 6'b111111;
12'd3460 : mem_out_dec = 6'b111111;
12'd3461 : mem_out_dec = 6'b111111;
12'd3462 : mem_out_dec = 6'b111111;
12'd3463 : mem_out_dec = 6'b111111;
12'd3464 : mem_out_dec = 6'b111111;
12'd3465 : mem_out_dec = 6'b111111;
12'd3466 : mem_out_dec = 6'b111111;
12'd3467 : mem_out_dec = 6'b111111;
12'd3468 : mem_out_dec = 6'b111111;
12'd3469 : mem_out_dec = 6'b111111;
12'd3470 : mem_out_dec = 6'b111111;
12'd3471 : mem_out_dec = 6'b111111;
12'd3472 : mem_out_dec = 6'b111111;
12'd3473 : mem_out_dec = 6'b111111;
12'd3474 : mem_out_dec = 6'b111111;
12'd3475 : mem_out_dec = 6'b111111;
12'd3476 : mem_out_dec = 6'b111111;
12'd3477 : mem_out_dec = 6'b111111;
12'd3478 : mem_out_dec = 6'b111111;
12'd3479 : mem_out_dec = 6'b111111;
12'd3480 : mem_out_dec = 6'b111111;
12'd3481 : mem_out_dec = 6'b111111;
12'd3482 : mem_out_dec = 6'b111111;
12'd3483 : mem_out_dec = 6'b111111;
12'd3484 : mem_out_dec = 6'b111111;
12'd3485 : mem_out_dec = 6'b111111;
12'd3486 : mem_out_dec = 6'b111111;
12'd3487 : mem_out_dec = 6'b111111;
12'd3488 : mem_out_dec = 6'b111111;
12'd3489 : mem_out_dec = 6'b111111;
12'd3490 : mem_out_dec = 6'b111111;
12'd3491 : mem_out_dec = 6'b111111;
12'd3492 : mem_out_dec = 6'b111111;
12'd3493 : mem_out_dec = 6'b111111;
12'd3494 : mem_out_dec = 6'b111111;
12'd3495 : mem_out_dec = 6'b111111;
12'd3496 : mem_out_dec = 6'b111111;
12'd3497 : mem_out_dec = 6'b111111;
12'd3498 : mem_out_dec = 6'b111111;
12'd3499 : mem_out_dec = 6'b111111;
12'd3500 : mem_out_dec = 6'b111111;
12'd3501 : mem_out_dec = 6'b111111;
12'd3502 : mem_out_dec = 6'b111111;
12'd3503 : mem_out_dec = 6'b111111;
12'd3504 : mem_out_dec = 6'b111111;
12'd3505 : mem_out_dec = 6'b111111;
12'd3506 : mem_out_dec = 6'b111111;
12'd3507 : mem_out_dec = 6'b111111;
12'd3508 : mem_out_dec = 6'b111111;
12'd3509 : mem_out_dec = 6'b111111;
12'd3510 : mem_out_dec = 6'b111111;
12'd3511 : mem_out_dec = 6'b111111;
12'd3512 : mem_out_dec = 6'b111111;
12'd3513 : mem_out_dec = 6'b111111;
12'd3514 : mem_out_dec = 6'b111111;
12'd3515 : mem_out_dec = 6'b111111;
12'd3516 : mem_out_dec = 6'b000101;
12'd3517 : mem_out_dec = 6'b000110;
12'd3518 : mem_out_dec = 6'b000110;
12'd3519 : mem_out_dec = 6'b000111;
12'd3520 : mem_out_dec = 6'b111111;
12'd3521 : mem_out_dec = 6'b111111;
12'd3522 : mem_out_dec = 6'b111111;
12'd3523 : mem_out_dec = 6'b111111;
12'd3524 : mem_out_dec = 6'b111111;
12'd3525 : mem_out_dec = 6'b111111;
12'd3526 : mem_out_dec = 6'b111111;
12'd3527 : mem_out_dec = 6'b111111;
12'd3528 : mem_out_dec = 6'b111111;
12'd3529 : mem_out_dec = 6'b111111;
12'd3530 : mem_out_dec = 6'b111111;
12'd3531 : mem_out_dec = 6'b111111;
12'd3532 : mem_out_dec = 6'b111111;
12'd3533 : mem_out_dec = 6'b111111;
12'd3534 : mem_out_dec = 6'b111111;
12'd3535 : mem_out_dec = 6'b111111;
12'd3536 : mem_out_dec = 6'b111111;
12'd3537 : mem_out_dec = 6'b111111;
12'd3538 : mem_out_dec = 6'b111111;
12'd3539 : mem_out_dec = 6'b111111;
12'd3540 : mem_out_dec = 6'b111111;
12'd3541 : mem_out_dec = 6'b111111;
12'd3542 : mem_out_dec = 6'b111111;
12'd3543 : mem_out_dec = 6'b111111;
12'd3544 : mem_out_dec = 6'b111111;
12'd3545 : mem_out_dec = 6'b111111;
12'd3546 : mem_out_dec = 6'b111111;
12'd3547 : mem_out_dec = 6'b111111;
12'd3548 : mem_out_dec = 6'b111111;
12'd3549 : mem_out_dec = 6'b111111;
12'd3550 : mem_out_dec = 6'b111111;
12'd3551 : mem_out_dec = 6'b111111;
12'd3552 : mem_out_dec = 6'b111111;
12'd3553 : mem_out_dec = 6'b111111;
12'd3554 : mem_out_dec = 6'b111111;
12'd3555 : mem_out_dec = 6'b111111;
12'd3556 : mem_out_dec = 6'b111111;
12'd3557 : mem_out_dec = 6'b111111;
12'd3558 : mem_out_dec = 6'b111111;
12'd3559 : mem_out_dec = 6'b111111;
12'd3560 : mem_out_dec = 6'b111111;
12'd3561 : mem_out_dec = 6'b111111;
12'd3562 : mem_out_dec = 6'b111111;
12'd3563 : mem_out_dec = 6'b111111;
12'd3564 : mem_out_dec = 6'b111111;
12'd3565 : mem_out_dec = 6'b111111;
12'd3566 : mem_out_dec = 6'b111111;
12'd3567 : mem_out_dec = 6'b111111;
12'd3568 : mem_out_dec = 6'b111111;
12'd3569 : mem_out_dec = 6'b111111;
12'd3570 : mem_out_dec = 6'b111111;
12'd3571 : mem_out_dec = 6'b111111;
12'd3572 : mem_out_dec = 6'b111111;
12'd3573 : mem_out_dec = 6'b111111;
12'd3574 : mem_out_dec = 6'b111111;
12'd3575 : mem_out_dec = 6'b111111;
12'd3576 : mem_out_dec = 6'b111111;
12'd3577 : mem_out_dec = 6'b111111;
12'd3578 : mem_out_dec = 6'b111111;
12'd3579 : mem_out_dec = 6'b111111;
12'd3580 : mem_out_dec = 6'b111111;
12'd3581 : mem_out_dec = 6'b000101;
12'd3582 : mem_out_dec = 6'b000110;
12'd3583 : mem_out_dec = 6'b000110;
12'd3584 : mem_out_dec = 6'b111111;
12'd3585 : mem_out_dec = 6'b111111;
12'd3586 : mem_out_dec = 6'b111111;
12'd3587 : mem_out_dec = 6'b111111;
12'd3588 : mem_out_dec = 6'b111111;
12'd3589 : mem_out_dec = 6'b111111;
12'd3590 : mem_out_dec = 6'b111111;
12'd3591 : mem_out_dec = 6'b111111;
12'd3592 : mem_out_dec = 6'b111111;
12'd3593 : mem_out_dec = 6'b111111;
12'd3594 : mem_out_dec = 6'b111111;
12'd3595 : mem_out_dec = 6'b111111;
12'd3596 : mem_out_dec = 6'b111111;
12'd3597 : mem_out_dec = 6'b111111;
12'd3598 : mem_out_dec = 6'b111111;
12'd3599 : mem_out_dec = 6'b111111;
12'd3600 : mem_out_dec = 6'b111111;
12'd3601 : mem_out_dec = 6'b111111;
12'd3602 : mem_out_dec = 6'b111111;
12'd3603 : mem_out_dec = 6'b111111;
12'd3604 : mem_out_dec = 6'b111111;
12'd3605 : mem_out_dec = 6'b111111;
12'd3606 : mem_out_dec = 6'b111111;
12'd3607 : mem_out_dec = 6'b111111;
12'd3608 : mem_out_dec = 6'b111111;
12'd3609 : mem_out_dec = 6'b111111;
12'd3610 : mem_out_dec = 6'b111111;
12'd3611 : mem_out_dec = 6'b111111;
12'd3612 : mem_out_dec = 6'b111111;
12'd3613 : mem_out_dec = 6'b111111;
12'd3614 : mem_out_dec = 6'b111111;
12'd3615 : mem_out_dec = 6'b111111;
12'd3616 : mem_out_dec = 6'b111111;
12'd3617 : mem_out_dec = 6'b111111;
12'd3618 : mem_out_dec = 6'b111111;
12'd3619 : mem_out_dec = 6'b111111;
12'd3620 : mem_out_dec = 6'b111111;
12'd3621 : mem_out_dec = 6'b111111;
12'd3622 : mem_out_dec = 6'b111111;
12'd3623 : mem_out_dec = 6'b111111;
12'd3624 : mem_out_dec = 6'b111111;
12'd3625 : mem_out_dec = 6'b111111;
12'd3626 : mem_out_dec = 6'b111111;
12'd3627 : mem_out_dec = 6'b111111;
12'd3628 : mem_out_dec = 6'b111111;
12'd3629 : mem_out_dec = 6'b111111;
12'd3630 : mem_out_dec = 6'b111111;
12'd3631 : mem_out_dec = 6'b111111;
12'd3632 : mem_out_dec = 6'b111111;
12'd3633 : mem_out_dec = 6'b111111;
12'd3634 : mem_out_dec = 6'b111111;
12'd3635 : mem_out_dec = 6'b111111;
12'd3636 : mem_out_dec = 6'b111111;
12'd3637 : mem_out_dec = 6'b111111;
12'd3638 : mem_out_dec = 6'b111111;
12'd3639 : mem_out_dec = 6'b111111;
12'd3640 : mem_out_dec = 6'b111111;
12'd3641 : mem_out_dec = 6'b111111;
12'd3642 : mem_out_dec = 6'b111111;
12'd3643 : mem_out_dec = 6'b111111;
12'd3644 : mem_out_dec = 6'b111111;
12'd3645 : mem_out_dec = 6'b111111;
12'd3646 : mem_out_dec = 6'b000100;
12'd3647 : mem_out_dec = 6'b000101;
12'd3648 : mem_out_dec = 6'b111111;
12'd3649 : mem_out_dec = 6'b111111;
12'd3650 : mem_out_dec = 6'b111111;
12'd3651 : mem_out_dec = 6'b111111;
12'd3652 : mem_out_dec = 6'b111111;
12'd3653 : mem_out_dec = 6'b111111;
12'd3654 : mem_out_dec = 6'b111111;
12'd3655 : mem_out_dec = 6'b111111;
12'd3656 : mem_out_dec = 6'b111111;
12'd3657 : mem_out_dec = 6'b111111;
12'd3658 : mem_out_dec = 6'b111111;
12'd3659 : mem_out_dec = 6'b111111;
12'd3660 : mem_out_dec = 6'b111111;
12'd3661 : mem_out_dec = 6'b111111;
12'd3662 : mem_out_dec = 6'b111111;
12'd3663 : mem_out_dec = 6'b111111;
12'd3664 : mem_out_dec = 6'b111111;
12'd3665 : mem_out_dec = 6'b111111;
12'd3666 : mem_out_dec = 6'b111111;
12'd3667 : mem_out_dec = 6'b111111;
12'd3668 : mem_out_dec = 6'b111111;
12'd3669 : mem_out_dec = 6'b111111;
12'd3670 : mem_out_dec = 6'b111111;
12'd3671 : mem_out_dec = 6'b111111;
12'd3672 : mem_out_dec = 6'b111111;
12'd3673 : mem_out_dec = 6'b111111;
12'd3674 : mem_out_dec = 6'b111111;
12'd3675 : mem_out_dec = 6'b111111;
12'd3676 : mem_out_dec = 6'b111111;
12'd3677 : mem_out_dec = 6'b111111;
12'd3678 : mem_out_dec = 6'b111111;
12'd3679 : mem_out_dec = 6'b111111;
12'd3680 : mem_out_dec = 6'b111111;
12'd3681 : mem_out_dec = 6'b111111;
12'd3682 : mem_out_dec = 6'b111111;
12'd3683 : mem_out_dec = 6'b111111;
12'd3684 : mem_out_dec = 6'b111111;
12'd3685 : mem_out_dec = 6'b111111;
12'd3686 : mem_out_dec = 6'b111111;
12'd3687 : mem_out_dec = 6'b111111;
12'd3688 : mem_out_dec = 6'b111111;
12'd3689 : mem_out_dec = 6'b111111;
12'd3690 : mem_out_dec = 6'b111111;
12'd3691 : mem_out_dec = 6'b111111;
12'd3692 : mem_out_dec = 6'b111111;
12'd3693 : mem_out_dec = 6'b111111;
12'd3694 : mem_out_dec = 6'b111111;
12'd3695 : mem_out_dec = 6'b111111;
12'd3696 : mem_out_dec = 6'b111111;
12'd3697 : mem_out_dec = 6'b111111;
12'd3698 : mem_out_dec = 6'b111111;
12'd3699 : mem_out_dec = 6'b111111;
12'd3700 : mem_out_dec = 6'b111111;
12'd3701 : mem_out_dec = 6'b111111;
12'd3702 : mem_out_dec = 6'b111111;
12'd3703 : mem_out_dec = 6'b111111;
12'd3704 : mem_out_dec = 6'b111111;
12'd3705 : mem_out_dec = 6'b111111;
12'd3706 : mem_out_dec = 6'b111111;
12'd3707 : mem_out_dec = 6'b111111;
12'd3708 : mem_out_dec = 6'b111111;
12'd3709 : mem_out_dec = 6'b111111;
12'd3710 : mem_out_dec = 6'b111111;
12'd3711 : mem_out_dec = 6'b000100;
12'd3712 : mem_out_dec = 6'b111111;
12'd3713 : mem_out_dec = 6'b111111;
12'd3714 : mem_out_dec = 6'b111111;
12'd3715 : mem_out_dec = 6'b111111;
12'd3716 : mem_out_dec = 6'b111111;
12'd3717 : mem_out_dec = 6'b111111;
12'd3718 : mem_out_dec = 6'b111111;
12'd3719 : mem_out_dec = 6'b111111;
12'd3720 : mem_out_dec = 6'b111111;
12'd3721 : mem_out_dec = 6'b111111;
12'd3722 : mem_out_dec = 6'b111111;
12'd3723 : mem_out_dec = 6'b111111;
12'd3724 : mem_out_dec = 6'b111111;
12'd3725 : mem_out_dec = 6'b111111;
12'd3726 : mem_out_dec = 6'b111111;
12'd3727 : mem_out_dec = 6'b111111;
12'd3728 : mem_out_dec = 6'b111111;
12'd3729 : mem_out_dec = 6'b111111;
12'd3730 : mem_out_dec = 6'b111111;
12'd3731 : mem_out_dec = 6'b111111;
12'd3732 : mem_out_dec = 6'b111111;
12'd3733 : mem_out_dec = 6'b111111;
12'd3734 : mem_out_dec = 6'b111111;
12'd3735 : mem_out_dec = 6'b111111;
12'd3736 : mem_out_dec = 6'b111111;
12'd3737 : mem_out_dec = 6'b111111;
12'd3738 : mem_out_dec = 6'b111111;
12'd3739 : mem_out_dec = 6'b111111;
12'd3740 : mem_out_dec = 6'b111111;
12'd3741 : mem_out_dec = 6'b111111;
12'd3742 : mem_out_dec = 6'b111111;
12'd3743 : mem_out_dec = 6'b111111;
12'd3744 : mem_out_dec = 6'b111111;
12'd3745 : mem_out_dec = 6'b111111;
12'd3746 : mem_out_dec = 6'b111111;
12'd3747 : mem_out_dec = 6'b111111;
12'd3748 : mem_out_dec = 6'b111111;
12'd3749 : mem_out_dec = 6'b111111;
12'd3750 : mem_out_dec = 6'b111111;
12'd3751 : mem_out_dec = 6'b111111;
12'd3752 : mem_out_dec = 6'b111111;
12'd3753 : mem_out_dec = 6'b111111;
12'd3754 : mem_out_dec = 6'b111111;
12'd3755 : mem_out_dec = 6'b111111;
12'd3756 : mem_out_dec = 6'b111111;
12'd3757 : mem_out_dec = 6'b111111;
12'd3758 : mem_out_dec = 6'b111111;
12'd3759 : mem_out_dec = 6'b111111;
12'd3760 : mem_out_dec = 6'b111111;
12'd3761 : mem_out_dec = 6'b111111;
12'd3762 : mem_out_dec = 6'b111111;
12'd3763 : mem_out_dec = 6'b111111;
12'd3764 : mem_out_dec = 6'b111111;
12'd3765 : mem_out_dec = 6'b111111;
12'd3766 : mem_out_dec = 6'b111111;
12'd3767 : mem_out_dec = 6'b111111;
12'd3768 : mem_out_dec = 6'b111111;
12'd3769 : mem_out_dec = 6'b111111;
12'd3770 : mem_out_dec = 6'b111111;
12'd3771 : mem_out_dec = 6'b111111;
12'd3772 : mem_out_dec = 6'b111111;
12'd3773 : mem_out_dec = 6'b111111;
12'd3774 : mem_out_dec = 6'b111111;
12'd3775 : mem_out_dec = 6'b111111;
12'd3776 : mem_out_dec = 6'b111111;
12'd3777 : mem_out_dec = 6'b111111;
12'd3778 : mem_out_dec = 6'b111111;
12'd3779 : mem_out_dec = 6'b111111;
12'd3780 : mem_out_dec = 6'b111111;
12'd3781 : mem_out_dec = 6'b111111;
12'd3782 : mem_out_dec = 6'b111111;
12'd3783 : mem_out_dec = 6'b111111;
12'd3784 : mem_out_dec = 6'b111111;
12'd3785 : mem_out_dec = 6'b111111;
12'd3786 : mem_out_dec = 6'b111111;
12'd3787 : mem_out_dec = 6'b111111;
12'd3788 : mem_out_dec = 6'b111111;
12'd3789 : mem_out_dec = 6'b111111;
12'd3790 : mem_out_dec = 6'b111111;
12'd3791 : mem_out_dec = 6'b111111;
12'd3792 : mem_out_dec = 6'b111111;
12'd3793 : mem_out_dec = 6'b111111;
12'd3794 : mem_out_dec = 6'b111111;
12'd3795 : mem_out_dec = 6'b111111;
12'd3796 : mem_out_dec = 6'b111111;
12'd3797 : mem_out_dec = 6'b111111;
12'd3798 : mem_out_dec = 6'b111111;
12'd3799 : mem_out_dec = 6'b111111;
12'd3800 : mem_out_dec = 6'b111111;
12'd3801 : mem_out_dec = 6'b111111;
12'd3802 : mem_out_dec = 6'b111111;
12'd3803 : mem_out_dec = 6'b111111;
12'd3804 : mem_out_dec = 6'b111111;
12'd3805 : mem_out_dec = 6'b111111;
12'd3806 : mem_out_dec = 6'b111111;
12'd3807 : mem_out_dec = 6'b111111;
12'd3808 : mem_out_dec = 6'b111111;
12'd3809 : mem_out_dec = 6'b111111;
12'd3810 : mem_out_dec = 6'b111111;
12'd3811 : mem_out_dec = 6'b111111;
12'd3812 : mem_out_dec = 6'b111111;
12'd3813 : mem_out_dec = 6'b111111;
12'd3814 : mem_out_dec = 6'b111111;
12'd3815 : mem_out_dec = 6'b111111;
12'd3816 : mem_out_dec = 6'b111111;
12'd3817 : mem_out_dec = 6'b111111;
12'd3818 : mem_out_dec = 6'b111111;
12'd3819 : mem_out_dec = 6'b111111;
12'd3820 : mem_out_dec = 6'b111111;
12'd3821 : mem_out_dec = 6'b111111;
12'd3822 : mem_out_dec = 6'b111111;
12'd3823 : mem_out_dec = 6'b111111;
12'd3824 : mem_out_dec = 6'b111111;
12'd3825 : mem_out_dec = 6'b111111;
12'd3826 : mem_out_dec = 6'b111111;
12'd3827 : mem_out_dec = 6'b111111;
12'd3828 : mem_out_dec = 6'b111111;
12'd3829 : mem_out_dec = 6'b111111;
12'd3830 : mem_out_dec = 6'b111111;
12'd3831 : mem_out_dec = 6'b111111;
12'd3832 : mem_out_dec = 6'b111111;
12'd3833 : mem_out_dec = 6'b111111;
12'd3834 : mem_out_dec = 6'b111111;
12'd3835 : mem_out_dec = 6'b111111;
12'd3836 : mem_out_dec = 6'b111111;
12'd3837 : mem_out_dec = 6'b111111;
12'd3838 : mem_out_dec = 6'b111111;
12'd3839 : mem_out_dec = 6'b111111;
12'd3840 : mem_out_dec = 6'b111111;
12'd3841 : mem_out_dec = 6'b111111;
12'd3842 : mem_out_dec = 6'b111111;
12'd3843 : mem_out_dec = 6'b111111;
12'd3844 : mem_out_dec = 6'b111111;
12'd3845 : mem_out_dec = 6'b111111;
12'd3846 : mem_out_dec = 6'b111111;
12'd3847 : mem_out_dec = 6'b111111;
12'd3848 : mem_out_dec = 6'b111111;
12'd3849 : mem_out_dec = 6'b111111;
12'd3850 : mem_out_dec = 6'b111111;
12'd3851 : mem_out_dec = 6'b111111;
12'd3852 : mem_out_dec = 6'b111111;
12'd3853 : mem_out_dec = 6'b111111;
12'd3854 : mem_out_dec = 6'b111111;
12'd3855 : mem_out_dec = 6'b111111;
12'd3856 : mem_out_dec = 6'b111111;
12'd3857 : mem_out_dec = 6'b111111;
12'd3858 : mem_out_dec = 6'b111111;
12'd3859 : mem_out_dec = 6'b111111;
12'd3860 : mem_out_dec = 6'b111111;
12'd3861 : mem_out_dec = 6'b111111;
12'd3862 : mem_out_dec = 6'b111111;
12'd3863 : mem_out_dec = 6'b111111;
12'd3864 : mem_out_dec = 6'b111111;
12'd3865 : mem_out_dec = 6'b111111;
12'd3866 : mem_out_dec = 6'b111111;
12'd3867 : mem_out_dec = 6'b111111;
12'd3868 : mem_out_dec = 6'b111111;
12'd3869 : mem_out_dec = 6'b111111;
12'd3870 : mem_out_dec = 6'b111111;
12'd3871 : mem_out_dec = 6'b111111;
12'd3872 : mem_out_dec = 6'b111111;
12'd3873 : mem_out_dec = 6'b111111;
12'd3874 : mem_out_dec = 6'b111111;
12'd3875 : mem_out_dec = 6'b111111;
12'd3876 : mem_out_dec = 6'b111111;
12'd3877 : mem_out_dec = 6'b111111;
12'd3878 : mem_out_dec = 6'b111111;
12'd3879 : mem_out_dec = 6'b111111;
12'd3880 : mem_out_dec = 6'b111111;
12'd3881 : mem_out_dec = 6'b111111;
12'd3882 : mem_out_dec = 6'b111111;
12'd3883 : mem_out_dec = 6'b111111;
12'd3884 : mem_out_dec = 6'b111111;
12'd3885 : mem_out_dec = 6'b111111;
12'd3886 : mem_out_dec = 6'b111111;
12'd3887 : mem_out_dec = 6'b111111;
12'd3888 : mem_out_dec = 6'b111111;
12'd3889 : mem_out_dec = 6'b111111;
12'd3890 : mem_out_dec = 6'b111111;
12'd3891 : mem_out_dec = 6'b111111;
12'd3892 : mem_out_dec = 6'b111111;
12'd3893 : mem_out_dec = 6'b111111;
12'd3894 : mem_out_dec = 6'b111111;
12'd3895 : mem_out_dec = 6'b111111;
12'd3896 : mem_out_dec = 6'b111111;
12'd3897 : mem_out_dec = 6'b111111;
12'd3898 : mem_out_dec = 6'b111111;
12'd3899 : mem_out_dec = 6'b111111;
12'd3900 : mem_out_dec = 6'b111111;
12'd3901 : mem_out_dec = 6'b111111;
12'd3902 : mem_out_dec = 6'b111111;
12'd3903 : mem_out_dec = 6'b111111;
12'd3904 : mem_out_dec = 6'b111111;
12'd3905 : mem_out_dec = 6'b111111;
12'd3906 : mem_out_dec = 6'b111111;
12'd3907 : mem_out_dec = 6'b111111;
12'd3908 : mem_out_dec = 6'b111111;
12'd3909 : mem_out_dec = 6'b111111;
12'd3910 : mem_out_dec = 6'b111111;
12'd3911 : mem_out_dec = 6'b111111;
12'd3912 : mem_out_dec = 6'b111111;
12'd3913 : mem_out_dec = 6'b111111;
12'd3914 : mem_out_dec = 6'b111111;
12'd3915 : mem_out_dec = 6'b111111;
12'd3916 : mem_out_dec = 6'b111111;
12'd3917 : mem_out_dec = 6'b111111;
12'd3918 : mem_out_dec = 6'b111111;
12'd3919 : mem_out_dec = 6'b111111;
12'd3920 : mem_out_dec = 6'b111111;
12'd3921 : mem_out_dec = 6'b111111;
12'd3922 : mem_out_dec = 6'b111111;
12'd3923 : mem_out_dec = 6'b111111;
12'd3924 : mem_out_dec = 6'b111111;
12'd3925 : mem_out_dec = 6'b111111;
12'd3926 : mem_out_dec = 6'b111111;
12'd3927 : mem_out_dec = 6'b111111;
12'd3928 : mem_out_dec = 6'b111111;
12'd3929 : mem_out_dec = 6'b111111;
12'd3930 : mem_out_dec = 6'b111111;
12'd3931 : mem_out_dec = 6'b111111;
12'd3932 : mem_out_dec = 6'b111111;
12'd3933 : mem_out_dec = 6'b111111;
12'd3934 : mem_out_dec = 6'b111111;
12'd3935 : mem_out_dec = 6'b111111;
12'd3936 : mem_out_dec = 6'b111111;
12'd3937 : mem_out_dec = 6'b111111;
12'd3938 : mem_out_dec = 6'b111111;
12'd3939 : mem_out_dec = 6'b111111;
12'd3940 : mem_out_dec = 6'b111111;
12'd3941 : mem_out_dec = 6'b111111;
12'd3942 : mem_out_dec = 6'b111111;
12'd3943 : mem_out_dec = 6'b111111;
12'd3944 : mem_out_dec = 6'b111111;
12'd3945 : mem_out_dec = 6'b111111;
12'd3946 : mem_out_dec = 6'b111111;
12'd3947 : mem_out_dec = 6'b111111;
12'd3948 : mem_out_dec = 6'b111111;
12'd3949 : mem_out_dec = 6'b111111;
12'd3950 : mem_out_dec = 6'b111111;
12'd3951 : mem_out_dec = 6'b111111;
12'd3952 : mem_out_dec = 6'b111111;
12'd3953 : mem_out_dec = 6'b111111;
12'd3954 : mem_out_dec = 6'b111111;
12'd3955 : mem_out_dec = 6'b111111;
12'd3956 : mem_out_dec = 6'b111111;
12'd3957 : mem_out_dec = 6'b111111;
12'd3958 : mem_out_dec = 6'b111111;
12'd3959 : mem_out_dec = 6'b111111;
12'd3960 : mem_out_dec = 6'b111111;
12'd3961 : mem_out_dec = 6'b111111;
12'd3962 : mem_out_dec = 6'b111111;
12'd3963 : mem_out_dec = 6'b111111;
12'd3964 : mem_out_dec = 6'b111111;
12'd3965 : mem_out_dec = 6'b111111;
12'd3966 : mem_out_dec = 6'b111111;
12'd3967 : mem_out_dec = 6'b111111;
12'd3968 : mem_out_dec = 6'b111111;
12'd3969 : mem_out_dec = 6'b111111;
12'd3970 : mem_out_dec = 6'b111111;
12'd3971 : mem_out_dec = 6'b111111;
12'd3972 : mem_out_dec = 6'b111111;
12'd3973 : mem_out_dec = 6'b111111;
12'd3974 : mem_out_dec = 6'b111111;
12'd3975 : mem_out_dec = 6'b111111;
12'd3976 : mem_out_dec = 6'b111111;
12'd3977 : mem_out_dec = 6'b111111;
12'd3978 : mem_out_dec = 6'b111111;
12'd3979 : mem_out_dec = 6'b111111;
12'd3980 : mem_out_dec = 6'b111111;
12'd3981 : mem_out_dec = 6'b111111;
12'd3982 : mem_out_dec = 6'b111111;
12'd3983 : mem_out_dec = 6'b111111;
12'd3984 : mem_out_dec = 6'b111111;
12'd3985 : mem_out_dec = 6'b111111;
12'd3986 : mem_out_dec = 6'b111111;
12'd3987 : mem_out_dec = 6'b111111;
12'd3988 : mem_out_dec = 6'b111111;
12'd3989 : mem_out_dec = 6'b111111;
12'd3990 : mem_out_dec = 6'b111111;
12'd3991 : mem_out_dec = 6'b111111;
12'd3992 : mem_out_dec = 6'b111111;
12'd3993 : mem_out_dec = 6'b111111;
12'd3994 : mem_out_dec = 6'b111111;
12'd3995 : mem_out_dec = 6'b111111;
12'd3996 : mem_out_dec = 6'b111111;
12'd3997 : mem_out_dec = 6'b111111;
12'd3998 : mem_out_dec = 6'b111111;
12'd3999 : mem_out_dec = 6'b111111;
12'd4000 : mem_out_dec = 6'b111111;
12'd4001 : mem_out_dec = 6'b111111;
12'd4002 : mem_out_dec = 6'b111111;
12'd4003 : mem_out_dec = 6'b111111;
12'd4004 : mem_out_dec = 6'b111111;
12'd4005 : mem_out_dec = 6'b111111;
12'd4006 : mem_out_dec = 6'b111111;
12'd4007 : mem_out_dec = 6'b111111;
12'd4008 : mem_out_dec = 6'b111111;
12'd4009 : mem_out_dec = 6'b111111;
12'd4010 : mem_out_dec = 6'b111111;
12'd4011 : mem_out_dec = 6'b111111;
12'd4012 : mem_out_dec = 6'b111111;
12'd4013 : mem_out_dec = 6'b111111;
12'd4014 : mem_out_dec = 6'b111111;
12'd4015 : mem_out_dec = 6'b111111;
12'd4016 : mem_out_dec = 6'b111111;
12'd4017 : mem_out_dec = 6'b111111;
12'd4018 : mem_out_dec = 6'b111111;
12'd4019 : mem_out_dec = 6'b111111;
12'd4020 : mem_out_dec = 6'b111111;
12'd4021 : mem_out_dec = 6'b111111;
12'd4022 : mem_out_dec = 6'b111111;
12'd4023 : mem_out_dec = 6'b111111;
12'd4024 : mem_out_dec = 6'b111111;
12'd4025 : mem_out_dec = 6'b111111;
12'd4026 : mem_out_dec = 6'b111111;
12'd4027 : mem_out_dec = 6'b111111;
12'd4028 : mem_out_dec = 6'b111111;
12'd4029 : mem_out_dec = 6'b111111;
12'd4030 : mem_out_dec = 6'b111111;
12'd4031 : mem_out_dec = 6'b111111;
12'd4032 : mem_out_dec = 6'b111111;
12'd4033 : mem_out_dec = 6'b111111;
12'd4034 : mem_out_dec = 6'b111111;
12'd4035 : mem_out_dec = 6'b111111;
12'd4036 : mem_out_dec = 6'b111111;
12'd4037 : mem_out_dec = 6'b111111;
12'd4038 : mem_out_dec = 6'b111111;
12'd4039 : mem_out_dec = 6'b111111;
12'd4040 : mem_out_dec = 6'b111111;
12'd4041 : mem_out_dec = 6'b111111;
12'd4042 : mem_out_dec = 6'b111111;
12'd4043 : mem_out_dec = 6'b111111;
12'd4044 : mem_out_dec = 6'b111111;
12'd4045 : mem_out_dec = 6'b111111;
12'd4046 : mem_out_dec = 6'b111111;
12'd4047 : mem_out_dec = 6'b111111;
12'd4048 : mem_out_dec = 6'b111111;
12'd4049 : mem_out_dec = 6'b111111;
12'd4050 : mem_out_dec = 6'b111111;
12'd4051 : mem_out_dec = 6'b111111;
12'd4052 : mem_out_dec = 6'b111111;
12'd4053 : mem_out_dec = 6'b111111;
12'd4054 : mem_out_dec = 6'b111111;
12'd4055 : mem_out_dec = 6'b111111;
12'd4056 : mem_out_dec = 6'b111111;
12'd4057 : mem_out_dec = 6'b111111;
12'd4058 : mem_out_dec = 6'b111111;
12'd4059 : mem_out_dec = 6'b111111;
12'd4060 : mem_out_dec = 6'b111111;
12'd4061 : mem_out_dec = 6'b111111;
12'd4062 : mem_out_dec = 6'b111111;
12'd4063 : mem_out_dec = 6'b111111;
12'd4064 : mem_out_dec = 6'b111111;
12'd4065 : mem_out_dec = 6'b111111;
12'd4066 : mem_out_dec = 6'b111111;
12'd4067 : mem_out_dec = 6'b111111;
12'd4068 : mem_out_dec = 6'b111111;
12'd4069 : mem_out_dec = 6'b111111;
12'd4070 : mem_out_dec = 6'b111111;
12'd4071 : mem_out_dec = 6'b111111;
12'd4072 : mem_out_dec = 6'b111111;
12'd4073 : mem_out_dec = 6'b111111;
12'd4074 : mem_out_dec = 6'b111111;
12'd4075 : mem_out_dec = 6'b111111;
12'd4076 : mem_out_dec = 6'b111111;
12'd4077 : mem_out_dec = 6'b111111;
12'd4078 : mem_out_dec = 6'b111111;
12'd4079 : mem_out_dec = 6'b111111;
12'd4080 : mem_out_dec = 6'b111111;
12'd4081 : mem_out_dec = 6'b111111;
12'd4082 : mem_out_dec = 6'b111111;
12'd4083 : mem_out_dec = 6'b111111;
12'd4084 : mem_out_dec = 6'b111111;
12'd4085 : mem_out_dec = 6'b111111;
12'd4086 : mem_out_dec = 6'b111111;
12'd4087 : mem_out_dec = 6'b111111;
12'd4088 : mem_out_dec = 6'b111111;
12'd4089 : mem_out_dec = 6'b111111;
12'd4090 : mem_out_dec = 6'b111111;
12'd4091 : mem_out_dec = 6'b111111;
12'd4092 : mem_out_dec = 6'b111111;
12'd4093 : mem_out_dec = 6'b111111;
12'd4094 : mem_out_dec = 6'b111111;
12'd4095 : mem_out_dec = 6'b111111;
endcase
end
always @ (posedge clk) begin
dec_cnt <= #TCQ mem_out_dec;
end
endmodule
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
// Date : Tue Sep 19 09:38:30 2017
// Host : DarkCube running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zynq_design_1_processing_system7_0_0_sim_netlist.v
// Design : zynq_design_1_processing_system7_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* C_DM_WIDTH = "4" *) (* C_DQS_WIDTH = "4" *) (* C_DQ_WIDTH = "32" *)
(* C_EMIO_GPIO_WIDTH = "64" *) (* C_EN_EMIO_ENET0 = "0" *) (* C_EN_EMIO_ENET1 = "0" *)
(* C_EN_EMIO_PJTAG = "0" *) (* C_EN_EMIO_TRACE = "0" *) (* C_FCLK_CLK0_BUF = "TRUE" *)
(* C_FCLK_CLK1_BUF = "FALSE" *) (* C_FCLK_CLK2_BUF = "FALSE" *) (* C_FCLK_CLK3_BUF = "FALSE" *)
(* C_GP0_EN_MODIFIABLE_TXN = "1" *) (* C_GP1_EN_MODIFIABLE_TXN = "1" *) (* C_INCLUDE_ACP_TRANS_CHECK = "0" *)
(* C_INCLUDE_TRACE_BUFFER = "0" *) (* C_IRQ_F2P_MODE = "DIRECT" *) (* C_MIO_PRIMITIVE = "54" *)
(* C_M_AXI_GP0_ENABLE_STATIC_REMAP = "0" *) (* C_M_AXI_GP0_ID_WIDTH = "12" *) (* C_M_AXI_GP0_THREAD_ID_WIDTH = "12" *)
(* C_M_AXI_GP1_ENABLE_STATIC_REMAP = "0" *) (* C_M_AXI_GP1_ID_WIDTH = "12" *) (* C_M_AXI_GP1_THREAD_ID_WIDTH = "12" *)
(* C_NUM_F2P_INTR_INPUTS = "1" *) (* C_PACKAGE_NAME = "clg484" *) (* C_PS7_SI_REV = "PRODUCTION" *)
(* C_S_AXI_ACP_ARUSER_VAL = "31" *) (* C_S_AXI_ACP_AWUSER_VAL = "31" *) (* C_S_AXI_ACP_ID_WIDTH = "3" *)
(* C_S_AXI_GP0_ID_WIDTH = "6" *) (* C_S_AXI_GP1_ID_WIDTH = "6" *) (* C_S_AXI_HP0_DATA_WIDTH = "64" *)
(* C_S_AXI_HP0_ID_WIDTH = "6" *) (* C_S_AXI_HP1_DATA_WIDTH = "64" *) (* C_S_AXI_HP1_ID_WIDTH = "6" *)
(* C_S_AXI_HP2_DATA_WIDTH = "64" *) (* C_S_AXI_HP2_ID_WIDTH = "6" *) (* C_S_AXI_HP3_DATA_WIDTH = "64" *)
(* C_S_AXI_HP3_ID_WIDTH = "6" *) (* C_TRACE_BUFFER_CLOCK_DELAY = "12" *) (* C_TRACE_BUFFER_FIFO_SIZE = "128" *)
(* C_TRACE_INTERNAL_WIDTH = "2" *) (* C_TRACE_PIPELINE_WIDTH = "8" *) (* C_USE_AXI_NONSECURE = "0" *)
(* C_USE_DEFAULT_ACP_USER_VAL = "0" *) (* C_USE_M_AXI_GP0 = "1" *) (* C_USE_M_AXI_GP1 = "0" *)
(* C_USE_S_AXI_ACP = "0" *) (* C_USE_S_AXI_GP0 = "0" *) (* C_USE_S_AXI_GP1 = "0" *)
(* C_USE_S_AXI_HP0 = "0" *) (* C_USE_S_AXI_HP1 = "0" *) (* C_USE_S_AXI_HP2 = "0" *)
(* C_USE_S_AXI_HP3 = "0" *) (* HW_HANDOFF = "zynq_design_1_processing_system7_0_0.hwdef" *) (* POWER = "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333313} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={10} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200.000000} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>" *)
(* USE_TRACE_DATA_EDGE_DETECTOR = "0" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7
(CAN0_PHY_TX,
CAN0_PHY_RX,
CAN1_PHY_TX,
CAN1_PHY_RX,
ENET0_GMII_TX_EN,
ENET0_GMII_TX_ER,
ENET0_MDIO_MDC,
ENET0_MDIO_O,
ENET0_MDIO_T,
ENET0_PTP_DELAY_REQ_RX,
ENET0_PTP_DELAY_REQ_TX,
ENET0_PTP_PDELAY_REQ_RX,
ENET0_PTP_PDELAY_REQ_TX,
ENET0_PTP_PDELAY_RESP_RX,
ENET0_PTP_PDELAY_RESP_TX,
ENET0_PTP_SYNC_FRAME_RX,
ENET0_PTP_SYNC_FRAME_TX,
ENET0_SOF_RX,
ENET0_SOF_TX,
ENET0_GMII_TXD,
ENET0_GMII_COL,
ENET0_GMII_CRS,
ENET0_GMII_RX_CLK,
ENET0_GMII_RX_DV,
ENET0_GMII_RX_ER,
ENET0_GMII_TX_CLK,
ENET0_MDIO_I,
ENET0_EXT_INTIN,
ENET0_GMII_RXD,
ENET1_GMII_TX_EN,
ENET1_GMII_TX_ER,
ENET1_MDIO_MDC,
ENET1_MDIO_O,
ENET1_MDIO_T,
ENET1_PTP_DELAY_REQ_RX,
ENET1_PTP_DELAY_REQ_TX,
ENET1_PTP_PDELAY_REQ_RX,
ENET1_PTP_PDELAY_REQ_TX,
ENET1_PTP_PDELAY_RESP_RX,
ENET1_PTP_PDELAY_RESP_TX,
ENET1_PTP_SYNC_FRAME_RX,
ENET1_PTP_SYNC_FRAME_TX,
ENET1_SOF_RX,
ENET1_SOF_TX,
ENET1_GMII_TXD,
ENET1_GMII_COL,
ENET1_GMII_CRS,
ENET1_GMII_RX_CLK,
ENET1_GMII_RX_DV,
ENET1_GMII_RX_ER,
ENET1_GMII_TX_CLK,
ENET1_MDIO_I,
ENET1_EXT_INTIN,
ENET1_GMII_RXD,
GPIO_I,
GPIO_O,
GPIO_T,
I2C0_SDA_I,
I2C0_SDA_O,
I2C0_SDA_T,
I2C0_SCL_I,
I2C0_SCL_O,
I2C0_SCL_T,
I2C1_SDA_I,
I2C1_SDA_O,
I2C1_SDA_T,
I2C1_SCL_I,
I2C1_SCL_O,
I2C1_SCL_T,
PJTAG_TCK,
PJTAG_TMS,
PJTAG_TDI,
PJTAG_TDO,
SDIO0_CLK,
SDIO0_CLK_FB,
SDIO0_CMD_O,
SDIO0_CMD_I,
SDIO0_CMD_T,
SDIO0_DATA_I,
SDIO0_DATA_O,
SDIO0_DATA_T,
SDIO0_LED,
SDIO0_CDN,
SDIO0_WP,
SDIO0_BUSPOW,
SDIO0_BUSVOLT,
SDIO1_CLK,
SDIO1_CLK_FB,
SDIO1_CMD_O,
SDIO1_CMD_I,
SDIO1_CMD_T,
SDIO1_DATA_I,
SDIO1_DATA_O,
SDIO1_DATA_T,
SDIO1_LED,
SDIO1_CDN,
SDIO1_WP,
SDIO1_BUSPOW,
SDIO1_BUSVOLT,
SPI0_SCLK_I,
SPI0_SCLK_O,
SPI0_SCLK_T,
SPI0_MOSI_I,
SPI0_MOSI_O,
SPI0_MOSI_T,
SPI0_MISO_I,
SPI0_MISO_O,
SPI0_MISO_T,
SPI0_SS_I,
SPI0_SS_O,
SPI0_SS1_O,
SPI0_SS2_O,
SPI0_SS_T,
SPI1_SCLK_I,
SPI1_SCLK_O,
SPI1_SCLK_T,
SPI1_MOSI_I,
SPI1_MOSI_O,
SPI1_MOSI_T,
SPI1_MISO_I,
SPI1_MISO_O,
SPI1_MISO_T,
SPI1_SS_I,
SPI1_SS_O,
SPI1_SS1_O,
SPI1_SS2_O,
SPI1_SS_T,
UART0_DTRN,
UART0_RTSN,
UART0_TX,
UART0_CTSN,
UART0_DCDN,
UART0_DSRN,
UART0_RIN,
UART0_RX,
UART1_DTRN,
UART1_RTSN,
UART1_TX,
UART1_CTSN,
UART1_DCDN,
UART1_DSRN,
UART1_RIN,
UART1_RX,
TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT,
TTC0_CLK0_IN,
TTC0_CLK1_IN,
TTC0_CLK2_IN,
TTC1_WAVE0_OUT,
TTC1_WAVE1_OUT,
TTC1_WAVE2_OUT,
TTC1_CLK0_IN,
TTC1_CLK1_IN,
TTC1_CLK2_IN,
WDT_CLK_IN,
WDT_RST_OUT,
TRACE_CLK,
TRACE_CTL,
TRACE_DATA,
TRACE_CLK_OUT,
USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
USB1_PORT_INDCTL,
USB1_VBUS_PWRSELECT,
USB1_VBUS_PWRFAULT,
SRAM_INTIN,
M_AXI_GP0_ARESETN,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
M_AXI_GP1_ARESETN,
M_AXI_GP1_ARVALID,
M_AXI_GP1_AWVALID,
M_AXI_GP1_BREADY,
M_AXI_GP1_RREADY,
M_AXI_GP1_WLAST,
M_AXI_GP1_WVALID,
M_AXI_GP1_ARID,
M_AXI_GP1_AWID,
M_AXI_GP1_WID,
M_AXI_GP1_ARBURST,
M_AXI_GP1_ARLOCK,
M_AXI_GP1_ARSIZE,
M_AXI_GP1_AWBURST,
M_AXI_GP1_AWLOCK,
M_AXI_GP1_AWSIZE,
M_AXI_GP1_ARPROT,
M_AXI_GP1_AWPROT,
M_AXI_GP1_ARADDR,
M_AXI_GP1_AWADDR,
M_AXI_GP1_WDATA,
M_AXI_GP1_ARCACHE,
M_AXI_GP1_ARLEN,
M_AXI_GP1_ARQOS,
M_AXI_GP1_AWCACHE,
M_AXI_GP1_AWLEN,
M_AXI_GP1_AWQOS,
M_AXI_GP1_WSTRB,
M_AXI_GP1_ACLK,
M_AXI_GP1_ARREADY,
M_AXI_GP1_AWREADY,
M_AXI_GP1_BVALID,
M_AXI_GP1_RLAST,
M_AXI_GP1_RVALID,
M_AXI_GP1_WREADY,
M_AXI_GP1_BID,
M_AXI_GP1_RID,
M_AXI_GP1_BRESP,
M_AXI_GP1_RRESP,
M_AXI_GP1_RDATA,
S_AXI_GP0_ARESETN,
S_AXI_GP0_ARREADY,
S_AXI_GP0_AWREADY,
S_AXI_GP0_BVALID,
S_AXI_GP0_RLAST,
S_AXI_GP0_RVALID,
S_AXI_GP0_WREADY,
S_AXI_GP0_BRESP,
S_AXI_GP0_RRESP,
S_AXI_GP0_RDATA,
S_AXI_GP0_BID,
S_AXI_GP0_RID,
S_AXI_GP0_ACLK,
S_AXI_GP0_ARVALID,
S_AXI_GP0_AWVALID,
S_AXI_GP0_BREADY,
S_AXI_GP0_RREADY,
S_AXI_GP0_WLAST,
S_AXI_GP0_WVALID,
S_AXI_GP0_ARBURST,
S_AXI_GP0_ARLOCK,
S_AXI_GP0_ARSIZE,
S_AXI_GP0_AWBURST,
S_AXI_GP0_AWLOCK,
S_AXI_GP0_AWSIZE,
S_AXI_GP0_ARPROT,
S_AXI_GP0_AWPROT,
S_AXI_GP0_ARADDR,
S_AXI_GP0_AWADDR,
S_AXI_GP0_WDATA,
S_AXI_GP0_ARCACHE,
S_AXI_GP0_ARLEN,
S_AXI_GP0_ARQOS,
S_AXI_GP0_AWCACHE,
S_AXI_GP0_AWLEN,
S_AXI_GP0_AWQOS,
S_AXI_GP0_WSTRB,
S_AXI_GP0_ARID,
S_AXI_GP0_AWID,
S_AXI_GP0_WID,
S_AXI_GP1_ARESETN,
S_AXI_GP1_ARREADY,
S_AXI_GP1_AWREADY,
S_AXI_GP1_BVALID,
S_AXI_GP1_RLAST,
S_AXI_GP1_RVALID,
S_AXI_GP1_WREADY,
S_AXI_GP1_BRESP,
S_AXI_GP1_RRESP,
S_AXI_GP1_RDATA,
S_AXI_GP1_BID,
S_AXI_GP1_RID,
S_AXI_GP1_ACLK,
S_AXI_GP1_ARVALID,
S_AXI_GP1_AWVALID,
S_AXI_GP1_BREADY,
S_AXI_GP1_RREADY,
S_AXI_GP1_WLAST,
S_AXI_GP1_WVALID,
S_AXI_GP1_ARBURST,
S_AXI_GP1_ARLOCK,
S_AXI_GP1_ARSIZE,
S_AXI_GP1_AWBURST,
S_AXI_GP1_AWLOCK,
S_AXI_GP1_AWSIZE,
S_AXI_GP1_ARPROT,
S_AXI_GP1_AWPROT,
S_AXI_GP1_ARADDR,
S_AXI_GP1_AWADDR,
S_AXI_GP1_WDATA,
S_AXI_GP1_ARCACHE,
S_AXI_GP1_ARLEN,
S_AXI_GP1_ARQOS,
S_AXI_GP1_AWCACHE,
S_AXI_GP1_AWLEN,
S_AXI_GP1_AWQOS,
S_AXI_GP1_WSTRB,
S_AXI_GP1_ARID,
S_AXI_GP1_AWID,
S_AXI_GP1_WID,
S_AXI_ACP_ARESETN,
S_AXI_ACP_ARREADY,
S_AXI_ACP_AWREADY,
S_AXI_ACP_BVALID,
S_AXI_ACP_RLAST,
S_AXI_ACP_RVALID,
S_AXI_ACP_WREADY,
S_AXI_ACP_BRESP,
S_AXI_ACP_RRESP,
S_AXI_ACP_BID,
S_AXI_ACP_RID,
S_AXI_ACP_RDATA,
S_AXI_ACP_ACLK,
S_AXI_ACP_ARVALID,
S_AXI_ACP_AWVALID,
S_AXI_ACP_BREADY,
S_AXI_ACP_RREADY,
S_AXI_ACP_WLAST,
S_AXI_ACP_WVALID,
S_AXI_ACP_ARID,
S_AXI_ACP_ARPROT,
S_AXI_ACP_AWID,
S_AXI_ACP_AWPROT,
S_AXI_ACP_WID,
S_AXI_ACP_ARADDR,
S_AXI_ACP_AWADDR,
S_AXI_ACP_ARCACHE,
S_AXI_ACP_ARLEN,
S_AXI_ACP_ARQOS,
S_AXI_ACP_AWCACHE,
S_AXI_ACP_AWLEN,
S_AXI_ACP_AWQOS,
S_AXI_ACP_ARBURST,
S_AXI_ACP_ARLOCK,
S_AXI_ACP_ARSIZE,
S_AXI_ACP_AWBURST,
S_AXI_ACP_AWLOCK,
S_AXI_ACP_AWSIZE,
S_AXI_ACP_ARUSER,
S_AXI_ACP_AWUSER,
S_AXI_ACP_WDATA,
S_AXI_ACP_WSTRB,
S_AXI_HP0_ARESETN,
S_AXI_HP0_ARREADY,
S_AXI_HP0_AWREADY,
S_AXI_HP0_BVALID,
S_AXI_HP0_RLAST,
S_AXI_HP0_RVALID,
S_AXI_HP0_WREADY,
S_AXI_HP0_BRESP,
S_AXI_HP0_RRESP,
S_AXI_HP0_BID,
S_AXI_HP0_RID,
S_AXI_HP0_RDATA,
S_AXI_HP0_RCOUNT,
S_AXI_HP0_WCOUNT,
S_AXI_HP0_RACOUNT,
S_AXI_HP0_WACOUNT,
S_AXI_HP0_ACLK,
S_AXI_HP0_ARVALID,
S_AXI_HP0_AWVALID,
S_AXI_HP0_BREADY,
S_AXI_HP0_RDISSUECAP1_EN,
S_AXI_HP0_RREADY,
S_AXI_HP0_WLAST,
S_AXI_HP0_WRISSUECAP1_EN,
S_AXI_HP0_WVALID,
S_AXI_HP0_ARBURST,
S_AXI_HP0_ARLOCK,
S_AXI_HP0_ARSIZE,
S_AXI_HP0_AWBURST,
S_AXI_HP0_AWLOCK,
S_AXI_HP0_AWSIZE,
S_AXI_HP0_ARPROT,
S_AXI_HP0_AWPROT,
S_AXI_HP0_ARADDR,
S_AXI_HP0_AWADDR,
S_AXI_HP0_ARCACHE,
S_AXI_HP0_ARLEN,
S_AXI_HP0_ARQOS,
S_AXI_HP0_AWCACHE,
S_AXI_HP0_AWLEN,
S_AXI_HP0_AWQOS,
S_AXI_HP0_ARID,
S_AXI_HP0_AWID,
S_AXI_HP0_WID,
S_AXI_HP0_WDATA,
S_AXI_HP0_WSTRB,
S_AXI_HP1_ARESETN,
S_AXI_HP1_ARREADY,
S_AXI_HP1_AWREADY,
S_AXI_HP1_BVALID,
S_AXI_HP1_RLAST,
S_AXI_HP1_RVALID,
S_AXI_HP1_WREADY,
S_AXI_HP1_BRESP,
S_AXI_HP1_RRESP,
S_AXI_HP1_BID,
S_AXI_HP1_RID,
S_AXI_HP1_RDATA,
S_AXI_HP1_RCOUNT,
S_AXI_HP1_WCOUNT,
S_AXI_HP1_RACOUNT,
S_AXI_HP1_WACOUNT,
S_AXI_HP1_ACLK,
S_AXI_HP1_ARVALID,
S_AXI_HP1_AWVALID,
S_AXI_HP1_BREADY,
S_AXI_HP1_RDISSUECAP1_EN,
S_AXI_HP1_RREADY,
S_AXI_HP1_WLAST,
S_AXI_HP1_WRISSUECAP1_EN,
S_AXI_HP1_WVALID,
S_AXI_HP1_ARBURST,
S_AXI_HP1_ARLOCK,
S_AXI_HP1_ARSIZE,
S_AXI_HP1_AWBURST,
S_AXI_HP1_AWLOCK,
S_AXI_HP1_AWSIZE,
S_AXI_HP1_ARPROT,
S_AXI_HP1_AWPROT,
S_AXI_HP1_ARADDR,
S_AXI_HP1_AWADDR,
S_AXI_HP1_ARCACHE,
S_AXI_HP1_ARLEN,
S_AXI_HP1_ARQOS,
S_AXI_HP1_AWCACHE,
S_AXI_HP1_AWLEN,
S_AXI_HP1_AWQOS,
S_AXI_HP1_ARID,
S_AXI_HP1_AWID,
S_AXI_HP1_WID,
S_AXI_HP1_WDATA,
S_AXI_HP1_WSTRB,
S_AXI_HP2_ARESETN,
S_AXI_HP2_ARREADY,
S_AXI_HP2_AWREADY,
S_AXI_HP2_BVALID,
S_AXI_HP2_RLAST,
S_AXI_HP2_RVALID,
S_AXI_HP2_WREADY,
S_AXI_HP2_BRESP,
S_AXI_HP2_RRESP,
S_AXI_HP2_BID,
S_AXI_HP2_RID,
S_AXI_HP2_RDATA,
S_AXI_HP2_RCOUNT,
S_AXI_HP2_WCOUNT,
S_AXI_HP2_RACOUNT,
S_AXI_HP2_WACOUNT,
S_AXI_HP2_ACLK,
S_AXI_HP2_ARVALID,
S_AXI_HP2_AWVALID,
S_AXI_HP2_BREADY,
S_AXI_HP2_RDISSUECAP1_EN,
S_AXI_HP2_RREADY,
S_AXI_HP2_WLAST,
S_AXI_HP2_WRISSUECAP1_EN,
S_AXI_HP2_WVALID,
S_AXI_HP2_ARBURST,
S_AXI_HP2_ARLOCK,
S_AXI_HP2_ARSIZE,
S_AXI_HP2_AWBURST,
S_AXI_HP2_AWLOCK,
S_AXI_HP2_AWSIZE,
S_AXI_HP2_ARPROT,
S_AXI_HP2_AWPROT,
S_AXI_HP2_ARADDR,
S_AXI_HP2_AWADDR,
S_AXI_HP2_ARCACHE,
S_AXI_HP2_ARLEN,
S_AXI_HP2_ARQOS,
S_AXI_HP2_AWCACHE,
S_AXI_HP2_AWLEN,
S_AXI_HP2_AWQOS,
S_AXI_HP2_ARID,
S_AXI_HP2_AWID,
S_AXI_HP2_WID,
S_AXI_HP2_WDATA,
S_AXI_HP2_WSTRB,
S_AXI_HP3_ARESETN,
S_AXI_HP3_ARREADY,
S_AXI_HP3_AWREADY,
S_AXI_HP3_BVALID,
S_AXI_HP3_RLAST,
S_AXI_HP3_RVALID,
S_AXI_HP3_WREADY,
S_AXI_HP3_BRESP,
S_AXI_HP3_RRESP,
S_AXI_HP3_BID,
S_AXI_HP3_RID,
S_AXI_HP3_RDATA,
S_AXI_HP3_RCOUNT,
S_AXI_HP3_WCOUNT,
S_AXI_HP3_RACOUNT,
S_AXI_HP3_WACOUNT,
S_AXI_HP3_ACLK,
S_AXI_HP3_ARVALID,
S_AXI_HP3_AWVALID,
S_AXI_HP3_BREADY,
S_AXI_HP3_RDISSUECAP1_EN,
S_AXI_HP3_RREADY,
S_AXI_HP3_WLAST,
S_AXI_HP3_WRISSUECAP1_EN,
S_AXI_HP3_WVALID,
S_AXI_HP3_ARBURST,
S_AXI_HP3_ARLOCK,
S_AXI_HP3_ARSIZE,
S_AXI_HP3_AWBURST,
S_AXI_HP3_AWLOCK,
S_AXI_HP3_AWSIZE,
S_AXI_HP3_ARPROT,
S_AXI_HP3_AWPROT,
S_AXI_HP3_ARADDR,
S_AXI_HP3_AWADDR,
S_AXI_HP3_ARCACHE,
S_AXI_HP3_ARLEN,
S_AXI_HP3_ARQOS,
S_AXI_HP3_AWCACHE,
S_AXI_HP3_AWLEN,
S_AXI_HP3_AWQOS,
S_AXI_HP3_ARID,
S_AXI_HP3_AWID,
S_AXI_HP3_WID,
S_AXI_HP3_WDATA,
S_AXI_HP3_WSTRB,
IRQ_P2F_DMAC_ABORT,
IRQ_P2F_DMAC0,
IRQ_P2F_DMAC1,
IRQ_P2F_DMAC2,
IRQ_P2F_DMAC3,
IRQ_P2F_DMAC4,
IRQ_P2F_DMAC5,
IRQ_P2F_DMAC6,
IRQ_P2F_DMAC7,
IRQ_P2F_SMC,
IRQ_P2F_QSPI,
IRQ_P2F_CTI,
IRQ_P2F_GPIO,
IRQ_P2F_USB0,
IRQ_P2F_ENET0,
IRQ_P2F_ENET_WAKE0,
IRQ_P2F_SDIO0,
IRQ_P2F_I2C0,
IRQ_P2F_SPI0,
IRQ_P2F_UART0,
IRQ_P2F_CAN0,
IRQ_P2F_USB1,
IRQ_P2F_ENET1,
IRQ_P2F_ENET_WAKE1,
IRQ_P2F_SDIO1,
IRQ_P2F_I2C1,
IRQ_P2F_SPI1,
IRQ_P2F_UART1,
IRQ_P2F_CAN1,
IRQ_F2P,
Core0_nFIQ,
Core0_nIRQ,
Core1_nFIQ,
Core1_nIRQ,
DMA0_DATYPE,
DMA0_DAVALID,
DMA0_DRREADY,
DMA0_RSTN,
DMA1_DATYPE,
DMA1_DAVALID,
DMA1_DRREADY,
DMA1_RSTN,
DMA2_DATYPE,
DMA2_DAVALID,
DMA2_DRREADY,
DMA2_RSTN,
DMA3_DATYPE,
DMA3_DAVALID,
DMA3_DRREADY,
DMA3_RSTN,
DMA0_ACLK,
DMA0_DAREADY,
DMA0_DRLAST,
DMA0_DRVALID,
DMA1_ACLK,
DMA1_DAREADY,
DMA1_DRLAST,
DMA1_DRVALID,
DMA2_ACLK,
DMA2_DAREADY,
DMA2_DRLAST,
DMA2_DRVALID,
DMA3_ACLK,
DMA3_DAREADY,
DMA3_DRLAST,
DMA3_DRVALID,
DMA0_DRTYPE,
DMA1_DRTYPE,
DMA2_DRTYPE,
DMA3_DRTYPE,
FCLK_CLK3,
FCLK_CLK2,
FCLK_CLK1,
FCLK_CLK0,
FCLK_CLKTRIG3_N,
FCLK_CLKTRIG2_N,
FCLK_CLKTRIG1_N,
FCLK_CLKTRIG0_N,
FCLK_RESET3_N,
FCLK_RESET2_N,
FCLK_RESET1_N,
FCLK_RESET0_N,
FTMD_TRACEIN_DATA,
FTMD_TRACEIN_VALID,
FTMD_TRACEIN_CLK,
FTMD_TRACEIN_ATID,
FTMT_F2P_TRIG_0,
FTMT_F2P_TRIGACK_0,
FTMT_F2P_TRIG_1,
FTMT_F2P_TRIGACK_1,
FTMT_F2P_TRIG_2,
FTMT_F2P_TRIGACK_2,
FTMT_F2P_TRIG_3,
FTMT_F2P_TRIGACK_3,
FTMT_F2P_DEBUG,
FTMT_P2F_TRIGACK_0,
FTMT_P2F_TRIG_0,
FTMT_P2F_TRIGACK_1,
FTMT_P2F_TRIG_1,
FTMT_P2F_TRIGACK_2,
FTMT_P2F_TRIG_2,
FTMT_P2F_TRIGACK_3,
FTMT_P2F_TRIG_3,
FTMT_P2F_DEBUG,
FPGA_IDLE_N,
EVENT_EVENTO,
EVENT_STANDBYWFE,
EVENT_STANDBYWFI,
EVENT_EVENTI,
DDR_ARB,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB);
output CAN0_PHY_TX;
input CAN0_PHY_RX;
output CAN1_PHY_TX;
input CAN1_PHY_RX;
output ENET0_GMII_TX_EN;
output ENET0_GMII_TX_ER;
output ENET0_MDIO_MDC;
output ENET0_MDIO_O;
output ENET0_MDIO_T;
output ENET0_PTP_DELAY_REQ_RX;
output ENET0_PTP_DELAY_REQ_TX;
output ENET0_PTP_PDELAY_REQ_RX;
output ENET0_PTP_PDELAY_REQ_TX;
output ENET0_PTP_PDELAY_RESP_RX;
output ENET0_PTP_PDELAY_RESP_TX;
output ENET0_PTP_SYNC_FRAME_RX;
output ENET0_PTP_SYNC_FRAME_TX;
output ENET0_SOF_RX;
output ENET0_SOF_TX;
output [7:0]ENET0_GMII_TXD;
input ENET0_GMII_COL;
input ENET0_GMII_CRS;
input ENET0_GMII_RX_CLK;
input ENET0_GMII_RX_DV;
input ENET0_GMII_RX_ER;
input ENET0_GMII_TX_CLK;
input ENET0_MDIO_I;
input ENET0_EXT_INTIN;
input [7:0]ENET0_GMII_RXD;
output ENET1_GMII_TX_EN;
output ENET1_GMII_TX_ER;
output ENET1_MDIO_MDC;
output ENET1_MDIO_O;
output ENET1_MDIO_T;
output ENET1_PTP_DELAY_REQ_RX;
output ENET1_PTP_DELAY_REQ_TX;
output ENET1_PTP_PDELAY_REQ_RX;
output ENET1_PTP_PDELAY_REQ_TX;
output ENET1_PTP_PDELAY_RESP_RX;
output ENET1_PTP_PDELAY_RESP_TX;
output ENET1_PTP_SYNC_FRAME_RX;
output ENET1_PTP_SYNC_FRAME_TX;
output ENET1_SOF_RX;
output ENET1_SOF_TX;
output [7:0]ENET1_GMII_TXD;
input ENET1_GMII_COL;
input ENET1_GMII_CRS;
input ENET1_GMII_RX_CLK;
input ENET1_GMII_RX_DV;
input ENET1_GMII_RX_ER;
input ENET1_GMII_TX_CLK;
input ENET1_MDIO_I;
input ENET1_EXT_INTIN;
input [7:0]ENET1_GMII_RXD;
input [63:0]GPIO_I;
output [63:0]GPIO_O;
output [63:0]GPIO_T;
input I2C0_SDA_I;
output I2C0_SDA_O;
output I2C0_SDA_T;
input I2C0_SCL_I;
output I2C0_SCL_O;
output I2C0_SCL_T;
input I2C1_SDA_I;
output I2C1_SDA_O;
output I2C1_SDA_T;
input I2C1_SCL_I;
output I2C1_SCL_O;
output I2C1_SCL_T;
input PJTAG_TCK;
input PJTAG_TMS;
input PJTAG_TDI;
output PJTAG_TDO;
output SDIO0_CLK;
input SDIO0_CLK_FB;
output SDIO0_CMD_O;
input SDIO0_CMD_I;
output SDIO0_CMD_T;
input [3:0]SDIO0_DATA_I;
output [3:0]SDIO0_DATA_O;
output [3:0]SDIO0_DATA_T;
output SDIO0_LED;
input SDIO0_CDN;
input SDIO0_WP;
output SDIO0_BUSPOW;
output [2:0]SDIO0_BUSVOLT;
output SDIO1_CLK;
input SDIO1_CLK_FB;
output SDIO1_CMD_O;
input SDIO1_CMD_I;
output SDIO1_CMD_T;
input [3:0]SDIO1_DATA_I;
output [3:0]SDIO1_DATA_O;
output [3:0]SDIO1_DATA_T;
output SDIO1_LED;
input SDIO1_CDN;
input SDIO1_WP;
output SDIO1_BUSPOW;
output [2:0]SDIO1_BUSVOLT;
input SPI0_SCLK_I;
output SPI0_SCLK_O;
output SPI0_SCLK_T;
input SPI0_MOSI_I;
output SPI0_MOSI_O;
output SPI0_MOSI_T;
input SPI0_MISO_I;
output SPI0_MISO_O;
output SPI0_MISO_T;
input SPI0_SS_I;
output SPI0_SS_O;
output SPI0_SS1_O;
output SPI0_SS2_O;
output SPI0_SS_T;
input SPI1_SCLK_I;
output SPI1_SCLK_O;
output SPI1_SCLK_T;
input SPI1_MOSI_I;
output SPI1_MOSI_O;
output SPI1_MOSI_T;
input SPI1_MISO_I;
output SPI1_MISO_O;
output SPI1_MISO_T;
input SPI1_SS_I;
output SPI1_SS_O;
output SPI1_SS1_O;
output SPI1_SS2_O;
output SPI1_SS_T;
output UART0_DTRN;
output UART0_RTSN;
output UART0_TX;
input UART0_CTSN;
input UART0_DCDN;
input UART0_DSRN;
input UART0_RIN;
input UART0_RX;
output UART1_DTRN;
output UART1_RTSN;
output UART1_TX;
input UART1_CTSN;
input UART1_DCDN;
input UART1_DSRN;
input UART1_RIN;
input UART1_RX;
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
input TTC0_CLK0_IN;
input TTC0_CLK1_IN;
input TTC0_CLK2_IN;
output TTC1_WAVE0_OUT;
output TTC1_WAVE1_OUT;
output TTC1_WAVE2_OUT;
input TTC1_CLK0_IN;
input TTC1_CLK1_IN;
input TTC1_CLK2_IN;
input WDT_CLK_IN;
output WDT_RST_OUT;
input TRACE_CLK;
output TRACE_CTL;
output [1:0]TRACE_DATA;
output TRACE_CLK_OUT;
output [1:0]USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output [1:0]USB1_PORT_INDCTL;
output USB1_VBUS_PWRSELECT;
input USB1_VBUS_PWRFAULT;
input SRAM_INTIN;
output M_AXI_GP0_ARESETN;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11:0]M_AXI_GP0_ARID;
output [11:0]M_AXI_GP0_AWID;
output [11:0]M_AXI_GP0_WID;
output [1:0]M_AXI_GP0_ARBURST;
output [1:0]M_AXI_GP0_ARLOCK;
output [2:0]M_AXI_GP0_ARSIZE;
output [1:0]M_AXI_GP0_AWBURST;
output [1:0]M_AXI_GP0_AWLOCK;
output [2:0]M_AXI_GP0_AWSIZE;
output [2:0]M_AXI_GP0_ARPROT;
output [2:0]M_AXI_GP0_AWPROT;
output [31:0]M_AXI_GP0_ARADDR;
output [31:0]M_AXI_GP0_AWADDR;
output [31:0]M_AXI_GP0_WDATA;
output [3:0]M_AXI_GP0_ARCACHE;
output [3:0]M_AXI_GP0_ARLEN;
output [3:0]M_AXI_GP0_ARQOS;
output [3:0]M_AXI_GP0_AWCACHE;
output [3:0]M_AXI_GP0_AWLEN;
output [3:0]M_AXI_GP0_AWQOS;
output [3:0]M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11:0]M_AXI_GP0_BID;
input [11:0]M_AXI_GP0_RID;
input [1:0]M_AXI_GP0_BRESP;
input [1:0]M_AXI_GP0_RRESP;
input [31:0]M_AXI_GP0_RDATA;
output M_AXI_GP1_ARESETN;
output M_AXI_GP1_ARVALID;
output M_AXI_GP1_AWVALID;
output M_AXI_GP1_BREADY;
output M_AXI_GP1_RREADY;
output M_AXI_GP1_WLAST;
output M_AXI_GP1_WVALID;
output [11:0]M_AXI_GP1_ARID;
output [11:0]M_AXI_GP1_AWID;
output [11:0]M_AXI_GP1_WID;
output [1:0]M_AXI_GP1_ARBURST;
output [1:0]M_AXI_GP1_ARLOCK;
output [2:0]M_AXI_GP1_ARSIZE;
output [1:0]M_AXI_GP1_AWBURST;
output [1:0]M_AXI_GP1_AWLOCK;
output [2:0]M_AXI_GP1_AWSIZE;
output [2:0]M_AXI_GP1_ARPROT;
output [2:0]M_AXI_GP1_AWPROT;
output [31:0]M_AXI_GP1_ARADDR;
output [31:0]M_AXI_GP1_AWADDR;
output [31:0]M_AXI_GP1_WDATA;
output [3:0]M_AXI_GP1_ARCACHE;
output [3:0]M_AXI_GP1_ARLEN;
output [3:0]M_AXI_GP1_ARQOS;
output [3:0]M_AXI_GP1_AWCACHE;
output [3:0]M_AXI_GP1_AWLEN;
output [3:0]M_AXI_GP1_AWQOS;
output [3:0]M_AXI_GP1_WSTRB;
input M_AXI_GP1_ACLK;
input M_AXI_GP1_ARREADY;
input M_AXI_GP1_AWREADY;
input M_AXI_GP1_BVALID;
input M_AXI_GP1_RLAST;
input M_AXI_GP1_RVALID;
input M_AXI_GP1_WREADY;
input [11:0]M_AXI_GP1_BID;
input [11:0]M_AXI_GP1_RID;
input [1:0]M_AXI_GP1_BRESP;
input [1:0]M_AXI_GP1_RRESP;
input [31:0]M_AXI_GP1_RDATA;
output S_AXI_GP0_ARESETN;
output S_AXI_GP0_ARREADY;
output S_AXI_GP0_AWREADY;
output S_AXI_GP0_BVALID;
output S_AXI_GP0_RLAST;
output S_AXI_GP0_RVALID;
output S_AXI_GP0_WREADY;
output [1:0]S_AXI_GP0_BRESP;
output [1:0]S_AXI_GP0_RRESP;
output [31:0]S_AXI_GP0_RDATA;
output [5:0]S_AXI_GP0_BID;
output [5:0]S_AXI_GP0_RID;
input S_AXI_GP0_ACLK;
input S_AXI_GP0_ARVALID;
input S_AXI_GP0_AWVALID;
input S_AXI_GP0_BREADY;
input S_AXI_GP0_RREADY;
input S_AXI_GP0_WLAST;
input S_AXI_GP0_WVALID;
input [1:0]S_AXI_GP0_ARBURST;
input [1:0]S_AXI_GP0_ARLOCK;
input [2:0]S_AXI_GP0_ARSIZE;
input [1:0]S_AXI_GP0_AWBURST;
input [1:0]S_AXI_GP0_AWLOCK;
input [2:0]S_AXI_GP0_AWSIZE;
input [2:0]S_AXI_GP0_ARPROT;
input [2:0]S_AXI_GP0_AWPROT;
input [31:0]S_AXI_GP0_ARADDR;
input [31:0]S_AXI_GP0_AWADDR;
input [31:0]S_AXI_GP0_WDATA;
input [3:0]S_AXI_GP0_ARCACHE;
input [3:0]S_AXI_GP0_ARLEN;
input [3:0]S_AXI_GP0_ARQOS;
input [3:0]S_AXI_GP0_AWCACHE;
input [3:0]S_AXI_GP0_AWLEN;
input [3:0]S_AXI_GP0_AWQOS;
input [3:0]S_AXI_GP0_WSTRB;
input [5:0]S_AXI_GP0_ARID;
input [5:0]S_AXI_GP0_AWID;
input [5:0]S_AXI_GP0_WID;
output S_AXI_GP1_ARESETN;
output S_AXI_GP1_ARREADY;
output S_AXI_GP1_AWREADY;
output S_AXI_GP1_BVALID;
output S_AXI_GP1_RLAST;
output S_AXI_GP1_RVALID;
output S_AXI_GP1_WREADY;
output [1:0]S_AXI_GP1_BRESP;
output [1:0]S_AXI_GP1_RRESP;
output [31:0]S_AXI_GP1_RDATA;
output [5:0]S_AXI_GP1_BID;
output [5:0]S_AXI_GP1_RID;
input S_AXI_GP1_ACLK;
input S_AXI_GP1_ARVALID;
input S_AXI_GP1_AWVALID;
input S_AXI_GP1_BREADY;
input S_AXI_GP1_RREADY;
input S_AXI_GP1_WLAST;
input S_AXI_GP1_WVALID;
input [1:0]S_AXI_GP1_ARBURST;
input [1:0]S_AXI_GP1_ARLOCK;
input [2:0]S_AXI_GP1_ARSIZE;
input [1:0]S_AXI_GP1_AWBURST;
input [1:0]S_AXI_GP1_AWLOCK;
input [2:0]S_AXI_GP1_AWSIZE;
input [2:0]S_AXI_GP1_ARPROT;
input [2:0]S_AXI_GP1_AWPROT;
input [31:0]S_AXI_GP1_ARADDR;
input [31:0]S_AXI_GP1_AWADDR;
input [31:0]S_AXI_GP1_WDATA;
input [3:0]S_AXI_GP1_ARCACHE;
input [3:0]S_AXI_GP1_ARLEN;
input [3:0]S_AXI_GP1_ARQOS;
input [3:0]S_AXI_GP1_AWCACHE;
input [3:0]S_AXI_GP1_AWLEN;
input [3:0]S_AXI_GP1_AWQOS;
input [3:0]S_AXI_GP1_WSTRB;
input [5:0]S_AXI_GP1_ARID;
input [5:0]S_AXI_GP1_AWID;
input [5:0]S_AXI_GP1_WID;
output S_AXI_ACP_ARESETN;
output S_AXI_ACP_ARREADY;
output S_AXI_ACP_AWREADY;
output S_AXI_ACP_BVALID;
output S_AXI_ACP_RLAST;
output S_AXI_ACP_RVALID;
output S_AXI_ACP_WREADY;
output [1:0]S_AXI_ACP_BRESP;
output [1:0]S_AXI_ACP_RRESP;
output [2:0]S_AXI_ACP_BID;
output [2:0]S_AXI_ACP_RID;
output [63:0]S_AXI_ACP_RDATA;
input S_AXI_ACP_ACLK;
input S_AXI_ACP_ARVALID;
input S_AXI_ACP_AWVALID;
input S_AXI_ACP_BREADY;
input S_AXI_ACP_RREADY;
input S_AXI_ACP_WLAST;
input S_AXI_ACP_WVALID;
input [2:0]S_AXI_ACP_ARID;
input [2:0]S_AXI_ACP_ARPROT;
input [2:0]S_AXI_ACP_AWID;
input [2:0]S_AXI_ACP_AWPROT;
input [2:0]S_AXI_ACP_WID;
input [31:0]S_AXI_ACP_ARADDR;
input [31:0]S_AXI_ACP_AWADDR;
input [3:0]S_AXI_ACP_ARCACHE;
input [3:0]S_AXI_ACP_ARLEN;
input [3:0]S_AXI_ACP_ARQOS;
input [3:0]S_AXI_ACP_AWCACHE;
input [3:0]S_AXI_ACP_AWLEN;
input [3:0]S_AXI_ACP_AWQOS;
input [1:0]S_AXI_ACP_ARBURST;
input [1:0]S_AXI_ACP_ARLOCK;
input [2:0]S_AXI_ACP_ARSIZE;
input [1:0]S_AXI_ACP_AWBURST;
input [1:0]S_AXI_ACP_AWLOCK;
input [2:0]S_AXI_ACP_AWSIZE;
input [4:0]S_AXI_ACP_ARUSER;
input [4:0]S_AXI_ACP_AWUSER;
input [63:0]S_AXI_ACP_WDATA;
input [7:0]S_AXI_ACP_WSTRB;
output S_AXI_HP0_ARESETN;
output S_AXI_HP0_ARREADY;
output S_AXI_HP0_AWREADY;
output S_AXI_HP0_BVALID;
output S_AXI_HP0_RLAST;
output S_AXI_HP0_RVALID;
output S_AXI_HP0_WREADY;
output [1:0]S_AXI_HP0_BRESP;
output [1:0]S_AXI_HP0_RRESP;
output [5:0]S_AXI_HP0_BID;
output [5:0]S_AXI_HP0_RID;
output [63:0]S_AXI_HP0_RDATA;
output [7:0]S_AXI_HP0_RCOUNT;
output [7:0]S_AXI_HP0_WCOUNT;
output [2:0]S_AXI_HP0_RACOUNT;
output [5:0]S_AXI_HP0_WACOUNT;
input S_AXI_HP0_ACLK;
input S_AXI_HP0_ARVALID;
input S_AXI_HP0_AWVALID;
input S_AXI_HP0_BREADY;
input S_AXI_HP0_RDISSUECAP1_EN;
input S_AXI_HP0_RREADY;
input S_AXI_HP0_WLAST;
input S_AXI_HP0_WRISSUECAP1_EN;
input S_AXI_HP0_WVALID;
input [1:0]S_AXI_HP0_ARBURST;
input [1:0]S_AXI_HP0_ARLOCK;
input [2:0]S_AXI_HP0_ARSIZE;
input [1:0]S_AXI_HP0_AWBURST;
input [1:0]S_AXI_HP0_AWLOCK;
input [2:0]S_AXI_HP0_AWSIZE;
input [2:0]S_AXI_HP0_ARPROT;
input [2:0]S_AXI_HP0_AWPROT;
input [31:0]S_AXI_HP0_ARADDR;
input [31:0]S_AXI_HP0_AWADDR;
input [3:0]S_AXI_HP0_ARCACHE;
input [3:0]S_AXI_HP0_ARLEN;
input [3:0]S_AXI_HP0_ARQOS;
input [3:0]S_AXI_HP0_AWCACHE;
input [3:0]S_AXI_HP0_AWLEN;
input [3:0]S_AXI_HP0_AWQOS;
input [5:0]S_AXI_HP0_ARID;
input [5:0]S_AXI_HP0_AWID;
input [5:0]S_AXI_HP0_WID;
input [63:0]S_AXI_HP0_WDATA;
input [7:0]S_AXI_HP0_WSTRB;
output S_AXI_HP1_ARESETN;
output S_AXI_HP1_ARREADY;
output S_AXI_HP1_AWREADY;
output S_AXI_HP1_BVALID;
output S_AXI_HP1_RLAST;
output S_AXI_HP1_RVALID;
output S_AXI_HP1_WREADY;
output [1:0]S_AXI_HP1_BRESP;
output [1:0]S_AXI_HP1_RRESP;
output [5:0]S_AXI_HP1_BID;
output [5:0]S_AXI_HP1_RID;
output [63:0]S_AXI_HP1_RDATA;
output [7:0]S_AXI_HP1_RCOUNT;
output [7:0]S_AXI_HP1_WCOUNT;
output [2:0]S_AXI_HP1_RACOUNT;
output [5:0]S_AXI_HP1_WACOUNT;
input S_AXI_HP1_ACLK;
input S_AXI_HP1_ARVALID;
input S_AXI_HP1_AWVALID;
input S_AXI_HP1_BREADY;
input S_AXI_HP1_RDISSUECAP1_EN;
input S_AXI_HP1_RREADY;
input S_AXI_HP1_WLAST;
input S_AXI_HP1_WRISSUECAP1_EN;
input S_AXI_HP1_WVALID;
input [1:0]S_AXI_HP1_ARBURST;
input [1:0]S_AXI_HP1_ARLOCK;
input [2:0]S_AXI_HP1_ARSIZE;
input [1:0]S_AXI_HP1_AWBURST;
input [1:0]S_AXI_HP1_AWLOCK;
input [2:0]S_AXI_HP1_AWSIZE;
input [2:0]S_AXI_HP1_ARPROT;
input [2:0]S_AXI_HP1_AWPROT;
input [31:0]S_AXI_HP1_ARADDR;
input [31:0]S_AXI_HP1_AWADDR;
input [3:0]S_AXI_HP1_ARCACHE;
input [3:0]S_AXI_HP1_ARLEN;
input [3:0]S_AXI_HP1_ARQOS;
input [3:0]S_AXI_HP1_AWCACHE;
input [3:0]S_AXI_HP1_AWLEN;
input [3:0]S_AXI_HP1_AWQOS;
input [5:0]S_AXI_HP1_ARID;
input [5:0]S_AXI_HP1_AWID;
input [5:0]S_AXI_HP1_WID;
input [63:0]S_AXI_HP1_WDATA;
input [7:0]S_AXI_HP1_WSTRB;
output S_AXI_HP2_ARESETN;
output S_AXI_HP2_ARREADY;
output S_AXI_HP2_AWREADY;
output S_AXI_HP2_BVALID;
output S_AXI_HP2_RLAST;
output S_AXI_HP2_RVALID;
output S_AXI_HP2_WREADY;
output [1:0]S_AXI_HP2_BRESP;
output [1:0]S_AXI_HP2_RRESP;
output [5:0]S_AXI_HP2_BID;
output [5:0]S_AXI_HP2_RID;
output [63:0]S_AXI_HP2_RDATA;
output [7:0]S_AXI_HP2_RCOUNT;
output [7:0]S_AXI_HP2_WCOUNT;
output [2:0]S_AXI_HP2_RACOUNT;
output [5:0]S_AXI_HP2_WACOUNT;
input S_AXI_HP2_ACLK;
input S_AXI_HP2_ARVALID;
input S_AXI_HP2_AWVALID;
input S_AXI_HP2_BREADY;
input S_AXI_HP2_RDISSUECAP1_EN;
input S_AXI_HP2_RREADY;
input S_AXI_HP2_WLAST;
input S_AXI_HP2_WRISSUECAP1_EN;
input S_AXI_HP2_WVALID;
input [1:0]S_AXI_HP2_ARBURST;
input [1:0]S_AXI_HP2_ARLOCK;
input [2:0]S_AXI_HP2_ARSIZE;
input [1:0]S_AXI_HP2_AWBURST;
input [1:0]S_AXI_HP2_AWLOCK;
input [2:0]S_AXI_HP2_AWSIZE;
input [2:0]S_AXI_HP2_ARPROT;
input [2:0]S_AXI_HP2_AWPROT;
input [31:0]S_AXI_HP2_ARADDR;
input [31:0]S_AXI_HP2_AWADDR;
input [3:0]S_AXI_HP2_ARCACHE;
input [3:0]S_AXI_HP2_ARLEN;
input [3:0]S_AXI_HP2_ARQOS;
input [3:0]S_AXI_HP2_AWCACHE;
input [3:0]S_AXI_HP2_AWLEN;
input [3:0]S_AXI_HP2_AWQOS;
input [5:0]S_AXI_HP2_ARID;
input [5:0]S_AXI_HP2_AWID;
input [5:0]S_AXI_HP2_WID;
input [63:0]S_AXI_HP2_WDATA;
input [7:0]S_AXI_HP2_WSTRB;
output S_AXI_HP3_ARESETN;
output S_AXI_HP3_ARREADY;
output S_AXI_HP3_AWREADY;
output S_AXI_HP3_BVALID;
output S_AXI_HP3_RLAST;
output S_AXI_HP3_RVALID;
output S_AXI_HP3_WREADY;
output [1:0]S_AXI_HP3_BRESP;
output [1:0]S_AXI_HP3_RRESP;
output [5:0]S_AXI_HP3_BID;
output [5:0]S_AXI_HP3_RID;
output [63:0]S_AXI_HP3_RDATA;
output [7:0]S_AXI_HP3_RCOUNT;
output [7:0]S_AXI_HP3_WCOUNT;
output [2:0]S_AXI_HP3_RACOUNT;
output [5:0]S_AXI_HP3_WACOUNT;
input S_AXI_HP3_ACLK;
input S_AXI_HP3_ARVALID;
input S_AXI_HP3_AWVALID;
input S_AXI_HP3_BREADY;
input S_AXI_HP3_RDISSUECAP1_EN;
input S_AXI_HP3_RREADY;
input S_AXI_HP3_WLAST;
input S_AXI_HP3_WRISSUECAP1_EN;
input S_AXI_HP3_WVALID;
input [1:0]S_AXI_HP3_ARBURST;
input [1:0]S_AXI_HP3_ARLOCK;
input [2:0]S_AXI_HP3_ARSIZE;
input [1:0]S_AXI_HP3_AWBURST;
input [1:0]S_AXI_HP3_AWLOCK;
input [2:0]S_AXI_HP3_AWSIZE;
input [2:0]S_AXI_HP3_ARPROT;
input [2:0]S_AXI_HP3_AWPROT;
input [31:0]S_AXI_HP3_ARADDR;
input [31:0]S_AXI_HP3_AWADDR;
input [3:0]S_AXI_HP3_ARCACHE;
input [3:0]S_AXI_HP3_ARLEN;
input [3:0]S_AXI_HP3_ARQOS;
input [3:0]S_AXI_HP3_AWCACHE;
input [3:0]S_AXI_HP3_AWLEN;
input [3:0]S_AXI_HP3_AWQOS;
input [5:0]S_AXI_HP3_ARID;
input [5:0]S_AXI_HP3_AWID;
input [5:0]S_AXI_HP3_WID;
input [63:0]S_AXI_HP3_WDATA;
input [7:0]S_AXI_HP3_WSTRB;
output IRQ_P2F_DMAC_ABORT;
output IRQ_P2F_DMAC0;
output IRQ_P2F_DMAC1;
output IRQ_P2F_DMAC2;
output IRQ_P2F_DMAC3;
output IRQ_P2F_DMAC4;
output IRQ_P2F_DMAC5;
output IRQ_P2F_DMAC6;
output IRQ_P2F_DMAC7;
output IRQ_P2F_SMC;
output IRQ_P2F_QSPI;
output IRQ_P2F_CTI;
output IRQ_P2F_GPIO;
output IRQ_P2F_USB0;
output IRQ_P2F_ENET0;
output IRQ_P2F_ENET_WAKE0;
output IRQ_P2F_SDIO0;
output IRQ_P2F_I2C0;
output IRQ_P2F_SPI0;
output IRQ_P2F_UART0;
output IRQ_P2F_CAN0;
output IRQ_P2F_USB1;
output IRQ_P2F_ENET1;
output IRQ_P2F_ENET_WAKE1;
output IRQ_P2F_SDIO1;
output IRQ_P2F_I2C1;
output IRQ_P2F_SPI1;
output IRQ_P2F_UART1;
output IRQ_P2F_CAN1;
input [0:0]IRQ_F2P;
input Core0_nFIQ;
input Core0_nIRQ;
input Core1_nFIQ;
input Core1_nIRQ;
output [1:0]DMA0_DATYPE;
output DMA0_DAVALID;
output DMA0_DRREADY;
output DMA0_RSTN;
output [1:0]DMA1_DATYPE;
output DMA1_DAVALID;
output DMA1_DRREADY;
output DMA1_RSTN;
output [1:0]DMA2_DATYPE;
output DMA2_DAVALID;
output DMA2_DRREADY;
output DMA2_RSTN;
output [1:0]DMA3_DATYPE;
output DMA3_DAVALID;
output DMA3_DRREADY;
output DMA3_RSTN;
input DMA0_ACLK;
input DMA0_DAREADY;
input DMA0_DRLAST;
input DMA0_DRVALID;
input DMA1_ACLK;
input DMA1_DAREADY;
input DMA1_DRLAST;
input DMA1_DRVALID;
input DMA2_ACLK;
input DMA2_DAREADY;
input DMA2_DRLAST;
input DMA2_DRVALID;
input DMA3_ACLK;
input DMA3_DAREADY;
input DMA3_DRLAST;
input DMA3_DRVALID;
input [1:0]DMA0_DRTYPE;
input [1:0]DMA1_DRTYPE;
input [1:0]DMA2_DRTYPE;
input [1:0]DMA3_DRTYPE;
output FCLK_CLK3;
output FCLK_CLK2;
output FCLK_CLK1;
output FCLK_CLK0;
input FCLK_CLKTRIG3_N;
input FCLK_CLKTRIG2_N;
input FCLK_CLKTRIG1_N;
input FCLK_CLKTRIG0_N;
output FCLK_RESET3_N;
output FCLK_RESET2_N;
output FCLK_RESET1_N;
output FCLK_RESET0_N;
input [31:0]FTMD_TRACEIN_DATA;
input FTMD_TRACEIN_VALID;
input FTMD_TRACEIN_CLK;
input [3:0]FTMD_TRACEIN_ATID;
input FTMT_F2P_TRIG_0;
output FTMT_F2P_TRIGACK_0;
input FTMT_F2P_TRIG_1;
output FTMT_F2P_TRIGACK_1;
input FTMT_F2P_TRIG_2;
output FTMT_F2P_TRIGACK_2;
input FTMT_F2P_TRIG_3;
output FTMT_F2P_TRIGACK_3;
input [31:0]FTMT_F2P_DEBUG;
input FTMT_P2F_TRIGACK_0;
output FTMT_P2F_TRIG_0;
input FTMT_P2F_TRIGACK_1;
output FTMT_P2F_TRIG_1;
input FTMT_P2F_TRIGACK_2;
output FTMT_P2F_TRIG_2;
input FTMT_P2F_TRIGACK_3;
output FTMT_P2F_TRIG_3;
output [31:0]FTMT_P2F_DEBUG;
input FPGA_IDLE_N;
output EVENT_EVENTO;
output [1:0]EVENT_STANDBYWFE;
output [1:0]EVENT_STANDBYWFI;
input EVENT_EVENTI;
input [3:0]DDR_ARB;
inout [53:0]MIO;
inout DDR_CAS_n;
inout DDR_CKE;
inout DDR_Clk_n;
inout DDR_Clk;
inout DDR_CS_n;
inout DDR_DRSTB;
inout DDR_ODT;
inout DDR_RAS_n;
inout DDR_WEB;
inout [2:0]DDR_BankAddr;
inout [14:0]DDR_Addr;
inout DDR_VRN;
inout DDR_VRP;
inout [3:0]DDR_DM;
inout [31:0]DDR_DQ;
inout [3:0]DDR_DQS_n;
inout [3:0]DDR_DQS;
inout PS_SRSTB;
inout PS_CLK;
inout PS_PORB;
wire \<const0> ;
wire \<const1> ;
wire CAN0_PHY_RX;
wire CAN0_PHY_TX;
wire CAN1_PHY_RX;
wire CAN1_PHY_TX;
wire Core0_nFIQ;
wire Core0_nIRQ;
wire Core1_nFIQ;
wire Core1_nIRQ;
wire [3:0]DDR_ARB;
wire [14:0]DDR_Addr;
wire [2:0]DDR_BankAddr;
wire DDR_CAS_n;
wire DDR_CKE;
wire DDR_CS_n;
wire DDR_Clk;
wire DDR_Clk_n;
wire [3:0]DDR_DM;
wire [31:0]DDR_DQ;
wire [3:0]DDR_DQS;
wire [3:0]DDR_DQS_n;
wire DDR_DRSTB;
wire DDR_ODT;
wire DDR_RAS_n;
wire DDR_VRN;
wire DDR_VRP;
wire DDR_WEB;
wire DMA0_ACLK;
wire DMA0_DAREADY;
wire [1:0]DMA0_DATYPE;
wire DMA0_DAVALID;
wire DMA0_DRLAST;
wire DMA0_DRREADY;
wire [1:0]DMA0_DRTYPE;
wire DMA0_DRVALID;
wire DMA0_RSTN;
wire DMA1_ACLK;
wire DMA1_DAREADY;
wire [1:0]DMA1_DATYPE;
wire DMA1_DAVALID;
wire DMA1_DRLAST;
wire DMA1_DRREADY;
wire [1:0]DMA1_DRTYPE;
wire DMA1_DRVALID;
wire DMA1_RSTN;
wire DMA2_ACLK;
wire DMA2_DAREADY;
wire [1:0]DMA2_DATYPE;
wire DMA2_DAVALID;
wire DMA2_DRLAST;
wire DMA2_DRREADY;
wire [1:0]DMA2_DRTYPE;
wire DMA2_DRVALID;
wire DMA2_RSTN;
wire DMA3_ACLK;
wire DMA3_DAREADY;
wire [1:0]DMA3_DATYPE;
wire DMA3_DAVALID;
wire DMA3_DRLAST;
wire DMA3_DRREADY;
wire [1:0]DMA3_DRTYPE;
wire DMA3_DRVALID;
wire DMA3_RSTN;
wire ENET0_EXT_INTIN;
wire ENET0_GMII_RX_CLK;
wire ENET0_GMII_TX_CLK;
wire ENET0_MDIO_I;
wire ENET0_MDIO_MDC;
wire ENET0_MDIO_O;
wire ENET0_MDIO_T;
wire ENET0_MDIO_T_n;
wire ENET0_PTP_DELAY_REQ_RX;
wire ENET0_PTP_DELAY_REQ_TX;
wire ENET0_PTP_PDELAY_REQ_RX;
wire ENET0_PTP_PDELAY_REQ_TX;
wire ENET0_PTP_PDELAY_RESP_RX;
wire ENET0_PTP_PDELAY_RESP_TX;
wire ENET0_PTP_SYNC_FRAME_RX;
wire ENET0_PTP_SYNC_FRAME_TX;
wire ENET0_SOF_RX;
wire ENET0_SOF_TX;
wire ENET1_EXT_INTIN;
wire ENET1_GMII_RX_CLK;
wire ENET1_GMII_TX_CLK;
wire ENET1_MDIO_I;
wire ENET1_MDIO_MDC;
wire ENET1_MDIO_O;
wire ENET1_MDIO_T;
wire ENET1_MDIO_T_n;
wire ENET1_PTP_DELAY_REQ_RX;
wire ENET1_PTP_DELAY_REQ_TX;
wire ENET1_PTP_PDELAY_REQ_RX;
wire ENET1_PTP_PDELAY_REQ_TX;
wire ENET1_PTP_PDELAY_RESP_RX;
wire ENET1_PTP_PDELAY_RESP_TX;
wire ENET1_PTP_SYNC_FRAME_RX;
wire ENET1_PTP_SYNC_FRAME_TX;
wire ENET1_SOF_RX;
wire ENET1_SOF_TX;
wire EVENT_EVENTI;
wire EVENT_EVENTO;
wire [1:0]EVENT_STANDBYWFE;
wire [1:0]EVENT_STANDBYWFI;
wire FCLK_CLK0;
wire FCLK_CLK1;
wire FCLK_CLK2;
wire FCLK_CLK3;
wire [0:0]FCLK_CLK_unbuffered;
wire FCLK_RESET0_N;
wire FCLK_RESET1_N;
wire FCLK_RESET2_N;
wire FCLK_RESET3_N;
wire FPGA_IDLE_N;
wire FTMD_TRACEIN_CLK;
wire [31:0]FTMT_F2P_DEBUG;
wire FTMT_F2P_TRIGACK_0;
wire FTMT_F2P_TRIGACK_1;
wire FTMT_F2P_TRIGACK_2;
wire FTMT_F2P_TRIGACK_3;
wire FTMT_F2P_TRIG_0;
wire FTMT_F2P_TRIG_1;
wire FTMT_F2P_TRIG_2;
wire FTMT_F2P_TRIG_3;
wire [31:0]FTMT_P2F_DEBUG;
wire FTMT_P2F_TRIGACK_0;
wire FTMT_P2F_TRIGACK_1;
wire FTMT_P2F_TRIGACK_2;
wire FTMT_P2F_TRIGACK_3;
wire FTMT_P2F_TRIG_0;
wire FTMT_P2F_TRIG_1;
wire FTMT_P2F_TRIG_2;
wire FTMT_P2F_TRIG_3;
wire [63:0]GPIO_I;
wire [63:0]GPIO_O;
wire [63:0]GPIO_T;
wire I2C0_SCL_I;
wire I2C0_SCL_O;
wire I2C0_SCL_T;
wire I2C0_SCL_T_n;
wire I2C0_SDA_I;
wire I2C0_SDA_O;
wire I2C0_SDA_T;
wire I2C0_SDA_T_n;
wire I2C1_SCL_I;
wire I2C1_SCL_O;
wire I2C1_SCL_T;
wire I2C1_SCL_T_n;
wire I2C1_SDA_I;
wire I2C1_SDA_O;
wire I2C1_SDA_T;
wire I2C1_SDA_T_n;
wire [0:0]IRQ_F2P;
wire IRQ_P2F_CAN0;
wire IRQ_P2F_CAN1;
wire IRQ_P2F_CTI;
wire IRQ_P2F_DMAC0;
wire IRQ_P2F_DMAC1;
wire IRQ_P2F_DMAC2;
wire IRQ_P2F_DMAC3;
wire IRQ_P2F_DMAC4;
wire IRQ_P2F_DMAC5;
wire IRQ_P2F_DMAC6;
wire IRQ_P2F_DMAC7;
wire IRQ_P2F_DMAC_ABORT;
wire IRQ_P2F_ENET0;
wire IRQ_P2F_ENET1;
wire IRQ_P2F_ENET_WAKE0;
wire IRQ_P2F_ENET_WAKE1;
wire IRQ_P2F_GPIO;
wire IRQ_P2F_I2C0;
wire IRQ_P2F_I2C1;
wire IRQ_P2F_QSPI;
wire IRQ_P2F_SDIO0;
wire IRQ_P2F_SDIO1;
wire IRQ_P2F_SMC;
wire IRQ_P2F_SPI0;
wire IRQ_P2F_SPI1;
wire IRQ_P2F_UART0;
wire IRQ_P2F_UART1;
wire IRQ_P2F_USB0;
wire IRQ_P2F_USB1;
wire [53:0]MIO;
wire M_AXI_GP0_ACLK;
wire [31:0]M_AXI_GP0_ARADDR;
wire [1:0]M_AXI_GP0_ARBURST;
wire [3:0]\^M_AXI_GP0_ARCACHE ;
wire M_AXI_GP0_ARESETN;
wire [11:0]M_AXI_GP0_ARID;
wire [3:0]M_AXI_GP0_ARLEN;
wire [1:0]M_AXI_GP0_ARLOCK;
wire [2:0]M_AXI_GP0_ARPROT;
wire [3:0]M_AXI_GP0_ARQOS;
wire M_AXI_GP0_ARREADY;
wire [1:0]\^M_AXI_GP0_ARSIZE ;
wire M_AXI_GP0_ARVALID;
wire [31:0]M_AXI_GP0_AWADDR;
wire [1:0]M_AXI_GP0_AWBURST;
wire [3:0]\^M_AXI_GP0_AWCACHE ;
wire [11:0]M_AXI_GP0_AWID;
wire [3:0]M_AXI_GP0_AWLEN;
wire [1:0]M_AXI_GP0_AWLOCK;
wire [2:0]M_AXI_GP0_AWPROT;
wire [3:0]M_AXI_GP0_AWQOS;
wire M_AXI_GP0_AWREADY;
wire [1:0]\^M_AXI_GP0_AWSIZE ;
wire M_AXI_GP0_AWVALID;
wire [11:0]M_AXI_GP0_BID;
wire M_AXI_GP0_BREADY;
wire [1:0]M_AXI_GP0_BRESP;
wire M_AXI_GP0_BVALID;
wire [31:0]M_AXI_GP0_RDATA;
wire [11:0]M_AXI_GP0_RID;
wire M_AXI_GP0_RLAST;
wire M_AXI_GP0_RREADY;
wire [1:0]M_AXI_GP0_RRESP;
wire M_AXI_GP0_RVALID;
wire [31:0]M_AXI_GP0_WDATA;
wire [11:0]M_AXI_GP0_WID;
wire M_AXI_GP0_WLAST;
wire M_AXI_GP0_WREADY;
wire [3:0]M_AXI_GP0_WSTRB;
wire M_AXI_GP0_WVALID;
wire M_AXI_GP1_ACLK;
wire [31:0]M_AXI_GP1_ARADDR;
wire [1:0]M_AXI_GP1_ARBURST;
wire [3:0]\^M_AXI_GP1_ARCACHE ;
wire M_AXI_GP1_ARESETN;
wire [11:0]M_AXI_GP1_ARID;
wire [3:0]M_AXI_GP1_ARLEN;
wire [1:0]M_AXI_GP1_ARLOCK;
wire [2:0]M_AXI_GP1_ARPROT;
wire [3:0]M_AXI_GP1_ARQOS;
wire M_AXI_GP1_ARREADY;
wire [1:0]\^M_AXI_GP1_ARSIZE ;
wire M_AXI_GP1_ARVALID;
wire [31:0]M_AXI_GP1_AWADDR;
wire [1:0]M_AXI_GP1_AWBURST;
wire [3:0]\^M_AXI_GP1_AWCACHE ;
wire [11:0]M_AXI_GP1_AWID;
wire [3:0]M_AXI_GP1_AWLEN;
wire [1:0]M_AXI_GP1_AWLOCK;
wire [2:0]M_AXI_GP1_AWPROT;
wire [3:0]M_AXI_GP1_AWQOS;
wire M_AXI_GP1_AWREADY;
wire [1:0]\^M_AXI_GP1_AWSIZE ;
wire M_AXI_GP1_AWVALID;
wire [11:0]M_AXI_GP1_BID;
wire M_AXI_GP1_BREADY;
wire [1:0]M_AXI_GP1_BRESP;
wire M_AXI_GP1_BVALID;
wire [31:0]M_AXI_GP1_RDATA;
wire [11:0]M_AXI_GP1_RID;
wire M_AXI_GP1_RLAST;
wire M_AXI_GP1_RREADY;
wire [1:0]M_AXI_GP1_RRESP;
wire M_AXI_GP1_RVALID;
wire [31:0]M_AXI_GP1_WDATA;
wire [11:0]M_AXI_GP1_WID;
wire M_AXI_GP1_WLAST;
wire M_AXI_GP1_WREADY;
wire [3:0]M_AXI_GP1_WSTRB;
wire M_AXI_GP1_WVALID;
wire PJTAG_TCK;
wire PJTAG_TDI;
wire PJTAG_TMS;
wire PS_CLK;
wire PS_PORB;
wire PS_SRSTB;
wire SDIO0_BUSPOW;
wire [2:0]SDIO0_BUSVOLT;
wire SDIO0_CDN;
wire SDIO0_CLK;
wire SDIO0_CLK_FB;
wire SDIO0_CMD_I;
wire SDIO0_CMD_O;
wire SDIO0_CMD_T;
wire SDIO0_CMD_T_n;
wire [3:0]SDIO0_DATA_I;
wire [3:0]SDIO0_DATA_O;
wire [3:0]SDIO0_DATA_T;
wire [3:0]SDIO0_DATA_T_n;
wire SDIO0_LED;
wire SDIO0_WP;
wire SDIO1_BUSPOW;
wire [2:0]SDIO1_BUSVOLT;
wire SDIO1_CDN;
wire SDIO1_CLK;
wire SDIO1_CLK_FB;
wire SDIO1_CMD_I;
wire SDIO1_CMD_O;
wire SDIO1_CMD_T;
wire SDIO1_CMD_T_n;
wire [3:0]SDIO1_DATA_I;
wire [3:0]SDIO1_DATA_O;
wire [3:0]SDIO1_DATA_T;
wire [3:0]SDIO1_DATA_T_n;
wire SDIO1_LED;
wire SDIO1_WP;
wire SPI0_MISO_I;
wire SPI0_MISO_O;
wire SPI0_MISO_T;
wire SPI0_MISO_T_n;
wire SPI0_MOSI_I;
wire SPI0_MOSI_O;
wire SPI0_MOSI_T;
wire SPI0_MOSI_T_n;
wire SPI0_SCLK_I;
wire SPI0_SCLK_O;
wire SPI0_SCLK_T;
wire SPI0_SCLK_T_n;
wire SPI0_SS1_O;
wire SPI0_SS2_O;
wire SPI0_SS_I;
wire SPI0_SS_O;
wire SPI0_SS_T;
wire SPI0_SS_T_n;
wire SPI1_MISO_I;
wire SPI1_MISO_O;
wire SPI1_MISO_T;
wire SPI1_MISO_T_n;
wire SPI1_MOSI_I;
wire SPI1_MOSI_O;
wire SPI1_MOSI_T;
wire SPI1_MOSI_T_n;
wire SPI1_SCLK_I;
wire SPI1_SCLK_O;
wire SPI1_SCLK_T;
wire SPI1_SCLK_T_n;
wire SPI1_SS1_O;
wire SPI1_SS2_O;
wire SPI1_SS_I;
wire SPI1_SS_O;
wire SPI1_SS_T;
wire SPI1_SS_T_n;
wire SRAM_INTIN;
wire S_AXI_ACP_ACLK;
wire [31:0]S_AXI_ACP_ARADDR;
wire [1:0]S_AXI_ACP_ARBURST;
wire [3:0]S_AXI_ACP_ARCACHE;
wire S_AXI_ACP_ARESETN;
wire [2:0]S_AXI_ACP_ARID;
wire [3:0]S_AXI_ACP_ARLEN;
wire [1:0]S_AXI_ACP_ARLOCK;
wire [2:0]S_AXI_ACP_ARPROT;
wire [3:0]S_AXI_ACP_ARQOS;
wire S_AXI_ACP_ARREADY;
wire [2:0]S_AXI_ACP_ARSIZE;
wire [4:0]S_AXI_ACP_ARUSER;
wire S_AXI_ACP_ARVALID;
wire [31:0]S_AXI_ACP_AWADDR;
wire [1:0]S_AXI_ACP_AWBURST;
wire [3:0]S_AXI_ACP_AWCACHE;
wire [2:0]S_AXI_ACP_AWID;
wire [3:0]S_AXI_ACP_AWLEN;
wire [1:0]S_AXI_ACP_AWLOCK;
wire [2:0]S_AXI_ACP_AWPROT;
wire [3:0]S_AXI_ACP_AWQOS;
wire S_AXI_ACP_AWREADY;
wire [2:0]S_AXI_ACP_AWSIZE;
wire [4:0]S_AXI_ACP_AWUSER;
wire S_AXI_ACP_AWVALID;
wire [2:0]S_AXI_ACP_BID;
wire S_AXI_ACP_BREADY;
wire [1:0]S_AXI_ACP_BRESP;
wire S_AXI_ACP_BVALID;
wire [63:0]S_AXI_ACP_RDATA;
wire [2:0]S_AXI_ACP_RID;
wire S_AXI_ACP_RLAST;
wire S_AXI_ACP_RREADY;
wire [1:0]S_AXI_ACP_RRESP;
wire S_AXI_ACP_RVALID;
wire [63:0]S_AXI_ACP_WDATA;
wire [2:0]S_AXI_ACP_WID;
wire S_AXI_ACP_WLAST;
wire S_AXI_ACP_WREADY;
wire [7:0]S_AXI_ACP_WSTRB;
wire S_AXI_ACP_WVALID;
wire S_AXI_GP0_ACLK;
wire [31:0]S_AXI_GP0_ARADDR;
wire [1:0]S_AXI_GP0_ARBURST;
wire [3:0]S_AXI_GP0_ARCACHE;
wire S_AXI_GP0_ARESETN;
wire [5:0]S_AXI_GP0_ARID;
wire [3:0]S_AXI_GP0_ARLEN;
wire [1:0]S_AXI_GP0_ARLOCK;
wire [2:0]S_AXI_GP0_ARPROT;
wire [3:0]S_AXI_GP0_ARQOS;
wire S_AXI_GP0_ARREADY;
wire [2:0]S_AXI_GP0_ARSIZE;
wire S_AXI_GP0_ARVALID;
wire [31:0]S_AXI_GP0_AWADDR;
wire [1:0]S_AXI_GP0_AWBURST;
wire [3:0]S_AXI_GP0_AWCACHE;
wire [5:0]S_AXI_GP0_AWID;
wire [3:0]S_AXI_GP0_AWLEN;
wire [1:0]S_AXI_GP0_AWLOCK;
wire [2:0]S_AXI_GP0_AWPROT;
wire [3:0]S_AXI_GP0_AWQOS;
wire S_AXI_GP0_AWREADY;
wire [2:0]S_AXI_GP0_AWSIZE;
wire S_AXI_GP0_AWVALID;
wire [5:0]S_AXI_GP0_BID;
wire S_AXI_GP0_BREADY;
wire [1:0]S_AXI_GP0_BRESP;
wire S_AXI_GP0_BVALID;
wire [31:0]S_AXI_GP0_RDATA;
wire [5:0]S_AXI_GP0_RID;
wire S_AXI_GP0_RLAST;
wire S_AXI_GP0_RREADY;
wire [1:0]S_AXI_GP0_RRESP;
wire S_AXI_GP0_RVALID;
wire [31:0]S_AXI_GP0_WDATA;
wire [5:0]S_AXI_GP0_WID;
wire S_AXI_GP0_WLAST;
wire S_AXI_GP0_WREADY;
wire [3:0]S_AXI_GP0_WSTRB;
wire S_AXI_GP0_WVALID;
wire S_AXI_GP1_ACLK;
wire [31:0]S_AXI_GP1_ARADDR;
wire [1:0]S_AXI_GP1_ARBURST;
wire [3:0]S_AXI_GP1_ARCACHE;
wire S_AXI_GP1_ARESETN;
wire [5:0]S_AXI_GP1_ARID;
wire [3:0]S_AXI_GP1_ARLEN;
wire [1:0]S_AXI_GP1_ARLOCK;
wire [2:0]S_AXI_GP1_ARPROT;
wire [3:0]S_AXI_GP1_ARQOS;
wire S_AXI_GP1_ARREADY;
wire [2:0]S_AXI_GP1_ARSIZE;
wire S_AXI_GP1_ARVALID;
wire [31:0]S_AXI_GP1_AWADDR;
wire [1:0]S_AXI_GP1_AWBURST;
wire [3:0]S_AXI_GP1_AWCACHE;
wire [5:0]S_AXI_GP1_AWID;
wire [3:0]S_AXI_GP1_AWLEN;
wire [1:0]S_AXI_GP1_AWLOCK;
wire [2:0]S_AXI_GP1_AWPROT;
wire [3:0]S_AXI_GP1_AWQOS;
wire S_AXI_GP1_AWREADY;
wire [2:0]S_AXI_GP1_AWSIZE;
wire S_AXI_GP1_AWVALID;
wire [5:0]S_AXI_GP1_BID;
wire S_AXI_GP1_BREADY;
wire [1:0]S_AXI_GP1_BRESP;
wire S_AXI_GP1_BVALID;
wire [31:0]S_AXI_GP1_RDATA;
wire [5:0]S_AXI_GP1_RID;
wire S_AXI_GP1_RLAST;
wire S_AXI_GP1_RREADY;
wire [1:0]S_AXI_GP1_RRESP;
wire S_AXI_GP1_RVALID;
wire [31:0]S_AXI_GP1_WDATA;
wire [5:0]S_AXI_GP1_WID;
wire S_AXI_GP1_WLAST;
wire S_AXI_GP1_WREADY;
wire [3:0]S_AXI_GP1_WSTRB;
wire S_AXI_GP1_WVALID;
wire S_AXI_HP0_ACLK;
wire [31:0]S_AXI_HP0_ARADDR;
wire [1:0]S_AXI_HP0_ARBURST;
wire [3:0]S_AXI_HP0_ARCACHE;
wire S_AXI_HP0_ARESETN;
wire [5:0]S_AXI_HP0_ARID;
wire [3:0]S_AXI_HP0_ARLEN;
wire [1:0]S_AXI_HP0_ARLOCK;
wire [2:0]S_AXI_HP0_ARPROT;
wire [3:0]S_AXI_HP0_ARQOS;
wire S_AXI_HP0_ARREADY;
wire [2:0]S_AXI_HP0_ARSIZE;
wire S_AXI_HP0_ARVALID;
wire [31:0]S_AXI_HP0_AWADDR;
wire [1:0]S_AXI_HP0_AWBURST;
wire [3:0]S_AXI_HP0_AWCACHE;
wire [5:0]S_AXI_HP0_AWID;
wire [3:0]S_AXI_HP0_AWLEN;
wire [1:0]S_AXI_HP0_AWLOCK;
wire [2:0]S_AXI_HP0_AWPROT;
wire [3:0]S_AXI_HP0_AWQOS;
wire S_AXI_HP0_AWREADY;
wire [2:0]S_AXI_HP0_AWSIZE;
wire S_AXI_HP0_AWVALID;
wire [5:0]S_AXI_HP0_BID;
wire S_AXI_HP0_BREADY;
wire [1:0]S_AXI_HP0_BRESP;
wire S_AXI_HP0_BVALID;
wire [2:0]S_AXI_HP0_RACOUNT;
wire [7:0]S_AXI_HP0_RCOUNT;
wire [63:0]S_AXI_HP0_RDATA;
wire S_AXI_HP0_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP0_RID;
wire S_AXI_HP0_RLAST;
wire S_AXI_HP0_RREADY;
wire [1:0]S_AXI_HP0_RRESP;
wire S_AXI_HP0_RVALID;
wire [5:0]S_AXI_HP0_WACOUNT;
wire [7:0]S_AXI_HP0_WCOUNT;
wire [63:0]S_AXI_HP0_WDATA;
wire [5:0]S_AXI_HP0_WID;
wire S_AXI_HP0_WLAST;
wire S_AXI_HP0_WREADY;
wire S_AXI_HP0_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP0_WSTRB;
wire S_AXI_HP0_WVALID;
wire S_AXI_HP1_ACLK;
wire [31:0]S_AXI_HP1_ARADDR;
wire [1:0]S_AXI_HP1_ARBURST;
wire [3:0]S_AXI_HP1_ARCACHE;
wire S_AXI_HP1_ARESETN;
wire [5:0]S_AXI_HP1_ARID;
wire [3:0]S_AXI_HP1_ARLEN;
wire [1:0]S_AXI_HP1_ARLOCK;
wire [2:0]S_AXI_HP1_ARPROT;
wire [3:0]S_AXI_HP1_ARQOS;
wire S_AXI_HP1_ARREADY;
wire [2:0]S_AXI_HP1_ARSIZE;
wire S_AXI_HP1_ARVALID;
wire [31:0]S_AXI_HP1_AWADDR;
wire [1:0]S_AXI_HP1_AWBURST;
wire [3:0]S_AXI_HP1_AWCACHE;
wire [5:0]S_AXI_HP1_AWID;
wire [3:0]S_AXI_HP1_AWLEN;
wire [1:0]S_AXI_HP1_AWLOCK;
wire [2:0]S_AXI_HP1_AWPROT;
wire [3:0]S_AXI_HP1_AWQOS;
wire S_AXI_HP1_AWREADY;
wire [2:0]S_AXI_HP1_AWSIZE;
wire S_AXI_HP1_AWVALID;
wire [5:0]S_AXI_HP1_BID;
wire S_AXI_HP1_BREADY;
wire [1:0]S_AXI_HP1_BRESP;
wire S_AXI_HP1_BVALID;
wire [2:0]S_AXI_HP1_RACOUNT;
wire [7:0]S_AXI_HP1_RCOUNT;
wire [63:0]S_AXI_HP1_RDATA;
wire S_AXI_HP1_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP1_RID;
wire S_AXI_HP1_RLAST;
wire S_AXI_HP1_RREADY;
wire [1:0]S_AXI_HP1_RRESP;
wire S_AXI_HP1_RVALID;
wire [5:0]S_AXI_HP1_WACOUNT;
wire [7:0]S_AXI_HP1_WCOUNT;
wire [63:0]S_AXI_HP1_WDATA;
wire [5:0]S_AXI_HP1_WID;
wire S_AXI_HP1_WLAST;
wire S_AXI_HP1_WREADY;
wire S_AXI_HP1_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP1_WSTRB;
wire S_AXI_HP1_WVALID;
wire S_AXI_HP2_ACLK;
wire [31:0]S_AXI_HP2_ARADDR;
wire [1:0]S_AXI_HP2_ARBURST;
wire [3:0]S_AXI_HP2_ARCACHE;
wire S_AXI_HP2_ARESETN;
wire [5:0]S_AXI_HP2_ARID;
wire [3:0]S_AXI_HP2_ARLEN;
wire [1:0]S_AXI_HP2_ARLOCK;
wire [2:0]S_AXI_HP2_ARPROT;
wire [3:0]S_AXI_HP2_ARQOS;
wire S_AXI_HP2_ARREADY;
wire [2:0]S_AXI_HP2_ARSIZE;
wire S_AXI_HP2_ARVALID;
wire [31:0]S_AXI_HP2_AWADDR;
wire [1:0]S_AXI_HP2_AWBURST;
wire [3:0]S_AXI_HP2_AWCACHE;
wire [5:0]S_AXI_HP2_AWID;
wire [3:0]S_AXI_HP2_AWLEN;
wire [1:0]S_AXI_HP2_AWLOCK;
wire [2:0]S_AXI_HP2_AWPROT;
wire [3:0]S_AXI_HP2_AWQOS;
wire S_AXI_HP2_AWREADY;
wire [2:0]S_AXI_HP2_AWSIZE;
wire S_AXI_HP2_AWVALID;
wire [5:0]S_AXI_HP2_BID;
wire S_AXI_HP2_BREADY;
wire [1:0]S_AXI_HP2_BRESP;
wire S_AXI_HP2_BVALID;
wire [2:0]S_AXI_HP2_RACOUNT;
wire [7:0]S_AXI_HP2_RCOUNT;
wire [63:0]S_AXI_HP2_RDATA;
wire S_AXI_HP2_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP2_RID;
wire S_AXI_HP2_RLAST;
wire S_AXI_HP2_RREADY;
wire [1:0]S_AXI_HP2_RRESP;
wire S_AXI_HP2_RVALID;
wire [5:0]S_AXI_HP2_WACOUNT;
wire [7:0]S_AXI_HP2_WCOUNT;
wire [63:0]S_AXI_HP2_WDATA;
wire [5:0]S_AXI_HP2_WID;
wire S_AXI_HP2_WLAST;
wire S_AXI_HP2_WREADY;
wire S_AXI_HP2_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP2_WSTRB;
wire S_AXI_HP2_WVALID;
wire S_AXI_HP3_ACLK;
wire [31:0]S_AXI_HP3_ARADDR;
wire [1:0]S_AXI_HP3_ARBURST;
wire [3:0]S_AXI_HP3_ARCACHE;
wire S_AXI_HP3_ARESETN;
wire [5:0]S_AXI_HP3_ARID;
wire [3:0]S_AXI_HP3_ARLEN;
wire [1:0]S_AXI_HP3_ARLOCK;
wire [2:0]S_AXI_HP3_ARPROT;
wire [3:0]S_AXI_HP3_ARQOS;
wire S_AXI_HP3_ARREADY;
wire [2:0]S_AXI_HP3_ARSIZE;
wire S_AXI_HP3_ARVALID;
wire [31:0]S_AXI_HP3_AWADDR;
wire [1:0]S_AXI_HP3_AWBURST;
wire [3:0]S_AXI_HP3_AWCACHE;
wire [5:0]S_AXI_HP3_AWID;
wire [3:0]S_AXI_HP3_AWLEN;
wire [1:0]S_AXI_HP3_AWLOCK;
wire [2:0]S_AXI_HP3_AWPROT;
wire [3:0]S_AXI_HP3_AWQOS;
wire S_AXI_HP3_AWREADY;
wire [2:0]S_AXI_HP3_AWSIZE;
wire S_AXI_HP3_AWVALID;
wire [5:0]S_AXI_HP3_BID;
wire S_AXI_HP3_BREADY;
wire [1:0]S_AXI_HP3_BRESP;
wire S_AXI_HP3_BVALID;
wire [2:0]S_AXI_HP3_RACOUNT;
wire [7:0]S_AXI_HP3_RCOUNT;
wire [63:0]S_AXI_HP3_RDATA;
wire S_AXI_HP3_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP3_RID;
wire S_AXI_HP3_RLAST;
wire S_AXI_HP3_RREADY;
wire [1:0]S_AXI_HP3_RRESP;
wire S_AXI_HP3_RVALID;
wire [5:0]S_AXI_HP3_WACOUNT;
wire [7:0]S_AXI_HP3_WCOUNT;
wire [63:0]S_AXI_HP3_WDATA;
wire [5:0]S_AXI_HP3_WID;
wire S_AXI_HP3_WLAST;
wire S_AXI_HP3_WREADY;
wire S_AXI_HP3_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP3_WSTRB;
wire S_AXI_HP3_WVALID;
wire TRACE_CLK;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[0] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[1] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[2] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[3] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[4] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[5] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[6] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[7] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[0] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[1] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[2] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[3] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[4] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[5] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[6] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[7] ;
wire TTC0_CLK0_IN;
wire TTC0_CLK1_IN;
wire TTC0_CLK2_IN;
wire TTC0_WAVE0_OUT;
wire TTC0_WAVE1_OUT;
wire TTC0_WAVE2_OUT;
wire TTC1_CLK0_IN;
wire TTC1_CLK1_IN;
wire TTC1_CLK2_IN;
wire TTC1_WAVE0_OUT;
wire TTC1_WAVE1_OUT;
wire TTC1_WAVE2_OUT;
wire UART0_CTSN;
wire UART0_DCDN;
wire UART0_DSRN;
wire UART0_DTRN;
wire UART0_RIN;
wire UART0_RTSN;
wire UART0_RX;
wire UART0_TX;
wire UART1_CTSN;
wire UART1_DCDN;
wire UART1_DSRN;
wire UART1_DTRN;
wire UART1_RIN;
wire UART1_RTSN;
wire UART1_RX;
wire UART1_TX;
wire [1:0]USB0_PORT_INDCTL;
wire USB0_VBUS_PWRFAULT;
wire USB0_VBUS_PWRSELECT;
wire [1:0]USB1_PORT_INDCTL;
wire USB1_VBUS_PWRFAULT;
wire USB1_VBUS_PWRSELECT;
wire WDT_CLK_IN;
wire WDT_RST_OUT;
wire [14:0]buffered_DDR_Addr;
wire [2:0]buffered_DDR_BankAddr;
wire buffered_DDR_CAS_n;
wire buffered_DDR_CKE;
wire buffered_DDR_CS_n;
wire buffered_DDR_Clk;
wire buffered_DDR_Clk_n;
wire [3:0]buffered_DDR_DM;
wire [31:0]buffered_DDR_DQ;
wire [3:0]buffered_DDR_DQS;
wire [3:0]buffered_DDR_DQS_n;
wire buffered_DDR_DRSTB;
wire buffered_DDR_ODT;
wire buffered_DDR_RAS_n;
wire buffered_DDR_VRN;
wire buffered_DDR_VRP;
wire buffered_DDR_WEB;
wire [53:0]buffered_MIO;
wire buffered_PS_CLK;
wire buffered_PS_PORB;
wire buffered_PS_SRSTB;
wire [63:0]gpio_out_t_n;
wire NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED;
wire NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED;
wire NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED;
wire NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED;
wire NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED;
wire NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED;
wire NLW_PS7_i_EMIOTRACECTL_UNCONNECTED;
wire [7:0]NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED;
wire [7:0]NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED;
wire [31:0]NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED;
wire [1:1]NLW_PS7_i_MAXIGP0ARCACHE_UNCONNECTED;
wire [1:1]NLW_PS7_i_MAXIGP0AWCACHE_UNCONNECTED;
wire [1:1]NLW_PS7_i_MAXIGP1ARCACHE_UNCONNECTED;
wire [1:1]NLW_PS7_i_MAXIGP1AWCACHE_UNCONNECTED;
assign ENET0_GMII_TXD[7] = \<const0> ;
assign ENET0_GMII_TXD[6] = \<const0> ;
assign ENET0_GMII_TXD[5] = \<const0> ;
assign ENET0_GMII_TXD[4] = \<const0> ;
assign ENET0_GMII_TXD[3] = \<const0> ;
assign ENET0_GMII_TXD[2] = \<const0> ;
assign ENET0_GMII_TXD[1] = \<const0> ;
assign ENET0_GMII_TXD[0] = \<const0> ;
assign ENET0_GMII_TX_EN = \<const0> ;
assign ENET0_GMII_TX_ER = \<const0> ;
assign ENET1_GMII_TXD[7] = \<const0> ;
assign ENET1_GMII_TXD[6] = \<const0> ;
assign ENET1_GMII_TXD[5] = \<const0> ;
assign ENET1_GMII_TXD[4] = \<const0> ;
assign ENET1_GMII_TXD[3] = \<const0> ;
assign ENET1_GMII_TXD[2] = \<const0> ;
assign ENET1_GMII_TXD[1] = \<const0> ;
assign ENET1_GMII_TXD[0] = \<const0> ;
assign ENET1_GMII_TX_EN = \<const0> ;
assign ENET1_GMII_TX_ER = \<const0> ;
assign M_AXI_GP0_ARCACHE[3:2] = \^M_AXI_GP0_ARCACHE [3:2];
assign M_AXI_GP0_ARCACHE[1] = \<const1> ;
assign M_AXI_GP0_ARCACHE[0] = \^M_AXI_GP0_ARCACHE [0];
assign M_AXI_GP0_ARSIZE[2] = \<const0> ;
assign M_AXI_GP0_ARSIZE[1:0] = \^M_AXI_GP0_ARSIZE [1:0];
assign M_AXI_GP0_AWCACHE[3:2] = \^M_AXI_GP0_AWCACHE [3:2];
assign M_AXI_GP0_AWCACHE[1] = \<const1> ;
assign M_AXI_GP0_AWCACHE[0] = \^M_AXI_GP0_AWCACHE [0];
assign M_AXI_GP0_AWSIZE[2] = \<const0> ;
assign M_AXI_GP0_AWSIZE[1:0] = \^M_AXI_GP0_AWSIZE [1:0];
assign M_AXI_GP1_ARCACHE[3:2] = \^M_AXI_GP1_ARCACHE [3:2];
assign M_AXI_GP1_ARCACHE[1] = \<const1> ;
assign M_AXI_GP1_ARCACHE[0] = \^M_AXI_GP1_ARCACHE [0];
assign M_AXI_GP1_ARSIZE[2] = \<const0> ;
assign M_AXI_GP1_ARSIZE[1:0] = \^M_AXI_GP1_ARSIZE [1:0];
assign M_AXI_GP1_AWCACHE[3:2] = \^M_AXI_GP1_AWCACHE [3:2];
assign M_AXI_GP1_AWCACHE[1] = \<const1> ;
assign M_AXI_GP1_AWCACHE[0] = \^M_AXI_GP1_AWCACHE [0];
assign M_AXI_GP1_AWSIZE[2] = \<const0> ;
assign M_AXI_GP1_AWSIZE[1:0] = \^M_AXI_GP1_AWSIZE [1:0];
assign PJTAG_TDO = \<const0> ;
assign TRACE_CLK_OUT = \<const0> ;
assign TRACE_CTL = \TRACE_CTL_PIPE[0] ;
assign TRACE_DATA[1:0] = \TRACE_DATA_PIPE[0] ;
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_CAS_n_BIBUF
(.IO(buffered_DDR_CAS_n),
.PAD(DDR_CAS_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_CKE_BIBUF
(.IO(buffered_DDR_CKE),
.PAD(DDR_CKE));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_CS_n_BIBUF
(.IO(buffered_DDR_CS_n),
.PAD(DDR_CS_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_Clk_BIBUF
(.IO(buffered_DDR_Clk),
.PAD(DDR_Clk));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_Clk_n_BIBUF
(.IO(buffered_DDR_Clk_n),
.PAD(DDR_Clk_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_DRSTB_BIBUF
(.IO(buffered_DDR_DRSTB),
.PAD(DDR_DRSTB));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_ODT_BIBUF
(.IO(buffered_DDR_ODT),
.PAD(DDR_ODT));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_RAS_n_BIBUF
(.IO(buffered_DDR_RAS_n),
.PAD(DDR_RAS_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_VRN_BIBUF
(.IO(buffered_DDR_VRN),
.PAD(DDR_VRN));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_VRP_BIBUF
(.IO(buffered_DDR_VRP),
.PAD(DDR_VRP));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_WEB_BIBUF
(.IO(buffered_DDR_WEB),
.PAD(DDR_WEB));
LUT1 #(
.INIT(2'h1))
ENET0_MDIO_T_INST_0
(.I0(ENET0_MDIO_T_n),
.O(ENET0_MDIO_T));
LUT1 #(
.INIT(2'h1))
ENET1_MDIO_T_INST_0
(.I0(ENET1_MDIO_T_n),
.O(ENET1_MDIO_T));
GND GND
(.G(\<const0> ));
LUT1 #(
.INIT(2'h1))
\GPIO_T[0]_INST_0
(.I0(gpio_out_t_n[0]),
.O(GPIO_T[0]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[10]_INST_0
(.I0(gpio_out_t_n[10]),
.O(GPIO_T[10]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[11]_INST_0
(.I0(gpio_out_t_n[11]),
.O(GPIO_T[11]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[12]_INST_0
(.I0(gpio_out_t_n[12]),
.O(GPIO_T[12]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[13]_INST_0
(.I0(gpio_out_t_n[13]),
.O(GPIO_T[13]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[14]_INST_0
(.I0(gpio_out_t_n[14]),
.O(GPIO_T[14]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[15]_INST_0
(.I0(gpio_out_t_n[15]),
.O(GPIO_T[15]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[16]_INST_0
(.I0(gpio_out_t_n[16]),
.O(GPIO_T[16]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[17]_INST_0
(.I0(gpio_out_t_n[17]),
.O(GPIO_T[17]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[18]_INST_0
(.I0(gpio_out_t_n[18]),
.O(GPIO_T[18]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[19]_INST_0
(.I0(gpio_out_t_n[19]),
.O(GPIO_T[19]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[1]_INST_0
(.I0(gpio_out_t_n[1]),
.O(GPIO_T[1]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[20]_INST_0
(.I0(gpio_out_t_n[20]),
.O(GPIO_T[20]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[21]_INST_0
(.I0(gpio_out_t_n[21]),
.O(GPIO_T[21]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[22]_INST_0
(.I0(gpio_out_t_n[22]),
.O(GPIO_T[22]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[23]_INST_0
(.I0(gpio_out_t_n[23]),
.O(GPIO_T[23]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[24]_INST_0
(.I0(gpio_out_t_n[24]),
.O(GPIO_T[24]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[25]_INST_0
(.I0(gpio_out_t_n[25]),
.O(GPIO_T[25]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[26]_INST_0
(.I0(gpio_out_t_n[26]),
.O(GPIO_T[26]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[27]_INST_0
(.I0(gpio_out_t_n[27]),
.O(GPIO_T[27]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[28]_INST_0
(.I0(gpio_out_t_n[28]),
.O(GPIO_T[28]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[29]_INST_0
(.I0(gpio_out_t_n[29]),
.O(GPIO_T[29]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[2]_INST_0
(.I0(gpio_out_t_n[2]),
.O(GPIO_T[2]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[30]_INST_0
(.I0(gpio_out_t_n[30]),
.O(GPIO_T[30]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[31]_INST_0
(.I0(gpio_out_t_n[31]),
.O(GPIO_T[31]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[32]_INST_0
(.I0(gpio_out_t_n[32]),
.O(GPIO_T[32]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[33]_INST_0
(.I0(gpio_out_t_n[33]),
.O(GPIO_T[33]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[34]_INST_0
(.I0(gpio_out_t_n[34]),
.O(GPIO_T[34]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[35]_INST_0
(.I0(gpio_out_t_n[35]),
.O(GPIO_T[35]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[36]_INST_0
(.I0(gpio_out_t_n[36]),
.O(GPIO_T[36]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[37]_INST_0
(.I0(gpio_out_t_n[37]),
.O(GPIO_T[37]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[38]_INST_0
(.I0(gpio_out_t_n[38]),
.O(GPIO_T[38]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[39]_INST_0
(.I0(gpio_out_t_n[39]),
.O(GPIO_T[39]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[3]_INST_0
(.I0(gpio_out_t_n[3]),
.O(GPIO_T[3]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[40]_INST_0
(.I0(gpio_out_t_n[40]),
.O(GPIO_T[40]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[41]_INST_0
(.I0(gpio_out_t_n[41]),
.O(GPIO_T[41]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[42]_INST_0
(.I0(gpio_out_t_n[42]),
.O(GPIO_T[42]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[43]_INST_0
(.I0(gpio_out_t_n[43]),
.O(GPIO_T[43]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[44]_INST_0
(.I0(gpio_out_t_n[44]),
.O(GPIO_T[44]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[45]_INST_0
(.I0(gpio_out_t_n[45]),
.O(GPIO_T[45]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[46]_INST_0
(.I0(gpio_out_t_n[46]),
.O(GPIO_T[46]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[47]_INST_0
(.I0(gpio_out_t_n[47]),
.O(GPIO_T[47]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[48]_INST_0
(.I0(gpio_out_t_n[48]),
.O(GPIO_T[48]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[49]_INST_0
(.I0(gpio_out_t_n[49]),
.O(GPIO_T[49]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[4]_INST_0
(.I0(gpio_out_t_n[4]),
.O(GPIO_T[4]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[50]_INST_0
(.I0(gpio_out_t_n[50]),
.O(GPIO_T[50]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[51]_INST_0
(.I0(gpio_out_t_n[51]),
.O(GPIO_T[51]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[52]_INST_0
(.I0(gpio_out_t_n[52]),
.O(GPIO_T[52]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[53]_INST_0
(.I0(gpio_out_t_n[53]),
.O(GPIO_T[53]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[54]_INST_0
(.I0(gpio_out_t_n[54]),
.O(GPIO_T[54]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[55]_INST_0
(.I0(gpio_out_t_n[55]),
.O(GPIO_T[55]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[56]_INST_0
(.I0(gpio_out_t_n[56]),
.O(GPIO_T[56]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[57]_INST_0
(.I0(gpio_out_t_n[57]),
.O(GPIO_T[57]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[58]_INST_0
(.I0(gpio_out_t_n[58]),
.O(GPIO_T[58]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[59]_INST_0
(.I0(gpio_out_t_n[59]),
.O(GPIO_T[59]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[5]_INST_0
(.I0(gpio_out_t_n[5]),
.O(GPIO_T[5]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[60]_INST_0
(.I0(gpio_out_t_n[60]),
.O(GPIO_T[60]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[61]_INST_0
(.I0(gpio_out_t_n[61]),
.O(GPIO_T[61]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[62]_INST_0
(.I0(gpio_out_t_n[62]),
.O(GPIO_T[62]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[63]_INST_0
(.I0(gpio_out_t_n[63]),
.O(GPIO_T[63]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[6]_INST_0
(.I0(gpio_out_t_n[6]),
.O(GPIO_T[6]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[7]_INST_0
(.I0(gpio_out_t_n[7]),
.O(GPIO_T[7]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[8]_INST_0
(.I0(gpio_out_t_n[8]),
.O(GPIO_T[8]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[9]_INST_0
(.I0(gpio_out_t_n[9]),
.O(GPIO_T[9]));
LUT1 #(
.INIT(2'h1))
I2C0_SCL_T_INST_0
(.I0(I2C0_SCL_T_n),
.O(I2C0_SCL_T));
LUT1 #(
.INIT(2'h1))
I2C0_SDA_T_INST_0
(.I0(I2C0_SDA_T_n),
.O(I2C0_SDA_T));
LUT1 #(
.INIT(2'h1))
I2C1_SCL_T_INST_0
(.I0(I2C1_SCL_T_n),
.O(I2C1_SCL_T));
LUT1 #(
.INIT(2'h1))
I2C1_SDA_T_INST_0
(.I0(I2C1_SDA_T_n),
.O(I2C1_SDA_T));
(* BOX_TYPE = "PRIMITIVE" *)
PS7 PS7_i
(.DDRA(buffered_DDR_Addr),
.DDRARB(DDR_ARB),
.DDRBA(buffered_DDR_BankAddr),
.DDRCASB(buffered_DDR_CAS_n),
.DDRCKE(buffered_DDR_CKE),
.DDRCKN(buffered_DDR_Clk_n),
.DDRCKP(buffered_DDR_Clk),
.DDRCSB(buffered_DDR_CS_n),
.DDRDM(buffered_DDR_DM),
.DDRDQ(buffered_DDR_DQ),
.DDRDQSN(buffered_DDR_DQS_n),
.DDRDQSP(buffered_DDR_DQS),
.DDRDRSTB(buffered_DDR_DRSTB),
.DDRODT(buffered_DDR_ODT),
.DDRRASB(buffered_DDR_RAS_n),
.DDRVRN(buffered_DDR_VRN),
.DDRVRP(buffered_DDR_VRP),
.DDRWEB(buffered_DDR_WEB),
.DMA0ACLK(DMA0_ACLK),
.DMA0DAREADY(DMA0_DAREADY),
.DMA0DATYPE(DMA0_DATYPE),
.DMA0DAVALID(DMA0_DAVALID),
.DMA0DRLAST(DMA0_DRLAST),
.DMA0DRREADY(DMA0_DRREADY),
.DMA0DRTYPE(DMA0_DRTYPE),
.DMA0DRVALID(DMA0_DRVALID),
.DMA0RSTN(DMA0_RSTN),
.DMA1ACLK(DMA1_ACLK),
.DMA1DAREADY(DMA1_DAREADY),
.DMA1DATYPE(DMA1_DATYPE),
.DMA1DAVALID(DMA1_DAVALID),
.DMA1DRLAST(DMA1_DRLAST),
.DMA1DRREADY(DMA1_DRREADY),
.DMA1DRTYPE(DMA1_DRTYPE),
.DMA1DRVALID(DMA1_DRVALID),
.DMA1RSTN(DMA1_RSTN),
.DMA2ACLK(DMA2_ACLK),
.DMA2DAREADY(DMA2_DAREADY),
.DMA2DATYPE(DMA2_DATYPE),
.DMA2DAVALID(DMA2_DAVALID),
.DMA2DRLAST(DMA2_DRLAST),
.DMA2DRREADY(DMA2_DRREADY),
.DMA2DRTYPE(DMA2_DRTYPE),
.DMA2DRVALID(DMA2_DRVALID),
.DMA2RSTN(DMA2_RSTN),
.DMA3ACLK(DMA3_ACLK),
.DMA3DAREADY(DMA3_DAREADY),
.DMA3DATYPE(DMA3_DATYPE),
.DMA3DAVALID(DMA3_DAVALID),
.DMA3DRLAST(DMA3_DRLAST),
.DMA3DRREADY(DMA3_DRREADY),
.DMA3DRTYPE(DMA3_DRTYPE),
.DMA3DRVALID(DMA3_DRVALID),
.DMA3RSTN(DMA3_RSTN),
.EMIOCAN0PHYRX(CAN0_PHY_RX),
.EMIOCAN0PHYTX(CAN0_PHY_TX),
.EMIOCAN1PHYRX(CAN1_PHY_RX),
.EMIOCAN1PHYTX(CAN1_PHY_TX),
.EMIOENET0EXTINTIN(ENET0_EXT_INTIN),
.EMIOENET0GMIICOL(1'b0),
.EMIOENET0GMIICRS(1'b0),
.EMIOENET0GMIIRXCLK(ENET0_GMII_RX_CLK),
.EMIOENET0GMIIRXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.EMIOENET0GMIIRXDV(1'b0),
.EMIOENET0GMIIRXER(1'b0),
.EMIOENET0GMIITXCLK(ENET0_GMII_TX_CLK),
.EMIOENET0GMIITXD(NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED[7:0]),
.EMIOENET0GMIITXEN(NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED),
.EMIOENET0GMIITXER(NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED),
.EMIOENET0MDIOI(ENET0_MDIO_I),
.EMIOENET0MDIOMDC(ENET0_MDIO_MDC),
.EMIOENET0MDIOO(ENET0_MDIO_O),
.EMIOENET0MDIOTN(ENET0_MDIO_T_n),
.EMIOENET0PTPDELAYREQRX(ENET0_PTP_DELAY_REQ_RX),
.EMIOENET0PTPDELAYREQTX(ENET0_PTP_DELAY_REQ_TX),
.EMIOENET0PTPPDELAYREQRX(ENET0_PTP_PDELAY_REQ_RX),
.EMIOENET0PTPPDELAYREQTX(ENET0_PTP_PDELAY_REQ_TX),
.EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
.EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
.EMIOENET0PTPSYNCFRAMERX(ENET0_PTP_SYNC_FRAME_RX),
.EMIOENET0PTPSYNCFRAMETX(ENET0_PTP_SYNC_FRAME_TX),
.EMIOENET0SOFRX(ENET0_SOF_RX),
.EMIOENET0SOFTX(ENET0_SOF_TX),
.EMIOENET1EXTINTIN(ENET1_EXT_INTIN),
.EMIOENET1GMIICOL(1'b0),
.EMIOENET1GMIICRS(1'b0),
.EMIOENET1GMIIRXCLK(ENET1_GMII_RX_CLK),
.EMIOENET1GMIIRXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.EMIOENET1GMIIRXDV(1'b0),
.EMIOENET1GMIIRXER(1'b0),
.EMIOENET1GMIITXCLK(ENET1_GMII_TX_CLK),
.EMIOENET1GMIITXD(NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED[7:0]),
.EMIOENET1GMIITXEN(NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED),
.EMIOENET1GMIITXER(NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED),
.EMIOENET1MDIOI(ENET1_MDIO_I),
.EMIOENET1MDIOMDC(ENET1_MDIO_MDC),
.EMIOENET1MDIOO(ENET1_MDIO_O),
.EMIOENET1MDIOTN(ENET1_MDIO_T_n),
.EMIOENET1PTPDELAYREQRX(ENET1_PTP_DELAY_REQ_RX),
.EMIOENET1PTPDELAYREQTX(ENET1_PTP_DELAY_REQ_TX),
.EMIOENET1PTPPDELAYREQRX(ENET1_PTP_PDELAY_REQ_RX),
.EMIOENET1PTPPDELAYREQTX(ENET1_PTP_PDELAY_REQ_TX),
.EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
.EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
.EMIOENET1PTPSYNCFRAMERX(ENET1_PTP_SYNC_FRAME_RX),
.EMIOENET1PTPSYNCFRAMETX(ENET1_PTP_SYNC_FRAME_TX),
.EMIOENET1SOFRX(ENET1_SOF_RX),
.EMIOENET1SOFTX(ENET1_SOF_TX),
.EMIOGPIOI(GPIO_I),
.EMIOGPIOO(GPIO_O),
.EMIOGPIOTN(gpio_out_t_n),
.EMIOI2C0SCLI(I2C0_SCL_I),
.EMIOI2C0SCLO(I2C0_SCL_O),
.EMIOI2C0SCLTN(I2C0_SCL_T_n),
.EMIOI2C0SDAI(I2C0_SDA_I),
.EMIOI2C0SDAO(I2C0_SDA_O),
.EMIOI2C0SDATN(I2C0_SDA_T_n),
.EMIOI2C1SCLI(I2C1_SCL_I),
.EMIOI2C1SCLO(I2C1_SCL_O),
.EMIOI2C1SCLTN(I2C1_SCL_T_n),
.EMIOI2C1SDAI(I2C1_SDA_I),
.EMIOI2C1SDAO(I2C1_SDA_O),
.EMIOI2C1SDATN(I2C1_SDA_T_n),
.EMIOPJTAGTCK(PJTAG_TCK),
.EMIOPJTAGTDI(PJTAG_TDI),
.EMIOPJTAGTDO(NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED),
.EMIOPJTAGTDTN(NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED),
.EMIOPJTAGTMS(PJTAG_TMS),
.EMIOSDIO0BUSPOW(SDIO0_BUSPOW),
.EMIOSDIO0BUSVOLT(SDIO0_BUSVOLT),
.EMIOSDIO0CDN(SDIO0_CDN),
.EMIOSDIO0CLK(SDIO0_CLK),
.EMIOSDIO0CLKFB(SDIO0_CLK_FB),
.EMIOSDIO0CMDI(SDIO0_CMD_I),
.EMIOSDIO0CMDO(SDIO0_CMD_O),
.EMIOSDIO0CMDTN(SDIO0_CMD_T_n),
.EMIOSDIO0DATAI(SDIO0_DATA_I),
.EMIOSDIO0DATAO(SDIO0_DATA_O),
.EMIOSDIO0DATATN(SDIO0_DATA_T_n),
.EMIOSDIO0LED(SDIO0_LED),
.EMIOSDIO0WP(SDIO0_WP),
.EMIOSDIO1BUSPOW(SDIO1_BUSPOW),
.EMIOSDIO1BUSVOLT(SDIO1_BUSVOLT),
.EMIOSDIO1CDN(SDIO1_CDN),
.EMIOSDIO1CLK(SDIO1_CLK),
.EMIOSDIO1CLKFB(SDIO1_CLK_FB),
.EMIOSDIO1CMDI(SDIO1_CMD_I),
.EMIOSDIO1CMDO(SDIO1_CMD_O),
.EMIOSDIO1CMDTN(SDIO1_CMD_T_n),
.EMIOSDIO1DATAI(SDIO1_DATA_I),
.EMIOSDIO1DATAO(SDIO1_DATA_O),
.EMIOSDIO1DATATN(SDIO1_DATA_T_n),
.EMIOSDIO1LED(SDIO1_LED),
.EMIOSDIO1WP(SDIO1_WP),
.EMIOSPI0MI(SPI0_MISO_I),
.EMIOSPI0MO(SPI0_MOSI_O),
.EMIOSPI0MOTN(SPI0_MOSI_T_n),
.EMIOSPI0SCLKI(SPI0_SCLK_I),
.EMIOSPI0SCLKO(SPI0_SCLK_O),
.EMIOSPI0SCLKTN(SPI0_SCLK_T_n),
.EMIOSPI0SI(SPI0_MOSI_I),
.EMIOSPI0SO(SPI0_MISO_O),
.EMIOSPI0SSIN(SPI0_SS_I),
.EMIOSPI0SSNTN(SPI0_SS_T_n),
.EMIOSPI0SSON({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
.EMIOSPI0STN(SPI0_MISO_T_n),
.EMIOSPI1MI(SPI1_MISO_I),
.EMIOSPI1MO(SPI1_MOSI_O),
.EMIOSPI1MOTN(SPI1_MOSI_T_n),
.EMIOSPI1SCLKI(SPI1_SCLK_I),
.EMIOSPI1SCLKO(SPI1_SCLK_O),
.EMIOSPI1SCLKTN(SPI1_SCLK_T_n),
.EMIOSPI1SI(SPI1_MOSI_I),
.EMIOSPI1SO(SPI1_MISO_O),
.EMIOSPI1SSIN(SPI1_SS_I),
.EMIOSPI1SSNTN(SPI1_SS_T_n),
.EMIOSPI1SSON({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
.EMIOSPI1STN(SPI1_MISO_T_n),
.EMIOSRAMINTIN(SRAM_INTIN),
.EMIOTRACECLK(TRACE_CLK),
.EMIOTRACECTL(NLW_PS7_i_EMIOTRACECTL_UNCONNECTED),
.EMIOTRACEDATA(NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED[31:0]),
.EMIOTTC0CLKI({TTC0_CLK2_IN,TTC0_CLK1_IN,TTC0_CLK0_IN}),
.EMIOTTC0WAVEO({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
.EMIOTTC1CLKI({TTC1_CLK2_IN,TTC1_CLK1_IN,TTC1_CLK0_IN}),
.EMIOTTC1WAVEO({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
.EMIOUART0CTSN(UART0_CTSN),
.EMIOUART0DCDN(UART0_DCDN),
.EMIOUART0DSRN(UART0_DSRN),
.EMIOUART0DTRN(UART0_DTRN),
.EMIOUART0RIN(UART0_RIN),
.EMIOUART0RTSN(UART0_RTSN),
.EMIOUART0RX(UART0_RX),
.EMIOUART0TX(UART0_TX),
.EMIOUART1CTSN(UART1_CTSN),
.EMIOUART1DCDN(UART1_DCDN),
.EMIOUART1DSRN(UART1_DSRN),
.EMIOUART1DTRN(UART1_DTRN),
.EMIOUART1RIN(UART1_RIN),
.EMIOUART1RTSN(UART1_RTSN),
.EMIOUART1RX(UART1_RX),
.EMIOUART1TX(UART1_TX),
.EMIOUSB0PORTINDCTL(USB0_PORT_INDCTL),
.EMIOUSB0VBUSPWRFAULT(USB0_VBUS_PWRFAULT),
.EMIOUSB0VBUSPWRSELECT(USB0_VBUS_PWRSELECT),
.EMIOUSB1PORTINDCTL(USB1_PORT_INDCTL),
.EMIOUSB1VBUSPWRFAULT(USB1_VBUS_PWRFAULT),
.EMIOUSB1VBUSPWRSELECT(USB1_VBUS_PWRSELECT),
.EMIOWDTCLKI(WDT_CLK_IN),
.EMIOWDTRSTO(WDT_RST_OUT),
.EVENTEVENTI(EVENT_EVENTI),
.EVENTEVENTO(EVENT_EVENTO),
.EVENTSTANDBYWFE(EVENT_STANDBYWFE),
.EVENTSTANDBYWFI(EVENT_STANDBYWFI),
.FCLKCLK({FCLK_CLK3,FCLK_CLK2,FCLK_CLK1,FCLK_CLK_unbuffered}),
.FCLKCLKTRIGN({1'b0,1'b0,1'b0,1'b0}),
.FCLKRESETN({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
.FPGAIDLEN(FPGA_IDLE_N),
.FTMDTRACEINATID({1'b0,1'b0,1'b0,1'b0}),
.FTMDTRACEINCLOCK(FTMD_TRACEIN_CLK),
.FTMDTRACEINDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.FTMDTRACEINVALID(1'b0),
.FTMTF2PDEBUG(FTMT_F2P_DEBUG),
.FTMTF2PTRIG({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
.FTMTF2PTRIGACK({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
.FTMTP2FDEBUG(FTMT_P2F_DEBUG),
.FTMTP2FTRIG({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
.FTMTP2FTRIGACK({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
.IRQF2P({Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,IRQ_F2P}),
.IRQP2F({IRQ_P2F_DMAC_ABORT,IRQ_P2F_DMAC7,IRQ_P2F_DMAC6,IRQ_P2F_DMAC5,IRQ_P2F_DMAC4,IRQ_P2F_DMAC3,IRQ_P2F_DMAC2,IRQ_P2F_DMAC1,IRQ_P2F_DMAC0,IRQ_P2F_SMC,IRQ_P2F_QSPI,IRQ_P2F_CTI,IRQ_P2F_GPIO,IRQ_P2F_USB0,IRQ_P2F_ENET0,IRQ_P2F_ENET_WAKE0,IRQ_P2F_SDIO0,IRQ_P2F_I2C0,IRQ_P2F_SPI0,IRQ_P2F_UART0,IRQ_P2F_CAN0,IRQ_P2F_USB1,IRQ_P2F_ENET1,IRQ_P2F_ENET_WAKE1,IRQ_P2F_SDIO1,IRQ_P2F_I2C1,IRQ_P2F_SPI1,IRQ_P2F_UART1,IRQ_P2F_CAN1}),
.MAXIGP0ACLK(M_AXI_GP0_ACLK),
.MAXIGP0ARADDR(M_AXI_GP0_ARADDR),
.MAXIGP0ARBURST(M_AXI_GP0_ARBURST),
.MAXIGP0ARCACHE(\^M_AXI_GP0_ARCACHE ),
.MAXIGP0ARESETN(M_AXI_GP0_ARESETN),
.MAXIGP0ARID(M_AXI_GP0_ARID),
.MAXIGP0ARLEN(M_AXI_GP0_ARLEN),
.MAXIGP0ARLOCK(M_AXI_GP0_ARLOCK),
.MAXIGP0ARPROT(M_AXI_GP0_ARPROT),
.MAXIGP0ARQOS(M_AXI_GP0_ARQOS),
.MAXIGP0ARREADY(M_AXI_GP0_ARREADY),
.MAXIGP0ARSIZE(\^M_AXI_GP0_ARSIZE ),
.MAXIGP0ARVALID(M_AXI_GP0_ARVALID),
.MAXIGP0AWADDR(M_AXI_GP0_AWADDR),
.MAXIGP0AWBURST(M_AXI_GP0_AWBURST),
.MAXIGP0AWCACHE(\^M_AXI_GP0_AWCACHE ),
.MAXIGP0AWID(M_AXI_GP0_AWID),
.MAXIGP0AWLEN(M_AXI_GP0_AWLEN),
.MAXIGP0AWLOCK(M_AXI_GP0_AWLOCK),
.MAXIGP0AWPROT(M_AXI_GP0_AWPROT),
.MAXIGP0AWQOS(M_AXI_GP0_AWQOS),
.MAXIGP0AWREADY(M_AXI_GP0_AWREADY),
.MAXIGP0AWSIZE(\^M_AXI_GP0_AWSIZE ),
.MAXIGP0AWVALID(M_AXI_GP0_AWVALID),
.MAXIGP0BID(M_AXI_GP0_BID),
.MAXIGP0BREADY(M_AXI_GP0_BREADY),
.MAXIGP0BRESP(M_AXI_GP0_BRESP),
.MAXIGP0BVALID(M_AXI_GP0_BVALID),
.MAXIGP0RDATA(M_AXI_GP0_RDATA),
.MAXIGP0RID(M_AXI_GP0_RID),
.MAXIGP0RLAST(M_AXI_GP0_RLAST),
.MAXIGP0RREADY(M_AXI_GP0_RREADY),
.MAXIGP0RRESP(M_AXI_GP0_RRESP),
.MAXIGP0RVALID(M_AXI_GP0_RVALID),
.MAXIGP0WDATA(M_AXI_GP0_WDATA),
.MAXIGP0WID(M_AXI_GP0_WID),
.MAXIGP0WLAST(M_AXI_GP0_WLAST),
.MAXIGP0WREADY(M_AXI_GP0_WREADY),
.MAXIGP0WSTRB(M_AXI_GP0_WSTRB),
.MAXIGP0WVALID(M_AXI_GP0_WVALID),
.MAXIGP1ACLK(M_AXI_GP1_ACLK),
.MAXIGP1ARADDR(M_AXI_GP1_ARADDR),
.MAXIGP1ARBURST(M_AXI_GP1_ARBURST),
.MAXIGP1ARCACHE(\^M_AXI_GP1_ARCACHE ),
.MAXIGP1ARESETN(M_AXI_GP1_ARESETN),
.MAXIGP1ARID(M_AXI_GP1_ARID),
.MAXIGP1ARLEN(M_AXI_GP1_ARLEN),
.MAXIGP1ARLOCK(M_AXI_GP1_ARLOCK),
.MAXIGP1ARPROT(M_AXI_GP1_ARPROT),
.MAXIGP1ARQOS(M_AXI_GP1_ARQOS),
.MAXIGP1ARREADY(M_AXI_GP1_ARREADY),
.MAXIGP1ARSIZE(\^M_AXI_GP1_ARSIZE ),
.MAXIGP1ARVALID(M_AXI_GP1_ARVALID),
.MAXIGP1AWADDR(M_AXI_GP1_AWADDR),
.MAXIGP1AWBURST(M_AXI_GP1_AWBURST),
.MAXIGP1AWCACHE(\^M_AXI_GP1_AWCACHE ),
.MAXIGP1AWID(M_AXI_GP1_AWID),
.MAXIGP1AWLEN(M_AXI_GP1_AWLEN),
.MAXIGP1AWLOCK(M_AXI_GP1_AWLOCK),
.MAXIGP1AWPROT(M_AXI_GP1_AWPROT),
.MAXIGP1AWQOS(M_AXI_GP1_AWQOS),
.MAXIGP1AWREADY(M_AXI_GP1_AWREADY),
.MAXIGP1AWSIZE(\^M_AXI_GP1_AWSIZE ),
.MAXIGP1AWVALID(M_AXI_GP1_AWVALID),
.MAXIGP1BID(M_AXI_GP1_BID),
.MAXIGP1BREADY(M_AXI_GP1_BREADY),
.MAXIGP1BRESP(M_AXI_GP1_BRESP),
.MAXIGP1BVALID(M_AXI_GP1_BVALID),
.MAXIGP1RDATA(M_AXI_GP1_RDATA),
.MAXIGP1RID(M_AXI_GP1_RID),
.MAXIGP1RLAST(M_AXI_GP1_RLAST),
.MAXIGP1RREADY(M_AXI_GP1_RREADY),
.MAXIGP1RRESP(M_AXI_GP1_RRESP),
.MAXIGP1RVALID(M_AXI_GP1_RVALID),
.MAXIGP1WDATA(M_AXI_GP1_WDATA),
.MAXIGP1WID(M_AXI_GP1_WID),
.MAXIGP1WLAST(M_AXI_GP1_WLAST),
.MAXIGP1WREADY(M_AXI_GP1_WREADY),
.MAXIGP1WSTRB(M_AXI_GP1_WSTRB),
.MAXIGP1WVALID(M_AXI_GP1_WVALID),
.MIO(buffered_MIO),
.PSCLK(buffered_PS_CLK),
.PSPORB(buffered_PS_PORB),
.PSSRSTB(buffered_PS_SRSTB),
.SAXIACPACLK(S_AXI_ACP_ACLK),
.SAXIACPARADDR(S_AXI_ACP_ARADDR),
.SAXIACPARBURST(S_AXI_ACP_ARBURST),
.SAXIACPARCACHE(S_AXI_ACP_ARCACHE),
.SAXIACPARESETN(S_AXI_ACP_ARESETN),
.SAXIACPARID(S_AXI_ACP_ARID),
.SAXIACPARLEN(S_AXI_ACP_ARLEN),
.SAXIACPARLOCK(S_AXI_ACP_ARLOCK),
.SAXIACPARPROT(S_AXI_ACP_ARPROT),
.SAXIACPARQOS(S_AXI_ACP_ARQOS),
.SAXIACPARREADY(S_AXI_ACP_ARREADY),
.SAXIACPARSIZE(S_AXI_ACP_ARSIZE[1:0]),
.SAXIACPARUSER(S_AXI_ACP_ARUSER),
.SAXIACPARVALID(S_AXI_ACP_ARVALID),
.SAXIACPAWADDR(S_AXI_ACP_AWADDR),
.SAXIACPAWBURST(S_AXI_ACP_AWBURST),
.SAXIACPAWCACHE(S_AXI_ACP_AWCACHE),
.SAXIACPAWID(S_AXI_ACP_AWID),
.SAXIACPAWLEN(S_AXI_ACP_AWLEN),
.SAXIACPAWLOCK(S_AXI_ACP_AWLOCK),
.SAXIACPAWPROT(S_AXI_ACP_AWPROT),
.SAXIACPAWQOS(S_AXI_ACP_AWQOS),
.SAXIACPAWREADY(S_AXI_ACP_AWREADY),
.SAXIACPAWSIZE(S_AXI_ACP_AWSIZE[1:0]),
.SAXIACPAWUSER(S_AXI_ACP_AWUSER),
.SAXIACPAWVALID(S_AXI_ACP_AWVALID),
.SAXIACPBID(S_AXI_ACP_BID),
.SAXIACPBREADY(S_AXI_ACP_BREADY),
.SAXIACPBRESP(S_AXI_ACP_BRESP),
.SAXIACPBVALID(S_AXI_ACP_BVALID),
.SAXIACPRDATA(S_AXI_ACP_RDATA),
.SAXIACPRID(S_AXI_ACP_RID),
.SAXIACPRLAST(S_AXI_ACP_RLAST),
.SAXIACPRREADY(S_AXI_ACP_RREADY),
.SAXIACPRRESP(S_AXI_ACP_RRESP),
.SAXIACPRVALID(S_AXI_ACP_RVALID),
.SAXIACPWDATA(S_AXI_ACP_WDATA),
.SAXIACPWID(S_AXI_ACP_WID),
.SAXIACPWLAST(S_AXI_ACP_WLAST),
.SAXIACPWREADY(S_AXI_ACP_WREADY),
.SAXIACPWSTRB(S_AXI_ACP_WSTRB),
.SAXIACPWVALID(S_AXI_ACP_WVALID),
.SAXIGP0ACLK(S_AXI_GP0_ACLK),
.SAXIGP0ARADDR(S_AXI_GP0_ARADDR),
.SAXIGP0ARBURST(S_AXI_GP0_ARBURST),
.SAXIGP0ARCACHE(S_AXI_GP0_ARCACHE),
.SAXIGP0ARESETN(S_AXI_GP0_ARESETN),
.SAXIGP0ARID(S_AXI_GP0_ARID),
.SAXIGP0ARLEN(S_AXI_GP0_ARLEN),
.SAXIGP0ARLOCK(S_AXI_GP0_ARLOCK),
.SAXIGP0ARPROT(S_AXI_GP0_ARPROT),
.SAXIGP0ARQOS(S_AXI_GP0_ARQOS),
.SAXIGP0ARREADY(S_AXI_GP0_ARREADY),
.SAXIGP0ARSIZE(S_AXI_GP0_ARSIZE[1:0]),
.SAXIGP0ARVALID(S_AXI_GP0_ARVALID),
.SAXIGP0AWADDR(S_AXI_GP0_AWADDR),
.SAXIGP0AWBURST(S_AXI_GP0_AWBURST),
.SAXIGP0AWCACHE(S_AXI_GP0_AWCACHE),
.SAXIGP0AWID(S_AXI_GP0_AWID),
.SAXIGP0AWLEN(S_AXI_GP0_AWLEN),
.SAXIGP0AWLOCK(S_AXI_GP0_AWLOCK),
.SAXIGP0AWPROT(S_AXI_GP0_AWPROT),
.SAXIGP0AWQOS(S_AXI_GP0_AWQOS),
.SAXIGP0AWREADY(S_AXI_GP0_AWREADY),
.SAXIGP0AWSIZE(S_AXI_GP0_AWSIZE[1:0]),
.SAXIGP0AWVALID(S_AXI_GP0_AWVALID),
.SAXIGP0BID(S_AXI_GP0_BID),
.SAXIGP0BREADY(S_AXI_GP0_BREADY),
.SAXIGP0BRESP(S_AXI_GP0_BRESP),
.SAXIGP0BVALID(S_AXI_GP0_BVALID),
.SAXIGP0RDATA(S_AXI_GP0_RDATA),
.SAXIGP0RID(S_AXI_GP0_RID),
.SAXIGP0RLAST(S_AXI_GP0_RLAST),
.SAXIGP0RREADY(S_AXI_GP0_RREADY),
.SAXIGP0RRESP(S_AXI_GP0_RRESP),
.SAXIGP0RVALID(S_AXI_GP0_RVALID),
.SAXIGP0WDATA(S_AXI_GP0_WDATA),
.SAXIGP0WID(S_AXI_GP0_WID),
.SAXIGP0WLAST(S_AXI_GP0_WLAST),
.SAXIGP0WREADY(S_AXI_GP0_WREADY),
.SAXIGP0WSTRB(S_AXI_GP0_WSTRB),
.SAXIGP0WVALID(S_AXI_GP0_WVALID),
.SAXIGP1ACLK(S_AXI_GP1_ACLK),
.SAXIGP1ARADDR(S_AXI_GP1_ARADDR),
.SAXIGP1ARBURST(S_AXI_GP1_ARBURST),
.SAXIGP1ARCACHE(S_AXI_GP1_ARCACHE),
.SAXIGP1ARESETN(S_AXI_GP1_ARESETN),
.SAXIGP1ARID(S_AXI_GP1_ARID),
.SAXIGP1ARLEN(S_AXI_GP1_ARLEN),
.SAXIGP1ARLOCK(S_AXI_GP1_ARLOCK),
.SAXIGP1ARPROT(S_AXI_GP1_ARPROT),
.SAXIGP1ARQOS(S_AXI_GP1_ARQOS),
.SAXIGP1ARREADY(S_AXI_GP1_ARREADY),
.SAXIGP1ARSIZE(S_AXI_GP1_ARSIZE[1:0]),
.SAXIGP1ARVALID(S_AXI_GP1_ARVALID),
.SAXIGP1AWADDR(S_AXI_GP1_AWADDR),
.SAXIGP1AWBURST(S_AXI_GP1_AWBURST),
.SAXIGP1AWCACHE(S_AXI_GP1_AWCACHE),
.SAXIGP1AWID(S_AXI_GP1_AWID),
.SAXIGP1AWLEN(S_AXI_GP1_AWLEN),
.SAXIGP1AWLOCK(S_AXI_GP1_AWLOCK),
.SAXIGP1AWPROT(S_AXI_GP1_AWPROT),
.SAXIGP1AWQOS(S_AXI_GP1_AWQOS),
.SAXIGP1AWREADY(S_AXI_GP1_AWREADY),
.SAXIGP1AWSIZE(S_AXI_GP1_AWSIZE[1:0]),
.SAXIGP1AWVALID(S_AXI_GP1_AWVALID),
.SAXIGP1BID(S_AXI_GP1_BID),
.SAXIGP1BREADY(S_AXI_GP1_BREADY),
.SAXIGP1BRESP(S_AXI_GP1_BRESP),
.SAXIGP1BVALID(S_AXI_GP1_BVALID),
.SAXIGP1RDATA(S_AXI_GP1_RDATA),
.SAXIGP1RID(S_AXI_GP1_RID),
.SAXIGP1RLAST(S_AXI_GP1_RLAST),
.SAXIGP1RREADY(S_AXI_GP1_RREADY),
.SAXIGP1RRESP(S_AXI_GP1_RRESP),
.SAXIGP1RVALID(S_AXI_GP1_RVALID),
.SAXIGP1WDATA(S_AXI_GP1_WDATA),
.SAXIGP1WID(S_AXI_GP1_WID),
.SAXIGP1WLAST(S_AXI_GP1_WLAST),
.SAXIGP1WREADY(S_AXI_GP1_WREADY),
.SAXIGP1WSTRB(S_AXI_GP1_WSTRB),
.SAXIGP1WVALID(S_AXI_GP1_WVALID),
.SAXIHP0ACLK(S_AXI_HP0_ACLK),
.SAXIHP0ARADDR(S_AXI_HP0_ARADDR),
.SAXIHP0ARBURST(S_AXI_HP0_ARBURST),
.SAXIHP0ARCACHE(S_AXI_HP0_ARCACHE),
.SAXIHP0ARESETN(S_AXI_HP0_ARESETN),
.SAXIHP0ARID(S_AXI_HP0_ARID),
.SAXIHP0ARLEN(S_AXI_HP0_ARLEN),
.SAXIHP0ARLOCK(S_AXI_HP0_ARLOCK),
.SAXIHP0ARPROT(S_AXI_HP0_ARPROT),
.SAXIHP0ARQOS(S_AXI_HP0_ARQOS),
.SAXIHP0ARREADY(S_AXI_HP0_ARREADY),
.SAXIHP0ARSIZE(S_AXI_HP0_ARSIZE[1:0]),
.SAXIHP0ARVALID(S_AXI_HP0_ARVALID),
.SAXIHP0AWADDR(S_AXI_HP0_AWADDR),
.SAXIHP0AWBURST(S_AXI_HP0_AWBURST),
.SAXIHP0AWCACHE(S_AXI_HP0_AWCACHE),
.SAXIHP0AWID(S_AXI_HP0_AWID),
.SAXIHP0AWLEN(S_AXI_HP0_AWLEN),
.SAXIHP0AWLOCK(S_AXI_HP0_AWLOCK),
.SAXIHP0AWPROT(S_AXI_HP0_AWPROT),
.SAXIHP0AWQOS(S_AXI_HP0_AWQOS),
.SAXIHP0AWREADY(S_AXI_HP0_AWREADY),
.SAXIHP0AWSIZE(S_AXI_HP0_AWSIZE[1:0]),
.SAXIHP0AWVALID(S_AXI_HP0_AWVALID),
.SAXIHP0BID(S_AXI_HP0_BID),
.SAXIHP0BREADY(S_AXI_HP0_BREADY),
.SAXIHP0BRESP(S_AXI_HP0_BRESP),
.SAXIHP0BVALID(S_AXI_HP0_BVALID),
.SAXIHP0RACOUNT(S_AXI_HP0_RACOUNT),
.SAXIHP0RCOUNT(S_AXI_HP0_RCOUNT),
.SAXIHP0RDATA(S_AXI_HP0_RDATA),
.SAXIHP0RDISSUECAP1EN(S_AXI_HP0_RDISSUECAP1_EN),
.SAXIHP0RID(S_AXI_HP0_RID),
.SAXIHP0RLAST(S_AXI_HP0_RLAST),
.SAXIHP0RREADY(S_AXI_HP0_RREADY),
.SAXIHP0RRESP(S_AXI_HP0_RRESP),
.SAXIHP0RVALID(S_AXI_HP0_RVALID),
.SAXIHP0WACOUNT(S_AXI_HP0_WACOUNT),
.SAXIHP0WCOUNT(S_AXI_HP0_WCOUNT),
.SAXIHP0WDATA(S_AXI_HP0_WDATA),
.SAXIHP0WID(S_AXI_HP0_WID),
.SAXIHP0WLAST(S_AXI_HP0_WLAST),
.SAXIHP0WREADY(S_AXI_HP0_WREADY),
.SAXIHP0WRISSUECAP1EN(S_AXI_HP0_WRISSUECAP1_EN),
.SAXIHP0WSTRB(S_AXI_HP0_WSTRB),
.SAXIHP0WVALID(S_AXI_HP0_WVALID),
.SAXIHP1ACLK(S_AXI_HP1_ACLK),
.SAXIHP1ARADDR(S_AXI_HP1_ARADDR),
.SAXIHP1ARBURST(S_AXI_HP1_ARBURST),
.SAXIHP1ARCACHE(S_AXI_HP1_ARCACHE),
.SAXIHP1ARESETN(S_AXI_HP1_ARESETN),
.SAXIHP1ARID(S_AXI_HP1_ARID),
.SAXIHP1ARLEN(S_AXI_HP1_ARLEN),
.SAXIHP1ARLOCK(S_AXI_HP1_ARLOCK),
.SAXIHP1ARPROT(S_AXI_HP1_ARPROT),
.SAXIHP1ARQOS(S_AXI_HP1_ARQOS),
.SAXIHP1ARREADY(S_AXI_HP1_ARREADY),
.SAXIHP1ARSIZE(S_AXI_HP1_ARSIZE[1:0]),
.SAXIHP1ARVALID(S_AXI_HP1_ARVALID),
.SAXIHP1AWADDR(S_AXI_HP1_AWADDR),
.SAXIHP1AWBURST(S_AXI_HP1_AWBURST),
.SAXIHP1AWCACHE(S_AXI_HP1_AWCACHE),
.SAXIHP1AWID(S_AXI_HP1_AWID),
.SAXIHP1AWLEN(S_AXI_HP1_AWLEN),
.SAXIHP1AWLOCK(S_AXI_HP1_AWLOCK),
.SAXIHP1AWPROT(S_AXI_HP1_AWPROT),
.SAXIHP1AWQOS(S_AXI_HP1_AWQOS),
.SAXIHP1AWREADY(S_AXI_HP1_AWREADY),
.SAXIHP1AWSIZE(S_AXI_HP1_AWSIZE[1:0]),
.SAXIHP1AWVALID(S_AXI_HP1_AWVALID),
.SAXIHP1BID(S_AXI_HP1_BID),
.SAXIHP1BREADY(S_AXI_HP1_BREADY),
.SAXIHP1BRESP(S_AXI_HP1_BRESP),
.SAXIHP1BVALID(S_AXI_HP1_BVALID),
.SAXIHP1RACOUNT(S_AXI_HP1_RACOUNT),
.SAXIHP1RCOUNT(S_AXI_HP1_RCOUNT),
.SAXIHP1RDATA(S_AXI_HP1_RDATA),
.SAXIHP1RDISSUECAP1EN(S_AXI_HP1_RDISSUECAP1_EN),
.SAXIHP1RID(S_AXI_HP1_RID),
.SAXIHP1RLAST(S_AXI_HP1_RLAST),
.SAXIHP1RREADY(S_AXI_HP1_RREADY),
.SAXIHP1RRESP(S_AXI_HP1_RRESP),
.SAXIHP1RVALID(S_AXI_HP1_RVALID),
.SAXIHP1WACOUNT(S_AXI_HP1_WACOUNT),
.SAXIHP1WCOUNT(S_AXI_HP1_WCOUNT),
.SAXIHP1WDATA(S_AXI_HP1_WDATA),
.SAXIHP1WID(S_AXI_HP1_WID),
.SAXIHP1WLAST(S_AXI_HP1_WLAST),
.SAXIHP1WREADY(S_AXI_HP1_WREADY),
.SAXIHP1WRISSUECAP1EN(S_AXI_HP1_WRISSUECAP1_EN),
.SAXIHP1WSTRB(S_AXI_HP1_WSTRB),
.SAXIHP1WVALID(S_AXI_HP1_WVALID),
.SAXIHP2ACLK(S_AXI_HP2_ACLK),
.SAXIHP2ARADDR(S_AXI_HP2_ARADDR),
.SAXIHP2ARBURST(S_AXI_HP2_ARBURST),
.SAXIHP2ARCACHE(S_AXI_HP2_ARCACHE),
.SAXIHP2ARESETN(S_AXI_HP2_ARESETN),
.SAXIHP2ARID(S_AXI_HP2_ARID),
.SAXIHP2ARLEN(S_AXI_HP2_ARLEN),
.SAXIHP2ARLOCK(S_AXI_HP2_ARLOCK),
.SAXIHP2ARPROT(S_AXI_HP2_ARPROT),
.SAXIHP2ARQOS(S_AXI_HP2_ARQOS),
.SAXIHP2ARREADY(S_AXI_HP2_ARREADY),
.SAXIHP2ARSIZE(S_AXI_HP2_ARSIZE[1:0]),
.SAXIHP2ARVALID(S_AXI_HP2_ARVALID),
.SAXIHP2AWADDR(S_AXI_HP2_AWADDR),
.SAXIHP2AWBURST(S_AXI_HP2_AWBURST),
.SAXIHP2AWCACHE(S_AXI_HP2_AWCACHE),
.SAXIHP2AWID(S_AXI_HP2_AWID),
.SAXIHP2AWLEN(S_AXI_HP2_AWLEN),
.SAXIHP2AWLOCK(S_AXI_HP2_AWLOCK),
.SAXIHP2AWPROT(S_AXI_HP2_AWPROT),
.SAXIHP2AWQOS(S_AXI_HP2_AWQOS),
.SAXIHP2AWREADY(S_AXI_HP2_AWREADY),
.SAXIHP2AWSIZE(S_AXI_HP2_AWSIZE[1:0]),
.SAXIHP2AWVALID(S_AXI_HP2_AWVALID),
.SAXIHP2BID(S_AXI_HP2_BID),
.SAXIHP2BREADY(S_AXI_HP2_BREADY),
.SAXIHP2BRESP(S_AXI_HP2_BRESP),
.SAXIHP2BVALID(S_AXI_HP2_BVALID),
.SAXIHP2RACOUNT(S_AXI_HP2_RACOUNT),
.SAXIHP2RCOUNT(S_AXI_HP2_RCOUNT),
.SAXIHP2RDATA(S_AXI_HP2_RDATA),
.SAXIHP2RDISSUECAP1EN(S_AXI_HP2_RDISSUECAP1_EN),
.SAXIHP2RID(S_AXI_HP2_RID),
.SAXIHP2RLAST(S_AXI_HP2_RLAST),
.SAXIHP2RREADY(S_AXI_HP2_RREADY),
.SAXIHP2RRESP(S_AXI_HP2_RRESP),
.SAXIHP2RVALID(S_AXI_HP2_RVALID),
.SAXIHP2WACOUNT(S_AXI_HP2_WACOUNT),
.SAXIHP2WCOUNT(S_AXI_HP2_WCOUNT),
.SAXIHP2WDATA(S_AXI_HP2_WDATA),
.SAXIHP2WID(S_AXI_HP2_WID),
.SAXIHP2WLAST(S_AXI_HP2_WLAST),
.SAXIHP2WREADY(S_AXI_HP2_WREADY),
.SAXIHP2WRISSUECAP1EN(S_AXI_HP2_WRISSUECAP1_EN),
.SAXIHP2WSTRB(S_AXI_HP2_WSTRB),
.SAXIHP2WVALID(S_AXI_HP2_WVALID),
.SAXIHP3ACLK(S_AXI_HP3_ACLK),
.SAXIHP3ARADDR(S_AXI_HP3_ARADDR),
.SAXIHP3ARBURST(S_AXI_HP3_ARBURST),
.SAXIHP3ARCACHE(S_AXI_HP3_ARCACHE),
.SAXIHP3ARESETN(S_AXI_HP3_ARESETN),
.SAXIHP3ARID(S_AXI_HP3_ARID),
.SAXIHP3ARLEN(S_AXI_HP3_ARLEN),
.SAXIHP3ARLOCK(S_AXI_HP3_ARLOCK),
.SAXIHP3ARPROT(S_AXI_HP3_ARPROT),
.SAXIHP3ARQOS(S_AXI_HP3_ARQOS),
.SAXIHP3ARREADY(S_AXI_HP3_ARREADY),
.SAXIHP3ARSIZE(S_AXI_HP3_ARSIZE[1:0]),
.SAXIHP3ARVALID(S_AXI_HP3_ARVALID),
.SAXIHP3AWADDR(S_AXI_HP3_AWADDR),
.SAXIHP3AWBURST(S_AXI_HP3_AWBURST),
.SAXIHP3AWCACHE(S_AXI_HP3_AWCACHE),
.SAXIHP3AWID(S_AXI_HP3_AWID),
.SAXIHP3AWLEN(S_AXI_HP3_AWLEN),
.SAXIHP3AWLOCK(S_AXI_HP3_AWLOCK),
.SAXIHP3AWPROT(S_AXI_HP3_AWPROT),
.SAXIHP3AWQOS(S_AXI_HP3_AWQOS),
.SAXIHP3AWREADY(S_AXI_HP3_AWREADY),
.SAXIHP3AWSIZE(S_AXI_HP3_AWSIZE[1:0]),
.SAXIHP3AWVALID(S_AXI_HP3_AWVALID),
.SAXIHP3BID(S_AXI_HP3_BID),
.SAXIHP3BREADY(S_AXI_HP3_BREADY),
.SAXIHP3BRESP(S_AXI_HP3_BRESP),
.SAXIHP3BVALID(S_AXI_HP3_BVALID),
.SAXIHP3RACOUNT(S_AXI_HP3_RACOUNT),
.SAXIHP3RCOUNT(S_AXI_HP3_RCOUNT),
.SAXIHP3RDATA(S_AXI_HP3_RDATA),
.SAXIHP3RDISSUECAP1EN(S_AXI_HP3_RDISSUECAP1_EN),
.SAXIHP3RID(S_AXI_HP3_RID),
.SAXIHP3RLAST(S_AXI_HP3_RLAST),
.SAXIHP3RREADY(S_AXI_HP3_RREADY),
.SAXIHP3RRESP(S_AXI_HP3_RRESP),
.SAXIHP3RVALID(S_AXI_HP3_RVALID),
.SAXIHP3WACOUNT(S_AXI_HP3_WACOUNT),
.SAXIHP3WCOUNT(S_AXI_HP3_WCOUNT),
.SAXIHP3WDATA(S_AXI_HP3_WDATA),
.SAXIHP3WID(S_AXI_HP3_WID),
.SAXIHP3WLAST(S_AXI_HP3_WLAST),
.SAXIHP3WREADY(S_AXI_HP3_WREADY),
.SAXIHP3WRISSUECAP1EN(S_AXI_HP3_WRISSUECAP1_EN),
.SAXIHP3WSTRB(S_AXI_HP3_WSTRB),
.SAXIHP3WVALID(S_AXI_HP3_WVALID));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF PS_CLK_BIBUF
(.IO(buffered_PS_CLK),
.PAD(PS_CLK));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF PS_PORB_BIBUF
(.IO(buffered_PS_PORB),
.PAD(PS_PORB));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF PS_SRSTB_BIBUF
(.IO(buffered_PS_SRSTB),
.PAD(PS_SRSTB));
LUT1 #(
.INIT(2'h1))
SDIO0_CMD_T_INST_0
(.I0(SDIO0_CMD_T_n),
.O(SDIO0_CMD_T));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[0]_INST_0
(.I0(SDIO0_DATA_T_n[0]),
.O(SDIO0_DATA_T[0]));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[1]_INST_0
(.I0(SDIO0_DATA_T_n[1]),
.O(SDIO0_DATA_T[1]));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[2]_INST_0
(.I0(SDIO0_DATA_T_n[2]),
.O(SDIO0_DATA_T[2]));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[3]_INST_0
(.I0(SDIO0_DATA_T_n[3]),
.O(SDIO0_DATA_T[3]));
LUT1 #(
.INIT(2'h1))
SDIO1_CMD_T_INST_0
(.I0(SDIO1_CMD_T_n),
.O(SDIO1_CMD_T));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[0]_INST_0
(.I0(SDIO1_DATA_T_n[0]),
.O(SDIO1_DATA_T[0]));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[1]_INST_0
(.I0(SDIO1_DATA_T_n[1]),
.O(SDIO1_DATA_T[1]));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[2]_INST_0
(.I0(SDIO1_DATA_T_n[2]),
.O(SDIO1_DATA_T[2]));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[3]_INST_0
(.I0(SDIO1_DATA_T_n[3]),
.O(SDIO1_DATA_T[3]));
LUT1 #(
.INIT(2'h1))
SPI0_MISO_T_INST_0
(.I0(SPI0_MISO_T_n),
.O(SPI0_MISO_T));
LUT1 #(
.INIT(2'h1))
SPI0_MOSI_T_INST_0
(.I0(SPI0_MOSI_T_n),
.O(SPI0_MOSI_T));
LUT1 #(
.INIT(2'h1))
SPI0_SCLK_T_INST_0
(.I0(SPI0_SCLK_T_n),
.O(SPI0_SCLK_T));
LUT1 #(
.INIT(2'h1))
SPI0_SS_T_INST_0
(.I0(SPI0_SS_T_n),
.O(SPI0_SS_T));
LUT1 #(
.INIT(2'h1))
SPI1_MISO_T_INST_0
(.I0(SPI1_MISO_T_n),
.O(SPI1_MISO_T));
LUT1 #(
.INIT(2'h1))
SPI1_MOSI_T_INST_0
(.I0(SPI1_MOSI_T_n),
.O(SPI1_MOSI_T));
LUT1 #(
.INIT(2'h1))
SPI1_SCLK_T_INST_0
(.I0(SPI1_SCLK_T_n),
.O(SPI1_SCLK_T));
LUT1 #(
.INIT(2'h1))
SPI1_SS_T_INST_0
(.I0(SPI1_SS_T_n),
.O(SPI1_SS_T));
VCC VCC
(.P(\<const1> ));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG \buffer_fclk_clk_0.FCLK_CLK_0_BUFG
(.I(FCLK_CLK_unbuffered),
.O(FCLK_CLK0));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[0].MIO_BIBUF
(.IO(buffered_MIO[0]),
.PAD(MIO[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[10].MIO_BIBUF
(.IO(buffered_MIO[10]),
.PAD(MIO[10]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[11].MIO_BIBUF
(.IO(buffered_MIO[11]),
.PAD(MIO[11]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[12].MIO_BIBUF
(.IO(buffered_MIO[12]),
.PAD(MIO[12]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[13].MIO_BIBUF
(.IO(buffered_MIO[13]),
.PAD(MIO[13]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[14].MIO_BIBUF
(.IO(buffered_MIO[14]),
.PAD(MIO[14]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[15].MIO_BIBUF
(.IO(buffered_MIO[15]),
.PAD(MIO[15]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[16].MIO_BIBUF
(.IO(buffered_MIO[16]),
.PAD(MIO[16]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[17].MIO_BIBUF
(.IO(buffered_MIO[17]),
.PAD(MIO[17]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[18].MIO_BIBUF
(.IO(buffered_MIO[18]),
.PAD(MIO[18]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[19].MIO_BIBUF
(.IO(buffered_MIO[19]),
.PAD(MIO[19]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[1].MIO_BIBUF
(.IO(buffered_MIO[1]),
.PAD(MIO[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[20].MIO_BIBUF
(.IO(buffered_MIO[20]),
.PAD(MIO[20]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[21].MIO_BIBUF
(.IO(buffered_MIO[21]),
.PAD(MIO[21]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[22].MIO_BIBUF
(.IO(buffered_MIO[22]),
.PAD(MIO[22]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[23].MIO_BIBUF
(.IO(buffered_MIO[23]),
.PAD(MIO[23]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[24].MIO_BIBUF
(.IO(buffered_MIO[24]),
.PAD(MIO[24]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[25].MIO_BIBUF
(.IO(buffered_MIO[25]),
.PAD(MIO[25]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[26].MIO_BIBUF
(.IO(buffered_MIO[26]),
.PAD(MIO[26]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[27].MIO_BIBUF
(.IO(buffered_MIO[27]),
.PAD(MIO[27]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[28].MIO_BIBUF
(.IO(buffered_MIO[28]),
.PAD(MIO[28]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[29].MIO_BIBUF
(.IO(buffered_MIO[29]),
.PAD(MIO[29]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[2].MIO_BIBUF
(.IO(buffered_MIO[2]),
.PAD(MIO[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[30].MIO_BIBUF
(.IO(buffered_MIO[30]),
.PAD(MIO[30]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[31].MIO_BIBUF
(.IO(buffered_MIO[31]),
.PAD(MIO[31]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[32].MIO_BIBUF
(.IO(buffered_MIO[32]),
.PAD(MIO[32]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[33].MIO_BIBUF
(.IO(buffered_MIO[33]),
.PAD(MIO[33]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[34].MIO_BIBUF
(.IO(buffered_MIO[34]),
.PAD(MIO[34]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[35].MIO_BIBUF
(.IO(buffered_MIO[35]),
.PAD(MIO[35]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[36].MIO_BIBUF
(.IO(buffered_MIO[36]),
.PAD(MIO[36]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[37].MIO_BIBUF
(.IO(buffered_MIO[37]),
.PAD(MIO[37]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[38].MIO_BIBUF
(.IO(buffered_MIO[38]),
.PAD(MIO[38]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[39].MIO_BIBUF
(.IO(buffered_MIO[39]),
.PAD(MIO[39]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[3].MIO_BIBUF
(.IO(buffered_MIO[3]),
.PAD(MIO[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[40].MIO_BIBUF
(.IO(buffered_MIO[40]),
.PAD(MIO[40]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[41].MIO_BIBUF
(.IO(buffered_MIO[41]),
.PAD(MIO[41]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[42].MIO_BIBUF
(.IO(buffered_MIO[42]),
.PAD(MIO[42]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[43].MIO_BIBUF
(.IO(buffered_MIO[43]),
.PAD(MIO[43]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[44].MIO_BIBUF
(.IO(buffered_MIO[44]),
.PAD(MIO[44]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[45].MIO_BIBUF
(.IO(buffered_MIO[45]),
.PAD(MIO[45]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[46].MIO_BIBUF
(.IO(buffered_MIO[46]),
.PAD(MIO[46]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[47].MIO_BIBUF
(.IO(buffered_MIO[47]),
.PAD(MIO[47]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[48].MIO_BIBUF
(.IO(buffered_MIO[48]),
.PAD(MIO[48]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[49].MIO_BIBUF
(.IO(buffered_MIO[49]),
.PAD(MIO[49]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[4].MIO_BIBUF
(.IO(buffered_MIO[4]),
.PAD(MIO[4]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[50].MIO_BIBUF
(.IO(buffered_MIO[50]),
.PAD(MIO[50]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[51].MIO_BIBUF
(.IO(buffered_MIO[51]),
.PAD(MIO[51]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[52].MIO_BIBUF
(.IO(buffered_MIO[52]),
.PAD(MIO[52]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[53].MIO_BIBUF
(.IO(buffered_MIO[53]),
.PAD(MIO[53]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[5].MIO_BIBUF
(.IO(buffered_MIO[5]),
.PAD(MIO[5]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[6].MIO_BIBUF
(.IO(buffered_MIO[6]),
.PAD(MIO[6]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[7].MIO_BIBUF
(.IO(buffered_MIO[7]),
.PAD(MIO[7]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[8].MIO_BIBUF
(.IO(buffered_MIO[8]),
.PAD(MIO[8]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[9].MIO_BIBUF
(.IO(buffered_MIO[9]),
.PAD(MIO[9]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk14[0].DDR_BankAddr_BIBUF
(.IO(buffered_DDR_BankAddr[0]),
.PAD(DDR_BankAddr[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk14[1].DDR_BankAddr_BIBUF
(.IO(buffered_DDR_BankAddr[1]),
.PAD(DDR_BankAddr[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk14[2].DDR_BankAddr_BIBUF
(.IO(buffered_DDR_BankAddr[2]),
.PAD(DDR_BankAddr[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[0].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[0]),
.PAD(DDR_Addr[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[10].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[10]),
.PAD(DDR_Addr[10]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[11].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[11]),
.PAD(DDR_Addr[11]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[12].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[12]),
.PAD(DDR_Addr[12]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[13].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[13]),
.PAD(DDR_Addr[13]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[14].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[14]),
.PAD(DDR_Addr[14]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[1].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[1]),
.PAD(DDR_Addr[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[2].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[2]),
.PAD(DDR_Addr[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[3].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[3]),
.PAD(DDR_Addr[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[4].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[4]),
.PAD(DDR_Addr[4]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[5].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[5]),
.PAD(DDR_Addr[5]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[6].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[6]),
.PAD(DDR_Addr[6]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[7].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[7]),
.PAD(DDR_Addr[7]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[8].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[8]),
.PAD(DDR_Addr[8]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[9].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[9]),
.PAD(DDR_Addr[9]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[0].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[0]),
.PAD(DDR_DM[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[1].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[1]),
.PAD(DDR_DM[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[2].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[2]),
.PAD(DDR_DM[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[3].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[3]),
.PAD(DDR_DM[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[0].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[0]),
.PAD(DDR_DQ[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[10].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[10]),
.PAD(DDR_DQ[10]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[11].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[11]),
.PAD(DDR_DQ[11]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[12].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[12]),
.PAD(DDR_DQ[12]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[13].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[13]),
.PAD(DDR_DQ[13]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[14].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[14]),
.PAD(DDR_DQ[14]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[15].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[15]),
.PAD(DDR_DQ[15]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[16].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[16]),
.PAD(DDR_DQ[16]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[17].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[17]),
.PAD(DDR_DQ[17]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[18].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[18]),
.PAD(DDR_DQ[18]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[19].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[19]),
.PAD(DDR_DQ[19]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[1].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[1]),
.PAD(DDR_DQ[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[20].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[20]),
.PAD(DDR_DQ[20]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[21].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[21]),
.PAD(DDR_DQ[21]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[22].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[22]),
.PAD(DDR_DQ[22]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[23].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[23]),
.PAD(DDR_DQ[23]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[24].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[24]),
.PAD(DDR_DQ[24]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[25].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[25]),
.PAD(DDR_DQ[25]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[26].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[26]),
.PAD(DDR_DQ[26]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[27].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[27]),
.PAD(DDR_DQ[27]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[28].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[28]),
.PAD(DDR_DQ[28]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[29].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[29]),
.PAD(DDR_DQ[29]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[2].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[2]),
.PAD(DDR_DQ[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[30].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[30]),
.PAD(DDR_DQ[30]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[31].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[31]),
.PAD(DDR_DQ[31]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[3].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[3]),
.PAD(DDR_DQ[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[4].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[4]),
.PAD(DDR_DQ[4]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[5].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[5]),
.PAD(DDR_DQ[5]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[6].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[6]),
.PAD(DDR_DQ[6]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[7].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[7]),
.PAD(DDR_DQ[7]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[8].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[8]),
.PAD(DDR_DQ[8]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[9].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[9]),
.PAD(DDR_DQ[9]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[0].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[0]),
.PAD(DDR_DQS_n[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[1].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[1]),
.PAD(DDR_DQS_n[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[2].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[2]),
.PAD(DDR_DQS_n[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[3].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[3]),
.PAD(DDR_DQS_n[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[0].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[0]),
.PAD(DDR_DQS[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[1].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[1]),
.PAD(DDR_DQS[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[2].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[2]),
.PAD(DDR_DQS[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[3].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[3]),
.PAD(DDR_DQS[3]));
LUT1 #(
.INIT(2'h2))
i_0
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[0] ));
LUT1 #(
.INIT(2'h2))
i_1
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[0] [1]));
LUT1 #(
.INIT(2'h2))
i_10
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[7] [1]));
LUT1 #(
.INIT(2'h2))
i_11
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[7] [0]));
LUT1 #(
.INIT(2'h2))
i_12
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[6] [1]));
LUT1 #(
.INIT(2'h2))
i_13
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[6] [0]));
LUT1 #(
.INIT(2'h2))
i_14
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[5] [1]));
LUT1 #(
.INIT(2'h2))
i_15
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[5] [0]));
LUT1 #(
.INIT(2'h2))
i_16
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[4] [1]));
LUT1 #(
.INIT(2'h2))
i_17
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[4] [0]));
LUT1 #(
.INIT(2'h2))
i_18
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[3] [1]));
LUT1 #(
.INIT(2'h2))
i_19
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[3] [0]));
LUT1 #(
.INIT(2'h2))
i_2
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[0] [0]));
LUT1 #(
.INIT(2'h2))
i_20
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[2] [1]));
LUT1 #(
.INIT(2'h2))
i_21
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[2] [0]));
LUT1 #(
.INIT(2'h2))
i_22
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[1] [1]));
LUT1 #(
.INIT(2'h2))
i_23
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[1] [0]));
LUT1 #(
.INIT(2'h2))
i_3
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[7] ));
LUT1 #(
.INIT(2'h2))
i_4
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[6] ));
LUT1 #(
.INIT(2'h2))
i_5
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[5] ));
LUT1 #(
.INIT(2'h2))
i_6
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[4] ));
LUT1 #(
.INIT(2'h2))
i_7
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[3] ));
LUT1 #(
.INIT(2'h2))
i_8
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[2] ));
LUT1 #(
.INIT(2'h2))
i_9
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[1] ));
endmodule
(* CHECK_LICENSE_TYPE = "zynq_design_1_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2017.2" *)
(* NotValidForBitStream *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT,
USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
FCLK_CLK0,
FCLK_RESET0_N,
FTMT_F2P_TRIG_0,
FTMT_F2P_TRIGACK_0,
FTMT_P2F_TRIGACK_0,
FTMT_P2F_TRIG_0,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB);
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 PORT_INDCTL" *) output [1:0]USB0_PORT_INDCTL;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRSELECT" *) output USB0_VBUS_PWRSELECT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRFAULT" *) input USB0_VBUS_PWRFAULT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARVALID" *) output M_AXI_GP0_ARVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWVALID" *) output M_AXI_GP0_AWVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BREADY" *) output M_AXI_GP0_BREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RREADY" *) output M_AXI_GP0_RREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WLAST" *) output M_AXI_GP0_WLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WVALID" *) output M_AXI_GP0_WVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARID" *) output [11:0]M_AXI_GP0_ARID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWID" *) output [11:0]M_AXI_GP0_AWID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WID" *) output [11:0]M_AXI_GP0_WID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST" *) output [1:0]M_AXI_GP0_ARBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLOCK" *) output [1:0]M_AXI_GP0_ARLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARSIZE" *) output [2:0]M_AXI_GP0_ARSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWBURST" *) output [1:0]M_AXI_GP0_AWBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLOCK" *) output [1:0]M_AXI_GP0_AWLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWSIZE" *) output [2:0]M_AXI_GP0_AWSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARPROT" *) output [2:0]M_AXI_GP0_ARPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWPROT" *) output [2:0]M_AXI_GP0_AWPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR" *) output [31:0]M_AXI_GP0_ARADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWADDR" *) output [31:0]M_AXI_GP0_AWADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WDATA" *) output [31:0]M_AXI_GP0_WDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARCACHE" *) output [3:0]M_AXI_GP0_ARCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLEN" *) output [3:0]M_AXI_GP0_ARLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARQOS" *) output [3:0]M_AXI_GP0_ARQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWCACHE" *) output [3:0]M_AXI_GP0_AWCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLEN" *) output [3:0]M_AXI_GP0_AWLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWQOS" *) output [3:0]M_AXI_GP0_AWQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB" *) output [3:0]M_AXI_GP0_WSTRB;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK" *) input M_AXI_GP0_ACLK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY" *) input M_AXI_GP0_ARREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY" *) input M_AXI_GP0_AWREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BVALID" *) input M_AXI_GP0_BVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RLAST" *) input M_AXI_GP0_RLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RVALID" *) input M_AXI_GP0_RVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WREADY" *) input M_AXI_GP0_WREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BID" *) input [11:0]M_AXI_GP0_BID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID" *) input [11:0]M_AXI_GP0_RID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP" *) input [1:0]M_AXI_GP0_BRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP" *) input [1:0]M_AXI_GP0_RRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA" *) input [31:0]M_AXI_GP0_RDATA;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK" *) output FCLK_CLK0;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST" *) output FCLK_RESET0_N;
(* X_INTERFACE_INFO = "xilinx.com:interface:trigger:1.0 TRIGGER_IN_0 TRIG" *) input FTMT_F2P_TRIG_0;
(* X_INTERFACE_INFO = "xilinx.com:interface:trigger:1.0 TRIGGER_IN_0 ACK" *) output FTMT_F2P_TRIGACK_0;
(* X_INTERFACE_INFO = "xilinx.com:interface:trigger:1.0 TRIGGER_OUT_0 ACK" *) input FTMT_P2F_TRIGACK_0;
(* X_INTERFACE_INFO = "xilinx.com:interface:trigger:1.0 TRIGGER_OUT_0 TRIG" *) output FTMT_P2F_TRIG_0;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *) inout [53:0]MIO;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *) inout DDR_CAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CKE" *) inout DDR_CKE;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_N" *) inout DDR_Clk_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_P" *) inout DDR_Clk;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CS_N" *) inout DDR_CS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RESET_N" *) inout DDR_DRSTB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ODT" *) inout DDR_ODT;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RAS_N" *) inout DDR_RAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR WE_N" *) inout DDR_WEB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR BA" *) inout [2:0]DDR_BankAddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ADDR" *) inout [14:0]DDR_Addr;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN" *) inout DDR_VRN;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP" *) inout DDR_VRP;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DM" *) inout [3:0]DDR_DM;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQ" *) inout [31:0]DDR_DQ;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_N" *) inout [3:0]DDR_DQS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_P" *) inout [3:0]DDR_DQS;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB" *) inout PS_SRSTB;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK" *) inout PS_CLK;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB" *) inout PS_PORB;
wire [14:0]DDR_Addr;
wire [2:0]DDR_BankAddr;
wire DDR_CAS_n;
wire DDR_CKE;
wire DDR_CS_n;
wire DDR_Clk;
wire DDR_Clk_n;
wire [3:0]DDR_DM;
wire [31:0]DDR_DQ;
wire [3:0]DDR_DQS;
wire [3:0]DDR_DQS_n;
wire DDR_DRSTB;
wire DDR_ODT;
wire DDR_RAS_n;
wire DDR_VRN;
wire DDR_VRP;
wire DDR_WEB;
wire FCLK_CLK0;
wire FCLK_RESET0_N;
wire FTMT_F2P_TRIGACK_0;
wire FTMT_F2P_TRIG_0;
wire FTMT_P2F_TRIGACK_0;
wire FTMT_P2F_TRIG_0;
wire [53:0]MIO;
wire M_AXI_GP0_ACLK;
wire [31:0]M_AXI_GP0_ARADDR;
wire [1:0]M_AXI_GP0_ARBURST;
wire [3:0]M_AXI_GP0_ARCACHE;
wire [11:0]M_AXI_GP0_ARID;
wire [3:0]M_AXI_GP0_ARLEN;
wire [1:0]M_AXI_GP0_ARLOCK;
wire [2:0]M_AXI_GP0_ARPROT;
wire [3:0]M_AXI_GP0_ARQOS;
wire M_AXI_GP0_ARREADY;
wire [2:0]M_AXI_GP0_ARSIZE;
wire M_AXI_GP0_ARVALID;
wire [31:0]M_AXI_GP0_AWADDR;
wire [1:0]M_AXI_GP0_AWBURST;
wire [3:0]M_AXI_GP0_AWCACHE;
wire [11:0]M_AXI_GP0_AWID;
wire [3:0]M_AXI_GP0_AWLEN;
wire [1:0]M_AXI_GP0_AWLOCK;
wire [2:0]M_AXI_GP0_AWPROT;
wire [3:0]M_AXI_GP0_AWQOS;
wire M_AXI_GP0_AWREADY;
wire [2:0]M_AXI_GP0_AWSIZE;
wire M_AXI_GP0_AWVALID;
wire [11:0]M_AXI_GP0_BID;
wire M_AXI_GP0_BREADY;
wire [1:0]M_AXI_GP0_BRESP;
wire M_AXI_GP0_BVALID;
wire [31:0]M_AXI_GP0_RDATA;
wire [11:0]M_AXI_GP0_RID;
wire M_AXI_GP0_RLAST;
wire M_AXI_GP0_RREADY;
wire [1:0]M_AXI_GP0_RRESP;
wire M_AXI_GP0_RVALID;
wire [31:0]M_AXI_GP0_WDATA;
wire [11:0]M_AXI_GP0_WID;
wire M_AXI_GP0_WLAST;
wire M_AXI_GP0_WREADY;
wire [3:0]M_AXI_GP0_WSTRB;
wire M_AXI_GP0_WVALID;
wire PS_CLK;
wire PS_PORB;
wire PS_SRSTB;
wire TTC0_WAVE0_OUT;
wire TTC0_WAVE1_OUT;
wire TTC0_WAVE2_OUT;
wire [1:0]USB0_PORT_INDCTL;
wire USB0_VBUS_PWRFAULT;
wire USB0_VBUS_PWRSELECT;
wire NLW_inst_CAN0_PHY_TX_UNCONNECTED;
wire NLW_inst_CAN1_PHY_TX_UNCONNECTED;
wire NLW_inst_DMA0_DAVALID_UNCONNECTED;
wire NLW_inst_DMA0_DRREADY_UNCONNECTED;
wire NLW_inst_DMA0_RSTN_UNCONNECTED;
wire NLW_inst_DMA1_DAVALID_UNCONNECTED;
wire NLW_inst_DMA1_DRREADY_UNCONNECTED;
wire NLW_inst_DMA1_RSTN_UNCONNECTED;
wire NLW_inst_DMA2_DAVALID_UNCONNECTED;
wire NLW_inst_DMA2_DRREADY_UNCONNECTED;
wire NLW_inst_DMA2_RSTN_UNCONNECTED;
wire NLW_inst_DMA3_DAVALID_UNCONNECTED;
wire NLW_inst_DMA3_DRREADY_UNCONNECTED;
wire NLW_inst_DMA3_RSTN_UNCONNECTED;
wire NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED;
wire NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED;
wire NLW_inst_ENET0_MDIO_MDC_UNCONNECTED;
wire NLW_inst_ENET0_MDIO_O_UNCONNECTED;
wire NLW_inst_ENET0_MDIO_T_UNCONNECTED;
wire NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED;
wire NLW_inst_ENET0_SOF_RX_UNCONNECTED;
wire NLW_inst_ENET0_SOF_TX_UNCONNECTED;
wire NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED;
wire NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED;
wire NLW_inst_ENET1_MDIO_MDC_UNCONNECTED;
wire NLW_inst_ENET1_MDIO_O_UNCONNECTED;
wire NLW_inst_ENET1_MDIO_T_UNCONNECTED;
wire NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED;
wire NLW_inst_ENET1_SOF_RX_UNCONNECTED;
wire NLW_inst_ENET1_SOF_TX_UNCONNECTED;
wire NLW_inst_EVENT_EVENTO_UNCONNECTED;
wire NLW_inst_FCLK_CLK1_UNCONNECTED;
wire NLW_inst_FCLK_CLK2_UNCONNECTED;
wire NLW_inst_FCLK_CLK3_UNCONNECTED;
wire NLW_inst_FCLK_RESET1_N_UNCONNECTED;
wire NLW_inst_FCLK_RESET2_N_UNCONNECTED;
wire NLW_inst_FCLK_RESET3_N_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED;
wire NLW_inst_I2C0_SCL_O_UNCONNECTED;
wire NLW_inst_I2C0_SCL_T_UNCONNECTED;
wire NLW_inst_I2C0_SDA_O_UNCONNECTED;
wire NLW_inst_I2C0_SDA_T_UNCONNECTED;
wire NLW_inst_I2C1_SCL_O_UNCONNECTED;
wire NLW_inst_I2C1_SCL_T_UNCONNECTED;
wire NLW_inst_I2C1_SDA_O_UNCONNECTED;
wire NLW_inst_I2C1_SDA_T_UNCONNECTED;
wire NLW_inst_IRQ_P2F_CAN0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_CAN1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_CTI_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_GPIO_UNCONNECTED;
wire NLW_inst_IRQ_P2F_I2C0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_I2C1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_QSPI_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SMC_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SPI0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SPI1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_UART0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_UART1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_USB0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_USB1_UNCONNECTED;
wire NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED;
wire NLW_inst_PJTAG_TDO_UNCONNECTED;
wire NLW_inst_SDIO0_BUSPOW_UNCONNECTED;
wire NLW_inst_SDIO0_CLK_UNCONNECTED;
wire NLW_inst_SDIO0_CMD_O_UNCONNECTED;
wire NLW_inst_SDIO0_CMD_T_UNCONNECTED;
wire NLW_inst_SDIO0_LED_UNCONNECTED;
wire NLW_inst_SDIO1_BUSPOW_UNCONNECTED;
wire NLW_inst_SDIO1_CLK_UNCONNECTED;
wire NLW_inst_SDIO1_CMD_O_UNCONNECTED;
wire NLW_inst_SDIO1_CMD_T_UNCONNECTED;
wire NLW_inst_SDIO1_LED_UNCONNECTED;
wire NLW_inst_SPI0_MISO_O_UNCONNECTED;
wire NLW_inst_SPI0_MISO_T_UNCONNECTED;
wire NLW_inst_SPI0_MOSI_O_UNCONNECTED;
wire NLW_inst_SPI0_MOSI_T_UNCONNECTED;
wire NLW_inst_SPI0_SCLK_O_UNCONNECTED;
wire NLW_inst_SPI0_SCLK_T_UNCONNECTED;
wire NLW_inst_SPI0_SS1_O_UNCONNECTED;
wire NLW_inst_SPI0_SS2_O_UNCONNECTED;
wire NLW_inst_SPI0_SS_O_UNCONNECTED;
wire NLW_inst_SPI0_SS_T_UNCONNECTED;
wire NLW_inst_SPI1_MISO_O_UNCONNECTED;
wire NLW_inst_SPI1_MISO_T_UNCONNECTED;
wire NLW_inst_SPI1_MOSI_O_UNCONNECTED;
wire NLW_inst_SPI1_MOSI_T_UNCONNECTED;
wire NLW_inst_SPI1_SCLK_O_UNCONNECTED;
wire NLW_inst_SPI1_SCLK_T_UNCONNECTED;
wire NLW_inst_SPI1_SS1_O_UNCONNECTED;
wire NLW_inst_SPI1_SS2_O_UNCONNECTED;
wire NLW_inst_SPI1_SS_O_UNCONNECTED;
wire NLW_inst_SPI1_SS_T_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED;
wire NLW_inst_TRACE_CLK_OUT_UNCONNECTED;
wire NLW_inst_TRACE_CTL_UNCONNECTED;
wire NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED;
wire NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED;
wire NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED;
wire NLW_inst_UART0_DTRN_UNCONNECTED;
wire NLW_inst_UART0_RTSN_UNCONNECTED;
wire NLW_inst_UART0_TX_UNCONNECTED;
wire NLW_inst_UART1_DTRN_UNCONNECTED;
wire NLW_inst_UART1_RTSN_UNCONNECTED;
wire NLW_inst_UART1_TX_UNCONNECTED;
wire NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED;
wire NLW_inst_WDT_RST_OUT_UNCONNECTED;
wire [1:0]NLW_inst_DMA0_DATYPE_UNCONNECTED;
wire [1:0]NLW_inst_DMA1_DATYPE_UNCONNECTED;
wire [1:0]NLW_inst_DMA2_DATYPE_UNCONNECTED;
wire [1:0]NLW_inst_DMA3_DATYPE_UNCONNECTED;
wire [7:0]NLW_inst_ENET0_GMII_TXD_UNCONNECTED;
wire [7:0]NLW_inst_ENET1_GMII_TXD_UNCONNECTED;
wire [1:0]NLW_inst_EVENT_STANDBYWFE_UNCONNECTED;
wire [1:0]NLW_inst_EVENT_STANDBYWFI_UNCONNECTED;
wire [31:0]NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED;
wire [63:0]NLW_inst_GPIO_O_UNCONNECTED;
wire [63:0]NLW_inst_GPIO_T_UNCONNECTED;
wire [31:0]NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED;
wire [11:0]NLW_inst_M_AXI_GP1_ARID_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED;
wire [31:0]NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED;
wire [11:0]NLW_inst_M_AXI_GP1_AWID_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED;
wire [31:0]NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED;
wire [11:0]NLW_inst_M_AXI_GP1_WID_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED;
wire [2:0]NLW_inst_SDIO0_BUSVOLT_UNCONNECTED;
wire [3:0]NLW_inst_SDIO0_DATA_O_UNCONNECTED;
wire [3:0]NLW_inst_SDIO0_DATA_T_UNCONNECTED;
wire [2:0]NLW_inst_SDIO1_BUSVOLT_UNCONNECTED;
wire [3:0]NLW_inst_SDIO1_DATA_O_UNCONNECTED;
wire [3:0]NLW_inst_SDIO1_DATA_T_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_ACP_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_ACP_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP0_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED;
wire [31:0]NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP0_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP1_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED;
wire [31:0]NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP1_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP0_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP0_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP1_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP1_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP2_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP2_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP3_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP3_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED;
wire [1:0]NLW_inst_TRACE_DATA_UNCONNECTED;
wire [1:0]NLW_inst_USB1_PORT_INDCTL_UNCONNECTED;
(* C_DM_WIDTH = "4" *)
(* C_DQS_WIDTH = "4" *)
(* C_DQ_WIDTH = "32" *)
(* C_EMIO_GPIO_WIDTH = "64" *)
(* C_EN_EMIO_ENET0 = "0" *)
(* C_EN_EMIO_ENET1 = "0" *)
(* C_EN_EMIO_PJTAG = "0" *)
(* C_EN_EMIO_TRACE = "0" *)
(* C_FCLK_CLK0_BUF = "TRUE" *)
(* C_FCLK_CLK1_BUF = "FALSE" *)
(* C_FCLK_CLK2_BUF = "FALSE" *)
(* C_FCLK_CLK3_BUF = "FALSE" *)
(* C_GP0_EN_MODIFIABLE_TXN = "1" *)
(* C_GP1_EN_MODIFIABLE_TXN = "1" *)
(* C_INCLUDE_ACP_TRANS_CHECK = "0" *)
(* C_INCLUDE_TRACE_BUFFER = "0" *)
(* C_IRQ_F2P_MODE = "DIRECT" *)
(* C_MIO_PRIMITIVE = "54" *)
(* C_M_AXI_GP0_ENABLE_STATIC_REMAP = "0" *)
(* C_M_AXI_GP0_ID_WIDTH = "12" *)
(* C_M_AXI_GP0_THREAD_ID_WIDTH = "12" *)
(* C_M_AXI_GP1_ENABLE_STATIC_REMAP = "0" *)
(* C_M_AXI_GP1_ID_WIDTH = "12" *)
(* C_M_AXI_GP1_THREAD_ID_WIDTH = "12" *)
(* C_NUM_F2P_INTR_INPUTS = "1" *)
(* C_PACKAGE_NAME = "clg484" *)
(* C_PS7_SI_REV = "PRODUCTION" *)
(* C_S_AXI_ACP_ARUSER_VAL = "31" *)
(* C_S_AXI_ACP_AWUSER_VAL = "31" *)
(* C_S_AXI_ACP_ID_WIDTH = "3" *)
(* C_S_AXI_GP0_ID_WIDTH = "6" *)
(* C_S_AXI_GP1_ID_WIDTH = "6" *)
(* C_S_AXI_HP0_DATA_WIDTH = "64" *)
(* C_S_AXI_HP0_ID_WIDTH = "6" *)
(* C_S_AXI_HP1_DATA_WIDTH = "64" *)
(* C_S_AXI_HP1_ID_WIDTH = "6" *)
(* C_S_AXI_HP2_DATA_WIDTH = "64" *)
(* C_S_AXI_HP2_ID_WIDTH = "6" *)
(* C_S_AXI_HP3_DATA_WIDTH = "64" *)
(* C_S_AXI_HP3_ID_WIDTH = "6" *)
(* C_TRACE_BUFFER_CLOCK_DELAY = "12" *)
(* C_TRACE_BUFFER_FIFO_SIZE = "128" *)
(* C_TRACE_INTERNAL_WIDTH = "2" *)
(* C_TRACE_PIPELINE_WIDTH = "8" *)
(* C_USE_AXI_NONSECURE = "0" *)
(* C_USE_DEFAULT_ACP_USER_VAL = "0" *)
(* C_USE_M_AXI_GP0 = "1" *)
(* C_USE_M_AXI_GP1 = "0" *)
(* C_USE_S_AXI_ACP = "0" *)
(* C_USE_S_AXI_GP0 = "0" *)
(* C_USE_S_AXI_GP1 = "0" *)
(* C_USE_S_AXI_HP0 = "0" *)
(* C_USE_S_AXI_HP1 = "0" *)
(* C_USE_S_AXI_HP2 = "0" *)
(* C_USE_S_AXI_HP3 = "0" *)
(* HW_HANDOFF = "zynq_design_1_processing_system7_0_0.hwdef" *)
(* POWER = "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333313} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={10} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200.000000} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>" *)
(* USE_TRACE_DATA_EDGE_DETECTOR = "0" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 inst
(.CAN0_PHY_RX(1'b0),
.CAN0_PHY_TX(NLW_inst_CAN0_PHY_TX_UNCONNECTED),
.CAN1_PHY_RX(1'b0),
.CAN1_PHY_TX(NLW_inst_CAN1_PHY_TX_UNCONNECTED),
.Core0_nFIQ(1'b0),
.Core0_nIRQ(1'b0),
.Core1_nFIQ(1'b0),
.Core1_nIRQ(1'b0),
.DDR_ARB({1'b0,1'b0,1'b0,1'b0}),
.DDR_Addr(DDR_Addr),
.DDR_BankAddr(DDR_BankAddr),
.DDR_CAS_n(DDR_CAS_n),
.DDR_CKE(DDR_CKE),
.DDR_CS_n(DDR_CS_n),
.DDR_Clk(DDR_Clk),
.DDR_Clk_n(DDR_Clk_n),
.DDR_DM(DDR_DM),
.DDR_DQ(DDR_DQ),
.DDR_DQS(DDR_DQS),
.DDR_DQS_n(DDR_DQS_n),
.DDR_DRSTB(DDR_DRSTB),
.DDR_ODT(DDR_ODT),
.DDR_RAS_n(DDR_RAS_n),
.DDR_VRN(DDR_VRN),
.DDR_VRP(DDR_VRP),
.DDR_WEB(DDR_WEB),
.DMA0_ACLK(1'b0),
.DMA0_DAREADY(1'b0),
.DMA0_DATYPE(NLW_inst_DMA0_DATYPE_UNCONNECTED[1:0]),
.DMA0_DAVALID(NLW_inst_DMA0_DAVALID_UNCONNECTED),
.DMA0_DRLAST(1'b0),
.DMA0_DRREADY(NLW_inst_DMA0_DRREADY_UNCONNECTED),
.DMA0_DRTYPE({1'b0,1'b0}),
.DMA0_DRVALID(1'b0),
.DMA0_RSTN(NLW_inst_DMA0_RSTN_UNCONNECTED),
.DMA1_ACLK(1'b0),
.DMA1_DAREADY(1'b0),
.DMA1_DATYPE(NLW_inst_DMA1_DATYPE_UNCONNECTED[1:0]),
.DMA1_DAVALID(NLW_inst_DMA1_DAVALID_UNCONNECTED),
.DMA1_DRLAST(1'b0),
.DMA1_DRREADY(NLW_inst_DMA1_DRREADY_UNCONNECTED),
.DMA1_DRTYPE({1'b0,1'b0}),
.DMA1_DRVALID(1'b0),
.DMA1_RSTN(NLW_inst_DMA1_RSTN_UNCONNECTED),
.DMA2_ACLK(1'b0),
.DMA2_DAREADY(1'b0),
.DMA2_DATYPE(NLW_inst_DMA2_DATYPE_UNCONNECTED[1:0]),
.DMA2_DAVALID(NLW_inst_DMA2_DAVALID_UNCONNECTED),
.DMA2_DRLAST(1'b0),
.DMA2_DRREADY(NLW_inst_DMA2_DRREADY_UNCONNECTED),
.DMA2_DRTYPE({1'b0,1'b0}),
.DMA2_DRVALID(1'b0),
.DMA2_RSTN(NLW_inst_DMA2_RSTN_UNCONNECTED),
.DMA3_ACLK(1'b0),
.DMA3_DAREADY(1'b0),
.DMA3_DATYPE(NLW_inst_DMA3_DATYPE_UNCONNECTED[1:0]),
.DMA3_DAVALID(NLW_inst_DMA3_DAVALID_UNCONNECTED),
.DMA3_DRLAST(1'b0),
.DMA3_DRREADY(NLW_inst_DMA3_DRREADY_UNCONNECTED),
.DMA3_DRTYPE({1'b0,1'b0}),
.DMA3_DRVALID(1'b0),
.DMA3_RSTN(NLW_inst_DMA3_RSTN_UNCONNECTED),
.ENET0_EXT_INTIN(1'b0),
.ENET0_GMII_COL(1'b0),
.ENET0_GMII_CRS(1'b0),
.ENET0_GMII_RXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ENET0_GMII_RX_CLK(1'b0),
.ENET0_GMII_RX_DV(1'b0),
.ENET0_GMII_RX_ER(1'b0),
.ENET0_GMII_TXD(NLW_inst_ENET0_GMII_TXD_UNCONNECTED[7:0]),
.ENET0_GMII_TX_CLK(1'b0),
.ENET0_GMII_TX_EN(NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED),
.ENET0_GMII_TX_ER(NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED),
.ENET0_MDIO_I(1'b0),
.ENET0_MDIO_MDC(NLW_inst_ENET0_MDIO_MDC_UNCONNECTED),
.ENET0_MDIO_O(NLW_inst_ENET0_MDIO_O_UNCONNECTED),
.ENET0_MDIO_T(NLW_inst_ENET0_MDIO_T_UNCONNECTED),
.ENET0_PTP_DELAY_REQ_RX(NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED),
.ENET0_PTP_DELAY_REQ_TX(NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED),
.ENET0_PTP_PDELAY_REQ_RX(NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED),
.ENET0_PTP_PDELAY_REQ_TX(NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED),
.ENET0_PTP_PDELAY_RESP_RX(NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED),
.ENET0_PTP_PDELAY_RESP_TX(NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED),
.ENET0_PTP_SYNC_FRAME_RX(NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED),
.ENET0_PTP_SYNC_FRAME_TX(NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED),
.ENET0_SOF_RX(NLW_inst_ENET0_SOF_RX_UNCONNECTED),
.ENET0_SOF_TX(NLW_inst_ENET0_SOF_TX_UNCONNECTED),
.ENET1_EXT_INTIN(1'b0),
.ENET1_GMII_COL(1'b0),
.ENET1_GMII_CRS(1'b0),
.ENET1_GMII_RXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ENET1_GMII_RX_CLK(1'b0),
.ENET1_GMII_RX_DV(1'b0),
.ENET1_GMII_RX_ER(1'b0),
.ENET1_GMII_TXD(NLW_inst_ENET1_GMII_TXD_UNCONNECTED[7:0]),
.ENET1_GMII_TX_CLK(1'b0),
.ENET1_GMII_TX_EN(NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED),
.ENET1_GMII_TX_ER(NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED),
.ENET1_MDIO_I(1'b0),
.ENET1_MDIO_MDC(NLW_inst_ENET1_MDIO_MDC_UNCONNECTED),
.ENET1_MDIO_O(NLW_inst_ENET1_MDIO_O_UNCONNECTED),
.ENET1_MDIO_T(NLW_inst_ENET1_MDIO_T_UNCONNECTED),
.ENET1_PTP_DELAY_REQ_RX(NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED),
.ENET1_PTP_DELAY_REQ_TX(NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED),
.ENET1_PTP_PDELAY_REQ_RX(NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED),
.ENET1_PTP_PDELAY_REQ_TX(NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED),
.ENET1_PTP_PDELAY_RESP_RX(NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED),
.ENET1_PTP_PDELAY_RESP_TX(NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED),
.ENET1_PTP_SYNC_FRAME_RX(NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED),
.ENET1_PTP_SYNC_FRAME_TX(NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED),
.ENET1_SOF_RX(NLW_inst_ENET1_SOF_RX_UNCONNECTED),
.ENET1_SOF_TX(NLW_inst_ENET1_SOF_TX_UNCONNECTED),
.EVENT_EVENTI(1'b0),
.EVENT_EVENTO(NLW_inst_EVENT_EVENTO_UNCONNECTED),
.EVENT_STANDBYWFE(NLW_inst_EVENT_STANDBYWFE_UNCONNECTED[1:0]),
.EVENT_STANDBYWFI(NLW_inst_EVENT_STANDBYWFI_UNCONNECTED[1:0]),
.FCLK_CLK0(FCLK_CLK0),
.FCLK_CLK1(NLW_inst_FCLK_CLK1_UNCONNECTED),
.FCLK_CLK2(NLW_inst_FCLK_CLK2_UNCONNECTED),
.FCLK_CLK3(NLW_inst_FCLK_CLK3_UNCONNECTED),
.FCLK_CLKTRIG0_N(1'b0),
.FCLK_CLKTRIG1_N(1'b0),
.FCLK_CLKTRIG2_N(1'b0),
.FCLK_CLKTRIG3_N(1'b0),
.FCLK_RESET0_N(FCLK_RESET0_N),
.FCLK_RESET1_N(NLW_inst_FCLK_RESET1_N_UNCONNECTED),
.FCLK_RESET2_N(NLW_inst_FCLK_RESET2_N_UNCONNECTED),
.FCLK_RESET3_N(NLW_inst_FCLK_RESET3_N_UNCONNECTED),
.FPGA_IDLE_N(1'b0),
.FTMD_TRACEIN_ATID({1'b0,1'b0,1'b0,1'b0}),
.FTMD_TRACEIN_CLK(1'b0),
.FTMD_TRACEIN_DATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.FTMD_TRACEIN_VALID(1'b0),
.FTMT_F2P_DEBUG({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.FTMT_F2P_TRIGACK_0(FTMT_F2P_TRIGACK_0),
.FTMT_F2P_TRIGACK_1(NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED),
.FTMT_F2P_TRIGACK_2(NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED),
.FTMT_F2P_TRIGACK_3(NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED),
.FTMT_F2P_TRIG_0(FTMT_F2P_TRIG_0),
.FTMT_F2P_TRIG_1(1'b0),
.FTMT_F2P_TRIG_2(1'b0),
.FTMT_F2P_TRIG_3(1'b0),
.FTMT_P2F_DEBUG(NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED[31:0]),
.FTMT_P2F_TRIGACK_0(FTMT_P2F_TRIGACK_0),
.FTMT_P2F_TRIGACK_1(1'b0),
.FTMT_P2F_TRIGACK_2(1'b0),
.FTMT_P2F_TRIGACK_3(1'b0),
.FTMT_P2F_TRIG_0(FTMT_P2F_TRIG_0),
.FTMT_P2F_TRIG_1(NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED),
.FTMT_P2F_TRIG_2(NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED),
.FTMT_P2F_TRIG_3(NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED),
.GPIO_I({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.GPIO_O(NLW_inst_GPIO_O_UNCONNECTED[63:0]),
.GPIO_T(NLW_inst_GPIO_T_UNCONNECTED[63:0]),
.I2C0_SCL_I(1'b0),
.I2C0_SCL_O(NLW_inst_I2C0_SCL_O_UNCONNECTED),
.I2C0_SCL_T(NLW_inst_I2C0_SCL_T_UNCONNECTED),
.I2C0_SDA_I(1'b0),
.I2C0_SDA_O(NLW_inst_I2C0_SDA_O_UNCONNECTED),
.I2C0_SDA_T(NLW_inst_I2C0_SDA_T_UNCONNECTED),
.I2C1_SCL_I(1'b0),
.I2C1_SCL_O(NLW_inst_I2C1_SCL_O_UNCONNECTED),
.I2C1_SCL_T(NLW_inst_I2C1_SCL_T_UNCONNECTED),
.I2C1_SDA_I(1'b0),
.I2C1_SDA_O(NLW_inst_I2C1_SDA_O_UNCONNECTED),
.I2C1_SDA_T(NLW_inst_I2C1_SDA_T_UNCONNECTED),
.IRQ_F2P(1'b0),
.IRQ_P2F_CAN0(NLW_inst_IRQ_P2F_CAN0_UNCONNECTED),
.IRQ_P2F_CAN1(NLW_inst_IRQ_P2F_CAN1_UNCONNECTED),
.IRQ_P2F_CTI(NLW_inst_IRQ_P2F_CTI_UNCONNECTED),
.IRQ_P2F_DMAC0(NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED),
.IRQ_P2F_DMAC1(NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED),
.IRQ_P2F_DMAC2(NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED),
.IRQ_P2F_DMAC3(NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED),
.IRQ_P2F_DMAC4(NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED),
.IRQ_P2F_DMAC5(NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED),
.IRQ_P2F_DMAC6(NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED),
.IRQ_P2F_DMAC7(NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED),
.IRQ_P2F_DMAC_ABORT(NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED),
.IRQ_P2F_ENET0(NLW_inst_IRQ_P2F_ENET0_UNCONNECTED),
.IRQ_P2F_ENET1(NLW_inst_IRQ_P2F_ENET1_UNCONNECTED),
.IRQ_P2F_ENET_WAKE0(NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED),
.IRQ_P2F_ENET_WAKE1(NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED),
.IRQ_P2F_GPIO(NLW_inst_IRQ_P2F_GPIO_UNCONNECTED),
.IRQ_P2F_I2C0(NLW_inst_IRQ_P2F_I2C0_UNCONNECTED),
.IRQ_P2F_I2C1(NLW_inst_IRQ_P2F_I2C1_UNCONNECTED),
.IRQ_P2F_QSPI(NLW_inst_IRQ_P2F_QSPI_UNCONNECTED),
.IRQ_P2F_SDIO0(NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED),
.IRQ_P2F_SDIO1(NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED),
.IRQ_P2F_SMC(NLW_inst_IRQ_P2F_SMC_UNCONNECTED),
.IRQ_P2F_SPI0(NLW_inst_IRQ_P2F_SPI0_UNCONNECTED),
.IRQ_P2F_SPI1(NLW_inst_IRQ_P2F_SPI1_UNCONNECTED),
.IRQ_P2F_UART0(NLW_inst_IRQ_P2F_UART0_UNCONNECTED),
.IRQ_P2F_UART1(NLW_inst_IRQ_P2F_UART1_UNCONNECTED),
.IRQ_P2F_USB0(NLW_inst_IRQ_P2F_USB0_UNCONNECTED),
.IRQ_P2F_USB1(NLW_inst_IRQ_P2F_USB1_UNCONNECTED),
.MIO(MIO),
.M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
.M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
.M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
.M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
.M_AXI_GP0_ARESETN(NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED),
.M_AXI_GP0_ARID(M_AXI_GP0_ARID),
.M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
.M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
.M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
.M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
.M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
.M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
.M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
.M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
.M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
.M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
.M_AXI_GP0_AWID(M_AXI_GP0_AWID),
.M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
.M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
.M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
.M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
.M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
.M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
.M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
.M_AXI_GP0_BID(M_AXI_GP0_BID),
.M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
.M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
.M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
.M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
.M_AXI_GP0_RID(M_AXI_GP0_RID),
.M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
.M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
.M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
.M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
.M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
.M_AXI_GP0_WID(M_AXI_GP0_WID),
.M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
.M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
.M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
.M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
.M_AXI_GP1_ACLK(1'b0),
.M_AXI_GP1_ARADDR(NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED[31:0]),
.M_AXI_GP1_ARBURST(NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED[1:0]),
.M_AXI_GP1_ARCACHE(NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED[3:0]),
.M_AXI_GP1_ARESETN(NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED),
.M_AXI_GP1_ARID(NLW_inst_M_AXI_GP1_ARID_UNCONNECTED[11:0]),
.M_AXI_GP1_ARLEN(NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED[3:0]),
.M_AXI_GP1_ARLOCK(NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED[1:0]),
.M_AXI_GP1_ARPROT(NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED[2:0]),
.M_AXI_GP1_ARQOS(NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED[3:0]),
.M_AXI_GP1_ARREADY(1'b0),
.M_AXI_GP1_ARSIZE(NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED[2:0]),
.M_AXI_GP1_ARVALID(NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED),
.M_AXI_GP1_AWADDR(NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED[31:0]),
.M_AXI_GP1_AWBURST(NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED[1:0]),
.M_AXI_GP1_AWCACHE(NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED[3:0]),
.M_AXI_GP1_AWID(NLW_inst_M_AXI_GP1_AWID_UNCONNECTED[11:0]),
.M_AXI_GP1_AWLEN(NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED[3:0]),
.M_AXI_GP1_AWLOCK(NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED[1:0]),
.M_AXI_GP1_AWPROT(NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED[2:0]),
.M_AXI_GP1_AWQOS(NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED[3:0]),
.M_AXI_GP1_AWREADY(1'b0),
.M_AXI_GP1_AWSIZE(NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED[2:0]),
.M_AXI_GP1_AWVALID(NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED),
.M_AXI_GP1_BID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.M_AXI_GP1_BREADY(NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED),
.M_AXI_GP1_BRESP({1'b0,1'b0}),
.M_AXI_GP1_BVALID(1'b0),
.M_AXI_GP1_RDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.M_AXI_GP1_RID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.M_AXI_GP1_RLAST(1'b0),
.M_AXI_GP1_RREADY(NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED),
.M_AXI_GP1_RRESP({1'b0,1'b0}),
.M_AXI_GP1_RVALID(1'b0),
.M_AXI_GP1_WDATA(NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED[31:0]),
.M_AXI_GP1_WID(NLW_inst_M_AXI_GP1_WID_UNCONNECTED[11:0]),
.M_AXI_GP1_WLAST(NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED),
.M_AXI_GP1_WREADY(1'b0),
.M_AXI_GP1_WSTRB(NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED[3:0]),
.M_AXI_GP1_WVALID(NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED),
.PJTAG_TCK(1'b0),
.PJTAG_TDI(1'b0),
.PJTAG_TDO(NLW_inst_PJTAG_TDO_UNCONNECTED),
.PJTAG_TMS(1'b0),
.PS_CLK(PS_CLK),
.PS_PORB(PS_PORB),
.PS_SRSTB(PS_SRSTB),
.SDIO0_BUSPOW(NLW_inst_SDIO0_BUSPOW_UNCONNECTED),
.SDIO0_BUSVOLT(NLW_inst_SDIO0_BUSVOLT_UNCONNECTED[2:0]),
.SDIO0_CDN(1'b0),
.SDIO0_CLK(NLW_inst_SDIO0_CLK_UNCONNECTED),
.SDIO0_CLK_FB(1'b0),
.SDIO0_CMD_I(1'b0),
.SDIO0_CMD_O(NLW_inst_SDIO0_CMD_O_UNCONNECTED),
.SDIO0_CMD_T(NLW_inst_SDIO0_CMD_T_UNCONNECTED),
.SDIO0_DATA_I({1'b0,1'b0,1'b0,1'b0}),
.SDIO0_DATA_O(NLW_inst_SDIO0_DATA_O_UNCONNECTED[3:0]),
.SDIO0_DATA_T(NLW_inst_SDIO0_DATA_T_UNCONNECTED[3:0]),
.SDIO0_LED(NLW_inst_SDIO0_LED_UNCONNECTED),
.SDIO0_WP(1'b0),
.SDIO1_BUSPOW(NLW_inst_SDIO1_BUSPOW_UNCONNECTED),
.SDIO1_BUSVOLT(NLW_inst_SDIO1_BUSVOLT_UNCONNECTED[2:0]),
.SDIO1_CDN(1'b0),
.SDIO1_CLK(NLW_inst_SDIO1_CLK_UNCONNECTED),
.SDIO1_CLK_FB(1'b0),
.SDIO1_CMD_I(1'b0),
.SDIO1_CMD_O(NLW_inst_SDIO1_CMD_O_UNCONNECTED),
.SDIO1_CMD_T(NLW_inst_SDIO1_CMD_T_UNCONNECTED),
.SDIO1_DATA_I({1'b0,1'b0,1'b0,1'b0}),
.SDIO1_DATA_O(NLW_inst_SDIO1_DATA_O_UNCONNECTED[3:0]),
.SDIO1_DATA_T(NLW_inst_SDIO1_DATA_T_UNCONNECTED[3:0]),
.SDIO1_LED(NLW_inst_SDIO1_LED_UNCONNECTED),
.SDIO1_WP(1'b0),
.SPI0_MISO_I(1'b0),
.SPI0_MISO_O(NLW_inst_SPI0_MISO_O_UNCONNECTED),
.SPI0_MISO_T(NLW_inst_SPI0_MISO_T_UNCONNECTED),
.SPI0_MOSI_I(1'b0),
.SPI0_MOSI_O(NLW_inst_SPI0_MOSI_O_UNCONNECTED),
.SPI0_MOSI_T(NLW_inst_SPI0_MOSI_T_UNCONNECTED),
.SPI0_SCLK_I(1'b0),
.SPI0_SCLK_O(NLW_inst_SPI0_SCLK_O_UNCONNECTED),
.SPI0_SCLK_T(NLW_inst_SPI0_SCLK_T_UNCONNECTED),
.SPI0_SS1_O(NLW_inst_SPI0_SS1_O_UNCONNECTED),
.SPI0_SS2_O(NLW_inst_SPI0_SS2_O_UNCONNECTED),
.SPI0_SS_I(1'b0),
.SPI0_SS_O(NLW_inst_SPI0_SS_O_UNCONNECTED),
.SPI0_SS_T(NLW_inst_SPI0_SS_T_UNCONNECTED),
.SPI1_MISO_I(1'b0),
.SPI1_MISO_O(NLW_inst_SPI1_MISO_O_UNCONNECTED),
.SPI1_MISO_T(NLW_inst_SPI1_MISO_T_UNCONNECTED),
.SPI1_MOSI_I(1'b0),
.SPI1_MOSI_O(NLW_inst_SPI1_MOSI_O_UNCONNECTED),
.SPI1_MOSI_T(NLW_inst_SPI1_MOSI_T_UNCONNECTED),
.SPI1_SCLK_I(1'b0),
.SPI1_SCLK_O(NLW_inst_SPI1_SCLK_O_UNCONNECTED),
.SPI1_SCLK_T(NLW_inst_SPI1_SCLK_T_UNCONNECTED),
.SPI1_SS1_O(NLW_inst_SPI1_SS1_O_UNCONNECTED),
.SPI1_SS2_O(NLW_inst_SPI1_SS2_O_UNCONNECTED),
.SPI1_SS_I(1'b0),
.SPI1_SS_O(NLW_inst_SPI1_SS_O_UNCONNECTED),
.SPI1_SS_T(NLW_inst_SPI1_SS_T_UNCONNECTED),
.SRAM_INTIN(1'b0),
.S_AXI_ACP_ACLK(1'b0),
.S_AXI_ACP_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARBURST({1'b0,1'b0}),
.S_AXI_ACP_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARESETN(NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED),
.S_AXI_ACP_ARID({1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARLOCK({1'b0,1'b0}),
.S_AXI_ACP_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARREADY(NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED),
.S_AXI_ACP_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARUSER({1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARVALID(1'b0),
.S_AXI_ACP_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWBURST({1'b0,1'b0}),
.S_AXI_ACP_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWID({1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWLOCK({1'b0,1'b0}),
.S_AXI_ACP_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWREADY(NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED),
.S_AXI_ACP_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWUSER({1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWVALID(1'b0),
.S_AXI_ACP_BID(NLW_inst_S_AXI_ACP_BID_UNCONNECTED[2:0]),
.S_AXI_ACP_BREADY(1'b0),
.S_AXI_ACP_BRESP(NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED[1:0]),
.S_AXI_ACP_BVALID(NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED),
.S_AXI_ACP_RDATA(NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED[63:0]),
.S_AXI_ACP_RID(NLW_inst_S_AXI_ACP_RID_UNCONNECTED[2:0]),
.S_AXI_ACP_RLAST(NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED),
.S_AXI_ACP_RREADY(1'b0),
.S_AXI_ACP_RRESP(NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED[1:0]),
.S_AXI_ACP_RVALID(NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED),
.S_AXI_ACP_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_WID({1'b0,1'b0,1'b0}),
.S_AXI_ACP_WLAST(1'b0),
.S_AXI_ACP_WREADY(NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED),
.S_AXI_ACP_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_WVALID(1'b0),
.S_AXI_GP0_ACLK(1'b0),
.S_AXI_GP0_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARBURST({1'b0,1'b0}),
.S_AXI_GP0_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARESETN(NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED),
.S_AXI_GP0_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARLOCK({1'b0,1'b0}),
.S_AXI_GP0_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARREADY(NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED),
.S_AXI_GP0_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARVALID(1'b0),
.S_AXI_GP0_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWBURST({1'b0,1'b0}),
.S_AXI_GP0_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWLOCK({1'b0,1'b0}),
.S_AXI_GP0_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWREADY(NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED),
.S_AXI_GP0_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWVALID(1'b0),
.S_AXI_GP0_BID(NLW_inst_S_AXI_GP0_BID_UNCONNECTED[5:0]),
.S_AXI_GP0_BREADY(1'b0),
.S_AXI_GP0_BRESP(NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED[1:0]),
.S_AXI_GP0_BVALID(NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED),
.S_AXI_GP0_RDATA(NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED[31:0]),
.S_AXI_GP0_RID(NLW_inst_S_AXI_GP0_RID_UNCONNECTED[5:0]),
.S_AXI_GP0_RLAST(NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED),
.S_AXI_GP0_RREADY(1'b0),
.S_AXI_GP0_RRESP(NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED[1:0]),
.S_AXI_GP0_RVALID(NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED),
.S_AXI_GP0_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_WLAST(1'b0),
.S_AXI_GP0_WREADY(NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED),
.S_AXI_GP0_WSTRB({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_WVALID(1'b0),
.S_AXI_GP1_ACLK(1'b0),
.S_AXI_GP1_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARBURST({1'b0,1'b0}),
.S_AXI_GP1_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARESETN(NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED),
.S_AXI_GP1_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARLOCK({1'b0,1'b0}),
.S_AXI_GP1_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARREADY(NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED),
.S_AXI_GP1_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARVALID(1'b0),
.S_AXI_GP1_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWBURST({1'b0,1'b0}),
.S_AXI_GP1_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWLOCK({1'b0,1'b0}),
.S_AXI_GP1_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWREADY(NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED),
.S_AXI_GP1_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWVALID(1'b0),
.S_AXI_GP1_BID(NLW_inst_S_AXI_GP1_BID_UNCONNECTED[5:0]),
.S_AXI_GP1_BREADY(1'b0),
.S_AXI_GP1_BRESP(NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED[1:0]),
.S_AXI_GP1_BVALID(NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED),
.S_AXI_GP1_RDATA(NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED[31:0]),
.S_AXI_GP1_RID(NLW_inst_S_AXI_GP1_RID_UNCONNECTED[5:0]),
.S_AXI_GP1_RLAST(NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED),
.S_AXI_GP1_RREADY(1'b0),
.S_AXI_GP1_RRESP(NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED[1:0]),
.S_AXI_GP1_RVALID(NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED),
.S_AXI_GP1_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_WLAST(1'b0),
.S_AXI_GP1_WREADY(NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED),
.S_AXI_GP1_WSTRB({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_WVALID(1'b0),
.S_AXI_HP0_ACLK(1'b0),
.S_AXI_HP0_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARBURST({1'b0,1'b0}),
.S_AXI_HP0_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARESETN(NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED),
.S_AXI_HP0_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARLOCK({1'b0,1'b0}),
.S_AXI_HP0_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARREADY(NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED),
.S_AXI_HP0_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARVALID(1'b0),
.S_AXI_HP0_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWBURST({1'b0,1'b0}),
.S_AXI_HP0_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWLOCK({1'b0,1'b0}),
.S_AXI_HP0_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWREADY(NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED),
.S_AXI_HP0_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWVALID(1'b0),
.S_AXI_HP0_BID(NLW_inst_S_AXI_HP0_BID_UNCONNECTED[5:0]),
.S_AXI_HP0_BREADY(1'b0),
.S_AXI_HP0_BRESP(NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP0_BVALID(NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED),
.S_AXI_HP0_RACOUNT(NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP0_RCOUNT(NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP0_RDATA(NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP0_RDISSUECAP1_EN(1'b0),
.S_AXI_HP0_RID(NLW_inst_S_AXI_HP0_RID_UNCONNECTED[5:0]),
.S_AXI_HP0_RLAST(NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED),
.S_AXI_HP0_RREADY(1'b0),
.S_AXI_HP0_RRESP(NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP0_RVALID(NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED),
.S_AXI_HP0_WACOUNT(NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP0_WCOUNT(NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP0_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_WLAST(1'b0),
.S_AXI_HP0_WREADY(NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED),
.S_AXI_HP0_WRISSUECAP1_EN(1'b0),
.S_AXI_HP0_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_WVALID(1'b0),
.S_AXI_HP1_ACLK(1'b0),
.S_AXI_HP1_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARBURST({1'b0,1'b0}),
.S_AXI_HP1_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARESETN(NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED),
.S_AXI_HP1_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARLOCK({1'b0,1'b0}),
.S_AXI_HP1_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARREADY(NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED),
.S_AXI_HP1_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARVALID(1'b0),
.S_AXI_HP1_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWBURST({1'b0,1'b0}),
.S_AXI_HP1_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWLOCK({1'b0,1'b0}),
.S_AXI_HP1_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWREADY(NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED),
.S_AXI_HP1_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWVALID(1'b0),
.S_AXI_HP1_BID(NLW_inst_S_AXI_HP1_BID_UNCONNECTED[5:0]),
.S_AXI_HP1_BREADY(1'b0),
.S_AXI_HP1_BRESP(NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP1_BVALID(NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED),
.S_AXI_HP1_RACOUNT(NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP1_RCOUNT(NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP1_RDATA(NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP1_RDISSUECAP1_EN(1'b0),
.S_AXI_HP1_RID(NLW_inst_S_AXI_HP1_RID_UNCONNECTED[5:0]),
.S_AXI_HP1_RLAST(NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED),
.S_AXI_HP1_RREADY(1'b0),
.S_AXI_HP1_RRESP(NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP1_RVALID(NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED),
.S_AXI_HP1_WACOUNT(NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP1_WCOUNT(NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP1_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_WLAST(1'b0),
.S_AXI_HP1_WREADY(NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED),
.S_AXI_HP1_WRISSUECAP1_EN(1'b0),
.S_AXI_HP1_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_WVALID(1'b0),
.S_AXI_HP2_ACLK(1'b0),
.S_AXI_HP2_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARBURST({1'b0,1'b0}),
.S_AXI_HP2_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARESETN(NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED),
.S_AXI_HP2_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARLOCK({1'b0,1'b0}),
.S_AXI_HP2_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARREADY(NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED),
.S_AXI_HP2_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARVALID(1'b0),
.S_AXI_HP2_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWBURST({1'b0,1'b0}),
.S_AXI_HP2_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWLOCK({1'b0,1'b0}),
.S_AXI_HP2_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWREADY(NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED),
.S_AXI_HP2_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWVALID(1'b0),
.S_AXI_HP2_BID(NLW_inst_S_AXI_HP2_BID_UNCONNECTED[5:0]),
.S_AXI_HP2_BREADY(1'b0),
.S_AXI_HP2_BRESP(NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP2_BVALID(NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED),
.S_AXI_HP2_RACOUNT(NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP2_RCOUNT(NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP2_RDATA(NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP2_RDISSUECAP1_EN(1'b0),
.S_AXI_HP2_RID(NLW_inst_S_AXI_HP2_RID_UNCONNECTED[5:0]),
.S_AXI_HP2_RLAST(NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED),
.S_AXI_HP2_RREADY(1'b0),
.S_AXI_HP2_RRESP(NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP2_RVALID(NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED),
.S_AXI_HP2_WACOUNT(NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP2_WCOUNT(NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP2_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_WLAST(1'b0),
.S_AXI_HP2_WREADY(NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED),
.S_AXI_HP2_WRISSUECAP1_EN(1'b0),
.S_AXI_HP2_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_WVALID(1'b0),
.S_AXI_HP3_ACLK(1'b0),
.S_AXI_HP3_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARBURST({1'b0,1'b0}),
.S_AXI_HP3_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARESETN(NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED),
.S_AXI_HP3_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARLOCK({1'b0,1'b0}),
.S_AXI_HP3_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARREADY(NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED),
.S_AXI_HP3_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARVALID(1'b0),
.S_AXI_HP3_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWBURST({1'b0,1'b0}),
.S_AXI_HP3_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWLOCK({1'b0,1'b0}),
.S_AXI_HP3_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWREADY(NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED),
.S_AXI_HP3_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWVALID(1'b0),
.S_AXI_HP3_BID(NLW_inst_S_AXI_HP3_BID_UNCONNECTED[5:0]),
.S_AXI_HP3_BREADY(1'b0),
.S_AXI_HP3_BRESP(NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP3_BVALID(NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED),
.S_AXI_HP3_RACOUNT(NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP3_RCOUNT(NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP3_RDATA(NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP3_RDISSUECAP1_EN(1'b0),
.S_AXI_HP3_RID(NLW_inst_S_AXI_HP3_RID_UNCONNECTED[5:0]),
.S_AXI_HP3_RLAST(NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED),
.S_AXI_HP3_RREADY(1'b0),
.S_AXI_HP3_RRESP(NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP3_RVALID(NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED),
.S_AXI_HP3_WACOUNT(NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP3_WCOUNT(NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP3_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_WLAST(1'b0),
.S_AXI_HP3_WREADY(NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED),
.S_AXI_HP3_WRISSUECAP1_EN(1'b0),
.S_AXI_HP3_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_WVALID(1'b0),
.TRACE_CLK(1'b0),
.TRACE_CLK_OUT(NLW_inst_TRACE_CLK_OUT_UNCONNECTED),
.TRACE_CTL(NLW_inst_TRACE_CTL_UNCONNECTED),
.TRACE_DATA(NLW_inst_TRACE_DATA_UNCONNECTED[1:0]),
.TTC0_CLK0_IN(1'b0),
.TTC0_CLK1_IN(1'b0),
.TTC0_CLK2_IN(1'b0),
.TTC0_WAVE0_OUT(TTC0_WAVE0_OUT),
.TTC0_WAVE1_OUT(TTC0_WAVE1_OUT),
.TTC0_WAVE2_OUT(TTC0_WAVE2_OUT),
.TTC1_CLK0_IN(1'b0),
.TTC1_CLK1_IN(1'b0),
.TTC1_CLK2_IN(1'b0),
.TTC1_WAVE0_OUT(NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED),
.TTC1_WAVE1_OUT(NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED),
.TTC1_WAVE2_OUT(NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED),
.UART0_CTSN(1'b0),
.UART0_DCDN(1'b0),
.UART0_DSRN(1'b0),
.UART0_DTRN(NLW_inst_UART0_DTRN_UNCONNECTED),
.UART0_RIN(1'b0),
.UART0_RTSN(NLW_inst_UART0_RTSN_UNCONNECTED),
.UART0_RX(1'b1),
.UART0_TX(NLW_inst_UART0_TX_UNCONNECTED),
.UART1_CTSN(1'b0),
.UART1_DCDN(1'b0),
.UART1_DSRN(1'b0),
.UART1_DTRN(NLW_inst_UART1_DTRN_UNCONNECTED),
.UART1_RIN(1'b0),
.UART1_RTSN(NLW_inst_UART1_RTSN_UNCONNECTED),
.UART1_RX(1'b1),
.UART1_TX(NLW_inst_UART1_TX_UNCONNECTED),
.USB0_PORT_INDCTL(USB0_PORT_INDCTL),
.USB0_VBUS_PWRFAULT(USB0_VBUS_PWRFAULT),
.USB0_VBUS_PWRSELECT(USB0_VBUS_PWRSELECT),
.USB1_PORT_INDCTL(NLW_inst_USB1_PORT_INDCTL_UNCONNECTED[1:0]),
.USB1_VBUS_PWRFAULT(1'b0),
.USB1_VBUS_PWRSELECT(NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED),
.WDT_CLK_IN(1'b0),
.WDT_RST_OUT(NLW_inst_WDT_RST_OUT_UNCONNECTED));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
// IP Revision: 9
(* X_CORE_INFO = "axi_protocol_converter_v2_1_9_axi_protocol_converter,Vivado 2016.2" *)
(* CHECK_LICENSE_TYPE = "dma_loopback_auto_pc_1,axi_protocol_converter_v2_1_9_axi_protocol_converter,{}" *)
(* CORE_GENERATION_INFO = "dma_loopback_auto_pc_1,axi_protocol_converter_v2_1_9_axi_protocol_converter,{x_ipProduct=Vivado 2016.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_protocol_converter,x_ipVersion=2.1,x_ipCoreRevision=9,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_M_AXI_PROTOCOL=0,C_S_AXI_PROTOCOL=1,C_IGNORE_ID=0,C_AXI_ID_WIDTH=12,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=32,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=1,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUS\
ER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_TRANSLATION_MODE=2}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module dma_loopback_auto_pc_1 (
aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
input wire [11 : 0] s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [3 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [1 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WID" *)
input wire [11 : 0] s_axi_wid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
output wire [11 : 0] s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
input wire [11 : 0] s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [3 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [1 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
output wire [11 : 0] s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWID" *)
output wire [11 : 0] m_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
output wire [7 : 0] m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
output wire [2 : 0] m_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
output wire [1 : 0] m_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
output wire [0 : 0] m_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
output wire [3 : 0] m_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREGION" *)
output wire [3 : 0] m_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
output wire [3 : 0] m_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [31 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [3 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
output wire m_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BID" *)
input wire [11 : 0] m_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARID" *)
output wire [11 : 0] m_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
output wire [7 : 0] m_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *)
output wire [2 : 0] m_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *)
output wire [1 : 0] m_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *)
output wire [0 : 0] m_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
output wire [3 : 0] m_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREGION" *)
output wire [3 : 0] m_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *)
output wire [3 : 0] m_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RID" *)
input wire [11 : 0] m_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [31 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
input wire m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_protocol_converter_v2_1_9_axi_protocol_converter #(
.C_FAMILY("zynq"),
.C_M_AXI_PROTOCOL(0),
.C_S_AXI_PROTOCOL(1),
.C_IGNORE_ID(0),
.C_AXI_ID_WIDTH(12),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(1),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_TRANSLATION_MODE(2)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(4'H0),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(s_axi_wid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(4'H0),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(m_axi_awid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(m_axi_awregion),
.m_axi_awqos(m_axi_awqos),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(m_axi_bid),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(m_axi_arid),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(m_axi_arlen),
.m_axi_arsize(m_axi_arsize),
.m_axi_arburst(m_axi_arburst),
.m_axi_arlock(m_axi_arlock),
.m_axi_arcache(m_axi_arcache),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(m_axi_arregion),
.m_axi_arqos(m_axi_arqos),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(m_axi_rid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(m_axi_rlast),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
`timescale 1ns/100ps
module cordic_pipelined(clk, z0, xn, yn);
parameter z_width = 12;
parameter iter_width = 17; // iteration width
input clk;
input signed [z_width:0] z0;
output reg signed [iter_width:0] xn, yn;
parameter N = 10; // number of iterations
reg [(N-1):0] d;
wire signed [iter_width:0] x [N:0];
wire signed [iter_width:0] y [N:0];
wire signed [z_width:0] z [N:0];
wire signed [z_width:0] current_angle;
assign x[0] = 'b01_0011_0110_1110_1001; // 0.60725 in binary
assign y[0] = 0;
assign current_angle = z0 - 'h0A0;
always @ (current_angle, x[N], y[N]) begin
// cordic only works in first and fourth quadrant
if (((current_angle[z_width]==1) && (current_angle < 'h1A60)) ||
((current_angle[z_width]==0) && (current_angle > 'h05A0))) begin // if < -90 || > +90
//$display("at 1");
// flip the sign for second or third quadrant using two-complement rule
xn = ~( x[N]-1 ); // xn = cos(z0)
yn = ~( y[N]-1 ); // yn = sin(z0)
end
else begin // z0 is already in first and fourth quadrant
xn = x[N]; // xn = cos(z0)
yn = y[N]; // yn = sin(z0)
end
end
always @ (z0) begin
if (((z0[z_width]==1) && (z0 < 'h1A60)) ||
((z0[z_width]==0) && (z0 > 'h05A0))) begin // if < -90 || > +90
if (z0[z_width] == 1) begin // if z0 < 0
z[0] = z0 + 'hB40; // third quadrant, so add 180 degrees
//$display("at 2");
end
else begin
z[0] = z0 - 'hB40; // second quadrant, so subtract 180 degrees
//$display("at 3");
end
end
else begin
z[0] = z0;
end
//$display("z[0] = ", z[0]);
end
wire signed [z_width:0] arctan [(N-1):0];
assign arctan[0] = 'b0_0010_1101_0000; // 45.000;
assign arctan[1] = 'b0_0001_1010_1001; // 26.565;
assign arctan[2] = 'b0_0000_1110_0000; // 14.036;
assign arctan[3] = 'b0_0000_0111_0010; // 7.1250;
assign arctan[4] = 'b0_0000_0011_1001; // 3.5763;
assign arctan[5] = 'b0_0000_0001_1100; // 1.7899;
assign arctan[6] = 'b0_0000_0000_1110; // 0.8952;
assign arctan[7] = 'b0_0000_0000_0111; // 0.4476;
assign arctan[8] = 'b0_0000_0000_0011; // 0.2238;
assign arctan[9] = 'b0_0000_0000_0001; // 0.1119;
genvar i;
generate
for(i=0; i<N; i=i+1)
begin: stage_generate
cordic_stage #(.i(i)) stage_i
(
.clk(clk),
.x_i(x[i]), .x_o(x[i+1]),
.y_i(y[i]), .y_o(y[i+1]),
.z_i(z[i]), .z_o(z[i+1]),
.arctan(arctan[i])
);
end
endgenerate
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Case Western Reserve University
// Engineer: David Ariando
//
// Create Date: 22:22:00 01/31/2018
// Project Name: EECS301 Digital Design
// Design Name: Lab #2 Project
// Module Name: TF_CLS_PWM_Interval_Timer.v
// Target Devices: Altera Cyclone V
// Tool versions: Quartus v17.1
// Description: CLS Scan Rate Timer Timer Testbench
//
// Dependencies:
//
//////////////////////////////////////////////////////////////////////////////////
module TF_CLS_Scan_Rate_Timer();
wire SRT_TICK;
reg CLOCK_50;
reg [1:0] RATE_SELECT;
//
// System Clock Emulation
//
// Toggle the CLOCK_50 signal every 10 ns to create to 50MHz clock signal
//
localparam CLK_RATE_HZ = 50000000; // Hz
localparam CLK_HALF_PER = ((1.0 / CLK_RATE_HZ) * 1000000000.0) / 2.0; // ns
initial
begin
CLOCK_50 = 1'b0;
forever #(CLK_HALF_PER) CLOCK_50 = ~CLOCK_50;
end
initial
begin
RATE_SELECT = 2'h0;
end
CLS_Scan_Rate_Timer
#(
.CLK_RATE_HZ (CLK_RATE_HZ) // Hz
)
uut
(
// Input Signals
.RATE_SELECT (RATE_SELECT),
// Output Signals
.SRT_TICK (SRT_TICK),
// System Signals
.CLK (CLOCK_50)
);
endmodule |
module VIDEO_OUT
(
pixel_clock,
reset,
vga_red_data,
vga_green_data,
vga_blue_data,
h_synch,
v_synch,
blank,
VGA_HSYNCH,
VGA_VSYNCH,
VGA_OUT_RED,
VGA_OUT_GREEN,
VGA_OUT_BLUE
);
input pixel_clock;
input reset;
input vga_red_data;
input vga_green_data;
input vga_blue_data;
input h_synch;
input v_synch;
input blank;
output VGA_HSYNCH;
output VGA_VSYNCH;
output VGA_OUT_RED;
output VGA_OUT_GREEN;
output VGA_OUT_BLUE;
reg VGA_HSYNCH;
reg VGA_VSYNCH;
reg VGA_OUT_RED;
reg VGA_OUT_GREEN;
reg VGA_OUT_BLUE;
// make the external video connections
always @ (posedge pixel_clock or posedge reset) begin
if (reset) begin
// shut down the video output during reset
VGA_HSYNCH <= 1'b1;
VGA_VSYNCH <= 1'b1;
VGA_OUT_RED <= 1'b0;
VGA_OUT_GREEN <= 1'b0;
VGA_OUT_BLUE <= 1'b0;
end
else if (blank) begin
// output black during the blank signal
VGA_HSYNCH <= h_synch;
VGA_VSYNCH <= v_synch;
VGA_OUT_RED <= 1'b0;
VGA_OUT_GREEN <= 1'b0;
VGA_OUT_BLUE <= 1'b0;
end
else begin
// output color data otherwise
VGA_HSYNCH <= h_synch;
VGA_VSYNCH <= v_synch;
VGA_OUT_RED <= vga_red_data;
VGA_OUT_GREEN <= vga_green_data;
VGA_OUT_BLUE <= vga_blue_data;
end
end
endmodule // VIDEO_OUT |
/*
* This tests the latching of an output that isn't really an output,
* but an intermediate symbol that is only used in some clauses.
*/
module main;
reg [15:0] out, a;
reg [7:0] b;
reg cy;
reg with_carry;
(* ivl_combinational *)
always @(with_carry, a, b, cy)
case (with_carry)
1'b1:
begin
{cy, out[7:0]} = {1'b0, a[7:0]} + {1'b0, b[7:0]};
out[15:8] = a[15:8] + {7'b0, cy};
end
1'b0:
begin
out = a + {8'h00, b};
end
endcase
(* ivl_synthesis_off *)
initial begin
a = 16'h00fe;
b = 8'h00;
with_carry = 0;
#1 if (out !== 16'h00fe) begin
$display("FAILED -- a=%h, b=%h, out=%h", a, b, out);
$finish;
end
with_carry = 1;
#1 if (out !== 16'h00fe) begin
$display("FAILED -- a=%h, b=%h, out=%h", a, b, out);
$finish;
end
b = 2;
#1 if (out !== 16'h0100) begin
$display("FAILED -- a=%h, b=%h, out=%h", a, b, out);
$finish;
end
with_carry = 0;
#1 if (out !== 16'h0100) begin
$display("FAILED -- a=%h, b=%h, out=%h", a, b, out);
$finish;
end
$display("PASSED");
end
endmodule // main
|
/*****************************************************************************
* File : processing_system7_vip_v1_0_5_unused_ports.v
*
* Date : 2012-11
*
* Description : Semantic checks for unused ports.
*
*****************************************************************************/
/* CAN */
assign CAN0_PHY_TX = 0;
assign CAN1_PHY_TX = 0;
always @(CAN0_PHY_RX or CAN1_PHY_RX)
begin
if(CAN0_PHY_RX | CAN1_PHY_RX)
$display("[%0d] : %0s : CAN Interface is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* ETHERNET */
/* ------------------------------------------- */
assign ENET0_GMII_TX_EN = 0;
assign ENET0_GMII_TX_ER = 0;
assign ENET0_MDIO_MDC = 0;
assign ENET0_MDIO_O = 0; /// confirm
assign ENET0_MDIO_T = 0;
assign ENET0_PTP_DELAY_REQ_RX = 0;
assign ENET0_PTP_DELAY_REQ_TX = 0;
assign ENET0_PTP_PDELAY_REQ_RX = 0;
assign ENET0_PTP_PDELAY_REQ_TX = 0;
assign ENET0_PTP_PDELAY_RESP_RX = 0;
assign ENET0_PTP_PDELAY_RESP_TX = 0;
assign ENET0_PTP_SYNC_FRAME_RX = 0;
assign ENET0_PTP_SYNC_FRAME_TX = 0;
assign ENET0_SOF_RX = 0;
assign ENET0_SOF_TX = 0;
assign ENET0_GMII_TXD = 0;
always@(ENET0_GMII_COL or ENET0_GMII_CRS or ENET0_EXT_INTIN or
ENET0_GMII_RX_CLK or ENET0_GMII_RX_DV or ENET0_GMII_RX_ER or
ENET0_GMII_TX_CLK or ENET0_MDIO_I or ENET0_GMII_RXD)
begin
if(ENET0_GMII_COL | ENET0_GMII_CRS | ENET0_EXT_INTIN |
ENET0_GMII_RX_CLK | ENET0_GMII_RX_DV | ENET0_GMII_RX_ER |
ENET0_GMII_TX_CLK | ENET0_MDIO_I )
$display("[%0d] : %0s : ETHERNET Interface is not supported.",$time, DISP_ERR);
end
assign ENET1_GMII_TX_EN = 0;
assign ENET1_GMII_TX_ER = 0;
assign ENET1_MDIO_MDC = 0;
assign ENET1_MDIO_O = 0;/// confirm
assign ENET1_MDIO_T = 0;
assign ENET1_PTP_DELAY_REQ_RX = 0;
assign ENET1_PTP_DELAY_REQ_TX = 0;
assign ENET1_PTP_PDELAY_REQ_RX = 0;
assign ENET1_PTP_PDELAY_REQ_TX = 0;
assign ENET1_PTP_PDELAY_RESP_RX = 0;
assign ENET1_PTP_PDELAY_RESP_TX = 0;
assign ENET1_PTP_SYNC_FRAME_RX = 0;
assign ENET1_PTP_SYNC_FRAME_TX = 0;
assign ENET1_SOF_RX = 0;
assign ENET1_SOF_TX = 0;
assign ENET1_GMII_TXD = 0;
always@(ENET1_GMII_COL or ENET1_GMII_CRS or ENET1_EXT_INTIN or
ENET1_GMII_RX_CLK or ENET1_GMII_RX_DV or ENET1_GMII_RX_ER or
ENET1_GMII_TX_CLK or ENET1_MDIO_I or ENET1_GMII_RXD)
begin
if(ENET1_GMII_COL | ENET1_GMII_CRS | ENET1_EXT_INTIN |
ENET1_GMII_RX_CLK | ENET1_GMII_RX_DV | ENET1_GMII_RX_ER |
ENET1_GMII_TX_CLK | ENET1_MDIO_I )
$display("[%0d] : %0s : ETHERNET Interface is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* GPIO */
/* ------------------------------------------- */
assign GPIO_O = 0;
assign GPIO_T = 0;
always@(GPIO_I)
begin
if(GPIO_I !== 0)
$display("[%0d] : %0s : GPIO Interface is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* I2C */
/* ------------------------------------------- */
assign I2C0_SDA_O = 0;
assign I2C0_SDA_T = 0;
assign I2C0_SCL_O = 0;
assign I2C0_SCL_T = 0;
assign I2C1_SDA_O = 0;
assign I2C1_SDA_T = 0;
assign I2C1_SCL_O = 0;
assign I2C1_SCL_T = 0;
always@(I2C0_SDA_I or I2C0_SCL_I or I2C1_SDA_I or I2C1_SCL_I )
begin
if(I2C0_SDA_I | I2C0_SCL_I | I2C1_SDA_I | I2C1_SCL_I)
$display("[%0d] : %0s : I2C Interface is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* JTAG */
/* ------------------------------------------- */
assign PJTAG_TD_T = 0;
assign PJTAG_TD_O = 0;
always@(PJTAG_TCK or PJTAG_TMS or PJTAG_TD_I)
begin
if(PJTAG_TCK | PJTAG_TMS | PJTAG_TD_I)
$display("[%0d] : %0s : JTAG Interface is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* SDIO */
/* ------------------------------------------- */
assign SDIO0_CLK = 0;
assign SDIO0_CMD_O = 0;
assign SDIO0_CMD_T = 0;
assign SDIO0_DATA_O = 0;
assign SDIO0_DATA_T = 0;
assign SDIO0_LED = 0;
assign SDIO0_BUSPOW = 0;
assign SDIO0_BUSVOLT = 0;
always@(SDIO0_CLK_FB or SDIO0_CMD_I or SDIO0_DATA_I or SDIO0_CDN or SDIO0_WP )
begin
if(SDIO0_CLK_FB | SDIO0_CMD_I | SDIO0_CDN | SDIO0_WP )
$display("[%0d] : %0s : SDIO Interface is not supported.",$time, DISP_ERR);
end
assign SDIO1_CLK = 0;
assign SDIO1_CMD_O = 0;
assign SDIO1_CMD_T = 0;
assign SDIO1_DATA_O = 0;
assign SDIO1_DATA_T = 0;
assign SDIO1_LED = 0;
assign SDIO1_BUSPOW = 0;
assign SDIO1_BUSVOLT = 0;
always@(SDIO1_CLK_FB or SDIO1_CMD_I or SDIO1_DATA_I or SDIO1_CDN or SDIO1_WP )
begin
if(SDIO1_CLK_FB | SDIO1_CMD_I | SDIO1_CDN | SDIO1_WP )
$display("[%0d] : %0s : SDIO Interface is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* SPI */
/* ------------------------------------------- */
assign SPI0_SCLK_O = 0;
assign SPI0_SCLK_T = 0;
assign SPI0_MOSI_O = 0;
assign SPI0_MOSI_T = 0;
assign SPI0_MISO_O = 0;
assign SPI0_MISO_T = 0;
assign SPI0_SS_O = 0; /// confirm
assign SPI0_SS1_O = 0;/// confirm
assign SPI0_SS2_O = 0;/// confirm
assign SPI0_SS_T = 0;
always@(SPI0_SCLK_I or SPI0_MOSI_I or SPI0_MISO_I or SPI0_SS_I)
begin
if(SPI0_SCLK_I | SPI0_MOSI_I | SPI0_MISO_I | SPI0_SS_I)
$display("[%0d] : %0s : SPI Interface is not supported.",$time, DISP_ERR);
end
assign SPI1_SCLK_O = 0;
assign SPI1_SCLK_T = 0;
assign SPI1_MOSI_O = 0;
assign SPI1_MOSI_T = 0;
assign SPI1_MISO_O = 0;
assign SPI1_MISO_T = 0;
assign SPI1_SS_O = 0;
assign SPI1_SS1_O = 0;
assign SPI1_SS2_O = 0;
assign SPI1_SS_T = 0;
always@(SPI1_SCLK_I or SPI1_MOSI_I or SPI1_MISO_I or SPI1_SS_I)
begin
if(SPI1_SCLK_I | SPI1_MOSI_I | SPI1_MISO_I | SPI1_SS_I)
$display("[%0d] : %0s : SPI Interface is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* UART */
/* ------------------------------------------- */
/// confirm
assign UART0_DTRN = 0;
assign UART0_RTSN = 0;
assign UART0_TX = 0;
always@(UART0_CTSN or UART0_DCDN or UART0_DSRN or UART0_RIN or UART0_RX)
begin
if(UART0_CTSN | UART0_DCDN | UART0_DSRN | UART0_RIN | UART0_RX)
$display("[%0d] : %0s : UART Interface is not supported.",$time, DISP_ERR);
end
assign UART1_DTRN = 0;
assign UART1_RTSN = 0;
assign UART1_TX = 0;
always@(UART1_CTSN or UART1_DCDN or UART1_DSRN or UART1_RIN or UART1_RX)
begin
if(UART1_CTSN | UART1_DCDN | UART1_DSRN | UART1_RIN | UART1_RX)
$display("[%0d] : %0s : UART Interface is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* TTC */
/* ------------------------------------------- */
assign TTC0_WAVE0_OUT = 0;
assign TTC0_WAVE1_OUT = 0;
assign TTC0_WAVE2_OUT = 0;
always@(TTC0_CLK0_IN or TTC0_CLK1_IN or TTC0_CLK2_IN)
begin
if(TTC0_CLK0_IN | TTC0_CLK1_IN | TTC0_CLK2_IN)
$display("[%0d] : %0s : TTC Interface is not supported.",$time, DISP_ERR);
end
assign TTC1_WAVE0_OUT = 0;
assign TTC1_WAVE1_OUT = 0;
assign TTC1_WAVE2_OUT = 0;
always@(TTC1_CLK0_IN or TTC1_CLK1_IN or TTC1_CLK2_IN)
begin
if(TTC1_CLK0_IN | TTC1_CLK1_IN | TTC1_CLK2_IN)
$display("[%0d] : %0s : TTC Interface is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* WDT */
/* ------------------------------------------- */
assign WDT_RST_OUT = 0;
always@(WDT_CLK_IN)
begin
if(WDT_CLK_IN)
$display("[%0d] : %0s : WDT Interface is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* TRACE */
/* ------------------------------------------- */
assign TRACE_CTL = 0;
assign TRACE_DATA = 0;
always@(TRACE_CLK)
begin
if(TRACE_CLK)
$display("[%0d] : %0s : TRACE Interface is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* USB */
/* ------------------------------------------- */
assign USB0_PORT_INDCTL = 0;
assign USB0_VBUS_PWRSELECT = 0;
always@(USB0_VBUS_PWRFAULT)
begin
if(USB0_VBUS_PWRFAULT)
$display("[%0d] : %0s : USB Interface is not supported.",$time, DISP_ERR);
end
assign USB1_PORT_INDCTL = 0;
assign USB1_VBUS_PWRSELECT = 0;
always@(USB1_VBUS_PWRFAULT)
begin
if(USB1_VBUS_PWRFAULT)
$display("[%0d] : %0s : USB Interface is not supported.",$time, DISP_ERR);
end
always@(SRAM_INTIN)
begin
if(SRAM_INTIN)
$display("[%0d] : %0s : SRAM_INTIN is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* DMA */
/* ------------------------------------------- */
assign DMA0_DATYPE = 0;
assign DMA0_DAVALID = 0;
assign DMA0_DRREADY = 0;
assign DMA0_RSTN = 0;
always@(DMA0_ACLK or DMA0_DAREADY or DMA0_DRLAST or DMA0_DRVALID or DMA0_DRTYPE)
begin
if(DMA0_ACLK | DMA0_DAREADY | DMA0_DRLAST | DMA0_DRVALID | DMA0_DRTYPE)
$display("[%0d] : %0s : DMA Interface is not supported.",$time, DISP_ERR);
end
assign DMA1_DATYPE = 0;
assign DMA1_DAVALID = 0;
assign DMA1_DRREADY = 0;
assign DMA1_RSTN = 0;
always@(DMA1_ACLK or DMA1_DAREADY or DMA1_DRLAST or DMA1_DRVALID or DMA1_DRTYPE)
begin
if(DMA1_ACLK | DMA1_DAREADY | DMA1_DRLAST | DMA1_DRVALID | DMA1_DRTYPE)
$display("[%0d] : %0s : DMA Interface is not supported.",$time, DISP_ERR);
end
assign DMA2_DATYPE = 0;
assign DMA2_DAVALID = 0;
assign DMA2_DRREADY = 0;
assign DMA2_RSTN = 0;
always@(DMA2_ACLK or DMA2_DAREADY or DMA2_DRLAST or DMA2_DRVALID or DMA2_DRTYPE)
begin
if(DMA2_ACLK | DMA2_DAREADY | DMA2_DRLAST | DMA2_DRVALID | DMA2_DRTYPE)
$display("[%0d] : %0s : DMA Interface is not supported.",$time, DISP_ERR);
end
assign DMA3_DATYPE = 0;
assign DMA3_DAVALID = 0;
assign DMA3_DRREADY = 0;
assign DMA3_RSTN = 0;
always@(DMA3_ACLK or DMA3_DAREADY or DMA3_DRLAST or DMA3_DRVALID or DMA3_DRTYPE)
begin
if(DMA3_ACLK | DMA3_DAREADY | DMA3_DRLAST | DMA3_DRVALID | DMA3_DRTYPE)
$display("[%0d] : %0s : DMA Interface is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* FTM */
/* ------------------------------------------- */
assign FTMT_F2P_TRIGACK = 0;
assign FTMT_P2F_TRIG = 0;
assign FTMT_P2F_DEBUG = 0;
always@(FTMD_TRACEIN_DATA or FTMD_TRACEIN_VALID or FTMD_TRACEIN_CLK or
FTMD_TRACEIN_ATID or FTMT_F2P_TRIG or FTMT_F2P_DEBUG or FTMT_P2F_TRIGACK)
begin
if(FTMD_TRACEIN_DATA | FTMD_TRACEIN_VALID | FTMD_TRACEIN_CLK | FTMD_TRACEIN_ATID | FTMT_F2P_TRIG | FTMT_F2P_DEBUG | FTMT_P2F_TRIGACK)
$display("[%0d] : %0s : FTM Interface is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* EVENT */
/* ------------------------------------------- */
assign EVENT_EVENTO = 0;
assign EVENT_STANDBYWFE = 0;
assign EVENT_STANDBYWFI = 0;
always@(EVENT_EVENTI)
begin
if(EVENT_EVENTI)
$display("[%0d] : %0s : EVENT Interface is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* MIO */
/* ------------------------------------------- */
always@(MIO)
begin
if(MIO !== 0)
$display("[%0d] : %0s : MIO is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* FCLK_TRIG */
/* ------------------------------------------- */
always@(FCLK_CLKTRIG3_N or FCLK_CLKTRIG2_N or FCLK_CLKTRIG1_N or FCLK_CLKTRIG0_N )
begin
if(FCLK_CLKTRIG3_N | FCLK_CLKTRIG2_N | FCLK_CLKTRIG1_N | FCLK_CLKTRIG0_N )
$display("[%0d] : %0s : FCLK_TRIG is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* MISC */
/* ------------------------------------------- */
always@(FPGA_IDLE_N)
begin
if(FPGA_IDLE_N)
$display("[%0d] : %0s : FPGA_IDLE_N is not supported.",$time, DISP_ERR);
end
always@(DDR_ARB)
begin
if(DDR_ARB !== 0)
$display("[%0d] : %0s : DDR_ARB is not supported.",$time, DISP_ERR);
end
always@(Core0_nFIQ or Core0_nIRQ or Core1_nFIQ or Core1_nIRQ )
begin
if(Core0_nFIQ | Core0_nIRQ | Core1_nFIQ | Core1_nIRQ)
$display("[%0d] : %0s : CORE FIQ,IRQ is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* DDR */
/* ------------------------------------------- */
assign DDR_WEB = 0;
always@(DDR_Clk or DDR_CS_n)
begin
if(!DDR_CS_n)
$display("[%0d] : %0s : EXTERNAL DDR is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* IRQ_P2F */
/* ------------------------------------------- */
assign IRQ_P2F_DMAC_ABORT = 0;
assign IRQ_P2F_DMAC0 = 0;
assign IRQ_P2F_DMAC1 = 0;
assign IRQ_P2F_DMAC2 = 0;
assign IRQ_P2F_DMAC3 = 0;
assign IRQ_P2F_DMAC4 = 0;
assign IRQ_P2F_DMAC5 = 0;
assign IRQ_P2F_DMAC6 = 0;
assign IRQ_P2F_DMAC7 = 0;
assign IRQ_P2F_SMC = 0;
assign IRQ_P2F_QSPI = 0;
assign IRQ_P2F_CTI = 0;
assign IRQ_P2F_GPIO = 0;
assign IRQ_P2F_USB0 = 0;
assign IRQ_P2F_ENET0 = 0;
assign IRQ_P2F_ENET_WAKE0 = 0;
assign IRQ_P2F_SDIO0 = 0;
assign IRQ_P2F_I2C0 = 0;
assign IRQ_P2F_SPI0 = 0;
assign IRQ_P2F_UART0 = 0;
assign IRQ_P2F_CAN0 = 0;
assign IRQ_P2F_USB1 = 0;
assign IRQ_P2F_ENET1 = 0;
assign IRQ_P2F_ENET_WAKE1 = 0;
assign IRQ_P2F_SDIO1 = 0;
assign IRQ_P2F_I2C1 = 0;
assign IRQ_P2F_SPI1 = 0;
assign IRQ_P2F_UART1 = 0;
assign IRQ_P2F_CAN1 = 0;
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_hcmd_sq_arb # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
input pcie_user_clk,
input pcie_user_rst_n,
input [8:0] sq_rst_n,
input [8:0] sq_valid,
input [7:0] admin_sq_size,
input [7:0] io_sq1_size,
input [7:0] io_sq2_size,
input [7:0] io_sq3_size,
input [7:0] io_sq4_size,
input [7:0] io_sq5_size,
input [7:0] io_sq6_size,
input [7:0] io_sq7_size,
input [7:0] io_sq8_size,
input [C_PCIE_ADDR_WIDTH-1:2] admin_sq_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq1_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq2_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq3_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq4_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq5_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq6_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq7_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq8_bs_addr,
input [7:0] admin_sq_tail_ptr,
input [7:0] io_sq1_tail_ptr,
input [7:0] io_sq2_tail_ptr,
input [7:0] io_sq3_tail_ptr,
input [7:0] io_sq4_tail_ptr,
input [7:0] io_sq5_tail_ptr,
input [7:0] io_sq6_tail_ptr,
input [7:0] io_sq7_tail_ptr,
input [7:0] io_sq8_tail_ptr,
output arb_sq_rdy,
output [3:0] sq_qid,
output [C_PCIE_ADDR_WIDTH-1:2] hcmd_pcie_addr,
input sq_hcmd_ack
);
localparam S_ARB_HCMD = 5'b00001;
localparam S_LOAD_HEAD_PTR = 5'b00010;
localparam S_CALC_ADDR = 5'b00100;
localparam S_GNT_HCMD = 5'b01000;
localparam S_UPDATE_HEAD_PTR = 5'b10000;
reg [4:0] cur_state;
reg [4:0] next_state;
reg [7:0] r_admin_sq_head_ptr;
reg [7:0] r_io_sq1_head_ptr;
reg [7:0] r_io_sq2_head_ptr;
reg [7:0] r_io_sq3_head_ptr;
reg [7:0] r_io_sq4_head_ptr;
reg [7:0] r_io_sq5_head_ptr;
reg [7:0] r_io_sq6_head_ptr;
reg [7:0] r_io_sq7_head_ptr;
reg [7:0] r_io_sq8_head_ptr;
reg r_arb_sq_rdy;
reg [3:0] r_sq_qid;
reg [7:0] r_sq_head_ptr;
reg [C_PCIE_ADDR_WIDTH-1:2] r_hcmd_pcie_addr;
wire [8:0] w_sq_entry_valid;
wire w_sq_entry_valid_ok;
reg [8:0] r_sq_entry_valid;
wire [8:0] w_sq_valid_mask;
reg [8:0] r_sq_update_entry;
wire [8:0] w_sq_rst_n;
assign arb_sq_rdy = r_arb_sq_rdy;
assign sq_qid = r_sq_qid;
assign hcmd_pcie_addr = r_hcmd_pcie_addr;
assign w_sq_entry_valid[0] = (r_admin_sq_head_ptr != admin_sq_tail_ptr) & sq_valid[0];
assign w_sq_entry_valid[1] = (r_io_sq1_head_ptr != io_sq1_tail_ptr) & sq_valid[1];
assign w_sq_entry_valid[2] = (r_io_sq2_head_ptr != io_sq2_tail_ptr) & sq_valid[2];
assign w_sq_entry_valid[3] = (r_io_sq3_head_ptr != io_sq3_tail_ptr) & sq_valid[3];
assign w_sq_entry_valid[4] = (r_io_sq4_head_ptr != io_sq4_tail_ptr) & sq_valid[4];
assign w_sq_entry_valid[5] = (r_io_sq5_head_ptr != io_sq5_tail_ptr) & sq_valid[5];
assign w_sq_entry_valid[6] = (r_io_sq6_head_ptr != io_sq6_tail_ptr) & sq_valid[6];
assign w_sq_entry_valid[7] = (r_io_sq7_head_ptr != io_sq7_tail_ptr) & sq_valid[7];
assign w_sq_entry_valid[8] = (r_io_sq8_head_ptr != io_sq8_tail_ptr) & sq_valid[8];
assign w_sq_valid_mask = {r_sq_entry_valid[7:0], r_sq_entry_valid[8]};
assign w_sq_entry_valid_ok = ((w_sq_entry_valid[8:1] & w_sq_valid_mask[8:1]) != 0) | w_sq_entry_valid[0];
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0)
cur_state <= S_ARB_HCMD;
else
cur_state <= next_state;
end
always @ (*)
begin
case(cur_state)
S_ARB_HCMD: begin
if(w_sq_entry_valid_ok == 1)
next_state <= S_LOAD_HEAD_PTR;
else
next_state <= S_ARB_HCMD;
end
S_LOAD_HEAD_PTR: begin
next_state <= S_CALC_ADDR;
end
S_CALC_ADDR: begin
next_state <= S_GNT_HCMD;
end
S_GNT_HCMD: begin
if(sq_hcmd_ack == 1)
next_state <= S_UPDATE_HEAD_PTR;
else
next_state <= S_GNT_HCMD;
end
S_UPDATE_HEAD_PTR: begin
next_state <= S_ARB_HCMD;
end
default: begin
next_state <= S_ARB_HCMD;
end
endcase
end
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0) begin
r_sq_entry_valid <= 1;
end
else begin
case(cur_state)
S_ARB_HCMD: begin
if(w_sq_entry_valid[0] == 1)
r_sq_entry_valid <= 1;
else
r_sq_entry_valid <= w_sq_valid_mask;
end
S_LOAD_HEAD_PTR: begin
end
S_CALC_ADDR: begin
end
S_GNT_HCMD: begin
end
S_UPDATE_HEAD_PTR: begin
end
default: begin
end
endcase
end
end
always @ (posedge pcie_user_clk)
begin
case(cur_state)
S_ARB_HCMD: begin
end
S_LOAD_HEAD_PTR: begin
case(r_sq_entry_valid) // synthesis parallel_case full_case
9'b000000001: begin
r_hcmd_pcie_addr <= admin_sq_bs_addr;
r_sq_head_ptr <= r_admin_sq_head_ptr;
end
9'b000000010: begin
r_hcmd_pcie_addr <= io_sq1_bs_addr;
r_sq_head_ptr <= r_io_sq1_head_ptr;
end
9'b000000100: begin
r_hcmd_pcie_addr <= io_sq2_bs_addr;
r_sq_head_ptr <= r_io_sq2_head_ptr;
end
9'b000001000: begin
r_hcmd_pcie_addr <= io_sq3_bs_addr;
r_sq_head_ptr <= r_io_sq3_head_ptr;
end
9'b000010000: begin
r_hcmd_pcie_addr <= io_sq4_bs_addr;
r_sq_head_ptr <= r_io_sq4_head_ptr;
end
9'b000100000: begin
r_hcmd_pcie_addr <= io_sq5_bs_addr;
r_sq_head_ptr <= r_io_sq5_head_ptr;
end
9'b001000000: begin
r_hcmd_pcie_addr <= io_sq6_bs_addr;
r_sq_head_ptr <= r_io_sq6_head_ptr;
end
9'b010000000: begin
r_hcmd_pcie_addr <= io_sq7_bs_addr;
r_sq_head_ptr <= r_io_sq7_head_ptr;
end
9'b100000000: begin
r_hcmd_pcie_addr <= io_sq8_bs_addr;
r_sq_head_ptr <= r_io_sq8_head_ptr;
end
endcase
end
S_CALC_ADDR: begin
r_hcmd_pcie_addr <= r_hcmd_pcie_addr + {r_sq_head_ptr, 4'b0};
r_sq_head_ptr <= r_sq_head_ptr + 1;
end
S_GNT_HCMD: begin
end
S_UPDATE_HEAD_PTR: begin
end
default: begin
end
endcase
end
always @ (*)
begin
case(cur_state)
S_ARB_HCMD: begin
r_arb_sq_rdy <= 0;
r_sq_update_entry <= 0;
end
S_LOAD_HEAD_PTR: begin
r_arb_sq_rdy <= 0;
r_sq_update_entry <= 0;
end
S_CALC_ADDR: begin
r_arb_sq_rdy <= 0;
r_sq_update_entry <= 0;
end
S_GNT_HCMD: begin
r_arb_sq_rdy <= 1;
r_sq_update_entry <= 0;
end
S_UPDATE_HEAD_PTR: begin
r_arb_sq_rdy <= 0;
r_sq_update_entry <= r_sq_entry_valid;
end
default: begin
r_arb_sq_rdy <= 0;
r_sq_update_entry <= 0;
end
endcase
end
always @ (*)
begin
case(r_sq_entry_valid) // synthesis parallel_case full_case
9'b000000001: r_sq_qid <= 4'h0;
9'b000000010: r_sq_qid <= 4'h1;
9'b000000100: r_sq_qid <= 4'h2;
9'b000001000: r_sq_qid <= 4'h3;
9'b000010000: r_sq_qid <= 4'h4;
9'b000100000: r_sq_qid <= 4'h5;
9'b001000000: r_sq_qid <= 4'h6;
9'b010000000: r_sq_qid <= 4'h7;
9'b100000000: r_sq_qid <= 4'h8;
endcase
end
assign w_sq_rst_n[0] = pcie_user_rst_n & sq_rst_n[0];
assign w_sq_rst_n[1] = pcie_user_rst_n & sq_rst_n[1];
assign w_sq_rst_n[2] = pcie_user_rst_n & sq_rst_n[2];
assign w_sq_rst_n[3] = pcie_user_rst_n & sq_rst_n[3];
assign w_sq_rst_n[4] = pcie_user_rst_n & sq_rst_n[4];
assign w_sq_rst_n[5] = pcie_user_rst_n & sq_rst_n[5];
assign w_sq_rst_n[6] = pcie_user_rst_n & sq_rst_n[6];
assign w_sq_rst_n[7] = pcie_user_rst_n & sq_rst_n[7];
assign w_sq_rst_n[8] = pcie_user_rst_n & sq_rst_n[8];
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[0])
begin
if(w_sq_rst_n[0] == 0) begin
r_admin_sq_head_ptr <= 0;
end
else begin
if(r_sq_update_entry[0] == 1) begin
if(r_admin_sq_head_ptr == admin_sq_size) begin
r_admin_sq_head_ptr <= 0;
end
else begin
r_admin_sq_head_ptr <= r_sq_head_ptr;
end
end
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[1])
begin
if(w_sq_rst_n[1] == 0) begin
r_io_sq1_head_ptr <= 0;
end
else begin
if(r_sq_update_entry[1] == 1) begin
if(r_io_sq1_head_ptr == io_sq1_size) begin
r_io_sq1_head_ptr <= 0;
end
else begin
r_io_sq1_head_ptr <= r_sq_head_ptr;
end
end
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[2])
begin
if(w_sq_rst_n[2] == 0) begin
r_io_sq2_head_ptr <= 0;
end
else begin
if(r_sq_update_entry[2] == 1) begin
if(r_io_sq2_head_ptr == io_sq2_size) begin
r_io_sq2_head_ptr <= 0;
end
else begin
r_io_sq2_head_ptr <= r_sq_head_ptr;
end
end
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[3])
begin
if(w_sq_rst_n[3] == 0) begin
r_io_sq3_head_ptr <= 0;
end
else begin
if(r_sq_update_entry[3] == 1) begin
if(r_io_sq3_head_ptr == io_sq3_size) begin
r_io_sq3_head_ptr <= 0;
end
else begin
r_io_sq3_head_ptr <= r_sq_head_ptr;
end
end
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[4])
begin
if(w_sq_rst_n[4] == 0) begin
r_io_sq4_head_ptr <= 0;
end
else begin
if(r_sq_update_entry[4] == 1) begin
if(r_io_sq4_head_ptr == io_sq4_size) begin
r_io_sq4_head_ptr <= 0;
end
else begin
r_io_sq4_head_ptr <= r_sq_head_ptr;
end
end
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[5])
begin
if(w_sq_rst_n[5] == 0) begin
r_io_sq5_head_ptr <= 0;
end
else begin
if(r_sq_update_entry[5] == 1) begin
if(r_io_sq5_head_ptr == io_sq5_size) begin
r_io_sq5_head_ptr <= 0;
end
else begin
r_io_sq5_head_ptr <= r_sq_head_ptr;
end
end
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[6])
begin
if(w_sq_rst_n[6] == 0) begin
r_io_sq6_head_ptr <= 0;
end
else begin
if(r_sq_update_entry[6] == 1) begin
if(r_io_sq6_head_ptr == io_sq6_size) begin
r_io_sq6_head_ptr <= 0;
end
else begin
r_io_sq6_head_ptr <= r_sq_head_ptr;
end
end
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[7])
begin
if(w_sq_rst_n[7] == 0) begin
r_io_sq7_head_ptr <= 0;
end
else begin
if(r_sq_update_entry[7] == 1) begin
if(r_io_sq7_head_ptr == io_sq7_size) begin
r_io_sq7_head_ptr <= 0;
end
else begin
r_io_sq7_head_ptr <= r_sq_head_ptr;
end
end
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[8])
begin
if(w_sq_rst_n[8] == 0) begin
r_io_sq8_head_ptr <= 0;
end
else begin
if(r_sq_update_entry[8] == 1) begin
if(r_io_sq8_head_ptr == io_sq8_size) begin
r_io_sq8_head_ptr <= 0;
end
else begin
r_io_sq8_head_ptr <= r_sq_head_ptr;
end
end
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLYGATE4SD3_FUNCTIONAL_V
`define SKY130_FD_SC_LS__DLYGATE4SD3_FUNCTIONAL_V
/**
* dlygate4sd3: Delay Buffer 4-stage 0.50um length inner stage gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__dlygate4sd3 (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLYGATE4SD3_FUNCTIONAL_V |
// DESCRIPTION: Verilator: Check initialisation of cloned clock variables
//
// This tests issue 1327 (Strange initialisation behaviour with
// "VinpClk" cloned clock variables)
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2018 by Rupert Swarbrick (Argon Design).
// SPDX-License-Identifier: CC0-1.0
// bug1327
// This models some device under test with an asynchronous reset pin
// which counts to 15.
module dut (input wire clk,
input wire rst_n,
output wire done);
reg [3:0] counter;
always @(posedge clk or negedge rst_n) begin
if (rst_n & ! clk) begin
$display("[%0t] %%Error: Oh dear! 'always @(posedge clk or negedge rst_n)' block triggered with clk=%0d, rst_n=%0d.",
$time, clk, rst_n);
$stop;
end
if (! rst_n) begin
counter <= 4'd0;
end else begin
counter <= counter < 4'd15 ? counter + 4'd1 : counter;
end
end
assign done = rst_n & (counter == 4'd15);
endmodule
module t(input wire clk,
input wire rst_n);
wire dut_done;
// A small FSM for driving the test
//
// This is just designed to be enough to force Verilator to make a
// "VinpClk" variant of dut_rst_n.
// Possible states:
//
// 0: Device in reset
// 1: Device running
// 2: Device finished
reg [1:0] state;
always @(posedge clk or negedge rst_n) begin
if (! rst_n) begin
state <= 0;
end else begin
if (state == 2'd0) begin
// One clock after resetting the device, we switch to running
// it.
state <= 2'd1;
end
else if (state == 2'd1) begin
// If the device is running, we switch to finished when its
// done signal goes high.
state <= dut_done ? 2'd2 : 2'd1;
end
else begin
// If the dut has finished, the test is done.
$write("*-* All Finished *-*\n");
$finish;
end
end
end
wire dut_rst_n = rst_n & (state != 0);
wire done;
dut dut_i (.clk (clk),
.rst_n (dut_rst_n),
.done (dut_done));
endmodule
|
/***********************************************************************
SPI Master
This file is part FPGA Libre project http://fpgalibre.sf.net/
Description:
Configurable Master Serial Protocol Interface controller.
This is different than SPI_controller:
- Modes can be configured with signals, not just generics.
- The SS logic is left to the upper level.
- We always return to IDLE before transmitting again.
- IMPORTANT! assumes that start_i resets the ena_i generator. In
this way start_i can last 1 clock cycle (no need to wait for
busy_o to become 1).
To Do:
-
Author:
- Salvador E. Tropea, salvador en inti gob ar
------------------------------------------------------------------------------
Copyright (c) 2017 Salvador E. Tropea <salvador en inti gob ar>
Copyright (c) 2017 Instituto Nacional de Tecnología Industrial
Distributed under the GPL v2 or newer license
------------------------------------------------------------------------------
Design unit: SPI_Master(RTL) (Entity and architecture)
File name: spi_master.v
Note: None
Limitations: None known
Errors: None known
Library: None
Dependencies: IEEE.std_logic_1164
IEEE.numeric_std
Target FPGA:
Language: Verilog
Wishbone: None
Synthesis tools:
Simulation tools: GHDL [Sokcho edition] (0.2x)
Text editor: SETEdit 0.5.x
***********************************************************************/
localparam integer CNT_BITS=$clog2(DATA_W);
localparam IDLE=0, LEADING_SCLK=1, TRAILING_SCLK=2, STOP=3; // state_t
reg [DATA_W-1:0] reg_r=0;
reg sclk_r=0;
reg [CNT_BITS-1:0] bit_cnt=0;
reg [1:0] state=IDLE; // states for shifter_FSM.
reg miso_r; // Sampled MISO
reg irq_r;
always @(posedge clk_i)
begin : shifter_FSM
if (rst_i)
begin
state <= IDLE;
sclk_r <= 0;
irq_r <= 0;
end
else
begin
if (ack_i)
irq_r <= 0;
case (state)
IDLE:
if (start_i) // init transaction
begin
state <= LEADING_SCLK;
reg_r <= tx_i;
bit_cnt <= 0;
end
LEADING_SCLK:
if (ena_i)
begin
state <= TRAILING_SCLK;
sclk_r <= !sclk_r;
if (!cpha_i) // Leading sample
miso_r <= miso_i;
end
TRAILING_SCLK:
if (ena_i)
begin
sclk_r <= !sclk_r;
if (bit_cnt==DATA_W-1)
begin
state <= STOP;
bit_cnt <= 0;
end
else
begin
state <= LEADING_SCLK;
bit_cnt <= bit_cnt+1;
end
if (cpha_i) // Leading sample
miso_r <= miso_i;
end
default: // STOP
// Maintain the last bit for half the clock to finish
// If we don't do it we could violate the slave hold time
if (ena_i)
begin
irq_r <= 1;
state <= IDLE;
end
endcase
// Shift in cases
if (ena_i)
if ( (state==TRAILING_SCLK && !cpha_i) ||
(((state==LEADING_SCLK && bit_cnt) || state==STOP) && cpha_i))
begin
// Shift
if (dord_i)
// Right
reg_r <= {miso_r,reg_r[DATA_W-1:1]};
else
// Left
reg_r <= {reg_r[DATA_W-2:0],miso_r};
end
end // !rst_i
end // shifter_FSM
assign irq_o=irq_r;
// The FSM generates CPOL=0, if CPOL is 1 we just invert
assign sclk_o=sclk_r^cpol_i;
// MOSI takes the LSB or MSB according to DORD
assign mosi_o=dord_i ? reg_r[0] : reg_r[DATA_W-1];
assign mosi_en_o=state!=IDLE;
assign rx_o=reg_r;
assign busy_o=state!=IDLE;
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKDLYINV3SD2_TB_V
`define SKY130_FD_SC_LS__CLKDLYINV3SD2_TB_V
/**
* clkdlyinv3sd2: Clock Delay Inverter 3-stage 0.25um length inner
* stage gate.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__clkdlyinv3sd2.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_ls__clkdlyinv3sd2 dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKDLYINV3SD2_TB_V
|
// hps_sdram.v
// This file was auto-generated from altera_mem_if_hps_emif_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 16.0 211
`timescale 1 ps / 1 ps
module hps_sdram (
input wire pll_ref_clk, // pll_ref_clk.clk
input wire global_reset_n, // global_reset.reset_n
input wire soft_reset_n, // soft_reset.reset_n
output wire [14:0] mem_a, // memory.mem_a
output wire [2:0] mem_ba, // .mem_ba
output wire [0:0] mem_ck, // .mem_ck
output wire [0:0] mem_ck_n, // .mem_ck_n
output wire [0:0] mem_cke, // .mem_cke
output wire [0:0] mem_cs_n, // .mem_cs_n
output wire [3:0] mem_dm, // .mem_dm
output wire [0:0] mem_ras_n, // .mem_ras_n
output wire [0:0] mem_cas_n, // .mem_cas_n
output wire [0:0] mem_we_n, // .mem_we_n
output wire mem_reset_n, // .mem_reset_n
inout wire [31:0] mem_dq, // .mem_dq
inout wire [3:0] mem_dqs, // .mem_dqs
inout wire [3:0] mem_dqs_n, // .mem_dqs_n
output wire [0:0] mem_odt, // .mem_odt
input wire oct_rzqin // oct.rzqin
);
wire pll_afi_clk_clk; // pll:afi_clk -> [c0:afi_clk, p0:afi_clk]
wire pll_afi_half_clk_clk; // pll:afi_half_clk -> [c0:afi_half_clk, p0:afi_half_clk]
wire [4:0] p0_afi_afi_rlat; // p0:afi_rlat -> c0:afi_rlat
wire p0_afi_afi_cal_success; // p0:afi_cal_success -> c0:afi_cal_success
wire [79:0] p0_afi_afi_rdata; // p0:afi_rdata -> c0:afi_rdata
wire [3:0] p0_afi_afi_wlat; // p0:afi_wlat -> c0:afi_wlat
wire p0_afi_afi_cal_fail; // p0:afi_cal_fail -> c0:afi_cal_fail
wire [0:0] p0_afi_afi_rdata_valid; // p0:afi_rdata_valid -> c0:afi_rdata_valid
wire p0_afi_reset_reset; // p0:afi_reset_n -> c0:afi_reset_n
wire [4:0] c0_afi_afi_rdata_en_full; // c0:afi_rdata_en_full -> p0:afi_rdata_en_full
wire [0:0] c0_afi_afi_rst_n; // c0:afi_rst_n -> p0:afi_rst_n
wire [4:0] c0_afi_afi_dqs_burst; // c0:afi_dqs_burst -> p0:afi_dqs_burst
wire [19:0] c0_afi_afi_addr; // c0:afi_addr -> p0:afi_addr
wire [9:0] c0_afi_afi_dm; // c0:afi_dm -> p0:afi_dm
wire [0:0] c0_afi_afi_mem_clk_disable; // c0:afi_mem_clk_disable -> p0:afi_mem_clk_disable
wire [0:0] c0_afi_afi_we_n; // c0:afi_we_n -> p0:afi_we_n
wire [4:0] c0_afi_afi_rdata_en; // c0:afi_rdata_en -> p0:afi_rdata_en
wire [1:0] c0_afi_afi_odt; // c0:afi_odt -> p0:afi_odt
wire [0:0] c0_afi_afi_ras_n; // c0:afi_ras_n -> p0:afi_ras_n
wire [1:0] c0_afi_afi_cke; // c0:afi_cke -> p0:afi_cke
wire [4:0] c0_afi_afi_wdata_valid; // c0:afi_wdata_valid -> p0:afi_wdata_valid
wire [79:0] c0_afi_afi_wdata; // c0:afi_wdata -> p0:afi_wdata
wire [2:0] c0_afi_afi_ba; // c0:afi_ba -> p0:afi_ba
wire [0:0] c0_afi_afi_cas_n; // c0:afi_cas_n -> p0:afi_cas_n
wire [1:0] c0_afi_afi_cs_n; // c0:afi_cs_n -> p0:afi_cs_n
wire [7:0] c0_hard_phy_cfg_cfg_tmrd; // c0:cfg_tmrd -> p0:cfg_tmrd
wire [23:0] c0_hard_phy_cfg_cfg_dramconfig; // c0:cfg_dramconfig -> p0:cfg_dramconfig
wire [7:0] c0_hard_phy_cfg_cfg_rowaddrwidth; // c0:cfg_rowaddrwidth -> p0:cfg_rowaddrwidth
wire [7:0] c0_hard_phy_cfg_cfg_devicewidth; // c0:cfg_devicewidth -> p0:cfg_devicewidth
wire [15:0] c0_hard_phy_cfg_cfg_trefi; // c0:cfg_trefi -> p0:cfg_trefi
wire [7:0] c0_hard_phy_cfg_cfg_tcl; // c0:cfg_tcl -> p0:cfg_tcl
wire [7:0] c0_hard_phy_cfg_cfg_csaddrwidth; // c0:cfg_csaddrwidth -> p0:cfg_csaddrwidth
wire [7:0] c0_hard_phy_cfg_cfg_coladdrwidth; // c0:cfg_coladdrwidth -> p0:cfg_coladdrwidth
wire [7:0] c0_hard_phy_cfg_cfg_trfc; // c0:cfg_trfc -> p0:cfg_trfc
wire [7:0] c0_hard_phy_cfg_cfg_addlat; // c0:cfg_addlat -> p0:cfg_addlat
wire [7:0] c0_hard_phy_cfg_cfg_bankaddrwidth; // c0:cfg_bankaddrwidth -> p0:cfg_bankaddrwidth
wire [7:0] c0_hard_phy_cfg_cfg_interfacewidth; // c0:cfg_interfacewidth -> p0:cfg_interfacewidth
wire [7:0] c0_hard_phy_cfg_cfg_twr; // c0:cfg_twr -> p0:cfg_twr
wire [7:0] c0_hard_phy_cfg_cfg_caswrlat; // c0:cfg_caswrlat -> p0:cfg_caswrlat
wire p0_ctl_clk_clk; // p0:ctl_clk -> c0:ctl_clk
wire p0_ctl_reset_reset; // p0:ctl_reset_n -> c0:ctl_reset_n
wire p0_io_int_io_intaficalfail; // p0:io_intaficalfail -> c0:io_intaficalfail
wire p0_io_int_io_intaficalsuccess; // p0:io_intaficalsuccess -> c0:io_intaficalsuccess
wire [15:0] oct_oct_sharing_parallelterminationcontrol; // oct:parallelterminationcontrol -> p0:parallelterminationcontrol
wire [15:0] oct_oct_sharing_seriesterminationcontrol; // oct:seriesterminationcontrol -> p0:seriesterminationcontrol
wire pll_pll_sharing_pll_write_clk; // pll:pll_write_clk -> p0:pll_write_clk
wire pll_pll_sharing_pll_avl_clk; // pll:pll_avl_clk -> p0:pll_avl_clk
wire pll_pll_sharing_pll_write_clk_pre_phy_clk; // pll:pll_write_clk_pre_phy_clk -> p0:pll_write_clk_pre_phy_clk
wire pll_pll_sharing_pll_addr_cmd_clk; // pll:pll_addr_cmd_clk -> p0:pll_addr_cmd_clk
wire pll_pll_sharing_pll_config_clk; // pll:pll_config_clk -> p0:pll_config_clk
wire pll_pll_sharing_pll_avl_phy_clk; // pll:pll_avl_phy_clk -> p0:pll_avl_phy_clk
wire pll_pll_sharing_afi_phy_clk; // pll:afi_phy_clk -> p0:afi_phy_clk
wire pll_pll_sharing_pll_mem_clk; // pll:pll_mem_clk -> p0:pll_mem_clk
wire pll_pll_sharing_pll_locked; // pll:pll_locked -> p0:pll_locked
wire pll_pll_sharing_pll_mem_phy_clk; // pll:pll_mem_phy_clk -> p0:pll_mem_phy_clk
wire p0_dll_clk_clk; // p0:dll_clk -> dll:clk
wire p0_dll_sharing_dll_pll_locked; // p0:dll_pll_locked -> dll:dll_pll_locked
wire [6:0] dll_dll_sharing_dll_delayctrl; // dll:dll_delayctrl -> p0:dll_delayctrl
hps_sdram_pll pll (
.global_reset_n (global_reset_n), // global_reset.reset_n
.pll_ref_clk (pll_ref_clk), // pll_ref_clk.clk
.afi_clk (pll_afi_clk_clk), // afi_clk.clk
.afi_half_clk (pll_afi_half_clk_clk), // afi_half_clk.clk
.pll_mem_clk (pll_pll_sharing_pll_mem_clk), // pll_sharing.pll_mem_clk
.pll_write_clk (pll_pll_sharing_pll_write_clk), // .pll_write_clk
.pll_locked (pll_pll_sharing_pll_locked), // .pll_locked
.pll_write_clk_pre_phy_clk (pll_pll_sharing_pll_write_clk_pre_phy_clk), // .pll_write_clk_pre_phy_clk
.pll_addr_cmd_clk (pll_pll_sharing_pll_addr_cmd_clk), // .pll_addr_cmd_clk
.pll_avl_clk (pll_pll_sharing_pll_avl_clk), // .pll_avl_clk
.pll_config_clk (pll_pll_sharing_pll_config_clk), // .pll_config_clk
.pll_mem_phy_clk (pll_pll_sharing_pll_mem_phy_clk), // .pll_mem_phy_clk
.afi_phy_clk (pll_pll_sharing_afi_phy_clk), // .afi_phy_clk
.pll_avl_phy_clk (pll_pll_sharing_pll_avl_phy_clk) // .pll_avl_phy_clk
);
hps_sdram_p0 p0 (
.global_reset_n (global_reset_n), // global_reset.reset_n
.soft_reset_n (soft_reset_n), // soft_reset.reset_n
.afi_reset_n (p0_afi_reset_reset), // afi_reset.reset_n
.afi_reset_export_n (), // afi_reset_export.reset_n
.ctl_reset_n (p0_ctl_reset_reset), // ctl_reset.reset_n
.afi_clk (pll_afi_clk_clk), // afi_clk.clk
.afi_half_clk (pll_afi_half_clk_clk), // afi_half_clk.clk
.ctl_clk (p0_ctl_clk_clk), // ctl_clk.clk
.avl_clk (), // avl_clk.clk
.avl_reset_n (), // avl_reset.reset_n
.scc_clk (), // scc_clk.clk
.scc_reset_n (), // scc_reset.reset_n
.avl_address (), // avl.address
.avl_write (), // .write
.avl_writedata (), // .writedata
.avl_read (), // .read
.avl_readdata (), // .readdata
.avl_waitrequest (), // .waitrequest
.dll_clk (p0_dll_clk_clk), // dll_clk.clk
.afi_addr (c0_afi_afi_addr), // afi.afi_addr
.afi_ba (c0_afi_afi_ba), // .afi_ba
.afi_cke (c0_afi_afi_cke), // .afi_cke
.afi_cs_n (c0_afi_afi_cs_n), // .afi_cs_n
.afi_ras_n (c0_afi_afi_ras_n), // .afi_ras_n
.afi_we_n (c0_afi_afi_we_n), // .afi_we_n
.afi_cas_n (c0_afi_afi_cas_n), // .afi_cas_n
.afi_rst_n (c0_afi_afi_rst_n), // .afi_rst_n
.afi_odt (c0_afi_afi_odt), // .afi_odt
.afi_dqs_burst (c0_afi_afi_dqs_burst), // .afi_dqs_burst
.afi_wdata_valid (c0_afi_afi_wdata_valid), // .afi_wdata_valid
.afi_wdata (c0_afi_afi_wdata), // .afi_wdata
.afi_dm (c0_afi_afi_dm), // .afi_dm
.afi_rdata (p0_afi_afi_rdata), // .afi_rdata
.afi_rdata_en (c0_afi_afi_rdata_en), // .afi_rdata_en
.afi_rdata_en_full (c0_afi_afi_rdata_en_full), // .afi_rdata_en_full
.afi_rdata_valid (p0_afi_afi_rdata_valid), // .afi_rdata_valid
.afi_wlat (p0_afi_afi_wlat), // .afi_wlat
.afi_rlat (p0_afi_afi_rlat), // .afi_rlat
.afi_cal_success (p0_afi_afi_cal_success), // .afi_cal_success
.afi_cal_fail (p0_afi_afi_cal_fail), // .afi_cal_fail
.scc_data (), // scc.scc_data
.scc_dqs_ena (), // .scc_dqs_ena
.scc_dqs_io_ena (), // .scc_dqs_io_ena
.scc_dq_ena (), // .scc_dq_ena
.scc_dm_ena (), // .scc_dm_ena
.capture_strobe_tracking (), // .capture_strobe_tracking
.scc_upd (), // .scc_upd
.cfg_addlat (c0_hard_phy_cfg_cfg_addlat), // hard_phy_cfg.cfg_addlat
.cfg_bankaddrwidth (c0_hard_phy_cfg_cfg_bankaddrwidth), // .cfg_bankaddrwidth
.cfg_caswrlat (c0_hard_phy_cfg_cfg_caswrlat), // .cfg_caswrlat
.cfg_coladdrwidth (c0_hard_phy_cfg_cfg_coladdrwidth), // .cfg_coladdrwidth
.cfg_csaddrwidth (c0_hard_phy_cfg_cfg_csaddrwidth), // .cfg_csaddrwidth
.cfg_devicewidth (c0_hard_phy_cfg_cfg_devicewidth), // .cfg_devicewidth
.cfg_dramconfig (c0_hard_phy_cfg_cfg_dramconfig), // .cfg_dramconfig
.cfg_interfacewidth (c0_hard_phy_cfg_cfg_interfacewidth), // .cfg_interfacewidth
.cfg_rowaddrwidth (c0_hard_phy_cfg_cfg_rowaddrwidth), // .cfg_rowaddrwidth
.cfg_tcl (c0_hard_phy_cfg_cfg_tcl), // .cfg_tcl
.cfg_tmrd (c0_hard_phy_cfg_cfg_tmrd), // .cfg_tmrd
.cfg_trefi (c0_hard_phy_cfg_cfg_trefi), // .cfg_trefi
.cfg_trfc (c0_hard_phy_cfg_cfg_trfc), // .cfg_trfc
.cfg_twr (c0_hard_phy_cfg_cfg_twr), // .cfg_twr
.afi_mem_clk_disable (c0_afi_afi_mem_clk_disable), // afi_mem_clk_disable.afi_mem_clk_disable
.pll_mem_clk (pll_pll_sharing_pll_mem_clk), // pll_sharing.pll_mem_clk
.pll_write_clk (pll_pll_sharing_pll_write_clk), // .pll_write_clk
.pll_locked (pll_pll_sharing_pll_locked), // .pll_locked
.pll_write_clk_pre_phy_clk (pll_pll_sharing_pll_write_clk_pre_phy_clk), // .pll_write_clk_pre_phy_clk
.pll_addr_cmd_clk (pll_pll_sharing_pll_addr_cmd_clk), // .pll_addr_cmd_clk
.pll_avl_clk (pll_pll_sharing_pll_avl_clk), // .pll_avl_clk
.pll_config_clk (pll_pll_sharing_pll_config_clk), // .pll_config_clk
.pll_mem_phy_clk (pll_pll_sharing_pll_mem_phy_clk), // .pll_mem_phy_clk
.afi_phy_clk (pll_pll_sharing_afi_phy_clk), // .afi_phy_clk
.pll_avl_phy_clk (pll_pll_sharing_pll_avl_phy_clk), // .pll_avl_phy_clk
.dll_pll_locked (p0_dll_sharing_dll_pll_locked), // dll_sharing.dll_pll_locked
.dll_delayctrl (dll_dll_sharing_dll_delayctrl), // .dll_delayctrl
.seriesterminationcontrol (oct_oct_sharing_seriesterminationcontrol), // oct_sharing.seriesterminationcontrol
.parallelterminationcontrol (oct_oct_sharing_parallelterminationcontrol), // .parallelterminationcontrol
.mem_a (mem_a), // memory.mem_a
.mem_ba (mem_ba), // .mem_ba
.mem_ck (mem_ck), // .mem_ck
.mem_ck_n (mem_ck_n), // .mem_ck_n
.mem_cke (mem_cke), // .mem_cke
.mem_cs_n (mem_cs_n), // .mem_cs_n
.mem_dm (mem_dm), // .mem_dm
.mem_ras_n (mem_ras_n), // .mem_ras_n
.mem_cas_n (mem_cas_n), // .mem_cas_n
.mem_we_n (mem_we_n), // .mem_we_n
.mem_reset_n (mem_reset_n), // .mem_reset_n
.mem_dq (mem_dq), // .mem_dq
.mem_dqs (mem_dqs), // .mem_dqs
.mem_dqs_n (mem_dqs_n), // .mem_dqs_n
.mem_odt (mem_odt), // .mem_odt
.io_intaficalfail (p0_io_int_io_intaficalfail), // io_int.io_intaficalfail
.io_intaficalsuccess (p0_io_int_io_intaficalsuccess), // .io_intaficalsuccess
.csr_soft_reset_req (1'b0), // (terminated)
.io_intaddrdout (64'b0000000000000000000000000000000000000000000000000000000000000000), // (terminated)
.io_intbadout (12'b000000000000), // (terminated)
.io_intcasndout (4'b0000), // (terminated)
.io_intckdout (4'b0000), // (terminated)
.io_intckedout (8'b00000000), // (terminated)
.io_intckndout (4'b0000), // (terminated)
.io_intcsndout (8'b00000000), // (terminated)
.io_intdmdout (20'b00000000000000000000), // (terminated)
.io_intdqdin (), // (terminated)
.io_intdqdout (180'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), // (terminated)
.io_intdqoe (90'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), // (terminated)
.io_intdqsbdout (20'b00000000000000000000), // (terminated)
.io_intdqsboe (10'b0000000000), // (terminated)
.io_intdqsdout (20'b00000000000000000000), // (terminated)
.io_intdqslogicdqsena (10'b0000000000), // (terminated)
.io_intdqslogicfiforeset (5'b00000), // (terminated)
.io_intdqslogicincrdataen (10'b0000000000), // (terminated)
.io_intdqslogicincwrptr (10'b0000000000), // (terminated)
.io_intdqslogicoct (10'b0000000000), // (terminated)
.io_intdqslogicrdatavalid (), // (terminated)
.io_intdqslogicreadlatency (25'b0000000000000000000000000), // (terminated)
.io_intdqsoe (10'b0000000000), // (terminated)
.io_intodtdout (8'b00000000), // (terminated)
.io_intrasndout (4'b0000), // (terminated)
.io_intresetndout (4'b0000), // (terminated)
.io_intwendout (4'b0000), // (terminated)
.io_intafirlat (), // (terminated)
.io_intafiwlat () // (terminated)
);
altera_mem_if_hhp_qseq_synth_top #(
.MEM_IF_DM_WIDTH (4),
.MEM_IF_DQS_WIDTH (4),
.MEM_IF_CS_WIDTH (1),
.MEM_IF_DQ_WIDTH (32)
) seq (
);
altera_mem_if_hard_memory_controller_top_cyclonev #(
.MEM_IF_DQS_WIDTH (4),
.MEM_IF_CS_WIDTH (1),
.MEM_IF_CHIP_BITS (1),
.MEM_IF_CLK_PAIR_COUNT (1),
.CSR_ADDR_WIDTH (10),
.CSR_DATA_WIDTH (8),
.CSR_BE_WIDTH (1),
.AVL_ADDR_WIDTH (27),
.AVL_DATA_WIDTH (64),
.AVL_SIZE_WIDTH (3),
.AVL_DATA_WIDTH_PORT_0 (1),
.AVL_ADDR_WIDTH_PORT_0 (1),
.AVL_NUM_SYMBOLS_PORT_0 (1),
.LSB_WFIFO_PORT_0 (5),
.MSB_WFIFO_PORT_0 (5),
.LSB_RFIFO_PORT_0 (5),
.MSB_RFIFO_PORT_0 (5),
.AVL_DATA_WIDTH_PORT_1 (1),
.AVL_ADDR_WIDTH_PORT_1 (1),
.AVL_NUM_SYMBOLS_PORT_1 (1),
.LSB_WFIFO_PORT_1 (5),
.MSB_WFIFO_PORT_1 (5),
.LSB_RFIFO_PORT_1 (5),
.MSB_RFIFO_PORT_1 (5),
.AVL_DATA_WIDTH_PORT_2 (1),
.AVL_ADDR_WIDTH_PORT_2 (1),
.AVL_NUM_SYMBOLS_PORT_2 (1),
.LSB_WFIFO_PORT_2 (5),
.MSB_WFIFO_PORT_2 (5),
.LSB_RFIFO_PORT_2 (5),
.MSB_RFIFO_PORT_2 (5),
.AVL_DATA_WIDTH_PORT_3 (1),
.AVL_ADDR_WIDTH_PORT_3 (1),
.AVL_NUM_SYMBOLS_PORT_3 (1),
.LSB_WFIFO_PORT_3 (5),
.MSB_WFIFO_PORT_3 (5),
.LSB_RFIFO_PORT_3 (5),
.MSB_RFIFO_PORT_3 (5),
.AVL_DATA_WIDTH_PORT_4 (1),
.AVL_ADDR_WIDTH_PORT_4 (1),
.AVL_NUM_SYMBOLS_PORT_4 (1),
.LSB_WFIFO_PORT_4 (5),
.MSB_WFIFO_PORT_4 (5),
.LSB_RFIFO_PORT_4 (5),
.MSB_RFIFO_PORT_4 (5),
.AVL_DATA_WIDTH_PORT_5 (1),
.AVL_ADDR_WIDTH_PORT_5 (1),
.AVL_NUM_SYMBOLS_PORT_5 (1),
.LSB_WFIFO_PORT_5 (5),
.MSB_WFIFO_PORT_5 (5),
.LSB_RFIFO_PORT_5 (5),
.MSB_RFIFO_PORT_5 (5),
.ENUM_ATTR_COUNTER_ONE_RESET ("DISABLED"),
.ENUM_ATTR_COUNTER_ZERO_RESET ("DISABLED"),
.ENUM_ATTR_STATIC_CONFIG_VALID ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_0 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_1 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_2 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_3 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_4 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_5 ("DISABLED"),
.ENUM_CAL_REQ ("DISABLED"),
.ENUM_CFG_BURST_LENGTH ("BL_8"),
.ENUM_CFG_INTERFACE_WIDTH ("DWIDTH_32"),
.ENUM_CFG_SELF_RFSH_EXIT_CYCLES ("SELF_RFSH_EXIT_CYCLES_512"),
.ENUM_CFG_STARVE_LIMIT ("STARVE_LIMIT_10"),
.ENUM_CFG_TYPE ("DDR3"),
.ENUM_CLOCK_OFF_0 ("DISABLED"),
.ENUM_CLOCK_OFF_1 ("DISABLED"),
.ENUM_CLOCK_OFF_2 ("DISABLED"),
.ENUM_CLOCK_OFF_3 ("DISABLED"),
.ENUM_CLOCK_OFF_4 ("DISABLED"),
.ENUM_CLOCK_OFF_5 ("DISABLED"),
.ENUM_CLR_INTR ("NO_CLR_INTR"),
.ENUM_CMD_PORT_IN_USE_0 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_1 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_2 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_3 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_4 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_5 ("FALSE"),
.ENUM_CPORT0_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT0_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT0_TYPE ("DISABLE"),
.ENUM_CPORT0_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT1_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT1_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT1_TYPE ("DISABLE"),
.ENUM_CPORT1_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT2_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT2_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT2_TYPE ("DISABLE"),
.ENUM_CPORT2_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT3_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT3_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT3_TYPE ("DISABLE"),
.ENUM_CPORT3_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT4_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT4_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT4_TYPE ("DISABLE"),
.ENUM_CPORT4_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT5_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT5_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT5_TYPE ("DISABLE"),
.ENUM_CPORT5_WFIFO_MAP ("FIFO_0"),
.ENUM_CTL_ADDR_ORDER ("CHIP_ROW_BANK_COL"),
.ENUM_CTL_ECC_ENABLED ("CTL_ECC_DISABLED"),
.ENUM_CTL_ECC_RMW_ENABLED ("CTL_ECC_RMW_DISABLED"),
.ENUM_CTL_REGDIMM_ENABLED ("REGDIMM_DISABLED"),
.ENUM_CTL_USR_REFRESH ("CTL_USR_REFRESH_DISABLED"),
.ENUM_CTRL_WIDTH ("DATA_WIDTH_64_BIT"),
.ENUM_DELAY_BONDING ("BONDING_LATENCY_0"),
.ENUM_DFX_BYPASS_ENABLE ("DFX_BYPASS_DISABLED"),
.ENUM_DISABLE_MERGING ("MERGING_ENABLED"),
.ENUM_ECC_DQ_WIDTH ("ECC_DQ_WIDTH_0"),
.ENUM_ENABLE_ATPG ("DISABLED"),
.ENUM_ENABLE_BONDING_0 ("DISABLED"),
.ENUM_ENABLE_BONDING_1 ("DISABLED"),
.ENUM_ENABLE_BONDING_2 ("DISABLED"),
.ENUM_ENABLE_BONDING_3 ("DISABLED"),
.ENUM_ENABLE_BONDING_4 ("DISABLED"),
.ENUM_ENABLE_BONDING_5 ("DISABLED"),
.ENUM_ENABLE_BONDING_WRAPBACK ("DISABLED"),
.ENUM_ENABLE_DQS_TRACKING ("ENABLED"),
.ENUM_ENABLE_ECC_CODE_OVERWRITES ("DISABLED"),
.ENUM_ENABLE_FAST_EXIT_PPD ("DISABLED"),
.ENUM_ENABLE_INTR ("DISABLED"),
.ENUM_ENABLE_NO_DM ("DISABLED"),
.ENUM_ENABLE_PIPELINEGLOBAL ("DISABLED"),
.ENUM_GANGED_ARF ("DISABLED"),
.ENUM_GEN_DBE ("GEN_DBE_DISABLED"),
.ENUM_GEN_SBE ("GEN_SBE_DISABLED"),
.ENUM_INC_SYNC ("FIFO_SET_2"),
.ENUM_LOCAL_IF_CS_WIDTH ("ADDR_WIDTH_0"),
.ENUM_MASK_CORR_DROPPED_INTR ("DISABLED"),
.ENUM_MASK_DBE_INTR ("DISABLED"),
.ENUM_MASK_SBE_INTR ("DISABLED"),
.ENUM_MEM_IF_AL ("AL_0"),
.ENUM_MEM_IF_BANKADDR_WIDTH ("ADDR_WIDTH_3"),
.ENUM_MEM_IF_BURSTLENGTH ("MEM_IF_BURSTLENGTH_8"),
.ENUM_MEM_IF_COLADDR_WIDTH ("ADDR_WIDTH_10"),
.ENUM_MEM_IF_CS_PER_RANK ("MEM_IF_CS_PER_RANK_1"),
.ENUM_MEM_IF_CS_WIDTH ("MEM_IF_CS_WIDTH_1"),
.ENUM_MEM_IF_DQ_PER_CHIP ("MEM_IF_DQ_PER_CHIP_8"),
.ENUM_MEM_IF_DQS_WIDTH ("DQS_WIDTH_4"),
.ENUM_MEM_IF_DWIDTH ("MEM_IF_DWIDTH_32"),
.ENUM_MEM_IF_MEMTYPE ("DDR3_SDRAM"),
.ENUM_MEM_IF_ROWADDR_WIDTH ("ADDR_WIDTH_15"),
.ENUM_MEM_IF_SPEEDBIN ("DDR3_1600_8_8_8"),
.ENUM_MEM_IF_TCCD ("TCCD_4"),
.ENUM_MEM_IF_TCL ("TCL_7"),
.ENUM_MEM_IF_TCWL ("TCWL_7"),
.ENUM_MEM_IF_TFAW ("TFAW_18"),
.ENUM_MEM_IF_TMRD ("TMRD_4"),
.ENUM_MEM_IF_TRAS ("TRAS_15"),
.ENUM_MEM_IF_TRC ("TRC_20"),
.ENUM_MEM_IF_TRCD ("TRCD_6"),
.ENUM_MEM_IF_TRP ("TRP_6"),
.ENUM_MEM_IF_TRRD ("TRRD_3"),
.ENUM_MEM_IF_TRTP ("TRTP_3"),
.ENUM_MEM_IF_TWR ("TWR_6"),
.ENUM_MEM_IF_TWTR ("TWTR_4"),
.ENUM_MMR_CFG_MEM_BL ("MP_BL_8"),
.ENUM_OUTPUT_REGD ("DISABLED"),
.ENUM_PDN_EXIT_CYCLES ("SLOW_EXIT"),
.ENUM_PORT0_WIDTH ("PORT_32_BIT"),
.ENUM_PORT1_WIDTH ("PORT_32_BIT"),
.ENUM_PORT2_WIDTH ("PORT_32_BIT"),
.ENUM_PORT3_WIDTH ("PORT_32_BIT"),
.ENUM_PORT4_WIDTH ("PORT_32_BIT"),
.ENUM_PORT5_WIDTH ("PORT_32_BIT"),
.ENUM_PRIORITY_0_0 ("WEIGHT_0"),
.ENUM_PRIORITY_0_1 ("WEIGHT_0"),
.ENUM_PRIORITY_0_2 ("WEIGHT_0"),
.ENUM_PRIORITY_0_3 ("WEIGHT_0"),
.ENUM_PRIORITY_0_4 ("WEIGHT_0"),
.ENUM_PRIORITY_0_5 ("WEIGHT_0"),
.ENUM_PRIORITY_1_0 ("WEIGHT_0"),
.ENUM_PRIORITY_1_1 ("WEIGHT_0"),
.ENUM_PRIORITY_1_2 ("WEIGHT_0"),
.ENUM_PRIORITY_1_3 ("WEIGHT_0"),
.ENUM_PRIORITY_1_4 ("WEIGHT_0"),
.ENUM_PRIORITY_1_5 ("WEIGHT_0"),
.ENUM_PRIORITY_2_0 ("WEIGHT_0"),
.ENUM_PRIORITY_2_1 ("WEIGHT_0"),
.ENUM_PRIORITY_2_2 ("WEIGHT_0"),
.ENUM_PRIORITY_2_3 ("WEIGHT_0"),
.ENUM_PRIORITY_2_4 ("WEIGHT_0"),
.ENUM_PRIORITY_2_5 ("WEIGHT_0"),
.ENUM_PRIORITY_3_0 ("WEIGHT_0"),
.ENUM_PRIORITY_3_1 ("WEIGHT_0"),
.ENUM_PRIORITY_3_2 ("WEIGHT_0"),
.ENUM_PRIORITY_3_3 ("WEIGHT_0"),
.ENUM_PRIORITY_3_4 ("WEIGHT_0"),
.ENUM_PRIORITY_3_5 ("WEIGHT_0"),
.ENUM_PRIORITY_4_0 ("WEIGHT_0"),
.ENUM_PRIORITY_4_1 ("WEIGHT_0"),
.ENUM_PRIORITY_4_2 ("WEIGHT_0"),
.ENUM_PRIORITY_4_3 ("WEIGHT_0"),
.ENUM_PRIORITY_4_4 ("WEIGHT_0"),
.ENUM_PRIORITY_4_5 ("WEIGHT_0"),
.ENUM_PRIORITY_5_0 ("WEIGHT_0"),
.ENUM_PRIORITY_5_1 ("WEIGHT_0"),
.ENUM_PRIORITY_5_2 ("WEIGHT_0"),
.ENUM_PRIORITY_5_3 ("WEIGHT_0"),
.ENUM_PRIORITY_5_4 ("WEIGHT_0"),
.ENUM_PRIORITY_5_5 ("WEIGHT_0"),
.ENUM_PRIORITY_6_0 ("WEIGHT_0"),
.ENUM_PRIORITY_6_1 ("WEIGHT_0"),
.ENUM_PRIORITY_6_2 ("WEIGHT_0"),
.ENUM_PRIORITY_6_3 ("WEIGHT_0"),
.ENUM_PRIORITY_6_4 ("WEIGHT_0"),
.ENUM_PRIORITY_6_5 ("WEIGHT_0"),
.ENUM_PRIORITY_7_0 ("WEIGHT_0"),
.ENUM_PRIORITY_7_1 ("WEIGHT_0"),
.ENUM_PRIORITY_7_2 ("WEIGHT_0"),
.ENUM_PRIORITY_7_3 ("WEIGHT_0"),
.ENUM_PRIORITY_7_4 ("WEIGHT_0"),
.ENUM_PRIORITY_7_5 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_0 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_1 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_2 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_3 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_4 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_5 ("WEIGHT_0"),
.ENUM_RCFG_USER_PRIORITY_0 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_1 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_2 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_3 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_4 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_5 ("PRIORITY_1"),
.ENUM_RD_DWIDTH_0 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_1 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_2 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_3 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_4 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_5 ("DWIDTH_0"),
.ENUM_RD_FIFO_IN_USE_0 ("FALSE"),
.ENUM_RD_FIFO_IN_USE_1 ("FALSE"),
.ENUM_RD_FIFO_IN_USE_2 ("FALSE"),
.ENUM_RD_FIFO_IN_USE_3 ("FALSE"),
.ENUM_RD_PORT_INFO_0 ("USE_NO"),
.ENUM_RD_PORT_INFO_1 ("USE_NO"),
.ENUM_RD_PORT_INFO_2 ("USE_NO"),
.ENUM_RD_PORT_INFO_3 ("USE_NO"),
.ENUM_RD_PORT_INFO_4 ("USE_NO"),
.ENUM_RD_PORT_INFO_5 ("USE_NO"),
.ENUM_READ_ODT_CHIP ("ODT_DISABLED"),
.ENUM_REORDER_DATA ("DATA_REORDERING"),
.ENUM_RFIFO0_CPORT_MAP ("CMD_PORT_0"),
.ENUM_RFIFO1_CPORT_MAP ("CMD_PORT_0"),
.ENUM_RFIFO2_CPORT_MAP ("CMD_PORT_0"),
.ENUM_RFIFO3_CPORT_MAP ("CMD_PORT_0"),
.ENUM_SINGLE_READY_0 ("CONCATENATE_RDY"),
.ENUM_SINGLE_READY_1 ("CONCATENATE_RDY"),
.ENUM_SINGLE_READY_2 ("CONCATENATE_RDY"),
.ENUM_SINGLE_READY_3 ("CONCATENATE_RDY"),
.ENUM_STATIC_WEIGHT_0 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_1 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_2 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_3 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_4 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_5 ("WEIGHT_0"),
.ENUM_SYNC_MODE_0 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_1 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_2 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_3 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_4 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_5 ("ASYNCHRONOUS"),
.ENUM_TEST_MODE ("NORMAL_MODE"),
.ENUM_THLD_JAR1_0 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_1 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_2 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_3 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_4 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_5 ("THRESHOLD_32"),
.ENUM_THLD_JAR2_0 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_1 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_2 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_3 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_4 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_5 ("THRESHOLD_16"),
.ENUM_USE_ALMOST_EMPTY_0 ("EMPTY"),
.ENUM_USE_ALMOST_EMPTY_1 ("EMPTY"),
.ENUM_USE_ALMOST_EMPTY_2 ("EMPTY"),
.ENUM_USE_ALMOST_EMPTY_3 ("EMPTY"),
.ENUM_USER_ECC_EN ("DISABLE"),
.ENUM_USER_PRIORITY_0 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_1 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_2 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_3 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_4 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_5 ("PRIORITY_1"),
.ENUM_WFIFO0_CPORT_MAP ("CMD_PORT_0"),
.ENUM_WFIFO0_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_WFIFO1_CPORT_MAP ("CMD_PORT_0"),
.ENUM_WFIFO1_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_WFIFO2_CPORT_MAP ("CMD_PORT_0"),
.ENUM_WFIFO2_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_WFIFO3_CPORT_MAP ("CMD_PORT_0"),
.ENUM_WFIFO3_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_WR_DWIDTH_0 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_1 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_2 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_3 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_4 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_5 ("DWIDTH_0"),
.ENUM_WR_FIFO_IN_USE_0 ("FALSE"),
.ENUM_WR_FIFO_IN_USE_1 ("FALSE"),
.ENUM_WR_FIFO_IN_USE_2 ("FALSE"),
.ENUM_WR_FIFO_IN_USE_3 ("FALSE"),
.ENUM_WR_PORT_INFO_0 ("USE_NO"),
.ENUM_WR_PORT_INFO_1 ("USE_NO"),
.ENUM_WR_PORT_INFO_2 ("USE_NO"),
.ENUM_WR_PORT_INFO_3 ("USE_NO"),
.ENUM_WR_PORT_INFO_4 ("USE_NO"),
.ENUM_WR_PORT_INFO_5 ("USE_NO"),
.ENUM_WRITE_ODT_CHIP ("WRITE_CHIP0_ODT0_CHIP1"),
.INTG_MEM_AUTO_PD_CYCLES (0),
.INTG_CYC_TO_RLD_JARS_0 (1),
.INTG_CYC_TO_RLD_JARS_1 (1),
.INTG_CYC_TO_RLD_JARS_2 (1),
.INTG_CYC_TO_RLD_JARS_3 (1),
.INTG_CYC_TO_RLD_JARS_4 (1),
.INTG_CYC_TO_RLD_JARS_5 (1),
.INTG_EXTRA_CTL_CLK_ACT_TO_ACT (0),
.INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK (0),
.INTG_EXTRA_CTL_CLK_ACT_TO_PCH (0),
.INTG_EXTRA_CTL_CLK_ACT_TO_RDWR (0),
.INTG_EXTRA_CTL_CLK_ARF_PERIOD (0),
.INTG_EXTRA_CTL_CLK_ARF_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT (0),
.INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_PCH_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_PDN_PERIOD (0),
.INTG_EXTRA_CTL_CLK_PDN_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_RD_TO_PCH (0),
.INTG_EXTRA_CTL_CLK_RD_TO_RD (0),
.INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP (0),
.INTG_EXTRA_CTL_CLK_RD_TO_WR (2),
.INTG_EXTRA_CTL_CLK_RD_TO_WR_BC (2),
.INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP (2),
.INTG_EXTRA_CTL_CLK_SRF_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL (0),
.INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_WR_TO_PCH (0),
.INTG_EXTRA_CTL_CLK_WR_TO_RD (3),
.INTG_EXTRA_CTL_CLK_WR_TO_RD_BC (3),
.INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP (3),
.INTG_EXTRA_CTL_CLK_WR_TO_WR (0),
.INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP (0),
.INTG_MEM_IF_TREFI (3120),
.INTG_MEM_IF_TRFC (120),
.INTG_RCFG_SUM_WT_PRIORITY_0 (0),
.INTG_RCFG_SUM_WT_PRIORITY_1 (0),
.INTG_RCFG_SUM_WT_PRIORITY_2 (0),
.INTG_RCFG_SUM_WT_PRIORITY_3 (0),
.INTG_RCFG_SUM_WT_PRIORITY_4 (0),
.INTG_RCFG_SUM_WT_PRIORITY_5 (0),
.INTG_RCFG_SUM_WT_PRIORITY_6 (0),
.INTG_RCFG_SUM_WT_PRIORITY_7 (0),
.INTG_SUM_WT_PRIORITY_0 (0),
.INTG_SUM_WT_PRIORITY_1 (0),
.INTG_SUM_WT_PRIORITY_2 (0),
.INTG_SUM_WT_PRIORITY_3 (0),
.INTG_SUM_WT_PRIORITY_4 (0),
.INTG_SUM_WT_PRIORITY_5 (0),
.INTG_SUM_WT_PRIORITY_6 (0),
.INTG_SUM_WT_PRIORITY_7 (0),
.INTG_POWER_SAVING_EXIT_CYCLES (5),
.INTG_MEM_CLK_ENTRY_CYCLES (10),
.ENUM_ENABLE_BURST_INTERRUPT ("DISABLED"),
.ENUM_ENABLE_BURST_TERMINATE ("DISABLED"),
.AFI_RATE_RATIO (1),
.AFI_ADDR_WIDTH (15),
.AFI_BANKADDR_WIDTH (3),
.AFI_CONTROL_WIDTH (1),
.AFI_CS_WIDTH (1),
.AFI_DM_WIDTH (8),
.AFI_DQ_WIDTH (64),
.AFI_ODT_WIDTH (1),
.AFI_WRITE_DQS_WIDTH (4),
.AFI_RLAT_WIDTH (6),
.AFI_WLAT_WIDTH (6),
.HARD_PHY (1)
) c0 (
.afi_clk (pll_afi_clk_clk), // afi_clk.clk
.afi_reset_n (p0_afi_reset_reset), // afi_reset.reset_n
.ctl_reset_n (p0_ctl_reset_reset), // ctl_reset.reset_n
.afi_half_clk (pll_afi_half_clk_clk), // afi_half_clk.clk
.ctl_clk (p0_ctl_clk_clk), // ctl_clk.clk
.local_init_done (), // status.local_init_done
.local_cal_success (), // .local_cal_success
.local_cal_fail (), // .local_cal_fail
.afi_addr (c0_afi_afi_addr), // afi.afi_addr
.afi_ba (c0_afi_afi_ba), // .afi_ba
.afi_cke (c0_afi_afi_cke), // .afi_cke
.afi_cs_n (c0_afi_afi_cs_n), // .afi_cs_n
.afi_ras_n (c0_afi_afi_ras_n), // .afi_ras_n
.afi_we_n (c0_afi_afi_we_n), // .afi_we_n
.afi_cas_n (c0_afi_afi_cas_n), // .afi_cas_n
.afi_rst_n (c0_afi_afi_rst_n), // .afi_rst_n
.afi_odt (c0_afi_afi_odt), // .afi_odt
.afi_mem_clk_disable (c0_afi_afi_mem_clk_disable), // .afi_mem_clk_disable
.afi_init_req (), // .afi_init_req
.afi_cal_req (), // .afi_cal_req
.afi_seq_busy (), // .afi_seq_busy
.afi_ctl_refresh_done (), // .afi_ctl_refresh_done
.afi_ctl_long_idle (), // .afi_ctl_long_idle
.afi_dqs_burst (c0_afi_afi_dqs_burst), // .afi_dqs_burst
.afi_wdata_valid (c0_afi_afi_wdata_valid), // .afi_wdata_valid
.afi_wdata (c0_afi_afi_wdata), // .afi_wdata
.afi_dm (c0_afi_afi_dm), // .afi_dm
.afi_rdata (p0_afi_afi_rdata), // .afi_rdata
.afi_rdata_en (c0_afi_afi_rdata_en), // .afi_rdata_en
.afi_rdata_en_full (c0_afi_afi_rdata_en_full), // .afi_rdata_en_full
.afi_rdata_valid (p0_afi_afi_rdata_valid), // .afi_rdata_valid
.afi_wlat (p0_afi_afi_wlat), // .afi_wlat
.afi_rlat (p0_afi_afi_rlat), // .afi_rlat
.afi_cal_success (p0_afi_afi_cal_success), // .afi_cal_success
.afi_cal_fail (p0_afi_afi_cal_fail), // .afi_cal_fail
.cfg_addlat (c0_hard_phy_cfg_cfg_addlat), // hard_phy_cfg.cfg_addlat
.cfg_bankaddrwidth (c0_hard_phy_cfg_cfg_bankaddrwidth), // .cfg_bankaddrwidth
.cfg_caswrlat (c0_hard_phy_cfg_cfg_caswrlat), // .cfg_caswrlat
.cfg_coladdrwidth (c0_hard_phy_cfg_cfg_coladdrwidth), // .cfg_coladdrwidth
.cfg_csaddrwidth (c0_hard_phy_cfg_cfg_csaddrwidth), // .cfg_csaddrwidth
.cfg_devicewidth (c0_hard_phy_cfg_cfg_devicewidth), // .cfg_devicewidth
.cfg_dramconfig (c0_hard_phy_cfg_cfg_dramconfig), // .cfg_dramconfig
.cfg_interfacewidth (c0_hard_phy_cfg_cfg_interfacewidth), // .cfg_interfacewidth
.cfg_rowaddrwidth (c0_hard_phy_cfg_cfg_rowaddrwidth), // .cfg_rowaddrwidth
.cfg_tcl (c0_hard_phy_cfg_cfg_tcl), // .cfg_tcl
.cfg_tmrd (c0_hard_phy_cfg_cfg_tmrd), // .cfg_tmrd
.cfg_trefi (c0_hard_phy_cfg_cfg_trefi), // .cfg_trefi
.cfg_trfc (c0_hard_phy_cfg_cfg_trfc), // .cfg_trfc
.cfg_twr (c0_hard_phy_cfg_cfg_twr), // .cfg_twr
.io_intaficalfail (p0_io_int_io_intaficalfail), // io_int.io_intaficalfail
.io_intaficalsuccess (p0_io_int_io_intaficalsuccess), // .io_intaficalsuccess
.mp_cmd_clk_0 (1'b0), // (terminated)
.mp_cmd_reset_n_0 (1'b1), // (terminated)
.mp_cmd_clk_1 (1'b0), // (terminated)
.mp_cmd_reset_n_1 (1'b1), // (terminated)
.mp_cmd_clk_2 (1'b0), // (terminated)
.mp_cmd_reset_n_2 (1'b1), // (terminated)
.mp_cmd_clk_3 (1'b0), // (terminated)
.mp_cmd_reset_n_3 (1'b1), // (terminated)
.mp_cmd_clk_4 (1'b0), // (terminated)
.mp_cmd_reset_n_4 (1'b1), // (terminated)
.mp_cmd_clk_5 (1'b0), // (terminated)
.mp_cmd_reset_n_5 (1'b1), // (terminated)
.mp_rfifo_clk_0 (1'b0), // (terminated)
.mp_rfifo_reset_n_0 (1'b1), // (terminated)
.mp_wfifo_clk_0 (1'b0), // (terminated)
.mp_wfifo_reset_n_0 (1'b1), // (terminated)
.mp_rfifo_clk_1 (1'b0), // (terminated)
.mp_rfifo_reset_n_1 (1'b1), // (terminated)
.mp_wfifo_clk_1 (1'b0), // (terminated)
.mp_wfifo_reset_n_1 (1'b1), // (terminated)
.mp_rfifo_clk_2 (1'b0), // (terminated)
.mp_rfifo_reset_n_2 (1'b1), // (terminated)
.mp_wfifo_clk_2 (1'b0), // (terminated)
.mp_wfifo_reset_n_2 (1'b1), // (terminated)
.mp_rfifo_clk_3 (1'b0), // (terminated)
.mp_rfifo_reset_n_3 (1'b1), // (terminated)
.mp_wfifo_clk_3 (1'b0), // (terminated)
.mp_wfifo_reset_n_3 (1'b1), // (terminated)
.csr_clk (1'b0), // (terminated)
.csr_reset_n (1'b1), // (terminated)
.avl_ready_0 (), // (terminated)
.avl_burstbegin_0 (1'b0), // (terminated)
.avl_addr_0 (1'b0), // (terminated)
.avl_rdata_valid_0 (), // (terminated)
.avl_rdata_0 (), // (terminated)
.avl_wdata_0 (1'b0), // (terminated)
.avl_be_0 (1'b0), // (terminated)
.avl_read_req_0 (1'b0), // (terminated)
.avl_write_req_0 (1'b0), // (terminated)
.avl_size_0 (3'b000), // (terminated)
.avl_ready_1 (), // (terminated)
.avl_burstbegin_1 (1'b0), // (terminated)
.avl_addr_1 (1'b0), // (terminated)
.avl_rdata_valid_1 (), // (terminated)
.avl_rdata_1 (), // (terminated)
.avl_wdata_1 (1'b0), // (terminated)
.avl_be_1 (1'b0), // (terminated)
.avl_read_req_1 (1'b0), // (terminated)
.avl_write_req_1 (1'b0), // (terminated)
.avl_size_1 (3'b000), // (terminated)
.avl_ready_2 (), // (terminated)
.avl_burstbegin_2 (1'b0), // (terminated)
.avl_addr_2 (1'b0), // (terminated)
.avl_rdata_valid_2 (), // (terminated)
.avl_rdata_2 (), // (terminated)
.avl_wdata_2 (1'b0), // (terminated)
.avl_be_2 (1'b0), // (terminated)
.avl_read_req_2 (1'b0), // (terminated)
.avl_write_req_2 (1'b0), // (terminated)
.avl_size_2 (3'b000), // (terminated)
.avl_ready_3 (), // (terminated)
.avl_burstbegin_3 (1'b0), // (terminated)
.avl_addr_3 (1'b0), // (terminated)
.avl_rdata_valid_3 (), // (terminated)
.avl_rdata_3 (), // (terminated)
.avl_wdata_3 (1'b0), // (terminated)
.avl_be_3 (1'b0), // (terminated)
.avl_read_req_3 (1'b0), // (terminated)
.avl_write_req_3 (1'b0), // (terminated)
.avl_size_3 (3'b000), // (terminated)
.avl_ready_4 (), // (terminated)
.avl_burstbegin_4 (1'b0), // (terminated)
.avl_addr_4 (1'b0), // (terminated)
.avl_rdata_valid_4 (), // (terminated)
.avl_rdata_4 (), // (terminated)
.avl_wdata_4 (1'b0), // (terminated)
.avl_be_4 (1'b0), // (terminated)
.avl_read_req_4 (1'b0), // (terminated)
.avl_write_req_4 (1'b0), // (terminated)
.avl_size_4 (3'b000), // (terminated)
.avl_ready_5 (), // (terminated)
.avl_burstbegin_5 (1'b0), // (terminated)
.avl_addr_5 (1'b0), // (terminated)
.avl_rdata_valid_5 (), // (terminated)
.avl_rdata_5 (), // (terminated)
.avl_wdata_5 (1'b0), // (terminated)
.avl_be_5 (1'b0), // (terminated)
.avl_read_req_5 (1'b0), // (terminated)
.avl_write_req_5 (1'b0), // (terminated)
.avl_size_5 (3'b000), // (terminated)
.csr_write_req (1'b0), // (terminated)
.csr_read_req (1'b0), // (terminated)
.csr_waitrequest (), // (terminated)
.csr_addr (10'b0000000000), // (terminated)
.csr_be (1'b0), // (terminated)
.csr_wdata (8'b00000000), // (terminated)
.csr_rdata (), // (terminated)
.csr_rdata_valid (), // (terminated)
.local_multicast (1'b0), // (terminated)
.local_refresh_req (1'b0), // (terminated)
.local_refresh_chip (1'b0), // (terminated)
.local_refresh_ack (), // (terminated)
.local_self_rfsh_req (1'b0), // (terminated)
.local_self_rfsh_chip (1'b0), // (terminated)
.local_self_rfsh_ack (), // (terminated)
.local_deep_powerdn_req (1'b0), // (terminated)
.local_deep_powerdn_chip (1'b0), // (terminated)
.local_deep_powerdn_ack (), // (terminated)
.local_powerdn_ack (), // (terminated)
.local_priority (1'b0), // (terminated)
.bonding_in_1 (4'b0000), // (terminated)
.bonding_in_2 (6'b000000), // (terminated)
.bonding_in_3 (6'b000000), // (terminated)
.bonding_out_1 (), // (terminated)
.bonding_out_2 (), // (terminated)
.bonding_out_3 () // (terminated)
);
altera_mem_if_oct_cyclonev #(
.OCT_TERM_CONTROL_WIDTH (16)
) oct (
.oct_rzqin (oct_rzqin), // oct.rzqin
.seriesterminationcontrol (oct_oct_sharing_seriesterminationcontrol), // oct_sharing.seriesterminationcontrol
.parallelterminationcontrol (oct_oct_sharing_parallelterminationcontrol) // .parallelterminationcontrol
);
altera_mem_if_dll_cyclonev #(
.DLL_DELAY_CTRL_WIDTH (7),
.DLL_OFFSET_CTRL_WIDTH (6),
.DELAY_BUFFER_MODE ("HIGH"),
.DELAY_CHAIN_LENGTH (8),
.DLL_INPUT_FREQUENCY_PS_STR ("2500 ps")
) dll (
.clk (p0_dll_clk_clk), // clk.clk
.dll_pll_locked (p0_dll_sharing_dll_pll_locked), // dll_sharing.dll_pll_locked
.dll_delayctrl (dll_dll_sharing_dll_delayctrl) // .dll_delayctrl
);
endmodule
|
module dis_controller (/*AUTOARG*/
// Outputs
dis_controller_start_alloc, dis_controller_alloc_ack,
dis_controller_wg_alloc_valid, dis_controller_wg_dealloc_valid,
dis_controller_wg_rejected_valid, dis_controller_cu_busy,
// Inputs
clk, rst, inflight_wg_buffer_alloc_valid,
inflight_wg_buffer_alloc_available, allocator_cu_valid,
allocator_cu_rejected, allocator_cu_id_out, grt_wg_alloc_done,
grt_wg_dealloc_done, grt_wg_alloc_wgid, grt_wg_dealloc_wgid,
grt_wg_alloc_cu_id, grt_wg_dealloc_cu_id,
gpu_interface_alloc_available, gpu_interface_dealloc_available,
gpu_interface_cu_id
) ;
parameter NUMBER_CU = 64;
parameter CU_ID_WIDTH = 6;
parameter RES_TABLE_ADDR_WIDTH = 1;
localparam NUMBER_RES_TABLE = 2**RES_TABLE_ADDR_WIDTH;
localparam CU_PER_RES_TABLE = NUMBER_CU/NUMBER_RES_TABLE;
input clk,rst;
input inflight_wg_buffer_alloc_valid, inflight_wg_buffer_alloc_available;
input allocator_cu_valid, allocator_cu_rejected;
input [CU_ID_WIDTH-1 :0] allocator_cu_id_out;
input grt_wg_alloc_done, grt_wg_dealloc_done;
input [CU_ID_WIDTH-1:0] grt_wg_alloc_wgid, grt_wg_dealloc_wgid;
input [CU_ID_WIDTH-1 :0] grt_wg_alloc_cu_id, grt_wg_dealloc_cu_id;
input gpu_interface_alloc_available,
gpu_interface_dealloc_available;
input [CU_ID_WIDTH-1:0] gpu_interface_cu_id;
// Outputs to handle incomming wg
output dis_controller_start_alloc;
// Outputs to handle wg going from allocator to resource table
output dis_controller_alloc_ack;
output dis_controller_wg_alloc_valid;
output dis_controller_wg_dealloc_valid;
output dis_controller_wg_rejected_valid;
// Output to allocator
output [NUMBER_CU-1:0] dis_controller_cu_busy;
reg [NUMBER_CU-1:0] cus_allocating;
reg [NUMBER_RES_TABLE-1:0] cu_groups_allocating;
reg [CU_ID_WIDTH-1 :0] alloc_waiting_cu_id;
reg alloc_waiting;
reg dis_controller_start_alloc_i;
reg dis_controller_alloc_ack_i;
reg dis_controller_wg_alloc_valid_i;
reg dis_controller_wg_dealloc_valid_i;
reg dis_controller_wg_rejected_valid_i;
localparam ALLOC_NUM_STATES = 4;
localparam ST_AL_IDLE = 0;
localparam ST_AL_ALLOC = 2;
localparam ST_AL_HANDLE_RESULT = 4;
localparam ST_AL_ACK_PROPAGATION = 8;
reg [ALLOC_NUM_STATES-1:0] alloc_st;
function [RES_TABLE_ADDR_WIDTH-1:0] get_res_tbl_addr;
input[CU_ID_WIDTH-1 :0] cu_id;
begin
get_res_tbl_addr = cu_id[CU_ID_WIDTH-1 -: RES_TABLE_ADDR_WIDTH];
end
endfunction // if
always @ ( posedge clk or posedge rst ) begin
if(rst) begin
alloc_st <= ST_AL_IDLE;
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
alloc_waiting <= 1'h0;
alloc_waiting_cu_id <= {CU_ID_WIDTH{1'b0}};
cu_groups_allocating <= {NUMBER_RES_TABLE{1'b0}};
dis_controller_alloc_ack_i <= 1'h0;
dis_controller_start_alloc_i <= 1'h0;
dis_controller_wg_alloc_valid_i <= 1'h0;
dis_controller_wg_dealloc_valid_i <= 1'h0;
dis_controller_wg_rejected_valid_i <= 1'h0;
// End of automatics
end
else begin
dis_controller_start_alloc_i <= 1'b0;
dis_controller_alloc_ack_i <= 1'b0;
// State machine that babysits the allocator.
// Waits until allocator input can be handled by the grt to acknowledge a allocated wg
case(alloc_st)
ST_AL_IDLE: begin
if(inflight_wg_buffer_alloc_valid && !(&cu_groups_allocating) ) begin
dis_controller_start_alloc_i <= 1'b1;
alloc_st <= ST_AL_ALLOC;
end
end
ST_AL_ALLOC: begin
if(allocator_cu_valid) begin
alloc_waiting <= 1'b1;
alloc_waiting_cu_id <= allocator_cu_id_out;
alloc_st <= ST_AL_HANDLE_RESULT;
end // if (allocator_cu_valid)
end
ST_AL_HANDLE_RESULT: begin
// If we served the waiting wg,
// then move on
if(!alloc_waiting) begin
dis_controller_alloc_ack_i <= 1'b1;
alloc_st <= ST_AL_ACK_PROPAGATION;
end
end // case: ST_AL_HANDLE_RESULT
ST_AL_ACK_PROPAGATION: begin
alloc_st <= ST_AL_IDLE;
end
endcase // case (alloc_st)
// Handles the grt
// Deallocations are always handled first
dis_controller_wg_dealloc_valid_i <= 1'b0;
dis_controller_wg_alloc_valid_i <= 1'b0;
dis_controller_wg_rejected_valid_i <= 1'b0;
if(gpu_interface_dealloc_available &&
!cu_groups_allocating[get_res_tbl_addr(gpu_interface_cu_id)]) begin
dis_controller_wg_dealloc_valid_i <= 1'b1;
cu_groups_allocating[get_res_tbl_addr(gpu_interface_cu_id)] <= 1'b1;
end
else if(alloc_waiting &&
!cu_groups_allocating[get_res_tbl_addr(alloc_waiting_cu_id)]) begin
if(allocator_cu_rejected) begin
alloc_waiting <= 1'b0;
dis_controller_wg_rejected_valid_i <= 1'b1;
end
else if(gpu_interface_alloc_available &&
inflight_wg_buffer_alloc_available) begin
alloc_waiting <= 1'b0;
dis_controller_wg_alloc_valid_i <= 1'b1;
cu_groups_allocating[get_res_tbl_addr(alloc_waiting_cu_id)] <= 1'b1;
end
end // if (alloc_waiting &&...
// End of allocation/deallocation
if(grt_wg_alloc_done) begin
cu_groups_allocating[get_res_tbl_addr(grt_wg_alloc_cu_id)] <= 1'b0;
end
else if(grt_wg_dealloc_done) begin
cu_groups_allocating[get_res_tbl_addr(grt_wg_dealloc_cu_id)] <= 1'b0;
end
end // else: !if(rst)
end // always @ ( posedge clk or posedge rst )
always @ ( /*AUTOSENSE*/cu_groups_allocating) begin : EXPAND_CU_GROUPS
reg[CU_ID_WIDTH :0] i;
for (i=0; i < NUMBER_CU; i=i+1) begin
cus_allocating[i] = cu_groups_allocating[get_res_tbl_addr(i[CU_ID_WIDTH-1:0])];
end
end
assign dis_controller_start_alloc = dis_controller_start_alloc_i;
assign dis_controller_alloc_ack = dis_controller_alloc_ack_i;
assign dis_controller_wg_alloc_valid = dis_controller_wg_alloc_valid_i;
assign dis_controller_wg_dealloc_valid = dis_controller_wg_dealloc_valid_i;
assign dis_controller_wg_rejected_valid = dis_controller_wg_rejected_valid_i;
assign dis_controller_cu_busy = cus_allocating;
endmodule // dis_controller
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module wasca_jtag_uart_0_sim_scfifo_w (
// inputs:
clk,
fifo_wdata,
fifo_wr,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
)
;
output fifo_FF;
output [ 7: 0] r_dat;
output wfifo_empty;
output [ 5: 0] wfifo_used;
input clk;
input [ 7: 0] fifo_wdata;
input fifo_wr;
wire fifo_FF;
wire [ 7: 0] r_dat;
wire wfifo_empty;
wire [ 5: 0] wfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
always @(posedge clk)
begin
if (fifo_wr)
$write("%c", fifo_wdata);
end
assign wfifo_used = {6{1'b0}};
assign r_dat = {8{1'b0}};
assign fifo_FF = 1'b0;
assign wfifo_empty = 1'b1;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module wasca_jtag_uart_0_scfifo_w (
// inputs:
clk,
fifo_clear,
fifo_wdata,
fifo_wr,
rd_wfifo,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
)
;
output fifo_FF;
output [ 7: 0] r_dat;
output wfifo_empty;
output [ 5: 0] wfifo_used;
input clk;
input fifo_clear;
input [ 7: 0] fifo_wdata;
input fifo_wr;
input rd_wfifo;
wire fifo_FF;
wire [ 7: 0] r_dat;
wire wfifo_empty;
wire [ 5: 0] wfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
wasca_jtag_uart_0_sim_scfifo_w the_wasca_jtag_uart_0_sim_scfifo_w
(
.clk (clk),
.fifo_FF (fifo_FF),
.fifo_wdata (fifo_wdata),
.fifo_wr (fifo_wr),
.r_dat (r_dat),
.wfifo_empty (wfifo_empty),
.wfifo_used (wfifo_used)
);
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// scfifo wfifo
// (
// .aclr (fifo_clear),
// .clock (clk),
// .data (fifo_wdata),
// .empty (wfifo_empty),
// .full (fifo_FF),
// .q (r_dat),
// .rdreq (rd_wfifo),
// .usedw (wfifo_used),
// .wrreq (fifo_wr)
// );
//
// defparam wfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
// wfifo.lpm_numwords = 64,
// wfifo.lpm_showahead = "OFF",
// wfifo.lpm_type = "scfifo",
// wfifo.lpm_width = 8,
// wfifo.lpm_widthu = 6,
// wfifo.overflow_checking = "OFF",
// wfifo.underflow_checking = "OFF",
// wfifo.use_eab = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module wasca_jtag_uart_0_sim_scfifo_r (
// inputs:
clk,
fifo_rd,
rst_n,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
)
;
output fifo_EF;
output [ 7: 0] fifo_rdata;
output rfifo_full;
output [ 5: 0] rfifo_used;
input clk;
input fifo_rd;
input rst_n;
reg [ 31: 0] bytes_left;
wire fifo_EF;
reg fifo_rd_d;
wire [ 7: 0] fifo_rdata;
wire new_rom;
wire [ 31: 0] num_bytes;
wire [ 6: 0] rfifo_entries;
wire rfifo_full;
wire [ 5: 0] rfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
// Generate rfifo_entries for simulation
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
begin
bytes_left <= 32'h0;
fifo_rd_d <= 1'b0;
end
else
begin
fifo_rd_d <= fifo_rd;
// decrement on read
if (fifo_rd_d)
bytes_left <= bytes_left - 1'b1;
// catch new contents
if (new_rom)
bytes_left <= num_bytes;
end
end
assign fifo_EF = bytes_left == 32'b0;
assign rfifo_full = bytes_left > 7'h40;
assign rfifo_entries = (rfifo_full) ? 7'h40 : bytes_left;
assign rfifo_used = rfifo_entries[5 : 0];
assign new_rom = 1'b0;
assign num_bytes = 32'b0;
assign fifo_rdata = 8'b0;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module wasca_jtag_uart_0_scfifo_r (
// inputs:
clk,
fifo_clear,
fifo_rd,
rst_n,
t_dat,
wr_rfifo,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
)
;
output fifo_EF;
output [ 7: 0] fifo_rdata;
output rfifo_full;
output [ 5: 0] rfifo_used;
input clk;
input fifo_clear;
input fifo_rd;
input rst_n;
input [ 7: 0] t_dat;
input wr_rfifo;
wire fifo_EF;
wire [ 7: 0] fifo_rdata;
wire rfifo_full;
wire [ 5: 0] rfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
wasca_jtag_uart_0_sim_scfifo_r the_wasca_jtag_uart_0_sim_scfifo_r
(
.clk (clk),
.fifo_EF (fifo_EF),
.fifo_rd (fifo_rd),
.fifo_rdata (fifo_rdata),
.rfifo_full (rfifo_full),
.rfifo_used (rfifo_used),
.rst_n (rst_n)
);
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// scfifo rfifo
// (
// .aclr (fifo_clear),
// .clock (clk),
// .data (t_dat),
// .empty (fifo_EF),
// .full (rfifo_full),
// .q (fifo_rdata),
// .rdreq (fifo_rd),
// .usedw (rfifo_used),
// .wrreq (wr_rfifo)
// );
//
// defparam rfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
// rfifo.lpm_numwords = 64,
// rfifo.lpm_showahead = "OFF",
// rfifo.lpm_type = "scfifo",
// rfifo.lpm_width = 8,
// rfifo.lpm_widthu = 6,
// rfifo.overflow_checking = "OFF",
// rfifo.underflow_checking = "OFF",
// rfifo.use_eab = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module wasca_jtag_uart_0 (
// inputs:
av_address,
av_chipselect,
av_read_n,
av_write_n,
av_writedata,
clk,
rst_n,
// outputs:
av_irq,
av_readdata,
av_waitrequest,
dataavailable,
readyfordata
)
/* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R101,C106,D101,D103\"" */ ;
output av_irq;
output [ 31: 0] av_readdata;
output av_waitrequest;
output dataavailable;
output readyfordata;
input av_address;
input av_chipselect;
input av_read_n;
input av_write_n;
input [ 31: 0] av_writedata;
input clk;
input rst_n;
reg ac;
wire activity;
wire av_irq;
wire [ 31: 0] av_readdata;
reg av_waitrequest;
reg dataavailable;
reg fifo_AE;
reg fifo_AF;
wire fifo_EF;
wire fifo_FF;
wire fifo_clear;
wire fifo_rd;
wire [ 7: 0] fifo_rdata;
wire [ 7: 0] fifo_wdata;
reg fifo_wr;
reg ien_AE;
reg ien_AF;
wire ipen_AE;
wire ipen_AF;
reg pause_irq;
wire [ 7: 0] r_dat;
wire r_ena;
reg r_val;
wire rd_wfifo;
reg read_0;
reg readyfordata;
wire rfifo_full;
wire [ 5: 0] rfifo_used;
reg rvalid;
reg sim_r_ena;
reg sim_t_dat;
reg sim_t_ena;
reg sim_t_pause;
wire [ 7: 0] t_dat;
reg t_dav;
wire t_ena;
wire t_pause;
wire wfifo_empty;
wire [ 5: 0] wfifo_used;
reg woverflow;
wire wr_rfifo;
//avalon_jtag_slave, which is an e_avalon_slave
assign rd_wfifo = r_ena & ~wfifo_empty;
assign wr_rfifo = t_ena & ~rfifo_full;
assign fifo_clear = ~rst_n;
wasca_jtag_uart_0_scfifo_w the_wasca_jtag_uart_0_scfifo_w
(
.clk (clk),
.fifo_FF (fifo_FF),
.fifo_clear (fifo_clear),
.fifo_wdata (fifo_wdata),
.fifo_wr (fifo_wr),
.r_dat (r_dat),
.rd_wfifo (rd_wfifo),
.wfifo_empty (wfifo_empty),
.wfifo_used (wfifo_used)
);
wasca_jtag_uart_0_scfifo_r the_wasca_jtag_uart_0_scfifo_r
(
.clk (clk),
.fifo_EF (fifo_EF),
.fifo_clear (fifo_clear),
.fifo_rd (fifo_rd),
.fifo_rdata (fifo_rdata),
.rfifo_full (rfifo_full),
.rfifo_used (rfifo_used),
.rst_n (rst_n),
.t_dat (t_dat),
.wr_rfifo (wr_rfifo)
);
assign ipen_AE = ien_AE & fifo_AE;
assign ipen_AF = ien_AF & (pause_irq | fifo_AF);
assign av_irq = ipen_AE | ipen_AF;
assign activity = t_pause | t_ena;
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
pause_irq <= 1'b0;
else // only if fifo is not empty...
if (t_pause & ~fifo_EF)
pause_irq <= 1'b1;
else if (read_0)
pause_irq <= 1'b0;
end
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
begin
r_val <= 1'b0;
t_dav <= 1'b1;
end
else
begin
r_val <= r_ena & ~wfifo_empty;
t_dav <= ~rfifo_full;
end
end
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
begin
fifo_AE <= 1'b0;
fifo_AF <= 1'b0;
fifo_wr <= 1'b0;
rvalid <= 1'b0;
read_0 <= 1'b0;
ien_AE <= 1'b0;
ien_AF <= 1'b0;
ac <= 1'b0;
woverflow <= 1'b0;
av_waitrequest <= 1'b1;
end
else
begin
fifo_AE <= {fifo_FF,wfifo_used} <= 8;
fifo_AF <= (7'h40 - {rfifo_full,rfifo_used}) <= 8;
fifo_wr <= 1'b0;
read_0 <= 1'b0;
av_waitrequest <= ~(av_chipselect & (~av_write_n | ~av_read_n) & av_waitrequest);
if (activity)
ac <= 1'b1;
// write
if (av_chipselect & ~av_write_n & av_waitrequest)
// addr 1 is control; addr 0 is data
if (av_address)
begin
ien_AF <= av_writedata[0];
ien_AE <= av_writedata[1];
if (av_writedata[10] & ~activity)
ac <= 1'b0;
end
else
begin
fifo_wr <= ~fifo_FF;
woverflow <= fifo_FF;
end
// read
if (av_chipselect & ~av_read_n & av_waitrequest)
begin
// addr 1 is interrupt; addr 0 is data
if (~av_address)
rvalid <= ~fifo_EF;
read_0 <= ~av_address;
end
end
end
assign fifo_wdata = av_writedata[7 : 0];
assign fifo_rd = (av_chipselect & ~av_read_n & av_waitrequest & ~av_address) ? ~fifo_EF : 1'b0;
assign av_readdata = read_0 ? { {9{1'b0}},rfifo_full,rfifo_used,rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,fifo_rdata } : { {9{1'b0}},(7'h40 - {fifo_FF,wfifo_used}),rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,{6{1'b0}},ien_AE,ien_AF };
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
readyfordata <= 0;
else
readyfordata <= ~fifo_FF;
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
// Tie off Atlantic Interface signals not used for simulation
always @(posedge clk)
begin
sim_t_pause <= 1'b0;
sim_t_ena <= 1'b0;
sim_t_dat <= t_dav ? r_dat : {8{r_val}};
sim_r_ena <= 1'b0;
end
assign r_ena = sim_r_ena;
assign t_ena = sim_t_ena;
assign t_dat = sim_t_dat;
assign t_pause = sim_t_pause;
always @(fifo_EF)
begin
dataavailable = ~fifo_EF;
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// alt_jtag_atlantic wasca_jtag_uart_0_alt_jtag_atlantic
// (
// .clk (clk),
// .r_dat (r_dat),
// .r_ena (r_ena),
// .r_val (r_val),
// .rst_n (rst_n),
// .t_dat (t_dat),
// .t_dav (t_dav),
// .t_ena (t_ena),
// .t_pause (t_pause)
// );
//
// defparam wasca_jtag_uart_0_alt_jtag_atlantic.INSTANCE_ID = 0,
// wasca_jtag_uart_0_alt_jtag_atlantic.LOG2_RXFIFO_DEPTH = 6,
// wasca_jtag_uart_0_alt_jtag_atlantic.LOG2_TXFIFO_DEPTH = 6,
// wasca_jtag_uart_0_alt_jtag_atlantic.SLD_AUTO_INSTANCE_INDEX = "YES";
//
// always @(posedge clk or negedge rst_n)
// begin
// if (rst_n == 0)
// dataavailable <= 0;
// else
// dataavailable <= ~fifo_EF;
// end
//
//
//synthesis read_comments_as_HDL off
endmodule
|
//`include "async_receiver.v"
//`include "async_transmitter.v"
// by teknohog, replaces virtual_wire by rs232
module serial_receive(clk, RxD, midstate, data2);
input clk;
input RxD;
wire RxD_data_ready;
wire [7:0] RxD_data;
async_receiver deserializer(.clk(clk), .RxD(RxD), .RxD_data_ready(RxD_data_ready), .RxD_data(RxD_data));
output [255:0] midstate;
output [255:0] data2;
// 256 bits midstate + 256 bits data at the same time = 64 bytes
// Might be a good idea to add some fixed start and stop sequences,
// so we really know we got all the data and nothing more. If a
// test for these fails, should ask for new data, so it needs more
// logic on the return side too. The check bits could be legible
// 7seg for quick feedback :)
reg [511:0] input_buffer;
reg [511:0] input_copy;
reg [6:0] demux_state = 7'b0000000;
assign midstate = input_copy[511:256];
assign data2 = input_copy[255:0];
// we probably don't need a busy signal here, just read the latest
// complete input that is available.
always @(posedge clk)
case (demux_state)
7'b1000000:
begin
input_copy <= input_buffer;
demux_state <= 0;
end
default:
if(RxD_data_ready)
begin
input_buffer <= input_buffer << 8;
input_buffer[7:0] <= RxD_data;
demux_state <= demux_state + 1;
end
endcase // case (demux_state)
endmodule // serial_receive
module serial_transmit (clk, TxD, busy, send, word);
// split 4-byte output into bytes
wire TxD_start;
wire TxD_busy;
reg [7:0] out_byte;
reg serial_start;
reg [3:0] mux_state = 4'b0000;
assign TxD_start = serial_start;
input clk;
output TxD;
input [31:0] word;
input send;
output busy;
reg [31:0] word_copy;
assign busy = (|mux_state);
always @(posedge clk)
begin
/*
case (mux_state)
4'b0000:
if (send)
begin
mux_state <= 4'b1000;
word_copy <= word;
end
4'b1000: out_byte <= word_copy[31:24];
4'b1010: out_byte <= word_copy[23:16];
4'b1100: out_byte <= word_copy[15:8];
4'b1110: out_byte <= word_copy[7:0];
default: mux_state <= 4'b0000;
endcase // case (mux_state)
*/
// Testing for busy is problematic if we are keeping the
// module busy all the time :-/ So we need some wait stages
// between the bytes.
if (!busy && send)
begin
mux_state <= 4'b1000;
word_copy <= word;
end
else if (mux_state[3] && ~mux_state[0] && !TxD_busy)
begin
serial_start <= 1;
mux_state <= mux_state + 1;
out_byte <= word_copy[31:24];
word_copy <= (word_copy << 8);
end
// wait stages
else if (mux_state[3] && mux_state[0])
begin
serial_start <= 0;
if (!TxD_busy) mux_state <= mux_state + 1;
end
end
async_transmitter serializer(.clk(clk), .TxD(TxD), .TxD_start(TxD_start), .TxD_data(out_byte), .TxD_busy(TxD_busy));
endmodule // serial_send
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//altera message_off 10036
///////////////////////////////////////////////////////////////////////////////
// Title : DDR controller AFi interfacing block
//
// File : afi_block.v
//
// Abstract : AFi block
///////////////////////////////////////////////////////////////////////////////
//Things to check
//1. Does afi_wlat need to be registered?
//2. Does ecc_wdata_fifo_read generation changes with ECC
//3. Why in ddrx controller int_dqs_burst and int_wdata_valid signals are registered when CFG_OUTPUT_REGD is 1. Why complex logic instead of simple registering??
//4. We need rdwr_data_valid signal from arbiter to determine how many datas are valid within one dram burst
//5. Do we need to end rdwr_data_valid with doing_write to generate ecc_wdata_fifo_read? Yes
//6. Look at all comments and SPRs for old ddrx afi block
//7. Currently additive_latency, ECC, HR features are not supported
`timescale 1 ps / 1 ps
module alt_mem_ddrx_rdwr_data_tmg
# (parameter
CFG_DWIDTH_RATIO = 2,
CFG_MEM_IF_CHIP = 1,
CFG_MEM_IF_DQ_WIDTH = 8,
CFG_MEM_IF_DQS_WIDTH = 1,
CFG_MEM_IF_DM_WIDTH = 1,
CFG_WLAT_BUS_WIDTH = 6,
CFG_DRAM_WLAT_GROUP = 1,
CFG_DATA_ID_WIDTH = 10,
CFG_WDATA_REG = 0,
CFG_ECC_ENC_REG = 0,
CFG_AFI_INTF_PHASE_NUM = 2,
CFG_PORT_WIDTH_ENABLE_ECC = 1,
CFG_PORT_WIDTH_OUTPUT_REGD = 1,
CFG_CTL_ARBITER_TYPE = "ROWCOL",
CFG_USE_SHADOW_REGS = 0
)
(
ctl_clk,
ctl_reset_n,
// configuration
cfg_enable_ecc,
cfg_output_regd,
cfg_output_regd_for_afi_output,
//Arbiter command input
bg_do_read,
bg_do_write,
bg_doing_read,
bg_doing_write,
bg_rdwr_data_valid, //Required for user burst length lesser than dram burst length
dataid,
bg_do_rmw_correct,
bg_do_rmw_partial,
bg_to_chip,
//Inputs from ECC/WFIFO blocks
ecc_wdata,
ecc_dm,
//Input from AFI Block
afi_wlat,
//Output from AFI Block
afi_doing_read, //Use to generate rdata_valid signals in PHY
afi_doing_read_full, //AFI 2.0 signal, used by UniPHY for dqs enable control
ecc_wdata_fifo_read,
ecc_wdata_fifo_dataid,
ecc_wdata_fifo_dataid_vector,
ecc_wdata_fifo_rmw_correct,
ecc_wdata_fifo_rmw_partial,
ecc_wdata_fifo_read_first,
ecc_wdata_fifo_dataid_first,
ecc_wdata_fifo_dataid_vector_first,
ecc_wdata_fifo_rmw_correct_first,
ecc_wdata_fifo_rmw_partial_first,
ecc_wdata_fifo_first_vector,
ecc_wdata_fifo_read_last,
ecc_wdata_fifo_dataid_last,
ecc_wdata_fifo_dataid_vector_last,
ecc_wdata_fifo_rmw_correct_last,
ecc_wdata_fifo_rmw_partial_last,
afi_rrank,
afi_wrank,
afi_dqs_burst,
afi_wdata_valid,
afi_wdata,
afi_dm
);
localparam integer CFG_WLAT_PIPE_LENGTH = 2**(CFG_WLAT_BUS_WIDTH/CFG_DRAM_WLAT_GROUP);
localparam integer CFG_DATAID_ARRAY_DEPTH = 2**CFG_DATA_ID_WIDTH;
integer i;
//=================================================================================================//
// input/output declaration //
//=================================================================================================//
input ctl_clk;
input ctl_reset_n;
// configuration
input [CFG_PORT_WIDTH_ENABLE_ECC-1:0] cfg_enable_ecc;
input [CFG_PORT_WIDTH_OUTPUT_REGD-1:0] cfg_output_regd;
output [CFG_PORT_WIDTH_OUTPUT_REGD-1:0] cfg_output_regd_for_afi_output;
//Arbiter command input
input [CFG_AFI_INTF_PHASE_NUM-1:0] bg_do_read;
input [CFG_AFI_INTF_PHASE_NUM-1:0] bg_do_write;
input bg_doing_read;
input bg_doing_write;
input bg_rdwr_data_valid;
input [CFG_DATA_ID_WIDTH-1:0] dataid;
input [CFG_AFI_INTF_PHASE_NUM-1:0] bg_do_rmw_correct;
input [CFG_AFI_INTF_PHASE_NUM-1:0] bg_do_rmw_partial;
input [(CFG_AFI_INTF_PHASE_NUM*CFG_MEM_IF_CHIP)-1:0] bg_to_chip;
//Inputs from ECC/WFIFO blocks
input [CFG_MEM_IF_DQ_WIDTH*CFG_DWIDTH_RATIO-1:0] ecc_wdata;
input [(CFG_MEM_IF_DQ_WIDTH*CFG_DWIDTH_RATIO)/(CFG_MEM_IF_DQ_WIDTH/CFG_MEM_IF_DQS_WIDTH)-1:0] ecc_dm;
//Input from AFI Block
input [CFG_WLAT_BUS_WIDTH-1:0] afi_wlat;
//output to AFI block
output [CFG_MEM_IF_DQS_WIDTH*(CFG_DWIDTH_RATIO/2)-1:0] afi_doing_read;
output [CFG_MEM_IF_DQS_WIDTH*(CFG_DWIDTH_RATIO/2)-1:0] afi_doing_read_full;
output [CFG_DRAM_WLAT_GROUP-1:0] ecc_wdata_fifo_read;
output [CFG_DRAM_WLAT_GROUP*CFG_DATA_ID_WIDTH-1:0] ecc_wdata_fifo_dataid;
output [CFG_DRAM_WLAT_GROUP*CFG_DATAID_ARRAY_DEPTH-1:0] ecc_wdata_fifo_dataid_vector;
output [CFG_DRAM_WLAT_GROUP-1:0] ecc_wdata_fifo_rmw_correct;
output [CFG_DRAM_WLAT_GROUP-1:0] ecc_wdata_fifo_rmw_partial;
output ecc_wdata_fifo_read_first;
output [CFG_DATA_ID_WIDTH-1:0] ecc_wdata_fifo_dataid_first;
output [CFG_DATAID_ARRAY_DEPTH-1:0] ecc_wdata_fifo_dataid_vector_first;
output ecc_wdata_fifo_rmw_correct_first;
output ecc_wdata_fifo_rmw_partial_first;
output [CFG_DRAM_WLAT_GROUP-1:0] ecc_wdata_fifo_first_vector;
output ecc_wdata_fifo_read_last;
output [CFG_DATA_ID_WIDTH-1:0] ecc_wdata_fifo_dataid_last;
output [CFG_DATAID_ARRAY_DEPTH-1:0] ecc_wdata_fifo_dataid_vector_last;
output ecc_wdata_fifo_rmw_correct_last;
output ecc_wdata_fifo_rmw_partial_last;
output [CFG_MEM_IF_CHIP*(CFG_DWIDTH_RATIO/2)*CFG_MEM_IF_DQS_WIDTH-1:0] afi_rrank;
output [CFG_MEM_IF_CHIP*(CFG_DWIDTH_RATIO/2)*CFG_MEM_IF_DQS_WIDTH-1:0] afi_wrank;
output [CFG_MEM_IF_DQS_WIDTH*(CFG_DWIDTH_RATIO/2)-1:0] afi_dqs_burst;
output [CFG_MEM_IF_DQS_WIDTH*(CFG_DWIDTH_RATIO/2)-1:0] afi_wdata_valid;
output [CFG_MEM_IF_DQ_WIDTH*CFG_DWIDTH_RATIO-1:0] afi_wdata;
output [CFG_MEM_IF_DM_WIDTH*CFG_DWIDTH_RATIO-1:0] afi_dm;
//=================================================================================================//
// reg/wire declaration //
//=================================================================================================//
wire [CFG_AFI_INTF_PHASE_NUM-1:0] bg_do_read;
wire [CFG_AFI_INTF_PHASE_NUM-1:0] bg_do_write;
wire bg_doing_read;
wire bg_doing_write;
wire bg_rdwr_data_valid;
wire [CFG_DATA_ID_WIDTH-1:0] dataid;
wire [CFG_AFI_INTF_PHASE_NUM-1:0] bg_do_rmw_correct;
wire [CFG_AFI_INTF_PHASE_NUM-1:0] bg_do_rmw_partial;
wire [(CFG_AFI_INTF_PHASE_NUM*CFG_MEM_IF_CHIP)-1:0] bg_to_chip;
wire [CFG_MEM_IF_DQS_WIDTH*(CFG_DWIDTH_RATIO/2)-1:0] afi_doing_read;
wire [CFG_MEM_IF_DQS_WIDTH*(CFG_DWIDTH_RATIO/2)-1:0] afi_doing_read_full;
wire [CFG_MEM_IF_DQS_WIDTH*(CFG_DWIDTH_RATIO/2)-1:0] int_afi_doing_read;
wire [CFG_MEM_IF_DQS_WIDTH*(CFG_DWIDTH_RATIO/2)-1:0] int_afi_doing_read_full;
reg [CFG_MEM_IF_DQS_WIDTH*(CFG_DWIDTH_RATIO/2)-1:0] int_afi_doing_read_r;
reg [CFG_MEM_IF_DQS_WIDTH*(CFG_DWIDTH_RATIO/2)-1:0] int_afi_doing_read_full_r;
wire [CFG_DRAM_WLAT_GROUP-1:0] ecc_wdata_fifo_read;
reg [CFG_DRAM_WLAT_GROUP-1:0] ecc_wdata_fifo_read_r1;
reg [CFG_DRAM_WLAT_GROUP-1:0] ecc_wdata_fifo_read_r2;
wire [CFG_DRAM_WLAT_GROUP*CFG_DATA_ID_WIDTH-1:0] ecc_wdata_fifo_dataid;
wire [CFG_DRAM_WLAT_GROUP*CFG_DATAID_ARRAY_DEPTH-1:0] ecc_wdata_fifo_dataid_vector;
wire [CFG_DRAM_WLAT_GROUP-1:0] ecc_wdata_fifo_rmw_correct;
wire [CFG_DRAM_WLAT_GROUP-1:0] ecc_wdata_fifo_rmw_partial;
wire ecc_wdata_fifo_read_first;
wire [CFG_DATA_ID_WIDTH-1:0] ecc_wdata_fifo_dataid_first;
wire [CFG_DATAID_ARRAY_DEPTH-1:0] ecc_wdata_fifo_dataid_vector_first;
wire ecc_wdata_fifo_rmw_correct_first;
wire ecc_wdata_fifo_rmw_partial_first;
reg [CFG_DRAM_WLAT_GROUP-1:0] ecc_wdata_fifo_first_vector;
wire ecc_wdata_fifo_read_last;
wire [CFG_DATA_ID_WIDTH-1:0] ecc_wdata_fifo_dataid_last;
wire [CFG_DATAID_ARRAY_DEPTH-1:0] ecc_wdata_fifo_dataid_vector_last;
wire ecc_wdata_fifo_rmw_correct_last;
wire ecc_wdata_fifo_rmw_partial_last;
wire [CFG_MEM_IF_CHIP*(CFG_DWIDTH_RATIO/2)*CFG_MEM_IF_DQS_WIDTH-1:0] afi_rrank;
wire [CFG_MEM_IF_CHIP*(CFG_DWIDTH_RATIO/2)*CFG_MEM_IF_DQS_WIDTH-1:0] afi_wrank;
wire [CFG_MEM_IF_DQS_WIDTH*(CFG_DWIDTH_RATIO/2)-1:0] afi_dqs_burst;
wire [CFG_MEM_IF_DQS_WIDTH*(CFG_DWIDTH_RATIO/2)-1:0] afi_wdata_valid;
wire [CFG_MEM_IF_DQS_WIDTH*(CFG_DWIDTH_RATIO/2)-1:0] int_afi_dqs_burst;
wire [CFG_MEM_IF_DQS_WIDTH*(CFG_DWIDTH_RATIO/2)-1:0] int_afi_wdata_valid;
reg [CFG_MEM_IF_DQS_WIDTH*(CFG_DWIDTH_RATIO/2)-1:0] int_afi_dqs_burst_r;
reg [CFG_MEM_IF_DQS_WIDTH*(CFG_DWIDTH_RATIO/2)-1:0] int_afi_wdata_valid_r;
wire [CFG_MEM_IF_DQ_WIDTH*CFG_DWIDTH_RATIO-1:0] afi_wdata;
wire [CFG_MEM_IF_DM_WIDTH*CFG_DWIDTH_RATIO-1:0] afi_dm;
//Internal signals
reg [CFG_PORT_WIDTH_OUTPUT_REGD-1:0] cfg_output_regd_for_afi_output_combi [CFG_DRAM_WLAT_GROUP-1:0];
reg [CFG_PORT_WIDTH_OUTPUT_REGD-1:0] cfg_output_regd_for_wdata_path_combi [CFG_DRAM_WLAT_GROUP-1:0];
reg [CFG_PORT_WIDTH_OUTPUT_REGD-1:0] cfg_output_regd_for_afi_output_mux [CFG_DRAM_WLAT_GROUP-1:0];
reg [CFG_PORT_WIDTH_OUTPUT_REGD-1:0] cfg_output_regd_for_wdata_path_mux [CFG_DRAM_WLAT_GROUP-1:0];
reg [CFG_PORT_WIDTH_OUTPUT_REGD-1:0] cfg_output_regd_for_afi_output;
reg [CFG_PORT_WIDTH_OUTPUT_REGD-1:0] cfg_output_regd_for_wdata_path;
reg doing_read_combi;
reg doing_read_full_combi;
reg doing_read_r;
reg doing_read_full_r;
reg [CFG_WLAT_PIPE_LENGTH-1:0] doing_write_pipe;
reg [CFG_WLAT_PIPE_LENGTH-1:0] rdwr_data_valid_pipe;
reg [CFG_WLAT_PIPE_LENGTH-1:0] do_write_pipe;
reg [CFG_WLAT_PIPE_LENGTH-1:0] rmw_correct_pipe;
reg [CFG_WLAT_PIPE_LENGTH-1:0] rmw_partial_pipe;
reg [CFG_DATA_ID_WIDTH-1:0] dataid_pipe [CFG_WLAT_PIPE_LENGTH-1:0];
reg [CFG_DATAID_ARRAY_DEPTH-1:0] dataid_vector_pipe [CFG_WLAT_PIPE_LENGTH-1:0];
reg [CFG_DATAID_ARRAY_DEPTH-1:0] dataid_vector;
reg [CFG_DRAM_WLAT_GROUP-1:0] int_dqs_burst;
reg [CFG_DRAM_WLAT_GROUP-1:0] int_dqs_burst_r;
reg [CFG_DRAM_WLAT_GROUP-1:0] int_wdata_valid;
reg [CFG_DRAM_WLAT_GROUP-1:0] int_wdata_valid_r;
reg [CFG_DRAM_WLAT_GROUP-1:0] int_real_wdata_valid;
reg [CFG_DRAM_WLAT_GROUP-1:0] int_ecc_wdata_fifo_read;
reg [CFG_DRAM_WLAT_GROUP-1:0] int_ecc_wdata_fifo_read_r;
reg [CFG_DATA_ID_WIDTH-1:0] int_ecc_wdata_fifo_dataid [CFG_DRAM_WLAT_GROUP-1:0];
reg [CFG_DATA_ID_WIDTH-1:0] int_ecc_wdata_fifo_dataid_r [CFG_DRAM_WLAT_GROUP-1:0];
reg [CFG_DATAID_ARRAY_DEPTH-1:0] int_ecc_wdata_fifo_dataid_vector [CFG_DRAM_WLAT_GROUP-1:0];
reg [CFG_DATAID_ARRAY_DEPTH-1:0] int_ecc_wdata_fifo_dataid_vector_r [CFG_DRAM_WLAT_GROUP-1:0];
reg [CFG_DRAM_WLAT_GROUP-1:0] int_ecc_wdata_fifo_rmw_correct;
reg [CFG_DRAM_WLAT_GROUP-1:0] int_ecc_wdata_fifo_rmw_correct_r;
reg [CFG_DRAM_WLAT_GROUP-1:0] int_ecc_wdata_fifo_rmw_partial;
reg [CFG_DRAM_WLAT_GROUP-1:0] int_ecc_wdata_fifo_rmw_partial_r;
reg [CFG_MEM_IF_CHIP-1:0] wr_chip_pipe [CFG_WLAT_PIPE_LENGTH-1:0];
reg [CFG_MEM_IF_CHIP-1:0] int_to_chip;
reg [CFG_MEM_IF_CHIP-1:0] int_rank [CFG_MEM_IF_DQS_WIDTH-1:0];
reg [CFG_MEM_IF_CHIP-1:0] rd_chip;
reg [CFG_MEM_IF_CHIP-1:0] int_rd_rank_full_rate;
reg [CFG_MEM_IF_CHIP-1:0] int_rd_rank_full_rate_r;
reg [CFG_MEM_IF_CHIP-1:0] int_wr_rank_full_rate [CFG_MEM_IF_DQS_WIDTH-1:0];
reg [CFG_MEM_IF_CHIP-1:0] int_wr_rank_full_rate_r [CFG_MEM_IF_DQS_WIDTH-1:0];
reg [CFG_MEM_IF_CHIP-1:0] int_wr_rank_half_rate [CFG_MEM_IF_DQS_WIDTH-1:0];
reg [CFG_MEM_IF_CHIP-1:0] int_wr_rank_half_rate_r [CFG_MEM_IF_DQS_WIDTH-1:0];
wire [CFG_MEM_IF_CHIP*(CFG_DWIDTH_RATIO/2)*CFG_MEM_IF_DQS_WIDTH-1:0] int_rd_rank;
wire [CFG_MEM_IF_CHIP*(CFG_DWIDTH_RATIO/2)*CFG_MEM_IF_DQS_WIDTH-1:0] int_wr_rank;
reg [CFG_MEM_IF_CHIP*(CFG_DWIDTH_RATIO/2)*CFG_MEM_IF_DQS_WIDTH-1:0] int_rd_rank_r;
reg [CFG_MEM_IF_CHIP*(CFG_DWIDTH_RATIO/2)*CFG_MEM_IF_DQS_WIDTH-1:0] int_wr_rank_r;
wire int_do_rmw_correct;
wire int_do_rmw_partial;
// DQS burst logic for half rate design
reg [CFG_DRAM_WLAT_GROUP-1:0] int_dqs_burst_half_rate;
reg [CFG_DRAM_WLAT_GROUP-1:0] int_dqs_burst_half_rate_r;
reg [CFG_DRAM_WLAT_GROUP-1:0] first_afi_wlat;
reg [CFG_DRAM_WLAT_GROUP-1:0] last_afi_wlat;
reg [CFG_WLAT_BUS_WIDTH/CFG_DRAM_WLAT_GROUP-1:0] smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1:0];
reg [CFG_WLAT_BUS_WIDTH/CFG_DRAM_WLAT_GROUP-1:0] largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1:0];
reg smallest_afi_wlat_eq_0;
reg [CFG_WLAT_BUS_WIDTH/CFG_DRAM_WLAT_GROUP-1:0] smallest_afi_wlat_minus_1;
reg [CFG_WLAT_BUS_WIDTH/CFG_DRAM_WLAT_GROUP-1:0] smallest_afi_wlat_minus_2;
reg [CFG_WLAT_BUS_WIDTH/CFG_DRAM_WLAT_GROUP-1:0] smallest_afi_wlat_minus_3;
reg [CFG_WLAT_BUS_WIDTH/CFG_DRAM_WLAT_GROUP-1:0] smallest_afi_wlat_minus_4;
reg smallest_doing_write_pipe_eq_afi_wlat_minus_0;
reg smallest_doing_write_pipe_eq_afi_wlat_minus_1;
reg smallest_doing_write_pipe_eq_afi_wlat_minus_2;
reg smallest_doing_write_pipe_eq_afi_wlat_minus_3;
reg smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1;
reg smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2;
reg smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_3;
reg [CFG_DATA_ID_WIDTH-1:0] smallest_dataid_pipe_eq_afi_wlat_minus_1;
reg [CFG_DATA_ID_WIDTH-1:0] smallest_dataid_pipe_eq_afi_wlat_minus_2;
reg [CFG_DATA_ID_WIDTH-1:0] smallest_dataid_pipe_eq_afi_wlat_minus_3;
reg [CFG_DATAID_ARRAY_DEPTH-1:0] smallest_dataid_vector_pipe_eq_afi_wlat_minus_1;
reg [CFG_DATAID_ARRAY_DEPTH-1:0] smallest_dataid_vector_pipe_eq_afi_wlat_minus_2;
reg [CFG_DATAID_ARRAY_DEPTH-1:0] smallest_dataid_vector_pipe_eq_afi_wlat_minus_3;
reg smallest_rmw_correct_pipe_eq_afi_wlat_minus_1;
reg smallest_rmw_correct_pipe_eq_afi_wlat_minus_2;
reg smallest_rmw_correct_pipe_eq_afi_wlat_minus_3;
reg smallest_rmw_partial_pipe_eq_afi_wlat_minus_1;
reg smallest_rmw_partial_pipe_eq_afi_wlat_minus_2;
reg smallest_rmw_partial_pipe_eq_afi_wlat_minus_3;
reg smallest_doing_write_pipe_eq_afi_wlat_minus_x;
reg smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_x;
reg [CFG_DATA_ID_WIDTH-1:0] smallest_dataid_pipe_eq_afi_wlat_minus_x;
reg [CFG_DATAID_ARRAY_DEPTH-1:0] smallest_dataid_vector_pipe_eq_afi_wlat_minus_x;
reg smallest_rmw_correct_pipe_eq_afi_wlat_minus_x;
reg smallest_rmw_partial_pipe_eq_afi_wlat_minus_x;
reg largest_afi_wlat_eq_0;
reg [CFG_WLAT_BUS_WIDTH/CFG_DRAM_WLAT_GROUP-1:0] largest_afi_wlat_minus_1;
reg [CFG_WLAT_BUS_WIDTH/CFG_DRAM_WLAT_GROUP-1:0] largest_afi_wlat_minus_2;
reg [CFG_WLAT_BUS_WIDTH/CFG_DRAM_WLAT_GROUP-1:0] largest_afi_wlat_minus_3;
reg [CFG_WLAT_BUS_WIDTH/CFG_DRAM_WLAT_GROUP-1:0] largest_afi_wlat_minus_4;
reg largest_doing_write_pipe_eq_afi_wlat_minus_0;
reg largest_doing_write_pipe_eq_afi_wlat_minus_1;
reg largest_doing_write_pipe_eq_afi_wlat_minus_2;
reg largest_doing_write_pipe_eq_afi_wlat_minus_3;
reg largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1;
reg largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2;
reg largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_3;
reg [CFG_DATA_ID_WIDTH-1:0] largest_dataid_pipe_eq_afi_wlat_minus_1;
reg [CFG_DATA_ID_WIDTH-1:0] largest_dataid_pipe_eq_afi_wlat_minus_2;
reg [CFG_DATA_ID_WIDTH-1:0] largest_dataid_pipe_eq_afi_wlat_minus_3;
reg [CFG_DATAID_ARRAY_DEPTH-1:0] largest_dataid_vector_pipe_eq_afi_wlat_minus_1;
reg [CFG_DATAID_ARRAY_DEPTH-1:0] largest_dataid_vector_pipe_eq_afi_wlat_minus_2;
reg [CFG_DATAID_ARRAY_DEPTH-1:0] largest_dataid_vector_pipe_eq_afi_wlat_minus_3;
reg largest_rmw_correct_pipe_eq_afi_wlat_minus_1;
reg largest_rmw_correct_pipe_eq_afi_wlat_minus_2;
reg largest_rmw_correct_pipe_eq_afi_wlat_minus_3;
reg largest_rmw_partial_pipe_eq_afi_wlat_minus_1;
reg largest_rmw_partial_pipe_eq_afi_wlat_minus_2;
reg largest_rmw_partial_pipe_eq_afi_wlat_minus_3;
reg largest_doing_write_pipe_eq_afi_wlat_minus_x;
reg largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_x;
reg [CFG_DATA_ID_WIDTH-1:0] largest_dataid_pipe_eq_afi_wlat_minus_x;
reg [CFG_DATAID_ARRAY_DEPTH-1:0] largest_dataid_vector_pipe_eq_afi_wlat_minus_x;
reg largest_rmw_correct_pipe_eq_afi_wlat_minus_x;
reg largest_rmw_partial_pipe_eq_afi_wlat_minus_x;
reg afi_wlat_eq_0 [CFG_DRAM_WLAT_GROUP-1:0];
reg [CFG_WLAT_BUS_WIDTH/CFG_DRAM_WLAT_GROUP-1:0] afi_wlat_minus_1 [CFG_DRAM_WLAT_GROUP-1:0];
reg [CFG_WLAT_BUS_WIDTH/CFG_DRAM_WLAT_GROUP-1:0] afi_wlat_minus_2 [CFG_DRAM_WLAT_GROUP-1:0];
reg [CFG_WLAT_BUS_WIDTH/CFG_DRAM_WLAT_GROUP-1:0] afi_wlat_minus_3 [CFG_DRAM_WLAT_GROUP-1:0];
reg [CFG_WLAT_BUS_WIDTH/CFG_DRAM_WLAT_GROUP-1:0] afi_wlat_minus_4 [CFG_DRAM_WLAT_GROUP-1:0];
reg doing_write_pipe_eq_afi_wlat_minus_0 [CFG_DRAM_WLAT_GROUP-1:0];
reg doing_write_pipe_eq_afi_wlat_minus_1 [CFG_DRAM_WLAT_GROUP-1:0];
reg doing_write_pipe_eq_afi_wlat_minus_2 [CFG_DRAM_WLAT_GROUP-1:0];
reg doing_write_pipe_eq_afi_wlat_minus_3 [CFG_DRAM_WLAT_GROUP-1:0];
reg rdwr_data_valid_pipe_eq_afi_wlat_minus_1 [CFG_DRAM_WLAT_GROUP-1:0];
reg rdwr_data_valid_pipe_eq_afi_wlat_minus_2 [CFG_DRAM_WLAT_GROUP-1:0];
reg rdwr_data_valid_pipe_eq_afi_wlat_minus_3 [CFG_DRAM_WLAT_GROUP-1:0];
reg [CFG_DATA_ID_WIDTH-1:0] dataid_pipe_eq_afi_wlat_minus_1 [CFG_DRAM_WLAT_GROUP-1:0];
reg [CFG_DATA_ID_WIDTH-1:0] dataid_pipe_eq_afi_wlat_minus_2 [CFG_DRAM_WLAT_GROUP-1:0];
reg [CFG_DATA_ID_WIDTH-1:0] dataid_pipe_eq_afi_wlat_minus_3 [CFG_DRAM_WLAT_GROUP-1:0];
reg [CFG_DATAID_ARRAY_DEPTH-1:0] dataid_vector_pipe_eq_afi_wlat_minus_1 [CFG_DRAM_WLAT_GROUP-1:0];
reg [CFG_DATAID_ARRAY_DEPTH-1:0] dataid_vector_pipe_eq_afi_wlat_minus_2 [CFG_DRAM_WLAT_GROUP-1:0];
reg [CFG_DATAID_ARRAY_DEPTH-1:0] dataid_vector_pipe_eq_afi_wlat_minus_3 [CFG_DRAM_WLAT_GROUP-1:0];
reg rmw_correct_pipe_eq_afi_wlat_minus_1 [CFG_DRAM_WLAT_GROUP-1:0];
reg rmw_correct_pipe_eq_afi_wlat_minus_2 [CFG_DRAM_WLAT_GROUP-1:0];
reg rmw_correct_pipe_eq_afi_wlat_minus_3 [CFG_DRAM_WLAT_GROUP-1:0];
reg rmw_partial_pipe_eq_afi_wlat_minus_1 [CFG_DRAM_WLAT_GROUP-1:0];
reg rmw_partial_pipe_eq_afi_wlat_minus_2 [CFG_DRAM_WLAT_GROUP-1:0];
reg rmw_partial_pipe_eq_afi_wlat_minus_3 [CFG_DRAM_WLAT_GROUP-1:0];
reg doing_write_pipe_eq_afi_wlat_minus_x [CFG_DRAM_WLAT_GROUP-1:0];
reg rdwr_data_valid_pipe_eq_afi_wlat_minus_x [CFG_DRAM_WLAT_GROUP-1:0];
reg [CFG_DATA_ID_WIDTH-1:0] dataid_pipe_eq_afi_wlat_minus_x [CFG_DRAM_WLAT_GROUP-1:0];
reg [CFG_DATAID_ARRAY_DEPTH-1:0] dataid_vector_pipe_eq_afi_wlat_minus_x [CFG_DRAM_WLAT_GROUP-1:0];
reg rmw_correct_pipe_eq_afi_wlat_minus_x [CFG_DRAM_WLAT_GROUP-1:0];
reg rmw_partial_pipe_eq_afi_wlat_minus_x [CFG_DRAM_WLAT_GROUP-1:0];
reg do_write_pipe_eq_afi_wlat_minus_0 [CFG_DRAM_WLAT_GROUP-1:0];
reg do_write_pipe_eq_afi_wlat_minus_1 [CFG_DRAM_WLAT_GROUP-1:0];
reg do_write_pipe_eq_afi_wlat_minus_2 [CFG_DRAM_WLAT_GROUP-1:0];
reg [CFG_MEM_IF_CHIP-1:0] wr_chip_pipe_eq_afi_wlat_minus_0 [CFG_DRAM_WLAT_GROUP-1:0];
reg [CFG_MEM_IF_CHIP-1:0] wr_chip_pipe_eq_afi_wlat_minus_1 [CFG_DRAM_WLAT_GROUP-1:0];
wire one = 1'b1;
wire zero = 1'b0;
//=================================================================================================//
// Internal cfg_output_regd //
//=================================================================================================//
generate
genvar N;
for (N = 0;N < CFG_DRAM_WLAT_GROUP;N = N + 1)
begin : output_regd_logic_per_dqs_group
always @ (*)
begin
if (CFG_WDATA_REG && CFG_ECC_ENC_REG)
begin
// When both wdata_reg and ecc_reg is enabled
// we need to fetch data from wdata path earlier and delay the command path
if (afi_wlat [(N + 1) * (CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP) - 1 : N * (CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP)] <= 1)
begin
// Extra latency one afi command output, to match wdata output latency
cfg_output_regd_for_afi_output_combi [N] = 2'd2;
cfg_output_regd_for_wdata_path_combi [N] = 2'd0;
end
else if (afi_wlat [(N + 1) * (CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP) - 1 : N * (CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP)] == 2)
begin
cfg_output_regd_for_afi_output_combi [N] = 2'd1;
cfg_output_regd_for_wdata_path_combi [N] = 2'd0;
end
else
begin
cfg_output_regd_for_afi_output_combi [N] = cfg_output_regd;
cfg_output_regd_for_wdata_path_combi [N] = cfg_output_regd;
end
end
else if (CFG_WDATA_REG || CFG_ECC_ENC_REG)
begin
if (afi_wlat [(N + 1) * (CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP) - 1 : N * (CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP)] <= 1)
begin
// We enable output_regd for signals going to PHY
// because we need to fetch data 2 clock cycles earlier
cfg_output_regd_for_afi_output_combi [N] = 2'd1;
// We disable output_regd for signals going to wdata_path
// because we need to fecth data 2 clock cycles earlier
cfg_output_regd_for_wdata_path_combi [N] = 2'd0;
end
else
begin
cfg_output_regd_for_afi_output_combi [N] = cfg_output_regd;
cfg_output_regd_for_wdata_path_combi [N] = cfg_output_regd;
end
end
else
begin
cfg_output_regd_for_afi_output_combi [N] = cfg_output_regd;
cfg_output_regd_for_wdata_path_combi [N] = cfg_output_regd;
end
end
end
for (N = 1;N < CFG_DRAM_WLAT_GROUP;N = N + 1)
begin : output_regd_mux_logic
always @ (*)
begin
cfg_output_regd_for_afi_output_mux [N] = cfg_output_regd_for_afi_output_combi [N] | cfg_output_regd_for_afi_output_mux [N-1];
cfg_output_regd_for_wdata_path_mux [N] = cfg_output_regd_for_wdata_path_combi [N] | cfg_output_regd_for_wdata_path_mux [N-1];
end
end
endgenerate
always @ (*)
begin
cfg_output_regd_for_afi_output_mux [0] = cfg_output_regd_for_afi_output_combi [0];
cfg_output_regd_for_wdata_path_mux [0] = cfg_output_regd_for_wdata_path_combi [0];
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
cfg_output_regd_for_afi_output <= 2'd0;
cfg_output_regd_for_wdata_path <= 2'd0;
end
else
begin
cfg_output_regd_for_afi_output <= cfg_output_regd_for_afi_output_mux [CFG_DRAM_WLAT_GROUP-1];
cfg_output_regd_for_wdata_path <= cfg_output_regd_for_wdata_path_mux [CFG_DRAM_WLAT_GROUP-1];
end
end
//=================================================================================================//
// Read timing logic //
//=================================================================================================//
//*************************************************************************************************//
// afi_doing_read generation logic //
//*************************************************************************************************//
always @(*)
begin
if (bg_doing_read && bg_rdwr_data_valid)
begin
doing_read_combi = 1'b1;
end
else
begin
doing_read_combi = 1'b0;
end
doing_read_full_combi = bg_doing_read;
end
// registered output
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
doing_read_r <= 1'b0;
doing_read_full_r <= 1'b0;
end
else
begin
doing_read_r <= doing_read_combi;
doing_read_full_r <= doing_read_full_combi;
end
end
generate
genvar I;
for (I = 0; I < CFG_MEM_IF_DQS_WIDTH*(CFG_DWIDTH_RATIO/2); I = I + 1)
begin : B
assign int_afi_doing_read [I] = (cfg_output_regd_for_afi_output) ? doing_read_r : doing_read_combi;
assign int_afi_doing_read_full [I] = (cfg_output_regd_for_afi_output) ? doing_read_full_r : doing_read_full_combi;
end
endgenerate
// Registered output
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_afi_doing_read_r <= 0;
int_afi_doing_read_full_r <= 0;
end
else
begin
int_afi_doing_read_r <= int_afi_doing_read;
int_afi_doing_read_full_r <= int_afi_doing_read_full;
end
end
assign afi_doing_read = (cfg_output_regd_for_afi_output == 2) ? int_afi_doing_read_r : int_afi_doing_read;
assign afi_doing_read_full = (cfg_output_regd_for_afi_output == 2) ? int_afi_doing_read_full_r : int_afi_doing_read_full;
//=================================================================================================//
// Write timing logic //
//=================================================================================================//
// Content of pipe shows how long dqs should toggle, used to generate dqs_burst
// content of pipe is also used to generate wdata_valid signal
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
doing_write_pipe <= 0;
end
else
begin
doing_write_pipe <= {doing_write_pipe[CFG_WLAT_PIPE_LENGTH-2:0],bg_doing_write};
end
end
// content of pipe shows how much data should be read out of the write data FIFO
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
rdwr_data_valid_pipe <= 0;
end
else
begin
rdwr_data_valid_pipe <= {rdwr_data_valid_pipe[CFG_WLAT_PIPE_LENGTH- 2:0],bg_rdwr_data_valid};
end
end
// do_write pipe information
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
do_write_pipe <= 0;
end
else
begin
do_write_pipe <= {do_write_pipe[CFG_WLAT_PIPE_LENGTH-2:0],|bg_do_write};
end
end
// to_chip pipe for write command
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_WLAT_PIPE_LENGTH; i=i+1)
begin
wr_chip_pipe [i] <= 0;
end
end
else
begin
wr_chip_pipe [0] <= int_to_chip;
for (i=1; i<CFG_WLAT_PIPE_LENGTH; i=i+1)
begin
wr_chip_pipe [i] <= wr_chip_pipe [i-1];
end
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_WLAT_PIPE_LENGTH; i=i+1)
begin
dataid_pipe [i] <= 0;
end
end
else
begin
dataid_pipe [0] <= dataid;
for (i=1; i<CFG_WLAT_PIPE_LENGTH; i=i+1)
begin
dataid_pipe [i] <= dataid_pipe [i-1];
end
end
end
//pre-calculated dataid comparison logic
always @ (*)
begin
for (i=0; i<(CFG_DATAID_ARRAY_DEPTH); i=i+1)
begin
if (dataid == i)
begin
dataid_vector [i] = 1'b1;
end
else
begin
dataid_vector [i] = 1'b0;
end
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
dataid_vector_pipe [0] <= 0;
for (i=1; i<CFG_WLAT_PIPE_LENGTH; i=i+1)
begin
dataid_vector_pipe [i] <= 0;
end
end
else
begin
dataid_vector_pipe [0] <= dataid_vector;
for (i=1; i<CFG_WLAT_PIPE_LENGTH; i=i+1)
begin
dataid_vector_pipe [i] <= dataid_vector_pipe[i-1];
end
end
end
assign int_do_rmw_correct = |bg_do_rmw_correct;
assign int_do_rmw_partial = |bg_do_rmw_partial;
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
rmw_correct_pipe <= 0;
end
else
begin
rmw_correct_pipe <= {rmw_correct_pipe[CFG_WLAT_PIPE_LENGTH - 2:0],int_do_rmw_correct};
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
rmw_partial_pipe <= 0;
end
else
begin
rmw_partial_pipe <= {rmw_partial_pipe[CFG_WLAT_PIPE_LENGTH - 2:0],int_do_rmw_partial};
end
end
// Pre-calculated logic for each DQS group
generate
genvar P;
for (P = 0;P < CFG_DRAM_WLAT_GROUP;P = P + 1)
begin : pre_calculate_logic_per_dqs_group
// afi_wlat for current DQS group
wire [(CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP) - 1 : 0] current_afi_wlat = afi_wlat [(P + 1) * (CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP) - 1 : P * (CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP)];
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
afi_wlat_eq_0 [P] <= 1'b0;
afi_wlat_minus_1 [P] <= {(CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP){1'b0}};
afi_wlat_minus_2 [P] <= {(CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP){1'b0}};
afi_wlat_minus_3 [P] <= {(CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP){1'b0}};
afi_wlat_minus_4 [P] <= {(CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP){1'b0}};
end
else
begin
if (current_afi_wlat == 0)
begin
afi_wlat_eq_0 [P] <= 1'b1;
end
else
begin
afi_wlat_eq_0 [P] <= 1'b0;
end
afi_wlat_minus_1 [P] <= current_afi_wlat - 1'd1;
afi_wlat_minus_2 [P] <= current_afi_wlat - 2'd2;
afi_wlat_minus_3 [P] <= current_afi_wlat - 2'd3;
afi_wlat_minus_4 [P] <= current_afi_wlat - 3'd4;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
doing_write_pipe_eq_afi_wlat_minus_0 [P] <= 1'b0;
doing_write_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
doing_write_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
doing_write_pipe_eq_afi_wlat_minus_3 [P] <= 1'b0;
end
else
begin
if (current_afi_wlat == 0)
begin
doing_write_pipe_eq_afi_wlat_minus_0 [P] <= 1'b0;
doing_write_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
doing_write_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
doing_write_pipe_eq_afi_wlat_minus_3 [P] <= 1'b0;
end
else if (current_afi_wlat == 1)
begin
if (doing_write_pipe[0])
begin
doing_write_pipe_eq_afi_wlat_minus_0 [P] <= 1'b1;
end
else
begin
doing_write_pipe_eq_afi_wlat_minus_0 [P] <= 1'b0;
end
if (bg_doing_write)
begin
doing_write_pipe_eq_afi_wlat_minus_1 [P] <= 1'b1;
end
else
begin
doing_write_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
end
if (bg_doing_write)
begin
doing_write_pipe_eq_afi_wlat_minus_2 [P] <= 1'b1;
end
else
begin
doing_write_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
end
if (bg_doing_write)
begin
doing_write_pipe_eq_afi_wlat_minus_3 [P] <= 1'b1;
end
else
begin
doing_write_pipe_eq_afi_wlat_minus_3 [P] <= 1'b0;
end
end
else if (current_afi_wlat == 2)
begin
if (doing_write_pipe[1])
begin
doing_write_pipe_eq_afi_wlat_minus_0 [P] <= 1'b1;
end
else
begin
doing_write_pipe_eq_afi_wlat_minus_0 [P] <= 1'b0;
end
if (doing_write_pipe[0])
begin
doing_write_pipe_eq_afi_wlat_minus_1 [P] <= 1'b1;
end
else
begin
doing_write_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
end
if (bg_doing_write)
begin
doing_write_pipe_eq_afi_wlat_minus_2 [P] <= 1'b1;
end
else
begin
doing_write_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
end
if (bg_doing_write)
begin
doing_write_pipe_eq_afi_wlat_minus_3 [P] <= 1'b1;
end
else
begin
doing_write_pipe_eq_afi_wlat_minus_3 [P] <= 1'b0;
end
end
else if (current_afi_wlat == 3)
begin
if (doing_write_pipe[2])
begin
doing_write_pipe_eq_afi_wlat_minus_0 [P] <= 1'b1;
end
else
begin
doing_write_pipe_eq_afi_wlat_minus_0 [P] <= 1'b0;
end
if (doing_write_pipe[1])
begin
doing_write_pipe_eq_afi_wlat_minus_1 [P] <= 1'b1;
end
else
begin
doing_write_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
end
if (doing_write_pipe[0])
begin
doing_write_pipe_eq_afi_wlat_minus_2 [P] <= 1'b1;
end
else
begin
doing_write_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
end
if (bg_doing_write)
begin
doing_write_pipe_eq_afi_wlat_minus_3 [P] <= 1'b1;
end
else
begin
doing_write_pipe_eq_afi_wlat_minus_3 [P] <= 1'b0;
end
end
else
begin
if (doing_write_pipe[afi_wlat_minus_1 [P]])
begin
doing_write_pipe_eq_afi_wlat_minus_0 [P] <= 1'b1;
end
else
begin
doing_write_pipe_eq_afi_wlat_minus_0 [P] <= 1'b0;
end
if (doing_write_pipe[afi_wlat_minus_2 [P]])
begin
doing_write_pipe_eq_afi_wlat_minus_1 [P] <= 1'b1;
end
else
begin
doing_write_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
end
if (doing_write_pipe[afi_wlat_minus_3 [P]])
begin
doing_write_pipe_eq_afi_wlat_minus_2 [P] <= 1'b1;
end
else
begin
doing_write_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
end
if (doing_write_pipe[afi_wlat_minus_4 [P]])
begin
doing_write_pipe_eq_afi_wlat_minus_3 [P] <= 1'b1;
end
else
begin
doing_write_pipe_eq_afi_wlat_minus_3 [P] <= 1'b0;
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
rdwr_data_valid_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
rdwr_data_valid_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
rdwr_data_valid_pipe_eq_afi_wlat_minus_3 [P] <= 1'b0;
end
else
begin
if (current_afi_wlat == 0)
begin
rdwr_data_valid_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
rdwr_data_valid_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
rdwr_data_valid_pipe_eq_afi_wlat_minus_3 [P] <= 1'b0;
end
else if (current_afi_wlat == 1)
begin
if (bg_rdwr_data_valid)
begin
rdwr_data_valid_pipe_eq_afi_wlat_minus_1 [P] <= 1'b1;
end
else
begin
rdwr_data_valid_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
end
if (bg_rdwr_data_valid)
begin
rdwr_data_valid_pipe_eq_afi_wlat_minus_2 [P] <= 1'b1;
end
else
begin
rdwr_data_valid_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
end
if (bg_rdwr_data_valid)
begin
rdwr_data_valid_pipe_eq_afi_wlat_minus_3 [P] <= 1'b1;
end
else
begin
rdwr_data_valid_pipe_eq_afi_wlat_minus_3 [P] <= 1'b0;
end
end
else if (current_afi_wlat == 2)
begin
if (rdwr_data_valid_pipe[0])
begin
rdwr_data_valid_pipe_eq_afi_wlat_minus_1 [P] <= 1'b1;
end
else
begin
rdwr_data_valid_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
end
if (bg_rdwr_data_valid)
begin
rdwr_data_valid_pipe_eq_afi_wlat_minus_2 [P] <= 1'b1;
end
else
begin
rdwr_data_valid_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
end
if (bg_rdwr_data_valid)
begin
rdwr_data_valid_pipe_eq_afi_wlat_minus_3 [P] <= 1'b1;
end
else
begin
rdwr_data_valid_pipe_eq_afi_wlat_minus_3 [P] <= 1'b0;
end
end
else if (current_afi_wlat == 3)
begin
if (rdwr_data_valid_pipe[1])
begin
rdwr_data_valid_pipe_eq_afi_wlat_minus_1 [P] <= 1'b1;
end
else
begin
rdwr_data_valid_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
end
if (rdwr_data_valid_pipe[0])
begin
rdwr_data_valid_pipe_eq_afi_wlat_minus_2 [P] <= 1'b1;
end
else
begin
rdwr_data_valid_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
end
if (bg_rdwr_data_valid)
begin
rdwr_data_valid_pipe_eq_afi_wlat_minus_3 [P] <= 1'b1;
end
else
begin
rdwr_data_valid_pipe_eq_afi_wlat_minus_3 [P] <= 1'b0;
end
end
else
begin
if (rdwr_data_valid_pipe[afi_wlat_minus_2 [P]])
begin
rdwr_data_valid_pipe_eq_afi_wlat_minus_1 [P] <= 1'b1;
end
else
begin
rdwr_data_valid_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
end
if (rdwr_data_valid_pipe[afi_wlat_minus_3 [P]])
begin
rdwr_data_valid_pipe_eq_afi_wlat_minus_2 [P] <= 1'b1;
end
else
begin
rdwr_data_valid_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
end
if (rdwr_data_valid_pipe[afi_wlat_minus_4 [P]])
begin
rdwr_data_valid_pipe_eq_afi_wlat_minus_3 [P] <= 1'b1;
end
else
begin
rdwr_data_valid_pipe_eq_afi_wlat_minus_3 [P] <= 1'b0;
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
do_write_pipe_eq_afi_wlat_minus_0 [P] <= 1'b0;
do_write_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
do_write_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
end
else
begin
if (current_afi_wlat == 0)
begin
do_write_pipe_eq_afi_wlat_minus_0 [P] <= 1'b0;
do_write_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
do_write_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
end
else if (current_afi_wlat == 1)
begin
if (do_write_pipe[0])
begin
do_write_pipe_eq_afi_wlat_minus_0 [P] <= 1'b1;
end
else
begin
do_write_pipe_eq_afi_wlat_minus_0 [P] <= 1'b0;
end
if (|bg_do_write)
begin
do_write_pipe_eq_afi_wlat_minus_1 [P] <= 1'b1;
end
else
begin
do_write_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
end
if (|bg_do_write) // we must disable int_cfg_output_regd when (afi_wlat < 2)
begin
do_write_pipe_eq_afi_wlat_minus_2 [P] <= 1'b1;
end
else
begin
do_write_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
end
end
else if (current_afi_wlat == 2)
begin
if (do_write_pipe[1])
begin
do_write_pipe_eq_afi_wlat_minus_0 [P] <= 1'b1;
end
else
begin
do_write_pipe_eq_afi_wlat_minus_0 [P] <= 1'b0;
end
if (do_write_pipe[0])
begin
do_write_pipe_eq_afi_wlat_minus_1 [P] <= 1'b1;
end
else
begin
do_write_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
end
if (|bg_do_write)
begin
do_write_pipe_eq_afi_wlat_minus_2 [P] <= 1'b1;
end
else
begin
do_write_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
end
end
else
begin
if (do_write_pipe[afi_wlat_minus_1 [P]])
begin
do_write_pipe_eq_afi_wlat_minus_0 [P] <= 1'b1;
end
else
begin
do_write_pipe_eq_afi_wlat_minus_0 [P] <= 1'b0;
end
if (do_write_pipe[afi_wlat_minus_2 [P]])
begin
do_write_pipe_eq_afi_wlat_minus_1 [P] <= 1'b1;
end
else
begin
do_write_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
end
if (do_write_pipe[afi_wlat_minus_3 [P]])
begin
do_write_pipe_eq_afi_wlat_minus_2 [P] <= 1'b1;
end
else
begin
do_write_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
wr_chip_pipe_eq_afi_wlat_minus_0 [P] <= 0;
wr_chip_pipe_eq_afi_wlat_minus_1 [P] <= 0;
end
else
begin
if (current_afi_wlat == 0)
begin
wr_chip_pipe_eq_afi_wlat_minus_0 [P] <= int_to_chip;
wr_chip_pipe_eq_afi_wlat_minus_1 [P] <= 0;
end
else if (current_afi_wlat == 1)
begin
wr_chip_pipe_eq_afi_wlat_minus_0 [P] <= wr_chip_pipe [0];
wr_chip_pipe_eq_afi_wlat_minus_1 [P] <= int_to_chip;
end
else
begin
wr_chip_pipe_eq_afi_wlat_minus_0 [P] <= wr_chip_pipe [afi_wlat_minus_1 [P]];
wr_chip_pipe_eq_afi_wlat_minus_1 [P] <= wr_chip_pipe [afi_wlat_minus_2 [P]];
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
dataid_pipe_eq_afi_wlat_minus_1 [P] <= 0;
dataid_pipe_eq_afi_wlat_minus_2 [P] <= 0;
dataid_pipe_eq_afi_wlat_minus_3 [P] <= 0;
dataid_vector_pipe_eq_afi_wlat_minus_1 [P] <= 0;
dataid_vector_pipe_eq_afi_wlat_minus_2 [P] <= 0;
dataid_vector_pipe_eq_afi_wlat_minus_3 [P] <= 0;
end
else
begin
if (current_afi_wlat == 0)
begin
dataid_pipe_eq_afi_wlat_minus_1 [P] <= 0;
dataid_pipe_eq_afi_wlat_minus_2 [P] <= 0;
dataid_pipe_eq_afi_wlat_minus_3 [P] <= 0;
dataid_vector_pipe_eq_afi_wlat_minus_1 [P] <= 0;
dataid_vector_pipe_eq_afi_wlat_minus_2 [P] <= 0;
dataid_vector_pipe_eq_afi_wlat_minus_3 [P] <= 0;
end
else if (current_afi_wlat == 1)
begin
dataid_pipe_eq_afi_wlat_minus_1 [P] <= dataid;
dataid_pipe_eq_afi_wlat_minus_2 [P] <= dataid;
dataid_pipe_eq_afi_wlat_minus_3 [P] <= dataid;
dataid_vector_pipe_eq_afi_wlat_minus_1 [P] <= dataid_vector;
dataid_vector_pipe_eq_afi_wlat_minus_2 [P] <= dataid_vector;
dataid_vector_pipe_eq_afi_wlat_minus_3 [P] <= dataid_vector;
end
else if (current_afi_wlat == 2)
begin
dataid_pipe_eq_afi_wlat_minus_1 [P] <= dataid_pipe [0];
dataid_pipe_eq_afi_wlat_minus_2 [P] <= dataid;
dataid_pipe_eq_afi_wlat_minus_3 [P] <= dataid;
dataid_vector_pipe_eq_afi_wlat_minus_1 [P] <= dataid_vector_pipe[0];
dataid_vector_pipe_eq_afi_wlat_minus_2 [P] <= dataid_vector;
dataid_vector_pipe_eq_afi_wlat_minus_3 [P] <= dataid_vector;
end
else if (current_afi_wlat == 3)
begin
dataid_pipe_eq_afi_wlat_minus_1 [P] <= dataid_pipe [1];
dataid_pipe_eq_afi_wlat_minus_2 [P] <= dataid_pipe [0];
dataid_pipe_eq_afi_wlat_minus_3 [P] <= dataid;
dataid_vector_pipe_eq_afi_wlat_minus_1 [P] <= dataid_vector_pipe[1];
dataid_vector_pipe_eq_afi_wlat_minus_2 [P] <= dataid_vector_pipe[0];
dataid_vector_pipe_eq_afi_wlat_minus_3 [P] <= dataid_vector;
end
else
begin
dataid_pipe_eq_afi_wlat_minus_1 [P] <= dataid_pipe [afi_wlat_minus_2 [P]];
dataid_pipe_eq_afi_wlat_minus_2 [P] <= dataid_pipe [afi_wlat_minus_3 [P]];
dataid_pipe_eq_afi_wlat_minus_3 [P] <= dataid_pipe [afi_wlat_minus_4 [P]];
dataid_vector_pipe_eq_afi_wlat_minus_1 [P] <= dataid_vector_pipe[afi_wlat_minus_2 [P]];
dataid_vector_pipe_eq_afi_wlat_minus_2 [P] <= dataid_vector_pipe[afi_wlat_minus_3 [P]];
dataid_vector_pipe_eq_afi_wlat_minus_3 [P] <= dataid_vector_pipe[afi_wlat_minus_4 [P]];
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
rmw_correct_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
rmw_correct_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
rmw_correct_pipe_eq_afi_wlat_minus_3 [P] <= 1'b0;
rmw_partial_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
rmw_partial_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
rmw_partial_pipe_eq_afi_wlat_minus_3 [P] <= 1'b0;
end
else
begin
if (current_afi_wlat == 0)
begin
rmw_correct_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
rmw_correct_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
rmw_correct_pipe_eq_afi_wlat_minus_3 [P] <= 1'b0;
rmw_partial_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
rmw_partial_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
rmw_partial_pipe_eq_afi_wlat_minus_3 [P] <= 1'b0;
end
else if (current_afi_wlat == 1)
begin
if (int_do_rmw_correct)
begin
rmw_correct_pipe_eq_afi_wlat_minus_1 [P] <= 1'b1;
end
else
begin
rmw_correct_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
end
if (int_do_rmw_partial)
begin
rmw_partial_pipe_eq_afi_wlat_minus_1 [P] <= 1'b1;
end
else
begin
rmw_partial_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
end
if (int_do_rmw_correct)
begin
rmw_correct_pipe_eq_afi_wlat_minus_2 [P] <= 1'b1;
end
else
begin
rmw_correct_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
end
if (int_do_rmw_partial)
begin
rmw_partial_pipe_eq_afi_wlat_minus_2 [P] <= 1'b1;
end
else
begin
rmw_partial_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
end
if (int_do_rmw_correct)
begin
rmw_correct_pipe_eq_afi_wlat_minus_3 [P] <= 1'b1;
end
else
begin
rmw_correct_pipe_eq_afi_wlat_minus_3 [P] <= 1'b0;
end
if (int_do_rmw_partial)
begin
rmw_partial_pipe_eq_afi_wlat_minus_3 [P] <= 1'b1;
end
else
begin
rmw_partial_pipe_eq_afi_wlat_minus_3 [P] <= 1'b0;
end
end
else if (current_afi_wlat == 2)
begin
if (rmw_correct_pipe[0])
begin
rmw_correct_pipe_eq_afi_wlat_minus_1 [P] <= 1'b1;
end
else
begin
rmw_correct_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
end
if (rmw_partial_pipe[0])
begin
rmw_partial_pipe_eq_afi_wlat_minus_1 [P] <= 1'b1;
end
else
begin
rmw_partial_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
end
if (int_do_rmw_correct)
begin
rmw_correct_pipe_eq_afi_wlat_minus_2 [P] <= 1'b1;
end
else
begin
rmw_correct_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
end
if (int_do_rmw_partial)
begin
rmw_partial_pipe_eq_afi_wlat_minus_2 [P] <= 1'b1;
end
else
begin
rmw_partial_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
end
if (int_do_rmw_correct)
begin
rmw_correct_pipe_eq_afi_wlat_minus_3 [P] <= 1'b1;
end
else
begin
rmw_correct_pipe_eq_afi_wlat_minus_3 [P] <= 1'b0;
end
if (int_do_rmw_partial)
begin
rmw_partial_pipe_eq_afi_wlat_minus_3 [P] <= 1'b1;
end
else
begin
rmw_partial_pipe_eq_afi_wlat_minus_3 [P] <= 1'b0;
end
end
else if (current_afi_wlat == 3)
begin
if (rmw_correct_pipe[1])
begin
rmw_correct_pipe_eq_afi_wlat_minus_1 [P] <= 1'b1;
end
else
begin
rmw_correct_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
end
if (rmw_partial_pipe[1])
begin
rmw_partial_pipe_eq_afi_wlat_minus_1 [P] <= 1'b1;
end
else
begin
rmw_partial_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
end
if (rmw_correct_pipe[0])
begin
rmw_correct_pipe_eq_afi_wlat_minus_2 [P] <= 1'b1;
end
else
begin
rmw_correct_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
end
if (rmw_partial_pipe[0])
begin
rmw_partial_pipe_eq_afi_wlat_minus_2 [P] <= 1'b1;
end
else
begin
rmw_partial_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
end
if (int_do_rmw_correct)
begin
rmw_correct_pipe_eq_afi_wlat_minus_3 [P] <= 1'b1;
end
else
begin
rmw_correct_pipe_eq_afi_wlat_minus_3 [P] <= 1'b0;
end
if (int_do_rmw_partial)
begin
rmw_partial_pipe_eq_afi_wlat_minus_3 [P] <= 1'b1;
end
else
begin
rmw_partial_pipe_eq_afi_wlat_minus_3 [P] <= 1'b0;
end
end
else
begin
if (rmw_correct_pipe[afi_wlat_minus_2 [P]])
begin
rmw_correct_pipe_eq_afi_wlat_minus_1 [P] <= 1'b1;
end
else
begin
rmw_correct_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
end
if (rmw_partial_pipe[afi_wlat_minus_2 [P]])
begin
rmw_partial_pipe_eq_afi_wlat_minus_1 [P] <= 1'b1;
end
else
begin
rmw_partial_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
end
if (rmw_correct_pipe[afi_wlat_minus_3 [P]])
begin
rmw_correct_pipe_eq_afi_wlat_minus_2 [P] <= 1'b1;
end
else
begin
rmw_correct_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
end
if (rmw_partial_pipe[afi_wlat_minus_3 [P]])
begin
rmw_partial_pipe_eq_afi_wlat_minus_2 [P] <= 1'b1;
end
else
begin
rmw_partial_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
end
if (rmw_correct_pipe[afi_wlat_minus_4 [P]])
begin
rmw_correct_pipe_eq_afi_wlat_minus_3 [P] <= 1'b1;
end
else
begin
rmw_correct_pipe_eq_afi_wlat_minus_3 [P] <= 1'b0;
end
if (rmw_partial_pipe[afi_wlat_minus_4 [P]])
begin
rmw_partial_pipe_eq_afi_wlat_minus_3 [P] <= 1'b1;
end
else
begin
rmw_partial_pipe_eq_afi_wlat_minus_3 [P] <= 1'b0;
end
end
end
end
always @ (*)
begin
if (CFG_WDATA_REG && CFG_ECC_ENC_REG)
begin
doing_write_pipe_eq_afi_wlat_minus_x [P] = doing_write_pipe_eq_afi_wlat_minus_3 [P];
rdwr_data_valid_pipe_eq_afi_wlat_minus_x [P] = rdwr_data_valid_pipe_eq_afi_wlat_minus_3 [P];
dataid_pipe_eq_afi_wlat_minus_x [P] = dataid_pipe_eq_afi_wlat_minus_3 [P];
dataid_vector_pipe_eq_afi_wlat_minus_x [P] = dataid_vector_pipe_eq_afi_wlat_minus_3 [P];
rmw_correct_pipe_eq_afi_wlat_minus_x [P] = rmw_correct_pipe_eq_afi_wlat_minus_3 [P];
rmw_partial_pipe_eq_afi_wlat_minus_x [P] = rmw_partial_pipe_eq_afi_wlat_minus_3 [P];
end
else if (CFG_WDATA_REG || CFG_ECC_ENC_REG)
begin
doing_write_pipe_eq_afi_wlat_minus_x [P] = doing_write_pipe_eq_afi_wlat_minus_2 [P];
rdwr_data_valid_pipe_eq_afi_wlat_minus_x [P] = rdwr_data_valid_pipe_eq_afi_wlat_minus_2 [P];
dataid_pipe_eq_afi_wlat_minus_x [P] = dataid_pipe_eq_afi_wlat_minus_2 [P];
dataid_vector_pipe_eq_afi_wlat_minus_x [P] = dataid_vector_pipe_eq_afi_wlat_minus_2 [P];
rmw_correct_pipe_eq_afi_wlat_minus_x [P] = rmw_correct_pipe_eq_afi_wlat_minus_2 [P];
rmw_partial_pipe_eq_afi_wlat_minus_x [P] = rmw_partial_pipe_eq_afi_wlat_minus_2 [P];
end
else
begin
doing_write_pipe_eq_afi_wlat_minus_x [P] = doing_write_pipe_eq_afi_wlat_minus_1 [P];
rdwr_data_valid_pipe_eq_afi_wlat_minus_x [P] = rdwr_data_valid_pipe_eq_afi_wlat_minus_1 [P];
dataid_pipe_eq_afi_wlat_minus_x [P] = dataid_pipe_eq_afi_wlat_minus_1 [P];
dataid_vector_pipe_eq_afi_wlat_minus_x [P] = dataid_vector_pipe_eq_afi_wlat_minus_1 [P];
rmw_correct_pipe_eq_afi_wlat_minus_x [P] = rmw_correct_pipe_eq_afi_wlat_minus_1 [P];
rmw_partial_pipe_eq_afi_wlat_minus_x [P] = rmw_partial_pipe_eq_afi_wlat_minus_1 [P];
end
end
// First vector
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
ecc_wdata_fifo_first_vector [P] <= 1'b0;
end
else
begin
if (current_afi_wlat == smallest_afi_wlat [CFG_DRAM_WLAT_GROUP - 1])
begin
ecc_wdata_fifo_first_vector [P] <= 1'b1;
end
else
begin
ecc_wdata_fifo_first_vector [P] <= 1'b0;
end
end
end
end
for (P = 1;P < CFG_DRAM_WLAT_GROUP;P = P + 1)
begin : afi_wlat_info_logic
// afi_wlat for current DQS group
wire [(CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP) - 1 : 0] current_afi_wlat = afi_wlat [(P + 1) * (CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP) - 1 : P * (CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP)];
// Smallest/largest afi_wlat logic
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
smallest_afi_wlat [P] <= 0;
largest_afi_wlat [P] <= 0;
end
else
begin
if (current_afi_wlat < smallest_afi_wlat [P-1])
begin
smallest_afi_wlat [P] <= current_afi_wlat;
end
else
begin
smallest_afi_wlat [P] <= smallest_afi_wlat [P-1];
end
if (current_afi_wlat > largest_afi_wlat [P-1])
begin
largest_afi_wlat [P] <= current_afi_wlat;
end
else
begin
largest_afi_wlat [P] <= largest_afi_wlat [P-1];
end
end
end
end
endgenerate
// Smallest/largest afi_wlat logic
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
smallest_afi_wlat [0] <= 0;
largest_afi_wlat [0] <= 0;
end
else
begin
smallest_afi_wlat [0] <= afi_wlat [(CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP) - 1 : 0];
largest_afi_wlat [0] <= afi_wlat [(CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP) - 1 : 0];
end
end
generate
if (CFG_DRAM_WLAT_GROUP == 1) // only one group of afi_wlat
begin
always @ (*)
begin
smallest_afi_wlat_eq_0 = afi_wlat_eq_0 [0];
smallest_afi_wlat_minus_1 = afi_wlat_minus_1 [0];
smallest_afi_wlat_minus_2 = afi_wlat_minus_2 [0];
smallest_afi_wlat_minus_3 = afi_wlat_minus_3 [0];
smallest_afi_wlat_minus_4 = afi_wlat_minus_4 [0];
smallest_doing_write_pipe_eq_afi_wlat_minus_0 = doing_write_pipe_eq_afi_wlat_minus_0 [0];
smallest_doing_write_pipe_eq_afi_wlat_minus_1 = doing_write_pipe_eq_afi_wlat_minus_1 [0];
smallest_doing_write_pipe_eq_afi_wlat_minus_2 = doing_write_pipe_eq_afi_wlat_minus_2 [0];
smallest_doing_write_pipe_eq_afi_wlat_minus_3 = doing_write_pipe_eq_afi_wlat_minus_3 [0];
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 = rdwr_data_valid_pipe_eq_afi_wlat_minus_1 [0];
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 = rdwr_data_valid_pipe_eq_afi_wlat_minus_2 [0];
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_3 = rdwr_data_valid_pipe_eq_afi_wlat_minus_3 [0];
smallest_dataid_pipe_eq_afi_wlat_minus_1 = dataid_pipe_eq_afi_wlat_minus_1 [0];
smallest_dataid_pipe_eq_afi_wlat_minus_2 = dataid_pipe_eq_afi_wlat_minus_2 [0];
smallest_dataid_pipe_eq_afi_wlat_minus_3 = dataid_pipe_eq_afi_wlat_minus_3 [0];
smallest_dataid_vector_pipe_eq_afi_wlat_minus_1 = dataid_vector_pipe_eq_afi_wlat_minus_1 [0];
smallest_dataid_vector_pipe_eq_afi_wlat_minus_2 = dataid_vector_pipe_eq_afi_wlat_minus_2 [0];
smallest_dataid_vector_pipe_eq_afi_wlat_minus_3 = dataid_vector_pipe_eq_afi_wlat_minus_3 [0];
smallest_rmw_correct_pipe_eq_afi_wlat_minus_1 = rmw_correct_pipe_eq_afi_wlat_minus_1 [0];
smallest_rmw_correct_pipe_eq_afi_wlat_minus_2 = rmw_correct_pipe_eq_afi_wlat_minus_2 [0];
smallest_rmw_correct_pipe_eq_afi_wlat_minus_3 = rmw_correct_pipe_eq_afi_wlat_minus_3 [0];
smallest_rmw_partial_pipe_eq_afi_wlat_minus_1 = rmw_partial_pipe_eq_afi_wlat_minus_1 [0];
smallest_rmw_partial_pipe_eq_afi_wlat_minus_2 = rmw_partial_pipe_eq_afi_wlat_minus_2 [0];
smallest_rmw_partial_pipe_eq_afi_wlat_minus_3 = rmw_partial_pipe_eq_afi_wlat_minus_3 [0];
smallest_doing_write_pipe_eq_afi_wlat_minus_x = doing_write_pipe_eq_afi_wlat_minus_x [0];
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_x = rdwr_data_valid_pipe_eq_afi_wlat_minus_x [0];
smallest_dataid_pipe_eq_afi_wlat_minus_x = dataid_pipe_eq_afi_wlat_minus_x [0];
smallest_dataid_vector_pipe_eq_afi_wlat_minus_x = dataid_vector_pipe_eq_afi_wlat_minus_x [0];
smallest_rmw_correct_pipe_eq_afi_wlat_minus_x = rmw_correct_pipe_eq_afi_wlat_minus_x [0];
smallest_rmw_partial_pipe_eq_afi_wlat_minus_x = rmw_partial_pipe_eq_afi_wlat_minus_x [0];
largest_afi_wlat_eq_0 = afi_wlat_eq_0 [0];
largest_afi_wlat_minus_1 = afi_wlat_minus_1 [0];
largest_afi_wlat_minus_2 = afi_wlat_minus_2 [0];
largest_afi_wlat_minus_3 = afi_wlat_minus_3 [0];
largest_afi_wlat_minus_4 = afi_wlat_minus_4 [0];
largest_doing_write_pipe_eq_afi_wlat_minus_0 = doing_write_pipe_eq_afi_wlat_minus_0 [0];
largest_doing_write_pipe_eq_afi_wlat_minus_1 = doing_write_pipe_eq_afi_wlat_minus_1 [0];
largest_doing_write_pipe_eq_afi_wlat_minus_2 = doing_write_pipe_eq_afi_wlat_minus_2 [0];
largest_doing_write_pipe_eq_afi_wlat_minus_3 = doing_write_pipe_eq_afi_wlat_minus_3 [0];
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 = rdwr_data_valid_pipe_eq_afi_wlat_minus_1 [0];
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 = rdwr_data_valid_pipe_eq_afi_wlat_minus_2 [0];
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_3 = rdwr_data_valid_pipe_eq_afi_wlat_minus_3 [0];
largest_dataid_pipe_eq_afi_wlat_minus_1 = dataid_pipe_eq_afi_wlat_minus_1 [0];
largest_dataid_pipe_eq_afi_wlat_minus_2 = dataid_pipe_eq_afi_wlat_minus_2 [0];
largest_dataid_pipe_eq_afi_wlat_minus_3 = dataid_pipe_eq_afi_wlat_minus_3 [0];
largest_dataid_vector_pipe_eq_afi_wlat_minus_1 = dataid_vector_pipe_eq_afi_wlat_minus_1 [0];
largest_dataid_vector_pipe_eq_afi_wlat_minus_2 = dataid_vector_pipe_eq_afi_wlat_minus_2 [0];
largest_dataid_vector_pipe_eq_afi_wlat_minus_3 = dataid_vector_pipe_eq_afi_wlat_minus_3 [0];
largest_rmw_correct_pipe_eq_afi_wlat_minus_1 = rmw_correct_pipe_eq_afi_wlat_minus_1 [0];
largest_rmw_correct_pipe_eq_afi_wlat_minus_2 = rmw_correct_pipe_eq_afi_wlat_minus_2 [0];
largest_rmw_correct_pipe_eq_afi_wlat_minus_3 = rmw_correct_pipe_eq_afi_wlat_minus_3 [0];
largest_rmw_partial_pipe_eq_afi_wlat_minus_1 = rmw_partial_pipe_eq_afi_wlat_minus_1 [0];
largest_rmw_partial_pipe_eq_afi_wlat_minus_2 = rmw_partial_pipe_eq_afi_wlat_minus_2 [0];
largest_rmw_partial_pipe_eq_afi_wlat_minus_3 = rmw_partial_pipe_eq_afi_wlat_minus_3 [0];
largest_doing_write_pipe_eq_afi_wlat_minus_x = doing_write_pipe_eq_afi_wlat_minus_x [0];
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_x = rdwr_data_valid_pipe_eq_afi_wlat_minus_x [0];
largest_dataid_pipe_eq_afi_wlat_minus_x = dataid_pipe_eq_afi_wlat_minus_x [0];
largest_dataid_vector_pipe_eq_afi_wlat_minus_x = dataid_vector_pipe_eq_afi_wlat_minus_x [0];
largest_rmw_correct_pipe_eq_afi_wlat_minus_x = rmw_correct_pipe_eq_afi_wlat_minus_x [0];
largest_rmw_partial_pipe_eq_afi_wlat_minus_x = rmw_partial_pipe_eq_afi_wlat_minus_x [0];
end
end
else
begin
// Pre-calculated logic for smallest/largest afi_wlat (for afi addr/cmd logic)
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
smallest_afi_wlat_eq_0 <= 1'b0;
smallest_afi_wlat_minus_1 <= {(CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP){1'b0}};
smallest_afi_wlat_minus_2 <= {(CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP){1'b0}};
smallest_afi_wlat_minus_3 <= {(CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP){1'b0}};
smallest_afi_wlat_minus_4 <= {(CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP){1'b0}};
end
else
begin
if (smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 0)
begin
smallest_afi_wlat_eq_0 <= 1'b1;
end
else
begin
smallest_afi_wlat_eq_0 <= 1'b0;
end
smallest_afi_wlat_minus_1 <= smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] - 1;
smallest_afi_wlat_minus_2 <= smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] - 2;
smallest_afi_wlat_minus_3 <= smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] - 3;
smallest_afi_wlat_minus_4 <= smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] - 4;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_0 <= 1'b0;
smallest_doing_write_pipe_eq_afi_wlat_minus_1 <= 1'b0;
smallest_doing_write_pipe_eq_afi_wlat_minus_2 <= 1'b0;
smallest_doing_write_pipe_eq_afi_wlat_minus_3 <= 1'b0;
end
else
begin
if (smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 0)
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_0 <= 1'b0;
smallest_doing_write_pipe_eq_afi_wlat_minus_1 <= 1'b0;
smallest_doing_write_pipe_eq_afi_wlat_minus_2 <= 1'b0;
smallest_doing_write_pipe_eq_afi_wlat_minus_3 <= 1'b0;
end
else if (smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 1)
begin
if (doing_write_pipe[0])
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_0 <= 1'b1;
end
else
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_0 <= 1'b0;
end
if (bg_doing_write)
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (bg_doing_write)
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
if (bg_doing_write)
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_3 <= 1'b1;
end
else
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_3 <= 1'b0;
end
end
else if (smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 2)
begin
if (doing_write_pipe[1])
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_0 <= 1'b1;
end
else
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_0 <= 1'b0;
end
if (doing_write_pipe[0])
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (bg_doing_write)
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
if (bg_doing_write)
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_3 <= 1'b1;
end
else
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_3 <= 1'b0;
end
end
else if (smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 3)
begin
if (doing_write_pipe[2])
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_0 <= 1'b1;
end
else
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_0 <= 1'b0;
end
if (doing_write_pipe[1])
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (doing_write_pipe[0])
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
if (bg_doing_write)
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_3 <= 1'b1;
end
else
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_3 <= 1'b0;
end
end
else
begin
if (doing_write_pipe[smallest_afi_wlat_minus_1])
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_0 <= 1'b1;
end
else
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_0 <= 1'b0;
end
if (doing_write_pipe[smallest_afi_wlat_minus_2])
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (doing_write_pipe[smallest_afi_wlat_minus_3])
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
if (doing_write_pipe[smallest_afi_wlat_minus_4])
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_3 <= 1'b1;
end
else
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_3 <= 1'b0;
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b0;
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b0;
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_3 <= 1'b0;
end
else
begin
if (smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 0)
begin
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b0;
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b0;
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_3 <= 1'b0;
end
else if (smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 1)
begin
if (bg_rdwr_data_valid)
begin
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (bg_rdwr_data_valid)
begin
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
if (bg_rdwr_data_valid)
begin
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_3 <= 1'b1;
end
else
begin
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_3 <= 1'b0;
end
end
else if (smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 2)
begin
if (rdwr_data_valid_pipe[0])
begin
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (bg_rdwr_data_valid)
begin
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
if (bg_rdwr_data_valid)
begin
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_3 <= 1'b1;
end
else
begin
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_3 <= 1'b0;
end
end
else if (smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 3)
begin
if (rdwr_data_valid_pipe[1])
begin
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (rdwr_data_valid_pipe[0])
begin
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
if (bg_rdwr_data_valid)
begin
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_3 <= 1'b1;
end
else
begin
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_3 <= 1'b0;
end
end
else
begin
if (rdwr_data_valid_pipe[smallest_afi_wlat_minus_2])
begin
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (rdwr_data_valid_pipe[smallest_afi_wlat_minus_3])
begin
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
if (rdwr_data_valid_pipe[smallest_afi_wlat_minus_4])
begin
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_3 <= 1'b1;
end
else
begin
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_3 <= 1'b0;
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
smallest_dataid_pipe_eq_afi_wlat_minus_1 <= 0;
smallest_dataid_pipe_eq_afi_wlat_minus_2 <= 0;
smallest_dataid_pipe_eq_afi_wlat_minus_3 <= 0;
smallest_dataid_vector_pipe_eq_afi_wlat_minus_1 <= 0;
smallest_dataid_vector_pipe_eq_afi_wlat_minus_2 <= 0;
smallest_dataid_vector_pipe_eq_afi_wlat_minus_3 <= 0;
end
else
begin
if (smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 0)
begin
smallest_dataid_pipe_eq_afi_wlat_minus_1 <= 0;
smallest_dataid_pipe_eq_afi_wlat_minus_2 <= 0;
smallest_dataid_pipe_eq_afi_wlat_minus_3 <= 0;
smallest_dataid_vector_pipe_eq_afi_wlat_minus_1 <= 0;
smallest_dataid_vector_pipe_eq_afi_wlat_minus_2 <= 0;
smallest_dataid_vector_pipe_eq_afi_wlat_minus_3 <= 0;
end
else if (smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 1)
begin
smallest_dataid_pipe_eq_afi_wlat_minus_1 <= dataid;
smallest_dataid_pipe_eq_afi_wlat_minus_2 <= dataid;
smallest_dataid_pipe_eq_afi_wlat_minus_3 <= dataid;
smallest_dataid_vector_pipe_eq_afi_wlat_minus_1 <= dataid_vector;
smallest_dataid_vector_pipe_eq_afi_wlat_minus_2 <= dataid_vector;
smallest_dataid_vector_pipe_eq_afi_wlat_minus_3 <= dataid_vector;
end
else if (smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 2)
begin
smallest_dataid_pipe_eq_afi_wlat_minus_1 <= dataid_pipe [0];
smallest_dataid_pipe_eq_afi_wlat_minus_2 <= dataid;
smallest_dataid_pipe_eq_afi_wlat_minus_3 <= dataid;
smallest_dataid_vector_pipe_eq_afi_wlat_minus_1 <= dataid_vector_pipe[0];
smallest_dataid_vector_pipe_eq_afi_wlat_minus_2 <= dataid_vector;
smallest_dataid_vector_pipe_eq_afi_wlat_minus_3 <= dataid_vector;
end
else if (smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 3)
begin
smallest_dataid_pipe_eq_afi_wlat_minus_1 <= dataid_pipe [1];
smallest_dataid_pipe_eq_afi_wlat_minus_2 <= dataid_pipe [0];
smallest_dataid_pipe_eq_afi_wlat_minus_3 <= dataid;
smallest_dataid_vector_pipe_eq_afi_wlat_minus_1 <= dataid_vector_pipe[1];
smallest_dataid_vector_pipe_eq_afi_wlat_minus_2 <= dataid_vector_pipe[0];
smallest_dataid_vector_pipe_eq_afi_wlat_minus_3 <= dataid_vector;
end
else
begin
smallest_dataid_pipe_eq_afi_wlat_minus_1 <= dataid_pipe [smallest_afi_wlat_minus_2];
smallest_dataid_pipe_eq_afi_wlat_minus_2 <= dataid_pipe [smallest_afi_wlat_minus_3];
smallest_dataid_pipe_eq_afi_wlat_minus_3 <= dataid_pipe [smallest_afi_wlat_minus_4];
smallest_dataid_vector_pipe_eq_afi_wlat_minus_1 <= dataid_vector_pipe[smallest_afi_wlat_minus_2];
smallest_dataid_vector_pipe_eq_afi_wlat_minus_2 <= dataid_vector_pipe[smallest_afi_wlat_minus_3];
smallest_dataid_vector_pipe_eq_afi_wlat_minus_3 <= dataid_vector_pipe[smallest_afi_wlat_minus_4];
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
smallest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b0;
smallest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b0;
smallest_rmw_correct_pipe_eq_afi_wlat_minus_3 <= 1'b0;
smallest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b0;
smallest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b0;
smallest_rmw_partial_pipe_eq_afi_wlat_minus_3 <= 1'b0;
end
else
begin
if (smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 0)
begin
smallest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b0;
smallest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b0;
smallest_rmw_correct_pipe_eq_afi_wlat_minus_3 <= 1'b0;
smallest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b0;
smallest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b0;
smallest_rmw_partial_pipe_eq_afi_wlat_minus_3 <= 1'b0;
end
else if (smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 1)
begin
if (int_do_rmw_correct)
begin
smallest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
smallest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (int_do_rmw_partial)
begin
smallest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
smallest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (int_do_rmw_correct)
begin
smallest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
smallest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
if (int_do_rmw_partial)
begin
smallest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
smallest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
if (int_do_rmw_correct)
begin
smallest_rmw_correct_pipe_eq_afi_wlat_minus_3 <= 1'b1;
end
else
begin
smallest_rmw_correct_pipe_eq_afi_wlat_minus_3 <= 1'b0;
end
if (int_do_rmw_partial)
begin
smallest_rmw_partial_pipe_eq_afi_wlat_minus_3 <= 1'b1;
end
else
begin
smallest_rmw_partial_pipe_eq_afi_wlat_minus_3 <= 1'b0;
end
end
else if (smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 2)
begin
if (rmw_correct_pipe[0])
begin
smallest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
smallest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (rmw_partial_pipe[0])
begin
smallest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
smallest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (int_do_rmw_correct)
begin
smallest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
smallest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
if (int_do_rmw_partial)
begin
smallest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
smallest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
if (int_do_rmw_correct)
begin
smallest_rmw_correct_pipe_eq_afi_wlat_minus_3 <= 1'b1;
end
else
begin
smallest_rmw_correct_pipe_eq_afi_wlat_minus_3 <= 1'b0;
end
if (int_do_rmw_partial)
begin
smallest_rmw_partial_pipe_eq_afi_wlat_minus_3 <= 1'b1;
end
else
begin
smallest_rmw_partial_pipe_eq_afi_wlat_minus_3 <= 1'b0;
end
end
else if (smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 3)
begin
if (rmw_correct_pipe[1])
begin
smallest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
smallest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (rmw_partial_pipe[1])
begin
smallest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
smallest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (rmw_correct_pipe[0])
begin
smallest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
smallest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
if (rmw_partial_pipe[0])
begin
smallest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
smallest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
if (int_do_rmw_correct)
begin
smallest_rmw_correct_pipe_eq_afi_wlat_minus_3 <= 1'b1;
end
else
begin
smallest_rmw_correct_pipe_eq_afi_wlat_minus_3 <= 1'b0;
end
if (int_do_rmw_partial)
begin
smallest_rmw_partial_pipe_eq_afi_wlat_minus_3 <= 1'b1;
end
else
begin
smallest_rmw_partial_pipe_eq_afi_wlat_minus_3 <= 1'b0;
end
end
else
begin
if (rmw_correct_pipe[smallest_afi_wlat_minus_2])
begin
smallest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
smallest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (rmw_partial_pipe[smallest_afi_wlat_minus_2])
begin
smallest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
smallest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (rmw_correct_pipe[smallest_afi_wlat_minus_3])
begin
smallest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
smallest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
if (rmw_partial_pipe[smallest_afi_wlat_minus_3])
begin
smallest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
smallest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
if (rmw_correct_pipe[smallest_afi_wlat_minus_4])
begin
smallest_rmw_correct_pipe_eq_afi_wlat_minus_3 <= 1'b1;
end
else
begin
smallest_rmw_correct_pipe_eq_afi_wlat_minus_3 <= 1'b0;
end
if (rmw_partial_pipe[smallest_afi_wlat_minus_4])
begin
smallest_rmw_partial_pipe_eq_afi_wlat_minus_3 <= 1'b1;
end
else
begin
smallest_rmw_partial_pipe_eq_afi_wlat_minus_3 <= 1'b0;
end
end
end
end
always @ (*)
begin
if (CFG_WDATA_REG && CFG_ECC_ENC_REG)
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_x = smallest_doing_write_pipe_eq_afi_wlat_minus_3 ;
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_x = smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_3;
smallest_dataid_pipe_eq_afi_wlat_minus_x = smallest_dataid_pipe_eq_afi_wlat_minus_3 ;
smallest_dataid_vector_pipe_eq_afi_wlat_minus_x = smallest_dataid_vector_pipe_eq_afi_wlat_minus_3 ;
smallest_rmw_correct_pipe_eq_afi_wlat_minus_x = smallest_rmw_correct_pipe_eq_afi_wlat_minus_3 ;
smallest_rmw_partial_pipe_eq_afi_wlat_minus_x = smallest_rmw_partial_pipe_eq_afi_wlat_minus_3 ;
end
else if (CFG_WDATA_REG || CFG_ECC_ENC_REG)
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_x = smallest_doing_write_pipe_eq_afi_wlat_minus_2 ;
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_x = smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2;
smallest_dataid_pipe_eq_afi_wlat_minus_x = smallest_dataid_pipe_eq_afi_wlat_minus_2 ;
smallest_dataid_vector_pipe_eq_afi_wlat_minus_x = smallest_dataid_vector_pipe_eq_afi_wlat_minus_2 ;
smallest_rmw_correct_pipe_eq_afi_wlat_minus_x = smallest_rmw_correct_pipe_eq_afi_wlat_minus_2 ;
smallest_rmw_partial_pipe_eq_afi_wlat_minus_x = smallest_rmw_partial_pipe_eq_afi_wlat_minus_2 ;
end
else
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_x = smallest_doing_write_pipe_eq_afi_wlat_minus_1 ;
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_x = smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1;
smallest_dataid_pipe_eq_afi_wlat_minus_x = smallest_dataid_pipe_eq_afi_wlat_minus_1 ;
smallest_dataid_vector_pipe_eq_afi_wlat_minus_x = smallest_dataid_vector_pipe_eq_afi_wlat_minus_1 ;
smallest_rmw_correct_pipe_eq_afi_wlat_minus_x = smallest_rmw_correct_pipe_eq_afi_wlat_minus_1 ;
smallest_rmw_partial_pipe_eq_afi_wlat_minus_x = smallest_rmw_partial_pipe_eq_afi_wlat_minus_1 ;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
largest_afi_wlat_eq_0 <= 1'b0;
largest_afi_wlat_minus_1 <= {(CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP){1'b0}};
largest_afi_wlat_minus_2 <= {(CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP){1'b0}};
largest_afi_wlat_minus_3 <= {(CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP){1'b0}};
largest_afi_wlat_minus_4 <= {(CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP){1'b0}};
end
else
begin
if (largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 0)
begin
largest_afi_wlat_eq_0 <= 1'b1;
end
else
begin
largest_afi_wlat_eq_0 <= 1'b0;
end
largest_afi_wlat_minus_1 <= largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] - 1;
largest_afi_wlat_minus_2 <= largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] - 2;
largest_afi_wlat_minus_3 <= largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] - 3;
largest_afi_wlat_minus_4 <= largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] - 4;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
largest_doing_write_pipe_eq_afi_wlat_minus_0 <= 1'b0;
largest_doing_write_pipe_eq_afi_wlat_minus_1 <= 1'b0;
largest_doing_write_pipe_eq_afi_wlat_minus_2 <= 1'b0;
largest_doing_write_pipe_eq_afi_wlat_minus_3 <= 1'b0;
end
else
begin
if (largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 0)
begin
largest_doing_write_pipe_eq_afi_wlat_minus_0 <= 1'b0;
largest_doing_write_pipe_eq_afi_wlat_minus_1 <= 1'b0;
largest_doing_write_pipe_eq_afi_wlat_minus_2 <= 1'b0;
largest_doing_write_pipe_eq_afi_wlat_minus_3 <= 1'b0;
end
else if (largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 1)
begin
if (doing_write_pipe[0])
begin
largest_doing_write_pipe_eq_afi_wlat_minus_0 <= 1'b1;
end
else
begin
largest_doing_write_pipe_eq_afi_wlat_minus_0 <= 1'b0;
end
if (bg_doing_write)
begin
largest_doing_write_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
largest_doing_write_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (bg_doing_write)
begin
largest_doing_write_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
largest_doing_write_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
if (bg_doing_write)
begin
largest_doing_write_pipe_eq_afi_wlat_minus_3 <= 1'b1;
end
else
begin
largest_doing_write_pipe_eq_afi_wlat_minus_3 <= 1'b0;
end
end
else if (largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 2)
begin
if (doing_write_pipe[1])
begin
largest_doing_write_pipe_eq_afi_wlat_minus_0 <= 1'b1;
end
else
begin
largest_doing_write_pipe_eq_afi_wlat_minus_0 <= 1'b0;
end
if (doing_write_pipe[0])
begin
largest_doing_write_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
largest_doing_write_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (bg_doing_write)
begin
largest_doing_write_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
largest_doing_write_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
if (bg_doing_write)
begin
largest_doing_write_pipe_eq_afi_wlat_minus_3 <= 1'b1;
end
else
begin
largest_doing_write_pipe_eq_afi_wlat_minus_3 <= 1'b0;
end
end
else if (largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 3)
begin
if (doing_write_pipe[2])
begin
largest_doing_write_pipe_eq_afi_wlat_minus_0 <= 1'b1;
end
else
begin
largest_doing_write_pipe_eq_afi_wlat_minus_0 <= 1'b0;
end
if (doing_write_pipe[1])
begin
largest_doing_write_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
largest_doing_write_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (doing_write_pipe[0])
begin
largest_doing_write_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
largest_doing_write_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
if (bg_doing_write)
begin
largest_doing_write_pipe_eq_afi_wlat_minus_3 <= 1'b1;
end
else
begin
largest_doing_write_pipe_eq_afi_wlat_minus_3 <= 1'b0;
end
end
else
begin
if (doing_write_pipe[largest_afi_wlat_minus_1])
begin
largest_doing_write_pipe_eq_afi_wlat_minus_0 <= 1'b1;
end
else
begin
largest_doing_write_pipe_eq_afi_wlat_minus_0 <= 1'b0;
end
if (doing_write_pipe[largest_afi_wlat_minus_2])
begin
largest_doing_write_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
largest_doing_write_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (doing_write_pipe[largest_afi_wlat_minus_3])
begin
largest_doing_write_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
largest_doing_write_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
if (doing_write_pipe[largest_afi_wlat_minus_4])
begin
largest_doing_write_pipe_eq_afi_wlat_minus_3 <= 1'b1;
end
else
begin
largest_doing_write_pipe_eq_afi_wlat_minus_3 <= 1'b0;
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b0;
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b0;
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_3 <= 1'b0;
end
else
begin
if (largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 0)
begin
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b0;
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b0;
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_3 <= 1'b0;
end
else if (largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 1)
begin
if (bg_rdwr_data_valid)
begin
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (bg_rdwr_data_valid)
begin
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
if (bg_rdwr_data_valid)
begin
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_3 <= 1'b1;
end
else
begin
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_3 <= 1'b0;
end
end
else if (largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 2)
begin
if (rdwr_data_valid_pipe[0])
begin
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (bg_rdwr_data_valid)
begin
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
if (bg_rdwr_data_valid)
begin
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_3 <= 1'b1;
end
else
begin
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_3 <= 1'b0;
end
end
else if (largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 3)
begin
if (rdwr_data_valid_pipe[1])
begin
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (rdwr_data_valid_pipe[0])
begin
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
if (bg_rdwr_data_valid)
begin
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_3 <= 1'b1;
end
else
begin
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_3 <= 1'b0;
end
end
else
begin
if (rdwr_data_valid_pipe[largest_afi_wlat_minus_2])
begin
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (rdwr_data_valid_pipe[largest_afi_wlat_minus_3])
begin
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
if (rdwr_data_valid_pipe[largest_afi_wlat_minus_4])
begin
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_3 <= 1'b1;
end
else
begin
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_3 <= 1'b0;
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
largest_dataid_pipe_eq_afi_wlat_minus_1 <= 0;
largest_dataid_pipe_eq_afi_wlat_minus_2 <= 0;
largest_dataid_pipe_eq_afi_wlat_minus_3 <= 0;
largest_dataid_vector_pipe_eq_afi_wlat_minus_1 <= 0;
largest_dataid_vector_pipe_eq_afi_wlat_minus_2 <= 0;
largest_dataid_vector_pipe_eq_afi_wlat_minus_3 <= 0;
end
else
begin
if (largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 0)
begin
largest_dataid_pipe_eq_afi_wlat_minus_1 <= 0;
largest_dataid_pipe_eq_afi_wlat_minus_2 <= 0;
largest_dataid_pipe_eq_afi_wlat_minus_3 <= 0;
largest_dataid_vector_pipe_eq_afi_wlat_minus_1 <= 0;
largest_dataid_vector_pipe_eq_afi_wlat_minus_2 <= 0;
largest_dataid_vector_pipe_eq_afi_wlat_minus_3 <= 0;
end
else if (largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 1)
begin
largest_dataid_pipe_eq_afi_wlat_minus_1 <= dataid;
largest_dataid_pipe_eq_afi_wlat_minus_2 <= dataid;
largest_dataid_pipe_eq_afi_wlat_minus_3 <= dataid;
largest_dataid_vector_pipe_eq_afi_wlat_minus_1 <= dataid_vector;
largest_dataid_vector_pipe_eq_afi_wlat_minus_2 <= dataid_vector;
largest_dataid_vector_pipe_eq_afi_wlat_minus_3 <= dataid_vector;
end
else if (largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 2)
begin
largest_dataid_pipe_eq_afi_wlat_minus_1 <= dataid_pipe [0];
largest_dataid_pipe_eq_afi_wlat_minus_2 <= dataid;
largest_dataid_pipe_eq_afi_wlat_minus_3 <= dataid;
largest_dataid_vector_pipe_eq_afi_wlat_minus_1 <= dataid_vector_pipe[0];
largest_dataid_vector_pipe_eq_afi_wlat_minus_2 <= dataid_vector;
largest_dataid_vector_pipe_eq_afi_wlat_minus_3 <= dataid_vector;
end
else if (largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 3)
begin
largest_dataid_pipe_eq_afi_wlat_minus_1 <= dataid_pipe [1];
largest_dataid_pipe_eq_afi_wlat_minus_2 <= dataid_pipe [0];
largest_dataid_pipe_eq_afi_wlat_minus_3 <= dataid;
largest_dataid_vector_pipe_eq_afi_wlat_minus_1 <= dataid_vector_pipe[1];
largest_dataid_vector_pipe_eq_afi_wlat_minus_2 <= dataid_vector_pipe[0];
largest_dataid_vector_pipe_eq_afi_wlat_minus_3 <= dataid_vector;
end
else
begin
largest_dataid_pipe_eq_afi_wlat_minus_1 <= dataid_pipe [largest_afi_wlat_minus_2];
largest_dataid_pipe_eq_afi_wlat_minus_2 <= dataid_pipe [largest_afi_wlat_minus_3];
largest_dataid_pipe_eq_afi_wlat_minus_3 <= dataid_pipe [largest_afi_wlat_minus_4];
largest_dataid_vector_pipe_eq_afi_wlat_minus_1 <= dataid_vector_pipe[largest_afi_wlat_minus_2];
largest_dataid_vector_pipe_eq_afi_wlat_minus_2 <= dataid_vector_pipe[largest_afi_wlat_minus_3];
largest_dataid_vector_pipe_eq_afi_wlat_minus_3 <= dataid_vector_pipe[largest_afi_wlat_minus_4];
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
largest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b0;
largest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b0;
largest_rmw_correct_pipe_eq_afi_wlat_minus_3 <= 1'b0;
largest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b0;
largest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b0;
largest_rmw_partial_pipe_eq_afi_wlat_minus_3 <= 1'b0;
end
else
begin
if (largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 0)
begin
largest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b0;
largest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b0;
largest_rmw_correct_pipe_eq_afi_wlat_minus_3 <= 1'b0;
largest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b0;
largest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b0;
largest_rmw_partial_pipe_eq_afi_wlat_minus_3 <= 1'b0;
end
else if (largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 1)
begin
if (int_do_rmw_correct)
begin
largest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
largest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (int_do_rmw_partial)
begin
largest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
largest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (int_do_rmw_correct)
begin
largest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
largest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
if (int_do_rmw_partial)
begin
largest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
largest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
if (int_do_rmw_correct)
begin
largest_rmw_correct_pipe_eq_afi_wlat_minus_3 <= 1'b1;
end
else
begin
largest_rmw_correct_pipe_eq_afi_wlat_minus_3 <= 1'b0;
end
if (int_do_rmw_partial)
begin
largest_rmw_partial_pipe_eq_afi_wlat_minus_3 <= 1'b1;
end
else
begin
largest_rmw_partial_pipe_eq_afi_wlat_minus_3 <= 1'b0;
end
end
else if (largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 2)
begin
if (rmw_correct_pipe[0])
begin
largest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
largest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (rmw_partial_pipe[0])
begin
largest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
largest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (int_do_rmw_correct)
begin
largest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
largest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
if (int_do_rmw_partial)
begin
largest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
largest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
if (int_do_rmw_correct)
begin
largest_rmw_correct_pipe_eq_afi_wlat_minus_3 <= 1'b1;
end
else
begin
largest_rmw_correct_pipe_eq_afi_wlat_minus_3 <= 1'b0;
end
if (int_do_rmw_partial)
begin
largest_rmw_partial_pipe_eq_afi_wlat_minus_3 <= 1'b1;
end
else
begin
largest_rmw_partial_pipe_eq_afi_wlat_minus_3 <= 1'b0;
end
end
else if (largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 3)
begin
if (rmw_correct_pipe[1])
begin
largest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
largest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (rmw_partial_pipe[1])
begin
largest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
largest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (rmw_correct_pipe[0])
begin
largest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
largest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
if (rmw_partial_pipe[0])
begin
largest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
largest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
if (int_do_rmw_correct)
begin
largest_rmw_correct_pipe_eq_afi_wlat_minus_3 <= 1'b1;
end
else
begin
largest_rmw_correct_pipe_eq_afi_wlat_minus_3 <= 1'b0;
end
if (int_do_rmw_partial)
begin
largest_rmw_partial_pipe_eq_afi_wlat_minus_3 <= 1'b1;
end
else
begin
largest_rmw_partial_pipe_eq_afi_wlat_minus_3 <= 1'b0;
end
end
else
begin
if (rmw_correct_pipe[largest_afi_wlat_minus_2])
begin
largest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
largest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (rmw_partial_pipe[largest_afi_wlat_minus_2])
begin
largest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
largest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (rmw_correct_pipe[largest_afi_wlat_minus_3])
begin
largest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
largest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
if (rmw_partial_pipe[largest_afi_wlat_minus_3])
begin
largest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
largest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
if (rmw_correct_pipe[largest_afi_wlat_minus_4])
begin
largest_rmw_correct_pipe_eq_afi_wlat_minus_3 <= 1'b1;
end
else
begin
largest_rmw_correct_pipe_eq_afi_wlat_minus_3 <= 1'b0;
end
if (rmw_partial_pipe[largest_afi_wlat_minus_4])
begin
largest_rmw_partial_pipe_eq_afi_wlat_minus_3 <= 1'b1;
end
else
begin
largest_rmw_partial_pipe_eq_afi_wlat_minus_3 <= 1'b0;
end
end
end
end
always @ (*)
begin
if (CFG_WDATA_REG && CFG_ECC_ENC_REG)
begin
largest_doing_write_pipe_eq_afi_wlat_minus_x = largest_doing_write_pipe_eq_afi_wlat_minus_3 ;
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_x = largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_3;
largest_dataid_pipe_eq_afi_wlat_minus_x = largest_dataid_pipe_eq_afi_wlat_minus_3 ;
largest_dataid_vector_pipe_eq_afi_wlat_minus_x = largest_dataid_vector_pipe_eq_afi_wlat_minus_3 ;
largest_rmw_correct_pipe_eq_afi_wlat_minus_x = largest_rmw_correct_pipe_eq_afi_wlat_minus_3 ;
largest_rmw_partial_pipe_eq_afi_wlat_minus_x = largest_rmw_partial_pipe_eq_afi_wlat_minus_3 ;
end
else if (CFG_WDATA_REG || CFG_ECC_ENC_REG)
begin
largest_doing_write_pipe_eq_afi_wlat_minus_x = largest_doing_write_pipe_eq_afi_wlat_minus_2 ;
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_x = largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2;
largest_dataid_pipe_eq_afi_wlat_minus_x = largest_dataid_pipe_eq_afi_wlat_minus_2 ;
largest_dataid_vector_pipe_eq_afi_wlat_minus_x = largest_dataid_vector_pipe_eq_afi_wlat_minus_2 ;
largest_rmw_correct_pipe_eq_afi_wlat_minus_x = largest_rmw_correct_pipe_eq_afi_wlat_minus_2 ;
largest_rmw_partial_pipe_eq_afi_wlat_minus_x = largest_rmw_partial_pipe_eq_afi_wlat_minus_2 ;
end
else
begin
largest_doing_write_pipe_eq_afi_wlat_minus_x = largest_doing_write_pipe_eq_afi_wlat_minus_1 ;
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_x = largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1;
largest_dataid_pipe_eq_afi_wlat_minus_x = largest_dataid_pipe_eq_afi_wlat_minus_1 ;
largest_dataid_vector_pipe_eq_afi_wlat_minus_x = largest_dataid_vector_pipe_eq_afi_wlat_minus_1 ;
largest_rmw_correct_pipe_eq_afi_wlat_minus_x = largest_rmw_correct_pipe_eq_afi_wlat_minus_1 ;
largest_rmw_partial_pipe_eq_afi_wlat_minus_x = largest_rmw_partial_pipe_eq_afi_wlat_minus_1 ;
end
end
end
endgenerate
//*************************************************************************************************//
// afi_rank generation logic //
//*************************************************************************************************//
// to_chip information, based on arbiter type, we need column chip information only
always @ (*)
begin
if (CFG_CTL_ARBITER_TYPE == "ROWCOL")
begin
// Take the top chip information
int_to_chip = bg_to_chip [CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP - 1 : (CFG_AFI_INTF_PHASE_NUM - 1) * CFG_MEM_IF_CHIP];
end
else if (CFG_CTL_ARBITER_TYPE == "COLROW")
begin
// Take the bottom chip information
int_to_chip = bg_to_chip [CFG_MEM_IF_CHIP - 1 : 0];
end
end
// Chip information for read command
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
rd_chip <= 0;
end
else
begin
if (|bg_do_read)
begin
rd_chip <= int_to_chip;
end
end
end
// afi_rank information for read command
always @ (*)
begin
if (|bg_do_read)
begin
int_rd_rank_full_rate = int_to_chip;
end
else if (bg_doing_read)
begin
int_rd_rank_full_rate = rd_chip;
end
else
begin
// afi_rrank needs to be sticky (case:45607)
int_rd_rank_full_rate = rd_chip;
end
end
// Registered read rank information
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_rd_rank_full_rate_r <= 0;
end
else
begin
int_rd_rank_full_rate_r <= int_rd_rank_full_rate;
end
end
// afi_rank information for write command
generate
genvar R;
for (R = 0;R < CFG_DRAM_WLAT_GROUP;R = R + 1)
begin : wr_rank_info_loop
// Full rate rank information
always @ (*)
begin
if (afi_wlat_eq_0 [R])
begin
if (do_write_pipe [0])
begin
int_wr_rank_full_rate [R] = wr_chip_pipe_eq_afi_wlat_minus_0 [R];
end
else if (|bg_do_write)
begin
int_wr_rank_full_rate [R] = int_to_chip;
end
else if (doing_write_pipe [0])
begin
int_wr_rank_full_rate [R] = int_wr_rank_full_rate_r [R];
end
else
begin
int_wr_rank_full_rate [R] = 0;
end
end
else
begin
if (do_write_pipe_eq_afi_wlat_minus_0 [R])
begin
int_wr_rank_full_rate [R] = wr_chip_pipe_eq_afi_wlat_minus_0 [R];
end
else if (do_write_pipe_eq_afi_wlat_minus_1 [R])
begin
int_wr_rank_full_rate [R] = wr_chip_pipe_eq_afi_wlat_minus_1 [R];
end
else if (doing_write_pipe_eq_afi_wlat_minus_0 [R])
begin
int_wr_rank_full_rate [R] = int_wr_rank_full_rate_r [R];
end
else
begin
int_wr_rank_full_rate [R] = 0;
end
end
end
// Half rate rank information
always @ (*)
begin
if (afi_wlat_eq_0 [R])
begin
if (do_write_pipe [0])
begin
int_wr_rank_half_rate [R] = wr_chip_pipe_eq_afi_wlat_minus_0 [R];
end
else if (doing_write_pipe [0])
begin
int_wr_rank_half_rate [R] = int_wr_rank_half_rate_r [R];
end
else
begin
int_wr_rank_half_rate [R] = 0;
end
end
else
begin
if (do_write_pipe_eq_afi_wlat_minus_0 [R])
begin
int_wr_rank_half_rate [R] = wr_chip_pipe_eq_afi_wlat_minus_0 [R];
end
else if (doing_write_pipe_eq_afi_wlat_minus_0 [R])
begin
int_wr_rank_half_rate [R] = int_wr_rank_half_rate_r [R];
end
else
begin
int_wr_rank_half_rate [R] = 0;
end
end
end
// Registered write rank information
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_wr_rank_full_rate_r [R] <= 0;
int_wr_rank_half_rate_r [R] <= 0;
end
else
begin
int_wr_rank_full_rate_r [R] <= int_wr_rank_full_rate [R];
int_wr_rank_half_rate_r [R] <= int_wr_rank_half_rate [R];
end
end
end
for (R = 0;R < CFG_MEM_IF_DQS_WIDTH;R = R + 1)
begin : rank_info_per_dqs_group
wire [CFG_MEM_IF_CHIP-1:0] derived_rd_rank_full_rate;
wire [CFG_MEM_IF_CHIP-1:0] derived_rd_rank_full_rate_r;
wire [CFG_MEM_IF_CHIP-1:0] derived_wr_rank_full_rate;
wire [CFG_MEM_IF_CHIP-1:0] derived_wr_rank_full_rate_r;
wire [CFG_MEM_IF_CHIP-1:0] derived_wr_rank_half_rate;
wire [CFG_MEM_IF_CHIP-1:0] derived_wr_rank_half_rate_r;
if (CFG_DRAM_WLAT_GROUP == 1)
begin
assign derived_rd_rank_full_rate = int_rd_rank_full_rate;
assign derived_rd_rank_full_rate_r = int_rd_rank_full_rate_r;
assign derived_wr_rank_full_rate = int_wr_rank_full_rate [0];
assign derived_wr_rank_full_rate_r = int_wr_rank_full_rate_r [0];
assign derived_wr_rank_half_rate = int_wr_rank_half_rate [0];
assign derived_wr_rank_half_rate_r = int_wr_rank_half_rate_r [0];
end
else
begin
assign derived_rd_rank_full_rate = int_rd_rank_full_rate;
assign derived_rd_rank_full_rate_r = int_rd_rank_full_rate_r;
assign derived_wr_rank_full_rate = int_wr_rank_full_rate [R];
assign derived_wr_rank_full_rate_r = int_wr_rank_full_rate_r [R];
assign derived_wr_rank_half_rate = int_wr_rank_half_rate [R];
assign derived_wr_rank_half_rate_r = int_wr_rank_half_rate_r [R];
end
// afi_rank information
if (CFG_DWIDTH_RATIO == 2) // full rate
begin
assign int_rd_rank [((R + 1) * CFG_MEM_IF_CHIP) + (CFG_MEM_IF_CHIP * CFG_MEM_IF_DQS_WIDTH * 0) - 1 : (R * CFG_MEM_IF_CHIP) + (CFG_MEM_IF_CHIP * CFG_MEM_IF_DQS_WIDTH * 0)] = (cfg_output_regd_for_afi_output) ? derived_rd_rank_full_rate_r : derived_rd_rank_full_rate;
assign int_wr_rank [((R + 1) * CFG_MEM_IF_CHIP) + (CFG_MEM_IF_CHIP * CFG_MEM_IF_DQS_WIDTH * 0) - 1 : (R * CFG_MEM_IF_CHIP) + (CFG_MEM_IF_CHIP * CFG_MEM_IF_DQS_WIDTH * 0)] = (cfg_output_regd_for_afi_output) ? derived_wr_rank_full_rate_r : derived_wr_rank_full_rate;
end
else if (CFG_DWIDTH_RATIO == 4) // half rate
begin
assign int_rd_rank [((R + 1) * CFG_MEM_IF_CHIP) + (CFG_MEM_IF_CHIP * CFG_MEM_IF_DQS_WIDTH * 1) - 1 : (R * CFG_MEM_IF_CHIP) + (CFG_MEM_IF_CHIP * CFG_MEM_IF_DQS_WIDTH * 1)] = (cfg_output_regd_for_afi_output) ? derived_rd_rank_full_rate_r : derived_rd_rank_full_rate;
assign int_rd_rank [((R + 1) * CFG_MEM_IF_CHIP) + (CFG_MEM_IF_CHIP * CFG_MEM_IF_DQS_WIDTH * 0) - 1 : (R * CFG_MEM_IF_CHIP) + (CFG_MEM_IF_CHIP * CFG_MEM_IF_DQS_WIDTH * 0)] = (cfg_output_regd_for_afi_output) ? derived_rd_rank_full_rate_r : derived_rd_rank_full_rate;
assign int_wr_rank [((R + 1) * CFG_MEM_IF_CHIP) + (CFG_MEM_IF_CHIP * CFG_MEM_IF_DQS_WIDTH * 1) - 1 : (R * CFG_MEM_IF_CHIP) + (CFG_MEM_IF_CHIP * CFG_MEM_IF_DQS_WIDTH * 1)] = (cfg_output_regd_for_afi_output) ? derived_wr_rank_full_rate_r: derived_wr_rank_full_rate;
assign int_wr_rank [((R + 1) * CFG_MEM_IF_CHIP) + (CFG_MEM_IF_CHIP * CFG_MEM_IF_DQS_WIDTH * 0) - 1 : (R * CFG_MEM_IF_CHIP) + (CFG_MEM_IF_CHIP * CFG_MEM_IF_DQS_WIDTH * 0)] = (cfg_output_regd_for_afi_output) ? derived_wr_rank_half_rate_r: derived_wr_rank_half_rate;
end
else if (CFG_DWIDTH_RATIO == 8) // quarter rate
begin
assign int_rd_rank [((R + 1) * CFG_MEM_IF_CHIP) + (CFG_MEM_IF_CHIP * CFG_MEM_IF_DQS_WIDTH * 3) - 1 : (R * CFG_MEM_IF_CHIP) + (CFG_MEM_IF_CHIP * CFG_MEM_IF_DQS_WIDTH * 3)] = (cfg_output_regd_for_afi_output) ? derived_rd_rank_full_rate_r : derived_rd_rank_full_rate;
assign int_rd_rank [((R + 1) * CFG_MEM_IF_CHIP) + (CFG_MEM_IF_CHIP * CFG_MEM_IF_DQS_WIDTH * 2) - 1 : (R * CFG_MEM_IF_CHIP) + (CFG_MEM_IF_CHIP * CFG_MEM_IF_DQS_WIDTH * 2)] = (cfg_output_regd_for_afi_output) ? derived_rd_rank_full_rate_r : derived_rd_rank_full_rate;
assign int_rd_rank [((R + 1) * CFG_MEM_IF_CHIP) + (CFG_MEM_IF_CHIP * CFG_MEM_IF_DQS_WIDTH * 1) - 1 : (R * CFG_MEM_IF_CHIP) + (CFG_MEM_IF_CHIP * CFG_MEM_IF_DQS_WIDTH * 1)] = (cfg_output_regd_for_afi_output) ? derived_rd_rank_full_rate_r : derived_rd_rank_full_rate;
assign int_rd_rank [((R + 1) * CFG_MEM_IF_CHIP) + (CFG_MEM_IF_CHIP * CFG_MEM_IF_DQS_WIDTH * 0) - 1 : (R * CFG_MEM_IF_CHIP) + (CFG_MEM_IF_CHIP * CFG_MEM_IF_DQS_WIDTH * 0)] = (cfg_output_regd_for_afi_output) ? derived_rd_rank_full_rate_r : derived_rd_rank_full_rate;
assign int_wr_rank [((R + 1) * CFG_MEM_IF_CHIP) + (CFG_MEM_IF_CHIP * CFG_MEM_IF_DQS_WIDTH * 3) - 1 : (R * CFG_MEM_IF_CHIP) + (CFG_MEM_IF_CHIP * CFG_MEM_IF_DQS_WIDTH * 3)] = (cfg_output_regd_for_afi_output) ? derived_wr_rank_full_rate_r : derived_wr_rank_full_rate;
assign int_wr_rank [((R + 1) * CFG_MEM_IF_CHIP) + (CFG_MEM_IF_CHIP * CFG_MEM_IF_DQS_WIDTH * 2) - 1 : (R * CFG_MEM_IF_CHIP) + (CFG_MEM_IF_CHIP * CFG_MEM_IF_DQS_WIDTH * 2)] = (cfg_output_regd_for_afi_output) ? derived_wr_rank_half_rate_r : derived_wr_rank_half_rate;
assign int_wr_rank [((R + 1) * CFG_MEM_IF_CHIP) + (CFG_MEM_IF_CHIP * CFG_MEM_IF_DQS_WIDTH * 1) - 1 : (R * CFG_MEM_IF_CHIP) + (CFG_MEM_IF_CHIP * CFG_MEM_IF_DQS_WIDTH * 1)] = (cfg_output_regd_for_afi_output) ? derived_wr_rank_half_rate_r : derived_wr_rank_half_rate;
assign int_wr_rank [((R + 1) * CFG_MEM_IF_CHIP) + (CFG_MEM_IF_CHIP * CFG_MEM_IF_DQS_WIDTH * 0) - 1 : (R * CFG_MEM_IF_CHIP) + (CFG_MEM_IF_CHIP * CFG_MEM_IF_DQS_WIDTH * 0)] = (cfg_output_regd_for_afi_output) ? derived_wr_rank_half_rate_r : derived_wr_rank_half_rate;
end
end
// Registered output
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_rd_rank_r <= 0;
int_wr_rank_r <= 0;
end
else
begin
int_rd_rank_r <= int_rd_rank;
int_wr_rank_r <= int_wr_rank;
end
end
if (CFG_USE_SHADOW_REGS)
begin
assign afi_rrank = (cfg_output_regd_for_afi_output == 2) ? int_rd_rank_r : int_rd_rank;
assign afi_wrank = (cfg_output_regd_for_afi_output == 2) ? int_wr_rank_r : int_wr_rank;
end
else
begin
assign afi_rrank = 0;
assign afi_wrank = 0;
end
endgenerate
//*************************************************************************************************//
// afi_dqs_burst generation logic //
//*************************************************************************************************//
generate
genvar S;
for (S = 0;S < CFG_DRAM_WLAT_GROUP;S = S + 1) // generate wlat logic for each DQS group
begin : dqs_burst_logic_per_dqs_group_1
// high earlier than wdata_valid but ends the same
// for writes only, where dqs should toggle, use doing_write_pipe
always @(*)
begin
if (afi_wlat_eq_0 [S])
begin
if (bg_doing_write || doing_write_pipe[0])
begin
int_dqs_burst [S] = 1'b1;
end
else
begin
int_dqs_burst [S] = 1'b0;
end
end
else
begin
if (doing_write_pipe_eq_afi_wlat_minus_1 [S] || doing_write_pipe_eq_afi_wlat_minus_0 [S])
begin
int_dqs_burst [S] = 1'b1;
end
else
begin
int_dqs_burst [S] = 1'b0;
end
end
end
// registered output
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_dqs_burst_r [S] <= 1'b0;
end
else
begin
int_dqs_burst_r [S] <= int_dqs_burst [S];
end
end
always @ (*)
begin
if (afi_wlat_eq_0 [S])
begin
if (doing_write_pipe[0])
begin
int_dqs_burst_half_rate [S] = 1'b1;
end
else
begin
int_dqs_burst_half_rate [S] = 1'b0;
end
end
else
begin
if (doing_write_pipe_eq_afi_wlat_minus_0 [S])
begin
int_dqs_burst_half_rate [S] = 1'b1;
end
else
begin
int_dqs_burst_half_rate [S] = 1'b0;
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_dqs_burst_half_rate_r [S] <= 1'b0;
end
else
begin
int_dqs_burst_half_rate_r [S] <= int_dqs_burst_half_rate [S];
end
end
end
for (S = 0; S < CFG_MEM_IF_DQS_WIDTH; S = S + 1)
begin : dqs_burst_logic_per_dqs_group_2
wire derived_dqs_burst;
wire derived_dqs_burst_r;
wire derived_dqs_burst_half_rate;
wire derived_dqs_burst_half_rate_r;
if (CFG_DRAM_WLAT_GROUP == 1)
begin
assign derived_dqs_burst = int_dqs_burst [0];
assign derived_dqs_burst_r = int_dqs_burst_r [0];
assign derived_dqs_burst_half_rate = int_dqs_burst_half_rate [0];
assign derived_dqs_burst_half_rate_r = int_dqs_burst_half_rate_r [0];
end
else
begin
assign derived_dqs_burst = int_dqs_burst [S];
assign derived_dqs_burst_r = int_dqs_burst_r [S];
assign derived_dqs_burst_half_rate = int_dqs_burst_half_rate [S];
assign derived_dqs_burst_half_rate_r = int_dqs_burst_half_rate_r [S];
end
if (CFG_DWIDTH_RATIO == 2) // fullrate
begin
assign int_afi_dqs_burst [S] = (cfg_output_regd_for_afi_output) ? derived_dqs_burst_r : derived_dqs_burst;
end
else if (CFG_DWIDTH_RATIO == 4) // halfrate
begin
assign int_afi_dqs_burst[S + CFG_MEM_IF_DQS_WIDTH] = (cfg_output_regd_for_afi_output) ? derived_dqs_burst_r : derived_dqs_burst ;
assign int_afi_dqs_burst[S ] = (cfg_output_regd_for_afi_output) ? derived_dqs_burst_half_rate_r : derived_dqs_burst_half_rate;
end
else if (CFG_DWIDTH_RATIO == 8) // quarterrate
begin
assign int_afi_dqs_burst[S + CFG_MEM_IF_DQS_WIDTH * 3] = (cfg_output_regd_for_afi_output) ? derived_dqs_burst_r : derived_dqs_burst ;
assign int_afi_dqs_burst[S + CFG_MEM_IF_DQS_WIDTH * 2] = (cfg_output_regd_for_afi_output) ? derived_dqs_burst_half_rate_r : derived_dqs_burst_half_rate;
assign int_afi_dqs_burst[S + CFG_MEM_IF_DQS_WIDTH * 1] = (cfg_output_regd_for_afi_output) ? derived_dqs_burst_half_rate_r : derived_dqs_burst_half_rate;
assign int_afi_dqs_burst[S ] = (cfg_output_regd_for_afi_output) ? derived_dqs_burst_half_rate_r : derived_dqs_burst_half_rate;
end
end
endgenerate
// Registered output
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_afi_dqs_burst_r <= 0;
end
else
begin
int_afi_dqs_burst_r <= int_afi_dqs_burst;
end
end
assign afi_dqs_burst = (cfg_output_regd_for_afi_output == 2) ? int_afi_dqs_burst_r : int_afi_dqs_burst;
//*************************************************************************************************//
// afi_wdata_valid generation logic //
//*************************************************************************************************//
generate
genvar T;
for (T = 0;T < CFG_DRAM_WLAT_GROUP;T = T + 1) // generate wlat logic for each DQS group
begin : wdata_valid_logic_per_dqs_group_1
always @(*)
begin
if (afi_wlat_eq_0 [T])
begin
if (doing_write_pipe[0])
begin
int_wdata_valid [T] = 1'b1;
end
else
begin
int_wdata_valid [T] = 1'b0;
end
end
else
begin
if (doing_write_pipe_eq_afi_wlat_minus_0 [T])
begin
int_wdata_valid [T] = 1'b1;
end
else
begin
int_wdata_valid [T] = 1'b0;
end
end
end
// registered output
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_wdata_valid_r [T] <= 1'b0;
end
else
begin
int_wdata_valid_r [T] <= int_wdata_valid [T];
end
end
end
for (T = 0;T < CFG_MEM_IF_DQS_WIDTH;T = T + 1)
begin : wdata_valid_logic_per_dqs_group_2
wire derived_wdata_valid;
wire derived_wdata_valid_r;
if (CFG_DRAM_WLAT_GROUP == 1)
begin
assign derived_wdata_valid = int_wdata_valid [0];
assign derived_wdata_valid_r = int_wdata_valid_r [0];
end
else
begin
assign derived_wdata_valid = int_wdata_valid [T];
assign derived_wdata_valid_r = int_wdata_valid_r [T];
end
if (CFG_DWIDTH_RATIO == 2) // fullrate
begin
assign int_afi_wdata_valid [T] = (cfg_output_regd_for_afi_output) ? derived_wdata_valid_r : derived_wdata_valid;
end
else if (CFG_DWIDTH_RATIO == 4) // halfrate
begin
assign int_afi_wdata_valid [T + CFG_MEM_IF_DQS_WIDTH] = (cfg_output_regd_for_afi_output) ? derived_wdata_valid_r : derived_wdata_valid;
assign int_afi_wdata_valid [T ] = (cfg_output_regd_for_afi_output) ? derived_wdata_valid_r : derived_wdata_valid;
end
else if (CFG_DWIDTH_RATIO == 8) // quarterrate
begin
assign int_afi_wdata_valid [T + CFG_MEM_IF_DQS_WIDTH * 3] = (cfg_output_regd_for_afi_output) ? derived_wdata_valid_r : derived_wdata_valid;
assign int_afi_wdata_valid [T + CFG_MEM_IF_DQS_WIDTH * 2] = (cfg_output_regd_for_afi_output) ? derived_wdata_valid_r : derived_wdata_valid;
assign int_afi_wdata_valid [T + CFG_MEM_IF_DQS_WIDTH * 1] = (cfg_output_regd_for_afi_output) ? derived_wdata_valid_r : derived_wdata_valid;
assign int_afi_wdata_valid [T ] = (cfg_output_regd_for_afi_output) ? derived_wdata_valid_r : derived_wdata_valid;
end
end
endgenerate
// Registered output
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_afi_wdata_valid_r <= 0;
end
else
begin
int_afi_wdata_valid_r <= int_afi_wdata_valid;
end
end
assign afi_wdata_valid = (cfg_output_regd_for_afi_output == 2) ? int_afi_wdata_valid_r : int_afi_wdata_valid;
//*************************************************************************************************//
// afi_wdata generation logic //
//*************************************************************************************************//
generate
genvar M;
for (M = 0;M < CFG_DRAM_WLAT_GROUP;M = M + 1) // generate wlat logic for each DQS group
begin : wlat_logic_per_dqs_group
//*************************************************************************************************//
// ecc_wdata_fifo_read //
//*************************************************************************************************//
// Indicate when to read from write data buffer
// based on burst_gen signals
always @(*)
begin
if (afi_wlat_eq_0 [M])
begin
if (bg_rdwr_data_valid && bg_doing_write)
begin
int_ecc_wdata_fifo_read [M] = 1'b1;
end
else
begin
int_ecc_wdata_fifo_read [M] = 1'b0;
end
end
else
begin
if (rdwr_data_valid_pipe_eq_afi_wlat_minus_x [M] && doing_write_pipe_eq_afi_wlat_minus_x [M])
begin
int_ecc_wdata_fifo_read [M] = 1'b1;
end
else
begin
int_ecc_wdata_fifo_read [M] = 1'b0;
end
end
end
// Registered output
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_ecc_wdata_fifo_read_r [M] <= 1'b0;
end
else
begin
int_ecc_wdata_fifo_read_r [M] <= int_ecc_wdata_fifo_read [M];
end
end
// Determine write data buffer read signal based on output_regd info
// output_regd info is derived based on afi_wlat value
assign ecc_wdata_fifo_read [M] = (cfg_output_regd_for_wdata_path) ? int_ecc_wdata_fifo_read_r [M] : int_ecc_wdata_fifo_read [M];
// Registered output
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
ecc_wdata_fifo_read_r1 [M] <= 1'b0;
ecc_wdata_fifo_read_r2 [M] <= 1'b0;
end
else
begin
ecc_wdata_fifo_read_r1 [M] <= ecc_wdata_fifo_read [M];
ecc_wdata_fifo_read_r2 [M] <= ecc_wdata_fifo_read_r1 [M];
end
end
// data valid one clock cycle after read
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_real_wdata_valid [M] <= 1'b0;
end
else
begin
if (CFG_WDATA_REG && CFG_ECC_ENC_REG)
begin
int_real_wdata_valid [M] <= ecc_wdata_fifo_read_r2 [M];
end
else if (CFG_WDATA_REG || CFG_ECC_ENC_REG)
begin
int_real_wdata_valid [M] <= ecc_wdata_fifo_read_r1 [M];
end
else
begin
int_real_wdata_valid [M] <= ecc_wdata_fifo_read [M];
end
end
end
//*************************************************************************************************//
// ecc_wdata_fifo_dataid/dataid_vector //
//*************************************************************************************************//
// Dataid generation to write buffer, to indicate which wdata should be passed to AFI
always @(*)
begin
if (afi_wlat_eq_0 [M])
begin
if (bg_rdwr_data_valid && bg_doing_write)
begin
int_ecc_wdata_fifo_dataid [M] = dataid;
int_ecc_wdata_fifo_dataid_vector [M] = dataid_vector;
end
else
begin
int_ecc_wdata_fifo_dataid [M] = {(CFG_DATA_ID_WIDTH){1'b0}};
int_ecc_wdata_fifo_dataid_vector [M] = {(CFG_DATAID_ARRAY_DEPTH){1'b0}};
end
end
else
begin
if (rdwr_data_valid_pipe_eq_afi_wlat_minus_x [M] && doing_write_pipe_eq_afi_wlat_minus_x [M])
begin
int_ecc_wdata_fifo_dataid [M] = dataid_pipe_eq_afi_wlat_minus_x [M];
int_ecc_wdata_fifo_dataid_vector [M] = dataid_vector_pipe_eq_afi_wlat_minus_x [M];
end
else
begin
int_ecc_wdata_fifo_dataid [M] = {(CFG_DATA_ID_WIDTH){1'b0}};
int_ecc_wdata_fifo_dataid_vector [M] = {(CFG_DATAID_ARRAY_DEPTH){1'b0}};
end
end
end
// Registered output
always @ (posedge ctl_clk, negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
int_ecc_wdata_fifo_dataid_r [M] <= 0;
int_ecc_wdata_fifo_dataid_vector_r [M] <= 0;
end
else
begin
int_ecc_wdata_fifo_dataid_r [M] <= int_ecc_wdata_fifo_dataid [M];
int_ecc_wdata_fifo_dataid_vector_r [M] <= int_ecc_wdata_fifo_dataid_vector [M];
end
end
assign ecc_wdata_fifo_dataid [(M + 1) * CFG_DATA_ID_WIDTH - 1 : M * CFG_DATA_ID_WIDTH ] = (cfg_output_regd_for_wdata_path) ? int_ecc_wdata_fifo_dataid_r [M] : int_ecc_wdata_fifo_dataid [M];
assign ecc_wdata_fifo_dataid_vector [(M + 1) * CFG_DATAID_ARRAY_DEPTH - 1 : M * CFG_DATAID_ARRAY_DEPTH] = (cfg_output_regd_for_wdata_path) ? int_ecc_wdata_fifo_dataid_vector_r [M] : int_ecc_wdata_fifo_dataid_vector [M];
//*************************************************************************************************//
// ecc_wdata_fifo_rmw_correct/partial //
//*************************************************************************************************//
// Read modify write info logic
always @(*)
begin
if (afi_wlat_eq_0 [M])
begin
if (bg_rdwr_data_valid && bg_doing_write)
begin
int_ecc_wdata_fifo_rmw_correct [M] = int_do_rmw_correct;
int_ecc_wdata_fifo_rmw_partial [M] = int_do_rmw_partial;
end
else
begin
int_ecc_wdata_fifo_rmw_correct [M] = 1'b0;
int_ecc_wdata_fifo_rmw_partial [M] = 1'b0;
end
end
else
begin
if (rdwr_data_valid_pipe_eq_afi_wlat_minus_x [M] && doing_write_pipe_eq_afi_wlat_minus_x [M])
begin
int_ecc_wdata_fifo_rmw_correct [M] = rmw_correct_pipe_eq_afi_wlat_minus_x [M];
int_ecc_wdata_fifo_rmw_partial [M] = rmw_partial_pipe_eq_afi_wlat_minus_x [M];
end
else
begin
int_ecc_wdata_fifo_rmw_correct [M] = 1'b0;
int_ecc_wdata_fifo_rmw_partial [M] = 1'b0;
end
end
end
always @ (posedge ctl_clk, negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
int_ecc_wdata_fifo_rmw_correct_r [M] <= 0;
int_ecc_wdata_fifo_rmw_partial_r [M] <= 0;
end
else
begin
int_ecc_wdata_fifo_rmw_correct_r [M] <= int_ecc_wdata_fifo_rmw_correct [M];
int_ecc_wdata_fifo_rmw_partial_r [M] <= int_ecc_wdata_fifo_rmw_partial [M];
end
end
assign ecc_wdata_fifo_rmw_correct [M] = (cfg_output_regd_for_wdata_path) ? int_ecc_wdata_fifo_rmw_correct_r [M] : int_ecc_wdata_fifo_rmw_correct [M];
assign ecc_wdata_fifo_rmw_partial [M] = (cfg_output_regd_for_wdata_path) ? int_ecc_wdata_fifo_rmw_partial_r [M] : int_ecc_wdata_fifo_rmw_partial [M];
end
endgenerate
generate
if (CFG_DRAM_WLAT_GROUP == 1) // only one group of afi_wlat
begin
assign ecc_wdata_fifo_read_first = ecc_wdata_fifo_read;
assign ecc_wdata_fifo_dataid_first = ecc_wdata_fifo_dataid;
assign ecc_wdata_fifo_dataid_vector_first = ecc_wdata_fifo_dataid_vector;
assign ecc_wdata_fifo_rmw_correct_first = ecc_wdata_fifo_rmw_correct;
assign ecc_wdata_fifo_rmw_partial_first = ecc_wdata_fifo_rmw_partial;
assign ecc_wdata_fifo_read_last = ecc_wdata_fifo_read;
assign ecc_wdata_fifo_dataid_last = ecc_wdata_fifo_dataid;
assign ecc_wdata_fifo_dataid_vector_last = ecc_wdata_fifo_dataid_vector;
assign ecc_wdata_fifo_rmw_correct_last = ecc_wdata_fifo_rmw_correct;
assign ecc_wdata_fifo_rmw_partial_last = ecc_wdata_fifo_rmw_partial;
end
else
begin
reg ecc_wdata_fifo_read_first_r;
reg int_ecc_wdata_fifo_read_first;
reg int_ecc_wdata_fifo_read_first_r;
reg [CFG_DATA_ID_WIDTH-1:0] int_ecc_wdata_fifo_dataid_first;
reg [CFG_DATA_ID_WIDTH-1:0] int_ecc_wdata_fifo_dataid_first_r;
reg [CFG_DATAID_ARRAY_DEPTH-1:0] int_ecc_wdata_fifo_dataid_vector_first;
reg [CFG_DATAID_ARRAY_DEPTH-1:0] int_ecc_wdata_fifo_dataid_vector_first_r;
reg int_ecc_wdata_fifo_rmw_correct_first;
reg int_ecc_wdata_fifo_rmw_correct_first_r;
reg int_ecc_wdata_fifo_rmw_partial_first;
reg int_ecc_wdata_fifo_rmw_partial_first_r;
reg ecc_wdata_fifo_read_last_r;
reg int_ecc_wdata_fifo_read_last;
reg int_ecc_wdata_fifo_read_last_r;
reg [CFG_DATA_ID_WIDTH-1:0] int_ecc_wdata_fifo_dataid_last;
reg [CFG_DATA_ID_WIDTH-1:0] int_ecc_wdata_fifo_dataid_last_r;
reg [CFG_DATAID_ARRAY_DEPTH-1:0] int_ecc_wdata_fifo_dataid_vector_last;
reg [CFG_DATAID_ARRAY_DEPTH-1:0] int_ecc_wdata_fifo_dataid_vector_last_r;
reg int_ecc_wdata_fifo_rmw_correct_last;
reg int_ecc_wdata_fifo_rmw_correct_last_r;
reg int_ecc_wdata_fifo_rmw_partial_last;
reg int_ecc_wdata_fifo_rmw_partial_last_r;
// Determine first ecc_wdata_fifo_* info
//*************************************************************************************************//
// ecc_wdata_fifo_read //
//*************************************************************************************************//
// Indicate when to read from write data buffer
// based on burst_gen signals
always @(*)
begin
if (smallest_afi_wlat_eq_0)
begin
if (bg_rdwr_data_valid && bg_doing_write)
begin
int_ecc_wdata_fifo_read_first = 1'b1;
end
else
begin
int_ecc_wdata_fifo_read_first = 1'b0;
end
end
else
begin
if (smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_x && smallest_doing_write_pipe_eq_afi_wlat_minus_x)
begin
int_ecc_wdata_fifo_read_first = 1'b1;
end
else
begin
int_ecc_wdata_fifo_read_first = 1'b0;
end
end
end
// Registered output
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_ecc_wdata_fifo_read_first_r <= 1'b0;
end
else
begin
int_ecc_wdata_fifo_read_first_r <= int_ecc_wdata_fifo_read_first;
end
end
// Determine write data buffer read signal based on output_regd info
// output_regd info is derived based on afi_wlat value
assign ecc_wdata_fifo_read_first = (cfg_output_regd_for_wdata_path) ? int_ecc_wdata_fifo_read_first_r : int_ecc_wdata_fifo_read_first;
// Registered output
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
ecc_wdata_fifo_read_first_r <= 1'b0;
end
else
begin
ecc_wdata_fifo_read_first_r <= ecc_wdata_fifo_read_first;
end
end
//*************************************************************************************************//
// ecc_wdata_fifo_dataid/dataid_vector //
//*************************************************************************************************//
// Dataid generation to write buffer, to indicate which wdata should be passed to AFI
always @(*)
begin
if (smallest_afi_wlat_eq_0)
begin
if (bg_rdwr_data_valid && bg_doing_write)
begin
int_ecc_wdata_fifo_dataid_first = dataid;
int_ecc_wdata_fifo_dataid_vector_first = dataid_vector;
end
else
begin
int_ecc_wdata_fifo_dataid_first = {(CFG_DATA_ID_WIDTH){1'b0}};
int_ecc_wdata_fifo_dataid_vector_first = {(CFG_DATAID_ARRAY_DEPTH){1'b0}};
end
end
else
begin
if (smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_x && smallest_doing_write_pipe_eq_afi_wlat_minus_x)
begin
int_ecc_wdata_fifo_dataid_first = smallest_dataid_pipe_eq_afi_wlat_minus_x ;
int_ecc_wdata_fifo_dataid_vector_first = smallest_dataid_vector_pipe_eq_afi_wlat_minus_x;
end
else
begin
int_ecc_wdata_fifo_dataid_first = {(CFG_DATA_ID_WIDTH){1'b0}};
int_ecc_wdata_fifo_dataid_vector_first = {(CFG_DATAID_ARRAY_DEPTH){1'b0}};
end
end
end
// Registered output
always @ (posedge ctl_clk, negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
int_ecc_wdata_fifo_dataid_first_r <= 0;
int_ecc_wdata_fifo_dataid_vector_first_r <= 0;
end
else
begin
int_ecc_wdata_fifo_dataid_first_r <= int_ecc_wdata_fifo_dataid_first ;
int_ecc_wdata_fifo_dataid_vector_first_r <= int_ecc_wdata_fifo_dataid_vector_first;
end
end
assign ecc_wdata_fifo_dataid_first = (cfg_output_regd_for_wdata_path) ? int_ecc_wdata_fifo_dataid_first_r : int_ecc_wdata_fifo_dataid_first ;
assign ecc_wdata_fifo_dataid_vector_first = (cfg_output_regd_for_wdata_path) ? int_ecc_wdata_fifo_dataid_vector_first_r : int_ecc_wdata_fifo_dataid_vector_first;
//*************************************************************************************************//
// ecc_wdata_fifo_rmw_correct/partial //
//*************************************************************************************************//
// Read modify write info logic
always @(*)
begin
if (smallest_afi_wlat_eq_0)
begin
if (bg_rdwr_data_valid && bg_doing_write)
begin
int_ecc_wdata_fifo_rmw_correct_first = int_do_rmw_correct;
int_ecc_wdata_fifo_rmw_partial_first = int_do_rmw_partial;
end
else
begin
int_ecc_wdata_fifo_rmw_correct_first = 1'b0;
int_ecc_wdata_fifo_rmw_partial_first = 1'b0;
end
end
else
begin
if (smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_x && smallest_doing_write_pipe_eq_afi_wlat_minus_x)
begin
int_ecc_wdata_fifo_rmw_correct_first = smallest_rmw_correct_pipe_eq_afi_wlat_minus_x;
int_ecc_wdata_fifo_rmw_partial_first = smallest_rmw_partial_pipe_eq_afi_wlat_minus_x;
end
else
begin
int_ecc_wdata_fifo_rmw_correct_first = 1'b0;
int_ecc_wdata_fifo_rmw_partial_first = 1'b0;
end
end
end
always @ (posedge ctl_clk, negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
int_ecc_wdata_fifo_rmw_correct_first_r <= 0;
int_ecc_wdata_fifo_rmw_partial_first_r <= 0;
end
else
begin
int_ecc_wdata_fifo_rmw_correct_first_r <= int_ecc_wdata_fifo_rmw_correct_first;
int_ecc_wdata_fifo_rmw_partial_first_r <= int_ecc_wdata_fifo_rmw_partial_first;
end
end
assign ecc_wdata_fifo_rmw_correct_first = (cfg_output_regd_for_wdata_path) ? int_ecc_wdata_fifo_rmw_correct_first_r : int_ecc_wdata_fifo_rmw_correct_first;
assign ecc_wdata_fifo_rmw_partial_first = (cfg_output_regd_for_wdata_path) ? int_ecc_wdata_fifo_rmw_partial_first_r : int_ecc_wdata_fifo_rmw_partial_first;
// Determine last ecc_wdata_fifo_* info
//*************************************************************************************************//
// ecc_wdata_fifo_read //
//*************************************************************************************************//
// Indicate when to read from write data buffer
// based on burst_gen signals
always @(*)
begin
if (largest_afi_wlat_eq_0)
begin
if (bg_rdwr_data_valid && bg_doing_write)
begin
int_ecc_wdata_fifo_read_last = 1'b1;
end
else
begin
int_ecc_wdata_fifo_read_last = 1'b0;
end
end
else
begin
if (largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_x && largest_doing_write_pipe_eq_afi_wlat_minus_x)
begin
int_ecc_wdata_fifo_read_last = 1'b1;
end
else
begin
int_ecc_wdata_fifo_read_last = 1'b0;
end
end
end
// Registered output
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_ecc_wdata_fifo_read_last_r <= 1'b0;
end
else
begin
int_ecc_wdata_fifo_read_last_r <= int_ecc_wdata_fifo_read_last;
end
end
// Determine write data buffer read signal based on output_regd info
// output_regd info is derived based on afi_wlat value
assign ecc_wdata_fifo_read_last = (cfg_output_regd_for_wdata_path) ? int_ecc_wdata_fifo_read_last_r : int_ecc_wdata_fifo_read_last;
// Registered output
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
ecc_wdata_fifo_read_last_r <= 1'b0;
end
else
begin
ecc_wdata_fifo_read_last_r <= ecc_wdata_fifo_read_last;
end
end
//*************************************************************************************************//
// ecc_wdata_fifo_dataid/dataid_vector //
//*************************************************************************************************//
// Dataid generation to write buffer, to indicate which wdata should be passed to AFI
always @(*)
begin
if (largest_afi_wlat_eq_0)
begin
if (bg_rdwr_data_valid && bg_doing_write)
begin
int_ecc_wdata_fifo_dataid_last = dataid;
int_ecc_wdata_fifo_dataid_vector_last = dataid_vector;
end
else
begin
int_ecc_wdata_fifo_dataid_last = {(CFG_DATA_ID_WIDTH){1'b0}};
int_ecc_wdata_fifo_dataid_vector_last = {(CFG_DATAID_ARRAY_DEPTH){1'b0}};
end
end
else
begin
if (largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_x && largest_doing_write_pipe_eq_afi_wlat_minus_x)
begin
int_ecc_wdata_fifo_dataid_last = largest_dataid_pipe_eq_afi_wlat_minus_x ;
int_ecc_wdata_fifo_dataid_vector_last = largest_dataid_vector_pipe_eq_afi_wlat_minus_x;
end
else
begin
int_ecc_wdata_fifo_dataid_last = {(CFG_DATA_ID_WIDTH){1'b0}};
int_ecc_wdata_fifo_dataid_vector_last = {(CFG_DATAID_ARRAY_DEPTH){1'b0}};
end
end
end
// Registered output
always @ (posedge ctl_clk, negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
int_ecc_wdata_fifo_dataid_last_r <= 0;
int_ecc_wdata_fifo_dataid_vector_last_r <= 0;
end
else
begin
int_ecc_wdata_fifo_dataid_last_r <= int_ecc_wdata_fifo_dataid_last ;
int_ecc_wdata_fifo_dataid_vector_last_r <= int_ecc_wdata_fifo_dataid_vector_last;
end
end
assign ecc_wdata_fifo_dataid_last = (cfg_output_regd_for_wdata_path) ? int_ecc_wdata_fifo_dataid_last_r : int_ecc_wdata_fifo_dataid_last ;
assign ecc_wdata_fifo_dataid_vector_last = (cfg_output_regd_for_wdata_path) ? int_ecc_wdata_fifo_dataid_vector_last_r : int_ecc_wdata_fifo_dataid_vector_last;
//*************************************************************************************************//
// ecc_wdata_fifo_rmw_correct/partial //
//*************************************************************************************************//
// Read modify write info logic
always @(*)
begin
if (largest_afi_wlat_eq_0)
begin
if (bg_rdwr_data_valid && bg_doing_write)
begin
int_ecc_wdata_fifo_rmw_correct_last = int_do_rmw_correct;
int_ecc_wdata_fifo_rmw_partial_last = int_do_rmw_partial;
end
else
begin
int_ecc_wdata_fifo_rmw_correct_last = 1'b0;
int_ecc_wdata_fifo_rmw_partial_last = 1'b0;
end
end
else
begin
if (largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_x && largest_doing_write_pipe_eq_afi_wlat_minus_x)
begin
int_ecc_wdata_fifo_rmw_correct_last = largest_rmw_correct_pipe_eq_afi_wlat_minus_x;
int_ecc_wdata_fifo_rmw_partial_last = largest_rmw_partial_pipe_eq_afi_wlat_minus_x;
end
else
begin
int_ecc_wdata_fifo_rmw_correct_last = 1'b0;
int_ecc_wdata_fifo_rmw_partial_last = 1'b0;
end
end
end
always @ (posedge ctl_clk, negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
int_ecc_wdata_fifo_rmw_correct_last_r <= 0;
int_ecc_wdata_fifo_rmw_partial_last_r <= 0;
end
else
begin
int_ecc_wdata_fifo_rmw_correct_last_r <= int_ecc_wdata_fifo_rmw_correct_last;
int_ecc_wdata_fifo_rmw_partial_last_r <= int_ecc_wdata_fifo_rmw_partial_last;
end
end
assign ecc_wdata_fifo_rmw_correct_last = (cfg_output_regd_for_wdata_path) ? int_ecc_wdata_fifo_rmw_correct_last_r : int_ecc_wdata_fifo_rmw_correct_last;
assign ecc_wdata_fifo_rmw_partial_last = (cfg_output_regd_for_wdata_path) ? int_ecc_wdata_fifo_rmw_partial_last_r : int_ecc_wdata_fifo_rmw_partial_last;
end
endgenerate
// No data manipulation on wdata
assign afi_wdata = ecc_wdata;
//*************************************************************************************************//
// afi_dm generation logic //
//*************************************************************************************************//
//Why do we need ecc_dm and rdwr_data_valid to determine DM
// ecc_dm will not get updated till we read another data from wrfifo, so we need to drive DMs based on rdwr_data_valid
//Output registered information already backed in ecc_wdata_fifo_read
generate
genvar J;
genvar K;
if (CFG_DRAM_WLAT_GROUP == 1)
begin
for (J = 0; J < CFG_MEM_IF_DM_WIDTH * CFG_DWIDTH_RATIO; J = J + 1)
begin : dm_loop
assign afi_dm [J] = ~ecc_dm [J] | ~int_real_wdata_valid;
end
end
else
begin
for (J = 0; J < CFG_DWIDTH_RATIO; J = J + 1)
begin : dwidth_ratio_loop
for (K = 0; K < CFG_DRAM_WLAT_GROUP; K = K + 1)
begin : dm_loop
assign afi_dm [(J * CFG_DRAM_WLAT_GROUP) + K] = ~ecc_dm [(J * CFG_DRAM_WLAT_GROUP) + K] | ~int_real_wdata_valid [K];
end
end
end
endgenerate
endmodule
|
// This file has been automatically generated by goFB and should not be edited by hand
// Compiler written by Hammond Pearce and available at github.com/kiwih/goFB
// Verilog support is EXPERIMENTAL ONLY
// This file represents the Top of the IEC61499 network
module top
(
input wire clk,
//input events
input wire UpdateLevels_eI,
input wire UpdateControls_eI,
//output events
output wire UpdatePump_eO,
//input variables
input wire unsigned [7:0] Level1_I,
input wire unsigned [7:0] Level2_I,
input wire ModeBalance_I,
input wire ModeFill1_I,
input wire ModeFill2_I,
//output variables
output reg PumpDir_O = 0,
output reg PumpRun_O = 0,
input reset
);
// I/O
FB_BfbWaterPump iec61499_network_top (
.clk(clk),
//input events
.UpdateLevels_eI(UpdateLevels_eI),
.UpdateControls_eI(UpdateControls_eI),
//output events
.UpdatePump_eO(UpdatePump_eO),
//input variables
.Level1_I(Level1_I),
.Level2_I(Level2_I),
.ModeBalance_I(ModeBalance_I),
.ModeFill1_I(ModeFill1_I),
.ModeFill2_I(ModeFill2_I),
//output variables
.PumpDir_O(PumpDir_O),
.PumpRun_O(PumpRun_O),
.reset(reset)
);
endmodule |
// -- (c) Copyright 1995 - 2012 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
// You must compile the fifo_generator wrapper file when simulating
// the core. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_data_fifo_v2_1_fifo_gen #(
parameter C_FAMILY = "virtex7",
parameter integer C_COMMON_CLOCK = 1,
parameter integer C_SYNCHRONIZER_STAGE = 3,
parameter integer C_FIFO_DEPTH_LOG = 5,
parameter integer C_FIFO_WIDTH = 64,
parameter C_FIFO_TYPE = "lut"
)(
clk,
rst,
wr_clk,
wr_en,
wr_ready,
wr_data,
rd_clk,
rd_en,
rd_valid,
rd_data);
input clk;
input wr_clk;
input rd_clk;
input rst;
input [C_FIFO_WIDTH-1 : 0] wr_data;
input wr_en;
input rd_en;
output [C_FIFO_WIDTH-1 : 0] rd_data;
output wr_ready;
output rd_valid;
wire full;
wire empty;
wire rd_valid = ~empty;
wire wr_ready = ~full;
localparam C_MEMORY_TYPE = (C_FIFO_TYPE == "bram")? 1 : 2;
localparam C_IMPLEMENTATION_TYPE = (C_COMMON_CLOCK == 1)? 0 : 2;
fifo_generator_v12_0 #(
.C_COMMON_CLOCK(C_COMMON_CLOCK),
.C_DIN_WIDTH(C_FIFO_WIDTH),
.C_DOUT_WIDTH(C_FIFO_WIDTH),
.C_FAMILY(C_FAMILY),
.C_IMPLEMENTATION_TYPE(C_IMPLEMENTATION_TYPE),
.C_MEMORY_TYPE(C_MEMORY_TYPE),
.C_RD_DEPTH(1<<C_FIFO_DEPTH_LOG),
.C_RD_PNTR_WIDTH(C_FIFO_DEPTH_LOG),
.C_WR_DEPTH(1<<C_FIFO_DEPTH_LOG),
.C_WR_PNTR_WIDTH(C_FIFO_DEPTH_LOG),
.C_ADD_NGC_CONSTRAINT(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_AXIS_TDATA_WIDTH(64),
.C_AXIS_TDEST_WIDTH(4),
.C_AXIS_TID_WIDTH(8),
.C_AXIS_TKEEP_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(4),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TYPE(0),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_DATA_WIDTH(64),
.C_AXI_ID_WIDTH(4),
.C_AXI_LEN_WIDTH(8),
.C_AXI_LOCK_WIDTH(2),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_TYPE(0),
.C_AXI_WUSER_WIDTH(1),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(6),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH_AXIS(1),
.C_DIN_WIDTH_RACH(32),
.C_DIN_WIDTH_RDCH(64),
.C_DIN_WIDTH_WACH(32),
.C_DIN_WIDTH_WDCH(64),
.C_DIN_WIDTH_WRCH(2),
.C_DOUT_RST_VAL("0"),
.C_ENABLE_RLOCS(0),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_FULL_FLAGS_RST_VAL(0),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_AXIS_TDATA(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TKEEP(0),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TUSER(0),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_RD_CHANNEL(0),
.C_HAS_AXI_RUSER(0),
.C_HAS_AXI_WR_CHANNEL(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_INT_CLK(0),
.C_HAS_MASTER_CE(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SLAVE_CE(0),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_IMPLEMENTATION_TYPE_RACH(1),
.C_IMPLEMENTATION_TYPE_RDCH(1),
.C_IMPLEMENTATION_TYPE_WACH(1),
.C_IMPLEMENTATION_TYPE_WDCH(1),
.C_IMPLEMENTATION_TYPE_WRCH(1),
.C_INIT_WR_PNTR_VAL(0),
.C_INTERFACE_TYPE(0),
.C_MIF_FILE_NAME("BlankString"),
.C_MSGON_VAL(1),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(0),
.C_PRELOAD_REGS(1),
.C_PRIM_FIFO_TYPE("512x36"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_EMPTY_TYPE_AXIS(0),
.C_PROG_EMPTY_TYPE_RACH(0),
.C_PROG_EMPTY_TYPE_RDCH(0),
.C_PROG_EMPTY_TYPE_WACH(0),
.C_PROG_EMPTY_TYPE_WDCH(0),
.C_PROG_EMPTY_TYPE_WRCH(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(31),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
.C_PROG_FULL_THRESH_NEGATE_VAL(30),
.C_PROG_FULL_TYPE(0),
.C_PROG_FULL_TYPE_AXIS(0),
.C_PROG_FULL_TYPE_RACH(0),
.C_PROG_FULL_TYPE_RDCH(0),
.C_PROG_FULL_TYPE_WACH(0),
.C_PROG_FULL_TYPE_WDCH(0),
.C_PROG_FULL_TYPE_WRCH(0),
.C_RACH_TYPE(0),
.C_RDCH_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(6),
.C_RD_FREQ(1),
.C_REG_SLICE_MODE_AXIS(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_SYNCHRONIZER_STAGE(C_SYNCHRONIZER_STAGE),
.C_UNDERFLOW_LOW(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_USE_DOUT_RST(0),
.C_USE_ECC(0),
.C_USE_ECC_AXIS(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(1),
.C_VALID_LOW(0),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WRCH_TYPE(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(6),
.C_WR_DEPTH_AXIS(1024),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_RESPONSE_LATENCY(1)
)
fifo_gen_inst (
.clk(clk),
.din(wr_data),
.dout(rd_data),
.empty(empty),
.full(full),
.rd_clk(rd_clk),
.rd_en(rd_en),
.rst(rst),
.wr_clk(wr_clk),
.wr_en(wr_en),
.almost_empty(),
.almost_full(),
.axi_ar_data_count(),
.axi_ar_dbiterr(),
.axi_ar_injectdbiterr(1'b0),
.axi_ar_injectsbiterr(1'b0),
.axi_ar_overflow(),
.axi_ar_prog_empty(),
.axi_ar_prog_empty_thresh(4'b0),
.axi_ar_prog_full(),
.axi_ar_prog_full_thresh(4'b0),
.axi_ar_rd_data_count(),
.axi_ar_sbiterr(),
.axi_ar_underflow(),
.axi_ar_wr_data_count(),
.axi_aw_data_count(),
.axi_aw_dbiterr(),
.axi_aw_injectdbiterr(1'b0),
.axi_aw_injectsbiterr(1'b0),
.axi_aw_overflow(),
.axi_aw_prog_empty(),
.axi_aw_prog_empty_thresh(4'b0),
.axi_aw_prog_full(),
.axi_aw_prog_full_thresh(4'b0),
.axi_aw_rd_data_count(),
.axi_aw_sbiterr(),
.axi_aw_underflow(),
.axi_aw_wr_data_count(),
.axi_b_data_count(),
.axi_b_dbiterr(),
.axi_b_injectdbiterr(1'b0),
.axi_b_injectsbiterr(1'b0),
.axi_b_overflow(),
.axi_b_prog_empty(),
.axi_b_prog_empty_thresh(4'b0),
.axi_b_prog_full(),
.axi_b_prog_full_thresh(4'b0),
.axi_b_rd_data_count(),
.axi_b_sbiterr(),
.axi_b_underflow(),
.axi_b_wr_data_count(),
.axi_r_data_count(),
.axi_r_dbiterr(),
.axi_r_injectdbiterr(1'b0),
.axi_r_injectsbiterr(1'b0),
.axi_r_overflow(),
.axi_r_prog_empty(),
.axi_r_prog_empty_thresh(10'b0),
.axi_r_prog_full(),
.axi_r_prog_full_thresh(10'b0),
.axi_r_rd_data_count(),
.axi_r_sbiterr(),
.axi_r_underflow(),
.axi_r_wr_data_count(),
.axi_w_data_count(),
.axi_w_dbiterr(),
.axi_w_injectdbiterr(1'b0),
.axi_w_injectsbiterr(1'b0),
.axi_w_overflow(),
.axi_w_prog_empty(),
.axi_w_prog_empty_thresh(10'b0),
.axi_w_prog_full(),
.axi_w_prog_full_thresh(10'b0),
.axi_w_rd_data_count(),
.axi_w_sbiterr(),
.axi_w_underflow(),
.axi_w_wr_data_count(),
.axis_data_count(),
.axis_dbiterr(),
.axis_injectdbiterr(1'b0),
.axis_injectsbiterr(1'b0),
.axis_overflow(),
.axis_prog_empty(),
.axis_prog_empty_thresh(10'b0),
.axis_prog_full(),
.axis_prog_full_thresh(10'b0),
.axis_rd_data_count(),
.axis_sbiterr(),
.axis_underflow(),
.axis_wr_data_count(),
.backup(1'b0),
.backup_marker(1'b0),
.data_count(),
.dbiterr(),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.int_clk(1'b0),
.m_aclk(1'b0),
.m_aclk_en(1'b0),
.m_axi_araddr(),
.m_axi_arburst(),
.m_axi_arcache(),
.m_axi_arid(),
.m_axi_arlen(),
.m_axi_arlock(),
.m_axi_arprot(),
.m_axi_arqos(),
.m_axi_arready(1'b0),
.m_axi_arregion(),
.m_axi_arsize(),
.m_axi_aruser(),
.m_axi_arvalid(),
.m_axi_awaddr(),
.m_axi_awburst(),
.m_axi_awcache(),
.m_axi_awid(),
.m_axi_awlen(),
.m_axi_awlock(),
.m_axi_awprot(),
.m_axi_awqos(),
.m_axi_awready(1'b0),
.m_axi_awregion(),
.m_axi_awsize(),
.m_axi_awuser(),
.m_axi_awvalid(),
.m_axi_bid(4'b0),
.m_axi_bready(),
.m_axi_bresp(2'b0),
.m_axi_buser(1'b0),
.m_axi_bvalid(1'b0),
.m_axi_rdata(64'b0),
.m_axi_rid(4'b0),
.m_axi_rlast(1'b0),
.m_axi_rready(),
.m_axi_rresp(2'b0),
.m_axi_ruser(1'b0),
.m_axi_rvalid(1'b0),
.m_axi_wdata(),
.m_axi_wid(),
.m_axi_wlast(),
.m_axi_wready(1'b0),
.m_axi_wstrb(),
.m_axi_wuser(),
.m_axi_wvalid(),
.m_axis_tdata(),
.m_axis_tdest(),
.m_axis_tid(),
.m_axis_tkeep(),
.m_axis_tlast(),
.m_axis_tready(1'b0),
.m_axis_tstrb(),
.m_axis_tuser(),
.m_axis_tvalid(),
.overflow(),
.prog_empty(),
.prog_empty_thresh(5'b0),
.prog_empty_thresh_assert(5'b0),
.prog_empty_thresh_negate(5'b0),
.prog_full(),
.prog_full_thresh(5'b0),
.prog_full_thresh_assert(5'b0),
.prog_full_thresh_negate(5'b0),
.rd_data_count(),
.rd_rst(1'b0),
.s_aclk(1'b0),
.s_aclk_en(1'b0),
.s_aresetn(1'b0),
.s_axi_araddr(32'b0),
.s_axi_arburst(2'b0),
.s_axi_arcache(4'b0),
.s_axi_arid(4'b0),
.s_axi_arlen(8'b0),
.s_axi_arlock(2'b0),
.s_axi_arprot(3'b0),
.s_axi_arqos(4'b0),
.s_axi_arready(),
.s_axi_arregion(4'b0),
.s_axi_arsize(3'b0),
.s_axi_aruser(1'b0),
.s_axi_arvalid(1'b0),
.s_axi_awaddr(32'b0),
.s_axi_awburst(2'b0),
.s_axi_awcache(4'b0),
.s_axi_awid(4'b0),
.s_axi_awlen(8'b0),
.s_axi_awlock(2'b0),
.s_axi_awprot(3'b0),
.s_axi_awqos(4'b0),
.s_axi_awready(),
.s_axi_awregion(4'b0),
.s_axi_awsize(3'b0),
.s_axi_awuser(1'b0),
.s_axi_awvalid(1'b0),
.s_axi_bid(),
.s_axi_bready(1'b0),
.s_axi_bresp(),
.s_axi_buser(),
.s_axi_bvalid(),
.s_axi_rdata(),
.s_axi_rid(),
.s_axi_rlast(),
.s_axi_rready(1'b0),
.s_axi_rresp(),
.s_axi_ruser(),
.s_axi_rvalid(),
.s_axi_wdata(64'b0),
.s_axi_wid(4'b0),
.s_axi_wlast(1'b0),
.s_axi_wready(),
.s_axi_wstrb(8'b0),
.s_axi_wuser(1'b0),
.s_axi_wvalid(1'b0),
.s_axis_tdata(64'b0),
.s_axis_tdest(4'b0),
.s_axis_tid(8'b0),
.s_axis_tkeep(4'b0),
.s_axis_tlast(1'b0),
.s_axis_tready(),
.s_axis_tstrb(4'b0),
.s_axis_tuser(4'b0),
.s_axis_tvalid(1'b0),
.sbiterr(),
.srst(1'b0),
.underflow(),
.valid(),
.wr_ack(),
.wr_data_count(),
.wr_rst(1'b0),
.wr_rst_busy(),
.rd_rst_busy(),
.sleep(1'b0)
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:54:16 03/16/2014
// Design Name:
// Module Name: Core
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Core(
input clk,
input nrst,
output instr,
output IFID_instr,
output IDEX_instr,
output EXMEM_instr,
output MEMWB_instr,
//output reg[31:0] iaddr,
output daddr,
output dout,
output MEMWB_dout,
output wr,
output EXMEM_wr,
output pc,
output IFID_pc,
output IDEX_pc,
output EXMEM_pc,
output reg_din,
output reg_raddr1,
output reg_dout1,
output IDEX_reg_dout1,
output reg_raddr2,
output reg_dout2,
output IDEX_reg_dout2,
output EXMEM_reg_dout2,
output wr_reg,
output EXMEM_wr_reg,
output MEMWB_wr_reg,
output reg_wr_addr,
output ALUOut,
output EXMEM_ALUOut,
output MEMWB_ALUOut,
output ALUOp,
output ALUSrc,
output ALUIn2,
output MemToReg,
output EXMEM_MemToReg,
output MEMWB_MemToReg,
output RegDst,
output EXMEM_RegDst,
output MEMWB_RegDst,
output PCSrc,
output wire[31:0] ram1,
output wire[31:0] ram2,
output wire[31:0] ram3,
output Zero,
output Branch,
output Jump,
output M3_Select,
output M2_Select,
output M7_Select,
output F4F8,
output F2F6,
output F1F5,
output F3F7,
output F9,
output F10,
output IFID_RegisterRd,
output IFID_RegisterRt,
output IFID_RegisterRs,
output IDEX_RegisterRd,
output IDEX_RegisterRt,
output IDEX_RegisterRs,
output EXMEM_RegisterRd,
output EXMEM_RegisterRt,
output EXMEM_RegisterRs,
output MEMWB_RegisterRd,
output MEMWB_RegisterRt,
output MEMWB_RegisterRs
);
wire[31:0] instr;
reg[31:0] IFID_instr;
reg[31:0] IDEX_instr;
reg[31:0] EXMEM_instr;
reg[31:0] MEMWB_instr;
reg[5:0] daddr;
wire[31:0] dout;
reg[31:0] MEMWB_dout;
reg[3:0] wr;
reg[3:0] EXMEM_wr;
reg[31:0] pc;
reg[31:0] IFID_pc;
reg[31:0] IDEX_pc;
reg[31:0] EXMEM_pc;
wire[31:0] reg_din;
reg[4:0] reg_raddr1;
wire[31:0] reg_dout1;
reg[31:0] IDEX_reg_dout1;
reg[4:0] reg_raddr2;
wire[31:0] reg_dout2;
reg[31:0] IDEX_reg_dout2;
reg[31:0] EXMEM_reg_dout2;
reg wr_reg;
reg EXMEM_wr_reg;
reg MEMWB_wr_reg;
reg[4:0] reg_wr_addr;
reg[31:0] ALUOut;
reg[31:0] EXMEM_ALUOut;
reg[31:0] MEMWB_ALUOut;
reg[3:0] ALUOp;
reg ALUSrc;
reg[31:0] ALUIn2;
reg MemToReg;
reg EXMEM_MemToReg;
reg MEMWB_MemToReg;
reg RegDst;
reg EXMEM_RegDst;
reg MEMWB_RegDst;
reg PCSrc;
reg Zero;
reg Branch;
reg Jump;
wire[31:0] F10;
wire[31:0] F4F8;
wire[31:0] F2F6;
wire[31:0] F1F5;
wire[31:0] F3F7;
wire[31:0] F9;
reg[1:0] M3_Select;
reg[1:0] M2_Select;
reg M7_Select;
reg[4:0] IFID_RegisterRd;
reg[4:0] IFID_RegisterRt;
reg[4:0] IFID_RegisterRs;
reg[4:0] IDEX_RegisterRd;
reg[4:0] IDEX_RegisterRt;
reg[4:0] IDEX_RegisterRs;
reg[4:0] EXMEM_RegisterRd;
reg[4:0] EXMEM_RegisterRt;
reg[4:0] EXMEM_RegisterRs;
reg[4:0] MEMWB_RegisterRd;
reg[4:0] MEMWB_RegisterRt;
reg[4:0] MEMWB_RegisterRs;
//Wires & Regs definitions
//wire[31:0] instr; ->moved to module inputs for debug purposes
//reg[31:0] ALUOut;
//reg[3:0] ALUOp;
//reg ALUSrc;
reg Carry;
//reg RegDst;
//reg MemToReg;
//reg[31:0] ALUIn2;
wire[7:0] din[0:3];
//reg[7:0] pc = 8'b00000000;
//reg[31:0] immediate_extended;
reg[31:0] next_pc;
reg[31:0] j_pc;
reg[31:0] shifted_pc;
reg[4:0] shamt;
/*
reg[4:0] reg_raddr1;
wire[31:0] reg_dout1;
reg[4:0] reg_raddr2;
wire[31:0] reg_dout2;
wire wr_reg;
reg[4:0] reg_wr_addr;
reg[31:0] reg_din;
moved to module outputs for debug purposes
*/
wire nclk;
assign nclk = !(clk);
regfile registers(
clk,
reg_raddr1,
reg_dout1,
reg_raddr2,
reg_dout2,
MEMWB_wr_reg,
reg_wr_addr,
reg_din,
nrst,
ram1,
ram2,
ram3
);
//Memory instantiations
wire[31:0] dina; //not used since we don't write to imem
//wire[31:0] tmp_instr;
wire z;
assign z = 0;
IMem imem (
nclk, // input clka
z, // input [0 : 0] wea
pc[7:2], // input [5 : 0] addra
dina, // input [31 : 0] dina
instr // output [31 : 0] douta
);
DMem dmem_0 (
clk, // input clka
EXMEM_wr[0], // input [0 : 0] wea
daddr[5:0], // input [5 : 0] addra
EXMEM_reg_dout2[7:0], // input [7 : 0] dina
dout[7:0] // output [7 : 0] douta
);
DMem dmem_1 (
clk, // input clka
EXMEM_wr[1], // input [0 : 0] wea
daddr[5:0], // input [5 : 0] addra
EXMEM_reg_dout2[15:8], // input [7 : 0] dina
dout[15:8] // output [7 : 0] douta
);
DMem dmem_2 (
clk, // input clka
EXMEM_wr[2], // input [0 : 0] wea
daddr[5:0], // input [5 : 0] addra
EXMEM_reg_dout2[23:16], // input [7 : 0] dina
dout[23:16] // output [7 : 0] douta
);
DMem dmem_3 (
clk, // input clka
EXMEM_wr[3], // input [0 : 0] wea
daddr[5:0], // input [5 : 0] addra
EXMEM_reg_dout2[31:24], // input [7 : 0] dina
dout[31:24] // output [7 : 0] douta
);
reg[31:0] JDest;
reg JR;
always @*
begin
//PCSrc Mux & Jump
//4'b0000 because our memory real pc is 8 bits and 4 MSBs are always 0 in our case
JDest <= JR ? (IDEX_reg_dout1 << 2) : {4'b0000, IDEX_instr[25:0], 2'b00};
j_pc <= Jump ? JDest : pc + 32'b100;
shifted_pc <= (({{16{IDEX_instr[15]}}, IDEX_instr[15:0]}) << 2) + (IDEX_pc + 32'b100);
PCSrc <= Branch & Zero;
next_pc <= PCSrc ? shifted_pc : j_pc;
//RegDst Mux
reg_wr_addr <= MEMWB_RegDst ? MEMWB_instr[15:11] : MEMWB_instr[20:16];
reg_raddr1 <= IFID_instr[25:21];
reg_raddr2 <= IFID_instr[20:16];
IFID_RegisterRd <= IFID_instr[31:26] == 6'b001000 ? IFID_instr[20:16] : IFID_instr[15:11];//IFID_instr[31:26] == 6'b100011) ? IFID_instr[20:16] : IFID_instr[15:11]; //LW : else
IFID_RegisterRt <= IFID_instr[20:16];
IFID_RegisterRs <= IFID_instr[25:21];
//ALUSrc Mux
ALUIn2 <= ALUSrc ? {{16{IDEX_instr[15]}}, IDEX_instr[15:0]} : IDEX_reg_dout2; //sign extended
end
//MemToReg Mux
assign reg_din = MEMWB_MemToReg ? MEMWB_dout : MEMWB_ALUOut;
//Forwarding Wires
assign F4F8 = EXMEM_ALUOut;
assign F2F6 = EXMEM_ALUOut;
assign F1F5 = EXMEM_ALUOut;
assign F3F7 = EXMEM_ALUOut;
assign F9 = dout;
assign F10 = dout;
//PC
always @(posedge clk)
begin
if (~nrst)
begin
pc = 32'b0;
Branch <= 0;
Jump <= 0;
//ALUOut <= 32'b0;
end
else
begin
pc = next_pc;
end
end
//Decode
always @(posedge clk)
begin
if (IFID_instr[31:26] == 6'b001000)
ALUOp = 4'b0000;
case (IFID_instr[31:26])
6'b000000 :
begin
//func
case (IFID_instr[10:0])
11'b00000100000 : //Add
begin
ALUOp = 4'b0000;
end
11'b00000100100 : //And
begin
ALUOp = 4'b0001;
end
11'b00000100010 : //Sub
begin
ALUOp = 4'b0100;
end
11'b00000100101: // OR
begin
ALUOp = 4'b0010;
end
11'b00000100110: // XOR
begin
ALUOp = 4'b0111;
end
11'b00000011010, 11'b00000011011 : // Div, Divu
begin
ALUOp = 4'b0101;
end
11'b00000011000, 11'b00000011001 : // Mult, Multu
begin
ALUOp = 4'b0110;
end
default :
begin
/*case(IFID_instr[5:0])
6'b000000 : //SLL
begin
ALUOp = 4'b0011;
end
endcase*/
end
endcase
end
6'b001101 : //ORI
ALUOp = 4'b0010;
6'b001110 : //XORI
ALUOp = 4'b0111;
6'b001100 : //ANDI
ALUOp = 4'b0000;
6'b001000 , 6'b001001 :
ALUOp = 4'b0000; // ADDI
6'b000100, 6'b000001, 6'b000111, 6'b000110, 6'b000001, 6'b000101 : // BEQ, BGEZ, BGEZAL, BGTZ, BLEZ, BLTZ, BLTZAL, BNE
ALUOp = 4'b0100; // (uses Sub)
6'b100000 : // LB
ALUOp = 4'b0000;
6'b001111 : // LUI
ALUOp = 4'b0000;
6'b100011 : // LW
ALUOp = 4'b0000;
6'b101000 : // SB
ALUOp = 4'b0000;
6'b101011 : // SW
ALUOp = 4'b0000;
/*6'b000011 : //JAL (Save ret addr in $31) Needs Fix
begin
//reg_din <= pc + 3'b100;
//reg_wr_addr = 5'b11111;
wr_reg <= 1;
end*/
default :
//6'b000010 : // Jump
//Nothing (we don't need the alu)
;
endcase
end
//Control
always @(posedge clk)
begin
if (IFID_instr == 32'b0) //NOP
begin
wr_reg <= 0;
wr <= 4'b0000;
Branch <= 0;
Jump <= 0;
Branch <= 0;
end
else
begin
case (IFID_instr[31:26])
6'b000000 :
begin
//func
case (IFID_instr[10:0])
11'b00000100000, 11'b00000100001, 11'b00000100010, 00000100011, 11'b00000100100, 11'b00000100101, 11'b00000100110 : //Add, Addu, Sub, Subu , And, Or, XOR
/*(Note: ALL arithmetic immediate values are sign-extended. After that, they are handled as
signed or unsigned 32 bit numbers, depending upon the instruction. The only difference between
signed and unsigned instructions is that signed instructions can generate an overflow exception
and unsigned instructions can not. )
*/
begin
RegDst <= 1;
ALUSrc <= 0;
//reg_raddr1 <= instr[25:21];
//reg_raddr2 <= instr[20:16];
//reg_wr_addr <<= instr[15:11];
wr_reg <= 1;
MemToReg <= 0;
Branch <= 0;
Jump <= 0;
end
11'b00000000000 : //???????????????
case(IFID_instr[5:0])
6'b000000 : //SLL
begin
RegDst <= 1;
ALUSrc <= 0;
wr_reg <= 1;
MemToReg <= 0;
Branch <= 0;
Jump <= 0;
shamt <= IDEX_instr[10:6];
end
endcase
11'b00000001000 : //JR
if (IFID_instr[20:0] == 21'b1000)
begin
reg_raddr1 <= instr[25:21];
wr_reg <= 0;
wr <= 4'b0000;
Branch <= 0;
Jump <= 1;
//JR <= 1;
end
default:
;
endcase
end
6'b001000, 6'b001001, 6'b001100, 6'b001101, 6'b001101 : //Addi, Addiu, Andi, Ori, Xori
begin
RegDst <= 0;
ALUSrc <= 1; //immediate
//reg_wr_addr <= instr[20:16];
wr_reg <= 1;
MemToReg <= 0;
Branch <= 0;
Jump <= 0;
end
6'b000100 : //BEQ
begin
Branch <= 1;
Jump <= 0;
MemToReg <= 0;
wr_reg <= 0;
wr <= 0;
ALUSrc <= 0;
end
//======================= MEMORY ==========================
6'b100000 : // LB
begin
RegDst <= 0;
ALUSrc <= 1; // immediate
wr[0] <= 0;
wr[1] <= 0;
wr[2] <= 0;
wr[3] <= 0;
//daddr[5:0] <= ALUOut[5:0];
//reg_wr_addr <= instr[20:16];
wr_reg <= 1;
MemToReg <= 1;
PCSrc <= 0;
Branch <= 0;
Jump <= 0;
end
6'b100011 : // LW
begin
RegDst <= 0;
ALUSrc <= 1; //if i=2
wr[0] <= 0;
wr[1] <= 0;
wr[2] <= 0;
wr[3] <= 0;
//daddr[5:0] <= ALUOut[5:0];
//reg_wr_addr <= instr[20:16];
wr_reg <= 1;
MemToReg <= 1;
PCSrc <= 0;
Branch <= 0;
Jump <= 0;
end
6'b101000 : // SB
begin
ALUSrc <= 1; // immediate
wr[0] <= 1;
wr[1] <= 0;
wr[2] <= 0;
wr[3] <= 0;
reg_raddr2 <= IFID_instr[20:16];
wr_reg <= 0;
MemToReg <= 0;
PCSrc <= 0;
Branch <= 0;
Jump <= 0;
end
6'b101011 : // SW
begin
ALUSrc <= 1; // immediate
wr[0] <= 1;
wr[1] <= 1;
wr[2] <= 1;
wr[3] <= 1;
reg_raddr2 <= IFID_instr[20:16];
wr_reg <= 0;
MemToReg <= 0;
PCSrc <= 0;
Branch <= 0;
Jump <= 0;
end
6'b000010 : // Jump
begin
wr_reg <= 0;
wr <= 4'b0000;
Branch <= 0;
Jump <= 1;
JR <= 0;
end
/*6'b000011 : // JAL
begin
wr_reg <= 0;
wr <= 4'b0000;
Branch <= 0;
Jump <= 1;
JR <= 0;
end*/
default :
;
endcase
end
end
//Pipeline
always @(posedge clk)
begin
if (nrst)
begin
MEMWB_instr <= EXMEM_instr;
EXMEM_instr <= IDEX_instr;
IDEX_instr <= IFID_instr;
IFID_instr <= instr;
EXMEM_pc <= IDEX_pc;
IDEX_pc <= IFID_pc;
IFID_pc <= pc;
MEMWB_ALUOut <= EXMEM_ALUOut;
EXMEM_ALUOut <= ALUOut;
//Moved to forwarding mux
//IDEX_reg_dout1 <= reg_dout1;
//EXMEM_reg_dout2 <= IDEX_reg_dout2;
//IDEX_reg_dout2 <= reg_dout2;
MEMWB_wr_reg <= EXMEM_wr_reg;
EXMEM_wr_reg <= wr_reg;
MEMWB_MemToReg <= EXMEM_MemToReg;
EXMEM_MemToReg <= MemToReg;
MEMWB_RegDst <= EXMEM_RegDst;
EXMEM_RegDst <= RegDst;
daddr[5:0] <= ALUOut[5:0];
MEMWB_dout <= dout;
EXMEM_wr <= wr;
MEMWB_RegisterRd <= EXMEM_RegisterRd;
EXMEM_RegisterRd <= IDEX_RegisterRd;
IDEX_RegisterRd <= IFID_RegisterRd;
MEMWB_RegisterRt <= EXMEM_RegisterRt;
EXMEM_RegisterRt <= IDEX_RegisterRt;
IDEX_RegisterRt <= IFID_RegisterRt;
MEMWB_RegisterRs <= EXMEM_RegisterRs;
EXMEM_RegisterRs <= IDEX_RegisterRs;
IDEX_RegisterRs <= IFID_RegisterRs;
end
end
//Forwarding Multiplexers
always @(negedge clk)
begin
case (M3_Select)
2'b00 :
IDEX_reg_dout2 <= reg_dout2;
//2'b01 :
//IDEX_reg_dout2 <= F10;
2'b10 :
IDEX_reg_dout2 <= F4F8;
2'b11 :
IDEX_reg_dout2 <= F2F6;
default :
IDEX_reg_dout2 <= reg_dout2;
endcase
case (M2_Select)
2'b00 :
IDEX_reg_dout1 <= F1F5;
2'b01 :
IDEX_reg_dout1 <= F3F7;
2'b10 :
IDEX_reg_dout1 <= F9;
2'b11 :
IDEX_reg_dout1 <= reg_dout1;
default :
IDEX_reg_dout1 <= reg_dout1;
endcase
//M7_Select
EXMEM_reg_dout2 <= M7_Select ? F10 : IDEX_reg_dout2;
end
//Forwarding Unit
always @(*)
begin
M2_Select <= 2'b11;
M3_Select <= 2'b00;
M7_Select <= 0;
if ((MEMWB_RegisterRt == EXMEM_RegisterRt) && (MEMWB_instr[31:26] == 6'b100011))
M7_Select <= 1;
if (EXMEM_wr_reg && (EXMEM_RegisterRd != 0))
begin
if (EXMEM_RegisterRd == IDEX_RegisterRs)
//forward A
M2_Select <= 2'b00;
else
M2_Select <= 2'b11;
if (EXMEM_RegisterRd == IDEX_RegisterRt)
//forward B
M3_Select <= 2'b11;
else
M3_Select <= 2'b00;
end
if ((MEMWB_RegisterRt == IDEX_RegisterRs) && (MEMWB_instr[31:26] == 6'b100011))
M2_Select <= 2'b10;
if ((MEMWB_wr_reg && (MEMWB_RegisterRd != 0)) && !(EXMEM_wr_reg && (EXMEM_RegisterRd != 0) && ((EXMEM_RegisterRd == IDEX_RegisterRs))))
begin
if (MEMWB_RegisterRd == IDEX_RegisterRs)
//forward A
M2_Select <= 2'b01;
else
M2_Select <= 2'b11;
end
if ((MEMWB_wr_reg && (MEMWB_RegisterRd != 0)) && !(EXMEM_wr_reg && (EXMEM_RegisterRd != 0) && (EXMEM_RegisterRd == IDEX_RegisterRt)))
begin
if (MEMWB_RegisterRd == IDEX_RegisterRt)
//forward B
M3_Select <= 2'b10;
else
M3_Select <= 2'b00;
end
end
//ALU
//reg[32:0] tmp; //used in add, to compute carry
always @(*)
begin
/*
0000 : add/i/ui/u
0001 : and/i
0010 : or
0011 : sll
0100 : Sub/u
0101 : Div
0110 : Mult
0111 : xor/i
: sllv
: sra
: srl
: srlv
*/
case (ALUOp)
4'b0000 : //Add
begin
ALUOut <= ALUIn2 + IDEX_reg_dout1;
//tmp <= ALUIn2 + reg_dout1;
//ALUOut <= tmp[31:0];
//Carry = tmp[32];
//Set Carry flag if signed!
end
4'b0001 : //And
begin
ALUOut <= IDEX_reg_dout1 & ALUIn2;
end
4'b0010 : // OR
begin
ALUOut <= IDEX_reg_dout1 | ALUIn2;
end
4'b0011 : // SLL
begin
ALUOut <= ALUIn2 << shamt;
end
4'b0100 : // Sub
begin
ALUOut <= IDEX_reg_dout1 - ALUIn2;
Zero <= (ALUOut == 32'b0) ? 1 : 0;
end
/*4'b0101 : // Div, Divu
begin
HI <= reg_dout1 / ALUIn2;
LO <= reg_dout1 % ALUIn2;
end*/
/*4'b0110 : // Mult, Multu
begin
{HI, LO} <= reg_dout1 * ALUIn2;
end*/
4'b0111 : // Xor, Xori
begin
ALUOut <= IDEX_reg_dout1 ^ ALUIn2;
end
default :
;
endcase
end
endmodule
|
module valu
(
alu_source1_data,
alu_source2_data,
alu_source3_data,
alu_source_vcc_value,
alu_source_exec_value,
alu_control,
alu_start,
alu_vgpr_dest_data,
alu_sgpr_dest_data,
alu_dest_vcc_value,
alu_dest_exec_value,
valu_done,
clk,
rst
);
parameter MODULE = `MODULE_SIMD;
input [511:0] alu_source1_data;
input [511:0] alu_source2_data;
input [511:0] alu_source3_data;
input [15:0] alu_source_vcc_value;
input [15:0] alu_source_exec_value;
input [31:0] alu_control;
input alu_start;
output [511:0] alu_vgpr_dest_data;
output [15:0] alu_sgpr_dest_data;
output [15:0] alu_dest_vcc_value;
output [15:0] alu_dest_exec_value;
output valu_done;
input clk;
input rst;
wire [15:0] alu_done;
assign alu_dest_exec_value = alu_source_exec_value;
assign valu_done = (&(alu_done | (~alu_source_exec_value))) & (|alu_control);
generate
if (MODULE == `MODULE_SIMD)
simd_alu simd_alu[15:0]
(
.alu_source1_data(alu_source1_data),
.alu_source2_data(alu_source2_data),
.alu_source3_data(alu_source3_data),
.alu_source_vcc_value(alu_source_vcc_value),
.alu_source_exec_value(alu_source_exec_value),
.alu_control(alu_control),
.alu_start(alu_start),
.alu_vgpr_dest_data(alu_vgpr_dest_data),
.alu_sgpr_dest_data(alu_sgpr_dest_data),
.alu_dest_vcc_value(alu_dest_vcc_value),
.alu_done(alu_done),
.clk(clk),
.rst(rst)
);
else if (MODULE == `MODULE_SIMF)
simf_alu simf_alu[15:0]
(
.alu_source1_data(alu_source1_data),
.alu_source2_data(alu_source2_data),
.alu_source3_data(alu_source3_data),
.alu_source_vcc_value(alu_source_vcc_value),
.alu_source_exec_value(alu_source_exec_value),
.alu_control(alu_control),
.alu_start(alu_start),
.alu_vgpr_dest_data(alu_vgpr_dest_data),
.alu_sgpr_dest_data(alu_sgpr_dest_data),
.alu_dest_vcc_value(alu_dest_vcc_value),
.alu_done(alu_done),
.clk(clk),
.rst(rst)
);
endgenerate
endmodule
|
/*
Copyright 2015, Google Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
module sd_phy (
input wire clk_50,
input wire reset_n,
input wire sd_clk,
input wire sd_cmd_i,
output wire sd_cmd_o,
output wire sd_cmd_t,
input wire [3:0] sd_dat_i,
output wire [3:0] sd_dat_o,
output wire [3:0] sd_dat_t,
input wire [3:0] card_state,
output reg [47:0] cmd_in,
output reg cmd_in_crc_good,
output reg cmd_in_act,
input wire data_in_act,
output reg data_in_busy,
input wire data_in_another,
input wire data_in_stop,
output reg data_in_done,
output reg data_in_crc_good,
input wire [135:0] resp_out,
input wire [3:0] resp_type,
input wire resp_busy,
input wire resp_act,
output reg resp_done,
input wire mode_4bit,
input wire [511:0] data_out_reg,
input wire data_out_src,
input wire [9:0] data_out_len,
output reg data_out_busy,
input wire data_out_act,
input wire data_out_stop,
output reg data_out_done,
output wire bram_rd_sd_clk,
output reg [6:0] bram_rd_sd_addr,
output reg bram_rd_sd_wren,
output reg [31:0] bram_rd_sd_data,
input wire [31:0] bram_rd_sd_q,
output wire bram_wr_sd_clk,
output reg [6:0] bram_wr_sd_addr,
output reg bram_wr_sd_wren,
output reg [31:0] bram_wr_sd_data,
input wire [31:0] bram_wr_sd_q
,
output reg [10:0] odc,
output reg [6:0] ostate
);
`include "sd_params.vh"
`include "sd_const.vh"
assign bram_rd_sd_clk = sd_clk;
assign bram_wr_sd_clk = sd_clk;
reg sd_cmd_out;
reg sd_cmd_oe;
wire sd_cmd = sd_cmd_i;
//assign sd_cmd = sd_cmd_oe ? sd_cmd_out : 1'bZ;
assign sd_cmd_t = !sd_cmd_oe;
assign sd_cmd_o = sd_cmd_out;
// tristate data lines when card state is DISCONNECT
reg [3:0] sd_dat_out;
reg [3:0] sd_dat_oe;
wire [3:0] sd_dat = sd_dat_i;
/*
assign sd_dat[3] = (sd_dat_oe[3] && card_state_s != CARD_DIS) ? sd_dat_out[3] : 1'bZ;
assign sd_dat[2] = (sd_dat_oe[2] && card_state_s != CARD_DIS) ? sd_dat_out[2] : 1'bZ;
assign sd_dat[1] = (sd_dat_oe[1] && card_state_s != CARD_DIS) ? sd_dat_out[1] : 1'bZ;
assign sd_dat[0] = (sd_dat_oe[0] && card_state_s != CARD_DIS) ? sd_dat_out[0] : 1'bZ;
*/
assign sd_dat_o = sd_dat_out;
assign sd_dat_t = ~sd_dat_oe | {4{card_state_s == CARD_DIS}};
reg sd_cmd_last;
reg sd_dat_last;
reg [46:0] cmd_in_latch;
reg [135:0] resp_out_latch;
reg [6:0] crc7_in;
reg [6:0] crc7_out;
reg [512:0] data_out_reg_latch;
reg [15:0] crc16_out3, crc16_out2, crc16_out1, crc16_out0;
reg [15:0] crc16_in3, crc16_in2, crc16_in1, crc16_in0;
reg [15:0] crc16_check3, crc16_check2, crc16_check1, crc16_check0;
reg [10:0] idc;
//reg [10:0] odc;
reg [6:0] istate;
//reg [6:0] ostate;
parameter [6:0] ST_RESET = 'd0,
ST_RESET_WAIT = 'd1,
ST_IDLE = 'd4,
ST_CMD_CHECK = 'd10,
ST_CMD_READ = 'd11,
ST_RESP_PREAMBLE = 'd14,
ST_RESP_WRITE = 'd15,
ST_RESP_WRITE_END = 'd16,
ST_DATA_READ = 'd20,
ST_DATA_READ_1 = 'd21,
ST_DATA_READ_2 = 'd22,
ST_DATA_READ_3 = 'd23,
ST_DATA_TOKEN = 'd24,
ST_DATA_TOKEN_1 = 'd25,
ST_DATA_TOKEN_2 = 'd26,
ST_DATA_TOKEN_3 = 'd27,
ST_DATA_WRITE = 'd30,
ST_DATA_WRITE_1 = 'd31,
ST_DATA_WRITE_2 = 'd32,
ST_DATA_WRITE_3 = 'd33,
ST_LAST = 'd127;
reg [15:0] didc;
reg [15:0] dodc;
reg [6:0] distate;
reg [6:0] dostate;
reg [31:0] dout_buf;
wire [3:0] dout_4bit = data_out_src ? data_out_reg_latch[511:508] : dout_buf[31:28];
wire [0:0] dout_1bit = data_out_src ? data_out_reg_latch[511] : dout_buf[31];
reg do_crc_token;
// synchronizers
wire data_in_act_s, data_in_act_r;
wire data_in_stop_s;
wire data_in_another_s;
wire resp_act_s, resp_act_r;
wire [3:0] resp_type_s;
wire [9:0] data_out_len_s;
wire data_out_act_s, data_out_act_r;
wire data_out_stop_s;
wire [3:0] card_state_s;
wire mode_4bit_s;
synch_3 a(data_in_act, data_in_act_s, sd_clk, data_in_act_r);
synch_3 i(data_in_stop, data_in_stop_s, sd_clk);
synch_3 j(data_in_another, data_in_another_s, sd_clk);
synch_3 b(resp_act, resp_act_s, sd_clk, resp_act_r);
synch_3 #(4) c(resp_type, resp_type_s, sd_clk);
synch_3 #(10) d(data_out_len, data_out_len_s, sd_clk);
synch_3 e(data_out_act, data_out_act_s, sd_clk, data_out_act_r);
synch_3 f(data_out_stop, data_out_stop_s, sd_clk);
synch_3 #(4) g(card_state, card_state_s, sd_clk);
synch_3 h(mode_4bit, mode_4bit_s, sd_clk);
always @(posedge sd_clk or negedge reset_n) begin
if(~reset_n) begin
istate <= ST_RESET;
distate <= ST_RESET;
end else begin
sd_cmd_last <= sd_cmd;
sd_dat_last <= sd_dat[0];
// free running counter
idc <= idc + 1'b1;
//
// command input FSM
//
case(istate)
ST_RESET: begin
idc <= 0;
if(sd_cmd) istate <= ST_RESET_WAIT;
end
ST_RESET_WAIT: begin
// spec mandates that hosts send at least 74 clocks before any commands
// some hosts may send many more, some only a few (which violates spec)
if (idc == 60) istate <= ST_IDLE;
end
ST_IDLE: begin
// falling edge of CMD, and output state not driving
if((~sd_cmd & sd_cmd_last) & ~sd_cmd_oe) begin //~resp_act_s) begin
// start bit 0 of command
cmd_in_latch <= 0;
cmd_in_act <= 0;
crc7_in <= 0;
idc <= 0;
istate <= ST_CMD_READ;
end
end
ST_CMD_READ: begin
// shift in command
cmd_in_latch <= {cmd_in_latch[45:0], sd_cmd};
// advance CRC over first 40 bits
if(idc < 39) begin
crc7_in <= { crc7_in[5], crc7_in[4], crc7_in[3], crc7_in[2] ^ crc7_in[6] ^ sd_cmd,
crc7_in[1], crc7_in[0], sd_cmd ^ crc7_in[6] };
end
// after last bit of CRC
if(idc == 45) begin
istate <= ST_CMD_CHECK;
end
end
ST_CMD_CHECK: begin
// compare CRC7
cmd_in_crc_good <= ( cmd_in_latch[6:0] == crc7_in );
cmd_in <= {cmd_in_latch, sd_cmd};
cmd_in_act <= cmd_in_latch[45];
istate <= ST_IDLE;
end
ST_LAST: begin
end
default: istate <= ST_RESET;
endcase
//
// data input FSM
//
didc <= didc + 1'b1;
bram_wr_sd_wren <= 0;
case(distate)
ST_RESET: begin
do_crc_token <= 0;
distate <= ST_IDLE;
end
ST_IDLE: begin
if(data_in_act_r | (data_in_another_s & ~data_in_stop_s)) begin
data_in_busy <= 1;
data_in_done <= 0;
distate <= ST_DATA_READ;
end
end
ST_DATA_READ: begin
// falling edge of DAT0, and output state not driving
if((~sd_dat[0] & sd_dat_last) & ~sd_dat_oe[0]) begin
// start bit 0 of data packet
crc16_in3 <= 0;
crc16_in2 <= 0;
crc16_in1 <= 0;
crc16_in0 <= 0;
didc <= 0;
bram_wr_sd_addr <= -1;
distate <= ST_DATA_READ_1;
end
if(data_in_stop_s) begin
data_in_done <= 1;
distate <= ST_DATA_READ_3;
end
end
ST_DATA_READ_1: begin
// shift in data
if(mode_4bit_s) begin
bram_wr_sd_data <= {bram_wr_sd_data[27:0], sd_dat};
crc16_in3 <= {crc16_in3[14:0], 1'b0} ^ ((sd_dat[3] ^ crc16_in3[15]) ? 16'h1021 : 16'h0);
crc16_in2 <= {crc16_in2[14:0], 1'b0} ^ ((sd_dat[2] ^ crc16_in2[15]) ? 16'h1021 : 16'h0);
crc16_in1 <= {crc16_in1[14:0], 1'b0} ^ ((sd_dat[1] ^ crc16_in1[15]) ? 16'h1021 : 16'h0);
crc16_in0 <= {crc16_in0[14:0], 1'b0} ^ ((sd_dat[0] ^ crc16_in0[15]) ? 16'h1021 : 16'h0);
if(didc[2:0] == 3'd0) bram_wr_sd_addr <= bram_wr_sd_addr + 1'b1;
if(didc[2:0] == 3'd7) bram_wr_sd_wren <= 1;
end else begin
bram_wr_sd_data <= {bram_wr_sd_data[31:0], sd_dat[0]};
crc16_in0 <= {crc16_in0[14:0], 1'b0} ^ ((sd_dat[0] ^ crc16_in0[15]) ? 16'h1021 : 16'h0);
if(didc[4:0] == 5'd0) bram_wr_sd_addr <= bram_wr_sd_addr + 1'b1;
if(didc[4:0] == 5'd31) bram_wr_sd_wren <= 1;
end
if((mode_4bit_s ? (didc+1) >> 1 : (didc+1) >> 3) == 512) begin
// end, read crc
didc <= 0;
distate <= ST_DATA_READ_2;
end
if(data_in_stop_s) begin
data_in_done <= 1;
distate <= ST_DATA_READ_3;
end
end
ST_DATA_READ_2: begin
// shift in CRC16
crc16_check3[15:0] <= {crc16_check3[14:0], sd_dat[3]};
crc16_check2[15:0] <= {crc16_check2[14:0], sd_dat[2]};
crc16_check1[15:0] <= {crc16_check1[14:0], sd_dat[1]};
crc16_check0[15:0] <= {crc16_check0[14:0], sd_dat[0]};
if(didc == 16 || data_in_stop_s) begin
// end, including 1 stop bit
data_in_done <= 1;
if( {crc16_check3, crc16_check2, crc16_check1, crc16_check0} ==
{crc16_in3, crc16_in2, crc16_in1, crc16_in0} ) begin
data_in_crc_good <= 1;
end else data_in_crc_good <= 0;
didc <= 0;
distate <= ST_DATA_READ_3;
// if STOP sent, do not send CRC token, just busy signal
do_crc_token <= ~data_in_stop_s;
end
end
ST_DATA_READ_3: begin
// after telling link we're done, wait for it to respond
if(~data_in_act_s) begin
do_crc_token <= 0;
data_in_busy <= 0;
distate <= ST_IDLE;
end
end
default: distate <= ST_RESET;
endcase
end
end
always @(negedge sd_clk or negedge reset_n) begin
if(~reset_n) begin
ostate <= ST_RESET;
dostate <= ST_RESET;
end else begin
// free running counter
odc <= odc + 1'b1;
//
// command output FSM
//
case(ostate)
ST_RESET: begin
resp_done <= 0;
sd_cmd_oe <= 0;
ostate <= ST_IDLE;
end
ST_IDLE: begin
if(resp_act_r) begin
resp_done <= 0;
resp_out_latch <= resp_out;
crc7_out <= 0;
ostate <= ST_RESP_PREAMBLE;
end
end
ST_RESP_PREAMBLE: begin
// to meet exact 5 cycle requirement between command and response for CMD2/ACMD41
odc <= 0;
ostate <= ST_RESP_WRITE;
end
ST_RESP_WRITE: begin
sd_cmd_oe <= 1;
sd_cmd_out <= resp_out_latch[135];
crc7_out <= { crc7_out[5], crc7_out[4], crc7_out[3], crc7_out[2] ^ crc7_out[6] ^ resp_out_latch[135],
crc7_out[1], crc7_out[0], resp_out_latch[135] ^ crc7_out[6] };
resp_out_latch <= {resp_out_latch[134:0], 1'b1};
case(resp_type_s)
RESP_R1, RESP_R1B, RESP_R3, RESP_R6, RESP_R7: begin
// 48 bit codes
if(resp_type_s == RESP_R3) begin
// fix R3 CRC to 1's
crc7_out <= 7'b1111111;
end
if(odc >= 40) begin
crc7_out <= {crc7_out[5:0], 1'b1};
sd_cmd_out <= crc7_out[6];
end
if(odc == 47) ostate <= ST_RESP_WRITE_END;
end
RESP_R2: begin
// 136 bit codes
// only CRC over the last 128 bits
if(odc < 8) crc7_out <= 0;
if(odc >= 128) begin
crc7_out <= {crc7_out[5:0], 1'b1};
sd_cmd_out <= crc7_out[6];
end
if(odc == 135) ostate <= ST_RESP_WRITE_END;
end
endcase
end
ST_RESP_WRITE_END: begin
sd_cmd_oe <= 0;
resp_done <= 1;
ostate <= ST_IDLE;
end
default: ostate <= ST_RESET;
endcase
dodc <= dodc + 1'b1;
bram_rd_sd_wren <= 0;
//
// data output FSM
//
case(dostate)
ST_RESET: begin
sd_dat_oe <= 4'b0;
data_out_busy <= 0;
data_out_done <= 0;
dostate <= ST_IDLE;
end
ST_IDLE: begin
dodc <= 0;
sd_dat_oe <= 4'b0;
if(data_out_act_r) begin
// start sending data packet
data_out_busy <= 1;
data_out_done <= 0;
bram_rd_sd_addr <= 0;
dostate <= ST_DATA_WRITE;
end else
if(do_crc_token) begin
// send data CRC token, busy signal for written blocks
dostate <= ST_DATA_TOKEN;
end
end
ST_DATA_WRITE: begin
// delay start of output
if(dodc == 0) begin // 0: no delay
dodc <= 0;
// enable which data lines will be driven
sd_dat_oe <= mode_4bit_s ? 4'b1111 : 4'b0001;
sd_dat_out <= 4'b0;
dostate <= ST_DATA_WRITE_1;
end
crc16_out3 <= 16'h0;
crc16_out2 <= 16'h0;
crc16_out1 <= 16'h0;
crc16_out0 <= 16'h0;
// preload bram Q data
dout_buf <= bram_rd_sd_q;
data_out_reg_latch <= data_out_reg;
end
ST_DATA_WRITE_1: begin
if(mode_4bit_s) begin
sd_dat_out <= dout_4bit;
crc16_out3 <= {crc16_out3[14:0], 1'b0} ^ ((dout_4bit[3] ^ crc16_out3[15]) ? 16'h1021 : 16'h0);
crc16_out2 <= {crc16_out2[14:0], 1'b0} ^ ((dout_4bit[2] ^ crc16_out2[15]) ? 16'h1021 : 16'h0);
crc16_out1 <= {crc16_out1[14:0], 1'b0} ^ ((dout_4bit[1] ^ crc16_out1[15]) ? 16'h1021 : 16'h0);
crc16_out0 <= {crc16_out0[14:0], 1'b0} ^ ((dout_4bit[0] ^ crc16_out0[15]) ? 16'h1021 : 16'h0);
data_out_reg_latch[511:0] <= {data_out_reg_latch[507:0], 4'b0};
dout_buf[31:0] <= {dout_buf[27:0], 4'b0};
// advance thru 32bit bram output word
if(dodc[2:0] == 3'd0) bram_rd_sd_addr <= bram_rd_sd_addr + 1'b1;
if(dodc[2:0] == 3'd7) dout_buf <= bram_rd_sd_q;
end else begin
sd_dat_out[0] <= dout_1bit;
crc16_out0 <= {crc16_out0[14:0], 1'b0} ^ ((dout_1bit[0] ^ crc16_out0[15]) ? 16'h1021 : 16'h0);
data_out_reg_latch[511:0] <= {data_out_reg_latch[510:0], 1'b0};
dout_buf[31:0] <= {dout_buf[30:0], 1'b0};
// advance thru 32bit bram output word
if(dodc[4:0] == 5'd0) bram_rd_sd_addr <= bram_rd_sd_addr + 1'b1;
if(dodc[4:0] == 5'd31) dout_buf <= bram_rd_sd_q;
end
if((mode_4bit_s ? (dodc+1) >> 1 : (dodc+1) >> 3) == data_out_len_s) begin
// end, dump crc
dodc <= 0;
dostate <= ST_DATA_WRITE_2;
end
if(data_out_stop_s) begin
sd_dat_out <= 4'hF;
data_out_done <= 1;
dostate <= ST_DATA_WRITE_3;
end
end
ST_DATA_WRITE_2: begin
sd_dat_out[3] <= crc16_out3[15];
sd_dat_out[2] <= crc16_out2[15];
sd_dat_out[1] <= crc16_out1[15];
sd_dat_out[0] <= crc16_out0[15];
crc16_out3[15:0] <= {crc16_out3[14:0], 1'b1};
crc16_out2[15:0] <= {crc16_out2[14:0], 1'b1};
crc16_out1[15:0] <= {crc16_out1[14:0], 1'b1};
crc16_out0[15:0] <= {crc16_out0[14:0], 1'b1};
if(dodc == 16 || data_out_stop_s) begin
// end, including 1 stop bit
data_out_done <= 1;
dostate <= ST_DATA_WRITE_3;
end
end
ST_DATA_WRITE_3: begin
if(~data_out_act_s) begin
// let link know we are able to detect ACT's next rising edge
// due to extreme differences in clock rates
data_out_busy <= 0;
dostate <= ST_IDLE;
end
end
ST_DATA_TOKEN: begin
// send CRC token
case(dodc)
1: begin
sd_dat_oe[0] <= 1;
sd_dat_out[0] <= 0; // start bit
end
2: sd_dat_out[0] <= ~data_in_crc_good;
3: sd_dat_out[0] <= data_in_crc_good;
4: sd_dat_out[0] <= ~data_in_crc_good;
5: sd_dat_out[0] <= 1; // stop/end bit
6: begin
sd_dat_out[0] <= 0; // start bit of busy
dostate <= ST_DATA_TOKEN_1;
end
endcase
end
ST_DATA_TOKEN_1: begin
// busy signal until data sink deasserts ACT
sd_dat_oe[0] <= 1;
sd_dat_out[0] <= 0;
if(~data_in_act_s) begin
// drive stop bit high
sd_dat_oe[0] <= 1;
sd_dat_out[0] <= 1;
dostate <= ST_DATA_TOKEN_2;
end
end
ST_DATA_TOKEN_2: begin
sd_dat_oe[0] <= 0;
dostate <= ST_IDLE;
end
default: dostate <= ST_RESET;
endcase
// for snooping real cards
// sd_dat_oe <= 4'b0;
// sd_cmd_oe <= 1'b0;
end
end
endmodule
|
//#############################################################################
//# Purpose: Device under test wrapper for toy accelerator example #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see below) #
//#############################################################################
module dut(/*AUTOARG*/
// Outputs
dut_active, clkout, wait_out, access_out, packet_out,
// Inputs
clk1, clk2, nreset, vdd, vss, access_in, packet_in, wait_in
);
//##########################################################################
//# INTERFACE
//##########################################################################
parameter AW = 32;
parameter ID = 12'h810;
parameter S_IDW = 12;
parameter M_IDW = 6;
parameter PW = 2*AW + 40;
parameter N = 1;
//clock,reset
input clk1;
input clk2;
input nreset;
input [N*N-1:0] vdd;
input vss;
output dut_active;
output clkout;
//Stimulus Driven Transaction
input [N-1:0] access_in;
input [N*PW-1:0] packet_in;
output [N-1:0] wait_out;
//DUT driven transaction
output [N-1:0] access_out;
output [N*PW-1:0] packet_out;
input [N-1:0] wait_in;
//##########################################################################
//#BODY
//##########################################################################
wire mem_rd_wait;
wire mem_wr_wait;
wire mem_access;
wire [PW-1:0] mem_packet;
/*AUTOINPUT*/
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire irq; // From axi_accelerator of axi_accelerator.v
wire [31:0] m_axi_araddr; // From axi_accelerator of axi_accelerator.v
wire [1:0] m_axi_arburst; // From axi_accelerator of axi_accelerator.v
wire [3:0] m_axi_arcache; // From axi_accelerator of axi_accelerator.v
wire [M_IDW-1:0] m_axi_arid; // From axi_accelerator of axi_accelerator.v
wire [7:0] m_axi_arlen; // From axi_accelerator of axi_accelerator.v
wire m_axi_arlock; // From axi_accelerator of axi_accelerator.v
wire [2:0] m_axi_arprot; // From axi_accelerator of axi_accelerator.v
wire [3:0] m_axi_arqos; // From axi_accelerator of axi_accelerator.v
wire m_axi_arready; // From m_stub of axislave_stub.v
wire [2:0] m_axi_arsize; // From axi_accelerator of axi_accelerator.v
wire m_axi_arvalid; // From axi_accelerator of axi_accelerator.v
wire [31:0] m_axi_awaddr; // From axi_accelerator of axi_accelerator.v
wire [1:0] m_axi_awburst; // From axi_accelerator of axi_accelerator.v
wire [3:0] m_axi_awcache; // From axi_accelerator of axi_accelerator.v
wire [M_IDW-1:0] m_axi_awid; // From axi_accelerator of axi_accelerator.v
wire [7:0] m_axi_awlen; // From axi_accelerator of axi_accelerator.v
wire m_axi_awlock; // From axi_accelerator of axi_accelerator.v
wire [2:0] m_axi_awprot; // From axi_accelerator of axi_accelerator.v
wire [3:0] m_axi_awqos; // From axi_accelerator of axi_accelerator.v
wire m_axi_awready; // From m_stub of axislave_stub.v
wire [2:0] m_axi_awsize; // From axi_accelerator of axi_accelerator.v
wire m_axi_awvalid; // From axi_accelerator of axi_accelerator.v
wire [S_IDW-1:0] m_axi_bid; // From m_stub of axislave_stub.v
wire m_axi_bready; // From axi_accelerator of axi_accelerator.v
wire [1:0] m_axi_bresp; // From m_stub of axislave_stub.v
wire m_axi_bvalid; // From m_stub of axislave_stub.v
wire [31:0] m_axi_rdata; // From m_stub of axislave_stub.v
wire [S_IDW-1:0] m_axi_rid; // From m_stub of axislave_stub.v
wire m_axi_rlast; // From m_stub of axislave_stub.v
wire m_axi_rready; // From axi_accelerator of axi_accelerator.v
wire [1:0] m_axi_rresp; // From m_stub of axislave_stub.v
wire m_axi_rvalid; // From m_stub of axislave_stub.v
wire [63:0] m_axi_wdata; // From axi_accelerator of axi_accelerator.v
wire [M_IDW-1:0] m_axi_wid; // From axi_accelerator of axi_accelerator.v
wire m_axi_wlast; // From axi_accelerator of axi_accelerator.v
wire m_axi_wready; // From m_stub of axislave_stub.v
wire [7:0] m_axi_wstrb; // From axi_accelerator of axi_accelerator.v
wire m_axi_wvalid; // From axi_accelerator of axi_accelerator.v
wire [31:0] s_axi_araddr; // From emaxi of emaxi.v
wire [1:0] s_axi_arburst; // From emaxi of emaxi.v
wire [3:0] s_axi_arcache; // From emaxi of emaxi.v
wire [M_IDW-1:0] s_axi_arid; // From emaxi of emaxi.v
wire [7:0] s_axi_arlen; // From emaxi of emaxi.v
wire s_axi_arlock; // From emaxi of emaxi.v
wire [2:0] s_axi_arprot; // From emaxi of emaxi.v
wire [3:0] s_axi_arqos; // From emaxi of emaxi.v
wire s_axi_arready; // From axi_accelerator of axi_accelerator.v
wire [2:0] s_axi_arsize; // From emaxi of emaxi.v
wire s_axi_arvalid; // From emaxi of emaxi.v
wire [31:0] s_axi_awaddr; // From emaxi of emaxi.v
wire [1:0] s_axi_awburst; // From emaxi of emaxi.v
wire [3:0] s_axi_awcache; // From emaxi of emaxi.v
wire [M_IDW-1:0] s_axi_awid; // From emaxi of emaxi.v
wire [7:0] s_axi_awlen; // From emaxi of emaxi.v
wire s_axi_awlock; // From emaxi of emaxi.v
wire [2:0] s_axi_awprot; // From emaxi of emaxi.v
wire [3:0] s_axi_awqos; // From emaxi of emaxi.v
wire s_axi_awready; // From axi_accelerator of axi_accelerator.v
wire [2:0] s_axi_awsize; // From emaxi of emaxi.v
wire s_axi_awvalid; // From emaxi of emaxi.v
wire [S_IDW-1:0] s_axi_bid; // From axi_accelerator of axi_accelerator.v
wire s_axi_bready; // From emaxi of emaxi.v
wire [1:0] s_axi_bresp; // From axi_accelerator of axi_accelerator.v
wire s_axi_bvalid; // From axi_accelerator of axi_accelerator.v
wire [31:0] s_axi_rdata; // From axi_accelerator of axi_accelerator.v
wire [S_IDW-1:0] s_axi_rid; // From axi_accelerator of axi_accelerator.v
wire s_axi_rlast; // From axi_accelerator of axi_accelerator.v
wire s_axi_rready; // From emaxi of emaxi.v
wire [1:0] s_axi_rresp; // From axi_accelerator of axi_accelerator.v
wire s_axi_rvalid; // From axi_accelerator of axi_accelerator.v
wire [63:0] s_axi_wdata; // From emaxi of emaxi.v
wire [M_IDW-1:0] s_axi_wid; // From emaxi of emaxi.v
wire s_axi_wlast; // From emaxi of emaxi.v
wire s_axi_wready; // From axi_accelerator of axi_accelerator.v
wire [7:0] s_axi_wstrb; // From emaxi of emaxi.v
wire s_axi_wvalid; // From emaxi of emaxi.v
// End of automatics
assign clkout = clk1;
assign dut_active = 1'b1;
//######################################################################
//ACCELERATOR
//######################################################################
axi_accelerator
axi_accelerator (.sys_nreset (nreset),
.sys_clk (clk1),
.m_axi_aresetn (nreset),
.s_axi_aresetn (nreset),
.s_axi_wstrb (s_axi_wstrb[7:4] | s_axi_wstrb[3:0]),
/*AUTOINST*/
// Outputs
.irq (irq),
.m_axi_awid (m_axi_awid[M_IDW-1:0]),
.m_axi_awaddr (m_axi_awaddr[31:0]),
.m_axi_awlen (m_axi_awlen[7:0]),
.m_axi_awsize (m_axi_awsize[2:0]),
.m_axi_awburst (m_axi_awburst[1:0]),
.m_axi_awlock (m_axi_awlock),
.m_axi_awcache (m_axi_awcache[3:0]),
.m_axi_awprot (m_axi_awprot[2:0]),
.m_axi_awqos (m_axi_awqos[3:0]),
.m_axi_awvalid (m_axi_awvalid),
.m_axi_wid (m_axi_wid[M_IDW-1:0]),
.m_axi_wdata (m_axi_wdata[63:0]),
.m_axi_wstrb (m_axi_wstrb[7:0]),
.m_axi_wlast (m_axi_wlast),
.m_axi_wvalid (m_axi_wvalid),
.m_axi_bready (m_axi_bready),
.m_axi_arid (m_axi_arid[M_IDW-1:0]),
.m_axi_araddr (m_axi_araddr[31:0]),
.m_axi_arlen (m_axi_arlen[7:0]),
.m_axi_arsize (m_axi_arsize[2:0]),
.m_axi_arburst (m_axi_arburst[1:0]),
.m_axi_arlock (m_axi_arlock),
.m_axi_arcache (m_axi_arcache[3:0]),
.m_axi_arprot (m_axi_arprot[2:0]),
.m_axi_arqos (m_axi_arqos[3:0]),
.m_axi_arvalid (m_axi_arvalid),
.m_axi_rready (m_axi_rready),
.s_axi_arready (s_axi_arready),
.s_axi_awready (s_axi_awready),
.s_axi_bid (s_axi_bid[S_IDW-1:0]),
.s_axi_bresp (s_axi_bresp[1:0]),
.s_axi_bvalid (s_axi_bvalid),
.s_axi_rid (s_axi_rid[S_IDW-1:0]),
.s_axi_rdata (s_axi_rdata[31:0]),
.s_axi_rlast (s_axi_rlast),
.s_axi_rresp (s_axi_rresp[1:0]),
.s_axi_rvalid (s_axi_rvalid),
.s_axi_wready (s_axi_wready),
// Inputs
.m_axi_awready (m_axi_awready),
.m_axi_wready (m_axi_wready),
.m_axi_bid (m_axi_bid[M_IDW-1:0]),
.m_axi_bresp (m_axi_bresp[1:0]),
.m_axi_bvalid (m_axi_bvalid),
.m_axi_arready (m_axi_arready),
.m_axi_rid (m_axi_rid[M_IDW-1:0]),
.m_axi_rdata (m_axi_rdata[63:0]),
.m_axi_rresp (m_axi_rresp[1:0]),
.m_axi_rlast (m_axi_rlast),
.m_axi_rvalid (m_axi_rvalid),
.s_axi_arid (s_axi_arid[S_IDW-1:0]),
.s_axi_araddr (s_axi_araddr[31:0]),
.s_axi_arburst (s_axi_arburst[1:0]),
.s_axi_arcache (s_axi_arcache[3:0]),
.s_axi_arlock (s_axi_arlock),
.s_axi_arlen (s_axi_arlen[7:0]),
.s_axi_arprot (s_axi_arprot[2:0]),
.s_axi_arqos (s_axi_arqos[3:0]),
.s_axi_arsize (s_axi_arsize[2:0]),
.s_axi_arvalid (s_axi_arvalid),
.s_axi_awid (s_axi_awid[S_IDW-1:0]),
.s_axi_awaddr (s_axi_awaddr[31:0]),
.s_axi_awburst (s_axi_awburst[1:0]),
.s_axi_awcache (s_axi_awcache[3:0]),
.s_axi_awlock (s_axi_awlock),
.s_axi_awlen (s_axi_awlen[7:0]),
.s_axi_awprot (s_axi_awprot[2:0]),
.s_axi_awqos (s_axi_awqos[3:0]),
.s_axi_awsize (s_axi_awsize[2:0]),
.s_axi_awvalid (s_axi_awvalid),
.s_axi_bready (s_axi_bready),
.s_axi_rready (s_axi_rready),
.s_axi_wid (s_axi_wid[S_IDW-1:0]),
.s_axi_wdata (s_axi_wdata[31:0]),
.s_axi_wlast (s_axi_wlast),
.s_axi_wvalid (s_axi_wvalid));
//######################################################################
//AXI MASTER
//######################################################################
//Split stimulus to read/write
assign wait_out = wr_wait | rd_wait;
assign write_in = access_in & packet_in[0];
assign read_in = access_in & ~packet_in[0];
/*emaxi AUTO_TEMPLATE (.m_\(.*\) (s_\1[]),
);
*/
emaxi #(.M_IDW(M_IDW))
emaxi (.m_axi_aclk (clk1),
.m_axi_aresetn (nreset),
.m_axi_rdata ({s_axi_rdata[31:0],s_axi_rdata[31:0]}),
.rr_wait (wait_in),
.rr_access (access_out),
.rr_packet (packet_out[PW-1:0]),
.wr_wait (wr_wait),
.wr_access (write_in),
.wr_packet (packet_in[PW-1:0]),
.rd_wait (rd_wait),
.rd_access (read_in),
.rd_packet (packet_in[PW-1:0]),
/*AUTOINST*/
// Outputs
.m_axi_awid (s_axi_awid[M_IDW-1:0]), // Templated
.m_axi_awaddr (s_axi_awaddr[31:0]), // Templated
.m_axi_awlen (s_axi_awlen[7:0]), // Templated
.m_axi_awsize (s_axi_awsize[2:0]), // Templated
.m_axi_awburst (s_axi_awburst[1:0]), // Templated
.m_axi_awlock (s_axi_awlock), // Templated
.m_axi_awcache (s_axi_awcache[3:0]), // Templated
.m_axi_awprot (s_axi_awprot[2:0]), // Templated
.m_axi_awqos (s_axi_awqos[3:0]), // Templated
.m_axi_awvalid (s_axi_awvalid), // Templated
.m_axi_wid (s_axi_wid[M_IDW-1:0]), // Templated
.m_axi_wdata (s_axi_wdata[63:0]), // Templated
.m_axi_wstrb (s_axi_wstrb[7:0]), // Templated
.m_axi_wlast (s_axi_wlast), // Templated
.m_axi_wvalid (s_axi_wvalid), // Templated
.m_axi_bready (s_axi_bready), // Templated
.m_axi_arid (s_axi_arid[M_IDW-1:0]), // Templated
.m_axi_araddr (s_axi_araddr[31:0]), // Templated
.m_axi_arlen (s_axi_arlen[7:0]), // Templated
.m_axi_arsize (s_axi_arsize[2:0]), // Templated
.m_axi_arburst (s_axi_arburst[1:0]), // Templated
.m_axi_arlock (s_axi_arlock), // Templated
.m_axi_arcache (s_axi_arcache[3:0]), // Templated
.m_axi_arprot (s_axi_arprot[2:0]), // Templated
.m_axi_arqos (s_axi_arqos[3:0]), // Templated
.m_axi_arvalid (s_axi_arvalid), // Templated
.m_axi_rready (s_axi_rready), // Templated
// Inputs
.m_axi_awready (s_axi_awready), // Templated
.m_axi_wready (s_axi_wready), // Templated
.m_axi_bid (s_axi_bid[M_IDW-1:0]), // Templated
.m_axi_bresp (s_axi_bresp[1:0]), // Templated
.m_axi_bvalid (s_axi_bvalid), // Templated
.m_axi_arready (s_axi_arready), // Templated
.m_axi_rid (s_axi_rid[M_IDW-1:0]), // Templated
.m_axi_rresp (s_axi_rresp[1:0]), // Templated
.m_axi_rlast (s_axi_rlast), // Templated
.m_axi_rvalid (s_axi_rvalid)); // Templated
//Tie off master output for now
/*axislave_stub AUTO_TEMPLATE (.s_\(.*\) (m_\1[]),
);
*/
axislave_stub m_stub (.s_axi_aclk (clk1),
.s_axi_aresetn (nreset),
/*AUTOINST*/
// Outputs
.s_axi_arready (m_axi_arready), // Templated
.s_axi_awready (m_axi_awready), // Templated
.s_axi_bid (m_axi_bid[S_IDW-1:0]), // Templated
.s_axi_bresp (m_axi_bresp[1:0]), // Templated
.s_axi_bvalid (m_axi_bvalid), // Templated
.s_axi_rid (m_axi_rid[S_IDW-1:0]), // Templated
.s_axi_rdata (m_axi_rdata[31:0]), // Templated
.s_axi_rlast (m_axi_rlast), // Templated
.s_axi_rresp (m_axi_rresp[1:0]), // Templated
.s_axi_rvalid (m_axi_rvalid), // Templated
.s_axi_wready (m_axi_wready), // Templated
// Inputs
.s_axi_arid (m_axi_arid[S_IDW-1:0]), // Templated
.s_axi_araddr (m_axi_araddr[31:0]), // Templated
.s_axi_arburst (m_axi_arburst[1:0]), // Templated
.s_axi_arcache (m_axi_arcache[3:0]), // Templated
.s_axi_arlock (m_axi_arlock), // Templated
.s_axi_arlen (m_axi_arlen[7:0]), // Templated
.s_axi_arprot (m_axi_arprot[2:0]), // Templated
.s_axi_arqos (m_axi_arqos[3:0]), // Templated
.s_axi_arsize (m_axi_arsize[2:0]), // Templated
.s_axi_arvalid (m_axi_arvalid), // Templated
.s_axi_awid (m_axi_awid[S_IDW-1:0]), // Templated
.s_axi_awaddr (m_axi_awaddr[31:0]), // Templated
.s_axi_awburst (m_axi_awburst[1:0]), // Templated
.s_axi_awcache (m_axi_awcache[3:0]), // Templated
.s_axi_awlock (m_axi_awlock), // Templated
.s_axi_awlen (m_axi_awlen[7:0]), // Templated
.s_axi_awprot (m_axi_awprot[2:0]), // Templated
.s_axi_awqos (m_axi_awqos[3:0]), // Templated
.s_axi_awsize (m_axi_awsize[2:0]), // Templated
.s_axi_awvalid (m_axi_awvalid), // Templated
.s_axi_bready (m_axi_bready), // Templated
.s_axi_rready (m_axi_rready), // Templated
.s_axi_wid (m_axi_wid[S_IDW-1:0]), // Templated
.s_axi_wdata (m_axi_wdata[31:0]), // Templated
.s_axi_wlast (m_axi_wlast), // Templated
.s_axi_wstrb (m_axi_wstrb[3:0]), // Templated
.s_axi_wvalid (m_axi_wvalid)); // Templated
endmodule
// Local Variables:
// verilog-library-directories:("." "../hdl" "../../emesh/dv" "../../axi/dv" "../../emesh/hdl" "../../memory/hdl" "../../axi/hdl")
// End:
//////////////////////////////////////////////////////////////////////////////
// The MIT License (MIT) //
// //
// Copyright (c) 2015-2016, Adapteva, Inc. //
// //
// Permission is hereby granted, free of charge, to any person obtaining a //
// copy of this software and associated documentation files (the "Software")//
// to deal in the Software without restriction, including without limitation//
// the rights to use, copy, modify, merge, publish, distribute, sublicense, //
// and/or sell copies of the Software, and to permit persons to whom the //
// Software is furnished to do so, subject to the following conditions: //
// //
// The above copyright notice and this permission notice shall be included //
// in all copies or substantial portions of the Software. //
// //
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS //
// OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF //
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. //
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY //
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT//
// OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR //
// THE USE OR OTHER DEALINGS IN THE SOFTWARE. //
// //
//////////////////////////////////////////////////////////////////////////////
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: INSTITUTO TECNOLOGICO DE COSTA RICA
// Engineer: MAURICIO CARVAJAL DELGADO
//
// Create Date: 10:33:48 03/17/2013
// Design Name:
// Module Name: Transmisor
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//////////////////////////////////////////////////////////////////////////////////
module Transmisor
#(
parameter DBIT = 8 , // #databits
SB_TICK = 16 // #ticks fors top bits
)
(
input wire clk, reset,
input wire tx_start, s_tick,
input wire [7:0] din,
output reg TX_Done=0,
output wire tx
);
// synlbolic s t a t e d e c l a r a t i o n
localparam [1:0]
idle = 2'b00,
start = 2'b01,
data = 2'b10,
stop = 2'b11;
// signal declaratio n
reg [1:0] state_reg=0, state_next=0;
reg [3:0] s_reg=0, s_next=0;
reg [2:0] n_reg=0, n_next=0;
reg [7:0] b_reg=0, b_next=0;
reg tx_reg=1, tx_next=1;
// FSMD state & data registers
always @(posedge clk, posedge reset)
if (reset)
begin
state_reg <= idle;
s_reg <= 0;
n_reg <= 0;
b_reg <= 0 ;
tx_reg <= 1'b1;
end
else
begin
state_reg <= state_next;
s_reg <= s_next;
n_reg <= n_next;
b_reg <= b_next;
tx_reg <= tx_next;
end
// FSMD next_state logic&functional units
always @*
begin
state_next = state_reg;
TX_Done = 1'b0;
s_next = s_reg;
n_next = n_reg;
b_next = b_reg;
tx_next = tx_reg;
case (state_reg)
idle:
begin
tx_next = 1'b1;
if (tx_start)
begin
state_next = start;
s_next =0;
b_next = din;
end
end
start:
begin
tx_next =1'b0;
if (s_tick)
if (s_reg ==15)
begin
state_next = data;
s_next = 0;
n_next = 0;
end
else
s_next = s_reg + 1;
end
data:
begin
tx_next =b_reg[0];
if (s_tick)
if (s_reg == 15)
begin
s_next =0;
b_next = b_reg>>1;
if (n_reg==(DBIT-1))
state_next = stop;
else
n_next = n_reg + 1;
end
else
s_next = s_reg + 1;
end
stop:
begin
tx_next =1'b1;
if (s_tick)
if (s_reg==(SB_TICK-1 ))
begin
state_next = idle;
TX_Done = 1'b1;
end
else
s_next = s_reg+ 1;
end
endcase
end
// output
assign tx = tx_reg;
endmodule
|
//////////////////////////////////////////////////////////////////////////
// Department of Computer Science
// National Tsing Hua University
// Project : FIFO for CS4125 Digital System Design
// Module : fifo_ctl.v
// Author : Chih-Tsun Huang
// E-mail : [email protected]
// Revision : 4
// Date : 2014/04/28
// Abstract :
// FIFO controller is mainly the finite state machine and its
// control signals to manage the RAM module.
// Note :
// 1. The purpose of this version is to provide a design style. It is
// not a complete module. Please fix any *unexpected feature* by
// yourself if any.
// 2. Feel free to rewrite this file header to your own.
//
module fifo_ctr (
// inputs
input wire clk,
input wire rst_n,
input wire push,
input wire pop,
// outputs
output reg empty,
output reg almost_empty,
output reg full,
output reg almost_full,
output reg error,
output reg cen,
output reg wen,
output reg oen,
output reg [4:0] addr
);
parameter numOfRam = 32;
// small delay of flip-flop outputs
parameter delay = 1.5;
// state encoding
parameter EMPTY = 2'b00;
parameter BETWEEN = 2'b01;
parameter READOUT = 2'b10;
parameter FULL = 2'b11;
// state vector
reg [1:0] state;
reg [1:0] state_next;
// pointers
reg [4:0] head;
reg [4:0] head_next;
reg [4:0] tail;
reg [4:0] tail_next;
reg head_plus;
reg tail_plus;
reg addr_head;
reg addr_tail;
reg do_idle;
reg do_pop;
reg do_push;
reg do_push_pop;
// sequential part
always @(posedge clk or negedge rst_n) begin
if (rst_n == 0) begin
state <= EMPTY;
head <= 5'b0;
tail <= 5'b0;
end else begin
state <= #(delay) state_next;
head <= #(delay) head_next;
tail <= #(delay) tail_next;
end
end
// combinational parts
// Lab Note:
// Complete your design here
always @(*) begin
do_idle = 1'b0;
do_pop = 1'b0;
do_push = 1'b0;
do_push_pop = 1'b0;
case ({push,pop})
2'b00: begin do_idle = 1'b1; end
2'b01: begin do_pop = 1'b1; end
2'b10: begin do_push = 1'b1; end
2'b11: begin do_push_pop = 1'b1; end
endcase
end
always @(*) begin
if (head_plus) begin
head_next = (head + 1'b1)%numOfRam;
end else begin
head_next = head;
end
if (tail_plus) begin
tail_next = (tail + 1'b1)%numOfRam;
end else begin
tail_next = tail;
end
end
always @(*) begin
if (tail == head - 1'b1) begin
almost_empty = 1'b1;
end else begin
almost_empty = 1'b0;
end
if (head == tail - 1'b1) begin
almost_full = 1'b1;
end else begin
almost_full = 1'b0;
end
oen = 1'b0;
end
// FSM
always @(*) begin
empty = 1'b0;
full = 1'b0;
error = 1'b0;
cen = 1'b0;
wen = 1'b1;
addr = 5'b0;
head_plus = 1'b0;
tail_plus = 1'b0;
addr_head = 1'b0;
addr_tail = 1'b0;
state_next = state;
case (state)
EMPTY: begin
if (do_idle || do_pop || do_push_pop) begin
error = (do_pop | do_push_pop);
state_next = EMPTY;
end else if (do_push) begin
addr = head;
head_plus = 1'b1;
wen = 1'b0;
state_next = BETWEEN;
end
end
BETWEEN: begin
if (do_push && !almost_full) begin
addr = head;
head_plus = 1'b1;
wen = 1'b0;
state_next = BETWEEN;
end else if (do_idle || do_push_pop) begin
error = do_push_pop;
state_next = BETWEEN;
end else if (do_pop) begin
addr = tail;
state_next = READOUT;
end else if (do_push && almost_full) begin
addr = head;
head_plus = 1'b1;
wen = 1'b0;
state_next = FULL;
end
end
READOUT: begin
// Wait for ram 1 cycle
if (!almost_empty) begin
tail_plus = 1'b1;
error = (do_push | do_pop);
state_next = BETWEEN;
end else begin
tail_plus = 1'b1;
error = (do_push | do_pop);
state_next = EMPTY;
end
end
FULL: begin
if (do_pop) begin
addr = tail;
state_next = READOUT;
end else if (do_idle || do_push || do_push_pop) begin
error = (do_push | do_push_pop);
state_next = FULL;
end
end
endcase
end
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 13 08:37:09 2016
/////////////////////////////////////////////////////////////
module CORDIC_Arch2_W64_EW11_SW52_SWR55_EWR6 ( clk, rst, beg_fsm_cordic,
ack_cordic, operation, data_in, shift_region_flag, r_mode,
ready_cordic, overflow_flag, underflow_flag, data_output );
input [63:0] data_in;
input [1:0] shift_region_flag;
input [1:0] r_mode;
output [63:0] data_output;
input clk, rst, beg_fsm_cordic, ack_cordic, operation;
output ready_cordic, overflow_flag, underflow_flag;
wire d_ff1_operation_out, sel_mux_1_reg, d_ff3_sign_out, sel_mux_3_reg,
data_output2_63_, cordic_FSM_state_next_1_,
add_subt_module_sign_final_result, add_subt_module_intAS,
add_subt_module_FSM_selector_D, add_subt_module_FSM_exp_operation_A_S,
add_subt_module_add_overflow_flag, add_subt_module_FSM_selector_C,
n1703, n1704, n1705, n1706, n1707, n1708, n1709, n1710, n1711, n1712,
n1713, n1714, n1715, n1716, n1717, n1718, n1719, n1720, n1721, n1722,
n1723, n1724, n1725, n1726, n1727, n1728, n1729, n1730, n1731, n1732,
n1733, n1734, n1735, n1736, n1737, n1738, n1739, n1740, n1741, n1742,
n1743, n1744, n1745, n1746, n1747, n1748, n1749, n1750, n1751, n1752,
n1753, n1754, n1755, n1756, n1757, n1758, n1759, n1760, n1761, n1762,
n1763, n1764, n1765, n1766, n1767, n1768, n1769, n1770, n1771, n1772,
n1773, n1774, n1775, n1776, n1777, n1778, n1779, n1780, n1781, n1782,
n1783, n1784, n1785, n1786, n1787, n1788, n1789, n1790, n1791, n1792,
n1793, n1794, n1795, n1796, n1797, n1798, n1799, n1800, n1801, n1802,
n1803, n1804, n1805, n1806, n1807, n1808, n1809, n1810, n1811, n1812,
n1813, n1814, n1815, n1816, n1817, n1818, n1819, n1820, n1821, n1822,
n1823, n1824, n1825, n1826, n1827, n1828, n1829, n1830, n1831, n1832,
n1833, n1834, n1835, n1836, n1837, n1838, n1839, n1840, n1841, n1842,
n1843, n1844, n1845, n1846, n1847, n1848, n1849, n1850, n1851, n1852,
n1853, n1854, n1855, n1856, n1857, n1858, n1859, n1860, n1861, n1862,
n1863, n1864, n1865, n1866, n1867, n1868, n1869, n1870, n1871, n1872,
n1873, n1874, n1875, n1876, n1877, n1878, n1879, n1880, n1881, n1882,
n1883, n1884, n1885, n1886, n1887, n1888, n1889, n1890, n1891, n1892,
n1893, n1894, n1895, n1896, n1897, n1898, n1899, n1900, n1901, n1902,
n1903, n1904, n1905, n1906, n1907, n1908, n1909, n1910, n1911, n1912,
n1913, n1914, n1915, n1916, n1917, n1918, n1919, n1920, n1921, n1922,
n1923, n1924, n1925, n1926, n1927, n1928, n1929, n1930, n1931, n1932,
n1933, n1934, n1935, n1936, n1937, n1938, n1939, n1940, n1941, n1942,
n1943, n1944, n1945, n1946, n1947, n1948, n1949, n1950, n1951, n1952,
n1953, n1954, n1955, n1956, n1957, n1958, n1959, n1961, n1963, n1964,
n1965, n1966, n1967, n1968, n1969, n1970, n1971, n1972, n1973, n1974,
n1975, n1976, n1977, n1978, n1979, n1980, n1981, n1982, n1983, n1984,
n1985, n1986, n1987, n1988, n1989, n1990, n1991, n1992, n1993, n1994,
n1995, n1996, n1997, n1998, n1999, n2000, n2001, n2002, n2003, n2004,
n2005, n2006, n2007, n2008, n2009, n2010, n2011, n2012, n2013, n2014,
n2015, n2016, n2017, n2018, n2019, n2020, n2021, n2022, n2023, n2024,
n2025, n2026, n2027, n2028, n2029, n2030, n2031, n2032, n2033, n2034,
n2035, n2036, n2037, n2038, n2039, n2040, n2041, n2042, n2043, n2044,
n2045, n2046, n2047, n2048, n2049, n2050, n2051, n2052, n2053, n2054,
n2055, n2056, n2057, n2058, n2059, n2060, n2061, n2062, n2063, n2064,
n2065, n2066, n2067, n2068, n2069, n2070, n2071, n2072, n2073, n2074,
n2075, n2076, n2077, n2078, n2079, n2080, n2081, n2082, n2083, n2084,
n2085, n2086, n2087, n2088, n2089, n2090, n2091, n2092, n2093, n2094,
n2095, n2096, n2097, n2098, n2099, n2100, n2101, n2102, n2103, n2104,
n2105, n2106, n2107, n2108, n2109, n2110, n2111, n2112, n2113, n2114,
n2115, n2116, n2117, n2118, n2119, n2120, n2121, n2122, n2123, n2124,
n2125, n2126, n2127, n2128, n2129, n2130, n2131, n2132, n2133, n2134,
n2135, n2136, n2137, n2138, n2139, n2140, n2141, n2142, n2143, n2144,
n2145, n2146, n2147, n2148, n2149, n2150, n2151, n2152, n2153, n2154,
n2155, n2156, n2157, n2158, n2159, n2160, n2161, n2162, n2163, n2164,
n2165, n2166, n2167, n2168, n2169, n2170, n2171, n2172, n2173, n2174,
n2175, n2176, n2177, n2178, n2179, n2180, n2181, n2182, n2183, n2184,
n2185, n2186, n2187, n2188, n2189, n2190, n2191, n2192, n2193, n2194,
n2195, n2196, n2197, n2198, n2199, n2200, n2201, n2202, n2203, n2204,
n2205, n2206, n2207, n2208, n2209, n2210, n2211, n2212, n2213, n2214,
n2215, n2216, n2217, n2218, n2219, n2220, n2221, n2222, n2223, n2224,
n2225, n2226, n2227, n2228, n2229, n2230, n2231, n2232, n2233, n2234,
n2235, n2236, n2237, n2238, n2239, n2240, n2241, n2242, n2243, n2244,
n2245, n2246, n2247, n2248, n2249, n2250, n2251, n2252, n2253, n2254,
n2255, n2256, n2257, n2258, n2259, n2260, n2261, n2262, n2263, n2264,
n2265, n2266, n2267, n2268, n2269, n2270, n2271, n2272, n2273, n2274,
n2275, n2276, n2277, n2278, n2279, n2280, n2281, n2282, n2283, n2284,
n2285, n2286, n2287, n2288, n2289, n2290, n2291, n2292, n2293, n2294,
n2295, n2296, n2297, n2298, n2299, n2300, n2301, n2302, n2303, n2304,
n2305, n2306, n2307, n2308, n2309, n2310, n2311, n2312, n2313, n2314,
n2315, n2316, n2317, n2318, n2319, n2320, n2321, n2322, n2323, n2324,
n2325, n2326, n2327, n2328, n2329, n2330, n2331, n2332, n2333, n2334,
n2335, n2336, n2337, n2338, n2339, n2340, n2341, n2342, n2343, n2344,
n2345, n2346, n2347, n2348, n2349, n2350, n2351, n2352, n2353, n2354,
n2355, n2356, n2357, n2358, n2359, n2360, n2361, n2362, n2363, n2364,
n2365, n2366, n2367, n2368, n2369, n2370, n2371, n2372, n2373, n2374,
n2375, n2376, n2377, n2378, n2379, n2380, n2381, n2382, n2383, n2384,
n2385, n2386, n2387, n2388, n2389, n2390, n2391, n2392, n2393, n2394,
n2395, n2396, n2397, n2398, n2399, n2400, n2401, n2402, n2403, n2404,
n2405, n2406, n2407, n2408, n2409, n2410, n2411, n2412, n2413, n2414,
n2415, n2416, n2417, n2418, n2419, n2420, n2421, n2422, n2423, n2424,
n2425, n2426, n2427, n2428, n2429, n2430, n2431, n2432, n2433, n2434,
n2435, n2436, n2437, n2438, n2439, n2440, n2441, n2442, n2443, n2444,
n2445, n2446, n2447, n2448, n2449, n2450, n2451, n2452, n2453, n2454,
n2455, n2456, n2457, n2458, n2459, n2460, n2461, n2462, n2463, n2464,
n2465, n2466, n2467, n2468, n2469, n2470, n2471, n2472, n2473, n2474,
n2475, n2476, n2477, n2478, n2479, n2480, n2481, n2482, n2483, n2484,
n2485, n2486, n2487, n2488, n2489, n2490, n2491, n2492, n2493, n2494,
n2495, n2496, n2497, n2498, n2499, n2500, n2501, n2502, n2503, n2504,
n2505, n2506, n2507, n2508, n2509, n2510, n2511, n2512, n2513, n2514,
n2515, n2516, n2517, n2518, n2519, n2520, n2521, n2522, n2523, n2524,
n2525, n2526, n2527, n2528, n2529, n2530, n2531, n2532, n2533, n2534,
n2535, n2536, n2537, n2538, n2539, n2540, n2541, n2542, n2543, n2544,
n2545, n2546, n2547, n2548, n2549, n2550, n2551, n2552, n2553, n2554,
n2555, n2556, n2557, n2558, n2559, n2560, n2561, n2562, n2563, n2564,
n2565, n2566, n2567, n2568, n2569, n2570, n2571, n2572, n2573, n2574,
n2575, n2576, n2577, n2578, n2579, n2580, n2581, n2582, n2583, n2584,
n2585, n2586, n2587, n2588, n2589, n2590, n2591, n2592, n2593, n2594,
n2595, n2596, n2597, n2598, n2599, n2600, n2601, n2602, n2603, n2604,
n2605, n2606, n2607, n2608, n2609, n2610, n2611, n2612, n2613, n2614,
n2615, n2616, n2617, n2618, n2619, n2620, n2621, n2622, n2623, n2624,
n2625, n2626, n2627, n2628, n2629, n2630, n2631, n2632, n2633, n2634,
n2635, n2636, n2637, n2638, n2639, n2640, n2641, n2642, n2643, n2644,
n2645, n2646, n2647, n2648, n2649, n2650, n2651, n2652, n2653, n2654,
n2655, n2656, n2657, n2658, n2659, n2660, n2661, n2662, n2663, n2664,
n2665, n2666, n2667, n2668, n2669, n2670, n2671, n2672, n2673, n2674,
n2675, n2676, n2677, n2678, n2679, n2680, n2681, n2682, n2683, n2684,
n2685, n2686, n2687, n2688, n2689, n2690, n2691, n2692, n2693, n2694,
n2695, n2696, n2697, n2698, n2699, n2700, n2701, n2702, n2703, n2704,
n2705, n2706, n2707, n2708, n2709, n2710, n2711, n2712, n2713, n2714,
n2715, n2716, n2717, n2718, n2719, n2720, n2721, n2722, n2723, n2724,
n2725, n2726, n2727, n2728, n2729, n2730, n2731, n2732, n2733, n2734,
n2735, n2736, n2737, n2738, n2739, n2740, n2741, n2742, n2743, n2744,
n2745, n2746, n2747, n2748, n2749, n2750, n2751, n2752, n2753, n2754,
n2755, n2756, n2757, n2758, n2759, n2760, n2761, n2762, n2763, n2764,
n2765, n2766, n2767, n2768, n2769, n2770, n2771, n2772, n2773, n2774,
n2775, n2776, n2777, n2778, n2779, n2780, n2781, n2782, n2783, n2784,
n2785, n2786, n2787, n2788, n2789, n2790, n2791, n2792, n2793, n2794,
n2795, n2796, n2797, n2798, n2799, n2800, n2801, n2802, n2803, n2804,
n2805, n2806, n2807, n2808, n2809, n2810, n2811, n2812, n2813, n2814,
n2815, n2816, n2817, n2818, n2819, n2820, n2821, n2822, n2823, n2824,
n2825, n2826, n2827, n2828, n2829, n2830, n2831, n2832, n2833, n2834,
n2835, n2836, n2837, n2838, n2839, n2840, n2841, n2842, n2843, n2844,
n2845, n2846, n2847, n2848, n2849, n2850, n2851, n2852, n2853, n2854,
n2855, n2856, n2857, n2858, n2859, n2860, n2861, n2862, n2863, n2864,
n2865, n2866, n2867, n2868, n2869, n2870, n2871, n2872, n2873, n2874,
n2875, n2876, n2877, n2878, n2879, n2880, n2881, n2882, n2883, n2884,
n2885, n2886, n2887, n2888, n2889, n2890, n2891, n2892, n2893, n2894,
n2895, n2896, n2897, n2898, n2899, n2900, n2901, n2902, n2903, n2904,
n2905, n2906, n2907, n2908, n2909, n2910, n2911, n2912, n2913, n2914,
n2915, n2916, n2917, n2918, n2919, n2920, n2921, n2922, n2923, n2924,
n2925, n2926, n2927, n2928, n2929, n2930, n2931, n2932, n2933, n2934,
n2935, n2936, n2937, n2938, n2939, n2940, DP_OP_92J137_122_9081_n26,
DP_OP_92J137_122_9081_n25, DP_OP_92J137_122_9081_n24,
DP_OP_92J137_122_9081_n23, DP_OP_92J137_122_9081_n22,
DP_OP_92J137_122_9081_n21, DP_OP_92J137_122_9081_n20,
DP_OP_92J137_122_9081_n19, DP_OP_92J137_122_9081_n18,
DP_OP_92J137_122_9081_n17, DP_OP_92J137_122_9081_n16,
DP_OP_92J137_122_9081_n11, DP_OP_92J137_122_9081_n10,
DP_OP_92J137_122_9081_n9, DP_OP_92J137_122_9081_n8,
DP_OP_92J137_122_9081_n7, DP_OP_92J137_122_9081_n6,
DP_OP_92J137_122_9081_n5, DP_OP_92J137_122_9081_n4,
DP_OP_92J137_122_9081_n3, DP_OP_92J137_122_9081_n2,
DP_OP_92J137_122_9081_n1, intadd_372_CI, intadd_372_SUM_2_,
intadd_372_SUM_1_, intadd_372_SUM_0_, intadd_372_n3, intadd_372_n2,
intadd_372_n1, intadd_373_CI, intadd_373_SUM_2_, intadd_373_SUM_1_,
intadd_373_SUM_0_, intadd_373_n3, intadd_373_n2, intadd_373_n1, n2953,
n2954, n2956, n2957, n2958, n2959, n2960, n2961, n2962, n2963, n2964,
n2965, n2966, n2967, n2968, n2969, n2970, n2971, n2972, n2973, n2974,
n2975, n2976, n2977, n2978, n2979, n2980, n2981, n2982, n2983, n2984,
n2985, n2986, n2987, n2988, n2989, n2990, n2991, n2992, n2993, n2994,
n2995, n2996, n2997, n2998, n2999, n3000, n3001, n3002, n3003, n3004,
n3005, n3006, n3007, n3008, n3009, n3010, n3011, n3012, n3013, n3014,
n3015, n3016, n3017, n3018, n3019, n3020, n3021, n3022, n3023, n3024,
n3025, n3026, n3027, n3028, n3029, n3030, n3031, n3032, n3033, n3034,
n3035, n3036, n3037, n3038, n3039, n3040, n3041, n3042, n3043, n3044,
n3045, n3046, n3047, n3048, n3049, n3050, n3051, n3052, n3053, n3054,
n3055, n3056, n3057, n3058, n3059, n3060, n3061, n3062, n3063, n3064,
n3065, n3066, n3067, n3068, n3069, n3070, n3071, n3072, n3073, n3074,
n3075, n3076, n3077, n3078, n3079, n3080, n3081, n3082, n3083, n3084,
n3085, n3086, n3087, n3088, n3089, n3090, n3091, n3092, n3093, n3094,
n3095, n3096, n3097, n3098, n3099, n3100, n3101, n3102, n3103, n3104,
n3105, n3106, n3107, n3108, n3109, n3110, n3111, n3112, n3113, n3114,
n3115, n3116, n3117, n3118, n3119, n3120, n3121, n3122, n3123, n3124,
n3125, n3126, n3127, n3128, n3129, n3130, n3131, n3132, n3133, n3134,
n3135, n3136, n3137, n3138, n3139, n3140, n3141, n3142, n3143, n3144,
n3145, n3146, n3147, n3148, n3149, n3150, n3151, n3152, n3153, n3154,
n3155, n3156, n3157, n3158, n3159, n3160, n3161, n3162, n3163, n3164,
n3165, n3166, n3167, n3168, n3169, n3170, n3171, n3172, n3173, n3174,
n3175, n3176, n3177, n3178, n3179, n3180, n3181, n3182, n3183, n3184,
n3185, n3186, n3187, n3188, n3189, n3190, n3191, n3192, n3193, n3194,
n3195, n3196, n3197, n3198, n3199, n3200, n3201, n3202, n3203, n3204,
n3205, n3206, n3207, n3208, n3209, n3210, n3211, n3212, n3213, n3214,
n3215, n3216, n3217, n3218, n3219, n3220, n3221, n3222, n3223, n3224,
n3225, n3226, n3227, n3228, n3229, n3230, n3231, n3232, n3233, n3234,
n3235, n3236, n3237, n3238, n3239, n3240, n3241, n3242, n3243, n3244,
n3245, n3246, n3247, n3248, n3249, n3250, n3251, n3252, n3253, n3254,
n3255, n3256, n3257, n3258, n3259, n3260, n3261, n3262, n3263, n3264,
n3265, n3266, n3267, n3268, n3269, n3270, n3271, n3272, n3273, n3274,
n3275, n3276, n3277, n3278, n3279, n3280, n3281, n3282, n3283, n3284,
n3285, n3286, n3287, n3288, n3289, n3290, n3291, n3292, n3293, n3294,
n3295, n3296, n3297, n3298, n3299, n3300, n3301, n3302, n3303, n3304,
n3305, n3306, n3307, n3308, n3309, n3310, n3311, n3312, n3313, n3314,
n3315, n3316, n3317, n3318, n3319, n3320, n3321, n3322, n3323, n3324,
n3325, n3326, n3327, n3328, n3329, n3330, n3331, n3332, n3333, n3334,
n3335, n3336, n3337, n3338, n3339, n3340, n3341, n3342, n3343, n3344,
n3345, n3346, n3347, n3348, n3349, n3350, n3351, n3352, n3353, n3354,
n3355, n3356, n3357, n3358, n3359, n3360, n3361, n3362, n3363, n3364,
n3365, n3366, n3367, n3368, n3369, n3370, n3371, n3372, n3373, n3374,
n3375, n3376, n3377, n3378, n3379, n3380, n3381, n3382, n3383, n3384,
n3385, n3386, n3387, n3388, n3389, n3390, n3391, n3392, n3393, n3394,
n3395, n3396, n3397, n3398, n3399, n3400, n3401, n3402, n3403, n3404,
n3405, n3406, n3407, n3408, n3409, n3410, n3411, n3412, n3413, n3414,
n3415, n3416, n3417, n3418, n3419, n3420, n3421, n3422, n3423, n3424,
n3425, n3426, n3427, n3428, n3429, n3430, n3431, n3432, n3433, n3434,
n3435, n3436, n3437, n3438, n3439, n3440, n3441, n3442, n3443, n3444,
n3445, n3446, n3447, n3448, n3449, n3450, n3451, n3452, n3453, n3454,
n3455, n3456, n3457, n3458, n3459, n3460, n3461, n3462, n3463, n3464,
n3465, n3466, n3467, n3468, n3469, n3470, n3471, n3472, n3473, n3474,
n3475, n3476, n3477, n3478, n3479, n3480, n3481, n3482, n3483, n3484,
n3485, n3486, n3487, n3488, n3489, n3490, n3491, n3492, n3493, n3494,
n3495, n3496, n3497, n3498, n3499, n3500, n3501, n3502, n3503, n3504,
n3505, n3506, n3507, n3508, n3509, n3510, n3511, n3512, n3513, n3514,
n3515, n3516, n3517, n3518, n3519, n3520, n3521, n3522, n3523, n3524,
n3525, n3526, n3527, n3528, n3529, n3530, n3531, n3532, n3533, n3534,
n3535, n3536, n3537, n3538, n3539, n3540, n3541, n3542, n3543, n3544,
n3545, n3546, n3547, n3548, n3549, n3550, n3551, n3552, n3553, n3554,
n3555, n3556, n3557, n3558, n3559, n3560, n3561, n3562, n3563, n3564,
n3565, n3566, n3567, n3568, n3569, n3570, n3571, n3572, n3573, n3574,
n3575, n3576, n3577, n3578, n3579, n3580, n3581, n3582, n3583, n3584,
n3585, n3586, n3587, n3588, n3589, n3590, n3591, n3592, n3593, n3594,
n3595, n3596, n3597, n3598, n3599, n3600, n3601, n3602, n3603, n3604,
n3605, n3606, n3607, n3608, n3609, n3610, n3611, n3612, n3613, n3614,
n3615, n3616, n3617, n3618, n3619, n3620, n3621, n3622, n3623, n3624,
n3625, n3626, n3627, n3628, n3629, n3630, n3631, n3632, n3633, n3634,
n3635, n3636, n3637, n3638, n3639, n3640, n3641, n3642, n3643, n3644,
n3645, n3646, n3647, n3648, n3649, n3650, n3651, n3652, n3653, n3654,
n3655, n3656, n3657, n3658, n3659, n3660, n3661, n3662, n3663, n3664,
n3665, n3666, n3667, n3668, n3669, n3670, n3671, n3672, n3673, n3674,
n3675, n3676, n3677, n3678, n3679, n3680, n3681, n3682, n3683, n3684,
n3685, n3686, n3687, n3688, n3689, n3690, n3691, n3692, n3693, n3694,
n3695, n3696, n3697, n3698, n3699, n3700, n3701, n3702, n3703, n3704,
n3705, n3706, n3707, n3708, n3709, n3710, n3711, n3712, n3713, n3714,
n3715, n3716, n3717, n3718, n3719, n3720, n3721, n3722, n3723, n3724,
n3725, n3726, n3727, n3728, n3729, n3730, n3731, n3732, n3733, n3734,
n3735, n3736, n3737, n3738, n3739, n3740, n3741, n3742, n3743, n3744,
n3745, n3746, n3747, n3748, n3749, n3750, n3751, n3752, n3753, n3754,
n3755, n3756, n3757, n3758, n3759, n3760, n3761, n3762, n3763, n3764,
n3765, n3766, n3767, n3768, n3769, n3770, n3771, n3772, n3773, n3774,
n3775, n3776, n3777, n3778, n3779, n3780, n3781, n3782, n3783, n3784,
n3785, n3786, n3787, n3788, n3789, n3790, n3791, n3792, n3793, n3794,
n3795, n3796, n3797, n3798, n3799, n3800, n3801, n3802, n3803, n3804,
n3805, n3806, n3807, n3808, n3809, n3810, n3811, n3812, n3813, n3814,
n3815, n3816, n3817, n3818, n3819, n3820, n3821, n3822, n3823, n3824,
n3825, n3826, n3827, n3828, n3829, n3830, n3831, n3832, n3833, n3834,
n3835, n3836, n3837, n3838, n3839, n3840, n3841, n3842, n3843, n3844,
n3845, n3846, n3847, n3848, n3849, n3850, n3851, n3852, n3853, n3854,
n3855, n3856, n3857, n3858, n3859, n3860, n3861, n3862, n3863, n3864,
n3865, n3866, n3867, n3868, n3869, n3870, n3871, n3872, n3873, n3874,
n3875, n3876, n3877, n3878, n3879, n3880, n3881, n3882, n3883, n3884,
n3885, n3886, n3887, n3888, n3889, n3890, n3891, n3892, n3893, n3894,
n3895, n3896, n3897, n3898, n3899, n3900, n3901, n3902, n3903, n3904,
n3905, n3906, n3907, n3908, n3909, n3910, n3911, n3912, n3913, n3914,
n3915, n3916, n3917, n3918, n3919, n3920, n3921, n3922, n3923, n3924,
n3925, n3926, n3927, n3928, n3929, n3930, n3931, n3932, n3933, n3934,
n3935, n3936, n3937, n3938, n3939, n3940, n3941, n3942, n3943, n3944,
n3945, n3946, n3947, n3948, n3949, n3950, n3951, n3952, n3953, n3954,
n3955, n3956, n3957, n3958, n3959, n3960, n3961, n3962, n3963, n3964,
n3965, n3966, n3967, n3968, n3969, n3970, n3971, n3972, n3973, n3974,
n3975, n3976, n3977, n3978, n3979, n3980, n3981, n3982, n3983, n3984,
n3985, n3986, n3987, n3988, n3989, n3990, n3991, n3992, n3993, n3994,
n3995, n3996, n3997, n3998, n3999, n4000, n4001, n4002, n4003, n4004,
n4005, n4006, n4007, n4008, n4009, n4010, n4011, n4012, n4013, n4014,
n4015, n4016, n4017, n4018, n4019, n4020, n4021, n4022, n4023, n4024,
n4025, n4026, n4027, n4029, n4030, n4031, n4032, n4033, n4034, n4035,
n4036, n4037, n4038, n4040, n4041, n4042, n4043, n4044, n4045, n4046,
n4047, n4048, n4049, n4050, n4051, n4052, n4053, n4054, n4055, n4056,
n4057, n4058, n4059, n4060, n4061, n4062, n4063, n4064, n4065, n4066,
n4067, n4068, n4069, n4070, n4071, n4072, n4073, n4074, n4075, n4076,
n4077, n4078, n4079, n4080, n4081, n4082, n4083, n4084, n4085, n4086,
n4087, n4088, n4089, n4090, n4091, n4092, n4093, n4094, n4095, n4096,
n4097, n4098, n4100, n4101, n4102, n4103, n4104, n4105, n4106, n4107,
n4108, n4109, n4110, n4111, n4112, n4113, n4114, n4115, n4116, n4117,
n4118, n4119, n4120, n4121, n4122, n4123, n4124, n4125, n4126, n4127,
n4128, n4129, n4130, n4131, n4132, n4133, n4134, n4135, n4136, n4137,
n4138, n4139, n4140, n4141, n4142, n4143, n4144, n4145, n4146, n4147,
n4148, n4149, n4150, n4151, n4152, n4153, n4154, n4155, n4156, n4157,
n4158, n4159, n4160, n4161, n4162, n4163, n4164, n4165, n4166, n4167,
n4168, n4169, n4170, n4171, n4172, n4173, n4174, n4175, n4176, n4177,
n4178, n4179, n4180, n4181, n4182, n4183, n4184, n4185, n4186, n4187,
n4188, n4189, n4190, n4191, n4192, n4193, n4194, n4195, n4196, n4197,
n4198, n4199, n4200, n4201, n4202, n4203, n4204, n4205, n4206, n4207,
n4208, n4209, n4210, n4211, n4212, n4213, n4214, n4215, n4216, n4217,
n4218, n4219, n4220, n4221, n4222, n4223, n4224, n4225, n4226, n4227,
n4228, n4229, n4230, n4231, n4232, n4233, n4234, n4235, n4236, n4237,
n4238, n4239, n4240, n4241, n4242, n4243, n4244, n4245, n4246, n4247,
n4248, n4249, n4250, n4251, n4252, n4253, n4254, n4255, n4256, n4257,
n4258, n4259, n4260, n4261, n4262, n4263, n4264, n4265, n4266, n4267,
n4268, n4269, n4270, n4271, n4272, n4273, n4274, n4275, n4276, n4277,
n4278, n4279, n4280, n4281, n4282, n4283, n4284, n4285, n4286, n4287,
n4288, n4289, n4290, n4291, n4292, n4293, n4294, n4295, n4296, n4297,
n4298, n4299, n4300, n4301, n4302, n4303, n4304, n4305, n4306, n4307,
n4308, n4309, n4310, n4311, n4312, n4313, n4314, n4315, n4316, n4317,
n4318, n4319, n4320, n4321, n4322, n4323, n4324, n4325, n4326, n4327,
n4328, n4329, n4330, n4331, n4332, n4333, n4334, n4335, n4336, n4337,
n4338, n4339, n4340, n4341, n4342, n4343, n4344, n4345, n4346, n4347,
n4348, n4349, n4350, n4351, n4352, n4353, n4354, n4355, n4356, n4357,
n4358, n4359, n4360, n4361, n4362, n4363, n4364, n4365, n4366, n4367,
n4368, n4369, n4370, n4371, n4372, n4373, n4374, n4375, n4376, n4377,
n4378, n4379, n4380, n4381, n4382, n4383, n4384, n4385, n4386, n4387,
n4388, n4389, n4390, n4391, n4392, n4393, n4394, n4395, n4396, n4397,
n4398, n4399, n4400, n4401, n4402, n4403, n4404, n4405, n4406, n4407,
n4408, n4409, n4410, n4411, n4412, n4413, n4414, n4415, n4416, n4417,
n4418, n4419, n4420, n4421, n4422, n4423, n4424, n4425, n4426, n4427,
n4428, n4429, n4430, n4431, n4432, n4433, n4434, n4435, n4436, n4437,
n4438, n4439, n4440, n4441, n4442, n4443, n4444, n4445, n4446, n4447,
n4448, n4449, n4450, n4451, n4452, n4453, n4454, n4455, n4456, n4457,
n4458, n4459, n4460, n4461, n4462, n4463, n4464, n4465, n4466, n4467,
n4468, n4469, n4470, n4471, n4472, n4473, n4474, n4475, n4476, n4477,
n4478, n4479, n4480, n4481, n4482, n4483, n4484, n4485, n4486, n4487,
n4488, n4489, n4490, n4491, n4492, n4493, n4494, n4495, n4496, n4497,
n4498, n4499, n4500, n4501, n4502, n4503, n4504, n4505, n4506, n4507,
n4508, n4509, n4510, n4511, n4512, n4513, n4514, n4515, n4516, n4517,
n4518, n4519, n4520, n4521, n4522, n4523, n4524, n4525, n4526, n4527,
n4528, n4529, n4530, n4531, n4532, n4533, n4534, n4535, n4536, n4537,
n4538, n4539, n4540, n4541, n4542, n4543, n4544, n4545, n4546, n4547,
n4548, n4549, n4550, n4551, n4552, n4553, n4554, n4555, n4556, n4557,
n4558, n4559, n4560, n4561, n4562, n4563, n4564, n4565, n4566, n4568,
n4569, n4570, n4571, n4572, n4573, n4574, n4575, n4576, n4577, n4578,
n4579, n4580, n4581, n4582, n4583, n4584, n4585, n4586, n4587, n4588,
n4589, n4590, n4591, n4592, n4593, n4594, n4595, n4596, n4597, n4598,
n4599, n4600, n4601, n4602, n4603, n4604, n4605, n4606, n4607, n4608,
n4609, n4610, n4611, n4612, n4613, n4614, n4615, n4616, n4617, n4618,
n4619, n4620, n4621, n4622, n4623, n4624, n4625, n4626, n4628, n4629,
n4630, n4631, n4632, n4633, n4634, n4635, n4636, n4637, n4638, n4639,
n4640, n4641, n4643, n4644, n4645, n4646, n4647, n4648, n4649, n4650,
n4651, n4652, n4653, n4654, n4655, n4656, n4657, n4658, n4659, n4660,
n4661, n4662, n4663, n4664, n4665, n4666, n4667, n4668, n4669, n4670,
n4671, n4672, n4673, n4674, n4675, n4676, n4677, n4678, n4679, n4680,
n4681, n4682, n4683, n4684, n4685, n4686, n4687, n4688, n4689, n4690,
n4691, n4692, n4693, n4694, n4695, n4696, n4697, n4698, n4699, n4700,
n4701, n4702, n4703, n4704, n4705, n4706, n4707, n4708, n4709, n4710,
n4711, n4712, n4713, n4714, n4715, n4716, n4717, n4718, n4719, n4720,
n4721, n4722, n4723, n4724, n4725, n4726, n4727, n4728, n4729, n4730,
n4731, n4732, n4733, n4734, n4735, n4736, n4737, n4738, n4739, n4740,
n4741, n4742, n4743, n4744, n4745, n4746, n4747, n4748, n4749, n4750,
n4751, n4752, n4753, n4754, n4755, n4756, n4757, n4758, n4759, n4760,
n4761, n4762, n4763, n4764, n4765, n4766, n4767, n4768, n4769, n4770,
n4771, n4772, n4773, n4774, n4775, n4776, n4777, n4779, n4780, n4781,
n4782, n4783, n4784, n4785, n4786, n4787, n4788, n4789, n4790, n4791,
n4792, n4793, n4794, n4795, n4796, n4797, n4798, n4799, n4800, n4801,
n4802, n4803, n4804, n4805, n4806, n4807, n4808, n4809, n4810, n4811,
n4812, n4813, n4814, n4816, n4817, n4818, n4819, n4820, n4821, n4822,
n4823, n4824, n4825, n4826, n4827, n4828, n4829, n4830, n4831, n4832,
n4833, n4834, n4835, n4836, n4837, n4838, n4839, n4840, n4841, n4842,
n4843, n4844, n4845, n4846, n4847, n4848, n4849, n4850, n4851, n4852,
n4853, n4854, n4855, n4856, n4857, n4858, n4859, n4860, n4861, n4862,
n4863, n4864, n4865, n4866, n4867, n4868, n4869, n4870, n4871, n4872,
n4873, n4874, n4875, n4876, n4877, n4878, n4879, n4880, n4881, n4882,
n4883, n4884, n4885, n4886, n4887, n4888, n4889, n4890, n4891, n4892,
n4893, n4894, n4895, n4896, n4897, n4898, n4899, n4900, n4901, n4902,
n4903, n4904, n4905, n4906, n4907, n4908, n4909, n4910, n4911, n4912,
n4913, n4914, n4915, n4916, n4917, n4918, n4919, n4920, n4921, n4922,
n4923, n4924, n4925, n4926, n4927, n4928, n4929, n4930, n4931, n4932,
n4933, n4934, n4935, n4936, n4937, n4938, n4939, n4940, n4941, n4942,
n4943, n4944, n4945, n4946, n4947, n4948, n4949, n4950, n4951, n4952,
n4953, n4954, n4955, n4956, n4957, n4958, n4959, n4960, n4961, n4962,
n4963, n4964, n4965, n4966, n4967, n4968, n4969, n4970, n4971, n4972,
n4973, n4974, n4975, n4976, n4977, n4978, n4979, n4980, n4981, n4982,
n4983, n4984, n4985, n4986, n4987, n4988, n4989, n4990, n4991, n4992,
n4993, n4994, n4995, n4996, n4997, n4998, n4999, n5000, n5001, n5002,
n5003, n5004, n5005, n5006, n5007, n5008, n5009, n5010, n5011, n5012,
n5013, n5014, n5015, n5016, n5017, n5018, n5019, n5020, n5021, n5022,
n5023, n5024, n5025, n5026, n5027, n5028, n5029, n5030, n5031, n5032,
n5033, n5034, n5035, n5036, n5037, n5038, n5039, n5040, n5041, n5042,
n5043, n5044, n5045, n5046, n5047, n5048, n5049, n5050, n5051, n5052,
n5053, n5054, n5055, n5056, n5057, n5058, n5059, n5060, n5061, n5062,
n5063, n5064, n5065, n5066, n5067, n5068, n5069, n5070, n5071, n5072,
n5073, n5074, n5075, n5076, n5077, n5078, n5079, n5080, n5081, n5082,
n5083, n5084, n5085, n5086, n5087, n5088, n5089, n5090, n5091, n5092,
n5093, n5094, n5095, n5096, n5097, n5098, n5099, n5100, n5101, n5102,
n5103, n5104, n5105, n5106, n5107, n5108, n5109, n5110, n5111, n5112,
n5113, n5114, n5115, n5116, n5117, n5118, n5119, n5120, n5121, n5122,
n5123, n5124, n5125, n5126, n5127, n5128, n5129, n5130, n5131, n5132,
n5133, n5134, n5135, n5136, n5137, n5138, n5139, n5140, n5141, n5142,
n5143, n5144, n5145, n5146, n5147, n5148, n5149, n5150, n5151, n5152,
n5153, n5154, n5155, n5156, n5157, n5158, n5159, n5160, n5161, n5162,
n5163, n5164, n5165, n5166, n5167, n5168, n5169, n5170, n5171, n5172,
n5173, n5174, n5175, n5176, n5177, n5178, n5179, n5180, n5181, n5182,
n5183, n5184, n5185, n5186, n5187, n5188, n5189, n5190, n5191, n5192,
n5193, n5194, n5195, n5196, n5197, n5198, n5199, n5200, n5201, n5202,
n5203, n5204, n5205, n5206, n5207, n5208, n5209, n5210, n5211, n5212,
n5213, n5214, n5215, n5216, n5217, n5218, n5219, n5220, n5221, n5222,
n5223, n5224, n5225, n5226, n5227, n5228, n5229, n5230, n5231, n5232,
n5233, n5234, n5235, n5236, n5237, n5238, n5239, n5240, n5241, n5242,
n5243, n5244, n5245, n5246, n5247, n5248, n5249, n5250, n5251, n5252,
n5253, n5254, n5255, n5256, n5257, n5258, n5259, n5260, n5261, n5262,
n5263, n5264, n5265, n5266, n5267, n5268, n5269, n5270, n5271, n5272,
n5273, n5274, n5275, n5276, n5277, n5278, n5279, n5280, n5281, n5282,
n5283, n5284, n5285, n5286, n5287, n5288, n5289, n5290, n5291, n5292,
n5293, n5294, n5295, n5296, n5297, n5298, n5299, n5300, n5301, n5302,
n5303, n5304, n5305, n5306, n5307, n5308, n5309, n5310, n5311, n5312,
n5313, n5314, n5315, n5316, n5317, n5318, n5319, n5320, n5321, n5322,
n5323, n5324, n5325, n5326, n5327, n5328, n5329, n5330, n5331, n5332,
n5333, n5334, n5335, n5336, n5337, n5338, n5339, n5340, n5341, n5342,
n5343, n5344, n5345, n5346, n5347, n5348, n5349, n5350, n5351, n5352,
n5353, n5354, n5355, n5356, n5357, n5358, n5359, n5360, n5361, n5362,
n5363, n5364, n5365, n5366, n5367, n5368, n5369, n5370, n5371, n5372,
n5373, n5374, n5375, n5376, n5377, n5378, n5379, n5380, n5381, n5382,
n5383, n5384, n5385, n5386, n5387, n5388, n5389, n5390, n5391, n5392,
n5393, n5394, n5395, n5396, n5397, n5398, n5399, n5400, n5401, n5402,
n5403, n5404;
wire [1:0] d_ff1_shift_region_flag_out;
wire [1:0] cont_var_out;
wire [3:0] cont_iter_out;
wire [63:0] d_ff1_Z;
wire [63:0] d_ff_Xn;
wire [63:0] d_ff_Yn;
wire [63:0] d_ff_Zn;
wire [63:0] d_ff2_X;
wire [63:0] d_ff2_Y;
wire [63:0] d_ff2_Z;
wire [63:0] d_ff3_sh_x_out;
wire [63:0] d_ff3_sh_y_out;
wire [56:0] d_ff3_LUT_out;
wire [1:0] sel_mux_2_reg;
wire [63:0] result_add_subt;
wire [62:0] sign_inv_out;
wire [3:0] cordic_FSM_state_reg;
wire [54:0] add_subt_module_Sgf_normalized_result;
wire [54:0] add_subt_module_Add_Subt_result;
wire [5:0] add_subt_module_LZA_output;
wire [10:0] add_subt_module_S_Oper_A_exp;
wire [10:0] add_subt_module_exp_oper_result;
wire [62:0] add_subt_module_DmP;
wire [62:0] add_subt_module_DMP;
wire [63:0] add_subt_module_intDY;
wire [63:0] add_subt_module_intDX;
wire [1:0] add_subt_module_FSM_selector_B;
wire [3:0] add_subt_module_FS_Module_state_reg;
wire [10:0] add_subt_module_Exp_Operation_Module_Data_S;
wire [109:0] add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array;
DFFRXLTS reg_Z0_Q_reg_62_ ( .D(n2917), .CK(clk), .RN(n5352), .Q(d_ff1_Z[62])
);
DFFRXLTS reg_Z0_Q_reg_61_ ( .D(n2916), .CK(clk), .RN(n5352), .Q(d_ff1_Z[61])
);
DFFRXLTS reg_Z0_Q_reg_60_ ( .D(n2915), .CK(clk), .RN(n5352), .Q(d_ff1_Z[60])
);
DFFRXLTS reg_Z0_Q_reg_59_ ( .D(n2914), .CK(clk), .RN(n5353), .Q(d_ff1_Z[59])
);
DFFRXLTS reg_Z0_Q_reg_58_ ( .D(n2913), .CK(clk), .RN(n5353), .Q(d_ff1_Z[58])
);
DFFRXLTS reg_Z0_Q_reg_57_ ( .D(n2912), .CK(clk), .RN(n5353), .Q(d_ff1_Z[57])
);
DFFRXLTS reg_Z0_Q_reg_56_ ( .D(n2911), .CK(clk), .RN(n5353), .Q(d_ff1_Z[56])
);
DFFRXLTS reg_Z0_Q_reg_55_ ( .D(n2910), .CK(clk), .RN(n5353), .Q(d_ff1_Z[55])
);
DFFRXLTS reg_Z0_Q_reg_54_ ( .D(n2909), .CK(clk), .RN(n5353), .Q(d_ff1_Z[54])
);
DFFRXLTS reg_Z0_Q_reg_53_ ( .D(n2908), .CK(clk), .RN(n5353), .Q(d_ff1_Z[53])
);
DFFRXLTS reg_Z0_Q_reg_52_ ( .D(n2907), .CK(clk), .RN(n5353), .Q(d_ff1_Z[52])
);
DFFRXLTS reg_Z0_Q_reg_51_ ( .D(n2906), .CK(clk), .RN(n5353), .Q(d_ff1_Z[51])
);
DFFRXLTS reg_Z0_Q_reg_50_ ( .D(n2905), .CK(clk), .RN(n5353), .Q(d_ff1_Z[50])
);
DFFRXLTS reg_Z0_Q_reg_49_ ( .D(n2904), .CK(clk), .RN(n5353), .Q(d_ff1_Z[49])
);
DFFRXLTS reg_Z0_Q_reg_48_ ( .D(n2903), .CK(clk), .RN(n5353), .Q(d_ff1_Z[48])
);
DFFRXLTS reg_Z0_Q_reg_47_ ( .D(n2902), .CK(clk), .RN(n5362), .Q(d_ff1_Z[47])
);
DFFRXLTS reg_Z0_Q_reg_46_ ( .D(n2901), .CK(clk), .RN(n5352), .Q(d_ff1_Z[46])
);
DFFRXLTS reg_Z0_Q_reg_45_ ( .D(n2900), .CK(clk), .RN(n5366), .Q(d_ff1_Z[45])
);
DFFRXLTS reg_Z0_Q_reg_44_ ( .D(n2899), .CK(clk), .RN(n5365), .Q(d_ff1_Z[44])
);
DFFRXLTS reg_Z0_Q_reg_43_ ( .D(n2898), .CK(clk), .RN(n5354), .Q(d_ff1_Z[43])
);
DFFRXLTS reg_Z0_Q_reg_42_ ( .D(n2897), .CK(clk), .RN(n5364), .Q(d_ff1_Z[42])
);
DFFRXLTS reg_Z0_Q_reg_41_ ( .D(n2896), .CK(clk), .RN(n5363), .Q(d_ff1_Z[41])
);
DFFRXLTS reg_Z0_Q_reg_40_ ( .D(n2895), .CK(clk), .RN(n5362), .Q(d_ff1_Z[40])
);
DFFRXLTS reg_Z0_Q_reg_39_ ( .D(n2894), .CK(clk), .RN(n5353), .Q(d_ff1_Z[39])
);
DFFRXLTS reg_Z0_Q_reg_38_ ( .D(n2893), .CK(clk), .RN(n5366), .Q(d_ff1_Z[38])
);
DFFRXLTS reg_Z0_Q_reg_37_ ( .D(n2892), .CK(clk), .RN(n5365), .Q(d_ff1_Z[37])
);
DFFRXLTS reg_Z0_Q_reg_36_ ( .D(n2891), .CK(clk), .RN(n5369), .Q(d_ff1_Z[36])
);
DFFRXLTS reg_Z0_Q_reg_35_ ( .D(n2890), .CK(clk), .RN(n5354), .Q(d_ff1_Z[35])
);
DFFRXLTS reg_Z0_Q_reg_34_ ( .D(n2889), .CK(clk), .RN(n5354), .Q(d_ff1_Z[34])
);
DFFRXLTS reg_Z0_Q_reg_33_ ( .D(n2888), .CK(clk), .RN(n5354), .Q(d_ff1_Z[33])
);
DFFRXLTS reg_Z0_Q_reg_32_ ( .D(n2887), .CK(clk), .RN(n5354), .Q(d_ff1_Z[32])
);
DFFRXLTS reg_Z0_Q_reg_31_ ( .D(n2886), .CK(clk), .RN(n5354), .Q(d_ff1_Z[31])
);
DFFRXLTS reg_Z0_Q_reg_30_ ( .D(n2885), .CK(clk), .RN(n5354), .Q(d_ff1_Z[30])
);
DFFRXLTS reg_Z0_Q_reg_29_ ( .D(n2884), .CK(clk), .RN(n5354), .Q(d_ff1_Z[29])
);
DFFRXLTS reg_Z0_Q_reg_28_ ( .D(n2883), .CK(clk), .RN(n5354), .Q(d_ff1_Z[28])
);
DFFRXLTS reg_Z0_Q_reg_27_ ( .D(n2882), .CK(clk), .RN(n5354), .Q(d_ff1_Z[27])
);
DFFRXLTS reg_Z0_Q_reg_26_ ( .D(n2881), .CK(clk), .RN(n5354), .Q(d_ff1_Z[26])
);
DFFRXLTS reg_Z0_Q_reg_25_ ( .D(n2880), .CK(clk), .RN(n5354), .Q(d_ff1_Z[25])
);
DFFRXLTS reg_Z0_Q_reg_24_ ( .D(n2879), .CK(clk), .RN(n5354), .Q(d_ff1_Z[24])
);
DFFRXLTS reg_Z0_Q_reg_23_ ( .D(n2878), .CK(clk), .RN(n5367), .Q(d_ff1_Z[23])
);
DFFRXLTS reg_Z0_Q_reg_22_ ( .D(n2877), .CK(clk), .RN(n5354), .Q(d_ff1_Z[22])
);
DFFRXLTS reg_Z0_Q_reg_21_ ( .D(n2876), .CK(clk), .RN(n5368), .Q(d_ff1_Z[21])
);
DFFRXLTS reg_Z0_Q_reg_20_ ( .D(n2875), .CK(clk), .RN(n5364), .Q(d_ff1_Z[20])
);
DFFRXLTS reg_Z0_Q_reg_19_ ( .D(n2874), .CK(clk), .RN(n5363), .Q(d_ff1_Z[19])
);
DFFRXLTS reg_Z0_Q_reg_18_ ( .D(n2873), .CK(clk), .RN(n5362), .Q(d_ff1_Z[18])
);
DFFRXLTS reg_Z0_Q_reg_17_ ( .D(n2872), .CK(clk), .RN(n5353), .Q(d_ff1_Z[17])
);
DFFRXLTS reg_Z0_Q_reg_16_ ( .D(n2871), .CK(clk), .RN(n5366), .Q(d_ff1_Z[16])
);
DFFRXLTS reg_Z0_Q_reg_15_ ( .D(n2870), .CK(clk), .RN(n5365), .Q(d_ff1_Z[15])
);
DFFRXLTS reg_Z0_Q_reg_14_ ( .D(n2869), .CK(clk), .RN(n5369), .Q(d_ff1_Z[14])
);
DFFRXLTS reg_Z0_Q_reg_13_ ( .D(n2868), .CK(clk), .RN(n5368), .Q(d_ff1_Z[13])
);
DFFRXLTS reg_Z0_Q_reg_12_ ( .D(n2867), .CK(clk), .RN(n5367), .Q(d_ff1_Z[12])
);
DFFRXLTS reg_Z0_Q_reg_11_ ( .D(n2866), .CK(clk), .RN(n5385), .Q(d_ff1_Z[11])
);
DFFRXLTS reg_Z0_Q_reg_10_ ( .D(n2865), .CK(clk), .RN(n5390), .Q(d_ff1_Z[10])
);
DFFRXLTS reg_Z0_Q_reg_9_ ( .D(n2864), .CK(clk), .RN(n5389), .Q(d_ff1_Z[9])
);
DFFRXLTS reg_Z0_Q_reg_8_ ( .D(n2863), .CK(clk), .RN(n5388), .Q(d_ff1_Z[8])
);
DFFRXLTS reg_Z0_Q_reg_7_ ( .D(n2862), .CK(clk), .RN(n5355), .Q(d_ff1_Z[7])
);
DFFRXLTS reg_Z0_Q_reg_6_ ( .D(n2861), .CK(clk), .RN(n5387), .Q(d_ff1_Z[6])
);
DFFRXLTS reg_Z0_Q_reg_5_ ( .D(n2860), .CK(clk), .RN(n5386), .Q(d_ff1_Z[5])
);
DFFRXLTS reg_Z0_Q_reg_4_ ( .D(n2859), .CK(clk), .RN(n5385), .Q(d_ff1_Z[4])
);
DFFRXLTS reg_Z0_Q_reg_3_ ( .D(n2858), .CK(clk), .RN(n5390), .Q(d_ff1_Z[3])
);
DFFRXLTS reg_Z0_Q_reg_2_ ( .D(n2857), .CK(clk), .RN(n5389), .Q(d_ff1_Z[2])
);
DFFRXLTS reg_Z0_Q_reg_1_ ( .D(n2856), .CK(clk), .RN(n5388), .Q(d_ff1_Z[1])
);
DFFRXLTS reg_Z0_Q_reg_0_ ( .D(n2855), .CK(clk), .RN(n5393), .Q(d_ff1_Z[0])
);
DFFRXLTS reg_Z0_Q_reg_63_ ( .D(n2854), .CK(clk), .RN(n5355), .Q(d_ff1_Z[63])
);
DFFRXLTS reg_LUT_Q_reg_56_ ( .D(n2850), .CK(clk), .RN(n5355), .Q(
d_ff3_LUT_out[56]) );
DFFRXLTS reg_LUT_Q_reg_55_ ( .D(n2849), .CK(clk), .RN(n5355), .Q(
d_ff3_LUT_out[55]) );
DFFRXLTS reg_LUT_Q_reg_54_ ( .D(n2848), .CK(clk), .RN(n5355), .Q(
d_ff3_LUT_out[54]) );
DFFRXLTS reg_LUT_Q_reg_53_ ( .D(n2847), .CK(clk), .RN(n5355), .Q(
d_ff3_LUT_out[53]) );
DFFRXLTS reg_LUT_Q_reg_52_ ( .D(n2846), .CK(clk), .RN(n5355), .Q(
d_ff3_LUT_out[52]) );
DFFRXLTS reg_LUT_Q_reg_50_ ( .D(n2845), .CK(clk), .RN(n5355), .Q(
d_ff3_LUT_out[50]) );
DFFRXLTS reg_LUT_Q_reg_49_ ( .D(n2844), .CK(clk), .RN(n5355), .Q(
d_ff3_LUT_out[49]) );
DFFRXLTS reg_LUT_Q_reg_47_ ( .D(n2842), .CK(clk), .RN(n5355), .Q(
d_ff3_LUT_out[47]) );
DFFRXLTS reg_LUT_Q_reg_46_ ( .D(n2841), .CK(clk), .RN(n5355), .Q(
d_ff3_LUT_out[46]) );
DFFRXLTS reg_LUT_Q_reg_45_ ( .D(n2840), .CK(clk), .RN(n5355), .Q(
d_ff3_LUT_out[45]) );
DFFRXLTS reg_LUT_Q_reg_44_ ( .D(n2839), .CK(clk), .RN(n5391), .Q(
d_ff3_LUT_out[44]) );
DFFRXLTS reg_LUT_Q_reg_43_ ( .D(n2838), .CK(clk), .RN(n5355), .Q(
d_ff3_LUT_out[43]) );
DFFRXLTS reg_LUT_Q_reg_42_ ( .D(n2837), .CK(clk), .RN(n5392), .Q(
d_ff3_LUT_out[42]) );
DFFRXLTS reg_LUT_Q_reg_41_ ( .D(n2836), .CK(clk), .RN(n5387), .Q(
d_ff3_LUT_out[41]) );
DFFRXLTS reg_LUT_Q_reg_40_ ( .D(n2835), .CK(clk), .RN(n5386), .Q(
d_ff3_LUT_out[40]) );
DFFRXLTS reg_LUT_Q_reg_39_ ( .D(n2834), .CK(clk), .RN(n5385), .Q(
d_ff3_LUT_out[39]) );
DFFRXLTS reg_LUT_Q_reg_38_ ( .D(n2833), .CK(clk), .RN(n5390), .Q(
d_ff3_LUT_out[38]) );
DFFRXLTS reg_LUT_Q_reg_37_ ( .D(n2832), .CK(clk), .RN(n5389), .Q(
d_ff3_LUT_out[37]) );
DFFRXLTS reg_LUT_Q_reg_36_ ( .D(n2831), .CK(clk), .RN(n5388), .Q(
d_ff3_LUT_out[36]) );
DFFRXLTS reg_LUT_Q_reg_35_ ( .D(n2830), .CK(clk), .RN(n5393), .Q(
d_ff3_LUT_out[35]) );
DFFRXLTS reg_LUT_Q_reg_34_ ( .D(n2829), .CK(clk), .RN(n5392), .Q(
d_ff3_LUT_out[34]) );
DFFRXLTS reg_LUT_Q_reg_33_ ( .D(n2828), .CK(clk), .RN(n5391), .Q(
d_ff3_LUT_out[33]), .QN(n5310) );
DFFRXLTS reg_LUT_Q_reg_32_ ( .D(n2827), .CK(clk), .RN(n5356), .Q(
d_ff3_LUT_out[32]) );
DFFRXLTS reg_LUT_Q_reg_31_ ( .D(n2826), .CK(clk), .RN(n5356), .Q(
d_ff3_LUT_out[31]) );
DFFRXLTS reg_LUT_Q_reg_30_ ( .D(n2825), .CK(clk), .RN(n5356), .Q(
d_ff3_LUT_out[30]) );
DFFRXLTS reg_LUT_Q_reg_29_ ( .D(n2824), .CK(clk), .RN(n5356), .Q(
d_ff3_LUT_out[29]) );
DFFRXLTS reg_LUT_Q_reg_28_ ( .D(n2823), .CK(clk), .RN(n5356), .Q(
d_ff3_LUT_out[28]) );
DFFRXLTS reg_LUT_Q_reg_27_ ( .D(n2822), .CK(clk), .RN(n5356), .Q(
d_ff3_LUT_out[27]) );
DFFRXLTS reg_LUT_Q_reg_26_ ( .D(n2821), .CK(clk), .RN(n5356), .Q(
d_ff3_LUT_out[26]) );
DFFRXLTS reg_LUT_Q_reg_25_ ( .D(n2820), .CK(clk), .RN(n5356), .Q(
d_ff3_LUT_out[25]) );
DFFRXLTS reg_LUT_Q_reg_24_ ( .D(n2819), .CK(clk), .RN(n5356), .Q(
d_ff3_LUT_out[24]) );
DFFRXLTS reg_LUT_Q_reg_23_ ( .D(n2818), .CK(clk), .RN(n5356), .Q(
d_ff3_LUT_out[23]), .QN(n5307) );
DFFRXLTS reg_LUT_Q_reg_22_ ( .D(n2817), .CK(clk), .RN(n5356), .Q(
d_ff3_LUT_out[22]) );
DFFRXLTS reg_LUT_Q_reg_21_ ( .D(n2816), .CK(clk), .RN(n5356), .Q(
d_ff3_LUT_out[21]) );
DFFRXLTS reg_LUT_Q_reg_20_ ( .D(n2815), .CK(clk), .RN(n5375), .Q(
d_ff3_LUT_out[20]) );
DFFRXLTS reg_LUT_Q_reg_19_ ( .D(n2814), .CK(clk), .RN(n5379), .Q(
d_ff3_LUT_out[19]), .QN(n5311) );
DFFRXLTS reg_LUT_Q_reg_18_ ( .D(n2813), .CK(clk), .RN(n5357), .Q(
d_ff3_LUT_out[18]) );
DFFRXLTS reg_LUT_Q_reg_17_ ( .D(n2812), .CK(clk), .RN(n5359), .Q(
d_ff3_LUT_out[17]) );
DFFRXLTS reg_LUT_Q_reg_16_ ( .D(n2811), .CK(clk), .RN(n5370), .Q(
d_ff3_LUT_out[16]) );
DFFRXLTS reg_LUT_Q_reg_15_ ( .D(n2810), .CK(clk), .RN(n5372), .Q(
d_ff3_LUT_out[15]) );
DFFRXLTS reg_LUT_Q_reg_14_ ( .D(n2809), .CK(clk), .RN(n5360), .Q(
d_ff3_LUT_out[14]) );
DFFRXLTS reg_LUT_Q_reg_13_ ( .D(n2808), .CK(clk), .RN(n5371), .Q(
d_ff3_LUT_out[13]) );
DFFRXLTS reg_LUT_Q_reg_12_ ( .D(n2807), .CK(clk), .RN(n5384), .Q(
d_ff3_LUT_out[12]) );
DFFRXLTS reg_LUT_Q_reg_11_ ( .D(n2806), .CK(clk), .RN(n5383), .Q(
d_ff3_LUT_out[11]) );
DFFRXLTS reg_LUT_Q_reg_10_ ( .D(n2805), .CK(clk), .RN(n5382), .Q(
d_ff3_LUT_out[10]) );
DFFRXLTS reg_LUT_Q_reg_9_ ( .D(n2804), .CK(clk), .RN(n5357), .Q(
d_ff3_LUT_out[9]) );
DFFRXLTS reg_LUT_Q_reg_8_ ( .D(n2803), .CK(clk), .RN(n5361), .Q(
d_ff3_LUT_out[8]), .QN(n5309) );
DFFRXLTS reg_LUT_Q_reg_7_ ( .D(n2802), .CK(clk), .RN(n5374), .Q(
d_ff3_LUT_out[7]) );
DFFRXLTS reg_LUT_Q_reg_6_ ( .D(n2801), .CK(clk), .RN(n5373), .Q(
d_ff3_LUT_out[6]), .QN(n5306) );
DFFRXLTS reg_LUT_Q_reg_5_ ( .D(n2800), .CK(clk), .RN(n5356), .Q(
d_ff3_LUT_out[5]) );
DFFRXLTS reg_LUT_Q_reg_4_ ( .D(n2799), .CK(clk), .RN(n5376), .Q(
d_ff3_LUT_out[4]) );
DFFRXLTS reg_LUT_Q_reg_2_ ( .D(n2797), .CK(clk), .RN(n5375), .Q(
d_ff3_LUT_out[2]) );
DFFRXLTS reg_LUT_Q_reg_1_ ( .D(n2796), .CK(clk), .RN(n5361), .Q(
d_ff3_LUT_out[1]) );
DFFRXLTS reg_LUT_Q_reg_0_ ( .D(n2795), .CK(clk), .RN(n5381), .Q(
d_ff3_LUT_out[0]) );
DFFRXLTS reg_shift_y_Q_reg_62_ ( .D(n2093), .CK(clk), .RN(n5380), .Q(
d_ff3_sh_y_out[62]) );
DFFRXLTS reg_shift_y_Q_reg_61_ ( .D(n2094), .CK(clk), .RN(n5379), .Q(
d_ff3_sh_y_out[61]) );
DFFRXLTS reg_shift_y_Q_reg_60_ ( .D(n2095), .CK(clk), .RN(n5358), .Q(
d_ff3_sh_y_out[60]) );
DFFRXLTS reg_shift_y_Q_reg_59_ ( .D(n2096), .CK(clk), .RN(n5358), .Q(
d_ff3_sh_y_out[59]) );
DFFRXLTS reg_shift_y_Q_reg_58_ ( .D(n2097), .CK(clk), .RN(n5380), .Q(
d_ff3_sh_y_out[58]) );
DFFRXLTS reg_shift_y_Q_reg_56_ ( .D(n2099), .CK(clk), .RN(n5372), .Q(
d_ff3_sh_y_out[56]) );
DFFRXLTS reg_shift_y_Q_reg_55_ ( .D(n2100), .CK(clk), .RN(n5360), .Q(
d_ff3_sh_y_out[55]) );
DFFRXLTS reg_shift_y_Q_reg_54_ ( .D(n2101), .CK(clk), .RN(n5403), .Q(
d_ff3_sh_y_out[54]) );
DFFRXLTS reg_shift_y_Q_reg_53_ ( .D(n2102), .CK(clk), .RN(n5376), .Q(
d_ff3_sh_y_out[53]) );
DFFRXLTS reg_shift_y_Q_reg_52_ ( .D(n2103), .CK(clk), .RN(n5381), .Q(
d_ff3_sh_y_out[52]) );
DFFRXLTS reg_shift_x_Q_reg_62_ ( .D(n2772), .CK(clk), .RN(n5371), .Q(
d_ff3_sh_x_out[62]) );
DFFRXLTS reg_shift_x_Q_reg_61_ ( .D(n2773), .CK(clk), .RN(n5384), .Q(
d_ff3_sh_x_out[61]) );
DFFRXLTS reg_shift_x_Q_reg_60_ ( .D(n2774), .CK(clk), .RN(n5383), .Q(
d_ff3_sh_x_out[60]) );
DFFRXLTS reg_shift_x_Q_reg_59_ ( .D(n2775), .CK(clk), .RN(n5382), .Q(
d_ff3_sh_x_out[59]) );
DFFRXLTS reg_shift_x_Q_reg_58_ ( .D(n2776), .CK(clk), .RN(n5357), .Q(
d_ff3_sh_x_out[58]) );
DFFRXLTS reg_shift_x_Q_reg_57_ ( .D(n2777), .CK(clk), .RN(n5357), .Q(
d_ff3_sh_x_out[57]) );
DFFRXLTS reg_shift_x_Q_reg_56_ ( .D(n2778), .CK(clk), .RN(n5357), .Q(
d_ff3_sh_x_out[56]), .QN(n5308) );
DFFRXLTS reg_shift_x_Q_reg_55_ ( .D(n2779), .CK(clk), .RN(n5357), .Q(
d_ff3_sh_x_out[55]) );
DFFRXLTS reg_shift_x_Q_reg_54_ ( .D(n2780), .CK(clk), .RN(n5357), .Q(
d_ff3_sh_x_out[54]) );
DFFRXLTS reg_shift_x_Q_reg_53_ ( .D(n2781), .CK(clk), .RN(n5357), .Q(
d_ff3_sh_x_out[53]) );
DFFRXLTS reg_shift_x_Q_reg_52_ ( .D(n2782), .CK(clk), .RN(n5357), .Q(
d_ff3_sh_x_out[52]) );
DFFRXLTS reg_ch_mux_1_Q_reg_0_ ( .D(n2853), .CK(clk), .RN(n5357), .Q(
sel_mux_1_reg), .QN(n5247) );
DFFRXLTS reg_ch_mux_2_Q_reg_0_ ( .D(n2852), .CK(clk), .RN(n5357), .Q(
sel_mux_2_reg[0]), .QN(n5240) );
DFFRXLTS reg_shift_x_Q_reg_0_ ( .D(n2668), .CK(clk), .RN(n5358), .Q(
d_ff3_sh_x_out[0]) );
DFFRXLTS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_39_ ( .D(
n2635), .CK(clk), .RN(n5332), .QN(n2957) );
DFFRXLTS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_22_ ( .D(
n2618), .CK(clk), .RN(n5329), .QN(n2960) );
DFFRXLTS add_subt_module_Leading_Zero_Detector_Module_Output_Reg_Q_reg_0_ (
.D(n2592), .CK(clk), .RN(n5344), .Q(add_subt_module_LZA_output[0]) );
DFFRXLTS add_subt_module_Leading_Zero_Detector_Module_Output_Reg_Q_reg_5_ (
.D(n2589), .CK(clk), .RN(n5339), .Q(add_subt_module_LZA_output[5]),
.QN(n5313) );
DFFRXLTS reg_shift_x_Q_reg_63_ ( .D(n2794), .CK(clk), .RN(n5358), .Q(
d_ff3_sh_x_out[63]) );
DFFRXLTS d_ff4_Yn_Q_reg_63_ ( .D(n2666), .CK(clk), .RN(n5358), .Q(
d_ff_Yn[63]), .QN(n5246) );
DFFRXLTS reg_shift_y_Q_reg_63_ ( .D(n2091), .CK(clk), .RN(n5358), .Q(
d_ff3_sh_y_out[63]) );
DFFRXLTS d_ff5_data_out_Q_reg_63_ ( .D(n1961), .CK(clk), .RN(n5358), .Q(
data_output[63]) );
DFFRXLTS d_ff4_Zn_Q_reg_63_ ( .D(n2665), .CK(clk), .RN(n5358), .Q(
d_ff_Zn[63]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_63_ ( .D(n2221), .CK(clk), .RN(n5358),
.Q(d_ff2_Z[63]), .QN(n5312) );
DFFRXLTS reg_sign_Q_reg_0_ ( .D(n2220), .CK(clk), .RN(n5359), .Q(
d_ff3_sign_out) );
DFFRXLTS d_ff4_Zn_Q_reg_62_ ( .D(n2533), .CK(clk), .RN(n5359), .Q(
d_ff_Zn[62]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_62_ ( .D(n2222), .CK(clk), .RN(n5359),
.Q(d_ff2_Z[62]) );
DFFRXLTS d_ff4_Yn_Q_reg_62_ ( .D(n2532), .CK(clk), .RN(n5359), .Q(
d_ff_Yn[62]), .QN(n5305) );
DFFRXLTS d_ff5_Q_reg_62_ ( .D(n1965), .CK(clk), .RN(n5359), .Q(
sign_inv_out[62]) );
DFFRXLTS d_ff5_data_out_Q_reg_62_ ( .D(n1964), .CK(clk), .RN(n5359), .Q(
data_output[62]) );
DFFRXLTS d_ff4_Zn_Q_reg_61_ ( .D(n2529), .CK(clk), .RN(n5359), .Q(
d_ff_Zn[61]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_61_ ( .D(n2223), .CK(clk), .RN(n5359),
.Q(d_ff2_Z[61]) );
DFFRXLTS d_ff4_Yn_Q_reg_61_ ( .D(n2528), .CK(clk), .RN(n5359), .Q(
d_ff_Yn[61]), .QN(n5304) );
DFFRXLTS d_ff5_Q_reg_61_ ( .D(n1967), .CK(clk), .RN(n5360), .Q(
sign_inv_out[61]) );
DFFRXLTS d_ff5_data_out_Q_reg_61_ ( .D(n1966), .CK(clk), .RN(n5360), .Q(
data_output[61]) );
DFFRXLTS d_ff4_Zn_Q_reg_60_ ( .D(n2525), .CK(clk), .RN(n5360), .Q(
d_ff_Zn[60]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_60_ ( .D(n2224), .CK(clk), .RN(n5360),
.Q(d_ff2_Z[60]) );
DFFRXLTS d_ff4_Yn_Q_reg_60_ ( .D(n2524), .CK(clk), .RN(n5360), .Q(
d_ff_Yn[60]), .QN(n2971) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_60_ ( .D(n2106), .CK(clk), .RN(n5360),
.Q(d_ff2_Y[60]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_60_ ( .D(n2791), .CK(clk), .RN(n5360),
.Q(d_ff2_X[60]) );
DFFRXLTS d_ff5_Q_reg_60_ ( .D(n1969), .CK(clk), .RN(n5360), .Q(
sign_inv_out[60]) );
DFFRXLTS d_ff5_data_out_Q_reg_60_ ( .D(n1968), .CK(clk), .RN(n5361), .Q(
data_output[60]) );
DFFRXLTS d_ff4_Zn_Q_reg_59_ ( .D(n2521), .CK(clk), .RN(n5361), .Q(
d_ff_Zn[59]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_59_ ( .D(n2225), .CK(clk), .RN(n5361),
.Q(d_ff2_Z[59]) );
DFFRXLTS d_ff4_Yn_Q_reg_59_ ( .D(n2520), .CK(clk), .RN(n5361), .Q(
d_ff_Yn[59]), .QN(n5303) );
DFFRXLTS d_ff5_Q_reg_59_ ( .D(n1971), .CK(clk), .RN(n5361), .Q(
sign_inv_out[59]) );
DFFRXLTS d_ff5_data_out_Q_reg_59_ ( .D(n1970), .CK(clk), .RN(n5361), .Q(
data_output[59]) );
DFFRXLTS d_ff4_Zn_Q_reg_58_ ( .D(n2517), .CK(clk), .RN(n5361), .Q(
d_ff_Zn[58]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_58_ ( .D(n2226), .CK(clk), .RN(n5361),
.Q(d_ff2_Z[58]) );
DFFRXLTS d_ff4_Yn_Q_reg_58_ ( .D(n2516), .CK(clk), .RN(n5361), .Q(
d_ff_Yn[58]), .QN(n2970) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_58_ ( .D(n2108), .CK(clk), .RN(n5362),
.Q(d_ff2_Y[58]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_58_ ( .D(n2789), .CK(clk), .RN(n5362),
.Q(d_ff2_X[58]) );
DFFRXLTS d_ff5_Q_reg_58_ ( .D(n1973), .CK(clk), .RN(n5362), .Q(
sign_inv_out[58]) );
DFFRXLTS d_ff5_data_out_Q_reg_58_ ( .D(n1972), .CK(clk), .RN(n5362), .Q(
data_output[58]) );
DFFRXLTS d_ff4_Zn_Q_reg_57_ ( .D(n2513), .CK(clk), .RN(n5362), .Q(
d_ff_Zn[57]) );
DFFRXLTS d_ff4_Yn_Q_reg_57_ ( .D(n2512), .CK(clk), .RN(n5362), .Q(
d_ff_Yn[57]), .QN(n2969) );
DFFRXLTS d_ff5_Q_reg_57_ ( .D(n1975), .CK(clk), .RN(n5362), .Q(
sign_inv_out[57]) );
DFFRXLTS d_ff5_data_out_Q_reg_57_ ( .D(n1974), .CK(clk), .RN(n5363), .Q(
data_output[57]) );
DFFRXLTS d_ff4_Zn_Q_reg_56_ ( .D(n2509), .CK(clk), .RN(n5363), .Q(
d_ff_Zn[56]) );
DFFRXLTS d_ff4_Yn_Q_reg_56_ ( .D(n2508), .CK(clk), .RN(n5363), .Q(
d_ff_Yn[56]), .QN(n5302) );
DFFRXLTS d_ff5_Q_reg_56_ ( .D(n1977), .CK(clk), .RN(n5363), .Q(
sign_inv_out[56]) );
DFFRXLTS d_ff5_data_out_Q_reg_56_ ( .D(n1976), .CK(clk), .RN(n5363), .Q(
data_output[56]) );
DFFRXLTS d_ff4_Zn_Q_reg_55_ ( .D(n2505), .CK(clk), .RN(n5363), .Q(
d_ff_Zn[55]) );
DFFRXLTS d_ff4_Yn_Q_reg_55_ ( .D(n2504), .CK(clk), .RN(n5363), .Q(
d_ff_Yn[55]), .QN(n5301) );
DFFRXLTS d_ff5_Q_reg_55_ ( .D(n1979), .CK(clk), .RN(n5364), .Q(
sign_inv_out[55]) );
DFFRXLTS d_ff5_data_out_Q_reg_55_ ( .D(n1978), .CK(clk), .RN(n5364), .Q(
data_output[55]) );
DFFRXLTS d_ff4_Zn_Q_reg_54_ ( .D(n2501), .CK(clk), .RN(n5364), .Q(
d_ff_Zn[54]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_54_ ( .D(n2230), .CK(clk), .RN(n5364),
.Q(d_ff2_Z[54]) );
DFFRXLTS d_ff4_Yn_Q_reg_54_ ( .D(n2500), .CK(clk), .RN(n5364), .Q(
d_ff_Yn[54]), .QN(n5300) );
DFFRXLTS d_ff5_Q_reg_54_ ( .D(n1981), .CK(clk), .RN(n5364), .Q(
sign_inv_out[54]) );
DFFRXLTS d_ff5_data_out_Q_reg_54_ ( .D(n1980), .CK(clk), .RN(n5365), .Q(
data_output[54]) );
DFFRXLTS d_ff4_Zn_Q_reg_53_ ( .D(n2497), .CK(clk), .RN(n5365), .Q(
d_ff_Zn[53]) );
DFFRXLTS d_ff4_Yn_Q_reg_53_ ( .D(n2496), .CK(clk), .RN(n5365), .Q(
d_ff_Yn[53]), .QN(n5299) );
DFFRXLTS d_ff5_Q_reg_53_ ( .D(n1983), .CK(clk), .RN(n5365), .Q(
sign_inv_out[53]) );
DFFRXLTS d_ff5_data_out_Q_reg_53_ ( .D(n1982), .CK(clk), .RN(n5365), .Q(
data_output[53]) );
DFFRXLTS d_ff4_Zn_Q_reg_52_ ( .D(n2493), .CK(clk), .RN(n5365), .Q(
d_ff_Zn[52]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_52_ ( .D(n2232), .CK(clk), .RN(n5365),
.Q(d_ff2_Z[52]) );
DFFRXLTS d_ff4_Yn_Q_reg_52_ ( .D(n2492), .CK(clk), .RN(n5365), .Q(
d_ff_Yn[52]), .QN(n2972) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_52_ ( .D(n2114), .CK(clk), .RN(n5366),
.Q(d_ff2_Y[52]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_52_ ( .D(n2783), .CK(clk), .RN(n5366),
.Q(d_ff2_X[52]), .QN(n5182) );
DFFRXLTS d_ff5_Q_reg_52_ ( .D(n1985), .CK(clk), .RN(n5366), .Q(
sign_inv_out[52]) );
DFFRXLTS d_ff5_data_out_Q_reg_52_ ( .D(n1984), .CK(clk), .RN(n5366), .Q(
data_output[52]) );
DFFRXLTS d_ff4_Zn_Q_reg_0_ ( .D(n2285), .CK(clk), .RN(n5366), .Q(d_ff_Zn[0])
);
DFFRXLTS d_ff4_Yn_Q_reg_0_ ( .D(n2219), .CK(clk), .RN(n5366), .Q(d_ff_Yn[0]),
.QN(n5248) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_1_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[1]),
.CK(clk), .RN(n5333), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[56]) );
DFFRXLTS d_ff4_Zn_Q_reg_51_ ( .D(n2489), .CK(clk), .RN(n5366), .Q(
d_ff_Zn[51]) );
DFFRXLTS d_ff4_Yn_Q_reg_51_ ( .D(n2488), .CK(clk), .RN(n5366), .Q(
d_ff_Yn[51]), .QN(n5298) );
DFFRXLTS reg_shift_y_Q_reg_51_ ( .D(n2115), .CK(clk), .RN(n5368), .Q(
d_ff3_sh_y_out[51]) );
DFFRXLTS reg_shift_x_Q_reg_51_ ( .D(n2770), .CK(clk), .RN(n5387), .Q(
d_ff3_sh_x_out[51]) );
DFFRXLTS d_ff4_Zn_Q_reg_4_ ( .D(n2301), .CK(clk), .RN(n5386), .Q(d_ff_Zn[4])
);
DFFRXLTS reg_val_muxZ_2stage_Q_reg_4_ ( .D(n2280), .CK(clk), .RN(n5392), .Q(
d_ff2_Z[4]) );
DFFRXLTS d_ff4_Yn_Q_reg_4_ ( .D(n2300), .CK(clk), .RN(n5393), .Q(d_ff_Yn[4]),
.QN(n5252) );
DFFRXLTS reg_shift_y_Q_reg_4_ ( .D(n2209), .CK(clk), .RN(n5364), .Q(
d_ff3_sh_y_out[4]) );
DFFRXLTS reg_shift_x_Q_reg_4_ ( .D(n2676), .CK(clk), .RN(n5367), .Q(
d_ff3_sh_x_out[4]) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_4_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[4]),
.CK(clk), .RN(n5315), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[59]) );
DFFRXLTS d_ff4_Zn_Q_reg_48_ ( .D(n2477), .CK(clk), .RN(n5367), .Q(
d_ff_Zn[48]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_48_ ( .D(n2236), .CK(clk), .RN(n5367),
.Q(d_ff2_Z[48]) );
DFFRXLTS d_ff4_Yn_Q_reg_48_ ( .D(n2476), .CK(clk), .RN(n5367), .Q(
d_ff_Yn[48]), .QN(n5295) );
DFFRXLTS reg_shift_y_Q_reg_48_ ( .D(n2121), .CK(clk), .RN(n5367), .Q(
d_ff3_sh_y_out[48]) );
DFFRXLTS reg_shift_x_Q_reg_48_ ( .D(n2764), .CK(clk), .RN(n5367), .Q(
d_ff3_sh_x_out[48]) );
DFFRXLTS d_ff5_Q_reg_48_ ( .D(n1993), .CK(clk), .RN(n5367), .Q(
sign_inv_out[48]) );
DFFRXLTS d_ff5_data_out_Q_reg_48_ ( .D(n1992), .CK(clk), .RN(n5367), .Q(
data_output[48]) );
DFFRXLTS d_ff4_Zn_Q_reg_2_ ( .D(n2293), .CK(clk), .RN(n5367), .Q(d_ff_Zn[2])
);
DFFRXLTS reg_val_muxZ_2stage_Q_reg_2_ ( .D(n2282), .CK(clk), .RN(n5368), .Q(
d_ff2_Z[2]) );
DFFRXLTS d_ff4_Yn_Q_reg_2_ ( .D(n2292), .CK(clk), .RN(n5368), .Q(d_ff_Yn[2]),
.QN(n5250) );
DFFRXLTS reg_shift_y_Q_reg_2_ ( .D(n2213), .CK(clk), .RN(n5368), .Q(
d_ff3_sh_y_out[2]) );
DFFRXLTS reg_shift_x_Q_reg_2_ ( .D(n2672), .CK(clk), .RN(n5368), .Q(
d_ff3_sh_x_out[2]) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_2_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[2]),
.CK(clk), .RN(n5316), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[57]) );
DFFRXLTS d_ff4_Zn_Q_reg_50_ ( .D(n2485), .CK(clk), .RN(n5368), .Q(
d_ff_Zn[50]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_50_ ( .D(n2234), .CK(clk), .RN(n5368),
.Q(d_ff2_Z[50]) );
DFFRXLTS d_ff4_Yn_Q_reg_50_ ( .D(n2484), .CK(clk), .RN(n5368), .Q(
d_ff_Yn[50]), .QN(n5297) );
DFFRXLTS reg_shift_y_Q_reg_50_ ( .D(n2117), .CK(clk), .RN(n5368), .Q(
d_ff3_sh_y_out[50]) );
DFFRXLTS reg_shift_x_Q_reg_50_ ( .D(n2768), .CK(clk), .RN(n5369), .Q(
d_ff3_sh_x_out[50]) );
DFFRXLTS d_ff4_Zn_Q_reg_47_ ( .D(n2473), .CK(clk), .RN(n5369), .Q(
d_ff_Zn[47]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_47_ ( .D(n2237), .CK(clk), .RN(n5369),
.Q(d_ff2_Z[47]) );
DFFRXLTS d_ff4_Yn_Q_reg_47_ ( .D(n2472), .CK(clk), .RN(n5369), .Q(
d_ff_Yn[47]), .QN(n5294) );
DFFRXLTS reg_shift_y_Q_reg_47_ ( .D(n2123), .CK(clk), .RN(n5369), .Q(
d_ff3_sh_y_out[47]) );
DFFRXLTS reg_shift_x_Q_reg_47_ ( .D(n2762), .CK(clk), .RN(n5369), .Q(
d_ff3_sh_x_out[47]) );
DFFRXLTS d_ff5_Q_reg_47_ ( .D(n1995), .CK(clk), .RN(n5369), .Q(
sign_inv_out[47]) );
DFFRXLTS d_ff5_data_out_Q_reg_47_ ( .D(n1994), .CK(clk), .RN(n5370), .Q(
data_output[47]) );
DFFRXLTS d_ff4_Zn_Q_reg_3_ ( .D(n2297), .CK(clk), .RN(n5370), .Q(d_ff_Zn[3])
);
DFFRXLTS reg_val_muxZ_2stage_Q_reg_3_ ( .D(n2281), .CK(clk), .RN(n5370), .Q(
d_ff2_Z[3]) );
DFFRXLTS d_ff4_Yn_Q_reg_3_ ( .D(n2296), .CK(clk), .RN(n5370), .Q(d_ff_Yn[3]),
.QN(n5251) );
DFFRXLTS reg_shift_y_Q_reg_3_ ( .D(n2211), .CK(clk), .RN(n5370), .Q(
d_ff3_sh_y_out[3]) );
DFFRXLTS reg_shift_x_Q_reg_3_ ( .D(n2674), .CK(clk), .RN(n5370), .Q(
d_ff3_sh_x_out[3]) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_3_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[3]),
.CK(clk), .RN(n5343), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[58]) );
DFFRXLTS d_ff4_Zn_Q_reg_1_ ( .D(n2289), .CK(clk), .RN(n5370), .Q(d_ff_Zn[1])
);
DFFRXLTS reg_val_muxZ_2stage_Q_reg_1_ ( .D(n2283), .CK(clk), .RN(n5370), .Q(
d_ff2_Z[1]) );
DFFRXLTS d_ff4_Yn_Q_reg_1_ ( .D(n2288), .CK(clk), .RN(n5370), .Q(d_ff_Yn[1]),
.QN(n5249) );
DFFRXLTS reg_shift_y_Q_reg_1_ ( .D(n2215), .CK(clk), .RN(n5371), .Q(
d_ff3_sh_y_out[1]) );
DFFRXLTS reg_shift_x_Q_reg_1_ ( .D(n2670), .CK(clk), .RN(n5371), .Q(
d_ff3_sh_x_out[1]) );
DFFRXLTS d_ff4_Zn_Q_reg_49_ ( .D(n2481), .CK(clk), .RN(n5371), .Q(
d_ff_Zn[49]) );
DFFRXLTS d_ff4_Yn_Q_reg_49_ ( .D(n2480), .CK(clk), .RN(n5371), .Q(
d_ff_Yn[49]), .QN(n5296) );
DFFRXLTS reg_shift_y_Q_reg_49_ ( .D(n2119), .CK(clk), .RN(n5371), .Q(
d_ff3_sh_y_out[49]) );
DFFRXLTS reg_shift_x_Q_reg_49_ ( .D(n2766), .CK(clk), .RN(n5372), .Q(
d_ff3_sh_x_out[49]) );
DFFRXLTS d_ff5_Q_reg_49_ ( .D(n1991), .CK(clk), .RN(n5372), .Q(
sign_inv_out[49]) );
DFFRXLTS d_ff5_data_out_Q_reg_49_ ( .D(n1990), .CK(clk), .RN(n5372), .Q(
data_output[49]) );
DFFRXLTS d_ff4_Zn_Q_reg_46_ ( .D(n2469), .CK(clk), .RN(n5372), .Q(
d_ff_Zn[46]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_46_ ( .D(n2238), .CK(clk), .RN(n5372),
.Q(d_ff2_Z[46]) );
DFFRXLTS d_ff4_Yn_Q_reg_46_ ( .D(n2468), .CK(clk), .RN(n5372), .Q(
d_ff_Yn[46]), .QN(n5293) );
DFFRXLTS reg_shift_y_Q_reg_46_ ( .D(n2125), .CK(clk), .RN(n5372), .Q(
d_ff3_sh_y_out[46]) );
DFFRXLTS reg_shift_x_Q_reg_46_ ( .D(n2760), .CK(clk), .RN(n5372), .Q(
d_ff3_sh_x_out[46]) );
DFFRXLTS d_ff5_Q_reg_46_ ( .D(n1997), .CK(clk), .RN(n5372), .Q(
sign_inv_out[46]) );
DFFRXLTS d_ff5_data_out_Q_reg_46_ ( .D(n1996), .CK(clk), .RN(n5373), .Q(
data_output[46]) );
DFFRXLTS d_ff4_Zn_Q_reg_16_ ( .D(n2349), .CK(clk), .RN(n5373), .Q(
d_ff_Zn[16]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_16_ ( .D(n2268), .CK(clk), .RN(n5373),
.Q(d_ff2_Z[16]) );
DFFRXLTS d_ff4_Yn_Q_reg_16_ ( .D(n2348), .CK(clk), .RN(n5373), .Q(
d_ff_Yn[16]), .QN(n5264) );
DFFRXLTS reg_shift_y_Q_reg_16_ ( .D(n2185), .CK(clk), .RN(n5373), .Q(
d_ff3_sh_y_out[16]) );
DFFRXLTS reg_shift_x_Q_reg_16_ ( .D(n2700), .CK(clk), .RN(n5373), .Q(
d_ff3_sh_x_out[16]) );
DFFRXLTS d_ff4_Zn_Q_reg_9_ ( .D(n2321), .CK(clk), .RN(n5373), .Q(d_ff_Zn[9])
);
DFFRXLTS reg_val_muxZ_2stage_Q_reg_9_ ( .D(n2275), .CK(clk), .RN(n5373), .Q(
d_ff2_Z[9]) );
DFFRXLTS d_ff4_Yn_Q_reg_9_ ( .D(n2320), .CK(clk), .RN(n5373), .Q(d_ff_Yn[9]),
.QN(n5257) );
DFFRXLTS reg_shift_y_Q_reg_9_ ( .D(n2199), .CK(clk), .RN(n5374), .Q(
d_ff3_sh_y_out[9]) );
DFFRXLTS reg_shift_x_Q_reg_9_ ( .D(n2686), .CK(clk), .RN(n5374), .Q(
d_ff3_sh_x_out[9]) );
DFFRXLTS d_ff4_Zn_Q_reg_44_ ( .D(n2461), .CK(clk), .RN(n5374), .Q(
d_ff_Zn[44]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_44_ ( .D(n2240), .CK(clk), .RN(n5374),
.Q(d_ff2_Z[44]) );
DFFRXLTS d_ff4_Yn_Q_reg_44_ ( .D(n2460), .CK(clk), .RN(n5374), .Q(
d_ff_Yn[44]), .QN(n5291) );
DFFRXLTS reg_shift_y_Q_reg_44_ ( .D(n2129), .CK(clk), .RN(n5374), .Q(
d_ff3_sh_y_out[44]) );
DFFRXLTS reg_shift_x_Q_reg_44_ ( .D(n2756), .CK(clk), .RN(n5399), .Q(
d_ff3_sh_x_out[44]) );
DFFRXLTS d_ff5_Q_reg_44_ ( .D(n2001), .CK(clk), .RN(n5358), .Q(
sign_inv_out[44]) );
DFFRXLTS d_ff5_data_out_Q_reg_44_ ( .D(n2000), .CK(clk), .RN(n5380), .Q(
data_output[44]) );
DFFRXLTS d_ff4_Zn_Q_reg_6_ ( .D(n2309), .CK(clk), .RN(n5370), .Q(d_ff_Zn[6])
);
DFFRXLTS reg_val_muxZ_2stage_Q_reg_6_ ( .D(n2278), .CK(clk), .RN(n5372), .Q(
d_ff2_Z[6]) );
DFFRXLTS d_ff4_Yn_Q_reg_6_ ( .D(n2308), .CK(clk), .RN(n5360), .Q(d_ff_Yn[6]),
.QN(n5254) );
DFFRXLTS reg_shift_y_Q_reg_6_ ( .D(n2205), .CK(clk), .RN(n5381), .Q(
d_ff3_sh_y_out[6]) );
DFFRXLTS reg_shift_x_Q_reg_6_ ( .D(n2680), .CK(clk), .RN(n5373), .Q(
d_ff3_sh_x_out[6]) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_7_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[7]),
.CK(clk), .RN(n5322), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[62]) );
DFFRXLTS d_ff4_Zn_Q_reg_5_ ( .D(n2305), .CK(clk), .RN(n5356), .Q(d_ff_Zn[5])
);
DFFRXLTS d_ff4_Yn_Q_reg_5_ ( .D(n2304), .CK(clk), .RN(n5375), .Q(d_ff_Yn[5]),
.QN(n5253) );
DFFRXLTS reg_shift_y_Q_reg_5_ ( .D(n2207), .CK(clk), .RN(n5375), .Q(
d_ff3_sh_y_out[5]) );
DFFRXLTS reg_shift_x_Q_reg_5_ ( .D(n2678), .CK(clk), .RN(n5375), .Q(
d_ff3_sh_x_out[5]) );
DFFRXLTS d_ff4_Zn_Q_reg_45_ ( .D(n2465), .CK(clk), .RN(n5375), .Q(
d_ff_Zn[45]) );
DFFRXLTS d_ff4_Yn_Q_reg_45_ ( .D(n2464), .CK(clk), .RN(n5375), .Q(
d_ff_Yn[45]), .QN(n5292) );
DFFRXLTS reg_shift_y_Q_reg_45_ ( .D(n2127), .CK(clk), .RN(n5375), .Q(
d_ff3_sh_y_out[45]) );
DFFRXLTS reg_shift_x_Q_reg_45_ ( .D(n2758), .CK(clk), .RN(n5401), .Q(
d_ff3_sh_x_out[45]) );
DFFRXLTS d_ff5_Q_reg_45_ ( .D(n1999), .CK(clk), .RN(n5382), .Q(
sign_inv_out[45]) );
DFFRXLTS d_ff5_data_out_Q_reg_45_ ( .D(n1998), .CK(clk), .RN(n5398), .Q(
data_output[45]) );
DFFRXLTS d_ff4_Zn_Q_reg_20_ ( .D(n2365), .CK(clk), .RN(n5397), .Q(
d_ff_Zn[20]) );
DFFRXLTS d_ff4_Yn_Q_reg_20_ ( .D(n2364), .CK(clk), .RN(n5394), .Q(
d_ff_Yn[20]), .QN(n5268) );
DFFRXLTS reg_shift_y_Q_reg_20_ ( .D(n2177), .CK(clk), .RN(n5354), .Q(
d_ff3_sh_y_out[20]) );
DFFRXLTS reg_shift_x_Q_reg_20_ ( .D(n2708), .CK(clk), .RN(n5376), .Q(
d_ff3_sh_x_out[20]) );
DFFRXLTS d_ff4_Zn_Q_reg_13_ ( .D(n2337), .CK(clk), .RN(n5376), .Q(
d_ff_Zn[13]) );
DFFRXLTS d_ff4_Yn_Q_reg_13_ ( .D(n2336), .CK(clk), .RN(n5376), .Q(
d_ff_Yn[13]), .QN(n5261) );
DFFRXLTS reg_shift_y_Q_reg_13_ ( .D(n2191), .CK(clk), .RN(n5376), .Q(
d_ff3_sh_y_out[13]) );
DFFRXLTS reg_shift_x_Q_reg_13_ ( .D(n2694), .CK(clk), .RN(n5376), .Q(
d_ff3_sh_x_out[13]) );
DFFRXLTS d_ff4_Zn_Q_reg_10_ ( .D(n2325), .CK(clk), .RN(n5376), .Q(
d_ff_Zn[10]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_10_ ( .D(n2274), .CK(clk), .RN(n5376),
.Q(d_ff2_Z[10]) );
DFFRXLTS d_ff4_Yn_Q_reg_10_ ( .D(n2324), .CK(clk), .RN(n5376), .Q(
d_ff_Yn[10]), .QN(n5258) );
DFFRXLTS reg_shift_y_Q_reg_10_ ( .D(n2197), .CK(clk), .RN(n5377), .Q(
d_ff3_sh_y_out[10]) );
DFFRXLTS reg_shift_x_Q_reg_10_ ( .D(n2688), .CK(clk), .RN(n5377), .Q(
d_ff3_sh_x_out[10]) );
DFFRXLTS d_ff4_Zn_Q_reg_43_ ( .D(n2457), .CK(clk), .RN(n5377), .Q(
d_ff_Zn[43]) );
DFFRXLTS d_ff4_Yn_Q_reg_43_ ( .D(n2456), .CK(clk), .RN(n5377), .Q(
d_ff_Yn[43]), .QN(n5290) );
DFFRXLTS reg_shift_y_Q_reg_43_ ( .D(n2131), .CK(clk), .RN(n5377), .Q(
d_ff3_sh_y_out[43]) );
DFFRXLTS reg_shift_x_Q_reg_43_ ( .D(n2754), .CK(clk), .RN(n5378), .Q(
d_ff3_sh_x_out[43]) );
DFFRXLTS d_ff5_Q_reg_43_ ( .D(n2003), .CK(clk), .RN(n5378), .Q(
sign_inv_out[43]) );
DFFRXLTS d_ff5_data_out_Q_reg_43_ ( .D(n2002), .CK(clk), .RN(n5378), .Q(
data_output[43]) );
DFFRXLTS d_ff4_Zn_Q_reg_7_ ( .D(n2313), .CK(clk), .RN(n5378), .Q(d_ff_Zn[7])
);
DFFRXLTS d_ff4_Yn_Q_reg_7_ ( .D(n2312), .CK(clk), .RN(n5378), .Q(d_ff_Yn[7]),
.QN(n5255) );
DFFRXLTS reg_shift_y_Q_reg_7_ ( .D(n2203), .CK(clk), .RN(n5378), .Q(
d_ff3_sh_y_out[7]) );
DFFRXLTS reg_shift_x_Q_reg_7_ ( .D(n2682), .CK(clk), .RN(n5378), .Q(
d_ff3_sh_x_out[7]) );
DFFRXLTS d_ff4_Zn_Q_reg_40_ ( .D(n2445), .CK(clk), .RN(n5378), .Q(
d_ff_Zn[40]) );
DFFRXLTS d_ff4_Yn_Q_reg_40_ ( .D(n2444), .CK(clk), .RN(n5377), .Q(
d_ff_Yn[40]), .QN(n5287) );
DFFRXLTS reg_shift_y_Q_reg_40_ ( .D(n2137), .CK(clk), .RN(n5377), .Q(
d_ff3_sh_y_out[40]) );
DFFRXLTS reg_shift_x_Q_reg_40_ ( .D(n2748), .CK(clk), .RN(n5378), .Q(
d_ff3_sh_x_out[40]) );
DFFRXLTS d_ff5_Q_reg_40_ ( .D(n2009), .CK(clk), .RN(n5377), .Q(
sign_inv_out[40]) );
DFFRXLTS d_ff5_data_out_Q_reg_40_ ( .D(n2008), .CK(clk), .RN(n5378), .Q(
data_output[40]) );
DFFRXLTS d_ff4_Zn_Q_reg_38_ ( .D(n2437), .CK(clk), .RN(n5377), .Q(
d_ff_Zn[38]) );
DFFRXLTS d_ff4_Yn_Q_reg_38_ ( .D(n2436), .CK(clk), .RN(n5377), .Q(
d_ff_Yn[38]), .QN(n5285) );
DFFRXLTS reg_shift_y_Q_reg_38_ ( .D(n2141), .CK(clk), .RN(n5379), .Q(
d_ff3_sh_y_out[38]) );
DFFRXLTS reg_shift_x_Q_reg_38_ ( .D(n2744), .CK(clk), .RN(n5379), .Q(
d_ff3_sh_x_out[38]) );
DFFRXLTS d_ff5_Q_reg_38_ ( .D(n2013), .CK(clk), .RN(n5379), .Q(
sign_inv_out[38]) );
DFFRXLTS d_ff5_data_out_Q_reg_38_ ( .D(n2012), .CK(clk), .RN(n5379), .Q(
data_output[38]) );
DFFRXLTS d_ff4_Zn_Q_reg_12_ ( .D(n2333), .CK(clk), .RN(n5379), .Q(
d_ff_Zn[12]) );
DFFRXLTS d_ff4_Yn_Q_reg_12_ ( .D(n2332), .CK(clk), .RN(n5379), .Q(
d_ff_Yn[12]), .QN(n5260) );
DFFRXLTS reg_shift_y_Q_reg_12_ ( .D(n2193), .CK(clk), .RN(n5379), .Q(
d_ff3_sh_y_out[12]) );
DFFRXLTS reg_shift_x_Q_reg_12_ ( .D(n2692), .CK(clk), .RN(n5380), .Q(
d_ff3_sh_x_out[12]) );
DFFRXLTS d_ff4_Zn_Q_reg_11_ ( .D(n2329), .CK(clk), .RN(n5380), .Q(
d_ff_Zn[11]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_11_ ( .D(n2273), .CK(clk), .RN(n5380),
.Q(d_ff2_Z[11]) );
DFFRXLTS d_ff4_Yn_Q_reg_11_ ( .D(n2328), .CK(clk), .RN(n5380), .Q(
d_ff_Yn[11]), .QN(n5259) );
DFFRXLTS reg_shift_y_Q_reg_11_ ( .D(n2195), .CK(clk), .RN(n5380), .Q(
d_ff3_sh_y_out[11]) );
DFFRXLTS reg_shift_x_Q_reg_11_ ( .D(n2690), .CK(clk), .RN(n5380), .Q(
d_ff3_sh_x_out[11]) );
DFFRXLTS d_ff4_Zn_Q_reg_42_ ( .D(n2453), .CK(clk), .RN(n5380), .Q(
d_ff_Zn[42]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_42_ ( .D(n2242), .CK(clk), .RN(n5381),
.Q(d_ff2_Z[42]) );
DFFRXLTS d_ff4_Yn_Q_reg_42_ ( .D(n2452), .CK(clk), .RN(n5381), .Q(
d_ff_Yn[42]), .QN(n5289) );
DFFRXLTS reg_shift_y_Q_reg_42_ ( .D(n2133), .CK(clk), .RN(n5381), .Q(
d_ff3_sh_y_out[42]) );
DFFRXLTS reg_shift_x_Q_reg_42_ ( .D(n2752), .CK(clk), .RN(n5381), .Q(
d_ff3_sh_x_out[42]) );
DFFRXLTS d_ff5_Q_reg_42_ ( .D(n2005), .CK(clk), .RN(n5381), .Q(
sign_inv_out[42]) );
DFFRXLTS d_ff5_data_out_Q_reg_42_ ( .D(n2004), .CK(clk), .RN(n5381), .Q(
data_output[42]) );
DFFRXLTS d_ff4_Zn_Q_reg_8_ ( .D(n2317), .CK(clk), .RN(n5381), .Q(d_ff_Zn[8])
);
DFFRXLTS reg_val_muxZ_2stage_Q_reg_8_ ( .D(n2276), .CK(clk), .RN(n5381), .Q(
d_ff2_Z[8]) );
DFFRXLTS d_ff4_Yn_Q_reg_8_ ( .D(n2316), .CK(clk), .RN(n5381), .Q(d_ff_Yn[8]),
.QN(n5256) );
DFFRXLTS reg_shift_y_Q_reg_8_ ( .D(n2201), .CK(clk), .RN(n5382), .Q(
d_ff3_sh_y_out[8]) );
DFFRXLTS reg_shift_x_Q_reg_8_ ( .D(n2684), .CK(clk), .RN(n5382), .Q(
d_ff3_sh_x_out[8]) );
DFFRXLTS d_ff4_Zn_Q_reg_41_ ( .D(n2449), .CK(clk), .RN(n5382), .Q(
d_ff_Zn[41]) );
DFFRXLTS d_ff4_Yn_Q_reg_41_ ( .D(n2448), .CK(clk), .RN(n5382), .Q(
d_ff_Yn[41]), .QN(n5288) );
DFFRXLTS reg_shift_y_Q_reg_41_ ( .D(n2135), .CK(clk), .RN(n5382), .Q(
d_ff3_sh_y_out[41]) );
DFFRXLTS reg_shift_x_Q_reg_41_ ( .D(n2750), .CK(clk), .RN(n5383), .Q(
d_ff3_sh_x_out[41]) );
DFFRXLTS d_ff5_Q_reg_41_ ( .D(n2007), .CK(clk), .RN(n5383), .Q(
sign_inv_out[41]) );
DFFRXLTS d_ff5_data_out_Q_reg_41_ ( .D(n2006), .CK(clk), .RN(n5383), .Q(
data_output[41]) );
DFFRXLTS d_ff4_Zn_Q_reg_39_ ( .D(n2441), .CK(clk), .RN(n5383), .Q(
d_ff_Zn[39]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_39_ ( .D(n2245), .CK(clk), .RN(n5383),
.Q(d_ff2_Z[39]) );
DFFRXLTS d_ff4_Yn_Q_reg_39_ ( .D(n2440), .CK(clk), .RN(n5383), .Q(
d_ff_Yn[39]), .QN(n5286) );
DFFRXLTS reg_shift_y_Q_reg_39_ ( .D(n2139), .CK(clk), .RN(n5383), .Q(
d_ff3_sh_y_out[39]) );
DFFRXLTS reg_shift_x_Q_reg_39_ ( .D(n2746), .CK(clk), .RN(n5383), .Q(
d_ff3_sh_x_out[39]) );
DFFRXLTS d_ff4_Zn_Q_reg_37_ ( .D(n2433), .CK(clk), .RN(n5383), .Q(
d_ff_Zn[37]) );
DFFRXLTS d_ff4_Yn_Q_reg_37_ ( .D(n2432), .CK(clk), .RN(n5384), .Q(
d_ff_Yn[37]), .QN(n5284) );
DFFRXLTS reg_shift_y_Q_reg_37_ ( .D(n2143), .CK(clk), .RN(n5384), .Q(
d_ff3_sh_y_out[37]) );
DFFRXLTS reg_shift_x_Q_reg_37_ ( .D(n2742), .CK(clk), .RN(n5384), .Q(
d_ff3_sh_x_out[37]) );
DFFRXLTS d_ff5_Q_reg_37_ ( .D(n2015), .CK(clk), .RN(n5384), .Q(
sign_inv_out[37]) );
DFFRXLTS d_ff5_data_out_Q_reg_37_ ( .D(n2014), .CK(clk), .RN(n5384), .Q(
data_output[37]) );
DFFRXLTS d_ff5_Q_reg_39_ ( .D(n2011), .CK(clk), .RN(n5384), .Q(
sign_inv_out[39]) );
DFFRXLTS d_ff5_data_out_Q_reg_39_ ( .D(n2010), .CK(clk), .RN(n5384), .Q(
data_output[39]) );
DFFRXLTS d_ff4_Zn_Q_reg_19_ ( .D(n2361), .CK(clk), .RN(n5384), .Q(
d_ff_Zn[19]) );
DFFRXLTS d_ff4_Yn_Q_reg_19_ ( .D(n2360), .CK(clk), .RN(n5385), .Q(
d_ff_Yn[19]), .QN(n5267) );
DFFRXLTS reg_shift_y_Q_reg_19_ ( .D(n2179), .CK(clk), .RN(n5385), .Q(
d_ff3_sh_y_out[19]) );
DFFRXLTS reg_shift_x_Q_reg_19_ ( .D(n2706), .CK(clk), .RN(n5385), .Q(
d_ff3_sh_x_out[19]) );
DFFRXLTS d_ff4_Zn_Q_reg_34_ ( .D(n2421), .CK(clk), .RN(n5385), .Q(
d_ff_Zn[34]) );
DFFRXLTS d_ff4_Yn_Q_reg_34_ ( .D(n2420), .CK(clk), .RN(n5385), .Q(
d_ff_Yn[34]), .QN(n5281) );
DFFRXLTS reg_shift_y_Q_reg_34_ ( .D(n2149), .CK(clk), .RN(n5385), .Q(
d_ff3_sh_y_out[34]) );
DFFRXLTS reg_shift_x_Q_reg_34_ ( .D(n2736), .CK(clk), .RN(n5386), .Q(
d_ff3_sh_x_out[34]) );
DFFRXLTS d_ff4_Zn_Q_reg_23_ ( .D(n2377), .CK(clk), .RN(n5386), .Q(
d_ff_Zn[23]) );
DFFRXLTS d_ff4_Yn_Q_reg_23_ ( .D(n2376), .CK(clk), .RN(n5386), .Q(
d_ff_Yn[23]), .QN(n5271) );
DFFRXLTS reg_shift_y_Q_reg_23_ ( .D(n2171), .CK(clk), .RN(n5386), .Q(
d_ff3_sh_y_out[23]) );
DFFRXLTS reg_shift_x_Q_reg_23_ ( .D(n2714), .CK(clk), .RN(n5386), .Q(
d_ff3_sh_x_out[23]) );
DFFRXLTS d_ff4_Zn_Q_reg_30_ ( .D(n2405), .CK(clk), .RN(n5386), .Q(
d_ff_Zn[30]) );
DFFRXLTS d_ff4_Yn_Q_reg_30_ ( .D(n2404), .CK(clk), .RN(n5387), .Q(
d_ff_Yn[30]), .QN(n5277) );
DFFRXLTS reg_shift_y_Q_reg_30_ ( .D(n2157), .CK(clk), .RN(n5387), .Q(
d_ff3_sh_y_out[30]) );
DFFRXLTS reg_shift_x_Q_reg_30_ ( .D(n2728), .CK(clk), .RN(n5387), .Q(
d_ff3_sh_x_out[30]) );
DFFRXLTS d_ff4_Zn_Q_reg_35_ ( .D(n2425), .CK(clk), .RN(n5387), .Q(
d_ff_Zn[35]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_35_ ( .D(n2249), .CK(clk), .RN(n5387),
.Q(d_ff2_Z[35]) );
DFFRXLTS d_ff4_Yn_Q_reg_35_ ( .D(n2424), .CK(clk), .RN(n5387), .Q(
d_ff_Yn[35]), .QN(n5282) );
DFFRXLTS reg_shift_y_Q_reg_35_ ( .D(n2147), .CK(clk), .RN(n5387), .Q(
d_ff3_sh_y_out[35]) );
DFFRXLTS reg_shift_x_Q_reg_35_ ( .D(n2738), .CK(clk), .RN(n5388), .Q(
d_ff3_sh_x_out[35]) );
DFFRXLTS d_ff5_Q_reg_35_ ( .D(n2019), .CK(clk), .RN(n5388), .Q(
sign_inv_out[35]) );
DFFRXLTS d_ff5_data_out_Q_reg_35_ ( .D(n2018), .CK(clk), .RN(n5388), .Q(
data_output[35]) );
DFFRXLTS d_ff4_Zn_Q_reg_15_ ( .D(n2345), .CK(clk), .RN(n5388), .Q(
d_ff_Zn[15]) );
DFFRXLTS d_ff4_Yn_Q_reg_15_ ( .D(n2344), .CK(clk), .RN(n5388), .Q(
d_ff_Yn[15]), .QN(n5263) );
DFFRXLTS reg_shift_y_Q_reg_15_ ( .D(n2187), .CK(clk), .RN(n5388), .Q(
d_ff3_sh_y_out[15]) );
DFFRXLTS reg_shift_x_Q_reg_15_ ( .D(n2698), .CK(clk), .RN(n5389), .Q(
d_ff3_sh_x_out[15]) );
DFFRXLTS d_ff4_Zn_Q_reg_36_ ( .D(n2429), .CK(clk), .RN(n5389), .Q(
d_ff_Zn[36]) );
DFFRXLTS d_ff4_Yn_Q_reg_36_ ( .D(n2428), .CK(clk), .RN(n5389), .Q(
d_ff_Yn[36]), .QN(n5283) );
DFFRXLTS reg_shift_y_Q_reg_36_ ( .D(n2145), .CK(clk), .RN(n5389), .Q(
d_ff3_sh_y_out[36]) );
DFFRXLTS reg_shift_x_Q_reg_36_ ( .D(n2740), .CK(clk), .RN(n5389), .Q(
d_ff3_sh_x_out[36]) );
DFFRXLTS d_ff5_Q_reg_36_ ( .D(n2017), .CK(clk), .RN(n5389), .Q(
sign_inv_out[36]) );
DFFRXLTS d_ff5_data_out_Q_reg_36_ ( .D(n2016), .CK(clk), .RN(n5389), .Q(
data_output[36]) );
DFFRXLTS d_ff4_Zn_Q_reg_14_ ( .D(n2341), .CK(clk), .RN(n5389), .Q(
d_ff_Zn[14]) );
DFFRXLTS d_ff4_Yn_Q_reg_14_ ( .D(n2340), .CK(clk), .RN(n5390), .Q(
d_ff_Yn[14]), .QN(n5262) );
DFFRXLTS reg_shift_y_Q_reg_14_ ( .D(n2189), .CK(clk), .RN(n5390), .Q(
d_ff3_sh_y_out[14]) );
DFFRXLTS reg_shift_x_Q_reg_14_ ( .D(n2696), .CK(clk), .RN(n5390), .Q(
d_ff3_sh_x_out[14]) );
DFFRXLTS d_ff4_Zn_Q_reg_27_ ( .D(n2393), .CK(clk), .RN(n5390), .Q(
d_ff_Zn[27]) );
DFFRXLTS d_ff4_Yn_Q_reg_27_ ( .D(n2392), .CK(clk), .RN(n5390), .Q(
d_ff_Yn[27]), .QN(n5274) );
DFFRXLTS reg_shift_y_Q_reg_27_ ( .D(n2163), .CK(clk), .RN(n5390), .Q(
d_ff3_sh_y_out[27]) );
DFFRXLTS reg_shift_x_Q_reg_27_ ( .D(n2722), .CK(clk), .RN(n5391), .Q(
d_ff3_sh_x_out[27]) );
DFFRXLTS d_ff5_Q_reg_27_ ( .D(n2035), .CK(clk), .RN(n5391), .Q(
sign_inv_out[27]) );
DFFRXLTS d_ff5_data_out_Q_reg_27_ ( .D(n2034), .CK(clk), .RN(n5391), .Q(
data_output[27]) );
DFFRXLTS d_ff4_Zn_Q_reg_31_ ( .D(n2409), .CK(clk), .RN(n5391), .Q(
d_ff_Zn[31]) );
DFFRXLTS d_ff4_Yn_Q_reg_31_ ( .D(n2408), .CK(clk), .RN(n5391), .Q(
d_ff_Yn[31]), .QN(n5278) );
DFFRXLTS reg_shift_y_Q_reg_31_ ( .D(n2155), .CK(clk), .RN(n5391), .Q(
d_ff3_sh_y_out[31]) );
DFFRXLTS reg_shift_x_Q_reg_31_ ( .D(n2730), .CK(clk), .RN(n5392), .Q(
d_ff3_sh_x_out[31]) );
DFFRXLTS d_ff5_Q_reg_31_ ( .D(n2027), .CK(clk), .RN(n5392), .Q(
sign_inv_out[31]) );
DFFRXLTS d_ff5_data_out_Q_reg_31_ ( .D(n2026), .CK(clk), .RN(n5392), .Q(
data_output[31]) );
DFFRXLTS d_ff4_Zn_Q_reg_29_ ( .D(n2401), .CK(clk), .RN(n5392), .Q(
d_ff_Zn[29]) );
DFFRXLTS d_ff4_Yn_Q_reg_29_ ( .D(n2400), .CK(clk), .RN(n5392), .Q(
d_ff_Yn[29]), .QN(n5276) );
DFFRXLTS reg_shift_y_Q_reg_29_ ( .D(n2159), .CK(clk), .RN(n5392), .Q(
d_ff3_sh_y_out[29]) );
DFFRXLTS reg_shift_x_Q_reg_29_ ( .D(n2726), .CK(clk), .RN(n5392), .Q(
d_ff3_sh_x_out[29]) );
DFFRXLTS d_ff5_Q_reg_29_ ( .D(n2031), .CK(clk), .RN(n5392), .Q(
sign_inv_out[29]) );
DFFRXLTS d_ff5_data_out_Q_reg_29_ ( .D(n2030), .CK(clk), .RN(n5393), .Q(
data_output[29]) );
DFFRXLTS d_ff4_Zn_Q_reg_21_ ( .D(n2369), .CK(clk), .RN(n5393), .Q(
d_ff_Zn[21]) );
DFFRXLTS d_ff4_Yn_Q_reg_21_ ( .D(n2368), .CK(clk), .RN(n5393), .Q(
d_ff_Yn[21]), .QN(n5269) );
DFFRXLTS reg_shift_y_Q_reg_21_ ( .D(n2175), .CK(clk), .RN(n5393), .Q(
d_ff3_sh_y_out[21]) );
DFFRXLTS reg_shift_x_Q_reg_21_ ( .D(n2710), .CK(clk), .RN(n5393), .Q(
d_ff3_sh_x_out[21]) );
DFFRXLTS d_ff4_Zn_Q_reg_18_ ( .D(n2357), .CK(clk), .RN(n5393), .Q(
d_ff_Zn[18]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_18_ ( .D(n2266), .CK(clk), .RN(n5393),
.Q(d_ff2_Z[18]) );
DFFRXLTS d_ff4_Yn_Q_reg_18_ ( .D(n2356), .CK(clk), .RN(n5393), .Q(
d_ff_Yn[18]), .QN(n5266) );
DFFRXLTS reg_shift_y_Q_reg_18_ ( .D(n2181), .CK(clk), .RN(n5394), .Q(
d_ff3_sh_y_out[18]) );
DFFRXLTS reg_shift_x_Q_reg_18_ ( .D(n2704), .CK(clk), .RN(n5394), .Q(
d_ff3_sh_x_out[18]) );
DFFRXLTS d_ff4_Zn_Q_reg_25_ ( .D(n2385), .CK(clk), .RN(n5394), .Q(
d_ff_Zn[25]) );
DFFRXLTS d_ff4_Yn_Q_reg_25_ ( .D(n2384), .CK(clk), .RN(n5394), .Q(
d_ff_Yn[25]), .QN(n5245) );
DFFRXLTS reg_shift_y_Q_reg_25_ ( .D(n2167), .CK(clk), .RN(n5394), .Q(
d_ff3_sh_y_out[25]) );
DFFRXLTS reg_shift_x_Q_reg_25_ ( .D(n2718), .CK(clk), .RN(n5397), .Q(
d_ff3_sh_x_out[25]) );
DFFRXLTS d_ff5_Q_reg_25_ ( .D(n2039), .CK(clk), .RN(n5396), .Q(
sign_inv_out[25]) );
DFFRXLTS d_ff5_data_out_Q_reg_25_ ( .D(n2038), .CK(clk), .RN(n5394), .Q(
data_output[25]) );
DFFRXLTS d_ff4_Zn_Q_reg_33_ ( .D(n2417), .CK(clk), .RN(n5403), .Q(
d_ff_Zn[33]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_33_ ( .D(n2251), .CK(clk), .RN(n5402),
.Q(d_ff2_Z[33]) );
DFFRXLTS d_ff4_Yn_Q_reg_33_ ( .D(n2416), .CK(clk), .RN(n5401), .Q(
d_ff_Yn[33]), .QN(n5280) );
DFFRXLTS reg_shift_y_Q_reg_33_ ( .D(n2151), .CK(clk), .RN(n5399), .Q(
d_ff3_sh_y_out[33]) );
DFFRXLTS reg_shift_x_Q_reg_33_ ( .D(n2734), .CK(clk), .RN(n5396), .Q(
d_ff3_sh_x_out[33]) );
DFFRXLTS d_ff5_Q_reg_33_ ( .D(n2023), .CK(clk), .RN(n5394), .Q(
sign_inv_out[33]) );
DFFRXLTS d_ff5_data_out_Q_reg_33_ ( .D(n2022), .CK(clk), .RN(n5395), .Q(
data_output[33]) );
DFFRXLTS d_ff4_Zn_Q_reg_17_ ( .D(n2353), .CK(clk), .RN(n5395), .Q(
d_ff_Zn[17]) );
DFFRXLTS d_ff4_Yn_Q_reg_17_ ( .D(n2352), .CK(clk), .RN(n5395), .Q(
d_ff_Yn[17]), .QN(n5265) );
DFFRXLTS reg_shift_y_Q_reg_17_ ( .D(n2183), .CK(clk), .RN(n5395), .Q(
d_ff3_sh_y_out[17]) );
DFFRXLTS reg_shift_x_Q_reg_17_ ( .D(n2702), .CK(clk), .RN(n5395), .Q(
d_ff3_sh_x_out[17]) );
DFFRXLTS d_ff4_Zn_Q_reg_32_ ( .D(n2413), .CK(clk), .RN(n5395), .Q(
d_ff_Zn[32]) );
DFFRXLTS d_ff4_Yn_Q_reg_32_ ( .D(n2412), .CK(clk), .RN(n5395), .Q(
d_ff_Yn[32]), .QN(n5279) );
DFFRXLTS reg_shift_y_Q_reg_32_ ( .D(n2153), .CK(clk), .RN(n5396), .Q(
d_ff3_sh_y_out[32]) );
DFFRXLTS reg_shift_x_Q_reg_32_ ( .D(n2732), .CK(clk), .RN(n5396), .Q(
d_ff3_sh_x_out[32]) );
DFFRXLTS d_ff5_Q_reg_32_ ( .D(n2025), .CK(clk), .RN(n5396), .Q(
sign_inv_out[32]) );
DFFRXLTS d_ff5_data_out_Q_reg_32_ ( .D(n2024), .CK(clk), .RN(n5396), .Q(
data_output[32]) );
DFFRXLTS d_ff4_Zn_Q_reg_24_ ( .D(n2381), .CK(clk), .RN(n5396), .Q(
d_ff_Zn[24]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_24_ ( .D(n2260), .CK(clk), .RN(n5396),
.Q(d_ff2_Z[24]) );
DFFRXLTS d_ff4_Yn_Q_reg_24_ ( .D(n2380), .CK(clk), .RN(n5396), .Q(
d_ff_Yn[24]), .QN(n5272) );
DFFRXLTS reg_shift_y_Q_reg_24_ ( .D(n2169), .CK(clk), .RN(n5396), .Q(
d_ff3_sh_y_out[24]) );
DFFRXLTS reg_shift_x_Q_reg_24_ ( .D(n2716), .CK(clk), .RN(n5397), .Q(
d_ff3_sh_x_out[24]) );
DFFRXLTS d_ff4_Zn_Q_reg_22_ ( .D(n2373), .CK(clk), .RN(n5397), .Q(
d_ff_Zn[22]) );
DFFRXLTS d_ff4_Yn_Q_reg_22_ ( .D(n2372), .CK(clk), .RN(n5397), .Q(
d_ff_Yn[22]), .QN(n5270) );
DFFRXLTS reg_shift_y_Q_reg_22_ ( .D(n2173), .CK(clk), .RN(n5397), .Q(
d_ff3_sh_y_out[22]) );
DFFRXLTS reg_shift_x_Q_reg_22_ ( .D(n2712), .CK(clk), .RN(n5397), .Q(
d_ff3_sh_x_out[22]) );
DFFRXLTS d_ff4_Zn_Q_reg_28_ ( .D(n2397), .CK(clk), .RN(n5397), .Q(
d_ff_Zn[28]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_28_ ( .D(n2256), .CK(clk), .RN(n5398),
.Q(d_ff2_Z[28]) );
DFFRXLTS d_ff4_Yn_Q_reg_28_ ( .D(n2396), .CK(clk), .RN(n5398), .Q(
d_ff_Yn[28]), .QN(n5275) );
DFFRXLTS reg_shift_y_Q_reg_28_ ( .D(n2161), .CK(clk), .RN(n5398), .Q(
d_ff3_sh_y_out[28]) );
DFFRXLTS reg_shift_x_Q_reg_28_ ( .D(n2724), .CK(clk), .RN(n5398), .Q(
d_ff3_sh_x_out[28]) );
DFFRXLTS d_ff5_Q_reg_28_ ( .D(n2033), .CK(clk), .RN(n5398), .Q(
sign_inv_out[28]) );
DFFRXLTS d_ff5_data_out_Q_reg_28_ ( .D(n2032), .CK(clk), .RN(n5398), .Q(
data_output[28]) );
DFFRXLTS d_ff4_Zn_Q_reg_26_ ( .D(n2389), .CK(clk), .RN(n5398), .Q(
d_ff_Zn[26]) );
DFFRXLTS d_ff4_Yn_Q_reg_26_ ( .D(n2388), .CK(clk), .RN(n5398), .Q(
d_ff_Yn[26]), .QN(n5273) );
DFFRXLTS reg_shift_y_Q_reg_26_ ( .D(n2165), .CK(clk), .RN(n5399), .Q(
d_ff3_sh_y_out[26]) );
DFFRXLTS reg_shift_x_Q_reg_26_ ( .D(n2720), .CK(clk), .RN(n5399), .Q(
d_ff3_sh_x_out[26]) );
DFFRXLTS d_ff5_Q_reg_26_ ( .D(n2037), .CK(clk), .RN(n5399), .Q(
sign_inv_out[26]) );
DFFRXLTS d_ff5_data_out_Q_reg_26_ ( .D(n2036), .CK(clk), .RN(n5399), .Q(
data_output[26]) );
DFFRXLTS d_ff5_Q_reg_22_ ( .D(n2045), .CK(clk), .RN(n5399), .Q(
sign_inv_out[22]) );
DFFRXLTS d_ff5_data_out_Q_reg_22_ ( .D(n2044), .CK(clk), .RN(n5399), .Q(
data_output[22]) );
DFFRXLTS d_ff5_Q_reg_24_ ( .D(n2041), .CK(clk), .RN(n5399), .Q(
sign_inv_out[24]) );
DFFRXLTS d_ff5_data_out_Q_reg_24_ ( .D(n2040), .CK(clk), .RN(n5399), .Q(
data_output[24]) );
DFFRXLTS d_ff5_Q_reg_17_ ( .D(n2055), .CK(clk), .RN(n5399), .Q(
sign_inv_out[17]) );
DFFRXLTS d_ff5_data_out_Q_reg_17_ ( .D(n2054), .CK(clk), .RN(n5400), .Q(
data_output[17]) );
DFFRXLTS d_ff5_Q_reg_18_ ( .D(n2053), .CK(clk), .RN(n5400), .Q(
sign_inv_out[18]) );
DFFRXLTS d_ff5_data_out_Q_reg_18_ ( .D(n2052), .CK(clk), .RN(n5400), .Q(
data_output[18]) );
DFFRXLTS d_ff5_Q_reg_21_ ( .D(n2047), .CK(clk), .RN(n5400), .Q(
sign_inv_out[21]) );
DFFRXLTS d_ff5_data_out_Q_reg_21_ ( .D(n2046), .CK(clk), .RN(n5400), .Q(
data_output[21]) );
DFFRXLTS d_ff5_Q_reg_14_ ( .D(n2061), .CK(clk), .RN(n5400), .Q(
sign_inv_out[14]) );
DFFRXLTS d_ff5_data_out_Q_reg_14_ ( .D(n2060), .CK(clk), .RN(n5400), .Q(
data_output[14]) );
DFFRXLTS d_ff5_Q_reg_15_ ( .D(n2059), .CK(clk), .RN(n5400), .Q(
sign_inv_out[15]) );
DFFRXLTS d_ff5_data_out_Q_reg_15_ ( .D(n2058), .CK(clk), .RN(n5400), .Q(
data_output[15]) );
DFFRXLTS d_ff5_Q_reg_30_ ( .D(n2029), .CK(clk), .RN(n5400), .Q(
sign_inv_out[30]) );
DFFRXLTS d_ff5_data_out_Q_reg_30_ ( .D(n2028), .CK(clk), .RN(n5400), .Q(
data_output[30]) );
DFFRXLTS d_ff5_Q_reg_23_ ( .D(n2043), .CK(clk), .RN(n5400), .Q(
sign_inv_out[23]) );
DFFRXLTS d_ff5_data_out_Q_reg_23_ ( .D(n2042), .CK(clk), .RN(n5401), .Q(
data_output[23]) );
DFFRXLTS d_ff5_Q_reg_34_ ( .D(n2021), .CK(clk), .RN(n5401), .Q(
sign_inv_out[34]) );
DFFRXLTS d_ff5_data_out_Q_reg_34_ ( .D(n2020), .CK(clk), .RN(n5401), .Q(
data_output[34]) );
DFFRXLTS d_ff5_Q_reg_19_ ( .D(n2051), .CK(clk), .RN(n5401), .Q(
sign_inv_out[19]) );
DFFRXLTS d_ff5_data_out_Q_reg_19_ ( .D(n2050), .CK(clk), .RN(n5401), .Q(
data_output[19]) );
DFFRXLTS d_ff5_Q_reg_8_ ( .D(n2073), .CK(clk), .RN(n5401), .Q(
sign_inv_out[8]) );
DFFRXLTS d_ff5_data_out_Q_reg_8_ ( .D(n2072), .CK(clk), .RN(n5401), .Q(
data_output[8]) );
DFFRXLTS d_ff5_Q_reg_11_ ( .D(n2067), .CK(clk), .RN(n5401), .Q(
sign_inv_out[11]) );
DFFRXLTS d_ff5_data_out_Q_reg_11_ ( .D(n2066), .CK(clk), .RN(n5401), .Q(
data_output[11]) );
DFFRXLTS d_ff5_Q_reg_12_ ( .D(n2065), .CK(clk), .RN(n5401), .Q(
sign_inv_out[12]) );
DFFRXLTS d_ff5_data_out_Q_reg_12_ ( .D(n2064), .CK(clk), .RN(n5401), .Q(
data_output[12]) );
DFFRXLTS d_ff5_Q_reg_7_ ( .D(n2075), .CK(clk), .RN(n5401), .Q(
sign_inv_out[7]) );
DFFRXLTS d_ff5_data_out_Q_reg_7_ ( .D(n2074), .CK(clk), .RN(n5402), .Q(
data_output[7]) );
DFFRXLTS d_ff5_Q_reg_10_ ( .D(n2069), .CK(clk), .RN(n5402), .Q(
sign_inv_out[10]) );
DFFRXLTS d_ff5_data_out_Q_reg_10_ ( .D(n2068), .CK(clk), .RN(n5402), .Q(
data_output[10]) );
DFFRXLTS d_ff5_Q_reg_13_ ( .D(n2063), .CK(clk), .RN(n5402), .Q(
sign_inv_out[13]) );
DFFRXLTS d_ff5_data_out_Q_reg_13_ ( .D(n2062), .CK(clk), .RN(n5402), .Q(
data_output[13]) );
DFFRXLTS d_ff5_Q_reg_20_ ( .D(n2049), .CK(clk), .RN(n5402), .Q(
sign_inv_out[20]) );
DFFRXLTS d_ff5_data_out_Q_reg_20_ ( .D(n2048), .CK(clk), .RN(n5402), .Q(
data_output[20]) );
DFFRXLTS d_ff5_Q_reg_5_ ( .D(n2079), .CK(clk), .RN(n5402), .Q(
sign_inv_out[5]) );
DFFRXLTS d_ff5_data_out_Q_reg_5_ ( .D(n2078), .CK(clk), .RN(n5402), .Q(
data_output[5]) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_6_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[6]),
.CK(clk), .RN(n5345), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[61]) );
DFFRXLTS d_ff5_Q_reg_6_ ( .D(n2077), .CK(clk), .RN(n5402), .Q(
sign_inv_out[6]) );
DFFRXLTS d_ff5_data_out_Q_reg_6_ ( .D(n2076), .CK(clk), .RN(n5402), .Q(
data_output[6]) );
DFFRXLTS d_ff5_Q_reg_9_ ( .D(n2071), .CK(clk), .RN(n5402), .Q(
sign_inv_out[9]) );
DFFRXLTS d_ff5_data_out_Q_reg_9_ ( .D(n2070), .CK(clk), .RN(n5403), .Q(
data_output[9]) );
DFFRXLTS d_ff5_Q_reg_16_ ( .D(n2057), .CK(clk), .RN(n5403), .Q(
sign_inv_out[16]) );
DFFRXLTS d_ff5_data_out_Q_reg_16_ ( .D(n2056), .CK(clk), .RN(n5403), .Q(
data_output[16]) );
DFFRXLTS d_ff5_Q_reg_1_ ( .D(n2087), .CK(clk), .RN(n5403), .Q(
sign_inv_out[1]) );
DFFRXLTS d_ff5_data_out_Q_reg_1_ ( .D(n2086), .CK(clk), .RN(n5403), .Q(
data_output[1]) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_5_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[5]),
.CK(clk), .RN(n5347), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[60]) );
DFFRXLTS d_ff5_Q_reg_3_ ( .D(n2083), .CK(clk), .RN(n5403), .Q(
sign_inv_out[3]) );
DFFRXLTS d_ff5_data_out_Q_reg_3_ ( .D(n2082), .CK(clk), .RN(n5403), .Q(
data_output[3]) );
DFFRXLTS d_ff5_Q_reg_50_ ( .D(n1989), .CK(clk), .RN(n5403), .Q(
sign_inv_out[50]) );
DFFRXLTS d_ff5_data_out_Q_reg_50_ ( .D(n1988), .CK(clk), .RN(n5403), .Q(
data_output[50]) );
DFFRXLTS d_ff5_Q_reg_2_ ( .D(n2085), .CK(clk), .RN(n5403), .Q(
sign_inv_out[2]) );
DFFRXLTS d_ff5_data_out_Q_reg_2_ ( .D(n2084), .CK(clk), .RN(n5403), .Q(
data_output[2]) );
DFFRXLTS d_ff5_Q_reg_4_ ( .D(n2081), .CK(clk), .RN(n5403), .Q(
sign_inv_out[4]) );
DFFRXLTS d_ff5_data_out_Q_reg_4_ ( .D(n2080), .CK(clk), .RN(n5361), .Q(
data_output[4]) );
DFFRXLTS d_ff5_Q_reg_51_ ( .D(n1987), .CK(clk), .RN(n5403), .Q(
sign_inv_out[51]) );
DFFRXLTS d_ff5_data_out_Q_reg_51_ ( .D(n1986), .CK(clk), .RN(n5402), .Q(
data_output[51]) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_0_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[0]),
.CK(clk), .RN(n5334), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[55]) );
DFFRXLTS reg_shift_y_Q_reg_0_ ( .D(n2217), .CK(clk), .RN(n5398), .Q(
d_ff3_sh_y_out[0]) );
DFFRXLTS d_ff5_Q_reg_0_ ( .D(n2089), .CK(clk), .RN(n5400), .Q(
sign_inv_out[0]) );
DFFRXLTS d_ff5_data_out_Q_reg_0_ ( .D(n2088), .CK(clk), .RN(n5401), .Q(
data_output[0]) );
DFFRXLTS add_subt_module_YRegister_Q_reg_63_ ( .D(n1946), .CK(clk), .RN(
n5335), .Q(add_subt_module_intDY[63]) );
DFFRXLTS add_subt_module_ASRegister_Q_reg_0_ ( .D(n1944), .CK(clk), .RN(
n5336), .Q(add_subt_module_intAS) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_62_ ( .D(n1940), .CK(clk), .RN(n5339), .Q(add_subt_module_DMP[62]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_61_ ( .D(n1937), .CK(clk), .RN(n5339), .Q(add_subt_module_DMP[61]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_60_ ( .D(n1934), .CK(clk), .RN(n5339), .Q(add_subt_module_DMP[60]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_59_ ( .D(n1932), .CK(clk), .RN(n5338), .Q(add_subt_module_DmP[59]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_59_ ( .D(n1931), .CK(clk), .RN(n5404), .Q(add_subt_module_DMP[59]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_58_ ( .D(n1929), .CK(clk), .RN(n5338), .Q(add_subt_module_DmP[58]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_58_ ( .D(n1928), .CK(clk), .RN(n5404), .Q(add_subt_module_DMP[58]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_57_ ( .D(n1926), .CK(clk), .RN(n5338), .Q(add_subt_module_DmP[57]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_57_ ( .D(n1925), .CK(clk), .RN(n5328), .Q(add_subt_module_DMP[57]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_56_ ( .D(n1923), .CK(clk), .RN(n5338), .Q(add_subt_module_DmP[56]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_55_ ( .D(n1920), .CK(clk), .RN(n5335), .Q(add_subt_module_DmP[55]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_54_ ( .D(n1917), .CK(clk), .RN(n5329), .Q(add_subt_module_DmP[54]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_54_ ( .D(n1916), .CK(clk), .RN(n5317), .Q(add_subt_module_DMP[54]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_53_ ( .D(n1914), .CK(clk), .RN(n5328), .Q(add_subt_module_DmP[53]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_53_ ( .D(n1913), .CK(clk), .RN(n5338), .Q(add_subt_module_DMP[53]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_52_ ( .D(n1911), .CK(clk), .RN(n5336), .Q(add_subt_module_DmP[52]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_52_ ( .D(n1910), .CK(clk), .RN(n5338), .Q(add_subt_module_DMP[52]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_50_ ( .D(n1892), .CK(clk), .RN(n5319), .Q(add_subt_module_DmP[50]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_49_ ( .D(n1879), .CK(clk), .RN(n5320), .Q(add_subt_module_DmP[49]), .QN(n5208) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_46_ ( .D(n1875), .CK(clk), .RN(n5343), .Q(add_subt_module_DmP[46]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_9_ ( .D(n1868),
.CK(clk), .RN(n5342), .Q(add_subt_module_DmP[9]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_5_ ( .D(n1858),
.CK(clk), .RN(n5343), .Q(add_subt_module_DmP[5]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_10_ ( .D(n1845), .CK(clk), .RN(n5321), .Q(add_subt_module_DmP[10]), .QN(n5211) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_41_ ( .D(n1814), .CK(clk), .RN(n5323), .Q(add_subt_module_DmP[41]), .QN(n5209) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_37_ ( .D(n1806), .CK(clk), .RN(n5336), .Q(add_subt_module_DMP[37]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_39_ ( .D(n1805), .CK(clk), .RN(n5335), .Q(add_subt_module_DMP[39]) );
DFFRXLTS add_subt_module_YRegister_Q_reg_30_ ( .D(n1794), .CK(clk), .RN(
n5325), .QN(n2962) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_30_ ( .D(n1793), .CK(clk), .RN(n5325), .Q(add_subt_module_DmP[30]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_35_ ( .D(n1789), .CK(clk), .RN(n5336), .Q(add_subt_module_DMP[35]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_15_ ( .D(n1786), .CK(clk), .RN(n5325), .Q(add_subt_module_DmP[15]), .QN(n5210) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_27_ ( .D(n1775), .CK(clk), .RN(n5334), .Q(add_subt_module_DMP[27]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_31_ ( .D(n1771), .CK(clk), .RN(n5336), .Q(add_subt_module_DMP[31]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_29_ ( .D(n1767), .CK(clk), .RN(n5346), .Q(add_subt_module_DMP[29]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_21_ ( .D(n1764), .CK(clk), .RN(n5326), .Q(add_subt_module_DmP[21]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_25_ ( .D(n1757), .CK(clk), .RN(n5321), .Q(add_subt_module_DMP[25]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_33_ ( .D(n1753), .CK(clk), .RN(n5346), .Q(add_subt_module_DMP[33]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_17_ ( .D(n1750), .CK(clk), .RN(n5327), .Q(add_subt_module_DmP[17]) );
DFFRXLTS add_subt_module_YRegister_Q_reg_32_ ( .D(n1748), .CK(clk), .RN(
n5327), .QN(n2964) );
DFFRXLTS add_subt_module_YRegister_Q_reg_24_ ( .D(n1744), .CK(clk), .RN(
n5327), .QN(n2961) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_24_ ( .D(n1743), .CK(clk), .RN(n5327), .Q(add_subt_module_DmP[24]) );
DFFRXLTS add_subt_module_YRegister_Q_reg_22_ ( .D(n1741), .CK(clk), .RN(
n5327), .QN(n2963) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_0_ ( .D(n1703),
.CK(clk), .RN(n5331), .Q(add_subt_module_DMP[0]) );
CMPR32X2TS DP_OP_92J137_122_9081_U12 ( .A(add_subt_module_S_Oper_A_exp[0]),
.B(add_subt_module_FSM_exp_operation_A_S), .C(
DP_OP_92J137_122_9081_n26), .CO(DP_OP_92J137_122_9081_n11), .S(
add_subt_module_Exp_Operation_Module_Data_S[0]) );
CMPR32X2TS DP_OP_92J137_122_9081_U11 ( .A(DP_OP_92J137_122_9081_n25), .B(
add_subt_module_S_Oper_A_exp[1]), .C(DP_OP_92J137_122_9081_n11), .CO(
DP_OP_92J137_122_9081_n10), .S(
add_subt_module_Exp_Operation_Module_Data_S[1]) );
CMPR32X2TS DP_OP_92J137_122_9081_U10 ( .A(DP_OP_92J137_122_9081_n24), .B(
add_subt_module_S_Oper_A_exp[2]), .C(DP_OP_92J137_122_9081_n10), .CO(
DP_OP_92J137_122_9081_n9), .S(
add_subt_module_Exp_Operation_Module_Data_S[2]) );
CMPR32X2TS DP_OP_92J137_122_9081_U9 ( .A(DP_OP_92J137_122_9081_n23), .B(
add_subt_module_S_Oper_A_exp[3]), .C(DP_OP_92J137_122_9081_n9), .CO(
DP_OP_92J137_122_9081_n8), .S(
add_subt_module_Exp_Operation_Module_Data_S[3]) );
CMPR32X2TS DP_OP_92J137_122_9081_U8 ( .A(DP_OP_92J137_122_9081_n22), .B(
add_subt_module_S_Oper_A_exp[4]), .C(DP_OP_92J137_122_9081_n8), .CO(
DP_OP_92J137_122_9081_n7), .S(
add_subt_module_Exp_Operation_Module_Data_S[4]) );
CMPR32X2TS DP_OP_92J137_122_9081_U7 ( .A(DP_OP_92J137_122_9081_n21), .B(
add_subt_module_S_Oper_A_exp[5]), .C(DP_OP_92J137_122_9081_n7), .CO(
DP_OP_92J137_122_9081_n6), .S(
add_subt_module_Exp_Operation_Module_Data_S[5]) );
CMPR32X2TS DP_OP_92J137_122_9081_U6 ( .A(DP_OP_92J137_122_9081_n20), .B(
add_subt_module_S_Oper_A_exp[6]), .C(DP_OP_92J137_122_9081_n6), .CO(
DP_OP_92J137_122_9081_n5), .S(
add_subt_module_Exp_Operation_Module_Data_S[6]) );
CMPR32X2TS DP_OP_92J137_122_9081_U5 ( .A(DP_OP_92J137_122_9081_n19), .B(
add_subt_module_S_Oper_A_exp[7]), .C(DP_OP_92J137_122_9081_n5), .CO(
DP_OP_92J137_122_9081_n4), .S(
add_subt_module_Exp_Operation_Module_Data_S[7]) );
CMPR32X2TS DP_OP_92J137_122_9081_U4 ( .A(DP_OP_92J137_122_9081_n18), .B(
add_subt_module_S_Oper_A_exp[8]), .C(DP_OP_92J137_122_9081_n4), .CO(
DP_OP_92J137_122_9081_n3), .S(
add_subt_module_Exp_Operation_Module_Data_S[8]) );
CMPR32X2TS DP_OP_92J137_122_9081_U3 ( .A(DP_OP_92J137_122_9081_n17), .B(
add_subt_module_S_Oper_A_exp[9]), .C(DP_OP_92J137_122_9081_n3), .CO(
DP_OP_92J137_122_9081_n2), .S(
add_subt_module_Exp_Operation_Module_Data_S[9]) );
CMPR32X2TS DP_OP_92J137_122_9081_U2 ( .A(DP_OP_92J137_122_9081_n16), .B(
add_subt_module_S_Oper_A_exp[10]), .C(DP_OP_92J137_122_9081_n2), .CO(
DP_OP_92J137_122_9081_n1), .S(
add_subt_module_Exp_Operation_Module_Data_S[10]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_SignRegister_Q_reg_0_ ( .D(
n1943), .CK(clk), .RN(n5404), .Q(add_subt_module_sign_final_result),
.QN(n5243) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_37_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[37]),
.CK(clk), .RN(n5318), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[92]), .QN(
n5239) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_18_ ( .D(
n2614), .CK(clk), .RN(n5330), .Q(add_subt_module_Add_Subt_result[18]),
.QN(n5238) );
DFFRX2TS add_subt_module_YRegister_Q_reg_51_ ( .D(n1906), .CK(clk), .RN(
n5340), .Q(add_subt_module_intDY[51]), .QN(n5236) );
DFFRX1TS add_subt_module_YRegister_Q_reg_48_ ( .D(n1900), .CK(clk), .RN(
n5319), .Q(add_subt_module_intDY[48]), .QN(n5235) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_52_ ( .D(
n2587), .CK(clk), .RN(n5322), .Q(
add_subt_module_Sgf_normalized_result[52]), .QN(n5234) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_53_ ( .D(
n2588), .CK(clk), .RN(n5323), .Q(
add_subt_module_Sgf_normalized_result[53]), .QN(n5233) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_20_ ( .D(
n2616), .CK(clk), .RN(n5329), .Q(add_subt_module_Add_Subt_result[20]),
.QN(n5231) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_2_ ( .D(
n2598), .CK(clk), .RN(n5330), .Q(add_subt_module_Add_Subt_result[2]),
.QN(n5230) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_39_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[39]),
.CK(clk), .RN(n5351), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[94]), .QN(
n5229) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_50_ ( .D(
n2585), .CK(clk), .RN(n5344), .Q(
add_subt_module_Sgf_normalized_result[50]), .QN(n5225) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_51_ ( .D(
n2586), .CK(clk), .RN(n5327), .Q(
add_subt_module_Sgf_normalized_result[51]), .QN(n5224) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_6_ ( .D(
n2602), .CK(clk), .RN(n5330), .Q(add_subt_module_Add_Subt_result[6]),
.QN(n5223) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_16_ ( .D(
n2612), .CK(clk), .RN(n5347), .Q(add_subt_module_Add_Subt_result[16]),
.QN(n5222) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_1_ ( .D(
n2597), .CK(clk), .RN(n5330), .Q(add_subt_module_Add_Subt_result[1]),
.QN(n5221) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_40_ ( .D(
n2636), .CK(clk), .RN(n5351), .Q(add_subt_module_Add_Subt_result[40]),
.QN(n5220) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_32_ ( .D(
n2628), .CK(clk), .RN(n5329), .Q(add_subt_module_Add_Subt_result[32]),
.QN(n5219) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_46_ ( .D(
n2642), .CK(clk), .RN(n5315), .Q(add_subt_module_Add_Subt_result[46]),
.QN(n5218) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_4_ ( .D(
n2600), .CK(clk), .RN(n5330), .Q(add_subt_module_Add_Subt_result[4]),
.QN(n5217) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_41_ ( .D(
n2637), .CK(clk), .RN(n5324), .Q(add_subt_module_Add_Subt_result[41]),
.QN(n5215) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_35_ ( .D(
n2631), .CK(clk), .RN(n5329), .Q(add_subt_module_Add_Subt_result[35]),
.QN(n5213) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_49_ ( .D(
n2584), .CK(clk), .RN(n5337), .Q(
add_subt_module_Sgf_normalized_result[49]), .QN(n5207) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_49_ ( .D(
n2645), .CK(clk), .RN(n5330), .Q(add_subt_module_Add_Subt_result[49]),
.QN(n5206) );
DFFRX2TS cont_var_count_reg_0_ ( .D(n2926), .CK(clk), .RN(n5352), .Q(
cont_var_out[0]), .QN(n5205) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_28_ ( .D(
n2624), .CK(clk), .RN(n5328), .Q(add_subt_module_Add_Subt_result[28]),
.QN(n5204) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_47_ ( .D(
n2582), .CK(clk), .RN(n5351), .Q(
add_subt_module_Sgf_normalized_result[47]), .QN(n5203) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_48_ ( .D(
n2583), .CK(clk), .RN(n5347), .Q(
add_subt_module_Sgf_normalized_result[48]), .QN(n5202) );
DFFRX1TS add_subt_module_YRegister_Q_reg_0_ ( .D(n1958), .CK(clk), .RN(n5341), .Q(add_subt_module_intDY[0]), .QN(n5201) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_9_ ( .D(
n2605), .CK(clk), .RN(n5338), .Q(add_subt_module_Add_Subt_result[9]),
.QN(n5200) );
DFFRX1TS add_subt_module_XRegister_Q_reg_51_ ( .D(n1907), .CK(clk), .RN(
n5349), .Q(add_subt_module_intDX[51]), .QN(n5199) );
DFFRX1TS add_subt_module_XRegister_Q_reg_48_ ( .D(n1901), .CK(clk), .RN(
n5319), .Q(add_subt_module_intDX[48]), .QN(n5198) );
DFFRX1TS add_subt_module_XRegister_Q_reg_4_ ( .D(n1904), .CK(clk), .RN(n5319), .Q(add_subt_module_intDX[4]), .QN(n5197) );
DFFRX2TS add_subt_module_XRegister_Q_reg_12_ ( .D(n1829), .CK(clk), .RN(
n5322), .Q(add_subt_module_intDX[12]), .QN(n5196) );
DFFRX1TS add_subt_module_XRegister_Q_reg_32_ ( .D(n1749), .CK(clk), .RN(
n5327), .Q(add_subt_module_intDX[32]), .QN(n5195) );
DFFRX2TS add_subt_module_XRegister_Q_reg_29_ ( .D(n1770), .CK(clk), .RN(
n5332), .Q(add_subt_module_intDX[29]), .QN(n5194) );
DFFRX1TS add_subt_module_YRegister_Q_reg_54_ ( .D(n1949), .CK(clk), .RN(
n5340), .Q(add_subt_module_intDY[54]), .QN(n5193) );
DFFRX2TS add_subt_module_XRegister_Q_reg_25_ ( .D(n1760), .CK(clk), .RN(
n5326), .Q(add_subt_module_intDX[25]), .QN(n5192) );
DFFRX2TS add_subt_module_XRegister_Q_reg_35_ ( .D(n1792), .CK(clk), .RN(
n5325), .Q(add_subt_module_intDX[35]), .QN(n5191) );
DFFRX2TS add_subt_module_XRegister_Q_reg_45_ ( .D(n1857), .CK(clk), .RN(
n5343), .Q(add_subt_module_intDX[45]), .QN(n5190) );
DFFRX1TS add_subt_module_XRegister_Q_reg_2_ ( .D(n1897), .CK(clk), .RN(n5319), .Q(add_subt_module_intDX[2]), .QN(n5189) );
DFFRX2TS add_subt_module_XRegister_Q_reg_3_ ( .D(n1887), .CK(clk), .RN(n5320), .Q(add_subt_module_intDX[3]), .QN(n5188) );
DFFRX2TS add_subt_module_XRegister_Q_reg_8_ ( .D(n1819), .CK(clk), .RN(n5323), .Q(add_subt_module_intDX[8]), .QN(n5187) );
DFFRX2TS add_subt_module_XRegister_Q_reg_18_ ( .D(n1763), .CK(clk), .RN(
n5326), .Q(add_subt_module_intDX[18]), .QN(n5186) );
DFFRX2TS add_subt_module_YRegister_Q_reg_60_ ( .D(n1955), .CK(clk), .RN(
n5314), .Q(add_subt_module_intDY[60]), .QN(n5185) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_45_ ( .D(
n2580), .CK(clk), .RN(n5336), .Q(
add_subt_module_Sgf_normalized_result[45]), .QN(n5184) );
DFFRX1TS add_subt_module_XRegister_Q_reg_13_ ( .D(n1850), .CK(clk), .RN(
n5321), .Q(add_subt_module_intDX[13]), .QN(n5181) );
DFFRX2TS add_subt_module_YRegister_Q_reg_13_ ( .D(n1849), .CK(clk), .RN(
n5321), .Q(add_subt_module_intDY[13]), .QN(n5180) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_50_ ( .D(
n2646), .CK(clk), .RN(n5330), .Q(add_subt_module_Add_Subt_result[50]),
.QN(n5179) );
DFFRX2TS add_subt_module_XRegister_Q_reg_14_ ( .D(n1781), .CK(clk), .RN(
n5345), .Q(add_subt_module_intDX[14]), .QN(n5178) );
DFFRX2TS add_subt_module_XRegister_Q_reg_23_ ( .D(n1798), .CK(clk), .RN(
n5324), .Q(add_subt_module_intDX[23]), .QN(n5177) );
DFFRX2TS add_subt_module_XRegister_Q_reg_17_ ( .D(n1752), .CK(clk), .RN(
n5327), .Q(add_subt_module_intDX[17]), .QN(n5176) );
DFFRX2TS add_subt_module_XRegister_Q_reg_26_ ( .D(n1735), .CK(clk), .RN(
n5328), .Q(add_subt_module_intDX[26]), .QN(n5175) );
DFFRX2TS add_subt_module_XRegister_Q_reg_43_ ( .D(n1844), .CK(clk), .RN(
n5321), .Q(add_subt_module_intDX[43]), .QN(n5174) );
DFFRX2TS add_subt_module_XRegister_Q_reg_30_ ( .D(n1795), .CK(clk), .RN(
n5325), .Q(add_subt_module_intDX[30]), .QN(n5173) );
DFFRX2TS add_subt_module_XRegister_Q_reg_11_ ( .D(n1826), .CK(clk), .RN(
n5322), .Q(add_subt_module_intDX[11]), .QN(n5172) );
DFFRX2TS add_subt_module_XRegister_Q_reg_33_ ( .D(n1756), .CK(clk), .RN(
n5326), .Q(add_subt_module_intDX[33]), .QN(n5171) );
DFFRX2TS add_subt_module_XRegister_Q_reg_36_ ( .D(n1785), .CK(clk), .RN(
n5325), .Q(add_subt_module_intDX[36]), .QN(n5170) );
DFFRX2TS add_subt_module_YRegister_Q_reg_61_ ( .D(n1956), .CK(clk), .RN(
n5348), .QN(n5169) );
DFFRX2TS cordic_FSM_state_reg_reg_2_ ( .D(n2939), .CK(clk), .RN(n5344), .Q(
cordic_FSM_state_reg[2]), .QN(n5168) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_44_ ( .D(
n2579), .CK(clk), .RN(n5337), .Q(
add_subt_module_Sgf_normalized_result[44]), .QN(n5166) );
DFFRX2TS add_subt_module_XRegister_Q_reg_20_ ( .D(n1853), .CK(clk), .RN(
n5345), .Q(add_subt_module_intDX[20]), .QN(n5165) );
DFFRX2TS add_subt_module_XRegister_Q_reg_28_ ( .D(n1739), .CK(clk), .RN(
n5328), .Q(add_subt_module_intDX[28]), .QN(n5164) );
DFFRX2TS add_subt_module_YRegister_Q_reg_52_ ( .D(n1947), .CK(clk), .RN(
n5347), .Q(add_subt_module_intDY[52]), .QN(n5163) );
DFFRX2TS add_subt_module_XRegister_Q_reg_21_ ( .D(n1766), .CK(clk), .RN(
n5326), .Q(add_subt_module_intDX[21]), .QN(n5162) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_13_ ( .D(
n2609), .CK(clk), .RN(n5341), .Q(add_subt_module_Add_Subt_result[13]),
.QN(n5161) );
DFFRX2TS add_subt_module_YRegister_Q_reg_16_ ( .D(n1872), .CK(clk), .RN(
n5345), .Q(add_subt_module_intDY[16]), .QN(n5160) );
DFFRX2TS add_subt_module_XRegister_Q_reg_59_ ( .D(n1933), .CK(clk), .RN(
n5348), .Q(add_subt_module_intDX[59]), .QN(n5159) );
DFFRX2TS add_subt_module_XRegister_Q_reg_49_ ( .D(n1881), .CK(clk), .RN(
n5320), .Q(add_subt_module_intDX[49]), .QN(n5158) );
DFFRX2TS add_subt_module_XRegister_Q_reg_41_ ( .D(n1816), .CK(clk), .RN(
n5323), .Q(add_subt_module_intDX[41]), .QN(n5157) );
DFFRX1TS add_subt_module_XRegister_Q_reg_10_ ( .D(n1847), .CK(clk), .RN(
n5321), .Q(add_subt_module_intDX[10]), .QN(n5156) );
DFFRX1TS add_subt_module_XRegister_Q_reg_5_ ( .D(n1860), .CK(clk), .RN(n5342), .Q(add_subt_module_intDX[5]), .QN(n5155) );
DFFRX1TS add_subt_module_XRegister_Q_reg_9_ ( .D(n1870), .CK(clk), .RN(n5336), .Q(add_subt_module_intDX[9]), .QN(n5154) );
DFFRX1TS add_subt_module_XRegister_Q_reg_37_ ( .D(n1809), .CK(clk), .RN(
n5324), .Q(add_subt_module_intDX[37]), .QN(n5153) );
DFFRX1TS add_subt_module_XRegister_Q_reg_40_ ( .D(n1837), .CK(clk), .RN(
n5322), .Q(add_subt_module_intDX[40]), .QN(n5152) );
DFFRX2TS add_subt_module_XRegister_Q_reg_46_ ( .D(n1877), .CK(clk), .RN(
n5336), .Q(add_subt_module_intDX[46]), .QN(n5151) );
DFFRX1TS add_subt_module_YRegister_Q_reg_56_ ( .D(n1951), .CK(clk), .RN(
n5348), .Q(add_subt_module_intDY[56]), .QN(n5150) );
DFFRX1TS add_subt_module_XRegister_Q_reg_7_ ( .D(n1840), .CK(clk), .RN(n5321), .Q(add_subt_module_intDX[7]), .QN(n5149) );
DFFRX1TS add_subt_module_YRegister_Q_reg_55_ ( .D(n1950), .CK(clk), .RN(
n5349), .Q(add_subt_module_intDY[55]), .QN(n5148) );
DFFRX1TS add_subt_module_XRegister_Q_reg_1_ ( .D(n1884), .CK(clk), .RN(n5320), .Q(add_subt_module_intDX[1]), .QN(n5147) );
DFFRX1TS add_subt_module_XRegister_Q_reg_16_ ( .D(n1873), .CK(clk), .RN(
n5342), .Q(add_subt_module_intDX[16]), .QN(n5146) );
DFFRX1TS add_subt_module_XRegister_Q_reg_6_ ( .D(n1863), .CK(clk), .RN(n5335), .Q(add_subt_module_intDX[6]), .QN(n5145) );
DFFRX1TS add_subt_module_XRegister_Q_reg_39_ ( .D(n1812), .CK(clk), .RN(
n5323), .Q(add_subt_module_intDX[39]), .QN(n5144) );
DFFRX1TS add_subt_module_XRegister_Q_reg_44_ ( .D(n1867), .CK(clk), .RN(
n5343), .Q(add_subt_module_intDX[44]), .QN(n5143) );
DFFRX2TS add_subt_module_YRegister_Q_reg_62_ ( .D(n1957), .CK(clk), .RN(
n5340), .Q(add_subt_module_intDY[62]), .QN(n5142) );
DFFRX2TS add_subt_module_YRegister_Q_reg_58_ ( .D(n1953), .CK(clk), .RN(
n5349), .Q(add_subt_module_intDY[58]), .QN(n5141) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_41_ ( .D(
n2576), .CK(clk), .RN(n5336), .Q(
add_subt_module_Sgf_normalized_result[41]), .QN(n5140) );
DFFRX2TS add_subt_module_YRegister_Q_reg_7_ ( .D(n1839), .CK(clk), .RN(n5321), .Q(add_subt_module_intDY[7]), .QN(n5138) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_38_ ( .D(
n2573), .CK(clk), .RN(n5336), .Q(
add_subt_module_Sgf_normalized_result[38]), .QN(n5137) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_40_ ( .D(
n2575), .CK(clk), .RN(n5336), .Q(
add_subt_module_Sgf_normalized_result[40]), .QN(n5135) );
DFFRX1TS add_subt_module_Sel_B_Q_reg_0_ ( .D(n2664), .CK(clk), .RN(n1959),
.Q(add_subt_module_FSM_selector_B[0]), .QN(n5134) );
DFFRX2TS add_subt_module_YRegister_Q_reg_5_ ( .D(n1859), .CK(clk), .RN(n5342), .Q(add_subt_module_intDY[5]), .QN(n5133) );
DFFRX2TS add_subt_module_YRegister_Q_reg_37_ ( .D(n1808), .CK(clk), .RN(
n5324), .Q(add_subt_module_intDY[37]), .QN(n5132) );
DFFRX2TS add_subt_module_XRegister_Q_reg_57_ ( .D(n1927), .CK(clk), .RN(
n5340), .Q(add_subt_module_intDX[57]), .QN(n5131) );
DFFRX2TS add_subt_module_XRegister_Q_reg_60_ ( .D(n1936), .CK(clk), .RN(
n5347), .Q(add_subt_module_intDX[60]), .QN(n5130) );
DFFRX2TS add_subt_module_YRegister_Q_reg_38_ ( .D(n1832), .CK(clk), .RN(
n5322), .Q(add_subt_module_intDY[38]), .QN(n5129) );
DFFRX2TS add_subt_module_YRegister_Q_reg_10_ ( .D(n1846), .CK(clk), .RN(
n5321), .Q(add_subt_module_intDY[10]), .QN(n5128) );
DFFRX2TS add_subt_module_YRegister_Q_reg_44_ ( .D(n1866), .CK(clk), .RN(
n5335), .Q(add_subt_module_intDY[44]), .QN(n5127) );
DFFRX2TS add_subt_module_XRegister_Q_reg_54_ ( .D(n1918), .CK(clk), .RN(
n5340), .Q(add_subt_module_intDX[54]), .QN(n5126) );
DFFRX2TS add_subt_module_XRegister_Q_reg_53_ ( .D(n1915), .CK(clk), .RN(
n5349), .Q(add_subt_module_intDX[53]), .QN(n5125) );
DFFRX2TS cordic_FSM_state_reg_reg_0_ ( .D(n2938), .CK(clk), .RN(n5348), .Q(
cordic_FSM_state_reg[0]), .QN(n5124) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_35_ ( .D(
n2570), .CK(clk), .RN(n5346), .Q(
add_subt_module_Sgf_normalized_result[35]), .QN(n5123) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_36_ ( .D(
n2571), .CK(clk), .RN(n5346), .Q(
add_subt_module_Sgf_normalized_result[36]), .QN(n5122) );
DFFRX2TS add_subt_module_FS_Module_state_reg_reg_0_ ( .D(n2929), .CK(clk),
.RN(n5314), .Q(add_subt_module_FS_Module_state_reg[0]), .QN(n5120) );
DFFRX2TS add_subt_module_YRegister_Q_reg_1_ ( .D(n1883), .CK(clk), .RN(n5320), .Q(add_subt_module_intDY[1]), .QN(n5119) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_32_ ( .D(
n2567), .CK(clk), .RN(n5346), .Q(
add_subt_module_Sgf_normalized_result[32]), .QN(n5117) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_33_ ( .D(
n2568), .CK(clk), .RN(n5346), .Q(
add_subt_module_Sgf_normalized_result[33]), .QN(n5116) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_34_ ( .D(
n2569), .CK(clk), .RN(n5346), .Q(
add_subt_module_Sgf_normalized_result[34]), .QN(n5115) );
DFFRX2TS add_subt_module_FS_Module_state_reg_reg_1_ ( .D(n2928), .CK(clk),
.RN(n5339), .Q(add_subt_module_FS_Module_state_reg[1]), .QN(n5114) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_29_ ( .D(
n2564), .CK(clk), .RN(n5324), .Q(
add_subt_module_Sgf_normalized_result[29]), .QN(n5113) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_30_ ( .D(
n2565), .CK(clk), .RN(n5337), .Q(
add_subt_module_Sgf_normalized_result[30]), .QN(n5112) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_31_ ( .D(
n2566), .CK(clk), .RN(n5346), .Q(
add_subt_module_Sgf_normalized_result[31]), .QN(n5111) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_25_ ( .D(
n2621), .CK(clk), .RN(n5328), .Q(add_subt_module_Add_Subt_result[25]),
.QN(n5110) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_26_ ( .D(
n2561), .CK(clk), .RN(n5333), .Q(
add_subt_module_Sgf_normalized_result[26]), .QN(n5109) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_28_ ( .D(
n2563), .CK(clk), .RN(n5316), .Q(
add_subt_module_Sgf_normalized_result[28]), .QN(n5108) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_27_ ( .D(
n2562), .CK(clk), .RN(n5325), .Q(
add_subt_module_Sgf_normalized_result[27]), .QN(n5107) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_24_ ( .D(
n2559), .CK(clk), .RN(n5351), .Q(
add_subt_module_Sgf_normalized_result[24]), .QN(n5105) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_25_ ( .D(
n2560), .CK(clk), .RN(n5347), .Q(
add_subt_module_Sgf_normalized_result[25]), .QN(n5104) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_21_ ( .D(
n2556), .CK(clk), .RN(n5334), .Q(
add_subt_module_Sgf_normalized_result[21]), .QN(n5103) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_22_ ( .D(
n2557), .CK(clk), .RN(n5334), .Q(
add_subt_module_Sgf_normalized_result[22]), .QN(n5102) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_33_ ( .D(
n2629), .CK(clk), .RN(n5329), .Q(add_subt_module_Add_Subt_result[33]),
.QN(n5101) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_17_ ( .D(
n2552), .CK(clk), .RN(n5315), .Q(
add_subt_module_Sgf_normalized_result[17]), .QN(n5100) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_18_ ( .D(
n2553), .CK(clk), .RN(n5316), .Q(
add_subt_module_Sgf_normalized_result[18]), .QN(n5099) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_19_ ( .D(
n2554), .CK(clk), .RN(n5351), .Q(
add_subt_module_Sgf_normalized_result[19]), .QN(n5098) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_20_ ( .D(
n2555), .CK(clk), .RN(n5317), .Q(
add_subt_module_Sgf_normalized_result[20]), .QN(n5097) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_15_ ( .D(
n2550), .CK(clk), .RN(n5315), .Q(
add_subt_module_Sgf_normalized_result[15]), .QN(n5096) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_16_ ( .D(
n2551), .CK(clk), .RN(n5316), .Q(
add_subt_module_Sgf_normalized_result[16]), .QN(n5095) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_11_ ( .D(
n2546), .CK(clk), .RN(n5332), .Q(
add_subt_module_Sgf_normalized_result[11]), .QN(n5094) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_12_ ( .D(
n2547), .CK(clk), .RN(n5332), .Q(
add_subt_module_Sgf_normalized_result[12]), .QN(n5093) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_13_ ( .D(
n2548), .CK(clk), .RN(n5316), .Q(
add_subt_module_Sgf_normalized_result[13]), .QN(n5092) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_9_ ( .D(
n2544), .CK(clk), .RN(n5332), .Q(
add_subt_module_Sgf_normalized_result[9]), .QN(n5090) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_10_ ( .D(
n2545), .CK(clk), .RN(n5332), .Q(
add_subt_module_Sgf_normalized_result[10]), .QN(n5089) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_6_ ( .D(
n2541), .CK(clk), .RN(n5331), .Q(
add_subt_module_Sgf_normalized_result[6]), .QN(n5088) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_7_ ( .D(
n2542), .CK(clk), .RN(n5332), .Q(
add_subt_module_Sgf_normalized_result[7]), .QN(n5087) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_8_ ( .D(
n2543), .CK(clk), .RN(n5332), .Q(
add_subt_module_Sgf_normalized_result[8]), .QN(n5086) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_3_ ( .D(
n2538), .CK(clk), .RN(n5331), .Q(
add_subt_module_Sgf_normalized_result[3]), .QN(n5085) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_4_ ( .D(
n2539), .CK(clk), .RN(n5331), .Q(
add_subt_module_Sgf_normalized_result[4]), .QN(n5084) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_5_ ( .D(
n2540), .CK(clk), .RN(n5331), .Q(
add_subt_module_Sgf_normalized_result[5]), .QN(n5083) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_47_ ( .D(
n2643), .CK(clk), .RN(n5332), .Q(add_subt_module_Add_Subt_result[47]),
.QN(n5082) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_25_ (
.D(n2386), .CK(clk), .RN(n5347), .Q(result_add_subt[25]), .QN(n5081)
);
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_63_ (
.D(n2933), .CK(clk), .RN(n5344), .Q(result_add_subt[63]), .QN(n5080)
);
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_12_ ( .D(
n2608), .CK(clk), .RN(n5338), .Q(add_subt_module_Add_Subt_result[12]),
.QN(n5078) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_11_ ( .D(
n2607), .CK(clk), .RN(n5330), .Q(add_subt_module_Add_Subt_result[11]),
.QN(n5077) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_37_ ( .D(
n2633), .CK(clk), .RN(n5347), .Q(add_subt_module_Add_Subt_result[37]),
.QN(n5076) );
DFFRX1TS add_subt_module_XRegister_Q_reg_24_ ( .D(n1745), .CK(clk), .RN(
n5327), .Q(add_subt_module_intDX[24]), .QN(n5075) );
DFFRX1TS add_subt_module_XRegister_Q_reg_38_ ( .D(n1833), .CK(clk), .RN(
n5322), .Q(add_subt_module_intDX[38]), .QN(n5074) );
DFFRX2TS add_subt_module_YRegister_Q_reg_59_ ( .D(n1954), .CK(clk), .RN(
n5345), .Q(add_subt_module_intDY[59]), .QN(n5073) );
DFFRX2TS add_subt_module_XRegister_Q_reg_19_ ( .D(n1804), .CK(clk), .RN(
n5324), .Q(add_subt_module_intDX[19]), .QN(n5072) );
DFFRX2TS add_subt_module_XRegister_Q_reg_27_ ( .D(n1778), .CK(clk), .RN(
n5315), .Q(add_subt_module_intDX[27]), .QN(n5071) );
DFFRX2TS add_subt_module_XRegister_Q_reg_50_ ( .D(n1894), .CK(clk), .RN(
n5319), .Q(add_subt_module_intDX[50]), .QN(n5070) );
DFFRX2TS add_subt_module_XRegister_Q_reg_31_ ( .D(n1774), .CK(clk), .RN(
n5323), .Q(add_subt_module_intDX[31]), .QN(n5069) );
DFFRX1TS add_subt_module_YRegister_Q_reg_53_ ( .D(n1948), .CK(clk), .RN(
n5349), .Q(add_subt_module_intDY[53]), .QN(n5068) );
DFFRX2TS add_subt_module_YRegister_Q_reg_57_ ( .D(n1952), .CK(clk), .RN(
n5347), .Q(add_subt_module_intDY[57]), .QN(n5067) );
DFFRX2TS add_subt_module_XRegister_Q_reg_22_ ( .D(n1742), .CK(clk), .RN(
n5327), .Q(add_subt_module_intDX[22]), .QN(n5066) );
DFFRX2TS add_subt_module_XRegister_Q_reg_34_ ( .D(n1801), .CK(clk), .RN(
n5324), .Q(add_subt_module_intDX[34]), .QN(n5065) );
DFFRX2TS add_subt_module_XRegister_Q_reg_42_ ( .D(n1823), .CK(clk), .RN(
n5323), .Q(add_subt_module_intDX[42]), .QN(n5064) );
DFFRX2TS add_subt_module_YRegister_Q_reg_6_ ( .D(n1862), .CK(clk), .RN(n5335), .Q(add_subt_module_intDY[6]), .QN(n5063) );
DFFRX2TS add_subt_module_XRegister_Q_reg_15_ ( .D(n1788), .CK(clk), .RN(
n5325), .Q(add_subt_module_intDX[15]), .QN(n5062) );
DFFRX1TS add_subt_module_XRegister_Q_reg_47_ ( .D(n1891), .CK(clk), .RN(
n5320), .Q(add_subt_module_intDX[47]), .QN(n5061) );
DFFRX2TS add_subt_module_YRegister_Q_reg_4_ ( .D(n1903), .CK(clk), .RN(n5319), .Q(add_subt_module_intDY[4]), .QN(n5060) );
DFFRX2TS add_subt_module_XRegister_Q_reg_58_ ( .D(n1930), .CK(clk), .RN(
n5349), .Q(add_subt_module_intDX[58]), .QN(n5059) );
DFFRX2TS add_subt_module_XRegister_Q_reg_55_ ( .D(n1921), .CK(clk), .RN(
n5314), .Q(add_subt_module_intDX[55]), .QN(n5058) );
DFFRX2TS cordic_FSM_state_reg_reg_1_ ( .D(cordic_FSM_state_next_1_), .CK(clk), .RN(n5340), .Q(cordic_FSM_state_reg[1]), .QN(n5057) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_30_ ( .D(
n2626), .CK(clk), .RN(n5328), .Q(add_subt_module_Add_Subt_result[30]),
.QN(n5055) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_17_ ( .D(
n2613), .CK(clk), .RN(n5341), .Q(add_subt_module_Add_Subt_result[17]),
.QN(n5053) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_10_ ( .D(
n2606), .CK(clk), .RN(n5325), .Q(add_subt_module_Add_Subt_result[10]),
.QN(n5052) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_14_ ( .D(
n2610), .CK(clk), .RN(n5325), .Q(add_subt_module_Add_Subt_result[14]),
.QN(n5051) );
DFFRX2TS add_subt_module_FS_Module_state_reg_reg_2_ ( .D(n2927), .CK(clk),
.RN(n5339), .Q(add_subt_module_FS_Module_state_reg[2]), .QN(n5050) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_43_ ( .D(
n2639), .CK(clk), .RN(n5333), .Q(add_subt_module_Add_Subt_result[43]),
.QN(n5048) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_42_ ( .D(
n2638), .CK(clk), .RN(n5316), .Q(add_subt_module_Add_Subt_result[42]),
.QN(n5047) );
DFFRX2TS cordic_FSM_state_reg_reg_3_ ( .D(n2940), .CK(clk), .RN(n5344), .Q(
cordic_FSM_state_reg[3]), .QN(n5045) );
DFFRX2TS add_subt_module_YRegister_Q_reg_3_ ( .D(n1886), .CK(clk), .RN(n5320), .Q(add_subt_module_intDY[3]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_35_ ( .D(n1791), .CK(clk), .RN(
n5325), .Q(add_subt_module_intDY[35]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_29_ ( .D(n1769), .CK(clk), .RN(
n5333), .Q(add_subt_module_intDY[29]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_33_ ( .D(n1755), .CK(clk), .RN(
n5326), .Q(add_subt_module_intDY[33]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_15_ ( .D(n1787), .CK(clk), .RN(
n5325), .Q(add_subt_module_intDY[15]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_31_ ( .D(n1773), .CK(clk), .RN(
n5316), .Q(add_subt_module_intDY[31]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_21_ ( .D(n1765), .CK(clk), .RN(
n5326), .Q(add_subt_module_intDY[21]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_23_ ( .D(n1797), .CK(clk), .RN(
n5324), .Q(add_subt_module_intDY[23]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_43_ ( .D(n1843), .CK(clk), .RN(
n5321), .Q(add_subt_module_intDY[43]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_41_ ( .D(n1815), .CK(clk), .RN(
n5323), .Q(add_subt_module_intDY[41]) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_45_ ( .D(
n2641), .CK(clk), .RN(n5351), .Q(add_subt_module_Add_Subt_result[45])
);
DFFRX2TS add_subt_module_YRegister_Q_reg_18_ ( .D(n1762), .CK(clk), .RN(
n5326), .Q(add_subt_module_intDY[18]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_25_ ( .D(n1759), .CK(clk), .RN(
n5326), .Q(add_subt_module_intDY[25]) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_29_ ( .D(
n2625), .CK(clk), .RN(n5328), .Q(add_subt_module_Add_Subt_result[29])
);
DFFRX2TS add_subt_module_YRegister_Q_reg_49_ ( .D(n1880), .CK(clk), .RN(
n5320), .Q(add_subt_module_intDY[49]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_11_ ( .D(n1825), .CK(clk), .RN(
n5322), .Q(add_subt_module_intDY[11]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_45_ ( .D(n1856), .CK(clk), .RN(
n5345), .Q(add_subt_module_intDY[45]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_26_ ( .D(n1734), .CK(clk), .RN(
n5328), .Q(add_subt_module_intDY[26]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_50_ ( .D(n1893), .CK(clk), .RN(
n5319), .Q(add_subt_module_intDY[50]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_36_ ( .D(n1784), .CK(clk), .RN(
n5325), .Q(add_subt_module_intDY[36]) );
DFFRX2TS add_subt_module_XRegister_Q_reg_61_ ( .D(n1939), .CK(clk), .RN(
n5314), .Q(add_subt_module_intDX[61]) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_overflow_Result_Q_reg_0_ (
.D(n2936), .CK(clk), .RN(n5331), .Q(add_subt_module_add_overflow_flag)
);
DFFRX2TS add_subt_module_YRegister_Q_reg_19_ ( .D(n1803), .CK(clk), .RN(
n5324), .Q(add_subt_module_intDY[19]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_27_ ( .D(n1777), .CK(clk), .RN(
n5319), .Q(add_subt_module_intDY[27]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_9_ ( .D(n1869), .CK(clk), .RN(n5345), .Q(add_subt_module_intDY[9]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_47_ ( .D(n1890), .CK(clk), .RN(
n5320), .Q(add_subt_module_intDY[47]) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_48_ ( .D(
n2644), .CK(clk), .RN(n5330), .Q(add_subt_module_Add_Subt_result[48])
);
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_8_ ( .D(
n2604), .CK(clk), .RN(n5314), .Q(add_subt_module_Add_Subt_result[8])
);
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_23_ ( .D(
n2619), .CK(clk), .RN(n5329), .Q(add_subt_module_Add_Subt_result[23])
);
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_24_ ( .D(
n2620), .CK(clk), .RN(n5329), .Q(add_subt_module_Add_Subt_result[24])
);
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_34_ ( .D(
n2630), .CK(clk), .RN(n5329), .Q(add_subt_module_Add_Subt_result[34])
);
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_38_ ( .D(
n2634), .CK(clk), .RN(n5319), .Q(add_subt_module_Add_Subt_result[38])
);
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_15_ ( .D(
n2611), .CK(clk), .RN(n5345), .Q(add_subt_module_Add_Subt_result[15])
);
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_5_ ( .D(
n2601), .CK(clk), .RN(n5330), .Q(add_subt_module_Add_Subt_result[5])
);
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_52_ ( .D(
n2648), .CK(clk), .RN(n5330), .Q(add_subt_module_Add_Subt_result[52])
);
DFFRX2TS reg_val_muxY_2stage_Q_reg_56_ ( .D(n2110), .CK(clk), .RN(n5363),
.Q(d_ff2_Y[56]) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_19_ ( .D(
n2615), .CK(clk), .RN(n5329), .Q(add_subt_module_Add_Subt_result[19])
);
DFFRX2TS reg_val_muxX_2stage_Q_reg_56_ ( .D(n2787), .CK(clk), .RN(n5363),
.Q(d_ff2_X[56]) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_53_ ( .D(
n2649), .CK(clk), .RN(n5330), .Q(add_subt_module_Add_Subt_result[53])
);
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_21_ ( .D(
n2617), .CK(clk), .RN(n5329), .Q(add_subt_module_Add_Subt_result[21])
);
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_31_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[31]),
.CK(clk), .RN(n5314), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[86]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_29_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[29]),
.CK(clk), .RN(n5326), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[84]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_34_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[34]),
.CK(clk), .RN(n5348), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[89]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_33_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[33]),
.CK(clk), .RN(n5350), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[88]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_24_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[24]),
.CK(clk), .RN(n5314), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[79]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_30_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[30]),
.CK(clk), .RN(n5341), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[85]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_28_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[28]),
.CK(clk), .RN(n5351), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[83]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_25_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[25]),
.CK(clk), .RN(n5350), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[80]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_35_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[35]),
.CK(clk), .RN(n5350), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[90]) );
DFFRX1TS add_subt_module_Exp_Operation_Module_exp_result_Q_reg_1_ ( .D(n2654), .CK(clk), .RN(n5338), .Q(add_subt_module_exp_oper_result[1]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_27_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[27]),
.CK(clk), .RN(n5350), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[82]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_57_ ( .D(n2788), .CK(clk), .RN(n5362),
.Q(d_ff2_X[57]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_59_ ( .D(n2790), .CK(clk), .RN(n5361),
.Q(d_ff2_X[59]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_61_ ( .D(n2792), .CK(clk), .RN(n5360),
.Q(d_ff2_X[61]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_59_ ( .D(n2107), .CK(clk), .RN(n5361),
.Q(d_ff2_Y[59]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_50_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[50]),
.CK(clk), .RN(n5316), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[105]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_53_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[53]),
.CK(clk), .RN(n5315), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[108]) );
DFFRX1TS cont_var_count_reg_1_ ( .D(n2925), .CK(clk), .RN(n5352), .Q(
cont_var_out[1]) );
DFFRX1TS add_subt_module_Exp_Operation_Module_exp_result_Q_reg_4_ ( .D(n2657), .CK(clk), .RN(n5343), .Q(add_subt_module_exp_oper_result[4]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_0_ ( .D(
n2535), .CK(clk), .RN(n5335), .Q(
add_subt_module_Sgf_normalized_result[0]) );
DFFRX1TS add_subt_module_Exp_Operation_Module_exp_result_Q_reg_5_ ( .D(n2658), .CK(clk), .RN(n5337), .Q(add_subt_module_exp_oper_result[5]) );
DFFRX1TS add_subt_module_Exp_Operation_Module_exp_result_Q_reg_0_ ( .D(n2653), .CK(clk), .RN(n5338), .Q(add_subt_module_exp_oper_result[0]) );
DFFRX1TS reg_operation_Q_reg_0_ ( .D(n2920), .CK(clk), .RN(n5352), .Q(
d_ff1_operation_out) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_7_ ( .D(n2277), .CK(clk), .RN(n5378), .Q(
d_ff2_Z[7]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_40_ ( .D(n2244), .CK(clk), .RN(n5378),
.Q(d_ff2_Z[40]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_40_ ( .D(n2138), .CK(clk), .RN(n5378),
.Q(d_ff2_Y[40]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_38_ ( .D(n2246), .CK(clk), .RN(n5378),
.Q(d_ff2_Z[38]) );
DFFRX1TS add_subt_module_Exp_Operation_Module_Overflow_Q_reg_0_ ( .D(n2651),
.CK(clk), .RN(n5348), .Q(overflow_flag) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_60_ (
.D(n2526), .CK(clk), .RN(n5333), .Q(result_add_subt[60]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_61_ (
.D(n2530), .CK(clk), .RN(n5347), .Q(result_add_subt[61]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_62_ (
.D(n2534), .CK(clk), .RN(n5314), .Q(result_add_subt[62]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_28_ (
.D(n2398), .CK(clk), .RN(n5334), .Q(result_add_subt[28]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_22_ (
.D(n2374), .CK(clk), .RN(n5317), .Q(result_add_subt[22]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_32_ (
.D(n2414), .CK(clk), .RN(n5341), .Q(result_add_subt[32]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_17_ (
.D(n2354), .CK(clk), .RN(n5327), .Q(result_add_subt[17]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_33_ (
.D(n2418), .CK(clk), .RN(n5350), .Q(result_add_subt[33]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_18_ (
.D(n2358), .CK(clk), .RN(n5326), .Q(result_add_subt[18]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_21_ (
.D(n2370), .CK(clk), .RN(n5350), .Q(result_add_subt[21]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_29_ (
.D(n2402), .CK(clk), .RN(n5327), .Q(result_add_subt[29]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_31_ (
.D(n2410), .CK(clk), .RN(n5344), .Q(result_add_subt[31]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_14_ (
.D(n2342), .CK(clk), .RN(n5326), .Q(result_add_subt[14]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_36_ (
.D(n2430), .CK(clk), .RN(n5348), .Q(result_add_subt[36]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_15_ (
.D(n2346), .CK(clk), .RN(n5327), .Q(result_add_subt[15]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_35_ (
.D(n2426), .CK(clk), .RN(n5340), .Q(result_add_subt[35]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_30_ (
.D(n2406), .CK(clk), .RN(n5320), .Q(result_add_subt[30]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_23_ (
.D(n2378), .CK(clk), .RN(n5350), .Q(result_add_subt[23]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_34_ (
.D(n2422), .CK(clk), .RN(n5318), .Q(result_add_subt[34]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_19_ (
.D(n2362), .CK(clk), .RN(n5318), .Q(result_add_subt[19]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_37_ (
.D(n2434), .CK(clk), .RN(n5318), .Q(result_add_subt[37]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_39_ (
.D(n2442), .CK(clk), .RN(n5318), .Q(result_add_subt[39]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_41_ (
.D(n2450), .CK(clk), .RN(n5318), .Q(result_add_subt[41]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_8_ (
.D(n2318), .CK(clk), .RN(n5318), .Q(result_add_subt[8]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_42_ (
.D(n2454), .CK(clk), .RN(n5318), .Q(result_add_subt[42]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_11_ (
.D(n2330), .CK(clk), .RN(n5317), .Q(result_add_subt[11]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_12_ (
.D(n2334), .CK(clk), .RN(n5351), .Q(result_add_subt[12]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_38_ (
.D(n2438), .CK(clk), .RN(n5334), .Q(result_add_subt[38]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_40_ (
.D(n2446), .CK(clk), .RN(n5317), .Q(result_add_subt[40]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_7_ (
.D(n2314), .CK(clk), .RN(n5351), .Q(result_add_subt[7]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_43_ (
.D(n2458), .CK(clk), .RN(n5334), .Q(result_add_subt[43]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_10_ (
.D(n2326), .CK(clk), .RN(n5317), .Q(result_add_subt[10]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_13_ (
.D(n2338), .CK(clk), .RN(n5322), .Q(result_add_subt[13]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_20_ (
.D(n2366), .CK(clk), .RN(n5321), .Q(result_add_subt[20]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_45_ (
.D(n2466), .CK(clk), .RN(n5334), .Q(result_add_subt[45]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_5_ (
.D(n2306), .CK(clk), .RN(n5324), .Q(result_add_subt[5]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_6_ (
.D(n2310), .CK(clk), .RN(n5329), .Q(result_add_subt[6]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_44_ (
.D(n2462), .CK(clk), .RN(n5323), .Q(result_add_subt[44]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_9_ (
.D(n2322), .CK(clk), .RN(n5340), .Q(result_add_subt[9]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_16_ (
.D(n2350), .CK(clk), .RN(n5336), .Q(result_add_subt[16]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_46_ (
.D(n2470), .CK(clk), .RN(n5349), .Q(result_add_subt[46]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_1_ (
.D(n2290), .CK(clk), .RN(n5343), .Q(result_add_subt[1]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_3_ (
.D(n2298), .CK(clk), .RN(n5343), .Q(result_add_subt[3]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_47_ (
.D(n2474), .CK(clk), .RN(n5332), .Q(result_add_subt[47]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_50_ (
.D(n2486), .CK(clk), .RN(n5316), .Q(result_add_subt[50]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_2_ (
.D(n2294), .CK(clk), .RN(n5315), .Q(result_add_subt[2]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_48_ (
.D(n2478), .CK(clk), .RN(n5316), .Q(result_add_subt[48]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_4_ (
.D(n2302), .CK(clk), .RN(n5315), .Q(result_add_subt[4]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_0_ (
.D(n2286), .CK(clk), .RN(n5333), .Q(result_add_subt[0]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_53_ ( .D(n2113), .CK(clk), .RN(n5365),
.Q(d_ff2_Y[53]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_54_ ( .D(n2785), .CK(clk), .RN(n5364),
.Q(d_ff2_X[54]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_55_ ( .D(n2786), .CK(clk), .RN(n5364),
.Q(d_ff2_X[55]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_54_ ( .D(n2112), .CK(clk), .RN(n5364),
.Q(d_ff2_Y[54]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_55_ ( .D(n2111), .CK(clk), .RN(n5364),
.Q(d_ff2_Y[55]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_23_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[23]),
.CK(clk), .RN(n5344), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[78]) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_3_ ( .D(
n2599), .CK(clk), .RN(n5330), .Q(add_subt_module_Add_Subt_result[3]),
.QN(n5046) );
DFFRX1TS add_subt_module_XRegister_Q_reg_63_ ( .D(n1945), .CK(clk), .RN(
n5337), .Q(add_subt_module_intDX[63]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_62_ ( .D(n2104), .CK(clk), .RN(n5359),
.Q(d_ff2_Y[62]) );
DFFRX1TS add_subt_module_Leading_Zero_Detector_Module_Output_Reg_Q_reg_4_ (
.D(n2590), .CK(clk), .RN(n5338), .Q(add_subt_module_LZA_output[4]) );
DFFRX1TS add_subt_module_Exp_Operation_Module_exp_result_Q_reg_6_ ( .D(n2659), .CK(clk), .RN(n5329), .Q(add_subt_module_exp_oper_result[6]) );
DFFRX1TS add_subt_module_Exp_Operation_Module_exp_result_Q_reg_7_ ( .D(n2660), .CK(clk), .RN(n5404), .Q(add_subt_module_exp_oper_result[7]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_28_ ( .D(n2162), .CK(clk), .RN(n5398),
.Q(d_ff2_Y[28]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_17_ ( .D(n2184), .CK(clk), .RN(n5395),
.Q(d_ff2_Y[17]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_35_ ( .D(n2148), .CK(clk), .RN(n5387),
.Q(d_ff2_Y[35]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_39_ ( .D(n2140), .CK(clk), .RN(n5383),
.Q(d_ff2_Y[39]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_8_ ( .D(n2202), .CK(clk), .RN(n5382), .Q(
d_ff2_Y[8]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_42_ ( .D(n2134), .CK(clk), .RN(n5381),
.Q(d_ff2_Y[42]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_11_ ( .D(n2196), .CK(clk), .RN(n5380),
.Q(d_ff2_Y[11]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_9_ ( .D(n2200), .CK(clk), .RN(n5374), .Q(
d_ff2_Y[9]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_16_ ( .D(n2186), .CK(clk), .RN(n5373),
.Q(d_ff2_Y[16]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_46_ ( .D(n2126), .CK(clk), .RN(n5372),
.Q(d_ff2_Y[46]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_1_ ( .D(n2216), .CK(clk), .RN(n5371), .Q(
d_ff2_Y[1]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_47_ ( .D(n2124), .CK(clk), .RN(n5369),
.Q(d_ff2_Y[47]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_50_ ( .D(n2118), .CK(clk), .RN(n5368),
.Q(d_ff2_Y[50]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_2_ ( .D(n2214), .CK(clk), .RN(n5368), .Q(
d_ff2_Y[2]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_48_ ( .D(n2122), .CK(clk), .RN(n5367),
.Q(d_ff2_Y[48]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_24_ ( .D(n2717), .CK(clk), .RN(n5397),
.Q(d_ff2_X[24]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_29_ ( .D(n2727), .CK(clk), .RN(n5392),
.Q(d_ff2_X[29]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_31_ ( .D(n2731), .CK(clk), .RN(n5391),
.Q(d_ff2_X[31]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_14_ ( .D(n2697), .CK(clk), .RN(n5390),
.Q(d_ff2_X[14]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_19_ ( .D(n2707), .CK(clk), .RN(n5385),
.Q(d_ff2_X[19]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_41_ ( .D(n2751), .CK(clk), .RN(n5382),
.Q(d_ff2_X[41]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_43_ ( .D(n2755), .CK(clk), .RN(n5377),
.Q(d_ff2_X[43]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_13_ ( .D(n2695), .CK(clk), .RN(n5376),
.Q(d_ff2_X[13]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_45_ ( .D(n2759), .CK(clk), .RN(n5379),
.Q(d_ff2_X[45]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_6_ ( .D(n2681), .CK(clk), .RN(n5374), .Q(
d_ff2_X[6]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_49_ ( .D(n2767), .CK(clk), .RN(n5371),
.Q(d_ff2_X[49]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_3_ ( .D(n2675), .CK(clk), .RN(n5370), .Q(
d_ff2_X[3]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_0_ ( .D(n2669), .CK(clk), .RN(n5358), .Q(
d_ff2_X[0]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_26_ ( .D(n2166), .CK(clk), .RN(n5399),
.Q(d_ff2_Y[26]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_22_ ( .D(n2713), .CK(clk), .RN(n5397),
.Q(d_ff2_X[22]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_32_ ( .D(n2154), .CK(clk), .RN(n5396),
.Q(d_ff2_Y[32]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_25_ ( .D(n2719), .CK(clk), .RN(n5394),
.Q(d_ff2_X[25]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_18_ ( .D(n2705), .CK(clk), .RN(n5394),
.Q(d_ff2_X[18]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_21_ ( .D(n2176), .CK(clk), .RN(n5393),
.Q(d_ff2_Y[21]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_36_ ( .D(n2146), .CK(clk), .RN(n5389),
.Q(d_ff2_Y[36]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_15_ ( .D(n2188), .CK(clk), .RN(n5388),
.Q(d_ff2_Y[15]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_30_ ( .D(n2729), .CK(clk), .RN(n5387),
.Q(d_ff2_X[30]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_23_ ( .D(n2715), .CK(clk), .RN(n5386),
.Q(d_ff2_X[23]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_23_ ( .D(n2172), .CK(clk), .RN(n5386),
.Q(d_ff2_Y[23]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_34_ ( .D(n2150), .CK(clk), .RN(n5385),
.Q(d_ff2_Y[34]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_37_ ( .D(n2743), .CK(clk), .RN(n5384),
.Q(d_ff2_X[37]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_37_ ( .D(n2144), .CK(clk), .RN(n5384),
.Q(d_ff2_Y[37]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_41_ ( .D(n2136), .CK(clk), .RN(n5382),
.Q(d_ff2_Y[41]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_12_ ( .D(n2693), .CK(clk), .RN(n5380),
.Q(d_ff2_X[12]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_12_ ( .D(n2194), .CK(clk), .RN(n5379),
.Q(d_ff2_Y[12]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_38_ ( .D(n2745), .CK(clk), .RN(n5379),
.Q(d_ff2_X[38]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_38_ ( .D(n2142), .CK(clk), .RN(n5379),
.Q(d_ff2_Y[38]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_40_ ( .D(n2749), .CK(clk), .RN(n5377),
.Q(d_ff2_X[40]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_43_ ( .D(n2132), .CK(clk), .RN(n5377),
.Q(d_ff2_Y[43]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_10_ ( .D(n2689), .CK(clk), .RN(n5377),
.Q(d_ff2_X[10]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_10_ ( .D(n2198), .CK(clk), .RN(n5377),
.Q(d_ff2_Y[10]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_13_ ( .D(n2192), .CK(clk), .RN(n5376),
.Q(d_ff2_Y[13]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_20_ ( .D(n2709), .CK(clk), .RN(n5374),
.Q(d_ff2_X[20]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_45_ ( .D(n2128), .CK(clk), .RN(n5375),
.Q(d_ff2_Y[45]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_5_ ( .D(n2679), .CK(clk), .RN(n5375), .Q(
d_ff2_X[5]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_5_ ( .D(n2208), .CK(clk), .RN(n5375), .Q(
d_ff2_Y[5]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_6_ ( .D(n2206), .CK(clk), .RN(n5376), .Q(
d_ff2_Y[6]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_44_ ( .D(n2757), .CK(clk), .RN(n5374),
.Q(d_ff2_X[44]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_44_ ( .D(n2130), .CK(clk), .RN(n5374),
.Q(d_ff2_Y[44]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_49_ ( .D(n2120), .CK(clk), .RN(n5371),
.Q(d_ff2_Y[49]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_3_ ( .D(n2212), .CK(clk), .RN(n5370), .Q(
d_ff2_Y[3]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_4_ ( .D(n2677), .CK(clk), .RN(n5352), .Q(
d_ff2_X[4]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_4_ ( .D(n2210), .CK(clk), .RN(n5391), .Q(
d_ff2_Y[4]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_51_ ( .D(n2771), .CK(clk), .RN(n5355),
.Q(d_ff2_X[51]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_51_ ( .D(n2116), .CK(clk), .RN(n5369),
.Q(d_ff2_Y[51]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_0_ ( .D(n2218), .CK(clk), .RN(n5366), .Q(
d_ff2_Y[0]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_55_ ( .D(n1919), .CK(clk), .RN(n5336), .Q(add_subt_module_DMP[55]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_26_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[26]),
.CK(clk), .RN(n5344), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[81]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_56_ ( .D(n1922), .CK(clk), .RN(n5337), .Q(add_subt_module_DMP[56]) );
DFFRX1TS reg_ch_mux_2_Q_reg_1_ ( .D(n2851), .CK(clk), .RN(n5357), .Q(
sel_mux_2_reg[1]), .QN(n5212) );
DFFRX1TS reg_LUT_Q_reg_48_ ( .D(n2843), .CK(clk), .RN(n5355), .Q(
d_ff3_LUT_out[48]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_57_ ( .D(n2109), .CK(clk), .RN(n5362),
.Q(d_ff2_Y[57]), .QN(n5244) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_37_ ( .D(n1807), .CK(clk), .RN(n5324), .Q(add_subt_module_DmP[37]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_39_ ( .D(n1810), .CK(clk), .RN(n5323), .Q(add_subt_module_DmP[39]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_8_ ( .D(n1817),
.CK(clk), .RN(n5323), .Q(add_subt_module_DmP[8]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_12_ ( .D(n1827), .CK(clk), .RN(n5322), .Q(add_subt_module_DmP[12]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_20_ ( .D(n1851), .CK(clk), .RN(n5345), .Q(add_subt_module_DmP[20]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_16_ ( .D(n1871), .CK(clk), .RN(n5335), .Q(add_subt_module_DmP[16]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_51_ ( .D(n1704), .CK(clk), .RN(n5337), .Q(add_subt_module_DMP[51]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_4_ ( .D(n1705),
.CK(clk), .RN(n5331), .Q(add_subt_module_DMP[4]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_2_ ( .D(n1706),
.CK(clk), .RN(n5331), .Q(add_subt_module_DMP[2]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_1_ ( .D(n1709),
.CK(clk), .RN(n5331), .Q(add_subt_module_DMP[1]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_6_ ( .D(n1712),
.CK(clk), .RN(n5332), .Q(add_subt_module_DMP[6]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_5_ ( .D(n1713),
.CK(clk), .RN(n5332), .Q(add_subt_module_DMP[5]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_7_ ( .D(n1717),
.CK(clk), .RN(n5332), .Q(add_subt_module_DMP[7]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_8_ ( .D(n1720),
.CK(clk), .RN(n5332), .Q(add_subt_module_DMP[8]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_34_ ( .D(n1722), .CK(clk), .RN(n5346), .Q(add_subt_module_DMP[34]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_32_ ( .D(n1746), .CK(clk), .RN(n5346), .Q(add_subt_module_DMP[32]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_42_ ( .D(n1820), .CK(clk), .RN(n5326), .Q(add_subt_module_DMP[42]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_38_ ( .D(n1830), .CK(clk), .RN(n5335), .Q(add_subt_module_DMP[38]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_40_ ( .D(n1834), .CK(clk), .RN(n5336), .Q(add_subt_module_DMP[40]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_44_ ( .D(n1864), .CK(clk), .RN(n5337), .Q(add_subt_module_DMP[44]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_46_ ( .D(n1874), .CK(clk), .RN(n5321), .Q(add_subt_module_DMP[46]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_48_ ( .D(n1898), .CK(clk), .RN(n5339), .Q(add_subt_module_DMP[48]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_14_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[14]),
.CK(clk), .RN(n5351), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[69]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_13_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[13]),
.CK(clk), .RN(n5351), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[68]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_12_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[12]),
.CK(clk), .RN(n5328), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[67]) );
DFFRX1TS d_ff5_Q_reg_63_ ( .D(n1963), .CK(clk), .RN(n5358), .Q(
data_output2_63_) );
DFFRX1TS reg_shift_y_Q_reg_57_ ( .D(n2098), .CK(clk), .RN(n5370), .Q(
d_ff3_sh_y_out[57]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_34_ ( .D(n1800), .CK(clk), .RN(
n5324), .Q(add_subt_module_intDY[34]) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_31_ ( .D(
n2627), .CK(clk), .RN(n5329), .Q(add_subt_module_Add_Subt_result[31])
);
DFFRX2TS add_subt_module_YRegister_Q_reg_46_ ( .D(n1876), .CK(clk), .RN(
n5342), .Q(add_subt_module_intDY[46]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_17_ ( .D(n1751), .CK(clk), .RN(
n5327), .Q(add_subt_module_intDY[17]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_20_ ( .D(n1852), .CK(clk), .RN(
n5343), .Q(add_subt_module_intDY[20]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_12_ ( .D(n1828), .CK(clk), .RN(
n5322), .Q(add_subt_module_intDY[12]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_28_ ( .D(n1738), .CK(clk), .RN(
n5328), .Q(add_subt_module_intDY[28]) );
DFFRX2TS add_subt_module_XRegister_Q_reg_52_ ( .D(n1912), .CK(clk), .RN(
n5349), .Q(add_subt_module_intDX[52]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_39_ ( .D(n1811), .CK(clk), .RN(
n5323), .Q(add_subt_module_intDY[39]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_8_ ( .D(n1818), .CK(clk), .RN(n5323), .Q(add_subt_module_intDY[8]) );
DFFRX2TS add_subt_module_XRegister_Q_reg_62_ ( .D(n1942), .CK(clk), .RN(
n5334), .Q(add_subt_module_intDX[62]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_42_ ( .D(n1822), .CK(clk), .RN(
n5323), .Q(add_subt_module_intDY[42]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_14_ ( .D(n1780), .CK(clk), .RN(
n5317), .Q(add_subt_module_intDY[14]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_40_ ( .D(n1836), .CK(clk), .RN(
n5322), .Q(add_subt_module_intDY[40]) );
DFFRX2TS add_subt_module_XRegister_Q_reg_56_ ( .D(n1924), .CK(clk), .RN(
n5347), .Q(add_subt_module_intDX[56]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_2_ ( .D(n1896), .CK(clk), .RN(n5319), .Q(add_subt_module_intDY[2]) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_7_ ( .D(
n2603), .CK(clk), .RN(n5349), .Q(add_subt_module_Add_Subt_result[7])
);
DFFRX2TS add_subt_module_XRegister_Q_reg_0_ ( .D(n1909), .CK(clk), .RN(n5348), .Q(add_subt_module_intDX[0]) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_44_ ( .D(
n2640), .CK(clk), .RN(n5314), .Q(add_subt_module_Add_Subt_result[44])
);
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_27_ ( .D(
n2623), .CK(clk), .RN(n5328), .Q(add_subt_module_Add_Subt_result[27])
);
DFFRX2TS add_subt_module_Sel_B_Q_reg_1_ ( .D(n2935), .CK(clk), .RN(n1959),
.Q(add_subt_module_FSM_selector_B[1]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_49_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[49]),
.CK(clk), .RN(n5316), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[104]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_51_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[51]),
.CK(clk), .RN(n5342), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[106]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_54_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[54]),
.CK(clk), .RN(n5348), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[109]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_38_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[38]),
.CK(clk), .RN(n5334), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[93]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_36_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[36]),
.CK(clk), .RN(n5320), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[91]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_32_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[32]),
.CK(clk), .RN(n5345), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[87]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_61_ ( .D(n2105), .CK(clk), .RN(n5360),
.Q(d_ff2_Y[61]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_52_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[52]),
.CK(clk), .RN(n5315), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[107]) );
DFFRX1TS add_subt_module_Exp_Operation_Module_exp_result_Q_reg_2_ ( .D(n2655), .CK(clk), .RN(n5343), .Q(add_subt_module_exp_oper_result[2]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_40_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[40]),
.CK(clk), .RN(n5334), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[95]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_1_ ( .D(
n2536), .CK(clk), .RN(n5404), .Q(
add_subt_module_Sgf_normalized_result[1]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_41_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[41]),
.CK(clk), .RN(n5318), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[96]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_45_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[45]),
.CK(clk), .RN(n5316), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[100]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_42_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[42]),
.CK(clk), .RN(n5317), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[97]) );
DFFRX1TS reg_region_flag_Q_reg_0_ ( .D(n2919), .CK(clk), .RN(n5352), .Q(
d_ff1_shift_region_flag_out[0]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_59_ (
.D(n2522), .CK(clk), .RN(n5333), .Q(result_add_subt[59]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_58_ (
.D(n2518), .CK(clk), .RN(n5333), .Q(result_add_subt[58]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_57_ (
.D(n2514), .CK(clk), .RN(n5333), .Q(result_add_subt[57]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_56_ (
.D(n2510), .CK(clk), .RN(n5333), .Q(result_add_subt[56]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_55_ (
.D(n2506), .CK(clk), .RN(n5333), .Q(result_add_subt[55]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_54_ (
.D(n2502), .CK(clk), .RN(n5333), .Q(result_add_subt[54]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_53_ (
.D(n2498), .CK(clk), .RN(n5333), .Q(result_add_subt[53]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_52_ (
.D(n2494), .CK(clk), .RN(n5333), .Q(result_add_subt[52]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_51_ (
.D(n2490), .CK(clk), .RN(n5333), .Q(result_add_subt[51]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_49_ (
.D(n2482), .CK(clk), .RN(n5345), .Q(result_add_subt[49]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_27_ (
.D(n2394), .CK(clk), .RN(n5320), .Q(result_add_subt[27]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_24_ (
.D(n2382), .CK(clk), .RN(n5347), .Q(result_add_subt[24]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_26_ (
.D(n2390), .CK(clk), .RN(n5314), .Q(result_add_subt[26]) );
DFFRX4TS cont_iter_count_reg_3_ ( .D(n2924), .CK(clk), .RN(n5352), .Q(
cont_iter_out[3]), .QN(n5056) );
DFFRX1TS add_subt_module_Leading_Zero_Detector_Module_Output_Reg_Q_reg_3_ (
.D(n2593), .CK(clk), .RN(n5337), .Q(add_subt_module_LZA_output[3]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_53_ ( .D(n2784), .CK(clk), .RN(n5365),
.Q(d_ff2_X[53]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_18_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[18]),
.CK(clk), .RN(n5318), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[73]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_22_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[22]),
.CK(clk), .RN(n5347), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[77]) );
DFFRX1TS reg_ch_mux_3_Q_reg_0_ ( .D(n2667), .CK(clk), .RN(n5357), .Q(
sel_mux_3_reg) );
DFFRX4TS cont_iter_count_reg_1_ ( .D(n2922), .CK(clk), .RN(n5352), .Q(
cont_iter_out[1]), .QN(n5049) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_62_ ( .D(n2793), .CK(clk), .RN(n5359),
.Q(d_ff2_X[62]) );
DFFRX1TS reg_region_flag_Q_reg_1_ ( .D(n2918), .CK(clk), .RN(n5352), .Q(
d_ff1_shift_region_flag_out[1]), .QN(n5241) );
DFFRX1TS d_ff4_Xn_Q_reg_62_ ( .D(n2531), .CK(clk), .RN(n5359), .Q(
d_ff_Xn[62]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_26_ ( .D(n1733), .CK(clk), .RN(n5328), .Q(add_subt_module_DmP[26]) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_36_ ( .D(
n2632), .CK(clk), .RN(n5329), .Q(add_subt_module_Add_Subt_result[36]),
.QN(n5216) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_19_ ( .D(n1802), .CK(clk), .RN(n5324), .Q(add_subt_module_DmP[19]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_34_ ( .D(n1799), .CK(clk), .RN(n5324), .Q(add_subt_module_DmP[34]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_23_ ( .D(n1796), .CK(clk), .RN(n5324), .Q(add_subt_module_DmP[23]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_31_ ( .D(n1772), .CK(clk), .RN(n5317), .Q(add_subt_module_DmP[31]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_29_ ( .D(n1768), .CK(clk), .RN(n5323), .Q(add_subt_module_DmP[29]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_38_ ( .D(n1831), .CK(clk), .RN(n5322), .Q(add_subt_module_DmP[38]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_11_ ( .D(n1824), .CK(clk), .RN(n5322), .Q(add_subt_module_DmP[11]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_31_ ( .D(n2253), .CK(clk), .RN(n5391),
.Q(d_ff2_Z[31]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_29_ ( .D(n2255), .CK(clk), .RN(n5392),
.Q(d_ff2_Z[29]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_15_ ( .D(n2269), .CK(clk), .RN(n5388),
.Q(d_ff2_Z[15]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_36_ ( .D(n2248), .CK(clk), .RN(n5389),
.Q(d_ff2_Z[36]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_34_ ( .D(n2250), .CK(clk), .RN(n5385),
.Q(d_ff2_Z[34]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_23_ ( .D(n2261), .CK(clk), .RN(n5386),
.Q(d_ff2_Z[23]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_37_ ( .D(n2247), .CK(clk), .RN(n5384),
.Q(d_ff2_Z[37]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_19_ ( .D(n2265), .CK(clk), .RN(n5385),
.Q(d_ff2_Z[19]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_12_ ( .D(n2272), .CK(clk), .RN(n5379),
.Q(d_ff2_Z[12]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_41_ ( .D(n2243), .CK(clk), .RN(n5382),
.Q(d_ff2_Z[41]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_5_ ( .D(n2279), .CK(clk), .RN(n5375), .Q(
d_ff2_Z[5]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_45_ ( .D(n2239), .CK(clk), .RN(n5375),
.Q(d_ff2_Z[45]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_0_ ( .D(n2284), .CK(clk), .RN(n5366), .Q(
d_ff2_Z[0]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_51_ ( .D(n2233), .CK(clk), .RN(n5366),
.Q(d_ff2_Z[51]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_55_ ( .D(n2229), .CK(clk), .RN(n5363),
.Q(d_ff2_Z[55]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_57_ ( .D(n2227), .CK(clk), .RN(n5362),
.Q(d_ff2_Z[57]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_56_ ( .D(n2228), .CK(clk), .RN(n5363),
.Q(d_ff2_Z[56]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_0_ ( .D(n1908),
.CK(clk), .RN(n5349), .Q(add_subt_module_DmP[0]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_42_ ( .D(
n2577), .CK(clk), .RN(n5336), .Q(
add_subt_module_Sgf_normalized_result[42]), .QN(n5139) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_63_ ( .D(n2092), .CK(clk), .RN(n5358),
.Q(d_ff2_Y[63]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_18_ ( .D(n2182), .CK(clk), .RN(n5394),
.Q(d_ff2_Y[18]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_22_ ( .D(n2174), .CK(clk), .RN(n5397),
.Q(d_ff2_Y[22]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_54_ ( .D(
n2937), .CK(clk), .RN(n5321), .Q(
add_subt_module_Sgf_normalized_result[54]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_14_ ( .D(n2190), .CK(clk), .RN(n5390),
.Q(d_ff2_Y[14]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_27_ ( .D(n2164), .CK(clk), .RN(n5390),
.Q(d_ff2_Y[27]) );
DFFRX4TS cont_iter_count_reg_2_ ( .D(n2921), .CK(clk), .RN(n5352), .Q(
cont_iter_out[2]), .QN(n5118) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_42_ ( .D(n1821), .CK(clk), .RN(n5323), .Q(add_subt_module_DmP[42]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_49_ ( .D(n2235), .CK(clk), .RN(n5371),
.Q(d_ff2_Z[49]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_53_ ( .D(n2231), .CK(clk), .RN(n5365),
.Q(d_ff2_Z[53]) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_0_ ( .D(
n2596), .CK(clk), .RN(n5330), .Q(add_subt_module_Add_Subt_result[0]),
.QN(n5232) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_32_ ( .D(n1747), .CK(clk), .RN(n5327), .Q(add_subt_module_DmP[32]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_16_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[16]),
.CK(clk), .RN(n5350), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[71]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_21_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[21]),
.CK(clk), .RN(n5314), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[76]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_17_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[17]),
.CK(clk), .RN(n5341), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[72]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_19_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[19]),
.CK(clk), .RN(n5348), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[74]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_20_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[20]),
.CK(clk), .RN(n5340), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[75]) );
DFFRX1TS add_subt_module_Leading_Zero_Detector_Module_Output_Reg_Q_reg_2_ (
.D(n2594), .CK(clk), .RN(n5339), .Q(add_subt_module_LZA_output[2]) );
DFFRX1TS d_ff4_Xn_Q_reg_56_ ( .D(n2507), .CK(clk), .RN(n5363), .Q(
d_ff_Xn[56]) );
DFFRX1TS d_ff4_Xn_Q_reg_57_ ( .D(n2511), .CK(clk), .RN(n5362), .Q(
d_ff_Xn[57]) );
DFFRX1TS d_ff4_Xn_Q_reg_59_ ( .D(n2519), .CK(clk), .RN(n5361), .Q(
d_ff_Xn[59]) );
DFFRX1TS d_ff4_Xn_Q_reg_26_ ( .D(n2387), .CK(clk), .RN(n5399), .Q(
d_ff_Xn[26]) );
DFFRX1TS d_ff4_Xn_Q_reg_28_ ( .D(n2395), .CK(clk), .RN(n5398), .Q(
d_ff_Xn[28]) );
DFFRX1TS d_ff4_Xn_Q_reg_24_ ( .D(n2379), .CK(clk), .RN(n5397), .Q(
d_ff_Xn[24]) );
DFFRX1TS d_ff4_Xn_Q_reg_32_ ( .D(n2411), .CK(clk), .RN(n5396), .Q(
d_ff_Xn[32]) );
DFFRX1TS d_ff4_Xn_Q_reg_29_ ( .D(n2399), .CK(clk), .RN(n5392), .Q(
d_ff_Xn[29]) );
DFFRX1TS d_ff4_Xn_Q_reg_31_ ( .D(n2407), .CK(clk), .RN(n5391), .Q(
d_ff_Xn[31]) );
DFFRX1TS d_ff4_Xn_Q_reg_14_ ( .D(n2339), .CK(clk), .RN(n5390), .Q(
d_ff_Xn[14]) );
DFFRX1TS d_ff4_Xn_Q_reg_36_ ( .D(n2427), .CK(clk), .RN(n5389), .Q(
d_ff_Xn[36]) );
DFFRX1TS d_ff4_Xn_Q_reg_35_ ( .D(n2423), .CK(clk), .RN(n5388), .Q(
d_ff_Xn[35]) );
DFFRX1TS d_ff4_Xn_Q_reg_34_ ( .D(n2419), .CK(clk), .RN(n5386), .Q(
d_ff_Xn[34]) );
DFFRX1TS d_ff4_Xn_Q_reg_19_ ( .D(n2359), .CK(clk), .RN(n5385), .Q(
d_ff_Xn[19]) );
DFFRX1TS d_ff4_Xn_Q_reg_39_ ( .D(n2439), .CK(clk), .RN(n5383), .Q(
d_ff_Xn[39]) );
DFFRX1TS d_ff4_Xn_Q_reg_41_ ( .D(n2447), .CK(clk), .RN(n5382), .Q(
d_ff_Xn[41]) );
DFFRX1TS d_ff4_Xn_Q_reg_8_ ( .D(n2315), .CK(clk), .RN(n5382), .Q(d_ff_Xn[8])
);
DFFRX1TS d_ff4_Xn_Q_reg_42_ ( .D(n2451), .CK(clk), .RN(n5381), .Q(
d_ff_Xn[42]) );
DFFRX1TS d_ff4_Xn_Q_reg_11_ ( .D(n2327), .CK(clk), .RN(n5380), .Q(
d_ff_Xn[11]) );
DFFRX1TS d_ff4_Xn_Q_reg_7_ ( .D(n2311), .CK(clk), .RN(n5378), .Q(d_ff_Xn[7])
);
DFFRX1TS d_ff4_Xn_Q_reg_43_ ( .D(n2455), .CK(clk), .RN(n5377), .Q(
d_ff_Xn[43]) );
DFFRX1TS d_ff4_Xn_Q_reg_13_ ( .D(n2335), .CK(clk), .RN(n5376), .Q(
d_ff_Xn[13]) );
DFFRX1TS d_ff4_Xn_Q_reg_45_ ( .D(n2463), .CK(clk), .RN(n5400), .Q(
d_ff_Xn[45]) );
DFFRX1TS d_ff4_Xn_Q_reg_6_ ( .D(n2307), .CK(clk), .RN(n5359), .Q(d_ff_Xn[6])
);
DFFRX1TS d_ff4_Xn_Q_reg_9_ ( .D(n2319), .CK(clk), .RN(n5374), .Q(d_ff_Xn[9])
);
DFFRX1TS d_ff4_Xn_Q_reg_46_ ( .D(n2467), .CK(clk), .RN(n5372), .Q(
d_ff_Xn[46]) );
DFFRX1TS d_ff4_Xn_Q_reg_49_ ( .D(n2479), .CK(clk), .RN(n5371), .Q(
d_ff_Xn[49]) );
DFFRX1TS d_ff4_Xn_Q_reg_3_ ( .D(n2295), .CK(clk), .RN(n5370), .Q(d_ff_Xn[3])
);
DFFRX1TS d_ff4_Xn_Q_reg_48_ ( .D(n2475), .CK(clk), .RN(n5367), .Q(
d_ff_Xn[48]) );
DFFRX1TS d_ff4_Xn_Q_reg_53_ ( .D(n2495), .CK(clk), .RN(n5365), .Q(
d_ff_Xn[53]) );
DFFRX1TS d_ff4_Xn_Q_reg_54_ ( .D(n2499), .CK(clk), .RN(n5364), .Q(
d_ff_Xn[54]) );
DFFRX1TS d_ff4_Xn_Q_reg_55_ ( .D(n2503), .CK(clk), .RN(n5364), .Q(
d_ff_Xn[55]) );
DFFRX1TS d_ff4_Xn_Q_reg_0_ ( .D(n2090), .CK(clk), .RN(n5357), .Q(d_ff_Xn[0])
);
DFFRX1TS d_ff4_Xn_Q_reg_61_ ( .D(n2527), .CK(clk), .RN(n5360), .Q(
d_ff_Xn[61]) );
DFFRX1TS add_subt_module_Leading_Zero_Detector_Module_Output_Reg_Q_reg_1_ (
.D(n2591), .CK(clk), .RN(n5404), .Q(add_subt_module_LZA_output[1]) );
DFFRX1TS d_ff4_Xn_Q_reg_22_ ( .D(n2371), .CK(clk), .RN(n5397), .Q(
d_ff_Xn[22]) );
DFFRX1TS d_ff4_Xn_Q_reg_17_ ( .D(n2351), .CK(clk), .RN(n5395), .Q(
d_ff_Xn[17]) );
DFFRX1TS d_ff4_Xn_Q_reg_33_ ( .D(n2415), .CK(clk), .RN(n5398), .Q(
d_ff_Xn[33]) );
DFFRX1TS d_ff4_Xn_Q_reg_18_ ( .D(n2355), .CK(clk), .RN(n5394), .Q(
d_ff_Xn[18]) );
DFFRX1TS d_ff4_Xn_Q_reg_21_ ( .D(n2367), .CK(clk), .RN(n5393), .Q(
d_ff_Xn[21]) );
DFFRX1TS d_ff4_Xn_Q_reg_27_ ( .D(n2391), .CK(clk), .RN(n5391), .Q(
d_ff_Xn[27]) );
DFFRX1TS d_ff4_Xn_Q_reg_15_ ( .D(n2343), .CK(clk), .RN(n5388), .Q(
d_ff_Xn[15]) );
DFFRX1TS d_ff4_Xn_Q_reg_30_ ( .D(n2403), .CK(clk), .RN(n5387), .Q(
d_ff_Xn[30]) );
DFFRX1TS d_ff4_Xn_Q_reg_23_ ( .D(n2375), .CK(clk), .RN(n5386), .Q(
d_ff_Xn[23]) );
DFFRX1TS d_ff4_Xn_Q_reg_37_ ( .D(n2431), .CK(clk), .RN(n5384), .Q(
d_ff_Xn[37]) );
DFFRX1TS d_ff4_Xn_Q_reg_12_ ( .D(n2331), .CK(clk), .RN(n5380), .Q(
d_ff_Xn[12]) );
DFFRX1TS d_ff4_Xn_Q_reg_38_ ( .D(n2435), .CK(clk), .RN(n5379), .Q(
d_ff_Xn[38]) );
DFFRX1TS d_ff4_Xn_Q_reg_40_ ( .D(n2443), .CK(clk), .RN(n5378), .Q(
d_ff_Xn[40]) );
DFFRX1TS d_ff4_Xn_Q_reg_10_ ( .D(n2323), .CK(clk), .RN(n5377), .Q(
d_ff_Xn[10]) );
DFFRX1TS d_ff4_Xn_Q_reg_20_ ( .D(n2363), .CK(clk), .RN(n5399), .Q(
d_ff_Xn[20]) );
DFFRX1TS d_ff4_Xn_Q_reg_5_ ( .D(n2303), .CK(clk), .RN(n5375), .Q(d_ff_Xn[5])
);
DFFRX1TS d_ff4_Xn_Q_reg_44_ ( .D(n2459), .CK(clk), .RN(n5374), .Q(
d_ff_Xn[44]) );
DFFRX1TS d_ff4_Xn_Q_reg_16_ ( .D(n2347), .CK(clk), .RN(n5373), .Q(
d_ff_Xn[16]) );
DFFRX1TS d_ff4_Xn_Q_reg_1_ ( .D(n2287), .CK(clk), .RN(n5371), .Q(d_ff_Xn[1])
);
DFFRX1TS d_ff4_Xn_Q_reg_47_ ( .D(n2471), .CK(clk), .RN(n5369), .Q(
d_ff_Xn[47]) );
DFFRX1TS d_ff4_Xn_Q_reg_50_ ( .D(n2483), .CK(clk), .RN(n5369), .Q(
d_ff_Xn[50]) );
DFFRX1TS d_ff4_Xn_Q_reg_2_ ( .D(n2291), .CK(clk), .RN(n5368), .Q(d_ff_Xn[2])
);
DFFRX1TS d_ff4_Xn_Q_reg_4_ ( .D(n2299), .CK(clk), .RN(n5363), .Q(d_ff_Xn[4])
);
DFFRX1TS d_ff4_Xn_Q_reg_51_ ( .D(n2487), .CK(clk), .RN(n5367), .Q(
d_ff_Xn[51]) );
DFFRX1TS d_ff4_Xn_Q_reg_25_ ( .D(n2383), .CK(clk), .RN(n5394), .Q(
d_ff_Xn[25]) );
DFFRX1TS d_ff4_Xn_Q_reg_63_ ( .D(n2932), .CK(clk), .RN(n5358), .Q(
d_ff_Xn[63]) );
DFFRX1TS add_subt_module_Exp_Operation_Module_exp_result_Q_reg_9_ ( .D(n2662), .CK(clk), .RN(n5339), .Q(add_subt_module_exp_oper_result[9]) );
DFFRX1TS add_subt_module_Exp_Operation_Module_exp_result_Q_reg_8_ ( .D(n2661), .CK(clk), .RN(n5404), .Q(add_subt_module_exp_oper_result[8]) );
DFFRX1TS add_subt_module_Exp_Operation_Module_exp_result_Q_reg_10_ ( .D(
n2652), .CK(clk), .RN(n5339), .Q(add_subt_module_exp_oper_result[10])
);
DFFRX1TS reg_val_muxY_2stage_Q_reg_24_ ( .D(n2170), .CK(clk), .RN(n5396),
.Q(d_ff2_Y[24]) );
DFFRX1TS d_ff4_Xn_Q_reg_58_ ( .D(n2515), .CK(clk), .RN(n5362), .Q(
d_ff_Xn[58]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_7_ ( .D(n2683), .CK(clk), .RN(n5378), .Q(
d_ff2_X[7]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_34_ ( .D(n2737), .CK(clk), .RN(n5386),
.Q(d_ff2_X[34]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_36_ ( .D(n2741), .CK(clk), .RN(n5389),
.Q(d_ff2_X[36]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_32_ ( .D(n2733), .CK(clk), .RN(n5396),
.Q(d_ff2_X[32]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_26_ ( .D(n2721), .CK(clk), .RN(n5399),
.Q(d_ff2_X[26]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_48_ ( .D(n2765), .CK(clk), .RN(n5367),
.Q(d_ff2_X[48]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_46_ ( .D(n2761), .CK(clk), .RN(n5372),
.Q(d_ff2_X[46]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_9_ ( .D(n2687), .CK(clk), .RN(n5374), .Q(
d_ff2_X[9]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_11_ ( .D(n2691), .CK(clk), .RN(n5380),
.Q(d_ff2_X[11]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_42_ ( .D(n2753), .CK(clk), .RN(n5381),
.Q(d_ff2_X[42]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_8_ ( .D(n2685), .CK(clk), .RN(n5382), .Q(
d_ff2_X[8]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_39_ ( .D(n2747), .CK(clk), .RN(n5383),
.Q(d_ff2_X[39]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_35_ ( .D(n2739), .CK(clk), .RN(n5388),
.Q(d_ff2_X[35]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_28_ ( .D(n2725), .CK(clk), .RN(n5398),
.Q(d_ff2_X[28]) );
DFFRX1TS d_ff4_Xn_Q_reg_60_ ( .D(n2523), .CK(clk), .RN(n5360), .Q(
d_ff_Xn[60]) );
DFFRX1TS d_ff4_Xn_Q_reg_52_ ( .D(n2491), .CK(clk), .RN(n5366), .Q(
d_ff_Xn[52]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_2_ ( .D(n2673), .CK(clk), .RN(n5368), .Q(
d_ff2_X[2]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_50_ ( .D(n2769), .CK(clk), .RN(n5369),
.Q(d_ff2_X[50]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_47_ ( .D(n2763), .CK(clk), .RN(n5369),
.Q(d_ff2_X[47]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_1_ ( .D(n2671), .CK(clk), .RN(n5371), .Q(
d_ff2_X[1]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_16_ ( .D(n2701), .CK(clk), .RN(n5373),
.Q(d_ff2_X[16]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_20_ ( .D(n2178), .CK(clk), .RN(n5384),
.Q(d_ff2_Y[20]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_7_ ( .D(n2204), .CK(clk), .RN(n5378), .Q(
d_ff2_Y[7]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_19_ ( .D(n2180), .CK(clk), .RN(n5385),
.Q(d_ff2_Y[19]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_30_ ( .D(n2158), .CK(clk), .RN(n5387),
.Q(d_ff2_Y[30]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_15_ ( .D(n2699), .CK(clk), .RN(n5388),
.Q(d_ff2_X[15]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_27_ ( .D(n2723), .CK(clk), .RN(n5391),
.Q(d_ff2_X[27]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_31_ ( .D(n2156), .CK(clk), .RN(n5391),
.Q(d_ff2_Y[31]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_29_ ( .D(n2160), .CK(clk), .RN(n5392),
.Q(d_ff2_Y[29]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_21_ ( .D(n2711), .CK(clk), .RN(n5393),
.Q(d_ff2_X[21]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_25_ ( .D(n2168), .CK(clk), .RN(n5394),
.Q(d_ff2_Y[25]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_33_ ( .D(n2152), .CK(clk), .RN(n5400),
.Q(d_ff2_Y[33]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_33_ ( .D(n2735), .CK(clk), .RN(n5397),
.Q(d_ff2_X[33]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_17_ ( .D(n2703), .CK(clk), .RN(n5395),
.Q(d_ff2_X[17]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_63_ ( .D(n2931), .CK(clk), .RN(n5358),
.Q(d_ff2_X[63]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_20_ ( .D(n2264), .CK(clk), .RN(n5396),
.Q(d_ff2_Z[20]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_13_ ( .D(n2271), .CK(clk), .RN(n5376),
.Q(d_ff2_Z[13]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_43_ ( .D(n2241), .CK(clk), .RN(n5377),
.Q(d_ff2_Z[43]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_30_ ( .D(n2254), .CK(clk), .RN(n5387),
.Q(d_ff2_Z[30]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_14_ ( .D(n2270), .CK(clk), .RN(n5390),
.Q(d_ff2_Z[14]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_27_ ( .D(n2257), .CK(clk), .RN(n5390),
.Q(d_ff2_Z[27]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_21_ ( .D(n2263), .CK(clk), .RN(n5393),
.Q(d_ff2_Z[21]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_25_ ( .D(n2259), .CK(clk), .RN(n5394),
.Q(d_ff2_Z[25]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_32_ ( .D(n2252), .CK(clk), .RN(n5395),
.Q(d_ff2_Z[32]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_22_ ( .D(n2262), .CK(clk), .RN(n5397),
.Q(d_ff2_Z[22]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_26_ ( .D(n2258), .CK(clk), .RN(n5398),
.Q(d_ff2_Z[26]) );
DFFRX2TS add_subt_module_Exp_Operation_Module_exp_result_Q_reg_3_ ( .D(n2656), .CK(clk), .RN(n5343), .Q(add_subt_module_exp_oper_result[3]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_13_ ( .D(n1848), .CK(clk), .RN(n5321), .Q(add_subt_module_DmP[13]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_43_ ( .D(n1842), .CK(clk), .RN(n5321), .Q(add_subt_module_DmP[43]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_17_ ( .D(n2267), .CK(clk), .RN(n5395),
.Q(d_ff2_Z[17]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_8_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[8]),
.CK(clk), .RN(n5328), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[63]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_2_ ( .D(n1895),
.CK(clk), .RN(n5319), .Q(add_subt_module_DmP[2]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_3_ ( .D(n1885),
.CK(clk), .RN(n5320), .Q(add_subt_module_DmP[3]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_45_ ( .D(n1855), .CK(clk), .RN(n5336), .Q(add_subt_module_DmP[45]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_7_ ( .D(n1838),
.CK(clk), .RN(n5321), .Q(add_subt_module_DmP[7]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_14_ ( .D(n1779), .CK(clk), .RN(n5322), .Q(add_subt_module_DmP[14]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_33_ ( .D(n1754), .CK(clk), .RN(n5326), .Q(add_subt_module_DmP[33]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_11_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[11]),
.CK(clk), .RN(n5342), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[66]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_15_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[15]),
.CK(clk), .RN(n5324), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[70]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_51_ ( .D(n1905), .CK(clk), .RN(n5335), .Q(add_subt_module_DmP[51]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_4_ ( .D(n1902),
.CK(clk), .RN(n5319), .Q(add_subt_module_DmP[4]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_48_ ( .D(n1899), .CK(clk), .RN(n5319), .Q(add_subt_module_DmP[48]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_47_ ( .D(n1889), .CK(clk), .RN(n5320), .Q(add_subt_module_DmP[47]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_1_ ( .D(n1882),
.CK(clk), .RN(n5320), .Q(add_subt_module_DmP[1]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_44_ ( .D(n1865), .CK(clk), .RN(n5343), .Q(add_subt_module_DmP[44]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_6_ ( .D(n1861),
.CK(clk), .RN(n5342), .Q(add_subt_module_DmP[6]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_40_ ( .D(n1835), .CK(clk), .RN(n5322), .Q(add_subt_module_DmP[40]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_35_ ( .D(n1790), .CK(clk), .RN(n5325), .Q(add_subt_module_DmP[35]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_36_ ( .D(n1783), .CK(clk), .RN(n5325), .Q(add_subt_module_DmP[36]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_27_ ( .D(n1776), .CK(clk), .RN(n5325), .Q(add_subt_module_DmP[27]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_18_ ( .D(n1761), .CK(clk), .RN(n5326), .Q(add_subt_module_DmP[18]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_25_ ( .D(n1758), .CK(clk), .RN(n5326), .Q(add_subt_module_DmP[25]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_22_ ( .D(n1740), .CK(clk), .RN(n5327), .Q(add_subt_module_DmP[22]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_28_ ( .D(n1737), .CK(clk), .RN(n5328), .Q(add_subt_module_DmP[28]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_47_ ( .D(n1888), .CK(clk), .RN(n5337), .Q(add_subt_module_DMP[47]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_49_ ( .D(n1878), .CK(clk), .RN(n5344), .Q(add_subt_module_DMP[49]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_45_ ( .D(n1854), .CK(clk), .RN(n5337), .Q(add_subt_module_DMP[45]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_43_ ( .D(n1841), .CK(clk), .RN(n5330), .Q(add_subt_module_DMP[43]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_41_ ( .D(n1813), .CK(clk), .RN(n5337), .Q(add_subt_module_DMP[41]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_36_ ( .D(n1782), .CK(clk), .RN(n5335), .Q(add_subt_module_DMP[36]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_28_ ( .D(n1736), .CK(clk), .RN(n5335), .Q(add_subt_module_DMP[28]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_26_ ( .D(n1732), .CK(clk), .RN(n5337), .Q(add_subt_module_DMP[26]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_22_ ( .D(n1731), .CK(clk), .RN(n5334), .Q(add_subt_module_DMP[22]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_17_ ( .D(n1729), .CK(clk), .RN(n5317), .Q(add_subt_module_DMP[17]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_18_ ( .D(n1728), .CK(clk), .RN(n5351), .Q(add_subt_module_DMP[18]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_21_ ( .D(n1727), .CK(clk), .RN(n5351), .Q(add_subt_module_DMP[21]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_14_ ( .D(n1726), .CK(clk), .RN(n5316), .Q(add_subt_module_DMP[14]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_15_ ( .D(n1725), .CK(clk), .RN(n5315), .Q(add_subt_module_DMP[15]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_30_ ( .D(n1724), .CK(clk), .RN(n5346), .Q(add_subt_module_DMP[30]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_23_ ( .D(n1723), .CK(clk), .RN(n5319), .Q(add_subt_module_DMP[23]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_19_ ( .D(n1721), .CK(clk), .RN(n5334), .Q(add_subt_module_DMP[19]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_11_ ( .D(n1719), .CK(clk), .RN(n5315), .Q(add_subt_module_DMP[11]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_12_ ( .D(n1718), .CK(clk), .RN(n5316), .Q(add_subt_module_DMP[12]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_13_ ( .D(n1715), .CK(clk), .RN(n5315), .Q(add_subt_module_DMP[13]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_20_ ( .D(n1714), .CK(clk), .RN(n5317), .Q(add_subt_module_DMP[20]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_9_ ( .D(n1711),
.CK(clk), .RN(n5332), .Q(add_subt_module_DMP[9]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_16_ ( .D(n1710), .CK(clk), .RN(n5316), .Q(add_subt_module_DMP[16]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_50_ ( .D(n1707), .CK(clk), .RN(n5317), .Q(add_subt_module_DMP[50]) );
DFFRX2TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_48_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[48]),
.CK(clk), .RN(n5335), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[103]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_60_ ( .D(n1935), .CK(clk), .RN(n5338), .Q(add_subt_module_DmP[60]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_62_ ( .D(n1941), .CK(clk), .RN(n5338), .Q(add_subt_module_DmP[62]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_61_ ( .D(n1938), .CK(clk), .RN(n5338), .Q(add_subt_module_DmP[61]) );
DFFRX1TS reg_LUT_Q_reg_3_ ( .D(n2798), .CK(clk), .RN(n5402), .Q(
d_ff3_LUT_out[3]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_9_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[9]),
.CK(clk), .RN(n5317), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[64]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_10_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[10]),
.CK(clk), .RN(n5351), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[65]) );
DFFRX2TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_47_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[47]),
.CK(clk), .RN(n5329), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[102]) );
DFFRXLTS add_subt_module_Exp_Operation_Module_Underflow_Q_reg_0_ ( .D(n2934),
.CK(clk), .RN(n5340), .Q(underflow_flag), .QN(n5237) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_43_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[43]),
.CK(clk), .RN(n5317), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[98]), .QN(
n5228) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_44_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[44]),
.CK(clk), .RN(n5349), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[99]), .QN(
n5227) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_46_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[46]),
.CK(clk), .RN(n5315), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[101]), .QN(
n5226) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_26_ ( .D(
n2622), .CK(clk), .RN(n5328), .Q(add_subt_module_Add_Subt_result[26]),
.QN(n5214) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_54_ ( .D(
n2595), .CK(clk), .RN(n5347), .Q(add_subt_module_Add_Subt_result[54]),
.QN(n5079) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_51_ ( .D(
n2647), .CK(clk), .RN(n5330), .Q(add_subt_module_Add_Subt_result[51]),
.QN(n5054) );
ADDFX1TS intadd_373_U2 ( .A(d_ff2_X[55]), .B(n5056), .CI(intadd_373_n2),
.CO(intadd_373_n1), .S(intadd_373_SUM_2_) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_2_ ( .D(
n2537), .CK(clk), .RN(n5331), .Q(
add_subt_module_Sgf_normalized_result[2]), .QN(n5242) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_46_ ( .D(
n2581), .CK(clk), .RN(n5315), .Q(
add_subt_module_Sgf_normalized_result[46]), .QN(n5183) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_43_ ( .D(
n2578), .CK(clk), .RN(n5320), .Q(
add_subt_module_Sgf_normalized_result[43]), .QN(n5167) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_39_ ( .D(
n2574), .CK(clk), .RN(n5335), .Q(
add_subt_module_Sgf_normalized_result[39]), .QN(n5136) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_37_ ( .D(
n2572), .CK(clk), .RN(n5335), .Q(
add_subt_module_Sgf_normalized_result[37]), .QN(n5121) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_23_ ( .D(
n2558), .CK(clk), .RN(n5317), .Q(
add_subt_module_Sgf_normalized_result[23]), .QN(n5106) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_14_ ( .D(
n2549), .CK(clk), .RN(n5315), .Q(
add_subt_module_Sgf_normalized_result[14]), .QN(n5091) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_10_ ( .D(n1716), .CK(clk), .RN(n5332), .Q(add_subt_module_DMP[10]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_24_ ( .D(n1730), .CK(clk), .RN(n5338), .Q(add_subt_module_DMP[24]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_3_ ( .D(n1708),
.CK(clk), .RN(n5331), .Q(add_subt_module_DMP[3]) );
DFFRX4TS add_subt_module_Sel_D_Q_reg_0_ ( .D(n2663), .CK(clk), .RN(n1959),
.Q(add_subt_module_FSM_selector_D) );
DFFRX4TS add_subt_module_FS_Module_state_reg_reg_3_ ( .D(n2930), .CK(clk),
.RN(n5337), .Q(add_subt_module_FS_Module_state_reg[3]) );
DFFRX4TS add_subt_module_Sel_C_Q_reg_0_ ( .D(n2650), .CK(clk), .RN(n1959),
.Q(add_subt_module_FSM_selector_C) );
DFFRX4TS cont_iter_count_reg_0_ ( .D(n2923), .CK(clk), .RN(n5352), .Q(
cont_iter_out[0]) );
CMPR32X2TS intadd_372_U4 ( .A(d_ff2_Y[53]), .B(n5049), .C(intadd_372_CI),
.CO(intadd_372_n3), .S(intadd_372_SUM_0_) );
CMPR32X2TS intadd_373_U4 ( .A(d_ff2_X[53]), .B(n5049), .C(intadd_373_CI),
.CO(intadd_373_n3), .S(intadd_373_SUM_0_) );
CMPR32X2TS intadd_373_U3 ( .A(d_ff2_X[54]), .B(n5118), .C(intadd_373_n3),
.CO(intadd_373_n2), .S(intadd_373_SUM_1_) );
CMPR32X2TS intadd_372_U3 ( .A(d_ff2_Y[54]), .B(n5118), .C(intadd_372_n3),
.CO(intadd_372_n2), .S(intadd_372_SUM_1_) );
CMPR32X2TS intadd_372_U2 ( .A(d_ff2_Y[55]), .B(n5056), .C(intadd_372_n2),
.CO(intadd_372_n1), .S(intadd_372_SUM_2_) );
OR3X4TS U3131 ( .A(cont_var_out[0]), .B(n4744), .C(n4743), .Y(n2992) );
AOI222X4TS U3132 ( .A0(n5168), .A1(n4650), .B0(n5168), .B1(n4602), .C0(n4601), .C1(n4600), .Y(n4604) );
AOI222X1TS U3133 ( .A0(n3294), .A1(d_ff2_Z[2]), .B0(n3254), .B1(d_ff1_Z[2]),
.C0(d_ff_Zn[2]), .C1(n4732), .Y(n3235) );
AOI222X1TS U3134 ( .A0(n3294), .A1(d_ff2_Z[1]), .B0(n3254), .B1(d_ff1_Z[1]),
.C0(d_ff_Zn[1]), .C1(n4732), .Y(n3246) );
AOI222X1TS U3135 ( .A0(n3294), .A1(d_ff2_Z[44]), .B0(n3302), .B1(d_ff1_Z[44]), .C0(d_ff_Zn[44]), .C1(n3285), .Y(n3257) );
AOI222X1TS U3136 ( .A0(n3303), .A1(d_ff2_Z[48]), .B0(n3302), .B1(d_ff1_Z[48]), .C0(d_ff_Zn[48]), .C1(n3285), .Y(n3265) );
AOI222X1TS U3137 ( .A0(n3306), .A1(d_ff2_Z[50]), .B0(n3302), .B1(d_ff1_Z[50]), .C0(d_ff_Zn[50]), .C1(n3285), .Y(n3286) );
AOI222X1TS U3138 ( .A0(n3303), .A1(d_ff2_Z[47]), .B0(n3302), .B1(d_ff1_Z[47]), .C0(d_ff_Zn[47]), .C1(n3285), .Y(n3272) );
AOI222X1TS U3139 ( .A0(n4711), .A1(d_ff2_Z[46]), .B0(n3302), .B1(d_ff1_Z[46]), .C0(d_ff_Zn[46]), .C1(n3285), .Y(n3251) );
AOI222X1TS U3140 ( .A0(n3303), .A1(d_ff2_Z[42]), .B0(n3302), .B1(d_ff1_Z[42]), .C0(d_ff_Zn[42]), .C1(n3300), .Y(n3275) );
AOI222X1TS U3141 ( .A0(n3303), .A1(d_ff2_Z[39]), .B0(n3302), .B1(d_ff1_Z[39]), .C0(d_ff_Zn[39]), .C1(n3285), .Y(n3278) );
AOI222X1TS U3142 ( .A0(n3294), .A1(d_ff2_Z[52]), .B0(n3302), .B1(d_ff1_Z[52]), .C0(d_ff_Zn[52]), .C1(n4732), .Y(n3288) );
AOI222X1TS U3143 ( .A0(n3294), .A1(d_ff2_Z[61]), .B0(n3302), .B1(d_ff1_Z[61]), .C0(d_ff_Zn[61]), .C1(n3300), .Y(n3266) );
AOI222X1TS U3144 ( .A0(n3303), .A1(d_ff2_Z[54]), .B0(n3305), .B1(d_ff1_Z[54]), .C0(d_ff_Zn[54]), .C1(n3285), .Y(n3260) );
AOI222X1TS U3145 ( .A0(n4711), .A1(d_ff2_Z[62]), .B0(n3298), .B1(d_ff1_Z[62]), .C0(d_ff_Zn[62]), .C1(n3285), .Y(n3274) );
AOI222X1TS U3146 ( .A0(n4711), .A1(d_ff2_Z[16]), .B0(n3305), .B1(d_ff1_Z[16]), .C0(d_ff_Zn[16]), .C1(n3285), .Y(n3259) );
AOI222X1TS U3147 ( .A0(n4711), .A1(d_ff2_Z[35]), .B0(n3298), .B1(d_ff1_Z[35]), .C0(d_ff_Zn[35]), .C1(n3300), .Y(n3271) );
AOI222X1TS U3148 ( .A0(n3294), .A1(d_ff2_Z[18]), .B0(n3305), .B1(d_ff1_Z[18]), .C0(d_ff_Zn[18]), .C1(n4807), .Y(n3279) );
AOI222X1TS U3149 ( .A0(n3306), .A1(d_ff2_Z[24]), .B0(n3305), .B1(d_ff1_Z[24]), .C0(d_ff_Zn[24]), .C1(n4807), .Y(n3307) );
AOI222X1TS U3150 ( .A0(n3303), .A1(d_ff2_Z[28]), .B0(n3298), .B1(d_ff1_Z[28]), .C0(d_ff_Zn[28]), .C1(n3285), .Y(n3276) );
AOI222X1TS U3151 ( .A0(n3294), .A1(d_ff2_Z[33]), .B0(n3298), .B1(d_ff1_Z[33]), .C0(d_ff_Zn[33]), .C1(n4807), .Y(n3261) );
AOI222X1TS U3152 ( .A0(n4711), .A1(d_ff2_Z[59]), .B0(n3254), .B1(d_ff1_Z[59]), .C0(d_ff_Zn[59]), .C1(n3291), .Y(n3242) );
AOI222X1TS U3153 ( .A0(n4711), .A1(d_ff2_Z[3]), .B0(n3254), .B1(d_ff1_Z[3]),
.C0(d_ff_Zn[3]), .C1(n3285), .Y(n3240) );
AOI222X1TS U3154 ( .A0(n3294), .A1(d_ff2_Z[6]), .B0(n3254), .B1(d_ff1_Z[6]),
.C0(d_ff_Zn[6]), .C1(n3285), .Y(n3248) );
AOI222X1TS U3155 ( .A0(n3294), .A1(d_ff2_Z[60]), .B0(n3254), .B1(d_ff1_Z[60]), .C0(d_ff_Zn[60]), .C1(n3285), .Y(n3236) );
AOI222X1TS U3156 ( .A0(n3294), .A1(d_ff2_Z[58]), .B0(n3254), .B1(d_ff1_Z[58]), .C0(d_ff_Zn[58]), .C1(n3285), .Y(n3249) );
AOI222X1TS U3157 ( .A0(n3294), .A1(d_ff2_Z[9]), .B0(n3254), .B1(d_ff1_Z[9]),
.C0(d_ff_Zn[9]), .C1(n3285), .Y(n3244) );
AOI222X1TS U3158 ( .A0(n3306), .A1(d_ff2_Z[8]), .B0(n3254), .B1(d_ff1_Z[8]),
.C0(d_ff_Zn[8]), .C1(n4798), .Y(n3234) );
AOI222X1TS U3159 ( .A0(n3306), .A1(d_ff2_Z[10]), .B0(n3254), .B1(d_ff1_Z[10]), .C0(d_ff_Zn[10]), .C1(n4807), .Y(n3237) );
AOI222X1TS U3160 ( .A0(n3306), .A1(d_ff2_Z[11]), .B0(n3254), .B1(d_ff1_Z[11]), .C0(d_ff_Zn[11]), .C1(n3300), .Y(n3239) );
AOI222X1TS U3161 ( .A0(n3306), .A1(d_ff2_Z[4]), .B0(n3254), .B1(d_ff1_Z[4]),
.C0(d_ff_Zn[4]), .C1(n4798), .Y(n3245) );
BUFX4TS U3162 ( .A(n2954), .Y(n3823) );
NAND2X4TS U3163 ( .A(n4735), .B(n5045), .Y(n4644) );
OAI222X1TS U3164 ( .A0(n4583), .A1(add_subt_module_Add_Subt_result[28]),
.B0(n4337), .B1(add_subt_module_Add_Subt_result[26]), .C0(
add_subt_module_FSM_selector_C), .C1(add_subt_module_DmP[24]), .Y(
n4448) );
NAND2X4TS U3165 ( .A(n4813), .B(sel_mux_1_reg), .Y(n4710) );
NOR2X6TS U3166 ( .A(n3135), .B(n3570), .Y(n3134) );
NOR2XLTS U3167 ( .A(add_subt_module_Add_Subt_result[41]), .B(n4749), .Y(
n3892) );
NOR2X6TS U3168 ( .A(add_subt_module_FSM_selector_B[1]), .B(
add_subt_module_FSM_selector_B[0]), .Y(n2953) );
OAI32X1TS U3169 ( .A0(n3950), .A1(add_subt_module_Add_Subt_result[6]), .A2(
add_subt_module_Add_Subt_result[4]), .B0(n3949), .B1(n3950), .Y(n4004)
);
INVX1TS U3170 ( .A(n3949), .Y(n3899) );
AOI211XLTS U3171 ( .A0(n4002), .A1(n4001), .B0(n4761), .C0(n4000), .Y(n4003)
);
AOI211XLTS U3172 ( .A0(add_subt_module_Add_Subt_result[17]), .A1(n4757),
.B0(n4756), .C0(n4755), .Y(n4758) );
AOI211XLTS U3173 ( .A0(n3964), .A1(n3963), .B0(n4756), .C0(n3962), .Y(n3965)
);
NAND3X1TS U3174 ( .A(n3991), .B(n5200), .C(n5052), .Y(n3904) );
NAND2BX1TS U3175 ( .AN(add_subt_module_Add_Subt_result[27]), .B(n3972), .Y(
n3893) );
NOR3X1TS U3176 ( .A(add_subt_module_Add_Subt_result[32]), .B(
add_subt_module_Add_Subt_result[31]), .C(n3968), .Y(n4002) );
AOI21X2TS U3177 ( .A0(n3634), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[105]), .B0(
n3633), .Y(n2958) );
NAND2X4TS U3178 ( .A(n3581), .B(n3684), .Y(n3582) );
BUFX3TS U3179 ( .A(n3735), .Y(n2954) );
NAND2X4TS U3180 ( .A(n3643), .B(n3131), .Y(n3128) );
BUFX4TS U3181 ( .A(n2992), .Y(n4784) );
BUFX3TS U3182 ( .A(n4886), .Y(n2977) );
OR2X4TS U3183 ( .A(n2980), .B(n4442), .Y(n4487) );
NAND2X4TS U3184 ( .A(n2980), .B(n4442), .Y(n3537) );
INVX4TS U3185 ( .A(n4576), .Y(n4533) );
CLKINVX3TS U3186 ( .A(n4037), .Y(n3675) );
NOR2X4TS U3187 ( .A(n4743), .B(n4741), .Y(n4742) );
BUFX4TS U3188 ( .A(n4813), .Y(n4803) );
NAND2X4TS U3189 ( .A(n4444), .B(n2980), .Y(n3309) );
BUFX4TS U3190 ( .A(n3575), .Y(n3788) );
BUFX6TS U3191 ( .A(n4838), .Y(n4818) );
CLKINVX3TS U3192 ( .A(n5006), .Y(n2956) );
NOR2X6TS U3193 ( .A(n3133), .B(n3131), .Y(n3129) );
BUFX4TS U3194 ( .A(n4417), .Y(n4530) );
BUFX4TS U3195 ( .A(n3088), .Y(n4838) );
NAND2X6TS U3196 ( .A(n3311), .B(add_subt_module_FSM_selector_C), .Y(n4337)
);
BUFX3TS U3197 ( .A(n3312), .Y(n4417) );
NAND2X4TS U3198 ( .A(n3113), .B(n4619), .Y(n3114) );
OA21X2TS U3199 ( .A0(n3906), .A1(n4624), .B0(n4623), .Y(n3123) );
NAND2BX4TS U3200 ( .AN(n3148), .B(sel_mux_3_reg), .Y(n3153) );
AND3X2TS U3201 ( .A(n3100), .B(n5045), .C(n5124), .Y(n3101) );
CLKAND2X4TS U3202 ( .A(n4616), .B(n4612), .Y(n3535) );
NAND3XLTS U3203 ( .A(cordic_FSM_state_reg[0]), .B(n4601), .C(n5057), .Y(
n3088) );
OR2X4TS U3204 ( .A(n4606), .B(n5168), .Y(n4845) );
BUFX4TS U3205 ( .A(n5337), .Y(n5343) );
NOR2X4TS U3206 ( .A(n5134), .B(add_subt_module_FSM_selector_B[1]), .Y(n3124)
);
CLKINVX2TS U3207 ( .A(n2960), .Y(n2983) );
NOR2BX1TS U3208 ( .AN(n4608), .B(n4102), .Y(n4053) );
BUFX6TS U3209 ( .A(n4053), .Y(n4113) );
MX2X1TS U3210 ( .A(add_subt_module_DMP[51]), .B(
add_subt_module_Sgf_normalized_result[53]), .S0(n4087), .Y(n4121) );
BUFX6TS U3211 ( .A(n4113), .Y(n4104) );
CLKAND2X2TS U3212 ( .A(n4102), .B(add_subt_module_Sgf_normalized_result[0]),
.Y(n4114) );
MX2X1TS U3213 ( .A(add_subt_module_DMP[34]), .B(
add_subt_module_Sgf_normalized_result[36]), .S0(n4064), .Y(n4259) );
NOR2XLTS U3214 ( .A(n5122), .B(n4071), .Y(n4061) );
MX2X1TS U3215 ( .A(add_subt_module_DMP[5]), .B(
add_subt_module_Sgf_normalized_result[7]), .S0(n4102), .Y(n4166) );
NOR2XLTS U3216 ( .A(n5087), .B(add_subt_module_FSM_selector_D), .Y(n4094) );
NOR2XLTS U3217 ( .A(n5111), .B(n4071), .Y(n4067) );
MX2X1TS U3218 ( .A(add_subt_module_DMP[1]), .B(
add_subt_module_Sgf_normalized_result[3]), .S0(n4102), .Y(n4138) );
NOR2XLTS U3219 ( .A(n5085), .B(add_subt_module_FSM_selector_D), .Y(n4098) );
MX2X1TS U3220 ( .A(add_subt_module_DMP[19]), .B(
add_subt_module_Sgf_normalized_result[21]), .S0(n4086), .Y(n4279) );
NOR2XLTS U3221 ( .A(n5103), .B(n4087), .Y(n4078) );
MX2X1TS U3222 ( .A(add_subt_module_DMP[17]), .B(
add_subt_module_Sgf_normalized_result[19]), .S0(n4086), .Y(n4263) );
NOR2XLTS U3223 ( .A(n5098), .B(n4087), .Y(n4080) );
MX2X1TS U3224 ( .A(add_subt_module_DMP[50]), .B(
add_subt_module_Sgf_normalized_result[52]), .S0(n4064), .Y(n4125) );
MX2X1TS U3225 ( .A(add_subt_module_DMP[3]), .B(
add_subt_module_Sgf_normalized_result[5]), .S0(n4102), .Y(n4150) );
NOR2XLTS U3226 ( .A(n5083), .B(add_subt_module_FSM_selector_D), .Y(n4096) );
MX2X1TS U3227 ( .A(add_subt_module_DMP[32]), .B(
add_subt_module_Sgf_normalized_result[34]), .S0(n4064), .Y(n4275) );
NOR2XLTS U3228 ( .A(n5115), .B(n4087), .Y(n4063) );
MX2X1TS U3229 ( .A(add_subt_module_DMP[22]), .B(
add_subt_module_Sgf_normalized_result[24]), .S0(n4086), .Y(n4303) );
NOR2XLTS U3230 ( .A(n5105), .B(n4087), .Y(n4075) );
MX2X1TS U3231 ( .A(add_subt_module_DMP[46]), .B(
add_subt_module_Sgf_normalized_result[48]), .S0(n4064), .Y(n4161) );
NOR2XLTS U3232 ( .A(n5113), .B(n4071), .Y(n4069) );
MX2X1TS U3233 ( .A(add_subt_module_DMP[43]), .B(
add_subt_module_Sgf_normalized_result[45]), .S0(n4064), .Y(n4181) );
MX2X1TS U3234 ( .A(add_subt_module_DMP[12]), .B(
add_subt_module_Sgf_normalized_result[14]), .S0(n4086), .Y(n4223) );
MX2X1TS U3235 ( .A(add_subt_module_DMP[8]), .B(
add_subt_module_Sgf_normalized_result[10]), .S0(n4102), .Y(n4190) );
NOR2XLTS U3236 ( .A(n5089), .B(add_subt_module_FSM_selector_D), .Y(n4091) );
MX2X1TS U3237 ( .A(add_subt_module_DMP[15]), .B(
add_subt_module_Sgf_normalized_result[17]), .S0(n4086), .Y(n4251) );
NOR2XLTS U3238 ( .A(n5107), .B(n4071), .Y(n4072) );
MX2X1TS U3239 ( .A(add_subt_module_DMP[42]), .B(
add_subt_module_Sgf_normalized_result[44]), .S0(n4064), .Y(n4193) );
MX2X1TS U3240 ( .A(add_subt_module_DMP[36]), .B(
add_subt_module_Sgf_normalized_result[38]), .S0(n4064), .Y(n4239) );
NOR2XLTS U3241 ( .A(n5137), .B(n4071), .Y(n4059) );
MX2X1TS U3242 ( .A(add_subt_module_DMP[21]), .B(
add_subt_module_Sgf_normalized_result[23]), .S0(n4086), .Y(n4299) );
MX2X1TS U3243 ( .A(add_subt_module_DMP[6]), .B(
add_subt_module_Sgf_normalized_result[8]), .S0(n4102), .Y(n4174) );
NOR2XLTS U3244 ( .A(n5086), .B(add_subt_module_FSM_selector_D), .Y(n4093) );
MX2X1TS U3245 ( .A(add_subt_module_DMP[40]), .B(
add_subt_module_Sgf_normalized_result[42]), .S0(n4064), .Y(n4205) );
MX2X1TS U3246 ( .A(add_subt_module_DMP[28]), .B(
add_subt_module_Sgf_normalized_result[30]), .S0(n4086), .Y(n4307) );
NOR2XLTS U3247 ( .A(n5112), .B(n4071), .Y(n4068) );
MX2X1TS U3248 ( .A(add_subt_module_DMP[10]), .B(
add_subt_module_Sgf_normalized_result[12]), .S0(n4102), .Y(n4210) );
NOR2XLTS U3249 ( .A(n5093), .B(add_subt_module_FSM_selector_D), .Y(n4089) );
NAND2BXLTS U3250 ( .AN(add_subt_module_Sgf_normalized_result[54]), .B(n4102),
.Y(n4109) );
MX2X1TS U3251 ( .A(add_subt_module_DMP[45]), .B(
add_subt_module_Sgf_normalized_result[47]), .S0(n4064), .Y(n4169) );
NOR2XLTS U3252 ( .A(n5116), .B(n4071), .Y(n4065) );
MX2X1TS U3253 ( .A(add_subt_module_DMP[23]), .B(
add_subt_module_Sgf_normalized_result[25]), .S0(n4086), .Y(n4315) );
MX2X1TS U3254 ( .A(add_subt_module_DMP[48]), .B(
add_subt_module_Sgf_normalized_result[50]), .S0(n4064), .Y(n4141) );
MX2X1TS U3255 ( .A(add_subt_module_DMP[2]), .B(
add_subt_module_Sgf_normalized_result[4]), .S0(n4102), .Y(n4146) );
NOR2XLTS U3256 ( .A(n5084), .B(add_subt_module_FSM_selector_D), .Y(n4097) );
CLKAND2X2TS U3257 ( .A(n4102), .B(add_subt_module_Sgf_normalized_result[1]),
.Y(n4118) );
MX2X1TS U3258 ( .A(add_subt_module_DMP[14]), .B(
add_subt_module_Sgf_normalized_result[16]), .S0(n4086), .Y(n4243) );
MX2X1TS U3259 ( .A(add_subt_module_DMP[18]), .B(
add_subt_module_Sgf_normalized_result[20]), .S0(n4086), .Y(n4271) );
NAND2BXLTS U3260 ( .AN(add_subt_module_intDY[2]), .B(
add_subt_module_intDX[2]), .Y(n3416) );
NAND2BXLTS U3261 ( .AN(add_subt_module_intDY[51]), .B(
add_subt_module_intDX[51]), .Y(n3516) );
NAND2BXLTS U3262 ( .AN(add_subt_module_intDY[19]), .B(
add_subt_module_intDX[19]), .Y(n3447) );
NAND2BXLTS U3263 ( .AN(add_subt_module_intDY[27]), .B(
add_subt_module_intDX[27]), .Y(n3402) );
NAND2BXLTS U3264 ( .AN(add_subt_module_intDY[9]), .B(
add_subt_module_intDX[9]), .Y(n3427) );
NAND2BXLTS U3265 ( .AN(add_subt_module_intDY[21]), .B(
add_subt_module_intDX[21]), .Y(n3410) );
NAND2BXLTS U3266 ( .AN(add_subt_module_intDY[47]), .B(
add_subt_module_intDX[47]), .Y(n3478) );
NAND2BXLTS U3267 ( .AN(add_subt_module_intDY[59]), .B(
add_subt_module_intDX[59]), .Y(n3467) );
NAND2BXLTS U3268 ( .AN(add_subt_module_intDY[29]), .B(
add_subt_module_intDX[29]), .Y(n3400) );
NAND3BXLTS U3269 ( .AN(n3450), .B(n3443), .C(n3442), .Y(n3463) );
NOR2X1TS U3270 ( .A(add_subt_module_Add_Subt_result[26]), .B(n3893), .Y(
n3981) );
NAND2X1TS U3271 ( .A(n3892), .B(n3980), .Y(n3956) );
NAND2X1TS U3272 ( .A(n3981), .B(n5110), .Y(n3966) );
CLKAND2X2TS U3273 ( .A(n4011), .B(n5048), .Y(n3947) );
CLKAND2X2TS U3274 ( .A(n3581), .B(n3637), .Y(n2965) );
CLKINVX6TS U3275 ( .A(n3570), .Y(n3634) );
CLKAND2X2TS U3276 ( .A(n3688), .B(n3792), .Y(n2966) );
CLKINVX6TS U3277 ( .A(n3135), .Y(n3792) );
NAND2BXLTS U3278 ( .AN(add_subt_module_intDY[40]), .B(
add_subt_module_intDX[40]), .Y(n3395) );
NAND2BXLTS U3279 ( .AN(add_subt_module_intDY[41]), .B(
add_subt_module_intDX[41]), .Y(n3396) );
NAND2BXLTS U3280 ( .AN(n2987), .B(add_subt_module_intDX[32]), .Y(n3397) );
NAND2BXLTS U3281 ( .AN(add_subt_module_intDY[62]), .B(
add_subt_module_intDX[62]), .Y(n3475) );
NAND2BXLTS U3282 ( .AN(add_subt_module_intDX[62]), .B(
add_subt_module_intDY[62]), .Y(n3473) );
CLKINVX6TS U3283 ( .A(n4533), .Y(n4540) );
NAND2BXLTS U3284 ( .AN(n3963), .B(n3964), .Y(n3951) );
NAND2X1TS U3285 ( .A(n3895), .B(n4757), .Y(n3902) );
NAND2X1TS U3286 ( .A(n5047), .B(n3947), .Y(n3943) );
NAND2X1TS U3287 ( .A(n3976), .B(n3946), .Y(n3894) );
NAND2X1TS U3288 ( .A(n4002), .B(n5055), .Y(n3960) );
CLKINVX6TS U3289 ( .A(n3535), .Y(n3859) );
NAND4BXLTS U3290 ( .AN(n4012), .B(n4011), .C(n5047), .D(n5215), .Y(n4014) );
NAND2X1TS U3291 ( .A(n3977), .B(n5101), .Y(n3968) );
NAND2BXLTS U3292 ( .AN(n3960), .B(add_subt_module_Add_Subt_result[28]), .Y(
n4015) );
NAND2X1TS U3293 ( .A(n4751), .B(n5082), .Y(n3998) );
NAND2BXLTS U3294 ( .AN(n3966), .B(add_subt_module_Add_Subt_result[24]), .Y(
n3997) );
OAI211XLTS U3295 ( .A0(n3969), .A1(n3968), .B0(n3967), .C0(n3997), .Y(n3970)
);
NAND3XLTS U3296 ( .A(n3994), .B(n3982), .C(n3996), .Y(n3983) );
NAND3XLTS U3297 ( .A(n5216), .B(add_subt_module_Add_Subt_result[34]), .C(
n4745), .Y(n3986) );
MX2X1TS U3298 ( .A(add_subt_module_DMP[13]), .B(
add_subt_module_Sgf_normalized_result[15]), .S0(n4086), .Y(n4235) );
MX2X1TS U3299 ( .A(add_subt_module_DMP[41]), .B(
add_subt_module_Sgf_normalized_result[43]), .S0(n4064), .Y(n4197) );
MX2X1TS U3300 ( .A(add_subt_module_DMP[49]), .B(
add_subt_module_Sgf_normalized_result[51]), .S0(n4064), .Y(n4133) );
MX2X1TS U3301 ( .A(add_subt_module_DMP[9]), .B(
add_subt_module_Sgf_normalized_result[11]), .S0(n4102), .Y(n4202) );
NOR2XLTS U3302 ( .A(n5094), .B(add_subt_module_FSM_selector_D), .Y(n4090) );
CLKINVX6TS U3303 ( .A(n3924), .Y(n3700) );
AO22XLTS U3304 ( .A0(n3631), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[105]), .B0(
n3129), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[97]), .Y(
n3616) );
AO22XLTS U3305 ( .A0(n3631), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[104]), .B0(
n3129), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[96]), .Y(
n3130) );
AOI211X2TS U3306 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[103]), .A1(
n3631), .B0(n3683), .C0(n3139), .Y(n3661) );
AO22XLTS U3307 ( .A0(n3634), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[87]), .B0(
n3129), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[95]), .Y(
n3139) );
OAI211X1TS U3308 ( .A0(n3792), .A1(n3796), .B0(n3614), .C0(n3613), .Y(n3646)
);
AOI211X2TS U3309 ( .A0(n3634), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[92]), .B0(
n3683), .C0(n3612), .Y(n3770) );
AO22XLTS U3310 ( .A0(n3631), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[108]), .B0(
n3129), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[100]), .Y(
n3612) );
OAI211X1TS U3311 ( .A0(n3792), .A1(n3590), .B0(n3559), .C0(n3558), .Y(n3591)
);
OAI211X1TS U3312 ( .A0(n3792), .A1(n3801), .B0(n3629), .C0(n3628), .Y(n3653)
);
MX2X1TS U3313 ( .A(add_subt_module_DMP[11]), .B(
add_subt_module_Sgf_normalized_result[13]), .S0(n4086), .Y(n4219) );
CLKINVX6TS U3314 ( .A(n3702), .Y(n3688) );
MX2X1TS U3315 ( .A(add_subt_module_DMP[7]), .B(
add_subt_module_Sgf_normalized_result[9]), .S0(n4102), .Y(n4186) );
NOR2XLTS U3316 ( .A(n5090), .B(add_subt_module_FSM_selector_D), .Y(n4092) );
MX2X1TS U3317 ( .A(add_subt_module_DMP[26]), .B(
add_subt_module_Sgf_normalized_result[28]), .S0(n4086), .Y(n4320) );
NOR2XLTS U3318 ( .A(n5108), .B(n4071), .Y(n4070) );
AOI31X1TS U3319 ( .A0(cont_var_out[0]), .A1(n4633), .A2(n4654), .B0(n4829),
.Y(n4634) );
MX2X1TS U3320 ( .A(add_subt_module_DMP[47]), .B(
add_subt_module_Sgf_normalized_result[49]), .S0(n4064), .Y(n4153) );
NOR2XLTS U3321 ( .A(n5123), .B(n4071), .Y(n4062) );
MX2X1TS U3322 ( .A(add_subt_module_DMP[24]), .B(
add_subt_module_Sgf_normalized_result[26]), .S0(n4086), .Y(n4324) );
MX2X1TS U3323 ( .A(add_subt_module_DMP[44]), .B(
add_subt_module_Sgf_normalized_result[46]), .S0(n4064), .Y(n4177) );
MX2X1TS U3324 ( .A(add_subt_module_DMP[30]), .B(
add_subt_module_Sgf_normalized_result[32]), .S0(n4086), .Y(n4291) );
NOR2XLTS U3325 ( .A(n5117), .B(n4071), .Y(n4066) );
MX2X1TS U3326 ( .A(add_subt_module_DMP[38]), .B(
add_subt_module_Sgf_normalized_result[40]), .S0(n4064), .Y(n4227) );
NOR2XLTS U3327 ( .A(n5135), .B(n4071), .Y(n4056) );
MX2X1TS U3328 ( .A(add_subt_module_DMP[4]), .B(
add_subt_module_Sgf_normalized_result[6]), .S0(n4102), .Y(n4158) );
NOR2XLTS U3329 ( .A(n5088), .B(add_subt_module_FSM_selector_D), .Y(n4095) );
MX2X1TS U3330 ( .A(add_subt_module_DMP[0]), .B(
add_subt_module_Sgf_normalized_result[2]), .S0(n4102), .Y(n4130) );
MX2X1TS U3331 ( .A(add_subt_module_DMP[16]), .B(
add_subt_module_Sgf_normalized_result[18]), .S0(n4086), .Y(n4255) );
OAI211X1TS U3332 ( .A0(n3792), .A1(n3791), .B0(n3790), .C0(n3789), .Y(n3922)
);
CLKINVX6TS U3333 ( .A(n3535), .Y(n3879) );
BUFX4TS U3334 ( .A(n4574), .Y(n4550) );
AO22XLTS U3335 ( .A0(n4578), .A1(add_subt_module_Add_Subt_result[1]), .B0(
n4577), .B1(add_subt_module_Add_Subt_result[53]), .Y(n4588) );
AOI31XLTS U3336 ( .A0(n3895), .A1(n5238), .A2(n5051), .B0(n3894), .Y(n3896)
);
NAND2BXLTS U3337 ( .AN(n3902), .B(add_subt_module_Add_Subt_result[15]), .Y(
n4752) );
OAI211XLTS U3338 ( .A0(n3944), .A1(n3943), .B0(n3942), .C0(n3982), .Y(n3945)
);
OAI211XLTS U3339 ( .A0(add_subt_module_Add_Subt_result[5]), .A1(n3940), .B0(
n3949), .C0(n5223), .Y(n3942) );
NAND4XLTS U3340 ( .A(n3995), .B(n3994), .C(n4013), .D(n3993), .Y(n4761) );
MX2X1TS U3341 ( .A(add_subt_module_DMP[20]), .B(
add_subt_module_Sgf_normalized_result[22]), .S0(n4086), .Y(n4287) );
NOR2XLTS U3342 ( .A(n5102), .B(add_subt_module_FSM_selector_D), .Y(n4077) );
NAND2X1TS U3343 ( .A(n4660), .B(n5056), .Y(n4655) );
OAI31X1TS U3344 ( .A0(cont_iter_out[2]), .A1(cont_iter_out[3]), .A2(n4679),
.B0(n4706), .Y(n4684) );
AO22XLTS U3345 ( .A0(n4767), .A1(result_add_subt[60]), .B0(n4792), .B1(
d_ff_Xn[60]), .Y(n2523) );
AO22XLTS U3346 ( .A0(n4767), .A1(result_add_subt[63]), .B0(n4780), .B1(
d_ff_Xn[63]), .Y(n2932) );
AO22XLTS U3347 ( .A0(n4773), .A1(result_add_subt[25]), .B0(n4843), .B1(
d_ff_Xn[25]), .Y(n2383) );
AO21XLTS U3348 ( .A0(add_subt_module_LZA_output[1]), .A1(n4024), .B0(n4023),
.Y(n2591) );
AOI31XLTS U3349 ( .A0(add_subt_module_Add_Subt_result[16]), .A1(n4757), .A2(
n5053), .B0(n4020), .Y(n4021) );
AO22XLTS U3350 ( .A0(n4767), .A1(result_add_subt[61]), .B0(n4792), .B1(
d_ff_Xn[61]), .Y(n2527) );
AOI2BB2XLTS U3351 ( .B0(n4004), .B1(n3965), .A0N(n4763), .A1N(
add_subt_module_LZA_output[2]), .Y(n2594) );
AO22XLTS U3352 ( .A0(d_ff_Yn[14]), .A1(n4809), .B0(d_ff2_Y[14]), .B1(n4841),
.Y(n2190) );
AO22XLTS U3353 ( .A0(d_ff_Yn[22]), .A1(n4799), .B0(d_ff2_Y[22]), .B1(n4811),
.Y(n2174) );
AO22XLTS U3354 ( .A0(d_ff_Yn[63]), .A1(n4809), .B0(d_ff2_Y[63]), .B1(n4841),
.Y(n2092) );
MX2X1TS U3355 ( .A(add_subt_module_Add_Subt_result[36]), .B(n4260), .S0(
n4325), .Y(n2632) );
MX2X1TS U3356 ( .A(n4007), .B(add_subt_module_LZA_output[3]), .S0(n4024),
.Y(n2593) );
OAI211XLTS U3357 ( .A0(n4006), .A1(n4005), .B0(n4004), .C0(n4003), .Y(n4007)
);
OAI211XLTS U3358 ( .A0(n3999), .A1(n3998), .B0(n3997), .C0(n3996), .Y(n4000)
);
AO22XLTS U3359 ( .A0(n4649), .A1(shift_region_flag[0]), .B0(n4645), .B1(
d_ff1_shift_region_flag_out[0]), .Y(n2919) );
MX2X1TS U3360 ( .A(add_subt_module_Add_Subt_result[44]), .B(n4195), .S0(
n4325), .Y(n2640) );
MX2X1TS U3361 ( .A(add_subt_module_Add_Subt_result[31]), .B(n4296), .S0(
n4330), .Y(n2627) );
NAND2BXLTS U3362 ( .AN(d_ff3_LUT_out[48]), .B(n4817), .Y(n2843) );
OAI32X1TS U3363 ( .A0(n3919), .A1(n3915), .A2(n5212), .B0(n4744), .B1(n3918),
.Y(n2851) );
AO22XLTS U3364 ( .A0(n4647), .A1(operation), .B0(n4640), .B1(
d_ff1_operation_out), .Y(n2920) );
MX2X1TS U3365 ( .A(add_subt_module_Add_Subt_result[53]), .B(n4123), .S0(
n4330), .Y(n2649) );
MX2X1TS U3366 ( .A(add_subt_module_Add_Subt_result[52]), .B(n4127), .S0(
n4325), .Y(n2648) );
MX2X1TS U3367 ( .A(add_subt_module_Add_Subt_result[38]), .B(n4240), .S0(
n4330), .Y(n2634) );
MX2X1TS U3368 ( .A(add_subt_module_Add_Subt_result[34]), .B(n4276), .S0(
n4325), .Y(n2630) );
MX2X1TS U3369 ( .A(add_subt_module_Add_Subt_result[48]), .B(n4163), .S0(
n4325), .Y(n2644) );
MX2X1TS U3370 ( .A(add_subt_module_add_overflow_flag), .B(n4106), .S0(n4325),
.Y(n2936) );
MX2X1TS U3371 ( .A(add_subt_module_Add_Subt_result[29]), .B(n4312), .S0(
n4330), .Y(n2625) );
MX2X1TS U3372 ( .A(add_subt_module_Add_Subt_result[45]), .B(n4183), .S0(
n4330), .Y(n2641) );
MX2X1TS U3373 ( .A(add_subt_module_Add_Subt_result[42]), .B(n4207), .S0(
n4330), .Y(n2638) );
MX2X1TS U3374 ( .A(add_subt_module_Add_Subt_result[43]), .B(n4199), .S0(
n4330), .Y(n2639) );
MX2X1TS U3375 ( .A(add_subt_module_Add_Subt_result[51]), .B(n4135), .S0(
n4325), .Y(n2647) );
MX2X1TS U3376 ( .A(add_subt_module_Add_Subt_result[30]), .B(n4308), .S0(
n4325), .Y(n2626) );
MX2X1TS U3377 ( .A(add_subt_module_Add_Subt_result[37]), .B(n4248), .S0(
n4325), .Y(n2633) );
MX2X1TS U3378 ( .A(add_subt_module_Add_Subt_result[54]), .B(n4111), .S0(
n4330), .Y(n2595) );
OAI32X1TS U3379 ( .A0(n4774), .A1(overflow_flag), .A2(n3008), .B0(n4772),
.B1(n5080), .Y(n2933) );
MX2X1TS U3380 ( .A(add_subt_module_Add_Subt_result[47]), .B(n4171), .S0(
n4325), .Y(n2643) );
MX2X1TS U3381 ( .A(add_subt_module_Add_Subt_result[33]), .B(n4284), .S0(
n4330), .Y(n2629) );
AOI211X1TS U3382 ( .A0(n4612), .A1(n5114), .B0(n4620), .C0(n4611), .Y(n4614)
);
AOI211X1TS U3383 ( .A0(cont_var_out[1]), .A1(n5205), .B0(n4632), .C0(n4599),
.Y(n4602) );
MX2X1TS U3384 ( .A(add_subt_module_Add_Subt_result[50]), .B(n4143), .S0(
n4330), .Y(n2646) );
MX2X1TS U3385 ( .A(add_subt_module_Add_Subt_result[28]), .B(n4321), .S0(
n4330), .Y(n2624) );
MX2X1TS U3386 ( .A(add_subt_module_Add_Subt_result[49]), .B(n4155), .S0(
n4325), .Y(n2645) );
MX2X1TS U3387 ( .A(add_subt_module_Add_Subt_result[35]), .B(n4268), .S0(
n4330), .Y(n2631) );
MX2X1TS U3388 ( .A(add_subt_module_Add_Subt_result[41]), .B(n4216), .S0(
n4325), .Y(n2637) );
MX2X1TS U3389 ( .A(add_subt_module_Add_Subt_result[46]), .B(n4179), .S0(
n4325), .Y(n2642) );
MX2X1TS U3390 ( .A(add_subt_module_Add_Subt_result[32]), .B(n4292), .S0(
n4325), .Y(n2628) );
MX2X1TS U3391 ( .A(add_subt_module_Add_Subt_result[40]), .B(n4228), .S0(
n4330), .Y(n2636) );
AO22XLTS U3392 ( .A0(n4797), .A1(d_ff_Yn[26]), .B0(n4796), .B1(
result_add_subt[26]), .Y(n2388) );
AO22XLTS U3393 ( .A0(n4771), .A1(d_ff_Yn[28]), .B0(n4796), .B1(
result_add_subt[28]), .Y(n2396) );
AO22XLTS U3394 ( .A0(n4797), .A1(d_ff_Yn[22]), .B0(n4775), .B1(
result_add_subt[22]), .Y(n2372) );
AO22XLTS U3395 ( .A0(n4797), .A1(d_ff_Yn[24]), .B0(n4775), .B1(
result_add_subt[24]), .Y(n2380) );
AO22XLTS U3396 ( .A0(n4797), .A1(d_ff_Yn[32]), .B0(n4796), .B1(
result_add_subt[32]), .Y(n2412) );
AO22XLTS U3397 ( .A0(n4797), .A1(d_ff_Yn[17]), .B0(n4775), .B1(
result_add_subt[17]), .Y(n2352) );
AO22XLTS U3398 ( .A0(n4771), .A1(d_ff_Yn[33]), .B0(n4796), .B1(
result_add_subt[33]), .Y(n2416) );
AO22XLTS U3399 ( .A0(n4797), .A1(d_ff_Yn[18]), .B0(n4775), .B1(
result_add_subt[18]), .Y(n2356) );
AO22XLTS U3400 ( .A0(n4797), .A1(d_ff_Yn[21]), .B0(n4775), .B1(
result_add_subt[21]), .Y(n2368) );
AO22XLTS U3401 ( .A0(n4797), .A1(d_ff_Yn[29]), .B0(n4796), .B1(
result_add_subt[29]), .Y(n2400) );
AO22XLTS U3402 ( .A0(n4771), .A1(d_ff_Yn[31]), .B0(n4796), .B1(
result_add_subt[31]), .Y(n2408) );
AO22XLTS U3403 ( .A0(n4797), .A1(d_ff_Yn[27]), .B0(n4796), .B1(
result_add_subt[27]), .Y(n2392) );
AO22XLTS U3404 ( .A0(n4797), .A1(d_ff_Yn[14]), .B0(n4775), .B1(
result_add_subt[14]), .Y(n2340) );
AO22XLTS U3405 ( .A0(n4791), .A1(d_ff_Yn[36]), .B0(n4786), .B1(
result_add_subt[36]), .Y(n2428) );
AO22XLTS U3406 ( .A0(n4797), .A1(d_ff_Yn[15]), .B0(n4775), .B1(
result_add_subt[15]), .Y(n2344) );
AO22XLTS U3407 ( .A0(n4791), .A1(d_ff_Yn[35]), .B0(n4796), .B1(
result_add_subt[35]), .Y(n2424) );
AO22XLTS U3408 ( .A0(n4771), .A1(d_ff_Yn[30]), .B0(n4796), .B1(
result_add_subt[30]), .Y(n2404) );
AO22XLTS U3409 ( .A0(n4797), .A1(d_ff_Yn[23]), .B0(n4775), .B1(
result_add_subt[23]), .Y(n2376) );
AO22XLTS U3410 ( .A0(n4791), .A1(d_ff_Yn[34]), .B0(n4796), .B1(
result_add_subt[34]), .Y(n2420) );
AO22XLTS U3411 ( .A0(n4797), .A1(d_ff_Yn[19]), .B0(n4775), .B1(
result_add_subt[19]), .Y(n2360) );
AO22XLTS U3412 ( .A0(n4791), .A1(d_ff_Yn[37]), .B0(n4786), .B1(
result_add_subt[37]), .Y(n2432) );
AO22XLTS U3413 ( .A0(n4791), .A1(d_ff_Yn[39]), .B0(n4786), .B1(
result_add_subt[39]), .Y(n2440) );
AO22XLTS U3414 ( .A0(n4771), .A1(d_ff_Yn[41]), .B0(n4786), .B1(
result_add_subt[41]), .Y(n2448) );
AO22XLTS U3415 ( .A0(n4791), .A1(d_ff_Yn[8]), .B0(n4781), .B1(
result_add_subt[8]), .Y(n2316) );
AO22XLTS U3416 ( .A0(n4771), .A1(d_ff_Yn[42]), .B0(n4786), .B1(
result_add_subt[42]), .Y(n2452) );
AO22XLTS U3417 ( .A0(n4791), .A1(d_ff_Yn[11]), .B0(n4781), .B1(
result_add_subt[11]), .Y(n2328) );
AO22XLTS U3418 ( .A0(n4797), .A1(d_ff_Yn[12]), .B0(n4781), .B1(
result_add_subt[12]), .Y(n2332) );
AO22XLTS U3419 ( .A0(n4791), .A1(d_ff_Yn[38]), .B0(n4786), .B1(
result_add_subt[38]), .Y(n2436) );
AO22XLTS U3420 ( .A0(n4771), .A1(d_ff_Yn[40]), .B0(n4786), .B1(
result_add_subt[40]), .Y(n2444) );
AO22XLTS U3421 ( .A0(n4791), .A1(d_ff_Yn[7]), .B0(n4781), .B1(
result_add_subt[7]), .Y(n2312) );
AO22XLTS U3422 ( .A0(n4771), .A1(d_ff_Yn[43]), .B0(n4786), .B1(
result_add_subt[43]), .Y(n2456) );
AO22XLTS U3423 ( .A0(n4791), .A1(d_ff_Yn[10]), .B0(n4786), .B1(
result_add_subt[10]), .Y(n2324) );
AO22XLTS U3424 ( .A0(n4797), .A1(d_ff_Yn[13]), .B0(n4781), .B1(
result_add_subt[13]), .Y(n2336) );
AO22XLTS U3425 ( .A0(n4797), .A1(d_ff_Yn[20]), .B0(n4775), .B1(
result_add_subt[20]), .Y(n2364) );
AO22XLTS U3426 ( .A0(n4771), .A1(d_ff_Yn[45]), .B0(n4786), .B1(
result_add_subt[45]), .Y(n2464) );
AO22XLTS U3427 ( .A0(n4791), .A1(d_ff_Yn[5]), .B0(n4781), .B1(
result_add_subt[5]), .Y(n2304) );
AO22XLTS U3428 ( .A0(n4791), .A1(d_ff_Yn[6]), .B0(n4781), .B1(
result_add_subt[6]), .Y(n2308) );
AO22XLTS U3429 ( .A0(n4771), .A1(d_ff_Yn[44]), .B0(n4786), .B1(
result_add_subt[44]), .Y(n2460) );
AO22XLTS U3430 ( .A0(n4791), .A1(d_ff_Yn[9]), .B0(n4781), .B1(
result_add_subt[9]), .Y(n2320) );
AO22XLTS U3431 ( .A0(n4797), .A1(d_ff_Yn[16]), .B0(n4775), .B1(
result_add_subt[16]), .Y(n2348) );
AO22XLTS U3432 ( .A0(n4765), .A1(d_ff_Yn[46]), .B0(n4786), .B1(
result_add_subt[46]), .Y(n2468) );
AO22XLTS U3433 ( .A0(n4765), .A1(d_ff_Yn[49]), .B0(n4781), .B1(
result_add_subt[49]), .Y(n2480) );
AO22XLTS U3434 ( .A0(n4791), .A1(d_ff_Yn[1]), .B0(n4796), .B1(
result_add_subt[1]), .Y(n2288) );
AO22XLTS U3435 ( .A0(n4791), .A1(d_ff_Yn[3]), .B0(n4796), .B1(
result_add_subt[3]), .Y(n2296) );
AO22XLTS U3436 ( .A0(n4765), .A1(d_ff_Yn[47]), .B0(n4781), .B1(
result_add_subt[47]), .Y(n2472) );
AO22XLTS U3437 ( .A0(n4765), .A1(d_ff_Yn[50]), .B0(n4781), .B1(
result_add_subt[50]), .Y(n2484) );
AO22XLTS U3438 ( .A0(n4791), .A1(d_ff_Yn[2]), .B0(n4786), .B1(
result_add_subt[2]), .Y(n2292) );
AO22XLTS U3439 ( .A0(n4765), .A1(d_ff_Yn[48]), .B0(n4781), .B1(
result_add_subt[48]), .Y(n2476) );
AO22XLTS U3440 ( .A0(n4791), .A1(d_ff_Yn[4]), .B0(n4781), .B1(
result_add_subt[4]), .Y(n2300) );
AO22XLTS U3441 ( .A0(n4765), .A1(d_ff_Yn[51]), .B0(n4781), .B1(
result_add_subt[51]), .Y(n2488) );
AO22XLTS U3442 ( .A0(n4797), .A1(d_ff_Yn[0]), .B0(n4796), .B1(
result_add_subt[0]), .Y(n2219) );
AO22XLTS U3443 ( .A0(n4765), .A1(d_ff_Yn[52]), .B0(n4781), .B1(
result_add_subt[52]), .Y(n2492) );
AO22XLTS U3444 ( .A0(n4765), .A1(d_ff_Yn[53]), .B0(n4781), .B1(
result_add_subt[53]), .Y(n2496) );
AO22XLTS U3445 ( .A0(n4771), .A1(d_ff_Yn[54]), .B0(n4781), .B1(
result_add_subt[54]), .Y(n2500) );
AO22XLTS U3446 ( .A0(n4771), .A1(d_ff_Yn[55]), .B0(n4781), .B1(
result_add_subt[55]), .Y(n2504) );
AO22XLTS U3447 ( .A0(n4771), .A1(d_ff_Yn[56]), .B0(n4781), .B1(
result_add_subt[56]), .Y(n2508) );
AO22XLTS U3448 ( .A0(n4771), .A1(d_ff_Yn[57]), .B0(n4781), .B1(
result_add_subt[57]), .Y(n2512) );
AO22XLTS U3449 ( .A0(n4771), .A1(d_ff_Yn[58]), .B0(n4742), .B1(
result_add_subt[58]), .Y(n2516) );
AO22XLTS U3450 ( .A0(n4771), .A1(d_ff_Yn[59]), .B0(n4742), .B1(
result_add_subt[59]), .Y(n2520) );
AO22XLTS U3451 ( .A0(n4771), .A1(d_ff_Yn[60]), .B0(n4742), .B1(
result_add_subt[60]), .Y(n2524) );
AO22XLTS U3452 ( .A0(n4771), .A1(d_ff_Yn[61]), .B0(n4775), .B1(
result_add_subt[61]), .Y(n2528) );
AO22XLTS U3453 ( .A0(n4791), .A1(d_ff_Yn[62]), .B0(n4742), .B1(
result_add_subt[62]), .Y(n2532) );
AOI211XLTS U3454 ( .A0(n3992), .A1(n3991), .B0(n3897), .C0(n3896), .Y(n3910)
);
OAI211XLTS U3455 ( .A0(n4760), .A1(n5221), .B0(n4759), .C0(n4758), .Y(n4762)
);
OAI211XLTS U3456 ( .A0(n5213), .A1(n4754), .B0(n4753), .C0(n4752), .Y(n4755)
);
MX2X1TS U3457 ( .A(n2984), .B(n4232), .S0(n4330), .Y(n2635) );
AO22X1TS U3458 ( .A0(add_subt_module_LZA_output[1]), .A1(n3124), .B0(n2953),
.B1(add_subt_module_exp_oper_result[1]), .Y(n2959) );
AOI21X2TS U3459 ( .A0(n4569), .A1(n5213), .B0(n4404), .Y(n2967) );
NOR2X2TS U3460 ( .A(n4702), .B(n4664), .Y(n2968) );
BUFX4TS U3461 ( .A(n5039), .Y(n4886) );
BUFX4TS U3462 ( .A(n5404), .Y(n5337) );
OAI21X1TS U3463 ( .A0(n3570), .A1(n5227), .B0(n3128), .Y(n3545) );
OAI21X1TS U3464 ( .A0(n3570), .A1(n5229), .B0(n3128), .Y(n3550) );
OAI21X1TS U3465 ( .A0(n3570), .A1(n5228), .B0(n3128), .Y(n3554) );
BUFX4TS U3466 ( .A(n5344), .Y(n5338) );
NOR2X2TS U3467 ( .A(cont_iter_out[3]), .B(n4669), .Y(n3231) );
BUFX4TS U3468 ( .A(n5345), .Y(n5321) );
CLKINVX6TS U3469 ( .A(n4803), .Y(n4841) );
CLKINVX6TS U3470 ( .A(n4803), .Y(n4811) );
CLKINVX6TS U3471 ( .A(n3123), .Y(n3785) );
AOI21X2TS U3472 ( .A0(n3634), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[104]), .B0(
n3633), .Y(n3796) );
AOI21X2TS U3473 ( .A0(n3634), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[102]), .B0(
n3633), .Y(n3590) );
AOI21X2TS U3474 ( .A0(n3634), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[103]), .B0(
n3633), .Y(n3801) );
AOI21X2TS U3475 ( .A0(n3634), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[108]), .B0(
n3633), .Y(n3767) );
CLKINVX6TS U3476 ( .A(n4818), .Y(n4729) );
NAND2X2TS U3477 ( .A(n2997), .B(n2996), .Y(n3127) );
NOR2X2TS U3478 ( .A(add_subt_module_FS_Module_state_reg[2]), .B(n3126), .Y(
n4107) );
NOR2X2TS U3479 ( .A(add_subt_module_FS_Module_state_reg[2]), .B(
add_subt_module_FS_Module_state_reg[1]), .Y(n3317) );
AOI211X2TS U3480 ( .A0(add_subt_module_intDX[44]), .A1(n5127), .B0(n3479),
.C0(n3488), .Y(n3486) );
NOR4X2TS U3481 ( .A(n3389), .B(n3388), .C(n3387), .D(n3386), .Y(n4609) );
NOR2X2TS U3482 ( .A(cordic_FSM_state_reg[3]), .B(cordic_FSM_state_reg[2]),
.Y(n4653) );
OAI21X2TS U3483 ( .A0(n5053), .A1(n4562), .B0(n4395), .Y(n4409) );
OAI21X2TS U3484 ( .A0(n5055), .A1(n4562), .B0(n4453), .Y(n4466) );
OAI21X2TS U3485 ( .A0(n5161), .A1(n4562), .B0(n4375), .Y(n4392) );
OAI21X2TS U3486 ( .A0(n5218), .A1(n4583), .B0(n4531), .Y(n4553) );
OAI21X2TS U3487 ( .A0(n5215), .A1(n4583), .B0(n4505), .Y(n4522) );
CLKINVX3TS U3488 ( .A(n4025), .Y(n2973) );
CLKINVX3TS U3489 ( .A(n4025), .Y(n2974) );
CLKINVX3TS U3490 ( .A(n2966), .Y(n2975) );
CLKINVX3TS U3491 ( .A(n2966), .Y(n2976) );
AOI21X2TS U3492 ( .A0(n4569), .A1(n5217), .B0(n4555), .Y(n4575) );
OAI21X2TS U3493 ( .A0(n5078), .A1(n4562), .B0(n4370), .Y(n4385) );
OAI21X2TS U3494 ( .A0(n5220), .A1(n4583), .B0(n4499), .Y(n4515) );
OAI21X2TS U3495 ( .A0(n5219), .A1(n4562), .B0(n4460), .Y(n4475) );
OAI21X2TS U3496 ( .A0(n5222), .A1(n4562), .B0(n4389), .Y(n4405) );
OAI21X2TS U3497 ( .A0(n5216), .A1(n4562), .B0(n4480), .Y(n4495) );
BUFX4TS U3498 ( .A(n5343), .Y(n5327) );
CLKINVX6TS U3499 ( .A(n2956), .Y(n5030) );
BUFX6TS U3500 ( .A(n5039), .Y(n4948) );
INVX1TS U3501 ( .A(n4735), .Y(n4736) );
BUFX4TS U3502 ( .A(n5342), .Y(n5323) );
AOI211X4TS U3503 ( .A0(add_subt_module_sign_final_result), .A1(r_mode[1]),
.B0(n3315), .C0(n3314), .Y(n4621) );
OAI21X2TS U3504 ( .A0(n5054), .A1(n4562), .B0(n4561), .Y(n4586) );
BUFX4TS U3505 ( .A(n3788), .Y(n4033) );
BUFX4TS U3506 ( .A(n3101), .Y(n4813) );
CLKINVX6TS U3507 ( .A(n4337), .Y(n4578) );
CLKINVX6TS U3508 ( .A(n3535), .Y(n3839) );
CLKINVX6TS U3509 ( .A(n3535), .Y(n3883) );
CLKINVX6TS U3510 ( .A(n3535), .Y(n3828) );
INVX2TS U3511 ( .A(n3785), .Y(n2978) );
CLKINVX6TS U3512 ( .A(n2978), .Y(n2979) );
BUFX6TS U3513 ( .A(add_subt_module_FSM_selector_D), .Y(n4064) );
BUFX4TS U3514 ( .A(n3144), .Y(n5035) );
CLKINVX3TS U3515 ( .A(n4838), .Y(n4822) );
CLKINVX6TS U3516 ( .A(n4838), .Y(n4706) );
INVX4TS U3517 ( .A(n3757), .Y(n3884) );
OAI21X1TS U3518 ( .A0(n3570), .A1(n5226), .B0(n3128), .Y(n3571) );
AOI222X4TS U3519 ( .A0(n4450), .A1(n2959), .B0(n4458), .B1(n4589), .C0(n4461), .C1(n4585), .Y(n4469) );
AOI222X4TS U3520 ( .A0(n4454), .A1(n2959), .B0(n4461), .B1(n4550), .C0(n4466), .C1(n4585), .Y(n4474) );
BUFX4TS U3521 ( .A(n3007), .Y(n4772) );
NOR3X1TS U3522 ( .A(n5120), .B(n4607), .C(n4617), .Y(n3007) );
BUFX4TS U3523 ( .A(n5342), .Y(n5345) );
AOI222X1TS U3524 ( .A0(n4711), .A1(d_ff2_Z[56]), .B0(n3298), .B1(d_ff1_Z[56]), .C0(d_ff_Zn[56]), .C1(n4798), .Y(n3268) );
AOI222X1TS U3525 ( .A0(n3294), .A1(d_ff2_Z[57]), .B0(n3305), .B1(d_ff1_Z[57]), .C0(d_ff_Zn[57]), .C1(n3291), .Y(n3287) );
AOI222X1TS U3526 ( .A0(n3303), .A1(d_ff2_Z[51]), .B0(n3302), .B1(d_ff1_Z[51]), .C0(d_ff_Zn[51]), .C1(n4798), .Y(n3270) );
AOI222X1TS U3527 ( .A0(n4711), .A1(d_ff2_Z[0]), .B0(n3254), .B1(d_ff1_Z[0]),
.C0(d_ff_Zn[0]), .C1(n3291), .Y(n3241) );
AOI222X1TS U3528 ( .A0(n3303), .A1(d_ff2_Z[45]), .B0(n3302), .B1(d_ff1_Z[45]), .C0(d_ff_Zn[45]), .C1(n4798), .Y(n3280) );
AOI222X1TS U3529 ( .A0(n4711), .A1(d_ff2_Z[5]), .B0(n3254), .B1(d_ff1_Z[5]),
.C0(d_ff_Zn[5]), .C1(n3291), .Y(n3238) );
AOI222X1TS U3530 ( .A0(n4711), .A1(d_ff2_Z[12]), .B0(n3254), .B1(d_ff1_Z[12]), .C0(d_ff_Zn[12]), .C1(n3291), .Y(n3247) );
AOI222X1TS U3531 ( .A0(n3294), .A1(d_ff2_Z[19]), .B0(n3305), .B1(d_ff1_Z[19]), .C0(d_ff_Zn[19]), .C1(n3300), .Y(n3262) );
AOI222X1TS U3532 ( .A0(n3303), .A1(d_ff2_Z[23]), .B0(n3305), .B1(d_ff1_Z[23]), .C0(d_ff_Zn[23]), .C1(n4798), .Y(n3256) );
AOI222X1TS U3533 ( .A0(n3294), .A1(d_ff2_Z[34]), .B0(n3298), .B1(d_ff1_Z[34]), .C0(d_ff_Zn[34]), .C1(n4807), .Y(n3253) );
AOI222X1TS U3534 ( .A0(n3306), .A1(d_ff2_Z[36]), .B0(n3298), .B1(d_ff1_Z[36]), .C0(d_ff_Zn[36]), .C1(n4732), .Y(n3281) );
AOI222X1TS U3535 ( .A0(n3294), .A1(d_ff2_Z[15]), .B0(n3305), .B1(d_ff1_Z[15]), .C0(d_ff_Zn[15]), .C1(n3300), .Y(n3295) );
AOI222X1TS U3536 ( .A0(n3303), .A1(d_ff2_Z[29]), .B0(n3298), .B1(d_ff1_Z[29]), .C0(d_ff_Zn[29]), .C1(n4807), .Y(n3299) );
AOI222X1TS U3537 ( .A0(n3294), .A1(d_ff2_Z[31]), .B0(n3298), .B1(d_ff1_Z[31]), .C0(d_ff_Zn[31]), .C1(n4807), .Y(n3273) );
AOI21X2TS U3538 ( .A0(n5049), .A1(n3108), .B0(n4658), .Y(n4679) );
BUFX4TS U3539 ( .A(n3915), .Y(n3003) );
AOI21X2TS U3540 ( .A0(n3634), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[106]), .B0(
n3633), .Y(n3804) );
CLKINVX6TS U3541 ( .A(n3003), .Y(n5377) );
BUFX4TS U3542 ( .A(n5343), .Y(n5335) );
BUFX4TS U3543 ( .A(n5343), .Y(n5336) );
BUFX4TS U3544 ( .A(n5339), .Y(n5332) );
BUFX4TS U3545 ( .A(n5350), .Y(n5317) );
BUFX4TS U3546 ( .A(n5319), .Y(n5351) );
BUFX4TS U3547 ( .A(n5345), .Y(n5334) );
BUFX4TS U3548 ( .A(n5350), .Y(n5315) );
BUFX4TS U3549 ( .A(n5350), .Y(n5333) );
BUFX4TS U3550 ( .A(n5350), .Y(n5316) );
BUFX4TS U3551 ( .A(n5334), .Y(n5347) );
BUFX3TS U3552 ( .A(n5351), .Y(n5344) );
NOR2X2TS U3553 ( .A(n4667), .B(n4817), .Y(n4677) );
BUFX4TS U3554 ( .A(n5345), .Y(n5322) );
BUFX4TS U3555 ( .A(n5344), .Y(n5325) );
AOI22X2TS U3556 ( .A0(cont_iter_out[1]), .A1(n3228), .B0(cont_iter_out[0]),
.B1(n5049), .Y(n4690) );
BUFX4TS U3557 ( .A(n5345), .Y(n5324) );
BUFX4TS U3558 ( .A(n5343), .Y(n5326) );
AOI21X2TS U3559 ( .A0(n4569), .A1(n5230), .B0(n4568), .Y(n4590) );
BUFX4TS U3560 ( .A(n5342), .Y(n5329) );
BUFX4TS U3561 ( .A(n5347), .Y(n5330) );
NOR2X2TS U3562 ( .A(n3637), .B(n3580), .Y(n3684) );
BUFX4TS U3563 ( .A(n5342), .Y(n5328) );
NOR3X4TS U3564 ( .A(n5114), .B(n5050), .C(
add_subt_module_FS_Module_state_reg[3]), .Y(n4211) );
NOR3X2TS U3565 ( .A(n4667), .B(n4693), .C(n4661), .Y(n4675) );
AOI21X2TS U3566 ( .A0(n3126), .A1(n4622), .B0(n3807), .Y(n4611) );
BUFX6TS U3567 ( .A(n3912), .Y(n4622) );
NOR3XLTS U3568 ( .A(n4479), .B(add_subt_module_FS_Module_state_reg[3]), .C(
add_subt_module_add_overflow_flag), .Y(n3122) );
AOI211X4TS U3569 ( .A0(n3534), .A1(n3533), .B0(n3532), .C0(n3531), .Y(n4027)
);
BUFX6TS U3570 ( .A(n3912), .Y(n4479) );
BUFX6TS U3571 ( .A(n5039), .Y(n4970) );
BUFX6TS U3572 ( .A(n5039), .Y(n5001) );
BUFX6TS U3573 ( .A(n3675), .Y(n3787) );
AOI31X2TS U3574 ( .A0(n5118), .A1(n5049), .A2(n5056), .B0(n4817), .Y(n4664)
);
BUFX6TS U3575 ( .A(n3046), .Y(n5036) );
BUFX6TS U3576 ( .A(n3046), .Y(n5011) );
BUFX6TS U3577 ( .A(n3046), .Y(n5040) );
AOI211XLTS U3578 ( .A0(add_subt_module_FS_Module_state_reg[3]), .A1(n5114),
.B0(n4626), .C0(n3114), .Y(n4630) );
AOI21X2TS U3579 ( .A0(n4569), .A1(n5082), .B0(n4347), .Y(n4362) );
CLKINVX6TS U3580 ( .A(n4337), .Y(n4569) );
AOI21X2TS U3581 ( .A0(n4569), .A1(n5222), .B0(n4490), .Y(n4506) );
AOI21X2TS U3582 ( .A0(n4569), .A1(n5200), .B0(n4525), .Y(n4545) );
BUFX6TS U3583 ( .A(n3144), .Y(n4971) );
NAND2X2TS U3584 ( .A(cont_iter_out[2]), .B(cont_iter_out[1]), .Y(n4637) );
NOR4X4TS U3585 ( .A(cont_iter_out[0]), .B(cont_iter_out[1]), .C(
cont_iter_out[3]), .D(n5118), .Y(n4667) );
OAI22X2TS U3586 ( .A0(cont_iter_out[2]), .A1(cont_iter_out[1]), .B0(n3108),
.B1(n4637), .Y(n4680) );
NAND2X1TS U3587 ( .A(cont_var_out[1]), .B(n4654), .Y(n4744) );
AOI22X2TS U3588 ( .A0(n4632), .A1(n4737), .B0(cont_var_out[0]), .B1(n4654),
.Y(n4741) );
NAND3X2TS U3589 ( .A(cont_iter_out[1]), .B(cont_iter_out[0]), .C(n4697), .Y(
n4654) );
NOR2XLTS U3590 ( .A(n5096), .B(n4087), .Y(n4084) );
NOR2XLTS U3591 ( .A(n5095), .B(n4087), .Y(n4083) );
NOR2XLTS U3592 ( .A(n5100), .B(n4087), .Y(n4082) );
NOR2XLTS U3593 ( .A(n5099), .B(n4087), .Y(n4081) );
BUFX4TS U3594 ( .A(add_subt_module_FSM_selector_D), .Y(n4087) );
CLKINVX6TS U3595 ( .A(n4818), .Y(n4829) );
CLKINVX6TS U3596 ( .A(n4742), .Y(n4791) );
NOR2X4TS U3597 ( .A(n3580), .B(n3634), .Y(n3633) );
AOI22X4TS U3598 ( .A0(add_subt_module_LZA_output[3]), .A1(n3124), .B0(n2953),
.B1(add_subt_module_exp_oper_result[3]), .Y(n3133) );
OAI21X2TS U3599 ( .A0(n5055), .A1(n4337), .B0(n4425), .Y(n4440) );
BUFX4TS U3600 ( .A(n4788), .Y(n4768) );
BUFX4TS U3601 ( .A(n4788), .Y(n4776) );
BUFX4TS U3602 ( .A(n4788), .Y(n4794) );
OAI21X2TS U3603 ( .A0(n5221), .A1(n4562), .B0(n3538), .Y(n4335) );
AOI222X1TS U3604 ( .A0(n2959), .A1(n3643), .B0(n4589), .B1(n3642), .C0(n4335), .C1(n4585), .Y(n4342) );
OAI21X2TS U3605 ( .A0(n5101), .A1(n4562), .B0(n4465), .Y(n4481) );
OAI21X2TS U3606 ( .A0(n5200), .A1(n4562), .B0(n4357), .Y(n4371) );
AOI222X4TS U3607 ( .A0(n4450), .A1(n2980), .B0(n4440), .B1(n4587), .C0(n4445), .C1(n4591), .Y(n4459) );
AOI222X4TS U3608 ( .A0(n4454), .A1(n2980), .B0(n4591), .B1(n4446), .C0(n4445), .C1(n4587), .Y(n4464) );
OAI21X2TS U3609 ( .A0(n5110), .A1(n4562), .B0(n4430), .Y(n4445) );
BUFX6TS U3610 ( .A(n4211), .Y(n4316) );
BUFX6TS U3611 ( .A(n4211), .Y(n4330) );
BUFX6TS U3612 ( .A(n4211), .Y(n4325) );
BUFX6TS U3613 ( .A(n3206), .Y(n3225) );
BUFX4TS U3614 ( .A(n3206), .Y(n3173) );
BUFX4TS U3615 ( .A(n3206), .Y(n3203) );
INVX2TS U3616 ( .A(n2959), .Y(n2980) );
BUFX6TS U3617 ( .A(n2993), .Y(n3004) );
CLKINVX3TS U3618 ( .A(n4800), .Y(n4799) );
CLKINVX6TS U3619 ( .A(n4800), .Y(n4809) );
CLKINVX6TS U3620 ( .A(n4800), .Y(n4842) );
INVX4TS U3621 ( .A(n4812), .Y(n3285) );
BUFX4TS U3622 ( .A(n4574), .Y(n4589) );
NOR2X4TS U3623 ( .A(n5118), .B(n5056), .Y(n4697) );
NAND2X2TS U3624 ( .A(n4706), .B(n5056), .Y(n4659) );
NAND2X2TS U3625 ( .A(cont_iter_out[0]), .B(n5056), .Y(n3108) );
INVX4TS U3626 ( .A(n4710), .Y(n3291) );
CLKINVX3TS U3627 ( .A(n2965), .Y(n2981) );
CLKINVX3TS U3628 ( .A(n2965), .Y(n2982) );
NOR2X4TS U3629 ( .A(n3133), .B(n3128), .Y(n3683) );
BUFX4TS U3630 ( .A(n4559), .Y(n4579) );
BUFX4TS U3631 ( .A(n4559), .Y(n4585) );
CLKINVX6TS U3632 ( .A(n3535), .Y(n3868) );
CLKINVX6TS U3633 ( .A(n3757), .Y(n3865) );
INVX4TS U3634 ( .A(n3757), .Y(n3838) );
CLKINVX6TS U3635 ( .A(n3820), .Y(n3889) );
CLKINVX6TS U3636 ( .A(n4577), .Y(n4583) );
AOI21X2TS U3637 ( .A0(n4577), .A1(n5206), .B0(n4549), .Y(n4570) );
OAI2BB1X1TS U3638 ( .A0N(add_subt_module_Add_Subt_result[34]), .A1N(n4577),
.B0(n4470), .Y(n4485) );
BUFX4TS U3639 ( .A(n4537), .Y(n4577) );
INVX4TS U3640 ( .A(n4728), .Y(n4732) );
OAI21X2TS U3641 ( .A0(n5218), .A1(n4337), .B0(n4352), .Y(n4366) );
OAI21X2TS U3642 ( .A0(n5206), .A1(n4337), .B0(n4338), .Y(n4355) );
OAI21X2TS U3643 ( .A0(n5052), .A1(n4337), .B0(n4519), .Y(n4539) );
OAI21X2TS U3644 ( .A0(n5223), .A1(n4337), .B0(n4544), .Y(n4563) );
OAI21X2TS U3645 ( .A0(n5110), .A1(n4337), .B0(n4449), .Y(n4461) );
INVX3TS U3646 ( .A(n4451), .Y(n4513) );
CLKINVX3TS U3647 ( .A(n3535), .Y(n3888) );
INVX3TS U3648 ( .A(n4780), .Y(n4767) );
INVX3TS U3649 ( .A(n4845), .Y(n4851) );
AOI21X2TS U3650 ( .A0(n3129), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[107]), .B0(
n3545), .Y(n3587) );
AOI21X2TS U3651 ( .A0(n3634), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[107]), .B0(
n3633), .Y(n3925) );
AOI21X2TS U3652 ( .A0(n3129), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[102]), .B0(
n3550), .Y(n3593) );
AOI211X2TS U3653 ( .A0(n3634), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[91]), .B0(
n3683), .C0(n3620), .Y(n3783) );
AOI211X2TS U3654 ( .A0(n3634), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[93]), .B0(
n3683), .C0(n3627), .Y(n3778) );
AOI21X2TS U3655 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[109]), .A1(
n3129), .B0(n3571), .Y(n3611) );
INVX2TS U3656 ( .A(n2957), .Y(n2984) );
AOI211X1TS U3657 ( .A0(n3972), .A1(add_subt_module_Add_Subt_result[27]),
.B0(n3971), .C0(n3970), .Y(n3974) );
AOI211X1TS U3658 ( .A0(add_subt_module_Add_Subt_result[44]), .A1(n4008),
.B0(add_subt_module_Add_Subt_result[47]), .C0(
add_subt_module_Add_Subt_result[48]), .Y(n4010) );
NOR4X2TS U3659 ( .A(add_subt_module_Add_Subt_result[46]), .B(
add_subt_module_Add_Subt_result[44]), .C(
add_subt_module_Add_Subt_result[45]), .D(n3998), .Y(n4011) );
NOR3XLTS U3660 ( .A(add_subt_module_Add_Subt_result[44]), .B(
add_subt_module_Add_Subt_result[46]), .C(
add_subt_module_Add_Subt_result[45]), .Y(n3999) );
AOI221X1TS U3661 ( .A0(n5194), .A1(add_subt_module_intDY[29]), .B0(
add_subt_module_intDX[0]), .B1(n5201), .C0(n3344), .Y(n3347) );
AOI211X1TS U3662 ( .A0(n3900), .A1(n3988), .B0(
add_subt_module_Add_Subt_result[8]), .C0(
add_subt_module_Add_Subt_result[7]), .Y(n3905) );
OAI211XLTS U3663 ( .A0(n3992), .A1(add_subt_module_Add_Subt_result[7]), .B0(
n3991), .C0(n4005), .Y(n3993) );
AOI221X1TS U3664 ( .A0(n5192), .A1(add_subt_module_intDY[25]), .B0(
add_subt_module_intDY[2]), .B1(n5189), .C0(n3345), .Y(n3346) );
OAI221XLTS U3665 ( .A0(n5069), .A1(add_subt_module_intDY[31]), .B0(n5150),
.B1(add_subt_module_intDX[56]), .C0(n3351), .Y(n3356) );
OAI221XLTS U3666 ( .A0(n5066), .A1(n2985), .B0(n5152), .B1(
add_subt_module_intDY[40]), .C0(n3367), .Y(n3372) );
OAI221XLTS U3667 ( .A0(n5173), .A1(n2986), .B0(n5178), .B1(
add_subt_module_intDY[14]), .C0(n3318), .Y(n3319) );
INVX2TS U3668 ( .A(n2963), .Y(n2985) );
INVX2TS U3669 ( .A(n2962), .Y(n2986) );
OAI221X1TS U3670 ( .A0(n5064), .A1(add_subt_module_intDY[42]), .B0(n5154),
.B1(add_subt_module_intDY[9]), .C0(n3374), .Y(n3381) );
OAI221X1TS U3671 ( .A0(n5171), .A1(add_subt_module_intDY[33]), .B0(n5142),
.B1(add_subt_module_intDX[62]), .C0(n3376), .Y(n3379) );
AOI221X1TS U3672 ( .A0(n5191), .A1(add_subt_module_intDY[35]), .B0(
add_subt_module_intDY[8]), .B1(n5187), .C0(n3343), .Y(n3348) );
OAI221XLTS U3673 ( .A0(n5144), .A1(add_subt_module_intDY[39]), .B0(n5177),
.B1(add_subt_module_intDY[23]), .C0(n3323), .Y(n3328) );
INVX2TS U3674 ( .A(n2964), .Y(n2987) );
AOI211X1TS U3675 ( .A0(add_subt_module_intDX[52]), .A1(n5163), .B0(n3392),
.C0(n3511), .Y(n3513) );
OAI221X1TS U3676 ( .A0(n5172), .A1(add_subt_module_intDY[11]), .B0(n5163),
.B1(add_subt_module_intDX[52]), .C0(n3324), .Y(n3327) );
OAI211X2TS U3677 ( .A0(add_subt_module_intDY[28]), .A1(n5164), .B0(n3409),
.C0(n3400), .Y(n3459) );
OAI221XLTS U3678 ( .A0(n5158), .A1(add_subt_module_intDY[49]), .B0(n5164),
.B1(add_subt_module_intDY[28]), .C0(n3359), .Y(n3364) );
OAI211X2TS U3679 ( .A0(add_subt_module_intDY[12]), .A1(n5196), .B0(n3437),
.C0(n3411), .Y(n3441) );
AOI221X1TS U3680 ( .A0(n5196), .A1(add_subt_module_intDY[12]), .B0(
add_subt_module_intDY[18]), .B1(n5186), .C0(n3337), .Y(n3338) );
OAI211X2TS U3681 ( .A0(add_subt_module_intDY[20]), .A1(n5165), .B0(n3456),
.C0(n3410), .Y(n3450) );
OAI221XLTS U3682 ( .A0(n5165), .A1(add_subt_module_intDY[20]), .B0(n5070),
.B1(add_subt_module_intDY[50]), .C0(n3353), .Y(n3354) );
OAI221XLTS U3683 ( .A0(n5062), .A1(add_subt_module_intDY[15]), .B0(n5176),
.B1(add_subt_module_intDY[17]), .C0(n3377), .Y(n3378) );
OAI221XLTS U3684 ( .A0(n5162), .A1(add_subt_module_intDY[21]), .B0(n5151),
.B1(add_subt_module_intDY[46]), .C0(n3369), .Y(n3370) );
INVX2TS U3685 ( .A(n2961), .Y(n2988) );
OAI221X1TS U3686 ( .A0(n5148), .A1(add_subt_module_intDX[55]), .B0(n5065),
.B1(add_subt_module_intDY[34]), .C0(n3366), .Y(n3373) );
AOI211X1TS U3687 ( .A0(n4653), .A1(n3921), .B0(n4735), .C0(n3111), .Y(n3112)
);
AOI222X4TS U3688 ( .A0(n3883), .A1(add_subt_module_DMP[0]), .B0(
add_subt_module_intDX[0]), .B1(n3746), .C0(n3889), .C1(
add_subt_module_intDY[0]), .Y(n3664) );
AOI222X4TS U3689 ( .A0(n2974), .A1(add_subt_module_intDY[63]), .B0(
d_ff3_sh_y_out[63]), .B1(n5039), .C0(d_ff3_sh_x_out[63]), .C1(n4954),
.Y(n3145) );
XOR2X1TS U3690 ( .A(add_subt_module_intAS), .B(add_subt_module_intDY[63]),
.Y(n4029) );
NOR4X2TS U3691 ( .A(n3393), .B(n3465), .C(n3477), .D(n3469), .Y(n3522) );
NOR3X2TS U3692 ( .A(add_subt_module_Add_Subt_result[8]), .B(
add_subt_module_Add_Subt_result[7]), .C(n3904), .Y(n3949) );
AOI32X1TS U3693 ( .A0(n4671), .A1(n4729), .A2(n4670), .B0(n5307), .B1(n4818),
.Y(n2818) );
AOI31X2TS U3694 ( .A0(n4669), .A1(n3108), .A2(n3104), .B0(n3110), .Y(n4671)
);
NOR2X6TS U3695 ( .A(n3009), .B(sel_mux_2_reg[1]), .Y(n5039) );
NOR2X4TS U3696 ( .A(n5050), .B(add_subt_module_FS_Module_state_reg[1]), .Y(
n4623) );
BUFX4TS U3697 ( .A(n5337), .Y(n5320) );
BUFX4TS U3698 ( .A(n5345), .Y(n5319) );
BUFX4TS U3699 ( .A(n3826), .Y(n3820) );
BUFX4TS U3700 ( .A(n3757), .Y(n3818) );
AOI21X2TS U3701 ( .A0(n3129), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[106]), .B0(
n3554), .Y(n3596) );
AOI21X2TS U3702 ( .A0(n3129), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[104]), .B0(
n3561), .Y(n3599) );
OAI32X1TS U3703 ( .A0(n3919), .A1(n2993), .A2(n5240), .B0(n4741), .B1(n3918),
.Y(n2852) );
NOR3X2TS U3704 ( .A(cordic_FSM_state_reg[0]), .B(n5057), .C(n3914), .Y(n3919) );
BUFX6TS U3705 ( .A(n4053), .Y(n4101) );
OAI21X2TS U3706 ( .A0(n5217), .A1(n4562), .B0(n4332), .Y(n4350) );
CLKAND2X4TS U3707 ( .A(n4624), .B(n3317), .Y(n4025) );
NOR2X2TS U3708 ( .A(n5120), .B(add_subt_module_FS_Module_state_reg[3]), .Y(
n4624) );
AOI211X2TS U3709 ( .A0(cont_iter_out[0]), .A1(cont_iter_out[1]), .B0(n4660),
.C0(n4659), .Y(n4685) );
NOR3X4TS U3710 ( .A(cont_iter_out[2]), .B(cont_iter_out[1]), .C(
cont_iter_out[0]), .Y(n4660) );
BUFX4TS U3711 ( .A(n3199), .Y(n3202) );
CLKINVX6TS U3712 ( .A(n3004), .Y(n5378) );
CLKBUFX2TS U3713 ( .A(n3582), .Y(n2989) );
BUFX3TS U3714 ( .A(n3151), .Y(n3206) );
INVX4TS U3715 ( .A(n4713), .Y(n3300) );
CLKINVX6TS U3716 ( .A(n4487), .Y(n4591) );
CLKINVX6TS U3717 ( .A(n2956), .Y(n5034) );
AOI22X2TS U3718 ( .A0(add_subt_module_LZA_output[4]), .A1(n3124), .B0(n2953),
.B1(add_subt_module_exp_oper_result[4]), .Y(n3132) );
AOI21X2TS U3719 ( .A0(n3129), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[108]), .B0(
n3562), .Y(n3584) );
AOI21X2TS U3720 ( .A0(n3129), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[105]), .B0(
n3546), .Y(n3602) );
NOR2X2TS U3721 ( .A(d_ff2_Y[59]), .B(n4827), .Y(n4831) );
CLKINVX6TS U3722 ( .A(n4644), .Y(n4647) );
NOR2X2TS U3723 ( .A(d_ff2_X[59]), .B(n4720), .Y(n4719) );
NOR3X2TS U3724 ( .A(d_ff2_X[57]), .B(d_ff2_X[56]), .C(intadd_373_n1), .Y(
n4716) );
AOI21X2TS U3725 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[103]), .A1(
n3129), .B0(n3569), .Y(n3607) );
AOI211X2TS U3726 ( .A0(n3634), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[90]), .B0(
n3683), .C0(n3632), .Y(n3774) );
AOI211X2TS U3727 ( .A0(n3634), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[88]), .B0(
n3683), .C0(n3130), .Y(n3650) );
AOI211X2TS U3728 ( .A0(n3634), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[89]), .B0(
n3683), .C0(n3616), .Y(n3791) );
BUFX6TS U3729 ( .A(add_subt_module_FSM_selector_D), .Y(n4086) );
INVX3TS U3730 ( .A(n4451), .Y(n4592) );
INVX3TS U3731 ( .A(n4803), .Y(n4806) );
INVX3TS U3732 ( .A(n4845), .Y(n4853) );
INVX3TS U3733 ( .A(n4783), .Y(n4773) );
NOR3X2TS U3734 ( .A(d_ff2_Y[57]), .B(d_ff2_Y[56]), .C(intadd_372_n1), .Y(
n4824) );
AOI21X2TS U3735 ( .A0(add_subt_module_Add_Subt_result[52]), .A1(n4578), .B0(
n3539), .Y(n4340) );
NOR2X2TS U3736 ( .A(add_subt_module_Add_Subt_result[6]), .B(
add_subt_module_Add_Subt_result[5]), .Y(n3900) );
NOR4X4TS U3737 ( .A(add_subt_module_Add_Subt_result[36]), .B(
add_subt_module_Add_Subt_result[34]), .C(
add_subt_module_Add_Subt_result[35]), .D(n3956), .Y(n3977) );
OAI211XLTS U3738 ( .A0(add_subt_module_Add_Subt_result[23]), .A1(n3996),
.B0(n3961), .C0(n4015), .Y(n3962) );
OAI221X1TS U3739 ( .A0(n5061), .A1(add_subt_module_intDY[47]), .B0(n5156),
.B1(add_subt_module_intDY[10]), .C0(n3358), .Y(n3365) );
AOI32X1TS U3740 ( .A0(n5175), .A1(n3402), .A2(add_subt_module_intDY[26]),
.B0(add_subt_module_intDY[27]), .B1(n5071), .Y(n3403) );
OAI221XLTS U3741 ( .A0(n5149), .A1(add_subt_module_intDY[7]), .B0(n5071),
.B1(add_subt_module_intDY[27]), .C0(n3375), .Y(n3380) );
AOI32X1TS U3742 ( .A0(n5186), .A1(n3447), .A2(add_subt_module_intDY[18]),
.B0(add_subt_module_intDY[19]), .B1(n5072), .Y(n3448) );
OAI221X1TS U3743 ( .A0(n5072), .A1(add_subt_module_intDY[19]), .B0(n5155),
.B1(add_subt_module_intDY[5]), .C0(n3352), .Y(n3355) );
NAND2X4TS U3744 ( .A(n3127), .B(add_subt_module_add_overflow_flag), .Y(
add_subt_module_FSM_exp_operation_A_S) );
OAI221X1TS U3745 ( .A0(n5147), .A1(add_subt_module_intDY[1]), .B0(n5169),
.B1(add_subt_module_intDX[61]), .C0(n3322), .Y(n3329) );
OAI221X1TS U3746 ( .A0(n5170), .A1(add_subt_module_intDY[36]), .B0(n5141),
.B1(add_subt_module_intDX[58]), .C0(n3360), .Y(n3363) );
OAI221XLTS U3747 ( .A0(n5143), .A1(add_subt_module_intDY[44]), .B0(n5175),
.B1(add_subt_module_intDY[26]), .C0(n3361), .Y(n3362) );
AOI221X1TS U3748 ( .A0(n5190), .A1(add_subt_module_intDY[45]), .B0(
add_subt_module_intDY[51]), .B1(n5199), .C0(n3335), .Y(n3340) );
OAI211XLTS U3749 ( .A0(add_subt_module_Add_Subt_result[29]), .A1(n4015),
.B0(n4014), .C0(n4013), .Y(n4016) );
OAI221X1TS U3750 ( .A0(n5145), .A1(add_subt_module_intDY[6]), .B0(n5157),
.B1(add_subt_module_intDY[41]), .C0(n3368), .Y(n3371) );
OAI221X1TS U3751 ( .A0(n5146), .A1(add_subt_module_intDY[16]), .B0(n5174),
.B1(add_subt_module_intDY[43]), .C0(n3350), .Y(n3357) );
OR2X1TS U3752 ( .A(add_subt_module_FSM_selector_D), .B(
add_subt_module_Sgf_normalized_result[2]), .Y(n2990) );
INVX2TS U3753 ( .A(n3906), .Y(n3126) );
OR3X2TS U3754 ( .A(n3133), .B(n3135), .C(n3131), .Y(n2991) );
AND3X4TS U3755 ( .A(n4653), .B(n5057), .C(n5124), .Y(n2993) );
OAI21XLTS U3756 ( .A0(add_subt_module_intDX[1]), .A1(n5119), .B0(
add_subt_module_intDX[0]), .Y(n3414) );
OAI21XLTS U3757 ( .A0(add_subt_module_intDY[35]), .A1(n5191), .B0(
add_subt_module_intDY[34]), .Y(n3497) );
NOR2XLTS U3758 ( .A(n3514), .B(add_subt_module_intDX[48]), .Y(n3515) );
OAI21XLTS U3759 ( .A0(add_subt_module_intDY[55]), .A1(n5058), .B0(
add_subt_module_intDY[54]), .Y(n3521) );
NOR2XLTS U3760 ( .A(n3465), .B(add_subt_module_intDX[56]), .Y(n3466) );
NOR2XLTS U3761 ( .A(n3512), .B(n3511), .Y(n3525) );
OAI21XLTS U3762 ( .A0(n3489), .A1(n3488), .B0(n3487), .Y(n3491) );
NOR2XLTS U3763 ( .A(n5091), .B(add_subt_module_FSM_selector_D), .Y(n4085) );
NOR2XLTS U3764 ( .A(n5104), .B(n4087), .Y(n4074) );
NOR2XLTS U3765 ( .A(n5092), .B(n4087), .Y(n4088) );
NOR2XLTS U3766 ( .A(n5109), .B(n4087), .Y(n4073) );
NOR2XLTS U3767 ( .A(n5097), .B(n4087), .Y(n4079) );
NOR2XLTS U3768 ( .A(n5106), .B(n4087), .Y(n4076) );
NOR2XLTS U3769 ( .A(n4431), .B(n4487), .Y(n4428) );
OAI21XLTS U3770 ( .A0(n4397), .A1(n4533), .B0(n4396), .Y(n4398) );
NOR2XLTS U3771 ( .A(n4487), .B(n4436), .Y(n4433) );
OAI21XLTS U3772 ( .A0(n4377), .A1(n4487), .B0(n4372), .Y(n4373) );
OAI21XLTS U3773 ( .A0(n4533), .A1(n4511), .B0(n4510), .Y(n4512) );
OAI21XLTS U3774 ( .A0(n4557), .A1(n4487), .B0(n4551), .Y(n4552) );
OAI21XLTS U3775 ( .A0(n4616), .A1(n4613), .B0(
add_subt_module_FS_Module_state_reg[3]), .Y(n3391) );
NOR3XLTS U3776 ( .A(cont_iter_out[3]), .B(n4667), .C(n4818), .Y(n4668) );
OAI211XLTS U3777 ( .A0(n3602), .A1(n2982), .B0(n3601), .C0(n2989), .Y(n2577)
);
OAI211XLTS U3778 ( .A0(n4025), .A1(n5067), .B0(n3098), .C0(n3097), .Y(n1952)
);
OAI21XLTS U3779 ( .A0(n3602), .A1(n2975), .B0(n3578), .Y(n2547) );
OAI21XLTS U3780 ( .A0(n3692), .A1(n3924), .B0(n3674), .Y(n2563) );
OAI211XLTS U3781 ( .A0(n3783), .A1(n2981), .B0(n3658), .C0(n3582), .Y(n2571)
);
OAI211XLTS U3782 ( .A0(n3778), .A1(n2981), .B0(n3654), .C0(n3582), .Y(n2573)
);
OAI211XLTS U3783 ( .A0(n4025), .A1(n5169), .B0(n3092), .C0(n3097), .Y(n1956)
);
OAI211XLTS U3784 ( .A0(n3584), .A1(n2981), .B0(n3583), .C0(n3582), .Y(n2580)
);
OAI211XLTS U3785 ( .A0(n4025), .A1(n5235), .B0(n3091), .C0(n3097), .Y(n1900)
);
OAI21XLTS U3786 ( .A0(n5154), .A1(n3891), .B0(n3875), .Y(n1711) );
OAI21XLTS U3787 ( .A0(n5062), .A1(n3727), .B0(n3724), .Y(n1725) );
OAI21XLTS U3788 ( .A0(n5066), .A1(n3818), .B0(n3755), .Y(n1740) );
OAI21XLTS U3789 ( .A0(n5186), .A1(n3818), .B0(n3704), .Y(n1761) );
OAI21XLTS U3790 ( .A0(n5071), .A1(n3820), .B0(n3732), .Y(n1776) );
OAI21XLTS U3791 ( .A0(n5177), .A1(n3826), .B0(n3764), .Y(n1796) );
OAI21XLTS U3792 ( .A0(n5187), .A1(n3826), .B0(n3760), .Y(n1817) );
OAI21XLTS U3793 ( .A0(n5152), .A1(n3820), .B0(n3753), .Y(n1835) );
OAI21XLTS U3794 ( .A0(n5155), .A1(n3826), .B0(n3709), .Y(n1858) );
OAI21XLTS U3795 ( .A0(n5158), .A1(n3867), .B0(n3830), .Y(n1878) );
OAI21XLTS U3796 ( .A0(n5235), .A1(n3867), .B0(n3829), .Y(n1899) );
OAI21XLTS U3797 ( .A0(n5148), .A1(n3870), .B0(n3857), .Y(n1920) );
OAI21XLTS U3798 ( .A0(n5288), .A1(n3153), .B0(n3217), .Y(n2007) );
OAI21XLTS U3799 ( .A0(n5295), .A1(n3223), .B0(n3212), .Y(n1993) );
OAI21XLTS U3800 ( .A0(n5302), .A1(n3223), .B0(n3167), .Y(n1977) );
NOR2XLTS U3801 ( .A(n4603), .B(n4599), .Y(ready_cordic) );
NOR2X2TS U3802 ( .A(add_subt_module_FS_Module_state_reg[0]), .B(
add_subt_module_FS_Module_state_reg[3]), .Y(n4612) );
NAND2X1TS U3803 ( .A(n4623), .B(n4612), .Y(n3113) );
INVX2TS U3804 ( .A(n3113), .Y(n2994) );
NAND2X1TS U3805 ( .A(n2994), .B(add_subt_module_FSM_selector_C), .Y(n2997)
);
NOR2X2TS U3806 ( .A(n5114), .B(add_subt_module_FS_Module_state_reg[2]), .Y(
n4616) );
NAND2X1TS U3807 ( .A(add_subt_module_FS_Module_state_reg[0]), .B(n4616), .Y(
n4619) );
INVX2TS U3808 ( .A(n4619), .Y(n2995) );
NAND2X1TS U3809 ( .A(add_subt_module_FS_Module_state_reg[3]), .B(n2995), .Y(
n2996) );
XOR2X1TS U3810 ( .A(DP_OP_92J137_122_9081_n1), .B(
add_subt_module_FSM_exp_operation_A_S), .Y(n3117) );
INVX2TS U3811 ( .A(n3127), .Y(n2998) );
OR4X2TS U3812 ( .A(add_subt_module_Exp_Operation_Module_Data_S[2]), .B(
add_subt_module_Exp_Operation_Module_Data_S[1]), .C(
add_subt_module_Exp_Operation_Module_Data_S[0]), .D(n2998), .Y(n2999)
);
OR4X2TS U3813 ( .A(add_subt_module_Exp_Operation_Module_Data_S[5]), .B(
add_subt_module_Exp_Operation_Module_Data_S[4]), .C(
add_subt_module_Exp_Operation_Module_Data_S[3]), .D(n2999), .Y(n3000)
);
OR4X2TS U3814 ( .A(add_subt_module_Exp_Operation_Module_Data_S[8]), .B(
add_subt_module_Exp_Operation_Module_Data_S[7]), .C(
add_subt_module_Exp_Operation_Module_Data_S[6]), .D(n3000), .Y(n3001)
);
OR4X2TS U3815 ( .A(n3117), .B(
add_subt_module_Exp_Operation_Module_Data_S[10]), .C(
add_subt_module_Exp_Operation_Module_Data_S[9]), .D(n3001), .Y(n3002)
);
OAI21XLTS U3816 ( .A0(n3127), .A1(n5237), .B0(n3002), .Y(n2934) );
NAND2X1TS U3817 ( .A(cordic_FSM_state_reg[2]), .B(n5057), .Y(n4603) );
NAND2X1TS U3818 ( .A(cordic_FSM_state_reg[3]), .B(cordic_FSM_state_reg[0]),
.Y(n4599) );
INVX2TS U3819 ( .A(rst), .Y(n5404) );
BUFX3TS U3820 ( .A(n5343), .Y(n5346) );
BUFX3TS U3821 ( .A(n5335), .Y(n5342) );
BUFX3TS U3822 ( .A(n5340), .Y(n5349) );
INVX4TS U3823 ( .A(n3004), .Y(n5394) );
INVX4TS U3824 ( .A(n3004), .Y(n5396) );
INVX4TS U3825 ( .A(n3915), .Y(n5397) );
INVX4TS U3826 ( .A(n3004), .Y(n5374) );
INVX4TS U3827 ( .A(n3003), .Y(n5380) );
INVX4TS U3828 ( .A(n3004), .Y(n5376) );
INVX4TS U3829 ( .A(n3004), .Y(n5381) );
INVX4TS U3830 ( .A(n3004), .Y(n5384) );
INVX4TS U3831 ( .A(n3004), .Y(n5383) );
INVX4TS U3832 ( .A(n3004), .Y(n5382) );
INVX4TS U3833 ( .A(n3003), .Y(n5357) );
INVX4TS U3834 ( .A(n3004), .Y(n5358) );
INVX4TS U3835 ( .A(n3004), .Y(n5379) );
BUFX3TS U3836 ( .A(n2993), .Y(n3915) );
INVX4TS U3837 ( .A(n3915), .Y(n5354) );
INVX4TS U3838 ( .A(n3003), .Y(n5353) );
INVX4TS U3839 ( .A(n3003), .Y(n5385) );
INVX4TS U3840 ( .A(n3003), .Y(n5390) );
INVX4TS U3841 ( .A(n3003), .Y(n5389) );
INVX4TS U3842 ( .A(n3004), .Y(n5356) );
INVX4TS U3843 ( .A(n3004), .Y(n5375) );
INVX4TS U3844 ( .A(n3003), .Y(n5386) );
INVX4TS U3845 ( .A(n3003), .Y(n5392) );
INVX4TS U3846 ( .A(n3003), .Y(n5393) );
INVX4TS U3847 ( .A(n3003), .Y(n5391) );
INVX4TS U3848 ( .A(n3003), .Y(n5387) );
INVX4TS U3849 ( .A(n3004), .Y(n5370) );
INVX4TS U3850 ( .A(n3004), .Y(n5371) );
INVX4TS U3851 ( .A(n3004), .Y(n5372) );
INVX4TS U3852 ( .A(n3915), .Y(n5355) );
INVX4TS U3853 ( .A(n3004), .Y(n5360) );
INVX4TS U3854 ( .A(n3004), .Y(n5359) );
INVX4TS U3855 ( .A(n2993), .Y(n5363) );
INVX4TS U3856 ( .A(n2993), .Y(n5364) );
INVX4TS U3857 ( .A(n3915), .Y(n5365) );
BUFX3TS U3858 ( .A(n5317), .Y(n5340) );
BUFX3TS U3859 ( .A(n5338), .Y(n5350) );
INVX4TS U3860 ( .A(n3915), .Y(n5366) );
INVX4TS U3861 ( .A(n3915), .Y(n5369) );
INVX4TS U3862 ( .A(n3915), .Y(n5368) );
INVX4TS U3863 ( .A(n3004), .Y(n5373) );
INVX4TS U3864 ( .A(n3915), .Y(n5367) );
INVX4TS U3865 ( .A(n2993), .Y(n5398) );
INVX4TS U3866 ( .A(n2993), .Y(n5401) );
BUFX3TS U3867 ( .A(n5334), .Y(n5318) );
INVX4TS U3868 ( .A(n2993), .Y(n5400) );
CLKBUFX2TS U3869 ( .A(n5347), .Y(n5341) );
BUFX3TS U3870 ( .A(n5348), .Y(n5339) );
INVX4TS U3871 ( .A(n3003), .Y(n5352) );
BUFX3TS U3872 ( .A(n5318), .Y(n5348) );
BUFX3TS U3873 ( .A(n5334), .Y(n5314) );
INVX4TS U3874 ( .A(n2993), .Y(n5403) );
INVX4TS U3875 ( .A(n3004), .Y(n5361) );
INVX4TS U3876 ( .A(n2993), .Y(n5402) );
BUFX3TS U3877 ( .A(n5351), .Y(n5331) );
NAND3X1TS U3878 ( .A(cordic_FSM_state_reg[3]), .B(n5057), .C(n5124), .Y(
n4606) );
NAND2X1TS U3879 ( .A(d_ff1_operation_out), .B(d_ff1_shift_region_flag_out[0]), .Y(n3916) );
OAI221XLTS U3880 ( .A0(d_ff1_shift_region_flag_out[1]), .A1(
d_ff1_shift_region_flag_out[0]), .B0(n5241), .B1(d_ff1_operation_out),
.C0(n3916), .Y(n3005) );
XNOR2X1TS U3881 ( .A(data_output2_63_), .B(n3005), .Y(n3006) );
BUFX3TS U3882 ( .A(n4845), .Y(n4852) );
AO22XLTS U3883 ( .A0(n4851), .A1(n3006), .B0(n4852), .B1(data_output[63]),
.Y(n1961) );
INVX2TS U3884 ( .A(add_subt_module_FS_Module_state_reg[3]), .Y(n4607) );
INVX2TS U3885 ( .A(n4623), .Y(n4617) );
INVX2TS U3886 ( .A(n4772), .Y(n4777) );
BUFX3TS U3887 ( .A(n4777), .Y(n4766) );
NOR2XLTS U3888 ( .A(add_subt_module_sign_final_result), .B(underflow_flag),
.Y(n3008) );
NAND2BX1TS U3889 ( .AN(sel_mux_2_reg[0]), .B(n4025), .Y(n3009) );
NOR2X2TS U3890 ( .A(n3009), .B(n5212), .Y(n5006) );
AOI22X1TS U3891 ( .A0(n5030), .A1(d_ff3_LUT_out[42]), .B0(n4948), .B1(
d_ff3_sh_y_out[42]), .Y(n3012) );
INVX2TS U3892 ( .A(n4025), .Y(n3046) );
NOR2XLTS U3893 ( .A(sel_mux_2_reg[1]), .B(n5240), .Y(n3010) );
AND2X2TS U3894 ( .A(n4025), .B(n3010), .Y(n3144) );
BUFX4TS U3895 ( .A(n3144), .Y(n4992) );
AOI22X1TS U3896 ( .A0(add_subt_module_intDY[42]), .A1(n5011), .B0(n5042),
.B1(d_ff3_sh_x_out[42]), .Y(n3011) );
NAND2X1TS U3897 ( .A(n3012), .B(n3011), .Y(n1822) );
AOI22X1TS U3898 ( .A0(d_ff3_LUT_out[8]), .A1(n5030), .B0(n4908), .B1(
d_ff3_sh_y_out[8]), .Y(n3014) );
AOI22X1TS U3899 ( .A0(add_subt_module_intDY[8]), .A1(n5036), .B0(n4931),
.B1(d_ff3_sh_x_out[8]), .Y(n3013) );
NAND2X1TS U3900 ( .A(n3014), .B(n3013), .Y(n1818) );
AOI22X1TS U3901 ( .A0(d_ff3_LUT_out[40]), .A1(n5030), .B0(n4970), .B1(
d_ff3_sh_y_out[40]), .Y(n3016) );
BUFX4TS U3902 ( .A(n3144), .Y(n4954) );
AOI22X1TS U3903 ( .A0(add_subt_module_intDY[40]), .A1(n2973), .B0(n4992),
.B1(d_ff3_sh_x_out[40]), .Y(n3015) );
NAND2X1TS U3904 ( .A(n3016), .B(n3015), .Y(n1836) );
AOI22X1TS U3905 ( .A0(d_ff3_LUT_out[11]), .A1(n5030), .B0(n5001), .B1(
d_ff3_sh_y_out[11]), .Y(n3018) );
AOI22X1TS U3906 ( .A0(add_subt_module_intDY[11]), .A1(n3046), .B0(n5027),
.B1(d_ff3_sh_x_out[11]), .Y(n3017) );
NAND2X1TS U3907 ( .A(n3018), .B(n3017), .Y(n1825) );
AOI22X1TS U3908 ( .A0(add_subt_module_intDY[34]), .A1(n2974), .B0(n4970),
.B1(d_ff3_sh_y_out[34]), .Y(n3020) );
AOI22X1TS U3909 ( .A0(d_ff3_LUT_out[34]), .A1(n5030), .B0(n5035), .B1(
d_ff3_sh_x_out[34]), .Y(n3019) );
NAND2X1TS U3910 ( .A(n3020), .B(n3019), .Y(n1800) );
AOI22X1TS U3911 ( .A0(n2986), .A1(n4922), .B0(n4908), .B1(d_ff3_sh_y_out[30]), .Y(n3022) );
AOI22X1TS U3912 ( .A0(d_ff3_LUT_out[30]), .A1(n5030), .B0(n5035), .B1(
d_ff3_sh_x_out[30]), .Y(n3021) );
NAND2X1TS U3913 ( .A(n3022), .B(n3021), .Y(n1794) );
INVX4TS U3914 ( .A(n2956), .Y(n5041) );
AOI22X1TS U3915 ( .A0(d_ff3_LUT_out[36]), .A1(n4913), .B0(n5001), .B1(
d_ff3_sh_y_out[36]), .Y(n3024) );
BUFX4TS U3916 ( .A(n3144), .Y(n5027) );
AOI22X1TS U3917 ( .A0(add_subt_module_intDY[36]), .A1(n4893), .B0(n5027),
.B1(d_ff3_sh_x_out[36]), .Y(n3023) );
NAND2X1TS U3918 ( .A(n3024), .B(n3023), .Y(n1784) );
AOI22X1TS U3919 ( .A0(d_ff3_LUT_out[27]), .A1(n5041), .B0(n5033), .B1(
d_ff3_sh_y_out[27]), .Y(n3026) );
AOI22X1TS U3920 ( .A0(add_subt_module_intDY[27]), .A1(n4922), .B0(n5042),
.B1(d_ff3_sh_x_out[27]), .Y(n3025) );
NAND2X1TS U3921 ( .A(n3026), .B(n3025), .Y(n1777) );
AOI22X1TS U3922 ( .A0(add_subt_module_intDY[14]), .A1(n5011), .B0(n5001),
.B1(d_ff3_sh_y_out[14]), .Y(n3028) );
AOI22X1TS U3923 ( .A0(d_ff3_LUT_out[14]), .A1(n5041), .B0(n5042), .B1(
d_ff3_sh_x_out[14]), .Y(n3027) );
NAND2X1TS U3924 ( .A(n3028), .B(n3027), .Y(n1780) );
BUFX4TS U3925 ( .A(n5039), .Y(n5033) );
AOI22X1TS U3926 ( .A0(d_ff3_LUT_out[32]), .A1(n5034), .B0(n4970), .B1(
d_ff3_sh_y_out[32]), .Y(n3030) );
AOI22X1TS U3927 ( .A0(n2987), .A1(n2974), .B0(n5042), .B1(d_ff3_sh_x_out[32]), .Y(n3029) );
NAND2X1TS U3928 ( .A(n3030), .B(n3029), .Y(n1748) );
AOI22X1TS U3929 ( .A0(d_ff3_LUT_out[28]), .A1(n5034), .B0(n5039), .B1(
d_ff3_sh_y_out[28]), .Y(n3032) );
AOI22X1TS U3930 ( .A0(add_subt_module_intDY[28]), .A1(n5036), .B0(n4971),
.B1(d_ff3_sh_x_out[28]), .Y(n3031) );
NAND2X1TS U3931 ( .A(n3032), .B(n3031), .Y(n1738) );
AOI22X1TS U3932 ( .A0(add_subt_module_intDY[25]), .A1(n4922), .B0(n4886),
.B1(d_ff3_sh_y_out[25]), .Y(n3034) );
AOI22X1TS U3933 ( .A0(d_ff3_LUT_out[25]), .A1(n5014), .B0(n4931), .B1(
d_ff3_sh_x_out[25]), .Y(n3033) );
NAND2X1TS U3934 ( .A(n3034), .B(n3033), .Y(n1759) );
AOI22X1TS U3935 ( .A0(n4931), .A1(d_ff2_Y[39]), .B0(n4948), .B1(d_ff2_X[39]),
.Y(n3036) );
AOI22X1TS U3936 ( .A0(add_subt_module_intDX[39]), .A1(n5040), .B0(
d_ff2_Z[39]), .B1(n5041), .Y(n3035) );
NAND2X1TS U3937 ( .A(n3036), .B(n3035), .Y(n1812) );
AOI22X1TS U3938 ( .A0(n4954), .A1(d_ff2_Y[8]), .B0(n5033), .B1(d_ff2_X[8]),
.Y(n3038) );
AOI22X1TS U3939 ( .A0(add_subt_module_intDX[8]), .A1(n5036), .B0(d_ff2_Z[8]),
.B1(n5014), .Y(n3037) );
NAND2X1TS U3940 ( .A(n3038), .B(n3037), .Y(n1819) );
NAND3BXLTS U3941 ( .AN(overflow_flag), .B(n4772), .C(n5237), .Y(n3039) );
BUFX4TS U3942 ( .A(n3039), .Y(n4788) );
OA22X1TS U3943 ( .A0(n4772), .A1(result_add_subt[60]), .B0(
add_subt_module_exp_oper_result[8]), .B1(n4776), .Y(n2526) );
OA22X1TS U3944 ( .A0(n4772), .A1(result_add_subt[61]), .B0(
add_subt_module_exp_oper_result[9]), .B1(n4776), .Y(n2530) );
OA22X1TS U3945 ( .A0(n4772), .A1(result_add_subt[62]), .B0(
add_subt_module_exp_oper_result[10]), .B1(n4794), .Y(n2534) );
BUFX4TS U3946 ( .A(n3144), .Y(n5042) );
AOI22X1TS U3947 ( .A0(n4992), .A1(d_ff2_Y[24]), .B0(n5001), .B1(d_ff2_X[24]),
.Y(n3041) );
INVX4TS U3948 ( .A(n2956), .Y(n5014) );
AOI22X1TS U3949 ( .A0(add_subt_module_intDX[24]), .A1(n5036), .B0(
d_ff2_Z[24]), .B1(n4913), .Y(n3040) );
NAND2X1TS U3950 ( .A(n3041), .B(n3040), .Y(n1745) );
BUFX4TS U3951 ( .A(n5039), .Y(n4908) );
AOI22X1TS U3952 ( .A0(n4954), .A1(d_ff2_Y[48]), .B0(n5033), .B1(d_ff2_X[48]),
.Y(n3043) );
BUFX4TS U3953 ( .A(n3046), .Y(n4893) );
AOI22X1TS U3954 ( .A0(add_subt_module_intDX[48]), .A1(n4893), .B0(
d_ff2_Z[48]), .B1(n5041), .Y(n3042) );
NAND2X1TS U3955 ( .A(n3043), .B(n3042), .Y(n1901) );
AOI22X1TS U3956 ( .A0(n4954), .A1(d_ff2_Y[2]), .B0(n4886), .B1(d_ff2_X[2]),
.Y(n3045) );
INVX4TS U3957 ( .A(n2956), .Y(n4913) );
AOI22X1TS U3958 ( .A0(add_subt_module_intDX[2]), .A1(n5011), .B0(d_ff2_Z[2]),
.B1(n5041), .Y(n3044) );
NAND2X1TS U3959 ( .A(n3045), .B(n3044), .Y(n1897) );
AOI22X1TS U3960 ( .A0(n4931), .A1(d_ff2_Y[16]), .B0(n4886), .B1(d_ff2_X[16]),
.Y(n3048) );
BUFX4TS U3961 ( .A(n3046), .Y(n4922) );
AOI22X1TS U3962 ( .A0(add_subt_module_intDX[16]), .A1(n2974), .B0(
d_ff2_Z[16]), .B1(n5014), .Y(n3047) );
NAND2X1TS U3963 ( .A(n3048), .B(n3047), .Y(n1873) );
AOI22X1TS U3964 ( .A0(n5027), .A1(d_ff2_Y[9]), .B0(n4886), .B1(d_ff2_X[9]),
.Y(n3050) );
AOI22X1TS U3965 ( .A0(add_subt_module_intDX[9]), .A1(n4922), .B0(d_ff2_Z[9]),
.B1(n4913), .Y(n3049) );
NAND2X1TS U3966 ( .A(n3050), .B(n3049), .Y(n1870) );
AOI22X1TS U3967 ( .A0(n5042), .A1(d_ff2_Y[47]), .B0(n4948), .B1(d_ff2_X[47]),
.Y(n3052) );
AOI22X1TS U3968 ( .A0(add_subt_module_intDX[47]), .A1(n5040), .B0(
d_ff2_Z[47]), .B1(n5041), .Y(n3051) );
NAND2X1TS U3969 ( .A(n3052), .B(n3051), .Y(n1891) );
AOI22X1TS U3970 ( .A0(n5042), .A1(d_ff2_Y[1]), .B0(n4886), .B1(d_ff2_X[1]),
.Y(n3054) );
AOI22X1TS U3971 ( .A0(add_subt_module_intDX[1]), .A1(n5011), .B0(d_ff2_Z[1]),
.B1(n5034), .Y(n3053) );
NAND2X1TS U3972 ( .A(n3054), .B(n3053), .Y(n1884) );
INVX4TS U3973 ( .A(n2956), .Y(n4953) );
AOI22X1TS U3974 ( .A0(n4953), .A1(d_ff3_LUT_out[24]), .B0(n5033), .B1(
d_ff3_sh_y_out[24]), .Y(n3056) );
AOI22X1TS U3975 ( .A0(n2988), .A1(n5011), .B0(n5035), .B1(d_ff3_sh_x_out[24]), .Y(n3055) );
NAND2X1TS U3976 ( .A(n3056), .B(n3055), .Y(n1744) );
INVX4TS U3977 ( .A(n2956), .Y(n4965) );
AOI22X1TS U3978 ( .A0(n4965), .A1(d_ff3_LUT_out[50]), .B0(n4948), .B1(
d_ff3_sh_y_out[50]), .Y(n3058) );
BUFX4TS U3979 ( .A(n3144), .Y(n4931) );
AOI22X1TS U3980 ( .A0(add_subt_module_intDY[50]), .A1(n2974), .B0(n4992),
.B1(d_ff3_sh_x_out[50]), .Y(n3057) );
NAND2X1TS U3981 ( .A(n3058), .B(n3057), .Y(n1893) );
AOI22X1TS U3982 ( .A0(n4953), .A1(d_ff3_LUT_out[20]), .B0(n4948), .B1(
d_ff3_sh_y_out[20]), .Y(n3060) );
AOI22X1TS U3983 ( .A0(add_subt_module_intDY[20]), .A1(n2974), .B0(n5027),
.B1(d_ff3_sh_x_out[20]), .Y(n3059) );
NAND2X1TS U3984 ( .A(n3060), .B(n3059), .Y(n1852) );
AOI22X1TS U3985 ( .A0(n4965), .A1(d_ff3_LUT_out[39]), .B0(n4948), .B1(
d_ff3_sh_y_out[39]), .Y(n3062) );
AOI22X1TS U3986 ( .A0(add_subt_module_intDY[39]), .A1(n5036), .B0(n5027),
.B1(d_ff3_sh_x_out[39]), .Y(n3061) );
NAND2X1TS U3987 ( .A(n3062), .B(n3061), .Y(n1811) );
AOI22X1TS U3988 ( .A0(n5035), .A1(d_ff3_sh_x_out[38]), .B0(n5001), .B1(
d_ff3_sh_y_out[38]), .Y(n3064) );
AOI22X1TS U3989 ( .A0(add_subt_module_intDY[38]), .A1(n5040), .B0(
d_ff3_LUT_out[38]), .B1(n4913), .Y(n3063) );
NAND2X1TS U3990 ( .A(n3064), .B(n3063), .Y(n1832) );
AOI22X1TS U3991 ( .A0(n4992), .A1(d_ff2_Y[28]), .B0(n4948), .B1(d_ff2_X[28]),
.Y(n3066) );
AOI22X1TS U3992 ( .A0(add_subt_module_intDX[28]), .A1(n4922), .B0(
d_ff2_Z[28]), .B1(n4913), .Y(n3065) );
NAND2X1TS U3993 ( .A(n3066), .B(n3065), .Y(n1739) );
AOI22X1TS U3994 ( .A0(n5027), .A1(d_ff2_Y[53]), .B0(n2977), .B1(d_ff2_X[53]),
.Y(n3068) );
AOI22X1TS U3995 ( .A0(add_subt_module_intDX[53]), .A1(n5036), .B0(
d_ff2_Z[53]), .B1(n5041), .Y(n3067) );
NAND2X1TS U3996 ( .A(n3068), .B(n3067), .Y(n1915) );
AOI22X1TS U3997 ( .A0(n4931), .A1(d_ff2_Y[46]), .B0(n4908), .B1(d_ff2_X[46]),
.Y(n3070) );
AOI22X1TS U3998 ( .A0(add_subt_module_intDX[46]), .A1(n2973), .B0(
d_ff2_Z[46]), .B1(n5014), .Y(n3069) );
NAND2X1TS U3999 ( .A(n3070), .B(n3069), .Y(n1877) );
AOI22X1TS U4000 ( .A0(n4992), .A1(d_ff2_Y[35]), .B0(n4970), .B1(d_ff2_X[35]),
.Y(n3072) );
AOI22X1TS U4001 ( .A0(add_subt_module_intDX[35]), .A1(n4922), .B0(
d_ff2_Z[35]), .B1(n4913), .Y(n3071) );
NAND2X1TS U4002 ( .A(n3072), .B(n3071), .Y(n1792) );
AOI22X1TS U4003 ( .A0(n5035), .A1(d_ff2_Y[42]), .B0(n2977), .B1(d_ff2_X[42]),
.Y(n3074) );
AOI22X1TS U4004 ( .A0(add_subt_module_intDX[42]), .A1(n4893), .B0(
d_ff2_Z[42]), .B1(n5041), .Y(n3073) );
NAND2X1TS U4005 ( .A(n3074), .B(n3073), .Y(n1823) );
AOI22X1TS U4006 ( .A0(n4954), .A1(d_ff2_Y[50]), .B0(n4970), .B1(d_ff2_X[50]),
.Y(n3076) );
AOI22X1TS U4007 ( .A0(add_subt_module_intDX[50]), .A1(n4893), .B0(
d_ff2_Z[50]), .B1(n5014), .Y(n3075) );
NAND2X1TS U4008 ( .A(n3076), .B(n3075), .Y(n1894) );
AOI22X1TS U4009 ( .A0(n4992), .A1(d_ff2_Y[17]), .B0(n5001), .B1(d_ff2_X[17]),
.Y(n3078) );
AOI22X1TS U4010 ( .A0(add_subt_module_intDX[17]), .A1(n2973), .B0(
d_ff2_Z[17]), .B1(n4913), .Y(n3077) );
NAND2X1TS U4011 ( .A(n3078), .B(n3077), .Y(n1752) );
AOI22X1TS U4012 ( .A0(n5042), .A1(d_ff2_Y[11]), .B0(n4908), .B1(d_ff2_X[11]),
.Y(n3080) );
AOI22X1TS U4013 ( .A0(add_subt_module_intDX[11]), .A1(n5040), .B0(
d_ff2_Z[11]), .B1(n4913), .Y(n3079) );
NAND2X1TS U4014 ( .A(n3080), .B(n3079), .Y(n1826) );
AOI22X1TS U4015 ( .A0(n4992), .A1(d_ff2_Y[18]), .B0(n4948), .B1(d_ff2_X[18]),
.Y(n3082) );
AOI22X1TS U4016 ( .A0(add_subt_module_intDX[18]), .A1(n5011), .B0(
d_ff2_Z[18]), .B1(n5041), .Y(n3081) );
NAND2X1TS U4017 ( .A(n3082), .B(n3081), .Y(n1763) );
AOI22X1TS U4018 ( .A0(n4965), .A1(d_ff2_Z[52]), .B0(n4908), .B1(d_ff2_X[52]),
.Y(n3084) );
AOI22X1TS U4019 ( .A0(add_subt_module_intDX[52]), .A1(n5040), .B0(n5042),
.B1(d_ff2_Y[52]), .Y(n3083) );
NAND2X1TS U4020 ( .A(n3084), .B(n3083), .Y(n1912) );
INVX2TS U4021 ( .A(n4697), .Y(n3085) );
INVX2TS U4022 ( .A(cont_iter_out[0]), .Y(n3228) );
NAND2X1TS U4023 ( .A(cordic_FSM_state_reg[2]), .B(n5045), .Y(n3914) );
INVX2TS U4024 ( .A(n3914), .Y(n4601) );
OAI21X1TS U4025 ( .A0(n3085), .A1(n4690), .B0(n4706), .Y(n4705) );
INVX2TS U4026 ( .A(n4637), .Y(n4669) );
NAND2X1TS U4027 ( .A(cont_iter_out[3]), .B(n3228), .Y(n3104) );
NOR2X1TS U4028 ( .A(n3108), .B(n4680), .Y(n3110) );
NAND2X2TS U4029 ( .A(cont_iter_out[1]), .B(n5118), .Y(n4701) );
INVX2TS U4030 ( .A(n4701), .Y(n4658) );
NOR2X2TS U4031 ( .A(cont_iter_out[0]), .B(cont_iter_out[3]), .Y(n4691) );
NAND2X2TS U4032 ( .A(n4658), .B(n4691), .Y(n4698) );
NAND2X1TS U4033 ( .A(n4671), .B(n4698), .Y(n3086) );
OA22X1TS U4034 ( .A0(n4705), .A1(n3086), .B0(n4822), .B1(d_ff3_LUT_out[27]),
.Y(n2822) );
NOR2X1TS U4035 ( .A(n3228), .B(n4701), .Y(n3090) );
AOI211X1TS U4036 ( .A0(cont_iter_out[2]), .A1(n5049), .B0(n4697), .C0(n4818),
.Y(n3089) );
NAND2X1TS U4037 ( .A(n3089), .B(n4655), .Y(n3087) );
OA22X1TS U4038 ( .A0(n3090), .A1(n3087), .B0(n4826), .B1(d_ff3_LUT_out[10]),
.Y(n2805) );
INVX4TS U4039 ( .A(n4818), .Y(n4819) );
BUFX4TS U4040 ( .A(n3088), .Y(n4726) );
AO22XLTS U4041 ( .A0(n4819), .A1(intadd_373_SUM_0_), .B0(n4726), .B1(
d_ff3_sh_x_out[53]), .Y(n2781) );
AO22XLTS U4042 ( .A0(n4819), .A1(n4690), .B0(n4726), .B1(d_ff3_LUT_out[53]),
.Y(n2847) );
AO22XLTS U4043 ( .A0(n4819), .A1(intadd_373_SUM_2_), .B0(n4726), .B1(
d_ff3_sh_x_out[55]), .Y(n2779) );
AO22XLTS U4044 ( .A0(n4819), .A1(intadd_373_SUM_1_), .B0(n4726), .B1(
d_ff3_sh_x_out[54]), .Y(n2780) );
NAND2X1TS U4045 ( .A(n3089), .B(n4698), .Y(n4666) );
OA22X1TS U4046 ( .A0(n3090), .A1(n4666), .B0(n4822), .B1(d_ff3_LUT_out[31]),
.Y(n2826) );
NAND2BXLTS U4047 ( .AN(n4679), .B(n5056), .Y(n4676) );
OA22X1TS U4048 ( .A0(n4822), .A1(d_ff3_LUT_out[24]), .B0(n4666), .B1(n4676),
.Y(n2819) );
AOI22X1TS U4049 ( .A0(n5027), .A1(d_ff3_sh_x_out[48]), .B0(n4970), .B1(
d_ff3_sh_y_out[48]), .Y(n3091) );
NAND2X2TS U4050 ( .A(n5034), .B(d_ff3_LUT_out[48]), .Y(n3097) );
AOI22X1TS U4051 ( .A0(d_ff3_sh_x_out[61]), .A1(n4971), .B0(
d_ff3_sh_y_out[61]), .B1(n5039), .Y(n3092) );
AOI22X1TS U4052 ( .A0(n4954), .A1(d_ff3_sh_x_out[51]), .B0(n4908), .B1(
d_ff3_sh_y_out[51]), .Y(n3093) );
OAI211XLTS U4053 ( .A0(n4025), .A1(n5236), .B0(n3093), .C0(n3097), .Y(n1906)
);
AOI22X1TS U4054 ( .A0(d_ff3_sh_x_out[60]), .A1(n4971), .B0(
d_ff3_sh_y_out[60]), .B1(n5039), .Y(n3094) );
OAI211XLTS U4055 ( .A0(n4025), .A1(n5185), .B0(n3094), .C0(n3097), .Y(n1955)
);
AOI22X1TS U4056 ( .A0(n4992), .A1(d_ff3_sh_x_out[58]), .B0(n5001), .B1(
d_ff3_sh_y_out[58]), .Y(n3095) );
OAI211XLTS U4057 ( .A0(n4025), .A1(n5141), .B0(n3095), .C0(n3097), .Y(n1953)
);
AOI22X1TS U4058 ( .A0(d_ff3_sh_x_out[59]), .A1(n4992), .B0(
d_ff3_sh_y_out[59]), .B1(n5039), .Y(n3096) );
OAI211XLTS U4059 ( .A0(n4025), .A1(n5073), .B0(n3096), .C0(n3097), .Y(n1954)
);
AOI22X1TS U4060 ( .A0(n5042), .A1(d_ff3_sh_x_out[57]), .B0(n5033), .B1(
d_ff3_sh_y_out[57]), .Y(n3098) );
INVX1TS U4061 ( .A(d_ff2_X[58]), .Y(n4712) );
NAND2X1TS U4062 ( .A(n4716), .B(n4712), .Y(n4720) );
OAI21XLTS U4063 ( .A0(n4716), .A1(n4712), .B0(n4720), .Y(n3099) );
AO22XLTS U4064 ( .A0(n4819), .A1(n3099), .B0(n4726), .B1(d_ff3_sh_x_out[58]),
.Y(n2776) );
INVX2TS U4065 ( .A(n4603), .Y(n3100) );
OA22X1TS U4066 ( .A0(n4813), .A1(d_ff2_X[13]), .B0(d_ff_Xn[13]), .B1(n4710),
.Y(n2695) );
OA22X1TS U4067 ( .A0(n4813), .A1(d_ff2_X[19]), .B0(d_ff_Xn[19]), .B1(n4710),
.Y(n2707) );
INVX2TS U4068 ( .A(n4654), .Y(n4632) );
BUFX4TS U4069 ( .A(n4838), .Y(n4817) );
INVX2TS U4070 ( .A(n4680), .Y(n4678) );
OAI21XLTS U4071 ( .A0(n4691), .A1(n4678), .B0(n4698), .Y(n3102) );
NOR3X1TS U4072 ( .A(n4632), .B(n4817), .C(n3102), .Y(n4657) );
AOI21X1TS U4073 ( .A0(n4706), .A1(cont_iter_out[0]), .B0(n4657), .Y(n3103)
);
OA22X1TS U4074 ( .A0(n4836), .A1(d_ff3_LUT_out[0]), .B0(n3103), .B1(n4679),
.Y(n2795) );
CLKBUFX2TS U4075 ( .A(n4710), .Y(n4800) );
BUFX4TS U4076 ( .A(n4800), .Y(n4728) );
OA22X1TS U4077 ( .A0(n4813), .A1(d_ff2_X[36]), .B0(d_ff_Xn[36]), .B1(n4728),
.Y(n2741) );
OA22X1TS U4078 ( .A0(n4813), .A1(d_ff2_X[39]), .B0(d_ff_Xn[39]), .B1(n4728),
.Y(n2747) );
OA22X1TS U4079 ( .A0(n4813), .A1(d_ff2_X[35]), .B0(d_ff_Xn[35]), .B1(n4728),
.Y(n2739) );
OA22X1TS U4080 ( .A0(n4813), .A1(d_ff2_X[34]), .B0(d_ff_Xn[34]), .B1(n4728),
.Y(n2737) );
BUFX3TS U4081 ( .A(n4710), .Y(n4812) );
OA22X1TS U4082 ( .A0(n4803), .A1(d_ff2_X[3]), .B0(d_ff_Xn[3]), .B1(n4812),
.Y(n2675) );
OA22X1TS U4083 ( .A0(n4813), .A1(d_ff2_X[8]), .B0(d_ff_Xn[8]), .B1(n4812),
.Y(n2685) );
OA22X1TS U4084 ( .A0(n4803), .A1(d_ff2_X[7]), .B0(d_ff_Xn[7]), .B1(n4812),
.Y(n2683) );
OA22X1TS U4085 ( .A0(n4813), .A1(d_ff2_X[11]), .B0(d_ff_Xn[11]), .B1(n4812),
.Y(n2691) );
OA22X1TS U4086 ( .A0(n4813), .A1(d_ff2_X[9]), .B0(d_ff_Xn[9]), .B1(n4812),
.Y(n2687) );
NAND2X1TS U4087 ( .A(n4677), .B(n4671), .Y(n3105) );
OA22X1TS U4088 ( .A0(n3231), .A1(n3105), .B0(n4819), .B1(d_ff3_LUT_out[55]),
.Y(n2849) );
NOR2XLTS U4089 ( .A(n4637), .B(n3104), .Y(n3106) );
OA22X1TS U4090 ( .A0(n4706), .A1(d_ff3_LUT_out[25]), .B0(n3106), .B1(n3105),
.Y(n2820) );
INVX1TS U4091 ( .A(d_ff2_X[60]), .Y(n4709) );
NAND2X1TS U4092 ( .A(n4719), .B(n4709), .Y(n4722) );
OAI21XLTS U4093 ( .A0(n4719), .A1(n4709), .B0(n4722), .Y(n3107) );
AO22XLTS U4094 ( .A0(n4819), .A1(n3107), .B0(n4726), .B1(d_ff3_sh_x_out[60]),
.Y(n2774) );
INVX2TS U4095 ( .A(n3108), .Y(n4682) );
AO21X1TS U4096 ( .A0(n5118), .A1(n4682), .B0(n4667), .Y(n4703) );
OAI21X1TS U4097 ( .A0(n4697), .A1(n4703), .B0(n4706), .Y(n3232) );
NAND3XLTS U4098 ( .A(n3231), .B(n4706), .C(n4698), .Y(n4663) );
AOI21X1TS U4099 ( .A0(n3232), .A1(n4663), .B0(n4667), .Y(n4696) );
AOI21X1TS U4100 ( .A0(n4677), .A1(n5056), .B0(n4696), .Y(n3109) );
OA22X1TS U4101 ( .A0(n4822), .A1(d_ff3_LUT_out[5]), .B0(n3110), .B1(n3109),
.Y(n2800) );
NOR2X1TS U4102 ( .A(cordic_FSM_state_reg[1]), .B(beg_fsm_cordic), .Y(n3921)
);
NOR3X2TS U4103 ( .A(cordic_FSM_state_reg[2]), .B(cordic_FSM_state_reg[0]),
.C(n5057), .Y(n4735) );
NOR2X2TS U4104 ( .A(add_subt_module_FS_Module_state_reg[0]), .B(n4607), .Y(
n3906) );
NAND4XLTS U4105 ( .A(add_subt_module_FS_Module_state_reg[2]), .B(
add_subt_module_FS_Module_state_reg[1]), .C(n3906), .D(n5168), .Y(
n4605) );
AOI21X1TS U4106 ( .A0(cordic_FSM_state_reg[3]), .A1(n4605), .B0(
cordic_FSM_state_reg[0]), .Y(n3111) );
NAND4X1TS U4107 ( .A(cordic_FSM_state_reg[3]), .B(cordic_FSM_state_reg[0]),
.C(n5057), .D(n5168), .Y(n4631) );
INVX2TS U4108 ( .A(n4631), .Y(n4633) );
NAND3BX1TS U4109 ( .AN(n4744), .B(n5205), .C(n4633), .Y(n3227) );
BUFX4TS U4110 ( .A(n4845), .Y(n4848) );
OR3X1TS U4111 ( .A(ack_cordic), .B(n4603), .C(n5045), .Y(n4597) );
NAND4XLTS U4112 ( .A(n3112), .B(n3227), .C(n4848), .D(n4597), .Y(n2938) );
NAND4XLTS U4113 ( .A(add_subt_module_Exp_Operation_Module_Data_S[2]), .B(
add_subt_module_Exp_Operation_Module_Data_S[1]), .C(n3114), .D(
add_subt_module_Exp_Operation_Module_Data_S[0]), .Y(n3115) );
NAND4BXLTS U4114 ( .AN(n3115), .B(
add_subt_module_Exp_Operation_Module_Data_S[5]), .C(
add_subt_module_Exp_Operation_Module_Data_S[4]), .D(
add_subt_module_Exp_Operation_Module_Data_S[3]), .Y(n3116) );
NAND4BXLTS U4115 ( .AN(n3116), .B(
add_subt_module_Exp_Operation_Module_Data_S[8]), .C(
add_subt_module_Exp_Operation_Module_Data_S[7]), .D(
add_subt_module_Exp_Operation_Module_Data_S[6]), .Y(n3118) );
NAND4BXLTS U4116 ( .AN(n3118), .B(n3117), .C(
add_subt_module_Exp_Operation_Module_Data_S[10]), .D(
add_subt_module_Exp_Operation_Module_Data_S[9]), .Y(n3121) );
INVX2TS U4117 ( .A(n3114), .Y(n3119) );
NAND2X1TS U4118 ( .A(n3119), .B(overflow_flag), .Y(n3120) );
NAND2X1TS U4119 ( .A(n3121), .B(n3120), .Y(n2651) );
INVX2TS U4120 ( .A(add_subt_module_FSM_selector_C), .Y(n3912) );
AND2X2TS U4121 ( .A(n4623), .B(n3122), .Y(n4537) );
CLKAND2X2TS U4122 ( .A(n4583), .B(n3123), .Y(n3784) );
NAND2X1TS U4123 ( .A(n3124), .B(add_subt_module_LZA_output[5]), .Y(n3931) );
NAND2X1TS U4124 ( .A(n2953), .B(add_subt_module_exp_oper_result[5]), .Y(
n3125) );
NAND2X2TS U4125 ( .A(n3931), .B(n3125), .Y(n3135) );
NAND2X2TS U4126 ( .A(n3133), .B(n3132), .Y(n3570) );
INVX4TS U4127 ( .A(n3123), .Y(n3807) );
OA21X2TS U4128 ( .A0(n4611), .A1(n3127), .B0(
add_subt_module_add_overflow_flag), .Y(n3643) );
INVX2TS U4129 ( .A(n3132), .Y(n3131) );
AND2X2TS U4130 ( .A(n3133), .B(n3131), .Y(n3631) );
INVX4TS U4131 ( .A(n2991), .Y(n4034) );
NOR3X1TS U4132 ( .A(n3133), .B(n3132), .C(n3135), .Y(n3575) );
AOI22X1TS U4133 ( .A0(n4034), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[64]), .B0(
n3788), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[80]), .Y(
n3137) );
INVX2TS U4134 ( .A(n3135), .Y(n3637) );
NAND2X1TS U4135 ( .A(n3637), .B(n3631), .Y(n4037) );
AOI22X1TS U4136 ( .A0(n3134), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[56]), .B0(
n3787), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[72]), .Y(
n3136) );
OAI211X1TS U4137 ( .A0(n3792), .A1(n3650), .B0(n3137), .C0(n3136), .Y(n3765)
);
INVX2TS U4138 ( .A(n3643), .Y(n3580) );
OR2X2TS U4139 ( .A(n4583), .B(n5120), .Y(n3702) );
AOI2BB2XLTS U4140 ( .B0(n3785), .B1(add_subt_module_Sgf_normalized_result[1]), .A0N(n3767), .A1N(n2976), .Y(n3138) );
OAI2BB1X1TS U4141 ( .A0N(n3784), .A1N(n3765), .B0(n3138), .Y(n2536) );
BUFX4TS U4142 ( .A(n3134), .Y(n3780) );
AOI22X1TS U4143 ( .A0(n3134), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[55]), .B0(
n3787), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[71]), .Y(
n3141) );
INVX4TS U4144 ( .A(n2991), .Y(n3685) );
AOI22X1TS U4145 ( .A0(n3685), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[63]), .B0(
n4033), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[79]), .Y(
n3140) );
OAI211X1TS U4146 ( .A0(n3792), .A1(n3661), .B0(n3141), .C0(n3140), .Y(n3805)
);
MXI2X2TS U4147 ( .A(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[109]), .B(
n3643), .S0(n3570), .Y(n3809) );
AOI2BB2XLTS U4148 ( .B0(n3785), .B1(add_subt_module_Sgf_normalized_result[0]), .A0N(n3809), .A1N(n2976), .Y(n3142) );
OAI2BB1X1TS U4149 ( .A0N(n3784), .A1N(n3805), .B0(n3142), .Y(n2535) );
INVX4TS U4150 ( .A(n2993), .Y(n5388) );
INVX4TS U4151 ( .A(n2993), .Y(n5362) );
INVX4TS U4152 ( .A(n2993), .Y(n5399) );
AOI22X1TS U4153 ( .A0(d_ff3_sh_x_out[62]), .A1(n5035), .B0(
d_ff3_sh_y_out[62]), .B1(n5039), .Y(n3143) );
OAI21XLTS U4154 ( .A0(n4025), .A1(n5142), .B0(n3143), .Y(n1957) );
INVX2TS U4155 ( .A(n3145), .Y(n1946) );
AOI22X1TS U4156 ( .A0(n4931), .A1(d_ff2_Y[63]), .B0(
add_subt_module_intDX[63]), .B1(n5011), .Y(n3147) );
NAND2X1TS U4157 ( .A(n2977), .B(d_ff2_X[63]), .Y(n3146) );
OAI211XLTS U4158 ( .A0(n2956), .A1(n5312), .B0(n3147), .C0(n3146), .Y(n1945)
);
INVX1TS U4159 ( .A(d_ff2_Y[52]), .Y(n4814) );
NAND2X1TS U4160 ( .A(cont_iter_out[0]), .B(n4814), .Y(intadd_372_CI) );
NAND2X1TS U4161 ( .A(cont_iter_out[0]), .B(n5182), .Y(intadd_373_CI) );
NAND2X1TS U4162 ( .A(cordic_FSM_state_reg[1]), .B(cordic_FSM_state_reg[0]),
.Y(n4600) );
INVX2TS U4163 ( .A(n4600), .Y(n4650) );
NAND3X1TS U4164 ( .A(n5168), .B(cordic_FSM_state_reg[3]), .C(n4650), .Y(
n3148) );
BUFX4TS U4165 ( .A(n3153), .Y(n3198) );
NOR2X1TS U4166 ( .A(sel_mux_3_reg), .B(n3148), .Y(n3151) );
BUFX4TS U4167 ( .A(n3148), .Y(n3199) );
BUFX3TS U4168 ( .A(n3199), .Y(n3224) );
AOI22X1TS U4169 ( .A0(d_ff_Xn[60]), .A1(n3206), .B0(sign_inv_out[60]), .B1(
n3224), .Y(n3149) );
OAI21XLTS U4170 ( .A0(n2971), .A1(n3198), .B0(n3149), .Y(n1969) );
BUFX4TS U4171 ( .A(n3153), .Y(n3223) );
AOI22X1TS U4172 ( .A0(d_ff_Xn[58]), .A1(n3206), .B0(sign_inv_out[58]), .B1(
n3202), .Y(n3150) );
OAI21XLTS U4173 ( .A0(n2970), .A1(n3223), .B0(n3150), .Y(n1973) );
AOI22X1TS U4174 ( .A0(d_ff_Xn[57]), .A1(n3151), .B0(sign_inv_out[57]), .B1(
n3224), .Y(n3152) );
OAI21XLTS U4175 ( .A0(n2969), .A1(n3223), .B0(n3152), .Y(n1975) );
BUFX4TS U4176 ( .A(n3199), .Y(n3220) );
AOI22X1TS U4177 ( .A0(d_ff_Xn[36]), .A1(n3225), .B0(sign_inv_out[36]), .B1(
n3220), .Y(n3154) );
OAI21XLTS U4178 ( .A0(n5283), .A1(n3153), .B0(n3154), .Y(n2017) );
AOI22X1TS U4179 ( .A0(d_ff_Xn[37]), .A1(n3203), .B0(sign_inv_out[37]), .B1(
n3224), .Y(n3155) );
OAI21XLTS U4180 ( .A0(n5284), .A1(n3153), .B0(n3155), .Y(n2015) );
AOI22X1TS U4181 ( .A0(d_ff_Xn[9]), .A1(n3206), .B0(sign_inv_out[9]), .B1(
n3199), .Y(n3156) );
OAI21XLTS U4182 ( .A0(n5257), .A1(n3198), .B0(n3156), .Y(n2071) );
AOI22X1TS U4183 ( .A0(d_ff_Xn[6]), .A1(n3206), .B0(sign_inv_out[6]), .B1(
n3199), .Y(n3157) );
OAI21XLTS U4184 ( .A0(n5254), .A1(n3198), .B0(n3157), .Y(n2077) );
AOI22X1TS U4185 ( .A0(d_ff_Xn[12]), .A1(n3203), .B0(sign_inv_out[12]), .B1(
n3199), .Y(n3158) );
OAI21XLTS U4186 ( .A0(n5260), .A1(n3198), .B0(n3158), .Y(n2065) );
AOI22X1TS U4187 ( .A0(d_ff_Xn[0]), .A1(n3206), .B0(sign_inv_out[0]), .B1(
n3202), .Y(n3159) );
OAI21XLTS U4188 ( .A0(n5248), .A1(n3198), .B0(n3159), .Y(n2089) );
AOI22X1TS U4189 ( .A0(d_ff_Xn[2]), .A1(n3225), .B0(sign_inv_out[2]), .B1(
n3220), .Y(n3160) );
OAI21XLTS U4190 ( .A0(n5250), .A1(n3198), .B0(n3160), .Y(n2085) );
AOI22X1TS U4191 ( .A0(d_ff_Xn[1]), .A1(n3173), .B0(sign_inv_out[1]), .B1(
n3224), .Y(n3161) );
OAI21XLTS U4192 ( .A0(n5249), .A1(n3198), .B0(n3161), .Y(n2087) );
AOI22X1TS U4193 ( .A0(d_ff_Xn[7]), .A1(n3173), .B0(sign_inv_out[7]), .B1(
n3199), .Y(n3162) );
OAI21XLTS U4194 ( .A0(n5255), .A1(n3198), .B0(n3162), .Y(n2075) );
AOI22X1TS U4195 ( .A0(d_ff_Xn[10]), .A1(n3203), .B0(sign_inv_out[10]), .B1(
n3199), .Y(n3163) );
OAI21XLTS U4196 ( .A0(n5258), .A1(n3198), .B0(n3163), .Y(n2069) );
AOI22X1TS U4197 ( .A0(d_ff_Xn[4]), .A1(n3225), .B0(sign_inv_out[4]), .B1(
n3199), .Y(n3164) );
OAI21XLTS U4198 ( .A0(n5252), .A1(n3198), .B0(n3164), .Y(n2081) );
AOI22X1TS U4199 ( .A0(d_ff_Xn[38]), .A1(n3225), .B0(sign_inv_out[38]), .B1(
n3220), .Y(n3165) );
OAI21XLTS U4200 ( .A0(n5285), .A1(n3153), .B0(n3165), .Y(n2013) );
AOI22X1TS U4201 ( .A0(d_ff_Xn[11]), .A1(n3206), .B0(sign_inv_out[11]), .B1(
n3199), .Y(n3166) );
OAI21XLTS U4202 ( .A0(n5259), .A1(n3198), .B0(n3166), .Y(n2067) );
AOI22X1TS U4203 ( .A0(d_ff_Xn[56]), .A1(n3203), .B0(sign_inv_out[56]), .B1(
n3224), .Y(n3167) );
AOI22X1TS U4204 ( .A0(d_ff_Xn[63]), .A1(n3203), .B0(data_output2_63_), .B1(
n3224), .Y(n3168) );
OAI21XLTS U4205 ( .A0(n5246), .A1(n3198), .B0(n3168), .Y(n1963) );
AOI22X1TS U4206 ( .A0(d_ff_Xn[5]), .A1(n3225), .B0(sign_inv_out[5]), .B1(
n3199), .Y(n3169) );
OAI21XLTS U4207 ( .A0(n5253), .A1(n3198), .B0(n3169), .Y(n2079) );
AOI22X1TS U4208 ( .A0(d_ff_Xn[62]), .A1(n3173), .B0(sign_inv_out[62]), .B1(
n3202), .Y(n3170) );
OAI21XLTS U4209 ( .A0(n5305), .A1(n3198), .B0(n3170), .Y(n1965) );
AOI22X1TS U4210 ( .A0(d_ff_Xn[54]), .A1(n3206), .B0(sign_inv_out[54]), .B1(
n3224), .Y(n3171) );
OAI21XLTS U4211 ( .A0(n5300), .A1(n3223), .B0(n3171), .Y(n1981) );
AOI22X1TS U4212 ( .A0(d_ff_Xn[3]), .A1(n3225), .B0(sign_inv_out[3]), .B1(
n3202), .Y(n3172) );
OAI21XLTS U4213 ( .A0(n5251), .A1(n3198), .B0(n3172), .Y(n2083) );
AOI22X1TS U4214 ( .A0(d_ff_Xn[8]), .A1(n3173), .B0(sign_inv_out[8]), .B1(
n3199), .Y(n3174) );
OAI21XLTS U4215 ( .A0(n5256), .A1(n3198), .B0(n3174), .Y(n2073) );
INVX4TS U4216 ( .A(n2993), .Y(n5395) );
OAI21X1TS U4217 ( .A0(d_ff2_Y[56]), .A1(intadd_372_n1), .B0(n4706), .Y(n4820) );
AOI22X1TS U4218 ( .A0(n4729), .A1(n4824), .B0(d_ff3_sh_y_out[57]), .B1(n4817), .Y(n3175) );
OAI21XLTS U4219 ( .A0(n5244), .A1(n4820), .B0(n3175), .Y(n2098) );
BUFX3TS U4220 ( .A(n3198), .Y(n3205) );
AOI22X1TS U4221 ( .A0(d_ff_Xn[29]), .A1(n3173), .B0(sign_inv_out[29]), .B1(
n3224), .Y(n3176) );
OAI21XLTS U4222 ( .A0(n5276), .A1(n3205), .B0(n3176), .Y(n2031) );
AOI22X1TS U4223 ( .A0(d_ff_Xn[34]), .A1(n3203), .B0(sign_inv_out[34]), .B1(
n3199), .Y(n3177) );
OAI21XLTS U4224 ( .A0(n5281), .A1(n3205), .B0(n3177), .Y(n2021) );
AOI22X1TS U4225 ( .A0(d_ff_Xn[28]), .A1(n3225), .B0(sign_inv_out[28]), .B1(
n3220), .Y(n3178) );
OAI21XLTS U4226 ( .A0(n5275), .A1(n3205), .B0(n3178), .Y(n2033) );
AOI22X1TS U4227 ( .A0(d_ff_Xn[33]), .A1(n3173), .B0(sign_inv_out[33]), .B1(
n3202), .Y(n3179) );
OAI21XLTS U4228 ( .A0(n5280), .A1(n3205), .B0(n3179), .Y(n2023) );
AOI22X1TS U4229 ( .A0(d_ff_Xn[32]), .A1(n3173), .B0(sign_inv_out[32]), .B1(
n3199), .Y(n3180) );
OAI21XLTS U4230 ( .A0(n5279), .A1(n3205), .B0(n3180), .Y(n2025) );
AOI22X1TS U4231 ( .A0(d_ff_Xn[31]), .A1(n3203), .B0(sign_inv_out[31]), .B1(
n3220), .Y(n3181) );
OAI21XLTS U4232 ( .A0(n5278), .A1(n3205), .B0(n3181), .Y(n2027) );
AOI22X1TS U4233 ( .A0(d_ff_Xn[27]), .A1(n3203), .B0(sign_inv_out[27]), .B1(
n3202), .Y(n3182) );
OAI21XLTS U4234 ( .A0(n5274), .A1(n3205), .B0(n3182), .Y(n2035) );
AOI22X1TS U4235 ( .A0(d_ff_Xn[26]), .A1(n3225), .B0(sign_inv_out[26]), .B1(
n3202), .Y(n3183) );
OAI21XLTS U4236 ( .A0(n5273), .A1(n3205), .B0(n3183), .Y(n2037) );
AOI22X1TS U4237 ( .A0(d_ff_Xn[30]), .A1(n3225), .B0(sign_inv_out[30]), .B1(
n3220), .Y(n3184) );
OAI21XLTS U4238 ( .A0(n5277), .A1(n3205), .B0(n3184), .Y(n2029) );
AOI22X1TS U4239 ( .A0(d_ff_Xn[35]), .A1(n3225), .B0(sign_inv_out[35]), .B1(
n3199), .Y(n3185) );
OAI21XLTS U4240 ( .A0(n5282), .A1(n3205), .B0(n3185), .Y(n2019) );
AOI22X1TS U4241 ( .A0(d_ff_Xn[15]), .A1(n3173), .B0(sign_inv_out[15]), .B1(
n3199), .Y(n3186) );
OAI21XLTS U4242 ( .A0(n5263), .A1(n3153), .B0(n3186), .Y(n2059) );
AOI22X1TS U4243 ( .A0(d_ff_Xn[21]), .A1(n3203), .B0(sign_inv_out[21]), .B1(
n3202), .Y(n3187) );
OAI21XLTS U4244 ( .A0(n5269), .A1(n3153), .B0(n3187), .Y(n2047) );
AOI22X1TS U4245 ( .A0(d_ff_Xn[55]), .A1(n3173), .B0(sign_inv_out[55]), .B1(
n3224), .Y(n3188) );
OAI21XLTS U4246 ( .A0(n5301), .A1(n3223), .B0(n3188), .Y(n1979) );
AOI22X1TS U4247 ( .A0(d_ff_Xn[18]), .A1(n3225), .B0(sign_inv_out[18]), .B1(
n3220), .Y(n3189) );
OAI21XLTS U4248 ( .A0(n5266), .A1(n3223), .B0(n3189), .Y(n2053) );
AOI22X1TS U4249 ( .A0(d_ff_Xn[22]), .A1(n3173), .B0(sign_inv_out[22]), .B1(
n3202), .Y(n3190) );
OAI21XLTS U4250 ( .A0(n5270), .A1(n3223), .B0(n3190), .Y(n2045) );
AOI22X1TS U4251 ( .A0(d_ff_Xn[17]), .A1(n3203), .B0(sign_inv_out[17]), .B1(
n3220), .Y(n3191) );
OAI21XLTS U4252 ( .A0(n5265), .A1(n3153), .B0(n3191), .Y(n2055) );
AOI22X1TS U4253 ( .A0(d_ff_Xn[14]), .A1(n3203), .B0(sign_inv_out[14]), .B1(
n3199), .Y(n3192) );
OAI21XLTS U4254 ( .A0(n5262), .A1(n3223), .B0(n3192), .Y(n2061) );
AOI22X1TS U4255 ( .A0(d_ff_Xn[16]), .A1(n3225), .B0(sign_inv_out[16]), .B1(
n3202), .Y(n3193) );
OAI21XLTS U4256 ( .A0(n5264), .A1(n3223), .B0(n3193), .Y(n2057) );
AOI22X1TS U4257 ( .A0(d_ff_Xn[23]), .A1(n3225), .B0(sign_inv_out[23]), .B1(
n3220), .Y(n3194) );
OAI21XLTS U4258 ( .A0(n5271), .A1(n3153), .B0(n3194), .Y(n2043) );
AOI22X1TS U4259 ( .A0(d_ff_Xn[20]), .A1(n3173), .B0(sign_inv_out[20]), .B1(
n3202), .Y(n3195) );
OAI21XLTS U4260 ( .A0(n5268), .A1(n3223), .B0(n3195), .Y(n2049) );
AOI22X1TS U4261 ( .A0(d_ff_Xn[19]), .A1(n3173), .B0(sign_inv_out[19]), .B1(
n3220), .Y(n3196) );
OAI21XLTS U4262 ( .A0(n5267), .A1(n3153), .B0(n3196), .Y(n2051) );
AOI22X1TS U4263 ( .A0(d_ff_Xn[61]), .A1(n3206), .B0(sign_inv_out[61]), .B1(
n3224), .Y(n3197) );
OAI21XLTS U4264 ( .A0(n5304), .A1(n3198), .B0(n3197), .Y(n1967) );
AOI22X1TS U4265 ( .A0(d_ff_Xn[13]), .A1(n3203), .B0(sign_inv_out[13]), .B1(
n3199), .Y(n3200) );
OAI21XLTS U4266 ( .A0(n5261), .A1(n3205), .B0(n3200), .Y(n2063) );
AOI22X1TS U4267 ( .A0(d_ff_Xn[25]), .A1(n3173), .B0(sign_inv_out[25]), .B1(
n3220), .Y(n3201) );
OAI21XLTS U4268 ( .A0(n5245), .A1(n3205), .B0(n3201), .Y(n2039) );
AOI22X1TS U4269 ( .A0(d_ff_Xn[24]), .A1(n3206), .B0(sign_inv_out[24]), .B1(
n3202), .Y(n3204) );
OAI21XLTS U4270 ( .A0(n5272), .A1(n3205), .B0(n3204), .Y(n2041) );
AOI22X1TS U4271 ( .A0(d_ff_Xn[52]), .A1(n3225), .B0(sign_inv_out[52]), .B1(
n3220), .Y(n3207) );
OAI21XLTS U4272 ( .A0(n2972), .A1(n3223), .B0(n3207), .Y(n1985) );
AOI22X1TS U4273 ( .A0(d_ff_Xn[50]), .A1(n3173), .B0(sign_inv_out[50]), .B1(
n3220), .Y(n3208) );
OAI21XLTS U4274 ( .A0(n5297), .A1(n3223), .B0(n3208), .Y(n1989) );
AOI22X1TS U4275 ( .A0(d_ff_Xn[47]), .A1(n3203), .B0(sign_inv_out[47]), .B1(
n3202), .Y(n3209) );
OAI21XLTS U4276 ( .A0(n5294), .A1(n3153), .B0(n3209), .Y(n1995) );
AOI22X1TS U4277 ( .A0(d_ff_Xn[46]), .A1(n3225), .B0(sign_inv_out[46]), .B1(
n3202), .Y(n3210) );
OAI21XLTS U4278 ( .A0(n5293), .A1(n3153), .B0(n3210), .Y(n1997) );
AOI22X1TS U4279 ( .A0(d_ff_Xn[49]), .A1(n3225), .B0(sign_inv_out[49]), .B1(
n3220), .Y(n3211) );
OAI21XLTS U4280 ( .A0(n5296), .A1(n3223), .B0(n3211), .Y(n1991) );
AOI22X1TS U4281 ( .A0(d_ff_Xn[48]), .A1(n3173), .B0(sign_inv_out[48]), .B1(
n3202), .Y(n3212) );
AOI22X1TS U4282 ( .A0(d_ff_Xn[53]), .A1(n3203), .B0(sign_inv_out[53]), .B1(
n3224), .Y(n3213) );
OAI21XLTS U4283 ( .A0(n5299), .A1(n3223), .B0(n3213), .Y(n1983) );
AOI22X1TS U4284 ( .A0(d_ff_Xn[51]), .A1(n3225), .B0(sign_inv_out[51]), .B1(
n3220), .Y(n3214) );
OAI21XLTS U4285 ( .A0(n5298), .A1(n3223), .B0(n3214), .Y(n1987) );
AOI22X1TS U4286 ( .A0(d_ff_Xn[42]), .A1(n3225), .B0(sign_inv_out[42]), .B1(
n3220), .Y(n3215) );
OAI21XLTS U4287 ( .A0(n5289), .A1(n3153), .B0(n3215), .Y(n2005) );
AOI22X1TS U4288 ( .A0(d_ff_Xn[44]), .A1(n3173), .B0(sign_inv_out[44]), .B1(
n3202), .Y(n3216) );
OAI21XLTS U4289 ( .A0(n5291), .A1(n3153), .B0(n3216), .Y(n2001) );
AOI22X1TS U4290 ( .A0(d_ff_Xn[41]), .A1(n3173), .B0(sign_inv_out[41]), .B1(
n3202), .Y(n3217) );
AOI22X1TS U4291 ( .A0(d_ff_Xn[43]), .A1(n3203), .B0(sign_inv_out[43]), .B1(
n3220), .Y(n3218) );
OAI21XLTS U4292 ( .A0(n5290), .A1(n3153), .B0(n3218), .Y(n2003) );
AOI22X1TS U4293 ( .A0(d_ff_Xn[45]), .A1(n3225), .B0(sign_inv_out[45]), .B1(
n3202), .Y(n3219) );
OAI21XLTS U4294 ( .A0(n5292), .A1(n3153), .B0(n3219), .Y(n1999) );
AOI22X1TS U4295 ( .A0(d_ff_Xn[40]), .A1(n3203), .B0(sign_inv_out[40]), .B1(
n3220), .Y(n3221) );
OAI21XLTS U4296 ( .A0(n5287), .A1(n3153), .B0(n3221), .Y(n2009) );
AOI22X1TS U4297 ( .A0(d_ff_Xn[59]), .A1(n3203), .B0(sign_inv_out[59]), .B1(
n3224), .Y(n3222) );
OAI21XLTS U4298 ( .A0(n5303), .A1(n3223), .B0(n3222), .Y(n1971) );
AOI22X1TS U4299 ( .A0(d_ff_Xn[39]), .A1(n3225), .B0(sign_inv_out[39]), .B1(
n3224), .Y(n3226) );
OAI21XLTS U4300 ( .A0(n5286), .A1(n3153), .B0(n3226), .Y(n2011) );
NOR2X1TS U4301 ( .A(n3228), .B(n3227), .Y(n4636) );
AOI211XLTS U4302 ( .A0(n3228), .A1(n3227), .B0(n4647), .C0(n4636), .Y(n2923)
);
AOI21X1TS U4303 ( .A0(n5049), .A1(n3228), .B0(n5118), .Y(n3230) );
NOR2X2TS U4304 ( .A(cont_iter_out[0]), .B(n4659), .Y(n4702) );
AOI21X1TS U4305 ( .A0(d_ff3_LUT_out[3]), .A1(n4817), .B0(n4702), .Y(n3229)
);
OAI31X1TS U4306 ( .A0(n4660), .A1(n3230), .A2(n4818), .B0(n3229), .Y(n2798)
);
INVX2TS U4307 ( .A(n4659), .Y(n4694) );
OAI21X1TS U4308 ( .A0(cont_iter_out[2]), .A1(cont_iter_out[1]), .B0(n4694),
.Y(n4672) );
OAI21X1TS U4309 ( .A0(n4660), .A1(n5056), .B0(n4655), .Y(n4661) );
OR2X1TS U4310 ( .A(n3231), .B(n4726), .Y(n4674) );
OR2X1TS U4311 ( .A(n4661), .B(n4674), .Y(n4707) );
OAI211XLTS U4312 ( .A0(n4729), .A1(n5311), .B0(n4672), .C0(n4707), .Y(n2814)
);
INVX2TS U4313 ( .A(n4660), .Y(n4673) );
OA21XLTS U4314 ( .A0(n4659), .A1(n4673), .B0(n3232), .Y(n4695) );
NAND3XLTS U4315 ( .A(cont_iter_out[1]), .B(cont_iter_out[3]), .C(n4706), .Y(
n4704) );
OAI211XLTS U4316 ( .A0(n4829), .A1(n5310), .B0(n4695), .C0(n4704), .Y(n2828)
);
INVX4TS U4317 ( .A(n4803), .Y(n3306) );
NOR2XLTS U4318 ( .A(sel_mux_1_reg), .B(n4806), .Y(n3233) );
BUFX4TS U4319 ( .A(n3233), .Y(n3254) );
CLKBUFX2TS U4320 ( .A(n4710), .Y(n4713) );
INVX2TS U4321 ( .A(n3234), .Y(n2276) );
INVX4TS U4322 ( .A(n4803), .Y(n3294) );
INVX2TS U4323 ( .A(n3235), .Y(n2282) );
INVX2TS U4324 ( .A(n3236), .Y(n2224) );
INVX2TS U4325 ( .A(n3237), .Y(n2274) );
INVX4TS U4326 ( .A(n4803), .Y(n4711) );
INVX2TS U4327 ( .A(n3238), .Y(n2279) );
INVX2TS U4328 ( .A(n3239), .Y(n2273) );
INVX2TS U4329 ( .A(n3240), .Y(n2281) );
INVX2TS U4330 ( .A(n3241), .Y(n2284) );
INVX2TS U4331 ( .A(n3242), .Y(n2225) );
AOI222X1TS U4332 ( .A0(n3306), .A1(d_ff2_Z[7]), .B0(n3254), .B1(d_ff1_Z[7]),
.C0(d_ff_Zn[7]), .C1(n3291), .Y(n3243) );
INVX2TS U4333 ( .A(n3243), .Y(n2277) );
INVX2TS U4334 ( .A(n3244), .Y(n2275) );
INVX2TS U4335 ( .A(n3245), .Y(n2280) );
INVX2TS U4336 ( .A(n3246), .Y(n2283) );
INVX2TS U4337 ( .A(n3247), .Y(n2272) );
INVX2TS U4338 ( .A(n3248), .Y(n2278) );
INVX2TS U4339 ( .A(n3249), .Y(n2226) );
BUFX4TS U4340 ( .A(n3254), .Y(n3298) );
AOI222X1TS U4341 ( .A0(n3306), .A1(d_ff2_Z[26]), .B0(n3298), .B1(d_ff1_Z[26]), .C0(d_ff_Zn[26]), .C1(n3291), .Y(n3250) );
INVX2TS U4342 ( .A(n3250), .Y(n2258) );
BUFX4TS U4343 ( .A(n3254), .Y(n3302) );
INVX2TS U4344 ( .A(n3251), .Y(n2238) );
AOI222X1TS U4345 ( .A0(n4711), .A1(d_ff2_Z[55]), .B0(n3302), .B1(d_ff1_Z[55]), .C0(d_ff_Zn[55]), .C1(n3291), .Y(n3252) );
INVX2TS U4346 ( .A(n3252), .Y(n2229) );
INVX4TS U4347 ( .A(n4713), .Y(n4807) );
INVX2TS U4348 ( .A(n3253), .Y(n2250) );
BUFX4TS U4349 ( .A(n3254), .Y(n3305) );
AOI222X1TS U4350 ( .A0(n3306), .A1(d_ff2_Z[14]), .B0(n3305), .B1(d_ff1_Z[14]), .C0(d_ff_Zn[14]), .C1(n3291), .Y(n3255) );
INVX2TS U4351 ( .A(n3255), .Y(n2270) );
INVX4TS U4352 ( .A(n4803), .Y(n3303) );
INVX4TS U4353 ( .A(n4713), .Y(n4798) );
INVX2TS U4354 ( .A(n3256), .Y(n2261) );
INVX2TS U4355 ( .A(n3257), .Y(n2240) );
AOI222X1TS U4356 ( .A0(n3306), .A1(d_ff2_Z[43]), .B0(n3302), .B1(d_ff1_Z[43]), .C0(d_ff_Zn[43]), .C1(n3291), .Y(n3258) );
INVX2TS U4357 ( .A(n3258), .Y(n2241) );
INVX2TS U4358 ( .A(n3259), .Y(n2268) );
INVX2TS U4359 ( .A(n3260), .Y(n2230) );
INVX2TS U4360 ( .A(n3261), .Y(n2251) );
INVX2TS U4361 ( .A(n3262), .Y(n2265) );
AOI222X1TS U4362 ( .A0(n4806), .A1(d_ff2_Z[53]), .B0(n3298), .B1(d_ff1_Z[53]), .C0(d_ff_Zn[53]), .C1(n3291), .Y(n3263) );
INVX2TS U4363 ( .A(n3263), .Y(n2231) );
AOI222X1TS U4364 ( .A0(n3306), .A1(d_ff2_Z[30]), .B0(n3298), .B1(d_ff1_Z[30]), .C0(d_ff_Zn[30]), .C1(n3291), .Y(n3264) );
INVX2TS U4365 ( .A(n3264), .Y(n2254) );
INVX2TS U4366 ( .A(n3265), .Y(n2236) );
INVX2TS U4367 ( .A(n3266), .Y(n2223) );
AOI222X1TS U4368 ( .A0(n4711), .A1(d_ff2_Z[37]), .B0(n3298), .B1(d_ff1_Z[37]), .C0(d_ff_Zn[37]), .C1(n3291), .Y(n3267) );
INVX2TS U4369 ( .A(n3267), .Y(n2247) );
INVX2TS U4370 ( .A(n3268), .Y(n2228) );
AOI222X1TS U4371 ( .A0(n3303), .A1(d_ff2_Z[25]), .B0(n3305), .B1(d_ff1_Z[25]), .C0(d_ff_Zn[25]), .C1(n3300), .Y(n3269) );
INVX2TS U4372 ( .A(n3269), .Y(n2259) );
INVX2TS U4373 ( .A(n3270), .Y(n2233) );
INVX2TS U4374 ( .A(n3271), .Y(n2249) );
INVX2TS U4375 ( .A(n3272), .Y(n2237) );
INVX2TS U4376 ( .A(n3273), .Y(n2253) );
INVX2TS U4377 ( .A(n3274), .Y(n2222) );
INVX2TS U4378 ( .A(n3275), .Y(n2242) );
INVX2TS U4379 ( .A(n3276), .Y(n2256) );
AOI222X1TS U4380 ( .A0(n3306), .A1(d_ff2_Z[32]), .B0(n3298), .B1(d_ff1_Z[32]), .C0(d_ff_Zn[32]), .C1(n3291), .Y(n3277) );
INVX2TS U4381 ( .A(n3277), .Y(n2252) );
INVX2TS U4382 ( .A(n3278), .Y(n2245) );
INVX2TS U4383 ( .A(n3279), .Y(n2266) );
INVX2TS U4384 ( .A(n3280), .Y(n2239) );
INVX2TS U4385 ( .A(n3281), .Y(n2248) );
AOI222X1TS U4386 ( .A0(n3303), .A1(d_ff2_Z[40]), .B0(n3302), .B1(d_ff1_Z[40]), .C0(d_ff_Zn[40]), .C1(n4798), .Y(n3282) );
INVX2TS U4387 ( .A(n3282), .Y(n2244) );
AOI222X1TS U4388 ( .A0(n3303), .A1(d_ff2_Z[22]), .B0(n3305), .B1(d_ff1_Z[22]), .C0(d_ff_Zn[22]), .C1(n3300), .Y(n3283) );
INVX2TS U4389 ( .A(n3283), .Y(n2262) );
AOI222X1TS U4390 ( .A0(n3306), .A1(d_ff2_Z[27]), .B0(n3298), .B1(d_ff1_Z[27]), .C0(d_ff_Zn[27]), .C1(n3291), .Y(n3284) );
INVX2TS U4391 ( .A(n3284), .Y(n2257) );
INVX2TS U4392 ( .A(n3286), .Y(n2234) );
INVX2TS U4393 ( .A(n3287), .Y(n2227) );
INVX2TS U4394 ( .A(n3288), .Y(n2232) );
AOI222X1TS U4395 ( .A0(n3294), .A1(d_ff2_Z[63]), .B0(n3305), .B1(d_ff1_Z[63]), .C0(d_ff_Zn[63]), .C1(n3300), .Y(n3289) );
INVX2TS U4396 ( .A(n3289), .Y(n2221) );
AOI222X1TS U4397 ( .A0(n3303), .A1(d_ff2_Z[17]), .B0(n3305), .B1(d_ff1_Z[17]), .C0(d_ff_Zn[17]), .C1(n4807), .Y(n3290) );
INVX2TS U4398 ( .A(n3290), .Y(n2267) );
AOI222X1TS U4399 ( .A0(n3303), .A1(d_ff2_Z[41]), .B0(n3302), .B1(d_ff1_Z[41]), .C0(d_ff_Zn[41]), .C1(n3291), .Y(n3292) );
INVX2TS U4400 ( .A(n3292), .Y(n2243) );
AOI222X1TS U4401 ( .A0(n3306), .A1(d_ff2_Z[13]), .B0(n3305), .B1(d_ff1_Z[13]), .C0(d_ff_Zn[13]), .C1(n4798), .Y(n3293) );
INVX2TS U4402 ( .A(n3293), .Y(n2271) );
INVX2TS U4403 ( .A(n3295), .Y(n2269) );
AOI222X1TS U4404 ( .A0(n4711), .A1(d_ff2_Z[20]), .B0(n3305), .B1(d_ff1_Z[20]), .C0(d_ff_Zn[20]), .C1(n3300), .Y(n3296) );
INVX2TS U4405 ( .A(n3296), .Y(n2264) );
AOI222X1TS U4406 ( .A0(n4711), .A1(d_ff2_Z[38]), .B0(n3298), .B1(d_ff1_Z[38]), .C0(d_ff_Zn[38]), .C1(n4798), .Y(n3297) );
INVX2TS U4407 ( .A(n3297), .Y(n2246) );
INVX2TS U4408 ( .A(n3299), .Y(n2255) );
AOI222X1TS U4409 ( .A0(n3306), .A1(d_ff2_Z[21]), .B0(n3305), .B1(d_ff1_Z[21]), .C0(d_ff_Zn[21]), .C1(n4807), .Y(n3301) );
INVX2TS U4410 ( .A(n3301), .Y(n2263) );
AOI222X1TS U4411 ( .A0(n3303), .A1(d_ff2_Z[49]), .B0(n3302), .B1(d_ff1_Z[49]), .C0(d_ff_Zn[49]), .C1(n4807), .Y(n3304) );
INVX2TS U4412 ( .A(n3304), .Y(n2235) );
INVX2TS U4413 ( .A(n3307), .Y(n2260) );
AOI22X1TS U4414 ( .A0(add_subt_module_LZA_output[2]), .A1(n3124), .B0(n2953),
.B1(add_subt_module_exp_oper_result[2]), .Y(n3312) );
BUFX3TS U4415 ( .A(n4417), .Y(n4451) );
NAND2X1TS U4416 ( .A(n3124), .B(add_subt_module_LZA_output[0]), .Y(n3937) );
INVX2TS U4417 ( .A(n3937), .Y(n3308) );
OAI32X4TS U4418 ( .A0(n3308), .A1(add_subt_module_FSM_selector_B[1]), .A2(
add_subt_module_exp_oper_result[0]), .B0(n5134), .B1(n3308), .Y(n4444)
);
INVX2TS U4419 ( .A(n3309), .Y(n4559) );
NOR2XLTS U4420 ( .A(add_subt_module_FS_Module_state_reg[3]), .B(
add_subt_module_add_overflow_flag), .Y(n3310) );
NAND2X1TS U4421 ( .A(n4623), .B(n3310), .Y(n3311) );
OA22X1TS U4422 ( .A0(n4337), .A1(add_subt_module_Add_Subt_result[54]), .B0(
add_subt_module_Add_Subt_result[0]), .B1(n4583), .Y(n3642) );
AOI22X1TS U4423 ( .A0(n4585), .A1(n3642), .B0(n3643), .B1(n3309), .Y(n4336)
);
INVX4TS U4424 ( .A(n3312), .Y(n4503) );
NAND2X1TS U4425 ( .A(n3643), .B(n4503), .Y(n3644) );
OAI21XLTS U4426 ( .A0(n4592), .A1(n4336), .B0(n3644), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[54]) );
NAND2X2TS U4427 ( .A(n4612), .B(n3317), .Y(n1959) );
INVX2TS U4428 ( .A(r_mode[0]), .Y(n3313) );
OAI22X1TS U4429 ( .A0(n3313), .A1(add_subt_module_sign_final_result), .B0(
add_subt_module_Sgf_normalized_result[0]), .B1(
add_subt_module_Sgf_normalized_result[1]), .Y(n3315) );
NOR2XLTS U4430 ( .A(r_mode[0]), .B(r_mode[1]), .Y(n3314) );
NOR2XLTS U4431 ( .A(n5120), .B(n4607), .Y(n3316) );
NAND2X1TS U4432 ( .A(n3317), .B(n3316), .Y(n4032) );
NOR2X1TS U4433 ( .A(n4600), .B(n3914), .Y(n4598) );
NAND4X1TS U4434 ( .A(add_subt_module_FS_Module_state_reg[2]), .B(
add_subt_module_FS_Module_state_reg[1]), .C(n3906), .D(n4631), .Y(
n4629) );
OAI21X1TS U4435 ( .A0(n4598), .A1(n1959), .B0(n4629), .Y(n4613) );
AOI22X1TS U4436 ( .A0(n5173), .A1(n2986), .B0(n5178), .B1(
add_subt_module_intDY[14]), .Y(n3318) );
AOI221X1TS U4437 ( .A0(add_subt_module_intDX[13]), .A1(n5180), .B0(n5181),
.B1(add_subt_module_intDY[13]), .C0(n3319), .Y(n3333) );
OAI22X1TS U4438 ( .A0(n5195), .A1(n2987), .B0(n5074), .B1(
add_subt_module_intDY[38]), .Y(n3320) );
AOI221X1TS U4439 ( .A0(n5195), .A1(n2987), .B0(add_subt_module_intDY[38]),
.B1(n5074), .C0(n3320), .Y(n3332) );
OAI22X1TS U4440 ( .A0(n5197), .A1(add_subt_module_intDY[4]), .B0(n5068),
.B1(add_subt_module_intDX[53]), .Y(n3321) );
AOI221X1TS U4441 ( .A0(n5197), .A1(add_subt_module_intDY[4]), .B0(
add_subt_module_intDX[53]), .B1(n5068), .C0(n3321), .Y(n3331) );
AOI22X1TS U4442 ( .A0(n5147), .A1(add_subt_module_intDY[1]), .B0(n5169),
.B1(add_subt_module_intDX[61]), .Y(n3322) );
AOI22X1TS U4443 ( .A0(n5144), .A1(add_subt_module_intDY[39]), .B0(n5177),
.B1(add_subt_module_intDY[23]), .Y(n3323) );
AOI22X1TS U4444 ( .A0(n5172), .A1(add_subt_module_intDY[11]), .B0(n5163),
.B1(add_subt_module_intDX[52]), .Y(n3324) );
AOI22X1TS U4445 ( .A0(n5067), .A1(add_subt_module_intDX[57]), .B0(n5153),
.B1(add_subt_module_intDY[37]), .Y(n3325) );
OAI221XLTS U4446 ( .A0(n5067), .A1(add_subt_module_intDX[57]), .B0(n5153),
.B1(add_subt_module_intDY[37]), .C0(n3325), .Y(n3326) );
NOR4X1TS U4447 ( .A(n3329), .B(n3328), .C(n3327), .D(n3326), .Y(n3330) );
NAND4XLTS U4448 ( .A(n3333), .B(n3332), .C(n3331), .D(n3330), .Y(n3389) );
OAI22X1TS U4449 ( .A0(n5193), .A1(add_subt_module_intDX[54]), .B0(n5075),
.B1(n2988), .Y(n3334) );
AOI221X1TS U4450 ( .A0(n5193), .A1(add_subt_module_intDX[54]), .B0(n2988),
.B1(n5075), .C0(n3334), .Y(n3341) );
OAI22X1TS U4451 ( .A0(n5190), .A1(add_subt_module_intDY[45]), .B0(n5199),
.B1(add_subt_module_intDY[51]), .Y(n3335) );
OAI22X1TS U4452 ( .A0(n5073), .A1(add_subt_module_intDX[59]), .B0(n5198),
.B1(add_subt_module_intDY[48]), .Y(n3336) );
AOI221X1TS U4453 ( .A0(n5073), .A1(add_subt_module_intDX[59]), .B0(
add_subt_module_intDY[48]), .B1(n5198), .C0(n3336), .Y(n3339) );
OAI22X1TS U4454 ( .A0(n5196), .A1(add_subt_module_intDY[12]), .B0(n5186),
.B1(add_subt_module_intDY[18]), .Y(n3337) );
NAND4XLTS U4455 ( .A(n3341), .B(n3340), .C(n3339), .D(n3338), .Y(n3388) );
OAI22X1TS U4456 ( .A0(n5185), .A1(add_subt_module_intDX[60]), .B0(n5188),
.B1(add_subt_module_intDY[3]), .Y(n3342) );
AOI221X1TS U4457 ( .A0(n5185), .A1(add_subt_module_intDX[60]), .B0(
add_subt_module_intDY[3]), .B1(n5188), .C0(n3342), .Y(n3349) );
OAI22X1TS U4458 ( .A0(n5191), .A1(add_subt_module_intDY[35]), .B0(n5187),
.B1(add_subt_module_intDY[8]), .Y(n3343) );
OAI22X1TS U4459 ( .A0(n5194), .A1(add_subt_module_intDY[29]), .B0(n5201),
.B1(add_subt_module_intDX[0]), .Y(n3344) );
OAI22X1TS U4460 ( .A0(n5192), .A1(add_subt_module_intDY[25]), .B0(n5189),
.B1(add_subt_module_intDY[2]), .Y(n3345) );
NAND4XLTS U4461 ( .A(n3349), .B(n3348), .C(n3347), .D(n3346), .Y(n3387) );
AOI22X1TS U4462 ( .A0(n5146), .A1(add_subt_module_intDY[16]), .B0(n5174),
.B1(add_subt_module_intDY[43]), .Y(n3350) );
AOI22X1TS U4463 ( .A0(n5069), .A1(add_subt_module_intDY[31]), .B0(n5150),
.B1(add_subt_module_intDX[56]), .Y(n3351) );
AOI22X1TS U4464 ( .A0(n5072), .A1(add_subt_module_intDY[19]), .B0(n5155),
.B1(add_subt_module_intDY[5]), .Y(n3352) );
AOI22X1TS U4465 ( .A0(n5165), .A1(add_subt_module_intDY[20]), .B0(n5070),
.B1(add_subt_module_intDY[50]), .Y(n3353) );
NOR4X1TS U4466 ( .A(n3357), .B(n3356), .C(n3355), .D(n3354), .Y(n3385) );
AOI22X1TS U4467 ( .A0(n5061), .A1(add_subt_module_intDY[47]), .B0(n5156),
.B1(add_subt_module_intDY[10]), .Y(n3358) );
AOI22X1TS U4468 ( .A0(n5158), .A1(add_subt_module_intDY[49]), .B0(n5164),
.B1(add_subt_module_intDY[28]), .Y(n3359) );
AOI22X1TS U4469 ( .A0(n5170), .A1(add_subt_module_intDY[36]), .B0(n5141),
.B1(add_subt_module_intDX[58]), .Y(n3360) );
AOI22X1TS U4470 ( .A0(n5143), .A1(add_subt_module_intDY[44]), .B0(n5175),
.B1(add_subt_module_intDY[26]), .Y(n3361) );
NOR4X1TS U4471 ( .A(n3365), .B(n3364), .C(n3363), .D(n3362), .Y(n3384) );
AOI22X1TS U4472 ( .A0(n5148), .A1(add_subt_module_intDX[55]), .B0(n5065),
.B1(add_subt_module_intDY[34]), .Y(n3366) );
AOI22X1TS U4473 ( .A0(n5066), .A1(n2985), .B0(n5152), .B1(
add_subt_module_intDY[40]), .Y(n3367) );
AOI22X1TS U4474 ( .A0(n5145), .A1(add_subt_module_intDY[6]), .B0(n5157),
.B1(add_subt_module_intDY[41]), .Y(n3368) );
AOI22X1TS U4475 ( .A0(n5162), .A1(add_subt_module_intDY[21]), .B0(n5151),
.B1(add_subt_module_intDY[46]), .Y(n3369) );
NOR4X1TS U4476 ( .A(n3373), .B(n3372), .C(n3371), .D(n3370), .Y(n3383) );
AOI22X1TS U4477 ( .A0(n5064), .A1(add_subt_module_intDY[42]), .B0(n5154),
.B1(add_subt_module_intDY[9]), .Y(n3374) );
AOI22X1TS U4478 ( .A0(n5149), .A1(add_subt_module_intDY[7]), .B0(n5071),
.B1(add_subt_module_intDY[27]), .Y(n3375) );
AOI22X1TS U4479 ( .A0(n5171), .A1(add_subt_module_intDY[33]), .B0(n5142),
.B1(add_subt_module_intDX[62]), .Y(n3376) );
AOI22X1TS U4480 ( .A0(n5062), .A1(add_subt_module_intDY[15]), .B0(n5176),
.B1(add_subt_module_intDY[17]), .Y(n3377) );
NOR4X1TS U4481 ( .A(n3381), .B(n3380), .C(n3379), .D(n3378), .Y(n3382) );
NAND4XLTS U4482 ( .A(n3385), .B(n3384), .C(n3383), .D(n3382), .Y(n3386) );
CLKXOR2X2TS U4483 ( .A(n4029), .B(add_subt_module_intDX[63]), .Y(n4608) );
AND3X1TS U4484 ( .A(n4609), .B(n3535), .C(n4608), .Y(n4626) );
NOR4X1TS U4485 ( .A(n4611), .B(n4626), .C(n4772), .D(n4211), .Y(n3390) );
OAI211XLTS U4486 ( .A0(n4621), .A1(n4032), .B0(n3391), .C0(n3390), .Y(n2930)
);
NOR2XLTS U4487 ( .A(n5125), .B(add_subt_module_intDY[53]), .Y(n3392) );
OAI22X1TS U4488 ( .A0(n5058), .A1(add_subt_module_intDY[55]), .B0(
add_subt_module_intDY[54]), .B1(n5126), .Y(n3511) );
NOR2BX1TS U4489 ( .AN(add_subt_module_intDX[56]), .B(
add_subt_module_intDY[56]), .Y(n3393) );
NOR2X1TS U4490 ( .A(n5131), .B(add_subt_module_intDY[57]), .Y(n3465) );
NAND2X1TS U4491 ( .A(n5169), .B(add_subt_module_intDX[61]), .Y(n3471) );
OAI211X1TS U4492 ( .A0(add_subt_module_intDY[60]), .A1(n5130), .B0(n3475),
.C0(n3471), .Y(n3477) );
OAI21X1TS U4493 ( .A0(add_subt_module_intDY[58]), .A1(n5059), .B0(n3467),
.Y(n3469) );
NOR2X1TS U4494 ( .A(n5158), .B(add_subt_module_intDY[49]), .Y(n3514) );
OAI21X1TS U4495 ( .A0(add_subt_module_intDY[50]), .A1(n5070), .B0(n3516),
.Y(n3520) );
AOI211X1TS U4496 ( .A0(add_subt_module_intDX[48]), .A1(n5235), .B0(n3514),
.C0(n3520), .Y(n3394) );
NAND3X1TS U4497 ( .A(n3513), .B(n3522), .C(n3394), .Y(n3530) );
NOR2BX1TS U4498 ( .AN(add_subt_module_intDX[39]), .B(
add_subt_module_intDY[39]), .Y(n3505) );
AOI21X1TS U4499 ( .A0(add_subt_module_intDX[38]), .A1(n5129), .B0(n3505),
.Y(n3504) );
NAND2X1TS U4500 ( .A(n5132), .B(add_subt_module_intDX[37]), .Y(n3493) );
OAI211X1TS U4501 ( .A0(add_subt_module_intDY[36]), .A1(n5170), .B0(n3504),
.C0(n3493), .Y(n3495) );
NOR2X1TS U4502 ( .A(n5190), .B(add_subt_module_intDY[45]), .Y(n3479) );
OAI21X1TS U4503 ( .A0(add_subt_module_intDY[46]), .A1(n5151), .B0(n3478),
.Y(n3488) );
OA22X1TS U4504 ( .A0(n5064), .A1(add_subt_module_intDY[42]), .B0(n5174),
.B1(add_subt_module_intDY[43]), .Y(n3484) );
NAND4XLTS U4505 ( .A(n3486), .B(n3484), .C(n3396), .D(n3395), .Y(n3528) );
OA22X1TS U4506 ( .A0(n5065), .A1(add_subt_module_intDY[34]), .B0(n5191),
.B1(add_subt_module_intDY[35]), .Y(n3499) );
OAI211XLTS U4507 ( .A0(n5171), .A1(add_subt_module_intDY[33]), .B0(n3397),
.C0(n3499), .Y(n3398) );
NOR4X1TS U4508 ( .A(n3530), .B(n3495), .C(n3528), .D(n3398), .Y(n3534) );
OA22X1TS U4509 ( .A0(n5173), .A1(n2986), .B0(n5069), .B1(
add_subt_module_intDY[31]), .Y(n3409) );
OAI21XLTS U4510 ( .A0(add_subt_module_intDY[29]), .A1(n5194), .B0(
add_subt_module_intDY[28]), .Y(n3399) );
OAI2BB2XLTS U4511 ( .B0(add_subt_module_intDX[28]), .B1(n3399), .A0N(
add_subt_module_intDY[29]), .A1N(n5194), .Y(n3408) );
OAI21X1TS U4512 ( .A0(add_subt_module_intDY[26]), .A1(n5175), .B0(n3402),
.Y(n3460) );
NOR2X1TS U4513 ( .A(n5192), .B(add_subt_module_intDY[25]), .Y(n3457) );
NOR2XLTS U4514 ( .A(n3457), .B(add_subt_module_intDX[24]), .Y(n3401) );
AOI22X1TS U4515 ( .A0(n3401), .A1(n2988), .B0(add_subt_module_intDY[25]),
.B1(n5192), .Y(n3404) );
OAI32X1TS U4516 ( .A0(n3460), .A1(n3459), .A2(n3404), .B0(n3403), .B1(n3459),
.Y(n3407) );
OAI21XLTS U4517 ( .A0(add_subt_module_intDY[31]), .A1(n5069), .B0(n2986),
.Y(n3405) );
OAI2BB2XLTS U4518 ( .B0(add_subt_module_intDX[30]), .B1(n3405), .A0N(
add_subt_module_intDY[31]), .A1N(n5069), .Y(n3406) );
AOI211X1TS U4519 ( .A0(n3409), .A1(n3408), .B0(n3407), .C0(n3406), .Y(n3464)
);
OA22X1TS U4520 ( .A0(n5066), .A1(n2985), .B0(n5177), .B1(
add_subt_module_intDY[23]), .Y(n3456) );
OA22X1TS U4521 ( .A0(n5178), .A1(add_subt_module_intDY[14]), .B0(n5062),
.B1(add_subt_module_intDY[15]), .Y(n3437) );
NAND2BXLTS U4522 ( .AN(add_subt_module_intDY[13]), .B(
add_subt_module_intDX[13]), .Y(n3411) );
OAI2BB1X1TS U4523 ( .A0N(n5133), .A1N(add_subt_module_intDX[5]), .B0(
add_subt_module_intDY[4]), .Y(n3412) );
OAI22X1TS U4524 ( .A0(add_subt_module_intDX[4]), .A1(n3412), .B0(n5133),
.B1(add_subt_module_intDX[5]), .Y(n3423) );
OAI2BB1X1TS U4525 ( .A0N(n5138), .A1N(add_subt_module_intDX[7]), .B0(
add_subt_module_intDY[6]), .Y(n3413) );
OAI22X1TS U4526 ( .A0(add_subt_module_intDX[6]), .A1(n3413), .B0(n5138),
.B1(add_subt_module_intDX[7]), .Y(n3422) );
AOI2BB2XLTS U4527 ( .B0(add_subt_module_intDX[1]), .B1(n5119), .A0N(
add_subt_module_intDY[0]), .A1N(n3414), .Y(n3415) );
OAI211XLTS U4528 ( .A0(n5188), .A1(add_subt_module_intDY[3]), .B0(n3416),
.C0(n3415), .Y(n3419) );
OAI21XLTS U4529 ( .A0(add_subt_module_intDY[3]), .A1(n5188), .B0(
add_subt_module_intDY[2]), .Y(n3417) );
AOI2BB2XLTS U4530 ( .B0(add_subt_module_intDY[3]), .B1(n5188), .A0N(
add_subt_module_intDX[2]), .A1N(n3417), .Y(n3418) );
AOI222X1TS U4531 ( .A0(add_subt_module_intDX[4]), .A1(n5060), .B0(
add_subt_module_intDX[5]), .B1(n5133), .C0(n3419), .C1(n3418), .Y(
n3421) );
AOI22X1TS U4532 ( .A0(add_subt_module_intDX[7]), .A1(n5138), .B0(
add_subt_module_intDX[6]), .B1(n5063), .Y(n3420) );
OAI32X1TS U4533 ( .A0(n3423), .A1(n3422), .A2(n3421), .B0(n3420), .B1(n3422),
.Y(n3440) );
NOR2X1TS U4534 ( .A(n5172), .B(add_subt_module_intDY[11]), .Y(n3425) );
AOI21X1TS U4535 ( .A0(add_subt_module_intDX[10]), .A1(n5128), .B0(n3425),
.Y(n3430) );
OAI211XLTS U4536 ( .A0(add_subt_module_intDY[8]), .A1(n5187), .B0(n3427),
.C0(n3430), .Y(n3439) );
OAI21XLTS U4537 ( .A0(add_subt_module_intDY[13]), .A1(n5181), .B0(
add_subt_module_intDY[12]), .Y(n3424) );
OAI2BB2XLTS U4538 ( .B0(add_subt_module_intDX[12]), .B1(n3424), .A0N(
add_subt_module_intDY[13]), .A1N(n5181), .Y(n3436) );
NOR2XLTS U4539 ( .A(n3425), .B(add_subt_module_intDX[10]), .Y(n3426) );
AOI22X1TS U4540 ( .A0(add_subt_module_intDY[11]), .A1(n5172), .B0(
add_subt_module_intDY[10]), .B1(n3426), .Y(n3432) );
NAND3XLTS U4541 ( .A(n5187), .B(n3427), .C(add_subt_module_intDY[8]), .Y(
n3429) );
NAND2BXLTS U4542 ( .AN(add_subt_module_intDX[9]), .B(
add_subt_module_intDY[9]), .Y(n3428) );
AOI21X1TS U4543 ( .A0(n3429), .A1(n3428), .B0(n3441), .Y(n3431) );
OAI2BB2XLTS U4544 ( .B0(n3432), .B1(n3441), .A0N(n3431), .A1N(n3430), .Y(
n3435) );
OAI21XLTS U4545 ( .A0(add_subt_module_intDY[15]), .A1(n5062), .B0(
add_subt_module_intDY[14]), .Y(n3433) );
OAI2BB2XLTS U4546 ( .B0(add_subt_module_intDX[14]), .B1(n3433), .A0N(
add_subt_module_intDY[15]), .A1N(n5062), .Y(n3434) );
AOI211X1TS U4547 ( .A0(n3437), .A1(n3436), .B0(n3435), .C0(n3434), .Y(n3438)
);
OAI31X1TS U4548 ( .A0(n3441), .A1(n3440), .A2(n3439), .B0(n3438), .Y(n3443)
);
NOR2X1TS U4549 ( .A(n5176), .B(add_subt_module_intDY[17]), .Y(n3445) );
OAI21X1TS U4550 ( .A0(add_subt_module_intDY[18]), .A1(n5186), .B0(n3447),
.Y(n3451) );
AOI211XLTS U4551 ( .A0(add_subt_module_intDX[16]), .A1(n5160), .B0(n3445),
.C0(n3451), .Y(n3442) );
OAI21XLTS U4552 ( .A0(add_subt_module_intDY[21]), .A1(n5162), .B0(
add_subt_module_intDY[20]), .Y(n3444) );
OAI2BB2XLTS U4553 ( .B0(add_subt_module_intDX[20]), .B1(n3444), .A0N(
add_subt_module_intDY[21]), .A1N(n5162), .Y(n3455) );
NOR2XLTS U4554 ( .A(n3445), .B(add_subt_module_intDX[16]), .Y(n3446) );
AOI22X1TS U4555 ( .A0(n3446), .A1(add_subt_module_intDY[16]), .B0(
add_subt_module_intDY[17]), .B1(n5176), .Y(n3449) );
OAI32X1TS U4556 ( .A0(n3451), .A1(n3450), .A2(n3449), .B0(n3448), .B1(n3450),
.Y(n3454) );
OAI21XLTS U4557 ( .A0(add_subt_module_intDY[23]), .A1(n5177), .B0(n2985),
.Y(n3452) );
OAI2BB2XLTS U4558 ( .B0(add_subt_module_intDX[22]), .B1(n3452), .A0N(
add_subt_module_intDY[23]), .A1N(n5177), .Y(n3453) );
AOI211X1TS U4559 ( .A0(n3456), .A1(n3455), .B0(n3454), .C0(n3453), .Y(n3462)
);
NOR2BX1TS U4560 ( .AN(add_subt_module_intDX[24]), .B(n2988), .Y(n3458) );
OR4X2TS U4561 ( .A(n3460), .B(n3459), .C(n3458), .D(n3457), .Y(n3461) );
AOI32X1TS U4562 ( .A0(n3464), .A1(n3463), .A2(n3462), .B0(n3461), .B1(n3464),
.Y(n3533) );
AOI22X1TS U4563 ( .A0(add_subt_module_intDY[57]), .A1(n5131), .B0(
add_subt_module_intDY[56]), .B1(n3466), .Y(n3470) );
AOI32X1TS U4564 ( .A0(n5059), .A1(n3467), .A2(add_subt_module_intDY[58]),
.B0(add_subt_module_intDY[59]), .B1(n5159), .Y(n3468) );
OA21XLTS U4565 ( .A0(n3470), .A1(n3469), .B0(n3468), .Y(n3476) );
NAND3XLTS U4566 ( .A(n5130), .B(n3471), .C(add_subt_module_intDY[60]), .Y(
n3472) );
OAI211XLTS U4567 ( .A0(add_subt_module_intDX[61]), .A1(n5169), .B0(n3473),
.C0(n3472), .Y(n3474) );
OAI2BB2XLTS U4568 ( .B0(n3477), .B1(n3476), .A0N(n3475), .A1N(n3474), .Y(
n3532) );
NOR2BX1TS U4569 ( .AN(n3478), .B(add_subt_module_intDX[46]), .Y(n3492) );
NOR2XLTS U4570 ( .A(n3479), .B(add_subt_module_intDX[44]), .Y(n3480) );
AOI22X1TS U4571 ( .A0(add_subt_module_intDY[45]), .A1(n5190), .B0(
add_subt_module_intDY[44]), .B1(n3480), .Y(n3489) );
OAI21XLTS U4572 ( .A0(add_subt_module_intDY[41]), .A1(n5157), .B0(
add_subt_module_intDY[40]), .Y(n3481) );
OAI2BB2XLTS U4573 ( .B0(add_subt_module_intDX[40]), .B1(n3481), .A0N(
add_subt_module_intDY[41]), .A1N(n5157), .Y(n3485) );
OAI21XLTS U4574 ( .A0(add_subt_module_intDY[43]), .A1(n5174), .B0(
add_subt_module_intDY[42]), .Y(n3482) );
OAI2BB2XLTS U4575 ( .B0(add_subt_module_intDX[42]), .B1(n3482), .A0N(
add_subt_module_intDY[43]), .A1N(n5174), .Y(n3483) );
AOI32X1TS U4576 ( .A0(n3486), .A1(n3485), .A2(n3484), .B0(n3483), .B1(n3486),
.Y(n3487) );
NOR2BX1TS U4577 ( .AN(add_subt_module_intDY[47]), .B(
add_subt_module_intDX[47]), .Y(n3490) );
AOI211XLTS U4578 ( .A0(add_subt_module_intDY[46]), .A1(n3492), .B0(n3491),
.C0(n3490), .Y(n3529) );
NAND3XLTS U4579 ( .A(n5170), .B(n3493), .C(add_subt_module_intDY[36]), .Y(
n3494) );
OAI21XLTS U4580 ( .A0(add_subt_module_intDX[37]), .A1(n5132), .B0(n3494),
.Y(n3503) );
INVX2TS U4581 ( .A(n3495), .Y(n3501) );
OAI21XLTS U4582 ( .A0(add_subt_module_intDY[33]), .A1(n5171), .B0(n2987),
.Y(n3496) );
OAI2BB2XLTS U4583 ( .B0(add_subt_module_intDX[32]), .B1(n3496), .A0N(
add_subt_module_intDY[33]), .A1N(n5171), .Y(n3500) );
OAI2BB2XLTS U4584 ( .B0(add_subt_module_intDX[34]), .B1(n3497), .A0N(
add_subt_module_intDY[35]), .A1N(n5191), .Y(n3498) );
AOI32X1TS U4585 ( .A0(n3501), .A1(n3500), .A2(n3499), .B0(n3498), .B1(n3501),
.Y(n3502) );
OAI2BB1X1TS U4586 ( .A0N(n3504), .A1N(n3503), .B0(n3502), .Y(n3509) );
NOR2BX1TS U4587 ( .AN(add_subt_module_intDY[39]), .B(
add_subt_module_intDX[39]), .Y(n3508) );
NOR3X1TS U4588 ( .A(n5129), .B(n3505), .C(add_subt_module_intDX[38]), .Y(
n3507) );
INVX2TS U4589 ( .A(n3530), .Y(n3506) );
OAI31X1TS U4590 ( .A0(n3509), .A1(n3508), .A2(n3507), .B0(n3506), .Y(n3527)
);
OAI21XLTS U4591 ( .A0(add_subt_module_intDY[53]), .A1(n5125), .B0(
add_subt_module_intDY[52]), .Y(n3510) );
AOI2BB2XLTS U4592 ( .B0(add_subt_module_intDY[53]), .B1(n5125), .A0N(
add_subt_module_intDX[52]), .A1N(n3510), .Y(n3512) );
INVX2TS U4593 ( .A(n3513), .Y(n3519) );
AOI22X1TS U4594 ( .A0(add_subt_module_intDY[49]), .A1(n5158), .B0(
add_subt_module_intDY[48]), .B1(n3515), .Y(n3518) );
AOI32X1TS U4595 ( .A0(n5070), .A1(n3516), .A2(add_subt_module_intDY[50]),
.B0(add_subt_module_intDY[51]), .B1(n5199), .Y(n3517) );
OAI32X1TS U4596 ( .A0(n3520), .A1(n3519), .A2(n3518), .B0(n3517), .B1(n3519),
.Y(n3524) );
OAI2BB2XLTS U4597 ( .B0(add_subt_module_intDX[54]), .B1(n3521), .A0N(
add_subt_module_intDY[55]), .A1N(n5058), .Y(n3523) );
OAI31X1TS U4598 ( .A0(n3525), .A1(n3524), .A2(n3523), .B0(n3522), .Y(n3526)
);
OAI221XLTS U4599 ( .A0(n3530), .A1(n3529), .B0(n3528), .B1(n3527), .C0(n3526), .Y(n3531) );
OR2X2TS U4600 ( .A(n4027), .B(n3868), .Y(n3757) );
AND2X2TS U4601 ( .A(n3535), .B(n4027), .Y(n3735) );
AOI22X1TS U4602 ( .A0(add_subt_module_DmP[36]), .A1(n3839), .B0(
add_subt_module_intDY[36]), .B1(n3735), .Y(n3536) );
OAI21XLTS U4603 ( .A0(n5170), .A1(n3818), .B0(n3536), .Y(n1783) );
INVX2TS U4604 ( .A(n4444), .Y(n4442) );
INVX2TS U4605 ( .A(n3537), .Y(n4574) );
INVX4TS U4606 ( .A(n4577), .Y(n4562) );
AOI22X1TS U4607 ( .A0(n4578), .A1(add_subt_module_Add_Subt_result[53]), .B0(
add_subt_module_DmP[51]), .B1(n4479), .Y(n3538) );
OAI2BB2XLTS U4608 ( .B0(n4583), .B1(n5230), .A0N(add_subt_module_DmP[50]),
.A1N(n4479), .Y(n3539) );
INVX4TS U4609 ( .A(n4487), .Y(n4538) );
NOR2X1TS U4610 ( .A(n4444), .B(n2980), .Y(n4576) );
INVX4TS U4611 ( .A(n4533), .Y(n4587) );
AOI22X1TS U4612 ( .A0(n3642), .A1(n4538), .B0(n4587), .B1(n3643), .Y(n3540)
);
OAI21XLTS U4613 ( .A0(n4340), .A1(n3309), .B0(n3540), .Y(n3541) );
AOI21X1TS U4614 ( .A0(n4550), .A1(n4335), .B0(n3541), .Y(n4346) );
INVX4TS U4615 ( .A(n4451), .Y(n4393) );
OAI21XLTS U4616 ( .A0(n4346), .A1(n4393), .B0(n3644), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[52]) );
AOI222X4TS U4617 ( .A0(n3912), .A1(n5208), .B0(n5054), .B1(n4569), .C0(n5046), .C1(n4537), .Y(n4343) );
AOI22X1TS U4618 ( .A0(n4587), .A1(n3642), .B0(n4538), .B1(n4335), .Y(n3542)
);
OAI21XLTS U4619 ( .A0(n4340), .A1(n3537), .B0(n3542), .Y(n3543) );
AOI21X1TS U4620 ( .A0(n4585), .A1(n4343), .B0(n3543), .Y(n4351) );
OAI21XLTS U4621 ( .A0(n4351), .A1(n4393), .B0(n3644), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[51]) );
AOI22X1TS U4622 ( .A0(add_subt_module_DmP[20]), .A1(n3868), .B0(
add_subt_module_intDY[20]), .B1(n3735), .Y(n3544) );
OAI21XLTS U4623 ( .A0(n5165), .A1(n3757), .B0(n3544), .Y(n1851) );
INVX2TS U4624 ( .A(n3784), .Y(n3924) );
OAI2BB1X1TS U4625 ( .A0N(n3634), .A1N(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[97]), .B0(
n3128), .Y(n3546) );
AOI22X1TS U4626 ( .A0(n3788), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[89]), .B0(
n3787), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[81]), .Y(
n3548) );
AOI22X1TS U4627 ( .A0(n4034), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[73]), .B0(
n3780), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[65]), .Y(
n3547) );
OAI211X1TS U4628 ( .A0(n3792), .A1(n3602), .B0(n3548), .C0(n3547), .Y(n3585)
);
AOI22X1TS U4629 ( .A0(n3785), .A1(add_subt_module_Sgf_normalized_result[10]),
.B0(n3700), .B1(n3585), .Y(n3549) );
OAI21XLTS U4630 ( .A0(n3587), .A1(n2975), .B0(n3549), .Y(n2545) );
AOI22X1TS U4631 ( .A0(n4033), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[86]), .B0(
n3780), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[62]), .Y(
n3552) );
AOI22X1TS U4632 ( .A0(n4034), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[70]), .B0(
n3787), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[78]), .Y(
n3551) );
OAI211X1TS U4633 ( .A0(n3792), .A1(n3593), .B0(n3552), .C0(n3551), .Y(n3588)
);
AOI22X1TS U4634 ( .A0(n3785), .A1(add_subt_module_Sgf_normalized_result[7]),
.B0(n3700), .B1(n3588), .Y(n3553) );
OAI21XLTS U4635 ( .A0(n3590), .A1(n2975), .B0(n3553), .Y(n2542) );
AOI22X1TS U4636 ( .A0(n4034), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[74]), .B0(
n3788), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[90]), .Y(
n3556) );
AOI22X1TS U4637 ( .A0(n3134), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[66]), .B0(
n3787), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[82]), .Y(
n3555) );
OAI211X1TS U4638 ( .A0(n3792), .A1(n3596), .B0(n3556), .C0(n3555), .Y(n3594)
);
AOI22X1TS U4639 ( .A0(n3785), .A1(add_subt_module_Sgf_normalized_result[11]),
.B0(n3700), .B1(n3594), .Y(n3557) );
OAI21XLTS U4640 ( .A0(n3596), .A1(n2975), .B0(n3557), .Y(n2546) );
AOI22X1TS U4641 ( .A0(n3685), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[78]), .B0(
n4033), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[94]), .Y(
n3559) );
AOI22X1TS U4642 ( .A0(n3134), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[70]), .B0(
n3787), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[86]), .Y(
n3558) );
AOI22X1TS U4643 ( .A0(n3785), .A1(add_subt_module_Sgf_normalized_result[15]),
.B0(n3700), .B1(n3591), .Y(n3560) );
OAI21XLTS U4644 ( .A0(n3593), .A1(n2975), .B0(n3560), .Y(n2550) );
OAI2BB1X1TS U4645 ( .A0N(n3634), .A1N(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[96]), .B0(
n3128), .Y(n3561) );
OAI2BB1X1TS U4646 ( .A0N(n3634), .A1N(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[100]), .B0(
n3128), .Y(n3562) );
AOI22X1TS U4647 ( .A0(n3788), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[92]), .B0(
n3780), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[68]), .Y(
n3564) );
AOI22X1TS U4648 ( .A0(n4034), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[76]), .B0(
n3787), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[84]), .Y(
n3563) );
OAI211X1TS U4649 ( .A0(n3792), .A1(n3584), .B0(n3564), .C0(n3563), .Y(n3597)
);
AOI22X1TS U4650 ( .A0(n3785), .A1(add_subt_module_Sgf_normalized_result[13]),
.B0(n3700), .B1(n3597), .Y(n3565) );
OAI21XLTS U4651 ( .A0(n3599), .A1(n2975), .B0(n3565), .Y(n2548) );
AOI22X1TS U4652 ( .A0(n4034), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[72]), .B0(
n3787), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[80]), .Y(
n3567) );
AOI22X1TS U4653 ( .A0(n3788), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[88]), .B0(
n3780), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[64]), .Y(
n3566) );
OAI211X1TS U4654 ( .A0(n3792), .A1(n3599), .B0(n3567), .C0(n3566), .Y(n3579)
);
AOI22X1TS U4655 ( .A0(n3785), .A1(add_subt_module_Sgf_normalized_result[9]),
.B0(n3700), .B1(n3579), .Y(n3568) );
OAI21XLTS U4656 ( .A0(n3584), .A1(n2975), .B0(n3568), .Y(n2544) );
OAI2BB1X1TS U4657 ( .A0N(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[95]), .A1N(
n3634), .B0(n3128), .Y(n3569) );
AOI22X1TS U4658 ( .A0(n4034), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[77]), .B0(
n3780), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[69]), .Y(
n3573) );
AOI22X1TS U4659 ( .A0(n3788), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[93]), .B0(
n3787), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[85]), .Y(
n3572) );
OAI211X1TS U4660 ( .A0(n3792), .A1(n3611), .B0(n3573), .C0(n3572), .Y(n3603)
);
AOI22X1TS U4661 ( .A0(n3785), .A1(add_subt_module_Sgf_normalized_result[14]),
.B0(n3700), .B1(n3603), .Y(n3574) );
OAI21XLTS U4662 ( .A0(n3607), .A1(n2975), .B0(n3574), .Y(n2549) );
AOI22X1TS U4663 ( .A0(n4034), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[75]), .B0(
n3780), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[67]), .Y(
n3577) );
AOI22X1TS U4664 ( .A0(n3575), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[91]), .B0(
n3787), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[83]), .Y(
n3576) );
OAI211X1TS U4665 ( .A0(n3792), .A1(n3587), .B0(n3577), .C0(n3576), .Y(n3600)
);
AOI22X1TS U4666 ( .A0(n3785), .A1(add_subt_module_Sgf_normalized_result[12]),
.B0(n3700), .B1(n3600), .Y(n3578) );
INVX2TS U4667 ( .A(n3924), .Y(n3581) );
AOI22X1TS U4668 ( .A0(n3807), .A1(add_subt_module_Sgf_normalized_result[45]),
.B0(n3688), .B1(n3579), .Y(n3583) );
AOI22X1TS U4669 ( .A0(n3807), .A1(add_subt_module_Sgf_normalized_result[44]),
.B0(n3688), .B1(n3585), .Y(n3586) );
OAI211XLTS U4670 ( .A0(n3587), .A1(n2981), .B0(n3586), .C0(n3582), .Y(n2579)
);
INVX2TS U4671 ( .A(n3702), .Y(n3806) );
AOI22X1TS U4672 ( .A0(n3807), .A1(add_subt_module_Sgf_normalized_result[47]),
.B0(n3806), .B1(n3588), .Y(n3589) );
OAI211XLTS U4673 ( .A0(n3590), .A1(n2982), .B0(n3589), .C0(n3582), .Y(n2582)
);
AOI22X1TS U4674 ( .A0(n2979), .A1(add_subt_module_Sgf_normalized_result[39]),
.B0(n3688), .B1(n3591), .Y(n3592) );
OAI211XLTS U4675 ( .A0(n3593), .A1(n2981), .B0(n3592), .C0(n3582), .Y(n2574)
);
AOI22X1TS U4676 ( .A0(n3807), .A1(add_subt_module_Sgf_normalized_result[43]),
.B0(n3688), .B1(n3594), .Y(n3595) );
OAI211XLTS U4677 ( .A0(n3596), .A1(n2981), .B0(n3595), .C0(n3582), .Y(n2578)
);
AOI22X1TS U4678 ( .A0(n3807), .A1(add_subt_module_Sgf_normalized_result[41]),
.B0(n3688), .B1(n3597), .Y(n3598) );
OAI211XLTS U4679 ( .A0(n3599), .A1(n2981), .B0(n3598), .C0(n3582), .Y(n2576)
);
AOI22X1TS U4680 ( .A0(n3807), .A1(add_subt_module_Sgf_normalized_result[42]),
.B0(n3688), .B1(n3600), .Y(n3601) );
AOI22X1TS U4681 ( .A0(n3807), .A1(add_subt_module_Sgf_normalized_result[40]),
.B0(n3688), .B1(n3603), .Y(n3604) );
OAI211XLTS U4682 ( .A0(n3607), .A1(n2981), .B0(n3604), .C0(n3582), .Y(n2575)
);
AOI22X1TS U4683 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[63]), .A1(
n3134), .B0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[79]), .B1(
n3675), .Y(n3606) );
AOI22X1TS U4684 ( .A0(n4034), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[71]), .B0(
n3788), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[87]), .Y(
n3605) );
OAI211X1TS U4685 ( .A0(n3792), .A1(n3607), .B0(n3606), .C0(n3605), .Y(n3609)
);
AOI22X1TS U4686 ( .A0(n3785), .A1(add_subt_module_Sgf_normalized_result[8]),
.B0(n3700), .B1(n3609), .Y(n3608) );
OAI21XLTS U4687 ( .A0(n3611), .A1(n2975), .B0(n3608), .Y(n2543) );
AOI22X1TS U4688 ( .A0(n3807), .A1(add_subt_module_Sgf_normalized_result[46]),
.B0(n3688), .B1(n3609), .Y(n3610) );
OAI211XLTS U4689 ( .A0(n3611), .A1(n2982), .B0(n3610), .C0(n3582), .Y(n2581)
);
AOI22X1TS U4690 ( .A0(n4033), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[96]), .B0(
n3787), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[88]), .Y(
n3614) );
AOI22X1TS U4691 ( .A0(n3685), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[80]), .B0(
n3134), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[72]), .Y(
n3613) );
AOI22X1TS U4692 ( .A0(n3785), .A1(add_subt_module_Sgf_normalized_result[17]),
.B0(n3700), .B1(n3646), .Y(n3615) );
OAI21XLTS U4693 ( .A0(n3770), .A1(n2976), .B0(n3615), .Y(n2552) );
AOI22X1TS U4694 ( .A0(n3685), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[83]), .B0(
n3780), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[75]), .Y(
n3618) );
AOI22X1TS U4695 ( .A0(n4033), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[99]), .B0(
n3787), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[91]), .Y(
n3617) );
OAI211X1TS U4696 ( .A0(n3637), .A1(n3925), .B0(n3618), .C0(n3617), .Y(n3655)
);
AOI22X1TS U4697 ( .A0(n2979), .A1(add_subt_module_Sgf_normalized_result[20]),
.B0(n3700), .B1(n3655), .Y(n3619) );
OAI21XLTS U4698 ( .A0(n3791), .A1(n2976), .B0(n3619), .Y(n2555) );
AO22XLTS U4699 ( .A0(n3631), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[107]), .B0(
n3129), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[99]), .Y(
n3620) );
AOI22X1TS U4700 ( .A0(n3134), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[73]), .B0(
n3787), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[89]), .Y(
n3622) );
AOI22X1TS U4701 ( .A0(n3685), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[81]), .B0(
n4033), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[97]), .Y(
n3621) );
OAI211X1TS U4702 ( .A0(n3637), .A1(n2958), .B0(n3622), .C0(n3621), .Y(n3657)
);
AOI22X1TS U4703 ( .A0(n3785), .A1(add_subt_module_Sgf_normalized_result[18]),
.B0(n3700), .B1(n3657), .Y(n3623) );
OAI21XLTS U4704 ( .A0(n3783), .A1(n2976), .B0(n3623), .Y(n2553) );
AOI22X1TS U4705 ( .A0(n3134), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[76]), .B0(
n3675), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[92]), .Y(
n3625) );
AOI22X1TS U4706 ( .A0(n3685), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[84]), .B0(
n4033), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[100]), .Y(
n3624) );
OAI211X1TS U4707 ( .A0(n3637), .A1(n3767), .B0(n3625), .C0(n3624), .Y(n3648)
);
AOI22X1TS U4708 ( .A0(n2979), .A1(add_subt_module_Sgf_normalized_result[21]),
.B0(n3700), .B1(n3648), .Y(n3626) );
OAI21XLTS U4709 ( .A0(n3650), .A1(n2976), .B0(n3626), .Y(n2556) );
AO22XLTS U4710 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[109]), .A1(
n3631), .B0(n3129), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[101]), .Y(
n3627) );
AOI22X1TS U4711 ( .A0(n3788), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[95]), .B0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[87]), .B1(
n3675), .Y(n3629) );
AOI22X1TS U4712 ( .A0(n3685), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[79]), .B0(
n3134), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[71]), .Y(
n3628) );
AOI22X1TS U4713 ( .A0(n3785), .A1(add_subt_module_Sgf_normalized_result[16]),
.B0(n3700), .B1(n3653), .Y(n3630) );
OAI21XLTS U4714 ( .A0(n3778), .A1(n2976), .B0(n3630), .Y(n2551) );
AO22XLTS U4715 ( .A0(n3631), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[106]), .B0(
n3129), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[98]), .Y(
n3632) );
AOI22X1TS U4716 ( .A0(n4033), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[98]), .B0(
n3675), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[90]), .Y(
n3636) );
AOI22X1TS U4717 ( .A0(n3685), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[82]), .B0(
n3780), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[74]), .Y(
n3635) );
OAI211X1TS U4718 ( .A0(n3637), .A1(n3804), .B0(n3636), .C0(n3635), .Y(n3651)
);
AOI22X1TS U4719 ( .A0(n3785), .A1(add_subt_module_Sgf_normalized_result[19]),
.B0(n3700), .B1(n3651), .Y(n3638) );
OAI21XLTS U4720 ( .A0(n3774), .A1(n2976), .B0(n3638), .Y(n2554) );
AOI22X1TS U4721 ( .A0(n4033), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[101]), .B0(
n3675), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[93]), .Y(
n3640) );
AOI22X1TS U4722 ( .A0(n3685), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[85]), .B0(
n3780), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[77]), .Y(
n3639) );
OAI211X1TS U4723 ( .A0(n3792), .A1(n3809), .B0(n3640), .C0(n3639), .Y(n3659)
);
AOI22X1TS U4724 ( .A0(n2979), .A1(add_subt_module_Sgf_normalized_result[22]),
.B0(n3700), .B1(n3659), .Y(n3641) );
OAI21XLTS U4725 ( .A0(n3661), .A1(n2976), .B0(n3641), .Y(n2557) );
OAI21XLTS U4726 ( .A0(n4342), .A1(n4393), .B0(n3644), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[53]) );
BUFX3TS U4727 ( .A(n2954), .Y(n3746) );
AOI22X1TS U4728 ( .A0(add_subt_module_DmP[37]), .A1(n3828), .B0(
add_subt_module_intDY[37]), .B1(n3746), .Y(n3645) );
OAI21XLTS U4729 ( .A0(n5153), .A1(n3826), .B0(n3645), .Y(n1807) );
AOI22X1TS U4730 ( .A0(n2979), .A1(add_subt_module_Sgf_normalized_result[37]),
.B0(n3688), .B1(n3646), .Y(n3647) );
OAI211XLTS U4731 ( .A0(n3770), .A1(n2982), .B0(n3647), .C0(n3582), .Y(n2572)
);
AOI22X1TS U4732 ( .A0(n2979), .A1(add_subt_module_Sgf_normalized_result[33]),
.B0(n3688), .B1(n3648), .Y(n3649) );
OAI211XLTS U4733 ( .A0(n3650), .A1(n2981), .B0(n3649), .C0(n3582), .Y(n2568)
);
AOI22X1TS U4734 ( .A0(n2979), .A1(add_subt_module_Sgf_normalized_result[35]),
.B0(n3688), .B1(n3651), .Y(n3652) );
OAI211XLTS U4735 ( .A0(n3774), .A1(n2981), .B0(n3652), .C0(n3582), .Y(n2570)
);
AOI22X1TS U4736 ( .A0(n2979), .A1(add_subt_module_Sgf_normalized_result[38]),
.B0(n3688), .B1(n3653), .Y(n3654) );
AOI22X1TS U4737 ( .A0(n2979), .A1(add_subt_module_Sgf_normalized_result[34]),
.B0(n3688), .B1(n3655), .Y(n3656) );
OAI211XLTS U4738 ( .A0(n3791), .A1(n2981), .B0(n3656), .C0(n3582), .Y(n2569)
);
AOI22X1TS U4739 ( .A0(n2979), .A1(add_subt_module_Sgf_normalized_result[36]),
.B0(n3688), .B1(n3657), .Y(n3658) );
AOI22X1TS U4740 ( .A0(n2979), .A1(add_subt_module_Sgf_normalized_result[32]),
.B0(n3688), .B1(n3659), .Y(n3660) );
OAI211XLTS U4741 ( .A0(n3661), .A1(n2981), .B0(n3660), .C0(n3582), .Y(n2567)
);
AOI22X1TS U4742 ( .A0(n3839), .A1(add_subt_module_DmP[46]), .B0(
add_subt_module_intDY[46]), .B1(n3746), .Y(n3662) );
OAI21XLTS U4743 ( .A0(n5151), .A1(n3818), .B0(n3662), .Y(n1875) );
AOI22X1TS U4744 ( .A0(add_subt_module_DmP[16]), .A1(n3839), .B0(
add_subt_module_intDY[16]), .B1(n3746), .Y(n3663) );
OAI21XLTS U4745 ( .A0(n5146), .A1(n3818), .B0(n3663), .Y(n1871) );
INVX2TS U4746 ( .A(n3664), .Y(n1703) );
AOI22X1TS U4747 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[109]), .A1(
n4033), .B0(n3780), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[85]), .Y(
n3665) );
INVX2TS U4748 ( .A(n3684), .Y(n4035) );
OAI211XLTS U4749 ( .A0(n4037), .A1(n5226), .B0(n3665), .C0(n4035), .Y(n3666)
);
AOI21X1TS U4750 ( .A0(n4034), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[93]), .B0(
n3666), .Y(n3698) );
AOI22X1TS U4751 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[79]), .A1(
n3134), .B0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[95]), .B1(
n3675), .Y(n3668) );
AOI22X1TS U4752 ( .A0(n3685), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[87]), .B0(
n4033), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[103]), .Y(
n3667) );
NAND3XLTS U4753 ( .A(n3668), .B(n3667), .C(n4035), .Y(n3696) );
AOI22X1TS U4754 ( .A0(n2979), .A1(add_subt_module_Sgf_normalized_result[30]),
.B0(n3688), .B1(n3696), .Y(n3669) );
OAI21XLTS U4755 ( .A0(n3698), .A1(n3924), .B0(n3669), .Y(n2565) );
AOI22X1TS U4756 ( .A0(n3788), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[107]), .B0(
n3780), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[83]), .Y(
n3670) );
OAI211XLTS U4757 ( .A0(n4037), .A1(n5227), .B0(n3670), .C0(n4035), .Y(n3671)
);
AOI21X1TS U4758 ( .A0(n3685), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[91]), .B0(
n3671), .Y(n3692) );
AOI22X1TS U4759 ( .A0(n3788), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[105]), .B0(
n3787), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[97]), .Y(
n3673) );
AOI22X1TS U4760 ( .A0(n3685), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[89]), .B0(
n3780), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[81]), .Y(
n3672) );
NAND3XLTS U4761 ( .A(n3673), .B(n3672), .C(n4035), .Y(n3690) );
AOI22X1TS U4762 ( .A0(n2979), .A1(add_subt_module_Sgf_normalized_result[28]),
.B0(n3688), .B1(n3690), .Y(n3674) );
AOI22X1TS U4763 ( .A0(n3780), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[84]), .B0(
n3675), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[100]), .Y(
n3676) );
OAI211XLTS U4764 ( .A0(n2991), .A1(n5239), .B0(n3676), .C0(n4035), .Y(n3677)
);
AOI21X1TS U4765 ( .A0(n3788), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[108]), .B0(
n3677), .Y(n3695) );
AOI22X1TS U4766 ( .A0(n3780), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[80]), .B0(
n3675), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[96]), .Y(
n3679) );
AOI22X1TS U4767 ( .A0(n3685), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[88]), .B0(
n4033), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[104]), .Y(
n3678) );
NAND3XLTS U4768 ( .A(n3679), .B(n3678), .C(n4035), .Y(n3693) );
AOI22X1TS U4769 ( .A0(n2979), .A1(add_subt_module_Sgf_normalized_result[29]),
.B0(n3688), .B1(n3693), .Y(n3680) );
OAI21XLTS U4770 ( .A0(n3695), .A1(n3924), .B0(n3680), .Y(n2564) );
AOI22X1TS U4771 ( .A0(n3780), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[86]), .B0(
n3787), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[102]), .Y(
n3681) );
OAI21XLTS U4772 ( .A0(n2991), .A1(n5229), .B0(n3681), .Y(n3682) );
NOR3X1TS U4773 ( .A(n3684), .B(n3683), .C(n3682), .Y(n3703) );
AOI22X1TS U4774 ( .A0(n3780), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[78]), .B0(
n3675), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[94]), .Y(
n3687) );
AOI22X1TS U4775 ( .A0(n3685), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[86]), .B0(
n4033), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[102]), .Y(
n3686) );
NAND3XLTS U4776 ( .A(n3687), .B(n3686), .C(n4035), .Y(n3699) );
AOI22X1TS U4777 ( .A0(n2979), .A1(add_subt_module_Sgf_normalized_result[31]),
.B0(n3688), .B1(n3699), .Y(n3689) );
OAI21XLTS U4778 ( .A0(n3703), .A1(n3924), .B0(n3689), .Y(n2566) );
AOI22X1TS U4779 ( .A0(n2979), .A1(add_subt_module_Sgf_normalized_result[26]),
.B0(n3700), .B1(n3690), .Y(n3691) );
OAI21XLTS U4780 ( .A0(n3692), .A1(n3702), .B0(n3691), .Y(n2561) );
AOI22X1TS U4781 ( .A0(n2979), .A1(add_subt_module_Sgf_normalized_result[25]),
.B0(n3700), .B1(n3693), .Y(n3694) );
OAI21XLTS U4782 ( .A0(n3695), .A1(n3702), .B0(n3694), .Y(n2560) );
AOI22X1TS U4783 ( .A0(n2979), .A1(add_subt_module_Sgf_normalized_result[24]),
.B0(n3700), .B1(n3696), .Y(n3697) );
OAI21XLTS U4784 ( .A0(n3698), .A1(n3702), .B0(n3697), .Y(n2559) );
AOI22X1TS U4785 ( .A0(n2979), .A1(add_subt_module_Sgf_normalized_result[23]),
.B0(n3700), .B1(n3699), .Y(n3701) );
OAI21XLTS U4786 ( .A0(n3703), .A1(n3702), .B0(n3701), .Y(n2558) );
BUFX4TS U4787 ( .A(n3757), .Y(n3826) );
AOI22X1TS U4788 ( .A0(add_subt_module_DmP[18]), .A1(n3828), .B0(
add_subt_module_intDY[18]), .B1(n2954), .Y(n3704) );
AOI22X1TS U4789 ( .A0(add_subt_module_DmP[21]), .A1(n3828), .B0(
add_subt_module_intDY[21]), .B1(n2954), .Y(n3705) );
OAI21XLTS U4790 ( .A0(n5162), .A1(n3818), .B0(n3705), .Y(n1764) );
AOI22X1TS U4791 ( .A0(add_subt_module_DmP[43]), .A1(n3839), .B0(
add_subt_module_intDY[43]), .B1(n3746), .Y(n3706) );
OAI21XLTS U4792 ( .A0(n5174), .A1(n3826), .B0(n3706), .Y(n1842) );
AOI22X1TS U4793 ( .A0(add_subt_module_DmP[25]), .A1(n3883), .B0(
add_subt_module_intDY[25]), .B1(n3735), .Y(n3707) );
OAI21XLTS U4794 ( .A0(n5192), .A1(n3818), .B0(n3707), .Y(n1758) );
AOI22X1TS U4795 ( .A0(add_subt_module_DmP[44]), .A1(n3868), .B0(
add_subt_module_intDY[44]), .B1(n3746), .Y(n3708) );
OAI21XLTS U4796 ( .A0(n5143), .A1(n3818), .B0(n3708), .Y(n1865) );
AOI22X1TS U4797 ( .A0(n3883), .A1(add_subt_module_DmP[5]), .B0(
add_subt_module_intDY[5]), .B1(n3746), .Y(n3709) );
AOI22X1TS U4798 ( .A0(add_subt_module_DmP[38]), .A1(n3839), .B0(
add_subt_module_intDY[38]), .B1(n2954), .Y(n3710) );
OAI21XLTS U4799 ( .A0(n5074), .A1(n3826), .B0(n3710), .Y(n1831) );
AOI22X1TS U4800 ( .A0(add_subt_module_DmP[32]), .A1(n3828), .B0(n2987), .B1(
n3735), .Y(n3711) );
OAI21XLTS U4801 ( .A0(n5195), .A1(n3826), .B0(n3711), .Y(n1747) );
INVX4TS U4802 ( .A(n2954), .Y(n3727) );
AOI22X1TS U4803 ( .A0(n3889), .A1(add_subt_module_intDY[3]), .B0(
add_subt_module_DMP[3]), .B1(n3883), .Y(n3712) );
OAI21XLTS U4804 ( .A0(n5188), .A1(n3727), .B0(n3712), .Y(n1708) );
AOI22X1TS U4805 ( .A0(n3838), .A1(add_subt_module_intDY[2]), .B0(
add_subt_module_DMP[2]), .B1(n3828), .Y(n3713) );
OAI21XLTS U4806 ( .A0(n5189), .A1(n3727), .B0(n3713), .Y(n1706) );
AOI22X1TS U4807 ( .A0(n3889), .A1(add_subt_module_intDY[4]), .B0(
add_subt_module_DMP[4]), .B1(n3839), .Y(n3714) );
OAI21XLTS U4808 ( .A0(n5197), .A1(n3727), .B0(n3714), .Y(n1705) );
AOI22X1TS U4809 ( .A0(n3884), .A1(add_subt_module_intDY[14]), .B0(
add_subt_module_DMP[14]), .B1(n3859), .Y(n3715) );
OAI21XLTS U4810 ( .A0(n5178), .A1(n3727), .B0(n3715), .Y(n1726) );
AOI22X1TS U4811 ( .A0(n3884), .A1(n2985), .B0(add_subt_module_DMP[22]), .B1(
n3888), .Y(n3716) );
OAI21XLTS U4812 ( .A0(n5066), .A1(n3727), .B0(n3716), .Y(n1731) );
AOI22X1TS U4813 ( .A0(n3865), .A1(add_subt_module_intDY[34]), .B0(
add_subt_module_DMP[34]), .B1(n3879), .Y(n3717) );
OAI21XLTS U4814 ( .A0(n5065), .A1(n3727), .B0(n3717), .Y(n1722) );
AOI22X1TS U4815 ( .A0(n3884), .A1(n2986), .B0(add_subt_module_DMP[30]), .B1(
n3859), .Y(n3718) );
OAI21XLTS U4816 ( .A0(n5173), .A1(n3727), .B0(n3718), .Y(n1724) );
AOI22X1TS U4817 ( .A0(n3865), .A1(add_subt_module_intDY[26]), .B0(
add_subt_module_DMP[26]), .B1(n3859), .Y(n3719) );
OAI21XLTS U4818 ( .A0(n5175), .A1(n3727), .B0(n3719), .Y(n1732) );
AOI22X1TS U4819 ( .A0(n3838), .A1(add_subt_module_intDY[17]), .B0(
add_subt_module_DMP[17]), .B1(n3859), .Y(n3720) );
OAI21XLTS U4820 ( .A0(n5176), .A1(n3727), .B0(n3720), .Y(n1729) );
AOI22X1TS U4821 ( .A0(n3884), .A1(add_subt_module_intDY[28]), .B0(
add_subt_module_DMP[28]), .B1(n3859), .Y(n3721) );
OAI21XLTS U4822 ( .A0(n5164), .A1(n3727), .B0(n3721), .Y(n1736) );
AOI22X1TS U4823 ( .A0(n3865), .A1(add_subt_module_intDY[18]), .B0(
add_subt_module_DMP[18]), .B1(n3859), .Y(n3722) );
OAI21XLTS U4824 ( .A0(n5186), .A1(n3727), .B0(n3722), .Y(n1728) );
AOI22X1TS U4825 ( .A0(n3889), .A1(n2988), .B0(add_subt_module_DMP[24]), .B1(
n3859), .Y(n3723) );
OAI21XLTS U4826 ( .A0(n5075), .A1(n3727), .B0(n3723), .Y(n1730) );
AOI22X1TS U4827 ( .A0(n3838), .A1(add_subt_module_intDY[15]), .B0(
add_subt_module_DMP[15]), .B1(n3859), .Y(n3724) );
AOI22X1TS U4828 ( .A0(n3865), .A1(add_subt_module_intDY[23]), .B0(
add_subt_module_DMP[23]), .B1(n3859), .Y(n3725) );
OAI21XLTS U4829 ( .A0(n5177), .A1(n3727), .B0(n3725), .Y(n1723) );
AOI22X1TS U4830 ( .A0(n3838), .A1(add_subt_module_intDY[21]), .B0(
add_subt_module_DMP[21]), .B1(n3859), .Y(n3726) );
OAI21XLTS U4831 ( .A0(n5162), .A1(n3727), .B0(n3726), .Y(n1727) );
AOI222X1TS U4832 ( .A0(n3889), .A1(add_subt_module_intDX[49]), .B0(
add_subt_module_DmP[49]), .B1(n3828), .C0(add_subt_module_intDY[49]),
.C1(n2954), .Y(n3728) );
INVX2TS U4833 ( .A(n3728), .Y(n1879) );
AOI22X1TS U4834 ( .A0(add_subt_module_DmP[50]), .A1(n3883), .B0(
add_subt_module_intDY[50]), .B1(n2954), .Y(n3729) );
OAI21XLTS U4835 ( .A0(n5070), .A1(n3820), .B0(n3729), .Y(n1892) );
AOI22X1TS U4836 ( .A0(add_subt_module_DmP[3]), .A1(n3883), .B0(
add_subt_module_intDY[3]), .B1(n3746), .Y(n3730) );
OAI21XLTS U4837 ( .A0(n5188), .A1(n3820), .B0(n3730), .Y(n1885) );
AOI22X1TS U4838 ( .A0(add_subt_module_DmP[45]), .A1(n3868), .B0(
add_subt_module_intDY[45]), .B1(n3746), .Y(n3731) );
OAI21XLTS U4839 ( .A0(n5190), .A1(n3820), .B0(n3731), .Y(n1855) );
AOI22X1TS U4840 ( .A0(add_subt_module_DmP[27]), .A1(n3839), .B0(
add_subt_module_intDY[27]), .B1(n2954), .Y(n3732) );
AOI22X1TS U4841 ( .A0(add_subt_module_DmP[2]), .A1(n3828), .B0(
add_subt_module_intDY[2]), .B1(n3735), .Y(n3733) );
OAI21XLTS U4842 ( .A0(n5189), .A1(n3820), .B0(n3733), .Y(n1895) );
AOI22X1TS U4843 ( .A0(add_subt_module_DmP[4]), .A1(n3839), .B0(
add_subt_module_intDY[4]), .B1(n3735), .Y(n3734) );
OAI21XLTS U4844 ( .A0(n5197), .A1(n3820), .B0(n3734), .Y(n1902) );
AOI22X1TS U4845 ( .A0(add_subt_module_DmP[6]), .A1(n3828), .B0(
add_subt_module_intDY[6]), .B1(n3735), .Y(n3736) );
OAI21XLTS U4846 ( .A0(n5145), .A1(n3820), .B0(n3736), .Y(n1861) );
AOI22X1TS U4847 ( .A0(add_subt_module_DmP[14]), .A1(n3883), .B0(
add_subt_module_intDY[14]), .B1(n3823), .Y(n3737) );
OAI21XLTS U4848 ( .A0(n5178), .A1(n3818), .B0(n3737), .Y(n1779) );
AOI22X1TS U4849 ( .A0(n3883), .A1(add_subt_module_DmP[9]), .B0(
add_subt_module_intDY[9]), .B1(n3823), .Y(n3738) );
OAI21XLTS U4850 ( .A0(n5154), .A1(n3820), .B0(n3738), .Y(n1868) );
AOI22X1TS U4851 ( .A0(add_subt_module_DmP[35]), .A1(n3828), .B0(
add_subt_module_intDY[35]), .B1(n3823), .Y(n3739) );
OAI21XLTS U4852 ( .A0(n5191), .A1(n3826), .B0(n3739), .Y(n1790) );
AOI22X1TS U4853 ( .A0(add_subt_module_DmP[17]), .A1(n3828), .B0(
add_subt_module_intDY[17]), .B1(n3823), .Y(n3740) );
OAI21XLTS U4854 ( .A0(n5176), .A1(n3818), .B0(n3740), .Y(n1750) );
BUFX4TS U4855 ( .A(n3746), .Y(n3763) );
AOI22X1TS U4856 ( .A0(n3763), .A1(add_subt_module_intDX[53]), .B0(
add_subt_module_DMP[53]), .B1(n3888), .Y(n3741) );
OAI21XLTS U4857 ( .A0(n5068), .A1(n3820), .B0(n3741), .Y(n1913) );
AOI22X1TS U4858 ( .A0(n3763), .A1(add_subt_module_intDX[62]), .B0(
add_subt_module_DMP[62]), .B1(n3868), .Y(n3742) );
OAI21XLTS U4859 ( .A0(n5142), .A1(n3826), .B0(n3742), .Y(n1940) );
AOI22X1TS U4860 ( .A0(n3763), .A1(add_subt_module_intDX[52]), .B0(
add_subt_module_DMP[52]), .B1(n3879), .Y(n3743) );
OAI21XLTS U4861 ( .A0(n5163), .A1(n3820), .B0(n3743), .Y(n1910) );
AOI222X1TS U4862 ( .A0(n3889), .A1(add_subt_module_intDX[15]), .B0(
add_subt_module_DmP[15]), .B1(n3839), .C0(add_subt_module_intDY[15]),
.C1(n3746), .Y(n3744) );
INVX2TS U4863 ( .A(n3744), .Y(n1786) );
AOI222X1TS U4864 ( .A0(n3889), .A1(add_subt_module_intDX[41]), .B0(
add_subt_module_DmP[41]), .B1(n3839), .C0(add_subt_module_intDY[41]),
.C1(n3746), .Y(n3745) );
INVX2TS U4865 ( .A(n3745), .Y(n1814) );
AOI222X1TS U4866 ( .A0(n3838), .A1(add_subt_module_intDX[10]), .B0(
add_subt_module_DmP[10]), .B1(n3883), .C0(add_subt_module_intDY[10]),
.C1(n3746), .Y(n3747) );
INVX2TS U4867 ( .A(n3747), .Y(n1845) );
AOI22X1TS U4868 ( .A0(add_subt_module_DmP[47]), .A1(n3883), .B0(
add_subt_module_intDY[47]), .B1(n3763), .Y(n3748) );
OAI21XLTS U4869 ( .A0(n5061), .A1(n3820), .B0(n3748), .Y(n1889) );
AOI22X1TS U4870 ( .A0(add_subt_module_DmP[19]), .A1(n3828), .B0(
add_subt_module_intDY[19]), .B1(n3763), .Y(n3749) );
OAI21XLTS U4871 ( .A0(n5072), .A1(n3826), .B0(n3749), .Y(n1802) );
AOI22X1TS U4872 ( .A0(add_subt_module_DmP[34]), .A1(n3883), .B0(
add_subt_module_intDY[34]), .B1(n3763), .Y(n3750) );
OAI21XLTS U4873 ( .A0(n5065), .A1(n3826), .B0(n3750), .Y(n1799) );
AOI22X1TS U4874 ( .A0(n3868), .A1(add_subt_module_DmP[30]), .B0(n2986), .B1(
n3763), .Y(n3751) );
OAI21XLTS U4875 ( .A0(n5173), .A1(n3818), .B0(n3751), .Y(n1793) );
AOI22X1TS U4876 ( .A0(add_subt_module_DmP[42]), .A1(n3839), .B0(
add_subt_module_intDY[42]), .B1(n3763), .Y(n3752) );
OAI21XLTS U4877 ( .A0(n5064), .A1(n3826), .B0(n3752), .Y(n1821) );
AOI22X1TS U4878 ( .A0(add_subt_module_DmP[40]), .A1(n3883), .B0(
add_subt_module_intDY[40]), .B1(n3763), .Y(n3753) );
AOI22X1TS U4879 ( .A0(add_subt_module_DmP[39]), .A1(n3828), .B0(
add_subt_module_intDY[39]), .B1(n3763), .Y(n3754) );
OAI21XLTS U4880 ( .A0(n5144), .A1(n3826), .B0(n3754), .Y(n1810) );
AOI22X1TS U4881 ( .A0(add_subt_module_DmP[22]), .A1(n3883), .B0(n2985), .B1(
n3763), .Y(n3755) );
AOI22X1TS U4882 ( .A0(add_subt_module_DmP[28]), .A1(n3839), .B0(
add_subt_module_intDY[28]), .B1(n3763), .Y(n3756) );
OAI21XLTS U4883 ( .A0(n5164), .A1(n3757), .B0(n3756), .Y(n1737) );
AOI22X1TS U4884 ( .A0(add_subt_module_DmP[11]), .A1(n3868), .B0(
add_subt_module_intDY[11]), .B1(n3763), .Y(n3758) );
OAI21XLTS U4885 ( .A0(n5172), .A1(n3818), .B0(n3758), .Y(n1824) );
AOI22X1TS U4886 ( .A0(add_subt_module_DmP[26]), .A1(n3828), .B0(
add_subt_module_intDY[26]), .B1(n3763), .Y(n3759) );
OAI21XLTS U4887 ( .A0(n5175), .A1(n3818), .B0(n3759), .Y(n1733) );
AOI22X1TS U4888 ( .A0(add_subt_module_DmP[8]), .A1(n3883), .B0(
add_subt_module_intDY[8]), .B1(n3763), .Y(n3760) );
AOI22X1TS U4889 ( .A0(add_subt_module_DmP[24]), .A1(n3883), .B0(n2988), .B1(
n3763), .Y(n3761) );
OAI21XLTS U4890 ( .A0(n5075), .A1(n3826), .B0(n3761), .Y(n1743) );
AOI22X1TS U4891 ( .A0(add_subt_module_DmP[12]), .A1(n3839), .B0(
add_subt_module_intDY[12]), .B1(n3763), .Y(n3762) );
OAI21XLTS U4892 ( .A0(n5196), .A1(n3826), .B0(n3762), .Y(n1827) );
AOI22X1TS U4893 ( .A0(add_subt_module_DmP[23]), .A1(n3828), .B0(
add_subt_module_intDY[23]), .B1(n3763), .Y(n3764) );
AOI22X1TS U4894 ( .A0(n3807), .A1(add_subt_module_Sgf_normalized_result[53]),
.B0(n3806), .B1(n3765), .Y(n3766) );
OAI211XLTS U4895 ( .A0(n3767), .A1(n2982), .B0(n3766), .C0(n2989), .Y(n2588)
);
AOI22X1TS U4896 ( .A0(n3788), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[84]), .B0(
n3134), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[60]), .Y(
n3769) );
AOI22X1TS U4897 ( .A0(n4034), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[68]), .B0(
n3787), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[76]), .Y(
n3768) );
OAI211X1TS U4898 ( .A0(n3792), .A1(n3770), .B0(n3769), .C0(n3768), .Y(n3794)
);
AOI22X1TS U4899 ( .A0(n3785), .A1(add_subt_module_Sgf_normalized_result[5]),
.B0(n3784), .B1(n3794), .Y(n3771) );
OAI21XLTS U4900 ( .A0(n3796), .A1(n2975), .B0(n3771), .Y(n2540) );
AOI22X1TS U4901 ( .A0(n3134), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[58]), .B0(
n3787), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[74]), .Y(
n3773) );
AOI22X1TS U4902 ( .A0(n4034), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[66]), .B0(
n3788), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[82]), .Y(
n3772) );
OAI211X1TS U4903 ( .A0(n3792), .A1(n3774), .B0(n3773), .C0(n3772), .Y(n3802)
);
AOI22X1TS U4904 ( .A0(n2979), .A1(add_subt_module_Sgf_normalized_result[3]),
.B0(n3784), .B1(n3802), .Y(n3775) );
OAI21XLTS U4905 ( .A0(n3804), .A1(n2976), .B0(n3775), .Y(n2538) );
AOI22X1TS U4906 ( .A0(n3788), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[85]), .B0(
n3787), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[77]), .Y(
n3777) );
AOI22X1TS U4907 ( .A0(n4034), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[69]), .B0(
n3780), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[61]), .Y(
n3776) );
OAI211X1TS U4908 ( .A0(n3792), .A1(n3778), .B0(n3777), .C0(n3776), .Y(n3799)
);
AOI22X1TS U4909 ( .A0(n3785), .A1(add_subt_module_Sgf_normalized_result[6]),
.B0(n3784), .B1(n3799), .Y(n3779) );
OAI21XLTS U4910 ( .A0(n3801), .A1(n2975), .B0(n3779), .Y(n2541) );
AOI22X1TS U4911 ( .A0(n4033), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[83]), .B0(
n3780), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[59]), .Y(
n3782) );
AOI22X1TS U4912 ( .A0(n4034), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[67]), .B0(
n3787), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[75]), .Y(
n3781) );
OAI211X1TS U4913 ( .A0(n3792), .A1(n3783), .B0(n3782), .C0(n3781), .Y(n3797)
);
AOI22X1TS U4914 ( .A0(n3785), .A1(add_subt_module_Sgf_normalized_result[4]),
.B0(n3784), .B1(n3797), .Y(n3786) );
OAI21XLTS U4915 ( .A0(n2958), .A1(n2976), .B0(n3786), .Y(n2539) );
AOI22X1TS U4916 ( .A0(n4034), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[65]), .B0(
n3134), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[57]), .Y(
n3790) );
AOI22X1TS U4917 ( .A0(n3788), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[81]), .B0(
n3787), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[73]), .Y(
n3789) );
AOI22X1TS U4918 ( .A0(n3807), .A1(add_subt_module_Sgf_normalized_result[52]),
.B0(n3806), .B1(n3922), .Y(n3793) );
OAI211XLTS U4919 ( .A0(n3925), .A1(n2982), .B0(n3793), .C0(n3582), .Y(n2587)
);
AOI22X1TS U4920 ( .A0(n3807), .A1(add_subt_module_Sgf_normalized_result[49]),
.B0(n3806), .B1(n3794), .Y(n3795) );
OAI211XLTS U4921 ( .A0(n3796), .A1(n2982), .B0(n3795), .C0(n3582), .Y(n2584)
);
AOI22X1TS U4922 ( .A0(n3807), .A1(add_subt_module_Sgf_normalized_result[50]),
.B0(n3806), .B1(n3797), .Y(n3798) );
OAI211XLTS U4923 ( .A0(n2958), .A1(n2982), .B0(n3798), .C0(n3582), .Y(n2585)
);
AOI22X1TS U4924 ( .A0(n3807), .A1(add_subt_module_Sgf_normalized_result[48]),
.B0(n3806), .B1(n3799), .Y(n3800) );
OAI211XLTS U4925 ( .A0(n3801), .A1(n2982), .B0(n3800), .C0(n2989), .Y(n2583)
);
AOI22X1TS U4926 ( .A0(n3807), .A1(add_subt_module_Sgf_normalized_result[51]),
.B0(n3806), .B1(n3802), .Y(n3803) );
OAI211XLTS U4927 ( .A0(n3804), .A1(n2982), .B0(n3803), .C0(n2989), .Y(n2586)
);
AOI22X1TS U4928 ( .A0(n3807), .A1(add_subt_module_Sgf_normalized_result[54]),
.B0(n3806), .B1(n3805), .Y(n3808) );
OAI211XLTS U4929 ( .A0(n3809), .A1(n2982), .B0(n2989), .C0(n3808), .Y(n2937)
);
AOI22X1TS U4930 ( .A0(n3823), .A1(add_subt_module_intDX[55]), .B0(
add_subt_module_DMP[55]), .B1(n3883), .Y(n3810) );
OAI21XLTS U4931 ( .A0(n5148), .A1(n3820), .B0(n3810), .Y(n1919) );
AOI22X1TS U4932 ( .A0(n3823), .A1(add_subt_module_intDX[57]), .B0(
add_subt_module_DMP[57]), .B1(n3828), .Y(n3811) );
OAI21XLTS U4933 ( .A0(n5067), .A1(n3818), .B0(n3811), .Y(n1925) );
AOI22X1TS U4934 ( .A0(n3823), .A1(add_subt_module_intDX[59]), .B0(
add_subt_module_DMP[59]), .B1(n3879), .Y(n3812) );
OAI21XLTS U4935 ( .A0(n5073), .A1(n3818), .B0(n3812), .Y(n1931) );
AOI22X1TS U4936 ( .A0(n3823), .A1(add_subt_module_intDX[54]), .B0(
add_subt_module_DMP[54]), .B1(n3888), .Y(n3813) );
OAI21XLTS U4937 ( .A0(n5193), .A1(n3820), .B0(n3813), .Y(n1916) );
AOI22X1TS U4938 ( .A0(n3823), .A1(add_subt_module_intDX[58]), .B0(
add_subt_module_DMP[58]), .B1(n3888), .Y(n3814) );
OAI21XLTS U4939 ( .A0(n5141), .A1(n3826), .B0(n3814), .Y(n1928) );
AOI22X1TS U4940 ( .A0(n3823), .A1(add_subt_module_intDX[60]), .B0(
add_subt_module_DMP[60]), .B1(n3868), .Y(n3815) );
OAI21XLTS U4941 ( .A0(n5185), .A1(n3818), .B0(n3815), .Y(n1934) );
AOI22X1TS U4942 ( .A0(n3823), .A1(add_subt_module_intDX[56]), .B0(
add_subt_module_DMP[56]), .B1(n3828), .Y(n3816) );
OAI21XLTS U4943 ( .A0(n5150), .A1(n3818), .B0(n3816), .Y(n1922) );
AOI22X1TS U4944 ( .A0(n3823), .A1(add_subt_module_intDX[61]), .B0(
add_subt_module_DMP[61]), .B1(n3888), .Y(n3817) );
OAI21XLTS U4945 ( .A0(n5169), .A1(n3826), .B0(n3817), .Y(n1937) );
AOI22X1TS U4946 ( .A0(add_subt_module_DmP[1]), .A1(n3839), .B0(
add_subt_module_intDY[1]), .B1(n3823), .Y(n3819) );
OAI21XLTS U4947 ( .A0(n5147), .A1(n3820), .B0(n3819), .Y(n1882) );
AOI22X1TS U4948 ( .A0(add_subt_module_DmP[7]), .A1(n3868), .B0(
add_subt_module_intDY[7]), .B1(n3823), .Y(n3821) );
OAI21XLTS U4949 ( .A0(n5149), .A1(n3818), .B0(n3821), .Y(n1838) );
AOI22X1TS U4950 ( .A0(add_subt_module_DmP[31]), .A1(n3839), .B0(
add_subt_module_intDY[31]), .B1(n3823), .Y(n3822) );
OAI21XLTS U4951 ( .A0(n5069), .A1(n3826), .B0(n3822), .Y(n1772) );
AOI22X1TS U4952 ( .A0(add_subt_module_DmP[33]), .A1(n3839), .B0(
add_subt_module_intDY[33]), .B1(n3823), .Y(n3824) );
OAI21XLTS U4953 ( .A0(n5171), .A1(n3818), .B0(n3824), .Y(n1754) );
AOI22X1TS U4954 ( .A0(add_subt_module_DmP[29]), .A1(n3883), .B0(
add_subt_module_intDY[29]), .B1(n2954), .Y(n3825) );
OAI21XLTS U4955 ( .A0(n5194), .A1(n3818), .B0(n3825), .Y(n1768) );
INVX4TS U4956 ( .A(n2954), .Y(n3867) );
AOI22X1TS U4957 ( .A0(n3865), .A1(add_subt_module_intDY[48]), .B0(
add_subt_module_DMP[48]), .B1(n3868), .Y(n3827) );
OAI21XLTS U4958 ( .A0(n5198), .A1(n3867), .B0(n3827), .Y(n1898) );
AOI22X1TS U4959 ( .A0(add_subt_module_DmP[48]), .A1(n3828), .B0(
add_subt_module_intDX[48]), .B1(n3865), .Y(n3829) );
AOI22X1TS U4960 ( .A0(n3865), .A1(add_subt_module_intDY[49]), .B0(
add_subt_module_DMP[49]), .B1(n3859), .Y(n3830) );
AOI22X1TS U4961 ( .A0(n3865), .A1(add_subt_module_intDY[46]), .B0(
add_subt_module_DMP[46]), .B1(n3879), .Y(n3831) );
OAI21XLTS U4962 ( .A0(n5151), .A1(n3867), .B0(n3831), .Y(n1874) );
INVX4TS U4963 ( .A(n3823), .Y(n3870) );
AOI22X1TS U4964 ( .A0(n3889), .A1(add_subt_module_intDX[52]), .B0(
add_subt_module_DmP[52]), .B1(n3868), .Y(n3832) );
OAI21XLTS U4965 ( .A0(n5163), .A1(n3870), .B0(n3832), .Y(n1911) );
AOI22X1TS U4966 ( .A0(n3865), .A1(add_subt_module_intDY[45]), .B0(
add_subt_module_DMP[45]), .B1(n3859), .Y(n3833) );
OAI21XLTS U4967 ( .A0(n5190), .A1(n3867), .B0(n3833), .Y(n1854) );
AOI22X1TS U4968 ( .A0(add_subt_module_DmP[51]), .A1(n3828), .B0(
add_subt_module_intDX[51]), .B1(n3865), .Y(n3834) );
OAI21XLTS U4969 ( .A0(n5236), .A1(n3867), .B0(n3834), .Y(n1905) );
AOI22X1TS U4970 ( .A0(n3865), .A1(add_subt_module_intDY[43]), .B0(
add_subt_module_DMP[43]), .B1(n3859), .Y(n3835) );
OAI21XLTS U4971 ( .A0(n5174), .A1(n3867), .B0(n3835), .Y(n1841) );
AOI22X1TS U4972 ( .A0(n3889), .A1(add_subt_module_intDY[41]), .B0(
add_subt_module_DMP[41]), .B1(n3859), .Y(n3836) );
OAI21XLTS U4973 ( .A0(n5157), .A1(n3867), .B0(n3836), .Y(n1813) );
AOI22X1TS U4974 ( .A0(add_subt_module_DmP[13]), .A1(n3868), .B0(
add_subt_module_intDX[13]), .B1(n3865), .Y(n3837) );
OAI21XLTS U4975 ( .A0(n5180), .A1(n3867), .B0(n3837), .Y(n1848) );
AOI22X1TS U4976 ( .A0(add_subt_module_DmP[0]), .A1(n3839), .B0(
add_subt_module_intDX[0]), .B1(n3838), .Y(n3840) );
OAI21XLTS U4977 ( .A0(n5201), .A1(n3870), .B0(n3840), .Y(n1908) );
AOI22X1TS U4978 ( .A0(n3865), .A1(add_subt_module_intDY[42]), .B0(
add_subt_module_DMP[42]), .B1(n3879), .Y(n3841) );
OAI21XLTS U4979 ( .A0(n5064), .A1(n3867), .B0(n3841), .Y(n1820) );
AOI22X1TS U4980 ( .A0(n3889), .A1(add_subt_module_intDX[59]), .B0(
add_subt_module_DmP[59]), .B1(n3868), .Y(n3842) );
OAI21XLTS U4981 ( .A0(n5073), .A1(n3870), .B0(n3842), .Y(n1932) );
AOI22X1TS U4982 ( .A0(n3838), .A1(add_subt_module_intDX[57]), .B0(
add_subt_module_DmP[57]), .B1(n3839), .Y(n3843) );
OAI21XLTS U4983 ( .A0(n5067), .A1(n3870), .B0(n3843), .Y(n1926) );
AOI22X1TS U4984 ( .A0(n3884), .A1(add_subt_module_intDY[35]), .B0(
add_subt_module_DMP[35]), .B1(n3879), .Y(n3844) );
OAI21XLTS U4985 ( .A0(n5191), .A1(n3870), .B0(n3844), .Y(n1789) );
AOI22X1TS U4986 ( .A0(n3884), .A1(add_subt_module_intDY[25]), .B0(
add_subt_module_DMP[25]), .B1(n3888), .Y(n3845) );
OAI21XLTS U4987 ( .A0(n5192), .A1(n3867), .B0(n3845), .Y(n1757) );
AOI22X1TS U4988 ( .A0(n3884), .A1(add_subt_module_intDY[29]), .B0(
add_subt_module_DMP[29]), .B1(n3888), .Y(n3846) );
OAI21XLTS U4989 ( .A0(n5194), .A1(n3870), .B0(n3846), .Y(n1767) );
AOI22X1TS U4990 ( .A0(n3884), .A1(add_subt_module_intDY[36]), .B0(
add_subt_module_DMP[36]), .B1(n3859), .Y(n3847) );
OAI21XLTS U4991 ( .A0(n5170), .A1(n3867), .B0(n3847), .Y(n1782) );
AOI22X1TS U4992 ( .A0(n3838), .A1(add_subt_module_intDX[61]), .B0(
add_subt_module_DmP[61]), .B1(n3868), .Y(n3848) );
OAI21XLTS U4993 ( .A0(n5169), .A1(n3870), .B0(n3848), .Y(n1938) );
AOI22X1TS U4994 ( .A0(n3889), .A1(add_subt_module_intDX[62]), .B0(
add_subt_module_DmP[62]), .B1(n3868), .Y(n3849) );
OAI21XLTS U4995 ( .A0(n5142), .A1(n3870), .B0(n3849), .Y(n1941) );
AOI22X1TS U4996 ( .A0(n3889), .A1(add_subt_module_intDX[58]), .B0(
add_subt_module_DmP[58]), .B1(n3868), .Y(n3850) );
OAI21XLTS U4997 ( .A0(n5141), .A1(n3870), .B0(n3850), .Y(n1929) );
AOI22X1TS U4998 ( .A0(n3838), .A1(add_subt_module_intDX[60]), .B0(
add_subt_module_DmP[60]), .B1(n3868), .Y(n3851) );
OAI21XLTS U4999 ( .A0(n5185), .A1(n3870), .B0(n3851), .Y(n1935) );
AOI22X1TS U5000 ( .A0(n3884), .A1(add_subt_module_intDY[27]), .B0(
add_subt_module_DMP[27]), .B1(n3879), .Y(n3852) );
OAI21XLTS U5001 ( .A0(n5071), .A1(n3870), .B0(n3852), .Y(n1775) );
AOI22X1TS U5002 ( .A0(n3884), .A1(add_subt_module_intDY[31]), .B0(
add_subt_module_DMP[31]), .B1(n3879), .Y(n3853) );
OAI21XLTS U5003 ( .A0(n5069), .A1(n3867), .B0(n3853), .Y(n1771) );
AOI22X1TS U5004 ( .A0(n3884), .A1(add_subt_module_intDY[33]), .B0(
add_subt_module_DMP[33]), .B1(n3888), .Y(n3854) );
OAI21XLTS U5005 ( .A0(n5171), .A1(n3870), .B0(n3854), .Y(n1753) );
AOI22X1TS U5006 ( .A0(n3865), .A1(add_subt_module_intDY[40]), .B0(
add_subt_module_DMP[40]), .B1(n3879), .Y(n3855) );
OAI21XLTS U5007 ( .A0(n5152), .A1(n3867), .B0(n3855), .Y(n1834) );
AOI22X1TS U5008 ( .A0(n3889), .A1(add_subt_module_intDX[56]), .B0(
add_subt_module_DmP[56]), .B1(n3868), .Y(n3856) );
OAI21XLTS U5009 ( .A0(n5150), .A1(n3870), .B0(n3856), .Y(n1923) );
AOI22X1TS U5010 ( .A0(n3865), .A1(add_subt_module_intDX[55]), .B0(
add_subt_module_DmP[55]), .B1(n3883), .Y(n3857) );
AOI22X1TS U5011 ( .A0(n3865), .A1(add_subt_module_intDY[44]), .B0(
add_subt_module_DMP[44]), .B1(n3868), .Y(n3858) );
OAI21XLTS U5012 ( .A0(n5143), .A1(n3867), .B0(n3858), .Y(n1864) );
AOI22X1TS U5013 ( .A0(n3865), .A1(add_subt_module_intDY[47]), .B0(
add_subt_module_DMP[47]), .B1(n3859), .Y(n3860) );
OAI21XLTS U5014 ( .A0(n5061), .A1(n3867), .B0(n3860), .Y(n1888) );
AOI22X1TS U5015 ( .A0(n3865), .A1(add_subt_module_intDY[37]), .B0(
add_subt_module_DMP[37]), .B1(n3879), .Y(n3861) );
OAI21XLTS U5016 ( .A0(n5153), .A1(n3870), .B0(n3861), .Y(n1806) );
AOI22X1TS U5017 ( .A0(n3884), .A1(add_subt_module_intDY[39]), .B0(
add_subt_module_DMP[39]), .B1(n3879), .Y(n3862) );
OAI21XLTS U5018 ( .A0(n5144), .A1(n3867), .B0(n3862), .Y(n1805) );
AOI22X1TS U5019 ( .A0(n3865), .A1(add_subt_module_intDX[53]), .B0(
add_subt_module_DmP[53]), .B1(n3828), .Y(n3863) );
OAI21XLTS U5020 ( .A0(n5068), .A1(n3870), .B0(n3863), .Y(n1914) );
AOI22X1TS U5021 ( .A0(n3884), .A1(n2987), .B0(add_subt_module_DMP[32]), .B1(
n3879), .Y(n3864) );
OAI21XLTS U5022 ( .A0(n5195), .A1(n3870), .B0(n3864), .Y(n1746) );
AOI22X1TS U5023 ( .A0(n3865), .A1(add_subt_module_intDY[38]), .B0(
add_subt_module_DMP[38]), .B1(n3888), .Y(n3866) );
OAI21XLTS U5024 ( .A0(n5074), .A1(n3867), .B0(n3866), .Y(n1830) );
AOI22X1TS U5025 ( .A0(n3889), .A1(add_subt_module_intDX[54]), .B0(
add_subt_module_DmP[54]), .B1(n3868), .Y(n3869) );
OAI21XLTS U5026 ( .A0(n5193), .A1(n3870), .B0(n3869), .Y(n1917) );
INVX4TS U5027 ( .A(n2954), .Y(n3891) );
AOI22X1TS U5028 ( .A0(n3838), .A1(add_subt_module_intDY[1]), .B0(
add_subt_module_DMP[1]), .B1(n3879), .Y(n3871) );
OAI21XLTS U5029 ( .A0(n5147), .A1(n3891), .B0(n3871), .Y(n1709) );
AOI22X1TS U5030 ( .A0(n3838), .A1(add_subt_module_intDY[11]), .B0(
add_subt_module_DMP[11]), .B1(n3879), .Y(n3872) );
OAI21XLTS U5031 ( .A0(n5172), .A1(n3891), .B0(n3872), .Y(n1719) );
AOI22X1TS U5032 ( .A0(n3838), .A1(add_subt_module_intDY[50]), .B0(
add_subt_module_DMP[50]), .B1(n3879), .Y(n3873) );
OAI21XLTS U5033 ( .A0(n5070), .A1(n3891), .B0(n3873), .Y(n1707) );
AOI22X1TS U5034 ( .A0(n3889), .A1(add_subt_module_intDY[16]), .B0(
add_subt_module_DMP[16]), .B1(n3888), .Y(n3874) );
OAI21XLTS U5035 ( .A0(n5146), .A1(n3891), .B0(n3874), .Y(n1710) );
AOI22X1TS U5036 ( .A0(n3838), .A1(add_subt_module_intDY[9]), .B0(
add_subt_module_DMP[9]), .B1(n3859), .Y(n3875) );
AOI22X1TS U5037 ( .A0(n3884), .A1(add_subt_module_intDY[12]), .B0(
add_subt_module_DMP[12]), .B1(n3879), .Y(n3876) );
OAI21XLTS U5038 ( .A0(n5196), .A1(n3891), .B0(n3876), .Y(n1718) );
AOI22X1TS U5039 ( .A0(n3889), .A1(add_subt_module_intDY[20]), .B0(
add_subt_module_DMP[20]), .B1(n3859), .Y(n3877) );
OAI21XLTS U5040 ( .A0(n5165), .A1(n3891), .B0(n3877), .Y(n1714) );
AOI22X1TS U5041 ( .A0(n3889), .A1(add_subt_module_intDY[10]), .B0(
add_subt_module_DMP[10]), .B1(n3888), .Y(n3878) );
OAI21XLTS U5042 ( .A0(n5156), .A1(n3891), .B0(n3878), .Y(n1716) );
AOI22X1TS U5043 ( .A0(n3884), .A1(add_subt_module_intDY[19]), .B0(
add_subt_module_DMP[19]), .B1(n3859), .Y(n3880) );
OAI21XLTS U5044 ( .A0(n5072), .A1(n3891), .B0(n3880), .Y(n1721) );
AOI22X1TS U5045 ( .A0(n3838), .A1(add_subt_module_intDY[8]), .B0(
add_subt_module_DMP[8]), .B1(n3879), .Y(n3881) );
OAI21XLTS U5046 ( .A0(n5187), .A1(n3891), .B0(n3881), .Y(n1720) );
AOI22X1TS U5047 ( .A0(n3889), .A1(add_subt_module_intDY[7]), .B0(
add_subt_module_DMP[7]), .B1(n3879), .Y(n3882) );
OAI21XLTS U5048 ( .A0(n5149), .A1(n3891), .B0(n3882), .Y(n1717) );
AOI22X1TS U5049 ( .A0(n3884), .A1(add_subt_module_intDY[51]), .B0(
add_subt_module_DMP[51]), .B1(n3883), .Y(n3885) );
OAI21XLTS U5050 ( .A0(n5199), .A1(n3891), .B0(n3885), .Y(n1704) );
AOI22X1TS U5051 ( .A0(n3838), .A1(add_subt_module_intDY[6]), .B0(
add_subt_module_DMP[6]), .B1(n3879), .Y(n3886) );
OAI21XLTS U5052 ( .A0(n5145), .A1(n3891), .B0(n3886), .Y(n1712) );
AOI22X1TS U5053 ( .A0(n3889), .A1(add_subt_module_intDY[13]), .B0(
add_subt_module_DMP[13]), .B1(n3859), .Y(n3887) );
OAI21XLTS U5054 ( .A0(n5181), .A1(n3891), .B0(n3887), .Y(n1715) );
AOI22X1TS U5055 ( .A0(n3889), .A1(add_subt_module_intDY[5]), .B0(
add_subt_module_DMP[5]), .B1(n3879), .Y(n3890) );
OAI21XLTS U5056 ( .A0(n5155), .A1(n3891), .B0(n3890), .Y(n1713) );
NOR2X1TS U5057 ( .A(add_subt_module_Add_Subt_result[10]), .B(n5200), .Y(
n3992) );
NOR2X1TS U5058 ( .A(add_subt_module_Add_Subt_result[16]), .B(
add_subt_module_Add_Subt_result[17]), .Y(n3895) );
NOR2X1TS U5059 ( .A(add_subt_module_Add_Subt_result[20]), .B(
add_subt_module_Add_Subt_result[19]), .Y(n3976) );
NOR2X1TS U5060 ( .A(add_subt_module_Add_Subt_result[52]), .B(
add_subt_module_Add_Subt_result[51]), .Y(n4009) );
NOR2X1TS U5061 ( .A(add_subt_module_Add_Subt_result[54]), .B(
add_subt_module_Add_Subt_result[53]), .Y(n4019) );
NAND2X1TS U5062 ( .A(n4009), .B(n4019), .Y(n3957) );
NOR4X2TS U5063 ( .A(add_subt_module_Add_Subt_result[48]), .B(
add_subt_module_Add_Subt_result[50]), .C(
add_subt_module_Add_Subt_result[49]), .D(n3957), .Y(n4751) );
NOR2X1TS U5064 ( .A(add_subt_module_Add_Subt_result[40]), .B(n2984), .Y(
n4012) );
NAND2BX1TS U5065 ( .AN(n3943), .B(n4012), .Y(n4749) );
NOR2X1TS U5066 ( .A(add_subt_module_Add_Subt_result[37]), .B(
add_subt_module_Add_Subt_result[38]), .Y(n3980) );
NOR3X1TS U5067 ( .A(add_subt_module_Add_Subt_result[29]), .B(
add_subt_module_Add_Subt_result[28]), .C(n3960), .Y(n3972) );
NOR2X2TS U5068 ( .A(add_subt_module_Add_Subt_result[24]), .B(n3966), .Y(
n3973) );
NOR3BX1TS U5069 ( .AN(n3973), .B(add_subt_module_Add_Subt_result[23]), .C(
n2983), .Y(n3941) );
NAND2BX1TS U5070 ( .AN(add_subt_module_Add_Subt_result[21]), .B(n3941), .Y(
n3975) );
INVX2TS U5071 ( .A(n3975), .Y(n3946) );
NOR2X2TS U5072 ( .A(add_subt_module_Add_Subt_result[18]), .B(n3894), .Y(
n4757) );
NOR2X2TS U5073 ( .A(add_subt_module_Add_Subt_result[15]), .B(n3902), .Y(
n3964) );
NOR2X1TS U5074 ( .A(add_subt_module_Add_Subt_result[12]), .B(
add_subt_module_Add_Subt_result[11]), .Y(n3901) );
NAND4X1TS U5075 ( .A(n3964), .B(n3901), .C(n5161), .D(n5051), .Y(n4006) );
INVX2TS U5076 ( .A(n4006), .Y(n3991) );
OAI21X1TS U5077 ( .A0(add_subt_module_Add_Subt_result[13]), .A1(n5078), .B0(
n5051), .Y(n3963) );
AOI21X1TS U5078 ( .A0(n5161), .A1(n5052), .B0(n3951), .Y(n3897) );
NAND2X1TS U5079 ( .A(n3949), .B(n3900), .Y(n3989) );
NOR3X1TS U5080 ( .A(add_subt_module_Add_Subt_result[4]), .B(
add_subt_module_Add_Subt_result[3]), .C(n3989), .Y(n3898) );
NAND2X1TS U5081 ( .A(n3898), .B(n5230), .Y(n4760) );
NOR3X1TS U5082 ( .A(add_subt_module_Add_Subt_result[1]), .B(n5232), .C(n4760), .Y(n3971) );
AOI21X1TS U5083 ( .A0(n3900), .A1(n5230), .B0(n3899), .Y(n3907) );
NAND2X1TS U5084 ( .A(n5217), .B(n5046), .Y(n3988) );
OR4X2TS U5085 ( .A(add_subt_module_Add_Subt_result[13]), .B(
add_subt_module_Add_Subt_result[14]), .C(n3901), .D(n3902), .Y(n3903)
);
OAI211X1TS U5086 ( .A0(n3905), .A1(n3904), .B0(n3903), .C0(n4752), .Y(n4020)
);
NAND2X2TS U5087 ( .A(n4107), .B(n5114), .Y(n4024) );
INVX2TS U5088 ( .A(n4024), .Y(n4763) );
OAI21X1TS U5089 ( .A0(n5221), .A1(n4760), .B0(n4763), .Y(n3985) );
NOR4X1TS U5090 ( .A(n3971), .B(n3907), .C(n4020), .D(n3985), .Y(n3909) );
NAND2X1TS U5091 ( .A(n4024), .B(n5313), .Y(n3908) );
OAI2BB1X1TS U5092 ( .A0N(n3910), .A1N(n3909), .B0(n3908), .Y(n3911) );
INVX2TS U5093 ( .A(n3911), .Y(n2589) );
INVX2TS U5094 ( .A(n4612), .Y(n3913) );
OAI31X1TS U5095 ( .A0(n5050), .A1(n5114), .A2(n3913), .B0(n3912), .Y(n2650)
);
INVX2TS U5096 ( .A(n3919), .Y(n3918) );
OAI21XLTS U5097 ( .A0(d_ff1_operation_out), .A1(
d_ff1_shift_region_flag_out[0]), .B0(n3916), .Y(n3917) );
XNOR2X1TS U5098 ( .A(d_ff1_shift_region_flag_out[1]), .B(n3917), .Y(n4737)
);
AOI22X1TS U5099 ( .A0(cordic_FSM_state_reg[1]), .A1(n5124), .B0(
cordic_FSM_state_reg[0]), .B1(n5057), .Y(n4651) );
NOR3X1TS U5100 ( .A(n4633), .B(n4735), .C(n4729), .Y(n3920) );
OAI31X1TS U5101 ( .A0(cordic_FSM_state_reg[3]), .A1(n3921), .A2(n4651), .B0(
n3920), .Y(cordic_FSM_state_next_1_) );
INVX2TS U5102 ( .A(n3922), .Y(n3923) );
OAI222X1TS U5103 ( .A0(n5242), .A1(n3123), .B0(n2976), .B1(n3925), .C0(n3924), .C1(n3923), .Y(n2537) );
CLKAND2X2TS U5104 ( .A(n2953), .B(add_subt_module_DmP[62]), .Y(n3926) );
XOR2X1TS U5105 ( .A(add_subt_module_FSM_exp_operation_A_S), .B(n3926), .Y(
DP_OP_92J137_122_9081_n16) );
CLKAND2X2TS U5106 ( .A(n2953), .B(add_subt_module_DmP[61]), .Y(n3927) );
XOR2X1TS U5107 ( .A(add_subt_module_FSM_exp_operation_A_S), .B(n3927), .Y(
DP_OP_92J137_122_9081_n17) );
CLKAND2X2TS U5108 ( .A(n2953), .B(add_subt_module_DmP[60]), .Y(n3928) );
XOR2X1TS U5109 ( .A(add_subt_module_FSM_exp_operation_A_S), .B(n3928), .Y(
DP_OP_92J137_122_9081_n18) );
CLKAND2X2TS U5110 ( .A(n2953), .B(add_subt_module_DmP[59]), .Y(n3929) );
XOR2X1TS U5111 ( .A(add_subt_module_FSM_exp_operation_A_S), .B(n3929), .Y(
DP_OP_92J137_122_9081_n19) );
CLKAND2X2TS U5112 ( .A(n2953), .B(add_subt_module_DmP[58]), .Y(n3930) );
XOR2X1TS U5113 ( .A(add_subt_module_FSM_exp_operation_A_S), .B(n3930), .Y(
DP_OP_92J137_122_9081_n20) );
OAI2BB1X1TS U5114 ( .A0N(add_subt_module_DmP[57]), .A1N(n2953), .B0(n3931),
.Y(n3932) );
XOR2X1TS U5115 ( .A(add_subt_module_FSM_exp_operation_A_S), .B(n3932), .Y(
DP_OP_92J137_122_9081_n21) );
AO22XLTS U5116 ( .A0(add_subt_module_LZA_output[4]), .A1(n3124), .B0(n2953),
.B1(add_subt_module_DmP[56]), .Y(n3933) );
XOR2X1TS U5117 ( .A(add_subt_module_FSM_exp_operation_A_S), .B(n3933), .Y(
DP_OP_92J137_122_9081_n22) );
AO22XLTS U5118 ( .A0(add_subt_module_LZA_output[3]), .A1(n3124), .B0(n2953),
.B1(add_subt_module_DmP[55]), .Y(n3934) );
XOR2X1TS U5119 ( .A(add_subt_module_FSM_exp_operation_A_S), .B(n3934), .Y(
DP_OP_92J137_122_9081_n23) );
AO22XLTS U5120 ( .A0(add_subt_module_LZA_output[2]), .A1(n3124), .B0(n2953),
.B1(add_subt_module_DmP[54]), .Y(n3935) );
XOR2X1TS U5121 ( .A(add_subt_module_FSM_exp_operation_A_S), .B(n3935), .Y(
DP_OP_92J137_122_9081_n24) );
AO22XLTS U5122 ( .A0(add_subt_module_LZA_output[1]), .A1(n3124), .B0(n2953),
.B1(add_subt_module_DmP[53]), .Y(n3936) );
XOR2X1TS U5123 ( .A(add_subt_module_FSM_exp_operation_A_S), .B(n3936), .Y(
DP_OP_92J137_122_9081_n25) );
NOR2XLTS U5124 ( .A(add_subt_module_FSM_selector_B[1]), .B(
add_subt_module_DmP[52]), .Y(n3938) );
OAI21XLTS U5125 ( .A0(add_subt_module_FSM_selector_B[0]), .A1(n3938), .B0(
n3937), .Y(n3939) );
XOR2X1TS U5126 ( .A(add_subt_module_FSM_exp_operation_A_S), .B(n3939), .Y(
DP_OP_92J137_122_9081_n26) );
AOI21X1TS U5127 ( .A0(n2984), .A1(n5220), .B0(
add_subt_module_Add_Subt_result[41]), .Y(n3944) );
NOR2XLTS U5128 ( .A(add_subt_module_Add_Subt_result[4]), .B(n5046), .Y(n3940) );
NAND2X1TS U5129 ( .A(add_subt_module_Add_Subt_result[21]), .B(n3941), .Y(
n3982) );
AOI31X1TS U5130 ( .A0(add_subt_module_Add_Subt_result[19]), .A1(n3946), .A2(
n5231), .B0(n3945), .Y(n4759) );
OAI21XLTS U5131 ( .A0(add_subt_module_Add_Subt_result[42]), .A1(
add_subt_module_Add_Subt_result[40]), .B0(n3947), .Y(n3948) );
OAI211X1TS U5132 ( .A0(n3975), .A1(n5231), .B0(n4759), .C0(n3948), .Y(n3950)
);
AOI21X1TS U5133 ( .A0(add_subt_module_Add_Subt_result[27]), .A1(n5204), .B0(
add_subt_module_Add_Subt_result[29]), .Y(n3955) );
AOI21X1TS U5134 ( .A0(n5161), .A1(n5077), .B0(n3951), .Y(n3952) );
AOI211X1TS U5135 ( .A0(add_subt_module_Add_Subt_result[47]), .A1(n4751),
.B0(n3952), .C0(n4024), .Y(n3954) );
AOI32X1TS U5136 ( .A0(add_subt_module_Add_Subt_result[31]), .A1(n3977), .A2(
n5219), .B0(add_subt_module_Add_Subt_result[33]), .B1(n3977), .Y(n3953) );
OAI211X1TS U5137 ( .A0(n3955), .A1(n3960), .B0(n3954), .C0(n3953), .Y(n4756)
);
NAND2X1TS U5138 ( .A(n3973), .B(n2983), .Y(n3996) );
INVX2TS U5139 ( .A(n3956), .Y(n4745) );
NOR3X1TS U5140 ( .A(add_subt_module_Add_Subt_result[48]), .B(
add_subt_module_Add_Subt_result[50]), .C(
add_subt_module_Add_Subt_result[49]), .Y(n3958) );
OAI22X1TS U5141 ( .A0(add_subt_module_Add_Subt_result[35]), .A1(n3986), .B0(
n3958), .B1(n3957), .Y(n3959) );
AOI2BB1XLTS U5142 ( .A0N(n5219), .A1N(n3968), .B0(n3959), .Y(n3961) );
MX2X1TS U5143 ( .A(add_subt_module_exp_oper_result[10]), .B(
add_subt_module_Exp_Operation_Module_Data_S[10]), .S0(n3114), .Y(n2652) );
BUFX6TS U5144 ( .A(add_subt_module_FSM_selector_D), .Y(n4102) );
MX2X1TS U5145 ( .A(add_subt_module_DMP[62]), .B(
add_subt_module_exp_oper_result[10]), .S0(n4102), .Y(
add_subt_module_S_Oper_A_exp[10]) );
MX2X1TS U5146 ( .A(add_subt_module_exp_oper_result[9]), .B(
add_subt_module_Exp_Operation_Module_Data_S[9]), .S0(n3114), .Y(n2662)
);
MX2X1TS U5147 ( .A(add_subt_module_DMP[61]), .B(
add_subt_module_exp_oper_result[9]), .S0(n4102), .Y(
add_subt_module_S_Oper_A_exp[9]) );
MX2X1TS U5148 ( .A(add_subt_module_exp_oper_result[8]), .B(
add_subt_module_Exp_Operation_Module_Data_S[8]), .S0(n3114), .Y(n2661)
);
MX2X1TS U5149 ( .A(add_subt_module_DMP[60]), .B(
add_subt_module_exp_oper_result[8]), .S0(n4087), .Y(
add_subt_module_S_Oper_A_exp[8]) );
MX2X1TS U5150 ( .A(add_subt_module_exp_oper_result[7]), .B(
add_subt_module_Exp_Operation_Module_Data_S[7]), .S0(n3114), .Y(n2660)
);
BUFX4TS U5151 ( .A(add_subt_module_FSM_selector_D), .Y(n4071) );
MX2X1TS U5152 ( .A(add_subt_module_DMP[59]), .B(
add_subt_module_exp_oper_result[7]), .S0(n4071), .Y(
add_subt_module_S_Oper_A_exp[7]) );
MX2X1TS U5153 ( .A(add_subt_module_exp_oper_result[6]), .B(
add_subt_module_Exp_Operation_Module_Data_S[6]), .S0(n3114), .Y(n2659)
);
MX2X1TS U5154 ( .A(add_subt_module_DMP[58]), .B(
add_subt_module_exp_oper_result[6]), .S0(n4071), .Y(
add_subt_module_S_Oper_A_exp[6]) );
MX2X1TS U5155 ( .A(add_subt_module_DMP[57]), .B(
add_subt_module_exp_oper_result[5]), .S0(n4071), .Y(
add_subt_module_S_Oper_A_exp[5]) );
MX2X1TS U5156 ( .A(add_subt_module_exp_oper_result[4]), .B(
add_subt_module_Exp_Operation_Module_Data_S[4]), .S0(n3114), .Y(n2657)
);
MX2X1TS U5157 ( .A(add_subt_module_DMP[56]), .B(
add_subt_module_exp_oper_result[4]), .S0(n4071), .Y(
add_subt_module_S_Oper_A_exp[4]) );
MX2X1TS U5158 ( .A(add_subt_module_exp_oper_result[3]), .B(
add_subt_module_Exp_Operation_Module_Data_S[3]), .S0(n3114), .Y(n2656)
);
BUFX4TS U5159 ( .A(add_subt_module_FSM_selector_D), .Y(n4057) );
MX2X1TS U5160 ( .A(add_subt_module_DMP[55]), .B(
add_subt_module_exp_oper_result[3]), .S0(n4057), .Y(
add_subt_module_S_Oper_A_exp[3]) );
MX2X1TS U5161 ( .A(add_subt_module_exp_oper_result[2]), .B(
add_subt_module_Exp_Operation_Module_Data_S[2]), .S0(n3114), .Y(n2655)
);
MX2X1TS U5162 ( .A(add_subt_module_DMP[54]), .B(
add_subt_module_exp_oper_result[2]), .S0(n4057), .Y(
add_subt_module_S_Oper_A_exp[2]) );
MX2X1TS U5163 ( .A(add_subt_module_exp_oper_result[1]), .B(
add_subt_module_Exp_Operation_Module_Data_S[1]), .S0(n3114), .Y(n2654)
);
MX2X1TS U5164 ( .A(add_subt_module_DMP[53]), .B(
add_subt_module_exp_oper_result[1]), .S0(n4057), .Y(
add_subt_module_S_Oper_A_exp[1]) );
MX2X1TS U5165 ( .A(add_subt_module_exp_oper_result[0]), .B(
add_subt_module_Exp_Operation_Module_Data_S[0]), .S0(n3114), .Y(n2653)
);
MX2X1TS U5166 ( .A(add_subt_module_DMP[52]), .B(
add_subt_module_exp_oper_result[0]), .S0(n4057), .Y(
add_subt_module_S_Oper_A_exp[0]) );
OA22X1TS U5167 ( .A0(n4024), .A1(add_subt_module_add_overflow_flag), .B0(
n4107), .B1(add_subt_module_FSM_selector_B[1]), .Y(n2935) );
NOR2XLTS U5168 ( .A(add_subt_module_Add_Subt_result[32]), .B(
add_subt_module_Add_Subt_result[31]), .Y(n3969) );
OAI21XLTS U5169 ( .A0(add_subt_module_Add_Subt_result[36]), .A1(
add_subt_module_Add_Subt_result[35]), .B0(n4745), .Y(n3967) );
NAND2X1TS U5170 ( .A(n3973), .B(add_subt_module_Add_Subt_result[23]), .Y(
n3995) );
OAI211X1TS U5171 ( .A0(n3976), .A1(n3975), .B0(n3974), .C0(n3995), .Y(n4017)
);
OR2X1TS U5172 ( .A(add_subt_module_Add_Subt_result[29]), .B(
add_subt_module_Add_Subt_result[28]), .Y(n3978) );
OAI31X1TS U5173 ( .A0(add_subt_module_Add_Subt_result[27]), .A1(n3978), .A2(
n5214), .B0(n5055), .Y(n4001) );
OAI31X1TS U5174 ( .A0(add_subt_module_Add_Subt_result[33]), .A1(n3978), .A2(
n4001), .B0(n3977), .Y(n3979) );
OAI31X1TS U5175 ( .A0(add_subt_module_Add_Subt_result[41]), .A1(n3980), .A2(
n4749), .B0(n3979), .Y(n3984) );
NAND2X1TS U5176 ( .A(add_subt_module_Add_Subt_result[25]), .B(n3981), .Y(
n3994) );
NOR4BX1TS U5177 ( .AN(n3986), .B(n3985), .C(n3984), .D(n3983), .Y(n3987) );
OAI31X1TS U5178 ( .A0(n3989), .A1(n3988), .A2(n5230), .B0(n3987), .Y(n3990)
);
OA22X1TS U5179 ( .A0(n4017), .A1(n3990), .B0(n4763), .B1(
add_subt_module_LZA_output[4]), .Y(n2590) );
AOI21X1TS U5180 ( .A0(add_subt_module_Add_Subt_result[8]), .A1(n5200), .B0(
add_subt_module_Add_Subt_result[10]), .Y(n4005) );
NAND2X1TS U5181 ( .A(add_subt_module_Add_Subt_result[43]), .B(n4011), .Y(
n4013) );
NOR2XLTS U5182 ( .A(add_subt_module_Add_Subt_result[46]), .B(
add_subt_module_Add_Subt_result[45]), .Y(n4008) );
OAI31X1TS U5183 ( .A0(add_subt_module_Add_Subt_result[50]), .A1(
add_subt_module_Add_Subt_result[49]), .A2(n4010), .B0(n4009), .Y(n4018) );
AOI211X1TS U5184 ( .A0(n4019), .A1(n4018), .B0(n4017), .C0(n4016), .Y(n4022)
);
AOI21X1TS U5185 ( .A0(n4022), .A1(n4021), .B0(n4024), .Y(n4023) );
MX2X1TS U5186 ( .A(add_subt_module_exp_oper_result[5]), .B(
add_subt_module_Exp_Operation_Module_Data_S[5]), .S0(n3114), .Y(n2658)
);
AO22XLTS U5187 ( .A0(n4829), .A1(d_ff2_X[63]), .B0(d_ff3_sh_x_out[63]), .B1(
n4726), .Y(n2794) );
BUFX3TS U5188 ( .A(n4817), .Y(n4801) );
BUFX3TS U5189 ( .A(n4801), .Y(n4730) );
AO22XLTS U5190 ( .A0(n4819), .A1(d_ff2_Y[63]), .B0(d_ff3_sh_y_out[63]), .B1(
n4730), .Y(n2091) );
XNOR2X1TS U5191 ( .A(cont_var_out[0]), .B(d_ff3_sign_out), .Y(n4026) );
MX2X1TS U5192 ( .A(add_subt_module_intAS), .B(n4026), .S0(n4025), .Y(n1944)
);
AOI2BB1XLTS U5193 ( .A0N(n4027), .A1N(n4609), .B0(add_subt_module_intDX[63]),
.Y(n4031) );
AOI21X1TS U5194 ( .A0(n3535), .A1(n4029), .B0(n3823), .Y(n4030) );
OAI22X1TS U5195 ( .A0(n4031), .A1(n4030), .B0(n3535), .B1(n5243), .Y(n1943)
);
INVX2TS U5196 ( .A(n4032), .Y(n4620) );
AO21XLTS U5197 ( .A0(n4621), .A1(n4620), .B0(n4057), .Y(n2663) );
AOI22X1TS U5198 ( .A0(n4034), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[90]), .B0(
n4033), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[106]), .Y(
n4036) );
OAI211XLTS U5199 ( .A0(n4037), .A1(n5228), .B0(n4036), .C0(n4035), .Y(n4038)
);
AOI21X1TS U5200 ( .A0(n3134), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[82]), .B0(
n4038), .Y(n4040) );
AOI2BB2XLTS U5201 ( .B0(n4040), .B1(n3123), .A0N(
add_subt_module_Sgf_normalized_result[27]), .A1N(n3123), .Y(n2562) );
NOR2BX1TS U5202 ( .AN(add_subt_module_Sgf_normalized_result[54]), .B(n4102),
.Y(n4041) );
XOR2X1TS U5203 ( .A(n4113), .B(n4041), .Y(n4110) );
NOR2XLTS U5204 ( .A(n5233), .B(n4057), .Y(n4042) );
XOR2X1TS U5205 ( .A(n4113), .B(n4042), .Y(n4122) );
NOR2XLTS U5206 ( .A(n5234), .B(n4057), .Y(n4043) );
XOR2X1TS U5207 ( .A(n4113), .B(n4043), .Y(n4126) );
NOR2XLTS U5208 ( .A(n5224), .B(n4057), .Y(n4044) );
XOR2X1TS U5209 ( .A(n4113), .B(n4044), .Y(n4134) );
NOR2XLTS U5210 ( .A(n5225), .B(n4057), .Y(n4045) );
XOR2X1TS U5211 ( .A(n4113), .B(n4045), .Y(n4142) );
NOR2XLTS U5212 ( .A(n5207), .B(n4057), .Y(n4046) );
XOR2X1TS U5213 ( .A(n4113), .B(n4046), .Y(n4154) );
NOR2XLTS U5214 ( .A(n5202), .B(n4057), .Y(n4047) );
XOR2X1TS U5215 ( .A(n4113), .B(n4047), .Y(n4162) );
NOR2XLTS U5216 ( .A(n5203), .B(n4057), .Y(n4048) );
XOR2X1TS U5217 ( .A(n4113), .B(n4048), .Y(n4170) );
NOR2XLTS U5218 ( .A(n5183), .B(n4071), .Y(n4049) );
XOR2X1TS U5219 ( .A(n4113), .B(n4049), .Y(n4178) );
NOR2XLTS U5220 ( .A(n5184), .B(n4057), .Y(n4050) );
XOR2X1TS U5221 ( .A(n4113), .B(n4050), .Y(n4182) );
NOR2XLTS U5222 ( .A(n5166), .B(n4057), .Y(n4051) );
XOR2X1TS U5223 ( .A(n4113), .B(n4051), .Y(n4194) );
NOR2XLTS U5224 ( .A(n5167), .B(n4057), .Y(n4052) );
XOR2X1TS U5225 ( .A(n4113), .B(n4052), .Y(n4198) );
NOR2XLTS U5226 ( .A(n5139), .B(n4057), .Y(n4054) );
XOR2X1TS U5227 ( .A(n4101), .B(n4054), .Y(n4206) );
MX2X1TS U5228 ( .A(add_subt_module_DMP[39]), .B(
add_subt_module_Sgf_normalized_result[41]), .S0(n4064), .Y(n4215) );
NOR2XLTS U5229 ( .A(n5140), .B(n4057), .Y(n4055) );
XOR2X1TS U5230 ( .A(n4113), .B(n4055), .Y(n4214) );
XOR2X1TS U5231 ( .A(n4113), .B(n4056), .Y(n4226) );
MX2X1TS U5232 ( .A(add_subt_module_DMP[37]), .B(
add_subt_module_Sgf_normalized_result[39]), .S0(n4064), .Y(n4231) );
NOR2XLTS U5233 ( .A(n5136), .B(n4057), .Y(n4058) );
XOR2X1TS U5234 ( .A(n4113), .B(n4058), .Y(n4230) );
XOR2X1TS U5235 ( .A(n4101), .B(n4059), .Y(n4238) );
MX2X1TS U5236 ( .A(add_subt_module_DMP[35]), .B(
add_subt_module_Sgf_normalized_result[37]), .S0(n4064), .Y(n4247) );
NOR2XLTS U5237 ( .A(n5121), .B(n4071), .Y(n4060) );
XOR2X1TS U5238 ( .A(n4101), .B(n4060), .Y(n4246) );
XOR2X1TS U5239 ( .A(n4101), .B(n4061), .Y(n4258) );
MX2X1TS U5240 ( .A(add_subt_module_DMP[33]), .B(
add_subt_module_Sgf_normalized_result[35]), .S0(n4064), .Y(n4267) );
XOR2X1TS U5241 ( .A(n4101), .B(n4062), .Y(n4266) );
XOR2X1TS U5242 ( .A(n4101), .B(n4063), .Y(n4274) );
MX2X1TS U5243 ( .A(add_subt_module_DMP[31]), .B(
add_subt_module_Sgf_normalized_result[33]), .S0(n4064), .Y(n4283) );
XOR2X1TS U5244 ( .A(n4101), .B(n4065), .Y(n4282) );
XOR2X1TS U5245 ( .A(n4101), .B(n4066), .Y(n4290) );
MX2X1TS U5246 ( .A(add_subt_module_DMP[29]), .B(
add_subt_module_Sgf_normalized_result[31]), .S0(n4086), .Y(n4295) );
XOR2X1TS U5247 ( .A(n4101), .B(n4067), .Y(n4294) );
XOR2X1TS U5248 ( .A(n4101), .B(n4068), .Y(n4306) );
MX2X1TS U5249 ( .A(add_subt_module_DMP[27]), .B(
add_subt_module_Sgf_normalized_result[29]), .S0(n4086), .Y(n4311) );
XOR2X1TS U5250 ( .A(n4101), .B(n4069), .Y(n4310) );
XOR2X1TS U5251 ( .A(n4101), .B(n4070), .Y(n4319) );
MX2X1TS U5252 ( .A(add_subt_module_DMP[25]), .B(
add_subt_module_Sgf_normalized_result[27]), .S0(n4086), .Y(n4329) );
XOR2X1TS U5253 ( .A(n4101), .B(n4072), .Y(n4328) );
XOR2X1TS U5254 ( .A(n4101), .B(n4073), .Y(n4323) );
XOR2X1TS U5255 ( .A(n4101), .B(n4074), .Y(n4314) );
XOR2X1TS U5256 ( .A(n4101), .B(n4075), .Y(n4302) );
XOR2X1TS U5257 ( .A(n4101), .B(n4076), .Y(n4298) );
XOR2X1TS U5258 ( .A(n4101), .B(n4077), .Y(n4286) );
XOR2X1TS U5259 ( .A(n4104), .B(n4078), .Y(n4278) );
XOR2X1TS U5260 ( .A(n4104), .B(n4079), .Y(n4270) );
XOR2X1TS U5261 ( .A(n4104), .B(n4080), .Y(n4262) );
XOR2X1TS U5262 ( .A(n4104), .B(n4081), .Y(n4254) );
XOR2X1TS U5263 ( .A(n4104), .B(n4082), .Y(n4250) );
XOR2X1TS U5264 ( .A(n4104), .B(n4083), .Y(n4242) );
XOR2X1TS U5265 ( .A(n4104), .B(n4084), .Y(n4234) );
XOR2X1TS U5266 ( .A(n4104), .B(n4085), .Y(n4222) );
XOR2X1TS U5267 ( .A(n4104), .B(n4088), .Y(n4218) );
XOR2X1TS U5268 ( .A(n4104), .B(n4089), .Y(n4209) );
XOR2X1TS U5269 ( .A(n4104), .B(n4090), .Y(n4201) );
XOR2X1TS U5270 ( .A(n4104), .B(n4091), .Y(n4189) );
XOR2X1TS U5271 ( .A(n4104), .B(n4092), .Y(n4185) );
XOR2X1TS U5272 ( .A(n4104), .B(n4093), .Y(n4173) );
XOR2X1TS U5273 ( .A(n4104), .B(n4094), .Y(n4165) );
XOR2X1TS U5274 ( .A(n4104), .B(n4095), .Y(n4157) );
XOR2X1TS U5275 ( .A(n4104), .B(n4096), .Y(n4149) );
XOR2X1TS U5276 ( .A(n4104), .B(n4097), .Y(n4145) );
XOR2X1TS U5277 ( .A(n4104), .B(n4098), .Y(n4137) );
XOR2X1TS U5278 ( .A(n4101), .B(n2990), .Y(n4129) );
NOR2BX1TS U5279 ( .AN(add_subt_module_Sgf_normalized_result[1]), .B(n4102),
.Y(n4100) );
XOR2X1TS U5280 ( .A(n4101), .B(n4100), .Y(n4117) );
NOR2BX1TS U5281 ( .AN(add_subt_module_Sgf_normalized_result[0]), .B(n4102),
.Y(n4103) );
XOR2X1TS U5282 ( .A(n4113), .B(n4103), .Y(n4112) );
XOR2X1TS U5283 ( .A(n4105), .B(n4104), .Y(n4106) );
MXI2X1TS U5284 ( .A(n5134), .B(add_subt_module_add_overflow_flag), .S0(n4107), .Y(n2664) );
CMPR32X2TS U5285 ( .A(n4110), .B(n4109), .C(n4108), .CO(n4105), .S(n4111) );
AFHCONX2TS U5286 ( .A(n4114), .B(n4113), .CI(n4112), .CON(n4116), .S(n4115)
);
MX2X1TS U5287 ( .A(add_subt_module_Add_Subt_result[0]), .B(n4115), .S0(n4325), .Y(n2596) );
AFHCINX2TS U5288 ( .CIN(n4116), .B(n4117), .A(n4118), .S(n4119), .CO(n4128)
);
MX2X1TS U5289 ( .A(add_subt_module_Add_Subt_result[1]), .B(n4119), .S0(n4330), .Y(n2597) );
CMPR32X2TS U5290 ( .A(n4122), .B(n4121), .C(n4120), .CO(n4108), .S(n4123) );
CMPR32X2TS U5291 ( .A(n4126), .B(n4125), .C(n4124), .CO(n4120), .S(n4127) );
AFHCONX2TS U5292 ( .A(n4130), .B(n4129), .CI(n4128), .CON(n4136), .S(n4131)
);
MX2X1TS U5293 ( .A(add_subt_module_Add_Subt_result[2]), .B(n4131), .S0(n4316), .Y(n2598) );
CMPR32X2TS U5294 ( .A(n4134), .B(n4133), .C(n4132), .CO(n4124), .S(n4135) );
AFHCINX2TS U5295 ( .CIN(n4136), .B(n4137), .A(n4138), .S(n4139), .CO(n4144)
);
MX2X1TS U5296 ( .A(add_subt_module_Add_Subt_result[3]), .B(n4139), .S0(n4325), .Y(n2599) );
CMPR32X2TS U5297 ( .A(n4142), .B(n4141), .C(n4140), .CO(n4132), .S(n4143) );
AFHCONX2TS U5298 ( .A(n4146), .B(n4145), .CI(n4144), .CON(n4148), .S(n4147)
);
MX2X1TS U5299 ( .A(add_subt_module_Add_Subt_result[4]), .B(n4147), .S0(n4330), .Y(n2600) );
AFHCINX2TS U5300 ( .CIN(n4148), .B(n4149), .A(n4150), .S(n4151), .CO(n4156)
);
MX2X1TS U5301 ( .A(add_subt_module_Add_Subt_result[5]), .B(n4151), .S0(n4325), .Y(n2601) );
CMPR32X2TS U5302 ( .A(n4154), .B(n4153), .C(n4152), .CO(n4140), .S(n4155) );
AFHCONX2TS U5303 ( .A(n4158), .B(n4157), .CI(n4156), .CON(n4164), .S(n4159)
);
MX2X1TS U5304 ( .A(add_subt_module_Add_Subt_result[6]), .B(n4159), .S0(n4316), .Y(n2602) );
CMPR32X2TS U5305 ( .A(n4162), .B(n4161), .C(n4160), .CO(n4152), .S(n4163) );
AFHCINX2TS U5306 ( .CIN(n4164), .B(n4165), .A(n4166), .S(n4167), .CO(n4172)
);
MX2X1TS U5307 ( .A(add_subt_module_Add_Subt_result[7]), .B(n4167), .S0(n4316), .Y(n2603) );
CMPR32X2TS U5308 ( .A(n4170), .B(n4169), .C(n4168), .CO(n4160), .S(n4171) );
AFHCONX2TS U5309 ( .A(n4174), .B(n4173), .CI(n4172), .CON(n4184), .S(n4175)
);
MX2X1TS U5310 ( .A(add_subt_module_Add_Subt_result[8]), .B(n4175), .S0(n4316), .Y(n2604) );
CMPR32X2TS U5311 ( .A(n4178), .B(n4177), .C(n4176), .CO(n4168), .S(n4179) );
CMPR32X2TS U5312 ( .A(n4182), .B(n4181), .C(n4180), .CO(n4176), .S(n4183) );
AFHCINX2TS U5313 ( .CIN(n4184), .B(n4185), .A(n4186), .S(n4187), .CO(n4188)
);
MX2X1TS U5314 ( .A(add_subt_module_Add_Subt_result[9]), .B(n4187), .S0(n4316), .Y(n2605) );
AFHCONX2TS U5315 ( .A(n4190), .B(n4189), .CI(n4188), .CON(n4200), .S(n4191)
);
MX2X1TS U5316 ( .A(add_subt_module_Add_Subt_result[10]), .B(n4191), .S0(
n4316), .Y(n2606) );
CMPR32X2TS U5317 ( .A(n4194), .B(n4193), .C(n4192), .CO(n4180), .S(n4195) );
CMPR32X2TS U5318 ( .A(n4198), .B(n4197), .C(n4196), .CO(n4192), .S(n4199) );
AFHCINX2TS U5319 ( .CIN(n4200), .B(n4201), .A(n4202), .S(n4203), .CO(n4208)
);
MX2X1TS U5320 ( .A(add_subt_module_Add_Subt_result[11]), .B(n4203), .S0(
n4316), .Y(n2607) );
CMPR32X2TS U5321 ( .A(n4206), .B(n4205), .C(n4204), .CO(n4196), .S(n4207) );
AFHCONX2TS U5322 ( .A(n4210), .B(n4209), .CI(n4208), .CON(n4217), .S(n4212)
);
MX2X1TS U5323 ( .A(add_subt_module_Add_Subt_result[12]), .B(n4212), .S0(
n4316), .Y(n2608) );
AFHCINX2TS U5324 ( .CIN(n4213), .B(n4214), .A(n4215), .S(n4216), .CO(n4204)
);
AFHCINX2TS U5325 ( .CIN(n4217), .B(n4218), .A(n4219), .S(n4220), .CO(n4221)
);
MX2X1TS U5326 ( .A(add_subt_module_Add_Subt_result[13]), .B(n4220), .S0(
n4330), .Y(n2609) );
AFHCONX2TS U5327 ( .A(n4223), .B(n4222), .CI(n4221), .CON(n4233), .S(n4224)
);
MX2X1TS U5328 ( .A(add_subt_module_Add_Subt_result[14]), .B(n4224), .S0(
n4325), .Y(n2610) );
AFHCONX2TS U5329 ( .A(n4227), .B(n4226), .CI(n4225), .CON(n4213), .S(n4228)
);
AFHCINX2TS U5330 ( .CIN(n4229), .B(n4230), .A(n4231), .S(n4232), .CO(n4225)
);
AFHCINX2TS U5331 ( .CIN(n4233), .B(n4234), .A(n4235), .S(n4236), .CO(n4241)
);
MX2X1TS U5332 ( .A(add_subt_module_Add_Subt_result[15]), .B(n4236), .S0(
n4316), .Y(n2611) );
AFHCONX2TS U5333 ( .A(n4239), .B(n4238), .CI(n4237), .CON(n4229), .S(n4240)
);
AFHCONX2TS U5334 ( .A(n4243), .B(n4242), .CI(n4241), .CON(n4249), .S(n4244)
);
MX2X1TS U5335 ( .A(add_subt_module_Add_Subt_result[16]), .B(n4244), .S0(
n4330), .Y(n2612) );
AFHCINX2TS U5336 ( .CIN(n4245), .B(n4246), .A(n4247), .S(n4248), .CO(n4237)
);
AFHCINX2TS U5337 ( .CIN(n4249), .B(n4250), .A(n4251), .S(n4252), .CO(n4253)
);
MX2X1TS U5338 ( .A(add_subt_module_Add_Subt_result[17]), .B(n4252), .S0(
n4316), .Y(n2613) );
AFHCONX2TS U5339 ( .A(n4255), .B(n4254), .CI(n4253), .CON(n4261), .S(n4256)
);
MX2X1TS U5340 ( .A(add_subt_module_Add_Subt_result[18]), .B(n4256), .S0(
n4316), .Y(n2614) );
AFHCONX2TS U5341 ( .A(n4259), .B(n4258), .CI(n4257), .CON(n4245), .S(n4260)
);
AFHCINX2TS U5342 ( .CIN(n4261), .B(n4262), .A(n4263), .S(n4264), .CO(n4269)
);
MX2X1TS U5343 ( .A(add_subt_module_Add_Subt_result[19]), .B(n4264), .S0(
n4316), .Y(n2615) );
AFHCINX2TS U5344 ( .CIN(n4265), .B(n4266), .A(n4267), .S(n4268), .CO(n4257)
);
AFHCONX2TS U5345 ( .A(n4271), .B(n4270), .CI(n4269), .CON(n4277), .S(n4272)
);
MX2X1TS U5346 ( .A(add_subt_module_Add_Subt_result[20]), .B(n4272), .S0(
n4316), .Y(n2616) );
AFHCONX2TS U5347 ( .A(n4275), .B(n4274), .CI(n4273), .CON(n4265), .S(n4276)
);
AFHCINX2TS U5348 ( .CIN(n4277), .B(n4278), .A(n4279), .S(n4280), .CO(n4285)
);
MX2X1TS U5349 ( .A(add_subt_module_Add_Subt_result[21]), .B(n4280), .S0(
n4316), .Y(n2617) );
AFHCINX2TS U5350 ( .CIN(n4281), .B(n4282), .A(n4283), .S(n4284), .CO(n4273)
);
AFHCONX2TS U5351 ( .A(n4287), .B(n4286), .CI(n4285), .CON(n4297), .S(n4288)
);
MX2X1TS U5352 ( .A(n2983), .B(n4288), .S0(n4316), .Y(n2618) );
AFHCONX2TS U5353 ( .A(n4291), .B(n4290), .CI(n4289), .CON(n4281), .S(n4292)
);
AFHCINX2TS U5354 ( .CIN(n4293), .B(n4294), .A(n4295), .S(n4296), .CO(n4289)
);
AFHCINX2TS U5355 ( .CIN(n4297), .B(n4298), .A(n4299), .S(n4300), .CO(n4301)
);
MX2X1TS U5356 ( .A(add_subt_module_Add_Subt_result[23]), .B(n4300), .S0(
n4316), .Y(n2619) );
AFHCONX2TS U5357 ( .A(n4303), .B(n4302), .CI(n4301), .CON(n4313), .S(n4304)
);
MX2X1TS U5358 ( .A(add_subt_module_Add_Subt_result[24]), .B(n4304), .S0(
n4316), .Y(n2620) );
AFHCONX2TS U5359 ( .A(n4307), .B(n4306), .CI(n4305), .CON(n4293), .S(n4308)
);
AFHCINX2TS U5360 ( .CIN(n4309), .B(n4310), .A(n4311), .S(n4312), .CO(n4305)
);
AFHCINX2TS U5361 ( .CIN(n4313), .B(n4314), .A(n4315), .S(n4317), .CO(n4322)
);
MX2X1TS U5362 ( .A(add_subt_module_Add_Subt_result[25]), .B(n4317), .S0(
n4316), .Y(n2621) );
AFHCONX2TS U5363 ( .A(n4320), .B(n4319), .CI(n4318), .CON(n4309), .S(n4321)
);
AFHCONX2TS U5364 ( .A(n4324), .B(n4323), .CI(n4322), .CON(n4327), .S(n4326)
);
MX2X1TS U5365 ( .A(add_subt_module_Add_Subt_result[26]), .B(n4326), .S0(
n4316), .Y(n2622) );
AFHCINX2TS U5366 ( .CIN(n4327), .B(n4328), .A(n4329), .S(n4331), .CO(n4318)
);
MX2X1TS U5367 ( .A(add_subt_module_Add_Subt_result[27]), .B(n4331), .S0(
n4325), .Y(n2623) );
AOI22X1TS U5368 ( .A0(add_subt_module_Add_Subt_result[50]), .A1(n4578), .B0(
add_subt_module_DmP[48]), .B1(n4479), .Y(n4332) );
AOI22X1TS U5369 ( .A0(n4579), .A1(n4350), .B0(n4550), .B1(n4343), .Y(n4333)
);
OAI21XLTS U5370 ( .A0(n4340), .A1(n4487), .B0(n4333), .Y(n4334) );
AOI21X1TS U5371 ( .A0(n4587), .A1(n4335), .B0(n4334), .Y(n4356) );
AOI22X1TS U5372 ( .A0(n4451), .A1(n4356), .B0(n4336), .B1(n4393), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[50]) );
AOI22X1TS U5373 ( .A0(add_subt_module_Add_Subt_result[5]), .A1(n4577), .B0(
add_subt_module_DmP[47]), .B1(n4479), .Y(n4338) );
AOI22X1TS U5374 ( .A0(n4538), .A1(n4343), .B0(n4579), .B1(n4355), .Y(n4339)
);
OAI21XLTS U5375 ( .A0(n4340), .A1(n4533), .B0(n4339), .Y(n4341) );
AOI21X1TS U5376 ( .A0(n4589), .A1(n4350), .B0(n4341), .Y(n4361) );
AOI22X1TS U5377 ( .A0(n4451), .A1(n4361), .B0(n4342), .B1(n4393), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[49]) );
AOI222X4TS U5378 ( .A0(n4622), .A1(add_subt_module_DmP[46]), .B0(
add_subt_module_Add_Subt_result[6]), .B1(n4577), .C0(
add_subt_module_Add_Subt_result[48]), .C1(n4569), .Y(n4359) );
AOI22X1TS U5379 ( .A0(n4540), .A1(n4343), .B0(n4589), .B1(n4355), .Y(n4344)
);
OAI21XLTS U5380 ( .A0(n4359), .A1(n3309), .B0(n4344), .Y(n4345) );
AOI21X1TS U5381 ( .A0(n4538), .A1(n4350), .B0(n4345), .Y(n4365) );
AOI22X1TS U5382 ( .A0(n4451), .A1(n4365), .B0(n4346), .B1(n4393), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[48]) );
OAI22X1TS U5383 ( .A0(add_subt_module_FSM_selector_C), .A1(
add_subt_module_DmP[45]), .B0(add_subt_module_Add_Subt_result[7]),
.B1(n4583), .Y(n4347) );
AOI22X1TS U5384 ( .A0(n4591), .A1(n4355), .B0(n4579), .B1(n4362), .Y(n4348)
);
OAI21XLTS U5385 ( .A0(n4359), .A1(n3537), .B0(n4348), .Y(n4349) );
AOI21X1TS U5386 ( .A0(n4587), .A1(n4350), .B0(n4349), .Y(n4369) );
AOI22X1TS U5387 ( .A0(n4451), .A1(n4369), .B0(n4351), .B1(n4393), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[47]) );
AOI22X1TS U5388 ( .A0(add_subt_module_Add_Subt_result[8]), .A1(n4577), .B0(
add_subt_module_DmP[44]), .B1(n4479), .Y(n4352) );
AOI22X1TS U5389 ( .A0(n4579), .A1(n4366), .B0(n4550), .B1(n4362), .Y(n4353)
);
OAI21XLTS U5390 ( .A0(n4359), .A1(n4487), .B0(n4353), .Y(n4354) );
AOI21X1TS U5391 ( .A0(n4587), .A1(n4355), .B0(n4354), .Y(n4374) );
AOI22X1TS U5392 ( .A0(n4417), .A1(n4374), .B0(n4356), .B1(n4393), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[46]) );
AOI22X1TS U5393 ( .A0(add_subt_module_Add_Subt_result[45]), .A1(n4578), .B0(
add_subt_module_DmP[43]), .B1(n4479), .Y(n4357) );
AOI22X1TS U5394 ( .A0(n4579), .A1(n4371), .B0(n4550), .B1(n4366), .Y(n4358)
);
OAI21XLTS U5395 ( .A0(n4359), .A1(n4533), .B0(n4358), .Y(n4360) );
AOI21X1TS U5396 ( .A0(n4591), .A1(n4362), .B0(n4360), .Y(n4379) );
AOI22X1TS U5397 ( .A0(n4451), .A1(n4379), .B0(n4361), .B1(n4393), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[45]) );
AOI222X4TS U5398 ( .A0(n4622), .A1(add_subt_module_DmP[42]), .B0(
add_subt_module_Add_Subt_result[10]), .B1(n4577), .C0(
add_subt_module_Add_Subt_result[44]), .C1(n4569), .Y(n4377) );
AOI22X1TS U5399 ( .A0(n4540), .A1(n4362), .B0(n4550), .B1(n4371), .Y(n4363)
);
OAI21XLTS U5400 ( .A0(n4377), .A1(n3309), .B0(n4363), .Y(n4364) );
AOI21X1TS U5401 ( .A0(n4538), .A1(n4366), .B0(n4364), .Y(n4383) );
AOI22X1TS U5402 ( .A0(n4417), .A1(n4383), .B0(n4365), .B1(n4393), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[44]) );
AOI222X4TS U5403 ( .A0(n4622), .A1(n5209), .B0(n5048), .B1(n4569), .C0(n5077), .C1(n4537), .Y(n4380) );
AOI22X1TS U5404 ( .A0(n4540), .A1(n4366), .B0(n4538), .B1(n4371), .Y(n4367)
);
OAI21XLTS U5405 ( .A0(n4377), .A1(n3537), .B0(n4367), .Y(n4368) );
AOI21X1TS U5406 ( .A0(n4585), .A1(n4380), .B0(n4368), .Y(n4388) );
AOI22X1TS U5407 ( .A0(n4417), .A1(n4388), .B0(n4369), .B1(n4393), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[43]) );
AOI22X1TS U5408 ( .A0(add_subt_module_Add_Subt_result[42]), .A1(n4578), .B0(
add_subt_module_DmP[40]), .B1(n4479), .Y(n4370) );
AOI22X1TS U5409 ( .A0(n4540), .A1(n4371), .B0(n4579), .B1(n4385), .Y(n4372)
);
AOI21X1TS U5410 ( .A0(n4550), .A1(n4380), .B0(n4373), .Y(n4394) );
AOI22X1TS U5411 ( .A0(n4451), .A1(n4394), .B0(n4374), .B1(n4393), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[42]) );
AOI22X1TS U5412 ( .A0(add_subt_module_Add_Subt_result[41]), .A1(n4578), .B0(
add_subt_module_DmP[39]), .B1(n4479), .Y(n4375) );
AOI22X1TS U5413 ( .A0(n4538), .A1(n4380), .B0(n4589), .B1(n4385), .Y(n4376)
);
OAI21XLTS U5414 ( .A0(n4377), .A1(n4533), .B0(n4376), .Y(n4378) );
AOI21X1TS U5415 ( .A0(n4559), .A1(n4392), .B0(n4378), .Y(n4399) );
AOI22X1TS U5416 ( .A0(n4451), .A1(n4399), .B0(n4379), .B1(n4393), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[41]) );
AOI222X4TS U5417 ( .A0(n4622), .A1(add_subt_module_DmP[38]), .B0(
add_subt_module_Add_Subt_result[14]), .B1(n4577), .C0(
add_subt_module_Add_Subt_result[40]), .C1(n4569), .Y(n4397) );
AOI22X1TS U5418 ( .A0(n4540), .A1(n4380), .B0(n4538), .B1(n4385), .Y(n4381)
);
OAI21XLTS U5419 ( .A0(n4397), .A1(n3309), .B0(n4381), .Y(n4382) );
AOI21X1TS U5420 ( .A0(n4550), .A1(n4392), .B0(n4382), .Y(n4403) );
AOI22X1TS U5421 ( .A0(n4417), .A1(n4403), .B0(n4383), .B1(n4393), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[40]) );
OAI22X1TS U5422 ( .A0(add_subt_module_FSM_selector_C), .A1(
add_subt_module_DmP[37]), .B0(n2984), .B1(n4337), .Y(n4384) );
AOI2BB1X2TS U5423 ( .A0N(n4562), .A1N(add_subt_module_Add_Subt_result[15]),
.B0(n4384), .Y(n4400) );
AOI22X1TS U5424 ( .A0(n4540), .A1(n4385), .B0(n4538), .B1(n4392), .Y(n4386)
);
OAI21XLTS U5425 ( .A0(n4397), .A1(n3537), .B0(n4386), .Y(n4387) );
AOI21X1TS U5426 ( .A0(n4559), .A1(n4400), .B0(n4387), .Y(n4408) );
AOI22X1TS U5427 ( .A0(n4451), .A1(n4408), .B0(n4388), .B1(n4393), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[39]) );
AOI22X1TS U5428 ( .A0(add_subt_module_Add_Subt_result[38]), .A1(n4578), .B0(
add_subt_module_DmP[36]), .B1(n4479), .Y(n4389) );
AOI22X1TS U5429 ( .A0(n4579), .A1(n4405), .B0(n4589), .B1(n4400), .Y(n4390)
);
OAI21XLTS U5430 ( .A0(n4397), .A1(n4487), .B0(n4390), .Y(n4391) );
AOI21X1TS U5431 ( .A0(n4587), .A1(n4392), .B0(n4391), .Y(n4412) );
AOI22X1TS U5432 ( .A0(n4417), .A1(n4412), .B0(n4394), .B1(n4393), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[38]) );
BUFX4TS U5433 ( .A(n4530), .Y(n4524) );
AOI22X1TS U5434 ( .A0(add_subt_module_Add_Subt_result[37]), .A1(n4578), .B0(
add_subt_module_DmP[35]), .B1(n4479), .Y(n4395) );
AOI22X1TS U5435 ( .A0(n4538), .A1(n4400), .B0(n4550), .B1(n4405), .Y(n4396)
);
AOI21X1TS U5436 ( .A0(n4559), .A1(n4409), .B0(n4398), .Y(n4416) );
AOI22X1TS U5437 ( .A0(n4524), .A1(n4416), .B0(n4399), .B1(n4503), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[37]) );
AOI222X4TS U5438 ( .A0(n4622), .A1(add_subt_module_DmP[34]), .B0(
add_subt_module_Add_Subt_result[18]), .B1(n4577), .C0(
add_subt_module_Add_Subt_result[36]), .C1(n4569), .Y(n4413) );
AOI22X1TS U5439 ( .A0(n4540), .A1(n4400), .B0(n4550), .B1(n4409), .Y(n4401)
);
OAI21XLTS U5440 ( .A0(n4413), .A1(n3309), .B0(n4401), .Y(n4402) );
AOI21X1TS U5441 ( .A0(n4591), .A1(n4405), .B0(n4402), .Y(n4420) );
AOI22X1TS U5442 ( .A0(n4417), .A1(n4420), .B0(n4403), .B1(n4503), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[36]) );
OAI22X1TS U5443 ( .A0(add_subt_module_FSM_selector_C), .A1(
add_subt_module_DmP[33]), .B0(add_subt_module_Add_Subt_result[19]),
.B1(n4583), .Y(n4404) );
AOI22X1TS U5444 ( .A0(n4540), .A1(n4405), .B0(n4538), .B1(n4409), .Y(n4406)
);
OAI21XLTS U5445 ( .A0(n4413), .A1(n3537), .B0(n4406), .Y(n4407) );
AOI21X1TS U5446 ( .A0(n4559), .A1(n2967), .B0(n4407), .Y(n4424) );
AOI22X1TS U5447 ( .A0(n4417), .A1(n4424), .B0(n4408), .B1(n4503), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[35]) );
AOI222X4TS U5448 ( .A0(n4622), .A1(add_subt_module_DmP[32]), .B0(
add_subt_module_Add_Subt_result[20]), .B1(n4577), .C0(
add_subt_module_Add_Subt_result[34]), .C1(n4569), .Y(n4421) );
AOI2BB2XLTS U5449 ( .B0(n4587), .B1(n4409), .A0N(n4487), .A1N(n4413), .Y(
n4410) );
OAI21XLTS U5450 ( .A0(n4421), .A1(n3309), .B0(n4410), .Y(n4411) );
AOI21X1TS U5451 ( .A0(n4550), .A1(n2967), .B0(n4411), .Y(n4429) );
AOI22X1TS U5452 ( .A0(n4417), .A1(n4429), .B0(n4412), .B1(n4503), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[34]) );
NOR2XLTS U5453 ( .A(n4421), .B(n3537), .Y(n4415) );
AOI222X4TS U5454 ( .A0(n4622), .A1(add_subt_module_DmP[31]), .B0(
add_subt_module_Add_Subt_result[21]), .B1(n4537), .C0(
add_subt_module_Add_Subt_result[33]), .C1(n4569), .Y(n4426) );
OAI22X1TS U5455 ( .A0(n4426), .A1(n3309), .B0(n4413), .B1(n4533), .Y(n4414)
);
AOI211X1TS U5456 ( .A0(n2967), .A1(n4538), .B0(n4415), .C0(n4414), .Y(n4434)
);
AOI22X1TS U5457 ( .A0(n4417), .A1(n4434), .B0(n4416), .B1(n4503), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[33]) );
NOR2XLTS U5458 ( .A(n4426), .B(n3537), .Y(n4419) );
AOI222X4TS U5459 ( .A0(n4622), .A1(add_subt_module_DmP[30]), .B0(n2983),
.B1(n4537), .C0(add_subt_module_Add_Subt_result[32]), .C1(n4569), .Y(
n4431) );
OAI22X1TS U5460 ( .A0(n4421), .A1(n4487), .B0(n4431), .B1(n3309), .Y(n4418)
);
AOI211X1TS U5461 ( .A0(n2967), .A1(n4540), .B0(n4419), .C0(n4418), .Y(n4438)
);
AOI22X1TS U5462 ( .A0(n4530), .A1(n4438), .B0(n4420), .B1(n4503), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[32]) );
OAI222X4TS U5463 ( .A0(n4337), .A1(add_subt_module_Add_Subt_result[31]),
.B0(n4583), .B1(add_subt_module_Add_Subt_result[23]), .C0(
add_subt_module_FSM_selector_C), .C1(add_subt_module_DmP[29]), .Y(
n4436) );
OAI22X1TS U5464 ( .A0(n4431), .A1(n3537), .B0(n3309), .B1(n4436), .Y(n4423)
);
OAI22X1TS U5465 ( .A0(n4421), .A1(n4533), .B0(n4426), .B1(n4487), .Y(n4422)
);
NOR2X1TS U5466 ( .A(n4423), .B(n4422), .Y(n4441) );
AOI22X1TS U5467 ( .A0(n4524), .A1(n4441), .B0(n4424), .B1(n4503), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[31]) );
AOI22X1TS U5468 ( .A0(add_subt_module_Add_Subt_result[24]), .A1(n4577), .B0(
add_subt_module_DmP[28]), .B1(n4479), .Y(n4425) );
OAI22X1TS U5469 ( .A0(n4426), .A1(n4533), .B0(n4436), .B1(n3537), .Y(n4427)
);
AOI211X1TS U5470 ( .A0(n4585), .A1(n4440), .B0(n4428), .C0(n4427), .Y(n4447)
);
AOI22X1TS U5471 ( .A0(n4530), .A1(n4447), .B0(n4429), .B1(n4503), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[30]) );
AOI22X1TS U5472 ( .A0(add_subt_module_Add_Subt_result[29]), .A1(n4578), .B0(
add_subt_module_DmP[27]), .B1(n4479), .Y(n4430) );
OAI2BB2XLTS U5473 ( .B0(n4431), .B1(n4533), .A0N(n4440), .A1N(n4589), .Y(
n4432) );
AOI211X1TS U5474 ( .A0(n4585), .A1(n4445), .B0(n4433), .C0(n4432), .Y(n4452)
);
AOI22X1TS U5475 ( .A0(n4524), .A1(n4452), .B0(n4434), .B1(n4503), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[29]) );
OAI222X1TS U5476 ( .A0(n4337), .A1(add_subt_module_Add_Subt_result[28]),
.B0(n4583), .B1(add_subt_module_Add_Subt_result[26]), .C0(
add_subt_module_FSM_selector_C), .C1(add_subt_module_DmP[26]), .Y(
n4439) );
INVX2TS U5477 ( .A(n4439), .Y(n4446) );
AOI22X1TS U5478 ( .A0(n4591), .A1(n4440), .B0(n4589), .B1(n4445), .Y(n4435)
);
OAI21XLTS U5479 ( .A0(n4533), .A1(n4436), .B0(n4435), .Y(n4437) );
AOI21X1TS U5480 ( .A0(n4585), .A1(n4446), .B0(n4437), .Y(n4455) );
AOI22X1TS U5481 ( .A0(n4524), .A1(n4455), .B0(n4438), .B1(n4503), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[28]) );
AOI22X1TS U5482 ( .A0(add_subt_module_FSM_selector_C), .A1(
add_subt_module_Add_Subt_result[27]), .B0(add_subt_module_DmP[25]),
.B1(n4479), .Y(n4443) );
AOI22X1TS U5483 ( .A0(n4444), .A1(n4443), .B0(n4439), .B1(n4442), .Y(n4450)
);
AOI22X1TS U5484 ( .A0(n4524), .A1(n4459), .B0(n4441), .B1(n4503), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[27]) );
AOI22X1TS U5485 ( .A0(n4444), .A1(n4448), .B0(n4443), .B1(n4442), .Y(n4454)
);
AOI22X1TS U5486 ( .A0(n4524), .A1(n4464), .B0(n4447), .B1(n4503), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[26]) );
INVX2TS U5487 ( .A(n4448), .Y(n4458) );
AOI22X1TS U5488 ( .A0(add_subt_module_Add_Subt_result[29]), .A1(n4577), .B0(
add_subt_module_DmP[23]), .B1(n4479), .Y(n4449) );
AOI22X1TS U5489 ( .A0(n4524), .A1(n4469), .B0(n4452), .B1(n4513), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[25]) );
AOI22X1TS U5490 ( .A0(add_subt_module_Add_Subt_result[24]), .A1(n4578), .B0(
add_subt_module_DmP[22]), .B1(n4479), .Y(n4453) );
AOI22X1TS U5491 ( .A0(n4524), .A1(n4474), .B0(n4455), .B1(n4513), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[24]) );
OAI222X4TS U5492 ( .A0(n4583), .A1(add_subt_module_Add_Subt_result[31]),
.B0(n4337), .B1(add_subt_module_Add_Subt_result[23]), .C0(
add_subt_module_FSM_selector_C), .C1(add_subt_module_DmP[21]), .Y(
n4472) );
AOI22X1TS U5493 ( .A0(n4591), .A1(n4461), .B0(n4589), .B1(n4466), .Y(n4456)
);
OAI21XLTS U5494 ( .A0(n3309), .A1(n4472), .B0(n4456), .Y(n4457) );
AOI21X1TS U5495 ( .A0(n4587), .A1(n4458), .B0(n4457), .Y(n4478) );
AOI22X1TS U5496 ( .A0(n4524), .A1(n4478), .B0(n4459), .B1(n4513), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[23]) );
AOI22X1TS U5497 ( .A0(n2983), .A1(n4578), .B0(add_subt_module_DmP[20]), .B1(
n4479), .Y(n4460) );
AOI22X1TS U5498 ( .A0(n4540), .A1(n4461), .B0(n4538), .B1(n4466), .Y(n4462)
);
OAI21XLTS U5499 ( .A0(n3537), .A1(n4472), .B0(n4462), .Y(n4463) );
AOI21X1TS U5500 ( .A0(n4559), .A1(n4475), .B0(n4463), .Y(n4484) );
AOI22X1TS U5501 ( .A0(n4524), .A1(n4484), .B0(n4464), .B1(n4513), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[22]) );
AOI22X1TS U5502 ( .A0(add_subt_module_Add_Subt_result[21]), .A1(n4578), .B0(
add_subt_module_DmP[19]), .B1(n4479), .Y(n4465) );
AOI22X1TS U5503 ( .A0(n4540), .A1(n4466), .B0(n4550), .B1(n4475), .Y(n4467)
);
OAI21XLTS U5504 ( .A0(n4487), .A1(n4472), .B0(n4467), .Y(n4468) );
AOI21X1TS U5505 ( .A0(n4585), .A1(n4481), .B0(n4468), .Y(n4489) );
AOI22X1TS U5506 ( .A0(n4524), .A1(n4489), .B0(n4469), .B1(n4513), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[21]) );
AOI22X1TS U5507 ( .A0(add_subt_module_Add_Subt_result[20]), .A1(n4578), .B0(
add_subt_module_DmP[18]), .B1(n4479), .Y(n4470) );
AOI22X1TS U5508 ( .A0(n4591), .A1(n4475), .B0(n4550), .B1(n4481), .Y(n4471)
);
OAI21XLTS U5509 ( .A0(n4533), .A1(n4472), .B0(n4471), .Y(n4473) );
AOI21X1TS U5510 ( .A0(n4585), .A1(n4485), .B0(n4473), .Y(n4494) );
AOI22X1TS U5511 ( .A0(n4524), .A1(n4494), .B0(n4474), .B1(n4513), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[20]) );
OAI222X4TS U5512 ( .A0(n4583), .A1(add_subt_module_Add_Subt_result[35]),
.B0(n4337), .B1(add_subt_module_Add_Subt_result[19]), .C0(
add_subt_module_FSM_selector_C), .C1(add_subt_module_DmP[17]), .Y(
n4492) );
AOI22X1TS U5513 ( .A0(n4540), .A1(n4475), .B0(n4589), .B1(n4485), .Y(n4476)
);
OAI21XLTS U5514 ( .A0(n3309), .A1(n4492), .B0(n4476), .Y(n4477) );
AOI21X1TS U5515 ( .A0(n4591), .A1(n4481), .B0(n4477), .Y(n4498) );
AOI22X1TS U5516 ( .A0(n4524), .A1(n4498), .B0(n4478), .B1(n4513), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[19]) );
AOI22X1TS U5517 ( .A0(add_subt_module_Add_Subt_result[18]), .A1(n4578), .B0(
add_subt_module_DmP[16]), .B1(n4479), .Y(n4480) );
AOI22X1TS U5518 ( .A0(n4540), .A1(n4481), .B0(n4579), .B1(n4495), .Y(n4482)
);
OAI21XLTS U5519 ( .A0(n3537), .A1(n4492), .B0(n4482), .Y(n4483) );
AOI21X1TS U5520 ( .A0(n4538), .A1(n4485), .B0(n4483), .Y(n4504) );
AOI22X1TS U5521 ( .A0(n4524), .A1(n4504), .B0(n4484), .B1(n4513), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[18]) );
AOI222X4TS U5522 ( .A0(n4622), .A1(n5210), .B0(n5076), .B1(n4537), .C0(n5053), .C1(n4569), .Y(n4500) );
AOI22X1TS U5523 ( .A0(n4540), .A1(n4485), .B0(n4579), .B1(n4500), .Y(n4486)
);
OAI21XLTS U5524 ( .A0(n4487), .A1(n4492), .B0(n4486), .Y(n4488) );
AOI21X1TS U5525 ( .A0(n4589), .A1(n4495), .B0(n4488), .Y(n4509) );
AOI22X1TS U5526 ( .A0(n4530), .A1(n4509), .B0(n4489), .B1(n4513), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[17]) );
OAI22X1TS U5527 ( .A0(add_subt_module_FSM_selector_C), .A1(
add_subt_module_DmP[14]), .B0(add_subt_module_Add_Subt_result[38]),
.B1(n4583), .Y(n4490) );
AOI22X1TS U5528 ( .A0(n4591), .A1(n4495), .B0(n4579), .B1(n4506), .Y(n4491)
);
OAI21XLTS U5529 ( .A0(n4533), .A1(n4492), .B0(n4491), .Y(n4493) );
AOI21X1TS U5530 ( .A0(n4550), .A1(n4500), .B0(n4493), .Y(n4514) );
AOI22X1TS U5531 ( .A0(n4524), .A1(n4514), .B0(n4494), .B1(n4513), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[16]) );
OAI222X4TS U5532 ( .A0(n4583), .A1(n2984), .B0(n4337), .B1(
add_subt_module_Add_Subt_result[15]), .C0(
add_subt_module_FSM_selector_C), .C1(add_subt_module_DmP[13]), .Y(
n4511) );
AOI22X1TS U5533 ( .A0(n4540), .A1(n4495), .B0(n4550), .B1(n4506), .Y(n4496)
);
OAI21XLTS U5534 ( .A0(n3309), .A1(n4511), .B0(n4496), .Y(n4497) );
AOI21X1TS U5535 ( .A0(n4591), .A1(n4500), .B0(n4497), .Y(n4518) );
AOI22X1TS U5536 ( .A0(n4530), .A1(n4518), .B0(n4498), .B1(n4513), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[15]) );
AOI22X1TS U5537 ( .A0(add_subt_module_Add_Subt_result[14]), .A1(n4578), .B0(
add_subt_module_DmP[12]), .B1(n4622), .Y(n4499) );
AOI22X1TS U5538 ( .A0(n4540), .A1(n4500), .B0(n4538), .B1(n4506), .Y(n4501)
);
OAI21XLTS U5539 ( .A0(n3537), .A1(n4511), .B0(n4501), .Y(n4502) );
AOI21X1TS U5540 ( .A0(n4559), .A1(n4515), .B0(n4502), .Y(n4523) );
AOI22X1TS U5541 ( .A0(n4524), .A1(n4523), .B0(n4504), .B1(n4503), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[14]) );
AOI22X1TS U5542 ( .A0(add_subt_module_Add_Subt_result[13]), .A1(n4578), .B0(
add_subt_module_DmP[11]), .B1(n4622), .Y(n4505) );
AOI22X1TS U5543 ( .A0(n4540), .A1(n4506), .B0(n4579), .B1(n4522), .Y(n4507)
);
OAI21XLTS U5544 ( .A0(n4487), .A1(n4511), .B0(n4507), .Y(n4508) );
AOI21X1TS U5545 ( .A0(n4589), .A1(n4515), .B0(n4508), .Y(n4529) );
AOI22X1TS U5546 ( .A0(n4530), .A1(n4529), .B0(n4509), .B1(n4513), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[13]) );
AOI222X4TS U5547 ( .A0(n4622), .A1(n5211), .B0(n5047), .B1(n4537), .C0(n5078), .C1(n4569), .Y(n4526) );
AOI22X1TS U5548 ( .A0(n4591), .A1(n4515), .B0(n4589), .B1(n4522), .Y(n4510)
);
AOI21X1TS U5549 ( .A0(n4585), .A1(n4526), .B0(n4512), .Y(n4536) );
AOI22X1TS U5550 ( .A0(n4524), .A1(n4536), .B0(n4514), .B1(n4513), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[12]) );
AOI222X4TS U5551 ( .A0(n4622), .A1(add_subt_module_DmP[9]), .B0(
add_subt_module_Add_Subt_result[11]), .B1(n4569), .C0(
add_subt_module_Add_Subt_result[43]), .C1(n4537), .Y(n4534) );
AOI22X1TS U5552 ( .A0(n4540), .A1(n4515), .B0(n4589), .B1(n4526), .Y(n4516)
);
OAI21XLTS U5553 ( .A0(n4534), .A1(n3309), .B0(n4516), .Y(n4517) );
AOI21X1TS U5554 ( .A0(n4538), .A1(n4522), .B0(n4517), .Y(n4543) );
AOI22X1TS U5555 ( .A0(n4530), .A1(n4543), .B0(n4518), .B1(n4592), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[11]) );
AOI22X1TS U5556 ( .A0(add_subt_module_Add_Subt_result[44]), .A1(n4577), .B0(
add_subt_module_DmP[8]), .B1(n4622), .Y(n4519) );
AOI22X1TS U5557 ( .A0(n4591), .A1(n4526), .B0(n4579), .B1(n4539), .Y(n4520)
);
OAI21XLTS U5558 ( .A0(n4534), .A1(n3537), .B0(n4520), .Y(n4521) );
AOI21X1TS U5559 ( .A0(n4587), .A1(n4522), .B0(n4521), .Y(n4548) );
AOI22X1TS U5560 ( .A0(n4524), .A1(n4548), .B0(n4523), .B1(n4592), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[10]) );
OAI22X1TS U5561 ( .A0(add_subt_module_FSM_selector_C), .A1(
add_subt_module_DmP[7]), .B0(add_subt_module_Add_Subt_result[45]),
.B1(n4583), .Y(n4525) );
AOI22X1TS U5562 ( .A0(n4540), .A1(n4526), .B0(n4579), .B1(n4545), .Y(n4527)
);
OAI21XLTS U5563 ( .A0(n4534), .A1(n4487), .B0(n4527), .Y(n4528) );
AOI21X1TS U5564 ( .A0(n4589), .A1(n4539), .B0(n4528), .Y(n4554) );
AOI22X1TS U5565 ( .A0(n4530), .A1(n4554), .B0(n4529), .B1(n4592), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[9]) );
AOI22X1TS U5566 ( .A0(add_subt_module_Add_Subt_result[8]), .A1(n4578), .B0(
add_subt_module_DmP[6]), .B1(n4622), .Y(n4531) );
AOI22X1TS U5567 ( .A0(n4591), .A1(n4539), .B0(n4579), .B1(n4553), .Y(n4532)
);
OAI21XLTS U5568 ( .A0(n4534), .A1(n4533), .B0(n4532), .Y(n4535) );
AOI21X1TS U5569 ( .A0(n4550), .A1(n4545), .B0(n4535), .Y(n4560) );
AOI22X1TS U5570 ( .A0(n4530), .A1(n4560), .B0(n4536), .B1(n4592), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[8]) );
AOI222X4TS U5571 ( .A0(n4622), .A1(add_subt_module_DmP[5]), .B0(
add_subt_module_Add_Subt_result[7]), .B1(n4569), .C0(
add_subt_module_Add_Subt_result[47]), .C1(n4537), .Y(n4557) );
AOI22X1TS U5572 ( .A0(n4540), .A1(n4539), .B0(n4538), .B1(n4545), .Y(n4541)
);
OAI21XLTS U5573 ( .A0(n4557), .A1(n3309), .B0(n4541), .Y(n4542) );
AOI21X1TS U5574 ( .A0(n4589), .A1(n4553), .B0(n4542), .Y(n4564) );
AOI22X1TS U5575 ( .A0(n4530), .A1(n4564), .B0(n4543), .B1(n4592), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[7]) );
AOI22X1TS U5576 ( .A0(add_subt_module_Add_Subt_result[48]), .A1(n4577), .B0(
add_subt_module_DmP[4]), .B1(n4622), .Y(n4544) );
AOI22X1TS U5577 ( .A0(n4587), .A1(n4545), .B0(n4579), .B1(n4563), .Y(n4546)
);
OAI21XLTS U5578 ( .A0(n4557), .A1(n3537), .B0(n4546), .Y(n4547) );
AOI21X1TS U5579 ( .A0(n4591), .A1(n4553), .B0(n4547), .Y(n4571) );
AOI22X1TS U5580 ( .A0(n4530), .A1(n4571), .B0(n4548), .B1(n4592), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[6]) );
OAI22X1TS U5581 ( .A0(add_subt_module_FSM_selector_C), .A1(
add_subt_module_DmP[3]), .B0(add_subt_module_Add_Subt_result[5]), .B1(
n4337), .Y(n4549) );
AOI22X1TS U5582 ( .A0(n4585), .A1(n4570), .B0(n4589), .B1(n4563), .Y(n4551)
);
AOI21X1TS U5583 ( .A0(n4587), .A1(n4553), .B0(n4552), .Y(n4580) );
AOI22X1TS U5584 ( .A0(n4530), .A1(n4580), .B0(n4554), .B1(n4592), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[5]) );
OAI22X1TS U5585 ( .A0(add_subt_module_FSM_selector_C), .A1(
add_subt_module_DmP[2]), .B0(add_subt_module_Add_Subt_result[50]),
.B1(n4583), .Y(n4555) );
AOI22X1TS U5586 ( .A0(n4591), .A1(n4563), .B0(n4550), .B1(n4570), .Y(n4556)
);
OAI21XLTS U5587 ( .A0(n4557), .A1(n4533), .B0(n4556), .Y(n4558) );
AOI21X1TS U5588 ( .A0(n4559), .A1(n4575), .B0(n4558), .Y(n4593) );
AOI22X1TS U5589 ( .A0(n4530), .A1(n4593), .B0(n4560), .B1(n4592), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[4]) );
AOI22X1TS U5590 ( .A0(add_subt_module_Add_Subt_result[3]), .A1(n4578), .B0(
add_subt_module_DmP[1]), .B1(n4622), .Y(n4561) );
AOI22X1TS U5591 ( .A0(n4587), .A1(n4563), .B0(n4585), .B1(n4586), .Y(n4566)
);
AOI22X1TS U5592 ( .A0(n4591), .A1(n4570), .B0(n4589), .B1(n4575), .Y(n4565)
);
AOI32X1TS U5593 ( .A0(n4566), .A1(n4530), .A2(n4565), .B0(n4564), .B1(n4592),
.Y(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[3]) );
AOI22X1TS U5594 ( .A0(n4591), .A1(n4575), .B0(n4574), .B1(n4586), .Y(n4573)
);
OAI22X1TS U5595 ( .A0(n4583), .A1(add_subt_module_Add_Subt_result[52]), .B0(
add_subt_module_FSM_selector_C), .B1(add_subt_module_DmP[0]), .Y(n4568) );
AOI22X1TS U5596 ( .A0(n4587), .A1(n4570), .B0(n4585), .B1(n4590), .Y(n4572)
);
AOI32X1TS U5597 ( .A0(n4573), .A1(n4530), .A2(n4572), .B0(n4571), .B1(n4592),
.Y(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[2]) );
AOI22X1TS U5598 ( .A0(n4576), .A1(n4575), .B0(n4574), .B1(n4590), .Y(n4582)
);
AOI22X1TS U5599 ( .A0(n4591), .A1(n4586), .B0(n4585), .B1(n4588), .Y(n4581)
);
AOI32X1TS U5600 ( .A0(n4582), .A1(n4530), .A2(n4581), .B0(n4580), .B1(n4592),
.Y(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[1]) );
OAI22X1TS U5601 ( .A0(n4337), .A1(n5232), .B0(n4583), .B1(n5079), .Y(n4584)
);
AOI22X1TS U5602 ( .A0(n4587), .A1(n4586), .B0(n4585), .B1(n4584), .Y(n4595)
);
AOI22X1TS U5603 ( .A0(n4591), .A1(n4590), .B0(n4550), .B1(n4588), .Y(n4594)
);
AOI32X1TS U5604 ( .A0(n4595), .A1(n4530), .A2(n4594), .B0(n4593), .B1(n4592),
.Y(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[0]) );
OAI211XLTS U5605 ( .A0(cordic_FSM_state_reg[1]), .A1(n4632), .B0(
cordic_FSM_state_reg[3]), .C0(n5168), .Y(n4596) );
NAND4BXLTS U5606 ( .AN(n4598), .B(n4606), .C(n4597), .D(n4596), .Y(n2940) );
AOI32X1TS U5607 ( .A0(cordic_FSM_state_reg[0]), .A1(n4604), .A2(ack_cordic),
.B0(n4603), .B1(n4604), .Y(n2939) );
NOR2X1TS U5608 ( .A(n4606), .B(n4605), .Y(n4740) );
NAND3X1TS U5609 ( .A(n4741), .B(n4740), .C(n4744), .Y(n4764) );
BUFX3TS U5610 ( .A(n4764), .Y(n4780) );
AO22XLTS U5611 ( .A0(d_ff_Xn[63]), .A1(n4842), .B0(d_ff2_X[63]), .B1(n4806),
.Y(n2931) );
NAND3XLTS U5612 ( .A(n4609), .B(n4608), .C(n4607), .Y(n4610) );
NAND3XLTS U5613 ( .A(n4610), .B(n4616), .C(n5120), .Y(n4615) );
AOI21X1TS U5614 ( .A0(n4615), .A1(n4614), .B0(n4613), .Y(n2929) );
AO21XLTS U5615 ( .A0(n4624), .A1(n4617), .B0(n4616), .Y(n4618) );
AOI22X1TS U5616 ( .A0(n4621), .A1(n4620), .B0(n4619), .B1(n4618), .Y(n4625)
);
NAND3XLTS U5617 ( .A(n4624), .B(n4623), .C(n4622), .Y(n4628) );
NAND4XLTS U5618 ( .A(n4625), .B(n4629), .C(n4774), .D(n4628), .Y(n2928) );
NAND3XLTS U5619 ( .A(n4630), .B(n4629), .C(n4628), .Y(n2927) );
NOR3X1TS U5620 ( .A(n4632), .B(cont_var_out[1]), .C(n4631), .Y(n4635) );
OA21XLTS U5621 ( .A0(cont_var_out[0]), .A1(n4635), .B0(n4634), .Y(n2926) );
AO22XLTS U5622 ( .A0(cont_var_out[0]), .A1(n4635), .B0(cont_var_out[1]),
.B1(n4634), .Y(n2925) );
INVX2TS U5623 ( .A(n4636), .Y(n4638) );
OAI22X1TS U5624 ( .A0(n4647), .A1(n5056), .B0(n4637), .B1(n4638), .Y(n2924)
);
OAI21X1TS U5625 ( .A0(n5049), .A1(n4638), .B0(n4644), .Y(n4639) );
AOI21X1TS U5626 ( .A0(n5049), .A1(n4638), .B0(n4639), .Y(n2922) );
OAI22X1TS U5627 ( .A0(n5118), .A1(n4639), .B0(n4638), .B1(n4701), .Y(n2921)
);
BUFX3TS U5628 ( .A(n4644), .Y(n4640) );
INVX4TS U5629 ( .A(n4640), .Y(n4649) );
BUFX3TS U5630 ( .A(n4644), .Y(n4645) );
BUFX3TS U5631 ( .A(n4644), .Y(n4648) );
BUFX4TS U5632 ( .A(n4644), .Y(n4646) );
INVX4TS U5633 ( .A(n4646), .Y(n4641) );
AO22XLTS U5634 ( .A0(n4648), .A1(d_ff1_shift_region_flag_out[1]), .B0(n4641),
.B1(shift_region_flag[1]), .Y(n2918) );
AO22XLTS U5635 ( .A0(n4649), .A1(data_in[62]), .B0(n4645), .B1(d_ff1_Z[62]),
.Y(n2917) );
AO22XLTS U5636 ( .A0(n4649), .A1(data_in[61]), .B0(n4645), .B1(d_ff1_Z[61]),
.Y(n2916) );
AO22XLTS U5637 ( .A0(n4649), .A1(data_in[60]), .B0(n4645), .B1(d_ff1_Z[60]),
.Y(n2915) );
AO22XLTS U5638 ( .A0(n4649), .A1(data_in[59]), .B0(n4645), .B1(d_ff1_Z[59]),
.Y(n2914) );
AO22XLTS U5639 ( .A0(n4649), .A1(data_in[58]), .B0(n4645), .B1(d_ff1_Z[58]),
.Y(n2913) );
AO22XLTS U5640 ( .A0(n4649), .A1(data_in[57]), .B0(n4645), .B1(d_ff1_Z[57]),
.Y(n2912) );
AO22XLTS U5641 ( .A0(n4649), .A1(data_in[56]), .B0(n4645), .B1(d_ff1_Z[56]),
.Y(n2911) );
AO22XLTS U5642 ( .A0(n4649), .A1(data_in[55]), .B0(n4646), .B1(d_ff1_Z[55]),
.Y(n2910) );
AO22XLTS U5643 ( .A0(n4649), .A1(data_in[54]), .B0(n4646), .B1(d_ff1_Z[54]),
.Y(n2909) );
AO22XLTS U5644 ( .A0(n4649), .A1(data_in[53]), .B0(n4646), .B1(d_ff1_Z[53]),
.Y(n2908) );
AO22XLTS U5645 ( .A0(n4649), .A1(data_in[52]), .B0(n4646), .B1(d_ff1_Z[52]),
.Y(n2907) );
AO22XLTS U5646 ( .A0(n4647), .A1(data_in[51]), .B0(n4646), .B1(d_ff1_Z[51]),
.Y(n2906) );
AO22XLTS U5647 ( .A0(n4641), .A1(data_in[50]), .B0(n4646), .B1(d_ff1_Z[50]),
.Y(n2905) );
AO22XLTS U5648 ( .A0(n4641), .A1(data_in[49]), .B0(n4646), .B1(d_ff1_Z[49]),
.Y(n2904) );
AO22XLTS U5649 ( .A0(n4641), .A1(data_in[48]), .B0(n4646), .B1(d_ff1_Z[48]),
.Y(n2903) );
AO22XLTS U5650 ( .A0(n4641), .A1(data_in[47]), .B0(n4646), .B1(d_ff1_Z[47]),
.Y(n2902) );
AO22XLTS U5651 ( .A0(n4641), .A1(data_in[46]), .B0(n4646), .B1(d_ff1_Z[46]),
.Y(n2901) );
AO22XLTS U5652 ( .A0(n4641), .A1(data_in[45]), .B0(n4646), .B1(d_ff1_Z[45]),
.Y(n2900) );
AO22XLTS U5653 ( .A0(n4641), .A1(data_in[44]), .B0(n4640), .B1(d_ff1_Z[44]),
.Y(n2899) );
AO22XLTS U5654 ( .A0(n4641), .A1(data_in[43]), .B0(n4640), .B1(d_ff1_Z[43]),
.Y(n2898) );
AO22XLTS U5655 ( .A0(n4641), .A1(data_in[42]), .B0(n4640), .B1(d_ff1_Z[42]),
.Y(n2897) );
AO22XLTS U5656 ( .A0(n4641), .A1(data_in[41]), .B0(n4640), .B1(d_ff1_Z[41]),
.Y(n2896) );
AO22XLTS U5657 ( .A0(n4641), .A1(data_in[40]), .B0(n4640), .B1(d_ff1_Z[40]),
.Y(n2895) );
AO22XLTS U5658 ( .A0(n4641), .A1(data_in[39]), .B0(n4640), .B1(d_ff1_Z[39]),
.Y(n2894) );
AO22XLTS U5659 ( .A0(n4649), .A1(data_in[38]), .B0(n4640), .B1(d_ff1_Z[38]),
.Y(n2893) );
AO22XLTS U5660 ( .A0(n4647), .A1(data_in[37]), .B0(n4640), .B1(d_ff1_Z[37]),
.Y(n2892) );
AO22XLTS U5661 ( .A0(n4647), .A1(data_in[36]), .B0(n4640), .B1(d_ff1_Z[36]),
.Y(n2891) );
AO22XLTS U5662 ( .A0(n4647), .A1(data_in[35]), .B0(n4640), .B1(d_ff1_Z[35]),
.Y(n2890) );
AO22XLTS U5663 ( .A0(n4647), .A1(data_in[34]), .B0(n4640), .B1(d_ff1_Z[34]),
.Y(n2889) );
AO22XLTS U5664 ( .A0(n4647), .A1(data_in[33]), .B0(n4648), .B1(d_ff1_Z[33]),
.Y(n2888) );
AO22XLTS U5665 ( .A0(n4647), .A1(data_in[32]), .B0(n4648), .B1(d_ff1_Z[32]),
.Y(n2887) );
INVX4TS U5666 ( .A(n4645), .Y(n4643) );
AO22XLTS U5667 ( .A0(n4643), .A1(data_in[31]), .B0(n4648), .B1(d_ff1_Z[31]),
.Y(n2886) );
AO22XLTS U5668 ( .A0(n4641), .A1(data_in[30]), .B0(n4648), .B1(d_ff1_Z[30]),
.Y(n2885) );
AO22XLTS U5669 ( .A0(n4649), .A1(data_in[29]), .B0(n4648), .B1(d_ff1_Z[29]),
.Y(n2884) );
AO22XLTS U5670 ( .A0(n4643), .A1(data_in[28]), .B0(n4648), .B1(d_ff1_Z[28]),
.Y(n2883) );
AO22XLTS U5671 ( .A0(n4643), .A1(data_in[27]), .B0(n4648), .B1(d_ff1_Z[27]),
.Y(n2882) );
AO22XLTS U5672 ( .A0(n4641), .A1(data_in[26]), .B0(n4648), .B1(d_ff1_Z[26]),
.Y(n2881) );
AO22XLTS U5673 ( .A0(n4649), .A1(data_in[25]), .B0(n4648), .B1(d_ff1_Z[25]),
.Y(n2880) );
AO22XLTS U5674 ( .A0(n4649), .A1(data_in[24]), .B0(n4648), .B1(d_ff1_Z[24]),
.Y(n2879) );
AO22XLTS U5675 ( .A0(n4643), .A1(data_in[23]), .B0(n4644), .B1(d_ff1_Z[23]),
.Y(n2878) );
AO22XLTS U5676 ( .A0(n4643), .A1(data_in[22]), .B0(n4644), .B1(d_ff1_Z[22]),
.Y(n2877) );
AO22XLTS U5677 ( .A0(n4643), .A1(data_in[21]), .B0(n4644), .B1(d_ff1_Z[21]),
.Y(n2876) );
AO22XLTS U5678 ( .A0(n4643), .A1(data_in[20]), .B0(n4644), .B1(d_ff1_Z[20]),
.Y(n2875) );
AO22XLTS U5679 ( .A0(n4643), .A1(data_in[19]), .B0(n4644), .B1(d_ff1_Z[19]),
.Y(n2874) );
AO22XLTS U5680 ( .A0(n4643), .A1(data_in[18]), .B0(n4644), .B1(d_ff1_Z[18]),
.Y(n2873) );
AO22XLTS U5681 ( .A0(n4643), .A1(data_in[17]), .B0(n4644), .B1(d_ff1_Z[17]),
.Y(n2872) );
AO22XLTS U5682 ( .A0(n4643), .A1(data_in[16]), .B0(n4644), .B1(d_ff1_Z[16]),
.Y(n2871) );
AO22XLTS U5683 ( .A0(n4643), .A1(data_in[15]), .B0(n4644), .B1(d_ff1_Z[15]),
.Y(n2870) );
AO22XLTS U5684 ( .A0(n4643), .A1(data_in[14]), .B0(n4644), .B1(d_ff1_Z[14]),
.Y(n2869) );
AO22XLTS U5685 ( .A0(n4643), .A1(data_in[13]), .B0(n4644), .B1(d_ff1_Z[13]),
.Y(n2868) );
AO22XLTS U5686 ( .A0(n4643), .A1(data_in[12]), .B0(n4645), .B1(d_ff1_Z[12]),
.Y(n2867) );
AO22XLTS U5687 ( .A0(n4643), .A1(data_in[11]), .B0(n4646), .B1(d_ff1_Z[11]),
.Y(n2866) );
AO22XLTS U5688 ( .A0(n4643), .A1(data_in[10]), .B0(n4646), .B1(d_ff1_Z[10]),
.Y(n2865) );
AO22XLTS U5689 ( .A0(n4647), .A1(data_in[9]), .B0(n4645), .B1(d_ff1_Z[9]),
.Y(n2864) );
AO22XLTS U5690 ( .A0(n4647), .A1(data_in[8]), .B0(n4646), .B1(d_ff1_Z[8]),
.Y(n2863) );
AO22XLTS U5691 ( .A0(n4647), .A1(data_in[7]), .B0(n4645), .B1(d_ff1_Z[7]),
.Y(n2862) );
AO22XLTS U5692 ( .A0(n4647), .A1(data_in[6]), .B0(n4646), .B1(d_ff1_Z[6]),
.Y(n2861) );
AO22XLTS U5693 ( .A0(n4647), .A1(data_in[5]), .B0(n4644), .B1(d_ff1_Z[5]),
.Y(n2860) );
AO22XLTS U5694 ( .A0(n4647), .A1(data_in[4]), .B0(n4644), .B1(d_ff1_Z[4]),
.Y(n2859) );
AO22XLTS U5695 ( .A0(n4647), .A1(data_in[3]), .B0(n4646), .B1(d_ff1_Z[3]),
.Y(n2858) );
AO22XLTS U5696 ( .A0(n4647), .A1(data_in[2]), .B0(n4645), .B1(d_ff1_Z[2]),
.Y(n2857) );
AO22XLTS U5697 ( .A0(n4647), .A1(data_in[1]), .B0(n4648), .B1(d_ff1_Z[1]),
.Y(n2856) );
AO22XLTS U5698 ( .A0(n4647), .A1(data_in[0]), .B0(n4646), .B1(d_ff1_Z[0]),
.Y(n2855) );
AO22XLTS U5699 ( .A0(n4649), .A1(data_in[63]), .B0(n4648), .B1(d_ff1_Z[63]),
.Y(n2854) );
NAND3XLTS U5700 ( .A(n4650), .B(n4653), .C(n4655), .Y(n4652) );
AOI32X1TS U5701 ( .A0(n4653), .A1(n4652), .A2(n4651), .B0(n5247), .B1(n4652),
.Y(n2853) );
INVX4TS U5702 ( .A(n4818), .Y(n4826) );
AO22XLTS U5703 ( .A0(n4826), .A1(n4654), .B0(n4818), .B1(d_ff3_LUT_out[56]),
.Y(n2850) );
OAI31X1TS U5704 ( .A0(cont_iter_out[0]), .A1(n5056), .A2(n4701), .B0(n4655),
.Y(n4686) );
INVX2TS U5705 ( .A(n4686), .Y(n4656) );
AOI2BB2XLTS U5706 ( .B0(n4657), .B1(n4656), .A0N(n4706), .A1N(
d_ff3_LUT_out[54]), .Y(n2848) );
AO22XLTS U5707 ( .A0(n4829), .A1(cont_iter_out[0]), .B0(n4726), .B1(
d_ff3_LUT_out[52]), .Y(n2846) );
AOI2BB2XLTS U5708 ( .B0(n4694), .B1(n4660), .A0N(n4836), .A1N(
d_ff3_LUT_out[50]), .Y(n2845) );
BUFX3TS U5709 ( .A(n4817), .Y(n4810) );
BUFX3TS U5710 ( .A(n4810), .Y(n4731) );
AO21XLTS U5711 ( .A0(d_ff3_LUT_out[49]), .A1(n4731), .B0(n4664), .Y(n2844)
);
INVX4TS U5712 ( .A(n4818), .Y(n4836) );
NAND2X1TS U5713 ( .A(n4702), .B(n5118), .Y(n4662) );
OA21XLTS U5714 ( .A0(n4836), .A1(d_ff3_LUT_out[47]), .B0(n4662), .Y(n2842)
);
AO21XLTS U5715 ( .A0(d_ff3_LUT_out[46]), .A1(n4731), .B0(n4664), .Y(n2841)
);
AOI2BB2XLTS U5716 ( .B0(n4658), .B1(n4694), .A0N(n4706), .A1N(
d_ff3_LUT_out[45]), .Y(n2840) );
AO21XLTS U5717 ( .A0(d_ff3_LUT_out[44]), .A1(n4731), .B0(n4664), .Y(n2839)
);
BUFX3TS U5718 ( .A(n4817), .Y(n4805) );
BUFX4TS U5719 ( .A(n4805), .Y(n4734) );
NAND2X1TS U5720 ( .A(n4674), .B(n4662), .Y(n4700) );
NOR2X2TS U5721 ( .A(n4685), .B(n4700), .Y(n4693) );
AOI21X1TS U5722 ( .A0(n4706), .A1(cont_iter_out[3]), .B0(n4675), .Y(n4665)
);
OAI2BB1X1TS U5723 ( .A0N(d_ff3_LUT_out[43]), .A1N(n4734), .B0(n4665), .Y(
n2838) );
OA21XLTS U5724 ( .A0(n4836), .A1(d_ff3_LUT_out[42]), .B0(n4662), .Y(n2837)
);
OA21XLTS U5725 ( .A0(n4836), .A1(d_ff3_LUT_out[41]), .B0(n4663), .Y(n2836)
);
OAI2BB1X1TS U5726 ( .A0N(d_ff3_LUT_out[40]), .A1N(n4731), .B0(n2968), .Y(
n2835) );
AOI2BB1XLTS U5727 ( .A0N(n4706), .A1N(d_ff3_LUT_out[39]), .B0(n4685), .Y(
n2834) );
BUFX3TS U5728 ( .A(n4726), .Y(n4727) );
OAI2BB1X1TS U5729 ( .A0N(d_ff3_LUT_out[38]), .A1N(n4727), .B0(n4693), .Y(
n2833) );
AOI2BB2XLTS U5730 ( .B0(cont_iter_out[2]), .B1(n4694), .A0N(n4706), .A1N(
d_ff3_LUT_out[37]), .Y(n2832) );
OAI2BB1X1TS U5731 ( .A0N(d_ff3_LUT_out[36]), .A1N(n4731), .B0(n2968), .Y(
n2831) );
AOI2BB1XLTS U5732 ( .A0N(n4706), .A1N(d_ff3_LUT_out[35]), .B0(n4675), .Y(
n2830) );
OAI2BB1X1TS U5733 ( .A0N(d_ff3_LUT_out[34]), .A1N(n4730), .B0(n4665), .Y(
n2829) );
OAI2BB1X1TS U5734 ( .A0N(d_ff3_LUT_out[32]), .A1N(n4731), .B0(n4693), .Y(
n2827) );
AO21XLTS U5735 ( .A0(d_ff3_LUT_out[30]), .A1(n4731), .B0(n4700), .Y(n2825)
);
OA21XLTS U5736 ( .A0(n4836), .A1(d_ff3_LUT_out[29]), .B0(n4666), .Y(n2824)
);
OAI2BB1X1TS U5737 ( .A0N(d_ff3_LUT_out[28]), .A1N(n4731), .B0(n2968), .Y(
n2823) );
AOI2BB2XLTS U5738 ( .B0(n4668), .B1(n4678), .A0N(n4822), .A1N(
d_ff3_LUT_out[26]), .Y(n2821) );
NAND2X1TS U5739 ( .A(n4669), .B(n4682), .Y(n4670) );
OA21XLTS U5740 ( .A0(n4836), .A1(d_ff3_LUT_out[22]), .B0(n4672), .Y(n2817)
);
AO22XLTS U5741 ( .A0(n4694), .A1(n4673), .B0(d_ff3_LUT_out[21]), .B1(n4731),
.Y(n2816) );
OAI2BB1X1TS U5742 ( .A0N(d_ff3_LUT_out[20]), .A1N(n4731), .B0(n4674), .Y(
n2815) );
AOI2BB2XLTS U5743 ( .B0(n4675), .B1(n4698), .A0N(n4822), .A1N(
d_ff3_LUT_out[18]), .Y(n2813) );
OAI2BB1X1TS U5744 ( .A0N(d_ff3_LUT_out[17]), .A1N(n4731), .B0(n4707), .Y(
n2812) );
AO22XLTS U5745 ( .A0(n4829), .A1(n4676), .B0(n4726), .B1(d_ff3_LUT_out[16]),
.Y(n2811) );
OAI211X1TS U5746 ( .A0(n4691), .A1(n4678), .B0(n4677), .C0(n4698), .Y(n4687)
);
OA21XLTS U5747 ( .A0(n4836), .A1(d_ff3_LUT_out[15]), .B0(n4687), .Y(n2810)
);
OAI2BB2XLTS U5748 ( .B0(n4684), .B1(n4680), .A0N(d_ff3_LUT_out[14]), .A1N(
n4818), .Y(n2809) );
NOR2XLTS U5749 ( .A(n4697), .B(n4817), .Y(n4681) );
OAI21XLTS U5750 ( .A0(n4682), .A1(n4701), .B0(n4681), .Y(n4683) );
OAI2BB1X1TS U5751 ( .A0N(d_ff3_LUT_out[13]), .A1N(n4730), .B0(n4683), .Y(
n2808) );
OAI2BB1X1TS U5752 ( .A0N(d_ff3_LUT_out[12]), .A1N(n4731), .B0(n4684), .Y(
n2807) );
INVX2TS U5753 ( .A(n4685), .Y(n4688) );
AOI211XLTS U5754 ( .A0(n4688), .A1(n4687), .B0(n4703), .C0(n4686), .Y(n4689)
);
AOI2BB1XLTS U5755 ( .A0N(n4706), .A1N(d_ff3_LUT_out[11]), .B0(n4689), .Y(
n2806) );
OAI31X1TS U5756 ( .A0(n4697), .A1(n4691), .A2(n4690), .B0(n4707), .Y(n4692)
);
OA22X1TS U5757 ( .A0(n4693), .A1(n4692), .B0(n4808), .B1(d_ff3_LUT_out[9]),
.Y(n2804) );
AOI22X1TS U5758 ( .A0(n5309), .A1(n4818), .B0(n4695), .B1(n4694), .Y(n2803)
);
AOI2BB1XLTS U5759 ( .A0N(n4706), .A1N(d_ff3_LUT_out[7]), .B0(n4696), .Y(
n2802) );
NOR2XLTS U5760 ( .A(n4697), .B(n4703), .Y(n4699) );
AOI32X1TS U5761 ( .A0(n4699), .A1(n4729), .A2(n4698), .B0(n4818), .B1(n5306),
.Y(n2801) );
AO21XLTS U5762 ( .A0(d_ff3_LUT_out[4]), .A1(n4726), .B0(n4700), .Y(n2799) );
AOI2BB2XLTS U5763 ( .B0(n4702), .B1(n4701), .A0N(n4706), .A1N(
d_ff3_LUT_out[2]), .Y(n2797) );
AOI21X1TS U5764 ( .A0(n4705), .A1(n4704), .B0(n4703), .Y(n4708) );
AOI2BB2XLTS U5765 ( .B0(n4708), .B1(n4707), .A0N(n4706), .A1N(
d_ff3_LUT_out[1]), .Y(n2796) );
AO22XLTS U5766 ( .A0(d_ff2_X[62]), .A1(n4806), .B0(d_ff_Xn[62]), .B1(n4842),
.Y(n2793) );
OA22X1TS U5767 ( .A0(d_ff_Xn[61]), .A1(n4800), .B0(d_ff2_X[61]), .B1(n4813),
.Y(n2792) );
AOI2BB2XLTS U5768 ( .B0(n4709), .B1(n4711), .A0N(d_ff_Xn[60]), .A1N(n4728),
.Y(n2791) );
BUFX3TS U5769 ( .A(n4803), .Y(n4733) );
OA22X1TS U5770 ( .A0(d_ff_Xn[59]), .A1(n4710), .B0(d_ff2_X[59]), .B1(n4733),
.Y(n2790) );
AOI2BB2XLTS U5771 ( .B0(n4712), .B1(n4711), .A0N(d_ff_Xn[58]), .A1N(n4728),
.Y(n2789) );
OA22X1TS U5772 ( .A0(d_ff_Xn[57]), .A1(n4710), .B0(d_ff2_X[57]), .B1(n4733),
.Y(n2788) );
OA22X1TS U5773 ( .A0(d_ff_Xn[56]), .A1(n4713), .B0(d_ff2_X[56]), .B1(n4733),
.Y(n2787) );
OA22X1TS U5774 ( .A0(n4733), .A1(d_ff2_X[55]), .B0(d_ff_Xn[55]), .B1(n4728),
.Y(n2786) );
OA22X1TS U5775 ( .A0(n4733), .A1(d_ff2_X[54]), .B0(d_ff_Xn[54]), .B1(n4728),
.Y(n2785) );
OA22X1TS U5776 ( .A0(n4733), .A1(d_ff2_X[53]), .B0(d_ff_Xn[53]), .B1(n4728),
.Y(n2784) );
AO22XLTS U5777 ( .A0(d_ff2_X[52]), .A1(n4806), .B0(d_ff_Xn[52]), .B1(n4732),
.Y(n2783) );
OAI21XLTS U5778 ( .A0(cont_iter_out[0]), .A1(n5182), .B0(intadd_373_CI), .Y(
n4714) );
AO22XLTS U5779 ( .A0(n4829), .A1(n4714), .B0(n4726), .B1(d_ff3_sh_x_out[52]),
.Y(n2782) );
OR2X1TS U5780 ( .A(d_ff2_X[56]), .B(intadd_373_n1), .Y(n4717) );
NAND2X1TS U5781 ( .A(d_ff2_X[56]), .B(intadd_373_n1), .Y(n4715) );
AOI32X1TS U5782 ( .A0(n4717), .A1(n4729), .A2(n4715), .B0(n5308), .B1(n4818),
.Y(n2778) );
AOI21X1TS U5783 ( .A0(d_ff2_X[57]), .A1(n4717), .B0(n4716), .Y(n4718) );
AOI2BB2XLTS U5784 ( .B0(n4829), .B1(n4718), .A0N(d_ff3_sh_x_out[57]), .A1N(
n4836), .Y(n2777) );
AOI21X1TS U5785 ( .A0(d_ff2_X[59]), .A1(n4720), .B0(n4719), .Y(n4721) );
AOI2BB2XLTS U5786 ( .B0(n4829), .B1(n4721), .A0N(d_ff3_sh_x_out[59]), .A1N(
n4836), .Y(n2775) );
NOR2X1TS U5787 ( .A(d_ff2_X[61]), .B(n4722), .Y(n4724) );
AOI21X1TS U5788 ( .A0(d_ff2_X[61]), .A1(n4722), .B0(n4724), .Y(n4723) );
AOI2BB2XLTS U5789 ( .B0(n4829), .B1(n4723), .A0N(d_ff3_sh_x_out[61]), .A1N(
n4836), .Y(n2773) );
XOR2XLTS U5790 ( .A(d_ff2_X[62]), .B(n4724), .Y(n4725) );
AO22XLTS U5791 ( .A0(n4829), .A1(n4725), .B0(n4726), .B1(d_ff3_sh_x_out[62]),
.Y(n2772) );
INVX4TS U5792 ( .A(n4803), .Y(n4802) );
AO22XLTS U5793 ( .A0(d_ff_Xn[51]), .A1(n3300), .B0(d_ff2_X[51]), .B1(n4802),
.Y(n2771) );
AO22XLTS U5794 ( .A0(n4829), .A1(d_ff2_X[51]), .B0(n4726), .B1(
d_ff3_sh_x_out[51]), .Y(n2770) );
INVX4TS U5795 ( .A(n4803), .Y(n4804) );
AO22XLTS U5796 ( .A0(d_ff_Xn[50]), .A1(n3300), .B0(d_ff2_X[50]), .B1(n4804),
.Y(n2769) );
AO22XLTS U5797 ( .A0(n4829), .A1(d_ff2_X[50]), .B0(n4726), .B1(
d_ff3_sh_x_out[50]), .Y(n2768) );
OA22X1TS U5798 ( .A0(n4733), .A1(d_ff2_X[49]), .B0(d_ff_Xn[49]), .B1(n4728),
.Y(n2767) );
AO22XLTS U5799 ( .A0(n4829), .A1(d_ff2_X[49]), .B0(n4726), .B1(
d_ff3_sh_x_out[49]), .Y(n2766) );
OA22X1TS U5800 ( .A0(n4733), .A1(d_ff2_X[48]), .B0(d_ff_Xn[48]), .B1(n4728),
.Y(n2765) );
AO22XLTS U5801 ( .A0(n4829), .A1(d_ff2_X[48]), .B0(n4726), .B1(
d_ff3_sh_x_out[48]), .Y(n2764) );
AO22XLTS U5802 ( .A0(d_ff_Xn[47]), .A1(n4807), .B0(d_ff2_X[47]), .B1(n4802),
.Y(n2763) );
AO22XLTS U5803 ( .A0(n4829), .A1(d_ff2_X[47]), .B0(n4726), .B1(
d_ff3_sh_x_out[47]), .Y(n2762) );
OA22X1TS U5804 ( .A0(n4733), .A1(d_ff2_X[46]), .B0(d_ff_Xn[46]), .B1(n4728),
.Y(n2761) );
AO22XLTS U5805 ( .A0(n4829), .A1(d_ff2_X[46]), .B0(n4726), .B1(
d_ff3_sh_x_out[46]), .Y(n2760) );
OA22X1TS U5806 ( .A0(n4733), .A1(d_ff2_X[45]), .B0(d_ff_Xn[45]), .B1(n4728),
.Y(n2759) );
AO22XLTS U5807 ( .A0(n4729), .A1(d_ff2_X[45]), .B0(n4838), .B1(
d_ff3_sh_x_out[45]), .Y(n2758) );
AO22XLTS U5808 ( .A0(d_ff_Xn[44]), .A1(n3300), .B0(d_ff2_X[44]), .B1(n4804),
.Y(n2757) );
AO22XLTS U5809 ( .A0(n4729), .A1(d_ff2_X[44]), .B0(n4838), .B1(
d_ff3_sh_x_out[44]), .Y(n2756) );
OA22X1TS U5810 ( .A0(n4733), .A1(d_ff2_X[43]), .B0(d_ff_Xn[43]), .B1(n4728),
.Y(n2755) );
AO22XLTS U5811 ( .A0(n4729), .A1(d_ff2_X[43]), .B0(n4838), .B1(
d_ff3_sh_x_out[43]), .Y(n2754) );
OA22X1TS U5812 ( .A0(n4733), .A1(d_ff2_X[42]), .B0(d_ff_Xn[42]), .B1(n4728),
.Y(n2753) );
AO22XLTS U5813 ( .A0(n4729), .A1(d_ff2_X[42]), .B0(n4727), .B1(
d_ff3_sh_x_out[42]), .Y(n2752) );
OA22X1TS U5814 ( .A0(n4733), .A1(d_ff2_X[41]), .B0(d_ff_Xn[41]), .B1(n4728),
.Y(n2751) );
AO22XLTS U5815 ( .A0(n4729), .A1(d_ff2_X[41]), .B0(n4727), .B1(
d_ff3_sh_x_out[41]), .Y(n2750) );
AO22XLTS U5816 ( .A0(d_ff_Xn[40]), .A1(n4807), .B0(d_ff2_X[40]), .B1(n4802),
.Y(n2749) );
AO22XLTS U5817 ( .A0(n4729), .A1(d_ff2_X[40]), .B0(n4727), .B1(
d_ff3_sh_x_out[40]), .Y(n2748) );
AO22XLTS U5818 ( .A0(n4729), .A1(d_ff2_X[39]), .B0(n4727), .B1(
d_ff3_sh_x_out[39]), .Y(n2746) );
AO22XLTS U5819 ( .A0(d_ff_Xn[38]), .A1(n4807), .B0(d_ff2_X[38]), .B1(n4804),
.Y(n2745) );
AO22XLTS U5820 ( .A0(n4729), .A1(d_ff2_X[38]), .B0(n4727), .B1(
d_ff3_sh_x_out[38]), .Y(n2744) );
AO22XLTS U5821 ( .A0(d_ff_Xn[37]), .A1(n4798), .B0(d_ff2_X[37]), .B1(n4802),
.Y(n2743) );
INVX4TS U5822 ( .A(n4818), .Y(n4808) );
AO22XLTS U5823 ( .A0(n4808), .A1(d_ff2_X[37]), .B0(n4727), .B1(
d_ff3_sh_x_out[37]), .Y(n2742) );
INVX4TS U5824 ( .A(n4818), .Y(n4840) );
AO22XLTS U5825 ( .A0(n4840), .A1(d_ff2_X[36]), .B0(n4727), .B1(
d_ff3_sh_x_out[36]), .Y(n2740) );
INVX4TS U5826 ( .A(n4818), .Y(n4833) );
AO22XLTS U5827 ( .A0(n4833), .A1(d_ff2_X[35]), .B0(n4727), .B1(
d_ff3_sh_x_out[35]), .Y(n2738) );
AO22XLTS U5828 ( .A0(n4826), .A1(d_ff2_X[34]), .B0(n4727), .B1(
d_ff3_sh_x_out[34]), .Y(n2736) );
AO22XLTS U5829 ( .A0(d_ff_Xn[33]), .A1(n4807), .B0(d_ff2_X[33]), .B1(n4802),
.Y(n2735) );
AO22XLTS U5830 ( .A0(n4819), .A1(d_ff2_X[33]), .B0(n4727), .B1(
d_ff3_sh_x_out[33]), .Y(n2734) );
OA22X1TS U5831 ( .A0(n3101), .A1(d_ff2_X[32]), .B0(d_ff_Xn[32]), .B1(n4728),
.Y(n2733) );
AO22XLTS U5832 ( .A0(n4808), .A1(d_ff2_X[32]), .B0(n4727), .B1(
d_ff3_sh_x_out[32]), .Y(n2732) );
OA22X1TS U5833 ( .A0(n3101), .A1(d_ff2_X[31]), .B0(d_ff_Xn[31]), .B1(n4728),
.Y(n2731) );
AO22XLTS U5834 ( .A0(n4833), .A1(d_ff2_X[31]), .B0(n4730), .B1(
d_ff3_sh_x_out[31]), .Y(n2730) );
AO22XLTS U5835 ( .A0(d_ff_Xn[30]), .A1(n3300), .B0(d_ff2_X[30]), .B1(n4802),
.Y(n2729) );
AO22XLTS U5836 ( .A0(n4833), .A1(d_ff2_X[30]), .B0(n4730), .B1(
d_ff3_sh_x_out[30]), .Y(n2728) );
OA22X1TS U5837 ( .A0(n3101), .A1(d_ff2_X[29]), .B0(d_ff_Xn[29]), .B1(n4710),
.Y(n2727) );
AO22XLTS U5838 ( .A0(n4833), .A1(d_ff2_X[29]), .B0(n4730), .B1(
d_ff3_sh_x_out[29]), .Y(n2726) );
OA22X1TS U5839 ( .A0(n3101), .A1(d_ff2_X[28]), .B0(d_ff_Xn[28]), .B1(n4710),
.Y(n2725) );
AO22XLTS U5840 ( .A0(n4833), .A1(d_ff2_X[28]), .B0(n4730), .B1(
d_ff3_sh_x_out[28]), .Y(n2724) );
AO22XLTS U5841 ( .A0(d_ff_Xn[27]), .A1(n4798), .B0(d_ff2_X[27]), .B1(n4802),
.Y(n2723) );
AO22XLTS U5842 ( .A0(n4833), .A1(d_ff2_X[27]), .B0(n4730), .B1(
d_ff3_sh_x_out[27]), .Y(n2722) );
OA22X1TS U5843 ( .A0(n3101), .A1(d_ff2_X[26]), .B0(d_ff_Xn[26]), .B1(n4710),
.Y(n2721) );
AO22XLTS U5844 ( .A0(n4833), .A1(d_ff2_X[26]), .B0(n4730), .B1(
d_ff3_sh_x_out[26]), .Y(n2720) );
AO22XLTS U5845 ( .A0(d_ff_Xn[25]), .A1(n4807), .B0(d_ff2_X[25]), .B1(n4802),
.Y(n2719) );
AO22XLTS U5846 ( .A0(n4833), .A1(d_ff2_X[25]), .B0(n4730), .B1(
d_ff3_sh_x_out[25]), .Y(n2718) );
OA22X1TS U5847 ( .A0(n3101), .A1(d_ff2_X[24]), .B0(d_ff_Xn[24]), .B1(n4710),
.Y(n2717) );
AO22XLTS U5848 ( .A0(n4833), .A1(d_ff2_X[24]), .B0(n4730), .B1(
d_ff3_sh_x_out[24]), .Y(n2716) );
AO22XLTS U5849 ( .A0(d_ff_Xn[23]), .A1(n4798), .B0(d_ff2_X[23]), .B1(n4802),
.Y(n2715) );
AO22XLTS U5850 ( .A0(n4729), .A1(d_ff2_X[23]), .B0(n4734), .B1(
d_ff3_sh_x_out[23]), .Y(n2714) );
AO22XLTS U5851 ( .A0(d_ff_Xn[22]), .A1(n4732), .B0(d_ff2_X[22]), .B1(n4802),
.Y(n2713) );
AO22XLTS U5852 ( .A0(n4729), .A1(d_ff2_X[22]), .B0(n4730), .B1(
d_ff3_sh_x_out[22]), .Y(n2712) );
AO22XLTS U5853 ( .A0(d_ff_Xn[21]), .A1(n4732), .B0(d_ff2_X[21]), .B1(n4802),
.Y(n2711) );
AO22XLTS U5854 ( .A0(n4729), .A1(d_ff2_X[21]), .B0(n4730), .B1(
d_ff3_sh_x_out[21]), .Y(n2710) );
AO22XLTS U5855 ( .A0(d_ff_Xn[20]), .A1(n4732), .B0(d_ff2_X[20]), .B1(n4802),
.Y(n2709) );
AO22XLTS U5856 ( .A0(n4729), .A1(d_ff2_X[20]), .B0(n4734), .B1(
d_ff3_sh_x_out[20]), .Y(n2708) );
AO22XLTS U5857 ( .A0(n4729), .A1(d_ff2_X[19]), .B0(n4734), .B1(
d_ff3_sh_x_out[19]), .Y(n2706) );
AO22XLTS U5858 ( .A0(d_ff_Xn[18]), .A1(n4732), .B0(d_ff2_X[18]), .B1(n4802),
.Y(n2705) );
AO22XLTS U5859 ( .A0(n4729), .A1(d_ff2_X[18]), .B0(n4734), .B1(
d_ff3_sh_x_out[18]), .Y(n2704) );
AO22XLTS U5860 ( .A0(d_ff_Xn[17]), .A1(n4732), .B0(d_ff2_X[17]), .B1(n4802),
.Y(n2703) );
AO22XLTS U5861 ( .A0(n4822), .A1(d_ff2_X[17]), .B0(n4734), .B1(
d_ff3_sh_x_out[17]), .Y(n2702) );
AO22XLTS U5862 ( .A0(d_ff_Xn[16]), .A1(n4732), .B0(d_ff2_X[16]), .B1(n4802),
.Y(n2701) );
AO22XLTS U5863 ( .A0(n4840), .A1(d_ff2_X[16]), .B0(n4734), .B1(
d_ff3_sh_x_out[16]), .Y(n2700) );
AO22XLTS U5864 ( .A0(d_ff_Xn[15]), .A1(n4732), .B0(d_ff2_X[15]), .B1(n4802),
.Y(n2699) );
AO22XLTS U5865 ( .A0(n4833), .A1(d_ff2_X[15]), .B0(n4734), .B1(
d_ff3_sh_x_out[15]), .Y(n2698) );
OA22X1TS U5866 ( .A0(n3101), .A1(d_ff2_X[14]), .B0(d_ff_Xn[14]), .B1(n4812),
.Y(n2697) );
AO22XLTS U5867 ( .A0(n4840), .A1(d_ff2_X[14]), .B0(n4731), .B1(
d_ff3_sh_x_out[14]), .Y(n2696) );
AO22XLTS U5868 ( .A0(n4822), .A1(d_ff2_X[13]), .B0(n4734), .B1(
d_ff3_sh_x_out[13]), .Y(n2694) );
AO22XLTS U5869 ( .A0(d_ff_Xn[12]), .A1(n4732), .B0(d_ff2_X[12]), .B1(n4802),
.Y(n2693) );
AO22XLTS U5870 ( .A0(n4840), .A1(d_ff2_X[12]), .B0(n4730), .B1(
d_ff3_sh_x_out[12]), .Y(n2692) );
AO22XLTS U5871 ( .A0(n4822), .A1(d_ff2_X[11]), .B0(n4734), .B1(
d_ff3_sh_x_out[11]), .Y(n2690) );
AO22XLTS U5872 ( .A0(d_ff_Xn[10]), .A1(n4732), .B0(d_ff2_X[10]), .B1(n4804),
.Y(n2689) );
AO22XLTS U5873 ( .A0(n4840), .A1(d_ff2_X[10]), .B0(n4731), .B1(
d_ff3_sh_x_out[10]), .Y(n2688) );
AO22XLTS U5874 ( .A0(n4822), .A1(d_ff2_X[9]), .B0(n4734), .B1(
d_ff3_sh_x_out[9]), .Y(n2686) );
AO22XLTS U5875 ( .A0(n4840), .A1(d_ff2_X[8]), .B0(n4734), .B1(
d_ff3_sh_x_out[8]), .Y(n2684) );
AO22XLTS U5876 ( .A0(n4840), .A1(d_ff2_X[7]), .B0(n4734), .B1(
d_ff3_sh_x_out[7]), .Y(n2682) );
OA22X1TS U5877 ( .A0(n3101), .A1(d_ff2_X[6]), .B0(d_ff_Xn[6]), .B1(n4812),
.Y(n2681) );
AO22XLTS U5878 ( .A0(n4840), .A1(d_ff2_X[6]), .B0(n4734), .B1(
d_ff3_sh_x_out[6]), .Y(n2680) );
AO22XLTS U5879 ( .A0(d_ff_Xn[5]), .A1(n4732), .B0(d_ff2_X[5]), .B1(n4804),
.Y(n2679) );
AO22XLTS U5880 ( .A0(n4822), .A1(d_ff2_X[5]), .B0(n4734), .B1(
d_ff3_sh_x_out[5]), .Y(n2678) );
AO22XLTS U5881 ( .A0(d_ff_Xn[4]), .A1(n4732), .B0(d_ff2_X[4]), .B1(n4804),
.Y(n2677) );
AO22XLTS U5882 ( .A0(n4840), .A1(d_ff2_X[4]), .B0(n4734), .B1(
d_ff3_sh_x_out[4]), .Y(n2676) );
AO22XLTS U5883 ( .A0(n4808), .A1(d_ff2_X[3]), .B0(n4734), .B1(
d_ff3_sh_x_out[3]), .Y(n2674) );
AO22XLTS U5884 ( .A0(d_ff_Xn[2]), .A1(n4732), .B0(d_ff2_X[2]), .B1(n4804),
.Y(n2673) );
AO22XLTS U5885 ( .A0(n4840), .A1(d_ff2_X[2]), .B0(n4734), .B1(
d_ff3_sh_x_out[2]), .Y(n2672) );
AO22XLTS U5886 ( .A0(d_ff_Xn[1]), .A1(n4732), .B0(d_ff2_X[1]), .B1(n4804),
.Y(n2671) );
AO22XLTS U5887 ( .A0(n4826), .A1(d_ff2_X[1]), .B0(n4734), .B1(
d_ff3_sh_x_out[1]), .Y(n2670) );
OA22X1TS U5888 ( .A0(n4733), .A1(d_ff2_X[0]), .B0(d_ff_Xn[0]), .B1(n4812),
.Y(n2669) );
AO22XLTS U5889 ( .A0(n4826), .A1(d_ff2_X[0]), .B0(n4734), .B1(
d_ff3_sh_x_out[0]), .Y(n2668) );
NOR2X1TS U5890 ( .A(n5045), .B(n4736), .Y(n4739) );
NAND2X1TS U5891 ( .A(sel_mux_3_reg), .B(n5395), .Y(n4738) );
OAI2BB2XLTS U5892 ( .B0(n4739), .B1(n4738), .A0N(n4739), .A1N(n4737), .Y(
n2667) );
INVX2TS U5893 ( .A(n4740), .Y(n4743) );
BUFX4TS U5894 ( .A(n4742), .Y(n4775) );
BUFX3TS U5895 ( .A(n4775), .Y(n4786) );
OAI22X1TS U5896 ( .A0(n4791), .A1(n5080), .B0(n4786), .B1(n5246), .Y(n2666)
);
CLKBUFX2TS U5897 ( .A(n2992), .Y(n4769) );
INVX4TS U5898 ( .A(n4769), .Y(n4795) );
AO22XLTS U5899 ( .A0(n4795), .A1(result_add_subt[63]), .B0(n4769), .B1(
d_ff_Zn[63]), .Y(n2665) );
NAND2X1TS U5900 ( .A(n4745), .B(n5216), .Y(n4754) );
AOI21X1TS U5901 ( .A0(n5179), .A1(add_subt_module_Add_Subt_result[49]), .B0(
add_subt_module_Add_Subt_result[51]), .Y(n4746) );
NOR2XLTS U5902 ( .A(n4746), .B(add_subt_module_Add_Subt_result[52]), .Y(
n4747) );
OAI21XLTS U5903 ( .A0(n4747), .A1(add_subt_module_Add_Subt_result[53]), .B0(
n5079), .Y(n4748) );
OAI31X1TS U5904 ( .A0(add_subt_module_Add_Subt_result[38]), .A1(n5076), .A2(
n4749), .B0(n4748), .Y(n4750) );
AOI31XLTS U5905 ( .A0(n4751), .A1(add_subt_module_Add_Subt_result[45]), .A2(
n5218), .B0(n4750), .Y(n4753) );
OA22X1TS U5906 ( .A0(n4763), .A1(add_subt_module_LZA_output[0]), .B0(n4762),
.B1(n4761), .Y(n2592) );
AO22XLTS U5907 ( .A0(n4795), .A1(result_add_subt[62]), .B0(n2992), .B1(
d_ff_Zn[62]), .Y(n2533) );
AO22XLTS U5908 ( .A0(n4767), .A1(result_add_subt[62]), .B0(n4787), .B1(
d_ff_Xn[62]), .Y(n2531) );
AO22XLTS U5909 ( .A0(n4795), .A1(result_add_subt[61]), .B0(n4784), .B1(
d_ff_Zn[61]), .Y(n2529) );
INVX4TS U5910 ( .A(n4775), .Y(n4771) );
BUFX4TS U5911 ( .A(n4764), .Y(n4783) );
BUFX3TS U5912 ( .A(n4783), .Y(n4792) );
AO22XLTS U5913 ( .A0(n4795), .A1(result_add_subt[60]), .B0(n4784), .B1(
d_ff_Zn[60]), .Y(n2525) );
OA22X1TS U5914 ( .A0(n4772), .A1(result_add_subt[59]), .B0(
add_subt_module_exp_oper_result[7]), .B1(n4788), .Y(n2522) );
AO22XLTS U5915 ( .A0(n4795), .A1(result_add_subt[59]), .B0(n4784), .B1(
d_ff_Zn[59]), .Y(n2521) );
AO22XLTS U5916 ( .A0(n4773), .A1(result_add_subt[59]), .B0(n4792), .B1(
d_ff_Xn[59]), .Y(n2519) );
OA22X1TS U5917 ( .A0(n4772), .A1(result_add_subt[58]), .B0(
add_subt_module_exp_oper_result[6]), .B1(n4788), .Y(n2518) );
AO22XLTS U5918 ( .A0(n4795), .A1(result_add_subt[58]), .B0(n4784), .B1(
d_ff_Zn[58]), .Y(n2517) );
AO22XLTS U5919 ( .A0(n4773), .A1(result_add_subt[58]), .B0(n4792), .B1(
d_ff_Xn[58]), .Y(n2515) );
OA22X1TS U5920 ( .A0(n4772), .A1(result_add_subt[57]), .B0(
add_subt_module_exp_oper_result[5]), .B1(n4788), .Y(n2514) );
AO22XLTS U5921 ( .A0(n4795), .A1(result_add_subt[57]), .B0(n4784), .B1(
d_ff_Zn[57]), .Y(n2513) );
BUFX4TS U5922 ( .A(n4775), .Y(n4781) );
AO22XLTS U5923 ( .A0(n4773), .A1(result_add_subt[57]), .B0(n4792), .B1(
d_ff_Xn[57]), .Y(n2511) );
OA22X1TS U5924 ( .A0(n4772), .A1(result_add_subt[56]), .B0(
add_subt_module_exp_oper_result[4]), .B1(n4776), .Y(n2510) );
AO22XLTS U5925 ( .A0(n4795), .A1(result_add_subt[56]), .B0(n4784), .B1(
d_ff_Zn[56]), .Y(n2509) );
AO22XLTS U5926 ( .A0(n4773), .A1(result_add_subt[56]), .B0(n4792), .B1(
d_ff_Xn[56]), .Y(n2507) );
OA22X1TS U5927 ( .A0(n4772), .A1(result_add_subt[55]), .B0(
add_subt_module_exp_oper_result[3]), .B1(n4794), .Y(n2506) );
AO22XLTS U5928 ( .A0(n4795), .A1(result_add_subt[55]), .B0(n4784), .B1(
d_ff_Zn[55]), .Y(n2505) );
AO22XLTS U5929 ( .A0(n4773), .A1(result_add_subt[55]), .B0(n4792), .B1(
d_ff_Xn[55]), .Y(n2503) );
OA22X1TS U5930 ( .A0(n4772), .A1(result_add_subt[54]), .B0(
add_subt_module_exp_oper_result[2]), .B1(n4794), .Y(n2502) );
AO22XLTS U5931 ( .A0(n4795), .A1(result_add_subt[54]), .B0(n4784), .B1(
d_ff_Zn[54]), .Y(n2501) );
AO22XLTS U5932 ( .A0(n4773), .A1(result_add_subt[54]), .B0(n4792), .B1(
d_ff_Xn[54]), .Y(n2499) );
OA22X1TS U5933 ( .A0(n4772), .A1(result_add_subt[53]), .B0(
add_subt_module_exp_oper_result[1]), .B1(n4794), .Y(n2498) );
AO22XLTS U5934 ( .A0(n4795), .A1(result_add_subt[53]), .B0(n4784), .B1(
d_ff_Zn[53]), .Y(n2497) );
INVX2TS U5935 ( .A(n4775), .Y(n4765) );
AO22XLTS U5936 ( .A0(n4773), .A1(result_add_subt[53]), .B0(n4792), .B1(
d_ff_Xn[53]), .Y(n2495) );
OA22X1TS U5937 ( .A0(n4772), .A1(result_add_subt[52]), .B0(
add_subt_module_exp_oper_result[0]), .B1(n4776), .Y(n2494) );
AO22XLTS U5938 ( .A0(n4795), .A1(result_add_subt[52]), .B0(n4784), .B1(
d_ff_Zn[52]), .Y(n2493) );
AO22XLTS U5939 ( .A0(n4773), .A1(result_add_subt[52]), .B0(n4792), .B1(
d_ff_Xn[52]), .Y(n2491) );
OAI2BB2XLTS U5940 ( .B0(n5233), .B1(n4768), .A0N(result_add_subt[51]), .A1N(
n4774), .Y(n2490) );
INVX4TS U5941 ( .A(n2992), .Y(n4770) );
AO22XLTS U5942 ( .A0(n4770), .A1(result_add_subt[51]), .B0(n4784), .B1(
d_ff_Zn[51]), .Y(n2489) );
AO22XLTS U5943 ( .A0(n4773), .A1(result_add_subt[51]), .B0(n4792), .B1(
d_ff_Xn[51]), .Y(n2487) );
OAI2BB2XLTS U5944 ( .B0(n5234), .B1(n4768), .A0N(result_add_subt[50]), .A1N(
n4774), .Y(n2486) );
BUFX3TS U5945 ( .A(n4784), .Y(n4789) );
AO22XLTS U5946 ( .A0(n4770), .A1(result_add_subt[50]), .B0(n4789), .B1(
d_ff_Zn[50]), .Y(n2485) );
BUFX3TS U5947 ( .A(n4783), .Y(n4787) );
AO22XLTS U5948 ( .A0(n4767), .A1(result_add_subt[50]), .B0(n4787), .B1(
d_ff_Xn[50]), .Y(n2483) );
OAI2BB2XLTS U5949 ( .B0(n5224), .B1(n4768), .A0N(result_add_subt[49]), .A1N(
n4774), .Y(n2482) );
AO22XLTS U5950 ( .A0(n4770), .A1(result_add_subt[49]), .B0(n4789), .B1(
d_ff_Zn[49]), .Y(n2481) );
AO22XLTS U5951 ( .A0(n4773), .A1(result_add_subt[49]), .B0(n4787), .B1(
d_ff_Xn[49]), .Y(n2479) );
OAI2BB2XLTS U5952 ( .B0(n5225), .B1(n4768), .A0N(result_add_subt[48]), .A1N(
n4774), .Y(n2478) );
AO22XLTS U5953 ( .A0(n4770), .A1(result_add_subt[48]), .B0(n4789), .B1(
d_ff_Zn[48]), .Y(n2477) );
AO22XLTS U5954 ( .A0(n4767), .A1(result_add_subt[48]), .B0(n4787), .B1(
d_ff_Xn[48]), .Y(n2475) );
OAI2BB2XLTS U5955 ( .B0(n5207), .B1(n4768), .A0N(result_add_subt[47]), .A1N(
n4774), .Y(n2474) );
AO22XLTS U5956 ( .A0(n4770), .A1(result_add_subt[47]), .B0(n4789), .B1(
d_ff_Zn[47]), .Y(n2473) );
AO22XLTS U5957 ( .A0(n4767), .A1(result_add_subt[47]), .B0(n4787), .B1(
d_ff_Xn[47]), .Y(n2471) );
OAI2BB2XLTS U5958 ( .B0(n5202), .B1(n4768), .A0N(result_add_subt[46]), .A1N(
n4774), .Y(n2470) );
AO22XLTS U5959 ( .A0(n4770), .A1(result_add_subt[46]), .B0(n4789), .B1(
d_ff_Zn[46]), .Y(n2469) );
AO22XLTS U5960 ( .A0(n4767), .A1(result_add_subt[46]), .B0(n4787), .B1(
d_ff_Xn[46]), .Y(n2467) );
OAI2BB2XLTS U5961 ( .B0(n5203), .B1(n4768), .A0N(result_add_subt[45]), .A1N(
n4774), .Y(n2466) );
AO22XLTS U5962 ( .A0(n4770), .A1(result_add_subt[45]), .B0(n4789), .B1(
d_ff_Zn[45]), .Y(n2465) );
AO22XLTS U5963 ( .A0(n4767), .A1(result_add_subt[45]), .B0(n4787), .B1(
d_ff_Xn[45]), .Y(n2463) );
OAI2BB2XLTS U5964 ( .B0(n5183), .B1(n4768), .A0N(result_add_subt[44]), .A1N(
n4774), .Y(n2462) );
AO22XLTS U5965 ( .A0(n4770), .A1(result_add_subt[44]), .B0(n4789), .B1(
d_ff_Zn[44]), .Y(n2461) );
AO22XLTS U5966 ( .A0(n4767), .A1(result_add_subt[44]), .B0(n4787), .B1(
d_ff_Xn[44]), .Y(n2459) );
OAI2BB2XLTS U5967 ( .B0(n5184), .B1(n4768), .A0N(result_add_subt[43]), .A1N(
n4774), .Y(n2458) );
AO22XLTS U5968 ( .A0(n4770), .A1(result_add_subt[43]), .B0(n4789), .B1(
d_ff_Zn[43]), .Y(n2457) );
AO22XLTS U5969 ( .A0(n4767), .A1(result_add_subt[43]), .B0(n4787), .B1(
d_ff_Xn[43]), .Y(n2455) );
OAI2BB2XLTS U5970 ( .B0(n5166), .B1(n4768), .A0N(result_add_subt[42]), .A1N(
n4774), .Y(n2454) );
AO22XLTS U5971 ( .A0(n4770), .A1(result_add_subt[42]), .B0(n4789), .B1(
d_ff_Zn[42]), .Y(n2453) );
AO22XLTS U5972 ( .A0(n4767), .A1(result_add_subt[42]), .B0(n4787), .B1(
d_ff_Xn[42]), .Y(n2451) );
OAI2BB2XLTS U5973 ( .B0(n5167), .B1(n4768), .A0N(result_add_subt[41]), .A1N(
n4774), .Y(n2450) );
AO22XLTS U5974 ( .A0(n4770), .A1(result_add_subt[41]), .B0(n4789), .B1(
d_ff_Zn[41]), .Y(n2449) );
AO22XLTS U5975 ( .A0(n4767), .A1(result_add_subt[41]), .B0(n4787), .B1(
d_ff_Xn[41]), .Y(n2447) );
OAI2BB2XLTS U5976 ( .B0(n5139), .B1(n4776), .A0N(result_add_subt[40]), .A1N(
n4774), .Y(n2446) );
AO22XLTS U5977 ( .A0(n4770), .A1(result_add_subt[40]), .B0(n4789), .B1(
d_ff_Zn[40]), .Y(n2445) );
AO22XLTS U5978 ( .A0(n4767), .A1(result_add_subt[40]), .B0(n4787), .B1(
d_ff_Xn[40]), .Y(n2443) );
BUFX4TS U5979 ( .A(n4777), .Y(n4774) );
OAI2BB2XLTS U5980 ( .B0(n5140), .B1(n4768), .A0N(result_add_subt[39]), .A1N(
n4774), .Y(n2442) );
INVX4TS U5981 ( .A(n4769), .Y(n4785) );
BUFX3TS U5982 ( .A(n2992), .Y(n4779) );
AO22XLTS U5983 ( .A0(n4785), .A1(result_add_subt[39]), .B0(n4779), .B1(
d_ff_Zn[39]), .Y(n2441) );
INVX4TS U5984 ( .A(n4764), .Y(n4844) );
AO22XLTS U5985 ( .A0(n4844), .A1(result_add_subt[39]), .B0(n4783), .B1(
d_ff_Xn[39]), .Y(n2439) );
OAI2BB2XLTS U5986 ( .B0(n5135), .B1(n4768), .A0N(result_add_subt[38]), .A1N(
n4774), .Y(n2438) );
INVX4TS U5987 ( .A(n4769), .Y(n4790) );
AO22XLTS U5988 ( .A0(n4790), .A1(result_add_subt[38]), .B0(n4779), .B1(
d_ff_Zn[38]), .Y(n2437) );
INVX4TS U5989 ( .A(n4792), .Y(n4782) );
AO22XLTS U5990 ( .A0(n4782), .A1(result_add_subt[38]), .B0(n4783), .B1(
d_ff_Xn[38]), .Y(n2435) );
OAI2BB2XLTS U5991 ( .B0(n5136), .B1(n4768), .A0N(result_add_subt[37]), .A1N(
n4766), .Y(n2434) );
AO22XLTS U5992 ( .A0(n4795), .A1(result_add_subt[37]), .B0(n4779), .B1(
d_ff_Zn[37]), .Y(n2433) );
AO22XLTS U5993 ( .A0(n4844), .A1(result_add_subt[37]), .B0(n4783), .B1(
d_ff_Xn[37]), .Y(n2431) );
OAI2BB2XLTS U5994 ( .B0(n5137), .B1(n4768), .A0N(result_add_subt[36]), .A1N(
n4774), .Y(n2430) );
AO22XLTS U5995 ( .A0(n4785), .A1(result_add_subt[36]), .B0(n4779), .B1(
d_ff_Zn[36]), .Y(n2429) );
AO22XLTS U5996 ( .A0(n4782), .A1(result_add_subt[36]), .B0(n4783), .B1(
d_ff_Xn[36]), .Y(n2427) );
OAI2BB2XLTS U5997 ( .B0(n5121), .B1(n4776), .A0N(result_add_subt[35]), .A1N(
n4766), .Y(n2426) );
AO22XLTS U5998 ( .A0(n4790), .A1(result_add_subt[35]), .B0(n4779), .B1(
d_ff_Zn[35]), .Y(n2425) );
BUFX3TS U5999 ( .A(n4775), .Y(n4796) );
AO22XLTS U6000 ( .A0(n4844), .A1(result_add_subt[35]), .B0(n4783), .B1(
d_ff_Xn[35]), .Y(n2423) );
OAI2BB2XLTS U6001 ( .B0(n5122), .B1(n4794), .A0N(result_add_subt[34]), .A1N(
n4774), .Y(n2422) );
AO22XLTS U6002 ( .A0(n4795), .A1(result_add_subt[34]), .B0(n4779), .B1(
d_ff_Zn[34]), .Y(n2421) );
AO22XLTS U6003 ( .A0(n4844), .A1(result_add_subt[34]), .B0(n4783), .B1(
d_ff_Xn[34]), .Y(n2419) );
OAI2BB2XLTS U6004 ( .B0(n5123), .B1(n4776), .A0N(result_add_subt[33]), .A1N(
n4766), .Y(n2418) );
AO22XLTS U6005 ( .A0(n4770), .A1(result_add_subt[33]), .B0(n4779), .B1(
d_ff_Zn[33]), .Y(n2417) );
AO22XLTS U6006 ( .A0(n4844), .A1(result_add_subt[33]), .B0(n4783), .B1(
d_ff_Xn[33]), .Y(n2415) );
OAI2BB2XLTS U6007 ( .B0(n5115), .B1(n4794), .A0N(result_add_subt[32]), .A1N(
n4766), .Y(n2414) );
AO22XLTS U6008 ( .A0(n4770), .A1(result_add_subt[32]), .B0(n4779), .B1(
d_ff_Zn[32]), .Y(n2413) );
INVX4TS U6009 ( .A(n4775), .Y(n4797) );
AO22XLTS U6010 ( .A0(n4844), .A1(result_add_subt[32]), .B0(n4783), .B1(
d_ff_Xn[32]), .Y(n2411) );
OAI2BB2XLTS U6011 ( .B0(n5116), .B1(n4776), .A0N(result_add_subt[31]), .A1N(
n4766), .Y(n2410) );
AO22XLTS U6012 ( .A0(n4770), .A1(result_add_subt[31]), .B0(n4779), .B1(
d_ff_Zn[31]), .Y(n2409) );
AO22XLTS U6013 ( .A0(n4844), .A1(result_add_subt[31]), .B0(n4783), .B1(
d_ff_Xn[31]), .Y(n2407) );
OAI2BB2XLTS U6014 ( .B0(n5117), .B1(n4794), .A0N(result_add_subt[30]), .A1N(
n4766), .Y(n2406) );
AO22XLTS U6015 ( .A0(n4770), .A1(result_add_subt[30]), .B0(n4779), .B1(
d_ff_Zn[30]), .Y(n2405) );
AO22XLTS U6016 ( .A0(n4844), .A1(result_add_subt[30]), .B0(n4783), .B1(
d_ff_Xn[30]), .Y(n2403) );
OAI2BB2XLTS U6017 ( .B0(n5111), .B1(n4776), .A0N(result_add_subt[29]), .A1N(
n4766), .Y(n2402) );
AO22XLTS U6018 ( .A0(n4770), .A1(result_add_subt[29]), .B0(n4779), .B1(
d_ff_Zn[29]), .Y(n2401) );
AO22XLTS U6019 ( .A0(n4844), .A1(result_add_subt[29]), .B0(n4783), .B1(
d_ff_Xn[29]), .Y(n2399) );
OAI2BB2XLTS U6020 ( .B0(n5112), .B1(n4794), .A0N(result_add_subt[28]), .A1N(
n4766), .Y(n2398) );
AO22XLTS U6021 ( .A0(n4770), .A1(result_add_subt[28]), .B0(n2992), .B1(
d_ff_Zn[28]), .Y(n2397) );
BUFX3TS U6022 ( .A(n4783), .Y(n4843) );
AO22XLTS U6023 ( .A0(n4844), .A1(result_add_subt[28]), .B0(n4843), .B1(
d_ff_Xn[28]), .Y(n2395) );
OAI2BB2XLTS U6024 ( .B0(n5113), .B1(n4776), .A0N(result_add_subt[27]), .A1N(
n4766), .Y(n2394) );
AO22XLTS U6025 ( .A0(n4790), .A1(result_add_subt[27]), .B0(n2992), .B1(
d_ff_Zn[27]), .Y(n2393) );
AO22XLTS U6026 ( .A0(n4773), .A1(result_add_subt[27]), .B0(n4843), .B1(
d_ff_Xn[27]), .Y(n2391) );
OAI2BB2XLTS U6027 ( .B0(n5108), .B1(n4794), .A0N(result_add_subt[26]), .A1N(
n4766), .Y(n2390) );
AO22XLTS U6028 ( .A0(n4790), .A1(result_add_subt[26]), .B0(n2992), .B1(
d_ff_Zn[26]), .Y(n2389) );
AO22XLTS U6029 ( .A0(n4773), .A1(result_add_subt[26]), .B0(n4843), .B1(
d_ff_Xn[26]), .Y(n2387) );
OAI22X1TS U6030 ( .A0(n4772), .A1(n5081), .B0(n5107), .B1(n4788), .Y(n2386)
);
AO22XLTS U6031 ( .A0(n4790), .A1(result_add_subt[25]), .B0(n2992), .B1(
d_ff_Zn[25]), .Y(n2385) );
OAI22X1TS U6032 ( .A0(n4791), .A1(n5081), .B0(n4796), .B1(n5245), .Y(n2384)
);
OAI2BB2XLTS U6033 ( .B0(n5109), .B1(n4776), .A0N(result_add_subt[24]), .A1N(
n4777), .Y(n2382) );
AO22XLTS U6034 ( .A0(n4790), .A1(result_add_subt[24]), .B0(n2992), .B1(
d_ff_Zn[24]), .Y(n2381) );
AO22XLTS U6035 ( .A0(n4773), .A1(result_add_subt[24]), .B0(n4843), .B1(
d_ff_Xn[24]), .Y(n2379) );
OAI2BB2XLTS U6036 ( .B0(n5104), .B1(n4794), .A0N(result_add_subt[23]), .A1N(
n4777), .Y(n2378) );
AO22XLTS U6037 ( .A0(n4790), .A1(result_add_subt[23]), .B0(n2992), .B1(
d_ff_Zn[23]), .Y(n2377) );
AO22XLTS U6038 ( .A0(n4844), .A1(result_add_subt[23]), .B0(n4843), .B1(
d_ff_Xn[23]), .Y(n2375) );
OAI2BB2XLTS U6039 ( .B0(n5105), .B1(n4776), .A0N(result_add_subt[22]), .A1N(
n4777), .Y(n2374) );
AO22XLTS U6040 ( .A0(n4790), .A1(result_add_subt[22]), .B0(n2992), .B1(
d_ff_Zn[22]), .Y(n2373) );
AO22XLTS U6041 ( .A0(n4782), .A1(result_add_subt[22]), .B0(n4843), .B1(
d_ff_Xn[22]), .Y(n2371) );
OAI2BB2XLTS U6042 ( .B0(n5106), .B1(n4794), .A0N(result_add_subt[21]), .A1N(
n4777), .Y(n2370) );
AO22XLTS U6043 ( .A0(n4790), .A1(result_add_subt[21]), .B0(n2992), .B1(
d_ff_Zn[21]), .Y(n2369) );
AO22XLTS U6044 ( .A0(n4844), .A1(result_add_subt[21]), .B0(n4843), .B1(
d_ff_Xn[21]), .Y(n2367) );
OAI2BB2XLTS U6045 ( .B0(n5102), .B1(n4776), .A0N(result_add_subt[20]), .A1N(
n4766), .Y(n2366) );
AO22XLTS U6046 ( .A0(n4790), .A1(result_add_subt[20]), .B0(n2992), .B1(
d_ff_Zn[20]), .Y(n2365) );
AO22XLTS U6047 ( .A0(n4782), .A1(result_add_subt[20]), .B0(n4843), .B1(
d_ff_Xn[20]), .Y(n2363) );
OAI2BB2XLTS U6048 ( .B0(n5103), .B1(n4794), .A0N(result_add_subt[19]), .A1N(
n4766), .Y(n2362) );
AO22XLTS U6049 ( .A0(n4790), .A1(result_add_subt[19]), .B0(n2992), .B1(
d_ff_Zn[19]), .Y(n2361) );
AO22XLTS U6050 ( .A0(n4844), .A1(result_add_subt[19]), .B0(n4843), .B1(
d_ff_Xn[19]), .Y(n2359) );
OAI2BB2XLTS U6051 ( .B0(n5097), .B1(n4776), .A0N(result_add_subt[18]), .A1N(
n4766), .Y(n2358) );
AO22XLTS U6052 ( .A0(n4790), .A1(result_add_subt[18]), .B0(n2992), .B1(
d_ff_Zn[18]), .Y(n2357) );
AO22XLTS U6053 ( .A0(n4782), .A1(result_add_subt[18]), .B0(n4843), .B1(
d_ff_Xn[18]), .Y(n2355) );
OAI2BB2XLTS U6054 ( .B0(n5098), .B1(n4794), .A0N(result_add_subt[17]), .A1N(
n4766), .Y(n2354) );
AO22XLTS U6055 ( .A0(n4790), .A1(result_add_subt[17]), .B0(n2992), .B1(
d_ff_Zn[17]), .Y(n2353) );
AO22XLTS U6056 ( .A0(n4844), .A1(result_add_subt[17]), .B0(n4780), .B1(
d_ff_Xn[17]), .Y(n2351) );
BUFX3TS U6057 ( .A(n4777), .Y(n4793) );
OAI2BB2XLTS U6058 ( .B0(n5099), .B1(n4776), .A0N(result_add_subt[16]), .A1N(
n4793), .Y(n2350) );
AO22XLTS U6059 ( .A0(n4790), .A1(result_add_subt[16]), .B0(n4779), .B1(
d_ff_Zn[16]), .Y(n2349) );
AO22XLTS U6060 ( .A0(n4782), .A1(result_add_subt[16]), .B0(n4780), .B1(
d_ff_Xn[16]), .Y(n2347) );
OAI2BB2XLTS U6061 ( .B0(n5100), .B1(n4794), .A0N(result_add_subt[15]), .A1N(
n4793), .Y(n2346) );
AO22XLTS U6062 ( .A0(n4785), .A1(result_add_subt[15]), .B0(n2992), .B1(
d_ff_Zn[15]), .Y(n2345) );
AO22XLTS U6063 ( .A0(n4782), .A1(result_add_subt[15]), .B0(n4780), .B1(
d_ff_Xn[15]), .Y(n2343) );
OAI2BB2XLTS U6064 ( .B0(n5095), .B1(n4776), .A0N(result_add_subt[14]), .A1N(
n4793), .Y(n2342) );
AO22XLTS U6065 ( .A0(n4785), .A1(result_add_subt[14]), .B0(n4779), .B1(
d_ff_Zn[14]), .Y(n2341) );
AO22XLTS U6066 ( .A0(n4782), .A1(result_add_subt[14]), .B0(n4780), .B1(
d_ff_Xn[14]), .Y(n2339) );
OAI2BB2XLTS U6067 ( .B0(n5096), .B1(n4794), .A0N(result_add_subt[13]), .A1N(
n4793), .Y(n2338) );
AO22XLTS U6068 ( .A0(n4785), .A1(result_add_subt[13]), .B0(n2992), .B1(
d_ff_Zn[13]), .Y(n2337) );
AO22XLTS U6069 ( .A0(n4782), .A1(result_add_subt[13]), .B0(n4780), .B1(
d_ff_Xn[13]), .Y(n2335) );
OAI2BB2XLTS U6070 ( .B0(n5091), .B1(n4788), .A0N(result_add_subt[12]), .A1N(
n4777), .Y(n2334) );
AO22XLTS U6071 ( .A0(n4785), .A1(result_add_subt[12]), .B0(n4784), .B1(
d_ff_Zn[12]), .Y(n2333) );
AO22XLTS U6072 ( .A0(n4782), .A1(result_add_subt[12]), .B0(n4780), .B1(
d_ff_Xn[12]), .Y(n2331) );
OAI2BB2XLTS U6073 ( .B0(n5092), .B1(n4788), .A0N(result_add_subt[11]), .A1N(
n4777), .Y(n2330) );
AO22XLTS U6074 ( .A0(n4785), .A1(result_add_subt[11]), .B0(n4789), .B1(
d_ff_Zn[11]), .Y(n2329) );
AO22XLTS U6075 ( .A0(n4782), .A1(result_add_subt[11]), .B0(n4780), .B1(
d_ff_Xn[11]), .Y(n2327) );
OAI2BB2XLTS U6076 ( .B0(n5093), .B1(n4788), .A0N(result_add_subt[10]), .A1N(
n4793), .Y(n2326) );
AO22XLTS U6077 ( .A0(n4785), .A1(result_add_subt[10]), .B0(n4784), .B1(
d_ff_Zn[10]), .Y(n2325) );
AO22XLTS U6078 ( .A0(n4782), .A1(result_add_subt[10]), .B0(n4780), .B1(
d_ff_Xn[10]), .Y(n2323) );
OAI2BB2XLTS U6079 ( .B0(n5094), .B1(n4788), .A0N(result_add_subt[9]), .A1N(
n4793), .Y(n2322) );
AO22XLTS U6080 ( .A0(n4785), .A1(result_add_subt[9]), .B0(n4789), .B1(
d_ff_Zn[9]), .Y(n2321) );
AO22XLTS U6081 ( .A0(n4782), .A1(result_add_subt[9]), .B0(n4780), .B1(
d_ff_Xn[9]), .Y(n2319) );
OAI2BB2XLTS U6082 ( .B0(n5089), .B1(n4788), .A0N(result_add_subt[8]), .A1N(
n4793), .Y(n2318) );
AO22XLTS U6083 ( .A0(n4785), .A1(result_add_subt[8]), .B0(n2992), .B1(
d_ff_Zn[8]), .Y(n2317) );
AO22XLTS U6084 ( .A0(n4782), .A1(result_add_subt[8]), .B0(n4780), .B1(
d_ff_Xn[8]), .Y(n2315) );
OAI2BB2XLTS U6085 ( .B0(n5090), .B1(n4788), .A0N(result_add_subt[7]), .A1N(
n4793), .Y(n2314) );
AO22XLTS U6086 ( .A0(n4785), .A1(result_add_subt[7]), .B0(n4779), .B1(
d_ff_Zn[7]), .Y(n2313) );
AO22XLTS U6087 ( .A0(n4782), .A1(result_add_subt[7]), .B0(n4780), .B1(
d_ff_Xn[7]), .Y(n2311) );
OAI2BB2XLTS U6088 ( .B0(n5086), .B1(n4788), .A0N(result_add_subt[6]), .A1N(
n4793), .Y(n2310) );
AO22XLTS U6089 ( .A0(n4785), .A1(result_add_subt[6]), .B0(n4784), .B1(
d_ff_Zn[6]), .Y(n2309) );
AO22XLTS U6090 ( .A0(n4782), .A1(result_add_subt[6]), .B0(n4783), .B1(
d_ff_Xn[6]), .Y(n2307) );
OAI2BB2XLTS U6091 ( .B0(n5087), .B1(n4788), .A0N(result_add_subt[5]), .A1N(
n4793), .Y(n2306) );
AO22XLTS U6092 ( .A0(n4785), .A1(result_add_subt[5]), .B0(n4784), .B1(
d_ff_Zn[5]), .Y(n2305) );
AO22XLTS U6093 ( .A0(n4782), .A1(result_add_subt[5]), .B0(n4783), .B1(
d_ff_Xn[5]), .Y(n2303) );
OAI2BB2XLTS U6094 ( .B0(n5088), .B1(n4788), .A0N(result_add_subt[4]), .A1N(
n4793), .Y(n2302) );
AO22XLTS U6095 ( .A0(n4785), .A1(result_add_subt[4]), .B0(n4784), .B1(
d_ff_Zn[4]), .Y(n2301) );
AO22XLTS U6096 ( .A0(n4782), .A1(result_add_subt[4]), .B0(n4783), .B1(
d_ff_Xn[4]), .Y(n2299) );
OAI2BB2XLTS U6097 ( .B0(n5083), .B1(n4788), .A0N(result_add_subt[3]), .A1N(
n4793), .Y(n2298) );
AO22XLTS U6098 ( .A0(n4795), .A1(result_add_subt[3]), .B0(n4784), .B1(
d_ff_Zn[3]), .Y(n2297) );
AO22XLTS U6099 ( .A0(n4844), .A1(result_add_subt[3]), .B0(n4783), .B1(
d_ff_Xn[3]), .Y(n2295) );
OAI2BB2XLTS U6100 ( .B0(n5084), .B1(n4788), .A0N(result_add_subt[2]), .A1N(
n4793), .Y(n2294) );
AO22XLTS U6101 ( .A0(n4785), .A1(result_add_subt[2]), .B0(n4784), .B1(
d_ff_Zn[2]), .Y(n2293) );
AO22XLTS U6102 ( .A0(n4844), .A1(result_add_subt[2]), .B0(n4787), .B1(
d_ff_Xn[2]), .Y(n2291) );
OAI2BB2XLTS U6103 ( .B0(n5085), .B1(n4788), .A0N(result_add_subt[1]), .A1N(
n4774), .Y(n2290) );
AO22XLTS U6104 ( .A0(n4790), .A1(result_add_subt[1]), .B0(n4789), .B1(
d_ff_Zn[1]), .Y(n2289) );
AO22XLTS U6105 ( .A0(n4844), .A1(result_add_subt[1]), .B0(n4792), .B1(
d_ff_Xn[1]), .Y(n2287) );
OAI2BB2XLTS U6106 ( .B0(n5242), .B1(n4794), .A0N(result_add_subt[0]), .A1N(
n4793), .Y(n2286) );
AO22XLTS U6107 ( .A0(n4795), .A1(result_add_subt[0]), .B0(n4784), .B1(
d_ff_Zn[0]), .Y(n2285) );
AO22XLTS U6108 ( .A0(n4826), .A1(d_ff2_Z[63]), .B0(n4805), .B1(
d_ff3_sign_out), .Y(n2220) );
AO22XLTS U6109 ( .A0(d_ff_Yn[0]), .A1(n3300), .B0(d_ff2_Y[0]), .B1(n4804),
.Y(n2218) );
AO22XLTS U6110 ( .A0(n4826), .A1(d_ff2_Y[0]), .B0(n4810), .B1(
d_ff3_sh_y_out[0]), .Y(n2217) );
AO22XLTS U6111 ( .A0(d_ff_Yn[1]), .A1(n4799), .B0(d_ff2_Y[1]), .B1(n4804),
.Y(n2216) );
AO22XLTS U6112 ( .A0(n4836), .A1(d_ff2_Y[1]), .B0(n4801), .B1(
d_ff3_sh_y_out[1]), .Y(n2215) );
AO22XLTS U6113 ( .A0(d_ff_Yn[2]), .A1(n4809), .B0(d_ff2_Y[2]), .B1(n4804),
.Y(n2214) );
AO22XLTS U6114 ( .A0(n4826), .A1(d_ff2_Y[2]), .B0(n4817), .B1(
d_ff3_sh_y_out[2]), .Y(n2213) );
AO22XLTS U6115 ( .A0(d_ff_Yn[3]), .A1(n4809), .B0(d_ff2_Y[3]), .B1(n4804),
.Y(n2212) );
AO22XLTS U6116 ( .A0(n4836), .A1(d_ff2_Y[3]), .B0(n4817), .B1(
d_ff3_sh_y_out[3]), .Y(n2211) );
AO22XLTS U6117 ( .A0(d_ff_Yn[4]), .A1(n4799), .B0(d_ff2_Y[4]), .B1(n4804),
.Y(n2210) );
AO22XLTS U6118 ( .A0(n4836), .A1(d_ff2_Y[4]), .B0(n4817), .B1(
d_ff3_sh_y_out[4]), .Y(n2209) );
AO22XLTS U6119 ( .A0(d_ff_Yn[5]), .A1(n4809), .B0(d_ff2_Y[5]), .B1(n4804),
.Y(n2208) );
AO22XLTS U6120 ( .A0(n4840), .A1(d_ff2_Y[5]), .B0(n4817), .B1(
d_ff3_sh_y_out[5]), .Y(n2207) );
AO22XLTS U6121 ( .A0(d_ff_Yn[6]), .A1(n4809), .B0(d_ff2_Y[6]), .B1(n4804),
.Y(n2206) );
AO22XLTS U6122 ( .A0(n4833), .A1(d_ff2_Y[6]), .B0(n4817), .B1(
d_ff3_sh_y_out[6]), .Y(n2205) );
AO22XLTS U6123 ( .A0(d_ff_Yn[7]), .A1(n4842), .B0(d_ff2_Y[7]), .B1(n4804),
.Y(n2204) );
AO22XLTS U6124 ( .A0(n4833), .A1(d_ff2_Y[7]), .B0(n4805), .B1(
d_ff3_sh_y_out[7]), .Y(n2203) );
AO22XLTS U6125 ( .A0(d_ff_Yn[8]), .A1(n4799), .B0(d_ff2_Y[8]), .B1(n4804),
.Y(n2202) );
AO22XLTS U6126 ( .A0(n4833), .A1(d_ff2_Y[8]), .B0(n4810), .B1(
d_ff3_sh_y_out[8]), .Y(n2201) );
AO22XLTS U6127 ( .A0(d_ff_Yn[9]), .A1(n4809), .B0(d_ff2_Y[9]), .B1(n4841),
.Y(n2200) );
AO22XLTS U6128 ( .A0(n4833), .A1(d_ff2_Y[9]), .B0(n4801), .B1(
d_ff3_sh_y_out[9]), .Y(n2199) );
AO22XLTS U6129 ( .A0(d_ff_Yn[10]), .A1(n4842), .B0(d_ff2_Y[10]), .B1(n4841),
.Y(n2198) );
AO22XLTS U6130 ( .A0(n4833), .A1(d_ff2_Y[10]), .B0(n4801), .B1(
d_ff3_sh_y_out[10]), .Y(n2197) );
AO22XLTS U6131 ( .A0(d_ff_Yn[11]), .A1(n4809), .B0(d_ff2_Y[11]), .B1(n4841),
.Y(n2196) );
AO22XLTS U6132 ( .A0(n4833), .A1(d_ff2_Y[11]), .B0(n4801), .B1(
d_ff3_sh_y_out[11]), .Y(n2195) );
AO22XLTS U6133 ( .A0(d_ff_Yn[12]), .A1(n4799), .B0(d_ff2_Y[12]), .B1(n4841),
.Y(n2194) );
AO22XLTS U6134 ( .A0(n4826), .A1(d_ff2_Y[12]), .B0(n4801), .B1(
d_ff3_sh_y_out[12]), .Y(n2193) );
AO22XLTS U6135 ( .A0(d_ff_Yn[13]), .A1(n4799), .B0(d_ff2_Y[13]), .B1(n4841),
.Y(n2192) );
AO22XLTS U6136 ( .A0(n4826), .A1(d_ff2_Y[13]), .B0(n4801), .B1(
d_ff3_sh_y_out[13]), .Y(n2191) );
AO22XLTS U6137 ( .A0(n4826), .A1(d_ff2_Y[14]), .B0(n4801), .B1(
d_ff3_sh_y_out[14]), .Y(n2189) );
AO22XLTS U6138 ( .A0(d_ff_Yn[15]), .A1(n4842), .B0(d_ff2_Y[15]), .B1(n4841),
.Y(n2188) );
AO22XLTS U6139 ( .A0(n4826), .A1(d_ff2_Y[15]), .B0(n4801), .B1(
d_ff3_sh_y_out[15]), .Y(n2187) );
AO22XLTS U6140 ( .A0(d_ff_Yn[16]), .A1(n4842), .B0(d_ff2_Y[16]), .B1(n4841),
.Y(n2186) );
AO22XLTS U6141 ( .A0(n4826), .A1(d_ff2_Y[16]), .B0(n4801), .B1(
d_ff3_sh_y_out[16]), .Y(n2185) );
AO22XLTS U6142 ( .A0(d_ff_Yn[17]), .A1(n4798), .B0(d_ff2_Y[17]), .B1(n4841),
.Y(n2184) );
AO22XLTS U6143 ( .A0(n4826), .A1(d_ff2_Y[17]), .B0(n4801), .B1(
d_ff3_sh_y_out[17]), .Y(n2183) );
AO22XLTS U6144 ( .A0(d_ff_Yn[18]), .A1(n4842), .B0(d_ff2_Y[18]), .B1(n4806),
.Y(n2182) );
AO22XLTS U6145 ( .A0(n4826), .A1(d_ff2_Y[18]), .B0(n4801), .B1(
d_ff3_sh_y_out[18]), .Y(n2181) );
AO22XLTS U6146 ( .A0(d_ff_Yn[19]), .A1(n4842), .B0(d_ff2_Y[19]), .B1(n4806),
.Y(n2180) );
AO22XLTS U6147 ( .A0(n4826), .A1(d_ff2_Y[19]), .B0(n4801), .B1(
d_ff3_sh_y_out[19]), .Y(n2179) );
AO22XLTS U6148 ( .A0(d_ff_Yn[20]), .A1(n4842), .B0(d_ff2_Y[20]), .B1(n4806),
.Y(n2178) );
AO22XLTS U6149 ( .A0(n4808), .A1(d_ff2_Y[20]), .B0(n4801), .B1(
d_ff3_sh_y_out[20]), .Y(n2177) );
AO22XLTS U6150 ( .A0(d_ff_Yn[21]), .A1(n4798), .B0(d_ff2_Y[21]), .B1(n4802),
.Y(n2176) );
AO22XLTS U6151 ( .A0(n4808), .A1(d_ff2_Y[21]), .B0(n4805), .B1(
d_ff3_sh_y_out[21]), .Y(n2175) );
AO22XLTS U6152 ( .A0(n4808), .A1(d_ff2_Y[22]), .B0(n4805), .B1(
d_ff3_sh_y_out[22]), .Y(n2173) );
AO22XLTS U6153 ( .A0(d_ff_Yn[23]), .A1(n3300), .B0(d_ff2_Y[23]), .B1(n4804),
.Y(n2172) );
AO22XLTS U6154 ( .A0(n4808), .A1(d_ff2_Y[23]), .B0(n4805), .B1(
d_ff3_sh_y_out[23]), .Y(n2171) );
AO22XLTS U6155 ( .A0(d_ff_Yn[24]), .A1(n4842), .B0(d_ff2_Y[24]), .B1(n4806),
.Y(n2170) );
AO22XLTS U6156 ( .A0(n4808), .A1(d_ff2_Y[24]), .B0(n4805), .B1(
d_ff3_sh_y_out[24]), .Y(n2169) );
AO22XLTS U6157 ( .A0(d_ff_Yn[25]), .A1(n4798), .B0(d_ff2_Y[25]), .B1(n4806),
.Y(n2168) );
AO22XLTS U6158 ( .A0(n4808), .A1(d_ff2_Y[25]), .B0(n4805), .B1(
d_ff3_sh_y_out[25]), .Y(n2167) );
AO22XLTS U6159 ( .A0(d_ff_Yn[26]), .A1(n4799), .B0(d_ff2_Y[26]), .B1(n4811),
.Y(n2166) );
AO22XLTS U6160 ( .A0(n4808), .A1(d_ff2_Y[26]), .B0(n4805), .B1(
d_ff3_sh_y_out[26]), .Y(n2165) );
AO22XLTS U6161 ( .A0(d_ff_Yn[27]), .A1(n3300), .B0(d_ff2_Y[27]), .B1(n4806),
.Y(n2164) );
AO22XLTS U6162 ( .A0(n4840), .A1(d_ff2_Y[27]), .B0(n4805), .B1(
d_ff3_sh_y_out[27]), .Y(n2163) );
AO22XLTS U6163 ( .A0(d_ff_Yn[28]), .A1(n4842), .B0(d_ff2_Y[28]), .B1(n4841),
.Y(n2162) );
AO22XLTS U6164 ( .A0(n4840), .A1(d_ff2_Y[28]), .B0(n4805), .B1(
d_ff3_sh_y_out[28]), .Y(n2161) );
AO22XLTS U6165 ( .A0(d_ff_Yn[29]), .A1(n4807), .B0(d_ff2_Y[29]), .B1(n4811),
.Y(n2160) );
AO22XLTS U6166 ( .A0(n4840), .A1(d_ff2_Y[29]), .B0(n4805), .B1(
d_ff3_sh_y_out[29]), .Y(n2159) );
AO22XLTS U6167 ( .A0(d_ff_Yn[30]), .A1(n4842), .B0(d_ff2_Y[30]), .B1(n4806),
.Y(n2158) );
AO22XLTS U6168 ( .A0(n4822), .A1(d_ff2_Y[30]), .B0(n4805), .B1(
d_ff3_sh_y_out[30]), .Y(n2157) );
AO22XLTS U6169 ( .A0(d_ff_Yn[31]), .A1(n4798), .B0(d_ff2_Y[31]), .B1(n4806),
.Y(n2156) );
AO22XLTS U6170 ( .A0(n4840), .A1(d_ff2_Y[31]), .B0(n4805), .B1(
d_ff3_sh_y_out[31]), .Y(n2155) );
AO22XLTS U6171 ( .A0(d_ff_Yn[32]), .A1(n4807), .B0(d_ff2_Y[32]), .B1(n4841),
.Y(n2154) );
AO22XLTS U6172 ( .A0(n4826), .A1(d_ff2_Y[32]), .B0(n4810), .B1(
d_ff3_sh_y_out[32]), .Y(n2153) );
AO22XLTS U6173 ( .A0(d_ff_Yn[33]), .A1(n4842), .B0(d_ff2_Y[33]), .B1(n4806),
.Y(n2152) );
AO22XLTS U6174 ( .A0(n4819), .A1(d_ff2_Y[33]), .B0(n4810), .B1(
d_ff3_sh_y_out[33]), .Y(n2151) );
AO22XLTS U6175 ( .A0(d_ff_Yn[34]), .A1(n4798), .B0(d_ff2_Y[34]), .B1(n4811),
.Y(n2150) );
AO22XLTS U6176 ( .A0(n4819), .A1(d_ff2_Y[34]), .B0(n4810), .B1(
d_ff3_sh_y_out[34]), .Y(n2149) );
AO22XLTS U6177 ( .A0(d_ff_Yn[35]), .A1(n4809), .B0(d_ff2_Y[35]), .B1(n4841),
.Y(n2148) );
AO22XLTS U6178 ( .A0(n4819), .A1(d_ff2_Y[35]), .B0(n4810), .B1(
d_ff3_sh_y_out[35]), .Y(n2147) );
AO22XLTS U6179 ( .A0(d_ff_Yn[36]), .A1(n4842), .B0(d_ff2_Y[36]), .B1(n4811),
.Y(n2146) );
AO22XLTS U6180 ( .A0(n4819), .A1(d_ff2_Y[36]), .B0(n4810), .B1(
d_ff3_sh_y_out[36]), .Y(n2145) );
AO22XLTS U6181 ( .A0(d_ff_Yn[37]), .A1(n4842), .B0(d_ff2_Y[37]), .B1(n4841),
.Y(n2144) );
AO22XLTS U6182 ( .A0(n4819), .A1(d_ff2_Y[37]), .B0(n4810), .B1(
d_ff3_sh_y_out[37]), .Y(n2143) );
AO22XLTS U6183 ( .A0(d_ff_Yn[38]), .A1(n4809), .B0(d_ff2_Y[38]), .B1(n4811),
.Y(n2142) );
AO22XLTS U6184 ( .A0(n4819), .A1(d_ff2_Y[38]), .B0(n4810), .B1(
d_ff3_sh_y_out[38]), .Y(n2141) );
AO22XLTS U6185 ( .A0(d_ff_Yn[39]), .A1(n4842), .B0(d_ff2_Y[39]), .B1(n4841),
.Y(n2140) );
AO22XLTS U6186 ( .A0(n4819), .A1(d_ff2_Y[39]), .B0(n4810), .B1(
d_ff3_sh_y_out[39]), .Y(n2139) );
AO22XLTS U6187 ( .A0(d_ff_Yn[40]), .A1(n4842), .B0(d_ff2_Y[40]), .B1(n4811),
.Y(n2138) );
AO22XLTS U6188 ( .A0(n4819), .A1(d_ff2_Y[40]), .B0(n4810), .B1(
d_ff3_sh_y_out[40]), .Y(n2137) );
AO22XLTS U6189 ( .A0(d_ff_Yn[41]), .A1(n4809), .B0(d_ff2_Y[41]), .B1(n4811),
.Y(n2136) );
AO22XLTS U6190 ( .A0(n4808), .A1(d_ff2_Y[41]), .B0(n4818), .B1(
d_ff3_sh_y_out[41]), .Y(n2135) );
AO22XLTS U6191 ( .A0(d_ff_Yn[42]), .A1(n4799), .B0(d_ff2_Y[42]), .B1(n4811),
.Y(n2134) );
AO22XLTS U6192 ( .A0(n4808), .A1(d_ff2_Y[42]), .B0(n4817), .B1(
d_ff3_sh_y_out[42]), .Y(n2133) );
AO22XLTS U6193 ( .A0(d_ff_Yn[43]), .A1(n4809), .B0(d_ff2_Y[43]), .B1(n4811),
.Y(n2132) );
AO22XLTS U6194 ( .A0(n4808), .A1(d_ff2_Y[43]), .B0(n4838), .B1(
d_ff3_sh_y_out[43]), .Y(n2131) );
AO22XLTS U6195 ( .A0(d_ff_Yn[44]), .A1(n4809), .B0(d_ff2_Y[44]), .B1(n4811),
.Y(n2130) );
AO22XLTS U6196 ( .A0(n4808), .A1(d_ff2_Y[44]), .B0(n4838), .B1(
d_ff3_sh_y_out[44]), .Y(n2129) );
AO22XLTS U6197 ( .A0(d_ff_Yn[45]), .A1(n4799), .B0(d_ff2_Y[45]), .B1(n4811),
.Y(n2128) );
AO22XLTS U6198 ( .A0(n4808), .A1(d_ff2_Y[45]), .B0(n4810), .B1(
d_ff3_sh_y_out[45]), .Y(n2127) );
AO22XLTS U6199 ( .A0(d_ff_Yn[46]), .A1(n4842), .B0(d_ff2_Y[46]), .B1(n4811),
.Y(n2126) );
AO22XLTS U6200 ( .A0(n4808), .A1(d_ff2_Y[46]), .B0(n4838), .B1(
d_ff3_sh_y_out[46]), .Y(n2125) );
AO22XLTS U6201 ( .A0(d_ff_Yn[47]), .A1(n4799), .B0(d_ff2_Y[47]), .B1(n4811),
.Y(n2124) );
AO22XLTS U6202 ( .A0(n4840), .A1(d_ff2_Y[47]), .B0(n4838), .B1(
d_ff3_sh_y_out[47]), .Y(n2123) );
AO22XLTS U6203 ( .A0(d_ff_Yn[48]), .A1(n4842), .B0(d_ff2_Y[48]), .B1(n4811),
.Y(n2122) );
AO22XLTS U6204 ( .A0(n4836), .A1(d_ff2_Y[48]), .B0(n4838), .B1(
d_ff3_sh_y_out[48]), .Y(n2121) );
AO22XLTS U6205 ( .A0(d_ff_Yn[49]), .A1(n4809), .B0(d_ff2_Y[49]), .B1(n4811),
.Y(n2120) );
AO22XLTS U6206 ( .A0(n4808), .A1(d_ff2_Y[49]), .B0(n4838), .B1(
d_ff3_sh_y_out[49]), .Y(n2119) );
AO22XLTS U6207 ( .A0(d_ff_Yn[50]), .A1(n4809), .B0(d_ff2_Y[50]), .B1(n4811),
.Y(n2118) );
AO22XLTS U6208 ( .A0(n4829), .A1(d_ff2_Y[50]), .B0(n4838), .B1(
d_ff3_sh_y_out[50]), .Y(n2117) );
AO22XLTS U6209 ( .A0(d_ff_Yn[51]), .A1(n4799), .B0(d_ff2_Y[51]), .B1(n4811),
.Y(n2116) );
AO22XLTS U6210 ( .A0(n4829), .A1(d_ff2_Y[51]), .B0(n4810), .B1(
d_ff3_sh_y_out[51]), .Y(n2115) );
OAI22X1TS U6211 ( .A0(n2972), .A1(n4812), .B0(n4814), .B1(n4813), .Y(n2114)
);
AO22XLTS U6212 ( .A0(d_ff_Yn[53]), .A1(n4809), .B0(d_ff2_Y[53]), .B1(n4811),
.Y(n2113) );
AO22XLTS U6213 ( .A0(d_ff_Yn[54]), .A1(n4799), .B0(d_ff2_Y[54]), .B1(n4811),
.Y(n2112) );
AO22XLTS U6214 ( .A0(d_ff_Yn[55]), .A1(n4809), .B0(d_ff2_Y[55]), .B1(n4841),
.Y(n2111) );
AO22XLTS U6215 ( .A0(d_ff_Yn[56]), .A1(n4842), .B0(d_ff2_Y[56]), .B1(n4841),
.Y(n2110) );
OAI22X1TS U6216 ( .A0(n5244), .A1(n4813), .B0(n2969), .B1(n4812), .Y(n2109)
);
INVX1TS U6217 ( .A(d_ff2_Y[58]), .Y(n4823) );
OAI22X1TS U6218 ( .A0(n4823), .A1(n4813), .B0(n2970), .B1(n4812), .Y(n2108)
);
AO22XLTS U6219 ( .A0(d_ff_Yn[59]), .A1(n4809), .B0(d_ff2_Y[59]), .B1(n4841),
.Y(n2107) );
INVX1TS U6220 ( .A(d_ff2_Y[60]), .Y(n4830) );
OAI22X1TS U6221 ( .A0(n4830), .A1(n4813), .B0(n2971), .B1(n4812), .Y(n2106)
);
AO22XLTS U6222 ( .A0(d_ff_Yn[61]), .A1(n4809), .B0(d_ff2_Y[61]), .B1(n4841),
.Y(n2105) );
AO22XLTS U6223 ( .A0(d_ff_Yn[62]), .A1(n4809), .B0(d_ff2_Y[62]), .B1(n4841),
.Y(n2104) );
OAI21XLTS U6224 ( .A0(cont_iter_out[0]), .A1(n4814), .B0(intadd_372_CI), .Y(
n4816) );
AO22XLTS U6225 ( .A0(n4829), .A1(n4816), .B0(n4817), .B1(d_ff3_sh_y_out[52]),
.Y(n2103) );
AO22XLTS U6226 ( .A0(n4833), .A1(intadd_372_SUM_0_), .B0(n4817), .B1(
d_ff3_sh_y_out[53]), .Y(n2102) );
AO22XLTS U6227 ( .A0(n4840), .A1(intadd_372_SUM_1_), .B0(n4817), .B1(
d_ff3_sh_y_out[54]), .Y(n2101) );
AO22XLTS U6228 ( .A0(n4819), .A1(intadd_372_SUM_2_), .B0(n4818), .B1(
d_ff3_sh_y_out[55]), .Y(n2100) );
AOI21X1TS U6229 ( .A0(d_ff2_Y[56]), .A1(intadd_372_n1), .B0(n4820), .Y(n4821) );
AOI2BB1XLTS U6230 ( .A0N(n4706), .A1N(d_ff3_sh_y_out[56]), .B0(n4821), .Y(
n2099) );
NAND2X1TS U6231 ( .A(n4824), .B(n4823), .Y(n4827) );
OAI21XLTS U6232 ( .A0(n4824), .A1(n4823), .B0(n4827), .Y(n4825) );
AO22XLTS U6233 ( .A0(n4826), .A1(n4825), .B0(n4838), .B1(d_ff3_sh_y_out[58]),
.Y(n2097) );
AOI21X1TS U6234 ( .A0(d_ff2_Y[59]), .A1(n4827), .B0(n4831), .Y(n4828) );
AOI2BB2XLTS U6235 ( .B0(n4829), .B1(n4828), .A0N(d_ff3_sh_y_out[59]), .A1N(
n4836), .Y(n2096) );
NAND2X1TS U6236 ( .A(n4831), .B(n4830), .Y(n4834) );
OAI21XLTS U6237 ( .A0(n4831), .A1(n4830), .B0(n4834), .Y(n4832) );
AO22XLTS U6238 ( .A0(n4833), .A1(n4832), .B0(n4838), .B1(d_ff3_sh_y_out[60]),
.Y(n2095) );
NOR2X1TS U6239 ( .A(d_ff2_Y[61]), .B(n4834), .Y(n4837) );
AOI21X1TS U6240 ( .A0(d_ff2_Y[61]), .A1(n4834), .B0(n4837), .Y(n4835) );
AOI2BB2XLTS U6241 ( .B0(n4836), .B1(n4835), .A0N(d_ff3_sh_y_out[61]), .A1N(
n4836), .Y(n2094) );
XOR2XLTS U6242 ( .A(d_ff2_Y[62]), .B(n4837), .Y(n4839) );
AO22XLTS U6243 ( .A0(n4840), .A1(n4839), .B0(n4838), .B1(d_ff3_sh_y_out[62]),
.Y(n2093) );
AO22XLTS U6244 ( .A0(n4844), .A1(result_add_subt[0]), .B0(n4843), .B1(
d_ff_Xn[0]), .Y(n2090) );
INVX4TS U6245 ( .A(n4845), .Y(n4846) );
AO22XLTS U6246 ( .A0(n4846), .A1(sign_inv_out[0]), .B0(n4845), .B1(
data_output[0]), .Y(n2088) );
AO22XLTS U6247 ( .A0(n4846), .A1(sign_inv_out[1]), .B0(n4845), .B1(
data_output[1]), .Y(n2086) );
AO22XLTS U6248 ( .A0(n4846), .A1(sign_inv_out[2]), .B0(n4848), .B1(
data_output[2]), .Y(n2084) );
AO22XLTS U6249 ( .A0(n4846), .A1(sign_inv_out[3]), .B0(n4848), .B1(
data_output[3]), .Y(n2082) );
AO22XLTS U6250 ( .A0(n4846), .A1(sign_inv_out[4]), .B0(n4848), .B1(
data_output[4]), .Y(n2080) );
AO22XLTS U6251 ( .A0(n4846), .A1(sign_inv_out[5]), .B0(n4848), .B1(
data_output[5]), .Y(n2078) );
AO22XLTS U6252 ( .A0(n4846), .A1(sign_inv_out[6]), .B0(n4848), .B1(
data_output[6]), .Y(n2076) );
AO22XLTS U6253 ( .A0(n4846), .A1(sign_inv_out[7]), .B0(n4848), .B1(
data_output[7]), .Y(n2074) );
AO22XLTS U6254 ( .A0(n4846), .A1(sign_inv_out[8]), .B0(n4848), .B1(
data_output[8]), .Y(n2072) );
AO22XLTS U6255 ( .A0(n4846), .A1(sign_inv_out[9]), .B0(n4848), .B1(
data_output[9]), .Y(n2070) );
AO22XLTS U6256 ( .A0(n4846), .A1(sign_inv_out[10]), .B0(n4848), .B1(
data_output[10]), .Y(n2068) );
AO22XLTS U6257 ( .A0(n4846), .A1(sign_inv_out[11]), .B0(n4848), .B1(
data_output[11]), .Y(n2066) );
INVX4TS U6258 ( .A(n4845), .Y(n4847) );
BUFX3TS U6259 ( .A(n4845), .Y(n4849) );
AO22XLTS U6260 ( .A0(n4847), .A1(sign_inv_out[12]), .B0(n4849), .B1(
data_output[12]), .Y(n2064) );
AO22XLTS U6261 ( .A0(n4847), .A1(sign_inv_out[13]), .B0(n4849), .B1(
data_output[13]), .Y(n2062) );
AO22XLTS U6262 ( .A0(n4847), .A1(sign_inv_out[14]), .B0(n4849), .B1(
data_output[14]), .Y(n2060) );
AO22XLTS U6263 ( .A0(n4847), .A1(sign_inv_out[15]), .B0(n4849), .B1(
data_output[15]), .Y(n2058) );
AO22XLTS U6264 ( .A0(n4847), .A1(sign_inv_out[16]), .B0(n4849), .B1(
data_output[16]), .Y(n2056) );
AO22XLTS U6265 ( .A0(n4847), .A1(sign_inv_out[17]), .B0(n4849), .B1(
data_output[17]), .Y(n2054) );
AO22XLTS U6266 ( .A0(n4847), .A1(sign_inv_out[18]), .B0(n4849), .B1(
data_output[18]), .Y(n2052) );
AO22XLTS U6267 ( .A0(n4847), .A1(sign_inv_out[19]), .B0(n4849), .B1(
data_output[19]), .Y(n2050) );
AO22XLTS U6268 ( .A0(n4847), .A1(sign_inv_out[20]), .B0(n4849), .B1(
data_output[20]), .Y(n2048) );
AO22XLTS U6269 ( .A0(n4847), .A1(sign_inv_out[21]), .B0(n4849), .B1(
data_output[21]), .Y(n2046) );
AO22XLTS U6270 ( .A0(n4847), .A1(sign_inv_out[22]), .B0(n4849), .B1(
data_output[22]), .Y(n2044) );
AO22XLTS U6271 ( .A0(n4847), .A1(sign_inv_out[23]), .B0(n4845), .B1(
data_output[23]), .Y(n2042) );
AO22XLTS U6272 ( .A0(n4846), .A1(sign_inv_out[24]), .B0(n4852), .B1(
data_output[24]), .Y(n2040) );
AO22XLTS U6273 ( .A0(n4847), .A1(sign_inv_out[25]), .B0(n4848), .B1(
data_output[25]), .Y(n2038) );
AO22XLTS U6274 ( .A0(n4846), .A1(sign_inv_out[26]), .B0(n4852), .B1(
data_output[26]), .Y(n2036) );
AO22XLTS U6275 ( .A0(n4847), .A1(sign_inv_out[27]), .B0(n4848), .B1(
data_output[27]), .Y(n2034) );
AO22XLTS U6276 ( .A0(n4846), .A1(sign_inv_out[28]), .B0(n4848), .B1(
data_output[28]), .Y(n2032) );
AO22XLTS U6277 ( .A0(n4847), .A1(sign_inv_out[29]), .B0(n4852), .B1(
data_output[29]), .Y(n2030) );
AO22XLTS U6278 ( .A0(n4846), .A1(sign_inv_out[30]), .B0(n4848), .B1(
data_output[30]), .Y(n2028) );
AO22XLTS U6279 ( .A0(n4847), .A1(sign_inv_out[31]), .B0(n4852), .B1(
data_output[31]), .Y(n2026) );
AO22XLTS U6280 ( .A0(n4846), .A1(sign_inv_out[32]), .B0(n4848), .B1(
data_output[32]), .Y(n2024) );
AO22XLTS U6281 ( .A0(n4847), .A1(sign_inv_out[33]), .B0(n4848), .B1(
data_output[33]), .Y(n2022) );
BUFX3TS U6282 ( .A(n4845), .Y(n4850) );
AO22XLTS U6283 ( .A0(n4846), .A1(sign_inv_out[34]), .B0(n4850), .B1(
data_output[34]), .Y(n2020) );
AO22XLTS U6284 ( .A0(n4847), .A1(sign_inv_out[35]), .B0(n4849), .B1(
data_output[35]), .Y(n2018) );
AO22XLTS U6285 ( .A0(n4853), .A1(sign_inv_out[36]), .B0(n4852), .B1(
data_output[36]), .Y(n2016) );
AO22XLTS U6286 ( .A0(n4853), .A1(sign_inv_out[37]), .B0(n4848), .B1(
data_output[37]), .Y(n2014) );
AO22XLTS U6287 ( .A0(n4853), .A1(sign_inv_out[38]), .B0(n4852), .B1(
data_output[38]), .Y(n2012) );
AO22XLTS U6288 ( .A0(n4853), .A1(sign_inv_out[39]), .B0(n4850), .B1(
data_output[39]), .Y(n2010) );
AO22XLTS U6289 ( .A0(n4853), .A1(sign_inv_out[40]), .B0(n4849), .B1(
data_output[40]), .Y(n2008) );
AO22XLTS U6290 ( .A0(n4853), .A1(sign_inv_out[41]), .B0(n4848), .B1(
data_output[41]), .Y(n2006) );
AO22XLTS U6291 ( .A0(n4853), .A1(sign_inv_out[42]), .B0(n4848), .B1(
data_output[42]), .Y(n2004) );
AO22XLTS U6292 ( .A0(n4853), .A1(sign_inv_out[43]), .B0(n4850), .B1(
data_output[43]), .Y(n2002) );
AO22XLTS U6293 ( .A0(n4853), .A1(sign_inv_out[44]), .B0(n4849), .B1(
data_output[44]), .Y(n2000) );
AO22XLTS U6294 ( .A0(n4853), .A1(sign_inv_out[45]), .B0(n4850), .B1(
data_output[45]), .Y(n1998) );
AO22XLTS U6295 ( .A0(n4853), .A1(sign_inv_out[46]), .B0(n4850), .B1(
data_output[46]), .Y(n1996) );
AO22XLTS U6296 ( .A0(n4853), .A1(sign_inv_out[47]), .B0(n4850), .B1(
data_output[47]), .Y(n1994) );
AO22XLTS U6297 ( .A0(n4851), .A1(sign_inv_out[48]), .B0(n4850), .B1(
data_output[48]), .Y(n1992) );
AO22XLTS U6298 ( .A0(n4851), .A1(sign_inv_out[49]), .B0(n4850), .B1(
data_output[49]), .Y(n1990) );
AO22XLTS U6299 ( .A0(n4851), .A1(sign_inv_out[50]), .B0(n4850), .B1(
data_output[50]), .Y(n1988) );
AO22XLTS U6300 ( .A0(n4851), .A1(sign_inv_out[51]), .B0(n4850), .B1(
data_output[51]), .Y(n1986) );
AO22XLTS U6301 ( .A0(n4851), .A1(sign_inv_out[52]), .B0(n4850), .B1(
data_output[52]), .Y(n1984) );
AO22XLTS U6302 ( .A0(n4851), .A1(sign_inv_out[53]), .B0(n4850), .B1(
data_output[53]), .Y(n1982) );
AO22XLTS U6303 ( .A0(n4851), .A1(sign_inv_out[54]), .B0(n4850), .B1(
data_output[54]), .Y(n1980) );
AO22XLTS U6304 ( .A0(n4851), .A1(sign_inv_out[55]), .B0(n4850), .B1(
data_output[55]), .Y(n1978) );
AO22XLTS U6305 ( .A0(n4851), .A1(sign_inv_out[56]), .B0(n4852), .B1(
data_output[56]), .Y(n1976) );
AO22XLTS U6306 ( .A0(n4851), .A1(sign_inv_out[57]), .B0(n4852), .B1(
data_output[57]), .Y(n1974) );
AO22XLTS U6307 ( .A0(n4851), .A1(sign_inv_out[58]), .B0(n4852), .B1(
data_output[58]), .Y(n1972) );
AO22XLTS U6308 ( .A0(n4851), .A1(sign_inv_out[59]), .B0(n4852), .B1(
data_output[59]), .Y(n1970) );
AO22XLTS U6309 ( .A0(n4853), .A1(sign_inv_out[60]), .B0(n4852), .B1(
data_output[60]), .Y(n1968) );
AO22XLTS U6310 ( .A0(n4851), .A1(sign_inv_out[61]), .B0(n4852), .B1(
data_output[61]), .Y(n1966) );
AO22XLTS U6311 ( .A0(n4853), .A1(sign_inv_out[62]), .B0(n4852), .B1(
data_output[62]), .Y(n1964) );
AOI22X1TS U6312 ( .A0(d_ff3_LUT_out[0]), .A1(n4953), .B0(n5033), .B1(
d_ff3_sh_y_out[0]), .Y(n4855) );
AOI22X1TS U6313 ( .A0(add_subt_module_intDY[0]), .A1(n2974), .B0(n4931),
.B1(d_ff3_sh_x_out[0]), .Y(n4854) );
NAND2X1TS U6314 ( .A(n4855), .B(n4854), .Y(n1958) );
AOI22X1TS U6315 ( .A0(add_subt_module_intDY[56]), .A1(n5011), .B0(n4886),
.B1(d_ff3_sh_y_out[56]), .Y(n4857) );
AOI22X1TS U6316 ( .A0(n4931), .A1(d_ff3_sh_x_out[56]), .B0(n4913), .B1(
d_ff3_LUT_out[56]), .Y(n4856) );
NAND2X1TS U6317 ( .A(n4857), .B(n4856), .Y(n1951) );
AOI22X1TS U6318 ( .A0(d_ff3_LUT_out[55]), .A1(n4965), .B0(n5001), .B1(
d_ff3_sh_y_out[55]), .Y(n4859) );
AOI22X1TS U6319 ( .A0(add_subt_module_intDY[55]), .A1(n5011), .B0(n4971),
.B1(d_ff3_sh_x_out[55]), .Y(n4858) );
NAND2X1TS U6320 ( .A(n4859), .B(n4858), .Y(n1950) );
AOI22X1TS U6321 ( .A0(d_ff3_LUT_out[54]), .A1(n4965), .B0(n4886), .B1(
d_ff3_sh_y_out[54]), .Y(n4861) );
AOI22X1TS U6322 ( .A0(add_subt_module_intDY[54]), .A1(n4893), .B0(n4971),
.B1(d_ff3_sh_x_out[54]), .Y(n4860) );
NAND2X1TS U6323 ( .A(n4861), .B(n4860), .Y(n1949) );
AOI22X1TS U6324 ( .A0(n4953), .A1(d_ff3_LUT_out[53]), .B0(n4908), .B1(
d_ff3_sh_y_out[53]), .Y(n4863) );
AOI22X1TS U6325 ( .A0(add_subt_module_intDY[53]), .A1(n4893), .B0(n5042),
.B1(d_ff3_sh_x_out[53]), .Y(n4862) );
NAND2X1TS U6326 ( .A(n4863), .B(n4862), .Y(n1948) );
AOI22X1TS U6327 ( .A0(n5030), .A1(d_ff3_LUT_out[52]), .B0(n5033), .B1(
d_ff3_sh_y_out[52]), .Y(n4865) );
AOI22X1TS U6328 ( .A0(add_subt_module_intDY[52]), .A1(n4893), .B0(n4954),
.B1(d_ff3_sh_x_out[52]), .Y(n4864) );
NAND2X1TS U6329 ( .A(n4865), .B(n4864), .Y(n1947) );
AOI22X1TS U6330 ( .A0(d_ff2_X[62]), .A1(n4948), .B0(d_ff2_Y[62]), .B1(n4931),
.Y(n4867) );
AOI22X1TS U6331 ( .A0(add_subt_module_intDX[62]), .A1(n5040), .B0(
d_ff2_Z[62]), .B1(n5041), .Y(n4866) );
NAND2X1TS U6332 ( .A(n4867), .B(n4866), .Y(n1942) );
AOI22X1TS U6333 ( .A0(d_ff2_X[61]), .A1(n4948), .B0(d_ff2_Z[61]), .B1(n5014),
.Y(n4869) );
AOI22X1TS U6334 ( .A0(add_subt_module_intDX[61]), .A1(n5040), .B0(
d_ff2_Y[61]), .B1(n4971), .Y(n4868) );
NAND2X1TS U6335 ( .A(n4869), .B(n4868), .Y(n1939) );
AOI22X1TS U6336 ( .A0(d_ff2_X[60]), .A1(n4970), .B0(d_ff2_Z[60]), .B1(n4913),
.Y(n4871) );
AOI22X1TS U6337 ( .A0(add_subt_module_intDX[60]), .A1(n2973), .B0(
d_ff2_Y[60]), .B1(n4954), .Y(n4870) );
NAND2X1TS U6338 ( .A(n4871), .B(n4870), .Y(n1936) );
AOI22X1TS U6339 ( .A0(d_ff2_X[59]), .A1(n4908), .B0(d_ff2_Z[59]), .B1(n5041),
.Y(n4873) );
AOI22X1TS U6340 ( .A0(add_subt_module_intDX[59]), .A1(n5040), .B0(
d_ff2_Y[59]), .B1(n5035), .Y(n4872) );
NAND2X1TS U6341 ( .A(n4873), .B(n4872), .Y(n1933) );
AOI22X1TS U6342 ( .A0(d_ff2_X[58]), .A1(n4970), .B0(d_ff2_Z[58]), .B1(n5041),
.Y(n4875) );
AOI22X1TS U6343 ( .A0(add_subt_module_intDX[58]), .A1(n5036), .B0(
d_ff2_Y[58]), .B1(n5042), .Y(n4874) );
NAND2X1TS U6344 ( .A(n4875), .B(n4874), .Y(n1930) );
AOI22X1TS U6345 ( .A0(d_ff2_X[57]), .A1(n5001), .B0(d_ff2_Z[57]), .B1(n5014),
.Y(n4877) );
AOI22X1TS U6346 ( .A0(add_subt_module_intDX[57]), .A1(n4893), .B0(
d_ff2_Y[57]), .B1(n5027), .Y(n4876) );
NAND2X1TS U6347 ( .A(n4877), .B(n4876), .Y(n1927) );
AOI22X1TS U6348 ( .A0(add_subt_module_intDX[56]), .A1(n5040), .B0(
d_ff2_X[56]), .B1(n5039), .Y(n4879) );
AOI22X1TS U6349 ( .A0(d_ff2_Y[56]), .A1(n4971), .B0(d_ff2_Z[56]), .B1(n5014),
.Y(n4878) );
NAND2X1TS U6350 ( .A(n4879), .B(n4878), .Y(n1924) );
AOI22X1TS U6351 ( .A0(d_ff2_Z[55]), .A1(n5030), .B0(n4970), .B1(d_ff2_X[55]),
.Y(n4881) );
AOI22X1TS U6352 ( .A0(add_subt_module_intDX[55]), .A1(n2973), .B0(n4931),
.B1(d_ff2_Y[55]), .Y(n4880) );
NAND2X1TS U6353 ( .A(n4881), .B(n4880), .Y(n1921) );
AOI22X1TS U6354 ( .A0(n4965), .A1(d_ff2_Z[54]), .B0(n5001), .B1(d_ff2_X[54]),
.Y(n4883) );
AOI22X1TS U6355 ( .A0(add_subt_module_intDX[54]), .A1(n5036), .B0(n4954),
.B1(d_ff2_Y[54]), .Y(n4882) );
NAND2X1TS U6356 ( .A(n4883), .B(n4882), .Y(n1918) );
AOI22X1TS U6357 ( .A0(d_ff2_Z[0]), .A1(n4965), .B0(n5033), .B1(d_ff2_X[0]),
.Y(n4885) );
AOI22X1TS U6358 ( .A0(add_subt_module_intDX[0]), .A1(n5040), .B0(n4971),
.B1(d_ff2_Y[0]), .Y(n4884) );
NAND2X1TS U6359 ( .A(n4885), .B(n4884), .Y(n1909) );
AOI22X1TS U6360 ( .A0(d_ff2_Z[51]), .A1(n4965), .B0(n4886), .B1(d_ff2_X[51]),
.Y(n4888) );
AOI22X1TS U6361 ( .A0(add_subt_module_intDX[51]), .A1(n5040), .B0(n4971),
.B1(d_ff2_Y[51]), .Y(n4887) );
NAND2X1TS U6362 ( .A(n4888), .B(n4887), .Y(n1907) );
AOI22X1TS U6363 ( .A0(n4965), .A1(d_ff2_Z[4]), .B0(n4908), .B1(d_ff2_X[4]),
.Y(n4890) );
AOI22X1TS U6364 ( .A0(add_subt_module_intDX[4]), .A1(n5040), .B0(n4931),
.B1(d_ff2_Y[4]), .Y(n4889) );
NAND2X1TS U6365 ( .A(n4890), .B(n4889), .Y(n1904) );
AOI22X1TS U6366 ( .A0(add_subt_module_intDY[4]), .A1(n5036), .B0(n2977),
.B1(d_ff3_sh_y_out[4]), .Y(n4892) );
AOI22X1TS U6367 ( .A0(d_ff3_LUT_out[4]), .A1(n4965), .B0(n5042), .B1(
d_ff3_sh_x_out[4]), .Y(n4891) );
NAND2X1TS U6368 ( .A(n4892), .B(n4891), .Y(n1903) );
AOI22X1TS U6369 ( .A0(n5035), .A1(d_ff3_sh_x_out[2]), .B0(n5001), .B1(
d_ff3_sh_y_out[2]), .Y(n4895) );
AOI22X1TS U6370 ( .A0(add_subt_module_intDY[2]), .A1(n5036), .B0(n4913),
.B1(d_ff3_LUT_out[2]), .Y(n4894) );
NAND2X1TS U6371 ( .A(n4895), .B(n4894), .Y(n1896) );
AOI22X1TS U6372 ( .A0(add_subt_module_intDY[47]), .A1(n5040), .B0(n5033),
.B1(d_ff3_sh_y_out[47]), .Y(n4897) );
AOI22X1TS U6373 ( .A0(n5035), .A1(d_ff3_sh_x_out[47]), .B0(n4913), .B1(
d_ff3_LUT_out[47]), .Y(n4896) );
NAND2X1TS U6374 ( .A(n4897), .B(n4896), .Y(n1890) );
AOI22X1TS U6375 ( .A0(add_subt_module_intDX[3]), .A1(n4893), .B0(n5001),
.B1(d_ff2_X[3]), .Y(n4899) );
AOI22X1TS U6376 ( .A0(n4965), .A1(d_ff2_Z[3]), .B0(n4992), .B1(d_ff2_Y[3]),
.Y(n4898) );
NAND2X1TS U6377 ( .A(n4899), .B(n4898), .Y(n1887) );
AOI22X1TS U6378 ( .A0(n5006), .A1(d_ff3_LUT_out[3]), .B0(n4886), .B1(
d_ff3_sh_y_out[3]), .Y(n4901) );
AOI22X1TS U6379 ( .A0(add_subt_module_intDY[3]), .A1(n4922), .B0(n5027),
.B1(d_ff3_sh_x_out[3]), .Y(n4900) );
NAND2X1TS U6380 ( .A(n4901), .B(n4900), .Y(n1886) );
AOI22X1TS U6381 ( .A0(add_subt_module_intDY[1]), .A1(n4893), .B0(n4908),
.B1(d_ff3_sh_y_out[1]), .Y(n4903) );
AOI22X1TS U6382 ( .A0(d_ff3_LUT_out[1]), .A1(n4965), .B0(n4992), .B1(
d_ff3_sh_x_out[1]), .Y(n4902) );
NAND2X1TS U6383 ( .A(n4903), .B(n4902), .Y(n1883) );
AOI22X1TS U6384 ( .A0(d_ff2_Z[49]), .A1(n4953), .B0(n4908), .B1(d_ff2_X[49]),
.Y(n4905) );
AOI22X1TS U6385 ( .A0(add_subt_module_intDX[49]), .A1(n4922), .B0(n4971),
.B1(d_ff2_Y[49]), .Y(n4904) );
NAND2X1TS U6386 ( .A(n4905), .B(n4904), .Y(n1881) );
AOI22X1TS U6387 ( .A0(n4971), .A1(d_ff3_sh_x_out[49]), .B0(n5033), .B1(
d_ff3_sh_y_out[49]), .Y(n4907) );
AOI22X1TS U6388 ( .A0(add_subt_module_intDY[49]), .A1(n5011), .B0(n5041),
.B1(d_ff3_LUT_out[49]), .Y(n4906) );
NAND2X1TS U6389 ( .A(n4907), .B(n4906), .Y(n1880) );
AOI22X1TS U6390 ( .A0(n4971), .A1(d_ff3_sh_x_out[46]), .B0(n4970), .B1(
d_ff3_sh_y_out[46]), .Y(n4910) );
AOI22X1TS U6391 ( .A0(add_subt_module_intDY[46]), .A1(n5036), .B0(n5014),
.B1(d_ff3_LUT_out[46]), .Y(n4909) );
NAND2X1TS U6392 ( .A(n4910), .B(n4909), .Y(n1876) );
AOI22X1TS U6393 ( .A0(add_subt_module_intDY[16]), .A1(n5011), .B0(n4886),
.B1(d_ff3_sh_y_out[16]), .Y(n4912) );
AOI22X1TS U6394 ( .A0(n4931), .A1(d_ff3_sh_x_out[16]), .B0(n4913), .B1(
d_ff3_LUT_out[16]), .Y(n4911) );
NAND2X1TS U6395 ( .A(n4912), .B(n4911), .Y(n1872) );
AOI22X1TS U6396 ( .A0(n5027), .A1(d_ff3_sh_x_out[9]), .B0(n2977), .B1(
d_ff3_sh_y_out[9]), .Y(n4915) );
AOI22X1TS U6397 ( .A0(add_subt_module_intDY[9]), .A1(n5036), .B0(
d_ff3_LUT_out[9]), .B1(n5014), .Y(n4914) );
NAND2X1TS U6398 ( .A(n4915), .B(n4914), .Y(n1869) );
AOI22X1TS U6399 ( .A0(add_subt_module_intDX[44]), .A1(n5040), .B0(n4970),
.B1(d_ff2_X[44]), .Y(n4917) );
AOI22X1TS U6400 ( .A0(n4965), .A1(d_ff2_Z[44]), .B0(n4992), .B1(d_ff2_Y[44]),
.Y(n4916) );
NAND2X1TS U6401 ( .A(n4917), .B(n4916), .Y(n1867) );
AOI22X1TS U6402 ( .A0(add_subt_module_intDY[44]), .A1(n5011), .B0(n4948),
.B1(d_ff3_sh_y_out[44]), .Y(n4919) );
AOI22X1TS U6403 ( .A0(n4954), .A1(d_ff3_sh_x_out[44]), .B0(n5041), .B1(
d_ff3_LUT_out[44]), .Y(n4918) );
NAND2X1TS U6404 ( .A(n4919), .B(n4918), .Y(n1866) );
AOI22X1TS U6405 ( .A0(n4953), .A1(d_ff2_Z[6]), .B0(n4948), .B1(d_ff2_X[6]),
.Y(n4921) );
AOI22X1TS U6406 ( .A0(add_subt_module_intDX[6]), .A1(n5040), .B0(n5027),
.B1(d_ff2_Y[6]), .Y(n4920) );
NAND2X1TS U6407 ( .A(n4921), .B(n4920), .Y(n1863) );
AOI22X1TS U6408 ( .A0(n4965), .A1(d_ff3_LUT_out[6]), .B0(n4970), .B1(
d_ff3_sh_y_out[6]), .Y(n4924) );
AOI22X1TS U6409 ( .A0(add_subt_module_intDY[6]), .A1(n5011), .B0(n5035),
.B1(d_ff3_sh_x_out[6]), .Y(n4923) );
NAND2X1TS U6410 ( .A(n4924), .B(n4923), .Y(n1862) );
AOI22X1TS U6411 ( .A0(d_ff2_Z[5]), .A1(n4953), .B0(n4908), .B1(d_ff2_X[5]),
.Y(n4926) );
AOI22X1TS U6412 ( .A0(add_subt_module_intDX[5]), .A1(n4893), .B0(n4971),
.B1(d_ff2_Y[5]), .Y(n4925) );
NAND2X1TS U6413 ( .A(n4926), .B(n4925), .Y(n1860) );
AOI22X1TS U6414 ( .A0(add_subt_module_intDY[5]), .A1(n4922), .B0(n5001),
.B1(d_ff3_sh_y_out[5]), .Y(n4928) );
AOI22X1TS U6415 ( .A0(d_ff3_LUT_out[5]), .A1(n5030), .B0(n4971), .B1(
d_ff3_sh_x_out[5]), .Y(n4927) );
NAND2X1TS U6416 ( .A(n4928), .B(n4927), .Y(n1859) );
AOI22X1TS U6417 ( .A0(add_subt_module_intDX[45]), .A1(n5011), .B0(n5033),
.B1(d_ff2_X[45]), .Y(n4930) );
AOI22X1TS U6418 ( .A0(d_ff2_Z[45]), .A1(n4953), .B0(n4931), .B1(d_ff2_Y[45]),
.Y(n4929) );
NAND2X1TS U6419 ( .A(n4930), .B(n4929), .Y(n1857) );
AOI22X1TS U6420 ( .A0(add_subt_module_intDY[45]), .A1(n4922), .B0(n5001),
.B1(d_ff3_sh_y_out[45]), .Y(n4933) );
AOI22X1TS U6421 ( .A0(n4971), .A1(d_ff3_sh_x_out[45]), .B0(n5014), .B1(
d_ff3_LUT_out[45]), .Y(n4932) );
NAND2X1TS U6422 ( .A(n4933), .B(n4932), .Y(n1856) );
AOI22X1TS U6423 ( .A0(d_ff2_Z[20]), .A1(n4953), .B0(n4970), .B1(d_ff2_X[20]),
.Y(n4935) );
AOI22X1TS U6424 ( .A0(add_subt_module_intDX[20]), .A1(n2973), .B0(n4954),
.B1(d_ff2_Y[20]), .Y(n4934) );
NAND2X1TS U6425 ( .A(n4935), .B(n4934), .Y(n1853) );
AOI22X1TS U6426 ( .A0(d_ff2_Z[13]), .A1(n4953), .B0(n5033), .B1(d_ff2_X[13]),
.Y(n4937) );
AOI22X1TS U6427 ( .A0(add_subt_module_intDX[13]), .A1(n4922), .B0(n5042),
.B1(d_ff2_Y[13]), .Y(n4936) );
NAND2X1TS U6428 ( .A(n4937), .B(n4936), .Y(n1850) );
AOI22X1TS U6429 ( .A0(n4965), .A1(d_ff3_LUT_out[13]), .B0(n5033), .B1(
d_ff3_sh_y_out[13]), .Y(n4939) );
AOI22X1TS U6430 ( .A0(add_subt_module_intDY[13]), .A1(n4893), .B0(n4992),
.B1(d_ff3_sh_x_out[13]), .Y(n4938) );
NAND2X1TS U6431 ( .A(n4939), .B(n4938), .Y(n1849) );
AOI22X1TS U6432 ( .A0(add_subt_module_intDX[10]), .A1(n5036), .B0(n4908),
.B1(d_ff2_X[10]), .Y(n4941) );
AOI22X1TS U6433 ( .A0(n4953), .A1(d_ff2_Z[10]), .B0(n5042), .B1(d_ff2_Y[10]),
.Y(n4940) );
NAND2X1TS U6434 ( .A(n4941), .B(n4940), .Y(n1847) );
AOI22X1TS U6435 ( .A0(n5035), .A1(d_ff3_sh_x_out[10]), .B0(n4948), .B1(
d_ff3_sh_y_out[10]), .Y(n4943) );
AOI22X1TS U6436 ( .A0(add_subt_module_intDY[10]), .A1(n2973), .B0(n4913),
.B1(d_ff3_LUT_out[10]), .Y(n4942) );
NAND2X1TS U6437 ( .A(n4943), .B(n4942), .Y(n1846) );
AOI22X1TS U6438 ( .A0(d_ff2_Z[43]), .A1(n4953), .B0(n5033), .B1(d_ff2_X[43]),
.Y(n4945) );
AOI22X1TS U6439 ( .A0(add_subt_module_intDX[43]), .A1(n5036), .B0(n4931),
.B1(d_ff2_Y[43]), .Y(n4944) );
NAND2X1TS U6440 ( .A(n4945), .B(n4944), .Y(n1844) );
AOI22X1TS U6441 ( .A0(d_ff3_LUT_out[43]), .A1(n4953), .B0(n4948), .B1(
d_ff3_sh_y_out[43]), .Y(n4947) );
AOI22X1TS U6442 ( .A0(add_subt_module_intDY[43]), .A1(n3046), .B0(n5035),
.B1(d_ff3_sh_x_out[43]), .Y(n4946) );
NAND2X1TS U6443 ( .A(n4947), .B(n4946), .Y(n1843) );
AOI22X1TS U6444 ( .A0(d_ff2_Z[7]), .A1(n4953), .B0(n4886), .B1(d_ff2_X[7]),
.Y(n4950) );
AOI22X1TS U6445 ( .A0(add_subt_module_intDX[7]), .A1(n2974), .B0(n4992),
.B1(d_ff2_Y[7]), .Y(n4949) );
NAND2X1TS U6446 ( .A(n4950), .B(n4949), .Y(n1840) );
AOI22X1TS U6447 ( .A0(add_subt_module_intDY[7]), .A1(n5036), .B0(n4948),
.B1(d_ff3_sh_y_out[7]), .Y(n4952) );
AOI22X1TS U6448 ( .A0(d_ff3_LUT_out[7]), .A1(n4953), .B0(n5042), .B1(
d_ff3_sh_x_out[7]), .Y(n4951) );
NAND2X1TS U6449 ( .A(n4952), .B(n4951), .Y(n1839) );
AOI22X1TS U6450 ( .A0(d_ff2_Z[40]), .A1(n4953), .B0(n4886), .B1(d_ff2_X[40]),
.Y(n4956) );
AOI22X1TS U6451 ( .A0(add_subt_module_intDX[40]), .A1(n4893), .B0(n5027),
.B1(d_ff2_Y[40]), .Y(n4955) );
NAND2X1TS U6452 ( .A(n4956), .B(n4955), .Y(n1837) );
AOI22X1TS U6453 ( .A0(add_subt_module_intDX[38]), .A1(n5040), .B0(n4970),
.B1(d_ff2_X[38]), .Y(n4958) );
AOI22X1TS U6454 ( .A0(d_ff2_Z[38]), .A1(n5030), .B0(n5035), .B1(d_ff2_Y[38]),
.Y(n4957) );
NAND2X1TS U6455 ( .A(n4958), .B(n4957), .Y(n1833) );
AOI22X1TS U6456 ( .A0(d_ff2_Z[12]), .A1(n5030), .B0(n2977), .B1(d_ff2_X[12]),
.Y(n4960) );
AOI22X1TS U6457 ( .A0(add_subt_module_intDX[12]), .A1(n2973), .B0(n5027),
.B1(d_ff2_Y[12]), .Y(n4959) );
NAND2X1TS U6458 ( .A(n4960), .B(n4959), .Y(n1829) );
AOI22X1TS U6459 ( .A0(n4931), .A1(d_ff3_sh_x_out[12]), .B0(n5001), .B1(
d_ff3_sh_y_out[12]), .Y(n4962) );
AOI22X1TS U6460 ( .A0(add_subt_module_intDY[12]), .A1(n5011), .B0(
d_ff3_LUT_out[12]), .B1(n5041), .Y(n4961) );
NAND2X1TS U6461 ( .A(n4962), .B(n4961), .Y(n1828) );
AOI22X1TS U6462 ( .A0(d_ff2_Z[41]), .A1(n5030), .B0(n4908), .B1(d_ff2_X[41]),
.Y(n4964) );
AOI22X1TS U6463 ( .A0(add_subt_module_intDX[41]), .A1(n5011), .B0(n4992),
.B1(d_ff2_Y[41]), .Y(n4963) );
NAND2X1TS U6464 ( .A(n4964), .B(n4963), .Y(n1816) );
AOI22X1TS U6465 ( .A0(n4965), .A1(d_ff3_LUT_out[41]), .B0(n5033), .B1(
d_ff3_sh_y_out[41]), .Y(n4967) );
AOI22X1TS U6466 ( .A0(add_subt_module_intDY[41]), .A1(n3046), .B0(n4931),
.B1(d_ff3_sh_x_out[41]), .Y(n4966) );
NAND2X1TS U6467 ( .A(n4967), .B(n4966), .Y(n1815) );
AOI22X1TS U6468 ( .A0(d_ff2_Z[37]), .A1(n5030), .B0(n5033), .B1(d_ff2_X[37]),
.Y(n4969) );
AOI22X1TS U6469 ( .A0(add_subt_module_intDX[37]), .A1(n5036), .B0(n4954),
.B1(d_ff2_Y[37]), .Y(n4968) );
NAND2X1TS U6470 ( .A(n4969), .B(n4968), .Y(n1809) );
AOI22X1TS U6471 ( .A0(add_subt_module_intDY[37]), .A1(n4922), .B0(n2977),
.B1(d_ff3_sh_y_out[37]), .Y(n4973) );
AOI22X1TS U6472 ( .A0(n4992), .A1(d_ff3_sh_x_out[37]), .B0(n5014), .B1(
d_ff3_LUT_out[37]), .Y(n4972) );
NAND2X1TS U6473 ( .A(n4973), .B(n4972), .Y(n1808) );
AOI22X1TS U6474 ( .A0(d_ff2_Z[19]), .A1(n5030), .B0(n4970), .B1(d_ff2_X[19]),
.Y(n4975) );
AOI22X1TS U6475 ( .A0(add_subt_module_intDX[19]), .A1(n5011), .B0(n5027),
.B1(d_ff2_Y[19]), .Y(n4974) );
NAND2X1TS U6476 ( .A(n4975), .B(n4974), .Y(n1804) );
AOI22X1TS U6477 ( .A0(add_subt_module_intDY[19]), .A1(n4922), .B0(n5033),
.B1(d_ff3_sh_y_out[19]), .Y(n4977) );
AOI22X1TS U6478 ( .A0(n5027), .A1(d_ff3_sh_x_out[19]), .B0(n4913), .B1(
d_ff3_LUT_out[19]), .Y(n4976) );
NAND2X1TS U6479 ( .A(n4977), .B(n4976), .Y(n1803) );
AOI22X1TS U6480 ( .A0(d_ff2_Z[34]), .A1(n5034), .B0(n4948), .B1(d_ff2_X[34]),
.Y(n4979) );
AOI22X1TS U6481 ( .A0(add_subt_module_intDX[34]), .A1(n5011), .B0(n4971),
.B1(d_ff2_Y[34]), .Y(n4978) );
NAND2X1TS U6482 ( .A(n4979), .B(n4978), .Y(n1801) );
AOI22X1TS U6483 ( .A0(d_ff2_Z[23]), .A1(n5014), .B0(n4970), .B1(d_ff2_X[23]),
.Y(n4981) );
AOI22X1TS U6484 ( .A0(add_subt_module_intDX[23]), .A1(n4893), .B0(n5042),
.B1(d_ff2_Y[23]), .Y(n4980) );
NAND2X1TS U6485 ( .A(n4981), .B(n4980), .Y(n1798) );
AOI22X1TS U6486 ( .A0(d_ff3_LUT_out[23]), .A1(n5030), .B0(n4970), .B1(
d_ff3_sh_y_out[23]), .Y(n4983) );
AOI22X1TS U6487 ( .A0(add_subt_module_intDY[23]), .A1(n4922), .B0(n5035),
.B1(d_ff3_sh_x_out[23]), .Y(n4982) );
NAND2X1TS U6488 ( .A(n4983), .B(n4982), .Y(n1797) );
AOI22X1TS U6489 ( .A0(d_ff2_Z[30]), .A1(n4913), .B0(n4948), .B1(d_ff2_X[30]),
.Y(n4985) );
AOI22X1TS U6490 ( .A0(add_subt_module_intDX[30]), .A1(n2973), .B0(n5035),
.B1(d_ff2_Y[30]), .Y(n4984) );
NAND2X1TS U6491 ( .A(n4985), .B(n4984), .Y(n1795) );
AOI22X1TS U6492 ( .A0(add_subt_module_intDY[35]), .A1(n2974), .B0(n5001),
.B1(d_ff3_sh_y_out[35]), .Y(n4987) );
AOI22X1TS U6493 ( .A0(d_ff3_LUT_out[35]), .A1(n5014), .B0(n4931), .B1(
d_ff3_sh_x_out[35]), .Y(n4986) );
NAND2X1TS U6494 ( .A(n4987), .B(n4986), .Y(n1791) );
AOI22X1TS U6495 ( .A0(d_ff2_Z[15]), .A1(n5034), .B0(n5001), .B1(d_ff2_X[15]),
.Y(n4989) );
AOI22X1TS U6496 ( .A0(add_subt_module_intDX[15]), .A1(n4922), .B0(n4954),
.B1(d_ff2_Y[15]), .Y(n4988) );
NAND2X1TS U6497 ( .A(n4989), .B(n4988), .Y(n1788) );
AOI22X1TS U6498 ( .A0(d_ff3_LUT_out[15]), .A1(n5034), .B0(n4948), .B1(
d_ff3_sh_y_out[15]), .Y(n4991) );
AOI22X1TS U6499 ( .A0(add_subt_module_intDY[15]), .A1(n5036), .B0(n5035),
.B1(d_ff3_sh_x_out[15]), .Y(n4990) );
NAND2X1TS U6500 ( .A(n4991), .B(n4990), .Y(n1787) );
AOI22X1TS U6501 ( .A0(d_ff2_Z[36]), .A1(n5034), .B0(n2977), .B1(d_ff2_X[36]),
.Y(n4994) );
AOI22X1TS U6502 ( .A0(add_subt_module_intDX[36]), .A1(n4893), .B0(n5035),
.B1(d_ff2_Y[36]), .Y(n4993) );
NAND2X1TS U6503 ( .A(n4994), .B(n4993), .Y(n1785) );
AOI22X1TS U6504 ( .A0(add_subt_module_intDX[14]), .A1(n2974), .B0(n4970),
.B1(d_ff2_X[14]), .Y(n4996) );
AOI22X1TS U6505 ( .A0(d_ff2_Z[14]), .A1(n5034), .B0(n4931), .B1(d_ff2_Y[14]),
.Y(n4995) );
NAND2X1TS U6506 ( .A(n4996), .B(n4995), .Y(n1781) );
AOI22X1TS U6507 ( .A0(d_ff2_Z[27]), .A1(n5034), .B0(n5001), .B1(d_ff2_X[27]),
.Y(n4998) );
AOI22X1TS U6508 ( .A0(add_subt_module_intDX[27]), .A1(n4893), .B0(n4971),
.B1(d_ff2_Y[27]), .Y(n4997) );
NAND2X1TS U6509 ( .A(n4998), .B(n4997), .Y(n1778) );
AOI22X1TS U6510 ( .A0(add_subt_module_intDX[31]), .A1(n4893), .B0(n4886),
.B1(d_ff2_X[31]), .Y(n5000) );
AOI22X1TS U6511 ( .A0(d_ff2_Z[31]), .A1(n5034), .B0(n5035), .B1(d_ff2_Y[31]),
.Y(n4999) );
NAND2X1TS U6512 ( .A(n5000), .B(n4999), .Y(n1774) );
AOI22X1TS U6513 ( .A0(n5006), .A1(d_ff3_LUT_out[31]), .B0(n4948), .B1(
d_ff3_sh_y_out[31]), .Y(n5003) );
AOI22X1TS U6514 ( .A0(add_subt_module_intDY[31]), .A1(n2973), .B0(n4992),
.B1(d_ff3_sh_x_out[31]), .Y(n5002) );
NAND2X1TS U6515 ( .A(n5003), .B(n5002), .Y(n1773) );
AOI22X1TS U6516 ( .A0(add_subt_module_intDX[29]), .A1(n5036), .B0(n4908),
.B1(d_ff2_X[29]), .Y(n5005) );
AOI22X1TS U6517 ( .A0(d_ff2_Z[29]), .A1(n5034), .B0(n4992), .B1(d_ff2_Y[29]),
.Y(n5004) );
NAND2X1TS U6518 ( .A(n5005), .B(n5004), .Y(n1770) );
AOI22X1TS U6519 ( .A0(n5006), .A1(d_ff3_LUT_out[29]), .B0(n5001), .B1(
d_ff3_sh_y_out[29]), .Y(n5008) );
AOI22X1TS U6520 ( .A0(add_subt_module_intDY[29]), .A1(n5036), .B0(n5027),
.B1(d_ff3_sh_x_out[29]), .Y(n5007) );
NAND2X1TS U6521 ( .A(n5008), .B(n5007), .Y(n1769) );
AOI22X1TS U6522 ( .A0(d_ff2_Z[21]), .A1(n5034), .B0(n4908), .B1(d_ff2_X[21]),
.Y(n5010) );
AOI22X1TS U6523 ( .A0(add_subt_module_intDX[21]), .A1(n4922), .B0(n4954),
.B1(d_ff2_Y[21]), .Y(n5009) );
NAND2X1TS U6524 ( .A(n5010), .B(n5009), .Y(n1766) );
AOI22X1TS U6525 ( .A0(n5030), .A1(d_ff3_LUT_out[21]), .B0(n2977), .B1(
d_ff3_sh_y_out[21]), .Y(n5013) );
AOI22X1TS U6526 ( .A0(add_subt_module_intDY[21]), .A1(n5011), .B0(n4971),
.B1(d_ff3_sh_x_out[21]), .Y(n5012) );
NAND2X1TS U6527 ( .A(n5013), .B(n5012), .Y(n1765) );
AOI22X1TS U6528 ( .A0(n5042), .A1(d_ff3_sh_x_out[18]), .B0(n2977), .B1(
d_ff3_sh_y_out[18]), .Y(n5016) );
AOI22X1TS U6529 ( .A0(add_subt_module_intDY[18]), .A1(n2973), .B0(
d_ff3_LUT_out[18]), .B1(n5014), .Y(n5015) );
NAND2X1TS U6530 ( .A(n5016), .B(n5015), .Y(n1762) );
AOI22X1TS U6531 ( .A0(add_subt_module_intDX[25]), .A1(n4893), .B0(n4908),
.B1(d_ff2_X[25]), .Y(n5018) );
AOI22X1TS U6532 ( .A0(d_ff2_Z[25]), .A1(n5034), .B0(n4971), .B1(d_ff2_Y[25]),
.Y(n5017) );
NAND2X1TS U6533 ( .A(n5018), .B(n5017), .Y(n1760) );
AOI22X1TS U6534 ( .A0(n5034), .A1(d_ff2_Z[33]), .B0(n2977), .B1(d_ff2_X[33]),
.Y(n5020) );
AOI22X1TS U6535 ( .A0(add_subt_module_intDX[33]), .A1(n5040), .B0(n5042),
.B1(d_ff2_Y[33]), .Y(n5019) );
NAND2X1TS U6536 ( .A(n5020), .B(n5019), .Y(n1756) );
AOI22X1TS U6537 ( .A0(add_subt_module_intDY[33]), .A1(n5040), .B0(n5033),
.B1(d_ff3_sh_y_out[33]), .Y(n5022) );
AOI22X1TS U6538 ( .A0(d_ff3_LUT_out[33]), .A1(n5034), .B0(n4954), .B1(
d_ff3_sh_x_out[33]), .Y(n5021) );
NAND2X1TS U6539 ( .A(n5022), .B(n5021), .Y(n1755) );
AOI22X1TS U6540 ( .A0(n5027), .A1(d_ff3_sh_x_out[17]), .B0(n4970), .B1(
d_ff3_sh_y_out[17]), .Y(n5024) );
AOI22X1TS U6541 ( .A0(add_subt_module_intDY[17]), .A1(n5011), .B0(n5041),
.B1(d_ff3_LUT_out[17]), .Y(n5023) );
NAND2X1TS U6542 ( .A(n5024), .B(n5023), .Y(n1751) );
AOI22X1TS U6543 ( .A0(d_ff2_Z[32]), .A1(n5034), .B0(n4948), .B1(d_ff2_X[32]),
.Y(n5026) );
AOI22X1TS U6544 ( .A0(add_subt_module_intDX[32]), .A1(n4922), .B0(n4954),
.B1(d_ff2_Y[32]), .Y(n5025) );
NAND2X1TS U6545 ( .A(n5026), .B(n5025), .Y(n1749) );
AOI22X1TS U6546 ( .A0(add_subt_module_intDX[22]), .A1(n2974), .B0(n5001),
.B1(d_ff2_X[22]), .Y(n5029) );
AOI22X1TS U6547 ( .A0(d_ff2_Z[22]), .A1(n5034), .B0(n4954), .B1(d_ff2_Y[22]),
.Y(n5028) );
NAND2X1TS U6548 ( .A(n5029), .B(n5028), .Y(n1742) );
AOI22X1TS U6549 ( .A0(n5030), .A1(d_ff3_LUT_out[22]), .B0(n4908), .B1(
d_ff3_sh_y_out[22]), .Y(n5032) );
AOI22X1TS U6550 ( .A0(n2985), .A1(n5040), .B0(n5027), .B1(d_ff3_sh_x_out[22]), .Y(n5031) );
NAND2X1TS U6551 ( .A(n5032), .B(n5031), .Y(n1741) );
AOI22X1TS U6552 ( .A0(d_ff2_Z[26]), .A1(n5034), .B0(n4970), .B1(d_ff2_X[26]),
.Y(n5038) );
AOI22X1TS U6553 ( .A0(add_subt_module_intDX[26]), .A1(n4922), .B0(n4971),
.B1(d_ff2_Y[26]), .Y(n5037) );
NAND2X1TS U6554 ( .A(n5038), .B(n5037), .Y(n1735) );
AOI22X1TS U6555 ( .A0(add_subt_module_intDY[26]), .A1(n5036), .B0(n5039),
.B1(d_ff3_sh_y_out[26]), .Y(n5044) );
AOI22X1TS U6556 ( .A0(n4954), .A1(d_ff3_sh_x_out[26]), .B0(n5014), .B1(
d_ff3_LUT_out[26]), .Y(n5043) );
NAND2X1TS U6557 ( .A(n5044), .B(n5043), .Y(n1734) );
initial $sdf_annotate("CORDIC_Arch2_ASIC_fpu_syn_constraints_clk30.tcl_syn.sdf");
endmodule
|
/*
* NAME
* ----
*
* decoder - specialized decoder
*
* DESCRIPTION
* -----------
*
* This is a specialized decoder designed
* to map the 7-bit addresses to the following
* active low enable signals.
*
* Full address decoding is used so devices cannot
* be inadvertly addressed using out of bounds addresses.
*
* address (hex) | device
* ----------------+---------------
* 0x74 | switch_ce_n
* 0x6C | bar_led_ce_n
* 0x50 - 0x5F | mem2_ce_n
* 0x2F | board_led_ce_n
* 0x00 - 0x0F | mem1_ce_n
*
* AUTHOR
* ------
*
* Jeremiah Mahler <[email protected]>
*
*/
module decoder(
input [6:0] address,
output reg bar_led_ce_n,
board_led_ce_n,
switch_ce_n,
mem1_ce_n,
mem2_ce_n);
always @(address) begin
// default, disabled
switch_ce_n = 1'b1;
bar_led_ce_n = 1'b1;
mem2_ce_n = 1'b1;
board_led_ce_n = 1'b1;
mem1_ce_n = 1'b1;
casex (address)
7'h74: switch_ce_n = 1'b0;
7'h6C: bar_led_ce_n = 1'b0;
7'h5?: mem2_ce_n = 1'b0;
7'h2F: board_led_ce_n = 1'b0;
7'h0?: mem1_ce_n = 1'b0;
endcase
end
endmodule
|
// megafunction wizard: %FIFO%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: fifo_4k.v
// Megafunction Name(s):
// dcfifo
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 5.0 Build 168 06/22/2005 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2005 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module fifo_4k (
data,
wrreq,
rdreq,
rdclk,
wrclk,
aclr,
q,
rdempty,
rdusedw,
wrfull,
wrusedw)/* synthesis synthesis_clearbox = 1 */;
input [15:0] data;
input wrreq;
input rdreq;
input rdclk;
input wrclk;
input aclr;
output [15:0] q;
output rdempty;
output [11:0] rdusedw;
output wrfull;
output [11:0] wrusedw;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: Width NUMERIC "16"
// Retrieval info: PRIVATE: Depth NUMERIC "4096"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4096"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "12"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
// Retrieval info: USED_PORT: rdusedw 0 0 12 0 OUTPUT NODEFVAL rdusedw[11..0]
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
// Retrieval info: USED_PORT: wrusedw 0 0 12 0 OUTPUT NODEFVAL wrusedw[11..0]
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: rdusedw 0 0 12 0 @rdusedw 0 0 12 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: CONNECT: wrusedw 0 0 12 0 @wrusedw 0 0 12 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_wave*.jpg FALSE
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_5_axi_slave.v
*
* Date : 2012-11
*
* Description : Model that acts as PS AXI Slave port interface.
* It uses AXI3 Slave BFM
*****************************************************************************/
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_5_axi_slave (
S_RESETN,
S_ARREADY,
S_AWREADY,
S_BVALID,
S_RLAST,
S_RVALID,
S_WREADY,
S_BRESP,
S_RRESP,
S_RDATA,
S_BID,
S_RID,
S_ACLK,
S_ARVALID,
S_AWVALID,
S_BREADY,
S_RREADY,
S_WLAST,
S_WVALID,
S_ARBURST,
S_ARLOCK,
S_ARSIZE,
S_AWBURST,
S_AWLOCK,
S_AWSIZE,
S_ARPROT,
S_AWPROT,
S_ARADDR,
S_AWADDR,
S_WDATA,
S_ARCACHE,
S_ARLEN,
S_AWCACHE,
S_AWLEN,
S_WSTRB,
S_ARID,
S_AWID,
S_WID,
S_AWQOS,
S_ARQOS,
SW_CLK,
WR_DATA_ACK_OCM,
WR_DATA_ACK_DDR,
WR_ADDR,
WR_DATA,
WR_BYTES,
WR_DATA_VALID_OCM,
WR_DATA_VALID_DDR,
WR_QOS,
RD_QOS,
RD_REQ_DDR,
RD_REQ_OCM,
RD_REQ_REG,
RD_ADDR,
RD_DATA_OCM,
RD_DATA_DDR,
RD_DATA_REG,
RD_BYTES,
RD_DATA_VALID_OCM,
RD_DATA_VALID_DDR,
RD_DATA_VALID_REG
);
parameter enable_this_port = 0;
parameter slave_name = "Slave";
parameter data_bus_width = 32;
parameter address_bus_width = 32;
parameter id_bus_width = 6;
parameter slave_base_address = 0;
parameter slave_high_address = 4;
parameter max_outstanding_transactions = 8;
parameter exclusive_access_supported = 0;
parameter max_wr_outstanding_transactions = 8;
parameter max_rd_outstanding_transactions = 8;
`include "processing_system7_bfm_v2_0_5_local_params.v"
/* Local parameters only for this module */
/* Internal counters that are used as Read/Write pointers to the fifo's that store all the transaction info on all channles.
This parameter is used to define the width of these pointers --> depending on Maximum outstanding transactions supported.
1-bit extra width than the no.of.bits needed to represent the outstanding transactions
Extra bit helps in generating the empty and full flags
*/
parameter int_wr_cntr_width = clogb2(max_wr_outstanding_transactions+1);
parameter int_rd_cntr_width = clogb2(max_rd_outstanding_transactions+1);
/* RESP data */
parameter rsp_fifo_bits = axi_rsp_width+id_bus_width;
parameter rsp_lsb = 0;
parameter rsp_msb = axi_rsp_width-1;
parameter rsp_id_lsb = rsp_msb + 1;
parameter rsp_id_msb = rsp_id_lsb + id_bus_width-1;
input S_RESETN;
output S_ARREADY;
output S_AWREADY;
output S_BVALID;
output S_RLAST;
output S_RVALID;
output S_WREADY;
output [axi_rsp_width-1:0] S_BRESP;
output [axi_rsp_width-1:0] S_RRESP;
output [data_bus_width-1:0] S_RDATA;
output [id_bus_width-1:0] S_BID;
output [id_bus_width-1:0] S_RID;
input S_ACLK;
input S_ARVALID;
input S_AWVALID;
input S_BREADY;
input S_RREADY;
input S_WLAST;
input S_WVALID;
input [axi_brst_type_width-1:0] S_ARBURST;
input [axi_lock_width-1:0] S_ARLOCK;
input [axi_size_width-1:0] S_ARSIZE;
input [axi_brst_type_width-1:0] S_AWBURST;
input [axi_lock_width-1:0] S_AWLOCK;
input [axi_size_width-1:0] S_AWSIZE;
input [axi_prot_width-1:0] S_ARPROT;
input [axi_prot_width-1:0] S_AWPROT;
input [address_bus_width-1:0] S_ARADDR;
input [address_bus_width-1:0] S_AWADDR;
input [data_bus_width-1:0] S_WDATA;
input [axi_cache_width-1:0] S_ARCACHE;
input [axi_cache_width-1:0] S_ARLEN;
input [axi_qos_width-1:0] S_ARQOS;
input [axi_cache_width-1:0] S_AWCACHE;
input [axi_len_width-1:0] S_AWLEN;
input [axi_qos_width-1:0] S_AWQOS;
input [(data_bus_width/8)-1:0] S_WSTRB;
input [id_bus_width-1:0] S_ARID;
input [id_bus_width-1:0] S_AWID;
input [id_bus_width-1:0] S_WID;
input SW_CLK;
input WR_DATA_ACK_DDR, WR_DATA_ACK_OCM;
output reg WR_DATA_VALID_DDR, WR_DATA_VALID_OCM;
output reg [max_burst_bits-1:0] WR_DATA;
output reg [addr_width-1:0] WR_ADDR;
output reg [max_burst_bytes_width:0] WR_BYTES;
output reg RD_REQ_OCM, RD_REQ_DDR, RD_REQ_REG;
output reg [addr_width-1:0] RD_ADDR;
input [max_burst_bits-1:0] RD_DATA_DDR,RD_DATA_OCM, RD_DATA_REG;
output reg[max_burst_bytes_width:0] RD_BYTES;
input RD_DATA_VALID_OCM,RD_DATA_VALID_DDR, RD_DATA_VALID_REG;
output reg [axi_qos_width-1:0] WR_QOS, RD_QOS;
wire net_ARVALID;
wire net_AWVALID;
wire net_WVALID;
real s_aclk_period;
cdn_axi3_slave_bfm #(slave_name,
data_bus_width,
address_bus_width,
id_bus_width,
slave_base_address,
(slave_high_address- slave_base_address),
max_outstanding_transactions,
0, ///MEMORY_MODEL_MODE,
exclusive_access_supported)
slave (.ACLK (S_ACLK),
.ARESETn (S_RESETN), /// confirm this
// Write Address Channel
.AWID (S_AWID),
.AWADDR (S_AWADDR),
.AWLEN (S_AWLEN),
.AWSIZE (S_AWSIZE),
.AWBURST (S_AWBURST),
.AWLOCK (S_AWLOCK),
.AWCACHE (S_AWCACHE),
.AWPROT (S_AWPROT),
.AWVALID (net_AWVALID),
.AWREADY (S_AWREADY),
// Write Data Channel Signals.
.WID (S_WID),
.WDATA (S_WDATA),
.WSTRB (S_WSTRB),
.WLAST (S_WLAST),
.WVALID (net_WVALID),
.WREADY (S_WREADY),
// Write Response Channel Signals.
.BID (S_BID),
.BRESP (S_BRESP),
.BVALID (S_BVALID),
.BREADY (S_BREADY),
// Read Address Channel Signals.
.ARID (S_ARID),
.ARADDR (S_ARADDR),
.ARLEN (S_ARLEN),
.ARSIZE (S_ARSIZE),
.ARBURST (S_ARBURST),
.ARLOCK (S_ARLOCK),
.ARCACHE (S_ARCACHE),
.ARPROT (S_ARPROT),
.ARVALID (net_ARVALID),
.ARREADY (S_ARREADY),
// Read Data Channel Signals.
.RID (S_RID),
.RDATA (S_RDATA),
.RRESP (S_RRESP),
.RLAST (S_RLAST),
.RVALID (S_RVALID),
.RREADY (S_RREADY));
/* Latency type and Debug/Error Control */
reg[1:0] latency_type = RANDOM_CASE;
reg DEBUG_INFO = 1;
reg STOP_ON_ERROR = 1'b1;
/* WR_FIFO stores 32-bit address, valid data and valid bytes for each AXI Write burst transaction */
reg [wr_fifo_data_bits-1:0] wr_fifo [0:max_wr_outstanding_transactions-1];
reg [int_wr_cntr_width-1:0] wr_fifo_wr_ptr = 0, wr_fifo_rd_ptr = 0;
wire wr_fifo_empty;
/* Store the awvalid receive time --- necessary for calculating the latency in sending the bresp*/
reg [7:0] aw_time_cnt = 0, bresp_time_cnt = 0;
real awvalid_receive_time[0:max_wr_outstanding_transactions]; // store the time when a new awvalid is received
reg awvalid_flag[0:max_wr_outstanding_transactions]; // indicates awvalid is received
/* Address Write Channel handshake*/
reg[int_wr_cntr_width-1:0] aw_cnt = 0;// count of awvalid
/* various FIFOs for storing the ADDR channel info */
reg [axi_size_width-1:0] awsize [0:max_wr_outstanding_transactions-1];
reg [axi_prot_width-1:0] awprot [0:max_wr_outstanding_transactions-1];
reg [axi_lock_width-1:0] awlock [0:max_wr_outstanding_transactions-1];
reg [axi_cache_width-1:0] awcache [0:max_wr_outstanding_transactions-1];
reg [axi_brst_type_width-1:0] awbrst [0:max_wr_outstanding_transactions-1];
reg [axi_len_width-1:0] awlen [0:max_wr_outstanding_transactions-1];
reg aw_flag [0:max_wr_outstanding_transactions-1];
reg [addr_width-1:0] awaddr [0:max_wr_outstanding_transactions-1];
reg [id_bus_width-1:0] awid [0:max_wr_outstanding_transactions-1];
reg [axi_qos_width-1:0] awqos [0:max_wr_outstanding_transactions-1];
wire aw_fifo_full; // indicates awvalid_fifo is full (max outstanding transactions reached)
/* internal fifos to store burst write data, ID & strobes*/
reg [(data_bus_width*axi_burst_len)-1:0] burst_data [0:max_wr_outstanding_transactions-1];
reg [max_burst_bytes_width:0] burst_valid_bytes [0:max_wr_outstanding_transactions-1]; /// total valid bytes received in a complete burst transfer
reg wlast_flag [0:max_wr_outstanding_transactions-1]; // flag to indicate WLAST received
wire wd_fifo_full;
/* Write Data Channel and Write Response handshake signals*/
reg [int_wr_cntr_width-1:0] wd_cnt = 0;
reg [(data_bus_width*axi_burst_len)-1:0] aligned_wr_data;
reg [addr_width-1:0] aligned_wr_addr;
reg [max_burst_bytes_width:0] valid_data_bytes;
reg [int_wr_cntr_width-1:0] wr_bresp_cnt = 0;
reg [axi_rsp_width-1:0] bresp;
reg [rsp_fifo_bits-1:0] fifo_bresp [0:max_wr_outstanding_transactions-1]; // store the ID and its corresponding response
reg enable_write_bresp;
reg [int_wr_cntr_width-1:0] rd_bresp_cnt = 0;
integer wr_latency_count;
reg wr_delayed;
wire bresp_fifo_empty;
/* states for managing read/write to WR_FIFO */
parameter SEND_DATA = 0, WAIT_ACK = 1;
reg state;
/* Qos*/
reg [axi_qos_width-1:0] ar_qos, aw_qos;
initial begin
if(DEBUG_INFO) begin
if(enable_this_port)
$display("[%0d] : %0s : %0s : Port is ENABLED.",$time, DISP_INFO, slave_name);
else
$display("[%0d] : %0s : %0s : Port is DISABLED.",$time, DISP_INFO, slave_name);
end
end
initial slave.set_disable_reset_value_checks(1);
initial begin
repeat(2) @(posedge S_ACLK);
if(!enable_this_port) begin
slave.set_channel_level_info(0);
slave.set_function_level_info(0);
end
slave.RESPONSE_TIMEOUT = 0;
end
/*--------------------------------------------------------------------------------*/
/* Set Latency type to be used */
task set_latency_type;
input[1:0] lat;
begin
if(enable_this_port)
latency_type = lat;
else begin
if(DEBUG_INFO)
$display("[%0d] : %0s : %0s : Port is disabled. 'Latency Profile' will not be set...",$time, DISP_WARN, slave_name);
end
end
endtask
/*--------------------------------------------------------------------------------*/
/* Set ARQoS to be used */
task set_arqos;
input[axi_qos_width-1:0] qos;
begin
if(enable_this_port)
ar_qos = qos;
else begin
if(DEBUG_INFO)
$display("[%0d] : %0s : %0s : Port is disabled. 'ARQOS' will not be set...",$time, DISP_WARN, slave_name);
end
end
endtask
/*--------------------------------------------------------------------------------*/
/* Set AWQoS to be used */
task set_awqos;
input[axi_qos_width-1:0] qos;
begin
if(enable_this_port)
aw_qos = qos;
else begin
if(DEBUG_INFO)
$display("[%0d] : %0s : %0s : Port is disabled. 'AWQOS' will not be set...",$time, DISP_WARN, slave_name);
end
end
endtask
/*--------------------------------------------------------------------------------*/
/* get the wr latency number */
function [31:0] get_wr_lat_number;
input dummy;
reg[1:0] temp;
begin
case(latency_type)
BEST_CASE : if(slave_name == axi_acp_name) get_wr_lat_number = acp_wr_min; else get_wr_lat_number = gp_wr_min;
AVG_CASE : if(slave_name == axi_acp_name) get_wr_lat_number = acp_wr_avg; else get_wr_lat_number = gp_wr_avg;
WORST_CASE : if(slave_name == axi_acp_name) get_wr_lat_number = acp_wr_max; else get_wr_lat_number = gp_wr_max;
default : begin // RANDOM_CASE
temp = $random;
case(temp)
2'b00 : if(slave_name == axi_acp_name) get_wr_lat_number = ($random()%10+ acp_wr_min); else get_wr_lat_number = ($random()%10+ gp_wr_min);
2'b01 : if(slave_name == axi_acp_name) get_wr_lat_number = ($random()%40+ acp_wr_avg); else get_wr_lat_number = ($random()%40+ gp_wr_avg);
default : if(slave_name == axi_acp_name) get_wr_lat_number = ($random()%60+ acp_wr_max); else get_wr_lat_number = ($random()%60+ gp_wr_max);
endcase
end
endcase
end
endfunction
/*--------------------------------------------------------------------------------*/
/* get the rd latency number */
function [31:0] get_rd_lat_number;
input dummy;
reg[1:0] temp;
begin
case(latency_type)
BEST_CASE : if(slave_name == axi_acp_name) get_rd_lat_number = acp_rd_min; else get_rd_lat_number = gp_rd_min;
AVG_CASE : if(slave_name == axi_acp_name) get_rd_lat_number = acp_rd_avg; else get_rd_lat_number = gp_rd_avg;
WORST_CASE : if(slave_name == axi_acp_name) get_rd_lat_number = acp_rd_max; else get_rd_lat_number = gp_rd_max;
default : begin // RANDOM_CASE
temp = $random;
case(temp)
2'b00 : if(slave_name == axi_acp_name) get_rd_lat_number = ($random()%10+ acp_rd_min); else get_rd_lat_number = ($random()%10+ gp_rd_min);
2'b01 : if(slave_name == axi_acp_name) get_rd_lat_number = ($random()%40+ acp_rd_avg); else get_rd_lat_number = ($random()%40+ gp_rd_avg);
default : if(slave_name == axi_acp_name) get_rd_lat_number = ($random()%60+ acp_rd_max); else get_rd_lat_number = ($random()%60+ gp_rd_max);
endcase
end
endcase
end
endfunction
/*--------------------------------------------------------------------------------*/
/* Store the Clock cycle time period */
always@(S_RESETN)
begin
if(S_RESETN) begin
@(posedge S_ACLK);
s_aclk_period = $time;
@(posedge S_ACLK);
s_aclk_period = $time - s_aclk_period;
end
end
/*--------------------------------------------------------------------------------*/
/* Check for any WRITE/READs when this port is disabled */
always@(S_AWVALID or S_WVALID or S_ARVALID)
begin
if((S_AWVALID | S_WVALID | S_ARVALID) && !enable_this_port) begin
$display("[%0d] : %0s : %0s : Port is disabled. AXI transaction is initiated on this port ...\nSimulation will halt ..",$time, DISP_ERR, slave_name);
$stop;
end
end
/*--------------------------------------------------------------------------------*/
assign net_ARVALID = enable_this_port ? S_ARVALID : 1'b0;
assign net_AWVALID = enable_this_port ? S_AWVALID : 1'b0;
assign net_WVALID = enable_this_port ? S_WVALID : 1'b0;
assign wr_fifo_empty = (wr_fifo_wr_ptr === wr_fifo_rd_ptr)?1'b1: 1'b0;
assign aw_fifo_full = ((aw_cnt[int_wr_cntr_width-1] !== rd_bresp_cnt[int_wr_cntr_width-1]) && (aw_cnt[int_wr_cntr_width-2:0] === rd_bresp_cnt[int_wr_cntr_width-2:0]))?1'b1 :1'b0; /// complete this
assign wd_fifo_full = ((wd_cnt[int_wr_cntr_width-1] !== rd_bresp_cnt[int_wr_cntr_width-1]) && (wd_cnt[int_wr_cntr_width-2:0] === rd_bresp_cnt[int_wr_cntr_width-2:0]))?1'b1 :1'b0; /// complete this
assign bresp_fifo_empty = (wr_bresp_cnt === rd_bresp_cnt)?1'b1:1'b0;
/* Store the awvalid receive time --- necessary for calculating the bresp latency */
always@(negedge S_RESETN or S_AWID or S_AWADDR or S_AWVALID )
begin
if(!S_RESETN)
aw_time_cnt = 0;
else begin
if(S_AWVALID) begin
awvalid_receive_time[aw_time_cnt] = $time;
awvalid_flag[aw_time_cnt] = 1'b1;
aw_time_cnt = aw_time_cnt + 1;
if(aw_time_cnt === max_wr_outstanding_transactions) aw_time_cnt = 0;
end
end // else
end /// always
/*--------------------------------------------------------------------------------*/
always@(posedge S_ACLK)
begin
if(net_AWVALID && S_AWREADY) begin
if(S_AWQOS === 0) awqos[aw_cnt[int_wr_cntr_width-2:0]] = aw_qos;
else awqos[aw_cnt[int_wr_cntr_width-2:0]] = S_AWQOS;
end
end
/*--------------------------------------------------------------------------------*/
always@(aw_fifo_full)
begin
if(aw_fifo_full && DEBUG_INFO)
$display("[%0d] : %0s : %0s : Reached the maximum outstanding Write transactions limit (%0d). Blocking all future Write transactions until at least 1 of the outstanding Write transaction has completed.",$time, DISP_INFO, slave_name,max_wr_outstanding_transactions);
end
/*--------------------------------------------------------------------------------*/
/* Address Write Channel handshake*/
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN) begin
aw_cnt = 0;
end else begin
if(!aw_fifo_full) begin
slave.RECEIVE_WRITE_ADDRESS(0,
id_invalid,
awaddr[aw_cnt[int_wr_cntr_width-2:0]],
awlen[aw_cnt[int_wr_cntr_width-2:0]],
awsize[aw_cnt[int_wr_cntr_width-2:0]],
awbrst[aw_cnt[int_wr_cntr_width-2:0]],
awlock[aw_cnt[int_wr_cntr_width-2:0]],
awcache[aw_cnt[int_wr_cntr_width-2:0]],
awprot[aw_cnt[int_wr_cntr_width-2:0]],
awid[aw_cnt[int_wr_cntr_width-2:0]]); /// sampled valid ID.
aw_flag[aw_cnt[int_wr_cntr_width-2:0]] = 1;
aw_cnt = aw_cnt + 1;
if(aw_cnt[int_wr_cntr_width-2:0] === (max_wr_outstanding_transactions-1)) begin
aw_cnt[int_wr_cntr_width-1] = ~aw_cnt[int_wr_cntr_width-1];
aw_cnt[int_wr_cntr_width-2:0] = 0;
end
end // if (!aw_fifo_full)
end /// if else
end /// always
/*--------------------------------------------------------------------------------*/
/* Write Data Channel Handshake */
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN) begin
wd_cnt = 0;
end else begin
if(!wd_fifo_full && S_WVALID) begin
slave.RECEIVE_WRITE_BURST_NO_CHECKS(S_WID,
burst_data[wd_cnt[int_wr_cntr_width-2:0]],
burst_valid_bytes[wd_cnt[int_wr_cntr_width-2:0]]);
wlast_flag[wd_cnt[int_wr_cntr_width-2:0]] = 1'b1;
wd_cnt = wd_cnt + 1;
if(wd_cnt[int_wr_cntr_width-2:0] === (max_wr_outstanding_transactions-1)) begin
wd_cnt[int_wr_cntr_width-1] = ~wd_cnt[int_wr_cntr_width-1];
wd_cnt[int_wr_cntr_width-2:0] = 0;
end
end /// if
end /// else
end /// always
/*--------------------------------------------------------------------------------*/
/* Align the wrap data for write transaction */
task automatic get_wrap_aligned_wr_data;
output [(data_bus_width*axi_burst_len)-1:0] aligned_data;
output [addr_width-1:0] start_addr; /// aligned start address
input [addr_width-1:0] addr;
input [(data_bus_width*axi_burst_len)-1:0] b_data;
input [max_burst_bytes_width:0] v_bytes;
reg [(data_bus_width*axi_burst_len)-1:0] temp_data, wrp_data;
integer wrp_bytes;
integer i;
begin
start_addr = (addr/v_bytes) * v_bytes;
wrp_bytes = addr - start_addr;
wrp_data = b_data;
temp_data = 0;
wrp_data = wrp_data << ((data_bus_width*axi_burst_len) - (v_bytes*8));
while(wrp_bytes > 0) begin /// get the data that is wrapped
temp_data = temp_data << 8;
temp_data[7:0] = wrp_data[(data_bus_width*axi_burst_len)-1 : (data_bus_width*axi_burst_len)-8];
wrp_data = wrp_data << 8;
wrp_bytes = wrp_bytes - 1;
end
wrp_bytes = addr - start_addr;
wrp_data = b_data << (wrp_bytes*8);
aligned_data = (temp_data | wrp_data);
end
endtask
/*--------------------------------------------------------------------------------*/
/* Calculate the Response for each read/write transaction */
function [axi_rsp_width-1:0] calculate_resp;
input rd_wr; // indicates Read(1) or Write(0) transaction
input [addr_width-1:0] awaddr;
input [axi_prot_width-1:0] awprot;
reg [axi_rsp_width-1:0] rsp;
begin
rsp = AXI_OK;
/* Address Decode */
if(decode_address(awaddr) === INVALID_MEM_TYPE) begin
rsp = AXI_SLV_ERR; //slave error
$display("[%0d] : %0s : %0s : AXI Access to Invalid location(0x%0h) ",$time, DISP_ERR, slave_name, awaddr);
end
if(!rd_wr && decode_address(awaddr) === REG_MEM) begin
rsp = AXI_SLV_ERR; //slave error
$display("[%0d] : %0s : %0s : AXI Write to Register Map(0x%0h) is not supported ",$time, DISP_ERR, slave_name, awaddr);
end
if(secure_access_enabled && awprot[1])
rsp = AXI_DEC_ERR; // decode error
calculate_resp = rsp;
end
endfunction
/*--------------------------------------------------------------------------------*/
/* Store the Write response for each write transaction */
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN) begin
wr_bresp_cnt = 0;
wr_fifo_wr_ptr = 0;
end else begin
enable_write_bresp = aw_flag[wr_bresp_cnt[int_wr_cntr_width-2:0]] && wlast_flag[wr_bresp_cnt[int_wr_cntr_width-2:0]];
/* calculate bresp only when AWVALID && WLAST is received */
if(enable_write_bresp) begin
aw_flag[wr_bresp_cnt[int_wr_cntr_width-2:0]] = 0;
wlast_flag[wr_bresp_cnt[int_wr_cntr_width-2:0]] = 0;
bresp = calculate_resp(1'b0, awaddr[wr_bresp_cnt[int_wr_cntr_width-2:0]],awprot[wr_bresp_cnt[int_wr_cntr_width-2:0]]);
fifo_bresp[wr_bresp_cnt[int_wr_cntr_width-2:0]] = {awid[wr_bresp_cnt[int_wr_cntr_width-2:0]],bresp};
/* Fill WR data FIFO */
if(bresp === AXI_OK) begin
if(awbrst[wr_bresp_cnt[int_wr_cntr_width-2:0]] === AXI_WRAP) begin /// wrap type? then align the data
get_wrap_aligned_wr_data(aligned_wr_data,aligned_wr_addr, awaddr[wr_bresp_cnt[int_wr_cntr_width-2:0]],burst_data[wr_bresp_cnt[int_wr_cntr_width-2:0]],burst_valid_bytes[wr_bresp_cnt[int_wr_cntr_width-2:0]]); /// gives wrapped start address
end else begin
aligned_wr_data = burst_data[wr_bresp_cnt[int_wr_cntr_width-2:0]];
aligned_wr_addr = awaddr[wr_bresp_cnt[int_wr_cntr_width-2:0]] ;
end
valid_data_bytes = burst_valid_bytes[wr_bresp_cnt[int_wr_cntr_width-2:0]];
end else
valid_data_bytes = 0;
wr_fifo[wr_fifo_wr_ptr[int_wr_cntr_width-2:0]] = {awqos[wr_bresp_cnt[int_wr_cntr_width-2:0]], aligned_wr_data, aligned_wr_addr, valid_data_bytes};
wr_fifo_wr_ptr = wr_fifo_wr_ptr + 1;
wr_bresp_cnt = wr_bresp_cnt+1;
if(wr_bresp_cnt[int_wr_cntr_width-2:0] === (max_wr_outstanding_transactions-1)) begin
wr_bresp_cnt[int_wr_cntr_width-1] = ~ wr_bresp_cnt[int_wr_cntr_width-1];
wr_bresp_cnt[int_wr_cntr_width-2:0] = 0;
end
end
end // else
end // always
/*--------------------------------------------------------------------------------*/
/* Send Write Response Channel handshake */
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN) begin
rd_bresp_cnt = 0;
wr_latency_count = get_wr_lat_number(1);
wr_delayed = 0;
bresp_time_cnt = 0;
end else begin
wr_delayed = 1'b0;
if(awvalid_flag[bresp_time_cnt] && (($time - awvalid_receive_time[bresp_time_cnt])/s_aclk_period >= wr_latency_count))
wr_delayed = 1;
if(!bresp_fifo_empty && wr_delayed) begin
slave.SEND_WRITE_RESPONSE(fifo_bresp[rd_bresp_cnt[int_wr_cntr_width-2:0]][rsp_id_msb : rsp_id_lsb], // ID
fifo_bresp[rd_bresp_cnt[int_wr_cntr_width-2:0]][rsp_msb : rsp_lsb] // Response
);
wr_delayed = 0;
awvalid_flag[bresp_time_cnt] = 1'b0;
bresp_time_cnt = bresp_time_cnt+1;
rd_bresp_cnt = rd_bresp_cnt + 1;
if(rd_bresp_cnt[int_wr_cntr_width-2:0] === (max_wr_outstanding_transactions-1)) begin
rd_bresp_cnt[int_wr_cntr_width-1] = ~ rd_bresp_cnt[int_wr_cntr_width-1];
rd_bresp_cnt[int_wr_cntr_width-2:0] = 0;
end
if(bresp_time_cnt === max_wr_outstanding_transactions) begin
bresp_time_cnt = 0;
end
wr_latency_count = get_wr_lat_number(1);
end
end // else
end//always
/*--------------------------------------------------------------------------------*/
/* Reading from the wr_fifo */
always@(negedge S_RESETN or posedge SW_CLK) begin
if(!S_RESETN) begin
WR_DATA_VALID_DDR = 1'b0;
WR_DATA_VALID_OCM = 1'b0;
wr_fifo_rd_ptr = 0;
state = SEND_DATA;
WR_QOS = 0;
end else begin
case(state)
SEND_DATA :begin
state = SEND_DATA;
WR_DATA_VALID_OCM = 0;
WR_DATA_VALID_DDR = 0;
if(!wr_fifo_empty) begin
WR_DATA = wr_fifo[wr_fifo_rd_ptr[int_wr_cntr_width-2:0]][wr_data_msb : wr_data_lsb];
WR_ADDR = wr_fifo[wr_fifo_rd_ptr[int_wr_cntr_width-2:0]][wr_addr_msb : wr_addr_lsb];
WR_BYTES = wr_fifo[wr_fifo_rd_ptr[int_wr_cntr_width-2:0]][wr_bytes_msb : wr_bytes_lsb];
WR_QOS = wr_fifo[wr_fifo_rd_ptr[int_wr_cntr_width-2:0]][wr_qos_msb : wr_qos_lsb];
state = WAIT_ACK;
case (decode_address(wr_fifo[wr_fifo_rd_ptr[int_wr_cntr_width-2:0]][wr_addr_msb : wr_addr_lsb]))
OCM_MEM : WR_DATA_VALID_OCM = 1;
DDR_MEM : WR_DATA_VALID_DDR = 1;
default : state = SEND_DATA;
endcase
wr_fifo_rd_ptr = wr_fifo_rd_ptr+1;
end
end
WAIT_ACK :begin
state = WAIT_ACK;
if(WR_DATA_ACK_OCM | WR_DATA_ACK_DDR) begin
WR_DATA_VALID_OCM = 1'b0;
WR_DATA_VALID_DDR = 1'b0;
state = SEND_DATA;
end
end
endcase
end
end
/*--------------------------------------------------------------------------------*/
/*-------------------------------- WRITE HANDSHAKE END ----------------------------------------*/
/*-------------------------------- READ HANDSHAKE ---------------------------------------------*/
/* READ CHANNELS */
/* Store the arvalid receive time --- necessary for calculating latency in sending the rresp latency */
reg [7:0] ar_time_cnt = 0,rresp_time_cnt = 0;
real arvalid_receive_time[0:max_rd_outstanding_transactions]; // store the time when a new arvalid is received
reg arvalid_flag[0:max_rd_outstanding_transactions]; // store the time when a new arvalid is received
reg [int_rd_cntr_width-1:0] ar_cnt = 0; // counter for arvalid info
/* various FIFOs for storing the ADDR channel info */
reg [axi_size_width-1:0] arsize [0:max_rd_outstanding_transactions-1];
reg [axi_prot_width-1:0] arprot [0:max_rd_outstanding_transactions-1];
reg [axi_brst_type_width-1:0] arbrst [0:max_rd_outstanding_transactions-1];
reg [axi_len_width-1:0] arlen [0:max_rd_outstanding_transactions-1];
reg [axi_cache_width-1:0] arcache [0:max_rd_outstanding_transactions-1];
reg [axi_lock_width-1:0] arlock [0:max_rd_outstanding_transactions-1];
reg ar_flag [0:max_rd_outstanding_transactions-1];
reg [addr_width-1:0] araddr [0:max_rd_outstanding_transactions-1];
reg [id_bus_width-1:0] arid [0:max_rd_outstanding_transactions-1];
reg [axi_qos_width-1:0] arqos [0:max_rd_outstanding_transactions-1];
wire ar_fifo_full; // indicates arvalid_fifo is full (max outstanding transactions reached)
reg [int_rd_cntr_width-1:0] rd_cnt = 0;
reg [int_rd_cntr_width-1:0] wr_rresp_cnt = 0;
reg [axi_rsp_width-1:0] rresp;
reg [rsp_fifo_bits-1:0] fifo_rresp [0:max_rd_outstanding_transactions-1]; // store the ID and its corresponding response
/* Send Read Response & Data Channel handshake */
integer rd_latency_count;
reg rd_delayed;
reg [max_burst_bits-1:0] read_fifo [0:max_rd_outstanding_transactions-1]; /// Store only AXI Burst Data ..
reg [int_rd_cntr_width-1:0] rd_fifo_wr_ptr = 0, rd_fifo_rd_ptr = 0;
wire read_fifo_full;
assign read_fifo_full = (rd_fifo_wr_ptr[int_rd_cntr_width-1] !== rd_fifo_rd_ptr[int_rd_cntr_width-1] && rd_fifo_wr_ptr[int_rd_cntr_width-2:0] === rd_fifo_rd_ptr[int_rd_cntr_width-2:0])?1'b1: 1'b0;
assign read_fifo_empty = (rd_fifo_wr_ptr === rd_fifo_rd_ptr)?1'b1: 1'b0;
assign ar_fifo_full = ((ar_cnt[int_rd_cntr_width-1] !== rd_cnt[int_rd_cntr_width-1]) && (ar_cnt[int_rd_cntr_width-2:0] === rd_cnt[int_rd_cntr_width-2:0]))?1'b1 :1'b0;
/* Store the arvalid receive time --- necessary for calculating the bresp latency */
always@(negedge S_RESETN or S_ARID or S_ARADDR or S_ARVALID )
begin
if(!S_RESETN)
ar_time_cnt = 0;
else begin
if(S_ARVALID) begin
arvalid_receive_time[ar_time_cnt] = $time;
arvalid_flag[ar_time_cnt] = 1'b1;
ar_time_cnt = ar_time_cnt + 1;
if(ar_time_cnt === max_rd_outstanding_transactions)
ar_time_cnt = 0;
end
end // else
end /// always
/*--------------------------------------------------------------------------------*/
always@(posedge S_ACLK)
begin
if(net_ARVALID && S_ARREADY) begin
if(S_ARQOS === 0) arqos[aw_cnt[int_rd_cntr_width-2:0]] = ar_qos;
else arqos[aw_cnt[int_rd_cntr_width-2:0]] = S_ARQOS;
end
end
/*--------------------------------------------------------------------------------*/
always@(ar_fifo_full)
begin
if(ar_fifo_full && DEBUG_INFO)
$display("[%0d] : %0s : %0s : Reached the maximum outstanding Read transactions limit (%0d). Blocking all future Read transactions until at least 1 of the outstanding Read transaction has completed.",$time, DISP_INFO, slave_name,max_rd_outstanding_transactions);
end
/*--------------------------------------------------------------------------------*/
/* Address Read Channel handshake*/
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN) begin
ar_cnt = 0;
end else begin
if(!ar_fifo_full) begin
slave.RECEIVE_READ_ADDRESS(0,
id_invalid,
araddr[ar_cnt[int_rd_cntr_width-2:0]],
arlen[ar_cnt[int_rd_cntr_width-2:0]],
arsize[ar_cnt[int_rd_cntr_width-2:0]],
arbrst[ar_cnt[int_rd_cntr_width-2:0]],
arlock[ar_cnt[int_rd_cntr_width-2:0]],
arcache[ar_cnt[int_rd_cntr_width-2:0]],
arprot[ar_cnt[int_rd_cntr_width-2:0]],
arid[ar_cnt[int_rd_cntr_width-2:0]]); /// sampled valid ID.
ar_flag[ar_cnt[int_rd_cntr_width-2:0]] = 1'b1;
ar_cnt = ar_cnt+1;
if(ar_cnt[int_rd_cntr_width-2:0] === max_rd_outstanding_transactions-1) begin
ar_cnt[int_rd_cntr_width-1] = ~ ar_cnt[int_rd_cntr_width-1];
ar_cnt[int_rd_cntr_width-2:0] = 0;
end
end /// if(!ar_fifo_full)
end /// if else
end /// always*/
/*--------------------------------------------------------------------------------*/
/* Align Wrap data for read transaction*/
task automatic get_wrap_aligned_rd_data;
output [(data_bus_width*axi_burst_len)-1:0] aligned_data;
input [addr_width-1:0] addr;
input [(data_bus_width*axi_burst_len)-1:0] b_data;
input [max_burst_bytes_width:0] v_bytes;
reg [addr_width-1:0] start_addr;
reg [(data_bus_width*axi_burst_len)-1:0] temp_data, wrp_data;
integer wrp_bytes;
integer i;
begin
start_addr = (addr/v_bytes) * v_bytes;
wrp_bytes = addr - start_addr;
wrp_data = b_data;
temp_data = 0;
while(wrp_bytes > 0) begin /// get the data that is wrapped
temp_data = temp_data >> 8;
temp_data[(data_bus_width*axi_burst_len)-1 : (data_bus_width*axi_burst_len)-8] = wrp_data[7:0];
wrp_data = wrp_data >> 8;
wrp_bytes = wrp_bytes - 1;
end
temp_data = temp_data >> ((data_bus_width*axi_burst_len) - (v_bytes*8));
wrp_bytes = addr - start_addr;
wrp_data = b_data >> (wrp_bytes*8);
aligned_data = (temp_data | wrp_data);
end
endtask
/*--------------------------------------------------------------------------------*/
parameter RD_DATA_REQ = 1'b0, WAIT_RD_VALID = 1'b1;
reg [addr_width-1:0] temp_read_address;
reg [max_burst_bytes_width:0] temp_rd_valid_bytes;
reg rd_fifo_state;
reg invalid_rd_req;
/* get the data from memory && also calculate the rresp*/
always@(negedge S_RESETN or posedge SW_CLK)
begin
if(!S_RESETN)begin
rd_fifo_wr_ptr = 0;
wr_rresp_cnt =0;
rd_fifo_state = RD_DATA_REQ;
temp_rd_valid_bytes = 0;
temp_read_address = 0;
RD_REQ_DDR = 0;
RD_REQ_OCM = 0;
RD_REQ_REG = 0;
RD_QOS = 0;
invalid_rd_req = 0;
end else begin
case(rd_fifo_state)
RD_DATA_REQ : begin
rd_fifo_state = RD_DATA_REQ;
RD_REQ_DDR = 0;
RD_REQ_OCM = 0;
RD_REQ_REG = 0;
RD_QOS = 0;
if(ar_flag[wr_rresp_cnt[int_rd_cntr_width-2:0]] && !read_fifo_full) begin
ar_flag[wr_rresp_cnt[int_rd_cntr_width-2:0]] = 0;
rresp = calculate_resp(1'b1, araddr[wr_rresp_cnt[int_rd_cntr_width-2:0]],arprot[wr_rresp_cnt[int_rd_cntr_width-2:0]]);
fifo_rresp[wr_rresp_cnt[int_rd_cntr_width-2:0]] = {arid[wr_rresp_cnt[int_rd_cntr_width-2:0]],rresp};
temp_rd_valid_bytes = (arlen[wr_rresp_cnt[int_rd_cntr_width-2:0]]+1)*(2**arsize[wr_rresp_cnt[int_rd_cntr_width-2:0]]);//data_bus_width/8;
if(arbrst[wr_rresp_cnt[int_rd_cntr_width-2:0]] === AXI_WRAP) /// wrap begin
temp_read_address = (araddr[wr_rresp_cnt[int_rd_cntr_width-2:0]]/temp_rd_valid_bytes) * temp_rd_valid_bytes;
else
temp_read_address = araddr[wr_rresp_cnt[int_rd_cntr_width-2:0]];
if(rresp === AXI_OK) begin
case(decode_address(temp_read_address))//decode_address(araddr[wr_rresp_cnt[int_rd_cntr_width-2:0]]);
OCM_MEM : RD_REQ_OCM = 1;
DDR_MEM : RD_REQ_DDR = 1;
REG_MEM : RD_REQ_REG = 1;
default : invalid_rd_req = 1;
endcase
end else
invalid_rd_req = 1;
RD_QOS = arqos[wr_rresp_cnt[int_rd_cntr_width-2:0]];
RD_ADDR = temp_read_address; ///araddr[wr_rresp_cnt[int_rd_cntr_width-2:0]];
RD_BYTES = temp_rd_valid_bytes;
rd_fifo_state = WAIT_RD_VALID;
wr_rresp_cnt = wr_rresp_cnt + 1;
if(wr_rresp_cnt[int_rd_cntr_width-2:0] === max_rd_outstanding_transactions-1) begin
wr_rresp_cnt[int_rd_cntr_width-1] = ~ wr_rresp_cnt[int_rd_cntr_width-1];
wr_rresp_cnt[int_rd_cntr_width-2:0] = 0;
end
end
end
WAIT_RD_VALID : begin
rd_fifo_state = WAIT_RD_VALID;
if(RD_DATA_VALID_OCM | RD_DATA_VALID_DDR | RD_DATA_VALID_REG | invalid_rd_req) begin ///temp_dec == 2'b11) begin
if(RD_DATA_VALID_DDR)
read_fifo[rd_fifo_wr_ptr[int_rd_cntr_width-2:0]] = RD_DATA_DDR;
else if(RD_DATA_VALID_OCM)
read_fifo[rd_fifo_wr_ptr[int_rd_cntr_width-2:0]] = RD_DATA_OCM;
else if(RD_DATA_VALID_REG)
read_fifo[rd_fifo_wr_ptr[int_rd_cntr_width-2:0]] = RD_DATA_REG;
else
read_fifo[rd_fifo_wr_ptr[int_rd_cntr_width-2:0]] = 0;
rd_fifo_wr_ptr = rd_fifo_wr_ptr + 1;
RD_REQ_DDR = 0;
RD_REQ_OCM = 0;
RD_REQ_REG = 0;
RD_QOS = 0;
invalid_rd_req = 0;
rd_fifo_state = RD_DATA_REQ;
end
end
endcase
end /// else
end /// always
/*--------------------------------------------------------------------------------*/
reg[max_burst_bytes_width:0] rd_v_b;
reg [(data_bus_width*axi_burst_len)-1:0] temp_read_data;
reg [(data_bus_width*axi_burst_len)-1:0] temp_wrap_data;
reg[(axi_rsp_width*axi_burst_len)-1:0] temp_read_rsp;
/* Read Data Channel handshake */
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN)begin
rd_fifo_rd_ptr = 0;
rd_cnt = 0;
rd_latency_count = get_rd_lat_number(1);
rd_delayed = 0;
rresp_time_cnt = 0;
rd_v_b = 0;
end else begin
if(arvalid_flag[rresp_time_cnt] && ((($time - arvalid_receive_time[rresp_time_cnt])/s_aclk_period) >= rd_latency_count))
rd_delayed = 1;
if(!read_fifo_empty && rd_delayed)begin
rd_delayed = 0;
arvalid_flag[rresp_time_cnt] = 1'b0;
rd_v_b = ((arlen[rd_cnt[int_rd_cntr_width-2:0]]+1)*(2**arsize[rd_cnt[int_rd_cntr_width-2:0]]));
temp_read_data = read_fifo[rd_fifo_rd_ptr[int_rd_cntr_width-2:0]];
rd_fifo_rd_ptr = rd_fifo_rd_ptr+1;
if(arbrst[rd_cnt[int_rd_cntr_width-2:0]]=== AXI_WRAP) begin
get_wrap_aligned_rd_data(temp_wrap_data, araddr[rd_cnt[int_rd_cntr_width-2:0]], temp_read_data, rd_v_b);
temp_read_data = temp_wrap_data;
end
temp_read_rsp = 0;
repeat(axi_burst_len) begin
temp_read_rsp = temp_read_rsp >> axi_rsp_width;
temp_read_rsp[(axi_rsp_width*axi_burst_len)-1:(axi_rsp_width*axi_burst_len)-axi_rsp_width] = fifo_rresp[rd_cnt[int_rd_cntr_width-2:0]][rsp_msb : rsp_lsb];
end
slave.SEND_READ_BURST_RESP_CTRL(arid[rd_cnt[int_rd_cntr_width-2:0]],
araddr[rd_cnt[int_rd_cntr_width-2:0]],
arlen[rd_cnt[int_rd_cntr_width-2:0]],
arsize[rd_cnt[int_rd_cntr_width-2:0]],
arbrst[rd_cnt[int_rd_cntr_width-2:0]],
temp_read_data,
temp_read_rsp);
rd_cnt = rd_cnt + 1;
rresp_time_cnt = rresp_time_cnt+1;
if(rresp_time_cnt === max_rd_outstanding_transactions) rresp_time_cnt = 0;
if(rd_cnt[int_rd_cntr_width-2:0] === (max_rd_outstanding_transactions-1)) begin
rd_cnt[int_rd_cntr_width-1] = ~ rd_cnt[int_rd_cntr_width-1];
rd_cnt[int_rd_cntr_width-2:0] = 0;
end
rd_latency_count = get_rd_lat_number(1);
end
end /// else
end /// always
endmodule
|
/*------------------------------------------------------------------------------
* This code was generated by Spiral Multiplier Block Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/licenses/bsd-license.php)
*------------------------------------------------------------------------------ */
/* ./multBlockGen.pl 31056 -fractionalBits 0*/
module multiplier_block (
i_data0,
o_data0
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0]
o_data0;
//Multipliers:
wire [31:0]
w1,
w2048,
w2049,
w128,
w1921,
w16,
w1937,
w4,
w1941,
w31056;
assign w1 = i_data0;
assign w128 = w1 << 7;
assign w16 = w1 << 4;
assign w1921 = w2049 - w128;
assign w1937 = w1921 + w16;
assign w1941 = w1937 + w4;
assign w2048 = w1 << 11;
assign w2049 = w1 + w2048;
assign w31056 = w1941 << 4;
assign w4 = w1 << 2;
assign o_data0 = w31056;
//multiplier_block area estimate = 6127.22886984412;
endmodule //multiplier_block
module surround_with_regs(
i_data0,
o_data0,
clk
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0] o_data0;
reg [31:0] o_data0;
input clk;
reg [31:0] i_data0_reg;
wire [30:0] o_data0_from_mult;
always @(posedge clk) begin
i_data0_reg <= i_data0;
o_data0 <= o_data0_from_mult;
end
multiplier_block mult_blk(
.i_data0(i_data0_reg),
.o_data0(o_data0_from_mult)
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:15:08 08/27/2015
// Design Name:
// Module Name: Tenth_Phase
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Tenth_Phase
//Module Parameters
/***SINGLE PRECISION***/
// W = 32
// EW = 8
// SW = 23
/***DOUBLE PRECISION***/
// W = 64
// EW = 11
// SW = 52
# (parameter W = 32, parameter EW = 8, parameter SW = 23)
// # (parameter W = 64, parameter EW = 11, parameter SW = 52)
(
//INPUTS
input wire clk, //Clock Signal
input wire rst, //Reset Signal
input wire load_i,
input wire sel_a_i, //Overflow/add/subt result's mux's selector
input wire sel_b_i, //underflow/add/subt result's mux's selector
input wire sign_i, //Sign of the largest Operand
input wire [EW-1:0] exp_ieee_i, //Final Exponent
input wire [SW-1:0] sgf_ieee_i,//Final Significand
//OUTPUTS
output wire [W-1:0] final_result_ieee_o //Final Result
);
//Wire Connection signals
wire [SW-1:0] Sgf_S_mux;
wire [EW-1:0] Exp_S_mux;
wire Sign_S_mux;
wire [W-1:0] final_result_reg;
wire overunder;
wire [EW-1:0] exp_mux_D1;
wire [SW-1:0] sgf_mux_D1;
//////////////////////////////////////////////////////////
assign overunder = sel_a_i | sel_b_i;
Mux_3x1 #(.W(1)) Sign_Mux (
.ctrl({sel_a_i,sel_b_i}),
.D0(sign_i),
.D1(1'b1),
.D2(1'b0),
.S(Sign_S_mux)
);
Multiplexer_AC #(.W(EW)) Exp_Mux (
.ctrl(overunder),
.D0(exp_ieee_i),
.D1(exp_mux_D1),
.S(Exp_S_mux)
);
Multiplexer_AC #(.W(SW)) Sgf_Mux (
.ctrl(overunder),
.D0(sgf_ieee_i),
.D1(sgf_mux_D1),
.S(Sgf_S_mux)
);
/////////////////////////////////////////////////////////
generate
if(W == 32) begin
assign exp_mux_D1 =8'hff;
assign sgf_mux_D1 =23'd0;
end
else begin
assign exp_mux_D1 =11'hfff;
assign sgf_mux_D1 =52'd0;
end
endgenerate
////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////
RegisterAdd #(.W(W)) Final_Result_IEEE (
.clk(clk),
.rst(rst),
.load(load_i),
.D({Sign_S_mux,Exp_S_mux,Sgf_S_mux}),
.Q(final_result_ieee_o)
);
endmodule
|
//////////////////////////////////////////////////////////////////////////////
//name : server
//input : input_eth_rx:16
//input : input_socket:16
//output : output_socket:16
//output : output_eth_tx:16
//source_file : ../source/server.c
///======
///
///Created by C2CHIP
//////////////////////////////////////////////////////////////////////////////
// Register Allocation
// ===================
// Register Name Size
// 0 put_eth return address 2
// 1 variable i 2
// 2 put_socket return address 2
// 3 variable i 2
// 4 get_eth return address 2
// 5 variable get_eth return value 2
// 6 rdy_eth return address 2
// 7 variable rdy_eth return value 2
// 8 get_socket return address 2
// 9 variable get_socket return value 2
// 10 array 2
// 11 variable checksum 4
// 12 reset_checksum return address 2
// 13 add_checksum return address 2
// 14 variable data 2
// 15 check_checksum return address 2
// 16 variable check_checksum return value 2
// 17 calc_ack return address 2
// 18 variable calc_ack return value 2
// 19 array 2
// 20 array 2
// 21 variable length 2
// 22 variable new_ack_0 2
// 23 variable new_ack_1 2
// 24 variable return_value 2
// 25 put_ethernet_packet return address 2
// 26 array 2
// 27 variable number_of_bytes 2
// 28 variable destination_mac_address_hi 2
// 29 variable destination_mac_address_med 2
// 30 variable destination_mac_address_lo 2
// 31 variable protocol 2
// 32 variable byte 2
// 33 variable index 2
// 34 get_ethernet_packet return address 2
// 35 variable get_ethernet_packet return value 2
// 36 array 2
// 37 variable number_of_bytes 2
// 38 variable index 2
// 39 variable byte 2
// 40 array 2
// 41 array 2
// 42 array 2
// 43 array 2
// 44 array 2
// 45 variable arp_pounsigneder 2
// 46 get_arp_cache return address 2
// 47 variable get_arp_cache return value 2
// 48 variable ip_hi 2
// 49 variable ip_lo 2
// 50 variable number_of_bytes 2
// 51 variable byte 2
// 52 array 2
// 53 variable i 2
// 54 put_ip_packet return address 2
// 55 array 2
// 56 variable total_length 2
// 57 variable protocol 2
// 58 variable ip_hi 2
// 59 variable ip_lo 2
// 60 variable number_of_bytes 2
// 61 variable i 2
// 62 variable arp_cache 2
// 63 get_ip_packet return address 2
// 64 variable get_ip_packet return value 2
// 65 array 2
// 66 variable total_length 2
// 67 variable header_length 2
// 68 variable payload_start 2
// 69 variable payload_length 2
// 70 variable i 2
// 71 variable from 2
// 72 variable to 2
// 73 variable payload_end 2
// 74 variable number_of_bytes 2
// 75 variable remote_ip_hi 2
// 76 variable remote_ip_lo 2
// 77 variable tx_source 2
// 78 variable tx_dest 2
// 79 array 2
// 80 array 2
// 81 array 2
// 82 variable tx_window 2
// 83 variable tx_fin_flag 2
// 84 variable tx_syn_flag 2
// 85 variable tx_rst_flag 2
// 86 variable tx_psh_flag 2
// 87 variable tx_ack_flag 2
// 88 variable tx_urg_flag 2
// 89 variable rx_source 2
// 90 variable rx_dest 2
// 91 array 2
// 92 array 2
// 93 variable rx_fin_flag 2
// 94 variable rx_syn_flag 2
// 95 variable rx_rst_flag 2
// 96 variable rx_ack_flag 2
// 97 put_tcp_packet return address 2
// 98 array 2
// 99 variable tx_length 2
// 100 variable payload_start 2
// 101 variable packet_length 2
// 102 variable index 2
// 103 variable i 2
// 104 variable rx_length 2
// 105 variable rx_start 2
// 106 get_tcp_packet return address 2
// 107 variable get_tcp_packet return value 2
// 108 array 2
// 109 variable number_of_bytes 2
// 110 variable header_length 2
// 111 variable payload_start 2
// 112 variable total_length 2
// 113 variable payload_length 2
// 114 variable tcp_header_length 2
// 115 application_put_data return address 2
// 116 array 2
// 117 variable start 2
// 118 variable length 2
// 119 variable i 2
// 120 variable index 2
// 121 application_get_data return address 2
// 122 variable application_get_data return value 2
// 123 array 2
// 124 variable start 2
// 125 variable i 2
// 126 variable index 2
// 127 variable length 2
// 128 server return address 2
// 129 array 2
// 130 array 2
// 131 variable tx_start 2
// 132 variable tx_length 2
// 133 variable timeout 2
// 134 variable resend_wait 2
// 135 variable bytes 2
// 136 variable index 2
// 137 variable last_state 2
// 138 variable new_rx_data 2
// 139 variable state 2
// 140 temporary_register 2
// 141 temporary_register 2
// 142 temporary_register 2
// 143 temporary_register 4
// 144 temporary_register 4
// 145 temporary_register 4
// 146 temporary_register 2
// 147 temporary_register 2
// 148 temporary_register 1024
// 149 temporary_register 2
// 150 temporary_register 2
// 151 temporary_register 2048
module server(input_eth_rx,input_socket,input_eth_rx_stb,input_socket_stb,output_socket_ack,output_eth_tx_ack,clk,rst,output_socket,output_eth_tx,output_socket_stb,output_eth_tx_stb,input_eth_rx_ack,input_socket_ack);
integer file_count;
real fp_value;
input [15:0] input_eth_rx;
input [15:0] input_socket;
input input_eth_rx_stb;
input input_socket_stb;
input output_socket_ack;
input output_eth_tx_ack;
input clk;
input rst;
output [15:0] output_socket;
output [15:0] output_eth_tx;
output output_socket_stb;
output output_eth_tx_stb;
output input_eth_rx_ack;
output input_socket_ack;
reg [15:0] timer;
reg timer_enable;
reg stage_0_enable;
reg stage_1_enable;
reg stage_2_enable;
reg [11:0] program_counter;
reg [11:0] program_counter_0;
reg [53:0] instruction_0;
reg [5:0] opcode_0;
reg [7:0] dest_0;
reg [7:0] src_0;
reg [7:0] srcb_0;
reg [31:0] literal_0;
reg [11:0] program_counter_1;
reg [5:0] opcode_1;
reg [7:0] dest_1;
reg [31:0] register_1;
reg [31:0] registerb_1;
reg [31:0] literal_1;
reg [7:0] dest_2;
reg [31:0] result_2;
reg write_enable_2;
reg [15:0] address_2;
reg [15:0] data_out_2;
reg [15:0] data_in_2;
reg memory_enable_2;
reg [15:0] address_4;
reg [31:0] data_out_4;
reg [31:0] data_in_4;
reg memory_enable_4;
reg [15:0] s_output_socket_stb;
reg [15:0] s_output_eth_tx_stb;
reg [15:0] s_output_socket;
reg [15:0] s_output_eth_tx;
reg [15:0] s_input_eth_rx_ack;
reg [15:0] s_input_socket_ack;
reg [15:0] memory_2 [2685:0];
reg [53:0] instructions [3437:0];
reg [31:0] registers [151:0];
//////////////////////////////////////////////////////////////////////////////
// INSTRUCTION INITIALIZATION
//
// Initialise the contents of the instruction memory
//
// Intruction Set
// ==============
// 0 {'float': False, 'literal': True, 'right': False, 'unsigned': False, 'op': 'literal'}
// 1 {'float': False, 'literal': True, 'right': False, 'unsigned': False, 'op': 'jmp_and_link'}
// 2 {'float': False, 'literal': False, 'right': False, 'unsigned': False, 'op': 'stop'}
// 3 {'float': False, 'literal': False, 'right': False, 'unsigned': False, 'op': 'move'}
// 4 {'float': False, 'literal': False, 'right': False, 'unsigned': False, 'op': 'nop'}
// 5 {'right': False, 'float': False, 'unsigned': False, 'literal': False, 'output': 'eth_tx', 'op': 'write'}
// 6 {'float': False, 'literal': False, 'right': False, 'unsigned': False, 'op': 'jmp_to_reg'}
// 7 {'right': False, 'float': False, 'unsigned': False, 'literal': False, 'output': 'socket', 'op': 'write'}
// 8 {'right': False, 'float': False, 'unsigned': False, 'literal': False, 'input': 'eth_rx', 'op': 'read'}
// 9 {'right': False, 'float': False, 'unsigned': False, 'literal': False, 'input': 'eth_rx', 'op': 'ready'}
// 10 {'right': False, 'float': False, 'unsigned': False, 'literal': False, 'input': 'socket', 'op': 'read'}
// 11 {'float': False, 'literal': False, 'right': False, 'unsigned': True, 'op': '+'}
// 12 {'float': False, 'literal': True, 'right': True, 'unsigned': True, 'op': '&'}
// 13 {'float': False, 'literal': True, 'right': False, 'unsigned': False, 'op': 'jmp_if_false'}
// 14 {'float': False, 'literal': True, 'right': True, 'unsigned': True, 'op': '+'}
// 15 {'float': False, 'literal': True, 'right': False, 'unsigned': False, 'op': 'goto'}
// 16 {'float': False, 'literal': False, 'right': False, 'unsigned': False, 'op': '~'}
// 17 {'right': False, 'element_size': 2, 'float': False, 'unsigned': False, 'literal': False, 'op': 'memory_read_request'}
// 18 {'right': False, 'element_size': 2, 'float': False, 'unsigned': False, 'literal': False, 'op': 'memory_read_wait'}
// 19 {'right': False, 'element_size': 2, 'float': False, 'unsigned': False, 'literal': False, 'op': 'memory_read'}
// 20 {'float': False, 'literal': False, 'right': False, 'unsigned': True, 'op': '<'}
// 21 {'float': False, 'literal': False, 'right': False, 'unsigned': True, 'op': '!='}
// 22 {'float': False, 'literal': True, 'right': False, 'unsigned': False, 'op': 'jmp_if_true'}
// 23 {'right': False, 'element_size': 2, 'float': False, 'unsigned': False, 'literal': False, 'op': 'memory_write'}
// 24 {'right': False, 'float': False, 'unsigned': True, 'literal': False, 'file': '/home/amer/Nexys3/GitHub/TCP11/source/server.h', 'line': 107, 'op': 'report'}
// 25 {'float': False, 'literal': True, 'right': True, 'unsigned': True, 'op': '=='}
// 26 {'float': False, 'literal': False, 'right': False, 'unsigned': False, 'op': '+'}
// 27 {'float': False, 'literal': True, 'right': True, 'unsigned': True, 'op': '<'}
// 28 {'float': False, 'literal': False, 'right': False, 'unsigned': True, 'op': '=='}
// 29 {'float': False, 'literal': True, 'right': False, 'unsigned': True, 'op': '|'}
// 30 {'float': False, 'literal': True, 'right': True, 'unsigned': True, 'op': '<='}
// 31 {'float': False, 'literal': True, 'right': True, 'unsigned': True, 'op': '!='}
// 32 {'float': False, 'literal': True, 'right': True, 'unsigned': True, 'op': '>>'}
// 33 {'float': False, 'literal': True, 'right': True, 'unsigned': True, 'op': '<<'}
// 34 {'float': False, 'literal': False, 'right': False, 'unsigned': True, 'op': '-'}
// 35 {'float': False, 'literal': True, 'right': True, 'unsigned': True, 'op': '-'}
// 36 {'float': False, 'literal': False, 'right': False, 'unsigned': True, 'op': '<='}
// 37 {'float': False, 'literal': True, 'right': True, 'unsigned': True, 'op': '|'}
// 38 {'right': False, 'float': False, 'unsigned': False, 'literal': False, 'input': 'socket', 'op': 'ready'}
// 39 {'float': False, 'literal': True, 'right': True, 'unsigned': False, 'op': '=='}
// 40 {'right': False, 'float': False, 'unsigned': False, 'literal': False, 'file': '/home/amer/Nexys3/GitHub/TCP11/source/server.h', 'line': 552, 'op': 'report'}
// 41 {'float': False, 'literal': False, 'right': False, 'unsigned': False, 'op': 'wait_clocks'}
// Intructions
// ===========
initial
begin
instructions[0] = {6'd0, 8'd10, 8'd0, 32'd0};//{'dest': 10, 'literal': 0, 'op': 'literal'}
instructions[1] = {6'd0, 8'd11, 8'd0, 32'd0};//{'dest': 11, 'literal': 0, 'size': 4, 'signed': 4, 'op': 'literal'}
instructions[2] = {6'd0, 8'd40, 8'd0, 32'd520};//{'dest': 40, 'literal': 520, 'op': 'literal'}
instructions[3] = {6'd0, 8'd41, 8'd0, 32'd536};//{'dest': 41, 'literal': 536, 'op': 'literal'}
instructions[4] = {6'd0, 8'd42, 8'd0, 32'd552};//{'dest': 42, 'literal': 552, 'op': 'literal'}
instructions[5] = {6'd0, 8'd43, 8'd0, 32'd568};//{'dest': 43, 'literal': 568, 'op': 'literal'}
instructions[6] = {6'd0, 8'd44, 8'd0, 32'd584};//{'dest': 44, 'literal': 584, 'op': 'literal'}
instructions[7] = {6'd0, 8'd45, 8'd0, 32'd0};//{'dest': 45, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[8] = {6'd0, 8'd75, 8'd0, 32'd0};//{'dest': 75, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[9] = {6'd0, 8'd76, 8'd0, 32'd0};//{'dest': 76, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[10] = {6'd0, 8'd77, 8'd0, 32'd0};//{'dest': 77, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[11] = {6'd0, 8'd78, 8'd0, 32'd0};//{'dest': 78, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[12] = {6'd0, 8'd79, 8'd0, 32'd620};//{'dest': 79, 'literal': 620, 'op': 'literal'}
instructions[13] = {6'd0, 8'd80, 8'd0, 32'd622};//{'dest': 80, 'literal': 622, 'op': 'literal'}
instructions[14] = {6'd0, 8'd81, 8'd0, 32'd624};//{'dest': 81, 'literal': 624, 'op': 'literal'}
instructions[15] = {6'd0, 8'd82, 8'd0, 32'd1460};//{'dest': 82, 'literal': 1460, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[16] = {6'd0, 8'd83, 8'd0, 32'd0};//{'dest': 83, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[17] = {6'd0, 8'd84, 8'd0, 32'd0};//{'dest': 84, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[18] = {6'd0, 8'd85, 8'd0, 32'd0};//{'dest': 85, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[19] = {6'd0, 8'd86, 8'd0, 32'd0};//{'dest': 86, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[20] = {6'd0, 8'd87, 8'd0, 32'd0};//{'dest': 87, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[21] = {6'd0, 8'd88, 8'd0, 32'd0};//{'dest': 88, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[22] = {6'd0, 8'd89, 8'd0, 32'd0};//{'dest': 89, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[23] = {6'd0, 8'd90, 8'd0, 32'd0};//{'dest': 90, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[24] = {6'd0, 8'd91, 8'd0, 32'd626};//{'dest': 91, 'literal': 626, 'op': 'literal'}
instructions[25] = {6'd0, 8'd92, 8'd0, 32'd628};//{'dest': 92, 'literal': 628, 'op': 'literal'}
instructions[26] = {6'd0, 8'd93, 8'd0, 32'd0};//{'dest': 93, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[27] = {6'd0, 8'd94, 8'd0, 32'd0};//{'dest': 94, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[28] = {6'd0, 8'd95, 8'd0, 32'd0};//{'dest': 95, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[29] = {6'd0, 8'd96, 8'd0, 32'd0};//{'dest': 96, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[30] = {6'd0, 8'd104, 8'd0, 32'd0};//{'dest': 104, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[31] = {6'd0, 8'd105, 8'd0, 32'd0};//{'dest': 105, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[32] = {6'd1, 8'd128, 8'd0, 32'd2513};//{'dest': 128, 'label': 2513, 'op': 'jmp_and_link'}
instructions[33] = {6'd2, 8'd0, 8'd0, 32'd0};//{'op': 'stop'}
instructions[34] = {6'd3, 8'd140, 8'd1, 32'd0};//{'dest': 140, 'src': 1, 'op': 'move'}
instructions[35] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[36] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[37] = {6'd5, 8'd0, 8'd140, 32'd0};//{'src': 140, 'output': 'eth_tx', 'op': 'write'}
instructions[38] = {6'd6, 8'd0, 8'd0, 32'd0};//{'src': 0, 'op': 'jmp_to_reg'}
instructions[39] = {6'd3, 8'd140, 8'd3, 32'd0};//{'dest': 140, 'src': 3, 'op': 'move'}
instructions[40] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[41] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[42] = {6'd7, 8'd0, 8'd140, 32'd0};//{'src': 140, 'output': 'socket', 'op': 'write'}
instructions[43] = {6'd6, 8'd0, 8'd2, 32'd0};//{'src': 2, 'op': 'jmp_to_reg'}
instructions[44] = {6'd8, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'input': 'eth_rx', 'op': 'read'}
instructions[45] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[46] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[47] = {6'd3, 8'd5, 8'd140, 32'd0};//{'dest': 5, 'src': 140, 'op': 'move'}
instructions[48] = {6'd6, 8'd0, 8'd4, 32'd0};//{'src': 4, 'op': 'jmp_to_reg'}
instructions[49] = {6'd9, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'input': 'eth_rx', 'op': 'ready'}
instructions[50] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[51] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[52] = {6'd3, 8'd7, 8'd140, 32'd0};//{'dest': 7, 'src': 140, 'op': 'move'}
instructions[53] = {6'd6, 8'd0, 8'd6, 32'd0};//{'src': 6, 'op': 'jmp_to_reg'}
instructions[54] = {6'd10, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'input': 'socket', 'op': 'read'}
instructions[55] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[56] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[57] = {6'd3, 8'd9, 8'd140, 32'd0};//{'dest': 9, 'src': 140, 'op': 'move'}
instructions[58] = {6'd6, 8'd0, 8'd8, 32'd0};//{'src': 8, 'op': 'jmp_to_reg'}
instructions[59] = {6'd0, 8'd143, 8'd0, 32'd0};//{'dest': 143, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[60] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[61] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[62] = {6'd3, 8'd11, 8'd143, 32'd0};//{'dest': 11, 'src': 143, 'op': 'move'}
instructions[63] = {6'd6, 8'd0, 8'd12, 32'd0};//{'src': 12, 'op': 'jmp_to_reg'}
instructions[64] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[65] = {6'd3, 8'd144, 8'd11, 32'd0};//{'dest': 144, 'src': 11, 'op': 'move'}
instructions[66] = {6'd3, 8'd145, 8'd14, 32'd0};//{'dest': 145, 'src': 14, 'op': 'move'}
instructions[67] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[68] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[69] = {6'd11, 8'd143, 8'd144, 32'd145};//{'srcb': 145, 'src': 144, 'dest': 143, 'signed': False, 'op': '+', 'type': 'int', 'size': 4}
instructions[70] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[71] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[72] = {6'd3, 8'd11, 8'd143, 32'd0};//{'dest': 11, 'src': 143, 'op': 'move'}
instructions[73] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[74] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[75] = {6'd3, 8'd144, 8'd11, 32'd0};//{'dest': 144, 'src': 11, 'op': 'move'}
instructions[76] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[77] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[78] = {6'd12, 8'd143, 8'd144, 32'd65536};//{'src': 144, 'right': 65536, 'dest': 143, 'signed': False, 'op': '&', 'type': 'int', 'size': 4}
instructions[79] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[80] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[81] = {6'd13, 8'd0, 8'd143, 32'd99};//{'src': 143, 'label': 99, 'op': 'jmp_if_false'}
instructions[82] = {6'd3, 8'd144, 8'd11, 32'd0};//{'dest': 144, 'src': 11, 'op': 'move'}
instructions[83] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[84] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[85] = {6'd12, 8'd143, 8'd144, 32'd65535};//{'src': 144, 'right': 65535, 'dest': 143, 'signed': False, 'op': '&', 'type': 'int', 'size': 4}
instructions[86] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[87] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[88] = {6'd3, 8'd11, 8'd143, 32'd0};//{'dest': 11, 'src': 143, 'op': 'move'}
instructions[89] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[90] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[91] = {6'd3, 8'd144, 8'd11, 32'd0};//{'dest': 144, 'src': 11, 'op': 'move'}
instructions[92] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[93] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[94] = {6'd14, 8'd143, 8'd144, 32'd1};//{'src': 144, 'right': 1, 'dest': 143, 'signed': False, 'op': '+', 'type': 'int', 'size': 4}
instructions[95] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[96] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[97] = {6'd3, 8'd11, 8'd143, 32'd0};//{'dest': 11, 'src': 143, 'op': 'move'}
instructions[98] = {6'd15, 8'd0, 8'd0, 32'd99};//{'label': 99, 'op': 'goto'}
instructions[99] = {6'd6, 8'd0, 8'd13, 32'd0};//{'src': 13, 'op': 'jmp_to_reg'}
instructions[100] = {6'd3, 8'd143, 8'd11, 32'd0};//{'dest': 143, 'src': 11, 'op': 'move'}
instructions[101] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[102] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[103] = {6'd16, 8'd140, 8'd143, 32'd0};//{'dest': 140, 'src': 143, 'op': '~'}
instructions[104] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[105] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[106] = {6'd3, 8'd16, 8'd140, 32'd0};//{'dest': 16, 'src': 140, 'op': 'move'}
instructions[107] = {6'd6, 8'd0, 8'd15, 32'd0};//{'src': 15, 'op': 'jmp_to_reg'}
instructions[108] = {6'd0, 8'd22, 8'd0, 32'd0};//{'dest': 22, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[109] = {6'd0, 8'd23, 8'd0, 32'd0};//{'dest': 23, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[110] = {6'd0, 8'd24, 8'd0, 32'd0};//{'dest': 24, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[111] = {6'd0, 8'd142, 8'd0, 32'd0};//{'dest': 142, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[112] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[113] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[114] = {6'd11, 8'd146, 8'd142, 32'd20};//{'dest': 146, 'src': 142, 'srcb': 20, 'signed': False, 'op': '+'}
instructions[115] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[116] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[117] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592953344, 'op': 'memory_read_request'}
instructions[118] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[119] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592953344, 'op': 'memory_read_wait'}
instructions[120] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139709592953344, 'element_size': 2, 'op': 'memory_read'}
instructions[121] = {6'd3, 8'd142, 8'd21, 32'd0};//{'dest': 142, 'src': 21, 'op': 'move'}
instructions[122] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[123] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[124] = {6'd11, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[125] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[126] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[127] = {6'd3, 8'd22, 8'd140, 32'd0};//{'dest': 22, 'src': 140, 'op': 'move'}
instructions[128] = {6'd0, 8'd141, 8'd0, 32'd1};//{'dest': 141, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[129] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[130] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[131] = {6'd11, 8'd142, 8'd141, 32'd20};//{'dest': 142, 'src': 141, 'srcb': 20, 'signed': False, 'op': '+'}
instructions[132] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[133] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[134] = {6'd17, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 139709592953848, 'op': 'memory_read_request'}
instructions[135] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[136] = {6'd18, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 139709592953848, 'op': 'memory_read_wait'}
instructions[137] = {6'd19, 8'd140, 8'd142, 32'd0};//{'dest': 140, 'src': 142, 'sequence': 139709592953848, 'element_size': 2, 'op': 'memory_read'}
instructions[138] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[139] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[140] = {6'd3, 8'd23, 8'd140, 32'd0};//{'dest': 23, 'src': 140, 'op': 'move'}
instructions[141] = {6'd3, 8'd141, 8'd22, 32'd0};//{'dest': 141, 'src': 22, 'op': 'move'}
instructions[142] = {6'd3, 8'd142, 8'd21, 32'd0};//{'dest': 142, 'src': 21, 'op': 'move'}
instructions[143] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[144] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[145] = {6'd20, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '<', 'type': 'int', 'size': 2}
instructions[146] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[147] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[148] = {6'd13, 8'd0, 8'd140, 32'd157};//{'src': 140, 'label': 157, 'op': 'jmp_if_false'}
instructions[149] = {6'd3, 8'd141, 8'd23, 32'd0};//{'dest': 141, 'src': 23, 'op': 'move'}
instructions[150] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[151] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[152] = {6'd14, 8'd140, 8'd141, 32'd1};//{'src': 141, 'right': 1, 'dest': 140, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[153] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[154] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[155] = {6'd3, 8'd23, 8'd140, 32'd0};//{'dest': 23, 'src': 140, 'op': 'move'}
instructions[156] = {6'd15, 8'd0, 8'd0, 32'd157};//{'label': 157, 'op': 'goto'}
instructions[157] = {6'd3, 8'd141, 8'd22, 32'd0};//{'dest': 141, 'src': 22, 'op': 'move'}
instructions[158] = {6'd0, 8'd146, 8'd0, 32'd0};//{'dest': 146, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[159] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[160] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[161] = {6'd11, 8'd147, 8'd146, 32'd19};//{'dest': 147, 'src': 146, 'srcb': 19, 'signed': False, 'op': '+'}
instructions[162] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[163] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[164] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709592975624, 'op': 'memory_read_request'}
instructions[165] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[166] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709592975624, 'op': 'memory_read_wait'}
instructions[167] = {6'd19, 8'd142, 8'd147, 32'd0};//{'dest': 142, 'src': 147, 'sequence': 139709592975624, 'element_size': 2, 'op': 'memory_read'}
instructions[168] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[169] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[170] = {6'd21, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '!=', 'type': 'int', 'size': 2}
instructions[171] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[172] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[173] = {6'd22, 8'd0, 8'd140, 32'd188};//{'src': 140, 'label': 188, 'op': 'jmp_if_true'}
instructions[174] = {6'd3, 8'd141, 8'd23, 32'd0};//{'dest': 141, 'src': 23, 'op': 'move'}
instructions[175] = {6'd0, 8'd146, 8'd0, 32'd1};//{'dest': 146, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[176] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[177] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[178] = {6'd11, 8'd147, 8'd146, 32'd19};//{'dest': 147, 'src': 146, 'srcb': 19, 'signed': False, 'op': '+'}
instructions[179] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[180] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[181] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709592975912, 'op': 'memory_read_request'}
instructions[182] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[183] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709592975912, 'op': 'memory_read_wait'}
instructions[184] = {6'd19, 8'd142, 8'd147, 32'd0};//{'dest': 142, 'src': 147, 'sequence': 139709592975912, 'element_size': 2, 'op': 'memory_read'}
instructions[185] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[186] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[187] = {6'd21, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '!=', 'type': 'int', 'size': 2}
instructions[188] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[189] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[190] = {6'd13, 8'd0, 8'd140, 32'd212};//{'src': 140, 'label': 212, 'op': 'jmp_if_false'}
instructions[191] = {6'd3, 8'd140, 8'd22, 32'd0};//{'dest': 140, 'src': 22, 'op': 'move'}
instructions[192] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[193] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[194] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[195] = {6'd11, 8'd142, 8'd141, 32'd19};//{'dest': 142, 'src': 141, 'srcb': 19, 'signed': False, 'op': '+'}
instructions[196] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[197] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[198] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[199] = {6'd3, 8'd140, 8'd23, 32'd0};//{'dest': 140, 'src': 23, 'op': 'move'}
instructions[200] = {6'd0, 8'd141, 8'd0, 32'd1};//{'dest': 141, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[201] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[202] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[203] = {6'd11, 8'd142, 8'd141, 32'd19};//{'dest': 142, 'src': 141, 'srcb': 19, 'signed': False, 'op': '+'}
instructions[204] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[205] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[206] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[207] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[208] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[209] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[210] = {6'd3, 8'd24, 8'd140, 32'd0};//{'dest': 24, 'src': 140, 'op': 'move'}
instructions[211] = {6'd15, 8'd0, 8'd0, 32'd212};//{'label': 212, 'op': 'goto'}
instructions[212] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[213] = {6'd3, 8'd140, 8'd24, 32'd0};//{'dest': 140, 'src': 24, 'op': 'move'}
instructions[214] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[215] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[216] = {6'd3, 8'd18, 8'd140, 32'd0};//{'dest': 18, 'src': 140, 'op': 'move'}
instructions[217] = {6'd6, 8'd0, 8'd17, 32'd0};//{'src': 17, 'op': 'jmp_to_reg'}
instructions[218] = {6'd0, 8'd32, 8'd0, 32'd0};//{'dest': 32, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[219] = {6'd0, 8'd33, 8'd0, 32'd0};//{'dest': 33, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[220] = {6'd3, 8'd140, 8'd27, 32'd0};//{'dest': 140, 'src': 27, 'op': 'move'}
instructions[221] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[222] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[223] = {6'd24, 8'd0, 8'd140, 32'd0};//{'src': 140, 'signed': False, 'file': '/home/amer/Nexys3/GitHub/TCP11/source/server.h', 'line': 107, 'type': 'int', 'op': 'report'}
instructions[224] = {6'd3, 8'd140, 8'd28, 32'd0};//{'dest': 140, 'src': 28, 'op': 'move'}
instructions[225] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[226] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[227] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[228] = {6'd11, 8'd142, 8'd141, 32'd26};//{'dest': 142, 'src': 141, 'srcb': 26, 'signed': False, 'op': '+'}
instructions[229] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[230] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[231] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[232] = {6'd3, 8'd140, 8'd29, 32'd0};//{'dest': 140, 'src': 29, 'op': 'move'}
instructions[233] = {6'd0, 8'd141, 8'd0, 32'd1};//{'dest': 141, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[234] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[235] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[236] = {6'd11, 8'd142, 8'd141, 32'd26};//{'dest': 142, 'src': 141, 'srcb': 26, 'signed': False, 'op': '+'}
instructions[237] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[238] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[239] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[240] = {6'd3, 8'd140, 8'd30, 32'd0};//{'dest': 140, 'src': 30, 'op': 'move'}
instructions[241] = {6'd0, 8'd141, 8'd0, 32'd2};//{'dest': 141, 'literal': 2, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[242] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[243] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[244] = {6'd11, 8'd142, 8'd141, 32'd26};//{'dest': 142, 'src': 141, 'srcb': 26, 'signed': False, 'op': '+'}
instructions[245] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[246] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[247] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[248] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[249] = {6'd0, 8'd141, 8'd0, 32'd3};//{'dest': 141, 'literal': 3, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[250] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[251] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[252] = {6'd11, 8'd142, 8'd141, 32'd26};//{'dest': 142, 'src': 141, 'srcb': 26, 'signed': False, 'op': '+'}
instructions[253] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[254] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[255] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[256] = {6'd0, 8'd140, 8'd0, 32'd515};//{'dest': 140, 'literal': 515, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[257] = {6'd0, 8'd141, 8'd0, 32'd4};//{'dest': 141, 'literal': 4, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[258] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[259] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[260] = {6'd11, 8'd142, 8'd141, 32'd26};//{'dest': 142, 'src': 141, 'srcb': 26, 'signed': False, 'op': '+'}
instructions[261] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[262] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[263] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[264] = {6'd0, 8'd140, 8'd0, 32'd1029};//{'dest': 140, 'literal': 1029, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[265] = {6'd0, 8'd141, 8'd0, 32'd5};//{'dest': 141, 'literal': 5, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[266] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[267] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[268] = {6'd11, 8'd142, 8'd141, 32'd26};//{'dest': 142, 'src': 141, 'srcb': 26, 'signed': False, 'op': '+'}
instructions[269] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[270] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[271] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[272] = {6'd3, 8'd140, 8'd31, 32'd0};//{'dest': 140, 'src': 31, 'op': 'move'}
instructions[273] = {6'd0, 8'd141, 8'd0, 32'd6};//{'dest': 141, 'literal': 6, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[274] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[275] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[276] = {6'd11, 8'd142, 8'd141, 32'd26};//{'dest': 142, 'src': 141, 'srcb': 26, 'signed': False, 'op': '+'}
instructions[277] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[278] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[279] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[280] = {6'd3, 8'd141, 8'd27, 32'd0};//{'dest': 141, 'src': 27, 'op': 'move'}
instructions[281] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[282] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[283] = {6'd3, 8'd1, 8'd141, 32'd0};//{'dest': 1, 'src': 141, 'op': 'move'}
instructions[284] = {6'd1, 8'd0, 8'd0, 32'd34};//{'dest': 0, 'label': 34, 'op': 'jmp_and_link'}
instructions[285] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[286] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[287] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[288] = {6'd3, 8'd33, 8'd140, 32'd0};//{'dest': 33, 'src': 140, 'op': 'move'}
instructions[289] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[290] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[291] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[292] = {6'd3, 8'd32, 8'd140, 32'd0};//{'dest': 32, 'src': 140, 'op': 'move'}
instructions[293] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[294] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[295] = {6'd3, 8'd141, 8'd32, 32'd0};//{'dest': 141, 'src': 32, 'op': 'move'}
instructions[296] = {6'd3, 8'd142, 8'd27, 32'd0};//{'dest': 142, 'src': 27, 'op': 'move'}
instructions[297] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[298] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[299] = {6'd20, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '<', 'type': 'int', 'size': 2}
instructions[300] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[301] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[302] = {6'd13, 8'd0, 8'd140, 32'd327};//{'src': 140, 'label': 327, 'op': 'jmp_if_false'}
instructions[303] = {6'd3, 8'd142, 8'd33, 32'd0};//{'dest': 142, 'src': 33, 'op': 'move'}
instructions[304] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[305] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[306] = {6'd11, 8'd146, 8'd142, 32'd26};//{'dest': 146, 'src': 142, 'srcb': 26, 'signed': False, 'op': '+'}
instructions[307] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[308] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[309] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592496104, 'op': 'memory_read_request'}
instructions[310] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[311] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592496104, 'op': 'memory_read_wait'}
instructions[312] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139709592496104, 'element_size': 2, 'op': 'memory_read'}
instructions[313] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[314] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[315] = {6'd3, 8'd1, 8'd141, 32'd0};//{'dest': 1, 'src': 141, 'op': 'move'}
instructions[316] = {6'd1, 8'd0, 8'd0, 32'd34};//{'dest': 0, 'label': 34, 'op': 'jmp_and_link'}
instructions[317] = {6'd3, 8'd140, 8'd33, 32'd0};//{'dest': 140, 'src': 33, 'op': 'move'}
instructions[318] = {6'd14, 8'd33, 8'd33, 32'd1};//{'src': 33, 'right': 1, 'dest': 33, 'signed': False, 'op': '+', 'size': 2}
instructions[319] = {6'd3, 8'd141, 8'd32, 32'd0};//{'dest': 141, 'src': 32, 'op': 'move'}
instructions[320] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[321] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[322] = {6'd14, 8'd140, 8'd141, 32'd2};//{'src': 141, 'right': 2, 'dest': 140, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[323] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[324] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[325] = {6'd3, 8'd32, 8'd140, 32'd0};//{'dest': 32, 'src': 140, 'op': 'move'}
instructions[326] = {6'd15, 8'd0, 8'd0, 32'd293};//{'label': 293, 'op': 'goto'}
instructions[327] = {6'd6, 8'd0, 8'd25, 32'd0};//{'src': 25, 'op': 'jmp_to_reg'}
instructions[328] = {6'd0, 8'd37, 8'd0, 32'd0};//{'dest': 37, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[329] = {6'd0, 8'd38, 8'd0, 32'd0};//{'dest': 38, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[330] = {6'd0, 8'd39, 8'd0, 32'd0};//{'dest': 39, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[331] = {6'd1, 8'd6, 8'd0, 32'd49};//{'dest': 6, 'label': 49, 'op': 'jmp_and_link'}
instructions[332] = {6'd3, 8'd141, 8'd7, 32'd0};//{'dest': 141, 'src': 7, 'op': 'move'}
instructions[333] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[334] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[335] = {6'd25, 8'd140, 8'd141, 32'd0};//{'src': 141, 'right': 0, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[336] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[337] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[338] = {6'd13, 8'd0, 8'd140, 32'd345};//{'src': 140, 'label': 345, 'op': 'jmp_if_false'}
instructions[339] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[340] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[341] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[342] = {6'd3, 8'd35, 8'd140, 32'd0};//{'dest': 35, 'src': 140, 'op': 'move'}
instructions[343] = {6'd6, 8'd0, 8'd34, 32'd0};//{'src': 34, 'op': 'jmp_to_reg'}
instructions[344] = {6'd15, 8'd0, 8'd0, 32'd345};//{'label': 345, 'op': 'goto'}
instructions[345] = {6'd1, 8'd4, 8'd0, 32'd44};//{'dest': 4, 'label': 44, 'op': 'jmp_and_link'}
instructions[346] = {6'd3, 8'd140, 8'd5, 32'd0};//{'dest': 140, 'src': 5, 'op': 'move'}
instructions[347] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[348] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[349] = {6'd3, 8'd37, 8'd140, 32'd0};//{'dest': 37, 'src': 140, 'op': 'move'}
instructions[350] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[351] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[352] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[353] = {6'd3, 8'd38, 8'd140, 32'd0};//{'dest': 38, 'src': 140, 'op': 'move'}
instructions[354] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[355] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[356] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[357] = {6'd3, 8'd39, 8'd140, 32'd0};//{'dest': 39, 'src': 140, 'op': 'move'}
instructions[358] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[359] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[360] = {6'd3, 8'd141, 8'd39, 32'd0};//{'dest': 141, 'src': 39, 'op': 'move'}
instructions[361] = {6'd3, 8'd142, 8'd37, 32'd0};//{'dest': 142, 'src': 37, 'op': 'move'}
instructions[362] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[363] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[364] = {6'd20, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '<', 'type': 'int', 'size': 2}
instructions[365] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[366] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[367] = {6'd13, 8'd0, 8'd140, 32'd387};//{'src': 140, 'label': 387, 'op': 'jmp_if_false'}
instructions[368] = {6'd1, 8'd4, 8'd0, 32'd44};//{'dest': 4, 'label': 44, 'op': 'jmp_and_link'}
instructions[369] = {6'd3, 8'd140, 8'd5, 32'd0};//{'dest': 140, 'src': 5, 'op': 'move'}
instructions[370] = {6'd3, 8'd141, 8'd38, 32'd0};//{'dest': 141, 'src': 38, 'op': 'move'}
instructions[371] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[372] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[373] = {6'd11, 8'd142, 8'd141, 32'd36};//{'dest': 142, 'src': 141, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[374] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[375] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[376] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[377] = {6'd3, 8'd140, 8'd38, 32'd0};//{'dest': 140, 'src': 38, 'op': 'move'}
instructions[378] = {6'd14, 8'd38, 8'd38, 32'd1};//{'src': 38, 'right': 1, 'dest': 38, 'signed': False, 'op': '+', 'size': 2}
instructions[379] = {6'd3, 8'd141, 8'd39, 32'd0};//{'dest': 141, 'src': 39, 'op': 'move'}
instructions[380] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[381] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[382] = {6'd14, 8'd140, 8'd141, 32'd2};//{'src': 141, 'right': 2, 'dest': 140, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[383] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[384] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[385] = {6'd3, 8'd39, 8'd140, 32'd0};//{'dest': 39, 'src': 140, 'op': 'move'}
instructions[386] = {6'd15, 8'd0, 8'd0, 32'd358};//{'label': 358, 'op': 'goto'}
instructions[387] = {6'd0, 8'd142, 8'd0, 32'd6};//{'dest': 142, 'literal': 6, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[388] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[389] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[390] = {6'd11, 8'd146, 8'd142, 32'd36};//{'dest': 146, 'src': 142, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[391] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[392] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[393] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592497112, 'op': 'memory_read_request'}
instructions[394] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[395] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592497112, 'op': 'memory_read_wait'}
instructions[396] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139709592497112, 'element_size': 2, 'op': 'memory_read'}
instructions[397] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[398] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[399] = {6'd25, 8'd140, 8'd141, 32'd2054};//{'src': 141, 'right': 2054, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[400] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[401] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[402] = {6'd13, 8'd0, 8'd140, 32'd635};//{'src': 140, 'label': 635, 'op': 'jmp_if_false'}
instructions[403] = {6'd0, 8'd142, 8'd0, 32'd10};//{'dest': 142, 'literal': 10, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[404] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[405] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[406] = {6'd11, 8'd146, 8'd142, 32'd36};//{'dest': 146, 'src': 142, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[407] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[408] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[409] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592497616, 'op': 'memory_read_request'}
instructions[410] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[411] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592497616, 'op': 'memory_read_wait'}
instructions[412] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139709592497616, 'element_size': 2, 'op': 'memory_read'}
instructions[413] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[414] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[415] = {6'd25, 8'd140, 8'd141, 32'd1};//{'src': 141, 'right': 1, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[416] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[417] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[418] = {6'd13, 8'd0, 8'd140, 32'd629};//{'src': 140, 'label': 629, 'op': 'jmp_if_false'}
instructions[419] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[420] = {6'd0, 8'd141, 8'd0, 32'd7};//{'dest': 141, 'literal': 7, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[421] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[422] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[423] = {6'd26, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': True, 'op': '+'}
instructions[424] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[425] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[426] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[427] = {6'd0, 8'd140, 8'd0, 32'd2048};//{'dest': 140, 'literal': 2048, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[428] = {6'd0, 8'd141, 8'd0, 32'd8};//{'dest': 141, 'literal': 8, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[429] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[430] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[431] = {6'd26, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': True, 'op': '+'}
instructions[432] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[433] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[434] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[435] = {6'd0, 8'd140, 8'd0, 32'd1540};//{'dest': 140, 'literal': 1540, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[436] = {6'd0, 8'd141, 8'd0, 32'd9};//{'dest': 141, 'literal': 9, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[437] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[438] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[439] = {6'd26, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': True, 'op': '+'}
instructions[440] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[441] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[442] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[443] = {6'd0, 8'd140, 8'd0, 32'd2};//{'dest': 140, 'literal': 2, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[444] = {6'd0, 8'd141, 8'd0, 32'd10};//{'dest': 141, 'literal': 10, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[445] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[446] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[447] = {6'd26, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': True, 'op': '+'}
instructions[448] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[449] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[450] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[451] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[452] = {6'd0, 8'd141, 8'd0, 32'd11};//{'dest': 141, 'literal': 11, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[453] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[454] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[455] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[456] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[457] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[458] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[459] = {6'd0, 8'd140, 8'd0, 32'd515};//{'dest': 140, 'literal': 515, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[460] = {6'd0, 8'd141, 8'd0, 32'd12};//{'dest': 141, 'literal': 12, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[461] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[462] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[463] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[464] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[465] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[466] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[467] = {6'd0, 8'd140, 8'd0, 32'd1029};//{'dest': 140, 'literal': 1029, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[468] = {6'd0, 8'd141, 8'd0, 32'd13};//{'dest': 141, 'literal': 13, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[469] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[470] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[471] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[472] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[473] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[474] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[475] = {6'd0, 8'd140, 8'd0, 32'd49320};//{'dest': 140, 'literal': 49320, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[476] = {6'd0, 8'd141, 8'd0, 32'd14};//{'dest': 141, 'literal': 14, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[477] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[478] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[479] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[480] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[481] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[482] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[483] = {6'd0, 8'd140, 8'd0, 32'd119};//{'dest': 140, 'literal': 119, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[484] = {6'd0, 8'd141, 8'd0, 32'd15};//{'dest': 141, 'literal': 15, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[485] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[486] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[487] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[488] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[489] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[490] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[491] = {6'd0, 8'd146, 8'd0, 32'd11};//{'dest': 146, 'literal': 11, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[492] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[493] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[494] = {6'd11, 8'd147, 8'd146, 32'd36};//{'dest': 147, 'src': 146, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[495] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[496] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[497] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709592521976, 'op': 'memory_read_request'}
instructions[498] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[499] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709592521976, 'op': 'memory_read_wait'}
instructions[500] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139709592521976, 'element_size': 2, 'op': 'memory_read'}
instructions[501] = {6'd0, 8'd141, 8'd0, 32'd16};//{'dest': 141, 'literal': 16, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[502] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[503] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[504] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[505] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[506] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[507] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[508] = {6'd0, 8'd146, 8'd0, 32'd12};//{'dest': 146, 'literal': 12, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[509] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[510] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[511] = {6'd11, 8'd147, 8'd146, 32'd36};//{'dest': 147, 'src': 146, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[512] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[513] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[514] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709592522408, 'op': 'memory_read_request'}
instructions[515] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[516] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709592522408, 'op': 'memory_read_wait'}
instructions[517] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139709592522408, 'element_size': 2, 'op': 'memory_read'}
instructions[518] = {6'd0, 8'd141, 8'd0, 32'd17};//{'dest': 141, 'literal': 17, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[519] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[520] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[521] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[522] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[523] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[524] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[525] = {6'd0, 8'd146, 8'd0, 32'd13};//{'dest': 146, 'literal': 13, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[526] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[527] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[528] = {6'd11, 8'd147, 8'd146, 32'd36};//{'dest': 147, 'src': 146, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[529] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[530] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[531] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709592539288, 'op': 'memory_read_request'}
instructions[532] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[533] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709592539288, 'op': 'memory_read_wait'}
instructions[534] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139709592539288, 'element_size': 2, 'op': 'memory_read'}
instructions[535] = {6'd0, 8'd141, 8'd0, 32'd18};//{'dest': 141, 'literal': 18, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[536] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[537] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[538] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[539] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[540] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[541] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[542] = {6'd0, 8'd146, 8'd0, 32'd14};//{'dest': 146, 'literal': 14, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[543] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[544] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[545] = {6'd11, 8'd147, 8'd146, 32'd36};//{'dest': 147, 'src': 146, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[546] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[547] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[548] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709592539720, 'op': 'memory_read_request'}
instructions[549] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[550] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709592539720, 'op': 'memory_read_wait'}
instructions[551] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139709592539720, 'element_size': 2, 'op': 'memory_read'}
instructions[552] = {6'd0, 8'd141, 8'd0, 32'd19};//{'dest': 141, 'literal': 19, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[553] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[554] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[555] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[556] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[557] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[558] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[559] = {6'd0, 8'd146, 8'd0, 32'd15};//{'dest': 146, 'literal': 15, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[560] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[561] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[562] = {6'd11, 8'd147, 8'd146, 32'd36};//{'dest': 147, 'src': 146, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[563] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[564] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[565] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709592540152, 'op': 'memory_read_request'}
instructions[566] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[567] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709592540152, 'op': 'memory_read_wait'}
instructions[568] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139709592540152, 'element_size': 2, 'op': 'memory_read'}
instructions[569] = {6'd0, 8'd141, 8'd0, 32'd20};//{'dest': 141, 'literal': 20, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[570] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[571] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[572] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[573] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[574] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[575] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[576] = {6'd3, 8'd148, 8'd10, 32'd0};//{'dest': 148, 'src': 10, 'op': 'move'}
instructions[577] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[578] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[579] = {6'd3, 8'd26, 8'd148, 32'd0};//{'dest': 26, 'src': 148, 'op': 'move'}
instructions[580] = {6'd0, 8'd141, 8'd0, 32'd64};//{'dest': 141, 'literal': 64, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[581] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[582] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[583] = {6'd3, 8'd27, 8'd141, 32'd0};//{'dest': 27, 'src': 141, 'op': 'move'}
instructions[584] = {6'd0, 8'd142, 8'd0, 32'd11};//{'dest': 142, 'literal': 11, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[585] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[586] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[587] = {6'd11, 8'd146, 8'd142, 32'd36};//{'dest': 146, 'src': 142, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[588] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[589] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[590] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592549136, 'op': 'memory_read_request'}
instructions[591] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[592] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592549136, 'op': 'memory_read_wait'}
instructions[593] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139709592549136, 'element_size': 2, 'op': 'memory_read'}
instructions[594] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[595] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[596] = {6'd3, 8'd28, 8'd141, 32'd0};//{'dest': 28, 'src': 141, 'op': 'move'}
instructions[597] = {6'd0, 8'd142, 8'd0, 32'd12};//{'dest': 142, 'literal': 12, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[598] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[599] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[600] = {6'd11, 8'd146, 8'd142, 32'd36};//{'dest': 146, 'src': 142, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[601] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[602] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[603] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592549280, 'op': 'memory_read_request'}
instructions[604] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[605] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592549280, 'op': 'memory_read_wait'}
instructions[606] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139709592549280, 'element_size': 2, 'op': 'memory_read'}
instructions[607] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[608] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[609] = {6'd3, 8'd29, 8'd141, 32'd0};//{'dest': 29, 'src': 141, 'op': 'move'}
instructions[610] = {6'd0, 8'd142, 8'd0, 32'd13};//{'dest': 142, 'literal': 13, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[611] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[612] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[613] = {6'd11, 8'd146, 8'd142, 32'd36};//{'dest': 146, 'src': 142, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[614] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[615] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[616] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592549424, 'op': 'memory_read_request'}
instructions[617] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[618] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592549424, 'op': 'memory_read_wait'}
instructions[619] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139709592549424, 'element_size': 2, 'op': 'memory_read'}
instructions[620] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[621] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[622] = {6'd3, 8'd30, 8'd141, 32'd0};//{'dest': 30, 'src': 141, 'op': 'move'}
instructions[623] = {6'd0, 8'd141, 8'd0, 32'd2054};//{'dest': 141, 'literal': 2054, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[624] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[625] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[626] = {6'd3, 8'd31, 8'd141, 32'd0};//{'dest': 31, 'src': 141, 'op': 'move'}
instructions[627] = {6'd1, 8'd25, 8'd0, 32'd218};//{'dest': 25, 'label': 218, 'op': 'jmp_and_link'}
instructions[628] = {6'd15, 8'd0, 8'd0, 32'd629};//{'label': 629, 'op': 'goto'}
instructions[629] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[630] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[631] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[632] = {6'd3, 8'd35, 8'd140, 32'd0};//{'dest': 35, 'src': 140, 'op': 'move'}
instructions[633] = {6'd6, 8'd0, 8'd34, 32'd0};//{'src': 34, 'op': 'jmp_to_reg'}
instructions[634] = {6'd15, 8'd0, 8'd0, 32'd635};//{'label': 635, 'op': 'goto'}
instructions[635] = {6'd3, 8'd140, 8'd37, 32'd0};//{'dest': 140, 'src': 37, 'op': 'move'}
instructions[636] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[637] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[638] = {6'd3, 8'd35, 8'd140, 32'd0};//{'dest': 35, 'src': 140, 'op': 'move'}
instructions[639] = {6'd6, 8'd0, 8'd34, 32'd0};//{'src': 34, 'op': 'jmp_to_reg'}
instructions[640] = {6'd0, 8'd50, 8'd0, 32'd0};//{'dest': 50, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[641] = {6'd0, 8'd51, 8'd0, 32'd0};//{'dest': 51, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[642] = {6'd0, 8'd52, 8'd0, 32'd600};//{'dest': 52, 'literal': 600, 'op': 'literal'}
instructions[643] = {6'd0, 8'd53, 8'd0, 32'd0};//{'dest': 53, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[644] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[645] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[646] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[647] = {6'd3, 8'd53, 8'd140, 32'd0};//{'dest': 53, 'src': 140, 'op': 'move'}
instructions[648] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[649] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[650] = {6'd3, 8'd141, 8'd53, 32'd0};//{'dest': 141, 'src': 53, 'op': 'move'}
instructions[651] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[652] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[653] = {6'd27, 8'd140, 8'd141, 32'd16};//{'src': 141, 'right': 16, 'dest': 140, 'signed': False, 'op': '<', 'type': 'int', 'size': 2}
instructions[654] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[655] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[656] = {6'd13, 8'd0, 8'd140, 32'd700};//{'src': 140, 'label': 700, 'op': 'jmp_if_false'}
instructions[657] = {6'd3, 8'd142, 8'd53, 32'd0};//{'dest': 142, 'src': 53, 'op': 'move'}
instructions[658] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[659] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[660] = {6'd11, 8'd146, 8'd142, 32'd40};//{'dest': 146, 'src': 142, 'srcb': 40, 'signed': False, 'op': '+'}
instructions[661] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[662] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[663] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592549784, 'op': 'memory_read_request'}
instructions[664] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[665] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592549784, 'op': 'memory_read_wait'}
instructions[666] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139709592549784, 'element_size': 2, 'op': 'memory_read'}
instructions[667] = {6'd3, 8'd142, 8'd48, 32'd0};//{'dest': 142, 'src': 48, 'op': 'move'}
instructions[668] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[669] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[670] = {6'd28, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[671] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[672] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[673] = {6'd13, 8'd0, 8'd140, 32'd688};//{'src': 140, 'label': 688, 'op': 'jmp_if_false'}
instructions[674] = {6'd3, 8'd142, 8'd53, 32'd0};//{'dest': 142, 'src': 53, 'op': 'move'}
instructions[675] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[676] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[677] = {6'd11, 8'd146, 8'd142, 32'd41};//{'dest': 146, 'src': 142, 'srcb': 41, 'signed': False, 'op': '+'}
instructions[678] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[679] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[680] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592550072, 'op': 'memory_read_request'}
instructions[681] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[682] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592550072, 'op': 'memory_read_wait'}
instructions[683] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139709592550072, 'element_size': 2, 'op': 'memory_read'}
instructions[684] = {6'd3, 8'd142, 8'd49, 32'd0};//{'dest': 142, 'src': 49, 'op': 'move'}
instructions[685] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[686] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[687] = {6'd28, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[688] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[689] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[690] = {6'd13, 8'd0, 8'd140, 32'd697};//{'src': 140, 'label': 697, 'op': 'jmp_if_false'}
instructions[691] = {6'd3, 8'd140, 8'd53, 32'd0};//{'dest': 140, 'src': 53, 'op': 'move'}
instructions[692] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[693] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[694] = {6'd3, 8'd47, 8'd140, 32'd0};//{'dest': 47, 'src': 140, 'op': 'move'}
instructions[695] = {6'd6, 8'd0, 8'd46, 32'd0};//{'src': 46, 'op': 'jmp_to_reg'}
instructions[696] = {6'd15, 8'd0, 8'd0, 32'd697};//{'label': 697, 'op': 'goto'}
instructions[697] = {6'd3, 8'd140, 8'd53, 32'd0};//{'dest': 140, 'src': 53, 'op': 'move'}
instructions[698] = {6'd14, 8'd53, 8'd53, 32'd1};//{'src': 53, 'right': 1, 'dest': 53, 'signed': False, 'op': '+', 'size': 2}
instructions[699] = {6'd15, 8'd0, 8'd0, 32'd648};//{'label': 648, 'op': 'goto'}
instructions[700] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[701] = {6'd0, 8'd141, 8'd0, 32'd7};//{'dest': 141, 'literal': 7, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[702] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[703] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[704] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[705] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[706] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[707] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[708] = {6'd0, 8'd140, 8'd0, 32'd2048};//{'dest': 140, 'literal': 2048, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[709] = {6'd0, 8'd141, 8'd0, 32'd8};//{'dest': 141, 'literal': 8, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[710] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[711] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[712] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[713] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[714] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[715] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[716] = {6'd0, 8'd140, 8'd0, 32'd1540};//{'dest': 140, 'literal': 1540, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[717] = {6'd0, 8'd141, 8'd0, 32'd9};//{'dest': 141, 'literal': 9, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[718] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[719] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[720] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[721] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[722] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[723] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[724] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[725] = {6'd0, 8'd141, 8'd0, 32'd10};//{'dest': 141, 'literal': 10, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[726] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[727] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[728] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[729] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[730] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[731] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[732] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[733] = {6'd0, 8'd141, 8'd0, 32'd11};//{'dest': 141, 'literal': 11, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[734] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[735] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[736] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[737] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[738] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[739] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[740] = {6'd0, 8'd140, 8'd0, 32'd515};//{'dest': 140, 'literal': 515, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[741] = {6'd0, 8'd141, 8'd0, 32'd12};//{'dest': 141, 'literal': 12, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[742] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[743] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[744] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[745] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[746] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[747] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[748] = {6'd0, 8'd140, 8'd0, 32'd1029};//{'dest': 140, 'literal': 1029, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[749] = {6'd0, 8'd141, 8'd0, 32'd13};//{'dest': 141, 'literal': 13, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[750] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[751] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[752] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[753] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[754] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[755] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[756] = {6'd0, 8'd140, 8'd0, 32'd49320};//{'dest': 140, 'literal': 49320, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[757] = {6'd0, 8'd141, 8'd0, 32'd14};//{'dest': 141, 'literal': 14, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[758] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[759] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[760] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[761] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[762] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[763] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[764] = {6'd0, 8'd140, 8'd0, 32'd119};//{'dest': 140, 'literal': 119, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[765] = {6'd0, 8'd141, 8'd0, 32'd15};//{'dest': 141, 'literal': 15, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[766] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[767] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[768] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[769] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[770] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[771] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[772] = {6'd3, 8'd140, 8'd48, 32'd0};//{'dest': 140, 'src': 48, 'op': 'move'}
instructions[773] = {6'd0, 8'd141, 8'd0, 32'd19};//{'dest': 141, 'literal': 19, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[774] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[775] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[776] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[777] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[778] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[779] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[780] = {6'd3, 8'd140, 8'd49, 32'd0};//{'dest': 140, 'src': 49, 'op': 'move'}
instructions[781] = {6'd0, 8'd141, 8'd0, 32'd20};//{'dest': 141, 'literal': 20, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[782] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[783] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[784] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[785] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[786] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[787] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[788] = {6'd3, 8'd148, 8'd10, 32'd0};//{'dest': 148, 'src': 10, 'op': 'move'}
instructions[789] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[790] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[791] = {6'd3, 8'd26, 8'd148, 32'd0};//{'dest': 26, 'src': 148, 'op': 'move'}
instructions[792] = {6'd0, 8'd141, 8'd0, 32'd64};//{'dest': 141, 'literal': 64, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[793] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[794] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[795] = {6'd3, 8'd27, 8'd141, 32'd0};//{'dest': 27, 'src': 141, 'op': 'move'}
instructions[796] = {6'd0, 8'd141, 8'd0, 32'd65535};//{'dest': 141, 'literal': 65535, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[797] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[798] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[799] = {6'd3, 8'd28, 8'd141, 32'd0};//{'dest': 28, 'src': 141, 'op': 'move'}
instructions[800] = {6'd0, 8'd141, 8'd0, 32'd65535};//{'dest': 141, 'literal': 65535, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[801] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[802] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[803] = {6'd3, 8'd29, 8'd141, 32'd0};//{'dest': 29, 'src': 141, 'op': 'move'}
instructions[804] = {6'd0, 8'd141, 8'd0, 32'd65535};//{'dest': 141, 'literal': 65535, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[805] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[806] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[807] = {6'd3, 8'd30, 8'd141, 32'd0};//{'dest': 30, 'src': 141, 'op': 'move'}
instructions[808] = {6'd0, 8'd141, 8'd0, 32'd2054};//{'dest': 141, 'literal': 2054, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[809] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[810] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[811] = {6'd3, 8'd31, 8'd141, 32'd0};//{'dest': 31, 'src': 141, 'op': 'move'}
instructions[812] = {6'd1, 8'd25, 8'd0, 32'd218};//{'dest': 25, 'label': 218, 'op': 'jmp_and_link'}
instructions[813] = {6'd1, 8'd4, 8'd0, 32'd44};//{'dest': 4, 'label': 44, 'op': 'jmp_and_link'}
instructions[814] = {6'd3, 8'd140, 8'd5, 32'd0};//{'dest': 140, 'src': 5, 'op': 'move'}
instructions[815] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[816] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[817] = {6'd3, 8'd50, 8'd140, 32'd0};//{'dest': 50, 'src': 140, 'op': 'move'}
instructions[818] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[819] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[820] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[821] = {6'd3, 8'd53, 8'd140, 32'd0};//{'dest': 53, 'src': 140, 'op': 'move'}
instructions[822] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[823] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[824] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[825] = {6'd3, 8'd51, 8'd140, 32'd0};//{'dest': 51, 'src': 140, 'op': 'move'}
instructions[826] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[827] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[828] = {6'd3, 8'd141, 8'd51, 32'd0};//{'dest': 141, 'src': 51, 'op': 'move'}
instructions[829] = {6'd3, 8'd142, 8'd50, 32'd0};//{'dest': 142, 'src': 50, 'op': 'move'}
instructions[830] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[831] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[832] = {6'd20, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '<', 'type': 'int', 'size': 2}
instructions[833] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[834] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[835] = {6'd13, 8'd0, 8'd140, 32'd865};//{'src': 140, 'label': 865, 'op': 'jmp_if_false'}
instructions[836] = {6'd3, 8'd141, 8'd53, 32'd0};//{'dest': 141, 'src': 53, 'op': 'move'}
instructions[837] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[838] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[839] = {6'd27, 8'd140, 8'd141, 32'd16};//{'src': 141, 'right': 16, 'dest': 140, 'signed': False, 'op': '<', 'type': 'int', 'size': 2}
instructions[840] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[841] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[842] = {6'd13, 8'd0, 8'd140, 32'd853};//{'src': 140, 'label': 853, 'op': 'jmp_if_false'}
instructions[843] = {6'd1, 8'd4, 8'd0, 32'd44};//{'dest': 4, 'label': 44, 'op': 'jmp_and_link'}
instructions[844] = {6'd3, 8'd140, 8'd5, 32'd0};//{'dest': 140, 'src': 5, 'op': 'move'}
instructions[845] = {6'd3, 8'd141, 8'd53, 32'd0};//{'dest': 141, 'src': 53, 'op': 'move'}
instructions[846] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[847] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[848] = {6'd11, 8'd142, 8'd141, 32'd52};//{'dest': 142, 'src': 141, 'srcb': 52, 'signed': False, 'op': '+'}
instructions[849] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[850] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[851] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[852] = {6'd15, 8'd0, 8'd0, 32'd855};//{'label': 855, 'op': 'goto'}
instructions[853] = {6'd1, 8'd4, 8'd0, 32'd44};//{'dest': 4, 'label': 44, 'op': 'jmp_and_link'}
instructions[854] = {6'd3, 8'd140, 8'd5, 32'd0};//{'dest': 140, 'src': 5, 'op': 'move'}
instructions[855] = {6'd3, 8'd140, 8'd53, 32'd0};//{'dest': 140, 'src': 53, 'op': 'move'}
instructions[856] = {6'd14, 8'd53, 8'd53, 32'd1};//{'src': 53, 'right': 1, 'dest': 53, 'signed': False, 'op': '+', 'size': 2}
instructions[857] = {6'd3, 8'd141, 8'd51, 32'd0};//{'dest': 141, 'src': 51, 'op': 'move'}
instructions[858] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[859] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[860] = {6'd14, 8'd140, 8'd141, 32'd2};//{'src': 141, 'right': 2, 'dest': 140, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[861] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[862] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[863] = {6'd3, 8'd51, 8'd140, 32'd0};//{'dest': 51, 'src': 140, 'op': 'move'}
instructions[864] = {6'd15, 8'd0, 8'd0, 32'd826};//{'label': 826, 'op': 'goto'}
instructions[865] = {6'd0, 8'd142, 8'd0, 32'd6};//{'dest': 142, 'literal': 6, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[866] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[867] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[868] = {6'd11, 8'd146, 8'd142, 32'd52};//{'dest': 146, 'src': 142, 'srcb': 52, 'signed': False, 'op': '+'}
instructions[869] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[870] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[871] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592600232, 'op': 'memory_read_request'}
instructions[872] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[873] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592600232, 'op': 'memory_read_wait'}
instructions[874] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139709592600232, 'element_size': 2, 'op': 'memory_read'}
instructions[875] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[876] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[877] = {6'd25, 8'd140, 8'd141, 32'd2054};//{'src': 141, 'right': 2054, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[878] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[879] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[880] = {6'd13, 8'd0, 8'd140, 32'd894};//{'src': 140, 'label': 894, 'op': 'jmp_if_false'}
instructions[881] = {6'd0, 8'd142, 8'd0, 32'd10};//{'dest': 142, 'literal': 10, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[882] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[883] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[884] = {6'd11, 8'd146, 8'd142, 32'd52};//{'dest': 146, 'src': 142, 'srcb': 52, 'signed': False, 'op': '+'}
instructions[885] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[886] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[887] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592600520, 'op': 'memory_read_request'}
instructions[888] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[889] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592600520, 'op': 'memory_read_wait'}
instructions[890] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139709592600520, 'element_size': 2, 'op': 'memory_read'}
instructions[891] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[892] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[893] = {6'd25, 8'd140, 8'd141, 32'd2};//{'src': 141, 'right': 2, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[894] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[895] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[896] = {6'd13, 8'd0, 8'd140, 32'd1025};//{'src': 140, 'label': 1025, 'op': 'jmp_if_false'}
instructions[897] = {6'd0, 8'd142, 8'd0, 32'd14};//{'dest': 142, 'literal': 14, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[898] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[899] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[900] = {6'd11, 8'd146, 8'd142, 32'd52};//{'dest': 146, 'src': 142, 'srcb': 52, 'signed': False, 'op': '+'}
instructions[901] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[902] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[903] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592613448, 'op': 'memory_read_request'}
instructions[904] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[905] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592613448, 'op': 'memory_read_wait'}
instructions[906] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139709592613448, 'element_size': 2, 'op': 'memory_read'}
instructions[907] = {6'd3, 8'd142, 8'd48, 32'd0};//{'dest': 142, 'src': 48, 'op': 'move'}
instructions[908] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[909] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[910] = {6'd28, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[911] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[912] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[913] = {6'd13, 8'd0, 8'd140, 32'd928};//{'src': 140, 'label': 928, 'op': 'jmp_if_false'}
instructions[914] = {6'd0, 8'd142, 8'd0, 32'd15};//{'dest': 142, 'literal': 15, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[915] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[916] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[917] = {6'd11, 8'd146, 8'd142, 32'd52};//{'dest': 146, 'src': 142, 'srcb': 52, 'signed': False, 'op': '+'}
instructions[918] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[919] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[920] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592613736, 'op': 'memory_read_request'}
instructions[921] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[922] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592613736, 'op': 'memory_read_wait'}
instructions[923] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139709592613736, 'element_size': 2, 'op': 'memory_read'}
instructions[924] = {6'd3, 8'd142, 8'd49, 32'd0};//{'dest': 142, 'src': 49, 'op': 'move'}
instructions[925] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[926] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[927] = {6'd28, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[928] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[929] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[930] = {6'd13, 8'd0, 8'd140, 32'd1024};//{'src': 140, 'label': 1024, 'op': 'jmp_if_false'}
instructions[931] = {6'd3, 8'd140, 8'd48, 32'd0};//{'dest': 140, 'src': 48, 'op': 'move'}
instructions[932] = {6'd3, 8'd141, 8'd45, 32'd0};//{'dest': 141, 'src': 45, 'op': 'move'}
instructions[933] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[934] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[935] = {6'd11, 8'd142, 8'd141, 32'd40};//{'dest': 142, 'src': 141, 'srcb': 40, 'signed': False, 'op': '+'}
instructions[936] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[937] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[938] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[939] = {6'd3, 8'd140, 8'd49, 32'd0};//{'dest': 140, 'src': 49, 'op': 'move'}
instructions[940] = {6'd3, 8'd141, 8'd45, 32'd0};//{'dest': 141, 'src': 45, 'op': 'move'}
instructions[941] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[942] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[943] = {6'd11, 8'd142, 8'd141, 32'd41};//{'dest': 142, 'src': 141, 'srcb': 41, 'signed': False, 'op': '+'}
instructions[944] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[945] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[946] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[947] = {6'd0, 8'd146, 8'd0, 32'd11};//{'dest': 146, 'literal': 11, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[948] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[949] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[950] = {6'd11, 8'd147, 8'd146, 32'd52};//{'dest': 147, 'src': 146, 'srcb': 52, 'signed': False, 'op': '+'}
instructions[951] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[952] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[953] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709592615104, 'op': 'memory_read_request'}
instructions[954] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[955] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709592615104, 'op': 'memory_read_wait'}
instructions[956] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139709592615104, 'element_size': 2, 'op': 'memory_read'}
instructions[957] = {6'd3, 8'd141, 8'd45, 32'd0};//{'dest': 141, 'src': 45, 'op': 'move'}
instructions[958] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[959] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[960] = {6'd11, 8'd142, 8'd141, 32'd42};//{'dest': 142, 'src': 141, 'srcb': 42, 'signed': False, 'op': '+'}
instructions[961] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[962] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[963] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[964] = {6'd0, 8'd146, 8'd0, 32'd12};//{'dest': 146, 'literal': 12, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[965] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[966] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[967] = {6'd11, 8'd147, 8'd146, 32'd52};//{'dest': 147, 'src': 146, 'srcb': 52, 'signed': False, 'op': '+'}
instructions[968] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[969] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[970] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709592615536, 'op': 'memory_read_request'}
instructions[971] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[972] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709592615536, 'op': 'memory_read_wait'}
instructions[973] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139709592615536, 'element_size': 2, 'op': 'memory_read'}
instructions[974] = {6'd3, 8'd141, 8'd45, 32'd0};//{'dest': 141, 'src': 45, 'op': 'move'}
instructions[975] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[976] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[977] = {6'd11, 8'd142, 8'd141, 32'd43};//{'dest': 142, 'src': 141, 'srcb': 43, 'signed': False, 'op': '+'}
instructions[978] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[979] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[980] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[981] = {6'd0, 8'd146, 8'd0, 32'd13};//{'dest': 146, 'literal': 13, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[982] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[983] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[984] = {6'd11, 8'd147, 8'd146, 32'd52};//{'dest': 147, 'src': 146, 'srcb': 52, 'signed': False, 'op': '+'}
instructions[985] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[986] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[987] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709592615968, 'op': 'memory_read_request'}
instructions[988] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[989] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709592615968, 'op': 'memory_read_wait'}
instructions[990] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139709592615968, 'element_size': 2, 'op': 'memory_read'}
instructions[991] = {6'd3, 8'd141, 8'd45, 32'd0};//{'dest': 141, 'src': 45, 'op': 'move'}
instructions[992] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[993] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[994] = {6'd11, 8'd142, 8'd141, 32'd44};//{'dest': 142, 'src': 141, 'srcb': 44, 'signed': False, 'op': '+'}
instructions[995] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[996] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[997] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[998] = {6'd3, 8'd140, 8'd45, 32'd0};//{'dest': 140, 'src': 45, 'op': 'move'}
instructions[999] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1000] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1001] = {6'd3, 8'd53, 8'd140, 32'd0};//{'dest': 53, 'src': 140, 'op': 'move'}
instructions[1002] = {6'd3, 8'd140, 8'd45, 32'd0};//{'dest': 140, 'src': 45, 'op': 'move'}
instructions[1003] = {6'd14, 8'd45, 8'd45, 32'd1};//{'src': 45, 'right': 1, 'dest': 45, 'signed': False, 'op': '+', 'size': 2}
instructions[1004] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1005] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1006] = {6'd3, 8'd141, 8'd45, 32'd0};//{'dest': 141, 'src': 45, 'op': 'move'}
instructions[1007] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1008] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1009] = {6'd25, 8'd140, 8'd141, 32'd16};//{'src': 141, 'right': 16, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[1010] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1011] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1012] = {6'd13, 8'd0, 8'd140, 32'd1018};//{'src': 140, 'label': 1018, 'op': 'jmp_if_false'}
instructions[1013] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1014] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1015] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1016] = {6'd3, 8'd45, 8'd140, 32'd0};//{'dest': 45, 'src': 140, 'op': 'move'}
instructions[1017] = {6'd15, 8'd0, 8'd0, 32'd1018};//{'label': 1018, 'op': 'goto'}
instructions[1018] = {6'd3, 8'd140, 8'd53, 32'd0};//{'dest': 140, 'src': 53, 'op': 'move'}
instructions[1019] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1020] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1021] = {6'd3, 8'd47, 8'd140, 32'd0};//{'dest': 47, 'src': 140, 'op': 'move'}
instructions[1022] = {6'd6, 8'd0, 8'd46, 32'd0};//{'src': 46, 'op': 'jmp_to_reg'}
instructions[1023] = {6'd15, 8'd0, 8'd0, 32'd1024};//{'label': 1024, 'op': 'goto'}
instructions[1024] = {6'd15, 8'd0, 8'd0, 32'd1025};//{'label': 1025, 'op': 'goto'}
instructions[1025] = {6'd15, 8'd0, 8'd0, 32'd813};//{'label': 813, 'op': 'goto'}
instructions[1026] = {6'd0, 8'd60, 8'd0, 32'd0};//{'dest': 60, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1027] = {6'd0, 8'd61, 8'd0, 32'd0};//{'dest': 61, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1028] = {6'd0, 8'd62, 8'd0, 32'd0};//{'dest': 62, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1029] = {6'd3, 8'd141, 8'd58, 32'd0};//{'dest': 141, 'src': 58, 'op': 'move'}
instructions[1030] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1031] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1032] = {6'd3, 8'd48, 8'd141, 32'd0};//{'dest': 48, 'src': 141, 'op': 'move'}
instructions[1033] = {6'd3, 8'd141, 8'd59, 32'd0};//{'dest': 141, 'src': 59, 'op': 'move'}
instructions[1034] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1035] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1036] = {6'd3, 8'd49, 8'd141, 32'd0};//{'dest': 49, 'src': 141, 'op': 'move'}
instructions[1037] = {6'd1, 8'd46, 8'd0, 32'd640};//{'dest': 46, 'label': 640, 'op': 'jmp_and_link'}
instructions[1038] = {6'd3, 8'd140, 8'd47, 32'd0};//{'dest': 140, 'src': 47, 'op': 'move'}
instructions[1039] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1040] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1041] = {6'd3, 8'd62, 8'd140, 32'd0};//{'dest': 62, 'src': 140, 'op': 'move'}
instructions[1042] = {6'd0, 8'd140, 8'd0, 32'd17664};//{'dest': 140, 'literal': 17664, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1043] = {6'd0, 8'd141, 8'd0, 32'd7};//{'dest': 141, 'literal': 7, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1044] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1045] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1046] = {6'd26, 8'd142, 8'd141, 32'd55};//{'dest': 142, 'src': 141, 'srcb': 55, 'signed': True, 'op': '+'}
instructions[1047] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1048] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1049] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1050] = {6'd3, 8'd140, 8'd56, 32'd0};//{'dest': 140, 'src': 56, 'op': 'move'}
instructions[1051] = {6'd0, 8'd141, 8'd0, 32'd8};//{'dest': 141, 'literal': 8, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1052] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1053] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1054] = {6'd11, 8'd142, 8'd141, 32'd55};//{'dest': 142, 'src': 141, 'srcb': 55, 'signed': False, 'op': '+'}
instructions[1055] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1056] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1057] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1058] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1059] = {6'd0, 8'd141, 8'd0, 32'd9};//{'dest': 141, 'literal': 9, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1060] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1061] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1062] = {6'd26, 8'd142, 8'd141, 32'd55};//{'dest': 142, 'src': 141, 'srcb': 55, 'signed': True, 'op': '+'}
instructions[1063] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1064] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1065] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1066] = {6'd0, 8'd140, 8'd0, 32'd16384};//{'dest': 140, 'literal': 16384, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1067] = {6'd0, 8'd141, 8'd0, 32'd10};//{'dest': 141, 'literal': 10, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1068] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1069] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1070] = {6'd26, 8'd142, 8'd141, 32'd55};//{'dest': 142, 'src': 141, 'srcb': 55, 'signed': True, 'op': '+'}
instructions[1071] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1072] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1073] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1074] = {6'd3, 8'd146, 8'd57, 32'd0};//{'dest': 146, 'src': 57, 'op': 'move'}
instructions[1075] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1076] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1077] = {6'd29, 8'd140, 8'd146, 32'd65280};//{'src': 146, 'dest': 140, 'signed': False, 'op': '|', 'size': 2, 'type': 'int', 'left': 65280}
instructions[1078] = {6'd0, 8'd141, 8'd0, 32'd11};//{'dest': 141, 'literal': 11, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1079] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1080] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1081] = {6'd11, 8'd142, 8'd141, 32'd55};//{'dest': 142, 'src': 141, 'srcb': 55, 'signed': False, 'op': '+'}
instructions[1082] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1083] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1084] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1085] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1086] = {6'd0, 8'd141, 8'd0, 32'd12};//{'dest': 141, 'literal': 12, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1087] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1088] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1089] = {6'd26, 8'd142, 8'd141, 32'd55};//{'dest': 142, 'src': 141, 'srcb': 55, 'signed': True, 'op': '+'}
instructions[1090] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1091] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1092] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1093] = {6'd0, 8'd140, 8'd0, 32'd49320};//{'dest': 140, 'literal': 49320, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1094] = {6'd0, 8'd141, 8'd0, 32'd13};//{'dest': 141, 'literal': 13, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1095] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1096] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1097] = {6'd11, 8'd142, 8'd141, 32'd55};//{'dest': 142, 'src': 141, 'srcb': 55, 'signed': False, 'op': '+'}
instructions[1098] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1099] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1100] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1101] = {6'd0, 8'd140, 8'd0, 32'd119};//{'dest': 140, 'literal': 119, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1102] = {6'd0, 8'd141, 8'd0, 32'd14};//{'dest': 141, 'literal': 14, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1103] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1104] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1105] = {6'd11, 8'd142, 8'd141, 32'd55};//{'dest': 142, 'src': 141, 'srcb': 55, 'signed': False, 'op': '+'}
instructions[1106] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1107] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1108] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1109] = {6'd3, 8'd140, 8'd58, 32'd0};//{'dest': 140, 'src': 58, 'op': 'move'}
instructions[1110] = {6'd0, 8'd141, 8'd0, 32'd15};//{'dest': 141, 'literal': 15, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1111] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1112] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1113] = {6'd11, 8'd142, 8'd141, 32'd55};//{'dest': 142, 'src': 141, 'srcb': 55, 'signed': False, 'op': '+'}
instructions[1114] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1115] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1116] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1117] = {6'd3, 8'd140, 8'd59, 32'd0};//{'dest': 140, 'src': 59, 'op': 'move'}
instructions[1118] = {6'd0, 8'd141, 8'd0, 32'd16};//{'dest': 141, 'literal': 16, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1119] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1120] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1121] = {6'd11, 8'd142, 8'd141, 32'd55};//{'dest': 142, 'src': 141, 'srcb': 55, 'signed': False, 'op': '+'}
instructions[1122] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1123] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1124] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1125] = {6'd3, 8'd141, 8'd56, 32'd0};//{'dest': 141, 'src': 56, 'op': 'move'}
instructions[1126] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1127] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1128] = {6'd14, 8'd140, 8'd141, 32'd14};//{'src': 141, 'right': 14, 'dest': 140, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1129] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1130] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1131] = {6'd3, 8'd60, 8'd140, 32'd0};//{'dest': 60, 'src': 140, 'op': 'move'}
instructions[1132] = {6'd1, 8'd12, 8'd0, 32'd59};//{'dest': 12, 'label': 59, 'op': 'jmp_and_link'}
instructions[1133] = {6'd0, 8'd140, 8'd0, 32'd7};//{'dest': 140, 'literal': 7, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1134] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1135] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1136] = {6'd3, 8'd61, 8'd140, 32'd0};//{'dest': 61, 'src': 140, 'op': 'move'}
instructions[1137] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1138] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1139] = {6'd3, 8'd141, 8'd61, 32'd0};//{'dest': 141, 'src': 61, 'op': 'move'}
instructions[1140] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1141] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1142] = {6'd30, 8'd140, 8'd141, 32'd16};//{'src': 141, 'right': 16, 'dest': 140, 'signed': False, 'op': '<=', 'type': 'int', 'size': 2}
instructions[1143] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1144] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1145] = {6'd13, 8'd0, 8'd140, 32'd1163};//{'src': 140, 'label': 1163, 'op': 'jmp_if_false'}
instructions[1146] = {6'd3, 8'd142, 8'd61, 32'd0};//{'dest': 142, 'src': 61, 'op': 'move'}
instructions[1147] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1148] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1149] = {6'd11, 8'd146, 8'd142, 32'd55};//{'dest': 146, 'src': 142, 'srcb': 55, 'signed': False, 'op': '+'}
instructions[1150] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1151] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1152] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592674248, 'op': 'memory_read_request'}
instructions[1153] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1154] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592674248, 'op': 'memory_read_wait'}
instructions[1155] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139709592674248, 'element_size': 2, 'op': 'memory_read'}
instructions[1156] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1157] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1158] = {6'd3, 8'd14, 8'd141, 32'd0};//{'dest': 14, 'src': 141, 'op': 'move'}
instructions[1159] = {6'd1, 8'd13, 8'd0, 32'd64};//{'dest': 13, 'label': 64, 'op': 'jmp_and_link'}
instructions[1160] = {6'd3, 8'd140, 8'd61, 32'd0};//{'dest': 140, 'src': 61, 'op': 'move'}
instructions[1161] = {6'd14, 8'd61, 8'd61, 32'd1};//{'src': 61, 'right': 1, 'dest': 61, 'signed': False, 'op': '+', 'size': 2}
instructions[1162] = {6'd15, 8'd0, 8'd0, 32'd1137};//{'label': 1137, 'op': 'goto'}
instructions[1163] = {6'd1, 8'd15, 8'd0, 32'd100};//{'dest': 15, 'label': 100, 'op': 'jmp_and_link'}
instructions[1164] = {6'd3, 8'd140, 8'd16, 32'd0};//{'dest': 140, 'src': 16, 'op': 'move'}
instructions[1165] = {6'd0, 8'd141, 8'd0, 32'd12};//{'dest': 141, 'literal': 12, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1166] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1167] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1168] = {6'd11, 8'd142, 8'd141, 32'd55};//{'dest': 142, 'src': 141, 'srcb': 55, 'signed': False, 'op': '+'}
instructions[1169] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1170] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1171] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1172] = {6'd3, 8'd141, 8'd60, 32'd0};//{'dest': 141, 'src': 60, 'op': 'move'}
instructions[1173] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1174] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1175] = {6'd27, 8'd140, 8'd141, 32'd64};//{'src': 141, 'right': 64, 'dest': 140, 'signed': False, 'op': '<', 'type': 'int', 'size': 2}
instructions[1176] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1177] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1178] = {6'd13, 8'd0, 8'd140, 32'd1184};//{'src': 140, 'label': 1184, 'op': 'jmp_if_false'}
instructions[1179] = {6'd0, 8'd140, 8'd0, 32'd64};//{'dest': 140, 'literal': 64, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1180] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1181] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1182] = {6'd3, 8'd60, 8'd140, 32'd0};//{'dest': 60, 'src': 140, 'op': 'move'}
instructions[1183] = {6'd15, 8'd0, 8'd0, 32'd1184};//{'label': 1184, 'op': 'goto'}
instructions[1184] = {6'd3, 8'd143, 8'd55, 32'd0};//{'dest': 143, 'src': 55, 'op': 'move'}
instructions[1185] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1186] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1187] = {6'd3, 8'd26, 8'd143, 32'd0};//{'dest': 26, 'src': 143, 'op': 'move'}
instructions[1188] = {6'd3, 8'd141, 8'd60, 32'd0};//{'dest': 141, 'src': 60, 'op': 'move'}
instructions[1189] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1190] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1191] = {6'd3, 8'd27, 8'd141, 32'd0};//{'dest': 27, 'src': 141, 'op': 'move'}
instructions[1192] = {6'd3, 8'd142, 8'd62, 32'd0};//{'dest': 142, 'src': 62, 'op': 'move'}
instructions[1193] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1194] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1195] = {6'd11, 8'd146, 8'd142, 32'd42};//{'dest': 146, 'src': 142, 'srcb': 42, 'signed': False, 'op': '+'}
instructions[1196] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1197] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1198] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592684232, 'op': 'memory_read_request'}
instructions[1199] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1200] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592684232, 'op': 'memory_read_wait'}
instructions[1201] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139709592684232, 'element_size': 2, 'op': 'memory_read'}
instructions[1202] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1203] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1204] = {6'd3, 8'd28, 8'd141, 32'd0};//{'dest': 28, 'src': 141, 'op': 'move'}
instructions[1205] = {6'd3, 8'd142, 8'd62, 32'd0};//{'dest': 142, 'src': 62, 'op': 'move'}
instructions[1206] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1207] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1208] = {6'd11, 8'd146, 8'd142, 32'd43};//{'dest': 146, 'src': 142, 'srcb': 43, 'signed': False, 'op': '+'}
instructions[1209] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1210] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1211] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592684376, 'op': 'memory_read_request'}
instructions[1212] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1213] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592684376, 'op': 'memory_read_wait'}
instructions[1214] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139709592684376, 'element_size': 2, 'op': 'memory_read'}
instructions[1215] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1216] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1217] = {6'd3, 8'd29, 8'd141, 32'd0};//{'dest': 29, 'src': 141, 'op': 'move'}
instructions[1218] = {6'd3, 8'd142, 8'd62, 32'd0};//{'dest': 142, 'src': 62, 'op': 'move'}
instructions[1219] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1220] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1221] = {6'd11, 8'd146, 8'd142, 32'd44};//{'dest': 146, 'src': 142, 'srcb': 44, 'signed': False, 'op': '+'}
instructions[1222] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1223] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1224] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592684520, 'op': 'memory_read_request'}
instructions[1225] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1226] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592684520, 'op': 'memory_read_wait'}
instructions[1227] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139709592684520, 'element_size': 2, 'op': 'memory_read'}
instructions[1228] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1229] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1230] = {6'd3, 8'd30, 8'd141, 32'd0};//{'dest': 30, 'src': 141, 'op': 'move'}
instructions[1231] = {6'd0, 8'd141, 8'd0, 32'd2048};//{'dest': 141, 'literal': 2048, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1232] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1233] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1234] = {6'd3, 8'd31, 8'd141, 32'd0};//{'dest': 31, 'src': 141, 'op': 'move'}
instructions[1235] = {6'd1, 8'd25, 8'd0, 32'd218};//{'dest': 25, 'label': 218, 'op': 'jmp_and_link'}
instructions[1236] = {6'd6, 8'd0, 8'd54, 32'd0};//{'src': 54, 'op': 'jmp_to_reg'}
instructions[1237] = {6'd0, 8'd66, 8'd0, 32'd0};//{'dest': 66, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1238] = {6'd0, 8'd67, 8'd0, 32'd0};//{'dest': 67, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1239] = {6'd0, 8'd68, 8'd0, 32'd0};//{'dest': 68, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1240] = {6'd0, 8'd69, 8'd0, 32'd0};//{'dest': 69, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1241] = {6'd0, 8'd70, 8'd0, 32'd0};//{'dest': 70, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1242] = {6'd0, 8'd71, 8'd0, 32'd0};//{'dest': 71, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1243] = {6'd0, 8'd72, 8'd0, 32'd0};//{'dest': 72, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1244] = {6'd0, 8'd73, 8'd0, 32'd0};//{'dest': 73, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1245] = {6'd0, 8'd74, 8'd0, 32'd0};//{'dest': 74, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1246] = {6'd3, 8'd143, 8'd65, 32'd0};//{'dest': 143, 'src': 65, 'op': 'move'}
instructions[1247] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1248] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1249] = {6'd3, 8'd36, 8'd143, 32'd0};//{'dest': 36, 'src': 143, 'op': 'move'}
instructions[1250] = {6'd1, 8'd34, 8'd0, 32'd328};//{'dest': 34, 'label': 328, 'op': 'jmp_and_link'}
instructions[1251] = {6'd3, 8'd140, 8'd35, 32'd0};//{'dest': 140, 'src': 35, 'op': 'move'}
instructions[1252] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1253] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1254] = {6'd3, 8'd74, 8'd140, 32'd0};//{'dest': 74, 'src': 140, 'op': 'move'}
instructions[1255] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1256] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1257] = {6'd3, 8'd141, 8'd74, 32'd0};//{'dest': 141, 'src': 74, 'op': 'move'}
instructions[1258] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1259] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1260] = {6'd25, 8'd140, 8'd141, 32'd0};//{'src': 141, 'right': 0, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[1261] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1262] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1263] = {6'd13, 8'd0, 8'd140, 32'd1270};//{'src': 140, 'label': 1270, 'op': 'jmp_if_false'}
instructions[1264] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1265] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1266] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1267] = {6'd3, 8'd64, 8'd140, 32'd0};//{'dest': 64, 'src': 140, 'op': 'move'}
instructions[1268] = {6'd6, 8'd0, 8'd63, 32'd0};//{'src': 63, 'op': 'jmp_to_reg'}
instructions[1269] = {6'd15, 8'd0, 8'd0, 32'd1270};//{'label': 1270, 'op': 'goto'}
instructions[1270] = {6'd0, 8'd142, 8'd0, 32'd6};//{'dest': 142, 'literal': 6, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1271] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1272] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1273] = {6'd11, 8'd146, 8'd142, 32'd65};//{'dest': 146, 'src': 142, 'srcb': 65, 'signed': False, 'op': '+'}
instructions[1274] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1275] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1276] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592685240, 'op': 'memory_read_request'}
instructions[1277] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1278] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592685240, 'op': 'memory_read_wait'}
instructions[1279] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139709592685240, 'element_size': 2, 'op': 'memory_read'}
instructions[1280] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1281] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1282] = {6'd31, 8'd140, 8'd141, 32'd2048};//{'src': 141, 'right': 2048, 'dest': 140, 'signed': False, 'op': '!=', 'type': 'int', 'size': 2}
instructions[1283] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1284] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1285] = {6'd13, 8'd0, 8'd140, 32'd1292};//{'src': 140, 'label': 1292, 'op': 'jmp_if_false'}
instructions[1286] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1287] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1288] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1289] = {6'd3, 8'd64, 8'd140, 32'd0};//{'dest': 64, 'src': 140, 'op': 'move'}
instructions[1290] = {6'd6, 8'd0, 8'd63, 32'd0};//{'src': 63, 'op': 'jmp_to_reg'}
instructions[1291] = {6'd15, 8'd0, 8'd0, 32'd1292};//{'label': 1292, 'op': 'goto'}
instructions[1292] = {6'd0, 8'd142, 8'd0, 32'd15};//{'dest': 142, 'literal': 15, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1293] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1294] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1295] = {6'd11, 8'd146, 8'd142, 32'd65};//{'dest': 146, 'src': 142, 'srcb': 65, 'signed': False, 'op': '+'}
instructions[1296] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1297] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1298] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592685744, 'op': 'memory_read_request'}
instructions[1299] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1300] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592685744, 'op': 'memory_read_wait'}
instructions[1301] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139709592685744, 'element_size': 2, 'op': 'memory_read'}
instructions[1302] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1303] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1304] = {6'd31, 8'd140, 8'd141, 32'd49320};//{'src': 141, 'right': 49320, 'dest': 140, 'signed': False, 'op': '!=', 'type': 'int', 'size': 2}
instructions[1305] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1306] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1307] = {6'd13, 8'd0, 8'd140, 32'd1314};//{'src': 140, 'label': 1314, 'op': 'jmp_if_false'}
instructions[1308] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1309] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1310] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1311] = {6'd3, 8'd64, 8'd140, 32'd0};//{'dest': 64, 'src': 140, 'op': 'move'}
instructions[1312] = {6'd6, 8'd0, 8'd63, 32'd0};//{'src': 63, 'op': 'jmp_to_reg'}
instructions[1313] = {6'd15, 8'd0, 8'd0, 32'd1314};//{'label': 1314, 'op': 'goto'}
instructions[1314] = {6'd0, 8'd142, 8'd0, 32'd16};//{'dest': 142, 'literal': 16, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1315] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1316] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1317] = {6'd11, 8'd146, 8'd142, 32'd65};//{'dest': 146, 'src': 142, 'srcb': 65, 'signed': False, 'op': '+'}
instructions[1318] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1319] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1320] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592686248, 'op': 'memory_read_request'}
instructions[1321] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1322] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592686248, 'op': 'memory_read_wait'}
instructions[1323] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139709592686248, 'element_size': 2, 'op': 'memory_read'}
instructions[1324] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1325] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1326] = {6'd31, 8'd140, 8'd141, 32'd119};//{'src': 141, 'right': 119, 'dest': 140, 'signed': False, 'op': '!=', 'type': 'int', 'size': 2}
instructions[1327] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1328] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1329] = {6'd13, 8'd0, 8'd140, 32'd1336};//{'src': 140, 'label': 1336, 'op': 'jmp_if_false'}
instructions[1330] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1331] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1332] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1333] = {6'd3, 8'd64, 8'd140, 32'd0};//{'dest': 64, 'src': 140, 'op': 'move'}
instructions[1334] = {6'd6, 8'd0, 8'd63, 32'd0};//{'src': 63, 'op': 'jmp_to_reg'}
instructions[1335] = {6'd15, 8'd0, 8'd0, 32'd1336};//{'label': 1336, 'op': 'goto'}
instructions[1336] = {6'd0, 8'd146, 8'd0, 32'd11};//{'dest': 146, 'literal': 11, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1337] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1338] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1339] = {6'd11, 8'd147, 8'd146, 32'd65};//{'dest': 147, 'src': 146, 'srcb': 65, 'signed': False, 'op': '+'}
instructions[1340] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1341] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1342] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709592707440, 'op': 'memory_read_request'}
instructions[1343] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1344] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709592707440, 'op': 'memory_read_wait'}
instructions[1345] = {6'd19, 8'd142, 8'd147, 32'd0};//{'dest': 142, 'src': 147, 'sequence': 139709592707440, 'element_size': 2, 'op': 'memory_read'}
instructions[1346] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1347] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1348] = {6'd12, 8'd141, 8'd142, 32'd255};//{'src': 142, 'right': 255, 'dest': 141, 'signed': False, 'op': '&', 'type': 'int', 'size': 2}
instructions[1349] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1350] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1351] = {6'd25, 8'd140, 8'd141, 32'd1};//{'src': 141, 'right': 1, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[1352] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1353] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1354] = {6'd13, 8'd0, 8'd140, 32'd1561};//{'src': 140, 'label': 1561, 'op': 'jmp_if_false'}
instructions[1355] = {6'd0, 8'd147, 8'd0, 32'd7};//{'dest': 147, 'literal': 7, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1356] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1357] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1358] = {6'd11, 8'd149, 8'd147, 32'd65};//{'dest': 149, 'src': 147, 'srcb': 65, 'signed': False, 'op': '+'}
instructions[1359] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1360] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1361] = {6'd17, 8'd0, 8'd149, 32'd0};//{'element_size': 2, 'src': 149, 'sequence': 139709592716424, 'op': 'memory_read_request'}
instructions[1362] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1363] = {6'd18, 8'd0, 8'd149, 32'd0};//{'element_size': 2, 'src': 149, 'sequence': 139709592716424, 'op': 'memory_read_wait'}
instructions[1364] = {6'd19, 8'd146, 8'd149, 32'd0};//{'dest': 146, 'src': 149, 'sequence': 139709592716424, 'element_size': 2, 'op': 'memory_read'}
instructions[1365] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1366] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1367] = {6'd32, 8'd142, 8'd146, 32'd8};//{'src': 146, 'right': 8, 'dest': 142, 'signed': False, 'op': '>>', 'type': 'int', 'size': 2}
instructions[1368] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1369] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1370] = {6'd12, 8'd141, 8'd142, 32'd15};//{'src': 142, 'right': 15, 'dest': 141, 'signed': False, 'op': '&', 'type': 'int', 'size': 2}
instructions[1371] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1372] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1373] = {6'd33, 8'd140, 8'd141, 32'd1};//{'src': 141, 'right': 1, 'dest': 140, 'signed': False, 'op': '<<', 'type': 'int', 'size': 2}
instructions[1374] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1375] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1376] = {6'd3, 8'd67, 8'd140, 32'd0};//{'dest': 67, 'src': 140, 'op': 'move'}
instructions[1377] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1378] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1379] = {6'd3, 8'd141, 8'd67, 32'd0};//{'dest': 141, 'src': 67, 'op': 'move'}
instructions[1380] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1381] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1382] = {6'd14, 8'd140, 8'd141, 32'd7};//{'src': 141, 'right': 7, 'dest': 140, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1383] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1384] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1385] = {6'd3, 8'd68, 8'd140, 32'd0};//{'dest': 68, 'src': 140, 'op': 'move'}
instructions[1386] = {6'd0, 8'd141, 8'd0, 32'd8};//{'dest': 141, 'literal': 8, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1387] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1388] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1389] = {6'd11, 8'd142, 8'd141, 32'd65};//{'dest': 142, 'src': 141, 'srcb': 65, 'signed': False, 'op': '+'}
instructions[1390] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1391] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1392] = {6'd17, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 139709593443864, 'op': 'memory_read_request'}
instructions[1393] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1394] = {6'd18, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 139709593443864, 'op': 'memory_read_wait'}
instructions[1395] = {6'd19, 8'd140, 8'd142, 32'd0};//{'dest': 140, 'src': 142, 'sequence': 139709593443864, 'element_size': 2, 'op': 'memory_read'}
instructions[1396] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1397] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1398] = {6'd3, 8'd66, 8'd140, 32'd0};//{'dest': 66, 'src': 140, 'op': 'move'}
instructions[1399] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1400] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1401] = {6'd3, 8'd146, 8'd66, 32'd0};//{'dest': 146, 'src': 66, 'op': 'move'}
instructions[1402] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1403] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1404] = {6'd14, 8'd142, 8'd146, 32'd1};//{'src': 146, 'right': 1, 'dest': 142, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1405] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1406] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1407] = {6'd32, 8'd141, 8'd142, 32'd1};//{'src': 142, 'right': 1, 'dest': 141, 'signed': False, 'op': '>>', 'type': 'int', 'size': 2}
instructions[1408] = {6'd3, 8'd142, 8'd67, 32'd0};//{'dest': 142, 'src': 67, 'op': 'move'}
instructions[1409] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1410] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1411] = {6'd34, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '-', 'type': 'int', 'size': 2}
instructions[1412] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1413] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1414] = {6'd3, 8'd69, 8'd140, 32'd0};//{'dest': 69, 'src': 140, 'op': 'move'}
instructions[1415] = {6'd3, 8'd142, 8'd68, 32'd0};//{'dest': 142, 'src': 68, 'op': 'move'}
instructions[1416] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1417] = {6'd3, 8'd146, 8'd69, 32'd0};//{'dest': 146, 'src': 69, 'op': 'move'}
instructions[1418] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1419] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1420] = {6'd11, 8'd141, 8'd142, 32'd146};//{'srcb': 146, 'src': 142, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1421] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1422] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1423] = {6'd35, 8'd140, 8'd141, 32'd1};//{'src': 141, 'right': 1, 'dest': 140, 'signed': False, 'op': '-', 'type': 'int', 'size': 2}
instructions[1424] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1425] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1426] = {6'd3, 8'd73, 8'd140, 32'd0};//{'dest': 73, 'src': 140, 'op': 'move'}
instructions[1427] = {6'd3, 8'd142, 8'd68, 32'd0};//{'dest': 142, 'src': 68, 'op': 'move'}
instructions[1428] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1429] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1430] = {6'd11, 8'd146, 8'd142, 32'd65};//{'dest': 146, 'src': 142, 'srcb': 65, 'signed': False, 'op': '+'}
instructions[1431] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1432] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1433] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592709960, 'op': 'memory_read_request'}
instructions[1434] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1435] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592709960, 'op': 'memory_read_wait'}
instructions[1436] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139709592709960, 'element_size': 2, 'op': 'memory_read'}
instructions[1437] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1438] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1439] = {6'd25, 8'd140, 8'd141, 32'd2048};//{'src': 141, 'right': 2048, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[1440] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1441] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1442] = {6'd13, 8'd0, 8'd140, 32'd1555};//{'src': 140, 'label': 1555, 'op': 'jmp_if_false'}
instructions[1443] = {6'd0, 8'd140, 8'd0, 32'd19};//{'dest': 140, 'literal': 19, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1444] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1445] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1446] = {6'd3, 8'd72, 8'd140, 32'd0};//{'dest': 72, 'src': 140, 'op': 'move'}
instructions[1447] = {6'd1, 8'd12, 8'd0, 32'd59};//{'dest': 12, 'label': 59, 'op': 'jmp_and_link'}
instructions[1448] = {6'd3, 8'd141, 8'd68, 32'd0};//{'dest': 141, 'src': 68, 'op': 'move'}
instructions[1449] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1450] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1451] = {6'd14, 8'd140, 8'd141, 32'd2};//{'src': 141, 'right': 2, 'dest': 140, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1452] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1453] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1454] = {6'd3, 8'd71, 8'd140, 32'd0};//{'dest': 71, 'src': 140, 'op': 'move'}
instructions[1455] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1456] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1457] = {6'd3, 8'd141, 8'd71, 32'd0};//{'dest': 141, 'src': 71, 'op': 'move'}
instructions[1458] = {6'd3, 8'd142, 8'd73, 32'd0};//{'dest': 142, 'src': 73, 'op': 'move'}
instructions[1459] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1460] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1461] = {6'd36, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '<=', 'type': 'int', 'size': 2}
instructions[1462] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1463] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1464] = {6'd13, 8'd0, 8'd140, 32'd1498};//{'src': 140, 'label': 1498, 'op': 'jmp_if_false'}
instructions[1465] = {6'd3, 8'd141, 8'd71, 32'd0};//{'dest': 141, 'src': 71, 'op': 'move'}
instructions[1466] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1467] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1468] = {6'd11, 8'd142, 8'd141, 32'd65};//{'dest': 142, 'src': 141, 'srcb': 65, 'signed': False, 'op': '+'}
instructions[1469] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1470] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1471] = {6'd17, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 139709592709240, 'op': 'memory_read_request'}
instructions[1472] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1473] = {6'd18, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 139709592709240, 'op': 'memory_read_wait'}
instructions[1474] = {6'd19, 8'd140, 8'd142, 32'd0};//{'dest': 140, 'src': 142, 'sequence': 139709592709240, 'element_size': 2, 'op': 'memory_read'}
instructions[1475] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1476] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1477] = {6'd3, 8'd70, 8'd140, 32'd0};//{'dest': 70, 'src': 140, 'op': 'move'}
instructions[1478] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1479] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1480] = {6'd3, 8'd141, 8'd70, 32'd0};//{'dest': 141, 'src': 70, 'op': 'move'}
instructions[1481] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1482] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1483] = {6'd3, 8'd14, 8'd141, 32'd0};//{'dest': 14, 'src': 141, 'op': 'move'}
instructions[1484] = {6'd1, 8'd13, 8'd0, 32'd64};//{'dest': 13, 'label': 64, 'op': 'jmp_and_link'}
instructions[1485] = {6'd3, 8'd140, 8'd70, 32'd0};//{'dest': 140, 'src': 70, 'op': 'move'}
instructions[1486] = {6'd3, 8'd141, 8'd72, 32'd0};//{'dest': 141, 'src': 72, 'op': 'move'}
instructions[1487] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1488] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1489] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[1490] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1491] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1492] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1493] = {6'd3, 8'd140, 8'd72, 32'd0};//{'dest': 140, 'src': 72, 'op': 'move'}
instructions[1494] = {6'd14, 8'd72, 8'd72, 32'd1};//{'src': 72, 'right': 1, 'dest': 72, 'signed': False, 'op': '+', 'size': 2}
instructions[1495] = {6'd3, 8'd140, 8'd71, 32'd0};//{'dest': 140, 'src': 71, 'op': 'move'}
instructions[1496] = {6'd14, 8'd71, 8'd71, 32'd1};//{'src': 71, 'right': 1, 'dest': 71, 'signed': False, 'op': '+', 'size': 2}
instructions[1497] = {6'd15, 8'd0, 8'd0, 32'd1455};//{'label': 1455, 'op': 'goto'}
instructions[1498] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1499] = {6'd0, 8'd141, 8'd0, 32'd17};//{'dest': 141, 'literal': 17, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1500] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1501] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1502] = {6'd26, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': True, 'op': '+'}
instructions[1503] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1504] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1505] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1506] = {6'd1, 8'd15, 8'd0, 32'd100};//{'dest': 15, 'label': 100, 'op': 'jmp_and_link'}
instructions[1507] = {6'd3, 8'd140, 8'd16, 32'd0};//{'dest': 140, 'src': 16, 'op': 'move'}
instructions[1508] = {6'd0, 8'd141, 8'd0, 32'd18};//{'dest': 141, 'literal': 18, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1509] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1510] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1511] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[1512] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1513] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1514] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1515] = {6'd3, 8'd148, 8'd10, 32'd0};//{'dest': 148, 'src': 10, 'op': 'move'}
instructions[1516] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1517] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1518] = {6'd3, 8'd55, 8'd148, 32'd0};//{'dest': 55, 'src': 148, 'op': 'move'}
instructions[1519] = {6'd3, 8'd141, 8'd66, 32'd0};//{'dest': 141, 'src': 66, 'op': 'move'}
instructions[1520] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1521] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1522] = {6'd3, 8'd56, 8'd141, 32'd0};//{'dest': 56, 'src': 141, 'op': 'move'}
instructions[1523] = {6'd0, 8'd141, 8'd0, 32'd1};//{'dest': 141, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1524] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1525] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1526] = {6'd3, 8'd57, 8'd141, 32'd0};//{'dest': 57, 'src': 141, 'op': 'move'}
instructions[1527] = {6'd0, 8'd142, 8'd0, 32'd13};//{'dest': 142, 'literal': 13, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1528] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1529] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1530] = {6'd11, 8'd146, 8'd142, 32'd65};//{'dest': 146, 'src': 142, 'srcb': 65, 'signed': False, 'op': '+'}
instructions[1531] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1532] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1533] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709593456936, 'op': 'memory_read_request'}
instructions[1534] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1535] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709593456936, 'op': 'memory_read_wait'}
instructions[1536] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139709593456936, 'element_size': 2, 'op': 'memory_read'}
instructions[1537] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1538] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1539] = {6'd3, 8'd58, 8'd141, 32'd0};//{'dest': 58, 'src': 141, 'op': 'move'}
instructions[1540] = {6'd0, 8'd142, 8'd0, 32'd14};//{'dest': 142, 'literal': 14, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1541] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1542] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1543] = {6'd11, 8'd146, 8'd142, 32'd65};//{'dest': 146, 'src': 142, 'srcb': 65, 'signed': False, 'op': '+'}
instructions[1544] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1545] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1546] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709593457080, 'op': 'memory_read_request'}
instructions[1547] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1548] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709593457080, 'op': 'memory_read_wait'}
instructions[1549] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139709593457080, 'element_size': 2, 'op': 'memory_read'}
instructions[1550] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1551] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1552] = {6'd3, 8'd59, 8'd141, 32'd0};//{'dest': 59, 'src': 141, 'op': 'move'}
instructions[1553] = {6'd1, 8'd54, 8'd0, 32'd1026};//{'dest': 54, 'label': 1026, 'op': 'jmp_and_link'}
instructions[1554] = {6'd15, 8'd0, 8'd0, 32'd1555};//{'label': 1555, 'op': 'goto'}
instructions[1555] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1556] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1557] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1558] = {6'd3, 8'd64, 8'd140, 32'd0};//{'dest': 64, 'src': 140, 'op': 'move'}
instructions[1559] = {6'd6, 8'd0, 8'd63, 32'd0};//{'src': 63, 'op': 'jmp_to_reg'}
instructions[1560] = {6'd15, 8'd0, 8'd0, 32'd1561};//{'label': 1561, 'op': 'goto'}
instructions[1561] = {6'd0, 8'd146, 8'd0, 32'd11};//{'dest': 146, 'literal': 11, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1562] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1563] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1564] = {6'd11, 8'd147, 8'd146, 32'd65};//{'dest': 147, 'src': 146, 'srcb': 65, 'signed': False, 'op': '+'}
instructions[1565] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1566] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1567] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709593457512, 'op': 'memory_read_request'}
instructions[1568] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1569] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709593457512, 'op': 'memory_read_wait'}
instructions[1570] = {6'd19, 8'd142, 8'd147, 32'd0};//{'dest': 142, 'src': 147, 'sequence': 139709593457512, 'element_size': 2, 'op': 'memory_read'}
instructions[1571] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1572] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1573] = {6'd12, 8'd141, 8'd142, 32'd255};//{'src': 142, 'right': 255, 'dest': 141, 'signed': False, 'op': '&', 'type': 'int', 'size': 2}
instructions[1574] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1575] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1576] = {6'd31, 8'd140, 8'd141, 32'd6};//{'src': 141, 'right': 6, 'dest': 140, 'signed': False, 'op': '!=', 'type': 'int', 'size': 2}
instructions[1577] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1578] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1579] = {6'd13, 8'd0, 8'd140, 32'd1586};//{'src': 140, 'label': 1586, 'op': 'jmp_if_false'}
instructions[1580] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1581] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1582] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1583] = {6'd3, 8'd64, 8'd140, 32'd0};//{'dest': 64, 'src': 140, 'op': 'move'}
instructions[1584] = {6'd6, 8'd0, 8'd63, 32'd0};//{'src': 63, 'op': 'jmp_to_reg'}
instructions[1585] = {6'd15, 8'd0, 8'd0, 32'd1586};//{'label': 1586, 'op': 'goto'}
instructions[1586] = {6'd3, 8'd140, 8'd74, 32'd0};//{'dest': 140, 'src': 74, 'op': 'move'}
instructions[1587] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1588] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1589] = {6'd3, 8'd64, 8'd140, 32'd0};//{'dest': 64, 'src': 140, 'op': 'move'}
instructions[1590] = {6'd6, 8'd0, 8'd63, 32'd0};//{'src': 63, 'op': 'jmp_to_reg'}
instructions[1591] = {6'd0, 8'd100, 8'd0, 32'd17};//{'dest': 100, 'literal': 17, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1592] = {6'd0, 8'd101, 8'd0, 32'd0};//{'dest': 101, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1593] = {6'd0, 8'd102, 8'd0, 32'd0};//{'dest': 102, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1594] = {6'd0, 8'd103, 8'd0, 32'd0};//{'dest': 103, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1595] = {6'd3, 8'd140, 8'd77, 32'd0};//{'dest': 140, 'src': 77, 'op': 'move'}
instructions[1596] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[1597] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1598] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1599] = {6'd14, 8'd141, 8'd146, 32'd0};//{'src': 146, 'right': 0, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1600] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1601] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1602] = {6'd11, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1603] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1604] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1605] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1606] = {6'd3, 8'd140, 8'd78, 32'd0};//{'dest': 140, 'src': 78, 'op': 'move'}
instructions[1607] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[1608] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1609] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1610] = {6'd14, 8'd141, 8'd146, 32'd1};//{'src': 146, 'right': 1, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1611] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1612] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1613] = {6'd11, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1614] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1615] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1616] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1617] = {6'd0, 8'd146, 8'd0, 32'd1};//{'dest': 146, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1618] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1619] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1620] = {6'd11, 8'd147, 8'd146, 32'd79};//{'dest': 147, 'src': 146, 'srcb': 79, 'signed': False, 'op': '+'}
instructions[1621] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1622] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1623] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709593471960, 'op': 'memory_read_request'}
instructions[1624] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1625] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709593471960, 'op': 'memory_read_wait'}
instructions[1626] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139709593471960, 'element_size': 2, 'op': 'memory_read'}
instructions[1627] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[1628] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1629] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1630] = {6'd14, 8'd141, 8'd146, 32'd2};//{'src': 146, 'right': 2, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1631] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1632] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1633] = {6'd11, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1634] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1635] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1636] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1637] = {6'd0, 8'd146, 8'd0, 32'd0};//{'dest': 146, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1638] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1639] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1640] = {6'd11, 8'd147, 8'd146, 32'd79};//{'dest': 147, 'src': 146, 'srcb': 79, 'signed': False, 'op': '+'}
instructions[1641] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1642] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1643] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709593472536, 'op': 'memory_read_request'}
instructions[1644] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1645] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709593472536, 'op': 'memory_read_wait'}
instructions[1646] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139709593472536, 'element_size': 2, 'op': 'memory_read'}
instructions[1647] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[1648] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1649] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1650] = {6'd14, 8'd141, 8'd146, 32'd3};//{'src': 146, 'right': 3, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1651] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1652] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1653] = {6'd11, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1654] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1655] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1656] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1657] = {6'd0, 8'd146, 8'd0, 32'd1};//{'dest': 146, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1658] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1659] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1660] = {6'd11, 8'd147, 8'd146, 32'd81};//{'dest': 147, 'src': 146, 'srcb': 81, 'signed': False, 'op': '+'}
instructions[1661] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1662] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1663] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709592240424, 'op': 'memory_read_request'}
instructions[1664] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1665] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709592240424, 'op': 'memory_read_wait'}
instructions[1666] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139709592240424, 'element_size': 2, 'op': 'memory_read'}
instructions[1667] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[1668] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1669] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1670] = {6'd14, 8'd141, 8'd146, 32'd4};//{'src': 146, 'right': 4, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1671] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1672] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1673] = {6'd11, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1674] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1675] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1676] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1677] = {6'd0, 8'd146, 8'd0, 32'd0};//{'dest': 146, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1678] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1679] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1680] = {6'd11, 8'd147, 8'd146, 32'd81};//{'dest': 147, 'src': 146, 'srcb': 81, 'signed': False, 'op': '+'}
instructions[1681] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1682] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1683] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709592240856, 'op': 'memory_read_request'}
instructions[1684] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1685] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709592240856, 'op': 'memory_read_wait'}
instructions[1686] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139709592240856, 'element_size': 2, 'op': 'memory_read'}
instructions[1687] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[1688] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1689] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1690] = {6'd14, 8'd141, 8'd146, 32'd5};//{'src': 146, 'right': 5, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1691] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1692] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1693] = {6'd11, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1694] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1695] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1696] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1697] = {6'd0, 8'd140, 8'd0, 32'd20480};//{'dest': 140, 'literal': 20480, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1698] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[1699] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1700] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1701] = {6'd14, 8'd141, 8'd146, 32'd6};//{'src': 146, 'right': 6, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1702] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1703] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1704] = {6'd26, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': True, 'op': '+'}
instructions[1705] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1706] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1707] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1708] = {6'd3, 8'd140, 8'd82, 32'd0};//{'dest': 140, 'src': 82, 'op': 'move'}
instructions[1709] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[1710] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1711] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1712] = {6'd14, 8'd141, 8'd146, 32'd7};//{'src': 146, 'right': 7, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1713] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1714] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1715] = {6'd11, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1716] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1717] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1718] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1719] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1720] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[1721] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1722] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1723] = {6'd14, 8'd141, 8'd146, 32'd8};//{'src': 146, 'right': 8, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1724] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1725] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1726] = {6'd26, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': True, 'op': '+'}
instructions[1727] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1728] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1729] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1730] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1731] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[1732] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1733] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1734] = {6'd14, 8'd141, 8'd146, 32'd9};//{'src': 146, 'right': 9, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1735] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1736] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1737] = {6'd26, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': True, 'op': '+'}
instructions[1738] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1739] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1740] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1741] = {6'd3, 8'd140, 8'd83, 32'd0};//{'dest': 140, 'src': 83, 'op': 'move'}
instructions[1742] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1743] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1744] = {6'd13, 8'd0, 8'd140, 32'd1772};//{'src': 140, 'label': 1772, 'op': 'jmp_if_false'}
instructions[1745] = {6'd3, 8'd150, 8'd100, 32'd0};//{'dest': 150, 'src': 100, 'op': 'move'}
instructions[1746] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1747] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1748] = {6'd14, 8'd147, 8'd150, 32'd6};//{'src': 150, 'right': 6, 'dest': 147, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1749] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1750] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1751] = {6'd11, 8'd149, 8'd147, 32'd98};//{'dest': 149, 'src': 147, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1752] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1753] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1754] = {6'd17, 8'd0, 8'd149, 32'd0};//{'element_size': 2, 'src': 149, 'sequence': 139709592243736, 'op': 'memory_read_request'}
instructions[1755] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1756] = {6'd18, 8'd0, 8'd149, 32'd0};//{'element_size': 2, 'src': 149, 'sequence': 139709592243736, 'op': 'memory_read_wait'}
instructions[1757] = {6'd19, 8'd146, 8'd149, 32'd0};//{'dest': 146, 'src': 149, 'sequence': 139709592243736, 'element_size': 2, 'op': 'memory_read'}
instructions[1758] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1759] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1760] = {6'd37, 8'd140, 8'd146, 32'd1};//{'src': 146, 'right': 1, 'dest': 140, 'signed': False, 'op': '|', 'type': 'int', 'size': 2}
instructions[1761] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[1762] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1763] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1764] = {6'd14, 8'd141, 8'd146, 32'd6};//{'src': 146, 'right': 6, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1765] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1766] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1767] = {6'd11, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1768] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1769] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1770] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1771] = {6'd15, 8'd0, 8'd0, 32'd1772};//{'label': 1772, 'op': 'goto'}
instructions[1772] = {6'd3, 8'd140, 8'd84, 32'd0};//{'dest': 140, 'src': 84, 'op': 'move'}
instructions[1773] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1774] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1775] = {6'd13, 8'd0, 8'd140, 32'd1803};//{'src': 140, 'label': 1803, 'op': 'jmp_if_false'}
instructions[1776] = {6'd3, 8'd150, 8'd100, 32'd0};//{'dest': 150, 'src': 100, 'op': 'move'}
instructions[1777] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1778] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1779] = {6'd14, 8'd147, 8'd150, 32'd6};//{'src': 150, 'right': 6, 'dest': 147, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1780] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1781] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1782] = {6'd11, 8'd149, 8'd147, 32'd98};//{'dest': 149, 'src': 147, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1783] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1784] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1785] = {6'd17, 8'd0, 8'd149, 32'd0};//{'element_size': 2, 'src': 149, 'sequence': 139709592244168, 'op': 'memory_read_request'}
instructions[1786] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1787] = {6'd18, 8'd0, 8'd149, 32'd0};//{'element_size': 2, 'src': 149, 'sequence': 139709592244168, 'op': 'memory_read_wait'}
instructions[1788] = {6'd19, 8'd146, 8'd149, 32'd0};//{'dest': 146, 'src': 149, 'sequence': 139709592244168, 'element_size': 2, 'op': 'memory_read'}
instructions[1789] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1790] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1791] = {6'd37, 8'd140, 8'd146, 32'd2};//{'src': 146, 'right': 2, 'dest': 140, 'signed': False, 'op': '|', 'type': 'int', 'size': 2}
instructions[1792] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[1793] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1794] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1795] = {6'd14, 8'd141, 8'd146, 32'd6};//{'src': 146, 'right': 6, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1796] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1797] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1798] = {6'd11, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1799] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1800] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1801] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1802] = {6'd15, 8'd0, 8'd0, 32'd1803};//{'label': 1803, 'op': 'goto'}
instructions[1803] = {6'd3, 8'd140, 8'd85, 32'd0};//{'dest': 140, 'src': 85, 'op': 'move'}
instructions[1804] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1805] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1806] = {6'd13, 8'd0, 8'd140, 32'd1834};//{'src': 140, 'label': 1834, 'op': 'jmp_if_false'}
instructions[1807] = {6'd3, 8'd150, 8'd100, 32'd0};//{'dest': 150, 'src': 100, 'op': 'move'}
instructions[1808] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1809] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1810] = {6'd14, 8'd147, 8'd150, 32'd6};//{'src': 150, 'right': 6, 'dest': 147, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1811] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1812] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1813] = {6'd11, 8'd149, 8'd147, 32'd98};//{'dest': 149, 'src': 147, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1814] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1815] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1816] = {6'd17, 8'd0, 8'd149, 32'd0};//{'element_size': 2, 'src': 149, 'sequence': 139709593486328, 'op': 'memory_read_request'}
instructions[1817] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1818] = {6'd18, 8'd0, 8'd149, 32'd0};//{'element_size': 2, 'src': 149, 'sequence': 139709593486328, 'op': 'memory_read_wait'}
instructions[1819] = {6'd19, 8'd146, 8'd149, 32'd0};//{'dest': 146, 'src': 149, 'sequence': 139709593486328, 'element_size': 2, 'op': 'memory_read'}
instructions[1820] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1821] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1822] = {6'd37, 8'd140, 8'd146, 32'd4};//{'src': 146, 'right': 4, 'dest': 140, 'signed': False, 'op': '|', 'type': 'int', 'size': 2}
instructions[1823] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[1824] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1825] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1826] = {6'd14, 8'd141, 8'd146, 32'd6};//{'src': 146, 'right': 6, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1827] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1828] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1829] = {6'd11, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1830] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1831] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1832] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1833] = {6'd15, 8'd0, 8'd0, 32'd1834};//{'label': 1834, 'op': 'goto'}
instructions[1834] = {6'd3, 8'd140, 8'd86, 32'd0};//{'dest': 140, 'src': 86, 'op': 'move'}
instructions[1835] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1836] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1837] = {6'd13, 8'd0, 8'd140, 32'd1865};//{'src': 140, 'label': 1865, 'op': 'jmp_if_false'}
instructions[1838] = {6'd3, 8'd150, 8'd100, 32'd0};//{'dest': 150, 'src': 100, 'op': 'move'}
instructions[1839] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1840] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1841] = {6'd14, 8'd147, 8'd150, 32'd6};//{'src': 150, 'right': 6, 'dest': 147, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1842] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1843] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1844] = {6'd11, 8'd149, 8'd147, 32'd98};//{'dest': 149, 'src': 147, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1845] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1846] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1847] = {6'd17, 8'd0, 8'd149, 32'd0};//{'element_size': 2, 'src': 149, 'sequence': 139709593487048, 'op': 'memory_read_request'}
instructions[1848] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1849] = {6'd18, 8'd0, 8'd149, 32'd0};//{'element_size': 2, 'src': 149, 'sequence': 139709593487048, 'op': 'memory_read_wait'}
instructions[1850] = {6'd19, 8'd146, 8'd149, 32'd0};//{'dest': 146, 'src': 149, 'sequence': 139709593487048, 'element_size': 2, 'op': 'memory_read'}
instructions[1851] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1852] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1853] = {6'd37, 8'd140, 8'd146, 32'd8};//{'src': 146, 'right': 8, 'dest': 140, 'signed': False, 'op': '|', 'type': 'int', 'size': 2}
instructions[1854] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[1855] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1856] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1857] = {6'd14, 8'd141, 8'd146, 32'd6};//{'src': 146, 'right': 6, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1858] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1859] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1860] = {6'd11, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1861] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1862] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1863] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1864] = {6'd15, 8'd0, 8'd0, 32'd1865};//{'label': 1865, 'op': 'goto'}
instructions[1865] = {6'd3, 8'd140, 8'd87, 32'd0};//{'dest': 140, 'src': 87, 'op': 'move'}
instructions[1866] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1867] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1868] = {6'd13, 8'd0, 8'd140, 32'd1896};//{'src': 140, 'label': 1896, 'op': 'jmp_if_false'}
instructions[1869] = {6'd3, 8'd150, 8'd100, 32'd0};//{'dest': 150, 'src': 100, 'op': 'move'}
instructions[1870] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1871] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1872] = {6'd14, 8'd147, 8'd150, 32'd6};//{'src': 150, 'right': 6, 'dest': 147, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1873] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1874] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1875] = {6'd11, 8'd149, 8'd147, 32'd98};//{'dest': 149, 'src': 147, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1876] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1877] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1878] = {6'd17, 8'd0, 8'd149, 32'd0};//{'element_size': 2, 'src': 149, 'sequence': 139709593487768, 'op': 'memory_read_request'}
instructions[1879] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1880] = {6'd18, 8'd0, 8'd149, 32'd0};//{'element_size': 2, 'src': 149, 'sequence': 139709593487768, 'op': 'memory_read_wait'}
instructions[1881] = {6'd19, 8'd146, 8'd149, 32'd0};//{'dest': 146, 'src': 149, 'sequence': 139709593487768, 'element_size': 2, 'op': 'memory_read'}
instructions[1882] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1883] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1884] = {6'd37, 8'd140, 8'd146, 32'd16};//{'src': 146, 'right': 16, 'dest': 140, 'signed': False, 'op': '|', 'type': 'int', 'size': 2}
instructions[1885] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[1886] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1887] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1888] = {6'd14, 8'd141, 8'd146, 32'd6};//{'src': 146, 'right': 6, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1889] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1890] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1891] = {6'd11, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1892] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1893] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1894] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1895] = {6'd15, 8'd0, 8'd0, 32'd1896};//{'label': 1896, 'op': 'goto'}
instructions[1896] = {6'd3, 8'd140, 8'd88, 32'd0};//{'dest': 140, 'src': 88, 'op': 'move'}
instructions[1897] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1898] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1899] = {6'd13, 8'd0, 8'd140, 32'd1927};//{'src': 140, 'label': 1927, 'op': 'jmp_if_false'}
instructions[1900] = {6'd3, 8'd150, 8'd100, 32'd0};//{'dest': 150, 'src': 100, 'op': 'move'}
instructions[1901] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1902] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1903] = {6'd14, 8'd147, 8'd150, 32'd6};//{'src': 150, 'right': 6, 'dest': 147, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1904] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1905] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1906] = {6'd11, 8'd149, 8'd147, 32'd98};//{'dest': 149, 'src': 147, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1907] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1908] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1909] = {6'd17, 8'd0, 8'd149, 32'd0};//{'element_size': 2, 'src': 149, 'sequence': 139709593488488, 'op': 'memory_read_request'}
instructions[1910] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1911] = {6'd18, 8'd0, 8'd149, 32'd0};//{'element_size': 2, 'src': 149, 'sequence': 139709593488488, 'op': 'memory_read_wait'}
instructions[1912] = {6'd19, 8'd146, 8'd149, 32'd0};//{'dest': 146, 'src': 149, 'sequence': 139709593488488, 'element_size': 2, 'op': 'memory_read'}
instructions[1913] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1914] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1915] = {6'd37, 8'd140, 8'd146, 32'd32};//{'src': 146, 'right': 32, 'dest': 140, 'signed': False, 'op': '|', 'type': 'int', 'size': 2}
instructions[1916] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[1917] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1918] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1919] = {6'd14, 8'd141, 8'd146, 32'd6};//{'src': 146, 'right': 6, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1920] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1921] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1922] = {6'd11, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1923] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1924] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1925] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1926] = {6'd15, 8'd0, 8'd0, 32'd1927};//{'label': 1927, 'op': 'goto'}
instructions[1927] = {6'd1, 8'd12, 8'd0, 32'd59};//{'dest': 12, 'label': 59, 'op': 'jmp_and_link'}
instructions[1928] = {6'd0, 8'd141, 8'd0, 32'd49320};//{'dest': 141, 'literal': 49320, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1929] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1930] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1931] = {6'd3, 8'd14, 8'd141, 32'd0};//{'dest': 14, 'src': 141, 'op': 'move'}
instructions[1932] = {6'd1, 8'd13, 8'd0, 32'd64};//{'dest': 13, 'label': 64, 'op': 'jmp_and_link'}
instructions[1933] = {6'd0, 8'd141, 8'd0, 32'd119};//{'dest': 141, 'literal': 119, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1934] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1935] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1936] = {6'd3, 8'd14, 8'd141, 32'd0};//{'dest': 14, 'src': 141, 'op': 'move'}
instructions[1937] = {6'd1, 8'd13, 8'd0, 32'd64};//{'dest': 13, 'label': 64, 'op': 'jmp_and_link'}
instructions[1938] = {6'd3, 8'd141, 8'd75, 32'd0};//{'dest': 141, 'src': 75, 'op': 'move'}
instructions[1939] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1940] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1941] = {6'd3, 8'd14, 8'd141, 32'd0};//{'dest': 14, 'src': 141, 'op': 'move'}
instructions[1942] = {6'd1, 8'd13, 8'd0, 32'd64};//{'dest': 13, 'label': 64, 'op': 'jmp_and_link'}
instructions[1943] = {6'd3, 8'd141, 8'd76, 32'd0};//{'dest': 141, 'src': 76, 'op': 'move'}
instructions[1944] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1945] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1946] = {6'd3, 8'd14, 8'd141, 32'd0};//{'dest': 14, 'src': 141, 'op': 'move'}
instructions[1947] = {6'd1, 8'd13, 8'd0, 32'd64};//{'dest': 13, 'label': 64, 'op': 'jmp_and_link'}
instructions[1948] = {6'd0, 8'd141, 8'd0, 32'd6};//{'dest': 141, 'literal': 6, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1949] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1950] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1951] = {6'd3, 8'd14, 8'd141, 32'd0};//{'dest': 14, 'src': 141, 'op': 'move'}
instructions[1952] = {6'd1, 8'd13, 8'd0, 32'd64};//{'dest': 13, 'label': 64, 'op': 'jmp_and_link'}
instructions[1953] = {6'd3, 8'd142, 8'd99, 32'd0};//{'dest': 142, 'src': 99, 'op': 'move'}
instructions[1954] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1955] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1956] = {6'd14, 8'd141, 8'd142, 32'd20};//{'src': 142, 'right': 20, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1957] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1958] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1959] = {6'd3, 8'd14, 8'd141, 32'd0};//{'dest': 14, 'src': 141, 'op': 'move'}
instructions[1960] = {6'd1, 8'd13, 8'd0, 32'd64};//{'dest': 13, 'label': 64, 'op': 'jmp_and_link'}
instructions[1961] = {6'd3, 8'd146, 8'd99, 32'd0};//{'dest': 146, 'src': 99, 'op': 'move'}
instructions[1962] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1963] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1964] = {6'd14, 8'd142, 8'd146, 32'd20};//{'src': 146, 'right': 20, 'dest': 142, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1965] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1966] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1967] = {6'd14, 8'd141, 8'd142, 32'd1};//{'src': 142, 'right': 1, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1968] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1969] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1970] = {6'd32, 8'd140, 8'd141, 32'd1};//{'src': 141, 'right': 1, 'dest': 140, 'signed': False, 'op': '>>', 'type': 'int', 'size': 2}
instructions[1971] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1972] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1973] = {6'd3, 8'd101, 8'd140, 32'd0};//{'dest': 101, 'src': 140, 'op': 'move'}
instructions[1974] = {6'd3, 8'd140, 8'd100, 32'd0};//{'dest': 140, 'src': 100, 'op': 'move'}
instructions[1975] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1976] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1977] = {6'd3, 8'd102, 8'd140, 32'd0};//{'dest': 102, 'src': 140, 'op': 'move'}
instructions[1978] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1979] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1980] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1981] = {6'd3, 8'd103, 8'd140, 32'd0};//{'dest': 103, 'src': 140, 'op': 'move'}
instructions[1982] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1983] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1984] = {6'd3, 8'd141, 8'd103, 32'd0};//{'dest': 141, 'src': 103, 'op': 'move'}
instructions[1985] = {6'd3, 8'd142, 8'd101, 32'd0};//{'dest': 142, 'src': 101, 'op': 'move'}
instructions[1986] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1987] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1988] = {6'd20, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '<', 'type': 'int', 'size': 2}
instructions[1989] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1990] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1991] = {6'd13, 8'd0, 8'd140, 32'd2011};//{'src': 140, 'label': 2011, 'op': 'jmp_if_false'}
instructions[1992] = {6'd3, 8'd142, 8'd102, 32'd0};//{'dest': 142, 'src': 102, 'op': 'move'}
instructions[1993] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1994] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1995] = {6'd11, 8'd146, 8'd142, 32'd98};//{'dest': 146, 'src': 142, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1996] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1997] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1998] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592280384, 'op': 'memory_read_request'}
instructions[1999] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2000] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592280384, 'op': 'memory_read_wait'}
instructions[2001] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139709592280384, 'element_size': 2, 'op': 'memory_read'}
instructions[2002] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2003] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2004] = {6'd3, 8'd14, 8'd141, 32'd0};//{'dest': 14, 'src': 141, 'op': 'move'}
instructions[2005] = {6'd1, 8'd13, 8'd0, 32'd64};//{'dest': 13, 'label': 64, 'op': 'jmp_and_link'}
instructions[2006] = {6'd3, 8'd140, 8'd102, 32'd0};//{'dest': 140, 'src': 102, 'op': 'move'}
instructions[2007] = {6'd14, 8'd102, 8'd102, 32'd1};//{'src': 102, 'right': 1, 'dest': 102, 'signed': False, 'op': '+', 'size': 2}
instructions[2008] = {6'd3, 8'd140, 8'd103, 32'd0};//{'dest': 140, 'src': 103, 'op': 'move'}
instructions[2009] = {6'd14, 8'd103, 8'd103, 32'd1};//{'src': 103, 'right': 1, 'dest': 103, 'signed': False, 'op': '+', 'size': 2}
instructions[2010] = {6'd15, 8'd0, 8'd0, 32'd1982};//{'label': 1982, 'op': 'goto'}
instructions[2011] = {6'd1, 8'd15, 8'd0, 32'd100};//{'dest': 15, 'label': 100, 'op': 'jmp_and_link'}
instructions[2012] = {6'd3, 8'd140, 8'd16, 32'd0};//{'dest': 140, 'src': 16, 'op': 'move'}
instructions[2013] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[2014] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2015] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2016] = {6'd14, 8'd141, 8'd146, 32'd8};//{'src': 146, 'right': 8, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2017] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2018] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2019] = {6'd11, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[2020] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2021] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2022] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2023] = {6'd3, 8'd143, 8'd98, 32'd0};//{'dest': 143, 'src': 98, 'op': 'move'}
instructions[2024] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2025] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2026] = {6'd3, 8'd55, 8'd143, 32'd0};//{'dest': 55, 'src': 143, 'op': 'move'}
instructions[2027] = {6'd3, 8'd142, 8'd99, 32'd0};//{'dest': 142, 'src': 99, 'op': 'move'}
instructions[2028] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2029] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2030] = {6'd14, 8'd141, 8'd142, 32'd40};//{'src': 142, 'right': 40, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2031] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2032] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2033] = {6'd3, 8'd56, 8'd141, 32'd0};//{'dest': 56, 'src': 141, 'op': 'move'}
instructions[2034] = {6'd0, 8'd141, 8'd0, 32'd6};//{'dest': 141, 'literal': 6, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2035] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2036] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2037] = {6'd3, 8'd57, 8'd141, 32'd0};//{'dest': 57, 'src': 141, 'op': 'move'}
instructions[2038] = {6'd3, 8'd141, 8'd75, 32'd0};//{'dest': 141, 'src': 75, 'op': 'move'}
instructions[2039] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2040] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2041] = {6'd3, 8'd58, 8'd141, 32'd0};//{'dest': 58, 'src': 141, 'op': 'move'}
instructions[2042] = {6'd3, 8'd141, 8'd76, 32'd0};//{'dest': 141, 'src': 76, 'op': 'move'}
instructions[2043] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2044] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2045] = {6'd3, 8'd59, 8'd141, 32'd0};//{'dest': 59, 'src': 141, 'op': 'move'}
instructions[2046] = {6'd1, 8'd54, 8'd0, 32'd1026};//{'dest': 54, 'label': 1026, 'op': 'jmp_and_link'}
instructions[2047] = {6'd6, 8'd0, 8'd97, 32'd0};//{'src': 97, 'op': 'jmp_to_reg'}
instructions[2048] = {6'd0, 8'd109, 8'd0, 32'd0};//{'dest': 109, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2049] = {6'd0, 8'd110, 8'd0, 32'd0};//{'dest': 110, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2050] = {6'd0, 8'd111, 8'd0, 32'd0};//{'dest': 111, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2051] = {6'd0, 8'd112, 8'd0, 32'd0};//{'dest': 112, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2052] = {6'd0, 8'd113, 8'd0, 32'd0};//{'dest': 113, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2053] = {6'd0, 8'd114, 8'd0, 32'd0};//{'dest': 114, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2054] = {6'd3, 8'd143, 8'd108, 32'd0};//{'dest': 143, 'src': 108, 'op': 'move'}
instructions[2055] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2056] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2057] = {6'd3, 8'd65, 8'd143, 32'd0};//{'dest': 65, 'src': 143, 'op': 'move'}
instructions[2058] = {6'd1, 8'd63, 8'd0, 32'd1237};//{'dest': 63, 'label': 1237, 'op': 'jmp_and_link'}
instructions[2059] = {6'd3, 8'd140, 8'd64, 32'd0};//{'dest': 140, 'src': 64, 'op': 'move'}
instructions[2060] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2061] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2062] = {6'd3, 8'd109, 8'd140, 32'd0};//{'dest': 109, 'src': 140, 'op': 'move'}
instructions[2063] = {6'd0, 8'd147, 8'd0, 32'd7};//{'dest': 147, 'literal': 7, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2064] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2065] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2066] = {6'd11, 8'd149, 8'd147, 32'd108};//{'dest': 149, 'src': 147, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2067] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2068] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2069] = {6'd17, 8'd0, 8'd149, 32'd0};//{'element_size': 2, 'src': 149, 'sequence': 139709592314656, 'op': 'memory_read_request'}
instructions[2070] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2071] = {6'd18, 8'd0, 8'd149, 32'd0};//{'element_size': 2, 'src': 149, 'sequence': 139709592314656, 'op': 'memory_read_wait'}
instructions[2072] = {6'd19, 8'd146, 8'd149, 32'd0};//{'dest': 146, 'src': 149, 'sequence': 139709592314656, 'element_size': 2, 'op': 'memory_read'}
instructions[2073] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2074] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2075] = {6'd32, 8'd142, 8'd146, 32'd8};//{'src': 146, 'right': 8, 'dest': 142, 'signed': False, 'op': '>>', 'type': 'int', 'size': 2}
instructions[2076] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2077] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2078] = {6'd12, 8'd141, 8'd142, 32'd15};//{'src': 142, 'right': 15, 'dest': 141, 'signed': False, 'op': '&', 'type': 'int', 'size': 2}
instructions[2079] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2080] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2081] = {6'd33, 8'd140, 8'd141, 32'd1};//{'src': 141, 'right': 1, 'dest': 140, 'signed': False, 'op': '<<', 'type': 'int', 'size': 2}
instructions[2082] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2083] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2084] = {6'd3, 8'd110, 8'd140, 32'd0};//{'dest': 110, 'src': 140, 'op': 'move'}
instructions[2085] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2086] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2087] = {6'd3, 8'd141, 8'd110, 32'd0};//{'dest': 141, 'src': 110, 'op': 'move'}
instructions[2088] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2089] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2090] = {6'd14, 8'd140, 8'd141, 32'd7};//{'src': 141, 'right': 7, 'dest': 140, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2091] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2092] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2093] = {6'd3, 8'd111, 8'd140, 32'd0};//{'dest': 111, 'src': 140, 'op': 'move'}
instructions[2094] = {6'd0, 8'd141, 8'd0, 32'd8};//{'dest': 141, 'literal': 8, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2095] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2096] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2097] = {6'd11, 8'd142, 8'd141, 32'd108};//{'dest': 142, 'src': 141, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2098] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2099] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2100] = {6'd17, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 139709592278800, 'op': 'memory_read_request'}
instructions[2101] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2102] = {6'd18, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 139709592278800, 'op': 'memory_read_wait'}
instructions[2103] = {6'd19, 8'd140, 8'd142, 32'd0};//{'dest': 140, 'src': 142, 'sequence': 139709592278800, 'element_size': 2, 'op': 'memory_read'}
instructions[2104] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2105] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2106] = {6'd3, 8'd112, 8'd140, 32'd0};//{'dest': 112, 'src': 140, 'op': 'move'}
instructions[2107] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2108] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2109] = {6'd3, 8'd141, 8'd112, 32'd0};//{'dest': 141, 'src': 112, 'op': 'move'}
instructions[2110] = {6'd3, 8'd146, 8'd110, 32'd0};//{'dest': 146, 'src': 110, 'op': 'move'}
instructions[2111] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2112] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2113] = {6'd33, 8'd142, 8'd146, 32'd1};//{'src': 146, 'right': 1, 'dest': 142, 'signed': False, 'op': '<<', 'type': 'int', 'size': 2}
instructions[2114] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2115] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2116] = {6'd34, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '-', 'type': 'int', 'size': 2}
instructions[2117] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2118] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2119] = {6'd3, 8'd113, 8'd140, 32'd0};//{'dest': 113, 'src': 140, 'op': 'move'}
instructions[2120] = {6'd3, 8'd149, 8'd111, 32'd0};//{'dest': 149, 'src': 111, 'op': 'move'}
instructions[2121] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2122] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2123] = {6'd14, 8'd146, 8'd149, 32'd6};//{'src': 149, 'right': 6, 'dest': 146, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2124] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2125] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2126] = {6'd11, 8'd147, 8'd146, 32'd108};//{'dest': 147, 'src': 146, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2127] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2128] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2129] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709593509112, 'op': 'memory_read_request'}
instructions[2130] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2131] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709593509112, 'op': 'memory_read_wait'}
instructions[2132] = {6'd19, 8'd142, 8'd147, 32'd0};//{'dest': 142, 'src': 147, 'sequence': 139709593509112, 'element_size': 2, 'op': 'memory_read'}
instructions[2133] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2134] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2135] = {6'd12, 8'd141, 8'd142, 32'd61440};//{'src': 142, 'right': 61440, 'dest': 141, 'signed': False, 'op': '&', 'type': 'int', 'size': 2}
instructions[2136] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2137] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2138] = {6'd32, 8'd140, 8'd141, 32'd10};//{'src': 141, 'right': 10, 'dest': 140, 'signed': False, 'op': '>>', 'type': 'int', 'size': 2}
instructions[2139] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2140] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2141] = {6'd3, 8'd114, 8'd140, 32'd0};//{'dest': 114, 'src': 140, 'op': 'move'}
instructions[2142] = {6'd3, 8'd141, 8'd113, 32'd0};//{'dest': 141, 'src': 113, 'op': 'move'}
instructions[2143] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2144] = {6'd3, 8'd142, 8'd114, 32'd0};//{'dest': 142, 'src': 114, 'op': 'move'}
instructions[2145] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2146] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2147] = {6'd34, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '-', 'type': 'int', 'size': 2}
instructions[2148] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2149] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2150] = {6'd3, 8'd104, 8'd140, 32'd0};//{'dest': 104, 'src': 140, 'op': 'move'}
instructions[2151] = {6'd3, 8'd141, 8'd111, 32'd0};//{'dest': 141, 'src': 111, 'op': 'move'}
instructions[2152] = {6'd3, 8'd146, 8'd114, 32'd0};//{'dest': 146, 'src': 114, 'op': 'move'}
instructions[2153] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2154] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2155] = {6'd32, 8'd142, 8'd146, 32'd1};//{'src': 146, 'right': 1, 'dest': 142, 'signed': False, 'op': '>>', 'type': 'int', 'size': 2}
instructions[2156] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2157] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2158] = {6'd11, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2159] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2160] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2161] = {6'd3, 8'd105, 8'd140, 32'd0};//{'dest': 105, 'src': 140, 'op': 'move'}
instructions[2162] = {6'd3, 8'd146, 8'd111, 32'd0};//{'dest': 146, 'src': 111, 'op': 'move'}
instructions[2163] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2164] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2165] = {6'd14, 8'd141, 8'd146, 32'd0};//{'src': 146, 'right': 0, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2166] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2167] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2168] = {6'd11, 8'd142, 8'd141, 32'd108};//{'dest': 142, 'src': 141, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2169] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2170] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2171] = {6'd17, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 139709592280168, 'op': 'memory_read_request'}
instructions[2172] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2173] = {6'd18, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 139709592280168, 'op': 'memory_read_wait'}
instructions[2174] = {6'd19, 8'd140, 8'd142, 32'd0};//{'dest': 140, 'src': 142, 'sequence': 139709592280168, 'element_size': 2, 'op': 'memory_read'}
instructions[2175] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2176] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2177] = {6'd3, 8'd89, 8'd140, 32'd0};//{'dest': 89, 'src': 140, 'op': 'move'}
instructions[2178] = {6'd3, 8'd146, 8'd111, 32'd0};//{'dest': 146, 'src': 111, 'op': 'move'}
instructions[2179] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2180] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2181] = {6'd14, 8'd141, 8'd146, 32'd1};//{'src': 146, 'right': 1, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2182] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2183] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2184] = {6'd11, 8'd142, 8'd141, 32'd108};//{'dest': 142, 'src': 141, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2185] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2186] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2187] = {6'd17, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 139709592315592, 'op': 'memory_read_request'}
instructions[2188] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2189] = {6'd18, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 139709592315592, 'op': 'memory_read_wait'}
instructions[2190] = {6'd19, 8'd140, 8'd142, 32'd0};//{'dest': 140, 'src': 142, 'sequence': 139709592315592, 'element_size': 2, 'op': 'memory_read'}
instructions[2191] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2192] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2193] = {6'd3, 8'd90, 8'd140, 32'd0};//{'dest': 90, 'src': 140, 'op': 'move'}
instructions[2194] = {6'd3, 8'd149, 8'd111, 32'd0};//{'dest': 149, 'src': 111, 'op': 'move'}
instructions[2195] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2196] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2197] = {6'd14, 8'd146, 8'd149, 32'd2};//{'src': 149, 'right': 2, 'dest': 146, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2198] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2199] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2200] = {6'd11, 8'd147, 8'd146, 32'd108};//{'dest': 147, 'src': 146, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2201] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2202] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2203] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709592315952, 'op': 'memory_read_request'}
instructions[2204] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2205] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709592315952, 'op': 'memory_read_wait'}
instructions[2206] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139709592315952, 'element_size': 2, 'op': 'memory_read'}
instructions[2207] = {6'd0, 8'd141, 8'd0, 32'd1};//{'dest': 141, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2208] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2209] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2210] = {6'd11, 8'd142, 8'd141, 32'd91};//{'dest': 142, 'src': 141, 'srcb': 91, 'signed': False, 'op': '+'}
instructions[2211] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2212] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2213] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2214] = {6'd3, 8'd149, 8'd111, 32'd0};//{'dest': 149, 'src': 111, 'op': 'move'}
instructions[2215] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2216] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2217] = {6'd14, 8'd146, 8'd149, 32'd3};//{'src': 149, 'right': 3, 'dest': 146, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2218] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2219] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2220] = {6'd11, 8'd147, 8'd146, 32'd108};//{'dest': 147, 'src': 146, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2221] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2222] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2223] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709592316960, 'op': 'memory_read_request'}
instructions[2224] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2225] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709592316960, 'op': 'memory_read_wait'}
instructions[2226] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139709592316960, 'element_size': 2, 'op': 'memory_read'}
instructions[2227] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2228] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2229] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2230] = {6'd11, 8'd142, 8'd141, 32'd91};//{'dest': 142, 'src': 141, 'srcb': 91, 'signed': False, 'op': '+'}
instructions[2231] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2232] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2233] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2234] = {6'd3, 8'd149, 8'd111, 32'd0};//{'dest': 149, 'src': 111, 'op': 'move'}
instructions[2235] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2236] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2237] = {6'd14, 8'd146, 8'd149, 32'd4};//{'src': 149, 'right': 4, 'dest': 146, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2238] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2239] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2240] = {6'd11, 8'd147, 8'd146, 32'd108};//{'dest': 147, 'src': 146, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2241] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2242] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2243] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709592317032, 'op': 'memory_read_request'}
instructions[2244] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2245] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709592317032, 'op': 'memory_read_wait'}
instructions[2246] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139709592317032, 'element_size': 2, 'op': 'memory_read'}
instructions[2247] = {6'd0, 8'd141, 8'd0, 32'd1};//{'dest': 141, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2248] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2249] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2250] = {6'd11, 8'd142, 8'd141, 32'd92};//{'dest': 142, 'src': 141, 'srcb': 92, 'signed': False, 'op': '+'}
instructions[2251] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2252] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2253] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2254] = {6'd3, 8'd149, 8'd111, 32'd0};//{'dest': 149, 'src': 111, 'op': 'move'}
instructions[2255] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2256] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2257] = {6'd14, 8'd146, 8'd149, 32'd5};//{'src': 149, 'right': 5, 'dest': 146, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2258] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2259] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2260] = {6'd11, 8'd147, 8'd146, 32'd108};//{'dest': 147, 'src': 146, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2261] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2262] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2263] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709592314224, 'op': 'memory_read_request'}
instructions[2264] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2265] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709592314224, 'op': 'memory_read_wait'}
instructions[2266] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139709592314224, 'element_size': 2, 'op': 'memory_read'}
instructions[2267] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2268] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2269] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2270] = {6'd11, 8'd142, 8'd141, 32'd92};//{'dest': 142, 'src': 141, 'srcb': 92, 'signed': False, 'op': '+'}
instructions[2271] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2272] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2273] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2274] = {6'd3, 8'd146, 8'd111, 32'd0};//{'dest': 146, 'src': 111, 'op': 'move'}
instructions[2275] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2276] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2277] = {6'd14, 8'd141, 8'd146, 32'd7};//{'src': 146, 'right': 7, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2278] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2279] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2280] = {6'd11, 8'd142, 8'd141, 32'd108};//{'dest': 142, 'src': 141, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2281] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2282] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2283] = {6'd17, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 139709592314008, 'op': 'memory_read_request'}
instructions[2284] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2285] = {6'd18, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 139709592314008, 'op': 'memory_read_wait'}
instructions[2286] = {6'd19, 8'd140, 8'd142, 32'd0};//{'dest': 140, 'src': 142, 'sequence': 139709592314008, 'element_size': 2, 'op': 'memory_read'}
instructions[2287] = {6'd3, 8'd147, 8'd111, 32'd0};//{'dest': 147, 'src': 111, 'op': 'move'}
instructions[2288] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2289] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2290] = {6'd14, 8'd142, 8'd147, 32'd6};//{'src': 147, 'right': 6, 'dest': 142, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2291] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2292] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2293] = {6'd11, 8'd146, 8'd142, 32'd108};//{'dest': 146, 'src': 142, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2294] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2295] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2296] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592314944, 'op': 'memory_read_request'}
instructions[2297] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2298] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592314944, 'op': 'memory_read_wait'}
instructions[2299] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139709592314944, 'element_size': 2, 'op': 'memory_read'}
instructions[2300] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2301] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2302] = {6'd12, 8'd140, 8'd141, 32'd1};//{'src': 141, 'right': 1, 'dest': 140, 'signed': False, 'op': '&', 'type': 'int', 'size': 2}
instructions[2303] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2304] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2305] = {6'd3, 8'd93, 8'd140, 32'd0};//{'dest': 93, 'src': 140, 'op': 'move'}
instructions[2306] = {6'd3, 8'd147, 8'd111, 32'd0};//{'dest': 147, 'src': 111, 'op': 'move'}
instructions[2307] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2308] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2309] = {6'd14, 8'd142, 8'd147, 32'd6};//{'src': 147, 'right': 6, 'dest': 142, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2310] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2311] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2312] = {6'd11, 8'd146, 8'd142, 32'd108};//{'dest': 146, 'src': 142, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2313] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2314] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2315] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709593507240, 'op': 'memory_read_request'}
instructions[2316] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2317] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709593507240, 'op': 'memory_read_wait'}
instructions[2318] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139709593507240, 'element_size': 2, 'op': 'memory_read'}
instructions[2319] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2320] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2321] = {6'd12, 8'd140, 8'd141, 32'd2};//{'src': 141, 'right': 2, 'dest': 140, 'signed': False, 'op': '&', 'type': 'int', 'size': 2}
instructions[2322] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2323] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2324] = {6'd3, 8'd94, 8'd140, 32'd0};//{'dest': 94, 'src': 140, 'op': 'move'}
instructions[2325] = {6'd3, 8'd147, 8'd111, 32'd0};//{'dest': 147, 'src': 111, 'op': 'move'}
instructions[2326] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2327] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2328] = {6'd14, 8'd142, 8'd147, 32'd6};//{'src': 147, 'right': 6, 'dest': 142, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2329] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2330] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2331] = {6'd11, 8'd146, 8'd142, 32'd108};//{'dest': 146, 'src': 142, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2332] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2333] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2334] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709593507672, 'op': 'memory_read_request'}
instructions[2335] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2336] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709593507672, 'op': 'memory_read_wait'}
instructions[2337] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139709593507672, 'element_size': 2, 'op': 'memory_read'}
instructions[2338] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2339] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2340] = {6'd12, 8'd140, 8'd141, 32'd4};//{'src': 141, 'right': 4, 'dest': 140, 'signed': False, 'op': '&', 'type': 'int', 'size': 2}
instructions[2341] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2342] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2343] = {6'd3, 8'd95, 8'd140, 32'd0};//{'dest': 95, 'src': 140, 'op': 'move'}
instructions[2344] = {6'd3, 8'd147, 8'd111, 32'd0};//{'dest': 147, 'src': 111, 'op': 'move'}
instructions[2345] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2346] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2347] = {6'd14, 8'd142, 8'd147, 32'd6};//{'src': 147, 'right': 6, 'dest': 142, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2348] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2349] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2350] = {6'd11, 8'd146, 8'd142, 32'd108};//{'dest': 146, 'src': 142, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2351] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2352] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2353] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709593507960, 'op': 'memory_read_request'}
instructions[2354] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2355] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709593507960, 'op': 'memory_read_wait'}
instructions[2356] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139709593507960, 'element_size': 2, 'op': 'memory_read'}
instructions[2357] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2358] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2359] = {6'd12, 8'd140, 8'd141, 32'd8};//{'src': 141, 'right': 8, 'dest': 140, 'signed': False, 'op': '&', 'type': 'int', 'size': 2}
instructions[2360] = {6'd3, 8'd147, 8'd111, 32'd0};//{'dest': 147, 'src': 111, 'op': 'move'}
instructions[2361] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2362] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2363] = {6'd14, 8'd142, 8'd147, 32'd6};//{'src': 147, 'right': 6, 'dest': 142, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2364] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2365] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2366] = {6'd11, 8'd146, 8'd142, 32'd108};//{'dest': 146, 'src': 142, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2367] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2368] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2369] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709593506232, 'op': 'memory_read_request'}
instructions[2370] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2371] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709593506232, 'op': 'memory_read_wait'}
instructions[2372] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139709593506232, 'element_size': 2, 'op': 'memory_read'}
instructions[2373] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2374] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2375] = {6'd12, 8'd140, 8'd141, 32'd16};//{'src': 141, 'right': 16, 'dest': 140, 'signed': False, 'op': '&', 'type': 'int', 'size': 2}
instructions[2376] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2377] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2378] = {6'd3, 8'd96, 8'd140, 32'd0};//{'dest': 96, 'src': 140, 'op': 'move'}
instructions[2379] = {6'd3, 8'd147, 8'd111, 32'd0};//{'dest': 147, 'src': 111, 'op': 'move'}
instructions[2380] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2381] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2382] = {6'd14, 8'd142, 8'd147, 32'd6};//{'src': 147, 'right': 6, 'dest': 142, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2383] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2384] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2385] = {6'd11, 8'd146, 8'd142, 32'd108};//{'dest': 146, 'src': 142, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2386] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2387] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2388] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709593509616, 'op': 'memory_read_request'}
instructions[2389] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2390] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709593509616, 'op': 'memory_read_wait'}
instructions[2391] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139709593509616, 'element_size': 2, 'op': 'memory_read'}
instructions[2392] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2393] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2394] = {6'd12, 8'd140, 8'd141, 32'd32};//{'src': 141, 'right': 32, 'dest': 140, 'signed': False, 'op': '&', 'type': 'int', 'size': 2}
instructions[2395] = {6'd3, 8'd140, 8'd109, 32'd0};//{'dest': 140, 'src': 109, 'op': 'move'}
instructions[2396] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2397] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2398] = {6'd3, 8'd107, 8'd140, 32'd0};//{'dest': 107, 'src': 140, 'op': 'move'}
instructions[2399] = {6'd6, 8'd0, 8'd106, 32'd0};//{'src': 106, 'op': 'jmp_to_reg'}
instructions[2400] = {6'd0, 8'd119, 8'd0, 32'd0};//{'dest': 119, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2401] = {6'd0, 8'd120, 8'd0, 32'd0};//{'dest': 120, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2402] = {6'd3, 8'd140, 8'd117, 32'd0};//{'dest': 140, 'src': 117, 'op': 'move'}
instructions[2403] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2404] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2405] = {6'd3, 8'd120, 8'd140, 32'd0};//{'dest': 120, 'src': 140, 'op': 'move'}
instructions[2406] = {6'd3, 8'd141, 8'd118, 32'd0};//{'dest': 141, 'src': 118, 'op': 'move'}
instructions[2407] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2408] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2409] = {6'd3, 8'd3, 8'd141, 32'd0};//{'dest': 3, 'src': 141, 'op': 'move'}
instructions[2410] = {6'd1, 8'd2, 8'd0, 32'd39};//{'dest': 2, 'label': 39, 'op': 'jmp_and_link'}
instructions[2411] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2412] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2413] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2414] = {6'd3, 8'd119, 8'd140, 32'd0};//{'dest': 119, 'src': 140, 'op': 'move'}
instructions[2415] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2416] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2417] = {6'd3, 8'd141, 8'd119, 32'd0};//{'dest': 141, 'src': 119, 'op': 'move'}
instructions[2418] = {6'd3, 8'd142, 8'd118, 32'd0};//{'dest': 142, 'src': 118, 'op': 'move'}
instructions[2419] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2420] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2421] = {6'd20, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '<', 'type': 'int', 'size': 2}
instructions[2422] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2423] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2424] = {6'd13, 8'd0, 8'd140, 32'd2449};//{'src': 140, 'label': 2449, 'op': 'jmp_if_false'}
instructions[2425] = {6'd3, 8'd142, 8'd120, 32'd0};//{'dest': 142, 'src': 120, 'op': 'move'}
instructions[2426] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2427] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2428] = {6'd11, 8'd146, 8'd142, 32'd116};//{'dest': 146, 'src': 142, 'srcb': 116, 'signed': False, 'op': '+'}
instructions[2429] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2430] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2431] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592358208, 'op': 'memory_read_request'}
instructions[2432] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2433] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592358208, 'op': 'memory_read_wait'}
instructions[2434] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139709592358208, 'element_size': 2, 'op': 'memory_read'}
instructions[2435] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2436] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2437] = {6'd3, 8'd3, 8'd141, 32'd0};//{'dest': 3, 'src': 141, 'op': 'move'}
instructions[2438] = {6'd1, 8'd2, 8'd0, 32'd39};//{'dest': 2, 'label': 39, 'op': 'jmp_and_link'}
instructions[2439] = {6'd3, 8'd140, 8'd120, 32'd0};//{'dest': 140, 'src': 120, 'op': 'move'}
instructions[2440] = {6'd14, 8'd120, 8'd120, 32'd1};//{'src': 120, 'right': 1, 'dest': 120, 'signed': False, 'op': '+', 'size': 2}
instructions[2441] = {6'd3, 8'd141, 8'd119, 32'd0};//{'dest': 141, 'src': 119, 'op': 'move'}
instructions[2442] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2443] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2444] = {6'd14, 8'd140, 8'd141, 32'd2};//{'src': 141, 'right': 2, 'dest': 140, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2445] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2446] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2447] = {6'd3, 8'd119, 8'd140, 32'd0};//{'dest': 119, 'src': 140, 'op': 'move'}
instructions[2448] = {6'd15, 8'd0, 8'd0, 32'd2415};//{'label': 2415, 'op': 'goto'}
instructions[2449] = {6'd6, 8'd0, 8'd115, 32'd0};//{'src': 115, 'op': 'jmp_to_reg'}
instructions[2450] = {6'd0, 8'd125, 8'd0, 32'd0};//{'dest': 125, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2451] = {6'd0, 8'd126, 8'd0, 32'd0};//{'dest': 126, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2452] = {6'd0, 8'd127, 8'd0, 32'd0};//{'dest': 127, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2453] = {6'd38, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'input': 'socket', 'op': 'ready'}
instructions[2454] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2455] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2456] = {6'd39, 8'd140, 8'd141, 32'd0};//{'src': 141, 'right': 0, 'dest': 140, 'signed': True, 'op': '==', 'type': 'int', 'size': 2}
instructions[2457] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2458] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2459] = {6'd13, 8'd0, 8'd140, 32'd2466};//{'src': 140, 'label': 2466, 'op': 'jmp_if_false'}
instructions[2460] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2461] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2462] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2463] = {6'd3, 8'd122, 8'd140, 32'd0};//{'dest': 122, 'src': 140, 'op': 'move'}
instructions[2464] = {6'd6, 8'd0, 8'd121, 32'd0};//{'src': 121, 'op': 'jmp_to_reg'}
instructions[2465] = {6'd15, 8'd0, 8'd0, 32'd2466};//{'label': 2466, 'op': 'goto'}
instructions[2466] = {6'd3, 8'd140, 8'd124, 32'd0};//{'dest': 140, 'src': 124, 'op': 'move'}
instructions[2467] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2468] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2469] = {6'd3, 8'd126, 8'd140, 32'd0};//{'dest': 126, 'src': 140, 'op': 'move'}
instructions[2470] = {6'd1, 8'd8, 8'd0, 32'd54};//{'dest': 8, 'label': 54, 'op': 'jmp_and_link'}
instructions[2471] = {6'd3, 8'd140, 8'd9, 32'd0};//{'dest': 140, 'src': 9, 'op': 'move'}
instructions[2472] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2473] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2474] = {6'd3, 8'd127, 8'd140, 32'd0};//{'dest': 127, 'src': 140, 'op': 'move'}
instructions[2475] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2476] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2477] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2478] = {6'd3, 8'd125, 8'd140, 32'd0};//{'dest': 125, 'src': 140, 'op': 'move'}
instructions[2479] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2480] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2481] = {6'd3, 8'd141, 8'd125, 32'd0};//{'dest': 141, 'src': 125, 'op': 'move'}
instructions[2482] = {6'd3, 8'd142, 8'd127, 32'd0};//{'dest': 142, 'src': 127, 'op': 'move'}
instructions[2483] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2484] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2485] = {6'd20, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '<', 'type': 'int', 'size': 2}
instructions[2486] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2487] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2488] = {6'd13, 8'd0, 8'd140, 32'd2508};//{'src': 140, 'label': 2508, 'op': 'jmp_if_false'}
instructions[2489] = {6'd1, 8'd8, 8'd0, 32'd54};//{'dest': 8, 'label': 54, 'op': 'jmp_and_link'}
instructions[2490] = {6'd3, 8'd140, 8'd9, 32'd0};//{'dest': 140, 'src': 9, 'op': 'move'}
instructions[2491] = {6'd3, 8'd141, 8'd126, 32'd0};//{'dest': 141, 'src': 126, 'op': 'move'}
instructions[2492] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2493] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2494] = {6'd11, 8'd142, 8'd141, 32'd123};//{'dest': 142, 'src': 141, 'srcb': 123, 'signed': False, 'op': '+'}
instructions[2495] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2496] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2497] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2498] = {6'd3, 8'd140, 8'd126, 32'd0};//{'dest': 140, 'src': 126, 'op': 'move'}
instructions[2499] = {6'd14, 8'd126, 8'd126, 32'd1};//{'src': 126, 'right': 1, 'dest': 126, 'signed': False, 'op': '+', 'size': 2}
instructions[2500] = {6'd3, 8'd141, 8'd125, 32'd0};//{'dest': 141, 'src': 125, 'op': 'move'}
instructions[2501] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2502] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2503] = {6'd14, 8'd140, 8'd141, 32'd2};//{'src': 141, 'right': 2, 'dest': 140, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2504] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2505] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2506] = {6'd3, 8'd125, 8'd140, 32'd0};//{'dest': 125, 'src': 140, 'op': 'move'}
instructions[2507] = {6'd15, 8'd0, 8'd0, 32'd2479};//{'label': 2479, 'op': 'goto'}
instructions[2508] = {6'd3, 8'd140, 8'd127, 32'd0};//{'dest': 140, 'src': 127, 'op': 'move'}
instructions[2509] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2510] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2511] = {6'd3, 8'd122, 8'd140, 32'd0};//{'dest': 122, 'src': 140, 'op': 'move'}
instructions[2512] = {6'd6, 8'd0, 8'd121, 32'd0};//{'src': 121, 'op': 'jmp_to_reg'}
instructions[2513] = {6'd0, 8'd129, 8'd0, 32'd638};//{'dest': 129, 'literal': 638, 'op': 'literal'}
instructions[2514] = {6'd0, 8'd130, 8'd0, 32'd1662};//{'dest': 130, 'literal': 1662, 'op': 'literal'}
instructions[2515] = {6'd0, 8'd131, 8'd0, 32'd27};//{'dest': 131, 'literal': 27, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2516] = {6'd0, 8'd132, 8'd0, 32'd0};//{'dest': 132, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2517] = {6'd0, 8'd133, 8'd0, 32'd0};//{'dest': 133, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2518] = {6'd0, 8'd134, 8'd0, 32'd0};//{'dest': 134, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2519] = {6'd0, 8'd135, 8'd0, 32'd0};//{'dest': 135, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2520] = {6'd0, 8'd136, 8'd0, 32'd0};//{'dest': 136, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2521] = {6'd0, 8'd137, 8'd0, 32'd0};//{'dest': 137, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2522] = {6'd0, 8'd138, 8'd0, 32'd0};//{'dest': 138, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2523] = {6'd0, 8'd139, 8'd0, 32'd0};//{'dest': 139, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2524] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2525] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2526] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2527] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2528] = {6'd26, 8'd142, 8'd141, 32'd79};//{'dest': 142, 'src': 141, 'srcb': 79, 'signed': True, 'op': '+'}
instructions[2529] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2530] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2531] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2532] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2533] = {6'd0, 8'd141, 8'd0, 32'd1};//{'dest': 141, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2534] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2535] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2536] = {6'd26, 8'd142, 8'd141, 32'd79};//{'dest': 142, 'src': 141, 'srcb': 79, 'signed': True, 'op': '+'}
instructions[2537] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2538] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2539] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2540] = {6'd3, 8'd140, 8'd133, 32'd0};//{'dest': 140, 'src': 133, 'op': 'move'}
instructions[2541] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2542] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2543] = {6'd13, 8'd0, 8'd140, 32'd2547};//{'src': 140, 'label': 2547, 'op': 'jmp_if_false'}
instructions[2544] = {6'd3, 8'd140, 8'd133, 32'd0};//{'dest': 140, 'src': 133, 'op': 'move'}
instructions[2545] = {6'd35, 8'd133, 8'd133, 32'd1};//{'src': 133, 'right': 1, 'dest': 133, 'signed': False, 'op': '-', 'size': 2}
instructions[2546] = {6'd15, 8'd0, 8'd0, 32'd2814};//{'label': 2814, 'op': 'goto'}
instructions[2547] = {6'd0, 8'd140, 8'd0, 32'd120};//{'dest': 140, 'literal': 120, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2548] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2549] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2550] = {6'd3, 8'd133, 8'd140, 32'd0};//{'dest': 133, 'src': 140, 'op': 'move'}
instructions[2551] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2552] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2553] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2554] = {6'd3, 8'd139, 8'd140, 32'd0};//{'dest': 139, 'src': 140, 'op': 'move'}
instructions[2555] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2556] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2557] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2558] = {6'd3, 8'd84, 8'd140, 32'd0};//{'dest': 84, 'src': 140, 'op': 'move'}
instructions[2559] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2560] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2561] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2562] = {6'd3, 8'd83, 8'd140, 32'd0};//{'dest': 83, 'src': 140, 'op': 'move'}
instructions[2563] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2564] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2565] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2566] = {6'd3, 8'd87, 8'd140, 32'd0};//{'dest': 87, 'src': 140, 'op': 'move'}
instructions[2567] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2568] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2569] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2570] = {6'd3, 8'd85, 8'd140, 32'd0};//{'dest': 85, 'src': 140, 'op': 'move'}
instructions[2571] = {6'd0, 8'd140, 8'd0, 32'd46};//{'dest': 140, 'literal': 46, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2572] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2573] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2574] = {6'd40, 8'd0, 8'd140, 32'd0};//{'src': 140, 'signed': True, 'file': '/home/amer/Nexys3/GitHub/TCP11/source/server.h', 'line': 552, 'type': 'int', 'op': 'report'}
instructions[2575] = {6'd0, 8'd141, 8'd0, 32'd46};//{'dest': 141, 'literal': 46, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2576] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2577] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2578] = {6'd3, 8'd1, 8'd141, 32'd0};//{'dest': 1, 'src': 141, 'op': 'move'}
instructions[2579] = {6'd1, 8'd0, 8'd0, 32'd34};//{'dest': 0, 'label': 34, 'op': 'jmp_and_link'}
instructions[2580] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2581] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2582] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2583] = {6'd3, 8'd136, 8'd140, 32'd0};//{'dest': 136, 'src': 140, 'op': 'move'}
instructions[2584] = {6'd0, 8'd140, 8'd0, 32'd24};//{'dest': 140, 'literal': 24, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2585] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2586] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2587] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2588] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2589] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2590] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2591] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2592] = {6'd0, 8'd140, 8'd0, 32'd62290};//{'dest': 140, 'literal': 62290, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2593] = {6'd0, 8'd141, 8'd0, 32'd1};//{'dest': 141, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2594] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2595] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2596] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2597] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2598] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2599] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2600] = {6'd0, 8'd140, 8'd0, 32'd64494};//{'dest': 140, 'literal': 64494, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2601] = {6'd0, 8'd141, 8'd0, 32'd2};//{'dest': 141, 'literal': 2, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2602] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2603] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2604] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2605] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2606] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2607] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2608] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2609] = {6'd0, 8'd141, 8'd0, 32'd3};//{'dest': 141, 'literal': 3, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2610] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2611] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2612] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2613] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2614] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2615] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2616] = {6'd0, 8'd140, 8'd0, 32'd515};//{'dest': 140, 'literal': 515, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2617] = {6'd0, 8'd141, 8'd0, 32'd4};//{'dest': 141, 'literal': 4, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2618] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2619] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2620] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2621] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2622] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2623] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2624] = {6'd0, 8'd140, 8'd0, 32'd1029};//{'dest': 140, 'literal': 1029, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2625] = {6'd0, 8'd141, 8'd0, 32'd5};//{'dest': 141, 'literal': 5, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2626] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2627] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2628] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2629] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2630] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2631] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2632] = {6'd0, 8'd140, 8'd0, 32'd2054};//{'dest': 140, 'literal': 2054, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2633] = {6'd0, 8'd141, 8'd0, 32'd6};//{'dest': 141, 'literal': 6, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2634] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2635] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2636] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2637] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2638] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2639] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2640] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2641] = {6'd0, 8'd141, 8'd0, 32'd7};//{'dest': 141, 'literal': 7, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2642] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2643] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2644] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2645] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2646] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2647] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2648] = {6'd0, 8'd140, 8'd0, 32'd2048};//{'dest': 140, 'literal': 2048, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2649] = {6'd0, 8'd141, 8'd0, 32'd8};//{'dest': 141, 'literal': 8, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2650] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2651] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2652] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2653] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2654] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2655] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2656] = {6'd0, 8'd140, 8'd0, 32'd1540};//{'dest': 140, 'literal': 1540, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2657] = {6'd0, 8'd141, 8'd0, 32'd9};//{'dest': 141, 'literal': 9, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2658] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2659] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2660] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2661] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2662] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2663] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2664] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2665] = {6'd0, 8'd141, 8'd0, 32'd10};//{'dest': 141, 'literal': 10, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2666] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2667] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2668] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2669] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2670] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2671] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2672] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2673] = {6'd0, 8'd141, 8'd0, 32'd11};//{'dest': 141, 'literal': 11, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2674] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2675] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2676] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2677] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2678] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2679] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2680] = {6'd0, 8'd140, 8'd0, 32'd515};//{'dest': 140, 'literal': 515, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2681] = {6'd0, 8'd141, 8'd0, 32'd12};//{'dest': 141, 'literal': 12, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2682] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2683] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2684] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2685] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2686] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2687] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2688] = {6'd0, 8'd140, 8'd0, 32'd1029};//{'dest': 140, 'literal': 1029, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2689] = {6'd0, 8'd141, 8'd0, 32'd13};//{'dest': 141, 'literal': 13, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2690] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2691] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2692] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2693] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2694] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2695] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2696] = {6'd0, 8'd140, 8'd0, 32'd49320};//{'dest': 140, 'literal': 49320, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2697] = {6'd0, 8'd141, 8'd0, 32'd14};//{'dest': 141, 'literal': 14, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2698] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2699] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2700] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2701] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2702] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2703] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2704] = {6'd0, 8'd140, 8'd0, 32'd119};//{'dest': 140, 'literal': 119, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2705] = {6'd0, 8'd141, 8'd0, 32'd15};//{'dest': 141, 'literal': 15, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2706] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2707] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2708] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2709] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2710] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2711] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2712] = {6'd0, 8'd140, 8'd0, 32'd24};//{'dest': 140, 'literal': 24, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2713] = {6'd0, 8'd141, 8'd0, 32'd16};//{'dest': 141, 'literal': 16, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2714] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2715] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2716] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2717] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2718] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2719] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2720] = {6'd0, 8'd140, 8'd0, 32'd62290};//{'dest': 140, 'literal': 62290, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2721] = {6'd0, 8'd141, 8'd0, 32'd17};//{'dest': 141, 'literal': 17, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2722] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2723] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2724] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2725] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2726] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2727] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2728] = {6'd0, 8'd140, 8'd0, 32'd64494};//{'dest': 140, 'literal': 64494, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2729] = {6'd0, 8'd141, 8'd0, 32'd18};//{'dest': 141, 'literal': 18, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2730] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2731] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2732] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2733] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2734] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2735] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2736] = {6'd0, 8'd140, 8'd0, 32'd49320};//{'dest': 140, 'literal': 49320, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2737] = {6'd0, 8'd141, 8'd0, 32'd19};//{'dest': 141, 'literal': 19, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2738] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2739] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2740] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2741] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2742] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2743] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2744] = {6'd0, 8'd140, 8'd0, 32'd105};//{'dest': 140, 'literal': 105, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2745] = {6'd0, 8'd141, 8'd0, 32'd20};//{'dest': 141, 'literal': 20, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2746] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2747] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2748] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2749] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2750] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2751] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2752] = {6'd0, 8'd140, 8'd0, 32'd58291};//{'dest': 140, 'literal': 58291, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2753] = {6'd0, 8'd141, 8'd0, 32'd21};//{'dest': 141, 'literal': 21, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2754] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2755] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2756] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2757] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2758] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2759] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2760] = {6'd0, 8'd140, 8'd0, 32'd12976};//{'dest': 140, 'literal': 12976, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2761] = {6'd0, 8'd141, 8'd0, 32'd22};//{'dest': 141, 'literal': 22, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2762] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2763] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2764] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2765] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2766] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2767] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2768] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2769] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2770] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2771] = {6'd3, 8'd135, 8'd140, 32'd0};//{'dest': 135, 'src': 140, 'op': 'move'}
instructions[2772] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2773] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2774] = {6'd3, 8'd141, 8'd135, 32'd0};//{'dest': 141, 'src': 135, 'op': 'move'}
instructions[2775] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2776] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2777] = {6'd27, 8'd140, 8'd141, 32'd46};//{'src': 141, 'right': 46, 'dest': 140, 'signed': False, 'op': '<', 'type': 'int', 'size': 2}
instructions[2778] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2779] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2780] = {6'd13, 8'd0, 8'd140, 32'd2805};//{'src': 140, 'label': 2805, 'op': 'jmp_if_false'}
instructions[2781] = {6'd3, 8'd142, 8'd136, 32'd0};//{'dest': 142, 'src': 136, 'op': 'move'}
instructions[2782] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2783] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2784] = {6'd11, 8'd146, 8'd142, 32'd130};//{'dest': 146, 'src': 142, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2785] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2786] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2787] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592441704, 'op': 'memory_read_request'}
instructions[2788] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2789] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592441704, 'op': 'memory_read_wait'}
instructions[2790] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139709592441704, 'element_size': 2, 'op': 'memory_read'}
instructions[2791] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2792] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2793] = {6'd3, 8'd1, 8'd141, 32'd0};//{'dest': 1, 'src': 141, 'op': 'move'}
instructions[2794] = {6'd1, 8'd0, 8'd0, 32'd34};//{'dest': 0, 'label': 34, 'op': 'jmp_and_link'}
instructions[2795] = {6'd3, 8'd140, 8'd136, 32'd0};//{'dest': 140, 'src': 136, 'op': 'move'}
instructions[2796] = {6'd14, 8'd136, 8'd136, 32'd1};//{'src': 136, 'right': 1, 'dest': 136, 'signed': False, 'op': '+', 'size': 2}
instructions[2797] = {6'd3, 8'd141, 8'd135, 32'd0};//{'dest': 141, 'src': 135, 'op': 'move'}
instructions[2798] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2799] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2800] = {6'd14, 8'd140, 8'd141, 32'd2};//{'src': 141, 'right': 2, 'dest': 140, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2801] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2802] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2803] = {6'd3, 8'd135, 8'd140, 32'd0};//{'dest': 135, 'src': 140, 'op': 'move'}
instructions[2804] = {6'd15, 8'd0, 8'd0, 32'd2772};//{'label': 2772, 'op': 'goto'}
instructions[2805] = {6'd3, 8'd151, 8'd130, 32'd0};//{'dest': 151, 'src': 130, 'op': 'move'}
instructions[2806] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2807] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2808] = {6'd3, 8'd98, 8'd151, 32'd0};//{'dest': 98, 'src': 151, 'op': 'move'}
instructions[2809] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2810] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2811] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2812] = {6'd3, 8'd99, 8'd141, 32'd0};//{'dest': 99, 'src': 141, 'op': 'move'}
instructions[2813] = {6'd1, 8'd97, 8'd0, 32'd1591};//{'dest': 97, 'label': 1591, 'op': 'jmp_and_link'}
instructions[2814] = {6'd3, 8'd140, 8'd139, 32'd0};//{'dest': 140, 'src': 139, 'op': 'move'}
instructions[2815] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2816] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2817] = {6'd39, 8'd141, 8'd140, 32'd0};//{'src': 140, 'right': 0, 'dest': 141, 'signed': True, 'op': '==', 'size': 2}
instructions[2818] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2819] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2820] = {6'd22, 8'd0, 8'd141, 32'd2837};//{'src': 141, 'label': 2837, 'op': 'jmp_if_true'}
instructions[2821] = {6'd39, 8'd141, 8'd140, 32'd1};//{'src': 140, 'right': 1, 'dest': 141, 'signed': True, 'op': '==', 'size': 2}
instructions[2822] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2823] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2824] = {6'd22, 8'd0, 8'd141, 32'd2854};//{'src': 141, 'label': 2854, 'op': 'jmp_if_true'}
instructions[2825] = {6'd39, 8'd141, 8'd140, 32'd2};//{'src': 140, 'right': 2, 'dest': 141, 'signed': True, 'op': '==', 'size': 2}
instructions[2826] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2827] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2828] = {6'd22, 8'd0, 8'd141, 32'd2920};//{'src': 141, 'label': 2920, 'op': 'jmp_if_true'}
instructions[2829] = {6'd39, 8'd141, 8'd140, 32'd3};//{'src': 140, 'right': 3, 'dest': 141, 'signed': True, 'op': '==', 'size': 2}
instructions[2830] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2831] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2832] = {6'd22, 8'd0, 8'd141, 32'd2999};//{'src': 141, 'label': 2999, 'op': 'jmp_if_true'}
instructions[2833] = {6'd39, 8'd141, 8'd140, 32'd4};//{'src': 140, 'right': 4, 'dest': 141, 'signed': True, 'op': '==', 'size': 2}
instructions[2834] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2835] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2836] = {6'd22, 8'd0, 8'd141, 32'd3009};//{'src': 141, 'label': 3009, 'op': 'jmp_if_true'}
instructions[2837] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2838] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2839] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2840] = {6'd3, 8'd85, 8'd140, 32'd0};//{'dest': 85, 'src': 140, 'op': 'move'}
instructions[2841] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2842] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2843] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2844] = {6'd3, 8'd84, 8'd140, 32'd0};//{'dest': 84, 'src': 140, 'op': 'move'}
instructions[2845] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2846] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2847] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2848] = {6'd3, 8'd83, 8'd140, 32'd0};//{'dest': 83, 'src': 140, 'op': 'move'}
instructions[2849] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2850] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2851] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2852] = {6'd3, 8'd87, 8'd140, 32'd0};//{'dest': 87, 'src': 140, 'op': 'move'}
instructions[2853] = {6'd15, 8'd0, 8'd0, 32'd3041};//{'label': 3041, 'op': 'goto'}
instructions[2854] = {6'd0, 8'd141, 8'd0, 32'd13};//{'dest': 141, 'literal': 13, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2855] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2856] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2857] = {6'd11, 8'd142, 8'd141, 32'd129};//{'dest': 142, 'src': 141, 'srcb': 129, 'signed': False, 'op': '+'}
instructions[2858] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2859] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2860] = {6'd17, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 139709592386376, 'op': 'memory_read_request'}
instructions[2861] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2862] = {6'd18, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 139709592386376, 'op': 'memory_read_wait'}
instructions[2863] = {6'd19, 8'd140, 8'd142, 32'd0};//{'dest': 140, 'src': 142, 'sequence': 139709592386376, 'element_size': 2, 'op': 'memory_read'}
instructions[2864] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2865] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2866] = {6'd3, 8'd75, 8'd140, 32'd0};//{'dest': 75, 'src': 140, 'op': 'move'}
instructions[2867] = {6'd0, 8'd141, 8'd0, 32'd14};//{'dest': 141, 'literal': 14, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2868] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2869] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2870] = {6'd11, 8'd142, 8'd141, 32'd129};//{'dest': 142, 'src': 141, 'srcb': 129, 'signed': False, 'op': '+'}
instructions[2871] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2872] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2873] = {6'd17, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 139709592386520, 'op': 'memory_read_request'}
instructions[2874] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2875] = {6'd18, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 139709592386520, 'op': 'memory_read_wait'}
instructions[2876] = {6'd19, 8'd140, 8'd142, 32'd0};//{'dest': 140, 'src': 142, 'sequence': 139709592386520, 'element_size': 2, 'op': 'memory_read'}
instructions[2877] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2878] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2879] = {6'd3, 8'd76, 8'd140, 32'd0};//{'dest': 76, 'src': 140, 'op': 'move'}
instructions[2880] = {6'd3, 8'd140, 8'd89, 32'd0};//{'dest': 140, 'src': 89, 'op': 'move'}
instructions[2881] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2882] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2883] = {6'd3, 8'd78, 8'd140, 32'd0};//{'dest': 78, 'src': 140, 'op': 'move'}
instructions[2884] = {6'd0, 8'd140, 8'd0, 32'd80};//{'dest': 140, 'literal': 80, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2885] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2886] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2887] = {6'd3, 8'd77, 8'd140, 32'd0};//{'dest': 77, 'src': 140, 'op': 'move'}
instructions[2888] = {6'd3, 8'd143, 8'd81, 32'd0};//{'dest': 143, 'src': 81, 'op': 'move'}
instructions[2889] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2890] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2891] = {6'd3, 8'd19, 8'd143, 32'd0};//{'dest': 19, 'src': 143, 'op': 'move'}
instructions[2892] = {6'd3, 8'd143, 8'd91, 32'd0};//{'dest': 143, 'src': 91, 'op': 'move'}
instructions[2893] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2894] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2895] = {6'd3, 8'd20, 8'd143, 32'd0};//{'dest': 20, 'src': 143, 'op': 'move'}
instructions[2896] = {6'd0, 8'd141, 8'd0, 32'd1};//{'dest': 141, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2897] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2898] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2899] = {6'd3, 8'd21, 8'd141, 32'd0};//{'dest': 21, 'src': 141, 'op': 'move'}
instructions[2900] = {6'd1, 8'd17, 8'd0, 32'd108};//{'dest': 17, 'label': 108, 'op': 'jmp_and_link'}
instructions[2901] = {6'd3, 8'd140, 8'd18, 32'd0};//{'dest': 140, 'src': 18, 'op': 'move'}
instructions[2902] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2903] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2904] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2905] = {6'd3, 8'd84, 8'd140, 32'd0};//{'dest': 84, 'src': 140, 'op': 'move'}
instructions[2906] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2907] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2908] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2909] = {6'd3, 8'd87, 8'd140, 32'd0};//{'dest': 87, 'src': 140, 'op': 'move'}
instructions[2910] = {6'd3, 8'd151, 8'd130, 32'd0};//{'dest': 151, 'src': 130, 'op': 'move'}
instructions[2911] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2912] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2913] = {6'd3, 8'd98, 8'd151, 32'd0};//{'dest': 98, 'src': 151, 'op': 'move'}
instructions[2914] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2915] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2916] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2917] = {6'd3, 8'd99, 8'd141, 32'd0};//{'dest': 99, 'src': 141, 'op': 'move'}
instructions[2918] = {6'd1, 8'd97, 8'd0, 32'd1591};//{'dest': 97, 'label': 1591, 'op': 'jmp_and_link'}
instructions[2919] = {6'd15, 8'd0, 8'd0, 32'd3041};//{'label': 3041, 'op': 'goto'}
instructions[2920] = {6'd3, 8'd151, 8'd130, 32'd0};//{'dest': 151, 'src': 130, 'op': 'move'}
instructions[2921] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2922] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2923] = {6'd3, 8'd123, 8'd151, 32'd0};//{'dest': 123, 'src': 151, 'op': 'move'}
instructions[2924] = {6'd3, 8'd141, 8'd131, 32'd0};//{'dest': 141, 'src': 131, 'op': 'move'}
instructions[2925] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2926] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2927] = {6'd3, 8'd124, 8'd141, 32'd0};//{'dest': 124, 'src': 141, 'op': 'move'}
instructions[2928] = {6'd1, 8'd121, 8'd0, 32'd2450};//{'dest': 121, 'label': 2450, 'op': 'jmp_and_link'}
instructions[2929] = {6'd3, 8'd140, 8'd122, 32'd0};//{'dest': 140, 'src': 122, 'op': 'move'}
instructions[2930] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2931] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2932] = {6'd3, 8'd132, 8'd140, 32'd0};//{'dest': 132, 'src': 140, 'op': 'move'}
instructions[2933] = {6'd0, 8'd146, 8'd0, 32'd0};//{'dest': 146, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2934] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2935] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2936] = {6'd11, 8'd147, 8'd146, 32'd80};//{'dest': 147, 'src': 146, 'srcb': 80, 'signed': False, 'op': '+'}
instructions[2937] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2938] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2939] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709592443864, 'op': 'memory_read_request'}
instructions[2940] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2941] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709592443864, 'op': 'memory_read_wait'}
instructions[2942] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139709592443864, 'element_size': 2, 'op': 'memory_read'}
instructions[2943] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2944] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2945] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2946] = {6'd11, 8'd142, 8'd141, 32'd79};//{'dest': 142, 'src': 141, 'srcb': 79, 'signed': False, 'op': '+'}
instructions[2947] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2948] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2949] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2950] = {6'd0, 8'd146, 8'd0, 32'd1};//{'dest': 146, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2951] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2952] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2953] = {6'd11, 8'd147, 8'd146, 32'd80};//{'dest': 147, 'src': 146, 'srcb': 80, 'signed': False, 'op': '+'}
instructions[2954] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2955] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2956] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709592444296, 'op': 'memory_read_request'}
instructions[2957] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2958] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709592444296, 'op': 'memory_read_wait'}
instructions[2959] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139709592444296, 'element_size': 2, 'op': 'memory_read'}
instructions[2960] = {6'd0, 8'd141, 8'd0, 32'd1};//{'dest': 141, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2961] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2962] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2963] = {6'd11, 8'd142, 8'd141, 32'd79};//{'dest': 142, 'src': 141, 'srcb': 79, 'signed': False, 'op': '+'}
instructions[2964] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2965] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2966] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2967] = {6'd3, 8'd143, 8'd80, 32'd0};//{'dest': 143, 'src': 80, 'op': 'move'}
instructions[2968] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2969] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2970] = {6'd3, 8'd19, 8'd143, 32'd0};//{'dest': 19, 'src': 143, 'op': 'move'}
instructions[2971] = {6'd3, 8'd143, 8'd79, 32'd0};//{'dest': 143, 'src': 79, 'op': 'move'}
instructions[2972] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2973] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2974] = {6'd3, 8'd20, 8'd143, 32'd0};//{'dest': 20, 'src': 143, 'op': 'move'}
instructions[2975] = {6'd3, 8'd141, 8'd132, 32'd0};//{'dest': 141, 'src': 132, 'op': 'move'}
instructions[2976] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2977] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2978] = {6'd3, 8'd21, 8'd141, 32'd0};//{'dest': 21, 'src': 141, 'op': 'move'}
instructions[2979] = {6'd1, 8'd17, 8'd0, 32'd108};//{'dest': 17, 'label': 108, 'op': 'jmp_and_link'}
instructions[2980] = {6'd3, 8'd140, 8'd18, 32'd0};//{'dest': 140, 'src': 18, 'op': 'move'}
instructions[2981] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2982] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2983] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2984] = {6'd3, 8'd84, 8'd140, 32'd0};//{'dest': 84, 'src': 140, 'op': 'move'}
instructions[2985] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2986] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2987] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2988] = {6'd3, 8'd87, 8'd140, 32'd0};//{'dest': 87, 'src': 140, 'op': 'move'}
instructions[2989] = {6'd3, 8'd151, 8'd130, 32'd0};//{'dest': 151, 'src': 130, 'op': 'move'}
instructions[2990] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2991] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2992] = {6'd3, 8'd98, 8'd151, 32'd0};//{'dest': 98, 'src': 151, 'op': 'move'}
instructions[2993] = {6'd3, 8'd141, 8'd132, 32'd0};//{'dest': 141, 'src': 132, 'op': 'move'}
instructions[2994] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2995] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2996] = {6'd3, 8'd99, 8'd141, 32'd0};//{'dest': 99, 'src': 141, 'op': 'move'}
instructions[2997] = {6'd1, 8'd97, 8'd0, 32'd1591};//{'dest': 97, 'label': 1591, 'op': 'jmp_and_link'}
instructions[2998] = {6'd15, 8'd0, 8'd0, 32'd3041};//{'label': 3041, 'op': 'goto'}
instructions[2999] = {6'd3, 8'd151, 8'd130, 32'd0};//{'dest': 151, 'src': 130, 'op': 'move'}
instructions[3000] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3001] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3002] = {6'd3, 8'd98, 8'd151, 32'd0};//{'dest': 98, 'src': 151, 'op': 'move'}
instructions[3003] = {6'd3, 8'd141, 8'd132, 32'd0};//{'dest': 141, 'src': 132, 'op': 'move'}
instructions[3004] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3005] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3006] = {6'd3, 8'd99, 8'd141, 32'd0};//{'dest': 99, 'src': 141, 'op': 'move'}
instructions[3007] = {6'd1, 8'd97, 8'd0, 32'd1591};//{'dest': 97, 'label': 1591, 'op': 'jmp_and_link'}
instructions[3008] = {6'd15, 8'd0, 8'd0, 32'd3041};//{'label': 3041, 'op': 'goto'}
instructions[3009] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3010] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3011] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3012] = {6'd3, 8'd83, 8'd140, 32'd0};//{'dest': 83, 'src': 140, 'op': 'move'}
instructions[3013] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3014] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3015] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3016] = {6'd3, 8'd87, 8'd140, 32'd0};//{'dest': 87, 'src': 140, 'op': 'move'}
instructions[3017] = {6'd3, 8'd143, 8'd81, 32'd0};//{'dest': 143, 'src': 81, 'op': 'move'}
instructions[3018] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3019] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3020] = {6'd3, 8'd19, 8'd143, 32'd0};//{'dest': 19, 'src': 143, 'op': 'move'}
instructions[3021] = {6'd3, 8'd143, 8'd91, 32'd0};//{'dest': 143, 'src': 91, 'op': 'move'}
instructions[3022] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3023] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3024] = {6'd3, 8'd20, 8'd143, 32'd0};//{'dest': 20, 'src': 143, 'op': 'move'}
instructions[3025] = {6'd0, 8'd141, 8'd0, 32'd1};//{'dest': 141, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3026] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3027] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3028] = {6'd3, 8'd21, 8'd141, 32'd0};//{'dest': 21, 'src': 141, 'op': 'move'}
instructions[3029] = {6'd1, 8'd17, 8'd0, 32'd108};//{'dest': 17, 'label': 108, 'op': 'jmp_and_link'}
instructions[3030] = {6'd3, 8'd140, 8'd18, 32'd0};//{'dest': 140, 'src': 18, 'op': 'move'}
instructions[3031] = {6'd3, 8'd151, 8'd130, 32'd0};//{'dest': 151, 'src': 130, 'op': 'move'}
instructions[3032] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3033] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3034] = {6'd3, 8'd98, 8'd151, 32'd0};//{'dest': 98, 'src': 151, 'op': 'move'}
instructions[3035] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3036] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3037] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3038] = {6'd3, 8'd99, 8'd141, 32'd0};//{'dest': 99, 'src': 141, 'op': 'move'}
instructions[3039] = {6'd1, 8'd97, 8'd0, 32'd1591};//{'dest': 97, 'label': 1591, 'op': 'jmp_and_link'}
instructions[3040] = {6'd15, 8'd0, 8'd0, 32'd3041};//{'label': 3041, 'op': 'goto'}
instructions[3041] = {6'd0, 8'd140, 8'd0, 32'd10000};//{'dest': 140, 'literal': 10000, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3042] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3043] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3044] = {6'd3, 8'd134, 8'd140, 32'd0};//{'dest': 134, 'src': 140, 'op': 'move'}
instructions[3045] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3046] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3047] = {6'd3, 8'd140, 8'd134, 32'd0};//{'dest': 140, 'src': 134, 'op': 'move'}
instructions[3048] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3049] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3050] = {6'd13, 8'd0, 8'd140, 32'd3436};//{'src': 140, 'label': 3436, 'op': 'jmp_if_false'}
instructions[3051] = {6'd3, 8'd151, 8'd129, 32'd0};//{'dest': 151, 'src': 129, 'op': 'move'}
instructions[3052] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3053] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3054] = {6'd3, 8'd108, 8'd151, 32'd0};//{'dest': 108, 'src': 151, 'op': 'move'}
instructions[3055] = {6'd1, 8'd106, 8'd0, 32'd2048};//{'dest': 106, 'label': 2048, 'op': 'jmp_and_link'}
instructions[3056] = {6'd3, 8'd140, 8'd107, 32'd0};//{'dest': 140, 'src': 107, 'op': 'move'}
instructions[3057] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3058] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3059] = {6'd3, 8'd135, 8'd140, 32'd0};//{'dest': 135, 'src': 140, 'op': 'move'}
instructions[3060] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3061] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3062] = {6'd3, 8'd140, 8'd135, 32'd0};//{'dest': 140, 'src': 135, 'op': 'move'}
instructions[3063] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3064] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3065] = {6'd13, 8'd0, 8'd140, 32'd3070};//{'src': 140, 'label': 3070, 'op': 'jmp_if_false'}
instructions[3066] = {6'd3, 8'd141, 8'd90, 32'd0};//{'dest': 141, 'src': 90, 'op': 'move'}
instructions[3067] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3068] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3069] = {6'd25, 8'd140, 8'd141, 32'd80};//{'src': 141, 'right': 80, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[3070] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3071] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3072] = {6'd13, 8'd0, 8'd140, 32'd3429};//{'src': 140, 'label': 3429, 'op': 'jmp_if_false'}
instructions[3073] = {6'd3, 8'd141, 8'd139, 32'd0};//{'dest': 141, 'src': 139, 'op': 'move'}
instructions[3074] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3075] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3076] = {6'd31, 8'd140, 8'd141, 32'd0};//{'src': 141, 'right': 0, 'dest': 140, 'signed': False, 'op': '!=', 'type': 'int', 'size': 2}
instructions[3077] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3078] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3079] = {6'd13, 8'd0, 8'd140, 32'd3085};//{'src': 140, 'label': 3085, 'op': 'jmp_if_false'}
instructions[3080] = {6'd3, 8'd141, 8'd89, 32'd0};//{'dest': 141, 'src': 89, 'op': 'move'}
instructions[3081] = {6'd3, 8'd142, 8'd78, 32'd0};//{'dest': 142, 'src': 78, 'op': 'move'}
instructions[3082] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3083] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3084] = {6'd21, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '!=', 'type': 'int', 'size': 2}
instructions[3085] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3086] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3087] = {6'd13, 8'd0, 8'd140, 32'd3090};//{'src': 140, 'label': 3090, 'op': 'jmp_if_false'}
instructions[3088] = {6'd15, 8'd0, 8'd0, 32'd3433};//{'label': 3433, 'op': 'goto'}
instructions[3089] = {6'd15, 8'd0, 8'd0, 32'd3090};//{'label': 3090, 'op': 'goto'}
instructions[3090] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3091] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3092] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3093] = {6'd3, 8'd138, 8'd140, 32'd0};//{'dest': 138, 'src': 140, 'op': 'move'}
instructions[3094] = {6'd3, 8'd140, 8'd139, 32'd0};//{'dest': 140, 'src': 139, 'op': 'move'}
instructions[3095] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3096] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3097] = {6'd3, 8'd137, 8'd140, 32'd0};//{'dest': 137, 'src': 140, 'op': 'move'}
instructions[3098] = {6'd3, 8'd140, 8'd139, 32'd0};//{'dest': 140, 'src': 139, 'op': 'move'}
instructions[3099] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3100] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3101] = {6'd39, 8'd141, 8'd140, 32'd0};//{'src': 140, 'right': 0, 'dest': 141, 'signed': True, 'op': '==', 'size': 2}
instructions[3102] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3103] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3104] = {6'd22, 8'd0, 8'd141, 32'd3121};//{'src': 141, 'label': 3121, 'op': 'jmp_if_true'}
instructions[3105] = {6'd39, 8'd141, 8'd140, 32'd1};//{'src': 140, 'right': 1, 'dest': 141, 'signed': True, 'op': '==', 'size': 2}
instructions[3106] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3107] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3108] = {6'd22, 8'd0, 8'd141, 32'd3144};//{'src': 141, 'label': 3144, 'op': 'jmp_if_true'}
instructions[3109] = {6'd39, 8'd141, 8'd140, 32'd2};//{'src': 140, 'right': 2, 'dest': 141, 'signed': True, 'op': '==', 'size': 2}
instructions[3110] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3111] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3112] = {6'd22, 8'd0, 8'd141, 32'd3222};//{'src': 141, 'label': 3222, 'op': 'jmp_if_true'}
instructions[3113] = {6'd39, 8'd141, 8'd140, 32'd3};//{'src': 140, 'right': 3, 'dest': 141, 'signed': True, 'op': '==', 'size': 2}
instructions[3114] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3115] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3116] = {6'd22, 8'd0, 8'd141, 32'd3258};//{'src': 141, 'label': 3258, 'op': 'jmp_if_true'}
instructions[3117] = {6'd39, 8'd141, 8'd140, 32'd4};//{'src': 140, 'right': 4, 'dest': 141, 'signed': True, 'op': '==', 'size': 2}
instructions[3118] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3119] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3120] = {6'd22, 8'd0, 8'd141, 32'd3346};//{'src': 141, 'label': 3346, 'op': 'jmp_if_true'}
instructions[3121] = {6'd3, 8'd140, 8'd94, 32'd0};//{'dest': 140, 'src': 94, 'op': 'move'}
instructions[3122] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3123] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3124] = {6'd13, 8'd0, 8'd140, 32'd3130};//{'src': 140, 'label': 3130, 'op': 'jmp_if_false'}
instructions[3125] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3126] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3127] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3128] = {6'd3, 8'd139, 8'd140, 32'd0};//{'dest': 139, 'src': 140, 'op': 'move'}
instructions[3129] = {6'd15, 8'd0, 8'd0, 32'd3143};//{'label': 3143, 'op': 'goto'}
instructions[3130] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3131] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3132] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3133] = {6'd3, 8'd85, 8'd140, 32'd0};//{'dest': 85, 'src': 140, 'op': 'move'}
instructions[3134] = {6'd3, 8'd151, 8'd130, 32'd0};//{'dest': 151, 'src': 130, 'op': 'move'}
instructions[3135] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3136] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3137] = {6'd3, 8'd98, 8'd151, 32'd0};//{'dest': 98, 'src': 151, 'op': 'move'}
instructions[3138] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3139] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3140] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3141] = {6'd3, 8'd99, 8'd141, 32'd0};//{'dest': 99, 'src': 141, 'op': 'move'}
instructions[3142] = {6'd1, 8'd97, 8'd0, 32'd1591};//{'dest': 97, 'label': 1591, 'op': 'jmp_and_link'}
instructions[3143] = {6'd15, 8'd0, 8'd0, 32'd3356};//{'label': 3356, 'op': 'goto'}
instructions[3144] = {6'd3, 8'd140, 8'd96, 32'd0};//{'dest': 140, 'src': 96, 'op': 'move'}
instructions[3145] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3146] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3147] = {6'd13, 8'd0, 8'd140, 32'd3221};//{'src': 140, 'label': 3221, 'op': 'jmp_if_false'}
instructions[3148] = {6'd0, 8'd146, 8'd0, 32'd1};//{'dest': 146, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3149] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3150] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3151] = {6'd11, 8'd147, 8'd146, 32'd92};//{'dest': 147, 'src': 146, 'srcb': 92, 'signed': False, 'op': '+'}
instructions[3152] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3153] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3154] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709591957944, 'op': 'memory_read_request'}
instructions[3155] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3156] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709591957944, 'op': 'memory_read_wait'}
instructions[3157] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139709591957944, 'element_size': 2, 'op': 'memory_read'}
instructions[3158] = {6'd0, 8'd141, 8'd0, 32'd1};//{'dest': 141, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3159] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3160] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3161] = {6'd11, 8'd142, 8'd141, 32'd79};//{'dest': 142, 'src': 141, 'srcb': 79, 'signed': False, 'op': '+'}
instructions[3162] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3163] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3164] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[3165] = {6'd0, 8'd146, 8'd0, 32'd0};//{'dest': 146, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3166] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3167] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3168] = {6'd11, 8'd147, 8'd146, 32'd92};//{'dest': 147, 'src': 146, 'srcb': 92, 'signed': False, 'op': '+'}
instructions[3169] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3170] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3171] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709591958376, 'op': 'memory_read_request'}
instructions[3172] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3173] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709591958376, 'op': 'memory_read_wait'}
instructions[3174] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139709591958376, 'element_size': 2, 'op': 'memory_read'}
instructions[3175] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3176] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3177] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3178] = {6'd11, 8'd142, 8'd141, 32'd79};//{'dest': 142, 'src': 141, 'srcb': 79, 'signed': False, 'op': '+'}
instructions[3179] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3180] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3181] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[3182] = {6'd0, 8'd146, 8'd0, 32'd1};//{'dest': 146, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3183] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3184] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3185] = {6'd11, 8'd147, 8'd146, 32'd92};//{'dest': 147, 'src': 146, 'srcb': 92, 'signed': False, 'op': '+'}
instructions[3186] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3187] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3188] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709591958808, 'op': 'memory_read_request'}
instructions[3189] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3190] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709591958808, 'op': 'memory_read_wait'}
instructions[3191] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139709591958808, 'element_size': 2, 'op': 'memory_read'}
instructions[3192] = {6'd0, 8'd141, 8'd0, 32'd1};//{'dest': 141, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3193] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3194] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3195] = {6'd11, 8'd142, 8'd141, 32'd80};//{'dest': 142, 'src': 141, 'srcb': 80, 'signed': False, 'op': '+'}
instructions[3196] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3197] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3198] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[3199] = {6'd0, 8'd146, 8'd0, 32'd0};//{'dest': 146, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3200] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3201] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3202] = {6'd11, 8'd147, 8'd146, 32'd92};//{'dest': 147, 'src': 146, 'srcb': 92, 'signed': False, 'op': '+'}
instructions[3203] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3204] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3205] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709591959240, 'op': 'memory_read_request'}
instructions[3206] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3207] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709591959240, 'op': 'memory_read_wait'}
instructions[3208] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139709591959240, 'element_size': 2, 'op': 'memory_read'}
instructions[3209] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3210] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3211] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3212] = {6'd11, 8'd142, 8'd141, 32'd80};//{'dest': 142, 'src': 141, 'srcb': 80, 'signed': False, 'op': '+'}
instructions[3213] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3214] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3215] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[3216] = {6'd0, 8'd140, 8'd0, 32'd2};//{'dest': 140, 'literal': 2, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3217] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3218] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3219] = {6'd3, 8'd139, 8'd140, 32'd0};//{'dest': 139, 'src': 140, 'op': 'move'}
instructions[3220] = {6'd15, 8'd0, 8'd0, 32'd3221};//{'label': 3221, 'op': 'goto'}
instructions[3221] = {6'd15, 8'd0, 8'd0, 32'd3356};//{'label': 3356, 'op': 'goto'}
instructions[3222] = {6'd3, 8'd143, 8'd81, 32'd0};//{'dest': 143, 'src': 81, 'op': 'move'}
instructions[3223] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3224] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3225] = {6'd3, 8'd19, 8'd143, 32'd0};//{'dest': 19, 'src': 143, 'op': 'move'}
instructions[3226] = {6'd3, 8'd143, 8'd91, 32'd0};//{'dest': 143, 'src': 91, 'op': 'move'}
instructions[3227] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3228] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3229] = {6'd3, 8'd20, 8'd143, 32'd0};//{'dest': 20, 'src': 143, 'op': 'move'}
instructions[3230] = {6'd3, 8'd141, 8'd104, 32'd0};//{'dest': 141, 'src': 104, 'op': 'move'}
instructions[3231] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3232] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3233] = {6'd3, 8'd21, 8'd141, 32'd0};//{'dest': 21, 'src': 141, 'op': 'move'}
instructions[3234] = {6'd1, 8'd17, 8'd0, 32'd108};//{'dest': 17, 'label': 108, 'op': 'jmp_and_link'}
instructions[3235] = {6'd3, 8'd140, 8'd18, 32'd0};//{'dest': 140, 'src': 18, 'op': 'move'}
instructions[3236] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3237] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3238] = {6'd3, 8'd138, 8'd140, 32'd0};//{'dest': 138, 'src': 140, 'op': 'move'}
instructions[3239] = {6'd3, 8'd140, 8'd93, 32'd0};//{'dest': 140, 'src': 93, 'op': 'move'}
instructions[3240] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3241] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3242] = {6'd13, 8'd0, 8'd140, 32'd3248};//{'src': 140, 'label': 3248, 'op': 'jmp_if_false'}
instructions[3243] = {6'd0, 8'd140, 8'd0, 32'd4};//{'dest': 140, 'literal': 4, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3244] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3245] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3246] = {6'd3, 8'd139, 8'd140, 32'd0};//{'dest': 139, 'src': 140, 'op': 'move'}
instructions[3247] = {6'd15, 8'd0, 8'd0, 32'd3257};//{'label': 3257, 'op': 'goto'}
instructions[3248] = {6'd3, 8'd140, 8'd132, 32'd0};//{'dest': 140, 'src': 132, 'op': 'move'}
instructions[3249] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3250] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3251] = {6'd13, 8'd0, 8'd140, 32'd3257};//{'src': 140, 'label': 3257, 'op': 'jmp_if_false'}
instructions[3252] = {6'd0, 8'd140, 8'd0, 32'd3};//{'dest': 140, 'literal': 3, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3253] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3254] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3255] = {6'd3, 8'd139, 8'd140, 32'd0};//{'dest': 139, 'src': 140, 'op': 'move'}
instructions[3256] = {6'd15, 8'd0, 8'd0, 32'd3257};//{'label': 3257, 'op': 'goto'}
instructions[3257] = {6'd15, 8'd0, 8'd0, 32'd3356};//{'label': 3356, 'op': 'goto'}
instructions[3258] = {6'd3, 8'd143, 8'd81, 32'd0};//{'dest': 143, 'src': 81, 'op': 'move'}
instructions[3259] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3260] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3261] = {6'd3, 8'd19, 8'd143, 32'd0};//{'dest': 19, 'src': 143, 'op': 'move'}
instructions[3262] = {6'd3, 8'd143, 8'd91, 32'd0};//{'dest': 143, 'src': 91, 'op': 'move'}
instructions[3263] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3264] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3265] = {6'd3, 8'd20, 8'd143, 32'd0};//{'dest': 20, 'src': 143, 'op': 'move'}
instructions[3266] = {6'd3, 8'd141, 8'd104, 32'd0};//{'dest': 141, 'src': 104, 'op': 'move'}
instructions[3267] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3268] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3269] = {6'd3, 8'd21, 8'd141, 32'd0};//{'dest': 21, 'src': 141, 'op': 'move'}
instructions[3270] = {6'd1, 8'd17, 8'd0, 32'd108};//{'dest': 17, 'label': 108, 'op': 'jmp_and_link'}
instructions[3271] = {6'd3, 8'd140, 8'd18, 32'd0};//{'dest': 140, 'src': 18, 'op': 'move'}
instructions[3272] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3273] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3274] = {6'd3, 8'd138, 8'd140, 32'd0};//{'dest': 138, 'src': 140, 'op': 'move'}
instructions[3275] = {6'd3, 8'd140, 8'd93, 32'd0};//{'dest': 140, 'src': 93, 'op': 'move'}
instructions[3276] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3277] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3278] = {6'd13, 8'd0, 8'd140, 32'd3284};//{'src': 140, 'label': 3284, 'op': 'jmp_if_false'}
instructions[3279] = {6'd0, 8'd140, 8'd0, 32'd4};//{'dest': 140, 'literal': 4, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3280] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3281] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3282] = {6'd3, 8'd139, 8'd140, 32'd0};//{'dest': 139, 'src': 140, 'op': 'move'}
instructions[3283] = {6'd15, 8'd0, 8'd0, 32'd3345};//{'label': 3345, 'op': 'goto'}
instructions[3284] = {6'd3, 8'd140, 8'd96, 32'd0};//{'dest': 140, 'src': 96, 'op': 'move'}
instructions[3285] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3286] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3287] = {6'd13, 8'd0, 8'd140, 32'd3311};//{'src': 140, 'label': 3311, 'op': 'jmp_if_false'}
instructions[3288] = {6'd0, 8'd142, 8'd0, 32'd1};//{'dest': 142, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3289] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3290] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3291] = {6'd11, 8'd146, 8'd142, 32'd80};//{'dest': 146, 'src': 142, 'srcb': 80, 'signed': False, 'op': '+'}
instructions[3292] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3293] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3294] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709591979720, 'op': 'memory_read_request'}
instructions[3295] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3296] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709591979720, 'op': 'memory_read_wait'}
instructions[3297] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139709591979720, 'element_size': 2, 'op': 'memory_read'}
instructions[3298] = {6'd0, 8'd146, 8'd0, 32'd1};//{'dest': 146, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3299] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3300] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3301] = {6'd11, 8'd147, 8'd146, 32'd92};//{'dest': 147, 'src': 146, 'srcb': 92, 'signed': False, 'op': '+'}
instructions[3302] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3303] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3304] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709591979864, 'op': 'memory_read_request'}
instructions[3305] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3306] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709591979864, 'op': 'memory_read_wait'}
instructions[3307] = {6'd19, 8'd142, 8'd147, 32'd0};//{'dest': 142, 'src': 147, 'sequence': 139709591979864, 'element_size': 2, 'op': 'memory_read'}
instructions[3308] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3309] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3310] = {6'd28, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[3311] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3312] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3313] = {6'd13, 8'd0, 8'd140, 32'd3337};//{'src': 140, 'label': 3337, 'op': 'jmp_if_false'}
instructions[3314] = {6'd0, 8'd142, 8'd0, 32'd0};//{'dest': 142, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3315] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3316] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3317] = {6'd11, 8'd146, 8'd142, 32'd80};//{'dest': 146, 'src': 142, 'srcb': 80, 'signed': False, 'op': '+'}
instructions[3318] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3319] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3320] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709591980152, 'op': 'memory_read_request'}
instructions[3321] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3322] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709591980152, 'op': 'memory_read_wait'}
instructions[3323] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139709591980152, 'element_size': 2, 'op': 'memory_read'}
instructions[3324] = {6'd0, 8'd146, 8'd0, 32'd0};//{'dest': 146, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3325] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3326] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3327] = {6'd11, 8'd147, 8'd146, 32'd92};//{'dest': 147, 'src': 146, 'srcb': 92, 'signed': False, 'op': '+'}
instructions[3328] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3329] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3330] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709591980296, 'op': 'memory_read_request'}
instructions[3331] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3332] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709591980296, 'op': 'memory_read_wait'}
instructions[3333] = {6'd19, 8'd142, 8'd147, 32'd0};//{'dest': 142, 'src': 147, 'sequence': 139709591980296, 'element_size': 2, 'op': 'memory_read'}
instructions[3334] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3335] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3336] = {6'd28, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[3337] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3338] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3339] = {6'd13, 8'd0, 8'd140, 32'd3345};//{'src': 140, 'label': 3345, 'op': 'jmp_if_false'}
instructions[3340] = {6'd0, 8'd140, 8'd0, 32'd2};//{'dest': 140, 'literal': 2, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3341] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3342] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3343] = {6'd3, 8'd139, 8'd140, 32'd0};//{'dest': 139, 'src': 140, 'op': 'move'}
instructions[3344] = {6'd15, 8'd0, 8'd0, 32'd3345};//{'label': 3345, 'op': 'goto'}
instructions[3345] = {6'd15, 8'd0, 8'd0, 32'd3356};//{'label': 3356, 'op': 'goto'}
instructions[3346] = {6'd3, 8'd140, 8'd96, 32'd0};//{'dest': 140, 'src': 96, 'op': 'move'}
instructions[3347] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3348] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3349] = {6'd13, 8'd0, 8'd140, 32'd3355};//{'src': 140, 'label': 3355, 'op': 'jmp_if_false'}
instructions[3350] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3351] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3352] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3353] = {6'd3, 8'd139, 8'd140, 32'd0};//{'dest': 139, 'src': 140, 'op': 'move'}
instructions[3354] = {6'd15, 8'd0, 8'd0, 32'd3355};//{'label': 3355, 'op': 'goto'}
instructions[3355] = {6'd15, 8'd0, 8'd0, 32'd3356};//{'label': 3356, 'op': 'goto'}
instructions[3356] = {6'd3, 8'd140, 8'd95, 32'd0};//{'dest': 140, 'src': 95, 'op': 'move'}
instructions[3357] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3358] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3359] = {6'd13, 8'd0, 8'd140, 32'd3365};//{'src': 140, 'label': 3365, 'op': 'jmp_if_false'}
instructions[3360] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3361] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3362] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3363] = {6'd3, 8'd139, 8'd140, 32'd0};//{'dest': 139, 'src': 140, 'op': 'move'}
instructions[3364] = {6'd15, 8'd0, 8'd0, 32'd3365};//{'label': 3365, 'op': 'goto'}
instructions[3365] = {6'd3, 8'd140, 8'd138, 32'd0};//{'dest': 140, 'src': 138, 'op': 'move'}
instructions[3366] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3367] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3368] = {6'd13, 8'd0, 8'd140, 32'd3401};//{'src': 140, 'label': 3401, 'op': 'jmp_if_false'}
instructions[3369] = {6'd3, 8'd151, 8'd129, 32'd0};//{'dest': 151, 'src': 129, 'op': 'move'}
instructions[3370] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3371] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3372] = {6'd3, 8'd116, 8'd151, 32'd0};//{'dest': 116, 'src': 151, 'op': 'move'}
instructions[3373] = {6'd3, 8'd141, 8'd105, 32'd0};//{'dest': 141, 'src': 105, 'op': 'move'}
instructions[3374] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3375] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3376] = {6'd3, 8'd117, 8'd141, 32'd0};//{'dest': 117, 'src': 141, 'op': 'move'}
instructions[3377] = {6'd3, 8'd141, 8'd104, 32'd0};//{'dest': 141, 'src': 104, 'op': 'move'}
instructions[3378] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3379] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3380] = {6'd3, 8'd118, 8'd141, 32'd0};//{'dest': 118, 'src': 141, 'op': 'move'}
instructions[3381] = {6'd1, 8'd115, 8'd0, 32'd2400};//{'dest': 115, 'label': 2400, 'op': 'jmp_and_link'}
instructions[3382] = {6'd3, 8'd141, 8'd139, 32'd0};//{'dest': 141, 'src': 139, 'op': 'move'}
instructions[3383] = {6'd3, 8'd142, 8'd137, 32'd0};//{'dest': 142, 'src': 137, 'op': 'move'}
instructions[3384] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3385] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3386] = {6'd28, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[3387] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3388] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3389] = {6'd13, 8'd0, 8'd140, 32'd3400};//{'src': 140, 'label': 3400, 'op': 'jmp_if_false'}
instructions[3390] = {6'd3, 8'd151, 8'd130, 32'd0};//{'dest': 151, 'src': 130, 'op': 'move'}
instructions[3391] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3392] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3393] = {6'd3, 8'd98, 8'd151, 32'd0};//{'dest': 98, 'src': 151, 'op': 'move'}
instructions[3394] = {6'd3, 8'd141, 8'd132, 32'd0};//{'dest': 141, 'src': 132, 'op': 'move'}
instructions[3395] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3396] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3397] = {6'd3, 8'd99, 8'd141, 32'd0};//{'dest': 99, 'src': 141, 'op': 'move'}
instructions[3398] = {6'd1, 8'd97, 8'd0, 32'd1591};//{'dest': 97, 'label': 1591, 'op': 'jmp_and_link'}
instructions[3399] = {6'd15, 8'd0, 8'd0, 32'd3400};//{'label': 3400, 'op': 'goto'}
instructions[3400] = {6'd15, 8'd0, 8'd0, 32'd3401};//{'label': 3401, 'op': 'goto'}
instructions[3401] = {6'd3, 8'd141, 8'd139, 32'd0};//{'dest': 141, 'src': 139, 'op': 'move'}
instructions[3402] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3403] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3404] = {6'd25, 8'd140, 8'd141, 32'd2};//{'src': 141, 'right': 2, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[3405] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3406] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3407] = {6'd13, 8'd0, 8'd140, 32'd3409};//{'src': 140, 'label': 3409, 'op': 'jmp_if_false'}
instructions[3408] = {6'd38, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'input': 'socket', 'op': 'ready'}
instructions[3409] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3410] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3411] = {6'd13, 8'd0, 8'd140, 32'd3414};//{'src': 140, 'label': 3414, 'op': 'jmp_if_false'}
instructions[3412] = {6'd15, 8'd0, 8'd0, 32'd3436};//{'label': 3436, 'op': 'goto'}
instructions[3413] = {6'd15, 8'd0, 8'd0, 32'd3414};//{'label': 3414, 'op': 'goto'}
instructions[3414] = {6'd3, 8'd141, 8'd139, 32'd0};//{'dest': 141, 'src': 139, 'op': 'move'}
instructions[3415] = {6'd3, 8'd142, 8'd137, 32'd0};//{'dest': 142, 'src': 137, 'op': 'move'}
instructions[3416] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3417] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3418] = {6'd21, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '!=', 'type': 'int', 'size': 2}
instructions[3419] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3420] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3421] = {6'd13, 8'd0, 8'd140, 32'd3428};//{'src': 140, 'label': 3428, 'op': 'jmp_if_false'}
instructions[3422] = {6'd0, 8'd140, 8'd0, 32'd120};//{'dest': 140, 'literal': 120, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3423] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3424] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3425] = {6'd3, 8'd133, 8'd140, 32'd0};//{'dest': 133, 'src': 140, 'op': 'move'}
instructions[3426] = {6'd15, 8'd0, 8'd0, 32'd3436};//{'label': 3436, 'op': 'goto'}
instructions[3427] = {6'd15, 8'd0, 8'd0, 32'd3428};//{'label': 3428, 'op': 'goto'}
instructions[3428] = {6'd15, 8'd0, 8'd0, 32'd3433};//{'label': 3433, 'op': 'goto'}
instructions[3429] = {6'd0, 8'd140, 8'd0, 32'd10000};//{'dest': 140, 'literal': 10000, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3430] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3431] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3432] = {6'd41, 8'd0, 8'd140, 32'd0};//{'src': 140, 'op': 'wait_clocks'}
instructions[3433] = {6'd3, 8'd140, 8'd134, 32'd0};//{'dest': 140, 'src': 134, 'op': 'move'}
instructions[3434] = {6'd35, 8'd134, 8'd134, 32'd1};//{'src': 134, 'right': 1, 'dest': 134, 'signed': False, 'op': '-', 'size': 2}
instructions[3435] = {6'd15, 8'd0, 8'd0, 32'd3045};//{'label': 3045, 'op': 'goto'}
instructions[3436] = {6'd15, 8'd0, 8'd0, 32'd2540};//{'label': 2540, 'op': 'goto'}
instructions[3437] = {6'd6, 8'd0, 8'd128, 32'd0};//{'src': 128, 'op': 'jmp_to_reg'}
end
//////////////////////////////////////////////////////////////////////////////
// CPU IMPLEMENTAION OF C PROCESS
//
// This section of the file contains a CPU implementing the C process.
always @(posedge clk)
begin
//implement memory for 2 byte x n arrays
if (memory_enable_2 == 1'b1) begin
memory_2[address_2] <= data_in_2;
end
data_out_2 <= memory_2[address_2];
memory_enable_2 <= 1'b0;
write_enable_2 <= 0;
//stage 0 instruction fetch
if (stage_0_enable) begin
stage_1_enable <= 1;
instruction_0 <= instructions[program_counter];
opcode_0 = instruction_0[53:48];
dest_0 = instruction_0[47:40];
src_0 = instruction_0[39:32];
srcb_0 = instruction_0[7:0];
literal_0 = instruction_0[31:0];
if(write_enable_2) begin
registers[dest_2] <= result_2;
end
program_counter_0 <= program_counter;
program_counter <= program_counter + 1;
end
//stage 1 opcode fetch
if (stage_1_enable) begin
stage_2_enable <= 1;
register_1 <= registers[src_0];
registerb_1 <= registers[srcb_0];
dest_1 <= dest_0;
literal_1 <= literal_0;
opcode_1 <= opcode_0;
program_counter_1 <= program_counter_0;
end
//stage 2 opcode fetch
if (stage_2_enable) begin
dest_2 <= dest_1;
case(opcode_1)
16'd0:
begin
result_2 <= literal_1;
write_enable_2 <= 1;
end
16'd1:
begin
program_counter <= literal_1;
result_2 <= program_counter_1 + 1;
write_enable_2 <= 1;
stage_0_enable <= 1;
stage_1_enable <= 0;
stage_2_enable <= 0;
end
16'd2:
begin
stage_0_enable <= 0;
stage_1_enable <= 0;
stage_2_enable <= 0;
end
16'd3:
begin
result_2 <= register_1;
write_enable_2 <= 1;
end
16'd5:
begin
stage_0_enable <= 0;
stage_1_enable <= 0;
stage_2_enable <= 0;
s_output_eth_tx_stb <= 1'b1;
s_output_eth_tx <= register_1;
end
16'd6:
begin
program_counter <= register_1;
stage_0_enable <= 1;
stage_1_enable <= 0;
stage_2_enable <= 0;
end
16'd7:
begin
stage_0_enable <= 0;
stage_1_enable <= 0;
stage_2_enable <= 0;
s_output_socket_stb <= 1'b1;
s_output_socket <= register_1;
end
16'd8:
begin
stage_0_enable <= 0;
stage_1_enable <= 0;
stage_2_enable <= 0;
s_input_eth_rx_ack <= 1'b1;
end
16'd9:
begin
result_2 <= 0;
result_2[0] <= input_eth_rx_stb;
write_enable_2 <= 1;
end
16'd10:
begin
stage_0_enable <= 0;
stage_1_enable <= 0;
stage_2_enable <= 0;
s_input_socket_ack <= 1'b1;
end
16'd11:
begin
result_2 <= $unsigned(register_1) + $unsigned(registerb_1);
write_enable_2 <= 1;
end
16'd12:
begin
result_2 <= $unsigned(register_1) & $unsigned(literal_1);
write_enable_2 <= 1;
end
16'd13:
begin
if (register_1 == 0) begin
program_counter <= literal_1;
stage_0_enable <= 1;
stage_1_enable <= 0;
stage_2_enable <= 0;
end
end
16'd14:
begin
result_2 <= $unsigned(register_1) + $unsigned(literal_1);
write_enable_2 <= 1;
end
16'd15:
begin
program_counter <= literal_1;
stage_0_enable <= 1;
stage_1_enable <= 0;
stage_2_enable <= 0;
end
16'd16:
begin
result_2 <= ~register_1;
write_enable_2 <= 1;
end
16'd17:
begin
address_2 <= register_1;
end
16'd19:
begin
result_2 <= data_out_2;
write_enable_2 <= 1;
end
16'd20:
begin
result_2 <= $unsigned(register_1) < $unsigned(registerb_1);
write_enable_2 <= 1;
end
16'd21:
begin
result_2 <= $unsigned(register_1) != $unsigned(registerb_1);
write_enable_2 <= 1;
end
16'd22:
begin
if (register_1 != 0) begin
program_counter <= literal_1;
stage_0_enable <= 1;
stage_1_enable <= 0;
stage_2_enable <= 0;
end
end
16'd23:
begin
address_2 <= register_1;
data_in_2 <= registerb_1;
memory_enable_2 <= 1'b1;
end
16'd24:
begin
$display ("%d (report at line: 107 in file: /home/amer/Nexys3/GitHub/TCP11/source/server.h)", $unsigned(register_1));
end
16'd25:
begin
result_2 <= $unsigned(register_1) == $unsigned(literal_1);
write_enable_2 <= 1;
end
16'd26:
begin
result_2 <= $signed(register_1) + $signed(registerb_1);
write_enable_2 <= 1;
end
16'd27:
begin
result_2 <= $unsigned(register_1) < $unsigned(literal_1);
write_enable_2 <= 1;
end
16'd28:
begin
result_2 <= $unsigned(register_1) == $unsigned(registerb_1);
write_enable_2 <= 1;
end
16'd29:
begin
result_2 <= $unsigned(literal_1) | $unsigned(register_1);
write_enable_2 <= 1;
end
16'd30:
begin
result_2 <= $unsigned(register_1) <= $unsigned(literal_1);
write_enable_2 <= 1;
end
16'd31:
begin
result_2 <= $unsigned(register_1) != $unsigned(literal_1);
write_enable_2 <= 1;
end
16'd32:
begin
result_2 <= $unsigned(register_1) >> $unsigned(literal_1);
write_enable_2 <= 1;
end
16'd33:
begin
result_2 <= $unsigned(register_1) << $unsigned(literal_1);
write_enable_2 <= 1;
end
16'd34:
begin
result_2 <= $unsigned(register_1) - $unsigned(registerb_1);
write_enable_2 <= 1;
end
16'd35:
begin
result_2 <= $unsigned(register_1) - $unsigned(literal_1);
write_enable_2 <= 1;
end
16'd36:
begin
result_2 <= $unsigned(register_1) <= $unsigned(registerb_1);
write_enable_2 <= 1;
end
16'd37:
begin
result_2 <= $unsigned(register_1) | $unsigned(literal_1);
write_enable_2 <= 1;
end
16'd38:
begin
result_2 <= 0;
result_2[0] <= input_socket_stb;
write_enable_2 <= 1;
end
16'd39:
begin
result_2 <= $signed(register_1) == $signed(literal_1);
write_enable_2 <= 1;
end
16'd40:
begin
$display ("%d (report at line: 552 in file: /home/amer/Nexys3/GitHub/TCP11/source/server.h)", $signed(register_1));
end
16'd41:
begin
timer <= register_1;
timer_enable <= 1;
stage_0_enable <= 0;
stage_1_enable <= 0;
stage_2_enable <= 0;
end
endcase
end
if (s_output_eth_tx_stb == 1'b1 && output_eth_tx_ack == 1'b1) begin
s_output_eth_tx_stb <= 1'b0;
stage_0_enable <= 1;
stage_1_enable <= 1;
stage_2_enable <= 1;
end
if (s_output_socket_stb == 1'b1 && output_socket_ack == 1'b1) begin
s_output_socket_stb <= 1'b0;
stage_0_enable <= 1;
stage_1_enable <= 1;
stage_2_enable <= 1;
end
if (s_input_eth_rx_ack == 1'b1 && input_eth_rx_stb == 1'b1) begin
result_2 <= input_eth_rx;
write_enable_2 <= 1;
s_input_eth_rx_ack <= 1'b0;
stage_0_enable <= 1;
stage_1_enable <= 1;
stage_2_enable <= 1;
end
if (s_input_socket_ack == 1'b1 && input_socket_stb == 1'b1) begin
result_2 <= input_socket;
write_enable_2 <= 1;
s_input_socket_ack <= 1'b0;
stage_0_enable <= 1;
stage_1_enable <= 1;
stage_2_enable <= 1;
end
if (timer == 0) begin
if (timer_enable) begin
stage_0_enable <= 1;
stage_1_enable <= 1;
stage_2_enable <= 1;
timer_enable <= 0;
end
end else begin
timer <= timer - 1;
end
if (rst == 1'b1) begin
stage_0_enable <= 1;
stage_1_enable <= 0;
stage_2_enable <= 0;
timer <= 0;
timer_enable <= 0;
program_counter <= 0;
s_input_eth_rx_ack <= 0;
s_input_socket_ack <= 0;
s_output_socket_stb <= 0;
s_output_eth_tx_stb <= 0;
end
end
assign input_eth_rx_ack = s_input_eth_rx_ack;
assign input_socket_ack = s_input_socket_ack;
assign output_socket_stb = s_output_socket_stb;
assign output_socket = s_output_socket;
assign output_eth_tx_stb = s_output_eth_tx_stb;
assign output_eth_tx = s_output_eth_tx;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: franp.com
// Engineer: Fran Pregernik <[email protected]>
//
// Create Date: 12/29/2016 08:04:28 PM
// Design Name:
// Module Name: radar_sim_target_axis
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module radar_sim_target_axis #
(
// Users to add parameters here
parameter integer DATA_WIDTH = 32,
// User parameters ends
// Do not modify the parameters beyond this line
// AXI4Stream sink: Data Width
parameter integer C_S_AXIS_TDATA_WIDTH = 3200
)
(
// Users to add ports here
// is the simulator enabled
(* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_HIGH" *)
(* MARK_DEBUG="true" *)
input wire EN,
// radar antenna angle change
(* MARK_DEBUG="true" *)
input wire RADAR_ARP_PE,
// radar antenna angle change
(* MARK_DEBUG="true" *)
input wire RADAR_ACP_PE,
input wire [DATA_WIDTH-1:0] ACP_CNT_MAX,
// is data stable
output wire DATA_VALID,
output reg [DATA_WIDTH-1:0] ACP_POS = 0,
output reg [C_S_AXIS_TDATA_WIDTH-1:0] BANK = 0,
(* MARK_DEBUG="true" *)
output wire DBG_READY,
(* MARK_DEBUG="true" *)
output wire DBG_VALID,
(* MARK_DEBUG="true" *)
output wire [DATA_WIDTH-1:0] DBG_ACP_CNT,
// User ports ends
// Do not modify the ports beyond this line
// AXI4Stream sink: Clock
input wire S_AXIS_ACLK,
// AXI4Stream sink: Reset
input wire S_AXIS_ARESETN,
// Ready to accept data in
output reg S_AXIS_TREADY = 0,
// Data in
input wire [C_S_AXIS_TDATA_WIDTH-1 : 0] S_AXIS_TDATA,
// Indicates boundary of last packet
input wire S_AXIS_TLAST,
// Data is in valid
input wire S_AXIS_TVALID
);
localparam POS_BIT_CNT = 16;
// SET on ARP, cleared on read of ACP data with idx 0
reg fast_fwd = 0;
// ACP since ARP
reg [DATA_WIDTH-1:0] acp_cnt = 0;
assign DATA_VALID = EN && (acp_cnt == ACP_POS);
assign DBG_READY = S_AXIS_TREADY;
assign DBG_VALID = S_AXIS_TVALID;
assign DBG_ACP_CNT = acp_cnt;
// keep track of ACP counts between ARPs
always @(posedge S_AXIS_ACLK) begin
if (RADAR_ARP_PE) begin
// edge case handling when both signals appear at the same time
// without this the count would be off by -1
if (RADAR_ACP_PE) begin
acp_cnt <= 1;
end else begin
acp_cnt <= 0;
end
end else if (RADAR_ACP_PE) begin
if (acp_cnt < ACP_CNT_MAX - 1) begin
acp_cnt <= acp_cnt + 1;
end
end
end
// data loading state machine
always @(posedge S_AXIS_ACLK) begin
if (!S_AXIS_ARESETN || !EN) begin
// Synchronous reset (active low)
BANK <= 0;
ACP_POS <= 0;
fast_fwd <= 0;
S_AXIS_TREADY <= 0;
end else if (EN) begin
if (RADAR_ARP_PE) begin
// set fast forwad flag
fast_fwd <= 1;
end
if (S_AXIS_TREADY && S_AXIS_TVALID) begin
// load new data from AXIS bus
BANK <= { S_AXIS_TDATA[C_S_AXIS_TDATA_WIDTH-1:POS_BIT_CNT], 16'b0 };
ACP_POS <= S_AXIS_TDATA[POS_BIT_CNT-1:0];
S_AXIS_TREADY <= 0;
// hold reset flag untill we read data for IDX 0
if (fast_fwd && S_AXIS_TDATA[POS_BIT_CNT-1:0] == 0) begin
fast_fwd <= 0;
end
end else begin
// ready to receive if the simulation is enabled and the next RADAR_ACP_PE happens
S_AXIS_TREADY <= (acp_cnt != ACP_POS);
end
end
end
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9122_channel (
// dac interface
dac_div_clk,
dac_rst,
dac_enable,
dac_data,
dac_frame,
dma_data,
// processor interface
dac_data_frame,
dac_data_sync,
dac_dds_format,
// bus interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
// parameters
parameter CHID = 32'h0;
parameter DP_DISABLE = 0;
// dac interface
input dac_div_clk;
input dac_rst;
output dac_enable;
output [63:0] dac_data;
output [ 3:0] dac_frame;
input [63:0] dma_data;
// processor interface
input dac_data_frame;
input dac_data_sync;
input dac_dds_format;
// bus interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
// internal registers
reg dac_enable = 'd0;
reg [63:0] dac_data = 'd0;
reg [ 3:0] dac_frame = 'd0;
reg [15:0] dac_dds_phase_0_0 = 'd0;
reg [15:0] dac_dds_phase_0_1 = 'd0;
reg [15:0] dac_dds_phase_1_0 = 'd0;
reg [15:0] dac_dds_phase_1_1 = 'd0;
reg [15:0] dac_dds_phase_2_0 = 'd0;
reg [15:0] dac_dds_phase_2_1 = 'd0;
reg [15:0] dac_dds_phase_3_0 = 'd0;
reg [15:0] dac_dds_phase_3_1 = 'd0;
reg [15:0] dac_dds_incr_0 = 'd0;
reg [15:0] dac_dds_incr_1 = 'd0;
reg [63:0] dac_dds_data = 'd0;
// internal signals
wire [15:0] dac_dds_data_0_s;
wire [15:0] dac_dds_data_1_s;
wire [15:0] dac_dds_data_2_s;
wire [15:0] dac_dds_data_3_s;
wire [15:0] dac_dds_scale_1_s;
wire [15:0] dac_dds_init_1_s;
wire [15:0] dac_dds_incr_1_s;
wire [15:0] dac_dds_scale_2_s;
wire [15:0] dac_dds_init_2_s;
wire [15:0] dac_dds_incr_2_s;
wire [15:0] dac_pat_data_1_s;
wire [15:0] dac_pat_data_2_s;
wire [ 3:0] dac_data_sel_s;
// dac data select
always @(posedge dac_div_clk) begin
dac_enable <= (dac_data_sel_s == 4'h2) ? 1'b1 : 1'b0;
case (dac_data_sel_s)
4'h2: dac_data <= dma_data;
4'h1: dac_data <= { dac_pat_data_2_s, dac_pat_data_1_s,
dac_pat_data_2_s, dac_pat_data_1_s};
default: dac_data <= dac_dds_data;
endcase
if (dac_data_sel_s == 4'h1) begin
dac_frame <= 4'b0101;
end else begin
dac_frame <= {3'd0, dac_data_frame};
end
end
// single channel dds
always @(posedge dac_div_clk) begin
if (dac_data_sync == 1'b1) begin
dac_dds_phase_0_0 <= dac_dds_init_1_s;
dac_dds_phase_0_1 <= dac_dds_init_2_s;
dac_dds_phase_1_0 <= dac_dds_phase_0_0 + dac_dds_incr_1_s;
dac_dds_phase_1_1 <= dac_dds_phase_0_1 + dac_dds_incr_2_s;
dac_dds_phase_2_0 <= dac_dds_phase_1_0 + dac_dds_incr_1_s;
dac_dds_phase_2_1 <= dac_dds_phase_1_1 + dac_dds_incr_2_s;
dac_dds_phase_3_0 <= dac_dds_phase_2_0 + dac_dds_incr_1_s;
dac_dds_phase_3_1 <= dac_dds_phase_2_1 + dac_dds_incr_2_s;
dac_dds_incr_0 <= {dac_dds_incr_1_s[13:0], 2'd0};
dac_dds_incr_1 <= {dac_dds_incr_2_s[13:0], 2'd0};
dac_dds_data <= 64'd0;
end else begin
dac_dds_phase_0_0 <= dac_dds_phase_0_0 + dac_dds_incr_0;
dac_dds_phase_0_1 <= dac_dds_phase_0_1 + dac_dds_incr_1;
dac_dds_phase_1_0 <= dac_dds_phase_1_0 + dac_dds_incr_0;
dac_dds_phase_1_1 <= dac_dds_phase_1_1 + dac_dds_incr_1;
dac_dds_phase_2_0 <= dac_dds_phase_2_0 + dac_dds_incr_0;
dac_dds_phase_2_1 <= dac_dds_phase_2_1 + dac_dds_incr_1;
dac_dds_phase_3_0 <= dac_dds_phase_3_0 + dac_dds_incr_0;
dac_dds_phase_3_1 <= dac_dds_phase_3_1 + dac_dds_incr_1;
dac_dds_incr_0 <= dac_dds_incr_0;
dac_dds_incr_1 <= dac_dds_incr_1;
dac_dds_data <= { dac_dds_data_3_s, dac_dds_data_2_s,
dac_dds_data_1_s, dac_dds_data_0_s};
end
end
generate
if (DP_DISABLE == 1) begin
assign dac_dds_data_0_s = 16'd0;
end else begin
ad_dds i_dds_0 (
.clk (dac_div_clk),
.dds_format (dac_dds_format),
.dds_phase_0 (dac_dds_phase_0_0),
.dds_scale_0 (dac_dds_scale_1_s),
.dds_phase_1 (dac_dds_phase_0_1),
.dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_0_s));
end
endgenerate
generate
if (DP_DISABLE == 1) begin
assign dac_dds_data_1_s = 16'd0;
end else begin
ad_dds i_dds_1 (
.clk (dac_div_clk),
.dds_format (dac_dds_format),
.dds_phase_0 (dac_dds_phase_1_0),
.dds_scale_0 (dac_dds_scale_1_s),
.dds_phase_1 (dac_dds_phase_1_1),
.dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_1_s));
end
endgenerate
generate
if (DP_DISABLE == 1) begin
assign dac_dds_data_2_s = 16'd0;
end else begin
ad_dds i_dds_2 (
.clk (dac_div_clk),
.dds_format (dac_dds_format),
.dds_phase_0 (dac_dds_phase_2_0),
.dds_scale_0 (dac_dds_scale_1_s),
.dds_phase_1 (dac_dds_phase_2_1),
.dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_2_s));
end
endgenerate
generate
if (DP_DISABLE == 1) begin
assign dac_dds_data_3_s = 16'd0;
end else begin
ad_dds i_dds_3 (
.clk (dac_div_clk),
.dds_format (dac_dds_format),
.dds_phase_0 (dac_dds_phase_3_0),
.dds_scale_0 (dac_dds_scale_1_s),
.dds_phase_1 (dac_dds_phase_3_1),
.dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_3_s));
end
endgenerate
// single channel processor
up_dac_channel #(.PCORE_DAC_CHID(CHID)) i_up_dac_channel (
.dac_clk (dac_div_clk),
.dac_rst (dac_rst),
.dac_dds_scale_1 (dac_dds_scale_1_s),
.dac_dds_init_1 (dac_dds_init_1_s),
.dac_dds_incr_1 (dac_dds_incr_1_s),
.dac_dds_scale_2 (dac_dds_scale_2_s),
.dac_dds_init_2 (dac_dds_init_2_s),
.dac_dds_incr_2 (dac_dds_incr_2_s),
.dac_pat_data_1 (dac_pat_data_1_s),
.dac_pat_data_2 (dac_pat_data_2_s),
.dac_data_sel (dac_data_sel_s),
.dac_iqcor_enb (),
.dac_iqcor_coeff_1 (),
.dac_iqcor_coeff_2 (),
.up_usr_datatype_be (),
.up_usr_datatype_signed (),
.up_usr_datatype_shift (),
.up_usr_datatype_total_bits (),
.up_usr_datatype_bits (),
.up_usr_interpolation_m (),
.up_usr_interpolation_n (),
.dac_usr_datatype_be (1'b0),
.dac_usr_datatype_signed (1'b1),
.dac_usr_datatype_shift (8'd0),
.dac_usr_datatype_total_bits (8'd16),
.dac_usr_datatype_bits (8'd16),
.dac_usr_interpolation_m (16'd1),
.dac_usr_interpolation_n (16'd1),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata),
.up_rack (up_rack));
endmodule
// ***************************************************************************
// ***************************************************************************
|
`include "bsg_defines.v"
//
// Converts a wormhole router stream into a higher level protocol without
// deserializing the data. This module can be used for converting various
// DMA formats to wormhole flits efficently and with minimal buffering.
// It can also be used to forward data between wormholes on different
// networks, or to convert between multiple protocol formats.
//
// Example use cases:
// - bsg_cache {dma_pkt, data/v/yumi} format <-> wormhole
// - SRAM read/write <-> bsg_wormhole_stream_in/out <-> Wormhole Network
// - Wide Network <-> bsg_wormhole_stream_in/out <-> Narrow Network
//
// Assumptions:
// Usage of this module requires correctly formed wormhole headers. The length
// field of the wormhole message determines how many protocol data beats are
// expected (some multiple or divisor of the flit_width). We expect most
// link and protocol data widths to be powers of 2 (32, 64, 512), so this
// length restriction is lenient.
//
// - data width is a multiple of flit width (would be easy to add support)
// - header width is a multiple of flit width (would be more challenging)
// - header width == wormhole header width + protocol header width
// - wormhole packets are laid out like the following:
// ---------------------------------------------------------------
// | data | data | data | data | protocol info | len cord |
// ---------------------------------------------------------------
// - header flits do not contain any data
//
// Header will arrive at or before data and either can be acked at any time.
// Typical users of this module will simply ack the header to learn the
// protocol information of the impending transaction, begin the transaction,
// and then forward or accept all of the data serially.
//
module bsg_wormhole_stream_out
#(// The wormhole router protocol information
// flit_width_p: number of physical data wires between links
// cord_width_p: the width of the {y,x} coordinate of the destination
// len_width_p : the width of the length field, denoting #flits+1
// cid_width : the width of the concentrator id of the destination
// Default to 0 for cord and cid, so that this module can be used either
// for concentrator or router
parameter `BSG_INV_PARAM(flit_width_p)
, parameter cord_width_p = 0
, parameter `BSG_INV_PARAM(len_width_p)
, parameter cid_width_p = 0
// Higher level protocol information
, parameter `BSG_INV_PARAM(pr_hdr_width_p)
, parameter `BSG_INV_PARAM(pr_data_width_p)
, parameter `BSG_INV_PARAM(pr_len_width_p)
// Size of the wormhole header + the protocol header. The data starts afterwards.
// Users may set this directly rather than relying on the protocol header derived default
, parameter hdr_width_p = cord_width_p + len_width_p + cid_width_p + pr_hdr_width_p
)
(input clk_i
, input reset_i
// The output of a wormhole network
, input [flit_width_p-1:0] link_data_i
, input link_v_i
, output link_ready_and_o
// The wormhole and protocol header information
, output [hdr_width_p-1:0] hdr_o
, output hdr_v_o
, input hdr_ready_and_i
// number of protocol message data in arriving wormhole message
// arrives late when hdr_v_o & hdr_ready_and_i
// value is len-1 (i.e., zero based)
, input [pr_len_width_p-1:0] pr_data_beats_i
// The protocol data information
, output [pr_data_width_p-1:0] data_o
, output data_v_o
, input data_ready_and_i
);
wire is_hdr, is_data;
localparam [len_width_p-1:0] hdr_len_lp = `BSG_CDIV(hdr_width_p, flit_width_p);
logic hdr_v_li, hdr_ready_lo;
// Aggregate flits until we have a full header-worth of data, then let the
// client process it
assign hdr_v_li = is_hdr & link_v_i;
bsg_serial_in_parallel_out_passthrough
#(.width_p(flit_width_p)
,.els_p(hdr_len_lp)
)
hdr_sipo
(.clk_i(clk_i)
,.reset_i(reset_i)
,.data_i(link_data_i)
,.v_i(hdr_v_li)
,.ready_and_o(hdr_ready_lo)
,.data_o(hdr_o)
,.v_o(hdr_v_o)
,.ready_and_i(hdr_ready_and_i)
);
logic data_v_li, data_ready_lo;
assign data_v_li = is_data & link_v_i;
// Protocol data is less than a single flit-sized. We accept a large
// wormhole flit, then let the client process it piecemeal
if (flit_width_p > pr_data_width_p)
begin : narrow
// flit_width_p > pr_data_width_p -> multiple protocol data per link flit
// and it is possible that last link flit is not completely filled with valid
// protocol data.
// number of protocol data per full link flit
localparam [len_width_p-1:0] max_els_lp = `BSG_CDIV(flit_width_p, pr_data_width_p);
localparam lg_max_els_lp = `BSG_SAFE_CLOG2(max_els_lp);
// PISO len_i is zero-based, i.e., input is len-1
localparam [lg_max_els_lp-1:0] piso_full_len_lp = max_els_lp - 1;
// PISO inputs
logic piso_first_lo;
logic [lg_max_els_lp-1:0] piso_len_li;
// count of protocol data packets to consume after current
// set late when hdr_v_o & hdr_ready_i
// set value is provided by consumer, derived from output header
logic [pr_len_width_p-1:0] pr_data_cnt;
wire pr_data_consumed = (pr_data_cnt == '0);
bsg_counter_set_down
#(.width_p(pr_len_width_p)
,.init_val_p('0)
,.set_and_down_exclusive_p(0)
)
pr_data_counter
(.clk_i(clk_i)
,.reset_i(reset_i)
,.set_i(hdr_v_o & hdr_ready_and_i)
,.val_i(pr_data_beats_i)
,.down_i(data_v_o & data_ready_and_i & ~pr_data_consumed)
,.count_r_o(pr_data_cnt)
);
// for each PISO transaction, provide number of protocol data to expect
assign piso_len_li = (pr_data_cnt >= piso_full_len_lp)
? piso_full_len_lp
: lg_max_els_lp'(pr_data_cnt);
bsg_parallel_in_serial_out_passthrough_dynamic
#(.width_p(pr_data_width_p)
,.max_els_p(max_els_lp)
)
data_piso
(.clk_i(clk_i)
,.reset_i(reset_i)
,.data_i(link_data_i)
,.v_i(data_v_li)
,.ready_and_o(data_ready_lo)
,.data_o(data_o)
,.v_o(data_v_o)
,.ready_and_i(data_ready_and_i)
,.first_o(piso_first_lo)
// must be presented when ready_and_i & first_o
,.len_i(piso_len_li)
);
end
else
// Protocol data is 1 or multiple flit-sized. We aggregate wormhole data
// until we have a full protocol data and then let the client process it
begin : wide
localparam [len_width_p-1:0] data_len_lp = `BSG_CDIV(pr_data_width_p, flit_width_p);
bsg_serial_in_parallel_out_passthrough
#(.width_p(flit_width_p)
,.els_p(data_len_lp)
)
data_sipo
(.clk_i(clk_i)
,.reset_i(reset_i)
,.data_i(link_data_i)
,.v_i(data_v_li)
,.ready_and_o(data_ready_lo)
,.data_o(data_o)
,.v_o(data_v_o)
,.ready_and_i(data_ready_and_i)
);
end
// Identifies which flits are header vs data flits
bsg_wormhole_stream_control
#(.len_width_p(len_width_p)
,.hdr_len_p(hdr_len_lp)
)
stream_control
(.clk_i(clk_i)
,.reset_i(reset_i)
,.len_i(link_data_i[cord_width_p+:len_width_p])
,.link_accept_i(link_ready_and_o & link_v_i)
,.is_hdr_o(is_hdr)
,.is_data_o(is_data)
);
assign link_ready_and_o = is_hdr ? hdr_ready_lo : data_ready_lo;
//synopsys translate_off
if (hdr_width_p % flit_width_p != 0)
$fatal("Header width: %d must be multiple of flit width: %d", hdr_width_p, flit_width_p);
if ((pr_data_width_p % flit_width_p != 0) && (flit_width_p % pr_data_width_p != 0))
$fatal("Protocol data width: %d must be multiple of flit width: %d", pr_data_width_p, flit_width_p);
//synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_wormhole_stream_out)
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:31:09 02/22/2015
// Design Name:
// Module Name: PackAdder
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module PackAdderProcess(
input [31:0] z_postNormaliseSum,
input [3:0] Opcode_NormaliseSum,
input idle_NormaliseSum,
input [31:0] sout_NormaliseSum,
input [27:0] sum_NormaliseSum,
input [7:0] InsTagNormaliseAdder,
input clock,
output reg [31:0] sout_PackSum,
output reg Done = 1'b0,
output reg [31:0] z_postPack,
output reg [3:0] Opcode_Pack,
output reg [7:0] InsTagPack
);
parameter no_idle = 1'b0,
put_idle = 1'b1;
wire s_sign;
wire [7:0] s_exponent;
assign s_sign = sout_NormaliseSum[31];
assign s_exponent = sout_NormaliseSum[30:23];
parameter sin_cos = 4'd0,
sinh_cosh = 4'd1,
arctan = 4'd2,
arctanh = 4'd3,
exp = 4'd4,
sqr_root = 4'd5, // Pre processed input is given 4'd11
// This requires pre processing. x = (a+1)/2 and y = (a-1)/2
division = 4'd6,
tan = 4'd7, // This is iterative. sin_cos followed by division.
tanh = 4'd8, // This is iterative. sinh_cosh followed by division.
nat_log = 4'd9, // This requires pre processing. x = (a+1) and y = (a-1)
hypotenuse = 4'd10,
PreProcess = 4'd11;
always @ (posedge clock)
begin
InsTagPack <= InsTagNormaliseAdder;
Opcode_Pack <= Opcode_NormaliseSum;
z_postPack <= z_postNormaliseSum;
//if (Opcode_NormaliseSum == PreProcess) begin
Done <= 1'b0;
if (idle_NormaliseSum != put_idle) begin
sout_PackSum[22:0] <= sum_NormaliseSum[25:3];
sout_PackSum[30:23] <= s_exponent + 127;
sout_PackSum[31] <= s_sign;
if ($signed(s_exponent) == -126 && sum_NormaliseSum[22] == 0) begin
sout_PackSum[30 : 23] <= 0;
end
if ($signed(s_exponent) <= -126) begin
sout_PackSum[30 : 23] <= 0;
sout_PackSum[22:0] <= 0;
end
//if overflow occurs, return inf
if ($signed(s_exponent) > 127) begin
sout_PackSum[22 : 0] <= 0;
sout_PackSum[30 : 23] <= 255;
sout_PackSum[31] <= s_sign;
end
end
else begin
sout_PackSum <= sout_NormaliseSum;
end
//end
if (Opcode_NormaliseSum == sqr_root || Opcode_NormaliseSum == nat_log) begin
Done <= 1'b1;
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 01/04/2017 01:13:05 AM
// Design Name:
// Module Name: tb_router_top
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`include "global.vh"
module tb_router_top;
reg clk, reset;
reg [`DATA_WIDTH-1:0] data_in_0, data_in_1, data_in_2, data_in_3, data_in_4;
wire [`DATA_WIDTH-1:0] data_out_0, data_out_1, data_out_2, data_out_3, data_out_4;
router carpool(
clk,
n_rst,
data_in_0,
data_in_1,
data_in_2,
data_in_3,
data_in_4,
data_out_0,
data_out_1,
data_out_2,
data_out_3,
data_out_4
);
initial begin
clk = 1'b0; reset = 1'b1;
#10;
reset = 1'b0;
#10;
reset = 1'b1;
`ifdef BLESS
data_in_0 = {8'h0,3'd3,3'd7,6'b0,3'd1,3'd0,3'd3,3'd3,128'hDEAD_BEEF_0000_0001};
data_in_1 = {8'h1,3'd7,3'd7,6'b0,3'd1,3'd0,3'd0,3'd0,128'hDEAD_BEEF_0000_0003};
data_in_2 = {8'h2,3'd0,3'd0,6'b0,3'd1,3'd0,3'd3,3'd4,128'hDEAD_BEEF_0000_0007};
data_in_3 = {8'h3,3'd1,3'd0,6'b0,3'd1,3'd0,3'd3,3'd4,128'hDEAD_BEEF_0000_000F};
data_in_4 = {8'h4,3'd0,3'd0,6'b0,3'd1,3'd0,3'd3,3'd4,128'hDEAD_BEEF_0000_0011};
`endif
`ifdef CARPOOL
data_in_0 = {8'h0,1'b0,1'b0,3'd3,3'd7,6'b0,4'd1,4'd0,3'd3,3'd3,128'hFFFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF};
data_in_1 = {8'h1,1'b0,1'b1,3'd7,3'd7,6'b0,4'd1,4'd0,3'd0,3'd0,64'h800000E3,64'hDEAD_BEEF_0000_0001};
data_in_2 = {8'h2,1'b1,1'b0,3'd0,3'd0,6'b0,4'd1,4'd0,3'd3,3'd4,64'h8,64'hDEAD_BEEF_0000_0003};
data_in_3 = {8'h3,1'b0,1'b0,3'd1,3'd0,6'b0,4'd1,4'd0,3'd3,3'd4,128'hFFFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF_0001};
data_in_4 = {8'h4,1'b1,1'b0,3'd0,3'd0,6'b0,4'd1,4'd0,3'd3,3'd4,64'h8000000,64'hDEAD_BEEF_0000_0007};
`endif //CARPOOL
end
always @ *
#5 clk <= ~clk;
endmodule
|
`timescale 1ns/1ns
// SEQUENCER: Top level TX module.
// Copyright 2010 University of Washington
// License: http://creativecommons.org/licenses/by/3.0/
// 2008 Dan Yeager
// Connects the TX module to its appropriate clock sources
// 0. !reset
// 1. Preamble is clocked until it's done flag is raised.
// 2. Data is clocked until it's done flag is raised.
// 3. If "docrc" input, CRC module is clocked until it's done flag is raised.
// 4. Dummy "1" bit is clocked out and !txenable signal is sent to TX module.
module sequencer (reset, rtcal_expired, oscclk, m, dr, docrc, trext, trcal,
databitsrc, datadone, dataclk, modout, txsetupdone, txdone);
input reset, rtcal_expired, trext, dr, docrc, databitsrc, datadone, oscclk;
input [9:0] trcal;
input [1:0] m;
output dataclk, modout, txsetupdone, txdone;
reg done;
reg tx_stop;
wire txsetupdone, txdone;
// module connections
wire txclk, txbitclk;
wire violation;
wire crcdone, preambledone; // datadone is an input
wire crcinclk, crcbitin;
wire txbitsrc, crcbitsrc, preamblebitsrc; // databitsrc is an input
wire crcoutclk, preambleclk, dataclk;
// MODULES! :)
txclkdivide U_DIV (reset, oscclk, trcal, dr, txclk);
tx U_TX0 (reset, rtcal_expired, tx_stop,
txclk, txbitsrc, violation, m,
modout, txbitclk, txsetupdone, txdone);
preamble U_PRE (reset, preambleclk, m, trext, preamblebitsrc, violation, preambledone);
crc16 U_CRC (reset, crcinclk, crcbitin, crcoutclk, crcbitsrc, crcdone);
// state machine variables
reg [1:0] state;
parameter STATE_PRE = 2'd0;
parameter STATE_DATA = 2'd1;
parameter STATE_CRC = 2'd2;
parameter STATE_END = 2'd3;
// mux the bit source for the tx module
wire [3:0] bitsrc;
assign bitsrc[0] = preamblebitsrc;
assign bitsrc[1] = databitsrc;
assign bitsrc[2] = crcbitsrc;
assign bitsrc[3] = 1;
assign txbitsrc = bitsrc[state];
reg bit_transition;
// crc gets the data bits too
assign crcbitin = databitsrc;
assign crcinclk = txbitclk & (state == STATE_DATA) & docrc;
// send the tx module bit clock to the appropriate module
// Note: Preamble and Data clocks overlap at handoffs
// because these modules need 1 clock for setup.
assign preambleclk = txbitclk && (state == STATE_PRE) && (!done);
assign dataclk = txbitclk && (state == STATE_DATA ||(state == STATE_PRE && bit_transition && !done));
assign crcoutclk = txbitclk && (state == STATE_CRC); // crc doesn't need extra pre data clk edge.
always @ (negedge txbitclk or posedge reset) begin
if (reset) begin
state <= 0;
done <= 0;
bit_transition <= 0;
tx_stop <= 0;
end else if (done) begin
// don't do anything after we are done
// wait for controller to reset us.
end else if (state == STATE_PRE) begin
if (bit_transition) begin
state <= STATE_DATA;
bit_transition <= 0;
end else if (preambledone) begin
bit_transition <= 1;
end
end else if (state == STATE_DATA) begin
if (bit_transition) begin
if (datadone && docrc) state <= STATE_CRC;
else if (datadone) state <= STATE_END;
bit_transition <= 0;
end else if (datadone) begin
bit_transition <= 1;
end
end else if (state == STATE_CRC) begin
if (bit_transition) begin
state <= STATE_END;
bit_transition <= 0;
end else if (crcdone) begin
bit_transition <= 1;
end
end else if (state == STATE_END) begin
if (txdone) begin
state <= STATE_PRE;
done <= 1;
end else begin
tx_stop <= 1;
end
end // no else required because states are exhaustive
end
endmodule
|
// Copyright 2012 Sriram Radhakrishnan, Varun Sampath, Shilpa Sarode
//
// This file is part of PVS.
//
// PVS is free software: you can redistribute it and/or modify it under the
// terms of the GNU General Public License as published by the Free Software
// Foundation, either version 3 of the License, or (at your option) any later
// version.
//
// PVS is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// PVS. If not, see <http://www.gnu.org/licenses/>.
`timescale 1 ns / 1 ns
// Widens the output signal using COUNT
// inputs:
// CLK
// output:
// parameter:
// HIGH_PERIOD
module light_up
(
clk,
header,
counter,
tachy_pin,
brady_pin,
normal_pin
);
//////////// INPUTS & OUTPUTS ////////////
input clk;
input[7:0] header;
input[31:0] counter;
output tachy_pin;
output brady_pin;
output normal_pin;
//////////// PARAMETERS ////////////
parameter FAST_BEAT = 32'd750; // with clk of 1.5kHz corresponds to 120 beats per minute
parameter SLOW_BEAT = 32'd1800; // with clk of 1.5kHz corresponds to 50 beats per minute
parameter CORRECT_HEAD1 = 8'd4; // RV & !vp
parameter CORRECT_HEAD2 = 8'd6; // RV & vp
//////////// SIGNALS & REGS ////////////
reg brady_flash;
reg tachy_flash;
reg[31:0] counter_previous;
wire[31:0] difference;
wire correct_header;
wire too_fast;
wire too_slow;
//////////// LOGIC ////////////
assign correct_header = (header == CORRECT_HEAD1 || header == CORRECT_HEAD2);
assign difference = counter - counter_previous;
assign too_fast = difference <= FAST_BEAT;
assign too_slow = difference >= SLOW_BEAT;
always @(posedge clk) begin
if (correct_header) begin
tachy_flash <= too_fast;
brady_flash <= too_slow;
counter_previous <= counter;
end
end
led_flasher tachy_flasher
(
.clk(clk),
.LED_flash(tachy_flash),
.LED_out(tachy_pin)
);
led_flasher brady_flasher
(
.clk(clk),
.LED_flash(brady_flash),
.LED_out(brady_pin)
);
//////////// OUTPUT ASSIGNS ////////////
assign normal_pin = !tachy_flash && !brady_flash;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2004 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [2:0] index_a;
reg [2:0] index_b;
prover #(4) p4 (/*AUTOINST*/
// Inputs
.clk (clk),
.index_a (index_a),
.index_b (index_b));
prover #(32) p32 (/*AUTOINST*/
// Inputs
.clk (clk),
.index_a (index_a),
.index_b (index_b));
prover #(63) p63 (/*AUTOINST*/
// Inputs
.clk (clk),
.index_a (index_a),
.index_b (index_b));
prover #(64) p64 (/*AUTOINST*/
// Inputs
.clk (clk),
.index_a (index_a),
.index_b (index_b));
prover #(72) p72 (/*AUTOINST*/
// Inputs
.clk (clk),
.index_a (index_a),
.index_b (index_b));
prover #(126) p126 (/*AUTOINST*/
// Inputs
.clk (clk),
.index_a (index_a),
.index_b (index_b));
prover #(128) p128 (/*AUTOINST*/
// Inputs
.clk (clk),
.index_a (index_a),
.index_b (index_b));
integer cyc; initial cyc=0;
initial index_a = 3'b0;
initial index_b = 3'b0;
always @* begin
index_a = cyc[2:0]; if (index_a>3'd4) index_a=3'd4;
index_b = cyc[5:3]; if (index_b>3'd4) index_b=3'd4;
end
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module prover (
input clk,
input [2:0] index_a,
input [2:0] index_b
);
parameter WIDTH = 4;
reg signed [WIDTH-1:0] as;
reg signed [WIDTH-1:0] bs;
wire [WIDTH-1:0] b = bs;
always @* begin
casez (index_a)
3'd0: as = {(WIDTH){1'd0}}; // 0
3'd1: as = {{(WIDTH-1){1'd0}}, 1'b1}; // 1
3'd2: as = {1'b0, {(WIDTH-1){1'd0}}}; // 127 or equiv
3'd3: as = {(WIDTH){1'd1}}; // -1
3'd4: as = {1'b1, {(WIDTH-1){1'd0}}}; // -128 or equiv
default: $stop;
endcase
casez (index_b)
3'd0: bs = {(WIDTH){1'd0}}; // 0
3'd1: bs = {{(WIDTH-1){1'd0}}, 1'b1}; // 1
3'd2: bs = {1'b0, {(WIDTH-1){1'd0}}}; // 127 or equiv
3'd3: bs = {(WIDTH){1'd1}}; // -1
3'd4: bs = {1'b1, {(WIDTH-1){1'd0}}}; // -128 or equiv
default: $stop;
endcase
end
reg [7:0] results[4:0][4:0];
wire gt = as>b;
wire gts = as>bs;
wire gte = as>=b;
wire gtes = as>=bs;
wire lt = as<b;
wire lts = as<bs;
wire lte = as<=b;
wire ltes = as<=bs;
reg [7:0] exp;
reg [7:0] got;
integer cyc=0;
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc>2) begin
`ifdef TEST_VERBOSE
$write("results[%d][%d] = 8'b%b_%b_%b_%b_%b_%b_%b_%b;\n",
index_a, index_b,
gt, gts, gte, gtes, lt, lts, lte, ltes);
`endif
exp = results[index_a][index_b];
got = {gt, gts, gte, gtes, lt, lts, lte, ltes};
if (exp !== got) begin
$display("%%Error: bad comparison width=%0d: %d/%d got=%b exp=%b", WIDTH, index_a,index_b,got, exp);
$stop;
end
end
end
// Result table
initial begin
// Indexes: 0, 1, -1, 127, -128
// Gt Gts Gte Gtes Lt Lts Lte Ltes
results[0][0] = 8'b0_0_1_1_0_0_1_1;
results[0][1] = 8'b0_0_0_0_1_1_1_1;
results[0][2] = 8'b0_0_1_1_0_0_1_1;
results[0][3] = 8'b0_1_0_1_1_0_1_0;
results[0][4] = 8'b0_1_0_1_1_0_1_0;
results[1][0] = 8'b1_1_1_1_0_0_0_0;
results[1][1] = 8'b0_0_1_1_0_0_1_1;
results[1][2] = 8'b1_1_1_1_0_0_0_0;
results[1][3] = 8'b0_1_0_1_1_0_1_0;
results[1][4] = 8'b0_1_0_1_1_0_1_0;
results[2][0] = 8'b0_0_1_1_0_0_1_1;
results[2][1] = 8'b0_0_0_0_1_1_1_1;
results[2][2] = 8'b0_0_1_1_0_0_1_1;
results[2][3] = 8'b0_1_0_1_1_0_1_0;
results[2][4] = 8'b0_1_0_1_1_0_1_0;
results[3][0] = 8'b1_0_1_0_0_1_0_1;
results[3][1] = 8'b1_0_1_0_0_1_0_1;
results[3][2] = 8'b1_0_1_0_0_1_0_1;
results[3][3] = 8'b0_0_1_1_0_0_1_1;
results[3][4] = 8'b1_1_1_1_0_0_0_0;
results[4][0] = 8'b1_0_1_0_0_1_0_1;
results[4][1] = 8'b1_0_1_0_0_1_0_1;
results[4][2] = 8'b1_0_1_0_0_1_0_1;
results[4][3] = 8'b0_0_0_0_1_1_1_1;
results[4][4] = 8'b0_0_1_1_0_0_1_1;
end
endmodule
|
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_b2s_ar_channel #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of ID signals.
// Range: >= 1.
parameter integer C_ID_WIDTH = 4,
// Width of AxADDR
// Range: 32.
parameter integer C_AXI_ADDR_WIDTH = 32
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// AXI Slave Interface
// Slave Interface System Signals
input wire clk ,
input wire reset ,
// Slave Interface Read Address Ports
input wire [C_ID_WIDTH-1:0] s_arid ,
input wire [C_AXI_ADDR_WIDTH-1:0] s_araddr ,
input wire [7:0] s_arlen ,
input wire [2:0] s_arsize ,
input wire [1:0] s_arburst ,
input wire s_arvalid ,
output wire s_arready ,
output wire m_arvalid ,
output wire [C_AXI_ADDR_WIDTH-1:0] m_araddr ,
input wire m_arready ,
// Connections to/from axi_protocol_converter_v2_1_b2s_r_channel module
output wire [C_ID_WIDTH-1:0] r_arid ,
output wire r_push ,
output wire r_rlast ,
input wire r_full
);
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
wire next ;
wire next_pending ;
wire a_push;
wire incr_burst;
reg [C_ID_WIDTH-1:0] s_arid_r;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// Translate the AXI transaction to the MC transaction(s)
axi_protocol_converter_v2_1_b2s_cmd_translator #
(
.C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH )
)
cmd_translator_0
(
.clk ( clk ) ,
.reset ( reset ) ,
.s_axaddr ( s_araddr ) ,
.s_axlen ( s_arlen ) ,
.s_axsize ( s_arsize ) ,
.s_axburst ( s_arburst ) ,
.s_axhandshake ( s_arvalid & a_push ) ,
.incr_burst ( incr_burst ) ,
.m_axaddr ( m_araddr ) ,
.next ( next ) ,
.next_pending ( next_pending )
);
axi_protocol_converter_v2_1_b2s_rd_cmd_fsm ar_cmd_fsm_0
(
.clk ( clk ) ,
.reset ( reset ) ,
.s_arready ( s_arready ) ,
.s_arvalid ( s_arvalid ) ,
.s_arlen ( s_arlen ) ,
.m_arvalid ( m_arvalid ) ,
.m_arready ( m_arready ) ,
.next ( next ) ,
.next_pending ( next_pending ) ,
.data_ready ( ~r_full ) ,
.a_push ( a_push ) ,
.r_push ( r_push )
);
// these signals can be moved out of this block to the top level.
assign r_arid = s_arid_r;
assign r_rlast = ~next_pending;
always @(posedge clk) begin
s_arid_r <= s_arid ;
end
endmodule
`default_nettype wire
|
// --------------------------------------------------------------------------------
//| Avalon Streaming Channel Adapter
// --------------------------------------------------------------------------------
`timescale 1ns / 100ps
module ik_swift_master_0_p2b_adapter (
// Interface: clk
input clk,
// Interface: reset
input reset_n,
// Interface: in
output reg in_ready,
input in_valid,
input [ 7: 0] in_data,
input in_startofpacket,
input in_endofpacket,
// Interface: out
input out_ready,
output reg out_valid,
output reg [ 7: 0] out_data,
output reg out_startofpacket,
output reg out_endofpacket,
output reg [ 7: 0] out_channel
);
reg in_channel = 0;
// ---------------------------------------------------------------------
//| Payload Mapping
// ---------------------------------------------------------------------
always @* begin
in_ready = out_ready;
out_valid = in_valid;
out_data = in_data;
out_startofpacket = in_startofpacket;
out_endofpacket = in_endofpacket;
out_channel = 0;
out_channel = in_channel;
end
endmodule
|
`include "sata_defines.v"
module sata_platform (
input rst,
input tx_comm_reset,
input tx_comm_wake,
output comm_init_detect,
output comm_wake_detect,
output rx_elec_idle,
input tx_elec_idle,
output rx_byte_is_aligned,
input [31:0] phy_tx_dout,
input phy_tx_isk,
output [31:0] phy_rx_din,
output [3:0] phy_rx_isk,
//Clock Interface
input mgtclk_in,
output reg cnt_rst,
output pll_locked,
output clk_75mhz,
output platform_ready,
output TXP0_OUT,
output TXN0_OUT,
input RXP0_IN,
input RXN0_IN,
output GTX115_TXP0_OUT,
output GTX115_TXN0_OUT,
input GTX115_RXP0_IN,
input GTX115_RXN0_IN
);
//Parameters
//Registers/Wires
//Submodules
//Asynchronous Logic
//Synchronous Logic
endmodule
|
module demo_sound1(
input clock,
output [7:0]key_code,
input k_tr
);
reg [15:0]tmp;
wire[15:0]tmpa;
reg tr;
reg [15:0]step;
wire[15:0]step_r;
reg [15:0]TT;
reg[5:0]st;
reg go_end;
////////Music-processing////////
always @(negedge k_tr or posedge clock) begin
if (!k_tr) begin
step=0;
st=0;
tr=0;
end
else
if (step<step_r) begin
case (st)
0: st=st+1;
1: begin tr=0; st=st+1;end
2: begin tr=1;st=st+1;end
3: if(go_end) st=st+1;
4: begin st=0;step=step+1;end
endcase
end
end
/////////////// pitch //////////////////
wire [7:0]key_code1=(
(TT[3:0]==1)?8'h2b:(//1
(TT[3:0]==2)?8'h34:(//2
(TT[3:0]==3)?8'h33:(//3
(TT[3:0]==4)?8'h3b:(//4
(TT[3:0]==5)?8'h42:(//5
(TT[3:0]==6)?8'h4b:(//6
(TT[3:0]==7)?8'h4c:(//7
(TT[3:0]==10)?8'h52:(//1
(TT[3:0]==15)?8'hf0:8'hf0
))))))))
);
/////////////// paddle ///////////////////
assign tmpa[15:0]=(
(TT[7:4]==15)?16'h10:(
(TT[7:4]==8)? 16'h20:(
(TT[7:4]==9)? 16'h30:(
(TT[7:4]==1)? 16'h40:(
(TT[7:4]==3)? 16'h60:(
(TT[7:4]==2)? 16'h80:(
(TT[7:4]==4)? 16'h100:0
))))))
);
/////////// note list ///////////
always @(step) begin
case (step)
0:TT=8'hfa;
1:TT=8'h1f;//end
endcase
end
assign step_r=1;///Total note
/////////////KEY release & code-out ////////////////
always @(negedge tr or posedge clock)begin
if(!tr) begin tmp=0;go_end=0 ;end
else if (tmp>tmpa)go_end=1;
else tmp=tmp+1;
end
assign key_code=(tmp<(tmpa-1))?key_code1:8'hf0;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11:39:13 09/04/2015
// Design Name:
// Module Name: First_Phase_M
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module First_Phase_M
//SINGLE PRECISION PARAMETERS
# (parameter W = 32)
//DOUBLE PRECISION PARAMETERS
/*# (parameter W = 64) */
(
input wire clk, //system clock
input wire rst, //module reset
input wire load, //load signal
input wire [W-1:0] Data_MX, //Data X and Y are the operands
input wire [W-1:0] Data_MY,
output wire [W-1:0] Op_MX, //Both Op signals are the outputs
output wire [W-1:0] Op_MY
);
//Module's Body
//Both registers could be set with the parameter signal
//to be 32 or 64 bitwidth
RegisterMult #(.W(W)) XMRegister ( //Data X input register
.clk(clk),
.rst(rst),
.load(load),
.D(Data_MX),
.Q(Op_MX)
);
RegisterMult #(.W(W)) YMRegister ( //Data Y input register
.clk(clk),
.rst(rst),
.load(load),
.D(Data_MY),
.Q(Op_MY)
);
endmodule
|
/*
* gpio.v
*
* Created on: 27.12.2017
* Author: Alexander Antonov <[email protected]>
* License: See LICENSE file for details
*/
module gpio
(
input [0:0] clk_i
, input [0:0] rst_i
, input [0:0] bus_req
, input [0:0] bus_we
, input [31:0] bus_addr
, input [3:0] bus_be
, input [31:0] bus_wdata
, output [0:0] bus_ack
, output reg [0:0] bus_resp
, output reg [31:0] bus_rdata
, input [15:0] gpio_bi
, output [15:0] gpio_bo
);
reg [3:0] led_register [3:0];
assign gpio_bo = {led_register[3], led_register[2], led_register[1], led_register[0]};
always @(posedge clk_i)
begin
if (rst_i) bus_resp <= 1'b0;
else bus_resp <= bus_req & !bus_we;
end
always @(posedge clk_i)
begin
if (rst_i) bus_rdata <= 32'h0;
else
begin
if (bus_addr[7:0] < 8'h10) bus_rdata <= led_register[bus_addr[3:2]];
else bus_rdata <= gpio_bi;
end
end
always @(posedge clk_i)
begin
if (rst_i) begin led_register[0] <= 8'h0; led_register[1] <= 8'h0; led_register[2] <= 8'h0; led_register[3] <= 8'h0; end
if (bus_req && bus_we && (bus_addr[7:0] < 8'h10)) led_register[bus_addr[3:2]] <= bus_wdata;
end
assign bus_ack = bus_req;
endmodule
|
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