text
stringlengths 992
1.04M
|
|---|
//Legal Notice: (C)2020 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
//Register map:
//addr register type
//0 read data r
//1 write data w
//2 status r/w
//3 control r/w
//4 reserved
//5 slave-enable r/w
//6 end-of-packet-value r/w
//INPUT_CLOCK: 116000000
//ISMASTER: 1
//DATABITS: 8
//TARGETCLOCK: 20000000
//NUMSLAVES: 1
//CPOL: 0
//CPHA: 0
//LSBFIRST: 0
//EXTRADELAY: 0
//TARGETSSDELAY: 0
module wasca_spi_sd_card (
// inputs:
MISO,
clk,
data_from_cpu,
mem_addr,
read_n,
reset_n,
spi_select,
write_n,
// outputs:
MOSI,
SCLK,
SS_n,
data_to_cpu,
dataavailable,
endofpacket,
irq,
readyfordata
)
;
output MOSI;
output SCLK;
output SS_n;
output [ 15: 0] data_to_cpu;
output dataavailable;
output endofpacket;
output irq;
output readyfordata;
input MISO;
input clk;
input [ 15: 0] data_from_cpu;
input [ 2: 0] mem_addr;
input read_n;
input reset_n;
input spi_select;
input write_n;
wire E;
reg EOP;
reg MISO_reg;
wire MOSI;
reg ROE;
reg RRDY;
wire SCLK;
reg SCLK_reg;
reg SSO_reg;
wire SS_n;
wire TMT;
reg TOE;
wire TRDY;
wire control_wr_strobe;
reg data_rd_strobe;
reg [ 15: 0] data_to_cpu;
reg data_wr_strobe;
wire dataavailable;
wire ds_MISO;
wire enableSS;
wire endofpacket;
reg [ 15: 0] endofpacketvalue_reg;
wire endofpacketvalue_wr_strobe;
reg iEOP_reg;
reg iE_reg;
reg iROE_reg;
reg iRRDY_reg;
reg iTMT_reg;
reg iTOE_reg;
reg iTRDY_reg;
wire irq;
reg irq_reg;
wire p1_data_rd_strobe;
wire [ 15: 0] p1_data_to_cpu;
wire p1_data_wr_strobe;
wire p1_rd_strobe;
wire [ 1: 0] p1_slowcount;
wire p1_wr_strobe;
reg rd_strobe;
wire readyfordata;
reg [ 7: 0] rx_holding_reg;
reg [ 7: 0] shift_reg;
wire slaveselect_wr_strobe;
wire slowclock;
reg [ 1: 0] slowcount;
wire [ 10: 0] spi_control;
reg [ 15: 0] spi_slave_select_holding_reg;
reg [ 15: 0] spi_slave_select_reg;
wire [ 10: 0] spi_status;
reg [ 4: 0] state;
reg stateZero;
wire status_wr_strobe;
reg transmitting;
reg tx_holding_primed;
reg [ 7: 0] tx_holding_reg;
reg wr_strobe;
wire write_shift_reg;
wire write_tx_holding;
//spi_control_port, which is an e_avalon_slave
assign p1_rd_strobe = ~rd_strobe & spi_select & ~read_n;
// Read is a two-cycle event.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
rd_strobe <= 0;
else
rd_strobe <= p1_rd_strobe;
end
assign p1_data_rd_strobe = p1_rd_strobe & (mem_addr == 0);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_rd_strobe <= 0;
else
data_rd_strobe <= p1_data_rd_strobe;
end
assign p1_wr_strobe = ~wr_strobe & spi_select & ~write_n;
// Write is a two-cycle event.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
wr_strobe <= 0;
else
wr_strobe <= p1_wr_strobe;
end
assign p1_data_wr_strobe = p1_wr_strobe & (mem_addr == 1);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_wr_strobe <= 0;
else
data_wr_strobe <= p1_data_wr_strobe;
end
assign control_wr_strobe = wr_strobe & (mem_addr == 3);
assign status_wr_strobe = wr_strobe & (mem_addr == 2);
assign slaveselect_wr_strobe = wr_strobe & (mem_addr == 5);
assign endofpacketvalue_wr_strobe = wr_strobe & (mem_addr == 6);
assign TMT = ~transmitting & ~tx_holding_primed;
assign E = ROE | TOE;
assign spi_status = {EOP, E, RRDY, TRDY, TMT, TOE, ROE, 3'b0};
// Streaming data ready for pickup.
assign dataavailable = RRDY;
// Ready to accept streaming data.
assign readyfordata = TRDY;
// Endofpacket condition detected.
assign endofpacket = EOP;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
iEOP_reg <= 0;
iE_reg <= 0;
iRRDY_reg <= 0;
iTRDY_reg <= 0;
iTMT_reg <= 0;
iTOE_reg <= 0;
iROE_reg <= 0;
SSO_reg <= 0;
end
else if (control_wr_strobe)
begin
iEOP_reg <= data_from_cpu[9];
iE_reg <= data_from_cpu[8];
iRRDY_reg <= data_from_cpu[7];
iTRDY_reg <= data_from_cpu[6];
iTMT_reg <= data_from_cpu[5];
iTOE_reg <= data_from_cpu[4];
iROE_reg <= data_from_cpu[3];
SSO_reg <= data_from_cpu[10];
end
end
assign spi_control = {SSO_reg, iEOP_reg, iE_reg, iRRDY_reg, iTRDY_reg, 1'b0, iTOE_reg, iROE_reg, 3'b0};
// IRQ output.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
irq_reg <= 0;
else
irq_reg <= (EOP & iEOP_reg) | ((TOE | ROE) & iE_reg) | (RRDY & iRRDY_reg) | (TRDY & iTRDY_reg) | (TOE & iTOE_reg) | (ROE & iROE_reg);
end
assign irq = irq_reg;
// Slave select register.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
spi_slave_select_reg <= 1;
else if (write_shift_reg || control_wr_strobe & data_from_cpu[10] & ~SSO_reg)
spi_slave_select_reg <= spi_slave_select_holding_reg;
end
// Slave select holding register.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
spi_slave_select_holding_reg <= 1;
else if (slaveselect_wr_strobe)
spi_slave_select_holding_reg <= data_from_cpu;
end
// slowclock is active once every 3 system clock pulses.
assign slowclock = slowcount == 2'h2;
assign p1_slowcount = ({2 {(transmitting && !slowclock)}} & (slowcount + 1)) |
({2 {(~((transmitting && !slowclock)))}} & 0);
// Divide counter for SPI clock.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
slowcount <= 0;
else
slowcount <= p1_slowcount;
end
// End-of-packet value register.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
endofpacketvalue_reg <= 0;
else if (endofpacketvalue_wr_strobe)
endofpacketvalue_reg <= data_from_cpu;
end
assign p1_data_to_cpu = ((mem_addr == 2))? spi_status :
((mem_addr == 3))? spi_control :
((mem_addr == 6))? endofpacketvalue_reg :
((mem_addr == 5))? spi_slave_select_reg :
rx_holding_reg;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_to_cpu <= 0;
else
// Data to cpu.
data_to_cpu <= p1_data_to_cpu;
end
// 'state' counts from 0 to 17.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
state <= 0;
stateZero <= 1;
end
else if (transmitting & slowclock)
begin
stateZero <= state == 17;
if (state == 17)
state <= 0;
else
state <= state + 1;
end
end
assign enableSS = transmitting & ~stateZero;
assign MOSI = shift_reg[7];
assign SS_n = (enableSS | SSO_reg) ? ~spi_slave_select_reg : {1 {1'b1} };
assign SCLK = SCLK_reg;
// As long as there's an empty spot somewhere,
//it's safe to write data.
assign TRDY = ~(transmitting & tx_holding_primed);
// Enable write to tx_holding_register.
assign write_tx_holding = data_wr_strobe & TRDY;
// Enable write to shift register.
assign write_shift_reg = tx_holding_primed & ~transmitting;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
shift_reg <= 0;
rx_holding_reg <= 0;
EOP <= 0;
RRDY <= 0;
ROE <= 0;
TOE <= 0;
tx_holding_reg <= 0;
tx_holding_primed <= 0;
transmitting <= 0;
SCLK_reg <= 0;
MISO_reg <= 0;
end
else
begin
if (write_tx_holding)
begin
tx_holding_reg <= data_from_cpu;
tx_holding_primed <= 1;
end
if (data_wr_strobe & ~TRDY)
// You wrote when I wasn't ready.
TOE <= 1;
// EOP must be updated by the last (2nd) cycle of access.
if ((p1_data_rd_strobe && (rx_holding_reg == endofpacketvalue_reg)) || (p1_data_wr_strobe && (data_from_cpu[7 : 0] == endofpacketvalue_reg)))
EOP <= 1;
if (write_shift_reg)
begin
shift_reg <= tx_holding_reg;
transmitting <= 1;
end
if (write_shift_reg & ~write_tx_holding)
// Clear tx_holding_primed
tx_holding_primed <= 0;
if (data_rd_strobe)
// On data read, clear the RRDY bit.
RRDY <= 0;
if (status_wr_strobe)
begin
// On status write, clear all status bits (ignore the data).
EOP <= 0;
RRDY <= 0;
ROE <= 0;
TOE <= 0;
end
if (slowclock)
begin
if (state == 17)
begin
transmitting <= 0;
RRDY <= 1;
rx_holding_reg <= shift_reg;
SCLK_reg <= 0;
if (RRDY)
ROE <= 1;
end
else if (state != 0)
if (transmitting)
SCLK_reg <= ~SCLK_reg;
if (SCLK_reg ^ 0 ^ 0)
begin
if (1)
shift_reg <= {shift_reg[6 : 0], MISO_reg};
end
else
MISO_reg <= ds_MISO;
end
end
end
assign ds_MISO = MISO;
endmodule
|
/*
*******************************************************************************
* File Name : ada_branch_unit.v
* Project : ADA processor
* Version : 0.1
* Date : Aug 2nd, 2014
* Author : Angel Terrones <[email protected]>
*
* Disclaimer : Copyright © 2014 Angel Terrones
* Release under the MIT License.
*
* Description : Calculates the branch address.
*******************************************************************************
*/
`include "ada_defines.v"
module ada_branch_unit(
input [5:0] opcode, // Instruction opcode
input [31:0] pc, // Instruction address
input [31:0] data_reg_a, // Data from R0
input [31:0] data_reg_b, // Data from R1
input [20:0] imm21, // imm21/Imm16
output [31:0] pc_branch_address, // Destination address
output haz_take_branch, // 1 if the branch is taken
output exc_bad_branch_addr // 1 if pc_branch_address[1:0] != 0
);
//--------------------------------------------------------------------------
// Signal Declaration: reg
//--------------------------------------------------------------------------
reg [31:0] dest_address;
reg take_branch;
//--------------------------------------------------------------------------
// Signal Declaration: wire
//--------------------------------------------------------------------------
wire bg;
wire bgu;
wire bge;
wire bgeu;
wire eq;
wire neq;
wire [31:0] long_jump;
wire [31:0] short_jump;
wire [5:0] inst_function;
//--------------------------------------------------------------------------
// assigments
//--------------------------------------------------------------------------
assign pc_branch_address = dest_address;
assign haz_take_branch = take_branch;
assign exc_bad_branch_addr = (dest_address[1:0] == 2'b00 ? 1'b0 : 1'b1) & haz_take_branch;
assign bg = $signed(data_reg_a) > $signed(data_reg_b);
assign bgu = data_reg_a > data_reg_b;
assign bge = bg | eq;
assign bgeu = bgu | eq;
assign eq = data_reg_a == data_reg_b;
assign neq = ~eq;
assign long_jump = pc + $signed( { imm21, 2'b00 } ); // precalculate the jump
assign short_jump = pc + $signed( { imm21[`ADA_INSTR_IMM16], 2'b00 } ); // same here
assign inst_function = imm21[`ADA_INSTR_FUNCT];
//--------------------------------------------------------------------------
// Calculate the destination address
//--------------------------------------------------------------------------
always @(*) begin
case (opcode)
`OP_B : begin dest_address <= long_jump; take_branch <= 1'b1; end
`OP_BE : begin dest_address <= short_jump; take_branch <= eq ? 1'b1 : 1'b0; end
`OP_BG : begin dest_address <= short_jump; take_branch <= bg ? 1'b1 : 1'b0; end
`OP_BGE : begin dest_address <= short_jump; take_branch <= bge ? 1'b1 : 1'b0; end
`OP_BGEU : begin dest_address <= short_jump; take_branch <= bgeu ? 1'b1 : 1'b0; end
`OP_BGU : begin dest_address <= short_jump; take_branch <= bgu ? 1'b1 : 1'b0; end
`OP_BNE : begin dest_address <= short_jump; take_branch <= neq ? 1'b1 : 1'b0; end
`OP_CALL : begin dest_address <= long_jump; take_branch <= 1'b1; end
`OP_TYPE_RRR : begin
case(inst_function)
`EXT_OP_BR : begin dest_address <= data_reg_b; take_branch <= 1'b1; end
`EXT_OP_CALLR : begin dest_address <= data_reg_b; take_branch <= 1'b1; end
`EXT_OP_RETURN : begin dest_address <= data_reg_b; take_branch <= 1'b1; end
default : begin dest_address <= 32'bx00; take_branch <= 1'b0; end
endcase
end
default : begin dest_address <= 32'bx00; take_branch <= 1'b0; end
endcase
end
endmodule
|
// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_crossbar:2.1
// IP Revision: 5
(* X_CORE_INFO = "axi_crossbar_v2_1_axi_crossbar,Vivado 2014.4" *)
(* CHECK_LICENSE_TYPE = "Test_AXI_Master_simple_v1_0_hw_1_xbar_0,axi_crossbar_v2_1_axi_crossbar,{}" *)
(* CORE_GENERATION_INFO = "Test_AXI_Master_simple_v1_0_hw_1_xbar_0,axi_crossbar_v2_1_axi_crossbar,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_crossbar,x_ipVersion=2.1,x_ipCoreRevision=5,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_NUM_SLAVE_SLOTS=2,C_NUM_MASTER_SLOTS=1,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=32,C_AXI_PROTOCOL=2,C_NUM_ADDR_RANGES=1,C_M_AXI_BASE_ADDR=0x0000000044a00000,C_M_AXI_ADDR_WIDTH=0x00000010,C_S_AXI_BASE_ID=0x0000000100000000,C_S_AXI_THREAD_ID_WIDTH=0x0000000000000000,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_M_AXI_WRITE_CONNECTIVITY=0x00000003,C_M_AXI_READ_CONNECTIVITY=0x00000003,C_R_REGISTER=1,C_S_AXI_SINGLE_THREAD=0x0000000100000001,C_S_AXI_WRITE_ACCEPTANCE=0x0000000100000001,C_S_AXI_READ_ACCEPTANCE=0x0000000100000001,C_M_AXI_WRITE_ISSUING=0x00000001,C_M_AXI_READ_ISSUING=0x00000001,C_S_AXI_ARB_PRIORITY=0x0000000000000000,C_M_AXI_SECURE=0x00000000,C_CONNECTIVITY_MODE=0}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module Test_AXI_Master_simple_v1_0_hw_1_xbar_0 (
aclk,
aresetn,
s_axi_awaddr,
s_axi_awprot,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arprot,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 S01_AXI AWADDR [31:0] [63:32]" *)
input wire [63 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI AWPROT [2:0] [5:3]" *)
input wire [5 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWVALID [0:0] [1:1]" *)
input wire [1 : 0] s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWREADY [0:0] [1:1]" *)
output wire [1 : 0] s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 S01_AXI WDATA [31:0] [63:32]" *)
input wire [63 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI WSTRB [3:0] [7:4]" *)
input wire [7 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI WVALID [0:0] [1:1]" *)
input wire [1 : 0] s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI WREADY [0:0] [1:1]" *)
output wire [1 : 0] s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI BRESP [1:0] [3:2]" *)
output wire [3 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI BVALID [0:0] [1:1]" *)
output wire [1 : 0] s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI BREADY [0:0] [1:1]" *)
input wire [1 : 0] s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 S01_AXI ARADDR [31:0] [63:32]" *)
input wire [63 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI ARPROT [2:0] [5:3]" *)
input wire [5 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARVALID [0:0] [1:1]" *)
input wire [1 : 0] s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARREADY [0:0] [1:1]" *)
output wire [1 : 0] s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 S01_AXI RDATA [31:0] [63:32]" *)
output wire [63 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI RRESP [1:0] [3:2]" *)
output wire [3 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RVALID [0:0] [1:1]" *)
output wire [1 : 0] s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RREADY [0:0] [1:1]" *)
input wire [1 : 0] s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID" *)
output wire [0 : 0] m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY" *)
input wire [0 : 0] m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WDATA" *)
output wire [31 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB" *)
output wire [3 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WVALID" *)
output wire [0 : 0] m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WREADY" *)
input wire [0 : 0] m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BVALID" *)
input wire [0 : 0] m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BREADY" *)
output wire [0 : 0] m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID" *)
output wire [0 : 0] m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY" *)
input wire [0 : 0] m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RDATA" *)
input wire [31 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RVALID" *)
input wire [0 : 0] m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RREADY" *)
output wire [0 : 0] m_axi_rready;
axi_crossbar_v2_1_axi_crossbar #(
.C_FAMILY("zynq"),
.C_NUM_SLAVE_SLOTS(2),
.C_NUM_MASTER_SLOTS(1),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_PROTOCOL(2),
.C_NUM_ADDR_RANGES(1),
.C_M_AXI_BASE_ADDR(64'H0000000044a00000),
.C_M_AXI_ADDR_WIDTH(32'H00000010),
.C_S_AXI_BASE_ID(64'H0000000100000000),
.C_S_AXI_THREAD_ID_WIDTH(64'H0000000000000000),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_M_AXI_WRITE_CONNECTIVITY(32'H00000003),
.C_M_AXI_READ_CONNECTIVITY(32'H00000003),
.C_R_REGISTER(1),
.C_S_AXI_SINGLE_THREAD(64'H0000000100000001),
.C_S_AXI_WRITE_ACCEPTANCE(64'H0000000100000001),
.C_S_AXI_READ_ACCEPTANCE(64'H0000000100000001),
.C_M_AXI_WRITE_ISSUING(32'H00000001),
.C_M_AXI_READ_ISSUING(32'H00000001),
.C_S_AXI_ARB_PRIORITY(64'H0000000000000000),
.C_M_AXI_SECURE(32'H00000000),
.C_CONNECTIVITY_MODE(0)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(2'H0),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(16'H0000),
.s_axi_awsize(6'H00),
.s_axi_awburst(4'H0),
.s_axi_awlock(2'H0),
.s_axi_awcache(8'H00),
.s_axi_awprot(s_axi_awprot),
.s_axi_awqos(8'H00),
.s_axi_awuser(2'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(2'H0),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(2'H3),
.s_axi_wuser(2'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(2'H0),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(16'H0000),
.s_axi_arsize(6'H00),
.s_axi_arburst(4'H0),
.s_axi_arlock(2'H0),
.s_axi_arcache(8'H00),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos(8'H00),
.s_axi_aruser(2'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(1'H0),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(1'H0),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(1'H1),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : PCIeGen2x8If128_axi_basic_rx_null_gen.v
// Version : 3.2
// //
// Description: //
// TRN to AXI RX null generator. Generates null packets for use in //
// discontinue situations. //
// //
// Notes: //
// Optional notes section. //
// //
// Hierarchical: //
// axi_basic_top //
// axi_basic_rx //
// axi_basic_rx_null_gen //
// //
//----------------------------------------------------------------------------//
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module PCIeGen2x8If128_axi_basic_rx_null_gen # (
parameter C_DATA_WIDTH = 128, // RX/TX interface data width
parameter TCQ = 1, // Clock to Q time
// Do not override parameters below this line
parameter KEEP_WIDTH = C_DATA_WIDTH / 8 // KEEP width
) (
// AXI RX
//-----------
input [C_DATA_WIDTH-1:0] m_axis_rx_tdata, // RX data to user
input m_axis_rx_tvalid, // RX data is valid
input m_axis_rx_tready, // RX ready for data
input m_axis_rx_tlast, // RX data is last
input [21:0] m_axis_rx_tuser, // RX user signals
// Null Inputs
//-----------
output null_rx_tvalid, // NULL generated tvalid
output null_rx_tlast, // NULL generated tlast
output [KEEP_WIDTH-1:0] null_rx_tkeep, // NULL generated tkeep
output null_rdst_rdy, // NULL generated rdst_rdy
output reg [4:0] null_is_eof, // NULL generated is_eof
// System
//-----------
input user_clk, // user clock from block
input user_rst // user reset from block
);
localparam INTERFACE_WIDTH_DWORDS = (C_DATA_WIDTH == 128) ? 11'd4 :
(C_DATA_WIDTH == 64) ? 11'd2 : 11'd1;
//----------------------------------------------------------------------------//
// NULL packet generator state machine //
// This state machine shadows the AXI RX interface, tracking each packet as //
// it's passed to the AXI user. When a multi-cycle packet is detected, the //
// state machine automatically generates a "null" packet. In the event of a //
// discontinue, the RX pipeline can switch over to this null packet as //
// necessary. //
//----------------------------------------------------------------------------//
// State machine variables and states
localparam IDLE = 0;
localparam IN_PACKET = 1;
reg cur_state;
reg next_state;
// Signals for tracking a packet on the AXI interface
reg [11:0] reg_pkt_len_counter;
reg [11:0] pkt_len_counter;
wire [11:0] pkt_len_counter_dec;
wire pkt_done;
// Calculate packet fields, which are needed to determine total packet length.
wire [11:0] new_pkt_len;
wire [9:0] payload_len;
wire [1:0] packet_fmt;
wire packet_td;
reg [3:0] packet_overhead;
// Misc.
wire [KEEP_WIDTH-1:0] eof_tkeep;
wire straddle_sof;
wire eof;
// Create signals to detect sof and eof situations. These signals vary depending
// on data width.
assign eof = m_axis_rx_tuser[21];
generate
if(C_DATA_WIDTH == 128) begin : sof_eof_128
assign straddle_sof = (m_axis_rx_tuser[14:13] == 2'b11);
end
else begin : sof_eof_64_32
assign straddle_sof = 1'b0;
end
endgenerate
//----------------------------------------------------------------------------//
// Calculate the length of the packet being presented on the RX interface. To //
// do so, we need the relevent packet fields that impact total packet length. //
// These are: //
// - Header length: obtained from bit 1 of FMT field in 1st DWORD of header //
// - Payload length: obtained from LENGTH field in 1st DWORD of header //
// - TLP digest: obtained from TD field in 1st DWORD of header //
// - Current data: the number of bytes that have already been presented //
// on the data interface //
// //
// packet length = header + payload + tlp digest - # of DWORDS already //
// transmitted //
// //
// packet_overhead is where we calculate everything except payload. //
//----------------------------------------------------------------------------//
generate
if(C_DATA_WIDTH == 128) begin : len_calc_128
assign packet_fmt = straddle_sof ?
m_axis_rx_tdata[94:93] : m_axis_rx_tdata[30:29];
assign packet_td = straddle_sof ?
m_axis_rx_tdata[79] : m_axis_rx_tdata[15];
assign payload_len = packet_fmt[1] ?
(straddle_sof ? m_axis_rx_tdata[73:64] : m_axis_rx_tdata[9:0]) : 10'h0;
always @(*) begin
// In 128-bit mode, the amount of data currently on the interface
// depends on whether we're straddling or not. If so, 2 DWORDs have been
// seen. If not, 4 DWORDs.
case({packet_fmt[0], packet_td, straddle_sof})
// Header + TD - Data currently on interface
3'b0_0_0: packet_overhead = 4'd3 + 4'd0 - 4'd4;
3'b0_0_1: packet_overhead = 4'd3 + 4'd0 - 4'd2;
3'b0_1_0: packet_overhead = 4'd3 + 4'd1 - 4'd4;
3'b0_1_1: packet_overhead = 4'd3 + 4'd1 - 4'd2;
3'b1_0_0: packet_overhead = 4'd4 + 4'd0 - 4'd4;
3'b1_0_1: packet_overhead = 4'd4 + 4'd0 - 4'd2;
3'b1_1_0: packet_overhead = 4'd4 + 4'd1 - 4'd4;
3'b1_1_1: packet_overhead = 4'd4 + 4'd1 - 4'd2;
endcase
end
assign new_pkt_len =
{{9{packet_overhead[3]}}, packet_overhead[2:0]} + {2'b0, payload_len};
end
else if(C_DATA_WIDTH == 64) begin : len_calc_64
assign packet_fmt = m_axis_rx_tdata[30:29];
assign packet_td = m_axis_rx_tdata[15];
assign payload_len = packet_fmt[1] ? m_axis_rx_tdata[9:0] : 10'h0;
always @(*) begin
// 64-bit mode: no straddling, so always 2 DWORDs
case({packet_fmt[0], packet_td})
// Header + TD - Data currently on interface
2'b0_0: packet_overhead[1:0] = 2'b01 ;//4'd3 + 4'd0 - 4'd2; // 1
2'b0_1: packet_overhead[1:0] = 2'b10 ;//4'd3 + 4'd1 - 4'd2; // 2
2'b1_0: packet_overhead[1:0] = 2'b10 ;//4'd4 + 4'd0 - 4'd2; // 2
2'b1_1: packet_overhead[1:0] = 2'b11 ;//4'd4 + 4'd1 - 4'd2; // 3
endcase
end
assign new_pkt_len =
{{10{1'b0}}, packet_overhead[1:0]} + {2'b0, payload_len};
end
else begin : len_calc_32
assign packet_fmt = m_axis_rx_tdata[30:29];
assign packet_td = m_axis_rx_tdata[15];
assign payload_len = packet_fmt[1] ? m_axis_rx_tdata[9:0] : 10'h0;
always @(*) begin
// 32-bit mode: no straddling, so always 1 DWORD
case({packet_fmt[0], packet_td})
// Header + TD - Data currently on interface
2'b0_0: packet_overhead = 4'd3 + 4'd0 - 4'd1;
2'b0_1: packet_overhead = 4'd3 + 4'd1 - 4'd1;
2'b1_0: packet_overhead = 4'd4 + 4'd0 - 4'd1;
2'b1_1: packet_overhead = 4'd4 + 4'd1 - 4'd1;
endcase
end
assign new_pkt_len =
{{9{packet_overhead[3]}}, packet_overhead[2:0]} + {2'b0, payload_len};
end
endgenerate
// Now calculate actual packet length, adding the packet overhead and the
// payload length. This is signed math, so sign-extend packet_overhead.
// NOTE: a payload length of zero means 1024 DW in the PCIe spec, but this
// behavior isn't supported in our block.
//assign new_pkt_len =
// {{9{packet_overhead[3]}}, packet_overhead[2:0]} + {2'b0, payload_len};
// Math signals needed in the state machine below. These are seperate wires to
// help ensure synthesis tools sre smart about optimizing them.
assign pkt_len_counter_dec = reg_pkt_len_counter - INTERFACE_WIDTH_DWORDS;
assign pkt_done = (reg_pkt_len_counter <= INTERFACE_WIDTH_DWORDS);
//----------------------------------------------------------------------------//
// Null generator Mealy state machine. Determine outputs based on: //
// 1) current st //
// 2) current inp //
//----------------------------------------------------------------------------//
always @(*) begin
case (cur_state)
// IDLE state: the interface is IDLE and we're waiting for a packet to
// start. If a packet starts, move to state IN_PACKET and begin tracking
// it as long as it's NOT a single cycle packet (indicated by assertion of
// eof at packet start)
IDLE: begin
if(m_axis_rx_tvalid && m_axis_rx_tready && !eof) begin
next_state = IN_PACKET;
end
else begin
next_state = IDLE;
end
pkt_len_counter = new_pkt_len;
end
// IN_PACKET: a mutli-cycle packet is in progress and we're tracking it. We
// are in lock-step with the AXI interface decrementing our packet length
// tracking reg, and waiting for the packet to finish.
//
// * If packet finished and a new one starts, this is a straddle situation.
// Next state is IN_PACKET (128-bit only).
// * If the current packet is done, next state is IDLE.
// * Otherwise, next state is IN_PACKET.
IN_PACKET: begin
// Straddle packet
if((C_DATA_WIDTH == 128) && straddle_sof && m_axis_rx_tvalid) begin
pkt_len_counter = new_pkt_len;
next_state = IN_PACKET;
end
// Current packet finished
else if(m_axis_rx_tready && pkt_done)
begin
pkt_len_counter = new_pkt_len;
next_state = IDLE;
end
// Packet in progress
else begin
if(m_axis_rx_tready) begin
// Not throttled
pkt_len_counter = pkt_len_counter_dec;
end
else begin
// Throttled
pkt_len_counter = reg_pkt_len_counter;
end
next_state = IN_PACKET;
end
end
default: begin
pkt_len_counter = reg_pkt_len_counter;
next_state = IDLE;
end
endcase
end
// Synchronous NULL packet generator state machine logic
always @(posedge user_clk) begin
if(user_rst) begin
cur_state <= #TCQ IDLE;
reg_pkt_len_counter <= #TCQ 12'h0;
end
else begin
cur_state <= #TCQ next_state;
reg_pkt_len_counter <= #TCQ pkt_len_counter;
end
end
// Generate tkeep/is_eof for an end-of-packet situation.
generate
if(C_DATA_WIDTH == 128) begin : strb_calc_128
always @(*) begin
// Assign null_is_eof depending on how many DWORDs are left in the
// packet.
case(pkt_len_counter)
10'd1: null_is_eof = 5'b10011;
10'd2: null_is_eof = 5'b10111;
10'd3: null_is_eof = 5'b11011;
10'd4: null_is_eof = 5'b11111;
default: null_is_eof = 5'b00011;
endcase
end
// tkeep not used in 128-bit interface
assign eof_tkeep = {KEEP_WIDTH{1'b0}};
end
else if(C_DATA_WIDTH == 64) begin : strb_calc_64
always @(*) begin
// Assign null_is_eof depending on how many DWORDs are left in the
// packet.
case(pkt_len_counter)
10'd1: null_is_eof = 5'b10011;
10'd2: null_is_eof = 5'b10111;
default: null_is_eof = 5'b00011;
endcase
end
// Assign tkeep to 0xFF or 0x0F depending on how many DWORDs are left in
// the current packet.
assign eof_tkeep = { ((pkt_len_counter == 12'd2) ? 4'hF:4'h0), 4'hF };
end
else begin : strb_calc_32
always @(*) begin
// is_eof is either on or off for 32-bit
if(pkt_len_counter == 12'd1) begin
null_is_eof = 5'b10011;
end
else begin
null_is_eof = 5'b00011;
end
end
// The entire DWORD is always valid in 32-bit mode, so tkeep is always 0xF
assign eof_tkeep = 4'hF;
end
endgenerate
// Finally, use everything we've generated to calculate our NULL outputs
assign null_rx_tvalid = 1'b1;
assign null_rx_tlast = (pkt_len_counter <= INTERFACE_WIDTH_DWORDS);
assign null_rx_tkeep = null_rx_tlast ? eof_tkeep : {KEEP_WIDTH{1'b1}};
assign null_rdst_rdy = null_rx_tlast;
endmodule
|
//-----------------------------------------------------------------------------
// Copyright (C) 2014 iZsh <izsh at fail0verflow.com>
//
// This code is licensed to you under the terms of the GNU GPL, version 2 or,
// at your option, any later version. See the LICENSE.txt file for the text of
// the license.
//-----------------------------------------------------------------------------
// testbench for lf_edge_detect
`include "lf_edge_detect.v"
`define FIN "tb_tmp/data.filtered.gold"
`define FOUT_MIN "tb_tmp/data.min"
`define FOUT_MAX "tb_tmp/data.max"
`define FOUT_STATE "tb_tmp/data.state"
`define FOUT_TOGGLE "tb_tmp/data.toggle"
`define FOUT_HIGH "tb_tmp/data.high"
`define FOUT_HIGHZ "tb_tmp/data.highz"
`define FOUT_LOWZ "tb_tmp/data.lowz"
`define FOUT_LOW "tb_tmp/data.low"
module lf_edge_detect_tb;
integer fin, fout_state, fout_toggle;
integer fout_high, fout_highz, fout_lowz, fout_low, fout_min, fout_max;
integer r;
reg clk = 0;
reg [7:0] adc_d;
wire adc_clk;
wire data_rdy;
wire edge_state;
wire edge_toggle;
wire [7:0] high_threshold;
wire [7:0] highz_threshold;
wire [7:0] lowz_threshold;
wire [7:0] low_threshold;
wire [7:0] max;
wire [7:0] min;
initial
begin
clk = 0;
fin = $fopen(`FIN, "r");
if (!fin) begin
$display("ERROR: can't open the data file");
$finish;
end
fout_min = $fopen(`FOUT_MIN, "w+");
fout_max = $fopen(`FOUT_MAX, "w+");
fout_state = $fopen(`FOUT_STATE, "w+");
fout_toggle = $fopen(`FOUT_TOGGLE, "w+");
fout_high = $fopen(`FOUT_HIGH, "w+");
fout_highz = $fopen(`FOUT_HIGHZ, "w+");
fout_lowz = $fopen(`FOUT_LOWZ, "w+");
fout_low = $fopen(`FOUT_LOW, "w+");
if (!$feof(fin))
adc_d = $fgetc(fin); // read the first value
end
always
# 1 clk = !clk;
// input
initial
begin
while (!$feof(fin)) begin
@(negedge clk) adc_d <= $fgetc(fin);
end
if ($feof(fin))
begin
# 3 $fclose(fin);
$fclose(fout_state);
$fclose(fout_toggle);
$fclose(fout_high);
$fclose(fout_highz);
$fclose(fout_lowz);
$fclose(fout_low);
$fclose(fout_min);
$fclose(fout_max);
$finish;
end
end
initial
begin
// $monitor("%d\t S: %b, E: %b", $time, edge_state, edge_toggle);
end
// output
always @(negedge clk)
if ($time > 2) begin
r = $fputc(min, fout_min);
r = $fputc(max, fout_max);
r = $fputc(edge_state, fout_state);
r = $fputc(edge_toggle, fout_toggle);
r = $fputc(high_threshold, fout_high);
r = $fputc(highz_threshold, fout_highz);
r = $fputc(lowz_threshold, fout_lowz);
r = $fputc(low_threshold, fout_low);
end
// module to test
lf_edge_detect detect(clk, adc_d, 8'd127,
max, min,
high_threshold, highz_threshold,
lowz_threshold, low_threshold,
edge_state, edge_toggle);
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A211OI_2_V
`define SKY130_FD_SC_MS__A211OI_2_V
/**
* a211oi: 2-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2) | B1 | C1)
*
* Verilog wrapper for a211oi with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a211oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a211oi_2 (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__a211oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a211oi_2 (
Y ,
A1,
A2,
B1,
C1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__a211oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__A211OI_2_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__UDP_DLATCH_P_TB_V
`define SKY130_FD_SC_HD__UDP_DLATCH_P_TB_V
/**
* udp_dlatch$P: D-latch, gated standard drive / active high
* (Q output UDP)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__udp_dlatch_p.v"
module top();
// Inputs are registered
reg D;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
#20 D = 1'b0;
#40 D = 1'b1;
#60 D = 1'b0;
#80 D = 1'b1;
#100 D = 1'bx;
end
// Create a clock
reg GATE;
initial
begin
GATE = 1'b0;
end
always
begin
#5 GATE = ~GATE;
end
sky130_fd_sc_hd__udp_dlatch$P dut (.D(D), .Q(Q), .GATE(GATE));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__UDP_DLATCH_P_TB_V
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// synopsys translate_off
`timescale 1 ns / 1 ns
// synopsys translate_on
module altera_jtag_sld_node (
ir_out,
tdo,
ir_in,
tck,
tdi,
virtual_state_cdr,
virtual_state_cir,
virtual_state_e1dr,
virtual_state_e2dr,
virtual_state_pdr,
virtual_state_sdr,
virtual_state_udr,
virtual_state_uir
);
parameter TCK_FREQ_MHZ = 20;
localparam TCK_HALF_PERIOD_US = (1000/TCK_FREQ_MHZ)/2;
localparam IRWIDTH = 3;
input [IRWIDTH - 1:0] ir_out;
input tdo;
output reg [IRWIDTH - 1:0] ir_in;
output tck;
output reg tdi = 1'b0;
output virtual_state_cdr;
output virtual_state_cir;
output virtual_state_e1dr;
output virtual_state_e2dr;
output virtual_state_pdr;
output virtual_state_sdr;
output virtual_state_udr;
output virtual_state_uir;
// PHY Simulation signals
`ifndef ALTERA_RESERVED_QIS
reg simulation_clock;
reg sdrs;
reg cdr;
reg sdr;
reg e1dr;
reg udr;
reg [7:0] bit_index;
`endif
// PHY Instantiation
`ifdef ALTERA_RESERVED_QIS
wire tdi_port;
wire [IRWIDTH - 1:0] ir_in_port;
always @(tdi_port)
tdi = tdi_port;
always @(ir_in_port)
ir_in = ir_in_port;
sld_virtual_jtag_basic sld_virtual_jtag_component (
.ir_out (ir_out),
.tdo (tdo),
.tdi (tdi_port),
.tck (tck),
.ir_in (ir_in_port),
.virtual_state_cir (virtual_state_cir),
.virtual_state_pdr (virtual_state_pdr),
.virtual_state_uir (virtual_state_uir),
.virtual_state_sdr (virtual_state_sdr),
.virtual_state_cdr (virtual_state_cdr),
.virtual_state_udr (virtual_state_udr),
.virtual_state_e1dr (virtual_state_e1dr),
.virtual_state_e2dr (virtual_state_e2dr)
// synopsys translate_off
,
.jtag_state_cdr (),
.jtag_state_cir (),
.jtag_state_e1dr (),
.jtag_state_e1ir (),
.jtag_state_e2dr (),
.jtag_state_e2ir (),
.jtag_state_pdr (),
.jtag_state_pir (),
.jtag_state_rti (),
.jtag_state_sdr (),
.jtag_state_sdrs (),
.jtag_state_sir (),
.jtag_state_sirs (),
.jtag_state_tlr (),
.jtag_state_udr (),
.jtag_state_uir (),
.tms ()
// synopsys translate_on
);
defparam
sld_virtual_jtag_component.sld_mfg_id = 110,
sld_virtual_jtag_component.sld_type_id = 132,
sld_virtual_jtag_component.sld_version = 1,
sld_virtual_jtag_component.sld_auto_instance_index = "YES",
sld_virtual_jtag_component.sld_instance_index = 0,
sld_virtual_jtag_component.sld_ir_width = IRWIDTH,
sld_virtual_jtag_component.sld_sim_action = "",
sld_virtual_jtag_component.sld_sim_n_scan = 0,
sld_virtual_jtag_component.sld_sim_total_length = 0;
`endif
// PHY Simulation
`ifndef ALTERA_RESERVED_QIS
localparam DATA = 0;
localparam LOOPBACK = 1;
localparam DEBUG = 2;
localparam INFO = 3;
localparam CONTROL = 4;
localparam MGMT = 5;
always
//#TCK_HALF_PERIOD_US simulation_clock = $random;
#TCK_HALF_PERIOD_US simulation_clock = ~simulation_clock;
assign tck = simulation_clock;
assign virtual_state_cdr = cdr;
assign virtual_state_sdr = sdr;
assign virtual_state_e1dr = e1dr;
assign virtual_state_udr = udr;
task reset_jtag_state;
begin
simulation_clock = 0;
enter_data_mode;
clear_states_async;
end
endtask
task enter_data_mode;
begin
ir_in = DATA;
clear_states;
end
endtask
task enter_loopback_mode;
begin
ir_in = LOOPBACK;
clear_states;
end
endtask
task enter_debug_mode;
begin
ir_in = DEBUG;
clear_states;
end
endtask
task enter_info_mode;
begin
ir_in = INFO;
clear_states;
end
endtask
task enter_control_mode;
begin
ir_in = CONTROL;
clear_states;
end
endtask
task enter_mgmt_mode;
begin
ir_in = MGMT;
clear_states;
end
endtask
task enter_sdrs_state;
begin
{sdrs, cdr, sdr, e1dr, udr} = 5'b10000;
tdi = 1'b0;
@(posedge tck);
end
endtask
task enter_cdr_state;
begin
{sdrs, cdr, sdr, e1dr, udr} = 5'b01000;
tdi = 1'b0;
@(posedge tck);
end
endtask
task enter_e1dr_state;
begin
{sdrs, cdr, sdr, e1dr, udr} = 5'b00010;
tdi = 1'b0;
@(posedge tck);
end
endtask
task enter_udr_state;
begin
{sdrs, cdr, sdr, e1dr, udr} = 5'b00001;
tdi = 1'b0;
@(posedge tck);
end
endtask
task clear_states;
begin
clear_states_async;
@(posedge tck);
end
endtask
task clear_states_async;
begin
{cdr, sdr, e1dr, udr} = 4'b0000;
end
endtask
task shift_one_bit;
input bit_to_send;
output reg bit_received;
begin
{cdr, sdr, e1dr, udr} = 4'b0100;
tdi = bit_to_send;
@(posedge tck);
bit_received = tdo;
end
endtask
task shift_one_byte;
input [7:0] byte_to_send;
output reg [7:0] byte_received;
integer i;
reg bit_received;
begin
for (i=0; i<8; i=i+1)
begin
bit_index = i;
shift_one_bit(byte_to_send[i], bit_received);
byte_received[i] = bit_received;
end
end
endtask
`endif
endmodule
|
// File: pwm_TBV.v
// Generated by MyHDL 0.10
// Date: Mon Aug 20 12:45:58 2018
`timescale 1ns/10ps
module pwm_TBV (
);
// myHDL-> Verilog Testbench for `pwm`
reg clk = 0;
reg [7:0] dutyCount = 0;
reg ofState = 0;
reg [7:0] pwm0_0_counter = 0;
always @(dutyCount, ofState, clk) begin: PWM_TBV_PRINT_DATA
$write("%h", clk);
$write(" ");
$write("%h", dutyCount);
$write(" ");
$write("%h", ofState);
$write("\n");
end
always @(posedge clk) begin: PWM_TBV_PWM0_0_LOGIC
pwm0_0_counter <= (pwm0_0_counter + 1);
ofState <= (pwm0_0_counter < dutyCount);
end
initial begin: PWM_TBV_CLK_SIGNAL
while (1'b1) begin
clk <= (!clk);
# 1;
end
end
initial begin: PWM_TBV_STIMULES
integer i;
i = 0;
while (1'b1) begin
case (i)
'h5: begin
dutyCount <= 20;
end
'h2d: begin
dutyCount <= 80;
end
'h64: begin
$finish;
end
default: begin
// pass
end
endcase
i = i + 1;
@(posedge clk);
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11:21:14 08/24/2011
// Design Name:
// Module Name: q15_mult
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module qmult #(
//Parameterized values
parameter Q = 15,
parameter N = 32
)
(
input [N-1:0] i_multiplicand,
input [N-1:0] i_multiplier,
output [N-1:0] o_result,
output reg ovr
);
// The underlying assumption, here, is that both fixed-point values are of the same length (N,Q)
// Because of this, the results will be of length N+N = 2N bits....
// This also simplifies the hand-back of results, as the binimal point
// will always be in the same location...
reg [2*N-1:0] r_result; // Multiplication by 2 values of N bits requires a
// register that is N+N = 2N deep...
reg [N-1:0] r_RetVal;
//--------------------------------------------------------------------------------
assign o_result = r_RetVal; // Only handing back the same number of bits as we received...
// with fixed point in same location...
//---------------------------------------------------------------------------------
always @(i_multiplicand, i_multiplier) begin // Do the multiply any time the inputs change
r_result <= i_multiplicand[N-2:0] * i_multiplier[N-2:0]; // Removing the sign bits from the multiply - that
// would introduce *big* errors
ovr <= 1'b0; // reset overflow flag to zero
end
// This always block will throw a warning, as it uses a & b, but only acts on changes in result...
always @(r_result) begin // Any time the result changes, we need to recompute the sign bit,
r_RetVal[N-1] <= i_multiplicand[N-1] ^ i_multiplier[N-1]; // which is the XOR of the input sign bits... (you do the truth table...)
r_RetVal[N-2:0] <= r_result[N-2+Q:Q]; // And we also need to push the proper N bits of result up to
// the calling entity...
if (r_result[2*N-2:N-1+Q] > 0) // And finally, we need to check for an overflow
ovr <= 1'b1;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFRTP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__SDFRTP_FUNCTIONAL_PP_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hdll__udp_mux_2to1.v"
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_hdll__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hdll__sdfrtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_hdll__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hdll__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, RESET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFRTP_FUNCTIONAL_PP_V |
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_rx_tag # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter P_FIFO_DEPTH_WIDTH = 9
)
(
input pcie_user_clk,
input pcie_user_rst_n,
input pcie_tag_alloc,
input [7:0] pcie_alloc_tag,
input [9:4] pcie_tag_alloc_len,
output pcie_tag_full_n,
input [7:0] cpld_fifo_tag,
input [C_PCIE_DATA_WIDTH-1:0] cpld_fifo_wr_data,
input cpld_fifo_wr_en,
input cpld_fifo_tag_last,
output fifo_wr_en,
output [P_FIFO_DEPTH_WIDTH-1:0] fifo_wr_addr,
output [C_PCIE_DATA_WIDTH-1:0] fifo_wr_data,
output [P_FIFO_DEPTH_WIDTH:0] rear_full_addr,
output [P_FIFO_DEPTH_WIDTH:0] rear_addr
);
localparam LP_PCIE_TAG_PREFIX = 4'b0001;
localparam LP_PCIE_TAG_WITDH = 4;
localparam LP_NUM_OF_PCIE_TAG = 8;
reg [LP_NUM_OF_PCIE_TAG:0] r_pcie_tag_rear;
reg [LP_NUM_OF_PCIE_TAG:0] r_pcie_tag_front;
reg [P_FIFO_DEPTH_WIDTH:0] r_alloc_base_addr;
reg [LP_PCIE_TAG_WITDH-1:0] r_pcie_tag [LP_NUM_OF_PCIE_TAG-1:0];
reg [P_FIFO_DEPTH_WIDTH:0] r_pcie_tag_addr [LP_NUM_OF_PCIE_TAG-1:0];
(* KEEP = "TRUE", EQUIVALENT_REGISTER_REMOVAL = "NO" *) reg [C_PCIE_DATA_WIDTH-1:0] r_cpld_fifo_wr_data;
reg r_cpld_fifo_wr_en;
reg r_cpld_fifo_tag_last;
wire [LP_NUM_OF_PCIE_TAG-1:0] w_pcie_tag_hit;
reg [LP_NUM_OF_PCIE_TAG-1:0] r_pcie_tag_hit;
reg [LP_NUM_OF_PCIE_TAG-1:0] r_pcie_tag_alloc_mask;
reg [LP_NUM_OF_PCIE_TAG-1:0] r_pcie_tag_update_mask;
reg [LP_NUM_OF_PCIE_TAG-1:0] r_pcie_tag_invalid_mask;
reg [LP_NUM_OF_PCIE_TAG-1:0] r_pcie_tag_free_mask;
reg [LP_NUM_OF_PCIE_TAG-1:0] r_pcie_tag_valid;
reg [LP_NUM_OF_PCIE_TAG-1:0] r_pcie_tag_invalid;
reg [P_FIFO_DEPTH_WIDTH:0] r_rear_addr;
reg [P_FIFO_DEPTH_WIDTH-1:0] r_fifo_wr_addr;
assign pcie_tag_full_n = ~((r_pcie_tag_rear[LP_NUM_OF_PCIE_TAG] ^ r_pcie_tag_front[LP_NUM_OF_PCIE_TAG])
& (r_pcie_tag_rear[LP_NUM_OF_PCIE_TAG-1:0] == r_pcie_tag_front[LP_NUM_OF_PCIE_TAG-1:0]));
assign fifo_wr_en = r_cpld_fifo_wr_en;
assign fifo_wr_addr = r_fifo_wr_addr;
assign fifo_wr_data = r_cpld_fifo_wr_data;
assign rear_full_addr = r_alloc_base_addr;
assign rear_addr = r_rear_addr;
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0) begin
r_pcie_tag_rear <= 1;
r_alloc_base_addr <= 0;
r_pcie_tag[0] <= {LP_PCIE_TAG_WITDH{1'b1}};
r_pcie_tag[1] <= {LP_PCIE_TAG_WITDH{1'b1}};
r_pcie_tag[2] <= {LP_PCIE_TAG_WITDH{1'b1}};
r_pcie_tag[3] <= {LP_PCIE_TAG_WITDH{1'b1}};
r_pcie_tag[4] <= {LP_PCIE_TAG_WITDH{1'b1}};
r_pcie_tag[5] <= {LP_PCIE_TAG_WITDH{1'b1}};
r_pcie_tag[6] <= {LP_PCIE_TAG_WITDH{1'b1}};
r_pcie_tag[7] <= {LP_PCIE_TAG_WITDH{1'b1}};
end
else begin
if(pcie_tag_alloc == 1) begin
r_pcie_tag_rear[LP_NUM_OF_PCIE_TAG-1:0] <= {r_pcie_tag_rear[LP_NUM_OF_PCIE_TAG-2:0], r_pcie_tag_rear[LP_NUM_OF_PCIE_TAG-1]};
r_alloc_base_addr <= r_alloc_base_addr + pcie_tag_alloc_len;
if(r_pcie_tag_rear[LP_NUM_OF_PCIE_TAG-1] == 1)
r_pcie_tag_rear[LP_NUM_OF_PCIE_TAG] <= ~r_pcie_tag_rear[LP_NUM_OF_PCIE_TAG];
end
if(r_pcie_tag_alloc_mask[0])
r_pcie_tag[0] <= pcie_alloc_tag[LP_PCIE_TAG_WITDH-1:0];
if(r_pcie_tag_alloc_mask[1])
r_pcie_tag[1] <= pcie_alloc_tag[LP_PCIE_TAG_WITDH-1:0];
if(r_pcie_tag_alloc_mask[2])
r_pcie_tag[2] <= pcie_alloc_tag[LP_PCIE_TAG_WITDH-1:0];
if(r_pcie_tag_alloc_mask[3])
r_pcie_tag[3] <= pcie_alloc_tag[LP_PCIE_TAG_WITDH-1:0];
if(r_pcie_tag_alloc_mask[4])
r_pcie_tag[4] <= pcie_alloc_tag[LP_PCIE_TAG_WITDH-1:0];
if(r_pcie_tag_alloc_mask[5])
r_pcie_tag[5] <= pcie_alloc_tag[LP_PCIE_TAG_WITDH-1:0];
if(r_pcie_tag_alloc_mask[6])
r_pcie_tag[6] <= pcie_alloc_tag[LP_PCIE_TAG_WITDH-1:0];
if(r_pcie_tag_alloc_mask[7])
r_pcie_tag[7] <= pcie_alloc_tag[LP_PCIE_TAG_WITDH-1:0];
end
end
always @ (*)
begin
if(pcie_tag_alloc == 1)
r_pcie_tag_alloc_mask <= r_pcie_tag_rear[LP_NUM_OF_PCIE_TAG-1:0];
else
r_pcie_tag_alloc_mask <= 0;
if(cpld_fifo_wr_en == 1)
r_pcie_tag_update_mask <= w_pcie_tag_hit;
else
r_pcie_tag_update_mask <= 0;
if(r_cpld_fifo_tag_last == 1)
r_pcie_tag_invalid_mask <= r_pcie_tag_hit;
else
r_pcie_tag_invalid_mask <= 0;
r_pcie_tag_free_mask <= r_pcie_tag_valid & r_pcie_tag_invalid & r_pcie_tag_front[LP_NUM_OF_PCIE_TAG-1:0];
end
always @ (posedge pcie_user_clk)
begin
case({r_pcie_tag_update_mask[0], r_pcie_tag_alloc_mask[0]}) // synthesis parallel_case
2'b01: r_pcie_tag_addr[0] <= r_alloc_base_addr;
2'b10: r_pcie_tag_addr[0] <= r_pcie_tag_addr[0] + 1;
endcase
case({r_pcie_tag_update_mask[1], r_pcie_tag_alloc_mask[1]}) // synthesis parallel_case
2'b01: r_pcie_tag_addr[1] <= r_alloc_base_addr;
2'b10: r_pcie_tag_addr[1] <= r_pcie_tag_addr[1] + 1;
endcase
case({r_pcie_tag_update_mask[2], r_pcie_tag_alloc_mask[2]}) // synthesis parallel_case
2'b01: r_pcie_tag_addr[2] <= r_alloc_base_addr;
2'b10: r_pcie_tag_addr[2] <= r_pcie_tag_addr[2] + 1;
endcase
case({r_pcie_tag_update_mask[3], r_pcie_tag_alloc_mask[3]}) // synthesis parallel_case
2'b01: r_pcie_tag_addr[3] <= r_alloc_base_addr;
2'b10: r_pcie_tag_addr[3] <= r_pcie_tag_addr[3] + 1;
endcase
case({r_pcie_tag_update_mask[4], r_pcie_tag_alloc_mask[4]}) // synthesis parallel_case
2'b01: r_pcie_tag_addr[4] <= r_alloc_base_addr;
2'b10: r_pcie_tag_addr[4] <= r_pcie_tag_addr[4] + 1;
endcase
case({r_pcie_tag_update_mask[5], r_pcie_tag_alloc_mask[5]}) // synthesis parallel_case
2'b01: r_pcie_tag_addr[5] <= r_alloc_base_addr;
2'b10: r_pcie_tag_addr[5] <= r_pcie_tag_addr[5] + 1;
endcase
case({r_pcie_tag_update_mask[6], r_pcie_tag_alloc_mask[6]}) // synthesis parallel_case
2'b01: r_pcie_tag_addr[6] <= r_alloc_base_addr;
2'b10: r_pcie_tag_addr[6] <= r_pcie_tag_addr[6] + 1;
endcase
case({r_pcie_tag_update_mask[7], r_pcie_tag_alloc_mask[7]}) // synthesis parallel_case
2'b01: r_pcie_tag_addr[7] <= r_alloc_base_addr;
2'b10: r_pcie_tag_addr[7] <= r_pcie_tag_addr[7] + 1;
endcase
end
assign w_pcie_tag_hit[0] = (r_pcie_tag[0] == cpld_fifo_tag[LP_PCIE_TAG_WITDH-1:0]) & r_pcie_tag_valid[0];
assign w_pcie_tag_hit[1] = (r_pcie_tag[1] == cpld_fifo_tag[LP_PCIE_TAG_WITDH-1:0]) & r_pcie_tag_valid[1];
assign w_pcie_tag_hit[2] = (r_pcie_tag[2] == cpld_fifo_tag[LP_PCIE_TAG_WITDH-1:0]) & r_pcie_tag_valid[2];
assign w_pcie_tag_hit[3] = (r_pcie_tag[3] == cpld_fifo_tag[LP_PCIE_TAG_WITDH-1:0]) & r_pcie_tag_valid[3];
assign w_pcie_tag_hit[4] = (r_pcie_tag[4] == cpld_fifo_tag[LP_PCIE_TAG_WITDH-1:0]) & r_pcie_tag_valid[4];
assign w_pcie_tag_hit[5] = (r_pcie_tag[5] == cpld_fifo_tag[LP_PCIE_TAG_WITDH-1:0]) & r_pcie_tag_valid[5];
assign w_pcie_tag_hit[6] = (r_pcie_tag[6] == cpld_fifo_tag[LP_PCIE_TAG_WITDH-1:0]) & r_pcie_tag_valid[6];
assign w_pcie_tag_hit[7] = (r_pcie_tag[7] == cpld_fifo_tag[LP_PCIE_TAG_WITDH-1:0]) & r_pcie_tag_valid[7];
always @ (posedge pcie_user_clk)
begin
r_cpld_fifo_tag_last <= cpld_fifo_tag_last;
r_cpld_fifo_wr_en <= cpld_fifo_wr_en;
r_cpld_fifo_wr_data <= cpld_fifo_wr_data;
end
always @ (posedge pcie_user_clk)
begin
r_pcie_tag_hit <= w_pcie_tag_hit;
case(w_pcie_tag_hit) // synthesis parallel_case
8'b00000001: r_fifo_wr_addr <= r_pcie_tag_addr[0][P_FIFO_DEPTH_WIDTH-1:0];
8'b00000010: r_fifo_wr_addr <= r_pcie_tag_addr[1][P_FIFO_DEPTH_WIDTH-1:0];
8'b00000100: r_fifo_wr_addr <= r_pcie_tag_addr[2][P_FIFO_DEPTH_WIDTH-1:0];
8'b00001000: r_fifo_wr_addr <= r_pcie_tag_addr[3][P_FIFO_DEPTH_WIDTH-1:0];
8'b00010000: r_fifo_wr_addr <= r_pcie_tag_addr[4][P_FIFO_DEPTH_WIDTH-1:0];
8'b00100000: r_fifo_wr_addr <= r_pcie_tag_addr[5][P_FIFO_DEPTH_WIDTH-1:0];
8'b01000000: r_fifo_wr_addr <= r_pcie_tag_addr[6][P_FIFO_DEPTH_WIDTH-1:0];
8'b10000000: r_fifo_wr_addr <= r_pcie_tag_addr[7][P_FIFO_DEPTH_WIDTH-1:0];
endcase
end
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0) begin
r_pcie_tag_front <= 1;
r_rear_addr <= 0;
r_pcie_tag_valid <= 0;
r_pcie_tag_invalid <= 0;
end
else begin
r_pcie_tag_valid <= (r_pcie_tag_valid | r_pcie_tag_alloc_mask) & ~r_pcie_tag_free_mask;
r_pcie_tag_invalid <= (r_pcie_tag_invalid | r_pcie_tag_invalid_mask) & ~r_pcie_tag_free_mask;
if(r_pcie_tag_free_mask != 0) begin
r_pcie_tag_front[LP_NUM_OF_PCIE_TAG-1:0] <= {r_pcie_tag_front[LP_NUM_OF_PCIE_TAG-2:0], r_pcie_tag_front[LP_NUM_OF_PCIE_TAG-1]};
if(r_pcie_tag_front[LP_NUM_OF_PCIE_TAG-1] == 1)
r_pcie_tag_front[LP_NUM_OF_PCIE_TAG] <= ~r_pcie_tag_front[LP_NUM_OF_PCIE_TAG];
end
case(r_pcie_tag_free_mask) // synthesis parallel_case
8'b00000001: r_rear_addr <= r_pcie_tag_addr[0];
8'b00000010: r_rear_addr <= r_pcie_tag_addr[1];
8'b00000100: r_rear_addr <= r_pcie_tag_addr[2];
8'b00001000: r_rear_addr <= r_pcie_tag_addr[3];
8'b00010000: r_rear_addr <= r_pcie_tag_addr[4];
8'b00100000: r_rear_addr <= r_pcie_tag_addr[5];
8'b01000000: r_rear_addr <= r_pcie_tag_addr[6];
8'b10000000: r_rear_addr <= r_pcie_tag_addr[7];
endcase
end
end
endmodule
|
//altremote_update CBX_AUTO_BLACKBOX="ALL" CBX_SINGLE_OUTPUT_FILE="ON" check_app_pof="false" config_device_addr_width=24 DEVICE_FAMILY="Cyclone IV E" in_data_width=24 is_epcq="false" operation_mode="remote" out_data_width=29 busy clock ctl_nupdt data_in data_out param read_param read_source reconfig reset reset_timer write_param
//VERSION_BEGIN 16.1 cbx_altremote_update 2016:10:19:21:26:20:SJ cbx_cycloneii 2016:10:19:21:26:20:SJ cbx_lpm_add_sub 2016:10:19:21:26:20:SJ cbx_lpm_compare 2016:10:19:21:26:20:SJ cbx_lpm_counter 2016:10:19:21:26:20:SJ cbx_lpm_decode 2016:10:19:21:26:20:SJ cbx_lpm_shiftreg 2016:10:19:21:26:20:SJ cbx_mgl 2016:10:19:22:10:30:SJ cbx_nadder 2016:10:19:21:26:20:SJ cbx_nightfury 2016:10:19:21:26:20:SJ cbx_stratix 2016:10:19:21:26:20:SJ cbx_stratixii 2016:10:19:21:26:20:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License
// Subscription Agreement, the Intel Quartus Prime License Agreement,
// the Intel MegaCore Function License Agreement, or other
// applicable license agreement, including, without limitation,
// that your use is for the sole purpose of programming logic
// devices manufactured by Intel and sold by Intel or its
// authorized distributors. Please refer to the applicable
// agreement for further details.
//synthesis_resources = cycloneive_rublock 1 lpm_counter 2 reg 62
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"suppress_da_rule_internal=c104;suppress_da_rule_internal=C101;suppress_da_rule_internal=C103"} *)
module altera_remote_update_core
(
busy,
clock,
ctl_nupdt,
data_in,
data_out,
param,
read_param,
read_source,
reconfig,
reset,
reset_timer,
write_param) /* synthesis synthesis_clearbox=1 */;
output busy;
input clock;
input ctl_nupdt;
input [23:0] data_in;
output [28:0] data_out;
input [2:0] param;
input read_param;
input [1:0] read_source;
input reconfig;
input reset;
input reset_timer;
input write_param;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 ctl_nupdt;
tri0 [23:0] data_in;
tri0 [2:0] param;
tri0 read_param;
tri0 [1:0] read_source;
tri0 reconfig;
tri0 reset_timer;
tri0 write_param;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg [0:0] check_busy_dffe;
reg [0:0] dffe1a0;
reg [0:0] dffe1a1;
wire [1:0] wire_dffe1a_ena;
reg [0:0] dffe2a0;
reg [0:0] dffe2a1;
reg [0:0] dffe2a2;
wire [2:0] wire_dffe2a_ena;
reg [0:0] dffe3a0;
reg [0:0] dffe3a1;
reg [0:0] dffe3a2;
wire [2:0] wire_dffe3a_ena;
reg [28:0] dffe7a;
wire [28:0] wire_dffe7a_ena;
reg dffe8;
reg [6:0] dffe9a;
wire [6:0] wire_dffe9a_ena;
reg idle_state;
reg idle_write_wait;
reg read_address_state;
wire wire_read_address_state_ena;
reg read_data_state;
reg read_init_counter_state;
reg read_init_state;
reg read_post_state;
reg read_pre_data_state;
reg read_source_update_state;
reg write_data_state;
reg write_init_counter_state;
reg write_init_state;
reg write_load_state;
reg write_post_data_state;
reg write_pre_data_state;
reg write_source_update_state;
reg write_wait_state;
wire [5:0] wire_cntr5_q;
wire [4:0] wire_cntr6_q;
wire wire_sd4_regout;
wire bit_counter_all_done;
wire bit_counter_clear;
wire bit_counter_enable;
wire [5:0] bit_counter_param_start;
wire bit_counter_param_start_match;
wire [6:0] combine_port;
wire global_gnd;
wire global_vcc;
wire idle;
wire [6:0] param_decoder_param_latch;
wire [22:0] param_decoder_select;
wire power_up;
wire read_address;
wire read_data;
wire read_init;
wire read_init_counter;
wire read_post;
wire read_pre_data;
wire read_source_update;
wire rsource_load;
wire [1:0] rsource_parallel_in;
wire rsource_serial_out;
wire rsource_shift_enable;
wire [2:0] rsource_state_par_ini;
wire rsource_update_done;
wire rublock_captnupdt;
wire rublock_clock;
wire rublock_reconfig;
wire rublock_reconfig_st;
wire rublock_regin;
wire rublock_regout;
wire rublock_regout_reg;
wire rublock_shiftnld;
wire select_shift_nloop;
wire shift_reg_clear;
wire shift_reg_load_enable;
wire shift_reg_serial_in;
wire shift_reg_serial_out;
wire shift_reg_shift_enable;
wire [5:0] start_bit_decoder_out;
wire [22:0] start_bit_decoder_param_select;
wire [1:0] w4w;
wire [5:0] w53w;
wire [4:0] w83w;
wire width_counter_all_done;
wire width_counter_clear;
wire width_counter_enable;
wire [4:0] width_counter_param_width;
wire width_counter_param_width_match;
wire [4:0] width_decoder_out;
wire [22:0] width_decoder_param_select;
wire write_data;
wire write_init;
wire write_init_counter;
wire write_load;
wire write_post_data;
wire write_pre_data;
wire write_source_update;
wire write_wait;
wire [2:0] wsource_state_par_ini;
wire wsource_update_done;
// synopsys translate_off
initial
check_busy_dffe[0:0] = 0;
// synopsys translate_on
// synopsys translate_off
initial
dffe1a0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe1a0 <= 1'b0;
else if (wire_dffe1a_ena[0:0] == 1'b1) dffe1a0 <= ((rsource_load & rsource_parallel_in[0]) | ((~ rsource_load) & dffe1a1[0:0]));
// synopsys translate_off
initial
dffe1a1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe1a1 <= 1'b0;
else if (wire_dffe1a_ena[1:1] == 1'b1) dffe1a1 <= (rsource_parallel_in[1] & rsource_load);
assign
wire_dffe1a_ena = {2{(rsource_load | rsource_shift_enable)}};
// synopsys translate_off
initial
dffe2a0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe2a0 <= 1'b0;
else if (wire_dffe2a_ena[0:0] == 1'b1) dffe2a0 <= ((rsource_load & rsource_state_par_ini[0]) | ((~ rsource_load) & dffe2a1[0:0]));
// synopsys translate_off
initial
dffe2a1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe2a1 <= 1'b0;
else if (wire_dffe2a_ena[1:1] == 1'b1) dffe2a1 <= ((rsource_load & rsource_state_par_ini[1]) | ((~ rsource_load) & dffe2a2[0:0]));
// synopsys translate_off
initial
dffe2a2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe2a2 <= 1'b0;
else if (wire_dffe2a_ena[2:2] == 1'b1) dffe2a2 <= (rsource_state_par_ini[2] & rsource_load);
assign
wire_dffe2a_ena = {3{(rsource_load | global_vcc)}};
// synopsys translate_off
initial
dffe3a0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe3a0 <= 1'b0;
else if (wire_dffe3a_ena[0:0] == 1'b1) dffe3a0 <= ((rsource_load & wsource_state_par_ini[0]) | ((~ rsource_load) & dffe3a1[0:0]));
// synopsys translate_off
initial
dffe3a1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe3a1 <= 1'b0;
else if (wire_dffe3a_ena[1:1] == 1'b1) dffe3a1 <= ((rsource_load & wsource_state_par_ini[1]) | ((~ rsource_load) & dffe3a2[0:0]));
// synopsys translate_off
initial
dffe3a2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe3a2 <= 1'b0;
else if (wire_dffe3a_ena[2:2] == 1'b1) dffe3a2 <= (wsource_state_par_ini[2] & rsource_load);
assign
wire_dffe3a_ena = {3{(rsource_load | global_vcc)}};
// synopsys translate_off
initial
dffe7a[0:0] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe7a[0:0] <= 1'b0;
else if (wire_dffe7a_ena[0:0] == 1'b1)
if (shift_reg_clear == 1'b1) dffe7a[0:0] <= 1'b0;
else dffe7a[0:0] <= ((shift_reg_load_enable & ((((param[2] & (~ param[1])) & (~ param[0])) & data_in[2]) | ((~ ((param[2] & (~ param[1])) & (~ param[0]))) & data_in[0]))) | ((~ shift_reg_load_enable) & dffe7a[1:1]));
// synopsys translate_off
initial
dffe7a[1:1] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe7a[1:1] <= 1'b0;
else if (wire_dffe7a_ena[1:1] == 1'b1)
if (shift_reg_clear == 1'b1) dffe7a[1:1] <= 1'b0;
else dffe7a[1:1] <= ((shift_reg_load_enable & ((((param[2] & (~ param[1])) & (~ param[0])) & data_in[3]) | ((~ ((param[2] & (~ param[1])) & (~ param[0]))) & data_in[1]))) | ((~ shift_reg_load_enable) & dffe7a[2:2]));
// synopsys translate_off
initial
dffe7a[2:2] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe7a[2:2] <= 1'b0;
else if (wire_dffe7a_ena[2:2] == 1'b1)
if (shift_reg_clear == 1'b1) dffe7a[2:2] <= 1'b0;
else dffe7a[2:2] <= ((shift_reg_load_enable & ((((param[2] & (~ param[1])) & (~ param[0])) & data_in[4]) | ((~ ((param[2] & (~ param[1])) & (~ param[0]))) & data_in[2]))) | ((~ shift_reg_load_enable) & dffe7a[3:3]));
// synopsys translate_off
initial
dffe7a[3:3] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe7a[3:3] <= 1'b0;
else if (wire_dffe7a_ena[3:3] == 1'b1)
if (shift_reg_clear == 1'b1) dffe7a[3:3] <= 1'b0;
else dffe7a[3:3] <= ((shift_reg_load_enable & ((((param[2] & (~ param[1])) & (~ param[0])) & data_in[5]) | ((~ ((param[2] & (~ param[1])) & (~ param[0]))) & data_in[3]))) | ((~ shift_reg_load_enable) & dffe7a[4:4]));
// synopsys translate_off
initial
dffe7a[4:4] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe7a[4:4] <= 1'b0;
else if (wire_dffe7a_ena[4:4] == 1'b1)
if (shift_reg_clear == 1'b1) dffe7a[4:4] <= 1'b0;
else dffe7a[4:4] <= ((shift_reg_load_enable & ((((param[2] & (~ param[1])) & (~ param[0])) & data_in[6]) | ((~ ((param[2] & (~ param[1])) & (~ param[0]))) & data_in[4]))) | ((~ shift_reg_load_enable) & dffe7a[5:5]));
// synopsys translate_off
initial
dffe7a[5:5] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe7a[5:5] <= 1'b0;
else if (wire_dffe7a_ena[5:5] == 1'b1)
if (shift_reg_clear == 1'b1) dffe7a[5:5] <= 1'b0;
else dffe7a[5:5] <= ((shift_reg_load_enable & ((((param[2] & (~ param[1])) & (~ param[0])) & data_in[7]) | ((~ ((param[2] & (~ param[1])) & (~ param[0]))) & data_in[5]))) | ((~ shift_reg_load_enable) & dffe7a[6:6]));
// synopsys translate_off
initial
dffe7a[6:6] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe7a[6:6] <= 1'b0;
else if (wire_dffe7a_ena[6:6] == 1'b1)
if (shift_reg_clear == 1'b1) dffe7a[6:6] <= 1'b0;
else dffe7a[6:6] <= ((shift_reg_load_enable & ((((param[2] & (~ param[1])) & (~ param[0])) & data_in[8]) | ((~ ((param[2] & (~ param[1])) & (~ param[0]))) & data_in[6]))) | ((~ shift_reg_load_enable) & dffe7a[7:7]));
// synopsys translate_off
initial
dffe7a[7:7] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe7a[7:7] <= 1'b0;
else if (wire_dffe7a_ena[7:7] == 1'b1)
if (shift_reg_clear == 1'b1) dffe7a[7:7] <= 1'b0;
else dffe7a[7:7] <= ((shift_reg_load_enable & ((((param[2] & (~ param[1])) & (~ param[0])) & data_in[9]) | ((~ ((param[2] & (~ param[1])) & (~ param[0]))) & data_in[7]))) | ((~ shift_reg_load_enable) & dffe7a[8:8]));
// synopsys translate_off
initial
dffe7a[8:8] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe7a[8:8] <= 1'b0;
else if (wire_dffe7a_ena[8:8] == 1'b1)
if (shift_reg_clear == 1'b1) dffe7a[8:8] <= 1'b0;
else dffe7a[8:8] <= ((shift_reg_load_enable & ((((param[2] & (~ param[1])) & (~ param[0])) & data_in[10]) | ((~ ((param[2] & (~ param[1])) & (~ param[0]))) & data_in[8]))) | ((~ shift_reg_load_enable) & dffe7a[9:9]));
// synopsys translate_off
initial
dffe7a[9:9] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe7a[9:9] <= 1'b0;
else if (wire_dffe7a_ena[9:9] == 1'b1)
if (shift_reg_clear == 1'b1) dffe7a[9:9] <= 1'b0;
else dffe7a[9:9] <= ((shift_reg_load_enable & ((((param[2] & (~ param[1])) & (~ param[0])) & data_in[11]) | ((~ ((param[2] & (~ param[1])) & (~ param[0]))) & data_in[9]))) | ((~ shift_reg_load_enable) & dffe7a[10:10]));
// synopsys translate_off
initial
dffe7a[10:10] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe7a[10:10] <= 1'b0;
else if (wire_dffe7a_ena[10:10] == 1'b1)
if (shift_reg_clear == 1'b1) dffe7a[10:10] <= 1'b0;
else dffe7a[10:10] <= ((shift_reg_load_enable & ((((param[2] & (~ param[1])) & (~ param[0])) & data_in[12]) | ((~ ((param[2] & (~ param[1])) & (~ param[0]))) & data_in[10]))) | ((~ shift_reg_load_enable) & dffe7a[11:11]));
// synopsys translate_off
initial
dffe7a[11:11] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe7a[11:11] <= 1'b0;
else if (wire_dffe7a_ena[11:11] == 1'b1)
if (shift_reg_clear == 1'b1) dffe7a[11:11] <= 1'b0;
else dffe7a[11:11] <= ((shift_reg_load_enable & ((((param[2] & (~ param[1])) & (~ param[0])) & data_in[13]) | ((~ ((param[2] & (~ param[1])) & (~ param[0]))) & data_in[11]))) | ((~ shift_reg_load_enable) & dffe7a[12:12]));
// synopsys translate_off
initial
dffe7a[12:12] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe7a[12:12] <= 1'b0;
else if (wire_dffe7a_ena[12:12] == 1'b1)
if (shift_reg_clear == 1'b1) dffe7a[12:12] <= 1'b0;
else dffe7a[12:12] <= ((shift_reg_load_enable & ((((param[2] & (~ param[1])) & (~ param[0])) & data_in[14]) | ((~ ((param[2] & (~ param[1])) & (~ param[0]))) & data_in[12]))) | ((~ shift_reg_load_enable) & dffe7a[13:13]));
// synopsys translate_off
initial
dffe7a[13:13] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe7a[13:13] <= 1'b0;
else if (wire_dffe7a_ena[13:13] == 1'b1)
if (shift_reg_clear == 1'b1) dffe7a[13:13] <= 1'b0;
else dffe7a[13:13] <= ((shift_reg_load_enable & ((((param[2] & (~ param[1])) & (~ param[0])) & data_in[15]) | ((~ ((param[2] & (~ param[1])) & (~ param[0]))) & data_in[13]))) | ((~ shift_reg_load_enable) & dffe7a[14:14]));
// synopsys translate_off
initial
dffe7a[14:14] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe7a[14:14] <= 1'b0;
else if (wire_dffe7a_ena[14:14] == 1'b1)
if (shift_reg_clear == 1'b1) dffe7a[14:14] <= 1'b0;
else dffe7a[14:14] <= ((shift_reg_load_enable & ((((param[2] & (~ param[1])) & (~ param[0])) & data_in[16]) | ((~ ((param[2] & (~ param[1])) & (~ param[0]))) & data_in[14]))) | ((~ shift_reg_load_enable) & dffe7a[15:15]));
// synopsys translate_off
initial
dffe7a[15:15] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe7a[15:15] <= 1'b0;
else if (wire_dffe7a_ena[15:15] == 1'b1)
if (shift_reg_clear == 1'b1) dffe7a[15:15] <= 1'b0;
else dffe7a[15:15] <= ((shift_reg_load_enable & ((((param[2] & (~ param[1])) & (~ param[0])) & data_in[17]) | ((~ ((param[2] & (~ param[1])) & (~ param[0]))) & data_in[15]))) | ((~ shift_reg_load_enable) & dffe7a[16:16]));
// synopsys translate_off
initial
dffe7a[16:16] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe7a[16:16] <= 1'b0;
else if (wire_dffe7a_ena[16:16] == 1'b1)
if (shift_reg_clear == 1'b1) dffe7a[16:16] <= 1'b0;
else dffe7a[16:16] <= ((shift_reg_load_enable & ((((param[2] & (~ param[1])) & (~ param[0])) & data_in[18]) | ((~ ((param[2] & (~ param[1])) & (~ param[0]))) & data_in[16]))) | ((~ shift_reg_load_enable) & dffe7a[17:17]));
// synopsys translate_off
initial
dffe7a[17:17] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe7a[17:17] <= 1'b0;
else if (wire_dffe7a_ena[17:17] == 1'b1)
if (shift_reg_clear == 1'b1) dffe7a[17:17] <= 1'b0;
else dffe7a[17:17] <= ((shift_reg_load_enable & ((((param[2] & (~ param[1])) & (~ param[0])) & data_in[19]) | ((~ ((param[2] & (~ param[1])) & (~ param[0]))) & data_in[17]))) | ((~ shift_reg_load_enable) & dffe7a[18:18]));
// synopsys translate_off
initial
dffe7a[18:18] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe7a[18:18] <= 1'b0;
else if (wire_dffe7a_ena[18:18] == 1'b1)
if (shift_reg_clear == 1'b1) dffe7a[18:18] <= 1'b0;
else dffe7a[18:18] <= ((shift_reg_load_enable & ((((param[2] & (~ param[1])) & (~ param[0])) & data_in[20]) | ((~ ((param[2] & (~ param[1])) & (~ param[0]))) & data_in[18]))) | ((~ shift_reg_load_enable) & dffe7a[19:19]));
// synopsys translate_off
initial
dffe7a[19:19] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe7a[19:19] <= 1'b0;
else if (wire_dffe7a_ena[19:19] == 1'b1)
if (shift_reg_clear == 1'b1) dffe7a[19:19] <= 1'b0;
else dffe7a[19:19] <= ((shift_reg_load_enable & ((((param[2] & (~ param[1])) & (~ param[0])) & data_in[21]) | ((~ ((param[2] & (~ param[1])) & (~ param[0]))) & data_in[19]))) | ((~ shift_reg_load_enable) & dffe7a[20:20]));
// synopsys translate_off
initial
dffe7a[20:20] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe7a[20:20] <= 1'b0;
else if (wire_dffe7a_ena[20:20] == 1'b1)
if (shift_reg_clear == 1'b1) dffe7a[20:20] <= 1'b0;
else dffe7a[20:20] <= ((shift_reg_load_enable & ((((param[2] & (~ param[1])) & (~ param[0])) & data_in[22]) | ((~ ((param[2] & (~ param[1])) & (~ param[0]))) & data_in[20]))) | ((~ shift_reg_load_enable) & dffe7a[21:21]));
// synopsys translate_off
initial
dffe7a[21:21] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe7a[21:21] <= 1'b0;
else if (wire_dffe7a_ena[21:21] == 1'b1)
if (shift_reg_clear == 1'b1) dffe7a[21:21] <= 1'b0;
else dffe7a[21:21] <= ((shift_reg_load_enable & ((((param[2] & (~ param[1])) & (~ param[0])) & data_in[23]) | ((~ ((param[2] & (~ param[1])) & (~ param[0]))) & data_in[21]))) | ((~ shift_reg_load_enable) & dffe7a[22:22]));
// synopsys translate_off
initial
dffe7a[22:22] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe7a[22:22] <= 1'b0;
else if (wire_dffe7a_ena[22:22] == 1'b1)
if (shift_reg_clear == 1'b1) dffe7a[22:22] <= 1'b0;
else dffe7a[22:22] <= ((~ shift_reg_load_enable) & dffe7a[23:23]);
// synopsys translate_off
initial
dffe7a[23:23] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe7a[23:23] <= 1'b0;
else if (wire_dffe7a_ena[23:23] == 1'b1)
if (shift_reg_clear == 1'b1) dffe7a[23:23] <= 1'b0;
else dffe7a[23:23] <= ((~ shift_reg_load_enable) & dffe7a[24:24]);
// synopsys translate_off
initial
dffe7a[24:24] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe7a[24:24] <= 1'b0;
else if (wire_dffe7a_ena[24:24] == 1'b1)
if (shift_reg_clear == 1'b1) dffe7a[24:24] <= 1'b0;
else dffe7a[24:24] <= ((~ shift_reg_load_enable) & dffe7a[25:25]);
// synopsys translate_off
initial
dffe7a[25:25] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe7a[25:25] <= 1'b0;
else if (wire_dffe7a_ena[25:25] == 1'b1)
if (shift_reg_clear == 1'b1) dffe7a[25:25] <= 1'b0;
else dffe7a[25:25] <= ((~ shift_reg_load_enable) & dffe7a[26:26]);
// synopsys translate_off
initial
dffe7a[26:26] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe7a[26:26] <= 1'b0;
else if (wire_dffe7a_ena[26:26] == 1'b1)
if (shift_reg_clear == 1'b1) dffe7a[26:26] <= 1'b0;
else dffe7a[26:26] <= ((~ shift_reg_load_enable) & dffe7a[27:27]);
// synopsys translate_off
initial
dffe7a[27:27] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe7a[27:27] <= 1'b0;
else if (wire_dffe7a_ena[27:27] == 1'b1)
if (shift_reg_clear == 1'b1) dffe7a[27:27] <= 1'b0;
else dffe7a[27:27] <= ((~ shift_reg_load_enable) & dffe7a[28:28]);
// synopsys translate_off
initial
dffe7a[28:28] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe7a[28:28] <= 1'b0;
else if (wire_dffe7a_ena[28:28] == 1'b1)
if (shift_reg_clear == 1'b1) dffe7a[28:28] <= 1'b0;
else dffe7a[28:28] <= ((~ shift_reg_load_enable) & shift_reg_serial_in);
assign
wire_dffe7a_ena = {29{((shift_reg_load_enable | shift_reg_shift_enable) | shift_reg_clear)}};
// synopsys translate_off
initial
dffe8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe8 <= 1'b0;
else dffe8 <= rublock_regout;
// synopsys translate_off
initial
dffe9a[0:0] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe9a[0:0] <= 1'b0;
else if (wire_dffe9a_ena[0:0] == 1'b1) dffe9a[0:0] <= combine_port[0:0];
// synopsys translate_off
initial
dffe9a[1:1] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe9a[1:1] <= 1'b0;
else if (wire_dffe9a_ena[1:1] == 1'b1) dffe9a[1:1] <= combine_port[1:1];
// synopsys translate_off
initial
dffe9a[2:2] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe9a[2:2] <= 1'b0;
else if (wire_dffe9a_ena[2:2] == 1'b1) dffe9a[2:2] <= combine_port[2:2];
// synopsys translate_off
initial
dffe9a[3:3] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe9a[3:3] <= 1'b0;
else if (wire_dffe9a_ena[3:3] == 1'b1) dffe9a[3:3] <= combine_port[3:3];
// synopsys translate_off
initial
dffe9a[4:4] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe9a[4:4] <= 1'b0;
else if (wire_dffe9a_ena[4:4] == 1'b1) dffe9a[4:4] <= combine_port[4:4];
// synopsys translate_off
initial
dffe9a[5:5] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe9a[5:5] <= 1'b0;
else if (wire_dffe9a_ena[5:5] == 1'b1) dffe9a[5:5] <= combine_port[5:5];
// synopsys translate_off
initial
dffe9a[6:6] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) dffe9a[6:6] <= 1'b0;
else if (wire_dffe9a_ena[6:6] == 1'b1) dffe9a[6:6] <= combine_port[6:6];
assign
wire_dffe9a_ena = {7{(idle & (write_param | read_param))}};
// synopsys translate_off
initial
idle_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) idle_state <= {1{1'b1}};
else idle_state <= ((((((idle & (~ read_param)) & (~ write_param)) | write_wait) | (read_data & width_counter_all_done)) | (read_post & width_counter_all_done)) | power_up);
// synopsys translate_off
initial
idle_write_wait = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) idle_write_wait <= 1'b0;
else idle_write_wait <= (((((((idle & (~ read_param)) & (~ write_param)) | write_wait) | (read_data & width_counter_all_done)) | (read_post & width_counter_all_done)) | power_up) & write_load);
// synopsys translate_off
initial
read_address_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) read_address_state <= 1'b0;
else if (wire_read_address_state_ena == 1'b1) read_address_state <= (((read_param | write_param) & ((param[2] & (~ param[1])) & (~ param[0]))) & (~ (~ idle)));
assign
wire_read_address_state_ena = (read_param | write_param);
// synopsys translate_off
initial
read_data_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) read_data_state <= 1'b0;
else read_data_state <= (((read_init_counter & bit_counter_param_start_match) | (read_pre_data & bit_counter_param_start_match)) | ((read_data & (~ width_counter_param_width_match)) & (~ width_counter_all_done)));
// synopsys translate_off
initial
read_init_counter_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) read_init_counter_state <= 1'b0;
else read_init_counter_state <= rsource_update_done;
// synopsys translate_off
initial
read_init_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) read_init_state <= 1'b0;
else read_init_state <= (idle & read_param);
// synopsys translate_off
initial
read_post_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) read_post_state <= 1'b0;
else read_post_state <= (((read_data & width_counter_param_width_match) & (~ width_counter_all_done)) | (read_post & (~ width_counter_all_done)));
// synopsys translate_off
initial
read_pre_data_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) read_pre_data_state <= 1'b0;
else read_pre_data_state <= ((read_init_counter & (~ bit_counter_param_start_match)) | (read_pre_data & (~ bit_counter_param_start_match)));
// synopsys translate_off
initial
read_source_update_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) read_source_update_state <= 1'b0;
else read_source_update_state <= ((read_init | read_source_update) & (~ rsource_update_done));
// synopsys translate_off
initial
write_data_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) write_data_state <= 1'b0;
else write_data_state <= (((write_init_counter & bit_counter_param_start_match) | (write_pre_data & bit_counter_param_start_match)) | ((write_data & (~ width_counter_param_width_match)) & (~ bit_counter_all_done)));
// synopsys translate_off
initial
write_init_counter_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) write_init_counter_state <= 1'b0;
else write_init_counter_state <= wsource_update_done;
// synopsys translate_off
initial
write_init_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) write_init_state <= 1'b0;
else write_init_state <= (idle & write_param);
// synopsys translate_off
initial
write_load_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) write_load_state <= 1'b0;
else write_load_state <= ((write_data & bit_counter_all_done) | (write_post_data & bit_counter_all_done));
// synopsys translate_off
initial
write_post_data_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) write_post_data_state <= 1'b0;
else write_post_data_state <= (((write_data & width_counter_param_width_match) & (~ bit_counter_all_done)) | (write_post_data & (~ bit_counter_all_done)));
// synopsys translate_off
initial
write_pre_data_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) write_pre_data_state <= 1'b0;
else write_pre_data_state <= ((write_init_counter & (~ bit_counter_param_start_match)) | (write_pre_data & (~ bit_counter_param_start_match)));
// synopsys translate_off
initial
write_source_update_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) write_source_update_state <= 1'b0;
else write_source_update_state <= ((write_init | write_source_update) & (~ wsource_update_done));
// synopsys translate_off
initial
write_wait_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) write_wait_state <= 1'b0;
else write_wait_state <= write_load;
lpm_counter cntr5
(
.aclr(reset),
.clock(clock),
.cnt_en(bit_counter_enable),
.cout(),
.eq(),
.q(wire_cntr5_q),
.sclr(bit_counter_clear)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aload(1'b0),
.aset(1'b0),
.cin(1'b1),
.clk_en(1'b1),
.data({6{1'b0}}),
.sload(1'b0),
.sset(1'b0),
.updown(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
cntr5.lpm_direction = "UP",
cntr5.lpm_port_updown = "PORT_UNUSED",
cntr5.lpm_width = 6,
cntr5.lpm_type = "lpm_counter";
lpm_counter cntr6
(
.aclr(reset),
.clock(clock),
.cnt_en(width_counter_enable),
.cout(),
.eq(),
.q(wire_cntr6_q),
.sclr(width_counter_clear)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aload(1'b0),
.aset(1'b0),
.cin(1'b1),
.clk_en(1'b1),
.data({5{1'b0}}),
.sload(1'b0),
.sset(1'b0),
.updown(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
cntr6.lpm_direction = "UP",
cntr6.lpm_port_updown = "PORT_UNUSED",
cntr6.lpm_width = 5,
cntr6.lpm_type = "lpm_counter";
cycloneive_rublock sd4
(
.captnupdt(rublock_captnupdt),
.clk(rublock_clock),
.rconfig(rublock_reconfig),
.regin(rublock_regin),
.regout(wire_sd4_regout),
.rsttimer(reset_timer),
.shiftnld(rublock_shiftnld));
assign
bit_counter_all_done = (((((wire_cntr5_q[0] & (~ wire_cntr5_q[1])) & (~ wire_cntr5_q[2])) & wire_cntr5_q[3]) & (~ wire_cntr5_q[4])) & wire_cntr5_q[5]),
bit_counter_clear = (rsource_update_done | wsource_update_done),
bit_counter_enable = (((((((((rsource_update_done | wsource_update_done) | read_init_counter) | write_init_counter) | read_pre_data) | write_pre_data) | read_data) | write_data) | read_post) | write_post_data),
bit_counter_param_start = start_bit_decoder_out,
bit_counter_param_start_match = ((((((~ w53w[0]) & (~ w53w[1])) & (~ w53w[2])) & (~ w53w[3])) & (~ w53w[4])) & (~ w53w[5])),
busy = (~ idle),
combine_port = {read_param, write_param, read_source, param},
data_out = {((read_address & dffe7a[26]) | ((~ read_address) & dffe7a[28])), ((read_address & dffe7a[25]) | ((~ read_address) & dffe7a[27])), ((read_address & dffe7a[24]) | ((~ read_address) & dffe7a[26])), ((read_address & dffe7a[23]) | ((~ read_address) & dffe7a[25])), ((read_address & dffe7a[22]) | ((~ read_address) & dffe7a[24])), ((read_address & dffe7a[21]) | ((~ read_address) & dffe7a[23])), ((read_address & dffe7a[20]) | ((~ read_address) & dffe7a[22])), ((read_address & dffe7a[19]) | ((~ read_address) & dffe7a[21])), ((read_address & dffe7a[18]) | ((~ read_address) & dffe7a[20])), ((read_address & dffe7a[17]) | ((~ read_address) & dffe7a[19])), ((read_address & dffe7a[16]) | ((~ read_address) & dffe7a[18])), ((read_address & dffe7a[15]) | ((~ read_address) & dffe7a[17])), ((read_address & dffe7a[14]) | ((~ read_address) & dffe7a[16])), ((read_address & dffe7a[13]) | ((~ read_address) & dffe7a[15])), ((read_address & dffe7a[12]) | ((~ read_address) & dffe7a[14])), ((read_address & dffe7a[11]) | ((~ read_address) & dffe7a[13])), ((read_address & dffe7a[10]) | ((~ read_address) & dffe7a[12])), ((read_address & dffe7a[9]) | ((~ read_address) & dffe7a[11])), ((read_address & dffe7a[8]) | ((~ read_address) & dffe7a[10])), ((read_address & dffe7a[7]) | ((~ read_address) & dffe7a[9])), ((read_address & dffe7a[6]) | ((~ read_address) & dffe7a[8])), ((read_address & dffe7a[5]) | ((~ read_address) & dffe7a[7])), ((read_address & dffe7a[4]) | ((~ read_address) & dffe7a[6])), ((read_address & dffe7a[3]) | ((~ read_address) & dffe7a[5])), ((read_address & dffe7a[2]) | ((~ read_address) & dffe7a[4])), ((read_address & dffe7a[1]) | ((~ read_address) & dffe7a[3])), ((read_address & dffe7a[0]) | ((~ read_address) & dffe7a[2])), ((~ read_address) & dffe7a[1]), ((~ read_address) & dffe7a[0])},
global_gnd = 1'b0,
global_vcc = 1'b1,
idle = idle_state,
param_decoder_param_latch = dffe9a,
param_decoder_select = {(((((((~ param_decoder_param_latch[0]) & param_decoder_param_latch[1]) & param_decoder_param_latch[2]) & param_decoder_param_latch[3]) & param_decoder_param_latch[4]) & (~ param_decoder_param_latch[5])) & param_decoder_param_latch[6]), (((((((~ param_decoder_param_latch[0]) & (~ param_decoder_param_latch[1])) & param_decoder_param_latch[2]) & param_decoder_param_latch[3]) & param_decoder_param_latch[4]) & (~ param_decoder_param_latch[5])) & param_decoder_param_latch[6]), ((((((param_decoder_param_latch[0] & param_decoder_param_latch[1]) & (~ param_decoder_param_latch[2])) & param_decoder_param_latch[3]) & param_decoder_param_latch[4]) & (~ param_decoder_param_latch[5])) & param_decoder_param_latch[6]), (((((((~ param_decoder_param_latch[0]) & param_decoder_param_latch[1]) & (~ param_decoder_param_latch[2])) & param_decoder_param_latch[3]) & param_decoder_param_latch[4]) & (~ param_decoder_param_latch[5])) & param_decoder_param_latch[6]), ((((((param_decoder_param_latch[0] & (~ param_decoder_param_latch[1])) & (~ param_decoder_param_latch[2])) & param_decoder_param_latch[3]) & param_decoder_param_latch[4]) & (~ param_decoder_param_latch[5])) & param_decoder_param_latch[6]), (((((((~ param_decoder_param_latch[0]) & param_decoder_param_latch[1]) & param_decoder_param_latch[2]) & (~ param_decoder_param_latch[3])) & (~ param_decoder_param_latch[4])) & param_decoder_param_latch[5]) & (~ param_decoder_param_latch[6])), (((((((~ param_decoder_param_latch[0]) & (~ param_decoder_param_latch[1])) & param_decoder_param_latch[2]) & (~ param_decoder_param_latch[3])) & (~ param_decoder_param_latch[4])) & param_decoder_param_latch[5]) & (~ param_decoder_param_latch[6])), ((((((param_decoder_param_latch[0] & param_decoder_param_latch[1]) & (~ param_decoder_param_latch[2])) & (~ param_decoder_param_latch[3])) & (~ param_decoder_param_latch[4])) & param_decoder_param_latch[5]) & (~ param_decoder_param_latch[6])), (((((((~ param_decoder_param_latch[0]) & param_decoder_param_latch[1]) & (~ param_decoder_param_latch[2]
)) & (~ param_decoder_param_latch[3])) & (~ param_decoder_param_latch[4])) & param_decoder_param_latch[5]) & (~ param_decoder_param_latch[6])), ((((((param_decoder_param_latch[0] & (~ param_decoder_param_latch[1])) & (~ param_decoder_param_latch[2])) & (~ param_decoder_param_latch[3])) & (~ param_decoder_param_latch[4])) & param_decoder_param_latch[5]) & (~ param_decoder_param_latch[6])), ((((((param_decoder_param_latch[0] & param_decoder_param_latch[1]) & param_decoder_param_latch[2]) & (~ param_decoder_param_latch[3])) & param_decoder_param_latch[4]) & (~ param_decoder_param_latch[5])) & param_decoder_param_latch[6]), (((((((~ param_decoder_param_latch[0]) & (~ param_decoder_param_latch[1])) & param_decoder_param_latch[2]) & (~ param_decoder_param_latch[3])) & param_decoder_param_latch[4]) & (~ param_decoder_param_latch[5])) & param_decoder_param_latch[6]), (((((((~ param_decoder_param_latch[0]) & (~ param_decoder_param_latch[1])) & (~ param_decoder_param_latch[2])) & (~ param_decoder_param_latch[3])) & param_decoder_param_latch[4]) & (~ param_decoder_param_latch[5])) & param_decoder_param_latch[6]), ((((((param_decoder_param_latch[0] & param_decoder_param_latch[1]) & param_decoder_param_latch[2]) & param_decoder_param_latch[3]) & (~ param_decoder_param_latch[4])) & (~ param_decoder_param_latch[5])) & param_decoder_param_latch[6]), (((((((~ param_decoder_param_latch[0]) & (~ param_decoder_param_latch[1])) & param_decoder_param_latch[2]) & param_decoder_param_latch[3]) & (~ param_decoder_param_latch[4])) & (~ param_decoder_param_latch[5])) & param_decoder_param_latch[6]), (((((((~ param_decoder_param_latch[0]) & (~ param_decoder_param_latch[1])) & (~ param_decoder_param_latch[2])) & param_decoder_param_latch[3]) & (~ param_decoder_param_latch[4])) & (~ param_decoder_param_latch[5])) & param_decoder_param_latch[6]), (((((((~ param_decoder_param_latch[0]) & (~ param_decoder_param_latch[1])) & param_decoder_param_latch[2]) & (~ param_decoder_param_latch[3])) & param_decoder_param_latch[4]) & (~ param_decoder_param_latch[5]
)) & param_decoder_param_latch[6]), (((((((~ param_decoder_param_latch[0]) & (~ param_decoder_param_latch[1])) & (~ param_decoder_param_latch[2])) & (~ param_decoder_param_latch[3])) & param_decoder_param_latch[4]) & (~ param_decoder_param_latch[5])) & param_decoder_param_latch[6]), ((((((param_decoder_param_latch[0] & param_decoder_param_latch[1]) & (~ param_decoder_param_latch[2])) & param_decoder_param_latch[3]) & (~ param_decoder_param_latch[4])) & (~ param_decoder_param_latch[5])) & param_decoder_param_latch[6]), (((((((~ param_decoder_param_latch[0]) & param_decoder_param_latch[1]) & (~ param_decoder_param_latch[2])) & param_decoder_param_latch[3]) & (~ param_decoder_param_latch[4])) & (~ param_decoder_param_latch[5])) & param_decoder_param_latch[6]), (((((((~ param_decoder_param_latch[0]) & (~ param_decoder_param_latch[1])) & (~ param_decoder_param_latch[2])) & param_decoder_param_latch[3]) & (~ param_decoder_param_latch[4])) & (~ param_decoder_param_latch[5])) & param_decoder_param_latch[6]), (((((((~ param_decoder_param_latch[0]) & (~ param_decoder_param_latch[1])) & param_decoder_param_latch[2]) & (~ param_decoder_param_latch[3])) & (~ param_decoder_param_latch[4])) & (~ param_decoder_param_latch[5])) & param_decoder_param_latch[6]), (((((((~ param_decoder_param_latch[0]) & (~ param_decoder_param_latch[1])) & (~ param_decoder_param_latch[2])) & (~ param_decoder_param_latch[3])) & (~ param_decoder_param_latch[4])) & (~ param_decoder_param_latch[5])) & param_decoder_param_latch[6])},
power_up = (((((((((((((((~ idle) & (~ read_init)) & (~ read_source_update)) & (~ read_init_counter)) & (~ read_pre_data)) & (~ read_data)) & (~ read_post)) & (~ write_init)) & (~ write_init_counter)) & (~ write_source_update)) & (~ write_pre_data)) & (~ write_data)) & (~ write_post_data)) & (~ write_load)) & (~ write_wait)),
read_address = read_address_state,
read_data = read_data_state,
read_init = read_init_state,
read_init_counter = read_init_counter_state,
read_post = read_post_state,
read_pre_data = read_pre_data_state,
read_source_update = read_source_update_state,
rsource_load = (idle & (write_param | read_param)),
rsource_parallel_in = {((w4w[1] & read_param) | write_param), ((w4w[0] & read_param) | write_param)},
rsource_serial_out = dffe1a0[0:0],
rsource_shift_enable = (read_source_update | write_source_update),
rsource_state_par_ini = {read_param, {2{global_gnd}}},
rsource_update_done = dffe2a0[0:0],
rublock_captnupdt = (~ write_load),
rublock_clock = (~ (clock | idle_write_wait)),
rublock_reconfig = rublock_reconfig_st,
rublock_reconfig_st = (idle & reconfig),
rublock_regin = (((((rublock_regout_reg & (~ select_shift_nloop)) & (~ read_source_update)) & (~ write_source_update)) | (((shift_reg_serial_out & select_shift_nloop) & (~ read_source_update)) & (~ write_source_update))) | ((read_source_update | write_source_update) & rsource_serial_out)),
rublock_regout = wire_sd4_regout,
rublock_regout_reg = dffe8,
rublock_shiftnld = (((((((read_pre_data | write_pre_data) | read_data) | write_data) | read_post) | write_post_data) | read_source_update) | write_source_update),
select_shift_nloop = ((read_data & (~ width_counter_param_width_match)) | (write_data & (~ width_counter_param_width_match))),
shift_reg_clear = rsource_update_done,
shift_reg_load_enable = (idle & write_param),
shift_reg_serial_in = (rublock_regout_reg & select_shift_nloop),
shift_reg_serial_out = dffe7a[0:0],
shift_reg_shift_enable = (((read_data | write_data) | read_post) | write_post_data),
start_bit_decoder_out = (((((((((((((((((((((({1'b0, {4{start_bit_decoder_param_select[0]}}, 1'b0} | {6{1'b0}}) | {1'b0, {4{start_bit_decoder_param_select[2]}}, 1'b0}) | {6{1'b0}}) | {1'b0, {3{start_bit_decoder_param_select[4]}}, 1'b0, start_bit_decoder_param_select[4]}) | {1'b0, {4{start_bit_decoder_param_select[5]}}, 1'b0}) | {6{1'b0}}) | {1'b0, {2{start_bit_decoder_param_select[7]}}, {3{1'b0}}}) | {6{1'b0}}) | {1'b0, {2{start_bit_decoder_param_select[9]}}, 1'b0, start_bit_decoder_param_select[9], 1'b0}) | {1'b0, {2{start_bit_decoder_param_select[10]}}, {3{1'b0}}}) | {6{1'b0}}) | {1'b0, {2{start_bit_decoder_param_select[12]}}, 1'b0, start_bit_decoder_param_select[12], 1'b0}) | {start_bit_decoder_param_select[13], {2{1'b0}}, start_bit_decoder_param_select[13], 1'b0, start_bit_decoder_param_select[13]}) | {6{1'b0}}) | {start_bit_decoder_param_select[15], {3{1'b0}}, {2{start_bit_decoder_param_select[15]}}}) | {{2{1'b0}}, {2{start_bit_decoder_param_select[16]}}, {2{1'b0}}}) | {start_bit_decoder_param_select[17], {2{1'b0}}, start_bit_decoder_param_select[17], {2{1'b0}}}) | {start_bit_decoder_param_select[18], {2{1'b0}}, start_bit_decoder_param_select[18], 1'b0, start_bit_decoder_param_select[18]}) | {6{1'b0}}) | {start_bit_decoder_param_select[20], {3{1'b0}}, {2{start_bit_decoder_param_select[20]}}}) | {{2{1'b0}}, {2{start_bit_decoder_param_select[21]}}, {2{1'b0}}}) | {start_bit_decoder_param_select[22], {2{1'b0}}, start_bit_decoder_param_select[22], {2{1'b0}}}),
start_bit_decoder_param_select = param_decoder_select,
w4w = read_source,
w53w = (wire_cntr5_q ^ bit_counter_param_start),
w83w = (wire_cntr6_q ^ width_counter_param_width),
width_counter_all_done = (((((~ wire_cntr6_q[0]) & (~ wire_cntr6_q[1])) & wire_cntr6_q[2]) & wire_cntr6_q[3]) & wire_cntr6_q[4]),
width_counter_clear = (rsource_update_done | wsource_update_done),
width_counter_enable = ((read_data | write_data) | read_post),
width_counter_param_width = width_decoder_out,
width_counter_param_width_match = (((((~ w83w[0]) & (~ w83w[1])) & (~ w83w[2])) & (~ w83w[3])) & (~ w83w[4])),
width_decoder_out = (((((((((((((((((((((({{3{1'b0}}, width_decoder_param_select[0], 1'b0} | {{2{width_decoder_param_select[1]}}, {3{1'b0}}}) | {{3{1'b0}}, width_decoder_param_select[2], 1'b0}) | {{3{width_decoder_param_select[3]}}, 1'b0, width_decoder_param_select[3]}) | {{4{1'b0}}, width_decoder_param_select[4]}) | {{3{1'b0}}, width_decoder_param_select[5], 1'b0}) | {{2{width_decoder_param_select[6]}}, {3{1'b0}}}) | {{3{1'b0}}, width_decoder_param_select[7], 1'b0}) | {{2{width_decoder_param_select[8]}}, {3{1'b0}}}) | {{2{1'b0}}, width_decoder_param_select[9], 1'b0, width_decoder_param_select[9]}) | {{3{1'b0}}, width_decoder_param_select[10], 1'b0}) | {{2{width_decoder_param_select[11]}}, {3{1'b0}}}) | {{2{1'b0}}, width_decoder_param_select[12], 1'b0, width_decoder_param_select[12]}) | {{4{1'b0}}, width_decoder_param_select[13]}) | {1'b0, {2{width_decoder_param_select[14]}}, {2{1'b0}}}) | {{4{1'b0}}, width_decoder_param_select[15]}) | {width_decoder_param_select[16], 1'b0, {2{width_decoder_param_select[16]}}, 1'b0}) | {{4{1'b0}}, width_decoder_param_select[17]}) | {{4{1'b0}}, width_decoder_param_select[18]}) | {1'b0, {2{width_decoder_param_select[19]}}, {2{1'b0}}}) | {{4{1'b0}}, width_decoder_param_select[20]}) | {width_decoder_param_select[21], 1'b0, {2{width_decoder_param_select[21]}}, 1'b0}) | {{4{1'b0}}, width_decoder_param_select[22]}),
width_decoder_param_select = param_decoder_select,
write_data = write_data_state,
write_init = write_init_state,
write_init_counter = write_init_counter_state,
write_load = write_load_state,
write_post_data = write_post_data_state,
write_pre_data = write_pre_data_state,
write_source_update = write_source_update_state,
write_wait = write_wait_state,
wsource_state_par_ini = {write_param, {2{global_gnd}}},
wsource_update_done = dffe3a0[0:0];
endmodule //altera_remote_update_core
//VALID FILE
|
/*
Copyright (c) 2019 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* AXI4-Stream FIFO with width converter
*/
module axis_fifo_adapter #
(
// FIFO depth in words
// KEEP_WIDTH words per cycle if KEEP_ENABLE set
// Rounded up to nearest power of 2 cycles
parameter DEPTH = 4096,
// Width of input AXI stream interface in bits
parameter S_DATA_WIDTH = 8,
// Propagate tkeep signal on input interface
// If disabled, tkeep assumed to be 1'b1
parameter S_KEEP_ENABLE = (S_DATA_WIDTH>8),
// tkeep signal width (words per cycle) on input interface
parameter S_KEEP_WIDTH = (S_DATA_WIDTH/8),
// Width of output AXI stream interface in bits
parameter M_DATA_WIDTH = 8,
// Propagate tkeep signal on output interface
// If disabled, tkeep assumed to be 1'b1
parameter M_KEEP_ENABLE = (M_DATA_WIDTH>8),
// tkeep signal width (words per cycle) on output interface
parameter M_KEEP_WIDTH = (M_DATA_WIDTH/8),
// Propagate tid signal
parameter ID_ENABLE = 0,
// tid signal width
parameter ID_WIDTH = 8,
// Propagate tdest signal
parameter DEST_ENABLE = 0,
// tdest signal width
parameter DEST_WIDTH = 8,
// Propagate tuser signal
parameter USER_ENABLE = 1,
// tuser signal width
parameter USER_WIDTH = 1,
// number of output pipeline registers
parameter PIPELINE_OUTPUT = 2,
// Frame FIFO mode - operate on frames instead of cycles
// When set, m_axis_tvalid will not be deasserted within a frame
// Requires LAST_ENABLE set
parameter FRAME_FIFO = 0,
// tuser value for bad frame marker
parameter USER_BAD_FRAME_VALUE = 1'b1,
// tuser mask for bad frame marker
parameter USER_BAD_FRAME_MASK = 1'b1,
// Drop frames larger than FIFO
// Requires FRAME_FIFO set
parameter DROP_OVERSIZE_FRAME = FRAME_FIFO,
// Drop frames marked bad
// Requires FRAME_FIFO and DROP_OVERSIZE_FRAME set
parameter DROP_BAD_FRAME = 0,
// Drop incoming frames when full
// When set, s_axis_tready is always asserted
// Requires FRAME_FIFO and DROP_OVERSIZE_FRAME set
parameter DROP_WHEN_FULL = 0
)
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [S_DATA_WIDTH-1:0] s_axis_tdata,
input wire [S_KEEP_WIDTH-1:0] s_axis_tkeep,
input wire s_axis_tvalid,
output wire s_axis_tready,
input wire s_axis_tlast,
input wire [ID_WIDTH-1:0] s_axis_tid,
input wire [DEST_WIDTH-1:0] s_axis_tdest,
input wire [USER_WIDTH-1:0] s_axis_tuser,
/*
* AXI output
*/
output wire [M_DATA_WIDTH-1:0] m_axis_tdata,
output wire [M_KEEP_WIDTH-1:0] m_axis_tkeep,
output wire m_axis_tvalid,
input wire m_axis_tready,
output wire m_axis_tlast,
output wire [ID_WIDTH-1:0] m_axis_tid,
output wire [DEST_WIDTH-1:0] m_axis_tdest,
output wire [USER_WIDTH-1:0] m_axis_tuser,
/*
* Status
*/
output wire status_overflow,
output wire status_bad_frame,
output wire status_good_frame
);
// force keep width to 1 when disabled
parameter S_KEEP_WIDTH_INT = S_KEEP_ENABLE ? S_KEEP_WIDTH : 1;
parameter M_KEEP_WIDTH_INT = M_KEEP_ENABLE ? M_KEEP_WIDTH : 1;
// bus word sizes (must be identical)
parameter S_DATA_WORD_SIZE = S_DATA_WIDTH / S_KEEP_WIDTH_INT;
parameter M_DATA_WORD_SIZE = M_DATA_WIDTH / M_KEEP_WIDTH_INT;
// output bus is wider
parameter EXPAND_BUS = M_KEEP_WIDTH_INT > S_KEEP_WIDTH_INT;
// total data and keep widths
parameter DATA_WIDTH = EXPAND_BUS ? M_DATA_WIDTH : S_DATA_WIDTH;
parameter KEEP_WIDTH = EXPAND_BUS ? M_KEEP_WIDTH_INT : S_KEEP_WIDTH_INT;
// bus width assertions
initial begin
if (S_DATA_WORD_SIZE * S_KEEP_WIDTH_INT != S_DATA_WIDTH) begin
$error("Error: input data width not evenly divisble (instance %m)");
$finish;
end
if (M_DATA_WORD_SIZE * M_KEEP_WIDTH_INT != M_DATA_WIDTH) begin
$error("Error: output data width not evenly divisble (instance %m)");
$finish;
end
if (S_DATA_WORD_SIZE != M_DATA_WORD_SIZE) begin
$error("Error: word size mismatch (instance %m)");
$finish;
end
end
wire [DATA_WIDTH-1:0] pre_fifo_axis_tdata;
wire [KEEP_WIDTH-1:0] pre_fifo_axis_tkeep;
wire pre_fifo_axis_tvalid;
wire pre_fifo_axis_tready;
wire pre_fifo_axis_tlast;
wire [ID_WIDTH-1:0] pre_fifo_axis_tid;
wire [DEST_WIDTH-1:0] pre_fifo_axis_tdest;
wire [USER_WIDTH-1:0] pre_fifo_axis_tuser;
wire [DATA_WIDTH-1:0] post_fifo_axis_tdata;
wire [KEEP_WIDTH-1:0] post_fifo_axis_tkeep;
wire post_fifo_axis_tvalid;
wire post_fifo_axis_tready;
wire post_fifo_axis_tlast;
wire [ID_WIDTH-1:0] post_fifo_axis_tid;
wire [DEST_WIDTH-1:0] post_fifo_axis_tdest;
wire [USER_WIDTH-1:0] post_fifo_axis_tuser;
generate
if (M_KEEP_WIDTH_INT == S_KEEP_WIDTH_INT) begin
// same width, no adapter needed
assign pre_fifo_axis_tdata = s_axis_tdata;
assign pre_fifo_axis_tkeep = s_axis_tkeep;
assign pre_fifo_axis_tvalid = s_axis_tvalid;
assign s_axis_tready = pre_fifo_axis_tready;
assign pre_fifo_axis_tlast = s_axis_tlast;
assign pre_fifo_axis_tid = s_axis_tid;
assign pre_fifo_axis_tdest = s_axis_tdest;
assign pre_fifo_axis_tuser = s_axis_tuser;
assign m_axis_tdata = post_fifo_axis_tdata;
assign m_axis_tkeep = post_fifo_axis_tkeep;
assign m_axis_tvalid = post_fifo_axis_tvalid;
assign post_fifo_axis_tready = m_axis_tready;
assign m_axis_tlast = post_fifo_axis_tlast;
assign m_axis_tid = post_fifo_axis_tid;
assign m_axis_tdest = post_fifo_axis_tdest;
assign m_axis_tuser = post_fifo_axis_tuser;
end else if (EXPAND_BUS) begin
// output wider, adapt width before FIFO
axis_adapter #(
.S_DATA_WIDTH(S_DATA_WIDTH),
.S_KEEP_ENABLE(S_KEEP_ENABLE),
.S_KEEP_WIDTH(S_KEEP_WIDTH),
.M_DATA_WIDTH(M_DATA_WIDTH),
.M_KEEP_ENABLE(M_KEEP_ENABLE),
.M_KEEP_WIDTH(M_KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH)
)
adapter_inst (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(s_axis_tid),
.s_axis_tdest(s_axis_tdest),
.s_axis_tuser(s_axis_tuser),
// AXI output
.m_axis_tdata(pre_fifo_axis_tdata),
.m_axis_tkeep(pre_fifo_axis_tkeep),
.m_axis_tvalid(pre_fifo_axis_tvalid),
.m_axis_tready(pre_fifo_axis_tready),
.m_axis_tlast(pre_fifo_axis_tlast),
.m_axis_tid(pre_fifo_axis_tid),
.m_axis_tdest(pre_fifo_axis_tdest),
.m_axis_tuser(pre_fifo_axis_tuser)
);
assign m_axis_tdata = post_fifo_axis_tdata;
assign m_axis_tkeep = post_fifo_axis_tkeep;
assign m_axis_tvalid = post_fifo_axis_tvalid;
assign post_fifo_axis_tready = m_axis_tready;
assign m_axis_tlast = post_fifo_axis_tlast;
assign m_axis_tid = post_fifo_axis_tid;
assign m_axis_tdest = post_fifo_axis_tdest;
assign m_axis_tuser = post_fifo_axis_tuser;
end else begin
// input wider, adapt width after FIFO
assign pre_fifo_axis_tdata = s_axis_tdata;
assign pre_fifo_axis_tkeep = s_axis_tkeep;
assign pre_fifo_axis_tvalid = s_axis_tvalid;
assign s_axis_tready = pre_fifo_axis_tready;
assign pre_fifo_axis_tlast = s_axis_tlast;
assign pre_fifo_axis_tid = s_axis_tid;
assign pre_fifo_axis_tdest = s_axis_tdest;
assign pre_fifo_axis_tuser = s_axis_tuser;
axis_adapter #(
.S_DATA_WIDTH(S_DATA_WIDTH),
.S_KEEP_ENABLE(S_KEEP_ENABLE),
.S_KEEP_WIDTH(S_KEEP_WIDTH),
.M_DATA_WIDTH(M_DATA_WIDTH),
.M_KEEP_ENABLE(M_KEEP_ENABLE),
.M_KEEP_WIDTH(M_KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH)
)
adapter_inst (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(post_fifo_axis_tdata),
.s_axis_tkeep(post_fifo_axis_tkeep),
.s_axis_tvalid(post_fifo_axis_tvalid),
.s_axis_tready(post_fifo_axis_tready),
.s_axis_tlast(post_fifo_axis_tlast),
.s_axis_tid(post_fifo_axis_tid),
.s_axis_tdest(post_fifo_axis_tdest),
.s_axis_tuser(post_fifo_axis_tuser),
// AXI output
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser)
);
end
endgenerate
axis_fifo #(
.DEPTH(DEPTH),
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(EXPAND_BUS ? M_KEEP_ENABLE : S_KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.LAST_ENABLE(1),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH),
.PIPELINE_OUTPUT(PIPELINE_OUTPUT),
.FRAME_FIFO(FRAME_FIFO),
.USER_BAD_FRAME_VALUE(USER_BAD_FRAME_VALUE),
.USER_BAD_FRAME_MASK(USER_BAD_FRAME_MASK),
.DROP_OVERSIZE_FRAME(DROP_OVERSIZE_FRAME),
.DROP_BAD_FRAME(DROP_BAD_FRAME),
.DROP_WHEN_FULL(DROP_WHEN_FULL)
)
fifo_inst (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(pre_fifo_axis_tdata),
.s_axis_tkeep(pre_fifo_axis_tkeep),
.s_axis_tvalid(pre_fifo_axis_tvalid),
.s_axis_tready(pre_fifo_axis_tready),
.s_axis_tlast(pre_fifo_axis_tlast),
.s_axis_tid(pre_fifo_axis_tid),
.s_axis_tdest(pre_fifo_axis_tdest),
.s_axis_tuser(pre_fifo_axis_tuser),
// AXI output
.m_axis_tdata(post_fifo_axis_tdata),
.m_axis_tkeep(post_fifo_axis_tkeep),
.m_axis_tvalid(post_fifo_axis_tvalid),
.m_axis_tready(post_fifo_axis_tready),
.m_axis_tlast(post_fifo_axis_tlast),
.m_axis_tid(post_fifo_axis_tid),
.m_axis_tdest(post_fifo_axis_tdest),
.m_axis_tuser(post_fifo_axis_tuser),
// Status
.status_overflow(status_overflow),
.status_bad_frame(status_bad_frame),
.status_good_frame(status_good_frame)
);
endmodule
`resetall
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Write Channel for ATC
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// w_atc
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
module processing_system7_v5_5_w_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_DATA_WIDTH = 64,
// Width of all DATA signals on SI and MI side of checker.
// Range: 64.
parameter integer C_AXI_WUSER_WIDTH = 1
// Width of AWUSER signals.
// Range: >= 1.
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface (In)
input wire cmd_w_valid,
input wire cmd_w_check,
input wire [C_AXI_ID_WIDTH-1:0] cmd_w_id,
output wire cmd_w_ready,
// Command Interface (Out)
output wire cmd_b_push,
output wire cmd_b_error,
output reg [C_AXI_ID_WIDTH-1:0] cmd_b_id,
input wire cmd_b_full,
// Slave Interface Write Port
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID,
input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input wire S_AXI_WLAST,
input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
// Master Interface Write Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID,
output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire M_AXI_WLAST,
output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY
);
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Detecttion.
wire any_strb_deasserted;
wire incoming_strb_issue;
reg first_word;
reg strb_issue;
// Data flow.
wire data_pop;
wire cmd_b_push_blocked;
reg cmd_b_push_i;
/////////////////////////////////////////////////////////////////////////////
// Detect error:
//
// Detect and accumulate error when a transaction shall be scanned for
// potential issues.
// Accumulation of error is restarted for each ne transaction.
//
/////////////////////////////////////////////////////////////////////////////
// Check stobe information
assign any_strb_deasserted = ( S_AXI_WSTRB != {C_AXI_DATA_WIDTH/8{1'b1}} );
assign incoming_strb_issue = cmd_w_valid & S_AXI_WVALID & cmd_w_check & any_strb_deasserted;
// Keep track of first word in a transaction.
always @ (posedge ACLK) begin
if (ARESET) begin
first_word <= 1'b1;
end else if ( data_pop ) begin
first_word <= S_AXI_WLAST;
end
end
// Keep track of error status.
always @ (posedge ACLK) begin
if (ARESET) begin
strb_issue <= 1'b0;
cmd_b_id <= {C_AXI_ID_WIDTH{1'b0}};
end else if ( data_pop ) begin
if ( first_word ) begin
strb_issue <= incoming_strb_issue;
end else begin
strb_issue <= incoming_strb_issue | strb_issue;
end
cmd_b_id <= cmd_w_id;
end
end
assign cmd_b_error = strb_issue;
/////////////////////////////////////////////////////////////////////////////
// Control command queue to B:
//
// Push command to B queue when all data for the transaction has flowed
// through.
// Delay pipelined command until there is room in the Queue.
//
/////////////////////////////////////////////////////////////////////////////
// Detect when data is popped.
assign data_pop = S_AXI_WVALID & M_AXI_WREADY & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked;
// Push command when last word in transfered (pipelined).
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_b_push_i <= 1'b0;
end else begin
cmd_b_push_i <= ( S_AXI_WLAST & data_pop ) | cmd_b_push_blocked;
end
end
// Detect if pipelined push is blocked.
assign cmd_b_push_blocked = cmd_b_push_i & cmd_b_full;
// Assign output.
assign cmd_b_push = cmd_b_push_i & ~cmd_b_full;
/////////////////////////////////////////////////////////////////////////////
// Transaction Throttling:
//
// Stall commands if FIFO is full or there is no valid command information
// from AW.
//
/////////////////////////////////////////////////////////////////////////////
// Propagate masked valid.
assign M_AXI_WVALID = S_AXI_WVALID & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked;
// Return ready with push back.
assign S_AXI_WREADY = M_AXI_WREADY & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked;
// End of burst.
assign cmd_w_ready = S_AXI_WVALID & M_AXI_WREADY & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked & S_AXI_WLAST;
/////////////////////////////////////////////////////////////////////////////
// Write propagation:
//
// All information is simply forwarded on from the SI- to MI-Side untouched.
//
/////////////////////////////////////////////////////////////////////////////
// 1:1 mapping.
assign M_AXI_WID = S_AXI_WID;
assign M_AXI_WDATA = S_AXI_WDATA;
assign M_AXI_WSTRB = S_AXI_WSTRB;
assign M_AXI_WLAST = S_AXI_WLAST;
assign M_AXI_WUSER = S_AXI_WUSER;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__UDP_DFF_PR_PP_PG_N_SYMBOL_V
`define SKY130_FD_SC_LS__UDP_DFF_PR_PP_PG_N_SYMBOL_V
/**
* udp_dff$PR_pp$PG$N: Positive edge triggered D flip-flop with active
* high
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__udp_dff$PR_pp$PG$N (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input NOTIFIER,
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__UDP_DFF_PR_PP_PG_N_SYMBOL_V
|
/* salsaengine.v
*
* Copyright (c) 2013 kramble
* Parts copyright (c) 2011 [email protected]
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
// NB HALFRAM no longer applies, configure via parameters ADDRBITS, THREADS
// Bracket this config option in SIM so we don't accidentally leave it set in a live build
`ifdef SIM
//`define ONETHREAD // Start one thread only (for SIMULATION less confusing and faster startup)
`endif
`timescale 1ns/1ps
module salsaengine (hash_clk, reset, din, dout, shift, start, busy, result );
input hash_clk;
input reset; // NB pbkdf_clk domain (need a long reset (at least THREADS+4) to initialize correctly, this is done in pbkdfengine (15 cycles)
input shift;
input start; // NB pbkdf_clk domain
output busy;
output reg result = 1'b0;
parameter SBITS = 8; // Shift data path width
input [SBITS-1:0] din;
output [SBITS-1:0] dout;
// Configure ADDRBITS to allocate RAM for core (automatically sets LOOKAHEAD_GAP)
// NB do not use ADDRBITS > 13 for THREADS=8 since this corresponds to more than a full scratchpad
// These settings are now overriden in ltcminer_icarus.v determined by LOCAL_MINERS ...
// parameter ADDRBITS = 13; // 8MBit RAM allocated to core, full scratchpad (will not fit LX150)
parameter ADDRBITS = 12; // 4MBit RAM allocated to core, half scratchpad
// parameter ADDRBITS = 11; // 2MBit RAM allocated to core, quarter scratchpad
// parameter ADDRBITS = 10; // 1MBit RAM allocated to core, eighth scratchpad
// Do not change THREADS - this must match the salsa pipeline (code is untested for other values)
parameter THREADS = 16; // NB Phase has THREADS+1 cycles
function integer clog2; // Courtesy of razorfishsl, replaces $clog2()
input integer value;
begin
value = value-1;
for (clog2=0; value>0; clog2=clog2+1)
value = value>>1;
end
endfunction
parameter THREADS_BITS = clog2(THREADS);
// Workaround for range-reversal error in inactive code when ADDRBITS=13
parameter ADDRBITSX = (ADDRBITS == 13) ? ADDRBITS-1 : ADDRBITS;
reg [THREADS_BITS:0]phase = 0;
reg [THREADS_BITS:0]phase_d = THREADS+1;
reg reset_d=0, fsmreset=0, start_d=0, fsmstart=0;
always @ (posedge hash_clk) // Phase control and sync
begin
phase <= (phase == THREADS) ? 0 : phase + 1;
phase_d <= phase;
reset_d <= reset; // Synchronise to hash_clk domain
fsmreset <= reset_d;
start_d <= start;
fsmstart <= start_d;
end
// Salsa Mix FSM (handles both loading of the scratchpad ROM and the subsequent processing)
parameter XSnull = 0, XSload = 1, XSmix = 2, XSram = 4; // One-hot since these map directly to mux contrls
reg [2:0] XCtl = XSnull;
parameter R_IDLE=0, R_START=1, R_WRITE=2, R_MIX=3, R_INT=4, R_WAIT=5;
reg [2:0] mstate = R_IDLE;
reg [10:0] cycle = 11'd0;
reg doneROM = 1'd0; // Yes ROM, as its referred thus in the salsa docs
reg addrsourceMix = 1'b0;
reg datasourceLoad = 1'b0;
reg addrsourceSave = 1'b0;
reg resultsourceRam = 1'b0;
reg xoren = 1'b1;
reg [THREADS_BITS+1:0] intcycles = 0; // Number of interpolation cycles required ... How many do we need? Say THREADS_BITS+1
wire [511:0] Xmix;
reg [511:0] X0;
reg [511:0] X1;
wire [511:0] X0in;
wire [511:0] X1in;
wire [511:0] X0out;
reg [1023:0] salsaShiftReg;
reg [31:0] nonce_sr; // In series with salsaShiftReg
assign dout = salsaShiftReg[1023:1024-SBITS];
// sstate is implemented in ram (alternatively could use a rotating shift register)
reg [THREADS_BITS+30:0] sstate [THREADS-1:0]; // NB initialized via a long reset (see pbkdfengine)
// List components of sstate here for ease of maintenance ...
wire [2:0] mstate_in;
wire [10:0] cycle_in;
wire [9:0] writeaddr_in;
wire doneROM_in;
wire addrsourceMix_in;
wire addrsourceSave_in;
wire [THREADS_BITS+1:0] intcycles_in; // How many do we need? Say THREADS_BITS+1
wire [9:0] writeaddr_next = writeaddr_in + 10'd1;
reg [31:0] snonce [THREADS-1:0]; // Nonce store. Note bidirectional loading below, this will either implement
// as registers or dual-port ram, so do NOT integrate with sstate.
// NB no busy_in or result_in as these flag are NOT saved on a per-thread basis
// Convert salsaShiftReg to little-endian word format to match scrypt.c as its easier to debug it
// this way rather than recoding the SMix salsa to work with original buffer
wire [1023:0] X;
`define IDX(x) (((x)+1)*(32)-1):((x)*(32))
genvar i;
generate
for (i = 0; i < 32; i = i + 1) begin : Xrewire
wire [31:0] tmp;
assign tmp = salsaShiftReg[`IDX(i)];
assign X[`IDX(i)] = { tmp[7:0], tmp[15:8], tmp[23:16], tmp[31:24] };
end
endgenerate
// NB writeaddr is cycle counter in R_WRITE so use full size regardless of RAM size
(* S = "TRUE" *) reg [9:0] writeaddr = 10'd0;
// ALTRAM Max is 256 bit width, so use four
// Ram is registered on inputs vis ram_addr, ram_din and ram_wren
// Output is unregistered, OLD data on write (less delay than NEW??)
wire [9:0] Xaddr;
wire [ADDRBITS-1:0]rd_addr;
wire [ADDRBITS-1:0]wr_addr1;
wire [ADDRBITS-1:0]wr_addr2;
wire [ADDRBITS-1:0]wr_addr3;
wire [ADDRBITS-1:0]wr_addr4;
wire [255:0]ram1_din;
wire [255:0]ram1_dout;
wire [255:0]ram2_din;
wire [255:0]ram2_dout;
wire [255:0]ram3_din;
wire [255:0]ram3_dout;
wire [255:0]ram4_din;
wire [255:0]ram4_dout;
wire [1023:0]ramout;
(* S = "TRUE" *) reg ram_wren = 1'b0;
wire ram_clk;
assign ram_clk = hash_clk; // Uses same clock as hasher for now
// Top ram address is reserved for X0Save/X1save, so adjust
wire [15:0] memtop = 16'hfffe; // One less than the top memory location (per THREAD bank)
wire [ADDRBITS-THREADS_BITS-1:0] adj_addr;
if (ADDRBITS < 13)
assign adj_addr = (Xaddr[9:THREADS_BITS+10-ADDRBITS] == memtop[9:THREADS_BITS+10-ADDRBITS]) ?
memtop[ADDRBITS-THREADS_BITS-1:0] : Xaddr[9:THREADS_BITS+10-ADDRBITS];
else
assign adj_addr = Xaddr;
wire [THREADS_BITS-1:0] phase_addr;
assign phase_addr = phase[THREADS_BITS-1:0];
// TODO can we remove the +1 and adjust the wr_addr to use the same prefix via phase_d?
assign rd_addr = { phase_addr+1, addrsourceSave_in ? memtop[ADDRBITS-THREADS_BITS:1] : adj_addr }; // LSB are ignored
wire [9:0] writeaddr_adj = addrsourceMix ? memtop[10:1] : writeaddr;
assign wr_addr1 = { phase_addr, writeaddr_adj[9:THREADS_BITS+10-ADDRBITS] };
assign wr_addr2 = { phase_addr, writeaddr_adj[9:THREADS_BITS+10-ADDRBITS] };
assign wr_addr3 = { phase_addr, writeaddr_adj[9:THREADS_BITS+10-ADDRBITS] };
assign wr_addr4 = { phase_addr, writeaddr_adj[9:THREADS_BITS+10-ADDRBITS] };
// Duplicate address to reduce fanout (its a ridiculous kludge, but seems to be the approved method)
(* S = "TRUE" *) reg [ADDRBITS-1:0] rd_addr_z_1 = 0;
(* S = "TRUE" *) reg [ADDRBITS-1:0] rd_addr_z_2 = 0;
(* S = "TRUE" *) reg [ADDRBITS-1:0] rd_addr_z_3 = 0;
(* S = "TRUE" *) reg [ADDRBITS-1:0] rd_addr_z_4 = 0;
(* S = "TRUE" *) wire [ADDRBITS-1:0] rd_addr1 = rd_addr | rd_addr_z_1;
(* S = "TRUE" *) wire [ADDRBITS-1:0] rd_addr2 = rd_addr | rd_addr_z_2;
(* S = "TRUE" *) wire [ADDRBITS-1:0] rd_addr3 = rd_addr | rd_addr_z_3;
(* S = "TRUE" *) wire [ADDRBITS-1:0] rd_addr4 = rd_addr | rd_addr_z_4;
ram # (.ADDRBITS(ADDRBITS)) ram1_blk (rd_addr1, wr_addr1, ram_clk, ram1_din, ram_wren, ram1_dout);
ram # (.ADDRBITS(ADDRBITS)) ram2_blk (rd_addr2, wr_addr2, ram_clk, ram2_din, ram_wren, ram2_dout);
ram # (.ADDRBITS(ADDRBITS)) ram3_blk (rd_addr3, wr_addr3, ram_clk, ram3_din, ram_wren, ram3_dout);
ram # (.ADDRBITS(ADDRBITS)) ram4_blk (rd_addr4, wr_addr4, ram_clk, ram4_din, ram_wren, ram4_dout);
assign ramout = { ram4_dout, ram3_dout, ram2_dout, ram1_dout }; // Unregistered output
assign { ram4_din, ram3_din, ram2_din, ram1_din } = datasourceLoad ? X : { Xmix, X0out}; // Registered input
// Salsa unit
salsa salsa_blk (hash_clk, X0, X1, Xmix, X0out, Xaddr);
// Main multiplexer
wire [511:0] Zbits;
assign Zbits = {512{xoren}}; // xoren enables xor from ram (else we load from ram)
// With luck the synthesizer will interpret this correctly as one-hot control ...
// DEBUG using default state of 0 for XSnull so as to show up issues with preserved values (previously held value X0/X1)
// assign X0in = (XCtl==XSmix) ? X0out : (XCtl==XSram) ? (X0out & Zbits) ^ ramout[511:0] : (XCtl==XSload) ? X[511:0] : 0;
// assign X1in = (XCtl==XSmix) ? Xmix : (XCtl==XSram) ? (Xmix & Zbits) ^ ramout[1023:512] : (XCtl==XSload) ? X[1023:512] : 0;
// Now using explicit control signals (rather than relying on synthesizer to map correctly)
// XSMix is now the default (XSnull is unused as this mapped onto zero in the DEBUG version above) - TODO amend FSM accordingly
assign X0in = XCtl[2] ? (X0out & Zbits) ^ ramout[511:0] : XCtl[0] ? X[511:0] : X0out;
assign X1in = XCtl[2] ? (Xmix & Zbits) ^ ramout[1023:512] : XCtl[0] ? X[1023:512] : Xmix;
// Salsa FSM - TODO may want to move this into a separate function (for floorplanning), see hashvariant-C
// Hold separate state for each thread (a bit of a kludge to avoid rewriting FSM from scratch)
// NB must ensure shift and result do NOT overlap by carefully controlling timing of start signal
// NB Phase has THREADS+1 cycles, but we do not save the state for (phase==THREADS) as it is never active
assign { mstate_in, writeaddr_in, cycle_in, doneROM_in, addrsourceMix_in, addrsourceSave_in, intcycles_in} =
(phase == THREADS ) ? 0 : sstate[phase];
// Interface FSM ensures threads start evenly (required for correct salsa FSM operation)
reg busy_flag = 1'b0;
`ifdef ONETHREAD
// TEST CONTROLLER ... just allow a single thread to run (busy is currently a common flag)
// NB the thread automatically restarts after it completes, so its a slight misnomer to say it starts once.
reg start_once = 1'b0;
wire start_flag;
assign start_flag = fsmstart & ~start_once;
assign busy = busy_flag; // Ack to pbkdfengine
`else
// NB start_flag only has effect when a thread is at R_IDLE, ie after reset, normally a thread will automatically
// restart on completion. We need to spread the R_IDLE starts evenly to ensure proper ooperation. NB the pbkdf
// engine requires busy and result, but this looks alter itself in the salsa FSM, even though these are global
// flags. Reset periodically (on loadnonce in pbkdfengine) to ensure it stays in sync.
reg [15:0] start_count = 0;
// TODO automatic configuration (currently assumes THREADS 8 or 16, and ADDRBITS 12,11,10 calculated as follows...)
// For THREADS=8, lookup_gap=2 salsa takes on average 9*(1024+(1024*1.5)) = 23040 clocks, generically 9*1024*(lookup_gap/2+1.5)
// For THREADS=16, use 17*1024*(lookup_gap/2+1.5), where lookupgap is double that for THREADS=8
parameter START_INTERVAL = (THREADS==16) ? ((ADDRBITS==12) ? 60928 : (ADDRBITS==11) ? 95744 : 165376) / THREADS : // 16 threads
((ADDRBITS==12) ? 23040 : (ADDRBITS==11) ? 36864 : 50688) / THREADS ; // 8 threads
reg start_flag = 1'b0;
assign busy = busy_flag; // Ack to pbkdfengine - this will toggle on transtion through R_START
`endif
always @ (posedge hash_clk)
begin
X0 <= X0in;
X1 <= X1in;
if (phase_d != THREADS)
sstate[phase_d] <= fsmreset ? 0 : { mstate, writeaddr, cycle, doneROM, addrsourceMix, addrsourceSave, intcycles };
mstate <= mstate_in; // Set defaults (overridden below as necessary)
writeaddr <= writeaddr_in;
cycle <= cycle_in;
intcycles <= intcycles_in;
doneROM <= doneROM_in;
addrsourceMix <= addrsourceMix_in;
addrsourceSave <= addrsourceSave_in; // Overwritten below, but addrsourceSave_in is used above
// Duplicate address to reduce fanout (its a ridiculous kludge, but seems to be the approved method)
rd_addr_z_1 <= {ADDRBITS{fsmreset}};
rd_addr_z_2 <= {ADDRBITS{fsmreset}};
rd_addr_z_3 <= {ADDRBITS{fsmreset}};
rd_addr_z_4 <= {ADDRBITS{fsmreset}};
XCtl <= XSnull; // Default states
addrsourceSave <= 0; // NB addrsourceSave_in is the active control so this DOES need to be in sstate
datasourceLoad <= 0; // Does not need to be saved in sstate
resultsourceRam <= 0; // Does not need to be saved in sstate
ram_wren <= 0;
xoren <= 1;
// Interface FSM ensures threads start evenly (required for correct salsa FSM operation)
`ifdef ONETHREAD
if (fsmstart && phase!=THREADS)
start_once <= 1'b1;
if (fsmreset)
start_once <= 1'b0;
`else
start_count <= start_count + 1;
// start_flag <= 1'b0; // Done below when we transition out of R_IDLE
if (fsmreset || start_count == START_INTERVAL)
begin
start_count <= 0;
if (~fsmreset && fsmstart)
start_flag <= 1'b1;
end
`endif
// Could use explicit mux for this ...
if (shift)
begin
salsaShiftReg <= { salsaShiftReg[1023-SBITS:0], nonce_sr[31:32-SBITS] };
nonce_sr <= { nonce_sr[31-SBITS:0], din};
end
else
if (XCtl==XSload && phase_d != THREADS) // Set at end of previous hash - this is executed regardless of phase
begin
salsaShiftReg <= resultsourceRam ? ramout : { Xmix, X0out }; // Simultaneously with XSload
nonce_sr <= snonce[phase_d]; // NB bidirectional load
snonce[phase_d] <= nonce_sr;
end
if (fsmreset == 1'b1)
begin
mstate <= R_IDLE; // This will propagate to all sstate slots as we hold reset for 10 cycles
busy_flag <= 1'b0;
result <= 1'b0;
end
else
begin
case (mstate_in)
R_IDLE: begin
// R_IDLE only applies after reset. Normally each thread will reenter at S_START and
// assumes that input data is waiting (this relies on the threads being started evenly,
// hence the interface FSM at the top of this file)
if (phase!=THREADS && start_flag) // Ensure (phase==THREADS) slot is never active
begin
XCtl <= XSload; // First time only (normally done at end of previous salsa cycle=1023)
`ifndef ONETHREAD
start_flag <= 1'b0;
`endif
busy_flag <= 1'b0; // Toggle the busy flag low to ack pbkdfengine (its usually already set
// since other threads are running)
writeaddr <= 0; // Preset to write X on next cycle
addrsourceMix <= 1'b0;
datasourceLoad <= 1'b1;
ram_wren <= 1'b1;
mstate <= R_START;
end
end
R_START: begin // Reentry point after thread completion. ASSUMES new data is ready.
XCtl <= XSmix;
writeaddr <= writeaddr_next;
cycle <= 0;
if (ADDRBITS == 13)
ram_wren <= 1'b1; // Full scratchpad needs to write to addr=001 next cycle
doneROM <= 1'b0;
busy_flag <= 1'b1;
result <= 1'b0;
mstate <= R_WRITE;
end
R_WRITE: begin
XCtl <= XSmix;
writeaddr <= writeaddr_next;
if (writeaddr_in==1022)
doneROM <= 1'b1; // Need to do one more cycle to update X0,X1
else
if (~doneROM_in)
begin
if (ADDRBITS < 13)
ram_wren <= ~|writeaddr_next[THREADS_BITS+9-ADDRBITSX:0]; // Only write non-interpolated addresses
else
ram_wren <= 1'b1;
end
if (doneROM_in)
begin
addrsourceMix <= 1'b1; // Remains set for duration of R_MIX
mstate <= R_MIX;
XCtl <= XSram; // Load from ram next cycle
// Need this to cover the case of the initial read being interpolated
// NB CODE IS REPLICATED IN R_MIX
if (ADDRBITS < 13)
begin
intcycles <= { {THREADS_BITS+12-ADDRBITSX{1'b0}}, Xaddr[THREADS_BITS+9-ADDRBITSX:0] }; // Interpolated addresses
if ( Xaddr[9:THREADS_BITS+10-ADDRBITSX] == memtop[ADDRBITSX-THREADS_BITS:1] ) // Highest address reserved
intcycles <= { {THREADS_BITS+11-ADDRBITSX{1'b0}}, 1'b1, Xaddr[THREADS_BITS+9-ADDRBITSX:0] };
if ( (Xaddr[9:THREADS_BITS+10-ADDRBITSX] == memtop[ADDRBITSX-THREADS_BITS:1]) || |Xaddr[THREADS_BITS+9-ADDRBITSX:0] )
begin
ram_wren <= 1'b1;
xoren <= 0; // Will do direct load from ram, not xor
mstate <= R_INT; // Interpolate
end
// If intcycles will be set to 1, need to preset for readback
if (
( Xaddr[THREADS_BITS+9-ADDRBITSX:0] == 1 ) &&
!( Xaddr[9:THREADS_BITS+10-ADDRBITSX] == memtop[ADDRBITSX-THREADS_BITS:1] )
)
addrsourceSave <= 1'b1; // Preset to read saved data (9 clocks later)
end
// END REPLICATED BLOCK
end
end
R_MIX: begin
// NB There is an extra step here cf R_WRITE above to read ram data hence 9 not 8 stages.
XCtl <= XSmix;
cycle <= cycle_in + 11'd1;
if (cycle_in==1023)
begin
busy_flag <= 1'b0; // Will hold at 0 for 9 clocks until set at R_START
if (fsmstart) // Check data input is ready
begin
XCtl <= XSload; // Initial load else we overwrite input NB This is
// executed on the next cycle, regardless of phase
// Flag the SHA256 FSM to start final PBKDF2_SHA256_80_128_32
result <= 1'b1;
mstate <= R_START; // Restart immediately
writeaddr <= 0; // Preset to write X on next cycle
datasourceLoad <= 1'b1;
addrsourceMix <= 1'b0;
ram_wren <= 1'b1;
end
else
begin
// mstate <= R_IDLE; // Wait for start_flag
mstate <= R_WAIT;
addrsourceSave <= 1'b1; // Preset to read saved data (9 clocks later)
ram_wren <= 1'b1; // Save result
end
end
else
begin
XCtl <= XSram; // Load from ram next cycle
// NB CODE IS REPLICATED IN R_WRITE
if (ADDRBITS < 13)
begin
intcycles <= { {THREADS_BITS+12-ADDRBITSX{1'b0}}, Xaddr[THREADS_BITS+9-ADDRBITSX:0] }; // Interpolated addresses
if ( Xaddr[9:THREADS_BITS+10-ADDRBITSX] == memtop[ADDRBITSX-THREADS_BITS:1] ) // Highest address reserved
intcycles <= { {THREADS_BITS+11-ADDRBITSX{1'b0}}, 1'b1, Xaddr[THREADS_BITS+9-ADDRBITSX:0] };
if ( (Xaddr[9:THREADS_BITS+10-ADDRBITSX] == memtop[ADDRBITSX-THREADS_BITS:1]) || |Xaddr[THREADS_BITS+9-ADDRBITSX:0] )
begin
ram_wren <= 1'b1;
xoren <= 0; // Will do direct load from ram, not xor
mstate <= R_INT; // Interpolate
end
// If intcycles will be set to 1, need to preset for readback
if (
( Xaddr[THREADS_BITS+9-ADDRBITSX:0] == 1 ) &&
!( Xaddr[9:THREADS_BITS+10-ADDRBITSX] == memtop[ADDRBITSX-THREADS_BITS:1] )
)
addrsourceSave <= 1'b1; // Preset to read saved data (9 clocks later)
end
// END REPLICATED BLOCK
end
end
R_WAIT: begin
if (fsmstart) // Check data input is ready
begin
XCtl <= XSload; // Initial load else we overwrite input NB This is
// executed on the next cycle, regardless of phase
// Flag the SHA256 FSM to start final PBKDF2_SHA256_80_128_32
result <= 1'b1;
mstate <= R_START; // Restart immediately
writeaddr <= 0; // Preset to write X on next cycle
datasourceLoad <= 1'b1;
resultsourceRam <= 1'b1;
addrsourceMix <= 1'b0;
ram_wren <= 1'b1;
end
else
addrsourceSave <= 1'b1; // Preset to read saved data (9 clocks later)
end
R_INT: begin
// Interpolate scratchpad for odd addresses
XCtl <= XSmix;
intcycles <= intcycles_in - 1;
if (intcycles_in==2)
addrsourceSave <= 1'b1; // Preset to read saved data (9 clocks later)
if (intcycles_in==1)
begin
XCtl <= XSram; // Setup to XOR from saved X0/X1 in ram at next cycle
mstate <= R_MIX;
end
// Else mstate remains at R_INT so we continue interpolating
end
endcase
end
`ifdef SIM
// Print the final Xmix for each cycle to compare with scrypt.c (debugging)
if (mstate==R_MIX)
$display ("phase %d cycle %d Xmix %08x\n", phase, cycle-1, Xmix[511:480]);
`endif
end // always @(posedge hash_clk)
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__TAPVPWRVGND_SYMBOL_V
`define SKY130_FD_SC_HD__TAPVPWRVGND_SYMBOL_V
/**
* tapvpwrvgnd: Substrate and well tap cell.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__tapvpwrvgnd ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__TAPVPWRVGND_SYMBOL_V
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcieCore_pcie_pipe_misc.v
// Version : 1.11
//
// Description: Misc PIPE module for 7-Series PCIe Block
//
//
//
//--------------------------------------------------------------------------------
`timescale 1ps/1ps
module pcieCore_pcie_pipe_misc #
(
parameter PIPE_PIPELINE_STAGES = 0 // 0 - 0 stages, 1 - 1 stage, 2 - 2 stages
)
(
input wire pipe_tx_rcvr_det_i , // PIPE Tx Receiver Detect
input wire pipe_tx_reset_i , // PIPE Tx Reset
input wire pipe_tx_rate_i , // PIPE Tx Rate
input wire pipe_tx_deemph_i , // PIPE Tx Deemphasis
input wire [2:0] pipe_tx_margin_i , // PIPE Tx Margin
input wire pipe_tx_swing_i , // PIPE Tx Swing
output wire pipe_tx_rcvr_det_o , // Pipelined PIPE Tx Receiver Detect
output wire pipe_tx_reset_o , // Pipelined PIPE Tx Reset
output wire pipe_tx_rate_o , // Pipelined PIPE Tx Rate
output wire pipe_tx_deemph_o , // Pipelined PIPE Tx Deemphasis
output wire [2:0] pipe_tx_margin_o , // Pipelined PIPE Tx Margin
output wire pipe_tx_swing_o , // Pipelined PIPE Tx Swing
input wire pipe_clk , // PIPE Clock
input wire rst_n // Reset
);
//******************************************************************//
// Reality check. //
//******************************************************************//
parameter TCQ = 1; // clock to out delay model
generate
if (PIPE_PIPELINE_STAGES == 0) begin : pipe_stages_0
assign pipe_tx_rcvr_det_o = pipe_tx_rcvr_det_i;
assign pipe_tx_reset_o = pipe_tx_reset_i;
assign pipe_tx_rate_o = pipe_tx_rate_i;
assign pipe_tx_deemph_o = pipe_tx_deemph_i;
assign pipe_tx_margin_o = pipe_tx_margin_i;
assign pipe_tx_swing_o = pipe_tx_swing_i;
end // if (PIPE_PIPELINE_STAGES == 0)
else if (PIPE_PIPELINE_STAGES == 1) begin : pipe_stages_1
reg pipe_tx_rcvr_det_q ;
reg pipe_tx_reset_q ;
reg pipe_tx_rate_q ;
reg pipe_tx_deemph_q ;
reg [2:0] pipe_tx_margin_q ;
reg pipe_tx_swing_q ;
always @(posedge pipe_clk) begin
if (rst_n)
begin
pipe_tx_rcvr_det_q <= #TCQ 0;
pipe_tx_reset_q <= #TCQ 1'b1;
pipe_tx_rate_q <= #TCQ 0;
pipe_tx_deemph_q <= #TCQ 1'b1;
pipe_tx_margin_q <= #TCQ 0;
pipe_tx_swing_q <= #TCQ 0;
end
else
begin
pipe_tx_rcvr_det_q <= #TCQ pipe_tx_rcvr_det_i;
pipe_tx_reset_q <= #TCQ pipe_tx_reset_i;
pipe_tx_rate_q <= #TCQ pipe_tx_rate_i;
pipe_tx_deemph_q <= #TCQ pipe_tx_deemph_i;
pipe_tx_margin_q <= #TCQ pipe_tx_margin_i;
pipe_tx_swing_q <= #TCQ pipe_tx_swing_i;
end
end
assign pipe_tx_rcvr_det_o = pipe_tx_rcvr_det_q;
assign pipe_tx_reset_o = pipe_tx_reset_q;
assign pipe_tx_rate_o = pipe_tx_rate_q;
assign pipe_tx_deemph_o = pipe_tx_deemph_q;
assign pipe_tx_margin_o = pipe_tx_margin_q;
assign pipe_tx_swing_o = pipe_tx_swing_q;
end // if (PIPE_PIPELINE_STAGES == 1)
else if (PIPE_PIPELINE_STAGES == 2) begin : pipe_stages_2
reg pipe_tx_rcvr_det_q ;
reg pipe_tx_reset_q ;
reg pipe_tx_rate_q ;
reg pipe_tx_deemph_q ;
reg [2:0] pipe_tx_margin_q ;
reg pipe_tx_swing_q ;
reg pipe_tx_rcvr_det_qq ;
reg pipe_tx_reset_qq ;
reg pipe_tx_rate_qq ;
reg pipe_tx_deemph_qq ;
reg [2:0] pipe_tx_margin_qq ;
reg pipe_tx_swing_qq ;
always @(posedge pipe_clk) begin
if (rst_n)
begin
pipe_tx_rcvr_det_q <= #TCQ 0;
pipe_tx_reset_q <= #TCQ 1'b1;
pipe_tx_rate_q <= #TCQ 0;
pipe_tx_deemph_q <= #TCQ 1'b1;
pipe_tx_margin_q <= #TCQ 0;
pipe_tx_swing_q <= #TCQ 0;
pipe_tx_rcvr_det_qq <= #TCQ 0;
pipe_tx_reset_qq <= #TCQ 1'b1;
pipe_tx_rate_qq <= #TCQ 0;
pipe_tx_deemph_qq <= #TCQ 1'b1;
pipe_tx_margin_qq <= #TCQ 0;
pipe_tx_swing_qq <= #TCQ 0;
end
else
begin
pipe_tx_rcvr_det_q <= #TCQ pipe_tx_rcvr_det_i;
pipe_tx_reset_q <= #TCQ pipe_tx_reset_i;
pipe_tx_rate_q <= #TCQ pipe_tx_rate_i;
pipe_tx_deemph_q <= #TCQ pipe_tx_deemph_i;
pipe_tx_margin_q <= #TCQ pipe_tx_margin_i;
pipe_tx_swing_q <= #TCQ pipe_tx_swing_i;
pipe_tx_rcvr_det_qq <= #TCQ pipe_tx_rcvr_det_q;
pipe_tx_reset_qq <= #TCQ pipe_tx_reset_q;
pipe_tx_rate_qq <= #TCQ pipe_tx_rate_q;
pipe_tx_deemph_qq <= #TCQ pipe_tx_deemph_q;
pipe_tx_margin_qq <= #TCQ pipe_tx_margin_q;
pipe_tx_swing_qq <= #TCQ pipe_tx_swing_q;
end
end
assign pipe_tx_rcvr_det_o = pipe_tx_rcvr_det_qq;
assign pipe_tx_reset_o = pipe_tx_reset_qq;
assign pipe_tx_rate_o = pipe_tx_rate_qq;
assign pipe_tx_deemph_o = pipe_tx_deemph_qq;
assign pipe_tx_margin_o = pipe_tx_margin_qq;
assign pipe_tx_swing_o = pipe_tx_swing_qq;
end // if (PIPE_PIPELINE_STAGES == 2)
endgenerate
endmodule
|
/*
* Modified to add "endtask : <name>" syntax. This modification tests
* the SystemVerilog extension to the syntax. -- Stephen Williams
*/
/*
* Copyright (c) 2001 Stephan Boettcher <[email protected]>
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
// $Id: task_scope.v,v 1.1 2001/06/19 13:52:13 ka6s Exp $
// $Log: task_scope.v,v $
// Revision 1.1 2001/06/19 13:52:13 ka6s
// Added 4 tests from Stephan Boettcher
//
// Test for task scope lookup in VVP
module test;
wire w;
jobs j(w);
task ini;
begin
j.set(1'bz);
end
endtask : ini
initial
begin
ini;
#1;
j.set(1'b1);
#1;
if (w===1)
$display("PASSED");
else
$display("FAILED");
end
endmodule // test
module jobs (out);
output out;
reg out;
task set;
input val;
begin
#1 out = val;
end
endtask : set
endmodule // jobs
|
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module acl_fp_atanpi_s5 (
enable,
clock,
dataa,
result);
input enable;
input clock;
input [31:0] dataa;
output [31:0] result;
wire [31:0] sub_wire0;
wire [31:0] result = sub_wire0[31:0];
fp_atanpi_s5 inst (
.en (enable),
.areset(1'b0),
.clk(clock),
.a(dataa),
.q(sub_wire0));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFBBN_TB_V
`define SKY130_FD_SC_MS__DFBBN_TB_V
/**
* dfbbn: Delay flop, inverted set, inverted reset, inverted clock,
* complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__dfbbn.v"
module top();
// Inputs are registered
reg D;
reg SET_B;
reg RESET_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET_B = 1'bX;
SET_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 RESET_B = 1'b0;
#60 SET_B = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 D = 1'b1;
#180 RESET_B = 1'b1;
#200 SET_B = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 D = 1'b0;
#320 RESET_B = 1'b0;
#340 SET_B = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 SET_B = 1'b1;
#540 RESET_B = 1'b1;
#560 D = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 SET_B = 1'bx;
#680 RESET_B = 1'bx;
#700 D = 1'bx;
end
// Create a clock
reg CLK_N;
initial
begin
CLK_N = 1'b0;
end
always
begin
#5 CLK_N = ~CLK_N;
end
sky130_fd_sc_ms__dfbbn dut (.D(D), .SET_B(SET_B), .RESET_B(RESET_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .CLK_N(CLK_N));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFBBN_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__BUFBUF_SYMBOL_V
`define SKY130_FD_SC_HDLL__BUFBUF_SYMBOL_V
/**
* bufbuf: Double buffer.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__bufbuf (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__BUFBUF_SYMBOL_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
// Date : Fri Mar 31 09:06:21 2017
// Host : Shaun running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/Users/Shaun/Desktop/ip_repo/axi_compression_1.0/src/output_fifo/output_fifo_stub.v
// Design : output_fifo
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "fifo_generator_v13_1_3,Vivado 2016.4" *)
module output_fifo(clk, srst, din, wr_en, rd_en, dout, full, empty)
/* synthesis syn_black_box black_box_pad_pin="clk,srst,din[11:0],wr_en,rd_en,dout[11:0],full,empty" */;
input clk;
input srst;
input [11:0]din;
input wr_en;
input rd_en;
output [11:0]dout;
output full;
output empty;
endmodule
|
/*
* Copyright (c) 2000 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module main;
reg foo = 0;
initial #10 foo = 1;
initial #1 begin
if (foo !== 1'b0) begin
$display("FAILED -- foo before wait is %b", foo);
$finish;
end
// This wait without a statement has caused a few bugs.
wait (foo) ;
if (foo !== 1'b1) begin
$display("FAILED -- foo after wait is %b", foo);
$finish;
end
if ($time != 10) begin
$display("FAILED -- $time after wait is %t", $time);
$finish;
end
$display("PASSED");
end
endmodule // main
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:37:28 07/09/2015
// Design Name:
// Module Name: DVI_OUT
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module DVI_OUT
( input PixelClk,
input PixelClk2,
input PixelClk10,
input SerDesStrobe,
input [7:0] Red,
input [7:0] Green,
input [7:0] Blue,
input HSync,
input VSync,
input VideoEnable,
output [3:0] TMDS_out_P,
output [3:0] TMDS_out_N
);
wire [9:0] EncRed;
wire [9:0] EncGreen;
wire [9:0] EncBlue;
wire SerOutRed;
wire SerOutGreen;
wire SerOutBlue;
wire SerOutClock;
Component_encoder CE_Red(.Data(Red), .C0(1'b0), .C1(1'b0), .DE(VideoEnable), .PixClk(PixelClk), .OutEncoded(EncRed));
Component_encoder CE_Green(.Data(Green), .C0(1'b0), .C1(1'b0), .DE(VideoEnable), .PixClk(PixelClk), .OutEncoded(EncGreen));
Component_encoder CE_Blue(.Data(Blue), .C0(HSync), .C1(VSync), .DE(VideoEnable), .PixClk(PixelClk), .OutEncoded(EncBlue));
Serializer_10_1 SER_Red(.Data(EncRed), .Clk_10(PixelClk10), .Clk_2(PixelClk2), .Strobe(SerDesStrobe), .Out(SerOutRed));
Serializer_10_1 SER_Green(.Data(EncGreen), .Clk_10(PixelClk10), .Clk_2(PixelClk2), .Strobe(SerDesStrobe), .Out(SerOutGreen));
Serializer_10_1 SER_Blue(.Data(EncBlue), .Clk_10(PixelClk10), .Clk_2(PixelClk2), .Strobe(SerDesStrobe), .Out(SerOutBlue));
Serializer_10_1 SER_Clock(.Data(10'b0000011111), .Clk_10(PixelClk10), .Clk_2(PixelClk2), .Strobe(SerDesStrobe), .Out(SerOutClock));
OBUFDS OutBufDif_B(.I(SerOutBlue), .O(TMDS_out_P[0]), .OB(TMDS_out_N[0]));
OBUFDS OutBufDif_G(.I(SerOutGreen), .O(TMDS_out_P[1]), .OB(TMDS_out_N[1]));
OBUFDS OutBufDif_R(.I(SerOutRed), .O(TMDS_out_P[2]), .OB(TMDS_out_N[2]));
OBUFDS OutBufDif_C(.I(SerOutClock), .O(TMDS_out_P[3]), .OB(TMDS_out_N[3]));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__OR4_PP_SYMBOL_V
`define SKY130_FD_SC_HS__OR4_PP_SYMBOL_V
/**
* or4: 4-input OR.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__or4 (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
input D ,
output X ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__OR4_PP_SYMBOL_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (clk);
input clk;
reg [2:0] a;
reg [2:0] b;
reg q;
f6 f6 (/*AUTOINST*/
// Outputs
.q (q),
// Inputs
.a (a[2:0]),
.b (b[2:0]),
.clk (clk));
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
a <= 3'b000;
b <= 3'b100;
end
if (cyc==2) begin
a <= 3'b011;
b <= 3'b001;
if (q != 1'b0) $stop;
end
if (cyc==3) begin
a <= 3'b011;
b <= 3'b011;
if (q != 1'b0) $stop;
end
if (cyc==9) begin
if (q != 1'b1) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module f6 (a, b, clk, q);
input [2:0] a;
input [2:0] b;
input clk;
output q;
reg out;
function func6;
reg result;
input [5:0] src;
begin
if (src[5:0] == 6'b011011) begin
result = 1'b1;
end
else begin
result = 1'b0;
end
func6 = result;
end
endfunction
wire [5:0] w6 = {a, b};
always @(posedge clk) begin
out <= func6(w6);
end
assign q = out;
endmodule
|
// amm_master_qsys_with_pcie_mm_interconnect_0_avalon_st_adapter_001.v
// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module amm_master_qsys_with_pcie_mm_interconnect_0_avalon_st_adapter_001 #(
parameter inBitsPerSymbol = 66,
parameter inUsePackets = 0,
parameter inDataWidth = 66,
parameter inChannelWidth = 0,
parameter inErrorWidth = 0,
parameter inUseEmptyPort = 0,
parameter inUseValid = 1,
parameter inUseReady = 1,
parameter inReadyLatency = 0,
parameter outDataWidth = 66,
parameter outChannelWidth = 0,
parameter outErrorWidth = 1,
parameter outUseEmptyPort = 0,
parameter outUseValid = 1,
parameter outUseReady = 1,
parameter outReadyLatency = 0
) (
input wire in_clk_0_clk, // in_clk_0.clk
input wire in_rst_0_reset, // in_rst_0.reset
input wire [65:0] in_0_data, // in_0.data
input wire in_0_valid, // .valid
output wire in_0_ready, // .ready
output wire [65:0] out_0_data, // out_0.data
output wire out_0_valid, // .valid
input wire out_0_ready, // .ready
output wire [0:0] out_0_error // .error
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (inBitsPerSymbol != 66)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inbitspersymbol_check ( .error(1'b1) );
end
if (inUsePackets != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusepackets_check ( .error(1'b1) );
end
if (inDataWidth != 66)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
indatawidth_check ( .error(1'b1) );
end
if (inChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inchannelwidth_check ( .error(1'b1) );
end
if (inErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inerrorwidth_check ( .error(1'b1) );
end
if (inUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseemptyport_check ( .error(1'b1) );
end
if (inUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusevalid_check ( .error(1'b1) );
end
if (inUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseready_check ( .error(1'b1) );
end
if (inReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inreadylatency_check ( .error(1'b1) );
end
if (outDataWidth != 66)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outdatawidth_check ( .error(1'b1) );
end
if (outChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outchannelwidth_check ( .error(1'b1) );
end
if (outErrorWidth != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outerrorwidth_check ( .error(1'b1) );
end
if (outUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseemptyport_check ( .error(1'b1) );
end
if (outUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outusevalid_check ( .error(1'b1) );
end
if (outUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseready_check ( .error(1'b1) );
end
if (outReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
amm_master_qsys_with_pcie_mm_interconnect_0_avalon_st_adapter_001_error_adapter_0 error_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_error (out_0_error) // .error
);
endmodule
|
//Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
//Date : Tue Sep 19 00:28:00 2017
//Host : DarkCube running 64-bit major release (build 9200)
//Command : generate_target bd_c3fe_wrapper.bd
//Design : bd_c3fe_wrapper
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module bd_c3fe_wrapper
(SLOT_0_AXI_araddr,
SLOT_0_AXI_arready,
SLOT_0_AXI_arvalid,
SLOT_0_AXI_awaddr,
SLOT_0_AXI_awready,
SLOT_0_AXI_awvalid,
SLOT_0_AXI_bready,
SLOT_0_AXI_bresp,
SLOT_0_AXI_bvalid,
SLOT_0_AXI_rdata,
SLOT_0_AXI_rready,
SLOT_0_AXI_rresp,
SLOT_0_AXI_rvalid,
SLOT_0_AXI_wdata,
SLOT_0_AXI_wready,
SLOT_0_AXI_wstrb,
SLOT_0_AXI_wvalid,
clk,
resetn);
input [8:0]SLOT_0_AXI_araddr;
input SLOT_0_AXI_arready;
input SLOT_0_AXI_arvalid;
input [8:0]SLOT_0_AXI_awaddr;
input SLOT_0_AXI_awready;
input SLOT_0_AXI_awvalid;
input SLOT_0_AXI_bready;
input [1:0]SLOT_0_AXI_bresp;
input SLOT_0_AXI_bvalid;
input [31:0]SLOT_0_AXI_rdata;
input SLOT_0_AXI_rready;
input [1:0]SLOT_0_AXI_rresp;
input SLOT_0_AXI_rvalid;
input [31:0]SLOT_0_AXI_wdata;
input SLOT_0_AXI_wready;
input [3:0]SLOT_0_AXI_wstrb;
input SLOT_0_AXI_wvalid;
input clk;
input resetn;
wire [8:0]SLOT_0_AXI_araddr;
wire SLOT_0_AXI_arready;
wire SLOT_0_AXI_arvalid;
wire [8:0]SLOT_0_AXI_awaddr;
wire SLOT_0_AXI_awready;
wire SLOT_0_AXI_awvalid;
wire SLOT_0_AXI_bready;
wire [1:0]SLOT_0_AXI_bresp;
wire SLOT_0_AXI_bvalid;
wire [31:0]SLOT_0_AXI_rdata;
wire SLOT_0_AXI_rready;
wire [1:0]SLOT_0_AXI_rresp;
wire SLOT_0_AXI_rvalid;
wire [31:0]SLOT_0_AXI_wdata;
wire SLOT_0_AXI_wready;
wire [3:0]SLOT_0_AXI_wstrb;
wire SLOT_0_AXI_wvalid;
wire clk;
wire resetn;
bd_c3fe bd_c3fe_i
(.SLOT_0_AXI_araddr(SLOT_0_AXI_araddr),
.SLOT_0_AXI_arready(SLOT_0_AXI_arready),
.SLOT_0_AXI_arvalid(SLOT_0_AXI_arvalid),
.SLOT_0_AXI_awaddr(SLOT_0_AXI_awaddr),
.SLOT_0_AXI_awready(SLOT_0_AXI_awready),
.SLOT_0_AXI_awvalid(SLOT_0_AXI_awvalid),
.SLOT_0_AXI_bready(SLOT_0_AXI_bready),
.SLOT_0_AXI_bresp(SLOT_0_AXI_bresp),
.SLOT_0_AXI_bvalid(SLOT_0_AXI_bvalid),
.SLOT_0_AXI_rdata(SLOT_0_AXI_rdata),
.SLOT_0_AXI_rready(SLOT_0_AXI_rready),
.SLOT_0_AXI_rresp(SLOT_0_AXI_rresp),
.SLOT_0_AXI_rvalid(SLOT_0_AXI_rvalid),
.SLOT_0_AXI_wdata(SLOT_0_AXI_wdata),
.SLOT_0_AXI_wready(SLOT_0_AXI_wready),
.SLOT_0_AXI_wstrb(SLOT_0_AXI_wstrb),
.SLOT_0_AXI_wvalid(SLOT_0_AXI_wvalid),
.clk(clk),
.resetn(resetn));
endmodule
|
/*
* Copyright 2018-2022 F4PGA Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
module RAM_TEST #(
parameter ADDR_WIDTH = 6,
parameter DATA_WIDTH = 1,
parameter IS_DUAL_PORT = 1,
parameter RANDOM_ITERATION_PER_LOOP = 10,
parameter LFSR_WIDTH = 16,
parameter LFSR_POLY = 16'hD008,
// How much to increment the address to move 1 full data width.
parameter ADDRESS_STEP = 1,
// Max address for this memory
parameter MAX_ADDRESS = 63
) (
input rst,
input clk,
// Memory connection
input [DATA_WIDTH-1:0] read_data,
output reg [DATA_WIDTH-1:0] write_data,
output reg write_enable,
output reg [ADDR_WIDTH-1:0] read_address,
output reg [ADDR_WIDTH-1:0] write_address,
// INIT ROM
// When the memory is first initialized, it is expected to match the ROM
// port.
input [DATA_WIDTH-1:0] rom_read_data,
output reg [ADDR_WIDTH-1:0] rom_read_address,
// When an iteration is complete, success will be 1 for 1 cycle
output reg loop_complete,
// If an error occurs during a test, error will be 1 for each cycle
// with an error.
output reg error,
// error_state will contain the state of test FSM when the error occured.
output reg [7:0] error_state,
// error_address will be the read address where the error occurred.
output reg [ADDR_WIDTH-1:0] error_address,
// expected_data will be the read value expected.
output reg [DATA_WIDTH-1:0] expected_data,
// actual_data will be the read value read.
output reg [DATA_WIDTH-1:0] actual_data
);
reg [7:0] state;
reg [DATA_WIDTH-1:0] test_value;
reg [$clog2(RANDOM_ITERATION_PER_LOOP)-1:0] rand_count;
localparam START = 8'd1,
VERIFY_INIT = 8'd2,
WRITE_ZEROS = 8'd3,
VERIFY_ZEROS = 8'd4,
WRITE_ONES = 8'd5,
VERIFY_ONES = 8'd6,
WRITE_10 = 8'd7,
VERIFY_10 = 8'd8,
WRITE_01 = 8'd9,
VERIFY_01 = 8'd10,
WRITE_RANDOM = 8'd11,
VERIFY_RANDOM = 8'd12,
RESTART_LOOP = 8'd13;
reg pause;
reg lfsr_reset;
reg wait_for_lfsr_reset;
reg [LFSR_WIDTH-1:0] lfsr_seed;
reg [LFSR_WIDTH-1:0] start_lfsr_seed;
wire [LFSR_WIDTH-1:0] rand_data;
LFSR #(
.WIDTH(LFSR_WIDTH),
.POLY(LFSR_POLY)
) lfsr (
.rst(lfsr_reset),
.clk(clk),
.seed(lfsr_seed),
.r(rand_data)
);
always @(posedge clk) begin
if(rst) begin
state <= START;
error <= 0;
write_enable <= 0;
lfsr_reset <= 1;
lfsr_seed <= 1;
end else begin
case(state)
START: begin
lfsr_reset <= 0;
state <= VERIFY_INIT;
read_address <= 0;
rom_read_address <= 0;
write_enable <= 0;
error <= 0;
end
VERIFY_INIT: begin
if(rom_read_data != read_data) begin
error <= 1;
error_state <= state;
error_address <= read_address;
expected_data <= rom_read_data;
actual_data <= read_data;
end else begin
error <= 0;
end
if(read_address + ADDRESS_STEP <= MAX_ADDRESS) begin
read_address <= read_address + ADDRESS_STEP;
rom_read_address <= rom_read_address + ADDRESS_STEP;
end else begin
read_address <= 0;
write_address <= 0;
write_enable <= 1;
write_data <= {DATA_WIDTH{1'b0}};
state <= WRITE_ZEROS;
end
end
WRITE_ZEROS: begin
loop_complete <= 0;
if(write_address + ADDRESS_STEP <= MAX_ADDRESS) begin
write_address <= write_address + ADDRESS_STEP;
end else begin
read_address <= 0;
write_address <= 0;
write_enable <= 0;
pause <= 1;
state <= VERIFY_ZEROS;
end
end
VERIFY_ZEROS: begin
if(pause) begin
pause <= 0;
end else begin
if(read_data != {DATA_WIDTH{1'b0}}) begin
error <= 1;
error_state <= state;
error_address <= read_address;
expected_data <= {DATA_WIDTH{1'b0}};
actual_data <= read_data;
end else begin
error <= 0;
end
if(read_address + ADDRESS_STEP <= MAX_ADDRESS) begin
read_address <= read_address + ADDRESS_STEP;
end else begin
read_address <= 0;
write_address <= 0;
write_enable <= 1;
write_data <= {DATA_WIDTH{1'b1}};
state <= WRITE_ONES;
end
end
end
WRITE_ONES: begin
// If dual port, data should still be zero.
if(IS_DUAL_PORT) begin
if(read_data != {DATA_WIDTH{1'b0}}) begin
error <= 1;
error_state <= state;
error_address <= read_address;
expected_data <= {DATA_WIDTH{1'b0}};
actual_data <= read_data;
end else begin
error <= 0;
end
end else begin
if(read_data != {DATA_WIDTH{1'b1}}) begin
error <= 1;
error_state <= state;
error_address <= read_address;
expected_data <= {DATA_WIDTH{1'b1}};
actual_data <= read_data;
end else begin
error <= 0;
end
end
if(write_address + ADDRESS_STEP <= MAX_ADDRESS) begin
read_address <= read_address + ADDRESS_STEP;
write_address <= write_address + ADDRESS_STEP;
end else begin
read_address <= 0;
write_address <= 0;
write_enable <= 0;
state <= VERIFY_ONES;
pause <= 1;
end
end
VERIFY_ONES: begin
if(pause) begin
pause <= 0;
end else begin
if(read_data != {DATA_WIDTH{1'b1}}) begin
error <= 1;
error_state <= state;
error_address <= read_address;
expected_data <= {DATA_WIDTH{1'b1}};
actual_data <= read_data;
end else begin
error <= 0;
end
if(read_address + ADDRESS_STEP <= MAX_ADDRESS) begin
read_address <= read_address + ADDRESS_STEP;
end else begin
state <= WRITE_RANDOM;
write_enable <= 1;
write_address <= 0;
lfsr_seed <= rand_data;
write_data <= rand_data[DATA_WIDTH-1:0];
read_address <= 0;
end
end
end
WRITE_RANDOM: begin
if(write_address + ADDRESS_STEP <= MAX_ADDRESS) begin
write_address <= write_address + ADDRESS_STEP;
write_data <= rand_data[DATA_WIDTH-1:0];
end else begin
read_address <= 0;
write_address <= 0;
write_enable <= 0;
state <= VERIFY_RANDOM;
// Return LFSR to state at beginning of WRITE_RANDOM.
lfsr_reset <= 1;
wait_for_lfsr_reset <= 1;
end
end
VERIFY_RANDOM: begin
if(wait_for_lfsr_reset) begin
wait_for_lfsr_reset <= 0;
lfsr_reset <= 1;
end else begin
lfsr_reset <= 0;
if(read_data != rand_data[DATA_WIDTH-1:0]) begin
error <= 1;
error_state <= state;
error_address <= read_address;
expected_data <= rand_data[DATA_WIDTH-1:0];
actual_data <= read_data;
end else begin
error <= 0;
end
if(read_address + ADDRESS_STEP <= MAX_ADDRESS) begin
read_address <= read_address + ADDRESS_STEP;
end else begin
state <= RESTART_LOOP;
end
end
end
RESTART_LOOP: begin
loop_complete <= 1;
error <= 0;
read_address <= 0;
write_address <= 0;
write_enable <= 1;
write_data <= {DATA_WIDTH{1'b0}};
state <= WRITE_ZEROS;
end
default: begin
state <= START;
error <= 0;
end
endcase
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A41O_FUNCTIONAL_V
`define SKY130_FD_SC_MS__A41O_FUNCTIONAL_V
/**
* a41o: 4-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3 & A4) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__a41o (
X ,
A1,
A2,
A3,
A4,
B1
);
// Module ports
output X ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Local signals
wire and0_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2, A3, A4 );
or or0 (or0_out_X, and0_out, B1 );
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A41O_FUNCTIONAL_V |
/*
*
* Copyright (c) 2011-2012 [email protected]
*
*
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`timescale 1ns/1ps
module fpgaminer_top (
input CLK_100MHZ
);
//// Configuration Options
//
// Frequency (MHz) of the incoming clock (CLK_100MHZ)
localparam INPUT_CLOCK_FREQUENCY = 100;
// What frequency of operation Synthesis and P&R should target. If
// ISE can meet timing requirements, then this is the guaranteed
// frequency of operation.
localparam SYNTHESIS_FREQUENCY = 50;
// What frequency the FPGA should boot-up to.
localparam BOOTUP_FREQUENCY = 50;
// What is the maximum allowed overclock. User will not be able to set
// clock frequency above this threshold.
localparam MAXIMUM_FREQUENCY = 100;
//// Clock Buffer
`ifndef SIM
wire clkin_100MHZ;
IBUFG clkin1_buf ( .I (CLK_100MHZ), .O (clkin_100MHZ));
`endif
////
reg [255:0] midstate = 0;
reg [95:0] data = 0;
reg [30:0] nonce = 31'd254, nonce2 = 31'd0;
//// PLL
wire hash_clk;
wire dcm_progdata, dcm_progen, dcm_progdone;
`ifndef SIM
dynamic_clock # (
.INPUT_FREQUENCY (INPUT_CLOCK_FREQUENCY),
.SYNTHESIS_FREQUENCY (SYNTHESIS_FREQUENCY)
) dynamic_clk_blk (
.CLK_IN1 (clkin_100MHZ),
.CLK_OUT1 (hash_clk),
.PROGCLK (clkin_100MHZ),
.PROGDATA (dcm_progdata),
.PROGEN (dcm_progen),
.PROGDONE (dcm_progdone)
);
`else
assign hash_clk = CLK_100MHZ;
`endif
//// Dual-Hasher
wire [255:0] hash0, hash1;
wire [31:0] hash2_w0, hash2_w1;
dual_sha256_transform first_hash_blk (
.clk (hash_clk),
.rx_state (midstate),
.rx_nonce (nonce),
.rx_input (data),
.tx_hash0 (hash0),
.tx_hash1 (hash1)
);
second_sha256_transform second_hash0_blk (
.clk (hash_clk),
.rx_input ({256'h0000010000000000000000000000000000000000000000000000000080000000, hash0}),
.tx_hash (hash2_w0)
);
second_sha256_transform second_hash1_blk (
.clk (hash_clk),
.rx_input ({256'h0000010000000000000000000000000000000000000000000000000080000000, hash1}),
.tx_hash (hash2_w1)
);
//// Communication Module
wire comm_new_work;
wire [255:0] comm_midstate;
wire [95:0] comm_data;
reg is_golden_ticket = 1'b0;
reg [31:0] golden_nonce;
reg [3:0] golden_ticket_buf = 4'b0;
reg [127:0] golden_nonce_buf;
`ifndef SIM
jtag_comm # (
.INPUT_FREQUENCY (INPUT_CLOCK_FREQUENCY),
.MAXIMUM_FREQUENCY (MAXIMUM_FREQUENCY),
.INITIAL_FREQUENCY (BOOTUP_FREQUENCY)
) comm_blk (
.rx_hash_clk (hash_clk),
.rx_new_nonce (golden_ticket_buf[3]),
.rx_golden_nonce (golden_nonce_buf[127:96]),
.tx_new_work (comm_new_work),
.tx_midstate (comm_midstate),
.tx_data (comm_data),
.rx_dcm_progclk (clkin_100MHZ),
.tx_dcm_progdata (dcm_progdata),
.tx_dcm_progen (dcm_progen),
.rx_dcm_progdone (dcm_progdone)
);
`endif
//// Control Unit
// NOTE: When the hashers first start churning on new work, results
// will be invalid for ~254 cycles. Since returning invalid results is
// not very detrimental (controlling software double checks results)
// we sacrifice a small amount of accuracy in exchange for simple
// logic.
reg reset = 1'b1;
always @ (posedge hash_clk)
begin
// Counters
if (reset | comm_new_work)
begin
nonce <= 31'd127;
nonce2 <= 31'd0;
end
else
begin
nonce <= nonce + 31'd1;
nonce2 <= nonce2 + 31'd1;
end
`ifndef SIM
// Give new data to the hasher
midstate <= comm_midstate;
data <= comm_data[95:0];
`endif
// Clear the reset signal when we get new work
if (comm_new_work)
reset <= 1'b0;
// Stop hashing if we've run out of nonces to check
else if (nonce2 == 31'h7FFFFFFF)
reset <= 1'b1;
// Check to see if the last hash generated is valid.
if (hash2_w0 == 32'hA41F32E7)
begin
is_golden_ticket <= 1'b1;
golden_nonce <= {1'b0, nonce2};
end
else if (hash2_w1 == 32'hA41F32E7)
begin
is_golden_ticket <= 1'b1;
golden_nonce <= {1'b1, nonce2};
end
else
is_golden_ticket <= 1'b0;
golden_ticket_buf <= {golden_ticket_buf[2:0], is_golden_ticket};
golden_nonce_buf <= {golden_nonce_buf[95:0], golden_nonce};
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2015 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire input_signal = crc[0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire output_signal; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.output_signal (output_signal),
// Inputs
.input_signal (input_signal));
// Aggregate outputs into a single result vector
wire [63:0] result = {63'h0, output_signal};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= '0;
end
else if (cyc<10) begin
sum <= '0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h765b2e12b25ec97b
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (
input input_signal,
output output_signal
);
// bug872
// verilator lint_off UNOPTFLAT
wire some_signal[1:0][1:0];
assign some_signal[0][0] = input_signal;
assign some_signal[0][1] = some_signal[0][0];
assign some_signal[1][0] = some_signal[0][1];
assign some_signal[1][1] = some_signal[1][0];
assign output_signal = some_signal[1][1];
endmodule
|
//*****************************************************************************
// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 3.7
// \ \ Application : MIG
// / / Filename : bank_common.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : Virtex-6
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// Common block for the bank machines. Bank_common computes various
// items that cross all of the bank machines. These values are then
// fed back to all of the bank machines. Most of these values have
// to do with a row machine figuring out where it belongs in a queue.
`timescale 1 ps / 1 ps
module bank_common #
(
parameter TCQ = 100,
parameter BM_CNT_WIDTH = 2,
parameter LOW_IDLE_CNT = 1,
parameter nBANK_MACHS = 4,
parameter nCK_PER_CLK = 2,
parameter nOP_WAIT = 0,
parameter nRFC = 44,
parameter RANK_WIDTH = 2,
parameter RANKS = 4,
parameter CWL = 5, //Added to fix CR #528228
parameter tZQCS = 64
)
(/*AUTOARG*/
// Outputs
accept_internal_r, accept_ns, accept, periodic_rd_insert,
periodic_rd_ack_r, accept_req, rb_hit_busy_cnt, idle_cnt, order_cnt,
adv_order_q, bank_mach_next, op_exit_grant, low_idle_cnt_r, was_wr,
was_priority, maint_wip_r, maint_idle, force_io_config_rd_r,
insert_maint_r,
// Inputs
clk, rst, idle_ns, dfi_init_complete, periodic_rd_r, use_addr,
rb_hit_busy_r, idle_r, ordered_r, ordered_issued, head_r, end_rtp,
passing_open_bank, op_exit_req, start_pre_wait, cmd, hi_priority,
maint_req_r, maint_zq_r, maint_hit, bm_end, io_config_valid_r,
io_config, slot_0_present, slot_1_present
);
function integer clogb2 (input integer size); // ceiling logb2
begin
size = size - 1;
for (clogb2=1; size>1; clogb2=clogb2+1)
size = size >> 1;
end
endfunction // clogb2
localparam ZERO = 0;
localparam ONE = 1;
localparam [BM_CNT_WIDTH-1:0] BM_CNT_ZERO = ZERO[0+:BM_CNT_WIDTH];
localparam [BM_CNT_WIDTH-1:0] BM_CNT_ONE = ONE[0+:BM_CNT_WIDTH];
input clk;
input rst;
input [nBANK_MACHS-1:0] idle_ns;
input dfi_init_complete;
wire accept_internal_ns = dfi_init_complete && |idle_ns;
output reg accept_internal_r;
always @(posedge clk) accept_internal_r <= accept_internal_ns;
wire periodic_rd_ack_ns;
wire accept_ns_lcl = accept_internal_ns && ~periodic_rd_ack_ns;
output wire accept_ns;
assign accept_ns = accept_ns_lcl;
reg accept_r;
always @(posedge clk) accept_r <= #TCQ accept_ns_lcl;
// Wire to user interface informing user that the request has been accepted.
output wire accept;
assign accept = accept_r;
`ifdef MC_SVA
property none_idle;
@(posedge clk) (dfi_init_complete && ~|idle_r);
endproperty
all_bank_machines_busy: cover property (none_idle);
`endif
// periodic_rd_insert tells everyone to mux in the periodic read.
input periodic_rd_r;
reg periodic_rd_ack_r_lcl;
wire periodic_rd_insert_lcl = periodic_rd_r && ~periodic_rd_ack_r_lcl;
output wire periodic_rd_insert;
assign periodic_rd_insert = periodic_rd_insert_lcl;
// periodic_rd_ack_r acknowledges that the read has been accepted
// into the queue.
assign periodic_rd_ack_ns = periodic_rd_insert_lcl && accept_internal_ns;
always @(posedge clk) periodic_rd_ack_r_lcl <= #TCQ periodic_rd_ack_ns;
output wire periodic_rd_ack_r;
assign periodic_rd_ack_r = periodic_rd_ack_r_lcl;
// accept_req tells all q entries that a request has been accepted.
input use_addr;
wire accept_req_lcl = periodic_rd_ack_r_lcl || (accept_r && use_addr);
output wire accept_req;
assign accept_req = accept_req_lcl;
// Count how many non idle bank machines hit on the rank and bank.
input [nBANK_MACHS-1:0] rb_hit_busy_r;
output reg [BM_CNT_WIDTH-1:0] rb_hit_busy_cnt;
integer i;
always @(/*AS*/rb_hit_busy_r) begin
rb_hit_busy_cnt = BM_CNT_ZERO;
for (i = 0; i < nBANK_MACHS; i = i + 1)
if (rb_hit_busy_r[i]) rb_hit_busy_cnt = rb_hit_busy_cnt + BM_CNT_ONE;
end
// Count the number of idle bank machines.
input [nBANK_MACHS-1:0] idle_r;
output reg [BM_CNT_WIDTH-1:0] idle_cnt;
always @(/*AS*/idle_r) begin
idle_cnt = BM_CNT_ZERO;
for (i = 0; i < nBANK_MACHS; i = i + 1)
if (idle_r[i]) idle_cnt = idle_cnt + BM_CNT_ONE;
end
// Count the number of bank machines in the ordering queue.
input [nBANK_MACHS-1:0] ordered_r;
output reg [BM_CNT_WIDTH-1:0] order_cnt;
always @(/*AS*/ordered_r) begin
order_cnt = BM_CNT_ZERO;
for (i = 0; i < nBANK_MACHS; i = i + 1)
if (ordered_r[i]) order_cnt = order_cnt + BM_CNT_ONE;
end
input [nBANK_MACHS-1:0] ordered_issued;
output wire adv_order_q;
assign adv_order_q = |ordered_issued;
// Figure out which bank machine is going to accept the next request.
input [nBANK_MACHS-1:0] head_r;
wire [nBANK_MACHS-1:0] next = idle_r & head_r;
output reg[BM_CNT_WIDTH-1:0] bank_mach_next;
always @(/*AS*/next) begin
bank_mach_next = BM_CNT_ZERO;
for (i = 0; i <= nBANK_MACHS-1; i = i + 1)
if (next[i]) bank_mach_next = i[BM_CNT_WIDTH-1:0];
end
input [nBANK_MACHS-1:0] end_rtp;
input [nBANK_MACHS-1:0] passing_open_bank;
input [nBANK_MACHS-1:0] op_exit_req;
output wire [nBANK_MACHS-1:0] op_exit_grant;
output reg low_idle_cnt_r = 1'b0;
input [nBANK_MACHS-1:0] start_pre_wait;
generate
// In support of open page mode, the following logic
// keeps track of how many "idle" bank machines there
// are. In this case, idle means a bank machine is on
// the idle list, or is in the process of precharging and
// will soon be idle.
if (nOP_WAIT == 0) begin : op_mode_disabled
assign op_exit_grant = {nBANK_MACHS{1'b0}};
end
else begin : op_mode_enabled
reg [BM_CNT_WIDTH:0] idle_cnt_r;
reg [BM_CNT_WIDTH:0] idle_cnt_ns;
always @(/*AS*/accept_req_lcl or idle_cnt_r or passing_open_bank
or rst or start_pre_wait)
if (rst) idle_cnt_ns = nBANK_MACHS;
else begin
idle_cnt_ns = idle_cnt_r - accept_req_lcl;
for (i = 0; i <= nBANK_MACHS-1; i = i + 1) begin
idle_cnt_ns = idle_cnt_ns + passing_open_bank[i];
end
idle_cnt_ns = idle_cnt_ns + |start_pre_wait;
end
always @(posedge clk) idle_cnt_r <= #TCQ idle_cnt_ns;
wire low_idle_cnt_ns = (idle_cnt_ns <= LOW_IDLE_CNT[0+:BM_CNT_WIDTH]);
always @(posedge clk) low_idle_cnt_r <= #TCQ low_idle_cnt_ns;
// This arbiter determines which bank machine should transition
// from open page wait to precharge. Ideally, this process
// would take the oldest waiter, but don't have any reasonable
// way to implement that. Instead, just use simple round robin
// arb with the small enhancement that the most recent bank machine
// to enter open page wait is given lowest priority in the arbiter.
wire upd_last_master = |end_rtp; // should be one bit set at most
round_robin_arb #
(.WIDTH (nBANK_MACHS))
op_arb0
(.grant_ns (op_exit_grant[nBANK_MACHS-1:0]),
.grant_r (),
.upd_last_master (upd_last_master),
.current_master (end_rtp[nBANK_MACHS-1:0]),
.clk (clk),
.rst (rst),
.req (op_exit_req[nBANK_MACHS-1:0]),
.disable_grant (1'b0));
end
endgenerate
// Register some command information. This information will be used
// by the bank machines to figure out if there is something behind it
// in the queue that require hi priority.
input [2:0] cmd;
output reg was_wr;
always @(posedge clk) was_wr <= #TCQ
cmd[0] && ~(periodic_rd_r && ~periodic_rd_ack_r_lcl);
input hi_priority;
output reg was_priority;
always @(posedge clk) was_priority <= #TCQ hi_priority;
// DRAM maintenance (refresh and ZQ) controller
input maint_req_r;
reg maint_wip_r_lcl;
output wire maint_wip_r;
assign maint_wip_r = maint_wip_r_lcl;
wire maint_idle_lcl;
output wire maint_idle;
assign maint_idle = maint_idle_lcl;
input maint_zq_r;
input [nBANK_MACHS-1:0] maint_hit;
input [nBANK_MACHS-1:0] bm_end;
input io_config_valid_r;
input [RANK_WIDTH:0] io_config;
wire start_maint;
wire maint_end;
output wire force_io_config_rd_r;
generate begin : maint_controller
// Idle when not (maintenance work in progress (wip), OR maintenance
// starting tick).
assign maint_idle_lcl = ~(maint_req_r || maint_wip_r_lcl);
// Maintenance work in progress starts with maint_reg_r tick, terminated
// with maint_end tick. maint_end tick is generated by the RFC ZQ timer below.
wire maint_wip_ns =
~rst && ~maint_end && (maint_wip_r_lcl || maint_req_r);
always @(posedge clk) maint_wip_r_lcl <= #TCQ maint_wip_ns;
// Keep track of which bank machines hit on the maintenance request
// when the request is made. As bank machines complete, an assertion
// of the bm_end signal clears the correspoding bit in the
// maint_hit_busies_r vector. Eventually, all bits should clear and
// the maintenance operation will proceed. ZQ hits on all
// non idle banks. Refresh hits only on non idle banks with the same rank as
// the refresh request.
wire [nBANK_MACHS-1:0] clear_vector = {nBANK_MACHS{rst}} | bm_end;
wire [nBANK_MACHS-1:0] maint_zq_hits = {nBANK_MACHS{maint_idle_lcl}} &
(maint_hit | {nBANK_MACHS{maint_zq_r}}) & ~idle_ns;
reg [nBANK_MACHS-1:0] maint_hit_busies_r;
wire [nBANK_MACHS-1:0] maint_hit_busies_ns =
~clear_vector & (maint_hit_busies_r | maint_zq_hits);
always @(posedge clk) maint_hit_busies_r <= #TCQ maint_hit_busies_ns;
// Look to see if io_config is in read mode.
wire io_config_rd = io_config_valid_r && ~io_config[RANK_WIDTH];
//Added to fix CR #528228
//Adding extra register stages to delay the maintainence
//commands from beign applied on the dfi interface bus.
//This is done to compensate the delays added to ODT logic
//in the mem_infc module.
reg io_config_rd_r;
reg io_config_rd_r1;
wire io_config_rd_delayed;
always @(posedge clk) begin
io_config_rd_r <= io_config_rd;
io_config_rd_r1 <= io_config_rd_r;
end
assign io_config_rd_delayed = (CWL >= 7) ? io_config_rd_r1:
io_config_rd_r;
// Queue is clear of requests conflicting with maintenance.
wire maint_clear = ~maint_idle_lcl && ~|maint_hit_busies_ns;
// Force io_config to read mode for ZQ. This insures the DQ
// bus is hi Z.
reg force_io_config_rd_r_lcl;
wire force_io_config_rd_ns =
maint_clear && maint_zq_r && ~io_config_rd && ~force_io_config_rd_r_lcl;
always @(posedge clk) force_io_config_rd_r_lcl <=
#TCQ force_io_config_rd_ns;
assign force_io_config_rd_r = force_io_config_rd_r_lcl;
// Ready to start sending maintenance commands.
wire maint_rdy = maint_clear && (~maint_zq_r || io_config_rd_delayed);
reg maint_rdy_r1;
always @(posedge clk) maint_rdy_r1 <= #TCQ maint_rdy;
assign start_maint = maint_rdy && ~maint_rdy_r1;
end // block: maint_controller
endgenerate
// Figure out how many maintenance commands to send, and send them.
input [7:0] slot_0_present;
input [7:0] slot_1_present;
reg insert_maint_r_lcl;
output wire insert_maint_r;
assign insert_maint_r = insert_maint_r_lcl;
generate begin : generate_maint_cmds
// Count up how many slots are occupied. This tells
// us how many ZQ commands to send out.
reg [RANK_WIDTH:0] present_count;
wire [7:0] present = slot_0_present | slot_1_present;
always @(/*AS*/present) begin
present_count = {RANK_WIDTH{1'b0}};
for (i=0; i<8; i=i+1)
present_count = present_count + {{RANK_WIDTH{1'b0}}, present[i]};
end
// For refresh, there is only a single command sent. For
// ZQ, each rank present will receive a ZQ command. The counter
// below counts down the number of ranks present.
reg [RANK_WIDTH:0] send_cnt_ns;
reg [RANK_WIDTH:0] send_cnt_r;
always @(/*AS*/maint_zq_r or present_count or rst or send_cnt_r
or start_maint)
if (rst) send_cnt_ns = 4'b0;
else begin
send_cnt_ns = send_cnt_r;
if (start_maint && maint_zq_r) send_cnt_ns = present_count;
if (|send_cnt_ns)
send_cnt_ns = send_cnt_ns - ONE[RANK_WIDTH-1:0];
end
always @(posedge clk) send_cnt_r <= #TCQ send_cnt_ns;
// Insert a maintenance command for start_maint, or when the sent count
// is not zero.
wire insert_maint_ns = start_maint || |send_cnt_r;
always @(posedge clk) insert_maint_r_lcl <= #TCQ insert_maint_ns;
end // block: generate_maint_cmds
endgenerate
// RFC ZQ timer. Generates delay from refresh or ZQ command until
// the end of the maintenance operation.
// Compute values for RFC and ZQ periods.
localparam nRFC_CLKS = (nCK_PER_CLK == 1) ? nRFC : ((nRFC/2) + (nRFC%2));
localparam nZQCS_CLKS = (nCK_PER_CLK == 1) ? tZQCS : ((tZQCS/2) + (tZQCS%2));
localparam RFC_ZQ_TIMER_WIDTH = (nZQCS_CLKS > nRFC_CLKS)
? clogb2(nZQCS_CLKS + 1)
: clogb2(nRFC_CLKS + 1);
localparam THREE = 3;
generate begin : rfc_zq_timer
reg [RFC_ZQ_TIMER_WIDTH-1:0] rfc_zq_timer_ns;
reg [RFC_ZQ_TIMER_WIDTH-1:0] rfc_zq_timer_r;
always @(/*AS*/insert_maint_r_lcl or maint_zq_r
or rfc_zq_timer_r or rst) begin
rfc_zq_timer_ns = rfc_zq_timer_r;
if (rst) rfc_zq_timer_ns = {RFC_ZQ_TIMER_WIDTH{1'b0}};
else if (insert_maint_r_lcl) rfc_zq_timer_ns = maint_zq_r
? nZQCS_CLKS
: nRFC_CLKS;
else if (|rfc_zq_timer_r) rfc_zq_timer_ns =
rfc_zq_timer_r - ONE[RFC_ZQ_TIMER_WIDTH-1:0];
end
always @(posedge clk) rfc_zq_timer_r <= #TCQ rfc_zq_timer_ns;
// Based on rfc_zq_timer_r, figure out when to release any bank
// machines waiting to send an activate. Need to add two to the end count.
// One because the counter starts a state after the insert_refresh_r, and
// one more because bm_end to insert_refresh_r is one state shorter
// than bm_end to rts_row.
assign maint_end = (rfc_zq_timer_r == THREE[RFC_ZQ_TIMER_WIDTH-1:0]);
end // block: rfc_zq_timer
endgenerate
endmodule // bank_common
|
// megafunction wizard: %LPM_MULT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsquare
// ============================================================
// File Name: squarer.v
// Megafunction Name(s):
// altsquare
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.0 Build 262 08/18/2010 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module squarer (
dataa,
result);
input [39:0] dataa;
output [79:0] result;
wire [79:0] sub_wire0;
wire [79:0] result = sub_wire0[79:0];
altsquare altsquare_component (
.data (dataa),
.result (sub_wire0),
.aclr (1'b0),
.clock (1'b1),
.ena (1'b1));
defparam
altsquare_component.data_width = 40,
altsquare_component.lpm_type = "ALTSQUARE",
altsquare_component.pipeline = 0,
altsquare_component.representation = "SIGNED",
altsquare_component.result_width = 80;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AutoSizeResult NUMERIC "1"
// Retrieval info: PRIVATE: B_isConstant NUMERIC "0"
// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
// Retrieval info: PRIVATE: Latency NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SignedMult NUMERIC "1"
// Retrieval info: PRIVATE: USE_MULT NUMERIC "0"
// Retrieval info: PRIVATE: ValidConstant NUMERIC "0"
// Retrieval info: PRIVATE: WidthA NUMERIC "40"
// Retrieval info: PRIVATE: WidthB NUMERIC "40"
// Retrieval info: PRIVATE: WidthP NUMERIC "80"
// Retrieval info: PRIVATE: aclr NUMERIC "0"
// Retrieval info: PRIVATE: clken NUMERIC "0"
// Retrieval info: PRIVATE: optimize NUMERIC "0"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: DATA_WIDTH NUMERIC "40"
// Retrieval info: CONSTANT: LPM_TYPE STRING "ALTSQUARE"
// Retrieval info: CONSTANT: PIPELINE NUMERIC "0"
// Retrieval info: CONSTANT: REPRESENTATION STRING "SIGNED"
// Retrieval info: CONSTANT: RESULT_WIDTH NUMERIC "80"
// Retrieval info: USED_PORT: dataa 0 0 40 0 INPUT NODEFVAL "dataa[39..0]"
// Retrieval info: USED_PORT: result 0 0 80 0 OUTPUT NODEFVAL "result[79..0]"
// Retrieval info: CONNECT: @data 0 0 40 0 dataa 0 0 40 0
// Retrieval info: CONNECT: result 0 0 80 0 @result 0 0 80 0
// Retrieval info: GEN_FILE: TYPE_NORMAL squarer.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL squarer.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL squarer.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL squarer.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL squarer_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL squarer_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_5_interconnect_model.v
*
* Date : 2012-11
*
* Description : Mimics Top_interconnect Switch.
*
*****************************************************************************/
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_5_interconnect_model (
rstn,
sw_clk,
w_qos_gp0,
w_qos_gp1,
w_qos_hp0,
w_qos_hp1,
w_qos_hp2,
w_qos_hp3,
r_qos_gp0,
r_qos_gp1,
r_qos_hp0,
r_qos_hp1,
r_qos_hp2,
r_qos_hp3,
wr_ack_ddr_gp0,
wr_ack_ocm_gp0,
wr_data_gp0,
wr_addr_gp0,
wr_bytes_gp0,
wr_dv_ddr_gp0,
wr_dv_ocm_gp0,
rd_req_ddr_gp0,
rd_req_ocm_gp0,
rd_req_reg_gp0,
rd_addr_gp0,
rd_bytes_gp0,
rd_data_ddr_gp0,
rd_data_ocm_gp0,
rd_data_reg_gp0,
rd_dv_ddr_gp0,
rd_dv_ocm_gp0,
rd_dv_reg_gp0,
wr_ack_ddr_gp1,
wr_ack_ocm_gp1,
wr_data_gp1,
wr_addr_gp1,
wr_bytes_gp1,
wr_dv_ddr_gp1,
wr_dv_ocm_gp1,
rd_req_ddr_gp1,
rd_req_ocm_gp1,
rd_req_reg_gp1,
rd_addr_gp1,
rd_bytes_gp1,
rd_data_ddr_gp1,
rd_data_ocm_gp1,
rd_data_reg_gp1,
rd_dv_ddr_gp1,
rd_dv_ocm_gp1,
rd_dv_reg_gp1,
wr_ack_ddr_hp0,
wr_ack_ocm_hp0,
wr_data_hp0,
wr_addr_hp0,
wr_bytes_hp0,
wr_dv_ddr_hp0,
wr_dv_ocm_hp0,
rd_req_ddr_hp0,
rd_req_ocm_hp0,
rd_addr_hp0,
rd_bytes_hp0,
rd_data_ddr_hp0,
rd_data_ocm_hp0,
rd_dv_ddr_hp0,
rd_dv_ocm_hp0,
wr_ack_ddr_hp1,
wr_ack_ocm_hp1,
wr_data_hp1,
wr_addr_hp1,
wr_bytes_hp1,
wr_dv_ddr_hp1,
wr_dv_ocm_hp1,
rd_req_ddr_hp1,
rd_req_ocm_hp1,
rd_addr_hp1,
rd_bytes_hp1,
rd_data_ddr_hp1,
rd_data_ocm_hp1,
rd_dv_ddr_hp1,
rd_dv_ocm_hp1,
wr_ack_ddr_hp2,
wr_ack_ocm_hp2,
wr_data_hp2,
wr_addr_hp2,
wr_bytes_hp2,
wr_dv_ddr_hp2,
wr_dv_ocm_hp2,
rd_req_ddr_hp2,
rd_req_ocm_hp2,
rd_addr_hp2,
rd_bytes_hp2,
rd_data_ddr_hp2,
rd_data_ocm_hp2,
rd_dv_ddr_hp2,
rd_dv_ocm_hp2,
wr_ack_ddr_hp3,
wr_ack_ocm_hp3,
wr_data_hp3,
wr_addr_hp3,
wr_bytes_hp3,
wr_dv_ddr_hp3,
wr_dv_ocm_hp3,
rd_req_ddr_hp3,
rd_req_ocm_hp3,
rd_addr_hp3,
rd_bytes_hp3,
rd_data_ddr_hp3,
rd_data_ocm_hp3,
rd_dv_ddr_hp3,
rd_dv_ocm_hp3,
/* Goes to port 1 of DDR */
ddr_wr_ack_port1,
ddr_wr_dv_port1,
ddr_rd_req_port1,
ddr_rd_dv_port1,
ddr_wr_addr_port1,
ddr_wr_data_port1,
ddr_wr_bytes_port1,
ddr_rd_addr_port1,
ddr_rd_data_port1,
ddr_rd_bytes_port1,
ddr_wr_qos_port1,
ddr_rd_qos_port1,
/* Goes to port2 of DDR */
ddr_wr_ack_port2,
ddr_wr_dv_port2,
ddr_rd_req_port2,
ddr_rd_dv_port2,
ddr_wr_addr_port2,
ddr_wr_data_port2,
ddr_wr_bytes_port2,
ddr_rd_addr_port2,
ddr_rd_data_port2,
ddr_rd_bytes_port2,
ddr_wr_qos_port2,
ddr_rd_qos_port2,
/* Goes to port3 of DDR */
ddr_wr_ack_port3,
ddr_wr_dv_port3,
ddr_rd_req_port3,
ddr_rd_dv_port3,
ddr_wr_addr_port3,
ddr_wr_data_port3,
ddr_wr_bytes_port3,
ddr_rd_addr_port3,
ddr_rd_data_port3,
ddr_rd_bytes_port3,
ddr_wr_qos_port3,
ddr_rd_qos_port3,
/* Goes to port1 of OCM */
ocm_wr_qos_port1,
ocm_rd_qos_port1,
ocm_wr_dv_port1,
ocm_wr_data_port1,
ocm_wr_addr_port1,
ocm_wr_bytes_port1,
ocm_wr_ack_port1,
ocm_rd_req_port1,
ocm_rd_data_port1,
ocm_rd_addr_port1,
ocm_rd_bytes_port1,
ocm_rd_dv_port1,
/* Goes to port1 for RegMap */
reg_rd_qos_port1,
reg_rd_req_port1,
reg_rd_data_port1,
reg_rd_addr_port1,
reg_rd_bytes_port1,
reg_rd_dv_port1
);
`include "processing_system7_bfm_v2_0_5_local_params.v"
input rstn;
input sw_clk;
input [axi_qos_width-1:0] w_qos_gp0;
input [axi_qos_width-1:0] w_qos_gp1;
input [axi_qos_width-1:0] w_qos_hp0;
input [axi_qos_width-1:0] w_qos_hp1;
input [axi_qos_width-1:0] w_qos_hp2;
input [axi_qos_width-1:0] w_qos_hp3;
input [axi_qos_width-1:0] r_qos_gp0;
input [axi_qos_width-1:0] r_qos_gp1;
input [axi_qos_width-1:0] r_qos_hp0;
input [axi_qos_width-1:0] r_qos_hp1;
input [axi_qos_width-1:0] r_qos_hp2;
input [axi_qos_width-1:0] r_qos_hp3;
output [axi_qos_width-1:0] ocm_wr_qos_port1;
output [axi_qos_width-1:0] ocm_rd_qos_port1;
output wr_ack_ddr_gp0;
output wr_ack_ocm_gp0;
input[max_burst_bits-1:0] wr_data_gp0;
input[addr_width-1:0] wr_addr_gp0;
input[max_burst_bytes_width:0] wr_bytes_gp0;
input wr_dv_ddr_gp0;
input wr_dv_ocm_gp0;
input rd_req_ddr_gp0;
input rd_req_ocm_gp0;
input rd_req_reg_gp0;
input[addr_width-1:0] rd_addr_gp0;
input[max_burst_bytes_width:0] rd_bytes_gp0;
output[max_burst_bits-1:0] rd_data_ddr_gp0;
output[max_burst_bits-1:0] rd_data_ocm_gp0;
output[max_burst_bits-1:0] rd_data_reg_gp0;
output rd_dv_ddr_gp0;
output rd_dv_ocm_gp0;
output rd_dv_reg_gp0;
output wr_ack_ddr_gp1;
output wr_ack_ocm_gp1;
input[max_burst_bits-1:0] wr_data_gp1;
input[addr_width-1:0] wr_addr_gp1;
input[max_burst_bytes_width:0] wr_bytes_gp1;
input wr_dv_ddr_gp1;
input wr_dv_ocm_gp1;
input rd_req_ddr_gp1;
input rd_req_ocm_gp1;
input rd_req_reg_gp1;
input[addr_width-1:0] rd_addr_gp1;
input[max_burst_bytes_width:0] rd_bytes_gp1;
output[max_burst_bits-1:0] rd_data_ddr_gp1;
output[max_burst_bits-1:0] rd_data_ocm_gp1;
output[max_burst_bits-1:0] rd_data_reg_gp1;
output rd_dv_ddr_gp1;
output rd_dv_ocm_gp1;
output rd_dv_reg_gp1;
output wr_ack_ddr_hp0;
output wr_ack_ocm_hp0;
input[max_burst_bits-1:0] wr_data_hp0;
input[addr_width-1:0] wr_addr_hp0;
input[max_burst_bytes_width:0] wr_bytes_hp0;
input wr_dv_ddr_hp0;
input wr_dv_ocm_hp0;
input rd_req_ddr_hp0;
input rd_req_ocm_hp0;
input[addr_width-1:0] rd_addr_hp0;
input[max_burst_bytes_width:0] rd_bytes_hp0;
output[max_burst_bits-1:0] rd_data_ddr_hp0;
output[max_burst_bits-1:0] rd_data_ocm_hp0;
output rd_dv_ddr_hp0;
output rd_dv_ocm_hp0;
output wr_ack_ddr_hp1;
output wr_ack_ocm_hp1;
input[max_burst_bits-1:0] wr_data_hp1;
input[addr_width-1:0] wr_addr_hp1;
input[max_burst_bytes_width:0] wr_bytes_hp1;
input wr_dv_ddr_hp1;
input wr_dv_ocm_hp1;
input rd_req_ddr_hp1;
input rd_req_ocm_hp1;
input[addr_width-1:0] rd_addr_hp1;
input[max_burst_bytes_width:0] rd_bytes_hp1;
output[max_burst_bits-1:0] rd_data_ddr_hp1;
output[max_burst_bits-1:0] rd_data_ocm_hp1;
output rd_dv_ddr_hp1;
output rd_dv_ocm_hp1;
output wr_ack_ddr_hp2;
output wr_ack_ocm_hp2;
input[max_burst_bits-1:0] wr_data_hp2;
input[addr_width-1:0] wr_addr_hp2;
input[max_burst_bytes_width:0] wr_bytes_hp2;
input wr_dv_ddr_hp2;
input wr_dv_ocm_hp2;
input rd_req_ddr_hp2;
input rd_req_ocm_hp2;
input[addr_width-1:0] rd_addr_hp2;
input[max_burst_bytes_width:0] rd_bytes_hp2;
output[max_burst_bits-1:0] rd_data_ddr_hp2;
output[max_burst_bits-1:0] rd_data_ocm_hp2;
output rd_dv_ddr_hp2;
output rd_dv_ocm_hp2;
output wr_ack_ddr_hp3;
output wr_ack_ocm_hp3;
input[max_burst_bits-1:0] wr_data_hp3;
input[addr_width-1:0] wr_addr_hp3;
input[max_burst_bytes_width:0] wr_bytes_hp3;
input wr_dv_ddr_hp3;
input wr_dv_ocm_hp3;
input rd_req_ddr_hp3;
input rd_req_ocm_hp3;
input[addr_width-1:0] rd_addr_hp3;
input[max_burst_bytes_width:0] rd_bytes_hp3;
output[max_burst_bits-1:0] rd_data_ddr_hp3;
output[max_burst_bits-1:0] rd_data_ocm_hp3;
output rd_dv_ddr_hp3;
output rd_dv_ocm_hp3;
/* Goes to port 1 of DDR */
input ddr_wr_ack_port1;
output ddr_wr_dv_port1;
output ddr_rd_req_port1;
input ddr_rd_dv_port1;
output[addr_width-1:0] ddr_wr_addr_port1;
output[max_burst_bits-1:0] ddr_wr_data_port1;
output[max_burst_bytes_width:0] ddr_wr_bytes_port1;
output[addr_width-1:0] ddr_rd_addr_port1;
input[max_burst_bits-1:0] ddr_rd_data_port1;
output[max_burst_bytes_width:0] ddr_rd_bytes_port1;
output [axi_qos_width-1:0] ddr_wr_qos_port1;
output [axi_qos_width-1:0] ddr_rd_qos_port1;
/* Goes to port2 of DDR */
input ddr_wr_ack_port2;
output ddr_wr_dv_port2;
output ddr_rd_req_port2;
input ddr_rd_dv_port2;
output[addr_width-1:0] ddr_wr_addr_port2;
output[max_burst_bits-1:0] ddr_wr_data_port2;
output[max_burst_bytes_width:0] ddr_wr_bytes_port2;
output[addr_width-1:0] ddr_rd_addr_port2;
input[max_burst_bits-1:0] ddr_rd_data_port2;
output[max_burst_bytes_width:0] ddr_rd_bytes_port2;
output [axi_qos_width-1:0] ddr_wr_qos_port2;
output [axi_qos_width-1:0] ddr_rd_qos_port2;
/* Goes to port3 of DDR */
input ddr_wr_ack_port3;
output ddr_wr_dv_port3;
output ddr_rd_req_port3;
input ddr_rd_dv_port3;
output[addr_width-1:0] ddr_wr_addr_port3;
output[max_burst_bits-1:0] ddr_wr_data_port3;
output[max_burst_bytes_width:0] ddr_wr_bytes_port3;
output[addr_width-1:0] ddr_rd_addr_port3;
input[max_burst_bits-1:0] ddr_rd_data_port3;
output[max_burst_bytes_width:0] ddr_rd_bytes_port3;
output [axi_qos_width-1:0] ddr_wr_qos_port3;
output [axi_qos_width-1:0] ddr_rd_qos_port3;
/* Goes to port1 of OCM */
input ocm_wr_ack_port1;
output ocm_wr_dv_port1;
output ocm_rd_req_port1;
input ocm_rd_dv_port1;
output[max_burst_bits-1:0] ocm_wr_data_port1;
output[addr_width-1:0] ocm_wr_addr_port1;
output[max_burst_bytes_width:0] ocm_wr_bytes_port1;
input[max_burst_bits-1:0] ocm_rd_data_port1;
output[addr_width-1:0] ocm_rd_addr_port1;
output[max_burst_bytes_width:0] ocm_rd_bytes_port1;
/* Goes to port1 of REG */
output [axi_qos_width-1:0] reg_rd_qos_port1;
output reg_rd_req_port1;
input reg_rd_dv_port1;
input[max_burst_bits-1:0] reg_rd_data_port1;
output[addr_width-1:0] reg_rd_addr_port1;
output[max_burst_bytes_width:0] reg_rd_bytes_port1;
wire ocm_wr_dv_osw0;
wire ocm_wr_dv_osw1;
wire[max_burst_bits-1:0] ocm_wr_data_osw0;
wire[max_burst_bits-1:0] ocm_wr_data_osw1;
wire[addr_width-1:0] ocm_wr_addr_osw0;
wire[addr_width-1:0] ocm_wr_addr_osw1;
wire[max_burst_bytes_width:0] ocm_wr_bytes_osw0;
wire[max_burst_bytes_width:0] ocm_wr_bytes_osw1;
wire ocm_wr_ack_osw0;
wire ocm_wr_ack_osw1;
wire ocm_rd_req_osw0;
wire ocm_rd_req_osw1;
wire[max_burst_bits-1:0] ocm_rd_data_osw0;
wire[max_burst_bits-1:0] ocm_rd_data_osw1;
wire[addr_width-1:0] ocm_rd_addr_osw0;
wire[addr_width-1:0] ocm_rd_addr_osw1;
wire[max_burst_bytes_width:0] ocm_rd_bytes_osw0;
wire[max_burst_bytes_width:0] ocm_rd_bytes_osw1;
wire ocm_rd_dv_osw0;
wire ocm_rd_dv_osw1;
wire [axi_qos_width-1:0] ocm_wr_qos_osw0;
wire [axi_qos_width-1:0] ocm_wr_qos_osw1;
wire [axi_qos_width-1:0] ocm_rd_qos_osw0;
wire [axi_qos_width-1:0] ocm_rd_qos_osw1;
processing_system7_bfm_v2_0_5_fmsw_gp fmsw (
.sw_clk(sw_clk),
.rstn(rstn),
.w_qos_gp0(w_qos_gp0),
.r_qos_gp0(r_qos_gp0),
.wr_ack_ocm_gp0(wr_ack_ocm_gp0),
.wr_ack_ddr_gp0(wr_ack_ddr_gp0),
.wr_data_gp0(wr_data_gp0),
.wr_addr_gp0(wr_addr_gp0),
.wr_bytes_gp0(wr_bytes_gp0),
.wr_dv_ocm_gp0(wr_dv_ocm_gp0),
.wr_dv_ddr_gp0(wr_dv_ddr_gp0),
.rd_req_ocm_gp0(rd_req_ocm_gp0),
.rd_req_ddr_gp0(rd_req_ddr_gp0),
.rd_req_reg_gp0(rd_req_reg_gp0),
.rd_addr_gp0(rd_addr_gp0),
.rd_bytes_gp0(rd_bytes_gp0),
.rd_data_ddr_gp0(rd_data_ddr_gp0),
.rd_data_ocm_gp0(rd_data_ocm_gp0),
.rd_data_reg_gp0(rd_data_reg_gp0),
.rd_dv_ocm_gp0(rd_dv_ocm_gp0),
.rd_dv_ddr_gp0(rd_dv_ddr_gp0),
.rd_dv_reg_gp0(rd_dv_reg_gp0),
.w_qos_gp1(w_qos_gp1),
.r_qos_gp1(r_qos_gp1),
.wr_ack_ocm_gp1(wr_ack_ocm_gp1),
.wr_ack_ddr_gp1(wr_ack_ddr_gp1),
.wr_data_gp1(wr_data_gp1),
.wr_addr_gp1(wr_addr_gp1),
.wr_bytes_gp1(wr_bytes_gp1),
.wr_dv_ocm_gp1(wr_dv_ocm_gp1),
.wr_dv_ddr_gp1(wr_dv_ddr_gp1),
.rd_req_ocm_gp1(rd_req_ocm_gp1),
.rd_req_ddr_gp1(rd_req_ddr_gp1),
.rd_req_reg_gp1(rd_req_reg_gp1),
.rd_addr_gp1(rd_addr_gp1),
.rd_bytes_gp1(rd_bytes_gp1),
.rd_data_ddr_gp1(rd_data_ddr_gp1),
.rd_data_ocm_gp1(rd_data_ocm_gp1),
.rd_data_reg_gp1(rd_data_reg_gp1),
.rd_dv_ocm_gp1(rd_dv_ocm_gp1),
.rd_dv_ddr_gp1(rd_dv_ddr_gp1),
.rd_dv_reg_gp1(rd_dv_reg_gp1),
.ocm_wr_ack (ocm_wr_ack_osw0),
.ocm_wr_dv (ocm_wr_dv_osw0),
.ocm_rd_req (ocm_rd_req_osw0),
.ocm_rd_dv (ocm_rd_dv_osw0),
.ocm_wr_addr(ocm_wr_addr_osw0),
.ocm_wr_data(ocm_wr_data_osw0),
.ocm_wr_bytes(ocm_wr_bytes_osw0),
.ocm_rd_addr(ocm_rd_addr_osw0),
.ocm_rd_data(ocm_rd_data_osw0),
.ocm_rd_bytes(ocm_rd_bytes_osw0),
.ocm_wr_qos(ocm_wr_qos_osw0),
.ocm_rd_qos(ocm_rd_qos_osw0),
.ddr_wr_qos(ddr_wr_qos_port1),
.ddr_rd_qos(ddr_rd_qos_port1),
.reg_rd_qos(reg_rd_qos_port1),
.ddr_wr_ack(ddr_wr_ack_port1),
.ddr_wr_dv(ddr_wr_dv_port1),
.ddr_rd_req(ddr_rd_req_port1),
.ddr_rd_dv(ddr_rd_dv_port1),
.ddr_wr_addr(ddr_wr_addr_port1),
.ddr_wr_data(ddr_wr_data_port1),
.ddr_wr_bytes(ddr_wr_bytes_port1),
.ddr_rd_addr(ddr_rd_addr_port1),
.ddr_rd_data(ddr_rd_data_port1),
.ddr_rd_bytes(ddr_rd_bytes_port1),
.reg_rd_req(reg_rd_req_port1),
.reg_rd_dv(reg_rd_dv_port1),
.reg_rd_addr(reg_rd_addr_port1),
.reg_rd_data(reg_rd_data_port1),
.reg_rd_bytes(reg_rd_bytes_port1)
);
processing_system7_bfm_v2_0_5_ssw_hp ssw(
.sw_clk(sw_clk),
.rstn(rstn),
.w_qos_hp0(w_qos_hp0),
.r_qos_hp0(r_qos_hp0),
.w_qos_hp1(w_qos_hp1),
.r_qos_hp1(r_qos_hp1),
.w_qos_hp2(w_qos_hp2),
.r_qos_hp2(r_qos_hp2),
.w_qos_hp3(w_qos_hp3),
.r_qos_hp3(r_qos_hp3),
.wr_ack_ddr_hp0(wr_ack_ddr_hp0),
.wr_data_hp0(wr_data_hp0),
.wr_addr_hp0(wr_addr_hp0),
.wr_bytes_hp0(wr_bytes_hp0),
.wr_dv_ddr_hp0(wr_dv_ddr_hp0),
.rd_req_ddr_hp0(rd_req_ddr_hp0),
.rd_addr_hp0(rd_addr_hp0),
.rd_bytes_hp0(rd_bytes_hp0),
.rd_data_ddr_hp0(rd_data_ddr_hp0),
.rd_data_ocm_hp0(rd_data_ocm_hp0),
.rd_dv_ddr_hp0(rd_dv_ddr_hp0),
.wr_ack_ocm_hp0(wr_ack_ocm_hp0),
.wr_dv_ocm_hp0(wr_dv_ocm_hp0),
.rd_req_ocm_hp0(rd_req_ocm_hp0),
.rd_dv_ocm_hp0(rd_dv_ocm_hp0),
.wr_ack_ddr_hp1(wr_ack_ddr_hp1),
.wr_data_hp1(wr_data_hp1),
.wr_addr_hp1(wr_addr_hp1),
.wr_bytes_hp1(wr_bytes_hp1),
.wr_dv_ddr_hp1(wr_dv_ddr_hp1),
.rd_req_ddr_hp1(rd_req_ddr_hp1),
.rd_addr_hp1(rd_addr_hp1),
.rd_bytes_hp1(rd_bytes_hp1),
.rd_data_ddr_hp1(rd_data_ddr_hp1),
.rd_data_ocm_hp1(rd_data_ocm_hp1),
.rd_dv_ddr_hp1(rd_dv_ddr_hp1),
.wr_ack_ocm_hp1(wr_ack_ocm_hp1),
.wr_dv_ocm_hp1(wr_dv_ocm_hp1),
.rd_req_ocm_hp1(rd_req_ocm_hp1),
.rd_dv_ocm_hp1(rd_dv_ocm_hp1),
.wr_ack_ddr_hp2(wr_ack_ddr_hp2),
.wr_data_hp2(wr_data_hp2),
.wr_addr_hp2(wr_addr_hp2),
.wr_bytes_hp2(wr_bytes_hp2),
.wr_dv_ddr_hp2(wr_dv_ddr_hp2),
.rd_req_ddr_hp2(rd_req_ddr_hp2),
.rd_addr_hp2(rd_addr_hp2),
.rd_bytes_hp2(rd_bytes_hp2),
.rd_data_ddr_hp2(rd_data_ddr_hp2),
.rd_data_ocm_hp2(rd_data_ocm_hp2),
.rd_dv_ddr_hp2(rd_dv_ddr_hp2),
.wr_ack_ocm_hp2(wr_ack_ocm_hp2),
.wr_dv_ocm_hp2(wr_dv_ocm_hp2),
.rd_req_ocm_hp2(rd_req_ocm_hp2),
.rd_dv_ocm_hp2(rd_dv_ocm_hp2),
.wr_ack_ddr_hp3(wr_ack_ddr_hp3),
.wr_data_hp3(wr_data_hp3),
.wr_addr_hp3(wr_addr_hp3),
.wr_bytes_hp3(wr_bytes_hp3),
.wr_dv_ddr_hp3(wr_dv_ddr_hp3),
.rd_req_ddr_hp3(rd_req_ddr_hp3),
.rd_addr_hp3(rd_addr_hp3),
.rd_bytes_hp3(rd_bytes_hp3),
.rd_data_ddr_hp3(rd_data_ddr_hp3),
.rd_data_ocm_hp3(rd_data_ocm_hp3),
.rd_dv_ddr_hp3(rd_dv_ddr_hp3),
.wr_ack_ocm_hp3(wr_ack_ocm_hp3),
.wr_dv_ocm_hp3(wr_dv_ocm_hp3),
.rd_req_ocm_hp3(rd_req_ocm_hp3),
.rd_dv_ocm_hp3(rd_dv_ocm_hp3),
.ddr_wr_ack0(ddr_wr_ack_port2),
.ddr_wr_dv0(ddr_wr_dv_port2),
.ddr_rd_req0(ddr_rd_req_port2),
.ddr_rd_dv0(ddr_rd_dv_port2),
.ddr_wr_addr0(ddr_wr_addr_port2),
.ddr_wr_data0(ddr_wr_data_port2),
.ddr_wr_bytes0(ddr_wr_bytes_port2),
.ddr_rd_addr0(ddr_rd_addr_port2),
.ddr_rd_data0(ddr_rd_data_port2),
.ddr_rd_bytes0(ddr_rd_bytes_port2),
.ddr_wr_qos0(ddr_wr_qos_port2),
.ddr_rd_qos0(ddr_rd_qos_port2),
.ddr_wr_ack1(ddr_wr_ack_port3),
.ddr_wr_dv1(ddr_wr_dv_port3),
.ddr_rd_req1(ddr_rd_req_port3),
.ddr_rd_dv1(ddr_rd_dv_port3),
.ddr_wr_addr1(ddr_wr_addr_port3),
.ddr_wr_data1(ddr_wr_data_port3),
.ddr_wr_bytes1(ddr_wr_bytes_port3),
.ddr_rd_addr1(ddr_rd_addr_port3),
.ddr_rd_data1(ddr_rd_data_port3),
.ddr_rd_bytes1(ddr_rd_bytes_port3),
.ddr_wr_qos1(ddr_wr_qos_port3),
.ddr_rd_qos1(ddr_rd_qos_port3),
.ocm_wr_qos(ocm_wr_qos_osw1),
.ocm_rd_qos(ocm_rd_qos_osw1),
.ocm_wr_ack (ocm_wr_ack_osw1),
.ocm_wr_dv (ocm_wr_dv_osw1),
.ocm_rd_req (ocm_rd_req_osw1),
.ocm_rd_dv (ocm_rd_dv_osw1),
.ocm_wr_addr(ocm_wr_addr_osw1),
.ocm_wr_data(ocm_wr_data_osw1),
.ocm_wr_bytes(ocm_wr_bytes_osw1),
.ocm_rd_addr(ocm_rd_addr_osw1),
.ocm_rd_data(ocm_rd_data_osw1),
.ocm_rd_bytes(ocm_rd_bytes_osw1)
);
processing_system7_bfm_v2_0_5_arb_wr osw_wr (
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(ocm_wr_qos_osw0), /// chk
.qos2(ocm_wr_qos_osw1), /// chk
.prt_dv1(ocm_wr_dv_osw0),
.prt_dv2(ocm_wr_dv_osw1),
.prt_data1(ocm_wr_data_osw0),
.prt_data2(ocm_wr_data_osw1),
.prt_addr1(ocm_wr_addr_osw0),
.prt_addr2(ocm_wr_addr_osw1),
.prt_bytes1(ocm_wr_bytes_osw0),
.prt_bytes2(ocm_wr_bytes_osw1),
.prt_ack1(ocm_wr_ack_osw0),
.prt_ack2(ocm_wr_ack_osw1),
.prt_req(ocm_wr_dv_port1),
.prt_qos(ocm_wr_qos_port1),
.prt_data(ocm_wr_data_port1),
.prt_addr(ocm_wr_addr_port1),
.prt_bytes(ocm_wr_bytes_port1),
.prt_ack(ocm_wr_ack_port1)
);
processing_system7_bfm_v2_0_5_arb_rd osw_rd(
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(ocm_rd_qos_osw0), // chk
.qos2(ocm_rd_qos_osw1), // chk
.prt_req1(ocm_rd_req_osw0),
.prt_req2(ocm_rd_req_osw1),
.prt_data1(ocm_rd_data_osw0),
.prt_data2(ocm_rd_data_osw1),
.prt_addr1(ocm_rd_addr_osw0),
.prt_addr2(ocm_rd_addr_osw1),
.prt_bytes1(ocm_rd_bytes_osw0),
.prt_bytes2(ocm_rd_bytes_osw1),
.prt_dv1(ocm_rd_dv_osw0),
.prt_dv2(ocm_rd_dv_osw1),
.prt_req(ocm_rd_req_port1),
.prt_qos(ocm_rd_qos_port1),
.prt_data(ocm_rd_data_port1),
.prt_addr(ocm_rd_addr_port1),
.prt_bytes(ocm_rd_bytes_port1),
.prt_dv(ocm_rd_dv_port1)
);
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.2
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1ns/1ps
`define AUTOTB_DUT matrix_mult
`define AUTOTB_DUT_INST AESL_inst_matrix_mult
`define AUTOTB_TOP apatb_matrix_mult_top
`define AUTOTB_LAT_RESULT_FILE "matrix_mult.result.lat.rb"
`define AUTOTB_PER_RESULT_TRANS_FILE "matrix_mult.performance.result.transaction.xml"
`define AUTOTB_TOP_INST AESL_inst_apatb_matrix_mult_top
`define AUTOTB_MAX_ALLOW_LATENCY 15000000
`define AUTOTB_CLOCK_PERIOD_DIV2 2.50
`define AESL_MEM_a AESL_automem_a
`define AESL_MEM_INST_a mem_inst_a
`define AESL_MEM_b AESL_automem_b
`define AESL_MEM_INST_b mem_inst_b
`define AESL_MEM_prod AESL_automem_prod
`define AESL_MEM_INST_prod mem_inst_prod
`define AUTOTB_TVIN_a "./c.matrix_mult.autotvin_a.dat"
`define AUTOTB_TVIN_b "./c.matrix_mult.autotvin_b.dat"
`define AUTOTB_TVIN_prod "./c.matrix_mult.autotvin_prod.dat"
`define AUTOTB_TVIN_a_out_wrapc "./rtl.matrix_mult.autotvin_a.dat"
`define AUTOTB_TVIN_b_out_wrapc "./rtl.matrix_mult.autotvin_b.dat"
`define AUTOTB_TVIN_prod_out_wrapc "./rtl.matrix_mult.autotvin_prod.dat"
`define AUTOTB_TVOUT_prod "./c.matrix_mult.autotvout_prod.dat"
`define AUTOTB_TVOUT_prod_out_wrapc "./impl_rtl.matrix_mult.autotvout_prod.dat"
module `AUTOTB_TOP;
parameter AUTOTB_TRANSACTION_NUM = 1;
parameter PROGRESS_TIMEOUT = 10000000;
parameter LATENCY_ESTIMATION = 686;
parameter LENGTH_a = 25;
parameter LENGTH_b = 25;
parameter LENGTH_prod = 25;
task read_token;
input integer fp;
output reg [127 : 0] token;
integer ret;
begin
token = "";
ret = 0;
ret = $fscanf(fp,"%s",token);
end
endtask
task post_check;
input integer fp1;
input integer fp2;
reg [127 : 0] token1;
reg [127 : 0] token2;
reg [127 : 0] golden;
reg [127 : 0] result;
integer ret;
begin
read_token(fp1, token1);
read_token(fp2, token2);
if (token1 != "[[[runtime]]]" || token2 != "[[[runtime]]]") begin
$display("ERROR: Simulation using HLS TB failed.");
$finish;
end
read_token(fp1, token1);
read_token(fp2, token2);
while (token1 != "[[[/runtime]]]" && token2 != "[[[/runtime]]]") begin
if (token1 != "[[transaction]]" || token2 != "[[transaction]]") begin
$display("ERROR: Simulation using HLS TB failed.");
$finish;
end
read_token(fp1, token1); // skip transaction number
read_token(fp2, token2); // skip transaction number
read_token(fp1, token1);
read_token(fp2, token2);
while(token1 != "[[/transaction]]" && token2 != "[[/transaction]]") begin
ret = $sscanf(token1, "0x%x", golden);
if (ret != 1) begin
$display("Failed to parse token!");
$display("ERROR: Simulation using HLS TB failed.");
$finish;
end
ret = $sscanf(token2, "0x%x", result);
if (ret != 1) begin
$display("Failed to parse token!");
$display("ERROR: Simulation using HLS TB failed.");
$finish;
end
if(golden != result) begin
$display("%x (expected) vs. %x (actual) - mismatch", golden, result);
$display("ERROR: Simulation using HLS TB failed.");
$finish;
end
read_token(fp1, token1);
read_token(fp2, token2);
end
read_token(fp1, token1);
read_token(fp2, token2);
end
end
endtask
reg AESL_clock;
reg rst;
reg start;
reg ce;
reg tb_continue;
wire AESL_start;
wire AESL_reset;
wire AESL_ce;
wire AESL_ready;
wire AESL_idle;
wire AESL_continue;
wire AESL_done;
reg AESL_done_delay = 0;
reg AESL_done_delay2 = 0;
reg AESL_ready_delay = 0;
wire ready;
wire ready_wire;
wire ap_start;
wire ap_done;
wire ap_idle;
wire ap_ready;
wire [4 : 0] a_address0;
wire a_ce0;
wire [7 : 0] a_q0;
wire [4 : 0] b_address0;
wire b_ce0;
wire [7 : 0] b_q0;
wire [4 : 0] prod_address0;
wire prod_ce0;
wire prod_we0;
wire [15 : 0] prod_d0;
integer done_cnt = 0;
integer AESL_ready_cnt = 0;
integer ready_cnt = 0;
reg ready_initial;
reg ready_initial_n;
reg ready_last_n;
reg ready_delay_last_n;
reg done_delay_last_n;
reg interface_done = 0;
wire ap_clk;
wire ap_rst;
wire ap_rst_n;
`AUTOTB_DUT `AUTOTB_DUT_INST(
.ap_clk(ap_clk),
.ap_rst(ap_rst),
.ap_start(ap_start),
.ap_done(ap_done),
.ap_idle(ap_idle),
.ap_ready(ap_ready),
.a_address0(a_address0),
.a_ce0(a_ce0),
.a_q0(a_q0),
.b_address0(b_address0),
.b_ce0(b_ce0),
.b_q0(b_q0),
.prod_address0(prod_address0),
.prod_ce0(prod_ce0),
.prod_we0(prod_we0),
.prod_d0(prod_d0));
// Assignment for control signal
assign ap_clk = AESL_clock;
assign ap_rst = AESL_reset;
assign ap_rst_n = ~AESL_reset;
assign AESL_reset = rst;
assign ap_start = AESL_start;
assign AESL_start = start;
assign AESL_done = ap_done;
assign AESL_idle = ap_idle;
assign AESL_ready = ap_ready;
assign AESL_ce = ce;
assign AESL_continue = tb_continue;
always @(posedge AESL_clock) begin
if (AESL_reset) begin
end else begin
if (AESL_done !== 1 && AESL_done !== 0) begin
$display("ERROR: Control signal AESL_done is invalid!");
$finish;
end
end
end
always @(posedge AESL_clock) begin
if (AESL_reset) begin
end else begin
if (AESL_ready !== 1 && AESL_ready !== 0) begin
$display("ERROR: Control signal AESL_ready is invalid!");
$finish;
end
end
end
//------------------------arraya Instantiation--------------
// The input and output of arraya
wire arraya_ce0, arraya_ce1;
wire arraya_we0, arraya_we1;
wire [4 : 0] arraya_address0, arraya_address1;
wire [7 : 0] arraya_din0, arraya_din1;
wire [7 : 0] arraya_dout0, arraya_dout1;
wire arraya_ready;
wire arraya_done;
`AESL_MEM_a `AESL_MEM_INST_a(
.clk (AESL_clock),
.rst (AESL_reset),
.ce0 (arraya_ce0),
.we0 (arraya_we0),
.address0 (arraya_address0),
.din0 (arraya_din0),
.dout0 (arraya_dout0),
.ce1 (arraya_ce1),
.we1 (arraya_we1),
.address1 (arraya_address1),
.din1 (arraya_din1),
.dout1 (arraya_dout1),
.ready (arraya_ready),
.done (arraya_done)
);
// Assignment between dut and arraya
assign arraya_address0 = a_address0;
assign arraya_ce0 = a_ce0;
assign a_q0 = arraya_dout0;
assign arraya_we0 = 0;
assign arraya_din0 = 0;
assign arraya_we1 = 0;
assign arraya_din1 = 0;
assign arraya_ready= ready;
assign arraya_done = 0;
//------------------------arrayb Instantiation--------------
// The input and output of arrayb
wire arrayb_ce0, arrayb_ce1;
wire arrayb_we0, arrayb_we1;
wire [4 : 0] arrayb_address0, arrayb_address1;
wire [7 : 0] arrayb_din0, arrayb_din1;
wire [7 : 0] arrayb_dout0, arrayb_dout1;
wire arrayb_ready;
wire arrayb_done;
`AESL_MEM_b `AESL_MEM_INST_b(
.clk (AESL_clock),
.rst (AESL_reset),
.ce0 (arrayb_ce0),
.we0 (arrayb_we0),
.address0 (arrayb_address0),
.din0 (arrayb_din0),
.dout0 (arrayb_dout0),
.ce1 (arrayb_ce1),
.we1 (arrayb_we1),
.address1 (arrayb_address1),
.din1 (arrayb_din1),
.dout1 (arrayb_dout1),
.ready (arrayb_ready),
.done (arrayb_done)
);
// Assignment between dut and arrayb
assign arrayb_address0 = b_address0;
assign arrayb_ce0 = b_ce0;
assign b_q0 = arrayb_dout0;
assign arrayb_we0 = 0;
assign arrayb_din0 = 0;
assign arrayb_we1 = 0;
assign arrayb_din1 = 0;
assign arrayb_ready= ready;
assign arrayb_done = 0;
//------------------------arrayprod Instantiation--------------
// The input and output of arrayprod
wire arrayprod_ce0, arrayprod_ce1;
wire arrayprod_we0, arrayprod_we1;
wire [4 : 0] arrayprod_address0, arrayprod_address1;
wire [15 : 0] arrayprod_din0, arrayprod_din1;
wire [15 : 0] arrayprod_dout0, arrayprod_dout1;
wire arrayprod_ready;
wire arrayprod_done;
`AESL_MEM_prod `AESL_MEM_INST_prod(
.clk (AESL_clock),
.rst (AESL_reset),
.ce0 (arrayprod_ce0),
.we0 (arrayprod_we0),
.address0 (arrayprod_address0),
.din0 (arrayprod_din0),
.dout0 (arrayprod_dout0),
.ce1 (arrayprod_ce1),
.we1 (arrayprod_we1),
.address1 (arrayprod_address1),
.din1 (arrayprod_din1),
.dout1 (arrayprod_dout1),
.ready (arrayprod_ready),
.done (arrayprod_done)
);
// Assignment between dut and arrayprod
assign arrayprod_address0 = prod_address0;
assign arrayprod_ce0 = prod_ce0;
assign arrayprod_we0 = prod_we0;
assign arrayprod_din0 = prod_d0;
assign arrayprod_we1 = 0;
assign arrayprod_din1 = 0;
assign arrayprod_ready= ready_initial | arrayprod_done;
assign arrayprod_done = AESL_done_delay;
initial begin : generate_AESL_ready_cnt_proc
AESL_ready_cnt = 0;
wait(AESL_reset === 0);
while(AESL_ready_cnt != AUTOTB_TRANSACTION_NUM) begin
while(AESL_ready !== 1) begin
@(posedge AESL_clock);
# 0.4;
end
@(negedge AESL_clock);
AESL_ready_cnt = AESL_ready_cnt + 1;
@(posedge AESL_clock);
# 0.4;
end
end
event next_trigger_ready_cnt;
initial begin : gen_ready_cnt
ready_cnt = 0;
wait (AESL_reset === 0);
forever begin
@ (posedge AESL_clock);
if (ready == 1) begin
if (ready_cnt < AUTOTB_TRANSACTION_NUM) begin
ready_cnt = ready_cnt + 1;
end
end
-> next_trigger_ready_cnt;
end
end
wire all_finish = (done_cnt == AUTOTB_TRANSACTION_NUM);
// done_cnt
always @ (posedge AESL_clock) begin
if (AESL_reset) begin
done_cnt <= 0;
end else begin
if (AESL_done == 1) begin
if (done_cnt < AUTOTB_TRANSACTION_NUM) begin
done_cnt <= done_cnt + 1;
end
end
end
end
initial begin : finish_simulation
integer fp1;
integer fp2;
wait (all_finish == 1);
// last transaction is saved at negedge right after last done
@ (posedge AESL_clock);
@ (posedge AESL_clock);
@ (posedge AESL_clock);
@ (posedge AESL_clock);
fp1 = $fopen("./rtl.matrix_mult.autotvout_prod.dat", "r");
fp2 = $fopen("./impl_rtl.matrix_mult.autotvout_prod.dat", "r");
if(fp1 == 0) // Failed to open file
$display("Failed to open file \"./rtl.matrix_mult.autotvout_prod.dat\"!");
else if(fp2 == 0)
$display("Failed to open file \"./impl_rtl.matrix_mult.autotvout_prod.dat\"!");
else begin
$display("Comparing rtl.matrix_mult.autotvout_prod.dat with impl_rtl.matrix_mult.autotvout_prod.dat");
post_check(fp1, fp2);
end
$fclose(fp1);
$fclose(fp2);
$display("Simulation Passed.");
$finish;
end
initial begin
AESL_clock = 0;
forever #`AUTOTB_CLOCK_PERIOD_DIV2 AESL_clock = ~AESL_clock;
end
reg end_a;
reg [31:0] size_a;
reg [31:0] size_a_backup;
reg end_b;
reg [31:0] size_b;
reg [31:0] size_b_backup;
reg end_prod;
reg [31:0] size_prod;
reg [31:0] size_prod_backup;
initial begin : initial_process
integer proc_rand;
rst = 1;
# 100;
repeat(3) @ (posedge AESL_clock);
rst = 0;
end
initial begin : start_process
integer proc_rand;
reg [31:0] start_cnt;
ce = 1;
start = 0;
start_cnt = 0;
wait (AESL_reset === 0);
@ (posedge AESL_clock);
#0 start = 1;
start_cnt = start_cnt + 1;
forever begin
@ (posedge AESL_clock);
if (start_cnt >= AUTOTB_TRANSACTION_NUM) begin
// keep pushing garbage in
#0 start = 1;
end
if (AESL_ready) begin
start_cnt = start_cnt + 1;
end
end
end
always @(AESL_done)
begin
tb_continue = AESL_done;
end
initial begin : ready_initial_process
ready_initial = 0;
wait (AESL_start === 1);
ready_initial = 1;
@(posedge AESL_clock);
ready_initial = 0;
end
always @(posedge AESL_clock)
begin
if(AESL_reset)
AESL_ready_delay = 0;
else
AESL_ready_delay = AESL_ready;
end
initial begin : ready_last_n_process
ready_last_n = 1;
wait(ready_cnt == AUTOTB_TRANSACTION_NUM)
@(posedge AESL_clock);
ready_last_n <= 0;
end
always @(posedge AESL_clock)
begin
if(AESL_reset)
ready_delay_last_n = 0;
else
ready_delay_last_n <= ready_last_n;
end
assign ready = (ready_initial | AESL_ready_delay);
assign ready_wire = ready_initial | AESL_ready_delay;
initial begin : done_delay_last_n_process
done_delay_last_n = 1;
while(done_cnt < AUTOTB_TRANSACTION_NUM)
@(posedge AESL_clock);
# 0.1;
done_delay_last_n = 0;
end
always @(posedge AESL_clock)
begin
if(AESL_reset)
begin
AESL_done_delay <= 0;
AESL_done_delay2 <= 0;
end
else begin
AESL_done_delay <= AESL_done & done_delay_last_n;
AESL_done_delay2 <= AESL_done_delay;
end
end
always @(posedge AESL_clock)
begin
if(AESL_reset)
interface_done = 0;
else begin
# 0.01;
if(ready === 1 && ready_cnt > 0 && ready_cnt < AUTOTB_TRANSACTION_NUM)
interface_done = 1;
else if(AESL_done_delay === 1 && done_cnt == AUTOTB_TRANSACTION_NUM)
interface_done = 1;
else
interface_done = 0;
end
end
reg dump_tvout_finish_prod;
initial begin : dump_tvout_runtime_sign_prod
integer fp;
dump_tvout_finish_prod = 0;
fp = $fopen(`AUTOTB_TVOUT_prod_out_wrapc, "w");
if (fp == 0) begin
$display("Failed to open file \"%s\"!", `AUTOTB_TVOUT_prod_out_wrapc);
$display("ERROR: Simulation using HLS TB failed.");
$finish;
end
$fdisplay(fp,"[[[runtime]]]");
$fclose(fp);
wait (done_cnt == AUTOTB_TRANSACTION_NUM);
// last transaction is saved at negedge right after last done
@ (posedge AESL_clock);
@ (posedge AESL_clock);
@ (posedge AESL_clock);
fp = $fopen(`AUTOTB_TVOUT_prod_out_wrapc, "a");
if (fp == 0) begin
$display("Failed to open file \"%s\"!", `AUTOTB_TVOUT_prod_out_wrapc);
$display("ERROR: Simulation using HLS TB failed.");
$finish;
end
$fdisplay(fp,"[[[/runtime]]]");
$fclose(fp);
dump_tvout_finish_prod = 1;
end
////////////////////////////////////////////
// progress and performance
////////////////////////////////////////////
task wait_start();
while (~AESL_start) begin
@ (posedge AESL_clock);
end
endtask
reg [31:0] clk_cnt = 0;
reg AESL_ready_p1;
always @ (posedge AESL_clock) begin
clk_cnt <= clk_cnt + 1;
AESL_ready_p1 <= AESL_ready;
end
reg [31:0] start_timestamp [0:AUTOTB_TRANSACTION_NUM - 1];
reg [31:0] start_cnt;
reg [31:0] finish_timestamp [0:AUTOTB_TRANSACTION_NUM - 1];
reg [31:0] finish_cnt;
event report_progress;
initial begin
start_cnt = 0;
finish_cnt = 0;
wait (AESL_reset == 0);
wait_start();
start_timestamp[start_cnt] = clk_cnt;
start_cnt = start_cnt + 1;
if (AESL_done) begin
finish_timestamp[finish_cnt] = clk_cnt;
finish_cnt = finish_cnt + 1;
end
-> report_progress;
forever begin
@ (posedge AESL_clock);
if (start_cnt < AUTOTB_TRANSACTION_NUM) begin
if (AESL_start && AESL_ready_p1) begin
start_timestamp[start_cnt] = clk_cnt;
start_cnt = start_cnt + 1;
end
end
if (finish_cnt < AUTOTB_TRANSACTION_NUM) begin
if (AESL_done) begin
finish_timestamp[finish_cnt] = clk_cnt;
finish_cnt = finish_cnt + 1;
end
end
-> report_progress;
end
end
reg [31:0] progress_timeout;
initial begin : simulation_progress
real intra_progress;
wait (AESL_reset == 0);
progress_timeout = PROGRESS_TIMEOUT;
$display("////////////////////////////////////////////////////////////////////////////////////");
$display("// Inter-Transaction Progress: Completed Transaction / Total Transaction");
$display("// Intra-Transaction Progress: Measured Latency / Latency Estimation * 100%%");
$display("//");
$display("// RTL Simulation : \"Inter-Transaction Progress\" [\"Intra-Transaction Progress\"] @ \"Simulation Time\"");
$display("////////////////////////////////////////////////////////////////////////////////////");
print_progress();
while (finish_cnt < AUTOTB_TRANSACTION_NUM) begin
@ (report_progress);
if (finish_cnt < AUTOTB_TRANSACTION_NUM) begin
if (AESL_done) begin
print_progress();
progress_timeout = PROGRESS_TIMEOUT;
end else begin
if (progress_timeout == 0) begin
print_progress();
progress_timeout = PROGRESS_TIMEOUT;
end else begin
progress_timeout = progress_timeout - 1;
end
end
end
end
print_progress();
$display("////////////////////////////////////////////////////////////////////////////////////");
calculate_performance();
end
task get_intra_progress(output real intra_progress);
begin
if (start_cnt > finish_cnt) begin
intra_progress = clk_cnt - start_timestamp[finish_cnt];
end else begin
intra_progress = 0;
end
intra_progress = intra_progress / LATENCY_ESTIMATION;
end
endtask
task print_progress();
real intra_progress;
begin
if (LATENCY_ESTIMATION > 0) begin
get_intra_progress(intra_progress);
$display("// RTL Simulation : %0d / %0d [%2.2f%%] @ \"%0t\"", finish_cnt, AUTOTB_TRANSACTION_NUM, intra_progress * 100, $time);
end else begin
$display("// RTL Simulation : %0d / %0d [n/a] @ \"%0t\"", finish_cnt, AUTOTB_TRANSACTION_NUM, $time);
end
end
endtask
task calculate_performance();
integer i;
integer fp;
reg [31:0] latency [0:AUTOTB_TRANSACTION_NUM - 1];
reg [31:0] latency_min;
reg [31:0] latency_max;
reg [31:0] latency_total;
reg [31:0] latency_average;
reg [31:0] interval [0:AUTOTB_TRANSACTION_NUM - 2];
reg [31:0] interval_min;
reg [31:0] interval_max;
reg [31:0] interval_total;
reg [31:0] interval_average;
begin
latency_min = -1;
latency_max = 0;
latency_total = 0;
interval_min = -1;
interval_max = 0;
interval_total = 0;
for (i = 0; i < AUTOTB_TRANSACTION_NUM; i = i + 1) begin
// calculate latency
latency[i] = finish_timestamp[i] - start_timestamp[i];
if (latency[i] > latency_max) latency_max = latency[i];
if (latency[i] < latency_min) latency_min = latency[i];
latency_total = latency_total + latency[i];
// calculate interval
if (AUTOTB_TRANSACTION_NUM == 1) begin
interval[i] = 0;
interval_max = 0;
interval_min = 0;
interval_total = 0;
end else if (i < AUTOTB_TRANSACTION_NUM - 1) begin
interval[i] = start_timestamp[i + 1] - start_timestamp[i];
if (interval[i] > interval_max) interval_max = interval[i];
if (interval[i] < interval_min) interval_min = interval[i];
interval_total = interval_total + interval[i];
end
end
latency_average = latency_total / AUTOTB_TRANSACTION_NUM;
if (AUTOTB_TRANSACTION_NUM == 1) begin
interval_average = 0;
end else begin
interval_average = interval_total / (AUTOTB_TRANSACTION_NUM - 1);
end
fp = $fopen(`AUTOTB_LAT_RESULT_FILE, "w");
$fdisplay(fp, "$MAX_LATENCY = \"%0d\"", latency_max);
$fdisplay(fp, "$MIN_LATENCY = \"%0d\"", latency_min);
$fdisplay(fp, "$AVER_LATENCY = \"%0d\"", latency_average);
$fdisplay(fp, "$MAX_THROUGHPUT = \"%0d\"", interval_max);
$fdisplay(fp, "$MIN_THROUGHPUT = \"%0d\"", interval_min);
$fdisplay(fp, "$AVER_THROUGHPUT = \"%0d\"", interval_average);
$fclose(fp);
fp = $fopen(`AUTOTB_PER_RESULT_TRANS_FILE, "w");
$fdisplay(fp, "%20s%16s%16s", "", "latency", "interval");
if (AUTOTB_TRANSACTION_NUM == 1) begin
i = 0;
$fdisplay(fp, "transaction%8d:%16d%16d", i, latency[i], interval[i]);
end else begin
for (i = 0; i < AUTOTB_TRANSACTION_NUM; i = i + 1) begin
if (i < AUTOTB_TRANSACTION_NUM - 1) begin
$fdisplay(fp, "transaction%8d:%16d%16d", i, latency[i], interval[i]);
end else begin
$fdisplay(fp, "transaction%8d:%16d x", i, latency[i]);
end
end
end
$fclose(fp);
end
endtask
////////////////////////////////////////////
// Dependence Check
////////////////////////////////////////////
`ifndef POST_SYN
`endif
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Engineer: Ryan
//
// Create Date: 05/23/2017
// Module Name: ClkDiv_66_67kHz
// Project Name: Joystick_Controller
// Target Devices: ICEStick
// Tool versions: iCEcube2
// Description: Converts input 12 MHz clock signal to a 66.67kHz clock signal for serial comm
//////////////////////////////////////////////////////////////////////////////////
// ==============================================================================
// Define Module
// ==============================================================================
module ClkDiv_66_67kHz(
CLK, // 12MHz onbaord clock
RST, // Reset
CLKOUT // New clock output
);
// ===========================================================================
// Port Declarations
// ===========================================================================
input CLK;
input RST;
output CLKOUT;
// ===========================================================================
// Parameters, Regsiters, and Wires
// ===========================================================================
// Output register
reg CLKOUT = 1'b1;
// Value to toggle output clock at
parameter cntEndVal = 7'b1011010;
// Current count
reg [6:0] clkCount = 7'b0000000;
// ===========================================================================
// Implementation
// ===========================================================================
//----------------------------------------------
// 66.67kHz Clock Divider, period 15us, for serial clock timing
//----------------------------------------------
always @(posedge CLK) begin
// Reset clock
if(RST == 1'b1) begin
CLKOUT <= 1'b0;
clkCount <= 0;
end
// Count/toggle normally
else begin
if(clkCount == cntEndVal) begin
CLKOUT <= ~CLKOUT;
clkCount <= 0;
end
else begin
clkCount <= clkCount + 1'b1;
end
end
end
endmodule
|
// Author: Adam Nunez, [email protected]
// Copyright (C) 2015 Adam Nunez
//
// This program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public License
// as published by the Free Software Foundation; either version 2
// of the License, or (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
`timescale 1ns/1ns
module KeyPadTestBench();
reg flag;
//Inputs to KeyPadInterpreter
reg Clock;
reg ResetButton;
reg KeyRead;
reg [3:0] RowDataIn;
//Outputs from KeyPadInterpreter
wire KeyReady;
wire [3:0] DataOut;
wire [3:0] ColDataOut;
wire [3:0] PressCount;
//Clock Setup
initial begin
Clock = 0;
end
always begin
#1 Clock = ~Clock;
end
//End Clock Setup
//Keypad Emulator,
// returns that "5" is pressed after flag goes high
always @(ColDataOut) begin
if(flag==1) begin
case(ColDataOut)
4'bzzz0: RowDataIn = 4'b1111;
4'bzz0z: RowDataIn = 4'b1111;
4'bz0zz: RowDataIn = 4'b1101;
4'b0zzz: RowDataIn = 4'b1111;
endcase
end
else begin
case(ColDataOut)
4'bzzz0: RowDataIn = 4'b1111;
4'bzz0z: RowDataIn = 4'b1111;
4'bz0zz: RowDataIn = 4'b1111;
4'b0zzz: RowDataIn = 4'b1111;
endcase
end
end
//End Keypad Emulator
//Actual Testing
initial begin
#0 flag = 0;
#0 ResetButton = 0;
#3 ResetButton = 1;
#10000000; //Wait a long time
flag = 1;
#10000000; //Wait a little more
if(DataOut == 4'b0110)
$display("CorrectKey");
else
$display("Wrong DataOut");
end
//End of Testing
//Module to be tested
KeyPadInterpreter test(Clock,ResetButton,KeyRead,RowDataIn,KeyReady,DataOut,ColDataOut,PressCount);
endmodule |
`timescale 1ns/1ps
module tb_multiplier (); /* this is automatically generated */
reg clk;
// clock
initial begin
clk = 0;
forever #5 clk = ~clk;
end
`ifdef SINGLE
parameter SW = 24;
`endif
`ifdef DOUBLE
parameter SW = 54;// */
`endif
// (*NOTE*) replace reset, clock
reg [SW-1:0] a;
reg [SW-1:0] b;
// wire [2*SW-2:0] BinaryRES;
wire [2*SW-1:0] FKOARES;
reg clk;
reg rst;
reg load_b_i;
`ifdef SINGLE
Sgf_Multiplication_SW24 #(.SW(SW))
`endif
`ifdef DOUBLE
Sgf_Multiplication_SW54 #(.SW(SW))
`endif
inst_Sgf_Multiplication (.clk(clk),.rst(rst),.load_b_i(load_b_i),.Data_A_i(a), .Data_B_i(b), .sgf_result_o(FKOARES));
integer i = 1;
parameter cycles = 1024;
initial begin
$monitor(a,b, FKOARES, a*b);
end
initial begin
b = 1;
rst = 1;
a = 1;
load_b_i = 0;
#30;
rst = 0;
#15;
load_b_i = 1;
#100;
b = 2;
repeat (cycles) begin
a = i;
b = b + 2;
i = i + 1;
#50;
end
$finish;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__CLKBUF_FUNCTIONAL_V
`define SKY130_FD_SC_HD__CLKBUF_FUNCTIONAL_V
/**
* clkbuf: Clock tree buffer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__clkbuf (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__CLKBUF_FUNCTIONAL_V |
// test case taken from amber23 Verilog code
module a23_barrel_shift_fpga_rotate(i_in, direction, shift_amount, rot_prod);
input [31:0] i_in;
input direction;
input [4:0] shift_amount;
output [31:0] rot_prod;
// Generic rotate. Theoretical cost: 32x5 4-to-1 LUTs.
// Practically a bit higher due to high fanout of "direction".
generate
genvar i, j;
for (i = 0; i < 5; i = i + 1)
begin : netgen
wire [31:0] in;
reg [31:0] out;
for (j = 0; j < 32; j = j + 1)
begin : net
always @*
out[j] = in[j] & (~shift_amount[i] ^ direction) |
in[wrap(j, i)] & (shift_amount[i] ^ direction);
end
end
// Order is reverted with respect to volatile shift_amount[0]
assign netgen[4].in = i_in;
for (i = 1; i < 5; i = i + 1)
begin : router
assign netgen[i-1].in = netgen[i].out;
end
endgenerate
// Aliasing
assign rot_prod = netgen[0].out;
function [4:0] wrap;
input integer pos;
input integer level;
integer out;
begin
out = pos - (1 << level);
wrap = out[4:0];
end
endfunction
endmodule
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
* for EE577b Troy WideWord Processor Project
*/
// Include definition of the control signals
`include "control.h"
// Behavioral model for the register file
module RegFileWW(rd1data,rd2data,wrdata,rd1addr,rd2addr,wraddr,
rd1en,rd2en,wren,wrbyteen,clk);
// Definitions for the constants the advanced register file
// parameter PARAM_NAME = VALUE;
// ===============================================================
// Output signals...
/**
* Output data that's read from the 2 ports of the advanced
* register file: data from Port 1 and Port 2
*
* Stay at high impedance state if no read operation is performed
*/
output [127:0] rd1data,rd2data;
// ===============================================================
// Input signals
// Input data coming into the write port of the register file
input [0:127] wrdata;
// Clock signal to facilitate state transitions
input clk;
// Write enable signal to facilitate writing signals; active-high
input wren;
// Read enable signals for two read ports; active-high
input rd1en, rd2en;
/**
* Addresses for write and read operations
*
* wraddr must have valid output data at positive edge of the
* clock when wren is set to logic HIGH
*
* rd?addr should contain valid value when rd?en = HIGH
*/
input [4:0] wraddr, rd1addr, rd2addr;
/**
* Byte-write enable signals: one for each byte of the data
*
* Asserted high when each byte of the address word needs to be
* updated during the write operation
*/
input [15:0] wrbyteen;
// ===============================================================
// Declare "wire" signals:
//wire FSM_OUTPUT;
// ===============================================================
// Declare "reg" signals:
reg [127:0] rd1data,rd2data; // Output signals
/**
* (32 word) depth and (128 bits per word) width
*/
reg [127:0] reg_file [31:0]; // Store the data here
reg [127:0] ones; // 128-bit ones
reg [127:0] result; // ones & operand
reg [7:0] operand; // Write data to operate with
// ===============================================================
always @(posedge clk)
begin
ones=128'd0;
ones=ones-1'd1;
if(wren)
begin
if(wrbyteen==16'h1)
begin
operand=wrdata[0:7];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'h3)
begin
operand=wrdata[8:15];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'h7)
begin
operand=wrdata[16:23];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'hf)
begin
operand=wrdata[24:31];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'h1f)
begin
operand=wrdata[32:39];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'h3f)
begin
operand=wrdata[40:47];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'h7f)
begin
operand=wrdata[48:55];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'hff)
begin
operand=wrdata[56:63];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'h1ff)
begin
operand=wrdata[64:71];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'h3ff)
begin
operand=wrdata[72:79];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'h7ff)
begin
operand=wrdata[80:87];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'hfff)
begin
operand=wrdata[88:95];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'h1fff)
begin
operand=wrdata[96:103];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'h3fff)
begin
operand=wrdata[104:111];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'h7fff)
begin
operand=wrdata[112:119];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'hffff)
begin
operand=wrdata[120:127];
result = ones & operand;
reg_file[wraddr] <= result;
end
end
if(rd1en && (rd1addr!==5'dx) && (rd1addr!==5'dz))
begin
rd1data<=reg_file[rd1addr];
end
else
begin
rd1data=128'dz;
end
if(rd2en && (rd2addr!==5'dx) && (rd2addr!==5'dz))
begin
rd2data<=reg_file[rd2addr];
end
else
begin
rd2data=128'dz;
end
end
endmodule
|
`timescale 1ns / 1ps
// Copyright (C) 2008 Schuyler Eldridge, Boston University
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
module mux(opA,opB,sum,dsp_sel,out);
input [3:0] opA,opB;
input [4:0] sum;
input [1:0] dsp_sel;
output [3:0] out;
reg cout;
always @ (sum)
begin
if (sum[4] == 1)
cout <= 4'b0001;
else
cout <= 4'b0000;
end
reg out;
always @(dsp_sel,sum,cout,opB,opA)
begin
if (dsp_sel == 2'b00)
out <= sum[3:0];
else if (dsp_sel == 2'b01)
out <= cout;
else if (dsp_sel == 2'b10)
out <= opB;
else if (dsp_sel == 2'b11)
out <= opA;
end
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Virtex-6 Integrated Block for PCI Express
// File : sys_clk_gen.v
// Version : 2.4
//--
//--------------------------------------------------------------------------------
`timescale 1ps/1ps
module sys_clk_gen (sys_clk);
output sys_clk;
reg sys_clk;
parameter offset = 0;
parameter halfcycle = 500;
initial begin
sys_clk = 0;
#(offset);
forever #(halfcycle) sys_clk = ~sys_clk;
end
endmodule // sys_clk_gen
|
module RegisterFile(input [31:0] in,Pcin,input [19:0] RSLCT,input Clk, RESET, LOADPC, LOAD,IR_CU, output [31:0] Rn,Rm,Rs,PCout);
wire [31:0] Q[15:0];
//Rd
wire [15:0] DecoderRd; // signal outputs of decoder
//Decoder4x16(input [3:0] IN,output reg [15:0] OUT)
Decoder4x16 DRd(.IN(RSLCT[15:12]),.OUT(DecoderRd)); //Decoder assembly
//Rn_CU
wire [3:0] _RN_CU;
//Multiplexer(input [31:0] IN1,IN2,input IR_CU,output [31:0] OUT);
Multiplexer mux(RSLCT[19:16],RSLCT[3:0],IR_CU,_RN_CU);
wire [15:0] DecoderRn_CU; // signal outputs of decoder
//Decoder4x16(input [3:0] IN,output reg [15:0] OUT)
Decoder4x16 DRn_CU(.IN(_RN_CU),.OUT(DecoderRn_CU));//Decoder assembly
//Rm
wire [15:0] DecoderRm; // signal outputs of decoder
//Decoder4x16(input [3:0] IN,output reg [15:0] OUT)
Decoder4x16 DRm(.IN(RSLCT[7:4]),.OUT(DecoderRm));//Decoder assembly
//Rs
wire [15:0] DecoderRs; // signal outputs of decoder
//Decoder4x16(input [3:0] IN,output reg [15:0] OUT)
Decoder4x16 DRs(.IN(RSLCT[11:8]),.OUT(DecoderRs));//Decoder assembly
wire [31:0] _pcin;
Buffer32_32 pcbufffer1(.IN(Pcin),.Store(LOADPC&!(DecoderRd[15]&LOAD)),.OUT(_pcin));
Buffer32_32 pcbufffer2(.IN(in),.Store((DecoderRd[15]&LOAD)),.OUT(_pcin));
generate
genvar i;
for (i=0; i<=15; i=i+1) begin : registers
if(i<15)
//Register(input [31:0] IN,input Clk, Reset,Load,output [31:0] OUT);
Register test_reg(.IN(in),
.Clk(Clk),
.Reset(RESET),
.Load(DecoderRd[i]&LOAD),
.OUT(Q[i]));
else
begin
//Register(input [31:0] IN,input Clk, Reset,Load,output [31:0] OUT);
Register test_reg(.IN(_pcin),
.Clk(Clk),
.Reset(RESET),
.Load((DecoderRd[i]&LOAD)||LOADPC),
.OUT(Q[i]));
end
end
for (i=0; i<=15; i=i+1) begin : buffers
//Buffer32_32(input [31:0] IN,input Store,output [31:0] OUT);
Buffer32_32 bufffer(.IN(Q[i]),.Store(DecoderRn_CU[i]),.OUT(Rn));
end
for (i=0; i<=15; i=i+1) begin : buffers2
//Buffer32_32(input [31:0] IN,input Store,output [31:0] OUT);
Buffer32_32 bufffer2(.IN(Q[i]),.Store(DecoderRm[i]),.OUT(Rm));
end
for (i=0; i<=15; i=i+1) begin : buffers3
//Buffer32_32(input [31:0] IN,input Store,output [31:0] OUT);
Buffer32_32 bufffer3(.IN(Q[i]),.Store(DecoderRs[i]),.OUT(Rs));
end
endgenerate
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A211OI_2_V
`define SKY130_FD_SC_LP__A211OI_2_V
/**
* a211oi: 2-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2) | B1 | C1)
*
* Verilog wrapper for a211oi with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a211oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a211oi_2 (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a211oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a211oi_2 (
Y ,
A1,
A2,
B1,
C1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a211oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A211OI_2_V
|
//////////////////////////////////////////////////////////////////////////////////
// NPCG_Toggle_BNC_P_read_AW30h for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Kibin Park <[email protected]>
// Ilyong Jung <[email protected]>
// Yong Ho Song <[email protected]>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Kibin Park <[email protected]>
//
// Project Name: Cosmos OpenSSD
// Design Name: NPCG_Toggle_BNC_P_read_AW30h
// Module Name: NPCG_Toggle_BNC_P_read_AW30h
// File Name: NPCG_Toggle_BNC_P_read_AW30h.v
//
// Version: v1.0.0
//
// Description: Page read trigger FSM
//
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module NPCG_Toggle_BNC_P_read_AW30h
#
(
parameter NumberOfWays = 4
)
(
iSystemClock ,
iReset ,
iOpcode ,
iTargetID ,
iSourceID ,
iCMDValid ,
oCMDReady ,
iWaySelect ,
iColAddress ,
iRowAddress ,
oStart ,
oLastStep ,
iPM_Ready ,
iPM_LastStep ,
oPM_PCommand ,
oPM_PCommandOption ,
oPM_TargetWay ,
oPM_NumOfData ,
oPM_CASelect ,
oPM_CAData
);
input iSystemClock ;
input iReset ;
input [5:0] iOpcode ;
input [4:0] iTargetID ;
input [4:0] iSourceID ;
input iCMDValid ;
output oCMDReady ;
input [NumberOfWays - 1:0] iWaySelect ;
input [15:0] iColAddress ;
input [23:0] iRowAddress ;
output oStart ;
output oLastStep ;
input [7:0] iPM_Ready ;
input [7:0] iPM_LastStep ;
output [7:0] oPM_PCommand ;
output [2:0] oPM_PCommandOption ;
output [NumberOfWays - 1:0] oPM_TargetWay ;
output [15:0] oPM_NumOfData ;
output oPM_CASelect ;
output [7:0] oPM_CAData ;
reg [NumberOfWays - 1:0] rTargetWay ;
reg [15:0] rColAddress ;
reg [23:0] rRowAddress ;
wire wModuleTriggered;
wire wTMStart ;
reg [7:0] rPMTrigger ;
reg [2:0] rPCommandOption ;
reg [15:0] rNumOfData ;
reg [7:0] rCAData ;
reg rPMCommandOrAddress ;
localparam State_Idle = 4'b0000 ;
localparam State_NCALIssue = 4'b0001 ;
localparam State_NCmdWrite0 = 4'b0011 ;
localparam State_NAddrWrite0 = 4'b0010 ;
localparam State_NAddrWrite1 = 4'b0110 ;
localparam State_NAddrWrite2 = 4'b0111 ;
localparam State_NAddrWrite3 = 4'b0101 ;
localparam State_NAddrWrite4 = 4'b0100 ;
localparam State_NCmdWrite1 = 4'b1100 ;
localparam State_NTMIssue = 4'b1101 ;
localparam State_WaitDone = 4'b1111 ;
reg [3:0] rCurState ;
reg [3:0] rNextState ;
always @ (posedge iSystemClock)
if (iReset)
rCurState <= State_Idle;
else
rCurState <= rNextState;
always @ (*)
case (rCurState)
State_Idle:
rNextState <= (wModuleTriggered)?State_NCALIssue:State_Idle;
State_NCALIssue:
rNextState <= (iPM_Ready)?State_NCmdWrite0:State_NCALIssue;
State_NCmdWrite0:
rNextState <= State_NAddrWrite0;
State_NAddrWrite0:
rNextState <= State_NAddrWrite1;
State_NAddrWrite1:
rNextState <= State_NAddrWrite2;
State_NAddrWrite2:
rNextState <= State_NAddrWrite3;
State_NAddrWrite3:
rNextState <= State_NAddrWrite4;
State_NAddrWrite4:
rNextState <= State_NCmdWrite1;
State_NCmdWrite1:
rNextState <= State_NTMIssue;
State_NTMIssue:
rNextState <= (wTMStart)?State_WaitDone:State_NTMIssue;
State_WaitDone:
rNextState <= (oLastStep)?State_Idle:State_WaitDone;
default:
rNextState <= State_Idle;
endcase
assign wModuleTriggered = (iCMDValid && iTargetID == 5'b00101 && iOpcode == 6'b000000);
assign wTMStart = (rCurState == State_NTMIssue) & iPM_LastStep[3];
assign oCMDReady = (rCurState == State_Idle);
always @ (posedge iSystemClock)
if (iReset)
begin
rTargetWay <= {(NumberOfWays){1'b0}};
rColAddress <= 16'b0;
rRowAddress <= 24'b0;
end
else
if (wModuleTriggered && (rCurState == State_Idle))
begin
rTargetWay <= iWaySelect ;
rColAddress <= iColAddress ;
rRowAddress <= iRowAddress ;
end
always @ (*)
case (rCurState)
State_NCALIssue:
rPMTrigger <= 8'b00001000;
State_NTMIssue:
rPMTrigger <= 8'b00000001;
default:
rPMTrigger <= 0;
endcase
always @ (*)
case (rCurState)
State_NTMIssue:
rPCommandOption[2:0] <= 3'b110;
default:
rPCommandOption[2:0] <= 0;
endcase
always @ (*)
case (rCurState)
State_NCALIssue:
rNumOfData[15:0] <= 16'd6; // 1 cmd + 5 addr + 1 cmd = 7 (=> 6)
State_NTMIssue:
rNumOfData[15:0] <= 16'd3; // 40 ns
default:
rNumOfData[15:0] <= 0;
endcase
always @ (*)
case (rCurState)
State_NCmdWrite0:
rPMCommandOrAddress <= 1'b0;
State_NCmdWrite1:
rPMCommandOrAddress <= 1'b0;
State_NAddrWrite0:
rPMCommandOrAddress <= 1'b1;
State_NAddrWrite1:
rPMCommandOrAddress <= 1'b1;
State_NAddrWrite2:
rPMCommandOrAddress <= 1'b1;
State_NAddrWrite3:
rPMCommandOrAddress <= 1'b1;
State_NAddrWrite4:
rPMCommandOrAddress <= 1'b1;
default:
rPMCommandOrAddress <= 1'b0;
endcase
always @ (posedge iSystemClock)
if (iReset)
rCAData <= 0;
else
case (rNextState)
State_NCmdWrite0:
rCAData <= 8'h00;
State_NAddrWrite0:
rCAData <= rColAddress[7:0];
State_NAddrWrite1:
rCAData <= rColAddress[15:8];
State_NAddrWrite2:
rCAData <= rRowAddress[7:0];
State_NAddrWrite3:
rCAData <= rRowAddress[15:8];
State_NAddrWrite4:
rCAData <= rRowAddress[23:16];
State_NCmdWrite1:
rCAData <= 8'h30;
default:
rCAData <= 0;
endcase
assign oStart = wModuleTriggered;
assign oLastStep = (rCurState == State_WaitDone) & iPM_LastStep[0];
assign oPM_PCommand = rPMTrigger;
assign oPM_PCommandOption = rPCommandOption;//1'b0;
assign oPM_TargetWay = rTargetWay;
assign oPM_NumOfData = rNumOfData; //16'd6;
assign oPM_CASelect = rPMCommandOrAddress;
assign oPM_CAData = rCAData;
endmodule
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2013 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module drives the vga dac on Altera's DE2 Board. *
* *
******************************************************************************/
module altera_up_avalon_video_vga_timing (
// inputs
clk,
reset,
red_to_vga_display,
green_to_vga_display,
blue_to_vga_display,
color_select,
// bidirectional
// outputs
read_enable,
end_of_active_frame,
end_of_frame,
// dac pins
vga_blank, // VGA BLANK
vga_c_sync, // VGA COMPOSITE SYNC
vga_h_sync, // VGA H_SYNC
vga_v_sync, // VGA V_SYNC
vga_data_enable, // VGA DEN
vga_red, // VGA Red[9:0]
vga_green, // VGA Green[9:0]
vga_blue, // VGA Blue[9:0]
vga_color_data // VGA Color[9:0] for TRDB_LCM
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter CW = 9;
/* Number of pixels */
parameter H_ACTIVE = 640;
parameter H_FRONT_PORCH = 16;
parameter H_SYNC = 96;
parameter H_BACK_PORCH = 48;
parameter H_TOTAL = 800;
/* Number of lines */
parameter V_ACTIVE = 480;
parameter V_FRONT_PORCH = 10;
parameter V_SYNC = 2;
parameter V_BACK_PORCH = 33;
parameter V_TOTAL = 525;
parameter PW = 10; // Number of bits for pixels
parameter PIXEL_COUNTER_INCREMENT = 10'h001;
parameter LW = 10; // Number of bits for lines
parameter LINE_COUNTER_INCREMENT = 10'h001;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [CW: 0] red_to_vga_display;
input [CW: 0] green_to_vga_display;
input [CW: 0] blue_to_vga_display;
input [ 3: 0] color_select;
// Bidirectionals
// Outputs
output read_enable;
output reg end_of_active_frame;
output reg end_of_frame;
// dac pins
output reg vga_blank; // VGA BLANK
output reg vga_c_sync; // VGA COMPOSITE SYNC
output reg vga_h_sync; // VGA H_SYNC
output reg vga_v_sync; // VGA V_SYNC
output reg vga_data_enable; // VGA DEN
output reg [CW: 0] vga_red; // VGA Red[9:0]
output reg [CW: 0] vga_green; // VGA Green[9:0]
output reg [CW: 0] vga_blue; // VGA Blue[9:0]
output reg [CW: 0] vga_color_data; // VGA Color[9:0] for TRDB_LCM
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
// Internal Registers
//reg clk_en;
reg [PW:1] pixel_counter;
reg [LW:1] line_counter;
reg early_hsync_pulse;
reg early_vsync_pulse;
reg hsync_pulse;
reg vsync_pulse;
reg csync_pulse;
reg hblanking_pulse;
reg vblanking_pulse;
reg blanking_pulse;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @ (posedge clk)
begin
if (reset)
begin
vga_c_sync <= 1'b1;
vga_blank <= 1'b1;
vga_h_sync <= 1'b1;
vga_v_sync <= 1'b1;
vga_red <= {(CW + 1){1'b0}};
vga_green <= {(CW + 1){1'b0}};
vga_blue <= {(CW + 1){1'b0}};
vga_color_data <= {(CW + 1){1'b0}};
end
else
begin
vga_blank <= ~blanking_pulse;
vga_c_sync <= ~csync_pulse;
vga_h_sync <= ~hsync_pulse;
vga_v_sync <= ~vsync_pulse;
// vga_data_enable <= hsync_pulse | vsync_pulse;
vga_data_enable <= ~blanking_pulse;
if (blanking_pulse)
begin
vga_red <= {(CW + 1){1'b0}};
vga_green <= {(CW + 1){1'b0}};
vga_blue <= {(CW + 1){1'b0}};
vga_color_data <= {(CW + 1){1'b0}};
end
else
begin
vga_red <= red_to_vga_display;
vga_green <= green_to_vga_display;
vga_blue <= blue_to_vga_display;
vga_color_data <= ({(CW + 1){color_select[0]}} & red_to_vga_display) |
({(CW + 1){color_select[1]}} & green_to_vga_display) |
({(CW + 1){color_select[2]}} & blue_to_vga_display);
end
end
end
// Internal Registers
always @ (posedge clk)
begin
if (reset)
begin
pixel_counter <= H_TOTAL - 3; // {PW{1'b0}};
line_counter <= V_TOTAL - 1; // {LW{1'b0}};
end
else
begin
// last pixel in the line
if (pixel_counter == (H_TOTAL - 1))
begin
pixel_counter <= {PW{1'b0}};
// last pixel in last line of frame
if (line_counter == (V_TOTAL - 1))
line_counter <= {LW{1'b0}};
// last pixel but not last line
else
line_counter <= line_counter + LINE_COUNTER_INCREMENT;
end
else
pixel_counter <= pixel_counter + PIXEL_COUNTER_INCREMENT;
end
end
always @ (posedge clk)
begin
if (reset)
begin
end_of_active_frame <= 1'b0;
end_of_frame <= 1'b0;
end
else
begin
if ((line_counter == (V_ACTIVE - 1)) &&
(pixel_counter == (H_ACTIVE - 2)))
end_of_active_frame <= 1'b1;
else
end_of_active_frame <= 1'b0;
if ((line_counter == (V_TOTAL - 1)) &&
(pixel_counter == (H_TOTAL - 2)))
end_of_frame <= 1'b1;
else
end_of_frame <= 1'b0;
end
end
always @ (posedge clk)
begin
if (reset)
begin
early_hsync_pulse <= 1'b0;
early_vsync_pulse <= 1'b0;
hsync_pulse <= 1'b0;
vsync_pulse <= 1'b0;
csync_pulse <= 1'b0;
end
else
begin
// start of horizontal sync
if (pixel_counter == (H_ACTIVE + H_FRONT_PORCH - 2))
early_hsync_pulse <= 1'b1;
// end of horizontal sync
else if (pixel_counter == (H_TOTAL - H_BACK_PORCH - 2))
early_hsync_pulse <= 1'b0;
// start of vertical sync
if ((line_counter == (V_ACTIVE + V_FRONT_PORCH - 1)) &&
(pixel_counter == (H_TOTAL - 2)))
early_vsync_pulse <= 1'b1;
// end of vertical sync
else if ((line_counter == (V_TOTAL - V_BACK_PORCH - 1)) &&
(pixel_counter == (H_TOTAL - 2)))
early_vsync_pulse <= 1'b0;
hsync_pulse <= early_hsync_pulse;
vsync_pulse <= early_vsync_pulse;
csync_pulse <= early_hsync_pulse ^ early_vsync_pulse;
end
end
always @ (posedge clk)
begin
if (reset)
begin
hblanking_pulse <= 1'b1;
vblanking_pulse <= 1'b1;
blanking_pulse <= 1'b1;
end
else
begin
if (pixel_counter == (H_ACTIVE - 2))
hblanking_pulse <= 1'b1;
else if (pixel_counter == (H_TOTAL - 2))
hblanking_pulse <= 1'b0;
if ((line_counter == (V_ACTIVE - 1)) &&
(pixel_counter == (H_TOTAL - 2)))
vblanking_pulse <= 1'b1;
else if ((line_counter == (V_TOTAL - 1)) &&
(pixel_counter == (H_TOTAL - 2)))
vblanking_pulse <= 1'b0;
blanking_pulse <= hblanking_pulse | vblanking_pulse;
end
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign read_enable = ~blanking_pulse;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for arbiter
*/
module test_arbiter_rr;
// Parameters
localparam PORTS = 32;
localparam ARB_TYPE_ROUND_ROBIN = 1;
localparam ARB_BLOCK = 1;
localparam ARB_BLOCK_ACK = 0;
localparam ARB_LSB_HIGH_PRIORITY = 0;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [PORTS-1:0] request = 0;
reg [PORTS-1:0] acknowledge = 0;
// Outputs
wire [PORTS-1:0] grant;
wire grant_valid;
wire [$clog2(PORTS)-1:0] grant_encoded;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
request,
acknowledge
);
$to_myhdl(
grant,
grant_valid,
grant_encoded
);
// dump file
$dumpfile("test_arbiter_rr.lxt");
$dumpvars(0, test_arbiter_rr);
end
arbiter #(
.PORTS(PORTS),
.ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
.ARB_BLOCK(ARB_BLOCK),
.ARB_BLOCK_ACK(ARB_BLOCK_ACK),
.ARB_LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)
)
UUT (
.clk(clk),
.rst(rst),
.request(request),
.acknowledge(acknowledge),
.grant(grant),
.grant_valid(grant_valid),
.grant_encoded(grant_encoded)
);
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.4
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module start_for_CvtColowdI_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module start_for_CvtColowdI (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
start_for_CvtColowdI_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_start_for_CvtColowdI_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Address AXI3 Slave Converter
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// a_axi3_conv
// axic_fifo
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_a_axi3_conv #
(
parameter C_FAMILY = "none",
parameter integer C_AXI_ID_WIDTH = 1,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_AUSER_WIDTH = 1,
parameter integer C_AXI_CHANNEL = 0,
// 0 = AXI AW Channel.
// 1 = AXI AR Channel.
parameter integer C_SUPPORT_SPLITTING = 1,
// Implement transaction splitting logic.
// Disabled whan all connected masters are AXI3 and have same or narrower data width.
parameter integer C_SUPPORT_BURSTS = 1,
// Disabled when all connected masters are AxiLite,
// allowing logic to be simplified.
parameter integer C_SINGLE_THREAD = 1
// 0 = Ignore ID when propagating transactions (assume all responses are in order).
// 1 = Enforce single-threading (one ID at a time) when any outstanding or
// requested transaction requires splitting.
// While no split is ongoing any new non-split transaction will pass immediately regardless
// off ID.
// A split transaction will stall if there are multiple ID (non-split) transactions
// ongoing, once it has been forwarded only transactions with the same ID is allowed
// (split or not) until all ongoing split transactios has been completed.
)
(
// System Signals
input wire ACLK,
input wire ARESET,
// Command Interface (W/R)
output wire cmd_valid,
output wire cmd_split,
output wire [C_AXI_ID_WIDTH-1:0] cmd_id,
output wire [4-1:0] cmd_length,
input wire cmd_ready,
// Command Interface (B)
output wire cmd_b_valid,
output wire cmd_b_split,
output wire [4-1:0] cmd_b_repeat,
input wire cmd_b_ready,
// Slave Interface Write Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_AID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AADDR,
input wire [8-1:0] S_AXI_ALEN,
input wire [3-1:0] S_AXI_ASIZE,
input wire [2-1:0] S_AXI_ABURST,
input wire [1-1:0] S_AXI_ALOCK,
input wire [4-1:0] S_AXI_ACACHE,
input wire [3-1:0] S_AXI_APROT,
input wire [4-1:0] S_AXI_AQOS,
input wire [C_AXI_AUSER_WIDTH-1:0] S_AXI_AUSER,
input wire S_AXI_AVALID,
output wire S_AXI_AREADY,
// Master Interface Write Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_AID,
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AADDR,
output wire [4-1:0] M_AXI_ALEN,
output wire [3-1:0] M_AXI_ASIZE,
output wire [2-1:0] M_AXI_ABURST,
output wire [2-1:0] M_AXI_ALOCK,
output wire [4-1:0] M_AXI_ACACHE,
output wire [3-1:0] M_AXI_APROT,
output wire [4-1:0] M_AXI_AQOS,
output wire [C_AXI_AUSER_WIDTH-1:0] M_AXI_AUSER,
output wire M_AXI_AVALID,
input wire M_AXI_AREADY
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for burst types.
localparam [2-1:0] C_FIX_BURST = 2'b00;
localparam [2-1:0] C_INCR_BURST = 2'b01;
localparam [2-1:0] C_WRAP_BURST = 2'b10;
// Depth for command FIFO.
localparam integer C_FIFO_DEPTH_LOG = 5;
// Constants used to generate size mask.
localparam [C_AXI_ADDR_WIDTH+8-1:0] C_SIZE_MASK = {{C_AXI_ADDR_WIDTH{1'b1}}, 8'b0000_0000};
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Access decoding related signals.
wire access_is_incr;
wire [4-1:0] num_transactions;
wire incr_need_to_split;
reg [C_AXI_ADDR_WIDTH-1:0] next_mi_addr;
reg split_ongoing;
reg [4-1:0] pushed_commands;
reg [16-1:0] addr_step;
reg [16-1:0] first_step;
wire [8-1:0] first_beats;
reg [C_AXI_ADDR_WIDTH-1:0] size_mask;
// Access decoding related signals for internal pipestage.
reg access_is_incr_q;
reg incr_need_to_split_q;
wire need_to_split_q;
reg [4-1:0] num_transactions_q;
reg [16-1:0] addr_step_q;
reg [16-1:0] first_step_q;
reg [C_AXI_ADDR_WIDTH-1:0] size_mask_q;
// Command buffer help signals.
reg [C_FIFO_DEPTH_LOG:0] cmd_depth;
reg cmd_empty;
reg [C_AXI_ID_WIDTH-1:0] queue_id;
wire id_match;
wire cmd_id_check;
wire s_ready;
wire cmd_full;
wire allow_this_cmd;
wire allow_new_cmd;
wire cmd_push;
reg cmd_push_block;
reg [C_FIFO_DEPTH_LOG:0] cmd_b_depth;
reg cmd_b_empty;
wire cmd_b_full;
wire cmd_b_push;
reg cmd_b_push_block;
wire pushed_new_cmd;
wire last_incr_split;
wire last_split;
wire first_split;
wire no_cmd;
wire allow_split_cmd;
wire almost_empty;
wire no_b_cmd;
wire allow_non_split_cmd;
wire almost_b_empty;
reg multiple_id_non_split;
reg split_in_progress;
// Internal Command Interface signals (W/R).
wire cmd_split_i;
wire [C_AXI_ID_WIDTH-1:0] cmd_id_i;
reg [4-1:0] cmd_length_i;
// Internal Command Interface signals (B).
wire cmd_b_split_i;
wire [4-1:0] cmd_b_repeat_i;
// Throttling help signals.
wire mi_stalling;
reg command_ongoing;
// Internal SI-side signals.
reg [C_AXI_ID_WIDTH-1:0] S_AXI_AID_Q;
reg [C_AXI_ADDR_WIDTH-1:0] S_AXI_AADDR_Q;
reg [8-1:0] S_AXI_ALEN_Q;
reg [3-1:0] S_AXI_ASIZE_Q;
reg [2-1:0] S_AXI_ABURST_Q;
reg [2-1:0] S_AXI_ALOCK_Q;
reg [4-1:0] S_AXI_ACACHE_Q;
reg [3-1:0] S_AXI_APROT_Q;
reg [4-1:0] S_AXI_AQOS_Q;
reg [C_AXI_AUSER_WIDTH-1:0] S_AXI_AUSER_Q;
reg S_AXI_AREADY_I;
// Internal MI-side signals.
wire [C_AXI_ID_WIDTH-1:0] M_AXI_AID_I;
reg [C_AXI_ADDR_WIDTH-1:0] M_AXI_AADDR_I;
reg [8-1:0] M_AXI_ALEN_I;
wire [3-1:0] M_AXI_ASIZE_I;
wire [2-1:0] M_AXI_ABURST_I;
reg [2-1:0] M_AXI_ALOCK_I;
wire [4-1:0] M_AXI_ACACHE_I;
wire [3-1:0] M_AXI_APROT_I;
wire [4-1:0] M_AXI_AQOS_I;
wire [C_AXI_AUSER_WIDTH-1:0] M_AXI_AUSER_I;
wire M_AXI_AVALID_I;
wire M_AXI_AREADY_I;
reg [1:0] areset_d; // Reset delay register
always @(posedge ACLK) begin
areset_d <= {areset_d[0], ARESET};
end
/////////////////////////////////////////////////////////////////////////////
// Capture SI-Side signals.
//
/////////////////////////////////////////////////////////////////////////////
// Register SI-Side signals.
always @ (posedge ACLK) begin
if ( ARESET ) begin
S_AXI_AID_Q <= {C_AXI_ID_WIDTH{1'b0}};
S_AXI_AADDR_Q <= {C_AXI_ADDR_WIDTH{1'b0}};
S_AXI_ALEN_Q <= 8'b0;
S_AXI_ASIZE_Q <= 3'b0;
S_AXI_ABURST_Q <= 2'b0;
S_AXI_ALOCK_Q <= 2'b0;
S_AXI_ACACHE_Q <= 4'b0;
S_AXI_APROT_Q <= 3'b0;
S_AXI_AQOS_Q <= 4'b0;
S_AXI_AUSER_Q <= {C_AXI_AUSER_WIDTH{1'b0}};
end else begin
if ( S_AXI_AREADY_I ) begin
S_AXI_AID_Q <= S_AXI_AID;
S_AXI_AADDR_Q <= S_AXI_AADDR;
S_AXI_ALEN_Q <= S_AXI_ALEN;
S_AXI_ASIZE_Q <= S_AXI_ASIZE;
S_AXI_ABURST_Q <= S_AXI_ABURST;
S_AXI_ALOCK_Q <= S_AXI_ALOCK;
S_AXI_ACACHE_Q <= S_AXI_ACACHE;
S_AXI_APROT_Q <= S_AXI_APROT;
S_AXI_AQOS_Q <= S_AXI_AQOS;
S_AXI_AUSER_Q <= S_AXI_AUSER;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Decode the Incoming Transaction.
//
// Extract transaction type and the number of splits that may be needed.
//
// Calculate the step size so that the address for each part of a split can
// can be calculated.
//
/////////////////////////////////////////////////////////////////////////////
// Transaction burst type.
assign access_is_incr = ( S_AXI_ABURST == C_INCR_BURST );
// Get number of transactions for split INCR.
assign num_transactions = S_AXI_ALEN[4 +: 4];
assign first_beats = {3'b0, S_AXI_ALEN[0 +: 4]} + 7'b01;
// Generate address increment of first split transaction.
always @ *
begin
case (S_AXI_ASIZE)
3'b000: first_step = first_beats << 0;
3'b001: first_step = first_beats << 1;
3'b010: first_step = first_beats << 2;
3'b011: first_step = first_beats << 3;
3'b100: first_step = first_beats << 4;
3'b101: first_step = first_beats << 5;
3'b110: first_step = first_beats << 6;
3'b111: first_step = first_beats << 7;
endcase
end
// Generate address increment for remaining split transactions.
always @ *
begin
case (S_AXI_ASIZE)
3'b000: addr_step = 16'h0010;
3'b001: addr_step = 16'h0020;
3'b010: addr_step = 16'h0040;
3'b011: addr_step = 16'h0080;
3'b100: addr_step = 16'h0100;
3'b101: addr_step = 16'h0200;
3'b110: addr_step = 16'h0400;
3'b111: addr_step = 16'h0800;
endcase
end
// Generate address mask bits to remove split transaction unalignment.
always @ *
begin
case (S_AXI_ASIZE)
3'b000: size_mask = C_SIZE_MASK[8 +: C_AXI_ADDR_WIDTH];
3'b001: size_mask = C_SIZE_MASK[7 +: C_AXI_ADDR_WIDTH];
3'b010: size_mask = C_SIZE_MASK[6 +: C_AXI_ADDR_WIDTH];
3'b011: size_mask = C_SIZE_MASK[5 +: C_AXI_ADDR_WIDTH];
3'b100: size_mask = C_SIZE_MASK[4 +: C_AXI_ADDR_WIDTH];
3'b101: size_mask = C_SIZE_MASK[3 +: C_AXI_ADDR_WIDTH];
3'b110: size_mask = C_SIZE_MASK[2 +: C_AXI_ADDR_WIDTH];
3'b111: size_mask = C_SIZE_MASK[1 +: C_AXI_ADDR_WIDTH];
endcase
end
/////////////////////////////////////////////////////////////////////////////
// Transfer SI-Side signals to internal Pipeline Stage.
//
/////////////////////////////////////////////////////////////////////////////
always @ (posedge ACLK) begin
if ( ARESET ) begin
access_is_incr_q <= 1'b0;
incr_need_to_split_q <= 1'b0;
num_transactions_q <= 4'b0;
addr_step_q <= 16'b0;
first_step_q <= 16'b0;
size_mask_q <= {C_AXI_ADDR_WIDTH{1'b0}};
end else begin
if ( S_AXI_AREADY_I ) begin
access_is_incr_q <= access_is_incr;
incr_need_to_split_q <= incr_need_to_split;
num_transactions_q <= num_transactions;
addr_step_q <= addr_step;
first_step_q <= first_step;
size_mask_q <= size_mask;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Generate Command Information.
//
// Detect if current transation needs to be split, and keep track of all
// the generated split transactions.
//
//
/////////////////////////////////////////////////////////////////////////////
// Detect when INCR must be split.
assign incr_need_to_split = access_is_incr & ( num_transactions != 0 ) &
( C_SUPPORT_SPLITTING == 1 ) &
( C_SUPPORT_BURSTS == 1 );
// Detect when a command has to be split.
assign need_to_split_q = incr_need_to_split_q;
// Handle progress of split transactions.
always @ (posedge ACLK) begin
if ( ARESET ) begin
split_ongoing <= 1'b0;
end else begin
if ( pushed_new_cmd ) begin
split_ongoing <= need_to_split_q & ~last_split;
end
end
end
// Keep track of number of transactions generated.
always @ (posedge ACLK) begin
if ( ARESET ) begin
pushed_commands <= 4'b0;
end else begin
if ( S_AXI_AREADY_I ) begin
pushed_commands <= 4'b0;
end else if ( pushed_new_cmd ) begin
pushed_commands <= pushed_commands + 4'b1;
end
end
end
// Detect last part of a command, split or not.
assign last_incr_split = access_is_incr_q & ( num_transactions_q == pushed_commands );
assign last_split = last_incr_split | ~access_is_incr_q |
( C_SUPPORT_SPLITTING == 0 ) |
( C_SUPPORT_BURSTS == 0 );
assign first_split = (pushed_commands == 4'b0);
// Calculate base for next address.
always @ (posedge ACLK) begin
if ( ARESET ) begin
next_mi_addr = {C_AXI_ADDR_WIDTH{1'b0}};
end else if ( pushed_new_cmd ) begin
next_mi_addr = M_AXI_AADDR_I + (first_split ? first_step_q : addr_step_q);
end
end
/////////////////////////////////////////////////////////////////////////////
// Translating Transaction.
//
// Set Split transaction information on all part except last for a transaction
// that needs splitting.
// The B Channel will only get one command for a Split transaction and in
// the Split bflag will be set in that case.
//
// The AWID is extracted and applied to all commands generated for the current
// incomming SI-Side transaction.
//
// The address is increased for each part of a Split transaction, the amount
// depends on the siSIZE for the transaction.
//
// The length has to be changed for Split transactions. All part except tha
// last one will have 0xF, the last one uses the 4 lsb bits from the SI-side
// transaction as length.
//
// Non-Split has untouched address and length information.
//
// Exclusive access are diasabled for a Split transaction because it is not
// possible to guarantee concistency between all the parts.
//
/////////////////////////////////////////////////////////////////////////////
// Assign Split signals.
assign cmd_split_i = need_to_split_q & ~last_split;
assign cmd_b_split_i = need_to_split_q & ~last_split;
// Copy AW ID to W.
assign cmd_id_i = S_AXI_AID_Q;
// Set B Responses to merge.
assign cmd_b_repeat_i = num_transactions_q;
// Select new size or remaining size.
always @ *
begin
if ( split_ongoing & access_is_incr_q ) begin
M_AXI_AADDR_I = next_mi_addr & size_mask_q;
end else begin
M_AXI_AADDR_I = S_AXI_AADDR_Q;
end
end
// Generate the base length for each transaction.
always @ *
begin
if ( first_split | ~need_to_split_q ) begin
M_AXI_ALEN_I = S_AXI_ALEN_Q[0 +: 4];
cmd_length_i = S_AXI_ALEN_Q[0 +: 4];
end else begin
M_AXI_ALEN_I = 4'hF;
cmd_length_i = 4'hF;
end
end
// Kill Exclusive for Split transactions.
always @ *
begin
if ( need_to_split_q ) begin
M_AXI_ALOCK_I = 2'b00;
end else begin
M_AXI_ALOCK_I = {1'b0, S_AXI_ALOCK_Q};
end
end
/////////////////////////////////////////////////////////////////////////////
// Forward the command to the MI-side interface.
//
// It is determined that this is an allowed command/access when there is
// room in the command queue (and it passes ID and Split checks as required).
//
/////////////////////////////////////////////////////////////////////////////
// Move SI-side transaction to internal pipe stage.
always @ (posedge ACLK) begin
if (ARESET) begin
command_ongoing <= 1'b0;
S_AXI_AREADY_I <= 1'b0;
end else begin
if (areset_d == 2'b10) begin
S_AXI_AREADY_I <= 1'b1;
end else begin
if ( S_AXI_AVALID & S_AXI_AREADY_I ) begin
command_ongoing <= 1'b1;
S_AXI_AREADY_I <= 1'b0;
end else if ( pushed_new_cmd & last_split ) begin
command_ongoing <= 1'b0;
S_AXI_AREADY_I <= 1'b1;
end
end
end
end
// Generate ready signal.
assign S_AXI_AREADY = S_AXI_AREADY_I;
// Only allowed to forward translated command when command queue is ok with it.
assign M_AXI_AVALID_I = allow_new_cmd & command_ongoing;
// Detect when MI-side is stalling.
assign mi_stalling = M_AXI_AVALID_I & ~M_AXI_AREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Simple transfer of paramters that doesn't need to be adjusted.
//
// ID - Transaction still recognized with the same ID.
// CACHE - No need to change the chache features. Even if the modyfiable
// bit is overridden (forcefully) there is no need to let downstream
// component beleive it is ok to modify it further.
// PROT - Security level of access is not changed when upsizing.
// QOS - Quality of Service is static 0.
// USER - User bits remains the same.
//
/////////////////////////////////////////////////////////////////////////////
assign M_AXI_AID_I = S_AXI_AID_Q;
assign M_AXI_ASIZE_I = S_AXI_ASIZE_Q;
assign M_AXI_ABURST_I = S_AXI_ABURST_Q;
assign M_AXI_ACACHE_I = S_AXI_ACACHE_Q;
assign M_AXI_APROT_I = S_AXI_APROT_Q;
assign M_AXI_AQOS_I = S_AXI_AQOS_Q;
assign M_AXI_AUSER_I = ( C_AXI_SUPPORTS_USER_SIGNALS ) ? S_AXI_AUSER_Q : {C_AXI_AUSER_WIDTH{1'b0}};
/////////////////////////////////////////////////////////////////////////////
// Control command queue to W/R channel.
//
// Commands can be pushed into the Cmd FIFO even if MI-side is stalling.
// A flag is set if MI-side is stalling when Command is pushed to the
// Cmd FIFO. This will prevent multiple push of the same Command as well as
// keeping the MI-side Valid signal if the Allow Cmd requirement has been
// updated to disable furter Commands (I.e. it is made sure that the SI-side
// Command has been forwarded to both Cmd FIFO and MI-side).
//
// It is allowed to continue pushing new commands as long as
// * There is room in the queue(s)
// * The ID is the same as previously queued. Since data is not reordered
// for the same ID it is always OK to let them proceed.
// Or, if no split transaction is ongoing any ID can be allowed.
//
/////////////////////////////////////////////////////////////////////////////
// Keep track of current ID in queue.
always @ (posedge ACLK) begin
if (ARESET) begin
queue_id <= {C_AXI_ID_WIDTH{1'b0}};
multiple_id_non_split <= 1'b0;
split_in_progress <= 1'b0;
end else begin
if ( cmd_push ) begin
// Store ID (it will be matching ID or a "new beginning").
queue_id <= S_AXI_AID_Q;
end
if ( no_cmd & no_b_cmd ) begin
multiple_id_non_split <= 1'b0;
end else if ( cmd_push & allow_non_split_cmd & ~id_match ) begin
multiple_id_non_split <= 1'b1;
end
if ( no_cmd & no_b_cmd ) begin
split_in_progress <= 1'b0;
end else if ( cmd_push & allow_split_cmd ) begin
split_in_progress <= 1'b1;
end
end
end
// Determine if the command FIFOs are empty.
assign no_cmd = almost_empty & cmd_ready | cmd_empty;
assign no_b_cmd = almost_b_empty & cmd_b_ready | cmd_b_empty;
// Check ID to make sure this command is allowed.
assign id_match = ( C_SINGLE_THREAD == 0 ) | ( queue_id == S_AXI_AID_Q);
assign cmd_id_check = (cmd_empty & cmd_b_empty) | ( id_match & (~cmd_empty | ~cmd_b_empty) );
// Command type affects possibility to push immediately or wait.
assign allow_split_cmd = need_to_split_q & cmd_id_check & ~multiple_id_non_split;
assign allow_non_split_cmd = ~need_to_split_q & (cmd_id_check | ~split_in_progress);
assign allow_this_cmd = allow_split_cmd | allow_non_split_cmd | ( C_SINGLE_THREAD == 0 );
// Check if it is allowed to push more commands.
assign allow_new_cmd = (~cmd_full & ~cmd_b_full & allow_this_cmd) |
cmd_push_block;
// Push new command when allowed and MI-side is able to receive the command.
assign cmd_push = M_AXI_AVALID_I & ~cmd_push_block;
assign cmd_b_push = M_AXI_AVALID_I & ~cmd_b_push_block & (C_AXI_CHANNEL == 0);
// Block furter push until command has been forwarded to MI-side.
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_push_block <= 1'b0;
end else begin
if ( pushed_new_cmd ) begin
cmd_push_block <= 1'b0;
end else if ( cmd_push & mi_stalling ) begin
cmd_push_block <= 1'b1;
end
end
end
// Block furter push until command has been forwarded to MI-side.
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_b_push_block <= 1'b0;
end else begin
if ( S_AXI_AREADY_I ) begin
cmd_b_push_block <= 1'b0;
end else if ( cmd_b_push ) begin
cmd_b_push_block <= 1'b1;
end
end
end
// Acknowledge command when we can push it into queue (and forward it).
assign pushed_new_cmd = M_AXI_AVALID_I & M_AXI_AREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Command Queue (W/R):
//
// Instantiate a FIFO as the queue and adjust the control signals.
//
// The features from Command FIFO can be reduced depending on configuration:
// Read Channel only need the split information.
// Write Channel always require ID information. When bursts are supported
// Split and Length information is also used.
//
/////////////////////////////////////////////////////////////////////////////
// Instantiated queue.
generate
if ( C_AXI_CHANNEL == 1 && C_SUPPORT_SPLITTING == 1 && C_SUPPORT_BURSTS == 1 ) begin : USE_R_CHANNEL
axi_data_fifo_v2_1_axic_fifo #
(
.C_FAMILY(C_FAMILY),
.C_FIFO_DEPTH_LOG(C_FIFO_DEPTH_LOG),
.C_FIFO_WIDTH(1),
.C_FIFO_TYPE("lut")
)
cmd_queue
(
.ACLK(ACLK),
.ARESET(ARESET),
.S_MESG({cmd_split_i}),
.S_VALID(cmd_push),
.S_READY(s_ready),
.M_MESG({cmd_split}),
.M_VALID(cmd_valid),
.M_READY(cmd_ready)
);
assign cmd_id = {C_AXI_ID_WIDTH{1'b0}};
assign cmd_length = 4'b0;
end else if (C_SUPPORT_BURSTS == 1) begin : USE_BURSTS
axi_data_fifo_v2_1_axic_fifo #
(
.C_FAMILY(C_FAMILY),
.C_FIFO_DEPTH_LOG(C_FIFO_DEPTH_LOG),
.C_FIFO_WIDTH(C_AXI_ID_WIDTH+4),
.C_FIFO_TYPE("lut")
)
cmd_queue
(
.ACLK(ACLK),
.ARESET(ARESET),
.S_MESG({cmd_id_i, cmd_length_i}),
.S_VALID(cmd_push),
.S_READY(s_ready),
.M_MESG({cmd_id, cmd_length}),
.M_VALID(cmd_valid),
.M_READY(cmd_ready)
);
assign cmd_split = 1'b0;
end else begin : NO_BURSTS
axi_data_fifo_v2_1_axic_fifo #
(
.C_FAMILY(C_FAMILY),
.C_FIFO_DEPTH_LOG(C_FIFO_DEPTH_LOG),
.C_FIFO_WIDTH(C_AXI_ID_WIDTH),
.C_FIFO_TYPE("lut")
)
cmd_queue
(
.ACLK(ACLK),
.ARESET(ARESET),
.S_MESG({cmd_id_i}),
.S_VALID(cmd_push),
.S_READY(s_ready),
.M_MESG({cmd_id}),
.M_VALID(cmd_valid),
.M_READY(cmd_ready)
);
assign cmd_split = 1'b0;
assign cmd_length = 4'b0;
end
endgenerate
// Queue is concidered full when not ready.
assign cmd_full = ~s_ready;
// Queue is empty when no data at output port.
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_empty <= 1'b1;
cmd_depth <= {C_FIFO_DEPTH_LOG+1{1'b0}};
end else begin
if ( cmd_push & ~cmd_ready ) begin
// Push only => Increase depth.
cmd_depth <= cmd_depth + 1'b1;
cmd_empty <= 1'b0;
end else if ( ~cmd_push & cmd_ready ) begin
// Pop only => Decrease depth.
cmd_depth <= cmd_depth - 1'b1;
cmd_empty <= almost_empty;
end
end
end
assign almost_empty = ( cmd_depth == 1 );
/////////////////////////////////////////////////////////////////////////////
// Command Queue (B):
//
// Add command queue for B channel only when it is AW channel and both burst
// and splitting is supported.
//
// When turned off the command appears always empty.
//
/////////////////////////////////////////////////////////////////////////////
// Instantiated queue.
generate
if ( C_AXI_CHANNEL == 0 && C_SUPPORT_SPLITTING == 1 && C_SUPPORT_BURSTS == 1 ) begin : USE_B_CHANNEL
wire cmd_b_valid_i;
wire s_b_ready;
axi_data_fifo_v2_1_axic_fifo #
(
.C_FAMILY(C_FAMILY),
.C_FIFO_DEPTH_LOG(C_FIFO_DEPTH_LOG),
.C_FIFO_WIDTH(1+4),
.C_FIFO_TYPE("lut")
)
cmd_b_queue
(
.ACLK(ACLK),
.ARESET(ARESET),
.S_MESG({cmd_b_split_i, cmd_b_repeat_i}),
.S_VALID(cmd_b_push),
.S_READY(s_b_ready),
.M_MESG({cmd_b_split, cmd_b_repeat}),
.M_VALID(cmd_b_valid_i),
.M_READY(cmd_b_ready)
);
// Queue is concidered full when not ready.
assign cmd_b_full = ~s_b_ready;
// Queue is empty when no data at output port.
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_b_empty <= 1'b1;
cmd_b_depth <= {C_FIFO_DEPTH_LOG+1{1'b0}};
end else begin
if ( cmd_b_push & ~cmd_b_ready ) begin
// Push only => Increase depth.
cmd_b_depth <= cmd_b_depth + 1'b1;
cmd_b_empty <= 1'b0;
end else if ( ~cmd_b_push & cmd_b_ready ) begin
// Pop only => Decrease depth.
cmd_b_depth <= cmd_b_depth - 1'b1;
cmd_b_empty <= ( cmd_b_depth == 1 );
end
end
end
assign almost_b_empty = ( cmd_b_depth == 1 );
// Assign external signal.
assign cmd_b_valid = cmd_b_valid_i;
end else begin : NO_B_CHANNEL
// Assign external command signals.
assign cmd_b_valid = 1'b0;
assign cmd_b_split = 1'b0;
assign cmd_b_repeat = 4'b0;
// Assign internal command FIFO signals.
assign cmd_b_full = 1'b0;
assign almost_b_empty = 1'b0;
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_b_empty <= 1'b1;
cmd_b_depth <= {C_FIFO_DEPTH_LOG+1{1'b0}};
end else begin
// Constant FF due to ModelSim behavior.
cmd_b_empty <= 1'b1;
cmd_b_depth <= {C_FIFO_DEPTH_LOG+1{1'b0}};
end
end
end
endgenerate
/////////////////////////////////////////////////////////////////////////////
// MI-side output handling
//
/////////////////////////////////////////////////////////////////////////////
assign M_AXI_AID = M_AXI_AID_I;
assign M_AXI_AADDR = M_AXI_AADDR_I;
assign M_AXI_ALEN = M_AXI_ALEN_I;
assign M_AXI_ASIZE = M_AXI_ASIZE_I;
assign M_AXI_ABURST = M_AXI_ABURST_I;
assign M_AXI_ALOCK = M_AXI_ALOCK_I;
assign M_AXI_ACACHE = M_AXI_ACACHE_I;
assign M_AXI_APROT = M_AXI_APROT_I;
assign M_AXI_AQOS = M_AXI_AQOS_I;
assign M_AXI_AUSER = M_AXI_AUSER_I;
assign M_AXI_AVALID = M_AXI_AVALID_I;
assign M_AXI_AREADY_I = M_AXI_AREADY;
endmodule
|
module cia_timerb
(
input clk, // clock
input clk7_en,
input wr, // write enable
input reset, // reset
input tlo, // timer low byte select
input thi, // timer high byte select
input tcr, // timer control register
input [7:0] data_in, // bus data in
output [7:0] data_out, // bus data out
input eclk, // count enable
input tmra_ovf, // timer A underflow
output irq // intterupt out
);
reg [15:0] tmr; // timer
reg [7:0] tmlh; // timer latch high byte
reg [7:0] tmll; // timer latch low byte
reg [6:0] tmcr; // timer control register
reg forceload; // force load strobe
wire oneshot; // oneshot mode
wire start; // timer start (enable)
reg thi_load; // load tmr after writing thi in one-shot mode
wire reload; // reload timer counter
wire zero; // timer counter is zero
wire underflow; // timer is going to underflow
wire count; // count enable signal
// Timer B count signal source
assign count = tmcr[6] ? tmra_ovf : eclk;
// writing timer control register
always @(posedge clk)
if (clk7_en) begin
if (reset) // synchronous reset
tmcr[6:0] <= 7'd0;
else if (tcr && wr) // load control register, bit 4(strobe) is always 0
tmcr[6:0] <= {data_in[6:5],1'b0,data_in[3:0]};
else if (thi_load && oneshot) // start timer if thi is written in one-shot mode
tmcr[0] <= 1'd1;
else if (underflow && oneshot) // stop timer in one-shot mode
tmcr[0] <= 1'd0;
end
always @(posedge clk)
if (clk7_en) begin
forceload <= tcr & wr & data_in[4]; // force load strobe
end
assign oneshot = tmcr[3]; // oneshot alias
assign start = tmcr[0]; // start alias
// timer B latches for high and low byte
always @(posedge clk)
if (clk7_en) begin
if (reset)
tmll[7:0] <= 8'b1111_1111;
else if (tlo && wr)
tmll[7:0] <= data_in[7:0];
end
always @(posedge clk)
if (clk7_en) begin
if (reset)
tmlh[7:0] <= 8'b1111_1111;
else if (thi && wr)
tmlh[7:0] <= data_in[7:0];
end
// thi is written in one-shot mode so tmr must be reloaded
always @(posedge clk)
if (clk7_en) begin
thi_load <= thi & wr & (~start | oneshot);
end
// timer counter reload signal
assign reload = thi_load | forceload | underflow;
// timer counter
always @(posedge clk)
if (clk7_en) begin
if (reset)
tmr[15:0] <= 16'hFF_FF;
else if (reload)
tmr[15:0] <= {tmlh[7:0],tmll[7:0]};
else if (start && count)
tmr[15:0] <= tmr[15:0] - 16'd1;
end
// timer counter equals zero
assign zero = ~|tmr;
// timer counter is going to underflow
assign underflow = zero & start & count;
// timer underflow interrupt request
assign irq = underflow;
// data output
assign data_out[7:0] = ({8{~wr&tlo}} & tmr[7:0])
| ({8{~wr&thi}} & tmr[15:8])
| ({8{~wr&tcr}} & {1'b0,tmcr[6:0]});
endmodule
|
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
//
// Revision Control Information
//
// $RCSfile: altera_tse_mac_pcs_pma_gige.v,v $
// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/RTL/Top_level_modules/altera_tse_mac_pcs_pma_gige.v,v $
//
// $Revision: #1 $
// $Date: 2010/01/07 $
// Check in by : $Author: max $
// Author : Arul Paniandi
//
// Project : Triple Speed Ethernet
//
// Description :
//
// Top level MAC + PCS + PMA module for Triple Speed Ethernet MAC + PCS + PMA
//
// ALTERA Confidential and Proprietary
// Copyright 2006 (c) Altera Corporation
// All rights reserved
//
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
//Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
(*altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION OFF" } *)
module altera_tse_mac_pcs_pma_gige /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R102,R105,D102,D101,D103\"" */(
// inputs:
address,
clk,
ff_rx_clk,
ff_rx_rdy,
ff_tx_clk,
ff_tx_crc_fwd,
ff_tx_data,
ff_tx_mod,
ff_tx_eop,
ff_tx_err,
ff_tx_sop,
ff_tx_wren,
gxb_cal_blk_clk,
gxb_pwrdn_in,
magic_sleep_n,
mdio_in,
read,
reconfig_clk,
reconfig_togxb,
ref_clk,
reset,
rxp,
write,
writedata,
xoff_gen,
xon_gen,
// outputs:
ff_rx_a_empty,
ff_rx_a_full,
ff_rx_data,
ff_rx_mod,
ff_rx_dsav,
ff_rx_dval,
ff_rx_eop,
ff_rx_sop,
ff_tx_a_empty,
ff_tx_a_full,
ff_tx_rdy,
ff_tx_septy,
led_an,
led_char_err,
led_col,
led_crs,
led_disp_err,
led_link,
magic_wakeup,
mdc,
mdio_oen,
mdio_out,
pcs_pwrdn_out,
readdata,
reconfig_fromgxb,
rx_err,
rx_err_stat,
rx_frm_type,
tx_ff_uflow,
txp,
waitrequest
);
// Parameters to configure the core for different variations
// ---------------------------------------------------------
parameter ENABLE_ENA = 8; // Enable n-Bit Local Interface
parameter ENABLE_GMII_LOOPBACK = 1; // GMII_LOOPBACK_ENA : Enable GMII Loopback Logic
parameter ENABLE_HD_LOGIC = 1; // HD_LOGIC_ENA : Enable Half Duplex Logic
parameter USE_SYNC_RESET = 1; // Use Synchronized Reset Inputs
parameter ENABLE_SUP_ADDR = 1; // SUP_ADDR_ENA : Enable Supplemental Addresses
parameter ENA_HASH = 1; // ENA_HASH Enable Hask Table
parameter STAT_CNT_ENA = 1; // STAT_CNT_ENA Enable Statistic Counters
parameter ENABLE_EXTENDED_STAT_REG = 0; // Enable a few extended statistic registers
parameter EG_FIFO = 256 ; // Egress FIFO Depth
parameter EG_ADDR = 8 ; // Egress FIFO Depth
parameter ING_FIFO = 256 ; // Ingress FIFO Depth
parameter ING_ADDR = 8 ; // Egress FIFO Depth
parameter RESET_LEVEL = 1'b 1 ; // Reset Active Level
parameter MDIO_CLK_DIV = 40 ; // Host Clock Division - MDC Generation
parameter CORE_VERSION = 16'h3; // MorethanIP Core Version
parameter CUST_VERSION = 1 ; // Customer Core Version
parameter REDUCED_INTERFACE_ENA = 1; // Enable the RGMII / MII Interface
parameter ENABLE_MDIO = 1; // Enable the MDIO Interface
parameter ENABLE_MAGIC_DETECT = 1; // Enable magic packet detection
parameter ENABLE_MACLITE = 0; // Enable MAC LITE operation
parameter MACLITE_GIGE = 0; // Enable/Disable Gigabit MAC operation for MAC LITE.
parameter CRC32DWIDTH = 4'b 1000; // input data width (informal, not for change)
parameter CRC32GENDELAY = 3'b 110; // when the data from the generator is valid
parameter CRC32CHECK16BIT = 1'b 0; // 1 compare two times 16 bit of the CRC (adds one pipeline step)
parameter CRC32S1L2_EXTERN = 1'b0; // false: merge enable
parameter ENABLE_SHIFT16 = 0; // Enable byte stuffing at packet header
parameter RAM_TYPE = "AUTO"; // Specify the RAM type
parameter INSERT_TA = 0; // Option to insert timing adapter for SOPC systems
parameter PHY_IDENTIFIER = 32'h 00000000;// PHY Identifier
parameter DEV_VERSION = 16'h 0001 ; // Customer Phy's Core Version
parameter ENABLE_SGMII = 1; // Enable SGMII logic for synthesis
parameter ENABLE_MAC_FLOW_CTRL = 1'b1; // Option to enable flow control
parameter ENABLE_MAC_TXADDR_SET = 1'b1; // Option to enable MAC address insertion onto 'to-be-transmitted' Ethernet frames on MAC TX data path
parameter ENABLE_MAC_RX_VLAN = 1'b1; // Option to enable VLAN tagged Ethernet frames on MAC RX data path
parameter ENABLE_MAC_TX_VLAN = 1'b1; // Option to enable VLAN tagged Ethernet frames on MAC TX data path
parameter EXPORT_PWRDN = 1'b0; // Option to export the Alt2gxb powerdown signal
parameter DEVICE_FAMILY = "ARRIAGX"; // The device family the the core is targetted for.
parameter TRANSCEIVER_OPTION = 1'b0; // Option to select transceiver block for MAC PCS PMA Instantiation. Valid Values are 0 and 1: 0 - GXB (GIGE Mode) 1 - LVDS I/O
parameter ENABLE_ALT_RECONFIG = 0; // Option to have the Alt_Reconfig ports exposed
parameter STARTING_CHANNEL_NUMBER = 0; // Starting Channel Number for Reconfig block
parameter SYNCHRONIZER_DEPTH = 3; // Number of synchronizer
output ff_rx_a_empty;
output ff_rx_a_full;
output [ENABLE_ENA-1:0] ff_rx_data;
output [1:0] ff_rx_mod;
output ff_rx_dsav;
output ff_rx_dval;
output ff_rx_eop;
output ff_rx_sop;
output ff_tx_a_empty;
output ff_tx_a_full;
output ff_tx_rdy;
output ff_tx_septy;
output led_an;
output led_char_err;
output led_col;
output led_crs;
output led_disp_err;
output led_link;
output magic_wakeup;
output mdc;
output mdio_oen;
output mdio_out;
output pcs_pwrdn_out;
output [31: 0] readdata;
output [16:0] reconfig_fromgxb;
output [5: 0] rx_err;
output [17: 0] rx_err_stat;
output [3: 0] rx_frm_type;
output tx_ff_uflow;
output txp;
output waitrequest;
input [7: 0] address;
input clk;
input ff_rx_clk;
input ff_rx_rdy;
input ff_tx_clk;
input ff_tx_crc_fwd;
input [ENABLE_ENA-1:0] ff_tx_data;
input [1:0] ff_tx_mod;
input ff_tx_eop;
input ff_tx_err;
input ff_tx_sop;
input ff_tx_wren;
input gxb_cal_blk_clk;
input gxb_pwrdn_in;
input magic_sleep_n;
input mdio_in;
input read;
input reconfig_clk;
input [3:0] reconfig_togxb;
input ref_clk;
input reset;
input rxp;
input write;
input [31:0] writedata;
input xoff_gen;
input xon_gen;
wire MAC_PCS_reset;
wire ff_rx_a_empty;
wire ff_rx_a_full;
wire [ENABLE_ENA-1:0] ff_rx_data;
wire [1:0] ff_rx_mod;
wire ff_rx_dsav;
wire ff_rx_dval;
wire ff_rx_eop;
wire ff_rx_sop;
wire ff_tx_a_empty;
wire ff_tx_a_full;
wire ff_tx_rdy;
wire ff_tx_septy;
wire gige_pma_reset;
wire led_an;
wire led_char_err;
wire led_char_err_gx;
wire led_col;
wire led_crs;
wire led_disp_err;
wire led_link;
wire link_status;
wire magic_wakeup;
wire mdc;
wire mdio_oen;
wire mdio_out;
wire pcs_clk;
wire [7:0] pcs_rx_frame;
wire pcs_rx_kchar;
wire pcs_pwrdn_out_sig;
wire gxb_pwrdn_in_sig;
wire gxb_cal_blk_clk_sig;
wire [31:0] readdata;
wire rx_char_err_gx;
wire rx_disp_err;
wire [5:0] rx_err;
wire [17:0] rx_err_stat;
wire [3:0] rx_frm_type;
wire [7:0] rx_frame;
wire rx_syncstatus;
wire rx_kchar;
wire sd_loopback;
wire tx_ff_uflow;
wire [7:0] tx_frame;
wire tx_kchar;
wire txp;
wire waitrequest;
wire rx_runlengthviolation;
wire rx_patterndetect;
wire rx_runningdisp;
wire rx_rmfifodatadeleted;
wire rx_rmfifodatainserted;
wire pcs_rx_carrierdetected;
wire pcs_rx_rmfifodatadeleted;
wire pcs_rx_rmfifodatainserted;
reg pma_digital_rst0;
reg pma_digital_rst1;
reg pma_digital_rst2;
wire [16:0] reconfig_fromgxb;
// Reset logic used to reset the PMA blocks
// ----------------------------------------
always @(posedge clk or posedge reset)
begin
if (reset == 1)
begin
pma_digital_rst0 <= reset;
pma_digital_rst1 <= reset;
pma_digital_rst2 <= reset;
end
else
begin
pma_digital_rst0 <= reset;
pma_digital_rst1 <= pma_digital_rst0;
pma_digital_rst2 <= pma_digital_rst1;
end
end
// Assign the digital reset of the PMA to the MAC_PCS logic
// --------------------------------------------------------
assign MAC_PCS_reset = pma_digital_rst2;
// Assign the character error and link status to top level leds
// ------------------------------------------------------------
assign led_char_err = led_char_err_gx;
assign led_link = link_status;
// Instantiation of the MAC_PCS core that connects to a PMA
// --------------------------------------------------------
altera_tse_mac_pcs_pma_strx_gx_ena altera_tse_mac_pcs_pma_strx_gx_ena_inst
(
.rx_carrierdetected(pcs_rx_carrierdetected),
.rx_rmfifodatadeleted(pcs_rx_rmfifodatadeleted),
.rx_rmfifodatainserted(pcs_rx_rmfifodatainserted),
.address (address),
.clk (clk),
.ff_rx_a_empty (ff_rx_a_empty),
.ff_rx_a_full (ff_rx_a_full),
.ff_rx_clk (ff_rx_clk),
.ff_rx_data (ff_rx_data),
.ff_rx_mod (ff_rx_mod),
.ff_rx_dsav (ff_rx_dsav),
.ff_rx_dval (ff_rx_dval),
.ff_rx_eop (ff_rx_eop),
.ff_rx_rdy (ff_rx_rdy),
.ff_rx_sop (ff_rx_sop),
.ff_tx_a_empty (ff_tx_a_empty),
.ff_tx_a_full (ff_tx_a_full),
.ff_tx_clk (ff_tx_clk),
.ff_tx_crc_fwd (ff_tx_crc_fwd),
.ff_tx_data (ff_tx_data),
.ff_tx_mod (ff_tx_mod),
.ff_tx_eop (ff_tx_eop),
.ff_tx_err (ff_tx_err),
.ff_tx_rdy (ff_tx_rdy),
.ff_tx_septy (ff_tx_septy),
.ff_tx_sop (ff_tx_sop),
.ff_tx_wren (ff_tx_wren),
.led_an (led_an),
.led_char_err (led_char_err_gx),
.led_col (led_col),
.led_crs (led_crs),
.led_link (link_status),
.magic_sleep_n (magic_sleep_n),
.magic_wakeup (magic_wakeup),
.mdc (mdc),
.mdio_in (mdio_in),
.mdio_oen (mdio_oen),
.mdio_out (mdio_out),
.powerdown (pcs_pwrdn_out_sig),
.read (read),
.readdata (readdata),
.reset (MAC_PCS_reset),
.rx_clkout (pcs_clk),
.rx_err (rx_err),
.rx_err_stat (rx_err_stat),
.rx_frame (pcs_rx_frame),
.rx_frm_type (rx_frm_type),
.rx_kchar (pcs_rx_kchar),
.sd_loopback (sd_loopback),
.tx_clkout (pcs_clk),
.tx_ff_uflow (tx_ff_uflow),
.tx_frame (tx_frame),
.tx_kchar (tx_kchar),
.waitrequest (waitrequest),
.write (write),
.writedata (writedata),
.xoff_gen (xoff_gen),
.xon_gen (xon_gen)
);
defparam
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_ENA = ENABLE_ENA,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_HD_LOGIC = ENABLE_HD_LOGIC,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_GMII_LOOPBACK = ENABLE_GMII_LOOPBACK,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.USE_SYNC_RESET = USE_SYNC_RESET,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_SUP_ADDR = ENABLE_SUP_ADDR,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENA_HASH = ENA_HASH,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.STAT_CNT_ENA = STAT_CNT_ENA,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_EXTENDED_STAT_REG = ENABLE_EXTENDED_STAT_REG,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.EG_FIFO = EG_FIFO,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.EG_ADDR = EG_ADDR,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ING_FIFO = ING_FIFO,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ING_ADDR = ING_ADDR,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.RESET_LEVEL = RESET_LEVEL,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.MDIO_CLK_DIV = MDIO_CLK_DIV,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.CORE_VERSION = CORE_VERSION,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.CUST_VERSION = CUST_VERSION,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.REDUCED_INTERFACE_ENA = REDUCED_INTERFACE_ENA,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_MDIO = ENABLE_MDIO,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_MAGIC_DETECT = ENABLE_MAGIC_DETECT,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_MACLITE = ENABLE_MACLITE,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.MACLITE_GIGE = MACLITE_GIGE,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.CRC32S1L2_EXTERN = CRC32S1L2_EXTERN,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.CRC32DWIDTH = CRC32DWIDTH,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.CRC32CHECK16BIT = CRC32CHECK16BIT,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.CRC32GENDELAY = CRC32GENDELAY,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_SHIFT16 = ENABLE_SHIFT16,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.INSERT_TA = INSERT_TA,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.RAM_TYPE = RAM_TYPE,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.PHY_IDENTIFIER = PHY_IDENTIFIER,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.DEV_VERSION = DEV_VERSION,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_SGMII = ENABLE_SGMII,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_MAC_FLOW_CTRL = ENABLE_MAC_FLOW_CTRL,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_MAC_TXADDR_SET = ENABLE_MAC_TXADDR_SET,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_MAC_RX_VLAN = ENABLE_MAC_RX_VLAN,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.SYNCHRONIZER_DEPTH = SYNCHRONIZER_DEPTH,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_MAC_TX_VLAN = ENABLE_MAC_TX_VLAN;
// Export powerdown signal or wire it internally
// ---------------------------------------------
generate if (EXPORT_PWRDN == 1)
begin
assign gxb_pwrdn_in_sig = gxb_pwrdn_in;
assign pcs_pwrdn_out = pcs_pwrdn_out_sig;
end
else
begin
assign gxb_pwrdn_in_sig = pcs_pwrdn_out_sig;
assign pcs_pwrdn_out = 1'b0;
end
endgenerate
// Instantiation of the Alt2gxb block as the PMA for Stratix_II_GX and ArriaGX devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync
(
.clk(pcs_clk),
.reset(MAC_PCS_reset),
//input (from alt2gxb)
.alt_dataout(rx_frame),
.alt_sync(rx_syncstatus),
.alt_disperr(rx_disp_err),
.alt_ctrldetect(rx_kchar),
.alt_errdetect(rx_char_err_gx),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted),
.alt_rmfifodatainserted(rx_rmfifodatainserted),
.alt_runlengthviolation(rx_runlengthviolation),
.alt_patterndetect(rx_patterndetect),
.alt_runningdisp(rx_runningdisp),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame),
.altpcs_sync(link_status),
.altpcs_disperr(led_disp_err),
.altpcs_ctrldetect(pcs_rx_kchar),
.altpcs_errdetect(led_char_err_gx),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted),
.altpcs_carrierdetect(pcs_rx_carrierdetected)
) ;
defparam
the_altera_tse_gxb_aligned_rxsync.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig),
.pll_inclk (ref_clk),
.reconfig_clk(reconfig_clk),
.reconfig_togxb(reconfig_togxb),
.reconfig_fromgxb(reconfig_fromgxb),
.rx_analogreset (reset),
.rx_cruclk (ref_clk),
.rx_ctrldetect (rx_kchar),
.rx_datain (rxp),
.rx_dataout (rx_frame),
.rx_digitalreset (pma_digital_rst2),
.rx_disperr (rx_disp_err),
.rx_errdetect (rx_char_err_gx),
.rx_patterndetect (rx_patterndetect),
.rx_rlv (rx_runlengthviolation),
.rx_seriallpbken (sd_loopback),
.rx_syncstatus (rx_syncstatus),
.tx_clkout (pcs_clk),
.tx_ctrlenable (tx_kchar),
.tx_datain (tx_frame),
.tx_dataout (txp),
.tx_digitalreset (pma_digital_rst2),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted),
.rx_rmfifodatainserted(rx_rmfifodatainserted),
.rx_runningdisp(rx_runningdisp)
);
defparam
the_altera_tse_gxb_gige_inst.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_inst.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER,
the_altera_tse_gxb_gige_inst.DEVICE_FAMILY = DEVICE_FAMILY;
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_fp_custom_add_ll(clock, enable, resetn, dataa, datab, result);
// This is a version of the adder with reduced latency.
input clock, enable, resetn;
input [31:0] dataa;
input [31:0] datab;
output [31:0] result;
// Total Latency = 8.
acl_fp_custom_add_core core(
.clock(clock),
.resetn(resetn),
.dataa(dataa),
.datab(datab),
.result(result),
.valid_in(),
.valid_out(),
.stall_in(),
.stall_out(),
.enable(enable));
defparam core.HIGH_LATENCY = 0;
defparam core.HIGH_CAPACITY = 0;
defparam core.FLUSH_DENORMS = 0;
defparam core.ROUNDING_MODE = 0;
defparam core.FINITE_MATH_ONLY = 0;
defparam core.REMOVE_STICKY = 0;
endmodule
|
/*
* Copyright (c) 2002 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This tests the rule in section 2.7.1:
* "Neither the leading backslash character nor the terminating
* white space is considered to be part of the identifier. There-
* fore, an escaped identifier \cpu3 is treated the same as a
* non escaped identifier cpu3."
*
* The cpu3 and \cpu3 notations are for the same object.
*/
module top;
reg \cpu3 ;
initial begin
cpu3 = 1;
$display("cpu3 == %b", \cpu3 );
if (top.\cpu3 !== cpu3) begin
$display("FAILED -- top.\cpu3 !== cpu3");
$finish;
end
if (\top .cpu3 !== \cpu3 ) begin
$display("FAILED -- \top .cpu3 !== cpu3");
$finish;
end
if (top.\cpu3 !== 1) begin
$display("FAILED -- top.\cpu3 !== 1");
$finish;
end
$display("PASSED");
end
endmodule // top
|
`timescale 1ns / 100ps
module sasc_brg(/*AUTOARG*/
// Outputs
sio_ce, sio_ce_x4,
// Inputs
clk, arst_n
);
output sio_ce; // baud rate
output sio_ce_x4; // baud rate x 4
input clk;
input arst_n;
reg sio_ce;
reg sio_ce_x4;
parameter br_38400_16MHz = 103; // 16e6 / (38400*4) = 104 = 103 + 1
`define BRX4pre &{brx4_cntr[6:5],brx4_cntr[2:0]}
reg [6:0] brx4_cntr;
reg [1:0] br_cntr;
always @ (posedge clk or negedge arst_n)
if (~arst_n)
brx4_cntr <= 0;
else if (`BRX4pre)
brx4_cntr <= 0;
else
brx4_cntr <= brx4_cntr + 1'b1;
always @ (posedge clk or negedge arst_n)
if (~arst_n)
br_cntr <= 0;
else if (`BRX4pre)
br_cntr <= br_cntr + 1'b1;
always @ (posedge clk or negedge arst_n)
if (~arst_n)
begin
sio_ce_x4 <= 1'b0;
sio_ce <= 1'b0;
end
else
begin
sio_ce_x4 <= `BRX4pre;
sio_ce <= (&br_cntr) & (`BRX4pre);
end
endmodule // sasc_brg
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2005,2006 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
`include "../../firmware/include/fpga_regs_common.v"
`include "../../firmware/include/fpga_regs_standard.v"
module io_pins
( inout wire [15:0] io_0, inout wire [15:0] io_1,
input wire [15:0] reg_0, input wire [15:0] reg_1,
input clock, input rx_reset, input tx_reset,
input [6:0] serial_addr, input [31:0] serial_data, input serial_strobe);
reg [15:0] io_0_oe,io_1_oe;
bidir_reg bidir_reg_0 (.tristate(io_0),.oe(io_0_oe),.reg_val(reg_0));
bidir_reg bidir_reg_1 (.tristate(io_1),.oe(io_1_oe),.reg_val(reg_1));
// Upper 16 bits are mask for lower 16
always @(posedge clock)
if(serial_strobe)
case(serial_addr)
`FR_OE_0 : io_0_oe
<= #1 (io_0_oe & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] );
`FR_OE_1 : io_1_oe
<= #1 (io_1_oe & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] );
endcase // case(serial_addr)
endmodule // io_pins
|
// Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2015.3 (win64) Build 1368829 Mon Sep 28 20:06:43 MDT 2015
// Date : Wed Mar 30 14:50:02 2016
// Host : DESKTOP-5FTSDRT running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// C:/Users/SKL/Desktop/ECE532/repo/streamed_encoder_ip_prj2/project_1.runs/mult_gen_0_synth_1/mult_gen_0_sim_netlist.v
// Design : mult_gen_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a200tsbg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "mult_gen_0,mult_gen_v12_0_9,{}" *) (* core_generation_info = "mult_gen_0,mult_gen_v12_0_9,{x_ipProduct=Vivado 2015.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=mult_gen,x_ipVersion=12.0,x_ipCoreRevision=9,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_VERBOSITY=0,C_MODEL_TYPE=0,C_OPTIMIZE_GOAL=1,C_XDEVICEFAMILY=artix7,C_HAS_CE=0,C_HAS_SCLR=0,C_LATENCY=0,C_A_WIDTH=33,C_A_TYPE=0,C_B_WIDTH=14,C_B_TYPE=0,C_OUT_HIGH=53,C_OUT_LOW=0,C_MULT_TYPE=1,C_CE_OVERRIDES_SCLR=0,C_CCM_IMP=0,C_B_VALUE=10000001,C_HAS_ZERO_DETECT=0,C_ROUND_OUTPUT=0,C_ROUND_PT=0}" *) (* downgradeipidentifiedwarnings = "yes" *)
(* x_core_info = "mult_gen_v12_0_9,Vivado 2015.3" *)
(* NotValidForBitStream *)
module mult_gen_0
(A,
B,
P);
(* x_interface_info = "xilinx.com:signal:data:1.0 a_intf DATA" *) input [32:0]A;
(* x_interface_info = "xilinx.com:signal:data:1.0 b_intf DATA" *) input [13:0]B;
(* x_interface_info = "xilinx.com:signal:data:1.0 p_intf DATA" *) output [53:0]P;
wire [32:0]A;
wire [13:0]B;
wire [53:0]P;
wire [47:0]NLW_U0_PCASC_UNCONNECTED;
wire [1:0]NLW_U0_ZERO_DETECT_UNCONNECTED;
(* C_A_TYPE = "0" *)
(* C_A_WIDTH = "33" *)
(* C_B_TYPE = "0" *)
(* C_B_VALUE = "10000001" *)
(* C_B_WIDTH = "14" *)
(* C_CCM_IMP = "0" *)
(* C_CE_OVERRIDES_SCLR = "0" *)
(* C_HAS_CE = "0" *)
(* C_HAS_SCLR = "0" *)
(* C_HAS_ZERO_DETECT = "0" *)
(* C_LATENCY = "0" *)
(* C_MODEL_TYPE = "0" *)
(* C_MULT_TYPE = "1" *)
(* C_OPTIMIZE_GOAL = "1" *)
(* C_OUT_HIGH = "53" *)
(* C_OUT_LOW = "0" *)
(* C_ROUND_OUTPUT = "0" *)
(* C_ROUND_PT = "0" *)
(* C_VERBOSITY = "0" *)
(* C_XDEVICEFAMILY = "artix7" *)
(* DONT_TOUCH *)
(* downgradeipidentifiedwarnings = "yes" *)
(* x_interface_info = "xilinx.com:signal:data:1.0 p_intf DATA" *)
mult_gen_0_mult_gen_v12_0_9 U0
(.A(A),
.B(B),
.CE(1'b1),
.CLK(1'b1),
.P(P),
.PCASC(NLW_U0_PCASC_UNCONNECTED[47:0]),
.SCLR(1'b0),
.ZERO_DETECT(NLW_U0_ZERO_DETECT_UNCONNECTED[1:0]));
endmodule
(* C_A_TYPE = "0" *) (* C_A_WIDTH = "33" *) (* C_B_TYPE = "0" *)
(* C_B_VALUE = "10000001" *) (* C_B_WIDTH = "14" *) (* C_CCM_IMP = "0" *)
(* C_CE_OVERRIDES_SCLR = "0" *) (* C_HAS_CE = "0" *) (* C_HAS_SCLR = "0" *)
(* C_HAS_ZERO_DETECT = "0" *) (* C_LATENCY = "0" *) (* C_MODEL_TYPE = "0" *)
(* C_MULT_TYPE = "1" *) (* C_OPTIMIZE_GOAL = "1" *) (* C_OUT_HIGH = "53" *)
(* C_OUT_LOW = "0" *) (* C_ROUND_OUTPUT = "0" *) (* C_ROUND_PT = "0" *)
(* C_VERBOSITY = "0" *) (* C_XDEVICEFAMILY = "artix7" *) (* ORIG_REF_NAME = "mult_gen_v12_0_9" *)
(* downgradeipidentifiedwarnings = "yes" *)
module mult_gen_0_mult_gen_v12_0_9
(CLK,
A,
B,
CE,
SCLR,
ZERO_DETECT,
P,
PCASC);
input CLK;
input [32:0]A;
input [13:0]B;
input CE;
input SCLR;
output [1:0]ZERO_DETECT;
output [53:0]P;
output [47:0]PCASC;
wire [32:0]A;
wire [13:0]B;
wire CE;
wire CLK;
wire [53:0]P;
wire [47:0]PCASC;
wire SCLR;
wire [1:0]ZERO_DETECT;
(* C_A_TYPE = "0" *)
(* C_A_WIDTH = "33" *)
(* C_B_TYPE = "0" *)
(* C_B_VALUE = "10000001" *)
(* C_B_WIDTH = "14" *)
(* C_CCM_IMP = "0" *)
(* C_CE_OVERRIDES_SCLR = "0" *)
(* C_HAS_CE = "0" *)
(* C_HAS_SCLR = "0" *)
(* C_HAS_ZERO_DETECT = "0" *)
(* C_LATENCY = "0" *)
(* C_MODEL_TYPE = "0" *)
(* C_MULT_TYPE = "1" *)
(* C_OPTIMIZE_GOAL = "1" *)
(* C_OUT_HIGH = "53" *)
(* C_OUT_LOW = "0" *)
(* C_ROUND_OUTPUT = "0" *)
(* C_ROUND_PT = "0" *)
(* C_VERBOSITY = "0" *)
(* C_XDEVICEFAMILY = "artix7" *)
(* downgradeipidentifiedwarnings = "yes" *)
mult_gen_0_mult_gen_v12_0_9_viv i_mult
(.A(A),
.B(B),
.CE(CE),
.CLK(CLK),
.P(P),
.PCASC(PCASC),
.SCLR(SCLR),
.ZERO_DETECT(ZERO_DETECT));
endmodule
`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "XILINX"
`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`pragma protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`pragma protect key_block
DndfBI7K3jXgN7GHRcECwyAER1W1Qh1PMsFelxk+HDT/ClV9Zo8izeECQIpMvK29OdY6SSkvB4qZ
+AYx/myMTw==
`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`pragma protect key_block
CdiSOlcZSDfE8CurfVdELYArX3+TnREZq8E2Yz6CqivQQWiw5RGxv4Gl7Au5kxChzGyLzNLvpmhT
ppQfKBpf+XrJYAfKx28pTmAx8X2waXhIlI0DeX8Ov4RDfCu2fd87Q/1t9q5AVlYHTpz7Pm37oQMC
BonWIfylGOa+liG14eQ=
`pragma protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
gt7F+PGAaFvQvayxMkye/PdntejydD0eqxluJporKL/eE7tO3gqhoJWrHr6EJ2JeFopjz8ez1QhZ
7fAYU5KG/SEWjH1mXWJASfakqz5iOx3/i4t+1xPIK6IS2CWsRDWrz7qcp4f25fwEKkNTRTb0kA3S
z037QRb6Gcl9T23pQbGxiebbA2gHBh4zigT1WwGjqx80nEVyADg7jOuLU2FeqX8nsBo4aya1AaGy
GqejeJaJ5IQ7EY9/zBAWE+DzyhN4Gv8mYP8lGSxa3Sth13PiRU0xsOZGac9yKFHDFVMpCjhoYAJR
tGl0wUk3TSBcSnsYqPGgP97x9w0OHGuDh5JvkA==
`pragma protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`pragma protect key_block
iuUGkiCJWqD6S+Ivv2+2YU4CYQvzOyv4L6Khf5yoSOlP+8rsrITJxR/snSS95M2cb2SYmzGxjaxu
2TAok7Q+ox5BAM9XQweWOfuwovlgJjHrloEcnxbtYORZwicYwSa91IutF7z8AhDo36QmuOnZx1Z9
NZoQDVYrfJs8Kz0Yenw=
`pragma protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
a8x2Lj9mmpL4v+zPKabbpGXEXECaXjvwa8IWoZyGK6gZzcKlusapcFQp2jYobjGuXoqhkYYp4ANR
/7TGF2cuIszd4V+i1ZZL4M5UXTQh9kLT8emsG5cwnR+Nehucye0a/SdOcbn6Pcg7yMce/+zpuuV0
ex4jlZMAsXf6i1il2ddPdtWT3k2AbR+Am3/f8ushp2fsmcGMgRVNtOOYROsCDX4KlRdas9YXlkq5
9d+ubkYzakIVQa0PQ0jQJQPW2/C1fKNsLisKy4kJNaDNwiXo2Ve5N6Qxb5irFP8wZ6iapscbnarw
DNy84LnVZiSVsU3OP8/S7YHAsdW5lukpeuJb8g==
`pragma protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
oHWnYLE0J5rZZEnXMuTAQxu9NgUolVXZM5hq9TvCFq0x5b12/jzoW51moxTIzUBj2smQ/sB1QlS7
m2fDrJuFXKoj/HCk0KONHoXlaXmLeXQqL6HYfKw/j2F2fFIBmmAhAJ5qyyPkPnlXCvkE7fsc67s3
qz8a+KKsHGqGWBdeF3lAT6y/10HKSeR6oGugaujjA2CDnjVv5Me6lAzz5C8lRfbolqR+3RNm4o5P
Ra7RJtGQz1ANkLxMLrxpjcw7kXNTLrC08BCVAukRWzPhr9a9wfHitoK0WlXx9s/o5jOgg3Z6WSqF
sJxU74LBWwstEEO17Re4mT3AJPySE6IUwgXMTw==
`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-PREC-RSA", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
TOeHEz07yLnXq1KJBe3T4/U/GnqIun+5rH/HHNrCFBzR8f6vv0/3ibUm4Q0u751Vz4zgT6mY9dpn
NRGcINFXmsrtx+Tw5cZMOIzm0+3+94aNVP/8Fs85Clits5pjzkEuEHGc3vAhYSh/6aZQhaCFj43V
UZgb6AgSy0Lx4Zg11FlApDSVfmru26YP/x2a7eLY5Yl1NzdHWZSC01PvpL3vV0hm6h91JJ+o85At
o4r32wVSfsSPD8b7LebjMB4Houv7LNpbCH9IReal4xeGEzFCrsKo40unNHiHU4OLfq+sJlg6qoT1
ou4EYtcmM1NFg2YzSpY6LxHBR3Gy3cnklzLJwA==
`pragma protect key_keyowner = "Synplicity", key_keyname= "SYNP05_001", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
lHB6n0R84hctVnXs2Km//0K1NUHPAIrlwuUmYJy+Jsop8FwVal49m7Ex+ziXjq4Be8snrMLu+JRE
Fv2GjMv1s9upl3mTUk0zGPXB/gRN9NdODiX/rC/xPv9TPva7ZqNZfn/oorLKZ1qrqfoOSAfGsknc
OXWmbjZBWVj5c2xpQxbWfeEIOK5wRxsaPnAQWbloWJKSL9+Zt+DI8fBTnVeKzLpuGCg5EQGoPzMA
Xdf6j6idXmrlTU/2jEH5ppPn/Kx6X8YcUEOJVDa2uQfqCuR3PuDnLwb72xDZk7Xcxfjgo3+Zy258
XHjstfxj89mgeTuAvCu/VuX6jA5Q7viSICrsmw==
`pragma protect data_method = "AES128-CBC"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 11280)
`pragma protect data_block
st22YR94QUc4wFmbqGRAjNJxJ7oAzpK1WXac1KoIcFiBEV6WKyGcb7lPS1a+SenAaianT2I8+7bH
uwbgH81hGPCG7pvROJu0cEdjsM7lBbg77VRjdCMq/fK7j0PzHgx29eUcxg3nxEaTF1VLIqxoH2Nj
u47MtqpPoj17zlujFa/Ve3h3Y7KPBl6fFSHLTp0Qfvep1EEMH1iKJ6q01BekSWM5PYdawPU7ucvt
YHziAOE5QBcsHfEPM1DoWZjt5ygRDFeL4VvevU1gj0tfYF7NrLJtQqoniZGtZyAVAJrrdA/uaWnM
wdQjYWhF9ctHJ1hKDI17XQQaxbng8Tm/vlqN+ysET8Zyi/OF9882TKCro84S5R4GxWBz1qOpnn2g
vnQqNfr/rnWfwQvxDNxX74PMLMIF4BVYpyQOT+LLqgPaBarQxlT+RRe4Rx+fEvqOL15Xi8mry1fr
2PGFoXePedgmXF5ZN2HI/pW4NgFTwcJlRfp1LsCLz/ZjpttHT5ejvBVNJloinWbwMGbt39cpkMl6
iK+7BimXSe9TzRr8ohychwvbe2JigHSjf9l/CDqWphONWoudk3wN8zvKtGHOJIV1UnOXcHBL/p1/
OtL1xE8Lbz7RmHsDab2NQS519wSe1/N9QqFYM8gvkUO7++1erImCRccszCEDpG0uD/ZwyrH4sj7/
E2pTv1htjk1AXg8zDY6wKeVB4/tJTCdwvjG3IqY6BxAJiqw6baUbTjflATpx5JkVS1OG1wz6VbTC
B9CdcpVK8UDNiNYAFbV+xt13xGbY3PP4yBH4lUaF11hfIEk53JJTFNkx+JTlVAo56TAXcN6KvD4b
jE/DmJdAqO8qJU2numZ4ODQ1ivf2v7s84nVIiW3vvoUC05DZwZTwDn21kgNt19Lr/92uoPEkBuJD
Y2Mz/gtxd+eEs8Ax6xX8Om3XkTr7+V00AdnFueSO7V+AoLip/KEevaufRsFgvksmbR3jMnKg80Ic
noDQTQQITXFjaB4avltCIkjtumBKAnaidRkROPfhZGBxMrBggn/LtwO5LctnX3PYsp4ulo+vK2N5
B4MGFONps6KxnCNdTwIGC3UsbthoabVBzfcdPngCE8MakRg+OXonMAtmJvVQPA1nW4afOMG/i967
z9WUNIoUdVRoyxBnwHiFvvI6iztbqerce9I8N4S5pkA0s5SdeMBH/KZGix1ixh/8M3X4tXLjDvbI
ximLkyt6tVMMmK1w0+7+LXqsWYlRmY+9Q8PjDPetHs7NEr5NBM4Iwg8c1WB5iuvhW0Qx50vXqnvs
EkADqUHJQoF64CxoEKSFH0Cd/dGiYhcskcEQzHj7gAcDfq1ArigGP5uzHoaBOYNYtdRuN1j5GHme
rmN1smwz6xRJeYg2ZjLvjvckXjkgL7MGaLwRQxWAOEVP8/aFLTNu+8b47704XCzuYzCRy5U+wtUC
39rzVyxkmTIdrAMrxaXK6GP2d9Kl//FYnQBvqOWIEWGRSdD/uVljcKgfREqBlfM+XhCPQQwXL7eX
njPTWF/F+u4YJQtsUgbM5J0zYfGKdk1w5TKbfGr/KnES0puEsWy2U0Nmo7vi+Mt4WiPJbsSsy8dU
+hjDfun3k0aa6YfIqLuqNEyBWxKgFjbCwZLHGeXxa7yx9qJBGte9a7Ipcgvv7FbSfIL79WK0tx+d
+0rpXRV9PQvd8aRG7XMyBe45cO19Z68qRDviBv0oK2zOCinaDfHdkDdyyeK3u4h2lYiw94AROZw+
Aakn++tWQFP7wpcWJhsww4Z23Ms4MzkpVXRUXixtQ/sVw2smpsFzBbepJdtEat+d5TSNAAgwCgDX
XDHqa9oE5rEMXbDxC5VubT54dOpjdXl5HK9du9P5tLz+nKMD1ODFrUbhuhfTB8HBGtEX4k1QCxyA
6jVkwhTAKQ3/8MvKxh63IARFvxw9E6HciiKRm2XgndoMlby32LJOJhmTZkNkShqfCE+gjKJci6wA
RLZ5ZF/MT/bKKRPtUU1PYK5yf7bQDyp2JHLRWs86l/MZViek7+1Nw7SQXRAlo7/WFPzL++LSQbRU
C7QhfoWOIwnVQ5PljOW8T+rECYRAVWmhrxllbJtbYDj3rpcH/RqhlcfL+4wPok//bv6V5qwlZ+vL
GO3rtS4fNssWDaWXmH0gOblEKOkwYhY5OCtlQ45jxBo0W72l1R9DS6CQaeLpeGAI3dKg8KE9oAwW
PjmL4GhGd1XMEhpGCqxiXTtAVFRUWgFoz2M+0wLcoor7Po+RHf7ZHp5LTnLIXL/w5I6vZzHcW2kr
QThRTTqivXN7sZkzGNcxDJ8qwQ3NbXWMVTmew+beoN/YzngZ5B9AWUjz6tfbBzyiQ2SgFnElH/1l
QoK26hGRS8780wDXXwAp3NJJ5d4YWAU7QO/eIg9/B3LVF2XLkGavWNA25otf9CvpT9o0wCuTlT/e
9XrSPgXbTDDz4naOUW3ir6sPbj6GFIO3gCzP35emqpgskt79BBYbVo61D+n5ViObhIJc1tqyMC9N
yKmwyVgOWyUXCJdrCaeiNdqKwPKm9jiWxZkeKif9fhq+1kXyNS1VinZaHN5VRr21Jqy/DGBOv0HB
Vn/CAVD8HxFbwCOOKCXk175msKcTI7aGFQpcXtOULa8u96e6iXcREPPRviZiJIy/g5AD1v4wtmTv
u986xGlKAKt/pUdCy5xSfl5zyjgT5q2N2l7WjpLQaQq2JucqYa84D/IOy7giBNyq00cPMmOqNuBe
aEYKl9LQYDZSmXmTE7PLIPCjRxPqPTjOvcgL9EJBccR+5tmtbC/agb23jN5U0As4EMI/wMbb3kDE
NpD/NkXZ1TuoXohJPbCvrGdm7ZQJbN4cKJAssgJqrxEYiuu/eIAvPW36J1LeokSG17nec9RDNmiZ
8HSTyv5MDvQd56wIowYBq/vBLPLjxJxg2XRHi2fIRljrIKC5pqRLMVUOBiVpfuHc5POOWCWQi+Bz
7I0q0LcrVJsLU1EiHp1QmJtZWaBNTLw2Nxvi4IQ342aGb/63ysz7s8SThpAisux6ZuRRDJmw4lCy
qDFmFLyveVdTeD944vqP9+7yksXzjCVlgOiG8tGvAXlCHntX+CSKtQ5PHXy8de9W6u3mXOtlNroC
ocsEaADZ4/H4DaEXQEZWosBb7IJToYsQVJhYRVVZR2MONJ8NNpP5OhDDbywCKB/qc1TeUpeRk6yF
NDck9gLgYROgURFCCEKKfbGn9wmmmfJFJQm1GMOMxKcao9lKXAbqW+tcLxpGFfQl9yTnAP3flApm
zncWS+XcaMPkhXci8IUVKYBTB38TAxukqppu3p+WoiYdWX6+ka3wuob+CG/gRwJlxPZIMDtY17vF
mKG5yxAxBBh7FaBJY09UKAPJzFSHPhF8tOp6eBlKe0j3L5CG0h5ceVsjgzvWpx0nPeOPhpzZ9Rbv
i5r3eoGzAEc8zxnNGtA6gEX7EJ4Zrser49hiUl4YNTZnvaNFMYRFwSZQ4mDVxa2y6QCYl/f2dk6H
R072l/XNUNoUJxK6/Wj3o89hHnz7X+lVQe9yb7ZSw81t/+ZhIrWyVL+NcLDvspskh4Hf94xTSJ3r
LZsGoKx0t8/HLvyCvi2uiHFhXi1Dck8+sjjPe1dgudLWskbGCoZQnr/bj1Q86oHHfOoZypuD6vgr
Lh4nbGpR0uvcXSrz4n+tiWFJAeqxbFDnesG0pW3B6fYKLwhBDXtfP4U+D1eczUfzcisGbIOUvzWw
EzavwuVtRuiWu5/mZP+vC79t6rRyYoijUthpIZePZxh5T9ZRQ7vgcmKHBqZFW9uu4oTChqSz88if
gL4IjCE52Pdk2F8TQ4tt7dhQw4g7nTPUDzwdMr/AmgPfJm5LvxJxagWavkOqMN0XoBBCq5UK4UT+
6rNQXUpdQA0IErw1GCF7mdRMmQ0mBjv9Orja/HJJPTzx3Em8tdpQM/6he0SZZKJnJUt6LKDlTtH6
9lmbVso9jAWcuR/T2nQpghiXsXw+EfWcv2DYQfX63fKFy4j+D/HPfBs8SN52662iN4Z0+8SrTEQQ
V9pQdYlixZ7AQMdK/VR0mMnfYYZzmEzGoJ+Ie5QjrHMBm7XCa39HndeTf78HSjuC5Shw3LTGjuB0
PO6iI2ZBVo+scxmtyPpgLU8hKHTnAan1fXwc/nZaMO39zx/ePZ9R2w11EMCRtsbIS8CKQrdSGZM8
YxuMchkm0rtavdKhCH0PoS3IlS1dRbh9x23lZ9rqIpqtNv4jlo/C4JEPKtTurnRSSbagUHmLL2BH
2aZN1hwsiFF3ep4EpgtdZTlk5hWDJc0izFGhL/pMyLwDdgrHn70AAs4FGspcF+l9jzUkYfVddDLX
kyNKkD/g7Q0PG3+4QLqtlIeba+MlOGBHd7HUPXqXoX1bN+bb2O4qavg0bkj4wJ/cKVBt//l0P2+F
D7bSpI63WYPUOrH3WQAQMWn/VDMn+jv3kIuemM63lRfywJRzNOR4RRwpy8k0DQyMJf9VAg0xV2UL
ZgF66XXCMF/b5pU9D1laVvmO0QRK+s+dKXP3Aq5TdYX8FHvPTEvD+8bYCZRf9JKUIiCqh+aV1qjG
BnAwgFrq2nPA8jdH6BLVmNwteIDdScYEcaUXSqtH+E8XQVVy+EEA2RAWo7UXXgYABXzT/TW9dvuk
pdHrH3SjDbWRBjH3yCsYLUzzo21TNWRoS+648B9ucHIF5XsP0p6Y0yWQvRZyDQC3vInYNf7wnmGx
nRfBxXA35hW2CSQKlY5NbPaqEbSvi5fD1HS1K2u9KHbmHlhFP65JZllydIrcagzmWIMHJTZSFc92
JBDhhh70C4FSv2WyrPp/56WCRgTrgKmkcdRtfH6Zf7KkvE1PkxDHucnqHWCNtAl/6MoL8ETfYbKL
o02yFnDTYuzGi1cxhOQPywx2Q0cDEy2Xn2aTtL1hLapOMx2tSmFdcLgBeHWz54tAO4b73mqwV9Xb
hZTf1s5GmQbXWoyK9j/UQoNXMqKW/DaJsPwoO0B4nBy2E+NtXNA672qXIUPR2uN38MjaDS/VR1MI
z2NAxB+R2JotTsUInEw41JeRE1srlrast2DH4qIaxc0iOfH0+M53QgwRodpENQ1NgO9AjfQ7sXbw
2KScDPeNHj/XklrUc4rTBBJ1l/tvKxMqwvTBPLKp3EIZ9gqwzkObhX5C+BUJu2YIa4//VYx3d+HH
hc5iJgZ0Va1EXiDshlId7xDi5LHlzalz38s+TCutbjrHaJLX3RbWEFE7YOsWPaE+bVu0Zm3AddDk
DMu+ep22X+p4ARS4cemeDjNL1S2eP3Pr7qVLjcLHve29KrLfW4McQM4PDiBaodgt9BwjiU8PrcuI
AuBCyaEAEQz3y8DE9673Sz7yD78MX4V02TysuguxIV75P49Ody9VoO9Vq8BxZA52KP62TmQ6QOs0
oQFe3aJwvzv/f+v79lP6VUJWqcCOha/KGvYwcessTTQ4aysgzWHz50cDSCM5k0im2jnx/W/N/Iez
AGF61xj9p6q2082tsfkdnptRVMei8pVUG1SMv718sGavUm0hPvBFVbWfCgMQ3fE1iGZFWLkBf0Pb
x212UH1tXxw7bOHrAZSDKrSnRS+msEmsWRcwgkpOP4m9vbtvGz8CzQwQae50ji8NIpDUYIcvf2QD
bgRZCaxwzyRgkfuScUzI26vBf49Fvb0VAZrpHGKClAN8r6cPuo9T7bJw1N7CjEqrSKdPZsPWZr8l
8iTwJg8ap74aKRcxA4FqX99+BHdg2x2WB85jm1H84FyAjaswEVN0b1DNWsTEmi9NeEZJXgacQf8T
zqYVAdzyKlaPY/Pd6Ik+ydGIo5G+R5dbT8zAspJN3r3p57RxaD4W5QGdMRyLSCvD4NmBLZX3KHhV
eGONtaxAu4kxMWEeOFBnubJz9lAC79sAsQ+I1JMXeDyzm+CSKy5DyIwWCAqojgk9816wmsuCboWC
3RkmbwXnSINsDBZyCKZYEOGBopEXEWJvktILxzbgkqvsvqjXWNjw/YHp7DvNpDOoZhKcmQ6LNE00
g/yM58geJM9R2OzQnBpIlZVoZlheMV+fyrlJqzULDI+nNMWssMLY3cwoEtOFkpK9KWnwhpYO6EOt
X60sYlEvQ0tgNDzy0fRnuwcQasX6cGYobZFVAWRk8/nQc4lToUvFYPla1EDO/dRq0E5+MrbAcmVz
KqU0sHWTviUVWkKdxk9+Rb2k3kSv6E0EbMFojGagQmNxmvFCXSx+HAeKMn/eiDinopVxp0onmHZq
XiOVt7xZJ2uLi2e2RflaY9jMG8Dy2/mFg4gF0QL0qH1tuna0zZvXft5FNLkXirS9Thvcex3LyByV
ivDmeuURjhBoMk83idgWNafai/xmEeDZQkreTpIQBvyDG39R9bxueEY9TebGDmdUT+zYPGSPwBnB
WUNAJecjoHRufpW1lu9Sf8GmPBxwIuOdLL7bUOZWjskexmkKmvx53epSuITIVWQhkY+FUYlnDnk9
ZLWi9o/EwNqpY7R0KYiAIRQF3RnTv0kDlb5s3HYVZbvaGrYI9OaBrPpeiyThti/DVrI9tSlhDzBm
tfUvlsa70sqemRYY3jaEU8/B1N+G+vWdOnxQybYrSGc4cSPG1zW1tz77UO/3OdrXbcfzi3jFbZNa
nVpGngm2G+Kad//b2rQ/eqZTF17g/N4E0T21MmCdSepLc1Q/AZBh5ACNzjcYYuWSgTarOZ0HYPvV
q0U0qJCs5ukTLXks5iLwJ6B1TjpSXrjRhlYTB3T9ojs+/CfhEathlRFe3OdDY3NDRXQUSYHdiWCr
X8s1WPcM3GYQbeFGLvfvfUz0hgmrcWl+bSZ1+YDRlldokxSWgdy27bcmQWegZ4MomCrLC3F7WC+g
S4MPtUHGlvWsb2S4uIBrUA4DUL3lw9OOu1/IfR6CBqPYCjYMox3ZYF0y3MNrN5E5qzoTJo8eGFCL
sJXsfSuVe9qsfcaPSNFGldCfMyI2NZQrrvbinRUgTvjkoxKd9Algmt799yf8SYxaFJy5wAcVc5f/
cL8VPUNiaos03OZl+CwF5On95cDZ9IE5kQgXGN32xgqwbL1D8o3AovZsutgZpCgzRwAv/JsNdv3W
j6j1qqSjsmZKcV2mJWa5k0KdAOz1/mq4yALwPUcbGmfWuZAHA1uaYBeliPnddzFmNRqJYIKxaNPT
LpiPCge3ds/zIYfoLw6W+31gsIIaZU5xsP58wJBvXQWwPaiN0OyoPQe3ObYHFQ9iB1rTzTCL6YnS
2jllo55agN4Fp+lgsNMyj54w9uACqVyi+8i3JBdCuzp1NLL59hwq/NOk0IkCGnTOCoWuvBkl2ODP
l8cZrsqBU3IJTNg60CYLTf66JkOH3wswB/YS5Ip4UGSal3CygVhP5J8EDYR/ubmj7s93Bsll4z/F
AajFfFgFpf9vC5PTdIi8Tk6YDCfdKUMHSrSqMiu29qibRrsz1jOwxDJK6mINZlpW6OmsJtjn4lUI
184Djc8OQh3Y56prAdHifHiOMvVC4k2dIEHYXN+R+mmPOHuCexrdNAeht6/EYHAexI2ufguKR1gC
mC7FAr0aOGGE1zzvWpgCX0N9xlUG6sWkxtAHOAcB2WMEw/L72oauj8XQYJLJg1q7I4xY0qnIfCad
fYeWEOabutGVKGh3pkrp1i9JxUC3ZM1ZQERz7nfpYICaHyrypa+VHLNSdePg42faY0GXUlwuFtg2
Ft5ITbLvF7DCRYzlg1y/eXas8vW8B3Uqrgclet6dlIidM5B/qBbqrYFswgLkVysC58bNW3f1+Ozm
V0EiW0/lwM3aA0NAKf3paREDxVv/nafxBhBZNwi99yBsZBBk2QDJ6k7coKGF5Z9t+jqFAZPDVi/O
VyAMIAxgmmZzqyk2RqUNimcV6dUxwS62LKB1mkxfAav0VoCDMOr0sStzB2gZlQHxN0/cLJMb4iHs
F+DSFA+rvL9YFLdy/37+GPEIztRfTrMLwjCOV76ellCkdvm9NydoIXPdwOX4edL5LrUDkBqDV5Zk
bAIrXHsSiDf1rDWQbOR8LjEZ093yWxP6aIzWtF/N3ufL77Xb1L7mRuoygLQhZrecJa9zYtMtVFR+
hIadG4HkvqGK30kyomw63qWj6Wc4/+xMmu3wnKOOBqZ0dYgbGjNhrqnlYli45Ct5uRZQSNtex1hu
JYep7tj+GV3LjPU1yGdYTAmSvHtrdMs+87/ceYJqsIH95JIV3CceOh1ElMJV1Lnrv2xR/Q27dnEP
fxlalcNTUga7B/ah18OyVIWoovlFuxoy5N+8IJGmVPxNW4I57zf2ViDIHu6Iz0Fc04s80Keyg4hg
9P8Qzpv5tWX/cxghIursAv+7X3LDK00stoEVuj9c0EdRxiMyCWeLUrXrL20t1rCMYdRJv2V4o7Aa
HKXpq5uZNc0ij25Hedh2vr3bBPidTl8jFMSvuFxsVZ64bTY2dIgZvFomb8YdwtJBDglSPRL5VpPR
LwbLqjdbzA5W7y/5IgtLxr4psTLtn0Lge1d++morj7pc4hho5IqW8UYZzRtVixk3li/q855+NSjO
DiXgXgfeo61n3vE7mVw3IQdwyUf2ibZO3QVyAkjPUuDlmat8d+gabE3SosbrxxPaQUXtZs/Ycbsb
BxW0xNRGNt6WUyvw76ocsdkKd9MYKtAPId3jrupOQ0rzYDO6oUNh+Kh0Va5rSLl0ijoa7Ryf/91n
gCuf4KsxpeSPJUWE9PbnePxVHpUsXEewOxCZmVYtQUsfo6/Y5N57FaB9lW3/JFaUNLZXiHNogRAB
k1RpnxBO63Pnvk2VAdfpr3ShUW7BQYucsYbXqagRautH49mPlxU9wA3S0mYqgarMe0gNOKdjIPiT
VJQMagPIbDbipuDM5KTsbS2fa4sbKqI4plrghLcEt0lwgTOwji6Lm5VDmCIceWjkX9nOcGde7gQN
wP/m5yo+ql/BNligVYufK8xlImfSCpbeWKYD8Q0SZ/MjMXkQ80s5T0oigor57dOeB75C8iPmmUEC
fldj3nVVE64EKNxxwmG6EOD62wHsj2EJdsNgSOaU+5hgK5SQAlsALv1rsiF0nYqM92/YWLnlNXbE
OlXtbHytutlNvlzg9orqHy0Mc1aAUX/YLJMGo6UtvhoQnHEjrctTq2AnART6SDrS48jIc/ExY9up
wWgRB6iSktjnEJBkQCEni0Odnpp222D3pvmPUKu7e/fcg4rqR/1zwRY6q4pOLfM30Dx1E05fL59I
cUG4/8msWcJOoniQY0Bh2x5jrb635eNVtjUGBs6g1b7WBip7JYHy3YqEeHqaH0QtT8+MJx26YuPZ
LfhlYoYuKwiBJlbenvazThRO8N+tiuyBUud79QGg31o1QjYRSKCpx7Os/fzXq0ZowqApfXTvpy7u
0ev2pjpgRQegfgq5wYNhpHdj1JWtj8bbWIdVss8E5xeYJ64Re7nS6YneMNYTjAoPecvVm3yK0lUK
67FNy8T3nMxE+IRuKXRXAmBmKwcuQhBSNQ8ghh9pC3SNrhvvEyODmDOQJfKQg0uE0rivUU4IgKHi
QKpeEGiB6NEkGdoE52O61/QU1bh3lYi7n15cozCN2H+1m/FWSzmmbSqN6p7wGzJgGU2NcwO6pAHL
9q6bg1+fBr40TF9MDALsXua8GfWchxf8HxUfxjCgyqL0BsUe7zd9tu3ijR07TkpiOlr/aGXfiY4r
VGmCdz7XoEJolp6E/iVzHTOADCWoRretTti2p8j1IeFJg4VvAit9iZy0WjkbmwdrFbNEUUy2YftE
5ZpQe2OjOMib8wD9tKK9qIrd9Wm9hnpF9NRU8+0Wd7ovQ2qk2lsL5LyzrsMDUqT1P5DX46cM0cV8
pOZB7cb7VYnY+pO9tQQih7zRadOGgSAz7NkZzfP46HfYaTtuD5iEntN0J+UAAeuRsoMm+wZ4U8/w
+ualPaGXamCn+kL58/U2RTa9eR0wPtvubtRIckA81JEQUGB4lCtSTc6xBn8CDf2kTDxAfoFxPNFZ
u7tvwoj/J5Rr3TuChtknbu5qeloQeJrmz0CZDNGX1Bd/DfdMLIfRgSr+OpheMi2UJVvmOEaq6pCq
4A7cI5ObSXqZYFIRY4JUge86eqvspfLg3OmtqGovqeF0nqHPivIzrys6kD8O0iIpjL2vgO1Ku75J
NgGPAtxP681mB9IxF4JRv4yb20r18seQ7TwC2xN7V5BsJvnbYwJrmy/irsJep2JmV7oeSqPF38is
Cw0beNvyQfOgatgxyfMELBtZmqMIqcsV+fBgIaWfZNtMiOJATKIiYA9LXZ0gnwtIWc0V+jbaXMuk
yMEplepRx1H49nCHLeOfTBZpN1rJ/XVpH06ihQKxir+RhHHrxkBb4O6fKOO7KUkho7iUfr+6MfQ2
QrF7zJLCpT1exwbMw5licpW3bsJfOJ3xHpJOix5v6OX5ny1cmnKb2hCs7VkvOM/njmTuJtw4xQcs
hTJyhfGVyKZC5tD0BB0KRD97+KrSVMFmpjFj0xrEl1AnQ4ejLi9TAMzNJ9b6P2BQ8h6b6X25Mnne
q3oAZ6YGKdXvBy6tXmeLR+0jZH7+A9/zcrzQhfOuZxDU2DDZlFcqHzOcYJDF1iLP6Wag66BcEiwE
rX9YCmHy2+n1cM5hFtJkkksL/eS0Z3ut94unJUT+U7iXWMSaFZHQeUl949sw/EOILetTFKy8j8V+
yQiluS+KslYqFTkZb7QYquk+pQDo0+3K9tOzFBLl6v550nF22X0y+RXzaXNCzvKBnqLr1/tEgFpN
ODobDoN3imb0cwZKdywy4yQJmRFx3/YZ5puB7y050JbXJ1nzmmWtNasuU4njmN48WC0+IZnRGrsr
LMpOXnCKx4GNE/umDGEbWvQRhpX5NEjNEzdz55MGSpI2dxQcUsExiru/Z8KhDn8wObdjz+t32kZa
oAxpWSDirbCsC5uL95vdyDUKdj2y+h+8L5dbWdni85u4m9cJ/GfU9Ynf3tRSgGiw3e82gs+D6eXV
XwjDB9CEpsNduQzFN0Bljzv0AYat2TCA26YZaxXAGlM5TMaivzpxUam+FCxpOAsl3nv/elL1uudW
JLJwUz0lLk1ZETihF8i9U2IZAKIVYeUuVWgi9BRdEAZo9X8matefQNXS9gr6vb4YFBjVUSfutyYr
0zLANr2dJ405tQMiT1xXDFrB498Y/sCWGED7yBc83iQM0zeqUw4/ZE/kDyYSnFBMF9pfMImeRF5A
QYR15cCXGwjR6hS5QZAcF2xUpsByHmzHU4rMCN03xdwFe7ulGh/aS5qYylHdBvjyIgLrY/saNKTw
5vUDjjJ8GbyPWj3MIinBznNB/ykDjIU8MJZHcYoLNih1gYf92Vgzc0VriklWwobh+ktE95w3OwfQ
Z4wyQF08P1yalsxuAsMfBmw7aUkQss7CDvasXvkmb+tT8ngkpAYc8KeZD7V9+7sAsBKj6l/bpy3J
h5vlruj00T0F9fh/1fbmzoQqVcSKIKDnzPlh1iuaWgMfmAH0k8YkXU9TJ4W829ABQybRDFqetvkK
RJQ36iraxeo6JJZlrFgidGWXctqeH5cTYjZYXa0vABODcqT5zD1nOcb6Ih3K2pl9qZLYUaYiEgdq
xtWZfi89wZKA6JJR72jV9z8jjq2VV+13piRsIkOOV6oKvqV6cxVerRwl6m+yNbSdIdFhGubKEEwU
1DNnEBGtEVMQ4yj1K36boghv2wmypyKtlbXr5YUdycqW+t/bbAxBistUb6jtH3fy0LRnrhArQtU/
TuXrxXlnBlY3ziAbCSH4CtCmbnCKS1JUhtVSO1p6sO9U3/xvMu1pWGIS/aEUfLAblLYzYBeULsGE
byBuvEisseyg7cQ4qjO6yyDcYDN9fsuIc8kLhlmPjr3sff0I0NfFUyliSh3CBHgmqRP8snGV2Lsz
lJb1jIOA6iGbolb7i8+/RtgHXsdrqPcbb0NYdFLBwDRz2WQ458EDAV/maQgvNA6TGwhzlU8o85y6
JBktjz6rcs1Q6ZgLiEN5eRGMnmyfKLy5wCNpRfjaLXdXXawGryaMLTNs5hasQfx/YrQp95BCquod
wUFvgUkN2SM9hwBcGI8X9ZkbedjWDnTeTjVnnboFOrqpaNKZL9bCawfKsv9EbSbJUH4VyiWF2QhW
Q4Qodca5DNJofnAqFOU0lKoJ6oUGI9hsA2hUIu5nZjM8QYHJ6xDFrRHCi7G5Y+EMTdQZHNV02dqD
onjGH43VelaaN+AMApbSuCKtg7AFP4HDAFcCYu6ViJ2HZxb7ebDjORzlDGajQwdK9+VFRMwAlApr
Slws057CaD95kKkAQ9WnWdQ1MS0h5TBDbXA9UZPavwlDbE+x05OhC5WAPfnYE3aEBULqO8/3kqAs
P5EhFDpBk4WEI6xF9cF2jq2wZwfn8ovA2xpL/HqLEhi5Qirx3OBjFs3EE4zOFRzvQRmJFx0XiDOF
ZcNnnuafkuZ5XoFApliJ3BHB3Dpcn2dsru/E3NbeSOdHD04Y6bRFQ051vaE0D67FPLy5Q0gpouJA
tprWY9xMFFD9SZmdH/x9B16+h+nTLwNjNXQnsv5uHkfikoaR3E8bjJ148fDzwnXsUTr8u0icBVrT
h1J1w8Rv7rDS6MBXPsCeyjmAzMX8kAAVb2+Yu/dw74/hnNwzPKHD4zQM9c3KE0gkzwh7AntPSEK3
gp45fefvOkTfE1OZvnVzDZM+zoHq+u7NjX3FOPlOWX0gjbShNCx1uspVmM4TTopVXHSjoyKuHVXc
bFMskZjxUyCSnK6NVHTfBUwUK4h+j/DYiiD4lsrjM42sZo/IP21RwCkX9rsT3R2dY5ystMzeBtTs
Nel8UlgFzxvOY5wQOWMP6itDBR0/R6Ve85+BcrbogHus2Ra5uusgOZHYnhBZhP6TgDsRtpDXMLTr
oFA0R6HFu6QWtRhiRVUCaHPU/lUu9T7xMDrAzah0hFutvEMiqVqRIv7CorHmtMg6hj+mPiw2NZHD
DtPjngLVhQNxdbYXeKPWnr0z1PAK7AqzESRrDpc1J5IJ1lXUeVdJCpJ0LtglTr5ITyDJ/cXKiB/E
5aY8ogjA1qsgdgEvxfHR18EDiT8XwWgD8/vP1oYDD66hJfislPIWbI+FsskqCPYwopRJQ+YJKCNp
Vl4naJgRUhj2efQDXjst3xjU8GHdOA8Omdu5/dZ+OG8uMx3dv8/Hmx8CCKjF5X9oHmH+Z5daBDIt
NlPB9xp91sxHvix0su6hvOPFM6Q6vuVQGqECmmby0ra3j926q4n7wqW4jj7vx+y9ImaE3g+LMTtn
xZMkvIgTbmU1FW74gGx9KpfwbtXRgC7r/W3JXzWpNqdm5U5CbpP5zK/O/BwzbWD1ixX54e1G1Hpg
DCKp3xmSBKFpaNjt0IRAMz5K6XGvOnNfTPvFHMEvHZ/iHOOc5pN/OYSGKAQS80/dhhBWu5RrmyJw
zsnhGezZ8M9B7LIe2kLSofJ1s0Ra2PBa8PIVJAi9/lKc46ubaDYFH3XyzJxgqMZrBXsIy72oTIlt
0bDKCc7Pq8A8NVqdhpr90B91Qqd/lj0eVShyBEu8uqNCLgPyYjXuR+NQQazrN3e/WKIOypQrBvZ1
LGvuiabxNxxvRwbqcmZc1eCgEEFzk8zqibsNl+K/G/+RMcIzzbtJCfepR25cKHylfURFfHS4wQDv
47YXfpdI8+aaIsZLrOqVoePtIbEHDzq+OdC0V+hM788KgMjOIjKl0IH9e3fWx4IGRMSnL89jVRLw
7VW7P6tE0wysm0BpGeQvS9IkY/3GiEPv7eQmSB91WSbpGZMmYIBD8P3cAIPTNQihblgKVVx3YVWx
sZN357YbPhgAg8Dreyrb64+06iucDqe9cY0tWm47iv00P6IsnfWWcIUAGEZ3FK0VBuGwsDBQEe6M
7hAZDbHYuiylIdNobX2D8C31LQ4QqWevcpE6Zc48lV22q2U/gCVEi1nH+/QNQ3wPfadvDTC5fOvM
0htnDWINI+Y7B1RtV4adJ4+xzChHwQTpdEXn6oLeAEvR85cULh0poub7qbYJuZ6uFE7MTMBtd+uF
8tTmlBl2QC56M07XZ/aUzOV4U+yo58seOMBtAk3H2bevt83awTVUqqi8KlEjuWim3fcNPQawAzuG
VKf+yrHyAT7nOp3SiB/L86PpYaOrl6TtXXnksc6H0ED4nZbw+EYWD9uULZzkO6oZYCuvTY/Jdmpv
O8zUDlUVSqjmcbvB/dnbckJO0wv23T5iptpkdepS6vmyzfQ/XvqCQu2+xgqcvPeY2jUfy9yas1/E
DFputwQcUGdIAkLmhVQPxCW68ggmpKs3tMznRRG+RpPchunMR2Z0qTVBpd+Ug7GDcUnewCUxgCPE
PYZuQ9ftzf27e3lBEk708nFs1gP7wfm1mECqTe3pd8G61hUim/FYnVwHomo3EN4XvpbRIE4o89pW
h7eYC+y3saQtSzXJPb8m3v842V4pWpIeetwSLe1dSP95/bEmQqYAA2UkmGcJuQsmUtfeLaFZHXpZ
bRd4/7IFnVWo7ArejVfNOeqYnl40jpLx9BV7OONd1Z9lP/Z8X4GoTTK3JaZouStP/3z8p5s/+97D
FfmdHenYRjJm8ov0PFs3ZHcRBFWh+CtO9rsLsPHqxtESSIQGLAHb3dQcLzLCv8Q5AUfqQztZhyXs
6HVFZWS5EzUrlc5h0j8NrSTN1gtC65hKum/JHklbqHS6MIam5x7hXwLR7gRJPgOP50/oyrTCRlE7
pPkLZi6LyCg8DKEzcwm3Aa9CveK7hwsM9bTbq8SNv1/JESPZCDzDhasOaOT6W4rycIxuGvc1ynEq
8SE5Gs2rZNPJbk3DaPpbOa8iOHcXLcukVaLq+TFWsGjv3XcdC3vhNbgQGFhdc9GwfdDm5CCbFVky
+Pe+CV+ygfPBZPjBFanGtSl8fE51P+ZD7281/rk3QhIHMo92bM+6XRU6gyV3ekQ9uoNJ9+EfIyeq
Z8tukbjGK1sXKRXqz0bKg+qpvyQduWtHzTEDCMx0wLiWJAr6Rcn66GPD3Jxe4BckmnLt0bHqBoZv
3m5BnK9MZXvE/JwArYAbxkH0k6+j/kbS8AHKxq3CFZXxEGn63jbk3ibf2mYyrMO39SJV
`pragma protect end_protected
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/15.1/ip/merlin/altera_reset_controller/altera_reset_synchronizer.v#1 $
// $Revision: #1 $
// $Date: 2015/08/09 $
// $Author: swbranch $
// -----------------------------------------------
// Reset Synchronizer
// -----------------------------------------------
`timescale 1 ns / 1 ns
module altera_reset_synchronizer
#(
parameter ASYNC_RESET = 1,
parameter DEPTH = 2
)
(
input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */,
input clk,
output reset_out
);
// -----------------------------------------------
// Synchronizer register chain. We cannot reuse the
// standard synchronizer in this implementation
// because our timing constraints are different.
//
// Instead of cutting the timing path to the d-input
// on the first flop we need to cut the aclr input.
//
// We omit the "preserve" attribute on the final
// output register, so that the synthesis tool can
// duplicate it where needed.
// -----------------------------------------------
(*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain;
reg altera_reset_synchronizer_int_chain_out;
generate if (ASYNC_RESET) begin
// -----------------------------------------------
// Assert asynchronously, deassert synchronously.
// -----------------------------------------------
always @(posedge clk or posedge reset_in) begin
if (reset_in) begin
altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}};
altera_reset_synchronizer_int_chain_out <= 1'b1;
end
else begin
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
altera_reset_synchronizer_int_chain[DEPTH-1] <= 0;
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
end
end
assign reset_out = altera_reset_synchronizer_int_chain_out;
end else begin
// -----------------------------------------------
// Assert synchronously, deassert synchronously.
// -----------------------------------------------
always @(posedge clk) begin
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in;
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
end
assign reset_out = altera_reset_synchronizer_int_chain_out;
end
endgenerate
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's Debug Unit ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Basic OR1200 debug unit. ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.11 2005/01/07 09:35:08 andreje
// du_hwbkpt disabled when debug unit not implemented
//
// Revision 1.10 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.9.4.4 2004/02/11 01:40:11 lampret
// preliminary HW breakpoints support in debug unit (by default disabled). To enable define OR1200_DU_HWBKPTS.
//
// Revision 1.9.4.3 2004/01/18 10:08:00 simons
// Error fixed.
//
// Revision 1.9.4.2 2004/01/17 21:14:14 simons
// Errors fixed.
//
// Revision 1.9.4.1 2004/01/15 06:46:38 markom
// interface to debug changed; no more opselect; stb-ack protocol
//
// Revision 1.9 2003/01/22 03:23:47 lampret
// Updated sensitivity list for trace buffer [only relevant for Xilinx FPGAs]
//
// Revision 1.8 2002/09/08 19:31:52 lampret
// Fixed a typo, reported by Taylor Su.
//
// Revision 1.7 2002/07/14 22:17:17 lampret
// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.
//
// Revision 1.6 2002/03/14 00:30:24 lampret
// Added alternative for critical path in DU.
//
// Revision 1.5 2002/02/11 04:33:17 lampret
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
//
// Revision 1.4 2002/01/28 01:16:00 lampret
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
//
// Revision 1.3 2002/01/18 07:56:00 lampret
// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
//
// Revision 1.2 2002/01/14 06:18:22 lampret
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.12 2001/11/30 18:58:00 simons
// Trap insn couses break after exits ex_insn.
//
// Revision 1.11 2001/11/23 08:38:51 lampret
// Changed DSR/DRR behavior and exception detection.
//
// Revision 1.10 2001/11/20 21:25:44 lampret
// Fixed dbg_is_o assignment width.
//
// Revision 1.9 2001/11/20 18:46:14 simons
// Break point bug fixed
//
// Revision 1.8 2001/11/18 08:36:28 lampret
// For GDB changed single stepping and disabled trap exception.
//
// Revision 1.7 2001/10/21 18:09:53 lampret
// Fixed sensitivity list.
//
// Revision 1.6 2001/10/14 13:12:09 lampret
// MP3 version.
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
//
// Debug unit
//
module or1200_du(
// RISC Internal Interface
clk, rst,
dcpu_cycstb_i, dcpu_we_i, dcpu_adr_i, dcpu_dat_lsu,
dcpu_dat_dc, icpu_cycstb_i,
ex_freeze, branch_op, ex_insn, id_pc,
spr_dat_npc, rf_dataw,
du_dsr, du_stall, du_addr, du_dat_i, du_dat_o,
du_read, du_write, du_except, du_hwbkpt,
spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
// External Debug Interface
dbg_stall_i, dbg_ewt_i, dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o,
dbg_stb_i, dbg_we_i, dbg_adr_i, dbg_dat_i, dbg_dat_o, dbg_ack_o
);
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_OPERAND_WIDTH;
//
// I/O
//
//
// RISC Internal Interface
//
input clk; // Clock
input rst; // Reset
input dcpu_cycstb_i; // LSU status
input dcpu_we_i; // LSU status
input [31:0] dcpu_adr_i; // LSU addr
input [31:0] dcpu_dat_lsu; // LSU store data
input [31:0] dcpu_dat_dc; // LSU load data
input [`OR1200_FETCHOP_WIDTH-1:0] icpu_cycstb_i; // IFETCH unit status
input ex_freeze; // EX stage freeze
input [`OR1200_BRANCHOP_WIDTH-1:0] branch_op; // Branch op
input [dw-1:0] ex_insn; // EX insn
input [31:0] id_pc; // insn fetch EA
input [31:0] spr_dat_npc; // Next PC (for trace)
input [31:0] rf_dataw; // ALU result (for trace)
output [`OR1200_DU_DSR_WIDTH-1:0] du_dsr; // DSR
output du_stall; // Debug Unit Stall
output [aw-1:0] du_addr; // Debug Unit Address
input [dw-1:0] du_dat_i; // Debug Unit Data In
output [dw-1:0] du_dat_o; // Debug Unit Data Out
output du_read; // Debug Unit Read Enable
output du_write; // Debug Unit Write Enable
input [12:0] du_except; // Exception masked by DSR
output du_hwbkpt; // Cause trap exception (HW Breakpoints)
input spr_cs; // SPR Chip Select
input spr_write; // SPR Read/Write
input [aw-1:0] spr_addr; // SPR Address
input [dw-1:0] spr_dat_i; // SPR Data Input
output [dw-1:0] spr_dat_o; // SPR Data Output
//
// External Debug Interface
//
input dbg_stall_i; // External Stall Input
input dbg_ewt_i; // External Watchpoint Trigger Input
output [3:0] dbg_lss_o; // External Load/Store Unit Status
output [1:0] dbg_is_o; // External Insn Fetch Status
output [10:0] dbg_wp_o; // Watchpoints Outputs
output dbg_bp_o; // Breakpoint Output
input dbg_stb_i; // External Address/Data Strobe
input dbg_we_i; // External Write Enable
input [aw-1:0] dbg_adr_i; // External Address Input
input [dw-1:0] dbg_dat_i; // External Data Input
output [dw-1:0] dbg_dat_o; // External Data Output
output dbg_ack_o; // External Data Acknowledge (not WB compatible)
//
// Some connections go directly from the CPU through DU to Debug I/F
//
`ifdef OR1200_DU_STATUS_UNIMPLEMENTED
assign dbg_lss_o = 4'b0000;
reg [1:0] dbg_is_o;
//
// Show insn activity (temp, must be removed)
//
always @(posedge clk or posedge rst)
if (rst)
dbg_is_o <= #1 2'b00;
else if (!ex_freeze &
~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]))
dbg_is_o <= #1 ~dbg_is_o;
`ifdef UNUSED
assign dbg_is_o = 2'b00;
`endif
`else
assign dbg_lss_o = dcpu_cycstb_i ? {dcpu_we_i, 3'b000} : 4'b0000;
assign dbg_is_o = {1'b0, icpu_cycstb_i};
`endif
assign dbg_wp_o = 11'b000_0000_0000;
assign dbg_dat_o = du_dat_i;
//
// Some connections go directly from Debug I/F through DU to the CPU
//
assign du_stall = dbg_stall_i;
assign du_addr = dbg_adr_i;
assign du_dat_o = dbg_dat_i;
assign du_read = dbg_stb_i && !dbg_we_i;
assign du_write = dbg_stb_i && dbg_we_i;
//
// Generate acknowledge -- just delay stb signal
//
reg dbg_ack_o;
always @(posedge clk or posedge rst)
if (rst)
dbg_ack_o <= #1 1'b0;
else
dbg_ack_o <= #1 dbg_stb_i;
`ifdef OR1200_DU_IMPLEMENTED
//
// Debug Mode Register 1
//
`ifdef OR1200_DU_DMR1
reg [24:0] dmr1; // DMR1 implemented
`else
wire [24:0] dmr1; // DMR1 not implemented
`endif
//
// Debug Mode Register 2
//
`ifdef OR1200_DU_DMR2
reg [23:0] dmr2; // DMR2 implemented
`else
wire [23:0] dmr2; // DMR2 not implemented
`endif
//
// Debug Stop Register
//
`ifdef OR1200_DU_DSR
reg [`OR1200_DU_DSR_WIDTH-1:0] dsr; // DSR implemented
`else
wire [`OR1200_DU_DSR_WIDTH-1:0] dsr; // DSR not implemented
`endif
//
// Debug Reason Register
//
`ifdef OR1200_DU_DRR
reg [13:0] drr; // DRR implemented
`else
wire [13:0] drr; // DRR not implemented
`endif
//
// Debug Value Register N
//
`ifdef OR1200_DU_DVR0
reg [31:0] dvr0;
`else
wire [31:0] dvr0;
`endif
//
// Debug Value Register N
//
`ifdef OR1200_DU_DVR1
reg [31:0] dvr1;
`else
wire [31:0] dvr1;
`endif
//
// Debug Value Register N
//
`ifdef OR1200_DU_DVR2
reg [31:0] dvr2;
`else
wire [31:0] dvr2;
`endif
//
// Debug Value Register N
//
`ifdef OR1200_DU_DVR3
reg [31:0] dvr3;
`else
wire [31:0] dvr3;
`endif
//
// Debug Value Register N
//
`ifdef OR1200_DU_DVR4
reg [31:0] dvr4;
`else
wire [31:0] dvr4;
`endif
//
// Debug Value Register N
//
`ifdef OR1200_DU_DVR5
reg [31:0] dvr5;
`else
wire [31:0] dvr5;
`endif
//
// Debug Value Register N
//
`ifdef OR1200_DU_DVR6
reg [31:0] dvr6;
`else
wire [31:0] dvr6;
`endif
//
// Debug Value Register N
//
`ifdef OR1200_DU_DVR7
reg [31:0] dvr7;
`else
wire [31:0] dvr7;
`endif
//
// Debug Control Register N
//
`ifdef OR1200_DU_DCR0
reg [7:0] dcr0;
`else
wire [7:0] dcr0;
`endif
//
// Debug Control Register N
//
`ifdef OR1200_DU_DCR1
reg [7:0] dcr1;
`else
wire [7:0] dcr1;
`endif
//
// Debug Control Register N
//
`ifdef OR1200_DU_DCR2
reg [7:0] dcr2;
`else
wire [7:0] dcr2;
`endif
//
// Debug Control Register N
//
`ifdef OR1200_DU_DCR3
reg [7:0] dcr3;
`else
wire [7:0] dcr3;
`endif
//
// Debug Control Register N
//
`ifdef OR1200_DU_DCR4
reg [7:0] dcr4;
`else
wire [7:0] dcr4;
`endif
//
// Debug Control Register N
//
`ifdef OR1200_DU_DCR5
reg [7:0] dcr5;
`else
wire [7:0] dcr5;
`endif
//
// Debug Control Register N
//
`ifdef OR1200_DU_DCR6
reg [7:0] dcr6;
`else
wire [7:0] dcr6;
`endif
//
// Debug Control Register N
//
`ifdef OR1200_DU_DCR7
reg [7:0] dcr7;
`else
wire [7:0] dcr7;
`endif
//
// Debug Watchpoint Counter Register 0
//
`ifdef OR1200_DU_DWCR0
reg [31:0] dwcr0;
`else
wire [31:0] dwcr0;
`endif
//
// Debug Watchpoint Counter Register 1
//
`ifdef OR1200_DU_DWCR1
reg [31:0] dwcr1;
`else
wire [31:0] dwcr1;
`endif
//
// Internal wires
//
wire dmr1_sel; // DMR1 select
wire dmr2_sel; // DMR2 select
wire dsr_sel; // DSR select
wire drr_sel; // DRR select
wire dvr0_sel,
dvr1_sel,
dvr2_sel,
dvr3_sel,
dvr4_sel,
dvr5_sel,
dvr6_sel,
dvr7_sel; // DVR selects
wire dcr0_sel,
dcr1_sel,
dcr2_sel,
dcr3_sel,
dcr4_sel,
dcr5_sel,
dcr6_sel,
dcr7_sel; // DCR selects
wire dwcr0_sel,
dwcr1_sel; // DWCR selects
reg dbg_bp_r;
`ifdef OR1200_DU_HWBKPTS
reg [31:0] match_cond0_ct;
reg [31:0] match_cond1_ct;
reg [31:0] match_cond2_ct;
reg [31:0] match_cond3_ct;
reg [31:0] match_cond4_ct;
reg [31:0] match_cond5_ct;
reg [31:0] match_cond6_ct;
reg [31:0] match_cond7_ct;
reg match_cond0_stb;
reg match_cond1_stb;
reg match_cond2_stb;
reg match_cond3_stb;
reg match_cond4_stb;
reg match_cond5_stb;
reg match_cond6_stb;
reg match_cond7_stb;
reg match0;
reg match1;
reg match2;
reg match3;
reg match4;
reg match5;
reg match6;
reg match7;
reg wpcntr0_match;
reg wpcntr1_match;
reg incr_wpcntr0;
reg incr_wpcntr1;
reg [10:0] wp;
`endif
wire du_hwbkpt;
`ifdef OR1200_DU_READREGS
reg [31:0] spr_dat_o;
`endif
reg [13:0] except_stop; // Exceptions that stop because of DSR
`ifdef OR1200_DU_TB_IMPLEMENTED
wire tb_enw;
reg [7:0] tb_wadr;
reg [31:0] tb_timstmp;
`endif
wire [31:0] tbia_dat_o;
wire [31:0] tbim_dat_o;
wire [31:0] tbar_dat_o;
wire [31:0] tbts_dat_o;
//
// DU registers address decoder
//
`ifdef OR1200_DU_DMR1
assign dmr1_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DMR1));
`endif
`ifdef OR1200_DU_DMR2
assign dmr2_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DMR2));
`endif
`ifdef OR1200_DU_DSR
assign dsr_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DSR));
`endif
`ifdef OR1200_DU_DRR
assign drr_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DRR));
`endif
`ifdef OR1200_DU_DVR0
assign dvr0_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR0));
`endif
`ifdef OR1200_DU_DVR1
assign dvr1_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR1));
`endif
`ifdef OR1200_DU_DVR2
assign dvr2_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR2));
`endif
`ifdef OR1200_DU_DVR3
assign dvr3_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR3));
`endif
`ifdef OR1200_DU_DVR4
assign dvr4_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR4));
`endif
`ifdef OR1200_DU_DVR5
assign dvr5_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR5));
`endif
`ifdef OR1200_DU_DVR6
assign dvr6_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR6));
`endif
`ifdef OR1200_DU_DVR7
assign dvr7_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR7));
`endif
`ifdef OR1200_DU_DCR0
assign dcr0_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR0));
`endif
`ifdef OR1200_DU_DCR1
assign dcr1_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR1));
`endif
`ifdef OR1200_DU_DCR2
assign dcr2_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR2));
`endif
`ifdef OR1200_DU_DCR3
assign dcr3_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR3));
`endif
`ifdef OR1200_DU_DCR4
assign dcr4_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR4));
`endif
`ifdef OR1200_DU_DCR5
assign dcr5_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR5));
`endif
`ifdef OR1200_DU_DCR6
assign dcr6_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR6));
`endif
`ifdef OR1200_DU_DCR7
assign dcr7_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR7));
`endif
`ifdef OR1200_DU_DWCR0
assign dwcr0_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DWCR0));
`endif
`ifdef OR1200_DU_DWCR1
assign dwcr1_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DWCR1));
`endif
//
// Decode started exception
//
always @(du_except) begin
except_stop = 14'b0000_0000_0000;
casex (du_except)
13'b1_xxxx_xxxx_xxxx:
except_stop[`OR1200_DU_DRR_TTE] = 1'b1;
13'b0_1xxx_xxxx_xxxx: begin
except_stop[`OR1200_DU_DRR_IE] = 1'b1;
end
13'b0_01xx_xxxx_xxxx: begin
except_stop[`OR1200_DU_DRR_IME] = 1'b1;
end
13'b0_001x_xxxx_xxxx:
except_stop[`OR1200_DU_DRR_IPFE] = 1'b1;
13'b0_0001_xxxx_xxxx: begin
except_stop[`OR1200_DU_DRR_BUSEE] = 1'b1;
end
13'b0_0000_1xxx_xxxx:
except_stop[`OR1200_DU_DRR_IIE] = 1'b1;
13'b0_0000_01xx_xxxx: begin
except_stop[`OR1200_DU_DRR_AE] = 1'b1;
end
13'b0_0000_001x_xxxx: begin
except_stop[`OR1200_DU_DRR_DME] = 1'b1;
end
13'b0_0000_0001_xxxx:
except_stop[`OR1200_DU_DRR_DPFE] = 1'b1;
13'b0_0000_0000_1xxx:
except_stop[`OR1200_DU_DRR_BUSEE] = 1'b1;
13'b0_0000_0000_01xx: begin
except_stop[`OR1200_DU_DRR_RE] = 1'b1;
end
13'b0_0000_0000_001x: begin
except_stop[`OR1200_DU_DRR_TE] = 1'b1;
end
13'b0_0000_0000_0001:
except_stop[`OR1200_DU_DRR_SCE] = 1'b1;
default:
except_stop = 14'b0000_0000_0000;
endcase
end
//
// dbg_bp_o is registered
//
assign dbg_bp_o = dbg_bp_r;
//
// Breakpoint activation register
//
always @(posedge clk or posedge rst)
if (rst)
dbg_bp_r <= #1 1'b0;
else if (!ex_freeze)
dbg_bp_r <= #1 |except_stop
`ifdef OR1200_DU_DMR1_ST
| ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]) & dmr1[`OR1200_DU_DMR1_ST]
`endif
`ifdef OR1200_DU_DMR1_BT
| (branch_op != `OR1200_BRANCHOP_NOP) & dmr1[`OR1200_DU_DMR1_BT]
`endif
;
else
dbg_bp_r <= #1 |except_stop;
//
// Write to DMR1
//
`ifdef OR1200_DU_DMR1
always @(posedge clk or posedge rst)
if (rst)
dmr1 <= 25'h000_0000;
else if (dmr1_sel && spr_write)
`ifdef OR1200_DU_HWBKPTS
dmr1 <= #1 spr_dat_i[24:0];
`else
dmr1 <= #1 {1'b0, spr_dat_i[23:22], 22'h00_0000};
`endif
`else
assign dmr1 = 25'h000_0000;
`endif
//
// Write to DMR2
//
`ifdef OR1200_DU_DMR2
always @(posedge clk or posedge rst)
if (rst)
dmr2 <= 24'h00_0000;
else if (dmr2_sel && spr_write)
dmr2 <= #1 spr_dat_i[23:0];
`else
assign dmr2 = 24'h00_0000;
`endif
//
// Write to DSR
//
`ifdef OR1200_DU_DSR
always @(posedge clk or posedge rst)
if (rst)
dsr <= {`OR1200_DU_DSR_WIDTH{1'b0}};
else if (dsr_sel && spr_write)
dsr <= #1 spr_dat_i[`OR1200_DU_DSR_WIDTH-1:0];
`else
assign dsr = {`OR1200_DU_DSR_WIDTH{1'b0}};
`endif
//
// Write to DRR
//
`ifdef OR1200_DU_DRR
always @(posedge clk or posedge rst)
if (rst)
drr <= 14'b0;
else if (drr_sel && spr_write)
drr <= #1 spr_dat_i[13:0];
else
drr <= #1 drr | except_stop;
`else
assign drr = 14'b0;
`endif
//
// Write to DVR0
//
`ifdef OR1200_DU_DVR0
always @(posedge clk or posedge rst)
if (rst)
dvr0 <= 32'h0000_0000;
else if (dvr0_sel && spr_write)
dvr0 <= #1 spr_dat_i[31:0];
`else
assign dvr0 = 32'h0000_0000;
`endif
//
// Write to DVR1
//
`ifdef OR1200_DU_DVR1
always @(posedge clk or posedge rst)
if (rst)
dvr1 <= 32'h0000_0000;
else if (dvr1_sel && spr_write)
dvr1 <= #1 spr_dat_i[31:0];
`else
assign dvr1 = 32'h0000_0000;
`endif
//
// Write to DVR2
//
`ifdef OR1200_DU_DVR2
always @(posedge clk or posedge rst)
if (rst)
dvr2 <= 32'h0000_0000;
else if (dvr2_sel && spr_write)
dvr2 <= #1 spr_dat_i[31:0];
`else
assign dvr2 = 32'h0000_0000;
`endif
//
// Write to DVR3
//
`ifdef OR1200_DU_DVR3
always @(posedge clk or posedge rst)
if (rst)
dvr3 <= 32'h0000_0000;
else if (dvr3_sel && spr_write)
dvr3 <= #1 spr_dat_i[31:0];
`else
assign dvr3 = 32'h0000_0000;
`endif
//
// Write to DVR4
//
`ifdef OR1200_DU_DVR4
always @(posedge clk or posedge rst)
if (rst)
dvr4 <= 32'h0000_0000;
else if (dvr4_sel && spr_write)
dvr4 <= #1 spr_dat_i[31:0];
`else
assign dvr4 = 32'h0000_0000;
`endif
//
// Write to DVR5
//
`ifdef OR1200_DU_DVR5
always @(posedge clk or posedge rst)
if (rst)
dvr5 <= 32'h0000_0000;
else if (dvr5_sel && spr_write)
dvr5 <= #1 spr_dat_i[31:0];
`else
assign dvr5 = 32'h0000_0000;
`endif
//
// Write to DVR6
//
`ifdef OR1200_DU_DVR6
always @(posedge clk or posedge rst)
if (rst)
dvr6 <= 32'h0000_0000;
else if (dvr6_sel && spr_write)
dvr6 <= #1 spr_dat_i[31:0];
`else
assign dvr6 = 32'h0000_0000;
`endif
//
// Write to DVR7
//
`ifdef OR1200_DU_DVR7
always @(posedge clk or posedge rst)
if (rst)
dvr7 <= 32'h0000_0000;
else if (dvr7_sel && spr_write)
dvr7 <= #1 spr_dat_i[31:0];
`else
assign dvr7 = 32'h0000_0000;
`endif
//
// Write to DCR0
//
`ifdef OR1200_DU_DCR0
always @(posedge clk or posedge rst)
if (rst)
dcr0 <= 8'h00;
else if (dcr0_sel && spr_write)
dcr0 <= #1 spr_dat_i[7:0];
`else
assign dcr0 = 8'h00;
`endif
//
// Write to DCR1
//
`ifdef OR1200_DU_DCR1
always @(posedge clk or posedge rst)
if (rst)
dcr1 <= 8'h00;
else if (dcr1_sel && spr_write)
dcr1 <= #1 spr_dat_i[7:0];
`else
assign dcr1 = 8'h00;
`endif
//
// Write to DCR2
//
`ifdef OR1200_DU_DCR2
always @(posedge clk or posedge rst)
if (rst)
dcr2 <= 8'h00;
else if (dcr2_sel && spr_write)
dcr2 <= #1 spr_dat_i[7:0];
`else
assign dcr2 = 8'h00;
`endif
//
// Write to DCR3
//
`ifdef OR1200_DU_DCR3
always @(posedge clk or posedge rst)
if (rst)
dcr3 <= 8'h00;
else if (dcr3_sel && spr_write)
dcr3 <= #1 spr_dat_i[7:0];
`else
assign dcr3 = 8'h00;
`endif
//
// Write to DCR4
//
`ifdef OR1200_DU_DCR4
always @(posedge clk or posedge rst)
if (rst)
dcr4 <= 8'h00;
else if (dcr4_sel && spr_write)
dcr4 <= #1 spr_dat_i[7:0];
`else
assign dcr4 = 8'h00;
`endif
//
// Write to DCR5
//
`ifdef OR1200_DU_DCR5
always @(posedge clk or posedge rst)
if (rst)
dcr5 <= 8'h00;
else if (dcr5_sel && spr_write)
dcr5 <= #1 spr_dat_i[7:0];
`else
assign dcr5 = 8'h00;
`endif
//
// Write to DCR6
//
`ifdef OR1200_DU_DCR6
always @(posedge clk or posedge rst)
if (rst)
dcr6 <= 8'h00;
else if (dcr6_sel && spr_write)
dcr6 <= #1 spr_dat_i[7:0];
`else
assign dcr6 = 8'h00;
`endif
//
// Write to DCR7
//
`ifdef OR1200_DU_DCR7
always @(posedge clk or posedge rst)
if (rst)
dcr7 <= 8'h00;
else if (dcr7_sel && spr_write)
dcr7 <= #1 spr_dat_i[7:0];
`else
assign dcr7 = 8'h00;
`endif
//
// Write to DWCR0
//
`ifdef OR1200_DU_DWCR0
always @(posedge clk or posedge rst)
if (rst)
dwcr0 <= 32'h0000_0000;
else if (dwcr0_sel && spr_write)
dwcr0 <= #1 spr_dat_i[31:0];
else if (incr_wpcntr0)
dwcr0[`OR1200_DU_DWCR_COUNT] <= #1 dwcr0[`OR1200_DU_DWCR_COUNT] + 16'h0001;
`else
assign dwcr0 = 32'h0000_0000;
`endif
//
// Write to DWCR1
//
`ifdef OR1200_DU_DWCR1
always @(posedge clk or posedge rst)
if (rst)
dwcr1 <= 32'h0000_0000;
else if (dwcr1_sel && spr_write)
dwcr1 <= #1 spr_dat_i[31:0];
else if (incr_wpcntr1)
dwcr1[`OR1200_DU_DWCR_COUNT] <= #1 dwcr1[`OR1200_DU_DWCR_COUNT] + 16'h0001;
`else
assign dwcr1 = 32'h0000_0000;
`endif
//
// Read DU registers
//
`ifdef OR1200_DU_READREGS
always @(spr_addr or dsr or drr or dmr1 or dmr2
or dvr0 or dvr1 or dvr2 or dvr3 or dvr4
or dvr5 or dvr6 or dvr7
or dcr0 or dcr1 or dcr2 or dcr3 or dcr4
or dcr5 or dcr6 or dcr7
or dwcr0 or dwcr1
`ifdef OR1200_DU_TB_IMPLEMENTED
or tb_wadr or tbia_dat_o or tbim_dat_o
or tbar_dat_o or tbts_dat_o
`endif
)
casex (spr_addr[`OR1200_DUOFS_BITS]) // synopsys parallel_case
`ifdef OR1200_DU_DVR0
`OR1200_DU_DVR0:
spr_dat_o = dvr0;
`endif
`ifdef OR1200_DU_DVR1
`OR1200_DU_DVR1:
spr_dat_o = dvr1;
`endif
`ifdef OR1200_DU_DVR2
`OR1200_DU_DVR2:
spr_dat_o = dvr2;
`endif
`ifdef OR1200_DU_DVR3
`OR1200_DU_DVR3:
spr_dat_o = dvr3;
`endif
`ifdef OR1200_DU_DVR4
`OR1200_DU_DVR4:
spr_dat_o = dvr4;
`endif
`ifdef OR1200_DU_DVR5
`OR1200_DU_DVR5:
spr_dat_o = dvr5;
`endif
`ifdef OR1200_DU_DVR6
`OR1200_DU_DVR6:
spr_dat_o = dvr6;
`endif
`ifdef OR1200_DU_DVR7
`OR1200_DU_DVR7:
spr_dat_o = dvr7;
`endif
`ifdef OR1200_DU_DCR0
`OR1200_DU_DCR0:
spr_dat_o = {24'h00_0000, dcr0};
`endif
`ifdef OR1200_DU_DCR1
`OR1200_DU_DCR1:
spr_dat_o = {24'h00_0000, dcr1};
`endif
`ifdef OR1200_DU_DCR2
`OR1200_DU_DCR2:
spr_dat_o = {24'h00_0000, dcr2};
`endif
`ifdef OR1200_DU_DCR3
`OR1200_DU_DCR3:
spr_dat_o = {24'h00_0000, dcr3};
`endif
`ifdef OR1200_DU_DCR4
`OR1200_DU_DCR4:
spr_dat_o = {24'h00_0000, dcr4};
`endif
`ifdef OR1200_DU_DCR5
`OR1200_DU_DCR5:
spr_dat_o = {24'h00_0000, dcr5};
`endif
`ifdef OR1200_DU_DCR6
`OR1200_DU_DCR6:
spr_dat_o = {24'h00_0000, dcr6};
`endif
`ifdef OR1200_DU_DCR7
`OR1200_DU_DCR7:
spr_dat_o = {24'h00_0000, dcr7};
`endif
`ifdef OR1200_DU_DMR1
`OR1200_DU_DMR1:
spr_dat_o = {7'h00, dmr1};
`endif
`ifdef OR1200_DU_DMR2
`OR1200_DU_DMR2:
spr_dat_o = {8'h00, dmr2};
`endif
`ifdef OR1200_DU_DWCR0
`OR1200_DU_DWCR0:
spr_dat_o = dwcr0;
`endif
`ifdef OR1200_DU_DWCR1
`OR1200_DU_DWCR1:
spr_dat_o = dwcr1;
`endif
`ifdef OR1200_DU_DSR
`OR1200_DU_DSR:
spr_dat_o = {18'b0, dsr};
`endif
`ifdef OR1200_DU_DRR
`OR1200_DU_DRR:
spr_dat_o = {18'b0, drr};
`endif
`ifdef OR1200_DU_TB_IMPLEMENTED
`OR1200_DU_TBADR:
spr_dat_o = {24'h000000, tb_wadr};
`OR1200_DU_TBIA:
spr_dat_o = tbia_dat_o;
`OR1200_DU_TBIM:
spr_dat_o = tbim_dat_o;
`OR1200_DU_TBAR:
spr_dat_o = tbar_dat_o;
`OR1200_DU_TBTS:
spr_dat_o = tbts_dat_o;
`endif
default:
spr_dat_o = 32'h0000_0000;
endcase
`endif
//
// DSR alias
//
assign du_dsr = dsr;
`ifdef OR1200_DU_HWBKPTS
//
// Compare To What (Match Condition 0)
//
always @(dcr0 or id_pc or dcpu_adr_i or dcpu_dat_dc
or dcpu_dat_lsu or dcpu_we_i)
case (dcr0[`OR1200_DU_DCR_CT]) // synopsys parallel_case
3'b001: match_cond0_ct = id_pc; // insn fetch EA
3'b010: match_cond0_ct = dcpu_adr_i; // load EA
3'b011: match_cond0_ct = dcpu_adr_i; // store EA
3'b100: match_cond0_ct = dcpu_dat_dc; // load data
3'b101: match_cond0_ct = dcpu_dat_lsu; // store data
3'b110: match_cond0_ct = dcpu_adr_i; // load/store EA
default:match_cond0_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
endcase
//
// When To Compare (Match Condition 0)
//
always @(dcr0 or dcpu_cycstb_i)
case (dcr0[`OR1200_DU_DCR_CT]) // synopsys parallel_case
3'b000: match_cond0_stb = 1'b0; //comparison disabled
3'b001: match_cond0_stb = 1'b1; // insn fetch EA
default:match_cond0_stb = dcpu_cycstb_i; // any load/store
endcase
//
// Match Condition 0
//
always @(match_cond0_stb or dcr0 or dvr0 or match_cond0_ct)
casex ({match_cond0_stb, dcr0[`OR1200_DU_DCR_CC]})
4'b0_xxx,
4'b1_000,
4'b1_111: match0 = 1'b0;
4'b1_001: match0 =
((match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]) ==
(dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]));
4'b1_010: match0 =
((match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]) <
(dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]));
4'b1_011: match0 =
((match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]) <=
(dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]));
4'b1_100: match0 =
((match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]) >
(dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]));
4'b1_101: match0 =
((match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]) >=
(dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]));
4'b1_110: match0 =
((match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]) !=
(dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]));
endcase
//
// Watchpoint 0
//
always @(dmr1 or match0)
case (dmr1[`OR1200_DU_DMR1_CW0])
2'b00: wp[0] = match0;
2'b01: wp[0] = match0;
2'b10: wp[0] = match0;
2'b11: wp[0] = 1'b0;
endcase
//
// Compare To What (Match Condition 1)
//
always @(dcr1 or id_pc or dcpu_adr_i or dcpu_dat_dc
or dcpu_dat_lsu or dcpu_we_i)
case (dcr1[`OR1200_DU_DCR_CT]) // synopsys parallel_case
3'b001: match_cond1_ct = id_pc; // insn fetch EA
3'b010: match_cond1_ct = dcpu_adr_i; // load EA
3'b011: match_cond1_ct = dcpu_adr_i; // store EA
3'b100: match_cond1_ct = dcpu_dat_dc; // load data
3'b101: match_cond1_ct = dcpu_dat_lsu; // store data
3'b110: match_cond1_ct = dcpu_adr_i; // load/store EA
default:match_cond1_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
endcase
//
// When To Compare (Match Condition 1)
//
always @(dcr1 or dcpu_cycstb_i)
case (dcr1[`OR1200_DU_DCR_CT]) // synopsys parallel_case
3'b000: match_cond1_stb = 1'b0; //comparison disabled
3'b001: match_cond1_stb = 1'b1; // insn fetch EA
default:match_cond1_stb = dcpu_cycstb_i; // any load/store
endcase
//
// Match Condition 1
//
always @(match_cond1_stb or dcr1 or dvr1 or match_cond1_ct)
casex ({match_cond1_stb, dcr1[`OR1200_DU_DCR_CC]})
4'b0_xxx,
4'b1_000,
4'b1_111: match1 = 1'b0;
4'b1_001: match1 =
((match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]) ==
(dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]));
4'b1_010: match1 =
((match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]) <
(dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]));
4'b1_011: match1 =
((match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]) <=
(dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]));
4'b1_100: match1 =
((match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]) >
(dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]));
4'b1_101: match1 =
((match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]) >=
(dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]));
4'b1_110: match1 =
((match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]) !=
(dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]));
endcase
//
// Watchpoint 1
//
always @(dmr1 or match1 or wp)
case (dmr1[`OR1200_DU_DMR1_CW1])
2'b00: wp[1] = match1;
2'b01: wp[1] = match1 & wp[0];
2'b10: wp[1] = match1 | wp[0];
2'b11: wp[1] = 1'b0;
endcase
//
// Compare To What (Match Condition 2)
//
always @(dcr2 or id_pc or dcpu_adr_i or dcpu_dat_dc
or dcpu_dat_lsu or dcpu_we_i)
case (dcr2[`OR1200_DU_DCR_CT]) // synopsys parallel_case
3'b001: match_cond2_ct = id_pc; // insn fetch EA
3'b010: match_cond2_ct = dcpu_adr_i; // load EA
3'b011: match_cond2_ct = dcpu_adr_i; // store EA
3'b100: match_cond2_ct = dcpu_dat_dc; // load data
3'b101: match_cond2_ct = dcpu_dat_lsu; // store data
3'b110: match_cond2_ct = dcpu_adr_i; // load/store EA
default:match_cond2_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
endcase
//
// When To Compare (Match Condition 2)
//
always @(dcr2 or dcpu_cycstb_i)
case (dcr2[`OR1200_DU_DCR_CT]) // synopsys parallel_case
3'b000: match_cond2_stb = 1'b0; //comparison disabled
3'b001: match_cond2_stb = 1'b1; // insn fetch EA
default:match_cond2_stb = dcpu_cycstb_i; // any load/store
endcase
//
// Match Condition 2
//
always @(match_cond2_stb or dcr2 or dvr2 or match_cond2_ct)
casex ({match_cond2_stb, dcr2[`OR1200_DU_DCR_CC]})
4'b0_xxx,
4'b1_000,
4'b1_111: match2 = 1'b0;
4'b1_001: match2 =
((match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]) ==
(dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]));
4'b1_010: match2 =
((match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]) <
(dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]));
4'b1_011: match2 =
((match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]) <=
(dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]));
4'b1_100: match2 =
((match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]) >
(dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]));
4'b1_101: match2 =
((match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]) >=
(dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]));
4'b1_110: match2 =
((match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]) !=
(dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]));
endcase
//
// Watchpoint 2
//
always @(dmr1 or match2 or wp)
case (dmr1[`OR1200_DU_DMR1_CW2])
2'b00: wp[2] = match2;
2'b01: wp[2] = match2 & wp[1];
2'b10: wp[2] = match2 | wp[1];
2'b11: wp[2] = 1'b0;
endcase
//
// Compare To What (Match Condition 3)
//
always @(dcr3 or id_pc or dcpu_adr_i or dcpu_dat_dc
or dcpu_dat_lsu or dcpu_we_i)
case (dcr3[`OR1200_DU_DCR_CT]) // synopsys parallel_case
3'b001: match_cond3_ct = id_pc; // insn fetch EA
3'b010: match_cond3_ct = dcpu_adr_i; // load EA
3'b011: match_cond3_ct = dcpu_adr_i; // store EA
3'b100: match_cond3_ct = dcpu_dat_dc; // load data
3'b101: match_cond3_ct = dcpu_dat_lsu; // store data
3'b110: match_cond3_ct = dcpu_adr_i; // load/store EA
default:match_cond3_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
endcase
//
// When To Compare (Match Condition 3)
//
always @(dcr3 or dcpu_cycstb_i)
case (dcr3[`OR1200_DU_DCR_CT]) // synopsys parallel_case
3'b000: match_cond3_stb = 1'b0; //comparison disabled
3'b001: match_cond3_stb = 1'b1; // insn fetch EA
default:match_cond3_stb = dcpu_cycstb_i; // any load/store
endcase
//
// Match Condition 3
//
always @(match_cond3_stb or dcr3 or dvr3 or match_cond3_ct)
casex ({match_cond3_stb, dcr3[`OR1200_DU_DCR_CC]})
4'b0_xxx,
4'b1_000,
4'b1_111: match3 = 1'b0;
4'b1_001: match3 =
((match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]) ==
(dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]));
4'b1_010: match3 =
((match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]) <
(dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]));
4'b1_011: match3 =
((match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]) <=
(dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]));
4'b1_100: match3 =
((match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]) >
(dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]));
4'b1_101: match3 =
((match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]) >=
(dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]));
4'b1_110: match3 =
((match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]) !=
(dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]));
endcase
//
// Watchpoint 3
//
always @(dmr1 or match3 or wp)
case (dmr1[`OR1200_DU_DMR1_CW3])
2'b00: wp[3] = match3;
2'b01: wp[3] = match3 & wp[2];
2'b10: wp[3] = match3 | wp[2];
2'b11: wp[3] = 1'b0;
endcase
//
// Compare To What (Match Condition 4)
//
always @(dcr4 or id_pc or dcpu_adr_i or dcpu_dat_dc
or dcpu_dat_lsu or dcpu_we_i)
case (dcr4[`OR1200_DU_DCR_CT]) // synopsys parallel_case
3'b001: match_cond4_ct = id_pc; // insn fetch EA
3'b010: match_cond4_ct = dcpu_adr_i; // load EA
3'b011: match_cond4_ct = dcpu_adr_i; // store EA
3'b100: match_cond4_ct = dcpu_dat_dc; // load data
3'b101: match_cond4_ct = dcpu_dat_lsu; // store data
3'b110: match_cond4_ct = dcpu_adr_i; // load/store EA
default:match_cond4_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
endcase
//
// When To Compare (Match Condition 4)
//
always @(dcr4 or dcpu_cycstb_i)
case (dcr4[`OR1200_DU_DCR_CT]) // synopsys parallel_case
3'b000: match_cond4_stb = 1'b0; //comparison disabled
3'b001: match_cond4_stb = 1'b1; // insn fetch EA
default:match_cond4_stb = dcpu_cycstb_i; // any load/store
endcase
//
// Match Condition 4
//
always @(match_cond4_stb or dcr4 or dvr4 or match_cond4_ct)
casex ({match_cond4_stb, dcr4[`OR1200_DU_DCR_CC]})
4'b0_xxx,
4'b1_000,
4'b1_111: match4 = 1'b0;
4'b1_001: match4 =
((match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]) ==
(dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]));
4'b1_010: match4 =
((match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]) <
(dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]));
4'b1_011: match4 =
((match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]) <=
(dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]));
4'b1_100: match4 =
((match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]) >
(dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]));
4'b1_101: match4 =
((match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]) >=
(dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]));
4'b1_110: match4 =
((match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]) !=
(dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]));
endcase
//
// Watchpoint 4
//
always @(dmr1 or match4 or wp)
case (dmr1[`OR1200_DU_DMR1_CW4])
2'b00: wp[4] = match4;
2'b01: wp[4] = match4 & wp[3];
2'b10: wp[4] = match4 | wp[3];
2'b11: wp[4] = 1'b0;
endcase
//
// Compare To What (Match Condition 5)
//
always @(dcr5 or id_pc or dcpu_adr_i or dcpu_dat_dc
or dcpu_dat_lsu or dcpu_we_i)
case (dcr5[`OR1200_DU_DCR_CT]) // synopsys parallel_case
3'b001: match_cond5_ct = id_pc; // insn fetch EA
3'b010: match_cond5_ct = dcpu_adr_i; // load EA
3'b011: match_cond5_ct = dcpu_adr_i; // store EA
3'b100: match_cond5_ct = dcpu_dat_dc; // load data
3'b101: match_cond5_ct = dcpu_dat_lsu; // store data
3'b110: match_cond5_ct = dcpu_adr_i; // load/store EA
default:match_cond5_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
endcase
//
// When To Compare (Match Condition 5)
//
always @(dcr5 or dcpu_cycstb_i)
case (dcr5[`OR1200_DU_DCR_CT]) // synopsys parallel_case
3'b000: match_cond5_stb = 1'b0; //comparison disabled
3'b001: match_cond5_stb = 1'b1; // insn fetch EA
default:match_cond5_stb = dcpu_cycstb_i; // any load/store
endcase
//
// Match Condition 5
//
always @(match_cond5_stb or dcr5 or dvr5 or match_cond5_ct)
casex ({match_cond5_stb, dcr5[`OR1200_DU_DCR_CC]})
4'b0_xxx,
4'b1_000,
4'b1_111: match5 = 1'b0;
4'b1_001: match5 =
((match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]) ==
(dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]));
4'b1_010: match5 =
((match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]) <
(dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]));
4'b1_011: match5 =
((match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]) <=
(dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]));
4'b1_100: match5 =
((match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]) >
(dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]));
4'b1_101: match5 =
((match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]) >=
(dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]));
4'b1_110: match5 =
((match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]) !=
(dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]));
endcase
//
// Watchpoint 5
//
always @(dmr1 or match5 or wp)
case (dmr1[`OR1200_DU_DMR1_CW5])
2'b00: wp[5] = match5;
2'b01: wp[5] = match5 & wp[4];
2'b10: wp[5] = match5 | wp[4];
2'b11: wp[5] = 1'b0;
endcase
//
// Compare To What (Match Condition 6)
//
always @(dcr6 or id_pc or dcpu_adr_i or dcpu_dat_dc
or dcpu_dat_lsu or dcpu_we_i)
case (dcr6[`OR1200_DU_DCR_CT]) // synopsys parallel_case
3'b001: match_cond6_ct = id_pc; // insn fetch EA
3'b010: match_cond6_ct = dcpu_adr_i; // load EA
3'b011: match_cond6_ct = dcpu_adr_i; // store EA
3'b100: match_cond6_ct = dcpu_dat_dc; // load data
3'b101: match_cond6_ct = dcpu_dat_lsu; // store data
3'b110: match_cond6_ct = dcpu_adr_i; // load/store EA
default:match_cond6_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
endcase
//
// When To Compare (Match Condition 6)
//
always @(dcr6 or dcpu_cycstb_i)
case (dcr6[`OR1200_DU_DCR_CT]) // synopsys parallel_case
3'b000: match_cond6_stb = 1'b0; //comparison disabled
3'b001: match_cond6_stb = 1'b1; // insn fetch EA
default:match_cond6_stb = dcpu_cycstb_i; // any load/store
endcase
//
// Match Condition 6
//
always @(match_cond6_stb or dcr6 or dvr6 or match_cond6_ct)
casex ({match_cond6_stb, dcr6[`OR1200_DU_DCR_CC]})
4'b0_xxx,
4'b1_000,
4'b1_111: match6 = 1'b0;
4'b1_001: match6 =
((match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]) ==
(dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]));
4'b1_010: match6 =
((match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]) <
(dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]));
4'b1_011: match6 =
((match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]) <=
(dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]));
4'b1_100: match6 =
((match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]) >
(dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]));
4'b1_101: match6 =
((match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]) >=
(dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]));
4'b1_110: match6 =
((match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]) !=
(dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]));
endcase
//
// Watchpoint 6
//
always @(dmr1 or match6 or wp)
case (dmr1[`OR1200_DU_DMR1_CW6])
2'b00: wp[6] = match6;
2'b01: wp[6] = match6 & wp[5];
2'b10: wp[6] = match6 | wp[5];
2'b11: wp[6] = 1'b0;
endcase
//
// Compare To What (Match Condition 7)
//
always @(dcr7 or id_pc or dcpu_adr_i or dcpu_dat_dc
or dcpu_dat_lsu or dcpu_we_i)
case (dcr7[`OR1200_DU_DCR_CT]) // synopsys parallel_case
3'b001: match_cond7_ct = id_pc; // insn fetch EA
3'b010: match_cond7_ct = dcpu_adr_i; // load EA
3'b011: match_cond7_ct = dcpu_adr_i; // store EA
3'b100: match_cond7_ct = dcpu_dat_dc; // load data
3'b101: match_cond7_ct = dcpu_dat_lsu; // store data
3'b110: match_cond7_ct = dcpu_adr_i; // load/store EA
default:match_cond7_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
endcase
//
// When To Compare (Match Condition 7)
//
always @(dcr7 or dcpu_cycstb_i)
case (dcr7[`OR1200_DU_DCR_CT]) // synopsys parallel_case
3'b000: match_cond7_stb = 1'b0; //comparison disabled
3'b001: match_cond7_stb = 1'b1; // insn fetch EA
default:match_cond7_stb = dcpu_cycstb_i; // any load/store
endcase
//
// Match Condition 7
//
always @(match_cond7_stb or dcr7 or dvr7 or match_cond7_ct)
casex ({match_cond7_stb, dcr7[`OR1200_DU_DCR_CC]})
4'b0_xxx,
4'b1_000,
4'b1_111: match7 = 1'b0;
4'b1_001: match7 =
((match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]) ==
(dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]));
4'b1_010: match7 =
((match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]) <
(dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]));
4'b1_011: match7 =
((match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]) <=
(dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]));
4'b1_100: match7 =
((match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]) >
(dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]));
4'b1_101: match7 =
((match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]) >=
(dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]));
4'b1_110: match7 =
((match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]) !=
(dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]));
endcase
//
// Watchpoint 7
//
always @(dmr1 or match7 or wp)
case (dmr1[`OR1200_DU_DMR1_CW7])
2'b00: wp[7] = match7;
2'b01: wp[7] = match7 & wp[6];
2'b10: wp[7] = match7 | wp[6];
2'b11: wp[7] = 1'b0;
endcase
//
// Increment Watchpoint Counter 0
//
always @(wp or dmr2)
if (dmr2[`OR1200_DU_DMR2_WCE0])
incr_wpcntr0 = |(wp & ~dmr2[`OR1200_DU_DMR2_AWTC]);
else
incr_wpcntr0 = 1'b0;
//
// Match Condition Watchpoint Counter 0
//
always @(dwcr0)
if (dwcr0[`OR1200_DU_DWCR_MATCH] == dwcr0[`OR1200_DU_DWCR_COUNT])
wpcntr0_match = 1'b1;
else
wpcntr0_match = 1'b0;
//
// Watchpoint 8
//
always @(dmr1 or wpcntr0_match or wp)
case (dmr1[`OR1200_DU_DMR1_CW8])
2'b00: wp[8] = wpcntr0_match;
2'b01: wp[8] = wpcntr0_match & wp[7];
2'b10: wp[8] = wpcntr0_match | wp[7];
2'b11: wp[8] = 1'b0;
endcase
//
// Increment Watchpoint Counter 1
//
always @(wp or dmr2)
if (dmr2[`OR1200_DU_DMR2_WCE1])
incr_wpcntr1 = |(wp & dmr2[`OR1200_DU_DMR2_AWTC]);
else
incr_wpcntr1 = 1'b0;
//
// Match Condition Watchpoint Counter 1
//
always @(dwcr1)
if (dwcr1[`OR1200_DU_DWCR_MATCH] == dwcr1[`OR1200_DU_DWCR_COUNT])
wpcntr1_match = 1'b1;
else
wpcntr1_match = 1'b0;
//
// Watchpoint 9
//
always @(dmr1 or wpcntr1_match or wp)
case (dmr1[`OR1200_DU_DMR1_CW9])
2'b00: wp[9] = wpcntr1_match;
2'b01: wp[9] = wpcntr1_match & wp[8];
2'b10: wp[9] = wpcntr1_match | wp[8];
2'b11: wp[9] = 1'b0;
endcase
//
// Watchpoint 10
//
always @(dmr1 or dbg_ewt_i or wp)
case (dmr1[`OR1200_DU_DMR1_CW10])
2'b00: wp[10] = dbg_ewt_i;
2'b01: wp[10] = dbg_ewt_i & wp[9];
2'b10: wp[10] = dbg_ewt_i | wp[9];
2'b11: wp[10] = 1'b0;
endcase
`endif
//
// Watchpoints can cause trap exception
//
`ifdef OR1200_DU_HWBKPTS
assign du_hwbkpt = |(wp & dmr2[`OR1200_DU_DMR2_WGB]);
`else
assign du_hwbkpt = 1'b0;
`endif
`ifdef OR1200_DU_TB_IMPLEMENTED
//
// Simple trace buffer
// (right now hardcoded for Xilinx Virtex FPGAs)
//
// Stores last 256 instruction addresses, instruction
// machine words and ALU results
//
//
// Trace buffer write enable
//
assign tb_enw = ~ex_freeze & ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]);
//
// Trace buffer write address pointer
//
always @(posedge clk or posedge rst)
if (rst)
tb_wadr <= #1 8'h00;
else if (tb_enw)
tb_wadr <= #1 tb_wadr + 8'd1;
//
// Free running counter (time stamp)
//
always @(posedge clk or posedge rst)
if (rst)
tb_timstmp <= #1 32'h00000000;
else if (!dbg_bp_r)
tb_timstmp <= #1 tb_timstmp + 32'd1;
//
// Trace buffer RAMs
//
or1200_dpram_256x32 tbia_ram(
.clk_a(clk),
.rst_a(rst),
.addr_a(spr_addr[7:0]),
.ce_a(1'b1),
.oe_a(1'b1),
.do_a(tbia_dat_o),
.clk_b(clk),
.rst_b(rst),
.addr_b(tb_wadr),
.di_b(spr_dat_npc),
.ce_b(1'b1),
.we_b(tb_enw)
);
or1200_dpram_256x32 tbim_ram(
.clk_a(clk),
.rst_a(rst),
.addr_a(spr_addr[7:0]),
.ce_a(1'b1),
.oe_a(1'b1),
.do_a(tbim_dat_o),
.clk_b(clk),
.rst_b(rst),
.addr_b(tb_wadr),
.di_b(ex_insn),
.ce_b(1'b1),
.we_b(tb_enw)
);
or1200_dpram_256x32 tbar_ram(
.clk_a(clk),
.rst_a(rst),
.addr_a(spr_addr[7:0]),
.ce_a(1'b1),
.oe_a(1'b1),
.do_a(tbar_dat_o),
.clk_b(clk),
.rst_b(rst),
.addr_b(tb_wadr),
.di_b(rf_dataw),
.ce_b(1'b1),
.we_b(tb_enw)
);
or1200_dpram_256x32 tbts_ram(
.clk_a(clk),
.rst_a(rst),
.addr_a(spr_addr[7:0]),
.ce_a(1'b1),
.oe_a(1'b1),
.do_a(tbts_dat_o),
.clk_b(clk),
.rst_b(rst),
.addr_b(tb_wadr),
.di_b(tb_timstmp),
.ce_b(1'b1),
.we_b(tb_enw)
);
`else
assign tbia_dat_o = 32'h0000_0000;
assign tbim_dat_o = 32'h0000_0000;
assign tbar_dat_o = 32'h0000_0000;
assign tbts_dat_o = 32'h0000_0000;
`endif // OR1200_DU_TB_IMPLEMENTED
`else // OR1200_DU_IMPLEMENTED
//
// When DU is not implemented, drive all outputs as would when DU is disabled
//
assign dbg_bp_o = 1'b0;
assign du_dsr = {`OR1200_DU_DSR_WIDTH{1'b0}};
assign du_hwbkpt = 1'b0;
//
// Read DU registers
//
`ifdef OR1200_DU_READREGS
assign spr_dat_o = 32'h0000_0000;
`ifdef OR1200_DU_UNUSED_ZERO
`endif
`endif
`endif
endmodule
|
`default_nettype none
`define CLKFREQ 25000000 // frequency of incoming signal 'clk'
`define BAUD 115200
// Simple baud generator for transmitter
// ser_clk pulses at 115200 Hz
module baudgen(
input wire clk,
output wire ser_clk);
localparam lim = (`CLKFREQ / `BAUD) - 1;
localparam w = $clog2(lim);
wire [w-1:0] limit = lim;
reg [w-1:0] counter;
assign ser_clk = (counter == limit);
always @(posedge clk)
counter <= ser_clk ? 0 : (counter + 1);
endmodule
// For receiver, a similar baud generator.
//
// Need to restart the counter when the transmission starts
// Generate 2X the baud rate to allow sampling on bit boundary
// So ser_clk pulses at 2*115200 Hz
module baudgen2(
input wire clk,
input wire restart,
output wire ser_clk);
localparam lim = (`CLKFREQ / (2 * `BAUD)) - 1;
localparam w = $clog2(lim);
wire [w-1:0] limit = lim;
reg [w-1:0] counter;
assign ser_clk = (counter == limit);
always @(posedge clk)
if (restart)
counter <= 0;
else
counter <= ser_clk ? 0 : (counter + 1);
endmodule
/*
-----+ +-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+----
| | | | | | | | | | | |
|start| 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 |stop1|stop2|
| | | | | | | | | | | ? |
+-----+-----+-----+-----+-----+-----+-----+-----+-----+ +
*/
module uart(
input wire clk,
input wire resetq,
output wire uart_busy, // High means UART is transmitting
output reg uart_tx, // UART transmit wire
input wire uart_wr_i, // Raise to transmit byte
input wire [7:0] uart_dat_i
);
reg [3:0] bitcount; // 0 means idle, so this is a 1-based counter
reg [8:0] shifter;
assign uart_busy = |bitcount;
wire sending = |bitcount;
wire ser_clk;
baudgen _baudgen(
.clk(clk),
.ser_clk(ser_clk));
always @(negedge resetq or posedge clk)
begin
if (!resetq) begin
uart_tx <= 1;
bitcount <= 0;
shifter <= 0;
end else begin
if (uart_wr_i) begin
{ shifter, uart_tx } <= { uart_dat_i[7:0], 1'b0, 1'b1 };
bitcount <= 1 + 8 + 1; // 1 start, 8 data, 1 stop
end else if (ser_clk & sending) begin
{ shifter, uart_tx } <= { 1'b1, shifter };
bitcount <= bitcount - 4'd1;
end
end
end
endmodule
module rxuart(
input wire clk,
input wire resetq,
input wire uart_rx, // UART recv wire
input wire rd, // read strobe
output wire valid, // has data
output wire [7:0] data); // data
reg [4:0] bitcount;
reg [7:0] shifter;
// bitcount == 11111: idle
// 0-17: sampling incoming bits
// 18: character received
// On starting edge, wait 3 half-bits then sample, and sample every 2 bits thereafter
wire idle = &bitcount;
assign valid = (bitcount == 18);
wire sample;
reg [2:0] hh = 3'b111;
wire [2:0] hhN = {hh[1:0], uart_rx};
wire startbit = idle & (hhN[2:1] == 2'b10);
wire [7:0] shifterN = sample ? {hh[1], shifter[7:1]} : shifter;
wire ser_clk;
baudgen2 _baudgen(
.clk(clk),
.restart(startbit),
.ser_clk(ser_clk));
reg [4:0] bitcountN;
always @*
if (startbit)
bitcountN = 0;
else if (!idle & !valid & ser_clk)
bitcountN = bitcount + 5'd1;
else if (valid & rd)
bitcountN = 5'b11111;
else
bitcountN = bitcount;
// 3,5,7,9,11,13,15,17
assign sample = (|bitcount[4:1]) & bitcount[0] & ser_clk;
assign data = shifter;
always @(negedge resetq or posedge clk)
begin
if (!resetq) begin
hh <= 3'b111;
bitcount <= 5'b11111;
shifter <= 0;
end else begin
hh <= hhN;
bitcount <= bitcountN;
shifter <= shifterN;
end
end
endmodule
module buart(
input wire clk,
input wire resetq,
input wire rx, // recv wire
output wire tx, // xmit wire
input wire rd, // read strobe
input wire wr, // write strobe
output wire valid, // has recv data
output wire busy, // is transmitting
input wire [7:0] tx_data,
output wire [7:0] rx_data // data
);
rxuart _rx (
.clk(clk),
.resetq(resetq),
.uart_rx(rx),
.rd(rd),
.valid(valid),
.data(rx_data));
uart _tx (
.clk(clk),
.resetq(resetq),
.uart_busy(busy),
.uart_tx(tx),
.uart_wr_i(wr),
.uart_dat_i(tx_data));
endmodule
|
(* -*- coding: utf-8 -*- *)
(************************************************************************)
(* * The Coq Proof Assistant / The Coq Development Team *)
(* v * Copyright INRIA, CNRS and contributors *)
(* <O___,, * (see version control and CREDITS file for authors & dates) *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(* * (see LICENSE file for the text of the license) *)
(************************************************************************)
(** * Typeclass-based relations, tactics and standard instances
This is the basic theory needed to formalize morphisms and setoids.
Author: Matthieu Sozeau
Institution: LRI, CNRS UMR 8623 - University Paris Sud
*)
Require Export Coq.Classes.Init.
Require Import Coq.Program.Basics.
Require Import Coq.Program.Tactics.
Require Import Coq.Relations.Relation_Definitions.
Generalizable Variables A B C D R S T U l eqA eqB eqC eqD.
(** We allow to unfold the [relation] definition while doing morphism search. *)
Section Defs.
Context {A : Type}.
(** We rebind relational properties in separate classes to be able to overload each proof. *)
Class Reflexive (R : relation A) :=
reflexivity : forall x : A, R x x.
Definition complement (R : relation A) : relation A := fun x y => R x y -> False.
(** Opaque for proof-search. *)
Typeclasses Opaque complement.
(** These are convertible. *)
Lemma complement_inverse R : complement (flip R) = flip (complement R).
Proof. reflexivity. Qed.
Class Irreflexive (R : relation A) :=
irreflexivity : Reflexive (complement R).
Class Symmetric (R : relation A) :=
symmetry : forall {x y}, R x y -> R y x.
Class Asymmetric (R : relation A) :=
asymmetry : forall {x y}, R x y -> R y x -> False.
Class Transitive (R : relation A) :=
transitivity : forall {x y z}, R x y -> R y z -> R x z.
(** Various combinations of reflexivity, symmetry and transitivity. *)
(** A [PreOrder] is both Reflexive and Transitive. *)
Class PreOrder (R : relation A) : Prop := {
PreOrder_Reflexive :> Reflexive R | 2 ;
PreOrder_Transitive :> Transitive R | 2 }.
(** A [StrictOrder] is both Irreflexive and Transitive. *)
Class StrictOrder (R : relation A) : Prop := {
StrictOrder_Irreflexive :> Irreflexive R ;
StrictOrder_Transitive :> Transitive R }.
(** By definition, a strict order is also asymmetric *)
Global Instance StrictOrder_Asymmetric `(StrictOrder R) : Asymmetric R.
Proof. firstorder. Qed.
(** A partial equivalence relation is Symmetric and Transitive. *)
Class PER (R : relation A) : Prop := {
PER_Symmetric :> Symmetric R | 3 ;
PER_Transitive :> Transitive R | 3 }.
(** Equivalence relations. *)
Class Equivalence (R : relation A) : Prop := {
Equivalence_Reflexive :> Reflexive R ;
Equivalence_Symmetric :> Symmetric R ;
Equivalence_Transitive :> Transitive R }.
(** An Equivalence is a PER plus reflexivity. *)
Global Instance Equivalence_PER {R} `(E:Equivalence R) : PER R | 10 :=
{ }.
(** An Equivalence is a PreOrder plus symmetry. *)
Global Instance Equivalence_PreOrder {R} `(E:Equivalence R) : PreOrder R | 10 :=
{ }.
(** We can now define antisymmetry w.r.t. an equivalence relation on the carrier. *)
Class Antisymmetric eqA `{equ : Equivalence eqA} (R : relation A) :=
antisymmetry : forall {x y}, R x y -> R y x -> eqA x y.
Class subrelation (R R' : relation A) : Prop :=
is_subrelation : forall {x y}, R x y -> R' x y.
(** Any symmetric relation is equal to its inverse. *)
Lemma subrelation_symmetric R `(Symmetric R) : subrelation (flip R) R.
Proof. hnf. intros x y H0. red in H0. apply symmetry. assumption. Qed.
Section flip.
Lemma flip_Reflexive `{Reflexive R} : Reflexive (flip R).
Proof. tauto. Qed.
Program Definition flip_Irreflexive `(Irreflexive R) : Irreflexive (flip R) :=
irreflexivity (R:=R).
Program Definition flip_Symmetric `(Symmetric R) : Symmetric (flip R) :=
fun x y H => symmetry (R:=R) H.
Program Definition flip_Asymmetric `(Asymmetric R) : Asymmetric (flip R) :=
fun x y H H' => asymmetry (R:=R) H H'.
Program Definition flip_Transitive `(Transitive R) : Transitive (flip R) :=
fun x y z H H' => transitivity (R:=R) H' H.
Program Definition flip_Antisymmetric `(Antisymmetric eqA R) :
Antisymmetric eqA (flip R).
Proof. firstorder. Qed.
(** Inversing the larger structures *)
Lemma flip_PreOrder `(PreOrder R) : PreOrder (flip R).
Proof. firstorder. Qed.
Lemma flip_StrictOrder `(StrictOrder R) : StrictOrder (flip R).
Proof. firstorder. Qed.
Lemma flip_PER `(PER R) : PER (flip R).
Proof. firstorder. Qed.
Lemma flip_Equivalence `(Equivalence R) : Equivalence (flip R).
Proof. firstorder. Qed.
End flip.
Section complement.
Definition complement_Irreflexive `(Reflexive R)
: Irreflexive (complement R).
Proof. firstorder. Qed.
Definition complement_Symmetric `(Symmetric R) : Symmetric (complement R).
Proof. firstorder. Qed.
End complement.
(** Rewrite relation on a given support: declares a relation as a rewrite
relation for use by the generalized rewriting tactic.
It helps choosing if a rewrite should be handled
by the generalized or the regular rewriting tactic using leibniz equality.
Users can declare an [RewriteRelation A RA] anywhere to declare default
relations. This is also done automatically by the [Declare Relation A RA]
commands. *)
Class RewriteRelation (RA : relation A).
(** Any [Equivalence] declared in the context is automatically considered
a rewrite relation. *)
Global Instance equivalence_rewrite_relation `(Equivalence eqA) : RewriteRelation eqA.
Defined.
(** Leibniz equality. *)
Section Leibniz.
Global Instance eq_Reflexive : Reflexive (@eq A) := @eq_refl A.
Global Instance eq_Symmetric : Symmetric (@eq A) := @eq_sym A.
Global Instance eq_Transitive : Transitive (@eq A) := @eq_trans A.
(** Leibinz equality [eq] is an equivalence relation.
The instance has low priority as it is always applicable
if only the type is constrained. *)
Global Program Instance eq_equivalence : Equivalence (@eq A) | 10.
End Leibniz.
End Defs.
(** Default rewrite relations handled by [setoid_rewrite]. *)
Instance: RewriteRelation impl.
Defined.
Instance: RewriteRelation iff.
Defined.
(** Hints to drive the typeclass resolution avoiding loops
due to the use of full unification. *)
#[global]
Hint Extern 1 (Reflexive (complement _)) => class_apply @irreflexivity : typeclass_instances.
#[global]
Hint Extern 3 (Symmetric (complement _)) => class_apply complement_Symmetric : typeclass_instances.
#[global]
Hint Extern 3 (Irreflexive (complement _)) => class_apply complement_Irreflexive : typeclass_instances.
#[global]
Hint Extern 3 (Reflexive (flip _)) => apply flip_Reflexive : typeclass_instances.
#[global]
Hint Extern 3 (Irreflexive (flip _)) => class_apply flip_Irreflexive : typeclass_instances.
#[global]
Hint Extern 3 (Symmetric (flip _)) => class_apply flip_Symmetric : typeclass_instances.
#[global]
Hint Extern 3 (Asymmetric (flip _)) => class_apply flip_Asymmetric : typeclass_instances.
#[global]
Hint Extern 3 (Antisymmetric (flip _)) => class_apply flip_Antisymmetric : typeclass_instances.
#[global]
Hint Extern 3 (Transitive (flip _)) => class_apply flip_Transitive : typeclass_instances.
#[global]
Hint Extern 3 (StrictOrder (flip _)) => class_apply flip_StrictOrder : typeclass_instances.
#[global]
Hint Extern 3 (PreOrder (flip _)) => class_apply flip_PreOrder : typeclass_instances.
#[global]
Hint Extern 4 (subrelation (flip _) _) =>
class_apply @subrelation_symmetric : typeclass_instances.
Arguments irreflexivity {A R Irreflexive} [x] _ : rename.
Arguments symmetry {A} {R} {_} [x] [y] _.
Arguments asymmetry {A} {R} {_} [x] [y] _ _.
Arguments transitivity {A} {R} {_} [x] [y] [z] _ _.
Arguments Antisymmetric A eqA {_} _.
#[global]
Hint Resolve irreflexivity : ord.
Unset Implicit Arguments.
Ltac solve_relation :=
match goal with
| [ |- ?R ?x ?x ] => reflexivity
| [ H : ?R ?x ?y |- ?R ?y ?x ] => symmetry ; exact H
end.
#[global]
Hint Extern 4 => solve_relation : relations.
(** We can already dualize all these properties. *)
(** * Standard instances. *)
Ltac reduce_hyp H :=
match type of H with
| context [ _ <-> _ ] => fail 1
| _ => red in H ; try reduce_hyp H
end.
Ltac reduce_goal :=
match goal with
| [ |- _ <-> _ ] => fail 1
| _ => red ; intros ; try reduce_goal
end.
Tactic Notation "reduce" "in" hyp(Hid) := reduce_hyp Hid.
Ltac reduce := reduce_goal.
Tactic Notation "apply" "*" constr(t) :=
first [ refine t | refine (t _) | refine (t _ _) | refine (t _ _ _) | refine (t _ _ _ _) |
refine (t _ _ _ _ _) | refine (t _ _ _ _ _ _) | refine (t _ _ _ _ _ _ _) ].
Ltac simpl_relation :=
unfold flip, impl, arrow ; try reduce ; program_simpl ;
try ( solve [ dintuition ]).
Local Obligation Tactic := try solve [ simpl_relation ].
(** Logical implication. *)
Program Instance impl_Reflexive : Reflexive impl.
Program Instance impl_Transitive : Transitive impl.
(** Logical equivalence. *)
Instance iff_Reflexive : Reflexive iff := iff_refl.
Instance iff_Symmetric : Symmetric iff := iff_sym.
Instance iff_Transitive : Transitive iff := iff_trans.
(** Logical equivalence [iff] is an equivalence relation. *)
Program Instance iff_equivalence : Equivalence iff.
(** We now develop a generalization of results on relations for arbitrary predicates.
The resulting theory can be applied to homogeneous binary relations but also to
arbitrary n-ary predicates. *)
Local Open Scope list_scope.
(** A compact representation of non-dependent arities, with the codomain singled-out. *)
(* Note, we do not use [list Type] because it imposes unnecessary universe constraints *)
Inductive Tlist : Type := Tnil : Tlist | Tcons : Type -> Tlist -> Tlist.
Local Infix "::" := Tcons.
Fixpoint arrows (l : Tlist) (r : Type) : Type :=
match l with
| Tnil => r
| A :: l' => A -> arrows l' r
end.
(** We can define abbreviations for operation and relation types based on [arrows]. *)
Definition unary_operation A := arrows (A::Tnil) A.
Definition binary_operation A := arrows (A::A::Tnil) A.
Definition ternary_operation A := arrows (A::A::A::Tnil) A.
(** We define n-ary [predicate]s as functions into [Prop]. *)
Notation predicate l := (arrows l Prop).
(** Unary predicates, or sets. *)
Definition unary_predicate A := predicate (A::Tnil).
(** Homogeneous binary relations, equivalent to [relation A]. *)
Definition binary_relation A := predicate (A::A::Tnil).
(** We can close a predicate by universal or existential quantification. *)
Fixpoint predicate_all (l : Tlist) : predicate l -> Prop :=
match l with
| Tnil => fun f => f
| A :: tl => fun f => forall x : A, predicate_all tl (f x)
end.
Fixpoint predicate_exists (l : Tlist) : predicate l -> Prop :=
match l with
| Tnil => fun f => f
| A :: tl => fun f => exists x : A, predicate_exists tl (f x)
end.
(** Pointwise extension of a binary operation on [T] to a binary operation
on functions whose codomain is [T].
For an operator on [Prop] this lifts the operator to a binary operation. *)
Fixpoint pointwise_extension {T : Type} (op : binary_operation T)
(l : Tlist) : binary_operation (arrows l T) :=
match l with
| Tnil => fun R R' => op R R'
| A :: tl => fun R R' =>
fun x => pointwise_extension op tl (R x) (R' x)
end.
(** Pointwise lifting, equivalent to doing [pointwise_extension] and closing using [predicate_all]. *)
Fixpoint pointwise_lifting (op : binary_relation Prop) (l : Tlist) : binary_relation (predicate l) :=
match l with
| Tnil => fun R R' => op R R'
| A :: tl => fun R R' =>
forall x, pointwise_lifting op tl (R x) (R' x)
end.
(** The n-ary equivalence relation, defined by lifting the 0-ary [iff] relation. *)
Definition predicate_equivalence {l : Tlist} : binary_relation (predicate l) :=
pointwise_lifting iff l.
(** The n-ary implication relation, defined by lifting the 0-ary [impl] relation. *)
Definition predicate_implication {l : Tlist} :=
pointwise_lifting impl l.
(** Notations for pointwise equivalence and implication of predicates. *)
Declare Scope predicate_scope.
Infix "<∙>" := predicate_equivalence (at level 95, no associativity) : predicate_scope.
Infix "-∙>" := predicate_implication (at level 70, right associativity) : predicate_scope.
Local Open Scope predicate_scope.
(** The pointwise liftings of conjunction and disjunctions.
Note that these are [binary_operation]s, building new relations out of old ones. *)
Definition predicate_intersection := pointwise_extension and.
Definition predicate_union := pointwise_extension or.
Infix "/∙\" := predicate_intersection (at level 80, right associativity) : predicate_scope.
Infix "\∙/" := predicate_union (at level 85, right associativity) : predicate_scope.
(** The always [True] and always [False] predicates. *)
Fixpoint true_predicate {l : Tlist} : predicate l :=
match l with
| Tnil => True
| A :: tl => fun _ => @true_predicate tl
end.
Fixpoint false_predicate {l : Tlist} : predicate l :=
match l with
| Tnil => False
| A :: tl => fun _ => @false_predicate tl
end.
Notation "∙⊤∙" := true_predicate : predicate_scope.
Notation "∙⊥∙" := false_predicate : predicate_scope.
(** Predicate equivalence is an equivalence, and predicate implication defines a preorder. *)
Program Instance predicate_equivalence_equivalence {l} :
Equivalence (@predicate_equivalence l).
Next Obligation.
intro l; induction l ; firstorder.
Qed.
Next Obligation.
intro l; induction l ; firstorder.
Qed.
Next Obligation.
intro l.
fold pointwise_lifting.
induction l as [|T l IHl].
- firstorder.
- intros x y z H H0 x0. pose (IHl (x x0) (y x0) (z x0)).
firstorder.
Qed.
Program Instance predicate_implication_preorder {l} :
PreOrder (@predicate_implication l).
Next Obligation.
intro l; induction l ; firstorder.
Qed.
Next Obligation.
intro l.
induction l as [|T l IHl].
- firstorder.
- intros x y z H H0 x0. pose (IHl (x x0) (y x0) (z x0)). firstorder.
Qed.
(** We define the various operations which define the algebra on binary relations,
from the general ones. *)
Section Binary.
Context {A : Type}.
Definition relation_equivalence : relation (relation A) :=
@predicate_equivalence (_::_::Tnil).
Global Instance: RewriteRelation relation_equivalence.
Defined.
Definition relation_conjunction (R : relation A) (R' : relation A) : relation A :=
@predicate_intersection (A::A::Tnil) R R'.
Definition relation_disjunction (R : relation A) (R' : relation A) : relation A :=
@predicate_union (A::A::Tnil) R R'.
(** Relation equivalence is an equivalence, and subrelation defines a partial order. *)
Global Instance relation_equivalence_equivalence :
Equivalence relation_equivalence.
Proof. exact (@predicate_equivalence_equivalence (A::A::Tnil)). Qed.
Global Instance relation_implication_preorder : PreOrder (@subrelation A).
Proof. exact (@predicate_implication_preorder (A::A::Tnil)). Qed.
(** *** Partial Order.
A partial order is a preorder which is additionally antisymmetric.
We give an equivalent definition, up-to an equivalence relation
on the carrier. *)
Class PartialOrder eqA `{equ : Equivalence A eqA} R `{preo : PreOrder A R} :=
partial_order_equivalence : relation_equivalence eqA (relation_conjunction R (flip R)).
(** The equivalence proof is sufficient for proving that [R] must be a
morphism for equivalence (see Morphisms). It is also sufficient to
show that [R] is antisymmetric w.r.t. [eqA] *)
Global Instance partial_order_antisym `(PartialOrder eqA R) : Antisymmetric A eqA R.
Proof with auto.
reduce_goal.
pose proof partial_order_equivalence as poe. do 3 red in poe.
apply <- poe. firstorder.
Qed.
Lemma PartialOrder_inverse `(PartialOrder eqA R) : PartialOrder eqA (flip R).
Proof. firstorder. Qed.
End Binary.
#[global]
Hint Extern 3 (PartialOrder (flip _)) => class_apply PartialOrder_inverse : typeclass_instances.
(** The partial order defined by subrelation and relation equivalence. *)
Program Instance subrelation_partial_order {A} :
PartialOrder (@relation_equivalence A) subrelation.
Next Obligation.
Proof.
unfold relation_equivalence in *. compute; firstorder.
Qed.
Typeclasses Opaque arrows predicate_implication predicate_equivalence
relation_equivalence pointwise_lifting.
|
`include "constants.vh"
`include "alu_ops.vh"
`include "rv32_opcodes.vh"
`default_nettype none
module rs_alu_ent
(
//Memory
input wire clk,
input wire reset,
input wire busy,
input wire [`ADDR_LEN-1:0] wpc,
input wire [`DATA_LEN-1:0] wsrc1,
input wire [`DATA_LEN-1:0] wsrc2,
input wire wvalid1,
input wire wvalid2,
input wire [`DATA_LEN-1:0] wimm,
input wire [`RRF_SEL-1:0] wrrftag,
input wire wdstval,
input wire [`SRC_A_SEL_WIDTH-1:0] wsrc_a,
input wire [`SRC_B_SEL_WIDTH-1:0] wsrc_b,
input wire [`ALU_OP_WIDTH-1:0] walu_op,
input wire [`SPECTAG_LEN-1:0] wspectag,
input wire we,
output wire [`DATA_LEN-1:0] ex_src1,
output wire [`DATA_LEN-1:0] ex_src2,
output wire ready,
output reg [`ADDR_LEN-1:0] pc,
output reg [`DATA_LEN-1:0] imm,
output reg [`RRF_SEL-1:0] rrftag,
output reg dstval,
output reg [`SRC_A_SEL_WIDTH-1:0] src_a,
output reg [`SRC_B_SEL_WIDTH-1:0] src_b,
output reg [`ALU_OP_WIDTH-1:0] alu_op,
output reg [`SPECTAG_LEN-1:0] spectag,
//EXRSLT
input wire [`DATA_LEN-1:0] exrslt1,
input wire [`RRF_SEL-1:0] exdst1,
input wire kill_spec1,
input wire [`DATA_LEN-1:0] exrslt2,
input wire [`RRF_SEL-1:0] exdst2,
input wire kill_spec2,
input wire [`DATA_LEN-1:0] exrslt3,
input wire [`RRF_SEL-1:0] exdst3,
input wire kill_spec3,
input wire [`DATA_LEN-1:0] exrslt4,
input wire [`RRF_SEL-1:0] exdst4,
input wire kill_spec4,
input wire [`DATA_LEN-1:0] exrslt5,
input wire [`RRF_SEL-1:0] exdst5,
input wire kill_spec5
);
reg [`DATA_LEN-1:0] src1;
reg [`DATA_LEN-1:0] src2;
reg valid1;
reg valid2;
wire [`DATA_LEN-1:0] nextsrc1;
wire [`DATA_LEN-1:0] nextsrc2;
wire nextvalid1;
wire nextvalid2;
assign ready = busy & valid1 & valid2;
assign ex_src1 = ~valid1 & nextvalid1 ?
nextsrc1 : src1;
assign ex_src2 = ~valid2 & nextvalid2 ?
nextsrc2 : src2;
always @ (posedge clk) begin
if (reset) begin
pc <= 0;
imm <= 0;
rrftag <= 0;
dstval <= 0;
src_a <= 0;
src_b <= 0;
alu_op <= 0;
spectag <= 0;
src1 <= 0;
src2 <= 0;
valid1 <= 0;
valid2 <= 0;
end else if (we) begin
pc <= wpc;
imm <= wimm;
rrftag <= wrrftag;
dstval <= wdstval;
src_a <= wsrc_a;
src_b <= wsrc_b;
alu_op <= walu_op;
spectag <= wspectag;
src1 <= wsrc1;
src2 <= wsrc2;
valid1 <= wvalid1;
valid2 <= wvalid2;
end else begin // if (we)
src1 <= nextsrc1;
src2 <= nextsrc2;
valid1 <= nextvalid1;
valid2 <= nextvalid2;
end
end
src_manager srcmng1(
.opr(src1),
.opr_rdy(valid1),
.exrslt1(exrslt1),
.exdst1(exdst1),
.kill_spec1(kill_spec1),
.exrslt2(exrslt2),
.exdst2(exdst2),
.kill_spec2(kill_spec2),
.exrslt3(exrslt3),
.exdst3(exdst3),
.kill_spec3(kill_spec3),
.exrslt4(exrslt4),
.exdst4(exdst4),
.kill_spec4(kill_spec4),
.exrslt5(exrslt5),
.exdst5(exdst5),
.kill_spec5(kill_spec5),
.src(nextsrc1),
.resolved(nextvalid1)
);
src_manager srcmng2(
.opr(src2),
.opr_rdy(valid2),
.exrslt1(exrslt1),
.exdst1(exdst1),
.kill_spec1(kill_spec1),
.exrslt2(exrslt2),
.exdst2(exdst2),
.kill_spec2(kill_spec2),
.exrslt3(exrslt3),
.exdst3(exdst3),
.kill_spec3(kill_spec3),
.exrslt4(exrslt4),
.exdst4(exdst4),
.kill_spec4(kill_spec4),
.exrslt5(exrslt5),
.exdst5(exdst5),
.kill_spec5(kill_spec5),
.src(nextsrc2),
.resolved(nextvalid2)
);
endmodule // rs_alu
module rs_alu
(
//System
input wire clk,
input wire reset,
output reg [`ALU_ENT_NUM-1:0] busyvec,
input wire prmiss,
input wire prsuccess,
input wire [`SPECTAG_LEN-1:0] prtag,
input wire [`SPECTAG_LEN-1:0] specfixtag,
output wire [`ALU_ENT_NUM*(`RRF_SEL+2)-1:0] histvect,
input wire nextrrfcyc,
//WriteSignal
input wire clearbusy, //Issue
input wire [`ALU_ENT_SEL-1:0] issueaddr,
input wire we1, //alloc1
input wire we2, //alloc2
input wire [`ALU_ENT_SEL-1:0] waddr1, //allocent1
input wire [`ALU_ENT_SEL-1:0] waddr2, //allocent2
//WriteSignal1
input wire [`ADDR_LEN-1:0] wpc_1,
input wire [`DATA_LEN-1:0] wsrc1_1,
input wire [`DATA_LEN-1:0] wsrc2_1,
input wire wvalid1_1,
input wire wvalid2_1,
input wire [`DATA_LEN-1:0] wimm_1,
input wire [`RRF_SEL-1:0] wrrftag_1,
input wire wdstval_1,
input wire [`SRC_A_SEL_WIDTH-1:0] wsrc_a_1,
input wire [`SRC_B_SEL_WIDTH-1:0] wsrc_b_1,
input wire [`ALU_OP_WIDTH-1:0] walu_op_1,
input wire [`SPECTAG_LEN-1:0] wspectag_1,
input wire wspecbit_1,
//WriteSignal2
input wire [`ADDR_LEN-1:0] wpc_2,
input wire [`DATA_LEN-1:0] wsrc1_2,
input wire [`DATA_LEN-1:0] wsrc2_2,
input wire wvalid1_2,
input wire wvalid2_2,
input wire [`DATA_LEN-1:0] wimm_2,
input wire [`RRF_SEL-1:0] wrrftag_2,
input wire wdstval_2,
input wire [`SRC_A_SEL_WIDTH-1:0] wsrc_a_2,
input wire [`SRC_B_SEL_WIDTH-1:0] wsrc_b_2,
input wire [`ALU_OP_WIDTH-1:0] walu_op_2,
input wire [`SPECTAG_LEN-1:0] wspectag_2,
input wire wspecbit_2,
//ReadSignal
output wire [`DATA_LEN-1:0] ex_src1,
output wire [`DATA_LEN-1:0] ex_src2,
output wire [`ALU_ENT_NUM-1:0] ready,
output wire [`ADDR_LEN-1:0] pc,
output wire [`DATA_LEN-1:0] imm,
output wire [`RRF_SEL-1:0] rrftag,
output wire dstval,
output wire [`SRC_A_SEL_WIDTH-1:0] src_a,
output wire [`SRC_B_SEL_WIDTH-1:0] src_b,
output wire [`ALU_OP_WIDTH-1:0] alu_op,
output wire [`SPECTAG_LEN-1:0] spectag,
output wire specbit,
//EXRSLT
input wire [`DATA_LEN-1:0] exrslt1,
input wire [`RRF_SEL-1:0] exdst1,
input wire kill_spec1,
input wire [`DATA_LEN-1:0] exrslt2,
input wire [`RRF_SEL-1:0] exdst2,
input wire kill_spec2,
input wire [`DATA_LEN-1:0] exrslt3,
input wire [`RRF_SEL-1:0] exdst3,
input wire kill_spec3,
input wire [`DATA_LEN-1:0] exrslt4,
input wire [`RRF_SEL-1:0] exdst4,
input wire kill_spec4,
input wire [`DATA_LEN-1:0] exrslt5,
input wire [`RRF_SEL-1:0] exdst5,
input wire kill_spec5
);
//_0
wire [`DATA_LEN-1:0] ex_src1_0;
wire [`DATA_LEN-1:0] ex_src2_0;
wire ready_0;
wire [`ADDR_LEN-1:0] pc_0;
wire [`DATA_LEN-1:0] imm_0;
wire [`RRF_SEL-1:0] rrftag_0;
wire dstval_0;
wire [`SRC_A_SEL_WIDTH-1:0] src_a_0;
wire [`SRC_B_SEL_WIDTH-1:0] src_b_0;
wire [`ALU_OP_WIDTH-1:0] alu_op_0;
wire [`SPECTAG_LEN-1:0] spectag_0;
//_1
wire [`DATA_LEN-1:0] ex_src1_1;
wire [`DATA_LEN-1:0] ex_src2_1;
wire ready_1;
wire [`ADDR_LEN-1:0] pc_1;
wire [`DATA_LEN-1:0] imm_1;
wire [`RRF_SEL-1:0] rrftag_1;
wire dstval_1;
wire [`SRC_A_SEL_WIDTH-1:0] src_a_1;
wire [`SRC_B_SEL_WIDTH-1:0] src_b_1;
wire [`ALU_OP_WIDTH-1:0] alu_op_1;
wire [`SPECTAG_LEN-1:0] spectag_1;
//_2
wire [`DATA_LEN-1:0] ex_src1_2;
wire [`DATA_LEN-1:0] ex_src2_2;
wire ready_2;
wire [`ADDR_LEN-1:0] pc_2;
wire [`DATA_LEN-1:0] imm_2;
wire [`RRF_SEL-1:0] rrftag_2;
wire dstval_2;
wire [`SRC_A_SEL_WIDTH-1:0] src_a_2;
wire [`SRC_B_SEL_WIDTH-1:0] src_b_2;
wire [`ALU_OP_WIDTH-1:0] alu_op_2;
wire [`SPECTAG_LEN-1:0] spectag_2;
//_3
wire [`DATA_LEN-1:0] ex_src1_3;
wire [`DATA_LEN-1:0] ex_src2_3;
wire ready_3;
wire [`ADDR_LEN-1:0] pc_3;
wire [`DATA_LEN-1:0] imm_3;
wire [`RRF_SEL-1:0] rrftag_3;
wire dstval_3;
wire [`SRC_A_SEL_WIDTH-1:0] src_a_3;
wire [`SRC_B_SEL_WIDTH-1:0] src_b_3;
wire [`ALU_OP_WIDTH-1:0] alu_op_3;
wire [`SPECTAG_LEN-1:0] spectag_3;
//_4
wire [`DATA_LEN-1:0] ex_src1_4;
wire [`DATA_LEN-1:0] ex_src2_4;
wire ready_4;
wire [`ADDR_LEN-1:0] pc_4;
wire [`DATA_LEN-1:0] imm_4;
wire [`RRF_SEL-1:0] rrftag_4;
wire dstval_4;
wire [`SRC_A_SEL_WIDTH-1:0] src_a_4;
wire [`SRC_B_SEL_WIDTH-1:0] src_b_4;
wire [`ALU_OP_WIDTH-1:0] alu_op_4;
wire [`SPECTAG_LEN-1:0] spectag_4;
//_5
wire [`DATA_LEN-1:0] ex_src1_5;
wire [`DATA_LEN-1:0] ex_src2_5;
wire ready_5;
wire [`ADDR_LEN-1:0] pc_5;
wire [`DATA_LEN-1:0] imm_5;
wire [`RRF_SEL-1:0] rrftag_5;
wire dstval_5;
wire [`SRC_A_SEL_WIDTH-1:0] src_a_5;
wire [`SRC_B_SEL_WIDTH-1:0] src_b_5;
wire [`ALU_OP_WIDTH-1:0] alu_op_5;
wire [`SPECTAG_LEN-1:0] spectag_5;
//_6
wire [`DATA_LEN-1:0] ex_src1_6;
wire [`DATA_LEN-1:0] ex_src2_6;
wire ready_6;
wire [`ADDR_LEN-1:0] pc_6;
wire [`DATA_LEN-1:0] imm_6;
wire [`RRF_SEL-1:0] rrftag_6;
wire dstval_6;
wire [`SRC_A_SEL_WIDTH-1:0] src_a_6;
wire [`SRC_B_SEL_WIDTH-1:0] src_b_6;
wire [`ALU_OP_WIDTH-1:0] alu_op_6;
wire [`SPECTAG_LEN-1:0] spectag_6;
//_7
wire [`DATA_LEN-1:0] ex_src1_7;
wire [`DATA_LEN-1:0] ex_src2_7;
wire ready_7;
wire [`ADDR_LEN-1:0] pc_7;
wire [`DATA_LEN-1:0] imm_7;
wire [`RRF_SEL-1:0] rrftag_7;
wire dstval_7;
wire [`SRC_A_SEL_WIDTH-1:0] src_a_7;
wire [`SRC_B_SEL_WIDTH-1:0] src_b_7;
wire [`ALU_OP_WIDTH-1:0] alu_op_7;
wire [`SPECTAG_LEN-1:0] spectag_7;
reg [`ALU_ENT_NUM-1:0] specbitvec;
reg [`ALU_ENT_NUM-1:0] sortbit;
wire [`ALU_ENT_NUM-1:0] inv_vector =
{(spectag_7 & specfixtag) == 0 ? 1'b1 : 1'b0,
(spectag_6 & specfixtag) == 0 ? 1'b1 : 1'b0,
(spectag_5 & specfixtag) == 0 ? 1'b1 : 1'b0,
(spectag_4 & specfixtag) == 0 ? 1'b1 : 1'b0,
(spectag_3 & specfixtag) == 0 ? 1'b1 : 1'b0,
(spectag_2 & specfixtag) == 0 ? 1'b1 : 1'b0,
(spectag_1 & specfixtag) == 0 ? 1'b1 : 1'b0,
(spectag_0 & specfixtag) == 0 ? 1'b1 : 1'b0};
wire [`ALU_ENT_NUM-1:0] inv_vector_spec =
{(spectag_7 == prtag) ? 1'b0 : 1'b1,
(spectag_6 == prtag) ? 1'b0 : 1'b1,
(spectag_5 == prtag) ? 1'b0 : 1'b1,
(spectag_4 == prtag) ? 1'b0 : 1'b1,
(spectag_3 == prtag) ? 1'b0 : 1'b1,
(spectag_2 == prtag) ? 1'b0 : 1'b1,
(spectag_1 == prtag) ? 1'b0 : 1'b1,
(spectag_0 == prtag) ? 1'b0 : 1'b1};
wire [`ALU_ENT_NUM-1:0] specbitvec_next =
(inv_vector_spec & specbitvec);
/* |
(we1 & wspecbit_1 ? (`ALU_ENT_SEL'b1 << waddr1) : 0) |
(we2 & wspecbit_2 ? (`ALU_ENT_SEL'b1 << waddr2) : 0);
*/
assign specbit = prsuccess ?
specbitvec_next[issueaddr] : specbitvec[issueaddr];
/*
assign specbit = prsuccess ?
((inv_vector & busyvec) |
(we1 & wspecbit_1 ? (`ALU_ENT_SEL'b1 << waddr1) : 0) |
(we2 & wspecbit_2 ? (`ALU_ENT_SEL'b1 << waddr2) : 0)) :
specbitvec[issueaddr];
*/
assign ready = {ready_7, ready_6, ready_5, ready_4,
ready_3, ready_2, ready_1, ready_0};
assign histvect = {
{~ready_7, sortbit[7], rrftag_7},
{~ready_6, sortbit[6], rrftag_6},
{~ready_5, sortbit[5], rrftag_5},
{~ready_4, sortbit[4], rrftag_4},
{~ready_3, sortbit[3], rrftag_3},
{~ready_2, sortbit[2], rrftag_2},
{~ready_1, sortbit[1], rrftag_1},
{~ready_0, sortbit[0], rrftag_0}
};
always @ (posedge clk) begin
if (reset) begin
sortbit <= `ALU_ENT_NUM'b1;
end else if (nextrrfcyc) begin
sortbit <= (we1 ? (`ALU_ENT_NUM'b1 << waddr1) : `ALU_ENT_NUM'b0) |
(we2 ? (`ALU_ENT_NUM'b1 << waddr2) : `ALU_ENT_NUM'b0);
end else begin
if (we1) begin
sortbit[waddr1] <= 1'b1;
end
if (we2) begin
sortbit[waddr2] <= 1'b1;
end
end
end
always @ (posedge clk) begin
if (reset) begin
busyvec <= 0;
specbitvec <= 0;
end else begin
if (prmiss) begin
busyvec <= inv_vector & busyvec;
specbitvec <= 0;
end else if (prsuccess) begin
/*
specbitvec <= (inv_vector & busyvec) |
(we1 & wspecbit_1 ? (`ALU_ENT_SEL'b1 << waddr1) : 0) |
(we2 & wspecbit_2 ? (`ALU_ENT_SEL'b1 << waddr2) : 0);
*/
specbitvec <= specbitvec_next;
/*
if (we1) begin
busyvec[waddr1] <= 1'b1;
end
if (we2) begin
busyvec[waddr2] <= 1'b1;
end
*/
if (clearbusy) begin
busyvec[issueaddr] <= 1'b0;
end
end else begin
if (we1) begin
busyvec[waddr1] <= 1'b1;
specbitvec[waddr1] <= wspecbit_1;
end
if (we2) begin
busyvec[waddr2] <= 1'b1;
specbitvec[waddr2] <= wspecbit_2;
end
if (clearbusy) begin
busyvec[issueaddr] <= 1'b0;
end
end
end
end
rs_alu_ent ent0(
.clk(clk),
.reset(reset),
.busy(busyvec[0]),
.wpc((we1 && (waddr1 == 0)) ? wpc_1 : wpc_2),
.wsrc1((we1 && (waddr1 == 0)) ? wsrc1_1 : wsrc1_2),
.wsrc2((we1 && (waddr1 == 0)) ? wsrc2_1 : wsrc2_2),
.wvalid1((we1 && (waddr1 == 0)) ? wvalid1_1 : wvalid1_2),
.wvalid2((we1 && (waddr1 == 0)) ? wvalid2_1 : wvalid2_2),
.wimm((we1 && (waddr1 == 0)) ? wimm_1 : wimm_2),
.wrrftag((we1 && (waddr1 == 0)) ? wrrftag_1 : wrrftag_2),
.wdstval((we1 && (waddr1 == 0)) ? wdstval_1 : wdstval_2),
.wsrc_a((we1 && (waddr1 == 0)) ? wsrc_a_1 : wsrc_a_2),
.wsrc_b((we1 && (waddr1 == 0)) ? wsrc_b_1 : wsrc_b_2),
.walu_op((we1 && (waddr1 == 0)) ? walu_op_1 : walu_op_2),
.wspectag((we1 && (waddr1 == 0)) ? wspectag_1 : wspectag_2),
.we((we1 && (waddr1 == 0)) || (we2 && (waddr2 == 0))),
.ex_src1(ex_src1_0),
.ex_src2(ex_src2_0),
.ready(ready_0),
.pc(pc_0),
.imm(imm_0),
.rrftag(rrftag_0),
.dstval(dstval_0),
.src_a(src_a_0),
.src_b(src_b_0),
.alu_op(alu_op_0),
.spectag(spectag_0),
.exrslt1(exrslt1),
.exdst1(exdst1),
.kill_spec1(kill_spec1),
.exrslt2(exrslt2),
.exdst2(exdst2),
.kill_spec2(kill_spec2),
.exrslt3(exrslt3),
.exdst3(exdst3),
.kill_spec3(kill_spec3),
.exrslt4(exrslt4),
.exdst4(exdst4),
.kill_spec4(kill_spec4),
.exrslt5(exrslt5),
.exdst5(exdst5),
.kill_spec5(kill_spec5)
);
rs_alu_ent ent1(
.clk(clk),
.reset(reset),
.busy(busyvec[1]),
.wpc((we1 && (waddr1 == 1)) ? wpc_1 : wpc_2),
.wsrc1((we1 && (waddr1 == 1)) ? wsrc1_1 : wsrc1_2),
.wsrc2((we1 && (waddr1 == 1)) ? wsrc2_1 : wsrc2_2),
.wvalid1((we1 && (waddr1 == 1)) ? wvalid1_1 : wvalid1_2),
.wvalid2((we1 && (waddr1 == 1)) ? wvalid2_1 : wvalid2_2),
.wimm((we1 && (waddr1 == 1)) ? wimm_1 : wimm_2),
.wrrftag((we1 && (waddr1 == 1)) ? wrrftag_1 : wrrftag_2),
.wdstval((we1 && (waddr1 == 1)) ? wdstval_1 : wdstval_2),
.wsrc_a((we1 && (waddr1 == 1)) ? wsrc_a_1 : wsrc_a_2),
.wsrc_b((we1 && (waddr1 == 1)) ? wsrc_b_1 : wsrc_b_2),
.walu_op((we1 && (waddr1 == 1)) ? walu_op_1 : walu_op_2),
.wspectag((we1 && (waddr1 == 1)) ? wspectag_1 : wspectag_2),
.we((we1 && (waddr1 == 1)) || (we2 && (waddr2 == 1))),
.ex_src1(ex_src1_1),
.ex_src2(ex_src2_1),
.ready(ready_1),
.pc(pc_1),
.imm(imm_1),
.rrftag(rrftag_1),
.dstval(dstval_1),
.src_a(src_a_1),
.src_b(src_b_1),
.alu_op(alu_op_1),
.spectag(spectag_1),
.exrslt1(exrslt1),
.exdst1(exdst1),
.kill_spec1(kill_spec1),
.exrslt2(exrslt2),
.exdst2(exdst2),
.kill_spec2(kill_spec2),
.exrslt3(exrslt3),
.exdst3(exdst3),
.kill_spec3(kill_spec3),
.exrslt4(exrslt4),
.exdst4(exdst4),
.kill_spec4(kill_spec4),
.exrslt5(exrslt5),
.exdst5(exdst5),
.kill_spec5(kill_spec5)
);
rs_alu_ent ent2(
.clk(clk),
.reset(reset),
.busy(busyvec[2]),
.wpc((we1 && (waddr1 == 2)) ? wpc_1 : wpc_2),
.wsrc1((we1 && (waddr1 == 2)) ? wsrc1_1 : wsrc1_2),
.wsrc2((we1 && (waddr1 == 2)) ? wsrc2_1 : wsrc2_2),
.wvalid1((we1 && (waddr1 == 2)) ? wvalid1_1 : wvalid1_2),
.wvalid2((we1 && (waddr1 == 2)) ? wvalid2_1 : wvalid2_2),
.wimm((we1 && (waddr1 == 2)) ? wimm_1 : wimm_2),
.wrrftag((we1 && (waddr1 == 2)) ? wrrftag_1 : wrrftag_2),
.wdstval((we1 && (waddr1 == 2)) ? wdstval_1 : wdstval_2),
.wsrc_a((we1 && (waddr1 == 2)) ? wsrc_a_1 : wsrc_a_2),
.wsrc_b((we1 && (waddr1 == 2)) ? wsrc_b_1 : wsrc_b_2),
.walu_op((we1 && (waddr1 == 2)) ? walu_op_1 : walu_op_2),
.wspectag((we1 && (waddr1 == 2)) ? wspectag_1 : wspectag_2),
.we((we1 && (waddr1 == 2)) || (we2 && (waddr2 == 2))),
.ex_src1(ex_src1_2),
.ex_src2(ex_src2_2),
.ready(ready_2),
.pc(pc_2),
.imm(imm_2),
.rrftag(rrftag_2),
.dstval(dstval_2),
.src_a(src_a_2),
.src_b(src_b_2),
.alu_op(alu_op_2),
.spectag(spectag_2),
.exrslt1(exrslt1),
.exdst1(exdst1),
.kill_spec1(kill_spec1),
.exrslt2(exrslt2),
.exdst2(exdst2),
.kill_spec2(kill_spec2),
.exrslt3(exrslt3),
.exdst3(exdst3),
.kill_spec3(kill_spec3),
.exrslt4(exrslt4),
.exdst4(exdst4),
.kill_spec4(kill_spec4),
.exrslt5(exrslt5),
.exdst5(exdst5),
.kill_spec5(kill_spec5)
);
rs_alu_ent ent3(
.clk(clk),
.reset(reset),
.busy(busyvec[3]),
.wpc((we1 && (waddr1 == 3)) ? wpc_1 : wpc_2),
.wsrc1((we1 && (waddr1 == 3)) ? wsrc1_1 : wsrc1_2),
.wsrc2((we1 && (waddr1 == 3)) ? wsrc2_1 : wsrc2_2),
.wvalid1((we1 && (waddr1 == 3)) ? wvalid1_1 : wvalid1_2),
.wvalid2((we1 && (waddr1 == 3)) ? wvalid2_1 : wvalid2_2),
.wimm((we1 && (waddr1 == 3)) ? wimm_1 : wimm_2),
.wrrftag((we1 && (waddr1 == 3)) ? wrrftag_1 : wrrftag_2),
.wdstval((we1 && (waddr1 == 3)) ? wdstval_1 : wdstval_2),
.wsrc_a((we1 && (waddr1 == 3)) ? wsrc_a_1 : wsrc_a_2),
.wsrc_b((we1 && (waddr1 == 3)) ? wsrc_b_1 : wsrc_b_2),
.walu_op((we1 && (waddr1 == 3)) ? walu_op_1 : walu_op_2),
.wspectag((we1 && (waddr1 == 3)) ? wspectag_1 : wspectag_2),
.we((we1 && (waddr1 == 3)) || (we2 && (waddr2 == 3))),
.ex_src1(ex_src1_3),
.ex_src2(ex_src2_3),
.ready(ready_3),
.pc(pc_3),
.imm(imm_3),
.rrftag(rrftag_3),
.dstval(dstval_3),
.src_a(src_a_3),
.src_b(src_b_3),
.alu_op(alu_op_3),
.spectag(spectag_3),
.exrslt1(exrslt1),
.exdst1(exdst1),
.kill_spec1(kill_spec1),
.exrslt2(exrslt2),
.exdst2(exdst2),
.kill_spec2(kill_spec2),
.exrslt3(exrslt3),
.exdst3(exdst3),
.kill_spec3(kill_spec3),
.exrslt4(exrslt4),
.exdst4(exdst4),
.kill_spec4(kill_spec4),
.exrslt5(exrslt5),
.exdst5(exdst5),
.kill_spec5(kill_spec5)
);
rs_alu_ent ent4(
.clk(clk),
.reset(reset),
.busy(busyvec[4]),
.wpc((we1 && (waddr1 == 4)) ? wpc_1 : wpc_2),
.wsrc1((we1 && (waddr1 == 4)) ? wsrc1_1 : wsrc1_2),
.wsrc2((we1 && (waddr1 == 4)) ? wsrc2_1 : wsrc2_2),
.wvalid1((we1 && (waddr1 == 4)) ? wvalid1_1 : wvalid1_2),
.wvalid2((we1 && (waddr1 == 4)) ? wvalid2_1 : wvalid2_2),
.wimm((we1 && (waddr1 == 4)) ? wimm_1 : wimm_2),
.wrrftag((we1 && (waddr1 == 4)) ? wrrftag_1 : wrrftag_2),
.wdstval((we1 && (waddr1 == 4)) ? wdstval_1 : wdstval_2),
.wsrc_a((we1 && (waddr1 == 4)) ? wsrc_a_1 : wsrc_a_2),
.wsrc_b((we1 && (waddr1 == 4)) ? wsrc_b_1 : wsrc_b_2),
.walu_op((we1 && (waddr1 == 4)) ? walu_op_1 : walu_op_2),
.wspectag((we1 && (waddr1 == 4)) ? wspectag_1 : wspectag_2),
.we((we1 && (waddr1 == 4)) || (we2 && (waddr2 == 4))),
.ex_src1(ex_src1_4),
.ex_src2(ex_src2_4),
.ready(ready_4),
.pc(pc_4),
.imm(imm_4),
.rrftag(rrftag_4),
.dstval(dstval_4),
.src_a(src_a_4),
.src_b(src_b_4),
.alu_op(alu_op_4),
.spectag(spectag_4),
.exrslt1(exrslt1),
.exdst1(exdst1),
.kill_spec1(kill_spec1),
.exrslt2(exrslt2),
.exdst2(exdst2),
.kill_spec2(kill_spec2),
.exrslt3(exrslt3),
.exdst3(exdst3),
.kill_spec3(kill_spec3),
.exrslt4(exrslt4),
.exdst4(exdst4),
.kill_spec4(kill_spec4),
.exrslt5(exrslt5),
.exdst5(exdst5),
.kill_spec5(kill_spec5)
);
rs_alu_ent ent5(
.clk(clk),
.reset(reset),
.busy(busyvec[5]),
.wpc((we1 && (waddr1 == 5)) ? wpc_1 : wpc_2),
.wsrc1((we1 && (waddr1 == 5)) ? wsrc1_1 : wsrc1_2),
.wsrc2((we1 && (waddr1 == 5)) ? wsrc2_1 : wsrc2_2),
.wvalid1((we1 && (waddr1 == 5)) ? wvalid1_1 : wvalid1_2),
.wvalid2((we1 && (waddr1 == 5)) ? wvalid2_1 : wvalid2_2),
.wimm((we1 && (waddr1 == 5)) ? wimm_1 : wimm_2),
.wrrftag((we1 && (waddr1 == 5)) ? wrrftag_1 : wrrftag_2),
.wdstval((we1 && (waddr1 == 5)) ? wdstval_1 : wdstval_2),
.wsrc_a((we1 && (waddr1 == 5)) ? wsrc_a_1 : wsrc_a_2),
.wsrc_b((we1 && (waddr1 == 5)) ? wsrc_b_1 : wsrc_b_2),
.walu_op((we1 && (waddr1 == 5)) ? walu_op_1 : walu_op_2),
.wspectag((we1 && (waddr1 == 5)) ? wspectag_1 : wspectag_2),
.we((we1 && (waddr1 == 5)) || (we2 && (waddr2 == 5))),
.ex_src1(ex_src1_5),
.ex_src2(ex_src2_5),
.ready(ready_5),
.pc(pc_5),
.imm(imm_5),
.rrftag(rrftag_5),
.dstval(dstval_5),
.src_a(src_a_5),
.src_b(src_b_5),
.alu_op(alu_op_5),
.spectag(spectag_5),
.exrslt1(exrslt1),
.exdst1(exdst1),
.kill_spec1(kill_spec1),
.exrslt2(exrslt2),
.exdst2(exdst2),
.kill_spec2(kill_spec2),
.exrslt3(exrslt3),
.exdst3(exdst3),
.kill_spec3(kill_spec3),
.exrslt4(exrslt4),
.exdst4(exdst4),
.kill_spec4(kill_spec4),
.exrslt5(exrslt5),
.exdst5(exdst5),
.kill_spec5(kill_spec5)
);
rs_alu_ent ent6(
.clk(clk),
.reset(reset),
.busy(busyvec[6]),
.wpc((we1 && (waddr1 == 6)) ? wpc_1 : wpc_2),
.wsrc1((we1 && (waddr1 == 6)) ? wsrc1_1 : wsrc1_2),
.wsrc2((we1 && (waddr1 == 6)) ? wsrc2_1 : wsrc2_2),
.wvalid1((we1 && (waddr1 == 6)) ? wvalid1_1 : wvalid1_2),
.wvalid2((we1 && (waddr1 == 6)) ? wvalid2_1 : wvalid2_2),
.wimm((we1 && (waddr1 == 6)) ? wimm_1 : wimm_2),
.wrrftag((we1 && (waddr1 == 6)) ? wrrftag_1 : wrrftag_2),
.wdstval((we1 && (waddr1 == 6)) ? wdstval_1 : wdstval_2),
.wsrc_a((we1 && (waddr1 == 6)) ? wsrc_a_1 : wsrc_a_2),
.wsrc_b((we1 && (waddr1 == 6)) ? wsrc_b_1 : wsrc_b_2),
.walu_op((we1 && (waddr1 == 6)) ? walu_op_1 : walu_op_2),
.wspectag((we1 && (waddr1 == 6)) ? wspectag_1 : wspectag_2),
.we((we1 && (waddr1 == 6)) || (we2 && (waddr2 == 6))),
.ex_src1(ex_src1_6),
.ex_src2(ex_src2_6),
.ready(ready_6),
.pc(pc_6),
.imm(imm_6),
.rrftag(rrftag_6),
.dstval(dstval_6),
.src_a(src_a_6),
.src_b(src_b_6),
.alu_op(alu_op_6),
.spectag(spectag_6),
.exrslt1(exrslt1),
.exdst1(exdst1),
.kill_spec1(kill_spec1),
.exrslt2(exrslt2),
.exdst2(exdst2),
.kill_spec2(kill_spec2),
.exrslt3(exrslt3),
.exdst3(exdst3),
.kill_spec3(kill_spec3),
.exrslt4(exrslt4),
.exdst4(exdst4),
.kill_spec4(kill_spec4),
.exrslt5(exrslt5),
.exdst5(exdst5),
.kill_spec5(kill_spec5)
);
rs_alu_ent ent7(
.clk(clk),
.reset(reset),
.busy(busyvec[7]),
.wpc((we1 && (waddr1 == 7)) ? wpc_1 : wpc_2),
.wsrc1((we1 && (waddr1 == 7)) ? wsrc1_1 : wsrc1_2),
.wsrc2((we1 && (waddr1 == 7)) ? wsrc2_1 : wsrc2_2),
.wvalid1((we1 && (waddr1 == 7)) ? wvalid1_1 : wvalid1_2),
.wvalid2((we1 && (waddr1 == 7)) ? wvalid2_1 : wvalid2_2),
.wimm((we1 && (waddr1 == 7)) ? wimm_1 : wimm_2),
.wrrftag((we1 && (waddr1 == 7)) ? wrrftag_1 : wrrftag_2),
.wdstval((we1 && (waddr1 == 7)) ? wdstval_1 : wdstval_2),
.wsrc_a((we1 && (waddr1 == 7)) ? wsrc_a_1 : wsrc_a_2),
.wsrc_b((we1 && (waddr1 == 7)) ? wsrc_b_1 : wsrc_b_2),
.walu_op((we1 && (waddr1 == 7)) ? walu_op_1 : walu_op_2),
.wspectag((we1 && (waddr1 == 7)) ? wspectag_1 : wspectag_2),
.we((we1 && (waddr1 == 7)) || (we2 && (waddr2 == 7))),
.ex_src1(ex_src1_7),
.ex_src2(ex_src2_7),
.ready(ready_7),
.pc(pc_7),
.imm(imm_7),
.rrftag(rrftag_7),
.dstval(dstval_7),
.src_a(src_a_7),
.src_b(src_b_7),
.alu_op(alu_op_7),
.spectag(spectag_7),
.exrslt1(exrslt1),
.exdst1(exdst1),
.kill_spec1(kill_spec1),
.exrslt2(exrslt2),
.exdst2(exdst2),
.kill_spec2(kill_spec2),
.exrslt3(exrslt3),
.exdst3(exdst3),
.kill_spec3(kill_spec3),
.exrslt4(exrslt4),
.exdst4(exdst4),
.kill_spec4(kill_spec4),
.exrslt5(exrslt5),
.exdst5(exdst5),
.kill_spec5(kill_spec5)
);
assign ex_src1 = (issueaddr == 0) ? ex_src1_0 :
(issueaddr == 1) ? ex_src1_1 :
(issueaddr == 2) ? ex_src1_2 :
(issueaddr == 3) ? ex_src1_3 :
(issueaddr == 4) ? ex_src1_4 :
(issueaddr == 5) ? ex_src1_5 :
(issueaddr == 6) ? ex_src1_6 : ex_src1_7;
assign ex_src2 = (issueaddr == 0) ? ex_src2_0 :
(issueaddr == 1) ? ex_src2_1 :
(issueaddr == 2) ? ex_src2_2 :
(issueaddr == 3) ? ex_src2_3 :
(issueaddr == 4) ? ex_src2_4 :
(issueaddr == 5) ? ex_src2_5 :
(issueaddr == 6) ? ex_src2_6 : ex_src2_7;
assign pc = (issueaddr == 0) ? pc_0 :
(issueaddr == 1) ? pc_1 :
(issueaddr == 2) ? pc_2 :
(issueaddr == 3) ? pc_3 :
(issueaddr == 4) ? pc_4 :
(issueaddr == 5) ? pc_5 :
(issueaddr == 6) ? pc_6 : pc_7;
assign imm = (issueaddr == 0) ? imm_0 :
(issueaddr == 1) ? imm_1 :
(issueaddr == 2) ? imm_2 :
(issueaddr == 3) ? imm_3 :
(issueaddr == 4) ? imm_4 :
(issueaddr == 5) ? imm_5 :
(issueaddr == 6) ? imm_6 : imm_7;
assign rrftag = (issueaddr == 0) ? rrftag_0 :
(issueaddr == 1) ? rrftag_1 :
(issueaddr == 2) ? rrftag_2 :
(issueaddr == 3) ? rrftag_3 :
(issueaddr == 4) ? rrftag_4 :
(issueaddr == 5) ? rrftag_5 :
(issueaddr == 6) ? rrftag_6 : rrftag_7;
assign dstval = (issueaddr == 0) ? dstval_0 :
(issueaddr == 1) ? dstval_1 :
(issueaddr == 2) ? dstval_2 :
(issueaddr == 3) ? dstval_3 :
(issueaddr == 4) ? dstval_4 :
(issueaddr == 5) ? dstval_5 :
(issueaddr == 6) ? dstval_6 : dstval_7;
assign src_a = (issueaddr == 0) ? src_a_0 :
(issueaddr == 1) ? src_a_1 :
(issueaddr == 2) ? src_a_2 :
(issueaddr == 3) ? src_a_3 :
(issueaddr == 4) ? src_a_4 :
(issueaddr == 5) ? src_a_5 :
(issueaddr == 6) ? src_a_6 : src_a_7;
assign src_b = (issueaddr == 0) ? src_b_0 :
(issueaddr == 1) ? src_b_1 :
(issueaddr == 2) ? src_b_2 :
(issueaddr == 3) ? src_b_3 :
(issueaddr == 4) ? src_b_4 :
(issueaddr == 5) ? src_b_5 :
(issueaddr == 6) ? src_b_6 : src_b_7;
assign alu_op = (issueaddr == 0) ? alu_op_0 :
(issueaddr == 1) ? alu_op_1 :
(issueaddr == 2) ? alu_op_2 :
(issueaddr == 3) ? alu_op_3 :
(issueaddr == 4) ? alu_op_4 :
(issueaddr == 5) ? alu_op_5 :
(issueaddr == 6) ? alu_op_6 : alu_op_7;
assign spectag = (issueaddr == 0) ? spectag_0 :
(issueaddr == 1) ? spectag_1 :
(issueaddr == 2) ? spectag_2 :
(issueaddr == 3) ? spectag_3 :
(issueaddr == 4) ? spectag_4 :
(issueaddr == 5) ? spectag_5 :
(issueaddr == 6) ? spectag_6 : spectag_7;
endmodule // rs_alu
`default_nettype wire
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t(/*AUTOARG*/
// Inputs
clk
);
input clk;
reg _ranit;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [4:0] par1; // From a1 of t_param_first_a.v
wire [4:0] par2; // From a2 of t_param_first_a.v
wire [4:0] par3; // From a3 of t_param_first_a.v
wire [4:0] par4; // From a4 of t_param_first_a.v
wire [1:0] varwidth1; // From a1 of t_param_first_a.v
wire [2:0] varwidth2; // From a2 of t_param_first_a.v
wire [3:0] varwidth3; // From a3 of t_param_first_a.v
wire [3:0] varwidth4; // From a4 of t_param_first_a.v
// End of automatics
/*t_param_first_a AUTO_TEMPLATE (
.par (par@[]));
.varwidth (varwidth@[]));
*/
parameter XX = 2'bXX;
parameter THREE = 3;
t_param_first_a #(1,5) a1
(
// Outputs
.varwidth (varwidth1[1:0]),
/*AUTOINST*/
// Outputs
.par (par1[4:0])); // Templated
t_param_first_a #(2,5) a2
(
// Outputs
.varwidth (varwidth2[2:0]),
/*AUTOINST*/
// Outputs
.par (par2[4:0])); // Templated
t_param_first_a #(THREE,5) a3
(
// Outputs
.varwidth (varwidth3[3:0]),
/*AUTOINST*/
// Outputs
.par (par3[4:0])); // Templated
t_param_first_a #(THREE,5) a4
(
// Outputs
.varwidth (varwidth4[3:0]),
/*AUTOINST*/
// Outputs
.par (par4[4:0])); // Templated
parameter THREE_BITS_WIDE = 3'b011;
parameter THREE_2WIDE = 2'b11;
parameter ALSO_THREE_WIDE = THREE_BITS_WIDE;
parameter THREEPP_32_WIDE = 2*8*2+3;
parameter THREEPP_3_WIDE = 3'd4*3'd4*3'd2+3'd3; // Yes folks VCS says 3 bits wide
// Width propagation doesn't care about LHS vs RHS
// But the width of a RHS/LHS on a upper node does affect lower nodes;
// Thus must double-descend in width analysis.
// VCS 7.0.1 is broken on this test!
parameter T10 = (3'h7+3'h7)+4'h0; //initial if (T10!==4'd14) $stop;
parameter T11 = 4'h0+(3'h7+3'h7); //initial if (T11!==4'd14) $stop;
// Parameters assign LHS is affectively width zero.
parameter T12 = THREE_2WIDE + THREE_2WIDE; initial if (T12!==2'd2) $stop;
parameter T13 = THREE_2WIDE + 3; initial if (T13!==32'd6) $stop;
// Must be careful about LSB's with extracts
parameter [39:8] T14 = 32'h00_1234_56; initial if (T14[24:16]!==9'h34) $stop;
//
parameter THREEPP_32P_WIDE = 3'd4*3'd4*2+3'd3;
parameter THREE_32_WIDE = 3%32;
parameter THIRTYTWO = 2; // Param is 32 bits
parameter [40:0] WIDEPARAM = 41'h12_3456789a;
parameter [40:0] WIDEPARAM2 = WIDEPARAM;
reg [7:0] eightb;
reg [3:0] fourb;
wire [7:0] eight = 8'b00010000;
wire [1:0] eight2two = eight[THREE_32_WIDE+1:THREE_32_WIDE];
wire [2:0] threebits = ALSO_THREE_WIDE;
// surefire lint_off CWCCXX
initial _ranit = 0;
always @ (posedge clk) begin
if (!_ranit) begin
_ranit <= 1;
$write("[%0t] t_param: Running\n", $time);
//
$write(" %d %d %d\n", par1,par2,par3);
if (par1!==5'd1) $stop;
if (par2!==5'd2) $stop;
if (par3!==5'd3) $stop;
if (par4!==5'd3) $stop;
if (varwidth1!==2'd2) $stop;
if (varwidth2!==3'd2) $stop;
if (varwidth3!==4'd2) $stop;
if (varwidth4!==4'd2) $stop;
if (threebits !== 3'b011) $stop;
if (eight !== 8'b00010000) $stop;
if (eight2two !== 2'b10) $stop;
$write(" Params = %b %b\n %b %b\n",
THREEPP_32_WIDE,THREEPP_3_WIDE,
THIRTYTWO, THREEPP_32P_WIDE);
if (THREEPP_32_WIDE !== 32'h23) $stop;
if (THREEPP_3_WIDE !== 3'h3) $stop;
if (THREEPP_32P_WIDE !== 32'h23) $stop;
if (THIRTYTWO[1:0] !== 2'h2) $stop;
if (THIRTYTWO !== 32'h2) $stop;
if (THIRTYTWO !== 2) $stop;
if ((THIRTYTWO[1:0]+2'b00) !== 2'b10) $stop;
if ({1'b1,{THIRTYTWO[1:0]+2'b00}} !== 3'b110) $stop;
if (XX===0 || XX===1 || XX===2 || XX===3) $stop; // Paradoxical but right, since 1'bx!=0 && !=1
//
// Example of assignment LHS affecting expression widths.
// verilator lint_off WIDTH
// surefire lint_off ASWCMB
// surefire lint_off ASWCBB
eightb = (4'd8+4'd8)/4'd4; if (eightb!==8'd4) $stop;
fourb = (4'd8+4'd8)/4'd4; if (fourb!==4'd0) $stop;
fourb = (4'd8+8)/4'd4; if (fourb!==4'd4) $stop;
// verilator lint_on WIDTH
// surefire lint_on ASWCMB
// surefire lint_on ASWCBB
//
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
//*****************************************************************************
// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: mcb_flow_control.v
// /___/ /\ Date Last Modified: $Date: 2011/05/27 14:31:13 $
// \ \ / \ Date Created:
// \___\/\___\
//
//Device: Virtex 6
//Design Name: DDR2/DDR3
//Purpose: This module is the main flow control between cmd_gen.v,
// write_data_path and read_data_path modules.
//Reference:
//Revision History: 7/29/10 Support V6 Back-to-back commands over user interface.
//
//*****************************************************************************
`timescale 1ps/1ps
module memc_flow_vcontrol #
(
parameter TCQ = 100,
parameter nCK_PER_CLK = 4,
parameter NUM_DQ_PINS = 32,
parameter BL_WIDTH = 6,
parameter MEM_BURST_LEN = 4,
parameter FAMILY = "SPARTAN6",
parameter MEM_TYPE = "DDR3"
)
(
input clk_i,
input [9:0] rst_i,
input [3:0] data_mode_i,
input [5:0] cmds_gap_delay_value,
// interface to cmd_gen, pipeline inserter
output reg cmd_rdy_o,
input cmd_valid_i,
input [2:0] cmd_i,
input [31:0] addr_i,
input [BL_WIDTH - 1:0] bl_i,
// interface to mcb_cmd port
input mcb_cmd_full,
input mcb_wr_full_i,
output reg [2:0] cmd_o,
output [31:0] addr_o,
output reg [BL_WIDTH-1:0] bl_o,
output cmd_en_o, // interface to write data path module
// *** interface to qdr ****
output reg qdr_rd_cmd_o,
// *************************
input mcb_wr_en_i,
input last_word_wr_i,
input wdp_rdy_i,
output reg wdp_valid_o,
output reg wdp_validB_o,
output reg wdp_validC_o,
output [31:0] wr_addr_o,
output [BL_WIDTH-1:0] wr_bl_o,
// interface to read data path module
input rdp_rdy_i,
output reg rdp_valid_o,
output [31:0] rd_addr_o,
output [BL_WIDTH-1:0] rd_bl_o
);
//FSM State Defination
localparam READY = 5'b00001,
READ = 5'b00010,
WRITE = 5'b00100,
CMD_WAIT = 5'b01000,
REFRESH_ST = 5'b10000;
localparam RD = 3'b001;
localparam RDP = 3'b011;
localparam WR = 3'b000;
localparam WRP = 3'b010;
localparam REFRESH = 3'b100;
localparam NOP = 3'b101; // this defination is local to this traffic gen and is not defined
reg cmd_fifo_rdy;
wire cmd_rd;
wire cmd_wr; // need equation
wire cmd_others;
reg push_cmd;
//reg xfer_cmd;
reg rd_vld ;
reg wr_vld;
reg cmd_rdy;
reg [31:0] addr_r;
reg [2:0] bank_cnt;
reg [2:0] cmd_reg;
reg [31:0] addr_reg;
reg [BL_WIDTH - 1:0] bl_reg;
reg [BL_WIDTH :0] cmd_counts;
reg rdp_valid;
(*EQUIVALENT_REGISTER_REMOVAL="NO"*) reg wdp_valid,wdp_validB,wdp_validC;
reg [4:0] current_state;
reg [4:0] next_state;
reg [3:0] tstpointA;
reg push_cmd_r;
reg wait_done;
reg cmd_en_r1 ;
reg wr_in_progress,wr_in_progress_r;
reg wrcmd_in_progress;
//reg [10:0] INC_COUNTS;
reg push_cmd_valid;
reg wr_path_full_r;
reg rdcmd_in_progress;
//localparam MEM_BURST_INT = (MEM_BURST_LEN == "8")? 8 : 4;
localparam MEM_BURST_INT = MEM_BURST_LEN ;
reg[5:0] commands_delay_counters;
reg goahead;
reg cmd_rdy_latch;
reg cmd_en_r2; // Spartan 6 use only
reg [3:0] addr_INC;
reg [8*50:0] flow_command;
always @ (posedge clk_i) begin
if (data_mode_i == 4'b1000 || FAMILY == "SPARTAN6" )
addr_INC <= #TCQ 0;
else // *** need to uncomment this for Fuji
addr_INC <= #TCQ MEM_BURST_LEN[3:0]; // *** need to uncomment this for Fuji
end
/*
always @ (posedge clk_i) begin
if ( (NUM_DQ_PINS >= 128 && NUM_DQ_PINS <= 144)) //256
INC_COUNTS <= #TCQ 64 * (MEM_BURST_INT/4);
else if ( (NUM_DQ_PINS >= 64 && NUM_DQ_PINS < 128)) //256
INC_COUNTS <= #TCQ 32 * (MEM_BURST_INT/4);
else if ((NUM_DQ_PINS >= 32) && (NUM_DQ_PINS < 64)) //128
INC_COUNTS <= #TCQ 16 * (MEM_BURST_INT/4) ;
else if ((NUM_DQ_PINS == 16) || (NUM_DQ_PINS == 24)) //64
INC_COUNTS <= #TCQ 8 * (MEM_BURST_INT/4);
else if ((NUM_DQ_PINS == 8) )
INC_COUNTS <= #TCQ 4 * (MEM_BURST_INT/4);
end
*/
// mcb_command bus outputs
always @(posedge clk_i) begin
if (rst_i[0] ) begin
commands_delay_counters <= 6'b00000;
goahead <= 1'b1;
end
else if (cmds_gap_delay_value == 5'd0)
goahead <= 1'b1;
else if ((wr_in_progress || wrcmd_in_progress || rdcmd_in_progress || cmd_rdy_o) ) begin
commands_delay_counters <= 6'b00000;
goahead <= 1'b0;
end
else
if (commands_delay_counters == cmds_gap_delay_value) begin
commands_delay_counters <= commands_delay_counters ;
goahead <= 1'b1;
end
else
commands_delay_counters <= commands_delay_counters + 1'b1;
end
assign cmd_en_o = (FAMILY == "VIRTEX6") ? cmd_en_r1 : (~cmd_en_r1 & cmd_en_r2) ;
always @ (posedge clk_i) begin
cmd_rdy_o <= #TCQ cmd_rdy;
end
//generate
//if (FAMILY == "VIRTEX6") begin
always @ (posedge clk_i)
begin
if (rst_i[8])
cmd_en_r1 <= #TCQ 1'b0;
else if (cmd_counts == 1 && (!mcb_cmd_full && cmd_en_r1 || mcb_wr_full_i))
cmd_en_r1 <= #TCQ 1'b0;
else if ( rdcmd_in_progress || wrcmd_in_progress && MEM_TYPE != "QDR2PLUS" ||
mcb_wr_en_i && MEM_TYPE == "QDR2PLUS")
cmd_en_r1 <= #TCQ 1'b1;
else if (!mcb_cmd_full )
cmd_en_r1 <= #TCQ 1'b0;
end
//end endgenerate
always @ (posedge clk_i)
begin
if (rst_i[8])
cmd_en_r2 <= #TCQ 1'b0;
else
cmd_en_r2 <= cmd_en_r1;
end
// QDR rd command generation
always @ (posedge clk_i)
begin
if (rst_i[8])
qdr_rd_cmd_o <= #TCQ 1'b0;
else if (cmd_counts == 1 && !mcb_cmd_full && rdcmd_in_progress && cmd_en_r1)
qdr_rd_cmd_o <= #TCQ 1'b0;
else if ( rdcmd_in_progress )
qdr_rd_cmd_o <= #TCQ 1'b1;
else if (!mcb_cmd_full)
qdr_rd_cmd_o <= #TCQ 1'b0;
end
always @ (posedge clk_i)
begin
if (rst_i[9])
cmd_fifo_rdy <= #TCQ 1'b1;
else if (cmd_en_r1 || mcb_cmd_full)//(xfer_cmd)
cmd_fifo_rdy <= #TCQ 1'b0;
else if (!mcb_cmd_full)
cmd_fifo_rdy <= #TCQ 1'b1;
end
always @ (posedge clk_i)
begin
if (rst_i[9]) begin
cmd_o <= #TCQ 'b0;
bl_o <= #TCQ 'b0;
end
//else if (xfer_cmd && current_state == READ ) begin // this one has bug
else if (push_cmd_r && current_state == READ ) begin
cmd_o <= #TCQ cmd_i;
bl_o <= #TCQ bl_i - 1'b1;
end
else if ( push_cmd_r && current_state == WRITE) begin
if (FAMILY == "SPARTAN6")
cmd_o <= #TCQ cmd_reg;
else
cmd_o <= #TCQ {2'b00,cmd_reg[0]};
bl_o <= #TCQ bl_reg;
end
end
always @ (posedge clk_i)
if (push_cmd)
addr_reg <= #TCQ addr_i;
reg COuta;
always @ (posedge clk_i)
begin
if (push_cmd && cmd_rd) begin
addr_r <= #TCQ addr_i;
end
else if (push_cmd_r && current_state != READ) begin
addr_r <= #TCQ addr_reg;
end
//else if (xfer_cmd ) begin
else if ((wrcmd_in_progress && ~mcb_cmd_full)|| (rdcmd_in_progress && cmd_en_r1 && ~mcb_cmd_full)) begin
if (cmd_en_r1) begin
// for V6, BL 8, BL 4
if (MEM_TYPE == "QDR2PLUS")
{COuta,addr_r[31:0]} <= addr_o + 1;
else
{COuta,addr_r[31:0]} <= addr_o + addr_INC;
end
end
end
//assign addr_o[24:0] = addr_r[24:0];
//assign addr_o[27:25] = bank_cnt;
//assign addr_o[31:28] = addr_r[31:28];
//assign addr_o[8:0] = addr_r[8:0];
//assign addr_o[31:9] = 'b0;
assign addr_o = addr_r;
// go directly to wr_datapath and rd_datapath modules
assign wr_addr_o = addr_i;
assign rd_addr_o = addr_i;
assign rd_bl_o = bl_i ;
assign wr_bl_o = bl_i ;
always @ (posedge clk_i)
begin
wdp_valid_o <= wdp_valid;
wdp_validB_o <= wdp_validB;
wdp_validC_o <= wdp_validC;
end
always @ (posedge clk_i)
begin
rdp_valid_o <= rdp_valid;
end
// internal control siganls
always @ (posedge clk_i)
begin
if (rst_i[8])
wait_done <= #TCQ 1'b1;
else if (push_cmd_r)
wait_done <= #TCQ 1'b1;
else if (cmd_rdy_o && cmd_valid_i && FAMILY == "SPARTAN6")
wait_done <= #TCQ 1'b0;
end
//
always @ (posedge clk_i)
begin
push_cmd_r <= #TCQ push_cmd;
end
always @ (posedge clk_i)
if (push_cmd)
begin
cmd_reg <= #TCQ cmd_i;
bl_reg <= #TCQ bl_i - 1'b1;
end
always @ (posedge clk_i)
begin
if (push_cmd)
if (bl_i == 0)
if (MEM_BURST_LEN == 8)
if (nCK_PER_CLK == 4)
cmd_counts <= #TCQ {2'b01, {BL_WIDTH-1{1'b0}}};
else
if (FAMILY == "SPARTAN6")
cmd_counts <= {1'b0,bl_i} ;
else
cmd_counts <= #TCQ {3'b001, {BL_WIDTH-2{1'b0}}};
else// not tested yet in MEM_BURST_LEN == 4
cmd_counts <= {1'b0,{BL_WIDTH{1'b1}}} ;//- 2;//63;
else
if (MEM_BURST_LEN == 8)
if (nCK_PER_CLK == 4)
cmd_counts <= {1'b0,bl_i} ;
else
if (FAMILY == "SPARTAN6")
cmd_counts <= {1'b0,bl_i} ;
else
cmd_counts <= {3'b000,bl_i[BL_WIDTH-2:1]};
else // not tested yet in MEM_BURST_LEN == 4
cmd_counts <= {1'b0,bl_i} ;//- 1 ;// {1'b0,bl_i[5:1]} -2;
else if ((wrcmd_in_progress || rdcmd_in_progress ) && cmd_en_r1 && ~mcb_cmd_full)
//if (MEM_BURST_LEN == 8 && cmd_counts > 0)
if ( cmd_counts > 0)
// cmd_counts <= cmd_counts - 2;
if (FAMILY == "VIRTEX6")
cmd_counts <= cmd_counts - 1'b1;
else
if (wrcmd_in_progress)
cmd_counts <= cmd_counts - 1'b1;
else
cmd_counts <= 0;
end
//--Command Decodes--
assign cmd_wr = ((cmd_i == WR | cmd_i == WRP) & cmd_valid_i ) ? 1'b1 : 1'b0;
assign cmd_rd = ((cmd_i == RD | cmd_i == RDP) & cmd_valid_i) ? 1'b1 : 1'b0;
assign cmd_others = ((cmd_i[2] == 1'b1)& cmd_valid_i && (FAMILY == "SPARTAN6")) ? 1'b1 : 1'b0;
reg cmd_wr_pending_r1;
always @ (posedge clk_i)
begin
if (rst_i[0])
cmd_wr_pending_r1 <= #TCQ 1'b0;
//else if (current_state == WRITE && last_word_wr_i && !cmd_fifo_rdy)
//else if ( last_word_wr_i && !cmd_fifo_rdy)
else if ( last_word_wr_i )
cmd_wr_pending_r1 <= #TCQ 1'b1;
else if (push_cmd)//xfer_cmd)
cmd_wr_pending_r1 <= #TCQ 1'b0;
end
// corner case if fixed read command with fixed bl 64
always @ (posedge clk_i)
begin
if (rst_i[0])
wr_in_progress <= #TCQ 1'b0;
else if (last_word_wr_i )
wr_in_progress <= #TCQ 1'b0;
else if (push_cmd && cmd_wr)
wr_in_progress <= #TCQ 1'b1;
end
always @ (posedge clk_i)
begin
if (rst_i[0])
wrcmd_in_progress <= #TCQ 1'b0;
//else if (last_word_wr_i )
else if (cmd_wr && push_cmd )
wrcmd_in_progress <= #TCQ 1'b1;
else if (cmd_counts == 0 || cmd_counts == 1)
wrcmd_in_progress <= #TCQ 1'b0;
end
always @ (posedge clk_i)
begin
if (rst_i[0])
rdcmd_in_progress <= #TCQ 1'b0;
else if (cmd_rd && push_cmd)
rdcmd_in_progress <= #TCQ 1'b1;
else if (cmd_counts <= 1)
rdcmd_in_progress <= #TCQ 1'b0;
end
always @ (posedge clk_i)
begin
if (rst_i[0])
current_state <= #TCQ 5'b00001;
else
current_state <= #TCQ next_state;
end
// mcb_flow_control statemachine
always @ (*)
begin
push_cmd = 1'b0;
// xfer_cmd = 1'b0;
wdp_valid = 1'b0;
wdp_validB = 1'b0;
wdp_validC = 1'b0;
rdp_valid = 1'b0;
cmd_rdy = 1'b0;
next_state = current_state;
case(current_state)
READY:
begin
if(rdp_rdy_i && cmd_rd && ~mcb_cmd_full) //rdp_rdy_i comes from read_data path
begin
next_state = READ;
push_cmd = 1'b1;
// xfer_cmd = 1'b0;
rdp_valid = 1'b1;
cmd_rdy = 1'b1;
end
else if (wdp_rdy_i && cmd_wr && ~mcb_cmd_full)
begin
next_state = WRITE;
push_cmd = 1'b1;
wdp_valid = 1'b1;
wdp_validB = 1'b1;
wdp_validC = 1'b1;
cmd_rdy = 1'b1;
end
else if ( cmd_others && cmd_fifo_rdy)
begin
next_state = REFRESH_ST;
push_cmd = 1'b1;
// xfer_cmd = 1'b0;
cmd_rdy = 1'b0;
end
else
begin
next_state = READY;
push_cmd = 1'b0;
cmd_rdy = 1'b0;
end
end
REFRESH_ST : begin
if (rdp_rdy_i && cmd_rd && cmd_fifo_rdy )
begin
next_state = READ;
push_cmd = 1'b1;
rdp_valid = 1'b1;
wdp_valid = 1'b0;
// xfer_cmd = 1'b1;
// tstpointA = 4'b0101;
end
else if (cmd_fifo_rdy && cmd_wr && wdp_rdy_i )
begin
next_state = WRITE;
push_cmd = 1'b1;
// xfer_cmd = 1'b1;
wdp_valid = 1'b1;
wdp_validB = 1'b1;
wdp_validC = 1'b1;
// tstpointA = 4'b0110;
end
else if (cmd_fifo_rdy && cmd_others)
begin
push_cmd = 1'b1;
// xfer_cmd = 1'b1;
end
else if (!cmd_fifo_rdy)
begin
next_state = CMD_WAIT;
tstpointA = 4'b1001;
end
else
next_state = READ;
cmd_rdy = 1'b0;
end
READ: begin
if (rdcmd_in_progress )
begin
next_state = READ;
push_cmd = 1'b0;
rdp_valid = 1'b0;
wdp_valid = 1'b0;
tstpointA = 4'b0101;
end
else if (!rdp_rdy_i )
begin
next_state = READ;
push_cmd = 1'b0;
tstpointA = 4'b0111;
wdp_valid = 1'b0;
wdp_validB = 1'b0;
wdp_validC = 1'b0;
rdp_valid = 1'b0;
end
else if (~cmd_fifo_rdy && ~rdcmd_in_progress && goahead)
begin
next_state = CMD_WAIT;
tstpointA = 4'b1001;
end
else if (goahead)
begin
next_state = READY;
cmd_rdy = 1'b0;
end
else
next_state = READ;
end
WRITE: begin // for write, always wait until the last_word_wr
if ( wr_in_progress || wrcmd_in_progress || push_cmd_r )
begin
next_state = WRITE;
tstpointA = 4'b0001;
wdp_valid = 1'b0;
wdp_validB = 1'b0;
wdp_validC = 1'b0;
push_cmd = 1'b0;
end
else if (!cmd_fifo_rdy && last_word_wr_i && goahead)
begin
next_state = CMD_WAIT;
push_cmd = 1'b0;
tstpointA = 4'b0011;
end
else if (goahead) begin
next_state = READY;
tstpointA = 4'b0100;
end
else
next_state = WRITE;
cmd_rdy = 1'b0;
end
CMD_WAIT: if (!cmd_fifo_rdy || wr_in_progress)
begin
next_state = CMD_WAIT;
cmd_rdy = 1'b0;
tstpointA = 4'b1010;
end
else if (cmd_fifo_rdy && rdp_rdy_i && cmd_rd)
begin
next_state = READY;
push_cmd = 1'b0;
cmd_rdy = 1'b0;
rdp_valid = 1'b0;
tstpointA = 4'b1011;
end
else if (cmd_fifo_rdy && cmd_wr && goahead && (wait_done || cmd_wr_pending_r1))
begin
next_state = READY;
push_cmd = 1'b0;
cmd_rdy = 1'b0;
wdp_valid = 1'b0;
wdp_validB = 1'b0;
wdp_validC = 1'b0;
tstpointA = 4'b1100;
end
else
begin
next_state = CMD_WAIT;
tstpointA = 4'b1110;
cmd_rdy = 1'b0;
end
default:
begin
push_cmd = 1'b0;
wdp_valid = 1'b0;
wdp_validB = 1'b0;
wdp_validC = 1'b0;
next_state = READY;
end
endcase
end
//synthesis translate_off
/*
always @(current_state)
begin
casex (current_state)
5'b00001 : flow_command = "READY";
5'b00010 : flow_command = "READ" ;
5'b00100 : flow_command = "WRITE";
5'b01000 : flow_command = "CMD_WAIT" ;
5'b10000 : flow_command = "REFRESH_ST";
default : flow_command = "XXXXX";
endcase
end
*/
//synthesis translate_on
endmodule
|
//
// Simple TX-only UART implementation
//
// Copyright (c) 2013 Jared Boone, ShareBrained Technology, Inc.
//
// This file is part of Project Daisho.
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; see the file COPYING. If not, write to
// the Free Software Foundation, Inc., 51 Franklin Street,
// Boston, MA 02110-1301, USA.
//
module uart_debug (
input wire clk_50,
input wire reset,
input wire mii_clk,
input wire [3:0] mii_in,
input wire mii_en,
output wire uart_tx
);
reg [9:0] baud_counter;
reg uart_shift_en;
always @(posedge clk_50) begin
uart_shift_en <= 0;
if (reset) begin
baud_counter <= 0;
end
else
begin
baud_counter <= baud_counter + 10'b1;
if (baud_counter == 217) begin
baud_counter <= 0;
uart_shift_en <= 1;
end
end
end
wire [7:0] nibble_ascii;
nibble_ascii nibble_ascii_rxd (
.nibble(mii_in),
.ascii(nibble_ascii)
);
parameter [3:0] ST_UART_IDLE = 0,
ST_UART_START = 1,
ST_UART_D0 = 2,
ST_UART_D1 = 3,
ST_UART_D2 = 4,
ST_UART_D3 = 5,
ST_UART_D4 = 6,
ST_UART_D5 = 7,
ST_UART_D6 = 8,
ST_UART_D7 = 9,
ST_UART_STOP = 10
;
reg [3:0] state_uart;
reg tx_bit;
assign uart_tx = tx_bit;
wire fifo_uart_reset = reset;
wire fifo_uart_i_clk = mii_clk;
wire fifo_uart_i_full;
wire fifo_uart_i_req = mii_en;
wire [7:0] fifo_uart_i_data = nibble_ascii;
wire fifo_uart_o_clk = clk_50;
wire fifo_uart_o_empty;
wire fifo_uart_o_not_empty = !fifo_uart_o_empty;
reg fifo_uart_o_req;
wire [7:0] fifo_uart_o_data;
reg fifo_uart_i_req_q;
wire end_of_packet = (fifo_uart_i_req == 0) && (fifo_uart_i_req_q == 1);
always @(posedge fifo_uart_i_clk) begin
if (reset) begin
fifo_uart_i_req_q <= 0;
end
else
begin
fifo_uart_i_req_q <= fifo_uart_i_req;
end
end
fifo_uart fifo_uart_inst (
.aclr ( fifo_uart_reset ),
.wrclk ( fifo_uart_i_clk ),
.wrfull ( fifo_uart_i_full ),
.wrreq ( fifo_uart_i_req || end_of_packet ),
.data ( end_of_packet ? 8'h0a : fifo_uart_i_data ),
.rdclk ( fifo_uart_o_clk ),
.rdempty ( fifo_uart_o_empty ),
.rdreq ( fifo_uart_o_req ),
.q ( fifo_uart_o_data )
);
always @(posedge clk_50) begin
fifo_uart_o_req <= 0;
if (reset) begin
state_uart <= ST_UART_IDLE;
tx_bit <= 1;
end
else
begin
if (uart_shift_en) begin
case(state_uart)
ST_UART_IDLE: begin
if (fifo_uart_o_not_empty) begin
fifo_uart_o_req <= 1;
state_uart <= ST_UART_START;
end
end
ST_UART_START: begin
tx_bit <= 0;
state_uart <= ST_UART_D0;
end
ST_UART_D0: begin
tx_bit <= fifo_uart_o_data[0];
state_uart <= ST_UART_D1;
end
ST_UART_D1: begin
tx_bit <= fifo_uart_o_data[1];
state_uart <= ST_UART_D2;
end
ST_UART_D2: begin
tx_bit <= fifo_uart_o_data[2];
state_uart <= ST_UART_D3;
end
ST_UART_D3: begin
tx_bit <= fifo_uart_o_data[3];
state_uart <= ST_UART_D4;
end
ST_UART_D4: begin
tx_bit <= fifo_uart_o_data[4];
state_uart <= ST_UART_D5;
end
ST_UART_D5: begin
tx_bit <= fifo_uart_o_data[5];
state_uart <= ST_UART_D6;
end
ST_UART_D6: begin
tx_bit <= fifo_uart_o_data[6];
state_uart <= ST_UART_D7;
end
ST_UART_D7: begin
tx_bit <= fifo_uart_o_data[7];
state_uart <= ST_UART_STOP;
end
ST_UART_STOP: begin
tx_bit <= 1;
state_uart <= ST_UART_IDLE;
end
endcase
end
end
end
endmodule
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of avfb_top_rs
//
// Generated
// by: wig
// on: Tue Apr 25 19:40:28 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bugver.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: avfb_top_rs.v,v 1.1 2006/07/10 07:30:08 wig Exp $
// $Date: 2006/07/10 07:30:08 $
// $Log: avfb_top_rs.v,v $
// Revision 1.1 2006/07/10 07:30:08 wig
// Updated more testcasess.
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.83 2006/04/19 07:32:08 wig Exp
//
// Generator: mix_0.pl Revision: 1.44 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of avfb_top_rs
//
// No user `defines in this module
module avfb_top_rs
//
// Generated module i_avfb_top_rs
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
// Generated Instance Port Map for i_rs_i2c_dcs
rs_I2C_DCS i_rs_i2c_dcs (
);
// End of Generated Instance Port Map for i_rs_i2c_dcs
endmodule
//
// End of Generated Module rtl of avfb_top_rs
//
//
//!End of Module/s
// --------------------------------------------------------------
|
////////////////////////////////////////////////////////////////////////////////
// //
// This file is placed into the Public Domain, for any use, without warranty. //
// 2012 by Iztok Jeras //
// //
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// //
// This testbench contains a bus source and a bus drain. The source creates //
// address and data bus values, while the drain is the final destination of //
// such pairs. All source and drain transfers are logged into memories, which //
// are used at the end of simulation to check for data transfer correctness. //
// Inside the RLT wrapper there is a multiplexer and a demultiplexer, they //
// bus transfers into a 8bit data stream and back. Both stream input and //
// output are exposed, they are connected together into a loopback. //
// //
// ----------- --------------------- //
// | bso_mem | | wrap | //
// ----------- | | //
// ----------- | | ----------- | //
// | bsi src | ------------> | -> | mux | -> | -> - sto //
// ----------- | ----------- | \ //
// | | | loopback //
// ----------- | ----------- | / //
// | bso drn | <------------ | <- | demux | <- | <- - sti //
// ----------- | | ----------- | //
// ----------- | | //
// | bso_mem | | | //
// ----------- --------------------- //
// //
// PROTOCOL: //
// //
// The 'vld' signal is driven by the source to indicate valid data is //
// available, 'rdy' is used by the drain to indicate is is ready to accept //
// valid data. A data transfer only happens if both 'vld' & 'rdy' are active. //
// //
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns/1ps
// include RTL files
`include "t_sv_bus_mux_demux/sv_bus_mux_demux_def.sv"
`include "t_sv_bus_mux_demux/sv_bus_mux_demux_demux.sv"
`include "t_sv_bus_mux_demux/sv_bus_mux_demux_mux.sv"
`include "t_sv_bus_mux_demux/sv_bus_mux_demux_wrap.sv"
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
parameter SIZ = 10;
// system signals
//logic clk = 1'b1; // clock
logic rst = 1'b1; // reset
integer rst_cnt = 0;
// input bus
logic bsi_vld; // valid (chip select)
logic [31:0] bsi_adr; // address
logic [31:0] bsi_dat; // data
logic bsi_rdy; // ready (acknowledge)
logic bsi_trn; // data transfer
logic [31:0] bsi_mem [SIZ];
// output stream
logic sto_vld; // valid (chip select)
logic [7:0] sto_bus; // data bus
logic sto_rdy; // ready (acknowledge)
// input stream
logic sti_vld; // valid (chip select)
logic [7:0] sti_bus; // data bus
logic sti_rdy; // ready (acknowledge)
// output bus
logic bso_vld; // valid (chip select)
logic [31:0] bso_adr; // address
logic [31:0] bso_dat; // data
logic bso_rdy; // ready (acknowledge)
logic bso_trn; // data transfer
logic [31:0] bso_mem [SIZ];
integer bso_cnt = 0;
////////////////////////////////////////////////////////////////////////////////
// clock and reset
////////////////////////////////////////////////////////////////////////////////
// clock toggling
//always #5 clk = ~clk;
// reset is removed after a delay
always @ (posedge clk)
begin
rst_cnt <= rst_cnt + 1;
rst <= rst_cnt <= 3;
end
// reset is removed after a delay
always @ (posedge clk)
if (bso_cnt == SIZ) begin
if (bsi_mem === bso_mem) begin $write("*-* All Finished *-*\n"); $finish(); end
else begin $display ("FAILED"); $stop(); end
end
////////////////////////////////////////////////////////////////////////////////
// input data generator
////////////////////////////////////////////////////////////////////////////////
// input data transfer
assign bsi_trn = bsi_vld & bsi_rdy;
// valid (for SIZ transfers)
always @ (posedge clk, posedge rst)
if (rst) bsi_vld = 1'b0;
else bsi_vld = (bsi_adr < SIZ);
// address (increments every transfer)
always @ (posedge clk, posedge rst)
if (rst) bsi_adr <= 32'h00000000;
else if (bsi_trn) bsi_adr <= bsi_adr + 'd1;
// data (new random value generated after every transfer)
always @ (posedge clk, posedge rst)
if (rst) bsi_dat <= 32'h00000000;
else if (bsi_trn) bsi_dat <= $random();
// storing transferred data into memory for final check
always @ (posedge clk)
if (bsi_trn) bsi_mem [bsi_adr] <= bsi_dat;
////////////////////////////////////////////////////////////////////////////////
// RTL instance
////////////////////////////////////////////////////////////////////////////////
sv_bus_mux_demux_wrap wrap (
// system signals
.clk (clk),
.rst (rst),
// input bus
.bsi_vld (bsi_vld),
.bsi_adr (bsi_adr),
.bsi_dat (bsi_dat),
.bsi_rdy (bsi_rdy),
// output stream
.sto_vld (sto_vld),
.sto_bus (sto_bus),
.sto_rdy (sto_rdy),
// input stream
.sti_vld (sti_vld),
.sti_bus (sti_bus),
.sti_rdy (sti_rdy),
// output bus
.bso_vld (bso_vld),
.bso_adr (bso_adr),
.bso_dat (bso_dat),
.bso_rdy (bso_rdy)
);
// stream output from mux is looped back into stream input for demux
assign sti_vld = sto_vld;
assign sti_bus = sto_bus;
assign sto_rdy = sti_rdy;
////////////////////////////////////////////////////////////////////////////////
// output data monitor
////////////////////////////////////////////////////////////////////////////////
// input data transfer
assign bso_trn = bso_vld & bso_rdy;
// output transfer counter used to end the test
always @ (posedge clk, posedge rst)
if (rst) bso_cnt <= 0;
else if (bso_trn) bso_cnt <= bso_cnt + 1;
// storing transferred data into memory for final check
always @ (posedge clk)
if (bso_trn) bso_mem [bso_adr] <= bso_dat;
// every output transfer against expected value stored in memory
always @ (posedge clk)
if (bso_trn && (bsi_mem [bso_adr] !== bso_dat))
$display ("@%08h i:%08h o:%08h", bso_adr, bsi_mem [bso_adr], bso_dat);
// ready is active for SIZ transfers
always @ (posedge clk, posedge rst)
if (rst) bso_rdy = 1'b0;
else bso_rdy = 1'b1;
endmodule : sv_bus_mux_demux_tb
|
//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_design_niosII_core_cpu_debug_slave_wrapper (
// inputs:
MonDReg,
break_readreg,
clk,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
// outputs:
jdo,
jrst_n,
st_ready_test_idle,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a
)
;
output [ 37: 0] jdo;
output jrst_n;
output st_ready_test_idle;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input clk;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
wire [ 37: 0] jdo;
wire jrst_n;
wire [ 37: 0] sr;
wire st_ready_test_idle;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire vji_cdr;
wire [ 1: 0] vji_ir_in;
wire [ 1: 0] vji_ir_out;
wire vji_rti;
wire vji_sdr;
wire vji_tck;
wire vji_tdi;
wire vji_tdo;
wire vji_udr;
wire vji_uir;
//Change the sld_virtual_jtag_basic's defparams to
//switch between a regular Nios II or an internally embedded Nios II.
//For a regular Nios II, sld_mfg_id = 70, sld_type_id = 34.
//For an internally embedded Nios II, slf_mfg_id = 110, sld_type_id = 135.
soc_design_niosII_core_cpu_debug_slave_tck the_soc_design_niosII_core_cpu_debug_slave_tck
(
.MonDReg (MonDReg),
.break_readreg (break_readreg),
.dbrk_hit0_latch (dbrk_hit0_latch),
.dbrk_hit1_latch (dbrk_hit1_latch),
.dbrk_hit2_latch (dbrk_hit2_latch),
.dbrk_hit3_latch (dbrk_hit3_latch),
.debugack (debugack),
.ir_in (vji_ir_in),
.ir_out (vji_ir_out),
.jrst_n (jrst_n),
.jtag_state_rti (vji_rti),
.monitor_error (monitor_error),
.monitor_ready (monitor_ready),
.reset_n (reset_n),
.resetlatch (resetlatch),
.sr (sr),
.st_ready_test_idle (st_ready_test_idle),
.tck (vji_tck),
.tdi (vji_tdi),
.tdo (vji_tdo),
.tracemem_on (tracemem_on),
.tracemem_trcdata (tracemem_trcdata),
.tracemem_tw (tracemem_tw),
.trc_im_addr (trc_im_addr),
.trc_on (trc_on),
.trc_wrap (trc_wrap),
.trigbrktype (trigbrktype),
.trigger_state_1 (trigger_state_1),
.vs_cdr (vji_cdr),
.vs_sdr (vji_sdr),
.vs_uir (vji_uir)
);
soc_design_niosII_core_cpu_debug_slave_sysclk the_soc_design_niosII_core_cpu_debug_slave_sysclk
(
.clk (clk),
.ir_in (vji_ir_in),
.jdo (jdo),
.sr (sr),
.take_action_break_a (take_action_break_a),
.take_action_break_b (take_action_break_b),
.take_action_break_c (take_action_break_c),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocimem_b (take_action_ocimem_b),
.take_action_tracectrl (take_action_tracectrl),
.take_no_action_break_a (take_no_action_break_a),
.take_no_action_break_b (take_no_action_break_b),
.take_no_action_break_c (take_no_action_break_c),
.take_no_action_ocimem_a (take_no_action_ocimem_a),
.vs_udr (vji_udr),
.vs_uir (vji_uir)
);
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign vji_tck = 1'b0;
assign vji_tdi = 1'b0;
assign vji_sdr = 1'b0;
assign vji_cdr = 1'b0;
assign vji_rti = 1'b0;
assign vji_uir = 1'b0;
assign vji_udr = 1'b0;
assign vji_ir_in = 2'b0;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// sld_virtual_jtag_basic soc_design_niosII_core_cpu_debug_slave_phy
// (
// .ir_in (vji_ir_in),
// .ir_out (vji_ir_out),
// .jtag_state_rti (vji_rti),
// .tck (vji_tck),
// .tdi (vji_tdi),
// .tdo (vji_tdo),
// .virtual_state_cdr (vji_cdr),
// .virtual_state_sdr (vji_sdr),
// .virtual_state_udr (vji_udr),
// .virtual_state_uir (vji_uir)
// );
//
// defparam soc_design_niosII_core_cpu_debug_slave_phy.sld_auto_instance_index = "YES",
// soc_design_niosII_core_cpu_debug_slave_phy.sld_instance_index = 0,
// soc_design_niosII_core_cpu_debug_slave_phy.sld_ir_width = 2,
// soc_design_niosII_core_cpu_debug_slave_phy.sld_mfg_id = 70,
// soc_design_niosII_core_cpu_debug_slave_phy.sld_sim_action = "",
// soc_design_niosII_core_cpu_debug_slave_phy.sld_sim_n_scan = 0,
// soc_design_niosII_core_cpu_debug_slave_phy.sld_sim_total_length = 0,
// soc_design_niosII_core_cpu_debug_slave_phy.sld_type_id = 34,
// soc_design_niosII_core_cpu_debug_slave_phy.sld_version = 3;
//
//synthesis read_comments_as_HDL off
endmodule
|
(************************************************************************)
(* * The Coq Proof Assistant / The Coq Development Team *)
(* v * Copyright INRIA, CNRS and contributors *)
(* <O___,, * (see version control and CREDITS file for authors & dates) *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(* * (see LICENSE file for the text of the license) *)
(************************************************************************)
Require Import Bool NAxioms NSub NPow NDiv NParity NLog.
(** Derived properties of bitwise operations *)
Module Type NBitsProp
(Import A : NAxiomsSig')
(Import B : NSubProp A)
(Import C : NParityProp A B)
(Import D : NPowProp A B C)
(Import E : NDivProp A B)
(Import F : NLog2Prop A B C D).
Include BoolEqualityFacts A.
Ltac order_nz := try apply pow_nonzero; order'.
Hint Rewrite div_0_l mod_0_l div_1_r mod_1_r : nz.
(** Some properties of power and division *)
Lemma pow_sub_r : forall a b c, a~=0 -> c<=b -> a^(b-c) == a^b / a^c.
Proof.
intros a b c Ha H.
apply div_unique with 0.
generalize (pow_nonzero a c Ha) (le_0_l (a^c)); order'.
nzsimpl. now rewrite <- pow_add_r, add_comm, sub_add.
Qed.
Lemma pow_div_l : forall a b c, b~=0 -> a mod b == 0 ->
(a/b)^c == a^c / b^c.
Proof.
intros a b c Hb H.
apply div_unique with 0.
generalize (pow_nonzero b c Hb) (le_0_l (b^c)); order'.
nzsimpl. rewrite <- pow_mul_l. f_equiv. now apply div_exact.
Qed.
(** An injection from bits [true] and [false] to numbers 1 and 0.
We declare it as a (local) coercion for shorter statements. *)
Definition b2n (b:bool) := if b then 1 else 0.
Local Coercion b2n : bool >-> t.
Instance b2n_proper : Proper (Logic.eq ==> eq) b2n.
Proof. solve_proper. Qed.
Lemma exists_div2 a : exists a' (b:bool), a == 2*a' + b.
Proof.
elim (Even_or_Odd a); [intros (a',H)| intros (a',H)].
exists a'. exists false. now nzsimpl.
exists a'. exists true. now simpl.
Qed.
(** We can compact [testbit_odd_0] [testbit_even_0]
[testbit_even_succ] [testbit_odd_succ] in only two lemmas. *)
Lemma testbit_0_r a (b:bool) : testbit (2*a+b) 0 = b.
Proof.
destruct b; simpl; rewrite ?add_0_r.
apply testbit_odd_0.
apply testbit_even_0.
Qed.
Lemma testbit_succ_r a (b:bool) n :
testbit (2*a+b) (succ n) = testbit a n.
Proof.
destruct b; simpl; rewrite ?add_0_r.
apply testbit_odd_succ, le_0_l.
apply testbit_even_succ, le_0_l.
Qed.
(** Alternative characterisations of [testbit] *)
(** This concise equation could have been taken as specification
for testbit in the interface, but it would have been hard to
implement with little initial knowledge about div and mod *)
Lemma testbit_spec' a n : a.[n] == (a / 2^n) mod 2.
Proof.
revert a. induct n.
intros a. nzsimpl.
destruct (exists_div2 a) as (a' & b & H). rewrite H at 1.
rewrite testbit_0_r. apply mod_unique with a'; trivial.
destruct b; order'.
intros n IH a.
destruct (exists_div2 a) as (a' & b & H). rewrite H at 1.
rewrite testbit_succ_r, IH. f_equiv.
rewrite pow_succ_r', <- div_div by order_nz. f_equiv.
apply div_unique with b; trivial.
destruct b; order'.
Qed.
(** This characterisation that uses only basic operations and
power was initially taken as specification for testbit.
We describe [a] as having a low part and a high part, with
the corresponding bit in the middle. This characterisation
is moderatly complex to implement, but also moderately
usable... *)
Lemma testbit_spec a n :
exists l h, 0<=l<2^n /\ a == l + (a.[n] + 2*h)*2^n.
Proof.
exists (a mod 2^n). exists (a / 2^n / 2). split.
split; [apply le_0_l | apply mod_upper_bound; order_nz].
rewrite add_comm, mul_comm, (add_comm a.[n]).
rewrite (div_mod a (2^n)) at 1 by order_nz. do 2 f_equiv.
rewrite testbit_spec'. apply div_mod. order'.
Qed.
Lemma testbit_true : forall a n,
a.[n] = true <-> (a / 2^n) mod 2 == 1.
Proof.
intros a n.
rewrite <- testbit_spec'; destruct a.[n]; split; simpl; now try order'.
Qed.
Lemma testbit_false : forall a n,
a.[n] = false <-> (a / 2^n) mod 2 == 0.
Proof.
intros a n.
rewrite <- testbit_spec'; destruct a.[n]; split; simpl; now try order'.
Qed.
Lemma testbit_eqb : forall a n,
a.[n] = eqb ((a / 2^n) mod 2) 1.
Proof.
intros a n.
apply eq_true_iff_eq. now rewrite testbit_true, eqb_eq.
Qed.
(** Results about the injection [b2n] *)
Lemma b2n_inj : forall (a0 b0:bool), a0 == b0 -> a0 = b0.
Proof.
intros [|] [|]; simpl; trivial; order'.
Qed.
Lemma add_b2n_double_div2 : forall (a0:bool) a, (a0+2*a)/2 == a.
Proof.
intros a0 a. rewrite mul_comm, div_add by order'.
now rewrite div_small, add_0_l by (destruct a0; order').
Qed.
Lemma add_b2n_double_bit0 : forall (a0:bool) a, (a0+2*a).[0] = a0.
Proof.
intros a0 a. apply b2n_inj.
rewrite testbit_spec'. nzsimpl. rewrite mul_comm, mod_add by order'.
now rewrite mod_small by (destruct a0; order').
Qed.
Lemma b2n_div2 : forall (a0:bool), a0/2 == 0.
Proof.
intros a0. rewrite <- (add_b2n_double_div2 a0 0). now nzsimpl.
Qed.
Lemma b2n_bit0 : forall (a0:bool), a0.[0] = a0.
Proof.
intros a0. rewrite <- (add_b2n_double_bit0 a0 0) at 2. now nzsimpl.
Qed.
(** The specification of testbit by low and high parts is complete *)
Lemma testbit_unique : forall a n (a0:bool) l h,
l<2^n -> a == l + (a0 + 2*h)*2^n -> a.[n] = a0.
Proof.
intros a n a0 l h Hl EQ.
apply b2n_inj. rewrite testbit_spec' by trivial.
symmetry. apply mod_unique with h. destruct a0; simpl; order'.
symmetry. apply div_unique with l; trivial.
now rewrite add_comm, (add_comm _ a0), mul_comm.
Qed.
(** All bits of number 0 are 0 *)
Lemma bits_0 : forall n, 0.[n] = false.
Proof.
intros n. apply testbit_false. nzsimpl; order_nz.
Qed.
(** Various ways to refer to the lowest bit of a number *)
Lemma bit0_odd : forall a, a.[0] = odd a.
Proof.
intros a. symmetry.
destruct (exists_div2 a) as (a' & b & EQ).
rewrite EQ, testbit_0_r, add_comm, odd_add_mul_2.
destruct b; simpl; apply odd_1 || apply odd_0.
Qed.
Lemma bit0_eqb : forall a, a.[0] = eqb (a mod 2) 1.
Proof.
intros a. rewrite testbit_eqb. now nzsimpl.
Qed.
Lemma bit0_mod : forall a, a.[0] == a mod 2.
Proof.
intros a. rewrite testbit_spec'. now nzsimpl.
Qed.
(** Hence testing a bit is equivalent to shifting and testing parity *)
Lemma testbit_odd : forall a n, a.[n] = odd (a>>n).
Proof.
intros. now rewrite <- bit0_odd, shiftr_spec, add_0_l.
Qed.
(** [log2] gives the highest nonzero bit *)
Lemma bit_log2 : forall a, a~=0 -> a.[log2 a] = true.
Proof.
intros a Ha.
assert (Ha' : 0 < a) by (generalize (le_0_l a); order).
destruct (log2_spec_alt a Ha') as (r & EQ & (_,Hr)).
rewrite EQ at 1.
rewrite testbit_true, add_comm.
rewrite <- (mul_1_l (2^log2 a)) at 1.
rewrite div_add by order_nz.
rewrite div_small by trivial.
rewrite add_0_l. apply mod_small. order'.
Qed.
Lemma bits_above_log2 : forall a n, log2 a < n ->
a.[n] = false.
Proof.
intros a n H.
rewrite testbit_false.
rewrite div_small. nzsimpl; order'.
apply log2_lt_cancel. rewrite log2_pow2; trivial using le_0_l.
Qed.
(** Hence the number of bits of [a] is [1+log2 a]
(see [Pos.size_nat] and [Pos.size]).
*)
(** Testing bits after division or multiplication by a power of two *)
Lemma div2_bits : forall a n, (a/2).[n] = a.[S n].
Proof.
intros. apply eq_true_iff_eq.
rewrite 2 testbit_true.
rewrite pow_succ_r by apply le_0_l.
now rewrite div_div by order_nz.
Qed.
Lemma div_pow2_bits : forall a n m, (a/2^n).[m] = a.[m+n].
Proof.
intros a n. revert a. induct n.
intros a m. now nzsimpl.
intros n IH a m. nzsimpl; try apply le_0_l.
rewrite <- div_div by order_nz.
now rewrite IH, div2_bits.
Qed.
Lemma double_bits_succ : forall a n, (2*a).[S n] = a.[n].
Proof.
intros. rewrite <- div2_bits. now rewrite mul_comm, div_mul by order'.
Qed.
Lemma mul_pow2_bits_add : forall a n m, (a*2^n).[m+n] = a.[m].
Proof.
intros. rewrite <- div_pow2_bits. now rewrite div_mul by order_nz.
Qed.
Lemma mul_pow2_bits_high : forall a n m, n<=m -> (a*2^n).[m] = a.[m-n].
Proof.
intros a n m ?.
rewrite <- (sub_add n m) at 1 by order'.
now rewrite mul_pow2_bits_add.
Qed.
Lemma mul_pow2_bits_low : forall a n m, m<n -> (a*2^n).[m] = false.
Proof.
intros a n m H. apply testbit_false.
rewrite <- (sub_add m n) by order'. rewrite pow_add_r, mul_assoc.
rewrite div_mul by order_nz.
rewrite <- (succ_pred (n-m)). rewrite pow_succ_r.
now rewrite (mul_comm 2), mul_assoc, mod_mul by order'.
apply lt_le_pred.
apply sub_gt in H. generalize (le_0_l (n-m)); order.
now apply sub_gt.
Qed.
(** Selecting the low part of a number can be done by a modulo *)
Lemma mod_pow2_bits_high : forall a n m, n<=m ->
(a mod 2^n).[m] = false.
Proof.
intros a n m H.
destruct (eq_0_gt_0_cases (a mod 2^n)) as [EQ|LT].
now rewrite EQ, bits_0.
apply bits_above_log2.
apply lt_le_trans with n; trivial.
apply log2_lt_pow2; trivial.
apply mod_upper_bound; order_nz.
Qed.
Lemma mod_pow2_bits_low : forall a n m, m<n ->
(a mod 2^n).[m] = a.[m].
Proof.
intros a n m H.
rewrite testbit_eqb.
rewrite <- (mod_add _ (2^(P (n-m))*(a/2^n))) by order'.
rewrite <- div_add by order_nz.
rewrite (mul_comm _ 2), mul_assoc, <- pow_succ_r', succ_pred
by now apply sub_gt.
rewrite mul_comm, mul_assoc, <- pow_add_r, (add_comm m), sub_add
by order.
rewrite add_comm, <- div_mod by order_nz.
symmetry. apply testbit_eqb.
Qed.
(** We now prove that having the same bits implies equality.
For that we use a notion of equality over functional
streams of bits. *)
Definition eqf (f g:t -> bool) := forall n:t, f n = g n.
Instance eqf_equiv : Equivalence eqf.
Proof.
split; congruence.
Qed.
Local Infix "===" := eqf (at level 70, no associativity).
Instance testbit_eqf : Proper (eq==>eqf) testbit.
Proof.
intros a a' Ha n. now rewrite Ha.
Qed.
(** Only zero corresponds to the always-false stream. *)
Lemma bits_inj_0 :
forall a, (forall n, a.[n] = false) -> a == 0.
Proof.
intros a H. destruct (eq_decidable a 0) as [EQ|NEQ]; trivial.
apply bit_log2 in NEQ. now rewrite H in NEQ.
Qed.
(** If two numbers produce the same stream of bits, they are equal. *)
Lemma bits_inj : forall a b, testbit a === testbit b -> a == b.
Proof.
intros a. pattern a.
apply strong_right_induction with 0;[solve_proper|clear a|apply le_0_l].
intros a _ IH b H.
destruct (eq_0_gt_0_cases a) as [EQ|LT].
rewrite EQ in H |- *. symmetry. apply bits_inj_0.
intros n. now rewrite <- H, bits_0.
rewrite (div_mod a 2), (div_mod b 2) by order'.
f_equiv; [ | now rewrite <- 2 bit0_mod, H].
f_equiv.
apply IH; trivial using le_0_l.
apply div_lt; order'.
intro n. rewrite 2 div2_bits. apply H.
Qed.
Lemma bits_inj_iff : forall a b, testbit a === testbit b <-> a == b.
Proof.
split. apply bits_inj. intros EQ; now rewrite EQ.
Qed.
Hint Rewrite lxor_spec lor_spec land_spec ldiff_spec bits_0 : bitwise.
Tactic Notation "bitwise" "as" simple_intropattern(m)
:= apply bits_inj; intros m; autorewrite with bitwise.
Ltac bitwise := bitwise as ?m.
(** The streams of bits that correspond to a natural numbers are
exactly the ones that are always 0 after some point *)
Lemma are_bits : forall (f:t->bool), Proper (eq==>Logic.eq) f ->
((exists n, f === testbit n) <->
(exists k, forall m, k<=m -> f m = false)).
Proof.
intros f Hf. split.
intros (a,H).
exists (S (log2 a)). intros m Hm. apply le_succ_l in Hm.
rewrite H, bits_above_log2; trivial using lt_succ_diag_r.
intros (k,Hk).
revert f Hf Hk. induct k.
intros f Hf H0.
exists 0. intros m. rewrite bits_0, H0; trivial. apply le_0_l.
intros k IH f Hf Hk.
destruct (IH (fun m => f (S m))) as (n, Hn).
solve_proper.
intros m Hm. apply Hk. now rewrite <- succ_le_mono.
exists (f 0 + 2*n). intros m.
destruct (zero_or_succ m) as [Hm|(m', Hm)]; rewrite Hm.
symmetry. apply add_b2n_double_bit0.
rewrite Hn, <- div2_bits.
rewrite mul_comm, div_add, b2n_div2, add_0_l; trivial. order'.
Qed.
(** Properties of shifts *)
Lemma shiftr_spec' : forall a n m, (a >> n).[m] = a.[m+n].
Proof.
intros. apply shiftr_spec. apply le_0_l.
Qed.
Lemma shiftl_spec_high' : forall a n m, n<=m -> (a << n).[m] = a.[m-n].
Proof.
intros. apply shiftl_spec_high; trivial. apply le_0_l.
Qed.
Lemma shiftr_div_pow2 : forall a n, a >> n == a / 2^n.
Proof.
intros. bitwise. rewrite shiftr_spec'.
symmetry. apply div_pow2_bits.
Qed.
Lemma shiftl_mul_pow2 : forall a n, a << n == a * 2^n.
Proof.
intros a n. bitwise as m.
destruct (le_gt_cases n m) as [H|H].
now rewrite shiftl_spec_high', mul_pow2_bits_high.
now rewrite shiftl_spec_low, mul_pow2_bits_low.
Qed.
Lemma shiftl_spec_alt : forall a n m, (a << n).[m+n] = a.[m].
Proof.
intros. now rewrite shiftl_mul_pow2, mul_pow2_bits_add.
Qed.
Instance shiftr_wd : Proper (eq==>eq==>eq) shiftr.
Proof.
intros a a' Ha b b' Hb. now rewrite 2 shiftr_div_pow2, Ha, Hb.
Qed.
Instance shiftl_wd : Proper (eq==>eq==>eq) shiftl.
Proof.
intros a a' Ha b b' Hb. now rewrite 2 shiftl_mul_pow2, Ha, Hb.
Qed.
Lemma shiftl_shiftl : forall a n m,
(a << n) << m == a << (n+m).
Proof.
intros. now rewrite !shiftl_mul_pow2, pow_add_r, mul_assoc.
Qed.
Lemma shiftr_shiftr : forall a n m,
(a >> n) >> m == a >> (n+m).
Proof.
intros.
now rewrite !shiftr_div_pow2, pow_add_r, div_div by order_nz.
Qed.
Lemma shiftr_shiftl_l : forall a n m, m<=n ->
(a << n) >> m == a << (n-m).
Proof.
intros a n m ?.
rewrite shiftr_div_pow2, !shiftl_mul_pow2.
rewrite <- (sub_add m n) at 1 by trivial.
now rewrite pow_add_r, mul_assoc, div_mul by order_nz.
Qed.
Lemma shiftr_shiftl_r : forall a n m, n<=m ->
(a << n) >> m == a >> (m-n).
Proof.
intros a n m ?.
rewrite !shiftr_div_pow2, shiftl_mul_pow2.
rewrite <- (sub_add n m) at 1 by trivial.
rewrite pow_add_r, (mul_comm (2^(m-n))).
now rewrite <- div_div, div_mul by order_nz.
Qed.
(** shifts and constants *)
Lemma shiftl_1_l : forall n, 1 << n == 2^n.
Proof.
intros. now rewrite shiftl_mul_pow2, mul_1_l.
Qed.
Lemma shiftl_0_r : forall a, a << 0 == a.
Proof.
intros. rewrite shiftl_mul_pow2. now nzsimpl.
Qed.
Lemma shiftr_0_r : forall a, a >> 0 == a.
Proof.
intros. rewrite shiftr_div_pow2. now nzsimpl.
Qed.
Lemma shiftl_0_l : forall n, 0 << n == 0.
Proof.
intros. rewrite shiftl_mul_pow2. now nzsimpl.
Qed.
Lemma shiftr_0_l : forall n, 0 >> n == 0.
Proof.
intros. rewrite shiftr_div_pow2. nzsimpl; order_nz.
Qed.
Lemma shiftl_eq_0_iff : forall a n, a << n == 0 <-> a == 0.
Proof.
intros a n. rewrite shiftl_mul_pow2. rewrite eq_mul_0. split.
intros [H | H]; trivial. contradict H; order_nz.
intros H. now left.
Qed.
Lemma shiftr_eq_0_iff : forall a n,
a >> n == 0 <-> a==0 \/ (0<a /\ log2 a < n).
Proof.
intros a n.
rewrite shiftr_div_pow2, div_small_iff by order_nz.
destruct (eq_0_gt_0_cases a) as [EQ|LT].
rewrite EQ. split. now left. intros _.
assert (H : 2~=0) by order'.
generalize (pow_nonzero 2 n H) (le_0_l (2^n)); order.
rewrite log2_lt_pow2; trivial.
split. right; split; trivial. intros [H|[_ H]]; now order.
Qed.
Lemma shiftr_eq_0 : forall a n, log2 a < n -> a >> n == 0.
Proof.
intros a n H. rewrite shiftr_eq_0_iff.
destruct (eq_0_gt_0_cases a) as [EQ|LT]. now left. right; now split.
Qed.
(** Properties of [div2]. *)
Lemma div2_div : forall a, div2 a == a/2.
Proof.
intros. rewrite div2_spec, shiftr_div_pow2. now nzsimpl.
Qed.
Instance div2_wd : Proper (eq==>eq) div2.
Proof.
intros a a' Ha. now rewrite 2 div2_div, Ha.
Qed.
Lemma div2_odd : forall a, a == 2*(div2 a) + odd a.
Proof.
intros a. rewrite div2_div, <- bit0_odd, bit0_mod.
apply div_mod. order'.
Qed.
(** Properties of [lxor] and others, directly deduced
from properties of [xorb] and others. *)
Instance lxor_wd : Proper (eq ==> eq ==> eq) lxor.
Proof.
intros a a' Ha b b' Hb. bitwise. now rewrite Ha, Hb.
Qed.
Instance land_wd : Proper (eq ==> eq ==> eq) land.
Proof.
intros a a' Ha b b' Hb. bitwise. now rewrite Ha, Hb.
Qed.
Instance lor_wd : Proper (eq ==> eq ==> eq) lor.
Proof.
intros a a' Ha b b' Hb. bitwise. now rewrite Ha, Hb.
Qed.
Instance ldiff_wd : Proper (eq ==> eq ==> eq) ldiff.
Proof.
intros a a' Ha b b' Hb. bitwise. now rewrite Ha, Hb.
Qed.
Lemma lxor_eq : forall a a', lxor a a' == 0 -> a == a'.
Proof.
intros a a' H. bitwise. apply xorb_eq.
now rewrite <- lxor_spec, H, bits_0.
Qed.
Lemma lxor_nilpotent : forall a, lxor a a == 0.
Proof.
intros. bitwise. apply xorb_nilpotent.
Qed.
Lemma lxor_eq_0_iff : forall a a', lxor a a' == 0 <-> a == a'.
Proof.
split. apply lxor_eq. intros EQ; rewrite EQ; apply lxor_nilpotent.
Qed.
Lemma lxor_0_l : forall a, lxor 0 a == a.
Proof.
intros. bitwise. apply xorb_false_l.
Qed.
Lemma lxor_0_r : forall a, lxor a 0 == a.
Proof.
intros. bitwise. apply xorb_false_r.
Qed.
Lemma lxor_comm : forall a b, lxor a b == lxor b a.
Proof.
intros. bitwise. apply xorb_comm.
Qed.
Lemma lxor_assoc :
forall a b c, lxor (lxor a b) c == lxor a (lxor b c).
Proof.
intros. bitwise. apply xorb_assoc.
Qed.
Lemma lor_0_l : forall a, lor 0 a == a.
Proof.
intros. bitwise. trivial.
Qed.
Lemma lor_0_r : forall a, lor a 0 == a.
Proof.
intros. bitwise. apply orb_false_r.
Qed.
Lemma lor_comm : forall a b, lor a b == lor b a.
Proof.
intros. bitwise. apply orb_comm.
Qed.
Lemma lor_assoc :
forall a b c, lor a (lor b c) == lor (lor a b) c.
Proof.
intros. bitwise. apply orb_assoc.
Qed.
Lemma lor_diag : forall a, lor a a == a.
Proof.
intros. bitwise. apply orb_diag.
Qed.
Lemma lor_eq_0_l : forall a b, lor a b == 0 -> a == 0.
Proof.
intros a b H. bitwise as m.
apply (orb_false_iff a.[m] b.[m]).
now rewrite <- lor_spec, H, bits_0.
Qed.
Lemma lor_eq_0_iff : forall a b, lor a b == 0 <-> a == 0 /\ b == 0.
Proof.
intros a b. split.
intro H; split. now apply lor_eq_0_l in H.
rewrite lor_comm in H. now apply lor_eq_0_l in H.
intros (EQ,EQ'). now rewrite EQ, lor_0_l.
Qed.
Lemma land_0_l : forall a, land 0 a == 0.
Proof.
intros. bitwise. trivial.
Qed.
Lemma land_0_r : forall a, land a 0 == 0.
Proof.
intros. bitwise. apply andb_false_r.
Qed.
Lemma land_comm : forall a b, land a b == land b a.
Proof.
intros. bitwise. apply andb_comm.
Qed.
Lemma land_assoc :
forall a b c, land a (land b c) == land (land a b) c.
Proof.
intros. bitwise. apply andb_assoc.
Qed.
Lemma land_diag : forall a, land a a == a.
Proof.
intros. bitwise. apply andb_diag.
Qed.
Lemma ldiff_0_l : forall a, ldiff 0 a == 0.
Proof.
intros. bitwise. trivial.
Qed.
Lemma ldiff_0_r : forall a, ldiff a 0 == a.
Proof.
intros. bitwise. now rewrite andb_true_r.
Qed.
Lemma ldiff_diag : forall a, ldiff a a == 0.
Proof.
intros. bitwise. apply andb_negb_r.
Qed.
Lemma lor_land_distr_l : forall a b c,
lor (land a b) c == land (lor a c) (lor b c).
Proof.
intros. bitwise. apply orb_andb_distrib_l.
Qed.
Lemma lor_land_distr_r : forall a b c,
lor a (land b c) == land (lor a b) (lor a c).
Proof.
intros. bitwise. apply orb_andb_distrib_r.
Qed.
Lemma land_lor_distr_l : forall a b c,
land (lor a b) c == lor (land a c) (land b c).
Proof.
intros. bitwise. apply andb_orb_distrib_l.
Qed.
Lemma land_lor_distr_r : forall a b c,
land a (lor b c) == lor (land a b) (land a c).
Proof.
intros. bitwise. apply andb_orb_distrib_r.
Qed.
Lemma ldiff_ldiff_l : forall a b c,
ldiff (ldiff a b) c == ldiff a (lor b c).
Proof.
intros. bitwise. now rewrite negb_orb, andb_assoc.
Qed.
Lemma lor_ldiff_and : forall a b,
lor (ldiff a b) (land a b) == a.
Proof.
intros. bitwise.
now rewrite <- andb_orb_distrib_r, orb_comm, orb_negb_r, andb_true_r.
Qed.
Lemma land_ldiff : forall a b,
land (ldiff a b) b == 0.
Proof.
intros. bitwise.
now rewrite <-andb_assoc, (andb_comm (negb _)), andb_negb_r, andb_false_r.
Qed.
(** Properties of [setbit] and [clearbit] *)
Definition setbit a n := lor a (1<<n).
Definition clearbit a n := ldiff a (1<<n).
Lemma setbit_spec' : forall a n, setbit a n == lor a (2^n).
Proof.
intros. unfold setbit. now rewrite shiftl_1_l.
Qed.
Lemma clearbit_spec' : forall a n, clearbit a n == ldiff a (2^n).
Proof.
intros. unfold clearbit. now rewrite shiftl_1_l.
Qed.
Instance setbit_wd : Proper (eq==>eq==>eq) setbit.
Proof. unfold setbit. solve_proper. Qed.
Instance clearbit_wd : Proper (eq==>eq==>eq) clearbit.
Proof. unfold clearbit. solve_proper. Qed.
Lemma pow2_bits_true : forall n, (2^n).[n] = true.
Proof.
intros n. rewrite <- (mul_1_l (2^n)). rewrite <- (add_0_l n) at 2.
now rewrite mul_pow2_bits_add, bit0_odd, odd_1.
Qed.
Lemma pow2_bits_false : forall n m, n~=m -> (2^n).[m] = false.
Proof.
intros n m ?.
rewrite <- (mul_1_l (2^n)).
destruct (le_gt_cases n m).
rewrite mul_pow2_bits_high; trivial.
rewrite <- (succ_pred (m-n)) by (apply sub_gt; order).
now rewrite <- div2_bits, div_small, bits_0 by order'.
rewrite mul_pow2_bits_low; trivial.
Qed.
Lemma pow2_bits_eqb : forall n m, (2^n).[m] = eqb n m.
Proof.
intros n m. apply eq_true_iff_eq. rewrite eqb_eq. split.
destruct (eq_decidable n m) as [H|H]. trivial.
now rewrite (pow2_bits_false _ _ H).
intros EQ. rewrite EQ. apply pow2_bits_true.
Qed.
Lemma setbit_eqb : forall a n m,
(setbit a n).[m] = eqb n m || a.[m].
Proof.
intros. now rewrite setbit_spec', lor_spec, pow2_bits_eqb, orb_comm.
Qed.
Lemma setbit_iff : forall a n m,
(setbit a n).[m] = true <-> n==m \/ a.[m] = true.
Proof.
intros. now rewrite setbit_eqb, orb_true_iff, eqb_eq.
Qed.
Lemma setbit_eq : forall a n, (setbit a n).[n] = true.
Proof.
intros. apply setbit_iff. now left.
Qed.
Lemma setbit_neq : forall a n m, n~=m ->
(setbit a n).[m] = a.[m].
Proof.
intros a n m H. rewrite setbit_eqb.
rewrite <- eqb_eq in H. apply not_true_is_false in H. now rewrite H.
Qed.
Lemma clearbit_eqb : forall a n m,
(clearbit a n).[m] = a.[m] && negb (eqb n m).
Proof.
intros. now rewrite clearbit_spec', ldiff_spec, pow2_bits_eqb.
Qed.
Lemma clearbit_iff : forall a n m,
(clearbit a n).[m] = true <-> a.[m] = true /\ n~=m.
Proof.
intros. rewrite clearbit_eqb, andb_true_iff, <- eqb_eq.
now rewrite negb_true_iff, not_true_iff_false.
Qed.
Lemma clearbit_eq : forall a n, (clearbit a n).[n] = false.
Proof.
intros a n. rewrite clearbit_eqb, (proj2 (eqb_eq _ _) (eq_refl n)).
apply andb_false_r.
Qed.
Lemma clearbit_neq : forall a n m, n~=m ->
(clearbit a n).[m] = a.[m].
Proof.
intros a n m H. rewrite clearbit_eqb.
rewrite <- eqb_eq in H. apply not_true_is_false in H. rewrite H.
apply andb_true_r.
Qed.
(** Shifts of bitwise operations *)
Lemma shiftl_lxor : forall a b n,
(lxor a b) << n == lxor (a << n) (b << n).
Proof.
intros a b n. bitwise as m.
destruct (le_gt_cases n m).
now rewrite !shiftl_spec_high', lxor_spec.
now rewrite !shiftl_spec_low.
Qed.
Lemma shiftr_lxor : forall a b n,
(lxor a b) >> n == lxor (a >> n) (b >> n).
Proof.
intros. bitwise. now rewrite !shiftr_spec', lxor_spec.
Qed.
Lemma shiftl_land : forall a b n,
(land a b) << n == land (a << n) (b << n).
Proof.
intros a b n. bitwise as m.
destruct (le_gt_cases n m).
now rewrite !shiftl_spec_high', land_spec.
now rewrite !shiftl_spec_low.
Qed.
Lemma shiftr_land : forall a b n,
(land a b) >> n == land (a >> n) (b >> n).
Proof.
intros. bitwise. now rewrite !shiftr_spec', land_spec.
Qed.
Lemma shiftl_lor : forall a b n,
(lor a b) << n == lor (a << n) (b << n).
Proof.
intros a b n. bitwise as m.
destruct (le_gt_cases n m).
now rewrite !shiftl_spec_high', lor_spec.
now rewrite !shiftl_spec_low.
Qed.
Lemma shiftr_lor : forall a b n,
(lor a b) >> n == lor (a >> n) (b >> n).
Proof.
intros. bitwise. now rewrite !shiftr_spec', lor_spec.
Qed.
Lemma shiftl_ldiff : forall a b n,
(ldiff a b) << n == ldiff (a << n) (b << n).
Proof.
intros a b n. bitwise as m.
destruct (le_gt_cases n m).
now rewrite !shiftl_spec_high', ldiff_spec.
now rewrite !shiftl_spec_low.
Qed.
Lemma shiftr_ldiff : forall a b n,
(ldiff a b) >> n == ldiff (a >> n) (b >> n).
Proof.
intros. bitwise. now rewrite !shiftr_spec', ldiff_spec.
Qed.
(** We cannot have a function complementing all bits of a number,
otherwise it would have an infinity of bit 1. Nonetheless,
we can design a bounded complement *)
Definition ones n := P (1 << n).
Definition lnot a n := lxor a (ones n).
Instance ones_wd : Proper (eq==>eq) ones.
Proof. unfold ones. solve_proper. Qed.
Instance lnot_wd : Proper (eq==>eq==>eq) lnot.
Proof. unfold lnot. solve_proper. Qed.
Lemma ones_equiv : forall n, ones n == P (2^n).
Proof.
intros; unfold ones; now rewrite shiftl_1_l.
Qed.
Lemma ones_add : forall n m, ones (m+n) == 2^m * ones n + ones m.
Proof.
intros n m. rewrite !ones_equiv.
rewrite <- !sub_1_r, mul_sub_distr_l, mul_1_r, <- pow_add_r.
rewrite add_sub_assoc, sub_add. reflexivity.
apply pow_le_mono_r. order'.
rewrite <- (add_0_r m) at 1. apply add_le_mono_l, le_0_l.
rewrite <- (pow_0_r 2). apply pow_le_mono_r. order'. apply le_0_l.
Qed.
Lemma ones_div_pow2 : forall n m, m<=n -> ones n / 2^m == ones (n-m).
Proof.
intros n m H. symmetry. apply div_unique with (ones m).
rewrite ones_equiv.
apply le_succ_l. rewrite succ_pred; order_nz.
rewrite <- (sub_add m n H) at 1. rewrite (add_comm _ m).
apply ones_add.
Qed.
Lemma ones_mod_pow2 : forall n m, m<=n -> (ones n) mod (2^m) == ones m.
Proof.
intros n m H. symmetry. apply mod_unique with (ones (n-m)).
rewrite ones_equiv.
apply le_succ_l. rewrite succ_pred; order_nz.
rewrite <- (sub_add m n H) at 1. rewrite (add_comm _ m).
apply ones_add.
Qed.
Lemma ones_spec_low : forall n m, m<n -> (ones n).[m] = true.
Proof.
intros. apply testbit_true. rewrite ones_div_pow2 by order.
rewrite <- (pow_1_r 2). rewrite ones_mod_pow2.
rewrite ones_equiv. now nzsimpl'.
apply le_add_le_sub_r. nzsimpl. now apply le_succ_l.
Qed.
Lemma ones_spec_high : forall n m, n<=m -> (ones n).[m] = false.
Proof.
intros n m ?.
destruct (eq_0_gt_0_cases n) as [EQ|LT]; rewrite ones_equiv.
now rewrite EQ, pow_0_r, one_succ, pred_succ, bits_0.
apply bits_above_log2.
rewrite log2_pred_pow2; trivial. rewrite <-le_succ_l, succ_pred; order.
Qed.
Lemma ones_spec_iff : forall n m, (ones n).[m] = true <-> m<n.
Proof.
intros. split. intros H.
apply lt_nge. intro H'. apply ones_spec_high in H'.
rewrite H in H'; discriminate.
apply ones_spec_low.
Qed.
Lemma lnot_spec_low : forall a n m, m<n ->
(lnot a n).[m] = negb a.[m].
Proof.
intros. unfold lnot. now rewrite lxor_spec, ones_spec_low.
Qed.
Lemma lnot_spec_high : forall a n m, n<=m ->
(lnot a n).[m] = a.[m].
Proof.
intros. unfold lnot. now rewrite lxor_spec, ones_spec_high, xorb_false_r.
Qed.
Lemma lnot_involutive : forall a n, lnot (lnot a n) n == a.
Proof.
intros a n. bitwise as m.
destruct (le_gt_cases n m).
now rewrite 2 lnot_spec_high.
now rewrite 2 lnot_spec_low, negb_involutive.
Qed.
Lemma lnot_0_l : forall n, lnot 0 n == ones n.
Proof.
intros. unfold lnot. apply lxor_0_l.
Qed.
Lemma lnot_ones : forall n, lnot (ones n) n == 0.
Proof.
intros. unfold lnot. apply lxor_nilpotent.
Qed.
(** Bounded complement and other operations *)
Lemma lor_ones_low : forall a n, log2 a < n ->
lor a (ones n) == ones n.
Proof.
intros a n H. bitwise as m. destruct (le_gt_cases n m).
rewrite ones_spec_high, bits_above_log2; trivial.
now apply lt_le_trans with n.
now rewrite ones_spec_low, orb_true_r.
Qed.
Lemma land_ones : forall a n, land a (ones n) == a mod 2^n.
Proof.
intros a n. bitwise as m. destruct (le_gt_cases n m).
now rewrite ones_spec_high, mod_pow2_bits_high, andb_false_r.
now rewrite ones_spec_low, mod_pow2_bits_low, andb_true_r.
Qed.
Lemma land_ones_low : forall a n, log2 a < n ->
land a (ones n) == a.
Proof.
intros; rewrite land_ones. apply mod_small.
apply log2_lt_cancel. rewrite log2_pow2; trivial using le_0_l.
Qed.
Lemma ldiff_ones_r : forall a n,
ldiff a (ones n) == (a >> n) << n.
Proof.
intros a n. bitwise as m. destruct (le_gt_cases n m).
rewrite ones_spec_high, shiftl_spec_high', shiftr_spec'; trivial.
rewrite sub_add; trivial. apply andb_true_r.
now rewrite ones_spec_low, shiftl_spec_low, andb_false_r.
Qed.
Lemma ldiff_ones_r_low : forall a n, log2 a < n ->
ldiff a (ones n) == 0.
Proof.
intros a n H. bitwise as m. destruct (le_gt_cases n m).
rewrite ones_spec_high, bits_above_log2; trivial.
now apply lt_le_trans with n.
now rewrite ones_spec_low, andb_false_r.
Qed.
Lemma ldiff_ones_l_low : forall a n, log2 a < n ->
ldiff (ones n) a == lnot a n.
Proof.
intros a n H. bitwise as m. destruct (le_gt_cases n m).
rewrite ones_spec_high, lnot_spec_high, bits_above_log2; trivial.
now apply lt_le_trans with n.
now rewrite ones_spec_low, lnot_spec_low.
Qed.
Lemma lor_lnot_diag : forall a n,
lor a (lnot a n) == lor a (ones n).
Proof.
intros a n. bitwise as m.
destruct (le_gt_cases n m).
rewrite lnot_spec_high, ones_spec_high; trivial. now destruct a.[m].
rewrite lnot_spec_low, ones_spec_low; trivial. now destruct a.[m].
Qed.
Lemma lor_lnot_diag_low : forall a n, log2 a < n ->
lor a (lnot a n) == ones n.
Proof.
intros a n H. now rewrite lor_lnot_diag, lor_ones_low.
Qed.
Lemma land_lnot_diag : forall a n,
land a (lnot a n) == ldiff a (ones n).
Proof.
intros a n. bitwise as m.
destruct (le_gt_cases n m).
rewrite lnot_spec_high, ones_spec_high; trivial. now destruct a.[m].
rewrite lnot_spec_low, ones_spec_low; trivial. now destruct a.[m].
Qed.
Lemma land_lnot_diag_low : forall a n, log2 a < n ->
land a (lnot a n) == 0.
Proof.
intros. now rewrite land_lnot_diag, ldiff_ones_r_low.
Qed.
Lemma lnot_lor_low : forall a b n, log2 a < n -> log2 b < n ->
lnot (lor a b) n == land (lnot a n) (lnot b n).
Proof.
intros a b n Ha Hb. bitwise as m. destruct (le_gt_cases n m).
rewrite !lnot_spec_high, lor_spec, !bits_above_log2; trivial.
now apply lt_le_trans with n.
now apply lt_le_trans with n.
now rewrite !lnot_spec_low, lor_spec, negb_orb.
Qed.
Lemma lnot_land_low : forall a b n, log2 a < n -> log2 b < n ->
lnot (land a b) n == lor (lnot a n) (lnot b n).
Proof.
intros a b n Ha Hb. bitwise as m. destruct (le_gt_cases n m).
rewrite !lnot_spec_high, land_spec, !bits_above_log2; trivial.
now apply lt_le_trans with n.
now apply lt_le_trans with n.
now rewrite !lnot_spec_low, land_spec, negb_andb.
Qed.
Lemma ldiff_land_low : forall a b n, log2 a < n ->
ldiff a b == land a (lnot b n).
Proof.
intros a b n Ha. bitwise as m. destruct (le_gt_cases n m).
rewrite (bits_above_log2 a m). trivial.
now apply lt_le_trans with n.
rewrite !lnot_spec_low; trivial.
Qed.
Lemma lnot_ldiff_low : forall a b n, log2 a < n -> log2 b < n ->
lnot (ldiff a b) n == lor (lnot a n) b.
Proof.
intros a b n Ha Hb. bitwise as m. destruct (le_gt_cases n m).
rewrite !lnot_spec_high, ldiff_spec, !bits_above_log2; trivial.
now apply lt_le_trans with n.
now apply lt_le_trans with n.
now rewrite !lnot_spec_low, ldiff_spec, negb_andb, negb_involutive.
Qed.
Lemma lxor_lnot_lnot : forall a b n,
lxor (lnot a n) (lnot b n) == lxor a b.
Proof.
intros a b n. bitwise as m. destruct (le_gt_cases n m).
rewrite !lnot_spec_high; trivial.
rewrite !lnot_spec_low, xorb_negb_negb; trivial.
Qed.
Lemma lnot_lxor_l : forall a b n,
lnot (lxor a b) n == lxor (lnot a n) b.
Proof.
intros a b n. bitwise as m. destruct (le_gt_cases n m).
rewrite !lnot_spec_high, lxor_spec; trivial.
rewrite !lnot_spec_low, lxor_spec, negb_xorb_l; trivial.
Qed.
Lemma lnot_lxor_r : forall a b n,
lnot (lxor a b) n == lxor a (lnot b n).
Proof.
intros a b n. bitwise as m. destruct (le_gt_cases n m).
rewrite !lnot_spec_high, lxor_spec; trivial.
rewrite !lnot_spec_low, lxor_spec, negb_xorb_r; trivial.
Qed.
Lemma lxor_lor : forall a b, land a b == 0 ->
lxor a b == lor a b.
Proof.
intros a b H. bitwise as m.
assert (a.[m] && b.[m] = false)
by now rewrite <- land_spec, H, bits_0.
now destruct a.[m], b.[m].
Qed.
(** Bitwise operations and log2 *)
Lemma log2_bits_unique : forall a n,
a.[n] = true ->
(forall m, n<m -> a.[m] = false) ->
log2 a == n.
Proof.
intros a n H H'.
destruct (eq_0_gt_0_cases a) as [Ha|Ha].
now rewrite Ha, bits_0 in H.
apply le_antisymm; apply le_ngt; intros LT.
specialize (H' _ LT). now rewrite bit_log2 in H' by order.
now rewrite bits_above_log2 in H by order.
Qed.
Lemma log2_shiftr : forall a n, log2 (a >> n) == log2 a - n.
Proof.
intros a n.
destruct (eq_0_gt_0_cases a) as [Ha|Ha].
now rewrite Ha, shiftr_0_l, log2_nonpos, sub_0_l by order.
destruct (lt_ge_cases (log2 a) n).
rewrite shiftr_eq_0, log2_nonpos by order.
symmetry. rewrite sub_0_le; order.
apply log2_bits_unique.
now rewrite shiftr_spec', sub_add, bit_log2 by order.
intros m Hm.
rewrite shiftr_spec'; trivial. apply bits_above_log2; try order.
now apply lt_sub_lt_add_r.
Qed.
Lemma log2_shiftl : forall a n, a~=0 -> log2 (a << n) == log2 a + n.
Proof.
intros a n Ha.
rewrite shiftl_mul_pow2, add_comm by trivial.
apply log2_mul_pow2. generalize (le_0_l a); order. apply le_0_l.
Qed.
Lemma log2_lor : forall a b,
log2 (lor a b) == max (log2 a) (log2 b).
Proof.
assert (AUX : forall a b, a<=b -> log2 (lor a b) == log2 b).
intros a b H.
destruct (eq_0_gt_0_cases a) as [Ha|Ha]. now rewrite Ha, lor_0_l.
apply log2_bits_unique.
now rewrite lor_spec, bit_log2, orb_true_r by order.
intros m Hm. assert (H' := log2_le_mono _ _ H).
now rewrite lor_spec, 2 bits_above_log2 by order.
(* main *)
intros a b. destruct (le_ge_cases a b) as [H|H].
rewrite max_r by now apply log2_le_mono.
now apply AUX.
rewrite max_l by now apply log2_le_mono.
rewrite lor_comm. now apply AUX.
Qed.
Lemma log2_land : forall a b,
log2 (land a b) <= min (log2 a) (log2 b).
Proof.
assert (AUX : forall a b, a<=b -> log2 (land a b) <= log2 a).
intros a b H.
apply le_ngt. intros H'.
destruct (eq_decidable (land a b) 0) as [EQ|NEQ].
rewrite EQ in H'. apply log2_lt_cancel in H'. generalize (le_0_l a); order.
generalize (bit_log2 (land a b) NEQ).
now rewrite land_spec, bits_above_log2.
(* main *)
intros a b.
destruct (le_ge_cases a b) as [H|H].
rewrite min_l by now apply log2_le_mono. now apply AUX.
rewrite min_r by now apply log2_le_mono. rewrite land_comm. now apply AUX.
Qed.
Lemma log2_lxor : forall a b,
log2 (lxor a b) <= max (log2 a) (log2 b).
Proof.
assert (AUX : forall a b, a<=b -> log2 (lxor a b) <= log2 b).
intros a b H.
apply le_ngt. intros H'.
destruct (eq_decidable (lxor a b) 0) as [EQ|NEQ].
rewrite EQ in H'. apply log2_lt_cancel in H'. generalize (le_0_l a); order.
generalize (bit_log2 (lxor a b) NEQ).
rewrite lxor_spec, 2 bits_above_log2; try order. discriminate.
apply le_lt_trans with (log2 b); trivial. now apply log2_le_mono.
(* main *)
intros a b.
destruct (le_ge_cases a b) as [H|H].
rewrite max_r by now apply log2_le_mono. now apply AUX.
rewrite max_l by now apply log2_le_mono. rewrite lxor_comm. now apply AUX.
Qed.
(** Bitwise operations and arithmetical operations *)
Local Notation xor3 a b c := (xorb (xorb a b) c).
Local Notation lxor3 a b c := (lxor (lxor a b) c).
Local Notation nextcarry a b c := ((a&&b) || (c && (a||b))).
Local Notation lnextcarry a b c := (lor (land a b) (land c (lor a b))).
Lemma add_bit0 : forall a b, (a+b).[0] = xorb a.[0] b.[0].
Proof.
intros. now rewrite !bit0_odd, odd_add.
Qed.
Lemma add3_bit0 : forall a b c,
(a+b+c).[0] = xor3 a.[0] b.[0] c.[0].
Proof.
intros. now rewrite !add_bit0.
Qed.
Lemma add3_bits_div2 : forall (a0 b0 c0 : bool),
(a0 + b0 + c0)/2 == nextcarry a0 b0 c0.
Proof.
assert (H : 1+1 == 2) by now nzsimpl'.
intros [|] [|] [|]; simpl; rewrite ?add_0_l, ?add_0_r, ?H;
(apply div_same; order') || (apply div_small; order') || idtac.
symmetry. apply div_unique with 1. order'. now nzsimpl'.
Qed.
Lemma add_carry_div2 : forall a b (c0:bool),
(a + b + c0)/2 == a/2 + b/2 + nextcarry a.[0] b.[0] c0.
Proof.
intros a b c0.
rewrite <- add3_bits_div2.
rewrite (add_comm ((a/2)+_)).
rewrite <- div_add by order'.
f_equiv.
rewrite <- !div2_div, mul_comm, mul_add_distr_l.
rewrite (div2_odd a), <- bit0_odd at 1. fold (b2n a.[0]).
rewrite (div2_odd b), <- bit0_odd at 1. fold (b2n b.[0]).
rewrite add_shuffle1.
rewrite <-(add_assoc _ _ c0). apply add_comm.
Qed.
(** The main result concerning addition: we express the bits of the sum
in term of bits of [a] and [b] and of some carry stream which is also
recursively determined by another equation.
*)
Lemma add_carry_bits : forall a b (c0:bool), exists c,
a+b+c0 == lxor3 a b c /\ c/2 == lnextcarry a b c /\ c.[0] = c0.
Proof.
intros a b c0.
(* induction over some n such that [a<2^n] and [b<2^n] *)
set (n:=max a b).
assert (Ha : a<2^n).
apply lt_le_trans with (2^a). apply pow_gt_lin_r, lt_1_2.
apply pow_le_mono_r. order'. unfold n.
destruct (le_ge_cases a b); [rewrite max_r|rewrite max_l]; order'.
assert (Hb : b<2^n).
apply lt_le_trans with (2^b). apply pow_gt_lin_r, lt_1_2.
apply pow_le_mono_r. order'. unfold n.
destruct (le_ge_cases a b); [rewrite max_r|rewrite max_l]; order'.
clearbody n.
revert a b c0 Ha Hb. induct n.
(*base*)
intros a b c0. rewrite !pow_0_r, !one_succ, !lt_succ_r. intros Ha Hb.
exists c0.
setoid_replace a with 0 by (generalize (le_0_l a); order').
setoid_replace b with 0 by (generalize (le_0_l b); order').
rewrite !add_0_l, !lxor_0_l, !lor_0_r, !land_0_r, !lor_0_r.
rewrite b2n_div2, b2n_bit0; now repeat split.
(*step*)
intros n IH a b c0 Ha Hb.
set (c1:=nextcarry a.[0] b.[0] c0).
destruct (IH (a/2) (b/2) c1) as (c & IH1 & IH2 & Hc); clear IH.
apply div_lt_upper_bound; trivial. order'. now rewrite <- pow_succ_r'.
apply div_lt_upper_bound; trivial. order'. now rewrite <- pow_succ_r'.
exists (c0 + 2*c). repeat split.
(* - add *)
bitwise as m.
destruct (zero_or_succ m) as [EQ|[m' EQ]]; rewrite EQ; clear EQ.
now rewrite add_b2n_double_bit0, add3_bit0, b2n_bit0.
rewrite <- !div2_bits, <- 2 lxor_spec.
f_equiv.
rewrite add_b2n_double_div2, <- IH1. apply add_carry_div2.
(* - carry *)
rewrite add_b2n_double_div2.
bitwise as m.
destruct (zero_or_succ m) as [EQ|[m' EQ]]; rewrite EQ; clear EQ.
now rewrite add_b2n_double_bit0.
rewrite <- !div2_bits, IH2. autorewrite with bitwise.
now rewrite add_b2n_double_div2.
(* - carry0 *)
apply add_b2n_double_bit0.
Qed.
(** Particular case : the second bit of an addition *)
Lemma add_bit1 : forall a b,
(a+b).[1] = xor3 a.[1] b.[1] (a.[0] && b.[0]).
Proof.
intros a b.
destruct (add_carry_bits a b false) as (c & EQ1 & EQ2 & Hc).
simpl in EQ1; rewrite add_0_r in EQ1. rewrite EQ1.
autorewrite with bitwise. f_equal.
rewrite one_succ, <- div2_bits, EQ2.
autorewrite with bitwise.
rewrite Hc. simpl. apply orb_false_r.
Qed.
(** In an addition, there will be no carries iff there is
no common bits in the numbers to add *)
Lemma nocarry_equiv : forall a b c,
c/2 == lnextcarry a b c -> c.[0] = false ->
(c == 0 <-> land a b == 0).
Proof.
intros a b c H H'.
split. intros EQ; rewrite EQ in *.
rewrite div_0_l in H by order'.
symmetry in H. now apply lor_eq_0_l in H.
intros EQ. rewrite EQ, lor_0_l in H.
apply bits_inj_0.
intro n; induct n. trivial.
intros n IH.
rewrite <- div2_bits, H.
autorewrite with bitwise.
now rewrite IH.
Qed.
(** When there is no common bits, the addition is just a xor *)
Lemma add_nocarry_lxor : forall a b, land a b == 0 ->
a+b == lxor a b.
Proof.
intros a b H.
destruct (add_carry_bits a b false) as (c & EQ1 & EQ2 & Hc).
simpl in EQ1; rewrite add_0_r in EQ1. rewrite EQ1.
apply (nocarry_equiv a b c) in H; trivial.
rewrite H. now rewrite lxor_0_r.
Qed.
(** A null [ldiff] implies being smaller *)
Lemma ldiff_le : forall a b, ldiff a b == 0 -> a <= b.
Proof.
cut (forall n a b, a < 2^n -> ldiff a b == 0 -> a <= b).
intros H a b. apply (H a), pow_gt_lin_r; order'.
intro n; induct n.
intros a b Ha _. rewrite pow_0_r, one_succ, lt_succ_r in Ha.
assert (Ha' : a == 0) by (generalize (le_0_l a); order').
rewrite Ha'. apply le_0_l.
intros n IH a b Ha H.
assert (NEQ : 2 ~= 0) by order'.
rewrite (div_mod a 2 NEQ), (div_mod b 2 NEQ).
apply add_le_mono.
apply mul_le_mono_l.
apply IH.
apply div_lt_upper_bound; trivial. now rewrite <- pow_succ_r'.
rewrite <- (pow_1_r 2), <- 2 shiftr_div_pow2.
now rewrite <- shiftr_ldiff, H, shiftr_div_pow2, pow_1_r, div_0_l.
rewrite <- 2 bit0_mod.
apply bits_inj_iff in H. specialize (H 0).
rewrite ldiff_spec, bits_0 in H.
destruct a.[0], b.[0]; try discriminate; simpl; order'.
Qed.
(** Subtraction can be a ldiff when the opposite ldiff is null. *)
Lemma sub_nocarry_ldiff : forall a b, ldiff b a == 0 ->
a-b == ldiff a b.
Proof.
intros a b H.
apply add_cancel_r with b.
rewrite sub_add.
symmetry.
rewrite add_nocarry_lxor.
bitwise as m.
apply bits_inj_iff in H. specialize (H m).
rewrite ldiff_spec, bits_0 in H.
now destruct a.[m], b.[m].
apply land_ldiff.
now apply ldiff_le.
Qed.
(** We can express lnot in term of subtraction *)
Lemma add_lnot_diag_low : forall a n, log2 a < n ->
a + lnot a n == ones n.
Proof.
intros a n H.
assert (H' := land_lnot_diag_low a n H).
rewrite add_nocarry_lxor, lxor_lor by trivial.
now apply lor_lnot_diag_low.
Qed.
Lemma lnot_sub_low : forall a n, log2 a < n ->
lnot a n == ones n - a.
Proof.
intros a n H.
now rewrite <- (add_lnot_diag_low a n H), add_comm, add_sub.
Qed.
(** Adding numbers with no common bits cannot lead to a much bigger number *)
Lemma add_nocarry_lt_pow2 : forall a b n, land a b == 0 ->
a < 2^n -> b < 2^n -> a+b < 2^n.
Proof.
intros a b n H Ha Hb.
rewrite add_nocarry_lxor by trivial.
apply div_small_iff. order_nz.
rewrite <- shiftr_div_pow2, shiftr_lxor, !shiftr_div_pow2.
rewrite 2 div_small by trivial.
apply lxor_0_l.
Qed.
Lemma add_nocarry_mod_lt_pow2 : forall a b n, land a b == 0 ->
a mod 2^n + b mod 2^n < 2^n.
Proof.
intros a b n H.
apply add_nocarry_lt_pow2.
bitwise as m.
destruct (le_gt_cases n m).
now rewrite mod_pow2_bits_high.
now rewrite !mod_pow2_bits_low, <- land_spec, H, bits_0.
apply mod_upper_bound; order_nz.
apply mod_upper_bound; order_nz.
Qed.
End NBitsProp.
|
/*
* This program tests the synthesis of small memories, including
* aysnchronous read w/ synchronous write.
*/
module main;
reg [1:0] mem;
reg D;
reg rst, clk, wr, wadr, radr;
/*
* This implements the synchronous write port to the memory.
* Asynchronous reset? In this case, yes, even though that is
* not normally the case for RAM devices.
*/
(* ivl_synthesis_on *)
always @(posedge clk or posedge rst)
if (rst) begin
mem[0] <= 0;
mem[1] <= 0;
end else if (wr) begin
mem[wadr] <= D;
end else begin
end
/* This is the asynchronous read port from the memory. */
wire Q = mem[radr];
(* ivl_synthesis_off *)
initial begin
rst = 0;
clk = 0;
wadr = 0;
radr = 0;
wr = 0;
#1 clk = 1;
#1 clk = 0;
// Make sure reset works.
rst = 1;
#1 if (mem[0] !== 0 || mem[1] !== 0) begin
$display("FAILED -- Reset: mem[0]=%b, mem[1]=%b", mem[0], mem[1]);
$finish;
end
radr = 0;
#1 if (Q !== mem[radr]) begin
$display("FAILED -- mem[%b] = %b, Q=%b", radr, mem[radr], Q);
$finish;
end
radr = 1;
#1 if (Q !== mem[radr]) begin
$display("FAILED -- mem[%b] = %b, Q=%b", radr, mem[radr], Q);
$finish;
end
rst = 0;
#1 clk = 1;
#1 clk = 0;
// Make sure memory remembers value.
if (mem[0] !== 0 || mem[1] !== 0) begin
$display("FAILED -- Reset: mem[0]=%b, mem[1]=%b", mem[0], mem[1]);
$finish;
end
D = 1;
wr = 1;
#1 clk = 1;
#1 clk = 0;
// Make sure write works.
if (mem[0] !== 1 || mem[1] !== 0) begin
$display("FAILED -- write D=%b: mem[0]=%b, mem[1]=%b",
D, mem[0], mem[1]);
$finish;
end
D = 0;
wadr = 1;
#1 clk = 1;
#1 clk = 0;
// Make sure write works.
if (mem[0] !== 1 || mem[1] !== 0) begin
$display("FAILED -- write D=%b: mem[0]=%b, mem[1]=%b",
D, mem[0], mem[1]);
$finish;
end
radr = 0;
#1 if (Q !== mem[radr]) begin
$display("FAILED -- mem[%b] = %b, Q=%b", radr, mem[radr], Q);
$finish;
end
wr = 0;
D = 1;
// Make sure memory remembers written values.
if (mem[0] !== 1 || mem[1] !== 0) begin
$display("FAILED -- write D=%b: mem[0]=%b, mem[1]=%b",
D, mem[0], mem[1]);
$finish;
end
$display("PASSED");
$finish;
end
endmodule // main
|
module taxi_top (reset, pulse, clk,
price_seg1, price_seg2, price_seg3,
wait_time_seg1, wait_time_seg2,
mileage_seg1, mileage_seg2, mileage_seg3);
input reset;
input pulse,clk;
output [6:0] price_seg1, price_seg2, price_seg3,
wait_time_seg1, wait_time_seg2,
mileage_seg1, mileage_seg2, mileage_seg3;
//8 segments
wire [15:0] wait_time_BCD; //decimal values in BCD
wire [15:0] price_BCD;
wire [15:0] mileage_BCD;
wire [11:0] price;
wire [11:0] wait_time; //binary
wire [11:0] mileage;
wire clk_1;
wire clk_10000;
wire [11:0] number_of_halfkm;
wire work;
BCD_decode BCD_inst1(
.binary(wait_time),
.bcd(wait_time_BCD)
);
BCD_decode BCD_inst2(
.binary(price),
.bcd(price_BCD)
);
BCD_decode BCD_inst3(
.binary(mileage),
.bcd(mileage_BCD)
);
clk_1Hz M1(
.clk(clk),
.clk_1(clk_1)
);
clk_10000Hz M2(
.clk(clk),
.clk_10000(clk_10000)
);
round_counter_module rcm1(
.reset(reset),
.work(work),
.pulse(pulse),
.mileage(mileage),
.clk(clk_10000),
.number_of_halfkm(number_of_halfkm),
.clk_1(clk_1)
);
price_module price_inst(
.reset(reset),
.wait_time(wait_time),
.number_of_halfkm(number_of_halfkm),
.price(price)
);
wait_time_module wt(
.reset(reset),
.work(work),
.clk(clk_1),
.wait_time(wait_time)
);
decode hex1 (.data(price_BCD [3:0]),.hex(price_seg1));
decode hex2 (.data(price_BCD [7:4]),.hex(price_seg2));
decode hex3 (.data(price_BCD [11:8]),.hex(price_seg3));
decode hex4 (.data(mileage_BCD [3:0]),.hex(mileage_seg1));
decode hex5 (.data(mileage_BCD [7:4]),.hex(mileage_seg2));
decode hex6 (.data(mileage_BCD [11:8]),.hex(mileage_seg3));
decode hex7 (.data(wait_time_BCD [3:0]),.hex(wait_time_seg1));
decode hex8 (.data(wait_time_BCD [7:4]),.hex(wait_time_seg2));
endmodule
/*
LED dispay descriptions
left wait_time
middle mileage
right price
*/
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A21OI_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__A21OI_PP_BLACKBOX_V
/**
* a21oi: 2-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2) | B1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__a21oi (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A21OI_PP_BLACKBOX_V
|
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <[email protected]>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* ---
*
* The internal logic cell technology mapper.
*
* This verilog library contains the mapping of internal cells (e.g. $not with
* variable bit width) to the internal logic cells (such as the single bit $_INV_
* gate). Usually this logic network is then mapped to the actual technology
* using e.g. the "abc" pass.
*
* Note that this library does not map $mem cells. They must be mapped to logic
* and $dff cells using the "memory_map" pass first. (Or map it to custom cells,
* which is of course highly recommended for larger memories.)
*
*/
// --------------------------------------------------------
(* techmap_simplemap *)
module \$not ;
endmodule
// --------------------------------------------------------
(* techmap_simplemap *)
module \$pos ;
endmodule
// --------------------------------------------------------
(* techmap_simplemap *)
module \$bu0 ;
endmodule
// --------------------------------------------------------
module \$neg (A, Y);
parameter A_SIGNED = 0;
parameter A_WIDTH = 1;
parameter Y_WIDTH = 1;
input [A_WIDTH-1:0] A;
output [Y_WIDTH-1:0] Y;
\$sub #(
.A_SIGNED(A_SIGNED),
.B_SIGNED(A_SIGNED),
.A_WIDTH(1),
.B_WIDTH(A_WIDTH),
.Y_WIDTH(Y_WIDTH)
) sub (
.A(1'b0),
.B(A),
.Y(Y)
);
endmodule
// --------------------------------------------------------
(* techmap_simplemap *)
module \$and ;
endmodule
// --------------------------------------------------------
(* techmap_simplemap *)
module \$or ;
endmodule
// --------------------------------------------------------
(* techmap_simplemap *)
module \$xor ;
endmodule
// --------------------------------------------------------
(* techmap_simplemap *)
module \$xnor ;
endmodule
// --------------------------------------------------------
(* techmap_simplemap *)
module \$reduce_and ;
endmodule
// --------------------------------------------------------
(* techmap_simplemap *)
module \$reduce_or ;
endmodule
// --------------------------------------------------------
(* techmap_simplemap *)
module \$reduce_xor ;
endmodule
// --------------------------------------------------------
(* techmap_simplemap *)
module \$reduce_xnor ;
endmodule
// --------------------------------------------------------
(* techmap_simplemap *)
module \$reduce_bool ;
endmodule
// --------------------------------------------------------
module \$__shift (X, A, Y);
parameter WIDTH = 1;
parameter SHIFT = 0;
input X;
input [WIDTH-1:0] A;
output [WIDTH-1:0] Y;
genvar i;
generate
for (i = 0; i < WIDTH; i = i + 1) begin:V
if (i+SHIFT < 0) begin
assign Y[i] = 0;
end else
if (i+SHIFT < WIDTH) begin
assign Y[i] = A[i+SHIFT];
end else begin
assign Y[i] = X;
end
end
endgenerate
endmodule
// --------------------------------------------------------
module \$shl (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
parameter WIDTH = Y_WIDTH;
localparam BB_WIDTH = $clog2(WIDTH) + 2 < B_WIDTH ? $clog2(WIDTH) + 2 : B_WIDTH;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
genvar i;
generate
wire [WIDTH*(BB_WIDTH+1)-1:0] chain;
\$bu0 #(
.A_SIGNED(A_SIGNED),
.A_WIDTH(A_WIDTH),
.Y_WIDTH(WIDTH)
) expand (
.A(A),
.Y(chain[WIDTH-1:0])
);
assign Y = chain[WIDTH*(BB_WIDTH+1)-1 : WIDTH*BB_WIDTH];
for (i = 0; i < BB_WIDTH; i = i + 1) begin:V
wire [WIDTH-1:0] unshifted, shifted, result;
assign unshifted = chain[WIDTH*i + WIDTH-1 : WIDTH*i];
assign chain[WIDTH*(i+1) + WIDTH-1 : WIDTH*(i+1)] = result;
wire BBIT;
if (i == BB_WIDTH-1 && BB_WIDTH < B_WIDTH)
assign BBIT = |B[B_WIDTH-1:BB_WIDTH-1];
else
assign BBIT = B[i];
\$__shift #(
.WIDTH(WIDTH),
.SHIFT(0 - (2 ** (i > 30 ? 30 : i)))
) sh (
.X(0),
.A(unshifted),
.Y(shifted)
);
\$mux #(
.WIDTH(WIDTH)
) mux (
.A(unshifted),
.B(shifted),
.Y(result),
.S(BBIT)
);
end
endgenerate
endmodule
// --------------------------------------------------------
module \$shr (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
localparam WIDTH = A_WIDTH > Y_WIDTH ? A_WIDTH : Y_WIDTH;
localparam BB_WIDTH = $clog2(WIDTH) + 2 < B_WIDTH ? $clog2(WIDTH) + 2 : B_WIDTH;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
genvar i;
generate
wire [WIDTH*(BB_WIDTH+1)-1:0] chain;
\$bu0 #(
.A_SIGNED(A_SIGNED),
.A_WIDTH(A_WIDTH),
.Y_WIDTH(WIDTH)
) expand (
.A(A),
.Y(chain[WIDTH-1:0])
);
assign Y = chain[WIDTH*(BB_WIDTH+1)-1 : WIDTH*BB_WIDTH];
for (i = 0; i < BB_WIDTH; i = i + 1) begin:V
wire [WIDTH-1:0] unshifted, shifted, result;
assign unshifted = chain[WIDTH*i + WIDTH-1 : WIDTH*i];
assign chain[WIDTH*(i+1) + WIDTH-1 : WIDTH*(i+1)] = result;
wire BBIT;
if (i == BB_WIDTH-1 && BB_WIDTH < B_WIDTH)
assign BBIT = |B[B_WIDTH-1:BB_WIDTH-1];
else
assign BBIT = B[i];
\$__shift #(
.WIDTH(WIDTH),
.SHIFT(2 ** (i > 30 ? 30 : i))
) sh (
.X(0),
.A(unshifted),
.Y(shifted)
);
\$mux #(
.WIDTH(WIDTH)
) mux (
.A(unshifted),
.B(shifted),
.Y(result),
.S(BBIT)
);
end
endgenerate
endmodule
// --------------------------------------------------------
module \$sshl (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
localparam WIDTH = Y_WIDTH;
localparam BB_WIDTH = $clog2(WIDTH) + 2 < B_WIDTH ? $clog2(WIDTH) + 2 : B_WIDTH;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
genvar i;
generate
wire [WIDTH*(BB_WIDTH+1)-1:0] chain;
\$bu0 #(
.A_SIGNED(A_SIGNED),
.A_WIDTH(A_WIDTH),
.Y_WIDTH(WIDTH)
) expand (
.A(A),
.Y(chain[WIDTH-1:0])
);
assign Y = chain[WIDTH*(BB_WIDTH+1)-1 : WIDTH*BB_WIDTH];
for (i = 0; i < BB_WIDTH; i = i + 1) begin:V
wire [WIDTH-1:0] unshifted, shifted, result;
assign unshifted = chain[WIDTH*i + WIDTH-1 : WIDTH*i];
assign chain[WIDTH*(i+1) + WIDTH-1 : WIDTH*(i+1)] = result;
wire BBIT;
if (i == BB_WIDTH-1 && BB_WIDTH < B_WIDTH)
assign BBIT = |B[B_WIDTH-1:BB_WIDTH-1];
else
assign BBIT = B[i];
\$__shift #(
.WIDTH(WIDTH),
.SHIFT(0 - (2 ** (i > 30 ? 30 : i)))
) sh (
.X(0),
.A(unshifted),
.Y(shifted)
);
\$mux #(
.WIDTH(WIDTH)
) mux (
.A(unshifted),
.B(shifted),
.Y(result),
.S(BBIT)
);
end
endgenerate
endmodule
// --------------------------------------------------------
module \$sshr (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
localparam WIDTH = A_WIDTH > Y_WIDTH ? A_WIDTH : Y_WIDTH;
localparam BB_WIDTH = $clog2(WIDTH) + 2 < B_WIDTH ? $clog2(WIDTH) + 2 : B_WIDTH;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
genvar i;
generate
wire [WIDTH*(BB_WIDTH+1)-1:0] chain;
\$bu0 #(
.A_SIGNED(A_SIGNED),
.A_WIDTH(A_WIDTH),
.Y_WIDTH(WIDTH)
) expand (
.A(A),
.Y(chain[WIDTH-1:0])
);
for (i = 0; i < Y_WIDTH; i = i + 1) begin:Y
if (i < WIDTH) begin
assign Y[i] = chain[WIDTH*BB_WIDTH + i];
end else
if (A_SIGNED) begin
assign Y[i] = chain[WIDTH*BB_WIDTH + WIDTH-1];
end else begin
assign Y[i] = 0;
end
end
for (i = 0; i < BB_WIDTH; i = i + 1) begin:V
wire [WIDTH-1:0] unshifted, shifted, result;
assign unshifted = chain[WIDTH*i + WIDTH-1 : WIDTH*i];
assign chain[WIDTH*(i+1) + WIDTH-1 : WIDTH*(i+1)] = result;
wire BBIT;
if (i == BB_WIDTH-1 && BB_WIDTH < B_WIDTH)
assign BBIT = |B[B_WIDTH-1:BB_WIDTH-1];
else
assign BBIT = B[i];
\$__shift #(
.WIDTH(WIDTH),
.SHIFT(2 ** (i > 30 ? 30 : i))
) sh (
.X(A_SIGNED && A[A_WIDTH-1]),
.A(unshifted),
.Y(shifted)
);
\$mux #(
.WIDTH(WIDTH)
) mux (
.A(unshifted),
.B(shifted),
.Y(result),
.S(BBIT)
);
end
endgenerate
endmodule
// --------------------------------------------------------
module \$__fulladd (A, B, C, X, Y);
// {X, Y} = A + B + C
input A, B, C;
output X, Y;
// {t1, t2} = A + B
wire t1, t2, t3;
//\$_AND_ gate1 ( .A(A), .B(B), .Y(t1) );
//\$_XOR_ gate2 ( .A(A), .B(B), .Y(t2) );
//\$_AND_ gate3 ( .A(t2), .B(C), .Y(t3) );
//\$_XOR_ gate4 ( .A(t2), .B(C), .Y(Y) );
//\$_OR_ gate5 ( .A(t1), .B(t3), .Y(X) );
\$_XOR_ gate1 ( .A(A), .B(C), .Y(t1) );
\$_XOR_ gate2 ( .A(B), .B(C), .Y(t2) );
\$_AND_ gate3 ( .A(t1), .B(t2), .Y(t3) );
\$_XOR_ gate4 ( .A(t1), .B(B), .Y(Y) );
\$_XOR_ gate5 ( .A(t3), .B(C), .Y(X) );
endmodule
// --------------------------------------------------------
module \$__alu (A, B, Cin, Y, Cout, Csign);
parameter WIDTH = 1;
input [WIDTH-1:0] A, B;
input Cin;
output [WIDTH-1:0] Y;
output Cout, Csign;
wire [WIDTH:0] carry;
assign carry[0] = Cin;
assign Cout = carry[WIDTH];
assign Csign = carry[WIDTH-1];
genvar i;
generate
for (i = 0; i < WIDTH; i = i + 1) begin:V
\$__fulladd adder (
.A(A[i]),
.B(B[i]),
.C(carry[i]),
.X(carry[i+1]),
.Y(Y[i])
);
end
endgenerate
endmodule
// --------------------------------------------------------
module \$lt (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
wire carry, carry_sign;
wire [WIDTH-1:0] A_buf, B_buf, Y_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
\$__alu #(
.WIDTH(WIDTH)
) alu (
.A(A_buf),
.B(~B_buf),
.Cin(1'b1),
.Y(Y_buf),
.Cout(carry),
.Csign(carry_sign)
);
// ALU flags
wire cf, of, zf, sf;
assign cf = !carry;
assign of = carry ^ carry_sign;
assign zf = ~|Y_buf;
assign sf = Y_buf[WIDTH-1];
generate
if (A_SIGNED && B_SIGNED) begin
assign Y = of != sf;
end else begin
assign Y = cf;
end
endgenerate
endmodule
// --------------------------------------------------------
module \$le (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
wire carry, carry_sign;
wire [WIDTH-1:0] A_buf, B_buf, Y_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
\$__alu #(
.WIDTH(WIDTH)
) alu (
.A(A_buf),
.B(~B_buf),
.Cin(1'b1),
.Y(Y_buf),
.Cout(carry),
.Csign(carry_sign)
);
// ALU flags
wire cf, of, zf, sf;
assign cf = !carry;
assign of = carry ^ carry_sign;
assign zf = ~|Y_buf;
assign sf = Y_buf[WIDTH-1];
generate
if (A_SIGNED && B_SIGNED) begin
assign Y = zf || (of != sf);
end else begin
assign Y = zf || cf;
end
endgenerate
endmodule
// --------------------------------------------------------
module \$eq (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
wire carry, carry_sign;
wire [WIDTH-1:0] A_buf, B_buf;
\$bu0 #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
\$bu0 #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
assign Y = ~|(A_buf ^ B_buf);
endmodule
// --------------------------------------------------------
module \$ne (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
wire carry, carry_sign;
wire [WIDTH-1:0] A_buf, B_buf;
\$bu0 #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
\$bu0 #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
assign Y = |(A_buf ^ B_buf);
endmodule
// --------------------------------------------------------
module \$eqx (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
wire carry, carry_sign;
wire [WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
assign Y = ~|(A_buf ^ B_buf);
endmodule
// --------------------------------------------------------
module \$nex (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
wire carry, carry_sign;
wire [WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
assign Y = |(A_buf ^ B_buf);
endmodule
// --------------------------------------------------------
module \$ge (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
\$le #(
.A_SIGNED(B_SIGNED),
.B_SIGNED(A_SIGNED),
.A_WIDTH(B_WIDTH),
.B_WIDTH(A_WIDTH),
.Y_WIDTH(Y_WIDTH)
) ge_via_le (
.A(B),
.B(A),
.Y(Y)
);
endmodule
// --------------------------------------------------------
module \$gt (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
\$lt #(
.A_SIGNED(B_SIGNED),
.B_SIGNED(A_SIGNED),
.A_WIDTH(B_WIDTH),
.B_WIDTH(A_WIDTH),
.Y_WIDTH(Y_WIDTH)
) gt_via_lt (
.A(B),
.B(A),
.Y(Y)
);
endmodule
// --------------------------------------------------------
module \$add (A, B, C, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter C_WIDTH = 1;
parameter Y_WIDTH = 1;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
input [C_WIDTH-1:0] C;
output [Y_WIDTH-1:0] Y;
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
\$__alu #(
.WIDTH(Y_WIDTH)
) alu (
.A(A_buf),
.B(B_buf),
.Cin(C),
.Y(Y)
);
endmodule
// --------------------------------------------------------
module \$sub (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
\$__alu #(
.WIDTH(Y_WIDTH)
) alu (
.A(A_buf),
.B(~B_buf),
.Cin(1'b1),
.Y(Y)
);
endmodule
// --------------------------------------------------------
module \$__arraymul (A, B, Y);
parameter WIDTH = 8;
input [WIDTH-1:0] A, B;
output [WIDTH-1:0] Y;
wire [WIDTH*WIDTH-1:0] partials;
genvar i;
assign partials[WIDTH-1 : 0] = A[0] ? B : 0;
generate for (i = 1; i < WIDTH; i = i+1) begin:gen
assign partials[WIDTH*(i+1)-1 : WIDTH*i] = (A[i] ? B << i : 0) + partials[WIDTH*i-1 : WIDTH*(i-1)];
end endgenerate
assign Y = partials[WIDTH*WIDTH-1 : WIDTH*(WIDTH-1)];
endmodule
// --------------------------------------------------------
module \$mul (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
\$__arraymul #(
.WIDTH(Y_WIDTH)
) arraymul (
.A(A_buf),
.B(B_buf),
.Y(Y)
);
endmodule
// --------------------------------------------------------
module \$__div_mod_u (A, B, Y, R);
parameter WIDTH = 1;
input [WIDTH-1:0] A, B;
output [WIDTH-1:0] Y, R;
wire [WIDTH*WIDTH-1:0] chaindata;
assign R = chaindata[WIDTH*WIDTH-1:WIDTH*(WIDTH-1)];
genvar i;
generate begin
for (i = 0; i < WIDTH; i=i+1) begin:stage
wire [WIDTH-1:0] stage_in;
if (i == 0) begin:cp
assign stage_in = A;
end else begin:cp
assign stage_in = chaindata[i*WIDTH-1:(i-1)*WIDTH];
end
assign Y[WIDTH-(i+1)] = stage_in >= {B, {WIDTH-(i+1){1'b0}}};
assign chaindata[(i+1)*WIDTH-1:i*WIDTH] = Y[WIDTH-(i+1)] ? stage_in - {B, {WIDTH-(i+1){1'b0}}} : stage_in;
end
end endgenerate
endmodule
// --------------------------------------------------------
module \$__div_mod (A, B, Y, R);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
localparam WIDTH =
A_WIDTH >= B_WIDTH && A_WIDTH >= Y_WIDTH ? A_WIDTH :
B_WIDTH >= A_WIDTH && B_WIDTH >= Y_WIDTH ? B_WIDTH : Y_WIDTH;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y, R;
wire [WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
wire [WIDTH-1:0] A_buf_u, B_buf_u, Y_u, R_u;
assign A_buf_u = A_SIGNED && A_buf[WIDTH-1] ? -A_buf : A_buf;
assign B_buf_u = B_SIGNED && B_buf[WIDTH-1] ? -B_buf : B_buf;
\$__div_mod_u #(
.WIDTH(WIDTH)
) div_mod_u (
.A(A_buf_u),
.B(B_buf_u),
.Y(Y_u),
.R(R_u)
);
assign Y = A_SIGNED && B_SIGNED && (A_buf[WIDTH-1] != B_buf[WIDTH-1]) ? -Y_u : Y_u;
assign R = A_SIGNED && B_SIGNED && A_buf[WIDTH-1] ? -R_u : R_u;
endmodule
// --------------------------------------------------------
module \$div (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
\$__div_mod #(
.A_SIGNED(A_SIGNED),
.B_SIGNED(B_SIGNED),
.A_WIDTH(A_WIDTH),
.B_WIDTH(B_WIDTH),
.Y_WIDTH(Y_WIDTH)
) div_mod (
.A(A),
.B(B),
.Y(Y)
);
endmodule
// --------------------------------------------------------
module \$mod (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
\$__div_mod #(
.A_SIGNED(A_SIGNED),
.B_SIGNED(B_SIGNED),
.A_WIDTH(A_WIDTH),
.B_WIDTH(B_WIDTH),
.Y_WIDTH(Y_WIDTH)
) div_mod (
.A(A),
.B(B),
.R(Y)
);
endmodule
/****
// --------------------------------------------------------
module \$pow (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
wire signed [A_WIDTH:0] buffer_a = A_SIGNED ? $signed(A) : A;
wire signed [B_WIDTH:0] buffer_b = B_SIGNED ? $signed(B) : B;
assign Y = buffer_a ** buffer_b;
endmodule
// --------------------------------------------------------
****/
(* techmap_simplemap *)
module \$logic_not ;
endmodule
// --------------------------------------------------------
(* techmap_simplemap *)
module \$logic_and ;
endmodule
// --------------------------------------------------------
(* techmap_simplemap *)
module \$logic_or ;
endmodule
// --------------------------------------------------------
(* techmap_simplemap *)
module \$slice ;
endmodule
// --------------------------------------------------------
(* techmap_simplemap *)
module \$concat ;
endmodule
// --------------------------------------------------------
(* techmap_simplemap *)
module \$mux ;
endmodule
// --------------------------------------------------------
module \$pmux (A, B, S, Y);
parameter WIDTH = 1;
parameter S_WIDTH = 1;
input [WIDTH-1:0] A;
input [WIDTH*S_WIDTH-1:0] B;
input [S_WIDTH-1:0] S;
output [WIDTH-1:0] Y;
wire [WIDTH-1:0] Y_B;
genvar i, j;
generate
wire [WIDTH*S_WIDTH-1:0] B_AND_S;
for (i = 0; i < S_WIDTH; i = i + 1) begin:B_AND
assign B_AND_S[WIDTH*(i+1)-1:WIDTH*i] = B[WIDTH*(i+1)-1:WIDTH*i] & {WIDTH{S[i]}};
end:B_AND
for (i = 0; i < WIDTH; i = i + 1) begin:B_OR
wire [S_WIDTH-1:0] B_AND_BITS;
for (j = 0; j < S_WIDTH; j = j + 1) begin:B_AND_BITS_COLLECT
assign B_AND_BITS[j] = B_AND_S[WIDTH*j+i];
end:B_AND_BITS_COLLECT
assign Y_B[i] = |B_AND_BITS;
end:B_OR
endgenerate
assign Y = |S ? Y_B : A;
endmodule
// --------------------------------------------------------
module \$safe_pmux (A, B, S, Y);
parameter WIDTH = 1;
parameter S_WIDTH = 1;
input [WIDTH-1:0] A;
input [WIDTH*S_WIDTH-1:0] B;
input [S_WIDTH-1:0] S;
output [WIDTH-1:0] Y;
wire [S_WIDTH-1:0] status_found_first;
wire [S_WIDTH-1:0] status_found_second;
genvar i;
generate
for (i = 0; i < S_WIDTH; i = i + 1) begin:GEN1
wire pre_first;
if (i > 0) begin:GEN2
assign pre_first = status_found_first[i-1];
end:GEN2 else begin:GEN3
assign pre_first = 0;
end:GEN3
assign status_found_first[i] = pre_first | S[i];
assign status_found_second[i] = pre_first & S[i];
end:GEN1
endgenerate
\$pmux #(
.WIDTH(WIDTH),
.S_WIDTH(S_WIDTH)
) pmux_cell (
.A(A),
.B(B),
.S(S & {S_WIDTH{~|status_found_second}}),
.Y(Y)
);
endmodule
// --------------------------------------------------------
(* techmap_simplemap *)
module \$sr ;
endmodule
// --------------------------------------------------------
(* techmap_simplemap *)
module \$dff ;
endmodule
// --------------------------------------------------------
(* techmap_simplemap *)
module \$adff ;
endmodule
// --------------------------------------------------------
(* techmap_simplemap *)
module \$dffsr ;
endmodule
// --------------------------------------------------------
(* techmap_simplemap *)
module \$dlatch ;
endmodule
// --------------------------------------------------------
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O2BB2AI_PP_SYMBOL_V
`define SKY130_FD_SC_LP__O2BB2AI_PP_SYMBOL_V
/**
* o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
*
* Y = !(!(A1 & A2) & (B1 | B2))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__o2bb2ai (
//# {{data|Data Signals}}
input A1_N,
input A2_N,
input B1 ,
input B2 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O2BB2AI_PP_SYMBOL_V
|
/* Verilog for cell 'FTC{sch}' from library 'wordlib8' */
/* Created on Fri Oct 25, 2013 21:56:14 */
/* Last revised on Fri Oct 25, 2013 22:27:32 */
/* Written on Tue Oct 29, 2013 15:50:09 by Electric VLSI Design System, version 8.06 */
module muddlib07__a2o1_1x(a, b, c, y);
input a;
input b;
input c;
output y;
supply1 vdd;
supply0 gnd;
wire net_0, net_11, net_19;
tranif1 nmos_0(gnd, net_19, a);
tranif1 nmos_1(net_19, net_0, b);
tranif1 nmos_2(gnd, net_0, c);
tranif1 nmos_3(gnd, y, net_0);
tranif0 pmos_0(net_0, net_11, c);
tranif0 pmos_1(net_11, vdd, b);
tranif0 pmos_2(net_11, vdd, a);
tranif0 pmos_3(y, vdd, net_0);
endmodule /* muddlib07__a2o1_1x */
module muddlib07__nand2_1x(a, b, y);
input a;
input b;
output y;
supply1 vdd;
supply0 gnd;
wire net_5;
tranif1 nmos_0(net_5, y, b);
tranif1 nmos_1(gnd, net_5, a);
tranif0 pmos_0(y, vdd, b);
tranif0 pmos_1(y, vdd, a);
endmodule /* muddlib07__nand2_1x */
module muddlib07__o2a1i_1x(a, b, c, y);
input a;
input b;
input c;
output y;
supply1 vdd;
supply0 gnd;
wire net_35, net_7;
tranif1 nmos_0(gnd, net_7, a);
tranif1 nmos_1(gnd, net_7, b);
tranif1 nmos_2(net_7, y, c);
tranif0 pmos_0(y, net_35, b);
tranif0 pmos_1(net_35, vdd, a);
tranif0 pmos_3(y, vdd, c);
endmodule /* muddlib07__o2a1i_1x */
module muddlib07__o22a2i_1x(a, b, c, d, y);
input a;
input b;
input c;
input d;
output y;
supply1 vdd;
supply0 gnd;
wire net_34, net_35, net_7;
tranif1 nmos_0(gnd, net_7, a);
tranif1 nmos_1(gnd, net_7, b);
tranif1 nmos_2(net_7, y, c);
tranif1 nmos_3(net_7, y, d);
tranif0 pmos_0(y, net_35, b);
tranif0 pmos_1(net_35, vdd, a);
tranif0 pmos_2(y, net_34, d);
tranif0 pmos_3(net_34, vdd, c);
endmodule /* muddlib07__o22a2i_1x */
module muddlib07__xor2_2x(a, b, y);
input a;
input b;
output y;
supply1 vdd;
supply0 gnd;
wire ab, bb, net_3, net_4, net_5, net_7, net_8;
tranif1 nmos_0(gnd, net_3, a);
tranif1 nmos_1(gnd, net_4, ab);
tranif1 nmos_2(net_3, net_5, bb);
tranif1 nmos_3(net_4, net_5, b);
tranif1 nmos_4(gnd, bb, b);
tranif1 nmos_5(gnd, ab, a);
tranif1 nmos_6(gnd, y, net_5);
tranif0 pmos_0(net_5, net_7, b);
tranif0 pmos_1(net_7, vdd, a);
tranif0 pmos_2(net_5, net_8, bb);
tranif0 pmos_3(net_8, vdd, ab);
tranif0 pmos_4(bb, vdd, b);
tranif0 pmos_5(ab, vdd, a);
tranif0 pmos_6(y, vdd, net_5);
endmodule /* muddlib07__xor2_2x */
module FTC(Cin, I1, I2, I3, I4, C, Cout, S);
input Cin;
input I1;
input I2;
input I3;
input I4;
output C;
output Cout;
output S;
supply1 vdd;
supply0 gnd;
wire net_2, net_35, net_37, net_4, net_49, net_56;
muddlib07__a2o1_1x a2o1_1x_0(.a(net_49), .b(Cin), .c(net_56), .y(C));
muddlib07__nand2_1x nand2_1x_0(.a(I1), .b(I2), .y(net_4));
muddlib07__nand2_1x nand2_1x_1(.a(I3), .b(I4), .y(net_2));
muddlib07__nand2_1x nand2_1x_2(.a(net_4), .b(net_2), .y(Cout));
muddlib07__o2a1i_1x o2a1i_1x_0(.a(I4), .b(I3), .c(net_2), .y(net_37));
muddlib07__o2a1i_1x o2a1i_1x_1(.a(I2), .b(I1), .c(net_4), .y(net_35));
muddlib07__o22a2i_1x o22a2i_1_0(.a(net_2), .b(net_4), .c(net_35), .d(net_37),
.y(net_56));
muddlib07__xor2_2x xor2_2x_0(.a(net_37), .b(net_35), .y(net_49));
muddlib07__xor2_2x xor2_2x_1(.a(net_49), .b(Cin), .y(S));
endmodule /* FTC */
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O22A_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__O22A_PP_BLACKBOX_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__o22a (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O22A_PP_BLACKBOX_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2009 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
enum integer {
EP_State_IDLE ,
EP_State_CMDSHIFT0 ,
EP_State_CMDSHIFT13 ,
EP_State_CMDSHIFT14 ,
EP_State_CMDSHIFT15 ,
EP_State_CMDSHIFT16 ,
EP_State_DWAIT ,
EP_State_DSHIFT0 ,
EP_State_DSHIFT1 ,
EP_State_DSHIFT15 } m_state_xr, m_state2_xr;
// Beginning of automatic ASCII enum decoding
reg [79:0] m_stateAscii_xr; // Decode of m_state_xr
always @(m_state_xr) begin
case ({m_state_xr})
EP_State_IDLE: m_stateAscii_xr = "idle ";
EP_State_CMDSHIFT0: m_stateAscii_xr = "cmdshift0 ";
EP_State_CMDSHIFT13: m_stateAscii_xr = "cmdshift13";
EP_State_CMDSHIFT14: m_stateAscii_xr = "cmdshift14";
EP_State_CMDSHIFT15: m_stateAscii_xr = "cmdshift15";
EP_State_CMDSHIFT16: m_stateAscii_xr = "cmdshift16";
EP_State_DWAIT: m_stateAscii_xr = "dwait ";
EP_State_DSHIFT0: m_stateAscii_xr = "dshift0 ";
EP_State_DSHIFT1: m_stateAscii_xr = "dshift1 ";
EP_State_DSHIFT15: m_stateAscii_xr = "dshift15 ";
default: m_stateAscii_xr = "%Error ";
endcase
end
// End of automatics
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
//$write("%d %x %x %x\n", cyc, data, wrapcheck_a, wrapcheck_b);
if (cyc==1) begin
m_state_xr <= EP_State_IDLE;
m_state2_xr <= EP_State_IDLE;
end
if (cyc==2) begin
if (m_stateAscii_xr != "idle ") $stop;
m_state_xr <= EP_State_CMDSHIFT13;
if (m_state2_xr != EP_State_IDLE) $stop;
m_state2_xr <= EP_State_CMDSHIFT13;
end
if (cyc==3) begin
if (m_stateAscii_xr != "cmdshift13") $stop;
m_state_xr <= EP_State_CMDSHIFT16;
if (m_state2_xr != EP_State_CMDSHIFT13) $stop;
m_state2_xr <= EP_State_CMDSHIFT16;
end
if (cyc==4) begin
if (m_stateAscii_xr != "cmdshift16") $stop;
m_state_xr <= EP_State_DWAIT;
if (m_state2_xr != EP_State_CMDSHIFT16) $stop;
m_state2_xr <= EP_State_DWAIT;
end
if (cyc==9) begin
if (m_stateAscii_xr != "dwait ") $stop;
if (m_state2_xr != EP_State_DWAIT) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module vfabric_zextend(clock, reset,
i_datain, i_datain_valid, o_datain_stall,
o_dataout, i_dataout_stall, o_dataout_valid);
parameter DATAIN_WIDTH = 32;
parameter DATAOUT_WIDTH = 64;
input clock, reset;
input [DATAIN_WIDTH-1:0] i_datain;
input i_datain_valid;
output o_datain_stall;
output [DATAOUT_WIDTH-1:0] o_dataout;
input i_dataout_stall;
output o_dataout_valid;
assign o_dataout = {{DATAOUT_WIDTH{1'b0}}, i_datain[DATAIN_WIDTH-1:0]};
assign o_datain_stall = i_dataout_stall;
assign o_dataout_valid = i_datain_valid;
endmodule
|
//////////////////////////////////////////////////////////////////////////////////
// V2DatapathClockConverter32 for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Kibin Park <[email protected]>
// Yong Ho Song <[email protected]>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Kibin Park <[email protected]>
//
// Project Name: Cosmos OpenSSD
// Design Name: V2 data path clock converter 32
// Module Name: V2DatapathClockConverter32
// File Name: V2DatapathClockConverter32.v
//
// Version: v1.0.0
//
// Description: data path clock converter
//
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 1 ps
module V2DatapathClockConverter32
#
(
)
(
iSClock ,
iSReset ,
iSWOpcode ,
iSWTargetID ,
iSWSourceID ,
iSWAddress ,
iSWLength ,
iSWCMDValid ,
oSWCMDReady ,
iSWriteData ,
iSWriteLast ,
iSWriteValid ,
oSWriteReady ,
iSROpcode ,
iSRTargetID ,
iSRSourceID ,
iSRAddress ,
iSRLength ,
iSRCMDValid ,
oSRCMDReady ,
oSReadData ,
oSReadLast ,
oSReadValid ,
iSReadReady ,
iMClock ,
iMReset ,
oMWOpcode ,
oMWTargetID ,
oMWSourceID ,
oMWAddress ,
oMWLength ,
oMWCMDValid ,
iMWCMDReady ,
oMWriteData ,
oMWriteLast ,
oMWriteValid ,
iMWriteReady ,
oMROpcode ,
oMRTargetID ,
oMRSourceID ,
oMRAddress ,
oMRLength ,
oMRCMDValid ,
iMRCMDReady ,
iMReadData ,
iMReadLast ,
iMReadValid ,
oMReadReady
);
input iSClock ;
input iSReset ;
input [5:0] iSWOpcode ;
input [4:0] iSWTargetID ;
input [4:0] iSWSourceID ;
input [31:0] iSWAddress ;
input [15:0] iSWLength ;
input iSWCMDValid ;
output oSWCMDReady ;
input [31:0] iSWriteData ;
input iSWriteLast ;
input iSWriteValid ;
output oSWriteReady ;
input [5:0] iSROpcode ;
input [4:0] iSRTargetID ;
input [4:0] iSRSourceID ;
input [31:0] iSRAddress ;
input [15:0] iSRLength ;
input iSRCMDValid ;
output oSRCMDReady ;
output [31:0] oSReadData ;
output oSReadLast ;
output oSReadValid ;
input iSReadReady ;
input iMClock ;
input iMReset ;
output [5:0] oMWOpcode ;
output [4:0] oMWTargetID ;
output [4:0] oMWSourceID ;
output [31:0] oMWAddress ;
output [15:0] oMWLength ;
output oMWCMDValid ;
input iMWCMDReady ;
output [31:0] oMWriteData ;
output oMWriteLast ;
output oMWriteValid ;
input iMWriteReady ;
output [5:0] oMROpcode ;
output [4:0] oMRTargetID ;
output [4:0] oMRSourceID ;
output [31:0] oMRAddress ;
output [15:0] oMRLength ;
output oMRCMDValid ;
input iMRCMDReady ;
input [31:0] iMReadData ;
input iMReadLast ;
input iMReadValid ;
output oMReadReady ;
genvar rbgen;
wire wCWChCDCFIFOPopEnable ;
wire wCWChCDCFIFOEmpty ;
wire wCWChCDCFIFOFull ;
wire [63:0] wCWChCmdDataIn ;
wire [63:0] wCWChCmdDataOut ;
wire wCRChCDCFIFOPopEnable ;
wire wCRChCDCFIFOEmpty ;
wire wCRChCDCFIFOFull ;
wire [63:0] wCRChCmdDataIn ;
wire [63:0] wCRChCmdDataOut ;
wire wWChCDCFIFOPopEnable ;
wire wWChCDCFIFOEmpty ;
wire wWChCDCFIFOFull ;
wire wRChCDCFIFOPopEnable ;
wire wRChCDCFIFOEmpty ;
wire wRChCDCFIFOFull ;
AutoFIFOPopControl
Inst_CWChCDCFIFOControl
(
.iClock (iMClock ),
.iReset (iMReset ),
.oPopSignal (wCWChCDCFIFOPopEnable ),
.iEmpty (wCWChCDCFIFOEmpty ),
.oValid (oMWCMDValid ),
.iReady (iMWCMDReady )
);
DCFIFO_64x16_DR
Inst_CWChCDCFIFO
(
.iWClock (iSClock ),
.iWReset (iSReset ),
.iPushData (wCWChCmdDataIn ),
.iPushEnable (iSWCMDValid & oSWCMDReady ),
.oIsFull (wCWChCDCFIFOFull ),
.iRClock (iMClock ),
.iRReset (iMReset ),
.oPopData (wCWChCmdDataOut ),
.iPopEnable (wCWChCDCFIFOPopEnable ),
.oIsEmpty (wCWChCDCFIFOEmpty )
);
assign wCWChCmdDataIn = {iSWOpcode, iSWTargetID, iSWSourceID, iSWAddress, iSWLength};
assign {oMWOpcode, oMWTargetID, oMWSourceID, oMWAddress, oMWLength} = wCWChCmdDataOut;
assign oSWCMDReady = !wCWChCDCFIFOFull;
AutoFIFOPopControl
Inst_CRChCDCFIFOControl
(
.iClock (iMClock ),
.iReset (iMReset ),
.oPopSignal (wCRChCDCFIFOPopEnable ),
.iEmpty (wCRChCDCFIFOEmpty ),
.oValid (oMRCMDValid ),
.iReady (iMRCMDReady )
);
DCFIFO_64x16_DR
Inst_CRChCDCFIFO
(
.iWClock (iSClock ),
.iWReset (iSReset ),
.iPushData (wCRChCmdDataIn ),
.iPushEnable (iSRCMDValid & oSRCMDReady ),
.oIsFull (wCRChCDCFIFOFull ),
.iRClock (iMClock ),
.iRReset (iMReset ),
.oPopData (wCRChCmdDataOut ),
.iPopEnable (wCRChCDCFIFOPopEnable ),
.oIsEmpty (wCRChCDCFIFOEmpty )
);
assign wCRChCmdDataIn = {iSROpcode, iSRTargetID, iSRSourceID, iSRAddress, iSRLength};
assign {oMROpcode, oMRTargetID, oMRSourceID, oMRAddress, oMRLength} = wCRChCmdDataOut;
assign oSRCMDReady = !wCRChCDCFIFOFull;
AutoFIFOPopControl
Inst_WChCDCFIFOControl
(
.iClock (iMClock ),
.iReset (iMReset ),
.oPopSignal (wWChCDCFIFOPopEnable ),
.iEmpty (wWChCDCFIFOEmpty ),
.oValid (oMWriteValid ),
.iReady (iMWriteReady )
);
DCFIFO_36x16_DR
Inst_WChCDCFIFO
(
.iWClock (iSClock ),
.iWReset (iSReset ),
.iPushData ({iSWriteData, iSWriteLast} ),
.iPushEnable (iSWriteValid & oSWriteReady),
.oIsFull (wWChCDCFIFOFull ),
.iRClock (iMClock ),
.iRReset (iMReset ),
.oPopData ({oMWriteData, oMWriteLast} ),
.iPopEnable (wWChCDCFIFOPopEnable ),
.oIsEmpty (wWChCDCFIFOEmpty )
);
assign oSWriteReady = !wWChCDCFIFOFull;
AutoFIFOPopControl
Inst_RChCDCFIFOControl
(
.iClock (iSClock ),
.iReset (iSReset ),
.oPopSignal (wRChCDCFIFOPopEnable ),
.iEmpty (wRChCDCFIFOEmpty ),
.oValid (oSReadValid ),
.iReady (iSReadReady )
);
DCFIFO_36x16_DR
Inst_RChCDCFIFO
(
.iWClock (iMClock ),
.iWReset (iMReset ),
.iPushData ({iMReadData, iMReadLast} ),
.iPushEnable (iMReadValid & oMReadReady ),
.oIsFull (wRChCDCFIFOFull ),
.iRClock (iSClock ),
.iRReset (iSReset ),
.oPopData ({oSReadData, oSReadLast} ),
.iPopEnable (wRChCDCFIFOPopEnable ),
.oIsEmpty (wRChCDCFIFOEmpty )
);
assign oMReadReady = !wRChCDCFIFOFull;
endmodule |
`ifndef MEMORY_V
`define MEMORY_V
`define MEM_CMD_WIDTH 1
`define MEM_CMD_READ 1'b0
`define MEM_CMD_WRITE 1'b1
module memory#(
parameter ADDRESS_WIDTH=32,
parameter DATA_WIDTH=32,
parameter SIZE = 1024*1024,
parameter READ_DELAY = 22,
parameter WRITE_DELAY = 15
)(
input clk,
input reset,
input [ADDRESS_WIDTH-1:0]i_address,
input [DATA_WIDTH-1:0]i_data,
input i_valid,
input i_res_ready,
input i_cmd,
output [DATA_WIDTH-1:0]o_data,
output o_res_valid,
output o_ready
);
`define CELLS (SIZE / (DATA_WIDTH / 8))
reg [DATA_WIDTH-1:0]memory_cells [0:`CELLS];
wire [ADDRESS_WIDTH-1:0]cell_address = i_address >> $clog2(DATA_WIDTH/8);
reg ready;
reg res_valid;
reg [DATA_WIDTH-1:0]data;
assign o_data = data;
assign o_res_valid = res_valid;
assign o_ready = ready;
//load data
initial begin
string file;
integer fd, size, result;
if ($value$plusargs("img=%s", file)) begin
// get file size
fd = $fopen(file, "r");
result = $fseek(fd, 0, 2);
result = $ftell(fd);
$fclose(fd);
size = (result / 11); // '0' + 'x' + 8chars + lf,
//one cell -- one line no matter the cell size
$display("Loading img file: %s, file size: %d, cells: %d", file, result, size);
$readmemh(file, memory_cells, 0, size - 1); // '0' + 'x' + 8chars + lf
$display("The first word is: %x", memory_cells[0]);
$display("The second word is: %x", memory_cells[1]);
end else begin
$display("Please specify input image file '+img'");
end
end
// reset
always @(posedge clk) begin
if (reset) begin
ready = 1'b1;
res_valid = 1'b0;
data = 1'bx;
end
if (!reset && i_valid && o_ready) begin
case (i_cmd)
//read takes
`MEM_CMD_READ: begin
#READ_DELAY data <= memory_cells[cell_address];
#READ_DELAY res_valid <= 1'b1;
ready <= 1'b0;
end
`MEM_CMD_WRITE: begin
//TODO
$display("Mem Write not implemented");
$finish();
end
endcase
end
if (!reset && res_valid && i_res_ready) begin
ready <= 1'b1;
res_valid <= 1'b0;
data <= 1'bx;
end
end
endmodule
`endif
|
/*
:Project
FPGA-Imaging-Library
:Design
FrameController
:Function
For controlling a BlockRAM from xilinx.
Give the first output after ram_read_latency cycles while the input enable.
:Module
Main module
:Version
1.0
:Modified
2015-05-12
Copyright (C) 2015 Tianyu Dai (dtysky) <[email protected]>
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
Homepage for this project:
http://fil.dtysky.moe
Sources for this project:
https://github.com/dtysky/FPGA-Imaging-Library
My e-mail:
[email protected]
My blog:
http://dtysky.moe
*/
`timescale 1ns / 1ps
module FrameController(
clk,
rst_n,
in_enable,
in_data,
out_ready,
out_data,
ram_addr);
/*
::description
This module's working mode.
::range
0 for Pipline, 1 for Req-ack
*/
parameter work_mode = 0;
/*
::description
This module's WR mode.
::range
0 for Write, 1 for Read
*/
parameter wr_mode = 0;
/*
::description
Data bit width.
*/
parameter data_width = 8;
/*
::description
Width of image.
::range
1 - 4096
*/
parameter im_width = 320;
/*
::description
Height of image.
::range
1 - 4096
*/
parameter im_height = 240;
/*
::description
Address bit width of a ram for storing this image.
::range
Depend on im_width and im_height.
*/
parameter addr_width = 17;
/*
::description
RL of RAM, in xilinx 7-series device, it is 2.
::range
0 - 15, Depend on your using ram.
*/
parameter ram_read_latency = 2;
/*
::description
The first row you want to storing, used for eliminating offset.
::range
Depend on your input offset.
*/
parameter row_init = 0;
/*
::description
Clock.
*/
input clk;
/*
::description
Reset, active low.
*/
input rst_n;
/*
::description
Input data enable, in pipeline mode, it works as another rst_n, in req-ack mode, only it is high will in_data can be really changes.
*/
input in_enable;
/*
::description
Input data, it must be synchronous with in_enable.
*/
input [data_width - 1 : 0] in_data;
/*
::description
Output data ready, in both two mode, it will be high while the out_data can be read.
*/
output out_ready;
/*
::description
Output data, it will be synchronous with out_ready.
*/
output[data_width - 1 : 0] out_data;
/*
::description
Address for ram.
*/
output[addr_width - 1 : 0] ram_addr;
reg[addr_width - 1 : 0] reg_ram_addr;
reg[3 : 0] con_ready;
assign ram_addr = reg_ram_addr;
assign out_data = out_ready ? in_data : 0;
generate
if(wr_mode == 0) begin
if(work_mode == 0) begin
always @(posedge clk or negedge rst_n or negedge in_enable) begin
if(~rst_n || ~in_enable)
reg_ram_addr <= row_init * im_width;
else if(reg_ram_addr == im_width * im_height - 1)
reg_ram_addr <= 0;
else
reg_ram_addr <= reg_ram_addr + 1;
end
end else begin
always @(posedge in_enable or negedge rst_n) begin
if(~rst_n)
reg_ram_addr <= row_init * im_width - 1;
else if(reg_ram_addr == im_width * im_height - 1)
reg_ram_addr <= 0;
else
reg_ram_addr <= reg_ram_addr + 1;
end
end
assign out_ready = ~rst_n || ~in_enable ? 0 : 1;
end else begin
if(work_mode == 0) begin
always @(posedge clk or negedge rst_n or negedge in_enable) begin
if(~rst_n || ~in_enable)
reg_ram_addr <= 0;
else if(reg_ram_addr == im_width * im_height - 1)
reg_ram_addr <= 0;
else
reg_ram_addr <= reg_ram_addr + 1;
end
end else begin
always @(posedge in_enable or negedge rst_n) begin
if(~rst_n)
reg_ram_addr <= 0 - 1;
else if(reg_ram_addr == im_width * im_height - 1)
reg_ram_addr <= 0;
else
reg_ram_addr <= reg_ram_addr + 1;
end
end
always @(posedge clk or negedge rst_n or negedge in_enable) begin
if(~rst_n || ~in_enable)
con_ready <= 0;
else if (con_ready == ram_read_latency)
con_ready <= con_ready;
else
con_ready <= con_ready + 1;
end
assign out_ready = con_ready == ram_read_latency ? 1 : 0;
end
endgenerate
endmodule |
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// Manually created global mem, to avoid qsys hex generation bug
// qsys will always generate a .hex file to initialize the
// altsyncram - EVEN if you specify not to init the ram,
// for big ram's, this causes qsys to hang
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module bram_256x67M (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
write,
writedata,
// outputs:
readdata
)
;
parameter DEPTH = 67108864;
parameter NWORDS_A = 67108864;
parameter ADDR_WIDTH = 26; // this should be $clog( DEPTH ), but qsys dies;
output [255: 0] readdata;
// ADDR_WIDTH
input [ 25: 0] address;
input [ 31: 0] byteenable;
input chipselect;
input clk;
input clken;
input reset;
input write;
input [255: 0] writedata;
reg [255: 0] readdata;
wire [255: 0] readdata_ram;
wire wren;
always @(posedge clk)
begin
if (clken)
readdata <= readdata_ram;
end
assign wren = chipselect & write;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clk),
.clocken0 (clken),
.data_a (writedata),
.q_a (readdata_ram),
.wren_a (wren)
);
defparam the_altsyncram.byte_size = 8,
the_altsyncram.init_file = "UNUSED",
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = DEPTH,
the_altsyncram.numwords_a = NWORDS_A,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 256,
the_altsyncram.width_byteena_a = 32,
the_altsyncram.widthad_a = ADDR_WIDTH;
//////////////// END SIMULATION-ONLY CONTENTS
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR4B_BLACKBOX_V
`define SKY130_FD_SC_LP__OR4B_BLACKBOX_V
/**
* or4b: 4-input OR, first input inverted.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__or4b (
X ,
A ,
B ,
C ,
D_N
);
output X ;
input A ;
input B ;
input C ;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR4B_BLACKBOX_V
|
// (C) 2001-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// (C) 2001-2013 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/15.1/ip/merlin/altera_reset_controller/altera_reset_controller.v#1 $
// $Revision: #1 $
// $Date: 2015/08/09 $
// $Author: swbranch $
// --------------------------------------
// Reset controller
//
// Combines all the input resets and synchronizes
// the result to the clk.
// ACDS13.1 - Added reset request as part of reset sequencing
// --------------------------------------
`timescale 1 ns / 1 ns
module altera_reset_controller
#(
parameter NUM_RESET_INPUTS = 6,
parameter USE_RESET_REQUEST_IN0 = 0,
parameter USE_RESET_REQUEST_IN1 = 0,
parameter USE_RESET_REQUEST_IN2 = 0,
parameter USE_RESET_REQUEST_IN3 = 0,
parameter USE_RESET_REQUEST_IN4 = 0,
parameter USE_RESET_REQUEST_IN5 = 0,
parameter USE_RESET_REQUEST_IN6 = 0,
parameter USE_RESET_REQUEST_IN7 = 0,
parameter USE_RESET_REQUEST_IN8 = 0,
parameter USE_RESET_REQUEST_IN9 = 0,
parameter USE_RESET_REQUEST_IN10 = 0,
parameter USE_RESET_REQUEST_IN11 = 0,
parameter USE_RESET_REQUEST_IN12 = 0,
parameter USE_RESET_REQUEST_IN13 = 0,
parameter USE_RESET_REQUEST_IN14 = 0,
parameter USE_RESET_REQUEST_IN15 = 0,
parameter OUTPUT_RESET_SYNC_EDGES = "deassert",
parameter SYNC_DEPTH = 2,
parameter RESET_REQUEST_PRESENT = 0,
parameter RESET_REQ_WAIT_TIME = 3,
parameter MIN_RST_ASSERTION_TIME = 11,
parameter RESET_REQ_EARLY_DSRT_TIME = 4,
parameter ADAPT_RESET_REQUEST = 0
)
(
// --------------------------------------
// We support up to 16 reset inputs, for now
// --------------------------------------
input reset_in0,
input reset_in1,
input reset_in2,
input reset_in3,
input reset_in4,
input reset_in5,
input reset_in6,
input reset_in7,
input reset_in8,
input reset_in9,
input reset_in10,
input reset_in11,
input reset_in12,
input reset_in13,
input reset_in14,
input reset_in15,
input reset_req_in0,
input reset_req_in1,
input reset_req_in2,
input reset_req_in3,
input reset_req_in4,
input reset_req_in5,
input reset_req_in6,
input reset_req_in7,
input reset_req_in8,
input reset_req_in9,
input reset_req_in10,
input reset_req_in11,
input reset_req_in12,
input reset_req_in13,
input reset_req_in14,
input reset_req_in15,
input clk,
output reg reset_out,
output reg reset_req
);
// Always use async reset synchronizer if reset_req is used
localparam ASYNC_RESET = (OUTPUT_RESET_SYNC_EDGES == "deassert");
// --------------------------------------
// Local parameter to control the reset_req and reset_out timing when RESET_REQUEST_PRESENT==1
// --------------------------------------
localparam MIN_METASTABLE = 3;
localparam RSTREQ_ASRT_SYNC_TAP = MIN_METASTABLE + RESET_REQ_WAIT_TIME;
localparam LARGER = RESET_REQ_WAIT_TIME > RESET_REQ_EARLY_DSRT_TIME ? RESET_REQ_WAIT_TIME : RESET_REQ_EARLY_DSRT_TIME;
localparam ASSERTION_CHAIN_LENGTH = (MIN_METASTABLE > LARGER) ?
MIN_RST_ASSERTION_TIME + 1 :
(
(MIN_RST_ASSERTION_TIME > LARGER)?
MIN_RST_ASSERTION_TIME + (LARGER - MIN_METASTABLE + 1) + 1 :
MIN_RST_ASSERTION_TIME + RESET_REQ_EARLY_DSRT_TIME + RESET_REQ_WAIT_TIME - MIN_METASTABLE + 2
);
localparam RESET_REQ_DRST_TAP = RESET_REQ_EARLY_DSRT_TIME + 1;
// --------------------------------------
wire merged_reset;
wire merged_reset_req_in;
wire reset_out_pre;
wire reset_req_pre;
// Registers and Interconnect
(*preserve*) reg [RSTREQ_ASRT_SYNC_TAP: 0] altera_reset_synchronizer_int_chain;
reg [ASSERTION_CHAIN_LENGTH-1: 0] r_sync_rst_chain;
reg r_sync_rst;
reg r_early_rst;
// --------------------------------------
// "Or" all the input resets together
// --------------------------------------
assign merged_reset = (
reset_in0 |
reset_in1 |
reset_in2 |
reset_in3 |
reset_in4 |
reset_in5 |
reset_in6 |
reset_in7 |
reset_in8 |
reset_in9 |
reset_in10 |
reset_in11 |
reset_in12 |
reset_in13 |
reset_in14 |
reset_in15
);
assign merged_reset_req_in = (
( (USE_RESET_REQUEST_IN0 == 1) ? reset_req_in0 : 1'b0) |
( (USE_RESET_REQUEST_IN1 == 1) ? reset_req_in1 : 1'b0) |
( (USE_RESET_REQUEST_IN2 == 1) ? reset_req_in2 : 1'b0) |
( (USE_RESET_REQUEST_IN3 == 1) ? reset_req_in3 : 1'b0) |
( (USE_RESET_REQUEST_IN4 == 1) ? reset_req_in4 : 1'b0) |
( (USE_RESET_REQUEST_IN5 == 1) ? reset_req_in5 : 1'b0) |
( (USE_RESET_REQUEST_IN6 == 1) ? reset_req_in6 : 1'b0) |
( (USE_RESET_REQUEST_IN7 == 1) ? reset_req_in7 : 1'b0) |
( (USE_RESET_REQUEST_IN8 == 1) ? reset_req_in8 : 1'b0) |
( (USE_RESET_REQUEST_IN9 == 1) ? reset_req_in9 : 1'b0) |
( (USE_RESET_REQUEST_IN10 == 1) ? reset_req_in10 : 1'b0) |
( (USE_RESET_REQUEST_IN11 == 1) ? reset_req_in11 : 1'b0) |
( (USE_RESET_REQUEST_IN12 == 1) ? reset_req_in12 : 1'b0) |
( (USE_RESET_REQUEST_IN13 == 1) ? reset_req_in13 : 1'b0) |
( (USE_RESET_REQUEST_IN14 == 1) ? reset_req_in14 : 1'b0) |
( (USE_RESET_REQUEST_IN15 == 1) ? reset_req_in15 : 1'b0)
);
// --------------------------------------
// And if required, synchronize it to the required clock domain,
// with the correct synchronization type
// --------------------------------------
generate if (OUTPUT_RESET_SYNC_EDGES == "none" && (RESET_REQUEST_PRESENT==0)) begin
assign reset_out_pre = merged_reset;
assign reset_req_pre = merged_reset_req_in;
end else begin
altera_reset_synchronizer
#(
.DEPTH (SYNC_DEPTH),
.ASYNC_RESET(RESET_REQUEST_PRESENT? 1'b1 : ASYNC_RESET)
)
alt_rst_sync_uq1
(
.clk (clk),
.reset_in (merged_reset),
.reset_out (reset_out_pre)
);
altera_reset_synchronizer
#(
.DEPTH (SYNC_DEPTH),
.ASYNC_RESET(0)
)
alt_rst_req_sync_uq1
(
.clk (clk),
.reset_in (merged_reset_req_in),
.reset_out (reset_req_pre)
);
end
endgenerate
generate if ( ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==0) )|
( (ADAPT_RESET_REQUEST == 1) && (OUTPUT_RESET_SYNC_EDGES != "deassert") ) ) begin
always @* begin
reset_out = reset_out_pre;
reset_req = reset_req_pre;
end
end else if ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==1) ) begin
wire reset_out_pre2;
altera_reset_synchronizer
#(
.DEPTH (SYNC_DEPTH+1),
.ASYNC_RESET(0)
)
alt_rst_sync_uq2
(
.clk (clk),
.reset_in (reset_out_pre),
.reset_out (reset_out_pre2)
);
always @* begin
reset_out = reset_out_pre2;
reset_req = reset_req_pre;
end
end
else begin
// 3-FF Metastability Synchronizer
initial
begin
altera_reset_synchronizer_int_chain <= {RSTREQ_ASRT_SYNC_TAP{1'b1}};
end
always @(posedge clk)
begin
altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP:0] <=
{altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP-1:0], reset_out_pre};
end
// Synchronous reset pipe
initial
begin
r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}};
end
always @(posedge clk)
begin
if (altera_reset_synchronizer_int_chain[MIN_METASTABLE-1] == 1'b1)
begin
r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}};
end
else
begin
r_sync_rst_chain <= {1'b0, r_sync_rst_chain[ASSERTION_CHAIN_LENGTH-1:1]};
end
end
// Standard synchronous reset output. From 0-1, the transition lags the early output. For 1->0, the transition
// matches the early input.
always @(posedge clk)
begin
case ({altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP], r_sync_rst_chain[1], r_sync_rst})
3'b000: r_sync_rst <= 1'b0; // Not reset
3'b001: r_sync_rst <= 1'b0;
3'b010: r_sync_rst <= 1'b0;
3'b011: r_sync_rst <= 1'b1;
3'b100: r_sync_rst <= 1'b1;
3'b101: r_sync_rst <= 1'b1;
3'b110: r_sync_rst <= 1'b1;
3'b111: r_sync_rst <= 1'b1; // In Reset
default: r_sync_rst <= 1'b1;
endcase
case ({r_sync_rst_chain[1], r_sync_rst_chain[RESET_REQ_DRST_TAP] | reset_req_pre})
2'b00: r_early_rst <= 1'b0; // Not reset
2'b01: r_early_rst <= 1'b1; // Coming out of reset
2'b10: r_early_rst <= 1'b0; // Spurious reset - should not be possible via synchronous design.
2'b11: r_early_rst <= 1'b1; // Held in reset
default: r_early_rst <= 1'b1;
endcase
end
always @* begin
reset_out = r_sync_rst;
reset_req = r_early_rst;
end
end
endgenerate
endmodule
|
`timescale 1ns / 1ps
/*
Copyright 2015, Google Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:37:26 05/13/2014
// Design Name:
// Module Name: wb_aes_ctrl
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module wb_aes_ctrl (
input wb_clk_i,
input wb_rst_i,
input [31:0] wb_adr_i,
input [31:0] wb_dat_i,
input [3:0] wb_sel_i,
input wb_we_i,
input [1:0] wb_bte_i,
input [2:0] wb_cti_i,
input wb_cyc_i,
input wb_stb_i,
output reg wb_ack_o,
output wb_err_o,
output wb_rty_o,
output reg [31:0] wb_dat_o,
output reg [255:0] key_o,
output reg dec_o,
output reg [1:0] size_o,
output reg [127:0] data_o,
output reg load_o,
input [127:0] data_i,
input busy_i
);
`include "wb_common.v"
assign wb_err_o = 0;
assign wb_rty_o = 0;
wire valid = (wb_cyc_i & wb_stb_i);
reg valid_r;
wire new_cycle = valid & ~valid_r;
reg [6:0] adr_r;
wire [6:0] next_adr = wb_next_adr(adr_r, wb_cti_i, wb_bte_i, 32);
wire [6:0] wb_adr = new_cycle ? wb_adr_i : next_adr;
reg [127:0] data_ir;
always @(posedge wb_clk_i)
begin
adr_r <= wb_adr;
valid_r <= valid;
wb_ack_o <= valid & (!((wb_cti_i == 3'b000) | (wb_cti_i == 3'b111)) | !wb_ack_o);
if(wb_rst_i)
begin
adr_r <= 0;
valid_r <= 0;
wb_ack_o <= 0;
end
end
reg busy_r, rst_r, go_r;
wire rst = (rst_r | wb_rst_i);
`define KEY_WRITE(x) \
key_o[256 - (x * 32) - 23:256 - (x * 32) - 32] <= (wb_sel_i[0]) \
? wb_dat_i[ 7: 0] : key_o[256 - (x * 32) - 23:256 - (x * 32) - 32]; \
key_o[256 - (x * 32) - 17:256 - (x * 32) - 24] <= (wb_sel_i[1]) \
? wb_dat_i[15: 8] : key_o[256 - (x * 32) - 17:256 - (x * 32) - 24]; \
key_o[256 - (x * 32) - 9:256 - (x * 32) - 16] <= (wb_sel_i[2]) \
? wb_dat_i[23:16] : key_o[256 - (x * 32) - 9:256 - (x * 32) - 16]; \
key_o[256 - (x * 32) - 1:256 - (x * 32) - 8] <= (wb_sel_i[3]) \
? wb_dat_i[31:24] : key_o[256 - (x * 32) - 1:256 - (x * 32) - 8];
`define DATA_READ(x) \
wb_dat_o <= (load_o | busy_i) \
? 32'h0 : data_ir[128 - (x * 32) - 1:128 - (x * 32) - 32];
`define DATA_WRITE(x) \
data_o[128 - (x * 32) - 23:128 - (x * 32) - 32] <= (wb_sel_i[0]) \
? wb_dat_i[ 7: 0] : data_o[128 - (x * 32) - 23:128 - (x * 32) - 32]; \
data_o[128 - (x * 32) - 17:128 - (x * 32) - 24] <= (wb_sel_i[1]) \
? wb_dat_i[15: 8] : data_o[128 - (x * 32) - 17:128 - (x * 32) - 24]; \
data_o[128 - (x * 32) - 9:128 - (x * 32) - 16] <= (wb_sel_i[2]) \
? wb_dat_i[23:16] : data_o[128 - (x * 32) - 9:128 - (x * 32) - 16]; \
data_o[128 - (x * 32) - 1:128 - (x * 32) - 8] <= (wb_sel_i[3]) \
? wb_dat_i[31:24] : data_o[128 - (x * 32) - 1:128 - (x * 32) - 8];
always @(posedge wb_clk_i)
begin : ctrl_block
busy_r <= busy_i;
rst_r <= 0;
if(rst)
begin
data_ir <= 0;
load_o <= 0;
dec_o <= 0;
size_o <= 0;
data_o <= 0;
key_o <= 0;
load_o <= 0;
end
else
begin
if(busy_r & ~busy_i)
begin
data_ir <= data_i;
end
if(busy_i)
load_o <= 0;
if(valid & wb_we_i & ~busy_i & ~load_o)
begin
case(wb_adr[6:4])
3'b000:
begin
case(wb_adr[3:2])
0: begin `KEY_WRITE(0); end
1: begin `KEY_WRITE(1); end
2: begin `KEY_WRITE(2); end
3: begin `KEY_WRITE(3); end
endcase
end
3'b001:
begin
case(wb_adr[3:2])
0: begin `KEY_WRITE(4); end
1: begin `KEY_WRITE(5); end
2: begin `KEY_WRITE(6); end
3: begin `KEY_WRITE(7); end
endcase
end
3'b010:
begin
case(wb_adr[3:2])
0: begin `DATA_WRITE(0); end
1: begin `DATA_WRITE(1); end
2: begin `DATA_WRITE(2); end
3: begin `DATA_WRITE(3); end
endcase
end
3'b100:
begin
if(wb_adr[3:2] == 0)
begin
load_o <= wb_sel_i[0] & wb_dat_i[0];
dec_o <= wb_sel_i[0] & wb_dat_i[1];
size_o <= {2{wb_sel_i[0]}} & wb_dat_i[3:2];
rst_r <= wb_sel_i[1] & wb_dat_i[8];
end
end
endcase
end // write handler
if(valid & ~wb_we_i)
begin
case(wb_adr[6:4])
3'b011:
begin
case(wb_adr[3:2])
0: begin `DATA_READ(0); end
1: begin `DATA_READ(1); end
2: begin `DATA_READ(2); end
3: begin `DATA_READ(3); end
endcase
end
3'b100:
begin
if(wb_adr[3:2] == 0)
wb_dat_o <= { 15'h0, load_o | busy_i, 16'h0 };
else
wb_dat_o <= 32'h0;
end
default: wb_dat_o <= 32'h0;
endcase
end // read handler
end
end
endmodule
|
// -- (c) Copyright 2012 -2013 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// File name: axi_protocol_converter.v
//
// Description:
// This module is a bank of AXI4-Lite and AXI3 protocol converters for a vectored AXI interface.
// The interface of this module consists of a vectored slave and master interface
// which are each concatenations of upper-level AXI pathways,
// plus various vectored parameters.
// This module instantiates a set of individual protocol converter modules.
//
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_axi_protocol_converter #(
parameter C_FAMILY = "virtex6",
parameter integer C_M_AXI_PROTOCOL = 0,
parameter integer C_S_AXI_PROTOCOL = 0,
parameter integer C_IGNORE_ID = 0,
// 0 = RID/BID are stored by axilite_conv.
// 1 = RID/BID have already been stored in an upstream device, like SASD crossbar.
parameter integer C_AXI_ID_WIDTH = 4,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_WRITE = 1,
parameter integer C_AXI_SUPPORTS_READ = 1,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
// 1 = Propagate all USER signals, 0 = Dont propagate.
parameter integer C_AXI_AWUSER_WIDTH = 1,
parameter integer C_AXI_ARUSER_WIDTH = 1,
parameter integer C_AXI_WUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AXI_BUSER_WIDTH = 1,
parameter integer C_TRANSLATION_MODE = 1
// 0 (Unprotected) = Disable all error checking; master is well-behaved.
// 1 (Protection) = Detect SI transaction violations, but perform no splitting.
// AXI4 -> AXI3 must be <= 16 beats; AXI4/3 -> AXI4LITE must be single.
// 2 (Conversion) = Include transaction splitting logic
) (
// Global Signals
input wire aclk,
input wire aresetn,
// Slave Interface Write Address Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_awid,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input wire [((C_S_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,
input wire [3-1:0] s_axi_awsize,
input wire [2-1:0] s_axi_awburst,
input wire [((C_S_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,
input wire [4-1:0] s_axi_awcache,
input wire [3-1:0] s_axi_awprot,
input wire [4-1:0] s_axi_awregion,
input wire [4-1:0] s_axi_awqos,
input wire [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,
input wire s_axi_awvalid,
output wire s_axi_awready,
// Slave Interface Write Data Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_wid,
input wire [C_AXI_DATA_WIDTH-1:0] s_axi_wdata,
input wire [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,
input wire s_axi_wlast,
input wire [C_AXI_WUSER_WIDTH-1:0] s_axi_wuser,
input wire s_axi_wvalid,
output wire s_axi_wready,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] s_axi_bid,
output wire [2-1:0] s_axi_bresp,
output wire [C_AXI_BUSER_WIDTH-1:0] s_axi_buser,
output wire s_axi_bvalid,
input wire s_axi_bready,
// Slave Interface Read Address Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_arid,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input wire [((C_S_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,
input wire [3-1:0] s_axi_arsize,
input wire [2-1:0] s_axi_arburst,
input wire [((C_S_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,
input wire [4-1:0] s_axi_arcache,
input wire [3-1:0] s_axi_arprot,
input wire [4-1:0] s_axi_arregion,
input wire [4-1:0] s_axi_arqos,
input wire [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,
input wire s_axi_arvalid,
output wire s_axi_arready,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] s_axi_rid,
output wire [C_AXI_DATA_WIDTH-1:0] s_axi_rdata,
output wire [2-1:0] s_axi_rresp,
output wire s_axi_rlast,
output wire [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,
output wire s_axi_rvalid,
input wire s_axi_rready,
// Master Interface Write Address Port
output wire [C_AXI_ID_WIDTH-1:0] m_axi_awid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [((C_M_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,
output wire [3-1:0] m_axi_awsize,
output wire [2-1:0] m_axi_awburst,
output wire [((C_M_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,
output wire [4-1:0] m_axi_awcache,
output wire [3-1:0] m_axi_awprot,
output wire [4-1:0] m_axi_awregion,
output wire [4-1:0] m_axi_awqos,
output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
output wire m_axi_awvalid,
input wire m_axi_awready,
// Master Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_wid,
output wire [C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output wire m_axi_wlast,
output wire [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
output wire m_axi_wvalid,
input wire m_axi_wready,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_bid,
input wire [2-1:0] m_axi_bresp,
input wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
input wire m_axi_bvalid,
output wire m_axi_bready,
// Master Interface Read Address Port
output wire [C_AXI_ID_WIDTH-1:0] m_axi_arid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [((C_M_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,
output wire [3-1:0] m_axi_arsize,
output wire [2-1:0] m_axi_arburst,
output wire [((C_M_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,
output wire [4-1:0] m_axi_arcache,
output wire [3-1:0] m_axi_arprot,
output wire [4-1:0] m_axi_arregion,
output wire [4-1:0] m_axi_arqos,
output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
output wire m_axi_arvalid,
input wire m_axi_arready,
// Master Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_rid,
input wire [C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input wire [2-1:0] m_axi_rresp,
input wire m_axi_rlast,
input wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
input wire m_axi_rvalid,
output wire m_axi_rready
);
localparam P_AXI4 = 32'h0;
localparam P_AXI3 = 32'h1;
localparam P_AXILITE = 32'h2;
localparam P_AXILITE_SIZE = (C_AXI_DATA_WIDTH == 32) ? 3'b010 : 3'b011;
localparam P_INCR = 2'b01;
localparam P_DECERR = 2'b11;
localparam P_SLVERR = 2'b10;
localparam integer P_PROTECTION = 1;
localparam integer P_CONVERSION = 2;
wire s_awvalid_i;
wire s_arvalid_i;
wire s_wvalid_i ;
wire s_bready_i ;
wire s_rready_i ;
wire s_awready_i;
wire s_wready_i;
wire s_bvalid_i;
wire [C_AXI_ID_WIDTH-1:0] s_bid_i;
wire [1:0] s_bresp_i;
wire [C_AXI_BUSER_WIDTH-1:0] s_buser_i;
wire s_arready_i;
wire s_rvalid_i;
wire [C_AXI_ID_WIDTH-1:0] s_rid_i;
wire [1:0] s_rresp_i;
wire [C_AXI_RUSER_WIDTH-1:0] s_ruser_i;
wire [C_AXI_DATA_WIDTH-1:0] s_rdata_i;
wire s_rlast_i;
generate
if ((C_M_AXI_PROTOCOL == P_AXILITE) || (C_S_AXI_PROTOCOL == P_AXILITE)) begin : gen_axilite
assign m_axi_awid = 0;
assign m_axi_awlen = 0;
assign m_axi_awsize = P_AXILITE_SIZE;
assign m_axi_awburst = P_INCR;
assign m_axi_awlock = 0;
assign m_axi_awcache = 0;
assign m_axi_awregion = 0;
assign m_axi_awqos = 0;
assign m_axi_awuser = 0;
assign m_axi_wid = 0;
assign m_axi_wlast = 1'b1;
assign m_axi_wuser = 0;
assign m_axi_arid = 0;
assign m_axi_arlen = 0;
assign m_axi_arsize = P_AXILITE_SIZE;
assign m_axi_arburst = P_INCR;
assign m_axi_arlock = 0;
assign m_axi_arcache = 0;
assign m_axi_arregion = 0;
assign m_axi_arqos = 0;
assign m_axi_aruser = 0;
if (((C_IGNORE_ID == 1) && (C_TRANSLATION_MODE != P_CONVERSION)) || (C_S_AXI_PROTOCOL == P_AXILITE)) begin : gen_axilite_passthru
assign m_axi_awaddr = s_axi_awaddr;
assign m_axi_awprot = s_axi_awprot;
assign m_axi_awvalid = s_awvalid_i;
assign s_awready_i = m_axi_awready;
assign m_axi_wdata = s_axi_wdata;
assign m_axi_wstrb = s_axi_wstrb;
assign m_axi_wvalid = s_wvalid_i;
assign s_wready_i = m_axi_wready;
assign s_bid_i = 0;
assign s_bresp_i = m_axi_bresp;
assign s_buser_i = 0;
assign s_bvalid_i = m_axi_bvalid;
assign m_axi_bready = s_bready_i;
assign m_axi_araddr = s_axi_araddr;
assign m_axi_arprot = s_axi_arprot;
assign m_axi_arvalid = s_arvalid_i;
assign s_arready_i = m_axi_arready;
assign s_rid_i = 0;
assign s_rdata_i = m_axi_rdata;
assign s_rresp_i = m_axi_rresp;
assign s_rlast_i = 1'b1;
assign s_ruser_i = 0;
assign s_rvalid_i = m_axi_rvalid;
assign m_axi_rready = s_rready_i;
end else if (C_TRANSLATION_MODE == P_CONVERSION) begin : gen_b2s_conv
assign s_buser_i = {C_AXI_BUSER_WIDTH{1'b0}};
assign s_ruser_i = {C_AXI_RUSER_WIDTH{1'b0}};
axi_protocol_converter_v2_1_b2s #(
.C_S_AXI_PROTOCOL (C_S_AXI_PROTOCOL),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_SUPPORTS_WRITE (C_AXI_SUPPORTS_WRITE),
.C_AXI_SUPPORTS_READ (C_AXI_SUPPORTS_READ)
) axilite_b2s (
.aresetn (aresetn),
.aclk (aclk),
.s_axi_awid (s_axi_awid),
.s_axi_awaddr (s_axi_awaddr),
.s_axi_awlen (s_axi_awlen),
.s_axi_awsize (s_axi_awsize),
.s_axi_awburst (s_axi_awburst),
.s_axi_awprot (s_axi_awprot),
.s_axi_awvalid (s_awvalid_i),
.s_axi_awready (s_awready_i),
.s_axi_wdata (s_axi_wdata),
.s_axi_wstrb (s_axi_wstrb),
.s_axi_wlast (s_axi_wlast),
.s_axi_wvalid (s_wvalid_i),
.s_axi_wready (s_wready_i),
.s_axi_bid (s_bid_i),
.s_axi_bresp (s_bresp_i),
.s_axi_bvalid (s_bvalid_i),
.s_axi_bready (s_bready_i),
.s_axi_arid (s_axi_arid),
.s_axi_araddr (s_axi_araddr),
.s_axi_arlen (s_axi_arlen),
.s_axi_arsize (s_axi_arsize),
.s_axi_arburst (s_axi_arburst),
.s_axi_arprot (s_axi_arprot),
.s_axi_arvalid (s_arvalid_i),
.s_axi_arready (s_arready_i),
.s_axi_rid (s_rid_i),
.s_axi_rdata (s_rdata_i),
.s_axi_rresp (s_rresp_i),
.s_axi_rlast (s_rlast_i),
.s_axi_rvalid (s_rvalid_i),
.s_axi_rready (s_rready_i),
.m_axi_awaddr (m_axi_awaddr),
.m_axi_awprot (m_axi_awprot),
.m_axi_awvalid (m_axi_awvalid),
.m_axi_awready (m_axi_awready),
.m_axi_wdata (m_axi_wdata),
.m_axi_wstrb (m_axi_wstrb),
.m_axi_wvalid (m_axi_wvalid),
.m_axi_wready (m_axi_wready),
.m_axi_bresp (m_axi_bresp),
.m_axi_bvalid (m_axi_bvalid),
.m_axi_bready (m_axi_bready),
.m_axi_araddr (m_axi_araddr),
.m_axi_arprot (m_axi_arprot),
.m_axi_arvalid (m_axi_arvalid),
.m_axi_arready (m_axi_arready),
.m_axi_rdata (m_axi_rdata),
.m_axi_rresp (m_axi_rresp),
.m_axi_rvalid (m_axi_rvalid),
.m_axi_rready (m_axi_rready)
);
end else begin : gen_axilite_conv
axi_protocol_converter_v2_1_axilite_conv #(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_SUPPORTS_WRITE (C_AXI_SUPPORTS_WRITE),
.C_AXI_SUPPORTS_READ (C_AXI_SUPPORTS_READ),
.C_AXI_RUSER_WIDTH (C_AXI_RUSER_WIDTH),
.C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH)
) axilite_conv_inst (
.ARESETN (aresetn),
.ACLK (aclk),
.S_AXI_AWID (s_axi_awid),
.S_AXI_AWADDR (s_axi_awaddr),
.S_AXI_AWPROT (s_axi_awprot),
.S_AXI_AWVALID (s_awvalid_i),
.S_AXI_AWREADY (s_awready_i),
.S_AXI_WDATA (s_axi_wdata),
.S_AXI_WSTRB (s_axi_wstrb),
.S_AXI_WVALID (s_wvalid_i),
.S_AXI_WREADY (s_wready_i),
.S_AXI_BID (s_bid_i),
.S_AXI_BRESP (s_bresp_i),
.S_AXI_BUSER (s_buser_i),
.S_AXI_BVALID (s_bvalid_i),
.S_AXI_BREADY (s_bready_i),
.S_AXI_ARID (s_axi_arid),
.S_AXI_ARADDR (s_axi_araddr),
.S_AXI_ARPROT (s_axi_arprot),
.S_AXI_ARVALID (s_arvalid_i),
.S_AXI_ARREADY (s_arready_i),
.S_AXI_RID (s_rid_i),
.S_AXI_RDATA (s_rdata_i),
.S_AXI_RRESP (s_rresp_i),
.S_AXI_RLAST (s_rlast_i),
.S_AXI_RUSER (s_ruser_i),
.S_AXI_RVALID (s_rvalid_i),
.S_AXI_RREADY (s_rready_i),
.M_AXI_AWADDR (m_axi_awaddr),
.M_AXI_AWPROT (m_axi_awprot),
.M_AXI_AWVALID (m_axi_awvalid),
.M_AXI_AWREADY (m_axi_awready),
.M_AXI_WDATA (m_axi_wdata),
.M_AXI_WSTRB (m_axi_wstrb),
.M_AXI_WVALID (m_axi_wvalid),
.M_AXI_WREADY (m_axi_wready),
.M_AXI_BRESP (m_axi_bresp),
.M_AXI_BVALID (m_axi_bvalid),
.M_AXI_BREADY (m_axi_bready),
.M_AXI_ARADDR (m_axi_araddr),
.M_AXI_ARPROT (m_axi_arprot),
.M_AXI_ARVALID (m_axi_arvalid),
.M_AXI_ARREADY (m_axi_arready),
.M_AXI_RDATA (m_axi_rdata),
.M_AXI_RRESP (m_axi_rresp),
.M_AXI_RVALID (m_axi_rvalid),
.M_AXI_RREADY (m_axi_rready)
);
end
end else if ((C_M_AXI_PROTOCOL == P_AXI3) && (C_S_AXI_PROTOCOL == P_AXI4)) begin : gen_axi4_axi3
axi_protocol_converter_v2_1_axi3_conv #(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_SUPPORTS_USER_SIGNALS (C_AXI_SUPPORTS_USER_SIGNALS),
.C_AXI_AWUSER_WIDTH (C_AXI_AWUSER_WIDTH),
.C_AXI_ARUSER_WIDTH (C_AXI_ARUSER_WIDTH),
.C_AXI_WUSER_WIDTH (C_AXI_WUSER_WIDTH),
.C_AXI_RUSER_WIDTH (C_AXI_RUSER_WIDTH),
.C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH),
.C_AXI_SUPPORTS_WRITE (C_AXI_SUPPORTS_WRITE),
.C_AXI_SUPPORTS_READ (C_AXI_SUPPORTS_READ),
.C_SUPPORT_SPLITTING ((C_TRANSLATION_MODE == P_CONVERSION) ? 1 : 0)
) axi3_conv_inst (
.ARESETN (aresetn),
.ACLK (aclk),
.S_AXI_AWID (s_axi_awid),
.S_AXI_AWADDR (s_axi_awaddr),
.S_AXI_AWLEN (s_axi_awlen),
.S_AXI_AWSIZE (s_axi_awsize),
.S_AXI_AWBURST (s_axi_awburst),
.S_AXI_AWLOCK (s_axi_awlock),
.S_AXI_AWCACHE (s_axi_awcache),
.S_AXI_AWPROT (s_axi_awprot),
.S_AXI_AWQOS (s_axi_awqos),
.S_AXI_AWUSER (s_axi_awuser),
.S_AXI_AWVALID (s_awvalid_i),
.S_AXI_AWREADY (s_awready_i),
.S_AXI_WDATA (s_axi_wdata),
.S_AXI_WSTRB (s_axi_wstrb),
.S_AXI_WLAST (s_axi_wlast),
.S_AXI_WUSER (s_axi_wuser),
.S_AXI_WVALID (s_wvalid_i),
.S_AXI_WREADY (s_wready_i),
.S_AXI_BID (s_bid_i),
.S_AXI_BRESP (s_bresp_i),
.S_AXI_BUSER (s_buser_i),
.S_AXI_BVALID (s_bvalid_i),
.S_AXI_BREADY (s_bready_i),
.S_AXI_ARID (s_axi_arid),
.S_AXI_ARADDR (s_axi_araddr),
.S_AXI_ARLEN (s_axi_arlen),
.S_AXI_ARSIZE (s_axi_arsize),
.S_AXI_ARBURST (s_axi_arburst),
.S_AXI_ARLOCK (s_axi_arlock),
.S_AXI_ARCACHE (s_axi_arcache),
.S_AXI_ARPROT (s_axi_arprot),
.S_AXI_ARQOS (s_axi_arqos),
.S_AXI_ARUSER (s_axi_aruser),
.S_AXI_ARVALID (s_arvalid_i),
.S_AXI_ARREADY (s_arready_i),
.S_AXI_RID (s_rid_i),
.S_AXI_RDATA (s_rdata_i),
.S_AXI_RRESP (s_rresp_i),
.S_AXI_RLAST (s_rlast_i),
.S_AXI_RUSER (s_ruser_i),
.S_AXI_RVALID (s_rvalid_i),
.S_AXI_RREADY (s_rready_i),
.M_AXI_AWID (m_axi_awid),
.M_AXI_AWADDR (m_axi_awaddr),
.M_AXI_AWLEN (m_axi_awlen),
.M_AXI_AWSIZE (m_axi_awsize),
.M_AXI_AWBURST (m_axi_awburst),
.M_AXI_AWLOCK (m_axi_awlock),
.M_AXI_AWCACHE (m_axi_awcache),
.M_AXI_AWPROT (m_axi_awprot),
.M_AXI_AWQOS (m_axi_awqos),
.M_AXI_AWUSER (m_axi_awuser),
.M_AXI_AWVALID (m_axi_awvalid),
.M_AXI_AWREADY (m_axi_awready),
.M_AXI_WID (m_axi_wid),
.M_AXI_WDATA (m_axi_wdata),
.M_AXI_WSTRB (m_axi_wstrb),
.M_AXI_WLAST (m_axi_wlast),
.M_AXI_WUSER (m_axi_wuser),
.M_AXI_WVALID (m_axi_wvalid),
.M_AXI_WREADY (m_axi_wready),
.M_AXI_BID (m_axi_bid),
.M_AXI_BRESP (m_axi_bresp),
.M_AXI_BUSER (m_axi_buser),
.M_AXI_BVALID (m_axi_bvalid),
.M_AXI_BREADY (m_axi_bready),
.M_AXI_ARID (m_axi_arid),
.M_AXI_ARADDR (m_axi_araddr),
.M_AXI_ARLEN (m_axi_arlen),
.M_AXI_ARSIZE (m_axi_arsize),
.M_AXI_ARBURST (m_axi_arburst),
.M_AXI_ARLOCK (m_axi_arlock),
.M_AXI_ARCACHE (m_axi_arcache),
.M_AXI_ARPROT (m_axi_arprot),
.M_AXI_ARQOS (m_axi_arqos),
.M_AXI_ARUSER (m_axi_aruser),
.M_AXI_ARVALID (m_axi_arvalid),
.M_AXI_ARREADY (m_axi_arready),
.M_AXI_RID (m_axi_rid),
.M_AXI_RDATA (m_axi_rdata),
.M_AXI_RRESP (m_axi_rresp),
.M_AXI_RLAST (m_axi_rlast),
.M_AXI_RUSER (m_axi_ruser),
.M_AXI_RVALID (m_axi_rvalid),
.M_AXI_RREADY (m_axi_rready)
);
assign m_axi_awregion = 0;
assign m_axi_arregion = 0;
end else if ((C_S_AXI_PROTOCOL == P_AXI3) && (C_M_AXI_PROTOCOL == P_AXI4)) begin : gen_axi3_axi4
assign m_axi_awid = s_axi_awid;
assign m_axi_awaddr = s_axi_awaddr;
assign m_axi_awlen = {4'h0, s_axi_awlen[3:0]};
assign m_axi_awsize = s_axi_awsize;
assign m_axi_awburst = s_axi_awburst;
assign m_axi_awlock = s_axi_awlock[0];
assign m_axi_awcache = s_axi_awcache;
assign m_axi_awprot = s_axi_awprot;
assign m_axi_awregion = 4'h0;
assign m_axi_awqos = s_axi_awqos;
assign m_axi_awuser = s_axi_awuser;
assign m_axi_awvalid = s_awvalid_i;
assign s_awready_i = m_axi_awready;
assign m_axi_wid = {C_AXI_ID_WIDTH{1'b0}} ;
assign m_axi_wdata = s_axi_wdata;
assign m_axi_wstrb = s_axi_wstrb;
assign m_axi_wlast = s_axi_wlast;
assign m_axi_wuser = s_axi_wuser;
assign m_axi_wvalid = s_wvalid_i;
assign s_wready_i = m_axi_wready;
assign s_bid_i = m_axi_bid;
assign s_bresp_i = m_axi_bresp;
assign s_buser_i = m_axi_buser;
assign s_bvalid_i = m_axi_bvalid;
assign m_axi_bready = s_bready_i;
assign m_axi_arid = s_axi_arid;
assign m_axi_araddr = s_axi_araddr;
assign m_axi_arlen = {4'h0, s_axi_arlen[3:0]};
assign m_axi_arsize = s_axi_arsize;
assign m_axi_arburst = s_axi_arburst;
assign m_axi_arlock = s_axi_arlock[0];
assign m_axi_arcache = s_axi_arcache;
assign m_axi_arprot = s_axi_arprot;
assign m_axi_arregion = 4'h0;
assign m_axi_arqos = s_axi_arqos;
assign m_axi_aruser = s_axi_aruser;
assign m_axi_arvalid = s_arvalid_i;
assign s_arready_i = m_axi_arready;
assign s_rid_i = m_axi_rid;
assign s_rdata_i = m_axi_rdata;
assign s_rresp_i = m_axi_rresp;
assign s_rlast_i = m_axi_rlast;
assign s_ruser_i = m_axi_ruser;
assign s_rvalid_i = m_axi_rvalid;
assign m_axi_rready = s_rready_i;
end else begin :gen_no_conv
assign m_axi_awid = s_axi_awid;
assign m_axi_awaddr = s_axi_awaddr;
assign m_axi_awlen = s_axi_awlen;
assign m_axi_awsize = s_axi_awsize;
assign m_axi_awburst = s_axi_awburst;
assign m_axi_awlock = s_axi_awlock;
assign m_axi_awcache = s_axi_awcache;
assign m_axi_awprot = s_axi_awprot;
assign m_axi_awregion = s_axi_awregion;
assign m_axi_awqos = s_axi_awqos;
assign m_axi_awuser = s_axi_awuser;
assign m_axi_awvalid = s_awvalid_i;
assign s_awready_i = m_axi_awready;
assign m_axi_wid = s_axi_wid;
assign m_axi_wdata = s_axi_wdata;
assign m_axi_wstrb = s_axi_wstrb;
assign m_axi_wlast = s_axi_wlast;
assign m_axi_wuser = s_axi_wuser;
assign m_axi_wvalid = s_wvalid_i;
assign s_wready_i = m_axi_wready;
assign s_bid_i = m_axi_bid;
assign s_bresp_i = m_axi_bresp;
assign s_buser_i = m_axi_buser;
assign s_bvalid_i = m_axi_bvalid;
assign m_axi_bready = s_bready_i;
assign m_axi_arid = s_axi_arid;
assign m_axi_araddr = s_axi_araddr;
assign m_axi_arlen = s_axi_arlen;
assign m_axi_arsize = s_axi_arsize;
assign m_axi_arburst = s_axi_arburst;
assign m_axi_arlock = s_axi_arlock;
assign m_axi_arcache = s_axi_arcache;
assign m_axi_arprot = s_axi_arprot;
assign m_axi_arregion = s_axi_arregion;
assign m_axi_arqos = s_axi_arqos;
assign m_axi_aruser = s_axi_aruser;
assign m_axi_arvalid = s_arvalid_i;
assign s_arready_i = m_axi_arready;
assign s_rid_i = m_axi_rid;
assign s_rdata_i = m_axi_rdata;
assign s_rresp_i = m_axi_rresp;
assign s_rlast_i = m_axi_rlast;
assign s_ruser_i = m_axi_ruser;
assign s_rvalid_i = m_axi_rvalid;
assign m_axi_rready = s_rready_i;
end
if ((C_TRANSLATION_MODE == P_PROTECTION) &&
(((C_S_AXI_PROTOCOL != P_AXILITE) && (C_M_AXI_PROTOCOL == P_AXILITE)) ||
((C_S_AXI_PROTOCOL == P_AXI4) && (C_M_AXI_PROTOCOL == P_AXI3)))) begin : gen_err_detect
wire e_awvalid;
reg e_awvalid_r;
wire e_arvalid;
reg e_arvalid_r;
wire e_wvalid;
wire e_bvalid;
wire e_rvalid;
reg e_awready;
reg e_arready;
wire e_wready;
reg [C_AXI_ID_WIDTH-1:0] e_awid;
reg [C_AXI_ID_WIDTH-1:0] e_arid;
reg [8-1:0] e_arlen;
wire [C_AXI_ID_WIDTH-1:0] e_bid;
wire [C_AXI_ID_WIDTH-1:0] e_rid;
wire e_rlast;
wire w_err;
wire r_err;
wire busy_aw;
wire busy_w;
wire busy_ar;
wire aw_push;
wire aw_pop;
wire w_pop;
wire ar_push;
wire ar_pop;
reg s_awvalid_pending;
reg s_awvalid_en;
reg s_arvalid_en;
reg s_awready_en;
reg s_arready_en;
reg [4:0] aw_cnt;
reg [4:0] ar_cnt;
reg [4:0] w_cnt;
reg w_borrow;
reg err_busy_w;
reg err_busy_r;
assign w_err = (C_M_AXI_PROTOCOL == P_AXILITE) ? (s_axi_awlen != 0) : ((s_axi_awlen>>4) != 0);
assign r_err = (C_M_AXI_PROTOCOL == P_AXILITE) ? (s_axi_arlen != 0) : ((s_axi_arlen>>4) != 0);
assign s_awvalid_i = s_axi_awvalid & s_awvalid_en & ~w_err;
assign e_awvalid = e_awvalid_r & ~busy_aw & ~busy_w;
assign s_arvalid_i = s_axi_arvalid & s_arvalid_en & ~r_err;
assign e_arvalid = e_arvalid_r & ~busy_ar ;
assign s_wvalid_i = s_axi_wvalid & (busy_w | (s_awvalid_pending & ~w_borrow));
assign e_wvalid = s_axi_wvalid & err_busy_w;
assign s_bready_i = s_axi_bready & busy_aw;
assign s_rready_i = s_axi_rready & busy_ar;
assign s_axi_awready = (s_awready_i & s_awready_en) | e_awready;
assign s_axi_wready = (s_wready_i & (busy_w | (s_awvalid_pending & ~w_borrow))) | e_wready;
assign s_axi_bvalid = (s_bvalid_i & busy_aw) | e_bvalid;
assign s_axi_bid = err_busy_w ? e_bid : s_bid_i;
assign s_axi_bresp = err_busy_w ? P_SLVERR : s_bresp_i;
assign s_axi_buser = err_busy_w ? {C_AXI_BUSER_WIDTH{1'b0}} : s_buser_i;
assign s_axi_arready = (s_arready_i & s_arready_en) | e_arready;
assign s_axi_rvalid = (s_rvalid_i & busy_ar) | e_rvalid;
assign s_axi_rid = err_busy_r ? e_rid : s_rid_i;
assign s_axi_rresp = err_busy_r ? P_SLVERR : s_rresp_i;
assign s_axi_ruser = err_busy_r ? {C_AXI_RUSER_WIDTH{1'b0}} : s_ruser_i;
assign s_axi_rdata = err_busy_r ? {C_AXI_DATA_WIDTH{1'b0}} : s_rdata_i;
assign s_axi_rlast = err_busy_r ? e_rlast : s_rlast_i;
assign busy_aw = (aw_cnt != 0);
assign busy_w = (w_cnt != 0);
assign busy_ar = (ar_cnt != 0);
assign aw_push = s_awvalid_i & s_awready_i & s_awready_en;
assign aw_pop = s_bvalid_i & s_bready_i;
assign w_pop = s_wvalid_i & s_wready_i & s_axi_wlast;
assign ar_push = s_arvalid_i & s_arready_i & s_arready_en;
assign ar_pop = s_rvalid_i & s_rready_i & s_rlast_i;
always @(posedge aclk) begin
if (~aresetn) begin
s_awvalid_en <= 1'b0;
s_arvalid_en <= 1'b0;
s_awready_en <= 1'b0;
s_arready_en <= 1'b0;
e_awvalid_r <= 1'b0;
e_arvalid_r <= 1'b0;
e_awready <= 1'b0;
e_arready <= 1'b0;
aw_cnt <= 0;
w_cnt <= 0;
ar_cnt <= 0;
err_busy_w <= 1'b0;
err_busy_r <= 1'b0;
w_borrow <= 1'b0;
s_awvalid_pending <= 1'b0;
end else begin
e_awready <= 1'b0; // One-cycle pulse
if (e_bvalid & s_axi_bready) begin
s_awvalid_en <= 1'b1;
s_awready_en <= 1'b1;
err_busy_w <= 1'b0;
end else if (e_awvalid) begin
e_awvalid_r <= 1'b0;
err_busy_w <= 1'b1;
end else if (s_axi_awvalid & w_err & ~e_awvalid_r & ~err_busy_w) begin
e_awvalid_r <= 1'b1;
e_awready <= ~(s_awready_i & s_awvalid_en); // 1-cycle pulse if awready not already asserted
s_awvalid_en <= 1'b0;
s_awready_en <= 1'b0;
end else if ((&aw_cnt) | (&w_cnt) | aw_push) begin
s_awvalid_en <= 1'b0;
s_awready_en <= 1'b0;
end else if (~err_busy_w & ~e_awvalid_r & ~(s_axi_awvalid & w_err)) begin
s_awvalid_en <= 1'b1;
s_awready_en <= 1'b1;
end
if (aw_push & ~aw_pop) begin
aw_cnt <= aw_cnt + 1;
end else if (~aw_push & aw_pop & (|aw_cnt)) begin
aw_cnt <= aw_cnt - 1;
end
if (aw_push) begin
if (~w_pop & ~w_borrow) begin
w_cnt <= w_cnt + 1;
end
w_borrow <= 1'b0;
end else if (~aw_push & w_pop) begin
if (|w_cnt) begin
w_cnt <= w_cnt - 1;
end else begin
w_borrow <= 1'b1;
end
end
s_awvalid_pending <= s_awvalid_i & ~s_awready_i;
e_arready <= 1'b0; // One-cycle pulse
if (e_rvalid & s_axi_rready & e_rlast) begin
s_arvalid_en <= 1'b1;
s_arready_en <= 1'b1;
err_busy_r <= 1'b0;
end else if (e_arvalid) begin
e_arvalid_r <= 1'b0;
err_busy_r <= 1'b1;
end else if (s_axi_arvalid & r_err & ~e_arvalid_r & ~err_busy_r) begin
e_arvalid_r <= 1'b1;
e_arready <= ~(s_arready_i & s_arvalid_en); // 1-cycle pulse if arready not already asserted
s_arvalid_en <= 1'b0;
s_arready_en <= 1'b0;
end else if ((&ar_cnt) | ar_push) begin
s_arvalid_en <= 1'b0;
s_arready_en <= 1'b0;
end else if (~err_busy_r & ~e_arvalid_r & ~(s_axi_arvalid & r_err)) begin
s_arvalid_en <= 1'b1;
s_arready_en <= 1'b1;
end
if (ar_push & ~ar_pop) begin
ar_cnt <= ar_cnt + 1;
end else if (~ar_push & ar_pop & (|ar_cnt)) begin
ar_cnt <= ar_cnt - 1;
end
end
end
always @(posedge aclk) begin
if (s_axi_awvalid & ~err_busy_w & ~e_awvalid_r ) begin
e_awid <= s_axi_awid;
end
if (s_axi_arvalid & ~err_busy_r & ~e_arvalid_r ) begin
e_arid <= s_axi_arid;
e_arlen <= s_axi_arlen;
end
end
axi_protocol_converter_v2_1_decerr_slave #
(
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_RUSER_WIDTH (C_AXI_RUSER_WIDTH),
.C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH),
.C_AXI_PROTOCOL (C_S_AXI_PROTOCOL),
.C_RESP (P_SLVERR),
.C_IGNORE_ID (C_IGNORE_ID)
)
decerr_slave_inst
(
.ACLK (aclk),
.ARESETN (aresetn),
.S_AXI_AWID (e_awid),
.S_AXI_AWVALID (e_awvalid),
.S_AXI_AWREADY (),
.S_AXI_WLAST (s_axi_wlast),
.S_AXI_WVALID (e_wvalid),
.S_AXI_WREADY (e_wready),
.S_AXI_BID (e_bid),
.S_AXI_BRESP (),
.S_AXI_BUSER (),
.S_AXI_BVALID (e_bvalid),
.S_AXI_BREADY (s_axi_bready),
.S_AXI_ARID (e_arid),
.S_AXI_ARLEN (e_arlen),
.S_AXI_ARVALID (e_arvalid),
.S_AXI_ARREADY (),
.S_AXI_RID (e_rid),
.S_AXI_RDATA (),
.S_AXI_RRESP (),
.S_AXI_RUSER (),
.S_AXI_RLAST (e_rlast),
.S_AXI_RVALID (e_rvalid),
.S_AXI_RREADY (s_axi_rready)
);
end else begin : gen_no_err_detect
assign s_awvalid_i = s_axi_awvalid;
assign s_arvalid_i = s_axi_arvalid;
assign s_wvalid_i = s_axi_wvalid;
assign s_bready_i = s_axi_bready;
assign s_rready_i = s_axi_rready;
assign s_axi_awready = s_awready_i;
assign s_axi_wready = s_wready_i;
assign s_axi_bvalid = s_bvalid_i;
assign s_axi_bid = s_bid_i;
assign s_axi_bresp = s_bresp_i;
assign s_axi_buser = s_buser_i;
assign s_axi_arready = s_arready_i;
assign s_axi_rvalid = s_rvalid_i;
assign s_axi_rid = s_rid_i;
assign s_axi_rresp = s_rresp_i;
assign s_axi_ruser = s_ruser_i;
assign s_axi_rdata = s_rdata_i;
assign s_axi_rlast = s_rlast_i;
end // gen_err_detect
endgenerate
endmodule
`default_nettype wire
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__MUXB4TO1_TB_V
`define SKY130_FD_SC_HDLL__MUXB4TO1_TB_V
/**
* muxb4to1: Buffered 4-input multiplexer.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__muxb4to1.v"
module top();
// Inputs are registered
reg D;
reg S;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Z;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
S = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 S = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 D = 1'b1;
#160 S = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 D = 1'b0;
#280 S = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 S = 1'b1;
#480 D = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 S = 1'bx;
#600 D = 1'bx;
end
sky130_fd_sc_hdll__muxb4to1 dut (.D(D), .S(S), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Z(Z));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__MUXB4TO1_TB_V
|
///////////////////////////////////////////////////////////////////////////////
//
// File name: axi_protocol_converter_v2_1_b2s.v
//
// Description:
// To handle AXI4 transactions to external memory on Virtex-6 architectures
// requires a bridge to convert the AXI4 transactions to the memory
// controller(MC) user interface. The MC user interface has bidirectional
// data path and supports data width of 256/128/64/32 bits.
// The bridge is designed to allow AXI4 IP masters to communicate with
// the MC user interface.
//
//
// Specifications:
// AXI4 Slave Side:
// Configurable data width of 32, 64, 128, 256
// Read acceptance depth is:
// Write acceptance depth is:
//
// Structure:
// axi_protocol_converter_v2_1_b2s
// WRITE_BUNDLE
// aw_channel_0
// cmd_translator_0
// rd_cmd_fsm_0
// w_channel_0
// b_channel_0
// READ_BUNDLE
// ar_channel_0
// cmd_translator_0
// rd_cmd_fsm_0
// r_channel_0
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_b2s #(
parameter C_S_AXI_PROTOCOL = 0,
// Width of all master and slave ID signals.
// Range: >= 1.
parameter integer C_AXI_ID_WIDTH = 4,
parameter integer C_AXI_ADDR_WIDTH = 30,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_WRITE = 1,
parameter integer C_AXI_SUPPORTS_READ = 1
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// AXI Slave Interface
// Slave Interface System Signals
input wire aclk ,
input wire aresetn ,
// Slave Interface Write Address Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_awid ,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr ,
input wire [((C_S_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,
input wire [2:0] s_axi_awsize ,
input wire [1:0] s_axi_awburst ,
input wire [2:0] s_axi_awprot ,
input wire s_axi_awvalid ,
output wire s_axi_awready ,
// Slave Interface Write Data Ports
input wire [C_AXI_DATA_WIDTH-1:0] s_axi_wdata ,
input wire [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb ,
input wire s_axi_wlast ,
input wire s_axi_wvalid ,
output wire s_axi_wready ,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] s_axi_bid ,
output wire [1:0] s_axi_bresp ,
output wire s_axi_bvalid ,
input wire s_axi_bready ,
// Slave Interface Read Address Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_arid ,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr ,
input wire [((C_S_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,
input wire [2:0] s_axi_arsize ,
input wire [1:0] s_axi_arburst ,
input wire [2:0] s_axi_arprot ,
input wire s_axi_arvalid ,
output wire s_axi_arready ,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] s_axi_rid ,
output wire [C_AXI_DATA_WIDTH-1:0] s_axi_rdata ,
output wire [1:0] s_axi_rresp ,
output wire s_axi_rlast ,
output wire s_axi_rvalid ,
input wire s_axi_rready ,
// Slave Interface Write Address Ports
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr ,
output wire [2:0] m_axi_awprot ,
output wire m_axi_awvalid ,
input wire m_axi_awready ,
// Slave Interface Write Data Ports
output wire [C_AXI_DATA_WIDTH-1:0] m_axi_wdata ,
output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb ,
output wire m_axi_wvalid ,
input wire m_axi_wready ,
// Slave Interface Write Response Ports
input wire [1:0] m_axi_bresp ,
input wire m_axi_bvalid ,
output wire m_axi_bready ,
// Slave Interface Read Address Ports
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr ,
output wire [2:0] m_axi_arprot ,
output wire m_axi_arvalid ,
input wire m_axi_arready ,
// Slave Interface Read Data Ports
input wire [C_AXI_DATA_WIDTH-1:0] m_axi_rdata ,
input wire [1:0] m_axi_rresp ,
input wire m_axi_rvalid ,
output wire m_axi_rready
);
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
reg areset_d1;
always @(posedge aclk)
areset_d1 <= ~aresetn;
// AW/W/B channel internal communication
wire b_push;
wire [C_AXI_ID_WIDTH-1:0] b_awid;
wire [7:0] b_awlen;
wire b_full;
wire [C_AXI_ID_WIDTH-1:0] si_rs_awid;
wire [C_AXI_ADDR_WIDTH-1:0] si_rs_awaddr;
wire [8-1:0] si_rs_awlen;
wire [3-1:0] si_rs_awsize;
wire [2-1:0] si_rs_awburst;
wire [3-1:0] si_rs_awprot;
wire si_rs_awvalid;
wire si_rs_awready;
wire [C_AXI_DATA_WIDTH-1:0] si_rs_wdata;
wire [C_AXI_DATA_WIDTH/8-1:0] si_rs_wstrb;
wire si_rs_wlast;
wire si_rs_wvalid;
wire si_rs_wready;
wire [C_AXI_ID_WIDTH-1:0] si_rs_bid;
wire [2-1:0] si_rs_bresp;
wire si_rs_bvalid;
wire si_rs_bready;
wire [C_AXI_ID_WIDTH-1:0] si_rs_arid;
wire [C_AXI_ADDR_WIDTH-1:0] si_rs_araddr;
wire [8-1:0] si_rs_arlen;
wire [3-1:0] si_rs_arsize;
wire [2-1:0] si_rs_arburst;
wire [3-1:0] si_rs_arprot;
wire si_rs_arvalid;
wire si_rs_arready;
wire [C_AXI_ID_WIDTH-1:0] si_rs_rid;
wire [C_AXI_DATA_WIDTH-1:0] si_rs_rdata;
wire [2-1:0] si_rs_rresp;
wire si_rs_rlast;
wire si_rs_rvalid;
wire si_rs_rready;
wire [C_AXI_ADDR_WIDTH-1:0] rs_mi_awaddr;
wire rs_mi_awvalid;
wire rs_mi_awready;
wire [C_AXI_DATA_WIDTH-1:0] rs_mi_wdata;
wire [C_AXI_DATA_WIDTH/8-1:0] rs_mi_wstrb;
wire rs_mi_wvalid;
wire rs_mi_wready;
wire [2-1:0] rs_mi_bresp;
wire rs_mi_bvalid;
wire rs_mi_bready;
wire [C_AXI_ADDR_WIDTH-1:0] rs_mi_araddr;
wire rs_mi_arvalid;
wire rs_mi_arready;
wire [C_AXI_DATA_WIDTH-1:0] rs_mi_rdata;
wire [2-1:0] rs_mi_rresp;
wire rs_mi_rvalid;
wire rs_mi_rready;
axi_register_slice_v2_1_axi_register_slice #(
.C_AXI_PROTOCOL ( C_S_AXI_PROTOCOL ) ,
.C_AXI_ID_WIDTH ( C_AXI_ID_WIDTH ) ,
.C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH ) ,
.C_AXI_DATA_WIDTH ( C_AXI_DATA_WIDTH ) ,
.C_AXI_SUPPORTS_USER_SIGNALS ( 0 ) ,
.C_AXI_AWUSER_WIDTH ( 1 ) ,
.C_AXI_ARUSER_WIDTH ( 1 ) ,
.C_AXI_WUSER_WIDTH ( 1 ) ,
.C_AXI_RUSER_WIDTH ( 1 ) ,
.C_AXI_BUSER_WIDTH ( 1 ) ,
.C_REG_CONFIG_AW ( 1 ) ,
.C_REG_CONFIG_AR ( 1 ) ,
.C_REG_CONFIG_W ( 0 ) ,
.C_REG_CONFIG_R ( 1 ) ,
.C_REG_CONFIG_B ( 1 )
) SI_REG (
.aresetn ( aresetn ) ,
.aclk ( aclk ) ,
.s_axi_awid ( s_axi_awid ) ,
.s_axi_awaddr ( s_axi_awaddr ) ,
.s_axi_awlen ( s_axi_awlen ) ,
.s_axi_awsize ( s_axi_awsize ) ,
.s_axi_awburst ( s_axi_awburst ) ,
.s_axi_awlock ( {((C_S_AXI_PROTOCOL == 1) ? 2 : 1){1'b0}} ) ,
.s_axi_awcache ( 4'h0 ) ,
.s_axi_awprot ( s_axi_awprot ) ,
.s_axi_awqos ( 4'h0 ) ,
.s_axi_awuser ( 1'b0 ) ,
.s_axi_awvalid ( s_axi_awvalid ) ,
.s_axi_awready ( s_axi_awready ) ,
.s_axi_awregion ( 4'h0 ) ,
.s_axi_wid ( {C_AXI_ID_WIDTH{1'b0}} ) ,
.s_axi_wdata ( s_axi_wdata ) ,
.s_axi_wstrb ( s_axi_wstrb ) ,
.s_axi_wlast ( s_axi_wlast ) ,
.s_axi_wuser ( 1'b0 ) ,
.s_axi_wvalid ( s_axi_wvalid ) ,
.s_axi_wready ( s_axi_wready ) ,
.s_axi_bid ( s_axi_bid ) ,
.s_axi_bresp ( s_axi_bresp ) ,
.s_axi_buser ( ) ,
.s_axi_bvalid ( s_axi_bvalid ) ,
.s_axi_bready ( s_axi_bready ) ,
.s_axi_arid ( s_axi_arid ) ,
.s_axi_araddr ( s_axi_araddr ) ,
.s_axi_arlen ( s_axi_arlen ) ,
.s_axi_arsize ( s_axi_arsize ) ,
.s_axi_arburst ( s_axi_arburst ) ,
.s_axi_arlock ( {((C_S_AXI_PROTOCOL == 1) ? 2 : 1){1'b0}} ) ,
.s_axi_arcache ( 4'h0 ) ,
.s_axi_arprot ( s_axi_arprot ) ,
.s_axi_arqos ( 4'h0 ) ,
.s_axi_aruser ( 1'b0 ) ,
.s_axi_arvalid ( s_axi_arvalid ) ,
.s_axi_arready ( s_axi_arready ) ,
.s_axi_arregion ( 4'h0 ) ,
.s_axi_rid ( s_axi_rid ) ,
.s_axi_rdata ( s_axi_rdata ) ,
.s_axi_rresp ( s_axi_rresp ) ,
.s_axi_rlast ( s_axi_rlast ) ,
.s_axi_ruser ( ) ,
.s_axi_rvalid ( s_axi_rvalid ) ,
.s_axi_rready ( s_axi_rready ) ,
.m_axi_awid ( si_rs_awid ) ,
.m_axi_awaddr ( si_rs_awaddr ) ,
.m_axi_awlen ( si_rs_awlen[((C_S_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] ) ,
.m_axi_awsize ( si_rs_awsize ) ,
.m_axi_awburst ( si_rs_awburst ) ,
.m_axi_awlock ( ) ,
.m_axi_awcache ( ) ,
.m_axi_awprot ( si_rs_awprot ) ,
.m_axi_awqos ( ) ,
.m_axi_awuser ( ) ,
.m_axi_awvalid ( si_rs_awvalid ) ,
.m_axi_awready ( si_rs_awready ) ,
.m_axi_awregion ( ) ,
.m_axi_wid ( ) ,
.m_axi_wdata ( si_rs_wdata ) ,
.m_axi_wstrb ( si_rs_wstrb ) ,
.m_axi_wlast ( si_rs_wlast ) ,
.m_axi_wuser ( ) ,
.m_axi_wvalid ( si_rs_wvalid ) ,
.m_axi_wready ( si_rs_wready ) ,
.m_axi_bid ( si_rs_bid ) ,
.m_axi_bresp ( si_rs_bresp ) ,
.m_axi_buser ( 1'b0 ) ,
.m_axi_bvalid ( si_rs_bvalid ) ,
.m_axi_bready ( si_rs_bready ) ,
.m_axi_arid ( si_rs_arid ) ,
.m_axi_araddr ( si_rs_araddr ) ,
.m_axi_arlen ( si_rs_arlen[((C_S_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] ) ,
.m_axi_arsize ( si_rs_arsize ) ,
.m_axi_arburst ( si_rs_arburst ) ,
.m_axi_arlock ( ) ,
.m_axi_arcache ( ) ,
.m_axi_arprot ( si_rs_arprot ) ,
.m_axi_arqos ( ) ,
.m_axi_aruser ( ) ,
.m_axi_arvalid ( si_rs_arvalid ) ,
.m_axi_arready ( si_rs_arready ) ,
.m_axi_arregion ( ) ,
.m_axi_rid ( si_rs_rid ) ,
.m_axi_rdata ( si_rs_rdata ) ,
.m_axi_rresp ( si_rs_rresp ) ,
.m_axi_rlast ( si_rs_rlast ) ,
.m_axi_ruser ( 1'b0 ) ,
.m_axi_rvalid ( si_rs_rvalid ) ,
.m_axi_rready ( si_rs_rready )
);
generate
if (C_AXI_SUPPORTS_WRITE == 1) begin : WR
axi_protocol_converter_v2_1_b2s_aw_channel #
(
.C_ID_WIDTH ( C_AXI_ID_WIDTH ),
.C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH )
)
aw_channel_0
(
.clk ( aclk ) ,
.reset ( areset_d1 ) ,
.s_awid ( si_rs_awid ) ,
.s_awaddr ( si_rs_awaddr ) ,
.s_awlen ( (C_S_AXI_PROTOCOL == 1) ? {4'h0,si_rs_awlen[3:0]} : si_rs_awlen),
.s_awsize ( si_rs_awsize ) ,
.s_awburst ( si_rs_awburst ) ,
.s_awvalid ( si_rs_awvalid ) ,
.s_awready ( si_rs_awready ) ,
.m_awvalid ( rs_mi_awvalid ) ,
.m_awaddr ( rs_mi_awaddr ) ,
.m_awready ( rs_mi_awready ) ,
.b_push ( b_push ) ,
.b_awid ( b_awid ) ,
.b_awlen ( b_awlen ) ,
.b_full ( b_full )
);
axi_protocol_converter_v2_1_b2s_b_channel #
(
.C_ID_WIDTH ( C_AXI_ID_WIDTH )
)
b_channel_0
(
.clk ( aclk ) ,
.reset ( areset_d1 ) ,
.s_bid ( si_rs_bid ) ,
.s_bresp ( si_rs_bresp ) ,
.s_bvalid ( si_rs_bvalid ) ,
.s_bready ( si_rs_bready ) ,
.m_bready ( rs_mi_bready ) ,
.m_bvalid ( rs_mi_bvalid ) ,
.m_bresp ( rs_mi_bresp ) ,
.b_push ( b_push ) ,
.b_awid ( b_awid ) ,
.b_awlen ( b_awlen ) ,
.b_full ( b_full ) ,
.b_resp_rdy ( si_rs_awready )
);
assign rs_mi_wdata = si_rs_wdata;
assign rs_mi_wstrb = si_rs_wstrb;
assign rs_mi_wvalid = si_rs_wvalid;
assign si_rs_wready = rs_mi_wready;
end else begin : NO_WR
assign rs_mi_awaddr = {C_AXI_ADDR_WIDTH{1'b0}};
assign rs_mi_awvalid = 1'b0;
assign si_rs_awready = 1'b0;
assign rs_mi_wdata = {C_AXI_DATA_WIDTH{1'b0}};
assign rs_mi_wstrb = {C_AXI_DATA_WIDTH/8{1'b0}};
assign rs_mi_wvalid = 1'b0;
assign si_rs_wready = 1'b0;
assign rs_mi_bready = 1'b0;
assign si_rs_bvalid = 1'b0;
assign si_rs_bresp = 2'b00;
assign si_rs_bid = {C_AXI_ID_WIDTH{1'b0}};
end
endgenerate
// AR/R channel communication
wire r_push ;
wire [C_AXI_ID_WIDTH-1:0] r_arid ;
wire r_rlast ;
wire r_full ;
generate
if (C_AXI_SUPPORTS_READ == 1) begin : RD
axi_protocol_converter_v2_1_b2s_ar_channel #
(
.C_ID_WIDTH ( C_AXI_ID_WIDTH ),
.C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH )
)
ar_channel_0
(
.clk ( aclk ) ,
.reset ( areset_d1 ) ,
.s_arid ( si_rs_arid ) ,
.s_araddr ( si_rs_araddr ) ,
.s_arlen ( (C_S_AXI_PROTOCOL == 1) ? {4'h0,si_rs_arlen[3:0]} : si_rs_arlen),
.s_arsize ( si_rs_arsize ) ,
.s_arburst ( si_rs_arburst ) ,
.s_arvalid ( si_rs_arvalid ) ,
.s_arready ( si_rs_arready ) ,
.m_arvalid ( rs_mi_arvalid ) ,
.m_araddr ( rs_mi_araddr ) ,
.m_arready ( rs_mi_arready ) ,
.r_push ( r_push ) ,
.r_arid ( r_arid ) ,
.r_rlast ( r_rlast ) ,
.r_full ( r_full )
);
axi_protocol_converter_v2_1_b2s_r_channel #
(
.C_ID_WIDTH ( C_AXI_ID_WIDTH ),
.C_DATA_WIDTH ( C_AXI_DATA_WIDTH )
)
r_channel_0
(
.clk ( aclk ) ,
.reset ( areset_d1 ) ,
.s_rid ( si_rs_rid ) ,
.s_rdata ( si_rs_rdata ) ,
.s_rresp ( si_rs_rresp ) ,
.s_rlast ( si_rs_rlast ) ,
.s_rvalid ( si_rs_rvalid ) ,
.s_rready ( si_rs_rready ) ,
.m_rvalid ( rs_mi_rvalid ) ,
.m_rready ( rs_mi_rready ) ,
.m_rdata ( rs_mi_rdata ) ,
.m_rresp ( rs_mi_rresp ) ,
.r_push ( r_push ) ,
.r_full ( r_full ) ,
.r_arid ( r_arid ) ,
.r_rlast ( r_rlast )
);
end else begin : NO_RD
assign rs_mi_araddr = {C_AXI_ADDR_WIDTH{1'b0}};
assign rs_mi_arvalid = 1'b0;
assign si_rs_arready = 1'b0;
assign si_rs_rlast = 1'b1;
assign si_rs_rdata = {C_AXI_DATA_WIDTH{1'b0}};
assign si_rs_rvalid = 1'b0;
assign si_rs_rresp = 2'b00;
assign si_rs_rid = {C_AXI_ID_WIDTH{1'b0}};
assign rs_mi_rready = 1'b0;
end
endgenerate
axi_register_slice_v2_1_axi_register_slice #(
.C_AXI_PROTOCOL ( 2 ) ,
.C_AXI_ID_WIDTH ( 1 ) ,
.C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH ) ,
.C_AXI_DATA_WIDTH ( C_AXI_DATA_WIDTH ) ,
.C_AXI_SUPPORTS_USER_SIGNALS ( 0 ) ,
.C_AXI_AWUSER_WIDTH ( 1 ) ,
.C_AXI_ARUSER_WIDTH ( 1 ) ,
.C_AXI_WUSER_WIDTH ( 1 ) ,
.C_AXI_RUSER_WIDTH ( 1 ) ,
.C_AXI_BUSER_WIDTH ( 1 ) ,
.C_REG_CONFIG_AW ( 0 ) ,
.C_REG_CONFIG_AR ( 0 ) ,
.C_REG_CONFIG_W ( 0 ) ,
.C_REG_CONFIG_R ( 0 ) ,
.C_REG_CONFIG_B ( 0 )
) MI_REG (
.aresetn ( aresetn ) ,
.aclk ( aclk ) ,
.s_axi_awid ( 1'b0 ) ,
.s_axi_awaddr ( rs_mi_awaddr ) ,
.s_axi_awlen ( 8'h00 ) ,
.s_axi_awsize ( 3'b000 ) ,
.s_axi_awburst ( 2'b01 ) ,
.s_axi_awlock ( 1'b0 ) ,
.s_axi_awcache ( 4'h0 ) ,
.s_axi_awprot ( si_rs_awprot ) ,
.s_axi_awqos ( 4'h0 ) ,
.s_axi_awuser ( 1'b0 ) ,
.s_axi_awvalid ( rs_mi_awvalid ) ,
.s_axi_awready ( rs_mi_awready ) ,
.s_axi_awregion ( 4'h0 ) ,
.s_axi_wid ( 1'b0 ) ,
.s_axi_wdata ( rs_mi_wdata ) ,
.s_axi_wstrb ( rs_mi_wstrb ) ,
.s_axi_wlast ( 1'b1 ) ,
.s_axi_wuser ( 1'b0 ) ,
.s_axi_wvalid ( rs_mi_wvalid ) ,
.s_axi_wready ( rs_mi_wready ) ,
.s_axi_bid ( ) ,
.s_axi_bresp ( rs_mi_bresp ) ,
.s_axi_buser ( ) ,
.s_axi_bvalid ( rs_mi_bvalid ) ,
.s_axi_bready ( rs_mi_bready ) ,
.s_axi_arid ( 1'b0 ) ,
.s_axi_araddr ( rs_mi_araddr ) ,
.s_axi_arlen ( 8'h00 ) ,
.s_axi_arsize ( 3'b000 ) ,
.s_axi_arburst ( 2'b01 ) ,
.s_axi_arlock ( 1'b0 ) ,
.s_axi_arcache ( 4'h0 ) ,
.s_axi_arprot ( si_rs_arprot ) ,
.s_axi_arqos ( 4'h0 ) ,
.s_axi_aruser ( 1'b0 ) ,
.s_axi_arvalid ( rs_mi_arvalid ) ,
.s_axi_arready ( rs_mi_arready ) ,
.s_axi_arregion ( 4'h0 ) ,
.s_axi_rid ( ) ,
.s_axi_rdata ( rs_mi_rdata ) ,
.s_axi_rresp ( rs_mi_rresp ) ,
.s_axi_rlast ( ) ,
.s_axi_ruser ( ) ,
.s_axi_rvalid ( rs_mi_rvalid ) ,
.s_axi_rready ( rs_mi_rready ) ,
.m_axi_awid ( ) ,
.m_axi_awaddr ( m_axi_awaddr ) ,
.m_axi_awlen ( ) ,
.m_axi_awsize ( ) ,
.m_axi_awburst ( ) ,
.m_axi_awlock ( ) ,
.m_axi_awcache ( ) ,
.m_axi_awprot ( m_axi_awprot ) ,
.m_axi_awqos ( ) ,
.m_axi_awuser ( ) ,
.m_axi_awvalid ( m_axi_awvalid ) ,
.m_axi_awready ( m_axi_awready ) ,
.m_axi_awregion ( ) ,
.m_axi_wid ( ) ,
.m_axi_wdata ( m_axi_wdata ) ,
.m_axi_wstrb ( m_axi_wstrb ) ,
.m_axi_wlast ( ) ,
.m_axi_wuser ( ) ,
.m_axi_wvalid ( m_axi_wvalid ) ,
.m_axi_wready ( m_axi_wready ) ,
.m_axi_bid ( 1'b0 ) ,
.m_axi_bresp ( m_axi_bresp ) ,
.m_axi_buser ( 1'b0 ) ,
.m_axi_bvalid ( m_axi_bvalid ) ,
.m_axi_bready ( m_axi_bready ) ,
.m_axi_arid ( ) ,
.m_axi_araddr ( m_axi_araddr ) ,
.m_axi_arlen ( ) ,
.m_axi_arsize ( ) ,
.m_axi_arburst ( ) ,
.m_axi_arlock ( ) ,
.m_axi_arcache ( ) ,
.m_axi_arprot ( m_axi_arprot ) ,
.m_axi_arqos ( ) ,
.m_axi_aruser ( ) ,
.m_axi_arvalid ( m_axi_arvalid ) ,
.m_axi_arready ( m_axi_arready ) ,
.m_axi_arregion ( ) ,
.m_axi_rid ( 1'b0 ) ,
.m_axi_rdata ( m_axi_rdata ) ,
.m_axi_rresp ( m_axi_rresp ) ,
.m_axi_rlast ( 1'b1 ) ,
.m_axi_ruser ( 1'b0 ) ,
.m_axi_rvalid ( m_axi_rvalid ) ,
.m_axi_rready ( m_axi_rready )
);
endmodule
`default_nettype wire
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Thu Feb 02 03:23:40 2017
// Host : TheMosass-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_axi_intc_0_0_sim_netlist.v
// Design : design_1_axi_intc_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder
(p_15_in,
p_17_in,
\mer_int_reg[0] ,
D,
ip2bus_wrack_prev2,
ip2bus_rdack_prev2,
Or128_vec2stdlogic19_out,
\mer_int_reg[0]_0 ,
\mer_int_reg[1] ,
\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ,
\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0] ,
\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0] ,
ip2bus_wrack_int_d1_reg,
Q,
s_axi_aclk,
is_write_reg,
ip2bus_wrack,
s_axi_aresetn,
ip2bus_rdack,
is_read,
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ,
\bus2ip_addr_i_reg[8] ,
\IPR_GEN.ipr_reg[0] ,
\bus2ip_addr_i_reg[3] ,
\bus2ip_addr_i_reg[2] ,
\IVR_GEN.ivr_reg[0] ,
ip2bus_wrack_int_d1,
ip2bus_rdack_int_d1,
s_axi_wdata,
\mer_int_reg[0]_1 ,
p_0_in,
sie,
cie,
\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0]_0 ,
bus2ip_rnw_i_reg);
output p_15_in;
output p_17_in;
output \mer_int_reg[0] ;
output [2:0]D;
output ip2bus_wrack_prev2;
output ip2bus_rdack_prev2;
output Or128_vec2stdlogic19_out;
output \mer_int_reg[0]_0 ;
output \mer_int_reg[1] ;
output \SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ;
output \CIE_GEN.CIE_BIT_GEN[0].cie_reg[0] ;
output \REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0] ;
output ip2bus_wrack_int_d1_reg;
input Q;
input s_axi_aclk;
input is_write_reg;
input ip2bus_wrack;
input s_axi_aresetn;
input ip2bus_rdack;
input is_read;
input [3:0]\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ;
input [6:0]\bus2ip_addr_i_reg[8] ;
input \IPR_GEN.ipr_reg[0] ;
input \bus2ip_addr_i_reg[3] ;
input \bus2ip_addr_i_reg[2] ;
input \IVR_GEN.ivr_reg[0] ;
input ip2bus_wrack_int_d1;
input ip2bus_rdack_int_d1;
input [1:0]s_axi_wdata;
input \mer_int_reg[0]_1 ;
input p_0_in;
input sie;
input cie;
input \REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0]_0 ;
input bus2ip_rnw_i_reg;
wire Bus_RNW_reg_i_1_n_0;
wire \CIE_GEN.CIE_BIT_GEN[0].cie_reg[0] ;
wire [2:0]D;
wire \GEN_BKEND_CE_REGISTERS[0].ce_out_i[0]_i_1_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_3_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16] ;
wire \GEN_BKEND_CE_REGISTERS[2].ce_out_i[2]_i_1_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_1_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[5].ce_out_i[5]_i_1_n_0 ;
wire [3:0]\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ;
wire \IPR_GEN.ipr_reg[0] ;
wire \IVR_GEN.ivr_reg[0] ;
wire Or128_vec2stdlogic19_out;
wire Q;
wire \REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0] ;
wire \REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0]_0 ;
wire \SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ;
wire \bus2ip_addr_i_reg[2] ;
wire \bus2ip_addr_i_reg[3] ;
wire [6:0]\bus2ip_addr_i_reg[8] ;
wire bus2ip_rnw_i_reg;
wire cie;
wire cs_ce_clr;
wire ip2bus_rdack;
wire ip2bus_rdack_int_d1;
wire ip2bus_rdack_prev2;
wire ip2bus_wrack;
wire ip2bus_wrack_int_d1;
wire ip2bus_wrack_int_d1_i_2_n_0;
wire ip2bus_wrack_int_d1_i_3_n_0;
wire ip2bus_wrack_int_d1_reg;
wire ip2bus_wrack_prev2;
wire is_read;
wire is_write_reg;
wire \mer_int_reg[0] ;
wire \mer_int_reg[0]_0 ;
wire \mer_int_reg[0]_1 ;
wire \mer_int_reg[1] ;
wire p_0_in;
wire p_10_in;
wire p_11_in;
wire p_12_in;
wire p_13_in;
wire p_14_in;
wire p_14_out;
wire p_15_in;
wire p_15_out;
wire p_16_in;
wire p_17_in;
wire p_1_out;
wire p_2_in;
wire p_2_out;
wire p_3_in;
wire p_3_out;
wire p_4_in;
wire p_4_out;
wire p_5_in;
wire p_5_out;
wire p_6_in;
wire p_6_out;
wire p_7_in;
wire p_7_out;
wire p_8_in;
wire p_8_out;
wire p_9_in;
wire p_9_out;
wire pselect_hit_i_0;
wire s_axi_aclk;
wire s_axi_aresetn;
wire \s_axi_rdata_i[0]_i_2_n_0 ;
wire \s_axi_rdata_i[31]_i_3_n_0 ;
wire \s_axi_rdata_i[31]_i_4_n_0 ;
wire [1:0]s_axi_wdata;
wire sie;
LUT3 #(
.INIT(8'hB8))
Bus_RNW_reg_i_1
(.I0(bus2ip_rnw_i_reg),
.I1(Q),
.I2(\mer_int_reg[0] ),
.O(Bus_RNW_reg_i_1_n_0));
FDRE Bus_RNW_reg_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(Bus_RNW_reg_i_1_n_0),
.Q(\mer_int_reg[0] ),
.R(1'b0));
LUT5 #(
.INIT(32'h02000000))
\CIE_GEN.CIE_BIT_GEN[0].cie[0]_i_1
(.I0(s_axi_aresetn),
.I1(cie),
.I2(\mer_int_reg[0] ),
.I3(p_12_in),
.I4(s_axi_wdata[0]),
.O(\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0] ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h00010000))
\GEN_BKEND_CE_REGISTERS[0].ce_out_i[0]_i_1
(.I0(\bus2ip_addr_i_reg[8] [1]),
.I1(\bus2ip_addr_i_reg[8] [2]),
.I2(\bus2ip_addr_i_reg[8] [0]),
.I3(\bus2ip_addr_i_reg[8] [3]),
.I4(\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ),
.O(\GEN_BKEND_CE_REGISTERS[0].ce_out_i[0]_i_1_n_0 ));
FDRE \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]
(.C(s_axi_aclk),
.CE(Q),
.D(\GEN_BKEND_CE_REGISTERS[0].ce_out_i[0]_i_1_n_0 ),
.Q(p_17_in),
.R(cs_ce_clr));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT5 #(
.INIT(32'h00400000))
\GEN_BKEND_CE_REGISTERS[10].ce_out_i[10]_i_1
(.I0(\bus2ip_addr_i_reg[8] [2]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\bus2ip_addr_i_reg[8] [3]),
.I3(\bus2ip_addr_i_reg[8] [0]),
.I4(\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ),
.O(p_5_out));
FDRE \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]
(.C(s_axi_aclk),
.CE(Q),
.D(p_5_out),
.Q(p_7_in),
.R(cs_ce_clr));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT5 #(
.INIT(32'h40000000))
\GEN_BKEND_CE_REGISTERS[11].ce_out_i[11]_i_1
(.I0(\bus2ip_addr_i_reg[8] [2]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ),
.I3(\bus2ip_addr_i_reg[8] [0]),
.I4(\bus2ip_addr_i_reg[8] [3]),
.O(p_4_out));
FDRE \GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11]
(.C(s_axi_aclk),
.CE(Q),
.D(p_4_out),
.Q(p_6_in),
.R(cs_ce_clr));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT5 #(
.INIT(32'h00400000))
\GEN_BKEND_CE_REGISTERS[12].ce_out_i[12]_i_1
(.I0(\bus2ip_addr_i_reg[8] [1]),
.I1(\bus2ip_addr_i_reg[8] [2]),
.I2(\bus2ip_addr_i_reg[8] [3]),
.I3(\bus2ip_addr_i_reg[8] [0]),
.I4(\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ),
.O(p_3_out));
FDRE \GEN_BKEND_CE_REGISTERS[12].ce_out_i_reg[12]
(.C(s_axi_aclk),
.CE(Q),
.D(p_3_out),
.Q(p_5_in),
.R(cs_ce_clr));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h40000000))
\GEN_BKEND_CE_REGISTERS[13].ce_out_i[13]_i_1
(.I0(\bus2ip_addr_i_reg[8] [1]),
.I1(\bus2ip_addr_i_reg[8] [2]),
.I2(\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ),
.I3(\bus2ip_addr_i_reg[8] [0]),
.I4(\bus2ip_addr_i_reg[8] [3]),
.O(p_2_out));
FDRE \GEN_BKEND_CE_REGISTERS[13].ce_out_i_reg[13]
(.C(s_axi_aclk),
.CE(Q),
.D(p_2_out),
.Q(p_4_in),
.R(cs_ce_clr));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT5 #(
.INIT(32'h00800000))
\GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_1
(.I0(\bus2ip_addr_i_reg[8] [1]),
.I1(\bus2ip_addr_i_reg[8] [2]),
.I2(\bus2ip_addr_i_reg[8] [3]),
.I3(\bus2ip_addr_i_reg[8] [0]),
.I4(\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ),
.O(p_1_out));
FDRE \GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14]
(.C(s_axi_aclk),
.CE(Q),
.D(p_1_out),
.Q(p_3_in),
.R(cs_ce_clr));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h80000000))
\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_1
(.I0(\bus2ip_addr_i_reg[8] [1]),
.I1(\bus2ip_addr_i_reg[8] [2]),
.I2(\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ),
.I3(\bus2ip_addr_i_reg[8] [0]),
.I4(\bus2ip_addr_i_reg[8] [3]),
.O(p_15_out));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT4 #(
.INIT(16'h0002))
\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2
(.I0(Q),
.I1(\bus2ip_addr_i_reg[8] [5]),
.I2(\bus2ip_addr_i_reg[8] [4]),
.I3(\bus2ip_addr_i_reg[8] [6]),
.O(\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ));
FDRE \GEN_BKEND_CE_REGISTERS[15].ce_out_i_reg[15]
(.C(s_axi_aclk),
.CE(Q),
.D(p_15_out),
.Q(p_2_in),
.R(cs_ce_clr));
LUT6 #(
.INIT(64'hFFCFFFFFFFCFFFEF))
\GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1
(.I0(is_write_reg),
.I1(ip2bus_wrack),
.I2(s_axi_aresetn),
.I3(ip2bus_rdack),
.I4(\GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_3_n_0 ),
.I5(is_read),
.O(cs_ce_clr));
LUT3 #(
.INIT(8'h08))
\GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_2
(.I0(Q),
.I1(\bus2ip_addr_i_reg[8] [6]),
.I2(\bus2ip_addr_i_reg[8] [5]),
.O(pselect_hit_i_0));
LUT4 #(
.INIT(16'hFFFD))
\GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_3
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [3]),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [2]),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [0]),
.I3(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [1]),
.O(\GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_3_n_0 ));
FDRE \GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg[16]
(.C(s_axi_aclk),
.CE(Q),
.D(pselect_hit_i_0),
.Q(\GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16] ),
.R(cs_ce_clr));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT5 #(
.INIT(32'h01000000))
\GEN_BKEND_CE_REGISTERS[1].ce_out_i[1]_i_1
(.I0(\bus2ip_addr_i_reg[8] [1]),
.I1(\bus2ip_addr_i_reg[8] [2]),
.I2(\bus2ip_addr_i_reg[8] [3]),
.I3(\bus2ip_addr_i_reg[8] [0]),
.I4(\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ),
.O(p_14_out));
FDRE \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]
(.C(s_axi_aclk),
.CE(Q),
.D(p_14_out),
.Q(p_16_in),
.R(cs_ce_clr));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT5 #(
.INIT(32'h00100000))
\GEN_BKEND_CE_REGISTERS[2].ce_out_i[2]_i_1
(.I0(\bus2ip_addr_i_reg[8] [0]),
.I1(\bus2ip_addr_i_reg[8] [3]),
.I2(\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ),
.I3(\bus2ip_addr_i_reg[8] [2]),
.I4(\bus2ip_addr_i_reg[8] [1]),
.O(\GEN_BKEND_CE_REGISTERS[2].ce_out_i[2]_i_1_n_0 ));
FDRE \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]
(.C(s_axi_aclk),
.CE(Q),
.D(\GEN_BKEND_CE_REGISTERS[2].ce_out_i[2]_i_1_n_0 ),
.Q(p_15_in),
.R(cs_ce_clr));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT5 #(
.INIT(32'h00400000))
\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_1
(.I0(\bus2ip_addr_i_reg[8] [3]),
.I1(\bus2ip_addr_i_reg[8] [0]),
.I2(\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ),
.I3(\bus2ip_addr_i_reg[8] [2]),
.I4(\bus2ip_addr_i_reg[8] [1]),
.O(\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_1_n_0 ));
FDRE \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]
(.C(s_axi_aclk),
.CE(Q),
.D(\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_1_n_0 ),
.Q(p_14_in),
.R(cs_ce_clr));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT5 #(
.INIT(32'h00100000))
\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1
(.I0(\bus2ip_addr_i_reg[8] [0]),
.I1(\bus2ip_addr_i_reg[8] [3]),
.I2(\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ),
.I3(\bus2ip_addr_i_reg[8] [1]),
.I4(\bus2ip_addr_i_reg[8] [2]),
.O(\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1_n_0 ));
FDRE \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]
(.C(s_axi_aclk),
.CE(Q),
.D(\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1_n_0 ),
.Q(p_13_in),
.R(cs_ce_clr));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT5 #(
.INIT(32'h00400000))
\GEN_BKEND_CE_REGISTERS[5].ce_out_i[5]_i_1
(.I0(\bus2ip_addr_i_reg[8] [3]),
.I1(\bus2ip_addr_i_reg[8] [0]),
.I2(\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ),
.I3(\bus2ip_addr_i_reg[8] [1]),
.I4(\bus2ip_addr_i_reg[8] [2]),
.O(\GEN_BKEND_CE_REGISTERS[5].ce_out_i[5]_i_1_n_0 ));
FDRE \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]
(.C(s_axi_aclk),
.CE(Q),
.D(\GEN_BKEND_CE_REGISTERS[5].ce_out_i[5]_i_1_n_0 ),
.Q(p_12_in),
.R(cs_ce_clr));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h10000000))
\GEN_BKEND_CE_REGISTERS[6].ce_out_i[6]_i_1
(.I0(\bus2ip_addr_i_reg[8] [0]),
.I1(\bus2ip_addr_i_reg[8] [3]),
.I2(\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ),
.I3(\bus2ip_addr_i_reg[8] [1]),
.I4(\bus2ip_addr_i_reg[8] [2]),
.O(p_9_out));
FDRE \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]
(.C(s_axi_aclk),
.CE(Q),
.D(p_9_out),
.Q(p_11_in),
.R(cs_ce_clr));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT5 #(
.INIT(32'h40000000))
\GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_1
(.I0(\bus2ip_addr_i_reg[8] [3]),
.I1(\bus2ip_addr_i_reg[8] [0]),
.I2(\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ),
.I3(\bus2ip_addr_i_reg[8] [1]),
.I4(\bus2ip_addr_i_reg[8] [2]),
.O(p_8_out));
FDRE \GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7]
(.C(s_axi_aclk),
.CE(Q),
.D(p_8_out),
.Q(p_10_in),
.R(cs_ce_clr));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT5 #(
.INIT(32'h00100000))
\GEN_BKEND_CE_REGISTERS[8].ce_out_i[8]_i_1
(.I0(\bus2ip_addr_i_reg[8] [1]),
.I1(\bus2ip_addr_i_reg[8] [2]),
.I2(\bus2ip_addr_i_reg[8] [3]),
.I3(\bus2ip_addr_i_reg[8] [0]),
.I4(\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ),
.O(p_7_out));
FDRE \GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]
(.C(s_axi_aclk),
.CE(Q),
.D(p_7_out),
.Q(p_9_in),
.R(cs_ce_clr));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT5 #(
.INIT(32'h02000000))
\GEN_BKEND_CE_REGISTERS[9].ce_out_i[9]_i_1
(.I0(\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ),
.I1(\bus2ip_addr_i_reg[8] [2]),
.I2(\bus2ip_addr_i_reg[8] [1]),
.I3(\bus2ip_addr_i_reg[8] [0]),
.I4(\bus2ip_addr_i_reg[8] [3]),
.O(p_6_out));
FDRE \GEN_BKEND_CE_REGISTERS[9].ce_out_i_reg[9]
(.C(s_axi_aclk),
.CE(Q),
.D(p_6_out),
.Q(p_8_in),
.R(cs_ce_clr));
LUT5 #(
.INIT(32'h00004000))
\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar[0]_i_1
(.I0(\mer_int_reg[0] ),
.I1(s_axi_wdata[0]),
.I2(p_14_in),
.I3(s_axi_aresetn),
.I4(\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0]_0 ),
.O(\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0] ));
LUT5 #(
.INIT(32'h00004000))
\SIE_GEN.SIE_BIT_GEN[0].sie[0]_i_1
(.I0(\mer_int_reg[0] ),
.I1(p_13_in),
.I2(s_axi_wdata[0]),
.I3(s_axi_aresetn),
.I4(sie),
.O(\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ));
LUT6 #(
.INIT(64'h00000000FFFB0000))
ip2bus_rdack_i_1
(.I0(\s_axi_rdata_i[31]_i_4_n_0 ),
.I1(\s_axi_rdata_i[0]_i_2_n_0 ),
.I2(ip2bus_wrack_int_d1_i_3_n_0),
.I3(ip2bus_wrack_int_d1_i_2_n_0),
.I4(\mer_int_reg[0] ),
.I5(ip2bus_rdack_int_d1),
.O(ip2bus_rdack_prev2));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT5 #(
.INIT(32'hAAAAA8AA))
ip2bus_rdack_int_d1_i_1
(.I0(\mer_int_reg[0] ),
.I1(ip2bus_wrack_int_d1_i_2_n_0),
.I2(ip2bus_wrack_int_d1_i_3_n_0),
.I3(\s_axi_rdata_i[0]_i_2_n_0 ),
.I4(\s_axi_rdata_i[31]_i_4_n_0 ),
.O(Or128_vec2stdlogic19_out));
LUT6 #(
.INIT(64'h000000000000FFFB))
ip2bus_wrack_i_1
(.I0(\s_axi_rdata_i[31]_i_4_n_0 ),
.I1(\s_axi_rdata_i[0]_i_2_n_0 ),
.I2(ip2bus_wrack_int_d1_i_3_n_0),
.I3(ip2bus_wrack_int_d1_i_2_n_0),
.I4(\mer_int_reg[0] ),
.I5(ip2bus_wrack_int_d1),
.O(ip2bus_wrack_prev2));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT5 #(
.INIT(32'h55555455))
ip2bus_wrack_int_d1_i_1
(.I0(\mer_int_reg[0] ),
.I1(ip2bus_wrack_int_d1_i_2_n_0),
.I2(ip2bus_wrack_int_d1_i_3_n_0),
.I3(\s_axi_rdata_i[0]_i_2_n_0 ),
.I4(\s_axi_rdata_i[31]_i_4_n_0 ),
.O(ip2bus_wrack_int_d1_reg));
LUT4 #(
.INIT(16'hFFFE))
ip2bus_wrack_int_d1_i_2
(.I0(p_4_in),
.I1(p_3_in),
.I2(p_6_in),
.I3(p_2_in),
.O(ip2bus_wrack_int_d1_i_2_n_0));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
ip2bus_wrack_int_d1_i_3
(.I0(p_12_in),
.I1(p_14_in),
.I2(p_13_in),
.I3(p_7_in),
.I4(\GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16] ),
.I5(p_5_in),
.O(ip2bus_wrack_int_d1_i_3_n_0));
LUT4 #(
.INIT(16'hFB08))
\mer_int[0]_i_1
(.I0(s_axi_wdata[0]),
.I1(p_10_in),
.I2(\mer_int_reg[0] ),
.I3(\mer_int_reg[0]_1 ),
.O(\mer_int_reg[0]_0 ));
LUT4 #(
.INIT(16'hFF20))
\mer_int[1]_i_1
(.I0(s_axi_wdata[1]),
.I1(\mer_int_reg[0] ),
.I2(p_10_in),
.I3(p_0_in),
.O(\mer_int_reg[1] ));
LUT6 #(
.INIT(64'h5151510051515151))
\s_axi_rdata_i[0]_i_1
(.I0(\s_axi_rdata_i[31]_i_3_n_0 ),
.I1(\s_axi_rdata_i[0]_i_2_n_0 ),
.I2(\s_axi_rdata_i[31]_i_4_n_0 ),
.I3(\IPR_GEN.ipr_reg[0] ),
.I4(\bus2ip_addr_i_reg[3] ),
.I5(\bus2ip_addr_i_reg[2] ),
.O(D[0]));
LUT3 #(
.INIT(8'h01))
\s_axi_rdata_i[0]_i_2
(.I0(p_8_in),
.I1(p_11_in),
.I2(p_9_in),
.O(\s_axi_rdata_i[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000000055555554))
\s_axi_rdata_i[1]_i_1
(.I0(\s_axi_rdata_i[31]_i_3_n_0 ),
.I1(p_9_in),
.I2(p_11_in),
.I3(p_8_in),
.I4(\s_axi_rdata_i[31]_i_4_n_0 ),
.I5(\IVR_GEN.ivr_reg[0] ),
.O(D[1]));
LUT6 #(
.INIT(64'h0000000055555554))
\s_axi_rdata_i[31]_i_2
(.I0(\s_axi_rdata_i[31]_i_3_n_0 ),
.I1(p_9_in),
.I2(p_11_in),
.I3(p_8_in),
.I4(\s_axi_rdata_i[31]_i_4_n_0 ),
.I5(\bus2ip_addr_i_reg[2] ),
.O(D[2]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT4 #(
.INIT(16'hFEFF))
\s_axi_rdata_i[31]_i_3
(.I0(\bus2ip_addr_i_reg[8] [5]),
.I1(\bus2ip_addr_i_reg[8] [4]),
.I2(\bus2ip_addr_i_reg[8] [6]),
.I3(\mer_int_reg[0] ),
.O(\s_axi_rdata_i[31]_i_3_n_0 ));
LUT4 #(
.INIT(16'hFFFE))
\s_axi_rdata_i[31]_i_4
(.I0(p_15_in),
.I1(p_17_in),
.I2(p_16_in),
.I3(p_10_in),
.O(\s_axi_rdata_i[31]_i_4_n_0 ));
endmodule
(* C_ASYNC_INTR = "-2" *) (* C_CASCADE_MASTER = "0" *) (* C_DISABLE_SYNCHRONIZERS = "0" *)
(* C_ENABLE_ASYNC = "0" *) (* C_EN_CASCADE_MODE = "0" *) (* C_FAMILY = "zynq" *)
(* C_HAS_CIE = "1" *) (* C_HAS_FAST = "0" *) (* C_HAS_ILR = "0" *)
(* C_HAS_IPR = "1" *) (* C_HAS_IVR = "1" *) (* C_HAS_SIE = "1" *)
(* C_INSTANCE = "design_1_axi_intc_0_0" *) (* C_IRQ_ACTIVE = "1'b1" *) (* C_IRQ_IS_LEVEL = "0" *)
(* C_IVAR_RESET_VALUE = "16" *) (* C_KIND_OF_EDGE = "-1" *) (* C_KIND_OF_INTR = "-2" *)
(* C_KIND_OF_LVL = "-1" *) (* C_MB_CLK_NOT_CONNECTED = "1" *) (* C_NUM_INTR_INPUTS = "1" *)
(* C_NUM_SW_INTR = "0" *) (* C_NUM_SYNC_FF = "2" *) (* C_S_AXI_ADDR_WIDTH = "9" *)
(* C_S_AXI_DATA_WIDTH = "32" *) (* hdl = "VHDL" *) (* imp_netlist = "TRUE" *)
(* ip_group = "LOGICORE" *) (* iptype = "PERIPHERAL" *) (* run_ngcbuild = "TRUE" *)
(* style = "HDL" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_intc
(s_axi_aclk,
s_axi_aresetn,
s_axi_awaddr,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
intr,
processor_clk,
processor_rst,
irq,
processor_ack,
interrupt_address,
irq_in,
interrupt_address_in,
processor_ack_out);
(* max_fanout = "10000" *) (* sigis = "Clk" *) input s_axi_aclk;
(* max_fanout = "10000" *) (* sigis = "Rstn" *) input s_axi_aresetn;
input [8:0]s_axi_awaddr;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [8:0]s_axi_araddr;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rvalid;
input s_axi_rready;
(* BUFFER_TYPE = "none" *) input [0:0]intr;
input processor_clk;
input processor_rst;
output irq;
input [1:0]processor_ack;
output [31:0]interrupt_address;
input irq_in;
input [31:0]interrupt_address_in;
output [1:0]processor_ack_out;
wire \<const0> ;
wire AXI_LITE_IPIF_I_n_12;
wire AXI_LITE_IPIF_I_n_13;
wire AXI_LITE_IPIF_I_n_14;
wire AXI_LITE_IPIF_I_n_15;
wire AXI_LITE_IPIF_I_n_16;
wire AXI_LITE_IPIF_I_n_17;
wire INTC_CORE_I_n_1;
wire INTC_CORE_I_n_2;
wire INTC_CORE_I_n_6;
wire \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg ;
wire \I_SLAVE_ATTACHMENT/I_DECODER/p_15_in ;
wire \I_SLAVE_ATTACHMENT/I_DECODER/p_17_in ;
wire Or128_vec2stdlogic19_out;
wire cie;
wire ier;
wire [0:0]intr;
wire ip2bus_rdack;
wire ip2bus_rdack_int_d1;
wire ip2bus_rdack_prev2;
wire ip2bus_wrack;
wire ip2bus_wrack_int_d1;
wire ip2bus_wrack_prev2;
wire [0:0]ipr;
wire irq;
wire isr;
wire ivr;
wire p_0_in;
(* MAX_FANOUT = "10000" *) (* RTL_MAX_FANOUT = "found" *) (* sigis = "Clk" *) wire s_axi_aclk;
wire [8:0]s_axi_araddr;
(* MAX_FANOUT = "10000" *) (* RTL_MAX_FANOUT = "found" *) (* sigis = "Rstn" *) wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [8:0]s_axi_awaddr;
wire s_axi_awvalid;
wire s_axi_bready;
wire [1:1]\^s_axi_bresp ;
wire s_axi_bvalid;
wire [30:0]\^s_axi_rdata ;
wire s_axi_rready;
wire [1:1]\^s_axi_rresp ;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
wire sie;
assign interrupt_address[31] = \<const0> ;
assign interrupt_address[30] = \<const0> ;
assign interrupt_address[29] = \<const0> ;
assign interrupt_address[28] = \<const0> ;
assign interrupt_address[27] = \<const0> ;
assign interrupt_address[26] = \<const0> ;
assign interrupt_address[25] = \<const0> ;
assign interrupt_address[24] = \<const0> ;
assign interrupt_address[23] = \<const0> ;
assign interrupt_address[22] = \<const0> ;
assign interrupt_address[21] = \<const0> ;
assign interrupt_address[20] = \<const0> ;
assign interrupt_address[19] = \<const0> ;
assign interrupt_address[18] = \<const0> ;
assign interrupt_address[17] = \<const0> ;
assign interrupt_address[16] = \<const0> ;
assign interrupt_address[15] = \<const0> ;
assign interrupt_address[14] = \<const0> ;
assign interrupt_address[13] = \<const0> ;
assign interrupt_address[12] = \<const0> ;
assign interrupt_address[11] = \<const0> ;
assign interrupt_address[10] = \<const0> ;
assign interrupt_address[9] = \<const0> ;
assign interrupt_address[8] = \<const0> ;
assign interrupt_address[7] = \<const0> ;
assign interrupt_address[6] = \<const0> ;
assign interrupt_address[5] = \<const0> ;
assign interrupt_address[4] = \<const0> ;
assign interrupt_address[3] = \<const0> ;
assign interrupt_address[2] = \<const0> ;
assign interrupt_address[1] = \<const0> ;
assign interrupt_address[0] = \<const0> ;
assign processor_ack_out[1] = \<const0> ;
assign processor_ack_out[0] = \<const0> ;
assign s_axi_awready = s_axi_wready;
assign s_axi_bresp[1] = \^s_axi_bresp [1];
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_rdata[31] = \^s_axi_rdata [30];
assign s_axi_rdata[30] = \^s_axi_rdata [30];
assign s_axi_rdata[29] = \^s_axi_rdata [30];
assign s_axi_rdata[28] = \^s_axi_rdata [30];
assign s_axi_rdata[27] = \^s_axi_rdata [30];
assign s_axi_rdata[26] = \^s_axi_rdata [30];
assign s_axi_rdata[25] = \^s_axi_rdata [30];
assign s_axi_rdata[24] = \^s_axi_rdata [30];
assign s_axi_rdata[23] = \^s_axi_rdata [30];
assign s_axi_rdata[22] = \^s_axi_rdata [30];
assign s_axi_rdata[21] = \^s_axi_rdata [30];
assign s_axi_rdata[20] = \^s_axi_rdata [30];
assign s_axi_rdata[19] = \^s_axi_rdata [30];
assign s_axi_rdata[18] = \^s_axi_rdata [30];
assign s_axi_rdata[17] = \^s_axi_rdata [30];
assign s_axi_rdata[16] = \^s_axi_rdata [30];
assign s_axi_rdata[15] = \^s_axi_rdata [30];
assign s_axi_rdata[14] = \^s_axi_rdata [30];
assign s_axi_rdata[13] = \^s_axi_rdata [30];
assign s_axi_rdata[12] = \^s_axi_rdata [30];
assign s_axi_rdata[11] = \^s_axi_rdata [30];
assign s_axi_rdata[10] = \^s_axi_rdata [30];
assign s_axi_rdata[9] = \^s_axi_rdata [30];
assign s_axi_rdata[8] = \^s_axi_rdata [30];
assign s_axi_rdata[7] = \^s_axi_rdata [30];
assign s_axi_rdata[6] = \^s_axi_rdata [30];
assign s_axi_rdata[5] = \^s_axi_rdata [30];
assign s_axi_rdata[4] = \^s_axi_rdata [30];
assign s_axi_rdata[3] = \^s_axi_rdata [30];
assign s_axi_rdata[2] = \^s_axi_rdata [30];
assign s_axi_rdata[1:0] = \^s_axi_rdata [1:0];
assign s_axi_rresp[1] = \^s_axi_rresp [1];
assign s_axi_rresp[0] = \<const0> ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif AXI_LITE_IPIF_I
(.Bus_RNW_reg(\I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg ),
.\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0] (AXI_LITE_IPIF_I_n_15),
.Or128_vec2stdlogic19_out(Or128_vec2stdlogic19_out),
.\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0] (AXI_LITE_IPIF_I_n_16),
.\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0]_0 (INTC_CORE_I_n_2),
.\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] (AXI_LITE_IPIF_I_n_14),
.cie(cie),
.ier(ier),
.ip2bus_rdack(ip2bus_rdack),
.ip2bus_rdack_int_d1(ip2bus_rdack_int_d1),
.ip2bus_rdack_prev2(ip2bus_rdack_prev2),
.ip2bus_wrack(ip2bus_wrack),
.ip2bus_wrack_int_d1(ip2bus_wrack_int_d1),
.ip2bus_wrack_int_d1_reg(AXI_LITE_IPIF_I_n_17),
.ip2bus_wrack_prev2(ip2bus_wrack_prev2),
.ipr(ipr),
.isr(isr),
.ivr(ivr),
.\mer_int_reg[0] (AXI_LITE_IPIF_I_n_12),
.\mer_int_reg[0]_0 (INTC_CORE_I_n_6),
.\mer_int_reg[1] (AXI_LITE_IPIF_I_n_13),
.p_0_in(p_0_in),
.p_15_in(\I_SLAVE_ATTACHMENT/I_DECODER/p_15_in ),
.p_17_in(\I_SLAVE_ATTACHMENT/I_DECODER/p_17_in ),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr[8:2]),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_aresetn_0(INTC_CORE_I_n_1),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr[8:2]),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(\^s_axi_bresp ),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata({\^s_axi_rdata [30],\^s_axi_rdata [1:0]}),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(\^s_axi_rresp ),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata[1:0]),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wvalid(s_axi_wvalid),
.sie(sie));
GND GND
(.G(\<const0> ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_intc_core INTC_CORE_I
(.Bus_RNW_reg(\I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg ),
.Bus_RNW_reg_reg(AXI_LITE_IPIF_I_n_16),
.Bus_RNW_reg_reg_0(AXI_LITE_IPIF_I_n_13),
.Bus_RNW_reg_reg_1(AXI_LITE_IPIF_I_n_14),
.\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]_0 (AXI_LITE_IPIF_I_n_15),
.\GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7] (AXI_LITE_IPIF_I_n_12),
.\IPR_GEN.ipr_reg[0]_0 (INTC_CORE_I_n_1),
.\IRQ_EDGE_GEN.IRQ_EDGE_NO_MB_CLK_GEN.current_state_reg[0]_0 (INTC_CORE_I_n_6),
.ack_or_reg_0(INTC_CORE_I_n_2),
.cie(cie),
.ier(ier),
.intr(intr),
.ipr(ipr),
.irq(irq),
.isr(isr),
.ivr(ivr),
.p_0_in(p_0_in),
.p_15_in(\I_SLAVE_ATTACHMENT/I_DECODER/p_15_in ),
.p_17_in(\I_SLAVE_ATTACHMENT/I_DECODER/p_17_in ),
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_wdata(s_axi_wdata[0]),
.sie(sie));
FDRE ip2bus_rdack_int_d1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(Or128_vec2stdlogic19_out),
.Q(ip2bus_rdack_int_d1),
.R(INTC_CORE_I_n_1));
FDRE ip2bus_rdack_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_rdack_prev2),
.Q(ip2bus_rdack),
.R(INTC_CORE_I_n_1));
FDRE ip2bus_wrack_int_d1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(AXI_LITE_IPIF_I_n_17),
.Q(ip2bus_wrack_int_d1),
.R(INTC_CORE_I_n_1));
FDRE ip2bus_wrack_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_wrack_prev2),
.Q(ip2bus_wrack),
.R(INTC_CORE_I_n_1));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif
(p_15_in,
p_17_in,
s_axi_rresp,
Bus_RNW_reg,
s_axi_rvalid,
s_axi_bvalid,
s_axi_bresp,
s_axi_wready,
s_axi_arready,
ip2bus_wrack_prev2,
ip2bus_rdack_prev2,
Or128_vec2stdlogic19_out,
\mer_int_reg[0] ,
\mer_int_reg[1] ,
\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ,
\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0] ,
\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0] ,
ip2bus_wrack_int_d1_reg,
s_axi_rdata,
s_axi_aresetn_0,
s_axi_aclk,
s_axi_arvalid,
ip2bus_wrack,
s_axi_aresetn,
ip2bus_rdack,
s_axi_rready,
s_axi_bready,
s_axi_wvalid,
s_axi_awvalid,
s_axi_araddr,
s_axi_awaddr,
ipr,
ier,
ivr,
p_0_in,
\mer_int_reg[0]_0 ,
isr,
ip2bus_wrack_int_d1,
ip2bus_rdack_int_d1,
s_axi_wstrb,
s_axi_wdata,
sie,
cie,
\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0]_0 );
output p_15_in;
output p_17_in;
output [0:0]s_axi_rresp;
output Bus_RNW_reg;
output s_axi_rvalid;
output s_axi_bvalid;
output [0:0]s_axi_bresp;
output s_axi_wready;
output s_axi_arready;
output ip2bus_wrack_prev2;
output ip2bus_rdack_prev2;
output Or128_vec2stdlogic19_out;
output \mer_int_reg[0] ;
output \mer_int_reg[1] ;
output \SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ;
output \CIE_GEN.CIE_BIT_GEN[0].cie_reg[0] ;
output \REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0] ;
output ip2bus_wrack_int_d1_reg;
output [2:0]s_axi_rdata;
input s_axi_aresetn_0;
input s_axi_aclk;
input s_axi_arvalid;
input ip2bus_wrack;
input s_axi_aresetn;
input ip2bus_rdack;
input s_axi_rready;
input s_axi_bready;
input s_axi_wvalid;
input s_axi_awvalid;
input [6:0]s_axi_araddr;
input [6:0]s_axi_awaddr;
input [0:0]ipr;
input ier;
input ivr;
input p_0_in;
input \mer_int_reg[0]_0 ;
input isr;
input ip2bus_wrack_int_d1;
input ip2bus_rdack_int_d1;
input [3:0]s_axi_wstrb;
input [1:0]s_axi_wdata;
input sie;
input cie;
input \REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0]_0 ;
wire Bus_RNW_reg;
wire \CIE_GEN.CIE_BIT_GEN[0].cie_reg[0] ;
wire Or128_vec2stdlogic19_out;
wire \REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0] ;
wire \REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0]_0 ;
wire \SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ;
wire cie;
wire ier;
wire ip2bus_rdack;
wire ip2bus_rdack_int_d1;
wire ip2bus_rdack_prev2;
wire ip2bus_wrack;
wire ip2bus_wrack_int_d1;
wire ip2bus_wrack_int_d1_reg;
wire ip2bus_wrack_prev2;
wire [0:0]ipr;
wire isr;
wire ivr;
wire \mer_int_reg[0] ;
wire \mer_int_reg[0]_0 ;
wire \mer_int_reg[1] ;
wire p_0_in;
wire p_15_in;
wire p_17_in;
wire s_axi_aclk;
wire [6:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_aresetn_0;
wire s_axi_arready;
wire s_axi_arvalid;
wire [6:0]s_axi_awaddr;
wire s_axi_awvalid;
wire s_axi_bready;
wire [0:0]s_axi_bresp;
wire s_axi_bvalid;
wire [2:0]s_axi_rdata;
wire s_axi_rready;
wire [0:0]s_axi_rresp;
wire s_axi_rvalid;
wire [1:0]s_axi_wdata;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
wire sie;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment I_SLAVE_ATTACHMENT
(.\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0] (\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0] ),
.Or128_vec2stdlogic19_out(Or128_vec2stdlogic19_out),
.\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0] (\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0] ),
.\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0]_0 (\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0]_0 ),
.\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] (\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ),
.cie(cie),
.ier(ier),
.ip2bus_rdack(ip2bus_rdack),
.ip2bus_rdack_int_d1(ip2bus_rdack_int_d1),
.ip2bus_rdack_prev2(ip2bus_rdack_prev2),
.ip2bus_wrack(ip2bus_wrack),
.ip2bus_wrack_int_d1(ip2bus_wrack_int_d1),
.ip2bus_wrack_int_d1_reg(ip2bus_wrack_int_d1_reg),
.ip2bus_wrack_prev2(ip2bus_wrack_prev2),
.ipr(ipr),
.isr(isr),
.ivr(ivr),
.\mer_int_reg[0] (Bus_RNW_reg),
.\mer_int_reg[0]_0 (\mer_int_reg[0] ),
.\mer_int_reg[0]_1 (\mer_int_reg[0]_0 ),
.\mer_int_reg[1] (\mer_int_reg[1] ),
.p_0_in(p_0_in),
.p_15_in(p_15_in),
.p_17_in(p_17_in),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_aresetn_0(s_axi_aresetn_0),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wvalid(s_axi_wvalid),
.sie(sie));
endmodule
(* CHECK_LICENSE_TYPE = "design_1_axi_intc_0_0,axi_intc,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "axi_intc,Vivado 2016.4" *)
(* NotValidForBitStream *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(s_axi_aclk,
s_axi_aresetn,
s_axi_awaddr,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
intr,
irq);
(* x_interface_info = "xilinx.com:signal:clock:1.0 s_axi_aclk CLK" *) input s_axi_aclk;
(* x_interface_info = "xilinx.com:signal:reset:1.0 s_resetn RST" *) input s_axi_aresetn;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi AWADDR" *) input [8:0]s_axi_awaddr;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi AWVALID" *) input s_axi_awvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi AWREADY" *) output s_axi_awready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi WDATA" *) input [31:0]s_axi_wdata;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi WSTRB" *) input [3:0]s_axi_wstrb;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi WVALID" *) input s_axi_wvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi WREADY" *) output s_axi_wready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi BRESP" *) output [1:0]s_axi_bresp;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi BVALID" *) output s_axi_bvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi BREADY" *) input s_axi_bready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi ARADDR" *) input [8:0]s_axi_araddr;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi ARVALID" *) input s_axi_arvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi ARREADY" *) output s_axi_arready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi RDATA" *) output [31:0]s_axi_rdata;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi RRESP" *) output [1:0]s_axi_rresp;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi RVALID" *) output s_axi_rvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi RREADY" *) input s_axi_rready;
(* x_interface_info = "xilinx.com:signal:interrupt:1.0 interrupt_input INTERRUPT" *) input [0:0]intr;
(* x_interface_info = "xilinx.com:interface:mbinterrupt:1.0 interrupt INTERRUPT" *) output irq;
wire [0:0]intr;
wire irq;
wire s_axi_aclk;
wire [8:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [8:0]s_axi_awaddr;
wire s_axi_awready;
wire s_axi_awvalid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire s_axi_rready;
wire [1:0]s_axi_rresp;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
wire [31:0]NLW_U0_interrupt_address_UNCONNECTED;
wire [1:0]NLW_U0_processor_ack_out_UNCONNECTED;
(* C_ASYNC_INTR = "-2" *)
(* C_CASCADE_MASTER = "0" *)
(* C_DISABLE_SYNCHRONIZERS = "0" *)
(* C_ENABLE_ASYNC = "0" *)
(* C_EN_CASCADE_MODE = "0" *)
(* C_FAMILY = "zynq" *)
(* C_HAS_CIE = "1" *)
(* C_HAS_FAST = "0" *)
(* C_HAS_ILR = "0" *)
(* C_HAS_IPR = "1" *)
(* C_HAS_IVR = "1" *)
(* C_HAS_SIE = "1" *)
(* C_INSTANCE = "design_1_axi_intc_0_0" *)
(* C_IRQ_ACTIVE = "1'b1" *)
(* C_IRQ_IS_LEVEL = "0" *)
(* C_IVAR_RESET_VALUE = "16" *)
(* C_KIND_OF_EDGE = "-1" *)
(* C_KIND_OF_INTR = "-2" *)
(* C_KIND_OF_LVL = "-1" *)
(* C_MB_CLK_NOT_CONNECTED = "1" *)
(* C_NUM_INTR_INPUTS = "1" *)
(* C_NUM_SW_INTR = "0" *)
(* C_NUM_SYNC_FF = "2" *)
(* C_S_AXI_ADDR_WIDTH = "9" *)
(* C_S_AXI_DATA_WIDTH = "32" *)
(* hdl = "VHDL" *)
(* imp_netlist = "TRUE" *)
(* ip_group = "LOGICORE" *)
(* iptype = "PERIPHERAL" *)
(* run_ngcbuild = "TRUE" *)
(* style = "HDL" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_intc U0
(.interrupt_address(NLW_U0_interrupt_address_UNCONNECTED[31:0]),
.interrupt_address_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.intr(intr),
.irq(irq),
.irq_in(1'b0),
.processor_ack({1'b0,1'b0}),
.processor_ack_out(NLW_U0_processor_ack_out_UNCONNECTED[1:0]),
.processor_clk(1'b0),
.processor_rst(1'b0),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wvalid(s_axi_wvalid));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_intc_core
(ier,
\IPR_GEN.ipr_reg[0]_0 ,
ack_or_reg_0,
irq,
ipr,
ivr,
\IRQ_EDGE_GEN.IRQ_EDGE_NO_MB_CLK_GEN.current_state_reg[0]_0 ,
p_0_in,
isr,
sie,
cie,
s_axi_aclk,
Bus_RNW_reg_reg,
\GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7] ,
Bus_RNW_reg_reg_0,
Bus_RNW_reg_reg_1,
\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]_0 ,
s_axi_aresetn,
s_axi_wdata,
p_15_in,
Bus_RNW_reg,
p_17_in,
intr);
output ier;
output \IPR_GEN.ipr_reg[0]_0 ;
output ack_or_reg_0;
output irq;
output [0:0]ipr;
output ivr;
output \IRQ_EDGE_GEN.IRQ_EDGE_NO_MB_CLK_GEN.current_state_reg[0]_0 ;
output p_0_in;
output isr;
output sie;
output cie;
input s_axi_aclk;
input Bus_RNW_reg_reg;
input \GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7] ;
input Bus_RNW_reg_reg_0;
input Bus_RNW_reg_reg_1;
input \CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]_0 ;
input s_axi_aresetn;
input [0:0]s_axi_wdata;
input p_15_in;
input Bus_RNW_reg;
input p_17_in;
input [0:0]intr;
wire Bus_RNW_reg;
wire Bus_RNW_reg_reg;
wire Bus_RNW_reg_reg_0;
wire Bus_RNW_reg_reg_1;
wire \CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]_0 ;
wire \GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7] ;
wire \INTR_DETECT_GEN[0].LVL_DETECT_GEN.hw_intr[0]_i_1_n_0 ;
wire \IPR_GEN.ipr[0]_i_1_n_0 ;
wire \IPR_GEN.ipr_reg[0]_0 ;
wire \IRQ_EDGE_GEN.IRQ_EDGE_NO_MB_CLK_GEN.Irq_i_2_n_0 ;
wire \IRQ_EDGE_GEN.IRQ_EDGE_NO_MB_CLK_GEN.current_state_reg[0]_0 ;
wire \IRQ_EDGE_GEN.IRQ_EDGE_NO_MB_CLK_GEN.current_state_reg_n_0_[0] ;
wire \IRQ_EDGE_GEN.IRQ_EDGE_NO_MB_CLK_GEN.current_state_reg_n_0_[1] ;
wire \REG_GEN[0].ier[0]_i_2_n_0 ;
wire \REG_GEN[0].isr[0]_i_1_n_0 ;
wire \REG_GEN[0].isr[0]_i_2_n_0 ;
wire ack_or;
wire ack_or_reg_0;
wire cie;
wire [1:0]current_state;
wire hw_intr;
wire ier;
wire [0:0]intr;
wire [0:0]ipr;
wire irq;
wire isr;
wire ivr;
wire p_0_in;
wire p_15_in;
wire p_17_in;
wire p_1_in;
wire p_5_out;
wire s_axi_aclk;
wire s_axi_aresetn;
wire [0:0]s_axi_wdata;
wire sie;
FDRE \CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]_0 ),
.Q(cie),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT4 #(
.INIT(16'h00E0))
\INTR_DETECT_GEN[0].LVL_DETECT_GEN.hw_intr[0]_i_1
(.I0(hw_intr),
.I1(intr),
.I2(s_axi_aresetn),
.I3(ack_or_reg_0),
.O(\INTR_DETECT_GEN[0].LVL_DETECT_GEN.hw_intr[0]_i_1_n_0 ));
FDRE \INTR_DETECT_GEN[0].LVL_DETECT_GEN.hw_intr_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\INTR_DETECT_GEN[0].LVL_DETECT_GEN.hw_intr[0]_i_1_n_0 ),
.Q(hw_intr),
.R(1'b0));
LUT2 #(
.INIT(4'h8))
\IPR_GEN.ipr[0]_i_1
(.I0(ier),
.I1(isr),
.O(\IPR_GEN.ipr[0]_i_1_n_0 ));
FDRE \IPR_GEN.ipr_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\IPR_GEN.ipr[0]_i_1_n_0 ),
.Q(ipr),
.R(\IPR_GEN.ipr_reg[0]_0 ));
LUT1 #(
.INIT(2'h1))
\IRQ_EDGE_GEN.IRQ_EDGE_NO_MB_CLK_GEN.Irq_i_1
(.I0(s_axi_aresetn),
.O(\IPR_GEN.ipr_reg[0]_0 ));
LUT2 #(
.INIT(4'h2))
\IRQ_EDGE_GEN.IRQ_EDGE_NO_MB_CLK_GEN.Irq_i_2
(.I0(\IRQ_EDGE_GEN.IRQ_EDGE_NO_MB_CLK_GEN.current_state_reg_n_0_[0] ),
.I1(\IRQ_EDGE_GEN.IRQ_EDGE_NO_MB_CLK_GEN.current_state_reg_n_0_[1] ),
.O(\IRQ_EDGE_GEN.IRQ_EDGE_NO_MB_CLK_GEN.Irq_i_2_n_0 ));
FDRE \IRQ_EDGE_GEN.IRQ_EDGE_NO_MB_CLK_GEN.Irq_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\IRQ_EDGE_GEN.IRQ_EDGE_NO_MB_CLK_GEN.Irq_i_2_n_0 ),
.Q(irq),
.R(\IPR_GEN.ipr_reg[0]_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT4 #(
.INIT(16'h1000))
\IRQ_EDGE_GEN.IRQ_EDGE_NO_MB_CLK_GEN.current_state[0]_i_1
(.I0(\IRQ_EDGE_GEN.IRQ_EDGE_NO_MB_CLK_GEN.current_state_reg_n_0_[0] ),
.I1(\IRQ_EDGE_GEN.IRQ_EDGE_NO_MB_CLK_GEN.current_state_reg_n_0_[1] ),
.I2(ipr),
.I3(\IRQ_EDGE_GEN.IRQ_EDGE_NO_MB_CLK_GEN.current_state_reg[0]_0 ),
.O(current_state[0]));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT3 #(
.INIT(8'hBA))
\IRQ_EDGE_GEN.IRQ_EDGE_NO_MB_CLK_GEN.current_state[1]_i_1
(.I0(\IRQ_EDGE_GEN.IRQ_EDGE_NO_MB_CLK_GEN.current_state_reg_n_0_[0] ),
.I1(ack_or),
.I2(\IRQ_EDGE_GEN.IRQ_EDGE_NO_MB_CLK_GEN.current_state_reg_n_0_[1] ),
.O(current_state[1]));
FDRE \IRQ_EDGE_GEN.IRQ_EDGE_NO_MB_CLK_GEN.current_state_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(current_state[0]),
.Q(\IRQ_EDGE_GEN.IRQ_EDGE_NO_MB_CLK_GEN.current_state_reg_n_0_[0] ),
.R(\IPR_GEN.ipr_reg[0]_0 ));
FDRE \IRQ_EDGE_GEN.IRQ_EDGE_NO_MB_CLK_GEN.current_state_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(current_state[1]),
.Q(\IRQ_EDGE_GEN.IRQ_EDGE_NO_MB_CLK_GEN.current_state_reg_n_0_[1] ),
.R(\IPR_GEN.ipr_reg[0]_0 ));
LUT2 #(
.INIT(4'h7))
\IVR_GEN.ivr[0]_i_1
(.I0(isr),
.I1(ier),
.O(p_1_in));
FDSE \IVR_GEN.ivr_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(p_1_in),
.Q(ivr),
.S(\IPR_GEN.ipr_reg[0]_0 ));
FDRE \REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Bus_RNW_reg_reg),
.Q(ack_or_reg_0),
.R(1'b0));
LUT6 #(
.INIT(64'hAAAAAAAAAA8A0080))
\REG_GEN[0].ier[0]_i_1
(.I0(\REG_GEN[0].ier[0]_i_2_n_0 ),
.I1(s_axi_wdata),
.I2(p_15_in),
.I3(Bus_RNW_reg),
.I4(ier),
.I5(sie),
.O(p_5_out));
LUT2 #(
.INIT(4'h2))
\REG_GEN[0].ier[0]_i_2
(.I0(s_axi_aresetn),
.I1(cie),
.O(\REG_GEN[0].ier[0]_i_2_n_0 ));
FDRE \REG_GEN[0].ier_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(p_5_out),
.Q(ier),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'h08))
\REG_GEN[0].isr[0]_i_1
(.I0(\REG_GEN[0].isr[0]_i_2_n_0 ),
.I1(s_axi_aresetn),
.I2(ack_or_reg_0),
.O(\REG_GEN[0].isr[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAFACAFAFA0ACA0A0))
\REG_GEN[0].isr[0]_i_2
(.I0(hw_intr),
.I1(s_axi_wdata),
.I2(p_0_in),
.I3(Bus_RNW_reg),
.I4(p_17_in),
.I5(isr),
.O(\REG_GEN[0].isr[0]_i_2_n_0 ));
FDRE \REG_GEN[0].isr_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\REG_GEN[0].isr[0]_i_1_n_0 ),
.Q(isr),
.R(1'b0));
FDRE \SIE_GEN.SIE_BIT_GEN[0].sie_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Bus_RNW_reg_reg_1),
.Q(sie),
.R(1'b0));
FDRE ack_or_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(ack_or_reg_0),
.Q(ack_or),
.R(\IPR_GEN.ipr_reg[0]_0 ));
FDRE \mer_int_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7] ),
.Q(\IRQ_EDGE_GEN.IRQ_EDGE_NO_MB_CLK_GEN.current_state_reg[0]_0 ),
.R(\IPR_GEN.ipr_reg[0]_0 ));
FDRE \mer_int_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Bus_RNW_reg_reg_0),
.Q(p_0_in),
.R(\IPR_GEN.ipr_reg[0]_0 ));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment
(p_15_in,
p_17_in,
s_axi_rresp,
\mer_int_reg[0] ,
s_axi_rvalid,
s_axi_bvalid,
s_axi_bresp,
s_axi_wready,
s_axi_arready,
ip2bus_wrack_prev2,
ip2bus_rdack_prev2,
Or128_vec2stdlogic19_out,
\mer_int_reg[0]_0 ,
\mer_int_reg[1] ,
\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ,
\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0] ,
\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0] ,
ip2bus_wrack_int_d1_reg,
s_axi_rdata,
s_axi_aresetn_0,
s_axi_aclk,
s_axi_arvalid,
ip2bus_wrack,
s_axi_aresetn,
ip2bus_rdack,
s_axi_rready,
s_axi_bready,
s_axi_wvalid,
s_axi_awvalid,
s_axi_araddr,
s_axi_awaddr,
ipr,
ier,
ivr,
p_0_in,
\mer_int_reg[0]_1 ,
isr,
ip2bus_wrack_int_d1,
ip2bus_rdack_int_d1,
s_axi_wstrb,
s_axi_wdata,
sie,
cie,
\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0]_0 );
output p_15_in;
output p_17_in;
output [0:0]s_axi_rresp;
output \mer_int_reg[0] ;
output s_axi_rvalid;
output s_axi_bvalid;
output [0:0]s_axi_bresp;
output s_axi_wready;
output s_axi_arready;
output ip2bus_wrack_prev2;
output ip2bus_rdack_prev2;
output Or128_vec2stdlogic19_out;
output \mer_int_reg[0]_0 ;
output \mer_int_reg[1] ;
output \SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ;
output \CIE_GEN.CIE_BIT_GEN[0].cie_reg[0] ;
output \REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0] ;
output ip2bus_wrack_int_d1_reg;
output [2:0]s_axi_rdata;
input s_axi_aresetn_0;
input s_axi_aclk;
input s_axi_arvalid;
input ip2bus_wrack;
input s_axi_aresetn;
input ip2bus_rdack;
input s_axi_rready;
input s_axi_bready;
input s_axi_wvalid;
input s_axi_awvalid;
input [6:0]s_axi_araddr;
input [6:0]s_axi_awaddr;
input [0:0]ipr;
input ier;
input ivr;
input p_0_in;
input \mer_int_reg[0]_1 ;
input isr;
input ip2bus_wrack_int_d1;
input ip2bus_rdack_int_d1;
input [3:0]s_axi_wstrb;
input [1:0]s_axi_wdata;
input sie;
input cie;
input \REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0]_0 ;
wire \CIE_GEN.CIE_BIT_GEN[0].cie_reg[0] ;
wire \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1_n_0 ;
wire [3:0]\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 ;
wire [31:0]IP2Bus_Data;
wire Or128_vec2stdlogic19_out;
wire \REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0] ;
wire \REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0]_0 ;
wire \SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ;
wire [8:2]bus2ip_addr;
wire \bus2ip_addr_i[2]_i_1_n_0 ;
wire \bus2ip_addr_i[3]_i_1_n_0 ;
wire \bus2ip_addr_i[4]_i_1_n_0 ;
wire \bus2ip_addr_i[5]_i_1_n_0 ;
wire \bus2ip_addr_i[6]_i_1_n_0 ;
wire \bus2ip_addr_i[7]_i_1_n_0 ;
wire \bus2ip_addr_i[8]_i_1_n_0 ;
wire \bus2ip_addr_i[8]_i_2_n_0 ;
wire bus2ip_rnw_i06_out;
wire bus2ip_rnw_i_reg_n_0;
wire cie;
wire ier;
wire ip2bus_error;
wire ip2bus_rdack;
wire ip2bus_rdack_int_d1;
wire ip2bus_rdack_prev2;
wire ip2bus_wrack;
wire ip2bus_wrack_int_d1;
wire ip2bus_wrack_int_d1_reg;
wire ip2bus_wrack_prev2;
wire [0:0]ipr;
wire is_read;
wire is_read_i_1_n_0;
wire is_read_i_2_n_0;
wire is_write_i_1_n_0;
wire is_write_reg_n_0;
wire isr;
wire ivr;
wire \mer_int_reg[0] ;
wire \mer_int_reg[0]_0 ;
wire \mer_int_reg[0]_1 ;
wire \mer_int_reg[1] ;
wire p_0_in;
wire p_15_in;
wire p_17_in;
wire [3:0]plusOp;
wire rst;
wire s_axi_aclk;
wire [6:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_aresetn_0;
wire s_axi_arready;
wire s_axi_arvalid;
wire [6:0]s_axi_awaddr;
wire s_axi_awvalid;
wire s_axi_bready;
wire [0:0]s_axi_bresp;
wire \s_axi_bresp_i[1]_i_1_n_0 ;
wire s_axi_bvalid;
wire s_axi_bvalid_i_i_1_n_0;
wire [2:0]s_axi_rdata;
wire s_axi_rdata_i;
wire \s_axi_rdata_i[0]_i_3_n_0 ;
wire \s_axi_rdata_i[0]_i_4_n_0 ;
wire \s_axi_rdata_i[1]_i_2_n_0 ;
wire \s_axi_rdata_i[31]_i_5_n_0 ;
wire s_axi_rready;
wire [0:0]s_axi_rresp;
wire s_axi_rvalid;
wire s_axi_rvalid_i_i_1_n_0;
wire [1:0]s_axi_wdata;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
wire sie;
wire start2;
wire start2_i_1_n_0;
wire [1:0]state;
wire \state[0]_i_1_n_0 ;
wire \state[0]_i_2_n_0 ;
wire \state[1]_i_1_n_0 ;
wire \state[1]_i_2_n_0 ;
wire \state[1]_i_3_n_0 ;
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT1 #(
.INIT(2'h1))
\INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.O(plusOp[0]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT2 #(
.INIT(4'h6))
\INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.O(plusOp[1]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'h78))
\INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
.O(plusOp[2]));
LUT2 #(
.INIT(4'h9))
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1
(.I0(state[1]),
.I1(state[0]),
.O(\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT4 #(
.INIT(16'h6AAA))
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.I3(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
.O(plusOp[3]));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[0]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.R(\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1_n_0 ));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[1]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.R(\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1_n_0 ));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[2]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
.R(\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1_n_0 ));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[3]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]),
.R(\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1_n_0 ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder I_DECODER
(.\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0] (\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0] ),
.D({IP2Bus_Data[31],IP2Bus_Data[1:0]}),
.\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] (\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 ),
.\IPR_GEN.ipr_reg[0] (\s_axi_rdata_i[0]_i_3_n_0 ),
.\IVR_GEN.ivr_reg[0] (\s_axi_rdata_i[1]_i_2_n_0 ),
.Or128_vec2stdlogic19_out(Or128_vec2stdlogic19_out),
.Q(start2),
.\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0] (\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0] ),
.\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0]_0 (\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0]_0 ),
.\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] (\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ),
.\bus2ip_addr_i_reg[2] (\s_axi_rdata_i[31]_i_5_n_0 ),
.\bus2ip_addr_i_reg[3] (\s_axi_rdata_i[0]_i_4_n_0 ),
.\bus2ip_addr_i_reg[8] (bus2ip_addr),
.bus2ip_rnw_i_reg(bus2ip_rnw_i_reg_n_0),
.cie(cie),
.ip2bus_rdack(ip2bus_rdack),
.ip2bus_rdack_int_d1(ip2bus_rdack_int_d1),
.ip2bus_rdack_prev2(ip2bus_rdack_prev2),
.ip2bus_wrack(ip2bus_wrack),
.ip2bus_wrack_int_d1(ip2bus_wrack_int_d1),
.ip2bus_wrack_int_d1_reg(ip2bus_wrack_int_d1_reg),
.ip2bus_wrack_prev2(ip2bus_wrack_prev2),
.is_read(is_read),
.is_write_reg(is_write_reg_n_0),
.\mer_int_reg[0] (\mer_int_reg[0] ),
.\mer_int_reg[0]_0 (\mer_int_reg[0]_0 ),
.\mer_int_reg[0]_1 (\mer_int_reg[0]_1 ),
.\mer_int_reg[1] (\mer_int_reg[1] ),
.p_0_in(p_0_in),
.p_15_in(p_15_in),
.p_17_in(p_17_in),
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_wdata(s_axi_wdata),
.sie(sie));
LUT5 #(
.INIT(32'hFFEF0020))
\bus2ip_addr_i[2]_i_1
(.I0(s_axi_araddr[0]),
.I1(state[1]),
.I2(s_axi_arvalid),
.I3(state[0]),
.I4(s_axi_awaddr[0]),
.O(\bus2ip_addr_i[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT5 #(
.INIT(32'hFFEF0020))
\bus2ip_addr_i[3]_i_1
(.I0(s_axi_araddr[1]),
.I1(state[1]),
.I2(s_axi_arvalid),
.I3(state[0]),
.I4(s_axi_awaddr[1]),
.O(\bus2ip_addr_i[3]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFEF0020))
\bus2ip_addr_i[4]_i_1
(.I0(s_axi_araddr[2]),
.I1(state[1]),
.I2(s_axi_arvalid),
.I3(state[0]),
.I4(s_axi_awaddr[2]),
.O(\bus2ip_addr_i[4]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFEF0020))
\bus2ip_addr_i[5]_i_1
(.I0(s_axi_araddr[3]),
.I1(state[1]),
.I2(s_axi_arvalid),
.I3(state[0]),
.I4(s_axi_awaddr[3]),
.O(\bus2ip_addr_i[5]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFEF0020))
\bus2ip_addr_i[6]_i_1
(.I0(s_axi_araddr[4]),
.I1(state[1]),
.I2(s_axi_arvalid),
.I3(state[0]),
.I4(s_axi_awaddr[4]),
.O(\bus2ip_addr_i[6]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFEF0020))
\bus2ip_addr_i[7]_i_1
(.I0(s_axi_araddr[5]),
.I1(state[1]),
.I2(s_axi_arvalid),
.I3(state[0]),
.I4(s_axi_awaddr[5]),
.O(\bus2ip_addr_i[7]_i_1_n_0 ));
LUT5 #(
.INIT(32'h000000EA))
\bus2ip_addr_i[8]_i_1
(.I0(s_axi_arvalid),
.I1(s_axi_wvalid),
.I2(s_axi_awvalid),
.I3(state[1]),
.I4(state[0]),
.O(\bus2ip_addr_i[8]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFEF0020))
\bus2ip_addr_i[8]_i_2
(.I0(s_axi_araddr[6]),
.I1(state[1]),
.I2(s_axi_arvalid),
.I3(state[0]),
.I4(s_axi_awaddr[6]),
.O(\bus2ip_addr_i[8]_i_2_n_0 ));
FDRE \bus2ip_addr_i_reg[2]
(.C(s_axi_aclk),
.CE(\bus2ip_addr_i[8]_i_1_n_0 ),
.D(\bus2ip_addr_i[2]_i_1_n_0 ),
.Q(bus2ip_addr[2]),
.R(rst));
FDRE \bus2ip_addr_i_reg[3]
(.C(s_axi_aclk),
.CE(\bus2ip_addr_i[8]_i_1_n_0 ),
.D(\bus2ip_addr_i[3]_i_1_n_0 ),
.Q(bus2ip_addr[3]),
.R(rst));
FDRE \bus2ip_addr_i_reg[4]
(.C(s_axi_aclk),
.CE(\bus2ip_addr_i[8]_i_1_n_0 ),
.D(\bus2ip_addr_i[4]_i_1_n_0 ),
.Q(bus2ip_addr[4]),
.R(rst));
FDRE \bus2ip_addr_i_reg[5]
(.C(s_axi_aclk),
.CE(\bus2ip_addr_i[8]_i_1_n_0 ),
.D(\bus2ip_addr_i[5]_i_1_n_0 ),
.Q(bus2ip_addr[5]),
.R(rst));
FDRE \bus2ip_addr_i_reg[6]
(.C(s_axi_aclk),
.CE(\bus2ip_addr_i[8]_i_1_n_0 ),
.D(\bus2ip_addr_i[6]_i_1_n_0 ),
.Q(bus2ip_addr[6]),
.R(rst));
FDRE \bus2ip_addr_i_reg[7]
(.C(s_axi_aclk),
.CE(\bus2ip_addr_i[8]_i_1_n_0 ),
.D(\bus2ip_addr_i[7]_i_1_n_0 ),
.Q(bus2ip_addr[7]),
.R(rst));
FDRE \bus2ip_addr_i_reg[8]
(.C(s_axi_aclk),
.CE(\bus2ip_addr_i[8]_i_1_n_0 ),
.D(\bus2ip_addr_i[8]_i_2_n_0 ),
.Q(bus2ip_addr[8]),
.R(rst));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'h04))
bus2ip_rnw_i_i_1
(.I0(state[1]),
.I1(s_axi_arvalid),
.I2(state[0]),
.O(bus2ip_rnw_i06_out));
FDRE bus2ip_rnw_i_reg
(.C(s_axi_aclk),
.CE(\bus2ip_addr_i[8]_i_1_n_0 ),
.D(bus2ip_rnw_i06_out),
.Q(bus2ip_rnw_i_reg_n_0),
.R(rst));
LUT4 #(
.INIT(16'h2F20))
is_read_i_1
(.I0(s_axi_arvalid),
.I1(state[1]),
.I2(is_read_i_2_n_0),
.I3(is_read),
.O(is_read_i_1_n_0));
LUT6 #(
.INIT(64'hAA80808055555555))
is_read_i_2
(.I0(state[0]),
.I1(s_axi_bready),
.I2(s_axi_bvalid),
.I3(s_axi_rready),
.I4(s_axi_rvalid),
.I5(state[1]),
.O(is_read_i_2_n_0));
FDRE is_read_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(is_read_i_1_n_0),
.Q(is_read),
.R(rst));
LUT6 #(
.INIT(64'h0040FFFF00400000))
is_write_i_1
(.I0(state[1]),
.I1(s_axi_wvalid),
.I2(s_axi_awvalid),
.I3(s_axi_arvalid),
.I4(is_read_i_2_n_0),
.I5(is_write_reg_n_0),
.O(is_write_i_1_n_0));
FDRE is_write_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(is_write_i_1_n_0),
.Q(is_write_reg_n_0),
.R(rst));
FDRE rst_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_axi_aresetn_0),
.Q(rst),
.R(1'b0));
LUT6 #(
.INIT(64'hAAAAAAAEAAAAAAAA))
s_axi_arready_INST_0
(.I0(ip2bus_rdack),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
.I3(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.I4(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.I5(is_read),
.O(s_axi_arready));
LUT4 #(
.INIT(16'hFB08))
\s_axi_bresp_i[1]_i_1
(.I0(ip2bus_error),
.I1(state[1]),
.I2(state[0]),
.I3(s_axi_bresp),
.O(\s_axi_bresp_i[1]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\s_axi_bresp_i_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\s_axi_bresp_i[1]_i_1_n_0 ),
.Q(s_axi_bresp),
.R(rst));
LUT5 #(
.INIT(32'h5D550C00))
s_axi_bvalid_i_i_1
(.I0(s_axi_bready),
.I1(state[1]),
.I2(state[0]),
.I3(s_axi_wready),
.I4(s_axi_bvalid),
.O(s_axi_bvalid_i_i_1_n_0));
FDRE #(
.INIT(1'b0))
s_axi_bvalid_i_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_axi_bvalid_i_i_1_n_0),
.Q(s_axi_bvalid),
.R(rst));
LUT6 #(
.INIT(64'h000000000300A0A0))
\s_axi_rdata_i[0]_i_3
(.I0(ipr),
.I1(bus2ip_addr[5]),
.I2(bus2ip_addr[2]),
.I3(ier),
.I4(bus2ip_addr[3]),
.I5(bus2ip_addr[4]),
.O(\s_axi_rdata_i[0]_i_3_n_0 ));
LUT6 #(
.INIT(64'h0000000081018000))
\s_axi_rdata_i[0]_i_4
(.I0(bus2ip_addr[3]),
.I1(bus2ip_addr[4]),
.I2(bus2ip_addr[2]),
.I3(\mer_int_reg[0]_1 ),
.I4(isr),
.I5(bus2ip_addr[5]),
.O(\s_axi_rdata_i[0]_i_4_n_0 ));
LUT6 #(
.INIT(64'hCDFDFFFFFFFF3F3F))
\s_axi_rdata_i[1]_i_2
(.I0(ivr),
.I1(bus2ip_addr[5]),
.I2(bus2ip_addr[2]),
.I3(p_0_in),
.I4(bus2ip_addr[3]),
.I5(bus2ip_addr[4]),
.O(\s_axi_rdata_i[1]_i_2_n_0 ));
LUT2 #(
.INIT(4'h2))
\s_axi_rdata_i[31]_i_1
(.I0(state[0]),
.I1(state[1]),
.O(s_axi_rdata_i));
LUT5 #(
.INIT(32'hEFFFFF77))
\s_axi_rdata_i[31]_i_5
(.I0(bus2ip_addr[2]),
.I1(bus2ip_addr[5]),
.I2(ivr),
.I3(bus2ip_addr[3]),
.I4(bus2ip_addr[4]),
.O(\s_axi_rdata_i[31]_i_5_n_0 ));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[0]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[0]),
.Q(s_axi_rdata[0]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[1]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[1]),
.Q(s_axi_rdata[1]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[31]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[31]),
.Q(s_axi_rdata[2]),
.R(rst));
LUT5 #(
.INIT(32'h070F0F0F))
\s_axi_rresp_i[1]_i_1
(.I0(s_axi_wstrb[1]),
.I1(s_axi_wstrb[2]),
.I2(bus2ip_rnw_i_reg_n_0),
.I3(s_axi_wstrb[0]),
.I4(s_axi_wstrb[3]),
.O(ip2bus_error));
FDRE #(
.INIT(1'b0))
\s_axi_rresp_i_reg[1]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(ip2bus_error),
.Q(s_axi_rresp),
.R(rst));
LUT5 #(
.INIT(32'h5D550C00))
s_axi_rvalid_i_i_1
(.I0(s_axi_rready),
.I1(state[0]),
.I2(state[1]),
.I3(s_axi_arready),
.I4(s_axi_rvalid),
.O(s_axi_rvalid_i_i_1_n_0));
FDRE #(
.INIT(1'b0))
s_axi_rvalid_i_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_axi_rvalid_i_i_1_n_0),
.Q(s_axi_rvalid),
.R(rst));
LUT6 #(
.INIT(64'hAAAAAAAEAAAAAAAA))
s_axi_wready_INST_0
(.I0(ip2bus_wrack),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
.I3(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.I4(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.I5(is_write_reg_n_0),
.O(s_axi_wready));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT5 #(
.INIT(32'h00000F08))
start2_i_1
(.I0(s_axi_wvalid),
.I1(s_axi_awvalid),
.I2(state[0]),
.I3(s_axi_arvalid),
.I4(state[1]),
.O(start2_i_1_n_0));
FDRE start2_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(start2_i_1_n_0),
.Q(start2),
.R(rst));
LUT5 #(
.INIT(32'hF4F4FFF0))
\state[0]_i_1
(.I0(state[0]),
.I1(s_axi_wready),
.I2(\state[0]_i_2_n_0 ),
.I3(s_axi_arvalid),
.I4(state[1]),
.O(\state[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'h557F7F7F00000000))
\state[0]_i_2
(.I0(state[1]),
.I1(s_axi_rvalid),
.I2(s_axi_rready),
.I3(s_axi_bvalid),
.I4(s_axi_bready),
.I5(state[0]),
.O(\state[0]_i_2_n_0 ));
LUT5 #(
.INIT(32'h22CFEECF))
\state[1]_i_1
(.I0(s_axi_arready),
.I1(state[1]),
.I2(\state[1]_i_2_n_0 ),
.I3(state[0]),
.I4(\state[1]_i_3_n_0 ),
.O(\state[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'hBF))
\state[1]_i_2
(.I0(s_axi_arvalid),
.I1(s_axi_awvalid),
.I2(s_axi_wvalid),
.O(\state[1]_i_2_n_0 ));
LUT4 #(
.INIT(16'hF888))
\state[1]_i_3
(.I0(s_axi_rvalid),
.I1(s_axi_rready),
.I2(s_axi_bvalid),
.I3(s_axi_bready),
.O(\state[1]_i_3_n_0 ));
FDRE \state_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\state[0]_i_1_n_0 ),
.Q(state[0]),
.R(rst));
FDRE \state_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\state[1]_i_1_n_0 ),
.Q(state[1]),
.R(rst));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
module exec(
lsu_rd_wfid,
salu_wr_exec_en,
salu_wr_vcc_en,
salu_wr_exec_value,
salu_wr_vcc_value,
salu_wr_wfid,
salu_rd_en,
salu_rd_wfid,
salu_wr_m0_en,
salu_wr_m0_value,
salu_wr_scc_en,
salu_wr_scc_value,
simd0_rd_wfid,
simd1_rd_wfid,
simd2_rd_wfid,
simd3_rd_wfid,
simd0_rd_en,
simd1_rd_en,
simd2_rd_en,
simd3_rd_en,
simd0_vcc_wr_wfid,
simd1_vcc_wr_wfid,
simd2_vcc_wr_wfid,
simd3_vcc_wr_wfid,
simd0_vcc_wr_en,
simd1_vcc_wr_en,
simd2_vcc_wr_en,
simd3_vcc_wr_en,
simd0_vcc_value,
simd1_vcc_value,
simd2_vcc_value,
simd3_vcc_value,
simf0_rd_wfid,
simf1_rd_wfid,
simf2_rd_wfid,
simf3_rd_wfid,
simf0_rd_en,
simf1_rd_en,
simf2_rd_en,
simf3_rd_en,
simf0_vcc_wr_wfid,
simf1_vcc_wr_wfid,
simf2_vcc_wr_wfid,
simf3_vcc_wr_wfid,
simf0_vcc_wr_en,
simf1_vcc_wr_en,
simf2_vcc_wr_en,
simf3_vcc_wr_en,
simf0_vcc_value,
simf1_vcc_value,
simf2_vcc_value,
simf3_vcc_value,
fetch_init_wf_en,
fetch_init_wf_id,
fetch_init_value,
rfa_select_fu,
lsu_exec_value,
lsu_rd_m0_value,
simd_rd_exec_value,
simd_rd_vcc_value,
simd_rd_m0_value,
simd_rd_scc_value,
simf_rd_exec_value,
simf_rd_vcc_value,
simf_rd_m0_value,
simf_rd_scc_value,
salu_rd_exec_value,
salu_rd_vcc_value,
salu_rd_m0_value,
salu_rd_scc_value,
issue_salu_wr_vcc_wfid,
issue_salu_wr_vcc_en,
issue_salu_wr_exec_en,
issue_salu_wr_m0_en,
issue_salu_wr_scc_en,
issue_valu_wr_vcc_wfid,
issue_valu_wr_vcc_en,
clk,
rst
);
input clk;
input rst;
input salu_wr_exec_en, salu_wr_vcc_en, salu_rd_en, salu_wr_m0_en, salu_wr_scc_en,
salu_wr_scc_value, simd0_rd_en, simd1_rd_en, simd2_rd_en, simd3_rd_en,
simd0_vcc_wr_en, simd1_vcc_wr_en, simd2_vcc_wr_en, simd3_vcc_wr_en,
simf0_rd_en, simf1_rd_en, simf2_rd_en, simf3_rd_en, simf0_vcc_wr_en,
simf1_vcc_wr_en, simf2_vcc_wr_en, simf3_vcc_wr_en, fetch_init_wf_en;
input[5:0] lsu_rd_wfid, salu_wr_wfid, salu_rd_wfid, simd0_rd_wfid, simd1_rd_wfid,
simd2_rd_wfid, simd3_rd_wfid, simd0_vcc_wr_wfid, simd1_vcc_wr_wfid,
simd2_vcc_wr_wfid, simd3_vcc_wr_wfid, simf0_rd_wfid, simf1_rd_wfid,
simf2_rd_wfid, simf3_rd_wfid, simf0_vcc_wr_wfid, simf1_vcc_wr_wfid,
simf2_vcc_wr_wfid, simf3_vcc_wr_wfid, fetch_init_wf_id;
input[15:0] rfa_select_fu;
input[31:0] salu_wr_m0_value;
input[63:0] salu_wr_exec_value, salu_wr_vcc_value, simd0_vcc_value,
simd1_vcc_value, simd2_vcc_value, simd3_vcc_value, simf0_vcc_value,
simf1_vcc_value, simf2_vcc_value, simf3_vcc_value, fetch_init_value;
output simd_rd_scc_value, simf_rd_scc_value, salu_rd_scc_value, issue_salu_wr_vcc_en,
issue_salu_wr_exec_en, issue_salu_wr_m0_en, issue_salu_wr_scc_en, issue_valu_wr_vcc_en;
output[5:0] issue_salu_wr_vcc_wfid, issue_valu_wr_vcc_wfid;
output[31:0] lsu_rd_m0_value, simd_rd_m0_value, simf_rd_m0_value, salu_rd_m0_value;
output[63:0] lsu_exec_value, simd_rd_exec_value, simd_rd_vcc_value,
simf_rd_exec_value, simf_rd_vcc_value, salu_rd_exec_value, salu_rd_vcc_value;
wire[5:0] alu_rd_wfid;
wire vcc_simd_wr_en;
wire[5:0] vcc_simd_wr_addr;
wire[63:0] vcc_simd_wr_data;
wire lsu_rd_scc_value; //if needed in future
wire[63:0] lsu_rd_vcc_value; //if needed in future
assign salu_rd_exec_value = simd_rd_exec_value;
assign salu_rd_vcc_value = simd_rd_vcc_value;
assign salu_rd_m0_value = simd_rd_m0_value;
assign salu_rd_scc_value = simd_rd_scc_value;
assign simf_rd_exec_value = simd_rd_exec_value;
assign simf_rd_vcc_value = simd_rd_vcc_value;
assign simf_rd_m0_value = simd_rd_m0_value;
assign simf_rd_scc_value = simd_rd_scc_value;
rd_port_9_to_1 #(6) alu_rd_port_mux(
.port0_rd_en(simd0_rd_en),
.port0_rd_addr(simd0_rd_wfid),
.port1_rd_en(simd1_rd_en),
.port1_rd_addr(simd1_rd_wfid),
.port2_rd_en(simd2_rd_en),
.port2_rd_addr(simd2_rd_wfid),
.port3_rd_en(simd3_rd_en),
.port3_rd_addr(simd3_rd_wfid),
.port4_rd_en(simf0_rd_en),
.port4_rd_addr(simf0_rd_wfid),
.port5_rd_en(simf1_rd_en),
.port5_rd_addr(simf1_rd_wfid),
.port6_rd_en(simf2_rd_en),
.port6_rd_addr(simf2_rd_wfid),
.port7_rd_en(simf3_rd_en),
.port7_rd_addr(simf3_rd_wfid),
.port8_rd_en(salu_rd_en),
.port8_rd_addr(salu_rd_wfid),
.rd_addr(alu_rd_wfid)
);
wr_port_40x64b_8_to_1 vcc_wr_port_mux(
.select(rfa_select_fu[7:0]),
.port0_wr_en(simd0_vcc_wr_en),
.port0_wr_addr(simd0_vcc_wr_wfid),
.port0_wr_data(simd0_vcc_value),
.port1_wr_en(simd1_vcc_wr_en),
.port1_wr_addr(simd1_vcc_wr_wfid),
.port1_wr_data(simd1_vcc_value),
.port2_wr_en(simd2_vcc_wr_en),
.port2_wr_addr(simd2_vcc_wr_wfid),
.port2_wr_data(simd2_vcc_value),
.port3_wr_en(simd3_vcc_wr_en),
.port3_wr_addr(simd3_vcc_wr_wfid),
.port3_wr_data(simd3_vcc_value),
.port4_wr_en(simf0_vcc_wr_en),
.port4_wr_addr(simf0_vcc_wr_wfid),
.port4_wr_data(simf0_vcc_value),
.port5_wr_en(simf1_vcc_wr_en),
.port5_wr_addr(simf1_vcc_wr_wfid),
.port5_wr_data(simf1_vcc_value),
.port6_wr_en(simf2_vcc_wr_en),
.port6_wr_addr(simf2_vcc_wr_wfid),
.port6_wr_data(simf2_vcc_value),
.port7_wr_en(simf3_vcc_wr_en),
.port7_wr_addr(simf3_vcc_wr_wfid),
.port7_wr_data(simf3_vcc_value),
.muxed_port_wr_en(vcc_simd_wr_en),
.muxed_port_wr_addr(vcc_simd_wr_addr),
.muxed_port_wr_data(vcc_simd_wr_data)
);
// m0
reg_40xX_2r_2w #(32) m0_file(
.rd0_addr(alu_rd_wfid),
.rd0_data(simd_rd_m0_value),
.rd1_addr(lsu_rd_wfid),
.rd1_data(lsu_rd_m0_value),
.wr0_en(fetch_init_wf_en),
.wr0_addr(fetch_init_wf_id),
.wr0_data(32'd0),
.wr1_en(salu_wr_m0_en),
.wr1_addr(salu_wr_wfid),
.wr1_data(salu_wr_m0_value),
.clk(clk),
.rst(rst)
);
// scc
reg_40xX_2r_2w #(1) scc_file(
.rd0_addr(alu_rd_wfid),
.rd0_data(simd_rd_scc_value),
.rd1_addr(lsu_rd_wfid),
.rd1_data(lsu_rd_scc_value),
.wr0_en(fetch_init_wf_en),
.wr0_addr(fetch_init_wf_id),
.wr0_data(1'b0),
.wr1_en(salu_wr_scc_en),
.wr1_addr(salu_wr_wfid),
.wr1_data(salu_wr_scc_value),
.clk(clk),
.rst(rst)
);
// vcc
reg_40xX_2r_3w #(64) vcc_file(
.rd0_addr(alu_rd_wfid),
.rd0_data(simd_rd_vcc_value),
.rd1_addr(lsu_rd_wfid),
.rd1_data(lsu_rd_vcc_value),
.wr0_en(fetch_init_wf_en),
.wr0_addr(fetch_init_wf_id),
.wr0_data(64'd0),
.wr1_en(vcc_simd_wr_en),
.wr1_addr(vcc_simd_wr_addr),
.wr1_data(vcc_simd_wr_data),
.wr2_en(salu_wr_vcc_en),
.wr2_addr(salu_wr_wfid),
.wr2_data(salu_wr_vcc_value),
.clk(clk),
.rst(rst)
);
// exec
reg_40xX_2r_2w #(64) exec_file(
.rd0_addr(alu_rd_wfid),
.rd0_data(simd_rd_exec_value),
.rd1_addr(lsu_rd_wfid),
.rd1_data(lsu_exec_value),
.wr0_en(fetch_init_wf_en),
.wr0_addr(fetch_init_wf_id),
.wr0_data(fetch_init_value),
.wr1_en(salu_wr_exec_en),
.wr1_addr(salu_wr_wfid),
.wr1_data(salu_wr_exec_value),
.clk(clk),
.rst(rst)
);
///////////////////////////////
assign issue_salu_wr_vcc_wfid = salu_wr_wfid;
assign issue_salu_wr_vcc_en = salu_wr_vcc_en;
assign issue_valu_wr_vcc_wfid = vcc_simd_wr_addr;
assign issue_valu_wr_vcc_en = vcc_simd_wr_en;
assign issue_salu_wr_exec_en = salu_wr_exec_en;
assign issue_salu_wr_m0_en = salu_wr_m0_en;
assign issue_salu_wr_scc_en = salu_wr_scc_en;
///////////////////////////////
endmodule
|
module tube_ula(
DACK
, DRQ
, HA0
, HA1
, HA2
, HCS
, HD0IN
, HD0OUT
, HD1IN
, HD1OUT
, HD2IN
, HD2OUT
, HD3IN
, HD3OUT
, HD4IN
, HD4OUT
, HD5IN
, HD5OUT
, HD6IN
, HD6OUT
, HD7IN
, HD7OUT
, HDOE
, HIRQ
, HO2
, HRST
, HRW
, PA0
, PA1
, PA2
, PCS
, PD0IN
, PD0OUT
, PD1IN
, PD1OUT
, PD2IN
, PD2OUT
, PD3IN
, PD3OUT
, PD4IN
, PD4OUT
, PD5IN
, PD5OUT
, PD6IN
, PD6OUT
, PD7IN
, PD7OUT
, PDOE
, PIRQ
, PNMI
, PNRDS
, PNWDS
, PRST
);
// Inputs
input DACK;
input HA0;
input HA1;
input HA2;
input HCS;
input HD0IN;
input HD1IN;
input HD2IN;
input HD3IN;
input HD4IN;
input HD5IN;
input HD6IN;
input HD7IN;
input HO2;
input HRST;
input HRW;
input PA0;
input PA1;
input PA2;
input PCS;
input PD0IN;
input PD1IN;
input PD2IN;
input PD3IN;
input PD4IN;
input PD5IN;
input PD6IN;
input PD7IN;
input PNRDS;
input PNWDS;
// Outputs
output DRQ;
output HD0OUT;
output HD1OUT;
output HD2OUT;
output HD3OUT;
output HD4OUT;
output HD5OUT;
output HD6OUT;
output HD7OUT;
output HDOE;
output HIRQ;
output PD0OUT;
output PD1OUT;
output PD2OUT;
output PD3OUT;
output PD4OUT;
output PD5OUT;
output PD6OUT;
output PD7OUT;
output PDOE;
output PIRQ;
output PNMI;
output PRST;
// Wires
wire HDOEA;
wire N1002;
wire N1003;
wire N1004;
wire N1035;
wire N1036;
wire N1037;
wire N1038;
wire N1039;
wire N1040;
wire N1041;
wire N1042;
wire N1043;
wire N1044;
wire N1046;
wire N1047;
wire N1048;
wire N1049;
wire N1050;
wire N1051;
wire N1052;
wire N1053;
wire N1056;
wire N1057;
wire N1058;
wire N1059;
wire N1060;
wire N1061;
wire N1062;
wire N1063;
wire N1064;
wire N1065;
wire N1066;
wire N1067;
wire N1068;
wire N1069;
wire N1070;
wire N1071;
wire N1072;
wire N1073;
wire N1074;
wire N1075;
wire N1076;
wire N1077;
wire N1078;
wire N1079;
wire N1080;
wire N1081;
wire N1082;
wire N1083;
wire N1084;
wire N1085;
wire N1086;
wire N1087;
wire N1089;
wire N1091;
wire N1093;
wire N1095;
wire N1097;
wire N1115;
wire N1117;
wire N1119;
wire N1121;
wire N1123;
wire N1125;
wire N1126;
wire N115;
wire N1155;
wire N116;
wire N117;
wire N118;
wire N1187;
wire N1188;
wire N1189;
wire N119;
wire N1190;
wire N1191;
wire N1192;
wire N1193;
wire N1194;
wire N1195;
wire N1196;
wire N1197;
wire N1198;
wire N1199;
wire N120;
wire N1200;
wire N1201;
wire N1202;
wire N1203;
wire N1204;
wire N1205;
wire N1206;
wire N1208;
wire N1209;
wire N121;
wire N1210;
wire N1211;
wire N1212;
wire N1213;
wire N1214;
wire N1215;
wire N1216;
wire N122;
wire N1226;
wire N1229;
wire N123;
wire N1232;
wire N1235;
wire N1238;
wire N124;
wire N1241;
wire N1244;
wire N1247;
wire N125;
wire N126;
wire N127;
wire N1313;
wire N1314;
wire N1315;
wire N1316;
wire N1317;
wire N1318;
wire N1319;
wire N1320;
wire N1321;
wire N1326;
wire N1327;
wire N1328;
wire N1329;
wire N1332;
wire N1335;
wire N1336;
wire N1339;
wire N1343;
wire N1346;
wire N1349;
wire N1396;
wire N1398;
wire N1399;
wire N140;
wire N141;
wire N1430;
wire N1431;
wire N1432;
wire N1433;
wire N1434;
wire N1435;
wire N1436;
wire N1437;
wire N1438;
wire N1439;
wire N1440;
wire N1441;
wire N1442;
wire N1443;
wire N1444;
wire N1445;
wire N1446;
wire N1447;
wire N1448;
wire N1449;
wire N1450;
wire N1451;
wire N1452;
wire N1453;
wire N1455;
wire N1456;
wire N1457;
wire N1458;
wire N1464;
wire N1466;
wire N1468;
wire N1470;
wire N1472;
wire N1474;
wire N1476;
wire N1478;
wire N1480;
wire N1482;
wire N1484;
wire N1486;
wire N1488;
wire N1490;
wire N1492;
wire N1494;
wire N1496;
wire N1498;
wire N1536;
wire N1537;
wire N1538;
wire N1570;
wire N1571;
wire N1572;
wire N1573;
wire N1574;
wire N1575;
wire N1576;
wire N1577;
wire N1578;
wire N1579;
wire N1580;
wire N1581;
wire N1582;
wire N1583;
wire N1584;
wire N1585;
wire N1586;
wire N1587;
wire N1588;
wire N1589;
wire N1590;
wire N1591;
wire N1592;
wire N1593;
wire N1594;
wire N1595;
wire N1596;
wire N1597;
wire N1598;
wire N1599;
wire N1600;
wire N1601;
wire N1602;
wire N1603;
wire N1604;
wire N1605;
wire N1606;
wire N1607;
wire N1608;
wire N1609;
wire N1610;
wire N1611;
wire N1612;
wire N1613;
wire N1614;
wire N1616;
wire N1617;
wire N1618;
wire N1619;
wire N1620;
wire N1622;
wire N1624;
wire N1626;
wire N1628;
wire N1630;
wire N1649;
wire N1651;
wire N1653;
wire N1655;
wire N1657;
wire N1687;
wire N1688;
wire N1719;
wire N1720;
wire N1721;
wire N1722;
wire N1723;
wire N1724;
wire N1725;
wire N1726;
wire N1727;
wire N1728;
wire N1729;
wire N1730;
wire N1731;
wire N1732;
wire N1733;
wire N1734;
wire N1735;
wire N1736;
wire N1737;
wire N1738;
wire N1739;
wire N1740;
wire N1741;
wire N1742;
wire N1743;
wire N1744;
wire N1745;
wire N1746;
wire N1748;
wire N175;
wire N1750;
wire N1759;
wire N176;
wire N1762;
wire N1765;
wire N1768;
wire N177;
wire N1771;
wire N1774;
wire N1777;
wire N1780;
wire N1817;
wire N1848;
wire N1849;
wire N1850;
wire N1851;
wire N1852;
wire N1853;
wire N1854;
wire N1855;
wire N1856;
wire N1857;
wire N1858;
wire N1859;
wire N1860;
wire N1861;
wire N1862;
wire N1863;
wire N1864;
wire N1865;
wire N1866;
wire N1867;
wire N1868;
wire N1869;
wire N1870;
wire N1871;
wire N1872;
wire N1873;
wire N1874;
wire N1875;
wire N1876;
wire N1877;
wire N1879;
wire N1882;
wire N1884;
wire N1886;
wire N1888;
wire N1890;
wire N1892;
wire N1894;
wire N1896;
wire N1898;
wire N1900;
wire N1902;
wire N1904;
wire N1906;
wire N1908;
wire N1910;
wire N1912;
wire N1914;
wire N1916;
wire N1955;
wire N1956;
wire N1988;
wire N1989;
wire N1990;
wire N1991;
wire N1992;
wire N1993;
wire N1994;
wire N1995;
wire N1996;
wire N1997;
wire N1998;
wire N1999;
wire N2000;
wire N2001;
wire N2002;
wire N2003;
wire N2004;
wire N2005;
wire N2006;
wire N2007;
wire N2008;
wire N2009;
wire N2010;
wire N2011;
wire N2012;
wire N2013;
wire N2014;
wire N2015;
wire N2016;
wire N2017;
wire N2018;
wire N2019;
wire N2020;
wire N2021;
wire N2022;
wire N2023;
wire N2024;
wire N2025;
wire N2026;
wire N2027;
wire N2028;
wire N2029;
wire N2030;
wire N2031;
wire N2032;
wire N2033;
wire N2034;
wire N2035;
wire N2036;
wire N2037;
wire N2038;
wire N2039;
wire N2040;
wire N2042;
wire N2044;
wire N2046;
wire N2048;
wire N2050;
wire N2069;
wire N207;
wire N2071;
wire N2073;
wire N2075;
wire N2077;
wire N2079;
wire N208;
wire N209;
wire N210;
wire N211;
wire N212;
wire N213;
wire N214;
wire N2140;
wire N2141;
wire N2142;
wire N2143;
wire N2144;
wire N2145;
wire N2146;
wire N2147;
wire N2148;
wire N2149;
wire N215;
wire N2150;
wire N2151;
wire N2152;
wire N2153;
wire N2154;
wire N2155;
wire N2156;
wire N2157;
wire N2158;
wire N2159;
wire N216;
wire N2160;
wire N2161;
wire N2162;
wire N2163;
wire N2164;
wire N2165;
wire N2166;
wire N2167;
wire N2168;
wire N217;
wire N2172;
wire N218;
wire N2181;
wire N2184;
wire N2187;
wire N219;
wire N2190;
wire N2193;
wire N2196;
wire N2199;
wire N220;
wire N2202;
wire N221;
wire N222;
wire N223;
wire N2239;
wire N2271;
wire N2272;
wire N2273;
wire N2274;
wire N2275;
wire N2276;
wire N2277;
wire N2278;
wire N2279;
wire N228;
wire N2280;
wire N2281;
wire N2282;
wire N2283;
wire N2284;
wire N2285;
wire N2286;
wire N2287;
wire N2288;
wire N2289;
wire N2290;
wire N2291;
wire N2292;
wire N2293;
wire N2294;
wire N2295;
wire N2296;
wire N2298;
wire N2299;
wire N23;
wire N230;
wire N2300;
wire N2301;
wire N2303;
wire N2306;
wire N2308;
wire N231;
wire N2310;
wire N2312;
wire N2314;
wire N2316;
wire N2318;
wire N2320;
wire N2322;
wire N2324;
wire N2326;
wire N2328;
wire N2330;
wire N2332;
wire N2334;
wire N2336;
wire N2338;
wire N234;
wire N2340;
wire N235;
wire N237;
wire N2379;
wire N2380;
wire N24;
wire N2412;
wire N2414;
wire N2415;
wire N2416;
wire N2417;
wire N2418;
wire N2419;
wire N2420;
wire N2421;
wire N2422;
wire N2423;
wire N2424;
wire N2425;
wire N2426;
wire N2427;
wire N2428;
wire N2429;
wire N2430;
wire N2431;
wire N2432;
wire N2433;
wire N2434;
wire N2435;
wire N2436;
wire N2437;
wire N2438;
wire N2439;
wire N2440;
wire N2441;
wire N2442;
wire N2443;
wire N2444;
wire N2445;
wire N2446;
wire N2447;
wire N2448;
wire N2449;
wire N2450;
wire N2451;
wire N2452;
wire N2453;
wire N2454;
wire N2455;
wire N2456;
wire N2457;
wire N2458;
wire N2459;
wire N2460;
wire N2461;
wire N2462;
wire N2463;
wire N2464;
wire N2465;
wire N2467;
wire N2469;
wire N2471;
wire N2473;
wire N2475;
wire N2494;
wire N2496;
wire N2498;
wire N25;
wire N2500;
wire N2502;
wire N2504;
wire N256;
wire N2565;
wire N2566;
wire N2567;
wire N2568;
wire N2569;
wire N2570;
wire N2571;
wire N2572;
wire N2573;
wire N2574;
wire N2575;
wire N2576;
wire N2577;
wire N2578;
wire N2579;
wire N2580;
wire N2581;
wire N2583;
wire N2584;
wire N2585;
wire N2586;
wire N2587;
wire N2588;
wire N2589;
wire N2590;
wire N2591;
wire N2592;
wire N2593;
wire N2594;
wire N2598;
wire N26;
wire N2607;
wire N2610;
wire N2613;
wire N2616;
wire N2619;
wire N2622;
wire N2625;
wire N2628;
wire N265;
wire N2665;
wire N269;
wire N2696;
wire N2697;
wire N2698;
wire N2699;
wire N27;
wire N2700;
wire N2701;
wire N2702;
wire N2703;
wire N2704;
wire N2705;
wire N2706;
wire N2707;
wire N2708;
wire N2709;
wire N2710;
wire N2711;
wire N2712;
wire N2713;
wire N2714;
wire N2715;
wire N2716;
wire N2717;
wire N2718;
wire N2719;
wire N2720;
wire N2721;
wire N2722;
wire N2723;
wire N2724;
wire N2725;
wire N2726;
wire N2729;
wire N2732;
wire N2734;
wire N2736;
wire N2738;
wire N2740;
wire N2742;
wire N2744;
wire N2746;
wire N2748;
wire N2750;
wire N2752;
wire N2754;
wire N2756;
wire N2758;
wire N2760;
wire N2762;
wire N2764;
wire N2766;
wire N28;
wire N2837;
wire N2838;
wire N2839;
wire N2840;
wire N2841;
wire N2842;
wire N2843;
wire N2844;
wire N2845;
wire N2846;
wire N2847;
wire N2848;
wire N2849;
wire N285;
wire N2850;
wire N2851;
wire N2852;
wire N2853;
wire N2854;
wire N2855;
wire N2856;
wire N2857;
wire N2859;
wire N286;
wire N2861;
wire N2862;
wire N2863;
wire N2864;
wire N2865;
wire N2866;
wire N2867;
wire N2868;
wire N2869;
wire N287;
wire N2870;
wire N2871;
wire N2872;
wire N2873;
wire N2874;
wire N2875;
wire N2876;
wire N2877;
wire N2878;
wire N2879;
wire N2880;
wire N2881;
wire N2882;
wire N2883;
wire N2884;
wire N2885;
wire N2887;
wire N2888;
wire N2889;
wire N2890;
wire N2891;
wire N2892;
wire N2894;
wire N2896;
wire N2898;
wire N2900;
wire N2902;
wire N2904;
wire N2923;
wire N2925;
wire N2927;
wire N2929;
wire N2931;
wire N2933;
wire N2993;
wire N2994;
wire N2995;
wire N2996;
wire N2997;
wire N2998;
wire N2999;
wire N3000;
wire N3001;
wire N3002;
wire N3003;
wire N3004;
wire N3005;
wire N3006;
wire N3007;
wire N3008;
wire N3009;
wire N3010;
wire N3011;
wire N3012;
wire N3013;
wire N3014;
wire N3015;
wire N3016;
wire N3017;
wire N3018;
wire N3019;
wire N3020;
wire N3021;
wire N3023;
wire N3033;
wire N3036;
wire N3039;
wire N3042;
wire N3045;
wire N3048;
wire N3051;
wire N3054;
wire N3093;
wire N31;
wire N3124;
wire N3125;
wire N3126;
wire N3127;
wire N3128;
wire N3129;
wire N3130;
wire N3131;
wire N3132;
wire N3133;
wire N3134;
wire N3135;
wire N3136;
wire N3137;
wire N3138;
wire N3139;
wire N3140;
wire N3141;
wire N3142;
wire N3143;
wire N3144;
wire N3145;
wire N3146;
wire N3147;
wire N3148;
wire N3149;
wire N3150;
wire N3151;
wire N3153;
wire N3154;
wire N3156;
wire N3157;
wire N3158;
wire N3160;
wire N3164;
wire N3166;
wire N3168;
wire N317;
wire N3170;
wire N3172;
wire N3174;
wire N3176;
wire N3178;
wire N318;
wire N3180;
wire N3182;
wire N3184;
wire N3186;
wire N3188;
wire N319;
wire N3190;
wire N3192;
wire N3194;
wire N3196;
wire N3198;
wire N32;
wire N320;
wire N3200;
wire N321;
wire N322;
wire N323;
wire N3237;
wire N3238;
wire N324;
wire N325;
wire N326;
wire N327;
wire N3270;
wire N3271;
wire N3272;
wire N3273;
wire N3274;
wire N3275;
wire N3276;
wire N3277;
wire N3278;
wire N3279;
wire N328;
wire N3280;
wire N3281;
wire N3282;
wire N3283;
wire N3284;
wire N3285;
wire N3286;
wire N3287;
wire N3288;
wire N3289;
wire N329;
wire N3291;
wire N3292;
wire N3293;
wire N3294;
wire N3295;
wire N3296;
wire N3297;
wire N3298;
wire N3299;
wire N33;
wire N330;
wire N3300;
wire N3301;
wire N3302;
wire N3303;
wire N3304;
wire N3305;
wire N3306;
wire N3307;
wire N3308;
wire N3309;
wire N331;
wire N3310;
wire N3311;
wire N3312;
wire N3313;
wire N3314;
wire N3315;
wire N3316;
wire N3317;
wire N3318;
wire N3319;
wire N332;
wire N3320;
wire N3321;
wire N3322;
wire N3323;
wire N3325;
wire N3327;
wire N3329;
wire N333;
wire N3331;
wire N3333;
wire N334;
wire N335;
wire N3352;
wire N3354;
wire N3356;
wire N3358;
wire N3360;
wire N3362;
wire N338;
wire N34;
wire N3423;
wire N3424;
wire N3425;
wire N3426;
wire N3427;
wire N3428;
wire N3429;
wire N343;
wire N3430;
wire N3431;
wire N3432;
wire N3433;
wire N3434;
wire N3435;
wire N3436;
wire N3437;
wire N3438;
wire N3439;
wire N3440;
wire N3441;
wire N3442;
wire N3443;
wire N3444;
wire N3445;
wire N3446;
wire N3447;
wire N3448;
wire N3449;
wire N3450;
wire N3451;
wire N3455;
wire N3464;
wire N3467;
wire N347;
wire N3470;
wire N3473;
wire N3476;
wire N3479;
wire N3482;
wire N3485;
wire N35;
wire N350;
wire N3522;
wire N3554;
wire N3555;
wire N3556;
wire N3557;
wire N3558;
wire N3559;
wire N3560;
wire N3561;
wire N3562;
wire N3563;
wire N3564;
wire N3565;
wire N3566;
wire N3567;
wire N3568;
wire N3569;
wire N3570;
wire N3571;
wire N3572;
wire N3573;
wire N3574;
wire N3575;
wire N3576;
wire N3577;
wire N3578;
wire N3579;
wire N3580;
wire N3582;
wire N3583;
wire N3584;
wire N3585;
wire N3587;
wire N3590;
wire N3592;
wire N3594;
wire N3596;
wire N3598;
wire N36;
wire N3600;
wire N3602;
wire N3604;
wire N3606;
wire N3608;
wire N3610;
wire N3612;
wire N3614;
wire N3616;
wire N3618;
wire N3620;
wire N3622;
wire N3624;
wire N3626;
wire N364;
wire N3664;
wire N3665;
wire N3697;
wire N3698;
wire N3699;
wire N37;
wire N3700;
wire N3701;
wire N3702;
wire N3703;
wire N3704;
wire N3705;
wire N3706;
wire N3707;
wire N3708;
wire N3709;
wire N3710;
wire N3711;
wire N3712;
wire N3713;
wire N3714;
wire N3715;
wire N3716;
wire N3718;
wire N3719;
wire N372;
wire N3720;
wire N3721;
wire N3722;
wire N3723;
wire N3724;
wire N3725;
wire N3726;
wire N3727;
wire N3728;
wire N3729;
wire N3730;
wire N3731;
wire N3732;
wire N3733;
wire N3734;
wire N3735;
wire N3736;
wire N3737;
wire N3738;
wire N3739;
wire N3740;
wire N3741;
wire N3742;
wire N3743;
wire N3744;
wire N3745;
wire N3746;
wire N3747;
wire N3748;
wire N3749;
wire N3750;
wire N3752;
wire N3754;
wire N3756;
wire N3758;
wire N3760;
wire N3779;
wire N3781;
wire N3783;
wire N3785;
wire N3787;
wire N3789;
wire N38;
wire N384;
wire N3851;
wire N3852;
wire N3853;
wire N3854;
wire N3855;
wire N3856;
wire N3857;
wire N3858;
wire N3859;
wire N3860;
wire N3861;
wire N3862;
wire N3863;
wire N3864;
wire N3865;
wire N3866;
wire N3867;
wire N3868;
wire N3869;
wire N3870;
wire N3871;
wire N3872;
wire N3873;
wire N3874;
wire N3875;
wire N3876;
wire N3877;
wire N3878;
wire N3879;
wire N3883;
wire N3892;
wire N3895;
wire N3898;
wire N39;
wire N390;
wire N3901;
wire N3904;
wire N3907;
wire N3910;
wire N3913;
wire N3950;
wire N397;
wire N398;
wire N3982;
wire N3983;
wire N3984;
wire N3985;
wire N3986;
wire N3987;
wire N3988;
wire N3989;
wire N399;
wire N3990;
wire N3991;
wire N3992;
wire N3993;
wire N3994;
wire N3995;
wire N3996;
wire N3997;
wire N3998;
wire N3999;
wire N40;
wire N4000;
wire N4001;
wire N4002;
wire N4003;
wire N4004;
wire N4005;
wire N4006;
wire N4007;
wire N4009;
wire N4010;
wire N4011;
wire N4012;
wire N4014;
wire N4017;
wire N4019;
wire N4021;
wire N4023;
wire N4025;
wire N4027;
wire N4029;
wire N4031;
wire N4033;
wire N4035;
wire N4037;
wire N4039;
wire N4041;
wire N4043;
wire N4045;
wire N4047;
wire N4049;
wire N4051;
wire N4090;
wire N4091;
wire N4123;
wire N4124;
wire N4125;
wire N4126;
wire N4127;
wire N4128;
wire N4129;
wire N4130;
wire N4131;
wire N4132;
wire N4133;
wire N4134;
wire N4135;
wire N4136;
wire N4137;
wire N4138;
wire N4139;
wire N4140;
wire N4141;
wire N4142;
wire N4144;
wire N4145;
wire N4146;
wire N4147;
wire N4148;
wire N4149;
wire N4150;
wire N4151;
wire N4152;
wire N4153;
wire N4154;
wire N4155;
wire N4156;
wire N4157;
wire N4158;
wire N4159;
wire N4160;
wire N4161;
wire N4162;
wire N4163;
wire N4164;
wire N4165;
wire N4166;
wire N4167;
wire N4168;
wire N4169;
wire N4170;
wire N4171;
wire N4172;
wire N4173;
wire N4174;
wire N4175;
wire N4176;
wire N4178;
wire N4180;
wire N4182;
wire N4184;
wire N4186;
wire N4205;
wire N4207;
wire N4209;
wire N4211;
wire N4213;
wire N4215;
wire N4276;
wire N4277;
wire N4278;
wire N4279;
wire N4280;
wire N4281;
wire N4282;
wire N4283;
wire N4284;
wire N4285;
wire N4286;
wire N4287;
wire N4288;
wire N4289;
wire N4290;
wire N4291;
wire N4292;
wire N4293;
wire N4294;
wire N4295;
wire N4296;
wire N4297;
wire N4298;
wire N4299;
wire N430;
wire N4300;
wire N4301;
wire N4302;
wire N4303;
wire N4304;
wire N4307;
wire N431;
wire N4316;
wire N4319;
wire N432;
wire N4322;
wire N4325;
wire N4328;
wire N433;
wire N4331;
wire N4334;
wire N4337;
wire N434;
wire N435;
wire N436;
wire N437;
wire N4375;
wire N438;
wire N439;
wire N440;
wire N4406;
wire N4407;
wire N4408;
wire N4409;
wire N441;
wire N4410;
wire N4411;
wire N4412;
wire N4413;
wire N442;
wire N443;
wire N444;
wire N445;
wire N446;
wire N447;
wire N448;
wire N449;
wire N450;
wire N451;
wire N452;
wire N453;
wire N454;
wire N455;
wire N456;
wire N457;
wire N459;
wire N462;
wire N464;
wire N466;
wire N468;
wire N470;
wire N472;
wire N473;
wire N475;
wire N476;
wire N478;
wire N479;
wire N481;
wire N483;
wire N486;
wire N488;
wire N490;
wire N492;
wire N493;
wire N496;
wire N498;
wire N50;
wire N507;
wire N510;
wire N514;
wire N518;
wire N522;
wire N526;
wire N530;
wire N533;
wire N541;
wire N542;
wire N543;
wire N544;
wire N545;
wire N546;
wire N547;
wire N578;
wire N579;
wire N580;
wire N581;
wire N582;
wire N583;
wire N584;
wire N585;
wire N586;
wire N587;
wire N588;
wire N589;
wire N590;
wire N591;
wire N592;
wire N594;
wire N595;
wire N596;
wire N597;
wire N598;
wire N599;
wire N600;
wire N601;
wire N602;
wire N603;
wire N604;
wire N628;
wire N632;
wire N638;
wire N641;
wire N644;
wire N647;
wire N650;
wire N653;
wire N656;
wire N659;
wire N662;
wire N664;
wire N666;
wire N701;
wire N702;
wire N703;
wire N704;
wire N705;
wire N706;
wire N707;
wire N708;
wire N709;
wire N710;
wire N711;
wire N712;
wire N713;
wire N714;
wire N715;
wire N716;
wire N717;
wire N718;
wire N719;
wire N720;
wire N721;
wire N722;
wire N723;
wire N724;
wire N725;
wire N737;
wire N772;
wire N792;
wire N799;
wire N800;
wire N801;
wire N802;
wire N803;
wire N804;
wire N805;
wire N806;
wire N807;
wire N808;
wire N809;
wire N818;
wire N819;
wire N822;
wire N823;
wire N824;
wire N825;
wire N826;
wire N827;
wire N828;
wire N829;
wire N830;
wire N831;
wire N832;
wire N833;
wire N834;
wire N835;
wire N837;
wire N839;
wire N84;
wire N876;
wire N899;
wire N900;
wire N901;
wire N902;
wire N903;
wire N904;
wire N905;
wire N906;
wire N907;
wire N908;
wire N909;
wire N910;
wire N911;
wire N912;
wire N913;
wire N914;
wire N915;
wire N916;
wire N917;
wire N918;
wire N919;
wire N920;
wire N921;
wire N922;
wire N923;
wire N924;
wire N926;
wire N932;
wire N934;
wire N936;
wire N938;
wire N940;
wire N942;
wire N944;
wire N946;
wire N948;
wire N950;
wire N952;
wire N954;
wire N956;
wire N958;
wire N960;
wire N962;
wire N967;
wire N974;
wire PDOEA;
wire PDOEB;
wire _HD0IN;
wire _HD1IN;
wire _HD2IN;
wire _HD3IN;
wire _HD4IN;
wire _HD5IN;
wire _HD6IN;
wire _HD7IN;
nor #5 GDRQ(DRQ,N321);
nor #5 GHD0OUT(HD0OUT,N4007,N4012,N4142,N4175,N4215);
nor #5 GHD1OUT(HD1OUT,N3580,N3585,N3716,N3749,N3789);
nor #5 GHD2OUT(HD2OUT,N3151,N3158,N3289,N3322,N3362);
nor #5 GHD3OUT(HD3OUT,N2725,N2726,N2856,N2857,N2933);
nor #5 GHD4OUT(HD4OUT,N2296,N2301,N2432,N2464,N2504);
nor #5 GHD5OUT(HD5OUT,N1873,N1877,N2007,N2039,N2079);
nor #5 GHD6OUT(HD6OUT,N1335,N1336,N1436,N1437,N1458,N1588,N1620,N1687);
nor #5 GHD7OUT(HD7OUT,N1035,N1083,N1125,N1155,N1187,N899,N921,N967);
nor #5 GHDOEA(HDOEA,HCS,N116,N50);
nor #5 GHIRQ(HIRQ,N1432);
nor #5 GN1002(N1002,N1060,N1093);
nor #5 GN1003(N1003,N903);
nor #5 GN1004(N1004,N1080,N1117);
nor #5 GN1035(N1035,N1004,N441);
nor #5 GN1036(N1036,N1057,N459);
nor #5 GN1037(N1037,N701,N934);
nor #5 GN1038(N1038,N702,N938);
nor #5 GN1039(N1039,N703,N942);
nor #5 GN1040(N1040,N704,N946);
nor #5 GN1041(N1041,N705,N950);
nor #5 GN1042(N1042,N706,N954);
nor #5 GN1043(N1043,N707,N958);
nor #5 GN1044(N1044,N1201,N792);
nor #5 GN1046(N1046,N601,N904);
nor #5 GN1047(N1047,N510,N906);
nor #5 GN1048(N1048,N579,N908);
nor #5 GN1049(N1049,N581,N910);
nor #5 GN1050(N1050,N583,N912);
nor #5 GN1051(N1051,N585,N914);
nor #5 GN1052(N1052,N587,N916);
nor #5 GN1053(N1053,N589,N918);
nor #5 GN1056(N1056,N34,N709);
nor #5 GN1057(N1057,N1059,N1091);
nor #5 GN1058(N1058,N1084,N1189);
nor #5 GN1059(N1059,N1057,N1190);
nor #5 GN1060(N1060,N1002,N1191);
nor #5 GN1061(N1061,N1192,N923);
nor #5 GN1062(N1062,N1085,N1193);
nor #5 GN1063(N1063,N1064,N904);
nor #5 GN1064(N1064,N1046,N1063);
nor #5 GN1065(N1065,N1066,N906);
nor #5 GN1066(N1066,N1047,N1065);
nor #5 GN1067(N1067,N1068,N908);
nor #5 GN1068(N1068,N1048,N1067);
nor #5 GN1069(N1069,N1070,N910);
nor #5 GN1070(N1070,N1049,N1069);
nor #5 GN1071(N1071,N1072,N912);
nor #5 GN1072(N1072,N1050,N1071);
nor #5 GN1073(N1073,N1074,N914);
nor #5 GN1074(N1074,N1051,N1073);
nor #5 GN1075(N1075,N1076,N916);
nor #5 GN1076(N1076,N1052,N1075);
nor #5 GN1077(N1077,N1078,N918);
nor #5 GN1078(N1078,N1053,N1077);
nor #5 GN1079(N1079,N1086,N1202);
nor #5 GN1080(N1080,N1004,N1203);
nor #5 GN1081(N1081,N1204,N920);
nor #5 GN1082(N1082,N1121,N1123);
nor #5 GN1083(N1083,N37,N664);
nor #5 GN1084(N1084,N1058,N1089);
nor #5 GN1085(N1085,N1062,N1097);
nor #5 GN1086(N1086,N1079,N1115);
nor #5 GN1087(N1087,N120,N628);
nor #5 GN1089(N1089,N710,N824);
nor #5 GN1091(N1091,N1190,N808);
nor #5 GN1093(N1093,N1191,N809);
nor #5 GN1095(N1095,N1192,N632);
nor #5 GN1097(N1097,N1193,N338);
nor #5 GN1115(N1115,N1202,N835);
nor #5 GN1117(N1117,N1203,N662);
nor #5 GN1119(N1119,N1204,N818);
nor #5 GN1121(N1121,N1082,N1205);
nor #5 GN1123(N1123,N1205,N819);
nor #5 GN1125(N1125,N498,N919);
nor #5 GN1126(N1126,N1058,N442);
nor #5 GN115(N115,N124,N35);
nor #5 GN1155(N1155,N343,N84);
nor #5 GN116(N116,HO2);
nor #5 GN117(N117,N122);
nor #5 GN118(N118,N24);
nor #5 GN1187(N1187,N1082,N334);
nor #5 GN1188(N1188,N118,N1208);
nor #5 GN1189(N1189,N1089,N824);
nor #5 GN119(N119,N36);
nor #5 GN1190(N1190,N710,N808);
nor #5 GN1191(N1191,N710,N809);
nor #5 GN1192(N1192,N1062,N632);
nor #5 GN1193(N1193,N338,N710);
nor #5 GN1194(N1194,N1209,N1226);
nor #5 GN1195(N1195,N1210,N1229);
nor #5 GN1196(N1196,N1211,N1232);
nor #5 GN1197(N1197,N1212,N1235);
nor #5 GN1198(N1198,N1213,N1238);
nor #5 GN1199(N1199,N1214,N1241);
nor #5 GN120(N120,N123);
nor #5 GN1200(N1200,N1215,N1244);
nor #5 GN1201(N1201,N1216,N1247);
nor #5 GN1202(N1202,N823,N835);
nor #5 GN1203(N1203,N1079,N662);
nor #5 GN1204(N1204,N818,N823);
nor #5 GN1205(N1205,N819,N823);
nor #5 GN1206(N1206,N332,N595);
nor #5 GN1208(N1208,N321);
nor #5 GN1209(N1209,N1063,N800);
nor #5 GN121(N121,HCS,N116,N50);
nor #5 GN1210(N1210,N1065,N801);
nor #5 GN1211(N1211,N1067,N802);
nor #5 GN1212(N1212,N1069,N803);
nor #5 GN1213(N1213,N1071,N804);
nor #5 GN1214(N1214,N1073,N805);
nor #5 GN1215(N1215,N1075,N806);
nor #5 GN1216(N1216,N1077,N807);
nor #5 GN122(N122,HA0,HA2,N39);
nor #5 GN1226(N1226,N1194,N1313);
nor #5 GN1229(N1229,N1195,N1315);
nor #5 GN123(N123,N23,N32,PA0,PA2);
nor #5 GN1232(N1232,N1196,N1316);
nor #5 GN1235(N1235,N1197,N1317);
nor #5 GN1238(N1238,N1198,N1318);
nor #5 GN124(N124,PCS,PNWDS);
nor #5 GN1241(N1241,N1199,N1319);
nor #5 GN1244(N1244,N1200,N1320);
nor #5 GN1247(N1247,N1201,N1321);
nor #5 GN125(N125,N126,N176);
nor #5 GN126(N126,PCS,PNRDS);
nor #5 GN127(N127,N121);
nor #5 GN1313(N1313,N1209,N800);
nor #5 GN1314(N1314,N664);
nor #5 GN1315(N1315,N1210,N801);
nor #5 GN1316(N1316,N1211,N802);
nor #5 GN1317(N1317,N1212,N803);
nor #5 GN1318(N1318,N1213,N804);
nor #5 GN1319(N1319,N1214,N805);
nor #5 GN1320(N1320,N1215,N806);
nor #5 GN1321(N1321,N1216,N807);
nor #5 GN1326(N1326,N1346);
nor #5 GN1327(N1327,N708);
nor #5 GN1328(N1328,N1314,N34);
nor #5 GN1329(N1329,N118,N1339);
nor #5 GN1332(N1332,N1343,N321);
nor #5 GN1335(N1335,N318,N84);
nor #5 GN1336(N1336,N1327,N335);
nor #5 GN1339(N1339,N343);
nor #5 GN1343(N1343,N1434);
nor #5 GN1346(N1346,N4011,N4017,N4123);
nor #5 GN1349(N1349,N1617,N1719);
nor #5 GN1396(N1396,N1496,N1498);
nor #5 GN1398(N1398,N120,N1430);
nor #5 GN1399(N1399,N628);
nor #5 GN140(N140,N23,PA0,PA1,PA2);
nor #5 GN141(N141,HA0,HA1,HA2);
nor #5 GN1430(N1430,N666);
nor #5 GN1431(N1431,N1736,N1750);
nor #5 GN1432(N1432,N1314,N1326);
nor #5 GN1433(N1433,N1876,N1882,N1988);
nor #5 GN1434(N1434,N2724,N2732,N2837);
nor #5 GN1435(N1435,N1349,N442);
nor #5 GN1436(N1436,N117,N1399);
nor #5 GN1437(N1437,N1396,N498);
nor #5 GN1438(N1438,N1431,N601);
nor #5 GN1439(N1439,N1468,N1470);
nor #5 GN1440(N1440,N1439,N510);
nor #5 GN1441(N1441,N1472,N1474);
nor #5 GN1442(N1442,N1441,N579);
nor #5 GN1443(N1443,N1476,N1478);
nor #5 GN1444(N1444,N1443,N581);
nor #5 GN1445(N1445,N1480,N1482);
nor #5 GN1446(N1446,N1445,N583);
nor #5 GN1447(N1447,N1484,N1486);
nor #5 GN1448(N1448,N1447,N585);
nor #5 GN1449(N1449,N1488,N1490);
nor #5 GN1450(N1450,N1449,N587);
nor #5 GN1451(N1451,N1492,N1494);
nor #5 GN1452(N1452,N1451,N589);
nor #5 GN1453(N1453,N709);
nor #5 GN1455(N1455,N325,N454);
nor #5 GN1456(N1456,N1592,N1628);
nor #5 GN1457(N1457,N1466,N435);
nor #5 GN1458(N1458,N1453,N37);
nor #5 GN1464(N1464,N1571,N924);
nor #5 GN1466(N1466,N1206,N1570,N1571);
nor #5 GN1468(N1468,N1439,N1572);
nor #5 GN1470(N1470,N1724,N701);
nor #5 GN1472(N1472,N1441,N1573);
nor #5 GN1474(N1474,N1725,N702);
nor #5 GN1476(N1476,N1443,N1574);
nor #5 GN1478(N1478,N1726,N703);
nor #5 GN1480(N1480,N1445,N1575);
nor #5 GN1482(N1482,N1727,N704);
nor #5 GN1484(N1484,N1447,N1576);
nor #5 GN1486(N1486,N1728,N705);
nor #5 GN1488(N1488,N1449,N1577);
nor #5 GN1490(N1490,N1729,N706);
nor #5 GN1492(N1492,N1451,N1578);
nor #5 GN1494(N1494,N1730,N707);
nor #5 GN1496(N1496,N1396,N1579);
nor #5 GN1498(N1498,N1579,N792);
nor #5 GN1536(N1536,N1456,N326);
nor #5 GN1537(N1537,N1591,N1626);
nor #5 GN1538(N1538,N1611,N1651);
nor #5 GN1570(N1570,N1206,N924);
nor #5 GN1571(N1571,N1745,N1746);
nor #5 GN1572(N1572,N1470,N701);
nor #5 GN1573(N1573,N1474,N702);
nor #5 GN1574(N1574,N1478,N703);
nor #5 GN1575(N1575,N1482,N704);
nor #5 GN1576(N1576,N1486,N705);
nor #5 GN1577(N1577,N1490,N706);
nor #5 GN1578(N1578,N1494,N707);
nor #5 GN1579(N1579,N1731,N792);
nor #5 GN1580(N1580,N1438,N601);
nor #5 GN1581(N1581,N1440,N510);
nor #5 GN1582(N1582,N1442,N579);
nor #5 GN1583(N1583,N1444,N581);
nor #5 GN1584(N1584,N1446,N583);
nor #5 GN1585(N1585,N1448,N585);
nor #5 GN1586(N1586,N1450,N587);
nor #5 GN1587(N1587,N1452,N589);
nor #5 GN1588(N1588,N1538,N441);
nor #5 GN1589(N1589,N1590,N1624);
nor #5 GN1590(N1590,N1589,N1720);
nor #5 GN1591(N1591,N1537,N1721);
nor #5 GN1592(N1592,N1456,N1722);
nor #5 GN1593(N1593,N1618,N1723);
nor #5 GN1594(N1594,N1438,N1595);
nor #5 GN1595(N1595,N1580,N1594);
nor #5 GN1596(N1596,N1440,N1597);
nor #5 GN1597(N1597,N1581,N1596);
nor #5 GN1598(N1598,N1442,N1599);
nor #5 GN1599(N1599,N1582,N1598);
nor #5 GN1600(N1600,N1444,N1601);
nor #5 GN1601(N1601,N1583,N1600);
nor #5 GN1602(N1602,N1446,N1603);
nor #5 GN1603(N1603,N1584,N1602);
nor #5 GN1604(N1604,N1448,N1605);
nor #5 GN1605(N1605,N1585,N1604);
nor #5 GN1606(N1606,N1450,N1607);
nor #5 GN1607(N1607,N1586,N1606);
nor #5 GN1608(N1608,N1452,N1609);
nor #5 GN1609(N1609,N1587,N1608);
nor #5 GN1610(N1610,N1619,N1732);
nor #5 GN1611(N1611,N1538,N1733);
nor #5 GN1612(N1612,N1613,N1653);
nor #5 GN1613(N1613,N1612,N1734);
nor #5 GN1614(N1614,N1655,N1657);
nor #5 GN1616(N1616,N1537,N327);
nor #5 GN1617(N1617,N1349,N1622);
nor #5 GN1618(N1618,N1593,N1630);
nor #5 GN1619(N1619,N1610,N1649);
nor #5 GN1620(N1620,N1612,N496);
nor #5 GN1622(N1622,N1571,N824);
nor #5 GN1624(N1624,N1720,N808);
nor #5 GN1626(N1626,N1721,N809);
nor #5 GN1628(N1628,N1722,N632);
nor #5 GN1630(N1630,N1723,N338);
nor #5 GN1649(N1649,N1732,N835);
nor #5 GN1651(N1651,N1733,N662);
nor #5 GN1653(N1653,N1734,N818);
nor #5 GN1655(N1655,N1614,N1735);
nor #5 GN1657(N1657,N1735,N819);
nor #5 GN1687(N1687,N1614,N334);
nor #5 GN1688(N1688,N1589,N459);
nor #5 GN1719(N1719,N1622,N824);
nor #5 GN1720(N1720,N1571,N808);
nor #5 GN1721(N1721,N1571,N809);
nor #5 GN1722(N1722,N1593,N632);
nor #5 GN1723(N1723,N1571,N338);
nor #5 GN1724(N1724,N1737,N1759);
nor #5 GN1725(N1725,N1738,N1762);
nor #5 GN1726(N1726,N1739,N1765);
nor #5 GN1727(N1727,N1740,N1768);
nor #5 GN1728(N1728,N1741,N1771);
nor #5 GN1729(N1729,N1742,N1774);
nor #5 GN1730(N1730,N1743,N1777);
nor #5 GN1731(N1731,N1744,N1780);
nor #5 GN1732(N1732,N1431,N835);
nor #5 GN1733(N1733,N1610,N662);
nor #5 GN1734(N1734,N1431,N818);
nor #5 GN1735(N1735,N1431,N819);
nor #5 GN1736(N1736,N115,N1748);
nor #5 GN1737(N1737,N1594,N800);
nor #5 GN1738(N1738,N1596,N801);
nor #5 GN1739(N1739,N1598,N802);
nor #5 GN1740(N1740,N1600,N803);
nor #5 GN1741(N1741,N1602,N804);
nor #5 GN1742(N1742,N1604,N805);
nor #5 GN1743(N1743,N1606,N806);
nor #5 GN1744(N1744,N1608,N807);
nor #5 GN1745(N1745,N1571,N1817);
nor #5 GN1746(N1746,N26,_HD6IN);
nor #5 GN1748(N1748,N115,PD6IN);
nor #5 GN175(N175,N124,N35);
nor #5 GN1750(N1750,N1431,N1748);
nor #5 GN1759(N1759,N1724,N1849);
nor #5 GN176(N176,DACK,PNWDS);
nor #5 GN1762(N1762,N1725,N1850);
nor #5 GN1765(N1765,N1726,N1851);
nor #5 GN1768(N1768,N1727,N1852);
nor #5 GN177(N177,N175,N459);
nor #5 GN1771(N1771,N1728,N1853);
nor #5 GN1774(N1774,N1729,N1854);
nor #5 GN1777(N1777,N1730,N1855);
nor #5 GN1780(N1780,N1731,N1856);
nor #5 GN1817(N1817,N1746,N26);
nor #5 GN1848(N1848,N2158,N2172);
nor #5 GN1849(N1849,N1737,N800);
nor #5 GN1850(N1850,N1738,N801);
nor #5 GN1851(N1851,N1739,N802);
nor #5 GN1852(N1852,N1740,N803);
nor #5 GN1853(N1853,N1741,N804);
nor #5 GN1854(N1854,N1742,N805);
nor #5 GN1855(N1855,N1743,N806);
nor #5 GN1856(N1856,N1744,N807);
nor #5 GN1857(N1857,N1848,N601);
nor #5 GN1858(N1858,N1886,N1888);
nor #5 GN1859(N1859,N1858,N510);
nor #5 GN1860(N1860,N1890,N1892);
nor #5 GN1861(N1861,N1860,N579);
nor #5 GN1862(N1862,N1894,N1896);
nor #5 GN1863(N1863,N1862,N581);
nor #5 GN1864(N1864,N1898,N1900);
nor #5 GN1865(N1865,N1864,N583);
nor #5 GN1866(N1866,N1902,N1904);
nor #5 GN1867(N1867,N1866,N585);
nor #5 GN1868(N1868,N1906,N1908);
nor #5 GN1869(N1869,N1868,N587);
nor #5 GN1870(N1870,N1910,N1912);
nor #5 GN1871(N1871,N1870,N589);
nor #5 GN1872(N1872,N1914,N1916);
nor #5 GN1873(N1873,N1433,N335);
nor #5 GN1874(N1874,N1433,N325);
nor #5 GN1875(N1875,N2013,N2048);
nor #5 GN1876(N1876,N1433,N1884);
nor #5 GN1877(N1877,N1872,N498);
nor #5 GN1879(N1879,N1875,N326);
nor #5 GN1882(N1882,N1990,N924);
nor #5 GN1884(N1884,N1206,N1988,N1990);
nor #5 GN1886(N1886,N1858,N1991);
nor #5 GN1888(N1888,N2145,N701);
nor #5 GN1890(N1890,N1860,N1992);
nor #5 GN1892(N1892,N2146,N702);
nor #5 GN1894(N1894,N1862,N1993);
nor #5 GN1896(N1896,N2147,N703);
nor #5 GN1898(N1898,N1864,N1994);
nor #5 GN1900(N1900,N2148,N704);
nor #5 GN1902(N1902,N1866,N1995);
nor #5 GN1904(N1904,N2149,N705);
nor #5 GN1906(N1906,N1868,N1996);
nor #5 GN1908(N1908,N2150,N706);
nor #5 GN1910(N1910,N1870,N1997);
nor #5 GN1912(N1912,N2151,N707);
nor #5 GN1914(N1914,N1872,N1998);
nor #5 GN1916(N1916,N1998,N792);
nor #5 GN1955(N1955,N2012,N2046);
nor #5 GN1956(N1956,N2032,N2071);
nor #5 GN1988(N1988,N1206,N924);
nor #5 GN1989(N1989,N1955,N327);
nor #5 GN1990(N1990,N2167,N2168);
nor #5 GN1991(N1991,N1888,N701);
nor #5 GN1992(N1992,N1892,N702);
nor #5 GN1993(N1993,N1896,N703);
nor #5 GN1994(N1994,N1900,N704);
nor #5 GN1995(N1995,N1904,N705);
nor #5 GN1996(N1996,N1908,N706);
nor #5 GN1997(N1997,N1912,N707);
nor #5 GN1998(N1998,N2152,N792);
nor #5 GN1999(N1999,N1857,N601);
nor #5 GN2000(N2000,N1859,N510);
nor #5 GN2001(N2001,N1861,N579);
nor #5 GN2002(N2002,N1863,N581);
nor #5 GN2003(N2003,N1865,N583);
nor #5 GN2004(N2004,N1867,N585);
nor #5 GN2005(N2005,N1869,N587);
nor #5 GN2006(N2006,N1871,N589);
nor #5 GN2007(N2007,N1956,N441);
nor #5 GN2008(N2008,N2010,N442);
nor #5 GN2009(N2009,N2011,N2044);
nor #5 GN2010(N2010,N2036,N2140);
nor #5 GN2011(N2011,N2009,N2141);
nor #5 GN2012(N2012,N1955,N2142);
nor #5 GN2013(N2013,N1875,N2143);
nor #5 GN2014(N2014,N2037,N2144);
nor #5 GN2015(N2015,N1857,N2016);
nor #5 GN2016(N2016,N1999,N2015);
nor #5 GN2017(N2017,N1859,N2018);
nor #5 GN2018(N2018,N2000,N2017);
nor #5 GN2019(N2019,N1861,N2020);
nor #5 GN2020(N2020,N2001,N2019);
nor #5 GN2021(N2021,N1863,N2022);
nor #5 GN2022(N2022,N2002,N2021);
nor #5 GN2023(N2023,N1865,N2024);
nor #5 GN2024(N2024,N2003,N2023);
nor #5 GN2025(N2025,N1867,N2026);
nor #5 GN2026(N2026,N2004,N2025);
nor #5 GN2027(N2027,N1869,N2028);
nor #5 GN2028(N2028,N2005,N2027);
nor #5 GN2029(N2029,N1871,N2030);
nor #5 GN2030(N2030,N2006,N2029);
nor #5 GN2031(N2031,N2038,N2153);
nor #5 GN2032(N2032,N1956,N2154);
nor #5 GN2033(N2033,N2034,N2073);
nor #5 GN2034(N2034,N2033,N2155);
nor #5 GN2035(N2035,N2075,N2077);
nor #5 GN2036(N2036,N2010,N2042);
nor #5 GN2037(N2037,N2014,N2050);
nor #5 GN2038(N2038,N2031,N2069);
nor #5 GN2039(N2039,N2033,N496);
nor #5 GN2040(N2040,N2009,N459);
nor #5 GN2042(N2042,N1990,N824);
nor #5 GN2044(N2044,N2141,N808);
nor #5 GN2046(N2046,N2142,N809);
nor #5 GN2048(N2048,N2143,N632);
nor #5 GN2050(N2050,N2144,N338);
nor #5 GN2069(N2069,N2153,N835);
nor #5 GN207(N207,N119,N498);
nor #5 GN2071(N2071,N2154,N662);
nor #5 GN2073(N2073,N2155,N818);
nor #5 GN2075(N2075,N2035,N2156);
nor #5 GN2077(N2077,N2156,N819);
nor #5 GN2079(N2079,N2035,N334);
nor #5 GN208(N208,N119,N496);
nor #5 GN209(N209,N175,N327);
nor #5 GN210(N210,N235,N237);
nor #5 GN211(N211,N23,N31,PA1,PA2);
nor #5 GN212(N212,N23,N31,N32,PA2);
nor #5 GN213(N213,N31,N33,PA1);
nor #5 GN214(N214,N23,N31,N32,N33);
nor #5 GN2140(N2140,N2042,N824);
nor #5 GN2141(N2141,N1990,N808);
nor #5 GN2142(N2142,N1990,N809);
nor #5 GN2143(N2143,N2014,N632);
nor #5 GN2144(N2144,N1990,N338);
nor #5 GN2145(N2145,N2159,N2181);
nor #5 GN2146(N2146,N2160,N2184);
nor #5 GN2147(N2147,N2161,N2187);
nor #5 GN2148(N2148,N2162,N2190);
nor #5 GN2149(N2149,N2163,N2193);
nor #5 GN215(N215,N175,N326);
nor #5 GN2150(N2150,N2164,N2196);
nor #5 GN2151(N2151,N2165,N2199);
nor #5 GN2152(N2152,N2166,N2202);
nor #5 GN2153(N2153,N1848,N835);
nor #5 GN2154(N2154,N2031,N662);
nor #5 GN2155(N2155,N1848,N818);
nor #5 GN2156(N2156,N1848,N819);
nor #5 GN2157(N2157,N115,PD5IN);
nor #5 GN2158(N2158,N115,N2157);
nor #5 GN2159(N2159,N2015,N800);
nor #5 GN216(N216,N228,N230);
nor #5 GN2160(N2160,N2017,N801);
nor #5 GN2161(N2161,N2019,N802);
nor #5 GN2162(N2162,N2021,N803);
nor #5 GN2163(N2163,N2023,N804);
nor #5 GN2164(N2164,N2025,N805);
nor #5 GN2165(N2165,N2027,N806);
nor #5 GN2166(N2166,N2029,N807);
nor #5 GN2167(N2167,N1990,N2239);
nor #5 GN2168(N2168,N26,_HD5IN);
nor #5 GN217(N217,N216,N231);
nor #5 GN2172(N2172,N1848,N2157);
nor #5 GN218(N218,N210,N234);
nor #5 GN2181(N2181,N2145,N2272);
nor #5 GN2184(N2184,N2146,N2273);
nor #5 GN2187(N2187,N2147,N2274);
nor #5 GN219(N219,N119,N335);
nor #5 GN2190(N2190,N2148,N2275);
nor #5 GN2193(N2193,N2149,N2276);
nor #5 GN2196(N2196,N2150,N2277);
nor #5 GN2199(N2199,N2151,N2278);
nor #5 GN220(N220,HA2,N39,N40);
nor #5 GN2202(N2202,N2152,N2279);
nor #5 GN221(N221,HA1,N38,N40);
nor #5 GN222(N222,N38,N39,N40);
nor #5 GN223(N223,HA1,HA2,N40);
nor #5 GN2239(N2239,N2168,N26);
nor #5 GN2271(N2271,N2584,N2598);
nor #5 GN2272(N2272,N2159,N800);
nor #5 GN2273(N2273,N2160,N801);
nor #5 GN2274(N2274,N2161,N802);
nor #5 GN2275(N2275,N2162,N803);
nor #5 GN2276(N2276,N2163,N804);
nor #5 GN2277(N2277,N2164,N805);
nor #5 GN2278(N2278,N2165,N806);
nor #5 GN2279(N2279,N2166,N807);
nor #5 GN228(N228,N323,N329,N330);
nor #5 GN2280(N2280,N2271,N601);
nor #5 GN2281(N2281,N2310,N2312);
nor #5 GN2282(N2282,N2281,N510);
nor #5 GN2283(N2283,N2314,N2316);
nor #5 GN2284(N2284,N2283,N579);
nor #5 GN2285(N2285,N2318,N2320);
nor #5 GN2286(N2286,N2285,N581);
nor #5 GN2287(N2287,N2322,N2324);
nor #5 GN2288(N2288,N2287,N583);
nor #5 GN2289(N2289,N2326,N2328);
nor #5 GN2290(N2290,N2289,N585);
nor #5 GN2291(N2291,N2330,N2332);
nor #5 GN2292(N2292,N2291,N587);
nor #5 GN2293(N2293,N2334,N2336);
nor #5 GN2294(N2294,N2293,N589);
nor #5 GN2295(N2295,N2338,N2340);
nor #5 GN2296(N2296,N269,N335);
nor #5 GN2298(N2298,N269,N325);
nor #5 GN2299(N2299,N2438,N2473);
nor #5 GN23(N23,DACK);
nor #5 GN230(N230,N269);
nor #5 GN2300(N2300,N2308,N269);
nor #5 GN2301(N2301,N2295,N498);
nor #5 GN2303(N2303,N2299,N326);
nor #5 GN2306(N2306,N2415,N924);
nor #5 GN2308(N2308,N1206,N2412,N2415);
nor #5 GN231(N231,N256,N269);
nor #5 GN2310(N2310,N2281,N2416);
nor #5 GN2312(N2312,N2570,N701);
nor #5 GN2314(N2314,N2283,N2417);
nor #5 GN2316(N2316,N2571,N702);
nor #5 GN2318(N2318,N2285,N2418);
nor #5 GN2320(N2320,N2572,N703);
nor #5 GN2322(N2322,N2287,N2419);
nor #5 GN2324(N2324,N2573,N704);
nor #5 GN2326(N2326,N2289,N2420);
nor #5 GN2328(N2328,N2574,N705);
nor #5 GN2330(N2330,N2291,N2421);
nor #5 GN2332(N2332,N2575,N706);
nor #5 GN2334(N2334,N2293,N2422);
nor #5 GN2336(N2336,N2576,N707);
nor #5 GN2338(N2338,N2295,N2423);
nor #5 GN234(N234,N269,N320);
nor #5 GN2340(N2340,N2423,N792);
nor #5 GN235(N235,N269);
nor #5 GN237(N237,N333,N347,N436);
nor #5 GN2379(N2379,N2437,N2471);
nor #5 GN2380(N2380,N2457,N2496);
nor #5 GN24(N24,N23,N33,PA0,PA1);
nor #5 GN2412(N2412,N1206,N924);
nor #5 GN2414(N2414,N2379,N327);
nor #5 GN2415(N2415,N2593,N2594);
nor #5 GN2416(N2416,N2312,N701);
nor #5 GN2417(N2417,N2316,N702);
nor #5 GN2418(N2418,N2320,N703);
nor #5 GN2419(N2419,N2324,N704);
nor #5 GN2420(N2420,N2328,N705);
nor #5 GN2421(N2421,N2332,N706);
nor #5 GN2422(N2422,N2336,N707);
nor #5 GN2423(N2423,N2577,N792);
nor #5 GN2424(N2424,N2280,N601);
nor #5 GN2425(N2425,N2282,N510);
nor #5 GN2426(N2426,N2284,N579);
nor #5 GN2427(N2427,N2286,N581);
nor #5 GN2428(N2428,N2288,N583);
nor #5 GN2429(N2429,N2290,N585);
nor #5 GN2430(N2430,N2292,N587);
nor #5 GN2431(N2431,N2294,N589);
nor #5 GN2432(N2432,N2380,N441);
nor #5 GN2433(N2433,N2435,N442);
nor #5 GN2434(N2434,N2436,N2469);
nor #5 GN2435(N2435,N2461,N2565);
nor #5 GN2436(N2436,N2434,N2566);
nor #5 GN2437(N2437,N2379,N2567);
nor #5 GN2438(N2438,N2299,N2568);
nor #5 GN2439(N2439,N2462,N2569);
nor #5 GN2440(N2440,N2280,N2441);
nor #5 GN2441(N2441,N2424,N2440);
nor #5 GN2442(N2442,N2282,N2443);
nor #5 GN2443(N2443,N2425,N2442);
nor #5 GN2444(N2444,N2284,N2445);
nor #5 GN2445(N2445,N2426,N2444);
nor #5 GN2446(N2446,N2286,N2447);
nor #5 GN2447(N2447,N2427,N2446);
nor #5 GN2448(N2448,N2288,N2449);
nor #5 GN2449(N2449,N2428,N2448);
nor #5 GN2450(N2450,N2290,N2451);
nor #5 GN2451(N2451,N2429,N2450);
nor #5 GN2452(N2452,N2292,N2453);
nor #5 GN2453(N2453,N2430,N2452);
nor #5 GN2454(N2454,N2294,N2455);
nor #5 GN2455(N2455,N2431,N2454);
nor #5 GN2456(N2456,N2463,N2578);
nor #5 GN2457(N2457,N2380,N2579);
nor #5 GN2458(N2458,N2459,N2498);
nor #5 GN2459(N2459,N2458,N2580);
nor #5 GN2460(N2460,N2500,N2502);
nor #5 GN2461(N2461,N2435,N2467);
nor #5 GN2462(N2462,N2439,N2475);
nor #5 GN2463(N2463,N2456,N2494);
nor #5 GN2464(N2464,N2458,N496);
nor #5 GN2465(N2465,N2434,N459);
nor #5 GN2467(N2467,N2415,N824);
nor #5 GN2469(N2469,N2566,N808);
nor #5 GN2471(N2471,N2567,N809);
nor #5 GN2473(N2473,N2568,N632);
nor #5 GN2475(N2475,N2569,N338);
nor #5 GN2494(N2494,N2578,N835);
nor #5 GN2496(N2496,N2579,N662);
nor #5 GN2498(N2498,N2580,N818);
nor #5 GN25(N25,N23,N32,N33,PA0);
nor #5 GN2500(N2500,N2460,N2581);
nor #5 GN2502(N2502,N2581,N819);
nor #5 GN2504(N2504,N2460,N334);
nor #5 GN256(N256,N330);
nor #5 GN2565(N2565,N2467,N824);
nor #5 GN2566(N2566,N2415,N808);
nor #5 GN2567(N2567,N2415,N809);
nor #5 GN2568(N2568,N2439,N632);
nor #5 GN2569(N2569,N2415,N338);
nor #5 GN2570(N2570,N2585,N2607);
nor #5 GN2571(N2571,N2586,N2610);
nor #5 GN2572(N2572,N2587,N2613);
nor #5 GN2573(N2573,N2588,N2616);
nor #5 GN2574(N2574,N2589,N2619);
nor #5 GN2575(N2575,N2590,N2622);
nor #5 GN2576(N2576,N2591,N2625);
nor #5 GN2577(N2577,N2592,N2628);
nor #5 GN2578(N2578,N2271,N835);
nor #5 GN2579(N2579,N2456,N662);
nor #5 GN2580(N2580,N2271,N818);
nor #5 GN2581(N2581,N2271,N819);
nor #5 GN2583(N2583,N115,PD4IN);
nor #5 GN2584(N2584,N115,N2583);
nor #5 GN2585(N2585,N2440,N800);
nor #5 GN2586(N2586,N2442,N801);
nor #5 GN2587(N2587,N2444,N802);
nor #5 GN2588(N2588,N2446,N803);
nor #5 GN2589(N2589,N2448,N804);
nor #5 GN2590(N2590,N2450,N805);
nor #5 GN2591(N2591,N2452,N806);
nor #5 GN2592(N2592,N2454,N807);
nor #5 GN2593(N2593,N2415,N2665);
nor #5 GN2594(N2594,N26,_HD4IN);
nor #5 GN2598(N2598,N2271,N2583);
nor #5 GN26(N26,N36);
nor #5 GN2607(N2607,N2570,N2697);
nor #5 GN2610(N2610,N2571,N2698);
nor #5 GN2613(N2613,N2572,N2699);
nor #5 GN2616(N2616,N2573,N2700);
nor #5 GN2619(N2619,N2574,N2701);
nor #5 GN2622(N2622,N2575,N2702);
nor #5 GN2625(N2625,N2576,N2703);
nor #5 GN2628(N2628,N2577,N2704);
nor #5 GN265(N265,N318,N434);
nor #5 GN2665(N2665,N2594,N26);
nor #5 GN269(N269,N2300,N2306,N2412);
nor #5 GN2696(N2696,N2707,N2729);
nor #5 GN2697(N2697,N2585,N800);
nor #5 GN2698(N2698,N2586,N801);
nor #5 GN2699(N2699,N2587,N802);
nor #5 GN27(N27,HA0,N38,N39);
nor #5 GN2700(N2700,N2588,N803);
nor #5 GN2701(N2701,N2589,N804);
nor #5 GN2702(N2702,N2590,N805);
nor #5 GN2703(N2703,N2591,N806);
nor #5 GN2704(N2704,N2592,N807);
nor #5 GN2705(N2705,N2764,N2766);
nor #5 GN2706(N2706,N115,PD3IN);
nor #5 GN2707(N2707,N115,N2706);
nor #5 GN2708(N2708,N2696,N601);
nor #5 GN2709(N2709,N2736,N2738);
nor #5 GN2710(N2710,N2709,N510);
nor #5 GN2711(N2711,N2740,N2742);
nor #5 GN2712(N2712,N2711,N579);
nor #5 GN2713(N2713,N2744,N2746);
nor #5 GN2714(N2714,N2713,N581);
nor #5 GN2715(N2715,N2748,N2750);
nor #5 GN2716(N2716,N2715,N583);
nor #5 GN2717(N2717,N2752,N2754);
nor #5 GN2718(N2718,N2717,N585);
nor #5 GN2719(N2719,N2756,N2758);
nor #5 GN2720(N2720,N2719,N587);
nor #5 GN2721(N2721,N2760,N2762);
nor #5 GN2722(N2722,N2721,N589);
nor #5 GN2723(N2723,N2885,N2927);
nor #5 GN2724(N2724,N1434,N2734);
nor #5 GN2725(N2725,N2723,N496);
nor #5 GN2726(N2726,N2705,N498);
nor #5 GN2729(N2729,N2696,N2706);
nor #5 GN2732(N2732,N2838,N924);
nor #5 GN2734(N2734,N1206,N2837,N2838);
nor #5 GN2736(N2736,N2709,N2839);
nor #5 GN2738(N2738,N2999,N701);
nor #5 GN2740(N2740,N2711,N2840);
nor #5 GN2742(N2742,N3000,N702);
nor #5 GN2744(N2744,N2713,N2841);
nor #5 GN2746(N2746,N3001,N703);
nor #5 GN2748(N2748,N2715,N2842);
nor #5 GN2750(N2750,N3002,N704);
nor #5 GN2752(N2752,N2717,N2843);
nor #5 GN2754(N2754,N3003,N705);
nor #5 GN2756(N2756,N2719,N2844);
nor #5 GN2758(N2758,N3004,N706);
nor #5 GN2760(N2760,N2721,N2845);
nor #5 GN2762(N2762,N3005,N707);
nor #5 GN2764(N2764,N2705,N2846);
nor #5 GN2766(N2766,N2846,N792);
nor #5 GN28(N28,HA0,HA1,N38);
nor #5 GN2837(N2837,N1206,N924);
nor #5 GN2838(N2838,N3020,N3021);
nor #5 GN2839(N2839,N2738,N701);
nor #5 GN2840(N2840,N2742,N702);
nor #5 GN2841(N2841,N2746,N703);
nor #5 GN2842(N2842,N2750,N704);
nor #5 GN2843(N2843,N2754,N705);
nor #5 GN2844(N2844,N2758,N706);
nor #5 GN2845(N2845,N2762,N707);
nor #5 GN2846(N2846,N3006,N792);
nor #5 GN2847(N2847,N2929,N2931);
nor #5 GN2848(N2848,N2708,N601);
nor #5 GN2849(N2849,N2710,N510);
nor #5 GN285(N285,N175,N442);
nor #5 GN2850(N2850,N2712,N579);
nor #5 GN2851(N2851,N2714,N581);
nor #5 GN2852(N2852,N2716,N583);
nor #5 GN2853(N2853,N2718,N585);
nor #5 GN2854(N2854,N2720,N587);
nor #5 GN2855(N2855,N2722,N589);
nor #5 GN2856(N2856,N2847,N334);
nor #5 GN2857(N2857,N1434,N335);
nor #5 GN2859(N2859,N2864,N2902);
nor #5 GN286(N286,N119,N334);
nor #5 GN2861(N2861,N2888,N2994);
nor #5 GN2862(N2862,N2889,N2995);
nor #5 GN2863(N2863,N2890,N2996);
nor #5 GN2864(N2864,N2859,N2997);
nor #5 GN2865(N2865,N2891,N2998);
nor #5 GN2866(N2866,N2708,N2867);
nor #5 GN2867(N2867,N2848,N2866);
nor #5 GN2868(N2868,N2710,N2869);
nor #5 GN2869(N2869,N2849,N2868);
nor #5 GN287(N287,N119,N441);
nor #5 GN2870(N2870,N2712,N2871);
nor #5 GN2871(N2871,N2850,N2870);
nor #5 GN2872(N2872,N2714,N2873);
nor #5 GN2873(N2873,N2851,N2872);
nor #5 GN2874(N2874,N2716,N2875);
nor #5 GN2875(N2875,N2852,N2874);
nor #5 GN2876(N2876,N2718,N2877);
nor #5 GN2877(N2877,N2853,N2876);
nor #5 GN2878(N2878,N2720,N2879);
nor #5 GN2879(N2879,N2854,N2878);
nor #5 GN2880(N2880,N2722,N2881);
nor #5 GN2881(N2881,N2855,N2880);
nor #5 GN2882(N2882,N2892,N3007);
nor #5 GN2883(N2883,N2884,N2925);
nor #5 GN2884(N2884,N2883,N3008);
nor #5 GN2885(N2885,N2723,N3009);
nor #5 GN2887(N2887,N1434,N325);
nor #5 GN2888(N2888,N2861,N2896);
nor #5 GN2889(N2889,N2862,N2898);
nor #5 GN2890(N2890,N2863,N2900);
nor #5 GN2891(N2891,N2865,N2904);
nor #5 GN2892(N2892,N2882,N2923);
nor #5 GN2894(N2894,N2859,N326);
nor #5 GN2896(N2896,N2838,N824);
nor #5 GN2898(N2898,N2995,N808);
nor #5 GN2900(N2900,N2996,N809);
nor #5 GN2902(N2902,N2997,N632);
nor #5 GN2904(N2904,N2998,N338);
nor #5 GN2923(N2923,N3007,N835);
nor #5 GN2925(N2925,N3008,N662);
nor #5 GN2927(N2927,N3009,N818);
nor #5 GN2929(N2929,N2847,N3010);
nor #5 GN2931(N2931,N3010,N819);
nor #5 GN2933(N2933,N2883,N441);
nor #5 GN2993(N2993,N2890,N327);
nor #5 GN2994(N2994,N2896,N824);
nor #5 GN2995(N2995,N2838,N808);
nor #5 GN2996(N2996,N2838,N809);
nor #5 GN2997(N2997,N2865,N632);
nor #5 GN2998(N2998,N2838,N338);
nor #5 GN2999(N2999,N3012,N3033);
nor #5 GN3000(N3000,N3013,N3036);
nor #5 GN3001(N3001,N3014,N3039);
nor #5 GN3002(N3002,N3015,N3042);
nor #5 GN3003(N3003,N3016,N3045);
nor #5 GN3004(N3004,N3017,N3048);
nor #5 GN3005(N3005,N3018,N3051);
nor #5 GN3006(N3006,N3019,N3054);
nor #5 GN3007(N3007,N2696,N835);
nor #5 GN3008(N3008,N2882,N662);
nor #5 GN3009(N3009,N2696,N818);
nor #5 GN3010(N3010,N2696,N819);
nor #5 GN3011(N3011,N2861,N442);
nor #5 GN3012(N3012,N2866,N800);
nor #5 GN3013(N3013,N2868,N801);
nor #5 GN3014(N3014,N2870,N802);
nor #5 GN3015(N3015,N2872,N803);
nor #5 GN3016(N3016,N2874,N804);
nor #5 GN3017(N3017,N2876,N805);
nor #5 GN3018(N3018,N2878,N806);
nor #5 GN3019(N3019,N2880,N807);
nor #5 GN3020(N3020,N2838,N3093);
nor #5 GN3021(N3021,N26,_HD3IN);
nor #5 GN3023(N3023,N2889,N459);
nor #5 GN3033(N3033,N2999,N3125);
nor #5 GN3036(N3036,N3000,N3126);
nor #5 GN3039(N3039,N3001,N3127);
nor #5 GN3042(N3042,N3002,N3128);
nor #5 GN3045(N3045,N3003,N3129);
nor #5 GN3048(N3048,N3004,N3130);
nor #5 GN3051(N3051,N3005,N3131);
nor #5 GN3054(N3054,N3006,N3132);
nor #5 GN3093(N3093,N26,N3021);
nor #5 GN31(N31,PA0);
nor #5 GN3124(N3124,N3441,N3455);
nor #5 GN3125(N3125,N3012,N800);
nor #5 GN3126(N3126,N3013,N801);
nor #5 GN3127(N3127,N3014,N802);
nor #5 GN3128(N3128,N3015,N803);
nor #5 GN3129(N3129,N3016,N804);
nor #5 GN3130(N3130,N3017,N805);
nor #5 GN3131(N3131,N3018,N806);
nor #5 GN3132(N3132,N3019,N807);
nor #5 GN3133(N3133,N3157,N3166,N3270);
nor #5 GN3134(N3134,N1327,N3590);
nor #5 GN3135(N3135,N3124,N601);
nor #5 GN3136(N3136,N3170,N3172);
nor #5 GN3137(N3137,N3136,N510);
nor #5 GN3138(N3138,N3174,N3176);
nor #5 GN3139(N3139,N3138,N579);
nor #5 GN3140(N3140,N3178,N3180);
nor #5 GN3141(N3141,N3140,N581);
nor #5 GN3142(N3142,N3182,N3184);
nor #5 GN3143(N3143,N3142,N583);
nor #5 GN3144(N3144,N3186,N3188);
nor #5 GN3145(N3145,N3144,N585);
nor #5 GN3146(N3146,N3190,N3192);
nor #5 GN3147(N3147,N3146,N587);
nor #5 GN3148(N3148,N3194,N3196);
nor #5 GN3149(N3149,N3148,N589);
nor #5 GN3150(N3150,N3198,N3200);
nor #5 GN3151(N3151,N3133,N335);
nor #5 GN3153(N3153,N3133,N325);
nor #5 GN3154(N3154,N3296,N3331);
nor #5 GN3156(N3156,N1453,N3164);
nor #5 GN3157(N3157,N3133,N3168);
nor #5 GN3158(N3158,N3150,N498);
nor #5 GN3160(N3160,N3154,N326);
nor #5 GN3164(N3164,N3133);
nor #5 GN3166(N3166,N3272,N924);
nor #5 GN3168(N3168,N1206,N3270,N3272);
nor #5 GN317(N317,N372);
nor #5 GN3170(N3170,N3136,N3273);
nor #5 GN3172(N3172,N3428,N701);
nor #5 GN3174(N3174,N3138,N3274);
nor #5 GN3176(N3176,N3429,N702);
nor #5 GN3178(N3178,N3140,N3275);
nor #5 GN318(N318,N217,N265);
nor #5 GN3180(N3180,N3430,N703);
nor #5 GN3182(N3182,N3142,N3276);
nor #5 GN3184(N3184,N3431,N704);
nor #5 GN3186(N3186,N3144,N3277);
nor #5 GN3188(N3188,N3432,N705);
nor #5 GN319(N319,N218,N317,N343);
nor #5 GN3190(N3190,N3146,N3278);
nor #5 GN3192(N3192,N3433,N706);
nor #5 GN3194(N3194,N3148,N3279);
nor #5 GN3196(N3196,N3434,N707);
nor #5 GN3198(N3198,N3150,N3280);
nor #5 GN32(N32,PA1);
nor #5 GN320(N320,N333);
nor #5 GN3200(N3200,N3280,N792);
nor #5 GN321(N321,N265,N319);
nor #5 GN322(N322,N125,N326);
nor #5 GN323(N323,N464,N594);
nor #5 GN3237(N3237,N3295,N3329);
nor #5 GN3238(N3238,N3315,N3354);
nor #5 GN324(N324,N127,N317,N498);
nor #5 GN325(N325,N140);
nor #5 GN326(N326,N213,N23);
nor #5 GN327(N327,N214);
nor #5 GN3270(N3270,N1206,N924);
nor #5 GN3271(N3271,N3237,N327);
nor #5 GN3272(N3272,N3450,N3451);
nor #5 GN3273(N3273,N3172,N701);
nor #5 GN3274(N3274,N3176,N702);
nor #5 GN3275(N3275,N3180,N703);
nor #5 GN3276(N3276,N3184,N704);
nor #5 GN3277(N3277,N3188,N705);
nor #5 GN3278(N3278,N3192,N706);
nor #5 GN3279(N3279,N3196,N707);
nor #5 GN328(N328,N338);
nor #5 GN3280(N3280,N3435,N792);
nor #5 GN3281(N3281,N3135,N601);
nor #5 GN3282(N3282,N3137,N510);
nor #5 GN3283(N3283,N3139,N579);
nor #5 GN3284(N3284,N3141,N581);
nor #5 GN3285(N3285,N3143,N583);
nor #5 GN3286(N3286,N3145,N585);
nor #5 GN3287(N3287,N3147,N587);
nor #5 GN3288(N3288,N3149,N589);
nor #5 GN3289(N3289,N3238,N441);
nor #5 GN329(N329,N328,N592,N594,N632);
nor #5 GN3291(N3291,N3293,N442);
nor #5 GN3292(N3292,N3294,N3327);
nor #5 GN3293(N3293,N3319,N3423);
nor #5 GN3294(N3294,N3292,N3424);
nor #5 GN3295(N3295,N3237,N3425);
nor #5 GN3296(N3296,N3154,N3426);
nor #5 GN3297(N3297,N3320,N3427);
nor #5 GN3298(N3298,N3135,N3299);
nor #5 GN3299(N3299,N3281,N3298);
nor #5 GN33(N33,PA2);
nor #5 GN330(N330,N329,N737);
nor #5 GN3300(N3300,N3137,N3301);
nor #5 GN3301(N3301,N3282,N3300);
nor #5 GN3302(N3302,N3139,N3303);
nor #5 GN3303(N3303,N3283,N3302);
nor #5 GN3304(N3304,N3141,N3305);
nor #5 GN3305(N3305,N3284,N3304);
nor #5 GN3306(N3306,N3143,N3307);
nor #5 GN3307(N3307,N3285,N3306);
nor #5 GN3308(N3308,N3145,N3309);
nor #5 GN3309(N3309,N3286,N3308);
nor #5 GN331(N331,N323);
nor #5 GN3310(N3310,N3147,N3311);
nor #5 GN3311(N3311,N3287,N3310);
nor #5 GN3312(N3312,N3149,N3313);
nor #5 GN3313(N3313,N3288,N3312);
nor #5 GN3314(N3314,N3321,N3436);
nor #5 GN3315(N3315,N3238,N3437);
nor #5 GN3316(N3316,N3317,N3356);
nor #5 GN3317(N3317,N3316,N3438);
nor #5 GN3318(N3318,N3358,N3360);
nor #5 GN3319(N3319,N3293,N3325);
nor #5 GN332(N332,HRST);
nor #5 GN3320(N3320,N3297,N3333);
nor #5 GN3321(N3321,N3314,N3352);
nor #5 GN3322(N3322,N3316,N496);
nor #5 GN3323(N3323,N3292,N459);
nor #5 GN3325(N3325,N3272,N824);
nor #5 GN3327(N3327,N3424,N808);
nor #5 GN3329(N3329,N3425,N809);
nor #5 GN333(N333,N317,N347,N772);
nor #5 GN3331(N3331,N3426,N632);
nor #5 GN3333(N3333,N338,N3427);
nor #5 GN334(N334,N220);
nor #5 GN335(N335,N141);
nor #5 GN3352(N3352,N3436,N835);
nor #5 GN3354(N3354,N3437,N662);
nor #5 GN3356(N3356,N3438,N818);
nor #5 GN3358(N3358,N3318,N3439);
nor #5 GN3360(N3360,N3439,N819);
nor #5 GN3362(N3362,N3318,N334);
nor #5 GN338(N338,N323);
nor #5 GN34(N34,N25);
nor #5 GN3423(N3423,N3325,N824);
nor #5 GN3424(N3424,N3272,N808);
nor #5 GN3425(N3425,N3272,N809);
nor #5 GN3426(N3426,N3297,N632);
nor #5 GN3427(N3427,N3272,N338);
nor #5 GN3428(N3428,N3442,N3464);
nor #5 GN3429(N3429,N3443,N3467);
nor #5 GN343(N343,N319,N398);
nor #5 GN3430(N3430,N3444,N3470);
nor #5 GN3431(N3431,N3445,N3473);
nor #5 GN3432(N3432,N3446,N3476);
nor #5 GN3433(N3433,N3447,N3479);
nor #5 GN3434(N3434,N3448,N3482);
nor #5 GN3435(N3435,N3449,N3485);
nor #5 GN3436(N3436,N3124,N835);
nor #5 GN3437(N3437,N3314,N662);
nor #5 GN3438(N3438,N3124,N818);
nor #5 GN3439(N3439,N3124,N819);
nor #5 GN3440(N3440,N115,PD2IN);
nor #5 GN3441(N3441,N115,N3440);
nor #5 GN3442(N3442,N3298,N800);
nor #5 GN3443(N3443,N3300,N801);
nor #5 GN3444(N3444,N3302,N802);
nor #5 GN3445(N3445,N3304,N803);
nor #5 GN3446(N3446,N3306,N804);
nor #5 GN3447(N3447,N3308,N805);
nor #5 GN3448(N3448,N3310,N806);
nor #5 GN3449(N3449,N3312,N807);
nor #5 GN3450(N3450,N3272,N3522);
nor #5 GN3451(N3451,N26,_HD2IN);
nor #5 GN3455(N3455,N3124,N3440);
nor #5 GN3464(N3464,N3428,N3555);
nor #5 GN3467(N3467,N3429,N3556);
nor #5 GN347(N347,N440,N597,N662,N712);
nor #5 GN3470(N3470,N3430,N3557);
nor #5 GN3473(N3473,N3431,N3558);
nor #5 GN3476(N3476,N3432,N3559);
nor #5 GN3479(N3479,N3433,N3560);
nor #5 GN3482(N3482,N3434,N3561);
nor #5 GN3485(N3485,N3435,N3562);
nor #5 GN35(N35,DACK,PNRDS);
nor #5 GN350(N350,N324,N384,N431);
nor #5 GN3522(N3522,N26,N3451);
nor #5 GN3554(N3554,N3869,N3883);
nor #5 GN3555(N3555,N3442,N800);
nor #5 GN3556(N3556,N3443,N801);
nor #5 GN3557(N3557,N3444,N802);
nor #5 GN3558(N3558,N3445,N803);
nor #5 GN3559(N3559,N3446,N804);
nor #5 GN3560(N3560,N3447,N805);
nor #5 GN3561(N3561,N3448,N806);
nor #5 GN3562(N3562,N3449,N807);
nor #5 GN3563(N3563,N3584,N3592,N3697);
nor #5 GN3564(N3564,N3554,N601);
nor #5 GN3565(N3565,N3596,N3598);
nor #5 GN3566(N3566,N3565,N510);
nor #5 GN3567(N3567,N3600,N3602);
nor #5 GN3568(N3568,N3567,N579);
nor #5 GN3569(N3569,N3604,N3606);
nor #5 GN3570(N3570,N3569,N581);
nor #5 GN3571(N3571,N3608,N3610);
nor #5 GN3572(N3572,N3571,N583);
nor #5 GN3573(N3573,N3612,N3614);
nor #5 GN3574(N3574,N3573,N585);
nor #5 GN3575(N3575,N3616,N3618);
nor #5 GN3576(N3576,N3575,N587);
nor #5 GN3577(N3577,N3620,N3622);
nor #5 GN3578(N3578,N3577,N589);
nor #5 GN3579(N3579,N3624,N3626);
nor #5 GN3580(N3580,N335,N3563);
nor #5 GN3582(N3582,N325,N3563);
nor #5 GN3583(N3583,N3723,N3758);
nor #5 GN3584(N3584,N3563,N3594);
nor #5 GN3585(N3585,N3579,N498);
nor #5 GN3587(N3587,N326,N3583);
nor #5 GN3590(N3590,N3563);
nor #5 GN3592(N3592,N3699,N924);
nor #5 GN3594(N3594,N1206,N3697,N3699);
nor #5 GN3596(N3596,N3565,N3700);
nor #5 GN3598(N3598,N3856,N701);
nor #5 GN36(N36,HCS,HRW,N116);
nor #5 GN3600(N3600,N3567,N3701);
nor #5 GN3602(N3602,N3857,N702);
nor #5 GN3604(N3604,N3569,N3702);
nor #5 GN3606(N3606,N3858,N703);
nor #5 GN3608(N3608,N3571,N3703);
nor #5 GN3610(N3610,N3859,N704);
nor #5 GN3612(N3612,N3573,N3704);
nor #5 GN3614(N3614,N3860,N705);
nor #5 GN3616(N3616,N3575,N3705);
nor #5 GN3618(N3618,N3861,N706);
nor #5 GN3620(N3620,N3577,N3706);
nor #5 GN3622(N3622,N3862,N707);
nor #5 GN3624(N3624,N3579,N3707);
nor #5 GN3626(N3626,N3707,N792);
nor #5 GN364(N364,N454,N507);
nor #5 GN3664(N3664,N3722,N3756);
nor #5 GN3665(N3665,N3742,N3781);
nor #5 GN3697(N3697,N1206,N924);
nor #5 GN3698(N3698,N327,N3664);
nor #5 GN3699(N3699,N3878,N3879);
nor #5 GN37(N37,N27);
nor #5 GN3700(N3700,N3598,N701);
nor #5 GN3701(N3701,N3602,N702);
nor #5 GN3702(N3702,N3606,N703);
nor #5 GN3703(N3703,N3610,N704);
nor #5 GN3704(N3704,N3614,N705);
nor #5 GN3705(N3705,N3618,N706);
nor #5 GN3706(N3706,N3622,N707);
nor #5 GN3707(N3707,N3863,N792);
nor #5 GN3708(N3708,N3564,N601);
nor #5 GN3709(N3709,N3566,N510);
nor #5 GN3710(N3710,N3568,N579);
nor #5 GN3711(N3711,N3570,N581);
nor #5 GN3712(N3712,N3572,N583);
nor #5 GN3713(N3713,N3574,N585);
nor #5 GN3714(N3714,N3576,N587);
nor #5 GN3715(N3715,N3578,N589);
nor #5 GN3716(N3716,N3665,N441);
nor #5 GN3718(N3718,N3720,N442);
nor #5 GN3719(N3719,N3721,N3754);
nor #5 GN372(N372,N332,N435);
nor #5 GN3720(N3720,N3746,N3851);
nor #5 GN3721(N3721,N3719,N3852);
nor #5 GN3722(N3722,N3664,N3853);
nor #5 GN3723(N3723,N3583,N3854);
nor #5 GN3724(N3724,N3747,N3855);
nor #5 GN3725(N3725,N3564,N3726);
nor #5 GN3726(N3726,N3708,N3725);
nor #5 GN3727(N3727,N3566,N3728);
nor #5 GN3728(N3728,N3709,N3727);
nor #5 GN3729(N3729,N3568,N3730);
nor #5 GN3730(N3730,N3710,N3729);
nor #5 GN3731(N3731,N3570,N3732);
nor #5 GN3732(N3732,N3711,N3731);
nor #5 GN3733(N3733,N3572,N3734);
nor #5 GN3734(N3734,N3712,N3733);
nor #5 GN3735(N3735,N3574,N3736);
nor #5 GN3736(N3736,N3713,N3735);
nor #5 GN3737(N3737,N3576,N3738);
nor #5 GN3738(N3738,N3714,N3737);
nor #5 GN3739(N3739,N3578,N3740);
nor #5 GN3740(N3740,N3715,N3739);
nor #5 GN3741(N3741,N3748,N3864);
nor #5 GN3742(N3742,N3665,N3865);
nor #5 GN3743(N3743,N3744,N3783);
nor #5 GN3744(N3744,N3743,N3866);
nor #5 GN3745(N3745,N3785,N3787);
nor #5 GN3746(N3746,N3720,N3752);
nor #5 GN3747(N3747,N3724,N3760);
nor #5 GN3748(N3748,N3741,N3779);
nor #5 GN3749(N3749,N3743,N496);
nor #5 GN3750(N3750,N3719,N459);
nor #5 GN3752(N3752,N3699,N824);
nor #5 GN3754(N3754,N3852,N808);
nor #5 GN3756(N3756,N3853,N809);
nor #5 GN3758(N3758,N3854,N632);
nor #5 GN3760(N3760,N338,N3855);
nor #5 GN3779(N3779,N3864,N835);
nor #5 GN3781(N3781,N3865,N662);
nor #5 GN3783(N3783,N3866,N818);
nor #5 GN3785(N3785,N3745,N3867);
nor #5 GN3787(N3787,N3867,N819);
nor #5 GN3789(N3789,N334,N3745);
nor #5 GN38(N38,HA2);
nor #5 GN384(N384,N350,N437);
nor #5 GN3851(N3851,N3752,N824);
nor #5 GN3852(N3852,N3699,N808);
nor #5 GN3853(N3853,N3699,N809);
nor #5 GN3854(N3854,N3724,N632);
nor #5 GN3855(N3855,N338,N3699);
nor #5 GN3856(N3856,N3870,N3892);
nor #5 GN3857(N3857,N3871,N3895);
nor #5 GN3858(N3858,N3872,N3898);
nor #5 GN3859(N3859,N3873,N3901);
nor #5 GN3860(N3860,N3874,N3904);
nor #5 GN3861(N3861,N3875,N3907);
nor #5 GN3862(N3862,N3876,N3910);
nor #5 GN3863(N3863,N3877,N3913);
nor #5 GN3864(N3864,N3554,N835);
nor #5 GN3865(N3865,N3741,N662);
nor #5 GN3866(N3866,N3554,N818);
nor #5 GN3867(N3867,N3554,N819);
nor #5 GN3868(N3868,N115,PD1IN);
nor #5 GN3869(N3869,N115,N3868);
nor #5 GN3870(N3870,N3725,N800);
nor #5 GN3871(N3871,N3727,N801);
nor #5 GN3872(N3872,N3729,N802);
nor #5 GN3873(N3873,N3731,N803);
nor #5 GN3874(N3874,N3733,N804);
nor #5 GN3875(N3875,N3735,N805);
nor #5 GN3876(N3876,N3737,N806);
nor #5 GN3877(N3877,N3739,N807);
nor #5 GN3878(N3878,N3699,N3950);
nor #5 GN3879(N3879,N26,_HD1IN);
nor #5 GN3883(N3883,N3554,N3868);
nor #5 GN3892(N3892,N3856,N3983);
nor #5 GN3895(N3895,N3857,N3984);
nor #5 GN3898(N3898,N3858,N3985);
nor #5 GN39(N39,HA1);
nor #5 GN390(N390,N438,N493);
nor #5 GN3901(N3901,N3859,N3986);
nor #5 GN3904(N3904,N3860,N3987);
nor #5 GN3907(N3907,N3861,N3988);
nor #5 GN3910(N3910,N3862,N3989);
nor #5 GN3913(N3913,N3863,N3990);
nor #5 GN3950(N3950,N26,N3879);
nor #5 GN397(N397,N364,N433);
nor #5 GN398(N398,N320,N399);
nor #5 GN3982(N3982,N4304,N4307);
nor #5 GN3983(N3983,N3870,N800);
nor #5 GN3984(N3984,N3871,N801);
nor #5 GN3985(N3985,N3872,N802);
nor #5 GN3986(N3986,N3873,N803);
nor #5 GN3987(N3987,N3874,N804);
nor #5 GN3988(N3988,N3875,N805);
nor #5 GN3989(N3989,N3876,N806);
nor #5 GN399(N399,N436);
nor #5 GN3990(N3990,N3877,N807);
nor #5 GN3991(N3991,N3982,N601);
nor #5 GN3992(N3992,N4021,N4023);
nor #5 GN3993(N3993,N3992,N510);
nor #5 GN3994(N3994,N4025,N4027);
nor #5 GN3995(N3995,N3994,N579);
nor #5 GN3996(N3996,N4029,N4031);
nor #5 GN3997(N3997,N3996,N581);
nor #5 GN3998(N3998,N4033,N4035);
nor #5 GN3999(N3999,N3998,N583);
nor #5 GN40(N40,HA0);
nor #5 GN4000(N4000,N4037,N4039);
nor #5 GN4001(N4001,N4000,N585);
nor #5 GN4002(N4002,N4041,N4043);
nor #5 GN4003(N4003,N4002,N587);
nor #5 GN4004(N4004,N4045,N4047);
nor #5 GN4005(N4005,N4004,N589);
nor #5 GN4006(N4006,N4049,N4051);
nor #5 GN4007(N4007,N1346,N335);
nor #5 GN4009(N4009,N1346,N325);
nor #5 GN4010(N4010,N4149,N4184);
nor #5 GN4011(N4011,N1346,N4019);
nor #5 GN4012(N4012,N4006,N498);
nor #5 GN4014(N4014,N326,N4010);
nor #5 GN4017(N4017,N4125,N924);
nor #5 GN4019(N4019,N1206,N4123,N4125);
nor #5 GN4021(N4021,N3992,N4126);
nor #5 GN4023(N4023,N4281,N701);
nor #5 GN4025(N4025,N3994,N4127);
nor #5 GN4027(N4027,N4282,N702);
nor #5 GN4029(N4029,N3996,N4128);
nor #5 GN4031(N4031,N4283,N703);
nor #5 GN4033(N4033,N3998,N4129);
nor #5 GN4035(N4035,N4284,N704);
nor #5 GN4037(N4037,N4000,N4130);
nor #5 GN4039(N4039,N4285,N705);
nor #5 GN4041(N4041,N4002,N4131);
nor #5 GN4043(N4043,N4286,N706);
nor #5 GN4045(N4045,N4004,N4132);
nor #5 GN4047(N4047,N4287,N707);
nor #5 GN4049(N4049,N4006,N4133);
nor #5 GN4051(N4051,N4133,N792);
nor #5 GN4090(N4090,N4148,N4182);
nor #5 GN4091(N4091,N4168,N4207);
nor #5 GN4123(N4123,N1206,N924);
nor #5 GN4124(N4124,N327,N4090);
nor #5 GN4125(N4125,N4302,N4303);
nor #5 GN4126(N4126,N4023,N701);
nor #5 GN4127(N4127,N4027,N702);
nor #5 GN4128(N4128,N4031,N703);
nor #5 GN4129(N4129,N4035,N704);
nor #5 GN4130(N4130,N4039,N705);
nor #5 GN4131(N4131,N4043,N706);
nor #5 GN4132(N4132,N4047,N707);
nor #5 GN4133(N4133,N4288,N792);
nor #5 GN4134(N4134,N3991,N601);
nor #5 GN4135(N4135,N3993,N510);
nor #5 GN4136(N4136,N3995,N579);
nor #5 GN4137(N4137,N3997,N581);
nor #5 GN4138(N4138,N3999,N583);
nor #5 GN4139(N4139,N4001,N585);
nor #5 GN4140(N4140,N4003,N587);
nor #5 GN4141(N4141,N4005,N589);
nor #5 GN4142(N4142,N4091,N441);
nor #5 GN4144(N4144,N4146,N442);
nor #5 GN4145(N4145,N4147,N4180);
nor #5 GN4146(N4146,N4172,N4276);
nor #5 GN4147(N4147,N4145,N4277);
nor #5 GN4148(N4148,N4090,N4278);
nor #5 GN4149(N4149,N4010,N4279);
nor #5 GN4150(N4150,N4173,N4280);
nor #5 GN4151(N4151,N3991,N4152);
nor #5 GN4152(N4152,N4134,N4151);
nor #5 GN4153(N4153,N3993,N4154);
nor #5 GN4154(N4154,N4135,N4153);
nor #5 GN4155(N4155,N3995,N4156);
nor #5 GN4156(N4156,N4136,N4155);
nor #5 GN4157(N4157,N3997,N4158);
nor #5 GN4158(N4158,N4137,N4157);
nor #5 GN4159(N4159,N3999,N4160);
nor #5 GN4160(N4160,N4138,N4159);
nor #5 GN4161(N4161,N4001,N4162);
nor #5 GN4162(N4162,N4139,N4161);
nor #5 GN4163(N4163,N4003,N4164);
nor #5 GN4164(N4164,N4140,N4163);
nor #5 GN4165(N4165,N4005,N4166);
nor #5 GN4166(N4166,N4141,N4165);
nor #5 GN4167(N4167,N4174,N4289);
nor #5 GN4168(N4168,N4091,N4290);
nor #5 GN4169(N4169,N4170,N4209);
nor #5 GN4170(N4170,N4169,N4291);
nor #5 GN4171(N4171,N4211,N4213);
nor #5 GN4172(N4172,N4146,N4178);
nor #5 GN4173(N4173,N4150,N4186);
nor #5 GN4174(N4174,N4167,N4205);
nor #5 GN4175(N4175,N4169,N496);
nor #5 GN4176(N4176,N4145,N459);
nor #5 GN4178(N4178,N4125,N824);
nor #5 GN4180(N4180,N4277,N808);
nor #5 GN4182(N4182,N4278,N809);
nor #5 GN4184(N4184,N4279,N632);
nor #5 GN4186(N4186,N338,N4280);
nor #5 GN4205(N4205,N4289,N835);
nor #5 GN4207(N4207,N4290,N662);
nor #5 GN4209(N4209,N4291,N818);
nor #5 GN4211(N4211,N4171,N4292);
nor #5 GN4213(N4213,N4292,N819);
nor #5 GN4215(N4215,N334,N4171);
nor #5 GN4276(N4276,N4178,N824);
nor #5 GN4277(N4277,N4125,N808);
nor #5 GN4278(N4278,N4125,N809);
nor #5 GN4279(N4279,N4150,N632);
nor #5 GN4280(N4280,N338,N4125);
nor #5 GN4281(N4281,N4294,N4316);
nor #5 GN4282(N4282,N4295,N4319);
nor #5 GN4283(N4283,N4296,N4322);
nor #5 GN4284(N4284,N4297,N4325);
nor #5 GN4285(N4285,N4298,N4328);
nor #5 GN4286(N4286,N4299,N4331);
nor #5 GN4287(N4287,N4300,N4334);
nor #5 GN4288(N4288,N4301,N4337);
nor #5 GN4289(N4289,N3982,N835);
nor #5 GN4290(N4290,N4167,N662);
nor #5 GN4291(N4291,N3982,N818);
nor #5 GN4292(N4292,N3982,N819);
nor #5 GN4293(N4293,N115,PD0IN);
nor #5 GN4294(N4294,N4151,N800);
nor #5 GN4295(N4295,N4153,N801);
nor #5 GN4296(N4296,N4155,N802);
nor #5 GN4297(N4297,N4157,N803);
nor #5 GN4298(N4298,N4159,N804);
nor #5 GN4299(N4299,N4161,N805);
nor #5 GN430(N430,N317);
nor #5 GN4300(N4300,N4163,N806);
nor #5 GN4301(N4301,N4165,N807);
nor #5 GN4302(N4302,N26,_HD0IN);
nor #5 GN4303(N4303,N4125,N4375);
nor #5 GN4304(N4304,N115,N4293);
nor #5 GN4307(N4307,N3982,N4293);
nor #5 GN431(N431,N116,N430);
nor #5 GN4316(N4316,N4281,N4406);
nor #5 GN4319(N4319,N4282,N4407);
nor #5 GN432(N432,N322,N439);
nor #5 GN4322(N4322,N4283,N4408);
nor #5 GN4325(N4325,N4284,N4409);
nor #5 GN4328(N4328,N4285,N4410);
nor #5 GN433(N433,N285,N397);
nor #5 GN4331(N4331,N4286,N4411);
nor #5 GN4334(N4334,N4287,N4412);
nor #5 GN4337(N4337,N4288,N4413);
nor #5 GN434(N434,N256,N331);
nor #5 GN435(N435,N1457,N1464,N1570);
nor #5 GN436(N436,N490,N597);
nor #5 GN437(N437,N602,N659);
nor #5 GN4375(N4375,N26,N4302);
nor #5 GN438(N438,N127,N441);
nor #5 GN439(N439,N330,N432);
nor #5 GN440(N440,N390,N438);
nor #5 GN4406(N4406,N4294,N800);
nor #5 GN4407(N4407,N4295,N801);
nor #5 GN4408(N4408,N4296,N802);
nor #5 GN4409(N4409,N4297,N803);
nor #5 GN441(N441,N221);
nor #5 GN4410(N4410,N4298,N804);
nor #5 GN4411(N4411,N4299,N805);
nor #5 GN4412(N4412,N4300,N806);
nor #5 GN4413(N4413,N4301,N807);
nor #5 GN442(N442,N211);
nor #5 GN443(N443,N462,N464);
nor #5 GN444(N444,N285,N433,N507);
nor #5 GN445(N445,N455,N468,N510,N591);
nor #5 GN446(N446,N470,N472,N514,N579);
nor #5 GN447(N447,N473,N475,N518,N581);
nor #5 GN448(N448,N476,N478,N522,N583);
nor #5 GN449(N449,N479,N481,N526,N585);
nor #5 GN450(N450,N456,N483,N530,N587);
nor #5 GN451(N451,N486,N488,N533,N589);
nor #5 GN452(N452,N490,N492);
nor #5 GN453(N453,N219,N466);
nor #5 GN454(N454,N364,N444);
nor #5 GN455(N455,N445,N507,N638,N701);
nor #5 GN456(N456,N450,N526,N653,N706);
nor #5 GN457(N457,N324,N350);
nor #5 GN459(N459,N212);
nor #5 GN462(N462,N287,N443);
nor #5 GN464(N464,N323,N329);
nor #5 GN466(N466,N453,N595,N596);
nor #5 GN468(N468,N455,N717);
nor #5 GN470(N470,N472,N718);
nor #5 GN472(N472,N446,N591,N641,N702);
nor #5 GN473(N473,N475,N719);
nor #5 GN475(N475,N447,N514,N644,N703);
nor #5 GN476(N476,N478,N720);
nor #5 GN478(N478,N448,N518,N647,N704);
nor #5 GN479(N479,N481,N721);
nor #5 GN481(N481,N449,N522,N650,N705);
nor #5 GN483(N483,N456,N722);
nor #5 GN486(N486,N488,N723);
nor #5 GN488(N488,N451,N530,N656,N707);
nor #5 GN490(N490,N317,N347,N436);
nor #5 GN492(N492,N215,N452);
nor #5 GN493(N493,N333,N390);
nor #5 GN496(N496,N222);
nor #5 GN498(N498,N223);
nor #5 GN50(N50,HRW);
nor #5 GN507(N507,N444,N454,N455,N800);
nor #5 GN510(N510,N541);
nor #5 GN514(N514,N446,N475,N542,N802);
nor #5 GN518(N518,N447,N478,N543,N803);
nor #5 GN522(N522,N448,N481,N544,N804);
nor #5 GN526(N526,N449,N456,N545,N805);
nor #5 GN530(N530,N450,N488,N546,N806);
nor #5 GN533(N533,N451,N547,N602,N807);
nor #5 GN541(N541,N445,N578);
nor #5 GN542(N542,N446,N580);
nor #5 GN543(N543,N447,N582);
nor #5 GN544(N544,N448,N584);
nor #5 GN545(N545,N449,N586);
nor #5 GN546(N546,N450,N588);
nor #5 GN547(N547,N451,N590);
nor #5 GN578(N578,N541,N591);
nor #5 GN579(N579,N542);
nor #5 GN580(N580,N514,N542);
nor #5 GN581(N581,N543);
nor #5 GN582(N582,N518,N543);
nor #5 GN583(N583,N544);
nor #5 GN584(N584,N522,N544);
nor #5 GN585(N585,N545);
nor #5 GN586(N586,N526,N545);
nor #5 GN587(N587,N546);
nor #5 GN588(N588,N530,N546);
nor #5 GN589(N589,N547);
nor #5 GN590(N590,N533,N547);
nor #5 GN591(N591,N445,N472,N541,N801);
nor #5 GN592(N592,N322,N432);
nor #5 GN594(N594,N287,N329,N462);
nor #5 GN595(N595,N219,N710,N799);
nor #5 GN596(N596,N219,N716,N799);
nor #5 GN597(N597,N215,N347,N492);
nor #5 GN598(N598,N125,N442);
nor #5 GN599(N599,N125,N459);
nor #5 GN600(N600,N125,N327);
nor #5 GN601(N601,N454);
nor #5 GN602(N602,N457,N533,N659,N711);
nor #5 GN603(N603,N127,N334);
nor #5 GN604(N604,N127,N496);
nor #5 GN628(N628,N317,N599,N714);
nor #5 GN632(N632,N330);
nor #5 GN638(N638,N507,N827);
nor #5 GN641(N641,N591,N828);
nor #5 GN644(N644,N514,N829);
nor #5 GN647(N647,N518,N830);
nor #5 GN650(N650,N522,N831);
nor #5 GN653(N653,N526,N832);
nor #5 GN656(N656,N530,N833);
nor #5 GN659(N659,N437,N457);
nor #5 GN662(N662,N333);
nor #5 GN664(N664,N317,N604,N724);
nor #5 GN666(N666,N317,N603,N725);
nor #5 GN701(N701,N468);
nor #5 GN702(N702,N470);
nor #5 GN703(N703,N473);
nor #5 GN704(N704,N476);
nor #5 GN705(N705,N479);
nor #5 GN706(N706,N483);
nor #5 GN707(N707,N486);
nor #5 GN708(N708,N317,N598,N713);
nor #5 GN709(N709,N317,N600,N715);
nor #5 GN710(N710,N825,N826);
nor #5 GN711(N711,N533,N834);
nor #5 GN712(N712,N835);
nor #5 GN713(N713,N207,N708);
nor #5 GN714(N714,N286,N628);
nor #5 GN715(N715,N208,N709);
nor #5 GN716(N716,N710);
nor #5 GN717(N717,N445,N468);
nor #5 GN718(N718,N446,N470);
nor #5 GN719(N719,N447,N473);
nor #5 GN720(N720,N448,N476);
nor #5 GN721(N721,N449,N479);
nor #5 GN722(N722,N450,N483);
nor #5 GN723(N723,N451,N486);
nor #5 GN724(N724,N209,N664);
nor #5 GN725(N725,N177,N666);
nor #5 GN737(N737,N317,N330,N592);
nor #5 GN772(N772,N333,N440);
nor #5 GN792(N792,N437);
nor #5 GN799(N799,N902);
nor #5 GN800(N800,N638);
nor #5 GN801(N801,N641);
nor #5 GN802(N802,N644);
nor #5 GN803(N803,N647);
nor #5 GN804(N804,N650);
nor #5 GN805(N805,N653);
nor #5 GN806(N806,N656);
nor #5 GN807(N807,N711);
nor #5 GN808(N808,N286);
nor #5 GN809(N809,N208);
nor #5 GN818(N818,N209);
nor #5 GN819(N819,N177);
nor #5 GN822(N822,N115,N837);
nor #5 GN823(N823,N822,N839);
nor #5 GN824(N824,N207);
nor #5 GN825(N825,N710,N876);
nor #5 GN826(N826,N26,_HD7IN);
nor #5 GN827(N827,N455,N638);
nor #5 GN828(N828,N472,N641);
nor #5 GN829(N829,N475,N644);
nor #5 GN830(N830,N478,N647);
nor #5 GN831(N831,N481,N650);
nor #5 GN832(N832,N456,N653);
nor #5 GN833(N833,N488,N656);
nor #5 GN834(N834,N602,N711);
nor #5 GN835(N835,N436);
nor #5 GN837(N837,N115,PD7IN);
nor #5 GN839(N839,N823,N837);
nor #5 GN84(N84,N28);
nor #5 GN876(N876,N26,N826);
nor #5 GN899(N899,N117,N666);
nor #5 GN900(N900,N326,N923);
nor #5 GN901(N901,N974);
nor #5 GN902(N902,N901);
nor #5 GN903(N903,N453);
nor #5 GN904(N904,N601,N823);
nor #5 GN905(N905,N932,N934);
nor #5 GN906(N906,N510,N905);
nor #5 GN907(N907,N936,N938);
nor #5 GN908(N908,N579,N907);
nor #5 GN909(N909,N940,N942);
nor #5 GN910(N910,N581,N909);
nor #5 GN911(N911,N944,N946);
nor #5 GN912(N912,N583,N911);
nor #5 GN913(N913,N948,N950);
nor #5 GN914(N914,N585,N913);
nor #5 GN915(N915,N952,N954);
nor #5 GN916(N916,N587,N915);
nor #5 GN917(N917,N956,N958);
nor #5 GN918(N918,N589,N917);
nor #5 GN919(N919,N960,N962);
nor #5 GN920(N920,N1081,N1119);
nor #5 GN921(N921,N496,N920);
nor #5 GN922(N922,N325,N708);
nor #5 GN923(N923,N1061,N1095);
nor #5 GN924(N924,N332,N596);
nor #5 GN926(N926,N1002,N327);
nor #5 GN932(N932,N1037,N905);
nor #5 GN934(N934,N1194,N701);
nor #5 GN936(N936,N1038,N907);
nor #5 GN938(N938,N1195,N702);
nor #5 GN940(N940,N1039,N909);
nor #5 GN942(N942,N1196,N703);
nor #5 GN944(N944,N1040,N911);
nor #5 GN946(N946,N1197,N704);
nor #5 GN948(N948,N1041,N913);
nor #5 GN950(N950,N1198,N705);
nor #5 GN952(N952,N1042,N915);
nor #5 GN954(N954,N1199,N706);
nor #5 GN956(N956,N1043,N917);
nor #5 GN958(N958,N1200,N707);
nor #5 GN960(N960,N1044,N919);
nor #5 GN962(N962,N1044,N792);
nor #5 GN967(N967,N335,N792);
nor #5 GN974(N974,N1003);
nor #5 GPD0OUT(PD0OUT,N4009,N4014,N4124,N4144,N4176);
nor #5 GPD1OUT(PD1OUT,N3582,N3587,N3698,N3718,N3750);
nor #5 GPD2OUT(PD2OUT,N3153,N3160,N3271,N3291,N3323);
nor #5 GPD3OUT(PD3OUT,N2887,N2894,N2993,N3011,N3023);
nor #5 GPD4OUT(PD4OUT,N2298,N2303,N2414,N2433,N2465);
nor #5 GPD5OUT(PD5OUT,N1874,N1879,N1989,N2008,N2040);
nor #5 GPD6OUT(PD6OUT,N1328,N1329,N1398,N1435,N1455,N1536,N1616,N1688);
nor #5 GPD7OUT(PD7OUT,N1036,N1056,N1087,N1126,N1188,N900,N922,N926);
nor #5 GPDOEA(PDOEA,DACK,PNWDS);
nor #5 GPDOEB(PDOEB,PCS,PNRDS);
nor #5 GPIRQ(PIRQ,N3134,N3156);
nor #5 GPNMI(PNMI,N1332);
nor #5 GPRST(PRST,N1433,N332);
nor #5 inv_HD0IN(_HD0IN,HD0IN);
nor #5 inv_HD1IN(_HD1IN,HD1IN);
nor #5 inv_HD2IN(_HD2IN,HD2IN);
nor #5 inv_HD3IN(_HD3IN,HD3IN);
nor #5 inv_HD4IN(_HD4IN,HD4IN);
nor #5 inv_HD5IN(_HD5IN,HD5IN);
nor #5 inv_HD6IN(_HD6IN,HD6IN);
nor #5 inv_HD7IN(_HD7IN,HD7IN);
nor #5 nor_hdoe(HDOE,HDOEA);
nor #5 nor_pdoe(PDOE,PDOEA,PDOEB);
endmodule
|
//---------------------------------------------------------------------
//
// Company: UNSW
// Original Author: Lingkan Gong
// Project Name: State_Migration
//
// Create Date: 12/06/2010
// Design Name: icapi_regs
//
//---------------------------------------------------------------------
`timescale 1ns/1ns
module icapi_regs # (
parameter C_DWIDTH = 128,
parameter C_MEM_BASEADDR = 'hffffffff,
parameter C_MEM_HIGHADDR = 'h00000000
)
(
input Bus2IP_Clk,
input Bus2IP_Reset,
input [31:0] Bus2IP_Addr,
input Bus2IP_CS,
input Bus2IP_RNW,
input [C_DWIDTH-1:0] Bus2IP_Data,
input [C_DWIDTH/8-1:0] Bus2IP_BE,
input Bus2IP_Burst,
input [8:0] Bus2IP_BurstLength,
input Bus2IP_RdReq,
input Bus2IP_WrReq,
output reg IP2Bus_AddrAck,
output [C_DWIDTH-1:0] IP2Bus_Data,
output reg IP2Bus_RdAck,
output reg IP2Bus_WrAck,
output IP2Bus_Error,
output soft_reset,
output rc_start,
output rc_bop,
output [31:0] rc_baddr,
output [31:0] rc_bsize,
input rc_done,
output IP2INTC_Irpt
);
`define ICAPI_OP_RdCfg 'h0
`define ICAPI_OP_WrCfg 'h1
`define ICAPI_IS_BUSY 'h0
`define ICAPI_IS_DONE 'h1
`define ICAPI_IS_ERROR 'h3
reg [31:0] m_ctrl;
reg [31:0] m_stat;
reg [31:0] m_bitstream_addr; // Bitstream Address in bytes
reg [31:0] m_bitstream_size; // Bitstream Size in bytes
reg [31:0] m_ier;
reg [31:0] read_data; // MSB 32bit of IP2Bus_Data
wire [31:0] written_data; // MSB 32bit of Bus2IP_Data
// WAR: For 128bit, the valid data does not always appear on MSB
// In fact, the valid bit position is defined by BE
// So the following code actually only support 32bit DWidth
generate begin if (C_DWIDTH>32)
assign IP2Bus_Data[C_DWIDTH-32-1:0] = {C_DWIDTH-32{1'b0}};
end endgenerate
assign IP2Bus_Data[C_DWIDTH-1:C_DWIDTH-32] = read_data;
assign written_data = Bus2IP_Data[C_DWIDTH-1:C_DWIDTH-32];
//-------------------------------------------------------------------
// Read Regs
//-------------------------------------------------------------------
always @(posedge Bus2IP_Clk or posedge Bus2IP_Reset) begin
if (Bus2IP_Reset) begin
IP2Bus_AddrAck <= 1'b0;
IP2Bus_RdAck <= 1'b0;
IP2Bus_WrAck <= 1'b0;
end else begin
IP2Bus_AddrAck <= (Bus2IP_RdReq || Bus2IP_WrReq);
IP2Bus_RdAck <= Bus2IP_RdReq;
IP2Bus_WrAck <= Bus2IP_WrReq;
end
end
always @(posedge Bus2IP_Clk or posedge Bus2IP_Reset) begin
if (Bus2IP_Reset) begin
read_data <= 32'h0;
end else begin
if (Bus2IP_RdReq) begin
case (Bus2IP_Addr-C_MEM_BASEADDR)
16'h0: begin read_data <= m_ctrl ; end
16'h4: begin read_data <= m_stat ; end
16'h8: begin read_data <= m_bitstream_addr ; end
16'hc: begin read_data <= m_bitstream_size ; end
16'h10: begin read_data <= m_ier ; end
default: begin end
endcase
end
end
end
assign IP2Bus_Error = 1'b0;
// TODO: assert BE == 0xffff ....
// TODO: assert Address == %4 ....
// TODO: assert Type == SINGLE_BEAT
//-------------------------------------------------------------------
// m_bitstream_addr
// m_bitstream_size
// m_ier
//-------------------------------------------------------------------
always @(posedge Bus2IP_Clk or posedge Bus2IP_Reset) begin
if (Bus2IP_Reset) begin
m_bitstream_addr <= 32'h0;
m_bitstream_size <= 32'h0;
m_ier <= 32'h0;
end else begin
if (Bus2IP_WrReq) begin
case (Bus2IP_Addr-C_MEM_BASEADDR)
16'h8: begin m_bitstream_addr <= written_data; end
16'hc: begin m_bitstream_size <= written_data; end
16'h10: begin m_ier <= written_data; end
default: begin end
endcase
end
end
end
assign rc_baddr = m_bitstream_addr >> 2; // rc_baddr: Bitstream Size in WORDS
assign rc_bsize = m_bitstream_size >> 2; // rc_bsize: Bitstream Size in WORDS
//-------------------------------------------------------------------
// m_ctrl
//-------------------------------------------------------------------
always @(posedge Bus2IP_Clk or posedge Bus2IP_Reset) begin
if (Bus2IP_Reset) begin
m_ctrl <= 32'h0;
end else begin
if ((Bus2IP_WrReq) && ((Bus2IP_Addr-C_MEM_BASEADDR)==32'h0)) begin
if (written_data[31]) begin // TODO: Soft Reset
m_ctrl[31] <= 1'b1;
m_ctrl[30:0] <= 'h0;
end else if (m_stat!=`ICAPI_IS_BUSY) begin
m_ctrl <= written_data;
end
end else begin
m_ctrl[31] <= 1'b0; // ICAPI_RESET only last one cycle
m_ctrl[0] <= 1'b0; // ICAPI_START only last one cycle
end
end
end
assign soft_reset = m_ctrl[31];// ICAPI_RESET == 1
assign rc_bop = m_ctrl[1]; // ICAPI_OP
assign rc_start = m_ctrl[0]; // ICAPI_START == 1: Start ICAPI && Clear m_stat
//-------------------------------------------------------------------
// m_stat
// IP2INTC_Irpt
//-------------------------------------------------------------------
always @(posedge Bus2IP_Clk or posedge Bus2IP_Reset) begin
if (Bus2IP_Reset) begin
m_stat <= `ICAPI_IS_DONE;
end else begin
if (rc_start) m_stat <= `ICAPI_IS_BUSY; // NOTE: One cycle later than rc_start
else if (rc_done) m_stat <= `ICAPI_IS_DONE; // NOTE: One cycle later than rc_done
end
end
assign IP2INTC_Irpt = ((m_stat == `ICAPI_IS_DONE) && m_ier[31]); // SIGIS = INTERRUPT, SENSITIVITY = LEVEL_HIGH
endmodule
|
`timescale 1ns / 1ps
`define PHASE 20 // 20ns per phase, 40ns per cycle, 25MHz
module PolarisCPU(
// MISC DIAGNOSTICS
output fence_o,
output trap_o,
output [3:0] cause_o,
output [63:0] mepc_o,
output mpie_o,
output mie_o,
input irq_i,
// I MASTER
input iack_i,
input [31:0] idat_i,
output [63:0] iadr_o,
output istb_o,
// D MASTER
input dack_i,
input [63:0] ddat_i,
output [63:0] ddat_o,
output [63:0] dadr_o,
output dwe_o,
output dcyc_o,
output dstb_o,
output [1:0] dsiz_o,
output dsigned_o,
// CSR ACCESS
output [11:0] cadr_o,
output coe_o,
output cwe_o,
input cvalid_i,
output [63:0] cdat_o,
input [63:0] cdat_i,
// SYSCON
input clk_i,
input reset_i
);
// Sequencer outputs
wire pc_mbvec, pc_pcPlus4;
wire ft0_o;
wire iadr_pc;
wire ir_idat;
// Sequencer inputs
reg ft0;
// Internal working wires and registers
reg rst;
reg [63:0] pc, ia;
wire [63:0] pc_mux, ia_mux;
reg [31:0] ir;
wire [31:0] ir_mux;
reg xt0, xt1, xt2, xt3, xt4;
wire xt0_o, xt1_o, xt2_o, xt3_o, xt4_o;
wire [4:0] ra_mux;
wire ra_ir1, ra_ir2, ra_ird;
wire rdat_alu, rdat_pc;
wire [63:0] rdat_i, rdat_o;
wire rwe_o;
reg [63:0] alua, alub;
wire [63:0] alua_mux, alub_mux;
wire alua_rdat, alua_0, alua_ia;
wire alub_rdat, alub_imm12i, alub_imm12s, alub_imm20u, alub_imm20uj;
wire [63:0] imm12i, imm12s, imm12sb;
wire pc_alu;
wire cflag_i;
wire sum_en;
wire and_en;
wire xor_en;
wire invB_en;
wire lsh_en;
wire rsh_en;
wire ltu_en, lts_en;
wire [63:0] aluResult, aluXResult;
wire cflag_o;
wire vflag_o;
wire zflag_o;
wire [3:0] rmask_i;
wire sx32_en;
wire alua_alua;
wire alub_alub;
wire [63:0] imm20u, imm20uj;
wire ia_pc;
wire dadr_alu;
wire dcyc_1;
wire dstb_1;
wire dsiz_fn3;
wire rdat_ddat;
wire ddat_rdat;
wire [7:0] ccr_mux;
reg [7:0] ccr;
wire ccr_alu;
wire alub_imm12sb;
reg trap;
wire mcause_2, mcause_3, mcause_11;
wire pc_mtvec;
reg [63:0] mepc;
wire [63:0] mepc_mux;
wire mepc_ia;
wire pc_mepc;
wire mie, mpie;
wire mie_0, mie_mpie;
wire mpie_mie, mpie_1;
wire rdat_cdat, cdat_rdat;
wire coe_1, cwe_1;
wire cdat_imm5;
wire cdat_alu;
wire alub_imm5;
wire alua_cdat;
wire icvalid_i;
wire [63:0] icdat_i;
wire [63:0] mtvec_i;
wire take_irq;
wire mepc_pc;
wire mcause_irq_o;
wire cvalid = icvalid_i | cvalid_i;
wire [63:0] ucdat_i = icdat_i | cdat_i;
wire rdNotZero = |ir[11:7];
wire r1NotZero = |ir[19:15];
wire [63:0] imm5 = {59'b0, ir[19:15]};
assign coe_o = coe_1 & rdNotZero;
assign cwe_o = cwe_1 & r1NotZero;
assign cadr_o = ir[31:20];
assign cdat_o = (cdat_rdat ? rdat_o : 0) |
(cdat_alu ? aluXResult : 0) |
(cdat_imm5 ? imm5 : 0);
wire ltFlag = aluXResult[63] ^ vflag_o;
assign ccr_mux = ccr_alu ? {cflag_o, ~cflag_o, ~ltFlag, ltFlag, 2'b00, ~zflag_o, zflag_o} : ccr;
assign dsigned_o = dsiz_fn3 & ~ir[14];
assign dsiz_o = dsiz_fn3 ? ir[13:12] : 2'b00;
assign dcyc_o = dcyc_1;
assign dstb_o = dstb_1;
assign dadr_o = (dadr_alu ? aluXResult : 64'd0);
assign ddat_o = (ddat_rdat ? rdat_o : 0);
assign aluXResult = (sx32_en ? {{32{aluResult[31]}}, aluResult[31:0]} : aluResult);
assign imm12i = {{52{ir[31]}}, ir[31:20]};
assign imm12s = {{52{ir[31]}}, ir[31:25], ir[11:7]};
assign imm12sb = {{51{ir[31]}}, ir[31], ir[7], ir[30:25], ir[11:8], 1'b0};
assign imm20u = {{32{ir[31]}}, ir[31:12], 12'd0};
assign imm20uj = {{43{ir[31]}}, ir[31], ir[19:12], ir[20], ir[30:21], 1'b0};
assign alua_alua = ~|{alua_rdat, alua_0, alua_ia, alua_cdat};
assign alub_alub = ~|{alub_rdat, alub_imm12i, alub_imm12s, alub_imm12sb, alub_imm20u, alub_imm20uj, alub_imm5};
assign alua_mux = // ignore alua_0 since that will force alua=0.
(alua_ia ? ia : 0) |
(alua_rdat ? rdat_o : 0) |
(alua_cdat ? ucdat_i : 0) |
(alua_alua ? alua : 0);
assign alub_mux =
(alub_rdat ? rdat_o : 0) |
(alub_imm12i ? imm12i : 0) |
(alub_imm12s ? imm12s : 0) |
(alub_imm12sb ? imm12sb : 0) |
(alub_imm20u ? imm20u : 0) |
(alub_imm20uj ? imm20uj : 0) |
(alub_imm5 ? imm5 : 0) |
(alub_alub ? alub : 0);
assign rdat_i = (rdat_alu ? aluXResult : 0) |
(rdat_ddat ? ddat_i : 0) |
(rdat_cdat ? ucdat_i : 0) |
(rdat_pc ? pc : 0);
assign ra_mux = (ra_ir1 ? ir[19:15] : 0) |
(ra_ir2 ? ir[24:20] : 0) |
(ra_ird ? ir[11:7] : 0); // Defaults to 0
wire pc_pc = ~|{pc_mbvec,pc_pcPlus4,pc_alu,pc_mtvec,pc_mepc};
assign pc_mux = (pc_mbvec ? 64'hFFFF_FFFF_FFFF_FF00 : 64'h0) |
(pc_pcPlus4 ? pc + 4 : 64'h0) |
(pc_alu ? aluXResult : 64'h0) |
(pc_mtvec ? mtvec_i : 64'h0) |
(pc_mepc ? mepc_o : 64'h0) |
(pc_pc ? pc : 64'h0); // base case
wire ia_ia = ~ia_pc;
assign ia_mux = (ia_pc ? pc : 0) |
(ia_ia ? ia : 0);
assign iadr_o = iadr_pc ? pc : 0;
wire ir_ir = ~ir_idat;
assign ir_mux = (ir_idat ? idat_i : 0) |
(ir_ir ? ir : 0); // base case
always @(posedge clk_i) begin
rst <= reset_i;
pc <= pc_mux;
ia <= ia_mux;
ft0 <= ft0_o;
xt0 <= xt0_o;
xt1 <= xt1_o;
xt2 <= xt2_o;
xt3 <= xt3_o;
xt4 <= xt4_o;
ir <= ir_mux;
alua <= alua_mux;
alub <= alub_mux;
ccr <= ccr_mux;
trap <= trap_o;
end
Sequencer s(
.xt0_o(xt0_o),
.xt1_o(xt1_o),
.xt2_o(xt2_o),
.xt3_o(xt3_o),
.xt0(xt0),
.xt1(xt1),
.xt2(xt2),
.xt3(xt3),
.ft0(ft0),
.istb_o(istb_o),
.iadr_pc(iadr_pc),
.iack_i(iack_i),
.pc_mbvec(pc_mbvec),
.pc_pcPlus4(pc_pcPlus4),
.ir_idat(ir_idat),
.ir(ir),
.ft0_o(ft0_o),
.rdat_pc(rdat_pc),
.sum_en(sum_en),
.pc_alu(pc_alu),
.ra_ir1(ra_ir1),
.ra_ir2(ra_ir2),
.ra_ird(ra_ird),
.alua_rdat(alua_rdat),
.alub_rdat(alub_rdat),
.alub_imm12i(alub_imm12i),
.rwe_o(rwe_o),
.rdat_alu(rdat_alu),
.and_en(and_en),
.xor_en(xor_en),
.invB_en(invB_en),
.lsh_en(lsh_en),
.rsh_en(rsh_en),
.cflag_i(cflag_i),
.sx32_en(sx32_en),
.alua_0(alua_0),
.alub_imm20u(alub_imm20u),
.ia_pc(ia_pc),
.alua_ia(alua_ia),
.dadr_alu(dadr_alu),
.dcyc_1(dcyc_1),
.dstb_1(dstb_1),
.dsiz_fn3(dsiz_fn3),
.rdat_ddat(rdat_ddat),
.dack_i(dack_i),
.ddat_rdat(ddat_rdat),
.alub_imm12s(alub_imm12s),
.dwe_o(dwe_o),
.alub_imm20uj(alub_imm20uj),
.ccr_alu(ccr_alu),
.alub_imm12sb(alub_imm12sb),
.xt4_o(xt4_o),
.xt4(xt4),
.ccr(ccr),
.fence_o(fence_o),
.trap_o(trap_o),
.trap(trap),
.mcause_2(mcause_2),
.mcause_3(mcause_3),
.mcause_11(mcause_11),
.pc_mtvec(pc_mtvec),
.mepc_ia(mepc_ia),
.pc_mepc(pc_mepc),
.mpie_mie(mpie_mie),
.mpie_1(mpie_1),
.mie_mpie(mie_mpie),
.mie_0(mie_0),
.csrok_i(cvalid),
.rdat_cdat(rdat_cdat),
.coe_o(coe_1),
.cdat_rdat(cdat_rdat),
.cwe_o(cwe_1),
.cdat_imm5(cdat_imm5),
.cdat_alu(cdat_alu),
.alub_imm5(alub_imm5),
.alua_cdat(alua_cdat),
.take_irq(take_irq),
.mepc_pc(mepc_pc),
.mcause_irq_o(mcause_irq_o),
.ltu_en(ltu_en),
.lts_en(lts_en),
.rst(rst)
);
xrs xrs(
.clk_i(clk_i),
.ra_i(ra_mux),
.rdat_i(rdat_i),
.rdat_o(rdat_o),
.rmask_i({4{rwe_o}})
);
alu alu(
.inA_i(alua),
.inB_i(alub),
.cflag_i(cflag_i),
.sum_en_i(sum_en),
.and_en_i(and_en),
.xor_en_i(xor_en),
.invB_en_i(invB_en),
.lsh_en_i(lsh_en),
.rsh_en_i(rsh_en),
.ltu_en_i(ltu_en),
.lts_en_i(lts_en),
.out_o(aluResult),
.cflag_o(cflag_o),
.vflag_o(vflag_o),
.zflag_o(zflag_o)
);
CSRs csrs(
.cadr_i(cadr_o),
.cvalid_o(icvalid_i),
.cdat_o(icdat_i),
.cdat_i(cdat_o),
.coe_i(coe_o),
.cwe_i(cwe_o),
.mie_0(mie_0),
.mie_mpie(mie_mpie),
.mpie_mie(mpie_mie),
.mpie_1(mpie_1),
.mtvec_o(mtvec_i),
.mepc_o(mepc_o),
.mie_o(mie_o),
.mpie_o(mpie_o),
.ft0_i(ft0),
.tick_i(1'b0), // for now
.mcause_2(mcause_2),
.mcause_3(mcause_3),
.mcause_11(mcause_11),
.mepc_ia(mepc_ia),
.mepc_pc(mepc_pc),
.ia_i(ia),
.pc_i(pc),
.cause_o(cause_o),
.irq_i(irq_i),
.take_irq_o(take_irq),
.mcause_irq_i(mcause_irq_o),
.reset_i(reset_i),
.clk_i(clk_i)
);
endmodule
module CSRs(
input [11:0] cadr_i,
output cvalid_o,
output [63:0] cdat_o,
input [63:0] cdat_i,
input coe_i,
input cwe_i,
input mie_0,
input mie_mpie,
input mpie_mie,
input mpie_1,
output [63:0] mtvec_o,
output [63:0] mepc_o,
output [3:0] cause_o,
input [63:0] ia_i,
input [63:0] pc_i,
output mie_o,
output mpie_o,
input ft0_i,
input tick_i,
input mcause_2,
input mcause_3,
input mcause_11,
input mcause_irq_i,
input mepc_ia,
input mepc_pc,
input irq_i,
output take_irq_o,
input reset_i,
input clk_i
);
reg mpie, mie;
reg [63:0] mtvec;
reg [63:0] mscratch;
reg [63:0] mepc;
reg [4:0] mcause; // Compacted; bit 4 here maps to bit 63 in software
reg [63:0] mbadaddr;
reg [63:0] mcycle;
reg [63:0] mtime;
reg [63:0] minstret;
reg irqEn;
wire mpie_mux, mie_mux;
wire [63:0] mtvec_mux;
wire [63:0] mscratch_mux;
wire [63:0] mepc_mux;
wire [4:0] mcause_mux;
wire [63:0] mbadaddr_mux;
wire [63:0] mcycle_mux;
wire [63:0] mtime_mux;
wire [63:0] minstret_mux;
assign mtvec_o = mtvec;
assign mepc_o = mepc;
wire csrv_misa = (cadr_i == 12'hF10);
wire csrv_mvendorid = (cadr_i == 12'hF11);
wire csrv_marchid = (cadr_i == 12'hF12);
wire csrv_mimpid = (cadr_i == 12'hF13);
wire csrv_mhartid = (cadr_i == 12'hF14);
wire csrv_mstatus = (cadr_i == 12'h300);
wire csrv_medeleg = (cadr_i == 12'h302);
wire csrv_mideleg = (cadr_i == 12'h303);
wire csrv_mie = (cadr_i == 12'h304);
wire csrv_mtvec = (cadr_i == 12'h305);
wire csrv_mscratch = (cadr_i == 12'h340);
wire csrv_mepc = (cadr_i == 12'h341);
wire csrv_mcause = (cadr_i == 12'h342);
wire csrv_mbadaddr = (cadr_i == 12'h343);
wire csrv_mip = (cadr_i == 12'h344);
wire csrv_mcycle = (cadr_i == 12'hF00);
wire csrv_mtime = (cadr_i == 12'hF01);
wire csrv_minstret = (cadr_i == 12'hF02);
assign cvalid_o = |{
csrv_misa, csrv_mvendorid, csrv_marchid,
csrv_mimpid, csrv_mhartid, csrv_mstatus,
csrv_medeleg, csrv_mideleg, csrv_mie,
csrv_mtvec, csrv_mscratch, csrv_mepc,
csrv_mcause, csrv_mbadaddr, csrv_mip,
csrv_mcycle, csrv_mtime, csrv_minstret
};
wire [63:0] csrd_misa = {2'b10, 36'd0, 26'b00000001000000000100000000};
wire [63:0] csrd_mvendorid = 64'd0;
wire [63:0] csrd_marchid = 64'd0;
wire [63:0] csrd_mimpid = 64'h1161008010000000;
wire [63:0] csrd_mhartid = 64'd0;
wire [63:0] csrd_mstatus = {
1'b0, // SD
34'd0, // reserved
5'b00000, // VM
4'b0000, // reserved
3'b000, // MXR, PUM, MPRV
2'b00, // XS
2'b00, // FS
2'b11, // MPP
2'b10, // HPP
1'b1, // SPP
mpie, 3'b000,
mie, 3'b000
};
wire [63:0] csrd_medeleg = 64'd0;
wire [63:0] csrd_mideleg = 64'd0;
wire [63:0] csrd_mie = {
52'd0,
irqEn,
11'd0
};
wire [63:0] csrd_mtvec = mtvec;
wire [63:0] csrd_mscratch = mscratch;
wire [63:0] csrd_mepc = mepc;
wire [63:0] csrd_mcause = {
mcause[4],
59'd0, // reserved
mcause[3:0]
};
wire [63:0] csrd_mbadaddr = mbadaddr;
wire [63:0] csrd_mip = {
52'd0,
irq_i,
11'd0
};
wire [63:0] csrd_mcycle = mcycle;
wire [63:0] csrd_mtime = mtime;
wire [63:0] csrd_minstret = minstret;
assign take_irq_o = mie & irqEn & irq_i;
assign cdat_o =
(csrv_misa ? csrd_misa : 0) |
(csrv_mvendorid ? csrd_mvendorid : 0) |
(csrv_marchid ? csrd_marchid : 0) |
(csrv_mimpid ? csrd_mimpid : 0) |
(csrv_mhartid ? csrd_mhartid : 0) |
(csrv_mstatus ? csrd_mstatus : 0) |
(csrv_medeleg ? csrd_medeleg : 0) |
(csrv_mideleg ? csrd_mideleg : 0) |
(csrv_mie ? csrd_mie : 0) |
(csrv_mtvec ? csrd_mtvec : 0) |
(csrv_mscratch ? csrd_mscratch : 0) |
(csrv_mepc ? csrd_mepc : 0) |
(csrv_mcause ? csrd_mcause : 0) |
(csrv_mbadaddr ? csrd_mbadaddr : 0) |
(csrv_mip ? csrd_mip : 0) |
(csrv_mcycle ? csrd_mcycle : 0) |
(csrv_mtime ? csrd_mtime : 0) |
(csrv_minstret ? csrd_minstret : 0);
wire irqEn_cdat = csrv_mie & cwe_i;
wire irqEn_irqEn = ~|{irqEn_cdat, reset_i};
wire irqEn_mux =
(irqEn_cdat ? cdat_i[11] : 0) |
(irqEn_irqEn ? irqEn : 0);
wire mstatus_we = csrv_mstatus & cwe_i;
wire mie_mie = ~|{mie_0, mie_mpie, mstatus_we};
assign mie_mux =
(mie_0 ? 0 : 0) |
(mie_mpie ? mpie : 0) |
(mstatus_we ? cdat_i[3] : 0) |
(mie_mie ? mie : 0);
wire mpie_mpie = ~|{mpie_mie, mpie_1, mstatus_we};
assign mpie_mux =
(mpie_mie ? mie : 0) |
(mpie_1 ? 1 : 0) |
(mstatus_we ? cdat_i[7] : 0) |
(mpie_mpie ? mpie : 0);
assign mie_o = mie;
assign mpie_o = mpie;
wire mtvec_we = csrv_mtvec & cwe_i;
wire mtvec_mtvec = ~|{mtvec_we, reset_i};
assign mtvec_mux =
(mtvec_we ? cdat_i : 0) |
(reset_i ? 64'hFFFF_FFFF_FFFF_FE00 : 0) |
(mtvec_mtvec ? mtvec : 0);
wire mscratch_we = csrv_mscratch & cwe_i;
assign mscratch_mux = (mscratch_we ? cdat_i : mscratch);
wire mepc_we = csrv_mepc & cwe_i;
wire mepc_mepc = ~|{mepc_we, mepc_ia, mepc_pc};
assign mepc_mux =
(mepc_we ? cdat_i : 0) |
(mepc_ia ? ia_i : 0) |
(mepc_pc ? pc_i : 0) |
(mepc_mepc ? mepc : 0);
wire mcause_we = csrv_mcause & cwe_i;
wire mcause_mcause = ~|{mcause_2, mcause_3, mcause_11, mcause_we};
assign cause_o = mcause_mux[3:0];
assign mcause_mux =
(mcause_we ? {cdat_i[63], cdat_i[3:0]} : 0) |
(mcause_2 ? {mcause_irq_i, 4'd2} : 0) |
(mcause_3 ? {mcause_irq_i, 4'd3} : 0) |
(mcause_11 ? {mcause_irq_i, 4'd11} : 0) |
(mcause_mcause ? mcause : 0);
wire mbadaddr_we = csrv_mbadaddr & cwe_i;
assign mbadaddr_mux = (mbadaddr_we ? cdat_i : mbadaddr);
assign mcycle_mux = (~reset_i ? mcycle + 1 : 0);
assign minstret_mux =
(~reset_i & ft0_i ? minstret + 1 : 0) |
(~reset_i & ~ft0_i ? minstret : 0);
assign mtime_mux =
(~reset_i & tick_i ? mtime + 1 : 0) |
(~reset_i & ~tick_i ? mtime : 0);
always @(posedge clk_i) begin
mie <= mie_mux;
mpie <= mpie_mux;
mtvec <= mtvec_mux;
mscratch <= mscratch_mux;
mepc <= mepc_mux;
mcause <= mcause_mux;
mbadaddr <= mbadaddr_mux;
mcycle <= mcycle_mux;
minstret <= minstret_mux;
mtime <= mtime_mux;
irqEn <= irqEn_mux;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t_case_huge_sub3 (/*AUTOARG*/
// Outputs
outr,
// Inputs
clk, index
);
input clk;
input [9:0] index;
output [3:0] outr;
// =============================
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg [3:0] outr;
// End of automatics
// =============================
// Created from perl
//for $i (0..255) { $r=rand(4); printf "\t8'h%02x: begin outr <= outr^index[8:5]^4'h%01x; end\n", $i,
//rand(256); };
// Reset cheating
initial outr = 4'b0;
always @(posedge clk) begin
case (index[7:0])
8'h00: begin outr <= 4'h0; end
8'h01: begin /*No Change*/ end
8'h02: begin outr <= outr^index[8:5]^4'ha; end
8'h03: begin outr <= outr^index[8:5]^4'h4; end
8'h04: begin outr <= outr^index[8:5]^4'hd; end
8'h05: begin outr <= outr^index[8:5]^4'h1; end
8'h06: begin outr <= outr^index[8:5]^4'hf; end
8'h07: begin outr <= outr^index[8:5]^4'he; end
8'h08: begin outr <= outr^index[8:5]^4'h0; end
8'h09: begin outr <= outr^index[8:5]^4'h4; end
8'h0a: begin outr <= outr^index[8:5]^4'h5; end
8'h0b: begin outr <= outr^index[8:5]^4'ha; end
8'h0c: begin outr <= outr^index[8:5]^4'h2; end
8'h0d: begin outr <= outr^index[8:5]^4'hf; end
8'h0e: begin outr <= outr^index[8:5]^4'h5; end
8'h0f: begin outr <= outr^index[8:5]^4'h0; end
8'h10: begin outr <= outr^index[8:5]^4'h3; end
8'h11: begin outr <= outr^index[8:5]^4'hb; end
8'h12: begin outr <= outr^index[8:5]^4'h0; end
8'h13: begin outr <= outr^index[8:5]^4'hf; end
8'h14: begin outr <= outr^index[8:5]^4'h3; end
8'h15: begin outr <= outr^index[8:5]^4'h5; end
8'h16: begin outr <= outr^index[8:5]^4'h7; end
8'h17: begin outr <= outr^index[8:5]^4'h2; end
8'h18: begin outr <= outr^index[8:5]^4'h3; end
8'h19: begin outr <= outr^index[8:5]^4'hb; end
8'h1a: begin outr <= outr^index[8:5]^4'h5; end
8'h1b: begin outr <= outr^index[8:5]^4'h4; end
8'h1c: begin outr <= outr^index[8:5]^4'h2; end
8'h1d: begin outr <= outr^index[8:5]^4'hf; end
8'h1e: begin outr <= outr^index[8:5]^4'h0; end
8'h1f: begin outr <= outr^index[8:5]^4'h4; end
8'h20: begin outr <= outr^index[8:5]^4'h6; end
8'h21: begin outr <= outr^index[8:5]^4'ha; end
8'h22: begin outr <= outr^index[8:5]^4'h6; end
8'h23: begin outr <= outr^index[8:5]^4'hb; end
8'h24: begin outr <= outr^index[8:5]^4'ha; end
8'h25: begin outr <= outr^index[8:5]^4'he; end
8'h26: begin outr <= outr^index[8:5]^4'h7; end
8'h27: begin outr <= outr^index[8:5]^4'ha; end
8'h28: begin outr <= outr^index[8:5]^4'h3; end
8'h29: begin outr <= outr^index[8:5]^4'h8; end
8'h2a: begin outr <= outr^index[8:5]^4'h1; end
8'h2b: begin outr <= outr^index[8:5]^4'h8; end
8'h2c: begin outr <= outr^index[8:5]^4'h4; end
8'h2d: begin outr <= outr^index[8:5]^4'h4; end
8'h2e: begin outr <= outr^index[8:5]^4'he; end
8'h2f: begin outr <= outr^index[8:5]^4'h8; end
8'h30: begin outr <= outr^index[8:5]^4'ha; end
8'h31: begin outr <= outr^index[8:5]^4'h7; end
8'h32: begin outr <= outr^index[8:5]^4'h0; end
8'h33: begin outr <= outr^index[8:5]^4'h3; end
8'h34: begin outr <= outr^index[8:5]^4'h1; end
8'h35: begin outr <= outr^index[8:5]^4'h3; end
8'h36: begin outr <= outr^index[8:5]^4'h4; end
8'h37: begin outr <= outr^index[8:5]^4'h6; end
8'h38: begin outr <= outr^index[8:5]^4'h4; end
8'h39: begin outr <= outr^index[8:5]^4'hb; end
8'h3a: begin outr <= outr^index[8:5]^4'h7; end
8'h3b: begin outr <= outr^index[8:5]^4'h1; end
8'h3c: begin outr <= outr^index[8:5]^4'h2; end
8'h3d: begin outr <= outr^index[8:5]^4'h0; end
8'h3e: begin outr <= outr^index[8:5]^4'h2; end
8'h3f: begin outr <= outr^index[8:5]^4'ha; end
8'h40: begin outr <= outr^index[8:5]^4'h7; end
8'h41: begin outr <= outr^index[8:5]^4'h5; end
8'h42: begin outr <= outr^index[8:5]^4'h5; end
8'h43: begin outr <= outr^index[8:5]^4'h4; end
8'h44: begin outr <= outr^index[8:5]^4'h8; end
8'h45: begin outr <= outr^index[8:5]^4'h5; end
8'h46: begin outr <= outr^index[8:5]^4'hf; end
8'h47: begin outr <= outr^index[8:5]^4'h6; end
8'h48: begin outr <= outr^index[8:5]^4'h7; end
8'h49: begin outr <= outr^index[8:5]^4'h4; end
8'h4a: begin outr <= outr^index[8:5]^4'ha; end
8'h4b: begin outr <= outr^index[8:5]^4'hd; end
8'h4c: begin outr <= outr^index[8:5]^4'hb; end
8'h4d: begin outr <= outr^index[8:5]^4'hf; end
8'h4e: begin outr <= outr^index[8:5]^4'hd; end
8'h4f: begin outr <= outr^index[8:5]^4'h7; end
8'h50: begin outr <= outr^index[8:5]^4'h9; end
8'h51: begin outr <= outr^index[8:5]^4'ha; end
8'h52: begin outr <= outr^index[8:5]^4'hf; end
8'h53: begin outr <= outr^index[8:5]^4'h3; end
8'h54: begin outr <= outr^index[8:5]^4'h1; end
8'h55: begin outr <= outr^index[8:5]^4'h0; end
8'h56: begin outr <= outr^index[8:5]^4'h2; end
8'h57: begin outr <= outr^index[8:5]^4'h9; end
8'h58: begin outr <= outr^index[8:5]^4'h2; end
8'h59: begin outr <= outr^index[8:5]^4'h4; end
8'h5a: begin outr <= outr^index[8:5]^4'hc; end
8'h5b: begin outr <= outr^index[8:5]^4'hd; end
8'h5c: begin outr <= outr^index[8:5]^4'h3; end
8'h5d: begin outr <= outr^index[8:5]^4'hb; end
8'h5e: begin outr <= outr^index[8:5]^4'hd; end
8'h5f: begin outr <= outr^index[8:5]^4'h7; end
8'h60: begin outr <= outr^index[8:5]^4'h7; end
8'h61: begin outr <= outr^index[8:5]^4'h3; end
8'h62: begin outr <= outr^index[8:5]^4'h3; end
8'h63: begin outr <= outr^index[8:5]^4'hb; end
8'h64: begin outr <= outr^index[8:5]^4'h9; end
8'h65: begin outr <= outr^index[8:5]^4'h4; end
8'h66: begin outr <= outr^index[8:5]^4'h3; end
8'h67: begin outr <= outr^index[8:5]^4'h6; end
8'h68: begin outr <= outr^index[8:5]^4'h7; end
8'h69: begin outr <= outr^index[8:5]^4'h7; end
8'h6a: begin outr <= outr^index[8:5]^4'hf; end
8'h6b: begin outr <= outr^index[8:5]^4'h6; end
8'h6c: begin outr <= outr^index[8:5]^4'h8; end
8'h6d: begin outr <= outr^index[8:5]^4'he; end
8'h6e: begin outr <= outr^index[8:5]^4'h4; end
8'h6f: begin outr <= outr^index[8:5]^4'h6; end
8'h70: begin outr <= outr^index[8:5]^4'hc; end
8'h71: begin outr <= outr^index[8:5]^4'h9; end
8'h72: begin outr <= outr^index[8:5]^4'h5; end
8'h73: begin outr <= outr^index[8:5]^4'ha; end
8'h74: begin outr <= outr^index[8:5]^4'h7; end
8'h75: begin outr <= outr^index[8:5]^4'h0; end
8'h76: begin outr <= outr^index[8:5]^4'h1; end
8'h77: begin outr <= outr^index[8:5]^4'he; end
8'h78: begin outr <= outr^index[8:5]^4'ha; end
8'h79: begin outr <= outr^index[8:5]^4'h7; end
8'h7a: begin outr <= outr^index[8:5]^4'hf; end
8'h7b: begin outr <= outr^index[8:5]^4'he; end
8'h7c: begin outr <= outr^index[8:5]^4'h6; end
8'h7d: begin outr <= outr^index[8:5]^4'hc; end
8'h7e: begin outr <= outr^index[8:5]^4'hc; end
8'h7f: begin outr <= outr^index[8:5]^4'h0; end
8'h80: begin outr <= outr^index[8:5]^4'h0; end
8'h81: begin outr <= outr^index[8:5]^4'hd; end
8'h82: begin outr <= outr^index[8:5]^4'hb; end
8'h83: begin outr <= outr^index[8:5]^4'hc; end
8'h84: begin outr <= outr^index[8:5]^4'h2; end
8'h85: begin outr <= outr^index[8:5]^4'h8; end
8'h86: begin outr <= outr^index[8:5]^4'h3; end
8'h87: begin outr <= outr^index[8:5]^4'ha; end
8'h88: begin outr <= outr^index[8:5]^4'he; end
8'h89: begin outr <= outr^index[8:5]^4'h9; end
8'h8a: begin outr <= outr^index[8:5]^4'h1; end
8'h8b: begin outr <= outr^index[8:5]^4'h1; end
8'h8c: begin outr <= outr^index[8:5]^4'hc; end
8'h8d: begin outr <= outr^index[8:5]^4'h2; end
8'h8e: begin outr <= outr^index[8:5]^4'h2; end
8'h8f: begin outr <= outr^index[8:5]^4'hd; end
8'h90: begin outr <= outr^index[8:5]^4'h0; end
8'h91: begin outr <= outr^index[8:5]^4'h6; end
8'h92: begin outr <= outr^index[8:5]^4'h7; end
8'h93: begin outr <= outr^index[8:5]^4'hc; end
8'h94: begin outr <= outr^index[8:5]^4'hb; end
8'h95: begin outr <= outr^index[8:5]^4'h3; end
8'h96: begin outr <= outr^index[8:5]^4'h0; end
8'h97: begin outr <= outr^index[8:5]^4'hc; end
8'h98: begin outr <= outr^index[8:5]^4'hc; end
8'h99: begin outr <= outr^index[8:5]^4'hb; end
8'h9a: begin outr <= outr^index[8:5]^4'h6; end
8'h9b: begin outr <= outr^index[8:5]^4'h5; end
8'h9c: begin outr <= outr^index[8:5]^4'h5; end
8'h9d: begin outr <= outr^index[8:5]^4'h4; end
8'h9e: begin outr <= outr^index[8:5]^4'h7; end
8'h9f: begin outr <= outr^index[8:5]^4'he; end
8'ha0: begin outr <= outr^index[8:5]^4'hc; end
8'ha1: begin outr <= outr^index[8:5]^4'hc; end
8'ha2: begin outr <= outr^index[8:5]^4'h0; end
8'ha3: begin outr <= outr^index[8:5]^4'h1; end
8'ha4: begin outr <= outr^index[8:5]^4'hd; end
8'ha5: begin outr <= outr^index[8:5]^4'h3; end
8'ha6: begin outr <= outr^index[8:5]^4'hc; end
8'ha7: begin outr <= outr^index[8:5]^4'h2; end
8'ha8: begin outr <= outr^index[8:5]^4'h3; end
8'ha9: begin outr <= outr^index[8:5]^4'hd; end
8'haa: begin outr <= outr^index[8:5]^4'h5; end
8'hab: begin outr <= outr^index[8:5]^4'hb; end
8'hac: begin outr <= outr^index[8:5]^4'he; end
8'had: begin outr <= outr^index[8:5]^4'h0; end
8'hae: begin outr <= outr^index[8:5]^4'hf; end
8'haf: begin outr <= outr^index[8:5]^4'h9; end
8'hb0: begin outr <= outr^index[8:5]^4'hf; end
8'hb1: begin outr <= outr^index[8:5]^4'h7; end
8'hb2: begin outr <= outr^index[8:5]^4'h9; end
8'hb3: begin outr <= outr^index[8:5]^4'hf; end
8'hb4: begin outr <= outr^index[8:5]^4'he; end
8'hb5: begin outr <= outr^index[8:5]^4'h3; end
8'hb6: begin outr <= outr^index[8:5]^4'he; end
8'hb7: begin outr <= outr^index[8:5]^4'h8; end
8'hb8: begin outr <= outr^index[8:5]^4'hf; end
8'hb9: begin outr <= outr^index[8:5]^4'hd; end
8'hba: begin outr <= outr^index[8:5]^4'h3; end
8'hbb: begin outr <= outr^index[8:5]^4'h5; end
8'hbc: begin outr <= outr^index[8:5]^4'hd; end
8'hbd: begin outr <= outr^index[8:5]^4'ha; end
8'hbe: begin outr <= outr^index[8:5]^4'h7; end
8'hbf: begin outr <= outr^index[8:5]^4'he; end
8'hc0: begin outr <= outr^index[8:5]^4'h2; end
8'hc1: begin outr <= outr^index[8:5]^4'he; end
8'hc2: begin outr <= outr^index[8:5]^4'h9; end
8'hc3: begin outr <= outr^index[8:5]^4'hb; end
8'hc4: begin outr <= outr^index[8:5]^4'h0; end
8'hc5: begin outr <= outr^index[8:5]^4'h5; end
8'hc6: begin outr <= outr^index[8:5]^4'h9; end
8'hc7: begin outr <= outr^index[8:5]^4'h6; end
8'hc8: begin outr <= outr^index[8:5]^4'ha; end
8'hc9: begin outr <= outr^index[8:5]^4'hf; end
8'hca: begin outr <= outr^index[8:5]^4'h3; end
8'hcb: begin outr <= outr^index[8:5]^4'hb; end
8'hcc: begin outr <= outr^index[8:5]^4'he; end
8'hcd: begin outr <= outr^index[8:5]^4'h2; end
8'hce: begin outr <= outr^index[8:5]^4'h5; end
8'hcf: begin outr <= outr^index[8:5]^4'hf; end
8'hd0: begin outr <= outr^index[8:5]^4'h2; end
8'hd1: begin outr <= outr^index[8:5]^4'h9; end
8'hd2: begin outr <= outr^index[8:5]^4'hb; end
8'hd3: begin outr <= outr^index[8:5]^4'h8; end
8'hd4: begin outr <= outr^index[8:5]^4'h0; end
8'hd5: begin outr <= outr^index[8:5]^4'h2; end
8'hd6: begin outr <= outr^index[8:5]^4'hb; end
8'hd7: begin outr <= outr^index[8:5]^4'h2; end
8'hd8: begin outr <= outr^index[8:5]^4'ha; end
8'hd9: begin outr <= outr^index[8:5]^4'hf; end
8'hda: begin outr <= outr^index[8:5]^4'h8; end
8'hdb: begin outr <= outr^index[8:5]^4'h4; end
8'hdc: begin outr <= outr^index[8:5]^4'he; end
8'hdd: begin outr <= outr^index[8:5]^4'h6; end
8'hde: begin outr <= outr^index[8:5]^4'h9; end
8'hdf: begin outr <= outr^index[8:5]^4'h9; end
8'he0: begin outr <= outr^index[8:5]^4'h7; end
8'he1: begin outr <= outr^index[8:5]^4'h0; end
8'he2: begin outr <= outr^index[8:5]^4'h9; end
8'he3: begin outr <= outr^index[8:5]^4'h3; end
8'he4: begin outr <= outr^index[8:5]^4'h2; end
8'he5: begin outr <= outr^index[8:5]^4'h4; end
8'he6: begin outr <= outr^index[8:5]^4'h5; end
8'he7: begin outr <= outr^index[8:5]^4'h5; end
8'he8: begin outr <= outr^index[8:5]^4'hf; end
8'he9: begin outr <= outr^index[8:5]^4'ha; end
8'hea: begin outr <= outr^index[8:5]^4'hc; end
8'heb: begin outr <= outr^index[8:5]^4'hd; end
8'hec: begin outr <= outr^index[8:5]^4'h1; end
8'hed: begin outr <= outr^index[8:5]^4'h5; end
8'hee: begin outr <= outr^index[8:5]^4'h9; end
8'hef: begin outr <= outr^index[8:5]^4'h0; end
8'hf0: begin outr <= outr^index[8:5]^4'hd; end
8'hf1: begin outr <= outr^index[8:5]^4'hf; end
8'hf2: begin outr <= outr^index[8:5]^4'h4; end
8'hf3: begin outr <= outr^index[8:5]^4'ha; end
8'hf4: begin outr <= outr^index[8:5]^4'h8; end
8'hf5: begin outr <= outr^index[8:5]^4'he; end
8'hf6: begin outr <= outr^index[8:5]^4'he; end
8'hf7: begin outr <= outr^index[8:5]^4'h1; end
8'hf8: begin outr <= outr^index[8:5]^4'h6; end
8'hf9: begin outr <= outr^index[8:5]^4'h0; end
8'hfa: begin outr <= outr^index[8:5]^4'h5; end
8'hfb: begin outr <= outr^index[8:5]^4'h1; end
8'hfc: begin outr <= outr^index[8:5]^4'h8; end
8'hfd: begin outr <= outr^index[8:5]^4'h6; end
8'hfe: begin outr <= outr^index[8:5]^4'h1; end
default: begin outr <= outr^index[8:5]^4'h6; end
endcase
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__INV_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__INV_BEHAVIORAL_PP_V
/**
* inv: Inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__inv (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__INV_BEHAVIORAL_PP_V |
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: pll.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pll (
inclk0,
c0,
c1,
c4,
locked);
input inclk0;
output c0;
output c1;
output c4;
output locked;
wire [4:0] sub_wire0;
wire sub_wire2;
wire [0:0] sub_wire7 = 1'h0;
wire [4:4] sub_wire4 = sub_wire0[4:4];
wire [0:0] sub_wire3 = sub_wire0[0:0];
wire [1:1] sub_wire1 = sub_wire0[1:1];
wire c1 = sub_wire1;
wire locked = sub_wire2;
wire c0 = sub_wire3;
wire c4 = sub_wire4;
wire sub_wire5 = inclk0;
wire [1:0] sub_wire6 = {sub_wire7, sub_wire5};
altpll altpll_component (
.inclk (sub_wire6),
.clk (sub_wire0),
.locked (sub_wire2),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 1,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 2,
altpll_component.clk0_phase_shift = "0",
altpll_component.clk1_divide_by = 1,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 2,
altpll_component.clk1_phase_shift = "-1750",
altpll_component.clk4_divide_by = 4,
altpll_component.clk4_duty_cycle = 50,
altpll_component.clk4_multiply_by = 1,
altpll_component.clk4_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 20000,
altpll_component.intended_device_family = "Cyclone IV E",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_USED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "OFF",
altpll_component.width_clock = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR4 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE4 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "100.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE4 STRING "12.500000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT4 STRING "ps"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK4 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR4 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ4 STRING "12.50000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE4 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT4 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "-63.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT4 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT4 STRING "ps"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK4 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLK4 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA4 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "-1750"
// Retrieval info: CONSTANT: CLK4_DIVIDE_BY NUMERIC "4"
// Retrieval info: CONSTANT: CLK4_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK4_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK4_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: c4 0 0 0 0 OUTPUT_CLK_EXT VCC "c4"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: c4 0 0 0 0 @clk 0 0 1 4
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : bank_state.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// Primary bank state machine. All bank specific timing is generated here.
//
// Conceptually, when a bank machine is assigned a request, conflicts are
// checked. If there is a conflict, then the new request is added
// to the queue for that rank-bank.
//
// Eventually, that request will find itself at the head of the queue for
// its rank-bank. Forthwith, the bank machine will begin arbitration to send an
// activate command to the DRAM. Once arbitration is successful and the
// activate is sent, the row state machine waits the RCD delay. The RAS
// counter is also started when the activate is sent.
//
// Upon completion of the RCD delay, the bank state machine will begin
// arbitration for sending out the column command. Once the column
// command has been sent, the bank state machine waits the RTP latency, and
// if the command is a write, the RAS counter is loaded with the WR latency.
//
// When the RTP counter reaches zero, the pre charge wait state is entered.
// Once the RAS timer reaches zero, arbitration to send a precharge command
// begins.
//
// Upon successful transmission of the precharge command, the bank state
// machine waits the precharge period and then rejoins the idle list.
//
// For an open rank-bank hit, a bank machine passes management of the rank-bank to
// a bank machine that is managing the subsequent request to the same page. A bank
// machine can either be a "passer" or a "passee" in this handoff. There
// are two conditions that have to occur before an open bank can be passed.
// A spatial condition, ie same rank-bank and row address. And a temporal condition,
// ie the passee has completed it work with the bank, but has not issued a precharge.
//
// The spatial condition is signalled by pass_open_bank_ns. The temporal condition
// is when the column command is issued, or when the bank_wait_in_progress
// signal is true. Bank_wait_in_progress is true when the RTP timer is not
// zero, or when the RAS/WR timer is not zero and the state machine is waiting
// to send out a precharge command.
//
// On an open bank pass, the passer transitions from the temporal condition
// noted above and performs the end of request processing and eventually lands
// in the act_wait_r state.
//
// On an open bank pass, the passee lands in the col_wait_r state and waits
// for its chance to send out a column command.
//
// Since there is a single data bus shared by all columns in all ranks, there
// is a single column machine. The column machine is primarily in charge of
// managing the timing on the DQ data bus. It reserves states for data transfer,
// driver turnaround states, and preambles. It also has the ability to add
// additional programmable delay for read to write changeovers. This read to write
// delay is generated in the column machine which inhibits writes via the
// inhbt_wr signal.
//
// There is a rank machine for every rank. The rank machines are responsible
// for enforcing rank specific timing such as FAW, and WTR. RRD is guaranteed
// in the bank machine since it is closely coupled to the operation of the
// bank machine and is timing critical.
//
// Since a bank machine can be working on a request for any rank, all rank machines
// inhibits are input to all bank machines. Based on the rank of the current
// request, each bank machine selects the rank information corresponding
// to the rank of its current request.
//
// Since driver turnaround states and WTR delays are so severe with DDRIII, the
// memory interface has the ability to promote requests that use the same
// driver as the most recent request. There is logic in this block that
// detects when the driver for its request is the same as the driver for
// the most recent request. In such a case, this block will send out special
// "same" request early enough to eliminate dead states when there is no
// driver changeover.
`timescale 1ps/1ps
`define BM_SHARED_BV (ID+nBANK_MACHS-1):(ID+1)
module mig_7series_v1_9_bank_state #
(
parameter TCQ = 100,
parameter ADDR_CMD_MODE = "1T",
parameter BM_CNT_WIDTH = 2,
parameter BURST_MODE = "8",
parameter CWL = 5,
parameter DATA_BUF_ADDR_WIDTH = 8,
parameter DRAM_TYPE = "DDR3",
parameter ECC = "OFF",
parameter ID = 0,
parameter nBANK_MACHS = 4,
parameter nCK_PER_CLK = 2,
parameter nOP_WAIT = 0,
parameter nRAS_CLKS = 10,
parameter nRP = 10,
parameter nRTP = 4,
parameter nRCD = 5,
parameter nWTP_CLKS = 5,
parameter ORDERING = "NORM",
parameter RANKS = 4,
parameter RANK_WIDTH = 4,
parameter RAS_TIMER_WIDTH = 5,
parameter STARVE_LIMIT = 2
)
(/*AUTOARG*/
// Outputs
start_rcd, act_wait_r, rd_half_rmw, ras_timer_ns, end_rtp,
bank_wait_in_progress, start_pre_wait, op_exit_req, pre_wait_r,
allow_auto_pre, precharge_bm_end, demand_act_priority, rts_row,
act_this_rank_r, demand_priority, col_rdy_wr, rts_col, wr_this_rank_r,
rd_this_rank_r, rts_pre, rtc,
// Inputs
clk, rst, bm_end, pass_open_bank_r, sending_row, sending_pre, rcv_open_bank,
sending_col, rd_wr_r, req_wr_r, rd_data_addr, req_data_buf_addr_r,
phy_rddata_valid, rd_rmw, ras_timer_ns_in, rb_hit_busies_r, idle_r,
passing_open_bank, low_idle_cnt_r, op_exit_grant, tail_r,
auto_pre_r, pass_open_bank_ns, req_rank_r, req_rank_r_in,
start_rcd_in, inhbt_act_faw_r, wait_for_maint_r, head_r, sent_row,
demand_act_priority_in, order_q_zero, sent_col, q_has_rd,
q_has_priority, req_priority_r, idle_ns, demand_priority_in, inhbt_rd,
inhbt_wr, dq_busy_data, rnk_config_strobe, rnk_config_valid_r, rnk_config,
rnk_config_kill_rts_col, phy_mc_cmd_full, phy_mc_ctl_full, phy_mc_data_full
);
function integer clogb2 (input integer size); // ceiling logb2
begin
size = size - 1;
for (clogb2=1; size>1; clogb2=clogb2+1)
size = size >> 1;
end
endfunction // clogb2
input clk;
input rst;
// Activate wait state machine.
input bm_end;
reg bm_end_r1;
always @(posedge clk) bm_end_r1 <= #TCQ bm_end;
reg col_wait_r;
input pass_open_bank_r;
input sending_row;
reg act_wait_r_lcl;
input rcv_open_bank;
wire start_rcd_lcl = act_wait_r_lcl && sending_row;
output wire start_rcd;
assign start_rcd = start_rcd_lcl;
wire act_wait_ns = rst ||
((act_wait_r_lcl && ~start_rcd_lcl && ~rcv_open_bank) ||
bm_end_r1 || (pass_open_bank_r && bm_end));
always @(posedge clk) act_wait_r_lcl <= #TCQ act_wait_ns;
output wire act_wait_r;
assign act_wait_r = act_wait_r_lcl;
// RCD timer
//
// When CWL is even, CAS commands are issued on slot 0 and RAS commands are
// issued on slot 1. This implies that the RCD can never expire in the same
// cycle as the RAS (otherwise the CAS for a given transaction would precede
// the RAS). Similarly, this can also cause premature expiration for longer
// RCD. An offset must be added to RCD before translating it to the FPGA clock
// domain. In this mode, CAS are on the first DRAM clock cycle corresponding to
// a given FPGA cycle. In 2:1 mode add 2 to generate this offset aligned to
// the FPGA cycle. Likewise, add 4 to generate an aligned offset in 4:1 mode.
//
// When CWL is odd, RAS commands are issued on slot 0 and CAS commands are
// issued on slot 1. There is a natural 1 cycle seperation between RAS and CAS
// in the DRAM clock domain so the RCD can expire in the same FPGA cycle as the
// RAS command. In 2:1 mode, there are only 2 slots so direct translation
// correctly places the CAS with respect to the corresponding RAS. In 4:1 mode,
// there are two slots after CAS, so 2 is added to shift the timer into the
// next FPGA cycle for cases that can't expire in the current cycle.
//
// In 2T mode, the offset from ROW to COL commands is fixed at 2. In 2:1 mode,
// It is sufficient to translate to the half-rate domain and add the remainder.
// In 4:1 mode, we must translate to the quarter-rate domain and add an
// additional fabric cycle only if the remainder exceeds the fixed offset of 2
localparam nRCD_CLKS =
nCK_PER_CLK == 1 ?
nRCD :
nCK_PER_CLK == 2 ?
ADDR_CMD_MODE == "2T" ?
(nRCD/2) + (nRCD%2) :
CWL % 2 ?
(nRCD/2) :
(nRCD+2) / 2 :
// (nCK_PER_CLK == 4)
ADDR_CMD_MODE == "2T" ?
(nRCD/4) + (nRCD%4 > 2 ? 1 : 0) :
CWL % 2 ?
(nRCD-2 ? (nRCD-2) / 4 + 1 : 1) :
nRCD/4 + 1;
localparam nRCD_CLKS_M2 = (nRCD_CLKS-2 <0) ? 0 : nRCD_CLKS-2;
localparam RCD_TIMER_WIDTH = clogb2(nRCD_CLKS_M2+1);
localparam ZERO = 0;
localparam ONE = 1;
reg [RCD_TIMER_WIDTH-1:0] rcd_timer_r = {RCD_TIMER_WIDTH{1'b0}};
reg end_rcd;
reg rcd_active_r = 1'b0;
generate
if (nRCD_CLKS <= 2) begin : rcd_timer_leq_2
always @(/*AS*/start_rcd_lcl) end_rcd = start_rcd_lcl;
end
else if (nRCD_CLKS > 2) begin : rcd_timer_gt_2
reg [RCD_TIMER_WIDTH-1:0] rcd_timer_ns;
always @(/*AS*/rcd_timer_r or rst or start_rcd_lcl) begin
if (rst) rcd_timer_ns = ZERO[RCD_TIMER_WIDTH-1:0];
else begin
rcd_timer_ns = rcd_timer_r;
if (start_rcd_lcl) rcd_timer_ns = nRCD_CLKS_M2[RCD_TIMER_WIDTH-1:0];
else if (|rcd_timer_r) rcd_timer_ns =
rcd_timer_r - ONE[RCD_TIMER_WIDTH-1:0];
end
end
always @(posedge clk) rcd_timer_r <= #TCQ rcd_timer_ns;
wire end_rcd_ns = (rcd_timer_ns == ONE[RCD_TIMER_WIDTH-1:0]);
always @(posedge clk) end_rcd = end_rcd_ns;
wire rcd_active_ns = |rcd_timer_ns;
always @(posedge clk) rcd_active_r <= #TCQ rcd_active_ns;
end
endgenerate
// Figure out if the read that's completing is for an RMW for
// this bank machine. Delay by a state if CWL != 8 since the
// data is not ready in the RMW buffer for the early write
// data fetch that happens with ECC and CWL != 8.
// Create a state bit indicating we're waiting for the read
// half of the rmw to complete.
input sending_col;
input rd_wr_r;
input req_wr_r;
input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr;
input [DATA_BUF_ADDR_WIDTH-1:0] req_data_buf_addr_r;
input phy_rddata_valid;
input rd_rmw;
reg rmw_rd_done = 1'b0;
reg rd_half_rmw_lcl = 1'b0;
output wire rd_half_rmw;
assign rd_half_rmw = rd_half_rmw_lcl;
reg rmw_wait_r = 1'b0;
generate
if (ECC != "OFF") begin : rmw_on
// Delay phy_rddata_valid and rd_rmw by one cycle to align them
// to req_data_buf_addr_r so that rmw_wait_r clears properly
reg phy_rddata_valid_r;
reg rd_rmw_r;
always @(posedge clk) begin
phy_rddata_valid_r <= #TCQ phy_rddata_valid;
rd_rmw_r <= #TCQ rd_rmw;
end
wire my_rmw_rd_ns = phy_rddata_valid_r && rd_rmw_r &&
(rd_data_addr == req_data_buf_addr_r);
if (CWL == 8) always @(my_rmw_rd_ns) rmw_rd_done = my_rmw_rd_ns;
else always @(posedge clk) rmw_rd_done = #TCQ my_rmw_rd_ns;
always @(/*AS*/rd_wr_r or req_wr_r) rd_half_rmw_lcl = req_wr_r && rd_wr_r;
wire rmw_wait_ns = ~rst &&
((rmw_wait_r && ~rmw_rd_done) || (rd_half_rmw_lcl && sending_col));
always @(posedge clk) rmw_wait_r <= #TCQ rmw_wait_ns;
end
endgenerate
// column wait state machine.
wire col_wait_ns = ~rst && ((col_wait_r && ~sending_col) || end_rcd
|| rcv_open_bank || (rmw_rd_done && rmw_wait_r));
always @(posedge clk) col_wait_r <= #TCQ col_wait_ns;
// Set up various RAS timer parameters, wires, etc.
localparam TWO = 2;
output reg [RAS_TIMER_WIDTH-1:0] ras_timer_ns;
reg [RAS_TIMER_WIDTH-1:0] ras_timer_r;
input [(2*(RAS_TIMER_WIDTH*nBANK_MACHS))-1:0] ras_timer_ns_in;
input [(nBANK_MACHS*2)-1:0] rb_hit_busies_r;
// On a bank pass, select the RAS timer from the passing bank machine.
reg [RAS_TIMER_WIDTH-1:0] passed_ras_timer;
integer i;
always @(/*AS*/ras_timer_ns_in or rb_hit_busies_r) begin
passed_ras_timer = {RAS_TIMER_WIDTH{1'b0}};
for (i=ID+1; i<(ID+nBANK_MACHS); i=i+1)
if (rb_hit_busies_r[i])
passed_ras_timer = ras_timer_ns_in[i*RAS_TIMER_WIDTH+:RAS_TIMER_WIDTH];
end
// RAS and (reused for) WTP timer. When an open bank is passed, this
// timer is passed to the new owner. The existing RAS prevents
// an activate from occuring too early.
wire start_wtp_timer = sending_col && ~rd_wr_r;
input idle_r;
always @(/*AS*/bm_end_r1 or ras_timer_r or rst or start_rcd_lcl
or start_wtp_timer) begin
if (bm_end_r1 || rst) ras_timer_ns = ZERO[RAS_TIMER_WIDTH-1:0];
else begin
ras_timer_ns = ras_timer_r;
if (start_rcd_lcl) ras_timer_ns =
nRAS_CLKS[RAS_TIMER_WIDTH-1:0] - TWO[RAS_TIMER_WIDTH-1:0];
if (start_wtp_timer) ras_timer_ns =
// As the timer is being reused, it is essential to compare
// before new value is loaded.
(ras_timer_r <= (nWTP_CLKS-2)) ? nWTP_CLKS[RAS_TIMER_WIDTH-1:0] - TWO[RAS_TIMER_WIDTH-1:0]
: ras_timer_r - ONE[RAS_TIMER_WIDTH-1:0];
if (|ras_timer_r && ~start_wtp_timer) ras_timer_ns =
ras_timer_r - ONE[RAS_TIMER_WIDTH-1:0];
end
end // always @ (...
wire [RAS_TIMER_WIDTH-1:0] ras_timer_passed_ns = rcv_open_bank
? passed_ras_timer
: ras_timer_ns;
always @(posedge clk) ras_timer_r <= #TCQ ras_timer_passed_ns;
wire ras_timer_zero_ns = (ras_timer_ns == ZERO[RAS_TIMER_WIDTH-1:0]);
reg ras_timer_zero_r;
always @(posedge clk) ras_timer_zero_r <= #TCQ ras_timer_zero_ns;
// RTP timer. Unless 2T mode, add one for 2:1 mode. This accounts for loss of
// one DRAM CK due to column command to row command fixed offset. In 2T mode,
// Add the remainder. In 4:1 mode, the fixed offset is -2. Add 2 unless in 2T
// mode, in which case we add 1 if the remainder exceeds the fixed offset.
localparam nRTP_CLKS = (nCK_PER_CLK == 1)
? nRTP :
(nCK_PER_CLK == 2)
? (nRTP/2) + ((ADDR_CMD_MODE == "2T") ? nRTP%2 : 1) :
(nRTP/4) + ((ADDR_CMD_MODE == "2T") ? (nRTP%4 > 2 ? 2 : 1) : 2);
localparam nRTP_CLKS_M1 = ((nRTP_CLKS-1) <= 0) ? 0 : nRTP_CLKS-1;
localparam RTP_TIMER_WIDTH = clogb2(nRTP_CLKS_M1 + 1);
reg [RTP_TIMER_WIDTH-1:0] rtp_timer_ns;
reg [RTP_TIMER_WIDTH-1:0] rtp_timer_r;
wire sending_col_not_rmw_rd = sending_col && ~rd_half_rmw_lcl;
always @(/*AS*/pass_open_bank_r or rst or rtp_timer_r
or sending_col_not_rmw_rd) begin
rtp_timer_ns = rtp_timer_r;
if (rst || pass_open_bank_r)
rtp_timer_ns = ZERO[RTP_TIMER_WIDTH-1:0];
else begin
if (sending_col_not_rmw_rd)
rtp_timer_ns = nRTP_CLKS_M1[RTP_TIMER_WIDTH-1:0];
if (|rtp_timer_r) rtp_timer_ns = rtp_timer_r - ONE[RTP_TIMER_WIDTH-1:0];
end
end
always @(posedge clk) rtp_timer_r <= #TCQ rtp_timer_ns;
wire end_rtp_lcl = ~pass_open_bank_r &&
((rtp_timer_r == ONE[RTP_TIMER_WIDTH-1:0]) ||
((nRTP_CLKS_M1 == 0) && sending_col_not_rmw_rd));
output wire end_rtp;
assign end_rtp = end_rtp_lcl;
// Optionally implement open page mode timer.
localparam OP_WIDTH = clogb2(nOP_WAIT + 1);
output wire bank_wait_in_progress;
output wire start_pre_wait;
input passing_open_bank;
input low_idle_cnt_r;
output wire op_exit_req;
input op_exit_grant;
input tail_r;
output reg pre_wait_r;
generate
if (nOP_WAIT == 0) begin : op_mode_disabled
assign bank_wait_in_progress = sending_col_not_rmw_rd || |rtp_timer_r ||
(pre_wait_r && ~ras_timer_zero_r);
assign start_pre_wait = end_rtp_lcl;
assign op_exit_req = 1'b0;
end
else begin : op_mode_enabled
reg op_wait_r;
assign bank_wait_in_progress = sending_col || |rtp_timer_r ||
(pre_wait_r && ~ras_timer_zero_r) ||
op_wait_r;
wire op_active = ~rst && ~passing_open_bank && ((end_rtp_lcl && tail_r)
|| op_wait_r);
wire op_wait_ns = ~op_exit_grant && op_active;
always @(posedge clk) op_wait_r <= #TCQ op_wait_ns;
assign start_pre_wait = op_exit_grant ||
(end_rtp_lcl && ~tail_r && ~passing_open_bank);
if (nOP_WAIT == -1)
assign op_exit_req = (low_idle_cnt_r && op_active);
else begin : op_cnt
reg [OP_WIDTH-1:0] op_cnt_r;
wire [OP_WIDTH-1:0] op_cnt_ns =
(passing_open_bank || op_exit_grant || rst)
? ZERO[OP_WIDTH-1:0]
: end_rtp_lcl
? nOP_WAIT[OP_WIDTH-1:0]
: |op_cnt_r
? op_cnt_r - ONE[OP_WIDTH-1:0]
: op_cnt_r;
always @(posedge clk) op_cnt_r <= #TCQ op_cnt_ns;
assign op_exit_req = (low_idle_cnt_r && op_active) ||
(op_wait_r && ~|op_cnt_r);
end
end
endgenerate
output allow_auto_pre;
wire allow_auto_pre = act_wait_r_lcl || rcd_active_r ||
(col_wait_r && ~sending_col);
// precharge wait state machine.
input auto_pre_r;
wire start_pre;
input pass_open_bank_ns;
wire pre_wait_ns = ~rst && (~pass_open_bank_ns &&
(start_pre_wait || (pre_wait_r && ~start_pre)));
always @(posedge clk) pre_wait_r <= #TCQ pre_wait_ns;
wire pre_request = pre_wait_r && ras_timer_zero_r && ~auto_pre_r;
// precharge timer.
localparam nRP_CLKS = (nCK_PER_CLK == 1) ? nRP :
(nCK_PER_CLK == 2) ? ((nRP/2) + (nRP%2)) :
/*(nCK_PER_CLK == 4)*/ ((nRP/4) + ((nRP%4) ? 1 : 0));
// Subtract two because there are a minimum of two fabric states from
// end of RP timer until earliest possible arb to send act.
localparam nRP_CLKS_M2 = (nRP_CLKS-2 < 0) ? 0 : nRP_CLKS-2;
localparam RP_TIMER_WIDTH = clogb2(nRP_CLKS_M2 + 1);
input sending_pre;
output rts_pre;
generate
if((nCK_PER_CLK == 4) && (ADDR_CMD_MODE != "2T")) begin
assign start_pre = pre_wait_r && ras_timer_zero_r &&
(sending_pre || auto_pre_r);
assign rts_pre = ~sending_pre && pre_request;
end
else begin
assign start_pre = pre_wait_r && ras_timer_zero_r &&
(sending_row || auto_pre_r);
assign rts_pre = 1'b0;
end
endgenerate
reg [RP_TIMER_WIDTH-1:0] rp_timer_r = ZERO[RP_TIMER_WIDTH-1:0];
generate
if (nRP_CLKS_M2 > ZERO) begin : rp_timer
reg [RP_TIMER_WIDTH-1:0] rp_timer_ns;
always @(/*AS*/rp_timer_r or rst or start_pre)
if (rst) rp_timer_ns = ZERO[RP_TIMER_WIDTH-1:0];
else begin
rp_timer_ns = rp_timer_r;
if (start_pre) rp_timer_ns = nRP_CLKS_M2[RP_TIMER_WIDTH-1:0];
else if (|rp_timer_r) rp_timer_ns =
rp_timer_r - ONE[RP_TIMER_WIDTH-1:0];
end
always @(posedge clk) rp_timer_r <= #TCQ rp_timer_ns;
end // block: rp_timer
endgenerate
output wire precharge_bm_end;
assign precharge_bm_end = (rp_timer_r == ONE[RP_TIMER_WIDTH-1:0]) ||
(start_pre && (nRP_CLKS_M2 == ZERO));
// Compute RRD related activate inhibit.
// Compare this bank machine's rank with others, then
// select result based on grant. An alternative is to
// select the just issued rank with the grant and simply
// compare against this bank machine's rank. However, this
// serializes the selection of the rank and the compare processes.
// As implemented below, the compare occurs first, then the
// selection based on grant. This is faster.
input [RANK_WIDTH-1:0] req_rank_r;
input [(RANK_WIDTH*nBANK_MACHS*2)-1:0] req_rank_r_in;
reg inhbt_act_rrd;
input [(nBANK_MACHS*2)-1:0] start_rcd_in;
generate
integer j;
if (RANKS == 1)
always @(/*AS*/req_rank_r or req_rank_r_in or start_rcd_in) begin
inhbt_act_rrd = 1'b0;
for (j=(ID+1); j<(ID+nBANK_MACHS); j=j+1)
inhbt_act_rrd = inhbt_act_rrd || start_rcd_in[j];
end
else begin
always @(/*AS*/req_rank_r or req_rank_r_in or start_rcd_in) begin
inhbt_act_rrd = 1'b0;
for (j=(ID+1); j<(ID+nBANK_MACHS); j=j+1)
inhbt_act_rrd = inhbt_act_rrd ||
(start_rcd_in[j] &&
(req_rank_r_in[(j*RANK_WIDTH)+:RANK_WIDTH] == req_rank_r));
end
end
endgenerate
// Extract the activate command inhibit for the rank associated
// with this request. FAW and RRD are computed separately so that
// gate level timing can be carefully managed.
input [RANKS-1:0] inhbt_act_faw_r;
wire my_inhbt_act_faw = inhbt_act_faw_r[req_rank_r];
input wait_for_maint_r;
input head_r;
wire act_req = ~idle_r && head_r && act_wait_r && ras_timer_zero_r &&
~wait_for_maint_r;
// Implement simple starvation avoidance for act requests. Precharge
// requests don't need this because they are never gated off by
// timing events such as inhbt_act_rrd. Priority request timeout
// is fixed at a single trip around the round robin arbiter.
input sent_row;
wire rts_act_denied = act_req && sent_row && ~sending_row;
reg [BM_CNT_WIDTH-1:0] act_starve_limit_cntr_ns;
reg [BM_CNT_WIDTH-1:0] act_starve_limit_cntr_r;
generate
if (BM_CNT_WIDTH > 1) // Number of Bank Machs > 2
begin :BM_MORE_THAN_2
always @(/*AS*/act_req or act_starve_limit_cntr_r or rts_act_denied)
begin
act_starve_limit_cntr_ns = act_starve_limit_cntr_r;
if (~act_req)
act_starve_limit_cntr_ns = {BM_CNT_WIDTH{1'b0}};
else
if (rts_act_denied && &act_starve_limit_cntr_r)
act_starve_limit_cntr_ns = act_starve_limit_cntr_r +
{{BM_CNT_WIDTH-1{1'b0}}, 1'b1};
end
end
else // Number of Bank Machs == 2
begin :BM_EQUAL_2
always @(/*AS*/act_req or act_starve_limit_cntr_r or rts_act_denied)
begin
act_starve_limit_cntr_ns = act_starve_limit_cntr_r;
if (~act_req)
act_starve_limit_cntr_ns = {BM_CNT_WIDTH{1'b0}};
else
if (rts_act_denied && &act_starve_limit_cntr_r)
act_starve_limit_cntr_ns = act_starve_limit_cntr_r +
{1'b1};
end
end
endgenerate
always @(posedge clk) act_starve_limit_cntr_r <=
#TCQ act_starve_limit_cntr_ns;
reg demand_act_priority_r;
wire demand_act_priority_ns = act_req &&
(demand_act_priority_r || (rts_act_denied && &act_starve_limit_cntr_r));
always @(posedge clk) demand_act_priority_r <= #TCQ demand_act_priority_ns;
`ifdef MC_SVA
cover_demand_act_priority:
cover property (@(posedge clk) (~rst && demand_act_priority_r));
`endif
output wire demand_act_priority;
assign demand_act_priority = demand_act_priority_r && ~sending_row;
// compute act_demanded from other demand_act_priorities
input [(nBANK_MACHS*2)-1:0] demand_act_priority_in;
reg act_demanded = 1'b0;
generate
if (nBANK_MACHS > 1) begin : compute_act_demanded
always @(demand_act_priority_in[`BM_SHARED_BV])
act_demanded = |demand_act_priority_in[`BM_SHARED_BV];
end
endgenerate
wire row_demand_ok = demand_act_priority_r || ~act_demanded;
// Generate the Request To Send row arbitation signal.
output wire rts_row;
generate
if((nCK_PER_CLK == 4) && (ADDR_CMD_MODE != "2T"))
assign rts_row = ~sending_row && row_demand_ok &&
(act_req && ~my_inhbt_act_faw && ~inhbt_act_rrd);
else
assign rts_row = ~sending_row && row_demand_ok &&
((act_req && ~my_inhbt_act_faw && ~inhbt_act_rrd) ||
pre_request);
endgenerate
`ifdef MC_SVA
four_activate_window_wait:
cover property (@(posedge clk)
(~rst && ~sending_row && act_req && my_inhbt_act_faw));
ras_ras_delay_wait:
cover property (@(posedge clk)
(~rst && ~sending_row && act_req && inhbt_act_rrd));
`endif
// Provide rank machines early knowledge that this bank machine is
// going to send an activate to the rank. In this way, the rank
// machines just need to use the sending_row wire to figure out if
// they need to keep track of the activate.
output reg [RANKS-1:0] act_this_rank_r;
reg [RANKS-1:0] act_this_rank_ns;
always @(/*AS*/act_wait_r or req_rank_r) begin
act_this_rank_ns = {RANKS{1'b0}};
for (i = 0; i < RANKS; i = i + 1)
act_this_rank_ns[i] = act_wait_r && (i[RANK_WIDTH-1:0] == req_rank_r);
end
always @(posedge clk) act_this_rank_r <= #TCQ act_this_rank_ns;
// Generate request to send column command signal.
input order_q_zero;
wire req_bank_rdy_ns = order_q_zero && col_wait_r;
reg req_bank_rdy_r;
always @(posedge clk) req_bank_rdy_r <= #TCQ req_bank_rdy_ns;
// Determine is we have been denied a column command request.
input sent_col;
wire rts_col_denied = req_bank_rdy_r && sent_col && ~sending_col;
// Implement a starvation limit counter. Count the number of times a
// request to send a column command has been denied.
localparam STARVE_LIMIT_CNT = STARVE_LIMIT * nBANK_MACHS;
localparam STARVE_LIMIT_WIDTH = clogb2(STARVE_LIMIT_CNT);
reg [STARVE_LIMIT_WIDTH-1:0] starve_limit_cntr_r;
reg [STARVE_LIMIT_WIDTH-1:0] starve_limit_cntr_ns;
always @(/*AS*/col_wait_r or rts_col_denied or starve_limit_cntr_r)
if (~col_wait_r)
starve_limit_cntr_ns = {STARVE_LIMIT_WIDTH{1'b0}};
else
if (rts_col_denied && (starve_limit_cntr_r != STARVE_LIMIT_CNT-1))
starve_limit_cntr_ns = starve_limit_cntr_r +
{{STARVE_LIMIT_WIDTH-1{1'b0}}, 1'b1};
else starve_limit_cntr_ns = starve_limit_cntr_r;
always @(posedge clk) starve_limit_cntr_r <= #TCQ starve_limit_cntr_ns;
input q_has_rd;
input q_has_priority;
// Decide if this bank machine should demand priority. Priority is demanded
// when starvation limit counter is reached, or a bit in the request.
wire starved = ((starve_limit_cntr_r == (STARVE_LIMIT_CNT-1)) &&
rts_col_denied);
input req_priority_r;
input idle_ns;
reg demand_priority_r;
wire demand_priority_ns = ~idle_ns && col_wait_ns &&
(demand_priority_r ||
(order_q_zero &&
(req_priority_r || q_has_priority)) ||
(starved && (q_has_rd || ~req_wr_r)));
always @(posedge clk) demand_priority_r <= #TCQ demand_priority_ns;
`ifdef MC_SVA
wire rdy_for_priority = ~rst && ~demand_priority_r && ~idle_ns &&
col_wait_ns;
req_triggers_demand_priority:
cover property (@(posedge clk)
(rdy_for_priority && req_priority_r && ~q_has_priority && ~starved));
q_priority_triggers_demand_priority:
cover property (@(posedge clk)
(rdy_for_priority && ~req_priority_r && q_has_priority && ~starved));
wire not_req_or_q_rdy_for_priority =
rdy_for_priority && ~req_priority_r && ~q_has_priority;
starved_req_triggers_demand_priority:
cover property (@(posedge clk)
(not_req_or_q_rdy_for_priority && starved && ~q_has_rd && ~req_wr_r));
starved_q_triggers_demand_priority:
cover property (@(posedge clk)
(not_req_or_q_rdy_for_priority && starved && q_has_rd && req_wr_r));
`endif
// compute demanded from other demand_priorities
input [(nBANK_MACHS*2)-1:0] demand_priority_in;
reg demanded = 1'b0;
generate
if (nBANK_MACHS > 1) begin : compute_demanded
always @(demand_priority_in[`BM_SHARED_BV]) demanded =
|demand_priority_in[`BM_SHARED_BV];
end
endgenerate
// In order to make sure that there is no starvation amongst a possibly
// unlimited stream of priority requests, add a second stage to the demand
// priority signal. If there are no other requests demanding priority, then
// go ahead and assert demand_priority. If any other requests are asserting
// demand_priority, hold off asserting demand_priority until these clear, then
// assert demand priority. Its possible to get multiple requests asserting
// demand priority simultaneously, but that's OK. Those requests will be
// serviced, demanded will fall, and another group of requests will be
// allowed to assert demand_priority.
reg demanded_prior_r;
wire demanded_prior_ns = demanded &&
(demanded_prior_r || ~demand_priority_r);
always @(posedge clk) demanded_prior_r <= #TCQ demanded_prior_ns;
output wire demand_priority;
assign demand_priority = demand_priority_r && ~demanded_prior_r &&
~sending_col;
`ifdef MC_SVA
demand_priority_gated:
cover property (@(posedge clk) (demand_priority_r && ~demand_priority));
generate
if (nBANK_MACHS >1) multiple_demand_priority:
cover property (@(posedge clk)
($countones(demand_priority_in[`BM_SHARED_BV]) > 1));
endgenerate
`endif
wire demand_ok = demand_priority_r || ~demanded;
// Figure out if the request in this bank machine matches the current rank
// configuration.
input rnk_config_strobe;
input rnk_config_kill_rts_col;
input rnk_config_valid_r;
input [RANK_WIDTH-1:0] rnk_config;
output wire rtc;
wire rnk_config_match = rnk_config_valid_r && (rnk_config == req_rank_r);
assign rtc = ~rnk_config_match && ~rnk_config_kill_rts_col && order_q_zero && col_wait_r && demand_ok;
// Using rank state provided by the rank machines, figure out if
// a read requests should wait for WTR or RTW.
input [RANKS-1:0] inhbt_rd;
wire my_inhbt_rd = inhbt_rd[req_rank_r];
input [RANKS-1:0] inhbt_wr;
wire my_inhbt_wr = inhbt_wr[req_rank_r];
wire allow_rw = ~rd_wr_r ? ~my_inhbt_wr : ~my_inhbt_rd;
// DQ bus timing constraints.
input dq_busy_data;
// Column command is ready to arbitrate, except for databus restrictions.
wire col_rdy = (col_wait_r || ((nRCD_CLKS <= 1) && end_rcd) ||
(rcv_open_bank && nCK_PER_CLK == 2 && DRAM_TYPE=="DDR2" && BURST_MODE == "4") ||
(rcv_open_bank && nCK_PER_CLK == 4 && BURST_MODE == "8")) &&
order_q_zero;
// Column command is ready to arbitrate for sending a write. Used
// to generate early wr_data_addr for ECC mode.
output wire col_rdy_wr;
assign col_rdy_wr = col_rdy && ~rd_wr_r;
// Figure out if we're ready to send a column command based on all timing
// constraints.
// if timing is an issue.
wire col_cmd_rts = col_rdy && ~dq_busy_data && allow_rw && rnk_config_match;
`ifdef MC_SVA
col_wait_for_order_q: cover property
(@(posedge clk)
(~rst && col_wait_r && ~order_q_zero && ~dq_busy_data &&
allow_rw));
col_wait_for_dq_busy: cover property
(@(posedge clk)
(~rst && col_wait_r && order_q_zero && dq_busy_data &&
allow_rw));
col_wait_for_allow_rw: cover property
(@(posedge clk)
(~rst && col_wait_r && order_q_zero && ~dq_busy_data &&
~allow_rw));
`endif
// Implement flow control for the command and control FIFOs and for the data
// FIFO during writes
input phy_mc_ctl_full;
input phy_mc_cmd_full;
input phy_mc_data_full;
// Register ctl_full and cmd_full
reg phy_mc_ctl_full_r = 1'b0;
reg phy_mc_cmd_full_r = 1'b0;
always @(posedge clk)
if(rst) begin
phy_mc_ctl_full_r <= #TCQ 1'b0;
phy_mc_cmd_full_r <= #TCQ 1'b0;
end else begin
phy_mc_ctl_full_r <= #TCQ phy_mc_ctl_full;
phy_mc_cmd_full_r <= #TCQ phy_mc_cmd_full;
end
// register output data pre-fifo almost full condition and fold in WR status
reg ofs_rdy_r = 1'b0;
always @(posedge clk)
if(rst)
ofs_rdy_r <= #TCQ 1'b0;
else
ofs_rdy_r <= #TCQ ~phy_mc_cmd_full_r && ~phy_mc_ctl_full_r && ~(phy_mc_data_full && ~rd_wr_r);
// Disable priority feature for one state after a config to insure
// forward progress on the just installed io config.
reg override_demand_r;
wire override_demand_ns = rnk_config_strobe || rnk_config_kill_rts_col;
always @(posedge clk) override_demand_r <= override_demand_ns;
output wire rts_col;
assign rts_col = ~sending_col && (demand_ok || override_demand_r) &&
col_cmd_rts && ofs_rdy_r;
// As in act_this_rank, wr/rd_this_rank informs rank machines
// that this bank machine is doing a write/rd. Removes logic
// after the grant.
reg [RANKS-1:0] wr_this_rank_ns;
reg [RANKS-1:0] rd_this_rank_ns;
always @(/*AS*/rd_wr_r or req_rank_r) begin
wr_this_rank_ns = {RANKS{1'b0}};
rd_this_rank_ns = {RANKS{1'b0}};
for (i=0; i<RANKS; i=i+1) begin
wr_this_rank_ns[i] = ~rd_wr_r && (i[RANK_WIDTH-1:0] == req_rank_r);
rd_this_rank_ns[i] = rd_wr_r && (i[RANK_WIDTH-1:0] == req_rank_r);
end
end
output reg [RANKS-1:0] wr_this_rank_r;
always @(posedge clk) wr_this_rank_r <= #TCQ wr_this_rank_ns;
output reg [RANKS-1:0] rd_this_rank_r;
always @(posedge clk) rd_this_rank_r <= #TCQ rd_this_rank_ns;
endmodule // bank_state
|
Subsets and Splits
No saved queries yet
Save your SQL queries to embed, download, and access them later. Queries will appear here once saved.