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// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer _mode; initial _mode = 0;
// verilator lint_off LITENDIAN
reg [7:0] mem_narrow [0:31]; //surefire lint_off_line RD_WRT WRTWRT NBAJAM
reg [77:0] mem_wide [1024:0]; //surefire lint_off_line RD_WRT WRTWRT NBAJAM
reg [7:0] mem_dly_narrow [0:1]; //surefire lint_off_line RD_WRT WRTWRT NBAJAM
reg [77:0] mem_dly_wide [1:0]; //surefire lint_off_line RD_WRT WRTWRT NBAJAM
reg [34:0] vec_wide;
// verilator lint_on LITENDIAN
reg [31:0] wrd0 [15:0];
wire [3:0] sel = 4'h3;
wire [31:0] selout = wrd0[sel];
// Must take LSBs into account in bit extract widths.
wire [15:14] sixt = 2'b10; // surefire lint_off_line ASWCBB
wire [16:14] sixt2 = 3'b110; // surefire lint_off_line ASWCBB
wire [3:0] sixfrom = 13;
wire [4:0] sixfrom2 = 16;
wire sixtext = sixt[sixfrom];
wire sixtext2 = sixt2[sixfrom2];
// Non-power of 2 memory overwriting checks
reg [2:0] np2_mem [5:0] /*verilator public*/;
reg [2:0] np2_guard [7:6] /*verilator public*/;
integer i;
always @ (posedge clk) begin
if (_mode!=0) begin
wrd0[0] = 32'h1;
//
for (i=0; i<32; i=i+1) begin //surefire lint_off_line STMFOR
mem_narrow[i] = i[7:0];
mem_wide[i] = {i[7:0],70'hfeed};
end
//
for (i=0; i<32; i=i+1) begin //surefire lint_off_line STMFOR
if (mem_narrow[i] !== i[7:0]) $stop;
if (mem_wide[i] !== {i[7:0],70'hfeed}) $stop;
end
//
vec_wide <= 0;
//
np2_guard[6] = 0;
np2_guard[7] = 0;
//
$write("selout %b %b %b\n", selout, sixtext, sixtext2);
end
if (_mode == 1) begin
_mode <= 2;
//
i=0;
mem_dly_narrow[0] <= ~i[7:0];
mem_dly_wide[0] <= {~i[7:0],70'hface};
i=1;
mem_dly_narrow[i] <= ~i[7:0];
mem_dly_wide[i] <= {~i[7:0],70'hface};
//
for (i=0; i<16; i=i+1) begin //surefire lint_off_line STMFOR
// verilator lint_off width
np2_mem[i] = i[2:0]; // surefire lint_off_line ASWSBB
// verilator lint_on width
if (np2_guard[6]!=0 || np2_guard[7]!=0) $stop;
end
// verilator lint_off SELRANGE
if (np2_mem[6] !== np2_mem[7]) begin
$write("Mem[6]!=Mem[7] during randomize...\n");
//$stop; // Random value, so this can happen
end
// verilator lint_on SELRANGE
//if (np2_mem[8] !== np2_mem[9]) $stop; // Enhancement: Illegal indexes, make sure map to X's
//
vec_wide[32:31] <= 2'b11;
vec_wide[34] <= 1'b1;
$display("%x",vec_wide);
end
if (_mode == 2) begin
_mode <= 3;
//
for (i=0; i<2; i=i+1) begin //surefire lint_off_line STMFOR
if (mem_dly_narrow[i] !== ~i[7:0]) $stop;
if (mem_dly_wide[i] !== {~i[7:0],70'hface}) $stop;
end
//
//$write ("VW %x %x\n", vec_wide[34:32], vec_wide[31:0]);
if (vec_wide != {4'b101_1,31'd0}) $stop;
//
$write("*-* All Finished *-*\n");
$finish;
end
_mode <= _mode + 1;
end
endmodule
|
//////////////////////////////////////////////////////////////////
////
////
//// CRCAHB CORE BLOCK
////
////
////
//// This file is part of the APB to I2C project
////
//// http://www.opencores.org/cores/apbi2c/
////
////
////
//// Description
////
//// Implementation of APB IP core according to
////
//// crcahb IP core specification document.
////
////
////
//// To Do: Things are right here but always all block can suffer changes
////
////
////
////
////
//// Author(s): - Julio Cesar
////
/////////////////////////////////////////////////////////////////
////
////
//// Copyright (C) 2009 Authors and OPENCORES.ORG
////
////
////
//// This source file may be used and distributed without
////
//// restriction provided that this copyright statement is not
////
//// removed from the file and that any derivative work contains
//// the original copyright notice and the associated disclaimer.
////
////
//// This source file is free software; you can redistribute it
////
//// and/or modify it under the terms of the GNU Lesser General
////
//// Public License as published by the Free Software Foundation;
//// either version 2.1 of the License, or (at your option) any
////
//// later version.
////
////
////
//// This source is distributed in the hope that it will be
////
//// useful, but WITHOUT ANY WARRANTY; without even the implied
////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
////
//// PURPOSE. See the GNU Lesser General Public License for more
//// details.
////
////
////
//// You should have received a copy of the GNU Lesser General
////
//// Public License along with this source; if not, download it
////
//// from http://www.opencores.org/lgpl.shtml
////
////
///////////////////////////////////////////////////////////////////
module crc_datapath
(
//OUTPUTS
output [31:0] crc_out,
output [ 1:0] size_out,
output [ 7:0] crc_idr_out,
output [31:0] crc_poly_out,
output [31:0] crc_init_out,
//INPUTS
input [31:0] bus_wr, //Write data Bus
input [ 1:0] rev_in_type, //select type of reversion of bus
input rev_out_type,
input buffer_en,
input byte_en,
input crc_init_en,
input crc_out_en,
input crc_idr_en,
input crc_poly_en,
input buffer_rst,
input bypass_byte0,
input bypass_size,
input [1:0] byte_sel,
input [1:0] size_in,
input clear_crc_init_sel,
input set_crc_init_sel,
input [1:0] crc_poly_size,
input clk,
input rst_n
);
//Reset definitions
localparam RESET_BUFFER = 32'hffffffff;
localparam RESET_BYTE = 32'hffffffff;
localparam RESET_BF_SIZE = 2'b10;
localparam RESET_SIZE = 2'b10;
localparam RESET_CRC_INIT_SEL = 1'b0;
localparam RESET_CRC_INIT = 32'hffffffff;
localparam RESET_CRC_OUT = 32'h0;
localparam RESET_CRC_IDR = 8'h0;
localparam RESET_CRC_POLY = 32'h04c11db7;
//Parameters definitions
localparam BYTE_0 = 2'b00;
localparam BYTE_1 = 2'b01;
localparam BYTE_2 = 2'b10;
localparam BYTE_3 = 2'b11;
localparam POLY_SIZE_32 = 2'b00;
localparam POLY_SIZE_16 = 2'b01;
localparam POLY_SIZE_8 = 2'b10;
localparam POLY_SIZE_7 = 2'b11;
//Flops Definition
reg [31:0] buffer_ff;
reg [31:0] byte_ff;
reg [31:0] crc_init_ff;
reg [31:0] crc_out_ff;
reg [31:0] crc_poly_ff;
reg [ 7:0] crc_idr_ff;
reg [ 1:0] bf_size_ff;
reg [ 1:0] size_ff;
reg crc_init_sel_ff;
//internal signals definition
reg [7:0] crc_data_in;
reg crc_poly_size_7;
reg crc_poly_size_8;
reg crc_poly_size_16;
reg crc_poly_size_32;
wire [31:0] bus_reversed;
wire [31:0] crc_init_mux;
wire [31:0] crc_unit_out;
wire [31:0] crc_poly_size_in;
wire [31:0] crc_out_rev;
wire [ 7:0] byte0_in;
wire [ 7:0] byte1_in;
wire [ 7:0] byte2_in;
wire [ 7:0] byte3_in;
wire [ 7:0] byte0_mux_out;
//Instantiatin of bit_reversed module
//to perform reversion fuctionality according with rev_type bits
bit_reversal
#(
.DATA_SIZE ( 32 )
)REV_IN
(
.data_out ( bus_reversed ),
.data_in ( bus_wr ),
.rev_type ( rev_in_type )
);
//Definition of Registers buffer_ff and byte_ff
always @(posedge clk)
begin
if(!rst_n)
begin
buffer_ff <= RESET_BUFFER;
byte_ff <= RESET_BYTE;
end
else
begin
if(buffer_en)
buffer_ff <= bus_reversed;
//else
// if(buffer_rst)
// buffer_ff <= RESET_BUFFER;
if(byte_en)
byte_ff <= buffer_ff;
end
end
//Definition of Registers bf_size_ff and size_ff
always @(posedge clk)
begin
if(!rst_n)
begin
bf_size_ff <= RESET_BF_SIZE;
size_ff <= RESET_SIZE;
end
else
begin
if(buffer_en)
bf_size_ff <= size_in;
else
if(buffer_rst)
bf_size_ff <= RESET_BF_SIZE;
if(byte_en)
size_ff <= bf_size_ff;
end
end
//Mux to bypass size_ff
//This informatin is used by FSM to decide the size of the current operatin
assign size_out = (bypass_size) ? bf_size_ff : size_ff;
assign byte0_in = byte_ff[ 7: 0];
assign byte1_in = byte_ff[15: 8];
assign byte2_in = byte_ff[23:16];
assign byte3_in = byte_ff[31:24];
//Mux to bypass byte0_ff
assign byte0_mux_out = (bypass_byte0) ? buffer_ff[7:0] : byte0_in;
//Mux to select input of CRC Unit
//TODO:AVALIAR A INFLUENCIA DA CODIFICACAO DA FSM NO SINAL BYTE_SEL
always @(*)
begin
crc_data_in = 32'h0;
case(byte_sel)
BYTE_0: crc_data_in = byte0_mux_out;
BYTE_1: crc_data_in = byte1_in;
BYTE_2: crc_data_in = byte2_in;
BYTE_3: crc_data_in = byte3_in;
default:crc_data_in = 32'h0;
endcase
end
//Definition of Register crc_init_sel_ff
//This is a set/clear flop where the clear wins set
//This flop controls when the CRC operation is chained (crc_init_sel_ff = 1) or not
//In the chained operatin the current crc calculation depends of the previous crc calculated
//in the unchained operatin the current crc calculation depends of value of crc_init register
always @(posedge clk)
begin
if(!rst_n)
crc_init_sel_ff <= RESET_CRC_INIT_SEL;
else
begin
if(clear_crc_init_sel)
crc_init_sel_ff <= 1'b0;
else
if(set_crc_init_sel)
crc_init_sel_ff <= 1'b1;
end
end
//This register contains the init value used in non chained operatin of crc
assign crc_init_out = crc_init_ff;
always @(posedge clk)
begin
if(!rst_n)
crc_init_ff <= RESET_CRC_INIT;
else
if(crc_init_en)
crc_init_ff <= bus_wr;
else
if(buffer_rst)
crc_init_ff <= RESET_CRC_INIT;
end
//This register contains the final value of crc
always @(posedge clk)
begin
if(!rst_n)
crc_out_ff <= RESET_CRC_OUT;
else
if(crc_out_en)
crc_out_ff <= crc_unit_out;
end
//this is a general purpouse register
//see the spec for more details
assign crc_idr_out = crc_idr_ff;
always @(posedge clk)
begin
if(!rst_n)
crc_idr_ff <= RESET_CRC_IDR;
else
if(crc_idr_en)
crc_idr_ff <= bus_wr[7:0];
end
//This register contains the polynomial coefficients to crc calculation
assign crc_poly_out = crc_poly_ff;
always @(posedge clk)
begin
if(!rst_n)
crc_poly_ff <= RESET_CRC_POLY;
else
if(crc_poly_en)
crc_poly_ff <= bus_wr;
end
//Mux that define the type of operation (chained or not)
assign crc_init_mux = (crc_init_sel_ff) ? crc_out_ff : crc_init_ff;
//Decoding of crc_poly_sizesignal
always @(*)
begin
crc_poly_size_7 = 1'b0;
crc_poly_size_8 = 1'b0;
crc_poly_size_16 = 1'b0;
crc_poly_size_32 = 1'b0;
case(crc_poly_size)
POLY_SIZE_7 : crc_poly_size_7 = 1'b1;
POLY_SIZE_8 : crc_poly_size_8 = 1'b1;
POLY_SIZE_16: crc_poly_size_16 = 1'b1;
POLY_SIZE_32: crc_poly_size_32 = 1'b1;
endcase
end
//This signal define the configurability of the CRC Unit
//In this case, the size of the polynomial can be: 7, 8, 16 or 32
assign crc_poly_size_in = {crc_poly_size_32, 15'h0, crc_poly_size_16, 7'h0, crc_poly_size_8, crc_poly_size_7, 6'h0};
//Instanciation of CRC Unit
//The module is configured to calculate CRC of 32 bits for 8 bits of data in parallel
crc_parallel
#(
.CRC_SIZE ( 32 ),
.FRAME_SIZE ( 8 )
)CRC_UNIT
(
.crc_out ( crc_unit_out ),
.data_in ( crc_data_in ),
.crc_init ( crc_init_mux ),
.crc_poly ( crc_poly_ff ),
.crc_poly_size ( crc_poly_size_in )
);
//crc_out_rev[31:0] = crc_out_ff[0:31]
generate
genvar i;
for(i = 0; i < 32; i = i + 1)
assign crc_out_rev[i] = crc_out_ff[31 - i];
endgenerate
assign crc_out = (rev_out_type) ? crc_out_rev : crc_out_ff;
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_hcmd_nlb # (
parameter P_DATA_WIDTH = 19,
parameter P_ADDR_WIDTH = 7
)
(
input clk,
input rst_n,
input wr0_en,
input [P_ADDR_WIDTH-1:0] wr0_addr,
input [P_DATA_WIDTH-1:0] wr0_data,
output wr0_rdy_n,
input wr1_en,
input [P_ADDR_WIDTH-1:0] wr1_addr,
input [P_DATA_WIDTH-1:0] wr1_data,
output wr1_rdy_n,
input [P_ADDR_WIDTH-1:0] rd_addr,
output [P_DATA_WIDTH-1:0] rd_data
);
localparam S_IDLE = 2'b01;
localparam S_WRITE = 2'b10;
reg [1:0] cur_state;
reg [1:0] next_state;
reg r_wr0_req;
reg r_wr1_req;
reg r_wr0_req_ack;
reg r_wr1_req_ack;
reg [1:0] r_wr_gnt;
reg r_wr_en;
reg [P_ADDR_WIDTH-1:0] r_wr_addr;
reg [P_DATA_WIDTH-1:0] r_wr_data;
reg [P_ADDR_WIDTH-1:0] r_wr0_addr;
reg [P_DATA_WIDTH-1:0] r_wr0_data;
reg [P_ADDR_WIDTH-1:0] r_wr1_addr;
reg [P_DATA_WIDTH-1:0] r_wr1_data;
assign wr0_rdy_n = r_wr0_req;
assign wr1_rdy_n = r_wr1_req | r_wr0_req;
always @(posedge clk)
begin
if(wr0_en == 1) begin
r_wr0_addr <= wr0_addr;
r_wr0_data <= wr0_data;
end
if(wr1_en == 1) begin
r_wr1_addr <= wr1_addr;
r_wr1_data <= wr1_data;
end
end
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0) begin
r_wr0_req <= 0;
r_wr1_req <= 0;
end
else begin
if(r_wr0_req_ack == 1)
r_wr0_req <= 0;
else if(wr0_en == 1)
r_wr0_req <= 1;
if(r_wr1_req_ack == 1)
r_wr1_req <= 0;
else if(wr1_en == 1)
r_wr1_req <= 1;
end
end
always @ (posedge clk or negedge rst_n)
begin
if(rst_n == 0)
cur_state <= S_IDLE;
else
cur_state <= next_state;
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
if(r_wr0_req == 1 || r_wr1_req == 1)
next_state <= S_WRITE;
else
next_state <= S_IDLE;
end
S_WRITE: begin
next_state <= S_IDLE;
end
default: begin
next_state <= S_IDLE;
end
endcase
end
always @ (posedge clk)
begin
case(cur_state)
S_IDLE: begin
if(r_wr1_req == 1)
r_wr_gnt <= 2'b10;
else if(r_wr0_req == 1)
r_wr_gnt <= 2'b01;
end
S_WRITE: begin
end
default: begin
end
endcase
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
r_wr_en <= 0;
r_wr0_req_ack <= 0;
r_wr1_req_ack <= 0;
end
S_WRITE: begin
r_wr_en <= 1;
r_wr0_req_ack <= r_wr_gnt[0];
r_wr1_req_ack <= r_wr_gnt[1];
end
default: begin
r_wr_en <= 0;
r_wr0_req_ack <= 0;
r_wr1_req_ack <= 0;
end
endcase
end
always @ (*)
begin
case(r_wr_gnt) // synthesis parallel_case full_case
2'b01: begin
r_wr_addr <= r_wr0_addr;
r_wr_data <= r_wr0_data;
end
2'b10: begin
r_wr_addr <= r_wr1_addr;
r_wr_data <= r_wr1_data;
end
endcase
end
localparam LP_DEVICE = "7SERIES";
localparam LP_BRAM_SIZE = "18Kb";
localparam LP_DOB_REG = 0;
localparam LP_READ_WIDTH = P_DATA_WIDTH;
localparam LP_WRITE_WIDTH = P_DATA_WIDTH;
localparam LP_WRITE_MODE = "READ_FIRST";
localparam LP_WE_WIDTH = 4;
localparam LP_ADDR_TOTAL_WITDH = 9;
localparam LP_ADDR_ZERO_PAD_WITDH = LP_ADDR_TOTAL_WITDH - P_ADDR_WIDTH;
generate
wire [LP_ADDR_TOTAL_WITDH-1:0] rdaddr;
wire [LP_ADDR_TOTAL_WITDH-1:0] wraddr;
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
if(LP_ADDR_ZERO_PAD_WITDH == 0) begin : calc_addr
assign rdaddr = rd_addr[P_ADDR_WIDTH-1:0];
assign wraddr = r_wr_addr[P_ADDR_WIDTH-1:0];
end
else begin
assign rdaddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], rd_addr[P_ADDR_WIDTH-1:0]};
assign wraddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], r_wr_addr[P_ADDR_WIDTH-1:0]};
end
endgenerate
BRAM_SDP_MACRO #(
.DEVICE (LP_DEVICE),
.BRAM_SIZE (LP_BRAM_SIZE),
.DO_REG (LP_DOB_REG),
.READ_WIDTH (LP_READ_WIDTH),
.WRITE_WIDTH (LP_WRITE_WIDTH),
.WRITE_MODE (LP_WRITE_MODE)
)
ramb18sdp_0(
.DO (rd_data[LP_READ_WIDTH-1:0]),
.DI (r_wr_data[LP_WRITE_WIDTH-1:0]),
.RDADDR (rdaddr),
.RDCLK (clk),
.RDEN (1'b1),
.REGCE (1'b1),
.RST (1'b0),
.WE ({LP_WE_WIDTH{1'b1}}),
.WRADDR (wraddr),
.WRCLK (clk),
.WREN (r_wr_en)
);
endmodule |
(** * Rel: Properties of Relations *)
(* $Date: 2011-03-21 10:44:46 -0400 (Mon, 21 Mar 2011) $ *)
(** This short chapter develops some basic definitions that will be
needed when we come to working with small-step operational
semantics in [Smallstep.v]. It can be postponed until just before
[Smallstep.v], but it is also a good source of good exercises for
developing facility with Coq's basic reasoning facilities, so it
may be useful to look at it just after [Logic.v]. *)
Require Export Logic.
(** A _relation_ is just a parameterized proposition. As you know
from your undergraduate discrete math course, there are a lot of
ways of discussing and describing relations _in general_ -- ways
of classifying relations (are they reflexive, transitive, etc.),
theorems that can be proved generically about classes of
relations, constructions that build one relation from another,
etc. Let us pause here to review a few that will be useful in
what follows. *)
(** A relation _on_ a set [X] is a proposition parameterized by two
[X]s -- i.e., it is a logical assertion involving two values from
the set [X]. *)
Definition relation (X: Type) := X->X->Prop.
(** Somewhat confusingly, the Coq standard library hijacks the generic
term "relation" for this specific instance. To maintain
consistency with the library, we will do the same. So, henceforth
the Coq identifier [relation] will always refer to a binary
relation between some set and itself, while the English word
"relation" can refer either to the specific Coq concept or the
more general concept of a relation between any number of possibly
different sets. The context of the discussion should always make
clear which is meant. *)
(* ######################################################### *)
(** * Basic Properties of Relations *)
(** A relation [R] on a set [X] is a _partial function_ if, for every
[x], there is at most one [y] such that [R x y] -- i.e., if [R x
y1] and [R x y2] together imply [y1 = y2]. *)
Definition partial_function {X: Type} (R: relation X) :=
forall x y1 y2 : X, R x y1 -> R x y2 -> y1 = y2.
(** For example, the [next_nat] relation defined in Logic.v is a
partial function. *)
Theorem next_nat_partial_function :
partial_function next_nat.
Proof.
unfold partial_function.
intros x y1 y2 P Q.
inversion P. inversion Q.
reflexivity. Qed.
(** However, the [<=] relation on numbers is not a partial function.
This can be shown by contradiction. In short: Assume, for a
contradiction, that [<=] is a partial function. But then, since
[0 <= 0] and [0 <= 1], it follows that [0 = 1]. This is nonsense,
so our assumption was contradictory. *)
Theorem le_not_a_partial_function :
~ (partial_function le).
Proof.
unfold not. unfold partial_function. intros H.
assert (0 = 1) as Nonsense.
Case "Proof of assertion".
apply H with 0.
apply le_n.
apply le_S. apply le_n.
inversion Nonsense. Qed.
(** **** Exercise: 2 stars, optional *)
(** Show that the [total_relation] defined in Logic.v is not a partial
function. *)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 2 stars, optional *)
(** Show that the [empty_relation] defined in Logic.v is a partial
function. *)
(* FILL IN HERE *)
(** [] *)
(** A _reflexive_ relation on a set [X] is one that holds for every
element of [X]. *)
Definition reflexive {X: Type} (R: relation X) :=
forall a : X, R a a.
Theorem le_reflexive :
reflexive le.
Proof.
unfold reflexive. intros n. apply le_n. Qed.
(** A relation [R] is _transitive_ if [R a c] holds whenever [R a b]
and [R b c] do. *)
Definition transitive {X: Type} (R: relation X) :=
forall a b c : X, (R a b) -> (R b c) -> (R a c).
Theorem le_trans :
transitive le.
Proof.
intros n m o Hnm Hmo.
induction Hmo.
Case "le_n". apply Hnm.
Case "le_S". apply le_S. apply IHHmo. Qed.
Theorem lt_trans:
transitive lt.
Proof.
unfold lt. unfold transitive.
intros n m o Hnm Hmo.
apply le_S in Hnm.
apply le_trans with (a := (S n)) (b := (S m)) (c := o).
apply Hnm.
apply Hmo. Qed.
(** **** Exercise: 2 stars, optional *)
(** We can also prove [lt_trans] more laboriously by induction,
without using le_trans. Do this.*)
Theorem lt_trans' :
transitive lt.
Proof.
(* Prove this by induction on evidence that [m] is less than [o]. *)
unfold lt. unfold transitive.
intros n m o Hnm Hmo.
induction Hmo as [| m' Hm'o].
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, optional *)
(** Prove the same thing again by induction on [o]. *)
Theorem lt_trans'' :
transitive lt.
Proof.
unfold lt. unfold transitive.
intros n m o Hnm Hmo.
induction o as [| o'].
(* FILL IN HERE *) Admitted.
(** [] *)
(** The transitivity of [le], in turn, can be used to prove some facts
that will be useful later (e.g., for the proof of antisymmetry
below)... *)
Theorem le_Sn_le : forall n m, S n <= m -> n <= m.
Proof.
intros n m H. apply le_trans with (S n).
apply le_S. apply le_n.
apply H. Qed.
(** **** Exercise: 1 star, optional *)
Theorem le_S_n : forall n m,
(S n <= S m) -> (n <= m).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, optional (le_Sn_n_inf) *)
(** Provide an informal proof of the following theorem:
Theorem: For every [n], [~(S n <= n)]
A formal proof of this is an optional exercise below, but try
the informal proof without doing the formal proof first.
Proof:
(* FILL IN HERE *)
[]
*)
(** **** Exercise: 1 star, optional *)
Theorem le_Sn_n : forall n,
~ (S n <= n).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** Reflexivity and transitivity are the main concepts we'll need for
later chapters, but, for a bit of additional practice working with
relations in Coq, here are a few more common ones.
A relation [R] is _symmetric_ if [R a b] implies [R b a]. *)
Definition symmetric {X: Type} (R: relation X) :=
forall a b : X, (R a b) -> (R b a).
(** **** Exercise: 2 stars, optional *)
Theorem le_not_symmetric :
~ (symmetric le).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** A relation [R] is _antisymmetric_ if [R a b] and [R b a] together
imply [a = b] -- that is, if the only "cycles" in [R] are trivial
ones. *)
Definition antisymmetric {X: Type} (R: relation X) :=
forall a b : X, (R a b) -> (R b a) -> a = b.
(** **** Exercise: 2 stars, optional *)
Theorem le_antisymmetric :
antisymmetric le.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, optional *)
Theorem le_step : forall n m p,
n < m ->
m <= S p ->
n <= p.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** A relation is an _equivalence_ if it's reflexive, symmetric, and
transitive. *)
Definition equivalence {X:Type} (R: relation X) :=
(reflexive R) /\ (symmetric R) /\ (transitive R).
(** A relation is a _partial order_ when it's reflexive,
_anti_-symmetric, and transitive. In the Coq standard library
it's called just "order" for short. *)
Definition order {X:Type} (R: relation X) :=
(reflexive R) /\ (antisymmetric R) /\ (transitive R).
(** A preorder is almost like a partial order, but doesn't have to be
antisymmetric. *)
Definition preorder {X:Type} (R: relation X) :=
(reflexive R) /\ (transitive R).
Theorem le_order :
order le.
Proof.
unfold order. split.
Case "refl". apply le_reflexive.
split.
Case "antisym". apply le_antisymmetric.
Case "transitive.". apply le_trans. Qed.
(* ########################################################### *)
(** * Reflexive, Transitive Closure *)
(** The _reflexive, transitive closure_ of a relation [R] is the
smallest relation that contains [R] and that is both reflexive and
transitive. Formally, it is defined like this in the Relations
module of the Coq standard library: *)
Inductive clos_refl_trans {A: Type} (R: relation A) : relation A :=
| rt_step : forall x y, R x y -> clos_refl_trans R x y
| rt_refl : forall x, clos_refl_trans R x x
| rt_trans : forall x y z,
clos_refl_trans R x y -> clos_refl_trans R y z -> clos_refl_trans R x z.
(** For example, the reflexive and transitive closure of the
[next_nat] relation coincides with the [le] relation. *)
Theorem next_nat_closure_is_le : forall n m,
(n <= m) <-> ((clos_refl_trans next_nat) n m).
Proof.
intros n m. split.
Case "->".
intro H. induction H.
apply rt_refl.
apply rt_trans with m. apply IHle. apply rt_step. apply nn.
Case "<-".
intro H. induction H.
SCase "rt_step". inversion H. apply le_S. apply le_n.
SCase "rt_refl". apply le_n.
SCase "rt_trans".
apply le_trans with y.
apply IHclos_refl_trans1.
apply IHclos_refl_trans2. Qed.
(** The above definition of reflexive, transitive closure is
natural -- it says, explicitly, that the reflexive and transitive
closure of [R] is the least relation that includes [R] and that is
closed under rules of reflexivity and transitivity. But it turns
out that this definition is not very convenient for doing
proofs -- the "nondeterminism" of the rt_trans rule can sometimes
lead to tricky inductions.
Here is a more useful definition... *)
Inductive refl_step_closure {X:Type} (R: relation X)
: X -> X -> Prop :=
| rsc_refl : forall (x : X),
refl_step_closure R x x
| rsc_step : forall (x y z : X),
R x y ->
refl_step_closure R y z ->
refl_step_closure R x z.
(** (The following [Tactic Notation] definitions are explained in
Imp.v. You can ignore them if you haven't read that chapter
yet.) *)
Tactic Notation "rt_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "rt_step" | Case_aux c "rt_refl"
| Case_aux c "rt_trans" ].
Tactic Notation "rsc_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "rsc_refl" | Case_aux c "rsc_step" ].
(** Our new definition of reflexive, transitive closure "bundles"
the [rtc_R] and [rtc_trans] rules into the single rule step.
The left-hand premise of this step is a single use of [R],
leading to a much simpler induction principle.
Before we go on, we should check that the two definitions do
indeed define the same relation...
First, we prove two lemmas showing that [rsc] mimics the behavior
of the two "missing" [rtc] constructors. *)
Theorem rsc_R : forall (X:Type) (R:relation X) (x y : X),
R x y -> refl_step_closure R x y.
Proof.
intros X R x y r.
apply rsc_step with y. apply r. apply rsc_refl. Qed.
(** **** Exercise: 2 stars, optional (rsc_trans) *)
Theorem rsc_trans :
forall (X:Type) (R: relation X) (x y z : X),
refl_step_closure R x y ->
refl_step_closure R y z ->
refl_step_closure R x z.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** Then we use these facts to prove that the two definitions of
reflexive, transitive closure do indeed define the same
relation. *)
(** **** Exercise: 3 stars, optional (rtc_rsc_coincide) *)
Theorem rtc_rsc_coincide :
forall (X:Type) (R: relation X) (x y : X),
clos_refl_trans R x y <-> refl_step_closure R x y.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_fp_atan(clock, resetn, enable, dataa, result);
input clock, resetn, enable;
input [31:0] dataa;
output [31:0] result;
fp_atan core(
.sysclk(clock),
.reset(~resetn),
.enable(enable),
.signin(dataa[31]),
.exponentin(dataa[30:23]),
.mantissain(dataa[22:0]),
.signout(result[31]),
.exponentout(result[30:23]),
.mantissaout(result[22:0])
);
endmodule
|
`default_nettype none
`define WIDTH 16
module stack2pipe4(
input wire clk,
output wire [`WIDTH-1:0] rd,
input wire we,
input wire [1:0] delta,
input wire [`WIDTH-1:0] wd);
parameter DEPTH = 18;
localparam BITS = (`WIDTH * DEPTH) - 1;
localparam STATESIZE = `WIDTH * (DEPTH + 1); // complete size of a stack, ie tail+head.
// there are four stacks in total, accessed always in round-robin order.
localparam STATEBITS = STATESIZE - 1; // for wire out of delay
localparam DELAYBITS = (STATESIZE * 3) - 1; // bits to hold the other three stacks.
wire move = delta[0];
wire pop = delta[1];
// these two still written to "now", ie, are the results to save from the present cycle.
reg [15:0] head;
reg [BITS:0] tail;
reg [DELAYBITS:0] delay;
wire [15:0] headN, oldhead;
wire [BITS:0] tailN, oldtail;
wire [DELAYBITS:0] delayN;
// read from the delay fifo, replaced head and tail as the place to read from the old version of current stack.
assign {oldtail, oldhead} = delay[STATEBITS:0];
assign rd = oldhead;
// note these retain old values if not move (and not we and not push). This used to be implicit, but can't be now, since head and tail will cycle through all the stacks, even if neither a move nor a write.
assign headN = we ? wd : (move ? oldtail[15:0] : oldhead);
assign tailN = move ? (pop ? {16'h55aa, oldtail[BITS:16]} : {oldtail[BITS-16:0], oldhead}) : oldtail;
// this is a clock stale already, since it takes it *from* head and tail.
// delay will delay it another three clock cycles.
assign delayN = {tail, head, delay[DELAYBITS:STATESIZE]};
always @(posedge clk) begin
// pass around the other three stacks.
delay <= delayN;
// update the current stack.
head <= headN;
tail <= tailN;
end
`ifdef VERILATOR
int depth /* verilator public_flat */;
always @(posedge clk) begin
if (delta == 2'b11)
depth <= depth - 1;
if (delta == 2'b01)
depth <= depth + 1;
end
`endif
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : arb_select.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// Based on granta_r and grantc_r, this module selects a
// row and column command from the request information
// provided by the bank machines.
//
// Depending on address mode configuration, nCL and nCWL, a column
// command pipeline of up to three states will be created.
`timescale 1 ps / 1 ps
module mig_7series_v4_0_arb_select #
(
parameter TCQ = 100,
parameter EVEN_CWL_2T_MODE = "OFF",
parameter ADDR_CMD_MODE = "1T",
parameter BANK_VECT_INDX = 11,
parameter BANK_WIDTH = 3,
parameter BURST_MODE = "8",
parameter CS_WIDTH = 4,
parameter CL = 5,
parameter CWL = 5,
parameter DATA_BUF_ADDR_VECT_INDX = 31,
parameter DATA_BUF_ADDR_WIDTH = 8,
parameter DRAM_TYPE = "DDR3",
parameter EARLY_WR_DATA_ADDR = "OFF",
parameter ECC = "OFF",
parameter nBANK_MACHS = 4,
parameter nCK_PER_CLK = 2,
parameter nCS_PER_RANK = 1,
parameter CKE_ODT_AUX = "FALSE",
parameter nSLOTS = 2,
parameter RANKS = 1,
parameter RANK_VECT_INDX = 15,
parameter RANK_WIDTH = 2,
parameter ROW_VECT_INDX = 63,
parameter ROW_WIDTH = 16,
parameter RTT_NOM = "40",
parameter RTT_WR = "120",
parameter SLOT_0_CONFIG = 8'b0000_0101,
parameter SLOT_1_CONFIG = 8'b0000_1010
)
(
// Outputs
output wire col_periodic_rd,
output wire [RANK_WIDTH-1:0] col_ra,
output wire [BANK_WIDTH-1:0] col_ba,
output wire [ROW_WIDTH-1:0] col_a,
output wire col_rmw,
output wire col_rd_wr,
output wire col_size,
output wire [ROW_WIDTH-1:0] col_row,
output wire [DATA_BUF_ADDR_WIDTH-1:0] col_data_buf_addr,
output wire [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr,
output wire [nCK_PER_CLK-1:0] mc_ras_n,
output wire [nCK_PER_CLK-1:0] mc_cas_n,
output wire [nCK_PER_CLK-1:0] mc_we_n,
output wire [nCK_PER_CLK*ROW_WIDTH-1:0] mc_address,
output wire [nCK_PER_CLK*BANK_WIDTH-1:0] mc_bank,
output wire [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mc_cs_n,
output wire [1:0] mc_odt,
output wire [nCK_PER_CLK-1:0] mc_cke,
output wire [3:0] mc_aux_out0,
output wire [3:0] mc_aux_out1,
output [2:0] mc_cmd,
output wire [5:0] mc_data_offset,
output wire [5:0] mc_data_offset_1,
output wire [5:0] mc_data_offset_2,
output wire [1:0] mc_cas_slot,
output wire [RANK_WIDTH-1:0] rnk_config,
// Inputs
input clk,
input rst,
input init_calib_complete,
input [RANK_VECT_INDX:0] req_rank_r,
input [BANK_VECT_INDX:0] req_bank_r,
input [nBANK_MACHS-1:0] req_ras,
input [nBANK_MACHS-1:0] req_cas,
input [nBANK_MACHS-1:0] req_wr_r,
input [nBANK_MACHS-1:0] grant_row_r,
input [nBANK_MACHS-1:0] grant_pre_r,
input [ROW_VECT_INDX:0] row_addr,
input [nBANK_MACHS-1:0] row_cmd_wr,
input insert_maint_r1,
input maint_zq_r,
input maint_sre_r,
input maint_srx_r,
input [RANK_WIDTH-1:0] maint_rank_r,
input [nBANK_MACHS-1:0] req_periodic_rd_r,
input [nBANK_MACHS-1:0] req_size_r,
input [nBANK_MACHS-1:0] rd_wr_r,
input [ROW_VECT_INDX:0] req_row_r,
input [ROW_VECT_INDX:0] col_addr,
input [DATA_BUF_ADDR_VECT_INDX:0] req_data_buf_addr_r,
input [nBANK_MACHS-1:0] grant_col_r,
input [nBANK_MACHS-1:0] grant_col_wr,
input [6*RANKS-1:0] calib_rddata_offset,
input [6*RANKS-1:0] calib_rddata_offset_1,
input [6*RANKS-1:0] calib_rddata_offset_2,
input [5:0] col_channel_offset,
input [nBANK_MACHS-1:0] grant_config_r,
input rnk_config_strobe,
input [7:0] slot_0_present,
input [7:0] slot_1_present,
input send_cmd0_row,
input send_cmd0_col,
input send_cmd1_row,
input send_cmd1_col,
input send_cmd2_row,
input send_cmd2_col,
input send_cmd2_pre,
input send_cmd3_col,
input sent_col,
input cs_en0,
input cs_en1,
input cs_en2,
input cs_en3
);
localparam OUT_CMD_WIDTH = RANK_WIDTH + BANK_WIDTH + ROW_WIDTH + 1 + 1 + 1;
reg col_rd_wr_ns;
reg col_rd_wr_r = 1'b0;
reg [OUT_CMD_WIDTH-1:0] col_cmd_r = {OUT_CMD_WIDTH {1'b0}};
reg [OUT_CMD_WIDTH-1:0] row_cmd_r = {OUT_CMD_WIDTH {1'b0}};
// calib_rd_data_offset for currently targeted rank
reg [5:0] rank_rddata_offset_0;
reg [5:0] rank_rddata_offset_1;
reg [5:0] rank_rddata_offset_2;
// Toggle CKE[0] when entering and exiting self-refresh, disable CKE[1]
assign mc_aux_out0[0] = (maint_sre_r || maint_srx_r) & insert_maint_r1;
assign mc_aux_out0[2] = 1'b0;
reg cke_r;
reg cke_ns;
generate
if(CKE_ODT_AUX == "FALSE")begin
always @(posedge clk)
begin
if (rst)
cke_r = 1'b1;
else
cke_r = cke_ns;
end
always @(*)
begin
cke_ns = 1'b1;
if (maint_sre_r & insert_maint_r1)
cke_ns = 1'b0;
else if (cke_r==1'b0)
begin
if (maint_srx_r & insert_maint_r1)
cke_ns = 1'b1;
else
cke_ns = 1'b0;
end
end
end
endgenerate
// Disable ODT & CKE toggle enable high bits
assign mc_aux_out1 = 4'b0;
// implement PHY command word
assign mc_cmd[0] = sent_col;
assign mc_cmd[1] = EVEN_CWL_2T_MODE == "ON" ?
sent_col && col_rd_wr_r :
sent_col && col_rd_wr_ns;
assign mc_cmd[2] = ~sent_col;
// generate calib_rd_data_offset for current rank - only use rank 0 values for now
always @(calib_rddata_offset or calib_rddata_offset_1 or calib_rddata_offset_2) begin
rank_rddata_offset_0 = calib_rddata_offset[5:0];
rank_rddata_offset_1 = calib_rddata_offset_1[5:0];
rank_rddata_offset_2 = calib_rddata_offset_2[5:0];
end
// generate data offset
generate
if(EVEN_CWL_2T_MODE == "ON") begin : gen_mc_data_offset_even_cwl_2t
assign mc_data_offset = ~sent_col ?
6'b0 :
col_rd_wr_r ?
rank_rddata_offset_0 + col_channel_offset :
nCK_PER_CLK == 2 ?
CWL - 2 + col_channel_offset :
// nCK_PER_CLK == 4
CWL + 2 + col_channel_offset;
assign mc_data_offset_1 = ~sent_col ?
6'b0 :
col_rd_wr_r ?
rank_rddata_offset_1 + col_channel_offset :
nCK_PER_CLK == 2 ?
CWL - 2 + col_channel_offset :
// nCK_PER_CLK == 4
CWL + 2 + col_channel_offset;
assign mc_data_offset_2 = ~sent_col ?
6'b0 :
col_rd_wr_r ?
rank_rddata_offset_2 + col_channel_offset :
nCK_PER_CLK == 2 ?
CWL - 2 + col_channel_offset :
// nCK_PER_CLK == 4
CWL + 2 + col_channel_offset;
end
else begin : gen_mc_data_offset_not_even_cwl_2t
assign mc_data_offset = ~sent_col ?
6'b0 :
col_rd_wr_ns ?
rank_rddata_offset_0 + col_channel_offset :
nCK_PER_CLK == 2 ?
CWL - 2 + col_channel_offset :
// nCK_PER_CLK == 4
CWL + 2 + col_channel_offset;
assign mc_data_offset_1 = ~sent_col ?
6'b0 :
col_rd_wr_ns ?
rank_rddata_offset_1 + col_channel_offset :
nCK_PER_CLK == 2 ?
CWL - 2 + col_channel_offset :
// nCK_PER_CLK == 4
CWL + 2 + col_channel_offset;
assign mc_data_offset_2 = ~sent_col ?
6'b0 :
col_rd_wr_ns ?
rank_rddata_offset_2 + col_channel_offset :
nCK_PER_CLK == 2 ?
CWL - 2 + col_channel_offset :
// nCK_PER_CLK == 4
CWL + 2 + col_channel_offset;
end
endgenerate
assign mc_cas_slot = col_channel_offset[1:0];
// Based on arbitration results, select the row and column commands.
integer i;
reg [OUT_CMD_WIDTH-1:0] row_cmd_ns;
generate
begin : row_mux
wire [OUT_CMD_WIDTH-1:0] maint_cmd =
{maint_rank_r, // maintenance rank
row_cmd_r[15+:(BANK_WIDTH+ROW_WIDTH-11)],
// bank plus upper address bits
1'b0, // A10 = 0 for ZQCS
row_cmd_r[3+:10], // address bits [9:0]
// ZQ, SRX or SRE/REFRESH
(maint_zq_r ? 3'b110 : maint_srx_r ? 3'b111 : 3'b001)
};
always @(/*AS*/grant_row_r or insert_maint_r1 or maint_cmd
or req_bank_r or req_cas or req_rank_r or req_ras
or row_addr or row_cmd_r or row_cmd_wr or rst)
begin
row_cmd_ns = rst
? {RANK_WIDTH{1'b0}}
: insert_maint_r1
? maint_cmd
: row_cmd_r;
for (i=0; i<nBANK_MACHS; i=i+1)
if (grant_row_r[i])
row_cmd_ns = {req_rank_r[(RANK_WIDTH*i)+:RANK_WIDTH],
req_bank_r[(BANK_WIDTH*i)+:BANK_WIDTH],
row_addr[(ROW_WIDTH*i)+:ROW_WIDTH],
req_ras[i],
req_cas[i],
row_cmd_wr[i]};
end
if (ADDR_CMD_MODE == "2T" && nCK_PER_CLK == 2)
always @(posedge clk) row_cmd_r <= #TCQ row_cmd_ns;
end // row_mux
endgenerate
reg [OUT_CMD_WIDTH-1:0] pre_cmd_ns;
generate
if((nCK_PER_CLK == 4) && (ADDR_CMD_MODE != "2T")) begin : pre_mux
reg [OUT_CMD_WIDTH-1:0] pre_cmd_r = {OUT_CMD_WIDTH {1'b0}};
always @(/*AS*/grant_pre_r or req_bank_r or req_cas or req_rank_r or req_ras
or row_addr or pre_cmd_r or row_cmd_wr or rst)
begin
pre_cmd_ns = rst
? {RANK_WIDTH{1'b0}}
: pre_cmd_r;
for (i=0; i<nBANK_MACHS; i=i+1)
if (grant_pre_r[i])
pre_cmd_ns = {req_rank_r[(RANK_WIDTH*i)+:RANK_WIDTH],
req_bank_r[(BANK_WIDTH*i)+:BANK_WIDTH],
row_addr[(ROW_WIDTH*i)+:ROW_WIDTH],
req_ras[i],
req_cas[i],
row_cmd_wr[i]};
end
end // pre_mux
endgenerate
reg [OUT_CMD_WIDTH-1:0] col_cmd_ns;
generate
begin : col_mux
reg col_periodic_rd_ns;
reg col_periodic_rd_r;
reg col_rmw_ns;
reg col_rmw_r;
reg col_size_ns;
reg col_size_r;
reg [ROW_WIDTH-1:0] col_row_ns;
reg [ROW_WIDTH-1:0] col_row_r;
reg [DATA_BUF_ADDR_WIDTH-1:0] col_data_buf_addr_ns;
reg [DATA_BUF_ADDR_WIDTH-1:0] col_data_buf_addr_r;
always @(col_addr or col_cmd_r or col_data_buf_addr_r
or col_periodic_rd_r or col_rmw_r or col_row_r
or col_size_r or grant_col_r or rd_wr_r or req_bank_r
or req_data_buf_addr_r or req_periodic_rd_r
or req_rank_r or req_row_r or req_size_r or req_wr_r
or rst or col_rd_wr_r)
begin
col_periodic_rd_ns = ~rst && col_periodic_rd_r;
col_cmd_ns = {(rst ? {RANK_WIDTH{1'b0}}
: col_cmd_r[(OUT_CMD_WIDTH-1)-:RANK_WIDTH]),
((rst && ECC != "OFF")
? {OUT_CMD_WIDTH-3-RANK_WIDTH{1'b0}}
: col_cmd_r[3+:(OUT_CMD_WIDTH-3-RANK_WIDTH)]),
(rst ? 3'b0 : col_cmd_r[2:0])};
col_rmw_ns = col_rmw_r;
col_size_ns = rst ? 1'b0 : col_size_r;
col_row_ns = col_row_r;
col_rd_wr_ns = col_rd_wr_r;
col_data_buf_addr_ns = col_data_buf_addr_r;
for (i=0; i<nBANK_MACHS; i=i+1)
if (grant_col_r[i]) begin
col_periodic_rd_ns = req_periodic_rd_r[i];
col_cmd_ns = {req_rank_r[(RANK_WIDTH*i)+:RANK_WIDTH],
req_bank_r[(BANK_WIDTH*i)+:BANK_WIDTH],
col_addr[(ROW_WIDTH*i)+:ROW_WIDTH],
1'b1,
1'b0,
rd_wr_r[i]};
col_rmw_ns = req_wr_r[i] && rd_wr_r[i];
col_size_ns = req_size_r[i];
col_row_ns = req_row_r[(ROW_WIDTH*i)+:ROW_WIDTH];
col_rd_wr_ns = rd_wr_r[i];
col_data_buf_addr_ns =
req_data_buf_addr_r[(DATA_BUF_ADDR_WIDTH*i)+:DATA_BUF_ADDR_WIDTH];
end
end // always @ (...
if (EARLY_WR_DATA_ADDR == "OFF") begin : early_wr_data_addr_off
assign col_wr_data_buf_addr = col_data_buf_addr_ns;
end
else begin : early_wr_data_addr_on
reg [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr_ns;
reg [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr_r;
always @(/*AS*/col_wr_data_buf_addr_r or grant_col_wr
or req_data_buf_addr_r) begin
col_wr_data_buf_addr_ns = col_wr_data_buf_addr_r;
for (i=0; i<nBANK_MACHS; i=i+1)
if (grant_col_wr[i])
col_wr_data_buf_addr_ns =
req_data_buf_addr_r[(DATA_BUF_ADDR_WIDTH*i)+:DATA_BUF_ADDR_WIDTH];
end
always @(posedge clk) col_wr_data_buf_addr_r <=
#TCQ col_wr_data_buf_addr_ns;
assign col_wr_data_buf_addr = col_wr_data_buf_addr_ns;
end
always @(posedge clk) col_periodic_rd_r <= #TCQ col_periodic_rd_ns;
always @(posedge clk) col_rmw_r <= #TCQ col_rmw_ns;
always @(posedge clk) col_size_r <= #TCQ col_size_ns;
always @(posedge clk) col_data_buf_addr_r <=
#TCQ col_data_buf_addr_ns;
if (ECC != "OFF" || EVEN_CWL_2T_MODE == "ON") begin
always @(posedge clk) col_cmd_r <= #TCQ col_cmd_ns;
always @(posedge clk) col_row_r <= #TCQ col_row_ns;
end
always @(posedge clk) col_rd_wr_r <= #TCQ col_rd_wr_ns;
if(EVEN_CWL_2T_MODE == "ON") begin
assign col_periodic_rd = col_periodic_rd_r;
assign col_ra = col_cmd_r[3+ROW_WIDTH+BANK_WIDTH+:RANK_WIDTH];
assign col_ba = col_cmd_r[3+ROW_WIDTH+:BANK_WIDTH];
assign col_a = col_cmd_r[3+:ROW_WIDTH];
assign col_rmw = col_rmw_r;
assign col_rd_wr = col_rd_wr_r;
assign col_size = col_size_r;
assign col_row = col_row_r;
assign col_data_buf_addr = col_data_buf_addr_r;
end
else begin
assign col_periodic_rd = col_periodic_rd_ns;
assign col_ra = col_cmd_ns[3+ROW_WIDTH+BANK_WIDTH+:RANK_WIDTH];
assign col_ba = col_cmd_ns[3+ROW_WIDTH+:BANK_WIDTH];
assign col_a = col_cmd_ns[3+:ROW_WIDTH];
assign col_rmw = col_rmw_ns;
assign col_rd_wr = col_rd_wr_ns;
assign col_size = col_size_ns;
assign col_row = col_row_ns;
assign col_data_buf_addr = col_data_buf_addr_ns;
end
end // col_mux
endgenerate
reg [OUT_CMD_WIDTH-1:0] cmd0 = {OUT_CMD_WIDTH{1'b1}};
reg cke0;
always @(send_cmd0_row or send_cmd0_col or row_cmd_ns or row_cmd_r or col_cmd_ns or col_cmd_r or cke_ns or cke_r ) begin
cmd0 = {OUT_CMD_WIDTH{1'b1}};
if (send_cmd0_row) cmd0 = row_cmd_ns;
if (send_cmd0_row && EVEN_CWL_2T_MODE == "ON" && nCK_PER_CLK == 2) cmd0 = row_cmd_r;
if (send_cmd0_col) cmd0 = col_cmd_ns;
if (send_cmd0_col && EVEN_CWL_2T_MODE == "ON") cmd0 = col_cmd_r;
if (send_cmd0_row) cke0 = cke_ns;
else cke0 = cke_r ;
end
reg [OUT_CMD_WIDTH-1:0] cmd1 = {OUT_CMD_WIDTH{1'b1}};
generate
if ((nCK_PER_CLK == 2) || (nCK_PER_CLK == 4))
always @(send_cmd1_row or send_cmd1_col or row_cmd_ns or col_cmd_ns or pre_cmd_ns) begin
cmd1 = {OUT_CMD_WIDTH{1'b1}};
if (send_cmd1_row) cmd1 = row_cmd_ns;
if (send_cmd1_col) cmd1 = col_cmd_ns;
end
endgenerate
reg [OUT_CMD_WIDTH-1:0] cmd2 = {OUT_CMD_WIDTH{1'b1}};
reg [OUT_CMD_WIDTH-1:0] cmd3 = {OUT_CMD_WIDTH{1'b1}};
generate
if (nCK_PER_CLK == 4)
always @(send_cmd2_row or send_cmd2_col or send_cmd2_pre or send_cmd3_col or row_cmd_ns or col_cmd_ns or pre_cmd_ns) begin
cmd2 = {OUT_CMD_WIDTH{1'b1}};
cmd3 = {OUT_CMD_WIDTH{1'b1}};
if (send_cmd2_row) cmd2 = row_cmd_ns;
if (send_cmd2_col) cmd2 = col_cmd_ns;
if (send_cmd2_pre) cmd2 = pre_cmd_ns;
if (send_cmd3_col) cmd3 = col_cmd_ns;
end
endgenerate
// Output command bus 0.
wire [RANK_WIDTH-1:0] ra0;
// assign address
assign {ra0, mc_bank[BANK_WIDTH-1:0], mc_address[ROW_WIDTH-1:0], mc_ras_n[0], mc_cas_n[0], mc_we_n[0]} = cmd0;
// Output command bus 1.
wire [RANK_WIDTH-1:0] ra1;
// assign address
assign {ra1, mc_bank[2*BANK_WIDTH-1:BANK_WIDTH], mc_address[2*ROW_WIDTH-1:ROW_WIDTH], mc_ras_n[1], mc_cas_n[1], mc_we_n[1]} = cmd1;
wire [RANK_WIDTH-1:0] ra2;
wire [RANK_WIDTH-1:0] ra3;
generate
if(nCK_PER_CLK == 4) begin
// Output command bus 2.
// assign address
assign {ra2, mc_bank[3*BANK_WIDTH-1:2*BANK_WIDTH], mc_address[3*ROW_WIDTH-1:2*ROW_WIDTH], mc_ras_n[2], mc_cas_n[2], mc_we_n[2]} = cmd2;
// Output command bus 3.
// assign address
assign {ra3, mc_bank[4*BANK_WIDTH-1:3*BANK_WIDTH], mc_address[4*ROW_WIDTH-1:3*ROW_WIDTH], mc_ras_n[3], mc_cas_n[3], mc_we_n[3]} =
cmd3;
end
endgenerate
generate
if(CKE_ODT_AUX == "FALSE")begin
assign mc_cke[0] = cke0;
assign mc_cke[1] = cke_ns;
if(nCK_PER_CLK == 4) begin
assign mc_cke[2] = cke_ns;
assign mc_cke[3] = cke_ns;
end
end
endgenerate
// Output cs busses.
localparam ONE = {nCS_PER_RANK{1'b1}};
wire [(CS_WIDTH*nCS_PER_RANK)-1:0] cs_one_hot =
{{CS_WIDTH{1'b0}},ONE};
assign mc_cs_n[CS_WIDTH*nCS_PER_RANK -1 :0 ] =
{(~(cs_one_hot << (nCS_PER_RANK*ra0)) | {CS_WIDTH*nCS_PER_RANK{~cs_en0}})};
assign mc_cs_n[2*CS_WIDTH*nCS_PER_RANK -1 : CS_WIDTH*nCS_PER_RANK ] =
{(~(cs_one_hot << (nCS_PER_RANK*ra1)) | {CS_WIDTH*nCS_PER_RANK{~cs_en1}})};
generate
if(nCK_PER_CLK == 4) begin
assign mc_cs_n[3*CS_WIDTH*nCS_PER_RANK -1 :2*CS_WIDTH*nCS_PER_RANK ] =
{(~(cs_one_hot << (nCS_PER_RANK*ra2)) | {CS_WIDTH*nCS_PER_RANK{~cs_en2}})};
assign mc_cs_n[4*CS_WIDTH*nCS_PER_RANK -1 :3*CS_WIDTH*nCS_PER_RANK ] =
{(~(cs_one_hot << (nCS_PER_RANK*ra3)) | {CS_WIDTH*nCS_PER_RANK{~cs_en3}})};
end
endgenerate
// Output rnk_config info.
reg [RANK_WIDTH-1:0] rnk_config_ns;
reg [RANK_WIDTH-1:0] rnk_config_r;
always @(/*AS*/grant_config_r
or rnk_config_r or rnk_config_strobe or req_rank_r or rst) begin
if (rst) rnk_config_ns = {RANK_WIDTH{1'b0}};
else begin
rnk_config_ns = rnk_config_r;
if (rnk_config_strobe)
for (i=0; i<nBANK_MACHS; i=i+1)
if (grant_config_r[i]) rnk_config_ns = req_rank_r[(RANK_WIDTH*i)+:RANK_WIDTH];
end
end
always @(posedge clk) rnk_config_r <= #TCQ rnk_config_ns;
assign rnk_config = rnk_config_ns;
// Generate ODT signals.
wire [CS_WIDTH-1:0] col_ra_one_hot = cs_one_hot << col_ra;
wire slot_0_select = (nSLOTS == 1) ? |(col_ra_one_hot & slot_0_present)
: (slot_0_present[2] & slot_0_present[0]) ?
|(col_ra_one_hot[CS_WIDTH-1:0] & {slot_0_present[2],
slot_0_present[0]}) : (slot_0_present[0])?
col_ra_one_hot[0] : 1'b0;
wire slot_0_read = EVEN_CWL_2T_MODE == "ON" ?
slot_0_select && col_rd_wr_r :
slot_0_select && col_rd_wr_ns;
wire slot_0_write = EVEN_CWL_2T_MODE == "ON" ?
slot_0_select && ~col_rd_wr_r :
slot_0_select && ~col_rd_wr_ns;
reg [1:0] slot_1_population = 2'b0;
reg[1:0] slot_0_population;
always @(/*AS*/slot_0_present) begin
slot_0_population = 2'b0;
for (i=0; i<8; i=i+1)
if (~slot_0_population[1])
if (slot_0_present[i] == 1'b1) slot_0_population =
slot_0_population + 2'b1;
end
// ODT on in slot 0 for writes to slot 0 (and R/W to slot 1 for DDR3)
wire slot_0_odt = (DRAM_TYPE == "DDR3") ? ~slot_0_read : slot_0_write;
assign mc_aux_out0[1] = slot_0_odt & sent_col; // Only send for COL cmds
generate
if (nSLOTS > 1) begin : slot_1_configured
wire slot_1_select = (slot_1_present[3] & slot_1_present[1])?
|({col_ra_one_hot[slot_0_population+1],
col_ra_one_hot[slot_0_population]}) :
(slot_1_present[1]) ? col_ra_one_hot[slot_0_population] :1'b0;
wire slot_1_read = EVEN_CWL_2T_MODE == "ON" ?
slot_1_select && col_rd_wr_r :
slot_1_select && col_rd_wr_ns;
wire slot_1_write = EVEN_CWL_2T_MODE == "ON" ?
slot_1_select && ~col_rd_wr_r :
slot_1_select && ~col_rd_wr_ns;
// ODT on in slot 1 for writes to slot 1 (and R/W to slot 0 for DDR3)
wire slot_1_odt = (DRAM_TYPE == "DDR3") ? ~slot_1_read : slot_1_write;
assign mc_aux_out0[3] = slot_1_odt & sent_col; // Only send for COL cmds
end // if (nSLOTS > 1)
else begin
// Disable slot 1 ODT when not present
assign mc_aux_out0[3] = 1'b0;
end // else: !if(nSLOTS > 1)
endgenerate
generate
if(CKE_ODT_AUX == "FALSE")begin
reg[1:0] mc_aux_out_r ;
reg[1:0] mc_aux_out_r_1 ;
reg[1:0] mc_aux_out_r_2 ;
always@(posedge clk) begin
mc_aux_out_r[0] <= #TCQ mc_aux_out0[1] ;
mc_aux_out_r[1] <= #TCQ mc_aux_out0[3] ;
mc_aux_out_r_1 <= #TCQ mc_aux_out_r ;
mc_aux_out_r_2 <= #TCQ mc_aux_out_r_1 ;
end
if((nCK_PER_CLK == 4) && (nSLOTS > 1 )) begin:odt_high_time_4_1_dslot
assign mc_odt[0] = mc_aux_out0[1] | mc_aux_out_r[0] | mc_aux_out_r_1[0];
assign mc_odt[1] = mc_aux_out0[3] | mc_aux_out_r[1] | mc_aux_out_r_1[1];
end else if(nCK_PER_CLK == 4) begin:odt_high_time_4_1
assign mc_odt[0] = mc_aux_out0[1] | mc_aux_out_r[0] ;
assign mc_odt[1] = mc_aux_out0[3] | mc_aux_out_r[1] ;
end else if(nCK_PER_CLK == 2) begin:odt_high_time_2_1
assign mc_odt[0] = mc_aux_out0[1] | mc_aux_out_r[0] | mc_aux_out_r_1[0] | mc_aux_out_r_2[0] ;
assign mc_odt[1] = mc_aux_out0[3] | mc_aux_out_r[1] | mc_aux_out_r_1[1] | mc_aux_out_r_2[1] ;
end
end
endgenerate
endmodule
|
//**********************************************************************
// Reset
// ______ _______ ______ _______ _______
// (_____ \(_______)/ _____|_______|_______)
// _____) )_____ ( (____ _____ _
// | __ /| ___) \____ \| ___) | |
// | | \ \| |_____ _____) ) |_____ | |
// |_| |_|_______|______/|_______) |_|
//
//**********************************************************************
`include "bsg_defines.v"
module bsg_nonsynth_reset_gen #(parameter num_clocks_p=1
, parameter `BSG_INV_PARAM(reset_cycles_lo_p)
, parameter `BSG_INV_PARAM(reset_cycles_hi_p))
(input bit [num_clocks_p-1:0] clk_i
, output bit async_reset_o);
genvar i;
// This module relies on the input clock wires starting at 0 at
// time 0 and not transitioning from X to 0 at time 0, and causing
// a spurious negedge. To accomplish this in > VCS 2020, the input
// must be declared as a bit. Moreover, the expectation is that
// this module's input comes from a clock generation module that
// uses bit, such as bsg_nonsynth_clk_gen, AND that the wire
// between them is a bit.
// use bit instead of logic to default to 0 initialization value
// this makes it non-synthesizeable, but also allows X prop mode to work
bit [num_clocks_p-1:0][$clog2(reset_cycles_lo_p+1)-1:0] ctr_lo_r;
bit [num_clocks_p-1:0][$clog2(reset_cycles_hi_p+1)-1:0] ctr_hi_r;
bit [num_clocks_p-1:0] phase_lo_r;
bit [num_clocks_p-1:0] phase_hi_r;
wire in_phase_1 = & phase_lo_r;
wire in_phase_2 = & phase_hi_r;
for (i = 0; i < num_clocks_p; i=i+1)
begin : rof
assign phase_lo_r[i] = (ctr_lo_r[i] == reset_cycles_lo_p);
assign phase_hi_r[i] = (ctr_hi_r[i] == reset_cycles_hi_p);
always @(negedge clk_i[i])
if (~phase_lo_r[i])
ctr_lo_r[i] <= ctr_lo_r[i] + 1;
else if (~phase_hi_r[i])
ctr_hi_r[i] <= ctr_hi_r[i] + in_phase_1;
end
assign async_reset_o = (in_phase_1 ^ in_phase_2);
always @(negedge async_reset_o)
begin
$display("__________ ___________ _______________________________");
$display("\\______ \\\\_ _____/ / _____/\\_ _____/\\__ ___/");
$display(" | _/ | __)_ \\_____ \\ | __)_ | | ");
$display(" | | \\ | \\ / \\ | \\ | | 1->0 time = ",$stime);
$display(" |____|_ //_______ //_______ //_______ / |____| ");
$display(" ASYNC \\/ \\/ \\/ \\/ ");
end
always @(posedge async_reset_o)
begin
$display("__________ ___________ _______________________________");
$display("\\______ \\\\_ _____/ / _____/\\_ _____/\\__ ___/");
$display(" | _/ | __)_ \\_____ \\ | __)_ | | ");
$display(" | | \\ | \\ / \\ | \\ | | 0->1 time = ",$stime);
$display(" |____|_ //_______ //_______ //_______ / |____| ");
$display(" ASYNC \\/ \\/ \\/ \\/ ");
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_nonsynth_reset_gen)
|
//*****************************************************************************
// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: data_prbs_gen.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:37:19 $
// \ \ / \ Date Created: Fri Sep 01 2006
// \___\/\___\
//
//Device: Spartan6
//Design Name: DDR/DDR2/DDR3/LPDDR
//Purpose: This module is used LFSR to generate random data for memory
// data write or memory data read comparison.The first data is
// seeded by the input prbs_seed_i which is connected to memory address.
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v1_9_data_prbs_gen #
(
parameter TCQ = 100,
parameter EYE_TEST = "FALSE",
parameter PRBS_WIDTH = 32, // "SEQUENTIAL_BUrst_i"
parameter SEED_WIDTH = 32
)
(
input clk_i,
input clk_en,
input rst_i,
input prbs_seed_init, // when high the prbs_x_seed will be loaded
input [PRBS_WIDTH - 1:0] prbs_seed_i,
output [PRBS_WIDTH - 1:0] prbs_o // generated address
);
reg [PRBS_WIDTH - 1 :0] prbs;
reg [PRBS_WIDTH :1] lfsr_q;
integer i;
always @ (posedge clk_i)
begin
if (prbs_seed_init && EYE_TEST == "FALSE" || rst_i ) //reset it to a known good state to prevent it locks up
// if (rst_i ) //reset it to a known good state to prevent it locks up
begin
lfsr_q[4:1] <= #TCQ prbs_seed_i[3:0] | 4'h5;
// lfsr_q[PRBS_WIDTH-1:4] <= #TCQ prbs_seed_i[PRBS_WIDTH-1:4] ;
lfsr_q[PRBS_WIDTH:5] <= #TCQ prbs_seed_i[PRBS_WIDTH-1:4] ;
end
else if (clk_en) begin
lfsr_q[32:9] <= #TCQ lfsr_q[31:8];
lfsr_q[8] <= #TCQ lfsr_q[32] ^ lfsr_q[7];
lfsr_q[7] <= #TCQ lfsr_q[32] ^ lfsr_q[6];
lfsr_q[6:4] <= #TCQ lfsr_q[5:3];
lfsr_q[3] <= #TCQ lfsr_q[32] ^ lfsr_q[2];
lfsr_q[2] <= #TCQ lfsr_q[1] ;
lfsr_q[1] <= #TCQ lfsr_q[32];
end
end
always @ (lfsr_q[PRBS_WIDTH:1]) begin
prbs = lfsr_q[PRBS_WIDTH:1];
end
assign prbs_o = prbs;
endmodule
|
`timescale 1ns / 1ps
module mux4to1_beh_1_tb;
// Inputs
reg [3:0] data_in;
reg [1:0] ctrl_sel;
// Outputs
wire data_out;
// Instantiate the Unit Under Test (UUT)
mux4to1_beh_1 uut (
.data_in(data_in),
.ctrl_sel(ctrl_sel),
.data_out(data_out)
);
task expect;
input exp_out;
if (data_out !== exp_out) begin
$display("TEST FAILED");
$display("At time %0d data_in=%b, ctrl_sel=%b, data_out=%b",
$time, data_in, ctrl_sel, data_out);
$display("data_out should be %b", exp_out);
$finish;
end
else begin
$display("At time %0d data_in=%b, ctrl_sel=%b, data_out=%b",
$time, data_in, ctrl_sel, data_out);
end
endtask
initial begin
data_in = 4'b1010;
ctrl_sel = 2'b00;
#10 expect(1'b0);
ctrl_sel = 2'b01;
#10 expect(1'b1);
ctrl_sel = 2'b10;
#10 expect(1'b0);
ctrl_sel = 2'b11;
#10 expect(1'b1);
$display("TEST PASSED");
$finish;
end
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// orpsoc-defines ////
//// ////
//// Top level ORPSoC defines file ////
//// ////
//// Included in toplevel and testbench ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
// Uncomment a `define BOARD_XYZ to configure design RTL for it.
//
// Mainly presets are for internal frequency settings, and what
// external oscillator is expected (ordb1's were made with various
// XTALs.)
//
//////////////////////////////////////////////////////////////////////
`define XILINX
`define XILINX_PLL
`define FPGA_BOARD_XILINX_ML501
`define IOCONFIG_XILINX_ML501
`define BOARD_CLOCK_PERIOD 5000 // 200MHz (pS accuracy for Xilinx sims.)
`define ADV_DEBUG
// `define JTAG_DEBUG
// `define ROM_WB
`define RAM_WB
// `define XILINX_SSRAM
`define XILINX_DDR2
`define UART0
// `define GPIO0
// `define SPI0
// `define I2C0
// `define I2C1
// `define ETH0
`define ETH0_PHY_RST
// end of included module defines - keep this comment line here, scripts depend on it!!
//
// Arbiter defines
//
// Uncomment to register things through arbiter (hopefully quicker design)
// Instruction bus arbiter
//`define ARBITER_IBUS_REGISTERING
`define ARBITER_IBUS_WATCHDOG
// Watchdog timeout: 2^(ARBITER_IBUS_WATCHDOG_TIMER_WIDTH+1) cycles
// This has to be kind of long, as DDR2 initialisation can take a little while
// and after reset, and if this is too short we'll always get bus error.
`ifdef XILINX_DDR2
`define ARBITER_IBUS_WATCHDOG_TIMER_WIDTH 20
`else
`define ARBITER_IBUS_WATCHDOG_TIMER_WIDTH 6
`endif
// Data bus arbiter
//`define ARBITER_DBUS_REGISTERING
`define ARBITER_DBUS_WATCHDOG
// Watchdog timeout: 2^(ARBITER_DBUS_WATCHDOG_TIMER_WIDTH+1) cycles
`ifdef XILINX_DDR2
`define ARBITER_DBUS_WATCHDOG_TIMER_WIDTH 20
`else
`define ARBITER_DBUS_WATCHDOG_TIMER_WIDTH 6
`endif
// Byte bus (peripheral bus) arbiter
// Don't really need the watchdog here - the databus will pick it up
//`define ARBITER_BYTEBUS_WATCHDOG
// Watchdog timeout: 2^(ARBITER_BYTEBUS_WATCHDOG_TIMER_WIDTH+1) cycles
`define ARBITER_BYTEBUS_WATCHDOG_TIMER_WIDTH 9
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [31:0] in_a;
reg [31:0] in_b;
reg [31:0] e,f,g,h;
always @ (/*AS*/in_a) begin
e = in_a;
f = {e[15:0], e[31:16]};
g = {f[15:0], f[31:16]};
h = {g[15:0], g[31:16]};
end
// verilator lint_off UNOPTFLAT
reg [31:0] e2,f2,g2,h2;
always @ (/*AS*/f2) begin
h2 = {g2[15:0], g2[31:16]};
g2 = {f2[15:0], f2[31:16]};
end
always @ (/*AS*/in_a) begin
f2 = {e2[15:0], e2[31:16]};
e2 = in_a;
end
// verilator lint_on UNOPTFLAT
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
//$write("%d %x %x\n", cyc, h, h2);
if (h != h2) $stop;
if (cyc==1) begin
in_a <= 32'h89a14fab;
in_b <= 32'h7ab512fa;
end
if (cyc==2) begin
in_a <= 32'hf4c11a42;
in_b <= 32'h359967c6;
if (h != 32'h4fab89a1) $stop;
end
if (cyc==3) begin
if (h != 32'h1a42f4c1) $stop;
end
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized COMPARATOR (against constant) with generic_baseblocks_v2_1_0_carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_0_comparator_sel_static #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter C_VALUE = 4'b0,
// Static value to compare against.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire S,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] B,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar bit_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 2;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_FIX_DATA_WIDTH-1:0] v_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign v_local = {C_VALUE, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = B;
assign v_local = C_VALUE;
end
// Instantiate one generic_baseblocks_v2_1_0_carry and per level.
for (bit_cnt = 0; bit_cnt < C_NUM_LUT ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[bit_cnt] = ( ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b0 ) ) |
( ( b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b1 ) );
// Instantiate each LUT level.
generic_baseblocks_v2_1_0_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[bit_cnt+1]),
.CIN (carry_local[bit_cnt]),
.S (sel[bit_cnt])
);
end // end for bit_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule
|
/* tern9.v
*/
module main;
reg flag;
reg val;
wire test1 = flag? val : 1'bx;
wire test2 = flag? 1'b0 : 1'bx;
wire test3 = flag? 1'bx : val;
initial begin
flag = 1;
val = 0;
#1 if (test1 !== 1'b0) begin
$display("FAILED -- flag=%b, val=%b, test1=%b", flag, val, test1);
$finish;
end
if (test2 !== 1'b0) begin
$display("FAILED -- flag=%b, test2=%b", flag, test2);
$finish;
end
if (test3 !== 1'bx) begin
$display("FAILED -- flag=%b, test3=%b", flag, test3);
$finish;
end
val = 1;
#1 if (test1 !== 1'b1) begin
$display("FAILED -- flag=%b, val=%b, test1=%b", flag, val, test1);
$finish;
end
val = 1'bx;
#1 if (test1 !== 1'bx) begin
$display("FAILED -- flag=%b, val=%b, test1=%b", flag, val, test1);
$finish;
end
val = 1'bz;
#1 if (test1 !== 1'bz) begin
$display("FAILED -- flag=%b, val=%b, test1=%b", flag, val, test1);
$finish;
end
flag = 0;
val = 0;
#1 if (test1 !== 1'bx) begin
$display("FAILED -- flag=%b, val=%b, test1=%b", flag, val, test1);
$finish;
end
if (test2 !== 1'bx) begin
$display("FAILED -- flag=%b, test2=%b", flag, test2);
$finish;
end
if (test3 !== 1'b0) begin
$display("FAILED -- flag=%b, test3=%b", flag, test3);
$finish;
end
val = 1;
#1 if (test1 !== 1'bx) begin
$display("FAILED -- flag=%b, val=%b, test1=%b", flag, val, test1);
$finish;
end
if (test3 !== 1'b1) begin
$display("FAILED -- flag=%b, test3=%b", flag, test3);
$finish;
end
val = 1'bx;
#1 if (test3 !== 1'bx) begin
$display("FAILED -- flag=%b, val=%b, test3=%b", flag, val, test3);
$finish;
end
val = 1'bz;
#1 if (test3 !== 1'bz) begin
$display("FAILED -- flag=%b, val=%b, test3=%b", flag, val, test3);
$finish;
end
$display("PASSED");
$finish;
end // initial begin
endmodule
|
`timescale 1ns/1ps
`include "project_defines.v"
module tb_cocotb (
//Virtual Host Interface Signals
input clk,
input rst,
input [31:0] test_id,
output device_interrupt,
output [1:0] ingress_rdy,
input [1:0] ingress_act,
input ingress_stb,
input [31:0] ingress_data,
output [23:0] ingress_size,
output egress_rdy,
input egress_act,
input egress_stb,
output [31:0] egress_data,
output [23:0] egress_size
);
reg r_rst;
reg [1:0] r_ingress_act;
reg r_ingress_stb;
reg [31:0] r_ingress_data;
reg r_egress_clk;
reg r_egress_act;
reg r_egress_stb;
//Parameters
//Registers/Wires
//wishbone signals
wire w_wbp_we;
wire w_wbp_cyc;
wire w_wbp_stb;
wire [3:0] w_wbp_sel;
wire [31:0] w_wbp_adr;
wire [31:0] w_wbp_dat_o;
wire [31:0] w_wbp_dat_i;
wire w_wbp_ack;
wire w_wbp_int;
//Wishbone Slave 0 (SDB) signals
wire w_wbs0_we;
wire w_wbs0_cyc;
wire [31:0] w_wbs0_dat_o;
wire w_wbs0_stb;
wire [3:0] w_wbs0_sel;
wire w_wbs0_ack;
wire [31:0] w_wbs0_dat_i;
wire [31:0] w_wbs0_adr;
wire w_wbs0_int;
//mem slave 0
wire w_sm0_i_wbs_we;
wire w_sm0_i_wbs_cyc;
wire [31:0] w_sm0_i_wbs_dat;
wire [31:0] w_sm0_o_wbs_dat;
wire [31:0] w_sm0_i_wbs_adr;
wire w_sm0_i_wbs_stb;
wire [3:0] w_sm0_i_wbs_sel;
wire w_sm0_o_wbs_ack;
wire w_sm0_o_wbs_int;
//wishbone slave 1 (Unit Under Test) signals
wire w_wbs1_we;
wire w_wbs1_cyc;
wire w_wbs1_stb;
wire [3:0] w_wbs1_sel;
wire w_wbs1_ack;
wire [31:0] w_wbs1_dat_i;
wire [31:0] w_wbs1_dat_o;
wire [31:0] w_wbs1_adr;
wire w_wbs1_int;
//Memory Interface
wire w_mem_we_o;
wire w_mem_cyc_o;
wire w_mem_stb_o;
wire [3:0] w_mem_sel_o;
wire [31:0] w_mem_adr_o;
wire [31:0] w_mem_dat_i;
wire [31:0] w_mem_dat_o;
wire w_mem_ack_i;
wire w_mem_int_i;
wire w_arb0_i_wbs_stb;
wire w_arb0_i_wbs_cyc;
wire w_arb0_i_wbs_we;
wire [3:0] w_arb0_i_wbs_sel;
wire [31:0] w_arb0_i_wbs_dat;
wire [31:0] w_arb0_o_wbs_dat;
wire [31:0] w_arb0_i_wbs_adr;
wire w_arb0_o_wbs_ack;
wire w_arb0_o_wbs_int;
wire mem_o_we;
wire mem_o_stb;
wire mem_o_cyc;
wire [3:0] mem_o_sel;
wire [31:0] mem_o_adr;
wire [31:0] mem_o_dat;
wire [31:0] mem_i_dat;
wire mem_i_ack;
wire mem_i_int;
//Submodules
wishbone_master #(
.INGRESS_FIFO_DEPTH (9 ),
.EGRESS_FIFO_DEPTH (9 ),
.ENABLE_WRITE_RESP (0 ),
.ENABLE_NACK (0 ),
.DEFAULT_TIMEOUT (`CLOCK_RATE )
) wm (
.clk (clk ),
.rst (r_rst ),
//indicate to the input that we are ready
.i_ingress_clk (clk ),
.o_ingress_rdy (ingress_rdy ),
.i_ingress_act (r_ingress_act ),
.i_ingress_stb (r_ingress_stb ),
.i_ingress_data (r_ingress_data ),
.o_ingress_size (ingress_size ),
.i_egress_clk (clk ),
.o_egress_rdy (egress_rdy ),
.i_egress_act (r_egress_act ),
.i_egress_stb (r_egress_stb ),
.o_egress_data (egress_data ),
.o_egress_size (egress_size ),
//General Control
.o_sync_rst (w_sync_rst ),
.o_per_we (w_wbp_we ),
.o_per_adr (w_wbp_adr ),
.o_per_dat (w_wbp_dat_i ),
.i_per_dat (w_wbp_dat_o ),
.o_per_stb (w_wbp_stb ),
.o_per_cyc (w_wbp_cyc ),
.o_per_msk (w_wbp_msk ),
.o_per_sel (w_wbp_sel ),
.i_per_ack (w_wbp_ack ),
.i_per_int (w_wbp_int ),
//memory interconnect signals
.o_mem_we (w_mem_we_o ),
.o_mem_adr (w_mem_adr_o ),
.o_mem_dat (w_mem_dat_o ),
.i_mem_dat (w_mem_dat_i ),
.o_mem_stb (w_mem_stb_o ),
.o_mem_cyc (w_mem_cyc_o ),
.o_mem_sel (w_mem_sel_o ),
.i_mem_ack (w_mem_ack_i ),
.i_mem_int (w_mem_int_i )
);
//slave 1
wb_master_test s1 (
.clk (clk ),
.rst (r_rst ),
.i_wbs_we (w_wbs1_we ),
.i_wbs_sel (4'b1111 ),
.i_wbs_cyc (w_wbs1_cyc ),
.i_wbs_dat (w_wbs1_dat_i ),
.i_wbs_stb (w_wbs1_stb ),
.o_wbs_ack (w_wbs1_ack ),
.o_wbs_dat (w_wbs1_dat_o ),
.i_wbs_adr (w_wbs1_adr ),
.o_wbs_int (w_wbs1_int )
);
wishbone_interconnect wi (
.clk (clk ),
.rst (r_rst ),
.i_m_we (w_wbp_we ),
.i_m_cyc (w_wbp_cyc ),
.i_m_stb (w_wbp_stb ),
.o_m_ack (w_wbp_ack ),
.i_m_dat (w_wbp_dat_i ),
.o_m_dat (w_wbp_dat_o ),
.i_m_adr (w_wbp_adr ),
.o_m_int (w_wbp_int ),
.o_s0_we (w_wbs0_we ),
.o_s0_cyc (w_wbs0_cyc ),
.o_s0_stb (w_wbs0_stb ),
.i_s0_ack (w_wbs0_ack ),
.o_s0_dat (w_wbs0_dat_i ),
.i_s0_dat (w_wbs0_dat_o ),
.o_s0_adr (w_wbs0_adr ),
.i_s0_int (w_wbs0_int ),
.o_s1_we (w_wbs1_we ),
.o_s1_cyc (w_wbs1_cyc ),
.o_s1_stb (w_wbs1_stb ),
.i_s1_ack (w_wbs1_ack ),
.o_s1_dat (w_wbs1_dat_i ),
.i_s1_dat (w_wbs1_dat_o ),
.o_s1_adr (w_wbs1_adr ),
.i_s1_int (w_wbs1_int )
);
wishbone_mem_interconnect wmi (
.clk (clk ),
.rst (r_rst ),
//master
.i_m_we (w_mem_we_o ),
.i_m_cyc (w_mem_cyc_o ),
.i_m_stb (w_mem_stb_o ),
.i_m_sel (w_mem_sel_o ),
.o_m_ack (w_mem_ack_i ),
.i_m_dat (w_mem_dat_o ),
.o_m_dat (w_mem_dat_i ),
.i_m_adr (w_mem_adr_o ),
.o_m_int (w_mem_int_i ),
//slave 0
.o_s0_we (w_sm0_i_wbs_we ),
.o_s0_cyc (w_sm0_i_wbs_cyc ),
.o_s0_stb (w_sm0_i_wbs_stb ),
.o_s0_sel (w_sm0_i_wbs_sel ),
.i_s0_ack (w_sm0_o_wbs_ack ),
.o_s0_dat (w_sm0_i_wbs_dat ),
.i_s0_dat (w_sm0_o_wbs_dat ),
.o_s0_adr (w_sm0_i_wbs_adr ),
.i_s0_int (w_sm0_o_wbs_int )
);
arbiter_2_masters arb0 (
.clk (clk ),
.rst (r_rst ),
//masters
.i_m1_we (mem_o_we ),
.i_m1_stb (mem_o_stb ),
.i_m1_cyc (mem_o_cyc ),
.i_m1_sel (mem_o_sel ),
.i_m1_dat (mem_o_dat ),
.i_m1_adr (mem_o_adr ),
.o_m1_dat (mem_i_dat ),
.o_m1_ack (mem_i_ack ),
.o_m1_int (mem_i_int ),
.i_m0_we (w_sm0_i_wbs_we ),
.i_m0_stb (w_sm0_i_wbs_stb ),
.i_m0_cyc (w_sm0_i_wbs_cyc ),
.i_m0_sel (w_sm0_i_wbs_sel ),
.i_m0_dat (w_sm0_i_wbs_dat ),
.i_m0_adr (w_sm0_i_wbs_adr ),
.o_m0_dat (w_sm0_o_wbs_dat ),
.o_m0_ack (w_sm0_o_wbs_ack ),
.o_m0_int (w_sm0_o_wbs_int ),
//slave
.o_s_we (w_arb0_i_wbs_we ),
.o_s_stb (w_arb0_i_wbs_stb ),
.o_s_cyc (w_arb0_i_wbs_cyc ),
.o_s_sel (w_arb0_i_wbs_sel ),
.o_s_dat (w_arb0_i_wbs_dat ),
.o_s_adr (w_arb0_i_wbs_adr ),
.i_s_dat (w_arb0_o_wbs_dat ),
.i_s_ack (w_arb0_o_wbs_ack ),
.i_s_int (w_arb0_o_wbs_int )
);
wb_bram #(
.DATA_WIDTH (32 ),
.ADDR_WIDTH (10 )
)bram(
.clk (clk ),
.rst (r_rst ),
.i_wbs_we (w_arb0_i_wbs_we ),
.i_wbs_sel (w_arb0_i_wbs_sel ),
.i_wbs_cyc (w_arb0_i_wbs_cyc ),
.i_wbs_dat (w_arb0_i_wbs_dat ),
.i_wbs_stb (w_arb0_i_wbs_stb ),
.i_wbs_adr (w_arb0_i_wbs_adr ),
.o_wbs_dat (w_arb0_o_wbs_dat ),
.o_wbs_ack (w_arb0_o_wbs_ack ),
.o_wbs_int (w_arb0_o_wbs_int )
);
//There is a bug in COCOTB when stiumlating a signal, sometimes it can be corrupted if not registered
always @ (*) r_rst = rst;
always @ (*) r_ingress_act = ingress_act;
always @ (*) r_ingress_stb = ingress_stb;
always @ (*) r_ingress_data = ingress_data;
always @ (*) r_egress_act = egress_act;
always @ (*) r_egress_stb = egress_stb;
//Disable Slave 0
assign w_wbs0_int = 0;
assign w_wbs0_ack = 0;
assign w_wbs0_dat_o = 0;
assign device_interrupt = w_wbp_int;
/*
READ ME IF YOUR MODULE WILL INTERFACE WITH MEMORY
If you want to talk to memory over the wishbone bus directly, your module must control the following signals:
(Your module will be a wishbone master)
mem_o_we
mem_o_stb
mem_o_cyc
mem_o_sel
mem_o_adr
mem_o_dat
mem_i_dat
mem_i_ack
mem_i_int
Currently this bus is disabled so if will not interface with memory these signals can be left
For a reference check out wb_sd_host
*/
assign mem_o_we = 0;
assign mem_o_stb = 0;
assign mem_o_cyc = 0;
assign mem_o_sel = 0;
assign mem_o_adr = 0;
assign mem_o_dat = 0;
//Submodules
//Asynchronous Logic
//Synchronous Logic
//Simulation Control
initial begin
$dumpfile ("design.vcd");
$dumpvars(0, tb_cocotb);
end
endmodule
|
//#############################################################################
//# Purpose: DMA datapath #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see below) #
//#############################################################################
module edma_dp (/*AUTOARG*/
// Outputs
count, srcaddr, dstaddr, wait_out, access_out, packet_out,
// Inputs
clk, nreset, master_active, update2d, datamode, ctrlmode,
stride_reg, count_reg, srcaddr_reg, dstaddr_reg, access_in,
packet_in, wait_in
);
parameter AW = 8; // divider counter width
parameter PW = 2*AW+40; // emesh packet width
// clk, reset, config
input clk; // main clock
input nreset; // async active low reset
input master_active; // master mode active
input update2d; // outer loop transfer
input [1:0] datamode; // datamode for master mode
input [4:0] ctrlmode; // ctrlmode for master mode
// data registers
input [31:0] stride_reg; // transfer stride
input [31:0] count_reg; // starting count
input [AW-1:0] srcaddr_reg; // starting source address
input [AW-1:0] dstaddr_reg; // starting destination address
// output to register file
output [31:0] count; // current count
output [AW-1:0] srcaddr; // current source address
output [AW-1:0] dstaddr; // current source address
// datapath interface
input access_in;
input [PW-1:0] packet_in; // streaming input data
output wait_out;
output access_out;
output [PW-1:0] packet_out; // output packet (with address)
input wait_in; // pushback
//######################################################################
//# BODY
//######################################################################
// regs
reg [PW-1:0] packet_out;
reg access_out;
// wires
wire [4:0] ctrlmode_out;
wire [AW-1:0] data_out;
wire [1:0] datamode_out;
wire [AW-1:0] dstaddr_out;
wire [AW-1:0] srcaddr_out;
wire write_out;
wire [PW-1:0] packet;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [4:0] ctrlmode_in; // From p2e of packet2emesh.v
wire [AW-1:0] data_in; // From p2e of packet2emesh.v
wire [1:0] datamode_in; // From p2e of packet2emesh.v
wire [AW-1:0] dstaddr_in; // From p2e of packet2emesh.v
wire [AW-1:0] srcaddr_in; // From p2e of packet2emesh.v
wire write_in; // From p2e of packet2emesh.v
// End of automatics
/*AUTOINPUT*/
//################################
//# COUNT
//################################
assign count[31:0] = update2d ? {(count_reg[31:16] - 1'b1),count_reg[15:0]} :
count_reg[31:0] - 1'b1;
//################################
//# SRCADDR
//################################
assign srcaddr[AW-1:0] = srcaddr_reg[AW-1:0] +
{{(AW-16){stride_reg[15]}},stride_reg[15:0]};
//################################
//# DSTADDR
//################################
assign dstaddr[AW-1:0] = dstaddr_reg[AW-1:0] +
{{(AW-16){stride_reg[31]}},stride_reg[31:16]};
//################################
//# MASTER/SLAVE MUX
//################################
// parsing input packet
packet2emesh #(.AW(AW),
.PW(PW))
p2e (/*AUTOINST*/
// Outputs
.write_in (write_in),
.datamode_in (datamode_in[1:0]),
.ctrlmode_in (ctrlmode_in[4:0]),
.dstaddr_in (dstaddr_in[AW-1:0]),
.srcaddr_in (srcaddr_in[AW-1:0]),
.data_in (data_in[AW-1:0]),
// Inputs
.packet_in (packet_in[PW-1:0]));
//master/slave mux
assign write_out = master_active ? 1'b0 : 1'b1;
assign datamode_out[1:0] = master_active ? datamode[1:0] : datamode_in[1:0];
assign ctrlmode_out[4:0] = master_active ? ctrlmode[4:0] : ctrlmode_in[4:0];
assign dstaddr_out[AW-1:0] = dstaddr[AW-1:0];
assign data_out[AW-1:0] = master_active ? {(AW){1'b0}} : data_in[31:0];
assign srcaddr_out[AW-1:0] = master_active ? {(AW){1'b0}} : srcaddr_in[31:0];
// constructing output packet
emesh2packet #(.AW(AW),
.PW(PW))
e2p (.packet_out (packet[PW-1:0]),
/*AUTOINST*/
// Inputs
.write_out (write_out),
.datamode_out (datamode_out[1:0]),
.ctrlmode_out (ctrlmode_out[4:0]),
.dstaddr_out (dstaddr_out[AW-1:0]),
.data_out (data_out[AW-1:0]),
.srcaddr_out (srcaddr_out[AW-1:0]));
//################################
//# REGISTER (FOR TIMING PURPOSES)
//################################
//pipelining the packet
always @ (posedge clk)
if(~wait_in)
packet_out[PW-1:0] <= packet[PW-1:0];
// access signal
always @ (posedge clk)
if(~wait_in)
access_out <= access_in | master_active;
//wait pass through (for slave access)
assign wait_out = wait_in;
endmodule // edma_dp
// Local Variables:
// verilog-library-directories:("." "../../emesh/hdl")
// End:
///////////////////////////////////////////////////////////////////////////////
// The MIT License (MIT) //
// //
// Copyright (c) 2015-2016, Adapteva, Inc. //
// //
// Permission is hereby granted, free of charge, to any person obtaining a //
// copy of this software and associated documentation files (the "Software") //
// to deal in the Software without restriction, including without limitation //
// the rights to use, copy, modify, merge, publish, distribute, sublicense, //
// and/or sell copies of the Software, and to permit persons to whom the //
// Software is furnished to do so, subject to the following conditions: //
// //
// The above copyright notice and this permission notice shall be included //
// in all copies or substantial portions of the Software. //
// //
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS //
// OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF //
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. //
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY //
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT //
// OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR //
// THE USE OR OTHER DEALINGS IN THE SOFTWARE. //
// //
///////////////////////////////////////////////////////////////////////////////
|
// megafunction wizard: %FIFO%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: fifo_4k.v
// Megafunction Name(s):
// dcfifo
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 5.0 Build 168 06/22/2005 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2005 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module fifo_4k (
data,
wrreq,
rdreq,
rdclk,
wrclk,
aclr,
q,
rdempty,
rdusedw,
wrfull,
wrusedw)/* synthesis synthesis_clearbox = 1 */;
input [15:0] data;
input wrreq;
input rdreq;
input rdclk;
input wrclk;
input aclr;
output [15:0] q;
output rdempty;
output [11:0] rdusedw;
output wrfull;
output [11:0] wrusedw;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: Width NUMERIC "16"
// Retrieval info: PRIVATE: Depth NUMERIC "4096"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4096"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "12"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
// Retrieval info: USED_PORT: rdusedw 0 0 12 0 OUTPUT NODEFVAL rdusedw[11..0]
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
// Retrieval info: USED_PORT: wrusedw 0 0 12 0 OUTPUT NODEFVAL wrusedw[11..0]
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: rdusedw 0 0 12 0 @rdusedw 0 0 12 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: CONNECT: wrusedw 0 0 12 0 @wrusedw 0 0 12 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_wave*.jpg FALSE
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : PIO_TX_ENGINE.v
// Version : 1.11
//-- Description: Local-Link Transmit Unit.
//--
//--------------------------------------------------------------------------------
`timescale 1ps/1ps
module PIO_TX_ENGINE #(
// RX/TX interface data width
parameter C_DATA_WIDTH = 64,
parameter TCQ = 1,
// TSTRB width
parameter KEEP_WIDTH = C_DATA_WIDTH / 8
)(
input clk,
input rst_n,
// AXIS
input s_axis_tx_tready,
output reg [C_DATA_WIDTH-1:0] s_axis_tx_tdata,
output reg [KEEP_WIDTH-1:0] s_axis_tx_tkeep,
output reg s_axis_tx_tlast,
output reg s_axis_tx_tvalid,
output tx_src_dsc,
input req_compl,
input req_compl_wd,
output reg compl_done,
input [2:0] req_tc,
input req_td,
input req_ep,
input [1:0] req_attr,
input [9:0] req_len,
input [15:0] req_rid,
input [7:0] req_tag,
input [7:0] req_be,
input [12:0] req_addr,
output [10:0] rd_addr,
output reg [3:0] rd_be,
input [31:0] rd_data,
input [15:0] completer_id
);
localparam PIO_CPLD_FMT_TYPE = 7'b10_01010;
localparam PIO_CPL_FMT_TYPE = 7'b00_01010;
localparam PIO_TX_RST_STATE = 1'b0;
localparam PIO_TX_CPLD_QW1 = 1'b1;
// Local registers
reg [11:0] byte_count;
reg [6:0] lower_addr;
reg req_compl_q;
reg req_compl_wd_q;
// Local wires
wire compl_wd;
// Unused discontinue
assign tx_src_dsc = 1'b0;
// Present address and byte enable to memory module
assign rd_addr = req_addr[12:2];
always @(posedge clk) begin
if (!rst_n)
begin
rd_be <= #TCQ 0;
end else begin
rd_be <= #TCQ req_be[3:0];
end
end
// Calculate byte count based on byte enable
always @ (rd_be) begin
casex (rd_be[3:0])
4'b1xx1 : byte_count = 12'h004;
4'b01x1 : byte_count = 12'h003;
4'b1x10 : byte_count = 12'h003;
4'b0011 : byte_count = 12'h002;
4'b0110 : byte_count = 12'h002;
4'b1100 : byte_count = 12'h002;
4'b0001 : byte_count = 12'h001;
4'b0010 : byte_count = 12'h001;
4'b0100 : byte_count = 12'h001;
4'b1000 : byte_count = 12'h001;
4'b0000 : byte_count = 12'h001;
endcase
end
always @ ( posedge clk ) begin
if (!rst_n )
begin
req_compl_q <= #TCQ 1'b0;
req_compl_wd_q <= #TCQ 1'b1;
end // if !rst_n
else
begin
req_compl_q <= #TCQ req_compl;
req_compl_wd_q <= #TCQ req_compl_wd;
end // if rst_n
end
// generate
// if (C_DATA_WIDTH == 128) begin : init_128
//
// reg req_compl_q2;
// reg req_compl_wd_q2;
//
// always @ ( posedge clk ) begin
// if (!rst_n )
// begin
// req_compl_q2 <= #TCQ 1'b0;
// req_compl_wd_q2 <= #TCQ 1'b0;
// end // if (!rst_n )
// else
// begin
// req_compl_q2 <= #TCQ req_compl_q;
// req_compl_wd_q2 <= #TCQ req_compl_wd_q;
// end // if (rst_n )
// end
// end
// endgenerate
// Calculate lower address based on byte enable
// generate
// if (C_DATA_WIDTH == 64) begin : cd_64
// assign compl_wd = req_compl_wd_q;
// end
// else if (C_DATA_WIDTH == 128) begin : cd_128
// assign compl_wd = req_compl_wd_q2;
// end
// endgenerate
always @ (rd_be or req_addr or compl_wd) begin
casex ({compl_wd, rd_be[3:0]})
5'b1_0000 : lower_addr = {req_addr[6:2], 2'b00};
5'b1_xxx1 : lower_addr = {req_addr[6:2], 2'b00};
5'b1_xx10 : lower_addr = {req_addr[6:2], 2'b01};
5'b1_x100 : lower_addr = {req_addr[6:2], 2'b10};
5'b1_1000 : lower_addr = {req_addr[6:2], 2'b11};
5'b0_xxxx : lower_addr = 8'h0;
endcase // casex ({compl_wd, rd_be[3:0]})
end
// Generate Completion with 1 DW Payload
generate
if (C_DATA_WIDTH == 64) begin : gen_cpl_64
reg state;
assign compl_wd = req_compl_wd_q;
always @ ( posedge clk ) begin
if (!rst_n )
begin
s_axis_tx_tlast <= #TCQ 1'b0;
s_axis_tx_tvalid <= #TCQ 1'b0;
s_axis_tx_tdata <= #TCQ {C_DATA_WIDTH{1'b0}};
s_axis_tx_tkeep <= #TCQ {KEEP_WIDTH{1'b0}};
compl_done <= #TCQ 1'b0;
state <= #TCQ PIO_TX_RST_STATE;
end // if (!rst_n )
else
begin
case ( state )
PIO_TX_RST_STATE : begin
if (req_compl_q)
begin
s_axis_tx_tlast <= #TCQ 1'b0;
s_axis_tx_tvalid <= #TCQ 1'b1;
// Swap DWORDS for AXI
s_axis_tx_tdata <= #TCQ { // Bits
completer_id, // 16
{3'b0}, // 3
{1'b0}, // 1
byte_count, // 12
{1'b0}, // 1
(req_compl_wd_q ?
PIO_CPLD_FMT_TYPE :
PIO_CPL_FMT_TYPE), // 7
{1'b0}, // 1
req_tc, // 3
{4'b0}, // 4
req_td, // 1
req_ep, // 1
req_attr, // 2
{2'b0}, // 2
req_len // 10
};
s_axis_tx_tkeep <= #TCQ 8'hFF;
// Wait in this state if the PCIe core does not accept
// the first beat of the packet
if (s_axis_tx_tready)
state <= #TCQ PIO_TX_CPLD_QW1;
else
state <= #TCQ PIO_TX_RST_STATE;
end // if (req_compl_q)
else
begin
s_axis_tx_tlast <= #TCQ 1'b0;
s_axis_tx_tvalid <= #TCQ 1'b0;
s_axis_tx_tdata <= #TCQ 64'b0;
s_axis_tx_tkeep <= #TCQ 8'hFF;
compl_done <= #TCQ 1'b0;
state <= #TCQ PIO_TX_RST_STATE;
end // if !(req_compl_q)
end // PIO_TX_RST_STATE
PIO_TX_CPLD_QW1 : begin
if (s_axis_tx_tready)
begin
s_axis_tx_tlast <= #TCQ 1'b1;
s_axis_tx_tvalid <= #TCQ 1'b1;
// Swap DWORDS for AXI
s_axis_tx_tdata <= #TCQ { // Bits
rd_data, // 32
req_rid, // 16
req_tag, // 8
{1'b0}, // 1
lower_addr // 7
};
// Here we select if the packet has data or
// not. The strobe signal will mask data
// when it is not needed. No reason to change
// the data bus.
if (req_compl_wd_q)
s_axis_tx_tkeep <= #TCQ 8'hFF;
else
s_axis_tx_tkeep <= #TCQ 8'h0F;
compl_done <= #TCQ 1'b1;
state <= #TCQ PIO_TX_RST_STATE;
end // if (s_axis_tx_tready)
else
state <= #TCQ PIO_TX_CPLD_QW1;
end // PIO_TX_CPLD_QW1
default : begin
// case default stmt
state <= #TCQ PIO_TX_RST_STATE;
end
endcase
end // if rst_n
end
end
else if (C_DATA_WIDTH == 128) begin : gen_cpl_128
reg hold_state;
reg req_compl_q2;
reg req_compl_wd_q2;
assign compl_wd = req_compl_wd_q2;
always @ ( posedge clk ) begin
if (!rst_n )
begin
req_compl_q2 <= #TCQ 1'b0;
req_compl_wd_q2 <= #TCQ 1'b0;
end // if (!rst_n )
else
begin
req_compl_q2 <= #TCQ req_compl_q;
req_compl_wd_q2 <= #TCQ req_compl_wd_q;
end // if (rst_n )
end
always @ ( posedge clk ) begin
if (!rst_n )
begin
s_axis_tx_tlast <= #TCQ 1'b0;
s_axis_tx_tvalid <= #TCQ 1'b0;
s_axis_tx_tdata <= #TCQ {C_DATA_WIDTH{1'b0}};
s_axis_tx_tkeep <= #TCQ {KEEP_WIDTH{1'b0}};
compl_done <= #TCQ 1'b0;
hold_state <= #TCQ 1'b0;
end // if !rst_n
else
begin
if (req_compl_q2 | hold_state)
begin
if (s_axis_tx_tready)
begin
s_axis_tx_tlast <= #TCQ 1'b1;
s_axis_tx_tvalid <= #TCQ 1'b1;
s_axis_tx_tdata <= #TCQ { // Bits
rd_data, // 32
req_rid, // 16
req_tag, // 8
{1'b0}, // 1
lower_addr, // 7
completer_id, // 16
{3'b0}, // 3
{1'b0}, // 1
byte_count, // 12
{1'b0}, // 1
(req_compl_wd_q2 ?
PIO_CPLD_FMT_TYPE :
PIO_CPL_FMT_TYPE), // 7
{1'b0}, // 1
req_tc, // 3
{4'b0}, // 4
req_td, // 1
req_ep, // 1
req_attr, // 2
{2'b0}, // 2
req_len // 10
};
// Here we select if the packet has data or
// not. The strobe signal will mask data
// when it is not needed. No reason to change
// the data bus.
if (req_compl_wd_q2)
s_axis_tx_tkeep <= #TCQ 16'hFFFF;
else
s_axis_tx_tkeep <= #TCQ 16'h0FFF;
compl_done <= #TCQ 1'b1;
hold_state <= #TCQ 1'b0;
end // if (s_axis_tx_tready)
else
hold_state <= #TCQ 1'b1;
end // if (req_compl_q2 | hold_state)
else
begin
s_axis_tx_tlast <= #TCQ 1'b0;
s_axis_tx_tvalid <= #TCQ 1'b0;
s_axis_tx_tdata <= #TCQ {C_DATA_WIDTH{1'b0}};
s_axis_tx_tkeep <= #TCQ {KEEP_WIDTH{1'b1}};
compl_done <= #TCQ 1'b0;
end // if !(req_compl_q2 | hold_state)
end // if rst_n
end
end
endgenerate
endmodule // PIO_TX_ENGINE
|
// (C) 2001-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// ********************************************************************************************************************************
// File name: acv_hard_memphy.v
// This file instantiates all the main components of the PHY.
// ********************************************************************************************************************************
`timescale 1 ps / 1 ps
module hps_sdram_p0_acv_hard_memphy (
global_reset_n,
soft_reset_n,
ctl_reset_n,
ctl_reset_export_n,
afi_reset_n,
pll_locked,
oct_ctl_rs_value,
oct_ctl_rt_value,
afi_addr,
afi_ba,
afi_cke,
afi_cs_n,
afi_ras_n,
afi_we_n,
afi_cas_n,
afi_rst_n,
afi_odt,
afi_mem_clk_disable,
afi_dqs_burst,
afi_wdata_valid,
afi_wdata,
afi_dm,
afi_rdata,
afi_rdata_en,
afi_rdata_en_full,
afi_rdata_valid,
afi_wlat,
afi_rlat,
afi_cal_success,
afi_cal_fail,
avl_read,
avl_write,
avl_address,
avl_writedata,
avl_waitrequest,
avl_readdata,
cfg_addlat,
cfg_bankaddrwidth,
cfg_caswrlat,
cfg_coladdrwidth,
cfg_csaddrwidth,
cfg_devicewidth,
cfg_dramconfig,
cfg_interfacewidth,
cfg_rowaddrwidth,
cfg_tcl,
cfg_tmrd,
cfg_trefi,
cfg_trfc,
cfg_twr,
io_intaddrdout,
io_intbadout,
io_intcasndout,
io_intckdout,
io_intckedout,
io_intckndout,
io_intcsndout,
io_intdmdout,
io_intdqdin,
io_intdqdout,
io_intdqoe,
io_intdqsbdout,
io_intdqsboe,
io_intdqsdout,
io_intdqslogicdqsena,
io_intdqslogicfiforeset,
io_intdqslogicincrdataen,
io_intdqslogicincwrptr,
io_intdqslogicoct,
io_intdqslogicrdatavalid,
io_intdqslogicreadlatency,
io_intdqsoe,
io_intodtdout,
io_intrasndout,
io_intresetndout,
io_intwendout,
io_intafirlat,
io_intafiwlat,
io_intaficalfail,
io_intaficalsuccess,
mem_a,
mem_ba,
mem_cs_n,
mem_cke,
mem_odt,
mem_we_n,
mem_ras_n,
mem_cas_n,
mem_reset_n,
mem_dq,
mem_dm,
mem_ck,
mem_ck_n,
mem_dqs,
mem_dqs_n,
reset_n_scc_clk,
reset_n_avl_clk,
scc_data,
scc_dqs_ena,
scc_dqs_io_ena,
scc_dq_ena,
scc_dm_ena,
scc_upd,
capture_strobe_tracking,
phy_clk,
ctl_clk,
phy_reset_n,
pll_afi_clk,
pll_afi_half_clk,
pll_addr_cmd_clk,
pll_mem_clk,
pll_mem_phy_clk,
pll_afi_phy_clk,
pll_avl_phy_clk,
pll_write_clk,
pll_write_clk_pre_phy_clk,
pll_dqs_ena_clk,
seq_clk,
pll_avl_clk,
pll_config_clk,
dll_clk,
dll_pll_locked,
dll_phy_delayctrl
);
// ********************************************************************************************************************************
// BEGIN PARAMETER SECTION
// All parameters default to "" will have their values passed in from higher level wrapper with the controller and driver
parameter DEVICE_FAMILY = "";
parameter IS_HHP_HPS = "false";
// On-chip termination
parameter OCT_SERIES_TERM_CONTROL_WIDTH = "";
parameter OCT_PARALLEL_TERM_CONTROL_WIDTH = "";
// PHY-Memory Interface
// Memory device specific parameters, they are set according to the memory spec
parameter MEM_ADDRESS_WIDTH = "";
parameter MEM_BANK_WIDTH = "";
parameter MEM_IF_CS_WIDTH = "";
parameter MEM_CLK_EN_WIDTH = "";
parameter MEM_CK_WIDTH = "";
parameter MEM_ODT_WIDTH = "";
parameter MEM_DQS_WIDTH = "";
parameter MEM_DM_WIDTH = "";
parameter MEM_CONTROL_WIDTH = "";
parameter MEM_DQ_WIDTH = "";
parameter MEM_READ_DQS_WIDTH = "";
parameter MEM_WRITE_DQS_WIDTH = "";
// PHY-Controller (AFI) Interface
// The AFI interface widths are derived from the memory interface widths based on full/half rate operations
// The calculations are done on higher level wrapper
// DLL Interface
// The DLL delay output control is always 6 bits for current existing devices
parameter DLL_DELAY_CTRL_WIDTH = "";
parameter MR1_ODS = "";
parameter MR1_RTT = "";
parameter MR2_RTT_WR = "";
parameter TB_PROTOCOL = "";
parameter TB_MEM_CLK_FREQ = "";
parameter TB_RATE = "";
parameter TB_MEM_DQ_WIDTH = "";
parameter TB_MEM_DQS_WIDTH = "";
parameter TB_PLL_DLL_MASTER = "";
parameter FAST_SIM_MODEL = "";
parameter FAST_SIM_CALIBRATION = "";
// Width of the calibration status register used to control calibration skipping.
parameter CALIB_REG_WIDTH = "";
parameter AC_ROM_INIT_FILE_NAME = "";
parameter INST_ROM_INIT_FILE_NAME = "";
// The number of AFI Resets to generate
localparam NUM_AFI_RESET = 4;
// Addr/cmd clock phase
localparam ADC_PHASE_SETTING = 0;
localparam ADC_INVERT_PHASE = "true";
// END PARAMETER SECTION
// ********************************************************************************************************************************
// ********************************************************************************************************************************
// BEGIN PORT SECTION
// Reset Interface
input global_reset_n; // Resets (active-low) the whole system (all PHY logic + PLL)
input soft_reset_n; // Resets (active-low) PHY logic only, PLL is NOT reset
input pll_locked; // Indicates that PLL is locked
output ctl_reset_n; // Asynchronously asserted and synchronously de-asserted on ctl_clk domain
output ctl_reset_export_n; // Asynchronously asserted and synchronously de-asserted on ctl_clk domain
output afi_reset_n; // Asynchronously asserted and synchronously de-asserted on afi_clk domain
input [OCT_SERIES_TERM_CONTROL_WIDTH-1:0] oct_ctl_rs_value;
input [OCT_PARALLEL_TERM_CONTROL_WIDTH-1:0] oct_ctl_rt_value;
// PHY-Controller Interface, AFI 2.0
// Control Interface
input [19:0] afi_addr;
input [2:0] afi_ba;
input [1:0] afi_cke;
input [1:0] afi_cs_n;
input [0:0] afi_cas_n;
input [1:0] afi_odt;
input [0:0] afi_ras_n;
input [0:0] afi_we_n;
input [0:0] afi_rst_n;
input [0:0] afi_mem_clk_disable;
input [4:0] afi_dqs_burst;
output [3:0] afi_wlat;
output [4:0] afi_rlat;
// Write data interface
input [79:0] afi_wdata; // write data
input [4:0] afi_wdata_valid; // write data valid, used to maintain write latency required by protocol spec
input [9:0] afi_dm; // write data mask
// Read data interface
output [79:0] afi_rdata; // read data
input [4:0] afi_rdata_en; // read enable, used to maintain the read latency calibrated by PHY
input [4:0] afi_rdata_en_full; // read enable full burst, used to create DQS enable
output [0:0] afi_rdata_valid; // read data valid
// Status interface
output afi_cal_success; // calibration success
output afi_cal_fail; // calibration failure
// Avalon interface to the sequencer
input [15:0] avl_address; //MarkW TODO: the sequencer only uses 13 bits
input avl_read;
output [31:0] avl_readdata;
output avl_waitrequest;
input avl_write;
input [31:0] avl_writedata;
// Configuration interface to the memory controller
input [7:0] cfg_addlat;
input [7:0] cfg_bankaddrwidth;
input [7:0] cfg_caswrlat;
input [7:0] cfg_coladdrwidth;
input [7:0] cfg_csaddrwidth;
input [7:0] cfg_devicewidth;
input [23:0] cfg_dramconfig;
input [7:0] cfg_interfacewidth;
input [7:0] cfg_rowaddrwidth;
input [7:0] cfg_tcl;
input [7:0] cfg_tmrd;
input [15:0] cfg_trefi;
input [7:0] cfg_trfc;
input [7:0] cfg_twr;
// IO/bypass interface to the core (or soft controller)
input [63:0] io_intaddrdout;
input [11:0] io_intbadout;
input [3:0] io_intcasndout;
input [3:0] io_intckdout;
input [7:0] io_intckedout;
input [3:0] io_intckndout;
input [7:0] io_intcsndout;
input [19:0] io_intdmdout;
output [179:0] io_intdqdin;
input [179:0] io_intdqdout;
input [89:0] io_intdqoe;
input [19:0] io_intdqsbdout;
input [9:0] io_intdqsboe;
input [19:0] io_intdqsdout;
input [9:0] io_intdqslogicdqsena;
input [4:0] io_intdqslogicfiforeset;
input [9:0] io_intdqslogicincrdataen;
input [9:0] io_intdqslogicincwrptr;
input [9:0] io_intdqslogicoct;
output [4:0] io_intdqslogicrdatavalid;
input [24:0] io_intdqslogicreadlatency;
input [9:0] io_intdqsoe;
input [7:0] io_intodtdout;
input [3:0] io_intrasndout;
input [3:0] io_intresetndout;
input [3:0] io_intwendout;
output [4:0] io_intafirlat;
output [3:0] io_intafiwlat;
output io_intaficalfail;
output io_intaficalsuccess;
// PHY-Memory Interface
output [MEM_ADDRESS_WIDTH-1:0] mem_a;
output [MEM_BANK_WIDTH-1:0] mem_ba;
output [MEM_IF_CS_WIDTH-1:0] mem_cs_n;
output [MEM_CLK_EN_WIDTH-1:0] mem_cke;
output [MEM_ODT_WIDTH-1:0] mem_odt;
output [MEM_CONTROL_WIDTH-1:0] mem_we_n;
output [MEM_CONTROL_WIDTH-1:0] mem_ras_n;
output [MEM_CONTROL_WIDTH-1:0] mem_cas_n;
output mem_reset_n;
inout [MEM_DQ_WIDTH-1:0] mem_dq;
output [MEM_DM_WIDTH-1:0] mem_dm;
output [MEM_CK_WIDTH-1:0] mem_ck;
output [MEM_CK_WIDTH-1:0] mem_ck_n;
inout [MEM_DQS_WIDTH-1:0] mem_dqs;
inout [MEM_DQS_WIDTH-1:0] mem_dqs_n;
output reset_n_scc_clk;
output reset_n_avl_clk;
// Scan chain configuration manager interface
input scc_data;
input [MEM_READ_DQS_WIDTH-1:0] scc_dqs_ena;
input [MEM_READ_DQS_WIDTH-1:0] scc_dqs_io_ena;
input [MEM_DQ_WIDTH-1:0] scc_dq_ena;
input [MEM_DM_WIDTH-1:0] scc_dm_ena;
input [0:0] scc_upd;
output [MEM_READ_DQS_WIDTH-1:0] capture_strobe_tracking;
output phy_clk;
output ctl_clk;
output phy_reset_n;
// PLL Interface
input pll_afi_clk; // clocks AFI interface logic
input pll_afi_half_clk; //
input pll_addr_cmd_clk; // clocks address/command DDIO
input pll_mem_clk; // output clock to memory
input pll_write_clk; // clocks write data DDIO
input pll_write_clk_pre_phy_clk;
input pll_dqs_ena_clk;
input seq_clk;
input pll_avl_clk;
input pll_config_clk;
input pll_mem_phy_clk;
input pll_afi_phy_clk;
input pll_avl_phy_clk;
// DLL Interface
output dll_clk;
output dll_pll_locked;
input [DLL_DELAY_CTRL_WIDTH-1:0] dll_phy_delayctrl; // dll output used to control the input DQS phase shift
// END PARAMETER SECTION
// ********************************************************************************************************************************
wire [179:0] ddio_phy_dqdin;
wire [4:0] ddio_phy_dqslogic_rdatavalid;
wire [63:0] phy_ddio_address;
wire [11:0] phy_ddio_bank;
wire [3:0] phy_ddio_cas_n;
wire [3:0] phy_ddio_ck;
wire [7:0] phy_ddio_cke;
wire [3:0] phy_ddio_ck_n;
wire [7:0] phy_ddio_cs_n;
wire [19:0] phy_ddio_dmdout;
wire [179:0] phy_ddio_dqdout;
wire [89:0] phy_ddio_dqoe;
wire [9:0] phy_ddio_dqsb_oe;
wire [9:0] phy_ddio_dqslogic_dqsena;
wire [4:0] phy_ddio_dqslogic_fiforeset;
wire [4:0] phy_ddio_dqslogic_aclr_pstamble;
wire [4:0] phy_ddio_dqslogic_aclr_fifoctrl;
wire [9:0] phy_ddio_dqslogic_incrdataen;
wire [9:0] phy_ddio_dqslogic_incwrptr;
wire [9:0] phy_ddio_dqslogic_oct;
wire [24:0] phy_ddio_dqslogic_readlatency;
wire [9:0] phy_ddio_dqs_oe;
wire [19:0] phy_ddio_dqs_dout;
wire [7:0] phy_ddio_odt;
wire [3:0] phy_ddio_ras_n;
wire [3:0] phy_ddio_reset_n;
wire [3:0] phy_ddio_we_n;
wire read_capture_clk;
wire [NUM_AFI_RESET-1:0] reset_n_afi_clk;
wire reset_n_addr_cmd_clk;
wire reset_n_seq_clk;
wire reset_n_scc_clk;
wire reset_n_avl_clk;
wire reset_n_resync_clk;
localparam SKIP_CALIBRATION_STEPS = 7'b1111111;
localparam CALIBRATION_STEPS = SKIP_CALIBRATION_STEPS;
localparam SKIP_MEM_INIT = 1'b1;
localparam SEQ_CALIB_INIT = {CALIBRATION_STEPS, SKIP_MEM_INIT};
generate
if (IS_HHP_HPS != "true") begin
reg [CALIB_REG_WIDTH-1:0] seq_calib_init_reg /* synthesis syn_noprune syn_preserve = 1 */;
// Initialization of the sequencer status register. This register
// is preserved in the netlist so that it can be forced during simulation
always @(posedge pll_afi_clk)
`ifdef SYNTH_FOR_SIM
`else
//synthesis translate_off
`endif
seq_calib_init_reg <= SEQ_CALIB_INIT;
`ifdef SYNTH_FOR_SIM
`else
//synthesis translate_on
//synthesis read_comments_as_HDL on
`endif
// seq_calib_init_reg <= {CALIB_REG_WIDTH{1'b0}};
`ifdef SYNTH_FOR_SIM
`else
// synthesis read_comments_as_HDL off
`endif
end
endgenerate
// ********************************************************************************************************************************
// The reset scheme used in the UNIPHY is asynchronous assert and synchronous de-assert
// The reset block has 2 main functionalities:
// 1. Keep all the PHY logic in reset state until after the PLL is locked
// 2. Synchronize the reset to each clock domain
// ********************************************************************************************************************************
generate
if (IS_HHP_HPS != "true") begin
hps_sdram_p0_reset ureset(
.pll_afi_clk (pll_afi_clk),
.pll_addr_cmd_clk (pll_addr_cmd_clk),
.pll_dqs_ena_clk (pll_dqs_ena_clk),
.seq_clk (seq_clk),
.pll_avl_clk (pll_avl_clk),
.scc_clk (pll_config_clk),
.reset_n_scc_clk (reset_n_scc_clk),
.reset_n_avl_clk (reset_n_avl_clk),
.read_capture_clk (read_capture_clk),
.pll_locked (pll_locked),
.global_reset_n (global_reset_n),
.soft_reset_n (soft_reset_n),
.ctl_reset_export_n (ctl_reset_export_n),
.reset_n_afi_clk (reset_n_afi_clk),
.reset_n_addr_cmd_clk (reset_n_addr_cmd_clk),
.reset_n_seq_clk (reset_n_seq_clk),
.reset_n_resync_clk (reset_n_resync_clk)
);
defparam ureset.MEM_READ_DQS_WIDTH = MEM_READ_DQS_WIDTH;
defparam ureset.NUM_AFI_RESET = NUM_AFI_RESET;
end else begin
// synthesis translate_off
hps_sdram_p0_reset ureset(
.pll_afi_clk (pll_afi_clk),
.pll_addr_cmd_clk (pll_addr_cmd_clk),
.pll_dqs_ena_clk (pll_dqs_ena_clk),
.seq_clk (seq_clk),
.pll_avl_clk (pll_avl_clk),
.scc_clk (pll_config_clk),
.reset_n_scc_clk (reset_n_scc_clk),
.reset_n_avl_clk (reset_n_avl_clk),
.read_capture_clk (read_capture_clk),
.pll_locked (pll_locked),
.global_reset_n (global_reset_n),
.soft_reset_n (soft_reset_n),
.ctl_reset_export_n (ctl_reset_export_n),
.reset_n_afi_clk (reset_n_afi_clk),
.reset_n_addr_cmd_clk (reset_n_addr_cmd_clk),
.reset_n_seq_clk (reset_n_seq_clk),
.reset_n_resync_clk (reset_n_resync_clk)
);
defparam ureset.MEM_READ_DQS_WIDTH = MEM_READ_DQS_WIDTH;
defparam ureset.NUM_AFI_RESET = NUM_AFI_RESET;
// synthesis translate_on
// synthesis read_comments_as_HDL on
// assign reset_n_afi_clk = {NUM_AFI_RESET{global_reset_n}};
// assign reset_n_addr_cmd_clk = global_reset_n;
// assign reset_n_avl_clk = global_reset_n;
// assign reset_n_scc_clk = global_reset_n;
// synthesis read_comments_as_HDL off
end
endgenerate
assign phy_clk = seq_clk;
assign phy_reset_n = reset_n_seq_clk;
assign dll_clk = pll_write_clk_pre_phy_clk;
assign dll_pll_locked = pll_locked;
// PHY clock and LDC
wire afi_clk;
wire avl_clk;
wire adc_clk;
wire adc_clk_cps;
hps_sdram_p0_acv_ldc # (
.DLL_DELAY_CTRL_WIDTH (DLL_DELAY_CTRL_WIDTH),
.ADC_PHASE_SETTING (ADC_PHASE_SETTING),
.ADC_INVERT_PHASE (ADC_INVERT_PHASE),
.IS_HHP_HPS (IS_HHP_HPS)
) memphy_ldc (
.pll_hr_clk (pll_avl_phy_clk),
.pll_dq_clk (pll_write_clk),
.pll_dqs_clk (pll_mem_phy_clk),
.dll_phy_delayctrl (dll_phy_delayctrl),
.afi_clk (afi_clk),
.avl_clk (avl_clk),
.adc_clk (adc_clk),
.adc_clk_cps (adc_clk_cps)
);
assign ctl_clk = afi_clk;
assign afi_reset_n = reset_n_afi_clk;
// ********************************************************************************************************************************
// This is the hard PHY instance
// ********************************************************************************************************************************
cyclonev_mem_phy hphy_inst (
.pllaficlk (afi_clk),
.pllavlclk (avl_clk),
.plllocked (pll_locked),
.plladdrcmdclk (adc_clk),
.globalresetn (global_reset_n),
.softresetn (soft_reset_n),
.phyresetn (phy_reset_n),
.ctlresetn (ctl_reset_n),
.iointaddrdout (io_intaddrdout),
.iointbadout (io_intbadout),
.iointcasndout (io_intcasndout),
.iointckdout (io_intckdout),
.iointckedout (io_intckedout),
.iointckndout (io_intckndout),
.iointcsndout (io_intcsndout),
.iointdmdout (io_intdmdout),
.iointdqdin (io_intdqdin),
.iointdqdout (io_intdqdout),
.iointdqoe (io_intdqoe),
.iointdqsbdout (io_intdqsbdout),
.iointdqsboe (io_intdqsboe),
.iointdqsdout (io_intdqsdout),
.iointdqslogicdqsena (io_intdqslogicdqsena),
.iointdqslogicfiforeset (io_intdqslogicfiforeset),
.iointdqslogicincrdataen (io_intdqslogicincrdataen),
.iointdqslogicincwrptr (io_intdqslogicincwrptr),
.iointdqslogicoct (io_intdqslogicoct),
.iointdqslogicrdatavalid (io_intdqslogicrdatavalid),
.iointdqslogicreadlatency (io_intdqslogicreadlatency),
.iointdqsoe (io_intdqsoe),
.iointodtdout (io_intodtdout),
.iointrasndout (io_intrasndout),
.iointresetndout (io_intresetndout),
.iointwendout (io_intwendout),
.iointafirlat (io_intafirlat),
.iointafiwlat (io_intafiwlat),
.iointaficalfail (io_intaficalfail),
.iointaficalsuccess (io_intaficalsuccess),
.ddiophydqdin (ddio_phy_dqdin),
.ddiophydqslogicrdatavalid (ddio_phy_dqslogic_rdatavalid),
.phyddioaddrdout (phy_ddio_address),
.phyddiobadout (phy_ddio_bank),
.phyddiocasndout (phy_ddio_cas_n),
.phyddiockdout (phy_ddio_ck),
.phyddiockedout (phy_ddio_cke),
.phyddiockndout (),
.phyddiocsndout (phy_ddio_cs_n),
.phyddiodmdout (phy_ddio_dmdout),
.phyddiodqdout (phy_ddio_dqdout),
.phyddiodqoe (phy_ddio_dqoe),
.phyddiodqsbdout (),
.phyddiodqsboe (phy_ddio_dqsb_oe),
.phyddiodqslogicdqsena (phy_ddio_dqslogic_dqsena),
.phyddiodqslogicfiforeset (phy_ddio_dqslogic_fiforeset),
.phyddiodqslogicaclrpstamble (phy_ddio_dqslogic_aclr_pstamble),
.phyddiodqslogicaclrfifoctrl (phy_ddio_dqslogic_aclr_fifoctrl),
.phyddiodqslogicincrdataen (phy_ddio_dqslogic_incrdataen),
.phyddiodqslogicincwrptr (phy_ddio_dqslogic_incwrptr),
.phyddiodqslogicoct (phy_ddio_dqslogic_oct),
.phyddiodqslogicreadlatency (phy_ddio_dqslogic_readlatency),
.phyddiodqsoe (phy_ddio_dqs_oe),
.phyddiodqsdout (phy_ddio_dqs_dout),
.phyddioodtdout (phy_ddio_odt),
.phyddiorasndout (phy_ddio_ras_n),
.phyddioresetndout (phy_ddio_reset_n),
.phyddiowendout (phy_ddio_we_n),
.afiaddr (afi_addr),
.afiba (afi_ba),
.aficalfail (afi_cal_fail),
.aficalsuccess (afi_cal_success),
.aficasn (afi_cas_n),
.aficke (afi_cke),
.aficsn (afi_cs_n),
.afidm (afi_dm),
.afidqsburst (afi_dqs_burst),
.afimemclkdisable (afi_mem_clk_disable),
.afiodt (afi_odt),
.afirasn (afi_ras_n),
.afirdata (afi_rdata),
.afirdataen (afi_rdata_en),
.afirdataenfull (afi_rdata_en_full),
.afirdatavalid (afi_rdata_valid),
.afirlat (afi_rlat),
.afirstn (afi_rst_n),
.afiwdata (afi_wdata),
.afiwdatavalid (afi_wdata_valid),
.afiwen (afi_we_n),
.afiwlat (afi_wlat),
.avladdress (avl_address),
.avlread (avl_read),
.avlreaddata (avl_readdata),
.avlresetn (reset_n_avl_clk),
.avlwaitrequest (avl_waitrequest),
.avlwrite (avl_write),
.avlwritedata (avl_writedata),
.cfgaddlat (cfg_addlat),
.cfgbankaddrwidth (cfg_bankaddrwidth),
.cfgcaswrlat (cfg_caswrlat),
.cfgcoladdrwidth (cfg_coladdrwidth),
.cfgcsaddrwidth (cfg_csaddrwidth),
.cfgdevicewidth (cfg_devicewidth),
.cfgdramconfig (cfg_dramconfig),
.cfginterfacewidth (cfg_interfacewidth),
.cfgrowaddrwidth (cfg_rowaddrwidth),
.cfgtcl (cfg_tcl),
.cfgtmrd (cfg_tmrd),
.cfgtrefi (cfg_trefi),
.cfgtrfc (cfg_trfc),
.cfgtwr (cfg_twr),
.scanen ()
);
defparam hphy_inst.hphy_ac_ddr_disable = "true";
defparam hphy_inst.hphy_datapath_delay = "one_cycle";
defparam hphy_inst.hphy_datapath_ac_delay = "one_and_half_cycles";
defparam hphy_inst.hphy_reset_delay_en = "false";
defparam hphy_inst.m_hphy_ac_rom_init_file = AC_ROM_INIT_FILE_NAME;
defparam hphy_inst.m_hphy_inst_rom_init_file = INST_ROM_INIT_FILE_NAME;
defparam hphy_inst.hphy_wrap_back_en = "false";
defparam hphy_inst.hphy_atpg_en = "false";
defparam hphy_inst.hphy_use_hphy = "true";
defparam hphy_inst.hphy_csr_pipelineglobalenable = "true";
defparam hphy_inst.hphy_hhp_hps = IS_HHP_HPS;
// ********************************************************************************************************************************
// The I/O block is responsible for instantiating all the built-in I/O logic in the FPGA
// ********************************************************************************************************************************
hps_sdram_p0_acv_hard_io_pads #(
.DEVICE_FAMILY(DEVICE_FAMILY),
.FAST_SIM_MODEL(FAST_SIM_MODEL),
.OCT_SERIES_TERM_CONTROL_WIDTH(OCT_SERIES_TERM_CONTROL_WIDTH),
.OCT_PARALLEL_TERM_CONTROL_WIDTH(OCT_PARALLEL_TERM_CONTROL_WIDTH),
.MEM_ADDRESS_WIDTH(MEM_ADDRESS_WIDTH),
.MEM_BANK_WIDTH(MEM_BANK_WIDTH),
.MEM_CHIP_SELECT_WIDTH(MEM_IF_CS_WIDTH),
.MEM_CLK_EN_WIDTH(MEM_CLK_EN_WIDTH),
.MEM_CK_WIDTH(MEM_CK_WIDTH),
.MEM_ODT_WIDTH(MEM_ODT_WIDTH),
.MEM_DQS_WIDTH(MEM_DQS_WIDTH),
.MEM_DM_WIDTH(MEM_DM_WIDTH),
.MEM_CONTROL_WIDTH(MEM_CONTROL_WIDTH),
.MEM_DQ_WIDTH(MEM_DQ_WIDTH),
.MEM_READ_DQS_WIDTH(MEM_READ_DQS_WIDTH),
.MEM_WRITE_DQS_WIDTH(MEM_WRITE_DQS_WIDTH),
.DLL_DELAY_CTRL_WIDTH(DLL_DELAY_CTRL_WIDTH),
.ADC_PHASE_SETTING(ADC_PHASE_SETTING),
.ADC_INVERT_PHASE(ADC_INVERT_PHASE),
.IS_HHP_HPS(IS_HHP_HPS)
) uio_pads (
.reset_n_addr_cmd_clk (reset_n_addr_cmd_clk),
.reset_n_afi_clk (reset_n_afi_clk[1]),
.oct_ctl_rs_value (oct_ctl_rs_value),
.oct_ctl_rt_value (oct_ctl_rt_value),
.phy_ddio_address (phy_ddio_address),
.phy_ddio_bank (phy_ddio_bank),
.phy_ddio_cs_n (phy_ddio_cs_n),
.phy_ddio_cke (phy_ddio_cke),
.phy_ddio_odt (phy_ddio_odt),
.phy_ddio_we_n (phy_ddio_we_n),
.phy_ddio_ras_n (phy_ddio_ras_n),
.phy_ddio_cas_n (phy_ddio_cas_n),
.phy_ddio_ck (phy_ddio_ck),
.phy_ddio_reset_n (phy_ddio_reset_n),
.phy_mem_address (mem_a),
.phy_mem_bank (mem_ba),
.phy_mem_cs_n (mem_cs_n),
.phy_mem_cke (mem_cke),
.phy_mem_odt (mem_odt),
.phy_mem_we_n (mem_we_n),
.phy_mem_ras_n (mem_ras_n),
.phy_mem_cas_n (mem_cas_n),
.phy_mem_reset_n (mem_reset_n),
.pll_afi_clk (pll_afi_clk),
.pll_mem_clk (pll_mem_clk),
.pll_afi_phy_clk (pll_afi_phy_clk),
.pll_avl_phy_clk (pll_avl_phy_clk),
.pll_avl_clk (pll_avl_clk),
.avl_clk (avl_clk),
.pll_mem_phy_clk (pll_mem_phy_clk),
.pll_write_clk (pll_write_clk),
.pll_dqs_ena_clk (pll_dqs_ena_clk),
.pll_addr_cmd_clk (adc_clk_cps),
.phy_mem_dq (mem_dq),
.phy_mem_dm (mem_dm),
.phy_mem_ck (mem_ck),
.phy_mem_ck_n (mem_ck_n),
.mem_dqs (mem_dqs),
.mem_dqs_n (mem_dqs_n),
.dll_phy_delayctrl (dll_phy_delayctrl),
.scc_clk (pll_config_clk),
.scc_data (scc_data),
.scc_dqs_ena (scc_dqs_ena),
.scc_dqs_io_ena (scc_dqs_io_ena),
.scc_dq_ena (scc_dq_ena),
.scc_dm_ena (scc_dm_ena),
.scc_upd (scc_upd[0]),
.phy_ddio_dmdout (phy_ddio_dmdout),
.phy_ddio_dqdout (phy_ddio_dqdout),
.phy_ddio_dqs_oe (phy_ddio_dqs_oe),
.phy_ddio_dqsdout (phy_ddio_dqs_dout),
.phy_ddio_dqsb_oe (phy_ddio_dqsb_oe),
.phy_ddio_dqslogic_oct (phy_ddio_dqslogic_oct),
.phy_ddio_dqslogic_fiforeset (phy_ddio_dqslogic_fiforeset),
.phy_ddio_dqslogic_aclr_pstamble (phy_ddio_dqslogic_aclr_pstamble),
.phy_ddio_dqslogic_aclr_fifoctrl (phy_ddio_dqslogic_aclr_fifoctrl),
.phy_ddio_dqslogic_incwrptr (phy_ddio_dqslogic_incwrptr),
.phy_ddio_dqslogic_readlatency (phy_ddio_dqslogic_readlatency),
.ddio_phy_dqslogic_rdatavalid (ddio_phy_dqslogic_rdatavalid),
.ddio_phy_dqdin (ddio_phy_dqdin),
.phy_ddio_dqslogic_incrdataen (phy_ddio_dqslogic_incrdataen),
.phy_ddio_dqslogic_dqsena (phy_ddio_dqslogic_dqsena),
.phy_ddio_dqoe (phy_ddio_dqoe),
.capture_strobe_tracking (capture_strobe_tracking)
);
generate
if (IS_HHP_HPS != "true") begin
reg afi_clk_reg /* synthesis dont_merge syn_noprune syn_preserve = 1 */;
always @(posedge pll_afi_clk)
afi_clk_reg <= ~afi_clk_reg;
reg afi_half_clk_reg /* synthesis dont_merge syn_noprune syn_preserve = 1 */;
always @(posedge pll_afi_half_clk)
afi_half_clk_reg <= ~afi_half_clk_reg;
reg avl_clk_reg /* synthesis dont_merge syn_noprune syn_preserve = 1 */;
always @(posedge pll_avl_clk)
avl_clk_reg <= ~avl_clk_reg;
reg config_clk_reg /* synthesis dont_merge syn_noprune syn_preserve = 1 */;
always @(posedge pll_config_clk)
config_clk_reg <= ~config_clk_reg;
end
endgenerate
// Calculate the ceiling of log_2 of the input value
function integer ceil_log2;
input integer value;
begin
value = value - 1;
for (ceil_log2 = 0; value > 0; ceil_log2 = ceil_log2 + 1)
value = value >> 1;
end
endfunction
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__TAP_TB_V
`define SKY130_FD_SC_HDLL__TAP_TB_V
/**
* tap: Tap cell with no tap connections (no contacts on metal1).
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__tap.v"
module top();
// Inputs are registered
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
initial
begin
// Initial state is x for all inputs.
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 VGND = 1'b0;
#40 VNB = 1'b0;
#60 VPB = 1'b0;
#80 VPWR = 1'b0;
#100 VGND = 1'b1;
#120 VNB = 1'b1;
#140 VPB = 1'b1;
#160 VPWR = 1'b1;
#180 VGND = 1'b0;
#200 VNB = 1'b0;
#220 VPB = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VPB = 1'b1;
#300 VNB = 1'b1;
#320 VGND = 1'b1;
#340 VPWR = 1'bx;
#360 VPB = 1'bx;
#380 VNB = 1'bx;
#400 VGND = 1'bx;
end
sky130_fd_sc_hdll__tap dut (.VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__TAP_TB_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer _mode; initial _mode=0;
reg [7:0] a;
reg [7:0] b;
reg [7:0] c;
reg [7:0] mode_d1r;
reg [7:0] mode_d2r;
reg [7:0] mode_d3r;
// surefire lint_off ITENST
// surefire lint_off STMINI
// surefire lint_off NBAJAM
always @ (posedge clk) begin // filp-flops with asynchronous reset
if (0) begin
_mode <= 0;
end
else begin
_mode <= _mode + 1;
if (_mode==0) begin
$write("[%0t] t_blocking: Running\n", $time);
a <= 8'd0;
b <= 8'd0;
c <= 8'd0;
end
else if (_mode==1) begin
if (a !== 8'd0) $stop;
if (b !== 8'd0) $stop;
if (c !== 8'd0) $stop;
a <= b;
b <= 8'd1;
c <= b;
if (a !== 8'd0) $stop;
if (b !== 8'd0) $stop;
if (c !== 8'd0) $stop;
end
else if (_mode==2) begin
if (a !== 8'd0) $stop;
if (b !== 8'd1) $stop;
if (c !== 8'd0) $stop;
a <= b;
b <= 8'd2;
c <= b;
if (a !== 8'd0) $stop;
if (b !== 8'd1) $stop;
if (c !== 8'd0) $stop;
end
else if (_mode==3) begin
if (a !== 8'd1) $stop;
if (b !== 8'd2) $stop;
if (c !== 8'd1) $stop;
end
else if (_mode==4) begin
if (mode_d3r != 8'd1) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
always @ (posedge clk) begin
mode_d3r <= mode_d2r;
mode_d2r <= mode_d1r;
mode_d1r <= _mode[7:0];
end
reg [14:10] bits;
// surefire lint_off SEQASS
always @ (posedge clk) begin
if (_mode==1) begin
bits[14:13] <= 2'b11;
bits[12] <= 1'b1;
end
if (_mode==2) begin
bits[11:10] <= 2'b10;
bits[13] <= 0;
end
if (_mode==3) begin
if (bits !== 5'b10110) $stop;
end
end
endmodule
|
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <[email protected]>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
// Input buffer map
module \$__inpad (input I, output O);
twentynm_io_ibuf _TECHMAP_REPLACE_ (.o(O), .i(I), .ibar(1'b0));
endmodule
// Output buffer map
module \$__outpad (input I, output O);
twentynm_io_obuf _TECHMAP_REPLACE_ (.o(O), .i(I), .oe(1'b1));
endmodule
// LUT Map
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
input [WIDTH-1:0] A;
output Y;
generate
if (WIDTH == 1) begin
assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function
end else
if (WIDTH == 2) begin
twentynm_lcell_comb #(.lut_mask({16{LUT}}), .shared_arith("off"), .extended_lut("off"))
_TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(1'b1),.datad(1'b1), .datae(1'b1), .dataf(1'b1), .datag(1'b1));
end /*else
if(WIDTH == 3) begin
fiftyfivenm_lcell_comb #(.lut_mask({2{LUT}}), .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(A[2]),.datad(1'b1));
end else
if(WIDTH == 4) begin
fiftyfivenm_lcell_comb #(.lut_mask(LUT), .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(A[2]),.datad(A[3]));
end*/ else
wire _TECHMAP_FAIL_ = 1;
endgenerate
endmodule //
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003,2004 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
// Serial Control Bus from Cypress chip
module serial_io
( input master_clk,
input serial_clock,
input serial_data_in,
input enable,
input reset,
inout wire serial_data_out,
output reg [6:0] serial_addr,
output reg [31:0] serial_data,
output wire serial_strobe,
input wire [31:0] readback_0,
input wire [31:0] readback_1,
input wire [31:0] readback_2,
input wire [31:0] readback_3,
input wire [31:0] readback_4,
input wire [31:0] readback_5,
input wire [31:0] readback_6,
input wire [31:0] readback_7
);
reg is_read;
reg [7:0] ser_ctr;
reg write_done;
assign serial_data_out = is_read ? serial_data[31] : 1'bz;
always @(posedge serial_clock, posedge reset, negedge enable)
if(reset)
ser_ctr <= #1 8'd0;
else if(~enable)
ser_ctr <= #1 8'd0;
else if(ser_ctr == 39)
ser_ctr <= #1 8'd0;
else
ser_ctr <= #1 ser_ctr + 8'd1;
always @(posedge serial_clock, posedge reset, negedge enable)
if(reset)
is_read <= #1 1'b0;
else if(~enable)
is_read <= #1 1'b0;
else if((ser_ctr == 7)&&(serial_addr[6]==1))
is_read <= #1 1'b1;
always @(posedge serial_clock, posedge reset)
if(reset)
begin
serial_addr <= #1 7'b0;
serial_data <= #1 32'b0;
write_done <= #1 1'b0;
end
else if(~enable)
begin
//serial_addr <= #1 7'b0;
//serial_data <= #1 32'b0;
write_done <= #1 1'b0;
end
else
begin
if(~is_read && (ser_ctr == 39))
write_done <= #1 1'b1;
else
write_done <= #1 1'b0;
if(is_read & (ser_ctr==8))
case (serial_addr)
7'd1: serial_data <= #1 readback_0;
7'd2: serial_data <= #1 readback_1;
7'd3: serial_data <= #1 readback_2;
7'd4: serial_data <= #1 readback_3;
7'd5: serial_data <= #1 readback_4;
7'd6: serial_data <= #1 readback_5;
7'd7: serial_data <= #1 readback_6;
7'd8: serial_data <= #1 readback_7;
default: serial_data <= #1 32'd0;
endcase // case(serial_addr)
else if(ser_ctr >= 8)
serial_data <= #1 {serial_data[30:0],serial_data_in};
else if(ser_ctr < 8)
serial_addr <= #1 {serial_addr[5:0],serial_data_in};
end // else: !if(~enable)
reg enable_d1, enable_d2;
always @(posedge master_clk)
begin
enable_d1 <= #1 enable;
enable_d2 <= #1 enable_d1;
end
assign serial_strobe = enable_d2 & ~enable_d1;
endmodule // serial_io
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axis_data_fifo:1.1
// IP Revision: 10
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_axis_data_fifo_0_0 (
s_axis_aresetn,
s_axis_aclk,
s_axis_tvalid,
s_axis_tready,
s_axis_tdata,
m_axis_tvalid,
m_axis_tready,
m_axis_tdata,
axis_data_count,
axis_wr_data_count,
axis_rd_data_count
);
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 S_RSTIF RST" *)
input wire s_axis_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 S_CLKIF CLK" *)
input wire s_axis_aclk;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TVALID" *)
input wire s_axis_tvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TREADY" *)
output wire s_axis_tready;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TDATA" *)
input wire [39 : 0] s_axis_tdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TVALID" *)
output wire m_axis_tvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TREADY" *)
input wire m_axis_tready;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TDATA" *)
output wire [39 : 0] m_axis_tdata;
output wire [31 : 0] axis_data_count;
output wire [31 : 0] axis_wr_data_count;
output wire [31 : 0] axis_rd_data_count;
axis_data_fifo_v1_1_10_axis_data_fifo #(
.C_FAMILY("zynq"),
.C_AXIS_TDATA_WIDTH(40),
.C_AXIS_TID_WIDTH(1),
.C_AXIS_TDEST_WIDTH(1),
.C_AXIS_TUSER_WIDTH(1),
.C_AXIS_SIGNAL_SET('B00000000000000000000000000000011),
.C_FIFO_DEPTH(1024),
.C_FIFO_MODE(1),
.C_IS_ACLK_ASYNC(0),
.C_SYNCHRONIZER_STAGE(2),
.C_ACLKEN_CONV_MODE(0)
) inst (
.s_axis_aresetn(s_axis_aresetn),
.m_axis_aresetn(1'H0),
.s_axis_aclk(s_axis_aclk),
.s_axis_aclken(1'H1),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tdata(s_axis_tdata),
.s_axis_tstrb(5'H1F),
.s_axis_tkeep(5'H1F),
.s_axis_tlast(1'H1),
.s_axis_tid(1'H0),
.s_axis_tdest(1'H0),
.s_axis_tuser(1'H0),
.m_axis_aclk(1'H0),
.m_axis_aclken(1'H1),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tdata(m_axis_tdata),
.m_axis_tstrb(),
.m_axis_tkeep(),
.m_axis_tlast(),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(),
.axis_data_count(axis_data_count),
.axis_wr_data_count(axis_wr_data_count),
.axis_rd_data_count(axis_rd_data_count)
);
endmodule
|
/*****************************************************************************
* *
* Module: Altera_UP_Avalon_RS232 *
* Description: *
* This module reads and writes data to the RS232 connector on Altera's *
* DE1 and DE2 Development and Education Boards. *
* *
*****************************************************************************/
/* Settings */
`define USE_DATA_WIDTH_8 1
/* End settings */
module Altera_UP_Avalon_RS232 (
// Inputs
clk,
reset,
address,
chipselect,
byteenable,
read,
write,
writedata,
UART_RXD,
// Bidirectionals
// Outputs
irq,
readdata,
UART_TXD
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter BAUD_COUNTER_WIDTH = 9;
parameter BAUD_TICK_INCREMENT = 9'd1;
parameter BAUD_TICK_COUNT = 9'd433;
parameter HALF_BAUD_TICK_COUNT = 9'd216;
parameter TOTAL_DATA_WIDTH = 10;
parameter DATA_WIDTH = 8;
parameter ODD_PARITY = 1'b0;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input address;
input chipselect;
input [3:0] byteenable;
input read;
input write;
input [31:0] writedata;
input UART_RXD;
// Bidirectionals
// Outputs
output reg irq;
output reg [31:0] readdata;
output UART_TXD;
/*****************************************************************************
* Internal wires and registers Declarations *
*****************************************************************************/
// Internal Wires
wire read_fifo_read_en;
wire [7:0] read_available;
`ifdef USE_PARITY
wire [DATA_WIDTH:0] read_data;
`else
wire [(DATA_WIDTH - 1):0] read_data;
`endif
wire parity_error;
wire write_data_parity;
wire [7:0] write_space;
// Internal Registers
reg read_interrupt_en;
reg write_interrupt_en;
reg read_interrupt;
reg write_interrupt;
reg write_fifo_write_en;
reg [(DATA_WIDTH - 1):0] data_to_uart;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential logic *
*****************************************************************************/
always @(posedge clk)
begin
if (reset == 1'b1)
irq <= 1'b0;
else
irq <= write_interrupt | read_interrupt;
end
always @(posedge clk)
begin
if (reset == 1'b1)
readdata <= 32'h00000000;
else if (chipselect == 1'b1)
begin
if (address == 1'b0)
readdata <=
{8'h00,
read_available,
6'h00,
parity_error,
`ifdef USE_DATA_WIDTH_7
2'h0,
`endif
`ifdef USE_DATA_WIDTH_8
1'b0,
`endif
read_data[(DATA_WIDTH - 1):0]};
else
readdata <=
{8'h00,
write_space,
6'h00,
write_interrupt,
read_interrupt,
6'h00,
write_interrupt_en,
read_interrupt_en};
end
end
always @(posedge clk)
begin
if (reset == 1'b1)
read_interrupt_en <= 1'b0;
else if ((chipselect == 1'b1) && (write == 1'b1) && (address == 1'b1) && (byteenable[0] == 1'b1))
read_interrupt_en <= writedata[0];
end
always @(posedge clk)
begin
if (reset == 1'b1)
write_interrupt_en <= 1'b0;
else if ((chipselect == 1'b1) && (write == 1'b1) && (address == 1'b1) && (byteenable[0] == 1'b1))
write_interrupt_en <= writedata[1];
end
always @(posedge clk)
begin
if (reset == 1'b1)
read_interrupt <= 1'b0;
else if (read_interrupt_en == 1'b0)
read_interrupt <= 1'b0;
else
read_interrupt <= (|read_available);
end
always @(posedge clk)
begin
if (reset == 1'b1)
write_interrupt <= 1'b0;
else if (write_interrupt_en == 1'b0)
write_interrupt <= 1'b0;
else
write_interrupt <= (&(write_space[6:5]) | write_space[7]);
end
always @(posedge clk)
begin
if (reset == 1'b1)
write_fifo_write_en <= 1'b0;
else
write_fifo_write_en <=
chipselect & write & ~address & byteenable[0];
end
always @(posedge clk)
begin
if (reset == 1'b1)
data_to_uart <= 1'b0;
else
data_to_uart <= writedata[(DATA_WIDTH - 1):0];
end
/*****************************************************************************
* Combinational logic *
*****************************************************************************/
`ifdef USE_PARITY
assign parity_error = (read_available != 8'h00) ?
((^(read_data[DATA_WIDTH:0])) ^ ODD_PARITY) :
1'b0;
`else
assign parity_error = 1'b0;
`endif
assign read_fifo_read_en = chipselect & read & ~address & byteenable[0];
assign write_data_parity = (^(data_to_uart)) ^ ODD_PARITY;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
Altera_UP_RS232_In_Deserializer RS232_In_Deserializer (
// Inputs
.clk (clk),
.reset (reset),
.serial_data_in (UART_RXD),
.receive_data_en (read_fifo_read_en),
// Bidirectionals
// Outputs
.fifo_read_available (read_available),
.received_data (read_data)
);
defparam
RS232_In_Deserializer.BAUD_COUNTER_WIDTH = BAUD_COUNTER_WIDTH,
RS232_In_Deserializer.BAUD_TICK_INCREMENT = BAUD_TICK_INCREMENT,
RS232_In_Deserializer.BAUD_TICK_COUNT = BAUD_TICK_COUNT,
RS232_In_Deserializer.HALF_BAUD_TICK_COUNT = HALF_BAUD_TICK_COUNT,
RS232_In_Deserializer.TOTAL_DATA_WIDTH = TOTAL_DATA_WIDTH,
`ifdef USE_PARITY
RS232_In_Deserializer.DATA_WIDTH = (DATA_WIDTH + 1);
`else
RS232_In_Deserializer.DATA_WIDTH = DATA_WIDTH;
`endif
Altera_UP_RS232_Out_Serializer RS232_Out_Serializer (
// Inputs
.clk (clk),
.reset (reset),
`ifdef USE_PARITY
.transmit_data ({write_data_parity, data_to_uart}),
`else
.transmit_data (data_to_uart),
`endif
.transmit_data_en (write_fifo_write_en),
// Bidirectionals
// Outputs
.fifo_write_space (write_space),
.serial_data_out (UART_TXD)
);
defparam
RS232_Out_Serializer.BAUD_COUNTER_WIDTH = BAUD_COUNTER_WIDTH,
RS232_Out_Serializer.BAUD_TICK_INCREMENT = BAUD_TICK_INCREMENT,
RS232_Out_Serializer.BAUD_TICK_COUNT = BAUD_TICK_COUNT,
RS232_Out_Serializer.HALF_BAUD_TICK_COUNT = HALF_BAUD_TICK_COUNT,
RS232_Out_Serializer.TOTAL_DATA_WIDTH = TOTAL_DATA_WIDTH,
`ifdef USE_PARITY
RS232_Out_Serializer.DATA_WIDTH = (DATA_WIDTH + 1);
`else
RS232_Out_Serializer.DATA_WIDTH = DATA_WIDTH;
`endif
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : PCIeGen2x8If128_pipe_wrapper.v
// Version : 3.2
//------------------------------------------------------------------------------
// Filename : pipe_wrapper.v
// Description : PIPE Wrapper for 7 Series Transceiver
// Version : 20.2
//------------------------------------------------------------------------------
//---------- PIPE Wrapper Hierarchy --------------------------------------------
// pipe_wrapper.v
// pipe_clock.v
// pipe_reset.v or gtp_pipe_reset.v
// qpll_reset.v
// * Generate GTXE2_CHANNEL for every lane.
// pipe_user.v
// pipe_rate.v or gtp_pipe_rate.v
// pipe_sync.v
// pipe_drp.v or gtp_pipe_drp.v
// pipe_eq.v
// rxeq_scan.v
// gt_wrapper.v
// GTXE2_CHANNEL or GTHE2_CHANNEL or GTPE2_CHANNEL
// GTXE2_COMMON or GTHE2_COMMON or GTPE2_CHANNEL
// * Generate GTXE2_COMMON for every quad.
// qpll_drp.v
// qpll_wrapper.v
//------------------------------------------------------------------------------
//---------- PIPE Wrapper Parameter Encoding -----------------------------------
// PCIE_SIM_MODE : "FALSE" = Normal mode (default)
// : "TRUE" = Simulation only
// PCIE_SIM_TX_EIDLE_DRIVE_LEVEL : "0", "1" (default), "X" simulation TX electrical idle drive level
// PCIE_GT_DEVICE : "GTX" (default)
// : "GTH"
// : "GTP"
// PCIE_USE_MODE : "1.0" = GTX IES 325T or GTP IES/GES use mode.
// : "1.1" = GTX IES 485T use mode.
// : "2.0" = GTH IES 690T use mode for 1.0 silicon.
// : "2.1" = GTH GES 690T use mode for 1.2 and 2.0 silicon. SW model use "2.0"
// : "3.0" = GTX GES 325T or 485T use mode (default).
// PCIE_PLL_SEL : "CPLL" (default)
// : "QPLL"
// PCIE_AUX_CDR_GEN3_EN : "FALSE" Use Primary CDR for Gen3 only (GTH 2.0)
// : "TRUE" Use AUX CDR for Gen3 only (default) (GTH 2.0)
// PCIE_LPM_DFE : "DFE" for Gen1/Gen2 only (GTX, GTH)
// : "LPM" for Gen1/Gen2 only (default) (GTX, GTH)
// PCIE_LPM_DFE_GEN3 : "DFE" for Gen3 only (GTX, GTH)
// : "LPM" for Gen3 only (default) (GTX, GTH)
// PCIE_EXT_CLK : "FALSE" = Use internal clock module(default)
// : "TRUE" = Use external clock module
// PCIE_POWER_SAVING : "FALSE" = Disable PLL power saving
// : "TRUE" = Enable PLL power saving (default)
// PCIE_ASYNC_EN : "FALSE" = Synchronous mode (default)
// : "TRUE" = Asynchronous mode.
// PCIE_TXBUF_EN : "FALSE" = TX buffer bypass for Gen1/Gen2 only (default)
// : "TRUE" = TX buffer use for Gen1/Gen2 only (for debug only)
// PCIE_RXBUF_EN : "FALSE" = RX buffer bypass for Gen3 only (not supported)
// : "TRUE" = RX buffer use for Gen3 only (default)
// PCIE_TXSYNC_MODE : 0 = Manual TX sync (default) (GTX, GTH)
// : 1 = Auto TX sync (GTH)
// PCIE_RXSYNC_MODE : 0 = Manual RX sync (default) (GTX, GTH)
// : 1 = Auto RX sync (GTH)
// PCIE_CHAN_BOND : 0 = One-Hop (default)
// : 1 = Daisy-Chain
// : 2 = Binary-Tree
// PCIE_CHAN_BOND_EN : "FALSE" = Channel bonding disable for Gen1/Gen2 only
// : "TRUE" = Channel bonding enable for Gen1/Gen2 only
// PCIE_LANE : 1 (default), 2, 4, or 8
// PCIE_LINK_SPEED : 1 = PCIe Gen1 Mode
// : 2 = PCIe Gen1/Gen2 Mode (default)
// : 3 = PCIe Gen1/Gen2/Gen3 Mode
// PCIE_REFCLK_FREQ : 0 = 100 MHz (default)
// : 1 = 125 MHz
// : 2 = 250 MHz
// PCIE_USERCLK[1/2]_FREQ : 0 = Disable user clock
// : 1 = 31.25 MHz
// : 2 = 62.50 MHz (default)
// : 3 = 125.00 MHz
// : 4 = 250.00 MHz
// : 5 = 500.00 MHz
// PCIE_TX_EIDLE_ASSERT_DELAY : 3'd0 to 3'd7 (default = 3'd4)
// PCIE_RXEQ_MODE_GEN3 : 0 = Return same TX coefficients
// : 1 = Return TX preset #5
// PCIE_OOBCLK_MODE : 0 = Reference clock
// : 1 = 62.50 MHz (default)
// : 2 = 50.00 MHz (requires 1 BUFG)
// PCIE_JTAG_MODE : 0 = Normal operation (default)
// : 1 = JTAG mode (for debug only)
// PCIE_DEBUG_MODE : 0 = Normal operation (default)
// : 1 = Debug mode (for debug only)
//------------------------------------------------------------------------------
//---------- Notes -------------------------------------------------------------
// Notes within the PIPE Wrapper RTL files are for internal use only.
// Data Width : This PIPE Wrapper supports a 32-bit [TX/RX]DATA interface.
// In Gen1/Gen2 modes, only 16-bits [15:0] are used.
// In Gen3 mode, all 32-bits are used.
//------------------------------------------------------------------------------
`timescale 1ns / 1ps
//---------- PIPE Wrapper ------------------------------------------------------
(* DowngradeIPIdentifiedWarnings = "yes" *)
module PCIeGen2x8If128_pipe_wrapper #
(
parameter PCIE_SIM_MODE = "FALSE", // PCIe sim mode
parameter PCIE_SIM_SPEEDUP = "FALSE", // PCIe sim speedup
parameter PCIE_SIM_TX_EIDLE_DRIVE_LEVEL = "1", // PCIe sim TX electrical idle drive level
parameter PCIE_GT_DEVICE = "GTX", // PCIe GT device
parameter PCIE_USE_MODE = "3.0", // PCIe use mode
parameter PCIE_PLL_SEL = "CPLL", // PCIe PLL select for Gen1/Gen2 (GTX/GTH) only
parameter PCIE_AUX_CDR_GEN3_EN = "TRUE", // PCIe AUX CDR for Gen3 (GTH 2.0) only
parameter PCIE_LPM_DFE = "LPM", // PCIe LPM or DFE mode for Gen1/Gen2 only
parameter PCIE_LPM_DFE_GEN3 = "DFE", // PCIe LPM or DFE mode for Gen3 only
parameter PCIE_EXT_CLK = "FALSE", // PCIe external clock
parameter PCIE_EXT_GT_COMMON = "FALSE", // PCIe external GT COMMON
parameter EXT_CH_GT_DRP = "FALSE", // PCIe external CH DRP
parameter TX_MARGIN_FULL_0 = 7'b1001111, // 1000 mV
parameter TX_MARGIN_FULL_1 = 7'b1001110, // 950 mV
parameter TX_MARGIN_FULL_2 = 7'b1001101, // 900 mV
parameter TX_MARGIN_FULL_3 = 7'b1001100, // 850 mV
parameter TX_MARGIN_FULL_4 = 7'b1000011, // 400 mV
parameter TX_MARGIN_LOW_0 = 7'b1000101, // 500 mV
parameter TX_MARGIN_LOW_1 = 7'b1000110 , // 450 mV
parameter TX_MARGIN_LOW_2 = 7'b1000011, // 400 mV
parameter TX_MARGIN_LOW_3 = 7'b1000010 , // 350 mV
parameter TX_MARGIN_LOW_4 = 7'b1000000 ,
parameter PCIE_POWER_SAVING = "TRUE", // PCIe power saving
parameter PCIE_ASYNC_EN = "FALSE", // PCIe async enable
parameter PCIE_TXBUF_EN = "FALSE", // PCIe TX buffer enable for Gen1/Gen2 only
parameter PCIE_RXBUF_EN = "TRUE", // PCIe RX buffer enable for Gen3 only
parameter PCIE_TXSYNC_MODE = 0, // PCIe TX sync mode
parameter PCIE_RXSYNC_MODE = 0, // PCIe RX sync mode
parameter PCIE_CHAN_BOND = 0, // PCIe channel bonding mode
parameter PCIE_CHAN_BOND_EN = "TRUE", // PCIe channel bonding enable for Gen1/Gen2 only
parameter PCIE_LANE = 8, // PCIe number of lanes
parameter PCIE_LINK_SPEED = 2, // PCIe link speed
parameter PCIE_REFCLK_FREQ = 0, // PCIe reference clock frequency
parameter PCIE_USERCLK1_FREQ = 5, // PCIe user clock 1 frequency
parameter PCIE_USERCLK2_FREQ = 4, // PCIe user clock 2 frequency
parameter PCIE_TX_EIDLE_ASSERT_DELAY = 3'd2, // PCIe TX electrical idle assert delay
parameter PCIE_RXEQ_MODE_GEN3 = 1, // PCIe RX equalization mode
parameter PCIE_OOBCLK_MODE = 1, // PCIe OOB clock mode
parameter PCIE_JTAG_MODE = 0, // PCIe JTAG mode
parameter PCIE_DEBUG_MODE = 0 // PCIe debug mode
)
//--------------------------------------
( // Gen1/Gen2 | Gen3
//--------------------------------------
//---------- PIPE Clock & Reset Ports ------------------
input PIPE_CLK, // Reference clock that drives MMCM
input PIPE_RESET_N, // PCLK | PCLK
output PIPE_PCLK, // Drives [TX/RX]USRCLK in Gen1/Gen2
// Drives TXUSRCLK in Gen3
// Drives RXUSRCLK in Gen3 async mode only
//---------- PIPE TX Data Ports ------------------------
input [(PCIE_LANE*32)-1:0]PIPE_TXDATA, // PCLK | PCLK
input [(PCIE_LANE*4)-1:0] PIPE_TXDATAK, // PCLK | PCLK
output [PCIE_LANE-1:0] PIPE_TXP, // Serial data
output [PCIE_LANE-1:0] PIPE_TXN, // Serial data
//---------- PIPE RX Data Ports ------------------------
input [PCIE_LANE-1:0] PIPE_RXP, // Serial data
input [PCIE_LANE-1:0] PIPE_RXN, // Serial data
output [(PCIE_LANE*32)-1:0]PIPE_RXDATA, // PCLK | RXUSRCLK
output [(PCIE_LANE*4)-1:0] PIPE_RXDATAK, // PCLK | RXUSRCLK
//---------- PIPE Command Ports ------------------------
input PIPE_TXDETECTRX, // PCLK | PCLK
input [PCIE_LANE-1:0] PIPE_TXELECIDLE, // PCLK | PCLK
input [PCIE_LANE-1:0] PIPE_TXCOMPLIANCE, // PCLK | PCLK
input [PCIE_LANE-1:0] PIPE_RXPOLARITY, // PCLK | RXUSRCLK
input [(PCIE_LANE*2)-1:0] PIPE_POWERDOWN, // PCLK | PCLK
input [ 1:0] PIPE_RATE, // PCLK | PCLK
//---------- PIPE Electrical Command Ports -------------
input [ 2:0] PIPE_TXMARGIN, // Async | Async
input PIPE_TXSWING, // Async | Async
input [PCIE_LANE-1:0] PIPE_TXDEEMPH, // Async/PCLK | Async/PCLK
input [(PCIE_LANE*2)-1:0] PIPE_TXEQ_CONTROL, // PCLK | PCLK
input [(PCIE_LANE*4)-1:0] PIPE_TXEQ_PRESET, // PCLK | PCLK
input [(PCIE_LANE*4)-1:0] PIPE_TXEQ_PRESET_DEFAULT,// PCLK | PCLK
input [(PCIE_LANE*6)-1:0] PIPE_TXEQ_DEEMPH, // PCLK | PCLK
input [(PCIE_LANE*2)-1:0] PIPE_RXEQ_CONTROL, // PCLK | PCLK
input [(PCIE_LANE*3)-1:0] PIPE_RXEQ_PRESET, // PCLK | PCLK
input [(PCIE_LANE*6)-1:0] PIPE_RXEQ_LFFS, // PCLK | PCLK
input [(PCIE_LANE*4)-1:0] PIPE_RXEQ_TXPRESET, // PCLK | PCLK
input [PCIE_LANE-1:0] PIPE_RXEQ_USER_EN, // PCLK | PCLK
input [(PCIE_LANE*18)-1:0]PIPE_RXEQ_USER_TXCOEFF, // PCLK | PCLK
input [PCIE_LANE-1:0] PIPE_RXEQ_USER_MODE, // PCLK | PCLK
output [ 5:0] PIPE_TXEQ_FS, // Async | Async
output [ 5:0] PIPE_TXEQ_LF, // Async | Async
output [(PCIE_LANE*18)-1:0]PIPE_TXEQ_COEFF, // PCLK | PCLK
output [PCIE_LANE-1:0] PIPE_TXEQ_DONE, // PCLK | PCLK
output [(PCIE_LANE*18)-1:0]PIPE_RXEQ_NEW_TXCOEFF, // PCLK | PCLK
output [PCIE_LANE-1:0] PIPE_RXEQ_LFFS_SEL, // PCLK | PCLK
output [PCIE_LANE-1:0] PIPE_RXEQ_ADAPT_DONE, // PCLK | PCLK
output [PCIE_LANE-1:0] PIPE_RXEQ_DONE, // PCLK | PCLK
//---------- PIPE Status Ports -------------------------
output [PCIE_LANE-1:0] PIPE_RXVALID, // PCLK | RXUSRCLK
output [PCIE_LANE-1:0] PIPE_PHYSTATUS, // PCLK | RXUSRCLK
output [PCIE_LANE-1:0] PIPE_PHYSTATUS_RST, // PCLK | RXUSRCLK
output [PCIE_LANE-1:0] PIPE_RXELECIDLE, // Async | Async
output [PCIE_LANE-1:0] PIPE_EYESCANDATAERROR, // Async | Async
output [(PCIE_LANE*3)-1:0] PIPE_RXSTATUS, // PCLK | RXUSRCLK
output [PCIE_LANE-1:0] PIPE_RXPMARESETDONE, // Async | Async
output [(PCIE_LANE*3)-1:0] PIPE_RXBUFSTATUS, // PCLK | RXUSRCLK
output [PCIE_LANE-1:0] PIPE_TXPHALIGNDONE, // Async | Async
output [PCIE_LANE-1:0] PIPE_TXPHINITDONE, // Async | Async
output [PCIE_LANE-1:0] PIPE_TXDLYSRESETDONE, // Async | Async
output [PCIE_LANE-1:0] PIPE_RXPHALIGNDONE, // Async | Async
output [PCIE_LANE-1:0] PIPE_RXDLYSRESETDONE, // Async | Async
output [PCIE_LANE-1:0] PIPE_RXSYNCDONE, // PCLK | RXUSRCLK
output [(PCIE_LANE*8)-1:0] PIPE_RXDISPERR, // PCLK | RXUSRCLK
output [(PCIE_LANE*8)-1:0] PIPE_RXNOTINTABLE, // PCLK | RXUSRCLK
output [PCIE_LANE-1:0] PIPE_RXCOMMADET, // PCLK | RXUSRCLK
//---------- PIPE User Ports ---------------------------
input PIPE_MMCM_RST_N, // Async | Async
input [PCIE_LANE-1:0] PIPE_RXSLIDE, // PCLK | RXUSRCLK
output [PCIE_LANE-1:0] PIPE_CPLL_LOCK, // Async | Async
output [(PCIE_LANE-1)>>2:0]PIPE_QPLL_LOCK, // Async | Async
output PIPE_PCLK_LOCK, // Async | Async
output [PCIE_LANE-1:0] PIPE_RXCDRLOCK, // Async | Async
output PIPE_USERCLK1, // Optional user clock
output PIPE_USERCLK2, // Optional user clock
output PIPE_RXUSRCLK, // RXUSRCLK
// Equivalent to PCLK in Gen1/Gen2
// Equivalent to RXOUTCLK[0] in Gen3
output [PCIE_LANE-1:0] PIPE_RXOUTCLK, // RX recovered clock (for debug only)
output [PCIE_LANE-1:0] PIPE_TXSYNC_DONE, // PCLK | PCLK
output [PCIE_LANE-1:0] PIPE_RXSYNC_DONE, // PCLK | PCLK
output [PCIE_LANE-1:0] PIPE_GEN3_RDY, // PCLK | RXUSRCLK
output [PCIE_LANE-1:0] PIPE_RXCHANISALIGNED,
output [PCIE_LANE-1:0] PIPE_ACTIVE_LANE,
// Shared Logic Internal
output INT_PCLK_OUT_SLAVE, // PCLK | PCLK
output INT_RXUSRCLK_OUT, // RXUSERCLK
output [PCIE_LANE-1:0 ] INT_RXOUTCLK_OUT, // RX recovered clock
output INT_DCLK_OUT, // DCLK | DCLK
output INT_USERCLK1_OUT, // Optional user clock
output INT_USERCLK2_OUT, // Optional user clock
output INT_OOBCLK_OUT, // OOB | OOB
output INT_MMCM_LOCK_OUT, // Async | Async
output [1:0] INT_QPLLLOCK_OUT,
output [1:0] INT_QPLLOUTCLK_OUT,
output [1:0] INT_QPLLOUTREFCLK_OUT,
input [PCIE_LANE-1:0] INT_PCLK_SEL_SLAVE,
// Shared Logic External
//---------- External Clock Ports ----------------------
input PIPE_PCLK_IN, // PCLK | PCLK
input PIPE_RXUSRCLK_IN, // RXUSERCLK
// Equivalent to PCLK in Gen1/Gen2
// Equivalent to RXOUTCLK[0] in Gen3
input [PCIE_LANE-1:0] PIPE_RXOUTCLK_IN, // RX recovered clock
input PIPE_DCLK_IN, // DCLK | DCLK
input PIPE_USERCLK1_IN, // Optional user clock
input PIPE_USERCLK2_IN, // Optional user clock
input PIPE_OOBCLK_IN, // OOB | OOB
input PIPE_MMCM_LOCK_IN, // Async | Async
output PIPE_TXOUTCLK_OUT, // PCLK | PCLK
output [PCIE_LANE-1:0] PIPE_RXOUTCLK_OUT, // RX recovered clock (for debug only)
output [PCIE_LANE-1:0] PIPE_PCLK_SEL_OUT, // PCLK | PCLK
output PIPE_GEN3_OUT, // PCLK | PCLK
//---------- External GT COMMON Ports ----------------------
input [11:0] QPLL_DRP_CRSCODE,
input [17:0] QPLL_DRP_FSM,
input [1:0] QPLL_DRP_DONE,
input [1:0] QPLL_DRP_RESET,
input [1:0] QPLL_QPLLLOCK,
input [1:0] QPLL_QPLLOUTCLK,
input [1:0] QPLL_QPLLOUTREFCLK,
output QPLL_QPLLPD,
output [1:0] QPLL_QPLLRESET,
output QPLL_DRP_CLK,
output QPLL_DRP_RST_N,
output QPLL_DRP_OVRD,
output QPLL_DRP_GEN3,
output QPLL_DRP_START,
//---------- TRANSCEIVER DEBUG -----------------------
input [ 2:0] PIPE_TXPRBSSEL, // PCLK | PCLK
input [ 2:0] PIPE_RXPRBSSEL, // PCLK | PCLK
input PIPE_TXPRBSFORCEERR, // PCLK | PCLK
input PIPE_RXPRBSCNTRESET, // PCLK | PCLK
input [ 2:0] PIPE_LOOPBACK, // PCLK | PCLK
output [PCIE_LANE-1:0] PIPE_RXPRBSERR, // PCLK | PCLK
input [PCIE_LANE-1:0] PIPE_TXINHIBIT, // PCLK | PCLK
//---------- FSM Ports ---------------------------------
output [4:0] PIPE_RST_FSM, // PCLK | PCLK
output [11:0] PIPE_QRST_FSM, // PCLK | PCLK
output [(PCIE_LANE*5)-1:0] PIPE_RATE_FSM, // PCLK | PCLK
output [(PCIE_LANE*6)-1:0] PIPE_SYNC_FSM_TX, // PCLK | PCLK
output [(PCIE_LANE*7)-1:0] PIPE_SYNC_FSM_RX, // PCLK | PCLK
output [(PCIE_LANE*7)-1:0] PIPE_DRP_FSM, // DCLK | DCLK
output [(PCIE_LANE*6)-1:0] PIPE_TXEQ_FSM, // PCLK | PCLK
output [(PCIE_LANE*6)-1:0] PIPE_RXEQ_FSM, // PCLK | PCLK
output [((((PCIE_LANE-1)>>2)+1)*9)-1:0]PIPE_QDRP_FSM, // DCLK | DCLK
output PIPE_RST_IDLE, // PCLK | PCLK
output PIPE_QRST_IDLE, // PCLK | PCLK
output PIPE_RATE_IDLE, // PCLK | PCLK
//----------- Channel DRP----------------------------
output EXT_CH_GT_DRPCLK,
input [(PCIE_LANE*9)-1:0] EXT_CH_GT_DRPADDR,
input [PCIE_LANE-1:0] EXT_CH_GT_DRPEN,
input [(PCIE_LANE*16)-1:0]EXT_CH_GT_DRPDI,
input [PCIE_LANE-1:0] EXT_CH_GT_DRPWE,
output [(PCIE_LANE*16)-1:0]EXT_CH_GT_DRPDO,
output [PCIE_LANE-1:0] EXT_CH_GT_DRPRDY,
//---------- JTAG Ports --------------------------------
input PIPE_JTAG_EN, // DCLK | DCLK
output [PCIE_LANE-1:0] PIPE_JTAG_RDY, // DCLK | DCLK
//---------- Debug Ports -------------------------------
output [PCIE_LANE-1:0] PIPE_DEBUG_0, // Async | Async
output [PCIE_LANE-1:0] PIPE_DEBUG_1, // Async | Async
output [PCIE_LANE-1:0] PIPE_DEBUG_2, // Async | Async
output [PCIE_LANE-1:0] PIPE_DEBUG_3, // Async | Async
output [PCIE_LANE-1:0] PIPE_DEBUG_4, // Async | Async
output [PCIE_LANE-1:0] PIPE_DEBUG_5, // Async | Async
output [PCIE_LANE-1:0] PIPE_DEBUG_6, // Async | Async
output [PCIE_LANE-1:0] PIPE_DEBUG_7, // Async | Async
output [PCIE_LANE-1:0] PIPE_DEBUG_8, // Async | Async
output [PCIE_LANE-1:0] PIPE_DEBUG_9, // Async | Async
output [31:0] PIPE_DEBUG, // Async | Async
output [(PCIE_LANE*15)-1:0] PIPE_DMONITOROUT // DMONITORCLK
);
//---------- Input Registers ---------------------------
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg reset_n_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg reset_n_reg2;
//---------- PIPE Clock Module Output ------------------
wire clk_pclk;
wire clk_rxusrclk;
wire [PCIE_LANE-1:0] clk_rxoutclk;
wire clk_dclk;
wire clk_oobclk;
wire clk_mmcm_lock;
//---------- PIPE Reset Module Output ------------------
wire rst_cpllreset;
wire rst_cpllpd;
wire rst_rxusrclk_reset;
wire rst_dclk_reset;
wire rst_gtreset;
wire rst_drp_start;
wire rst_drp_x16x20_mode;
wire rst_drp_x16;
wire rst_userrdy;
wire rst_txsync_start;
wire rst_idle;
wire [4:0] rst_fsm;
//------------------------------------------------------
wire gtp_rst_qpllreset; // GTP
wire gtp_rst_qpllpd; // GTP
//------------------------------------------------------
wire [(PCIE_LANE-1)>>2:0]qpllreset;
wire qpllpd;
//---------- QPLL Reset Module Output ------------------
wire qrst_ovrd;
wire qrst_drp_start;
wire qrst_qpllreset;
wire qrst_qpllpd;
wire qrst_idle;
wire [3:0] qrst_fsm;
//---------- PIPE_JTAG Master Module Output ------------
wire [(PCIE_LANE*37)-1:0] jtag_sl_iport;
wire [(PCIE_LANE*17)-1:0] jtag_sl_oport;
//---------- PIPE User Module Output -------------------
wire [PCIE_LANE-1:0] gt_txpmareset_i;
wire [PCIE_LANE-1:0] gt_rxpmareset_i;
wire [PCIE_LANE-1:0] user_oobclk;
wire [PCIE_LANE-1:0] user_resetovrd;
wire [PCIE_LANE-1:0] user_txpmareset;
wire [PCIE_LANE-1:0] user_rxpmareset;
wire [PCIE_LANE-1:0] user_rxcdrreset;
wire [PCIE_LANE-1:0] user_rxcdrfreqreset;
wire [PCIE_LANE-1:0] user_rxdfelpmreset;
wire [PCIE_LANE-1:0] user_eyescanreset;
wire [PCIE_LANE-1:0] user_txpcsreset;
wire [PCIE_LANE-1:0] user_rxpcsreset;
wire [PCIE_LANE-1:0] user_rxbufreset;
wire [PCIE_LANE-1:0] user_resetovrd_done;
wire [PCIE_LANE-1:0] user_active_lane;
wire [PCIE_LANE-1:0] user_resetdone /* synthesis syn_keep=1 */;
wire [PCIE_LANE-1:0] user_rxcdrlock;
wire [PCIE_LANE-1:0] user_rx_converge;
//---------- PIPE Rate Module Output -------------------
wire [PCIE_LANE-1:0] rate_cpllpd;
wire [PCIE_LANE-1:0] rate_qpllpd;
wire [PCIE_LANE-1:0] rate_cpllreset;
wire [PCIE_LANE-1:0] rate_qpllreset;
wire [PCIE_LANE-1:0] rate_txpmareset;
wire [PCIE_LANE-1:0] rate_rxpmareset;
wire [(PCIE_LANE*2)-1:0] rate_sysclksel;
wire [PCIE_LANE-1:0] rate_pclk_sel;
wire [PCIE_LANE-1:0] rate_drp_start;
wire [PCIE_LANE-1:0] rate_drp_x16x20_mode;
wire [PCIE_LANE-1:0] rate_drp_x16;
wire [PCIE_LANE-1:0] rate_gen3;
wire [(PCIE_LANE*3)-1:0] rate_rate;
wire [PCIE_LANE-1:0] rate_resetovrd_start;
wire [PCIE_LANE-1:0] rate_txsync_start;
wire [PCIE_LANE-1:0] rate_done;
wire [PCIE_LANE-1:0] rate_rxsync_start;
wire [PCIE_LANE-1:0] rate_rxsync;
wire [PCIE_LANE-1:0] rate_idle;
wire [(PCIE_LANE*5)-1:0] rate_fsm;
//---------- PIPE Sync Module Output -------------------
wire [PCIE_LANE-1:0] sync_txphdlyreset;
wire [PCIE_LANE-1:0] sync_txphalign;
wire [PCIE_LANE-1:0] sync_txphalignen;
wire [PCIE_LANE-1:0] sync_txphinit;
wire [PCIE_LANE-1:0] sync_txdlybypass;
wire [PCIE_LANE-1:0] sync_txdlysreset;
wire [PCIE_LANE-1:0] sync_txdlyen;
wire [PCIE_LANE-1:0] sync_txsync_done;
wire [(PCIE_LANE*6)-1:0] sync_fsm_tx;
wire [PCIE_LANE-1:0] sync_rxphalign;
wire [PCIE_LANE-1:0] sync_rxphalignen;
wire [PCIE_LANE-1:0] sync_rxdlybypass;
wire [PCIE_LANE-1:0] sync_rxdlysreset;
wire [PCIE_LANE-1:0] sync_rxdlyen;
wire [PCIE_LANE-1:0] sync_rxddien;
wire [PCIE_LANE-1:0] sync_rxsync_done;
wire [PCIE_LANE-1:0] sync_rxsync_donem;
wire [(PCIE_LANE*7)-1:0] sync_fsm_rx;
wire [PCIE_LANE-1:0] txdlysresetdone;
wire [PCIE_LANE-1:0] txphaligndone;
wire [PCIE_LANE-1:0] rxdlysresetdone;
wire [PCIE_LANE-1:0] rxphaligndone_s;
wire txsyncallin; // GTH
wire rxsyncallin; // GTH
//---------- PIPE DRP Module Output --------------------
wire [(PCIE_LANE*9)-1:0] drp_addr;
wire [PCIE_LANE-1:0] drp_en;
wire [(PCIE_LANE*16)-1:0]drp_di;
wire [PCIE_LANE-1:0] drp_we;
wire [PCIE_LANE-1:0] drp_done;
wire [(PCIE_LANE*3)-1:0] drp_fsm;
//---------- PIPE JTAG Slave Module Output--------------
wire [(PCIE_LANE*17)-1:0]jtag_sl_addr;
wire [PCIE_LANE-1:0] jtag_sl_den;
wire [PCIE_LANE-1:0] jtag_sl_en;
wire [(PCIE_LANE*16)-1:0]jtag_sl_di;
wire [PCIE_LANE-1:0] jtag_sl_we;
//---------- PIPE DRP MUX Output -----------------------
wire [(PCIE_LANE*9)-1:0] drp_mux_addr;
wire [PCIE_LANE-1:0] drp_mux_en;
wire [(PCIE_LANE*16)-1:0]drp_mux_di;
wire [PCIE_LANE-1:0] drp_mux_we;
//---------- PIPE EQ Module Output ---------------------
wire [PCIE_LANE-1:0] eq_txeq_deemph;
wire [(PCIE_LANE*5)-1:0] eq_txeq_precursor;
wire [(PCIE_LANE*7)-1:0] eq_txeq_maincursor;
wire [(PCIE_LANE*5)-1:0] eq_txeq_postcursor;
wire [PCIE_LANE-1:0] eq_rxeq_adapt_done;
//---------- PIPE DRP Module Output --------------------
wire [((((PCIE_LANE-1)>>2)+1)*8)-1:0] qdrp_addr;
wire [(PCIE_LANE-1)>>2:0] qdrp_en;
wire [((((PCIE_LANE-1)>>2)+1)*16)-1:0] qdrp_di;
wire [(PCIE_LANE-1)>>2:0] qdrp_we;
wire [(PCIE_LANE-1)>>2:0] qdrp_done;
wire [(PCIE_LANE-1)>>2:0] qdrp_qpllreset;
wire [((((PCIE_LANE-1)>>2)+1)*6)-1:0] qdrp_crscode;
wire [((((PCIE_LANE-1)>>2)+1)*9)-1:0] qdrp_fsm;
//---------- QPLL Wrapper Output -----------------------
wire [(PCIE_LANE-1)>>2:0] qpll_qplloutclk;
wire [(PCIE_LANE-1)>>2:0] qpll_qplloutrefclk;
wire [(PCIE_LANE-1)>>2:0] qpll_qplllock;
wire [((((PCIE_LANE-1)>>2)+1)*16)-1:0] qpll_do;
wire [(PCIE_LANE-1)>>2:0] qpll_rdy;
//---------- GTX Wrapper Output ------------------------
wire [PCIE_LANE-1:0] gt_txoutclk;
wire [PCIE_LANE-1:0] gt_rxoutclk;
wire [PCIE_LANE-1:0] gt_cplllock;
wire [PCIE_LANE-1:0] gt_rxcdrlock;
wire [PCIE_LANE-1:0] gt_txresetdone;
wire [PCIE_LANE-1:0] gt_rxresetdone;
wire [PCIE_LANE-1:0] gt_eyescandataerror;
wire [PCIE_LANE-1:0] gt_rxpmaresetdone;
wire [(PCIE_LANE*8)-1:0] gt_rxdisperr;
wire [(PCIE_LANE*8)-1:0] gt_rxnotintable;
wire [PCIE_LANE-1:0] gt_rxvalid;
wire [PCIE_LANE-1:0] gt_phystatus;
wire [(PCIE_LANE*3)-1:0] gt_rxstatus;
wire [(PCIE_LANE*3)-1:0] gt_rxbufstatus;
wire [PCIE_LANE-1:0] gt_rxelecidle;
wire [PCIE_LANE-1:0] gt_txratedone;
wire [PCIE_LANE-1:0] gt_rxratedone;
wire [(PCIE_LANE*16)-1:0]gt_do;
wire [PCIE_LANE-1:0] gt_rdy;
wire [PCIE_LANE-1:0] gt_txphinitdone;
wire [PCIE_LANE-1:0] gt_txdlysresetdone;
wire [PCIE_LANE-1:0] gt_txphaligndone;
wire [PCIE_LANE-1:0] gt_rxdlysresetdone;
wire [PCIE_LANE:0] gt_rxphaligndone; // Custom width for calculation
wire [PCIE_LANE-1:0] gt_txsyncout; // GTH
wire [PCIE_LANE-1:0] gt_txsyncdone; // GTH
wire [PCIE_LANE-1:0] gt_rxsyncout; // GTH
wire [PCIE_LANE-1:0] gt_rxsyncdone; // GTH
wire [PCIE_LANE-1:0] gt_rxcommadet;
wire [(PCIE_LANE*4)-1:0] gt_rxchariscomma;
wire [PCIE_LANE-1:0] gt_rxbyteisaligned;
wire [PCIE_LANE-1:0] gt_rxbyterealign;
wire [ 4:0] gt_rxchbondi [PCIE_LANE:0];
wire [(PCIE_LANE*3)-1:0] gt_rxchbondlevel;
wire [ 4:0] gt_rxchbondo [PCIE_LANE:0];
wire [PCIE_LANE-1:0] rxchbonden;
wire [PCIE_LANE-1:0] rxchbondmaster;
wire [PCIE_LANE-1:0] rxchbondslave;
wire [PCIE_LANE-1:0] oobclk;
//---------- TX EQ -------------------------------------
localparam TXEQ_FS = 6'd40; // TX equalization full swing
localparam TXEQ_LF = 6'd15; // TX equalization low frequency
//---------- Select JTAG Slave Type ----------------------------------------
localparam GC_XSDB_SLAVE_TYPE = (PCIE_GT_DEVICE == "GTP") ? 16'h0400 : (PCIE_GT_DEVICE == "GTH") ? 16'h004A : 16'h0046;
//---------- Generate Per-Lane Signals -----------------
genvar i; // Index for per-lane signals
//---------- Assignments -------------------------------------------------------
assign gt_rxchbondo[0] = 5'd0; // Initialize rxchbond for lane 0
assign gt_rxphaligndone[PCIE_LANE] = 1'd1; // Mot used
assign txsyncallin = &(gt_txphaligndone | (~user_active_lane));
assign rxsyncallin = &(gt_rxphaligndone | (~user_active_lane));
//---------- Reset Synchronizer ------------------------------------------------
always @ (posedge clk_pclk or negedge PIPE_RESET_N)
begin
if (!PIPE_RESET_N)
begin
reset_n_reg1 <= 1'd0;
reset_n_reg2 <= 1'd0;
end
else
begin
reset_n_reg1 <= 1'd1;
reset_n_reg2 <= reset_n_reg1;
end
end
//---------- PIPE Clock Module -------------------------------------------------
generate
begin : pipe_clock_int
PCIeGen2x8If128_pipe_clock #
(
.PCIE_ASYNC_EN (PCIE_ASYNC_EN), // PCIe async enable
.PCIE_TXBUF_EN (PCIE_TXBUF_EN), // PCIe TX buffer enable for Gen1/Gen2 only
.PCIE_LANE (PCIE_LANE), // PCIe number of lanes
.PCIE_LINK_SPEED (PCIE_LINK_SPEED), // PCIe link speed
.PCIE_REFCLK_FREQ (PCIE_REFCLK_FREQ), // PCIe reference clock frequency
.PCIE_USERCLK1_FREQ (PCIE_USERCLK1_FREQ), // PCIe user clock 1 frequency
.PCIE_USERCLK2_FREQ (PCIE_USERCLK2_FREQ), // PCIe user clock 2 frequency
.PCIE_OOBCLK_MODE (PCIE_OOBCLK_MODE), // PCIe OOB clock mode
.PCIE_DEBUG_MODE (PCIE_DEBUG_MODE) // PCIe debug mode
)
pipe_clock_i
(
//---------- Input -------------------------------------
.CLK_CLK (PIPE_CLK),
.CLK_TXOUTCLK (gt_txoutclk[0]), // Reference clock from lane 0
.CLK_RXOUTCLK_IN (gt_rxoutclk),
//.CLK_RST_N (1'b1),
.CLK_RST_N (PIPE_MMCM_RST_N), // Allow system reset for error recovery
.CLK_PCLK_SEL (rate_pclk_sel),
.CLK_PCLK_SEL_SLAVE (INT_PCLK_SEL_SLAVE ),
.CLK_GEN3 (rate_gen3[0]),
//---------- Output ------------------------------------
.CLK_PCLK (clk_pclk),
.CLK_PCLK_SLAVE (INT_PCLK_OUT_SLAVE),
.CLK_RXUSRCLK (clk_rxusrclk),
.CLK_RXOUTCLK_OUT (clk_rxoutclk),
.CLK_DCLK (clk_dclk),
.CLK_USERCLK1 (PIPE_USERCLK1),
.CLK_USERCLK2 (PIPE_USERCLK2),
.CLK_OOBCLK (clk_oobclk),
.CLK_MMCM_LOCK (clk_mmcm_lock)
);
assign INT_RXUSRCLK_OUT = clk_rxusrclk;
assign INT_RXOUTCLK_OUT = clk_rxoutclk;
assign INT_DCLK_OUT = clk_dclk;
assign INT_USERCLK1_OUT = PIPE_USERCLK1;
assign INT_USERCLK2_OUT = PIPE_USERCLK2;
assign INT_OOBCLK_OUT = clk_oobclk;
assign INT_MMCM_LOCK_OUT = clk_mmcm_lock;
end
endgenerate
//---------- PIPE Reset Module -------------------------------------------------
generate
if (PCIE_GT_DEVICE == "GTP")
begin : gtp_pipe_reset
//---------- GTP PIPE Reset Module -------------------------------------
PCIeGen2x8If128_gtp_pipe_reset #
(
.PCIE_SIM_SPEEDUP (PCIE_SIM_SPEEDUP), // PCIe sim mode
//.PCIE_PLL_SEL (PCIE_PLL_SEL), // removed for GTP
//.PCIE_POWER_SAVING (PCIE_POWER_SAVING), // removed for GTP
//.PCIE_TXBUF_EN (PCIE_TXBUF_EN), // PCIe TX buffer enable for Gen1/Gen2 only
.PCIE_LANE (PCIE_LANE) // PCIe number of lanes
)
gtp_pipe_reset_i
(
//---------- Input -----------------------------
.RST_CLK (clk_pclk),
.RST_RXUSRCLK (clk_rxusrclk),
.RST_DCLK (clk_dclk),
.RST_RST_N (reset_n_reg2),
.RST_DRP_DONE (drp_done),
.RST_RXPMARESETDONE (gt_rxpmaresetdone),
.RST_PLLLOCK (&qpll_qplllock),
//.RST_QPLL_IDLE (qrst_idle), // removed for GTP
.RST_RATE_IDLE (rate_idle),
.RST_RXCDRLOCK (user_rxcdrlock),
.RST_MMCM_LOCK (clk_mmcm_lock),
.RST_RESETDONE (user_resetdone),
.RST_PHYSTATUS (gt_phystatus),
.RST_TXSYNC_DONE (sync_txsync_done),
//---------- Output ----------------------------
.RST_CPLLRESET (rst_cpllreset),
.RST_CPLLPD (rst_cpllpd),
.RST_RXUSRCLK_RESET (rst_rxusrclk_reset),
.RST_DCLK_RESET (rst_dclk_reset),
.RST_GTRESET (rst_gtreset),
.RST_DRP_START (rst_drp_start),
.RST_DRP_X16 (rst_drp_x16),
.RST_USERRDY (rst_userrdy),
.RST_TXSYNC_START (rst_txsync_start),
.RST_IDLE (rst_idle),
.RST_FSM (rst_fsm)
);
//---------- Default ---------------------------------------------------
assign gtp_rst_qpllreset = rst_cpllreset;
assign gtp_rst_qpllpd = rst_cpllpd;
end
else
begin : pipe_reset
//---------- PIPE Reset Module -----------------------------------------
PCIeGen2x8If128_pipe_reset #
(
.PCIE_SIM_SPEEDUP (PCIE_SIM_SPEEDUP), // PCIe sim mode
.PCIE_GT_DEVICE (PCIE_GT_DEVICE), // PCIe GT Device
.PCIE_PLL_SEL (PCIE_PLL_SEL), // PCIe PLL select for Gen1/Gen2 only
.PCIE_POWER_SAVING (PCIE_POWER_SAVING), // PCIe power saving
.PCIE_TXBUF_EN (PCIE_TXBUF_EN), // PCIe TX buffer enable for Gen1/Gen2 only
.PCIE_LANE (PCIE_LANE) // PCIe number of lanes
)
pipe_reset_i
(
//---------- Input -----------------------------
.RST_CLK (clk_pclk),
.RST_RXUSRCLK (clk_rxusrclk),
.RST_DCLK (clk_dclk),
.RST_RST_N (reset_n_reg2),
.RST_DRP_DONE (drp_done),
.RST_RXPMARESETDONE (gt_rxpmaresetdone),
.RST_CPLLLOCK (gt_cplllock),
.RST_QPLL_IDLE (qrst_idle),
.RST_RATE_IDLE (rate_idle),
.RST_RXCDRLOCK (user_rxcdrlock),
.RST_MMCM_LOCK (clk_mmcm_lock),
.RST_RESETDONE (user_resetdone),
.RST_PHYSTATUS (gt_phystatus),
.RST_TXSYNC_DONE (sync_txsync_done),
//---------- Output ----------------------------
.RST_CPLLRESET (rst_cpllreset),
.RST_CPLLPD (rst_cpllpd),
.RST_RXUSRCLK_RESET (rst_rxusrclk_reset),
.RST_DCLK_RESET (rst_dclk_reset),
.RST_GTRESET (rst_gtreset),
.RST_DRP_START (rst_drp_start),
.RST_DRP_X16X20_MODE (rst_drp_x16x20_mode),
.RST_DRP_X16 (rst_drp_x16),
.RST_USERRDY (rst_userrdy),
.RST_TXSYNC_START (rst_txsync_start),
.RST_IDLE (rst_idle),
.RST_FSM (rst_fsm[4:0])
);
//---------- Default ---------------------------------------------------
assign gtp_rst_qpllreset = 1'd0;
assign gtp_rst_qpllpd = 1'd0;
end
endgenerate
//---------- QPLL Reset Module -------------------------------------------------
generate
if ((PCIE_LINK_SPEED == 3) || (PCIE_PLL_SEL == "QPLL"))
begin : qpll_reset
PCIeGen2x8If128_qpll_reset #
(
.PCIE_PLL_SEL (PCIE_PLL_SEL), // PCIe PLL select for Gen1/Gen2 only
.PCIE_POWER_SAVING (PCIE_POWER_SAVING),// PCIe power saving
.PCIE_LANE (PCIE_LANE) // PCIe number of lanes
)
qpll_reset_i
(
//---------- Input ---------------------------------
.QRST_CLK (clk_pclk),
.QRST_RST_N (reset_n_reg2),
.QRST_MMCM_LOCK (clk_mmcm_lock),
.QRST_CPLLLOCK (gt_cplllock),
.QRST_DRP_DONE (qdrp_done),
.QRST_QPLLLOCK (qpll_qplllock),
.QRST_RATE (PIPE_RATE),
.QRST_QPLLRESET_IN (rate_qpllreset),
.QRST_QPLLPD_IN (rate_qpllpd),
//---------- Output --------------------------------
.QRST_OVRD (qrst_ovrd),
.QRST_DRP_START (qrst_drp_start),
.QRST_QPLLRESET_OUT (qrst_qpllreset),
.QRST_QPLLPD_OUT (qrst_qpllpd),
.QRST_IDLE (qrst_idle),
.QRST_FSM (qrst_fsm)
);
end
else
//---------- QPLL Reset Defaults ---------------------------------------
begin : qpll_reset_disable
assign qrst_ovrd = 1'd0;
assign qrst_drp_start = 1'd0;
assign qrst_qpllreset = 1'd0;
assign qrst_qpllpd = 1'd0;
assign qrst_idle = 1'd0;
assign qrst_fsm = 1;
end
endgenerate
assign jtag_sl_iport = {PCIE_LANE{37'd0}};
//Reference Clock for CPLLPD Fix
wire gt_cpllpdrefclk;
BUFG cpllpd_refclk_inst (.I (PIPE_CLK), .O (gt_cpllpdrefclk));
//---------- Generate PIPE Lane ------------------------------------------------
generate for (i=0; i<PCIE_LANE; i=i+1)
begin : pipe_lane
//---------- PIPE User Module ----------------------------------------------
PCIeGen2x8If128_pipe_user #
(
.PCIE_USE_MODE (PCIE_USE_MODE),
.PCIE_OOBCLK_MODE (PCIE_OOBCLK_MODE)
)
pipe_user_i
(
//---------- Input ---------------------------------
.USER_TXUSRCLK (clk_pclk),
.USER_RXUSRCLK (clk_rxusrclk),
.USER_OOBCLK_IN (clk_oobclk),
.USER_RST_N (!rst_cpllreset),
.USER_RXUSRCLK_RST_N (!rst_rxusrclk_reset),
.USER_PCLK_SEL (rate_pclk_sel[i]),
.USER_RESETOVRD_START (rate_resetovrd_start[i]),
.USER_TXRESETDONE (gt_txresetdone[i]),
.USER_RXRESETDONE (gt_rxresetdone[i]),
.USER_TXELECIDLE (PIPE_TXELECIDLE[i]),
.USER_TXCOMPLIANCE (PIPE_TXCOMPLIANCE[i]),
.USER_RXCDRLOCK_IN (gt_rxcdrlock[i]),
.USER_RXVALID_IN (gt_rxvalid[i]),
.USER_RXSTATUS_IN (gt_rxstatus[(3*i)+2]),
.USER_PHYSTATUS_IN (gt_phystatus[i]),
.USER_RATE_DONE (rate_done[i]),
.USER_RST_IDLE (rst_idle),
.USER_RATE_RXSYNC (rate_rxsync[i]),
.USER_RATE_IDLE (rate_idle[i]),
.USER_RATE_GEN3 (rate_gen3[i]),
.USER_RXEQ_ADAPT_DONE (eq_rxeq_adapt_done[i]),
//---------- Output --------------------------------
.USER_OOBCLK (user_oobclk[i]),
.USER_RESETOVRD (user_resetovrd[i]),
.USER_TXPMARESET (user_txpmareset[i]),
.USER_RXPMARESET (user_rxpmareset[i]),
.USER_RXCDRRESET (user_rxcdrreset[i]),
.USER_RXCDRFREQRESET (user_rxcdrfreqreset[i]),
.USER_RXDFELPMRESET (user_rxdfelpmreset[i]),
.USER_EYESCANRESET (user_eyescanreset[i]),
.USER_TXPCSRESET (user_txpcsreset[i]),
.USER_RXPCSRESET (user_rxpcsreset[i]),
.USER_RXBUFRESET (user_rxbufreset[i]),
.USER_RESETOVRD_DONE (user_resetovrd_done[i]),
.USER_RESETDONE (user_resetdone[i]),
.USER_ACTIVE_LANE (user_active_lane[i]),
.USER_RXCDRLOCK_OUT (user_rxcdrlock[i]),
.USER_RXVALID_OUT (PIPE_RXVALID[i]),
.USER_PHYSTATUS_OUT (PIPE_PHYSTATUS[i]),
.USER_PHYSTATUS_RST (PIPE_PHYSTATUS_RST[i]),
.USER_GEN3_RDY (PIPE_GEN3_RDY[i]),
.USER_RX_CONVERGE (user_rx_converge[i])
);
//---------- GTP PIPE Rate Module ------------------------------------------
if (PCIE_GT_DEVICE == "GTP")
begin : gtp_pipe_rate
PCIeGen2x8If128_gtp_pipe_rate #
(
.PCIE_SIM_SPEEDUP (PCIE_SIM_SPEEDUP) // PCIe sim speedup
//.PCIE_USE_MODE (PCIE_USE_MODE), // removed for GTP
//.PCIE_PLL_SEL (PCIE_PLL_SEL), // removed for GTP
//.PCIE_POWER_SAVING (PCIE_POWER_SAVING), // removed for GTP
//.PCIE_ASYNC_EN (PCIE_ASYNC_EN), // removed for GTP
//.PCIE_TXBUF_EN (PCIE_TXBUF_EN), // removed for GTP
//.PCIE_RXBUF_EN (PCIE_RXBUF_EN) // removed for GTP
)
gtp_pipe_rate_i
(
//---------- Input -----------------------------
.RATE_CLK (clk_pclk),
.RATE_RST_N (!rst_cpllreset),
//.RATE_RST_IDLE (rst_idle), // removed for GTP
//.RATE_ACTIVE_LANE (user_active_lane[i]), // removed for GTP
.RATE_RATE_IN (PIPE_RATE),
//.RATE_CPLLLOCK (gt_cplllock[i]), // removed for GTP
//.RATE_QPLLLOCK (qpll_qplllock[i>>2]) // removed for GTP
//.RATE_MMCM_LOCK (clk_mmcm_lock), // removed for GTP
.RATE_DRP_DONE (drp_done[i]),
.RATE_RXPMARESETDONE (gt_rxpmaresetdone[i]),
//.RATE_TXRESETDONE (gt_txresetdone[i]), // removed for GTP
//.RATE_RXRESETDONE (gt_rxresetdone[i]), // removed for GTP
.RATE_TXRATEDONE (gt_txratedone[i]),
.RATE_RXRATEDONE (gt_rxratedone[i]),
.RATE_PHYSTATUS (gt_phystatus[i]),
//.RATE_RESETOVRD_DONE (user_resetovrd_done[i]), // removed for GTP
.RATE_TXSYNC_DONE (sync_txsync_done[i]),
//.RATE_RXSYNC_DONE (sync_rxsync_done[i]), // removed for GTP
//---------- Output ----------------------------
//.RATE_CPLLPD (rate_cpllpd[i]), // removed for GTP
//.RATE_QPLLPD (rate_qpllpd[i]), // removed for GTP
//.RATE_CPLLRESET (rate_cpllreset[i]), // removed for GTP
//.RATE_QPLLRESET (rate_qpllreset[i]), // removed for GTP
//.RATE_TXPMARESET (rate_txpmareset[i]), // removed for GTP
//.RATE_RXPMARESET (rate_rxpmareset[i]), // removed for GTP
//.RATE_SYSCLKSEL (rate_sysclksel[(2*i)+1:(2*i)]), // removed for GTP
.RATE_DRP_START (rate_drp_start[i]),
.RATE_DRP_X16 (rate_drp_x16[i]),
.RATE_PCLK_SEL (rate_pclk_sel[i]),
//.RATE_GEN3 (rate_gen3[i]), // removed for GTP
.RATE_RATE_OUT (rate_rate[(3*i)+2:(3*i)]),
//.RATE_RESETOVRD_START (rate_resetovrd_start[i]), // removed for GTP
.RATE_TXSYNC_START (rate_txsync_start[i]),
.RATE_DONE (rate_done[i]),
//.RATE_RXSYNC_START (rate_rxsync_start[i]), // removed for GTP
//.RATE_RXSYNC (rate_rxsync[i]), // removed for GTP
.RATE_IDLE (rate_idle[i]),
.RATE_FSM (rate_fsm[(5*i)+4:(5*i)])
);
//---------- Default for GTP -----------------------
assign rate_cpllpd[i] = 1'd0;
assign rate_qpllpd[i] = 1'd0;
assign rate_cpllreset[i] = 1'd0;
assign rate_qpllreset[i] = 1'd0;
assign rate_txpmareset[i] = 1'd0;
assign rate_rxpmareset[i] = 1'd0;
assign rate_sysclksel[(2*i)+1:(2*i)] = 2'b0;
assign rate_gen3[i] = 1'd0;
assign rate_resetovrd_start[i] = 1'd0;
assign rate_rxsync_start[i] = 1'd0;
assign rate_rxsync[i] = 1'd0;
end
else
begin : pipe_rate
//---------- PIPE Rate Module ----------------------------------------------
PCIeGen2x8If128_pipe_rate #
(
.PCIE_SIM_SPEEDUP (PCIE_SIM_SPEEDUP), // PCIe sim speedup
.PCIE_GT_DEVICE (PCIE_GT_DEVICE), // PCIe GT device
.PCIE_USE_MODE (PCIE_USE_MODE), // PCIe use mode
.PCIE_PLL_SEL (PCIE_PLL_SEL), // PCIe PLL select for Gen1/Gen2 only
.PCIE_POWER_SAVING (PCIE_POWER_SAVING),// PCIe power saving
.PCIE_ASYNC_EN (PCIE_ASYNC_EN), // PCIe async enable
.PCIE_TXBUF_EN (PCIE_TXBUF_EN), // PCIe TX buffer enable for Gen1/Gen2 only
.PCIE_RXBUF_EN (PCIE_RXBUF_EN) // PCIe RX buffer enable for Gen3 only
)
pipe_rate_i
(
//---------- Input ---------------------------------
.RATE_CLK (clk_pclk),
.RATE_RST_N (!rst_cpllreset),
.RATE_RST_IDLE (rst_idle),
.RATE_ACTIVE_LANE (user_active_lane[i]),
.RATE_RATE_IN (PIPE_RATE),
.RATE_CPLLLOCK (gt_cplllock[i]),
.RATE_QPLLLOCK (qpll_qplllock[i>>2]),
.RATE_MMCM_LOCK (clk_mmcm_lock),
.RATE_DRP_DONE (drp_done[i]),
.RATE_RXPMARESETDONE (gt_rxpmaresetdone[i]),
.RATE_TXRESETDONE (gt_txresetdone[i]),
.RATE_RXRESETDONE (gt_rxresetdone[i]),
.RATE_TXRATEDONE (gt_txratedone[i]),
.RATE_RXRATEDONE (gt_rxratedone[i]),
.RATE_PHYSTATUS (gt_phystatus[i]),
.RATE_RESETOVRD_DONE (user_resetovrd_done[i]),
.RATE_TXSYNC_DONE (sync_txsync_done[i]),
.RATE_RXSYNC_DONE (sync_rxsync_done[i]),
//---------- Output --------------------------------
.RATE_CPLLPD (rate_cpllpd[i]),
.RATE_QPLLPD (rate_qpllpd[i]),
.RATE_CPLLRESET (rate_cpllreset[i]),
.RATE_QPLLRESET (rate_qpllreset[i]),
.RATE_TXPMARESET (rate_txpmareset[i]),
.RATE_RXPMARESET (rate_rxpmareset[i]),
.RATE_SYSCLKSEL (rate_sysclksel[(2*i)+1:(2*i)]),
.RATE_DRP_START (rate_drp_start[i]),
.RATE_DRP_X16X20_MODE (rate_drp_x16x20_mode[i]),
.RATE_DRP_X16 (rate_drp_x16[i]),
.RATE_PCLK_SEL (rate_pclk_sel[i]),
.RATE_GEN3 (rate_gen3[i]),
.RATE_RATE_OUT (rate_rate[(3*i)+2:(3*i)]),
.RATE_RESETOVRD_START (rate_resetovrd_start[i]),
.RATE_TXSYNC_START (rate_txsync_start[i]),
.RATE_DONE (rate_done[i]),
.RATE_RXSYNC_START (rate_rxsync_start[i]),
.RATE_RXSYNC (rate_rxsync[i]),
.RATE_IDLE (rate_idle[i]),
.RATE_FSM (rate_fsm[(5*i)+4:(5*i)])
);
end
//---------- PIPE Sync Module ----------------------------------------------
PCIeGen2x8If128_pipe_sync #
(
.PCIE_GT_DEVICE (PCIE_GT_DEVICE), // PCIe GT Device
.PCIE_TXBUF_EN (PCIE_TXBUF_EN), // PCIe TX buffer enable for Gen1/Gen2 only
.PCIE_RXBUF_EN (PCIE_RXBUF_EN), // PCIe RX buffer enable for Gen3 only
.PCIE_TXSYNC_MODE (PCIE_TXSYNC_MODE), // PCIe TX sync mode
.PCIE_RXSYNC_MODE (PCIE_RXSYNC_MODE), // PCIe RX sync mode
.PCIE_LANE (PCIE_LANE), // PCIe lane
.PCIE_LINK_SPEED (PCIE_LINK_SPEED) // PCIe link speed
)
pipe_sync_i
(
//---------- Input ---------------------------------
.SYNC_CLK (clk_pclk),
.SYNC_RST_N (!rst_cpllreset),
.SYNC_SLAVE (i > 0),
.SYNC_GEN3 (rate_gen3[i]),
.SYNC_RATE_IDLE (rate_idle[i]),
.SYNC_MMCM_LOCK (clk_mmcm_lock),
.SYNC_RXELECIDLE (gt_rxelecidle[i]),
.SYNC_RXCDRLOCK (user_rxcdrlock[i]),
.SYNC_ACTIVE_LANE (user_active_lane[i]),
.SYNC_TXSYNC_START (rate_txsync_start[i] || rst_txsync_start),
.SYNC_TXPHINITDONE (&(gt_txphinitdone | (~user_active_lane))),
.SYNC_TXDLYSRESETDONE (txdlysresetdone[i]),
.SYNC_TXPHALIGNDONE (txphaligndone[i]),
.SYNC_TXSYNCDONE (gt_txsyncdone[i]), // GTH
.SYNC_RXSYNC_START (rate_rxsync_start[i]),
.SYNC_RXDLYSRESETDONE (rxdlysresetdone[i]),
.SYNC_RXPHALIGNDONE_M (gt_rxphaligndone[0]),
.SYNC_RXPHALIGNDONE_S (rxphaligndone_s[i]),
.SYNC_RXSYNC_DONEM_IN (sync_rxsync_donem[0]),
.SYNC_RXSYNCDONE (gt_rxsyncdone[i]), // GTH
//---------- Output --------------------------------
.SYNC_TXPHDLYRESET (sync_txphdlyreset[i]),
.SYNC_TXPHALIGN (sync_txphalign[i]),
.SYNC_TXPHALIGNEN (sync_txphalignen[i]),
.SYNC_TXPHINIT (sync_txphinit[i]),
.SYNC_TXDLYBYPASS (sync_txdlybypass[i]),
.SYNC_TXDLYSRESET (sync_txdlysreset[i]),
.SYNC_TXDLYEN (sync_txdlyen[i]),
.SYNC_TXSYNC_DONE (sync_txsync_done[i]),
.SYNC_FSM_TX (sync_fsm_tx[(6*i)+5:(6*i)]),
.SYNC_RXPHALIGN (sync_rxphalign[i]),
.SYNC_RXPHALIGNEN (sync_rxphalignen[i]),
.SYNC_RXDLYBYPASS (sync_rxdlybypass[i]),
.SYNC_RXDLYSRESET (sync_rxdlysreset[i]),
.SYNC_RXDLYEN (sync_rxdlyen[i]),
.SYNC_RXDDIEN (sync_rxddien[i]),
.SYNC_RXSYNC_DONEM_OUT (sync_rxsync_donem[i]),
.SYNC_RXSYNC_DONE (sync_rxsync_done[i]),
.SYNC_FSM_RX (sync_fsm_rx[(7*i)+6:(7*i)])
);
//---------- PIPE Sync Assignments -----------------------------------------
assign txdlysresetdone[i] = (PCIE_TXSYNC_MODE == 1) ? gt_txdlysresetdone[i] : >_txdlysresetdone;
assign txphaligndone[i] = (PCIE_TXSYNC_MODE == 1) ? gt_txphaligndone[i] : &(gt_txphaligndone | (~user_active_lane));
assign rxdlysresetdone[i] = (PCIE_RXSYNC_MODE == 1) ? gt_rxdlysresetdone[i] : >_rxdlysresetdone;
assign rxphaligndone_s[i] = (PCIE_LANE == 1) ? 1'd0 : >_rxphaligndone[PCIE_LANE:1];
//---------- GTP PIPE DRP Module -------------------------------------------
if (PCIE_GT_DEVICE == "GTP")
begin : gtp_pipe_drp
//---------- GTP PIPE DRP Module ---------------------------------------
PCIeGen2x8If128_gtp_pipe_drp
gtp_pipe_drp_i
(
//---------- Input ---------------------------------
.DRP_CLK (clk_dclk),
.DRP_RST_N (!rst_dclk_reset),
.DRP_X16 (rst_drp_x16 || rate_drp_x16[i]),
.DRP_START (rst_drp_start || rate_drp_start[i]),
.DRP_DO (gt_do[(16*i)+15:(16*i)]),
.DRP_RDY (gt_rdy[i]),
//---------- Output --------------------------------
.DRP_ADDR (drp_addr[(9*i)+8:(9*i)]),
.DRP_EN (drp_en[i]),
.DRP_DI (drp_di[(16*i)+15:(16*i)]),
.DRP_WE (drp_we[i]),
.DRP_DONE (drp_done[i]),
.DRP_FSM (drp_fsm[(3*i)+2:(3*i)])
);
end
else
begin : pipe_drp
//---------- PIPE DRP Module -------------------------------------------
PCIeGen2x8If128_pipe_drp #
(
.PCIE_GT_DEVICE (PCIE_GT_DEVICE), // PCIe GT device
.PCIE_USE_MODE (PCIE_USE_MODE), // PCIe use mode
.PCIE_PLL_SEL (PCIE_PLL_SEL), // PCIe PLL select for Gen1/Gen2 only
.PCIE_AUX_CDR_GEN3_EN (PCIE_AUX_CDR_GEN3_EN), // PCIe AUX CDR Gen3 enable
.PCIE_ASYNC_EN (PCIE_ASYNC_EN), // PCIe async enable
.PCIE_TXBUF_EN (PCIE_TXBUF_EN), // PCIe TX buffer enable for Gen1/Gen2 only
.PCIE_RXBUF_EN (PCIE_RXBUF_EN), // PCIe RX buffer enable for Gen3 only
.PCIE_TXSYNC_MODE (PCIE_TXSYNC_MODE), // PCIe TX sync mode
.PCIE_RXSYNC_MODE (PCIE_RXSYNC_MODE) // PCIe RX sync mode
)
pipe_drp_i
(
//---------- Input ---------------------------------
.DRP_CLK (clk_dclk),
.DRP_RST_N (!rst_dclk_reset),
.DRP_GTXRESET (rst_gtreset),
.DRP_RATE (PIPE_RATE),
.DRP_X16X20_MODE (rst_drp_x16x20_mode || rate_drp_x16x20_mode[i]),
.DRP_X16 (rst_drp_x16 || rate_drp_x16[i]),
.DRP_START (rst_drp_start || rate_drp_start[i]),
.DRP_DO (gt_do[(16*i)+15:(16*i)]),
.DRP_RDY (gt_rdy[i]),
//---------- Output --------------------------------
.DRP_ADDR (drp_addr[(9*i)+8:(9*i)]),
.DRP_EN (drp_en[i]),
.DRP_DI (drp_di[(16*i)+15:(16*i)]),
.DRP_WE (drp_we[i]),
.DRP_DONE (drp_done[i]),
.DRP_FSM (drp_fsm[(3*i)+2:(3*i)])
);
end
assign jtag_sl_oport[((i+1)*17)-1 : (i*17)] = 17'd0;
assign jtag_sl_addr[(17*i)+16:(17*i)] = 17'd0;
assign jtag_sl_den[i] = 1'd0;
assign jtag_sl_di[(16*i)+15:(16*i)] = 16'd0;
assign jtag_sl_we[i] = 1'd0;
//---------- Generate DRP MUX ----------------------------------------------
assign PIPE_JTAG_RDY[i] = (drp_fsm[(3*i)+2:(3*i)] == 3'b000);
assign jtag_sl_en[i] = (jtag_sl_addr[(17*i)+16:(17*i)+9] == 8'd0) ? jtag_sl_den[i] : 1'd0;
// Channel DRP
assign drp_mux_en[i] = (PIPE_JTAG_RDY[i] && EXT_CH_GT_DRP) ? EXT_CH_GT_DRPEN[i] : drp_en[i];
assign drp_mux_di[(16*i)+15:(16*i)] = (PIPE_JTAG_RDY[i] && EXT_CH_GT_DRP) ? EXT_CH_GT_DRPDI[(16*i)+15:(16*i)] : drp_di[(16*i)+15:(16*i)];
assign drp_mux_addr[(9*i)+8:(9*i)] = (PIPE_JTAG_RDY[i] && EXT_CH_GT_DRP) ? EXT_CH_GT_DRPADDR[(9*i)+8:(9*i)] : drp_addr[(9*i)+8:(9*i)];
assign drp_mux_we[i] = (PIPE_JTAG_RDY[i] && EXT_CH_GT_DRP) ? EXT_CH_GT_DRPWE[i] : drp_we[i];
//---------- Generate PIPE EQ ----------------------------------------------
if (PCIE_LINK_SPEED == 3)
begin : pipe_eq
//---------- PIPE EQ Module --------------------------------------------
PCIeGen2x8If128_pipe_eq #
(
.PCIE_SIM_MODE (PCIE_SIM_MODE), // PCIe sim mode
.PCIE_GT_DEVICE (PCIE_GT_DEVICE),
.PCIE_RXEQ_MODE_GEN3 (PCIE_RXEQ_MODE_GEN3) // PCIe RX equalization mode
)
pipe_eq_i
(
//---------- Input -----------------------------
.EQ_CLK (clk_pclk),
.EQ_RST_N (!rst_cpllreset),
.EQ_GEN3 (rate_gen3[i]),
.EQ_TXEQ_CONTROL (PIPE_TXEQ_CONTROL[(2*i)+1:(2*i)]),
.EQ_TXEQ_PRESET (PIPE_TXEQ_PRESET[(4*i)+3:(4*i)]),
.EQ_TXEQ_PRESET_DEFAULT (PIPE_TXEQ_PRESET_DEFAULT[(4*i)+3:(4*i)]),
.EQ_TXEQ_DEEMPH_IN (PIPE_TXEQ_DEEMPH[(6*i)+5:(6*i)]), // renamed
.EQ_RXEQ_CONTROL (PIPE_RXEQ_CONTROL[(2*i)+1:(2*i)]),
.EQ_RXEQ_PRESET (PIPE_RXEQ_PRESET[(3*i)+2:(3*i)]),
.EQ_RXEQ_LFFS (PIPE_RXEQ_LFFS[(6*i)+5:(6*i)]),
.EQ_RXEQ_TXPRESET (PIPE_RXEQ_TXPRESET[(4*i)+3:(4*i)]),
.EQ_RXEQ_USER_EN (PIPE_RXEQ_USER_EN[i]),
.EQ_RXEQ_USER_TXCOEFF (PIPE_RXEQ_USER_TXCOEFF[(18*i)+17:(18*i)]),
.EQ_RXEQ_USER_MODE (PIPE_RXEQ_USER_MODE[i]),
//---------- Output ----------------------------
.EQ_TXEQ_DEEMPH (eq_txeq_deemph[i]),
.EQ_TXEQ_PRECURSOR (eq_txeq_precursor[(5*i)+4:(5*i)]),
.EQ_TXEQ_MAINCURSOR (eq_txeq_maincursor[(7*i)+6:(7*i)]),
.EQ_TXEQ_POSTCURSOR (eq_txeq_postcursor[(5*i)+4:(5*i)]),
.EQ_TXEQ_DEEMPH_OUT (PIPE_TXEQ_COEFF[(18*i)+17:(18*i)]),// renamed
.EQ_TXEQ_DONE (PIPE_TXEQ_DONE[i]),
.EQ_TXEQ_FSM (PIPE_TXEQ_FSM[(6*i)+5:(6*i)]),
.EQ_RXEQ_NEW_TXCOEFF (PIPE_RXEQ_NEW_TXCOEFF[(18*i)+17:(18*i)]),
.EQ_RXEQ_LFFS_SEL (PIPE_RXEQ_LFFS_SEL[i]),
.EQ_RXEQ_ADAPT_DONE (eq_rxeq_adapt_done[i]),
.EQ_RXEQ_DONE (PIPE_RXEQ_DONE[i]),
.EQ_RXEQ_FSM (PIPE_RXEQ_FSM[(6*i)+5:(6*i)])
);
end
else
//---------- PIPE EQ Defaults ------------------------------------------
begin : pipe_eq_disable
assign eq_txeq_deemph[i] = 1'd0;
assign eq_txeq_precursor[(5*i)+4:(5*i)] = 5'h00;
assign eq_txeq_maincursor[(7*i)+6:(7*i)] = 7'h00;
assign eq_txeq_postcursor[(5*i)+4:(5*i)] = 5'h00;
assign eq_rxeq_adapt_done[i] = 1'd0;
assign PIPE_TXEQ_COEFF[(18*i)+17:(18*i)] = 18'd0;
assign PIPE_TXEQ_DONE[i] = 1'd0;
assign PIPE_TXEQ_FSM[(6*i)+5:(6*i)] = 6'd0;
assign PIPE_RXEQ_NEW_TXCOEFF[(18*i)+17:(18*i)] = 18'd0;
assign PIPE_RXEQ_LFFS_SEL[i] = 1'd0;
assign PIPE_RXEQ_ADAPT_DONE[i] = 1'd0;
assign PIPE_RXEQ_DONE[i] = 1'd0;
assign PIPE_RXEQ_FSM[(6*i)+5:(6*i)] = 6'd0;
end
//---------- Generate PIPE Common Per Quad for Gen3 ------------------------
if ((i%4)==0)
begin : pipe_quad
//---------- Generate QPLL Powerdown and Reset -------------------------
assign qpllpd = (PCIE_GT_DEVICE == "GTP") ? gtp_rst_qpllpd : qrst_qpllpd;
assign qpllreset[i>>2] = (PCIE_GT_DEVICE == "GTP") ? gtp_rst_qpllreset : (qrst_qpllreset || qdrp_qpllreset[i>>2]);
if ((PCIE_LINK_SPEED == 3) || (PCIE_PLL_SEL == "QPLL") || (PCIE_GT_DEVICE == "GTP"))
begin : gt_common_enabled
if (PCIE_EXT_GT_COMMON == "FALSE")
begin : gt_common_int
//---------- GT COMMON INTERNAL Module ---------------------------------------
PCIeGen2x8If128_gt_common #
(
.PCIE_SIM_MODE (PCIE_SIM_MODE), // PCIe sim mode
.PCIE_GT_DEVICE (PCIE_GT_DEVICE), // PCIe GT device
.PCIE_USE_MODE (PCIE_USE_MODE), // PCIe use mode
.PCIE_PLL_SEL (PCIE_PLL_SEL), // PCIe PLL select for Gen1/Gen2 only
.PCIE_REFCLK_FREQ (PCIE_REFCLK_FREQ) // PCIe reference clock frequency
)
gt_common_i
(
//---------- Input -------------------------
.CPLLPDREFCLK (gt_cpllpdrefclk),
.PIPE_CLK (PIPE_CLK),
.QPLL_QPLLPD (qpllpd),
.QPLL_QPLLRESET (qpllreset[i>>2]),
.QPLL_DRP_CLK (clk_dclk),
.QPLL_DRP_RST_N (rst_dclk_reset),
.QPLL_DRP_OVRD (qrst_ovrd),
.QPLL_DRP_GEN3 (&rate_gen3),
.QPLL_DRP_START (qrst_drp_start),
.QPLL_DRP_CRSCODE (qdrp_crscode[(6*(i>>2))+5:(6*(i>>2))]),
.QPLL_DRP_FSM (qdrp_fsm[(9*(i>>2))+8:(9*(i>>2))]),
.QPLL_DRP_DONE (qdrp_done[i>>2]),
.QPLL_DRP_RESET (qdrp_qpllreset[i>>2]),
.QPLL_QPLLOUTCLK (qpll_qplloutclk[i>>2]),
.QPLL_QPLLOUTREFCLK (qpll_qplloutrefclk[i>>2]),
.QPLL_QPLLLOCK (qpll_qplllock[i>>2])
);
assign QPLL_QPLLPD = 1'b0;
assign QPLL_QPLLRESET[i>>2] = 1'b0;
assign QPLL_DRP_CLK = 1'b0;
assign QPLL_DRP_RST_N = 1'b0;
assign QPLL_DRP_OVRD = 1'b0;
assign QPLL_DRP_GEN3 = 1'b0;
assign QPLL_DRP_START = 1'b0;
assign INT_QPLLLOCK_OUT[i>>2] = qpll_qplllock[i>>2] ;
assign INT_QPLLOUTREFCLK_OUT[i>>2] = qpll_qplloutrefclk[i>>2];
assign INT_QPLLOUTCLK_OUT[i>>2] = qpll_qplloutclk[i>>2];
end
else
begin : gt_common_ext
assign qdrp_done[i>>2] = QPLL_DRP_DONE[i>>2];
assign qdrp_qpllreset[i>>2] = QPLL_DRP_RESET[i>>2];
assign qdrp_crscode[(6*(i>>2))+5:(6*(i>>2))] = QPLL_DRP_CRSCODE[(6*(i>>2))+5:(6*(i>>2))];
assign qdrp_fsm[(9*(i>>2))+8:(9*(i>>2))] = QPLL_DRP_FSM[(9*(i>>2))+8:(9*(i>>2))];
assign qpll_qplloutclk[i>>2] = QPLL_QPLLOUTCLK[i>>2];
assign qpll_qplloutrefclk[i>>2] = QPLL_QPLLOUTREFCLK[i>>2];
assign qpll_qplllock[i>>2] = QPLL_QPLLLOCK[i>>2];
assign QPLL_QPLLPD = qpllpd;
assign QPLL_QPLLRESET[i>>2] = qpllreset[i>>2];
assign QPLL_DRP_CLK = clk_dclk;
assign QPLL_DRP_RST_N = rst_dclk_reset;
assign QPLL_DRP_OVRD = qrst_ovrd;
assign QPLL_DRP_GEN3 = &rate_gen3;
assign QPLL_DRP_START = qrst_drp_start;
assign INT_QPLLLOCK_OUT[i>>2] = 1'b0;
assign INT_QPLLOUTCLK_OUT[i>>2] = 1'b0;
assign INT_QPLLOUTREFCLK_OUT[i>>2] = 1'b0;
end
end
else
//---------- PIPE Common Defaults ----------------------------------
begin : gt_common_disabled
assign qdrp_done[i>>2] = 1'd0;
assign qdrp_crscode[(6*(i>>2))+5:(6*(i>>2))] = 6'd0;
assign qdrp_fsm[(9*(i>>2))+8:(9*(i>>2))] = 9'd0;
assign qpll_qplloutclk[i>>2] = 1'd0;
assign qpll_qplloutrefclk[i>>2] = 1'd0;
assign qpll_qplllock[i>>2] = 1'd0;
assign QPLL_QPLLPD = 1'b0;
assign QPLL_QPLLRESET[i>>2] = 1'b0;
assign QPLL_DRP_CLK = 1'b0;
assign QPLL_DRP_RST_N = 1'b0;
assign QPLL_DRP_OVRD = 1'b0;
assign QPLL_DRP_GEN3 = 1'b0;
assign QPLL_DRP_START = 1'b0;
assign INT_QPLLLOCK_OUT[i>>2] = 1'b0;
assign INT_QPLLOUTCLK_OUT[i>>2] = 1'b0;
assign INT_QPLLOUTREFCLK_OUT[i>>2] = 1'b0;
end
end
//---------- GT Wrapper ----------------------------------------------------
assign gt_txpmareset_i[i] = (user_txpmareset[i] || rate_txpmareset[i]);
assign gt_rxpmareset_i[i] = (user_rxpmareset[i] || rate_rxpmareset[i]);
PCIeGen2x8If128_gt_wrapper #
(
.PCIE_SIM_MODE (PCIE_SIM_MODE), // PCIe sim mode
.PCIE_SIM_SPEEDUP (PCIE_SIM_SPEEDUP), // PCIe sim speedup
.PCIE_SIM_TX_EIDLE_DRIVE_LEVEL (PCIE_SIM_TX_EIDLE_DRIVE_LEVEL), // PCIe sim TX electrical idle drive level
.PCIE_GT_DEVICE (PCIE_GT_DEVICE), // PCIe GT device
.PCIE_USE_MODE (PCIE_USE_MODE), // PCIe use mode
.PCIE_PLL_SEL (PCIE_PLL_SEL), // PCIe PLL select for Gen1/Gen2 only
.PCIE_LPM_DFE (PCIE_LPM_DFE), // PCIe LPM or DFE mode for Gen1/Gen2 only
.PCIE_LPM_DFE_GEN3 (PCIE_LPM_DFE_GEN3), // PCIe LPM or DFE mode for Gen3 only
.PCIE_ASYNC_EN (PCIE_ASYNC_EN), // PCIe async enable
.PCIE_TXBUF_EN (PCIE_TXBUF_EN), // PCIe TX buffer enable for Gen1/Gen2 only
.PCIE_TXSYNC_MODE (PCIE_TXSYNC_MODE), // PCIe TX sync mode
.PCIE_RXSYNC_MODE (PCIE_RXSYNC_MODE), // PCIe RX sync mode
.PCIE_CHAN_BOND (PCIE_CHAN_BOND), // PCIe Channel bonding mode
.PCIE_CHAN_BOND_EN (PCIE_CHAN_BOND_EN), // PCIe Channel bonding enable for Gen1/Gen2 only
.PCIE_LANE (PCIE_LANE), // PCIe number of lane
.PCIE_REFCLK_FREQ (PCIE_REFCLK_FREQ), // PCIe reference clock frequency
.PCIE_TX_EIDLE_ASSERT_DELAY (PCIE_TX_EIDLE_ASSERT_DELAY), // PCIe TX electrical idle assert delay
.PCIE_OOBCLK_MODE (PCIE_OOBCLK_MODE), // PCIe OOB clock mode
.TX_MARGIN_FULL_0 (TX_MARGIN_FULL_0),
.TX_MARGIN_FULL_1 (TX_MARGIN_FULL_1),
.TX_MARGIN_FULL_2 (TX_MARGIN_FULL_2),
.TX_MARGIN_FULL_3 (TX_MARGIN_FULL_3),
.TX_MARGIN_FULL_4 (TX_MARGIN_FULL_4),
.TX_MARGIN_LOW_0 (TX_MARGIN_LOW_0),
.TX_MARGIN_LOW_1 (TX_MARGIN_LOW_1),
.TX_MARGIN_LOW_2 (TX_MARGIN_LOW_2),
.TX_MARGIN_LOW_3 (TX_MARGIN_LOW_3),
.TX_MARGIN_LOW_4 (TX_MARGIN_LOW_4),
.PCIE_DEBUG_MODE (PCIE_DEBUG_MODE) // PCIe debug mode
)
gt_wrapper_i
(
//---------- GT User Ports -------------------------
.GT_MASTER (i == 0),
.GT_GEN3 (rate_gen3[i]),
.GT_RX_CONVERGE (&user_rx_converge),
//---------- GT Clock Ports ------------------------
.GT_GTREFCLK0 (PIPE_CLK),
.GT_QPLLCLK (qpll_qplloutclk[i>>2]),
.GT_QPLLREFCLK (qpll_qplloutrefclk[i>>2]),
.GT_TXUSRCLK (clk_pclk),
.GT_RXUSRCLK (clk_rxusrclk),
.GT_TXUSRCLK2 (clk_pclk),
.GT_RXUSRCLK2 (clk_rxusrclk),
.GT_OOBCLK (oobclk[i]),
.GT_TXSYSCLKSEL (rate_sysclksel[(2*i)+1:(2*i)]),
.GT_RXSYSCLKSEL (rate_sysclksel[(2*i)+1:(2*i)]),
.GT_CPLLPDREFCLK (gt_cpllpdrefclk),
.GT_TXOUTCLK (gt_txoutclk[i]),
.GT_RXOUTCLK (gt_rxoutclk[i]),
.GT_CPLLLOCK (gt_cplllock[i]),
.GT_RXCDRLOCK (gt_rxcdrlock[i]),
//---------- GT Reset Ports ------------------------
.GT_CPLLPD (rst_cpllpd || rate_cpllpd[i]),
.GT_CPLLRESET (rst_cpllreset || rate_cpllreset[i]),
.GT_TXUSERRDY (rst_userrdy),
.GT_RXUSERRDY (rst_userrdy),
.GT_RESETOVRD (user_resetovrd[i]),
.GT_GTTXRESET (rst_gtreset),
.GT_GTRXRESET (rst_gtreset),
.GT_TXPMARESET (gt_txpmareset_i[i]), // (user_txpmareset[i] || rate_txpmareset[i]),
.GT_RXPMARESET (gt_rxpmareset_i[i]), // (user_rxpmareset[i] || rate_rxpmareset[i]),
.GT_RXCDRRESET (user_rxcdrreset[i]),
.GT_RXCDRFREQRESET (user_rxcdrfreqreset[i]),
.GT_RXDFELPMRESET (user_rxdfelpmreset[i]),
.GT_EYESCANRESET (user_eyescanreset[i]),
.GT_TXPCSRESET (user_txpcsreset[i]),
.GT_RXPCSRESET (user_rxpcsreset[i]),
.GT_RXBUFRESET (user_rxbufreset[i]),
.GT_EYESCANDATAERROR (gt_eyescandataerror[i]),
.GT_TXRESETDONE (gt_txresetdone[i]),
.GT_RXRESETDONE (gt_rxresetdone[i]),
.GT_RXPMARESETDONE (gt_rxpmaresetdone[i]),
//---------- GT TX Data Ports ----------------------
.GT_TXDATA (PIPE_TXDATA[(32*i)+31:(32*i)]),
.GT_TXDATAK (PIPE_TXDATAK[(4*i)+3:(4*i)]),
.GT_TXP (PIPE_TXP[i]),
.GT_TXN (PIPE_TXN[i]),
//---------- GT RX Data Ports ----------------------
.GT_RXP (PIPE_RXP[i]),
.GT_RXN (PIPE_RXN[i]),
.GT_RXDATA (PIPE_RXDATA[(32*i)+31:(32*i)]),
.GT_RXDATAK (PIPE_RXDATAK[(4*i)+3:(4*i)]),
//---------- GT Command Ports ----------------------
.GT_TXDETECTRX (PIPE_TXDETECTRX),
.GT_TXELECIDLE (PIPE_TXELECIDLE[i]),
.GT_TXCOMPLIANCE (PIPE_TXCOMPLIANCE[i]),
.GT_RXPOLARITY (PIPE_RXPOLARITY[i]),
.GT_TXPOWERDOWN (PIPE_POWERDOWN[(2*i)+1:(2*i)]),
.GT_RXPOWERDOWN (PIPE_POWERDOWN[(2*i)+1:(2*i)]),
.GT_TXRATE (rate_rate[(3*i)+2:(3*i)]),
.GT_RXRATE (rate_rate[(3*i)+2:(3*i)]),
//---------- GT Electrical Command Ports -----------
.GT_TXMARGIN (PIPE_TXMARGIN),
.GT_TXSWING (PIPE_TXSWING),
.GT_TXDEEMPH (PIPE_TXDEEMPH[i]),
.GT_TXINHIBIT (PIPE_TXINHIBIT[i]),
.GT_TXPRECURSOR (eq_txeq_precursor[(5*i)+4:(5*i)]),
.GT_TXMAINCURSOR (eq_txeq_maincursor[(7*i)+6:(7*i)]),
.GT_TXPOSTCURSOR (eq_txeq_postcursor[(5*i)+4:(5*i)]),
//---------- GT Status Ports -----------------------
.GT_RXVALID (gt_rxvalid[i]),
.GT_PHYSTATUS (gt_phystatus[i]),
.GT_RXELECIDLE (gt_rxelecidle[i]),
.GT_RXSTATUS (gt_rxstatus[(3*i)+2:(3*i)]),
.GT_RXBUFSTATUS (gt_rxbufstatus[(3*i)+2:(3*i)]),
.GT_TXRATEDONE (gt_txratedone[i]),
.GT_RXRATEDONE (gt_rxratedone[i]),
.GT_RXDISPERR (gt_rxdisperr[(8*i)+7:(8*i)]),
.GT_RXNOTINTABLE (gt_rxnotintable[(8*i)+7:(8*i)]),
//---------- GT DRP Ports --------------------------
.GT_DRPCLK (clk_dclk),
.GT_DRPADDR (drp_mux_addr[(9*i)+8:(9*i)]),
.GT_DRPEN (drp_mux_en[i]),
.GT_DRPDI (drp_mux_di[(16*i)+15:(16*i)]),
.GT_DRPWE (drp_mux_we[i]),
.GT_DRPDO (gt_do[(16*i)+15:(16*i)]),
.GT_DRPRDY (gt_rdy[i]),
//---------- GT TX Sync Ports ----------------------
.GT_TXPHALIGN (sync_txphalign[i]),
.GT_TXPHALIGNEN (sync_txphalignen[i]),
.GT_TXPHINIT (sync_txphinit[i]),
.GT_TXDLYBYPASS (sync_txdlybypass[i]),
.GT_TXDLYSRESET (sync_txdlysreset[i]),
.GT_TXDLYEN (sync_txdlyen[i]),
.GT_TXDLYSRESETDONE (gt_txdlysresetdone[i]),
.GT_TXPHINITDONE (gt_txphinitdone[i]),
.GT_TXPHALIGNDONE (gt_txphaligndone[i]),
.GT_TXPHDLYRESET (sync_txphdlyreset[i]),
.GT_TXSYNCMODE (i == 0), // GTH, GTP
.GT_TXSYNCIN (gt_txsyncout[0]), // GTH, GTP
.GT_TXSYNCALLIN (txsyncallin), // GTH, GTP
.GT_TXSYNCOUT (gt_txsyncout[i]), // GTH, GTP
.GT_TXSYNCDONE (gt_txsyncdone[i]), // GTH, GTP
//---------- GT RX Sync Ports ----------------------
.GT_RXPHALIGN (sync_rxphalign[i]),
.GT_RXPHALIGNEN (sync_rxphalignen[i]),
.GT_RXDLYBYPASS (sync_rxdlybypass[i]),
.GT_RXDLYSRESET (sync_rxdlysreset[i]),
.GT_RXDLYEN (sync_rxdlyen[i]),
.GT_RXDDIEN (sync_rxddien[i]),
.GT_RXDLYSRESETDONE (gt_rxdlysresetdone[i]),
.GT_RXPHALIGNDONE (gt_rxphaligndone[i]),
.GT_RXSYNCMODE (i == 0), // GTH
.GT_RXSYNCIN (gt_rxsyncout[0]), // GTH
.GT_RXSYNCALLIN (rxsyncallin), // GTH
.GT_RXSYNCOUT (gt_rxsyncout[i]), // GTH
.GT_RXSYNCDONE (gt_rxsyncdone[i]), // GTH
//---------- GT Comma Alignment Ports --------------
.GT_RXSLIDE (PIPE_RXSLIDE[i]),
.GT_RXCOMMADET (gt_rxcommadet[i]),
.GT_RXCHARISCOMMA (gt_rxchariscomma[(4*i)+3:(4*i)]),
.GT_RXBYTEISALIGNED (gt_rxbyteisaligned[i]),
.GT_RXBYTEREALIGN (gt_rxbyterealign[i]),
//---------- GT Channel Bonding Ports --------------
.GT_RXCHANISALIGNED (PIPE_RXCHANISALIGNED[i]),
.GT_RXCHBONDEN (rxchbonden[i]),
.GT_RXCHBONDI (gt_rxchbondi[i]),
.GT_RXCHBONDLEVEL (gt_rxchbondlevel[(3*i)+2:(3*i)]),
.GT_RXCHBONDMASTER (rxchbondmaster[i]),
.GT_RXCHBONDSLAVE (rxchbondslave[i]),
.GT_RXCHBONDO (gt_rxchbondo[i+1]),
//---------- GT PRBS/Loopback Ports ----------------
.GT_TXPRBSSEL (PIPE_TXPRBSSEL),
.GT_RXPRBSSEL (PIPE_RXPRBSSEL),
.GT_TXPRBSFORCEERR (PIPE_TXPRBSFORCEERR),
.GT_RXPRBSCNTRESET (PIPE_RXPRBSCNTRESET),
.GT_LOOPBACK (PIPE_LOOPBACK),
.GT_RXPRBSERR (PIPE_RXPRBSERR[i]),
//---------- GT Debug Port -------------------------
.GT_DMONITOROUT (PIPE_DMONITOROUT[(15*i)+14:(15*i)])
);
//---------- GT Wrapper Assignments ----------------------------------------
assign oobclk[i] = (PCIE_OOBCLK_MODE == 1) ? user_oobclk[i] : clk_oobclk;
//---------- Channel Bonding Master Slave Enable ---------------------------
if (PCIE_CHAN_BOND_EN == "FALSE")
begin : channel_bonding_ms_disable
assign rxchbonden[i] = 1'd0;
assign rxchbondmaster[i] = 1'd0;
assign rxchbondslave[i] = 1'd0;
end
else
begin : channel_bonding_ms_enable
assign rxchbonden[i] = (PCIE_LANE > 1) && (PCIE_CHAN_BOND_EN == "TRUE") ? !rate_gen3[i] : 1'd0;
assign rxchbondmaster[i] = rate_gen3[i] ? 1'd0 : (i == 0);
assign rxchbondslave[i] = rate_gen3[i] ? 1'd0 : (i > 0);
end
//---------- Channel Bonding Input Connection ------------------------------
if (PCIE_CHAN_BOND_EN == "FALSE")
begin : channel_bonding_in_disable
assign gt_rxchbondi[i] = 5'd0;
assign gt_rxchbondlevel[(3*i)+2:(3*i)] = 3'd0;
end
else
begin : channel_bonding_in_enable
//---------- Channel Bonding (2: Binary-Tree) --------------------------
if (PCIE_CHAN_BOND == 2)
begin : channel_bonding_a
case (i)
//---------- Lane 0 --------------------------------
0 :
begin
assign gt_rxchbondi[0] = gt_rxchbondo[0];
assign gt_rxchbondlevel[2:0] = (PCIE_LANE == 4'd8) ? 3'd4 :
(PCIE_LANE > 4'd5) ? 3'd3 :
(PCIE_LANE > 4'd3) ? 3'd2 :
(PCIE_LANE > 4'd1) ? 3'd1 : 3'd0;
end
//---------- Lane 1 --------------------------------
1 :
begin
assign gt_rxchbondi[1] = gt_rxchbondo[1];
assign gt_rxchbondlevel[5:3] = (PCIE_LANE == 4'd8) ? 3'd3 :
(PCIE_LANE > 4'd5) ? 3'd2 :
(PCIE_LANE > 4'd3) ? 3'd1 : 3'd0;
end
//---------- Lane 2 --------------------------------
2 :
begin
assign gt_rxchbondi[2] = gt_rxchbondo[1];
assign gt_rxchbondlevel[8:6] = (PCIE_LANE == 4'd8) ? 3'd3 :
(PCIE_LANE > 4'd5) ? 3'd2 :
(PCIE_LANE > 4'd3) ? 3'd1 : 3'd0;
end
//---------- Lane 3 --------------------------------
3 :
begin
assign gt_rxchbondi[3] = gt_rxchbondo[3];
assign gt_rxchbondlevel[11:9] = (PCIE_LANE == 4'd8) ? 3'd2 :
(PCIE_LANE > 4'd5) ? 3'd1 : 3'd0;
end
//---------- Lane 4 --------------------------------
4 :
begin
assign gt_rxchbondi[4] = gt_rxchbondo[3];
assign gt_rxchbondlevel[14:12] = (PCIE_LANE == 4'd8) ? 3'd2 :
(PCIE_LANE > 4'd5) ? 3'd1 : 3'd0;
end
//---------- Lane 5 --------------------------------
5 :
begin
assign gt_rxchbondi[5] = gt_rxchbondo[5];
assign gt_rxchbondlevel[17:15] = (PCIE_LANE == 4'd8) ? 3'd1 : 3'd0;
end
//---------- Lane 6 --------------------------------
6 :
begin
assign gt_rxchbondi[6] = gt_rxchbondo[5];
assign gt_rxchbondlevel[20:18] = (PCIE_LANE == 4'd8) ? 3'd1 : 3'd0;
end
//---------- Lane 7 --------------------------------
7 :
begin
assign gt_rxchbondi[7] = gt_rxchbondo[7];
assign gt_rxchbondlevel[23:21] = 3'd0;
end
//---------- Default -------------------------------
default :
begin
assign gt_rxchbondi[i] = gt_rxchbondo[7];
assign gt_rxchbondlevel[(3*i)+2:(3*i)] = 3'd0;
end
endcase
end
//---------- Channel Bonding (0: One-Hop, 1: Daisy Chain) --------------
else
begin : channel_bonding_b
assign gt_rxchbondi[i] = (PCIE_CHAN_BOND == 1) ? gt_rxchbondo[i] : ((i == 0) ? gt_rxchbondo[0] : gt_rxchbondo[1]);
assign gt_rxchbondlevel[(3*i)+2:(3*i)] = (PCIE_CHAN_BOND == 1) ? (PCIE_LANE-1)-i : ((PCIE_LANE > 1) && (i == 0));
end
end
end
endgenerate
//---------- PIPE Wrapper Output -----------------------------------------------
assign PIPE_TXEQ_FS = 0;//TXEQ_FS;
assign PIPE_TXEQ_LF = 0;//TXEQ_LF;
assign PIPE_RXELECIDLE = gt_rxelecidle;
assign PIPE_RXSTATUS = gt_rxstatus;
assign PIPE_RXDISPERR = gt_rxdisperr;
assign PIPE_RXNOTINTABLE = gt_rxnotintable;
assign PIPE_RXPMARESETDONE = gt_rxpmaresetdone;
assign PIPE_RXBUFSTATUS = gt_rxbufstatus;
assign PIPE_TXPHALIGNDONE = gt_txphaligndone;
assign PIPE_TXPHINITDONE = gt_txphinitdone;
assign PIPE_TXDLYSRESETDONE = gt_txdlysresetdone;
assign PIPE_RXPHALIGNDONE = gt_rxphaligndone;
assign PIPE_RXDLYSRESETDONE = gt_rxdlysresetdone;
assign PIPE_RXSYNCDONE = gt_rxsyncdone;
assign PIPE_RXCOMMADET = gt_rxcommadet;
assign PIPE_QPLL_LOCK = qpll_qplllock;
assign PIPE_CPLL_LOCK = gt_cplllock;
assign PIPE_PCLK = clk_pclk;
assign PIPE_PCLK_LOCK = clk_mmcm_lock;
assign PIPE_RXCDRLOCK = 0;//user_rxcdrlock;
assign PIPE_RXUSRCLK = 0;//clk_rxusrclk;
assign PIPE_RXOUTCLK = 0;//clk_rxoutclk;
assign PIPE_TXSYNC_DONE = 0;//sync_txsync_done;
assign PIPE_RXSYNC_DONE = 0;//sync_rxsync_done;
assign PIPE_ACTIVE_LANE = 0;//user_active_lane;
assign PIPE_TXOUTCLK_OUT = gt_txoutclk[0];
assign PIPE_RXOUTCLK_OUT = gt_rxoutclk;
assign PIPE_PCLK_SEL_OUT = rate_pclk_sel;
assign PIPE_GEN3_OUT = rate_gen3[0];
assign PIPE_RXEQ_CONVERGE = user_rx_converge;
assign PIPE_RXEQ_ADAPT_DONE = (PCIE_GT_DEVICE == "GTP") ? {PCIE_LANE{1'd0}} : eq_rxeq_adapt_done;
assign PIPE_EYESCANDATAERROR = gt_eyescandataerror;
assign PIPE_RST_FSM = rst_fsm;
assign PIPE_QRST_FSM = qrst_fsm;
assign PIPE_RATE_FSM = rate_fsm;
assign PIPE_SYNC_FSM_TX = sync_fsm_tx;
assign PIPE_SYNC_FSM_RX = sync_fsm_rx;
assign PIPE_DRP_FSM = drp_fsm;
assign PIPE_QDRP_FSM = 0;//qdrp_fsm;
assign PIPE_RST_IDLE = &rst_idle;
assign PIPE_QRST_IDLE = &qrst_idle;
assign PIPE_RATE_IDLE = &rate_idle;
assign EXT_CH_GT_DRPDO = gt_do[(PCIE_LANE*16)-1:0];
assign EXT_CH_GT_DRPRDY = gt_rdy[(PCIE_LANE-1):0];
assign EXT_CH_GT_DRPCLK = clk_dclk;
assign PIPE_DEBUG_0 = (PCIE_DEBUG_MODE == 1) ? gt_txresetdone : {PCIE_LANE{1'b0}};
assign PIPE_DEBUG_1 = (PCIE_DEBUG_MODE == 1) ? gt_rxresetdone : {PCIE_LANE{1'b0}};
assign PIPE_DEBUG_2 = (PCIE_DEBUG_MODE == 1) ? gt_phystatus : {PCIE_LANE{1'b0}};
assign PIPE_DEBUG_3 = (PCIE_DEBUG_MODE == 1) ? gt_rxvalid : {PCIE_LANE{1'b0}};
assign PIPE_DEBUG_4 = (PCIE_DEBUG_MODE == 1) ? clk_dclk : {PCIE_LANE{1'b0}};
assign PIPE_DEBUG_5 = (PCIE_DEBUG_MODE == 1) ? drp_mux_en : {PCIE_LANE{1'b0}};
assign PIPE_DEBUG_6 = (PCIE_DEBUG_MODE == 1) ? drp_mux_we : {PCIE_LANE{1'b0}};
assign PIPE_DEBUG_7 = (PCIE_DEBUG_MODE == 1) ? gt_rdy : {PCIE_LANE{1'b0}};
assign PIPE_DEBUG_8 = (PCIE_DEBUG_MODE == 1) ? user_rx_converge : {PCIE_LANE{1'b0}};
assign PIPE_DEBUG_9 = (PCIE_DEBUG_MODE == 1) ? PIPE_TXELECIDLE : {PCIE_LANE{1'b0}};
assign PIPE_DEBUG[ 1:0] = (PCIE_DEBUG_MODE == 1) ? PIPE_TXEQ_CONTROL[1:0] : 2'd0;
assign PIPE_DEBUG[ 5:2] = (PCIE_DEBUG_MODE == 1) ? PIPE_TXEQ_PRESET[3:0] : 4'd0;
assign PIPE_DEBUG[31:6] = 26'd0;
endmodule
|
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2012 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
(** * Int31 numbers defines indeed a cyclic structure : Z/(2^31)Z *)
(**
Author: Arnaud Spiwack (+ Pierre Letouzey)
*)
Require Import List.
Require Import Min.
Require Export Int31.
Require Import Znumtheory.
Require Import Zgcd_alt.
Require Import Zpow_facts.
Require Import BigNumPrelude.
Require Import CyclicAxioms.
Require Import ROmega.
Local Open Scope nat_scope.
Local Open Scope int31_scope.
Section Basics.
(** * Basic results about [iszero], [shiftl], [shiftr] *)
Lemma iszero_eq0 : forall x, iszero x = true -> x=0.
Proof.
destruct x; simpl; intros.
repeat
match goal with H:(if ?d then _ else _) = true |- _ =>
destruct d; try discriminate
end.
reflexivity.
Qed.
Lemma iszero_not_eq0 : forall x, iszero x = false -> x<>0.
Proof.
intros x H Eq; rewrite Eq in H; simpl in *; discriminate.
Qed.
Lemma sneakl_shiftr : forall x,
x = sneakl (firstr x) (shiftr x).
Proof.
destruct x; simpl; auto.
Qed.
Lemma sneakr_shiftl : forall x,
x = sneakr (firstl x) (shiftl x).
Proof.
destruct x; simpl; auto.
Qed.
Lemma twice_zero : forall x,
twice x = 0 <-> twice_plus_one x = 1.
Proof.
destruct x; simpl in *; split;
intro H; injection H; intros; subst; auto.
Qed.
Lemma twice_or_twice_plus_one : forall x,
x = twice (shiftr x) \/ x = twice_plus_one (shiftr x).
Proof.
intros; case_eq (firstr x); intros.
destruct x; simpl in *; rewrite H; auto.
destruct x; simpl in *; rewrite H; auto.
Qed.
(** * Iterated shift to the right *)
Definition nshiftr n x := iter_nat n _ shiftr x.
Lemma nshiftr_S :
forall n x, nshiftr (S n) x = shiftr (nshiftr n x).
Proof.
reflexivity.
Qed.
Lemma nshiftr_S_tail :
forall n x, nshiftr (S n) x = nshiftr n (shiftr x).
Proof.
induction n; simpl; auto.
intros; rewrite nshiftr_S, IHn, nshiftr_S; auto.
Qed.
Lemma nshiftr_n_0 : forall n, nshiftr n 0 = 0.
Proof.
induction n; simpl; auto.
rewrite nshiftr_S, IHn; auto.
Qed.
Lemma nshiftr_size : forall x, nshiftr size x = 0.
Proof.
destruct x; simpl; auto.
Qed.
Lemma nshiftr_above_size : forall k x, size<=k ->
nshiftr k x = 0.
Proof.
intros.
replace k with ((k-size)+size)%nat by omega.
induction (k-size)%nat; auto.
rewrite nshiftr_size; auto.
simpl; rewrite nshiftr_S, IHn; auto.
Qed.
(** * Iterated shift to the left *)
Definition nshiftl n x := iter_nat n _ shiftl x.
Lemma nshiftl_S :
forall n x, nshiftl (S n) x = shiftl (nshiftl n x).
Proof.
reflexivity.
Qed.
Lemma nshiftl_S_tail :
forall n x, nshiftl (S n) x = nshiftl n (shiftl x).
Proof.
induction n; simpl; auto.
intros; rewrite nshiftl_S, IHn, nshiftl_S; auto.
Qed.
Lemma nshiftl_n_0 : forall n, nshiftl n 0 = 0.
Proof.
induction n; simpl; auto.
rewrite nshiftl_S, IHn; auto.
Qed.
Lemma nshiftl_size : forall x, nshiftl size x = 0.
Proof.
destruct x; simpl; auto.
Qed.
Lemma nshiftl_above_size : forall k x, size<=k ->
nshiftl k x = 0.
Proof.
intros.
replace k with ((k-size)+size)%nat by omega.
induction (k-size)%nat; auto.
rewrite nshiftl_size; auto.
simpl; rewrite nshiftl_S, IHn; auto.
Qed.
Lemma firstr_firstl :
forall x, firstr x = firstl (nshiftl (pred size) x).
Proof.
destruct x; simpl; auto.
Qed.
Lemma firstl_firstr :
forall x, firstl x = firstr (nshiftr (pred size) x).
Proof.
destruct x; simpl; auto.
Qed.
(** More advanced results about [nshiftr] *)
Lemma nshiftr_predsize_0_firstl : forall x,
nshiftr (pred size) x = 0 -> firstl x = D0.
Proof.
destruct x; compute; intros H; injection H; intros; subst; auto.
Qed.
Lemma nshiftr_0_propagates : forall n p x, n <= p ->
nshiftr n x = 0 -> nshiftr p x = 0.
Proof.
intros.
replace p with ((p-n)+n)%nat by omega.
induction (p-n)%nat.
simpl; auto.
simpl; rewrite nshiftr_S; rewrite IHn0; auto.
Qed.
Lemma nshiftr_0_firstl : forall n x, n < size ->
nshiftr n x = 0 -> firstl x = D0.
Proof.
intros.
apply nshiftr_predsize_0_firstl.
apply nshiftr_0_propagates with n; auto; omega.
Qed.
(** * Some induction principles over [int31] *)
(** Not used for the moment. Are they really useful ? *)
Lemma int31_ind_sneakl : forall P : int31->Prop,
P 0 ->
(forall x d, P x -> P (sneakl d x)) ->
forall x, P x.
Proof.
intros.
assert (forall n, n<=size -> P (nshiftr (size - n) x)).
induction n; intros.
rewrite nshiftr_size; auto.
rewrite sneakl_shiftr.
apply H0.
change (P (nshiftr (S (size - S n)) x)).
replace (S (size - S n))%nat with (size - n)%nat by omega.
apply IHn; omega.
change x with (nshiftr (size-size) x); auto.
Qed.
Lemma int31_ind_twice : forall P : int31->Prop,
P 0 ->
(forall x, P x -> P (twice x)) ->
(forall x, P x -> P (twice_plus_one x)) ->
forall x, P x.
Proof.
induction x using int31_ind_sneakl; auto.
destruct d; auto.
Qed.
(** * Some generic results about [recr] *)
Section Recr.
(** [recr] satisfies the fixpoint equation used for its definition. *)
Variable (A:Type)(case0:A)(caserec:digits->int31->A->A).
Lemma recr_aux_eqn : forall n x, iszero x = false ->
recr_aux (S n) A case0 caserec x =
caserec (firstr x) (shiftr x) (recr_aux n A case0 caserec (shiftr x)).
Proof.
intros; simpl; rewrite H; auto.
Qed.
Lemma recr_aux_converges :
forall n p x, n <= size -> n <= p ->
recr_aux n A case0 caserec (nshiftr (size - n) x) =
recr_aux p A case0 caserec (nshiftr (size - n) x).
Proof.
induction n.
simpl; intros.
rewrite nshiftr_size; destruct p; simpl; auto.
intros.
destruct p.
inversion H0.
unfold recr_aux; fold recr_aux.
destruct (iszero (nshiftr (size - S n) x)); auto.
f_equal.
change (shiftr (nshiftr (size - S n) x)) with (nshiftr (S (size - S n)) x).
replace (S (size - S n))%nat with (size - n)%nat by omega.
apply IHn; auto with arith.
Qed.
Lemma recr_eqn : forall x, iszero x = false ->
recr A case0 caserec x =
caserec (firstr x) (shiftr x) (recr A case0 caserec (shiftr x)).
Proof.
intros.
unfold recr.
change x with (nshiftr (size - size) x).
rewrite (recr_aux_converges size (S size)); auto with arith.
rewrite recr_aux_eqn; auto.
Qed.
(** [recr] is usually equivalent to a variant [recrbis]
written without [iszero] check. *)
Fixpoint recrbis_aux (n:nat)(A:Type)(case0:A)(caserec:digits->int31->A->A)
(i:int31) : A :=
match n with
| O => case0
| S next =>
let si := shiftr i in
caserec (firstr i) si (recrbis_aux next A case0 caserec si)
end.
Definition recrbis := recrbis_aux size.
Hypothesis case0_caserec : caserec D0 0 case0 = case0.
Lemma recrbis_aux_equiv : forall n x,
recrbis_aux n A case0 caserec x = recr_aux n A case0 caserec x.
Proof.
induction n; simpl; auto; intros.
case_eq (iszero x); intros; [ | f_equal; auto ].
rewrite (iszero_eq0 _ H); simpl; auto.
replace (recrbis_aux n A case0 caserec 0) with case0; auto.
clear H IHn; induction n; simpl; congruence.
Qed.
Lemma recrbis_equiv : forall x,
recrbis A case0 caserec x = recr A case0 caserec x.
Proof.
intros; apply recrbis_aux_equiv; auto.
Qed.
End Recr.
(** * Incrementation *)
Section Incr.
(** Variant of [incr] via [recrbis] *)
Let Incr (b : digits) (si rec : int31) :=
match b with
| D0 => sneakl D1 si
| D1 => sneakl D0 rec
end.
Definition incrbis_aux n x := recrbis_aux n _ In Incr x.
Lemma incrbis_aux_equiv : forall x, incrbis_aux size x = incr x.
Proof.
unfold incr, recr, incrbis_aux; fold Incr; intros.
apply recrbis_aux_equiv; auto.
Qed.
(** Recursive equations satisfied by [incr] *)
Lemma incr_eqn1 :
forall x, firstr x = D0 -> incr x = twice_plus_one (shiftr x).
Proof.
intros.
case_eq (iszero x); intros.
rewrite (iszero_eq0 _ H0); simpl; auto.
unfold incr; rewrite recr_eqn; fold incr; auto.
rewrite H; auto.
Qed.
Lemma incr_eqn2 :
forall x, firstr x = D1 -> incr x = twice (incr (shiftr x)).
Proof.
intros.
case_eq (iszero x); intros.
rewrite (iszero_eq0 _ H0) in H; simpl in H; discriminate.
unfold incr; rewrite recr_eqn; fold incr; auto.
rewrite H; auto.
Qed.
Lemma incr_twice : forall x, incr (twice x) = twice_plus_one x.
Proof.
intros.
rewrite incr_eqn1; destruct x; simpl; auto.
Qed.
Lemma incr_twice_plus_one_firstl :
forall x, firstl x = D0 -> incr (twice_plus_one x) = twice (incr x).
Proof.
intros.
rewrite incr_eqn2; [ | destruct x; simpl; auto ].
f_equal; f_equal.
destruct x; simpl in *; rewrite H; auto.
Qed.
(** The previous result is actually true even without the
constraint on [firstl], but this is harder to prove
(see later). *)
End Incr.
(** * Conversion to [Z] : the [phi] function *)
Section Phi.
(** Variant of [phi] via [recrbis] *)
Let Phi := fun b (_:int31) =>
match b with D0 => Z.double | D1 => Z.succ_double end.
Definition phibis_aux n x := recrbis_aux n _ Z0 Phi x.
Lemma phibis_aux_equiv : forall x, phibis_aux size x = phi x.
Proof.
unfold phi, recr, phibis_aux; fold Phi; intros.
apply recrbis_aux_equiv; auto.
Qed.
(** Recursive equations satisfied by [phi] *)
Lemma phi_eqn1 : forall x, firstr x = D0 ->
phi x = Z.double (phi (shiftr x)).
Proof.
intros.
case_eq (iszero x); intros.
rewrite (iszero_eq0 _ H0); simpl; auto.
intros; unfold phi; rewrite recr_eqn; fold phi; auto.
rewrite H; auto.
Qed.
Lemma phi_eqn2 : forall x, firstr x = D1 ->
phi x = Z.succ_double (phi (shiftr x)).
Proof.
intros.
case_eq (iszero x); intros.
rewrite (iszero_eq0 _ H0) in H; simpl in H; discriminate.
intros; unfold phi; rewrite recr_eqn; fold phi; auto.
rewrite H; auto.
Qed.
Lemma phi_twice_firstl : forall x, firstl x = D0 ->
phi (twice x) = Z.double (phi x).
Proof.
intros.
rewrite phi_eqn1; auto; [ | destruct x; auto ].
f_equal; f_equal.
destruct x; simpl in *; rewrite H; auto.
Qed.
Lemma phi_twice_plus_one_firstl : forall x, firstl x = D0 ->
phi (twice_plus_one x) = Z.succ_double (phi x).
Proof.
intros.
rewrite phi_eqn2; auto; [ | destruct x; auto ].
f_equal; f_equal.
destruct x; simpl in *; rewrite H; auto.
Qed.
End Phi.
(** [phi x] is positive and lower than [2^31] *)
Lemma phibis_aux_pos : forall n x, (0 <= phibis_aux n x)%Z.
Proof.
induction n.
simpl; unfold phibis_aux; simpl; auto with zarith.
intros.
unfold phibis_aux, recrbis_aux; fold recrbis_aux;
fold (phibis_aux n (shiftr x)).
destruct (firstr x).
specialize IHn with (shiftr x); rewrite Z.double_spec; omega.
specialize IHn with (shiftr x); rewrite Z.succ_double_spec; omega.
Qed.
Lemma phibis_aux_bounded :
forall n x, n <= size ->
(phibis_aux n (nshiftr (size-n) x) < 2 ^ (Z.of_nat n))%Z.
Proof.
induction n.
simpl; unfold phibis_aux; simpl; auto with zarith.
intros.
unfold phibis_aux, recrbis_aux; fold recrbis_aux;
fold (phibis_aux n (shiftr (nshiftr (size - S n) x))).
assert (shiftr (nshiftr (size - S n) x) = nshiftr (size-n) x).
replace (size - n)%nat with (S (size - (S n))) by omega.
simpl; auto.
rewrite H0.
assert (H1 : n <= size) by omega.
specialize (IHn x H1).
set (y:=phibis_aux n (nshiftr (size - n) x)) in *.
rewrite Nat2Z.inj_succ, Z.pow_succ_r; auto with zarith.
case_eq (firstr (nshiftr (size - S n) x)); intros.
rewrite Z.double_spec; auto with zarith.
rewrite Z.succ_double_spec; auto with zarith.
Qed.
Lemma phi_bounded : forall x, (0 <= phi x < 2 ^ (Z.of_nat size))%Z.
Proof.
intros.
rewrite <- phibis_aux_equiv.
split.
apply phibis_aux_pos.
change x with (nshiftr (size-size) x).
apply phibis_aux_bounded; auto.
Qed.
Lemma phibis_aux_lowerbound :
forall n x, firstr (nshiftr n x) = D1 ->
(2 ^ Z.of_nat n <= phibis_aux (S n) x)%Z.
Proof.
induction n.
intros.
unfold nshiftr in H; simpl in *.
unfold phibis_aux, recrbis_aux.
rewrite H, Z.succ_double_spec; omega.
intros.
remember (S n) as m.
unfold phibis_aux, recrbis_aux; fold recrbis_aux;
fold (phibis_aux m (shiftr x)).
subst m.
rewrite Nat2Z.inj_succ, Z.pow_succ_r; auto with zarith.
assert (2^(Z.of_nat n) <= phibis_aux (S n) (shiftr x))%Z.
apply IHn.
rewrite <- nshiftr_S_tail; auto.
destruct (firstr x).
change (Z.double (phibis_aux (S n) (shiftr x))) with
(2*(phibis_aux (S n) (shiftr x)))%Z.
omega.
rewrite Z.succ_double_spec; omega.
Qed.
Lemma phi_lowerbound :
forall x, firstl x = D1 -> (2^(Z.of_nat (pred size)) <= phi x)%Z.
Proof.
intros.
generalize (phibis_aux_lowerbound (pred size) x).
rewrite <- firstl_firstr.
change (S (pred size)) with size; auto.
rewrite phibis_aux_equiv; auto.
Qed.
(** * Equivalence modulo [2^n] *)
Section EqShiftL.
(** After killing [n] bits at the left, are the numbers equal ?*)
Definition EqShiftL n x y :=
nshiftl n x = nshiftl n y.
Lemma EqShiftL_zero : forall x y, EqShiftL O x y <-> x = y.
Proof.
unfold EqShiftL; intros; unfold nshiftl; simpl; split; auto.
Qed.
Lemma EqShiftL_size : forall k x y, size<=k -> EqShiftL k x y.
Proof.
red; intros; rewrite 2 nshiftl_above_size; auto.
Qed.
Lemma EqShiftL_le : forall k k' x y, k <= k' ->
EqShiftL k x y -> EqShiftL k' x y.
Proof.
unfold EqShiftL; intros.
replace k' with ((k'-k)+k)%nat by omega.
remember (k'-k)%nat as n.
clear Heqn H k'.
induction n; simpl; auto.
rewrite 2 nshiftl_S; f_equal; auto.
Qed.
Lemma EqShiftL_firstr : forall k x y, k < size ->
EqShiftL k x y -> firstr x = firstr y.
Proof.
intros.
rewrite 2 firstr_firstl.
f_equal.
apply EqShiftL_le with k; auto.
unfold size.
auto with arith.
Qed.
Lemma EqShiftL_twice : forall k x y,
EqShiftL k (twice x) (twice y) <-> EqShiftL (S k) x y.
Proof.
intros; unfold EqShiftL.
rewrite 2 nshiftl_S_tail; split; auto.
Qed.
(** * From int31 to list of digits. *)
(** Lower (=rightmost) bits comes first. *)
Definition i2l := recrbis _ nil (fun d _ rec => d::rec).
Lemma i2l_length : forall x, length (i2l x) = size.
Proof.
intros; reflexivity.
Qed.
Fixpoint lshiftl l x :=
match l with
| nil => x
| d::l => sneakl d (lshiftl l x)
end.
Definition l2i l := lshiftl l On.
Lemma l2i_i2l : forall x, l2i (i2l x) = x.
Proof.
destruct x; compute; auto.
Qed.
Lemma i2l_sneakr : forall x d,
i2l (sneakr d x) = tail (i2l x) ++ d::nil.
Proof.
destruct x; compute; auto.
Qed.
Lemma i2l_sneakl : forall x d,
i2l (sneakl d x) = d :: removelast (i2l x).
Proof.
destruct x; compute; auto.
Qed.
Lemma i2l_l2i : forall l, length l = size ->
i2l (l2i l) = l.
Proof.
repeat (destruct l as [ |? l]; [intros; discriminate | ]).
destruct l; [ | intros; discriminate].
intros _; compute; auto.
Qed.
Fixpoint cstlist (A:Type)(a:A) n :=
match n with
| O => nil
| S n => a::cstlist _ a n
end.
Lemma i2l_nshiftl : forall n x, n<=size ->
i2l (nshiftl n x) = cstlist _ D0 n ++ firstn (size-n) (i2l x).
Proof.
induction n.
intros.
assert (firstn (size-0) (i2l x) = i2l x).
rewrite <- minus_n_O, <- (i2l_length x).
induction (i2l x); simpl; f_equal; auto.
rewrite H0; clear H0.
reflexivity.
intros.
rewrite nshiftl_S.
unfold shiftl; rewrite i2l_sneakl.
simpl cstlist.
rewrite <- app_comm_cons; f_equal.
rewrite IHn; [ | omega].
rewrite removelast_app.
f_equal.
replace (size-n)%nat with (S (size - S n))%nat by omega.
rewrite removelast_firstn; auto.
rewrite i2l_length; omega.
generalize (firstn_length (size-n) (i2l x)).
rewrite i2l_length.
intros H0 H1; rewrite H1 in H0.
rewrite min_l in H0 by omega.
simpl length in H0.
omega.
Qed.
(** [i2l] can be used to define a relation equivalent to [EqShiftL] *)
Lemma EqShiftL_i2l : forall k x y,
EqShiftL k x y <-> firstn (size-k) (i2l x) = firstn (size-k) (i2l y).
Proof.
intros.
destruct (le_lt_dec size k).
split; intros.
replace (size-k)%nat with O by omega.
unfold firstn; auto.
apply EqShiftL_size; auto.
unfold EqShiftL.
assert (k <= size) by omega.
split; intros.
assert (i2l (nshiftl k x) = i2l (nshiftl k y)) by (f_equal; auto).
rewrite 2 i2l_nshiftl in H1; auto.
eapply app_inv_head; eauto.
assert (i2l (nshiftl k x) = i2l (nshiftl k y)).
rewrite 2 i2l_nshiftl; auto.
f_equal; auto.
rewrite <- (l2i_i2l (nshiftl k x)), <- (l2i_i2l (nshiftl k y)).
f_equal; auto.
Qed.
(** This equivalence allows to prove easily the following delicate
result *)
Lemma EqShiftL_twice_plus_one : forall k x y,
EqShiftL k (twice_plus_one x) (twice_plus_one y) <-> EqShiftL (S k) x y.
Proof.
intros.
destruct (le_lt_dec size k).
split; intros; apply EqShiftL_size; auto.
rewrite 2 EqShiftL_i2l.
unfold twice_plus_one.
rewrite 2 i2l_sneakl.
replace (size-k)%nat with (S (size - S k))%nat by omega.
remember (size - S k)%nat as n.
remember (i2l x) as lx.
remember (i2l y) as ly.
simpl.
rewrite 2 firstn_removelast.
split; intros.
injection H; auto.
f_equal; auto.
subst ly n; rewrite i2l_length; omega.
subst lx n; rewrite i2l_length; omega.
Qed.
Lemma EqShiftL_shiftr : forall k x y, EqShiftL k x y ->
EqShiftL (S k) (shiftr x) (shiftr y).
Proof.
intros.
destruct (le_lt_dec size (S k)).
apply EqShiftL_size; auto.
case_eq (firstr x); intros.
rewrite <- EqShiftL_twice.
unfold twice; rewrite <- H0.
rewrite <- sneakl_shiftr.
rewrite (EqShiftL_firstr k x y); auto.
rewrite <- sneakl_shiftr; auto.
omega.
rewrite <- EqShiftL_twice_plus_one.
unfold twice_plus_one; rewrite <- H0.
rewrite <- sneakl_shiftr.
rewrite (EqShiftL_firstr k x y); auto.
rewrite <- sneakl_shiftr; auto.
omega.
Qed.
Lemma EqShiftL_incrbis : forall n k x y, n<=size ->
(n+k=S size)%nat ->
EqShiftL k x y ->
EqShiftL k (incrbis_aux n x) (incrbis_aux n y).
Proof.
induction n; simpl; intros.
red; auto.
destruct (eq_nat_dec k size).
subst k; apply EqShiftL_size; auto.
unfold incrbis_aux; simpl;
fold (incrbis_aux n (shiftr x)); fold (incrbis_aux n (shiftr y)).
rewrite (EqShiftL_firstr k x y); auto; try omega.
case_eq (firstr y); intros.
rewrite EqShiftL_twice_plus_one.
apply EqShiftL_shiftr; auto.
rewrite EqShiftL_twice.
apply IHn; try omega.
apply EqShiftL_shiftr; auto.
Qed.
Lemma EqShiftL_incr : forall x y,
EqShiftL 1 x y -> EqShiftL 1 (incr x) (incr y).
Proof.
intros.
rewrite <- 2 incrbis_aux_equiv.
apply EqShiftL_incrbis; auto.
Qed.
End EqShiftL.
(** * More equations about [incr] *)
Lemma incr_twice_plus_one :
forall x, incr (twice_plus_one x) = twice (incr x).
Proof.
intros.
rewrite incr_eqn2; [ | destruct x; simpl; auto].
apply EqShiftL_incr.
red; destruct x; simpl; auto.
Qed.
Lemma incr_firstr : forall x, firstr (incr x) <> firstr x.
Proof.
intros.
case_eq (firstr x); intros.
rewrite incr_eqn1; auto.
destruct (shiftr x); simpl; discriminate.
rewrite incr_eqn2; auto.
destruct (incr (shiftr x)); simpl; discriminate.
Qed.
Lemma incr_inv : forall x y,
incr x = twice_plus_one y -> x = twice y.
Proof.
intros.
case_eq (iszero x); intros.
rewrite (iszero_eq0 _ H0) in *; simpl in *.
change (incr 0) with 1 in H.
symmetry; rewrite twice_zero; auto.
case_eq (firstr x); intros.
rewrite incr_eqn1 in H; auto.
clear H0; destruct x; destruct y; simpl in *.
injection H; intros; subst; auto.
elim (incr_firstr x).
rewrite H1, H; destruct y; simpl; auto.
Qed.
(** * Conversion from [Z] : the [phi_inv] function *)
(** First, recursive equations *)
Lemma phi_inv_double_plus_one : forall z,
phi_inv (Z.succ_double z) = twice_plus_one (phi_inv z).
Proof.
destruct z; simpl; auto.
induction p; simpl.
rewrite 2 incr_twice; auto.
rewrite incr_twice, incr_twice_plus_one.
f_equal.
apply incr_inv; auto.
auto.
Qed.
Lemma phi_inv_double : forall z,
phi_inv (Z.double z) = twice (phi_inv z).
Proof.
destruct z; simpl; auto.
rewrite incr_twice_plus_one; auto.
Qed.
Lemma phi_inv_incr : forall z,
phi_inv (Z.succ z) = incr (phi_inv z).
Proof.
destruct z.
simpl; auto.
simpl; auto.
induction p; simpl; auto.
rewrite <- Pos.add_1_r, IHp, incr_twice_plus_one; auto.
rewrite incr_twice; auto.
simpl; auto.
destruct p; simpl; auto.
rewrite incr_twice; auto.
f_equal.
rewrite incr_twice_plus_one; auto.
induction p; simpl; auto.
rewrite incr_twice; auto.
f_equal.
rewrite incr_twice_plus_one; auto.
Qed.
(** [phi_inv o inv], the always-exact and easy-to-prove trip :
from int31 to Z and then back to int31. *)
Lemma phi_inv_phi_aux :
forall n x, n <= size ->
phi_inv (phibis_aux n (nshiftr (size-n) x)) =
nshiftr (size-n) x.
Proof.
induction n.
intros; simpl.
rewrite nshiftr_size; auto.
intros.
unfold phibis_aux, recrbis_aux; fold recrbis_aux;
fold (phibis_aux n (shiftr (nshiftr (size-S n) x))).
assert (shiftr (nshiftr (size - S n) x) = nshiftr (size-n) x).
replace (size - n)%nat with (S (size - (S n))); auto; omega.
rewrite H0.
case_eq (firstr (nshiftr (size - S n) x)); intros.
rewrite phi_inv_double.
rewrite IHn by omega.
rewrite <- H0.
remember (nshiftr (size - S n) x) as y.
destruct y; simpl in H1; rewrite H1; auto.
rewrite phi_inv_double_plus_one.
rewrite IHn by omega.
rewrite <- H0.
remember (nshiftr (size - S n) x) as y.
destruct y; simpl in H1; rewrite H1; auto.
Qed.
Lemma phi_inv_phi : forall x, phi_inv (phi x) = x.
Proof.
intros.
rewrite <- phibis_aux_equiv.
replace x with (nshiftr (size - size) x) by auto.
apply phi_inv_phi_aux; auto.
Qed.
(** The other composition [phi o phi_inv] is harder to prove correct.
In particular, an overflow can happen, so a modulo is needed.
For the moment, we proceed via several steps, the first one
being a detour to [positive_to_in31]. *)
(** * [positive_to_int31] *)
(** A variant of [p2i] with [twice] and [twice_plus_one] instead of
[2*i] and [2*i+1] *)
Fixpoint p2ibis n p : (N*int31)%type :=
match n with
| O => (Npos p, On)
| S n => match p with
| xO p => let (r,i) := p2ibis n p in (r, twice i)
| xI p => let (r,i) := p2ibis n p in (r, twice_plus_one i)
| xH => (N0, In)
end
end.
Lemma p2ibis_bounded : forall n p,
nshiftr n (snd (p2ibis n p)) = 0.
Proof.
induction n.
simpl; intros; auto.
simpl; intros.
destruct p; simpl.
specialize IHn with p.
destruct (p2ibis n p); simpl in *.
rewrite nshiftr_S_tail.
destruct (le_lt_dec size n).
rewrite nshiftr_above_size; auto.
assert (H:=nshiftr_0_firstl _ _ l IHn).
replace (shiftr (twice_plus_one i)) with i; auto.
destruct i; simpl in *; rewrite H; auto.
specialize IHn with p.
destruct (p2ibis n p); simpl in *.
rewrite nshiftr_S_tail.
destruct (le_lt_dec size n).
rewrite nshiftr_above_size; auto.
assert (H:=nshiftr_0_firstl _ _ l IHn).
replace (shiftr (twice i)) with i; auto.
destruct i; simpl in *; rewrite H; auto.
rewrite nshiftr_S_tail; auto.
replace (shiftr In) with 0; auto.
apply nshiftr_n_0.
Qed.
Local Open Scope Z_scope.
Lemma p2ibis_spec : forall n p, (n<=size)%nat ->
Zpos p = (Z.of_N (fst (p2ibis n p)))*2^(Z.of_nat n) +
phi (snd (p2ibis n p)).
Proof.
induction n; intros.
simpl; rewrite Pos.mul_1_r; auto.
replace (2^(Z.of_nat (S n)))%Z with (2*2^(Z.of_nat n))%Z by
(rewrite <- Z.pow_succ_r, <- Zpos_P_of_succ_nat;
auto with zarith).
rewrite (Z.mul_comm 2).
assert (n<=size)%nat by omega.
destruct p; simpl; [ | | auto];
specialize (IHn p H0);
generalize (p2ibis_bounded n p);
destruct (p2ibis n p) as (r,i); simpl in *; intros.
change (Zpos p~1) with (2*Zpos p + 1)%Z.
rewrite phi_twice_plus_one_firstl, Z.succ_double_spec.
rewrite IHn; ring.
apply (nshiftr_0_firstl n); auto; try omega.
change (Zpos p~0) with (2*Zpos p)%Z.
rewrite phi_twice_firstl.
change (Z.double (phi i)) with (2*(phi i))%Z.
rewrite IHn; ring.
apply (nshiftr_0_firstl n); auto; try omega.
Qed.
(** We now prove that this [p2ibis] is related to [phi_inv_positive] *)
Lemma phi_inv_positive_p2ibis : forall n p, (n<=size)%nat ->
EqShiftL (size-n) (phi_inv_positive p) (snd (p2ibis n p)).
Proof.
induction n.
intros.
apply EqShiftL_size; auto.
intros.
simpl p2ibis; destruct p; [ | | red; auto];
specialize IHn with p;
destruct (p2ibis n p); simpl snd in *; simpl phi_inv_positive;
rewrite ?EqShiftL_twice_plus_one, ?EqShiftL_twice;
replace (S (size - S n))%nat with (size - n)%nat by omega;
apply IHn; omega.
Qed.
(** This gives the expected result about [phi o phi_inv], at least
for the positive case. *)
Lemma phi_phi_inv_positive : forall p,
phi (phi_inv_positive p) = (Zpos p) mod (2^(Z.of_nat size)).
Proof.
intros.
replace (phi_inv_positive p) with (snd (p2ibis size p)).
rewrite (p2ibis_spec size p) by auto.
rewrite Z.add_comm, Z_mod_plus.
symmetry; apply Zmod_small.
apply phi_bounded.
auto with zarith.
symmetry.
rewrite <- EqShiftL_zero.
apply (phi_inv_positive_p2ibis size p); auto.
Qed.
(** Moreover, [p2ibis] is also related with [p2i] and hence with
[positive_to_int31]. *)
Lemma double_twice_firstl : forall x, firstl x = D0 ->
(Twon*x = twice x)%int31.
Proof.
intros.
unfold mul31.
rewrite <- Z.double_spec, <- phi_twice_firstl, phi_inv_phi; auto.
Qed.
Lemma double_twice_plus_one_firstl : forall x, firstl x = D0 ->
(Twon*x+In = twice_plus_one x)%int31.
Proof.
intros.
rewrite double_twice_firstl; auto.
unfold add31.
rewrite phi_twice_firstl, <- Z.succ_double_spec,
<- phi_twice_plus_one_firstl, phi_inv_phi; auto.
Qed.
Lemma p2i_p2ibis : forall n p, (n<=size)%nat ->
p2i n p = p2ibis n p.
Proof.
induction n; simpl; auto; intros.
destruct p; auto; specialize IHn with p;
generalize (p2ibis_bounded n p);
rewrite IHn; try omega; destruct (p2ibis n p); simpl; intros;
f_equal; auto.
apply double_twice_plus_one_firstl.
apply (nshiftr_0_firstl n); auto; omega.
apply double_twice_firstl.
apply (nshiftr_0_firstl n); auto; omega.
Qed.
Lemma positive_to_int31_phi_inv_positive : forall p,
snd (positive_to_int31 p) = phi_inv_positive p.
Proof.
intros; unfold positive_to_int31.
rewrite p2i_p2ibis; auto.
symmetry.
rewrite <- EqShiftL_zero.
apply (phi_inv_positive_p2ibis size); auto.
Qed.
Lemma positive_to_int31_spec : forall p,
Zpos p = (Z.of_N (fst (positive_to_int31 p)))*2^(Z.of_nat size) +
phi (snd (positive_to_int31 p)).
Proof.
unfold positive_to_int31.
intros; rewrite p2i_p2ibis; auto.
apply p2ibis_spec; auto.
Qed.
(** Thanks to the result about [phi o phi_inv_positive], we can
now establish easily the most general results about
[phi o twice] and so one. *)
Lemma phi_twice : forall x,
phi (twice x) = (Z.double (phi x)) mod 2^(Z.of_nat size).
Proof.
intros.
pattern x at 1; rewrite <- (phi_inv_phi x).
rewrite <- phi_inv_double.
assert (0 <= Z.double (phi x)).
rewrite Z.double_spec; generalize (phi_bounded x); omega.
destruct (Z.double (phi x)).
simpl; auto.
apply phi_phi_inv_positive.
compute in H; elim H; auto.
Qed.
Lemma phi_twice_plus_one : forall x,
phi (twice_plus_one x) = (Z.succ_double (phi x)) mod 2^(Z.of_nat size).
Proof.
intros.
pattern x at 1; rewrite <- (phi_inv_phi x).
rewrite <- phi_inv_double_plus_one.
assert (0 <= Z.succ_double (phi x)).
rewrite Z.succ_double_spec; generalize (phi_bounded x); omega.
destruct (Z.succ_double (phi x)).
simpl; auto.
apply phi_phi_inv_positive.
compute in H; elim H; auto.
Qed.
Lemma phi_incr : forall x,
phi (incr x) = (Z.succ (phi x)) mod 2^(Z.of_nat size).
Proof.
intros.
pattern x at 1; rewrite <- (phi_inv_phi x).
rewrite <- phi_inv_incr.
assert (0 <= Z.succ (phi x)).
change (Z.succ (phi x)) with ((phi x)+1)%Z;
generalize (phi_bounded x); omega.
destruct (Z.succ (phi x)).
simpl; auto.
apply phi_phi_inv_positive.
compute in H; elim H; auto.
Qed.
(** With the previous results, we can deal with [phi o phi_inv] even
in the negative case *)
Lemma phi_phi_inv_negative :
forall p, phi (incr (complement_negative p)) = (Zneg p) mod 2^(Z.of_nat size).
Proof.
induction p.
simpl complement_negative.
rewrite phi_incr in IHp.
rewrite incr_twice, phi_twice_plus_one.
remember (phi (complement_negative p)) as q.
rewrite Z.succ_double_spec.
replace (2*q+1) with (2*(Z.succ q)-1) by omega.
rewrite <- Zminus_mod_idemp_l, <- Zmult_mod_idemp_r, IHp.
rewrite Zmult_mod_idemp_r, Zminus_mod_idemp_l; auto with zarith.
simpl complement_negative.
rewrite incr_twice_plus_one, phi_twice.
remember (phi (incr (complement_negative p))) as q.
rewrite Z.double_spec, IHp, Zmult_mod_idemp_r; auto with zarith.
simpl; auto.
Qed.
Lemma phi_phi_inv :
forall z, phi (phi_inv z) = z mod 2 ^ (Z.of_nat size).
Proof.
destruct z.
simpl; auto.
apply phi_phi_inv_positive.
apply phi_phi_inv_negative.
Qed.
End Basics.
Instance int31_ops : ZnZ.Ops int31 :=
{
digits := 31%positive; (* number of digits *)
zdigits := 31; (* number of digits *)
to_Z := phi; (* conversion to Z *)
of_pos := positive_to_int31; (* positive -> N*int31 : p => N,i
where p = N*2^31+phi i *)
head0 := head031; (* number of head 0 *)
tail0 := tail031; (* number of tail 0 *)
zero := 0;
one := 1;
minus_one := Tn; (* 2^31 - 1 *)
compare := compare31;
eq0 := fun i => match i ?= 0 with Eq => true | _ => false end;
opp_c := fun i => 0 -c i;
opp := opp31;
opp_carry := fun i => 0-i-1;
succ_c := fun i => i +c 1;
add_c := add31c;
add_carry_c := add31carryc;
succ := fun i => i + 1;
add := add31;
add_carry := fun i j => i + j + 1;
pred_c := fun i => i -c 1;
sub_c := sub31c;
sub_carry_c := sub31carryc;
pred := fun i => i - 1;
sub := sub31;
sub_carry := fun i j => i - j - 1;
mul_c := mul31c;
mul := mul31;
square_c := fun x => x *c x;
div21 := div3121;
div_gt := div31; (* this is supposed to be the special case of
division a/b where a > b *)
div := div31;
modulo_gt := fun i j => let (_,r) := i/j in r;
modulo := fun i j => let (_,r) := i/j in r;
gcd_gt := gcd31;
gcd := gcd31;
add_mul_div := addmuldiv31;
pos_mod := (* modulo 2^p *)
fun p i =>
match p ?= 31 with
| Lt => addmuldiv31 p 0 (addmuldiv31 (31-p) i 0)
| _ => i
end;
is_even :=
fun i => let (_,r) := i/2 in
match r ?= 0 with Eq => true | _ => false end;
sqrt2 := sqrt312;
sqrt := sqrt31
}.
Section Int31_Specs.
Local Open Scope Z_scope.
Notation "[| x |]" := (phi x) (at level 0, x at level 99).
Local Notation wB := (2 ^ (Z.of_nat size)).
Lemma wB_pos : wB > 0.
Proof.
auto with zarith.
Qed.
Notation "[+| c |]" :=
(interp_carry 1 wB phi c) (at level 0, x at level 99).
Notation "[-| c |]" :=
(interp_carry (-1) wB phi c) (at level 0, x at level 99).
Notation "[|| x ||]" :=
(zn2z_to_Z wB phi x) (at level 0, x at level 99).
Lemma spec_zdigits : [| 31 |] = 31.
Proof.
reflexivity.
Qed.
Lemma spec_more_than_1_digit: 1 < 31.
Proof.
auto with zarith.
Qed.
Lemma spec_0 : [| 0 |] = 0.
Proof.
reflexivity.
Qed.
Lemma spec_1 : [| 1 |] = 1.
Proof.
reflexivity.
Qed.
Lemma spec_m1 : [| Tn |] = wB - 1.
Proof.
reflexivity.
Qed.
Lemma spec_compare : forall x y,
(x ?= y)%int31 = ([|x|] ?= [|y|]).
Proof. reflexivity. Qed.
(** Addition *)
Lemma spec_add_c : forall x y, [+|add31c x y|] = [|x|] + [|y|].
Proof.
intros; unfold add31c, add31, interp_carry; rewrite phi_phi_inv.
generalize (phi_bounded x)(phi_bounded y); intros.
set (X:=[|x|]) in *; set (Y:=[|y|]) in *; clearbody X Y.
assert ((X+Y) mod wB ?= X+Y <> Eq -> [+|C1 (phi_inv (X+Y))|] = X+Y).
unfold interp_carry; rewrite phi_phi_inv, Z.compare_eq_iff; intros.
destruct (Z_lt_le_dec (X+Y) wB).
contradict H1; auto using Zmod_small with zarith.
rewrite <- (Z_mod_plus_full (X+Y) (-1) wB).
rewrite Zmod_small; romega.
generalize (Z.compare_eq ((X+Y) mod wB) (X+Y)); intros Heq.
destruct Z.compare; intros;
[ rewrite phi_phi_inv; auto | now apply H1 | now apply H1].
Qed.
Lemma spec_succ_c : forall x, [+|add31c x 1|] = [|x|] + 1.
Proof.
intros; apply spec_add_c.
Qed.
Lemma spec_add_carry_c : forall x y, [+|add31carryc x y|] = [|x|] + [|y|] + 1.
Proof.
intros.
unfold add31carryc, interp_carry; rewrite phi_phi_inv.
generalize (phi_bounded x)(phi_bounded y); intros.
set (X:=[|x|]) in *; set (Y:=[|y|]) in *; clearbody X Y.
assert ((X+Y+1) mod wB ?= X+Y+1 <> Eq -> [+|C1 (phi_inv (X+Y+1))|] = X+Y+1).
unfold interp_carry; rewrite phi_phi_inv, Z.compare_eq_iff; intros.
destruct (Z_lt_le_dec (X+Y+1) wB).
contradict H1; auto using Zmod_small with zarith.
rewrite <- (Z_mod_plus_full (X+Y+1) (-1) wB).
rewrite Zmod_small; romega.
generalize (Z.compare_eq ((X+Y+1) mod wB) (X+Y+1)); intros Heq.
destruct Z.compare; intros;
[ rewrite phi_phi_inv; auto | now apply H1 | now apply H1].
Qed.
Lemma spec_add : forall x y, [|x+y|] = ([|x|] + [|y|]) mod wB.
Proof.
intros; apply phi_phi_inv.
Qed.
Lemma spec_add_carry :
forall x y, [|x+y+1|] = ([|x|] + [|y|] + 1) mod wB.
Proof.
unfold add31; intros.
repeat rewrite phi_phi_inv.
apply Zplus_mod_idemp_l.
Qed.
Lemma spec_succ : forall x, [|x+1|] = ([|x|] + 1) mod wB.
Proof.
intros; rewrite <- spec_1; apply spec_add.
Qed.
(** Substraction *)
Lemma spec_sub_c : forall x y, [-|sub31c x y|] = [|x|] - [|y|].
Proof.
unfold sub31c, sub31, interp_carry; intros.
rewrite phi_phi_inv.
generalize (phi_bounded x)(phi_bounded y); intros.
set (X:=[|x|]) in *; set (Y:=[|y|]) in *; clearbody X Y.
assert ((X-Y) mod wB ?= X-Y <> Eq -> [-|C1 (phi_inv (X-Y))|] = X-Y).
unfold interp_carry; rewrite phi_phi_inv, Z.compare_eq_iff; intros.
destruct (Z_lt_le_dec (X-Y) 0).
rewrite <- (Z_mod_plus_full (X-Y) 1 wB).
rewrite Zmod_small; romega.
contradict H1; apply Zmod_small; romega.
generalize (Z.compare_eq ((X-Y) mod wB) (X-Y)); intros Heq.
destruct Z.compare; intros;
[ rewrite phi_phi_inv; auto | now apply H1 | now apply H1].
Qed.
Lemma spec_sub_carry_c : forall x y, [-|sub31carryc x y|] = [|x|] - [|y|] - 1.
Proof.
unfold sub31carryc, sub31, interp_carry; intros.
rewrite phi_phi_inv.
generalize (phi_bounded x)(phi_bounded y); intros.
set (X:=[|x|]) in *; set (Y:=[|y|]) in *; clearbody X Y.
assert ((X-Y-1) mod wB ?= X-Y-1 <> Eq -> [-|C1 (phi_inv (X-Y-1))|] = X-Y-1).
unfold interp_carry; rewrite phi_phi_inv, Z.compare_eq_iff; intros.
destruct (Z_lt_le_dec (X-Y-1) 0).
rewrite <- (Z_mod_plus_full (X-Y-1) 1 wB).
rewrite Zmod_small; romega.
contradict H1; apply Zmod_small; romega.
generalize (Z.compare_eq ((X-Y-1) mod wB) (X-Y-1)); intros Heq.
destruct Z.compare; intros;
[ rewrite phi_phi_inv; auto | now apply H1 | now apply H1].
Qed.
Lemma spec_sub : forall x y, [|x-y|] = ([|x|] - [|y|]) mod wB.
Proof.
intros; apply phi_phi_inv.
Qed.
Lemma spec_sub_carry :
forall x y, [|x-y-1|] = ([|x|] - [|y|] - 1) mod wB.
Proof.
unfold sub31; intros.
repeat rewrite phi_phi_inv.
apply Zminus_mod_idemp_l.
Qed.
Lemma spec_opp_c : forall x, [-|sub31c 0 x|] = -[|x|].
Proof.
intros; apply spec_sub_c.
Qed.
Lemma spec_opp : forall x, [|0 - x|] = (-[|x|]) mod wB.
Proof.
intros; apply phi_phi_inv.
Qed.
Lemma spec_opp_carry : forall x, [|0 - x - 1|] = wB - [|x|] - 1.
Proof.
unfold sub31; intros.
repeat rewrite phi_phi_inv.
change [|1|] with 1; change [|0|] with 0.
rewrite <- (Z_mod_plus_full (0-[|x|]) 1 wB).
rewrite Zminus_mod_idemp_l.
rewrite Zmod_small; generalize (phi_bounded x); romega.
Qed.
Lemma spec_pred_c : forall x, [-|sub31c x 1|] = [|x|] - 1.
Proof.
intros; apply spec_sub_c.
Qed.
Lemma spec_pred : forall x, [|x-1|] = ([|x|] - 1) mod wB.
Proof.
intros; apply spec_sub.
Qed.
(** Multiplication *)
Lemma phi2_phi_inv2 : forall x, [||phi_inv2 x||] = x mod (wB^2).
Proof.
assert (forall z, (z / wB) mod wB * wB + z mod wB = z mod wB ^ 2).
intros.
assert ((z/wB) mod wB = z/wB - (z/wB/wB)*wB).
rewrite (Z_div_mod_eq (z/wB) wB wB_pos) at 2; ring.
assert (z mod wB = z - (z/wB)*wB).
rewrite (Z_div_mod_eq z wB wB_pos) at 2; ring.
rewrite H.
rewrite H0 at 1.
ring_simplify.
rewrite Zdiv_Zdiv; auto with zarith.
rewrite (Z_div_mod_eq z (wB*wB)) at 2; auto with zarith.
change (wB*wB) with (wB^2); ring.
unfold phi_inv2.
destruct x; unfold zn2z_to_Z; rewrite ?phi_phi_inv;
change base with wB; auto.
Qed.
Lemma spec_mul_c : forall x y, [|| mul31c x y ||] = [|x|] * [|y|].
Proof.
unfold mul31c; intros.
rewrite phi2_phi_inv2.
apply Zmod_small.
generalize (phi_bounded x)(phi_bounded y); intros.
change (wB^2) with (wB * wB).
auto using Z.mul_lt_mono_nonneg with zarith.
Qed.
Lemma spec_mul : forall x y, [|x*y|] = ([|x|] * [|y|]) mod wB.
Proof.
intros; apply phi_phi_inv.
Qed.
Lemma spec_square_c : forall x, [|| mul31c x x ||] = [|x|] * [|x|].
Proof.
intros; apply spec_mul_c.
Qed.
(** Division *)
Lemma spec_div21 : forall a1 a2 b,
wB/2 <= [|b|] ->
[|a1|] < [|b|] ->
let (q,r) := div3121 a1 a2 b in
[|a1|] *wB+ [|a2|] = [|q|] * [|b|] + [|r|] /\
0 <= [|r|] < [|b|].
Proof.
unfold div3121; intros.
generalize (phi_bounded a1)(phi_bounded a2)(phi_bounded b); intros.
assert ([|b|]>0) by (auto with zarith).
generalize (Z_div_mod (phi2 a1 a2) [|b|] H4) (Z_div_pos (phi2 a1 a2) [|b|] H4).
unfold Z.div; destruct (Z.div_eucl (phi2 a1 a2) [|b|]); simpl.
rewrite ?phi_phi_inv.
destruct 1; intros.
unfold phi2 in *.
change base with wB; change base with wB in H5.
change (Z.pow_pos 2 31) with wB; change (Z.pow_pos 2 31) with wB in H.
rewrite H5, Z.mul_comm.
replace (z0 mod wB) with z0 by (symmetry; apply Zmod_small; omega).
replace (z mod wB) with z; auto with zarith.
symmetry; apply Zmod_small.
split.
apply H7; change base with wB; auto with zarith.
apply Z.mul_lt_mono_pos_r with [|b|]; [omega| ].
rewrite Z.mul_comm.
apply Z.le_lt_trans with ([|b|]*z+z0); [omega| ].
rewrite <- H5.
apply Z.le_lt_trans with ([|a1|]*wB+(wB-1)); [omega | ].
replace ([|a1|]*wB+(wB-1)) with (wB*([|a1|]+1)-1) by ring.
assert (wB*([|a1|]+1) <= wB*[|b|]); try omega.
apply Z.mul_le_mono_nonneg; omega.
Qed.
Lemma spec_div : forall a b, 0 < [|b|] ->
let (q,r) := div31 a b in
[|a|] = [|q|] * [|b|] + [|r|] /\
0 <= [|r|] < [|b|].
Proof.
unfold div31; intros.
assert ([|b|]>0) by (auto with zarith).
generalize (Z_div_mod [|a|] [|b|] H0) (Z_div_pos [|a|] [|b|] H0).
unfold Z.div; destruct (Z.div_eucl [|a|] [|b|]); simpl.
rewrite ?phi_phi_inv.
destruct 1; intros.
rewrite H1, Z.mul_comm.
generalize (phi_bounded a)(phi_bounded b); intros.
replace (z0 mod wB) with z0 by (symmetry; apply Zmod_small; omega).
replace (z mod wB) with z; auto with zarith.
symmetry; apply Zmod_small.
split; auto with zarith.
apply Z.le_lt_trans with [|a|]; auto with zarith.
rewrite H1.
apply Z.le_trans with ([|b|]*z); try omega.
rewrite <- (Z.mul_1_l z) at 1.
apply Z.mul_le_mono_nonneg; auto with zarith.
Qed.
Lemma spec_mod : forall a b, 0 < [|b|] ->
[|let (_,r) := (a/b)%int31 in r|] = [|a|] mod [|b|].
Proof.
unfold div31; intros.
assert ([|b|]>0) by (auto with zarith).
unfold Z.modulo.
generalize (Z_div_mod [|a|] [|b|] H0).
destruct (Z.div_eucl [|a|] [|b|]); simpl.
rewrite ?phi_phi_inv.
destruct 1; intros.
generalize (phi_bounded b); intros.
apply Zmod_small; omega.
Qed.
Lemma phi_gcd : forall i j,
[|gcd31 i j|] = Zgcdn (2*size) [|j|] [|i|].
Proof.
unfold gcd31.
induction (2*size)%nat; intros.
reflexivity.
simpl.
unfold compare31.
change [|On|] with 0.
generalize (phi_bounded j)(phi_bounded i); intros.
case_eq [|j|]; intros.
simpl; intros.
generalize (Zabs_spec [|i|]); omega.
simpl.
rewrite IHn, H1; f_equal.
rewrite spec_mod, H1; auto.
rewrite H1; compute; auto.
rewrite H1 in H; destruct H as [H _]; compute in H; elim H; auto.
Qed.
Lemma spec_gcd : forall a b, Zis_gcd [|a|] [|b|] [|gcd31 a b|].
Proof.
intros.
rewrite phi_gcd.
apply Zis_gcd_sym.
apply Zgcdn_is_gcd.
unfold Zgcd_bound.
generalize (phi_bounded b).
destruct [|b|].
unfold size; auto with zarith.
intros (_,H).
cut (Pos.size_nat p <= size)%nat; [ omega | rewrite <- Zpower2_Psize; auto].
intros (H,_); compute in H; elim H; auto.
Qed.
Lemma iter_int31_iter_nat : forall A f i a,
iter_int31 i A f a = iter_nat (Z.abs_nat [|i|]) A f a.
Proof.
intros.
unfold iter_int31.
rewrite <- recrbis_equiv; auto; unfold recrbis.
rewrite <- phibis_aux_equiv.
revert i a; induction size.
simpl; auto.
simpl; intros.
case_eq (firstr i); intros H; rewrite 2 IHn;
unfold phibis_aux; simpl; rewrite H; fold (phibis_aux n (shiftr i));
generalize (phibis_aux_pos n (shiftr i)); intros;
set (z := phibis_aux n (shiftr i)) in *; clearbody z;
rewrite <- iter_nat_plus.
f_equal.
rewrite Z.double_spec, <- Z.add_diag.
symmetry; apply Zabs2Nat.inj_add; auto with zarith.
change (iter_nat (S (Z.abs_nat z + Z.abs_nat z)) A f a =
iter_nat (Z.abs_nat (Z.succ_double z)) A f a); f_equal.
rewrite Z.succ_double_spec, <- Z.add_diag.
rewrite Zabs2Nat.inj_add; auto with zarith.
rewrite Zabs2Nat.inj_add; auto with zarith.
change (Z.abs_nat 1) with 1%nat; omega.
Qed.
Fixpoint addmuldiv31_alt n i j :=
match n with
| O => i
| S n => addmuldiv31_alt n (sneakl (firstl j) i) (shiftl j)
end.
Lemma addmuldiv31_equiv : forall p x y,
addmuldiv31 p x y = addmuldiv31_alt (Z.abs_nat [|p|]) x y.
Proof.
intros.
unfold addmuldiv31.
rewrite iter_int31_iter_nat.
set (n:=Z.abs_nat [|p|]); clearbody n; clear p.
revert x y; induction n.
simpl; auto.
intros.
simpl addmuldiv31_alt.
replace (S n) with (n+1)%nat by (rewrite plus_comm; auto).
rewrite iter_nat_plus; simpl; auto.
Qed.
Lemma spec_add_mul_div : forall x y p, [|p|] <= Zpos 31 ->
[| addmuldiv31 p x y |] =
([|x|] * (2 ^ [|p|]) + [|y|] / (2 ^ ((Zpos 31) - [|p|]))) mod wB.
Proof.
intros.
rewrite addmuldiv31_equiv.
assert ([|p|] = Z.of_nat (Z.abs_nat [|p|])).
rewrite Zabs2Nat.id_abs; symmetry; apply Z.abs_eq.
destruct (phi_bounded p); auto.
rewrite H0; rewrite H0 in H; clear H0; rewrite Zabs2Nat.id.
set (n := Z.abs_nat [|p|]) in *; clearbody n.
assert (n <= 31)%nat.
rewrite Nat2Z.inj_le; auto with zarith.
clear p H; revert x y.
induction n.
simpl; intros.
change (Z.pow_pos 2 31) with (2^31).
rewrite Z.mul_1_r.
replace ([|y|] / 2^31) with 0.
rewrite Z.add_0_r.
symmetry; apply Zmod_small; apply phi_bounded.
symmetry; apply Zdiv_small; apply phi_bounded.
simpl addmuldiv31_alt; intros.
rewrite IHn; [ | omega ].
case_eq (firstl y); intros.
rewrite phi_twice, Z.double_spec.
rewrite phi_twice_firstl; auto.
change (Z.double [|y|]) with (2*[|y|]).
rewrite Nat2Z.inj_succ, Z.pow_succ_r; auto with zarith.
rewrite Zplus_mod; rewrite Zmult_mod_idemp_l; rewrite <- Zplus_mod.
f_equal.
f_equal.
ring.
replace (31-Z.of_nat n) with (Z.succ(31-Z.succ(Z.of_nat n))) by ring.
rewrite Z.pow_succ_r, <- Zdiv_Zdiv; auto with zarith.
rewrite Z.mul_comm, Z_div_mult; auto with zarith.
rewrite phi_twice_plus_one, Z.succ_double_spec.
rewrite phi_twice; auto.
change (Z.double [|y|]) with (2*[|y|]).
rewrite Nat2Z.inj_succ, Z.pow_succ_r; auto with zarith.
rewrite Zplus_mod; rewrite Zmult_mod_idemp_l; rewrite <- Zplus_mod.
rewrite Z.mul_add_distr_r, Z.mul_1_l, <- Z.add_assoc.
f_equal.
f_equal.
ring.
assert ((2*[|y|]) mod wB = 2*[|y|] - wB).
clear - H. symmetry. apply Zmod_unique with 1; [ | ring ].
generalize (phi_lowerbound _ H) (phi_bounded y).
set (wB' := 2^Z.of_nat (pred size)).
replace wB with (2*wB'); [ omega | ].
unfold wB'. rewrite <- Z.pow_succ_r, <- Nat2Z.inj_succ by (auto with zarith).
f_equal.
rewrite H1.
replace wB with (2^(Z.of_nat n)*2^(31-Z.of_nat n)) by
(rewrite <- Zpower_exp; auto with zarith; f_equal; unfold size; ring).
unfold Z.sub; rewrite <- Z.mul_opp_l.
rewrite Z_div_plus; auto with zarith.
ring_simplify.
replace (31+-Z.of_nat n) with (Z.succ(31-Z.succ(Z.of_nat n))) by ring.
rewrite Z.pow_succ_r, <- Zdiv_Zdiv; auto with zarith.
rewrite Z.mul_comm, Z_div_mult; auto with zarith.
Qed.
Lemma spec_pos_mod : forall w p,
[|ZnZ.pos_mod p w|] = [|w|] mod (2 ^ [|p|]).
Proof.
unfold ZnZ.pos_mod, int31_ops, compare31.
change [|31|] with 31%Z.
assert (forall w p, 31<=p -> [|w|] = [|w|] mod 2^p).
intros.
generalize (phi_bounded w).
symmetry; apply Zmod_small.
split; auto with zarith.
apply Z.lt_le_trans with wB; auto with zarith.
apply Zpower_le_monotone; auto with zarith.
intros.
case_eq ([|p|] ?= 31); intros;
[ apply H; rewrite (Z.compare_eq _ _ H0); auto with zarith | |
apply H; change ([|p|]>31)%Z in H0; auto with zarith ].
change ([|p|]<31) in H0.
rewrite spec_add_mul_div by auto with zarith.
change [|0|] with 0%Z; rewrite Z.mul_0_l, Z.add_0_l.
generalize (phi_bounded p)(phi_bounded w); intros.
assert (31-[|p|]<wB).
apply Z.le_lt_trans with 31%Z; auto with zarith.
compute; auto.
assert ([|31-p|]=31-[|p|]).
unfold sub31; rewrite phi_phi_inv.
change [|31|] with 31%Z.
apply Zmod_small; auto with zarith.
rewrite spec_add_mul_div by (rewrite H4; auto with zarith).
change [|0|] with 0%Z; rewrite Zdiv_0_l, Z.add_0_r.
rewrite H4.
apply shift_unshift_mod_2; auto with zarith.
Qed.
(** Shift operations *)
Lemma spec_head00: forall x, [|x|] = 0 -> [|head031 x|] = Zpos 31.
Proof.
intros.
generalize (phi_inv_phi x).
rewrite H; simpl.
intros H'; rewrite <- H'.
simpl; auto.
Qed.
Fixpoint head031_alt n x :=
match n with
| O => 0%nat
| S n => match firstl x with
| D0 => S (head031_alt n (shiftl x))
| D1 => 0%nat
end
end.
Lemma head031_equiv :
forall x, [|head031 x|] = Z.of_nat (head031_alt size x).
Proof.
intros.
case_eq (iszero x); intros.
rewrite (iszero_eq0 _ H).
simpl; auto.
unfold head031, recl.
change On with (phi_inv (Z.of_nat (31-size))).
replace (head031_alt size x) with
(head031_alt size x + (31 - size))%nat by auto.
assert (size <= 31)%nat by auto with arith.
revert x H; induction size; intros.
simpl; auto.
unfold recl_aux; fold recl_aux.
unfold head031_alt; fold head031_alt.
rewrite H.
assert ([|phi_inv (Z.of_nat (31-S n))|] = Z.of_nat (31 - S n)).
rewrite phi_phi_inv.
apply Zmod_small.
split.
change 0 with (Z.of_nat O); apply inj_le; omega.
apply Z.le_lt_trans with (Z.of_nat 31).
apply inj_le; omega.
compute; auto.
case_eq (firstl x); intros; auto.
rewrite plus_Sn_m, plus_n_Sm.
replace (S (31 - S n)) with (31 - n)%nat by omega.
rewrite <- IHn; [ | omega | ].
f_equal; f_equal.
unfold add31.
rewrite H1.
f_equal.
change [|In|] with 1.
replace (31-n)%nat with (S (31 - S n))%nat by omega.
rewrite Nat2Z.inj_succ; ring.
clear - H H2.
rewrite (sneakr_shiftl x) in H.
rewrite H2 in H.
case_eq (iszero (shiftl x)); intros; auto.
rewrite (iszero_eq0 _ H0) in H; discriminate.
Qed.
Lemma phi_nz : forall x, 0 < [|x|] <-> x <> 0%int31.
Proof.
split; intros.
red; intro; subst x; discriminate.
assert ([|x|]<>0%Z).
contradict H.
rewrite <- (phi_inv_phi x); rewrite H; auto.
generalize (phi_bounded x); auto with zarith.
Qed.
Lemma spec_head0 : forall x, 0 < [|x|] ->
wB/ 2 <= 2 ^ ([|head031 x|]) * [|x|] < wB.
Proof.
intros.
rewrite head031_equiv.
assert (nshiftl size x = 0%int31).
apply nshiftl_size.
revert x H H0.
unfold size at 2 5.
induction size.
simpl Z.of_nat.
intros.
compute in H0; rewrite H0 in H; discriminate.
intros.
simpl head031_alt.
case_eq (firstl x); intros.
rewrite (Nat2Z.inj_succ (head031_alt n (shiftl x))), Z.pow_succ_r; auto with zarith.
rewrite <- Z.mul_assoc, Z.mul_comm, <- Z.mul_assoc, <-(Z.mul_comm 2).
rewrite <- Z.double_spec, <- (phi_twice_firstl _ H1).
apply IHn.
rewrite phi_nz; rewrite phi_nz in H; contradict H.
change twice with shiftl in H.
rewrite (sneakr_shiftl x), H1, H; auto.
rewrite <- nshiftl_S_tail; auto.
change (2^(Z.of_nat 0)) with 1; rewrite Z.mul_1_l.
generalize (phi_bounded x); unfold size; split; auto with zarith.
change (2^(Z.of_nat 31)/2) with (2^(Z.of_nat (pred size))).
apply phi_lowerbound; auto.
Qed.
Lemma spec_tail00: forall x, [|x|] = 0 -> [|tail031 x|] = Zpos 31.
Proof.
intros.
generalize (phi_inv_phi x).
rewrite H; simpl.
intros H'; rewrite <- H'.
simpl; auto.
Qed.
Fixpoint tail031_alt n x :=
match n with
| O => 0%nat
| S n => match firstr x with
| D0 => S (tail031_alt n (shiftr x))
| D1 => 0%nat
end
end.
Lemma tail031_equiv :
forall x, [|tail031 x|] = Z.of_nat (tail031_alt size x).
Proof.
intros.
case_eq (iszero x); intros.
rewrite (iszero_eq0 _ H).
simpl; auto.
unfold tail031, recr.
change On with (phi_inv (Z.of_nat (31-size))).
replace (tail031_alt size x) with
(tail031_alt size x + (31 - size))%nat by auto.
assert (size <= 31)%nat by auto with arith.
revert x H; induction size; intros.
simpl; auto.
unfold recr_aux; fold recr_aux.
unfold tail031_alt; fold tail031_alt.
rewrite H.
assert ([|phi_inv (Z.of_nat (31-S n))|] = Z.of_nat (31 - S n)).
rewrite phi_phi_inv.
apply Zmod_small.
split.
change 0 with (Z.of_nat O); apply inj_le; omega.
apply Z.le_lt_trans with (Z.of_nat 31).
apply inj_le; omega.
compute; auto.
case_eq (firstr x); intros; auto.
rewrite plus_Sn_m, plus_n_Sm.
replace (S (31 - S n)) with (31 - n)%nat by omega.
rewrite <- IHn; [ | omega | ].
f_equal; f_equal.
unfold add31.
rewrite H1.
f_equal.
change [|In|] with 1.
replace (31-n)%nat with (S (31 - S n))%nat by omega.
rewrite Nat2Z.inj_succ; ring.
clear - H H2.
rewrite (sneakl_shiftr x) in H.
rewrite H2 in H.
case_eq (iszero (shiftr x)); intros; auto.
rewrite (iszero_eq0 _ H0) in H; discriminate.
Qed.
Lemma spec_tail0 : forall x, 0 < [|x|] ->
exists y, 0 <= y /\ [|x|] = (2 * y + 1) * (2 ^ [|tail031 x|]).
Proof.
intros.
rewrite tail031_equiv.
assert (nshiftr size x = 0%int31).
apply nshiftr_size.
revert x H H0.
induction size.
simpl Z.of_nat.
intros.
compute in H0; rewrite H0 in H; discriminate.
intros.
simpl tail031_alt.
case_eq (firstr x); intros.
rewrite (Nat2Z.inj_succ (tail031_alt n (shiftr x))), Z.pow_succ_r; auto with zarith.
destruct (IHn (shiftr x)) as (y & Hy1 & Hy2).
rewrite phi_nz; rewrite phi_nz in H; contradict H.
rewrite (sneakl_shiftr x), H1, H; auto.
rewrite <- nshiftr_S_tail; auto.
exists y; split; auto.
rewrite phi_eqn1; auto.
rewrite Z.double_spec, Hy2; ring.
exists [|shiftr x|].
split.
generalize (phi_bounded (shiftr x)); auto with zarith.
rewrite phi_eqn2; auto.
rewrite Z.succ_double_spec; simpl; ring.
Qed.
(* Sqrt *)
(* Direct transcription of an old proof
of a fortran program in boyer-moore *)
Lemma quotient_by_2 a: a - 1 <= (a/2) + (a/2).
Proof.
case (Z_mod_lt a 2); auto with zarith.
intros H1; rewrite Zmod_eq_full; auto with zarith.
Qed.
Lemma sqrt_main_trick j k: 0 <= j -> 0 <= k ->
(j * k) + j <= ((j + k)/2 + 1) ^ 2.
Proof.
intros Hj; generalize Hj k; pattern j; apply natlike_ind;
auto; clear k j Hj.
intros _ k Hk; repeat rewrite Z.add_0_l.
apply Z.mul_nonneg_nonneg; generalize (Z_div_pos k 2); auto with zarith.
intros j Hj Hrec _ k Hk; pattern k; apply natlike_ind; auto; clear k Hk.
rewrite Z.mul_0_r, Z.add_0_r, Z.add_0_l.
generalize (sqr_pos (Z.succ j / 2)) (quotient_by_2 (Z.succ j));
unfold Z.succ.
rewrite Z.pow_2_r, Z.mul_add_distr_r; repeat rewrite Z.mul_add_distr_l.
auto with zarith.
intros k Hk _.
replace ((Z.succ j + Z.succ k) / 2) with ((j + k)/2 + 1).
generalize (Hrec Hj k Hk) (quotient_by_2 (j + k)).
unfold Z.succ; repeat rewrite Z.pow_2_r;
repeat rewrite Z.mul_add_distr_r; repeat rewrite Z.mul_add_distr_l.
repeat rewrite Z.mul_1_l; repeat rewrite Z.mul_1_r.
auto with zarith.
rewrite Z.add_comm, <- Z_div_plus_full_l; auto with zarith.
apply f_equal2 with (f := Z.div); auto with zarith.
Qed.
Lemma sqrt_main i j: 0 <= i -> 0 < j -> i < ((j + (i/j))/2 + 1) ^ 2.
Proof.
intros Hi Hj.
assert (Hij: 0 <= i/j) by (apply Z_div_pos; auto with zarith).
apply Z.lt_le_trans with (2 := sqrt_main_trick _ _ (Z.lt_le_incl _ _ Hj) Hij).
pattern i at 1; rewrite (Z_div_mod_eq i j); case (Z_mod_lt i j); auto with zarith.
Qed.
Lemma sqrt_init i: 1 < i -> i < (i/2 + 1) ^ 2.
Proof.
intros Hi.
assert (H1: 0 <= i - 2) by auto with zarith.
assert (H2: 1 <= (i / 2) ^ 2); auto with zarith.
replace i with (1* 2 + (i - 2)); auto with zarith.
rewrite Z.pow_2_r, Z_div_plus_full_l; auto with zarith.
generalize (sqr_pos ((i - 2)/ 2)) (Z_div_pos (i - 2) 2).
rewrite Z.mul_add_distr_r; repeat rewrite Z.mul_add_distr_l.
auto with zarith.
generalize (quotient_by_2 i).
rewrite Z.pow_2_r in H2 |- *;
repeat (rewrite Z.mul_add_distr_r ||
rewrite Z.mul_add_distr_l ||
rewrite Z.mul_1_l || rewrite Z.mul_1_r).
auto with zarith.
Qed.
Lemma sqrt_test_true i j: 0 <= i -> 0 < j -> i/j >= j -> j ^ 2 <= i.
Proof.
intros Hi Hj Hd; rewrite Z.pow_2_r.
apply Z.le_trans with (j * (i/j)); auto with zarith.
apply Z_mult_div_ge; auto with zarith.
Qed.
Lemma sqrt_test_false i j: 0 <= i -> 0 < j -> i/j < j -> (j + (i/j))/2 < j.
Proof.
intros Hi Hj H; case (Z.le_gt_cases j ((j + (i/j))/2)); auto.
intros H1; contradict H; apply Z.le_ngt.
assert (2 * j <= j + (i/j)); auto with zarith.
apply Z.le_trans with (2 * ((j + (i/j))/2)); auto with zarith.
apply Z_mult_div_ge; auto with zarith.
Qed.
Lemma sqrt31_step_def rec i j:
sqrt31_step rec i j =
match (fst (i/j) ?= j)%int31 with
Lt => rec i (fst ((j + fst(i/j))/2))%int31
| _ => j
end.
Proof.
unfold sqrt31_step; case div31; intros.
simpl; case compare31; auto.
Qed.
Lemma div31_phi i j: 0 < [|j|] -> [|fst (i/j)%int31|] = [|i|]/[|j|].
intros Hj; generalize (spec_div i j Hj).
case div31; intros q r; simpl fst.
intros (H1,H2); apply Zdiv_unique with [|r|]; auto with zarith.
rewrite H1; ring.
Qed.
Lemma sqrt31_step_correct rec i j:
0 < [|i|] -> 0 < [|j|] -> [|i|] < ([|j|] + 1) ^ 2 ->
2 * [|j|] < wB ->
(forall j1 : int31,
0 < [|j1|] < [|j|] -> [|i|] < ([|j1|] + 1) ^ 2 ->
[|rec i j1|] ^ 2 <= [|i|] < ([|rec i j1|] + 1) ^ 2) ->
[|sqrt31_step rec i j|] ^ 2 <= [|i|] < ([|sqrt31_step rec i j|] + 1) ^ 2.
Proof.
assert (Hp2: 0 < [|2|]) by exact (eq_refl Lt).
intros Hi Hj Hij H31 Hrec; rewrite sqrt31_step_def.
rewrite spec_compare, div31_phi; auto.
case Z.compare_spec; auto; intros Hc;
try (split; auto; apply sqrt_test_true; auto with zarith; fail).
apply Hrec; repeat rewrite div31_phi; auto with zarith.
replace [|(j + fst (i / j)%int31)|] with ([|j|] + [|i|] / [|j|]).
split.
apply Z.le_succ_l in Hj. change (1 <= [|j|]) in Hj.
Z.le_elim Hj.
replace ([|j|] + [|i|]/[|j|]) with
(1 * 2 + (([|j|] - 2) + [|i|] / [|j|])); try ring.
rewrite Z_div_plus_full_l; auto with zarith.
assert (0 <= [|i|]/ [|j|]) by (apply Z_div_pos; auto with zarith).
assert (0 <= ([|j|] - 2 + [|i|] / [|j|]) / [|2|]) ; auto with zarith.
rewrite <- Hj, Zdiv_1_r.
replace (1 + [|i|])%Z with (1 * 2 + ([|i|] - 1))%Z; try ring.
rewrite Z_div_plus_full_l; auto with zarith.
assert (0 <= ([|i|] - 1) /2)%Z by (apply Z_div_pos; auto with zarith).
change ([|2|]) with 2%Z; auto with zarith.
apply sqrt_test_false; auto with zarith.
rewrite spec_add, div31_phi; auto.
symmetry; apply Zmod_small.
split; auto with zarith.
replace [|j + fst (i / j)%int31|] with ([|j|] + [|i|] / [|j|]).
apply sqrt_main; auto with zarith.
rewrite spec_add, div31_phi; auto.
symmetry; apply Zmod_small.
split; auto with zarith.
Qed.
Lemma iter31_sqrt_correct n rec i j: 0 < [|i|] -> 0 < [|j|] ->
[|i|] < ([|j|] + 1) ^ 2 -> 2 * [|j|] < 2 ^ (Z.of_nat size) ->
(forall j1, 0 < [|j1|] -> 2^(Z.of_nat n) + [|j1|] <= [|j|] ->
[|i|] < ([|j1|] + 1) ^ 2 -> 2 * [|j1|] < 2 ^ (Z.of_nat size) ->
[|rec i j1|] ^ 2 <= [|i|] < ([|rec i j1|] + 1) ^ 2) ->
[|iter31_sqrt n rec i j|] ^ 2 <= [|i|] < ([|iter31_sqrt n rec i j|] + 1) ^ 2.
Proof.
revert rec i j; elim n; unfold iter31_sqrt; fold iter31_sqrt; clear n.
intros rec i j Hi Hj Hij H31 Hrec; apply sqrt31_step_correct; auto with zarith.
intros; apply Hrec; auto with zarith.
rewrite Z.pow_0_r; auto with zarith.
intros n Hrec rec i j Hi Hj Hij H31 HHrec.
apply sqrt31_step_correct; auto.
intros j1 Hj1 Hjp1; apply Hrec; auto with zarith.
intros j2 Hj2 H2j2 Hjp2 Hj31; apply Hrec; auto with zarith.
intros j3 Hj3 Hpj3.
apply HHrec; auto.
rewrite Nat2Z.inj_succ, Z.pow_succ_r.
apply Z.le_trans with (2 ^Z.of_nat n + [|j2|]); auto with zarith.
apply Nat2Z.is_nonneg.
Qed.
Lemma spec_sqrt : forall x,
[|sqrt31 x|] ^ 2 <= [|x|] < ([|sqrt31 x|] + 1) ^ 2.
Proof.
intros i; unfold sqrt31.
rewrite spec_compare. case Z.compare_spec; change [|1|] with 1;
intros Hi; auto with zarith.
repeat rewrite Z.pow_2_r; auto with zarith.
apply iter31_sqrt_correct; auto with zarith.
rewrite div31_phi; change ([|2|]) with 2; auto with zarith.
replace ([|i|]) with (1 * 2 + ([|i|] - 2))%Z; try ring.
assert (0 <= ([|i|] - 2)/2)%Z by (apply Z_div_pos; auto with zarith).
rewrite Z_div_plus_full_l; auto with zarith.
rewrite div31_phi; change ([|2|]) with 2; auto with zarith.
apply sqrt_init; auto.
rewrite div31_phi; change ([|2|]) with 2; auto with zarith.
apply Z.le_lt_trans with ([|i|]).
apply Z_mult_div_ge; auto with zarith.
case (phi_bounded i); auto.
intros j2 H1 H2; contradict H2; apply Z.lt_nge.
rewrite div31_phi; change ([|2|]) with 2; auto with zarith.
apply Z.le_lt_trans with ([|i|]); auto with zarith.
assert (0 <= [|i|]/2)%Z by (apply Z_div_pos; auto with zarith).
apply Z.le_trans with (2 * ([|i|]/2)); auto with zarith.
apply Z_mult_div_ge; auto with zarith.
case (phi_bounded i); unfold size; auto with zarith.
change [|0|] with 0; auto with zarith.
case (phi_bounded i); repeat rewrite Z.pow_2_r; auto with zarith.
Qed.
Lemma sqrt312_step_def rec ih il j:
sqrt312_step rec ih il j =
match (ih ?= j)%int31 with
Eq => j
| Gt => j
| _ =>
match (fst (div3121 ih il j) ?= j)%int31 with
Lt => let m := match j +c fst (div3121 ih il j) with
C0 m1 => fst (m1/2)%int31
| C1 m1 => (fst (m1/2) + v30)%int31
end in rec ih il m
| _ => j
end
end.
Proof.
unfold sqrt312_step; case div3121; intros.
simpl; case compare31; auto.
Qed.
Lemma sqrt312_lower_bound ih il j:
phi2 ih il < ([|j|] + 1) ^ 2 -> [|ih|] <= [|j|].
Proof.
intros H1.
case (phi_bounded j); intros Hbj _.
case (phi_bounded il); intros Hbil _.
case (phi_bounded ih); intros Hbih Hbih1.
assert (([|ih|] < [|j|] + 1)%Z); auto with zarith.
apply Z.square_lt_simpl_nonneg; auto with zarith.
repeat rewrite <-Z.pow_2_r; apply Z.le_lt_trans with (2 := H1).
apply Z.le_trans with ([|ih|] * base)%Z; unfold phi2, base;
try rewrite Z.pow_2_r; auto with zarith.
Qed.
Lemma div312_phi ih il j: (2^30 <= [|j|] -> [|ih|] < [|j|] ->
[|fst (div3121 ih il j)|] = phi2 ih il/[|j|])%Z.
Proof.
intros Hj Hj1.
generalize (spec_div21 ih il j Hj Hj1).
case div3121; intros q r (Hq, Hr).
apply Zdiv_unique with (phi r); auto with zarith.
simpl fst; apply eq_trans with (1 := Hq); ring.
Qed.
Lemma sqrt312_step_correct rec ih il j:
2 ^ 29 <= [|ih|] -> 0 < [|j|] -> phi2 ih il < ([|j|] + 1) ^ 2 ->
(forall j1, 0 < [|j1|] < [|j|] -> phi2 ih il < ([|j1|] + 1) ^ 2 ->
[|rec ih il j1|] ^ 2 <= phi2 ih il < ([|rec ih il j1|] + 1) ^ 2) ->
[|sqrt312_step rec ih il j|] ^ 2 <= phi2 ih il
< ([|sqrt312_step rec ih il j|] + 1) ^ 2.
Proof.
assert (Hp2: (0 < [|2|])%Z) by exact (eq_refl Lt).
intros Hih Hj Hij Hrec; rewrite sqrt312_step_def.
assert (H1: ([|ih|] <= [|j|])%Z) by (apply sqrt312_lower_bound with il; auto).
case (phi_bounded ih); intros Hih1 _.
case (phi_bounded il); intros Hil1 _.
case (phi_bounded j); intros _ Hj1.
assert (Hp3: (0 < phi2 ih il)).
unfold phi2; apply Z.lt_le_trans with ([|ih|] * base)%Z; auto with zarith.
apply Z.mul_pos_pos; auto with zarith.
apply Z.lt_le_trans with (2:= Hih); auto with zarith.
rewrite spec_compare. case Z.compare_spec; intros Hc1.
split; auto.
apply sqrt_test_true; auto.
unfold phi2, base; auto with zarith.
unfold phi2; rewrite Hc1.
assert (0 <= [|il|]/[|j|]) by (apply Z_div_pos; auto with zarith).
rewrite Z.mul_comm, Z_div_plus_full_l; unfold base; auto with zarith.
unfold Z.pow, Z.pow_pos in Hj1; simpl in Hj1; auto with zarith.
case (Z.le_gt_cases (2 ^ 30) [|j|]); intros Hjj.
rewrite spec_compare; case Z.compare_spec;
rewrite div312_phi; auto; intros Hc;
try (split; auto; apply sqrt_test_true; auto with zarith; fail).
apply Hrec.
assert (Hf1: 0 <= phi2 ih il/ [|j|]) by (apply Z_div_pos; auto with zarith).
apply Z.le_succ_l in Hj. change (1 <= [|j|]) in Hj.
Z.le_elim Hj.
2: contradict Hc; apply Z.le_ngt; rewrite <- Hj, Zdiv_1_r; auto with zarith.
assert (Hf3: 0 < ([|j|] + phi2 ih il / [|j|]) / 2).
replace ([|j|] + phi2 ih il/ [|j|])%Z with
(1 * 2 + (([|j|] - 2) + phi2 ih il / [|j|])); try ring.
rewrite Z_div_plus_full_l; auto with zarith.
assert (0 <= ([|j|] - 2 + phi2 ih il / [|j|]) / 2) ; auto with zarith.
assert (Hf4: ([|j|] + phi2 ih il / [|j|]) / 2 < [|j|]).
apply sqrt_test_false; auto with zarith.
generalize (spec_add_c j (fst (div3121 ih il j))).
unfold interp_carry; case add31c; intros r;
rewrite div312_phi; auto with zarith.
rewrite div31_phi; change [|2|] with 2%Z; auto with zarith.
intros HH; rewrite HH; clear HH; auto with zarith.
rewrite spec_add, div31_phi; change [|2|] with 2%Z; auto.
rewrite Z.mul_1_l; intros HH.
rewrite Z.add_comm, <- Z_div_plus_full_l; auto with zarith.
change (phi v30 * 2) with (2 ^ Z.of_nat size).
rewrite HH, Zmod_small; auto with zarith.
replace (phi
match j +c fst (div3121 ih il j) with
| C0 m1 => fst (m1 / 2)%int31
| C1 m1 => fst (m1 / 2)%int31 + v30
end) with ((([|j|] + (phi2 ih il)/([|j|]))/2)).
apply sqrt_main; auto with zarith.
generalize (spec_add_c j (fst (div3121 ih il j))).
unfold interp_carry; case add31c; intros r;
rewrite div312_phi; auto with zarith.
rewrite div31_phi; auto with zarith.
intros HH; rewrite HH; auto with zarith.
intros HH; rewrite <- HH.
change (1 * 2 ^ Z.of_nat size) with (phi (v30) * 2).
rewrite Z_div_plus_full_l; auto with zarith.
rewrite Z.add_comm.
rewrite spec_add, Zmod_small.
rewrite div31_phi; auto.
split; auto with zarith.
case (phi_bounded (fst (r/2)%int31));
case (phi_bounded v30); auto with zarith.
rewrite div31_phi; change (phi 2) with 2%Z; auto.
change (2 ^Z.of_nat size) with (base/2 + phi v30).
assert (phi r / 2 < base/2); auto with zarith.
apply Z.mul_lt_mono_pos_r with 2; auto with zarith.
change (base/2 * 2) with base.
apply Z.le_lt_trans with (phi r).
rewrite Z.mul_comm; apply Z_mult_div_ge; auto with zarith.
case (phi_bounded r); auto with zarith.
contradict Hij; apply Z.le_ngt.
assert ((1 + [|j|]) <= 2 ^ 30); auto with zarith.
apply Z.le_trans with ((2 ^ 30) * (2 ^ 30)); auto with zarith.
assert (0 <= 1 + [|j|]); auto with zarith.
apply Z.mul_le_mono_nonneg; auto with zarith.
change ((2 ^ 30) * (2 ^ 30)) with ((2 ^ 29) * base).
apply Z.le_trans with ([|ih|] * base); auto with zarith.
unfold phi2, base; auto with zarith.
split; auto.
apply sqrt_test_true; auto.
unfold phi2, base; auto with zarith.
apply Z.le_ge; apply Z.le_trans with (([|j|] * base)/[|j|]).
rewrite Z.mul_comm, Z_div_mult; auto with zarith.
apply Z.ge_le; apply Z_div_ge; auto with zarith.
Qed.
Lemma iter312_sqrt_correct n rec ih il j:
2^29 <= [|ih|] -> 0 < [|j|] -> phi2 ih il < ([|j|] + 1) ^ 2 ->
(forall j1, 0 < [|j1|] -> 2^(Z.of_nat n) + [|j1|] <= [|j|] ->
phi2 ih il < ([|j1|] + 1) ^ 2 ->
[|rec ih il j1|] ^ 2 <= phi2 ih il < ([|rec ih il j1|] + 1) ^ 2) ->
[|iter312_sqrt n rec ih il j|] ^ 2 <= phi2 ih il
< ([|iter312_sqrt n rec ih il j|] + 1) ^ 2.
Proof.
revert rec ih il j; elim n; unfold iter312_sqrt; fold iter312_sqrt; clear n.
intros rec ih il j Hi Hj Hij Hrec; apply sqrt312_step_correct; auto with zarith.
intros; apply Hrec; auto with zarith.
rewrite Z.pow_0_r; auto with zarith.
intros n Hrec rec ih il j Hi Hj Hij HHrec.
apply sqrt312_step_correct; auto.
intros j1 Hj1 Hjp1; apply Hrec; auto with zarith.
intros j2 Hj2 H2j2 Hjp2; apply Hrec; auto with zarith.
intros j3 Hj3 Hpj3.
apply HHrec; auto.
rewrite Nat2Z.inj_succ, Z.pow_succ_r.
apply Z.le_trans with (2 ^Z.of_nat n + [|j2|])%Z; auto with zarith.
apply Nat2Z.is_nonneg.
Qed.
Lemma spec_sqrt2 : forall x y,
wB/ 4 <= [|x|] ->
let (s,r) := sqrt312 x y in
[||WW x y||] = [|s|] ^ 2 + [+|r|] /\
[+|r|] <= 2 * [|s|].
Proof.
intros ih il Hih; unfold sqrt312.
change [||WW ih il||] with (phi2 ih il).
assert (Hbin: forall s, s * s + 2* s + 1 = (s + 1) ^ 2) by
(intros s; ring).
assert (Hb: 0 <= base) by (red; intros HH; discriminate).
assert (Hi2: phi2 ih il < (phi Tn + 1) ^ 2).
{ change ((phi Tn + 1) ^ 2) with (2^62).
apply Z.le_lt_trans with ((2^31 -1) * base + (2^31 - 1)); auto with zarith.
2: simpl; unfold Z.pow_pos; simpl; auto with zarith.
case (phi_bounded ih); case (phi_bounded il); intros H1 H2 H3 H4.
unfold base, Z.pow, Z.pow_pos in H2,H4; simpl in H2,H4.
unfold phi2,Z.pow, Z.pow_pos. simpl Pos.iter; auto with zarith. }
case (iter312_sqrt_correct 31 (fun _ _ j => j) ih il Tn); auto with zarith.
change [|Tn|] with 2147483647; auto with zarith.
intros j1 _ HH; contradict HH.
apply Z.lt_nge.
change [|Tn|] with 2147483647; auto with zarith.
change (2 ^ Z.of_nat 31) with 2147483648; auto with zarith.
case (phi_bounded j1); auto with zarith.
set (s := iter312_sqrt 31 (fun _ _ j : int31 => j) ih il Tn).
intros Hs1 Hs2.
generalize (spec_mul_c s s); case mul31c.
simpl zn2z_to_Z; intros HH.
assert ([|s|] = 0).
{ symmetry in HH. rewrite Z.mul_eq_0 in HH. destruct HH; auto. }
contradict Hs2; apply Z.le_ngt; rewrite H.
change ((0 + 1) ^ 2) with 1.
apply Z.le_trans with (2 ^ Z.of_nat size / 4 * base).
simpl; auto with zarith.
apply Z.le_trans with ([|ih|] * base); auto with zarith.
unfold phi2; case (phi_bounded il); auto with zarith.
intros ih1 il1.
change [||WW ih1 il1||] with (phi2 ih1 il1).
intros Hihl1.
generalize (spec_sub_c il il1).
case sub31c; intros il2 Hil2.
simpl interp_carry in Hil2.
rewrite spec_compare; case Z.compare_spec.
unfold interp_carry.
intros H1; split.
rewrite Z.pow_2_r, <- Hihl1.
unfold phi2; ring[Hil2 H1].
replace [|il2|] with (phi2 ih il - phi2 ih1 il1).
rewrite Hihl1.
rewrite <-Hbin in Hs2; auto with zarith.
unfold phi2; rewrite H1, Hil2; ring.
unfold interp_carry.
intros H1; contradict Hs1.
apply Z.lt_nge; rewrite Z.pow_2_r, <-Hihl1.
unfold phi2.
case (phi_bounded il); intros _ H2.
apply Z.lt_le_trans with (([|ih|] + 1) * base + 0).
rewrite Z.mul_add_distr_r, Z.add_0_r; auto with zarith.
case (phi_bounded il1); intros H3 _.
apply Z.add_le_mono; auto with zarith.
unfold interp_carry; change (1 * 2 ^ Z.of_nat size) with base.
rewrite Z.pow_2_r, <- Hihl1, Hil2.
intros H1.
rewrite <- Z.le_succ_l, <- Z.add_1_r in H1.
Z.le_elim H1.
contradict Hs2; apply Z.le_ngt.
replace (([|s|] + 1) ^ 2) with (phi2 ih1 il1 + 2 * [|s|] + 1).
unfold phi2.
case (phi_bounded il); intros Hpil _.
assert (Hl1l: [|il1|] <= [|il|]).
{ case (phi_bounded il2); rewrite Hil2; auto with zarith. }
assert ([|ih1|] * base + 2 * [|s|] + 1 <= [|ih|] * base); auto with zarith.
case (phi_bounded s); change (2 ^ Z.of_nat size) with base; intros _ Hps.
case (phi_bounded ih1); intros Hpih1 _; auto with zarith.
apply Z.le_trans with (([|ih1|] + 2) * base); auto with zarith.
rewrite Z.mul_add_distr_r.
assert (2 * [|s|] + 1 <= 2 * base); auto with zarith.
rewrite Hihl1, Hbin; auto.
split.
unfold phi2; rewrite <- H1; ring.
replace (base + ([|il|] - [|il1|])) with (phi2 ih il - ([|s|] * [|s|])).
rewrite <-Hbin in Hs2; auto with zarith.
rewrite <- Hihl1; unfold phi2; rewrite <- H1; ring.
unfold interp_carry in Hil2 |- *.
unfold interp_carry; change (1 * 2 ^ Z.of_nat size) with base.
assert (Hsih: [|ih - 1|] = [|ih|] - 1).
{ rewrite spec_sub, Zmod_small; auto; change [|1|] with 1.
case (phi_bounded ih); intros H1 H2.
generalize Hih; change (2 ^ Z.of_nat size / 4) with 536870912.
split; auto with zarith. }
rewrite spec_compare; case Z.compare_spec.
rewrite Hsih.
intros H1; split.
rewrite Z.pow_2_r, <- Hihl1.
unfold phi2; rewrite <-H1.
transitivity ([|ih|] * base + [|il1|] + ([|il|] - [|il1|])).
ring.
rewrite <-Hil2.
change (2 ^ Z.of_nat size) with base; ring.
replace [|il2|] with (phi2 ih il - phi2 ih1 il1).
rewrite Hihl1.
rewrite <-Hbin in Hs2; auto with zarith.
unfold phi2.
rewrite <-H1.
ring_simplify.
transitivity (base + ([|il|] - [|il1|])).
ring.
rewrite <-Hil2.
change (2 ^ Z.of_nat size) with base; ring.
rewrite Hsih; intros H1.
assert (He: [|ih|] = [|ih1|]).
{ apply Z.le_antisymm; auto with zarith.
case (Z.le_gt_cases [|ih1|] [|ih|]); auto; intros H2.
contradict Hs1; apply Z.lt_nge; rewrite Z.pow_2_r, <-Hihl1.
unfold phi2.
case (phi_bounded il); change (2 ^ Z.of_nat size) with base;
intros _ Hpil1.
apply Z.lt_le_trans with (([|ih|] + 1) * base).
rewrite Z.mul_add_distr_r, Z.mul_1_l; auto with zarith.
case (phi_bounded il1); intros Hpil2 _.
apply Z.le_trans with (([|ih1|]) * base); auto with zarith. }
rewrite Z.pow_2_r, <-Hihl1; unfold phi2; rewrite <-He.
contradict Hs1; apply Z.lt_nge; rewrite Z.pow_2_r, <-Hihl1.
unfold phi2; rewrite He.
assert (phi il - phi il1 < 0); auto with zarith.
rewrite <-Hil2.
case (phi_bounded il2); auto with zarith.
intros H1.
rewrite Z.pow_2_r, <-Hihl1.
assert (H2 : [|ih1|]+2 <= [|ih|]); auto with zarith.
Z.le_elim H2.
contradict Hs2; apply Z.le_ngt.
replace (([|s|] + 1) ^ 2) with (phi2 ih1 il1 + 2 * [|s|] + 1).
unfold phi2.
assert ([|ih1|] * base + 2 * phi s + 1 <= [|ih|] * base + ([|il|] - [|il1|]));
auto with zarith.
rewrite <-Hil2.
change (-1 * 2 ^ Z.of_nat size) with (-base).
case (phi_bounded il2); intros Hpil2 _.
apply Z.le_trans with ([|ih|] * base + - base); auto with zarith.
case (phi_bounded s); change (2 ^ Z.of_nat size) with base; intros _ Hps.
assert (2 * [|s|] + 1 <= 2 * base); auto with zarith.
apply Z.le_trans with ([|ih1|] * base + 2 * base); auto with zarith.
assert (Hi: ([|ih1|] + 3) * base <= [|ih|] * base); auto with zarith.
rewrite Z.mul_add_distr_r in Hi; auto with zarith.
rewrite Hihl1, Hbin; auto.
unfold phi2; rewrite <-H2.
split.
replace [|il|] with (([|il|] - [|il1|]) + [|il1|]); try ring.
rewrite <-Hil2.
change (-1 * 2 ^ Z.of_nat size) with (-base); ring.
replace (base + [|il2|]) with (phi2 ih il - phi2 ih1 il1).
rewrite Hihl1.
rewrite <-Hbin in Hs2; auto with zarith.
unfold phi2; rewrite <-H2.
replace [|il|] with (([|il|] - [|il1|]) + [|il1|]); try ring.
rewrite <-Hil2.
change (-1 * 2 ^ Z.of_nat size) with (-base); ring.
Qed.
(** [iszero] *)
Lemma spec_eq0 : forall x, ZnZ.eq0 x = true -> [|x|] = 0.
Proof.
clear; unfold ZnZ.eq0; simpl.
unfold compare31; simpl; intros.
change [|0|] with 0 in H.
apply Z.compare_eq.
now destruct ([|x|] ?= 0).
Qed.
(* Even *)
Lemma spec_is_even : forall x,
if ZnZ.is_even x then [|x|] mod 2 = 0 else [|x|] mod 2 = 1.
Proof.
unfold ZnZ.is_even; simpl; intros.
generalize (spec_div x 2).
destruct (x/2)%int31 as (q,r); intros.
unfold compare31.
change [|2|] with 2 in H.
change [|0|] with 0.
destruct H; auto with zarith.
replace ([|x|] mod 2) with [|r|].
destruct H; auto with zarith.
case Z.compare_spec; auto with zarith.
apply Zmod_unique with [|q|]; auto with zarith.
Qed.
Global Instance int31_specs : ZnZ.Specs int31_ops := {
spec_to_Z := phi_bounded;
spec_of_pos := positive_to_int31_spec;
spec_zdigits := spec_zdigits;
spec_more_than_1_digit := spec_more_than_1_digit;
spec_0 := spec_0;
spec_1 := spec_1;
spec_m1 := spec_m1;
spec_compare := spec_compare;
spec_eq0 := spec_eq0;
spec_opp_c := spec_opp_c;
spec_opp := spec_opp;
spec_opp_carry := spec_opp_carry;
spec_succ_c := spec_succ_c;
spec_add_c := spec_add_c;
spec_add_carry_c := spec_add_carry_c;
spec_succ := spec_succ;
spec_add := spec_add;
spec_add_carry := spec_add_carry;
spec_pred_c := spec_pred_c;
spec_sub_c := spec_sub_c;
spec_sub_carry_c := spec_sub_carry_c;
spec_pred := spec_pred;
spec_sub := spec_sub;
spec_sub_carry := spec_sub_carry;
spec_mul_c := spec_mul_c;
spec_mul := spec_mul;
spec_square_c := spec_square_c;
spec_div21 := spec_div21;
spec_div_gt := fun a b _ => spec_div a b;
spec_div := spec_div;
spec_modulo_gt := fun a b _ => spec_mod a b;
spec_modulo := spec_mod;
spec_gcd_gt := fun a b _ => spec_gcd a b;
spec_gcd := spec_gcd;
spec_head00 := spec_head00;
spec_head0 := spec_head0;
spec_tail00 := spec_tail00;
spec_tail0 := spec_tail0;
spec_add_mul_div := spec_add_mul_div;
spec_pos_mod := spec_pos_mod;
spec_is_even := spec_is_even;
spec_sqrt2 := spec_sqrt2;
spec_sqrt := spec_sqrt }.
End Int31_Specs.
Module Int31Cyclic <: CyclicType.
Definition t := int31.
Definition ops := int31_ops.
Definition specs := int31_specs.
End Int31Cyclic.
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
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// otherwise provided in a valid license issued to you by
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
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// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
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// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
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// Applications, subject only to applicable laws and
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_7x_v1_3_qpll_wrapper.v
// Version : 1.3
//------------------------------------------------------------------------------
// Filename : qpll_wrapper.v
// Description : QPLL Wrapper Module for 7 Series Transceiver
// Version : 11.4
//------------------------------------------------------------------------------
`timescale 1ns / 1ps
//---------- QPLL Wrapper ----------------------------------------------------
module pcie_7x_v1_3_qpll_wrapper #
(
parameter PCIE_SIM_MODE = "FALSE", // PCIe sim mode
parameter PCIE_GT_DEVICE = "GTX", // PCIe GT device
parameter PCIE_USE_MODE = "1.1", // PCIe use mode
parameter PCIE_PLL_SEL = "CPLL", // PCIe PLL select for Gen1/Gen2 only
parameter PCIE_REFCLK_FREQ = 0 // PCIe reference clock frequency
)
(
//---------- QPLL Clock Ports --------------------------
input QPLL_GTGREFCLK,
input QPLL_QPLLLOCKDETCLK,
output QPLL_QPLLOUTCLK,
output QPLL_QPLLOUTREFCLK,
output QPLL_QPLLLOCK,
//---------- QPLL Reset Ports --------------------------
input QPLL_QPLLPD,
input QPLL_QPLLRESET,
//---------- QPLL DRP Ports ----------------------------
input QPLL_DRPCLK,
input [ 7:0] QPLL_DRPADDR,
input QPLL_DRPEN,
input [15:0] QPLL_DRPDI,
input QPLL_DRPWE,
output [15:0] QPLL_DRPDO,
output QPLL_DRPRDY
);
//---------- Select QPLL Feedback Divider --------------
// N = 100 for 100 MHz ref clk and 10Gb/s line rate
// N = 80 for 125 MHz ref clk and 10Gb/s line rate
// N = 40 for 250 MHz ref clk and 10Gb/s line rate
//------------------------------------------------------
// N = 80 for 100 MHz ref clk and 8Gb/s line rate
// N = 64 for 125 MHz ref clk and 8Gb/s line rate
// N = 32 for 250 MHz ref clk and 8Gb/s line rate
//------------------------------------------------------
localparam QPLL_FBDIV = (PCIE_REFCLK_FREQ == 2) && (PCIE_PLL_SEL == "QPLL") ? 10'b0010000000 :
(PCIE_REFCLK_FREQ == 1) && (PCIE_PLL_SEL == "QPLL") ? 10'b0100100000 :
(PCIE_REFCLK_FREQ == 0) && (PCIE_PLL_SEL == "QPLL") ? 10'b0101110000 :
(PCIE_REFCLK_FREQ == 2) && (PCIE_PLL_SEL == "CPLL") ? 10'b0001100000 :
(PCIE_REFCLK_FREQ == 1) && (PCIE_PLL_SEL == "CPLL") ? 10'b0011100000 : 10'b0100100000;
//---------- Select BIAS_CFG ---------------------------
localparam BIAS_CFG = ((PCIE_USE_MODE == "1.0") && (PCIE_PLL_SEL == "CPLL")) ? 64'h0000042000001000 : 64'h0000040000001000;
//---------- Select GTX or GTH -------------------------------------------------
// Notes : Attributes that are commented out uses the GT default settings
//------------------------------------------------------------------------------
generate if (PCIE_GT_DEVICE == "GTH")
//---------- GTH Common ----------------------------------------------------
begin : gth_common
//---------- GTX Common Module ---------------------------------------------
GTHE2_COMMON #
(
//---------- Simulation Attributes -------------------------------------
.SIM_QPLLREFCLK_SEL (3'b001), //
.SIM_RESET_SPEEDUP (PCIE_SIM_MODE), //
.SIM_VERSION (PCIE_USE_MODE), //
//---------- Clock Attributes ------------------------------------------
.QPLL_CFG (27'h06801C1), // Optimized for silicon
//.QPLL_CLKOUT_CFG ( 4'b0000), //
.QPLL_COARSE_FREQ_OVRD ( 6'b010000), //
.QPLL_COARSE_FREQ_OVRD_EN ( 1'b0), //
.QPLL_CP (10'h1FF), // Optimized for compliance
.QPLL_CP_MONITOR_EN ( 1'b0), //
.QPLL_DMONITOR_SEL ( 1'b0), //
.QPLL_FBDIV (QPLL_FBDIV), //
.QPLL_FBDIV_MONITOR_EN ( 1'b0), //
.QPLL_FBDIV_RATIO ( 1'b1), //
//.QPLL_INIT_CFG (24'h000006), //
.QPLL_LOCK_CFG (16'h01D0), // Optimized for silicon
.QPLL_LPF ( 4'hD), // Optimized for silicon
.QPLL_REFCLK_DIV ( 1), //
//----------------------------------------------------------------------
.BIAS_CFG (BIAS_CFG) // Optimized for silicon
//.COMMON_CFG (32'h00000000), //
//---------- GTH -------------------------------------------------------
//.RSVD_ATTR0 (16'h0000), //
//.RSVD_ATTR1 (16'h0000) //
)
gthe2_common_i
(
//---------- Clock -----------------------------------------------------
.GTGREFCLK ( 1'd0), //
.GTREFCLK0 (QPLL_GTGREFCLK), //
.GTREFCLK1 ( 1'd0), //
.GTNORTHREFCLK0 ( 1'd0), //
.GTNORTHREFCLK1 ( 1'd0), //
.GTSOUTHREFCLK0 ( 1'd0), //
.GTSOUTHREFCLK1 ( 1'd0), //
.QPLLLOCKDETCLK (QPLL_QPLLLOCKDETCLK), //
.QPLLLOCKEN ( 1'd1), //
.QPLLREFCLKSEL ( 3'd1), //
.QPLLRSVD1 (16'd0), //
.QPLLRSVD2 ( 5'b11111), //
.QPLLOUTCLK (QPLL_QPLLOUTCLK), //
.QPLLOUTREFCLK (QPLL_QPLLOUTREFCLK), //
.QPLLLOCK (QPLL_QPLLLOCK), //
.QPLLFBCLKLOST (), //
.QPLLREFCLKLOST (), //
.QPLLDMONITOR (), //
//---------- Reset -----------------------------------------------------
.QPLLPD (QPLL_QPLLPD), //
.QPLLRESET (QPLL_QPLLRESET), //
.QPLLOUTRESET (1'd0), //
//---------- DRP -------------------------------------------------------
.DRPCLK (QPLL_DRPCLK), //
.DRPADDR (QPLL_DRPADDR), //
.DRPEN (QPLL_DRPEN), //
.DRPDI (QPLL_DRPDI), //
.DRPWE (QPLL_DRPWE), //
.DRPDO (QPLL_DRPDO), //
.DRPRDY (QPLL_DRPRDY), //
//---------- Band Gap --------------------------------------------------
.BGBYPASSB ( 1'd1), //
.BGMONITORENB ( 1'd1), //
.BGPDB ( 1'd1), //
.BGRCALOVRD ( 5'd0), //
//----------------------------------------------------------------------
.PMARSVD ( 8'd0), //
.RCALENB ( 1'b0), //
.REFCLKOUTMONITOR (), //
//---------- GTH -------------------------------------------------------
.BGRCALOVRDENB ( 1'd0), //
.PMARSVDOUT () //
);
end
else
begin : gtx_common
//---------- GTX Common Module ---------------------------------------------
GTXE2_COMMON #
(
//---------- Simulation Attributes -------------------------------------
.SIM_QPLLREFCLK_SEL (3'b001), //
.SIM_RESET_SPEEDUP (PCIE_SIM_MODE), //
.SIM_VERSION (PCIE_USE_MODE), //
//---------- Clock Attributes ------------------------------------------
.QPLL_CFG (27'h06801C1), // Optimized for silicon
//.QPLL_CLKOUT_CFG ( 4'b0000), //
.QPLL_COARSE_FREQ_OVRD ( 6'b010000), //
.QPLL_COARSE_FREQ_OVRD_EN ( 1'b0), //
.QPLL_CP (10'h1FF), // Optimized for compliance
.QPLL_CP_MONITOR_EN ( 1'b0), //
.QPLL_DMONITOR_SEL ( 1'b0), //
.QPLL_FBDIV (QPLL_FBDIV), //
.QPLL_FBDIV_MONITOR_EN ( 1'b0), //
.QPLL_FBDIV_RATIO ( 1'b1), //
//.QPLL_INIT_CFG (24'h000006), //
.QPLL_LOCK_CFG (16'h01D0), // Optimized for silicon
.QPLL_LPF ( 4'hD), // Optimized for silicon
.QPLL_REFCLK_DIV ( 1), //
//----------------------------------------------------------------------
.BIAS_CFG (BIAS_CFG) // Optimized for silicon
//.COMMON_CFG (32'h00000000) //
)
gtxe2_common_i
(
//---------- Clock -----------------------------------------------------
.GTGREFCLK ( 1'd0), //
.GTREFCLK0 (QPLL_GTGREFCLK), //
.GTREFCLK1 ( 1'd0), //
.GTNORTHREFCLK0 ( 1'd0), //
.GTNORTHREFCLK1 ( 1'd0), //
.GTSOUTHREFCLK0 ( 1'd0), //
.GTSOUTHREFCLK1 ( 1'd0), //
.QPLLLOCKDETCLK (QPLL_QPLLLOCKDETCLK), //
.QPLLLOCKEN ( 1'd1), //
.QPLLREFCLKSEL ( 3'd1), //
.QPLLRSVD1 (16'd0), //
.QPLLRSVD2 ( 5'b11111), //
.QPLLOUTCLK (QPLL_QPLLOUTCLK), //
.QPLLOUTREFCLK (QPLL_QPLLOUTREFCLK), //
.QPLLLOCK (QPLL_QPLLLOCK), //
.QPLLFBCLKLOST (), //
.QPLLREFCLKLOST (), //
.QPLLDMONITOR (), //
//---------- Reset -----------------------------------------------------
.QPLLPD (QPLL_QPLLPD), //
.QPLLRESET (QPLL_QPLLRESET), //
.QPLLOUTRESET ( 1'd0), //
//---------- DRP -------------------------------------------------------
.DRPCLK (QPLL_DRPCLK), //
.DRPADDR (QPLL_DRPADDR), //
.DRPEN (QPLL_DRPEN), //
.DRPDI (QPLL_DRPDI), //
.DRPWE (QPLL_DRPWE), //
.DRPDO (QPLL_DRPDO), //
.DRPRDY (QPLL_DRPRDY), //
//---------- Band Gap --------------------------------------------------
.BGBYPASSB ( 1'd1), //
.BGMONITORENB ( 1'd1), //
.BGPDB ( 1'd1), //
.BGRCALOVRD ( 5'd0), //
//----------------------------------------------------------------------
.PMARSVD ( 8'd0), //
.RCALENB ( 1'b0), //
.REFCLKOUTMONITOR () //
);
end
endgenerate
endmodule
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosii_jtag_uart_0_sim_scfifo_w (
// inputs:
clk,
fifo_wdata,
fifo_wr,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
)
;
output fifo_FF;
output [ 7: 0] r_dat;
output wfifo_empty;
output [ 5: 0] wfifo_used;
input clk;
input [ 7: 0] fifo_wdata;
input fifo_wr;
wire fifo_FF;
wire [ 7: 0] r_dat;
wire wfifo_empty;
wire [ 5: 0] wfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
always @(posedge clk)
begin
if (fifo_wr)
$write("%c", fifo_wdata);
end
assign wfifo_used = {6{1'b0}};
assign r_dat = {8{1'b0}};
assign fifo_FF = 1'b0;
assign wfifo_empty = 1'b1;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosii_jtag_uart_0_scfifo_w (
// inputs:
clk,
fifo_clear,
fifo_wdata,
fifo_wr,
rd_wfifo,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
)
;
output fifo_FF;
output [ 7: 0] r_dat;
output wfifo_empty;
output [ 5: 0] wfifo_used;
input clk;
input fifo_clear;
input [ 7: 0] fifo_wdata;
input fifo_wr;
input rd_wfifo;
wire fifo_FF;
wire [ 7: 0] r_dat;
wire wfifo_empty;
wire [ 5: 0] wfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
niosii_jtag_uart_0_sim_scfifo_w the_niosii_jtag_uart_0_sim_scfifo_w
(
.clk (clk),
.fifo_FF (fifo_FF),
.fifo_wdata (fifo_wdata),
.fifo_wr (fifo_wr),
.r_dat (r_dat),
.wfifo_empty (wfifo_empty),
.wfifo_used (wfifo_used)
);
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// scfifo wfifo
// (
// .aclr (fifo_clear),
// .clock (clk),
// .data (fifo_wdata),
// .empty (wfifo_empty),
// .full (fifo_FF),
// .q (r_dat),
// .rdreq (rd_wfifo),
// .usedw (wfifo_used),
// .wrreq (fifo_wr)
// );
//
// defparam wfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
// wfifo.lpm_numwords = 64,
// wfifo.lpm_showahead = "OFF",
// wfifo.lpm_type = "scfifo",
// wfifo.lpm_width = 8,
// wfifo.lpm_widthu = 6,
// wfifo.overflow_checking = "OFF",
// wfifo.underflow_checking = "OFF",
// wfifo.use_eab = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosii_jtag_uart_0_sim_scfifo_r (
// inputs:
clk,
fifo_rd,
rst_n,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
)
;
output fifo_EF;
output [ 7: 0] fifo_rdata;
output rfifo_full;
output [ 5: 0] rfifo_used;
input clk;
input fifo_rd;
input rst_n;
reg [ 31: 0] bytes_left;
wire fifo_EF;
reg fifo_rd_d;
wire [ 7: 0] fifo_rdata;
wire new_rom;
wire [ 31: 0] num_bytes;
wire [ 6: 0] rfifo_entries;
wire rfifo_full;
wire [ 5: 0] rfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
// Generate rfifo_entries for simulation
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
begin
bytes_left <= 32'h0;
fifo_rd_d <= 1'b0;
end
else
begin
fifo_rd_d <= fifo_rd;
// decrement on read
if (fifo_rd_d)
bytes_left <= bytes_left - 1'b1;
// catch new contents
if (new_rom)
bytes_left <= num_bytes;
end
end
assign fifo_EF = bytes_left == 32'b0;
assign rfifo_full = bytes_left > 7'h40;
assign rfifo_entries = (rfifo_full) ? 7'h40 : bytes_left;
assign rfifo_used = rfifo_entries[5 : 0];
assign new_rom = 1'b0;
assign num_bytes = 32'b0;
assign fifo_rdata = 8'b0;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosii_jtag_uart_0_scfifo_r (
// inputs:
clk,
fifo_clear,
fifo_rd,
rst_n,
t_dat,
wr_rfifo,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
)
;
output fifo_EF;
output [ 7: 0] fifo_rdata;
output rfifo_full;
output [ 5: 0] rfifo_used;
input clk;
input fifo_clear;
input fifo_rd;
input rst_n;
input [ 7: 0] t_dat;
input wr_rfifo;
wire fifo_EF;
wire [ 7: 0] fifo_rdata;
wire rfifo_full;
wire [ 5: 0] rfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
niosii_jtag_uart_0_sim_scfifo_r the_niosii_jtag_uart_0_sim_scfifo_r
(
.clk (clk),
.fifo_EF (fifo_EF),
.fifo_rd (fifo_rd),
.fifo_rdata (fifo_rdata),
.rfifo_full (rfifo_full),
.rfifo_used (rfifo_used),
.rst_n (rst_n)
);
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// scfifo rfifo
// (
// .aclr (fifo_clear),
// .clock (clk),
// .data (t_dat),
// .empty (fifo_EF),
// .full (rfifo_full),
// .q (fifo_rdata),
// .rdreq (fifo_rd),
// .usedw (rfifo_used),
// .wrreq (wr_rfifo)
// );
//
// defparam rfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
// rfifo.lpm_numwords = 64,
// rfifo.lpm_showahead = "OFF",
// rfifo.lpm_type = "scfifo",
// rfifo.lpm_width = 8,
// rfifo.lpm_widthu = 6,
// rfifo.overflow_checking = "OFF",
// rfifo.underflow_checking = "OFF",
// rfifo.use_eab = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosii_jtag_uart_0 (
// inputs:
av_address,
av_chipselect,
av_read_n,
av_write_n,
av_writedata,
clk,
rst_n,
// outputs:
av_irq,
av_readdata,
av_waitrequest,
dataavailable,
readyfordata
)
/* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R101,C106,D101,D103\"" */ ;
output av_irq;
output [ 31: 0] av_readdata;
output av_waitrequest;
output dataavailable;
output readyfordata;
input av_address;
input av_chipselect;
input av_read_n;
input av_write_n;
input [ 31: 0] av_writedata;
input clk;
input rst_n;
reg ac;
wire activity;
wire av_irq;
wire [ 31: 0] av_readdata;
reg av_waitrequest;
reg dataavailable;
reg fifo_AE;
reg fifo_AF;
wire fifo_EF;
wire fifo_FF;
wire fifo_clear;
wire fifo_rd;
wire [ 7: 0] fifo_rdata;
wire [ 7: 0] fifo_wdata;
reg fifo_wr;
reg ien_AE;
reg ien_AF;
wire ipen_AE;
wire ipen_AF;
reg pause_irq;
wire [ 7: 0] r_dat;
wire r_ena;
reg r_val;
wire rd_wfifo;
reg read_0;
reg readyfordata;
wire rfifo_full;
wire [ 5: 0] rfifo_used;
reg rvalid;
reg sim_r_ena;
reg sim_t_dat;
reg sim_t_ena;
reg sim_t_pause;
wire [ 7: 0] t_dat;
reg t_dav;
wire t_ena;
wire t_pause;
wire wfifo_empty;
wire [ 5: 0] wfifo_used;
reg woverflow;
wire wr_rfifo;
//avalon_jtag_slave, which is an e_avalon_slave
assign rd_wfifo = r_ena & ~wfifo_empty;
assign wr_rfifo = t_ena & ~rfifo_full;
assign fifo_clear = ~rst_n;
niosii_jtag_uart_0_scfifo_w the_niosii_jtag_uart_0_scfifo_w
(
.clk (clk),
.fifo_FF (fifo_FF),
.fifo_clear (fifo_clear),
.fifo_wdata (fifo_wdata),
.fifo_wr (fifo_wr),
.r_dat (r_dat),
.rd_wfifo (rd_wfifo),
.wfifo_empty (wfifo_empty),
.wfifo_used (wfifo_used)
);
niosii_jtag_uart_0_scfifo_r the_niosii_jtag_uart_0_scfifo_r
(
.clk (clk),
.fifo_EF (fifo_EF),
.fifo_clear (fifo_clear),
.fifo_rd (fifo_rd),
.fifo_rdata (fifo_rdata),
.rfifo_full (rfifo_full),
.rfifo_used (rfifo_used),
.rst_n (rst_n),
.t_dat (t_dat),
.wr_rfifo (wr_rfifo)
);
assign ipen_AE = ien_AE & fifo_AE;
assign ipen_AF = ien_AF & (pause_irq | fifo_AF);
assign av_irq = ipen_AE | ipen_AF;
assign activity = t_pause | t_ena;
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
pause_irq <= 1'b0;
else // only if fifo is not empty...
if (t_pause & ~fifo_EF)
pause_irq <= 1'b1;
else if (read_0)
pause_irq <= 1'b0;
end
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
begin
r_val <= 1'b0;
t_dav <= 1'b1;
end
else
begin
r_val <= r_ena & ~wfifo_empty;
t_dav <= ~rfifo_full;
end
end
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
begin
fifo_AE <= 1'b0;
fifo_AF <= 1'b0;
fifo_wr <= 1'b0;
rvalid <= 1'b0;
read_0 <= 1'b0;
ien_AE <= 1'b0;
ien_AF <= 1'b0;
ac <= 1'b0;
woverflow <= 1'b0;
av_waitrequest <= 1'b1;
end
else
begin
fifo_AE <= {fifo_FF,wfifo_used} <= 8;
fifo_AF <= (7'h40 - {rfifo_full,rfifo_used}) <= 8;
fifo_wr <= 1'b0;
read_0 <= 1'b0;
av_waitrequest <= ~(av_chipselect & (~av_write_n | ~av_read_n) & av_waitrequest);
if (activity)
ac <= 1'b1;
// write
if (av_chipselect & ~av_write_n & av_waitrequest)
// addr 1 is control; addr 0 is data
if (av_address)
begin
ien_AF <= av_writedata[0];
ien_AE <= av_writedata[1];
if (av_writedata[10] & ~activity)
ac <= 1'b0;
end
else
begin
fifo_wr <= ~fifo_FF;
woverflow <= fifo_FF;
end
// read
if (av_chipselect & ~av_read_n & av_waitrequest)
begin
// addr 1 is interrupt; addr 0 is data
if (~av_address)
rvalid <= ~fifo_EF;
read_0 <= ~av_address;
end
end
end
assign fifo_wdata = av_writedata[7 : 0];
assign fifo_rd = (av_chipselect & ~av_read_n & av_waitrequest & ~av_address) ? ~fifo_EF : 1'b0;
assign av_readdata = read_0 ? { {9{1'b0}},rfifo_full,rfifo_used,rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,fifo_rdata } : { {9{1'b0}},(7'h40 - {fifo_FF,wfifo_used}),rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,{6{1'b0}},ien_AE,ien_AF };
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
readyfordata <= 0;
else
readyfordata <= ~fifo_FF;
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
// Tie off Atlantic Interface signals not used for simulation
always @(posedge clk)
begin
sim_t_pause <= 1'b0;
sim_t_ena <= 1'b0;
sim_t_dat <= t_dav ? r_dat : {8{r_val}};
sim_r_ena <= 1'b0;
end
assign r_ena = sim_r_ena;
assign t_ena = sim_t_ena;
assign t_dat = sim_t_dat;
assign t_pause = sim_t_pause;
always @(fifo_EF)
begin
dataavailable = ~fifo_EF;
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// alt_jtag_atlantic niosii_jtag_uart_0_alt_jtag_atlantic
// (
// .clk (clk),
// .r_dat (r_dat),
// .r_ena (r_ena),
// .r_val (r_val),
// .rst_n (rst_n),
// .t_dat (t_dat),
// .t_dav (t_dav),
// .t_ena (t_ena),
// .t_pause (t_pause)
// );
//
// defparam niosii_jtag_uart_0_alt_jtag_atlantic.INSTANCE_ID = 0,
// niosii_jtag_uart_0_alt_jtag_atlantic.LOG2_RXFIFO_DEPTH = 6,
// niosii_jtag_uart_0_alt_jtag_atlantic.LOG2_TXFIFO_DEPTH = 6,
// niosii_jtag_uart_0_alt_jtag_atlantic.SLD_AUTO_INSTANCE_INDEX = "YES";
//
// always @(posedge clk or negedge rst_n)
// begin
// if (rst_n == 0)
// dataavailable <= 0;
// else
// dataavailable <= ~fifo_EF;
// end
//
//
//synthesis read_comments_as_HDL off
endmodule
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_system_onchip_memory2_0 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
)
;
parameter INIT_FILE = "soc_system_onchip_memory2_0.hex";
output [ 63: 0] readdata;
input [ 12: 0] address;
input [ 7: 0] byteenable;
input chipselect;
input clk;
input clken;
input reset;
input reset_req;
input write;
input [ 63: 0] writedata;
wire clocken0;
wire [ 63: 0] readdata;
wire wren;
assign wren = chipselect & write;
assign clocken0 = clken & ~reset_req;
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clk),
.clocken0 (clocken0),
.data_a (writedata),
.q_a (readdata),
.wren_a (wren)
);
defparam the_altsyncram.byte_size = 8,
the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 8192,
the_altsyncram.numwords_a = 8192,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 64,
the_altsyncram.width_byteena_a = 8,
the_altsyncram.widthad_a = 13;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SRDLSTP_1_V
`define SKY130_FD_SC_LP__SRDLSTP_1_V
/**
* srdlstp: ????.
*
* Verilog wrapper for srdlstp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__srdlstp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__srdlstp_1 (
Q ,
SET_B ,
D ,
GATE ,
SLEEP_B,
KAPWR ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input SET_B ;
input D ;
input GATE ;
input SLEEP_B;
input KAPWR ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__srdlstp base (
.Q(Q),
.SET_B(SET_B),
.D(D),
.GATE(GATE),
.SLEEP_B(SLEEP_B),
.KAPWR(KAPWR),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__srdlstp_1 (
Q ,
SET_B ,
D ,
GATE ,
SLEEP_B
);
output Q ;
input SET_B ;
input D ;
input GATE ;
input SLEEP_B;
// Voltage supply signals
supply1 KAPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__srdlstp base (
.Q(Q),
.SET_B(SET_B),
.D(D),
.GATE(GATE),
.SLEEP_B(SLEEP_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__SRDLSTP_1_V
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_dma_cmd_gen # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
input pcie_user_clk,
input pcie_user_rst_n,
output pcie_cmd_rd_en,
input [33:0] pcie_cmd_rd_data,
input pcie_cmd_empty_n,
output prp_fifo_rd_en,
input [C_PCIE_DATA_WIDTH-1:0] prp_fifo_rd_data,
output prp_fifo_free_en,
output [5:4] prp_fifo_free_len,
input prp_fifo_empty_n,
output pcie_rx_cmd_wr_en,
output [33:0] pcie_rx_cmd_wr_data,
input pcie_rx_cmd_full_n,
output pcie_tx_cmd_wr_en,
output [33:0] pcie_tx_cmd_wr_data,
input pcie_tx_cmd_full_n
);
localparam S_IDLE = 15'b000000000000001;
localparam S_CMD0 = 15'b000000000000010;
localparam S_CMD1 = 15'b000000000000100;
localparam S_CMD2 = 15'b000000000001000;
localparam S_CMD3 = 15'b000000000010000;
localparam S_CHECK_PRP_FIFO = 15'b000000000100000;
localparam S_RD_PRP0 = 15'b000000001000000;
localparam S_RD_PRP1 = 15'b000000010000000;
localparam S_PCIE_PRP = 15'b000000100000000;
localparam S_CHECK_PCIE_CMD_FIFO0 = 15'b000001000000000;
localparam S_PCIE_CMD0 = 15'b000010000000000;
localparam S_PCIE_CMD1 = 15'b000100000000000;
localparam S_CHECK_PCIE_CMD_FIFO1 = 15'b001000000000000;
localparam S_PCIE_CMD2 = 15'b010000000000000;
localparam S_PCIE_CMD3 = 15'b100000000000000;
reg [14:0] cur_state;
reg [14:0] next_state;
reg r_dma_cmd_type;
reg r_dma_cmd_dir;
reg r_2st_valid;
reg r_1st_mrd_need;
reg r_2st_mrd_need;
reg [6:0] r_hcmd_slot_tag;
reg r_pcie_rcb_cross;
reg [12:2] r_1st_4b_len;
reg [12:2] r_2st_4b_len;
reg [C_PCIE_ADDR_WIDTH-1:2] r_hcmd_prp_1;
reg [C_PCIE_ADDR_WIDTH-1:2] r_hcmd_prp_2;
reg [63:2] r_prp_1;
reg [63:2] r_prp_2;
reg r_pcie_cmd_rd_en;
reg r_prp_fifo_rd_en;
reg r_prp_fifo_free_en;
reg r_pcie_rx_cmd_wr_en;
reg r_pcie_tx_cmd_wr_en;
reg [3:0] r_pcie_cmd_wr_data_sel;
reg [33:0] r_pcie_cmd_wr_data;
wire w_pcie_cmd_full_n;
assign pcie_cmd_rd_en = r_pcie_cmd_rd_en;
assign prp_fifo_rd_en = r_prp_fifo_rd_en;
assign prp_fifo_free_en = r_prp_fifo_free_en;
assign prp_fifo_free_len = (r_pcie_rcb_cross == 0) ? 2'b01 : 2'b10;
assign pcie_rx_cmd_wr_en = r_pcie_rx_cmd_wr_en;
assign pcie_rx_cmd_wr_data = r_pcie_cmd_wr_data;
assign pcie_tx_cmd_wr_en = r_pcie_tx_cmd_wr_en;
assign pcie_tx_cmd_wr_data = r_pcie_cmd_wr_data;
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0)
cur_state <= S_IDLE;
else
cur_state <= next_state;
end
assign w_pcie_cmd_full_n = (r_dma_cmd_dir == 1'b1) ? pcie_tx_cmd_full_n : pcie_rx_cmd_full_n;
always @ (*)
begin
case(cur_state)
S_IDLE: begin
if(pcie_cmd_empty_n == 1'b1)
next_state <= S_CMD0;
else
next_state <= S_IDLE;
end
S_CMD0: begin
next_state <= S_CMD1;
end
S_CMD1: begin
next_state <= S_CMD2;
end
S_CMD2: begin
next_state <= S_CMD3;
end
S_CMD3: begin
if((r_1st_mrd_need | (r_2st_valid & r_2st_mrd_need)) == 1'b1)
next_state <= S_CHECK_PRP_FIFO;
else
next_state <= S_CHECK_PCIE_CMD_FIFO0;
end
S_CHECK_PRP_FIFO: begin
if(prp_fifo_empty_n == 1)
next_state <= S_RD_PRP0;
else
next_state <= S_CHECK_PRP_FIFO;
end
S_RD_PRP0: begin
if(r_pcie_rcb_cross == 1)
next_state <= S_RD_PRP1;
else
next_state <= S_PCIE_PRP;
end
S_RD_PRP1: begin
next_state <= S_PCIE_PRP;
end
S_PCIE_PRP: begin
next_state <= S_CHECK_PCIE_CMD_FIFO0;
end
S_CHECK_PCIE_CMD_FIFO0: begin
if(w_pcie_cmd_full_n == 1'b1)
next_state <= S_PCIE_CMD0;
else
next_state <= S_CHECK_PCIE_CMD_FIFO0;
end
S_PCIE_CMD0: begin
next_state <= S_PCIE_CMD1;
end
S_PCIE_CMD1: begin
if(r_2st_valid == 1'b1)
next_state <= S_CHECK_PCIE_CMD_FIFO1;
else
next_state <= S_IDLE;
end
S_CHECK_PCIE_CMD_FIFO1: begin
if(w_pcie_cmd_full_n == 1'b1)
next_state <= S_PCIE_CMD2;
else
next_state <= S_CHECK_PCIE_CMD_FIFO1;
end
S_PCIE_CMD2: begin
next_state <= S_PCIE_CMD3;
end
S_PCIE_CMD3: begin
next_state <= S_IDLE;
end
default: begin
next_state <= S_IDLE;
end
endcase
end
always @ (posedge pcie_user_clk)
begin
case(cur_state)
S_IDLE: begin
end
S_CMD0: begin
r_dma_cmd_type <= pcie_cmd_rd_data[11];
r_dma_cmd_dir <= pcie_cmd_rd_data[10];
r_2st_valid <= pcie_cmd_rd_data[9];
r_1st_mrd_need <= pcie_cmd_rd_data[8];
r_2st_mrd_need <= pcie_cmd_rd_data[7];
r_hcmd_slot_tag <= pcie_cmd_rd_data[6:0];
end
S_CMD1: begin
r_pcie_rcb_cross <= pcie_cmd_rd_data[22];
r_1st_4b_len <= pcie_cmd_rd_data[21:11];
r_2st_4b_len <= pcie_cmd_rd_data[10:0];
end
S_CMD2: begin
r_hcmd_prp_1 <= pcie_cmd_rd_data[33:0];
end
S_CMD3: begin
r_hcmd_prp_2 <= {pcie_cmd_rd_data[33:10], 10'b0};
end
S_CHECK_PRP_FIFO: begin
end
S_RD_PRP0: begin
r_prp_1 <= prp_fifo_rd_data[63:2];
r_prp_2 <= prp_fifo_rd_data[127:66];
end
S_RD_PRP1: begin
r_prp_2 <= prp_fifo_rd_data[63:2];
end
S_PCIE_PRP: begin
if(r_1st_mrd_need == 1) begin
r_hcmd_prp_1[C_PCIE_ADDR_WIDTH-1:12] <= r_prp_1[C_PCIE_ADDR_WIDTH-1:12];
r_hcmd_prp_2[C_PCIE_ADDR_WIDTH-1:12] <= r_prp_2[C_PCIE_ADDR_WIDTH-1:12];
end
else begin
r_hcmd_prp_2[C_PCIE_ADDR_WIDTH-1:12] <= r_prp_1[C_PCIE_ADDR_WIDTH-1:12];
end
end
S_CHECK_PCIE_CMD_FIFO0: begin
end
S_PCIE_CMD0: begin
end
S_PCIE_CMD1: begin
end
S_CHECK_PCIE_CMD_FIFO1: begin
end
S_PCIE_CMD2: begin
end
S_PCIE_CMD3: begin
end
default: begin
end
endcase
end
always @ (*)
begin
case(r_pcie_cmd_wr_data_sel) // synthesis parallel_case full_case
4'b0001: r_pcie_cmd_wr_data <= {14'b0, r_dma_cmd_type, ~r_2st_valid, r_hcmd_slot_tag, r_1st_4b_len};
4'b0010: r_pcie_cmd_wr_data <= r_hcmd_prp_1;
4'b0100: r_pcie_cmd_wr_data <= {14'b0, r_dma_cmd_type, 1'b1, r_hcmd_slot_tag, r_2st_4b_len};
4'b1000: r_pcie_cmd_wr_data <= {r_hcmd_prp_2[C_PCIE_ADDR_WIDTH-1:12], 10'b0};
endcase
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
r_pcie_cmd_rd_en <= 0;
r_prp_fifo_rd_en <= 0;
r_prp_fifo_free_en <= 0;
r_pcie_rx_cmd_wr_en <= 0;
r_pcie_tx_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0000;
end
S_CMD0: begin
r_pcie_cmd_rd_en <= 1;
r_prp_fifo_rd_en <= 0;
r_prp_fifo_free_en <= 0;
r_pcie_rx_cmd_wr_en <= 0;
r_pcie_tx_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0000;
end
S_CMD1: begin
r_pcie_cmd_rd_en <= 1;
r_prp_fifo_rd_en <= 0;
r_prp_fifo_free_en <= 0;
r_pcie_rx_cmd_wr_en <= 0;
r_pcie_tx_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0000;
end
S_CMD2: begin
r_pcie_cmd_rd_en <= 1;
r_prp_fifo_rd_en <= 0;
r_prp_fifo_free_en <= 0;
r_pcie_rx_cmd_wr_en <= 0;
r_pcie_tx_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0000;
end
S_CMD3: begin
r_pcie_cmd_rd_en <= 1;
r_prp_fifo_rd_en <= 0;
r_prp_fifo_free_en <= 0;
r_pcie_rx_cmd_wr_en <= 0;
r_pcie_tx_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0000;
end
S_CHECK_PRP_FIFO: begin
r_pcie_cmd_rd_en <= 0;
r_prp_fifo_rd_en <= 0;
r_prp_fifo_free_en <= 0;
r_pcie_rx_cmd_wr_en <= 0;
r_pcie_tx_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0000;
end
S_RD_PRP0: begin
r_pcie_cmd_rd_en <= 0;
r_prp_fifo_rd_en <= 1;
r_prp_fifo_free_en <= 1;
r_pcie_rx_cmd_wr_en <= 0;
r_pcie_tx_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0000;
end
S_RD_PRP1: begin
r_pcie_cmd_rd_en <= 0;
r_prp_fifo_rd_en <= 1;
r_prp_fifo_free_en <= 0;
r_pcie_rx_cmd_wr_en <= 0;
r_pcie_tx_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0000;
end
S_PCIE_PRP: begin
r_pcie_cmd_rd_en <= 0;
r_prp_fifo_rd_en <= 0;
r_prp_fifo_free_en <= 0;
r_pcie_rx_cmd_wr_en <= 0;
r_pcie_tx_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0000;
end
S_CHECK_PCIE_CMD_FIFO0: begin
r_pcie_cmd_rd_en <= 0;
r_prp_fifo_rd_en <= 0;
r_prp_fifo_free_en <= 0;
r_pcie_rx_cmd_wr_en <= 0;
r_pcie_tx_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0000;
end
S_PCIE_CMD0: begin
r_pcie_cmd_rd_en <= 0;
r_prp_fifo_rd_en <= 0;
r_prp_fifo_free_en <= 0;
r_pcie_rx_cmd_wr_en <= ~r_dma_cmd_dir;
r_pcie_tx_cmd_wr_en <= r_dma_cmd_dir;
r_pcie_cmd_wr_data_sel <= 4'b0001;
end
S_PCIE_CMD1: begin
r_pcie_cmd_rd_en <= 0;
r_prp_fifo_rd_en <= 0;
r_prp_fifo_free_en <= 0;
r_pcie_rx_cmd_wr_en <= ~r_dma_cmd_dir;
r_pcie_tx_cmd_wr_en <= r_dma_cmd_dir;
r_pcie_cmd_wr_data_sel <= 4'b0010;
end
S_CHECK_PCIE_CMD_FIFO1: begin
r_pcie_cmd_rd_en <= 0;
r_prp_fifo_rd_en <= 0;
r_prp_fifo_free_en <= 0;
r_pcie_rx_cmd_wr_en <= 0;
r_pcie_tx_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0000;
end
S_PCIE_CMD2: begin
r_pcie_cmd_rd_en <= 0;
r_prp_fifo_rd_en <= 0;
r_prp_fifo_free_en <= 0;
r_pcie_rx_cmd_wr_en <= ~r_dma_cmd_dir;
r_pcie_tx_cmd_wr_en <= r_dma_cmd_dir;
r_pcie_cmd_wr_data_sel <= 4'b0100;
end
S_PCIE_CMD3: begin
r_pcie_cmd_rd_en <= 0;
r_prp_fifo_rd_en <= 0;
r_prp_fifo_free_en <= 0;
r_pcie_rx_cmd_wr_en <= ~r_dma_cmd_dir;
r_pcie_tx_cmd_wr_en <= r_dma_cmd_dir;
r_pcie_cmd_wr_data_sel <= 4'b1000;
end
default: begin
r_pcie_cmd_rd_en <= 0;
r_prp_fifo_rd_en <= 0;
r_prp_fifo_free_en <= 0;
r_pcie_rx_cmd_wr_en <= 0;
r_pcie_tx_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0000;
end
endcase
end
endmodule |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLXTP_FUNCTIONAL_V
`define SKY130_FD_SC_HS__DLXTP_FUNCTIONAL_V
/**
* dlxtp: Delay latch, non-inverted enable, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_dl_p_pg/sky130_fd_sc_hs__u_dl_p_pg.v"
`celldefine
module sky130_fd_sc_hs__dlxtp (
VPWR,
VGND,
Q ,
D ,
GATE
);
// Module ports
input VPWR;
input VGND;
output Q ;
input D ;
input GATE;
// Local signals
wire buf_Q GATE_delayed;
wire buf_Q D_delayed ;
wire buf_Q ;
// Name Output Other arguments
sky130_fd_sc_hs__u_dl_p_pg u_dl_p_pg0 (buf_Q , D, GATE, VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLXTP_FUNCTIONAL_V |
Require Import List.
Import ListNotations.
Require Import Relations.
Require Import Omega.
Require Import StructTact.StructTactics.
Require Import StructTact.Update.
Require Import InfSeqExt.infseq.
Require Import InfSeqExt.classical.
Require Import Chord.InfSeqTactics.
Require Import Chord.Chord.
Require Import Chord.HandlerLemmas.
Require Import Chord.SystemReachable.
Require Import Chord.SystemLemmas.
Require Import Chord.LabeledLemmas.
Require Import Chord.ChannelLemmas.
Require Import Chord.LiveNodesNotClients.
Require Import Chord.QueryInvariant.
Require Import Chord.NodesHaveState.
Set Bullet Behavior "Strict Subproofs".
(* The (blocked_by s h) relation relates a live node h to a node s when
a message from h is stored in the delayed_queries list at s. *)
Definition blocked_by (gst : global_state) (s h : addr) : Prop :=
In h (nodes gst) /\
In s (nodes gst) /\
exists st__h st__s dstp q m,
sigma gst h = Some st__h /\
sigma gst s = Some st__s /\
cur_request st__h = Some (dstp, q, m) /\
addr_of dstp = s /\
In (h, m) (delayed_queries st__s).
Lemma blocked_by_intro :
forall gst s h,
In h (nodes gst) ->
In s (nodes gst) ->
forall st__h st__s dstp q m,
sigma gst h = Some st__h ->
sigma gst s = Some st__s ->
cur_request st__h = Some (dstp, q, m) ->
addr_of dstp = s ->
In (h, m) (delayed_queries st__s) ->
blocked_by gst s h.
Proof.
unfold blocked_by.
intuition (repeat eexists; eauto).
Qed.
Hint Resolve blocked_by_intro.
(* There is a cycle in a relation iff there's an element related to
itself by the transitive closure of the relation. *)
Definition has_cycle {A : Type} (R : A -> A -> Prop) : Prop :=
exists x,
clos_trans_1n A R x x.
(* A circular wait (in a given state) is a cycle in the blocked_by
relation (for that state). *)
Definition circular_wait (occ : occurrence) : Prop :=
has_cycle (blocked_by (occ_gst occ)).
Inductive fin_chain {A : Type} (R : A -> A -> Prop) : list A -> Prop :=
| FinChainNil : fin_chain R []
| FinChainOne : forall x, fin_chain R [x]
| FinChainCons : forall x y l,
R x y ->
fin_chain R (y :: l) ->
fin_chain R (x :: y :: l).
Hint Constructors fin_chain.
Theorem pigeon_cycle :
forall A (R : A -> A -> Prop) l,
(forall a b, R a b -> In a l /\ In b l) ->
forall c,
fin_chain R c ->
length c > length l ->
has_cycle R.
Proof.
(* not sure I need this machinery yet *)
Admitted.
Definition busy_if_live (h : addr) (occ : occurrence) :=
forall st,
live_node (occ_gst occ) h ->
sigma (occ_gst occ) h = Some st ->
cur_request st <> None.
Definition not_busy_if_live (h : addr) (occ : occurrence) :=
forall st,
live_node (occ_gst occ) h ->
sigma (occ_gst occ) h = Some st ->
cur_request st = None.
Lemma now_const :
forall T (P : T -> Prop),
(forall t, P t) ->
forall ex,
(now P) ex.
Proof.
destruct ex.
simpl; auto.
Qed.
Hint Resolve now_const.
Lemma always_const :
forall T (P : infseq T -> Prop),
(forall s, P s) ->
forall ex,
always P ex.
Proof.
intros.
eapply always_monotonic; [|eapply always_true].
auto.
Qed.
Hint Resolve always_const.
Theorem joined_nodes_never_run_join :
forall gst h st,
reachable_st gst ->
sigma gst h = Some st ->
joined st = true ->
forall dst q m k,
cur_request st = Some (dst, q, m) ->
q <> Join k.
Proof.
Admitted.
Lemma continuously_false_false :
forall T (s : infseq T),
continuously (fun _ => False) s ->
False.
Proof.
intros.
induction 0 as [[o s] ?|o s];
now inv_prop always.
Qed.
Theorem l_enabled_RecvMsg_means_in_msgs :
forall src dst m occ,
l_enabled (RecvMsg src dst m) occ ->
In (src, (dst, m)) (msgs (occ_gst occ)).
Proof.
intros.
inv_prop l_enabled.
inv_labeled_step.
handler_def.
repeat find_rewrite; destruct m0 as [? [? ?]];
repeat find_rewrite || find_injection;
eauto with datatypes.
Qed.
Hint Resolve l_enabled_RecvMsg_means_in_msgs.
Theorem cur_request_constant_when_res_on_wire :
forall gst l gst' h st st' dstp q m,
labeled_step_dynamic gst l gst' ->
sigma gst h = Some st ->
sigma gst' h = Some st' ->
cur_request st = Some (dstp, q, m) ->
query_request q m ->
In (h, (addr_of dstp, m)) (msgs gst) ->
~ In (addr_of dstp) (failed_nodes gst) ->
cur_request st' = Some (dstp, q, m).
Proof.
Admitted.
Theorem req_on_wire_until_response :
forall ex h,
lb_execution ex ->
reachable_st (occ_gst (hd ex)) ->
strong_local_fairness ex ->
live_node (occ_gst (hd ex)) h ->
forall dstp q m st,
sigma (occ_gst (hd ex)) h = Some st ->
cur_request st = Some (dstp, q, m) ->
query_request q m ->
In m (channel (occ_gst (hd ex)) h (addr_of dstp)) ->
live_node (occ_gst (hd ex)) (addr_of dstp) ->
until (now (fun o =>
In m (channel (occ_gst o) h (addr_of dstp))))
(next (now (fun o =>
blocked_by (occ_gst o) (addr_of dstp) h \/
exists res,
request_response_pair m res /\
In res (channel (occ_gst o) (addr_of dstp) h))))
ex.
Proof.
intros.
assert (until (now (l_enabled (RecvMsg h (addr_of dstp) m)))
(now (occurred (RecvMsg h (addr_of dstp) m))) ex).
{
find_apply_lem_hyp in_channel_in_msgs.
inv_prop live_node; expand_def; eauto.
eapply RecvMsg_strong_until_occurred;
eauto using strong_local_fairness_weak.
}
assert (forall st, sigma (occ_gst (hd ex)) h = Some st -> cur_request st = Some (dstp, q, m))
by (intros; congruence).
repeat match goal with
| H: In _ (channel _ _ _) |- _ => clear H
| H: sigma _ _ = _ |- _ => clear H
| H: cur_request st = _ |- _ => clear H
end.
match goal with
| H: until _ _ _ |- _ => induction H
end.
- destruct s as [o [o' s]].
eapply U0; simpl in *.
unfold occurred in *;
inv_lb_execution;
inv_labeled_step;
clean_up_labeled_step_cases.
handler_def.
destruct m0 as [? [? ?]]; repeat find_rewrite || find_injection.
simpl (fst _) in *; simpl (snd _) in *.
find_copy_apply_lem_hyp requests_get_response_or_queued; eauto.
break_or_hyp; break_and.
+ left.
repeat split; invar_eauto.
simpl.
assert (live_node (occ_gst o') a) by invar_eauto.
assert (live_node (occ_gst o') (addr_of dstp)) by invar_eauto.
assert (live_node (occ_gst o) a) by invar_eauto.
assert (live_node (occ_gst o) (addr_of dstp)) by invar_eauto.
do 4 invcs_prop live_node; expand_def.
pose proof (query_message_ok_invariant (occ_gst o') ltac:(invar_eauto) a (addr_of dstp)) as Qi'.
do 2 insterU Qi'.
repeat conclude Qi' eauto.
pose proof (query_message_ok_invariant (occ_gst o) ltac:(invar_eauto) a (addr_of dstp)) as Qi.
do 2 insterU Qi.
repeat conclude Qi eauto.
rewrite update_same.
assert (cur_request x1 = Some (dstp, q, p)) by eauto.
assert (cur_request st0 = cur_request d).
{
destruct (cur_request x2) as [[[? ?] ?]|] eqn:?.
- repeat find_rewrite || find_injection.
simpl in *.
repeat find_inversion.
repeat find_reverse_rewrite.
eapply recv_msg_not_right_response_preserves_cur_request; eauto.
- congruence.
}
destruct_update.
* repeat (find_rewrite; find_injection).
repeat eexists; eauto.
instantiate (1:=q).
congruence.
* repeat eexists; eauto.
+ right.
break_exists_exists; intuition eauto.
apply in_msgs_in_channel; simpl.
apply in_or_app; left.
apply in_map_iff; eauto.
- destruct s as [o [o' s]]; simpl in *.
apply U_next; eauto.
+ simpl.
eapply in_msgs_in_channel, l_enabled_RecvMsg_means_in_msgs.
eauto.
+ apply IHuntil; invar_eauto.
intros.
inv_prop lb_execution.
repeat invcs_prop live_node; expand_def.
eapply cur_request_constant_when_res_on_wire; invar_eauto.
Qed.
Theorem have_cur_request_msg_on_wire_preserves :
forall h dst ex q m r,
reachable_st (occ_gst (hd ex)) ->
live_node (occ_gst (hd ex)) h ->
(exists st, sigma (occ_gst (hd ex)) (addr_of dst) = Some st) ->
lb_execution ex ->
In r (channel (occ_gst (hd ex)) (addr_of dst) h) ->
(forall st,
sigma (occ_gst (hd ex)) h = Some st ->
cur_request st = Some (dst, q, m)) ->
request_response_pair m r ->
weak_until (now (fun o => In r (channel (occ_gst o) (addr_of dst) h) ->
exists st,
sigma (occ_gst o) h = Some st /\
cur_request st = Some (dst, q, m)))
(now (fun o => ~ In r (channel (occ_gst o) (addr_of dst) h)))
ex.
Proof.
cofix c.
intros.
eapply W_tl; simpl.
- intros.
destruct ex; simpl.
repeat invcs_prop live_node; expand_def.
eexists; split; eauto.
- destruct ex as [o [o' ex]].
set (gst := occ_gst o).
pose proof (query_message_ok'_invariant gst ltac:(eauto) h (addr_of dst)).
destruct (label_eq_dec (RecvMsg (addr_of dst) h r) (occ_label o)).
+ eapply W0.
simpl.
inv_prop lb_execution.
repeat find_reverse_rewrite.
inv_labeled_step; clean_up_labeled_step_cases.
repeat find_rewrite; intuition.
repeat invcs_prop live_node; expand_def.
copy_eapply_prop_hyp query_message_ok' sigma; eauto.
inv_prop query_message_ok';
try inv_prop query_message_ok;
try solve [congruence
|eapply_prop no_responses;
repeat find_rewrite; eauto].
* assert (res0 = r) by admit; subst.
admit.
* assert (res0 = r) by admit; subst.
admit.
* inv_option_map.
repeat find_rewrite.
admit.
* admit.
+ assert (live_node (occ_gst o') h) by invar_eauto.
apply c; invar_eauto.
* admit.
* apply in_msgs_in_channel.
simpl.
inv_lb_execution.
inv_labeled_step; repeat find_rewrite; simpl.
-- eauto with datatypes.
-- handler_def.
assert (m0 <> (addr_of dst, (h, r)))
by (destruct m0 as [? [? ?]]; simpl in *; congruence).
find_apply_lem_hyp in_channel_in_msgs; simpl in *.
repeat find_rewrite.
apply in_or_app; right.
find_apply_lem_hyp in_app_or; simpl in *.
intuition eauto with datatypes.
-- eauto.
-- assert (m0 <> (addr_of dst, (h, r))).
{
intro; subst.
exfalso; eapply live_nodes_not_clients; invar_eauto.
}
find_apply_lem_hyp in_channel_in_msgs; simpl in *.
repeat find_rewrite.
find_apply_lem_hyp in_app_or; simpl in *.
intuition eauto with datatypes.
* admit.
Admitted.
Theorem never_stuck_on_non_stabilize_with_res_on_wire :
forall ex h,
lb_execution ex ->
reachable_st (occ_gst (hd ex)) ->
strong_local_fairness ex ->
live_node (occ_gst (hd ex)) h ->
forall dstp q m res st,
q <> Stabilize ->
query_response q res ->
In res (channel (occ_gst (hd ex)) (addr_of dstp) h) ->
sigma (occ_gst (hd ex)) h = Some st ->
cur_request st = Some (dstp, q, m) ->
always (now
(fun o =>
forall st,
sigma (occ_gst o) h = Some st ->
cur_request st <> None))
ex ->
False.
Proof.
intros.
cut (continuously (fun _ => False) ex);
[eauto using continuously_false_false|].
find_copy_eapply_lem_hyp have_cur_request_msg_on_wire_preserves; eauto;
[
|eapply nodes_have_state; try eapply sent_non_client_message_means_in_nodes; invar_eauto;
inv_prop query_response; intro; inv_prop client_payload
|intros; repeat find_rewrite; find_injection; eauto
].
find_apply_lem_hyp in_channel_in_msgs.
find_eapply_lem_hyp RecvMsg_strong_until_occurred;
eauto using strong_local_fairness_weak, l_enabled_RecvMsg_In_msgs.
match goal with
| H: In _ (msgs _) |- _ => clear H
end.
match goal with
| H: until _ _ _ |- _ => induction H
end.
- destruct s as [o [o' [o'' s]]]; simpl in *.
break_and; do 2 invcs_prop lb_execution.
assert (In res0 (channel (occ_gst o) (addr_of dstp) h)).
{ simpl in *.
unfold occurred in *.
repeat find_reverse_rewrite.
inv_prop RecvMsg; clean_up_labeled_step_cases.
handler_def; find_injection.
apply in_msgs_in_channel; repeat find_rewrite.
replace (fst m0, (fst (snd m0), snd (snd m0))) with m0
by (destruct m0 as [? [? ?]]; reflexivity).
eauto with datatypes.
}
inv_prop channel;
[simpl in *; tauto|].
simpl in *; concludes.
expand_def; repeat find_rewrite || find_injection.
assert (exists st, sigma (occ_gst o') h = Some st /\ cur_request st = None).
{
unfold occurred in *; repeat find_reverse_rewrite.
inv_prop (labeled_step_dynamic (occ_gst o)); clean_up_labeled_step_cases.
recover_msg_from_recv_step_equality.
subst; simpl in *.
find_apply_lem_hyp always_now'; simpl in * |-.
repeat find_rewrite; simpl in *.
eexists; rewrite_update; split; eauto.
repeat find_rewrite || find_injection.
eapply recv_handler_response_clears_cur_request_q_single;
try eapply recv_handler_labeling; eauto.
intros.
eapply joined_nodes_never_run_join; invar_eauto.
inv_prop live_node; expand_def; congruence.
}
break_exists; expand_def.
find_apply_lem_hyp always_invar; find_apply_lem_hyp always_now'.
assert (cur_request _ <> None) by eauto.
tauto.
- inv_prop weak_until.
+ simpl in *; intuition; find_false; eauto.
+ eapply E_next, IHuntil; invar_eauto.
Qed.
Theorem always_stuck_blocked_always_blocked :
forall ex h,
lb_execution ex ->
reachable_st (occ_gst (hd ex)) ->
strong_local_fairness ex ->
live_node (occ_gst (hd ex)) h ->
forall dstp q m,
live_node (occ_gst (hd ex)) (addr_of dstp) ->
always (now
(fun o =>
forall st,
sigma (occ_gst o) h = Some st ->
cur_request st = Some (dstp, q, m)))
ex ->
blocked_by (occ_gst (hd ex)) (addr_of dstp) h ->
always (now (fun o => blocked_by (occ_gst o) (addr_of dstp) h)) ex.
Proof.
intros.
inv_prop blocked_by.
Admitted.
Theorem stuck_on_a_single_query_means_blocked :
forall ex h,
lb_execution ex ->
reachable_st (occ_gst (hd ex)) ->
strong_local_fairness ex ->
live_node (occ_gst (hd ex)) h ->
forall dstp q m,
live_node (occ_gst (hd ex)) (addr_of dstp) ->
always (now
(fun o =>
forall st,
sigma (occ_gst o) h = Some st ->
cur_request st = Some (dstp, q, m)))
ex ->
continuously (now (fun o => blocked_by (occ_gst o) (addr_of dstp) h)) ex.
Proof.
intros.
destruct ex as [o ex].
pose proof (query_message_ok'_invariant
(occ_gst o) ltac:(eauto) h (addr_of dstp))
as Qok.
set (gst := occ_gst o).
set (dst := addr_of dstp).
find_copy_apply_lem_hyp (live_node_means_state_exists gst h).
break_exists_name st__h.
find_copy_apply_lem_hyp (live_node_means_state_exists gst dst).
break_exists_name st__dst.
specialize (Qok st__h ltac:(eauto)).
find_copy_apply_lem_hyp always_now; simpl in *.
inv_prop query_message_ok';
try inv_prop query_message_ok.
- find_apply_hyp_hyp; congruence.
- find_apply_hyp_hyp; congruence.
- admit.
- admit.
- eapply always_continuously, always_stuck_blocked_always_blocked;
invar_eauto.
admit.
- admit.
- admit.
Admitted.
Lemma blocking_node_continuously_also_blocked :
forall ex,
lb_execution ex ->
reachable_st (occ_gst (hd ex)) ->
strong_local_fairness ex ->
forall h s,
always (now (fun o => blocked_by (occ_gst o) s h)) ex ->
exists w,
continuously (now (fun o => blocked_by (occ_gst o) w s)) ex.
Proof.
Admitted.
Lemma now_and_tl_comm :
forall T (P Q : T -> Prop) s,
(now P /\_ now Q) s = now (fun o => P o /\ Q o) s.
Proof.
intros.
destruct s.
reflexivity.
Qed.
Hint Rewrite now_and_tl_comm.
Theorem query_always_stuck_gives_chain :
forall k ex h,
lb_execution ex ->
reachable_st (occ_gst (hd ex)) ->
strong_local_fairness ex ->
live_node (occ_gst (hd ex)) h ->
always (~_ (now circular_wait)) ex ->
forall dstp q m,
always (now (fun o => forall st,
sigma (occ_gst o) h = Some st ->
cur_request st = Some (dstp, q, m)))
ex ->
k >= 1 ->
exists c,
length c = k /\
In h c /\
continuously
(now (fun occ => fin_chain (blocked_by (occ_gst occ)) c)) ex.
Proof.
induction k as [|[|?]]; intros.
- omega.
- exists [h]; intuition.
constructor; eauto.
- find_copy_eapply_lem_hyp IHk; eauto; [|omega].
break_exists_name c; intuition.
induction H9; intros; subst.
+ destruct c as [|w [|w' c]];
[simpl in * |-; tauto| |].
* assert (w = h) by (simpl in *; tauto); subst.
exists [addr_of dstp; h]; intuition.
simpl in *; congruence.
find_copy_eapply_lem_hyp stuck_on_a_single_query_means_blocked; eauto.
find_apply_lem_hyp always_continuously.
find_continuously_and_tl.
eapply continuously_monotonic; try eassumption.
intro s0; rewrite now_and_tl_comm.
apply now_monotonic; intuition eauto.
admit.
* assert (always (now (fun o => blocked_by (occ_gst o) w w')) s).
{
eapply always_monotonic;
[eapply now_monotonic|eassumption].
intros; now inv_prop @fin_chain.
}
find_eapply_lem_hyp blocking_node_continuously_also_blocked; eauto.
break_exists_name w0.
exists (w0 :: w :: w' :: c).
intuition; simpl in *; try omega.
find_apply_lem_hyp always_continuously.
find_continuously_and_tl.
eapply continuously_monotonic; try eassumption.
intro s0; rewrite now_and_tl_comm.
apply now_monotonic; intuition eauto.
+ assert (exists c : list addr,
length c = S (S n) /\
In h c /\
continuously (now (fun occ => fin_chain (blocked_by (occ_gst occ)) c)) s)
by (eapply IHeventually; invar_eauto).
break_exists_exists; intuition.
constructor; now auto.
Admitted.
Theorem never_stopping_means_stuck_on_a_single_query :
forall ex h,
lb_execution ex ->
reachable_st (occ_gst (hd ex)) ->
strong_local_fairness ex ->
live_node (occ_gst (hd ex)) h ->
forall st dstp q m,
sigma (occ_gst (hd ex)) h = Some st ->
cur_request st = Some (dstp, q, m) ->
always (~_ (now circular_wait)) ex ->
always (now (fun o => forall st',
sigma (occ_gst o) h = Some st' ->
cur_request st' <> None)) ex ->
exists dstp' q' m',
continuously (now (fun o =>
forall st',
sigma (occ_gst o) h = Some st' ->
cur_request st' = Some (dstp', q', m')))
ex.
Proof.
Admitted.
Theorem queries_dont_always_not_stop :
forall ex h,
lb_execution ex ->
reachable_st (occ_gst (hd ex)) ->
strong_local_fairness ex ->
live_node (occ_gst (hd ex)) h ->
forall st dstp q m,
sigma (occ_gst (hd ex)) h = Some st ->
cur_request st = Some (dstp, q, m) ->
always (~_ (now circular_wait)) ex ->
~ always (now (fun o => forall st',
sigma (occ_gst o) h = Some st' ->
cur_request st' <> None)) ex.
Proof.
intuition.
cut (eventually (now circular_wait) ex).
{
intros.
clear H3.
induction H7.
- repeat find_apply_lem_hyp always_now'.
unfold not_tl in *.
destruct s; auto.
- apply IHeventually; invar_eauto.
}
find_eapply_lem_hyp never_stopping_means_stuck_on_a_single_query; eauto; break_exists.
match goal with
| H: sigma _ h = Some _ |- _ => clear H
end.
match goal with
| H: continuously _ _ |- _ => induction H
end.
- remember (length (nodes (occ_gst (hd s)))) as k.
find_eapply_lem_hyp (query_always_stuck_gives_chain (S k)); omega || eauto.
break_exists; break_and.
match goal with
| H: continuously _ _ |- _ => induction H
end.
+ destruct s; apply E0.
find_apply_lem_hyp always_now'; simpl in *.
eapply pigeon_cycle with (l := nodes (occ_gst o));
[|eassumption|omega].
intros; inv_prop blocked_by; tauto.
+ eapply E_next, IHeventually; invar_eauto.
inv_prop lb_execution.
inv_prop labeled_step_dynamic;
simpl;
repeat (find_rewrite || find_injection);
auto using apply_handler_result_nodes.
- eapply E_next, IHeventually; invar_eauto.
Qed.
Theorem queries_eventually_stop' :
forall ex h,
lb_execution ex ->
reachable_st (occ_gst (hd ex)) ->
strong_local_fairness ex ->
live_node (occ_gst (hd ex)) h ->
forall st dstp q m,
sigma (occ_gst (hd ex)) h = Some st ->
cur_request st = Some (dstp, q, m) ->
always (~_ (now circular_wait)) ex ->
eventually (now (fun o => forall st',
sigma (occ_gst o) h = Some st' ->
cur_request st' = None)) ex.
Proof.
intros.
find_eapply_lem_hyp queries_dont_always_not_stop; eauto.
eapply not_always_eventually_not in H5.
eapply eventually_monotonic_simple; [|eassumption].
unfold not_tl; destruct s; simpl.
intros.
apply Classical_Prop.NNPP.
firstorder.
Qed.
(** the big assumption for inf_often stabilization *)
Theorem queries_eventually_stop :
forall ex h,
lb_execution ex ->
reachable_st (occ_gst (hd ex)) ->
strong_local_fairness ex ->
live_node (occ_gst (hd ex)) h ->
busy_if_live h (hd ex) ->
always (~_ (now circular_wait)) ex ->
eventually (now (not_busy_if_live h)) ex.
Proof.
intros.
inv_prop live_node; repeat (break_exists || break_and).
copy_eapply_prop_hyp busy_if_live live_node;
forwards; eauto; concludes; eauto.
destruct (cur_request x) as [[[? ?] ?]|] eqn:?; try congruence.
find_eapply_lem_hyp queries_eventually_stop'; eauto.
eapply eventually_monotonic_simple; try eassumption.
destruct s; unfold not_busy_if_live.
simpl; firstorder.
(*
This is tricky.
If you have an open request, you're in the middle of some operation.
Operations (stabilization, rectifying, etc) undertaken by joined nodes complete
in finitely many request-response pairs.
A request eventually gets a response if there are no circular waits...
DIFFICULTY: Ryan
USED: In phase one for the proof of eventual stabilization.
*)
Qed.
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O22AI_TB_V
`define SKY130_FD_SC_HDLL__O22AI_TB_V
/**
* o22ai: 2-input OR into both inputs of 2-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__o22ai.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg B2;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A1 = 1'b1;
#200 A2 = 1'b1;
#220 B1 = 1'b1;
#240 B2 = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A1 = 1'b0;
#360 A2 = 1'b0;
#380 B1 = 1'b0;
#400 B2 = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 B2 = 1'b1;
#600 B1 = 1'b1;
#620 A2 = 1'b1;
#640 A1 = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 B2 = 1'bx;
#760 B1 = 1'bx;
#780 A2 = 1'bx;
#800 A1 = 1'bx;
end
sky130_fd_sc_hdll__o22ai dut (.A1(A1), .A2(A2), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O22AI_TB_V
|
/*
* PS2 Mouse Interface
* Copyright (C) 2010 Donna Polehn <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module ps2_mouse (
input clk, // Clock Input
input reset, // Reset Input
inout ps2_clk, // PS2 Clock, Bidirectional
inout ps2_dat, // PS2 Data, Bidirectional
input [7:0] the_command, // Command to send to mouse
input send_command, // Signal to send
output command_was_sent, // Signal command finished sending
output error_communication_timed_out,
output [7:0] received_data, // Received data
output received_data_en, // If 1 - new data has been received
output start_receiving_data,
output wait_for_incoming_data
);
// --------------------------------------------------------------------
// Internal wires and registers Declarations
// --------------------------------------------------------------------
wire ps2_clk_posedge; // Internal Wires
wire ps2_clk_negedge;
reg [7:0] idle_counter; // Internal Registers
reg ps2_clk_reg;
reg ps2_data_reg;
reg last_ps2_clk;
reg [2:0] ns_ps2_transceiver; // State Machine Registers
reg [2:0] s_ps2_transceiver;
// --------------------------------------------------------------------
// Constant Declarations
// --------------------------------------------------------------------
localparam PS2_STATE_0_IDLE = 3'h0, // states
PS2_STATE_1_DATA_IN = 3'h1,
PS2_STATE_2_COMMAND_OUT = 3'h2,
PS2_STATE_3_END_TRANSFER = 3'h3,
PS2_STATE_4_END_DELAYED = 3'h4;
// --------------------------------------------------------------------
// Finite State Machine(s)
// --------------------------------------------------------------------
always @(posedge clk) begin
if(reset == 1'b1) s_ps2_transceiver <= PS2_STATE_0_IDLE;
else s_ps2_transceiver <= ns_ps2_transceiver;
end
always @(*) begin
ns_ps2_transceiver = PS2_STATE_0_IDLE; // Defaults
case (s_ps2_transceiver)
PS2_STATE_0_IDLE:
begin
if((idle_counter == 8'hFF) && (send_command == 1'b1))
ns_ps2_transceiver = PS2_STATE_2_COMMAND_OUT;
else if ((ps2_data_reg == 1'b0) && (ps2_clk_posedge == 1'b1))
ns_ps2_transceiver = PS2_STATE_1_DATA_IN;
else ns_ps2_transceiver = PS2_STATE_0_IDLE;
end
PS2_STATE_1_DATA_IN:
begin
// if((received_data_en == 1'b1) && (ps2_clk_posedge == 1'b1))
if((received_data_en == 1'b1)) ns_ps2_transceiver = PS2_STATE_0_IDLE;
else ns_ps2_transceiver = PS2_STATE_1_DATA_IN;
end
PS2_STATE_2_COMMAND_OUT:
begin
if((command_was_sent == 1'b1) || (error_communication_timed_out == 1'b1))
ns_ps2_transceiver = PS2_STATE_3_END_TRANSFER;
else ns_ps2_transceiver = PS2_STATE_2_COMMAND_OUT;
end
PS2_STATE_3_END_TRANSFER:
begin
if(send_command == 1'b0) ns_ps2_transceiver = PS2_STATE_0_IDLE;
else if((ps2_data_reg == 1'b0) && (ps2_clk_posedge == 1'b1))
ns_ps2_transceiver = PS2_STATE_4_END_DELAYED;
else ns_ps2_transceiver = PS2_STATE_3_END_TRANSFER;
end
PS2_STATE_4_END_DELAYED:
begin
if(received_data_en == 1'b1) begin
if(send_command == 1'b0) ns_ps2_transceiver = PS2_STATE_0_IDLE;
else ns_ps2_transceiver = PS2_STATE_3_END_TRANSFER;
end
else ns_ps2_transceiver = PS2_STATE_4_END_DELAYED;
end
default:
ns_ps2_transceiver = PS2_STATE_0_IDLE;
endcase
end
// --------------------------------------------------------------------
// Sequential logic
// --------------------------------------------------------------------
always @(posedge clk) begin
if(reset == 1'b1) begin
last_ps2_clk <= 1'b1;
ps2_clk_reg <= 1'b1;
ps2_data_reg <= 1'b1;
end
else begin
last_ps2_clk <= ps2_clk_reg;
ps2_clk_reg <= ps2_clk;
ps2_data_reg <= ps2_dat;
end
end
always @(posedge clk) begin
if(reset == 1'b1) idle_counter <= 6'h00;
else if((s_ps2_transceiver == PS2_STATE_0_IDLE) && (idle_counter != 8'hFF))
idle_counter <= idle_counter + 6'h01;
else if (s_ps2_transceiver != PS2_STATE_0_IDLE)
idle_counter <= 6'h00;
end
// --------------------------------------------------------------------
// Combinational logic
// --------------------------------------------------------------------
assign ps2_clk_posedge = ((ps2_clk_reg == 1'b1) && (last_ps2_clk == 1'b0)) ? 1'b1 : 1'b0;
assign ps2_clk_negedge = ((ps2_clk_reg == 1'b0) && (last_ps2_clk == 1'b1)) ? 1'b1 : 1'b0;
assign start_receiving_data = (s_ps2_transceiver == PS2_STATE_1_DATA_IN);
assign wait_for_incoming_data = (s_ps2_transceiver == PS2_STATE_3_END_TRANSFER);
// --------------------------------------------------------------------
// Internal Modules
// --------------------------------------------------------------------
ps2_mouse_cmdout mouse_cmdout (
.clk (clk), // Inputs
.reset (reset),
.the_command (the_command),
.send_command (send_command),
.ps2_clk_posedge (ps2_clk_posedge),
.ps2_clk_negedge (ps2_clk_negedge),
.ps2_clk (ps2_clk), // Bidirectionals
.ps2_dat (ps2_dat),
.command_was_sent (command_was_sent), // Outputs
.error_communication_timed_out (error_communication_timed_out)
);
ps2_mouse_datain mouse_datain (
.clk (clk), // Inputs
.reset (reset),
.wait_for_incoming_data (wait_for_incoming_data),
.start_receiving_data (start_receiving_data),
.ps2_clk_posedge (ps2_clk_posedge),
.ps2_clk_negedge (ps2_clk_negedge),
.ps2_data (ps2_data_reg),
.received_data (received_data), // Outputs
.received_data_en (received_data_en)
);
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
// Date : Mon Sep 18 12:32:27 2017
// Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode funcsim
// C:/Projects/srio_test/srio_test/srio_test.srcs/sources_1/ip/vio_0/vio_0_sim_netlist.v
// Design : vio_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7k325tffg676-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "vio_0,vio,{}" *) (* X_CORE_INFO = "vio,Vivado 2016.3" *)
(* NotValidForBitStream *)
module vio_0
(clk,
probe_in0,
probe_in1,
probe_in2,
probe_in3);
input clk;
input [0:0]probe_in0;
input [0:0]probe_in1;
input [0:0]probe_in2;
input [0:0]probe_in3;
wire clk;
wire [0:0]probe_in0;
wire [0:0]probe_in1;
wire [0:0]probe_in2;
wire [0:0]probe_in3;
wire [0:0]NLW_inst_probe_out0_UNCONNECTED;
wire [0:0]NLW_inst_probe_out1_UNCONNECTED;
wire [0:0]NLW_inst_probe_out10_UNCONNECTED;
wire [0:0]NLW_inst_probe_out100_UNCONNECTED;
wire [0:0]NLW_inst_probe_out101_UNCONNECTED;
wire [0:0]NLW_inst_probe_out102_UNCONNECTED;
wire [0:0]NLW_inst_probe_out103_UNCONNECTED;
wire [0:0]NLW_inst_probe_out104_UNCONNECTED;
wire [0:0]NLW_inst_probe_out105_UNCONNECTED;
wire [0:0]NLW_inst_probe_out106_UNCONNECTED;
wire [0:0]NLW_inst_probe_out107_UNCONNECTED;
wire [0:0]NLW_inst_probe_out108_UNCONNECTED;
wire [0:0]NLW_inst_probe_out109_UNCONNECTED;
wire [0:0]NLW_inst_probe_out11_UNCONNECTED;
wire [0:0]NLW_inst_probe_out110_UNCONNECTED;
wire [0:0]NLW_inst_probe_out111_UNCONNECTED;
wire [0:0]NLW_inst_probe_out112_UNCONNECTED;
wire [0:0]NLW_inst_probe_out113_UNCONNECTED;
wire [0:0]NLW_inst_probe_out114_UNCONNECTED;
wire [0:0]NLW_inst_probe_out115_UNCONNECTED;
wire [0:0]NLW_inst_probe_out116_UNCONNECTED;
wire [0:0]NLW_inst_probe_out117_UNCONNECTED;
wire [0:0]NLW_inst_probe_out118_UNCONNECTED;
wire [0:0]NLW_inst_probe_out119_UNCONNECTED;
wire [0:0]NLW_inst_probe_out12_UNCONNECTED;
wire [0:0]NLW_inst_probe_out120_UNCONNECTED;
wire [0:0]NLW_inst_probe_out121_UNCONNECTED;
wire [0:0]NLW_inst_probe_out122_UNCONNECTED;
wire [0:0]NLW_inst_probe_out123_UNCONNECTED;
wire [0:0]NLW_inst_probe_out124_UNCONNECTED;
wire [0:0]NLW_inst_probe_out125_UNCONNECTED;
wire [0:0]NLW_inst_probe_out126_UNCONNECTED;
wire [0:0]NLW_inst_probe_out127_UNCONNECTED;
wire [0:0]NLW_inst_probe_out128_UNCONNECTED;
wire [0:0]NLW_inst_probe_out129_UNCONNECTED;
wire [0:0]NLW_inst_probe_out13_UNCONNECTED;
wire [0:0]NLW_inst_probe_out130_UNCONNECTED;
wire [0:0]NLW_inst_probe_out131_UNCONNECTED;
wire [0:0]NLW_inst_probe_out132_UNCONNECTED;
wire [0:0]NLW_inst_probe_out133_UNCONNECTED;
wire [0:0]NLW_inst_probe_out134_UNCONNECTED;
wire [0:0]NLW_inst_probe_out135_UNCONNECTED;
wire [0:0]NLW_inst_probe_out136_UNCONNECTED;
wire [0:0]NLW_inst_probe_out137_UNCONNECTED;
wire [0:0]NLW_inst_probe_out138_UNCONNECTED;
wire [0:0]NLW_inst_probe_out139_UNCONNECTED;
wire [0:0]NLW_inst_probe_out14_UNCONNECTED;
wire [0:0]NLW_inst_probe_out140_UNCONNECTED;
wire [0:0]NLW_inst_probe_out141_UNCONNECTED;
wire [0:0]NLW_inst_probe_out142_UNCONNECTED;
wire [0:0]NLW_inst_probe_out143_UNCONNECTED;
wire [0:0]NLW_inst_probe_out144_UNCONNECTED;
wire [0:0]NLW_inst_probe_out145_UNCONNECTED;
wire [0:0]NLW_inst_probe_out146_UNCONNECTED;
wire [0:0]NLW_inst_probe_out147_UNCONNECTED;
wire [0:0]NLW_inst_probe_out148_UNCONNECTED;
wire [0:0]NLW_inst_probe_out149_UNCONNECTED;
wire [0:0]NLW_inst_probe_out15_UNCONNECTED;
wire [0:0]NLW_inst_probe_out150_UNCONNECTED;
wire [0:0]NLW_inst_probe_out151_UNCONNECTED;
wire [0:0]NLW_inst_probe_out152_UNCONNECTED;
wire [0:0]NLW_inst_probe_out153_UNCONNECTED;
wire [0:0]NLW_inst_probe_out154_UNCONNECTED;
wire [0:0]NLW_inst_probe_out155_UNCONNECTED;
wire [0:0]NLW_inst_probe_out156_UNCONNECTED;
wire [0:0]NLW_inst_probe_out157_UNCONNECTED;
wire [0:0]NLW_inst_probe_out158_UNCONNECTED;
wire [0:0]NLW_inst_probe_out159_UNCONNECTED;
wire [0:0]NLW_inst_probe_out16_UNCONNECTED;
wire [0:0]NLW_inst_probe_out160_UNCONNECTED;
wire [0:0]NLW_inst_probe_out161_UNCONNECTED;
wire [0:0]NLW_inst_probe_out162_UNCONNECTED;
wire [0:0]NLW_inst_probe_out163_UNCONNECTED;
wire [0:0]NLW_inst_probe_out164_UNCONNECTED;
wire [0:0]NLW_inst_probe_out165_UNCONNECTED;
wire [0:0]NLW_inst_probe_out166_UNCONNECTED;
wire [0:0]NLW_inst_probe_out167_UNCONNECTED;
wire [0:0]NLW_inst_probe_out168_UNCONNECTED;
wire [0:0]NLW_inst_probe_out169_UNCONNECTED;
wire [0:0]NLW_inst_probe_out17_UNCONNECTED;
wire [0:0]NLW_inst_probe_out170_UNCONNECTED;
wire [0:0]NLW_inst_probe_out171_UNCONNECTED;
wire [0:0]NLW_inst_probe_out172_UNCONNECTED;
wire [0:0]NLW_inst_probe_out173_UNCONNECTED;
wire [0:0]NLW_inst_probe_out174_UNCONNECTED;
wire [0:0]NLW_inst_probe_out175_UNCONNECTED;
wire [0:0]NLW_inst_probe_out176_UNCONNECTED;
wire [0:0]NLW_inst_probe_out177_UNCONNECTED;
wire [0:0]NLW_inst_probe_out178_UNCONNECTED;
wire [0:0]NLW_inst_probe_out179_UNCONNECTED;
wire [0:0]NLW_inst_probe_out18_UNCONNECTED;
wire [0:0]NLW_inst_probe_out180_UNCONNECTED;
wire [0:0]NLW_inst_probe_out181_UNCONNECTED;
wire [0:0]NLW_inst_probe_out182_UNCONNECTED;
wire [0:0]NLW_inst_probe_out183_UNCONNECTED;
wire [0:0]NLW_inst_probe_out184_UNCONNECTED;
wire [0:0]NLW_inst_probe_out185_UNCONNECTED;
wire [0:0]NLW_inst_probe_out186_UNCONNECTED;
wire [0:0]NLW_inst_probe_out187_UNCONNECTED;
wire [0:0]NLW_inst_probe_out188_UNCONNECTED;
wire [0:0]NLW_inst_probe_out189_UNCONNECTED;
wire [0:0]NLW_inst_probe_out19_UNCONNECTED;
wire [0:0]NLW_inst_probe_out190_UNCONNECTED;
wire [0:0]NLW_inst_probe_out191_UNCONNECTED;
wire [0:0]NLW_inst_probe_out192_UNCONNECTED;
wire [0:0]NLW_inst_probe_out193_UNCONNECTED;
wire [0:0]NLW_inst_probe_out194_UNCONNECTED;
wire [0:0]NLW_inst_probe_out195_UNCONNECTED;
wire [0:0]NLW_inst_probe_out196_UNCONNECTED;
wire [0:0]NLW_inst_probe_out197_UNCONNECTED;
wire [0:0]NLW_inst_probe_out198_UNCONNECTED;
wire [0:0]NLW_inst_probe_out199_UNCONNECTED;
wire [0:0]NLW_inst_probe_out2_UNCONNECTED;
wire [0:0]NLW_inst_probe_out20_UNCONNECTED;
wire [0:0]NLW_inst_probe_out200_UNCONNECTED;
wire [0:0]NLW_inst_probe_out201_UNCONNECTED;
wire [0:0]NLW_inst_probe_out202_UNCONNECTED;
wire [0:0]NLW_inst_probe_out203_UNCONNECTED;
wire [0:0]NLW_inst_probe_out204_UNCONNECTED;
wire [0:0]NLW_inst_probe_out205_UNCONNECTED;
wire [0:0]NLW_inst_probe_out206_UNCONNECTED;
wire [0:0]NLW_inst_probe_out207_UNCONNECTED;
wire [0:0]NLW_inst_probe_out208_UNCONNECTED;
wire [0:0]NLW_inst_probe_out209_UNCONNECTED;
wire [0:0]NLW_inst_probe_out21_UNCONNECTED;
wire [0:0]NLW_inst_probe_out210_UNCONNECTED;
wire [0:0]NLW_inst_probe_out211_UNCONNECTED;
wire [0:0]NLW_inst_probe_out212_UNCONNECTED;
wire [0:0]NLW_inst_probe_out213_UNCONNECTED;
wire [0:0]NLW_inst_probe_out214_UNCONNECTED;
wire [0:0]NLW_inst_probe_out215_UNCONNECTED;
wire [0:0]NLW_inst_probe_out216_UNCONNECTED;
wire [0:0]NLW_inst_probe_out217_UNCONNECTED;
wire [0:0]NLW_inst_probe_out218_UNCONNECTED;
wire [0:0]NLW_inst_probe_out219_UNCONNECTED;
wire [0:0]NLW_inst_probe_out22_UNCONNECTED;
wire [0:0]NLW_inst_probe_out220_UNCONNECTED;
wire [0:0]NLW_inst_probe_out221_UNCONNECTED;
wire [0:0]NLW_inst_probe_out222_UNCONNECTED;
wire [0:0]NLW_inst_probe_out223_UNCONNECTED;
wire [0:0]NLW_inst_probe_out224_UNCONNECTED;
wire [0:0]NLW_inst_probe_out225_UNCONNECTED;
wire [0:0]NLW_inst_probe_out226_UNCONNECTED;
wire [0:0]NLW_inst_probe_out227_UNCONNECTED;
wire [0:0]NLW_inst_probe_out228_UNCONNECTED;
wire [0:0]NLW_inst_probe_out229_UNCONNECTED;
wire [0:0]NLW_inst_probe_out23_UNCONNECTED;
wire [0:0]NLW_inst_probe_out230_UNCONNECTED;
wire [0:0]NLW_inst_probe_out231_UNCONNECTED;
wire [0:0]NLW_inst_probe_out232_UNCONNECTED;
wire [0:0]NLW_inst_probe_out233_UNCONNECTED;
wire [0:0]NLW_inst_probe_out234_UNCONNECTED;
wire [0:0]NLW_inst_probe_out235_UNCONNECTED;
wire [0:0]NLW_inst_probe_out236_UNCONNECTED;
wire [0:0]NLW_inst_probe_out237_UNCONNECTED;
wire [0:0]NLW_inst_probe_out238_UNCONNECTED;
wire [0:0]NLW_inst_probe_out239_UNCONNECTED;
wire [0:0]NLW_inst_probe_out24_UNCONNECTED;
wire [0:0]NLW_inst_probe_out240_UNCONNECTED;
wire [0:0]NLW_inst_probe_out241_UNCONNECTED;
wire [0:0]NLW_inst_probe_out242_UNCONNECTED;
wire [0:0]NLW_inst_probe_out243_UNCONNECTED;
wire [0:0]NLW_inst_probe_out244_UNCONNECTED;
wire [0:0]NLW_inst_probe_out245_UNCONNECTED;
wire [0:0]NLW_inst_probe_out246_UNCONNECTED;
wire [0:0]NLW_inst_probe_out247_UNCONNECTED;
wire [0:0]NLW_inst_probe_out248_UNCONNECTED;
wire [0:0]NLW_inst_probe_out249_UNCONNECTED;
wire [0:0]NLW_inst_probe_out25_UNCONNECTED;
wire [0:0]NLW_inst_probe_out250_UNCONNECTED;
wire [0:0]NLW_inst_probe_out251_UNCONNECTED;
wire [0:0]NLW_inst_probe_out252_UNCONNECTED;
wire [0:0]NLW_inst_probe_out253_UNCONNECTED;
wire [0:0]NLW_inst_probe_out254_UNCONNECTED;
wire [0:0]NLW_inst_probe_out255_UNCONNECTED;
wire [0:0]NLW_inst_probe_out26_UNCONNECTED;
wire [0:0]NLW_inst_probe_out27_UNCONNECTED;
wire [0:0]NLW_inst_probe_out28_UNCONNECTED;
wire [0:0]NLW_inst_probe_out29_UNCONNECTED;
wire [0:0]NLW_inst_probe_out3_UNCONNECTED;
wire [0:0]NLW_inst_probe_out30_UNCONNECTED;
wire [0:0]NLW_inst_probe_out31_UNCONNECTED;
wire [0:0]NLW_inst_probe_out32_UNCONNECTED;
wire [0:0]NLW_inst_probe_out33_UNCONNECTED;
wire [0:0]NLW_inst_probe_out34_UNCONNECTED;
wire [0:0]NLW_inst_probe_out35_UNCONNECTED;
wire [0:0]NLW_inst_probe_out36_UNCONNECTED;
wire [0:0]NLW_inst_probe_out37_UNCONNECTED;
wire [0:0]NLW_inst_probe_out38_UNCONNECTED;
wire [0:0]NLW_inst_probe_out39_UNCONNECTED;
wire [0:0]NLW_inst_probe_out4_UNCONNECTED;
wire [0:0]NLW_inst_probe_out40_UNCONNECTED;
wire [0:0]NLW_inst_probe_out41_UNCONNECTED;
wire [0:0]NLW_inst_probe_out42_UNCONNECTED;
wire [0:0]NLW_inst_probe_out43_UNCONNECTED;
wire [0:0]NLW_inst_probe_out44_UNCONNECTED;
wire [0:0]NLW_inst_probe_out45_UNCONNECTED;
wire [0:0]NLW_inst_probe_out46_UNCONNECTED;
wire [0:0]NLW_inst_probe_out47_UNCONNECTED;
wire [0:0]NLW_inst_probe_out48_UNCONNECTED;
wire [0:0]NLW_inst_probe_out49_UNCONNECTED;
wire [0:0]NLW_inst_probe_out5_UNCONNECTED;
wire [0:0]NLW_inst_probe_out50_UNCONNECTED;
wire [0:0]NLW_inst_probe_out51_UNCONNECTED;
wire [0:0]NLW_inst_probe_out52_UNCONNECTED;
wire [0:0]NLW_inst_probe_out53_UNCONNECTED;
wire [0:0]NLW_inst_probe_out54_UNCONNECTED;
wire [0:0]NLW_inst_probe_out55_UNCONNECTED;
wire [0:0]NLW_inst_probe_out56_UNCONNECTED;
wire [0:0]NLW_inst_probe_out57_UNCONNECTED;
wire [0:0]NLW_inst_probe_out58_UNCONNECTED;
wire [0:0]NLW_inst_probe_out59_UNCONNECTED;
wire [0:0]NLW_inst_probe_out6_UNCONNECTED;
wire [0:0]NLW_inst_probe_out60_UNCONNECTED;
wire [0:0]NLW_inst_probe_out61_UNCONNECTED;
wire [0:0]NLW_inst_probe_out62_UNCONNECTED;
wire [0:0]NLW_inst_probe_out63_UNCONNECTED;
wire [0:0]NLW_inst_probe_out64_UNCONNECTED;
wire [0:0]NLW_inst_probe_out65_UNCONNECTED;
wire [0:0]NLW_inst_probe_out66_UNCONNECTED;
wire [0:0]NLW_inst_probe_out67_UNCONNECTED;
wire [0:0]NLW_inst_probe_out68_UNCONNECTED;
wire [0:0]NLW_inst_probe_out69_UNCONNECTED;
wire [0:0]NLW_inst_probe_out7_UNCONNECTED;
wire [0:0]NLW_inst_probe_out70_UNCONNECTED;
wire [0:0]NLW_inst_probe_out71_UNCONNECTED;
wire [0:0]NLW_inst_probe_out72_UNCONNECTED;
wire [0:0]NLW_inst_probe_out73_UNCONNECTED;
wire [0:0]NLW_inst_probe_out74_UNCONNECTED;
wire [0:0]NLW_inst_probe_out75_UNCONNECTED;
wire [0:0]NLW_inst_probe_out76_UNCONNECTED;
wire [0:0]NLW_inst_probe_out77_UNCONNECTED;
wire [0:0]NLW_inst_probe_out78_UNCONNECTED;
wire [0:0]NLW_inst_probe_out79_UNCONNECTED;
wire [0:0]NLW_inst_probe_out8_UNCONNECTED;
wire [0:0]NLW_inst_probe_out80_UNCONNECTED;
wire [0:0]NLW_inst_probe_out81_UNCONNECTED;
wire [0:0]NLW_inst_probe_out82_UNCONNECTED;
wire [0:0]NLW_inst_probe_out83_UNCONNECTED;
wire [0:0]NLW_inst_probe_out84_UNCONNECTED;
wire [0:0]NLW_inst_probe_out85_UNCONNECTED;
wire [0:0]NLW_inst_probe_out86_UNCONNECTED;
wire [0:0]NLW_inst_probe_out87_UNCONNECTED;
wire [0:0]NLW_inst_probe_out88_UNCONNECTED;
wire [0:0]NLW_inst_probe_out89_UNCONNECTED;
wire [0:0]NLW_inst_probe_out9_UNCONNECTED;
wire [0:0]NLW_inst_probe_out90_UNCONNECTED;
wire [0:0]NLW_inst_probe_out91_UNCONNECTED;
wire [0:0]NLW_inst_probe_out92_UNCONNECTED;
wire [0:0]NLW_inst_probe_out93_UNCONNECTED;
wire [0:0]NLW_inst_probe_out94_UNCONNECTED;
wire [0:0]NLW_inst_probe_out95_UNCONNECTED;
wire [0:0]NLW_inst_probe_out96_UNCONNECTED;
wire [0:0]NLW_inst_probe_out97_UNCONNECTED;
wire [0:0]NLW_inst_probe_out98_UNCONNECTED;
wire [0:0]NLW_inst_probe_out99_UNCONNECTED;
wire [16:0]NLW_inst_sl_oport0_UNCONNECTED;
(* C_BUILD_REVISION = "0" *)
(* C_BUS_ADDR_WIDTH = "17" *)
(* C_BUS_DATA_WIDTH = "16" *)
(* C_CORE_INFO1 = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
(* C_CORE_INFO2 = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
(* C_CORE_MAJOR_VER = "2" *)
(* C_CORE_MINOR_ALPHA_VER = "97" *)
(* C_CORE_MINOR_VER = "0" *)
(* C_CORE_TYPE = "2" *)
(* C_CSE_DRV_VER = "1" *)
(* C_EN_PROBE_IN_ACTIVITY = "1" *)
(* C_EN_SYNCHRONIZATION = "1" *)
(* C_MAJOR_VERSION = "2013" *)
(* C_MAX_NUM_PROBE = "256" *)
(* C_MAX_WIDTH_PER_PROBE = "256" *)
(* C_MINOR_VERSION = "1" *)
(* C_NEXT_SLAVE = "0" *)
(* C_NUM_PROBE_IN = "4" *)
(* C_NUM_PROBE_OUT = "0" *)
(* C_PIPE_IFACE = "0" *)
(* C_PROBE_IN0_WIDTH = "1" *)
(* C_PROBE_IN100_WIDTH = "1" *)
(* C_PROBE_IN101_WIDTH = "1" *)
(* C_PROBE_IN102_WIDTH = "1" *)
(* C_PROBE_IN103_WIDTH = "1" *)
(* C_PROBE_IN104_WIDTH = "1" *)
(* C_PROBE_IN105_WIDTH = "1" *)
(* C_PROBE_IN106_WIDTH = "1" *)
(* C_PROBE_IN107_WIDTH = "1" *)
(* C_PROBE_IN108_WIDTH = "1" *)
(* C_PROBE_IN109_WIDTH = "1" *)
(* C_PROBE_IN10_WIDTH = "1" *)
(* C_PROBE_IN110_WIDTH = "1" *)
(* C_PROBE_IN111_WIDTH = "1" *)
(* C_PROBE_IN112_WIDTH = "1" *)
(* C_PROBE_IN113_WIDTH = "1" *)
(* C_PROBE_IN114_WIDTH = "1" *)
(* C_PROBE_IN115_WIDTH = "1" *)
(* C_PROBE_IN116_WIDTH = "1" *)
(* C_PROBE_IN117_WIDTH = "1" *)
(* C_PROBE_IN118_WIDTH = "1" *)
(* C_PROBE_IN119_WIDTH = "1" *)
(* C_PROBE_IN11_WIDTH = "1" *)
(* C_PROBE_IN120_WIDTH = "1" *)
(* C_PROBE_IN121_WIDTH = "1" *)
(* C_PROBE_IN122_WIDTH = "1" *)
(* C_PROBE_IN123_WIDTH = "1" *)
(* C_PROBE_IN124_WIDTH = "1" *)
(* C_PROBE_IN125_WIDTH = "1" *)
(* C_PROBE_IN126_WIDTH = "1" *)
(* C_PROBE_IN127_WIDTH = "1" *)
(* C_PROBE_IN128_WIDTH = "1" *)
(* C_PROBE_IN129_WIDTH = "1" *)
(* C_PROBE_IN12_WIDTH = "1" *)
(* C_PROBE_IN130_WIDTH = "1" *)
(* C_PROBE_IN131_WIDTH = "1" *)
(* C_PROBE_IN132_WIDTH = "1" *)
(* C_PROBE_IN133_WIDTH = "1" *)
(* C_PROBE_IN134_WIDTH = "1" *)
(* C_PROBE_IN135_WIDTH = "1" *)
(* C_PROBE_IN136_WIDTH = "1" *)
(* C_PROBE_IN137_WIDTH = "1" *)
(* C_PROBE_IN138_WIDTH = "1" *)
(* C_PROBE_IN139_WIDTH = "1" *)
(* C_PROBE_IN13_WIDTH = "1" *)
(* C_PROBE_IN140_WIDTH = "1" *)
(* C_PROBE_IN141_WIDTH = "1" *)
(* C_PROBE_IN142_WIDTH = "1" *)
(* C_PROBE_IN143_WIDTH = "1" *)
(* C_PROBE_IN144_WIDTH = "1" *)
(* C_PROBE_IN145_WIDTH = "1" *)
(* C_PROBE_IN146_WIDTH = "1" *)
(* C_PROBE_IN147_WIDTH = "1" *)
(* C_PROBE_IN148_WIDTH = "1" *)
(* C_PROBE_IN149_WIDTH = "1" *)
(* C_PROBE_IN14_WIDTH = "1" *)
(* C_PROBE_IN150_WIDTH = "1" *)
(* C_PROBE_IN151_WIDTH = "1" *)
(* C_PROBE_IN152_WIDTH = "1" *)
(* C_PROBE_IN153_WIDTH = "1" *)
(* C_PROBE_IN154_WIDTH = "1" *)
(* C_PROBE_IN155_WIDTH = "1" *)
(* C_PROBE_IN156_WIDTH = "1" *)
(* C_PROBE_IN157_WIDTH = "1" *)
(* C_PROBE_IN158_WIDTH = "1" *)
(* C_PROBE_IN159_WIDTH = "1" *)
(* C_PROBE_IN15_WIDTH = "1" *)
(* C_PROBE_IN160_WIDTH = "1" *)
(* C_PROBE_IN161_WIDTH = "1" *)
(* C_PROBE_IN162_WIDTH = "1" *)
(* C_PROBE_IN163_WIDTH = "1" *)
(* C_PROBE_IN164_WIDTH = "1" *)
(* C_PROBE_IN165_WIDTH = "1" *)
(* C_PROBE_IN166_WIDTH = "1" *)
(* C_PROBE_IN167_WIDTH = "1" *)
(* C_PROBE_IN168_WIDTH = "1" *)
(* C_PROBE_IN169_WIDTH = "1" *)
(* C_PROBE_IN16_WIDTH = "1" *)
(* C_PROBE_IN170_WIDTH = "1" *)
(* C_PROBE_IN171_WIDTH = "1" *)
(* C_PROBE_IN172_WIDTH = "1" *)
(* C_PROBE_IN173_WIDTH = "1" *)
(* C_PROBE_IN174_WIDTH = "1" *)
(* C_PROBE_IN175_WIDTH = "1" *)
(* C_PROBE_IN176_WIDTH = "1" *)
(* C_PROBE_IN177_WIDTH = "1" *)
(* C_PROBE_IN178_WIDTH = "1" *)
(* C_PROBE_IN179_WIDTH = "1" *)
(* C_PROBE_IN17_WIDTH = "1" *)
(* C_PROBE_IN180_WIDTH = "1" *)
(* C_PROBE_IN181_WIDTH = "1" *)
(* C_PROBE_IN182_WIDTH = "1" *)
(* C_PROBE_IN183_WIDTH = "1" *)
(* C_PROBE_IN184_WIDTH = "1" *)
(* C_PROBE_IN185_WIDTH = "1" *)
(* C_PROBE_IN186_WIDTH = "1" *)
(* C_PROBE_IN187_WIDTH = "1" *)
(* C_PROBE_IN188_WIDTH = "1" *)
(* C_PROBE_IN189_WIDTH = "1" *)
(* C_PROBE_IN18_WIDTH = "1" *)
(* C_PROBE_IN190_WIDTH = "1" *)
(* C_PROBE_IN191_WIDTH = "1" *)
(* C_PROBE_IN192_WIDTH = "1" *)
(* C_PROBE_IN193_WIDTH = "1" *)
(* C_PROBE_IN194_WIDTH = "1" *)
(* C_PROBE_IN195_WIDTH = "1" *)
(* C_PROBE_IN196_WIDTH = "1" *)
(* C_PROBE_IN197_WIDTH = "1" *)
(* C_PROBE_IN198_WIDTH = "1" *)
(* C_PROBE_IN199_WIDTH = "1" *)
(* C_PROBE_IN19_WIDTH = "1" *)
(* C_PROBE_IN1_WIDTH = "1" *)
(* C_PROBE_IN200_WIDTH = "1" *)
(* C_PROBE_IN201_WIDTH = "1" *)
(* C_PROBE_IN202_WIDTH = "1" *)
(* C_PROBE_IN203_WIDTH = "1" *)
(* C_PROBE_IN204_WIDTH = "1" *)
(* C_PROBE_IN205_WIDTH = "1" *)
(* C_PROBE_IN206_WIDTH = "1" *)
(* C_PROBE_IN207_WIDTH = "1" *)
(* C_PROBE_IN208_WIDTH = "1" *)
(* C_PROBE_IN209_WIDTH = "1" *)
(* C_PROBE_IN20_WIDTH = "1" *)
(* C_PROBE_IN210_WIDTH = "1" *)
(* C_PROBE_IN211_WIDTH = "1" *)
(* C_PROBE_IN212_WIDTH = "1" *)
(* C_PROBE_IN213_WIDTH = "1" *)
(* C_PROBE_IN214_WIDTH = "1" *)
(* C_PROBE_IN215_WIDTH = "1" *)
(* C_PROBE_IN216_WIDTH = "1" *)
(* C_PROBE_IN217_WIDTH = "1" *)
(* C_PROBE_IN218_WIDTH = "1" *)
(* C_PROBE_IN219_WIDTH = "1" *)
(* C_PROBE_IN21_WIDTH = "1" *)
(* C_PROBE_IN220_WIDTH = "1" *)
(* C_PROBE_IN221_WIDTH = "1" *)
(* C_PROBE_IN222_WIDTH = "1" *)
(* C_PROBE_IN223_WIDTH = "1" *)
(* C_PROBE_IN224_WIDTH = "1" *)
(* C_PROBE_IN225_WIDTH = "1" *)
(* C_PROBE_IN226_WIDTH = "1" *)
(* C_PROBE_IN227_WIDTH = "1" *)
(* C_PROBE_IN228_WIDTH = "1" *)
(* C_PROBE_IN229_WIDTH = "1" *)
(* C_PROBE_IN22_WIDTH = "1" *)
(* C_PROBE_IN230_WIDTH = "1" *)
(* C_PROBE_IN231_WIDTH = "1" *)
(* C_PROBE_IN232_WIDTH = "1" *)
(* C_PROBE_IN233_WIDTH = "1" *)
(* C_PROBE_IN234_WIDTH = "1" *)
(* C_PROBE_IN235_WIDTH = "1" *)
(* C_PROBE_IN236_WIDTH = "1" *)
(* C_PROBE_IN237_WIDTH = "1" *)
(* C_PROBE_IN238_WIDTH = "1" *)
(* C_PROBE_IN239_WIDTH = "1" *)
(* C_PROBE_IN23_WIDTH = "1" *)
(* C_PROBE_IN240_WIDTH = "1" *)
(* C_PROBE_IN241_WIDTH = "1" *)
(* C_PROBE_IN242_WIDTH = "1" *)
(* C_PROBE_IN243_WIDTH = "1" *)
(* C_PROBE_IN244_WIDTH = "1" *)
(* C_PROBE_IN245_WIDTH = "1" *)
(* C_PROBE_IN246_WIDTH = "1" *)
(* C_PROBE_IN247_WIDTH = "1" *)
(* C_PROBE_IN248_WIDTH = "1" *)
(* C_PROBE_IN249_WIDTH = "1" *)
(* C_PROBE_IN24_WIDTH = "1" *)
(* C_PROBE_IN250_WIDTH = "1" *)
(* C_PROBE_IN251_WIDTH = "1" *)
(* C_PROBE_IN252_WIDTH = "1" *)
(* C_PROBE_IN253_WIDTH = "1" *)
(* C_PROBE_IN254_WIDTH = "1" *)
(* C_PROBE_IN255_WIDTH = "1" *)
(* C_PROBE_IN25_WIDTH = "1" *)
(* C_PROBE_IN26_WIDTH = "1" *)
(* C_PROBE_IN27_WIDTH = "1" *)
(* C_PROBE_IN28_WIDTH = "1" *)
(* C_PROBE_IN29_WIDTH = "1" *)
(* C_PROBE_IN2_WIDTH = "1" *)
(* C_PROBE_IN30_WIDTH = "1" *)
(* C_PROBE_IN31_WIDTH = "1" *)
(* C_PROBE_IN32_WIDTH = "1" *)
(* C_PROBE_IN33_WIDTH = "1" *)
(* C_PROBE_IN34_WIDTH = "1" *)
(* C_PROBE_IN35_WIDTH = "1" *)
(* C_PROBE_IN36_WIDTH = "1" *)
(* C_PROBE_IN37_WIDTH = "1" *)
(* C_PROBE_IN38_WIDTH = "1" *)
(* C_PROBE_IN39_WIDTH = "1" *)
(* C_PROBE_IN3_WIDTH = "1" *)
(* C_PROBE_IN40_WIDTH = "1" *)
(* C_PROBE_IN41_WIDTH = "1" *)
(* C_PROBE_IN42_WIDTH = "1" *)
(* C_PROBE_IN43_WIDTH = "1" *)
(* C_PROBE_IN44_WIDTH = "1" *)
(* C_PROBE_IN45_WIDTH = "1" *)
(* C_PROBE_IN46_WIDTH = "1" *)
(* C_PROBE_IN47_WIDTH = "1" *)
(* C_PROBE_IN48_WIDTH = "1" *)
(* C_PROBE_IN49_WIDTH = "1" *)
(* C_PROBE_IN4_WIDTH = "1" *)
(* C_PROBE_IN50_WIDTH = "1" *)
(* C_PROBE_IN51_WIDTH = "1" *)
(* C_PROBE_IN52_WIDTH = "1" *)
(* C_PROBE_IN53_WIDTH = "1" *)
(* C_PROBE_IN54_WIDTH = "1" *)
(* C_PROBE_IN55_WIDTH = "1" *)
(* C_PROBE_IN56_WIDTH = "1" *)
(* C_PROBE_IN57_WIDTH = "1" *)
(* C_PROBE_IN58_WIDTH = "1" *)
(* C_PROBE_IN59_WIDTH = "1" *)
(* C_PROBE_IN5_WIDTH = "1" *)
(* C_PROBE_IN60_WIDTH = "1" *)
(* C_PROBE_IN61_WIDTH = "1" *)
(* C_PROBE_IN62_WIDTH = "1" *)
(* C_PROBE_IN63_WIDTH = "1" *)
(* C_PROBE_IN64_WIDTH = "1" *)
(* C_PROBE_IN65_WIDTH = "1" *)
(* C_PROBE_IN66_WIDTH = "1" *)
(* C_PROBE_IN67_WIDTH = "1" *)
(* C_PROBE_IN68_WIDTH = "1" *)
(* C_PROBE_IN69_WIDTH = "1" *)
(* C_PROBE_IN6_WIDTH = "1" *)
(* C_PROBE_IN70_WIDTH = "1" *)
(* C_PROBE_IN71_WIDTH = "1" *)
(* C_PROBE_IN72_WIDTH = "1" *)
(* C_PROBE_IN73_WIDTH = "1" *)
(* C_PROBE_IN74_WIDTH = "1" *)
(* C_PROBE_IN75_WIDTH = "1" *)
(* C_PROBE_IN76_WIDTH = "1" *)
(* C_PROBE_IN77_WIDTH = "1" *)
(* C_PROBE_IN78_WIDTH = "1" *)
(* C_PROBE_IN79_WIDTH = "1" *)
(* C_PROBE_IN7_WIDTH = "1" *)
(* C_PROBE_IN80_WIDTH = "1" *)
(* C_PROBE_IN81_WIDTH = "1" *)
(* C_PROBE_IN82_WIDTH = "1" *)
(* C_PROBE_IN83_WIDTH = "1" *)
(* C_PROBE_IN84_WIDTH = "1" *)
(* C_PROBE_IN85_WIDTH = "1" *)
(* C_PROBE_IN86_WIDTH = "1" *)
(* C_PROBE_IN87_WIDTH = "1" *)
(* C_PROBE_IN88_WIDTH = "1" *)
(* C_PROBE_IN89_WIDTH = "1" *)
(* C_PROBE_IN8_WIDTH = "1" *)
(* C_PROBE_IN90_WIDTH = "1" *)
(* C_PROBE_IN91_WIDTH = "1" *)
(* C_PROBE_IN92_WIDTH = "1" *)
(* C_PROBE_IN93_WIDTH = "1" *)
(* C_PROBE_IN94_WIDTH = "1" *)
(* C_PROBE_IN95_WIDTH = "1" *)
(* C_PROBE_IN96_WIDTH = "1" *)
(* C_PROBE_IN97_WIDTH = "1" *)
(* C_PROBE_IN98_WIDTH = "1" *)
(* C_PROBE_IN99_WIDTH = "1" *)
(* C_PROBE_IN9_WIDTH = "1" *)
(* C_PROBE_OUT0_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT0_WIDTH = "1" *)
(* C_PROBE_OUT100_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT100_WIDTH = "1" *)
(* C_PROBE_OUT101_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT101_WIDTH = "1" *)
(* C_PROBE_OUT102_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT102_WIDTH = "1" *)
(* C_PROBE_OUT103_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT103_WIDTH = "1" *)
(* C_PROBE_OUT104_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT104_WIDTH = "1" *)
(* C_PROBE_OUT105_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT105_WIDTH = "1" *)
(* C_PROBE_OUT106_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT106_WIDTH = "1" *)
(* C_PROBE_OUT107_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT107_WIDTH = "1" *)
(* C_PROBE_OUT108_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT108_WIDTH = "1" *)
(* C_PROBE_OUT109_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT109_WIDTH = "1" *)
(* C_PROBE_OUT10_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT10_WIDTH = "1" *)
(* C_PROBE_OUT110_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT110_WIDTH = "1" *)
(* C_PROBE_OUT111_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT111_WIDTH = "1" *)
(* C_PROBE_OUT112_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT112_WIDTH = "1" *)
(* C_PROBE_OUT113_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT113_WIDTH = "1" *)
(* C_PROBE_OUT114_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT114_WIDTH = "1" *)
(* C_PROBE_OUT115_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT115_WIDTH = "1" *)
(* C_PROBE_OUT116_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT116_WIDTH = "1" *)
(* C_PROBE_OUT117_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT117_WIDTH = "1" *)
(* C_PROBE_OUT118_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT118_WIDTH = "1" *)
(* C_PROBE_OUT119_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT119_WIDTH = "1" *)
(* C_PROBE_OUT11_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT11_WIDTH = "1" *)
(* C_PROBE_OUT120_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT120_WIDTH = "1" *)
(* C_PROBE_OUT121_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT121_WIDTH = "1" *)
(* C_PROBE_OUT122_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT122_WIDTH = "1" *)
(* C_PROBE_OUT123_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT123_WIDTH = "1" *)
(* C_PROBE_OUT124_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT124_WIDTH = "1" *)
(* C_PROBE_OUT125_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT125_WIDTH = "1" *)
(* C_PROBE_OUT126_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT126_WIDTH = "1" *)
(* C_PROBE_OUT127_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT127_WIDTH = "1" *)
(* C_PROBE_OUT128_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT128_WIDTH = "1" *)
(* C_PROBE_OUT129_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT129_WIDTH = "1" *)
(* C_PROBE_OUT12_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT12_WIDTH = "1" *)
(* C_PROBE_OUT130_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT130_WIDTH = "1" *)
(* C_PROBE_OUT131_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT131_WIDTH = "1" *)
(* C_PROBE_OUT132_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT132_WIDTH = "1" *)
(* C_PROBE_OUT133_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT133_WIDTH = "1" *)
(* C_PROBE_OUT134_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT134_WIDTH = "1" *)
(* C_PROBE_OUT135_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT135_WIDTH = "1" *)
(* C_PROBE_OUT136_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT136_WIDTH = "1" *)
(* C_PROBE_OUT137_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT137_WIDTH = "1" *)
(* C_PROBE_OUT138_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT138_WIDTH = "1" *)
(* C_PROBE_OUT139_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT139_WIDTH = "1" *)
(* C_PROBE_OUT13_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT13_WIDTH = "1" *)
(* C_PROBE_OUT140_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT140_WIDTH = "1" *)
(* C_PROBE_OUT141_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT141_WIDTH = "1" *)
(* C_PROBE_OUT142_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT142_WIDTH = "1" *)
(* C_PROBE_OUT143_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT143_WIDTH = "1" *)
(* C_PROBE_OUT144_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT144_WIDTH = "1" *)
(* C_PROBE_OUT145_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT145_WIDTH = "1" *)
(* C_PROBE_OUT146_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT146_WIDTH = "1" *)
(* C_PROBE_OUT147_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT147_WIDTH = "1" *)
(* C_PROBE_OUT148_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT148_WIDTH = "1" *)
(* C_PROBE_OUT149_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT149_WIDTH = "1" *)
(* C_PROBE_OUT14_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT14_WIDTH = "1" *)
(* C_PROBE_OUT150_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT150_WIDTH = "1" *)
(* C_PROBE_OUT151_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT151_WIDTH = "1" *)
(* C_PROBE_OUT152_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT152_WIDTH = "1" *)
(* C_PROBE_OUT153_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT153_WIDTH = "1" *)
(* C_PROBE_OUT154_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT154_WIDTH = "1" *)
(* C_PROBE_OUT155_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT155_WIDTH = "1" *)
(* C_PROBE_OUT156_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT156_WIDTH = "1" *)
(* C_PROBE_OUT157_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT157_WIDTH = "1" *)
(* C_PROBE_OUT158_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT158_WIDTH = "1" *)
(* C_PROBE_OUT159_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT159_WIDTH = "1" *)
(* C_PROBE_OUT15_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT15_WIDTH = "1" *)
(* C_PROBE_OUT160_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT160_WIDTH = "1" *)
(* C_PROBE_OUT161_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT161_WIDTH = "1" *)
(* C_PROBE_OUT162_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT162_WIDTH = "1" *)
(* C_PROBE_OUT163_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT163_WIDTH = "1" *)
(* C_PROBE_OUT164_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT164_WIDTH = "1" *)
(* C_PROBE_OUT165_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT165_WIDTH = "1" *)
(* C_PROBE_OUT166_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT166_WIDTH = "1" *)
(* C_PROBE_OUT167_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT167_WIDTH = "1" *)
(* C_PROBE_OUT168_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT168_WIDTH = "1" *)
(* C_PROBE_OUT169_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT169_WIDTH = "1" *)
(* C_PROBE_OUT16_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT16_WIDTH = "1" *)
(* C_PROBE_OUT170_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT170_WIDTH = "1" *)
(* C_PROBE_OUT171_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT171_WIDTH = "1" *)
(* C_PROBE_OUT172_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT172_WIDTH = "1" *)
(* C_PROBE_OUT173_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT173_WIDTH = "1" *)
(* C_PROBE_OUT174_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT174_WIDTH = "1" *)
(* C_PROBE_OUT175_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT175_WIDTH = "1" *)
(* C_PROBE_OUT176_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT176_WIDTH = "1" *)
(* C_PROBE_OUT177_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT177_WIDTH = "1" *)
(* C_PROBE_OUT178_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT178_WIDTH = "1" *)
(* C_PROBE_OUT179_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT179_WIDTH = "1" *)
(* C_PROBE_OUT17_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT17_WIDTH = "1" *)
(* C_PROBE_OUT180_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT180_WIDTH = "1" *)
(* C_PROBE_OUT181_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT181_WIDTH = "1" *)
(* C_PROBE_OUT182_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT182_WIDTH = "1" *)
(* C_PROBE_OUT183_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT183_WIDTH = "1" *)
(* C_PROBE_OUT184_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT184_WIDTH = "1" *)
(* C_PROBE_OUT185_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT185_WIDTH = "1" *)
(* C_PROBE_OUT186_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT186_WIDTH = "1" *)
(* C_PROBE_OUT187_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT187_WIDTH = "1" *)
(* C_PROBE_OUT188_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT188_WIDTH = "1" *)
(* C_PROBE_OUT189_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT189_WIDTH = "1" *)
(* C_PROBE_OUT18_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT18_WIDTH = "1" *)
(* C_PROBE_OUT190_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT190_WIDTH = "1" *)
(* C_PROBE_OUT191_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT191_WIDTH = "1" *)
(* C_PROBE_OUT192_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT192_WIDTH = "1" *)
(* C_PROBE_OUT193_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT193_WIDTH = "1" *)
(* C_PROBE_OUT194_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT194_WIDTH = "1" *)
(* C_PROBE_OUT195_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT195_WIDTH = "1" *)
(* C_PROBE_OUT196_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT196_WIDTH = "1" *)
(* C_PROBE_OUT197_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT197_WIDTH = "1" *)
(* C_PROBE_OUT198_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT198_WIDTH = "1" *)
(* C_PROBE_OUT199_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT199_WIDTH = "1" *)
(* C_PROBE_OUT19_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT19_WIDTH = "1" *)
(* C_PROBE_OUT1_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT1_WIDTH = "1" *)
(* C_PROBE_OUT200_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT200_WIDTH = "1" *)
(* C_PROBE_OUT201_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT201_WIDTH = "1" *)
(* C_PROBE_OUT202_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT202_WIDTH = "1" *)
(* C_PROBE_OUT203_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT203_WIDTH = "1" *)
(* C_PROBE_OUT204_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT204_WIDTH = "1" *)
(* C_PROBE_OUT205_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT205_WIDTH = "1" *)
(* C_PROBE_OUT206_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT206_WIDTH = "1" *)
(* C_PROBE_OUT207_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT207_WIDTH = "1" *)
(* C_PROBE_OUT208_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT208_WIDTH = "1" *)
(* C_PROBE_OUT209_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT209_WIDTH = "1" *)
(* C_PROBE_OUT20_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT20_WIDTH = "1" *)
(* C_PROBE_OUT210_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT210_WIDTH = "1" *)
(* C_PROBE_OUT211_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT211_WIDTH = "1" *)
(* C_PROBE_OUT212_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT212_WIDTH = "1" *)
(* C_PROBE_OUT213_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT213_WIDTH = "1" *)
(* C_PROBE_OUT214_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT214_WIDTH = "1" *)
(* C_PROBE_OUT215_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT215_WIDTH = "1" *)
(* C_PROBE_OUT216_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT216_WIDTH = "1" *)
(* C_PROBE_OUT217_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT217_WIDTH = "1" *)
(* C_PROBE_OUT218_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT218_WIDTH = "1" *)
(* C_PROBE_OUT219_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT219_WIDTH = "1" *)
(* C_PROBE_OUT21_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT21_WIDTH = "1" *)
(* C_PROBE_OUT220_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT220_WIDTH = "1" *)
(* C_PROBE_OUT221_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT221_WIDTH = "1" *)
(* C_PROBE_OUT222_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT222_WIDTH = "1" *)
(* C_PROBE_OUT223_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT223_WIDTH = "1" *)
(* C_PROBE_OUT224_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT224_WIDTH = "1" *)
(* C_PROBE_OUT225_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT225_WIDTH = "1" *)
(* C_PROBE_OUT226_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT226_WIDTH = "1" *)
(* C_PROBE_OUT227_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT227_WIDTH = "1" *)
(* C_PROBE_OUT228_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT228_WIDTH = "1" *)
(* C_PROBE_OUT229_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT229_WIDTH = "1" *)
(* C_PROBE_OUT22_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT22_WIDTH = "1" *)
(* C_PROBE_OUT230_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT230_WIDTH = "1" *)
(* C_PROBE_OUT231_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT231_WIDTH = "1" *)
(* C_PROBE_OUT232_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT232_WIDTH = "1" *)
(* C_PROBE_OUT233_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT233_WIDTH = "1" *)
(* C_PROBE_OUT234_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT234_WIDTH = "1" *)
(* C_PROBE_OUT235_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT235_WIDTH = "1" *)
(* C_PROBE_OUT236_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT236_WIDTH = "1" *)
(* C_PROBE_OUT237_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT237_WIDTH = "1" *)
(* C_PROBE_OUT238_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT238_WIDTH = "1" *)
(* C_PROBE_OUT239_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT239_WIDTH = "1" *)
(* C_PROBE_OUT23_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT23_WIDTH = "1" *)
(* C_PROBE_OUT240_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT240_WIDTH = "1" *)
(* C_PROBE_OUT241_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT241_WIDTH = "1" *)
(* C_PROBE_OUT242_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT242_WIDTH = "1" *)
(* C_PROBE_OUT243_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT243_WIDTH = "1" *)
(* C_PROBE_OUT244_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT244_WIDTH = "1" *)
(* C_PROBE_OUT245_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT245_WIDTH = "1" *)
(* C_PROBE_OUT246_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT246_WIDTH = "1" *)
(* C_PROBE_OUT247_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT247_WIDTH = "1" *)
(* C_PROBE_OUT248_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT248_WIDTH = "1" *)
(* C_PROBE_OUT249_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT249_WIDTH = "1" *)
(* C_PROBE_OUT24_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT24_WIDTH = "1" *)
(* C_PROBE_OUT250_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT250_WIDTH = "1" *)
(* C_PROBE_OUT251_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT251_WIDTH = "1" *)
(* C_PROBE_OUT252_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT252_WIDTH = "1" *)
(* C_PROBE_OUT253_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT253_WIDTH = "1" *)
(* C_PROBE_OUT254_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT254_WIDTH = "1" *)
(* C_PROBE_OUT255_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT255_WIDTH = "1" *)
(* C_PROBE_OUT25_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT25_WIDTH = "1" *)
(* C_PROBE_OUT26_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT26_WIDTH = "1" *)
(* C_PROBE_OUT27_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT27_WIDTH = "1" *)
(* C_PROBE_OUT28_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT28_WIDTH = "1" *)
(* C_PROBE_OUT29_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT29_WIDTH = "1" *)
(* C_PROBE_OUT2_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT2_WIDTH = "1" *)
(* C_PROBE_OUT30_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT30_WIDTH = "1" *)
(* C_PROBE_OUT31_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT31_WIDTH = "1" *)
(* C_PROBE_OUT32_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT32_WIDTH = "1" *)
(* C_PROBE_OUT33_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT33_WIDTH = "1" *)
(* C_PROBE_OUT34_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT34_WIDTH = "1" *)
(* C_PROBE_OUT35_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT35_WIDTH = "1" *)
(* C_PROBE_OUT36_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT36_WIDTH = "1" *)
(* C_PROBE_OUT37_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT37_WIDTH = "1" *)
(* C_PROBE_OUT38_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT38_WIDTH = "1" *)
(* C_PROBE_OUT39_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT39_WIDTH = "1" *)
(* C_PROBE_OUT3_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT3_WIDTH = "1" *)
(* C_PROBE_OUT40_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT40_WIDTH = "1" *)
(* C_PROBE_OUT41_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT41_WIDTH = "1" *)
(* C_PROBE_OUT42_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT42_WIDTH = "1" *)
(* C_PROBE_OUT43_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT43_WIDTH = "1" *)
(* C_PROBE_OUT44_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT44_WIDTH = "1" *)
(* C_PROBE_OUT45_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT45_WIDTH = "1" *)
(* C_PROBE_OUT46_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT46_WIDTH = "1" *)
(* C_PROBE_OUT47_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT47_WIDTH = "1" *)
(* C_PROBE_OUT48_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT48_WIDTH = "1" *)
(* C_PROBE_OUT49_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT49_WIDTH = "1" *)
(* C_PROBE_OUT4_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT4_WIDTH = "1" *)
(* C_PROBE_OUT50_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT50_WIDTH = "1" *)
(* C_PROBE_OUT51_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT51_WIDTH = "1" *)
(* C_PROBE_OUT52_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT52_WIDTH = "1" *)
(* C_PROBE_OUT53_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT53_WIDTH = "1" *)
(* C_PROBE_OUT54_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT54_WIDTH = "1" *)
(* C_PROBE_OUT55_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT55_WIDTH = "1" *)
(* C_PROBE_OUT56_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT56_WIDTH = "1" *)
(* C_PROBE_OUT57_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT57_WIDTH = "1" *)
(* C_PROBE_OUT58_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT58_WIDTH = "1" *)
(* C_PROBE_OUT59_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT59_WIDTH = "1" *)
(* C_PROBE_OUT5_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT5_WIDTH = "1" *)
(* C_PROBE_OUT60_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT60_WIDTH = "1" *)
(* C_PROBE_OUT61_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT61_WIDTH = "1" *)
(* C_PROBE_OUT62_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT62_WIDTH = "1" *)
(* C_PROBE_OUT63_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT63_WIDTH = "1" *)
(* C_PROBE_OUT64_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT64_WIDTH = "1" *)
(* C_PROBE_OUT65_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT65_WIDTH = "1" *)
(* C_PROBE_OUT66_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT66_WIDTH = "1" *)
(* C_PROBE_OUT67_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT67_WIDTH = "1" *)
(* C_PROBE_OUT68_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT68_WIDTH = "1" *)
(* C_PROBE_OUT69_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT69_WIDTH = "1" *)
(* C_PROBE_OUT6_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT6_WIDTH = "1" *)
(* C_PROBE_OUT70_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT70_WIDTH = "1" *)
(* C_PROBE_OUT71_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT71_WIDTH = "1" *)
(* C_PROBE_OUT72_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT72_WIDTH = "1" *)
(* C_PROBE_OUT73_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT73_WIDTH = "1" *)
(* C_PROBE_OUT74_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT74_WIDTH = "1" *)
(* C_PROBE_OUT75_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT75_WIDTH = "1" *)
(* C_PROBE_OUT76_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT76_WIDTH = "1" *)
(* C_PROBE_OUT77_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT77_WIDTH = "1" *)
(* C_PROBE_OUT78_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT78_WIDTH = "1" *)
(* C_PROBE_OUT79_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT79_WIDTH = "1" *)
(* C_PROBE_OUT7_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT7_WIDTH = "1" *)
(* C_PROBE_OUT80_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT80_WIDTH = "1" *)
(* C_PROBE_OUT81_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT81_WIDTH = "1" *)
(* C_PROBE_OUT82_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT82_WIDTH = "1" *)
(* C_PROBE_OUT83_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT83_WIDTH = "1" *)
(* C_PROBE_OUT84_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT84_WIDTH = "1" *)
(* C_PROBE_OUT85_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT85_WIDTH = "1" *)
(* C_PROBE_OUT86_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT86_WIDTH = "1" *)
(* C_PROBE_OUT87_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT87_WIDTH = "1" *)
(* C_PROBE_OUT88_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT88_WIDTH = "1" *)
(* C_PROBE_OUT89_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT89_WIDTH = "1" *)
(* C_PROBE_OUT8_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT8_WIDTH = "1" *)
(* C_PROBE_OUT90_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT90_WIDTH = "1" *)
(* C_PROBE_OUT91_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT91_WIDTH = "1" *)
(* C_PROBE_OUT92_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT92_WIDTH = "1" *)
(* C_PROBE_OUT93_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT93_WIDTH = "1" *)
(* C_PROBE_OUT94_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT94_WIDTH = "1" *)
(* C_PROBE_OUT95_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT95_WIDTH = "1" *)
(* C_PROBE_OUT96_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT96_WIDTH = "1" *)
(* C_PROBE_OUT97_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT97_WIDTH = "1" *)
(* C_PROBE_OUT98_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT98_WIDTH = "1" *)
(* C_PROBE_OUT99_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT99_WIDTH = "1" *)
(* C_PROBE_OUT9_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT9_WIDTH = "1" *)
(* C_USE_TEST_REG = "1" *)
(* C_XDEVICEFAMILY = "kintex7" *)
(* C_XLNX_HW_PROBE_INFO = "DEFAULT" *)
(* C_XSDB_SLAVE_TYPE = "33" *)
(* DONT_TOUCH *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
(* LC_HIGH_BIT_POS_PROBE_OUT0 = "16'b0000000000000000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT1 = "16'b0000000000000001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT10 = "16'b0000000000001010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT100 = "16'b0000000001100100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT101 = "16'b0000000001100101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT102 = "16'b0000000001100110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT103 = "16'b0000000001100111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT104 = "16'b0000000001101000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT105 = "16'b0000000001101001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT106 = "16'b0000000001101010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT107 = "16'b0000000001101011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT108 = "16'b0000000001101100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT109 = "16'b0000000001101101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT11 = "16'b0000000000001011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT110 = "16'b0000000001101110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT111 = "16'b0000000001101111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT112 = "16'b0000000001110000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT113 = "16'b0000000001110001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT114 = "16'b0000000001110010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT115 = "16'b0000000001110011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT116 = "16'b0000000001110100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT117 = "16'b0000000001110101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT118 = "16'b0000000001110110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT119 = "16'b0000000001110111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT12 = "16'b0000000000001100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT120 = "16'b0000000001111000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT121 = "16'b0000000001111001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT122 = "16'b0000000001111010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT123 = "16'b0000000001111011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT124 = "16'b0000000001111100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT125 = "16'b0000000001111101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT126 = "16'b0000000001111110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT127 = "16'b0000000001111111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT128 = "16'b0000000010000000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT129 = "16'b0000000010000001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT13 = "16'b0000000000001101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT130 = "16'b0000000010000010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT131 = "16'b0000000010000011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT132 = "16'b0000000010000100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT133 = "16'b0000000010000101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT134 = "16'b0000000010000110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT135 = "16'b0000000010000111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT136 = "16'b0000000010001000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT137 = "16'b0000000010001001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT138 = "16'b0000000010001010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT139 = "16'b0000000010001011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT14 = "16'b0000000000001110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT140 = "16'b0000000010001100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT141 = "16'b0000000010001101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT142 = "16'b0000000010001110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT143 = "16'b0000000010001111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT144 = "16'b0000000010010000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT145 = "16'b0000000010010001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT146 = "16'b0000000010010010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT147 = "16'b0000000010010011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT148 = "16'b0000000010010100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT149 = "16'b0000000010010101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT15 = "16'b0000000000001111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT150 = "16'b0000000010010110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT151 = "16'b0000000010010111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT152 = "16'b0000000010011000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT153 = "16'b0000000010011001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT154 = "16'b0000000010011010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT155 = "16'b0000000010011011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT156 = "16'b0000000010011100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT157 = "16'b0000000010011101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT158 = "16'b0000000010011110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT159 = "16'b0000000010011111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT16 = "16'b0000000000010000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT160 = "16'b0000000010100000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT161 = "16'b0000000010100001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT162 = "16'b0000000010100010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT163 = "16'b0000000010100011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT164 = "16'b0000000010100100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT165 = "16'b0000000010100101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT166 = "16'b0000000010100110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT167 = "16'b0000000010100111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT168 = "16'b0000000010101000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT169 = "16'b0000000010101001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT17 = "16'b0000000000010001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT170 = "16'b0000000010101010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT171 = "16'b0000000010101011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT172 = "16'b0000000010101100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT173 = "16'b0000000010101101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT174 = "16'b0000000010101110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT175 = "16'b0000000010101111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT176 = "16'b0000000010110000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT177 = "16'b0000000010110001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT178 = "16'b0000000010110010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT179 = "16'b0000000010110011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT18 = "16'b0000000000010010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT180 = "16'b0000000010110100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT181 = "16'b0000000010110101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT182 = "16'b0000000010110110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT183 = "16'b0000000010110111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT184 = "16'b0000000010111000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT185 = "16'b0000000010111001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT186 = "16'b0000000010111010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT187 = "16'b0000000010111011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT188 = "16'b0000000010111100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT189 = "16'b0000000010111101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT19 = "16'b0000000000010011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT190 = "16'b0000000010111110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT191 = "16'b0000000010111111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT192 = "16'b0000000011000000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT193 = "16'b0000000011000001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT194 = "16'b0000000011000010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT195 = "16'b0000000011000011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT196 = "16'b0000000011000100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT197 = "16'b0000000011000101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT198 = "16'b0000000011000110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT199 = "16'b0000000011000111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT2 = "16'b0000000000000010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT20 = "16'b0000000000010100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT200 = "16'b0000000011001000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT201 = "16'b0000000011001001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT202 = "16'b0000000011001010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT203 = "16'b0000000011001011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT204 = "16'b0000000011001100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT205 = "16'b0000000011001101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT206 = "16'b0000000011001110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT207 = "16'b0000000011001111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT208 = "16'b0000000011010000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT209 = "16'b0000000011010001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT21 = "16'b0000000000010101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT210 = "16'b0000000011010010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT211 = "16'b0000000011010011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT212 = "16'b0000000011010100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT213 = "16'b0000000011010101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT214 = "16'b0000000011010110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT215 = "16'b0000000011010111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT216 = "16'b0000000011011000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT217 = "16'b0000000011011001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT218 = "16'b0000000011011010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT219 = "16'b0000000011011011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT22 = "16'b0000000000010110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT220 = "16'b0000000011011100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT221 = "16'b0000000011011101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT222 = "16'b0000000011011110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT223 = "16'b0000000011011111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT224 = "16'b0000000011100000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT225 = "16'b0000000011100001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT226 = "16'b0000000011100010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT227 = "16'b0000000011100011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT228 = "16'b0000000011100100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT229 = "16'b0000000011100101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT23 = "16'b0000000000010111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT230 = "16'b0000000011100110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT231 = "16'b0000000011100111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT232 = "16'b0000000011101000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT233 = "16'b0000000011101001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT234 = "16'b0000000011101010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT235 = "16'b0000000011101011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT236 = "16'b0000000011101100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT237 = "16'b0000000011101101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT238 = "16'b0000000011101110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT239 = "16'b0000000011101111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT24 = "16'b0000000000011000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT240 = "16'b0000000011110000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT241 = "16'b0000000011110001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT242 = "16'b0000000011110010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT243 = "16'b0000000011110011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT244 = "16'b0000000011110100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT245 = "16'b0000000011110101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT246 = "16'b0000000011110110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT247 = "16'b0000000011110111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT248 = "16'b0000000011111000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT249 = "16'b0000000011111001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT25 = "16'b0000000000011001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT250 = "16'b0000000011111010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT251 = "16'b0000000011111011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT252 = "16'b0000000011111100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT253 = "16'b0000000011111101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT254 = "16'b0000000011111110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT255 = "16'b0000000011111111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT26 = "16'b0000000000011010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT27 = "16'b0000000000011011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT28 = "16'b0000000000011100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT29 = "16'b0000000000011101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT3 = "16'b0000000000000011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT30 = "16'b0000000000011110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT31 = "16'b0000000000011111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT32 = "16'b0000000000100000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT33 = "16'b0000000000100001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT34 = "16'b0000000000100010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT35 = "16'b0000000000100011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT36 = "16'b0000000000100100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT37 = "16'b0000000000100101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT38 = "16'b0000000000100110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT39 = "16'b0000000000100111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT4 = "16'b0000000000000100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT40 = "16'b0000000000101000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT41 = "16'b0000000000101001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT42 = "16'b0000000000101010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT43 = "16'b0000000000101011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT44 = "16'b0000000000101100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT45 = "16'b0000000000101101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT46 = "16'b0000000000101110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT47 = "16'b0000000000101111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT48 = "16'b0000000000110000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT49 = "16'b0000000000110001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT5 = "16'b0000000000000101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT50 = "16'b0000000000110010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT51 = "16'b0000000000110011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT52 = "16'b0000000000110100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT53 = "16'b0000000000110101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT54 = "16'b0000000000110110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT55 = "16'b0000000000110111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT56 = "16'b0000000000111000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT57 = "16'b0000000000111001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT58 = "16'b0000000000111010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT59 = "16'b0000000000111011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT6 = "16'b0000000000000110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT60 = "16'b0000000000111100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT61 = "16'b0000000000111101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT62 = "16'b0000000000111110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT63 = "16'b0000000000111111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT64 = "16'b0000000001000000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT65 = "16'b0000000001000001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT66 = "16'b0000000001000010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT67 = "16'b0000000001000011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT68 = "16'b0000000001000100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT69 = "16'b0000000001000101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT7 = "16'b0000000000000111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT70 = "16'b0000000001000110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT71 = "16'b0000000001000111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT72 = "16'b0000000001001000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT73 = "16'b0000000001001001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT74 = "16'b0000000001001010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT75 = "16'b0000000001001011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT76 = "16'b0000000001001100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT77 = "16'b0000000001001101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT78 = "16'b0000000001001110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT79 = "16'b0000000001001111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT8 = "16'b0000000000001000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT80 = "16'b0000000001010000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT81 = "16'b0000000001010001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT82 = "16'b0000000001010010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT83 = "16'b0000000001010011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT84 = "16'b0000000001010100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT85 = "16'b0000000001010101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT86 = "16'b0000000001010110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT87 = "16'b0000000001010111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT88 = "16'b0000000001011000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT89 = "16'b0000000001011001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT9 = "16'b0000000000001001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT90 = "16'b0000000001011010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT91 = "16'b0000000001011011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT92 = "16'b0000000001011100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT93 = "16'b0000000001011101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT94 = "16'b0000000001011110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT95 = "16'b0000000001011111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT96 = "16'b0000000001100000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT97 = "16'b0000000001100001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT98 = "16'b0000000001100010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT99 = "16'b0000000001100011" *)
(* LC_LOW_BIT_POS_PROBE_OUT0 = "16'b0000000000000000" *)
(* LC_LOW_BIT_POS_PROBE_OUT1 = "16'b0000000000000001" *)
(* LC_LOW_BIT_POS_PROBE_OUT10 = "16'b0000000000001010" *)
(* LC_LOW_BIT_POS_PROBE_OUT100 = "16'b0000000001100100" *)
(* LC_LOW_BIT_POS_PROBE_OUT101 = "16'b0000000001100101" *)
(* LC_LOW_BIT_POS_PROBE_OUT102 = "16'b0000000001100110" *)
(* LC_LOW_BIT_POS_PROBE_OUT103 = "16'b0000000001100111" *)
(* LC_LOW_BIT_POS_PROBE_OUT104 = "16'b0000000001101000" *)
(* LC_LOW_BIT_POS_PROBE_OUT105 = "16'b0000000001101001" *)
(* LC_LOW_BIT_POS_PROBE_OUT106 = "16'b0000000001101010" *)
(* LC_LOW_BIT_POS_PROBE_OUT107 = "16'b0000000001101011" *)
(* LC_LOW_BIT_POS_PROBE_OUT108 = "16'b0000000001101100" *)
(* LC_LOW_BIT_POS_PROBE_OUT109 = "16'b0000000001101101" *)
(* LC_LOW_BIT_POS_PROBE_OUT11 = "16'b0000000000001011" *)
(* LC_LOW_BIT_POS_PROBE_OUT110 = "16'b0000000001101110" *)
(* LC_LOW_BIT_POS_PROBE_OUT111 = "16'b0000000001101111" *)
(* LC_LOW_BIT_POS_PROBE_OUT112 = "16'b0000000001110000" *)
(* LC_LOW_BIT_POS_PROBE_OUT113 = "16'b0000000001110001" *)
(* LC_LOW_BIT_POS_PROBE_OUT114 = "16'b0000000001110010" *)
(* LC_LOW_BIT_POS_PROBE_OUT115 = "16'b0000000001110011" *)
(* LC_LOW_BIT_POS_PROBE_OUT116 = "16'b0000000001110100" *)
(* LC_LOW_BIT_POS_PROBE_OUT117 = "16'b0000000001110101" *)
(* LC_LOW_BIT_POS_PROBE_OUT118 = "16'b0000000001110110" *)
(* LC_LOW_BIT_POS_PROBE_OUT119 = "16'b0000000001110111" *)
(* LC_LOW_BIT_POS_PROBE_OUT12 = "16'b0000000000001100" *)
(* LC_LOW_BIT_POS_PROBE_OUT120 = "16'b0000000001111000" *)
(* LC_LOW_BIT_POS_PROBE_OUT121 = "16'b0000000001111001" *)
(* LC_LOW_BIT_POS_PROBE_OUT122 = "16'b0000000001111010" *)
(* LC_LOW_BIT_POS_PROBE_OUT123 = "16'b0000000001111011" *)
(* LC_LOW_BIT_POS_PROBE_OUT124 = "16'b0000000001111100" *)
(* LC_LOW_BIT_POS_PROBE_OUT125 = "16'b0000000001111101" *)
(* LC_LOW_BIT_POS_PROBE_OUT126 = "16'b0000000001111110" *)
(* LC_LOW_BIT_POS_PROBE_OUT127 = "16'b0000000001111111" *)
(* LC_LOW_BIT_POS_PROBE_OUT128 = "16'b0000000010000000" *)
(* LC_LOW_BIT_POS_PROBE_OUT129 = "16'b0000000010000001" *)
(* LC_LOW_BIT_POS_PROBE_OUT13 = "16'b0000000000001101" *)
(* LC_LOW_BIT_POS_PROBE_OUT130 = "16'b0000000010000010" *)
(* LC_LOW_BIT_POS_PROBE_OUT131 = "16'b0000000010000011" *)
(* LC_LOW_BIT_POS_PROBE_OUT132 = "16'b0000000010000100" *)
(* LC_LOW_BIT_POS_PROBE_OUT133 = "16'b0000000010000101" *)
(* LC_LOW_BIT_POS_PROBE_OUT134 = "16'b0000000010000110" *)
(* LC_LOW_BIT_POS_PROBE_OUT135 = "16'b0000000010000111" *)
(* LC_LOW_BIT_POS_PROBE_OUT136 = "16'b0000000010001000" *)
(* LC_LOW_BIT_POS_PROBE_OUT137 = "16'b0000000010001001" *)
(* LC_LOW_BIT_POS_PROBE_OUT138 = "16'b0000000010001010" *)
(* LC_LOW_BIT_POS_PROBE_OUT139 = "16'b0000000010001011" *)
(* LC_LOW_BIT_POS_PROBE_OUT14 = "16'b0000000000001110" *)
(* LC_LOW_BIT_POS_PROBE_OUT140 = "16'b0000000010001100" *)
(* LC_LOW_BIT_POS_PROBE_OUT141 = "16'b0000000010001101" *)
(* LC_LOW_BIT_POS_PROBE_OUT142 = "16'b0000000010001110" *)
(* LC_LOW_BIT_POS_PROBE_OUT143 = "16'b0000000010001111" *)
(* LC_LOW_BIT_POS_PROBE_OUT144 = "16'b0000000010010000" *)
(* LC_LOW_BIT_POS_PROBE_OUT145 = "16'b0000000010010001" *)
(* LC_LOW_BIT_POS_PROBE_OUT146 = "16'b0000000010010010" *)
(* LC_LOW_BIT_POS_PROBE_OUT147 = "16'b0000000010010011" *)
(* LC_LOW_BIT_POS_PROBE_OUT148 = "16'b0000000010010100" *)
(* LC_LOW_BIT_POS_PROBE_OUT149 = "16'b0000000010010101" *)
(* LC_LOW_BIT_POS_PROBE_OUT15 = "16'b0000000000001111" *)
(* LC_LOW_BIT_POS_PROBE_OUT150 = "16'b0000000010010110" *)
(* LC_LOW_BIT_POS_PROBE_OUT151 = "16'b0000000010010111" *)
(* LC_LOW_BIT_POS_PROBE_OUT152 = "16'b0000000010011000" *)
(* LC_LOW_BIT_POS_PROBE_OUT153 = "16'b0000000010011001" *)
(* LC_LOW_BIT_POS_PROBE_OUT154 = "16'b0000000010011010" *)
(* LC_LOW_BIT_POS_PROBE_OUT155 = "16'b0000000010011011" *)
(* LC_LOW_BIT_POS_PROBE_OUT156 = "16'b0000000010011100" *)
(* LC_LOW_BIT_POS_PROBE_OUT157 = "16'b0000000010011101" *)
(* LC_LOW_BIT_POS_PROBE_OUT158 = "16'b0000000010011110" *)
(* LC_LOW_BIT_POS_PROBE_OUT159 = "16'b0000000010011111" *)
(* LC_LOW_BIT_POS_PROBE_OUT16 = "16'b0000000000010000" *)
(* LC_LOW_BIT_POS_PROBE_OUT160 = "16'b0000000010100000" *)
(* LC_LOW_BIT_POS_PROBE_OUT161 = "16'b0000000010100001" *)
(* LC_LOW_BIT_POS_PROBE_OUT162 = "16'b0000000010100010" *)
(* LC_LOW_BIT_POS_PROBE_OUT163 = "16'b0000000010100011" *)
(* LC_LOW_BIT_POS_PROBE_OUT164 = "16'b0000000010100100" *)
(* LC_LOW_BIT_POS_PROBE_OUT165 = "16'b0000000010100101" *)
(* LC_LOW_BIT_POS_PROBE_OUT166 = "16'b0000000010100110" *)
(* LC_LOW_BIT_POS_PROBE_OUT167 = "16'b0000000010100111" *)
(* LC_LOW_BIT_POS_PROBE_OUT168 = "16'b0000000010101000" *)
(* LC_LOW_BIT_POS_PROBE_OUT169 = "16'b0000000010101001" *)
(* LC_LOW_BIT_POS_PROBE_OUT17 = "16'b0000000000010001" *)
(* LC_LOW_BIT_POS_PROBE_OUT170 = "16'b0000000010101010" *)
(* LC_LOW_BIT_POS_PROBE_OUT171 = "16'b0000000010101011" *)
(* LC_LOW_BIT_POS_PROBE_OUT172 = "16'b0000000010101100" *)
(* LC_LOW_BIT_POS_PROBE_OUT173 = "16'b0000000010101101" *)
(* LC_LOW_BIT_POS_PROBE_OUT174 = "16'b0000000010101110" *)
(* LC_LOW_BIT_POS_PROBE_OUT175 = "16'b0000000010101111" *)
(* LC_LOW_BIT_POS_PROBE_OUT176 = "16'b0000000010110000" *)
(* LC_LOW_BIT_POS_PROBE_OUT177 = "16'b0000000010110001" *)
(* LC_LOW_BIT_POS_PROBE_OUT178 = "16'b0000000010110010" *)
(* LC_LOW_BIT_POS_PROBE_OUT179 = "16'b0000000010110011" *)
(* LC_LOW_BIT_POS_PROBE_OUT18 = "16'b0000000000010010" *)
(* LC_LOW_BIT_POS_PROBE_OUT180 = "16'b0000000010110100" *)
(* LC_LOW_BIT_POS_PROBE_OUT181 = "16'b0000000010110101" *)
(* LC_LOW_BIT_POS_PROBE_OUT182 = "16'b0000000010110110" *)
(* LC_LOW_BIT_POS_PROBE_OUT183 = "16'b0000000010110111" *)
(* LC_LOW_BIT_POS_PROBE_OUT184 = "16'b0000000010111000" *)
(* LC_LOW_BIT_POS_PROBE_OUT185 = "16'b0000000010111001" *)
(* LC_LOW_BIT_POS_PROBE_OUT186 = "16'b0000000010111010" *)
(* LC_LOW_BIT_POS_PROBE_OUT187 = "16'b0000000010111011" *)
(* LC_LOW_BIT_POS_PROBE_OUT188 = "16'b0000000010111100" *)
(* LC_LOW_BIT_POS_PROBE_OUT189 = "16'b0000000010111101" *)
(* LC_LOW_BIT_POS_PROBE_OUT19 = "16'b0000000000010011" *)
(* LC_LOW_BIT_POS_PROBE_OUT190 = "16'b0000000010111110" *)
(* LC_LOW_BIT_POS_PROBE_OUT191 = "16'b0000000010111111" *)
(* LC_LOW_BIT_POS_PROBE_OUT192 = "16'b0000000011000000" *)
(* LC_LOW_BIT_POS_PROBE_OUT193 = "16'b0000000011000001" *)
(* LC_LOW_BIT_POS_PROBE_OUT194 = "16'b0000000011000010" *)
(* LC_LOW_BIT_POS_PROBE_OUT195 = "16'b0000000011000011" *)
(* LC_LOW_BIT_POS_PROBE_OUT196 = "16'b0000000011000100" *)
(* LC_LOW_BIT_POS_PROBE_OUT197 = "16'b0000000011000101" *)
(* LC_LOW_BIT_POS_PROBE_OUT198 = "16'b0000000011000110" *)
(* LC_LOW_BIT_POS_PROBE_OUT199 = "16'b0000000011000111" *)
(* LC_LOW_BIT_POS_PROBE_OUT2 = "16'b0000000000000010" *)
(* LC_LOW_BIT_POS_PROBE_OUT20 = "16'b0000000000010100" *)
(* LC_LOW_BIT_POS_PROBE_OUT200 = "16'b0000000011001000" *)
(* LC_LOW_BIT_POS_PROBE_OUT201 = "16'b0000000011001001" *)
(* LC_LOW_BIT_POS_PROBE_OUT202 = "16'b0000000011001010" *)
(* LC_LOW_BIT_POS_PROBE_OUT203 = "16'b0000000011001011" *)
(* LC_LOW_BIT_POS_PROBE_OUT204 = "16'b0000000011001100" *)
(* LC_LOW_BIT_POS_PROBE_OUT205 = "16'b0000000011001101" *)
(* LC_LOW_BIT_POS_PROBE_OUT206 = "16'b0000000011001110" *)
(* LC_LOW_BIT_POS_PROBE_OUT207 = "16'b0000000011001111" *)
(* LC_LOW_BIT_POS_PROBE_OUT208 = "16'b0000000011010000" *)
(* LC_LOW_BIT_POS_PROBE_OUT209 = "16'b0000000011010001" *)
(* LC_LOW_BIT_POS_PROBE_OUT21 = "16'b0000000000010101" *)
(* LC_LOW_BIT_POS_PROBE_OUT210 = "16'b0000000011010010" *)
(* LC_LOW_BIT_POS_PROBE_OUT211 = "16'b0000000011010011" *)
(* LC_LOW_BIT_POS_PROBE_OUT212 = "16'b0000000011010100" *)
(* LC_LOW_BIT_POS_PROBE_OUT213 = "16'b0000000011010101" *)
(* LC_LOW_BIT_POS_PROBE_OUT214 = "16'b0000000011010110" *)
(* LC_LOW_BIT_POS_PROBE_OUT215 = "16'b0000000011010111" *)
(* LC_LOW_BIT_POS_PROBE_OUT216 = "16'b0000000011011000" *)
(* LC_LOW_BIT_POS_PROBE_OUT217 = "16'b0000000011011001" *)
(* LC_LOW_BIT_POS_PROBE_OUT218 = "16'b0000000011011010" *)
(* LC_LOW_BIT_POS_PROBE_OUT219 = "16'b0000000011011011" *)
(* LC_LOW_BIT_POS_PROBE_OUT22 = "16'b0000000000010110" *)
(* LC_LOW_BIT_POS_PROBE_OUT220 = "16'b0000000011011100" *)
(* LC_LOW_BIT_POS_PROBE_OUT221 = "16'b0000000011011101" *)
(* LC_LOW_BIT_POS_PROBE_OUT222 = "16'b0000000011011110" *)
(* LC_LOW_BIT_POS_PROBE_OUT223 = "16'b0000000011011111" *)
(* LC_LOW_BIT_POS_PROBE_OUT224 = "16'b0000000011100000" *)
(* LC_LOW_BIT_POS_PROBE_OUT225 = "16'b0000000011100001" *)
(* LC_LOW_BIT_POS_PROBE_OUT226 = "16'b0000000011100010" *)
(* LC_LOW_BIT_POS_PROBE_OUT227 = "16'b0000000011100011" *)
(* LC_LOW_BIT_POS_PROBE_OUT228 = "16'b0000000011100100" *)
(* LC_LOW_BIT_POS_PROBE_OUT229 = "16'b0000000011100101" *)
(* LC_LOW_BIT_POS_PROBE_OUT23 = "16'b0000000000010111" *)
(* LC_LOW_BIT_POS_PROBE_OUT230 = "16'b0000000011100110" *)
(* LC_LOW_BIT_POS_PROBE_OUT231 = "16'b0000000011100111" *)
(* LC_LOW_BIT_POS_PROBE_OUT232 = "16'b0000000011101000" *)
(* LC_LOW_BIT_POS_PROBE_OUT233 = "16'b0000000011101001" *)
(* LC_LOW_BIT_POS_PROBE_OUT234 = "16'b0000000011101010" *)
(* LC_LOW_BIT_POS_PROBE_OUT235 = "16'b0000000011101011" *)
(* LC_LOW_BIT_POS_PROBE_OUT236 = "16'b0000000011101100" *)
(* LC_LOW_BIT_POS_PROBE_OUT237 = "16'b0000000011101101" *)
(* LC_LOW_BIT_POS_PROBE_OUT238 = "16'b0000000011101110" *)
(* LC_LOW_BIT_POS_PROBE_OUT239 = "16'b0000000011101111" *)
(* LC_LOW_BIT_POS_PROBE_OUT24 = "16'b0000000000011000" *)
(* LC_LOW_BIT_POS_PROBE_OUT240 = "16'b0000000011110000" *)
(* LC_LOW_BIT_POS_PROBE_OUT241 = "16'b0000000011110001" *)
(* LC_LOW_BIT_POS_PROBE_OUT242 = "16'b0000000011110010" *)
(* LC_LOW_BIT_POS_PROBE_OUT243 = "16'b0000000011110011" *)
(* LC_LOW_BIT_POS_PROBE_OUT244 = "16'b0000000011110100" *)
(* LC_LOW_BIT_POS_PROBE_OUT245 = "16'b0000000011110101" *)
(* LC_LOW_BIT_POS_PROBE_OUT246 = "16'b0000000011110110" *)
(* LC_LOW_BIT_POS_PROBE_OUT247 = "16'b0000000011110111" *)
(* LC_LOW_BIT_POS_PROBE_OUT248 = "16'b0000000011111000" *)
(* LC_LOW_BIT_POS_PROBE_OUT249 = "16'b0000000011111001" *)
(* LC_LOW_BIT_POS_PROBE_OUT25 = "16'b0000000000011001" *)
(* LC_LOW_BIT_POS_PROBE_OUT250 = "16'b0000000011111010" *)
(* LC_LOW_BIT_POS_PROBE_OUT251 = "16'b0000000011111011" *)
(* LC_LOW_BIT_POS_PROBE_OUT252 = "16'b0000000011111100" *)
(* LC_LOW_BIT_POS_PROBE_OUT253 = "16'b0000000011111101" *)
(* LC_LOW_BIT_POS_PROBE_OUT254 = "16'b0000000011111110" *)
(* LC_LOW_BIT_POS_PROBE_OUT255 = "16'b0000000011111111" *)
(* LC_LOW_BIT_POS_PROBE_OUT26 = "16'b0000000000011010" *)
(* LC_LOW_BIT_POS_PROBE_OUT27 = "16'b0000000000011011" *)
(* LC_LOW_BIT_POS_PROBE_OUT28 = "16'b0000000000011100" *)
(* LC_LOW_BIT_POS_PROBE_OUT29 = "16'b0000000000011101" *)
(* LC_LOW_BIT_POS_PROBE_OUT3 = "16'b0000000000000011" *)
(* LC_LOW_BIT_POS_PROBE_OUT30 = "16'b0000000000011110" *)
(* LC_LOW_BIT_POS_PROBE_OUT31 = "16'b0000000000011111" *)
(* LC_LOW_BIT_POS_PROBE_OUT32 = "16'b0000000000100000" *)
(* LC_LOW_BIT_POS_PROBE_OUT33 = "16'b0000000000100001" *)
(* LC_LOW_BIT_POS_PROBE_OUT34 = "16'b0000000000100010" *)
(* LC_LOW_BIT_POS_PROBE_OUT35 = "16'b0000000000100011" *)
(* LC_LOW_BIT_POS_PROBE_OUT36 = "16'b0000000000100100" *)
(* LC_LOW_BIT_POS_PROBE_OUT37 = "16'b0000000000100101" *)
(* LC_LOW_BIT_POS_PROBE_OUT38 = "16'b0000000000100110" *)
(* LC_LOW_BIT_POS_PROBE_OUT39 = "16'b0000000000100111" *)
(* LC_LOW_BIT_POS_PROBE_OUT4 = "16'b0000000000000100" *)
(* LC_LOW_BIT_POS_PROBE_OUT40 = "16'b0000000000101000" *)
(* LC_LOW_BIT_POS_PROBE_OUT41 = "16'b0000000000101001" *)
(* LC_LOW_BIT_POS_PROBE_OUT42 = "16'b0000000000101010" *)
(* LC_LOW_BIT_POS_PROBE_OUT43 = "16'b0000000000101011" *)
(* LC_LOW_BIT_POS_PROBE_OUT44 = "16'b0000000000101100" *)
(* LC_LOW_BIT_POS_PROBE_OUT45 = "16'b0000000000101101" *)
(* LC_LOW_BIT_POS_PROBE_OUT46 = "16'b0000000000101110" *)
(* LC_LOW_BIT_POS_PROBE_OUT47 = "16'b0000000000101111" *)
(* LC_LOW_BIT_POS_PROBE_OUT48 = "16'b0000000000110000" *)
(* LC_LOW_BIT_POS_PROBE_OUT49 = "16'b0000000000110001" *)
(* LC_LOW_BIT_POS_PROBE_OUT5 = "16'b0000000000000101" *)
(* LC_LOW_BIT_POS_PROBE_OUT50 = "16'b0000000000110010" *)
(* LC_LOW_BIT_POS_PROBE_OUT51 = "16'b0000000000110011" *)
(* LC_LOW_BIT_POS_PROBE_OUT52 = "16'b0000000000110100" *)
(* LC_LOW_BIT_POS_PROBE_OUT53 = "16'b0000000000110101" *)
(* LC_LOW_BIT_POS_PROBE_OUT54 = "16'b0000000000110110" *)
(* LC_LOW_BIT_POS_PROBE_OUT55 = "16'b0000000000110111" *)
(* LC_LOW_BIT_POS_PROBE_OUT56 = "16'b0000000000111000" *)
(* LC_LOW_BIT_POS_PROBE_OUT57 = "16'b0000000000111001" *)
(* LC_LOW_BIT_POS_PROBE_OUT58 = "16'b0000000000111010" *)
(* LC_LOW_BIT_POS_PROBE_OUT59 = "16'b0000000000111011" *)
(* LC_LOW_BIT_POS_PROBE_OUT6 = "16'b0000000000000110" *)
(* LC_LOW_BIT_POS_PROBE_OUT60 = "16'b0000000000111100" *)
(* LC_LOW_BIT_POS_PROBE_OUT61 = "16'b0000000000111101" *)
(* LC_LOW_BIT_POS_PROBE_OUT62 = "16'b0000000000111110" *)
(* LC_LOW_BIT_POS_PROBE_OUT63 = "16'b0000000000111111" *)
(* LC_LOW_BIT_POS_PROBE_OUT64 = "16'b0000000001000000" *)
(* LC_LOW_BIT_POS_PROBE_OUT65 = "16'b0000000001000001" *)
(* LC_LOW_BIT_POS_PROBE_OUT66 = "16'b0000000001000010" *)
(* LC_LOW_BIT_POS_PROBE_OUT67 = "16'b0000000001000011" *)
(* LC_LOW_BIT_POS_PROBE_OUT68 = "16'b0000000001000100" *)
(* LC_LOW_BIT_POS_PROBE_OUT69 = "16'b0000000001000101" *)
(* LC_LOW_BIT_POS_PROBE_OUT7 = "16'b0000000000000111" *)
(* LC_LOW_BIT_POS_PROBE_OUT70 = "16'b0000000001000110" *)
(* LC_LOW_BIT_POS_PROBE_OUT71 = "16'b0000000001000111" *)
(* LC_LOW_BIT_POS_PROBE_OUT72 = "16'b0000000001001000" *)
(* LC_LOW_BIT_POS_PROBE_OUT73 = "16'b0000000001001001" *)
(* LC_LOW_BIT_POS_PROBE_OUT74 = "16'b0000000001001010" *)
(* LC_LOW_BIT_POS_PROBE_OUT75 = "16'b0000000001001011" *)
(* LC_LOW_BIT_POS_PROBE_OUT76 = "16'b0000000001001100" *)
(* LC_LOW_BIT_POS_PROBE_OUT77 = "16'b0000000001001101" *)
(* LC_LOW_BIT_POS_PROBE_OUT78 = "16'b0000000001001110" *)
(* LC_LOW_BIT_POS_PROBE_OUT79 = "16'b0000000001001111" *)
(* LC_LOW_BIT_POS_PROBE_OUT8 = "16'b0000000000001000" *)
(* LC_LOW_BIT_POS_PROBE_OUT80 = "16'b0000000001010000" *)
(* LC_LOW_BIT_POS_PROBE_OUT81 = "16'b0000000001010001" *)
(* LC_LOW_BIT_POS_PROBE_OUT82 = "16'b0000000001010010" *)
(* LC_LOW_BIT_POS_PROBE_OUT83 = "16'b0000000001010011" *)
(* LC_LOW_BIT_POS_PROBE_OUT84 = "16'b0000000001010100" *)
(* LC_LOW_BIT_POS_PROBE_OUT85 = "16'b0000000001010101" *)
(* LC_LOW_BIT_POS_PROBE_OUT86 = "16'b0000000001010110" *)
(* LC_LOW_BIT_POS_PROBE_OUT87 = "16'b0000000001010111" *)
(* LC_LOW_BIT_POS_PROBE_OUT88 = "16'b0000000001011000" *)
(* LC_LOW_BIT_POS_PROBE_OUT89 = "16'b0000000001011001" *)
(* LC_LOW_BIT_POS_PROBE_OUT9 = "16'b0000000000001001" *)
(* LC_LOW_BIT_POS_PROBE_OUT90 = "16'b0000000001011010" *)
(* LC_LOW_BIT_POS_PROBE_OUT91 = "16'b0000000001011011" *)
(* LC_LOW_BIT_POS_PROBE_OUT92 = "16'b0000000001011100" *)
(* LC_LOW_BIT_POS_PROBE_OUT93 = "16'b0000000001011101" *)
(* LC_LOW_BIT_POS_PROBE_OUT94 = "16'b0000000001011110" *)
(* LC_LOW_BIT_POS_PROBE_OUT95 = "16'b0000000001011111" *)
(* LC_LOW_BIT_POS_PROBE_OUT96 = "16'b0000000001100000" *)
(* LC_LOW_BIT_POS_PROBE_OUT97 = "16'b0000000001100001" *)
(* LC_LOW_BIT_POS_PROBE_OUT98 = "16'b0000000001100010" *)
(* LC_LOW_BIT_POS_PROBE_OUT99 = "16'b0000000001100011" *)
(* LC_PROBE_IN_WIDTH_STRING = "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
(* LC_PROBE_OUT_HIGH_BIT_POS_STRING = "4096'b0000000011111111000000001111111000000000111111010000000011111100000000001111101100000000111110100000000011111001000000001111100000000000111101110000000011110110000000001111010100000000111101000000000011110011000000001111001000000000111100010000000011110000000000001110111100000000111011100000000011101101000000001110110000000000111010110000000011101010000000001110100100000000111010000000000011100111000000001110011000000000111001010000000011100100000000001110001100000000111000100000000011100001000000001110000000000000110111110000000011011110000000001101110100000000110111000000000011011011000000001101101000000000110110010000000011011000000000001101011100000000110101100000000011010101000000001101010000000000110100110000000011010010000000001101000100000000110100000000000011001111000000001100111000000000110011010000000011001100000000001100101100000000110010100000000011001001000000001100100000000000110001110000000011000110000000001100010100000000110001000000000011000011000000001100001000000000110000010000000011000000000000001011111100000000101111100000000010111101000000001011110000000000101110110000000010111010000000001011100100000000101110000000000010110111000000001011011000000000101101010000000010110100000000001011001100000000101100100000000010110001000000001011000000000000101011110000000010101110000000001010110100000000101011000000000010101011000000001010101000000000101010010000000010101000000000001010011100000000101001100000000010100101000000001010010000000000101000110000000010100010000000001010000100000000101000000000000010011111000000001001111000000000100111010000000010011100000000001001101100000000100110100000000010011001000000001001100000000000100101110000000010010110000000001001010100000000100101000000000010010011000000001001001000000000100100010000000010010000000000001000111100000000100011100000000010001101000000001000110000000000100010110000000010001010000000001000100100000000100010000000000010000111000000001000011000000000100001010000000010000100000000001000001100000000100000100000000010000001000000001000000000000000011111110000000001111110000000000111110100000000011111000000000001111011000000000111101000000000011110010000000001111000000000000111011100000000011101100000000001110101000000000111010000000000011100110000000001110010000000000111000100000000011100000000000001101111000000000110111000000000011011010000000001101100000000000110101100000000011010100000000001101001000000000110100000000000011001110000000001100110000000000110010100000000011001000000000001100011000000000110001000000000011000010000000001100000000000000101111100000000010111100000000001011101000000000101110000000000010110110000000001011010000000000101100100000000010110000000000001010111000000000101011000000000010101010000000001010100000000000101001100000000010100100000000001010001000000000101000000000000010011110000000001001110000000000100110100000000010011000000000001001011000000000100101000000000010010010000000001001000000000000100011100000000010001100000000001000101000000000100010000000000010000110000000001000010000000000100000100000000010000000000000000111111000000000011111000000000001111010000000000111100000000000011101100000000001110100000000000111001000000000011100000000000001101110000000000110110000000000011010100000000001101000000000000110011000000000011001000000000001100010000000000110000000000000010111100000000001011100000000000101101000000000010110000000000001010110000000000101010000000000010100100000000001010000000000000100111000000000010011000000000001001010000000000100100000000000010001100000000001000100000000000100001000000000010000000000000000111110000000000011110000000000001110100000000000111000000000000011011000000000001101000000000000110010000000000011000000000000001011100000000000101100000000000010101000000000001010000000000000100110000000000010010000000000001000100000000000100000000000000001111000000000000111000000000000011010000000000001100000000000000101100000000000010100000000000001001000000000000100000000000000001110000000000000110000000000000010100000000000001000000000000000011000000000000001000000000000000010000000000000000" *)
(* LC_PROBE_OUT_INIT_VAL_STRING = "256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
(* LC_PROBE_OUT_LOW_BIT_POS_STRING = "4096'b0000000011111111000000001111111000000000111111010000000011111100000000001111101100000000111110100000000011111001000000001111100000000000111101110000000011110110000000001111010100000000111101000000000011110011000000001111001000000000111100010000000011110000000000001110111100000000111011100000000011101101000000001110110000000000111010110000000011101010000000001110100100000000111010000000000011100111000000001110011000000000111001010000000011100100000000001110001100000000111000100000000011100001000000001110000000000000110111110000000011011110000000001101110100000000110111000000000011011011000000001101101000000000110110010000000011011000000000001101011100000000110101100000000011010101000000001101010000000000110100110000000011010010000000001101000100000000110100000000000011001111000000001100111000000000110011010000000011001100000000001100101100000000110010100000000011001001000000001100100000000000110001110000000011000110000000001100010100000000110001000000000011000011000000001100001000000000110000010000000011000000000000001011111100000000101111100000000010111101000000001011110000000000101110110000000010111010000000001011100100000000101110000000000010110111000000001011011000000000101101010000000010110100000000001011001100000000101100100000000010110001000000001011000000000000101011110000000010101110000000001010110100000000101011000000000010101011000000001010101000000000101010010000000010101000000000001010011100000000101001100000000010100101000000001010010000000000101000110000000010100010000000001010000100000000101000000000000010011111000000001001111000000000100111010000000010011100000000001001101100000000100110100000000010011001000000001001100000000000100101110000000010010110000000001001010100000000100101000000000010010011000000001001001000000000100100010000000010010000000000001000111100000000100011100000000010001101000000001000110000000000100010110000000010001010000000001000100100000000100010000000000010000111000000001000011000000000100001010000000010000100000000001000001100000000100000100000000010000001000000001000000000000000011111110000000001111110000000000111110100000000011111000000000001111011000000000111101000000000011110010000000001111000000000000111011100000000011101100000000001110101000000000111010000000000011100110000000001110010000000000111000100000000011100000000000001101111000000000110111000000000011011010000000001101100000000000110101100000000011010100000000001101001000000000110100000000000011001110000000001100110000000000110010100000000011001000000000001100011000000000110001000000000011000010000000001100000000000000101111100000000010111100000000001011101000000000101110000000000010110110000000001011010000000000101100100000000010110000000000001010111000000000101011000000000010101010000000001010100000000000101001100000000010100100000000001010001000000000101000000000000010011110000000001001110000000000100110100000000010011000000000001001011000000000100101000000000010010010000000001001000000000000100011100000000010001100000000001000101000000000100010000000000010000110000000001000010000000000100000100000000010000000000000000111111000000000011111000000000001111010000000000111100000000000011101100000000001110100000000000111001000000000011100000000000001101110000000000110110000000000011010100000000001101000000000000110011000000000011001000000000001100010000000000110000000000000010111100000000001011100000000000101101000000000010110000000000001010110000000000101010000000000010100100000000001010000000000000100111000000000010011000000000001001010000000000100100000000000010001100000000001000100000000000100001000000000010000000000000000111110000000000011110000000000001110100000000000111000000000000011011000000000001101000000000000110010000000000011000000000000001011100000000000101100000000000010101000000000001010000000000000100110000000000010010000000000001000100000000000100000000000000001111000000000000111000000000000011010000000000001100000000000000101100000000000010100000000000001001000000000000100000000000000001110000000000000110000000000000010100000000000001000000000000000011000000000000001000000000000000010000000000000000" *)
(* LC_PROBE_OUT_WIDTH_STRING = "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
(* LC_TOTAL_PROBE_IN_WIDTH = "4" *)
(* LC_TOTAL_PROBE_OUT_WIDTH = "0" *)
(* syn_noprune = "1" *)
vio_0_vio_v3_0_13_vio inst
(.clk(clk),
.probe_in0(probe_in0),
.probe_in1(probe_in1),
.probe_in10(1'b0),
.probe_in100(1'b0),
.probe_in101(1'b0),
.probe_in102(1'b0),
.probe_in103(1'b0),
.probe_in104(1'b0),
.probe_in105(1'b0),
.probe_in106(1'b0),
.probe_in107(1'b0),
.probe_in108(1'b0),
.probe_in109(1'b0),
.probe_in11(1'b0),
.probe_in110(1'b0),
.probe_in111(1'b0),
.probe_in112(1'b0),
.probe_in113(1'b0),
.probe_in114(1'b0),
.probe_in115(1'b0),
.probe_in116(1'b0),
.probe_in117(1'b0),
.probe_in118(1'b0),
.probe_in119(1'b0),
.probe_in12(1'b0),
.probe_in120(1'b0),
.probe_in121(1'b0),
.probe_in122(1'b0),
.probe_in123(1'b0),
.probe_in124(1'b0),
.probe_in125(1'b0),
.probe_in126(1'b0),
.probe_in127(1'b0),
.probe_in128(1'b0),
.probe_in129(1'b0),
.probe_in13(1'b0),
.probe_in130(1'b0),
.probe_in131(1'b0),
.probe_in132(1'b0),
.probe_in133(1'b0),
.probe_in134(1'b0),
.probe_in135(1'b0),
.probe_in136(1'b0),
.probe_in137(1'b0),
.probe_in138(1'b0),
.probe_in139(1'b0),
.probe_in14(1'b0),
.probe_in140(1'b0),
.probe_in141(1'b0),
.probe_in142(1'b0),
.probe_in143(1'b0),
.probe_in144(1'b0),
.probe_in145(1'b0),
.probe_in146(1'b0),
.probe_in147(1'b0),
.probe_in148(1'b0),
.probe_in149(1'b0),
.probe_in15(1'b0),
.probe_in150(1'b0),
.probe_in151(1'b0),
.probe_in152(1'b0),
.probe_in153(1'b0),
.probe_in154(1'b0),
.probe_in155(1'b0),
.probe_in156(1'b0),
.probe_in157(1'b0),
.probe_in158(1'b0),
.probe_in159(1'b0),
.probe_in16(1'b0),
.probe_in160(1'b0),
.probe_in161(1'b0),
.probe_in162(1'b0),
.probe_in163(1'b0),
.probe_in164(1'b0),
.probe_in165(1'b0),
.probe_in166(1'b0),
.probe_in167(1'b0),
.probe_in168(1'b0),
.probe_in169(1'b0),
.probe_in17(1'b0),
.probe_in170(1'b0),
.probe_in171(1'b0),
.probe_in172(1'b0),
.probe_in173(1'b0),
.probe_in174(1'b0),
.probe_in175(1'b0),
.probe_in176(1'b0),
.probe_in177(1'b0),
.probe_in178(1'b0),
.probe_in179(1'b0),
.probe_in18(1'b0),
.probe_in180(1'b0),
.probe_in181(1'b0),
.probe_in182(1'b0),
.probe_in183(1'b0),
.probe_in184(1'b0),
.probe_in185(1'b0),
.probe_in186(1'b0),
.probe_in187(1'b0),
.probe_in188(1'b0),
.probe_in189(1'b0),
.probe_in19(1'b0),
.probe_in190(1'b0),
.probe_in191(1'b0),
.probe_in192(1'b0),
.probe_in193(1'b0),
.probe_in194(1'b0),
.probe_in195(1'b0),
.probe_in196(1'b0),
.probe_in197(1'b0),
.probe_in198(1'b0),
.probe_in199(1'b0),
.probe_in2(probe_in2),
.probe_in20(1'b0),
.probe_in200(1'b0),
.probe_in201(1'b0),
.probe_in202(1'b0),
.probe_in203(1'b0),
.probe_in204(1'b0),
.probe_in205(1'b0),
.probe_in206(1'b0),
.probe_in207(1'b0),
.probe_in208(1'b0),
.probe_in209(1'b0),
.probe_in21(1'b0),
.probe_in210(1'b0),
.probe_in211(1'b0),
.probe_in212(1'b0),
.probe_in213(1'b0),
.probe_in214(1'b0),
.probe_in215(1'b0),
.probe_in216(1'b0),
.probe_in217(1'b0),
.probe_in218(1'b0),
.probe_in219(1'b0),
.probe_in22(1'b0),
.probe_in220(1'b0),
.probe_in221(1'b0),
.probe_in222(1'b0),
.probe_in223(1'b0),
.probe_in224(1'b0),
.probe_in225(1'b0),
.probe_in226(1'b0),
.probe_in227(1'b0),
.probe_in228(1'b0),
.probe_in229(1'b0),
.probe_in23(1'b0),
.probe_in230(1'b0),
.probe_in231(1'b0),
.probe_in232(1'b0),
.probe_in233(1'b0),
.probe_in234(1'b0),
.probe_in235(1'b0),
.probe_in236(1'b0),
.probe_in237(1'b0),
.probe_in238(1'b0),
.probe_in239(1'b0),
.probe_in24(1'b0),
.probe_in240(1'b0),
.probe_in241(1'b0),
.probe_in242(1'b0),
.probe_in243(1'b0),
.probe_in244(1'b0),
.probe_in245(1'b0),
.probe_in246(1'b0),
.probe_in247(1'b0),
.probe_in248(1'b0),
.probe_in249(1'b0),
.probe_in25(1'b0),
.probe_in250(1'b0),
.probe_in251(1'b0),
.probe_in252(1'b0),
.probe_in253(1'b0),
.probe_in254(1'b0),
.probe_in255(1'b0),
.probe_in26(1'b0),
.probe_in27(1'b0),
.probe_in28(1'b0),
.probe_in29(1'b0),
.probe_in3(probe_in3),
.probe_in30(1'b0),
.probe_in31(1'b0),
.probe_in32(1'b0),
.probe_in33(1'b0),
.probe_in34(1'b0),
.probe_in35(1'b0),
.probe_in36(1'b0),
.probe_in37(1'b0),
.probe_in38(1'b0),
.probe_in39(1'b0),
.probe_in4(1'b0),
.probe_in40(1'b0),
.probe_in41(1'b0),
.probe_in42(1'b0),
.probe_in43(1'b0),
.probe_in44(1'b0),
.probe_in45(1'b0),
.probe_in46(1'b0),
.probe_in47(1'b0),
.probe_in48(1'b0),
.probe_in49(1'b0),
.probe_in5(1'b0),
.probe_in50(1'b0),
.probe_in51(1'b0),
.probe_in52(1'b0),
.probe_in53(1'b0),
.probe_in54(1'b0),
.probe_in55(1'b0),
.probe_in56(1'b0),
.probe_in57(1'b0),
.probe_in58(1'b0),
.probe_in59(1'b0),
.probe_in6(1'b0),
.probe_in60(1'b0),
.probe_in61(1'b0),
.probe_in62(1'b0),
.probe_in63(1'b0),
.probe_in64(1'b0),
.probe_in65(1'b0),
.probe_in66(1'b0),
.probe_in67(1'b0),
.probe_in68(1'b0),
.probe_in69(1'b0),
.probe_in7(1'b0),
.probe_in70(1'b0),
.probe_in71(1'b0),
.probe_in72(1'b0),
.probe_in73(1'b0),
.probe_in74(1'b0),
.probe_in75(1'b0),
.probe_in76(1'b0),
.probe_in77(1'b0),
.probe_in78(1'b0),
.probe_in79(1'b0),
.probe_in8(1'b0),
.probe_in80(1'b0),
.probe_in81(1'b0),
.probe_in82(1'b0),
.probe_in83(1'b0),
.probe_in84(1'b0),
.probe_in85(1'b0),
.probe_in86(1'b0),
.probe_in87(1'b0),
.probe_in88(1'b0),
.probe_in89(1'b0),
.probe_in9(1'b0),
.probe_in90(1'b0),
.probe_in91(1'b0),
.probe_in92(1'b0),
.probe_in93(1'b0),
.probe_in94(1'b0),
.probe_in95(1'b0),
.probe_in96(1'b0),
.probe_in97(1'b0),
.probe_in98(1'b0),
.probe_in99(1'b0),
.probe_out0(NLW_inst_probe_out0_UNCONNECTED[0]),
.probe_out1(NLW_inst_probe_out1_UNCONNECTED[0]),
.probe_out10(NLW_inst_probe_out10_UNCONNECTED[0]),
.probe_out100(NLW_inst_probe_out100_UNCONNECTED[0]),
.probe_out101(NLW_inst_probe_out101_UNCONNECTED[0]),
.probe_out102(NLW_inst_probe_out102_UNCONNECTED[0]),
.probe_out103(NLW_inst_probe_out103_UNCONNECTED[0]),
.probe_out104(NLW_inst_probe_out104_UNCONNECTED[0]),
.probe_out105(NLW_inst_probe_out105_UNCONNECTED[0]),
.probe_out106(NLW_inst_probe_out106_UNCONNECTED[0]),
.probe_out107(NLW_inst_probe_out107_UNCONNECTED[0]),
.probe_out108(NLW_inst_probe_out108_UNCONNECTED[0]),
.probe_out109(NLW_inst_probe_out109_UNCONNECTED[0]),
.probe_out11(NLW_inst_probe_out11_UNCONNECTED[0]),
.probe_out110(NLW_inst_probe_out110_UNCONNECTED[0]),
.probe_out111(NLW_inst_probe_out111_UNCONNECTED[0]),
.probe_out112(NLW_inst_probe_out112_UNCONNECTED[0]),
.probe_out113(NLW_inst_probe_out113_UNCONNECTED[0]),
.probe_out114(NLW_inst_probe_out114_UNCONNECTED[0]),
.probe_out115(NLW_inst_probe_out115_UNCONNECTED[0]),
.probe_out116(NLW_inst_probe_out116_UNCONNECTED[0]),
.probe_out117(NLW_inst_probe_out117_UNCONNECTED[0]),
.probe_out118(NLW_inst_probe_out118_UNCONNECTED[0]),
.probe_out119(NLW_inst_probe_out119_UNCONNECTED[0]),
.probe_out12(NLW_inst_probe_out12_UNCONNECTED[0]),
.probe_out120(NLW_inst_probe_out120_UNCONNECTED[0]),
.probe_out121(NLW_inst_probe_out121_UNCONNECTED[0]),
.probe_out122(NLW_inst_probe_out122_UNCONNECTED[0]),
.probe_out123(NLW_inst_probe_out123_UNCONNECTED[0]),
.probe_out124(NLW_inst_probe_out124_UNCONNECTED[0]),
.probe_out125(NLW_inst_probe_out125_UNCONNECTED[0]),
.probe_out126(NLW_inst_probe_out126_UNCONNECTED[0]),
.probe_out127(NLW_inst_probe_out127_UNCONNECTED[0]),
.probe_out128(NLW_inst_probe_out128_UNCONNECTED[0]),
.probe_out129(NLW_inst_probe_out129_UNCONNECTED[0]),
.probe_out13(NLW_inst_probe_out13_UNCONNECTED[0]),
.probe_out130(NLW_inst_probe_out130_UNCONNECTED[0]),
.probe_out131(NLW_inst_probe_out131_UNCONNECTED[0]),
.probe_out132(NLW_inst_probe_out132_UNCONNECTED[0]),
.probe_out133(NLW_inst_probe_out133_UNCONNECTED[0]),
.probe_out134(NLW_inst_probe_out134_UNCONNECTED[0]),
.probe_out135(NLW_inst_probe_out135_UNCONNECTED[0]),
.probe_out136(NLW_inst_probe_out136_UNCONNECTED[0]),
.probe_out137(NLW_inst_probe_out137_UNCONNECTED[0]),
.probe_out138(NLW_inst_probe_out138_UNCONNECTED[0]),
.probe_out139(NLW_inst_probe_out139_UNCONNECTED[0]),
.probe_out14(NLW_inst_probe_out14_UNCONNECTED[0]),
.probe_out140(NLW_inst_probe_out140_UNCONNECTED[0]),
.probe_out141(NLW_inst_probe_out141_UNCONNECTED[0]),
.probe_out142(NLW_inst_probe_out142_UNCONNECTED[0]),
.probe_out143(NLW_inst_probe_out143_UNCONNECTED[0]),
.probe_out144(NLW_inst_probe_out144_UNCONNECTED[0]),
.probe_out145(NLW_inst_probe_out145_UNCONNECTED[0]),
.probe_out146(NLW_inst_probe_out146_UNCONNECTED[0]),
.probe_out147(NLW_inst_probe_out147_UNCONNECTED[0]),
.probe_out148(NLW_inst_probe_out148_UNCONNECTED[0]),
.probe_out149(NLW_inst_probe_out149_UNCONNECTED[0]),
.probe_out15(NLW_inst_probe_out15_UNCONNECTED[0]),
.probe_out150(NLW_inst_probe_out150_UNCONNECTED[0]),
.probe_out151(NLW_inst_probe_out151_UNCONNECTED[0]),
.probe_out152(NLW_inst_probe_out152_UNCONNECTED[0]),
.probe_out153(NLW_inst_probe_out153_UNCONNECTED[0]),
.probe_out154(NLW_inst_probe_out154_UNCONNECTED[0]),
.probe_out155(NLW_inst_probe_out155_UNCONNECTED[0]),
.probe_out156(NLW_inst_probe_out156_UNCONNECTED[0]),
.probe_out157(NLW_inst_probe_out157_UNCONNECTED[0]),
.probe_out158(NLW_inst_probe_out158_UNCONNECTED[0]),
.probe_out159(NLW_inst_probe_out159_UNCONNECTED[0]),
.probe_out16(NLW_inst_probe_out16_UNCONNECTED[0]),
.probe_out160(NLW_inst_probe_out160_UNCONNECTED[0]),
.probe_out161(NLW_inst_probe_out161_UNCONNECTED[0]),
.probe_out162(NLW_inst_probe_out162_UNCONNECTED[0]),
.probe_out163(NLW_inst_probe_out163_UNCONNECTED[0]),
.probe_out164(NLW_inst_probe_out164_UNCONNECTED[0]),
.probe_out165(NLW_inst_probe_out165_UNCONNECTED[0]),
.probe_out166(NLW_inst_probe_out166_UNCONNECTED[0]),
.probe_out167(NLW_inst_probe_out167_UNCONNECTED[0]),
.probe_out168(NLW_inst_probe_out168_UNCONNECTED[0]),
.probe_out169(NLW_inst_probe_out169_UNCONNECTED[0]),
.probe_out17(NLW_inst_probe_out17_UNCONNECTED[0]),
.probe_out170(NLW_inst_probe_out170_UNCONNECTED[0]),
.probe_out171(NLW_inst_probe_out171_UNCONNECTED[0]),
.probe_out172(NLW_inst_probe_out172_UNCONNECTED[0]),
.probe_out173(NLW_inst_probe_out173_UNCONNECTED[0]),
.probe_out174(NLW_inst_probe_out174_UNCONNECTED[0]),
.probe_out175(NLW_inst_probe_out175_UNCONNECTED[0]),
.probe_out176(NLW_inst_probe_out176_UNCONNECTED[0]),
.probe_out177(NLW_inst_probe_out177_UNCONNECTED[0]),
.probe_out178(NLW_inst_probe_out178_UNCONNECTED[0]),
.probe_out179(NLW_inst_probe_out179_UNCONNECTED[0]),
.probe_out18(NLW_inst_probe_out18_UNCONNECTED[0]),
.probe_out180(NLW_inst_probe_out180_UNCONNECTED[0]),
.probe_out181(NLW_inst_probe_out181_UNCONNECTED[0]),
.probe_out182(NLW_inst_probe_out182_UNCONNECTED[0]),
.probe_out183(NLW_inst_probe_out183_UNCONNECTED[0]),
.probe_out184(NLW_inst_probe_out184_UNCONNECTED[0]),
.probe_out185(NLW_inst_probe_out185_UNCONNECTED[0]),
.probe_out186(NLW_inst_probe_out186_UNCONNECTED[0]),
.probe_out187(NLW_inst_probe_out187_UNCONNECTED[0]),
.probe_out188(NLW_inst_probe_out188_UNCONNECTED[0]),
.probe_out189(NLW_inst_probe_out189_UNCONNECTED[0]),
.probe_out19(NLW_inst_probe_out19_UNCONNECTED[0]),
.probe_out190(NLW_inst_probe_out190_UNCONNECTED[0]),
.probe_out191(NLW_inst_probe_out191_UNCONNECTED[0]),
.probe_out192(NLW_inst_probe_out192_UNCONNECTED[0]),
.probe_out193(NLW_inst_probe_out193_UNCONNECTED[0]),
.probe_out194(NLW_inst_probe_out194_UNCONNECTED[0]),
.probe_out195(NLW_inst_probe_out195_UNCONNECTED[0]),
.probe_out196(NLW_inst_probe_out196_UNCONNECTED[0]),
.probe_out197(NLW_inst_probe_out197_UNCONNECTED[0]),
.probe_out198(NLW_inst_probe_out198_UNCONNECTED[0]),
.probe_out199(NLW_inst_probe_out199_UNCONNECTED[0]),
.probe_out2(NLW_inst_probe_out2_UNCONNECTED[0]),
.probe_out20(NLW_inst_probe_out20_UNCONNECTED[0]),
.probe_out200(NLW_inst_probe_out200_UNCONNECTED[0]),
.probe_out201(NLW_inst_probe_out201_UNCONNECTED[0]),
.probe_out202(NLW_inst_probe_out202_UNCONNECTED[0]),
.probe_out203(NLW_inst_probe_out203_UNCONNECTED[0]),
.probe_out204(NLW_inst_probe_out204_UNCONNECTED[0]),
.probe_out205(NLW_inst_probe_out205_UNCONNECTED[0]),
.probe_out206(NLW_inst_probe_out206_UNCONNECTED[0]),
.probe_out207(NLW_inst_probe_out207_UNCONNECTED[0]),
.probe_out208(NLW_inst_probe_out208_UNCONNECTED[0]),
.probe_out209(NLW_inst_probe_out209_UNCONNECTED[0]),
.probe_out21(NLW_inst_probe_out21_UNCONNECTED[0]),
.probe_out210(NLW_inst_probe_out210_UNCONNECTED[0]),
.probe_out211(NLW_inst_probe_out211_UNCONNECTED[0]),
.probe_out212(NLW_inst_probe_out212_UNCONNECTED[0]),
.probe_out213(NLW_inst_probe_out213_UNCONNECTED[0]),
.probe_out214(NLW_inst_probe_out214_UNCONNECTED[0]),
.probe_out215(NLW_inst_probe_out215_UNCONNECTED[0]),
.probe_out216(NLW_inst_probe_out216_UNCONNECTED[0]),
.probe_out217(NLW_inst_probe_out217_UNCONNECTED[0]),
.probe_out218(NLW_inst_probe_out218_UNCONNECTED[0]),
.probe_out219(NLW_inst_probe_out219_UNCONNECTED[0]),
.probe_out22(NLW_inst_probe_out22_UNCONNECTED[0]),
.probe_out220(NLW_inst_probe_out220_UNCONNECTED[0]),
.probe_out221(NLW_inst_probe_out221_UNCONNECTED[0]),
.probe_out222(NLW_inst_probe_out222_UNCONNECTED[0]),
.probe_out223(NLW_inst_probe_out223_UNCONNECTED[0]),
.probe_out224(NLW_inst_probe_out224_UNCONNECTED[0]),
.probe_out225(NLW_inst_probe_out225_UNCONNECTED[0]),
.probe_out226(NLW_inst_probe_out226_UNCONNECTED[0]),
.probe_out227(NLW_inst_probe_out227_UNCONNECTED[0]),
.probe_out228(NLW_inst_probe_out228_UNCONNECTED[0]),
.probe_out229(NLW_inst_probe_out229_UNCONNECTED[0]),
.probe_out23(NLW_inst_probe_out23_UNCONNECTED[0]),
.probe_out230(NLW_inst_probe_out230_UNCONNECTED[0]),
.probe_out231(NLW_inst_probe_out231_UNCONNECTED[0]),
.probe_out232(NLW_inst_probe_out232_UNCONNECTED[0]),
.probe_out233(NLW_inst_probe_out233_UNCONNECTED[0]),
.probe_out234(NLW_inst_probe_out234_UNCONNECTED[0]),
.probe_out235(NLW_inst_probe_out235_UNCONNECTED[0]),
.probe_out236(NLW_inst_probe_out236_UNCONNECTED[0]),
.probe_out237(NLW_inst_probe_out237_UNCONNECTED[0]),
.probe_out238(NLW_inst_probe_out238_UNCONNECTED[0]),
.probe_out239(NLW_inst_probe_out239_UNCONNECTED[0]),
.probe_out24(NLW_inst_probe_out24_UNCONNECTED[0]),
.probe_out240(NLW_inst_probe_out240_UNCONNECTED[0]),
.probe_out241(NLW_inst_probe_out241_UNCONNECTED[0]),
.probe_out242(NLW_inst_probe_out242_UNCONNECTED[0]),
.probe_out243(NLW_inst_probe_out243_UNCONNECTED[0]),
.probe_out244(NLW_inst_probe_out244_UNCONNECTED[0]),
.probe_out245(NLW_inst_probe_out245_UNCONNECTED[0]),
.probe_out246(NLW_inst_probe_out246_UNCONNECTED[0]),
.probe_out247(NLW_inst_probe_out247_UNCONNECTED[0]),
.probe_out248(NLW_inst_probe_out248_UNCONNECTED[0]),
.probe_out249(NLW_inst_probe_out249_UNCONNECTED[0]),
.probe_out25(NLW_inst_probe_out25_UNCONNECTED[0]),
.probe_out250(NLW_inst_probe_out250_UNCONNECTED[0]),
.probe_out251(NLW_inst_probe_out251_UNCONNECTED[0]),
.probe_out252(NLW_inst_probe_out252_UNCONNECTED[0]),
.probe_out253(NLW_inst_probe_out253_UNCONNECTED[0]),
.probe_out254(NLW_inst_probe_out254_UNCONNECTED[0]),
.probe_out255(NLW_inst_probe_out255_UNCONNECTED[0]),
.probe_out26(NLW_inst_probe_out26_UNCONNECTED[0]),
.probe_out27(NLW_inst_probe_out27_UNCONNECTED[0]),
.probe_out28(NLW_inst_probe_out28_UNCONNECTED[0]),
.probe_out29(NLW_inst_probe_out29_UNCONNECTED[0]),
.probe_out3(NLW_inst_probe_out3_UNCONNECTED[0]),
.probe_out30(NLW_inst_probe_out30_UNCONNECTED[0]),
.probe_out31(NLW_inst_probe_out31_UNCONNECTED[0]),
.probe_out32(NLW_inst_probe_out32_UNCONNECTED[0]),
.probe_out33(NLW_inst_probe_out33_UNCONNECTED[0]),
.probe_out34(NLW_inst_probe_out34_UNCONNECTED[0]),
.probe_out35(NLW_inst_probe_out35_UNCONNECTED[0]),
.probe_out36(NLW_inst_probe_out36_UNCONNECTED[0]),
.probe_out37(NLW_inst_probe_out37_UNCONNECTED[0]),
.probe_out38(NLW_inst_probe_out38_UNCONNECTED[0]),
.probe_out39(NLW_inst_probe_out39_UNCONNECTED[0]),
.probe_out4(NLW_inst_probe_out4_UNCONNECTED[0]),
.probe_out40(NLW_inst_probe_out40_UNCONNECTED[0]),
.probe_out41(NLW_inst_probe_out41_UNCONNECTED[0]),
.probe_out42(NLW_inst_probe_out42_UNCONNECTED[0]),
.probe_out43(NLW_inst_probe_out43_UNCONNECTED[0]),
.probe_out44(NLW_inst_probe_out44_UNCONNECTED[0]),
.probe_out45(NLW_inst_probe_out45_UNCONNECTED[0]),
.probe_out46(NLW_inst_probe_out46_UNCONNECTED[0]),
.probe_out47(NLW_inst_probe_out47_UNCONNECTED[0]),
.probe_out48(NLW_inst_probe_out48_UNCONNECTED[0]),
.probe_out49(NLW_inst_probe_out49_UNCONNECTED[0]),
.probe_out5(NLW_inst_probe_out5_UNCONNECTED[0]),
.probe_out50(NLW_inst_probe_out50_UNCONNECTED[0]),
.probe_out51(NLW_inst_probe_out51_UNCONNECTED[0]),
.probe_out52(NLW_inst_probe_out52_UNCONNECTED[0]),
.probe_out53(NLW_inst_probe_out53_UNCONNECTED[0]),
.probe_out54(NLW_inst_probe_out54_UNCONNECTED[0]),
.probe_out55(NLW_inst_probe_out55_UNCONNECTED[0]),
.probe_out56(NLW_inst_probe_out56_UNCONNECTED[0]),
.probe_out57(NLW_inst_probe_out57_UNCONNECTED[0]),
.probe_out58(NLW_inst_probe_out58_UNCONNECTED[0]),
.probe_out59(NLW_inst_probe_out59_UNCONNECTED[0]),
.probe_out6(NLW_inst_probe_out6_UNCONNECTED[0]),
.probe_out60(NLW_inst_probe_out60_UNCONNECTED[0]),
.probe_out61(NLW_inst_probe_out61_UNCONNECTED[0]),
.probe_out62(NLW_inst_probe_out62_UNCONNECTED[0]),
.probe_out63(NLW_inst_probe_out63_UNCONNECTED[0]),
.probe_out64(NLW_inst_probe_out64_UNCONNECTED[0]),
.probe_out65(NLW_inst_probe_out65_UNCONNECTED[0]),
.probe_out66(NLW_inst_probe_out66_UNCONNECTED[0]),
.probe_out67(NLW_inst_probe_out67_UNCONNECTED[0]),
.probe_out68(NLW_inst_probe_out68_UNCONNECTED[0]),
.probe_out69(NLW_inst_probe_out69_UNCONNECTED[0]),
.probe_out7(NLW_inst_probe_out7_UNCONNECTED[0]),
.probe_out70(NLW_inst_probe_out70_UNCONNECTED[0]),
.probe_out71(NLW_inst_probe_out71_UNCONNECTED[0]),
.probe_out72(NLW_inst_probe_out72_UNCONNECTED[0]),
.probe_out73(NLW_inst_probe_out73_UNCONNECTED[0]),
.probe_out74(NLW_inst_probe_out74_UNCONNECTED[0]),
.probe_out75(NLW_inst_probe_out75_UNCONNECTED[0]),
.probe_out76(NLW_inst_probe_out76_UNCONNECTED[0]),
.probe_out77(NLW_inst_probe_out77_UNCONNECTED[0]),
.probe_out78(NLW_inst_probe_out78_UNCONNECTED[0]),
.probe_out79(NLW_inst_probe_out79_UNCONNECTED[0]),
.probe_out8(NLW_inst_probe_out8_UNCONNECTED[0]),
.probe_out80(NLW_inst_probe_out80_UNCONNECTED[0]),
.probe_out81(NLW_inst_probe_out81_UNCONNECTED[0]),
.probe_out82(NLW_inst_probe_out82_UNCONNECTED[0]),
.probe_out83(NLW_inst_probe_out83_UNCONNECTED[0]),
.probe_out84(NLW_inst_probe_out84_UNCONNECTED[0]),
.probe_out85(NLW_inst_probe_out85_UNCONNECTED[0]),
.probe_out86(NLW_inst_probe_out86_UNCONNECTED[0]),
.probe_out87(NLW_inst_probe_out87_UNCONNECTED[0]),
.probe_out88(NLW_inst_probe_out88_UNCONNECTED[0]),
.probe_out89(NLW_inst_probe_out89_UNCONNECTED[0]),
.probe_out9(NLW_inst_probe_out9_UNCONNECTED[0]),
.probe_out90(NLW_inst_probe_out90_UNCONNECTED[0]),
.probe_out91(NLW_inst_probe_out91_UNCONNECTED[0]),
.probe_out92(NLW_inst_probe_out92_UNCONNECTED[0]),
.probe_out93(NLW_inst_probe_out93_UNCONNECTED[0]),
.probe_out94(NLW_inst_probe_out94_UNCONNECTED[0]),
.probe_out95(NLW_inst_probe_out95_UNCONNECTED[0]),
.probe_out96(NLW_inst_probe_out96_UNCONNECTED[0]),
.probe_out97(NLW_inst_probe_out97_UNCONNECTED[0]),
.probe_out98(NLW_inst_probe_out98_UNCONNECTED[0]),
.probe_out99(NLW_inst_probe_out99_UNCONNECTED[0]),
.sl_iport0({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.sl_oport0(NLW_inst_sl_oport0_UNCONNECTED[16:0]));
endmodule
(* ORIG_REF_NAME = "vio_v3_0_13_decoder" *)
module vio_0_vio_v3_0_13_decoder
(s_drdy_i,
\wr_en_reg[4]_0 ,
\wr_en_reg[4]_1 ,
\wr_en_reg[4]_2 ,
E,
s_do_i,
s_rst_o,
Q,
out,
s_daddr_o,
s_dwe_o,
s_den_o,
\Bus_Data_out_reg[11] );
output s_drdy_i;
output \wr_en_reg[4]_0 ;
output \wr_en_reg[4]_1 ;
output \wr_en_reg[4]_2 ;
output [0:0]E;
output [15:0]s_do_i;
input s_rst_o;
input [15:0]Q;
input out;
input [16:0]s_daddr_o;
input s_dwe_o;
input s_den_o;
input [11:0]\Bus_Data_out_reg[11] ;
wire [11:0]\Bus_Data_out_reg[11] ;
wire [0:0]E;
wire Hold_probe_in;
wire [15:0]Q;
wire clear_int;
wire committ_int;
wire [15:0]data_info_probe_in__67;
wire int_cnt_rst;
wire out;
wire [15:0]probe_out_modified;
wire rd_en_p1;
wire rd_en_p2;
wire [16:0]s_daddr_o;
wire s_den_o;
wire [15:0]s_do_i;
wire s_drdy_i;
wire s_dwe_o;
wire s_rst_o;
wire wr_control_reg;
wire \wr_en[2]_i_1_n_0 ;
wire \wr_en[2]_i_2_n_0 ;
wire \wr_en[4]_i_1_n_0 ;
wire \wr_en[4]_i_6_n_0 ;
wire \wr_en_reg[4]_0 ;
wire \wr_en_reg[4]_1 ;
wire \wr_en_reg[4]_2 ;
wire wr_probe_out_modified;
wire [2:0]xsdb_addr_2_0_p1;
wire [2:0]xsdb_addr_2_0_p2;
wire xsdb_addr_8_p1;
wire xsdb_addr_8_p2;
wire xsdb_drdy_i_1_n_0;
wire xsdb_rd;
wire xsdb_wr;
LUT6 #(
.INIT(64'hAF00AF000FC000C0))
\Bus_data_out[0]_i_1
(.I0(\Bus_Data_out_reg[11] [0]),
.I1(probe_out_modified[0]),
.I2(xsdb_addr_2_0_p2[2]),
.I3(xsdb_addr_2_0_p2[1]),
.I4(committ_int),
.I5(xsdb_addr_2_0_p2[0]),
.O(data_info_probe_in__67[0]));
LUT5 #(
.INIT(32'h88200020))
\Bus_data_out[10]_i_1
(.I0(xsdb_addr_2_0_p2[2]),
.I1(xsdb_addr_2_0_p2[0]),
.I2(probe_out_modified[10]),
.I3(xsdb_addr_2_0_p2[1]),
.I4(\Bus_Data_out_reg[11] [10]),
.O(data_info_probe_in__67[10]));
LUT5 #(
.INIT(32'h88200020))
\Bus_data_out[11]_i_1
(.I0(xsdb_addr_2_0_p2[2]),
.I1(xsdb_addr_2_0_p2[0]),
.I2(probe_out_modified[11]),
.I3(xsdb_addr_2_0_p2[1]),
.I4(\Bus_Data_out_reg[11] [11]),
.O(data_info_probe_in__67[11]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT4 #(
.INIT(16'h0020))
\Bus_data_out[12]_i_1
(.I0(xsdb_addr_2_0_p2[2]),
.I1(xsdb_addr_2_0_p2[1]),
.I2(probe_out_modified[12]),
.I3(xsdb_addr_2_0_p2[0]),
.O(data_info_probe_in__67[12]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT4 #(
.INIT(16'h0020))
\Bus_data_out[13]_i_1
(.I0(xsdb_addr_2_0_p2[2]),
.I1(xsdb_addr_2_0_p2[1]),
.I2(probe_out_modified[13]),
.I3(xsdb_addr_2_0_p2[0]),
.O(data_info_probe_in__67[13]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT4 #(
.INIT(16'h0020))
\Bus_data_out[14]_i_1
(.I0(xsdb_addr_2_0_p2[2]),
.I1(xsdb_addr_2_0_p2[1]),
.I2(probe_out_modified[14]),
.I3(xsdb_addr_2_0_p2[0]),
.O(data_info_probe_in__67[14]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT4 #(
.INIT(16'h0020))
\Bus_data_out[15]_i_1
(.I0(xsdb_addr_2_0_p2[2]),
.I1(xsdb_addr_2_0_p2[1]),
.I2(probe_out_modified[15]),
.I3(xsdb_addr_2_0_p2[0]),
.O(data_info_probe_in__67[15]));
LUT6 #(
.INIT(64'hA0000FC0A00000C0))
\Bus_data_out[1]_i_1
(.I0(\Bus_Data_out_reg[11] [1]),
.I1(probe_out_modified[1]),
.I2(xsdb_addr_2_0_p2[2]),
.I3(xsdb_addr_2_0_p2[1]),
.I4(xsdb_addr_2_0_p2[0]),
.I5(clear_int),
.O(data_info_probe_in__67[1]));
LUT6 #(
.INIT(64'hA0A000000F00CFCF))
\Bus_data_out[2]_i_1
(.I0(\Bus_Data_out_reg[11] [2]),
.I1(probe_out_modified[2]),
.I2(xsdb_addr_2_0_p2[2]),
.I3(int_cnt_rst),
.I4(xsdb_addr_2_0_p2[1]),
.I5(xsdb_addr_2_0_p2[0]),
.O(data_info_probe_in__67[2]));
LUT5 #(
.INIT(32'h88200020))
\Bus_data_out[3]_i_1
(.I0(xsdb_addr_2_0_p2[2]),
.I1(xsdb_addr_2_0_p2[0]),
.I2(probe_out_modified[3]),
.I3(xsdb_addr_2_0_p2[1]),
.I4(\Bus_Data_out_reg[11] [3]),
.O(data_info_probe_in__67[3]));
LUT5 #(
.INIT(32'h88200020))
\Bus_data_out[4]_i_1
(.I0(xsdb_addr_2_0_p2[2]),
.I1(xsdb_addr_2_0_p2[0]),
.I2(probe_out_modified[4]),
.I3(xsdb_addr_2_0_p2[1]),
.I4(\Bus_Data_out_reg[11] [4]),
.O(data_info_probe_in__67[4]));
LUT5 #(
.INIT(32'h88200020))
\Bus_data_out[5]_i_1
(.I0(xsdb_addr_2_0_p2[2]),
.I1(xsdb_addr_2_0_p2[0]),
.I2(probe_out_modified[5]),
.I3(xsdb_addr_2_0_p2[1]),
.I4(\Bus_Data_out_reg[11] [5]),
.O(data_info_probe_in__67[5]));
LUT5 #(
.INIT(32'h88200020))
\Bus_data_out[6]_i_1
(.I0(xsdb_addr_2_0_p2[2]),
.I1(xsdb_addr_2_0_p2[0]),
.I2(probe_out_modified[6]),
.I3(xsdb_addr_2_0_p2[1]),
.I4(\Bus_Data_out_reg[11] [6]),
.O(data_info_probe_in__67[6]));
LUT5 #(
.INIT(32'h88200020))
\Bus_data_out[7]_i_1
(.I0(xsdb_addr_2_0_p2[2]),
.I1(xsdb_addr_2_0_p2[0]),
.I2(probe_out_modified[7]),
.I3(xsdb_addr_2_0_p2[1]),
.I4(\Bus_Data_out_reg[11] [7]),
.O(data_info_probe_in__67[7]));
LUT5 #(
.INIT(32'h88200020))
\Bus_data_out[8]_i_1
(.I0(xsdb_addr_2_0_p2[2]),
.I1(xsdb_addr_2_0_p2[0]),
.I2(probe_out_modified[8]),
.I3(xsdb_addr_2_0_p2[1]),
.I4(\Bus_Data_out_reg[11] [8]),
.O(data_info_probe_in__67[8]));
LUT5 #(
.INIT(32'h88200020))
\Bus_data_out[9]_i_1
(.I0(xsdb_addr_2_0_p2[2]),
.I1(xsdb_addr_2_0_p2[0]),
.I2(probe_out_modified[9]),
.I3(xsdb_addr_2_0_p2[1]),
.I4(\Bus_Data_out_reg[11] [9]),
.O(data_info_probe_in__67[9]));
FDRE \Bus_data_out_reg[0]
(.C(out),
.CE(1'b1),
.D(data_info_probe_in__67[0]),
.Q(s_do_i[0]),
.R(xsdb_addr_8_p2));
FDRE \Bus_data_out_reg[10]
(.C(out),
.CE(1'b1),
.D(data_info_probe_in__67[10]),
.Q(s_do_i[10]),
.R(xsdb_addr_8_p2));
FDRE \Bus_data_out_reg[11]
(.C(out),
.CE(1'b1),
.D(data_info_probe_in__67[11]),
.Q(s_do_i[11]),
.R(xsdb_addr_8_p2));
FDRE \Bus_data_out_reg[12]
(.C(out),
.CE(1'b1),
.D(data_info_probe_in__67[12]),
.Q(s_do_i[12]),
.R(xsdb_addr_8_p2));
FDRE \Bus_data_out_reg[13]
(.C(out),
.CE(1'b1),
.D(data_info_probe_in__67[13]),
.Q(s_do_i[13]),
.R(xsdb_addr_8_p2));
FDRE \Bus_data_out_reg[14]
(.C(out),
.CE(1'b1),
.D(data_info_probe_in__67[14]),
.Q(s_do_i[14]),
.R(xsdb_addr_8_p2));
FDRE \Bus_data_out_reg[15]
(.C(out),
.CE(1'b1),
.D(data_info_probe_in__67[15]),
.Q(s_do_i[15]),
.R(xsdb_addr_8_p2));
FDRE \Bus_data_out_reg[1]
(.C(out),
.CE(1'b1),
.D(data_info_probe_in__67[1]),
.Q(s_do_i[1]),
.R(xsdb_addr_8_p2));
FDRE \Bus_data_out_reg[2]
(.C(out),
.CE(1'b1),
.D(data_info_probe_in__67[2]),
.Q(s_do_i[2]),
.R(xsdb_addr_8_p2));
FDRE \Bus_data_out_reg[3]
(.C(out),
.CE(1'b1),
.D(data_info_probe_in__67[3]),
.Q(s_do_i[3]),
.R(xsdb_addr_8_p2));
FDRE \Bus_data_out_reg[4]
(.C(out),
.CE(1'b1),
.D(data_info_probe_in__67[4]),
.Q(s_do_i[4]),
.R(xsdb_addr_8_p2));
FDRE \Bus_data_out_reg[5]
(.C(out),
.CE(1'b1),
.D(data_info_probe_in__67[5]),
.Q(s_do_i[5]),
.R(xsdb_addr_8_p2));
FDRE \Bus_data_out_reg[6]
(.C(out),
.CE(1'b1),
.D(data_info_probe_in__67[6]),
.Q(s_do_i[6]),
.R(xsdb_addr_8_p2));
FDRE \Bus_data_out_reg[7]
(.C(out),
.CE(1'b1),
.D(data_info_probe_in__67[7]),
.Q(s_do_i[7]),
.R(xsdb_addr_8_p2));
FDRE \Bus_data_out_reg[8]
(.C(out),
.CE(1'b1),
.D(data_info_probe_in__67[8]),
.Q(s_do_i[8]),
.R(xsdb_addr_8_p2));
FDRE \Bus_data_out_reg[9]
(.C(out),
.CE(1'b1),
.D(data_info_probe_in__67[9]),
.Q(s_do_i[9]),
.R(xsdb_addr_8_p2));
FDRE Hold_probe_in_reg
(.C(out),
.CE(wr_control_reg),
.D(Q[3]),
.Q(Hold_probe_in),
.R(s_rst_o));
FDRE clear_int_reg
(.C(out),
.CE(wr_control_reg),
.D(Q[1]),
.Q(clear_int),
.R(s_rst_o));
FDRE committ_int_reg
(.C(out),
.CE(wr_control_reg),
.D(Q[0]),
.Q(committ_int),
.R(s_rst_o));
FDRE int_cnt_rst_reg
(.C(out),
.CE(wr_control_reg),
.D(Q[2]),
.Q(int_cnt_rst),
.R(s_rst_o));
LUT1 #(
.INIT(2'h1))
\probe_in_reg[3]_i_1
(.I0(Hold_probe_in),
.O(E));
FDRE \probe_out_modified_reg[0]
(.C(out),
.CE(wr_probe_out_modified),
.D(Q[0]),
.Q(probe_out_modified[0]),
.R(clear_int));
FDRE \probe_out_modified_reg[10]
(.C(out),
.CE(wr_probe_out_modified),
.D(Q[10]),
.Q(probe_out_modified[10]),
.R(clear_int));
FDRE \probe_out_modified_reg[11]
(.C(out),
.CE(wr_probe_out_modified),
.D(Q[11]),
.Q(probe_out_modified[11]),
.R(clear_int));
FDRE \probe_out_modified_reg[12]
(.C(out),
.CE(wr_probe_out_modified),
.D(Q[12]),
.Q(probe_out_modified[12]),
.R(clear_int));
FDRE \probe_out_modified_reg[13]
(.C(out),
.CE(wr_probe_out_modified),
.D(Q[13]),
.Q(probe_out_modified[13]),
.R(clear_int));
FDRE \probe_out_modified_reg[14]
(.C(out),
.CE(wr_probe_out_modified),
.D(Q[14]),
.Q(probe_out_modified[14]),
.R(clear_int));
FDRE \probe_out_modified_reg[15]
(.C(out),
.CE(wr_probe_out_modified),
.D(Q[15]),
.Q(probe_out_modified[15]),
.R(clear_int));
FDRE \probe_out_modified_reg[1]
(.C(out),
.CE(wr_probe_out_modified),
.D(Q[1]),
.Q(probe_out_modified[1]),
.R(clear_int));
FDRE \probe_out_modified_reg[2]
(.C(out),
.CE(wr_probe_out_modified),
.D(Q[2]),
.Q(probe_out_modified[2]),
.R(clear_int));
FDRE \probe_out_modified_reg[3]
(.C(out),
.CE(wr_probe_out_modified),
.D(Q[3]),
.Q(probe_out_modified[3]),
.R(clear_int));
FDRE \probe_out_modified_reg[4]
(.C(out),
.CE(wr_probe_out_modified),
.D(Q[4]),
.Q(probe_out_modified[4]),
.R(clear_int));
FDRE \probe_out_modified_reg[5]
(.C(out),
.CE(wr_probe_out_modified),
.D(Q[5]),
.Q(probe_out_modified[5]),
.R(clear_int));
FDRE \probe_out_modified_reg[6]
(.C(out),
.CE(wr_probe_out_modified),
.D(Q[6]),
.Q(probe_out_modified[6]),
.R(clear_int));
FDRE \probe_out_modified_reg[7]
(.C(out),
.CE(wr_probe_out_modified),
.D(Q[7]),
.Q(probe_out_modified[7]),
.R(clear_int));
FDRE \probe_out_modified_reg[8]
(.C(out),
.CE(wr_probe_out_modified),
.D(Q[8]),
.Q(probe_out_modified[8]),
.R(clear_int));
FDRE \probe_out_modified_reg[9]
(.C(out),
.CE(wr_probe_out_modified),
.D(Q[9]),
.Q(probe_out_modified[9]),
.R(clear_int));
LUT2 #(
.INIT(4'h2))
rd_en_p1_i_1
(.I0(s_den_o),
.I1(s_dwe_o),
.O(xsdb_rd));
FDRE rd_en_p1_reg
(.C(out),
.CE(1'b1),
.D(xsdb_rd),
.Q(rd_en_p1),
.R(s_rst_o));
FDRE rd_en_p2_reg
(.C(out),
.CE(1'b1),
.D(rd_en_p1),
.Q(rd_en_p2),
.R(s_rst_o));
LUT6 #(
.INIT(64'h0000000000000002))
\wr_en[2]_i_1
(.I0(xsdb_wr),
.I1(s_daddr_o[2]),
.I2(\wr_en_reg[4]_0 ),
.I3(\wr_en_reg[4]_2 ),
.I4(\wr_en_reg[4]_1 ),
.I5(\wr_en[2]_i_2_n_0 ),
.O(\wr_en[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT2 #(
.INIT(4'hB))
\wr_en[2]_i_2
(.I0(s_daddr_o[0]),
.I1(s_daddr_o[1]),
.O(\wr_en[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000000000020000))
\wr_en[4]_i_1
(.I0(xsdb_wr),
.I1(\wr_en_reg[4]_0 ),
.I2(\wr_en_reg[4]_2 ),
.I3(\wr_en_reg[4]_1 ),
.I4(s_daddr_o[2]),
.I5(\wr_en[4]_i_6_n_0 ),
.O(\wr_en[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT2 #(
.INIT(4'h8))
\wr_en[4]_i_2
(.I0(s_den_o),
.I1(s_dwe_o),
.O(xsdb_wr));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\wr_en[4]_i_3
(.I0(s_daddr_o[15]),
.I1(s_daddr_o[16]),
.I2(s_daddr_o[13]),
.I3(s_daddr_o[14]),
.I4(s_daddr_o[4]),
.I5(s_daddr_o[3]),
.O(\wr_en_reg[4]_0 ));
LUT4 #(
.INIT(16'hFFFE))
\wr_en[4]_i_4
(.I0(s_daddr_o[6]),
.I1(s_daddr_o[5]),
.I2(s_daddr_o[8]),
.I3(s_daddr_o[7]),
.O(\wr_en_reg[4]_2 ));
LUT4 #(
.INIT(16'hFFFE))
\wr_en[4]_i_5
(.I0(s_daddr_o[10]),
.I1(s_daddr_o[9]),
.I2(s_daddr_o[12]),
.I3(s_daddr_o[11]),
.O(\wr_en_reg[4]_1 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT2 #(
.INIT(4'hE))
\wr_en[4]_i_6
(.I0(s_daddr_o[0]),
.I1(s_daddr_o[1]),
.O(\wr_en[4]_i_6_n_0 ));
FDRE \wr_en_reg[2]
(.C(out),
.CE(1'b1),
.D(\wr_en[2]_i_1_n_0 ),
.Q(wr_control_reg),
.R(1'b0));
FDRE \wr_en_reg[4]
(.C(out),
.CE(1'b1),
.D(\wr_en[4]_i_1_n_0 ),
.Q(wr_probe_out_modified),
.R(1'b0));
FDRE \xsdb_addr_2_0_p1_reg[0]
(.C(out),
.CE(1'b1),
.D(s_daddr_o[0]),
.Q(xsdb_addr_2_0_p1[0]),
.R(1'b0));
FDRE \xsdb_addr_2_0_p1_reg[1]
(.C(out),
.CE(1'b1),
.D(s_daddr_o[1]),
.Q(xsdb_addr_2_0_p1[1]),
.R(1'b0));
FDRE \xsdb_addr_2_0_p1_reg[2]
(.C(out),
.CE(1'b1),
.D(s_daddr_o[2]),
.Q(xsdb_addr_2_0_p1[2]),
.R(1'b0));
FDRE \xsdb_addr_2_0_p2_reg[0]
(.C(out),
.CE(1'b1),
.D(xsdb_addr_2_0_p1[0]),
.Q(xsdb_addr_2_0_p2[0]),
.R(1'b0));
FDRE \xsdb_addr_2_0_p2_reg[1]
(.C(out),
.CE(1'b1),
.D(xsdb_addr_2_0_p1[1]),
.Q(xsdb_addr_2_0_p2[1]),
.R(1'b0));
FDRE \xsdb_addr_2_0_p2_reg[2]
(.C(out),
.CE(1'b1),
.D(xsdb_addr_2_0_p1[2]),
.Q(xsdb_addr_2_0_p2[2]),
.R(1'b0));
FDRE xsdb_addr_8_p1_reg
(.C(out),
.CE(1'b1),
.D(s_daddr_o[8]),
.Q(xsdb_addr_8_p1),
.R(1'b0));
FDRE xsdb_addr_8_p2_reg
(.C(out),
.CE(1'b1),
.D(xsdb_addr_8_p1),
.Q(xsdb_addr_8_p2),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'hF8))
xsdb_drdy_i_1
(.I0(s_dwe_o),
.I1(s_den_o),
.I2(rd_en_p2),
.O(xsdb_drdy_i_1_n_0));
FDRE xsdb_drdy_reg
(.C(out),
.CE(1'b1),
.D(xsdb_drdy_i_1_n_0),
.Q(s_drdy_i),
.R(s_rst_o));
endmodule
(* ORIG_REF_NAME = "vio_v3_0_13_probe_in_one" *)
module vio_0_vio_v3_0_13_probe_in_one
(Q,
out,
\wr_en[4]_i_3 ,
\wr_en[4]_i_4 ,
\wr_en[4]_i_5 ,
s_daddr_o,
s_dwe_o,
s_den_o,
E,
D,
clk,
s_rst_o);
output [11:0]Q;
input out;
input \wr_en[4]_i_3 ;
input \wr_en[4]_i_4 ;
input \wr_en[4]_i_5 ;
input [2:0]s_daddr_o;
input s_dwe_o;
input s_den_o;
input [0:0]E;
input [3:0]D;
input clk;
input s_rst_o;
wire [3:0]D;
wire \DECODER_INST/rd_en_int_7 ;
wire [0:0]E;
wire [11:0]Q;
wire Read_int;
wire Read_int_i_2_n_0;
wire clk;
(* async_reg = "true" *) wire [3:0]data_int_sync1;
(* async_reg = "true" *) wire [3:0]data_int_sync2;
wire \dn_activity[0]_i_1_n_0 ;
wire \dn_activity[1]_i_1_n_0 ;
wire \dn_activity[2]_i_1_n_0 ;
wire \dn_activity[3]_i_1_n_0 ;
wire \dn_activity_reg_n_0_[0] ;
wire \dn_activity_reg_n_0_[3] ;
wire out;
wire p_6_in;
wire p_9_in;
(* DONT_TOUCH *) wire [3:0]probe_in_reg;
(* MAX_FANOUT = "200" *) (* RTL_MAX_FANOUT = "found" *) wire read_done;
wire read_done_i_1_n_0;
wire [2:0]s_daddr_o;
wire s_den_o;
wire s_dwe_o;
wire s_rst_o;
wire \up_activity[0]_i_1_n_0 ;
wire \up_activity[1]_i_1_n_0 ;
wire \up_activity[2]_i_1_n_0 ;
wire \up_activity[3]_i_1_n_0 ;
wire \up_activity_reg_n_0_[0] ;
wire \up_activity_reg_n_0_[1] ;
wire \up_activity_reg_n_0_[2] ;
wire \up_activity_reg_n_0_[3] ;
wire \wr_en[4]_i_3 ;
wire \wr_en[4]_i_4 ;
wire \wr_en[4]_i_5 ;
FDRE \Bus_Data_out_reg[0]
(.C(out),
.CE(1'b1),
.D(data_int_sync2[0]),
.Q(Q[0]),
.R(1'b0));
FDRE \Bus_Data_out_reg[10]
(.C(out),
.CE(1'b1),
.D(p_9_in),
.Q(Q[10]),
.R(1'b0));
FDRE \Bus_Data_out_reg[11]
(.C(out),
.CE(1'b1),
.D(\dn_activity_reg_n_0_[3] ),
.Q(Q[11]),
.R(1'b0));
FDRE \Bus_Data_out_reg[1]
(.C(out),
.CE(1'b1),
.D(data_int_sync2[1]),
.Q(Q[1]),
.R(1'b0));
FDRE \Bus_Data_out_reg[2]
(.C(out),
.CE(1'b1),
.D(data_int_sync2[2]),
.Q(Q[2]),
.R(1'b0));
FDRE \Bus_Data_out_reg[3]
(.C(out),
.CE(1'b1),
.D(data_int_sync2[3]),
.Q(Q[3]),
.R(1'b0));
FDRE \Bus_Data_out_reg[4]
(.C(out),
.CE(1'b1),
.D(\up_activity_reg_n_0_[0] ),
.Q(Q[4]),
.R(1'b0));
FDRE \Bus_Data_out_reg[5]
(.C(out),
.CE(1'b1),
.D(\up_activity_reg_n_0_[1] ),
.Q(Q[5]),
.R(1'b0));
FDRE \Bus_Data_out_reg[6]
(.C(out),
.CE(1'b1),
.D(\up_activity_reg_n_0_[2] ),
.Q(Q[6]),
.R(1'b0));
FDRE \Bus_Data_out_reg[7]
(.C(out),
.CE(1'b1),
.D(\up_activity_reg_n_0_[3] ),
.Q(Q[7]),
.R(1'b0));
FDRE \Bus_Data_out_reg[8]
(.C(out),
.CE(1'b1),
.D(\dn_activity_reg_n_0_[0] ),
.Q(Q[8]),
.R(1'b0));
FDRE \Bus_Data_out_reg[9]
(.C(out),
.CE(1'b1),
.D(p_6_in),
.Q(Q[9]),
.R(1'b0));
LUT4 #(
.INIT(16'h0002))
Read_int_i_1
(.I0(Read_int_i_2_n_0),
.I1(\wr_en[4]_i_3 ),
.I2(\wr_en[4]_i_4 ),
.I3(\wr_en[4]_i_5 ),
.O(\DECODER_INST/rd_en_int_7 ));
LUT5 #(
.INIT(32'h00800000))
Read_int_i_2
(.I0(s_daddr_o[0]),
.I1(s_daddr_o[1]),
.I2(s_daddr_o[2]),
.I3(s_dwe_o),
.I4(s_den_o),
.O(Read_int_i_2_n_0));
FDRE Read_int_reg
(.C(out),
.CE(1'b1),
.D(\DECODER_INST/rd_en_int_7 ),
.Q(Read_int),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\data_int_sync1_reg[0]
(.C(out),
.CE(1'b1),
.D(probe_in_reg[0]),
.Q(data_int_sync1[0]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\data_int_sync1_reg[1]
(.C(out),
.CE(1'b1),
.D(probe_in_reg[1]),
.Q(data_int_sync1[1]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\data_int_sync1_reg[2]
(.C(out),
.CE(1'b1),
.D(probe_in_reg[2]),
.Q(data_int_sync1[2]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\data_int_sync1_reg[3]
(.C(out),
.CE(1'b1),
.D(probe_in_reg[3]),
.Q(data_int_sync1[3]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\data_int_sync2_reg[0]
(.C(out),
.CE(1'b1),
.D(data_int_sync1[0]),
.Q(data_int_sync2[0]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\data_int_sync2_reg[1]
(.C(out),
.CE(1'b1),
.D(data_int_sync1[1]),
.Q(data_int_sync2[1]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\data_int_sync2_reg[2]
(.C(out),
.CE(1'b1),
.D(data_int_sync1[2]),
.Q(data_int_sync2[2]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\data_int_sync2_reg[3]
(.C(out),
.CE(1'b1),
.D(data_int_sync1[3]),
.Q(data_int_sync2[3]),
.R(1'b0));
LUT3 #(
.INIT(8'hBA))
\dn_activity[0]_i_1
(.I0(\dn_activity_reg_n_0_[0] ),
.I1(data_int_sync1[0]),
.I2(data_int_sync2[0]),
.O(\dn_activity[0]_i_1_n_0 ));
LUT3 #(
.INIT(8'hBA))
\dn_activity[1]_i_1
(.I0(p_6_in),
.I1(data_int_sync1[1]),
.I2(data_int_sync2[1]),
.O(\dn_activity[1]_i_1_n_0 ));
LUT3 #(
.INIT(8'hBA))
\dn_activity[2]_i_1
(.I0(p_9_in),
.I1(data_int_sync1[2]),
.I2(data_int_sync2[2]),
.O(\dn_activity[2]_i_1_n_0 ));
LUT3 #(
.INIT(8'hBA))
\dn_activity[3]_i_1
(.I0(\dn_activity_reg_n_0_[3] ),
.I1(data_int_sync1[3]),
.I2(data_int_sync2[3]),
.O(\dn_activity[3]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\dn_activity_reg[0]
(.C(out),
.CE(1'b1),
.D(\dn_activity[0]_i_1_n_0 ),
.Q(\dn_activity_reg_n_0_[0] ),
.R(read_done));
FDRE #(
.INIT(1'b0))
\dn_activity_reg[1]
(.C(out),
.CE(1'b1),
.D(\dn_activity[1]_i_1_n_0 ),
.Q(p_6_in),
.R(read_done));
FDRE #(
.INIT(1'b0))
\dn_activity_reg[2]
(.C(out),
.CE(1'b1),
.D(\dn_activity[2]_i_1_n_0 ),
.Q(p_9_in),
.R(read_done));
FDRE #(
.INIT(1'b0))
\dn_activity_reg[3]
(.C(out),
.CE(1'b1),
.D(\dn_activity[3]_i_1_n_0 ),
.Q(\dn_activity_reg_n_0_[3] ),
.R(read_done));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\probe_in_reg_reg[0]
(.C(clk),
.CE(E),
.D(D[0]),
.Q(probe_in_reg[0]),
.R(1'b0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\probe_in_reg_reg[1]
(.C(clk),
.CE(E),
.D(D[1]),
.Q(probe_in_reg[1]),
.R(1'b0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\probe_in_reg_reg[2]
(.C(clk),
.CE(E),
.D(D[2]),
.Q(probe_in_reg[2]),
.R(1'b0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\probe_in_reg_reg[3]
(.C(clk),
.CE(E),
.D(D[3]),
.Q(probe_in_reg[3]),
.R(1'b0));
LUT3 #(
.INIT(8'h02))
read_done_i_1
(.I0(Read_int),
.I1(read_done),
.I2(s_rst_o),
.O(read_done_i_1_n_0));
(* RTL_MAX_FANOUT = "found" *)
FDRE read_done_reg
(.C(out),
.CE(1'b1),
.D(read_done_i_1_n_0),
.Q(read_done),
.R(1'b0));
LUT3 #(
.INIT(8'hBA))
\up_activity[0]_i_1
(.I0(\up_activity_reg_n_0_[0] ),
.I1(data_int_sync2[0]),
.I2(data_int_sync1[0]),
.O(\up_activity[0]_i_1_n_0 ));
LUT3 #(
.INIT(8'hBA))
\up_activity[1]_i_1
(.I0(\up_activity_reg_n_0_[1] ),
.I1(data_int_sync2[1]),
.I2(data_int_sync1[1]),
.O(\up_activity[1]_i_1_n_0 ));
LUT3 #(
.INIT(8'hBA))
\up_activity[2]_i_1
(.I0(\up_activity_reg_n_0_[2] ),
.I1(data_int_sync2[2]),
.I2(data_int_sync1[2]),
.O(\up_activity[2]_i_1_n_0 ));
LUT3 #(
.INIT(8'hBA))
\up_activity[3]_i_1
(.I0(\up_activity_reg_n_0_[3] ),
.I1(data_int_sync2[3]),
.I2(data_int_sync1[3]),
.O(\up_activity[3]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\up_activity_reg[0]
(.C(out),
.CE(1'b1),
.D(\up_activity[0]_i_1_n_0 ),
.Q(\up_activity_reg_n_0_[0] ),
.R(read_done));
FDRE #(
.INIT(1'b0))
\up_activity_reg[1]
(.C(out),
.CE(1'b1),
.D(\up_activity[1]_i_1_n_0 ),
.Q(\up_activity_reg_n_0_[1] ),
.R(read_done));
FDRE #(
.INIT(1'b0))
\up_activity_reg[2]
(.C(out),
.CE(1'b1),
.D(\up_activity[2]_i_1_n_0 ),
.Q(\up_activity_reg_n_0_[2] ),
.R(read_done));
FDRE #(
.INIT(1'b0))
\up_activity_reg[3]
(.C(out),
.CE(1'b1),
.D(\up_activity[3]_i_1_n_0 ),
.Q(\up_activity_reg_n_0_[3] ),
.R(read_done));
endmodule
(* C_BUILD_REVISION = "0" *) (* C_BUS_ADDR_WIDTH = "17" *) (* C_BUS_DATA_WIDTH = "16" *)
(* C_CORE_INFO1 = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) (* C_CORE_INFO2 = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) (* C_CORE_MAJOR_VER = "2" *)
(* C_CORE_MINOR_ALPHA_VER = "97" *) (* C_CORE_MINOR_VER = "0" *) (* C_CORE_TYPE = "2" *)
(* C_CSE_DRV_VER = "1" *) (* C_EN_PROBE_IN_ACTIVITY = "1" *) (* C_EN_SYNCHRONIZATION = "1" *)
(* C_MAJOR_VERSION = "2013" *) (* C_MAX_NUM_PROBE = "256" *) (* C_MAX_WIDTH_PER_PROBE = "256" *)
(* C_MINOR_VERSION = "1" *) (* C_NEXT_SLAVE = "0" *) (* C_NUM_PROBE_IN = "4" *)
(* C_NUM_PROBE_OUT = "0" *) (* C_PIPE_IFACE = "0" *) (* C_PROBE_IN0_WIDTH = "1" *)
(* C_PROBE_IN100_WIDTH = "1" *) (* C_PROBE_IN101_WIDTH = "1" *) (* C_PROBE_IN102_WIDTH = "1" *)
(* C_PROBE_IN103_WIDTH = "1" *) (* C_PROBE_IN104_WIDTH = "1" *) (* C_PROBE_IN105_WIDTH = "1" *)
(* C_PROBE_IN106_WIDTH = "1" *) (* C_PROBE_IN107_WIDTH = "1" *) (* C_PROBE_IN108_WIDTH = "1" *)
(* C_PROBE_IN109_WIDTH = "1" *) (* C_PROBE_IN10_WIDTH = "1" *) (* C_PROBE_IN110_WIDTH = "1" *)
(* C_PROBE_IN111_WIDTH = "1" *) (* C_PROBE_IN112_WIDTH = "1" *) (* C_PROBE_IN113_WIDTH = "1" *)
(* C_PROBE_IN114_WIDTH = "1" *) (* C_PROBE_IN115_WIDTH = "1" *) (* C_PROBE_IN116_WIDTH = "1" *)
(* C_PROBE_IN117_WIDTH = "1" *) (* C_PROBE_IN118_WIDTH = "1" *) (* C_PROBE_IN119_WIDTH = "1" *)
(* C_PROBE_IN11_WIDTH = "1" *) (* C_PROBE_IN120_WIDTH = "1" *) (* C_PROBE_IN121_WIDTH = "1" *)
(* C_PROBE_IN122_WIDTH = "1" *) (* C_PROBE_IN123_WIDTH = "1" *) (* C_PROBE_IN124_WIDTH = "1" *)
(* C_PROBE_IN125_WIDTH = "1" *) (* C_PROBE_IN126_WIDTH = "1" *) (* C_PROBE_IN127_WIDTH = "1" *)
(* C_PROBE_IN128_WIDTH = "1" *) (* C_PROBE_IN129_WIDTH = "1" *) (* C_PROBE_IN12_WIDTH = "1" *)
(* C_PROBE_IN130_WIDTH = "1" *) (* C_PROBE_IN131_WIDTH = "1" *) (* C_PROBE_IN132_WIDTH = "1" *)
(* C_PROBE_IN133_WIDTH = "1" *) (* C_PROBE_IN134_WIDTH = "1" *) (* C_PROBE_IN135_WIDTH = "1" *)
(* C_PROBE_IN136_WIDTH = "1" *) (* C_PROBE_IN137_WIDTH = "1" *) (* C_PROBE_IN138_WIDTH = "1" *)
(* C_PROBE_IN139_WIDTH = "1" *) (* C_PROBE_IN13_WIDTH = "1" *) (* C_PROBE_IN140_WIDTH = "1" *)
(* C_PROBE_IN141_WIDTH = "1" *) (* C_PROBE_IN142_WIDTH = "1" *) (* C_PROBE_IN143_WIDTH = "1" *)
(* C_PROBE_IN144_WIDTH = "1" *) (* C_PROBE_IN145_WIDTH = "1" *) (* C_PROBE_IN146_WIDTH = "1" *)
(* C_PROBE_IN147_WIDTH = "1" *) (* C_PROBE_IN148_WIDTH = "1" *) (* C_PROBE_IN149_WIDTH = "1" *)
(* C_PROBE_IN14_WIDTH = "1" *) (* C_PROBE_IN150_WIDTH = "1" *) (* C_PROBE_IN151_WIDTH = "1" *)
(* C_PROBE_IN152_WIDTH = "1" *) (* C_PROBE_IN153_WIDTH = "1" *) (* C_PROBE_IN154_WIDTH = "1" *)
(* C_PROBE_IN155_WIDTH = "1" *) (* C_PROBE_IN156_WIDTH = "1" *) (* C_PROBE_IN157_WIDTH = "1" *)
(* C_PROBE_IN158_WIDTH = "1" *) (* C_PROBE_IN159_WIDTH = "1" *) (* C_PROBE_IN15_WIDTH = "1" *)
(* C_PROBE_IN160_WIDTH = "1" *) (* C_PROBE_IN161_WIDTH = "1" *) (* C_PROBE_IN162_WIDTH = "1" *)
(* C_PROBE_IN163_WIDTH = "1" *) (* C_PROBE_IN164_WIDTH = "1" *) (* C_PROBE_IN165_WIDTH = "1" *)
(* C_PROBE_IN166_WIDTH = "1" *) (* C_PROBE_IN167_WIDTH = "1" *) (* C_PROBE_IN168_WIDTH = "1" *)
(* C_PROBE_IN169_WIDTH = "1" *) (* C_PROBE_IN16_WIDTH = "1" *) (* C_PROBE_IN170_WIDTH = "1" *)
(* C_PROBE_IN171_WIDTH = "1" *) (* C_PROBE_IN172_WIDTH = "1" *) (* C_PROBE_IN173_WIDTH = "1" *)
(* C_PROBE_IN174_WIDTH = "1" *) (* C_PROBE_IN175_WIDTH = "1" *) (* C_PROBE_IN176_WIDTH = "1" *)
(* C_PROBE_IN177_WIDTH = "1" *) (* C_PROBE_IN178_WIDTH = "1" *) (* C_PROBE_IN179_WIDTH = "1" *)
(* C_PROBE_IN17_WIDTH = "1" *) (* C_PROBE_IN180_WIDTH = "1" *) (* C_PROBE_IN181_WIDTH = "1" *)
(* C_PROBE_IN182_WIDTH = "1" *) (* C_PROBE_IN183_WIDTH = "1" *) (* C_PROBE_IN184_WIDTH = "1" *)
(* C_PROBE_IN185_WIDTH = "1" *) (* C_PROBE_IN186_WIDTH = "1" *) (* C_PROBE_IN187_WIDTH = "1" *)
(* C_PROBE_IN188_WIDTH = "1" *) (* C_PROBE_IN189_WIDTH = "1" *) (* C_PROBE_IN18_WIDTH = "1" *)
(* C_PROBE_IN190_WIDTH = "1" *) (* C_PROBE_IN191_WIDTH = "1" *) (* C_PROBE_IN192_WIDTH = "1" *)
(* C_PROBE_IN193_WIDTH = "1" *) (* C_PROBE_IN194_WIDTH = "1" *) (* C_PROBE_IN195_WIDTH = "1" *)
(* C_PROBE_IN196_WIDTH = "1" *) (* C_PROBE_IN197_WIDTH = "1" *) (* C_PROBE_IN198_WIDTH = "1" *)
(* C_PROBE_IN199_WIDTH = "1" *) (* C_PROBE_IN19_WIDTH = "1" *) (* C_PROBE_IN1_WIDTH = "1" *)
(* C_PROBE_IN200_WIDTH = "1" *) (* C_PROBE_IN201_WIDTH = "1" *) (* C_PROBE_IN202_WIDTH = "1" *)
(* C_PROBE_IN203_WIDTH = "1" *) (* C_PROBE_IN204_WIDTH = "1" *) (* C_PROBE_IN205_WIDTH = "1" *)
(* C_PROBE_IN206_WIDTH = "1" *) (* C_PROBE_IN207_WIDTH = "1" *) (* C_PROBE_IN208_WIDTH = "1" *)
(* C_PROBE_IN209_WIDTH = "1" *) (* C_PROBE_IN20_WIDTH = "1" *) (* C_PROBE_IN210_WIDTH = "1" *)
(* C_PROBE_IN211_WIDTH = "1" *) (* C_PROBE_IN212_WIDTH = "1" *) (* C_PROBE_IN213_WIDTH = "1" *)
(* C_PROBE_IN214_WIDTH = "1" *) (* C_PROBE_IN215_WIDTH = "1" *) (* C_PROBE_IN216_WIDTH = "1" *)
(* C_PROBE_IN217_WIDTH = "1" *) (* C_PROBE_IN218_WIDTH = "1" *) (* C_PROBE_IN219_WIDTH = "1" *)
(* C_PROBE_IN21_WIDTH = "1" *) (* C_PROBE_IN220_WIDTH = "1" *) (* C_PROBE_IN221_WIDTH = "1" *)
(* C_PROBE_IN222_WIDTH = "1" *) (* C_PROBE_IN223_WIDTH = "1" *) (* C_PROBE_IN224_WIDTH = "1" *)
(* C_PROBE_IN225_WIDTH = "1" *) (* C_PROBE_IN226_WIDTH = "1" *) (* C_PROBE_IN227_WIDTH = "1" *)
(* C_PROBE_IN228_WIDTH = "1" *) (* C_PROBE_IN229_WIDTH = "1" *) (* C_PROBE_IN22_WIDTH = "1" *)
(* C_PROBE_IN230_WIDTH = "1" *) (* C_PROBE_IN231_WIDTH = "1" *) (* C_PROBE_IN232_WIDTH = "1" *)
(* C_PROBE_IN233_WIDTH = "1" *) (* C_PROBE_IN234_WIDTH = "1" *) (* C_PROBE_IN235_WIDTH = "1" *)
(* C_PROBE_IN236_WIDTH = "1" *) (* C_PROBE_IN237_WIDTH = "1" *) (* C_PROBE_IN238_WIDTH = "1" *)
(* C_PROBE_IN239_WIDTH = "1" *) (* C_PROBE_IN23_WIDTH = "1" *) (* C_PROBE_IN240_WIDTH = "1" *)
(* C_PROBE_IN241_WIDTH = "1" *) (* C_PROBE_IN242_WIDTH = "1" *) (* C_PROBE_IN243_WIDTH = "1" *)
(* C_PROBE_IN244_WIDTH = "1" *) (* C_PROBE_IN245_WIDTH = "1" *) (* C_PROBE_IN246_WIDTH = "1" *)
(* C_PROBE_IN247_WIDTH = "1" *) (* C_PROBE_IN248_WIDTH = "1" *) (* C_PROBE_IN249_WIDTH = "1" *)
(* C_PROBE_IN24_WIDTH = "1" *) (* C_PROBE_IN250_WIDTH = "1" *) (* C_PROBE_IN251_WIDTH = "1" *)
(* C_PROBE_IN252_WIDTH = "1" *) (* C_PROBE_IN253_WIDTH = "1" *) (* C_PROBE_IN254_WIDTH = "1" *)
(* C_PROBE_IN255_WIDTH = "1" *) (* C_PROBE_IN25_WIDTH = "1" *) (* C_PROBE_IN26_WIDTH = "1" *)
(* C_PROBE_IN27_WIDTH = "1" *) (* C_PROBE_IN28_WIDTH = "1" *) (* C_PROBE_IN29_WIDTH = "1" *)
(* C_PROBE_IN2_WIDTH = "1" *) (* C_PROBE_IN30_WIDTH = "1" *) (* C_PROBE_IN31_WIDTH = "1" *)
(* C_PROBE_IN32_WIDTH = "1" *) (* C_PROBE_IN33_WIDTH = "1" *) (* C_PROBE_IN34_WIDTH = "1" *)
(* C_PROBE_IN35_WIDTH = "1" *) (* C_PROBE_IN36_WIDTH = "1" *) (* C_PROBE_IN37_WIDTH = "1" *)
(* C_PROBE_IN38_WIDTH = "1" *) (* C_PROBE_IN39_WIDTH = "1" *) (* C_PROBE_IN3_WIDTH = "1" *)
(* C_PROBE_IN40_WIDTH = "1" *) (* C_PROBE_IN41_WIDTH = "1" *) (* C_PROBE_IN42_WIDTH = "1" *)
(* C_PROBE_IN43_WIDTH = "1" *) (* C_PROBE_IN44_WIDTH = "1" *) (* C_PROBE_IN45_WIDTH = "1" *)
(* C_PROBE_IN46_WIDTH = "1" *) (* C_PROBE_IN47_WIDTH = "1" *) (* C_PROBE_IN48_WIDTH = "1" *)
(* C_PROBE_IN49_WIDTH = "1" *) (* C_PROBE_IN4_WIDTH = "1" *) (* C_PROBE_IN50_WIDTH = "1" *)
(* C_PROBE_IN51_WIDTH = "1" *) (* C_PROBE_IN52_WIDTH = "1" *) (* C_PROBE_IN53_WIDTH = "1" *)
(* C_PROBE_IN54_WIDTH = "1" *) (* C_PROBE_IN55_WIDTH = "1" *) (* C_PROBE_IN56_WIDTH = "1" *)
(* C_PROBE_IN57_WIDTH = "1" *) (* C_PROBE_IN58_WIDTH = "1" *) (* C_PROBE_IN59_WIDTH = "1" *)
(* C_PROBE_IN5_WIDTH = "1" *) (* C_PROBE_IN60_WIDTH = "1" *) (* C_PROBE_IN61_WIDTH = "1" *)
(* C_PROBE_IN62_WIDTH = "1" *) (* C_PROBE_IN63_WIDTH = "1" *) (* C_PROBE_IN64_WIDTH = "1" *)
(* C_PROBE_IN65_WIDTH = "1" *) (* C_PROBE_IN66_WIDTH = "1" *) (* C_PROBE_IN67_WIDTH = "1" *)
(* C_PROBE_IN68_WIDTH = "1" *) (* C_PROBE_IN69_WIDTH = "1" *) (* C_PROBE_IN6_WIDTH = "1" *)
(* C_PROBE_IN70_WIDTH = "1" *) (* C_PROBE_IN71_WIDTH = "1" *) (* C_PROBE_IN72_WIDTH = "1" *)
(* C_PROBE_IN73_WIDTH = "1" *) (* C_PROBE_IN74_WIDTH = "1" *) (* C_PROBE_IN75_WIDTH = "1" *)
(* C_PROBE_IN76_WIDTH = "1" *) (* C_PROBE_IN77_WIDTH = "1" *) (* C_PROBE_IN78_WIDTH = "1" *)
(* C_PROBE_IN79_WIDTH = "1" *) (* C_PROBE_IN7_WIDTH = "1" *) (* C_PROBE_IN80_WIDTH = "1" *)
(* C_PROBE_IN81_WIDTH = "1" *) (* C_PROBE_IN82_WIDTH = "1" *) (* C_PROBE_IN83_WIDTH = "1" *)
(* C_PROBE_IN84_WIDTH = "1" *) (* C_PROBE_IN85_WIDTH = "1" *) (* C_PROBE_IN86_WIDTH = "1" *)
(* C_PROBE_IN87_WIDTH = "1" *) (* C_PROBE_IN88_WIDTH = "1" *) (* C_PROBE_IN89_WIDTH = "1" *)
(* C_PROBE_IN8_WIDTH = "1" *) (* C_PROBE_IN90_WIDTH = "1" *) (* C_PROBE_IN91_WIDTH = "1" *)
(* C_PROBE_IN92_WIDTH = "1" *) (* C_PROBE_IN93_WIDTH = "1" *) (* C_PROBE_IN94_WIDTH = "1" *)
(* C_PROBE_IN95_WIDTH = "1" *) (* C_PROBE_IN96_WIDTH = "1" *) (* C_PROBE_IN97_WIDTH = "1" *)
(* C_PROBE_IN98_WIDTH = "1" *) (* C_PROBE_IN99_WIDTH = "1" *) (* C_PROBE_IN9_WIDTH = "1" *)
(* C_PROBE_OUT0_INIT_VAL = "1'b0" *) (* C_PROBE_OUT0_WIDTH = "1" *) (* C_PROBE_OUT100_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT100_WIDTH = "1" *) (* C_PROBE_OUT101_INIT_VAL = "1'b0" *) (* C_PROBE_OUT101_WIDTH = "1" *)
(* C_PROBE_OUT102_INIT_VAL = "1'b0" *) (* C_PROBE_OUT102_WIDTH = "1" *) (* C_PROBE_OUT103_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT103_WIDTH = "1" *) (* C_PROBE_OUT104_INIT_VAL = "1'b0" *) (* C_PROBE_OUT104_WIDTH = "1" *)
(* C_PROBE_OUT105_INIT_VAL = "1'b0" *) (* C_PROBE_OUT105_WIDTH = "1" *) (* C_PROBE_OUT106_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT106_WIDTH = "1" *) (* C_PROBE_OUT107_INIT_VAL = "1'b0" *) (* C_PROBE_OUT107_WIDTH = "1" *)
(* C_PROBE_OUT108_INIT_VAL = "1'b0" *) (* C_PROBE_OUT108_WIDTH = "1" *) (* C_PROBE_OUT109_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT109_WIDTH = "1" *) (* C_PROBE_OUT10_INIT_VAL = "1'b0" *) (* C_PROBE_OUT10_WIDTH = "1" *)
(* C_PROBE_OUT110_INIT_VAL = "1'b0" *) (* C_PROBE_OUT110_WIDTH = "1" *) (* C_PROBE_OUT111_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT111_WIDTH = "1" *) (* C_PROBE_OUT112_INIT_VAL = "1'b0" *) (* C_PROBE_OUT112_WIDTH = "1" *)
(* C_PROBE_OUT113_INIT_VAL = "1'b0" *) (* C_PROBE_OUT113_WIDTH = "1" *) (* C_PROBE_OUT114_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT114_WIDTH = "1" *) (* C_PROBE_OUT115_INIT_VAL = "1'b0" *) (* C_PROBE_OUT115_WIDTH = "1" *)
(* C_PROBE_OUT116_INIT_VAL = "1'b0" *) (* C_PROBE_OUT116_WIDTH = "1" *) (* C_PROBE_OUT117_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT117_WIDTH = "1" *) (* C_PROBE_OUT118_INIT_VAL = "1'b0" *) (* C_PROBE_OUT118_WIDTH = "1" *)
(* C_PROBE_OUT119_INIT_VAL = "1'b0" *) (* C_PROBE_OUT119_WIDTH = "1" *) (* C_PROBE_OUT11_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT11_WIDTH = "1" *) (* C_PROBE_OUT120_INIT_VAL = "1'b0" *) (* C_PROBE_OUT120_WIDTH = "1" *)
(* C_PROBE_OUT121_INIT_VAL = "1'b0" *) (* C_PROBE_OUT121_WIDTH = "1" *) (* C_PROBE_OUT122_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT122_WIDTH = "1" *) (* C_PROBE_OUT123_INIT_VAL = "1'b0" *) (* C_PROBE_OUT123_WIDTH = "1" *)
(* C_PROBE_OUT124_INIT_VAL = "1'b0" *) (* C_PROBE_OUT124_WIDTH = "1" *) (* C_PROBE_OUT125_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT125_WIDTH = "1" *) (* C_PROBE_OUT126_INIT_VAL = "1'b0" *) (* C_PROBE_OUT126_WIDTH = "1" *)
(* C_PROBE_OUT127_INIT_VAL = "1'b0" *) (* C_PROBE_OUT127_WIDTH = "1" *) (* C_PROBE_OUT128_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT128_WIDTH = "1" *) (* C_PROBE_OUT129_INIT_VAL = "1'b0" *) (* C_PROBE_OUT129_WIDTH = "1" *)
(* C_PROBE_OUT12_INIT_VAL = "1'b0" *) (* C_PROBE_OUT12_WIDTH = "1" *) (* C_PROBE_OUT130_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT130_WIDTH = "1" *) (* C_PROBE_OUT131_INIT_VAL = "1'b0" *) (* C_PROBE_OUT131_WIDTH = "1" *)
(* C_PROBE_OUT132_INIT_VAL = "1'b0" *) (* C_PROBE_OUT132_WIDTH = "1" *) (* C_PROBE_OUT133_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT133_WIDTH = "1" *) (* C_PROBE_OUT134_INIT_VAL = "1'b0" *) (* C_PROBE_OUT134_WIDTH = "1" *)
(* C_PROBE_OUT135_INIT_VAL = "1'b0" *) (* C_PROBE_OUT135_WIDTH = "1" *) (* C_PROBE_OUT136_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT136_WIDTH = "1" *) (* C_PROBE_OUT137_INIT_VAL = "1'b0" *) (* C_PROBE_OUT137_WIDTH = "1" *)
(* C_PROBE_OUT138_INIT_VAL = "1'b0" *) (* C_PROBE_OUT138_WIDTH = "1" *) (* C_PROBE_OUT139_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT139_WIDTH = "1" *) (* C_PROBE_OUT13_INIT_VAL = "1'b0" *) (* C_PROBE_OUT13_WIDTH = "1" *)
(* C_PROBE_OUT140_INIT_VAL = "1'b0" *) (* C_PROBE_OUT140_WIDTH = "1" *) (* C_PROBE_OUT141_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT141_WIDTH = "1" *) (* C_PROBE_OUT142_INIT_VAL = "1'b0" *) (* C_PROBE_OUT142_WIDTH = "1" *)
(* C_PROBE_OUT143_INIT_VAL = "1'b0" *) (* C_PROBE_OUT143_WIDTH = "1" *) (* C_PROBE_OUT144_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT144_WIDTH = "1" *) (* C_PROBE_OUT145_INIT_VAL = "1'b0" *) (* C_PROBE_OUT145_WIDTH = "1" *)
(* C_PROBE_OUT146_INIT_VAL = "1'b0" *) (* C_PROBE_OUT146_WIDTH = "1" *) (* C_PROBE_OUT147_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT147_WIDTH = "1" *) (* C_PROBE_OUT148_INIT_VAL = "1'b0" *) (* C_PROBE_OUT148_WIDTH = "1" *)
(* C_PROBE_OUT149_INIT_VAL = "1'b0" *) (* C_PROBE_OUT149_WIDTH = "1" *) (* C_PROBE_OUT14_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT14_WIDTH = "1" *) (* C_PROBE_OUT150_INIT_VAL = "1'b0" *) (* C_PROBE_OUT150_WIDTH = "1" *)
(* C_PROBE_OUT151_INIT_VAL = "1'b0" *) (* C_PROBE_OUT151_WIDTH = "1" *) (* C_PROBE_OUT152_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT152_WIDTH = "1" *) (* C_PROBE_OUT153_INIT_VAL = "1'b0" *) (* C_PROBE_OUT153_WIDTH = "1" *)
(* C_PROBE_OUT154_INIT_VAL = "1'b0" *) (* C_PROBE_OUT154_WIDTH = "1" *) (* C_PROBE_OUT155_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT155_WIDTH = "1" *) (* C_PROBE_OUT156_INIT_VAL = "1'b0" *) (* C_PROBE_OUT156_WIDTH = "1" *)
(* C_PROBE_OUT157_INIT_VAL = "1'b0" *) (* C_PROBE_OUT157_WIDTH = "1" *) (* C_PROBE_OUT158_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT158_WIDTH = "1" *) (* C_PROBE_OUT159_INIT_VAL = "1'b0" *) (* C_PROBE_OUT159_WIDTH = "1" *)
(* C_PROBE_OUT15_INIT_VAL = "1'b0" *) (* C_PROBE_OUT15_WIDTH = "1" *) (* C_PROBE_OUT160_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT160_WIDTH = "1" *) (* C_PROBE_OUT161_INIT_VAL = "1'b0" *) (* C_PROBE_OUT161_WIDTH = "1" *)
(* C_PROBE_OUT162_INIT_VAL = "1'b0" *) (* C_PROBE_OUT162_WIDTH = "1" *) (* C_PROBE_OUT163_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT163_WIDTH = "1" *) (* C_PROBE_OUT164_INIT_VAL = "1'b0" *) (* C_PROBE_OUT164_WIDTH = "1" *)
(* C_PROBE_OUT165_INIT_VAL = "1'b0" *) (* C_PROBE_OUT165_WIDTH = "1" *) (* C_PROBE_OUT166_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT166_WIDTH = "1" *) (* C_PROBE_OUT167_INIT_VAL = "1'b0" *) (* C_PROBE_OUT167_WIDTH = "1" *)
(* C_PROBE_OUT168_INIT_VAL = "1'b0" *) (* C_PROBE_OUT168_WIDTH = "1" *) (* C_PROBE_OUT169_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT169_WIDTH = "1" *) (* C_PROBE_OUT16_INIT_VAL = "1'b0" *) (* C_PROBE_OUT16_WIDTH = "1" *)
(* C_PROBE_OUT170_INIT_VAL = "1'b0" *) (* C_PROBE_OUT170_WIDTH = "1" *) (* C_PROBE_OUT171_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT171_WIDTH = "1" *) (* C_PROBE_OUT172_INIT_VAL = "1'b0" *) (* C_PROBE_OUT172_WIDTH = "1" *)
(* C_PROBE_OUT173_INIT_VAL = "1'b0" *) (* C_PROBE_OUT173_WIDTH = "1" *) (* C_PROBE_OUT174_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT174_WIDTH = "1" *) (* C_PROBE_OUT175_INIT_VAL = "1'b0" *) (* C_PROBE_OUT175_WIDTH = "1" *)
(* C_PROBE_OUT176_INIT_VAL = "1'b0" *) (* C_PROBE_OUT176_WIDTH = "1" *) (* C_PROBE_OUT177_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT177_WIDTH = "1" *) (* C_PROBE_OUT178_INIT_VAL = "1'b0" *) (* C_PROBE_OUT178_WIDTH = "1" *)
(* C_PROBE_OUT179_INIT_VAL = "1'b0" *) (* C_PROBE_OUT179_WIDTH = "1" *) (* C_PROBE_OUT17_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT17_WIDTH = "1" *) (* C_PROBE_OUT180_INIT_VAL = "1'b0" *) (* C_PROBE_OUT180_WIDTH = "1" *)
(* C_PROBE_OUT181_INIT_VAL = "1'b0" *) (* C_PROBE_OUT181_WIDTH = "1" *) (* C_PROBE_OUT182_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT182_WIDTH = "1" *) (* C_PROBE_OUT183_INIT_VAL = "1'b0" *) (* C_PROBE_OUT183_WIDTH = "1" *)
(* C_PROBE_OUT184_INIT_VAL = "1'b0" *) (* C_PROBE_OUT184_WIDTH = "1" *) (* C_PROBE_OUT185_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT185_WIDTH = "1" *) (* C_PROBE_OUT186_INIT_VAL = "1'b0" *) (* C_PROBE_OUT186_WIDTH = "1" *)
(* C_PROBE_OUT187_INIT_VAL = "1'b0" *) (* C_PROBE_OUT187_WIDTH = "1" *) (* C_PROBE_OUT188_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT188_WIDTH = "1" *) (* C_PROBE_OUT189_INIT_VAL = "1'b0" *) (* C_PROBE_OUT189_WIDTH = "1" *)
(* C_PROBE_OUT18_INIT_VAL = "1'b0" *) (* C_PROBE_OUT18_WIDTH = "1" *) (* C_PROBE_OUT190_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT190_WIDTH = "1" *) (* C_PROBE_OUT191_INIT_VAL = "1'b0" *) (* C_PROBE_OUT191_WIDTH = "1" *)
(* C_PROBE_OUT192_INIT_VAL = "1'b0" *) (* C_PROBE_OUT192_WIDTH = "1" *) (* C_PROBE_OUT193_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT193_WIDTH = "1" *) (* C_PROBE_OUT194_INIT_VAL = "1'b0" *) (* C_PROBE_OUT194_WIDTH = "1" *)
(* C_PROBE_OUT195_INIT_VAL = "1'b0" *) (* C_PROBE_OUT195_WIDTH = "1" *) (* C_PROBE_OUT196_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT196_WIDTH = "1" *) (* C_PROBE_OUT197_INIT_VAL = "1'b0" *) (* C_PROBE_OUT197_WIDTH = "1" *)
(* C_PROBE_OUT198_INIT_VAL = "1'b0" *) (* C_PROBE_OUT198_WIDTH = "1" *) (* C_PROBE_OUT199_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT199_WIDTH = "1" *) (* C_PROBE_OUT19_INIT_VAL = "1'b0" *) (* C_PROBE_OUT19_WIDTH = "1" *)
(* C_PROBE_OUT1_INIT_VAL = "1'b0" *) (* C_PROBE_OUT1_WIDTH = "1" *) (* C_PROBE_OUT200_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT200_WIDTH = "1" *) (* C_PROBE_OUT201_INIT_VAL = "1'b0" *) (* C_PROBE_OUT201_WIDTH = "1" *)
(* C_PROBE_OUT202_INIT_VAL = "1'b0" *) (* C_PROBE_OUT202_WIDTH = "1" *) (* C_PROBE_OUT203_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT203_WIDTH = "1" *) (* C_PROBE_OUT204_INIT_VAL = "1'b0" *) (* C_PROBE_OUT204_WIDTH = "1" *)
(* C_PROBE_OUT205_INIT_VAL = "1'b0" *) (* C_PROBE_OUT205_WIDTH = "1" *) (* C_PROBE_OUT206_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT206_WIDTH = "1" *) (* C_PROBE_OUT207_INIT_VAL = "1'b0" *) (* C_PROBE_OUT207_WIDTH = "1" *)
(* C_PROBE_OUT208_INIT_VAL = "1'b0" *) (* C_PROBE_OUT208_WIDTH = "1" *) (* C_PROBE_OUT209_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT209_WIDTH = "1" *) (* C_PROBE_OUT20_INIT_VAL = "1'b0" *) (* C_PROBE_OUT20_WIDTH = "1" *)
(* C_PROBE_OUT210_INIT_VAL = "1'b0" *) (* C_PROBE_OUT210_WIDTH = "1" *) (* C_PROBE_OUT211_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT211_WIDTH = "1" *) (* C_PROBE_OUT212_INIT_VAL = "1'b0" *) (* C_PROBE_OUT212_WIDTH = "1" *)
(* C_PROBE_OUT213_INIT_VAL = "1'b0" *) (* C_PROBE_OUT213_WIDTH = "1" *) (* C_PROBE_OUT214_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT214_WIDTH = "1" *) (* C_PROBE_OUT215_INIT_VAL = "1'b0" *) (* C_PROBE_OUT215_WIDTH = "1" *)
(* C_PROBE_OUT216_INIT_VAL = "1'b0" *) (* C_PROBE_OUT216_WIDTH = "1" *) (* C_PROBE_OUT217_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT217_WIDTH = "1" *) (* C_PROBE_OUT218_INIT_VAL = "1'b0" *) (* C_PROBE_OUT218_WIDTH = "1" *)
(* C_PROBE_OUT219_INIT_VAL = "1'b0" *) (* C_PROBE_OUT219_WIDTH = "1" *) (* C_PROBE_OUT21_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT21_WIDTH = "1" *) (* C_PROBE_OUT220_INIT_VAL = "1'b0" *) (* C_PROBE_OUT220_WIDTH = "1" *)
(* C_PROBE_OUT221_INIT_VAL = "1'b0" *) (* C_PROBE_OUT221_WIDTH = "1" *) (* C_PROBE_OUT222_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT222_WIDTH = "1" *) (* C_PROBE_OUT223_INIT_VAL = "1'b0" *) (* C_PROBE_OUT223_WIDTH = "1" *)
(* C_PROBE_OUT224_INIT_VAL = "1'b0" *) (* C_PROBE_OUT224_WIDTH = "1" *) (* C_PROBE_OUT225_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT225_WIDTH = "1" *) (* C_PROBE_OUT226_INIT_VAL = "1'b0" *) (* C_PROBE_OUT226_WIDTH = "1" *)
(* C_PROBE_OUT227_INIT_VAL = "1'b0" *) (* C_PROBE_OUT227_WIDTH = "1" *) (* C_PROBE_OUT228_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT228_WIDTH = "1" *) (* C_PROBE_OUT229_INIT_VAL = "1'b0" *) (* C_PROBE_OUT229_WIDTH = "1" *)
(* C_PROBE_OUT22_INIT_VAL = "1'b0" *) (* C_PROBE_OUT22_WIDTH = "1" *) (* C_PROBE_OUT230_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT230_WIDTH = "1" *) (* C_PROBE_OUT231_INIT_VAL = "1'b0" *) (* C_PROBE_OUT231_WIDTH = "1" *)
(* C_PROBE_OUT232_INIT_VAL = "1'b0" *) (* C_PROBE_OUT232_WIDTH = "1" *) (* C_PROBE_OUT233_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT233_WIDTH = "1" *) (* C_PROBE_OUT234_INIT_VAL = "1'b0" *) (* C_PROBE_OUT234_WIDTH = "1" *)
(* C_PROBE_OUT235_INIT_VAL = "1'b0" *) (* C_PROBE_OUT235_WIDTH = "1" *) (* C_PROBE_OUT236_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT236_WIDTH = "1" *) (* C_PROBE_OUT237_INIT_VAL = "1'b0" *) (* C_PROBE_OUT237_WIDTH = "1" *)
(* C_PROBE_OUT238_INIT_VAL = "1'b0" *) (* C_PROBE_OUT238_WIDTH = "1" *) (* C_PROBE_OUT239_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT239_WIDTH = "1" *) (* C_PROBE_OUT23_INIT_VAL = "1'b0" *) (* C_PROBE_OUT23_WIDTH = "1" *)
(* C_PROBE_OUT240_INIT_VAL = "1'b0" *) (* C_PROBE_OUT240_WIDTH = "1" *) (* C_PROBE_OUT241_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT241_WIDTH = "1" *) (* C_PROBE_OUT242_INIT_VAL = "1'b0" *) (* C_PROBE_OUT242_WIDTH = "1" *)
(* C_PROBE_OUT243_INIT_VAL = "1'b0" *) (* C_PROBE_OUT243_WIDTH = "1" *) (* C_PROBE_OUT244_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT244_WIDTH = "1" *) (* C_PROBE_OUT245_INIT_VAL = "1'b0" *) (* C_PROBE_OUT245_WIDTH = "1" *)
(* C_PROBE_OUT246_INIT_VAL = "1'b0" *) (* C_PROBE_OUT246_WIDTH = "1" *) (* C_PROBE_OUT247_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT247_WIDTH = "1" *) (* C_PROBE_OUT248_INIT_VAL = "1'b0" *) (* C_PROBE_OUT248_WIDTH = "1" *)
(* C_PROBE_OUT249_INIT_VAL = "1'b0" *) (* C_PROBE_OUT249_WIDTH = "1" *) (* C_PROBE_OUT24_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT24_WIDTH = "1" *) (* C_PROBE_OUT250_INIT_VAL = "1'b0" *) (* C_PROBE_OUT250_WIDTH = "1" *)
(* C_PROBE_OUT251_INIT_VAL = "1'b0" *) (* C_PROBE_OUT251_WIDTH = "1" *) (* C_PROBE_OUT252_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT252_WIDTH = "1" *) (* C_PROBE_OUT253_INIT_VAL = "1'b0" *) (* C_PROBE_OUT253_WIDTH = "1" *)
(* C_PROBE_OUT254_INIT_VAL = "1'b0" *) (* C_PROBE_OUT254_WIDTH = "1" *) (* C_PROBE_OUT255_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT255_WIDTH = "1" *) (* C_PROBE_OUT25_INIT_VAL = "1'b0" *) (* C_PROBE_OUT25_WIDTH = "1" *)
(* C_PROBE_OUT26_INIT_VAL = "1'b0" *) (* C_PROBE_OUT26_WIDTH = "1" *) (* C_PROBE_OUT27_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT27_WIDTH = "1" *) (* C_PROBE_OUT28_INIT_VAL = "1'b0" *) (* C_PROBE_OUT28_WIDTH = "1" *)
(* C_PROBE_OUT29_INIT_VAL = "1'b0" *) (* C_PROBE_OUT29_WIDTH = "1" *) (* C_PROBE_OUT2_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT2_WIDTH = "1" *) (* C_PROBE_OUT30_INIT_VAL = "1'b0" *) (* C_PROBE_OUT30_WIDTH = "1" *)
(* C_PROBE_OUT31_INIT_VAL = "1'b0" *) (* C_PROBE_OUT31_WIDTH = "1" *) (* C_PROBE_OUT32_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT32_WIDTH = "1" *) (* C_PROBE_OUT33_INIT_VAL = "1'b0" *) (* C_PROBE_OUT33_WIDTH = "1" *)
(* C_PROBE_OUT34_INIT_VAL = "1'b0" *) (* C_PROBE_OUT34_WIDTH = "1" *) (* C_PROBE_OUT35_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT35_WIDTH = "1" *) (* C_PROBE_OUT36_INIT_VAL = "1'b0" *) (* C_PROBE_OUT36_WIDTH = "1" *)
(* C_PROBE_OUT37_INIT_VAL = "1'b0" *) (* C_PROBE_OUT37_WIDTH = "1" *) (* C_PROBE_OUT38_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT38_WIDTH = "1" *) (* C_PROBE_OUT39_INIT_VAL = "1'b0" *) (* C_PROBE_OUT39_WIDTH = "1" *)
(* C_PROBE_OUT3_INIT_VAL = "1'b0" *) (* C_PROBE_OUT3_WIDTH = "1" *) (* C_PROBE_OUT40_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT40_WIDTH = "1" *) (* C_PROBE_OUT41_INIT_VAL = "1'b0" *) (* C_PROBE_OUT41_WIDTH = "1" *)
(* C_PROBE_OUT42_INIT_VAL = "1'b0" *) (* C_PROBE_OUT42_WIDTH = "1" *) (* C_PROBE_OUT43_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT43_WIDTH = "1" *) (* C_PROBE_OUT44_INIT_VAL = "1'b0" *) (* C_PROBE_OUT44_WIDTH = "1" *)
(* C_PROBE_OUT45_INIT_VAL = "1'b0" *) (* C_PROBE_OUT45_WIDTH = "1" *) (* C_PROBE_OUT46_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT46_WIDTH = "1" *) (* C_PROBE_OUT47_INIT_VAL = "1'b0" *) (* C_PROBE_OUT47_WIDTH = "1" *)
(* C_PROBE_OUT48_INIT_VAL = "1'b0" *) (* C_PROBE_OUT48_WIDTH = "1" *) (* C_PROBE_OUT49_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT49_WIDTH = "1" *) (* C_PROBE_OUT4_INIT_VAL = "1'b0" *) (* C_PROBE_OUT4_WIDTH = "1" *)
(* C_PROBE_OUT50_INIT_VAL = "1'b0" *) (* C_PROBE_OUT50_WIDTH = "1" *) (* C_PROBE_OUT51_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT51_WIDTH = "1" *) (* C_PROBE_OUT52_INIT_VAL = "1'b0" *) (* C_PROBE_OUT52_WIDTH = "1" *)
(* C_PROBE_OUT53_INIT_VAL = "1'b0" *) (* C_PROBE_OUT53_WIDTH = "1" *) (* C_PROBE_OUT54_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT54_WIDTH = "1" *) (* C_PROBE_OUT55_INIT_VAL = "1'b0" *) (* C_PROBE_OUT55_WIDTH = "1" *)
(* C_PROBE_OUT56_INIT_VAL = "1'b0" *) (* C_PROBE_OUT56_WIDTH = "1" *) (* C_PROBE_OUT57_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT57_WIDTH = "1" *) (* C_PROBE_OUT58_INIT_VAL = "1'b0" *) (* C_PROBE_OUT58_WIDTH = "1" *)
(* C_PROBE_OUT59_INIT_VAL = "1'b0" *) (* C_PROBE_OUT59_WIDTH = "1" *) (* C_PROBE_OUT5_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT5_WIDTH = "1" *) (* C_PROBE_OUT60_INIT_VAL = "1'b0" *) (* C_PROBE_OUT60_WIDTH = "1" *)
(* C_PROBE_OUT61_INIT_VAL = "1'b0" *) (* C_PROBE_OUT61_WIDTH = "1" *) (* C_PROBE_OUT62_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT62_WIDTH = "1" *) (* C_PROBE_OUT63_INIT_VAL = "1'b0" *) (* C_PROBE_OUT63_WIDTH = "1" *)
(* C_PROBE_OUT64_INIT_VAL = "1'b0" *) (* C_PROBE_OUT64_WIDTH = "1" *) (* C_PROBE_OUT65_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT65_WIDTH = "1" *) (* C_PROBE_OUT66_INIT_VAL = "1'b0" *) (* C_PROBE_OUT66_WIDTH = "1" *)
(* C_PROBE_OUT67_INIT_VAL = "1'b0" *) (* C_PROBE_OUT67_WIDTH = "1" *) (* C_PROBE_OUT68_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT68_WIDTH = "1" *) (* C_PROBE_OUT69_INIT_VAL = "1'b0" *) (* C_PROBE_OUT69_WIDTH = "1" *)
(* C_PROBE_OUT6_INIT_VAL = "1'b0" *) (* C_PROBE_OUT6_WIDTH = "1" *) (* C_PROBE_OUT70_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT70_WIDTH = "1" *) (* C_PROBE_OUT71_INIT_VAL = "1'b0" *) (* C_PROBE_OUT71_WIDTH = "1" *)
(* C_PROBE_OUT72_INIT_VAL = "1'b0" *) (* C_PROBE_OUT72_WIDTH = "1" *) (* C_PROBE_OUT73_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT73_WIDTH = "1" *) (* C_PROBE_OUT74_INIT_VAL = "1'b0" *) (* C_PROBE_OUT74_WIDTH = "1" *)
(* C_PROBE_OUT75_INIT_VAL = "1'b0" *) (* C_PROBE_OUT75_WIDTH = "1" *) (* C_PROBE_OUT76_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT76_WIDTH = "1" *) (* C_PROBE_OUT77_INIT_VAL = "1'b0" *) (* C_PROBE_OUT77_WIDTH = "1" *)
(* C_PROBE_OUT78_INIT_VAL = "1'b0" *) (* C_PROBE_OUT78_WIDTH = "1" *) (* C_PROBE_OUT79_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT79_WIDTH = "1" *) (* C_PROBE_OUT7_INIT_VAL = "1'b0" *) (* C_PROBE_OUT7_WIDTH = "1" *)
(* C_PROBE_OUT80_INIT_VAL = "1'b0" *) (* C_PROBE_OUT80_WIDTH = "1" *) (* C_PROBE_OUT81_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT81_WIDTH = "1" *) (* C_PROBE_OUT82_INIT_VAL = "1'b0" *) (* C_PROBE_OUT82_WIDTH = "1" *)
(* C_PROBE_OUT83_INIT_VAL = "1'b0" *) (* C_PROBE_OUT83_WIDTH = "1" *) (* C_PROBE_OUT84_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT84_WIDTH = "1" *) (* C_PROBE_OUT85_INIT_VAL = "1'b0" *) (* C_PROBE_OUT85_WIDTH = "1" *)
(* C_PROBE_OUT86_INIT_VAL = "1'b0" *) (* C_PROBE_OUT86_WIDTH = "1" *) (* C_PROBE_OUT87_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT87_WIDTH = "1" *) (* C_PROBE_OUT88_INIT_VAL = "1'b0" *) (* C_PROBE_OUT88_WIDTH = "1" *)
(* C_PROBE_OUT89_INIT_VAL = "1'b0" *) (* C_PROBE_OUT89_WIDTH = "1" *) (* C_PROBE_OUT8_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT8_WIDTH = "1" *) (* C_PROBE_OUT90_INIT_VAL = "1'b0" *) (* C_PROBE_OUT90_WIDTH = "1" *)
(* C_PROBE_OUT91_INIT_VAL = "1'b0" *) (* C_PROBE_OUT91_WIDTH = "1" *) (* C_PROBE_OUT92_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT92_WIDTH = "1" *) (* C_PROBE_OUT93_INIT_VAL = "1'b0" *) (* C_PROBE_OUT93_WIDTH = "1" *)
(* C_PROBE_OUT94_INIT_VAL = "1'b0" *) (* C_PROBE_OUT94_WIDTH = "1" *) (* C_PROBE_OUT95_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT95_WIDTH = "1" *) (* C_PROBE_OUT96_INIT_VAL = "1'b0" *) (* C_PROBE_OUT96_WIDTH = "1" *)
(* C_PROBE_OUT97_INIT_VAL = "1'b0" *) (* C_PROBE_OUT97_WIDTH = "1" *) (* C_PROBE_OUT98_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT98_WIDTH = "1" *) (* C_PROBE_OUT99_INIT_VAL = "1'b0" *) (* C_PROBE_OUT99_WIDTH = "1" *)
(* C_PROBE_OUT9_INIT_VAL = "1'b0" *) (* C_PROBE_OUT9_WIDTH = "1" *) (* C_USE_TEST_REG = "1" *)
(* C_XDEVICEFAMILY = "kintex7" *) (* C_XLNX_HW_PROBE_INFO = "DEFAULT" *) (* C_XSDB_SLAVE_TYPE = "33" *)
(* DowngradeIPIdentifiedWarnings = "yes" *) (* LC_HIGH_BIT_POS_PROBE_OUT0 = "16'b0000000000000000" *) (* LC_HIGH_BIT_POS_PROBE_OUT1 = "16'b0000000000000001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT10 = "16'b0000000000001010" *) (* LC_HIGH_BIT_POS_PROBE_OUT100 = "16'b0000000001100100" *) (* LC_HIGH_BIT_POS_PROBE_OUT101 = "16'b0000000001100101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT102 = "16'b0000000001100110" *) (* LC_HIGH_BIT_POS_PROBE_OUT103 = "16'b0000000001100111" *) (* LC_HIGH_BIT_POS_PROBE_OUT104 = "16'b0000000001101000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT105 = "16'b0000000001101001" *) (* LC_HIGH_BIT_POS_PROBE_OUT106 = "16'b0000000001101010" *) (* LC_HIGH_BIT_POS_PROBE_OUT107 = "16'b0000000001101011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT108 = "16'b0000000001101100" *) (* LC_HIGH_BIT_POS_PROBE_OUT109 = "16'b0000000001101101" *) (* LC_HIGH_BIT_POS_PROBE_OUT11 = "16'b0000000000001011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT110 = "16'b0000000001101110" *) (* LC_HIGH_BIT_POS_PROBE_OUT111 = "16'b0000000001101111" *) (* LC_HIGH_BIT_POS_PROBE_OUT112 = "16'b0000000001110000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT113 = "16'b0000000001110001" *) (* LC_HIGH_BIT_POS_PROBE_OUT114 = "16'b0000000001110010" *) (* LC_HIGH_BIT_POS_PROBE_OUT115 = "16'b0000000001110011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT116 = "16'b0000000001110100" *) (* LC_HIGH_BIT_POS_PROBE_OUT117 = "16'b0000000001110101" *) (* LC_HIGH_BIT_POS_PROBE_OUT118 = "16'b0000000001110110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT119 = "16'b0000000001110111" *) (* LC_HIGH_BIT_POS_PROBE_OUT12 = "16'b0000000000001100" *) (* LC_HIGH_BIT_POS_PROBE_OUT120 = "16'b0000000001111000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT121 = "16'b0000000001111001" *) (* LC_HIGH_BIT_POS_PROBE_OUT122 = "16'b0000000001111010" *) (* LC_HIGH_BIT_POS_PROBE_OUT123 = "16'b0000000001111011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT124 = "16'b0000000001111100" *) (* LC_HIGH_BIT_POS_PROBE_OUT125 = "16'b0000000001111101" *) (* LC_HIGH_BIT_POS_PROBE_OUT126 = "16'b0000000001111110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT127 = "16'b0000000001111111" *) (* LC_HIGH_BIT_POS_PROBE_OUT128 = "16'b0000000010000000" *) (* LC_HIGH_BIT_POS_PROBE_OUT129 = "16'b0000000010000001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT13 = "16'b0000000000001101" *) (* LC_HIGH_BIT_POS_PROBE_OUT130 = "16'b0000000010000010" *) (* LC_HIGH_BIT_POS_PROBE_OUT131 = "16'b0000000010000011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT132 = "16'b0000000010000100" *) (* LC_HIGH_BIT_POS_PROBE_OUT133 = "16'b0000000010000101" *) (* LC_HIGH_BIT_POS_PROBE_OUT134 = "16'b0000000010000110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT135 = "16'b0000000010000111" *) (* LC_HIGH_BIT_POS_PROBE_OUT136 = "16'b0000000010001000" *) (* LC_HIGH_BIT_POS_PROBE_OUT137 = "16'b0000000010001001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT138 = "16'b0000000010001010" *) (* LC_HIGH_BIT_POS_PROBE_OUT139 = "16'b0000000010001011" *) (* LC_HIGH_BIT_POS_PROBE_OUT14 = "16'b0000000000001110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT140 = "16'b0000000010001100" *) (* LC_HIGH_BIT_POS_PROBE_OUT141 = "16'b0000000010001101" *) (* LC_HIGH_BIT_POS_PROBE_OUT142 = "16'b0000000010001110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT143 = "16'b0000000010001111" *) (* LC_HIGH_BIT_POS_PROBE_OUT144 = "16'b0000000010010000" *) (* LC_HIGH_BIT_POS_PROBE_OUT145 = "16'b0000000010010001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT146 = "16'b0000000010010010" *) (* LC_HIGH_BIT_POS_PROBE_OUT147 = "16'b0000000010010011" *) (* LC_HIGH_BIT_POS_PROBE_OUT148 = "16'b0000000010010100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT149 = "16'b0000000010010101" *) (* LC_HIGH_BIT_POS_PROBE_OUT15 = "16'b0000000000001111" *) (* LC_HIGH_BIT_POS_PROBE_OUT150 = "16'b0000000010010110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT151 = "16'b0000000010010111" *) (* LC_HIGH_BIT_POS_PROBE_OUT152 = "16'b0000000010011000" *) (* LC_HIGH_BIT_POS_PROBE_OUT153 = "16'b0000000010011001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT154 = "16'b0000000010011010" *) (* LC_HIGH_BIT_POS_PROBE_OUT155 = "16'b0000000010011011" *) (* LC_HIGH_BIT_POS_PROBE_OUT156 = "16'b0000000010011100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT157 = "16'b0000000010011101" *) (* LC_HIGH_BIT_POS_PROBE_OUT158 = "16'b0000000010011110" *) (* LC_HIGH_BIT_POS_PROBE_OUT159 = "16'b0000000010011111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT16 = "16'b0000000000010000" *) (* LC_HIGH_BIT_POS_PROBE_OUT160 = "16'b0000000010100000" *) (* LC_HIGH_BIT_POS_PROBE_OUT161 = "16'b0000000010100001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT162 = "16'b0000000010100010" *) (* LC_HIGH_BIT_POS_PROBE_OUT163 = "16'b0000000010100011" *) (* LC_HIGH_BIT_POS_PROBE_OUT164 = "16'b0000000010100100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT165 = "16'b0000000010100101" *) (* LC_HIGH_BIT_POS_PROBE_OUT166 = "16'b0000000010100110" *) (* LC_HIGH_BIT_POS_PROBE_OUT167 = "16'b0000000010100111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT168 = "16'b0000000010101000" *) (* LC_HIGH_BIT_POS_PROBE_OUT169 = "16'b0000000010101001" *) (* LC_HIGH_BIT_POS_PROBE_OUT17 = "16'b0000000000010001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT170 = "16'b0000000010101010" *) (* LC_HIGH_BIT_POS_PROBE_OUT171 = "16'b0000000010101011" *) (* LC_HIGH_BIT_POS_PROBE_OUT172 = "16'b0000000010101100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT173 = "16'b0000000010101101" *) (* LC_HIGH_BIT_POS_PROBE_OUT174 = "16'b0000000010101110" *) (* LC_HIGH_BIT_POS_PROBE_OUT175 = "16'b0000000010101111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT176 = "16'b0000000010110000" *) (* LC_HIGH_BIT_POS_PROBE_OUT177 = "16'b0000000010110001" *) (* LC_HIGH_BIT_POS_PROBE_OUT178 = "16'b0000000010110010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT179 = "16'b0000000010110011" *) (* LC_HIGH_BIT_POS_PROBE_OUT18 = "16'b0000000000010010" *) (* LC_HIGH_BIT_POS_PROBE_OUT180 = "16'b0000000010110100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT181 = "16'b0000000010110101" *) (* LC_HIGH_BIT_POS_PROBE_OUT182 = "16'b0000000010110110" *) (* LC_HIGH_BIT_POS_PROBE_OUT183 = "16'b0000000010110111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT184 = "16'b0000000010111000" *) (* LC_HIGH_BIT_POS_PROBE_OUT185 = "16'b0000000010111001" *) (* LC_HIGH_BIT_POS_PROBE_OUT186 = "16'b0000000010111010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT187 = "16'b0000000010111011" *) (* LC_HIGH_BIT_POS_PROBE_OUT188 = "16'b0000000010111100" *) (* LC_HIGH_BIT_POS_PROBE_OUT189 = "16'b0000000010111101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT19 = "16'b0000000000010011" *) (* LC_HIGH_BIT_POS_PROBE_OUT190 = "16'b0000000010111110" *) (* LC_HIGH_BIT_POS_PROBE_OUT191 = "16'b0000000010111111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT192 = "16'b0000000011000000" *) (* LC_HIGH_BIT_POS_PROBE_OUT193 = "16'b0000000011000001" *) (* LC_HIGH_BIT_POS_PROBE_OUT194 = "16'b0000000011000010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT195 = "16'b0000000011000011" *) (* LC_HIGH_BIT_POS_PROBE_OUT196 = "16'b0000000011000100" *) (* LC_HIGH_BIT_POS_PROBE_OUT197 = "16'b0000000011000101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT198 = "16'b0000000011000110" *) (* LC_HIGH_BIT_POS_PROBE_OUT199 = "16'b0000000011000111" *) (* LC_HIGH_BIT_POS_PROBE_OUT2 = "16'b0000000000000010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT20 = "16'b0000000000010100" *) (* LC_HIGH_BIT_POS_PROBE_OUT200 = "16'b0000000011001000" *) (* LC_HIGH_BIT_POS_PROBE_OUT201 = "16'b0000000011001001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT202 = "16'b0000000011001010" *) (* LC_HIGH_BIT_POS_PROBE_OUT203 = "16'b0000000011001011" *) (* LC_HIGH_BIT_POS_PROBE_OUT204 = "16'b0000000011001100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT205 = "16'b0000000011001101" *) (* LC_HIGH_BIT_POS_PROBE_OUT206 = "16'b0000000011001110" *) (* LC_HIGH_BIT_POS_PROBE_OUT207 = "16'b0000000011001111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT208 = "16'b0000000011010000" *) (* LC_HIGH_BIT_POS_PROBE_OUT209 = "16'b0000000011010001" *) (* LC_HIGH_BIT_POS_PROBE_OUT21 = "16'b0000000000010101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT210 = "16'b0000000011010010" *) (* LC_HIGH_BIT_POS_PROBE_OUT211 = "16'b0000000011010011" *) (* LC_HIGH_BIT_POS_PROBE_OUT212 = "16'b0000000011010100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT213 = "16'b0000000011010101" *) (* LC_HIGH_BIT_POS_PROBE_OUT214 = "16'b0000000011010110" *) (* LC_HIGH_BIT_POS_PROBE_OUT215 = "16'b0000000011010111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT216 = "16'b0000000011011000" *) (* LC_HIGH_BIT_POS_PROBE_OUT217 = "16'b0000000011011001" *) (* LC_HIGH_BIT_POS_PROBE_OUT218 = "16'b0000000011011010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT219 = "16'b0000000011011011" *) (* LC_HIGH_BIT_POS_PROBE_OUT22 = "16'b0000000000010110" *) (* LC_HIGH_BIT_POS_PROBE_OUT220 = "16'b0000000011011100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT221 = "16'b0000000011011101" *) (* LC_HIGH_BIT_POS_PROBE_OUT222 = "16'b0000000011011110" *) (* LC_HIGH_BIT_POS_PROBE_OUT223 = "16'b0000000011011111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT224 = "16'b0000000011100000" *) (* LC_HIGH_BIT_POS_PROBE_OUT225 = "16'b0000000011100001" *) (* LC_HIGH_BIT_POS_PROBE_OUT226 = "16'b0000000011100010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT227 = "16'b0000000011100011" *) (* LC_HIGH_BIT_POS_PROBE_OUT228 = "16'b0000000011100100" *) (* LC_HIGH_BIT_POS_PROBE_OUT229 = "16'b0000000011100101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT23 = "16'b0000000000010111" *) (* LC_HIGH_BIT_POS_PROBE_OUT230 = "16'b0000000011100110" *) (* LC_HIGH_BIT_POS_PROBE_OUT231 = "16'b0000000011100111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT232 = "16'b0000000011101000" *) (* LC_HIGH_BIT_POS_PROBE_OUT233 = "16'b0000000011101001" *) (* LC_HIGH_BIT_POS_PROBE_OUT234 = "16'b0000000011101010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT235 = "16'b0000000011101011" *) (* LC_HIGH_BIT_POS_PROBE_OUT236 = "16'b0000000011101100" *) (* LC_HIGH_BIT_POS_PROBE_OUT237 = "16'b0000000011101101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT238 = "16'b0000000011101110" *) (* LC_HIGH_BIT_POS_PROBE_OUT239 = "16'b0000000011101111" *) (* LC_HIGH_BIT_POS_PROBE_OUT24 = "16'b0000000000011000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT240 = "16'b0000000011110000" *) (* LC_HIGH_BIT_POS_PROBE_OUT241 = "16'b0000000011110001" *) (* LC_HIGH_BIT_POS_PROBE_OUT242 = "16'b0000000011110010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT243 = "16'b0000000011110011" *) (* LC_HIGH_BIT_POS_PROBE_OUT244 = "16'b0000000011110100" *) (* LC_HIGH_BIT_POS_PROBE_OUT245 = "16'b0000000011110101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT246 = "16'b0000000011110110" *) (* LC_HIGH_BIT_POS_PROBE_OUT247 = "16'b0000000011110111" *) (* LC_HIGH_BIT_POS_PROBE_OUT248 = "16'b0000000011111000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT249 = "16'b0000000011111001" *) (* LC_HIGH_BIT_POS_PROBE_OUT25 = "16'b0000000000011001" *) (* LC_HIGH_BIT_POS_PROBE_OUT250 = "16'b0000000011111010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT251 = "16'b0000000011111011" *) (* LC_HIGH_BIT_POS_PROBE_OUT252 = "16'b0000000011111100" *) (* LC_HIGH_BIT_POS_PROBE_OUT253 = "16'b0000000011111101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT254 = "16'b0000000011111110" *) (* LC_HIGH_BIT_POS_PROBE_OUT255 = "16'b0000000011111111" *) (* LC_HIGH_BIT_POS_PROBE_OUT26 = "16'b0000000000011010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT27 = "16'b0000000000011011" *) (* LC_HIGH_BIT_POS_PROBE_OUT28 = "16'b0000000000011100" *) (* LC_HIGH_BIT_POS_PROBE_OUT29 = "16'b0000000000011101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT3 = "16'b0000000000000011" *) (* LC_HIGH_BIT_POS_PROBE_OUT30 = "16'b0000000000011110" *) (* LC_HIGH_BIT_POS_PROBE_OUT31 = "16'b0000000000011111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT32 = "16'b0000000000100000" *) (* LC_HIGH_BIT_POS_PROBE_OUT33 = "16'b0000000000100001" *) (* LC_HIGH_BIT_POS_PROBE_OUT34 = "16'b0000000000100010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT35 = "16'b0000000000100011" *) (* LC_HIGH_BIT_POS_PROBE_OUT36 = "16'b0000000000100100" *) (* LC_HIGH_BIT_POS_PROBE_OUT37 = "16'b0000000000100101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT38 = "16'b0000000000100110" *) (* LC_HIGH_BIT_POS_PROBE_OUT39 = "16'b0000000000100111" *) (* LC_HIGH_BIT_POS_PROBE_OUT4 = "16'b0000000000000100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT40 = "16'b0000000000101000" *) (* LC_HIGH_BIT_POS_PROBE_OUT41 = "16'b0000000000101001" *) (* LC_HIGH_BIT_POS_PROBE_OUT42 = "16'b0000000000101010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT43 = "16'b0000000000101011" *) (* LC_HIGH_BIT_POS_PROBE_OUT44 = "16'b0000000000101100" *) (* LC_HIGH_BIT_POS_PROBE_OUT45 = "16'b0000000000101101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT46 = "16'b0000000000101110" *) (* LC_HIGH_BIT_POS_PROBE_OUT47 = "16'b0000000000101111" *) (* LC_HIGH_BIT_POS_PROBE_OUT48 = "16'b0000000000110000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT49 = "16'b0000000000110001" *) (* LC_HIGH_BIT_POS_PROBE_OUT5 = "16'b0000000000000101" *) (* LC_HIGH_BIT_POS_PROBE_OUT50 = "16'b0000000000110010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT51 = "16'b0000000000110011" *) (* LC_HIGH_BIT_POS_PROBE_OUT52 = "16'b0000000000110100" *) (* LC_HIGH_BIT_POS_PROBE_OUT53 = "16'b0000000000110101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT54 = "16'b0000000000110110" *) (* LC_HIGH_BIT_POS_PROBE_OUT55 = "16'b0000000000110111" *) (* LC_HIGH_BIT_POS_PROBE_OUT56 = "16'b0000000000111000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT57 = "16'b0000000000111001" *) (* LC_HIGH_BIT_POS_PROBE_OUT58 = "16'b0000000000111010" *) (* LC_HIGH_BIT_POS_PROBE_OUT59 = "16'b0000000000111011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT6 = "16'b0000000000000110" *) (* LC_HIGH_BIT_POS_PROBE_OUT60 = "16'b0000000000111100" *) (* LC_HIGH_BIT_POS_PROBE_OUT61 = "16'b0000000000111101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT62 = "16'b0000000000111110" *) (* LC_HIGH_BIT_POS_PROBE_OUT63 = "16'b0000000000111111" *) (* LC_HIGH_BIT_POS_PROBE_OUT64 = "16'b0000000001000000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT65 = "16'b0000000001000001" *) (* LC_HIGH_BIT_POS_PROBE_OUT66 = "16'b0000000001000010" *) (* LC_HIGH_BIT_POS_PROBE_OUT67 = "16'b0000000001000011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT68 = "16'b0000000001000100" *) (* LC_HIGH_BIT_POS_PROBE_OUT69 = "16'b0000000001000101" *) (* LC_HIGH_BIT_POS_PROBE_OUT7 = "16'b0000000000000111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT70 = "16'b0000000001000110" *) (* LC_HIGH_BIT_POS_PROBE_OUT71 = "16'b0000000001000111" *) (* LC_HIGH_BIT_POS_PROBE_OUT72 = "16'b0000000001001000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT73 = "16'b0000000001001001" *) (* LC_HIGH_BIT_POS_PROBE_OUT74 = "16'b0000000001001010" *) (* LC_HIGH_BIT_POS_PROBE_OUT75 = "16'b0000000001001011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT76 = "16'b0000000001001100" *) (* LC_HIGH_BIT_POS_PROBE_OUT77 = "16'b0000000001001101" *) (* LC_HIGH_BIT_POS_PROBE_OUT78 = "16'b0000000001001110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT79 = "16'b0000000001001111" *) (* LC_HIGH_BIT_POS_PROBE_OUT8 = "16'b0000000000001000" *) (* LC_HIGH_BIT_POS_PROBE_OUT80 = "16'b0000000001010000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT81 = "16'b0000000001010001" *) (* LC_HIGH_BIT_POS_PROBE_OUT82 = "16'b0000000001010010" *) (* LC_HIGH_BIT_POS_PROBE_OUT83 = "16'b0000000001010011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT84 = "16'b0000000001010100" *) (* LC_HIGH_BIT_POS_PROBE_OUT85 = "16'b0000000001010101" *) (* LC_HIGH_BIT_POS_PROBE_OUT86 = "16'b0000000001010110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT87 = "16'b0000000001010111" *) (* LC_HIGH_BIT_POS_PROBE_OUT88 = "16'b0000000001011000" *) (* LC_HIGH_BIT_POS_PROBE_OUT89 = "16'b0000000001011001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT9 = "16'b0000000000001001" *) (* LC_HIGH_BIT_POS_PROBE_OUT90 = "16'b0000000001011010" *) (* LC_HIGH_BIT_POS_PROBE_OUT91 = "16'b0000000001011011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT92 = "16'b0000000001011100" *) (* LC_HIGH_BIT_POS_PROBE_OUT93 = "16'b0000000001011101" *) (* LC_HIGH_BIT_POS_PROBE_OUT94 = "16'b0000000001011110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT95 = "16'b0000000001011111" *) (* LC_HIGH_BIT_POS_PROBE_OUT96 = "16'b0000000001100000" *) (* LC_HIGH_BIT_POS_PROBE_OUT97 = "16'b0000000001100001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT98 = "16'b0000000001100010" *) (* LC_HIGH_BIT_POS_PROBE_OUT99 = "16'b0000000001100011" *) (* LC_LOW_BIT_POS_PROBE_OUT0 = "16'b0000000000000000" *)
(* LC_LOW_BIT_POS_PROBE_OUT1 = "16'b0000000000000001" *) (* LC_LOW_BIT_POS_PROBE_OUT10 = "16'b0000000000001010" *) (* LC_LOW_BIT_POS_PROBE_OUT100 = "16'b0000000001100100" *)
(* LC_LOW_BIT_POS_PROBE_OUT101 = "16'b0000000001100101" *) (* LC_LOW_BIT_POS_PROBE_OUT102 = "16'b0000000001100110" *) (* LC_LOW_BIT_POS_PROBE_OUT103 = "16'b0000000001100111" *)
(* LC_LOW_BIT_POS_PROBE_OUT104 = "16'b0000000001101000" *) (* LC_LOW_BIT_POS_PROBE_OUT105 = "16'b0000000001101001" *) (* LC_LOW_BIT_POS_PROBE_OUT106 = "16'b0000000001101010" *)
(* LC_LOW_BIT_POS_PROBE_OUT107 = "16'b0000000001101011" *) (* LC_LOW_BIT_POS_PROBE_OUT108 = "16'b0000000001101100" *) (* LC_LOW_BIT_POS_PROBE_OUT109 = "16'b0000000001101101" *)
(* LC_LOW_BIT_POS_PROBE_OUT11 = "16'b0000000000001011" *) (* LC_LOW_BIT_POS_PROBE_OUT110 = "16'b0000000001101110" *) (* LC_LOW_BIT_POS_PROBE_OUT111 = "16'b0000000001101111" *)
(* LC_LOW_BIT_POS_PROBE_OUT112 = "16'b0000000001110000" *) (* LC_LOW_BIT_POS_PROBE_OUT113 = "16'b0000000001110001" *) (* LC_LOW_BIT_POS_PROBE_OUT114 = "16'b0000000001110010" *)
(* LC_LOW_BIT_POS_PROBE_OUT115 = "16'b0000000001110011" *) (* LC_LOW_BIT_POS_PROBE_OUT116 = "16'b0000000001110100" *) (* LC_LOW_BIT_POS_PROBE_OUT117 = "16'b0000000001110101" *)
(* LC_LOW_BIT_POS_PROBE_OUT118 = "16'b0000000001110110" *) (* LC_LOW_BIT_POS_PROBE_OUT119 = "16'b0000000001110111" *) (* LC_LOW_BIT_POS_PROBE_OUT12 = "16'b0000000000001100" *)
(* LC_LOW_BIT_POS_PROBE_OUT120 = "16'b0000000001111000" *) (* LC_LOW_BIT_POS_PROBE_OUT121 = "16'b0000000001111001" *) (* LC_LOW_BIT_POS_PROBE_OUT122 = "16'b0000000001111010" *)
(* LC_LOW_BIT_POS_PROBE_OUT123 = "16'b0000000001111011" *) (* LC_LOW_BIT_POS_PROBE_OUT124 = "16'b0000000001111100" *) (* LC_LOW_BIT_POS_PROBE_OUT125 = "16'b0000000001111101" *)
(* LC_LOW_BIT_POS_PROBE_OUT126 = "16'b0000000001111110" *) (* LC_LOW_BIT_POS_PROBE_OUT127 = "16'b0000000001111111" *) (* LC_LOW_BIT_POS_PROBE_OUT128 = "16'b0000000010000000" *)
(* LC_LOW_BIT_POS_PROBE_OUT129 = "16'b0000000010000001" *) (* LC_LOW_BIT_POS_PROBE_OUT13 = "16'b0000000000001101" *) (* LC_LOW_BIT_POS_PROBE_OUT130 = "16'b0000000010000010" *)
(* LC_LOW_BIT_POS_PROBE_OUT131 = "16'b0000000010000011" *) (* LC_LOW_BIT_POS_PROBE_OUT132 = "16'b0000000010000100" *) (* LC_LOW_BIT_POS_PROBE_OUT133 = "16'b0000000010000101" *)
(* LC_LOW_BIT_POS_PROBE_OUT134 = "16'b0000000010000110" *) (* LC_LOW_BIT_POS_PROBE_OUT135 = "16'b0000000010000111" *) (* LC_LOW_BIT_POS_PROBE_OUT136 = "16'b0000000010001000" *)
(* LC_LOW_BIT_POS_PROBE_OUT137 = "16'b0000000010001001" *) (* LC_LOW_BIT_POS_PROBE_OUT138 = "16'b0000000010001010" *) (* LC_LOW_BIT_POS_PROBE_OUT139 = "16'b0000000010001011" *)
(* LC_LOW_BIT_POS_PROBE_OUT14 = "16'b0000000000001110" *) (* LC_LOW_BIT_POS_PROBE_OUT140 = "16'b0000000010001100" *) (* LC_LOW_BIT_POS_PROBE_OUT141 = "16'b0000000010001101" *)
(* LC_LOW_BIT_POS_PROBE_OUT142 = "16'b0000000010001110" *) (* LC_LOW_BIT_POS_PROBE_OUT143 = "16'b0000000010001111" *) (* LC_LOW_BIT_POS_PROBE_OUT144 = "16'b0000000010010000" *)
(* LC_LOW_BIT_POS_PROBE_OUT145 = "16'b0000000010010001" *) (* LC_LOW_BIT_POS_PROBE_OUT146 = "16'b0000000010010010" *) (* LC_LOW_BIT_POS_PROBE_OUT147 = "16'b0000000010010011" *)
(* LC_LOW_BIT_POS_PROBE_OUT148 = "16'b0000000010010100" *) (* LC_LOW_BIT_POS_PROBE_OUT149 = "16'b0000000010010101" *) (* LC_LOW_BIT_POS_PROBE_OUT15 = "16'b0000000000001111" *)
(* LC_LOW_BIT_POS_PROBE_OUT150 = "16'b0000000010010110" *) (* LC_LOW_BIT_POS_PROBE_OUT151 = "16'b0000000010010111" *) (* LC_LOW_BIT_POS_PROBE_OUT152 = "16'b0000000010011000" *)
(* LC_LOW_BIT_POS_PROBE_OUT153 = "16'b0000000010011001" *) (* LC_LOW_BIT_POS_PROBE_OUT154 = "16'b0000000010011010" *) (* LC_LOW_BIT_POS_PROBE_OUT155 = "16'b0000000010011011" *)
(* LC_LOW_BIT_POS_PROBE_OUT156 = "16'b0000000010011100" *) (* LC_LOW_BIT_POS_PROBE_OUT157 = "16'b0000000010011101" *) (* LC_LOW_BIT_POS_PROBE_OUT158 = "16'b0000000010011110" *)
(* LC_LOW_BIT_POS_PROBE_OUT159 = "16'b0000000010011111" *) (* LC_LOW_BIT_POS_PROBE_OUT16 = "16'b0000000000010000" *) (* LC_LOW_BIT_POS_PROBE_OUT160 = "16'b0000000010100000" *)
(* LC_LOW_BIT_POS_PROBE_OUT161 = "16'b0000000010100001" *) (* LC_LOW_BIT_POS_PROBE_OUT162 = "16'b0000000010100010" *) (* LC_LOW_BIT_POS_PROBE_OUT163 = "16'b0000000010100011" *)
(* LC_LOW_BIT_POS_PROBE_OUT164 = "16'b0000000010100100" *) (* LC_LOW_BIT_POS_PROBE_OUT165 = "16'b0000000010100101" *) (* LC_LOW_BIT_POS_PROBE_OUT166 = "16'b0000000010100110" *)
(* LC_LOW_BIT_POS_PROBE_OUT167 = "16'b0000000010100111" *) (* LC_LOW_BIT_POS_PROBE_OUT168 = "16'b0000000010101000" *) (* LC_LOW_BIT_POS_PROBE_OUT169 = "16'b0000000010101001" *)
(* LC_LOW_BIT_POS_PROBE_OUT17 = "16'b0000000000010001" *) (* LC_LOW_BIT_POS_PROBE_OUT170 = "16'b0000000010101010" *) (* LC_LOW_BIT_POS_PROBE_OUT171 = "16'b0000000010101011" *)
(* LC_LOW_BIT_POS_PROBE_OUT172 = "16'b0000000010101100" *) (* LC_LOW_BIT_POS_PROBE_OUT173 = "16'b0000000010101101" *) (* LC_LOW_BIT_POS_PROBE_OUT174 = "16'b0000000010101110" *)
(* LC_LOW_BIT_POS_PROBE_OUT175 = "16'b0000000010101111" *) (* LC_LOW_BIT_POS_PROBE_OUT176 = "16'b0000000010110000" *) (* LC_LOW_BIT_POS_PROBE_OUT177 = "16'b0000000010110001" *)
(* LC_LOW_BIT_POS_PROBE_OUT178 = "16'b0000000010110010" *) (* LC_LOW_BIT_POS_PROBE_OUT179 = "16'b0000000010110011" *) (* LC_LOW_BIT_POS_PROBE_OUT18 = "16'b0000000000010010" *)
(* LC_LOW_BIT_POS_PROBE_OUT180 = "16'b0000000010110100" *) (* LC_LOW_BIT_POS_PROBE_OUT181 = "16'b0000000010110101" *) (* LC_LOW_BIT_POS_PROBE_OUT182 = "16'b0000000010110110" *)
(* LC_LOW_BIT_POS_PROBE_OUT183 = "16'b0000000010110111" *) (* LC_LOW_BIT_POS_PROBE_OUT184 = "16'b0000000010111000" *) (* LC_LOW_BIT_POS_PROBE_OUT185 = "16'b0000000010111001" *)
(* LC_LOW_BIT_POS_PROBE_OUT186 = "16'b0000000010111010" *) (* LC_LOW_BIT_POS_PROBE_OUT187 = "16'b0000000010111011" *) (* LC_LOW_BIT_POS_PROBE_OUT188 = "16'b0000000010111100" *)
(* LC_LOW_BIT_POS_PROBE_OUT189 = "16'b0000000010111101" *) (* LC_LOW_BIT_POS_PROBE_OUT19 = "16'b0000000000010011" *) (* LC_LOW_BIT_POS_PROBE_OUT190 = "16'b0000000010111110" *)
(* LC_LOW_BIT_POS_PROBE_OUT191 = "16'b0000000010111111" *) (* LC_LOW_BIT_POS_PROBE_OUT192 = "16'b0000000011000000" *) (* LC_LOW_BIT_POS_PROBE_OUT193 = "16'b0000000011000001" *)
(* LC_LOW_BIT_POS_PROBE_OUT194 = "16'b0000000011000010" *) (* LC_LOW_BIT_POS_PROBE_OUT195 = "16'b0000000011000011" *) (* LC_LOW_BIT_POS_PROBE_OUT196 = "16'b0000000011000100" *)
(* LC_LOW_BIT_POS_PROBE_OUT197 = "16'b0000000011000101" *) (* LC_LOW_BIT_POS_PROBE_OUT198 = "16'b0000000011000110" *) (* LC_LOW_BIT_POS_PROBE_OUT199 = "16'b0000000011000111" *)
(* LC_LOW_BIT_POS_PROBE_OUT2 = "16'b0000000000000010" *) (* LC_LOW_BIT_POS_PROBE_OUT20 = "16'b0000000000010100" *) (* LC_LOW_BIT_POS_PROBE_OUT200 = "16'b0000000011001000" *)
(* LC_LOW_BIT_POS_PROBE_OUT201 = "16'b0000000011001001" *) (* LC_LOW_BIT_POS_PROBE_OUT202 = "16'b0000000011001010" *) (* LC_LOW_BIT_POS_PROBE_OUT203 = "16'b0000000011001011" *)
(* LC_LOW_BIT_POS_PROBE_OUT204 = "16'b0000000011001100" *) (* LC_LOW_BIT_POS_PROBE_OUT205 = "16'b0000000011001101" *) (* LC_LOW_BIT_POS_PROBE_OUT206 = "16'b0000000011001110" *)
(* LC_LOW_BIT_POS_PROBE_OUT207 = "16'b0000000011001111" *) (* LC_LOW_BIT_POS_PROBE_OUT208 = "16'b0000000011010000" *) (* LC_LOW_BIT_POS_PROBE_OUT209 = "16'b0000000011010001" *)
(* LC_LOW_BIT_POS_PROBE_OUT21 = "16'b0000000000010101" *) (* LC_LOW_BIT_POS_PROBE_OUT210 = "16'b0000000011010010" *) (* LC_LOW_BIT_POS_PROBE_OUT211 = "16'b0000000011010011" *)
(* LC_LOW_BIT_POS_PROBE_OUT212 = "16'b0000000011010100" *) (* LC_LOW_BIT_POS_PROBE_OUT213 = "16'b0000000011010101" *) (* LC_LOW_BIT_POS_PROBE_OUT214 = "16'b0000000011010110" *)
(* LC_LOW_BIT_POS_PROBE_OUT215 = "16'b0000000011010111" *) (* LC_LOW_BIT_POS_PROBE_OUT216 = "16'b0000000011011000" *) (* LC_LOW_BIT_POS_PROBE_OUT217 = "16'b0000000011011001" *)
(* LC_LOW_BIT_POS_PROBE_OUT218 = "16'b0000000011011010" *) (* LC_LOW_BIT_POS_PROBE_OUT219 = "16'b0000000011011011" *) (* LC_LOW_BIT_POS_PROBE_OUT22 = "16'b0000000000010110" *)
(* LC_LOW_BIT_POS_PROBE_OUT220 = "16'b0000000011011100" *) (* LC_LOW_BIT_POS_PROBE_OUT221 = "16'b0000000011011101" *) (* LC_LOW_BIT_POS_PROBE_OUT222 = "16'b0000000011011110" *)
(* LC_LOW_BIT_POS_PROBE_OUT223 = "16'b0000000011011111" *) (* LC_LOW_BIT_POS_PROBE_OUT224 = "16'b0000000011100000" *) (* LC_LOW_BIT_POS_PROBE_OUT225 = "16'b0000000011100001" *)
(* LC_LOW_BIT_POS_PROBE_OUT226 = "16'b0000000011100010" *) (* LC_LOW_BIT_POS_PROBE_OUT227 = "16'b0000000011100011" *) (* LC_LOW_BIT_POS_PROBE_OUT228 = "16'b0000000011100100" *)
(* LC_LOW_BIT_POS_PROBE_OUT229 = "16'b0000000011100101" *) (* LC_LOW_BIT_POS_PROBE_OUT23 = "16'b0000000000010111" *) (* LC_LOW_BIT_POS_PROBE_OUT230 = "16'b0000000011100110" *)
(* LC_LOW_BIT_POS_PROBE_OUT231 = "16'b0000000011100111" *) (* LC_LOW_BIT_POS_PROBE_OUT232 = "16'b0000000011101000" *) (* LC_LOW_BIT_POS_PROBE_OUT233 = "16'b0000000011101001" *)
(* LC_LOW_BIT_POS_PROBE_OUT234 = "16'b0000000011101010" *) (* LC_LOW_BIT_POS_PROBE_OUT235 = "16'b0000000011101011" *) (* LC_LOW_BIT_POS_PROBE_OUT236 = "16'b0000000011101100" *)
(* LC_LOW_BIT_POS_PROBE_OUT237 = "16'b0000000011101101" *) (* LC_LOW_BIT_POS_PROBE_OUT238 = "16'b0000000011101110" *) (* LC_LOW_BIT_POS_PROBE_OUT239 = "16'b0000000011101111" *)
(* LC_LOW_BIT_POS_PROBE_OUT24 = "16'b0000000000011000" *) (* LC_LOW_BIT_POS_PROBE_OUT240 = "16'b0000000011110000" *) (* LC_LOW_BIT_POS_PROBE_OUT241 = "16'b0000000011110001" *)
(* LC_LOW_BIT_POS_PROBE_OUT242 = "16'b0000000011110010" *) (* LC_LOW_BIT_POS_PROBE_OUT243 = "16'b0000000011110011" *) (* LC_LOW_BIT_POS_PROBE_OUT244 = "16'b0000000011110100" *)
(* LC_LOW_BIT_POS_PROBE_OUT245 = "16'b0000000011110101" *) (* LC_LOW_BIT_POS_PROBE_OUT246 = "16'b0000000011110110" *) (* LC_LOW_BIT_POS_PROBE_OUT247 = "16'b0000000011110111" *)
(* LC_LOW_BIT_POS_PROBE_OUT248 = "16'b0000000011111000" *) (* LC_LOW_BIT_POS_PROBE_OUT249 = "16'b0000000011111001" *) (* LC_LOW_BIT_POS_PROBE_OUT25 = "16'b0000000000011001" *)
(* LC_LOW_BIT_POS_PROBE_OUT250 = "16'b0000000011111010" *) (* LC_LOW_BIT_POS_PROBE_OUT251 = "16'b0000000011111011" *) (* LC_LOW_BIT_POS_PROBE_OUT252 = "16'b0000000011111100" *)
(* LC_LOW_BIT_POS_PROBE_OUT253 = "16'b0000000011111101" *) (* LC_LOW_BIT_POS_PROBE_OUT254 = "16'b0000000011111110" *) (* LC_LOW_BIT_POS_PROBE_OUT255 = "16'b0000000011111111" *)
(* LC_LOW_BIT_POS_PROBE_OUT26 = "16'b0000000000011010" *) (* LC_LOW_BIT_POS_PROBE_OUT27 = "16'b0000000000011011" *) (* LC_LOW_BIT_POS_PROBE_OUT28 = "16'b0000000000011100" *)
(* LC_LOW_BIT_POS_PROBE_OUT29 = "16'b0000000000011101" *) (* LC_LOW_BIT_POS_PROBE_OUT3 = "16'b0000000000000011" *) (* LC_LOW_BIT_POS_PROBE_OUT30 = "16'b0000000000011110" *)
(* LC_LOW_BIT_POS_PROBE_OUT31 = "16'b0000000000011111" *) (* LC_LOW_BIT_POS_PROBE_OUT32 = "16'b0000000000100000" *) (* LC_LOW_BIT_POS_PROBE_OUT33 = "16'b0000000000100001" *)
(* LC_LOW_BIT_POS_PROBE_OUT34 = "16'b0000000000100010" *) (* LC_LOW_BIT_POS_PROBE_OUT35 = "16'b0000000000100011" *) (* LC_LOW_BIT_POS_PROBE_OUT36 = "16'b0000000000100100" *)
(* LC_LOW_BIT_POS_PROBE_OUT37 = "16'b0000000000100101" *) (* LC_LOW_BIT_POS_PROBE_OUT38 = "16'b0000000000100110" *) (* LC_LOW_BIT_POS_PROBE_OUT39 = "16'b0000000000100111" *)
(* LC_LOW_BIT_POS_PROBE_OUT4 = "16'b0000000000000100" *) (* LC_LOW_BIT_POS_PROBE_OUT40 = "16'b0000000000101000" *) (* LC_LOW_BIT_POS_PROBE_OUT41 = "16'b0000000000101001" *)
(* LC_LOW_BIT_POS_PROBE_OUT42 = "16'b0000000000101010" *) (* LC_LOW_BIT_POS_PROBE_OUT43 = "16'b0000000000101011" *) (* LC_LOW_BIT_POS_PROBE_OUT44 = "16'b0000000000101100" *)
(* LC_LOW_BIT_POS_PROBE_OUT45 = "16'b0000000000101101" *) (* LC_LOW_BIT_POS_PROBE_OUT46 = "16'b0000000000101110" *) (* LC_LOW_BIT_POS_PROBE_OUT47 = "16'b0000000000101111" *)
(* LC_LOW_BIT_POS_PROBE_OUT48 = "16'b0000000000110000" *) (* LC_LOW_BIT_POS_PROBE_OUT49 = "16'b0000000000110001" *) (* LC_LOW_BIT_POS_PROBE_OUT5 = "16'b0000000000000101" *)
(* LC_LOW_BIT_POS_PROBE_OUT50 = "16'b0000000000110010" *) (* LC_LOW_BIT_POS_PROBE_OUT51 = "16'b0000000000110011" *) (* LC_LOW_BIT_POS_PROBE_OUT52 = "16'b0000000000110100" *)
(* LC_LOW_BIT_POS_PROBE_OUT53 = "16'b0000000000110101" *) (* LC_LOW_BIT_POS_PROBE_OUT54 = "16'b0000000000110110" *) (* LC_LOW_BIT_POS_PROBE_OUT55 = "16'b0000000000110111" *)
(* LC_LOW_BIT_POS_PROBE_OUT56 = "16'b0000000000111000" *) (* LC_LOW_BIT_POS_PROBE_OUT57 = "16'b0000000000111001" *) (* LC_LOW_BIT_POS_PROBE_OUT58 = "16'b0000000000111010" *)
(* LC_LOW_BIT_POS_PROBE_OUT59 = "16'b0000000000111011" *) (* LC_LOW_BIT_POS_PROBE_OUT6 = "16'b0000000000000110" *) (* LC_LOW_BIT_POS_PROBE_OUT60 = "16'b0000000000111100" *)
(* LC_LOW_BIT_POS_PROBE_OUT61 = "16'b0000000000111101" *) (* LC_LOW_BIT_POS_PROBE_OUT62 = "16'b0000000000111110" *) (* LC_LOW_BIT_POS_PROBE_OUT63 = "16'b0000000000111111" *)
(* LC_LOW_BIT_POS_PROBE_OUT64 = "16'b0000000001000000" *) (* LC_LOW_BIT_POS_PROBE_OUT65 = "16'b0000000001000001" *) (* LC_LOW_BIT_POS_PROBE_OUT66 = "16'b0000000001000010" *)
(* LC_LOW_BIT_POS_PROBE_OUT67 = "16'b0000000001000011" *) (* LC_LOW_BIT_POS_PROBE_OUT68 = "16'b0000000001000100" *) (* LC_LOW_BIT_POS_PROBE_OUT69 = "16'b0000000001000101" *)
(* LC_LOW_BIT_POS_PROBE_OUT7 = "16'b0000000000000111" *) (* LC_LOW_BIT_POS_PROBE_OUT70 = "16'b0000000001000110" *) (* LC_LOW_BIT_POS_PROBE_OUT71 = "16'b0000000001000111" *)
(* LC_LOW_BIT_POS_PROBE_OUT72 = "16'b0000000001001000" *) (* LC_LOW_BIT_POS_PROBE_OUT73 = "16'b0000000001001001" *) (* LC_LOW_BIT_POS_PROBE_OUT74 = "16'b0000000001001010" *)
(* LC_LOW_BIT_POS_PROBE_OUT75 = "16'b0000000001001011" *) (* LC_LOW_BIT_POS_PROBE_OUT76 = "16'b0000000001001100" *) (* LC_LOW_BIT_POS_PROBE_OUT77 = "16'b0000000001001101" *)
(* LC_LOW_BIT_POS_PROBE_OUT78 = "16'b0000000001001110" *) (* LC_LOW_BIT_POS_PROBE_OUT79 = "16'b0000000001001111" *) (* LC_LOW_BIT_POS_PROBE_OUT8 = "16'b0000000000001000" *)
(* LC_LOW_BIT_POS_PROBE_OUT80 = "16'b0000000001010000" *) (* LC_LOW_BIT_POS_PROBE_OUT81 = "16'b0000000001010001" *) (* LC_LOW_BIT_POS_PROBE_OUT82 = "16'b0000000001010010" *)
(* LC_LOW_BIT_POS_PROBE_OUT83 = "16'b0000000001010011" *) (* LC_LOW_BIT_POS_PROBE_OUT84 = "16'b0000000001010100" *) (* LC_LOW_BIT_POS_PROBE_OUT85 = "16'b0000000001010101" *)
(* LC_LOW_BIT_POS_PROBE_OUT86 = "16'b0000000001010110" *) (* LC_LOW_BIT_POS_PROBE_OUT87 = "16'b0000000001010111" *) (* LC_LOW_BIT_POS_PROBE_OUT88 = "16'b0000000001011000" *)
(* LC_LOW_BIT_POS_PROBE_OUT89 = "16'b0000000001011001" *) (* LC_LOW_BIT_POS_PROBE_OUT9 = "16'b0000000000001001" *) (* LC_LOW_BIT_POS_PROBE_OUT90 = "16'b0000000001011010" *)
(* LC_LOW_BIT_POS_PROBE_OUT91 = "16'b0000000001011011" *) (* LC_LOW_BIT_POS_PROBE_OUT92 = "16'b0000000001011100" *) (* LC_LOW_BIT_POS_PROBE_OUT93 = "16'b0000000001011101" *)
(* LC_LOW_BIT_POS_PROBE_OUT94 = "16'b0000000001011110" *) (* LC_LOW_BIT_POS_PROBE_OUT95 = "16'b0000000001011111" *) (* LC_LOW_BIT_POS_PROBE_OUT96 = "16'b0000000001100000" *)
(* LC_LOW_BIT_POS_PROBE_OUT97 = "16'b0000000001100001" *) (* LC_LOW_BIT_POS_PROBE_OUT98 = "16'b0000000001100010" *) (* LC_LOW_BIT_POS_PROBE_OUT99 = "16'b0000000001100011" *)
(* LC_PROBE_IN_WIDTH_STRING = "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) (* LC_PROBE_OUT_HIGH_BIT_POS_STRING = "4096'b0000000011111111000000001111111000000000111111010000000011111100000000001111101100000000111110100000000011111001000000001111100000000000111101110000000011110110000000001111010100000000111101000000000011110011000000001111001000000000111100010000000011110000000000001110111100000000111011100000000011101101000000001110110000000000111010110000000011101010000000001110100100000000111010000000000011100111000000001110011000000000111001010000000011100100000000001110001100000000111000100000000011100001000000001110000000000000110111110000000011011110000000001101110100000000110111000000000011011011000000001101101000000000110110010000000011011000000000001101011100000000110101100000000011010101000000001101010000000000110100110000000011010010000000001101000100000000110100000000000011001111000000001100111000000000110011010000000011001100000000001100101100000000110010100000000011001001000000001100100000000000110001110000000011000110000000001100010100000000110001000000000011000011000000001100001000000000110000010000000011000000000000001011111100000000101111100000000010111101000000001011110000000000101110110000000010111010000000001011100100000000101110000000000010110111000000001011011000000000101101010000000010110100000000001011001100000000101100100000000010110001000000001011000000000000101011110000000010101110000000001010110100000000101011000000000010101011000000001010101000000000101010010000000010101000000000001010011100000000101001100000000010100101000000001010010000000000101000110000000010100010000000001010000100000000101000000000000010011111000000001001111000000000100111010000000010011100000000001001101100000000100110100000000010011001000000001001100000000000100101110000000010010110000000001001010100000000100101000000000010010011000000001001001000000000100100010000000010010000000000001000111100000000100011100000000010001101000000001000110000000000100010110000000010001010000000001000100100000000100010000000000010000111000000001000011000000000100001010000000010000100000000001000001100000000100000100000000010000001000000001000000000000000011111110000000001111110000000000111110100000000011111000000000001111011000000000111101000000000011110010000000001111000000000000111011100000000011101100000000001110101000000000111010000000000011100110000000001110010000000000111000100000000011100000000000001101111000000000110111000000000011011010000000001101100000000000110101100000000011010100000000001101001000000000110100000000000011001110000000001100110000000000110010100000000011001000000000001100011000000000110001000000000011000010000000001100000000000000101111100000000010111100000000001011101000000000101110000000000010110110000000001011010000000000101100100000000010110000000000001010111000000000101011000000000010101010000000001010100000000000101001100000000010100100000000001010001000000000101000000000000010011110000000001001110000000000100110100000000010011000000000001001011000000000100101000000000010010010000000001001000000000000100011100000000010001100000000001000101000000000100010000000000010000110000000001000010000000000100000100000000010000000000000000111111000000000011111000000000001111010000000000111100000000000011101100000000001110100000000000111001000000000011100000000000001101110000000000110110000000000011010100000000001101000000000000110011000000000011001000000000001100010000000000110000000000000010111100000000001011100000000000101101000000000010110000000000001010110000000000101010000000000010100100000000001010000000000000100111000000000010011000000000001001010000000000100100000000000010001100000000001000100000000000100001000000000010000000000000000111110000000000011110000000000001110100000000000111000000000000011011000000000001101000000000000110010000000000011000000000000001011100000000000101100000000000010101000000000001010000000000000100110000000000010010000000000001000100000000000100000000000000001111000000000000111000000000000011010000000000001100000000000000101100000000000010100000000000001001000000000000100000000000000001110000000000000110000000000000010100000000000001000000000000000011000000000000001000000000000000010000000000000000" *) (* LC_PROBE_OUT_INIT_VAL_STRING = "256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
(* LC_PROBE_OUT_LOW_BIT_POS_STRING = "4096'b0000000011111111000000001111111000000000111111010000000011111100000000001111101100000000111110100000000011111001000000001111100000000000111101110000000011110110000000001111010100000000111101000000000011110011000000001111001000000000111100010000000011110000000000001110111100000000111011100000000011101101000000001110110000000000111010110000000011101010000000001110100100000000111010000000000011100111000000001110011000000000111001010000000011100100000000001110001100000000111000100000000011100001000000001110000000000000110111110000000011011110000000001101110100000000110111000000000011011011000000001101101000000000110110010000000011011000000000001101011100000000110101100000000011010101000000001101010000000000110100110000000011010010000000001101000100000000110100000000000011001111000000001100111000000000110011010000000011001100000000001100101100000000110010100000000011001001000000001100100000000000110001110000000011000110000000001100010100000000110001000000000011000011000000001100001000000000110000010000000011000000000000001011111100000000101111100000000010111101000000001011110000000000101110110000000010111010000000001011100100000000101110000000000010110111000000001011011000000000101101010000000010110100000000001011001100000000101100100000000010110001000000001011000000000000101011110000000010101110000000001010110100000000101011000000000010101011000000001010101000000000101010010000000010101000000000001010011100000000101001100000000010100101000000001010010000000000101000110000000010100010000000001010000100000000101000000000000010011111000000001001111000000000100111010000000010011100000000001001101100000000100110100000000010011001000000001001100000000000100101110000000010010110000000001001010100000000100101000000000010010011000000001001001000000000100100010000000010010000000000001000111100000000100011100000000010001101000000001000110000000000100010110000000010001010000000001000100100000000100010000000000010000111000000001000011000000000100001010000000010000100000000001000001100000000100000100000000010000001000000001000000000000000011111110000000001111110000000000111110100000000011111000000000001111011000000000111101000000000011110010000000001111000000000000111011100000000011101100000000001110101000000000111010000000000011100110000000001110010000000000111000100000000011100000000000001101111000000000110111000000000011011010000000001101100000000000110101100000000011010100000000001101001000000000110100000000000011001110000000001100110000000000110010100000000011001000000000001100011000000000110001000000000011000010000000001100000000000000101111100000000010111100000000001011101000000000101110000000000010110110000000001011010000000000101100100000000010110000000000001010111000000000101011000000000010101010000000001010100000000000101001100000000010100100000000001010001000000000101000000000000010011110000000001001110000000000100110100000000010011000000000001001011000000000100101000000000010010010000000001001000000000000100011100000000010001100000000001000101000000000100010000000000010000110000000001000010000000000100000100000000010000000000000000111111000000000011111000000000001111010000000000111100000000000011101100000000001110100000000000111001000000000011100000000000001101110000000000110110000000000011010100000000001101000000000000110011000000000011001000000000001100010000000000110000000000000010111100000000001011100000000000101101000000000010110000000000001010110000000000101010000000000010100100000000001010000000000000100111000000000010011000000000001001010000000000100100000000000010001100000000001000100000000000100001000000000010000000000000000111110000000000011110000000000001110100000000000111000000000000011011000000000001101000000000000110010000000000011000000000000001011100000000000101100000000000010101000000000001010000000000000100110000000000010010000000000001000100000000000100000000000000001111000000000000111000000000000011010000000000001100000000000000101100000000000010100000000000001001000000000000100000000000000001110000000000000110000000000000010100000000000001000000000000000011000000000000001000000000000000010000000000000000" *) (* LC_PROBE_OUT_WIDTH_STRING = "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) (* LC_TOTAL_PROBE_IN_WIDTH = "4" *)
(* LC_TOTAL_PROBE_OUT_WIDTH = "0" *) (* ORIG_REF_NAME = "vio_v3_0_13_vio" *) (* dont_touch = "true" *)
module vio_0_vio_v3_0_13_vio
(clk,
probe_in0,
probe_in1,
probe_in2,
probe_in3,
probe_in4,
probe_in5,
probe_in6,
probe_in7,
probe_in8,
probe_in9,
probe_in10,
probe_in11,
probe_in12,
probe_in13,
probe_in14,
probe_in15,
probe_in16,
probe_in17,
probe_in18,
probe_in19,
probe_in20,
probe_in21,
probe_in22,
probe_in23,
probe_in24,
probe_in25,
probe_in26,
probe_in27,
probe_in28,
probe_in29,
probe_in30,
probe_in31,
probe_in32,
probe_in33,
probe_in34,
probe_in35,
probe_in36,
probe_in37,
probe_in38,
probe_in39,
probe_in40,
probe_in41,
probe_in42,
probe_in43,
probe_in44,
probe_in45,
probe_in46,
probe_in47,
probe_in48,
probe_in49,
probe_in50,
probe_in51,
probe_in52,
probe_in53,
probe_in54,
probe_in55,
probe_in56,
probe_in57,
probe_in58,
probe_in59,
probe_in60,
probe_in61,
probe_in62,
probe_in63,
probe_in64,
probe_in65,
probe_in66,
probe_in67,
probe_in68,
probe_in69,
probe_in70,
probe_in71,
probe_in72,
probe_in73,
probe_in74,
probe_in75,
probe_in76,
probe_in77,
probe_in78,
probe_in79,
probe_in80,
probe_in81,
probe_in82,
probe_in83,
probe_in84,
probe_in85,
probe_in86,
probe_in87,
probe_in88,
probe_in89,
probe_in90,
probe_in91,
probe_in92,
probe_in93,
probe_in94,
probe_in95,
probe_in96,
probe_in97,
probe_in98,
probe_in99,
probe_in100,
probe_in101,
probe_in102,
probe_in103,
probe_in104,
probe_in105,
probe_in106,
probe_in107,
probe_in108,
probe_in109,
probe_in110,
probe_in111,
probe_in112,
probe_in113,
probe_in114,
probe_in115,
probe_in116,
probe_in117,
probe_in118,
probe_in119,
probe_in120,
probe_in121,
probe_in122,
probe_in123,
probe_in124,
probe_in125,
probe_in126,
probe_in127,
probe_in128,
probe_in129,
probe_in130,
probe_in131,
probe_in132,
probe_in133,
probe_in134,
probe_in135,
probe_in136,
probe_in137,
probe_in138,
probe_in139,
probe_in140,
probe_in141,
probe_in142,
probe_in143,
probe_in144,
probe_in145,
probe_in146,
probe_in147,
probe_in148,
probe_in149,
probe_in150,
probe_in151,
probe_in152,
probe_in153,
probe_in154,
probe_in155,
probe_in156,
probe_in157,
probe_in158,
probe_in159,
probe_in160,
probe_in161,
probe_in162,
probe_in163,
probe_in164,
probe_in165,
probe_in166,
probe_in167,
probe_in168,
probe_in169,
probe_in170,
probe_in171,
probe_in172,
probe_in173,
probe_in174,
probe_in175,
probe_in176,
probe_in177,
probe_in178,
probe_in179,
probe_in180,
probe_in181,
probe_in182,
probe_in183,
probe_in184,
probe_in185,
probe_in186,
probe_in187,
probe_in188,
probe_in189,
probe_in190,
probe_in191,
probe_in192,
probe_in193,
probe_in194,
probe_in195,
probe_in196,
probe_in197,
probe_in198,
probe_in199,
probe_in200,
probe_in201,
probe_in202,
probe_in203,
probe_in204,
probe_in205,
probe_in206,
probe_in207,
probe_in208,
probe_in209,
probe_in210,
probe_in211,
probe_in212,
probe_in213,
probe_in214,
probe_in215,
probe_in216,
probe_in217,
probe_in218,
probe_in219,
probe_in220,
probe_in221,
probe_in222,
probe_in223,
probe_in224,
probe_in225,
probe_in226,
probe_in227,
probe_in228,
probe_in229,
probe_in230,
probe_in231,
probe_in232,
probe_in233,
probe_in234,
probe_in235,
probe_in236,
probe_in237,
probe_in238,
probe_in239,
probe_in240,
probe_in241,
probe_in242,
probe_in243,
probe_in244,
probe_in245,
probe_in246,
probe_in247,
probe_in248,
probe_in249,
probe_in250,
probe_in251,
probe_in252,
probe_in253,
probe_in254,
probe_in255,
sl_iport0,
sl_oport0,
probe_out0,
probe_out1,
probe_out2,
probe_out3,
probe_out4,
probe_out5,
probe_out6,
probe_out7,
probe_out8,
probe_out9,
probe_out10,
probe_out11,
probe_out12,
probe_out13,
probe_out14,
probe_out15,
probe_out16,
probe_out17,
probe_out18,
probe_out19,
probe_out20,
probe_out21,
probe_out22,
probe_out23,
probe_out24,
probe_out25,
probe_out26,
probe_out27,
probe_out28,
probe_out29,
probe_out30,
probe_out31,
probe_out32,
probe_out33,
probe_out34,
probe_out35,
probe_out36,
probe_out37,
probe_out38,
probe_out39,
probe_out40,
probe_out41,
probe_out42,
probe_out43,
probe_out44,
probe_out45,
probe_out46,
probe_out47,
probe_out48,
probe_out49,
probe_out50,
probe_out51,
probe_out52,
probe_out53,
probe_out54,
probe_out55,
probe_out56,
probe_out57,
probe_out58,
probe_out59,
probe_out60,
probe_out61,
probe_out62,
probe_out63,
probe_out64,
probe_out65,
probe_out66,
probe_out67,
probe_out68,
probe_out69,
probe_out70,
probe_out71,
probe_out72,
probe_out73,
probe_out74,
probe_out75,
probe_out76,
probe_out77,
probe_out78,
probe_out79,
probe_out80,
probe_out81,
probe_out82,
probe_out83,
probe_out84,
probe_out85,
probe_out86,
probe_out87,
probe_out88,
probe_out89,
probe_out90,
probe_out91,
probe_out92,
probe_out93,
probe_out94,
probe_out95,
probe_out96,
probe_out97,
probe_out98,
probe_out99,
probe_out100,
probe_out101,
probe_out102,
probe_out103,
probe_out104,
probe_out105,
probe_out106,
probe_out107,
probe_out108,
probe_out109,
probe_out110,
probe_out111,
probe_out112,
probe_out113,
probe_out114,
probe_out115,
probe_out116,
probe_out117,
probe_out118,
probe_out119,
probe_out120,
probe_out121,
probe_out122,
probe_out123,
probe_out124,
probe_out125,
probe_out126,
probe_out127,
probe_out128,
probe_out129,
probe_out130,
probe_out131,
probe_out132,
probe_out133,
probe_out134,
probe_out135,
probe_out136,
probe_out137,
probe_out138,
probe_out139,
probe_out140,
probe_out141,
probe_out142,
probe_out143,
probe_out144,
probe_out145,
probe_out146,
probe_out147,
probe_out148,
probe_out149,
probe_out150,
probe_out151,
probe_out152,
probe_out153,
probe_out154,
probe_out155,
probe_out156,
probe_out157,
probe_out158,
probe_out159,
probe_out160,
probe_out161,
probe_out162,
probe_out163,
probe_out164,
probe_out165,
probe_out166,
probe_out167,
probe_out168,
probe_out169,
probe_out170,
probe_out171,
probe_out172,
probe_out173,
probe_out174,
probe_out175,
probe_out176,
probe_out177,
probe_out178,
probe_out179,
probe_out180,
probe_out181,
probe_out182,
probe_out183,
probe_out184,
probe_out185,
probe_out186,
probe_out187,
probe_out188,
probe_out189,
probe_out190,
probe_out191,
probe_out192,
probe_out193,
probe_out194,
probe_out195,
probe_out196,
probe_out197,
probe_out198,
probe_out199,
probe_out200,
probe_out201,
probe_out202,
probe_out203,
probe_out204,
probe_out205,
probe_out206,
probe_out207,
probe_out208,
probe_out209,
probe_out210,
probe_out211,
probe_out212,
probe_out213,
probe_out214,
probe_out215,
probe_out216,
probe_out217,
probe_out218,
probe_out219,
probe_out220,
probe_out221,
probe_out222,
probe_out223,
probe_out224,
probe_out225,
probe_out226,
probe_out227,
probe_out228,
probe_out229,
probe_out230,
probe_out231,
probe_out232,
probe_out233,
probe_out234,
probe_out235,
probe_out236,
probe_out237,
probe_out238,
probe_out239,
probe_out240,
probe_out241,
probe_out242,
probe_out243,
probe_out244,
probe_out245,
probe_out246,
probe_out247,
probe_out248,
probe_out249,
probe_out250,
probe_out251,
probe_out252,
probe_out253,
probe_out254,
probe_out255);
input clk;
input [0:0]probe_in0;
input [0:0]probe_in1;
input [0:0]probe_in2;
input [0:0]probe_in3;
input [0:0]probe_in4;
input [0:0]probe_in5;
input [0:0]probe_in6;
input [0:0]probe_in7;
input [0:0]probe_in8;
input [0:0]probe_in9;
input [0:0]probe_in10;
input [0:0]probe_in11;
input [0:0]probe_in12;
input [0:0]probe_in13;
input [0:0]probe_in14;
input [0:0]probe_in15;
input [0:0]probe_in16;
input [0:0]probe_in17;
input [0:0]probe_in18;
input [0:0]probe_in19;
input [0:0]probe_in20;
input [0:0]probe_in21;
input [0:0]probe_in22;
input [0:0]probe_in23;
input [0:0]probe_in24;
input [0:0]probe_in25;
input [0:0]probe_in26;
input [0:0]probe_in27;
input [0:0]probe_in28;
input [0:0]probe_in29;
input [0:0]probe_in30;
input [0:0]probe_in31;
input [0:0]probe_in32;
input [0:0]probe_in33;
input [0:0]probe_in34;
input [0:0]probe_in35;
input [0:0]probe_in36;
input [0:0]probe_in37;
input [0:0]probe_in38;
input [0:0]probe_in39;
input [0:0]probe_in40;
input [0:0]probe_in41;
input [0:0]probe_in42;
input [0:0]probe_in43;
input [0:0]probe_in44;
input [0:0]probe_in45;
input [0:0]probe_in46;
input [0:0]probe_in47;
input [0:0]probe_in48;
input [0:0]probe_in49;
input [0:0]probe_in50;
input [0:0]probe_in51;
input [0:0]probe_in52;
input [0:0]probe_in53;
input [0:0]probe_in54;
input [0:0]probe_in55;
input [0:0]probe_in56;
input [0:0]probe_in57;
input [0:0]probe_in58;
input [0:0]probe_in59;
input [0:0]probe_in60;
input [0:0]probe_in61;
input [0:0]probe_in62;
input [0:0]probe_in63;
input [0:0]probe_in64;
input [0:0]probe_in65;
input [0:0]probe_in66;
input [0:0]probe_in67;
input [0:0]probe_in68;
input [0:0]probe_in69;
input [0:0]probe_in70;
input [0:0]probe_in71;
input [0:0]probe_in72;
input [0:0]probe_in73;
input [0:0]probe_in74;
input [0:0]probe_in75;
input [0:0]probe_in76;
input [0:0]probe_in77;
input [0:0]probe_in78;
input [0:0]probe_in79;
input [0:0]probe_in80;
input [0:0]probe_in81;
input [0:0]probe_in82;
input [0:0]probe_in83;
input [0:0]probe_in84;
input [0:0]probe_in85;
input [0:0]probe_in86;
input [0:0]probe_in87;
input [0:0]probe_in88;
input [0:0]probe_in89;
input [0:0]probe_in90;
input [0:0]probe_in91;
input [0:0]probe_in92;
input [0:0]probe_in93;
input [0:0]probe_in94;
input [0:0]probe_in95;
input [0:0]probe_in96;
input [0:0]probe_in97;
input [0:0]probe_in98;
input [0:0]probe_in99;
input [0:0]probe_in100;
input [0:0]probe_in101;
input [0:0]probe_in102;
input [0:0]probe_in103;
input [0:0]probe_in104;
input [0:0]probe_in105;
input [0:0]probe_in106;
input [0:0]probe_in107;
input [0:0]probe_in108;
input [0:0]probe_in109;
input [0:0]probe_in110;
input [0:0]probe_in111;
input [0:0]probe_in112;
input [0:0]probe_in113;
input [0:0]probe_in114;
input [0:0]probe_in115;
input [0:0]probe_in116;
input [0:0]probe_in117;
input [0:0]probe_in118;
input [0:0]probe_in119;
input [0:0]probe_in120;
input [0:0]probe_in121;
input [0:0]probe_in122;
input [0:0]probe_in123;
input [0:0]probe_in124;
input [0:0]probe_in125;
input [0:0]probe_in126;
input [0:0]probe_in127;
input [0:0]probe_in128;
input [0:0]probe_in129;
input [0:0]probe_in130;
input [0:0]probe_in131;
input [0:0]probe_in132;
input [0:0]probe_in133;
input [0:0]probe_in134;
input [0:0]probe_in135;
input [0:0]probe_in136;
input [0:0]probe_in137;
input [0:0]probe_in138;
input [0:0]probe_in139;
input [0:0]probe_in140;
input [0:0]probe_in141;
input [0:0]probe_in142;
input [0:0]probe_in143;
input [0:0]probe_in144;
input [0:0]probe_in145;
input [0:0]probe_in146;
input [0:0]probe_in147;
input [0:0]probe_in148;
input [0:0]probe_in149;
input [0:0]probe_in150;
input [0:0]probe_in151;
input [0:0]probe_in152;
input [0:0]probe_in153;
input [0:0]probe_in154;
input [0:0]probe_in155;
input [0:0]probe_in156;
input [0:0]probe_in157;
input [0:0]probe_in158;
input [0:0]probe_in159;
input [0:0]probe_in160;
input [0:0]probe_in161;
input [0:0]probe_in162;
input [0:0]probe_in163;
input [0:0]probe_in164;
input [0:0]probe_in165;
input [0:0]probe_in166;
input [0:0]probe_in167;
input [0:0]probe_in168;
input [0:0]probe_in169;
input [0:0]probe_in170;
input [0:0]probe_in171;
input [0:0]probe_in172;
input [0:0]probe_in173;
input [0:0]probe_in174;
input [0:0]probe_in175;
input [0:0]probe_in176;
input [0:0]probe_in177;
input [0:0]probe_in178;
input [0:0]probe_in179;
input [0:0]probe_in180;
input [0:0]probe_in181;
input [0:0]probe_in182;
input [0:0]probe_in183;
input [0:0]probe_in184;
input [0:0]probe_in185;
input [0:0]probe_in186;
input [0:0]probe_in187;
input [0:0]probe_in188;
input [0:0]probe_in189;
input [0:0]probe_in190;
input [0:0]probe_in191;
input [0:0]probe_in192;
input [0:0]probe_in193;
input [0:0]probe_in194;
input [0:0]probe_in195;
input [0:0]probe_in196;
input [0:0]probe_in197;
input [0:0]probe_in198;
input [0:0]probe_in199;
input [0:0]probe_in200;
input [0:0]probe_in201;
input [0:0]probe_in202;
input [0:0]probe_in203;
input [0:0]probe_in204;
input [0:0]probe_in205;
input [0:0]probe_in206;
input [0:0]probe_in207;
input [0:0]probe_in208;
input [0:0]probe_in209;
input [0:0]probe_in210;
input [0:0]probe_in211;
input [0:0]probe_in212;
input [0:0]probe_in213;
input [0:0]probe_in214;
input [0:0]probe_in215;
input [0:0]probe_in216;
input [0:0]probe_in217;
input [0:0]probe_in218;
input [0:0]probe_in219;
input [0:0]probe_in220;
input [0:0]probe_in221;
input [0:0]probe_in222;
input [0:0]probe_in223;
input [0:0]probe_in224;
input [0:0]probe_in225;
input [0:0]probe_in226;
input [0:0]probe_in227;
input [0:0]probe_in228;
input [0:0]probe_in229;
input [0:0]probe_in230;
input [0:0]probe_in231;
input [0:0]probe_in232;
input [0:0]probe_in233;
input [0:0]probe_in234;
input [0:0]probe_in235;
input [0:0]probe_in236;
input [0:0]probe_in237;
input [0:0]probe_in238;
input [0:0]probe_in239;
input [0:0]probe_in240;
input [0:0]probe_in241;
input [0:0]probe_in242;
input [0:0]probe_in243;
input [0:0]probe_in244;
input [0:0]probe_in245;
input [0:0]probe_in246;
input [0:0]probe_in247;
input [0:0]probe_in248;
input [0:0]probe_in249;
input [0:0]probe_in250;
input [0:0]probe_in251;
input [0:0]probe_in252;
input [0:0]probe_in253;
input [0:0]probe_in254;
input [0:0]probe_in255;
(* dont_touch = "true" *) input [36:0]sl_iport0;
(* dont_touch = "true" *) output [16:0]sl_oport0;
output [0:0]probe_out0;
output [0:0]probe_out1;
output [0:0]probe_out2;
output [0:0]probe_out3;
output [0:0]probe_out4;
output [0:0]probe_out5;
output [0:0]probe_out6;
output [0:0]probe_out7;
output [0:0]probe_out8;
output [0:0]probe_out9;
output [0:0]probe_out10;
output [0:0]probe_out11;
output [0:0]probe_out12;
output [0:0]probe_out13;
output [0:0]probe_out14;
output [0:0]probe_out15;
output [0:0]probe_out16;
output [0:0]probe_out17;
output [0:0]probe_out18;
output [0:0]probe_out19;
output [0:0]probe_out20;
output [0:0]probe_out21;
output [0:0]probe_out22;
output [0:0]probe_out23;
output [0:0]probe_out24;
output [0:0]probe_out25;
output [0:0]probe_out26;
output [0:0]probe_out27;
output [0:0]probe_out28;
output [0:0]probe_out29;
output [0:0]probe_out30;
output [0:0]probe_out31;
output [0:0]probe_out32;
output [0:0]probe_out33;
output [0:0]probe_out34;
output [0:0]probe_out35;
output [0:0]probe_out36;
output [0:0]probe_out37;
output [0:0]probe_out38;
output [0:0]probe_out39;
output [0:0]probe_out40;
output [0:0]probe_out41;
output [0:0]probe_out42;
output [0:0]probe_out43;
output [0:0]probe_out44;
output [0:0]probe_out45;
output [0:0]probe_out46;
output [0:0]probe_out47;
output [0:0]probe_out48;
output [0:0]probe_out49;
output [0:0]probe_out50;
output [0:0]probe_out51;
output [0:0]probe_out52;
output [0:0]probe_out53;
output [0:0]probe_out54;
output [0:0]probe_out55;
output [0:0]probe_out56;
output [0:0]probe_out57;
output [0:0]probe_out58;
output [0:0]probe_out59;
output [0:0]probe_out60;
output [0:0]probe_out61;
output [0:0]probe_out62;
output [0:0]probe_out63;
output [0:0]probe_out64;
output [0:0]probe_out65;
output [0:0]probe_out66;
output [0:0]probe_out67;
output [0:0]probe_out68;
output [0:0]probe_out69;
output [0:0]probe_out70;
output [0:0]probe_out71;
output [0:0]probe_out72;
output [0:0]probe_out73;
output [0:0]probe_out74;
output [0:0]probe_out75;
output [0:0]probe_out76;
output [0:0]probe_out77;
output [0:0]probe_out78;
output [0:0]probe_out79;
output [0:0]probe_out80;
output [0:0]probe_out81;
output [0:0]probe_out82;
output [0:0]probe_out83;
output [0:0]probe_out84;
output [0:0]probe_out85;
output [0:0]probe_out86;
output [0:0]probe_out87;
output [0:0]probe_out88;
output [0:0]probe_out89;
output [0:0]probe_out90;
output [0:0]probe_out91;
output [0:0]probe_out92;
output [0:0]probe_out93;
output [0:0]probe_out94;
output [0:0]probe_out95;
output [0:0]probe_out96;
output [0:0]probe_out97;
output [0:0]probe_out98;
output [0:0]probe_out99;
output [0:0]probe_out100;
output [0:0]probe_out101;
output [0:0]probe_out102;
output [0:0]probe_out103;
output [0:0]probe_out104;
output [0:0]probe_out105;
output [0:0]probe_out106;
output [0:0]probe_out107;
output [0:0]probe_out108;
output [0:0]probe_out109;
output [0:0]probe_out110;
output [0:0]probe_out111;
output [0:0]probe_out112;
output [0:0]probe_out113;
output [0:0]probe_out114;
output [0:0]probe_out115;
output [0:0]probe_out116;
output [0:0]probe_out117;
output [0:0]probe_out118;
output [0:0]probe_out119;
output [0:0]probe_out120;
output [0:0]probe_out121;
output [0:0]probe_out122;
output [0:0]probe_out123;
output [0:0]probe_out124;
output [0:0]probe_out125;
output [0:0]probe_out126;
output [0:0]probe_out127;
output [0:0]probe_out128;
output [0:0]probe_out129;
output [0:0]probe_out130;
output [0:0]probe_out131;
output [0:0]probe_out132;
output [0:0]probe_out133;
output [0:0]probe_out134;
output [0:0]probe_out135;
output [0:0]probe_out136;
output [0:0]probe_out137;
output [0:0]probe_out138;
output [0:0]probe_out139;
output [0:0]probe_out140;
output [0:0]probe_out141;
output [0:0]probe_out142;
output [0:0]probe_out143;
output [0:0]probe_out144;
output [0:0]probe_out145;
output [0:0]probe_out146;
output [0:0]probe_out147;
output [0:0]probe_out148;
output [0:0]probe_out149;
output [0:0]probe_out150;
output [0:0]probe_out151;
output [0:0]probe_out152;
output [0:0]probe_out153;
output [0:0]probe_out154;
output [0:0]probe_out155;
output [0:0]probe_out156;
output [0:0]probe_out157;
output [0:0]probe_out158;
output [0:0]probe_out159;
output [0:0]probe_out160;
output [0:0]probe_out161;
output [0:0]probe_out162;
output [0:0]probe_out163;
output [0:0]probe_out164;
output [0:0]probe_out165;
output [0:0]probe_out166;
output [0:0]probe_out167;
output [0:0]probe_out168;
output [0:0]probe_out169;
output [0:0]probe_out170;
output [0:0]probe_out171;
output [0:0]probe_out172;
output [0:0]probe_out173;
output [0:0]probe_out174;
output [0:0]probe_out175;
output [0:0]probe_out176;
output [0:0]probe_out177;
output [0:0]probe_out178;
output [0:0]probe_out179;
output [0:0]probe_out180;
output [0:0]probe_out181;
output [0:0]probe_out182;
output [0:0]probe_out183;
output [0:0]probe_out184;
output [0:0]probe_out185;
output [0:0]probe_out186;
output [0:0]probe_out187;
output [0:0]probe_out188;
output [0:0]probe_out189;
output [0:0]probe_out190;
output [0:0]probe_out191;
output [0:0]probe_out192;
output [0:0]probe_out193;
output [0:0]probe_out194;
output [0:0]probe_out195;
output [0:0]probe_out196;
output [0:0]probe_out197;
output [0:0]probe_out198;
output [0:0]probe_out199;
output [0:0]probe_out200;
output [0:0]probe_out201;
output [0:0]probe_out202;
output [0:0]probe_out203;
output [0:0]probe_out204;
output [0:0]probe_out205;
output [0:0]probe_out206;
output [0:0]probe_out207;
output [0:0]probe_out208;
output [0:0]probe_out209;
output [0:0]probe_out210;
output [0:0]probe_out211;
output [0:0]probe_out212;
output [0:0]probe_out213;
output [0:0]probe_out214;
output [0:0]probe_out215;
output [0:0]probe_out216;
output [0:0]probe_out217;
output [0:0]probe_out218;
output [0:0]probe_out219;
output [0:0]probe_out220;
output [0:0]probe_out221;
output [0:0]probe_out222;
output [0:0]probe_out223;
output [0:0]probe_out224;
output [0:0]probe_out225;
output [0:0]probe_out226;
output [0:0]probe_out227;
output [0:0]probe_out228;
output [0:0]probe_out229;
output [0:0]probe_out230;
output [0:0]probe_out231;
output [0:0]probe_out232;
output [0:0]probe_out233;
output [0:0]probe_out234;
output [0:0]probe_out235;
output [0:0]probe_out236;
output [0:0]probe_out237;
output [0:0]probe_out238;
output [0:0]probe_out239;
output [0:0]probe_out240;
output [0:0]probe_out241;
output [0:0]probe_out242;
output [0:0]probe_out243;
output [0:0]probe_out244;
output [0:0]probe_out245;
output [0:0]probe_out246;
output [0:0]probe_out247;
output [0:0]probe_out248;
output [0:0]probe_out249;
output [0:0]probe_out250;
output [0:0]probe_out251;
output [0:0]probe_out252;
output [0:0]probe_out253;
output [0:0]probe_out254;
output [0:0]probe_out255;
wire \<const0> ;
wire [11:0]Bus_Data_out;
wire DECODER_INST_n_1;
wire DECODER_INST_n_2;
wire DECODER_INST_n_3;
wire DECODER_INST_n_4;
wire [16:0]bus_addr;
(* DONT_TOUCH *) wire bus_clk;
wire \bus_data_int_reg_n_0_[0] ;
wire \bus_data_int_reg_n_0_[10] ;
wire \bus_data_int_reg_n_0_[11] ;
wire \bus_data_int_reg_n_0_[12] ;
wire \bus_data_int_reg_n_0_[13] ;
wire \bus_data_int_reg_n_0_[14] ;
wire \bus_data_int_reg_n_0_[15] ;
wire \bus_data_int_reg_n_0_[2] ;
wire \bus_data_int_reg_n_0_[3] ;
wire \bus_data_int_reg_n_0_[4] ;
wire \bus_data_int_reg_n_0_[5] ;
wire \bus_data_int_reg_n_0_[6] ;
wire \bus_data_int_reg_n_0_[7] ;
wire \bus_data_int_reg_n_0_[8] ;
wire \bus_data_int_reg_n_0_[9] ;
wire bus_den;
wire [15:0]bus_di;
wire [15:0]bus_do;
wire bus_drdy;
wire bus_dwe;
wire bus_rst;
wire clk;
wire p_0_in;
wire [0:0]probe_in0;
wire [0:0]probe_in1;
wire [0:0]probe_in2;
wire [0:0]probe_in3;
(* DONT_TOUCH *) wire [36:0]sl_iport0;
(* DONT_TOUCH *) wire [16:0]sl_oport0;
assign probe_out0[0] = \<const0> ;
assign probe_out1[0] = \<const0> ;
assign probe_out10[0] = \<const0> ;
assign probe_out100[0] = \<const0> ;
assign probe_out101[0] = \<const0> ;
assign probe_out102[0] = \<const0> ;
assign probe_out103[0] = \<const0> ;
assign probe_out104[0] = \<const0> ;
assign probe_out105[0] = \<const0> ;
assign probe_out106[0] = \<const0> ;
assign probe_out107[0] = \<const0> ;
assign probe_out108[0] = \<const0> ;
assign probe_out109[0] = \<const0> ;
assign probe_out11[0] = \<const0> ;
assign probe_out110[0] = \<const0> ;
assign probe_out111[0] = \<const0> ;
assign probe_out112[0] = \<const0> ;
assign probe_out113[0] = \<const0> ;
assign probe_out114[0] = \<const0> ;
assign probe_out115[0] = \<const0> ;
assign probe_out116[0] = \<const0> ;
assign probe_out117[0] = \<const0> ;
assign probe_out118[0] = \<const0> ;
assign probe_out119[0] = \<const0> ;
assign probe_out12[0] = \<const0> ;
assign probe_out120[0] = \<const0> ;
assign probe_out121[0] = \<const0> ;
assign probe_out122[0] = \<const0> ;
assign probe_out123[0] = \<const0> ;
assign probe_out124[0] = \<const0> ;
assign probe_out125[0] = \<const0> ;
assign probe_out126[0] = \<const0> ;
assign probe_out127[0] = \<const0> ;
assign probe_out128[0] = \<const0> ;
assign probe_out129[0] = \<const0> ;
assign probe_out13[0] = \<const0> ;
assign probe_out130[0] = \<const0> ;
assign probe_out131[0] = \<const0> ;
assign probe_out132[0] = \<const0> ;
assign probe_out133[0] = \<const0> ;
assign probe_out134[0] = \<const0> ;
assign probe_out135[0] = \<const0> ;
assign probe_out136[0] = \<const0> ;
assign probe_out137[0] = \<const0> ;
assign probe_out138[0] = \<const0> ;
assign probe_out139[0] = \<const0> ;
assign probe_out14[0] = \<const0> ;
assign probe_out140[0] = \<const0> ;
assign probe_out141[0] = \<const0> ;
assign probe_out142[0] = \<const0> ;
assign probe_out143[0] = \<const0> ;
assign probe_out144[0] = \<const0> ;
assign probe_out145[0] = \<const0> ;
assign probe_out146[0] = \<const0> ;
assign probe_out147[0] = \<const0> ;
assign probe_out148[0] = \<const0> ;
assign probe_out149[0] = \<const0> ;
assign probe_out15[0] = \<const0> ;
assign probe_out150[0] = \<const0> ;
assign probe_out151[0] = \<const0> ;
assign probe_out152[0] = \<const0> ;
assign probe_out153[0] = \<const0> ;
assign probe_out154[0] = \<const0> ;
assign probe_out155[0] = \<const0> ;
assign probe_out156[0] = \<const0> ;
assign probe_out157[0] = \<const0> ;
assign probe_out158[0] = \<const0> ;
assign probe_out159[0] = \<const0> ;
assign probe_out16[0] = \<const0> ;
assign probe_out160[0] = \<const0> ;
assign probe_out161[0] = \<const0> ;
assign probe_out162[0] = \<const0> ;
assign probe_out163[0] = \<const0> ;
assign probe_out164[0] = \<const0> ;
assign probe_out165[0] = \<const0> ;
assign probe_out166[0] = \<const0> ;
assign probe_out167[0] = \<const0> ;
assign probe_out168[0] = \<const0> ;
assign probe_out169[0] = \<const0> ;
assign probe_out17[0] = \<const0> ;
assign probe_out170[0] = \<const0> ;
assign probe_out171[0] = \<const0> ;
assign probe_out172[0] = \<const0> ;
assign probe_out173[0] = \<const0> ;
assign probe_out174[0] = \<const0> ;
assign probe_out175[0] = \<const0> ;
assign probe_out176[0] = \<const0> ;
assign probe_out177[0] = \<const0> ;
assign probe_out178[0] = \<const0> ;
assign probe_out179[0] = \<const0> ;
assign probe_out18[0] = \<const0> ;
assign probe_out180[0] = \<const0> ;
assign probe_out181[0] = \<const0> ;
assign probe_out182[0] = \<const0> ;
assign probe_out183[0] = \<const0> ;
assign probe_out184[0] = \<const0> ;
assign probe_out185[0] = \<const0> ;
assign probe_out186[0] = \<const0> ;
assign probe_out187[0] = \<const0> ;
assign probe_out188[0] = \<const0> ;
assign probe_out189[0] = \<const0> ;
assign probe_out19[0] = \<const0> ;
assign probe_out190[0] = \<const0> ;
assign probe_out191[0] = \<const0> ;
assign probe_out192[0] = \<const0> ;
assign probe_out193[0] = \<const0> ;
assign probe_out194[0] = \<const0> ;
assign probe_out195[0] = \<const0> ;
assign probe_out196[0] = \<const0> ;
assign probe_out197[0] = \<const0> ;
assign probe_out198[0] = \<const0> ;
assign probe_out199[0] = \<const0> ;
assign probe_out2[0] = \<const0> ;
assign probe_out20[0] = \<const0> ;
assign probe_out200[0] = \<const0> ;
assign probe_out201[0] = \<const0> ;
assign probe_out202[0] = \<const0> ;
assign probe_out203[0] = \<const0> ;
assign probe_out204[0] = \<const0> ;
assign probe_out205[0] = \<const0> ;
assign probe_out206[0] = \<const0> ;
assign probe_out207[0] = \<const0> ;
assign probe_out208[0] = \<const0> ;
assign probe_out209[0] = \<const0> ;
assign probe_out21[0] = \<const0> ;
assign probe_out210[0] = \<const0> ;
assign probe_out211[0] = \<const0> ;
assign probe_out212[0] = \<const0> ;
assign probe_out213[0] = \<const0> ;
assign probe_out214[0] = \<const0> ;
assign probe_out215[0] = \<const0> ;
assign probe_out216[0] = \<const0> ;
assign probe_out217[0] = \<const0> ;
assign probe_out218[0] = \<const0> ;
assign probe_out219[0] = \<const0> ;
assign probe_out22[0] = \<const0> ;
assign probe_out220[0] = \<const0> ;
assign probe_out221[0] = \<const0> ;
assign probe_out222[0] = \<const0> ;
assign probe_out223[0] = \<const0> ;
assign probe_out224[0] = \<const0> ;
assign probe_out225[0] = \<const0> ;
assign probe_out226[0] = \<const0> ;
assign probe_out227[0] = \<const0> ;
assign probe_out228[0] = \<const0> ;
assign probe_out229[0] = \<const0> ;
assign probe_out23[0] = \<const0> ;
assign probe_out230[0] = \<const0> ;
assign probe_out231[0] = \<const0> ;
assign probe_out232[0] = \<const0> ;
assign probe_out233[0] = \<const0> ;
assign probe_out234[0] = \<const0> ;
assign probe_out235[0] = \<const0> ;
assign probe_out236[0] = \<const0> ;
assign probe_out237[0] = \<const0> ;
assign probe_out238[0] = \<const0> ;
assign probe_out239[0] = \<const0> ;
assign probe_out24[0] = \<const0> ;
assign probe_out240[0] = \<const0> ;
assign probe_out241[0] = \<const0> ;
assign probe_out242[0] = \<const0> ;
assign probe_out243[0] = \<const0> ;
assign probe_out244[0] = \<const0> ;
assign probe_out245[0] = \<const0> ;
assign probe_out246[0] = \<const0> ;
assign probe_out247[0] = \<const0> ;
assign probe_out248[0] = \<const0> ;
assign probe_out249[0] = \<const0> ;
assign probe_out25[0] = \<const0> ;
assign probe_out250[0] = \<const0> ;
assign probe_out251[0] = \<const0> ;
assign probe_out252[0] = \<const0> ;
assign probe_out253[0] = \<const0> ;
assign probe_out254[0] = \<const0> ;
assign probe_out255[0] = \<const0> ;
assign probe_out26[0] = \<const0> ;
assign probe_out27[0] = \<const0> ;
assign probe_out28[0] = \<const0> ;
assign probe_out29[0] = \<const0> ;
assign probe_out3[0] = \<const0> ;
assign probe_out30[0] = \<const0> ;
assign probe_out31[0] = \<const0> ;
assign probe_out32[0] = \<const0> ;
assign probe_out33[0] = \<const0> ;
assign probe_out34[0] = \<const0> ;
assign probe_out35[0] = \<const0> ;
assign probe_out36[0] = \<const0> ;
assign probe_out37[0] = \<const0> ;
assign probe_out38[0] = \<const0> ;
assign probe_out39[0] = \<const0> ;
assign probe_out4[0] = \<const0> ;
assign probe_out40[0] = \<const0> ;
assign probe_out41[0] = \<const0> ;
assign probe_out42[0] = \<const0> ;
assign probe_out43[0] = \<const0> ;
assign probe_out44[0] = \<const0> ;
assign probe_out45[0] = \<const0> ;
assign probe_out46[0] = \<const0> ;
assign probe_out47[0] = \<const0> ;
assign probe_out48[0] = \<const0> ;
assign probe_out49[0] = \<const0> ;
assign probe_out5[0] = \<const0> ;
assign probe_out50[0] = \<const0> ;
assign probe_out51[0] = \<const0> ;
assign probe_out52[0] = \<const0> ;
assign probe_out53[0] = \<const0> ;
assign probe_out54[0] = \<const0> ;
assign probe_out55[0] = \<const0> ;
assign probe_out56[0] = \<const0> ;
assign probe_out57[0] = \<const0> ;
assign probe_out58[0] = \<const0> ;
assign probe_out59[0] = \<const0> ;
assign probe_out6[0] = \<const0> ;
assign probe_out60[0] = \<const0> ;
assign probe_out61[0] = \<const0> ;
assign probe_out62[0] = \<const0> ;
assign probe_out63[0] = \<const0> ;
assign probe_out64[0] = \<const0> ;
assign probe_out65[0] = \<const0> ;
assign probe_out66[0] = \<const0> ;
assign probe_out67[0] = \<const0> ;
assign probe_out68[0] = \<const0> ;
assign probe_out69[0] = \<const0> ;
assign probe_out7[0] = \<const0> ;
assign probe_out70[0] = \<const0> ;
assign probe_out71[0] = \<const0> ;
assign probe_out72[0] = \<const0> ;
assign probe_out73[0] = \<const0> ;
assign probe_out74[0] = \<const0> ;
assign probe_out75[0] = \<const0> ;
assign probe_out76[0] = \<const0> ;
assign probe_out77[0] = \<const0> ;
assign probe_out78[0] = \<const0> ;
assign probe_out79[0] = \<const0> ;
assign probe_out8[0] = \<const0> ;
assign probe_out80[0] = \<const0> ;
assign probe_out81[0] = \<const0> ;
assign probe_out82[0] = \<const0> ;
assign probe_out83[0] = \<const0> ;
assign probe_out84[0] = \<const0> ;
assign probe_out85[0] = \<const0> ;
assign probe_out86[0] = \<const0> ;
assign probe_out87[0] = \<const0> ;
assign probe_out88[0] = \<const0> ;
assign probe_out89[0] = \<const0> ;
assign probe_out9[0] = \<const0> ;
assign probe_out90[0] = \<const0> ;
assign probe_out91[0] = \<const0> ;
assign probe_out92[0] = \<const0> ;
assign probe_out93[0] = \<const0> ;
assign probe_out94[0] = \<const0> ;
assign probe_out95[0] = \<const0> ;
assign probe_out96[0] = \<const0> ;
assign probe_out97[0] = \<const0> ;
assign probe_out98[0] = \<const0> ;
assign probe_out99[0] = \<const0> ;
vio_0_vio_v3_0_13_decoder DECODER_INST
(.\Bus_Data_out_reg[11] (Bus_Data_out),
.E(DECODER_INST_n_4),
.Q({\bus_data_int_reg_n_0_[15] ,\bus_data_int_reg_n_0_[14] ,\bus_data_int_reg_n_0_[13] ,\bus_data_int_reg_n_0_[12] ,\bus_data_int_reg_n_0_[11] ,\bus_data_int_reg_n_0_[10] ,\bus_data_int_reg_n_0_[9] ,\bus_data_int_reg_n_0_[8] ,\bus_data_int_reg_n_0_[7] ,\bus_data_int_reg_n_0_[6] ,\bus_data_int_reg_n_0_[5] ,\bus_data_int_reg_n_0_[4] ,\bus_data_int_reg_n_0_[3] ,\bus_data_int_reg_n_0_[2] ,p_0_in,\bus_data_int_reg_n_0_[0] }),
.out(bus_clk),
.s_daddr_o(bus_addr),
.s_den_o(bus_den),
.s_do_i(bus_do),
.s_drdy_i(bus_drdy),
.s_dwe_o(bus_dwe),
.s_rst_o(bus_rst),
.\wr_en_reg[4]_0 (DECODER_INST_n_1),
.\wr_en_reg[4]_1 (DECODER_INST_n_2),
.\wr_en_reg[4]_2 (DECODER_INST_n_3));
GND GND
(.G(\<const0> ));
vio_0_vio_v3_0_13_probe_in_one PROBE_IN_INST
(.D({probe_in3,probe_in2,probe_in1,probe_in0}),
.E(DECODER_INST_n_4),
.Q(Bus_Data_out),
.clk(clk),
.out(bus_clk),
.s_daddr_o(bus_addr[2:0]),
.s_den_o(bus_den),
.s_dwe_o(bus_dwe),
.s_rst_o(bus_rst),
.\wr_en[4]_i_3 (DECODER_INST_n_1),
.\wr_en[4]_i_4 (DECODER_INST_n_3),
.\wr_en[4]_i_5 (DECODER_INST_n_2));
(* C_BUILD_REVISION = "0" *)
(* C_CORE_INFO1 = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
(* C_CORE_INFO2 = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
(* C_CORE_MAJOR_VER = "2" *)
(* C_CORE_MINOR_VER = "0" *)
(* C_CORE_TYPE = "2" *)
(* C_CSE_DRV_VER = "1" *)
(* C_MAJOR_VERSION = "2013" *)
(* C_MINOR_VERSION = "1" *)
(* C_NEXT_SLAVE = "0" *)
(* C_PIPE_IFACE = "0" *)
(* C_USE_TEST_REG = "1" *)
(* C_XDEVICEFAMILY = "kintex7" *)
(* C_XSDB_SLAVE_TYPE = "33" *)
(* DONT_TOUCH *)
vio_0_xsdbs_v1_0_2_xsdbs U_XSDB_SLAVE
(.s_daddr_o(bus_addr),
.s_dclk_o(bus_clk),
.s_den_o(bus_den),
.s_di_o(bus_di),
.s_do_i(bus_do),
.s_drdy_i(bus_drdy),
.s_dwe_o(bus_dwe),
.s_rst_o(bus_rst),
.sl_iport_i(sl_iport0),
.sl_oport_o(sl_oport0));
FDRE \bus_data_int_reg[0]
(.C(bus_clk),
.CE(1'b1),
.D(bus_di[0]),
.Q(\bus_data_int_reg_n_0_[0] ),
.R(1'b0));
FDRE \bus_data_int_reg[10]
(.C(bus_clk),
.CE(1'b1),
.D(bus_di[10]),
.Q(\bus_data_int_reg_n_0_[10] ),
.R(1'b0));
FDRE \bus_data_int_reg[11]
(.C(bus_clk),
.CE(1'b1),
.D(bus_di[11]),
.Q(\bus_data_int_reg_n_0_[11] ),
.R(1'b0));
FDRE \bus_data_int_reg[12]
(.C(bus_clk),
.CE(1'b1),
.D(bus_di[12]),
.Q(\bus_data_int_reg_n_0_[12] ),
.R(1'b0));
FDRE \bus_data_int_reg[13]
(.C(bus_clk),
.CE(1'b1),
.D(bus_di[13]),
.Q(\bus_data_int_reg_n_0_[13] ),
.R(1'b0));
FDRE \bus_data_int_reg[14]
(.C(bus_clk),
.CE(1'b1),
.D(bus_di[14]),
.Q(\bus_data_int_reg_n_0_[14] ),
.R(1'b0));
FDRE \bus_data_int_reg[15]
(.C(bus_clk),
.CE(1'b1),
.D(bus_di[15]),
.Q(\bus_data_int_reg_n_0_[15] ),
.R(1'b0));
FDRE \bus_data_int_reg[1]
(.C(bus_clk),
.CE(1'b1),
.D(bus_di[1]),
.Q(p_0_in),
.R(1'b0));
FDRE \bus_data_int_reg[2]
(.C(bus_clk),
.CE(1'b1),
.D(bus_di[2]),
.Q(\bus_data_int_reg_n_0_[2] ),
.R(1'b0));
FDRE \bus_data_int_reg[3]
(.C(bus_clk),
.CE(1'b1),
.D(bus_di[3]),
.Q(\bus_data_int_reg_n_0_[3] ),
.R(1'b0));
FDRE \bus_data_int_reg[4]
(.C(bus_clk),
.CE(1'b1),
.D(bus_di[4]),
.Q(\bus_data_int_reg_n_0_[4] ),
.R(1'b0));
FDRE \bus_data_int_reg[5]
(.C(bus_clk),
.CE(1'b1),
.D(bus_di[5]),
.Q(\bus_data_int_reg_n_0_[5] ),
.R(1'b0));
FDRE \bus_data_int_reg[6]
(.C(bus_clk),
.CE(1'b1),
.D(bus_di[6]),
.Q(\bus_data_int_reg_n_0_[6] ),
.R(1'b0));
FDRE \bus_data_int_reg[7]
(.C(bus_clk),
.CE(1'b1),
.D(bus_di[7]),
.Q(\bus_data_int_reg_n_0_[7] ),
.R(1'b0));
FDRE \bus_data_int_reg[8]
(.C(bus_clk),
.CE(1'b1),
.D(bus_di[8]),
.Q(\bus_data_int_reg_n_0_[8] ),
.R(1'b0));
FDRE \bus_data_int_reg[9]
(.C(bus_clk),
.CE(1'b1),
.D(bus_di[9]),
.Q(\bus_data_int_reg_n_0_[9] ),
.R(1'b0));
endmodule
(* C_BUILD_REVISION = "0" *) (* C_CORE_INFO1 = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) (* C_CORE_INFO2 = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
(* C_CORE_MAJOR_VER = "2" *) (* C_CORE_MINOR_VER = "0" *) (* C_CORE_TYPE = "2" *)
(* C_CSE_DRV_VER = "1" *) (* C_MAJOR_VERSION = "2013" *) (* C_MINOR_VERSION = "1" *)
(* C_NEXT_SLAVE = "0" *) (* C_PIPE_IFACE = "0" *) (* C_USE_TEST_REG = "1" *)
(* C_XDEVICEFAMILY = "kintex7" *) (* C_XSDB_SLAVE_TYPE = "33" *) (* ORIG_REF_NAME = "xsdbs_v1_0_2_xsdbs" *)
(* dont_touch = "true" *)
module vio_0_xsdbs_v1_0_2_xsdbs
(s_rst_o,
s_dclk_o,
s_den_o,
s_dwe_o,
s_daddr_o,
s_di_o,
sl_oport_o,
s_do_i,
sl_iport_i,
s_drdy_i);
output s_rst_o;
output s_dclk_o;
output s_den_o;
output s_dwe_o;
output [16:0]s_daddr_o;
output [15:0]s_di_o;
output [16:0]sl_oport_o;
input [15:0]s_do_i;
input [36:0]sl_iport_i;
input s_drdy_i;
wire [8:0]reg_do;
wire \reg_do[10]_i_1_n_0 ;
wire \reg_do[10]_i_2_n_0 ;
wire \reg_do[15]_i_1_n_0 ;
wire \reg_do[1]_i_2_n_0 ;
wire \reg_do[2]_i_1_n_0 ;
wire \reg_do[3]_i_1_n_0 ;
wire \reg_do[4]_i_1_n_0 ;
wire \reg_do[5]_i_2_n_0 ;
wire \reg_do[6]_i_1_n_0 ;
wire \reg_do[7]_i_1_n_0 ;
wire \reg_do[8]_i_2_n_0 ;
wire \reg_do[9]_i_1_n_0 ;
wire \reg_do_reg_n_0_[0] ;
wire \reg_do_reg_n_0_[10] ;
wire \reg_do_reg_n_0_[11] ;
wire \reg_do_reg_n_0_[12] ;
wire \reg_do_reg_n_0_[13] ;
wire \reg_do_reg_n_0_[14] ;
wire \reg_do_reg_n_0_[15] ;
wire \reg_do_reg_n_0_[1] ;
wire \reg_do_reg_n_0_[2] ;
wire \reg_do_reg_n_0_[3] ;
wire \reg_do_reg_n_0_[4] ;
wire \reg_do_reg_n_0_[5] ;
wire \reg_do_reg_n_0_[6] ;
wire \reg_do_reg_n_0_[7] ;
wire \reg_do_reg_n_0_[8] ;
wire \reg_do_reg_n_0_[9] ;
wire reg_drdy;
wire reg_drdy_i_1_n_0;
wire [15:0]reg_test;
wire reg_test0;
wire s_den_o;
wire s_den_o_INST_0_i_1_n_0;
wire [15:0]s_do_i;
wire s_drdy_i;
wire [36:0]sl_iport_i;
wire [16:0]sl_oport_o;
assign s_daddr_o[16:0] = sl_iport_i[20:4];
assign s_dclk_o = sl_iport_i[1];
assign s_di_o[15:0] = sl_iport_i[36:21];
assign s_dwe_o = sl_iport_i[3];
assign s_rst_o = sl_iport_i[0];
LUT6 #(
.INIT(64'hBAAAFFFFAAAAAAAA))
\reg_do[0]_i_1
(.I0(\reg_do[5]_i_2_n_0 ),
.I1(sl_iport_i[4]),
.I2(reg_test[0]),
.I3(sl_iport_i[6]),
.I4(sl_iport_i[5]),
.I5(sl_iport_i[8]),
.O(reg_do[0]));
LUT3 #(
.INIT(8'h40))
\reg_do[10]_i_1
(.I0(sl_iport_i[5]),
.I1(\reg_do[8]_i_2_n_0 ),
.I2(sl_iport_i[4]),
.O(\reg_do[10]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'h0800))
\reg_do[10]_i_2
(.I0(\reg_do[8]_i_2_n_0 ),
.I1(sl_iport_i[5]),
.I2(sl_iport_i[4]),
.I3(reg_test[10]),
.O(\reg_do[10]_i_2_n_0 ));
LUT3 #(
.INIT(8'hF7))
\reg_do[15]_i_1
(.I0(\reg_do[8]_i_2_n_0 ),
.I1(sl_iport_i[5]),
.I2(sl_iport_i[4]),
.O(\reg_do[15]_i_1_n_0 ));
LUT5 #(
.INIT(32'h20220000))
\reg_do[1]_i_1
(.I0(sl_iport_i[5]),
.I1(sl_iport_i[4]),
.I2(reg_test[1]),
.I3(sl_iport_i[6]),
.I4(\reg_do[1]_i_2_n_0 ),
.O(reg_do[1]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h00800000))
\reg_do[1]_i_2
(.I0(sl_iport_i[8]),
.I1(sl_iport_i[10]),
.I2(sl_iport_i[11]),
.I3(sl_iport_i[7]),
.I4(sl_iport_i[9]),
.O(\reg_do[1]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'h0800))
\reg_do[2]_i_1
(.I0(\reg_do[8]_i_2_n_0 ),
.I1(sl_iport_i[5]),
.I2(sl_iport_i[4]),
.I3(reg_test[2]),
.O(\reg_do[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h0800))
\reg_do[3]_i_1
(.I0(\reg_do[8]_i_2_n_0 ),
.I1(sl_iport_i[5]),
.I2(sl_iport_i[4]),
.I3(reg_test[3]),
.O(\reg_do[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'h0800))
\reg_do[4]_i_1
(.I0(\reg_do[8]_i_2_n_0 ),
.I1(sl_iport_i[5]),
.I2(sl_iport_i[4]),
.I3(reg_test[4]),
.O(\reg_do[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF00800044))
\reg_do[5]_i_1
(.I0(sl_iport_i[6]),
.I1(sl_iport_i[8]),
.I2(reg_test[5]),
.I3(sl_iport_i[4]),
.I4(sl_iport_i[5]),
.I5(\reg_do[5]_i_2_n_0 ),
.O(reg_do[5]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'hBFFFFFFC))
\reg_do[5]_i_2
(.I0(sl_iport_i[7]),
.I1(sl_iport_i[8]),
.I2(sl_iport_i[11]),
.I3(sl_iport_i[10]),
.I4(sl_iport_i[9]),
.O(\reg_do[5]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h0800))
\reg_do[6]_i_1
(.I0(\reg_do[8]_i_2_n_0 ),
.I1(sl_iport_i[5]),
.I2(sl_iport_i[4]),
.I3(reg_test[6]),
.O(\reg_do[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'h0800))
\reg_do[7]_i_1
(.I0(\reg_do[8]_i_2_n_0 ),
.I1(sl_iport_i[5]),
.I2(sl_iport_i[4]),
.I3(reg_test[7]),
.O(\reg_do[7]_i_1_n_0 ));
LUT4 #(
.INIT(16'h2F00))
\reg_do[8]_i_1
(.I0(reg_test[8]),
.I1(sl_iport_i[4]),
.I2(sl_iport_i[5]),
.I3(\reg_do[8]_i_2_n_0 ),
.O(reg_do[8]));
LUT6 #(
.INIT(64'h2000000000000000))
\reg_do[8]_i_2
(.I0(sl_iport_i[9]),
.I1(sl_iport_i[7]),
.I2(sl_iport_i[11]),
.I3(sl_iport_i[10]),
.I4(sl_iport_i[8]),
.I5(sl_iport_i[6]),
.O(\reg_do[8]_i_2_n_0 ));
LUT5 #(
.INIT(32'h0C008000))
\reg_do[9]_i_1
(.I0(reg_test[9]),
.I1(\reg_do[1]_i_2_n_0 ),
.I2(sl_iport_i[6]),
.I3(sl_iport_i[5]),
.I4(sl_iport_i[4]),
.O(\reg_do[9]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\reg_do_reg[0]
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(reg_do[0]),
.Q(\reg_do_reg_n_0_[0] ),
.R(1'b0));
FDSE #(
.INIT(1'b0))
\reg_do_reg[10]
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(\reg_do[10]_i_2_n_0 ),
.Q(\reg_do_reg_n_0_[10] ),
.S(\reg_do[10]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\reg_do_reg[11]
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(reg_test[11]),
.Q(\reg_do_reg_n_0_[11] ),
.R(\reg_do[15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\reg_do_reg[12]
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(reg_test[12]),
.Q(\reg_do_reg_n_0_[12] ),
.R(\reg_do[15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\reg_do_reg[13]
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(reg_test[13]),
.Q(\reg_do_reg_n_0_[13] ),
.R(\reg_do[15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\reg_do_reg[14]
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(reg_test[14]),
.Q(\reg_do_reg_n_0_[14] ),
.R(\reg_do[15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\reg_do_reg[15]
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(reg_test[15]),
.Q(\reg_do_reg_n_0_[15] ),
.R(\reg_do[15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\reg_do_reg[1]
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(reg_do[1]),
.Q(\reg_do_reg_n_0_[1] ),
.R(1'b0));
FDSE #(
.INIT(1'b0))
\reg_do_reg[2]
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(\reg_do[2]_i_1_n_0 ),
.Q(\reg_do_reg_n_0_[2] ),
.S(\reg_do[10]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\reg_do_reg[3]
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(\reg_do[3]_i_1_n_0 ),
.Q(\reg_do_reg_n_0_[3] ),
.S(\reg_do[10]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\reg_do_reg[4]
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(\reg_do[4]_i_1_n_0 ),
.Q(\reg_do_reg_n_0_[4] ),
.S(\reg_do[10]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\reg_do_reg[5]
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(reg_do[5]),
.Q(\reg_do_reg_n_0_[5] ),
.R(1'b0));
FDSE #(
.INIT(1'b0))
\reg_do_reg[6]
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(\reg_do[6]_i_1_n_0 ),
.Q(\reg_do_reg_n_0_[6] ),
.S(\reg_do[10]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\reg_do_reg[7]
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(\reg_do[7]_i_1_n_0 ),
.Q(\reg_do_reg_n_0_[7] ),
.S(\reg_do[10]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\reg_do_reg[8]
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(reg_do[8]),
.Q(\reg_do_reg_n_0_[8] ),
.R(1'b0));
FDSE #(
.INIT(1'b0))
\reg_do_reg[9]
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(\reg_do[9]_i_1_n_0 ),
.Q(\reg_do_reg_n_0_[9] ),
.S(\reg_do[10]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0000000080000000))
reg_drdy_i_1
(.I0(sl_iport_i[2]),
.I1(s_den_o_INST_0_i_1_n_0),
.I2(sl_iport_i[12]),
.I3(sl_iport_i[13]),
.I4(sl_iport_i[14]),
.I5(sl_iport_i[0]),
.O(reg_drdy_i_1_n_0));
FDRE #(
.INIT(1'b0))
reg_drdy_reg
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(reg_drdy_i_1_n_0),
.Q(reg_drdy),
.R(1'b0));
LUT6 #(
.INIT(64'h8000000000000000))
\reg_test[15]_i_1
(.I0(sl_iport_i[3]),
.I1(sl_iport_i[2]),
.I2(sl_iport_i[14]),
.I3(sl_iport_i[13]),
.I4(sl_iport_i[12]),
.I5(s_den_o_INST_0_i_1_n_0),
.O(reg_test0));
FDRE #(
.INIT(1'b0))
\reg_test_reg[0]
(.C(sl_iport_i[1]),
.CE(reg_test0),
.D(sl_iport_i[21]),
.Q(reg_test[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\reg_test_reg[10]
(.C(sl_iport_i[1]),
.CE(reg_test0),
.D(sl_iport_i[31]),
.Q(reg_test[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\reg_test_reg[11]
(.C(sl_iport_i[1]),
.CE(reg_test0),
.D(sl_iport_i[32]),
.Q(reg_test[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\reg_test_reg[12]
(.C(sl_iport_i[1]),
.CE(reg_test0),
.D(sl_iport_i[33]),
.Q(reg_test[12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\reg_test_reg[13]
(.C(sl_iport_i[1]),
.CE(reg_test0),
.D(sl_iport_i[34]),
.Q(reg_test[13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\reg_test_reg[14]
(.C(sl_iport_i[1]),
.CE(reg_test0),
.D(sl_iport_i[35]),
.Q(reg_test[14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\reg_test_reg[15]
(.C(sl_iport_i[1]),
.CE(reg_test0),
.D(sl_iport_i[36]),
.Q(reg_test[15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\reg_test_reg[1]
(.C(sl_iport_i[1]),
.CE(reg_test0),
.D(sl_iport_i[22]),
.Q(reg_test[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\reg_test_reg[2]
(.C(sl_iport_i[1]),
.CE(reg_test0),
.D(sl_iport_i[23]),
.Q(reg_test[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\reg_test_reg[3]
(.C(sl_iport_i[1]),
.CE(reg_test0),
.D(sl_iport_i[24]),
.Q(reg_test[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\reg_test_reg[4]
(.C(sl_iport_i[1]),
.CE(reg_test0),
.D(sl_iport_i[25]),
.Q(reg_test[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\reg_test_reg[5]
(.C(sl_iport_i[1]),
.CE(reg_test0),
.D(sl_iport_i[26]),
.Q(reg_test[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\reg_test_reg[6]
(.C(sl_iport_i[1]),
.CE(reg_test0),
.D(sl_iport_i[27]),
.Q(reg_test[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\reg_test_reg[7]
(.C(sl_iport_i[1]),
.CE(reg_test0),
.D(sl_iport_i[28]),
.Q(reg_test[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\reg_test_reg[8]
(.C(sl_iport_i[1]),
.CE(reg_test0),
.D(sl_iport_i[29]),
.Q(reg_test[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\reg_test_reg[9]
(.C(sl_iport_i[1]),
.CE(reg_test0),
.D(sl_iport_i[30]),
.Q(reg_test[9]),
.R(1'b0));
LUT5 #(
.INIT(32'h2AAAAAAA))
s_den_o_INST_0
(.I0(sl_iport_i[2]),
.I1(sl_iport_i[14]),
.I2(sl_iport_i[13]),
.I3(sl_iport_i[12]),
.I4(s_den_o_INST_0_i_1_n_0),
.O(s_den_o));
LUT6 #(
.INIT(64'h8000000000000000))
s_den_o_INST_0_i_1
(.I0(sl_iport_i[15]),
.I1(sl_iport_i[16]),
.I2(sl_iport_i[17]),
.I3(sl_iport_i[18]),
.I4(sl_iport_i[20]),
.I5(sl_iport_i[19]),
.O(s_den_o_INST_0_i_1_n_0));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT2 #(
.INIT(4'hE))
\sl_oport_o[0]_INST_0
(.I0(s_drdy_i),
.I1(reg_drdy),
.O(sl_oport_o[0]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'hAC))
\sl_oport_o[10]_INST_0
(.I0(\reg_do_reg_n_0_[9] ),
.I1(s_do_i[9]),
.I2(reg_drdy),
.O(sl_oport_o[10]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'hAC))
\sl_oport_o[11]_INST_0
(.I0(\reg_do_reg_n_0_[10] ),
.I1(s_do_i[10]),
.I2(reg_drdy),
.O(sl_oport_o[11]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'hAC))
\sl_oport_o[12]_INST_0
(.I0(\reg_do_reg_n_0_[11] ),
.I1(s_do_i[11]),
.I2(reg_drdy),
.O(sl_oport_o[12]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'hAC))
\sl_oport_o[13]_INST_0
(.I0(\reg_do_reg_n_0_[12] ),
.I1(s_do_i[12]),
.I2(reg_drdy),
.O(sl_oport_o[13]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'hAC))
\sl_oport_o[14]_INST_0
(.I0(\reg_do_reg_n_0_[13] ),
.I1(s_do_i[13]),
.I2(reg_drdy),
.O(sl_oport_o[14]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'hAC))
\sl_oport_o[15]_INST_0
(.I0(\reg_do_reg_n_0_[14] ),
.I1(s_do_i[14]),
.I2(reg_drdy),
.O(sl_oport_o[15]));
LUT3 #(
.INIT(8'hAC))
\sl_oport_o[16]_INST_0
(.I0(\reg_do_reg_n_0_[15] ),
.I1(s_do_i[15]),
.I2(reg_drdy),
.O(sl_oport_o[16]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT3 #(
.INIT(8'hAC))
\sl_oport_o[1]_INST_0
(.I0(\reg_do_reg_n_0_[0] ),
.I1(s_do_i[0]),
.I2(reg_drdy),
.O(sl_oport_o[1]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT3 #(
.INIT(8'hAC))
\sl_oport_o[2]_INST_0
(.I0(\reg_do_reg_n_0_[1] ),
.I1(s_do_i[1]),
.I2(reg_drdy),
.O(sl_oport_o[2]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT3 #(
.INIT(8'hAC))
\sl_oport_o[3]_INST_0
(.I0(\reg_do_reg_n_0_[2] ),
.I1(s_do_i[2]),
.I2(reg_drdy),
.O(sl_oport_o[3]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'hAC))
\sl_oport_o[4]_INST_0
(.I0(\reg_do_reg_n_0_[3] ),
.I1(s_do_i[3]),
.I2(reg_drdy),
.O(sl_oport_o[4]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'hAC))
\sl_oport_o[5]_INST_0
(.I0(\reg_do_reg_n_0_[4] ),
.I1(s_do_i[4]),
.I2(reg_drdy),
.O(sl_oport_o[5]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'hAC))
\sl_oport_o[6]_INST_0
(.I0(\reg_do_reg_n_0_[5] ),
.I1(s_do_i[5]),
.I2(reg_drdy),
.O(sl_oport_o[6]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'hAC))
\sl_oport_o[7]_INST_0
(.I0(\reg_do_reg_n_0_[6] ),
.I1(s_do_i[6]),
.I2(reg_drdy),
.O(sl_oport_o[7]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'hAC))
\sl_oport_o[8]_INST_0
(.I0(\reg_do_reg_n_0_[7] ),
.I1(s_do_i[7]),
.I2(reg_drdy),
.O(sl_oport_o[8]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'hAC))
\sl_oport_o[9]_INST_0
(.I0(\reg_do_reg_n_0_[8] ),
.I1(s_do_i[8]),
.I2(reg_drdy),
.O(sl_oport_o[9]));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized COMPARATOR with generic_baseblocks_v2_1_carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_comparator #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] B,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar bit_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 3;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = B;
end
// Instantiate one generic_baseblocks_v2_1_carry and per level.
for (bit_cnt = 0; bit_cnt < C_NUM_LUT ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[bit_cnt] = ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] );
// Instantiate each LUT level.
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[bit_cnt+1]),
.CIN (carry_local[bit_cnt]),
.S (sel[bit_cnt])
);
end // end for bit_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule
|
module b14_inj (clock,reset,addr,datai,datao,rd,wr,p_b_Z_p_O_FDC,p_desc52_p_O_FDC,p_desc53_p_O_FDC,p_desc54_p_O_FDC,p_desc55_p_O_FDC,p_desc56_p_O_FDC,p_desc57_p_O_FDC,p_desc58_p_O_FDC,p_desc59_p_O_FDC,p_desc60_p_O_FDC,p_desc61_p_O_FDC,p_desc62_p_O_FDC,p_desc63_p_O_FDC,p_desc64_p_O_FDC,p_desc65_p_O_FDC,p_desc66_p_O_FDC,p_desc67_p_O_FDC,p_desc68_p_O_FDC,p_desc69_p_O_FDC,p_desc70_p_O_FDC,p_desc71_p_O_FDC,p_desc72_p_O_FDC,p_desc73_p_O_FDC,p_desc74_p_O_FDC,p_desc75_p_O_FDC,p_desc76_p_O_FDC,p_desc77_p_O_FDC,p_desc78_p_O_FDC,p_desc79_p_O_FDC,p_desc80_p_O_FDC,p_desc81_p_O_FDC,p_desc82_p_O_FDC,p_desc83_p_O_FDC,p_rd_Z_p_O_FDC,p_desc261_p_O_FDC,p_wr_Z_p_O_FDC,p_desc262_p_O_FDC,p_desc50_p_O_FDCE,p_desc51_p_O_FDCE,p_desc84_p_O_FDCE,p_desc85_p_O_FDCE,p_desc86_p_O_FDCE,p_desc87_p_O_FDCE,p_desc88_p_O_FDCE,p_desc89_p_O_FDCE,p_desc90_p_O_FDCE,p_desc91_p_O_FDCE,p_desc92_p_O_FDCE,p_desc93_p_O_FDCE,p_desc94_p_O_FDCE,p_desc95_p_O_FDCE,p_desc96_p_O_FDCE,p_desc97_p_O_FDCE,p_desc98_p_O_FDCE,p_desc99_p_O_FDCE,p_desc100_p_O_FDCE,p_desc101_p_O_FDCE,p_desc102_p_O_FDCE,p_desc103_p_O_FDCE,p_desc104_p_O_FDCE,p_desc105_p_O_FDCE,p_desc106_p_O_FDCE,p_desc107_p_O_FDCE,p_desc108_p_O_FDCE,p_desc109_p_O_FDCE,p_desc110_p_O_FDCE,p_desc111_p_O_FDCE,p_desc112_p_O_FDCE,p_desc113_p_O_FDCE,p_desc114_p_O_FDCE,p_desc115_p_O_FDCE,p_desc116_p_O_FDCE,p_desc117_p_O_FDCE,p_desc118_p_O_FDCE,p_desc119_p_O_FDCE,p_desc120_p_O_FDCE,p_desc121_p_O_FDCE,p_desc122_p_O_FDCE,p_desc123_p_O_FDCE,p_desc124_p_O_FDCE,p_desc125_p_O_FDCE,p_desc126_p_O_FDCE,p_desc127_p_O_FDCE,p_desc128_p_O_FDCE,p_desc129_p_O_FDCE,p_desc130_p_O_FDCE,p_desc131_p_O_FDCE,p_desc132_p_O_FDCE,p_desc133_p_O_FDCE,p_desc134_p_O_FDCE,p_desc135_p_O_FDCE,p_desc136_p_O_FDCE,p_desc137_p_O_FDCE,p_desc138_p_O_FDCE,p_desc139_p_O_FDCE,p_desc140_p_O_FDCE,p_desc141_p_O_FDCE,p_desc142_p_O_FDCE,p_desc143_p_O_FDCE,p_desc144_p_O_FDCE,p_desc145_p_O_FDCE,p_desc146_p_O_FDCE,p_desc147_p_O_FDCE,p_desc148_p_O_FDCE,p_desc149_p_O_FDCE,p_desc150_p_O_FDCE,p_desc151_p_O_FDCE,p_desc152_p_O_FDCE,p_desc153_p_O_FDCE,p_desc154_p_O_FDCE,p_desc155_p_O_FDCE,p_desc156_p_O_FDCE,p_desc157_p_O_FDCE,p_desc158_p_O_FDCE,p_desc159_p_O_FDCE,p_desc160_p_O_FDCE,p_desc161_p_O_FDCE,p_desc162_p_O_FDCE,p_desc163_p_O_FDCE,p_desc164_p_O_FDCE,p_desc165_p_O_FDCE,p_desc166_p_O_FDCE,p_desc167_p_O_FDCE,p_desc168_p_O_FDCE,p_desc169_p_O_FDCE,p_desc170_p_O_FDCE,p_desc171_p_O_FDCE,p_desc172_p_O_FDCE,p_desc173_p_O_FDCE,p_desc174_p_O_FDCE,p_desc175_p_O_FDCE,p_desc176_p_O_FDCE,p_desc177_p_O_FDCE,p_desc178_p_O_FDCE,p_desc179_p_O_FDCE,p_desc180_p_O_FDCE,p_desc181_p_O_FDCE,p_desc182_p_O_FDCE,p_desc183_p_O_FDCE,p_desc184_p_O_FDCE,p_desc185_p_O_FDCE,p_desc186_p_O_FDCE,p_desc187_p_O_FDCE,p_desc188_p_O_FDCE,p_desc189_p_O_FDCE,p_desc190_p_O_FDCE,p_desc191_p_O_FDCE,p_desc192_p_O_FDCE,p_desc193_p_O_FDCE,p_desc194_p_O_FDCE,p_desc195_p_O_FDCE,p_desc196_p_O_FDCE,p_desc197_p_O_FDCE,p_desc198_p_O_FDCE,p_desc199_p_O_FDCE,p_desc200_p_O_FDCE,p_desc201_p_O_FDCE,p_desc202_p_O_FDCE,p_desc203_p_O_FDCE,p_desc204_p_O_FDCE,p_desc205_p_O_FDCE,p_desc206_p_O_FDCE,p_desc207_p_O_FDCE,p_desc208_p_O_FDCE,p_desc209_p_O_FDCE,p_desc210_p_O_FDCE,p_desc211_p_O_FDCE,p_desc212_p_O_FDCE,p_desc213_p_O_FDCE,p_desc214_p_O_FDCE,p_desc215_p_O_FDCE,p_desc216_p_O_FDCE,p_desc217_p_O_FDCE,p_desc218_p_O_FDCE,p_desc219_p_O_FDCE,p_desc220_p_O_FDCE,p_desc221_p_O_FDCE,p_desc222_p_O_FDCE,p_desc223_p_O_FDCE,p_desc224_p_O_FDCE,p_desc225_p_O_FDCE,p_desc226_p_O_FDCE,p_desc227_p_O_FDCE,p_desc228_p_O_FDCE,p_desc229_p_O_FDCE,p_desc230_p_O_FDCE,p_desc231_p_O_FDCE,p_desc232_p_O_FDCE,p_desc233_p_O_FDCE,p_desc234_p_O_FDCE,p_desc235_p_O_FDCE,p_desc236_p_O_FDCE,p_desc237_p_O_FDCE,p_desc238_p_O_FDCE,p_desc239_p_O_FDCE,p_desc240_p_O_FDCE,p_desc241_p_O_FDCE,p_desc242_p_O_FDCE,p_desc243_p_O_FDCE,p_desc244_p_O_FDCE,p_desc245_p_O_FDCE,p_desc246_p_O_FDCE,p_desc247_p_O_FDCE,p_desc248_p_O_FDCE,p_desc249_p_O_FDCE,p_desc250_p_O_FDCE,p_desc251_p_O_FDCE,p_desc252_p_O_FDCE,p_desc253_p_O_FDCE,p_desc254_p_O_FDCE,p_desc255_p_O_FDCE,p_desc256_p_O_FDCE,p_desc257_p_O_FDCE,p_desc258_p_O_FDCE,p_desc259_p_O_FDCE,p_desc260_p_O_FDCE);
input clock ;
input reset ;
output [19:0] addr ;
input [31:0] datai ;
output [31:0] datao ;
output rd ;
output wr ;
wire clock ;
wire reset ;
wire rd ;
wire wr ;
wire state ;
wire [31:0] ir ;
wire [28:0] reg3 ;
wire [31:0] ir_3 ;
wire [31:0] reg2 ;
wire [31:0] m_2 ;
wire [31:0] reg1 ;
wire [31:0] r_4 ;
wire [31:0] reg0 ;
wire [30:0] un11_r_cry ;
wire [1:0] d ;
wire [30:30] r_6 ;
wire [30:0] un26_r_cry ;
wire [31:0] reg2_16 ;
wire [19:0] un1_inf_abs0_10 ;
wire [19:0] un1_inf_abs0_11 ;
wire [18:0] reg0_28 ;
wire [18:0] reg1_16 ;
wire [28:0] reg3_17 ;
wire [28:0] b18_cry ;
wire [30:30] r_4_3_lut6_2_O5 ;
wire [9:0] un14_r_0_data_tmp ;
wire [16:1] t_6 ;
wire d_cnst ;
wire dce ;
wire [31:0] inf_abs0_2 ;
wire [31:1] reg3_1_1 ;
wire [31:0] t_1 ;
wire [18:17] reg0_28_7_a1 ;
wire [24:24] reg0_28_7_d ;
wire [24:21] reg3_17_a0 ;
wire [29:29] reg2_16_11_a1 ;
wire [29:17] reg2_16_11_a2 ;
wire [29:17] reg2_16_11_a3 ;
wire [1:0] r_4_2_a0 ;
wire [13:13] reg3_17_4_a2 ;
wire [10:10] r_4_1_RNIDBOH1 ;
wire [25:21] reg2_16_11_a4 ;
wire [9:9] r_4_1_RNIS3K91 ;
wire [7:7] r_4_1_RNIFO731 ;
wire [8:8] r_4_1_RNIIQ731 ;
wire [5:5] r_4_1_RNI9K731 ;
wire [6:6] r_4_1_RNICM731 ;
wire [3:3] r_4_2_a1_lut6_2_RNI5V8R3 ;
wire [3:3] r_4_2_a1_lut6_2_RNI2T8R3 ;
wire [24:21] \d_cnst_sn.reg3_17_0_tz ;
wire [4:0] \d_cnst_sn.r_4_0_0 ;
wire [20:20] reg2_16_2_d ;
wire [3:3] r_4_2_a1_lut6_2_O6 ;
wire [3:3] r_4_2_a1_lut6_2_O5 ;
wire [28:28] \d_cnst_sn.reg2_16_0_1_tz ;
wire [28:28] \d_cnst_sn.reg2_16_11_1_tz ;
wire [7:7] \d_cnst_sn.reg0_28_a0_1 ;
wire [5:5] \d_cnst_sn.reg1_16_a2_0 ;
wire [4:4] \d_cnst_sn.reg0_28_a1_1 ;
wire [3:3] \d_cnst_sn.reg1_16_a0_1 ;
wire [9:9] \d_cnst_sn.reg0_28_7_a0_0 ;
wire [24:24] \d_cnst_sn.reg3_17_a1_2 ;
wire state_i ;
wire [31:31] r_4_i ;
wire [31:0] m_2_i ;
wire [28:20] \d_cnst_sn.reg3_17_4_a2_0 ;
wire [21:21] \d_cnst_sn.reg3_17_a2_2_0 ;
wire [8:2] \d_cnst_sn.reg0_1 ;
wire [8:3] \d_cnst_sn.reg1_1 ;
wire [28:12] \d_cnst_sn.reg3_17_6_0 ;
wire [19:12] \d_cnst_sn.reg3_17_6_1 ;
wire [20:19] \d_cnst_sn.reg0_28_0 ;
wire [25:20] \d_cnst_sn.reg2_16_0 ;
wire [29:20] \d_cnst_sn.reg2_16_1 ;
wire [17:17] \d_cnst_sn.reg0_0 ;
wire [18:18] \d_cnst_sn.reg1_0 ;
wire [28:26] \d_cnst_sn.reg2_16_0_1_0 ;
wire [31:31] r_4_3_ci ;
wire [31:31] ir_fast ;
wire [31:31] ir_3_fast ;
wire [31:31] inf_abs0_2_0 ;
wire [31:31] inf_abs0_2_1 ;
wire [1:1] \d_cnst_sn.reg2_16_11muxnet_0 ;
wire [1:1] \d_cnst_sn.reg2_16_11muxnet_1 ;
wire b ;
wire VCC ;
wire GND ;
wire addr_4_sqmuxa_1 ;
wire un14_r_0_I_83 ;
wire b18 ;
wire un11_reg0_s_1 ;
wire un11_reg0_s_2 ;
wire un11_reg0_s_3 ;
wire un11_reg0_s_4 ;
wire un11_reg0_s_5 ;
wire un11_reg0_s_6 ;
wire un11_reg0_s_7 ;
wire un11_reg0_s_8 ;
wire un11_reg0_s_9 ;
wire un11_reg0_s_10 ;
wire un11_reg0_s_11 ;
wire un11_reg0_s_12 ;
wire un11_reg0_s_13 ;
wire un11_reg0_s_14 ;
wire un11_reg0_s_15 ;
wire un11_reg0_s_16 ;
wire un11_reg0_s_17 ;
wire un11_reg0_s_18 ;
wire un11_reg0_s_19 ;
wire un11_reg0_s_20 ;
wire un11_reg0_s_21 ;
wire un11_reg0_s_22 ;
wire un11_reg0_s_23 ;
wire un11_reg0_s_24 ;
wire un11_reg0_s_25 ;
wire un11_reg0_s_26 ;
wire un11_reg0_s_27 ;
wire un11_reg0_s_28 ;
wire un11_reg0_s_29 ;
wire rd_18 ;
wire un11_r_df0 ;
wire un11_r_lt0 ;
wire un11_r_df2 ;
wire un11_r_lt2 ;
wire un11_r_df4 ;
wire un11_r_lt4 ;
wire un11_r_df6 ;
wire un11_r_lt6 ;
wire un11_r_df8 ;
wire un11_r_lt8 ;
wire un11_r_df10 ;
wire un11_r_lt10 ;
wire un11_r_df12 ;
wire un11_r_lt12 ;
wire un11_r_df14 ;
wire un11_r_lt14 ;
wire un11_r_df16 ;
wire un11_r_lt16 ;
wire un11_r_df18 ;
wire un11_r_lt18 ;
wire un11_r_df20 ;
wire un11_r_lt20 ;
wire un11_r_df22 ;
wire un11_r_lt22 ;
wire un11_r_df24 ;
wire un11_r_lt24 ;
wire un11_r_df26 ;
wire un11_r_lt26 ;
wire un11_r_df28 ;
wire un11_r_lt28 ;
wire un11_r_df30 ;
wire un11_r_lt30 ;
wire b18_df0 ;
wire b18_lt0 ;
wire b18_df2 ;
wire b18_lt2 ;
wire b18_df4 ;
wire b18_lt4 ;
wire b18_df6 ;
wire b18_lt6 ;
wire b18_df8 ;
wire b18_lt8 ;
wire b18_df10 ;
wire b18_lt10 ;
wire b18_df12 ;
wire b18_lt12 ;
wire b18_df14 ;
wire b18_lt14 ;
wire b18_df16 ;
wire b18_lt16 ;
wire b18_df18 ;
wire b18_lt18 ;
wire b18_df20 ;
wire b18_lt20 ;
wire b18_df22 ;
wire b18_lt22 ;
wire b18_df24 ;
wire b18_lt24 ;
wire b18_df26 ;
wire b18_lt26 ;
wire b18_df28 ;
wire b18_lt28 ;
wire b18_df30 ;
wire b18_lt30 ;
wire un26_r_df0 ;
wire un26_r_lt0 ;
wire un26_r_df2 ;
wire un26_r_lt2 ;
wire un26_r_df4 ;
wire un26_r_lt4 ;
wire un26_r_df6 ;
wire un26_r_lt6 ;
wire un26_r_df8 ;
wire un26_r_lt8 ;
wire un26_r_df10 ;
wire un26_r_lt10 ;
wire un26_r_df12 ;
wire un26_r_lt12 ;
wire un26_r_df14 ;
wire un26_r_lt14 ;
wire un26_r_df16 ;
wire un26_r_lt16 ;
wire un26_r_df18 ;
wire un26_r_lt18 ;
wire un26_r_df20 ;
wire un26_r_lt20 ;
wire un26_r_df22 ;
wire un26_r_lt22 ;
wire un26_r_df24 ;
wire un26_r_lt24 ;
wire un26_r_df26 ;
wire un26_r_lt26 ;
wire un26_r_df28 ;
wire un26_r_lt28 ;
wire un26_r_df30 ;
wire un26_r_lt30 ;
wire r_4_3_30_680_i_m2 ;
wire r_4_3_29_706_i_m2 ;
wire r_4_3_28_732_i_m2 ;
wire r_4_3_27_758_i_m2 ;
wire r_4_3_25_810_i_m2 ;
wire r_4_3_24_836_i_m2 ;
wire r_4_3_23_1078_i_m2 ;
wire r_4_3_22_1104_i_m2 ;
wire r_4_3_20_1156_i_m2 ;
wire r_4_3_19_1182_i_m2 ;
wire r_4_3_18_1208_i_m2 ;
wire r_4_3_17_1234_i_m2 ;
wire r_4_3_16_1260_i_m2 ;
wire r_4_3_15_1286_i_m2 ;
wire r_4_3_14_1312_i_m2 ;
wire r_4_3_13_1338_i_m2 ;
wire r_4_3_12_1364_i_m2 ;
wire r_4_3_11_1390_i_m2 ;
wire r_4_3_10_1416_i_m2 ;
wire r_4_3_9_1442_i_m2 ;
wire r_4_3_8_1467 ;
wire r_4_3_6_1508_i_m2 ;
wire r_4_3_5_1534_i_m2 ;
wire r_4_3_4_1560_i_m2 ;
wire r_4_3_3_1586_i_m2 ;
wire r_4_3_2_1612_i_m2 ;
wire r_4_3_1_1638_i_m2 ;
wire r_4_3_0_1664_i_m2 ;
wire r_4_3_1690_i_m2 ;
wire reg1_16_9 ;
wire reg1_16_8_1837 ;
wire reg1_16_7_1870 ;
wire reg0_28_10_2261_a6_3_2_lut6_2_RNIOK9O5 ;
wire reg0_28_8_2327 ;
wire reg0_28_7_2360 ;
wire reg0_28_6_2393 ;
wire reg0_28_5_2426 ;
wire reg0_28_4_2459 ;
wire reg0_28_3_2492 ;
wire un14_r_0_N_2 ;
wire un14_r_0_N_7 ;
wire un14_r_0_N_14 ;
wire un14_r_0_N_21 ;
wire un14_r_0_N_28 ;
wire un14_r_0_N_35 ;
wire un14_r_0_N_42 ;
wire un14_r_0_N_49 ;
wire un14_r_0_N_56 ;
wire un14_r_0_N_63 ;
wire un14_r_0_N_70 ;
wire N_28 ;
wire N_3550 ;
wire N_3856 ;
wire N_2724 ;
wire N_3673 ;
wire N_939 ;
wire N_3_0 ;
wire N_971 ;
wire N_13 ;
wire un1_cf ;
wire N_1688 ;
wire reg3_1_sqmuxa ;
wire un1_df_16 ;
wire N_1750 ;
wire reg3_14_sqmuxa ;
wire N_1812 ;
wire N_1810 ;
wire N_1841 ;
wire N_1661 ;
wire N_1816 ;
wire N_1681 ;
wire N_1743 ;
wire N_938 ;
wire N_970 ;
wire N_1033 ;
wire N_513_i ;
wire N_3873_2 ;
wire N_512_i ;
wire un1_df_1 ;
wire un36_df ;
wire d_cnst_sm0 ;
wire N_3913 ;
wire N_1342 ;
wire N_1374 ;
wire N_514_i ;
wire N_1566 ;
wire N_1584 ;
wire N_1890 ;
wire un86_df ;
wire N_1664 ;
wire N_1819 ;
wire N_1682 ;
wire N_1837 ;
wire N_527_i ;
wire N_1042 ;
wire N_3916 ;
wire N_1270 ;
wire N_1132 ;
wire N_1892 ;
wire N_2641 ;
wire un87_df ;
wire N_7_i ;
wire N_1043 ;
wire b_2_sqmuxa ;
wire N_3912 ;
wire N_895 ;
wire N_526_i ;
wire un1_df_17_2 ;
wire N_1493 ;
wire N_1337 ;
wire N_1343 ;
wire N_1369 ;
wire N_1375 ;
wire N_1561 ;
wire N_1567 ;
wire N_934 ;
wire N_2722 ;
wire N_45 ;
wire N_54 ;
wire m7 ;
wire N_1901 ;
wire addr_4_sqmuxa_1_1 ;
wire un1_b57 ;
wire rd_4_sqmuxa ;
wire N_1740 ;
wire N_2240_i ;
wire N_3568 ;
wire N_2660_2 ;
wire N_915 ;
wire N_919 ;
wire N_918 ;
wire N_1076 ;
wire N_1044 ;
wire N_953 ;
wire N_921 ;
wire N_959 ;
wire N_927 ;
wire N_969 ;
wire N_937 ;
wire N_1084 ;
wire N_1052 ;
wire N_965 ;
wire N_933 ;
wire N_1741 ;
wire N_1679 ;
wire N_1742 ;
wire N_1680 ;
wire N_3614 ;
wire N_974 ;
wire N_942 ;
wire N_1838 ;
wire N_1683 ;
wire N_1039 ;
wire N_1085 ;
wire N_1053 ;
wire N_1083 ;
wire N_1051 ;
wire N_1040 ;
wire N_1038 ;
wire N_952 ;
wire N_920 ;
wire N_1077 ;
wire N_1045 ;
wire N_1081 ;
wire N_1049 ;
wire N_1827 ;
wire N_1672 ;
wire N_1082 ;
wire N_1050 ;
wire N_964 ;
wire N_932 ;
wire N_962 ;
wire N_930 ;
wire N_967 ;
wire N_935 ;
wire N_1079 ;
wire N_1047 ;
wire N_1068 ;
wire N_1036 ;
wire N_1078 ;
wire N_1046 ;
wire N_968 ;
wire N_936 ;
wire N_1069 ;
wire N_1037 ;
wire N_916 ;
wire N_1080 ;
wire N_1048 ;
wire N_1815 ;
wire N_1660 ;
wire N_1820 ;
wire N_1818 ;
wire N_1814 ;
wire N_1665 ;
wire N_1663 ;
wire N_1659 ;
wire N_1752 ;
wire N_1690 ;
wire N_955 ;
wire N_923 ;
wire N_954 ;
wire N_922 ;
wire N_1823 ;
wire N_1668 ;
wire N_956 ;
wire N_924 ;
wire N_1822 ;
wire N_1667 ;
wire N_957 ;
wire N_925 ;
wire N_1829 ;
wire N_1824 ;
wire N_1674 ;
wire N_1669 ;
wire N_961 ;
wire N_929 ;
wire N_1817 ;
wire N_1662 ;
wire N_963 ;
wire N_931 ;
wire N_1830 ;
wire N_1826 ;
wire N_1675 ;
wire N_1671 ;
wire N_960 ;
wire N_928 ;
wire N_1832 ;
wire N_1677 ;
wire N_1831 ;
wire N_1821 ;
wire N_1676 ;
wire N_1666 ;
wire N_1041 ;
wire N_1828 ;
wire N_1673 ;
wire N_972 ;
wire N_940 ;
wire N_1840 ;
wire N_1685 ;
wire N_975 ;
wire N_943 ;
wire N_1839 ;
wire N_1684 ;
wire N_973 ;
wire N_941 ;
wire N_958 ;
wire N_926 ;
wire un1_b59 ;
wire N_1813 ;
wire N_1732 ;
wire N_1670 ;
wire N_1658 ;
wire N_1751 ;
wire N_1689 ;
wire N_1583 ;
wire N_1582 ;
wire N_1581 ;
wire N_1580 ;
wire N_1575 ;
wire N_1574 ;
wire N_1573 ;
wire N_1572 ;
wire N_1571 ;
wire N_1570 ;
wire N_1569 ;
wire N_1568 ;
wire N_1565 ;
wire N_1564 ;
wire N_1563 ;
wire N_1562 ;
wire N_1560 ;
wire N_1035 ;
wire N_1363 ;
wire N_1362 ;
wire N_1361 ;
wire N_1354 ;
wire N_1353 ;
wire N_1352 ;
wire N_1351 ;
wire N_1383 ;
wire N_1350 ;
wire N_1382 ;
wire N_1349 ;
wire N_1381 ;
wire N_1348 ;
wire N_1380 ;
wire N_1347 ;
wire N_1379 ;
wire N_1346 ;
wire N_1378 ;
wire N_1345 ;
wire N_1377 ;
wire N_1344 ;
wire N_1376 ;
wire N_1341 ;
wire N_1373 ;
wire N_1340 ;
wire N_1372 ;
wire N_1339 ;
wire N_1371 ;
wire N_1338 ;
wire N_1370 ;
wire N_1336 ;
wire N_1368 ;
wire N_1335 ;
wire inf_abs0_2_axb_0 ;
wire inf_abs0_2_cry_0 ;
wire inf_abs0_2_axb_1 ;
wire inf_abs0_2_cry_1 ;
wire inf_abs0_2_axb_2 ;
wire inf_abs0_2_cry_2 ;
wire inf_abs0_2_axb_3 ;
wire inf_abs0_2_cry_3 ;
wire inf_abs0_2_axb_4 ;
wire inf_abs0_2_cry_4 ;
wire inf_abs0_2_axb_5 ;
wire inf_abs0_2_cry_5 ;
wire inf_abs0_2_axb_6 ;
wire inf_abs0_2_cry_6 ;
wire inf_abs0_2_axb_7 ;
wire inf_abs0_2_cry_7 ;
wire inf_abs0_2_axb_8 ;
wire inf_abs0_2_cry_8 ;
wire inf_abs0_2_axb_9 ;
wire inf_abs0_2_cry_9 ;
wire inf_abs0_2_axb_10 ;
wire inf_abs0_2_cry_10 ;
wire inf_abs0_2_axb_11 ;
wire inf_abs0_2_cry_11 ;
wire inf_abs0_2_axb_12 ;
wire inf_abs0_2_cry_12 ;
wire inf_abs0_2_axb_13 ;
wire inf_abs0_2_cry_13 ;
wire inf_abs0_2_axb_14 ;
wire inf_abs0_2_cry_14 ;
wire inf_abs0_2_axb_15 ;
wire inf_abs0_2_cry_15 ;
wire inf_abs0_2_axb_16 ;
wire inf_abs0_2_cry_16 ;
wire inf_abs0_2_axb_17 ;
wire inf_abs0_2_cry_17 ;
wire inf_abs0_2_axb_18 ;
wire inf_abs0_2_cry_18 ;
wire inf_abs0_2_axb_19 ;
wire inf_abs0_2_cry_19 ;
wire inf_abs0_2_axb_20 ;
wire inf_abs0_2_cry_20 ;
wire inf_abs0_2_axb_21 ;
wire inf_abs0_2_cry_21 ;
wire inf_abs0_2_axb_22 ;
wire inf_abs0_2_cry_22 ;
wire inf_abs0_2_axb_23 ;
wire inf_abs0_2_cry_23 ;
wire inf_abs0_2_axb_24 ;
wire inf_abs0_2_cry_24 ;
wire inf_abs0_2_axb_25 ;
wire inf_abs0_2_cry_25 ;
wire inf_abs0_2_axb_26 ;
wire inf_abs0_2_cry_26 ;
wire inf_abs0_2_axb_27 ;
wire inf_abs0_2_cry_27 ;
wire inf_abs0_2_axb_28 ;
wire inf_abs0_2_cry_28 ;
wire inf_abs0_2_axb_29 ;
wire inf_abs0_2_cry_29 ;
wire inf_abs0_2_axb_30 ;
wire reg3_1_1_axb_0 ;
wire reg3_1_1_cry_0 ;
wire reg3_1_1_axb_1 ;
wire reg3_1_1_cry_1 ;
wire reg3_1_1_axb_2 ;
wire reg3_1_1_cry_2 ;
wire reg3_1_1_axb_3 ;
wire reg3_1_1_cry_3 ;
wire reg3_1_1_axb_4 ;
wire reg3_1_1_cry_4 ;
wire reg3_1_1_axb_5 ;
wire reg3_1_1_cry_5 ;
wire reg3_1_1_axb_6 ;
wire reg3_1_1_cry_6 ;
wire reg3_1_1_axb_7 ;
wire reg3_1_1_cry_7 ;
wire reg3_1_1_axb_8 ;
wire reg3_1_1_cry_8 ;
wire reg3_1_1_axb_9 ;
wire reg3_1_1_cry_9 ;
wire reg3_1_1_axb_10 ;
wire reg3_1_1_cry_10 ;
wire reg3_1_1_axb_11 ;
wire reg3_1_1_cry_11 ;
wire reg3_1_1_axb_12 ;
wire reg3_1_1_cry_12 ;
wire reg3_1_1_axb_13 ;
wire reg3_1_1_cry_13 ;
wire reg3_1_1_axb_14 ;
wire reg3_1_1_cry_14 ;
wire reg3_1_1_axb_15 ;
wire reg3_1_1_cry_15 ;
wire reg3_1_1_axb_16 ;
wire reg3_1_1_cry_16 ;
wire reg3_1_1_axb_17 ;
wire reg3_1_1_cry_17 ;
wire reg3_1_1_axb_18 ;
wire reg3_1_1_cry_18 ;
wire reg3_1_1_axb_19 ;
wire reg3_1_1_cry_19 ;
wire reg3_1_1_cry_20 ;
wire reg3_1_1_cry_21 ;
wire reg3_1_1_cry_22 ;
wire reg3_1_1_cry_23 ;
wire reg3_1_1_cry_24 ;
wire reg3_1_1_cry_25 ;
wire reg3_1_1_cry_26 ;
wire reg3_1_1_cry_27 ;
wire reg3_1_1_cry_28 ;
wire reg3_1_1_axb_29 ;
wire reg3_1_1_cry_29 ;
wire reg3_1_1_axb_30 ;
wire reg3_1_1_cry_30 ;
wire reg3_1_1_axb_31 ;
wire un3_t_s_1 ;
wire un3_t_s_2 ;
wire un3_t_s_3 ;
wire un3_t_s_4 ;
wire un3_t_s_5 ;
wire un3_t_s_6 ;
wire un3_t_s_7 ;
wire un3_t_s_8 ;
wire un3_t_s_9 ;
wire un3_t_s_10 ;
wire un3_t_s_11 ;
wire un3_t_s_12 ;
wire un3_t_s_13 ;
wire un3_t_s_14 ;
wire un3_t_s_15 ;
wire un3_t_s_16 ;
wire un3_t_s_17 ;
wire un3_t_s_18 ;
wire un3_t_s_19 ;
wire un3_t_s_20 ;
wire un3_t_s_21 ;
wire un3_t_s_22 ;
wire un3_t_s_23 ;
wire un3_t_s_24 ;
wire un3_t_s_25 ;
wire un3_t_s_26 ;
wire un3_t_s_27 ;
wire un3_t_s_28 ;
wire un3_t_s_29 ;
wire un3_t_s_30 ;
wire un3_t_s_31 ;
wire un3_t_cry_0 ;
wire un3_t_cry_1 ;
wire un3_t_axb_2 ;
wire un3_t_cry_2 ;
wire un3_t_cry_3 ;
wire un3_t_cry_4 ;
wire un3_t_cry_5 ;
wire un3_t_cry_6 ;
wire un3_t_cry_7 ;
wire un3_t_cry_8 ;
wire un3_t_cry_9 ;
wire un3_t_cry_10 ;
wire un3_t_cry_11 ;
wire un3_t_cry_12 ;
wire un3_t_cry_13 ;
wire un3_t_cry_14 ;
wire un3_t_cry_15 ;
wire un3_t_cry_16 ;
wire un3_t_cry_17 ;
wire un3_t_cry_18 ;
wire un3_t_cry_19 ;
wire un3_t_cry_20 ;
wire un3_t_cry_21 ;
wire un3_t_cry_22 ;
wire un3_t_cry_23 ;
wire un3_t_cry_24 ;
wire un3_t_cry_25 ;
wire un3_t_cry_26 ;
wire un3_t_cry_27 ;
wire un3_t_cry_28 ;
wire un3_t_axb_29 ;
wire un3_t_cry_29 ;
wire un3_t_axb_30 ;
wire un3_t_cry_30 ;
wire un3_t_axb_31 ;
wire un11_reg0_axb_0 ;
wire un11_reg0_cry_0 ;
wire un11_reg0_axb_1 ;
wire un11_reg0_cry_1 ;
wire un11_reg0_axb_2 ;
wire un11_reg0_cry_2 ;
wire un11_reg0_axb_3 ;
wire un11_reg0_cry_3 ;
wire un11_reg0_axb_4 ;
wire un11_reg0_cry_4 ;
wire un11_reg0_axb_5 ;
wire un11_reg0_cry_5 ;
wire un11_reg0_axb_6 ;
wire un11_reg0_cry_6 ;
wire un11_reg0_axb_7 ;
wire un11_reg0_cry_7 ;
wire un11_reg0_axb_8 ;
wire un11_reg0_cry_8 ;
wire un11_reg0_axb_9 ;
wire un11_reg0_cry_9 ;
wire un11_reg0_axb_10 ;
wire un11_reg0_cry_10 ;
wire un11_reg0_axb_11 ;
wire un11_reg0_cry_11 ;
wire un11_reg0_axb_12 ;
wire un11_reg0_cry_12 ;
wire un11_reg0_axb_13 ;
wire un11_reg0_cry_13 ;
wire un11_reg0_axb_14 ;
wire un11_reg0_cry_14 ;
wire un11_reg0_axb_15 ;
wire un11_reg0_cry_15 ;
wire un11_reg0_axb_16 ;
wire un11_reg0_cry_16 ;
wire un11_reg0_axb_17 ;
wire un11_reg0_cry_17 ;
wire un11_reg0_axb_18 ;
wire un11_reg0_cry_18 ;
wire un11_reg0_axb_19 ;
wire un11_reg0_cry_19 ;
wire un11_reg0_axb_20 ;
wire un11_reg0_cry_20 ;
wire un11_reg0_axb_21 ;
wire un11_reg0_cry_21 ;
wire un11_reg0_axb_22 ;
wire un11_reg0_cry_22 ;
wire un11_reg0_axb_23 ;
wire un11_reg0_cry_23 ;
wire un11_reg0_axb_24 ;
wire un11_reg0_cry_24 ;
wire un11_reg0_axb_25 ;
wire un11_reg0_cry_25 ;
wire un11_reg0_axb_26 ;
wire un11_reg0_cry_26 ;
wire un11_reg0_axb_27 ;
wire un11_reg0_cry_27 ;
wire un11_reg0_axb_28 ;
wire un11_reg0_cry_28 ;
wire un11_reg0_axb_29 ;
wire un32_reg0_s_1 ;
wire un32_reg0_s_2 ;
wire un32_reg0_s_3 ;
wire un32_reg0_s_4 ;
wire un32_reg0_s_5 ;
wire un32_reg0_s_6 ;
wire un32_reg0_s_7 ;
wire un32_reg0_s_8 ;
wire un32_reg0_s_9 ;
wire un32_reg0_s_10 ;
wire un32_reg0_s_11 ;
wire un32_reg0_s_12 ;
wire un32_reg0_s_13 ;
wire un32_reg0_s_14 ;
wire un32_reg0_s_15 ;
wire un32_reg0_s_16 ;
wire un32_reg0_s_17 ;
wire un32_reg0_s_18 ;
wire un32_reg0_s_19 ;
wire un32_reg0_s_20 ;
wire un32_reg0_s_21 ;
wire un32_reg0_s_22 ;
wire un32_reg0_s_23 ;
wire un32_reg0_s_24 ;
wire un32_reg0_s_25 ;
wire un32_reg0_s_26 ;
wire un32_reg0_s_27 ;
wire un32_reg0_s_28 ;
wire un32_reg0_s_29 ;
wire un32_reg0_cry_0 ;
wire un32_reg0_axb_1 ;
wire un32_reg0_cry_1 ;
wire un32_reg0_axb_2 ;
wire un32_reg0_cry_2 ;
wire un32_reg0_axb_3 ;
wire un32_reg0_cry_3 ;
wire un32_reg0_axb_4 ;
wire un32_reg0_cry_4 ;
wire un32_reg0_axb_5 ;
wire un32_reg0_cry_5 ;
wire un32_reg0_axb_6 ;
wire un32_reg0_cry_6 ;
wire un32_reg0_axb_7 ;
wire un32_reg0_cry_7 ;
wire un32_reg0_axb_8 ;
wire un32_reg0_cry_8 ;
wire un32_reg0_axb_9 ;
wire un32_reg0_cry_9 ;
wire un32_reg0_axb_10 ;
wire un32_reg0_cry_10 ;
wire un32_reg0_axb_11 ;
wire un32_reg0_cry_11 ;
wire un32_reg0_axb_12 ;
wire un32_reg0_cry_12 ;
wire un32_reg0_axb_13 ;
wire un32_reg0_cry_13 ;
wire un32_reg0_axb_14 ;
wire un32_reg0_cry_14 ;
wire un32_reg0_axb_15 ;
wire un32_reg0_cry_15 ;
wire un32_reg0_axb_16 ;
wire un32_reg0_cry_16 ;
wire un32_reg0_axb_17 ;
wire un32_reg0_cry_17 ;
wire un32_reg0_axb_18 ;
wire un32_reg0_cry_18 ;
wire un32_reg0_axb_19 ;
wire un32_reg0_cry_19 ;
wire un32_reg0_axb_20 ;
wire un32_reg0_cry_20 ;
wire un32_reg0_axb_21 ;
wire un32_reg0_cry_21 ;
wire un32_reg0_axb_22 ;
wire un32_reg0_cry_22 ;
wire un32_reg0_axb_23 ;
wire un32_reg0_cry_23 ;
wire un32_reg0_axb_24 ;
wire un32_reg0_cry_24 ;
wire un32_reg0_axb_25 ;
wire un32_reg0_cry_25 ;
wire un32_reg0_axb_26 ;
wire un32_reg0_cry_26 ;
wire un32_reg0_axb_27 ;
wire un32_reg0_cry_27 ;
wire un32_reg0_axb_28 ;
wire un32_reg0_cry_28 ;
wire un32_reg0_axb_29 ;
wire un1_inf_abs0_cry_0 ;
wire un1_inf_abs0_axb_1 ;
wire un1_inf_abs0_cry_1 ;
wire un1_inf_abs0_axb_2 ;
wire un1_inf_abs0_cry_2 ;
wire un1_inf_abs0_axb_3 ;
wire un1_inf_abs0_cry_3 ;
wire un1_inf_abs0_axb_4 ;
wire un1_inf_abs0_cry_4 ;
wire un1_inf_abs0_axb_5 ;
wire un1_inf_abs0_cry_5 ;
wire un1_inf_abs0_axb_6 ;
wire un1_inf_abs0_cry_6 ;
wire un1_inf_abs0_axb_7 ;
wire un1_inf_abs0_cry_7 ;
wire un1_inf_abs0_axb_8 ;
wire un1_inf_abs0_cry_8 ;
wire un1_inf_abs0_axb_9 ;
wire un1_inf_abs0_cry_9 ;
wire un1_inf_abs0_axb_10 ;
wire un1_inf_abs0_cry_10 ;
wire un1_inf_abs0_axb_11 ;
wire un1_inf_abs0_cry_11 ;
wire un1_inf_abs0_axb_12 ;
wire un1_inf_abs0_cry_12 ;
wire un1_inf_abs0_axb_13 ;
wire un1_inf_abs0_cry_13 ;
wire un1_inf_abs0_axb_14 ;
wire un1_inf_abs0_cry_14 ;
wire un1_inf_abs0_axb_15 ;
wire un1_inf_abs0_cry_15 ;
wire un1_inf_abs0_axb_16 ;
wire un1_inf_abs0_cry_16 ;
wire un1_inf_abs0_axb_17 ;
wire un1_inf_abs0_cry_17 ;
wire un1_inf_abs0_axb_18 ;
wire un1_inf_abs0_cry_18 ;
wire un1_inf_abs0_axb_19 ;
wire un1_inf_abs0_0_cry_0 ;
wire un1_inf_abs0_0_axb_1 ;
wire un1_inf_abs0_0_cry_1 ;
wire un1_inf_abs0_0_axb_2 ;
wire un1_inf_abs0_0_cry_2 ;
wire un1_inf_abs0_0_axb_3 ;
wire un1_inf_abs0_0_cry_3 ;
wire un1_inf_abs0_0_axb_4 ;
wire un1_inf_abs0_0_cry_4 ;
wire un1_inf_abs0_0_axb_5 ;
wire un1_inf_abs0_0_cry_5 ;
wire un1_inf_abs0_0_axb_6 ;
wire un1_inf_abs0_0_cry_6 ;
wire un1_inf_abs0_0_axb_7 ;
wire un1_inf_abs0_0_cry_7 ;
wire un1_inf_abs0_0_axb_8 ;
wire un1_inf_abs0_0_cry_8 ;
wire un1_inf_abs0_0_axb_9 ;
wire un1_inf_abs0_0_cry_9 ;
wire un1_inf_abs0_0_axb_10 ;
wire un1_inf_abs0_0_cry_10 ;
wire un1_inf_abs0_0_axb_11 ;
wire un1_inf_abs0_0_cry_11 ;
wire un1_inf_abs0_0_axb_12 ;
wire un1_inf_abs0_0_cry_12 ;
wire un1_inf_abs0_0_axb_13 ;
wire un1_inf_abs0_0_cry_13 ;
wire un1_inf_abs0_0_axb_14 ;
wire un1_inf_abs0_0_cry_14 ;
wire un1_inf_abs0_0_axb_15 ;
wire un1_inf_abs0_0_cry_15 ;
wire un1_inf_abs0_0_axb_16 ;
wire un1_inf_abs0_0_cry_16 ;
wire un1_inf_abs0_0_axb_17 ;
wire un1_inf_abs0_0_cry_17 ;
wire un1_inf_abs0_0_axb_18 ;
wire un1_inf_abs0_0_cry_18 ;
wire un1_inf_abs0_0_axb_19 ;
wire un3_reg3_s_1 ;
wire un3_reg3_s_2 ;
wire un3_reg3_s_3 ;
wire un3_reg3_s_4 ;
wire un3_reg3_s_5 ;
wire un3_reg3_s_6 ;
wire un3_reg3_s_7 ;
wire un3_reg3_s_8 ;
wire un3_reg3_s_9 ;
wire un3_reg3_s_10 ;
wire un3_reg3_s_11 ;
wire un3_reg3_s_12 ;
wire un3_reg3_s_13 ;
wire un3_reg3_s_14 ;
wire un3_reg3_s_15 ;
wire un3_reg3_s_16 ;
wire un3_reg3_s_17 ;
wire un3_reg3_s_18 ;
wire un3_reg3_s_19 ;
wire un3_reg3_s_20 ;
wire un3_reg3_s_21 ;
wire un3_reg3_s_22 ;
wire un3_reg3_s_23 ;
wire un3_reg3_s_24 ;
wire un3_reg3_s_25 ;
wire un3_reg3_cry_25 ;
wire un3_reg3_axb_1 ;
wire un3_reg3_cry_1 ;
wire un3_reg3_axb_2 ;
wire un3_reg3_cry_2 ;
wire un3_reg3_axb_3 ;
wire un3_reg3_cry_3 ;
wire un3_reg3_axb_4 ;
wire un3_reg3_cry_4 ;
wire un3_reg3_axb_5 ;
wire un3_reg3_cry_5 ;
wire un3_reg3_axb_6 ;
wire un3_reg3_cry_6 ;
wire un3_reg3_axb_7 ;
wire un3_reg3_cry_7 ;
wire un3_reg3_axb_8 ;
wire un3_reg3_cry_8 ;
wire un3_reg3_axb_9 ;
wire un3_reg3_cry_9 ;
wire un3_reg3_axb_10 ;
wire un3_reg3_cry_10 ;
wire un3_reg3_axb_11 ;
wire un3_reg3_cry_11 ;
wire un3_reg3_axb_12 ;
wire un3_reg3_cry_12 ;
wire un3_reg3_axb_13 ;
wire un3_reg3_cry_13 ;
wire un3_reg3_axb_14 ;
wire un3_reg3_cry_14 ;
wire un3_reg3_axb_15 ;
wire un3_reg3_cry_15 ;
wire un3_reg3_axb_16 ;
wire un3_reg3_cry_16 ;
wire un3_reg3_axb_17 ;
wire un3_reg3_cry_17 ;
wire un3_reg3_axb_18 ;
wire un3_reg3_cry_18 ;
wire un3_reg3_axb_19 ;
wire un3_reg3_cry_19 ;
wire un3_reg3_axb_20 ;
wire un3_reg3_cry_20 ;
wire un3_reg3_axb_21 ;
wire un3_reg3_cry_21 ;
wire un3_reg3_axb_22 ;
wire un3_reg3_cry_22 ;
wire un3_reg3_axb_23 ;
wire un3_reg3_cry_23 ;
wire un3_reg3_axb_24 ;
wire un3_reg3_cry_24 ;
wire un3_reg3_axb_25 ;
wire t_1_cry_0 ;
wire t_1_cry_1 ;
wire t_1_cry_2 ;
wire t_1_cry_3 ;
wire t_1_cry_4 ;
wire t_1_cry_5 ;
wire t_1_cry_6 ;
wire t_1_cry_7 ;
wire t_1_cry_8 ;
wire t_1_cry_9 ;
wire t_1_cry_10 ;
wire t_1_cry_11 ;
wire t_1_cry_12 ;
wire t_1_cry_13 ;
wire t_1_cry_14 ;
wire t_1_cry_15 ;
wire t_1_cry_16 ;
wire t_1_cry_17 ;
wire t_1_cry_18 ;
wire t_1_cry_19 ;
wire t_1_cry_20 ;
wire t_1_cry_21 ;
wire t_1_cry_22 ;
wire t_1_cry_23 ;
wire t_1_cry_24 ;
wire t_1_cry_25 ;
wire t_1_cry_26 ;
wire t_1_cry_27 ;
wire t_1_cry_28 ;
wire t_1_cry_29 ;
wire t_1_cry_30 ;
wire \d_cnst_sn.reg1_16_8_1837_2_tz ;
wire reg0_28_sn_m6_lut6_2_O5 ;
wire \d_cnst_sn.reg3_17_sn_m7_0 ;
wire reg3_1_sqmuxa_RNIH1DM1 ;
wire reg3_1_sqmuxa_RNIE1DM1 ;
wire reg3_1_sqmuxa_RNIQMUH1 ;
wire reg3_1_sqmuxa_RNITMUH1 ;
wire reg3_1_sqmuxa_RNIKMUH1 ;
wire reg3_1_sqmuxa_RNINMUH1 ;
wire reg3_1_sqmuxa_RNIHMUH1 ;
wire reg3_1_sqmuxa_RNIEMUH1 ;
wire reg0_m9_i_a1 ;
wire \d_cnst_sn.reg2_N_3_mux ;
wire g0_2_0_i2_lut6_2_O6 ;
wire reg3_N_7_i_RNO ;
wire \d_cnst_sn.reg1_16_9_1804_3_tz ;
wire \d_cnst_sn.addr_20_iv_1052_i_a6_1_0 ;
wire \d_cnst_sn.reg0_m8_e_0 ;
wire \d_cnst_sn.reg3_5_sqmuxa_2_1 ;
wire \d_cnst_sn.reg0_28_9_2294_a6_3_0 ;
wire N_3910 ;
wire \d_cnst_sn.un1_state_3_1 ;
wire \d_cnst_sn.b60_0 ;
wire \d_cnst_sn.b64_0 ;
wire \d_cnst_sn.reg0_m9_i_a3_0 ;
wire reg3_17_sn_N_5 ;
wire \d_cnst_sn.reg0_28_2526_a5_1_0 ;
wire N_4571_i ;
wire N_4570_i ;
wire N_4569_i ;
wire N_4568_i ;
wire N_4567_i ;
wire N_4566_i ;
wire N_4565_i ;
wire N_4564_i ;
wire N_4563_i ;
wire N_4562_i ;
wire N_4561_i ;
wire N_4560_i ;
wire N_4559_i ;
wire N_4558_i ;
wire N_4557_i ;
wire N_4556_i ;
wire N_4555_i ;
wire N_4554_i ;
wire N_4553_i ;
wire N_4552_i ;
wire N_4551_i ;
wire N_4550_i ;
wire N_4549_i ;
wire N_4548_i ;
wire N_4547_i ;
wire N_4546_i ;
wire N_4545_i ;
wire N_4544_i ;
wire N_4543_i ;
wire N_4542_i ;
wire N_4541_i ;
wire \d_cnst_sn.reg3_N_7_i ;
wire N_2099_i ;
wire addr_0_sqmuxa_1_i ;
wire N_2119_i ;
wire N_2139_i ;
wire N_2159_i ;
wire N_2179_i ;
wire N_2199_i ;
wire N_2219_i ;
wire N_56_i ;
wire N_2267_i ;
wire N_47_i ;
wire N_2315_i ;
wire N_2335_i ;
wire N_36_i ;
wire N_2516_i ;
wire N_2536_i ;
wire N_2556_i ;
wire N_2576_i ;
wire N_2596_i ;
wire N_2616_i ;
wire N_2636_i ;
wire N_2656_i ;
wire un1_state_1_0_i ;
wire un1_state_3_i ;
wire un1_state_4_i ;
wire \d_cnst_sn.addr_20_iv_1052_i_a6_2_0 ;
wire \d_cnst_sn.m26_0_1 ;
wire \d_cnst_sn.m19_0_1 ;
wire \d_cnst_sn.addr_20_iv_7_654_i_1 ;
wire \d_cnst_sn.addr_20_iv_8_627_i_1 ;
wire \d_cnst_sn.addr_20_iv_16_389_i_1 ;
wire \d_cnst_sn.addr_20_iv_12_497_i_1 ;
wire \d_cnst_sn.addr_20_iv_10_562_i_1 ;
wire \d_cnst_sn.addr_20_iv_14_443_i_2 ;
wire \d_cnst_sn.addr_20_iv_15_416_i_1 ;
wire \d_cnst_sn.addr_20_iv_17_362_i_1 ;
wire \d_cnst_sn.addr_20_iv_13_470_i_1 ;
wire \d_cnst_sn.addr_20_iv_18_335_i_1 ;
wire \d_cnst_sn.addr_20_iv_2_971_i_0 ;
wire \d_cnst_sn.addr_20_iv_1_998_i_0 ;
wire \d_cnst_sn.addr_20_iv_1052_i_0 ;
wire \d_cnst_sn.addr_20_iv_0_1025_i_0 ;
wire \d_cnst_sn.addr_20_iv_3_944_i_0 ;
wire \d_cnst_sn.addr_20_iv_4_917_i_0 ;
wire \d_cnst_sn.addr_20_iv_5_890_i_0 ;
wire \d_cnst_sn.addr_20_iv_6_863_i_0 ;
wire \d_cnst_sn.reg0_28_12_2195_a6_1_2_0 ;
wire \d_cnst_sn.reg0_m9_i_a0_0 ;
wire \d_cnst_sn.reg0_28_5_2426_a6_1_1 ;
wire \d_cnst_sn.reg0_28_5_2426_3_1 ;
wire \d_cnst_sn.reg0_28_8_2327_a6_1_1 ;
wire \d_cnst_sn.reg0_28_6_2393_3_1 ;
wire \d_cnst_sn.reg0_28_6_2393_a6_1_1 ;
wire \d_cnst_sn.reg0_28_7_2360_3_1 ;
wire \d_cnst_sn.reg0_28_7_2360_a6_1_1 ;
wire \d_cnst_sn.reg0_28_14_2135_1_a0_2 ;
wire \d_cnst_sn.reg0_28_9_2294_a6_1_1 ;
wire \d_cnst_sn.reg0_28_9_2294_3_1 ;
wire \d_cnst_sn.reg1_16_7_1870_3_1 ;
wire \d_cnst_sn.reg0_28_10_2261_a6_1_1 ;
wire \d_cnst_sn.reg1_16_8_1837_3_1 ;
wire \d_cnst_sn.reg0_28_11_2228_a6_1_1 ;
wire \d_cnst_sn.reg0_28_3_2492_0 ;
wire \d_cnst_sn.reg0_28_3_2492_1 ;
wire \d_cnst_sn.reg0_28_4_2459_0 ;
wire \d_cnst_sn.reg0_28_8_2327_0 ;
wire \d_cnst_sn.reg0_28_5_2426_0 ;
wire \d_cnst_sn.reg0_28_6_2393_0 ;
wire \d_cnst_sn.reg0_28_7_2360_0 ;
wire \d_cnst_sn.reg0_28_14_0 ;
wire \d_cnst_sn.reg0_28_9_2294_0 ;
wire \d_cnst_sn.reg1_16_7_1870_0 ;
wire \d_cnst_sn.reg1_16_8_1837_0 ;
wire b_0 ;
wire un3_t_axb_28 ;
wire un3_t_axb_27 ;
wire un3_t_axb_26 ;
wire un3_t_axb_25 ;
wire un3_t_axb_24 ;
wire un3_t_axb_23 ;
wire un3_t_axb_22 ;
wire un3_t_axb_21 ;
wire un3_t_axb_20 ;
wire un3_t_axb_19 ;
wire un3_t_axb_18 ;
wire un3_t_axb_17 ;
wire un3_t_axb_16 ;
wire un3_t_axb_15 ;
wire un3_t_axb_14 ;
wire un3_t_axb_13 ;
wire un3_t_axb_12 ;
wire un3_t_axb_11 ;
wire un3_t_axb_10 ;
wire un3_t_axb_9 ;
wire un3_t_axb_8 ;
wire un3_t_axb_7 ;
wire un3_t_axb_6 ;
wire un3_t_axb_5 ;
wire un3_t_axb_4 ;
wire un3_t_axb_3 ;
wire un3_t_axb_1 ;
wire un3_t_axb_0 ;
wire reg3_1_1_axb_28 ;
wire reg3_1_1_axb_27 ;
wire reg3_1_1_axb_26 ;
wire reg3_1_1_axb_25 ;
wire reg3_1_1_axb_24 ;
wire reg3_1_1_axb_23 ;
wire reg3_1_1_axb_22 ;
wire reg3_1_1_axb_21 ;
wire reg3_1_1_axb_20 ;
wire t_1_cry_0_cy ;
wire un3_t_cry_0_cy ;
wire N_7 ;
wire N_12 ;
wire \d_cnst_sn.g0_3_a2_2 ;
wire \d_cnst_sn.g0_3_1 ;
wire \d_cnst_sn.g3 ;
wire \d_cnst_sn.reg0_N_13_0 ;
wire \d_cnst_sn.g0_0_2 ;
wire \d_cnst_sn.g0_1 ;
wire N_7_0 ;
wire \d_cnst_sn.g0_0_0_a5_0_0 ;
wire \d_cnst_sn.g0_0_0_a5_2 ;
wire \d_cnst_sn.g0_0_0_1 ;
wire N_3856_rep1 ;
wire N_3569_rep1 ;
wire N_3289_rep1 ;
wire N_3315_rep1 ;
wire N_3550_rep1 ;
wire N_3341_rep1 ;
wire N_3673_rep1 ;
wire N_3699_rep1 ;
wire N_3725_rep1 ;
wire N_3751_rep1 ;
wire N_3777_rep1 ;
wire N_3803_rep1 ;
wire N_3829_rep1 ;
wire \d_cnst_sn.g0_rn_1 ;
wire reg0_28_7_rep1 ;
wire d_cnst_ss0_x ;
wire un1_cf_x ;
wire un3_reg3_cry_25_0 ;
wire un3_reg3_cry_25_1 ;
wire inf_abs0_2_cry_29_0 ;
wire inf_abs0_2_cry_29_1 ;
input p_b_Z_p_O_FDC ;
input p_desc52_p_O_FDC ;
input p_desc53_p_O_FDC ;
input p_desc54_p_O_FDC ;
input p_desc55_p_O_FDC ;
input p_desc56_p_O_FDC ;
input p_desc57_p_O_FDC ;
input p_desc58_p_O_FDC ;
input p_desc59_p_O_FDC ;
input p_desc60_p_O_FDC ;
input p_desc61_p_O_FDC ;
input p_desc62_p_O_FDC ;
input p_desc63_p_O_FDC ;
input p_desc64_p_O_FDC ;
input p_desc65_p_O_FDC ;
input p_desc66_p_O_FDC ;
input p_desc67_p_O_FDC ;
input p_desc68_p_O_FDC ;
input p_desc69_p_O_FDC ;
input p_desc70_p_O_FDC ;
input p_desc71_p_O_FDC ;
input p_desc72_p_O_FDC ;
input p_desc73_p_O_FDC ;
input p_desc74_p_O_FDC ;
input p_desc75_p_O_FDC ;
input p_desc76_p_O_FDC ;
input p_desc77_p_O_FDC ;
input p_desc78_p_O_FDC ;
input p_desc79_p_O_FDC ;
input p_desc80_p_O_FDC ;
input p_desc81_p_O_FDC ;
input p_desc82_p_O_FDC ;
input p_desc83_p_O_FDC ;
input p_rd_Z_p_O_FDC ;
input p_desc261_p_O_FDC ;
input p_wr_Z_p_O_FDC ;
input p_desc262_p_O_FDC ;
input p_desc50_p_O_FDCE ;
input p_desc51_p_O_FDCE ;
input p_desc84_p_O_FDCE ;
input p_desc85_p_O_FDCE ;
input p_desc86_p_O_FDCE ;
input p_desc87_p_O_FDCE ;
input p_desc88_p_O_FDCE ;
input p_desc89_p_O_FDCE ;
input p_desc90_p_O_FDCE ;
input p_desc91_p_O_FDCE ;
input p_desc92_p_O_FDCE ;
input p_desc93_p_O_FDCE ;
input p_desc94_p_O_FDCE ;
input p_desc95_p_O_FDCE ;
input p_desc96_p_O_FDCE ;
input p_desc97_p_O_FDCE ;
input p_desc98_p_O_FDCE ;
input p_desc99_p_O_FDCE ;
input p_desc100_p_O_FDCE ;
input p_desc101_p_O_FDCE ;
input p_desc102_p_O_FDCE ;
input p_desc103_p_O_FDCE ;
input p_desc104_p_O_FDCE ;
input p_desc105_p_O_FDCE ;
input p_desc106_p_O_FDCE ;
input p_desc107_p_O_FDCE ;
input p_desc108_p_O_FDCE ;
input p_desc109_p_O_FDCE ;
input p_desc110_p_O_FDCE ;
input p_desc111_p_O_FDCE ;
input p_desc112_p_O_FDCE ;
input p_desc113_p_O_FDCE ;
input p_desc114_p_O_FDCE ;
input p_desc115_p_O_FDCE ;
input p_desc116_p_O_FDCE ;
input p_desc117_p_O_FDCE ;
input p_desc118_p_O_FDCE ;
input p_desc119_p_O_FDCE ;
input p_desc120_p_O_FDCE ;
input p_desc121_p_O_FDCE ;
input p_desc122_p_O_FDCE ;
input p_desc123_p_O_FDCE ;
input p_desc124_p_O_FDCE ;
input p_desc125_p_O_FDCE ;
input p_desc126_p_O_FDCE ;
input p_desc127_p_O_FDCE ;
input p_desc128_p_O_FDCE ;
input p_desc129_p_O_FDCE ;
input p_desc130_p_O_FDCE ;
input p_desc131_p_O_FDCE ;
input p_desc132_p_O_FDCE ;
input p_desc133_p_O_FDCE ;
input p_desc134_p_O_FDCE ;
input p_desc135_p_O_FDCE ;
input p_desc136_p_O_FDCE ;
input p_desc137_p_O_FDCE ;
input p_desc138_p_O_FDCE ;
input p_desc139_p_O_FDCE ;
input p_desc140_p_O_FDCE ;
input p_desc141_p_O_FDCE ;
input p_desc142_p_O_FDCE ;
input p_desc143_p_O_FDCE ;
input p_desc144_p_O_FDCE ;
input p_desc145_p_O_FDCE ;
input p_desc146_p_O_FDCE ;
input p_desc147_p_O_FDCE ;
input p_desc148_p_O_FDCE ;
input p_desc149_p_O_FDCE ;
input p_desc150_p_O_FDCE ;
input p_desc151_p_O_FDCE ;
input p_desc152_p_O_FDCE ;
input p_desc153_p_O_FDCE ;
input p_desc154_p_O_FDCE ;
input p_desc155_p_O_FDCE ;
input p_desc156_p_O_FDCE ;
input p_desc157_p_O_FDCE ;
input p_desc158_p_O_FDCE ;
input p_desc159_p_O_FDCE ;
input p_desc160_p_O_FDCE ;
input p_desc161_p_O_FDCE ;
input p_desc162_p_O_FDCE ;
input p_desc163_p_O_FDCE ;
input p_desc164_p_O_FDCE ;
input p_desc165_p_O_FDCE ;
input p_desc166_p_O_FDCE ;
input p_desc167_p_O_FDCE ;
input p_desc168_p_O_FDCE ;
input p_desc169_p_O_FDCE ;
input p_desc170_p_O_FDCE ;
input p_desc171_p_O_FDCE ;
input p_desc172_p_O_FDCE ;
input p_desc173_p_O_FDCE ;
input p_desc174_p_O_FDCE ;
input p_desc175_p_O_FDCE ;
input p_desc176_p_O_FDCE ;
input p_desc177_p_O_FDCE ;
input p_desc178_p_O_FDCE ;
input p_desc179_p_O_FDCE ;
input p_desc180_p_O_FDCE ;
input p_desc181_p_O_FDCE ;
input p_desc182_p_O_FDCE ;
input p_desc183_p_O_FDCE ;
input p_desc184_p_O_FDCE ;
input p_desc185_p_O_FDCE ;
input p_desc186_p_O_FDCE ;
input p_desc187_p_O_FDCE ;
input p_desc188_p_O_FDCE ;
input p_desc189_p_O_FDCE ;
input p_desc190_p_O_FDCE ;
input p_desc191_p_O_FDCE ;
input p_desc192_p_O_FDCE ;
input p_desc193_p_O_FDCE ;
input p_desc194_p_O_FDCE ;
input p_desc195_p_O_FDCE ;
input p_desc196_p_O_FDCE ;
input p_desc197_p_O_FDCE ;
input p_desc198_p_O_FDCE ;
input p_desc199_p_O_FDCE ;
input p_desc200_p_O_FDCE ;
input p_desc201_p_O_FDCE ;
input p_desc202_p_O_FDCE ;
input p_desc203_p_O_FDCE ;
input p_desc204_p_O_FDCE ;
input p_desc205_p_O_FDCE ;
input p_desc206_p_O_FDCE ;
input p_desc207_p_O_FDCE ;
input p_desc208_p_O_FDCE ;
input p_desc209_p_O_FDCE ;
input p_desc210_p_O_FDCE ;
input p_desc211_p_O_FDCE ;
input p_desc212_p_O_FDCE ;
input p_desc213_p_O_FDCE ;
input p_desc214_p_O_FDCE ;
input p_desc215_p_O_FDCE ;
input p_desc216_p_O_FDCE ;
input p_desc217_p_O_FDCE ;
input p_desc218_p_O_FDCE ;
input p_desc219_p_O_FDCE ;
input p_desc220_p_O_FDCE ;
input p_desc221_p_O_FDCE ;
input p_desc222_p_O_FDCE ;
input p_desc223_p_O_FDCE ;
input p_desc224_p_O_FDCE ;
input p_desc225_p_O_FDCE ;
input p_desc226_p_O_FDCE ;
input p_desc227_p_O_FDCE ;
input p_desc228_p_O_FDCE ;
input p_desc229_p_O_FDCE ;
input p_desc230_p_O_FDCE ;
input p_desc231_p_O_FDCE ;
input p_desc232_p_O_FDCE ;
input p_desc233_p_O_FDCE ;
input p_desc234_p_O_FDCE ;
input p_desc235_p_O_FDCE ;
input p_desc236_p_O_FDCE ;
input p_desc237_p_O_FDCE ;
input p_desc238_p_O_FDCE ;
input p_desc239_p_O_FDCE ;
input p_desc240_p_O_FDCE ;
input p_desc241_p_O_FDCE ;
input p_desc242_p_O_FDCE ;
input p_desc243_p_O_FDCE ;
input p_desc244_p_O_FDCE ;
input p_desc245_p_O_FDCE ;
input p_desc246_p_O_FDCE ;
input p_desc247_p_O_FDCE ;
input p_desc248_p_O_FDCE ;
input p_desc249_p_O_FDCE ;
input p_desc250_p_O_FDCE ;
input p_desc251_p_O_FDCE ;
input p_desc252_p_O_FDCE ;
input p_desc253_p_O_FDCE ;
input p_desc254_p_O_FDCE ;
input p_desc255_p_O_FDCE ;
input p_desc256_p_O_FDCE ;
input p_desc257_p_O_FDCE ;
input p_desc258_p_O_FDCE ;
input p_desc259_p_O_FDCE ;
input p_desc260_p_O_FDCE ;
// instances
GND GND_cZ(.G(GND));
VCC VCC_cZ(.P(VCC));
MUXF8 desc0(.I0(\d_cnst_sn.reg2_16_11muxnet_0 [1:1]),.I1(\d_cnst_sn.reg2_16_11muxnet_1 [1:1]),.S(N_513_i),.O(reg2_16[1:1]));
MUXF7 desc1(.I0(N_1560),.I1(t_6[1:1]),.S(N_514_i),.O(\d_cnst_sn.reg2_16_11muxnet_1 [1:1]));
MUXF7 desc2(.I0(N_1336),.I1(N_1368),.S(N_514_i),.O(\d_cnst_sn.reg2_16_11muxnet_0 [1:1]));
LUT1 inf_abs0_2_cry_29_outextlut(.I0(VCC),.O(inf_abs0_2_cry_29_1));
defparam inf_abs0_2_cry_29_outextlut.INIT=2'h3;
LUT1 un3_reg3_cry_25_outextlut(.I0(VCC),.O(un3_reg3_cry_25_1));
defparam un3_reg3_cry_25_outextlut.INIT=2'h3;
LUT1 inf_abs0_2_cry_30_outextlut(.I0(VCC),.O(inf_abs0_2_1[31:31]));
defparam inf_abs0_2_cry_30_outextlut.INIT=2'h3;
LUT6_2 desc3(.I0(reg0[30:30]),.I1(reg1[30:30]),.I2(reg2[30:30]),.I3(inf_abs0_2[29:29]),.I4(inf_abs0_2[30:30]),.I5(inf_abs0_2[31:31]),.O6(r_4[30:30]),.O5(r_4_3_lut6_2_O5[30:30]));
defparam desc3.INIT=64'hAAAAAAAA00F0CCAA;
LUT4 un11_r_df0_cZ(.I0(m_2[0:0]),.I1(m_2[1:1]),.I2(r_4[0:0]),.I3(r_4[1:1]),.O(un11_r_df0));
defparam un11_r_df0_cZ.INIT=16'h8421;
LUT4 un11_r_df2_cZ(.I0(N_28),.I1(m_2[2:2]),.I2(m_2[3:3]),.I3(r_4[3:3]),.O(un11_r_df2));
defparam un11_r_df2_cZ.INIT=16'h9009;
LUT4 un11_r_df4_cZ(.I0(m_2[4:4]),.I1(m_2[5:5]),.I2(r_4[4:4]),.I3(r_4[5:5]),.O(un11_r_df4));
defparam un11_r_df4_cZ.INIT=16'h8421;
LUT4 un11_r_df6_cZ(.I0(m_2[6:6]),.I1(m_2[7:7]),.I2(r_4[6:6]),.I3(r_4[7:7]),.O(un11_r_df6));
defparam un11_r_df6_cZ.INIT=16'h8421;
LUT4 un11_r_df8_cZ(.I0(m_2[8:8]),.I1(m_2[9:9]),.I2(r_4[8:8]),.I3(r_4[9:9]),.O(un11_r_df8));
defparam un11_r_df8_cZ.INIT=16'h8421;
LUT4 un11_r_df10_cZ(.I0(m_2[10:10]),.I1(m_2[11:11]),.I2(r_4[10:10]),.I3(r_4[11:11]),.O(un11_r_df10));
defparam un11_r_df10_cZ.INIT=16'h8421;
LUT4 un11_r_df12_cZ(.I0(m_2[12:12]),.I1(m_2[13:13]),.I2(r_4[12:12]),.I3(r_4[13:13]),.O(un11_r_df12));
defparam un11_r_df12_cZ.INIT=16'h8421;
LUT4 un11_r_df14_cZ(.I0(m_2[14:14]),.I1(m_2[15:15]),.I2(r_4[14:14]),.I3(r_4[15:15]),.O(un11_r_df14));
defparam un11_r_df14_cZ.INIT=16'h8421;
LUT4 un11_r_df16_cZ(.I0(m_2[16:16]),.I1(m_2[17:17]),.I2(r_4[16:16]),.I3(r_4[17:17]),.O(un11_r_df16));
defparam un11_r_df16_cZ.INIT=16'h8421;
LUT4 un11_r_df18_cZ(.I0(m_2[18:18]),.I1(m_2[19:19]),.I2(r_4[18:18]),.I3(r_4[19:19]),.O(un11_r_df18));
defparam un11_r_df18_cZ.INIT=16'h8421;
LUT4 b18_df0_cZ(.I0(m_2[0:0]),.I1(m_2[1:1]),.I2(r_4[0:0]),.I3(r_4[1:1]),.O(b18_df0));
defparam b18_df0_cZ.INIT=16'h8421;
LUT4 b18_df2_cZ(.I0(N_28),.I1(m_2[2:2]),.I2(m_2[3:3]),.I3(r_4[3:3]),.O(b18_df2));
defparam b18_df2_cZ.INIT=16'h9009;
LUT4 b18_df4_cZ(.I0(m_2[4:4]),.I1(m_2[5:5]),.I2(r_4[4:4]),.I3(r_4[5:5]),.O(b18_df4));
defparam b18_df4_cZ.INIT=16'h8421;
LUT4 b18_df6_cZ(.I0(m_2[6:6]),.I1(m_2[7:7]),.I2(r_4[6:6]),.I3(r_4[7:7]),.O(b18_df6));
defparam b18_df6_cZ.INIT=16'h8421;
LUT4 b18_df8_cZ(.I0(m_2[8:8]),.I1(m_2[9:9]),.I2(r_4[8:8]),.I3(r_4[9:9]),.O(b18_df8));
defparam b18_df8_cZ.INIT=16'h8421;
LUT4 b18_df10_cZ(.I0(m_2[10:10]),.I1(m_2[11:11]),.I2(r_4[10:10]),.I3(r_4[11:11]),.O(b18_df10));
defparam b18_df10_cZ.INIT=16'h8421;
LUT4 b18_df12_cZ(.I0(m_2[12:12]),.I1(m_2[13:13]),.I2(r_4[12:12]),.I3(r_4[13:13]),.O(b18_df12));
defparam b18_df12_cZ.INIT=16'h8421;
LUT4 b18_df14_cZ(.I0(m_2[14:14]),.I1(m_2[15:15]),.I2(r_4[14:14]),.I3(r_4[15:15]),.O(b18_df14));
defparam b18_df14_cZ.INIT=16'h8421;
LUT4 b18_df16_cZ(.I0(m_2[16:16]),.I1(m_2[17:17]),.I2(r_4[16:16]),.I3(r_4[17:17]),.O(b18_df16));
defparam b18_df16_cZ.INIT=16'h8421;
LUT4 b18_df18_cZ(.I0(m_2[18:18]),.I1(m_2[19:19]),.I2(r_4[18:18]),.I3(r_4[19:19]),.O(b18_df18));
defparam b18_df18_cZ.INIT=16'h8421;
LUT4 un26_r_df0_cZ(.I0(m_2[0:0]),.I1(m_2[1:1]),.I2(r_4[0:0]),.I3(r_4[1:1]),.O(un26_r_df0));
defparam un26_r_df0_cZ.INIT=16'h8421;
LUT4 un26_r_df2_cZ(.I0(N_28),.I1(m_2[2:2]),.I2(m_2[3:3]),.I3(r_4[3:3]),.O(un26_r_df2));
defparam un26_r_df2_cZ.INIT=16'h9009;
LUT4 un26_r_df4_cZ(.I0(m_2[4:4]),.I1(m_2[5:5]),.I2(r_4[4:4]),.I3(r_4[5:5]),.O(un26_r_df4));
defparam un26_r_df4_cZ.INIT=16'h8421;
LUT4 un26_r_df6_cZ(.I0(m_2[6:6]),.I1(m_2[7:7]),.I2(r_4[6:6]),.I3(r_4[7:7]),.O(un26_r_df6));
defparam un26_r_df6_cZ.INIT=16'h8421;
LUT4 un26_r_df8_cZ(.I0(m_2[8:8]),.I1(m_2[9:9]),.I2(r_4[8:8]),.I3(r_4[9:9]),.O(un26_r_df8));
defparam un26_r_df8_cZ.INIT=16'h8421;
LUT4 un26_r_df10_cZ(.I0(m_2[10:10]),.I1(m_2[11:11]),.I2(r_4[10:10]),.I3(r_4[11:11]),.O(un26_r_df10));
defparam un26_r_df10_cZ.INIT=16'h8421;
LUT4 un26_r_df12_cZ(.I0(m_2[12:12]),.I1(m_2[13:13]),.I2(r_4[12:12]),.I3(r_4[13:13]),.O(un26_r_df12));
defparam un26_r_df12_cZ.INIT=16'h8421;
LUT4 un26_r_df14_cZ(.I0(m_2[14:14]),.I1(m_2[15:15]),.I2(r_4[14:14]),.I3(r_4[15:15]),.O(un26_r_df14));
defparam un26_r_df14_cZ.INIT=16'h8421;
LUT4 un26_r_df16_cZ(.I0(m_2[16:16]),.I1(m_2[17:17]),.I2(r_4[16:16]),.I3(r_4[17:17]),.O(un26_r_df16));
defparam un26_r_df16_cZ.INIT=16'h8421;
LUT4 un26_r_df18_cZ(.I0(m_2[18:18]),.I1(m_2[19:19]),.I2(r_4[18:18]),.I3(r_4[19:19]),.O(un26_r_df18));
defparam un26_r_df18_cZ.INIT=16'h8421;
LUT2 inf_abs0_2_axb_0_cZ(.I0(ir[0:0]),.I1(ir_fast[31:31]),.O(inf_abs0_2_axb_0));
defparam inf_abs0_2_axb_0_cZ.INIT=4'h6;
LUT2 inf_abs0_2_axb_1_cZ(.I0(ir[1:1]),.I1(ir_fast[31:31]),.O(inf_abs0_2_axb_1));
defparam inf_abs0_2_axb_1_cZ.INIT=4'h6;
LUT2 inf_abs0_2_axb_2_cZ(.I0(ir[2:2]),.I1(ir_fast[31:31]),.O(inf_abs0_2_axb_2));
defparam inf_abs0_2_axb_2_cZ.INIT=4'h6;
LUT2 inf_abs0_2_axb_3_cZ(.I0(ir[3:3]),.I1(ir_fast[31:31]),.O(inf_abs0_2_axb_3));
defparam inf_abs0_2_axb_3_cZ.INIT=4'h6;
LUT2 inf_abs0_2_axb_4_cZ(.I0(ir[4:4]),.I1(ir_fast[31:31]),.O(inf_abs0_2_axb_4));
defparam inf_abs0_2_axb_4_cZ.INIT=4'h6;
LUT2 inf_abs0_2_axb_5_cZ(.I0(ir[5:5]),.I1(ir_fast[31:31]),.O(inf_abs0_2_axb_5));
defparam inf_abs0_2_axb_5_cZ.INIT=4'h6;
LUT2 inf_abs0_2_axb_6_cZ(.I0(ir[6:6]),.I1(ir_fast[31:31]),.O(inf_abs0_2_axb_6));
defparam inf_abs0_2_axb_6_cZ.INIT=4'h6;
LUT2 inf_abs0_2_axb_7_cZ(.I0(ir[7:7]),.I1(ir_fast[31:31]),.O(inf_abs0_2_axb_7));
defparam inf_abs0_2_axb_7_cZ.INIT=4'h6;
LUT2 inf_abs0_2_axb_8_cZ(.I0(ir[8:8]),.I1(ir_fast[31:31]),.O(inf_abs0_2_axb_8));
defparam inf_abs0_2_axb_8_cZ.INIT=4'h6;
LUT2 inf_abs0_2_axb_9_cZ(.I0(ir[9:9]),.I1(ir[31:31]),.O(inf_abs0_2_axb_9));
defparam inf_abs0_2_axb_9_cZ.INIT=4'h6;
LUT2 inf_abs0_2_axb_10_cZ(.I0(ir[10:10]),.I1(ir[31:31]),.O(inf_abs0_2_axb_10));
defparam inf_abs0_2_axb_10_cZ.INIT=4'h6;
LUT2 inf_abs0_2_axb_11_cZ(.I0(ir[11:11]),.I1(ir[31:31]),.O(inf_abs0_2_axb_11));
defparam inf_abs0_2_axb_11_cZ.INIT=4'h6;
LUT2 inf_abs0_2_axb_12_cZ(.I0(ir[12:12]),.I1(ir[31:31]),.O(inf_abs0_2_axb_12));
defparam inf_abs0_2_axb_12_cZ.INIT=4'h6;
LUT2 inf_abs0_2_axb_13_cZ(.I0(ir[13:13]),.I1(ir[31:31]),.O(inf_abs0_2_axb_13));
defparam inf_abs0_2_axb_13_cZ.INIT=4'h6;
LUT2 inf_abs0_2_axb_14_cZ(.I0(ir[14:14]),.I1(ir[31:31]),.O(inf_abs0_2_axb_14));
defparam inf_abs0_2_axb_14_cZ.INIT=4'h6;
LUT2 inf_abs0_2_axb_15_cZ(.I0(ir[15:15]),.I1(ir[31:31]),.O(inf_abs0_2_axb_15));
defparam inf_abs0_2_axb_15_cZ.INIT=4'h6;
LUT2 inf_abs0_2_axb_16_cZ(.I0(ir[16:16]),.I1(ir[31:31]),.O(inf_abs0_2_axb_16));
defparam inf_abs0_2_axb_16_cZ.INIT=4'h6;
LUT2 inf_abs0_2_axb_17_cZ(.I0(ir[17:17]),.I1(ir[31:31]),.O(inf_abs0_2_axb_17));
defparam inf_abs0_2_axb_17_cZ.INIT=4'h6;
LUT2 inf_abs0_2_axb_18_cZ(.I0(ir[18:18]),.I1(ir[31:31]),.O(inf_abs0_2_axb_18));
defparam inf_abs0_2_axb_18_cZ.INIT=4'h6;
LUT2 inf_abs0_2_axb_19_cZ(.I0(ir[19:19]),.I1(ir[31:31]),.O(inf_abs0_2_axb_19));
defparam inf_abs0_2_axb_19_cZ.INIT=4'h6;
LUT2 inf_abs0_2_axb_20_cZ(.I0(ir[20:20]),.I1(ir[31:31]),.O(inf_abs0_2_axb_20));
defparam inf_abs0_2_axb_20_cZ.INIT=4'h6;
LUT2 inf_abs0_2_axb_21_cZ(.I0(ir[21:21]),.I1(ir[31:31]),.O(inf_abs0_2_axb_21));
defparam inf_abs0_2_axb_21_cZ.INIT=4'h6;
LUT2 inf_abs0_2_axb_22_cZ(.I0(ir[22:22]),.I1(ir[31:31]),.O(inf_abs0_2_axb_22));
defparam inf_abs0_2_axb_22_cZ.INIT=4'h6;
LUT2 inf_abs0_2_axb_23_cZ(.I0(ir[23:23]),.I1(ir[31:31]),.O(inf_abs0_2_axb_23));
defparam inf_abs0_2_axb_23_cZ.INIT=4'h6;
LUT2 inf_abs0_2_axb_24_cZ(.I0(ir[24:24]),.I1(ir[31:31]),.O(inf_abs0_2_axb_24));
defparam inf_abs0_2_axb_24_cZ.INIT=4'h6;
LUT2 inf_abs0_2_axb_25_cZ(.I0(ir[25:25]),.I1(ir[31:31]),.O(inf_abs0_2_axb_25));
defparam inf_abs0_2_axb_25_cZ.INIT=4'h6;
LUT2 inf_abs0_2_axb_26_cZ(.I0(ir[26:26]),.I1(ir[31:31]),.O(inf_abs0_2_axb_26));
defparam inf_abs0_2_axb_26_cZ.INIT=4'h6;
LUT2 inf_abs0_2_axb_27_cZ(.I0(ir[27:27]),.I1(ir[31:31]),.O(inf_abs0_2_axb_27));
defparam inf_abs0_2_axb_27_cZ.INIT=4'h6;
LUT2 inf_abs0_2_axb_28_cZ(.I0(ir[28:28]),.I1(ir[31:31]),.O(inf_abs0_2_axb_28));
defparam inf_abs0_2_axb_28_cZ.INIT=4'h6;
LUT4 desc4(.I0(datai[20:20]),.I1(inf_abs0_2[27:27]),.I2(inf_abs0_2[28:28]),.I3(inf_abs0_2[31:31]),.O(reg3_1_1_axb_20));
defparam desc4.INIT=16'hFF57;
LUT4 desc5(.I0(datai[21:21]),.I1(inf_abs0_2[27:27]),.I2(inf_abs0_2[28:28]),.I3(inf_abs0_2[31:31]),.O(reg3_1_1_axb_21));
defparam desc5.INIT=16'hFF57;
LUT4 desc6(.I0(datai[22:22]),.I1(inf_abs0_2[27:27]),.I2(inf_abs0_2[28:28]),.I3(inf_abs0_2[31:31]),.O(reg3_1_1_axb_22));
defparam desc6.INIT=16'hFF57;
LUT4 desc7(.I0(datai[23:23]),.I1(inf_abs0_2[27:27]),.I2(inf_abs0_2[28:28]),.I3(inf_abs0_2[31:31]),.O(reg3_1_1_axb_23));
defparam desc7.INIT=16'hFF57;
LUT4 desc8(.I0(datai[24:24]),.I1(inf_abs0_2[27:27]),.I2(inf_abs0_2[28:28]),.I3(inf_abs0_2[31:31]),.O(reg3_1_1_axb_24));
defparam desc8.INIT=16'hFF57;
LUT4 desc9(.I0(datai[25:25]),.I1(inf_abs0_2[27:27]),.I2(inf_abs0_2[28:28]),.I3(inf_abs0_2[31:31]),.O(reg3_1_1_axb_25));
defparam desc9.INIT=16'hFF57;
LUT4 desc10(.I0(datai[26:26]),.I1(inf_abs0_2[27:27]),.I2(inf_abs0_2[28:28]),.I3(inf_abs0_2[31:31]),.O(reg3_1_1_axb_26));
defparam desc10.INIT=16'hFF57;
LUT4 desc11(.I0(datai[27:27]),.I1(inf_abs0_2[27:27]),.I2(inf_abs0_2[28:28]),.I3(inf_abs0_2[31:31]),.O(reg3_1_1_axb_27));
defparam desc11.INIT=16'hFF57;
LUT4 desc12(.I0(datai[28:28]),.I1(inf_abs0_2[27:27]),.I2(inf_abs0_2[28:28]),.I3(inf_abs0_2[31:31]),.O(reg3_1_1_axb_28));
defparam desc12.INIT=16'hFF57;
LUT4 reg3_1_1_axb_29_cZ(.I0(datai[29:29]),.I1(inf_abs0_2[27:27]),.I2(inf_abs0_2[28:28]),.I3(inf_abs0_2[31:31]),.O(reg3_1_1_axb_29));
defparam reg3_1_1_axb_29_cZ.INIT=16'hFF57;
LUT4 reg3_1_1_axb_30_cZ(.I0(datai[30:30]),.I1(inf_abs0_2[27:27]),.I2(inf_abs0_2[28:28]),.I3(inf_abs0_2[31:31]),.O(reg3_1_1_axb_30));
defparam reg3_1_1_axb_30_cZ.INIT=16'hFF57;
LUT2 un1_inf_abs0_cry_0_RNO(.I0(inf_abs0_2[0:0]),.I1(reg2[0:0]),.O(un1_inf_abs0_10[0:0]));
defparam un1_inf_abs0_cry_0_RNO.INIT=4'h6;
LUT2 desc13(.I0(inf_abs0_2[1:1]),.I1(reg2[1:1]),.O(un1_inf_abs0_axb_1));
defparam desc13.INIT=4'h6;
LUT2 desc14(.I0(inf_abs0_2[2:2]),.I1(reg2[2:2]),.O(un1_inf_abs0_axb_2));
defparam desc14.INIT=4'h6;
LUT2 desc15(.I0(inf_abs0_2[3:3]),.I1(reg2[3:3]),.O(un1_inf_abs0_axb_3));
defparam desc15.INIT=4'h6;
LUT2 desc16(.I0(inf_abs0_2[4:4]),.I1(reg2[4:4]),.O(un1_inf_abs0_axb_4));
defparam desc16.INIT=4'h6;
LUT2 desc17(.I0(inf_abs0_2[5:5]),.I1(reg2[5:5]),.O(un1_inf_abs0_axb_5));
defparam desc17.INIT=4'h6;
LUT2 desc18(.I0(inf_abs0_2[6:6]),.I1(reg2[6:6]),.O(un1_inf_abs0_axb_6));
defparam desc18.INIT=4'h6;
LUT2 desc19(.I0(inf_abs0_2[7:7]),.I1(reg2[7:7]),.O(un1_inf_abs0_axb_7));
defparam desc19.INIT=4'h6;
LUT2 desc20(.I0(inf_abs0_2[8:8]),.I1(reg2[8:8]),.O(un1_inf_abs0_axb_8));
defparam desc20.INIT=4'h6;
LUT2 desc21(.I0(inf_abs0_2[9:9]),.I1(reg2[9:9]),.O(un1_inf_abs0_axb_9));
defparam desc21.INIT=4'h6;
LUT2 desc22(.I0(inf_abs0_2[10:10]),.I1(reg2[10:10]),.O(un1_inf_abs0_axb_10));
defparam desc22.INIT=4'h6;
LUT2 desc23(.I0(inf_abs0_2[11:11]),.I1(reg2[11:11]),.O(un1_inf_abs0_axb_11));
defparam desc23.INIT=4'h6;
LUT2 desc24(.I0(inf_abs0_2[12:12]),.I1(reg2[12:12]),.O(un1_inf_abs0_axb_12));
defparam desc24.INIT=4'h6;
LUT2 desc25(.I0(inf_abs0_2[13:13]),.I1(reg2[13:13]),.O(un1_inf_abs0_axb_13));
defparam desc25.INIT=4'h6;
LUT2 desc26(.I0(inf_abs0_2[14:14]),.I1(reg2[14:14]),.O(un1_inf_abs0_axb_14));
defparam desc26.INIT=4'h6;
LUT2 desc27(.I0(inf_abs0_2[15:15]),.I1(reg2[15:15]),.O(un1_inf_abs0_axb_15));
defparam desc27.INIT=4'h6;
LUT2 desc28(.I0(inf_abs0_2[16:16]),.I1(reg2[16:16]),.O(un1_inf_abs0_axb_16));
defparam desc28.INIT=4'h6;
LUT2 desc29(.I0(inf_abs0_2[17:17]),.I1(reg2[17:17]),.O(un1_inf_abs0_axb_17));
defparam desc29.INIT=4'h6;
LUT2 desc30(.I0(inf_abs0_2[18:18]),.I1(reg2[18:18]),.O(un1_inf_abs0_axb_18));
defparam desc30.INIT=4'h6;
LUT2 un1_inf_abs0_0_cry_0_RNO(.I0(inf_abs0_2[0:0]),.I1(reg1[0:0]),.O(un1_inf_abs0_11[0:0]));
defparam un1_inf_abs0_0_cry_0_RNO.INIT=4'h6;
LUT2 desc31(.I0(inf_abs0_2[1:1]),.I1(reg1[1:1]),.O(un1_inf_abs0_0_axb_1));
defparam desc31.INIT=4'h6;
LUT2 desc32(.I0(inf_abs0_2[2:2]),.I1(reg1[2:2]),.O(un1_inf_abs0_0_axb_2));
defparam desc32.INIT=4'h6;
LUT2 desc33(.I0(inf_abs0_2[3:3]),.I1(reg1[3:3]),.O(un1_inf_abs0_0_axb_3));
defparam desc33.INIT=4'h6;
LUT2 desc34(.I0(inf_abs0_2[4:4]),.I1(reg1[4:4]),.O(un1_inf_abs0_0_axb_4));
defparam desc34.INIT=4'h6;
LUT2 desc35(.I0(inf_abs0_2[5:5]),.I1(reg1[5:5]),.O(un1_inf_abs0_0_axb_5));
defparam desc35.INIT=4'h6;
LUT2 desc36(.I0(inf_abs0_2[6:6]),.I1(reg1[6:6]),.O(un1_inf_abs0_0_axb_6));
defparam desc36.INIT=4'h6;
LUT2 desc37(.I0(inf_abs0_2[7:7]),.I1(reg1[7:7]),.O(un1_inf_abs0_0_axb_7));
defparam desc37.INIT=4'h6;
LUT2 desc38(.I0(inf_abs0_2[8:8]),.I1(reg1[8:8]),.O(un1_inf_abs0_0_axb_8));
defparam desc38.INIT=4'h6;
LUT2 desc39(.I0(inf_abs0_2[9:9]),.I1(reg1[9:9]),.O(un1_inf_abs0_0_axb_9));
defparam desc39.INIT=4'h6;
LUT2 desc40(.I0(inf_abs0_2[10:10]),.I1(reg1[10:10]),.O(un1_inf_abs0_0_axb_10));
defparam desc40.INIT=4'h6;
LUT2 desc41(.I0(inf_abs0_2[11:11]),.I1(reg1[11:11]),.O(un1_inf_abs0_0_axb_11));
defparam desc41.INIT=4'h6;
LUT2 desc42(.I0(inf_abs0_2[12:12]),.I1(reg1[12:12]),.O(un1_inf_abs0_0_axb_12));
defparam desc42.INIT=4'h6;
LUT2 desc43(.I0(inf_abs0_2[13:13]),.I1(reg1[13:13]),.O(un1_inf_abs0_0_axb_13));
defparam desc43.INIT=4'h6;
LUT2 desc44(.I0(inf_abs0_2[14:14]),.I1(reg1[14:14]),.O(un1_inf_abs0_0_axb_14));
defparam desc44.INIT=4'h6;
LUT2 desc45(.I0(inf_abs0_2[15:15]),.I1(reg1[15:15]),.O(un1_inf_abs0_0_axb_15));
defparam desc45.INIT=4'h6;
LUT2 desc46(.I0(inf_abs0_2[16:16]),.I1(reg1[16:16]),.O(un1_inf_abs0_0_axb_16));
defparam desc46.INIT=4'h6;
LUT2 desc47(.I0(inf_abs0_2[17:17]),.I1(reg1[17:17]),.O(un1_inf_abs0_0_axb_17));
defparam desc47.INIT=4'h6;
LUT2 desc48(.I0(inf_abs0_2[18:18]),.I1(reg1[18:18]),.O(un1_inf_abs0_0_axb_18));
defparam desc48.INIT=4'h6;
LUT1 un3_reg3_axb_1_cZ(.I0(reg3[4:4]),.O(un3_reg3_axb_1));
defparam un3_reg3_axb_1_cZ.INIT=2'h2;
LUT1 un3_reg3_axb_2_cZ(.I0(reg3[5:5]),.O(un3_reg3_axb_2));
defparam un3_reg3_axb_2_cZ.INIT=2'h2;
LUT1 un3_reg3_axb_3_cZ(.I0(reg3[6:6]),.O(un3_reg3_axb_3));
defparam un3_reg3_axb_3_cZ.INIT=2'h2;
LUT1 un3_reg3_axb_4_cZ(.I0(reg3[7:7]),.O(un3_reg3_axb_4));
defparam un3_reg3_axb_4_cZ.INIT=2'h2;
LUT1 un3_reg3_axb_5_cZ(.I0(reg3[8:8]),.O(un3_reg3_axb_5));
defparam un3_reg3_axb_5_cZ.INIT=2'h2;
LUT1 un3_reg3_axb_6_cZ(.I0(reg3[9:9]),.O(un3_reg3_axb_6));
defparam un3_reg3_axb_6_cZ.INIT=2'h2;
LUT1 un3_reg3_axb_7_cZ(.I0(reg3[10:10]),.O(un3_reg3_axb_7));
defparam un3_reg3_axb_7_cZ.INIT=2'h2;
LUT1 un3_reg3_axb_8_cZ(.I0(reg3[11:11]),.O(un3_reg3_axb_8));
defparam un3_reg3_axb_8_cZ.INIT=2'h2;
LUT1 un3_reg3_axb_9_cZ(.I0(reg3[12:12]),.O(un3_reg3_axb_9));
defparam un3_reg3_axb_9_cZ.INIT=2'h2;
LUT1 un3_reg3_axb_10_cZ(.I0(reg3[13:13]),.O(un3_reg3_axb_10));
defparam un3_reg3_axb_10_cZ.INIT=2'h2;
LUT1 un3_reg3_axb_11_cZ(.I0(reg3[14:14]),.O(un3_reg3_axb_11));
defparam un3_reg3_axb_11_cZ.INIT=2'h2;
LUT1 un3_reg3_axb_12_cZ(.I0(reg3[15:15]),.O(un3_reg3_axb_12));
defparam un3_reg3_axb_12_cZ.INIT=2'h2;
LUT1 un3_reg3_axb_13_cZ(.I0(reg3[16:16]),.O(un3_reg3_axb_13));
defparam un3_reg3_axb_13_cZ.INIT=2'h2;
LUT1 un3_reg3_axb_14_cZ(.I0(reg3[17:17]),.O(un3_reg3_axb_14));
defparam un3_reg3_axb_14_cZ.INIT=2'h2;
LUT1 un3_reg3_axb_15_cZ(.I0(reg3[18:18]),.O(un3_reg3_axb_15));
defparam un3_reg3_axb_15_cZ.INIT=2'h2;
LUT1 un3_reg3_axb_16_cZ(.I0(reg3[19:19]),.O(un3_reg3_axb_16));
defparam un3_reg3_axb_16_cZ.INIT=2'h2;
LUT1 un3_reg3_axb_17_cZ(.I0(reg3[20:20]),.O(un3_reg3_axb_17));
defparam un3_reg3_axb_17_cZ.INIT=2'h2;
LUT1 un3_reg3_axb_18_cZ(.I0(reg3[21:21]),.O(un3_reg3_axb_18));
defparam un3_reg3_axb_18_cZ.INIT=2'h2;
LUT1 un3_reg3_axb_19_cZ(.I0(reg3[22:22]),.O(un3_reg3_axb_19));
defparam un3_reg3_axb_19_cZ.INIT=2'h2;
LUT1 un3_reg3_axb_20_cZ(.I0(reg3[23:23]),.O(un3_reg3_axb_20));
defparam un3_reg3_axb_20_cZ.INIT=2'h2;
LUT1 un3_reg3_axb_21_cZ(.I0(reg3[24:24]),.O(un3_reg3_axb_21));
defparam un3_reg3_axb_21_cZ.INIT=2'h2;
LUT1 un3_reg3_axb_22_cZ(.I0(reg3[25:25]),.O(un3_reg3_axb_22));
defparam un3_reg3_axb_22_cZ.INIT=2'h2;
LUT1 un3_reg3_axb_23_cZ(.I0(reg3[26:26]),.O(un3_reg3_axb_23));
defparam un3_reg3_axb_23_cZ.INIT=2'h2;
LUT1 un3_reg3_axb_24_cZ(.I0(reg3[27:27]),.O(un3_reg3_axb_24));
defparam un3_reg3_axb_24_cZ.INIT=2'h2;
LUT1 un3_reg3_axb_25_cZ(.I0(reg3[28:28]),.O(un3_reg3_axb_25));
defparam un3_reg3_axb_25_cZ.INIT=2'h2;
LUT1 un3_t_s_1_RNIB3TC(.I0(un3_t_s_1),.O(N_4541_i));
defparam un3_t_s_1_RNIB3TC.INIT=2'h1;
LUT1 un3_t_s_2_RNIC3TC(.I0(un3_t_s_2),.O(N_4542_i));
defparam un3_t_s_2_RNIC3TC.INIT=2'h1;
LUT1 un3_t_s_3_RNID3TC(.I0(un3_t_s_3),.O(N_4543_i));
defparam un3_t_s_3_RNID3TC.INIT=2'h1;
LUT1 un3_t_s_4_RNIE3TC(.I0(un3_t_s_4),.O(N_4544_i));
defparam un3_t_s_4_RNIE3TC.INIT=2'h1;
LUT1 un3_t_s_5_RNIF3TC(.I0(un3_t_s_5),.O(N_4545_i));
defparam un3_t_s_5_RNIF3TC.INIT=2'h1;
LUT1 un3_t_s_6_RNIG3TC(.I0(un3_t_s_6),.O(N_4546_i));
defparam un3_t_s_6_RNIG3TC.INIT=2'h1;
LUT1 un3_t_s_7_RNIH3TC(.I0(un3_t_s_7),.O(N_4547_i));
defparam un3_t_s_7_RNIH3TC.INIT=2'h1;
LUT1 un3_t_s_8_RNII3TC(.I0(un3_t_s_8),.O(N_4548_i));
defparam un3_t_s_8_RNII3TC.INIT=2'h1;
LUT1 un3_t_s_9_RNIJ3TC(.I0(un3_t_s_9),.O(N_4549_i));
defparam un3_t_s_9_RNIJ3TC.INIT=2'h1;
LUT1 un3_t_s_10_RNIRF0A(.I0(un3_t_s_10),.O(N_4550_i));
defparam un3_t_s_10_RNIRF0A.INIT=2'h1;
LUT1 un3_t_s_11_RNISF0A(.I0(un3_t_s_11),.O(N_4551_i));
defparam un3_t_s_11_RNISF0A.INIT=2'h1;
LUT1 un3_t_s_12_RNITF0A(.I0(un3_t_s_12),.O(N_4552_i));
defparam un3_t_s_12_RNITF0A.INIT=2'h1;
LUT1 un3_t_s_13_RNIUF0A(.I0(un3_t_s_13),.O(N_4553_i));
defparam un3_t_s_13_RNIUF0A.INIT=2'h1;
LUT1 un3_t_s_14_RNIVF0A(.I0(un3_t_s_14),.O(N_4554_i));
defparam un3_t_s_14_RNIVF0A.INIT=2'h1;
LUT1 un3_t_s_15_RNI0G0A(.I0(un3_t_s_15),.O(N_4555_i));
defparam un3_t_s_15_RNI0G0A.INIT=2'h1;
LUT1 un3_t_s_16_RNI1G0A(.I0(un3_t_s_16),.O(N_4556_i));
defparam un3_t_s_16_RNI1G0A.INIT=2'h1;
LUT1 un3_t_s_17_RNI2G0A(.I0(un3_t_s_17),.O(N_4557_i));
defparam un3_t_s_17_RNI2G0A.INIT=2'h1;
LUT1 un3_t_s_18_RNI3G0A(.I0(un3_t_s_18),.O(N_4558_i));
defparam un3_t_s_18_RNI3G0A.INIT=2'h1;
LUT1 un3_t_s_19_RNI4G0A(.I0(un3_t_s_19),.O(N_4559_i));
defparam un3_t_s_19_RNI4G0A.INIT=2'h1;
LUT1 un3_t_s_20_RNISG0A(.I0(un3_t_s_20),.O(N_4560_i));
defparam un3_t_s_20_RNISG0A.INIT=2'h1;
LUT1 un3_t_s_21_RNITG0A(.I0(un3_t_s_21),.O(N_4561_i));
defparam un3_t_s_21_RNITG0A.INIT=2'h1;
LUT1 un3_t_s_22_RNIUG0A(.I0(un3_t_s_22),.O(N_4562_i));
defparam un3_t_s_22_RNIUG0A.INIT=2'h1;
LUT1 un3_t_s_23_RNIVG0A(.I0(un3_t_s_23),.O(N_4563_i));
defparam un3_t_s_23_RNIVG0A.INIT=2'h1;
LUT1 un3_t_s_24_RNI0H0A(.I0(un3_t_s_24),.O(N_4564_i));
defparam un3_t_s_24_RNI0H0A.INIT=2'h1;
LUT1 un3_t_s_25_RNI1H0A(.I0(un3_t_s_25),.O(N_4565_i));
defparam un3_t_s_25_RNI1H0A.INIT=2'h1;
LUT1 un3_t_s_26_RNI2H0A(.I0(un3_t_s_26),.O(N_4566_i));
defparam un3_t_s_26_RNI2H0A.INIT=2'h1;
LUT1 un3_t_s_27_RNI3H0A(.I0(un3_t_s_27),.O(N_4567_i));
defparam un3_t_s_27_RNI3H0A.INIT=2'h1;
LUT1 un3_t_s_28_RNI4H0A(.I0(un3_t_s_28),.O(N_4568_i));
defparam un3_t_s_28_RNI4H0A.INIT=2'h1;
LUT1 un3_t_s_29_RNI5H0A(.I0(un3_t_s_29),.O(N_4569_i));
defparam un3_t_s_29_RNI5H0A.INIT=2'h1;
LUT1 un3_t_s_30_RNITH0A(.I0(un3_t_s_30),.O(N_4570_i));
defparam un3_t_s_30_RNITH0A.INIT=2'h1;
LUT1 un3_t_s_31_RNIUH0A(.I0(un3_t_s_31),.O(N_4571_i));
defparam un3_t_s_31_RNIUH0A.INIT=2'h1;
LUT2 inf_abs0_2_axb_29_cZ(.I0(ir[29:29]),.I1(ir[31:31]),.O(inf_abs0_2_axb_29));
defparam inf_abs0_2_axb_29_cZ.INIT=4'h6;
LUT4 un26_r_df30_cZ(.I0(m_2[30:30]),.I1(m_2_i[31:31]),.I2(r_4_i[31:31]),.I3(r_6[30:30]),.O(un26_r_df30));
defparam un26_r_df30_cZ.INIT=16'h8241;
LUT4 desc49(.I0(m_2[30:30]),.I1(m_2[31:31]),.I2(r_4[30:30]),.I3(r_4[31:31]),.O(un14_r_0_N_2));
defparam desc49.INIT=16'h8421;
p_O_FDC b_Z(.Q(b),.D(b_0),.C(clock),.CLR(reset),.E(p_b_Z_p_O_FDC));
p_O_FDCE desc50(.Q(d[0:0]),.D(d_cnst),.C(clock),.CLR(reset),.CE(dce),.E(p_desc50_p_O_FDCE));
p_O_FDCE desc51(.Q(d[1:1]),.D(d_cnst_sm0),.C(clock),.CLR(reset),.CE(dce),.E(p_desc51_p_O_FDCE));
p_O_FDC desc52(.Q(ir[22:22]),.D(ir_3[22:22]),.C(clock),.CLR(reset),.E(p_desc52_p_O_FDC));
p_O_FDC desc53(.Q(ir[23:23]),.D(ir_3[23:23]),.C(clock),.CLR(reset),.E(p_desc53_p_O_FDC));
p_O_FDC desc54(.Q(ir[24:24]),.D(ir_3[24:24]),.C(clock),.CLR(reset),.E(p_desc54_p_O_FDC));
p_O_FDC desc55(.Q(ir[25:25]),.D(ir_3[25:25]),.C(clock),.CLR(reset),.E(p_desc55_p_O_FDC));
p_O_FDC desc56(.Q(ir[26:26]),.D(ir_3[26:26]),.C(clock),.CLR(reset),.E(p_desc56_p_O_FDC));
p_O_FDC desc57(.Q(ir[27:27]),.D(ir_3[27:27]),.C(clock),.CLR(reset),.E(p_desc57_p_O_FDC));
p_O_FDC desc58(.Q(ir[28:28]),.D(ir_3[28:28]),.C(clock),.CLR(reset),.E(p_desc58_p_O_FDC));
p_O_FDC desc59(.Q(ir[29:29]),.D(ir_3[29:29]),.C(clock),.CLR(reset),.E(p_desc59_p_O_FDC));
p_O_FDC desc60(.Q(ir[30:30]),.D(ir_3[30:30]),.C(clock),.CLR(reset),.E(p_desc60_p_O_FDC));
p_O_FDC desc61(.Q(ir[31:31]),.D(ir_3[31:31]),.C(clock),.CLR(reset),.E(p_desc61_p_O_FDC));
p_O_FDC desc62(.Q(ir[7:7]),.D(ir_3[7:7]),.C(clock),.CLR(reset),.E(p_desc62_p_O_FDC));
p_O_FDC desc63(.Q(ir[8:8]),.D(ir_3[8:8]),.C(clock),.CLR(reset),.E(p_desc63_p_O_FDC));
p_O_FDC desc64(.Q(ir[9:9]),.D(ir_3[9:9]),.C(clock),.CLR(reset),.E(p_desc64_p_O_FDC));
p_O_FDC desc65(.Q(ir[10:10]),.D(ir_3[10:10]),.C(clock),.CLR(reset),.E(p_desc65_p_O_FDC));
p_O_FDC desc66(.Q(ir[11:11]),.D(ir_3[11:11]),.C(clock),.CLR(reset),.E(p_desc66_p_O_FDC));
p_O_FDC desc67(.Q(ir[12:12]),.D(ir_3[12:12]),.C(clock),.CLR(reset),.E(p_desc67_p_O_FDC));
p_O_FDC desc68(.Q(ir[13:13]),.D(ir_3[13:13]),.C(clock),.CLR(reset),.E(p_desc68_p_O_FDC));
p_O_FDC desc69(.Q(ir[14:14]),.D(ir_3[14:14]),.C(clock),.CLR(reset),.E(p_desc69_p_O_FDC));
p_O_FDC desc70(.Q(ir[15:15]),.D(ir_3[15:15]),.C(clock),.CLR(reset),.E(p_desc70_p_O_FDC));
p_O_FDC desc71(.Q(ir[16:16]),.D(ir_3[16:16]),.C(clock),.CLR(reset),.E(p_desc71_p_O_FDC));
p_O_FDC desc72(.Q(ir[17:17]),.D(ir_3[17:17]),.C(clock),.CLR(reset),.E(p_desc72_p_O_FDC));
p_O_FDC desc73(.Q(ir[18:18]),.D(ir_3[18:18]),.C(clock),.CLR(reset),.E(p_desc73_p_O_FDC));
p_O_FDC desc74(.Q(ir[19:19]),.D(ir_3[19:19]),.C(clock),.CLR(reset),.E(p_desc74_p_O_FDC));
p_O_FDC desc75(.Q(ir[20:20]),.D(ir_3[20:20]),.C(clock),.CLR(reset),.E(p_desc75_p_O_FDC));
p_O_FDC desc76(.Q(ir[21:21]),.D(ir_3[21:21]),.C(clock),.CLR(reset),.E(p_desc76_p_O_FDC));
p_O_FDC desc77(.Q(ir[0:0]),.D(ir_3[0:0]),.C(clock),.CLR(reset),.E(p_desc77_p_O_FDC));
p_O_FDC desc78(.Q(ir[1:1]),.D(ir_3[1:1]),.C(clock),.CLR(reset),.E(p_desc78_p_O_FDC));
p_O_FDC desc79(.Q(ir[2:2]),.D(ir_3[2:2]),.C(clock),.CLR(reset),.E(p_desc79_p_O_FDC));
p_O_FDC desc80(.Q(ir[3:3]),.D(ir_3[3:3]),.C(clock),.CLR(reset),.E(p_desc80_p_O_FDC));
p_O_FDC desc81(.Q(ir[4:4]),.D(ir_3[4:4]),.C(clock),.CLR(reset),.E(p_desc81_p_O_FDC));
p_O_FDC desc82(.Q(ir[5:5]),.D(ir_3[5:5]),.C(clock),.CLR(reset),.E(p_desc82_p_O_FDC));
p_O_FDC desc83(.Q(ir[6:6]),.D(ir_3[6:6]),.C(clock),.CLR(reset),.E(p_desc83_p_O_FDC));
p_O_FDCE desc84(.Q(reg0[31:31]),.D(N_3856_rep1),.C(clock),.CLR(reset),.CE(un1_state_4_i),.E(p_desc84_p_O_FDCE));
p_O_FDCE desc85(.Q(reg0[16:16]),.D(reg0_28[16:16]),.C(clock),.CLR(reset),.CE(un1_state_4_i),.E(p_desc85_p_O_FDCE));
p_O_FDCE desc86(.Q(reg0[17:17]),.D(reg0_28[17:17]),.C(clock),.CLR(reset),.CE(un1_state_4_i),.E(p_desc86_p_O_FDCE));
p_O_FDCE desc87(.Q(reg0[18:18]),.D(reg0_28[18:18]),.C(clock),.CLR(reset),.CE(un1_state_4_i),.E(p_desc87_p_O_FDCE));
p_O_FDCE desc88(.Q(reg0[19:19]),.D(N_3829_rep1),.C(clock),.CLR(reset),.CE(un1_state_4_i),.E(p_desc88_p_O_FDCE));
p_O_FDCE desc89(.Q(reg0[20:20]),.D(N_3803_rep1),.C(clock),.CLR(reset),.CE(un1_state_4_i),.E(p_desc89_p_O_FDCE));
p_O_FDCE desc90(.Q(reg0[21:21]),.D(N_3777_rep1),.C(clock),.CLR(reset),.CE(un1_state_4_i),.E(p_desc90_p_O_FDCE));
p_O_FDCE desc91(.Q(reg0[22:22]),.D(N_3751_rep1),.C(clock),.CLR(reset),.CE(un1_state_4_i),.E(p_desc91_p_O_FDCE));
p_O_FDCE desc92(.Q(reg0[23:23]),.D(N_3725_rep1),.C(clock),.CLR(reset),.CE(un1_state_4_i),.E(p_desc92_p_O_FDCE));
p_O_FDCE desc93(.Q(reg0[24:24]),.D(N_3699_rep1),.C(clock),.CLR(reset),.CE(un1_state_4_i),.E(p_desc93_p_O_FDCE));
p_O_FDCE desc94(.Q(reg0[25:25]),.D(N_3673_rep1),.C(clock),.CLR(reset),.CE(un1_state_4_i),.E(p_desc94_p_O_FDCE));
p_O_FDCE desc95(.Q(reg0[26:26]),.D(N_3341_rep1),.C(clock),.CLR(reset),.CE(un1_state_4_i),.E(p_desc95_p_O_FDCE));
p_O_FDCE desc96(.Q(reg0[27:27]),.D(N_3315_rep1),.C(clock),.CLR(reset),.CE(un1_state_4_i),.E(p_desc96_p_O_FDCE));
p_O_FDCE desc97(.Q(reg0[28:28]),.D(N_3289_rep1),.C(clock),.CLR(reset),.CE(un1_state_4_i),.E(p_desc97_p_O_FDCE));
p_O_FDCE desc98(.Q(reg0[29:29]),.D(N_3569_rep1),.C(clock),.CLR(reset),.CE(un1_state_4_i),.E(p_desc98_p_O_FDCE));
p_O_FDCE desc99(.Q(reg0[30:30]),.D(N_3550_rep1),.C(clock),.CLR(reset),.CE(un1_state_4_i),.E(p_desc99_p_O_FDCE));
p_O_FDCE desc100(.Q(reg0[1:1]),.D(reg0_28[1:1]),.C(clock),.CLR(reset),.CE(un1_state_4_i),.E(p_desc100_p_O_FDCE));
p_O_FDCE desc101(.Q(reg0[2:2]),.D(reg0_28[2:2]),.C(clock),.CLR(reset),.CE(un1_state_4_i),.E(p_desc101_p_O_FDCE));
p_O_FDCE desc102(.Q(reg0[3:3]),.D(reg0_28[3:3]),.C(clock),.CLR(reset),.CE(un1_state_4_i),.E(p_desc102_p_O_FDCE));
p_O_FDCE desc103(.Q(reg0[4:4]),.D(reg0_28[4:4]),.C(clock),.CLR(reset),.CE(un1_state_4_i),.E(p_desc103_p_O_FDCE));
p_O_FDCE desc104(.Q(reg0[5:5]),.D(reg0_28[5:5]),.C(clock),.CLR(reset),.CE(un1_state_4_i),.E(p_desc104_p_O_FDCE));
p_O_FDCE desc105(.Q(reg0[6:6]),.D(reg0_28[6:6]),.C(clock),.CLR(reset),.CE(un1_state_4_i),.E(p_desc105_p_O_FDCE));
p_O_FDCE desc106(.Q(reg0[7:7]),.D(reg0_28_7_rep1),.C(clock),.CLR(reset),.CE(un1_state_4_i),.E(p_desc106_p_O_FDCE));
p_O_FDCE desc107(.Q(reg0[8:8]),.D(reg0_28[8:8]),.C(clock),.CLR(reset),.CE(un1_state_4_i),.E(p_desc107_p_O_FDCE));
p_O_FDCE desc108(.Q(reg0[9:9]),.D(reg0_28[9:9]),.C(clock),.CLR(reset),.CE(un1_state_4_i),.E(p_desc108_p_O_FDCE));
p_O_FDCE desc109(.Q(reg0[10:10]),.D(reg0_28[10:10]),.C(clock),.CLR(reset),.CE(un1_state_4_i),.E(p_desc109_p_O_FDCE));
p_O_FDCE desc110(.Q(reg0[11:11]),.D(reg0_28[11:11]),.C(clock),.CLR(reset),.CE(un1_state_4_i),.E(p_desc110_p_O_FDCE));
p_O_FDCE desc111(.Q(reg0[12:12]),.D(reg0_28[12:12]),.C(clock),.CLR(reset),.CE(un1_state_4_i),.E(p_desc111_p_O_FDCE));
p_O_FDCE desc112(.Q(reg0[13:13]),.D(reg0_28[13:13]),.C(clock),.CLR(reset),.CE(un1_state_4_i),.E(p_desc112_p_O_FDCE));
p_O_FDCE desc113(.Q(reg0[14:14]),.D(reg0_28[14:14]),.C(clock),.CLR(reset),.CE(un1_state_4_i),.E(p_desc113_p_O_FDCE));
p_O_FDCE desc114(.Q(reg0[15:15]),.D(reg0_28[15:15]),.C(clock),.CLR(reset),.CE(un1_state_4_i),.E(p_desc114_p_O_FDCE));
p_O_FDCE desc115(.Q(reg1[18:18]),.D(reg1_16[18:18]),.C(clock),.CLR(reset),.CE(un1_state_3_i),.E(p_desc115_p_O_FDCE));
p_O_FDCE desc116(.Q(reg1[19:19]),.D(reg0_28_3_2492),.C(clock),.CLR(reset),.CE(un1_state_3_i),.E(p_desc116_p_O_FDCE));
p_O_FDCE desc117(.Q(reg1[20:20]),.D(reg0_28_4_2459),.C(clock),.CLR(reset),.CE(un1_state_3_i),.E(p_desc117_p_O_FDCE));
p_O_FDCE desc118(.Q(reg1[21:21]),.D(reg0_28_5_2426),.C(clock),.CLR(reset),.CE(un1_state_3_i),.E(p_desc118_p_O_FDCE));
p_O_FDCE desc119(.Q(reg1[22:22]),.D(reg0_28_6_2393),.C(clock),.CLR(reset),.CE(un1_state_3_i),.E(p_desc119_p_O_FDCE));
p_O_FDCE desc120(.Q(reg1[23:23]),.D(reg0_28_7_2360),.C(clock),.CLR(reset),.CE(un1_state_3_i),.E(p_desc120_p_O_FDCE));
p_O_FDCE desc121(.Q(reg1[24:24]),.D(reg0_28_8_2327),.C(clock),.CLR(reset),.CE(un1_state_3_i),.E(p_desc121_p_O_FDCE));
p_O_FDCE desc122(.Q(reg1[25:25]),.D(N_3673),.C(clock),.CLR(reset),.CE(un1_state_3_i),.E(p_desc122_p_O_FDCE));
p_O_FDCE desc123(.Q(reg1[26:26]),.D(reg1_16_7_1870),.C(clock),.CLR(reset),.CE(un1_state_3_i),.E(p_desc123_p_O_FDCE));
p_O_FDCE desc124(.Q(reg1[27:27]),.D(reg1_16_8_1837),.C(clock),.CLR(reset),.CE(un1_state_3_i),.E(p_desc124_p_O_FDCE));
p_O_FDCE desc125(.Q(reg1[28:28]),.D(reg1_16_9),.C(clock),.CLR(reset),.CE(un1_state_3_i),.E(p_desc125_p_O_FDCE));
p_O_FDCE desc126(.Q(reg1[29:29]),.D(reg0_28_10_2261_a6_3_2_lut6_2_RNIOK9O5),.C(clock),.CLR(reset),.CE(un1_state_3_i),.E(p_desc126_p_O_FDCE));
p_O_FDCE desc127(.Q(reg1[30:30]),.D(N_3550),.C(clock),.CLR(reset),.CE(un1_state_3_i),.E(p_desc127_p_O_FDCE));
p_O_FDCE desc128(.Q(reg1[31:31]),.D(N_3856),.C(clock),.CLR(reset),.CE(un1_state_3_i),.E(p_desc128_p_O_FDCE));
p_O_FDCE desc129(.Q(reg0[0:0]),.D(reg0_28[0:0]),.C(clock),.CLR(reset),.CE(un1_state_4_i),.E(p_desc129_p_O_FDCE));
p_O_FDCE desc130(.Q(reg1[3:3]),.D(reg1_16[3:3]),.C(clock),.CLR(reset),.CE(un1_state_3_i),.E(p_desc130_p_O_FDCE));
p_O_FDCE desc131(.Q(reg1[4:4]),.D(reg1_16[4:4]),.C(clock),.CLR(reset),.CE(un1_state_3_i),.E(p_desc131_p_O_FDCE));
p_O_FDCE desc132(.Q(reg1[5:5]),.D(reg1_16[5:5]),.C(clock),.CLR(reset),.CE(un1_state_3_i),.E(p_desc132_p_O_FDCE));
p_O_FDCE desc133(.Q(reg1[6:6]),.D(reg1_16[6:6]),.C(clock),.CLR(reset),.CE(un1_state_3_i),.E(p_desc133_p_O_FDCE));
p_O_FDCE desc134(.Q(reg1[7:7]),.D(reg0_28[7:7]),.C(clock),.CLR(reset),.CE(un1_state_3_i),.E(p_desc134_p_O_FDCE));
p_O_FDCE desc135(.Q(reg1[8:8]),.D(reg1_16[8:8]),.C(clock),.CLR(reset),.CE(un1_state_3_i),.E(p_desc135_p_O_FDCE));
p_O_FDCE desc136(.Q(reg1[9:9]),.D(reg1_16[9:9]),.C(clock),.CLR(reset),.CE(un1_state_3_i),.E(p_desc136_p_O_FDCE));
p_O_FDCE desc137(.Q(reg1[10:10]),.D(reg1_16[10:10]),.C(clock),.CLR(reset),.CE(un1_state_3_i),.E(p_desc137_p_O_FDCE));
p_O_FDCE desc138(.Q(reg1[11:11]),.D(reg1_16[11:11]),.C(clock),.CLR(reset),.CE(un1_state_3_i),.E(p_desc138_p_O_FDCE));
p_O_FDCE desc139(.Q(reg1[12:12]),.D(reg1_16[12:12]),.C(clock),.CLR(reset),.CE(un1_state_3_i),.E(p_desc139_p_O_FDCE));
p_O_FDCE desc140(.Q(reg1[13:13]),.D(reg1_16[13:13]),.C(clock),.CLR(reset),.CE(un1_state_3_i),.E(p_desc140_p_O_FDCE));
p_O_FDCE desc141(.Q(reg1[14:14]),.D(reg1_16[14:14]),.C(clock),.CLR(reset),.CE(un1_state_3_i),.E(p_desc141_p_O_FDCE));
p_O_FDCE desc142(.Q(reg1[15:15]),.D(reg1_16[15:15]),.C(clock),.CLR(reset),.CE(un1_state_3_i),.E(p_desc142_p_O_FDCE));
p_O_FDCE desc143(.Q(reg1[16:16]),.D(reg1_16[16:16]),.C(clock),.CLR(reset),.CE(un1_state_3_i),.E(p_desc143_p_O_FDCE));
p_O_FDCE desc144(.Q(reg1[17:17]),.D(reg1_16[17:17]),.C(clock),.CLR(reset),.CE(un1_state_3_i),.E(p_desc144_p_O_FDCE));
p_O_FDCE desc145(.Q(reg2[20:20]),.D(reg2_16[20:20]),.C(clock),.CLR(reset),.CE(un1_state_1_0_i),.E(p_desc145_p_O_FDCE));
p_O_FDCE desc146(.Q(reg2[21:21]),.D(reg2_16[21:21]),.C(clock),.CLR(reset),.CE(un1_state_1_0_i),.E(p_desc146_p_O_FDCE));
p_O_FDCE desc147(.Q(reg2[22:22]),.D(reg2_16[22:22]),.C(clock),.CLR(reset),.CE(un1_state_1_0_i),.E(p_desc147_p_O_FDCE));
p_O_FDCE desc148(.Q(reg2[23:23]),.D(reg2_16[23:23]),.C(clock),.CLR(reset),.CE(un1_state_1_0_i),.E(p_desc148_p_O_FDCE));
p_O_FDCE desc149(.Q(reg2[24:24]),.D(reg2_16[24:24]),.C(clock),.CLR(reset),.CE(un1_state_1_0_i),.E(p_desc149_p_O_FDCE));
p_O_FDCE desc150(.Q(reg2[25:25]),.D(reg2_16[25:25]),.C(clock),.CLR(reset),.CE(un1_state_1_0_i),.E(p_desc150_p_O_FDCE));
p_O_FDCE desc151(.Q(reg2[26:26]),.D(reg2_16[26:26]),.C(clock),.CLR(reset),.CE(un1_state_1_0_i),.E(p_desc151_p_O_FDCE));
p_O_FDCE desc152(.Q(reg2[27:27]),.D(reg2_16[27:27]),.C(clock),.CLR(reset),.CE(un1_state_1_0_i),.E(p_desc152_p_O_FDCE));
p_O_FDCE desc153(.Q(reg2[28:28]),.D(reg2_16[28:28]),.C(clock),.CLR(reset),.CE(un1_state_1_0_i),.E(p_desc153_p_O_FDCE));
p_O_FDCE desc154(.Q(reg2[29:29]),.D(reg2_16[29:29]),.C(clock),.CLR(reset),.CE(un1_state_1_0_i),.E(p_desc154_p_O_FDCE));
p_O_FDCE desc155(.Q(reg2[30:30]),.D(reg2_16[30:30]),.C(clock),.CLR(reset),.CE(un1_state_1_0_i),.E(p_desc155_p_O_FDCE));
p_O_FDCE desc156(.Q(reg2[31:31]),.D(reg2_16[31:31]),.C(clock),.CLR(reset),.CE(un1_state_1_0_i),.E(p_desc156_p_O_FDCE));
p_O_FDCE desc157(.Q(reg1[0:0]),.D(reg1_16[0:0]),.C(clock),.CLR(reset),.CE(un1_state_3_i),.E(p_desc157_p_O_FDCE));
p_O_FDCE desc158(.Q(reg1[1:1]),.D(reg1_16[1:1]),.C(clock),.CLR(reset),.CE(un1_state_3_i),.E(p_desc158_p_O_FDCE));
p_O_FDCE desc159(.Q(reg1[2:2]),.D(reg1_16[2:2]),.C(clock),.CLR(reset),.CE(un1_state_3_i),.E(p_desc159_p_O_FDCE));
p_O_FDCE desc160(.Q(reg2[5:5]),.D(reg2_16[5:5]),.C(clock),.CLR(reset),.CE(un1_state_1_0_i),.E(p_desc160_p_O_FDCE));
p_O_FDCE desc161(.Q(reg2[6:6]),.D(reg2_16[6:6]),.C(clock),.CLR(reset),.CE(un1_state_1_0_i),.E(p_desc161_p_O_FDCE));
p_O_FDCE desc162(.Q(reg2[7:7]),.D(reg2_16[7:7]),.C(clock),.CLR(reset),.CE(un1_state_1_0_i),.E(p_desc162_p_O_FDCE));
p_O_FDCE desc163(.Q(reg2[8:8]),.D(reg2_16[8:8]),.C(clock),.CLR(reset),.CE(un1_state_1_0_i),.E(p_desc163_p_O_FDCE));
p_O_FDCE desc164(.Q(reg2[9:9]),.D(reg2_16[9:9]),.C(clock),.CLR(reset),.CE(un1_state_1_0_i),.E(p_desc164_p_O_FDCE));
p_O_FDCE desc165(.Q(reg2[10:10]),.D(reg2_16[10:10]),.C(clock),.CLR(reset),.CE(un1_state_1_0_i),.E(p_desc165_p_O_FDCE));
p_O_FDCE desc166(.Q(reg2[11:11]),.D(reg2_16[11:11]),.C(clock),.CLR(reset),.CE(un1_state_1_0_i),.E(p_desc166_p_O_FDCE));
p_O_FDCE desc167(.Q(reg2[12:12]),.D(reg2_16[12:12]),.C(clock),.CLR(reset),.CE(un1_state_1_0_i),.E(p_desc167_p_O_FDCE));
p_O_FDCE desc168(.Q(reg2[13:13]),.D(reg2_16[13:13]),.C(clock),.CLR(reset),.CE(un1_state_1_0_i),.E(p_desc168_p_O_FDCE));
p_O_FDCE desc169(.Q(reg2[14:14]),.D(reg2_16[14:14]),.C(clock),.CLR(reset),.CE(un1_state_1_0_i),.E(p_desc169_p_O_FDCE));
p_O_FDCE desc170(.Q(reg2[15:15]),.D(reg2_16[15:15]),.C(clock),.CLR(reset),.CE(un1_state_1_0_i),.E(p_desc170_p_O_FDCE));
p_O_FDCE desc171(.Q(reg2[16:16]),.D(reg2_16[16:16]),.C(clock),.CLR(reset),.CE(un1_state_1_0_i),.E(p_desc171_p_O_FDCE));
p_O_FDCE desc172(.Q(reg2[17:17]),.D(reg2_16[17:17]),.C(clock),.CLR(reset),.CE(un1_state_1_0_i),.E(p_desc172_p_O_FDCE));
p_O_FDCE desc173(.Q(reg2[18:18]),.D(reg2_16[18:18]),.C(clock),.CLR(reset),.CE(un1_state_1_0_i),.E(p_desc173_p_O_FDCE));
p_O_FDCE desc174(.Q(reg2[19:19]),.D(reg2_16[19:19]),.C(clock),.CLR(reset),.CE(un1_state_1_0_i),.E(p_desc174_p_O_FDCE));
p_O_FDCE desc175(.Q(datao[22:22]),.D(r_4_3_1690_i_m2),.C(clock),.CLR(reset),.CE(addr_4_sqmuxa_1),.E(p_desc175_p_O_FDCE));
p_O_FDCE desc176(.Q(datao[23:23]),.D(r_4_3_0_1664_i_m2),.C(clock),.CLR(reset),.CE(addr_4_sqmuxa_1),.E(p_desc176_p_O_FDCE));
p_O_FDCE desc177(.Q(datao[24:24]),.D(r_4_3_1_1638_i_m2),.C(clock),.CLR(reset),.CE(addr_4_sqmuxa_1),.E(p_desc177_p_O_FDCE));
p_O_FDCE desc178(.Q(datao[25:25]),.D(r_4_3_2_1612_i_m2),.C(clock),.CLR(reset),.CE(addr_4_sqmuxa_1),.E(p_desc178_p_O_FDCE));
p_O_FDCE desc179(.Q(datao[26:26]),.D(r_4_3_3_1586_i_m2),.C(clock),.CLR(reset),.CE(addr_4_sqmuxa_1),.E(p_desc179_p_O_FDCE));
p_O_FDCE desc180(.Q(datao[27:27]),.D(r_4_3_4_1560_i_m2),.C(clock),.CLR(reset),.CE(addr_4_sqmuxa_1),.E(p_desc180_p_O_FDCE));
p_O_FDCE desc181(.Q(datao[28:28]),.D(r_4_3_5_1534_i_m2),.C(clock),.CLR(reset),.CE(addr_4_sqmuxa_1),.E(p_desc181_p_O_FDCE));
p_O_FDCE desc182(.Q(datao[29:29]),.D(r_4_3_6_1508_i_m2),.C(clock),.CLR(reset),.CE(addr_4_sqmuxa_1),.E(p_desc182_p_O_FDCE));
p_O_FDCE desc183(.Q(datao[30:30]),.D(r_4_3_lut6_2_O5[30:30]),.C(clock),.CLR(reset),.CE(addr_4_sqmuxa_1),.E(p_desc183_p_O_FDCE));
p_O_FDCE desc184(.Q(datao[31:31]),.D(r_4_3_8_1467),.C(clock),.CLR(reset),.CE(addr_4_sqmuxa_1),.E(p_desc184_p_O_FDCE));
p_O_FDCE desc185(.Q(reg2[0:0]),.D(reg2_16[0:0]),.C(clock),.CLR(reset),.CE(un1_state_1_0_i),.E(p_desc185_p_O_FDCE));
p_O_FDCE desc186(.Q(reg2[1:1]),.D(reg2_16[1:1]),.C(clock),.CLR(reset),.CE(un1_state_1_0_i),.E(p_desc186_p_O_FDCE));
p_O_FDCE desc187(.Q(reg2[2:2]),.D(reg2_16[2:2]),.C(clock),.CLR(reset),.CE(un1_state_1_0_i),.E(p_desc187_p_O_FDCE));
p_O_FDCE desc188(.Q(reg2[3:3]),.D(reg2_16[3:3]),.C(clock),.CLR(reset),.CE(un1_state_1_0_i),.E(p_desc188_p_O_FDCE));
p_O_FDCE desc189(.Q(reg2[4:4]),.D(reg2_16[4:4]),.C(clock),.CLR(reset),.CE(un1_state_1_0_i),.E(p_desc189_p_O_FDCE));
p_O_FDCE desc190(.Q(datao[7:7]),.D(r_4_3_9_1442_i_m2),.C(clock),.CLR(reset),.CE(addr_4_sqmuxa_1),.E(p_desc190_p_O_FDCE));
p_O_FDCE desc191(.Q(datao[8:8]),.D(r_4_3_10_1416_i_m2),.C(clock),.CLR(reset),.CE(addr_4_sqmuxa_1),.E(p_desc191_p_O_FDCE));
p_O_FDCE desc192(.Q(datao[9:9]),.D(r_4_3_11_1390_i_m2),.C(clock),.CLR(reset),.CE(addr_4_sqmuxa_1),.E(p_desc192_p_O_FDCE));
p_O_FDCE desc193(.Q(datao[10:10]),.D(r_4_3_12_1364_i_m2),.C(clock),.CLR(reset),.CE(addr_4_sqmuxa_1),.E(p_desc193_p_O_FDCE));
p_O_FDCE desc194(.Q(datao[11:11]),.D(r_4_3_13_1338_i_m2),.C(clock),.CLR(reset),.CE(addr_4_sqmuxa_1),.E(p_desc194_p_O_FDCE));
p_O_FDCE desc195(.Q(datao[12:12]),.D(r_4_3_14_1312_i_m2),.C(clock),.CLR(reset),.CE(addr_4_sqmuxa_1),.E(p_desc195_p_O_FDCE));
p_O_FDCE desc196(.Q(datao[13:13]),.D(r_4_3_15_1286_i_m2),.C(clock),.CLR(reset),.CE(addr_4_sqmuxa_1),.E(p_desc196_p_O_FDCE));
p_O_FDCE desc197(.Q(datao[14:14]),.D(r_4_3_16_1260_i_m2),.C(clock),.CLR(reset),.CE(addr_4_sqmuxa_1),.E(p_desc197_p_O_FDCE));
p_O_FDCE desc198(.Q(datao[15:15]),.D(r_4_3_17_1234_i_m2),.C(clock),.CLR(reset),.CE(addr_4_sqmuxa_1),.E(p_desc198_p_O_FDCE));
p_O_FDCE desc199(.Q(datao[16:16]),.D(r_4_3_18_1208_i_m2),.C(clock),.CLR(reset),.CE(addr_4_sqmuxa_1),.E(p_desc199_p_O_FDCE));
p_O_FDCE desc200(.Q(datao[17:17]),.D(r_4_3_19_1182_i_m2),.C(clock),.CLR(reset),.CE(addr_4_sqmuxa_1),.E(p_desc200_p_O_FDCE));
p_O_FDCE desc201(.Q(datao[18:18]),.D(r_4_3_20_1156_i_m2),.C(clock),.CLR(reset),.CE(addr_4_sqmuxa_1),.E(p_desc201_p_O_FDCE));
p_O_FDCE desc202(.Q(datao[19:19]),.D(N_2724),.C(clock),.CLR(reset),.CE(addr_4_sqmuxa_1),.E(p_desc202_p_O_FDCE));
p_O_FDCE desc203(.Q(datao[20:20]),.D(r_4_3_22_1104_i_m2),.C(clock),.CLR(reset),.CE(addr_4_sqmuxa_1),.E(p_desc203_p_O_FDCE));
p_O_FDCE desc204(.Q(datao[21:21]),.D(r_4_3_23_1078_i_m2),.C(clock),.CLR(reset),.CE(addr_4_sqmuxa_1),.E(p_desc204_p_O_FDCE));
p_O_FDCE desc205(.Q(addr[12:12]),.D(N_2656_i),.C(clock),.CLR(reset),.CE(addr_0_sqmuxa_1_i),.E(p_desc205_p_O_FDCE));
p_O_FDCE desc206(.Q(addr[13:13]),.D(N_2636_i),.C(clock),.CLR(reset),.CE(addr_0_sqmuxa_1_i),.E(p_desc206_p_O_FDCE));
p_O_FDCE desc207(.Q(addr[14:14]),.D(N_2616_i),.C(clock),.CLR(reset),.CE(addr_0_sqmuxa_1_i),.E(p_desc207_p_O_FDCE));
p_O_FDCE desc208(.Q(addr[15:15]),.D(N_2596_i),.C(clock),.CLR(reset),.CE(addr_0_sqmuxa_1_i),.E(p_desc208_p_O_FDCE));
p_O_FDCE desc209(.Q(addr[16:16]),.D(N_2576_i),.C(clock),.CLR(reset),.CE(addr_0_sqmuxa_1_i),.E(p_desc209_p_O_FDCE));
p_O_FDCE desc210(.Q(addr[17:17]),.D(N_2556_i),.C(clock),.CLR(reset),.CE(addr_0_sqmuxa_1_i),.E(p_desc210_p_O_FDCE));
p_O_FDCE desc211(.Q(addr[18:18]),.D(N_2536_i),.C(clock),.CLR(reset),.CE(addr_0_sqmuxa_1_i),.E(p_desc211_p_O_FDCE));
p_O_FDCE desc212(.Q(addr[19:19]),.D(N_2516_i),.C(clock),.CLR(reset),.CE(addr_0_sqmuxa_1_i),.E(p_desc212_p_O_FDCE));
p_O_FDCE desc213(.Q(datao[0:0]),.D(r_4_3_24_836_i_m2),.C(clock),.CLR(reset),.CE(addr_4_sqmuxa_1),.E(p_desc213_p_O_FDCE));
p_O_FDCE desc214(.Q(datao[1:1]),.D(r_4_3_25_810_i_m2),.C(clock),.CLR(reset),.CE(addr_4_sqmuxa_1),.E(p_desc214_p_O_FDCE));
p_O_FDCE desc215(.Q(datao[2:2]),.D(N_36_i),.C(clock),.CLR(reset),.CE(addr_4_sqmuxa_1),.E(p_desc215_p_O_FDCE));
p_O_FDCE desc216(.Q(datao[3:3]),.D(r_4_3_27_758_i_m2),.C(clock),.CLR(reset),.CE(addr_4_sqmuxa_1),.E(p_desc216_p_O_FDCE));
p_O_FDCE desc217(.Q(datao[4:4]),.D(r_4_3_28_732_i_m2),.C(clock),.CLR(reset),.CE(addr_4_sqmuxa_1),.E(p_desc217_p_O_FDCE));
p_O_FDCE desc218(.Q(datao[5:5]),.D(r_4_3_29_706_i_m2),.C(clock),.CLR(reset),.CE(addr_4_sqmuxa_1),.E(p_desc218_p_O_FDCE));
p_O_FDCE desc219(.Q(datao[6:6]),.D(r_4_3_30_680_i_m2),.C(clock),.CLR(reset),.CE(addr_4_sqmuxa_1),.E(p_desc219_p_O_FDCE));
p_O_FDCE desc220(.Q(reg3[26:26]),.D(reg3_17[26:26]),.C(clock),.CLR(reset),.CE(state),.E(p_desc220_p_O_FDCE));
p_O_FDCE desc221(.Q(reg3[27:27]),.D(reg3_17[27:27]),.C(clock),.CLR(reset),.CE(state),.E(p_desc221_p_O_FDCE));
p_O_FDCE desc222(.Q(reg3[28:28]),.D(reg3_17[28:28]),.C(clock),.CLR(reset),.CE(state),.E(p_desc222_p_O_FDCE));
p_O_FDCE desc223(.Q(addr[0:0]),.D(N_2335_i),.C(clock),.CLR(reset),.CE(addr_0_sqmuxa_1_i),.E(p_desc223_p_O_FDCE));
p_O_FDCE desc224(.Q(addr[1:1]),.D(N_2315_i),.C(clock),.CLR(reset),.CE(addr_0_sqmuxa_1_i),.E(p_desc224_p_O_FDCE));
p_O_FDCE desc225(.Q(addr[2:2]),.D(N_47_i),.C(clock),.CLR(reset),.CE(addr_0_sqmuxa_1_i),.E(p_desc225_p_O_FDCE));
p_O_FDCE desc226(.Q(addr[3:3]),.D(N_2267_i),.C(clock),.CLR(reset),.CE(addr_0_sqmuxa_1_i),.E(p_desc226_p_O_FDCE));
p_O_FDCE desc227(.Q(addr[4:4]),.D(N_56_i),.C(clock),.CLR(reset),.CE(addr_0_sqmuxa_1_i),.E(p_desc227_p_O_FDCE));
p_O_FDCE desc228(.Q(addr[5:5]),.D(N_2219_i),.C(clock),.CLR(reset),.CE(addr_0_sqmuxa_1_i),.E(p_desc228_p_O_FDCE));
p_O_FDCE desc229(.Q(addr[6:6]),.D(N_2199_i),.C(clock),.CLR(reset),.CE(addr_0_sqmuxa_1_i),.E(p_desc229_p_O_FDCE));
p_O_FDCE desc230(.Q(addr[7:7]),.D(N_2179_i),.C(clock),.CLR(reset),.CE(addr_0_sqmuxa_1_i),.E(p_desc230_p_O_FDCE));
p_O_FDCE desc231(.Q(addr[8:8]),.D(N_2159_i),.C(clock),.CLR(reset),.CE(addr_0_sqmuxa_1_i),.E(p_desc231_p_O_FDCE));
p_O_FDCE desc232(.Q(addr[9:9]),.D(N_2139_i),.C(clock),.CLR(reset),.CE(addr_0_sqmuxa_1_i),.E(p_desc232_p_O_FDCE));
p_O_FDCE desc233(.Q(addr[10:10]),.D(N_2119_i),.C(clock),.CLR(reset),.CE(addr_0_sqmuxa_1_i),.E(p_desc233_p_O_FDCE));
p_O_FDCE desc234(.Q(addr[11:11]),.D(N_2099_i),.C(clock),.CLR(reset),.CE(addr_0_sqmuxa_1_i),.E(p_desc234_p_O_FDCE));
p_O_FDCE desc235(.Q(reg3[11:11]),.D(reg3_17[11:11]),.C(clock),.CLR(reset),.CE(state),.E(p_desc235_p_O_FDCE));
p_O_FDCE desc236(.Q(reg3[12:12]),.D(reg3_17[12:12]),.C(clock),.CLR(reset),.CE(state),.E(p_desc236_p_O_FDCE));
p_O_FDCE desc237(.Q(reg3[13:13]),.D(reg3_17[13:13]),.C(clock),.CLR(reset),.CE(state),.E(p_desc237_p_O_FDCE));
p_O_FDCE desc238(.Q(reg3[14:14]),.D(reg3_17[14:14]),.C(clock),.CLR(reset),.CE(state),.E(p_desc238_p_O_FDCE));
p_O_FDCE desc239(.Q(reg3[15:15]),.D(reg3_17[15:15]),.C(clock),.CLR(reset),.CE(state),.E(p_desc239_p_O_FDCE));
p_O_FDCE desc240(.Q(reg3[16:16]),.D(reg3_17[16:16]),.C(clock),.CLR(reset),.CE(state),.E(p_desc240_p_O_FDCE));
p_O_FDCE desc241(.Q(reg3[17:17]),.D(reg3_17[17:17]),.C(clock),.CLR(reset),.CE(state),.E(p_desc241_p_O_FDCE));
p_O_FDCE desc242(.Q(reg3[18:18]),.D(reg3_17[18:18]),.C(clock),.CLR(reset),.CE(state),.E(p_desc242_p_O_FDCE));
p_O_FDCE desc243(.Q(reg3[19:19]),.D(reg3_17[19:19]),.C(clock),.CLR(reset),.CE(state),.E(p_desc243_p_O_FDCE));
p_O_FDCE desc244(.Q(reg3[20:20]),.D(reg3_17[20:20]),.C(clock),.CLR(reset),.CE(state),.E(p_desc244_p_O_FDCE));
p_O_FDCE desc245(.Q(reg3[21:21]),.D(reg3_17[21:21]),.C(clock),.CLR(reset),.CE(state),.E(p_desc245_p_O_FDCE));
p_O_FDCE desc246(.Q(reg3[22:22]),.D(reg3_17[22:22]),.C(clock),.CLR(reset),.CE(state),.E(p_desc246_p_O_FDCE));
p_O_FDCE desc247(.Q(reg3[23:23]),.D(reg3_17[23:23]),.C(clock),.CLR(reset),.CE(state),.E(p_desc247_p_O_FDCE));
p_O_FDCE desc248(.Q(reg3[24:24]),.D(reg3_17[24:24]),.C(clock),.CLR(reset),.CE(state),.E(p_desc248_p_O_FDCE));
p_O_FDCE desc249(.Q(reg3[25:25]),.D(reg3_17[25:25]),.C(clock),.CLR(reset),.CE(state),.E(p_desc249_p_O_FDCE));
p_O_FDCE desc250(.Q(reg3[0:0]),.D(reg3_17[0:0]),.C(clock),.CLR(reset),.CE(state),.E(p_desc250_p_O_FDCE));
p_O_FDCE desc251(.Q(reg3[1:1]),.D(reg3_17[1:1]),.C(clock),.CLR(reset),.CE(state),.E(p_desc251_p_O_FDCE));
p_O_FDCE desc252(.Q(reg3[2:2]),.D(reg3_17[2:2]),.C(clock),.CLR(reset),.CE(state),.E(p_desc252_p_O_FDCE));
p_O_FDCE desc253(.Q(reg3[3:3]),.D(\d_cnst_sn.reg3_N_7_i ),.C(clock),.CLR(reset),.CE(state),.E(p_desc253_p_O_FDCE));
p_O_FDCE desc254(.Q(reg3[4:4]),.D(reg3_17[4:4]),.C(clock),.CLR(reset),.CE(state),.E(p_desc254_p_O_FDCE));
p_O_FDCE desc255(.Q(reg3[5:5]),.D(reg3_17[5:5]),.C(clock),.CLR(reset),.CE(state),.E(p_desc255_p_O_FDCE));
p_O_FDCE desc256(.Q(reg3[6:6]),.D(reg3_17[6:6]),.C(clock),.CLR(reset),.CE(state),.E(p_desc256_p_O_FDCE));
p_O_FDCE desc257(.Q(reg3[7:7]),.D(reg3_17[7:7]),.C(clock),.CLR(reset),.CE(state),.E(p_desc257_p_O_FDCE));
p_O_FDCE desc258(.Q(reg3[8:8]),.D(reg3_17[8:8]),.C(clock),.CLR(reset),.CE(state),.E(p_desc258_p_O_FDCE));
p_O_FDCE desc259(.Q(reg3[9:9]),.D(reg3_17[9:9]),.C(clock),.CLR(reset),.CE(state),.E(p_desc259_p_O_FDCE));
p_O_FDCE desc260(.Q(reg3[10:10]),.D(reg3_17[10:10]),.C(clock),.CLR(reset),.CE(state),.E(p_desc260_p_O_FDCE));
p_O_FDC rd_Z(.Q(rd),.D(rd_18),.C(clock),.CLR(reset),.E(p_rd_Z_p_O_FDC));
p_O_FDC desc261(.Q(state),.D(state_i),.C(clock),.CLR(reset),.E(p_desc261_p_O_FDC));
p_O_FDC wr_Z(.Q(wr),.D(addr_4_sqmuxa_1),.C(clock),.CLR(reset),.E(p_wr_Z_p_O_FDC));
p_O_FDC desc262(.Q(ir_fast[31:31]),.D(ir_3_fast[31:31]),.C(clock),.CLR(reset),.E(p_desc262_p_O_FDC));
MUXCY_L inf_abs0_2_cry_29_outext(.DI(GND),.CI(inf_abs0_2_cry_29_0),.S(inf_abs0_2_cry_29_1),.LO(inf_abs0_2_cry_29));
MUXCY un3_reg3_cry_25_outext(.DI(GND),.CI(un3_reg3_cry_25_0),.S(un3_reg3_cry_25_1),.O(un3_reg3_cry_25));
MUXCY inf_abs0_2_cry_30_outext(.DI(GND),.CI(inf_abs0_2_0[31:31]),.S(inf_abs0_2_1[31:31]),.O(inf_abs0_2[31:31]));
MUXCY un14_r_0_I_83_cZ(.DI(GND),.CI(un14_r_0_data_tmp[9:9]),.S(un14_r_0_N_2),.O(un14_r_0_I_83));
MUXCY desc263(.DI(un11_r_lt30),.CI(un11_r_cry[28:28]),.S(un11_r_df30),.O(un11_r_cry[30:30]));
MUXCY desc264(.DI(b18_lt30),.CI(b18_cry[28:28]),.S(b18_df30),.O(b18));
MUXCY desc265(.DI(un26_r_lt30),.CI(un26_r_cry[28:28]),.S(un26_r_df30),.O(un26_r_cry[30:30]));
MUXCY inf_abs0_2_cry_29_cZ(.DI(GND),.CI(inf_abs0_2_cry_28),.S(inf_abs0_2_axb_29),.O(inf_abs0_2_cry_29_0));
LUT5 desc266(.I0(d[0:0]),.I1(d[1:1]),.I2(d_cnst_ss0_x),.I3(un1_df_1),.I4(d_cnst_sm0),.O(un87_df));
defparam desc266.INIT=32'h88F08800;
LUT4_L desc267(.I0(\d_cnst_sn.g0_0_2 ),.I1(\d_cnst_sn.reg0_m9_i_a3_0 ),.I2(t_1[29:29]),.I3(\d_cnst_sn.g0_rn_1 ),.LO(reg0_28_10_2261_a6_3_2_lut6_2_RNIOK9O5));
defparam desc267.INIT=16'hFF02;
LUT6 desc268(.I0(inf_abs0_2[23:23]),.I1(un36_df),.I2(N_1890),.I3(m7),.I4(un1_cf_x),.I5(un87_df),.O(\d_cnst_sn.reg3_17_sn_m7_0 ));
defparam desc268.INIT=64'h0000FFFEFFFEFFFE;
LUT4 desc269(.I0(inf_abs0_2[23:23]),.I1(inf_abs0_2[20:20]),.I2(inf_abs0_2[21:21]),.I3(\d_cnst_sn.reg3_5_sqmuxa_2_1 ),.O(un1_cf_x));
defparam desc269.INIT=16'h0400;
LUT3 desc270(.I0(inf_abs0_2[24:24]),.I1(inf_abs0_2[25:25]),.I2(inf_abs0_2[26:26]),.O(d_cnst_ss0_x));
defparam desc270.INIT=8'hBA;
LUT6_L desc271(.I0(\d_cnst_sn.b64_0 ),.I1(\d_cnst_sn.b60_0 ),.I2(\d_cnst_sn.reg1_16_a0_1 [3:3]),.I3(\d_cnst_sn.reg0_1 [7:7]),.I4(t_1[7:7]),.I5(N_1042),.LO(reg0_28_7_rep1));
defparam desc271.INIT=64'h0F00FF0001001100;
LUT6 desc272(.I0(datai[0:0]),.I1(inf_abs0_2_axb_30),.I2(inf_abs0_2[0:0]),.I3(inf_abs0_2_cry_29),.I4(inf_abs0_2[27:27]),.I5(inf_abs0_2[28:28]),.O(m_2_i[0:0]));
defparam desc272.INIT=64'h1D551D551D550F0F;
LUT5_L desc273(.I0(\d_cnst_sn.reg0_m9_i_a3_0 ),.I1(N_1033),.I2(\d_cnst_sn.g0_1 ),.I3(un32_reg0_s_29),.I4(un11_reg0_s_29),.LO(\d_cnst_sn.g0_rn_1 ));
defparam desc273.INIT=32'hFAF8F2F0;
LUT6 desc274(.I0(b),.I1(inf_abs0_2_axb_30),.I2(inf_abs0_2_cry_29),.I3(inf_abs0_2[24:24]),.I4(inf_abs0_2[25:25]),.I5(inf_abs0_2[26:26]),.O(un1_df_1));
defparam desc274.INIT=64'h2A3F2A1500000000;
LUT5_L desc275(.I0(\d_cnst_sn.g0_0_2 ),.I1(\d_cnst_sn.reg0_m9_i_a3_0 ),.I2(\d_cnst_sn.g0_1 ),.I3(t_1[29:29]),.I4(\d_cnst_sn.g3 ),.LO(N_3569_rep1));
defparam desc275.INIT=32'hFCFEF0F2;
LUT6_L desc276(.I0(\d_cnst_sn.reg0_28_2526_a5_1_0 ),.I1(\d_cnst_sn.reg1_16_8_1837_2_tz ),.I2(\d_cnst_sn.reg0_28_7_a0_0 [9:9]),.I3(\d_cnst_sn.reg0_28_0 [19:19]),.I4(t_1[19:19]),.I5(\d_cnst_sn.reg0_28_3_2492_1 ),.LO(N_3829_rep1));
defparam desc276.INIT=64'hFFFFFFFF0E00EE00;
LUT6_L desc277(.I0(\d_cnst_sn.reg0_28_2526_a5_1_0 ),.I1(\d_cnst_sn.reg1_16_8_1837_2_tz ),.I2(\d_cnst_sn.reg0_28_7_a0_0 [9:9]),.I3(\d_cnst_sn.reg0_28_0 [20:20]),.I4(t_1[20:20]),.I5(\d_cnst_sn.reg0_28_4_2459_0 ),.LO(N_3803_rep1));
defparam desc277.INIT=64'hFFFFFFFF0E00EE00;
LUT5_L desc278(.I0(\d_cnst_sn.reg0_28_7_a0_0 [9:9]),.I1(\d_cnst_sn.reg0_28_5_2426_3_1 ),.I2(\d_cnst_sn.reg0_28_5_2426_a6_1_1 ),.I3(t_1[21:21]),.I4(\d_cnst_sn.reg0_28_5_2426_0 ),.LO(N_3777_rep1));
defparam desc278.INIT=32'hFFFF54FC;
LUT5_L desc279(.I0(\d_cnst_sn.reg0_28_7_a0_0 [9:9]),.I1(\d_cnst_sn.reg0_28_6_2393_3_1 ),.I2(\d_cnst_sn.reg0_28_6_2393_a6_1_1 ),.I3(t_1[22:22]),.I4(\d_cnst_sn.reg0_28_6_2393_0 ),.LO(N_3751_rep1));
defparam desc279.INIT=32'hFFFF54FC;
LUT5_L desc280(.I0(\d_cnst_sn.reg0_28_7_a0_0 [9:9]),.I1(\d_cnst_sn.reg0_28_7_2360_3_1 ),.I2(\d_cnst_sn.reg0_28_7_2360_a6_1_1 ),.I3(t_1[23:23]),.I4(\d_cnst_sn.reg0_28_7_2360_0 ),.LO(N_3725_rep1));
defparam desc280.INIT=32'hFFFF54FC;
LUT6_L desc281(.I0(\d_cnst_sn.reg1_16_8_1837_2_tz ),.I1(\d_cnst_sn.reg0_28_7_a0_0 [9:9]),.I2(reg0_28_7_d[24:24]),.I3(\d_cnst_sn.reg0_28_8_2327_a6_1_1 ),.I4(t_1[24:24]),.I5(\d_cnst_sn.reg0_28_8_2327_0 ),.LO(N_3699_rep1));
defparam desc281.INIT=64'hFFFFFFFF3320FFA8;
LUT5_L desc282(.I0(\d_cnst_sn.reg0_28_7_a0_0 [9:9]),.I1(\d_cnst_sn.reg0_28_9_2294_3_1 ),.I2(\d_cnst_sn.reg0_28_9_2294_a6_1_1 ),.I3(t_1[25:25]),.I4(\d_cnst_sn.reg0_28_9_2294_0 ),.LO(N_3673_rep1));
defparam desc282.INIT=32'hFFFF54FC;
LUT5_L desc283(.I0(\d_cnst_sn.reg0_28_7_a0_0 [9:9]),.I1(\d_cnst_sn.reg0_28_10_2261_a6_1_1 ),.I2(\d_cnst_sn.reg1_16_7_1870_3_1 ),.I3(t_1[26:26]),.I4(\d_cnst_sn.reg1_16_7_1870_0 ),.LO(N_3341_rep1));
defparam desc283.INIT=32'hFFFF54FC;
LUT5_L desc284(.I0(inf_abs0_2[31:31]),.I1(\d_cnst_sn.reg0_28_14_2135_1_a0_2 ),.I2(reg3_1_1[30:30]),.I3(\d_cnst_sn.reg0_28_14_0 ),.I4(t_1[30:30]),.LO(N_3550_rep1));
defparam desc284.INIT=32'hFFA0FFEC;
LUT5_L desc285(.I0(\d_cnst_sn.reg0_28_7_a0_0 [9:9]),.I1(\d_cnst_sn.reg0_28_11_2228_a6_1_1 ),.I2(\d_cnst_sn.reg1_16_8_1837_3_1 ),.I3(t_1[27:27]),.I4(\d_cnst_sn.reg1_16_8_1837_0 ),.LO(N_3315_rep1));
defparam desc285.INIT=32'hFFFF54FC;
LUT6_L desc286(.I0(\d_cnst_sn.reg0_28_9_2294_a6_3_0 ),.I1(m_2[28:28]),.I2(\d_cnst_sn.reg0_28_7_a0_0 [9:9]),.I3(\d_cnst_sn.reg1_16_9_1804_3_tz ),.I4(t_1[28:28]),.I5(N_3614),.LO(N_3289_rep1));
defparam desc286.INIT=64'hFFFFFFFF8F88FF88;
LUT6_L desc287(.I0(b),.I1(inf_abs0_2[27:27]),.I2(\d_cnst_sn.g0_3_a2_2 ),.I3(\d_cnst_sn.g0_3_1 ),.I4(t_1[31:31]),.I5(t_1[30:30]),.LO(N_3856_rep1));
defparam desc287.INIT=64'hFF00FF30FF40FF70;
LUT6 desc288(.I0(inf_abs0_2[21:21]),.I1(inf_abs0_2[22:22]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[27:27]),.I4(inf_abs0_2[28:28]),.I5(\d_cnst_sn.g0_0_0_a5_0_0 ),.O(N_7_0));
defparam desc288.INIT=64'h0101010000000000;
LUT6 desc289(.I0(inf_abs0_2[19:19]),.I1(inf_abs0_2[20:20]),.I2(inf_abs0_2[31:31]),.I3(N_7_0),.I4(\d_cnst_sn.reg1_16_a2_0 [5:5]),.I5(reg3_1_1[31:31]),.O(\d_cnst_sn.g0_0_0_1 ));
defparam desc289.INIT=64'hFFF1FF00FF00FF00;
LUT6_L desc290(.I0(b),.I1(inf_abs0_2[27:27]),.I2(\d_cnst_sn.g0_0_0_a5_2 ),.I3(\d_cnst_sn.g0_0_0_1 ),.I4(t_1[31:31]),.I5(t_1[30:30]),.LO(reg2_16[31:31]));
defparam desc290.INIT=64'hFF00FF30FF40FF70;
LUT3_L desc291(.I0(N_1033),.I1(un32_reg0_s_29),.I2(un11_reg0_s_29),.LO(\d_cnst_sn.g3 ));
defparam desc291.INIT=8'hE4;
LUT5 desc292(.I0(b),.I1(inf_abs0_2[21:21]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[27:27]),.I4(inf_abs0_2[28:28]),.O(\d_cnst_sn.g0_0_2 ));
defparam desc292.INIT=32'h0000040C;
LUT6 desc293(.I0(\d_cnst_sn.reg0_N_13_0 ),.I1(\d_cnst_sn.reg0_28_9_2294_a6_3_0 ),.I2(N_513_i),.I3(m_2[29:29]),.I4(reg0_m9_i_a1),.I5(reg3_1_1[29:29]),.O(\d_cnst_sn.g0_1 ));
defparam desc293.INIT=64'hFFFFCD05FFFFCC00;
LUT6 desc294(.I0(datai[31:31]),.I1(inf_abs0_2[20:20]),.I2(inf_abs0_2[21:21]),.I3(inf_abs0_2[22:22]),.I4(inf_abs0_2[31:31]),.I5(N_7),.O(N_12));
defparam desc294.INIT=64'h0000000800000000;
LUT6 desc295(.I0(inf_abs0_2[20:20]),.I1(inf_abs0_2[21:21]),.I2(inf_abs0_2[22:22]),.I3(inf_abs0_2[31:31]),.I4(N_12),.I5(reg3_1_1[31:31]),.O(\d_cnst_sn.g0_3_1 ));
defparam desc295.INIT=64'hFFFFFF01FFFF0000;
LUT6_L desc296(.I0(b),.I1(inf_abs0_2[27:27]),.I2(\d_cnst_sn.g0_3_a2_2 ),.I3(\d_cnst_sn.g0_3_1 ),.I4(t_1[31:31]),.I5(t_1[30:30]),.LO(N_3856));
defparam desc296.INIT=64'hFF00FF30FF40FF70;
LUT4 desc297(.I0(datai[28:28]),.I1(inf_abs0_2[27:27]),.I2(inf_abs0_2[28:28]),.I3(un1_cf),.O(N_1685));
defparam desc297.INIT=16'hA8AA;
LUT4 desc298(.I0(datai[27:27]),.I1(inf_abs0_2[27:27]),.I2(inf_abs0_2[28:28]),.I3(un1_cf),.O(N_1684));
defparam desc298.INIT=16'hA8AA;
LUT4 desc299(.I0(datai[26:26]),.I1(inf_abs0_2[27:27]),.I2(inf_abs0_2[28:28]),.I3(un1_cf),.O(N_1683));
defparam desc299.INIT=16'hA8AA;
LUT4 desc300(.I0(datai[25:25]),.I1(inf_abs0_2[27:27]),.I2(inf_abs0_2[28:28]),.I3(un1_cf),.O(N_1682));
defparam desc300.INIT=16'hA8AA;
LUT4_L desc301(.I0(datai[24:24]),.I1(inf_abs0_2[27:27]),.I2(inf_abs0_2[28:28]),.I3(un1_cf),.LO(N_1681));
defparam desc301.INIT=16'hA8AA;
LUT4_L desc302(.I0(datai[23:23]),.I1(inf_abs0_2[27:27]),.I2(inf_abs0_2[28:28]),.I3(un1_cf),.LO(N_1680));
defparam desc302.INIT=16'hA8AA;
LUT4_L desc303(.I0(datai[22:22]),.I1(inf_abs0_2[27:27]),.I2(inf_abs0_2[28:28]),.I3(un1_cf),.LO(N_1679));
defparam desc303.INIT=16'hA8AA;
LUT4 desc304(.I0(datai[20:20]),.I1(inf_abs0_2[27:27]),.I2(inf_abs0_2[28:28]),.I3(un1_cf),.O(N_1677));
defparam desc304.INIT=16'hA8AA;
LUT5 desc305(.I0(datai[7:7]),.I1(inf_abs0_2[7:7]),.I2(inf_abs0_2[27:27]),.I3(inf_abs0_2[28:28]),.I4(un1_cf),.O(N_1664));
defparam desc305.INIT=32'hAAACAAAA;
LUT5 desc306(.I0(datai[6:6]),.I1(inf_abs0_2[6:6]),.I2(inf_abs0_2[27:27]),.I3(inf_abs0_2[28:28]),.I4(un1_cf),.O(N_1663));
defparam desc306.INIT=32'hAAACAAAA;
LUT5_L desc307(.I0(datai[2:2]),.I1(inf_abs0_2[2:2]),.I2(inf_abs0_2[27:27]),.I3(inf_abs0_2[28:28]),.I4(un1_cf),.LO(N_1659));
defparam desc307.INIT=32'hAAACAAAA;
LUT5 desc308(.I0(datai[9:9]),.I1(inf_abs0_2[9:9]),.I2(inf_abs0_2[27:27]),.I3(inf_abs0_2[28:28]),.I4(un1_cf),.O(N_1666));
defparam desc308.INIT=32'hAAACAAAA;
LUT5 desc309(.I0(datai[11:11]),.I1(inf_abs0_2[11:11]),.I2(inf_abs0_2[27:27]),.I3(inf_abs0_2[28:28]),.I4(un1_cf),.O(N_1668));
defparam desc309.INIT=32'hAAACAAAA;
LUT5 desc310(.I0(datai[10:10]),.I1(inf_abs0_2[10:10]),.I2(inf_abs0_2[27:27]),.I3(inf_abs0_2[28:28]),.I4(un1_cf),.O(N_1667));
defparam desc310.INIT=32'hAAACAAAA;
LUT5 desc311(.I0(datai[17:17]),.I1(inf_abs0_2[17:17]),.I2(inf_abs0_2[27:27]),.I3(inf_abs0_2[28:28]),.I4(un1_cf),.O(N_1674));
defparam desc311.INIT=32'hAAACAAAA;
LUT5 desc312(.I0(datai[12:12]),.I1(inf_abs0_2[12:12]),.I2(inf_abs0_2[27:27]),.I3(inf_abs0_2[28:28]),.I4(un1_cf),.O(N_1669));
defparam desc312.INIT=32'hAAACAAAA;
LUT5 desc313(.I0(datai[18:18]),.I1(inf_abs0_2[18:18]),.I2(inf_abs0_2[27:27]),.I3(inf_abs0_2[28:28]),.I4(un1_cf),.O(N_1675));
defparam desc313.INIT=32'hAAACAAAA;
LUT5 desc314(.I0(datai[14:14]),.I1(inf_abs0_2[14:14]),.I2(inf_abs0_2[27:27]),.I3(inf_abs0_2[28:28]),.I4(un1_cf),.O(N_1671));
defparam desc314.INIT=32'hAAACAAAA;
LUT5 desc315(.I0(datai[19:19]),.I1(inf_abs0_2[19:19]),.I2(inf_abs0_2[27:27]),.I3(inf_abs0_2[28:28]),.I4(un1_cf),.O(N_1676));
defparam desc315.INIT=32'hAAACAAAA;
LUT5 desc316(.I0(datai[13:13]),.I1(inf_abs0_2[13:13]),.I2(inf_abs0_2[27:27]),.I3(inf_abs0_2[28:28]),.I4(un1_cf),.O(N_1670));
defparam desc316.INIT=32'hAAACAAAA;
LUT5_L desc317(.I0(datai[1:1]),.I1(inf_abs0_2[1:1]),.I2(inf_abs0_2[27:27]),.I3(inf_abs0_2[28:28]),.I4(un1_cf),.LO(N_1658));
defparam desc317.INIT=32'hAAACAAAA;
LUT5 desc318(.I0(datai[16:16]),.I1(inf_abs0_2[16:16]),.I2(inf_abs0_2[27:27]),.I3(inf_abs0_2[28:28]),.I4(un1_cf),.O(N_1673));
defparam desc318.INIT=32'hAAACAAAA;
LUT5 desc319(.I0(datai[15:15]),.I1(inf_abs0_2[15:15]),.I2(inf_abs0_2[27:27]),.I3(inf_abs0_2[28:28]),.I4(un1_cf),.O(N_1672));
defparam desc319.INIT=32'hAAACAAAA;
LUT5 desc320(.I0(datai[8:8]),.I1(inf_abs0_2[8:8]),.I2(inf_abs0_2[27:27]),.I3(inf_abs0_2[28:28]),.I4(un1_cf),.O(N_1665));
defparam desc320.INIT=32'hAAACAAAA;
LUT5 desc321(.I0(inf_abs0_2[23:23]),.I1(inf_abs0_2[20:20]),.I2(inf_abs0_2[21:21]),.I3(\d_cnst_sn.reg3_5_sqmuxa_2_1 ),.I4(un87_df),.O(un1_cf));
defparam desc321.INIT=32'h04000000;
LUT5 desc322(.I0(inf_abs0_2[23:23]),.I1(inf_abs0_2[27:27]),.I2(inf_abs0_2[28:28]),.I3(un36_df),.I4(N_1890),.O(rd_4_sqmuxa));
defparam desc322.INIT=32'h00000001;
LUT5 desc323(.I0(inf_abs0_2[23:23]),.I1(un1_b57),.I2(un1_df_17_2),.I3(un1_df_16),.I4(\d_cnst_sn.reg3_17_sn_m7_0 ),.O(N_1841));
defparam desc323.INIT=32'h00BF0000;
LUT4 desc324(.I0(inf_abs0_2[23:23]),.I1(un36_df),.I2(un1_b59),.I3(un87_df),.O(un1_df_16));
defparam desc324.INIT=16'h1000;
LUT5 desc325(.I0(inf_abs0_2[23:23]),.I1(un1_b57),.I2(un36_df),.I3(un1_b59),.I4(un87_df),.O(N_1810));
defparam desc325.INIT=32'hFAFBFFFF;
LUT5_L desc326(.I0(inf_abs0_2[28:28]),.I1(inf_abs0_2[29:29]),.I2(N_933),.I3(N_965),.I4(reg3_14_sqmuxa),.LO(\d_cnst_sn.reg3_17_6_0 [19:19]));
defparam desc326.INIT=32'hFD75FFFF;
LUT3_L desc327(.I0(inf_abs0_2[28:28]),.I1(reg3_14_sqmuxa),.I2(t_1[13:13]),.LO(reg3_17_4_a2[13:13]));
defparam desc327.INIT=8'h40;
LUT5 desc328(.I0(inf_abs0_2[2:2]),.I1(inf_abs0_2[28:28]),.I2(r_4[1:1]),.I3(reg3_14_sqmuxa),.I4(t_1[2:2]),.O(N_1752));
defparam desc328.INIT=32'hC0AAF3AA;
LUT5 desc329(.I0(inf_abs0_2[1:1]),.I1(inf_abs0_2[28:28]),.I2(r_4[0:0]),.I3(reg3_14_sqmuxa),.I4(t_1[1:1]),.O(N_1751));
defparam desc329.INIT=32'hC0AAF3AA;
LUT4_L desc330(.I0(inf_abs0_2[0:0]),.I1(inf_abs0_2[28:28]),.I2(reg3_14_sqmuxa),.I3(t_1[0:0]),.LO(N_1750));
defparam desc330.INIT=16'h0A3A;
LUT5 desc331(.I0(inf_abs0_2[28:28]),.I1(r_4[23:23]),.I2(\d_cnst_sn.reg3_17_sn_m7_0 ),.I3(reg3_14_sqmuxa),.I4(N_1681),.O(\d_cnst_sn.reg3_17_0_tz [24:24]));
defparam desc331.INIT=32'h8F0F8000;
LUT5 desc332(.I0(inf_abs0_2[28:28]),.I1(r_4[21:21]),.I2(\d_cnst_sn.reg3_17_sn_m7_0 ),.I3(reg3_14_sqmuxa),.I4(N_1679),.O(\d_cnst_sn.reg3_17_0_tz [22:22]));
defparam desc332.INIT=32'h8F0F8000;
LUT5 desc333(.I0(inf_abs0_2[28:28]),.I1(r_4[22:22]),.I2(\d_cnst_sn.reg3_17_sn_m7_0 ),.I3(reg3_14_sqmuxa),.I4(N_1680),.O(\d_cnst_sn.reg3_17_0_tz [23:23]));
defparam desc333.INIT=32'h8F0F8000;
LUT5_L desc334(.I0(inf_abs0_2[17:17]),.I1(inf_abs0_2[28:28]),.I2(r_4[16:16]),.I3(rd_4_sqmuxa),.I4(reg3_14_sqmuxa),.LO(\d_cnst_sn.reg3_17_6_0 [17:17]));
defparam desc334.INIT=32'hF3F3AAFF;
LUT5_L desc335(.I0(inf_abs0_2[16:16]),.I1(inf_abs0_2[28:28]),.I2(r_4[15:15]),.I3(rd_4_sqmuxa),.I4(reg3_14_sqmuxa),.LO(\d_cnst_sn.reg3_17_6_0 [16:16]));
defparam desc335.INIT=32'hF3F3AAFF;
LUT5_L desc336(.I0(inf_abs0_2[14:14]),.I1(inf_abs0_2[28:28]),.I2(r_4[13:13]),.I3(rd_4_sqmuxa),.I4(reg3_14_sqmuxa),.LO(\d_cnst_sn.reg3_17_6_0 [14:14]));
defparam desc336.INIT=32'hF3F3AAFF;
LUT5_L desc337(.I0(inf_abs0_2[15:15]),.I1(inf_abs0_2[28:28]),.I2(r_4[14:14]),.I3(rd_4_sqmuxa),.I4(reg3_14_sqmuxa),.LO(\d_cnst_sn.reg3_17_6_0 [15:15]));
defparam desc337.INIT=32'hF3F3AAFF;
LUT5_L desc338(.I0(inf_abs0_2[12:12]),.I1(inf_abs0_2[28:28]),.I2(r_4[11:11]),.I3(rd_4_sqmuxa),.I4(reg3_14_sqmuxa),.LO(\d_cnst_sn.reg3_17_6_0 [12:12]));
defparam desc338.INIT=32'hF3F3AAFF;
LUT5_L desc339(.I0(inf_abs0_2[13:13]),.I1(inf_abs0_2[28:28]),.I2(r_4[12:12]),.I3(rd_4_sqmuxa),.I4(reg3_14_sqmuxa),.LO(\d_cnst_sn.reg3_17_6_0 [13:13]));
defparam desc339.INIT=32'hF3F3AAFF;
LUT5_L desc340(.I0(inf_abs0_2[18:18]),.I1(inf_abs0_2[28:28]),.I2(r_4[17:17]),.I3(rd_4_sqmuxa),.I4(reg3_14_sqmuxa),.LO(\d_cnst_sn.reg3_17_6_0 [18:18]));
defparam desc340.INIT=32'hF3F3AAFF;
LUT2 desc341(.I0(inf_abs0_2[28:28]),.I1(reg3_14_sqmuxa),.O(\d_cnst_sn.reg3_17_a1_2 [24:24]));
defparam desc341.INIT=4'h4;
LUT5 desc342(.I0(datai[4:4]),.I1(inf_abs0_2[4:4]),.I2(inf_abs0_2[27:27]),.I3(inf_abs0_2[28:28]),.I4(un1_cf),.O(N_1661));
defparam desc342.INIT=32'hAAACAAAA;
LUT5_L desc343(.I0(datai[3:3]),.I1(inf_abs0_2[3:3]),.I2(inf_abs0_2[27:27]),.I3(inf_abs0_2[28:28]),.I4(un1_cf),.LO(N_1660));
defparam desc343.INIT=32'hAAACAAAA;
LUT5 desc344(.I0(datai[5:5]),.I1(inf_abs0_2[5:5]),.I2(inf_abs0_2[27:27]),.I3(inf_abs0_2[28:28]),.I4(un1_cf),.O(N_1662));
defparam desc344.INIT=32'hAAACAAAA;
LUT6 desc345(.I0(inf_abs0_2[21:21]),.I1(inf_abs0_2[22:22]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[28:28]),.I4(r_4[26:26]),.I5(reg3_1_1[27:27]),.O(\d_cnst_sn.reg1_16_8_1837_3_1 ));
defparam desc345.INIT=64'hF8F8F0F808080008;
LUT6 desc346(.I0(inf_abs0_2[21:21]),.I1(inf_abs0_2[22:22]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[28:28]),.I4(r_4[25:25]),.I5(reg3_1_1[26:26]),.O(\d_cnst_sn.reg1_16_7_1870_3_1 ));
defparam desc346.INIT=64'hF8F8F0F808080008;
LUT6 desc347(.I0(inf_abs0_2[21:21]),.I1(inf_abs0_2[22:22]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[28:28]),.I4(r_4[24:24]),.I5(reg3_1_1[25:25]),.O(\d_cnst_sn.reg0_28_9_2294_3_1 ));
defparam desc347.INIT=64'hF8F8F0F808080008;
LUT6 desc348(.I0(inf_abs0_2[21:21]),.I1(inf_abs0_2[22:22]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[28:28]),.I4(r_4[22:22]),.I5(reg3_1_1[23:23]),.O(\d_cnst_sn.reg0_28_7_2360_3_1 ));
defparam desc348.INIT=64'hF8F8F0F808080008;
LUT6 desc349(.I0(inf_abs0_2[21:21]),.I1(inf_abs0_2[22:22]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[28:28]),.I4(r_4[21:21]),.I5(reg3_1_1[22:22]),.O(\d_cnst_sn.reg0_28_6_2393_3_1 ));
defparam desc349.INIT=64'hF8F8F0F808080008;
LUT6 desc350(.I0(inf_abs0_2[21:21]),.I1(inf_abs0_2[22:22]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[28:28]),.I4(r_4[20:20]),.I5(reg3_1_1[21:21]),.O(\d_cnst_sn.reg0_28_5_2426_3_1 ));
defparam desc350.INIT=64'hF8F8F0F808080008;
LUT6 desc351(.I0(reg0[18:18]),.I1(reg2[18:18]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[29:29]),.I4(inf_abs0_2[30:30]),.I5(N_965),.O(r_4[18:18]));
defparam desc351.INIT=64'hAFACAFAAA0ACA0AA;
LUT6 desc352(.I0(reg0[18:18]),.I1(reg2[18:18]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[29:29]),.I4(inf_abs0_2[30:30]),.I5(N_965),.O(un3_t_axb_18));
defparam desc352.INIT=64'h505350555F535F55;
LUT6 desc353(.I0(reg0[21:21]),.I1(reg2[21:21]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[29:29]),.I4(inf_abs0_2[30:30]),.I5(N_968),.O(un3_t_axb_21));
defparam desc353.INIT=64'h505350555F535F55;
LUT6 desc354(.I0(reg0[21:21]),.I1(reg2[21:21]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[29:29]),.I4(inf_abs0_2[30:30]),.I5(N_968),.O(r_4[21:21]));
defparam desc354.INIT=64'hAFACAFAAA0ACA0AA;
LUT5 un32_reg0_axb_29_cZ(.I0(datai[29:29]),.I1(inf_abs0_2[31:31]),.I2(inf_abs0_2[27:27]),.I3(inf_abs0_2[28:28]),.I4(r_4[29:29]),.O(un32_reg0_axb_29));
defparam un32_reg0_axb_29_cZ.INIT=32'h2220DDDF;
LUT6 desc355(.I0(inf_abs0_2[19:19]),.I1(inf_abs0_2[20:20]),.I2(inf_abs0_2[22:22]),.I3(inf_abs0_2[31:31]),.I4(m_2[30:30]),.I5(reg3_1_1[30:30]),.O(N_1493));
defparam desc355.INIT=64'hFF0DFF01000C0000;
LUT6 desc356(.I0(un3_reg3_s_25),.I1(inf_abs0_2[19:19]),.I2(inf_abs0_2[20:20]),.I3(inf_abs0_2[31:31]),.I4(m_2[28:28]),.I5(reg3_1_1[28:28]),.O(N_1363));
defparam desc356.INIT=64'hFFFBFF0B00F80008;
LUT6 desc357(.I0(un3_reg3_s_24),.I1(inf_abs0_2[19:19]),.I2(inf_abs0_2[20:20]),.I3(inf_abs0_2[31:31]),.I4(m_2[27:27]),.I5(reg3_1_1[27:27]),.O(N_1362));
defparam desc357.INIT=64'hFFFBFF0B00F80008;
LUT6 desc358(.I0(un3_reg3_s_23),.I1(inf_abs0_2[19:19]),.I2(inf_abs0_2[20:20]),.I3(inf_abs0_2[31:31]),.I4(m_2[26:26]),.I5(reg3_1_1[26:26]),.O(N_1361));
defparam desc358.INIT=64'hFFFBFF0B00F80008;
LUT6 desc359(.I0(un3_reg3_s_16),.I1(inf_abs0_2[19:19]),.I2(inf_abs0_2[20:20]),.I3(inf_abs0_2[31:31]),.I4(m_2[19:19]),.I5(reg3_1_1[19:19]),.O(N_1354));
defparam desc359.INIT=64'hFFFBFF0B00F80008;
LUT6 desc360(.I0(un3_reg3_s_15),.I1(inf_abs0_2[19:19]),.I2(inf_abs0_2[20:20]),.I3(inf_abs0_2[31:31]),.I4(m_2[18:18]),.I5(reg3_1_1[18:18]),.O(N_1353));
defparam desc360.INIT=64'hFFFBFF0B00F80008;
LUT6 desc361(.I0(un3_reg3_s_14),.I1(inf_abs0_2[19:19]),.I2(inf_abs0_2[20:20]),.I3(inf_abs0_2[31:31]),.I4(m_2[17:17]),.I5(reg3_1_1[17:17]),.O(N_1352));
defparam desc361.INIT=64'hFFFBFF0B00F80008;
LUT6 desc362(.I0(un3_reg3_s_13),.I1(inf_abs0_2[19:19]),.I2(inf_abs0_2[20:20]),.I3(inf_abs0_2[31:31]),.I4(m_2[16:16]),.I5(reg3_1_1[16:16]),.O(N_1351));
defparam desc362.INIT=64'hFFFBFF0B00F80008;
LUT6 desc363(.I0(un3_reg3_s_12),.I1(inf_abs0_2[19:19]),.I2(inf_abs0_2[20:20]),.I3(inf_abs0_2[31:31]),.I4(m_2[15:15]),.I5(reg3_1_1[15:15]),.O(N_1350));
defparam desc363.INIT=64'hFFFBFF0B00F80008;
LUT6 desc364(.I0(un3_reg3_s_11),.I1(inf_abs0_2[19:19]),.I2(inf_abs0_2[20:20]),.I3(inf_abs0_2[31:31]),.I4(m_2[14:14]),.I5(reg3_1_1[14:14]),.O(N_1349));
defparam desc364.INIT=64'hFFFBFF0B00F80008;
LUT6 desc365(.I0(un3_reg3_s_10),.I1(inf_abs0_2[19:19]),.I2(inf_abs0_2[20:20]),.I3(inf_abs0_2[31:31]),.I4(m_2[13:13]),.I5(reg3_1_1[13:13]),.O(N_1348));
defparam desc365.INIT=64'hFFFBFF0B00F80008;
LUT6 desc366(.I0(un3_reg3_s_9),.I1(inf_abs0_2[19:19]),.I2(inf_abs0_2[20:20]),.I3(inf_abs0_2[31:31]),.I4(m_2[12:12]),.I5(reg3_1_1[12:12]),.O(N_1347));
defparam desc366.INIT=64'hFFFBFF0B00F80008;
LUT6 desc367(.I0(un3_reg3_s_8),.I1(inf_abs0_2[19:19]),.I2(inf_abs0_2[20:20]),.I3(inf_abs0_2[31:31]),.I4(m_2[11:11]),.I5(reg3_1_1[11:11]),.O(N_1346));
defparam desc367.INIT=64'hFFFBFF0B00F80008;
LUT6 desc368(.I0(un3_reg3_s_7),.I1(inf_abs0_2[19:19]),.I2(inf_abs0_2[20:20]),.I3(inf_abs0_2[31:31]),.I4(m_2[10:10]),.I5(reg3_1_1[10:10]),.O(N_1345));
defparam desc368.INIT=64'hFFFBFF0B00F80008;
LUT6 desc369(.I0(un3_reg3_s_6),.I1(inf_abs0_2[19:19]),.I2(inf_abs0_2[20:20]),.I3(inf_abs0_2[31:31]),.I4(m_2[9:9]),.I5(reg3_1_1[9:9]),.O(N_1344));
defparam desc369.INIT=64'hFFFBFF0B00F80008;
LUT6 desc370(.I0(un3_reg3_s_5),.I1(inf_abs0_2[19:19]),.I2(inf_abs0_2[20:20]),.I3(inf_abs0_2[31:31]),.I4(m_2[8:8]),.I5(reg3_1_1[8:8]),.O(N_1343));
defparam desc370.INIT=64'hFFFBFF0B00F80008;
LUT6 desc371(.I0(un3_reg3_s_4),.I1(inf_abs0_2[19:19]),.I2(inf_abs0_2[20:20]),.I3(inf_abs0_2[31:31]),.I4(m_2[7:7]),.I5(reg3_1_1[7:7]),.O(N_1342));
defparam desc371.INIT=64'hFFFBFF0B00F80008;
LUT6 desc372(.I0(un3_reg3_s_3),.I1(inf_abs0_2[19:19]),.I2(inf_abs0_2[20:20]),.I3(inf_abs0_2[31:31]),.I4(m_2[6:6]),.I5(reg3_1_1[6:6]),.O(N_1341));
defparam desc372.INIT=64'hFFFBFF0B00F80008;
LUT6 desc373(.I0(un3_reg3_s_2),.I1(inf_abs0_2[19:19]),.I2(inf_abs0_2[20:20]),.I3(inf_abs0_2[31:31]),.I4(m_2[5:5]),.I5(reg3_1_1[5:5]),.O(N_1340));
defparam desc373.INIT=64'hFFFBFF0B00F80008;
LUT6 desc374(.I0(un3_reg3_s_1),.I1(inf_abs0_2[19:19]),.I2(inf_abs0_2[20:20]),.I3(inf_abs0_2[31:31]),.I4(m_2[4:4]),.I5(reg3_1_1[4:4]),.O(N_1339));
defparam desc374.INIT=64'hFFFBFF0B00F80008;
LUT6 desc375(.I0(reg3[3:3]),.I1(inf_abs0_2[19:19]),.I2(inf_abs0_2[20:20]),.I3(inf_abs0_2[31:31]),.I4(m_2[3:3]),.I5(reg3_1_1[3:3]),.O(N_1338));
defparam desc375.INIT=64'hFFF7FF0700F40004;
LUT6 desc376(.I0(reg3[2:2]),.I1(inf_abs0_2[19:19]),.I2(inf_abs0_2[20:20]),.I3(inf_abs0_2[31:31]),.I4(m_2[2:2]),.I5(reg3_1_1[2:2]),.O(N_1337));
defparam desc376.INIT=64'hFFFBFF0B00F80008;
LUT6 desc377(.I0(reg3[1:1]),.I1(inf_abs0_2[19:19]),.I2(inf_abs0_2[20:20]),.I3(inf_abs0_2[31:31]),.I4(m_2[1:1]),.I5(reg3_1_1[1:1]),.O(N_1336));
defparam desc377.INIT=64'hFFFBFF0B00F80008;
LUT6 desc378(.I0(un3_reg3_s_22),.I1(inf_abs0_2[19:19]),.I2(inf_abs0_2[31:31]),.I3(\d_cnst_sn.reg0_28_a0_1 [7:7]),.I4(\d_cnst_sn.reg2_16_0 [25:25]),.I5(reg3_1_1[25:25]),.O(\d_cnst_sn.reg2_16_1 [25:25]));
defparam desc378.INIT=64'hFBFF000008FF0000;
LUT6 desc379(.I0(un3_reg3_s_21),.I1(inf_abs0_2[19:19]),.I2(inf_abs0_2[31:31]),.I3(\d_cnst_sn.reg0_28_a0_1 [7:7]),.I4(\d_cnst_sn.reg2_16_0 [24:24]),.I5(reg3_1_1[24:24]),.O(\d_cnst_sn.reg2_16_1 [24:24]));
defparam desc379.INIT=64'hFBFF000008FF0000;
LUT6 desc380(.I0(un3_reg3_s_20),.I1(inf_abs0_2[19:19]),.I2(inf_abs0_2[31:31]),.I3(\d_cnst_sn.reg0_28_a0_1 [7:7]),.I4(\d_cnst_sn.reg2_16_0 [23:23]),.I5(reg3_1_1[23:23]),.O(\d_cnst_sn.reg2_16_1 [23:23]));
defparam desc380.INIT=64'hFBFF000008FF0000;
LUT6 desc381(.I0(un3_reg3_s_19),.I1(inf_abs0_2[19:19]),.I2(inf_abs0_2[31:31]),.I3(\d_cnst_sn.reg0_28_a0_1 [7:7]),.I4(\d_cnst_sn.reg2_16_0 [22:22]),.I5(reg3_1_1[22:22]),.O(\d_cnst_sn.reg2_16_1 [22:22]));
defparam desc381.INIT=64'hFBFF000008FF0000;
LUT6 desc382(.I0(un3_reg3_s_18),.I1(inf_abs0_2[19:19]),.I2(inf_abs0_2[31:31]),.I3(\d_cnst_sn.reg0_28_a0_1 [7:7]),.I4(reg3_1_1[21:21]),.I5(\d_cnst_sn.reg2_16_0 [21:21]),.O(\d_cnst_sn.reg2_16_1 [21:21]));
defparam desc382.INIT=64'hFBFF08FF00000000;
LUT6 desc383(.I0(inf_abs0_2[21:21]),.I1(inf_abs0_2[31:31]),.I2(inf_abs0_2[28:28]),.I3(r_4[15:15]),.I4(reg3_1_1[16:16]),.I5(t_1[16:16]),.O(N_1083));
defparam desc383.INIT=64'hFDDD2000FFDF2202;
LUT6 desc384(.I0(inf_abs0_2[21:21]),.I1(inf_abs0_2[31:31]),.I2(inf_abs0_2[28:28]),.I3(r_4[14:14]),.I4(reg3_1_1[15:15]),.I5(t_1[15:15]),.O(N_1082));
defparam desc384.INIT=64'hFDDD2000FFDF2202;
LUT6 desc385(.I0(inf_abs0_2[21:21]),.I1(inf_abs0_2[31:31]),.I2(inf_abs0_2[28:28]),.I3(r_4[13:13]),.I4(reg3_1_1[14:14]),.I5(t_1[14:14]),.O(N_1081));
defparam desc385.INIT=64'hFDDD2000FFDF2202;
LUT6 desc386(.I0(inf_abs0_2[21:21]),.I1(inf_abs0_2[31:31]),.I2(inf_abs0_2[28:28]),.I3(r_4[12:12]),.I4(reg3_1_1[13:13]),.I5(t_1[13:13]),.O(N_1080));
defparam desc386.INIT=64'hFDDD2000FFDF2202;
LUT6 desc387(.I0(inf_abs0_2[21:21]),.I1(inf_abs0_2[31:31]),.I2(inf_abs0_2[28:28]),.I3(r_4[11:11]),.I4(reg3_1_1[12:12]),.I5(t_1[12:12]),.O(N_1079));
defparam desc387.INIT=64'hFDDD2000FFDF2202;
LUT6 desc388(.I0(inf_abs0_2[21:21]),.I1(inf_abs0_2[31:31]),.I2(inf_abs0_2[28:28]),.I3(r_4[10:10]),.I4(reg3_1_1[11:11]),.I5(t_1[11:11]),.O(N_1078));
defparam desc388.INIT=64'hFDDD2000FFDF2202;
LUT6 desc389(.I0(inf_abs0_2[21:21]),.I1(inf_abs0_2[31:31]),.I2(inf_abs0_2[28:28]),.I3(r_4[9:9]),.I4(reg3_1_1[10:10]),.I5(t_1[10:10]),.O(N_1077));
defparam desc389.INIT=64'hFDDD2000FFDF2202;
LUT6 desc390(.I0(inf_abs0_2[21:21]),.I1(inf_abs0_2[31:31]),.I2(inf_abs0_2[28:28]),.I3(r_4[8:8]),.I4(reg3_1_1[9:9]),.I5(t_1[9:9]),.O(N_1076));
defparam desc390.INIT=64'hFDDD2000FFDF2202;
LUT6_L desc391(.I0(inf_abs0_2[21:21]),.I1(inf_abs0_2[31:31]),.I2(inf_abs0_2[28:28]),.I3(reg3_1_1[2:2]),.I4(r_4[1:1]),.I5(t_1[2:2]),.LO(N_1069));
defparam desc391.INIT=64'hFD20DD00FF22DF02;
LUT6 desc392(.I0(inf_abs0_2[21:21]),.I1(inf_abs0_2[31:31]),.I2(inf_abs0_2[28:28]),.I3(reg3_1_1[1:1]),.I4(r_4[0:0]),.I5(t_1[1:1]),.O(N_1068));
defparam desc392.INIT=64'hFD20DD00FF22DF02;
LUT6 desc393(.I0(inf_abs0_2[20:20]),.I1(inf_abs0_2[21:21]),.I2(inf_abs0_2[22:22]),.I3(inf_abs0_2[31:31]),.I4(N_3568),.I5(reg3_1_1[30:30]),.O(\d_cnst_sn.reg0_28_14_0 ));
defparam desc393.INIT=64'hFFFFC101FFFF0000;
LUT6 desc394(.I0(reg1[4:4]),.I1(un3_reg3_s_1),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[29:29]),.I4(inf_abs0_2[30:30]),.I5(N_919),.O(r_4[4:4]));
defparam desc394.INIT=64'hFCFFFAFF0C000A00;
LUT6 desc395(.I0(reg1[4:4]),.I1(un3_reg3_s_1),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[29:29]),.I4(inf_abs0_2[30:30]),.I5(N_919),.O(un3_t_axb_4));
defparam desc395.INIT=64'h03000500F3FFF5FF;
LUT6 desc396(.I0(reg1[1:1]),.I1(reg3[1:1]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[29:29]),.I4(inf_abs0_2[30:30]),.I5(N_916),.O(un3_t_axb_1));
defparam desc396.INIT=64'h03000500F3FFF5FF;
LUT6 desc397(.I0(reg1[1:1]),.I1(reg3[1:1]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[29:29]),.I4(inf_abs0_2[30:30]),.I5(N_916),.O(r_4[1:1]));
defparam desc397.INIT=64'hFCFFFAFF0C000A00;
LUT6 desc398(.I0(reg1[0:0]),.I1(reg3[0:0]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[29:29]),.I4(inf_abs0_2[30:30]),.I5(N_915),.O(r_4[0:0]));
defparam desc398.INIT=64'hFCFFFAFF0C000A00;
LUT6 desc399(.I0(reg1[0:0]),.I1(reg3[0:0]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[29:29]),.I4(inf_abs0_2[30:30]),.I5(N_915),.O(un3_t_axb_0));
defparam desc399.INIT=64'h03000500F3FFF5FF;
LUT6 desc400(.I0(reg1[24:24]),.I1(un3_reg3_s_21),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[29:29]),.I4(inf_abs0_2[30:30]),.I5(N_939),.O(r_4[24:24]));
defparam desc400.INIT=64'hFCFFFAFF0C000A00;
LUT6 desc401(.I0(reg1[24:24]),.I1(un3_reg3_s_21),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[29:29]),.I4(inf_abs0_2[30:30]),.I5(N_939),.O(un3_t_axb_24));
defparam desc401.INIT=64'h03000500F3FFF5FF;
LUT6 desc402(.I0(reg1[23:23]),.I1(un3_reg3_s_20),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[29:29]),.I4(inf_abs0_2[30:30]),.I5(N_938),.O(r_4[23:23]));
defparam desc402.INIT=64'hFCFFFAFF0C000A00;
LUT6 desc403(.I0(reg1[23:23]),.I1(un3_reg3_s_20),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[29:29]),.I4(inf_abs0_2[30:30]),.I5(N_938),.O(un3_t_axb_23));
defparam desc403.INIT=64'h03000500F3FFF5FF;
LUT6 desc404(.I0(reg1[27:27]),.I1(un3_reg3_s_24),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[29:29]),.I4(inf_abs0_2[30:30]),.I5(N_942),.O(r_4[27:27]));
defparam desc404.INIT=64'hFCFFFAFF0C000A00;
LUT6 desc405(.I0(reg1[27:27]),.I1(un3_reg3_s_24),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[29:29]),.I4(inf_abs0_2[30:30]),.I5(N_942),.O(un3_t_axb_27));
defparam desc405.INIT=64'h03000500F3FFF5FF;
LUT6 desc406(.I0(reg1[20:20]),.I1(un3_reg3_s_17),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[29:29]),.I4(inf_abs0_2[30:30]),.I5(N_935),.O(r_4[20:20]));
defparam desc406.INIT=64'hFCFFFAFF0C000A00;
LUT6 desc407(.I0(reg1[20:20]),.I1(un3_reg3_s_17),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[29:29]),.I4(inf_abs0_2[30:30]),.I5(N_935),.O(un3_t_axb_20));
defparam desc407.INIT=64'h03000500F3FFF5FF;
LUT6 desc408(.I0(reg0[25:25]),.I1(reg2[25:25]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[29:29]),.I4(inf_abs0_2[30:30]),.I5(N_972),.O(r_4[25:25]));
defparam desc408.INIT=64'hAFACAFAAA0ACA0AA;
LUT6 desc409(.I0(reg0[25:25]),.I1(reg2[25:25]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[29:29]),.I4(inf_abs0_2[30:30]),.I5(N_972),.O(un3_t_axb_25));
defparam desc409.INIT=64'h505350555F535F55;
LUT6 desc410(.I0(reg0[28:28]),.I1(reg2[28:28]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[29:29]),.I4(inf_abs0_2[30:30]),.I5(N_975),.O(r_4[28:28]));
defparam desc410.INIT=64'hAFACAFAAA0ACA0AA;
LUT6 desc411(.I0(reg0[28:28]),.I1(reg2[28:28]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[29:29]),.I4(inf_abs0_2[30:30]),.I5(N_975),.O(un3_t_axb_28));
defparam desc411.INIT=64'h505350555F535F55;
LUT6 desc412(.I0(reg0[26:26]),.I1(reg2[26:26]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[29:29]),.I4(inf_abs0_2[30:30]),.I5(N_973),.O(r_4[26:26]));
defparam desc412.INIT=64'hAFACAFAAA0ACA0AA;
LUT6 desc413(.I0(reg0[26:26]),.I1(reg2[26:26]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[29:29]),.I4(inf_abs0_2[30:30]),.I5(N_973),.O(un3_t_axb_26));
defparam desc413.INIT=64'h505350555F535F55;
LUT6 desc414(.I0(reg1[22:22]),.I1(un3_reg3_s_19),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[29:29]),.I4(inf_abs0_2[30:30]),.I5(N_937),.O(un3_t_axb_22));
defparam desc414.INIT=64'h03000500F3FFF5FF;
LUT6 desc415(.I0(reg1[22:22]),.I1(un3_reg3_s_19),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[29:29]),.I4(inf_abs0_2[30:30]),.I5(N_937),.O(r_4[22:22]));
defparam desc415.INIT=64'hFCFFFAFF0C000A00;
LUT6 desc416(.I0(reg1[3:3]),.I1(reg3[3:3]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[29:29]),.I4(inf_abs0_2[30:30]),.I5(N_918),.O(r_4[3:3]));
defparam desc416.INIT=64'hF3FFFAFF03000A00;
LUT6 desc417(.I0(reg1[3:3]),.I1(reg3[3:3]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[29:29]),.I4(inf_abs0_2[30:30]),.I5(N_918),.O(un3_t_axb_3));
defparam desc417.INIT=64'h0C000500FCFFF5FF;
LUT5 desc418(.I0(inf_abs0_2[31:31]),.I1(inf_abs0_2[28:28]),.I2(inf_abs0_2[29:29]),.I3(N_967),.I4(N_935),.O(\d_cnst_sn.reg3_17_a2_2_0 [21:21]));
defparam desc418.INIT=32'h44044000;
LUT5 desc419(.I0(inf_abs0_2[31:31]),.I1(inf_abs0_2[28:28]),.I2(inf_abs0_2[29:29]),.I3(N_941),.I4(N_973),.O(\d_cnst_sn.reg3_17_4_a2_0 [27:27]));
defparam desc419.INIT=32'h44400400;
LUT5 desc420(.I0(inf_abs0_2[31:31]),.I1(inf_abs0_2[28:28]),.I2(inf_abs0_2[29:29]),.I3(N_971),.I4(N_939),.O(\d_cnst_sn.reg3_17_4_a2_0 [25:25]));
defparam desc420.INIT=32'h44044000;
LUT5 desc421(.I0(inf_abs0_2[31:31]),.I1(inf_abs0_2[28:28]),.I2(inf_abs0_2[29:29]),.I3(N_974),.I4(N_942),.O(\d_cnst_sn.reg3_17_4_a2_0 [28:28]));
defparam desc421.INIT=32'h44044000;
LUT5 desc422(.I0(inf_abs0_2[31:31]),.I1(inf_abs0_2[28:28]),.I2(inf_abs0_2[29:29]),.I3(N_940),.I4(N_972),.O(\d_cnst_sn.reg3_17_4_a2_0 [26:26]));
defparam desc422.INIT=32'h44400400;
LUT6 desc423(.I0(inf_abs0_2[21:21]),.I1(inf_abs0_2[31:31]),.I2(inf_abs0_2[29:29]),.I3(N_970),.I4(N_938),.I5(reg3_1_1[24:24]),.O(reg0_28_7_d[24:24]));
defparam desc423.INIT=64'hFFDFFDDD22022000;
LUT6 desc424(.I0(datai[26:26]),.I1(inf_abs0_2[31:31]),.I2(inf_abs0_2[29:29]),.I3(N_941),.I4(N_973),.I5(m7),.O(un32_reg0_axb_26));
defparam desc424.INIT=64'h00CF30FFAA659A55;
LUT6 desc425(.I0(datai[25:25]),.I1(inf_abs0_2[31:31]),.I2(inf_abs0_2[29:29]),.I3(N_940),.I4(N_972),.I5(m7),.O(un32_reg0_axb_25));
defparam desc425.INIT=64'h00CF30FFAA659A55;
LUT6 desc426(.I0(datai[23:23]),.I1(inf_abs0_2[31:31]),.I2(inf_abs0_2[29:29]),.I3(N_970),.I4(N_938),.I5(m7),.O(un32_reg0_axb_23));
defparam desc426.INIT=64'h0030CFFFAA9A6555;
LUT6 desc427(.I0(inf_abs0_2[31:31]),.I1(inf_abs0_2[29:29]),.I2(r_4_2_a0[1:1]),.I3(\d_cnst_sn.r_4_0_0 [1:1]),.I4(N_916),.I5(m_2[1:1]),.O(un32_reg0_axb_1));
defparam desc427.INIT=64'hBFBB04004044FBFF;
LUT6 desc428(.I0(inf_abs0_2[31:31]),.I1(inf_abs0_2[29:29]),.I2(m_2_i[0:0]),.I3(r_4_2_a0[0:0]),.I4(\d_cnst_sn.r_4_0_0 [0:0]),.I5(N_915),.O(N_1035));
defparam desc428.INIT=64'h4B0F4B4BF0B4F0F0;
LUT6 desc429(.I0(datai[28:28]),.I1(inf_abs0_2[31:31]),.I2(inf_abs0_2[29:29]),.I3(N_943),.I4(N_975),.I5(m7),.O(un32_reg0_axb_28));
defparam desc429.INIT=64'h00CF30FFAA659A55;
LUT6 desc430(.I0(datai[27:27]),.I1(inf_abs0_2[31:31]),.I2(inf_abs0_2[29:29]),.I3(N_974),.I4(N_942),.I5(m7),.O(un32_reg0_axb_27));
defparam desc430.INIT=64'h0030CFFFAA9A6555;
LUT6 desc431(.I0(datai[20:20]),.I1(inf_abs0_2[31:31]),.I2(inf_abs0_2[29:29]),.I3(N_967),.I4(N_935),.I5(m7),.O(un32_reg0_axb_20));
defparam desc431.INIT=64'h0030CFFFAA9A6555;
LUT6 desc432(.I0(datai[24:24]),.I1(inf_abs0_2[31:31]),.I2(inf_abs0_2[29:29]),.I3(N_971),.I4(N_939),.I5(m7),.O(un32_reg0_axb_24));
defparam desc432.INIT=64'h0030CFFFAA9A6555;
LUT6 desc433(.I0(datai[22:22]),.I1(inf_abs0_2[31:31]),.I2(inf_abs0_2[29:29]),.I3(N_969),.I4(N_937),.I5(m7),.O(un32_reg0_axb_22));
defparam desc433.INIT=64'h0030CFFFAA9A6555;
LUT6 desc434(.I0(datai[21:21]),.I1(inf_abs0_2[31:31]),.I2(inf_abs0_2[29:29]),.I3(N_936),.I4(N_968),.I5(m7),.O(un32_reg0_axb_21));
defparam desc434.INIT=64'h00CF30FFAA659A55;
LUT5 desc435(.I0(state),.I1(inf_abs0_2[23:23]),.I2(inf_abs0_2[31:31]),.I3(un1_df_1),.I4(un36_df),.O(dce));
defparam desc435.INIT=32'h000000A2;
LUT6 desc436(.I0(state),.I1(inf_abs0_2[23:23]),.I2(inf_abs0_2[31:31]),.I3(N_1892),.I4(un36_df),.I5(N_1890),.O(\d_cnst_sn.un1_state_3_1 ));
defparam desc436.INIT=64'hFFFFFF5DFFFFFFFF;
LUT4 desc437(.I0(inf_abs0_2[31:31]),.I1(inf_abs0_2[28:28]),.I2(N_28),.I3(t_1[3:3]),.O(t_6[3:3]));
defparam desc437.INIT=16'h40FB;
LUT6 desc438(.I0(inf_abs0_2[21:21]),.I1(inf_abs0_2[22:22]),.I2(inf_abs0_2[31:31]),.I3(N_1033),.I4(un32_reg0_s_28),.I5(un11_reg0_s_28),.O(N_3614));
defparam desc438.INIT=64'h0606060000060000;
LUT5 un11_reg0_axb_29_cZ(.I0(datai[29:29]),.I1(inf_abs0_2[31:31]),.I2(inf_abs0_2[27:27]),.I3(inf_abs0_2[28:28]),.I4(r_4[29:29]),.O(un11_reg0_axb_29));
defparam un11_reg0_axb_29_cZ.INIT=32'hDDDF2220;
LUT6 desc439(.I0(reg0[19:19]),.I1(reg2[19:19]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[29:29]),.I4(inf_abs0_2[30:30]),.I5(N_2722),.O(r_4[19:19]));
defparam desc439.INIT=64'hAFACAFAAA0ACA0AA;
LUT6 desc440(.I0(reg0[19:19]),.I1(reg2[19:19]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[29:29]),.I4(inf_abs0_2[30:30]),.I5(N_2722),.O(un3_t_axb_19));
defparam desc440.INIT=64'h505350555F535F55;
LUT6 desc441(.I0(reg0[6:6]),.I1(reg2[6:6]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[29:29]),.I4(inf_abs0_2[30:30]),.I5(N_953),.O(r_4[6:6]));
defparam desc441.INIT=64'hAFACAFAAA0ACA0AA;
LUT6 desc442(.I0(reg0[6:6]),.I1(reg2[6:6]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[29:29]),.I4(inf_abs0_2[30:30]),.I5(N_953),.O(un3_t_axb_6));
defparam desc442.INIT=64'h505350555F535F55;
LUT6 desc443(.I0(reg0[12:12]),.I1(reg2[12:12]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[29:29]),.I4(inf_abs0_2[30:30]),.I5(N_959),.O(un3_t_axb_12));
defparam desc443.INIT=64'h505350555F535F55;
LUT6 desc444(.I0(reg0[12:12]),.I1(reg2[12:12]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[29:29]),.I4(inf_abs0_2[30:30]),.I5(N_959),.O(r_4[12:12]));
defparam desc444.INIT=64'hAFACAFAAA0ACA0AA;
LUT6 desc445(.I0(reg0[5:5]),.I1(reg2[5:5]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[29:29]),.I4(inf_abs0_2[30:30]),.I5(N_952),.O(r_4[5:5]));
defparam desc445.INIT=64'hAFACAFAAA0ACA0AA;
LUT6 desc446(.I0(reg0[5:5]),.I1(reg2[5:5]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[29:29]),.I4(inf_abs0_2[30:30]),.I5(N_952),.O(un3_t_axb_5));
defparam desc446.INIT=64'h505350555F535F55;
LUT6 desc447(.I0(reg0[17:17]),.I1(reg2[17:17]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[29:29]),.I4(inf_abs0_2[30:30]),.I5(N_964),.O(r_4[17:17]));
defparam desc447.INIT=64'hAFACAFAAA0ACA0AA;
LUT6 desc448(.I0(reg0[17:17]),.I1(reg2[17:17]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[29:29]),.I4(inf_abs0_2[30:30]),.I5(N_964),.O(un3_t_axb_17));
defparam desc448.INIT=64'h505350555F535F55;
LUT6 desc449(.I0(reg0[7:7]),.I1(reg2[7:7]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[29:29]),.I4(inf_abs0_2[30:30]),.I5(N_954),.O(r_4[7:7]));
defparam desc449.INIT=64'hAFACAFAAA0ACA0AA;
LUT6 desc450(.I0(reg0[7:7]),.I1(reg2[7:7]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[29:29]),.I4(inf_abs0_2[30:30]),.I5(N_954),.O(un3_t_axb_7));
defparam desc450.INIT=64'h505350555F535F55;
LUT6 desc451(.I0(reg0[9:9]),.I1(reg2[9:9]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[29:29]),.I4(inf_abs0_2[30:30]),.I5(N_956),.O(r_4[9:9]));
defparam desc451.INIT=64'hAFACAFAAA0ACA0AA;
LUT6 desc452(.I0(reg0[9:9]),.I1(reg2[9:9]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[29:29]),.I4(inf_abs0_2[30:30]),.I5(N_956),.O(un3_t_axb_9));
defparam desc452.INIT=64'h505350555F535F55;
LUT6 desc453(.I0(reg0[10:10]),.I1(reg2[10:10]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[29:29]),.I4(inf_abs0_2[30:30]),.I5(N_957),.O(r_4[10:10]));
defparam desc453.INIT=64'hAFACAFAAA0ACA0AA;
LUT6 desc454(.I0(reg0[10:10]),.I1(reg2[10:10]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[29:29]),.I4(inf_abs0_2[30:30]),.I5(N_957),.O(un3_t_axb_10));
defparam desc454.INIT=64'h505350555F535F55;
LUT6 desc455(.I0(reg0[14:14]),.I1(reg2[14:14]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[29:29]),.I4(inf_abs0_2[30:30]),.I5(N_961),.O(un3_t_axb_14));
defparam desc455.INIT=64'h505350555F535F55;
LUT6 desc456(.I0(reg0[14:14]),.I1(reg2[14:14]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[29:29]),.I4(inf_abs0_2[30:30]),.I5(N_961),.O(r_4[14:14]));
defparam desc456.INIT=64'hAFACAFAAA0ACA0AA;
LUT6 desc457(.I0(reg0[16:16]),.I1(reg2[16:16]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[29:29]),.I4(inf_abs0_2[30:30]),.I5(N_963),.O(r_4[16:16]));
defparam desc457.INIT=64'hAFACAFAAA0ACA0AA;
LUT6 desc458(.I0(reg0[16:16]),.I1(reg2[16:16]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[29:29]),.I4(inf_abs0_2[30:30]),.I5(N_963),.O(un3_t_axb_16));
defparam desc458.INIT=64'h505350555F535F55;
LUT6 desc459(.I0(reg0[13:13]),.I1(reg2[13:13]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[29:29]),.I4(inf_abs0_2[30:30]),.I5(N_960),.O(r_4[13:13]));
defparam desc459.INIT=64'hAFACAFAAA0ACA0AA;
LUT6 desc460(.I0(reg0[13:13]),.I1(reg2[13:13]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[29:29]),.I4(inf_abs0_2[30:30]),.I5(N_960),.O(un3_t_axb_13));
defparam desc460.INIT=64'h505350555F535F55;
LUT6 desc461(.I0(reg0[11:11]),.I1(reg2[11:11]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[29:29]),.I4(inf_abs0_2[30:30]),.I5(N_958),.O(r_4[11:11]));
defparam desc461.INIT=64'hAFACAFAAA0ACA0AA;
LUT6 desc462(.I0(reg0[11:11]),.I1(reg2[11:11]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[29:29]),.I4(inf_abs0_2[30:30]),.I5(N_958),.O(un3_t_axb_11));
defparam desc462.INIT=64'h505350555F535F55;
LUT6 desc463(.I0(reg1[4:4]),.I1(inf_abs0_2[30:30]),.I2(\d_cnst_sn.r_4_0_0 [4:4]),.I3(N_919),.I4(m_2[4:4]),.I5(N_13),.O(un32_reg0_axb_4));
defparam desc463.INIT=64'hFF0000FFE0E01F1F;
LUT6 desc464(.I0(reg0[15:15]),.I1(reg2[15:15]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[29:29]),.I4(inf_abs0_2[30:30]),.I5(N_962),.O(r_4[15:15]));
defparam desc464.INIT=64'hAFACAFAAA0ACA0AA;
LUT6 desc465(.I0(reg0[15:15]),.I1(reg2[15:15]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[29:29]),.I4(inf_abs0_2[30:30]),.I5(N_962),.O(un3_t_axb_15));
defparam desc465.INIT=64'h505350555F535F55;
LUT6_L desc466(.I0(state),.I1(un1_inf_abs0_10[1:1]),.I2(inf_abs0_2[27:27]),.I3(inf_abs0_2[28:28]),.I4(\d_cnst_sn.addr_20_iv_8_627_i_1 ),.I5(N_2641),.LO(N_2315_i));
defparam desc466.INIT=64'h000000000000DFFF;
LUT6 desc467(.I0(reg0[8:8]),.I1(reg2[8:8]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[29:29]),.I4(inf_abs0_2[30:30]),.I5(N_955),.O(r_4[8:8]));
defparam desc467.INIT=64'hAFACAFAAA0ACA0AA;
LUT6 desc468(.I0(reg0[8:8]),.I1(reg2[8:8]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[29:29]),.I4(inf_abs0_2[30:30]),.I5(N_955),.O(un3_t_axb_8));
defparam desc468.INIT=64'h505350555F535F55;
LUT6_L desc469(.I0(reg2[0:0]),.I1(inf_abs0_2[0:0]),.I2(inf_abs0_2[28:28]),.I3(\d_cnst_sn.addr_20_iv_7_654_i_1 ),.I4(N_2660_2),.I5(N_2641),.LO(N_2335_i));
defparam desc469.INIT=64'h00000000006F00FF;
LUT6 desc470(.I0(reg1[3:3]),.I1(inf_abs0_2[30:30]),.I2(\d_cnst_sn.r_4_0_0 [3:3]),.I3(N_918),.I4(m_2[3:3]),.I5(N_13),.O(un32_reg0_axb_3));
defparam desc470.INIT=64'hFF0000FFE0E01F1F;
LUT6 desc471(.I0(datai[2:2]),.I1(inf_abs0_2[2:2]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[27:27]),.I4(inf_abs0_2[28:28]),.I5(N_28),.O(un32_reg0_axb_2));
defparam desc471.INIT=64'hCACACACC35353533;
LUT4 desc472(.I0(inf_abs0_2[20:20]),.I1(inf_abs0_2[31:31]),.I2(un32_reg0_s_22),.I3(un11_reg0_s_22),.O(N_1581));
defparam desc472.INIT=16'hFD20;
LUT6 un11_r_df22_cZ(.I0(N_969),.I1(N_937),.I2(m_2[22:22]),.I3(m_2[23:23]),.I4(N_13),.I5(r_4[23:23]),.O(un11_r_df22));
defparam un11_r_df22_cZ.INIT=64'hC300A50000C300A5;
LUT6 un11_r_lt22_cZ(.I0(N_969),.I1(N_937),.I2(m_2[22:22]),.I3(m_2[23:23]),.I4(N_13),.I5(r_4[23:23]),.O(un11_r_lt22));
defparam un11_r_lt22_cZ.INIT=64'h30005000FF30FF50;
LUT6 un26_r_lt22_cZ(.I0(N_969),.I1(N_937),.I2(m_2[22:22]),.I3(m_2[23:23]),.I4(N_13),.I5(r_4[23:23]),.O(un26_r_lt22));
defparam un26_r_lt22_cZ.INIT=64'h30005000FF30FF50;
LUT6 un26_r_df22_cZ(.I0(N_969),.I1(N_937),.I2(m_2[22:22]),.I3(m_2[23:23]),.I4(N_13),.I5(r_4[23:23]),.O(un26_r_df22));
defparam un26_r_df22_cZ.INIT=64'hC300A50000C300A5;
LUT6 b18_df22_cZ(.I0(N_969),.I1(N_937),.I2(m_2[22:22]),.I3(m_2[23:23]),.I4(N_13),.I5(r_4[23:23]),.O(b18_df22));
defparam b18_df22_cZ.INIT=64'hC300A50000C300A5;
LUT6 b18_lt22_cZ(.I0(N_969),.I1(N_937),.I2(m_2[22:22]),.I3(m_2[23:23]),.I4(N_13),.I5(r_4[23:23]),.O(b18_lt22));
defparam b18_lt22_cZ.INIT=64'h0CFF0AFF000C000A;
LUT4 desc473(.I0(inf_abs0_2[19:19]),.I1(inf_abs0_2[31:31]),.I2(un32_reg0_s_8),.I3(un11_reg0_s_8),.O(N_1375));
defparam desc473.INIT=16'hFD20;
LUT4 desc474(.I0(inf_abs0_2[20:20]),.I1(inf_abs0_2[31:31]),.I2(un32_reg0_s_23),.I3(un11_reg0_s_23),.O(N_1582));
defparam desc474.INIT=16'hFD20;
LUT4_L desc475(.I0(inf_abs0_2[20:20]),.I1(inf_abs0_2[31:31]),.I2(b18),.I3(un26_r_cry[30:30]),.LO(N_895));
defparam desc475.INIT=16'h2F0D;
LUT4 desc476(.I0(inf_abs0_2[20:20]),.I1(inf_abs0_2[31:31]),.I2(un32_reg0_s_21),.I3(un11_reg0_s_21),.O(N_1580));
defparam desc476.INIT=16'hFD20;
LUT4 desc477(.I0(inf_abs0_2[20:20]),.I1(inf_abs0_2[31:31]),.I2(un32_reg0_s_16),.I3(un11_reg0_s_16),.O(N_1575));
defparam desc477.INIT=16'hFD20;
LUT4 desc478(.I0(inf_abs0_2[19:19]),.I1(inf_abs0_2[31:31]),.I2(un32_reg0_s_14),.I3(un11_reg0_s_14),.O(N_1381));
defparam desc478.INIT=16'hFD20;
LUT4 desc479(.I0(inf_abs0_2[20:20]),.I1(inf_abs0_2[31:31]),.I2(un32_reg0_s_24),.I3(un11_reg0_s_24),.O(N_1583));
defparam desc479.INIT=16'hFD20;
LUT6_L desc480(.I0(r_4_2_a0[1:1]),.I1(\d_cnst_sn.r_4_0_0 [1:1]),.I2(N_916),.I3(N_527_i),.I4(N_13),.I5(t_1[2:2]),.LO(t_6[2:2]));
defparam desc480.INIT=64'hF0004400F0FF44FF;
LUT4 desc481(.I0(inf_abs0_2[19:19]),.I1(inf_abs0_2[31:31]),.I2(un11_reg0_s_2),.I3(un32_reg0_s_2),.O(N_1369));
defparam desc481.INIT=16'hF2D0;
LUT6_L desc482(.I0(r_4_2_a1_lut6_2_O5[3:3]),.I1(\d_cnst_sn.r_4_0_0 [4:4]),.I2(N_919),.I3(N_527_i),.I4(N_13),.I5(t_1[5:5]),.LO(t_6[5:5]));
defparam desc482.INIT=64'hF0004400F0FF44FF;
LUT6_L desc483(.I0(r_4_2_a1_lut6_2_O5[3:3]),.I1(\d_cnst_sn.r_4_0_0 [4:4]),.I2(N_919),.I3(N_527_i),.I4(N_13),.I5(t_1[5:5]),.LO(r_4_2_a1_lut6_2_RNI5V8R3[3:3]));
defparam desc483.INIT=64'h0FFFBBFF0F00BB00;
LUT6_L desc484(.I0(reg1[19:19]),.I1(reg0[19:19]),.I2(reg2[19:19]),.I3(un3_reg3_s_16),.I4(inf_abs0_2[29:29]),.I5(inf_abs0_2[30:30]),.LO(N_2724));
defparam desc484.INIT=64'hFF00F0F0AAAACCCC;
LUT6_L desc485(.I0(r_4_2_a1_lut6_2_O6[3:3]),.I1(\d_cnst_sn.r_4_0_0 [3:3]),.I2(N_918),.I3(N_527_i),.I4(N_13),.I5(t_1[4:4]),.LO(t_6[4:4]));
defparam desc485.INIT=64'hF0004400F0FF44FF;
LUT6_L desc486(.I0(r_4_2_a1_lut6_2_O6[3:3]),.I1(\d_cnst_sn.r_4_0_0 [3:3]),.I2(N_918),.I3(N_527_i),.I4(N_13),.I5(t_1[4:4]),.LO(r_4_2_a1_lut6_2_RNI2T8R3[3:3]));
defparam desc486.INIT=64'h0FFFBBFF0F00BB00;
LUT6 desc487(.I0(inf_abs0_2[19:19]),.I1(inf_abs0_2[20:20]),.I2(inf_abs0_2[21:21]),.I3(inf_abs0_2[31:31]),.I4(un32_reg0_s_8),.I5(un11_reg0_s_8),.O(N_1043));
defparam desc487.INIT=64'hFFFFFF3500CA0000;
LUT6 un11_r_df20_cZ(.I0(N_967),.I1(N_935),.I2(m_2[20:20]),.I3(m_2[21:21]),.I4(N_13),.I5(r_4[21:21]),.O(un11_r_df20));
defparam un11_r_df20_cZ.INIT=64'hC300A50000C300A5;
LUT6 un11_r_lt20_cZ(.I0(N_967),.I1(N_935),.I2(m_2[20:20]),.I3(m_2[21:21]),.I4(N_13),.I5(r_4[21:21]),.O(un11_r_lt20));
defparam un11_r_lt20_cZ.INIT=64'h30005000FF30FF50;
LUT6 un26_r_df20_cZ(.I0(N_967),.I1(N_935),.I2(m_2[20:20]),.I3(m_2[21:21]),.I4(N_13),.I5(r_4[21:21]),.O(un26_r_df20));
defparam un26_r_df20_cZ.INIT=64'hC300A50000C300A5;
LUT6 un26_r_lt20_cZ(.I0(N_967),.I1(N_935),.I2(m_2[20:20]),.I3(m_2[21:21]),.I4(N_13),.I5(r_4[21:21]),.O(un26_r_lt20));
defparam un26_r_lt20_cZ.INIT=64'h30005000FF30FF50;
LUT6 b18_df20_cZ(.I0(N_967),.I1(N_935),.I2(m_2[20:20]),.I3(m_2[21:21]),.I4(N_13),.I5(r_4[21:21]),.O(b18_df20));
defparam b18_df20_cZ.INIT=64'hC300A50000C300A5;
LUT6 b18_lt20_cZ(.I0(N_967),.I1(N_935),.I2(m_2[20:20]),.I3(m_2[21:21]),.I4(N_13),.I5(r_4[21:21]),.O(b18_lt20));
defparam b18_lt20_cZ.INIT=64'h0CFF0AFF000C000A;
LUT4 desc488(.I0(inf_abs0_2[19:19]),.I1(inf_abs0_2[31:31]),.I2(un32_reg0_s_12),.I3(un11_reg0_s_12),.O(N_1379));
defparam desc488.INIT=16'hFD20;
LUT6_L desc489(.I0(N_513_i),.I1(m_2[0:0]),.I2(N_527_i),.I3(N_3916),.I4(N_1035),.I5(t_1[0:0]),.LO(reg1_16[0:0]));
defparam desc489.INIT=64'h0044FF44004EFF4E;
LUT6_L desc490(.I0(N_513_i),.I1(m_2[0:0]),.I2(N_527_i),.I3(N_3916),.I4(N_1035),.I5(t_1[0:0]),.LO(reg0_28[0:0]));
defparam desc490.INIT=64'h0044FF44004EFF4E;
LUT4 desc491(.I0(inf_abs0_2[20:20]),.I1(inf_abs0_2[31:31]),.I2(un32_reg0_s_15),.I3(un11_reg0_s_15),.O(N_1574));
defparam desc491.INIT=16'hFD20;
LUT6 desc492(.I0(inf_abs0_2[19:19]),.I1(inf_abs0_2[20:20]),.I2(inf_abs0_2[21:21]),.I3(inf_abs0_2[31:31]),.I4(un32_reg0_s_7),.I5(un11_reg0_s_7),.O(N_1042));
defparam desc492.INIT=64'hFFFFFF3500CA0000;
LUT6 desc493(.I0(inf_abs0_2[19:19]),.I1(inf_abs0_2[20:20]),.I2(inf_abs0_2[21:21]),.I3(inf_abs0_2[31:31]),.I4(un32_reg0_s_11),.I5(un11_reg0_s_11),.O(N_1046));
defparam desc493.INIT=64'hFFFFFF3500CA0000;
LUT4 desc494(.I0(inf_abs0_2[19:19]),.I1(inf_abs0_2[31:31]),.I2(un32_reg0_s_13),.I3(un11_reg0_s_13),.O(N_1380));
defparam desc494.INIT=16'hFD20;
LUT6 desc495(.I0(inf_abs0_2[19:19]),.I1(inf_abs0_2[20:20]),.I2(inf_abs0_2[21:21]),.I3(inf_abs0_2[31:31]),.I4(un32_reg0_s_13),.I5(un11_reg0_s_13),.O(N_1048));
defparam desc495.INIT=64'hFFFFFF3500CA0000;
LUT4 desc496(.I0(inf_abs0_2[19:19]),.I1(inf_abs0_2[31:31]),.I2(un32_reg0_s_11),.I3(un11_reg0_s_11),.O(N_1378));
defparam desc496.INIT=16'hFD20;
LUT4 desc497(.I0(inf_abs0_2[19:19]),.I1(inf_abs0_2[31:31]),.I2(un32_reg0_s_10),.I3(un11_reg0_s_10),.O(N_1377));
defparam desc497.INIT=16'hFD20;
LUT4 desc498(.I0(inf_abs0_2[19:19]),.I1(inf_abs0_2[31:31]),.I2(un32_reg0_s_9),.I3(un11_reg0_s_9),.O(N_1376));
defparam desc498.INIT=16'hFD20;
LUT4 desc499(.I0(inf_abs0_2[19:19]),.I1(inf_abs0_2[31:31]),.I2(un32_reg0_s_6),.I3(un11_reg0_s_6),.O(N_1373));
defparam desc499.INIT=16'hFD20;
LUT4 desc500(.I0(inf_abs0_2[19:19]),.I1(inf_abs0_2[31:31]),.I2(un32_reg0_s_3),.I3(un11_reg0_s_3),.O(N_1370));
defparam desc500.INIT=16'hFD20;
LUT4 desc501(.I0(inf_abs0_2[19:19]),.I1(inf_abs0_2[31:31]),.I2(un11_reg0_s_1),.I3(un32_reg0_s_1),.O(N_1368));
defparam desc501.INIT=16'hF2D0;
LUT6 un11_r_df28_cZ(.I0(N_943),.I1(N_975),.I2(m_2[29:29]),.I3(m_2[28:28]),.I4(N_13),.I5(r_4[29:29]),.O(un11_r_df28));
defparam un11_r_df28_cZ.INIT=64'hA050C0300A050C03;
LUT6 un11_r_lt28_cZ(.I0(N_943),.I1(N_975),.I2(m_2[29:29]),.I3(m_2[28:28]),.I4(N_13),.I5(r_4[29:29]),.O(un11_r_lt28));
defparam un11_r_lt28_cZ.INIT=64'h50003000F5F0F3F0;
LUT6 un26_r_df28_cZ(.I0(N_943),.I1(N_975),.I2(m_2[29:29]),.I3(m_2[28:28]),.I4(N_13),.I5(r_4[29:29]),.O(un26_r_df28));
defparam un26_r_df28_cZ.INIT=64'hA050C0300A050C03;
LUT6 un26_r_lt28_cZ(.I0(N_943),.I1(N_975),.I2(m_2[29:29]),.I3(m_2[28:28]),.I4(N_13),.I5(r_4[29:29]),.O(un26_r_lt28));
defparam un26_r_lt28_cZ.INIT=64'h50003000F5F0F3F0;
LUT6 b18_df28_cZ(.I0(N_943),.I1(N_975),.I2(m_2[29:29]),.I3(m_2[28:28]),.I4(N_13),.I5(r_4[29:29]),.O(b18_df28));
defparam b18_df28_cZ.INIT=64'hA050C0300A050C03;
LUT6 b18_lt28_cZ(.I0(N_943),.I1(N_975),.I2(m_2[29:29]),.I3(m_2[28:28]),.I4(N_13),.I5(r_4[29:29]),.O(b18_lt28));
defparam b18_lt28_cZ.INIT=64'h0FAF0FCF000A000C;
LUT6 un11_r_df26_cZ(.I0(N_941),.I1(N_973),.I2(m_2[26:26]),.I3(m_2[27:27]),.I4(N_13),.I5(r_4[27:27]),.O(un11_r_df26));
defparam un11_r_df26_cZ.INIT=64'hA500C30000A500C3;
LUT6 un11_r_lt26_cZ(.I0(N_941),.I1(N_973),.I2(m_2[26:26]),.I3(m_2[27:27]),.I4(N_13),.I5(r_4[27:27]),.O(un11_r_lt26));
defparam un11_r_lt26_cZ.INIT=64'h50003000FF50FF30;
LUT6 b18_df26_cZ(.I0(N_941),.I1(N_973),.I2(m_2[26:26]),.I3(m_2[27:27]),.I4(N_13),.I5(r_4[27:27]),.O(b18_df26));
defparam b18_df26_cZ.INIT=64'hA500C30000A500C3;
LUT6 un26_r_df26_cZ(.I0(N_941),.I1(N_973),.I2(m_2[26:26]),.I3(m_2[27:27]),.I4(N_13),.I5(r_4[27:27]),.O(un26_r_df26));
defparam un26_r_df26_cZ.INIT=64'hA500C30000A500C3;
LUT6 un26_r_lt26_cZ(.I0(N_941),.I1(N_973),.I2(m_2[26:26]),.I3(m_2[27:27]),.I4(N_13),.I5(r_4[27:27]),.O(un26_r_lt26));
defparam un26_r_lt26_cZ.INIT=64'h50003000FF50FF30;
LUT6 b18_lt26_cZ(.I0(N_941),.I1(N_973),.I2(m_2[26:26]),.I3(m_2[27:27]),.I4(N_13),.I5(r_4[27:27]),.O(b18_lt26));
defparam b18_lt26_cZ.INIT=64'h0AFF0CFF000A000C;
LUT6 un11_r_lt24_cZ(.I0(N_940),.I1(N_972),.I2(m_2[24:24]),.I3(m_2[25:25]),.I4(N_13),.I5(r_4[24:24]),.O(un11_r_lt24));
defparam un11_r_lt24_cZ.INIT=64'h55003300F550F330;
LUT6 un11_r_df24_cZ(.I0(N_940),.I1(N_972),.I2(m_2[24:24]),.I3(m_2[25:25]),.I4(N_13),.I5(r_4[24:24]),.O(un11_r_df24));
defparam un11_r_df24_cZ.INIT=64'hA050C0300A050C03;
LUT6 b18_df24_cZ(.I0(N_940),.I1(N_972),.I2(m_2[24:24]),.I3(m_2[25:25]),.I4(N_13),.I5(r_4[24:24]),.O(b18_df24));
defparam b18_df24_cZ.INIT=64'hA050C0300A050C03;
LUT6 b18_lt24_cZ(.I0(N_940),.I1(N_972),.I2(m_2[24:24]),.I3(m_2[25:25]),.I4(N_13),.I5(r_4[24:24]),.O(b18_lt24));
defparam b18_lt24_cZ.INIT=64'h0AAF0CCF00AA00CC;
LUT6 un26_r_df24_cZ(.I0(N_940),.I1(N_972),.I2(m_2[24:24]),.I3(m_2[25:25]),.I4(N_13),.I5(r_4[24:24]),.O(un26_r_df24));
defparam un26_r_df24_cZ.INIT=64'hA050C0300A050C03;
LUT6 un26_r_lt24_cZ(.I0(N_940),.I1(N_972),.I2(m_2[24:24]),.I3(m_2[25:25]),.I4(N_13),.I5(r_4[24:24]),.O(un26_r_lt24));
defparam un26_r_lt24_cZ.INIT=64'h55003300F550F330;
LUT6_L desc502(.I0(r_4_2_a0[0:0]),.I1(\d_cnst_sn.r_4_0_0 [0:0]),.I2(N_915),.I3(N_527_i),.I4(N_13),.I5(t_1[1:1]),.LO(t_6[1:1]));
defparam desc502.INIT=64'hF0004400F0FF44FF;
LUT6 desc503(.I0(inf_abs0_2[19:19]),.I1(inf_abs0_2[20:20]),.I2(inf_abs0_2[21:21]),.I3(inf_abs0_2[31:31]),.I4(un32_reg0_s_9),.I5(un11_reg0_s_9),.O(N_1044));
defparam desc503.INIT=64'hFFFFFF3500CA0000;
LUT6 desc504(.I0(inf_abs0_2[19:19]),.I1(inf_abs0_2[20:20]),.I2(inf_abs0_2[21:21]),.I3(inf_abs0_2[31:31]),.I4(un11_reg0_s_1),.I5(un32_reg0_s_1),.O(N_1036));
defparam desc504.INIT=64'hFFFF00CAFF350000;
LUT6 desc505(.I0(inf_abs0_2[19:19]),.I1(inf_abs0_2[20:20]),.I2(inf_abs0_2[21:21]),.I3(inf_abs0_2[31:31]),.I4(un11_reg0_s_2),.I5(un32_reg0_s_2),.O(N_1037));
defparam desc505.INIT=64'hFFFF00CAFF350000;
LUT6 desc506(.I0(inf_abs0_2[19:19]),.I1(inf_abs0_2[20:20]),.I2(inf_abs0_2[21:21]),.I3(inf_abs0_2[31:31]),.I4(un32_reg0_s_6),.I5(un11_reg0_s_6),.O(N_1041));
defparam desc506.INIT=64'hFFFFFF3500CA0000;
LUT6 desc507(.I0(inf_abs0_2[19:19]),.I1(inf_abs0_2[21:21]),.I2(inf_abs0_2[22:22]),.I3(inf_abs0_2[31:31]),.I4(un32_reg0_s_22),.I5(un11_reg0_s_22),.O(reg2_16_11_a4[22:22]));
defparam desc507.INIT=64'h0000002000100030;
LUT6 desc508(.I0(inf_abs0_2[19:19]),.I1(inf_abs0_2[21:21]),.I2(inf_abs0_2[22:22]),.I3(inf_abs0_2[31:31]),.I4(un32_reg0_s_21),.I5(un11_reg0_s_21),.O(reg2_16_11_a4[21:21]));
defparam desc508.INIT=64'h0000002000100030;
LUT6 desc509(.I0(inf_abs0_2[20:20]),.I1(inf_abs0_2[21:21]),.I2(inf_abs0_2[22:22]),.I3(inf_abs0_2[31:31]),.I4(un32_reg0_s_17),.I5(un11_reg0_s_17),.O(reg2_16_11_a2[17:17]));
defparam desc509.INIT=64'h000000080004000C;
LUT6 desc510(.I0(inf_abs0_2[19:19]),.I1(inf_abs0_2[20:20]),.I2(inf_abs0_2[21:21]),.I3(inf_abs0_2[22:22]),.I4(inf_abs0_2[31:31]),.I5(un32_reg0_s_20),.O(\d_cnst_sn.reg2_16_1 [20:20]));
defparam desc510.INIT=64'hFFFFFFFFFFFFF53F;
LUT4 desc511(.I0(inf_abs0_2[20:20]),.I1(inf_abs0_2[31:31]),.I2(un32_reg0_s_14),.I3(un11_reg0_s_14),.O(N_1573));
defparam desc511.INIT=16'hFD20;
LUT4 desc512(.I0(inf_abs0_2[20:20]),.I1(inf_abs0_2[31:31]),.I2(un32_reg0_s_13),.I3(un11_reg0_s_13),.O(N_1572));
defparam desc512.INIT=16'hFD20;
LUT4 desc513(.I0(inf_abs0_2[20:20]),.I1(inf_abs0_2[31:31]),.I2(un32_reg0_s_12),.I3(un11_reg0_s_12),.O(N_1571));
defparam desc513.INIT=16'hFD20;
LUT4 desc514(.I0(inf_abs0_2[20:20]),.I1(inf_abs0_2[31:31]),.I2(un32_reg0_s_11),.I3(un11_reg0_s_11),.O(N_1570));
defparam desc514.INIT=16'hFD20;
LUT4 desc515(.I0(inf_abs0_2[20:20]),.I1(inf_abs0_2[31:31]),.I2(un32_reg0_s_10),.I3(un11_reg0_s_10),.O(N_1569));
defparam desc515.INIT=16'hFD20;
LUT5 desc516(.I0(state),.I1(inf_abs0_2[27:27]),.I2(inf_abs0_2[28:28]),.I3(un1_inf_abs0_10[7:7]),.I4(un1_inf_abs0_11[7:7]),.O(\d_cnst_sn.addr_20_iv_14_443_i_2 ));
defparam desc516.INIT=32'h008022A2;
LUT4 desc517(.I0(inf_abs0_2[19:19]),.I1(inf_abs0_2[31:31]),.I2(un32_reg0_s_15),.I3(un11_reg0_s_15),.O(N_1382));
defparam desc517.INIT=16'hFD20;
LUT6 desc518(.I0(inf_abs0_2[19:19]),.I1(inf_abs0_2[21:21]),.I2(inf_abs0_2[22:22]),.I3(inf_abs0_2[31:31]),.I4(un32_reg0_s_25),.I5(un11_reg0_s_25),.O(reg2_16_11_a4[25:25]));
defparam desc518.INIT=64'h0000002000100030;
LUT4 desc519(.I0(inf_abs0_2[19:19]),.I1(inf_abs0_2[31:31]),.I2(un32_reg0_s_5),.I3(un11_reg0_s_5),.O(N_1372));
defparam desc519.INIT=16'hFD20;
LUT6 desc520(.I0(inf_abs0_2[19:19]),.I1(inf_abs0_2[20:20]),.I2(inf_abs0_2[21:21]),.I3(inf_abs0_2[31:31]),.I4(un32_reg0_s_16),.I5(un11_reg0_s_16),.O(N_1051));
defparam desc520.INIT=64'hFFFFFF3500CA0000;
LUT4 desc521(.I0(inf_abs0_2[19:19]),.I1(inf_abs0_2[31:31]),.I2(un32_reg0_s_4),.I3(un11_reg0_s_4),.O(N_1371));
defparam desc521.INIT=16'hFD20;
LUT6 desc522(.I0(inf_abs0_2[19:19]),.I1(inf_abs0_2[20:20]),.I2(inf_abs0_2[21:21]),.I3(inf_abs0_2[31:31]),.I4(un32_reg0_s_15),.I5(un11_reg0_s_15),.O(N_1050));
defparam desc522.INIT=64'hFFFFFF3500CA0000;
LUT6 desc523(.I0(inf_abs0_2[19:19]),.I1(inf_abs0_2[20:20]),.I2(inf_abs0_2[21:21]),.I3(inf_abs0_2[31:31]),.I4(un32_reg0_s_17),.I5(un11_reg0_s_17),.O(N_1052));
defparam desc523.INIT=64'hFFFFFF3500CA0000;
LUT4 desc524(.I0(inf_abs0_2[19:19]),.I1(inf_abs0_2[31:31]),.I2(un32_reg0_s_16),.I3(un11_reg0_s_16),.O(N_1383));
defparam desc524.INIT=16'hFD20;
LUT6 desc525(.I0(inf_abs0_2[19:19]),.I1(inf_abs0_2[21:21]),.I2(inf_abs0_2[22:22]),.I3(inf_abs0_2[31:31]),.I4(un32_reg0_s_29),.I5(un11_reg0_s_29),.O(reg2_16_11_a3[29:29]));
defparam desc525.INIT=64'h0030001000200000;
LUT6 desc526(.I0(inf_abs0_2[19:19]),.I1(inf_abs0_2[21:21]),.I2(inf_abs0_2[22:22]),.I3(inf_abs0_2[31:31]),.I4(un32_reg0_s_24),.I5(un11_reg0_s_24),.O(reg2_16_11_a4[24:24]));
defparam desc526.INIT=64'h0000002000100030;
LUT6 desc527(.I0(inf_abs0_2[20:20]),.I1(inf_abs0_2[21:21]),.I2(inf_abs0_2[22:22]),.I3(inf_abs0_2[31:31]),.I4(un32_reg0_s_18),.I5(un11_reg0_s_18),.O(reg2_16_11_a2[18:18]));
defparam desc527.INIT=64'h000000080004000C;
LUT4 desc528(.I0(inf_abs0_2[20:20]),.I1(inf_abs0_2[31:31]),.I2(un32_reg0_s_5),.I3(un11_reg0_s_5),.O(N_1564));
defparam desc528.INIT=16'hFD20;
LUT6 desc529(.I0(inf_abs0_2[19:19]),.I1(inf_abs0_2[20:20]),.I2(inf_abs0_2[21:21]),.I3(inf_abs0_2[31:31]),.I4(un32_reg0_s_10),.I5(un11_reg0_s_10),.O(N_1045));
defparam desc529.INIT=64'hFFFFFF3500CA0000;
LUT6 desc530(.I0(inf_abs0_2[19:19]),.I1(inf_abs0_2[20:20]),.I2(inf_abs0_2[21:21]),.I3(inf_abs0_2[31:31]),.I4(un32_reg0_s_14),.I5(un11_reg0_s_14),.O(N_1049));
defparam desc530.INIT=64'hFFFFFF3500CA0000;
LUT4 desc531(.I0(inf_abs0_2[20:20]),.I1(inf_abs0_2[31:31]),.I2(un32_reg0_s_9),.I3(un11_reg0_s_9),.O(N_1568));
defparam desc531.INIT=16'hFD20;
LUT6 desc532(.I0(inf_abs0_2[20:20]),.I1(inf_abs0_2[21:21]),.I2(inf_abs0_2[22:22]),.I3(inf_abs0_2[31:31]),.I4(un32_reg0_s_19),.I5(un11_reg0_s_19),.O(reg2_16_11_a2[19:19]));
defparam desc532.INIT=64'h000000080004000C;
LUT6 desc533(.I0(inf_abs0_2[19:19]),.I1(inf_abs0_2[20:20]),.I2(inf_abs0_2[21:21]),.I3(inf_abs0_2[31:31]),.I4(un32_reg0_s_4),.I5(un11_reg0_s_4),.O(N_1039));
defparam desc533.INIT=64'hFFFFFF3500CA0000;
LUT6 desc534(.I0(inf_abs0_2[19:19]),.I1(inf_abs0_2[20:20]),.I2(inf_abs0_2[21:21]),.I3(inf_abs0_2[31:31]),.I4(un32_reg0_s_18),.I5(un11_reg0_s_18),.O(N_1053));
defparam desc534.INIT=64'hFFFFFF3500CA0000;
LUT4 desc535(.I0(inf_abs0_2[20:20]),.I1(inf_abs0_2[31:31]),.I2(un32_reg0_s_6),.I3(un11_reg0_s_6),.O(N_1565));
defparam desc535.INIT=16'hFD20;
LUT4 desc536(.I0(inf_abs0_2[19:19]),.I1(inf_abs0_2[31:31]),.I2(un32_reg0_s_7),.I3(un11_reg0_s_7),.O(N_1374));
defparam desc536.INIT=16'hFD20;
LUT4 desc537(.I0(inf_abs0_2[20:20]),.I1(inf_abs0_2[31:31]),.I2(un32_reg0_s_8),.I3(un11_reg0_s_8),.O(N_1567));
defparam desc537.INIT=16'hFD20;
LUT6 desc538(.I0(inf_abs0_2[19:19]),.I1(inf_abs0_2[21:21]),.I2(inf_abs0_2[22:22]),.I3(inf_abs0_2[31:31]),.I4(un32_reg0_s_23),.I5(un11_reg0_s_23),.O(reg2_16_11_a4[23:23]));
defparam desc538.INIT=64'h0000002000100030;
LUT6 desc539(.I0(inf_abs0_2[19:19]),.I1(inf_abs0_2[20:20]),.I2(inf_abs0_2[21:21]),.I3(inf_abs0_2[31:31]),.I4(un32_reg0_s_5),.I5(un11_reg0_s_5),.O(N_1040));
defparam desc539.INIT=64'hFFFFFF3500CA0000;
LUT6 desc540(.I0(inf_abs0_2[19:19]),.I1(inf_abs0_2[20:20]),.I2(inf_abs0_2[21:21]),.I3(inf_abs0_2[31:31]),.I4(un32_reg0_s_3),.I5(un11_reg0_s_3),.O(N_1038));
defparam desc540.INIT=64'hFFFFFF3500CA0000;
LUT6 desc541(.I0(inf_abs0_2[19:19]),.I1(inf_abs0_2[20:20]),.I2(inf_abs0_2[21:21]),.I3(inf_abs0_2[31:31]),.I4(un32_reg0_s_12),.I5(un11_reg0_s_12),.O(N_1047));
defparam desc541.INIT=64'hFFFFFF3500CA0000;
LUT4 desc542(.I0(inf_abs0_2[20:20]),.I1(inf_abs0_2[21:21]),.I2(inf_abs0_2[22:22]),.I3(reg3_1_1[27:27]),.O(\d_cnst_sn.reg0_28_11_2228_a6_1_1 ));
defparam desc542.INIT=16'h0100;
LUT4 desc543(.I0(inf_abs0_2[20:20]),.I1(inf_abs0_2[31:31]),.I2(un11_reg0_s_2),.I3(un32_reg0_s_2),.O(N_1561));
defparam desc543.INIT=16'hF2D0;
LUT4 desc544(.I0(inf_abs0_2[20:20]),.I1(inf_abs0_2[31:31]),.I2(un32_reg0_s_25),.I3(un11_reg0_s_25),.O(N_1584));
defparam desc544.INIT=16'hFD20;
LUT4 desc545(.I0(inf_abs0_2[20:20]),.I1(inf_abs0_2[31:31]),.I2(un32_reg0_s_4),.I3(un11_reg0_s_4),.O(N_1563));
defparam desc545.INIT=16'hFD20;
LUT4 desc546(.I0(inf_abs0_2[20:20]),.I1(inf_abs0_2[31:31]),.I2(un32_reg0_s_7),.I3(un11_reg0_s_7),.O(N_1566));
defparam desc546.INIT=16'hFD20;
LUT4 desc547(.I0(inf_abs0_2[20:20]),.I1(inf_abs0_2[31:31]),.I2(un32_reg0_s_3),.I3(un11_reg0_s_3),.O(N_1562));
defparam desc547.INIT=16'hFD20;
LUT6 desc548(.I0(datai[20:20]),.I1(un3_reg3_s_17),.I2(inf_abs0_2[20:20]),.I3(inf_abs0_2[31:31]),.I4(inf_abs0_2[27:27]),.I5(inf_abs0_2[28:28]),.O(reg2_16_2_d[20:20]));
defparam desc548.INIT=64'hCCACCCACCCACCC0C;
LUT4 desc549(.I0(inf_abs0_2[20:20]),.I1(inf_abs0_2[31:31]),.I2(un11_reg0_s_1),.I3(un32_reg0_s_1),.O(N_1560));
defparam desc549.INIT=16'hF2D0;
LUT6_L desc550(.I0(inf_abs0_2[31:31]),.I1(inf_abs0_2[28:28]),.I2(inf_abs0_2[29:29]),.I3(N_921),.I4(N_953),.I5(t_1[7:7]),.LO(t_6[7:7]));
defparam desc550.INIT=64'h44400400FFFBBFBB;
LUT6_L desc551(.I0(inf_abs0_2[31:31]),.I1(inf_abs0_2[28:28]),.I2(inf_abs0_2[29:29]),.I3(N_920),.I4(N_952),.I5(t_1[6:6]),.LO(t_6[6:6]));
defparam desc551.INIT=64'h44400400FFFBBFBB;
LUT6_L desc552(.I0(inf_abs0_2[31:31]),.I1(inf_abs0_2[28:28]),.I2(inf_abs0_2[29:29]),.I3(N_927),.I4(N_959),.I5(t_1[13:13]),.LO(t_6[13:13]));
defparam desc552.INIT=64'h44400400FFFBBFBB;
LUT6_L desc553(.I0(inf_abs0_2[31:31]),.I1(inf_abs0_2[28:28]),.I2(inf_abs0_2[29:29]),.I3(N_929),.I4(N_961),.I5(t_1[15:15]),.LO(t_6[15:15]));
defparam desc553.INIT=64'h44400400FFFBBFBB;
LUT6_L desc554(.I0(inf_abs0_2[31:31]),.I1(inf_abs0_2[28:28]),.I2(inf_abs0_2[29:29]),.I3(N_930),.I4(N_962),.I5(t_1[16:16]),.LO(t_6[16:16]));
defparam desc554.INIT=64'h44400400FFFBBFBB;
LUT6_L desc555(.I0(inf_abs0_2[31:31]),.I1(inf_abs0_2[28:28]),.I2(inf_abs0_2[29:29]),.I3(N_928),.I4(N_960),.I5(t_1[14:14]),.LO(t_6[14:14]));
defparam desc555.INIT=64'h44400400FFFBBFBB;
LUT5 desc556(.I0(inf_abs0_2[31:31]),.I1(inf_abs0_2[28:28]),.I2(inf_abs0_2[29:29]),.I3(N_934),.I4(N_2722),.O(\d_cnst_sn.reg3_17_4_a2_0 [20:20]));
defparam desc556.INIT=32'h44400400;
LUT6_L desc557(.I0(N_513_i),.I1(N_514_i),.I2(N_527_i),.I3(N_1335),.I4(N_1035),.I5(t_1[0:0]),.LO(reg2_16[0:0]));
defparam desc557.INIT=64'h1100776619087F6E;
LUT6_L desc558(.I0(inf_abs0_2[31:31]),.I1(inf_abs0_2[28:28]),.I2(inf_abs0_2[29:29]),.I3(N_923),.I4(N_955),.I5(t_1[9:9]),.LO(r_4_1_RNIIQ731[8:8]));
defparam desc558.INIT=64'hBBBFFBFF00044044;
LUT6_L desc559(.I0(inf_abs0_2[31:31]),.I1(inf_abs0_2[28:28]),.I2(inf_abs0_2[29:29]),.I3(N_925),.I4(N_957),.I5(t_1[11:11]),.LO(t_6[11:11]));
defparam desc559.INIT=64'h44400400FFFBBFBB;
LUT6_L desc560(.I0(inf_abs0_2[31:31]),.I1(inf_abs0_2[28:28]),.I2(inf_abs0_2[29:29]),.I3(N_926),.I4(N_958),.I5(t_1[12:12]),.LO(t_6[12:12]));
defparam desc560.INIT=64'h44400400FFFBBFBB;
LUT6_L desc561(.I0(inf_abs0_2[31:31]),.I1(inf_abs0_2[28:28]),.I2(inf_abs0_2[29:29]),.I3(N_920),.I4(N_952),.I5(t_1[6:6]),.LO(r_4_1_RNI9K731[5:5]));
defparam desc561.INIT=64'hBBBFFBFF00044044;
LUT6_L desc562(.I0(inf_abs0_2[31:31]),.I1(inf_abs0_2[28:28]),.I2(inf_abs0_2[29:29]),.I3(N_921),.I4(N_953),.I5(t_1[7:7]),.LO(r_4_1_RNICM731[6:6]));
defparam desc562.INIT=64'hBBBFFBFF00044044;
LUT6_L desc563(.I0(inf_abs0_2[31:31]),.I1(inf_abs0_2[28:28]),.I2(inf_abs0_2[29:29]),.I3(N_925),.I4(N_957),.I5(t_1[11:11]),.LO(r_4_1_RNIDBOH1[10:10]));
defparam desc563.INIT=64'hBBBFFBFF00044044;
LUT6_L desc564(.I0(inf_abs0_2[31:31]),.I1(inf_abs0_2[28:28]),.I2(inf_abs0_2[29:29]),.I3(N_924),.I4(N_956),.I5(t_1[10:10]),.LO(r_4_1_RNIS3K91[9:9]));
defparam desc564.INIT=64'hBBBFFBFF00044044;
LUT6_L desc565(.I0(inf_abs0_2[31:31]),.I1(inf_abs0_2[28:28]),.I2(inf_abs0_2[29:29]),.I3(N_922),.I4(N_954),.I5(t_1[8:8]),.LO(r_4_1_RNIFO731[7:7]));
defparam desc565.INIT=64'hBBBFFBFF00044044;
LUT6 desc566(.I0(inf_abs0_2[21:21]),.I1(inf_abs0_2[31:31]),.I2(inf_abs0_2[28:28]),.I3(inf_abs0_2[29:29]),.I4(N_931),.I5(N_963),.O(reg0_28_7_a1[17:17]));
defparam desc566.INIT=64'h0000002020002020;
LUT6_L desc567(.I0(inf_abs0_2[31:31]),.I1(inf_abs0_2[28:28]),.I2(inf_abs0_2[29:29]),.I3(N_922),.I4(N_954),.I5(t_1[8:8]),.LO(t_6[8:8]));
defparam desc567.INIT=64'h44400400FFFBBFBB;
LUT6_L desc568(.I0(inf_abs0_2[31:31]),.I1(inf_abs0_2[28:28]),.I2(inf_abs0_2[29:29]),.I3(N_923),.I4(N_955),.I5(t_1[9:9]),.LO(t_6[9:9]));
defparam desc568.INIT=64'h44400400FFFBBFBB;
LUT6 desc569(.I0(inf_abs0_2[21:21]),.I1(inf_abs0_2[31:31]),.I2(inf_abs0_2[28:28]),.I3(inf_abs0_2[29:29]),.I4(N_932),.I5(N_964),.O(reg0_28_7_a1[18:18]));
defparam desc569.INIT=64'h0000002020002020;
LUT6_L desc570(.I0(inf_abs0_2[31:31]),.I1(inf_abs0_2[28:28]),.I2(inf_abs0_2[29:29]),.I3(N_924),.I4(N_956),.I5(t_1[10:10]),.LO(t_6[10:10]));
defparam desc570.INIT=64'h44400400FFFBBFBB;
LUT6_L desc571(.I0(N_7_i),.I1(un36_df),.I2(un1_b59),.I3(un87_df),.I4(un32_reg0_s_23),.I5(un11_reg0_s_23),.LO(N_1742));
defparam desc571.INIT=64'hFFFFEFFF10000000;
LUT6_L desc572(.I0(N_7_i),.I1(un36_df),.I2(un1_b59),.I3(un87_df),.I4(un32_reg0_s_24),.I5(un11_reg0_s_24),.LO(N_1743));
defparam desc572.INIT=64'hFFFFEFFF10000000;
LUT6_L desc573(.I0(inf_abs0_2[21:21]),.I1(inf_abs0_2[31:31]),.I2(inf_abs0_2[28:28]),.I3(r_4[17:17]),.I4(reg3_1_1[18:18]),.I5(t_1[18:18]),.LO(N_1085));
defparam desc573.INIT=64'hFDDD2000FFDF2202;
LUT6 desc574(.I0(N_7_i),.I1(un36_df),.I2(un1_b59),.I3(un87_df),.I4(un32_reg0_s_13),.I5(un11_reg0_s_13),.O(N_1732));
defparam desc574.INIT=64'hFFFFEFFF10000000;
LUT6_L desc575(.I0(inf_abs0_2[21:21]),.I1(inf_abs0_2[31:31]),.I2(inf_abs0_2[28:28]),.I3(r_4[16:16]),.I4(reg3_1_1[17:17]),.I5(t_1[17:17]),.LO(N_1084));
defparam desc575.INIT=64'hFDDD2000FFDF2202;
LUT5 desc576(.I0(datai[0:0]),.I1(m_2[0:0]),.I2(N_1035),.I3(un1_cf),.I4(N_1810),.O(N_1812));
defparam desc576.INIT=32'hCCAA0F0F;
LUT6_L desc577(.I0(N_7_i),.I1(un36_df),.I2(un1_b59),.I3(un87_df),.I4(un32_reg0_s_22),.I5(un11_reg0_s_22),.LO(N_1741));
defparam desc577.INIT=64'hFFFFEFFF10000000;
LUT6_L desc578(.I0(N_7_i),.I1(un36_df),.I2(un1_b59),.I3(un87_df),.I4(un32_reg0_s_21),.I5(un11_reg0_s_21),.LO(N_1740));
defparam desc578.INIT=64'hFFFFEFFF10000000;
MUXCY_L un3_t_cry_0_cy_cZ(.DI(GND),.CI(VCC),.S(r_4_3_ci[31:31]),.LO(un3_t_cry_0_cy));
LUT6 desc579(.I0(reg0[31:31]),.I1(reg1[31:31]),.I2(reg2[31:31]),.I3(inf_abs0_2[31:31]),.I4(inf_abs0_2[29:29]),.I5(inf_abs0_2[30:30]),.O(r_4_3_ci[31:31]));
defparam desc579.INIT=64'hAA00AAF0AACCAAAA;
MUXCY_L t_1_cry_0_cy_cZ(.DI(GND),.CI(VCC),.S(r_4_i[31:31]),.LO(t_1_cry_0_cy));
LUT5 desc580(.I0(reg0[2:2]),.I1(reg2[2:2]),.I2(inf_abs0_2[31:31]),.I3(\d_cnst_sn.m19_0_1 ),.I4(\d_cnst_sn.m26_0_1 ),.O(N_28));
defparam desc580.INIT=32'hACA0AFAA;
LUT5 un3_t_axb_2_cZ(.I0(reg0[2:2]),.I1(reg2[2:2]),.I2(inf_abs0_2[31:31]),.I3(\d_cnst_sn.m19_0_1 ),.I4(\d_cnst_sn.m26_0_1 ),.O(un3_t_axb_2));
defparam un3_t_axb_2_cZ.INIT=32'h535F5055;
LUT5_L desc581(.I0(inf_abs0_2[31:31]),.I1(\d_cnst_sn.reg0_28_14_2135_1_a0_2 ),.I2(reg3_1_1[30:30]),.I3(\d_cnst_sn.reg0_28_14_0 ),.I4(t_1[30:30]),.LO(N_3550));
defparam desc581.INIT=32'hFFA0FFEC;
LUT4 desc582(.I0(m_2[21:21]),.I1(\d_cnst_sn.reg3_17_a2_2_0 [21:21]),.I2(\d_cnst_sn.reg3_17_sn_m7_0 ),.I3(reg3_14_sqmuxa),.O(\d_cnst_sn.reg3_17_0_tz [21:21]));
defparam desc582.INIT=16'hC00A;
LUT5_L desc583(.I0(N_3916),.I1(\d_cnst_sn.reg0_28_7_a0_0 [9:9]),.I2(\d_cnst_sn.reg0_0 [17:17]),.I3(t_1[17:17]),.I4(N_1052),.LO(reg0_28[17:17]));
defparam desc583.INIT=32'hB0F01050;
LUT5_L desc584(.I0(N_3916),.I1(\d_cnst_sn.reg0_28_7_a0_0 [9:9]),.I2(\d_cnst_sn.reg1_0 [18:18]),.I3(t_1[18:18]),.I4(N_1053),.LO(reg1_16[18:18]));
defparam desc584.INIT=32'hB0F01050;
LUT1_L desc585(.I0(state),.LO(state_i));
defparam desc585.INIT=2'h1;
LUT2 un1_inf_abs0_0_s_19_RNO(.I0(reg1[19:19]),.I1(inf_abs0_2[19:19]),.O(un1_inf_abs0_0_axb_19));
defparam un1_inf_abs0_0_s_19_RNO.INIT=4'h6;
LUT2 un1_inf_abs0_s_19_RNO(.I0(reg2[19:19]),.I1(inf_abs0_2[19:19]),.O(un1_inf_abs0_axb_19));
defparam un1_inf_abs0_s_19_RNO.INIT=4'h6;
LUT2 desc586(.I0(inf_abs0_2[31:31]),.I1(inf_abs0_2[30:30]),.O(N_3_0));
defparam desc586.INIT=4'h4;
LUT3_L desc587(.I0(datai[8:8]),.I1(state),.I2(inf_abs0_2[8:8]),.LO(ir_3[8:8]));
defparam desc587.INIT=8'hE2;
LUT3_L desc588(.I0(datai[16:16]),.I1(state),.I2(inf_abs0_2[16:16]),.LO(ir_3[16:16]));
defparam desc588.INIT=8'hE2;
LUT3_L desc589(.I0(datai[3:3]),.I1(state),.I2(inf_abs0_2[3:3]),.LO(ir_3[3:3]));
defparam desc589.INIT=8'hE2;
LUT3_L desc590(.I0(datai[0:0]),.I1(state),.I2(inf_abs0_2[0:0]),.LO(ir_3[0:0]));
defparam desc590.INIT=8'hE2;
LUT3_L desc591(.I0(datai[27:27]),.I1(state),.I2(inf_abs0_2[27:27]),.LO(ir_3[27:27]));
defparam desc591.INIT=8'hE2;
LUT3_L desc592(.I0(datai[23:23]),.I1(state),.I2(inf_abs0_2[23:23]),.LO(ir_3[23:23]));
defparam desc592.INIT=8'hE2;
LUT3_L desc593(.I0(datai[26:26]),.I1(state),.I2(inf_abs0_2[26:26]),.LO(ir_3[26:26]));
defparam desc593.INIT=8'hE2;
LUT3_L desc594(.I0(datai[5:5]),.I1(state),.I2(inf_abs0_2[5:5]),.LO(ir_3[5:5]));
defparam desc594.INIT=8'hE2;
LUT3_L desc595(.I0(datai[2:2]),.I1(state),.I2(inf_abs0_2[2:2]),.LO(ir_3[2:2]));
defparam desc595.INIT=8'hE2;
LUT3_L desc596(.I0(datai[18:18]),.I1(state),.I2(inf_abs0_2[18:18]),.LO(ir_3[18:18]));
defparam desc596.INIT=8'hE2;
LUT3_L desc597(.I0(datai[19:19]),.I1(state),.I2(inf_abs0_2[19:19]),.LO(ir_3[19:19]));
defparam desc597.INIT=8'hE2;
LUT3_L desc598(.I0(datai[10:10]),.I1(state),.I2(inf_abs0_2[10:10]),.LO(ir_3[10:10]));
defparam desc598.INIT=8'hE2;
LUT3_L desc599(.I0(datai[9:9]),.I1(state),.I2(inf_abs0_2[9:9]),.LO(ir_3[9:9]));
defparam desc599.INIT=8'hE2;
LUT3_L desc600(.I0(datai[6:6]),.I1(state),.I2(inf_abs0_2[6:6]),.LO(ir_3[6:6]));
defparam desc600.INIT=8'hE2;
LUT3_L desc601(.I0(datai[4:4]),.I1(state),.I2(inf_abs0_2[4:4]),.LO(ir_3[4:4]));
defparam desc601.INIT=8'hE2;
LUT3_L desc602(.I0(datai[22:22]),.I1(state),.I2(inf_abs0_2[22:22]),.LO(ir_3[22:22]));
defparam desc602.INIT=8'hE2;
LUT3 desc603(.I0(reg1[19:19]),.I1(un3_reg3_s_16),.I2(inf_abs0_2[30:30]),.O(N_2722));
defparam desc603.INIT=8'hCA;
LUT3_L desc604(.I0(datai[21:21]),.I1(state),.I2(inf_abs0_2[21:21]),.LO(ir_3[21:21]));
defparam desc604.INIT=8'hE2;
LUT3_L desc605(.I0(datai[1:1]),.I1(state),.I2(inf_abs0_2[1:1]),.LO(ir_3[1:1]));
defparam desc605.INIT=8'hE2;
LUT3_L desc606(.I0(datai[7:7]),.I1(state),.I2(inf_abs0_2[7:7]),.LO(ir_3[7:7]));
defparam desc606.INIT=8'hE2;
LUT3_L desc607(.I0(datai[25:25]),.I1(state),.I2(inf_abs0_2[25:25]),.LO(ir_3[25:25]));
defparam desc607.INIT=8'hE2;
LUT3_L desc608(.I0(datai[24:24]),.I1(state),.I2(inf_abs0_2[24:24]),.LO(ir_3[24:24]));
defparam desc608.INIT=8'hE2;
LUT3_L desc609(.I0(datai[29:29]),.I1(state),.I2(inf_abs0_2[29:29]),.LO(ir_3[29:29]));
defparam desc609.INIT=8'hE2;
LUT3_L desc610(.I0(datai[11:11]),.I1(state),.I2(inf_abs0_2[11:11]),.LO(ir_3[11:11]));
defparam desc610.INIT=8'hE2;
LUT3 desc611(.I0(reg3[0:0]),.I1(inf_abs0_2[31:31]),.I2(inf_abs0_2[30:30]),.O(r_4_2_a0[0:0]));
defparam desc611.INIT=8'h10;
LUT3 desc612(.I0(reg3[1:1]),.I1(inf_abs0_2[31:31]),.I2(inf_abs0_2[30:30]),.O(r_4_2_a0[1:1]));
defparam desc612.INIT=8'h10;
LUT3 desc613(.I0(reg1[0:0]),.I1(inf_abs0_2[31:31]),.I2(inf_abs0_2[30:30]),.O(\d_cnst_sn.r_4_0_0 [0:0]));
defparam desc613.INIT=8'hBA;
LUT3 desc614(.I0(reg1[1:1]),.I1(inf_abs0_2[31:31]),.I2(inf_abs0_2[30:30]),.O(\d_cnst_sn.r_4_0_0 [1:1]));
defparam desc614.INIT=8'hBA;
LUT3 desc615(.I0(inf_abs0_2[31:31]),.I1(inf_abs0_2[27:27]),.I2(inf_abs0_2[28:28]),.O(m7));
defparam desc615.INIT=8'hAB;
LUT2 inf_abs0_2_axb_30_cZ(.I0(ir[30:30]),.I1(ir[31:31]),.O(inf_abs0_2_axb_30));
defparam inf_abs0_2_axb_30_cZ.INIT=4'h6;
LUT2 desc616(.I0(inf_abs0_2[23:23]),.I1(inf_abs0_2[31:31]),.O(N_7_i));
defparam desc616.INIT=4'h2;
LUT2 desc617(.I0(inf_abs0_2[31:31]),.I1(inf_abs0_2[29:29]),.O(N_13));
defparam desc617.INIT=4'hB;
LUT2 desc618(.I0(inf_abs0_2[22:22]),.I1(inf_abs0_2[31:31]),.O(N_514_i));
defparam desc618.INIT=4'h2;
LUT2 desc619(.I0(inf_abs0_2[21:21]),.I1(inf_abs0_2[31:31]),.O(N_513_i));
defparam desc619.INIT=4'h2;
LUT4 desc620(.I0(reg0[11:11]),.I1(reg2[11:11]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[30:30]),.O(N_926));
defparam desc620.INIT=16'hACAA;
LUT4 desc621(.I0(reg0[26:26]),.I1(reg2[26:26]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[30:30]),.O(N_941));
defparam desc621.INIT=16'hACAA;
LUT4 desc622(.I0(reg1[11:11]),.I1(un3_reg3_s_8),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[30:30]),.O(N_958));
defparam desc622.INIT=16'hACAA;
LUT4 desc623(.I0(reg1[26:26]),.I1(un3_reg3_s_23),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[30:30]),.O(N_973));
defparam desc623.INIT=16'hACAA;
LUT4 desc624(.I0(reg0[28:28]),.I1(reg2[28:28]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[30:30]),.O(N_943));
defparam desc624.INIT=16'hACAA;
LUT4 desc625(.I0(reg1[28:28]),.I1(un3_reg3_s_25),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[30:30]),.O(N_975));
defparam desc625.INIT=16'hACAA;
LUT4 desc626(.I0(reg0[25:25]),.I1(reg2[25:25]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[30:30]),.O(N_940));
defparam desc626.INIT=16'hACAA;
LUT4 desc627(.I0(reg1[25:25]),.I1(un3_reg3_s_22),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[30:30]),.O(N_972));
defparam desc627.INIT=16'hACAA;
LUT4 desc628(.I0(reg0[13:13]),.I1(reg2[13:13]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[30:30]),.O(N_928));
defparam desc628.INIT=16'hACAA;
LUT4 desc629(.I0(reg1[13:13]),.I1(un3_reg3_s_10),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[30:30]),.O(N_960));
defparam desc629.INIT=16'hACAA;
LUT4 desc630(.I0(reg0[16:16]),.I1(reg2[16:16]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[30:30]),.O(N_931));
defparam desc630.INIT=16'hACAA;
LUT4 desc631(.I0(reg1[16:16]),.I1(un3_reg3_s_13),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[30:30]),.O(N_963));
defparam desc631.INIT=16'hACAA;
LUT4 desc632(.I0(reg0[14:14]),.I1(reg2[14:14]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[30:30]),.O(N_929));
defparam desc632.INIT=16'hACAA;
LUT4 desc633(.I0(reg1[14:14]),.I1(un3_reg3_s_11),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[30:30]),.O(N_961));
defparam desc633.INIT=16'hACAA;
LUT4 desc634(.I0(reg0[10:10]),.I1(reg2[10:10]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[30:30]),.O(N_925));
defparam desc634.INIT=16'hACAA;
LUT4 desc635(.I0(reg1[10:10]),.I1(un3_reg3_s_7),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[30:30]),.O(N_957));
defparam desc635.INIT=16'hACAA;
LUT4 desc636(.I0(reg0[9:9]),.I1(reg2[9:9]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[30:30]),.O(N_924));
defparam desc636.INIT=16'hACAA;
LUT4 desc637(.I0(reg1[9:9]),.I1(un3_reg3_s_6),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[30:30]),.O(N_956));
defparam desc637.INIT=16'hACAA;
LUT4 desc638(.I0(reg0[7:7]),.I1(reg2[7:7]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[30:30]),.O(N_922));
defparam desc638.INIT=16'hACAA;
LUT4 desc639(.I0(reg0[8:8]),.I1(reg2[8:8]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[30:30]),.O(N_923));
defparam desc639.INIT=16'hACAA;
LUT4 desc640(.I0(reg1[7:7]),.I1(un3_reg3_s_4),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[30:30]),.O(N_954));
defparam desc640.INIT=16'hACAA;
LUT4 desc641(.I0(reg1[8:8]),.I1(un3_reg3_s_5),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[30:30]),.O(N_955));
defparam desc641.INIT=16'hACAA;
LUT4 desc642(.I0(reg0[21:21]),.I1(reg2[21:21]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[30:30]),.O(N_936));
defparam desc642.INIT=16'hACAA;
LUT4 desc643(.I0(reg1[21:21]),.I1(un3_reg3_s_18),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[30:30]),.O(N_968));
defparam desc643.INIT=16'hACAA;
LUT4 desc644(.I0(reg0[20:20]),.I1(reg2[20:20]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[30:30]),.O(N_935));
defparam desc644.INIT=16'hACAA;
LUT4 desc645(.I0(reg1[20:20]),.I1(un3_reg3_s_17),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[30:30]),.O(N_967));
defparam desc645.INIT=16'hACAA;
LUT4 desc646(.I0(reg0[15:15]),.I1(reg2[15:15]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[30:30]),.O(N_930));
defparam desc646.INIT=16'hACAA;
LUT4 desc647(.I0(reg0[17:17]),.I1(reg2[17:17]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[30:30]),.O(N_932));
defparam desc647.INIT=16'hACAA;
LUT4 desc648(.I0(reg1[15:15]),.I1(un3_reg3_s_12),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[30:30]),.O(N_962));
defparam desc648.INIT=16'hACAA;
LUT4 desc649(.I0(reg1[17:17]),.I1(un3_reg3_s_14),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[30:30]),.O(N_964));
defparam desc649.INIT=16'hACAA;
LUT4 desc650(.I0(reg0[5:5]),.I1(reg2[5:5]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[30:30]),.O(N_920));
defparam desc650.INIT=16'hACAA;
LUT4 desc651(.I0(reg1[5:5]),.I1(un3_reg3_s_2),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[30:30]),.O(N_952));
defparam desc651.INIT=16'hACAA;
LUT4 desc652(.I0(reg0[27:27]),.I1(reg2[27:27]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[30:30]),.O(N_942));
defparam desc652.INIT=16'hACAA;
LUT4 desc653(.I0(reg1[27:27]),.I1(un3_reg3_s_24),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[30:30]),.O(N_974));
defparam desc653.INIT=16'hACAA;
LUT4 desc654(.I0(reg0[18:18]),.I1(reg2[18:18]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[30:30]),.O(N_933));
defparam desc654.INIT=16'hACAA;
LUT4 desc655(.I0(reg1[18:18]),.I1(un3_reg3_s_15),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[30:30]),.O(N_965));
defparam desc655.INIT=16'hACAA;
LUT4 desc656(.I0(reg0[22:22]),.I1(reg2[22:22]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[30:30]),.O(N_937));
defparam desc656.INIT=16'hACAA;
LUT4 desc657(.I0(reg1[22:22]),.I1(un3_reg3_s_19),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[30:30]),.O(N_969));
defparam desc657.INIT=16'hACAA;
LUT4 desc658(.I0(reg0[12:12]),.I1(reg2[12:12]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[30:30]),.O(N_927));
defparam desc658.INIT=16'hACAA;
LUT4 desc659(.I0(reg1[12:12]),.I1(un3_reg3_s_9),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[30:30]),.O(N_959));
defparam desc659.INIT=16'hACAA;
LUT4 desc660(.I0(reg0[6:6]),.I1(reg2[6:6]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[30:30]),.O(N_921));
defparam desc660.INIT=16'hACAA;
LUT4 desc661(.I0(reg1[6:6]),.I1(un3_reg3_s_3),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[30:30]),.O(N_953));
defparam desc661.INIT=16'hACAA;
LUT4 desc662(.I0(reg0[19:19]),.I1(reg2[19:19]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[30:30]),.O(N_934));
defparam desc662.INIT=16'hACAA;
LUT4 desc663(.I0(reg1[23:23]),.I1(un3_reg3_s_20),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[30:30]),.O(N_970));
defparam desc663.INIT=16'hACAA;
LUT4 desc664(.I0(reg0[23:23]),.I1(reg2[23:23]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[30:30]),.O(N_938));
defparam desc664.INIT=16'hACAA;
LUT4 desc665(.I0(reg1[24:24]),.I1(un3_reg3_s_21),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[30:30]),.O(N_971));
defparam desc665.INIT=16'hACAA;
LUT4 desc666(.I0(reg0[24:24]),.I1(reg2[24:24]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[30:30]),.O(N_939));
defparam desc666.INIT=16'hACAA;
LUT4 desc667(.I0(reg1[2:2]),.I1(reg3[2:2]),.I2(inf_abs0_2[29:29]),.I3(inf_abs0_2[30:30]),.O(\d_cnst_sn.m19_0_1 ));
defparam desc667.INIT=16'hCFA0;
LUT4 desc668(.I0(reg1[2:2]),.I1(reg3[2:2]),.I2(inf_abs0_2[29:29]),.I3(inf_abs0_2[30:30]),.O(\d_cnst_sn.m26_0_1 ));
defparam desc668.INIT=16'h3F50;
LUT4 desc669(.I0(reg1[3:3]),.I1(reg3[3:3]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[30:30]),.O(\d_cnst_sn.r_4_0_0 [3:3]));
defparam desc669.INIT=16'hA3AF;
LUT4 desc670(.I0(reg1[4:4]),.I1(un3_reg3_s_1),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[30:30]),.O(\d_cnst_sn.r_4_0_0 [4:4]));
defparam desc670.INIT=16'hACAF;
LUT6 desc671(.I0(m_2[22:22]),.I1(m_2[23:23]),.I2(m_2[21:21]),.I3(r_4[21:21]),.I4(r_4[23:23]),.I5(r_4[22:22]),.O(un14_r_0_N_56));
defparam desc671.INIT=64'h8008200240041001;
LUT5 desc672(.I0(state),.I1(inf_abs0_2[24:24]),.I2(inf_abs0_2[23:23]),.I3(inf_abs0_2[25:25]),.I4(inf_abs0_2[26:26]),.O(N_2641));
defparam desc672.INIT=32'h08000000;
LUT6 desc673(.I0(m_2[24:24]),.I1(m_2[25:25]),.I2(m_2[26:26]),.I3(r_4[24:24]),.I4(r_4[25:25]),.I5(r_4[26:26]),.O(un14_r_0_N_35));
defparam desc673.INIT=64'h8040201008040201;
LUT4 desc674(.I0(reg0[0:0]),.I1(reg2[0:0]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[30:30]),.O(N_915));
defparam desc674.INIT=16'hACAA;
LUT4 desc675(.I0(reg0[1:1]),.I1(reg2[1:1]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[30:30]),.O(N_916));
defparam desc675.INIT=16'hACAA;
LUT6_L desc676(.I0(reg0[29:29]),.I1(reg1[29:29]),.I2(reg2[29:29]),.I3(un3_reg3_cry_25),.I4(inf_abs0_2[29:29]),.I5(inf_abs0_2[30:30]),.LO(r_4_3_6_1508_i_m2));
defparam desc676.INIT=64'hFF00F0F0CCCCAAAA;
LUT6_L desc677(.I0(reg1[28:28]),.I1(reg0[28:28]),.I2(reg2[28:28]),.I3(un3_reg3_s_25),.I4(inf_abs0_2[29:29]),.I5(inf_abs0_2[30:30]),.LO(r_4_3_5_1534_i_m2));
defparam desc677.INIT=64'hFF00F0F0AAAACCCC;
LUT6_L desc678(.I0(reg0[24:24]),.I1(reg2[24:24]),.I2(reg1[24:24]),.I3(un3_reg3_s_21),.I4(inf_abs0_2[29:29]),.I5(inf_abs0_2[30:30]),.LO(r_4_3_1_1638_i_m2));
defparam desc678.INIT=64'hFF00CCCCF0F0AAAA;
LUT6_L desc679(.I0(reg1[16:16]),.I1(reg0[16:16]),.I2(reg2[16:16]),.I3(un3_reg3_s_13),.I4(inf_abs0_2[29:29]),.I5(inf_abs0_2[30:30]),.LO(r_4_3_18_1208_i_m2));
defparam desc679.INIT=64'hFF00F0F0AAAACCCC;
LUT6_L desc680(.I0(reg1[13:13]),.I1(reg0[13:13]),.I2(reg2[13:13]),.I3(un3_reg3_s_10),.I4(inf_abs0_2[29:29]),.I5(inf_abs0_2[30:30]),.LO(r_4_3_15_1286_i_m2));
defparam desc680.INIT=64'hFF00F0F0AAAACCCC;
LUT6_L desc681(.I0(reg1[11:11]),.I1(reg0[11:11]),.I2(reg2[11:11]),.I3(un3_reg3_s_8),.I4(inf_abs0_2[29:29]),.I5(inf_abs0_2[30:30]),.LO(r_4_3_13_1338_i_m2));
defparam desc681.INIT=64'hFF00F0F0AAAACCCC;
LUT6_L desc682(.I0(reg1[17:17]),.I1(reg0[17:17]),.I2(reg2[17:17]),.I3(un3_reg3_s_14),.I4(inf_abs0_2[29:29]),.I5(inf_abs0_2[30:30]),.LO(r_4_3_19_1182_i_m2));
defparam desc682.INIT=64'hFF00F0F0AAAACCCC;
LUT6_L desc683(.I0(reg1[12:12]),.I1(reg0[12:12]),.I2(reg2[12:12]),.I3(un3_reg3_s_9),.I4(inf_abs0_2[29:29]),.I5(inf_abs0_2[30:30]),.LO(r_4_3_14_1312_i_m2));
defparam desc683.INIT=64'hFF00F0F0AAAACCCC;
LUT6_L desc684(.I0(reg1[10:10]),.I1(reg0[10:10]),.I2(reg2[10:10]),.I3(un3_reg3_s_7),.I4(inf_abs0_2[29:29]),.I5(inf_abs0_2[30:30]),.LO(r_4_3_12_1364_i_m2));
defparam desc684.INIT=64'hFF00F0F0AAAACCCC;
LUT6_L desc685(.I0(reg1[26:26]),.I1(reg0[26:26]),.I2(reg2[26:26]),.I3(un3_reg3_s_23),.I4(inf_abs0_2[29:29]),.I5(inf_abs0_2[30:30]),.LO(r_4_3_3_1586_i_m2));
defparam desc685.INIT=64'hFF00F0F0AAAACCCC;
LUT6_L desc686(.I0(reg1[14:14]),.I1(reg0[14:14]),.I2(reg2[14:14]),.I3(un3_reg3_s_11),.I4(inf_abs0_2[29:29]),.I5(inf_abs0_2[30:30]),.LO(r_4_3_16_1260_i_m2));
defparam desc686.INIT=64'hFF00F0F0AAAACCCC;
LUT6_L desc687(.I0(reg1[9:9]),.I1(reg0[9:9]),.I2(reg2[9:9]),.I3(un3_reg3_s_6),.I4(inf_abs0_2[29:29]),.I5(inf_abs0_2[30:30]),.LO(r_4_3_11_1390_i_m2));
defparam desc687.INIT=64'hFF00F0F0AAAACCCC;
LUT6_L desc688(.I0(reg1[6:6]),.I1(reg0[6:6]),.I2(reg2[6:6]),.I3(un3_reg3_s_3),.I4(inf_abs0_2[29:29]),.I5(inf_abs0_2[30:30]),.LO(r_4_3_30_680_i_m2));
defparam desc688.INIT=64'hFF00F0F0AAAACCCC;
LUT6_L desc689(.I0(reg1[8:8]),.I1(reg0[8:8]),.I2(reg2[8:8]),.I3(un3_reg3_s_5),.I4(inf_abs0_2[29:29]),.I5(inf_abs0_2[30:30]),.LO(r_4_3_10_1416_i_m2));
defparam desc689.INIT=64'hFF00F0F0AAAACCCC;
LUT6_L desc690(.I0(reg1[7:7]),.I1(reg0[7:7]),.I2(reg2[7:7]),.I3(un3_reg3_s_4),.I4(inf_abs0_2[29:29]),.I5(inf_abs0_2[30:30]),.LO(r_4_3_9_1442_i_m2));
defparam desc690.INIT=64'hFF00F0F0AAAACCCC;
LUT6_L desc691(.I0(reg0[23:23]),.I1(reg2[23:23]),.I2(reg1[23:23]),.I3(un3_reg3_s_20),.I4(inf_abs0_2[29:29]),.I5(inf_abs0_2[30:30]),.LO(r_4_3_0_1664_i_m2));
defparam desc691.INIT=64'hFF00CCCCF0F0AAAA;
LUT6_L desc692(.I0(reg0[20:20]),.I1(reg2[20:20]),.I2(reg1[20:20]),.I3(un3_reg3_s_17),.I4(inf_abs0_2[29:29]),.I5(inf_abs0_2[30:30]),.LO(r_4_3_22_1104_i_m2));
defparam desc692.INIT=64'hFF00CCCCF0F0AAAA;
LUT6_L desc693(.I0(reg0[1:1]),.I1(reg2[1:1]),.I2(reg1[1:1]),.I3(reg3[1:1]),.I4(inf_abs0_2[29:29]),.I5(inf_abs0_2[30:30]),.LO(r_4_3_25_810_i_m2));
defparam desc693.INIT=64'hFF00CCCCF0F0AAAA;
LUT6_L desc694(.I0(reg1[15:15]),.I1(reg0[15:15]),.I2(reg2[15:15]),.I3(un3_reg3_s_12),.I4(inf_abs0_2[29:29]),.I5(inf_abs0_2[30:30]),.LO(r_4_3_17_1234_i_m2));
defparam desc694.INIT=64'hFF00F0F0AAAACCCC;
LUT6_L desc695(.I0(reg1[5:5]),.I1(reg0[5:5]),.I2(reg2[5:5]),.I3(un3_reg3_s_2),.I4(inf_abs0_2[29:29]),.I5(inf_abs0_2[30:30]),.LO(r_4_3_29_706_i_m2));
defparam desc695.INIT=64'hFF00F0F0AAAACCCC;
LUT6_L desc696(.I0(reg0[0:0]),.I1(reg2[0:0]),.I2(reg1[0:0]),.I3(reg3[0:0]),.I4(inf_abs0_2[29:29]),.I5(inf_abs0_2[30:30]),.LO(r_4_3_24_836_i_m2));
defparam desc696.INIT=64'hFF00CCCCF0F0AAAA;
LUT6_L desc697(.I0(reg0[27:27]),.I1(reg2[27:27]),.I2(reg1[27:27]),.I3(un3_reg3_s_24),.I4(inf_abs0_2[29:29]),.I5(inf_abs0_2[30:30]),.LO(r_4_3_4_1560_i_m2));
defparam desc697.INIT=64'hFF00CCCCF0F0AAAA;
LUT4 desc698(.I0(datai[29:29]),.I1(inf_abs0_2[31:31]),.I2(inf_abs0_2[27:27]),.I3(inf_abs0_2[28:28]),.O(m_2[29:29]));
defparam desc698.INIT=16'h2220;
LUT6_L desc699(.I0(reg1[18:18]),.I1(reg0[18:18]),.I2(reg2[18:18]),.I3(un3_reg3_s_15),.I4(inf_abs0_2[29:29]),.I5(inf_abs0_2[30:30]),.LO(r_4_3_20_1156_i_m2));
defparam desc699.INIT=64'hFF00F0F0AAAACCCC;
LUT6_L desc700(.I0(reg0[22:22]),.I1(reg2[22:22]),.I2(reg1[22:22]),.I3(un3_reg3_s_19),.I4(inf_abs0_2[29:29]),.I5(inf_abs0_2[30:30]),.LO(r_4_3_1690_i_m2));
defparam desc700.INIT=64'hFF00CCCCF0F0AAAA;
LUT6_L desc701(.I0(reg0[4:4]),.I1(reg2[4:4]),.I2(reg1[4:4]),.I3(un3_reg3_s_1),.I4(inf_abs0_2[29:29]),.I5(inf_abs0_2[30:30]),.LO(r_4_3_28_732_i_m2));
defparam desc701.INIT=64'hFF00CCCCF0F0AAAA;
LUT6_L desc702(.I0(reg1[25:25]),.I1(reg0[25:25]),.I2(reg2[25:25]),.I3(un3_reg3_s_22),.I4(inf_abs0_2[29:29]),.I5(inf_abs0_2[30:30]),.LO(r_4_3_2_1612_i_m2));
defparam desc702.INIT=64'hFF00F0F0AAAACCCC;
LUT6_L desc703(.I0(reg1[21:21]),.I1(reg0[21:21]),.I2(reg2[21:21]),.I3(un3_reg3_s_18),.I4(inf_abs0_2[29:29]),.I5(inf_abs0_2[30:30]),.LO(r_4_3_23_1078_i_m2));
defparam desc703.INIT=64'hFF00F0F0AAAACCCC;
LUT6_L desc704(.I0(reg0[3:3]),.I1(reg2[3:3]),.I2(reg1[3:3]),.I3(reg3[3:3]),.I4(inf_abs0_2[29:29]),.I5(inf_abs0_2[30:30]),.LO(r_4_3_27_758_i_m2));
defparam desc704.INIT=64'h00FFCCCCF0F0AAAA;
LUT3 desc705(.I0(inf_abs0_2[19:19]),.I1(inf_abs0_2[20:20]),.I2(inf_abs0_2[31:31]),.O(N_1901));
defparam desc705.INIT=8'h0E;
LUT5 desc706(.I0(datai[5:5]),.I1(inf_abs0_2[5:5]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[27:27]),.I4(inf_abs0_2[28:28]),.O(m_2[5:5]));
defparam desc706.INIT=32'hCACACACC;
LUT5 desc707(.I0(datai[8:8]),.I1(inf_abs0_2[8:8]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[27:27]),.I4(inf_abs0_2[28:28]),.O(m_2[8:8]));
defparam desc707.INIT=32'hCACACACC;
LUT5 desc708(.I0(datai[15:15]),.I1(inf_abs0_2[15:15]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[27:27]),.I4(inf_abs0_2[28:28]),.O(m_2[15:15]));
defparam desc708.INIT=32'hCACACACC;
LUT5 desc709(.I0(datai[16:16]),.I1(inf_abs0_2[16:16]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[27:27]),.I4(inf_abs0_2[28:28]),.O(m_2[16:16]));
defparam desc709.INIT=32'hCACACACC;
LUT5 desc710(.I0(datai[3:3]),.I1(inf_abs0_2[3:3]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[27:27]),.I4(inf_abs0_2[28:28]),.O(m_2[3:3]));
defparam desc710.INIT=32'hCACACACC;
LUT5 desc711(.I0(datai[1:1]),.I1(inf_abs0_2[1:1]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[27:27]),.I4(inf_abs0_2[28:28]),.O(m_2[1:1]));
defparam desc711.INIT=32'hCACACACC;
LUT5_L desc712(.I0(reg0[31:31]),.I1(reg1[31:31]),.I2(reg2[31:31]),.I3(inf_abs0_2[29:29]),.I4(inf_abs0_2[30:30]),.LO(r_4_3_8_1467));
defparam desc712.INIT=32'h00F0CCAA;
LUT5 desc713(.I0(datai[13:13]),.I1(inf_abs0_2[13:13]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[27:27]),.I4(inf_abs0_2[28:28]),.O(m_2[13:13]));
defparam desc713.INIT=32'hCACACACC;
LUT5 desc714(.I0(datai[19:19]),.I1(inf_abs0_2[19:19]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[27:27]),.I4(inf_abs0_2[28:28]),.O(m_2[19:19]));
defparam desc714.INIT=32'hCACACACC;
LUT5 desc715(.I0(datai[14:14]),.I1(inf_abs0_2[14:14]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[27:27]),.I4(inf_abs0_2[28:28]),.O(m_2[14:14]));
defparam desc715.INIT=32'hCACACACC;
LUT5 desc716(.I0(datai[18:18]),.I1(inf_abs0_2[18:18]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[27:27]),.I4(inf_abs0_2[28:28]),.O(m_2[18:18]));
defparam desc716.INIT=32'hCACACACC;
LUT5 desc717(.I0(datai[12:12]),.I1(inf_abs0_2[12:12]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[27:27]),.I4(inf_abs0_2[28:28]),.O(m_2[12:12]));
defparam desc717.INIT=32'hCACACACC;
LUT5 desc718(.I0(datai[17:17]),.I1(inf_abs0_2[17:17]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[27:27]),.I4(inf_abs0_2[28:28]),.O(m_2[17:17]));
defparam desc718.INIT=32'hCACACACC;
LUT5 desc719(.I0(datai[10:10]),.I1(inf_abs0_2[10:10]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[27:27]),.I4(inf_abs0_2[28:28]),.O(m_2[10:10]));
defparam desc719.INIT=32'hCACACACC;
LUT5 desc720(.I0(datai[11:11]),.I1(inf_abs0_2[11:11]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[27:27]),.I4(inf_abs0_2[28:28]),.O(m_2[11:11]));
defparam desc720.INIT=32'hCACACACC;
LUT5 desc721(.I0(datai[9:9]),.I1(inf_abs0_2[9:9]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[27:27]),.I4(inf_abs0_2[28:28]),.O(m_2[9:9]));
defparam desc721.INIT=32'hCACACACC;
LUT5 desc722(.I0(datai[2:2]),.I1(inf_abs0_2[2:2]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[27:27]),.I4(inf_abs0_2[28:28]),.O(m_2[2:2]));
defparam desc722.INIT=32'hCACACACC;
LUT5 desc723(.I0(datai[6:6]),.I1(inf_abs0_2[6:6]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[27:27]),.I4(inf_abs0_2[28:28]),.O(m_2[6:6]));
defparam desc723.INIT=32'hCACACACC;
LUT5 desc724(.I0(datai[7:7]),.I1(inf_abs0_2[7:7]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[27:27]),.I4(inf_abs0_2[28:28]),.O(m_2[7:7]));
defparam desc724.INIT=32'hCACACACC;
LUT5 desc725(.I0(datai[4:4]),.I1(inf_abs0_2[4:4]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[27:27]),.I4(inf_abs0_2[28:28]),.O(m_2[4:4]));
defparam desc725.INIT=32'hCACACACC;
LUT5_L desc726(.I0(reg3[11:11]),.I1(state),.I2(inf_abs0_2[11:11]),.I3(inf_abs0_2[28:28]),.I4(N_2641),.LO(\d_cnst_sn.addr_20_iv_18_335_i_1 ));
defparam desc726.INIT=32'hFFFF111D;
LUT5_L desc727(.I0(reg3[6:6]),.I1(state),.I2(inf_abs0_2[6:6]),.I3(inf_abs0_2[28:28]),.I4(N_2641),.LO(\d_cnst_sn.addr_20_iv_13_470_i_1 ));
defparam desc727.INIT=32'hFFFF111D;
LUT5_L desc728(.I0(reg3[10:10]),.I1(state),.I2(inf_abs0_2[10:10]),.I3(inf_abs0_2[28:28]),.I4(N_2641),.LO(\d_cnst_sn.addr_20_iv_17_362_i_1 ));
defparam desc728.INIT=32'hFFFF111D;
LUT5_L desc729(.I0(reg3[8:8]),.I1(state),.I2(inf_abs0_2[8:8]),.I3(inf_abs0_2[28:28]),.I4(N_2641),.LO(\d_cnst_sn.addr_20_iv_15_416_i_1 ));
defparam desc729.INIT=32'hFFFF111D;
LUT5_L desc730(.I0(reg3[3:3]),.I1(state),.I2(inf_abs0_2[3:3]),.I3(inf_abs0_2[28:28]),.I4(N_2641),.LO(\d_cnst_sn.addr_20_iv_10_562_i_1 ));
defparam desc730.INIT=32'hFFFF111D;
LUT5_L desc731(.I0(reg3[5:5]),.I1(state),.I2(inf_abs0_2[5:5]),.I3(inf_abs0_2[28:28]),.I4(N_2641),.LO(\d_cnst_sn.addr_20_iv_12_497_i_1 ));
defparam desc731.INIT=32'hFFFF111D;
LUT5_L desc732(.I0(reg3[9:9]),.I1(state),.I2(inf_abs0_2[9:9]),.I3(inf_abs0_2[28:28]),.I4(N_2641),.LO(\d_cnst_sn.addr_20_iv_16_389_i_1 ));
defparam desc732.INIT=32'hFFFF111D;
LUT6 desc733(.I0(reg3[1:1]),.I1(state),.I2(inf_abs0_2[1:1]),.I3(un1_inf_abs0_11[1:1]),.I4(inf_abs0_2[27:27]),.I5(inf_abs0_2[28:28]),.O(\d_cnst_sn.addr_20_iv_8_627_i_1 ));
defparam desc733.INIT=64'h111111DD1D1D1DDD;
LUT4 desc734(.I0(reg0[4:4]),.I1(reg2[4:4]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[30:30]),.O(N_919));
defparam desc734.INIT=16'hACAA;
LUT4 desc735(.I0(reg0[3:3]),.I1(reg2[3:3]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[30:30]),.O(N_918));
defparam desc735.INIT=16'hACAA;
LUT5 desc736(.I0(inf_abs0_2[19:19]),.I1(inf_abs0_2[20:20]),.I2(inf_abs0_2[21:21]),.I3(inf_abs0_2[22:22]),.I4(inf_abs0_2[31:31]),.O(N_1890));
defparam desc736.INIT=32'hFFFFFFFD;
LUT4 desc737(.I0(inf_abs0_2[24:24]),.I1(inf_abs0_2[25:25]),.I2(inf_abs0_2[26:26]),.I3(inf_abs0_2[31:31]),.O(un36_df));
defparam desc737.INIT=16'h0080;
LUT5 desc738(.I0(datai[0:0]),.I1(inf_abs0_2[0:0]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[27:27]),.I4(inf_abs0_2[28:28]),.O(m_2[0:0]));
defparam desc738.INIT=32'hCACACACC;
LUT6 desc739(.I0(datai[30:30]),.I1(inf_abs0_2[20:20]),.I2(inf_abs0_2[21:21]),.I3(inf_abs0_2[22:22]),.I4(inf_abs0_2[31:31]),.I5(g0_2_0_i2_lut6_2_O6),.O(N_3568));
defparam desc739.INIT=64'h0000000000000008;
LUT4 reg3_1_1_axb_31_cZ(.I0(datai[31:31]),.I1(inf_abs0_2[31:31]),.I2(inf_abs0_2[27:27]),.I3(inf_abs0_2[28:28]),.O(reg3_1_1_axb_31));
defparam reg3_1_1_axb_31_cZ.INIT=16'hDDDF;
LUT6 desc740(.I0(reg0[29:29]),.I1(reg1[29:29]),.I2(reg2[29:29]),.I3(un3_reg3_cry_25),.I4(N_3_0),.I5(N_13),.O(r_4[29:29]));
defparam desc740.INIT=64'hF0F0AAAAFF00CCCC;
LUT6_L desc741(.I0(reg0[2:2]),.I1(reg1[2:2]),.I2(reg2[2:2]),.I3(reg3[2:2]),.I4(inf_abs0_2[29:29]),.I5(inf_abs0_2[30:30]),.LO(N_36_i));
defparam desc741.INIT=64'hFF00F0F0CCCCAAAA;
LUT6 un11_reg0_axb_19_cZ(.I0(datai[19:19]),.I1(inf_abs0_2[19:19]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[27:27]),.I4(inf_abs0_2[28:28]),.I5(r_4[19:19]),.O(un11_reg0_axb_19));
defparam un11_reg0_axb_19_cZ.INIT=64'h35353533CACACACC;
LUT6 un11_reg0_axb_18_cZ(.I0(datai[18:18]),.I1(inf_abs0_2[18:18]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[27:27]),.I4(inf_abs0_2[28:28]),.I5(r_4[18:18]),.O(un11_reg0_axb_18));
defparam un11_reg0_axb_18_cZ.INIT=64'h35353533CACACACC;
LUT6 un11_reg0_axb_17_cZ(.I0(datai[17:17]),.I1(inf_abs0_2[17:17]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[27:27]),.I4(inf_abs0_2[28:28]),.I5(r_4[17:17]),.O(un11_reg0_axb_17));
defparam un11_reg0_axb_17_cZ.INIT=64'h35353533CACACACC;
LUT6 un11_reg0_axb_16_cZ(.I0(datai[16:16]),.I1(inf_abs0_2[16:16]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[27:27]),.I4(inf_abs0_2[28:28]),.I5(r_4[16:16]),.O(un11_reg0_axb_16));
defparam un11_reg0_axb_16_cZ.INIT=64'h35353533CACACACC;
LUT6 un11_reg0_axb_15_cZ(.I0(datai[15:15]),.I1(inf_abs0_2[15:15]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[27:27]),.I4(inf_abs0_2[28:28]),.I5(r_4[15:15]),.O(un11_reg0_axb_15));
defparam un11_reg0_axb_15_cZ.INIT=64'h35353533CACACACC;
LUT6 un11_reg0_axb_14_cZ(.I0(datai[14:14]),.I1(inf_abs0_2[14:14]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[27:27]),.I4(inf_abs0_2[28:28]),.I5(r_4[14:14]),.O(un11_reg0_axb_14));
defparam un11_reg0_axb_14_cZ.INIT=64'h35353533CACACACC;
LUT6 un11_reg0_axb_13_cZ(.I0(datai[13:13]),.I1(inf_abs0_2[13:13]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[27:27]),.I4(inf_abs0_2[28:28]),.I5(r_4[13:13]),.O(un11_reg0_axb_13));
defparam un11_reg0_axb_13_cZ.INIT=64'h35353533CACACACC;
LUT6 un11_reg0_axb_12_cZ(.I0(datai[12:12]),.I1(inf_abs0_2[12:12]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[27:27]),.I4(inf_abs0_2[28:28]),.I5(r_4[12:12]),.O(un11_reg0_axb_12));
defparam un11_reg0_axb_12_cZ.INIT=64'h35353533CACACACC;
LUT6 un11_reg0_axb_11_cZ(.I0(datai[11:11]),.I1(inf_abs0_2[11:11]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[27:27]),.I4(inf_abs0_2[28:28]),.I5(r_4[11:11]),.O(un11_reg0_axb_11));
defparam un11_reg0_axb_11_cZ.INIT=64'h35353533CACACACC;
LUT6 un11_reg0_axb_10_cZ(.I0(datai[10:10]),.I1(inf_abs0_2[10:10]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[27:27]),.I4(inf_abs0_2[28:28]),.I5(r_4[10:10]),.O(un11_reg0_axb_10));
defparam un11_reg0_axb_10_cZ.INIT=64'h35353533CACACACC;
LUT6 un11_reg0_axb_9_cZ(.I0(datai[9:9]),.I1(inf_abs0_2[9:9]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[27:27]),.I4(inf_abs0_2[28:28]),.I5(r_4[9:9]),.O(un11_reg0_axb_9));
defparam un11_reg0_axb_9_cZ.INIT=64'h35353533CACACACC;
LUT6 un11_reg0_axb_8_cZ(.I0(datai[8:8]),.I1(inf_abs0_2[8:8]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[27:27]),.I4(inf_abs0_2[28:28]),.I5(r_4[8:8]),.O(un11_reg0_axb_8));
defparam un11_reg0_axb_8_cZ.INIT=64'h35353533CACACACC;
LUT6 un11_reg0_axb_7_cZ(.I0(datai[7:7]),.I1(inf_abs0_2[7:7]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[27:27]),.I4(inf_abs0_2[28:28]),.I5(r_4[7:7]),.O(un11_reg0_axb_7));
defparam un11_reg0_axb_7_cZ.INIT=64'h35353533CACACACC;
LUT6 un11_reg0_axb_6_cZ(.I0(datai[6:6]),.I1(inf_abs0_2[6:6]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[27:27]),.I4(inf_abs0_2[28:28]),.I5(r_4[6:6]),.O(un11_reg0_axb_6));
defparam un11_reg0_axb_6_cZ.INIT=64'h35353533CACACACC;
LUT6 un11_reg0_axb_5_cZ(.I0(datai[5:5]),.I1(inf_abs0_2[5:5]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[27:27]),.I4(inf_abs0_2[28:28]),.I5(r_4[5:5]),.O(un11_reg0_axb_5));
defparam un11_reg0_axb_5_cZ.INIT=64'h35353533CACACACC;
LUT6 un11_reg0_axb_4_cZ(.I0(datai[4:4]),.I1(inf_abs0_2[4:4]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[27:27]),.I4(inf_abs0_2[28:28]),.I5(r_4[4:4]),.O(un11_reg0_axb_4));
defparam un11_reg0_axb_4_cZ.INIT=64'h35353533CACACACC;
LUT6 un11_reg0_axb_3_cZ(.I0(datai[3:3]),.I1(inf_abs0_2[3:3]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[27:27]),.I4(inf_abs0_2[28:28]),.I5(r_4[3:3]),.O(un11_reg0_axb_3));
defparam un11_reg0_axb_3_cZ.INIT=64'h35353533CACACACC;
LUT6 un11_reg0_axb_2_cZ(.I0(datai[2:2]),.I1(inf_abs0_2[2:2]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[27:27]),.I4(inf_abs0_2[28:28]),.I5(N_28),.O(un11_reg0_axb_2));
defparam un11_reg0_axb_2_cZ.INIT=64'h35353533CACACACC;
LUT6 un11_reg0_axb_1_cZ(.I0(datai[1:1]),.I1(inf_abs0_2[1:1]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[27:27]),.I4(inf_abs0_2[28:28]),.I5(r_4[1:1]),.O(un11_reg0_axb_1));
defparam un11_reg0_axb_1_cZ.INIT=64'h35353533CACACACC;
LUT5 reg3_1_1_axb_19_cZ(.I0(datai[19:19]),.I1(inf_abs0_2[19:19]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[27:27]),.I4(inf_abs0_2[28:28]),.O(reg3_1_1_axb_19));
defparam reg3_1_1_axb_19_cZ.INIT=32'h35353533;
LUT5 reg3_1_1_axb_18_cZ(.I0(datai[18:18]),.I1(inf_abs0_2[18:18]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[27:27]),.I4(inf_abs0_2[28:28]),.O(reg3_1_1_axb_18));
defparam reg3_1_1_axb_18_cZ.INIT=32'h35353533;
LUT5 reg3_1_1_axb_17_cZ(.I0(datai[17:17]),.I1(inf_abs0_2[17:17]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[27:27]),.I4(inf_abs0_2[28:28]),.O(reg3_1_1_axb_17));
defparam reg3_1_1_axb_17_cZ.INIT=32'h35353533;
LUT5 reg3_1_1_axb_16_cZ(.I0(datai[16:16]),.I1(inf_abs0_2[16:16]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[27:27]),.I4(inf_abs0_2[28:28]),.O(reg3_1_1_axb_16));
defparam reg3_1_1_axb_16_cZ.INIT=32'h35353533;
LUT5 reg3_1_1_axb_15_cZ(.I0(datai[15:15]),.I1(inf_abs0_2[15:15]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[27:27]),.I4(inf_abs0_2[28:28]),.O(reg3_1_1_axb_15));
defparam reg3_1_1_axb_15_cZ.INIT=32'h35353533;
LUT5 reg3_1_1_axb_14_cZ(.I0(datai[14:14]),.I1(inf_abs0_2[14:14]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[27:27]),.I4(inf_abs0_2[28:28]),.O(reg3_1_1_axb_14));
defparam reg3_1_1_axb_14_cZ.INIT=32'h35353533;
LUT5 reg3_1_1_axb_13_cZ(.I0(datai[13:13]),.I1(inf_abs0_2[13:13]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[27:27]),.I4(inf_abs0_2[28:28]),.O(reg3_1_1_axb_13));
defparam reg3_1_1_axb_13_cZ.INIT=32'h35353533;
LUT5 reg3_1_1_axb_12_cZ(.I0(datai[12:12]),.I1(inf_abs0_2[12:12]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[27:27]),.I4(inf_abs0_2[28:28]),.O(reg3_1_1_axb_12));
defparam reg3_1_1_axb_12_cZ.INIT=32'h35353533;
LUT5 reg3_1_1_axb_11_cZ(.I0(datai[11:11]),.I1(inf_abs0_2[11:11]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[27:27]),.I4(inf_abs0_2[28:28]),.O(reg3_1_1_axb_11));
defparam reg3_1_1_axb_11_cZ.INIT=32'h35353533;
LUT5 reg3_1_1_axb_10_cZ(.I0(datai[10:10]),.I1(inf_abs0_2[10:10]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[27:27]),.I4(inf_abs0_2[28:28]),.O(reg3_1_1_axb_10));
defparam reg3_1_1_axb_10_cZ.INIT=32'h35353533;
LUT5 reg3_1_1_axb_9_cZ(.I0(datai[9:9]),.I1(inf_abs0_2[9:9]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[27:27]),.I4(inf_abs0_2[28:28]),.O(reg3_1_1_axb_9));
defparam reg3_1_1_axb_9_cZ.INIT=32'h35353533;
LUT5 reg3_1_1_axb_8_cZ(.I0(datai[8:8]),.I1(inf_abs0_2[8:8]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[27:27]),.I4(inf_abs0_2[28:28]),.O(reg3_1_1_axb_8));
defparam reg3_1_1_axb_8_cZ.INIT=32'h35353533;
LUT5 reg3_1_1_axb_7_cZ(.I0(datai[7:7]),.I1(inf_abs0_2[7:7]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[27:27]),.I4(inf_abs0_2[28:28]),.O(reg3_1_1_axb_7));
defparam reg3_1_1_axb_7_cZ.INIT=32'h35353533;
LUT5 reg3_1_1_axb_6_cZ(.I0(datai[6:6]),.I1(inf_abs0_2[6:6]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[27:27]),.I4(inf_abs0_2[28:28]),.O(reg3_1_1_axb_6));
defparam reg3_1_1_axb_6_cZ.INIT=32'h35353533;
LUT5 reg3_1_1_axb_5_cZ(.I0(datai[5:5]),.I1(inf_abs0_2[5:5]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[27:27]),.I4(inf_abs0_2[28:28]),.O(reg3_1_1_axb_5));
defparam reg3_1_1_axb_5_cZ.INIT=32'h35353533;
LUT5 reg3_1_1_axb_4_cZ(.I0(datai[4:4]),.I1(inf_abs0_2[4:4]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[27:27]),.I4(inf_abs0_2[28:28]),.O(reg3_1_1_axb_4));
defparam reg3_1_1_axb_4_cZ.INIT=32'h35353533;
LUT5 reg3_1_1_axb_3_cZ(.I0(datai[3:3]),.I1(inf_abs0_2[3:3]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[27:27]),.I4(inf_abs0_2[28:28]),.O(reg3_1_1_axb_3));
defparam reg3_1_1_axb_3_cZ.INIT=32'h35353533;
LUT5 reg3_1_1_axb_2_cZ(.I0(datai[2:2]),.I1(inf_abs0_2[2:2]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[27:27]),.I4(inf_abs0_2[28:28]),.O(reg3_1_1_axb_2));
defparam reg3_1_1_axb_2_cZ.INIT=32'h35353533;
LUT5 reg3_1_1_axb_1_cZ(.I0(datai[1:1]),.I1(inf_abs0_2[1:1]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[27:27]),.I4(inf_abs0_2[28:28]),.O(reg3_1_1_axb_1));
defparam reg3_1_1_axb_1_cZ.INIT=32'h35353533;
LUT6 desc742(.I0(reg0[31:31]),.I1(reg1[31:31]),.I2(reg2[31:31]),.I3(inf_abs0_2[31:31]),.I4(inf_abs0_2[29:29]),.I5(inf_abs0_2[30:30]),.O(r_4[31:31]));
defparam desc742.INIT=64'hAA00AAF0AACCAAAA;
LUT4 desc743(.I0(inf_abs0_2[24:24]),.I1(inf_abs0_2[25:25]),.I2(inf_abs0_2[26:26]),.I3(inf_abs0_2[31:31]),.O(d_cnst_sm0));
defparam desc743.INIT=16'h00BC;
LUT6 desc744(.I0(datai[19:19]),.I1(inf_abs0_2[19:19]),.I2(inf_abs0_2[20:20]),.I3(inf_abs0_2[31:31]),.I4(N_3873_2),.I5(g0_2_0_i2_lut6_2_O6),.O(\d_cnst_sn.reg0_28_3_2492_0 ));
defparam desc744.INIT=64'h00CC000000A00000;
LUT6 desc745(.I0(reg1[0:0]),.I1(reg3[0:0]),.I2(state),.I3(inf_abs0_2[0:0]),.I4(inf_abs0_2[27:27]),.I5(inf_abs0_2[28:28]),.O(\d_cnst_sn.addr_20_iv_7_654_i_1 ));
defparam desc745.INIT=64'h0303A35303F3A3F3;
LUT5 desc746(.I0(inf_abs0_2[24:24]),.I1(inf_abs0_2[25:25]),.I2(inf_abs0_2[26:26]),.I3(inf_abs0_2[22:22]),.I4(inf_abs0_2[31:31]),.O(\d_cnst_sn.reg3_5_sqmuxa_2_1 ));
defparam desc746.INIT=32'hFFFF007F;
LUT5 desc747(.I0(inf_abs0_2[21:21]),.I1(inf_abs0_2[22:22]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[28:28]),.I4(r_4[28:28]),.O(reg2_16_11_a1[29:29]));
defparam desc747.INIT=32'h08000000;
LUT6 desc748(.I0(N_3913),.I1(N_512_i),.I2(N_513_i),.I3(un11_r_cry[30:30]),.I4(un14_r_0_I_83),.I5(N_895),.O(N_3912));
defparam desc748.INIT=64'h5556595AA5A6A9AA;
LUT6 un11_reg0_axb_0_cZ(.I0(datai[0:0]),.I1(inf_abs0_2[0:0]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[27:27]),.I4(inf_abs0_2[28:28]),.I5(r_4[0:0]),.O(un11_reg0_axb_0));
defparam un11_reg0_axb_0_cZ.INIT=64'h35353533CACACACC;
LUT6 un3_t_axb_30_cZ(.I0(reg0[30:30]),.I1(reg1[30:30]),.I2(reg2[30:30]),.I3(inf_abs0_2[31:31]),.I4(inf_abs0_2[29:29]),.I5(inf_abs0_2[30:30]),.O(un3_t_axb_30));
defparam un3_t_axb_30_cZ.INIT=64'h55FF550F55335555;
LUT6 un3_t_axb_29_cZ(.I0(reg0[29:29]),.I1(reg1[29:29]),.I2(reg2[29:29]),.I3(un3_reg3_cry_25),.I4(N_3_0),.I5(N_13),.O(un3_t_axb_29));
defparam un3_t_axb_29_cZ.INIT=64'h0F0F555500FF3333;
LUT5 reg3_1_1_axb_0_cZ(.I0(datai[0:0]),.I1(inf_abs0_2[0:0]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[27:27]),.I4(inf_abs0_2[28:28]),.O(reg3_1_1_axb_0));
defparam reg3_1_1_axb_0_cZ.INIT=32'h35353533;
LUT5 desc749(.I0(inf_abs0_2[24:24]),.I1(inf_abs0_2[23:23]),.I2(inf_abs0_2[25:25]),.I3(inf_abs0_2[26:26]),.I4(inf_abs0_2[31:31]),.O(addr_4_sqmuxa_1_1));
defparam desc749.INIT=32'h00002000;
LUT6 desc750(.I0(reg0[31:31]),.I1(reg1[31:31]),.I2(reg2[31:31]),.I3(inf_abs0_2[31:31]),.I4(inf_abs0_2[29:29]),.I5(inf_abs0_2[30:30]),.O(r_4_i[31:31]));
defparam desc750.INIT=64'h55FF550F55335555;
LUT6 un3_t_axb_31_cZ(.I0(reg0[31:31]),.I1(reg1[31:31]),.I2(reg2[31:31]),.I3(inf_abs0_2[31:31]),.I4(inf_abs0_2[29:29]),.I5(inf_abs0_2[30:30]),.O(un3_t_axb_31));
defparam un3_t_axb_31_cZ.INIT=64'h55FF550F55335555;
LUT6 desc751(.I0(reg2[0:0]),.I1(reg1[0:0]),.I2(inf_abs0_2[0:0]),.I3(inf_abs0_2[31:31]),.I4(inf_abs0_2[27:27]),.I5(inf_abs0_2[28:28]),.O(N_2240_i));
defparam desc751.INIT=64'hF05AF03CF0F0F0F0;
LUT6 desc752(.I0(b),.I1(inf_abs0_2[21:21]),.I2(inf_abs0_2[22:22]),.I3(inf_abs0_2[31:31]),.I4(inf_abs0_2[27:27]),.I5(inf_abs0_2[28:28]),.O(\d_cnst_sn.reg0_28_14_2135_1_a0_2 ));
defparam desc752.INIT=64'h00000000004000C0;
LUT6 desc753(.I0(N_512_i),.I1(N_513_i),.I2(N_514_i),.I3(m_2[25:25]),.I4(N_527_i),.I5(r_4[24:24]),.O(\d_cnst_sn.reg2_16_0 [25:25]));
defparam desc753.INIT=64'hFFFDFFFD3F3DFFFD;
LUT6 desc754(.I0(N_512_i),.I1(N_513_i),.I2(N_514_i),.I3(m_2[24:24]),.I4(N_527_i),.I5(r_4[23:23]),.O(\d_cnst_sn.reg2_16_0 [24:24]));
defparam desc754.INIT=64'hFFFDFFFD3F3DFFFD;
LUT6 desc755(.I0(N_512_i),.I1(N_513_i),.I2(N_514_i),.I3(m_2[23:23]),.I4(N_527_i),.I5(r_4[22:22]),.O(\d_cnst_sn.reg2_16_0 [23:23]));
defparam desc755.INIT=64'hFFFDFFFD3F3DFFFD;
LUT6 desc756(.I0(N_512_i),.I1(N_513_i),.I2(N_514_i),.I3(m_2[22:22]),.I4(N_527_i),.I5(r_4[21:21]),.O(\d_cnst_sn.reg2_16_0 [22:22]));
defparam desc756.INIT=64'hFFFDFFFD3F3DFFFD;
LUT6_L desc757(.I0(N_512_i),.I1(N_513_i),.I2(N_514_i),.I3(m_2[21:21]),.I4(N_527_i),.I5(r_4[20:20]),.LO(\d_cnst_sn.reg2_16_0 [21:21]));
defparam desc757.INIT=64'hFFFDFFFD3F3DFFFD;
LUT5 desc758(.I0(inf_abs0_2[19:19]),.I1(inf_abs0_2[20:20]),.I2(inf_abs0_2[21:21]),.I3(inf_abs0_2[22:22]),.I4(inf_abs0_2[31:31]),.O(un1_b59));
defparam desc758.INIT=32'h00000AC0;
LUT5 desc759(.I0(inf_abs0_2[19:19]),.I1(inf_abs0_2[20:20]),.I2(inf_abs0_2[21:21]),.I3(inf_abs0_2[22:22]),.I4(inf_abs0_2[31:31]),.O(un1_b57));
defparam desc759.INIT=32'h00000530;
LUT5 desc760(.I0(inf_abs0_2[21:21]),.I1(inf_abs0_2[22:22]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[28:28]),.I4(r_4[28:28]),.O(reg0_m9_i_a1));
defparam desc760.INIT=32'h08000000;
LUT6 desc761(.I0(un3_reg3_cry_25),.I1(N_3913),.I2(N_512_i),.I3(\d_cnst_sn.reg1_16_a2_0 [5:5]),.I4(m_2[29:29]),.I5(reg3_1_1[29:29]),.O(reg2_16_11_a2[29:29]));
defparam desc761.INIT=64'hFE000E00F2000200;
LUT6 desc762(.I0(state),.I1(inf_abs0_2[24:24]),.I2(inf_abs0_2[23:23]),.I3(inf_abs0_2[25:25]),.I4(inf_abs0_2[26:26]),.I5(inf_abs0_2[31:31]),.O(addr_4_sqmuxa_1));
defparam desc762.INIT=64'h0000000008000000;
LUT4 desc763(.I0(inf_abs0_2[24:24]),.I1(inf_abs0_2[25:25]),.I2(inf_abs0_2[26:26]),.I3(inf_abs0_2[31:31]),.O(d_cnst));
defparam desc763.INIT=16'h00BA;
LUT6_L desc764(.I0(inf_abs0_2[28:28]),.I1(un1_inf_abs0_10[10:10]),.I2(un1_inf_abs0_11[10:10]),.I3(N_2660_2),.I4(\d_cnst_sn.addr_20_iv_1052_i_a6_1_0 ),.I5(\d_cnst_sn.addr_20_iv_17_362_i_1 ),.LO(N_2119_i));
defparam desc764.INIT=64'h00000000D0F0DDFF;
LUT6_L desc765(.I0(inf_abs0_2[28:28]),.I1(un1_inf_abs0_10[9:9]),.I2(un1_inf_abs0_11[9:9]),.I3(N_2660_2),.I4(\d_cnst_sn.addr_20_iv_1052_i_a6_1_0 ),.I5(\d_cnst_sn.addr_20_iv_16_389_i_1 ),.LO(N_2139_i));
defparam desc765.INIT=64'h00000000D0F0DDFF;
LUT6_L desc766(.I0(state),.I1(inf_abs0_2[27:27]),.I2(inf_abs0_2[28:28]),.I3(un1_inf_abs0_10[8:8]),.I4(un1_inf_abs0_11[8:8]),.I5(\d_cnst_sn.addr_20_iv_15_416_i_1 ),.LO(N_2159_i));
defparam desc766.INIT=64'h00000000FF7FDD5D;
LUT6_L desc767(.I0(reg3[7:7]),.I1(state),.I2(inf_abs0_2[7:7]),.I3(inf_abs0_2[28:28]),.I4(\d_cnst_sn.addr_20_iv_14_443_i_2 ),.I5(N_2641),.LO(N_2179_i));
defparam desc767.INIT=64'h000000000000EEE2;
LUT6_L desc768(.I0(state),.I1(inf_abs0_2[27:27]),.I2(inf_abs0_2[28:28]),.I3(un1_inf_abs0_10[6:6]),.I4(un1_inf_abs0_11[6:6]),.I5(\d_cnst_sn.addr_20_iv_13_470_i_1 ),.LO(N_2199_i));
defparam desc768.INIT=64'h00000000FF7FDD5D;
LUT6_L desc769(.I0(state),.I1(inf_abs0_2[27:27]),.I2(inf_abs0_2[28:28]),.I3(un1_inf_abs0_10[5:5]),.I4(un1_inf_abs0_11[5:5]),.I5(\d_cnst_sn.addr_20_iv_12_497_i_1 ),.LO(N_2219_i));
defparam desc769.INIT=64'h00000000FF7FDD5D;
LUT6_L desc770(.I0(state),.I1(inf_abs0_2[27:27]),.I2(inf_abs0_2[28:28]),.I3(un1_inf_abs0_10[3:3]),.I4(un1_inf_abs0_11[3:3]),.I5(\d_cnst_sn.addr_20_iv_10_562_i_1 ),.LO(N_2267_i));
defparam desc770.INIT=64'h00000000FF7FDD5D;
LUT6 desc771(.I0(\d_cnst_sn.reg2_N_3_mux ),.I1(reg2_16_2_d[20:20]),.I2(\d_cnst_sn.reg1_16_a2_0 [5:5]),.I3(\d_cnst_sn.reg0_28_a1_1 [4:4]),.I4(r_4[19:19]),.I5(reg3_1_1[20:20]),.O(\d_cnst_sn.reg2_16_0 [20:20]));
defparam desc771.INIT=64'hEFEF00EF4F4F004F;
LUT6 desc772(.I0(m_2[2:2]),.I1(m_2[1:1]),.I2(m_2[0:0]),.I3(r_4[0:0]),.I4(r_4[1:1]),.I5(N_28),.O(un14_r_0_N_70));
defparam desc772.INIT=64'h8008200240041001;
LUT6 desc773(.I0(m_2[15:15]),.I1(m_2[16:16]),.I2(m_2[17:17]),.I3(r_4[15:15]),.I4(r_4[16:16]),.I5(r_4[17:17]),.O(un14_r_0_N_42));
defparam desc773.INIT=64'h8040201008040201;
LUT6 desc774(.I0(m_2[3:3]),.I1(m_2[4:4]),.I2(m_2[5:5]),.I3(r_4[3:3]),.I4(r_4[4:4]),.I5(r_4[5:5]),.O(un14_r_0_N_14));
defparam desc774.INIT=64'h8040201008040201;
LUT6 desc775(.I0(m_2[19:19]),.I1(m_2[20:20]),.I2(m_2[18:18]),.I3(r_4[19:19]),.I4(r_4[18:18]),.I5(r_4[20:20]),.O(un14_r_0_N_49));
defparam desc775.INIT=64'h8040080420100201;
LUT6 desc776(.I0(m_2[12:12]),.I1(m_2[13:13]),.I2(m_2[14:14]),.I3(r_4[12:12]),.I4(r_4[13:13]),.I5(r_4[14:14]),.O(un14_r_0_N_7));
defparam desc776.INIT=64'h8040201008040201;
LUT6 desc777(.I0(m_2[9:9]),.I1(m_2[10:10]),.I2(m_2[11:11]),.I3(r_4[11:11]),.I4(r_4[9:9]),.I5(r_4[10:10]),.O(un14_r_0_N_28));
defparam desc777.INIT=64'h8008400420021001;
LUT6 desc778(.I0(m_2[7:7]),.I1(m_2[6:6]),.I2(m_2[8:8]),.I3(r_4[6:6]),.I4(r_4[8:8]),.I5(r_4[7:7]),.O(un14_r_0_N_21));
defparam desc778.INIT=64'h8020080240100401;
LUT6 desc779(.I0(reg0[30:30]),.I1(reg1[30:30]),.I2(reg2[30:30]),.I3(N_3_0),.I4(r_4[31:31]),.I5(N_13),.O(r_6[30:30]));
defparam desc779.INIT=64'hF0AA000000CC0000;
LUT6 desc780(.I0(N_3910),.I1(\d_cnst_sn.reg0_28_a0_1 [7:7]),.I2(m_2[7:7]),.I3(\d_cnst_sn.reg0_28_a1_1 [4:4]),.I4(r_4[6:6]),.I5(reg3_1_1[7:7]),.O(\d_cnst_sn.reg0_1 [7:7]));
defparam desc780.INIT=64'hF5F500F531310031;
LUT6 desc781(.I0(m_2[29:29]),.I1(m_2[27:27]),.I2(m_2[28:28]),.I3(r_4[27:27]),.I4(r_4[28:28]),.I5(r_4[29:29]),.O(un14_r_0_N_63));
defparam desc781.INIT=64'h8020080240100401;
LUT6 desc782(.I0(N_526_i),.I1(N_1901),.I2(N_513_i),.I3(N_514_i),.I4(un36_df),.I5(N_527_i),.O(b_2_sqmuxa));
defparam desc782.INIT=64'h0000200000000000;
LUT6_L desc783(.I0(state),.I1(inf_abs0_2[27:27]),.I2(inf_abs0_2[28:28]),.I3(un1_inf_abs0_10[11:11]),.I4(un1_inf_abs0_11[11:11]),.I5(\d_cnst_sn.addr_20_iv_18_335_i_1 ),.LO(N_2099_i));
defparam desc783.INIT=64'h00000000FF7FDD5D;
LUT6_L desc784(.I0(\d_cnst_sn.addr_20_iv_6_863_i_0 ),.I1(un1_inf_abs0_10[19:19]),.I2(un1_inf_abs0_11[19:19]),.I3(\d_cnst_sn.addr_20_iv_1052_i_a6_1_0 ),.I4(\d_cnst_sn.addr_20_iv_1052_i_a6_2_0 ),.I5(N_2641),.LO(N_2516_i));
defparam desc784.INIT=64'h0000000040445055;
LUT6_L desc785(.I0(\d_cnst_sn.addr_20_iv_5_890_i_0 ),.I1(un1_inf_abs0_10[18:18]),.I2(un1_inf_abs0_11[18:18]),.I3(\d_cnst_sn.addr_20_iv_1052_i_a6_1_0 ),.I4(\d_cnst_sn.addr_20_iv_1052_i_a6_2_0 ),.I5(N_2641),.LO(N_2536_i));
defparam desc785.INIT=64'h0000000040445055;
LUT6_L desc786(.I0(\d_cnst_sn.addr_20_iv_4_917_i_0 ),.I1(un1_inf_abs0_10[17:17]),.I2(un1_inf_abs0_11[17:17]),.I3(\d_cnst_sn.addr_20_iv_1052_i_a6_1_0 ),.I4(\d_cnst_sn.addr_20_iv_1052_i_a6_2_0 ),.I5(N_2641),.LO(N_2556_i));
defparam desc786.INIT=64'h0000000040445055;
LUT6_L desc787(.I0(\d_cnst_sn.addr_20_iv_3_944_i_0 ),.I1(un1_inf_abs0_10[16:16]),.I2(un1_inf_abs0_11[16:16]),.I3(\d_cnst_sn.addr_20_iv_1052_i_a6_1_0 ),.I4(\d_cnst_sn.addr_20_iv_1052_i_a6_2_0 ),.I5(N_2641),.LO(N_2576_i));
defparam desc787.INIT=64'h0000000040445055;
LUT6_L desc788(.I0(\d_cnst_sn.addr_20_iv_2_971_i_0 ),.I1(un1_inf_abs0_10[15:15]),.I2(un1_inf_abs0_11[15:15]),.I3(\d_cnst_sn.addr_20_iv_1052_i_a6_1_0 ),.I4(\d_cnst_sn.addr_20_iv_1052_i_a6_2_0 ),.I5(N_2641),.LO(N_2596_i));
defparam desc788.INIT=64'h0000000040445055;
LUT6_L desc789(.I0(\d_cnst_sn.addr_20_iv_1_998_i_0 ),.I1(un1_inf_abs0_10[14:14]),.I2(un1_inf_abs0_11[14:14]),.I3(\d_cnst_sn.addr_20_iv_1052_i_a6_1_0 ),.I4(\d_cnst_sn.addr_20_iv_1052_i_a6_2_0 ),.I5(N_2641),.LO(N_2616_i));
defparam desc789.INIT=64'h0000000040445055;
LUT6_L desc790(.I0(\d_cnst_sn.addr_20_iv_0_1025_i_0 ),.I1(un1_inf_abs0_10[13:13]),.I2(un1_inf_abs0_11[13:13]),.I3(\d_cnst_sn.addr_20_iv_1052_i_a6_1_0 ),.I4(\d_cnst_sn.addr_20_iv_1052_i_a6_2_0 ),.I5(N_2641),.LO(N_2636_i));
defparam desc790.INIT=64'h0000000040445055;
LUT6_L desc791(.I0(\d_cnst_sn.addr_20_iv_1052_i_0 ),.I1(un1_inf_abs0_10[12:12]),.I2(un1_inf_abs0_11[12:12]),.I3(\d_cnst_sn.addr_20_iv_1052_i_a6_1_0 ),.I4(\d_cnst_sn.addr_20_iv_1052_i_a6_2_0 ),.I5(N_2641),.LO(N_2656_i));
defparam desc791.INIT=64'h0000000040445055;
LUT6 desc792(.I0(\d_cnst_sn.reg2_16_0_1_tz [28:28]),.I1(\d_cnst_sn.reg1_16_a2_0 [5:5]),.I2(\d_cnst_sn.reg0_28_a1_1 [4:4]),.I3(r_4[27:27]),.I4(N_1363),.I5(un32_reg0_s_28),.O(\d_cnst_sn.reg2_16_0_1_0 [28:28]));
defparam desc792.INIT=64'hFF0F3303AA0A2202;
LUT6 desc793(.I0(\d_cnst_sn.reg2_16_0_1_tz [28:28]),.I1(\d_cnst_sn.reg1_16_a2_0 [5:5]),.I2(\d_cnst_sn.reg0_28_a1_1 [4:4]),.I3(r_4[26:26]),.I4(N_1362),.I5(un32_reg0_s_27),.O(\d_cnst_sn.reg2_16_0_1_0 [27:27]));
defparam desc793.INIT=64'hFF0F3303AA0A2202;
LUT6 desc794(.I0(\d_cnst_sn.reg2_16_0_1_tz [28:28]),.I1(\d_cnst_sn.reg1_16_a2_0 [5:5]),.I2(\d_cnst_sn.reg0_28_a1_1 [4:4]),.I3(r_4[25:25]),.I4(N_1361),.I5(un32_reg0_s_26),.O(\d_cnst_sn.reg2_16_0_1_0 [26:26]));
defparam desc794.INIT=64'hFF0F3303AA0A2202;
LUT6 desc795(.I0(N_3913),.I1(N_513_i),.I2(N_514_i),.I3(N_1352),.I4(un32_reg0_s_17),.I5(un11_reg0_s_17),.O(reg2_16_11_a3[17:17]));
defparam desc795.INIT=64'h0003101320233033;
LUT6 desc796(.I0(N_3913),.I1(N_513_i),.I2(N_514_i),.I3(N_1354),.I4(un32_reg0_s_19),.I5(un11_reg0_s_19),.O(reg2_16_11_a3[19:19]));
defparam desc796.INIT=64'h0003101320233033;
LUT6 desc797(.I0(N_3913),.I1(N_513_i),.I2(N_514_i),.I3(N_1353),.I4(un32_reg0_s_18),.I5(un11_reg0_s_18),.O(reg2_16_11_a3[18:18]));
defparam desc797.INIT=64'h0003101320233033;
LUT6_L desc798(.I0(inf_abs0_2[22:22]),.I1(reg0_28_sn_m6_lut6_2_O5),.I2(N_513_i),.I3(N_527_i),.I4(N_1493),.I5(t_1[30:30]),.LO(reg2_16[30:30]));
defparam desc798.INIT=64'h0F0F00000F2F0020;
LUT6 desc799(.I0(\d_cnst_sn.reg0_m9_i_a3_0 ),.I1(N_1033),.I2(\d_cnst_sn.reg0_28_9_2294_a6_3_0 ),.I3(m_2[27:27]),.I4(un32_reg0_s_27),.I5(un11_reg0_s_27),.O(\d_cnst_sn.reg1_16_8_1837_0 ));
defparam desc799.INIT=64'hFAAAF888F222F000;
LUT6 desc800(.I0(\d_cnst_sn.reg0_m9_i_a3_0 ),.I1(N_1033),.I2(\d_cnst_sn.reg0_28_9_2294_a6_3_0 ),.I3(m_2[26:26]),.I4(un32_reg0_s_26),.I5(un11_reg0_s_26),.O(\d_cnst_sn.reg1_16_7_1870_0 ));
defparam desc800.INIT=64'hFAAAF888F222F000;
LUT6 desc801(.I0(\d_cnst_sn.reg0_m9_i_a3_0 ),.I1(N_1033),.I2(\d_cnst_sn.reg0_28_9_2294_a6_3_0 ),.I3(m_2[25:25]),.I4(un32_reg0_s_25),.I5(un11_reg0_s_25),.O(\d_cnst_sn.reg0_28_9_2294_0 ));
defparam desc801.INIT=64'hFAAAF888F222F000;
LUT6 desc802(.I0(\d_cnst_sn.reg0_m9_i_a3_0 ),.I1(N_1033),.I2(\d_cnst_sn.reg0_28_9_2294_a6_3_0 ),.I3(m_2[23:23]),.I4(un32_reg0_s_23),.I5(un11_reg0_s_23),.O(\d_cnst_sn.reg0_28_7_2360_0 ));
defparam desc802.INIT=64'hFAAAF888F222F000;
LUT6 desc803(.I0(\d_cnst_sn.reg0_m9_i_a3_0 ),.I1(N_1033),.I2(\d_cnst_sn.reg0_28_9_2294_a6_3_0 ),.I3(m_2[22:22]),.I4(un32_reg0_s_22),.I5(un11_reg0_s_22),.O(\d_cnst_sn.reg0_28_6_2393_0 ));
defparam desc803.INIT=64'hFAAAF888F222F000;
LUT6 desc804(.I0(\d_cnst_sn.reg0_m9_i_a3_0 ),.I1(N_1033),.I2(\d_cnst_sn.reg0_28_9_2294_a6_3_0 ),.I3(m_2[21:21]),.I4(un32_reg0_s_21),.I5(un11_reg0_s_21),.O(\d_cnst_sn.reg0_28_5_2426_0 ));
defparam desc804.INIT=64'hFAAAF888F222F000;
LUT6 desc805(.I0(\d_cnst_sn.reg0_m9_i_a3_0 ),.I1(N_1033),.I2(\d_cnst_sn.reg0_28_9_2294_a6_3_0 ),.I3(m_2[24:24]),.I4(un32_reg0_s_24),.I5(un11_reg0_s_24),.O(\d_cnst_sn.reg0_28_8_2327_0 ));
defparam desc805.INIT=64'hFAAAF888F222F000;
LUT6 desc806(.I0(\d_cnst_sn.reg0_m9_i_a3_0 ),.I1(N_1033),.I2(\d_cnst_sn.reg0_28_9_2294_a6_3_0 ),.I3(m_2[20:20]),.I4(un32_reg0_s_20),.I5(un11_reg0_s_20),.O(\d_cnst_sn.reg0_28_4_2459_0 ));
defparam desc806.INIT=64'hFAAAF888F222F000;
LUT5 desc807(.I0(\d_cnst_sn.reg0_m9_i_a3_0 ),.I1(N_1033),.I2(\d_cnst_sn.reg0_28_3_2492_0 ),.I3(un32_reg0_s_19),.I4(un11_reg0_s_19),.O(\d_cnst_sn.reg0_28_3_2492_1 ));
defparam desc807.INIT=32'hFAF8F2F0;
LUT6 desc808(.I0(N_512_i),.I1(\d_cnst_sn.b60_0 ),.I2(reg2_16_11_a1[29:29]),.I3(reg2_16_11_a2[29:29]),.I4(un32_reg0_s_29),.I5(un11_reg0_s_29),.O(\d_cnst_sn.reg2_16_1 [29:29]));
defparam desc808.INIT=64'hFFFCFFF4FFF8FFF0;
LUT6_L desc809(.I0(N_513_i),.I1(N_514_i),.I2(N_1338),.I3(N_1370),.I4(N_1562),.I5(t_6[3:3]),.LO(reg2_16[3:3]));
defparam desc809.INIT=64'hFEBADC9876325410;
LUT6_L desc810(.I0(N_513_i),.I1(N_514_i),.I2(N_1339),.I3(N_1371),.I4(N_1563),.I5(t_6[4:4]),.LO(reg2_16[4:4]));
defparam desc810.INIT=64'hFEBADC9876325410;
LUT6_L desc811(.I0(N_513_i),.I1(N_514_i),.I2(N_1340),.I3(N_1372),.I4(N_1564),.I5(t_6[5:5]),.LO(reg2_16[5:5]));
defparam desc811.INIT=64'hFEBADC9876325410;
LUT6_L desc812(.I0(N_513_i),.I1(N_514_i),.I2(N_1341),.I3(N_1373),.I4(N_1565),.I5(t_6[6:6]),.LO(reg2_16[6:6]));
defparam desc812.INIT=64'hFEBADC9876325410;
LUT6_L desc813(.I0(N_513_i),.I1(N_514_i),.I2(N_1344),.I3(N_1376),.I4(N_1568),.I5(t_6[9:9]),.LO(reg2_16[9:9]));
defparam desc813.INIT=64'hFEBADC9876325410;
LUT6_L desc814(.I0(N_513_i),.I1(N_514_i),.I2(N_1345),.I3(N_1377),.I4(N_1569),.I5(t_6[10:10]),.LO(reg2_16[10:10]));
defparam desc814.INIT=64'hFEBADC9876325410;
LUT6_L desc815(.I0(N_513_i),.I1(N_514_i),.I2(N_1346),.I3(N_1378),.I4(N_1570),.I5(t_6[11:11]),.LO(reg2_16[11:11]));
defparam desc815.INIT=64'hFEBADC9876325410;
LUT6_L desc816(.I0(N_513_i),.I1(N_514_i),.I2(N_1347),.I3(N_1379),.I4(N_1571),.I5(t_6[12:12]),.LO(reg2_16[12:12]));
defparam desc816.INIT=64'hFEBADC9876325410;
LUT6_L desc817(.I0(N_513_i),.I1(N_514_i),.I2(N_1348),.I3(N_1380),.I4(N_1572),.I5(t_6[13:13]),.LO(reg2_16[13:13]));
defparam desc817.INIT=64'hFEBADC9876325410;
LUT6_L desc818(.I0(N_513_i),.I1(N_514_i),.I2(N_1349),.I3(N_1381),.I4(N_1573),.I5(t_6[14:14]),.LO(reg2_16[14:14]));
defparam desc818.INIT=64'hFEBADC9876325410;
LUT6_L desc819(.I0(N_513_i),.I1(N_514_i),.I2(N_1350),.I3(N_1382),.I4(N_1574),.I5(t_6[15:15]),.LO(reg2_16[15:15]));
defparam desc819.INIT=64'hFEBADC9876325410;
LUT6_L desc820(.I0(N_513_i),.I1(N_514_i),.I2(N_1351),.I3(N_1383),.I4(N_1575),.I5(t_6[16:16]),.LO(reg2_16[16:16]));
defparam desc820.INIT=64'hFEBADC9876325410;
LUT6_L desc821(.I0(state),.I1(N_7_i),.I2(N_513_i),.I3(N_514_i),.I4(un36_df),.I5(m7),.LO(rd_18));
defparam desc821.INIT=64'h55555555DDDDDFFF;
LUT6_L desc822(.I0(N_513_i),.I1(N_514_i),.I2(N_1343),.I3(N_1375),.I4(N_1567),.I5(t_6[8:8]),.LO(reg2_16[8:8]));
defparam desc822.INIT=64'hFEBADC9876325410;
LUT6_L desc823(.I0(N_513_i),.I1(N_514_i),.I2(N_1337),.I3(N_1369),.I4(N_1561),.I5(t_6[2:2]),.LO(reg2_16[2:2]));
defparam desc823.INIT=64'hFEBADC9876325410;
LUT6_L desc824(.I0(N_513_i),.I1(N_514_i),.I2(N_1342),.I3(N_1374),.I4(N_1566),.I5(t_6[7:7]),.LO(reg2_16[7:7]));
defparam desc824.INIT=64'hFEBADC9876325410;
LUT6 desc825(.I0(state),.I1(N_7_i),.I2(N_513_i),.I3(N_514_i),.I4(un36_df),.I5(m7),.O(addr_0_sqmuxa_1_i));
defparam desc825.INIT=64'h77775555FFFFDFFF;
LUT6 desc826(.I0(\d_cnst_sn.reg0_28_12_2195_a6_1_2_0 ),.I1(\d_cnst_sn.reg0_m8_e_0 ),.I2(N_513_i),.I3(N_527_i),.I4(r_4[27:27]),.I5(reg3_1_1[28:28]),.O(\d_cnst_sn.reg1_16_9_1804_3_tz ));
defparam desc826.INIT=64'hBBBBABBBB0B0A0B0;
LUT6_L desc827(.I0(\d_cnst_sn.reg0_28_a1_1 [4:4]),.I1(\d_cnst_sn.reg1_16_a0_1 [3:3]),.I2(r_4[16:16]),.I3(t_1[17:17]),.I4(reg2_16_11_a2[17:17]),.I5(reg2_16_11_a3[17:17]),.LO(reg2_16[17:17]));
defparam desc827.INIT=64'h00000000000031F5;
LUT6_L desc828(.I0(\d_cnst_sn.reg0_28_a1_1 [4:4]),.I1(\d_cnst_sn.reg1_16_a0_1 [3:3]),.I2(r_4[18:18]),.I3(t_1[19:19]),.I4(reg2_16_11_a2[19:19]),.I5(reg2_16_11_a3[19:19]),.LO(reg2_16[19:19]));
defparam desc828.INIT=64'h00000000000031F5;
LUT6_L desc829(.I0(\d_cnst_sn.reg0_28_a1_1 [4:4]),.I1(\d_cnst_sn.reg1_16_a0_1 [3:3]),.I2(r_4[17:17]),.I3(t_1[18:18]),.I4(reg2_16_11_a2[18:18]),.I5(reg2_16_11_a3[18:18]),.LO(reg2_16[18:18]));
defparam desc829.INIT=64'h00000000000031F5;
LUT6_L desc830(.I0(\d_cnst_sn.reg2_16_11_1_tz [28:28]),.I1(\d_cnst_sn.reg1_16_a0_1 [3:3]),.I2(\d_cnst_sn.reg2_16_0 [20:20]),.I3(un11_reg0_s_20),.I4(\d_cnst_sn.reg2_16_1 [20:20]),.I5(t_1[20:20]),.LO(reg2_16[20:20]));
defparam desc830.INIT=64'h30200000F0A00000;
LUT5_L desc831(.I0(\d_cnst_sn.reg2_16_11_1_tz [28:28]),.I1(\d_cnst_sn.reg1_16_a0_1 [3:3]),.I2(un11_reg0_s_28),.I3(\d_cnst_sn.reg2_16_0_1_0 [28:28]),.I4(t_1[28:28]),.LO(reg2_16[28:28]));
defparam desc831.INIT=32'h3200FA00;
LUT5_L desc832(.I0(\d_cnst_sn.reg2_16_11_1_tz [28:28]),.I1(\d_cnst_sn.reg1_16_a0_1 [3:3]),.I2(un11_reg0_s_27),.I3(\d_cnst_sn.reg2_16_0_1_0 [27:27]),.I4(t_1[27:27]),.LO(reg2_16[27:27]));
defparam desc832.INIT=32'h3200FA00;
LUT5_L desc833(.I0(\d_cnst_sn.reg2_16_11_1_tz [28:28]),.I1(\d_cnst_sn.reg1_16_a0_1 [3:3]),.I2(un11_reg0_s_26),.I3(\d_cnst_sn.reg2_16_0_1_0 [26:26]),.I4(t_1[26:26]),.LO(reg2_16[26:26]));
defparam desc833.INIT=32'h3200FA00;
LUT5_L desc834(.I0(d[0:0]),.I1(d[1:1]),.I2(un1_df_1),.I3(d_cnst),.I4(d_cnst_sm0),.LO(un86_df));
defparam desc834.INIT=32'h404F4040;
LUT6_L desc835(.I0(\d_cnst_sn.reg0_28_2526_a5_1_0 ),.I1(\d_cnst_sn.reg1_16_8_1837_2_tz ),.I2(\d_cnst_sn.reg0_28_7_a0_0 [9:9]),.I3(\d_cnst_sn.reg0_28_0 [20:20]),.I4(t_1[20:20]),.I5(\d_cnst_sn.reg0_28_4_2459_0 ),.LO(reg0_28_4_2459));
defparam desc835.INIT=64'hFFFFFFFF0E00EE00;
LUT5_L desc836(.I0(\d_cnst_sn.reg0_28_7_a0_0 [9:9]),.I1(\d_cnst_sn.reg0_28_11_2228_a6_1_1 ),.I2(\d_cnst_sn.reg1_16_8_1837_3_1 ),.I3(t_1[27:27]),.I4(\d_cnst_sn.reg1_16_8_1837_0 ),.LO(reg1_16_8_1837));
defparam desc836.INIT=32'hFFFF54FC;
LUT5_L desc837(.I0(\d_cnst_sn.reg0_28_7_a0_0 [9:9]),.I1(\d_cnst_sn.reg0_28_7_2360_3_1 ),.I2(\d_cnst_sn.reg0_28_7_2360_a6_1_1 ),.I3(t_1[23:23]),.I4(\d_cnst_sn.reg0_28_7_2360_0 ),.LO(reg0_28_7_2360));
defparam desc837.INIT=32'hFFFF54FC;
LUT5_L desc838(.I0(\d_cnst_sn.reg0_28_7_a0_0 [9:9]),.I1(\d_cnst_sn.reg0_28_10_2261_a6_1_1 ),.I2(\d_cnst_sn.reg1_16_7_1870_3_1 ),.I3(t_1[26:26]),.I4(\d_cnst_sn.reg1_16_7_1870_0 ),.LO(reg1_16_7_1870));
defparam desc838.INIT=32'hFFFF54FC;
LUT5_L desc839(.I0(\d_cnst_sn.reg0_28_7_a0_0 [9:9]),.I1(\d_cnst_sn.reg0_28_5_2426_3_1 ),.I2(\d_cnst_sn.reg0_28_5_2426_a6_1_1 ),.I3(t_1[21:21]),.I4(\d_cnst_sn.reg0_28_5_2426_0 ),.LO(reg0_28_5_2426));
defparam desc839.INIT=32'hFFFF54FC;
LUT6_L desc840(.I0(\d_cnst_sn.reg0_28_2526_a5_1_0 ),.I1(\d_cnst_sn.reg1_16_8_1837_2_tz ),.I2(\d_cnst_sn.reg0_28_7_a0_0 [9:9]),.I3(\d_cnst_sn.reg0_28_0 [19:19]),.I4(t_1[19:19]),.I5(\d_cnst_sn.reg0_28_3_2492_1 ),.LO(reg0_28_3_2492));
defparam desc840.INIT=64'hFFFFFFFF0E00EE00;
LUT5_L desc841(.I0(\d_cnst_sn.reg0_28_7_a0_0 [9:9]),.I1(\d_cnst_sn.reg0_28_6_2393_3_1 ),.I2(\d_cnst_sn.reg0_28_6_2393_a6_1_1 ),.I3(t_1[22:22]),.I4(\d_cnst_sn.reg0_28_6_2393_0 ),.LO(reg0_28_6_2393));
defparam desc841.INIT=32'hFFFF54FC;
LUT5_L desc842(.I0(\d_cnst_sn.reg0_28_7_a0_0 [9:9]),.I1(\d_cnst_sn.reg0_28_9_2294_3_1 ),.I2(\d_cnst_sn.reg0_28_9_2294_a6_1_1 ),.I3(t_1[25:25]),.I4(\d_cnst_sn.reg0_28_9_2294_0 ),.LO(N_3673));
defparam desc842.INIT=32'hFFFF54FC;
LUT6_L desc843(.I0(\d_cnst_sn.reg1_16_8_1837_2_tz ),.I1(\d_cnst_sn.reg0_28_7_a0_0 [9:9]),.I2(reg0_28_7_d[24:24]),.I3(\d_cnst_sn.reg0_28_8_2327_a6_1_1 ),.I4(t_1[24:24]),.I5(\d_cnst_sn.reg0_28_8_2327_0 ),.LO(reg0_28_8_2327));
defparam desc843.INIT=64'hFFFFFFFF3320FFA8;
LUT6_L desc844(.I0(\d_cnst_sn.reg0_m9_i_a0_0 ),.I1(N_514_i),.I2(N_527_i),.I3(t_1[29:29]),.I4(reg2_16_11_a3[29:29]),.I5(\d_cnst_sn.reg2_16_1 [29:29]),.LO(reg2_16[29:29]));
defparam desc844.INIT=64'hFFFFFFFFFFFF0008;
LUT6_L desc845(.I0(\d_cnst_sn.b64_0 ),.I1(\d_cnst_sn.b60_0 ),.I2(\d_cnst_sn.reg1_16_a0_1 [3:3]),.I3(\d_cnst_sn.reg0_1 [7:7]),.I4(t_1[7:7]),.I5(N_1042),.LO(reg0_28[7:7]));
defparam desc845.INIT=64'h0F00FF0001001100;
LUT6_L desc846(.I0(\d_cnst_sn.b60_0 ),.I1(\d_cnst_sn.reg1_16_a0_1 [3:3]),.I2(\d_cnst_sn.reg2_16_1 [25:25]),.I3(t_1[25:25]),.I4(reg2_16_11_a4[25:25]),.I5(N_1584),.LO(reg2_16[25:25]));
defparam desc846.INIT=64'h000030F000001050;
LUT6_L desc847(.I0(\d_cnst_sn.b60_0 ),.I1(\d_cnst_sn.reg1_16_a0_1 [3:3]),.I2(\d_cnst_sn.reg2_16_1 [24:24]),.I3(t_1[24:24]),.I4(reg2_16_11_a4[24:24]),.I5(N_1583),.LO(reg2_16[24:24]));
defparam desc847.INIT=64'h000030F000001050;
LUT6_L desc848(.I0(\d_cnst_sn.b60_0 ),.I1(\d_cnst_sn.reg1_16_a0_1 [3:3]),.I2(\d_cnst_sn.reg2_16_1 [23:23]),.I3(t_1[23:23]),.I4(reg2_16_11_a4[23:23]),.I5(N_1582),.LO(reg2_16[23:23]));
defparam desc848.INIT=64'h000030F000001050;
LUT6_L desc849(.I0(\d_cnst_sn.b60_0 ),.I1(\d_cnst_sn.reg1_16_a0_1 [3:3]),.I2(\d_cnst_sn.reg2_16_1 [22:22]),.I3(t_1[22:22]),.I4(reg2_16_11_a4[22:22]),.I5(N_1581),.LO(reg2_16[22:22]));
defparam desc849.INIT=64'h000030F000001050;
LUT6_L desc850(.I0(\d_cnst_sn.b60_0 ),.I1(\d_cnst_sn.reg1_16_a0_1 [3:3]),.I2(\d_cnst_sn.reg2_16_1 [21:21]),.I3(t_1[21:21]),.I4(reg2_16_11_a4[21:21]),.I5(N_1580),.LO(reg2_16[21:21]));
defparam desc850.INIT=64'h000030F000001050;
LUT6_L b_e(.I0(b),.I1(state),.I2(N_7_i),.I3(N_514_i),.I4(b_2_sqmuxa),.I5(N_3912),.LO(b_0));
defparam b_e.INIT=64'hA222AA2AE2E2EAEA;
LUT6 desc851(.I0(d[0:0]),.I1(d[1:1]),.I2(un1_df_1),.I3(d_cnst),.I4(d_cnst_sm0),.I5(un36_df),.O(un1_df_17_2));
defparam desc851.INIT=64'h000000008F808080;
LUT6_L desc852(.I0(inf_abs0_2[4:4]),.I1(inf_abs0_2[27:27]),.I2(inf_abs0_2[28:28]),.I3(un1_inf_abs0_10[4:4]),.I4(un1_inf_abs0_11[4:4]),.I5(addr_4_sqmuxa_1_1),.LO(N_54));
defparam desc852.INIT=64'hFFFFFFFF04C435F5;
LUT6_L desc853(.I0(inf_abs0_2[2:2]),.I1(inf_abs0_2[27:27]),.I2(inf_abs0_2[28:28]),.I3(un1_inf_abs0_10[2:2]),.I4(un1_inf_abs0_11[2:2]),.I5(addr_4_sqmuxa_1_1),.LO(N_45));
defparam desc853.INIT=64'hFFFFFFFF04C435F5;
LUT6 desc854(.I0(d[0:0]),.I1(d[1:1]),.I2(un1_df_1),.I3(N_3910),.I4(d_cnst),.I5(d_cnst_sm0),.O(N_1132));
defparam desc854.INIT=64'h1000100010001F00;
LUT6 desc855(.I0(d[0:0]),.I1(d[1:1]),.I2(un1_df_1),.I3(N_3910),.I4(d_cnst),.I5(d_cnst_sm0),.O(N_1270));
defparam desc855.INIT=64'h200020002F002000;
LUT6_L desc856(.I0(\d_cnst_sn.reg0_28_9_2294_a6_3_0 ),.I1(m_2[28:28]),.I2(\d_cnst_sn.reg0_28_7_a0_0 [9:9]),.I3(\d_cnst_sn.reg1_16_9_1804_3_tz ),.I4(t_1[28:28]),.I5(N_3614),.LO(reg1_16_9));
defparam desc856.INIT=64'hFFFFFFFF8F88FF88;
LUT6 desc857(.I0(N_7_i),.I1(N_1901),.I2(N_513_i),.I3(N_514_i),.I4(un36_df),.I5(un87_df),.O(reg3_1_sqmuxa));
defparam desc857.INIT=64'h0000000100000000;
LUT6 desc858(.I0(N_7_i),.I1(N_1901),.I2(N_513_i),.I3(N_514_i),.I4(un36_df),.I5(un87_df),.O(reg3_14_sqmuxa));
defparam desc858.INIT=64'h0000100000000000;
LUT6 desc859(.I0(d[0:0]),.I1(d[1:1]),.I2(un1_df_1),.I3(d_cnst),.I4(d_cnst_sm0),.I5(\d_cnst_sn.un1_state_3_1 ),.O(un1_state_3_i));
defparam desc859.INIT=64'h0000000020202F20;
LUT6 desc860(.I0(d[0:0]),.I1(d[1:1]),.I2(un1_df_1),.I3(d_cnst),.I4(d_cnst_sm0),.I5(\d_cnst_sn.un1_state_3_1 ),.O(un1_state_4_i));
defparam desc860.INIT=64'h000000001010101F;
LUT5_L desc861(.I0(m_2[15:15]),.I1(N_3916),.I2(N_1132),.I3(N_1050),.I4(N_1082),.LO(reg0_28[15:15]));
defparam desc861.INIT=32'hAFA3ACA0;
LUT5_L desc862(.I0(m_2[15:15]),.I1(N_3916),.I2(N_1270),.I3(N_1050),.I4(N_1082),.LO(reg1_16[15:15]));
defparam desc862.INIT=32'hAFA3ACA0;
LUT5_L desc863(.I0(m_2[1:1]),.I1(N_3916),.I2(N_1132),.I3(N_1036),.I4(N_1068),.LO(reg0_28[1:1]));
defparam desc863.INIT=32'hAFA3ACA0;
LUT5_L desc864(.I0(m_2[16:16]),.I1(N_3916),.I2(N_1132),.I3(N_1051),.I4(N_1083),.LO(reg0_28[16:16]));
defparam desc864.INIT=32'hAFA3ACA0;
LUT5_L desc865(.I0(m_2[18:18]),.I1(N_3916),.I2(N_1132),.I3(N_1053),.I4(N_1085),.LO(reg0_28[18:18]));
defparam desc865.INIT=32'hAFA3ACA0;
LUT5_L desc866(.I0(m_2[1:1]),.I1(N_3916),.I2(N_1270),.I3(N_1036),.I4(N_1068),.LO(reg1_16[1:1]));
defparam desc866.INIT=32'hAFA3ACA0;
LUT5_L desc867(.I0(m_2[16:16]),.I1(N_3916),.I2(N_1270),.I3(N_1051),.I4(N_1083),.LO(reg1_16[16:16]));
defparam desc867.INIT=32'hAFA3ACA0;
LUT5_L desc868(.I0(m_2[13:13]),.I1(N_3916),.I2(N_1132),.I3(N_1048),.I4(N_1080),.LO(reg0_28[13:13]));
defparam desc868.INIT=32'hAFA3ACA0;
LUT5_L desc869(.I0(m_2[13:13]),.I1(N_3916),.I2(N_1270),.I3(N_1048),.I4(N_1080),.LO(reg1_16[13:13]));
defparam desc869.INIT=32'hAFA3ACA0;
LUT5_L desc870(.I0(m_2[9:9]),.I1(N_3916),.I2(N_1132),.I3(N_1044),.I4(N_1076),.LO(reg0_28[9:9]));
defparam desc870.INIT=32'hAFA3ACA0;
LUT5_L desc871(.I0(m_2[10:10]),.I1(N_3916),.I2(N_1132),.I3(N_1045),.I4(N_1077),.LO(reg0_28[10:10]));
defparam desc871.INIT=32'hAFA3ACA0;
LUT5_L desc872(.I0(m_2[11:11]),.I1(N_3916),.I2(N_1132),.I3(N_1046),.I4(N_1078),.LO(reg0_28[11:11]));
defparam desc872.INIT=32'hAFA3ACA0;
LUT5_L desc873(.I0(m_2[12:12]),.I1(N_3916),.I2(N_1132),.I3(N_1047),.I4(N_1079),.LO(reg0_28[12:12]));
defparam desc873.INIT=32'hAFA3ACA0;
LUT5_L desc874(.I0(m_2[14:14]),.I1(N_3916),.I2(N_1132),.I3(N_1049),.I4(N_1081),.LO(reg0_28[14:14]));
defparam desc874.INIT=32'hAFA3ACA0;
LUT5_L desc875(.I0(m_2[2:2]),.I1(N_3916),.I2(N_1270),.I3(N_1037),.I4(N_1069),.LO(reg1_16[2:2]));
defparam desc875.INIT=32'hAFA3ACA0;
LUT5_L desc876(.I0(m_2[9:9]),.I1(N_3916),.I2(N_1270),.I3(N_1044),.I4(N_1076),.LO(reg1_16[9:9]));
defparam desc876.INIT=32'hAFA3ACA0;
LUT5_L desc877(.I0(m_2[10:10]),.I1(N_3916),.I2(N_1270),.I3(N_1045),.I4(N_1077),.LO(reg1_16[10:10]));
defparam desc877.INIT=32'hAFA3ACA0;
LUT5_L desc878(.I0(m_2[11:11]),.I1(N_3916),.I2(N_1270),.I3(N_1046),.I4(N_1078),.LO(reg1_16[11:11]));
defparam desc878.INIT=32'hAFA3ACA0;
LUT5_L desc879(.I0(m_2[12:12]),.I1(N_3916),.I2(N_1270),.I3(N_1047),.I4(N_1079),.LO(reg1_16[12:12]));
defparam desc879.INIT=32'hAFA3ACA0;
LUT5_L desc880(.I0(m_2[14:14]),.I1(N_3916),.I2(N_1270),.I3(N_1049),.I4(N_1081),.LO(reg1_16[14:14]));
defparam desc880.INIT=32'hAFA3ACA0;
LUT5_L desc881(.I0(m_2[17:17]),.I1(N_3916),.I2(N_1270),.I3(N_1052),.I4(N_1084),.LO(reg1_16[17:17]));
defparam desc881.INIT=32'hAFA3ACA0;
LUT6 desc882(.I0(N_7_i),.I1(N_1901),.I2(N_513_i),.I3(N_514_i),.I4(un1_df_17_2),.I5(rd_4_sqmuxa),.O(reg3_17_sn_N_5));
defparam desc882.INIT=64'h00000000EFFFFFFF;
LUT6 desc883(.I0(state),.I1(N_7_i),.I2(N_1892),.I3(un36_df),.I4(N_1890),.I5(un86_df),.O(un1_state_1_0_i));
defparam desc883.INIT=64'h0002000200000002;
LUT3 desc884(.I0(reg3[1:1]),.I1(reg3_1_1[1:1]),.I2(reg3_1_sqmuxa),.O(N_1689));
defparam desc884.INIT=8'hCA;
LUT3 desc885(.I0(reg3[2:2]),.I1(reg3_1_1[2:2]),.I2(reg3_1_sqmuxa),.O(N_1690));
defparam desc885.INIT=8'hCA;
LUT3 desc886(.I0(reg3[0:0]),.I1(m_2[0:0]),.I2(reg3_1_sqmuxa),.O(N_1688));
defparam desc886.INIT=8'hCA;
LUT6 desc887(.I0(N_513_i),.I1(m_2[18:18]),.I2(N_3916),.I3(reg0_28_7_a1[18:18]),.I4(N_1270),.I5(reg3_1_1[18:18]),.O(\d_cnst_sn.reg1_0 [18:18]));
defparam desc887.INIT=64'hCCCCF0FFCCCCF0FA;
LUT6 desc888(.I0(N_513_i),.I1(m_2[17:17]),.I2(N_3916),.I3(reg0_28_7_a1[17:17]),.I4(N_1132),.I5(reg3_1_1[17:17]),.O(\d_cnst_sn.reg0_0 [17:17]));
defparam desc888.INIT=64'hCCCCF0FFCCCCF0FA;
LUT6 desc889(.I0(\d_cnst_sn.reg1_16_a2_0 [5:5]),.I1(m_2[8:8]),.I2(\d_cnst_sn.reg0_28_a1_1 [4:4]),.I3(r_4[7:7]),.I4(reg3_1_1[8:8]),.I5(N_1132),.O(\d_cnst_sn.reg0_1 [8:8]));
defparam desc889.INIT=64'hCCCCCCCCFF0F5505;
LUT6 desc890(.I0(\d_cnst_sn.reg1_16_a2_0 [5:5]),.I1(m_2[8:8]),.I2(\d_cnst_sn.reg0_28_a1_1 [4:4]),.I3(r_4[7:7]),.I4(reg3_1_1[8:8]),.I5(N_1270),.O(\d_cnst_sn.reg1_1 [8:8]));
defparam desc890.INIT=64'hCCCCCCCCFF0F5505;
LUT6 desc891(.I0(\d_cnst_sn.reg1_16_a2_0 [5:5]),.I1(m_2[6:6]),.I2(\d_cnst_sn.reg0_28_a1_1 [4:4]),.I3(r_4[5:5]),.I4(reg3_1_1[6:6]),.I5(N_1132),.O(\d_cnst_sn.reg0_1 [6:6]));
defparam desc891.INIT=64'hCCCCCCCCFF0F5505;
LUT6 desc892(.I0(\d_cnst_sn.reg1_16_a2_0 [5:5]),.I1(m_2[6:6]),.I2(\d_cnst_sn.reg0_28_a1_1 [4:4]),.I3(r_4[5:5]),.I4(reg3_1_1[6:6]),.I5(N_1270),.O(\d_cnst_sn.reg1_1 [6:6]));
defparam desc892.INIT=64'hCCCCCCCCFF0F5505;
LUT6 desc893(.I0(\d_cnst_sn.reg1_16_a2_0 [5:5]),.I1(m_2[5:5]),.I2(\d_cnst_sn.reg0_28_a1_1 [4:4]),.I3(r_4[4:4]),.I4(reg3_1_1[5:5]),.I5(N_1132),.O(\d_cnst_sn.reg0_1 [5:5]));
defparam desc893.INIT=64'hCCCCCCCCFF0F5505;
LUT6 desc894(.I0(\d_cnst_sn.reg1_16_a2_0 [5:5]),.I1(m_2[5:5]),.I2(\d_cnst_sn.reg0_28_a1_1 [4:4]),.I3(r_4[4:4]),.I4(reg3_1_1[5:5]),.I5(N_1270),.O(\d_cnst_sn.reg1_1 [5:5]));
defparam desc894.INIT=64'hCCCCCCCCFF0F5505;
LUT6 desc895(.I0(\d_cnst_sn.reg1_16_a2_0 [5:5]),.I1(m_2[4:4]),.I2(\d_cnst_sn.reg0_28_a1_1 [4:4]),.I3(r_4[3:3]),.I4(reg3_1_1[4:4]),.I5(N_1270),.O(\d_cnst_sn.reg1_1 [4:4]));
defparam desc895.INIT=64'hCCCCCCCCFF0F5505;
LUT6 desc896(.I0(\d_cnst_sn.reg1_16_a2_0 [5:5]),.I1(m_2[4:4]),.I2(\d_cnst_sn.reg0_28_a1_1 [4:4]),.I3(r_4[3:3]),.I4(reg3_1_1[4:4]),.I5(N_1132),.O(\d_cnst_sn.reg0_1 [4:4]));
defparam desc896.INIT=64'hCCCCCCCCFF0F5505;
LUT6 desc897(.I0(\d_cnst_sn.reg1_16_a2_0 [5:5]),.I1(m_2[3:3]),.I2(\d_cnst_sn.reg0_28_a1_1 [4:4]),.I3(reg3_1_1[3:3]),.I4(N_28),.I5(N_1270),.O(\d_cnst_sn.reg1_1 [3:3]));
defparam desc897.INIT=64'hCCCCCCCCFF550F05;
LUT6 desc898(.I0(\d_cnst_sn.reg1_16_a2_0 [5:5]),.I1(m_2[3:3]),.I2(\d_cnst_sn.reg0_28_a1_1 [4:4]),.I3(reg3_1_1[3:3]),.I4(N_28),.I5(N_1132),.O(\d_cnst_sn.reg0_1 [3:3]));
defparam desc898.INIT=64'hCCCCCCCCFF550F05;
LUT6 desc899(.I0(\d_cnst_sn.reg1_16_a2_0 [5:5]),.I1(m_2[2:2]),.I2(\d_cnst_sn.reg0_28_a1_1 [4:4]),.I3(reg3_1_1[2:2]),.I4(r_4[1:1]),.I5(N_1132),.O(\d_cnst_sn.reg0_1 [2:2]));
defparam desc899.INIT=64'hCCCCCCCCFF550F05;
LUT6_L desc900(.I0(reg3[4:4]),.I1(state),.I2(inf_abs0_2[31:31]),.I3(N_2240_i),.I4(addr_4_sqmuxa_1_1),.I5(N_54),.LO(N_56_i));
defparam desc900.INIT=64'hEE22E222EEEEEEEE;
LUT6_L desc901(.I0(reg3[2:2]),.I1(state),.I2(inf_abs0_2[31:31]),.I3(N_2240_i),.I4(addr_4_sqmuxa_1_1),.I5(N_45),.LO(N_47_i));
defparam desc901.INIT=64'hEE22E222EEEEEEEE;
LUT5 desc902(.I0(reg3[3:3]),.I1(inf_abs0_2[3:3]),.I2(reg3_1_1[3:3]),.I3(rd_4_sqmuxa),.I4(reg3_1_sqmuxa),.O(reg3_N_7_i_RNO));
defparam desc902.INIT=32'h330F33AA;
LUT5 desc903(.I0(un3_reg3_s_1),.I1(inf_abs0_2[4:4]),.I2(reg3_1_1[4:4]),.I3(rd_4_sqmuxa),.I4(reg3_1_sqmuxa),.O(reg3_1_sqmuxa_RNIEMUH1));
defparam desc903.INIT=32'h330F3355;
LUT5 desc904(.I0(un3_reg3_s_2),.I1(inf_abs0_2[5:5]),.I2(reg3_1_1[5:5]),.I3(rd_4_sqmuxa),.I4(reg3_1_sqmuxa),.O(reg3_1_sqmuxa_RNIHMUH1));
defparam desc904.INIT=32'h330F3355;
LUT5 desc905(.I0(un3_reg3_s_4),.I1(inf_abs0_2[7:7]),.I2(reg3_1_1[7:7]),.I3(rd_4_sqmuxa),.I4(reg3_1_sqmuxa),.O(reg3_1_sqmuxa_RNINMUH1));
defparam desc905.INIT=32'h330F3355;
LUT5 desc906(.I0(un3_reg3_s_3),.I1(inf_abs0_2[6:6]),.I2(reg3_1_1[6:6]),.I3(rd_4_sqmuxa),.I4(reg3_1_sqmuxa),.O(reg3_1_sqmuxa_RNIKMUH1));
defparam desc906.INIT=32'h330F3355;
LUT5 desc907(.I0(un3_reg3_s_6),.I1(inf_abs0_2[9:9]),.I2(reg3_1_1[9:9]),.I3(rd_4_sqmuxa),.I4(reg3_1_sqmuxa),.O(reg3_1_sqmuxa_RNITMUH1));
defparam desc907.INIT=32'h330F3355;
LUT5 desc908(.I0(un3_reg3_s_5),.I1(inf_abs0_2[8:8]),.I2(reg3_1_1[8:8]),.I3(rd_4_sqmuxa),.I4(reg3_1_sqmuxa),.O(reg3_1_sqmuxa_RNIQMUH1));
defparam desc908.INIT=32'h330F3355;
LUT5 desc909(.I0(un3_reg3_s_7),.I1(inf_abs0_2[10:10]),.I2(reg3_1_1[10:10]),.I3(rd_4_sqmuxa),.I4(reg3_1_sqmuxa),.O(reg3_1_sqmuxa_RNIE1DM1));
defparam desc909.INIT=32'h330F3355;
LUT5 desc910(.I0(un3_reg3_s_8),.I1(inf_abs0_2[11:11]),.I2(reg3_1_1[11:11]),.I3(rd_4_sqmuxa),.I4(reg3_1_sqmuxa),.O(reg3_1_sqmuxa_RNIH1DM1));
defparam desc910.INIT=32'h330F3355;
LUT5_L desc911(.I0(un1_df_16),.I1(N_1810),.I2(un11_reg0_s_1),.I3(un32_reg0_s_1),.I4(N_1658),.LO(N_1813));
defparam desc911.INIT=32'hFEDC3210;
LUT5_L desc912(.I0(un1_df_16),.I1(N_1810),.I2(N_1684),.I3(un32_reg0_s_27),.I4(un11_reg0_s_27),.LO(N_1839));
defparam desc912.INIT=32'hF3D1E2C0;
LUT5_L desc913(.I0(un1_df_16),.I1(N_1810),.I2(N_1685),.I3(un32_reg0_s_28),.I4(un11_reg0_s_28),.LO(N_1840));
defparam desc913.INIT=32'hF3D1E2C0;
LUT5_L desc914(.I0(un1_df_16),.I1(N_1810),.I2(N_1673),.I3(un32_reg0_s_16),.I4(un11_reg0_s_16),.LO(N_1828));
defparam desc914.INIT=32'hF3D1E2C0;
LUT5 desc915(.I0(un1_df_16),.I1(N_1810),.I2(N_1666),.I3(un32_reg0_s_9),.I4(un11_reg0_s_9),.O(N_1821));
defparam desc915.INIT=32'hF3D1E2C0;
LUT5_L desc916(.I0(un1_df_16),.I1(N_1810),.I2(N_1676),.I3(un32_reg0_s_19),.I4(un11_reg0_s_19),.LO(N_1831));
defparam desc916.INIT=32'hF3D1E2C0;
LUT5_L desc917(.I0(un1_df_16),.I1(N_1810),.I2(N_1677),.I3(un32_reg0_s_20),.I4(un11_reg0_s_20),.LO(N_1832));
defparam desc917.INIT=32'hF3D1E2C0;
LUT5_L desc918(.I0(un1_df_16),.I1(N_1810),.I2(N_1671),.I3(un32_reg0_s_14),.I4(un11_reg0_s_14),.LO(N_1826));
defparam desc918.INIT=32'hF3D1E2C0;
LUT5_L desc919(.I0(un1_df_16),.I1(N_1810),.I2(N_1675),.I3(un32_reg0_s_18),.I4(un11_reg0_s_18),.LO(N_1830));
defparam desc919.INIT=32'hF3D1E2C0;
LUT5 desc920(.I0(un1_df_16),.I1(N_1810),.I2(N_1662),.I3(un32_reg0_s_5),.I4(un11_reg0_s_5),.O(N_1817));
defparam desc920.INIT=32'hF3D1E2C0;
LUT5_L desc921(.I0(un1_df_16),.I1(N_1810),.I2(N_1669),.I3(un32_reg0_s_12),.I4(un11_reg0_s_12),.LO(N_1824));
defparam desc921.INIT=32'hF3D1E2C0;
LUT5_L desc922(.I0(un1_df_16),.I1(N_1810),.I2(N_1674),.I3(un32_reg0_s_17),.I4(un11_reg0_s_17),.LO(N_1829));
defparam desc922.INIT=32'hF3D1E2C0;
LUT5 desc923(.I0(un1_df_16),.I1(N_1810),.I2(N_1667),.I3(un32_reg0_s_10),.I4(un11_reg0_s_10),.O(N_1822));
defparam desc923.INIT=32'hF3D1E2C0;
LUT5 desc924(.I0(un1_df_16),.I1(N_1810),.I2(N_1668),.I3(un32_reg0_s_11),.I4(un11_reg0_s_11),.O(N_1823));
defparam desc924.INIT=32'hF3D1E2C0;
LUT5_L desc925(.I0(un1_df_16),.I1(N_1810),.I2(un11_reg0_s_2),.I3(un32_reg0_s_2),.I4(N_1659),.LO(N_1814));
defparam desc925.INIT=32'hFEDC3210;
LUT5 desc926(.I0(un1_df_16),.I1(N_1810),.I2(N_1663),.I3(un32_reg0_s_6),.I4(un11_reg0_s_6),.O(N_1818));
defparam desc926.INIT=32'hF3D1E2C0;
LUT5 desc927(.I0(un1_df_16),.I1(N_1810),.I2(N_1665),.I3(un32_reg0_s_8),.I4(un11_reg0_s_8),.O(N_1820));
defparam desc927.INIT=32'hF3D1E2C0;
LUT5 desc928(.I0(un1_df_16),.I1(N_1810),.I2(un32_reg0_s_3),.I3(un11_reg0_s_3),.I4(N_1660),.O(N_1815));
defparam desc928.INIT=32'hFDEC3120;
LUT5_L desc929(.I0(un1_df_16),.I1(N_1810),.I2(N_1672),.I3(un32_reg0_s_15),.I4(un11_reg0_s_15),.LO(N_1827));
defparam desc929.INIT=32'hF3D1E2C0;
LUT5_L desc930(.I0(un1_df_16),.I1(N_1810),.I2(N_1683),.I3(un32_reg0_s_26),.I4(un11_reg0_s_26),.LO(N_1838));
defparam desc930.INIT=32'hF3D1E2C0;
LUT5_L desc931(.I0(un1_df_16),.I1(N_1810),.I2(N_1682),.I3(un32_reg0_s_25),.I4(un11_reg0_s_25),.LO(N_1837));
defparam desc931.INIT=32'hF3D1E2C0;
LUT5 desc932(.I0(un1_df_16),.I1(N_1810),.I2(N_1664),.I3(un32_reg0_s_7),.I4(un11_reg0_s_7),.O(N_1819));
defparam desc932.INIT=32'hF3D1E2C0;
LUT5 desc933(.I0(un1_df_16),.I1(N_1810),.I2(N_1661),.I3(un32_reg0_s_4),.I4(un11_reg0_s_4),.O(N_1816));
defparam desc933.INIT=32'hF3D1E2C0;
LUT6 desc934(.I0(un3_reg3_s_25),.I1(\d_cnst_sn.reg3_17_4_a2_0 [28:28]),.I2(rd_4_sqmuxa),.I3(reg3_1_1[28:28]),.I4(reg3_1_sqmuxa),.I5(reg3_14_sqmuxa),.O(\d_cnst_sn.reg3_17_6_0 [28:28]));
defparam desc934.INIT=64'hCCCCCCCC0F000A0A;
LUT6 desc935(.I0(un3_reg3_s_24),.I1(\d_cnst_sn.reg3_17_4_a2_0 [27:27]),.I2(rd_4_sqmuxa),.I3(reg3_1_1[27:27]),.I4(reg3_1_sqmuxa),.I5(reg3_14_sqmuxa),.O(\d_cnst_sn.reg3_17_6_0 [27:27]));
defparam desc935.INIT=64'hCCCCCCCC0F000A0A;
LUT6 desc936(.I0(un3_reg3_s_15),.I1(reg3_1_1[18:18]),.I2(rd_4_sqmuxa),.I3(reg3_1_sqmuxa),.I4(reg3_14_sqmuxa),.I5(\d_cnst_sn.reg3_17_6_0 [18:18]),.O(\d_cnst_sn.reg3_17_6_1 [18:18]));
defparam desc936.INIT=64'hFFFFFCFA00000000;
LUT6 desc937(.I0(un3_reg3_s_16),.I1(reg3_1_1[19:19]),.I2(rd_4_sqmuxa),.I3(reg3_1_sqmuxa),.I4(reg3_14_sqmuxa),.I5(\d_cnst_sn.reg3_17_6_0 [19:19]),.O(\d_cnst_sn.reg3_17_6_1 [19:19]));
defparam desc937.INIT=64'hFFFFFCFA00000000;
LUT6 desc938(.I0(un3_reg3_s_23),.I1(\d_cnst_sn.reg3_17_4_a2_0 [26:26]),.I2(rd_4_sqmuxa),.I3(reg3_1_1[26:26]),.I4(reg3_1_sqmuxa),.I5(reg3_14_sqmuxa),.O(\d_cnst_sn.reg3_17_6_0 [26:26]));
defparam desc938.INIT=64'hCCCCCCCC0F000A0A;
LUT6 desc939(.I0(un3_reg3_s_14),.I1(reg3_1_1[17:17]),.I2(rd_4_sqmuxa),.I3(reg3_1_sqmuxa),.I4(reg3_14_sqmuxa),.I5(\d_cnst_sn.reg3_17_6_0 [17:17]),.O(\d_cnst_sn.reg3_17_6_1 [17:17]));
defparam desc939.INIT=64'hFFFFFCFA00000000;
LUT6 desc940(.I0(un3_reg3_s_22),.I1(\d_cnst_sn.reg3_17_4_a2_0 [25:25]),.I2(rd_4_sqmuxa),.I3(reg3_1_1[25:25]),.I4(reg3_1_sqmuxa),.I5(reg3_14_sqmuxa),.O(\d_cnst_sn.reg3_17_6_0 [25:25]));
defparam desc940.INIT=64'hCCCCCCCC0F000A0A;
LUT6 desc941(.I0(un3_reg3_s_13),.I1(reg3_1_1[16:16]),.I2(rd_4_sqmuxa),.I3(reg3_1_sqmuxa),.I4(reg3_14_sqmuxa),.I5(\d_cnst_sn.reg3_17_6_0 [16:16]),.O(\d_cnst_sn.reg3_17_6_1 [16:16]));
defparam desc941.INIT=64'hFFFFFCFA00000000;
LUT6 desc942(.I0(un3_reg3_s_12),.I1(reg3_1_1[15:15]),.I2(rd_4_sqmuxa),.I3(reg3_1_sqmuxa),.I4(reg3_14_sqmuxa),.I5(\d_cnst_sn.reg3_17_6_0 [15:15]),.O(\d_cnst_sn.reg3_17_6_1 [15:15]));
defparam desc942.INIT=64'hFFFFFCFA00000000;
LUT6 desc943(.I0(un3_reg3_s_11),.I1(reg3_1_1[14:14]),.I2(rd_4_sqmuxa),.I3(reg3_1_sqmuxa),.I4(reg3_14_sqmuxa),.I5(\d_cnst_sn.reg3_17_6_0 [14:14]),.O(\d_cnst_sn.reg3_17_6_1 [14:14]));
defparam desc943.INIT=64'hFFFFFCFA00000000;
LUT6 desc944(.I0(un3_reg3_s_10),.I1(reg3_1_1[13:13]),.I2(rd_4_sqmuxa),.I3(reg3_1_sqmuxa),.I4(reg3_14_sqmuxa),.I5(\d_cnst_sn.reg3_17_6_0 [13:13]),.O(\d_cnst_sn.reg3_17_6_1 [13:13]));
defparam desc944.INIT=64'hFFFFFCFA00000000;
LUT6 desc945(.I0(un3_reg3_s_17),.I1(\d_cnst_sn.reg3_17_4_a2_0 [20:20]),.I2(reg3_1_1[20:20]),.I3(rd_4_sqmuxa),.I4(reg3_1_sqmuxa),.I5(reg3_14_sqmuxa),.O(\d_cnst_sn.reg3_17_6_0 [20:20]));
defparam desc945.INIT=64'hCCCCCCCC00F000AA;
LUT6 desc946(.I0(un3_reg3_s_9),.I1(reg3_1_1[12:12]),.I2(rd_4_sqmuxa),.I3(reg3_1_sqmuxa),.I4(reg3_14_sqmuxa),.I5(\d_cnst_sn.reg3_17_6_0 [12:12]),.O(\d_cnst_sn.reg3_17_6_1 [12:12]));
defparam desc946.INIT=64'hFFFFFCFA00000000;
LUT6 desc947(.I0(un3_reg3_s_21),.I1(reg3_1_1[24:24]),.I2(N_1810),.I3(\d_cnst_sn.reg3_17_sn_m7_0 ),.I4(reg3_1_sqmuxa),.I5(reg3_17_sn_N_5),.O(reg3_17_a0[24:24]));
defparam desc947.INIT=64'hC000A00000000000;
LUT6 desc948(.I0(un3_reg3_s_20),.I1(reg3_1_1[23:23]),.I2(N_1810),.I3(\d_cnst_sn.reg3_17_sn_m7_0 ),.I4(reg3_1_sqmuxa),.I5(reg3_17_sn_N_5),.O(reg3_17_a0[23:23]));
defparam desc948.INIT=64'hC000A00000000000;
LUT6 desc949(.I0(un3_reg3_s_19),.I1(reg3_1_1[22:22]),.I2(N_1810),.I3(\d_cnst_sn.reg3_17_sn_m7_0 ),.I4(reg3_1_sqmuxa),.I5(reg3_17_sn_N_5),.O(reg3_17_a0[22:22]));
defparam desc949.INIT=64'hC000A00000000000;
LUT6 desc950(.I0(un3_reg3_s_18),.I1(reg3_1_1[21:21]),.I2(N_1810),.I3(\d_cnst_sn.reg3_17_sn_m7_0 ),.I4(reg3_1_sqmuxa),.I5(reg3_17_sn_N_5),.O(reg3_17_a0[21:21]));
defparam desc950.INIT=64'hC000A00000000000;
LUT6_L desc951(.I0(N_1810),.I1(\d_cnst_sn.reg3_17_sn_m7_0 ),.I2(reg3_17_sn_N_5),.I3(N_1689),.I4(N_1751),.I5(N_1813),.LO(reg3_17[1:1]));
defparam desc951.INIT=64'hFF7FF77788088000;
LUT5_L desc952(.I0(reg3_17_sn_N_5),.I1(N_1690),.I2(N_1841),.I3(N_1752),.I4(N_1814),.LO(reg3_17[2:2]));
defparam desc952.INIT=32'hDF8FD080;
LUT6_L desc953(.I0(N_1810),.I1(\d_cnst_sn.reg3_17_sn_m7_0 ),.I2(reg3_17_sn_N_5),.I3(N_1812),.I4(N_1688),.I5(N_1750),.LO(reg3_17[0:0]));
defparam desc953.INIT=64'hFF887F08F7807700;
LUT6_L desc954(.I0(\d_cnst_sn.b64_0 ),.I1(\d_cnst_sn.b60_0 ),.I2(\d_cnst_sn.reg1_16_a0_1 [3:3]),.I3(\d_cnst_sn.reg0_1 [3:3]),.I4(t_1[3:3]),.I5(N_1038),.LO(reg0_28[3:3]));
defparam desc954.INIT=64'h0F00FF0001001100;
LUT6_L desc955(.I0(\d_cnst_sn.b64_0 ),.I1(\d_cnst_sn.b60_0 ),.I2(\d_cnst_sn.reg1_16_a0_1 [3:3]),.I3(\d_cnst_sn.reg0_1 [2:2]),.I4(t_1[2:2]),.I5(N_1037),.LO(reg0_28[2:2]));
defparam desc955.INIT=64'h0F00FF0001001100;
LUT6_L desc956(.I0(\d_cnst_sn.b64_0 ),.I1(\d_cnst_sn.b60_0 ),.I2(\d_cnst_sn.reg1_16_a0_1 [3:3]),.I3(\d_cnst_sn.reg1_1 [3:3]),.I4(t_1[3:3]),.I5(N_1038),.LO(reg1_16[3:3]));
defparam desc956.INIT=64'h0F00FF0001001100;
LUT6_L desc957(.I0(\d_cnst_sn.b64_0 ),.I1(\d_cnst_sn.b60_0 ),.I2(\d_cnst_sn.reg1_16_a0_1 [3:3]),.I3(\d_cnst_sn.reg0_1 [8:8]),.I4(t_1[8:8]),.I5(N_1043),.LO(reg0_28[8:8]));
defparam desc957.INIT=64'h0F00FF0001001100;
LUT6_L desc958(.I0(\d_cnst_sn.b64_0 ),.I1(\d_cnst_sn.b60_0 ),.I2(\d_cnst_sn.reg1_16_a0_1 [3:3]),.I3(\d_cnst_sn.reg1_1 [8:8]),.I4(t_1[8:8]),.I5(N_1043),.LO(reg1_16[8:8]));
defparam desc958.INIT=64'h0F00FF0001001100;
LUT6_L desc959(.I0(\d_cnst_sn.b64_0 ),.I1(\d_cnst_sn.b60_0 ),.I2(\d_cnst_sn.reg1_16_a0_1 [3:3]),.I3(\d_cnst_sn.reg1_1 [6:6]),.I4(t_1[6:6]),.I5(N_1041),.LO(reg1_16[6:6]));
defparam desc959.INIT=64'h0F00FF0001001100;
LUT6_L desc960(.I0(\d_cnst_sn.b64_0 ),.I1(\d_cnst_sn.b60_0 ),.I2(\d_cnst_sn.reg1_16_a0_1 [3:3]),.I3(\d_cnst_sn.reg0_1 [5:5]),.I4(t_1[5:5]),.I5(N_1040),.LO(reg0_28[5:5]));
defparam desc960.INIT=64'h0F00FF0001001100;
LUT6_L desc961(.I0(\d_cnst_sn.b64_0 ),.I1(\d_cnst_sn.b60_0 ),.I2(\d_cnst_sn.reg1_16_a0_1 [3:3]),.I3(\d_cnst_sn.reg0_1 [6:6]),.I4(t_1[6:6]),.I5(N_1041),.LO(reg0_28[6:6]));
defparam desc961.INIT=64'h0F00FF0001001100;
LUT6_L desc962(.I0(\d_cnst_sn.b64_0 ),.I1(\d_cnst_sn.b60_0 ),.I2(\d_cnst_sn.reg1_16_a0_1 [3:3]),.I3(\d_cnst_sn.reg1_1 [4:4]),.I4(t_1[4:4]),.I5(N_1039),.LO(reg1_16[4:4]));
defparam desc962.INIT=64'h0F00FF0001001100;
LUT6_L desc963(.I0(\d_cnst_sn.b64_0 ),.I1(\d_cnst_sn.b60_0 ),.I2(\d_cnst_sn.reg1_16_a0_1 [3:3]),.I3(\d_cnst_sn.reg1_1 [5:5]),.I4(t_1[5:5]),.I5(N_1040),.LO(reg1_16[5:5]));
defparam desc963.INIT=64'h0F00FF0001001100;
LUT6_L desc964(.I0(\d_cnst_sn.b64_0 ),.I1(\d_cnst_sn.b60_0 ),.I2(\d_cnst_sn.reg1_16_a0_1 [3:3]),.I3(\d_cnst_sn.reg0_1 [4:4]),.I4(t_1[4:4]),.I5(N_1039),.LO(reg0_28[4:4]));
defparam desc964.INIT=64'h0F00FF0001001100;
LUT6_L desc965(.I0(N_1810),.I1(\d_cnst_sn.reg3_17_sn_m7_0 ),.I2(reg3_14_sqmuxa),.I3(reg3_1_sqmuxa_RNIEMUH1),.I4(N_1816),.I5(r_4_2_a1_lut6_2_RNI2T8R3[3:3]),.LO(reg3_17[4:4]));
defparam desc965.INIT=64'h777F0008F7FF8088;
LUT6_L desc966(.I0(N_1810),.I1(\d_cnst_sn.reg3_17_sn_m7_0 ),.I2(reg3_14_sqmuxa),.I3(reg3_1_sqmuxa_RNIHMUH1),.I4(N_1817),.I5(r_4_2_a1_lut6_2_RNI5V8R3[3:3]),.LO(reg3_17[5:5]));
defparam desc966.INIT=64'h777F0008F7FF8088;
LUT6_L desc967(.I0(N_1810),.I1(\d_cnst_sn.reg3_17_sn_m7_0 ),.I2(reg3_14_sqmuxa),.I3(reg3_1_sqmuxa_RNINMUH1),.I4(N_1819),.I5(r_4_1_RNICM731[6:6]),.LO(reg3_17[7:7]));
defparam desc967.INIT=64'h777F0008F7FF8088;
LUT6_L desc968(.I0(N_1810),.I1(\d_cnst_sn.reg3_17_sn_m7_0 ),.I2(reg3_14_sqmuxa),.I3(reg3_1_sqmuxa_RNIKMUH1),.I4(N_1818),.I5(r_4_1_RNI9K731[5:5]),.LO(reg3_17[6:6]));
defparam desc968.INIT=64'h777F0008F7FF8088;
LUT6_L desc969(.I0(N_1810),.I1(\d_cnst_sn.reg3_17_sn_m7_0 ),.I2(reg3_14_sqmuxa),.I3(reg3_1_sqmuxa_RNITMUH1),.I4(N_1821),.I5(r_4_1_RNIIQ731[8:8]),.LO(reg3_17[9:9]));
defparam desc969.INIT=64'h777F0008F7FF8088;
LUT6_L desc970(.I0(N_1810),.I1(\d_cnst_sn.reg3_17_sn_m7_0 ),.I2(reg3_14_sqmuxa),.I3(reg3_1_sqmuxa_RNIQMUH1),.I4(N_1820),.I5(r_4_1_RNIFO731[7:7]),.LO(reg3_17[8:8]));
defparam desc970.INIT=64'h777F0008F7FF8088;
LUT6_L desc971(.I0(N_1810),.I1(\d_cnst_sn.reg3_17_sn_m7_0 ),.I2(reg3_14_sqmuxa),.I3(reg3_1_sqmuxa_RNIE1DM1),.I4(N_1822),.I5(r_4_1_RNIS3K91[9:9]),.LO(reg3_17[10:10]));
defparam desc971.INIT=64'h777F0008F7FF8088;
LUT6_L desc972(.I0(N_1810),.I1(\d_cnst_sn.reg3_17_sn_m7_0 ),.I2(reg3_14_sqmuxa),.I3(reg3_1_sqmuxa_RNIH1DM1),.I4(N_1823),.I5(r_4_1_RNIDBOH1[10:10]),.LO(reg3_17[11:11]));
defparam desc972.INIT=64'h777F0008F7FF8088;
LUT6_L desc973(.I0(N_1810),.I1(\d_cnst_sn.reg3_17_sn_m7_0 ),.I2(N_1670),.I3(\d_cnst_sn.reg3_17_6_1 [13:13]),.I4(N_1732),.I5(reg3_17_4_a2[13:13]),.LO(reg3_17[13:13]));
defparam desc973.INIT=64'h75752020FD75A820;
LUT6_L desc974(.I0(N_527_i),.I1(reg3_14_sqmuxa),.I2(\d_cnst_sn.reg3_17_6_0 [27:27]),.I3(N_1841),.I4(t_1[27:27]),.I5(N_1839),.LO(reg3_17[27:27]));
defparam desc974.INIT=64'hF0FFF4FFF000F400;
LUT6_L desc975(.I0(N_527_i),.I1(reg3_14_sqmuxa),.I2(\d_cnst_sn.reg3_17_6_0 [28:28]),.I3(N_1841),.I4(t_1[28:28]),.I5(N_1840),.LO(reg3_17[28:28]));
defparam desc975.INIT=64'hF0FFF4FFF000F400;
LUT6_L desc976(.I0(N_527_i),.I1(reg3_14_sqmuxa),.I2(N_1841),.I3(\d_cnst_sn.reg3_17_6_1 [16:16]),.I4(t_1[16:16]),.I5(N_1828),.LO(reg3_17[16:16]));
defparam desc976.INIT=64'hBF0FFF0FB000F000;
LUT6_L desc977(.I0(N_527_i),.I1(reg3_14_sqmuxa),.I2(N_1841),.I3(\d_cnst_sn.reg3_17_6_1 [19:19]),.I4(t_1[19:19]),.I5(N_1831),.LO(reg3_17[19:19]));
defparam desc977.INIT=64'hBF0FFF0FB000F000;
LUT6_L desc978(.I0(N_527_i),.I1(reg3_14_sqmuxa),.I2(\d_cnst_sn.reg3_17_6_0 [20:20]),.I3(N_1841),.I4(t_1[20:20]),.I5(N_1832),.LO(reg3_17[20:20]));
defparam desc978.INIT=64'hF0FFF4FFF000F400;
LUT6_L desc979(.I0(N_527_i),.I1(reg3_14_sqmuxa),.I2(t_1[14:14]),.I3(N_1841),.I4(\d_cnst_sn.reg3_17_6_1 [14:14]),.I5(N_1826),.LO(reg3_17[14:14]));
defparam desc979.INIT=64'hBFFF00FFBF000000;
LUT6_L desc980(.I0(N_527_i),.I1(reg3_14_sqmuxa),.I2(N_1841),.I3(\d_cnst_sn.reg3_17_6_1 [18:18]),.I4(t_1[18:18]),.I5(N_1830),.LO(reg3_17[18:18]));
defparam desc980.INIT=64'hBF0FFF0FB000F000;
LUT6_L desc981(.I0(N_527_i),.I1(reg3_14_sqmuxa),.I2(t_1[12:12]),.I3(N_1841),.I4(\d_cnst_sn.reg3_17_6_1 [12:12]),.I5(N_1824),.LO(reg3_17[12:12]));
defparam desc981.INIT=64'hBFFF00FFBF000000;
LUT6_L desc982(.I0(N_527_i),.I1(reg3_14_sqmuxa),.I2(N_1841),.I3(\d_cnst_sn.reg3_17_6_1 [17:17]),.I4(t_1[17:17]),.I5(N_1829),.LO(reg3_17[17:17]));
defparam desc982.INIT=64'hBF0FFF0FB000F000;
LUT6_L desc983(.I0(N_527_i),.I1(reg3_14_sqmuxa),.I2(N_1841),.I3(\d_cnst_sn.reg3_17_6_1 [15:15]),.I4(t_1[15:15]),.I5(N_1827),.LO(reg3_17[15:15]));
defparam desc983.INIT=64'hBF0FFF0FB000F000;
LUT6_L desc984(.I0(N_527_i),.I1(reg3_14_sqmuxa),.I2(\d_cnst_sn.reg3_17_6_0 [26:26]),.I3(N_1841),.I4(t_1[26:26]),.I5(N_1838),.LO(reg3_17[26:26]));
defparam desc984.INIT=64'hF0FFF4FFF000F400;
LUT6_L desc985(.I0(N_527_i),.I1(reg3_14_sqmuxa),.I2(\d_cnst_sn.reg3_17_6_0 [25:25]),.I3(N_1841),.I4(t_1[25:25]),.I5(N_1837),.LO(reg3_17[25:25]));
defparam desc985.INIT=64'hF0FFF4FFF000F400;
LUT6_L desc986(.I0(N_1810),.I1(reg3_17_a0[24:24]),.I2(\d_cnst_sn.reg3_17_a1_2 [24:24]),.I3(\d_cnst_sn.reg3_17_0_tz [24:24]),.I4(t_1[24:24]),.I5(N_1743),.LO(reg3_17[24:24]));
defparam desc986.INIT=64'hFFDDFFFDEECCFEFC;
LUT6_L desc987(.I0(N_1810),.I1(reg3_17_a0[23:23]),.I2(\d_cnst_sn.reg3_17_a1_2 [24:24]),.I3(\d_cnst_sn.reg3_17_0_tz [23:23]),.I4(t_1[23:23]),.I5(N_1742),.LO(reg3_17[23:23]));
defparam desc987.INIT=64'hFFDDFFFDEECCFEFC;
LUT6_L desc988(.I0(N_1810),.I1(reg3_17_a0[22:22]),.I2(\d_cnst_sn.reg3_17_a1_2 [24:24]),.I3(\d_cnst_sn.reg3_17_0_tz [22:22]),.I4(t_1[22:22]),.I5(N_1741),.LO(reg3_17[22:22]));
defparam desc988.INIT=64'hFFDDFFFDEECCFEFC;
LUT6_L desc989(.I0(N_1810),.I1(\d_cnst_sn.reg3_17_0_tz [21:21]),.I2(reg3_17_a0[21:21]),.I3(\d_cnst_sn.reg3_17_a1_2 [24:24]),.I4(t_1[21:21]),.I5(N_1740),.LO(reg3_17[21:21]));
defparam desc989.INIT=64'hFDFDFFFDF8F8FFF8;
LUT6_L desc990(.I0(N_1810),.I1(\d_cnst_sn.reg3_17_sn_m7_0 ),.I2(reg3_14_sqmuxa),.I3(reg3_N_7_i_RNO),.I4(N_1815),.I5(t_6[3:3]),.LO(\d_cnst_sn.reg3_N_7_i ));
defparam desc990.INIT=64'hF7FF8088777F0008;
LUT5 desc991(.I0(datai[20:20]),.I1(inf_abs0_2[31:31]),.I2(inf_abs0_2[27:27]),.I3(inf_abs0_2[28:28]),.I4(r_4[20:20]),.O(un11_reg0_axb_20));
defparam desc991.INIT=32'hDDDF2220;
LUT4 desc992(.I0(datai[20:20]),.I1(inf_abs0_2[31:31]),.I2(inf_abs0_2[27:27]),.I3(inf_abs0_2[28:28]),.O(m_2[20:20]));
defparam desc992.INIT=16'h2220;
LUT5 desc993(.I0(datai[21:21]),.I1(inf_abs0_2[31:31]),.I2(inf_abs0_2[27:27]),.I3(inf_abs0_2[28:28]),.I4(r_4[21:21]),.O(un11_reg0_axb_21));
defparam desc993.INIT=32'hDDDF2220;
LUT4 desc994(.I0(datai[21:21]),.I1(inf_abs0_2[31:31]),.I2(inf_abs0_2[27:27]),.I3(inf_abs0_2[28:28]),.O(m_2[21:21]));
defparam desc994.INIT=16'h2220;
LUT5 desc995(.I0(datai[22:22]),.I1(inf_abs0_2[31:31]),.I2(inf_abs0_2[27:27]),.I3(inf_abs0_2[28:28]),.I4(r_4[22:22]),.O(un11_reg0_axb_22));
defparam desc995.INIT=32'hDDDF2220;
LUT4 desc996(.I0(datai[22:22]),.I1(inf_abs0_2[31:31]),.I2(inf_abs0_2[27:27]),.I3(inf_abs0_2[28:28]),.O(m_2[22:22]));
defparam desc996.INIT=16'h2220;
LUT5 desc997(.I0(datai[23:23]),.I1(inf_abs0_2[31:31]),.I2(inf_abs0_2[27:27]),.I3(inf_abs0_2[28:28]),.I4(r_4[23:23]),.O(un11_reg0_axb_23));
defparam desc997.INIT=32'hDDDF2220;
LUT4 desc998(.I0(datai[23:23]),.I1(inf_abs0_2[31:31]),.I2(inf_abs0_2[27:27]),.I3(inf_abs0_2[28:28]),.O(m_2[23:23]));
defparam desc998.INIT=16'h2220;
LUT5 desc999(.I0(datai[24:24]),.I1(inf_abs0_2[31:31]),.I2(inf_abs0_2[27:27]),.I3(inf_abs0_2[28:28]),.I4(r_4[24:24]),.O(un11_reg0_axb_24));
defparam desc999.INIT=32'hDDDF2220;
LUT4 desc1000(.I0(datai[24:24]),.I1(inf_abs0_2[31:31]),.I2(inf_abs0_2[27:27]),.I3(inf_abs0_2[28:28]),.O(m_2[24:24]));
defparam desc1000.INIT=16'h2220;
LUT5 desc1001(.I0(datai[25:25]),.I1(inf_abs0_2[31:31]),.I2(inf_abs0_2[27:27]),.I3(inf_abs0_2[28:28]),.I4(r_4[25:25]),.O(un11_reg0_axb_25));
defparam desc1001.INIT=32'hDDDF2220;
LUT4 desc1002(.I0(datai[25:25]),.I1(inf_abs0_2[31:31]),.I2(inf_abs0_2[27:27]),.I3(inf_abs0_2[28:28]),.O(m_2[25:25]));
defparam desc1002.INIT=16'h2220;
LUT5 desc1003(.I0(datai[26:26]),.I1(inf_abs0_2[31:31]),.I2(inf_abs0_2[27:27]),.I3(inf_abs0_2[28:28]),.I4(r_4[26:26]),.O(un11_reg0_axb_26));
defparam desc1003.INIT=32'hDDDF2220;
LUT4 desc1004(.I0(datai[26:26]),.I1(inf_abs0_2[31:31]),.I2(inf_abs0_2[27:27]),.I3(inf_abs0_2[28:28]),.O(m_2[26:26]));
defparam desc1004.INIT=16'h2220;
LUT5 desc1005(.I0(datai[27:27]),.I1(inf_abs0_2[31:31]),.I2(inf_abs0_2[27:27]),.I3(inf_abs0_2[28:28]),.I4(r_4[27:27]),.O(un11_reg0_axb_27));
defparam desc1005.INIT=32'hDDDF2220;
LUT4 desc1006(.I0(datai[27:27]),.I1(inf_abs0_2[31:31]),.I2(inf_abs0_2[27:27]),.I3(inf_abs0_2[28:28]),.O(m_2[27:27]));
defparam desc1006.INIT=16'h2220;
LUT5 desc1007(.I0(datai[28:28]),.I1(inf_abs0_2[31:31]),.I2(inf_abs0_2[27:27]),.I3(inf_abs0_2[28:28]),.I4(r_4[28:28]),.O(un11_reg0_axb_28));
defparam desc1007.INIT=32'hDDDF2220;
LUT4 desc1008(.I0(datai[28:28]),.I1(inf_abs0_2[31:31]),.I2(inf_abs0_2[27:27]),.I3(inf_abs0_2[28:28]),.O(m_2[28:28]));
defparam desc1008.INIT=16'h2220;
LUT5 desc1009(.I0(inf_abs0_2[31:31]),.I1(inf_abs0_2[29:29]),.I2(N_920),.I3(N_952),.I4(m_2[5:5]),.O(un32_reg0_axb_5));
defparam desc1009.INIT=32'hF4B00B4F;
LUT5 desc1010(.I0(inf_abs0_2[31:31]),.I1(inf_abs0_2[29:29]),.I2(N_921),.I3(N_953),.I4(m_2[6:6]),.O(un32_reg0_axb_6));
defparam desc1010.INIT=32'hF4B00B4F;
LUT5 desc1011(.I0(inf_abs0_2[31:31]),.I1(inf_abs0_2[29:29]),.I2(N_922),.I3(N_954),.I4(m_2[7:7]),.O(un32_reg0_axb_7));
defparam desc1011.INIT=32'hF4B00B4F;
LUT5 desc1012(.I0(inf_abs0_2[31:31]),.I1(inf_abs0_2[29:29]),.I2(N_923),.I3(N_955),.I4(m_2[8:8]),.O(un32_reg0_axb_8));
defparam desc1012.INIT=32'hF4B00B4F;
LUT5 desc1013(.I0(inf_abs0_2[31:31]),.I1(inf_abs0_2[29:29]),.I2(N_924),.I3(N_956),.I4(m_2[9:9]),.O(un32_reg0_axb_9));
defparam desc1013.INIT=32'hF4B00B4F;
LUT5 desc1014(.I0(inf_abs0_2[31:31]),.I1(inf_abs0_2[29:29]),.I2(N_925),.I3(N_957),.I4(m_2[10:10]),.O(un32_reg0_axb_10));
defparam desc1014.INIT=32'hF4B00B4F;
LUT5 desc1015(.I0(inf_abs0_2[31:31]),.I1(inf_abs0_2[29:29]),.I2(N_926),.I3(N_958),.I4(m_2[11:11]),.O(un32_reg0_axb_11));
defparam desc1015.INIT=32'hF4B00B4F;
LUT5 desc1016(.I0(inf_abs0_2[31:31]),.I1(inf_abs0_2[29:29]),.I2(N_927),.I3(N_959),.I4(m_2[12:12]),.O(un32_reg0_axb_12));
defparam desc1016.INIT=32'hF4B00B4F;
LUT5 desc1017(.I0(inf_abs0_2[31:31]),.I1(inf_abs0_2[29:29]),.I2(N_928),.I3(N_960),.I4(m_2[13:13]),.O(un32_reg0_axb_13));
defparam desc1017.INIT=32'hF4B00B4F;
LUT5 desc1018(.I0(inf_abs0_2[31:31]),.I1(inf_abs0_2[29:29]),.I2(N_929),.I3(N_961),.I4(m_2[14:14]),.O(un32_reg0_axb_14));
defparam desc1018.INIT=32'hF4B00B4F;
LUT5 desc1019(.I0(inf_abs0_2[31:31]),.I1(inf_abs0_2[29:29]),.I2(N_930),.I3(N_962),.I4(m_2[15:15]),.O(un32_reg0_axb_15));
defparam desc1019.INIT=32'hF4B00B4F;
LUT5 desc1020(.I0(inf_abs0_2[31:31]),.I1(inf_abs0_2[29:29]),.I2(N_931),.I3(N_963),.I4(m_2[16:16]),.O(un32_reg0_axb_16));
defparam desc1020.INIT=32'hF4B00B4F;
LUT5 desc1021(.I0(inf_abs0_2[31:31]),.I1(inf_abs0_2[29:29]),.I2(N_932),.I3(N_964),.I4(m_2[17:17]),.O(un32_reg0_axb_17));
defparam desc1021.INIT=32'hF4B00B4F;
LUT5 desc1022(.I0(inf_abs0_2[31:31]),.I1(inf_abs0_2[29:29]),.I2(N_933),.I3(N_965),.I4(m_2[18:18]),.O(un32_reg0_axb_18));
defparam desc1022.INIT=32'hF4B00B4F;
LUT5 desc1023(.I0(inf_abs0_2[31:31]),.I1(inf_abs0_2[29:29]),.I2(N_934),.I3(N_2722),.I4(m_2[19:19]),.O(un32_reg0_axb_19));
defparam desc1023.INIT=32'hF4B00B4F;
XORCY t_1_s_31(.LI(r_4[31:31]),.CI(t_1_cry_30),.O(t_1[31:31]));
XORCY t_1_s_30(.LI(N_4571_i),.CI(t_1_cry_29),.O(t_1[30:30]));
MUXCY_L t_1_cry_30_cZ(.DI(VCC),.CI(t_1_cry_29),.S(N_4571_i),.LO(t_1_cry_30));
XORCY t_1_s_29(.LI(N_4570_i),.CI(t_1_cry_28),.O(t_1[29:29]));
MUXCY_L t_1_cry_29_cZ(.DI(VCC),.CI(t_1_cry_28),.S(N_4570_i),.LO(t_1_cry_29));
XORCY t_1_s_28(.LI(N_4569_i),.CI(t_1_cry_27),.O(t_1[28:28]));
MUXCY_L t_1_cry_28_cZ(.DI(VCC),.CI(t_1_cry_27),.S(N_4569_i),.LO(t_1_cry_28));
XORCY t_1_s_27(.LI(N_4568_i),.CI(t_1_cry_26),.O(t_1[27:27]));
MUXCY_L t_1_cry_27_cZ(.DI(VCC),.CI(t_1_cry_26),.S(N_4568_i),.LO(t_1_cry_27));
XORCY t_1_s_26(.LI(N_4567_i),.CI(t_1_cry_25),.O(t_1[26:26]));
MUXCY_L t_1_cry_26_cZ(.DI(VCC),.CI(t_1_cry_25),.S(N_4567_i),.LO(t_1_cry_26));
XORCY t_1_s_25(.LI(N_4566_i),.CI(t_1_cry_24),.O(t_1[25:25]));
MUXCY_L t_1_cry_25_cZ(.DI(VCC),.CI(t_1_cry_24),.S(N_4566_i),.LO(t_1_cry_25));
XORCY t_1_s_24(.LI(N_4565_i),.CI(t_1_cry_23),.O(t_1[24:24]));
MUXCY_L t_1_cry_24_cZ(.DI(VCC),.CI(t_1_cry_23),.S(N_4565_i),.LO(t_1_cry_24));
XORCY t_1_s_23(.LI(N_4564_i),.CI(t_1_cry_22),.O(t_1[23:23]));
MUXCY_L t_1_cry_23_cZ(.DI(VCC),.CI(t_1_cry_22),.S(N_4564_i),.LO(t_1_cry_23));
XORCY t_1_s_22(.LI(N_4563_i),.CI(t_1_cry_21),.O(t_1[22:22]));
MUXCY_L t_1_cry_22_cZ(.DI(VCC),.CI(t_1_cry_21),.S(N_4563_i),.LO(t_1_cry_22));
XORCY t_1_s_21(.LI(N_4562_i),.CI(t_1_cry_20),.O(t_1[21:21]));
MUXCY_L t_1_cry_21_cZ(.DI(VCC),.CI(t_1_cry_20),.S(N_4562_i),.LO(t_1_cry_21));
XORCY t_1_s_20(.LI(N_4561_i),.CI(t_1_cry_19),.O(t_1[20:20]));
MUXCY_L t_1_cry_20_cZ(.DI(VCC),.CI(t_1_cry_19),.S(N_4561_i),.LO(t_1_cry_20));
XORCY t_1_s_19(.LI(N_4560_i),.CI(t_1_cry_18),.O(t_1[19:19]));
MUXCY_L t_1_cry_19_cZ(.DI(VCC),.CI(t_1_cry_18),.S(N_4560_i),.LO(t_1_cry_19));
XORCY t_1_s_18(.LI(N_4559_i),.CI(t_1_cry_17),.O(t_1[18:18]));
MUXCY_L t_1_cry_18_cZ(.DI(VCC),.CI(t_1_cry_17),.S(N_4559_i),.LO(t_1_cry_18));
XORCY t_1_s_17(.LI(N_4558_i),.CI(t_1_cry_16),.O(t_1[17:17]));
MUXCY_L t_1_cry_17_cZ(.DI(VCC),.CI(t_1_cry_16),.S(N_4558_i),.LO(t_1_cry_17));
XORCY t_1_s_16(.LI(N_4557_i),.CI(t_1_cry_15),.O(t_1[16:16]));
MUXCY_L t_1_cry_16_cZ(.DI(VCC),.CI(t_1_cry_15),.S(N_4557_i),.LO(t_1_cry_16));
XORCY t_1_s_15(.LI(N_4556_i),.CI(t_1_cry_14),.O(t_1[15:15]));
MUXCY_L t_1_cry_15_cZ(.DI(VCC),.CI(t_1_cry_14),.S(N_4556_i),.LO(t_1_cry_15));
XORCY t_1_s_14(.LI(N_4555_i),.CI(t_1_cry_13),.O(t_1[14:14]));
MUXCY_L t_1_cry_14_cZ(.DI(VCC),.CI(t_1_cry_13),.S(N_4555_i),.LO(t_1_cry_14));
XORCY t_1_s_13(.LI(N_4554_i),.CI(t_1_cry_12),.O(t_1[13:13]));
MUXCY_L t_1_cry_13_cZ(.DI(VCC),.CI(t_1_cry_12),.S(N_4554_i),.LO(t_1_cry_13));
XORCY t_1_s_12(.LI(N_4553_i),.CI(t_1_cry_11),.O(t_1[12:12]));
MUXCY_L t_1_cry_12_cZ(.DI(VCC),.CI(t_1_cry_11),.S(N_4553_i),.LO(t_1_cry_12));
XORCY t_1_s_11(.LI(N_4552_i),.CI(t_1_cry_10),.O(t_1[11:11]));
MUXCY_L t_1_cry_11_cZ(.DI(VCC),.CI(t_1_cry_10),.S(N_4552_i),.LO(t_1_cry_11));
XORCY t_1_s_10(.LI(N_4551_i),.CI(t_1_cry_9),.O(t_1[10:10]));
MUXCY_L t_1_cry_10_cZ(.DI(VCC),.CI(t_1_cry_9),.S(N_4551_i),.LO(t_1_cry_10));
XORCY t_1_s_9(.LI(N_4550_i),.CI(t_1_cry_8),.O(t_1[9:9]));
MUXCY_L t_1_cry_9_cZ(.DI(VCC),.CI(t_1_cry_8),.S(N_4550_i),.LO(t_1_cry_9));
XORCY t_1_s_8(.LI(N_4549_i),.CI(t_1_cry_7),.O(t_1[8:8]));
MUXCY_L t_1_cry_8_cZ(.DI(VCC),.CI(t_1_cry_7),.S(N_4549_i),.LO(t_1_cry_8));
XORCY t_1_s_7(.LI(N_4548_i),.CI(t_1_cry_6),.O(t_1[7:7]));
MUXCY_L t_1_cry_7_cZ(.DI(VCC),.CI(t_1_cry_6),.S(N_4548_i),.LO(t_1_cry_7));
XORCY t_1_s_6(.LI(N_4547_i),.CI(t_1_cry_5),.O(t_1[6:6]));
MUXCY_L t_1_cry_6_cZ(.DI(VCC),.CI(t_1_cry_5),.S(N_4547_i),.LO(t_1_cry_6));
XORCY t_1_s_5(.LI(N_4546_i),.CI(t_1_cry_4),.O(t_1[5:5]));
MUXCY_L t_1_cry_5_cZ(.DI(VCC),.CI(t_1_cry_4),.S(N_4546_i),.LO(t_1_cry_5));
XORCY t_1_s_4(.LI(N_4545_i),.CI(t_1_cry_3),.O(t_1[4:4]));
MUXCY_L t_1_cry_4_cZ(.DI(VCC),.CI(t_1_cry_3),.S(N_4545_i),.LO(t_1_cry_4));
XORCY t_1_s_3(.LI(N_4544_i),.CI(t_1_cry_2),.O(t_1[3:3]));
MUXCY_L t_1_cry_3_cZ(.DI(VCC),.CI(t_1_cry_2),.S(N_4544_i),.LO(t_1_cry_3));
XORCY t_1_s_2(.LI(N_4543_i),.CI(t_1_cry_1),.O(t_1[2:2]));
MUXCY_L t_1_cry_2_cZ(.DI(VCC),.CI(t_1_cry_1),.S(N_4543_i),.LO(t_1_cry_2));
XORCY t_1_s_1(.LI(N_4542_i),.CI(t_1_cry_0),.O(t_1[1:1]));
MUXCY_L t_1_cry_1_cZ(.DI(VCC),.CI(t_1_cry_0),.S(N_4542_i),.LO(t_1_cry_1));
XORCY t_1_s_0(.LI(N_4541_i),.CI(t_1_cry_0_cy),.O(t_1[0:0]));
MUXCY_L t_1_cry_0_cZ(.DI(VCC),.CI(t_1_cry_0_cy),.S(N_4541_i),.LO(t_1_cry_0));
XORCY un3_reg3_s_25_cZ(.LI(un3_reg3_axb_25),.CI(un3_reg3_cry_24),.O(un3_reg3_s_25));
MUXCY un3_reg3_cry_25_cZ(.DI(GND),.CI(un3_reg3_cry_24),.S(un3_reg3_axb_25),.O(un3_reg3_cry_25_0));
XORCY un3_reg3_s_24_cZ(.LI(un3_reg3_axb_24),.CI(un3_reg3_cry_23),.O(un3_reg3_s_24));
MUXCY_L un3_reg3_cry_24_cZ(.DI(GND),.CI(un3_reg3_cry_23),.S(un3_reg3_axb_24),.LO(un3_reg3_cry_24));
XORCY un3_reg3_s_23_cZ(.LI(un3_reg3_axb_23),.CI(un3_reg3_cry_22),.O(un3_reg3_s_23));
MUXCY_L un3_reg3_cry_23_cZ(.DI(GND),.CI(un3_reg3_cry_22),.S(un3_reg3_axb_23),.LO(un3_reg3_cry_23));
XORCY un3_reg3_s_22_cZ(.LI(un3_reg3_axb_22),.CI(un3_reg3_cry_21),.O(un3_reg3_s_22));
MUXCY_L un3_reg3_cry_22_cZ(.DI(GND),.CI(un3_reg3_cry_21),.S(un3_reg3_axb_22),.LO(un3_reg3_cry_22));
XORCY un3_reg3_s_21_cZ(.LI(un3_reg3_axb_21),.CI(un3_reg3_cry_20),.O(un3_reg3_s_21));
MUXCY_L un3_reg3_cry_21_cZ(.DI(GND),.CI(un3_reg3_cry_20),.S(un3_reg3_axb_21),.LO(un3_reg3_cry_21));
XORCY un3_reg3_s_20_cZ(.LI(un3_reg3_axb_20),.CI(un3_reg3_cry_19),.O(un3_reg3_s_20));
MUXCY_L un3_reg3_cry_20_cZ(.DI(GND),.CI(un3_reg3_cry_19),.S(un3_reg3_axb_20),.LO(un3_reg3_cry_20));
XORCY un3_reg3_s_19_cZ(.LI(un3_reg3_axb_19),.CI(un3_reg3_cry_18),.O(un3_reg3_s_19));
MUXCY_L un3_reg3_cry_19_cZ(.DI(GND),.CI(un3_reg3_cry_18),.S(un3_reg3_axb_19),.LO(un3_reg3_cry_19));
XORCY un3_reg3_s_18_cZ(.LI(un3_reg3_axb_18),.CI(un3_reg3_cry_17),.O(un3_reg3_s_18));
MUXCY_L un3_reg3_cry_18_cZ(.DI(GND),.CI(un3_reg3_cry_17),.S(un3_reg3_axb_18),.LO(un3_reg3_cry_18));
XORCY un3_reg3_s_17_cZ(.LI(un3_reg3_axb_17),.CI(un3_reg3_cry_16),.O(un3_reg3_s_17));
MUXCY_L un3_reg3_cry_17_cZ(.DI(GND),.CI(un3_reg3_cry_16),.S(un3_reg3_axb_17),.LO(un3_reg3_cry_17));
XORCY un3_reg3_s_16_cZ(.LI(un3_reg3_axb_16),.CI(un3_reg3_cry_15),.O(un3_reg3_s_16));
MUXCY_L un3_reg3_cry_16_cZ(.DI(GND),.CI(un3_reg3_cry_15),.S(un3_reg3_axb_16),.LO(un3_reg3_cry_16));
XORCY un3_reg3_s_15_cZ(.LI(un3_reg3_axb_15),.CI(un3_reg3_cry_14),.O(un3_reg3_s_15));
MUXCY_L un3_reg3_cry_15_cZ(.DI(GND),.CI(un3_reg3_cry_14),.S(un3_reg3_axb_15),.LO(un3_reg3_cry_15));
XORCY un3_reg3_s_14_cZ(.LI(un3_reg3_axb_14),.CI(un3_reg3_cry_13),.O(un3_reg3_s_14));
MUXCY_L un3_reg3_cry_14_cZ(.DI(GND),.CI(un3_reg3_cry_13),.S(un3_reg3_axb_14),.LO(un3_reg3_cry_14));
XORCY un3_reg3_s_13_cZ(.LI(un3_reg3_axb_13),.CI(un3_reg3_cry_12),.O(un3_reg3_s_13));
MUXCY_L un3_reg3_cry_13_cZ(.DI(GND),.CI(un3_reg3_cry_12),.S(un3_reg3_axb_13),.LO(un3_reg3_cry_13));
XORCY un3_reg3_s_12_cZ(.LI(un3_reg3_axb_12),.CI(un3_reg3_cry_11),.O(un3_reg3_s_12));
MUXCY_L un3_reg3_cry_12_cZ(.DI(GND),.CI(un3_reg3_cry_11),.S(un3_reg3_axb_12),.LO(un3_reg3_cry_12));
XORCY un3_reg3_s_11_cZ(.LI(un3_reg3_axb_11),.CI(un3_reg3_cry_10),.O(un3_reg3_s_11));
MUXCY_L un3_reg3_cry_11_cZ(.DI(GND),.CI(un3_reg3_cry_10),.S(un3_reg3_axb_11),.LO(un3_reg3_cry_11));
XORCY un3_reg3_s_10_cZ(.LI(un3_reg3_axb_10),.CI(un3_reg3_cry_9),.O(un3_reg3_s_10));
MUXCY_L un3_reg3_cry_10_cZ(.DI(GND),.CI(un3_reg3_cry_9),.S(un3_reg3_axb_10),.LO(un3_reg3_cry_10));
XORCY un3_reg3_s_9_cZ(.LI(un3_reg3_axb_9),.CI(un3_reg3_cry_8),.O(un3_reg3_s_9));
MUXCY_L un3_reg3_cry_9_cZ(.DI(GND),.CI(un3_reg3_cry_8),.S(un3_reg3_axb_9),.LO(un3_reg3_cry_9));
XORCY un3_reg3_s_8_cZ(.LI(un3_reg3_axb_8),.CI(un3_reg3_cry_7),.O(un3_reg3_s_8));
MUXCY_L un3_reg3_cry_8_cZ(.DI(GND),.CI(un3_reg3_cry_7),.S(un3_reg3_axb_8),.LO(un3_reg3_cry_8));
XORCY un3_reg3_s_7_cZ(.LI(un3_reg3_axb_7),.CI(un3_reg3_cry_6),.O(un3_reg3_s_7));
MUXCY_L un3_reg3_cry_7_cZ(.DI(GND),.CI(un3_reg3_cry_6),.S(un3_reg3_axb_7),.LO(un3_reg3_cry_7));
XORCY un3_reg3_s_6_cZ(.LI(un3_reg3_axb_6),.CI(un3_reg3_cry_5),.O(un3_reg3_s_6));
MUXCY_L un3_reg3_cry_6_cZ(.DI(GND),.CI(un3_reg3_cry_5),.S(un3_reg3_axb_6),.LO(un3_reg3_cry_6));
XORCY un3_reg3_s_5_cZ(.LI(un3_reg3_axb_5),.CI(un3_reg3_cry_4),.O(un3_reg3_s_5));
MUXCY_L un3_reg3_cry_5_cZ(.DI(GND),.CI(un3_reg3_cry_4),.S(un3_reg3_axb_5),.LO(un3_reg3_cry_5));
XORCY un3_reg3_s_4_cZ(.LI(un3_reg3_axb_4),.CI(un3_reg3_cry_3),.O(un3_reg3_s_4));
MUXCY_L un3_reg3_cry_4_cZ(.DI(GND),.CI(un3_reg3_cry_3),.S(un3_reg3_axb_4),.LO(un3_reg3_cry_4));
XORCY un3_reg3_s_3_cZ(.LI(un3_reg3_axb_3),.CI(un3_reg3_cry_2),.O(un3_reg3_s_3));
MUXCY_L un3_reg3_cry_3_cZ(.DI(GND),.CI(un3_reg3_cry_2),.S(un3_reg3_axb_3),.LO(un3_reg3_cry_3));
XORCY un3_reg3_s_2_cZ(.LI(un3_reg3_axb_2),.CI(un3_reg3_cry_1),.O(un3_reg3_s_2));
MUXCY_L un3_reg3_cry_2_cZ(.DI(GND),.CI(un3_reg3_cry_1),.S(un3_reg3_axb_2),.LO(un3_reg3_cry_2));
XORCY un3_reg3_s_1_cZ(.LI(un3_reg3_axb_1),.CI(reg3[3:3]),.O(un3_reg3_s_1));
MUXCY_L un3_reg3_cry_1_cZ(.DI(GND),.CI(reg3[3:3]),.S(un3_reg3_axb_1),.LO(un3_reg3_cry_1));
XORCY un1_inf_abs0_0_s_19(.LI(un1_inf_abs0_0_axb_19),.CI(un1_inf_abs0_0_cry_18),.O(un1_inf_abs0_11[19:19]));
XORCY un1_inf_abs0_0_s_18(.LI(un1_inf_abs0_0_axb_18),.CI(un1_inf_abs0_0_cry_17),.O(un1_inf_abs0_11[18:18]));
MUXCY_L un1_inf_abs0_0_cry_18_cZ(.DI(inf_abs0_2[18:18]),.CI(un1_inf_abs0_0_cry_17),.S(un1_inf_abs0_0_axb_18),.LO(un1_inf_abs0_0_cry_18));
XORCY un1_inf_abs0_0_s_17(.LI(un1_inf_abs0_0_axb_17),.CI(un1_inf_abs0_0_cry_16),.O(un1_inf_abs0_11[17:17]));
MUXCY_L un1_inf_abs0_0_cry_17_cZ(.DI(inf_abs0_2[17:17]),.CI(un1_inf_abs0_0_cry_16),.S(un1_inf_abs0_0_axb_17),.LO(un1_inf_abs0_0_cry_17));
XORCY un1_inf_abs0_0_s_16(.LI(un1_inf_abs0_0_axb_16),.CI(un1_inf_abs0_0_cry_15),.O(un1_inf_abs0_11[16:16]));
MUXCY_L un1_inf_abs0_0_cry_16_cZ(.DI(inf_abs0_2[16:16]),.CI(un1_inf_abs0_0_cry_15),.S(un1_inf_abs0_0_axb_16),.LO(un1_inf_abs0_0_cry_16));
XORCY un1_inf_abs0_0_s_15(.LI(un1_inf_abs0_0_axb_15),.CI(un1_inf_abs0_0_cry_14),.O(un1_inf_abs0_11[15:15]));
MUXCY_L un1_inf_abs0_0_cry_15_cZ(.DI(inf_abs0_2[15:15]),.CI(un1_inf_abs0_0_cry_14),.S(un1_inf_abs0_0_axb_15),.LO(un1_inf_abs0_0_cry_15));
XORCY un1_inf_abs0_0_s_14(.LI(un1_inf_abs0_0_axb_14),.CI(un1_inf_abs0_0_cry_13),.O(un1_inf_abs0_11[14:14]));
MUXCY_L un1_inf_abs0_0_cry_14_cZ(.DI(inf_abs0_2[14:14]),.CI(un1_inf_abs0_0_cry_13),.S(un1_inf_abs0_0_axb_14),.LO(un1_inf_abs0_0_cry_14));
XORCY un1_inf_abs0_0_s_13(.LI(un1_inf_abs0_0_axb_13),.CI(un1_inf_abs0_0_cry_12),.O(un1_inf_abs0_11[13:13]));
MUXCY_L un1_inf_abs0_0_cry_13_cZ(.DI(inf_abs0_2[13:13]),.CI(un1_inf_abs0_0_cry_12),.S(un1_inf_abs0_0_axb_13),.LO(un1_inf_abs0_0_cry_13));
XORCY un1_inf_abs0_0_s_12(.LI(un1_inf_abs0_0_axb_12),.CI(un1_inf_abs0_0_cry_11),.O(un1_inf_abs0_11[12:12]));
MUXCY_L un1_inf_abs0_0_cry_12_cZ(.DI(inf_abs0_2[12:12]),.CI(un1_inf_abs0_0_cry_11),.S(un1_inf_abs0_0_axb_12),.LO(un1_inf_abs0_0_cry_12));
XORCY un1_inf_abs0_0_s_11(.LI(un1_inf_abs0_0_axb_11),.CI(un1_inf_abs0_0_cry_10),.O(un1_inf_abs0_11[11:11]));
MUXCY_L un1_inf_abs0_0_cry_11_cZ(.DI(inf_abs0_2[11:11]),.CI(un1_inf_abs0_0_cry_10),.S(un1_inf_abs0_0_axb_11),.LO(un1_inf_abs0_0_cry_11));
XORCY un1_inf_abs0_0_s_10(.LI(un1_inf_abs0_0_axb_10),.CI(un1_inf_abs0_0_cry_9),.O(un1_inf_abs0_11[10:10]));
MUXCY_L un1_inf_abs0_0_cry_10_cZ(.DI(inf_abs0_2[10:10]),.CI(un1_inf_abs0_0_cry_9),.S(un1_inf_abs0_0_axb_10),.LO(un1_inf_abs0_0_cry_10));
XORCY un1_inf_abs0_0_s_9(.LI(un1_inf_abs0_0_axb_9),.CI(un1_inf_abs0_0_cry_8),.O(un1_inf_abs0_11[9:9]));
MUXCY_L un1_inf_abs0_0_cry_9_cZ(.DI(inf_abs0_2[9:9]),.CI(un1_inf_abs0_0_cry_8),.S(un1_inf_abs0_0_axb_9),.LO(un1_inf_abs0_0_cry_9));
XORCY un1_inf_abs0_0_s_8(.LI(un1_inf_abs0_0_axb_8),.CI(un1_inf_abs0_0_cry_7),.O(un1_inf_abs0_11[8:8]));
MUXCY_L un1_inf_abs0_0_cry_8_cZ(.DI(inf_abs0_2[8:8]),.CI(un1_inf_abs0_0_cry_7),.S(un1_inf_abs0_0_axb_8),.LO(un1_inf_abs0_0_cry_8));
XORCY un1_inf_abs0_0_s_7(.LI(un1_inf_abs0_0_axb_7),.CI(un1_inf_abs0_0_cry_6),.O(un1_inf_abs0_11[7:7]));
MUXCY_L un1_inf_abs0_0_cry_7_cZ(.DI(inf_abs0_2[7:7]),.CI(un1_inf_abs0_0_cry_6),.S(un1_inf_abs0_0_axb_7),.LO(un1_inf_abs0_0_cry_7));
XORCY un1_inf_abs0_0_s_6(.LI(un1_inf_abs0_0_axb_6),.CI(un1_inf_abs0_0_cry_5),.O(un1_inf_abs0_11[6:6]));
MUXCY_L un1_inf_abs0_0_cry_6_cZ(.DI(inf_abs0_2[6:6]),.CI(un1_inf_abs0_0_cry_5),.S(un1_inf_abs0_0_axb_6),.LO(un1_inf_abs0_0_cry_6));
XORCY un1_inf_abs0_0_s_5(.LI(un1_inf_abs0_0_axb_5),.CI(un1_inf_abs0_0_cry_4),.O(un1_inf_abs0_11[5:5]));
MUXCY_L un1_inf_abs0_0_cry_5_cZ(.DI(inf_abs0_2[5:5]),.CI(un1_inf_abs0_0_cry_4),.S(un1_inf_abs0_0_axb_5),.LO(un1_inf_abs0_0_cry_5));
XORCY un1_inf_abs0_0_s_4(.LI(un1_inf_abs0_0_axb_4),.CI(un1_inf_abs0_0_cry_3),.O(un1_inf_abs0_11[4:4]));
MUXCY_L un1_inf_abs0_0_cry_4_cZ(.DI(inf_abs0_2[4:4]),.CI(un1_inf_abs0_0_cry_3),.S(un1_inf_abs0_0_axb_4),.LO(un1_inf_abs0_0_cry_4));
XORCY un1_inf_abs0_0_s_3(.LI(un1_inf_abs0_0_axb_3),.CI(un1_inf_abs0_0_cry_2),.O(un1_inf_abs0_11[3:3]));
MUXCY_L un1_inf_abs0_0_cry_3_cZ(.DI(inf_abs0_2[3:3]),.CI(un1_inf_abs0_0_cry_2),.S(un1_inf_abs0_0_axb_3),.LO(un1_inf_abs0_0_cry_3));
XORCY un1_inf_abs0_0_s_2(.LI(un1_inf_abs0_0_axb_2),.CI(un1_inf_abs0_0_cry_1),.O(un1_inf_abs0_11[2:2]));
MUXCY_L un1_inf_abs0_0_cry_2_cZ(.DI(inf_abs0_2[2:2]),.CI(un1_inf_abs0_0_cry_1),.S(un1_inf_abs0_0_axb_2),.LO(un1_inf_abs0_0_cry_2));
XORCY un1_inf_abs0_0_s_1(.LI(un1_inf_abs0_0_axb_1),.CI(un1_inf_abs0_0_cry_0),.O(un1_inf_abs0_11[1:1]));
MUXCY_L un1_inf_abs0_0_cry_1_cZ(.DI(inf_abs0_2[1:1]),.CI(un1_inf_abs0_0_cry_0),.S(un1_inf_abs0_0_axb_1),.LO(un1_inf_abs0_0_cry_1));
MUXCY_L un1_inf_abs0_0_cry_0_cZ(.DI(inf_abs0_2[0:0]),.CI(GND),.S(un1_inf_abs0_11[0:0]),.LO(un1_inf_abs0_0_cry_0));
XORCY un1_inf_abs0_s_19(.LI(un1_inf_abs0_axb_19),.CI(un1_inf_abs0_cry_18),.O(un1_inf_abs0_10[19:19]));
XORCY un1_inf_abs0_s_18(.LI(un1_inf_abs0_axb_18),.CI(un1_inf_abs0_cry_17),.O(un1_inf_abs0_10[18:18]));
MUXCY_L un1_inf_abs0_cry_18_cZ(.DI(inf_abs0_2[18:18]),.CI(un1_inf_abs0_cry_17),.S(un1_inf_abs0_axb_18),.LO(un1_inf_abs0_cry_18));
XORCY un1_inf_abs0_s_17(.LI(un1_inf_abs0_axb_17),.CI(un1_inf_abs0_cry_16),.O(un1_inf_abs0_10[17:17]));
MUXCY_L un1_inf_abs0_cry_17_cZ(.DI(inf_abs0_2[17:17]),.CI(un1_inf_abs0_cry_16),.S(un1_inf_abs0_axb_17),.LO(un1_inf_abs0_cry_17));
XORCY un1_inf_abs0_s_16(.LI(un1_inf_abs0_axb_16),.CI(un1_inf_abs0_cry_15),.O(un1_inf_abs0_10[16:16]));
MUXCY_L un1_inf_abs0_cry_16_cZ(.DI(inf_abs0_2[16:16]),.CI(un1_inf_abs0_cry_15),.S(un1_inf_abs0_axb_16),.LO(un1_inf_abs0_cry_16));
XORCY un1_inf_abs0_s_15(.LI(un1_inf_abs0_axb_15),.CI(un1_inf_abs0_cry_14),.O(un1_inf_abs0_10[15:15]));
MUXCY_L un1_inf_abs0_cry_15_cZ(.DI(inf_abs0_2[15:15]),.CI(un1_inf_abs0_cry_14),.S(un1_inf_abs0_axb_15),.LO(un1_inf_abs0_cry_15));
XORCY un1_inf_abs0_s_14(.LI(un1_inf_abs0_axb_14),.CI(un1_inf_abs0_cry_13),.O(un1_inf_abs0_10[14:14]));
MUXCY_L un1_inf_abs0_cry_14_cZ(.DI(inf_abs0_2[14:14]),.CI(un1_inf_abs0_cry_13),.S(un1_inf_abs0_axb_14),.LO(un1_inf_abs0_cry_14));
XORCY un1_inf_abs0_s_13(.LI(un1_inf_abs0_axb_13),.CI(un1_inf_abs0_cry_12),.O(un1_inf_abs0_10[13:13]));
MUXCY_L un1_inf_abs0_cry_13_cZ(.DI(inf_abs0_2[13:13]),.CI(un1_inf_abs0_cry_12),.S(un1_inf_abs0_axb_13),.LO(un1_inf_abs0_cry_13));
XORCY un1_inf_abs0_s_12(.LI(un1_inf_abs0_axb_12),.CI(un1_inf_abs0_cry_11),.O(un1_inf_abs0_10[12:12]));
MUXCY_L un1_inf_abs0_cry_12_cZ(.DI(inf_abs0_2[12:12]),.CI(un1_inf_abs0_cry_11),.S(un1_inf_abs0_axb_12),.LO(un1_inf_abs0_cry_12));
XORCY un1_inf_abs0_s_11(.LI(un1_inf_abs0_axb_11),.CI(un1_inf_abs0_cry_10),.O(un1_inf_abs0_10[11:11]));
MUXCY_L un1_inf_abs0_cry_11_cZ(.DI(inf_abs0_2[11:11]),.CI(un1_inf_abs0_cry_10),.S(un1_inf_abs0_axb_11),.LO(un1_inf_abs0_cry_11));
XORCY un1_inf_abs0_s_10(.LI(un1_inf_abs0_axb_10),.CI(un1_inf_abs0_cry_9),.O(un1_inf_abs0_10[10:10]));
MUXCY_L un1_inf_abs0_cry_10_cZ(.DI(inf_abs0_2[10:10]),.CI(un1_inf_abs0_cry_9),.S(un1_inf_abs0_axb_10),.LO(un1_inf_abs0_cry_10));
XORCY un1_inf_abs0_s_9(.LI(un1_inf_abs0_axb_9),.CI(un1_inf_abs0_cry_8),.O(un1_inf_abs0_10[9:9]));
MUXCY_L un1_inf_abs0_cry_9_cZ(.DI(inf_abs0_2[9:9]),.CI(un1_inf_abs0_cry_8),.S(un1_inf_abs0_axb_9),.LO(un1_inf_abs0_cry_9));
XORCY un1_inf_abs0_s_8(.LI(un1_inf_abs0_axb_8),.CI(un1_inf_abs0_cry_7),.O(un1_inf_abs0_10[8:8]));
MUXCY_L un1_inf_abs0_cry_8_cZ(.DI(inf_abs0_2[8:8]),.CI(un1_inf_abs0_cry_7),.S(un1_inf_abs0_axb_8),.LO(un1_inf_abs0_cry_8));
XORCY un1_inf_abs0_s_7(.LI(un1_inf_abs0_axb_7),.CI(un1_inf_abs0_cry_6),.O(un1_inf_abs0_10[7:7]));
MUXCY_L un1_inf_abs0_cry_7_cZ(.DI(inf_abs0_2[7:7]),.CI(un1_inf_abs0_cry_6),.S(un1_inf_abs0_axb_7),.LO(un1_inf_abs0_cry_7));
XORCY un1_inf_abs0_s_6(.LI(un1_inf_abs0_axb_6),.CI(un1_inf_abs0_cry_5),.O(un1_inf_abs0_10[6:6]));
MUXCY_L un1_inf_abs0_cry_6_cZ(.DI(inf_abs0_2[6:6]),.CI(un1_inf_abs0_cry_5),.S(un1_inf_abs0_axb_6),.LO(un1_inf_abs0_cry_6));
XORCY un1_inf_abs0_s_5(.LI(un1_inf_abs0_axb_5),.CI(un1_inf_abs0_cry_4),.O(un1_inf_abs0_10[5:5]));
MUXCY_L un1_inf_abs0_cry_5_cZ(.DI(inf_abs0_2[5:5]),.CI(un1_inf_abs0_cry_4),.S(un1_inf_abs0_axb_5),.LO(un1_inf_abs0_cry_5));
XORCY un1_inf_abs0_s_4(.LI(un1_inf_abs0_axb_4),.CI(un1_inf_abs0_cry_3),.O(un1_inf_abs0_10[4:4]));
MUXCY_L un1_inf_abs0_cry_4_cZ(.DI(inf_abs0_2[4:4]),.CI(un1_inf_abs0_cry_3),.S(un1_inf_abs0_axb_4),.LO(un1_inf_abs0_cry_4));
XORCY un1_inf_abs0_s_3(.LI(un1_inf_abs0_axb_3),.CI(un1_inf_abs0_cry_2),.O(un1_inf_abs0_10[3:3]));
MUXCY_L un1_inf_abs0_cry_3_cZ(.DI(inf_abs0_2[3:3]),.CI(un1_inf_abs0_cry_2),.S(un1_inf_abs0_axb_3),.LO(un1_inf_abs0_cry_3));
XORCY un1_inf_abs0_s_2(.LI(un1_inf_abs0_axb_2),.CI(un1_inf_abs0_cry_1),.O(un1_inf_abs0_10[2:2]));
MUXCY_L un1_inf_abs0_cry_2_cZ(.DI(inf_abs0_2[2:2]),.CI(un1_inf_abs0_cry_1),.S(un1_inf_abs0_axb_2),.LO(un1_inf_abs0_cry_2));
XORCY un1_inf_abs0_s_1(.LI(un1_inf_abs0_axb_1),.CI(un1_inf_abs0_cry_0),.O(un1_inf_abs0_10[1:1]));
MUXCY_L un1_inf_abs0_cry_1_cZ(.DI(inf_abs0_2[1:1]),.CI(un1_inf_abs0_cry_0),.S(un1_inf_abs0_axb_1),.LO(un1_inf_abs0_cry_1));
MUXCY_L un1_inf_abs0_cry_0_cZ(.DI(inf_abs0_2[0:0]),.CI(GND),.S(un1_inf_abs0_10[0:0]),.LO(un1_inf_abs0_cry_0));
XORCY un32_reg0_s_29_cZ(.LI(un32_reg0_axb_29),.CI(un32_reg0_cry_28),.O(un32_reg0_s_29));
XORCY un32_reg0_s_28_cZ(.LI(un32_reg0_axb_28),.CI(un32_reg0_cry_27),.O(un32_reg0_s_28));
MUXCY_L un32_reg0_cry_28_cZ(.DI(r_4[28:28]),.CI(un32_reg0_cry_27),.S(un32_reg0_axb_28),.LO(un32_reg0_cry_28));
XORCY un32_reg0_s_27_cZ(.LI(un32_reg0_axb_27),.CI(un32_reg0_cry_26),.O(un32_reg0_s_27));
MUXCY_L un32_reg0_cry_27_cZ(.DI(r_4[27:27]),.CI(un32_reg0_cry_26),.S(un32_reg0_axb_27),.LO(un32_reg0_cry_27));
XORCY un32_reg0_s_26_cZ(.LI(un32_reg0_axb_26),.CI(un32_reg0_cry_25),.O(un32_reg0_s_26));
MUXCY_L un32_reg0_cry_26_cZ(.DI(r_4[26:26]),.CI(un32_reg0_cry_25),.S(un32_reg0_axb_26),.LO(un32_reg0_cry_26));
XORCY un32_reg0_s_25_cZ(.LI(un32_reg0_axb_25),.CI(un32_reg0_cry_24),.O(un32_reg0_s_25));
MUXCY_L un32_reg0_cry_25_cZ(.DI(r_4[25:25]),.CI(un32_reg0_cry_24),.S(un32_reg0_axb_25),.LO(un32_reg0_cry_25));
XORCY un32_reg0_s_24_cZ(.LI(un32_reg0_axb_24),.CI(un32_reg0_cry_23),.O(un32_reg0_s_24));
MUXCY_L un32_reg0_cry_24_cZ(.DI(r_4[24:24]),.CI(un32_reg0_cry_23),.S(un32_reg0_axb_24),.LO(un32_reg0_cry_24));
XORCY un32_reg0_s_23_cZ(.LI(un32_reg0_axb_23),.CI(un32_reg0_cry_22),.O(un32_reg0_s_23));
MUXCY_L un32_reg0_cry_23_cZ(.DI(r_4[23:23]),.CI(un32_reg0_cry_22),.S(un32_reg0_axb_23),.LO(un32_reg0_cry_23));
XORCY un32_reg0_s_22_cZ(.LI(un32_reg0_axb_22),.CI(un32_reg0_cry_21),.O(un32_reg0_s_22));
MUXCY_L un32_reg0_cry_22_cZ(.DI(r_4[22:22]),.CI(un32_reg0_cry_21),.S(un32_reg0_axb_22),.LO(un32_reg0_cry_22));
XORCY un32_reg0_s_21_cZ(.LI(un32_reg0_axb_21),.CI(un32_reg0_cry_20),.O(un32_reg0_s_21));
MUXCY_L un32_reg0_cry_21_cZ(.DI(r_4[21:21]),.CI(un32_reg0_cry_20),.S(un32_reg0_axb_21),.LO(un32_reg0_cry_21));
XORCY un32_reg0_s_20_cZ(.LI(un32_reg0_axb_20),.CI(un32_reg0_cry_19),.O(un32_reg0_s_20));
MUXCY_L un32_reg0_cry_20_cZ(.DI(r_4[20:20]),.CI(un32_reg0_cry_19),.S(un32_reg0_axb_20),.LO(un32_reg0_cry_20));
XORCY un32_reg0_s_19_cZ(.LI(un32_reg0_axb_19),.CI(un32_reg0_cry_18),.O(un32_reg0_s_19));
MUXCY_L un32_reg0_cry_19_cZ(.DI(r_4[19:19]),.CI(un32_reg0_cry_18),.S(un32_reg0_axb_19),.LO(un32_reg0_cry_19));
XORCY un32_reg0_s_18_cZ(.LI(un32_reg0_axb_18),.CI(un32_reg0_cry_17),.O(un32_reg0_s_18));
MUXCY_L un32_reg0_cry_18_cZ(.DI(r_4[18:18]),.CI(un32_reg0_cry_17),.S(un32_reg0_axb_18),.LO(un32_reg0_cry_18));
XORCY un32_reg0_s_17_cZ(.LI(un32_reg0_axb_17),.CI(un32_reg0_cry_16),.O(un32_reg0_s_17));
MUXCY_L un32_reg0_cry_17_cZ(.DI(r_4[17:17]),.CI(un32_reg0_cry_16),.S(un32_reg0_axb_17),.LO(un32_reg0_cry_17));
XORCY un32_reg0_s_16_cZ(.LI(un32_reg0_axb_16),.CI(un32_reg0_cry_15),.O(un32_reg0_s_16));
MUXCY_L un32_reg0_cry_16_cZ(.DI(r_4[16:16]),.CI(un32_reg0_cry_15),.S(un32_reg0_axb_16),.LO(un32_reg0_cry_16));
XORCY un32_reg0_s_15_cZ(.LI(un32_reg0_axb_15),.CI(un32_reg0_cry_14),.O(un32_reg0_s_15));
MUXCY_L un32_reg0_cry_15_cZ(.DI(r_4[15:15]),.CI(un32_reg0_cry_14),.S(un32_reg0_axb_15),.LO(un32_reg0_cry_15));
XORCY un32_reg0_s_14_cZ(.LI(un32_reg0_axb_14),.CI(un32_reg0_cry_13),.O(un32_reg0_s_14));
MUXCY_L un32_reg0_cry_14_cZ(.DI(r_4[14:14]),.CI(un32_reg0_cry_13),.S(un32_reg0_axb_14),.LO(un32_reg0_cry_14));
XORCY un32_reg0_s_13_cZ(.LI(un32_reg0_axb_13),.CI(un32_reg0_cry_12),.O(un32_reg0_s_13));
MUXCY_L un32_reg0_cry_13_cZ(.DI(r_4[13:13]),.CI(un32_reg0_cry_12),.S(un32_reg0_axb_13),.LO(un32_reg0_cry_13));
XORCY un32_reg0_s_12_cZ(.LI(un32_reg0_axb_12),.CI(un32_reg0_cry_11),.O(un32_reg0_s_12));
MUXCY_L un32_reg0_cry_12_cZ(.DI(r_4[12:12]),.CI(un32_reg0_cry_11),.S(un32_reg0_axb_12),.LO(un32_reg0_cry_12));
XORCY un32_reg0_s_11_cZ(.LI(un32_reg0_axb_11),.CI(un32_reg0_cry_10),.O(un32_reg0_s_11));
MUXCY_L un32_reg0_cry_11_cZ(.DI(r_4[11:11]),.CI(un32_reg0_cry_10),.S(un32_reg0_axb_11),.LO(un32_reg0_cry_11));
XORCY un32_reg0_s_10_cZ(.LI(un32_reg0_axb_10),.CI(un32_reg0_cry_9),.O(un32_reg0_s_10));
MUXCY_L un32_reg0_cry_10_cZ(.DI(r_4[10:10]),.CI(un32_reg0_cry_9),.S(un32_reg0_axb_10),.LO(un32_reg0_cry_10));
XORCY un32_reg0_s_9_cZ(.LI(un32_reg0_axb_9),.CI(un32_reg0_cry_8),.O(un32_reg0_s_9));
MUXCY_L un32_reg0_cry_9_cZ(.DI(r_4[9:9]),.CI(un32_reg0_cry_8),.S(un32_reg0_axb_9),.LO(un32_reg0_cry_9));
XORCY un32_reg0_s_8_cZ(.LI(un32_reg0_axb_8),.CI(un32_reg0_cry_7),.O(un32_reg0_s_8));
MUXCY_L un32_reg0_cry_8_cZ(.DI(r_4[8:8]),.CI(un32_reg0_cry_7),.S(un32_reg0_axb_8),.LO(un32_reg0_cry_8));
XORCY un32_reg0_s_7_cZ(.LI(un32_reg0_axb_7),.CI(un32_reg0_cry_6),.O(un32_reg0_s_7));
MUXCY_L un32_reg0_cry_7_cZ(.DI(r_4[7:7]),.CI(un32_reg0_cry_6),.S(un32_reg0_axb_7),.LO(un32_reg0_cry_7));
XORCY un32_reg0_s_6_cZ(.LI(un32_reg0_axb_6),.CI(un32_reg0_cry_5),.O(un32_reg0_s_6));
MUXCY_L un32_reg0_cry_6_cZ(.DI(r_4[6:6]),.CI(un32_reg0_cry_5),.S(un32_reg0_axb_6),.LO(un32_reg0_cry_6));
XORCY un32_reg0_s_5_cZ(.LI(un32_reg0_axb_5),.CI(un32_reg0_cry_4),.O(un32_reg0_s_5));
MUXCY_L un32_reg0_cry_5_cZ(.DI(r_4[5:5]),.CI(un32_reg0_cry_4),.S(un32_reg0_axb_5),.LO(un32_reg0_cry_5));
XORCY un32_reg0_s_4_cZ(.LI(un32_reg0_axb_4),.CI(un32_reg0_cry_3),.O(un32_reg0_s_4));
MUXCY_L un32_reg0_cry_4_cZ(.DI(r_4[4:4]),.CI(un32_reg0_cry_3),.S(un32_reg0_axb_4),.LO(un32_reg0_cry_4));
XORCY un32_reg0_s_3_cZ(.LI(un32_reg0_axb_3),.CI(un32_reg0_cry_2),.O(un32_reg0_s_3));
MUXCY_L un32_reg0_cry_3_cZ(.DI(r_4[3:3]),.CI(un32_reg0_cry_2),.S(un32_reg0_axb_3),.LO(un32_reg0_cry_3));
XORCY un32_reg0_s_2_cZ(.LI(un32_reg0_axb_2),.CI(un32_reg0_cry_1),.O(un32_reg0_s_2));
MUXCY_L un32_reg0_cry_2_cZ(.DI(N_28),.CI(un32_reg0_cry_1),.S(un32_reg0_axb_2),.LO(un32_reg0_cry_2));
XORCY un32_reg0_s_1_cZ(.LI(un32_reg0_axb_1),.CI(un32_reg0_cry_0),.O(un32_reg0_s_1));
MUXCY_L un32_reg0_cry_1_cZ(.DI(r_4[1:1]),.CI(un32_reg0_cry_0),.S(un32_reg0_axb_1),.LO(un32_reg0_cry_1));
MUXCY_L un32_reg0_cry_0_cZ(.DI(r_4[0:0]),.CI(VCC),.S(N_1035),.LO(un32_reg0_cry_0));
XORCY un11_reg0_s_29_cZ(.LI(un11_reg0_axb_29),.CI(un11_reg0_cry_28),.O(un11_reg0_s_29));
XORCY un11_reg0_s_28_cZ(.LI(un11_reg0_axb_28),.CI(un11_reg0_cry_27),.O(un11_reg0_s_28));
MUXCY_L un11_reg0_cry_28_cZ(.DI(m_2[28:28]),.CI(un11_reg0_cry_27),.S(un11_reg0_axb_28),.LO(un11_reg0_cry_28));
XORCY un11_reg0_s_27_cZ(.LI(un11_reg0_axb_27),.CI(un11_reg0_cry_26),.O(un11_reg0_s_27));
MUXCY_L un11_reg0_cry_27_cZ(.DI(m_2[27:27]),.CI(un11_reg0_cry_26),.S(un11_reg0_axb_27),.LO(un11_reg0_cry_27));
XORCY un11_reg0_s_26_cZ(.LI(un11_reg0_axb_26),.CI(un11_reg0_cry_25),.O(un11_reg0_s_26));
MUXCY_L un11_reg0_cry_26_cZ(.DI(m_2[26:26]),.CI(un11_reg0_cry_25),.S(un11_reg0_axb_26),.LO(un11_reg0_cry_26));
XORCY un11_reg0_s_25_cZ(.LI(un11_reg0_axb_25),.CI(un11_reg0_cry_24),.O(un11_reg0_s_25));
MUXCY_L un11_reg0_cry_25_cZ(.DI(m_2[25:25]),.CI(un11_reg0_cry_24),.S(un11_reg0_axb_25),.LO(un11_reg0_cry_25));
XORCY un11_reg0_s_24_cZ(.LI(un11_reg0_axb_24),.CI(un11_reg0_cry_23),.O(un11_reg0_s_24));
MUXCY_L un11_reg0_cry_24_cZ(.DI(m_2[24:24]),.CI(un11_reg0_cry_23),.S(un11_reg0_axb_24),.LO(un11_reg0_cry_24));
XORCY un11_reg0_s_23_cZ(.LI(un11_reg0_axb_23),.CI(un11_reg0_cry_22),.O(un11_reg0_s_23));
MUXCY_L un11_reg0_cry_23_cZ(.DI(m_2[23:23]),.CI(un11_reg0_cry_22),.S(un11_reg0_axb_23),.LO(un11_reg0_cry_23));
XORCY un11_reg0_s_22_cZ(.LI(un11_reg0_axb_22),.CI(un11_reg0_cry_21),.O(un11_reg0_s_22));
MUXCY_L un11_reg0_cry_22_cZ(.DI(m_2[22:22]),.CI(un11_reg0_cry_21),.S(un11_reg0_axb_22),.LO(un11_reg0_cry_22));
XORCY un11_reg0_s_21_cZ(.LI(un11_reg0_axb_21),.CI(un11_reg0_cry_20),.O(un11_reg0_s_21));
MUXCY_L un11_reg0_cry_21_cZ(.DI(m_2[21:21]),.CI(un11_reg0_cry_20),.S(un11_reg0_axb_21),.LO(un11_reg0_cry_21));
XORCY un11_reg0_s_20_cZ(.LI(un11_reg0_axb_20),.CI(un11_reg0_cry_19),.O(un11_reg0_s_20));
MUXCY_L un11_reg0_cry_20_cZ(.DI(m_2[20:20]),.CI(un11_reg0_cry_19),.S(un11_reg0_axb_20),.LO(un11_reg0_cry_20));
XORCY un11_reg0_s_19_cZ(.LI(un11_reg0_axb_19),.CI(un11_reg0_cry_18),.O(un11_reg0_s_19));
MUXCY_L un11_reg0_cry_19_cZ(.DI(r_4[19:19]),.CI(un11_reg0_cry_18),.S(un11_reg0_axb_19),.LO(un11_reg0_cry_19));
XORCY un11_reg0_s_18_cZ(.LI(un11_reg0_axb_18),.CI(un11_reg0_cry_17),.O(un11_reg0_s_18));
MUXCY_L un11_reg0_cry_18_cZ(.DI(r_4[18:18]),.CI(un11_reg0_cry_17),.S(un11_reg0_axb_18),.LO(un11_reg0_cry_18));
XORCY un11_reg0_s_17_cZ(.LI(un11_reg0_axb_17),.CI(un11_reg0_cry_16),.O(un11_reg0_s_17));
MUXCY_L un11_reg0_cry_17_cZ(.DI(r_4[17:17]),.CI(un11_reg0_cry_16),.S(un11_reg0_axb_17),.LO(un11_reg0_cry_17));
XORCY un11_reg0_s_16_cZ(.LI(un11_reg0_axb_16),.CI(un11_reg0_cry_15),.O(un11_reg0_s_16));
MUXCY_L un11_reg0_cry_16_cZ(.DI(r_4[16:16]),.CI(un11_reg0_cry_15),.S(un11_reg0_axb_16),.LO(un11_reg0_cry_16));
XORCY un11_reg0_s_15_cZ(.LI(un11_reg0_axb_15),.CI(un11_reg0_cry_14),.O(un11_reg0_s_15));
MUXCY_L un11_reg0_cry_15_cZ(.DI(r_4[15:15]),.CI(un11_reg0_cry_14),.S(un11_reg0_axb_15),.LO(un11_reg0_cry_15));
XORCY un11_reg0_s_14_cZ(.LI(un11_reg0_axb_14),.CI(un11_reg0_cry_13),.O(un11_reg0_s_14));
MUXCY_L un11_reg0_cry_14_cZ(.DI(r_4[14:14]),.CI(un11_reg0_cry_13),.S(un11_reg0_axb_14),.LO(un11_reg0_cry_14));
XORCY un11_reg0_s_13_cZ(.LI(un11_reg0_axb_13),.CI(un11_reg0_cry_12),.O(un11_reg0_s_13));
MUXCY_L un11_reg0_cry_13_cZ(.DI(r_4[13:13]),.CI(un11_reg0_cry_12),.S(un11_reg0_axb_13),.LO(un11_reg0_cry_13));
XORCY un11_reg0_s_12_cZ(.LI(un11_reg0_axb_12),.CI(un11_reg0_cry_11),.O(un11_reg0_s_12));
MUXCY_L un11_reg0_cry_12_cZ(.DI(r_4[12:12]),.CI(un11_reg0_cry_11),.S(un11_reg0_axb_12),.LO(un11_reg0_cry_12));
XORCY un11_reg0_s_11_cZ(.LI(un11_reg0_axb_11),.CI(un11_reg0_cry_10),.O(un11_reg0_s_11));
MUXCY_L un11_reg0_cry_11_cZ(.DI(r_4[11:11]),.CI(un11_reg0_cry_10),.S(un11_reg0_axb_11),.LO(un11_reg0_cry_11));
XORCY un11_reg0_s_10_cZ(.LI(un11_reg0_axb_10),.CI(un11_reg0_cry_9),.O(un11_reg0_s_10));
MUXCY_L un11_reg0_cry_10_cZ(.DI(r_4[10:10]),.CI(un11_reg0_cry_9),.S(un11_reg0_axb_10),.LO(un11_reg0_cry_10));
XORCY un11_reg0_s_9_cZ(.LI(un11_reg0_axb_9),.CI(un11_reg0_cry_8),.O(un11_reg0_s_9));
MUXCY_L un11_reg0_cry_9_cZ(.DI(r_4[9:9]),.CI(un11_reg0_cry_8),.S(un11_reg0_axb_9),.LO(un11_reg0_cry_9));
XORCY un11_reg0_s_8_cZ(.LI(un11_reg0_axb_8),.CI(un11_reg0_cry_7),.O(un11_reg0_s_8));
MUXCY_L un11_reg0_cry_8_cZ(.DI(r_4[8:8]),.CI(un11_reg0_cry_7),.S(un11_reg0_axb_8),.LO(un11_reg0_cry_8));
XORCY un11_reg0_s_7_cZ(.LI(un11_reg0_axb_7),.CI(un11_reg0_cry_6),.O(un11_reg0_s_7));
MUXCY_L un11_reg0_cry_7_cZ(.DI(r_4[7:7]),.CI(un11_reg0_cry_6),.S(un11_reg0_axb_7),.LO(un11_reg0_cry_7));
XORCY un11_reg0_s_6_cZ(.LI(un11_reg0_axb_6),.CI(un11_reg0_cry_5),.O(un11_reg0_s_6));
MUXCY_L un11_reg0_cry_6_cZ(.DI(r_4[6:6]),.CI(un11_reg0_cry_5),.S(un11_reg0_axb_6),.LO(un11_reg0_cry_6));
XORCY un11_reg0_s_5_cZ(.LI(un11_reg0_axb_5),.CI(un11_reg0_cry_4),.O(un11_reg0_s_5));
MUXCY_L un11_reg0_cry_5_cZ(.DI(r_4[5:5]),.CI(un11_reg0_cry_4),.S(un11_reg0_axb_5),.LO(un11_reg0_cry_5));
XORCY un11_reg0_s_4_cZ(.LI(un11_reg0_axb_4),.CI(un11_reg0_cry_3),.O(un11_reg0_s_4));
MUXCY_L un11_reg0_cry_4_cZ(.DI(r_4[4:4]),.CI(un11_reg0_cry_3),.S(un11_reg0_axb_4),.LO(un11_reg0_cry_4));
XORCY un11_reg0_s_3_cZ(.LI(un11_reg0_axb_3),.CI(un11_reg0_cry_2),.O(un11_reg0_s_3));
MUXCY_L un11_reg0_cry_3_cZ(.DI(r_4[3:3]),.CI(un11_reg0_cry_2),.S(un11_reg0_axb_3),.LO(un11_reg0_cry_3));
XORCY un11_reg0_s_2_cZ(.LI(un11_reg0_axb_2),.CI(un11_reg0_cry_1),.O(un11_reg0_s_2));
MUXCY_L un11_reg0_cry_2_cZ(.DI(N_28),.CI(un11_reg0_cry_1),.S(un11_reg0_axb_2),.LO(un11_reg0_cry_2));
XORCY un11_reg0_s_1_cZ(.LI(un11_reg0_axb_1),.CI(un11_reg0_cry_0),.O(un11_reg0_s_1));
MUXCY_L un11_reg0_cry_1_cZ(.DI(r_4[1:1]),.CI(un11_reg0_cry_0),.S(un11_reg0_axb_1),.LO(un11_reg0_cry_1));
MUXCY_L un11_reg0_cry_0_cZ(.DI(r_4[0:0]),.CI(GND),.S(un11_reg0_axb_0),.LO(un11_reg0_cry_0));
XORCY un3_t_s_31_cZ(.LI(un3_t_axb_31),.CI(un3_t_cry_30),.O(un3_t_s_31));
XORCY un3_t_s_30_cZ(.LI(un3_t_axb_30),.CI(un3_t_cry_29),.O(un3_t_s_30));
MUXCY_L un3_t_cry_30_cZ(.DI(GND),.CI(un3_t_cry_29),.S(un3_t_axb_30),.LO(un3_t_cry_30));
XORCY un3_t_s_29_cZ(.LI(un3_t_axb_29),.CI(un3_t_cry_28),.O(un3_t_s_29));
MUXCY_L un3_t_cry_29_cZ(.DI(GND),.CI(un3_t_cry_28),.S(un3_t_axb_29),.LO(un3_t_cry_29));
XORCY un3_t_s_28_cZ(.LI(un3_t_axb_28),.CI(un3_t_cry_27),.O(un3_t_s_28));
MUXCY_L un3_t_cry_28_cZ(.DI(GND),.CI(un3_t_cry_27),.S(un3_t_axb_28),.LO(un3_t_cry_28));
XORCY un3_t_s_27_cZ(.LI(un3_t_axb_27),.CI(un3_t_cry_26),.O(un3_t_s_27));
MUXCY_L un3_t_cry_27_cZ(.DI(GND),.CI(un3_t_cry_26),.S(un3_t_axb_27),.LO(un3_t_cry_27));
XORCY un3_t_s_26_cZ(.LI(un3_t_axb_26),.CI(un3_t_cry_25),.O(un3_t_s_26));
MUXCY_L un3_t_cry_26_cZ(.DI(GND),.CI(un3_t_cry_25),.S(un3_t_axb_26),.LO(un3_t_cry_26));
XORCY un3_t_s_25_cZ(.LI(un3_t_axb_25),.CI(un3_t_cry_24),.O(un3_t_s_25));
MUXCY_L un3_t_cry_25_cZ(.DI(GND),.CI(un3_t_cry_24),.S(un3_t_axb_25),.LO(un3_t_cry_25));
XORCY un3_t_s_24_cZ(.LI(un3_t_axb_24),.CI(un3_t_cry_23),.O(un3_t_s_24));
MUXCY_L un3_t_cry_24_cZ(.DI(GND),.CI(un3_t_cry_23),.S(un3_t_axb_24),.LO(un3_t_cry_24));
XORCY un3_t_s_23_cZ(.LI(un3_t_axb_23),.CI(un3_t_cry_22),.O(un3_t_s_23));
MUXCY_L un3_t_cry_23_cZ(.DI(GND),.CI(un3_t_cry_22),.S(un3_t_axb_23),.LO(un3_t_cry_23));
XORCY un3_t_s_22_cZ(.LI(un3_t_axb_22),.CI(un3_t_cry_21),.O(un3_t_s_22));
MUXCY_L un3_t_cry_22_cZ(.DI(GND),.CI(un3_t_cry_21),.S(un3_t_axb_22),.LO(un3_t_cry_22));
XORCY un3_t_s_21_cZ(.LI(un3_t_axb_21),.CI(un3_t_cry_20),.O(un3_t_s_21));
MUXCY_L un3_t_cry_21_cZ(.DI(GND),.CI(un3_t_cry_20),.S(un3_t_axb_21),.LO(un3_t_cry_21));
XORCY un3_t_s_20_cZ(.LI(un3_t_axb_20),.CI(un3_t_cry_19),.O(un3_t_s_20));
MUXCY_L un3_t_cry_20_cZ(.DI(GND),.CI(un3_t_cry_19),.S(un3_t_axb_20),.LO(un3_t_cry_20));
XORCY un3_t_s_19_cZ(.LI(un3_t_axb_19),.CI(un3_t_cry_18),.O(un3_t_s_19));
MUXCY_L un3_t_cry_19_cZ(.DI(GND),.CI(un3_t_cry_18),.S(un3_t_axb_19),.LO(un3_t_cry_19));
XORCY un3_t_s_18_cZ(.LI(un3_t_axb_18),.CI(un3_t_cry_17),.O(un3_t_s_18));
MUXCY_L un3_t_cry_18_cZ(.DI(GND),.CI(un3_t_cry_17),.S(un3_t_axb_18),.LO(un3_t_cry_18));
XORCY un3_t_s_17_cZ(.LI(un3_t_axb_17),.CI(un3_t_cry_16),.O(un3_t_s_17));
MUXCY_L un3_t_cry_17_cZ(.DI(GND),.CI(un3_t_cry_16),.S(un3_t_axb_17),.LO(un3_t_cry_17));
XORCY un3_t_s_16_cZ(.LI(un3_t_axb_16),.CI(un3_t_cry_15),.O(un3_t_s_16));
MUXCY_L un3_t_cry_16_cZ(.DI(GND),.CI(un3_t_cry_15),.S(un3_t_axb_16),.LO(un3_t_cry_16));
XORCY un3_t_s_15_cZ(.LI(un3_t_axb_15),.CI(un3_t_cry_14),.O(un3_t_s_15));
MUXCY_L un3_t_cry_15_cZ(.DI(GND),.CI(un3_t_cry_14),.S(un3_t_axb_15),.LO(un3_t_cry_15));
XORCY un3_t_s_14_cZ(.LI(un3_t_axb_14),.CI(un3_t_cry_13),.O(un3_t_s_14));
MUXCY_L un3_t_cry_14_cZ(.DI(GND),.CI(un3_t_cry_13),.S(un3_t_axb_14),.LO(un3_t_cry_14));
XORCY un3_t_s_13_cZ(.LI(un3_t_axb_13),.CI(un3_t_cry_12),.O(un3_t_s_13));
MUXCY_L un3_t_cry_13_cZ(.DI(GND),.CI(un3_t_cry_12),.S(un3_t_axb_13),.LO(un3_t_cry_13));
XORCY un3_t_s_12_cZ(.LI(un3_t_axb_12),.CI(un3_t_cry_11),.O(un3_t_s_12));
MUXCY_L un3_t_cry_12_cZ(.DI(GND),.CI(un3_t_cry_11),.S(un3_t_axb_12),.LO(un3_t_cry_12));
XORCY un3_t_s_11_cZ(.LI(un3_t_axb_11),.CI(un3_t_cry_10),.O(un3_t_s_11));
MUXCY_L un3_t_cry_11_cZ(.DI(GND),.CI(un3_t_cry_10),.S(un3_t_axb_11),.LO(un3_t_cry_11));
XORCY un3_t_s_10_cZ(.LI(un3_t_axb_10),.CI(un3_t_cry_9),.O(un3_t_s_10));
MUXCY_L un3_t_cry_10_cZ(.DI(GND),.CI(un3_t_cry_9),.S(un3_t_axb_10),.LO(un3_t_cry_10));
XORCY un3_t_s_9_cZ(.LI(un3_t_axb_9),.CI(un3_t_cry_8),.O(un3_t_s_9));
MUXCY_L un3_t_cry_9_cZ(.DI(GND),.CI(un3_t_cry_8),.S(un3_t_axb_9),.LO(un3_t_cry_9));
XORCY un3_t_s_8_cZ(.LI(un3_t_axb_8),.CI(un3_t_cry_7),.O(un3_t_s_8));
MUXCY_L un3_t_cry_8_cZ(.DI(GND),.CI(un3_t_cry_7),.S(un3_t_axb_8),.LO(un3_t_cry_8));
XORCY un3_t_s_7_cZ(.LI(un3_t_axb_7),.CI(un3_t_cry_6),.O(un3_t_s_7));
MUXCY_L un3_t_cry_7_cZ(.DI(GND),.CI(un3_t_cry_6),.S(un3_t_axb_7),.LO(un3_t_cry_7));
XORCY un3_t_s_6_cZ(.LI(un3_t_axb_6),.CI(un3_t_cry_5),.O(un3_t_s_6));
MUXCY_L un3_t_cry_6_cZ(.DI(GND),.CI(un3_t_cry_5),.S(un3_t_axb_6),.LO(un3_t_cry_6));
XORCY un3_t_s_5_cZ(.LI(un3_t_axb_5),.CI(un3_t_cry_4),.O(un3_t_s_5));
MUXCY_L un3_t_cry_5_cZ(.DI(GND),.CI(un3_t_cry_4),.S(un3_t_axb_5),.LO(un3_t_cry_5));
XORCY un3_t_s_4_cZ(.LI(un3_t_axb_4),.CI(un3_t_cry_3),.O(un3_t_s_4));
MUXCY_L un3_t_cry_4_cZ(.DI(GND),.CI(un3_t_cry_3),.S(un3_t_axb_4),.LO(un3_t_cry_4));
XORCY un3_t_s_3_cZ(.LI(un3_t_axb_3),.CI(un3_t_cry_2),.O(un3_t_s_3));
MUXCY_L un3_t_cry_3_cZ(.DI(GND),.CI(un3_t_cry_2),.S(un3_t_axb_3),.LO(un3_t_cry_3));
XORCY un3_t_s_2_cZ(.LI(un3_t_axb_2),.CI(un3_t_cry_1),.O(un3_t_s_2));
MUXCY_L un3_t_cry_2_cZ(.DI(GND),.CI(un3_t_cry_1),.S(un3_t_axb_2),.LO(un3_t_cry_2));
XORCY un3_t_s_1_cZ(.LI(un3_t_axb_1),.CI(un3_t_cry_0),.O(un3_t_s_1));
MUXCY_L un3_t_cry_1_cZ(.DI(GND),.CI(un3_t_cry_0),.S(un3_t_axb_1),.LO(un3_t_cry_1));
MUXCY_L un3_t_cry_0_cZ(.DI(GND),.CI(un3_t_cry_0_cy),.S(un3_t_axb_0),.LO(un3_t_cry_0));
XORCY reg3_1_1_s_31(.LI(reg3_1_1_axb_31),.CI(reg3_1_1_cry_30),.O(reg3_1_1[31:31]));
XORCY reg3_1_1_s_30(.LI(reg3_1_1_axb_30),.CI(reg3_1_1_cry_29),.O(reg3_1_1[30:30]));
MUXCY_L reg3_1_1_cry_30_cZ(.DI(GND),.CI(reg3_1_1_cry_29),.S(reg3_1_1_axb_30),.LO(reg3_1_1_cry_30));
XORCY reg3_1_1_s_29(.LI(reg3_1_1_axb_29),.CI(reg3_1_1_cry_28),.O(reg3_1_1[29:29]));
MUXCY_L reg3_1_1_cry_29_cZ(.DI(GND),.CI(reg3_1_1_cry_28),.S(reg3_1_1_axb_29),.LO(reg3_1_1_cry_29));
XORCY reg3_1_1_s_28(.LI(reg3_1_1_axb_28),.CI(reg3_1_1_cry_27),.O(reg3_1_1[28:28]));
MUXCY_L reg3_1_1_cry_28_cZ(.DI(GND),.CI(reg3_1_1_cry_27),.S(reg3_1_1_axb_28),.LO(reg3_1_1_cry_28));
XORCY reg3_1_1_s_27(.LI(reg3_1_1_axb_27),.CI(reg3_1_1_cry_26),.O(reg3_1_1[27:27]));
MUXCY_L reg3_1_1_cry_27_cZ(.DI(GND),.CI(reg3_1_1_cry_26),.S(reg3_1_1_axb_27),.LO(reg3_1_1_cry_27));
XORCY reg3_1_1_s_26(.LI(reg3_1_1_axb_26),.CI(reg3_1_1_cry_25),.O(reg3_1_1[26:26]));
MUXCY_L reg3_1_1_cry_26_cZ(.DI(GND),.CI(reg3_1_1_cry_25),.S(reg3_1_1_axb_26),.LO(reg3_1_1_cry_26));
XORCY reg3_1_1_s_25(.LI(reg3_1_1_axb_25),.CI(reg3_1_1_cry_24),.O(reg3_1_1[25:25]));
MUXCY_L reg3_1_1_cry_25_cZ(.DI(GND),.CI(reg3_1_1_cry_24),.S(reg3_1_1_axb_25),.LO(reg3_1_1_cry_25));
XORCY reg3_1_1_s_24(.LI(reg3_1_1_axb_24),.CI(reg3_1_1_cry_23),.O(reg3_1_1[24:24]));
MUXCY_L reg3_1_1_cry_24_cZ(.DI(GND),.CI(reg3_1_1_cry_23),.S(reg3_1_1_axb_24),.LO(reg3_1_1_cry_24));
XORCY reg3_1_1_s_23(.LI(reg3_1_1_axb_23),.CI(reg3_1_1_cry_22),.O(reg3_1_1[23:23]));
MUXCY_L reg3_1_1_cry_23_cZ(.DI(GND),.CI(reg3_1_1_cry_22),.S(reg3_1_1_axb_23),.LO(reg3_1_1_cry_23));
XORCY reg3_1_1_s_22(.LI(reg3_1_1_axb_22),.CI(reg3_1_1_cry_21),.O(reg3_1_1[22:22]));
MUXCY_L reg3_1_1_cry_22_cZ(.DI(GND),.CI(reg3_1_1_cry_21),.S(reg3_1_1_axb_22),.LO(reg3_1_1_cry_22));
XORCY reg3_1_1_s_21(.LI(reg3_1_1_axb_21),.CI(reg3_1_1_cry_20),.O(reg3_1_1[21:21]));
MUXCY_L reg3_1_1_cry_21_cZ(.DI(GND),.CI(reg3_1_1_cry_20),.S(reg3_1_1_axb_21),.LO(reg3_1_1_cry_21));
XORCY reg3_1_1_s_20(.LI(reg3_1_1_axb_20),.CI(reg3_1_1_cry_19),.O(reg3_1_1[20:20]));
MUXCY_L reg3_1_1_cry_20_cZ(.DI(GND),.CI(reg3_1_1_cry_19),.S(reg3_1_1_axb_20),.LO(reg3_1_1_cry_20));
XORCY reg3_1_1_s_19(.LI(reg3_1_1_axb_19),.CI(reg3_1_1_cry_18),.O(reg3_1_1[19:19]));
MUXCY_L reg3_1_1_cry_19_cZ(.DI(GND),.CI(reg3_1_1_cry_18),.S(reg3_1_1_axb_19),.LO(reg3_1_1_cry_19));
XORCY reg3_1_1_s_18(.LI(reg3_1_1_axb_18),.CI(reg3_1_1_cry_17),.O(reg3_1_1[18:18]));
MUXCY_L reg3_1_1_cry_18_cZ(.DI(GND),.CI(reg3_1_1_cry_17),.S(reg3_1_1_axb_18),.LO(reg3_1_1_cry_18));
XORCY reg3_1_1_s_17(.LI(reg3_1_1_axb_17),.CI(reg3_1_1_cry_16),.O(reg3_1_1[17:17]));
MUXCY_L reg3_1_1_cry_17_cZ(.DI(GND),.CI(reg3_1_1_cry_16),.S(reg3_1_1_axb_17),.LO(reg3_1_1_cry_17));
XORCY reg3_1_1_s_16(.LI(reg3_1_1_axb_16),.CI(reg3_1_1_cry_15),.O(reg3_1_1[16:16]));
MUXCY_L reg3_1_1_cry_16_cZ(.DI(GND),.CI(reg3_1_1_cry_15),.S(reg3_1_1_axb_16),.LO(reg3_1_1_cry_16));
XORCY reg3_1_1_s_15(.LI(reg3_1_1_axb_15),.CI(reg3_1_1_cry_14),.O(reg3_1_1[15:15]));
MUXCY_L reg3_1_1_cry_15_cZ(.DI(GND),.CI(reg3_1_1_cry_14),.S(reg3_1_1_axb_15),.LO(reg3_1_1_cry_15));
XORCY reg3_1_1_s_14(.LI(reg3_1_1_axb_14),.CI(reg3_1_1_cry_13),.O(reg3_1_1[14:14]));
MUXCY_L reg3_1_1_cry_14_cZ(.DI(GND),.CI(reg3_1_1_cry_13),.S(reg3_1_1_axb_14),.LO(reg3_1_1_cry_14));
XORCY reg3_1_1_s_13(.LI(reg3_1_1_axb_13),.CI(reg3_1_1_cry_12),.O(reg3_1_1[13:13]));
MUXCY_L reg3_1_1_cry_13_cZ(.DI(GND),.CI(reg3_1_1_cry_12),.S(reg3_1_1_axb_13),.LO(reg3_1_1_cry_13));
XORCY reg3_1_1_s_12(.LI(reg3_1_1_axb_12),.CI(reg3_1_1_cry_11),.O(reg3_1_1[12:12]));
MUXCY_L reg3_1_1_cry_12_cZ(.DI(GND),.CI(reg3_1_1_cry_11),.S(reg3_1_1_axb_12),.LO(reg3_1_1_cry_12));
XORCY reg3_1_1_s_11(.LI(reg3_1_1_axb_11),.CI(reg3_1_1_cry_10),.O(reg3_1_1[11:11]));
MUXCY_L reg3_1_1_cry_11_cZ(.DI(GND),.CI(reg3_1_1_cry_10),.S(reg3_1_1_axb_11),.LO(reg3_1_1_cry_11));
XORCY reg3_1_1_s_10(.LI(reg3_1_1_axb_10),.CI(reg3_1_1_cry_9),.O(reg3_1_1[10:10]));
MUXCY_L reg3_1_1_cry_10_cZ(.DI(GND),.CI(reg3_1_1_cry_9),.S(reg3_1_1_axb_10),.LO(reg3_1_1_cry_10));
XORCY reg3_1_1_s_9(.LI(reg3_1_1_axb_9),.CI(reg3_1_1_cry_8),.O(reg3_1_1[9:9]));
MUXCY_L reg3_1_1_cry_9_cZ(.DI(GND),.CI(reg3_1_1_cry_8),.S(reg3_1_1_axb_9),.LO(reg3_1_1_cry_9));
XORCY reg3_1_1_s_8(.LI(reg3_1_1_axb_8),.CI(reg3_1_1_cry_7),.O(reg3_1_1[8:8]));
MUXCY_L reg3_1_1_cry_8_cZ(.DI(GND),.CI(reg3_1_1_cry_7),.S(reg3_1_1_axb_8),.LO(reg3_1_1_cry_8));
XORCY reg3_1_1_s_7(.LI(reg3_1_1_axb_7),.CI(reg3_1_1_cry_6),.O(reg3_1_1[7:7]));
MUXCY_L reg3_1_1_cry_7_cZ(.DI(GND),.CI(reg3_1_1_cry_6),.S(reg3_1_1_axb_7),.LO(reg3_1_1_cry_7));
XORCY reg3_1_1_s_6(.LI(reg3_1_1_axb_6),.CI(reg3_1_1_cry_5),.O(reg3_1_1[6:6]));
MUXCY_L reg3_1_1_cry_6_cZ(.DI(GND),.CI(reg3_1_1_cry_5),.S(reg3_1_1_axb_6),.LO(reg3_1_1_cry_6));
XORCY reg3_1_1_s_5(.LI(reg3_1_1_axb_5),.CI(reg3_1_1_cry_4),.O(reg3_1_1[5:5]));
MUXCY_L reg3_1_1_cry_5_cZ(.DI(GND),.CI(reg3_1_1_cry_4),.S(reg3_1_1_axb_5),.LO(reg3_1_1_cry_5));
XORCY reg3_1_1_s_4(.LI(reg3_1_1_axb_4),.CI(reg3_1_1_cry_3),.O(reg3_1_1[4:4]));
MUXCY_L reg3_1_1_cry_4_cZ(.DI(GND),.CI(reg3_1_1_cry_3),.S(reg3_1_1_axb_4),.LO(reg3_1_1_cry_4));
XORCY reg3_1_1_s_3(.LI(reg3_1_1_axb_3),.CI(reg3_1_1_cry_2),.O(reg3_1_1[3:3]));
MUXCY_L reg3_1_1_cry_3_cZ(.DI(GND),.CI(reg3_1_1_cry_2),.S(reg3_1_1_axb_3),.LO(reg3_1_1_cry_3));
XORCY reg3_1_1_s_2(.LI(reg3_1_1_axb_2),.CI(reg3_1_1_cry_1),.O(reg3_1_1[2:2]));
MUXCY_L reg3_1_1_cry_2_cZ(.DI(GND),.CI(reg3_1_1_cry_1),.S(reg3_1_1_axb_2),.LO(reg3_1_1_cry_2));
XORCY reg3_1_1_s_1(.LI(reg3_1_1_axb_1),.CI(reg3_1_1_cry_0),.O(reg3_1_1[1:1]));
MUXCY_L reg3_1_1_cry_1_cZ(.DI(GND),.CI(reg3_1_1_cry_0),.S(reg3_1_1_axb_1),.LO(reg3_1_1_cry_1));
MUXCY_L reg3_1_1_cry_0_cZ(.DI(GND),.CI(VCC),.S(reg3_1_1_axb_0),.LO(reg3_1_1_cry_0));
XORCY inf_abs0_2_s_30(.LI(inf_abs0_2_axb_30),.CI(inf_abs0_2_cry_29),.O(inf_abs0_2[30:30]));
MUXCY inf_abs0_2_cry_30(.DI(GND),.CI(inf_abs0_2_cry_29),.S(inf_abs0_2_axb_30),.O(inf_abs0_2_0[31:31]));
XORCY inf_abs0_2_s_29(.LI(inf_abs0_2_axb_29),.CI(inf_abs0_2_cry_28),.O(inf_abs0_2[29:29]));
XORCY inf_abs0_2_s_28(.LI(inf_abs0_2_axb_28),.CI(inf_abs0_2_cry_27),.O(inf_abs0_2[28:28]));
MUXCY_L inf_abs0_2_cry_28_cZ(.DI(GND),.CI(inf_abs0_2_cry_27),.S(inf_abs0_2_axb_28),.LO(inf_abs0_2_cry_28));
XORCY inf_abs0_2_s_27(.LI(inf_abs0_2_axb_27),.CI(inf_abs0_2_cry_26),.O(inf_abs0_2[27:27]));
MUXCY_L inf_abs0_2_cry_27_cZ(.DI(GND),.CI(inf_abs0_2_cry_26),.S(inf_abs0_2_axb_27),.LO(inf_abs0_2_cry_27));
XORCY inf_abs0_2_s_26(.LI(inf_abs0_2_axb_26),.CI(inf_abs0_2_cry_25),.O(inf_abs0_2[26:26]));
MUXCY_L inf_abs0_2_cry_26_cZ(.DI(GND),.CI(inf_abs0_2_cry_25),.S(inf_abs0_2_axb_26),.LO(inf_abs0_2_cry_26));
XORCY inf_abs0_2_s_25(.LI(inf_abs0_2_axb_25),.CI(inf_abs0_2_cry_24),.O(inf_abs0_2[25:25]));
MUXCY_L inf_abs0_2_cry_25_cZ(.DI(GND),.CI(inf_abs0_2_cry_24),.S(inf_abs0_2_axb_25),.LO(inf_abs0_2_cry_25));
XORCY inf_abs0_2_s_24(.LI(inf_abs0_2_axb_24),.CI(inf_abs0_2_cry_23),.O(inf_abs0_2[24:24]));
MUXCY_L inf_abs0_2_cry_24_cZ(.DI(GND),.CI(inf_abs0_2_cry_23),.S(inf_abs0_2_axb_24),.LO(inf_abs0_2_cry_24));
XORCY inf_abs0_2_s_23(.LI(inf_abs0_2_axb_23),.CI(inf_abs0_2_cry_22),.O(inf_abs0_2[23:23]));
MUXCY_L inf_abs0_2_cry_23_cZ(.DI(GND),.CI(inf_abs0_2_cry_22),.S(inf_abs0_2_axb_23),.LO(inf_abs0_2_cry_23));
XORCY inf_abs0_2_s_22(.LI(inf_abs0_2_axb_22),.CI(inf_abs0_2_cry_21),.O(inf_abs0_2[22:22]));
MUXCY_L inf_abs0_2_cry_22_cZ(.DI(GND),.CI(inf_abs0_2_cry_21),.S(inf_abs0_2_axb_22),.LO(inf_abs0_2_cry_22));
XORCY inf_abs0_2_s_21(.LI(inf_abs0_2_axb_21),.CI(inf_abs0_2_cry_20),.O(inf_abs0_2[21:21]));
MUXCY_L inf_abs0_2_cry_21_cZ(.DI(GND),.CI(inf_abs0_2_cry_20),.S(inf_abs0_2_axb_21),.LO(inf_abs0_2_cry_21));
XORCY inf_abs0_2_s_20(.LI(inf_abs0_2_axb_20),.CI(inf_abs0_2_cry_19),.O(inf_abs0_2[20:20]));
MUXCY_L inf_abs0_2_cry_20_cZ(.DI(GND),.CI(inf_abs0_2_cry_19),.S(inf_abs0_2_axb_20),.LO(inf_abs0_2_cry_20));
XORCY inf_abs0_2_s_19(.LI(inf_abs0_2_axb_19),.CI(inf_abs0_2_cry_18),.O(inf_abs0_2[19:19]));
MUXCY_L inf_abs0_2_cry_19_cZ(.DI(GND),.CI(inf_abs0_2_cry_18),.S(inf_abs0_2_axb_19),.LO(inf_abs0_2_cry_19));
XORCY inf_abs0_2_s_18(.LI(inf_abs0_2_axb_18),.CI(inf_abs0_2_cry_17),.O(inf_abs0_2[18:18]));
MUXCY_L inf_abs0_2_cry_18_cZ(.DI(GND),.CI(inf_abs0_2_cry_17),.S(inf_abs0_2_axb_18),.LO(inf_abs0_2_cry_18));
XORCY inf_abs0_2_s_17(.LI(inf_abs0_2_axb_17),.CI(inf_abs0_2_cry_16),.O(inf_abs0_2[17:17]));
MUXCY_L inf_abs0_2_cry_17_cZ(.DI(GND),.CI(inf_abs0_2_cry_16),.S(inf_abs0_2_axb_17),.LO(inf_abs0_2_cry_17));
XORCY inf_abs0_2_s_16(.LI(inf_abs0_2_axb_16),.CI(inf_abs0_2_cry_15),.O(inf_abs0_2[16:16]));
MUXCY_L inf_abs0_2_cry_16_cZ(.DI(GND),.CI(inf_abs0_2_cry_15),.S(inf_abs0_2_axb_16),.LO(inf_abs0_2_cry_16));
XORCY inf_abs0_2_s_15(.LI(inf_abs0_2_axb_15),.CI(inf_abs0_2_cry_14),.O(inf_abs0_2[15:15]));
MUXCY_L inf_abs0_2_cry_15_cZ(.DI(GND),.CI(inf_abs0_2_cry_14),.S(inf_abs0_2_axb_15),.LO(inf_abs0_2_cry_15));
XORCY inf_abs0_2_s_14(.LI(inf_abs0_2_axb_14),.CI(inf_abs0_2_cry_13),.O(inf_abs0_2[14:14]));
MUXCY_L inf_abs0_2_cry_14_cZ(.DI(GND),.CI(inf_abs0_2_cry_13),.S(inf_abs0_2_axb_14),.LO(inf_abs0_2_cry_14));
XORCY inf_abs0_2_s_13(.LI(inf_abs0_2_axb_13),.CI(inf_abs0_2_cry_12),.O(inf_abs0_2[13:13]));
MUXCY_L inf_abs0_2_cry_13_cZ(.DI(GND),.CI(inf_abs0_2_cry_12),.S(inf_abs0_2_axb_13),.LO(inf_abs0_2_cry_13));
XORCY inf_abs0_2_s_12(.LI(inf_abs0_2_axb_12),.CI(inf_abs0_2_cry_11),.O(inf_abs0_2[12:12]));
MUXCY_L inf_abs0_2_cry_12_cZ(.DI(GND),.CI(inf_abs0_2_cry_11),.S(inf_abs0_2_axb_12),.LO(inf_abs0_2_cry_12));
XORCY inf_abs0_2_s_11(.LI(inf_abs0_2_axb_11),.CI(inf_abs0_2_cry_10),.O(inf_abs0_2[11:11]));
MUXCY_L inf_abs0_2_cry_11_cZ(.DI(GND),.CI(inf_abs0_2_cry_10),.S(inf_abs0_2_axb_11),.LO(inf_abs0_2_cry_11));
XORCY inf_abs0_2_s_10(.LI(inf_abs0_2_axb_10),.CI(inf_abs0_2_cry_9),.O(inf_abs0_2[10:10]));
MUXCY_L inf_abs0_2_cry_10_cZ(.DI(GND),.CI(inf_abs0_2_cry_9),.S(inf_abs0_2_axb_10),.LO(inf_abs0_2_cry_10));
XORCY inf_abs0_2_s_9(.LI(inf_abs0_2_axb_9),.CI(inf_abs0_2_cry_8),.O(inf_abs0_2[9:9]));
MUXCY_L inf_abs0_2_cry_9_cZ(.DI(GND),.CI(inf_abs0_2_cry_8),.S(inf_abs0_2_axb_9),.LO(inf_abs0_2_cry_9));
XORCY inf_abs0_2_s_8(.LI(inf_abs0_2_axb_8),.CI(inf_abs0_2_cry_7),.O(inf_abs0_2[8:8]));
MUXCY_L inf_abs0_2_cry_8_cZ(.DI(GND),.CI(inf_abs0_2_cry_7),.S(inf_abs0_2_axb_8),.LO(inf_abs0_2_cry_8));
XORCY inf_abs0_2_s_7(.LI(inf_abs0_2_axb_7),.CI(inf_abs0_2_cry_6),.O(inf_abs0_2[7:7]));
MUXCY_L inf_abs0_2_cry_7_cZ(.DI(GND),.CI(inf_abs0_2_cry_6),.S(inf_abs0_2_axb_7),.LO(inf_abs0_2_cry_7));
XORCY inf_abs0_2_s_6(.LI(inf_abs0_2_axb_6),.CI(inf_abs0_2_cry_5),.O(inf_abs0_2[6:6]));
MUXCY_L inf_abs0_2_cry_6_cZ(.DI(GND),.CI(inf_abs0_2_cry_5),.S(inf_abs0_2_axb_6),.LO(inf_abs0_2_cry_6));
XORCY inf_abs0_2_s_5(.LI(inf_abs0_2_axb_5),.CI(inf_abs0_2_cry_4),.O(inf_abs0_2[5:5]));
MUXCY_L inf_abs0_2_cry_5_cZ(.DI(GND),.CI(inf_abs0_2_cry_4),.S(inf_abs0_2_axb_5),.LO(inf_abs0_2_cry_5));
XORCY inf_abs0_2_s_4(.LI(inf_abs0_2_axb_4),.CI(inf_abs0_2_cry_3),.O(inf_abs0_2[4:4]));
MUXCY_L inf_abs0_2_cry_4_cZ(.DI(GND),.CI(inf_abs0_2_cry_3),.S(inf_abs0_2_axb_4),.LO(inf_abs0_2_cry_4));
XORCY inf_abs0_2_s_3(.LI(inf_abs0_2_axb_3),.CI(inf_abs0_2_cry_2),.O(inf_abs0_2[3:3]));
MUXCY_L inf_abs0_2_cry_3_cZ(.DI(GND),.CI(inf_abs0_2_cry_2),.S(inf_abs0_2_axb_3),.LO(inf_abs0_2_cry_3));
XORCY inf_abs0_2_s_2(.LI(inf_abs0_2_axb_2),.CI(inf_abs0_2_cry_1),.O(inf_abs0_2[2:2]));
MUXCY_L inf_abs0_2_cry_2_cZ(.DI(GND),.CI(inf_abs0_2_cry_1),.S(inf_abs0_2_axb_2),.LO(inf_abs0_2_cry_2));
XORCY inf_abs0_2_s_1(.LI(inf_abs0_2_axb_1),.CI(inf_abs0_2_cry_0),.O(inf_abs0_2[1:1]));
MUXCY_L inf_abs0_2_cry_1_cZ(.DI(GND),.CI(inf_abs0_2_cry_0),.S(inf_abs0_2_axb_1),.LO(inf_abs0_2_cry_1));
XORCY inf_abs0_2_s_0(.LI(inf_abs0_2_axb_0),.CI(ir_fast[31:31]),.O(inf_abs0_2[0:0]));
MUXCY_L inf_abs0_2_cry_0_cZ(.DI(GND),.CI(ir_fast[31:31]),.S(inf_abs0_2_axb_0),.LO(inf_abs0_2_cry_0));
LUT4 un26_r_lt30_cZ(.I0(m_2_i[31:31]),.I1(m_2[30:30]),.I2(r_4_i[31:31]),.I3(r_6[30:30]),.O(un26_r_lt30));
defparam un26_r_lt30_cZ.INIT=16'h0A8E;
MUXCY_L desc1024(.DI(un26_r_lt28),.CI(un26_r_cry[26:26]),.S(un26_r_df28),.LO(un26_r_cry[28:28]));
MUXCY_L desc1025(.DI(un26_r_lt26),.CI(un26_r_cry[24:24]),.S(un26_r_df26),.LO(un26_r_cry[26:26]));
MUXCY_L desc1026(.DI(un26_r_lt24),.CI(un26_r_cry[22:22]),.S(un26_r_df24),.LO(un26_r_cry[24:24]));
MUXCY_L desc1027(.DI(un26_r_lt22),.CI(un26_r_cry[20:20]),.S(un26_r_df22),.LO(un26_r_cry[22:22]));
MUXCY_L desc1028(.DI(un26_r_lt20),.CI(un26_r_cry[18:18]),.S(un26_r_df20),.LO(un26_r_cry[20:20]));
MUXCY_L desc1029(.DI(un26_r_lt18),.CI(un26_r_cry[16:16]),.S(un26_r_df18),.LO(un26_r_cry[18:18]));
LUT4 un26_r_lt18_cZ(.I0(m_2[19:19]),.I1(m_2[18:18]),.I2(r_4[19:19]),.I3(r_4[18:18]),.O(un26_r_lt18));
defparam un26_r_lt18_cZ.INIT=16'h0A8E;
MUXCY_L desc1030(.DI(un26_r_lt16),.CI(un26_r_cry[14:14]),.S(un26_r_df16),.LO(un26_r_cry[16:16]));
LUT4 un26_r_lt16_cZ(.I0(m_2[16:16]),.I1(m_2[17:17]),.I2(r_4[16:16]),.I3(r_4[17:17]),.O(un26_r_lt16));
defparam un26_r_lt16_cZ.INIT=16'h08CE;
MUXCY_L desc1031(.DI(un26_r_lt14),.CI(un26_r_cry[12:12]),.S(un26_r_df14),.LO(un26_r_cry[14:14]));
LUT4 un26_r_lt14_cZ(.I0(m_2[14:14]),.I1(m_2[15:15]),.I2(r_4[14:14]),.I3(r_4[15:15]),.O(un26_r_lt14));
defparam un26_r_lt14_cZ.INIT=16'h08CE;
MUXCY_L desc1032(.DI(un26_r_lt12),.CI(un26_r_cry[10:10]),.S(un26_r_df12),.LO(un26_r_cry[12:12]));
LUT4 un26_r_lt12_cZ(.I0(m_2[12:12]),.I1(m_2[13:13]),.I2(r_4[12:12]),.I3(r_4[13:13]),.O(un26_r_lt12));
defparam un26_r_lt12_cZ.INIT=16'h08CE;
MUXCY_L desc1033(.DI(un26_r_lt10),.CI(un26_r_cry[8:8]),.S(un26_r_df10),.LO(un26_r_cry[10:10]));
LUT4 un26_r_lt10_cZ(.I0(m_2[10:10]),.I1(m_2[11:11]),.I2(r_4[11:11]),.I3(r_4[10:10]),.O(un26_r_lt10));
defparam un26_r_lt10_cZ.INIT=16'h0C8E;
MUXCY_L desc1034(.DI(un26_r_lt8),.CI(un26_r_cry[6:6]),.S(un26_r_df8),.LO(un26_r_cry[8:8]));
LUT4 un26_r_lt8_cZ(.I0(m_2[8:8]),.I1(m_2[9:9]),.I2(r_4[8:8]),.I3(r_4[9:9]),.O(un26_r_lt8));
defparam un26_r_lt8_cZ.INIT=16'h08CE;
MUXCY_L desc1035(.DI(un26_r_lt6),.CI(un26_r_cry[4:4]),.S(un26_r_df6),.LO(un26_r_cry[6:6]));
LUT4 un26_r_lt6_cZ(.I0(m_2[7:7]),.I1(m_2[6:6]),.I2(r_4[6:6]),.I3(r_4[7:7]),.O(un26_r_lt6));
defparam un26_r_lt6_cZ.INIT=16'h08AE;
MUXCY_L desc1036(.DI(un26_r_lt4),.CI(un26_r_cry[2:2]),.S(un26_r_df4),.LO(un26_r_cry[4:4]));
LUT4 un26_r_lt4_cZ(.I0(m_2[4:4]),.I1(m_2[5:5]),.I2(r_4[4:4]),.I3(r_4[5:5]),.O(un26_r_lt4));
defparam un26_r_lt4_cZ.INIT=16'h08CE;
MUXCY_L desc1037(.DI(un26_r_lt2),.CI(un26_r_cry[0:0]),.S(un26_r_df2),.LO(un26_r_cry[2:2]));
LUT4 un26_r_lt2_cZ(.I0(m_2[2:2]),.I1(m_2[3:3]),.I2(r_4[3:3]),.I3(N_28),.O(un26_r_lt2));
defparam un26_r_lt2_cZ.INIT=16'h0C8E;
MUXCY_L desc1038(.DI(un26_r_lt0),.CI(GND),.S(un26_r_df0),.LO(un26_r_cry[0:0]));
LUT4 un26_r_lt0_cZ(.I0(m_2[1:1]),.I1(m_2[0:0]),.I2(r_4[0:0]),.I3(r_4[1:1]),.O(un26_r_lt0));
defparam un26_r_lt0_cZ.INIT=16'h08AE;
MUXCY_L desc1039(.DI(b18_lt28),.CI(b18_cry[26:26]),.S(b18_df28),.LO(b18_cry[28:28]));
MUXCY_L desc1040(.DI(b18_lt26),.CI(b18_cry[24:24]),.S(b18_df26),.LO(b18_cry[26:26]));
MUXCY_L desc1041(.DI(b18_lt24),.CI(b18_cry[22:22]),.S(b18_df24),.LO(b18_cry[24:24]));
MUXCY_L desc1042(.DI(b18_lt22),.CI(b18_cry[20:20]),.S(b18_df22),.LO(b18_cry[22:22]));
MUXCY_L desc1043(.DI(b18_lt20),.CI(b18_cry[18:18]),.S(b18_df20),.LO(b18_cry[20:20]));
MUXCY_L desc1044(.DI(b18_lt18),.CI(b18_cry[16:16]),.S(b18_df18),.LO(b18_cry[18:18]));
LUT4 b18_lt18_cZ(.I0(m_2[19:19]),.I1(m_2[18:18]),.I2(r_4[19:19]),.I3(r_4[18:18]),.O(b18_lt18));
defparam b18_lt18_cZ.INIT=16'h7150;
MUXCY_L desc1045(.DI(b18_lt16),.CI(b18_cry[14:14]),.S(b18_df16),.LO(b18_cry[16:16]));
LUT4 b18_lt16_cZ(.I0(m_2[16:16]),.I1(m_2[17:17]),.I2(r_4[16:16]),.I3(r_4[17:17]),.O(b18_lt16));
defparam b18_lt16_cZ.INIT=16'h7310;
MUXCY_L desc1046(.DI(b18_lt14),.CI(b18_cry[12:12]),.S(b18_df14),.LO(b18_cry[14:14]));
LUT4 b18_lt14_cZ(.I0(m_2[14:14]),.I1(m_2[15:15]),.I2(r_4[14:14]),.I3(r_4[15:15]),.O(b18_lt14));
defparam b18_lt14_cZ.INIT=16'h7310;
MUXCY_L desc1047(.DI(b18_lt12),.CI(b18_cry[10:10]),.S(b18_df12),.LO(b18_cry[12:12]));
LUT4 b18_lt12_cZ(.I0(m_2[12:12]),.I1(m_2[13:13]),.I2(r_4[12:12]),.I3(r_4[13:13]),.O(b18_lt12));
defparam b18_lt12_cZ.INIT=16'h7310;
MUXCY_L desc1048(.DI(b18_lt10),.CI(b18_cry[8:8]),.S(b18_df10),.LO(b18_cry[10:10]));
LUT4 b18_lt10_cZ(.I0(m_2[10:10]),.I1(m_2[11:11]),.I2(r_4[11:11]),.I3(r_4[10:10]),.O(b18_lt10));
defparam b18_lt10_cZ.INIT=16'h7130;
MUXCY_L desc1049(.DI(b18_lt8),.CI(b18_cry[6:6]),.S(b18_df8),.LO(b18_cry[8:8]));
LUT4 b18_lt8_cZ(.I0(m_2[8:8]),.I1(m_2[9:9]),.I2(r_4[8:8]),.I3(r_4[9:9]),.O(b18_lt8));
defparam b18_lt8_cZ.INIT=16'h7310;
MUXCY_L desc1050(.DI(b18_lt6),.CI(b18_cry[4:4]),.S(b18_df6),.LO(b18_cry[6:6]));
LUT4 b18_lt6_cZ(.I0(m_2[7:7]),.I1(m_2[6:6]),.I2(r_4[6:6]),.I3(r_4[7:7]),.O(b18_lt6));
defparam b18_lt6_cZ.INIT=16'h7510;
MUXCY_L desc1051(.DI(b18_lt4),.CI(b18_cry[2:2]),.S(b18_df4),.LO(b18_cry[4:4]));
LUT4 b18_lt4_cZ(.I0(m_2[4:4]),.I1(m_2[5:5]),.I2(r_4[4:4]),.I3(r_4[5:5]),.O(b18_lt4));
defparam b18_lt4_cZ.INIT=16'h7310;
MUXCY_L desc1052(.DI(b18_lt2),.CI(b18_cry[0:0]),.S(b18_df2),.LO(b18_cry[2:2]));
LUT4 b18_lt2_cZ(.I0(m_2[2:2]),.I1(m_2[3:3]),.I2(r_4[3:3]),.I3(N_28),.O(b18_lt2));
defparam b18_lt2_cZ.INIT=16'h7130;
MUXCY_L desc1053(.DI(b18_lt0),.CI(GND),.S(b18_df0),.LO(b18_cry[0:0]));
LUT4 b18_lt0_cZ(.I0(m_2[1:1]),.I1(m_2[0:0]),.I2(r_4[0:0]),.I3(r_4[1:1]),.O(b18_lt0));
defparam b18_lt0_cZ.INIT=16'h7510;
MUXCY_L desc1054(.DI(un11_r_lt28),.CI(un11_r_cry[26:26]),.S(un11_r_df28),.LO(un11_r_cry[28:28]));
MUXCY_L desc1055(.DI(un11_r_lt26),.CI(un11_r_cry[24:24]),.S(un11_r_df26),.LO(un11_r_cry[26:26]));
MUXCY_L desc1056(.DI(un11_r_lt24),.CI(un11_r_cry[22:22]),.S(un11_r_df24),.LO(un11_r_cry[24:24]));
MUXCY_L desc1057(.DI(un11_r_lt22),.CI(un11_r_cry[20:20]),.S(un11_r_df22),.LO(un11_r_cry[22:22]));
MUXCY_L desc1058(.DI(un11_r_lt20),.CI(un11_r_cry[18:18]),.S(un11_r_df20),.LO(un11_r_cry[20:20]));
MUXCY_L desc1059(.DI(un11_r_lt18),.CI(un11_r_cry[16:16]),.S(un11_r_df18),.LO(un11_r_cry[18:18]));
LUT4 un11_r_lt18_cZ(.I0(m_2[19:19]),.I1(m_2[18:18]),.I2(r_4[19:19]),.I3(r_4[18:18]),.O(un11_r_lt18));
defparam un11_r_lt18_cZ.INIT=16'h0A8E;
MUXCY_L desc1060(.DI(un11_r_lt16),.CI(un11_r_cry[14:14]),.S(un11_r_df16),.LO(un11_r_cry[16:16]));
LUT4 un11_r_lt16_cZ(.I0(m_2[16:16]),.I1(m_2[17:17]),.I2(r_4[16:16]),.I3(r_4[17:17]),.O(un11_r_lt16));
defparam un11_r_lt16_cZ.INIT=16'h08CE;
MUXCY_L desc1061(.DI(un11_r_lt14),.CI(un11_r_cry[12:12]),.S(un11_r_df14),.LO(un11_r_cry[14:14]));
LUT4 un11_r_lt14_cZ(.I0(m_2[14:14]),.I1(m_2[15:15]),.I2(r_4[14:14]),.I3(r_4[15:15]),.O(un11_r_lt14));
defparam un11_r_lt14_cZ.INIT=16'h08CE;
MUXCY_L desc1062(.DI(un11_r_lt12),.CI(un11_r_cry[10:10]),.S(un11_r_df12),.LO(un11_r_cry[12:12]));
LUT4 un11_r_lt12_cZ(.I0(m_2[12:12]),.I1(m_2[13:13]),.I2(r_4[12:12]),.I3(r_4[13:13]),.O(un11_r_lt12));
defparam un11_r_lt12_cZ.INIT=16'h08CE;
MUXCY_L desc1063(.DI(un11_r_lt10),.CI(un11_r_cry[8:8]),.S(un11_r_df10),.LO(un11_r_cry[10:10]));
LUT4 un11_r_lt10_cZ(.I0(m_2[10:10]),.I1(m_2[11:11]),.I2(r_4[11:11]),.I3(r_4[10:10]),.O(un11_r_lt10));
defparam un11_r_lt10_cZ.INIT=16'h0C8E;
MUXCY_L desc1064(.DI(un11_r_lt8),.CI(un11_r_cry[6:6]),.S(un11_r_df8),.LO(un11_r_cry[8:8]));
LUT4 un11_r_lt8_cZ(.I0(m_2[8:8]),.I1(m_2[9:9]),.I2(r_4[8:8]),.I3(r_4[9:9]),.O(un11_r_lt8));
defparam un11_r_lt8_cZ.INIT=16'h08CE;
MUXCY_L desc1065(.DI(un11_r_lt6),.CI(un11_r_cry[4:4]),.S(un11_r_df6),.LO(un11_r_cry[6:6]));
LUT4 un11_r_lt6_cZ(.I0(m_2[7:7]),.I1(m_2[6:6]),.I2(r_4[6:6]),.I3(r_4[7:7]),.O(un11_r_lt6));
defparam un11_r_lt6_cZ.INIT=16'h08AE;
MUXCY_L desc1066(.DI(un11_r_lt4),.CI(un11_r_cry[2:2]),.S(un11_r_df4),.LO(un11_r_cry[4:4]));
LUT4 un11_r_lt4_cZ(.I0(m_2[4:4]),.I1(m_2[5:5]),.I2(r_4[4:4]),.I3(r_4[5:5]),.O(un11_r_lt4));
defparam un11_r_lt4_cZ.INIT=16'h08CE;
MUXCY_L desc1067(.DI(un11_r_lt2),.CI(un11_r_cry[0:0]),.S(un11_r_df2),.LO(un11_r_cry[2:2]));
LUT4 un11_r_lt2_cZ(.I0(m_2[2:2]),.I1(m_2[3:3]),.I2(r_4[3:3]),.I3(N_28),.O(un11_r_lt2));
defparam un11_r_lt2_cZ.INIT=16'h0C8E;
MUXCY_L desc1068(.DI(un11_r_lt0),.CI(GND),.S(un11_r_df0),.LO(un11_r_cry[0:0]));
LUT4 un11_r_lt0_cZ(.I0(m_2[1:1]),.I1(m_2[0:0]),.I2(r_4[0:0]),.I3(r_4[1:1]),.O(un11_r_lt0));
defparam un11_r_lt0_cZ.INIT=16'h08AE;
MUXCY_L un14_r_0_I_75(.DI(GND),.CI(un14_r_0_data_tmp[3:3]),.S(un14_r_0_N_7),.LO(un14_r_0_data_tmp[4:4]));
MUXCY_L un14_r_0_I_67(.DI(GND),.CI(un14_r_0_data_tmp[0:0]),.S(un14_r_0_N_14),.LO(un14_r_0_data_tmp[1:1]));
MUXCY_L un14_r_0_I_59(.DI(GND),.CI(un14_r_0_data_tmp[1:1]),.S(un14_r_0_N_21),.LO(un14_r_0_data_tmp[2:2]));
MUXCY_L un14_r_0_I_51(.DI(GND),.CI(un14_r_0_data_tmp[2:2]),.S(un14_r_0_N_28),.LO(un14_r_0_data_tmp[3:3]));
MUXCY_L un14_r_0_I_43(.DI(GND),.CI(un14_r_0_data_tmp[7:7]),.S(un14_r_0_N_35),.LO(un14_r_0_data_tmp[8:8]));
MUXCY_L un14_r_0_I_35(.DI(GND),.CI(un14_r_0_data_tmp[4:4]),.S(un14_r_0_N_42),.LO(un14_r_0_data_tmp[5:5]));
MUXCY_L un14_r_0_I_27(.DI(GND),.CI(un14_r_0_data_tmp[5:5]),.S(un14_r_0_N_49),.LO(un14_r_0_data_tmp[6:6]));
MUXCY_L un14_r_0_I_19(.DI(GND),.CI(un14_r_0_data_tmp[6:6]),.S(un14_r_0_N_56),.LO(un14_r_0_data_tmp[7:7]));
MUXCY_L un14_r_0_I_11(.DI(GND),.CI(un14_r_0_data_tmp[8:8]),.S(un14_r_0_N_63),.LO(un14_r_0_data_tmp[9:9]));
MUXCY_L un14_r_0_I_1(.DI(GND),.CI(VCC),.S(un14_r_0_N_70),.LO(un14_r_0_data_tmp[0:0]));
LUT4 desc1069(.I0(inf_abs0_2[20:20]),.I1(inf_abs0_2[21:21]),.I2(inf_abs0_2[22:22]),.I3(reg3_1_1[21:21]),.O(\d_cnst_sn.reg0_28_5_2426_a6_1_1 ));
defparam desc1069.INIT=16'h0100;
LUT3 desc1070(.I0(inf_abs0_2[20:20]),.I1(inf_abs0_2[21:21]),.I2(inf_abs0_2[22:22]),.O(\d_cnst_sn.reg0_28_12_2195_a6_1_2_0 ));
defparam desc1070.INIT=8'h01;
LUT4 desc1071(.I0(inf_abs0_2[20:20]),.I1(inf_abs0_2[21:21]),.I2(inf_abs0_2[22:22]),.I3(reg3_1_1[25:25]),.O(\d_cnst_sn.reg0_28_9_2294_a6_1_1 ));
defparam desc1071.INIT=16'h0100;
LUT4 desc1072(.I0(inf_abs0_2[20:20]),.I1(inf_abs0_2[21:21]),.I2(inf_abs0_2[22:22]),.I3(reg3_1_1[26:26]),.O(\d_cnst_sn.reg0_28_10_2261_a6_1_1 ));
defparam desc1072.INIT=16'h0100;
LUT2 desc1073(.I0(reg1[3:3]),.I1(inf_abs0_2[30:30]),.O(r_4_2_a1_lut6_2_O6[3:3]));
defparam desc1073.INIT=4'h1;
LUT2 desc1074(.I0(reg1[4:4]),.I1(inf_abs0_2[30:30]),.O(r_4_2_a1_lut6_2_O5[3:3]));
defparam desc1074.INIT=4'h1;
LUT4 desc1075(.I0(inf_abs0_2[20:20]),.I1(inf_abs0_2[21:21]),.I2(inf_abs0_2[22:22]),.I3(reg3_1_1[23:23]),.O(\d_cnst_sn.reg0_28_7_2360_a6_1_1 ));
defparam desc1075.INIT=16'h0100;
LUT2 desc1076(.I0(inf_abs0_2[21:21]),.I1(inf_abs0_2[22:22]),.O(N_3873_2));
defparam desc1076.INIT=4'h1;
LUT2 desc1077(.I0(datai[31:31]),.I1(inf_abs0_2[20:20]),.O(\d_cnst_sn.g0_0_0_a5_0_0 ));
defparam desc1077.INIT=4'h8;
LUT3 desc1078(.I0(datai[20:20]),.I1(state),.I2(inf_abs0_2[20:20]),.O(ir_3[20:20]));
defparam desc1078.INIT=8'hE2;
LUT3 desc1079(.I0(state),.I1(inf_abs0_2[27:27]),.I2(inf_abs0_2[28:28]),.O(\d_cnst_sn.addr_20_iv_1052_i_a6_2_0 ));
defparam desc1079.INIT=8'h80;
LUT3 desc1080(.I0(datai[30:30]),.I1(state),.I2(inf_abs0_2[30:30]),.O(ir_3[30:30]));
defparam desc1080.INIT=8'hE2;
LUT2 desc1081(.I0(state),.I1(inf_abs0_2[27:27]),.O(\d_cnst_sn.addr_20_iv_1052_i_a6_1_0 ));
defparam desc1081.INIT=4'h2;
LUT3 desc1082(.I0(datai[31:31]),.I1(state),.I2(inf_abs0_2[31:31]),.O(ir_3[31:31]));
defparam desc1082.INIT=8'hE2;
LUT3 desc1083(.I0(inf_abs0_2[20:20]),.I1(inf_abs0_2[21:21]),.I2(inf_abs0_2[22:22]),.O(\d_cnst_sn.reg0_28_2526_a5_1_0 ));
defparam desc1083.INIT=8'h01;
LUT4 desc1084(.I0(inf_abs0_2[21:21]),.I1(inf_abs0_2[22:22]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[28:28]),.O(\d_cnst_sn.g0_0_0_a5_2 ));
defparam desc1084.INIT=16'h0008;
LUT4 desc1085(.I0(inf_abs0_2[20:20]),.I1(inf_abs0_2[21:21]),.I2(inf_abs0_2[22:22]),.I3(inf_abs0_2[31:31]),.O(\d_cnst_sn.reg0_N_13_0 ));
defparam desc1085.INIT=16'h003E;
LUT3 desc1086(.I0(inf_abs0_2[21:21]),.I1(inf_abs0_2[22:22]),.I2(inf_abs0_2[31:31]),.O(\d_cnst_sn.reg0_m8_e_0 ));
defparam desc1086.INIT=8'h07;
LUT4 desc1087(.I0(inf_abs0_2[20:20]),.I1(inf_abs0_2[21:21]),.I2(inf_abs0_2[22:22]),.I3(reg3_1_1[24:24]),.O(\d_cnst_sn.reg0_28_8_2327_a6_1_1 ));
defparam desc1087.INIT=16'h0100;
LUT3 desc1088(.I0(inf_abs0_2[21:21]),.I1(inf_abs0_2[22:22]),.I2(inf_abs0_2[31:31]),.O(\d_cnst_sn.reg1_16_8_1837_2_tz ));
defparam desc1088.INIT=8'hF8;
LUT2 desc1089(.I0(inf_abs0_2[31:31]),.I1(inf_abs0_2[28:28]),.O(N_527_i));
defparam desc1089.INIT=4'h4;
LUT5 desc1090(.I0(inf_abs0_2[21:21]),.I1(inf_abs0_2[31:31]),.I2(inf_abs0_2[28:28]),.I3(r_4[18:18]),.I4(reg3_1_1[19:19]),.O(\d_cnst_sn.reg0_28_0 [19:19]));
defparam desc1090.INIT=32'hFFDF2202;
LUT4 desc1091(.I0(reg3[19:19]),.I1(state),.I2(inf_abs0_2[19:19]),.I3(inf_abs0_2[28:28]),.O(\d_cnst_sn.addr_20_iv_6_863_i_0 ));
defparam desc1091.INIT=16'h111D;
LUT3 desc1092(.I0(datai[28:28]),.I1(state),.I2(inf_abs0_2[28:28]),.O(ir_3[28:28]));
defparam desc1092.INIT=8'hE2;
LUT2 desc1093(.I0(inf_abs0_2[27:27]),.I1(inf_abs0_2[28:28]),.O(g0_2_0_i2_lut6_2_O6));
defparam desc1093.INIT=4'h1;
LUT4 desc1094(.I0(reg3[18:18]),.I1(state),.I2(inf_abs0_2[18:18]),.I3(inf_abs0_2[28:28]),.O(\d_cnst_sn.addr_20_iv_5_890_i_0 ));
defparam desc1094.INIT=16'h111D;
LUT4 desc1095(.I0(reg3[17:17]),.I1(state),.I2(inf_abs0_2[17:17]),.I3(inf_abs0_2[28:28]),.O(\d_cnst_sn.addr_20_iv_4_917_i_0 ));
defparam desc1095.INIT=16'h111D;
LUT3 desc1096(.I0(datai[17:17]),.I1(state),.I2(inf_abs0_2[17:17]),.O(ir_3[17:17]));
defparam desc1096.INIT=8'hE2;
LUT2 desc1097(.I0(inf_abs0_2[27:27]),.I1(inf_abs0_2[28:28]),.O(N_7));
defparam desc1097.INIT=4'hE;
LUT4 desc1098(.I0(reg3[16:16]),.I1(state),.I2(inf_abs0_2[16:16]),.I3(inf_abs0_2[28:28]),.O(\d_cnst_sn.addr_20_iv_3_944_i_0 ));
defparam desc1098.INIT=16'h111D;
LUT4 desc1099(.I0(reg3[13:13]),.I1(state),.I2(inf_abs0_2[13:13]),.I3(inf_abs0_2[28:28]),.O(\d_cnst_sn.addr_20_iv_0_1025_i_0 ));
defparam desc1099.INIT=16'h111D;
LUT3 desc1100(.I0(datai[13:13]),.I1(state),.I2(inf_abs0_2[13:13]),.O(ir_3[13:13]));
defparam desc1100.INIT=8'hE2;
LUT4 desc1101(.I0(reg3[12:12]),.I1(state),.I2(inf_abs0_2[12:12]),.I3(inf_abs0_2[28:28]),.O(\d_cnst_sn.addr_20_iv_1052_i_0 ));
defparam desc1101.INIT=16'h111D;
LUT3 desc1102(.I0(datai[12:12]),.I1(state),.I2(inf_abs0_2[12:12]),.O(ir_3[12:12]));
defparam desc1102.INIT=8'hE2;
LUT4 desc1103(.I0(reg3[14:14]),.I1(state),.I2(inf_abs0_2[14:14]),.I3(inf_abs0_2[28:28]),.O(\d_cnst_sn.addr_20_iv_1_998_i_0 ));
defparam desc1103.INIT=16'h111D;
LUT3 desc1104(.I0(datai[14:14]),.I1(state),.I2(inf_abs0_2[14:14]),.O(ir_3[14:14]));
defparam desc1104.INIT=8'hE2;
LUT4 desc1105(.I0(reg3[15:15]),.I1(state),.I2(inf_abs0_2[15:15]),.I3(inf_abs0_2[28:28]),.O(\d_cnst_sn.addr_20_iv_2_971_i_0 ));
defparam desc1105.INIT=16'h111D;
LUT3 desc1106(.I0(datai[15:15]),.I1(state),.I2(inf_abs0_2[15:15]),.O(ir_3[15:15]));
defparam desc1106.INIT=8'hE2;
LUT4 desc1107(.I0(inf_abs0_2[20:20]),.I1(inf_abs0_2[21:21]),.I2(inf_abs0_2[22:22]),.I3(reg3_1_1[22:22]),.O(\d_cnst_sn.reg0_28_6_2393_a6_1_1 ));
defparam desc1107.INIT=16'h0100;
LUT3 desc1108(.I0(inf_abs0_2[21:21]),.I1(inf_abs0_2[22:22]),.I2(inf_abs0_2[31:31]),.O(\d_cnst_sn.b60_0 ));
defparam desc1108.INIT=8'h02;
LUT2 desc1109(.I0(inf_abs0_2[20:20]),.I1(inf_abs0_2[31:31]),.O(N_512_i));
defparam desc1109.INIT=4'h2;
LUT3 desc1110(.I0(inf_abs0_2[21:21]),.I1(inf_abs0_2[22:22]),.I2(inf_abs0_2[31:31]),.O(\d_cnst_sn.reg0_m9_i_a3_0 ));
defparam desc1110.INIT=8'h06;
LUT5 desc1111(.I0(inf_abs0_2[21:21]),.I1(inf_abs0_2[31:31]),.I2(inf_abs0_2[28:28]),.I3(r_4[19:19]),.I4(reg3_1_1[20:20]),.O(\d_cnst_sn.reg0_28_0 [20:20]));
defparam desc1111.INIT=32'hFFDF2202;
LUT3 desc1112(.I0(inf_abs0_2[21:21]),.I1(inf_abs0_2[31:31]),.I2(inf_abs0_2[28:28]),.O(\d_cnst_sn.reg0_28_7_a0_0 [9:9]));
defparam desc1112.INIT=8'h02;
LUT3 desc1113(.I0(inf_abs0_2[21:21]),.I1(inf_abs0_2[22:22]),.I2(inf_abs0_2[31:31]),.O(\d_cnst_sn.reg1_16_a2_0 [5:5]));
defparam desc1113.INIT=8'hF1;
LUT2 desc1114(.I0(inf_abs0_2[19:19]),.I1(inf_abs0_2[31:31]),.O(N_3913));
defparam desc1114.INIT=4'hD;
LUT3 desc1115(.I0(inf_abs0_2[19:19]),.I1(inf_abs0_2[20:20]),.I2(inf_abs0_2[31:31]),.O(\d_cnst_sn.reg2_N_3_mux ));
defparam desc1115.INIT=8'hF1;
LUT5 desc1116(.I0(reg3[0:0]),.I1(inf_abs0_2[19:19]),.I2(inf_abs0_2[20:20]),.I3(inf_abs0_2[31:31]),.I4(m_2[0:0]),.O(N_1335));
defparam desc1116.INIT=32'hFFFB0008;
LUT3 desc1117(.I0(inf_abs0_2[21:21]),.I1(inf_abs0_2[22:22]),.I2(inf_abs0_2[31:31]),.O(\d_cnst_sn.b64_0 ));
defparam desc1117.INIT=8'h04;
LUT2 desc1118(.I0(inf_abs0_2[31:31]),.I1(inf_abs0_2[27:27]),.O(N_526_i));
defparam desc1118.INIT=4'h4;
LUT4 desc1119(.I0(datai[30:30]),.I1(inf_abs0_2[31:31]),.I2(inf_abs0_2[27:27]),.I3(inf_abs0_2[28:28]),.O(m_2[30:30]));
defparam desc1119.INIT=16'h2220;
LUT4 desc1120(.I0(datai[31:31]),.I1(inf_abs0_2[31:31]),.I2(inf_abs0_2[27:27]),.I3(inf_abs0_2[28:28]),.O(m_2[31:31]));
defparam desc1120.INIT=16'h2220;
LUT3 desc1121(.I0(inf_abs0_2[21:21]),.I1(inf_abs0_2[22:22]),.I2(inf_abs0_2[31:31]),.O(N_3916));
defparam desc1121.INIT=8'h06;
LUT3 desc1122(.I0(b),.I1(inf_abs0_2[31:31]),.I2(inf_abs0_2[27:27]),.O(reg0_28_sn_m6_lut6_2_O5));
defparam desc1122.INIT=8'h20;
LUT4 desc1123(.I0(b),.I1(inf_abs0_2[21:21]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[27:27]),.O(\d_cnst_sn.reg0_m9_i_a0_0 ));
defparam desc1123.INIT=16'h040C;
LUT2 desc1124(.I0(state),.I1(inf_abs0_2[27:27]),.O(N_2660_2));
defparam desc1124.INIT=4'h8;
LUT4 desc1125(.I0(inf_abs0_2[20:20]),.I1(inf_abs0_2[21:21]),.I2(inf_abs0_2[22:22]),.I3(inf_abs0_2[31:31]),.O(N_3910));
defparam desc1125.INIT=16'h0002;
LUT4 desc1126(.I0(inf_abs0_2[21:21]),.I1(inf_abs0_2[22:22]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[28:28]),.O(\d_cnst_sn.g0_3_a2_2 ));
defparam desc1126.INIT=16'h0008;
LUT4 desc1127(.I0(inf_abs0_2[21:21]),.I1(inf_abs0_2[22:22]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[28:28]),.O(\d_cnst_sn.reg0_28_a1_1 [4:4]));
defparam desc1127.INIT=16'h0800;
LUT4 desc1128(.I0(inf_abs0_2[20:20]),.I1(inf_abs0_2[21:21]),.I2(inf_abs0_2[22:22]),.I3(inf_abs0_2[31:31]),.O(\d_cnst_sn.reg0_28_9_2294_a6_3_0 ));
defparam desc1128.INIT=16'h0002;
LUT4 desc1129(.I0(inf_abs0_2[20:20]),.I1(inf_abs0_2[21:21]),.I2(inf_abs0_2[22:22]),.I3(inf_abs0_2[31:31]),.O(\d_cnst_sn.reg0_28_a0_1 [7:7]));
defparam desc1129.INIT=16'hFF01;
LUT4 desc1130(.I0(inf_abs0_2[21:21]),.I1(inf_abs0_2[22:22]),.I2(inf_abs0_2[31:31]),.I3(inf_abs0_2[28:28]),.O(\d_cnst_sn.reg1_16_a0_1 [3:3]));
defparam desc1130.INIT=16'h0008;
LUT4 desc1131(.I0(datai[31:31]),.I1(inf_abs0_2[31:31]),.I2(inf_abs0_2[27:27]),.I3(inf_abs0_2[28:28]),.O(m_2_i[31:31]));
defparam desc1131.INIT=16'hDDDF;
LUT3 desc1132(.I0(datai[31:31]),.I1(state),.I2(inf_abs0_2[31:31]),.O(ir_3_fast[31:31]));
defparam desc1132.INIT=8'hE2;
LUT4 desc1133(.I0(inf_abs0_2[19:19]),.I1(inf_abs0_2[20:20]),.I2(inf_abs0_2[21:21]),.I3(inf_abs0_2[31:31]),.O(N_1033));
defparam desc1133.INIT=16'hFF35;
LUT5 desc1134(.I0(inf_abs0_2[19:19]),.I1(inf_abs0_2[20:20]),.I2(inf_abs0_2[21:21]),.I3(inf_abs0_2[22:22]),.I4(inf_abs0_2[31:31]),.O(\d_cnst_sn.reg2_16_11_1_tz [28:28]));
defparam desc1134.INIT=32'hFFFFFACF;
LUT5 desc1135(.I0(inf_abs0_2[19:19]),.I1(inf_abs0_2[20:20]),.I2(inf_abs0_2[21:21]),.I3(inf_abs0_2[22:22]),.I4(inf_abs0_2[31:31]),.O(N_1892));
defparam desc1135.INIT=32'h0000E000;
LUT5 desc1136(.I0(inf_abs0_2[19:19]),.I1(inf_abs0_2[20:20]),.I2(inf_abs0_2[21:21]),.I3(inf_abs0_2[22:22]),.I4(inf_abs0_2[31:31]),.O(\d_cnst_sn.reg2_16_0_1_tz [28:28]));
defparam desc1136.INIT=32'hFFFFF53F;
LUT4 b18_df30_lut6_2_o6(.I0(m_2_i[31:31]),.I1(r_4[30:30]),.I2(m_2[30:30]),.I3(r_4_i[31:31]),.O(b18_df30));
defparam b18_df30_lut6_2_o6.INIT=16'h8241;
LUT4 b18_df30_lut6_2_o5(.I0(m_2_i[31:31]),.I1(r_4[30:30]),.I2(m_2[30:30]),.I3(r_4_i[31:31]),.O(b18_lt30));
defparam b18_df30_lut6_2_o5.INIT=16'h5D04;
LUT4 un11_r_df30_lut6_2_o6(.I0(m_2_i[31:31]),.I1(r_4[30:30]),.I2(m_2[30:30]),.I3(r_4_i[31:31]),.O(un11_r_df30));
defparam un11_r_df30_lut6_2_o6.INIT=16'h8241;
LUT4 un11_r_df30_lut6_2_o5(.I0(m_2_i[31:31]),.I1(r_4[30:30]),.I2(m_2[30:30]),.I3(r_4_i[31:31]),.O(un11_r_lt30));
defparam un11_r_df30_lut6_2_o5.INIT=16'h20BA;
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// fpu_post_norm_addsub ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://opencores.org/project,or1k ////
//// ////
//// Description ////
//// post-normalization entity for the addition/subtraction unit ////
//// ////
//// To Do: ////
//// ////
//// ////
//// Author(s): ////
//// - Original design (FPU100) - ////
//// Jidan Al-eryani, [email protected] ////
//// - Conv. to Verilog and inclusion in OR1200 - ////
//// Julius Baxter, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2006, 2010
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR
// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
module fpu_post_norm_addsub
(
clk,
rst,
opa_i,
opb_i,
fract_28_i,
exp_i,
sign_i,
fpu_op_i,
rmode_i,
output_o,
ine_o
);
parameter FP_WIDTH = 32;
parameter MUL_SERIAL = 0; // 0 for parallel multiplier, 1 for serial
parameter MUL_COUNT = 11; //11 for parallel multiplier, 34 for serial
parameter FRAC_WIDTH = 23;
parameter EXP_WIDTH = 8;
parameter ZERO_VECTOR = 31'd0;
parameter INF = 31'b1111111100000000000000000000000;
parameter QNAN = 31'b1111111110000000000000000000000;
parameter SNAN = 31'b1111111100000000000000000000001;
input clk;
input rst;
input [FP_WIDTH-1:0] opa_i;
input [FP_WIDTH-1:0] opb_i;
input [FRAC_WIDTH+4:0] fract_28_i;
input [EXP_WIDTH-1:0] exp_i;
input sign_i;
input fpu_op_i;
input [1:0] rmode_i;
output reg [FP_WIDTH-1:0] output_o;
output reg ine_o;
wire [FP_WIDTH-1:0] s_opa_i;
wire [FP_WIDTH-1:0] s_opb_i;
wire [FRAC_WIDTH+4:0] s_fract_28_i;
wire [EXP_WIDTH-1:0] s_exp_i;
wire s_sign_i;
wire s_fpu_op_i;
wire [1:0] s_rmode_i;
wire [FP_WIDTH-1:0] s_output_o;
wire s_ine_o;
wire s_overflow;
wire [5:0] s_zeros;
reg [5:0] s_shr1;
reg [5:0] s_shl1;
wire s_shr2, s_carry;
wire [9:0] s_exp10;
reg [EXP_WIDTH:0] s_expo9_1;
wire [EXP_WIDTH:0] s_expo9_2;
wire [EXP_WIDTH:0] s_expo9_3;
reg [FRAC_WIDTH+4:0] s_fracto28_1;
wire [FRAC_WIDTH+4:0] s_fracto28_2;
wire [FRAC_WIDTH+4:0] s_fracto28_rnd;
wire s_roundup;
wire s_sticky;
wire s_zero_fract;
wire s_lost;
wire s_infa, s_infb;
wire s_nan_in, s_nan_op, s_nan_a, s_nan_b, s_nan_sign;
assign s_opa_i = opa_i;
assign s_opb_i = opb_i;
assign s_fract_28_i = fract_28_i;
assign s_exp_i = exp_i;
assign s_sign_i = sign_i;
assign s_fpu_op_i = fpu_op_i;
assign s_rmode_i = rmode_i;
// Output Register
always @(posedge clk or posedge rst)
if (rst)
begin
output_o <= 'd0;
ine_o <= 1'b0;
end
else
begin
output_o <= s_output_o;
ine_o <= s_ine_o;
end
//*** Stage 1 ****
// figure out the output exponent and how much the fraction has to be
// shiftd right/left
assign s_carry = s_fract_28_i[27];
reg [5:0] lzeroes;
always @(s_fract_28_i)
casez(s_fract_28_i[26:0]) // synopsys full_case parallel_case
27'b1??????????????????????????: lzeroes = 0;
27'b01?????????????????????????: lzeroes = 1;
27'b001????????????????????????: lzeroes = 2;
27'b0001???????????????????????: lzeroes = 3;
27'b00001??????????????????????: lzeroes = 4;
27'b000001?????????????????????: lzeroes = 5;
27'b0000001????????????????????: lzeroes = 6;
27'b00000001???????????????????: lzeroes = 7;
27'b000000001??????????????????: lzeroes = 8;
27'b0000000001?????????????????: lzeroes = 9;
27'b00000000001????????????????: lzeroes = 10;
27'b000000000001???????????????: lzeroes = 11;
27'b0000000000001??????????????: lzeroes = 12;
27'b00000000000001?????????????: lzeroes = 13;
27'b000000000000001????????????: lzeroes = 14;
27'b0000000000000001???????????: lzeroes = 15;
27'b00000000000000001??????????: lzeroes = 16;
27'b000000000000000001?????????: lzeroes = 17;
27'b0000000000000000001????????: lzeroes = 18;
27'b00000000000000000001???????: lzeroes = 19;
27'b000000000000000000001??????: lzeroes = 20;
27'b0000000000000000000001?????: lzeroes = 21;
27'b00000000000000000000001????: lzeroes = 22;
27'b000000000000000000000001???: lzeroes = 23;
27'b0000000000000000000000001??: lzeroes = 24;
27'b00000000000000000000000001?: lzeroes = 25;
27'b000000000000000000000000001: lzeroes = 26;
27'b000000000000000000000000000: lzeroes = 27;
endcase
assign s_zeros = s_fract_28_i[27] ? 6'd0 : lzeroes;
// negative flag & large flag & exp
assign s_exp10 = {2'd0,s_exp_i} + {9'd0,s_carry} - {4'd0,s_zeros};
always @(posedge clk or posedge rst)
if (rst)
begin
s_shr1 <= 0;
s_shl1 <= 0;
s_expo9_1 <= 'd0;
end
else
begin
if (s_exp10[9] | !(|s_exp10))
begin
s_shr1 <= 0;
s_expo9_1 <= 9'd1;
if (|s_exp_i)
s_shl1 <= s_exp_i[5:0] - 6'd1;
else
s_shl1 <= 0;
end
else if (s_exp10[8])
begin
s_shr1 <= 0;
s_shl1 <= 0;
s_expo9_1 <= 9'b011111111;
end
else
begin
s_shr1 <= {5'd0,s_carry};
s_shl1 <= s_zeros;
s_expo9_1 <= s_exp10[8:0];
end // else: !if(s_exp10[8])
end // always @ (posedge clk or posedge rst)
//-
// *** Stage 2 ***
// Shifting the fraction and rounding
always @(posedge clk or posedge rst)
if (rst)
s_fracto28_1 <= 'd0;
else
if (|s_shr1)
s_fracto28_1 <= s_fract_28_i >> s_shr1;
else
s_fracto28_1 <= s_fract_28_i << s_shl1;
assign s_expo9_2 = (s_fracto28_1[27:26]==2'b00) ?
s_expo9_1 - 9'd1 : s_expo9_1;
// round
//check last bit, before and after right-shift
assign s_sticky = s_fracto28_1[0] | (s_fract_28_i[0] & s_fract_28_i[27]);
assign s_roundup = s_rmode_i==2'b00 ?
// round to nearset even
s_fracto28_1[2] & ((s_fracto28_1[1] | s_sticky) |
s_fracto28_1[3]) :
s_rmode_i==2'b10 ?
// round up
(s_fracto28_1[2] | s_fracto28_1[1] | s_sticky) & !s_sign_i:
s_rmode_i==2'b11 ?
// round down
(s_fracto28_1[2] | s_fracto28_1[1] | s_sticky) & s_sign_i :
// round to zero(truncate = no rounding)
1'b0;
assign s_fracto28_rnd = s_roundup ?
s_fracto28_1+28'b0000_0000_0000_0000_0000_0000_1000 :
s_fracto28_1;
// ***Stage 3***
// right-shift after rounding (if necessary)
assign s_shr2 = s_fracto28_rnd[27];
assign s_expo9_3 = (s_shr2 & s_expo9_2!=9'b011111111) ?
s_expo9_2 + 9'b000000001 : s_expo9_2;
assign s_fracto28_2 = s_shr2 ? {1'b0,s_fracto28_rnd[27:1]} : s_fracto28_rnd;
////-
assign s_infa = &s_opa_i[30:23];
assign s_infb = &s_opb_i[30:23];
assign s_nan_a = s_infa & (|s_opa_i[22:0]);
assign s_nan_b = s_infb & (|s_opb_i[22:0]);
assign s_nan_in = s_nan_a | s_nan_b;
// inf-inf=Nan
assign s_nan_op = (s_infa & s_infb) &
(s_opa_i[31] ^ (s_fpu_op_i ^ s_opb_i[31]));
assign s_nan_sign = (s_nan_a & s_nan_b) ? s_sign_i :
s_nan_a ?
s_opa_i[31] : s_opb_i[31];
// check if result is inexact;
assign s_lost = (s_shr1[0] & s_fract_28_i[0]) |
(s_shr2 & s_fracto28_rnd[0]) | (|s_fracto28_2[2:0]);
assign s_ine_o = (s_lost | s_overflow) & !(s_infa | s_infb);
assign s_overflow = s_expo9_3==9'b011111111 & !(s_infa | s_infb);
// '1' if fraction result is zero
assign s_zero_fract = s_zeros==27 & !s_fract_28_i[27];
// Generate result
assign s_output_o = (s_nan_in | s_nan_op) ?
{s_nan_sign,QNAN} :
(s_infa | s_infb) | s_overflow ?
{s_sign_i,INF} :
s_zero_fract ?
{s_sign_i,ZERO_VECTOR} :
{s_sign_i,s_expo9_3[7:0],s_fracto28_2[25:3]};
endmodule // fpu_post_norm_addsub
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2016 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
//
// Special cases of "string parameters" :
// This table compares obtain results from big-3 simulators to Verilator
// expected behavior. Base specified integer literals are also included as
// string detection may impact results for such cases.
//
// | Option/Param file | simulator 1 | simulator 2 | simulator 3 | verilator |
// |---------------------|-------------|-------------|-------------|-------------|
// | -gC0='"AB CD"' | AB CD | UNSUPPORTED | AB CD | AB CD |
// | -gC1=\"AB\ CD\" | AB CD | UNSUPPORTED | UNSUPPORTED | AB CD |
// | -gC2="\"AB CD\"" | AB CD | AB CD | AB CD | AB CD |
// | -gC3="\"AB\ CD\"" | AB CD | AB\\ CD | AB CD | AB CD |
// | -gC4=32'h600D600D | UNSUPPORTED | 32'h600D600D| 32'h600D600D| 32'h600D600D|
// | -gC5=32\'h600D600D | 32'h600D600D| UNSUPPORTED | UNSUPPORTED | 32'h600D600D|
// | -gC6="32'h600D600D" | 32'h600D600D| 32'h600D600D| UNSUPPORTED | 32'h600D600D|
// | -gC7='AB CD' | AB CD | UNSUPPORTED | UNSUPPORTED | UNSUPPORTED |
`define check(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: Wrong parameter value", `__FILE__,`__LINE__); $stop; end while(0);
module t;
parameter string1 = "Original String";
parameter string2 = "Original String";
parameter string11 = "Original String";
parameter string12 = "Original String";
parameter string21 = "Original String";
parameter string22 = "Original String";
parameter real11 = 0.1;
parameter real12 = 0.1;
parameter real21 = 0.1;
parameter real22 = 0.1;
parameter real31 = 0.1;
parameter real32 = 0.1;
parameter real41 = 0.1;
parameter real42 = 0.1;
parameter real51 = 0.1;
parameter real52 = 0.1;
parameter int11 = 1;
parameter int12 = 1;
parameter int21 = 1;
parameter int22 = 1;
parameter int31 = 1;
parameter int32 = 1;
parameter int41 = 1;
parameter int42 = 1;
parameter int51 = 1;
parameter int52 = 1;
parameter int61 = 1;
parameter int62 = 1;
parameter int71 = 1;
parameter int72 = 1;
initial begin
`check(string1,"New String");
`check(string2,"New String");
`check(string11,"New String");
`check(string12,"New String");
`check(string21,"New String");
`check(string22,"New String");
`check(real11,0.2);
`check(real12,0.2);
`check(real21,400);
`check(real22,400);
`check(real31,20);
`check(real32,20);
`check(real41,582.5);
`check(real42,582.5);
`check(real51,145.5);
`check(real52,145.5);
`check(int11,16);
`check(int12,16);
`check(int21,16);
`check(int22,16);
`check(int31,123);
`check(int32,123);
`check(int41,32'hdeadbeef);
`check(int42,32'hdeadbeef);
`check(int51,32'hdeadbeef);
`check(int52,32'hdeadbeef);
`check(int61,32'hdeadbeef);
`check(int62,32'hdeadbeef);
`check(int71,-1000);
`check(int72,-1000);
// Check parameter assigned simple integer literal is signed
if ((int11 << 27) >>> 31 != -1) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O2BB2A_FUNCTIONAL_V
`define SKY130_FD_SC_LS__O2BB2A_FUNCTIONAL_V
/**
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
*
* X = (!(A1 & A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__o2bb2a (
X ,
A1_N,
A2_N,
B1 ,
B2
);
// Module ports
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Local signals
wire nand0_out ;
wire or0_out ;
wire and0_out_X;
// Name Output Other arguments
nand nand0 (nand0_out , A2_N, A1_N );
or or0 (or0_out , B2, B1 );
and and0 (and0_out_X, nand0_out, or0_out);
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O2BB2A_FUNCTIONAL_V |
//sata_phy_layer.v
/*
Distributed under the MIT license.
Copyright (c) 2011 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
`include "sata_defines.v"
module sata_phy_layer (
input rst, //reset
input clk,
input platform_ready, //the underlying physical platform is
output linkup, //link is finished
output [31:0] tx_dout,
output tx_isk,
output tx_comm_reset,
output tx_comm_wake,
output tx_elec_idle,
input [31:0] rx_din,
input [3:0] rx_isk,
input rx_elec_idle,
input rx_byte_is_aligned,
input comm_init_detect,
input comm_wake_detect,
output phy_ready,
output [3:0] lax_state
);
//Parameters
parameter NOT_READY = 4'h0;
parameter SEND_FIRST_ALIGN = 4'h1;
parameter SEND_SECOND_ALIGN = 4'h2;
parameter READY = 4'h3;
//Registers/Wires
reg [3:0] state;
reg [7:0] align_count;
//OOB Control
wire [31:0] oob_tx_dout;
wire oob_tx_isk;
//Phy Control
wire [31:0] phy_tx_dout;
wire phy_tx_isk;
wire align_detected;
//Submodules
oob_controller oob (
.rst (rst),
.clk (clk),
//OOB controller
.platform_ready (platform_ready),
.linkup (linkup),
//Platform Control
.tx_dout (oob_tx_dout),
.tx_isk (oob_tx_isk),
.tx_comm_reset (tx_comm_reset),
.tx_comm_wake (tx_comm_wake),
.tx_set_elec_idle (tx_elec_idle),
.rx_din (rx_din),
.rx_isk (rx_isk),
.comm_init_detect (comm_init_detect),
.comm_wake_detect (comm_wake_detect),
.rx_byte_is_aligned (rx_byte_is_aligned),
.rx_is_elec_idle (rx_elec_idle),
.lax_state (lax_state)
);
//Asynchronous Logic
assign tx_dout = !linkup ? oob_tx_dout : phy_tx_dout;
assign tx_isk = !linkup ? oob_tx_isk : phy_tx_isk;
assign phy_tx_dout = `PRIM_ALIGN;
assign phy_tx_isk = 1;
assign align_detected = ((rx_isk > 0) && (rx_din == `PRIM_ALIGN) && rx_byte_is_aligned);
//assign phy_ready = ((state == READY) && (!align_detected));
assign phy_ready = (state == READY);
//Synchronous Logic
always @ (posedge clk) begin
if (rst) begin
state <= NOT_READY;
align_count <= 0;
end
else begin
if (state == READY) begin
align_count <= align_count + 1;
end
case (state)
NOT_READY: begin
align_count <= 0;
if (linkup) begin
$display ("sata_phy_layer: linkup! send aligns");
state <= SEND_FIRST_ALIGN;
end
end
SEND_FIRST_ALIGN: begin
state <= SEND_SECOND_ALIGN;
end
SEND_SECOND_ALIGN: begin
state <= READY;
end
READY: begin
if (align_count == 255) begin
state <= SEND_FIRST_ALIGN;
$display ("sata_phy_layer: linkup! send alignment dwords");
//Send an align primitive
end
end
default: begin
end
endcase
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DLATCH_PSA_PP_PKG_SN_BLACKBOX_V
`define SKY130_FD_SC_HS__UDP_DLATCH_PSA_PP_PKG_SN_BLACKBOX_V
/**
* udp_dlatch$PSa_pp$PKG$sN: Positive level sensitive D-type -latch
* with active low
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__udp_dlatch$PSa_pp$PKG$sN (
Q ,
D ,
GATE ,
SET_ASYNC ,
SLEEP_B ,
NOTIFIER_REG,
KAPWR ,
VGND ,
VPWR
);
output Q ;
input D ;
input GATE ;
input SET_ASYNC ;
input SLEEP_B ;
input NOTIFIER_REG;
input KAPWR ;
input VGND ;
input VPWR ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DLATCH_PSA_PP_PKG_SN_BLACKBOX_V
|
module regs_testbench();
// faz o include dos parameters das instrucoes
`include "params_proc.v"
// indica o numero de testes a serem feitos
parameter N_TESTES = 11;
// contador de testes a serem feitos
integer testes;
// declaracao input / output
reg clk, en_write;
reg [REG_ADDR_WIDTH-1:0] addr_write, addr_read1, addr_read2;
reg signed [DATA_WIDTH-1:0] data_write;
wire signed [DATA_WIDTH-1:0] data_read1, data_read2;
// criacao das instancias
regs regs0(
.clk(clk),
.en_write(en_write),
.data_write(data_write),
.addr_write(addr_write),
.addr_read1(addr_read1),
.addr_read2(addr_read2),
.data_read1(data_read1),
.data_read2(data_read2));
// inicializando testes em 0
initial begin
testes <= 0;
// inicilizacao dos inputs
clk <= 0;
end
// gerando clock
always begin
// gere o clock quando os sinais de teste estiverem estabilizados
#2;
clk = !clk;
end
// gerandos os testes aqui
always begin
#4;
testes = testes+1;
// DESCREVA OS CASOS DE TESTE ABAIXO
case(testes)
1: begin
en_write = 1;
addr_write = 0;
data_write = 5;
addr_read1 = 0;
addr_read2 = 0;
end
2: begin
en_write = 0;
addr_write = 7;
data_write = 65;
addr_read1 = 0;
addr_read2 = 1;
end
3: begin
en_write = 1;
addr_write = 8;
data_write = 11;
addr_read1 = 0;
addr_read2 = 1;
end
4: begin
en_write = 0;
addr_write = 7;
data_write = 18;
addr_read1 = 8;
addr_read2 = 1;
end
5: begin
en_write = 1;
addr_write = 1;
data_write = 16;
addr_read1 = 0;
addr_read2 = 1;
end
6: begin
en_write = 1;
addr_write = 2;
data_write = 24;
addr_read1 = 0;
addr_read2 = 1;
end
7: begin
en_write = 0;
addr_write = 2;
data_write = 29;
addr_read1 = 1;
addr_read2 = 2;
end
8: begin
en_write = 1;
addr_write = 15;
data_write = 20;
addr_read1 = 1;
addr_read2 = 2;
end
9: begin
en_write = 0;
addr_write = 21;
data_write = 25400;
addr_read1 = 15;
addr_read2 = 0;
end
10: begin
en_write = 1;
addr_write = 31;
data_write = 2000;
addr_read1 = 15;
addr_read2 = 0;
end
11: begin
en_write = 0;
addr_write = 20;
data_write = 200;
addr_read1 = 31;
addr_read2 = 0;
end
default: begin
// nao faca nada de proposito
end
endcase
end
// mostre os resultados dos testes
always @(posedge clk) begin
if (testes > 0 && testes <= N_TESTES) begin
// aqui aparecem os resultados das entradas
$display(" Teste # %2d => ", testes);
$display("\t WRITE - EN: %b - ADDR: %3d - DATA: %6d ", en_write, addr_write, data_write);
$display("\t READ_1\n\t ADDR: %3d ", addr_read1);
$display("\t DATA: %6d ", data_read1);
$display("\t READ_2\n\t ADDR: %3d ", addr_read2);
$display("\t DATA: %6d ", data_read2);
$display(" ");
end
end
endmodule |
//////////////////////////////////////////////////////////////////////////////////
// InterChannelELPBuffer.v for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Jinwoo Jeong <[email protected]>
// Ilyong Jung <[email protected]>
// Yong Ho Song <[email protected]>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Jinwoo Jeong <[email protected]>
// Ilyong Jung <[email protected]>
//
// Project Name: Cosmos OpenSSD
// Design Name: BCH Page Decoder
// Module Name: InterChannelELPBuffer
// File Name: InterChannelELPBuffer.v
//
// Version: v1.0.0
//
// Description: Error location polynomial (ELP) coefficient buffer array
//
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module InterChannelELPBuffer
#(
parameter Channel = 4,
parameter Multi = 2,
parameter MaxErrorCountBits = 9,
parameter GaloisFieldDegree = 12,
parameter ELPCoefficients = 15
)
(
iClock ,
iReset ,
iChannelSel ,
iKESEnd ,
iKESFail ,
iClusterCorrectionEnd ,
iCorrectedChunkNumber ,
iChunkErrorCount ,
oBufferReady ,
iELPCoefficient000 ,
iELPCoefficient001 ,
iELPCoefficient002 ,
iELPCoefficient003 ,
iELPCoefficient004 ,
iELPCoefficient005 ,
iELPCoefficient006 ,
iELPCoefficient007 ,
iELPCoefficient008 ,
iELPCoefficient009 ,
iELPCoefficient010 ,
iELPCoefficient011 ,
iELPCoefficient012 ,
iELPCoefficient013 ,
iELPCoefficient014 ,
iCSAvailable ,
oIntraSharedKESEnd ,
oErroredChunk ,
oCorrectionFail ,
oClusterErrorCount ,
oELPCoefficients
);
input iClock ;
input iReset ;
input [3:0] iChannelSel ;
input iKESEnd ;
input iKESFail ;
input iClusterCorrectionEnd ;
input iCorrectedChunkNumber ;
input [3:0] iChunkErrorCount ;
output oBufferReady ;
input [GaloisFieldDegree - 1:0] iELPCoefficient000 ;
input [GaloisFieldDegree - 1:0] iELPCoefficient001 ;
input [GaloisFieldDegree - 1:0] iELPCoefficient002 ;
input [GaloisFieldDegree - 1:0] iELPCoefficient003 ;
input [GaloisFieldDegree - 1:0] iELPCoefficient004 ;
input [GaloisFieldDegree - 1:0] iELPCoefficient005 ;
input [GaloisFieldDegree - 1:0] iELPCoefficient006 ;
input [GaloisFieldDegree - 1:0] iELPCoefficient007 ;
input [GaloisFieldDegree - 1:0] iELPCoefficient008 ;
input [GaloisFieldDegree - 1:0] iELPCoefficient009 ;
input [GaloisFieldDegree - 1:0] iELPCoefficient010 ;
input [GaloisFieldDegree - 1:0] iELPCoefficient011 ;
input [GaloisFieldDegree - 1:0] iELPCoefficient012 ;
input [GaloisFieldDegree - 1:0] iELPCoefficient013 ;
input [GaloisFieldDegree - 1:0] iELPCoefficient014 ;
input [Channel - 1:0] iCSAvailable ;
output [Channel - 1:0] oIntraSharedKESEnd ;
output [Channel*Multi - 1:0] oErroredChunk ;
output [Channel*Multi - 1:0] oCorrectionFail ;
output [Channel*Multi*MaxErrorCountBits - 1:0] oClusterErrorCount ;
output [Channel*Multi*GaloisFieldDegree*ELPCoefficients - 1:0] oELPCoefficients ;
reg rChannelSel ;
wire [Channel - 1:0] wKESEnd ;
wire [Channel - 1:0] wBufferReady ;
assign wKESEnd = (iKESEnd) ? iChannelSel : 0;
genvar c;
generate
for (c = 0; c < Channel; c = c + 1)
d_KES_CS_buffer
#(
.Multi(2),
.GaloisFieldDegree(12),
.MaxErrorCountBits(9),
.ELPCoefficients(15)
)
Inst_PageDecoderCSBuffer
(
.i_clk (iClock ),
.i_RESET (iReset ),
.i_stop_dec (1'b0 ),
.i_exe_buf (wKESEnd[c] ),
.i_kes_fail (iKESFail ),
.i_buf_sequence_end (iClusterCorrectionEnd ),
.i_chunk_number (iCorrectedChunkNumber ),
.i_error_count (iChunkErrorCount ),
.i_v_000 (iELPCoefficient000 ),
.i_v_001 (iELPCoefficient001 ),
.i_v_002 (iELPCoefficient002 ),
.i_v_003 (iELPCoefficient003 ),
.i_v_004 (iELPCoefficient004 ),
.i_v_005 (iELPCoefficient005 ),
.i_v_006 (iELPCoefficient006 ),
.i_v_007 (iELPCoefficient007 ),
.i_v_008 (iELPCoefficient008 ),
.i_v_009 (iELPCoefficient009 ),
.i_v_010 (iELPCoefficient010 ),
.i_v_011 (iELPCoefficient011 ),
.i_v_012 (iELPCoefficient012 ),
.i_v_013 (iELPCoefficient013 ),
.i_v_014 (iELPCoefficient014 ),
.i_cs_available (iCSAvailable[c] ),
.o_buf_available (wBufferReady[c] ),
.o_exe_cs (oIntraSharedKESEnd[c] ),
.o_kes_sequence_end (oErroredChunk[(c+1)*Multi - 1: c*Multi] ),
.o_kes_fail (oCorrectionFail[(c+1)*Multi - 1: c*Multi] ),
.o_error_count (oClusterErrorCount[(c+1)*Multi*MaxErrorCountBits - 1: c*Multi*MaxErrorCountBits] ),
.o_ELP_coef (oELPCoefficients[(c+1)*Multi*GaloisFieldDegree*ELPCoefficients - 1: c*Multi*GaloisFieldDegree*ELPCoefficients] )
);
endgenerate
assign oBufferReady = (iChannelSel == 4'b0001) ? wBufferReady[0] :
(iChannelSel == 4'b0010) ? wBufferReady[1] :
(iChannelSel == 4'b0100) ? wBufferReady[2] :
(iChannelSel == 4'b1000) ? wBufferReady[3] : 1'b0;
endmodule |
/* Simple button module */
module button (
// input clock
clk,
// I/O pins
pin_in,
press,
);
input clk;
input pin_in;
output press;
/* Pull-up settings for input:
PIN_TYPE: <output_type=0>_<input=1>
PULLUP: <enable=1>
PACKAGE_PIN: <user pad name>
D_IN_0: <internal pin wire (data in)>
*/
wire pin_din;
SB_IO #(
.PIN_TYPE(6'b0000_01),
.PULLUP(1'b1)
) pin_in_config (
.PACKAGE_PIN(pin_in),
.D_IN_0(pin_din)
);
/* Debouncing timer and period = 10 ms */
reg [31:0] debounce_timer = 32'b0;
parameter DEBOUNCE_PERIOD = 32'd120000;
reg debouncing = 1'b0;
reg buttonpress = 1'b0;
assign press = buttonpress;
/* Our high speed clock will deal with debounce timing */
always @ (posedge clk) begin
// check for button presses
if (~debouncing && ~pin_din) begin
buttonpress <= 1;
debouncing <= 1;
// reset debouncing if button is held low
end else if (debouncing && ~pin_din) begin
debounce_timer <= 32'b0;
// or if it's high, increment debounce timer
end else if (debouncing && debounce_timer < DEBOUNCE_PERIOD) begin
debounce_timer <= debounce_timer + 1;
// finally, if it's high and timer expired, debouncing done!
end else if (debouncing) begin
debounce_timer <= 32'b0;
debouncing <= 1'b0;
buttonpress <= 0;
end
end
endmodule |
/*
Legal Notice: (C)2009 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details.
*/
/*
Author: JCJB
Date: 08/13/2010
Version 2.5
This write master module is responsible for taking in streaming data and
writing the contents out to memory. It is controlled by a streaming
sink port called the 'command port'. Any information that must be communicated
back to a host such as an error in transfer is made available by the
streaming source port called the 'response port'.
There are various parameters to control the synthesis of this hardware
either for functionality changes or speed/resource optimizations. Some
of the parameters will be hidden in the component GUI since they are derived
from some other parameters. When this master module is used in a MM to MM
transfer disable the packet support since the packet hardware is not needed.
In order to increase the Fmax you should enable only full accesses so that
the unaligned access and byte enable blocks can be reduced to wires. Also
only configure the length width to be as wide as you need as it will typically
be the critical path of this module.
Revision History:
1.0 Initial version which used a simple exported hand shake control scheme.
2.0 Added support for unaligned accesses, stride, and streaming.
2.1 Fixed control logic and removed the early termination enable logic (it's
always on now so for packet transfers make sure the length register is
programmed accordingly.
2.2 Added burst support.
2.3 Added additional conditional code for 8-bit case to avoid synthesis issues.
2.4 Corrected burst bug that prevented full bursts from being presented to the
fabric. Corrected the stop/reset logic to ensure masters can be stopped
or reset while idle.
2.5 Corrected a packet problem where EOP wasn't qualified by ready and valid.
Added 64-bit addressing.
*/
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module write_master (
clk,
reset,
// descriptor commands sink port
snk_command_data,
snk_command_valid,
snk_command_ready,
// response source port
src_response_data,
src_response_valid,
src_response_ready,
// data path sink port
snk_data,
snk_valid,
snk_ready,
snk_sop,
snk_eop,
snk_empty,
snk_error,
// data path master port
master_address,
master_write,
master_byteenable,
master_writedata,
master_waitrequest,
master_burstcount
);
parameter UNALIGNED_ACCESSES_ENABLE = 0; // when enabled allows transfers to begin from off word boundaries
parameter ONLY_FULL_ACCESS_ENABLE = 0; // when enabled allows transfers to end with partial access, master achieve a much higher fmax when this is enabled
parameter STRIDE_ENABLE = 0; // stride support can only be enabled when unaligned accesses is disabled
parameter STRIDE_WIDTH = 1; // when stride support is enabled this value controls the rate in which the address increases (in words), the stride width + log2(byte enable width) + 1 cannot exceed address width
parameter PACKET_ENABLE = 0;
parameter ERROR_ENABLE = 0;
parameter ERROR_WIDTH = 8; // must be between 1-8, this will only be enabled in the GUI when error enable is turned on
parameter DATA_WIDTH = 32;
parameter BYTE_ENABLE_WIDTH = 4; // set by the .tcl file (hidden in GUI)
parameter BYTE_ENABLE_WIDTH_LOG2 = 2; // set by the .tcl file (hidden in GUI)
parameter ADDRESS_WIDTH = 32; // set in the .tcl file (hidden in GUI) by the address span of the master
parameter LENGTH_WIDTH = 32; // GUI setting with warning if ADDRESS_WIDTH < LENGTH_WIDTH (waste of logic for the length counter)
parameter ACTUAL_BYTES_TRANSFERRED_WIDTH = 32; // GUI setting which can only be set when packet support is enabled (otherwise it'll be set to 32). A warning will be issued if overrun protection is enabled and this setting is less than the length width.
parameter FIFO_DEPTH = 32;
parameter FIFO_DEPTH_LOG2 = 5; // set by the .tcl file (hidden in GUI)
parameter FIFO_SPEED_OPTIMIZATION = 1; // set by the .tcl file (hidden in GUI) The default will be on since it only impacts the latency of the entire transfer by 1 clock cycle and adds very little additional logic.
parameter SYMBOL_WIDTH = 8; // set by the .tcl file (hidden in GUI)
parameter NUMBER_OF_SYMBOLS = 4; // set by the .tcl file (hidden in GUI)
parameter NUMBER_OF_SYMBOLS_LOG2 = 2; // set by the .tcl file (hidden in GUI)
parameter BURST_ENABLE = 0;
parameter MAX_BURST_COUNT = 2; // must be a power of 2, when BURST_ENABLE = 0 set the maximum burst count to 1 (automatically done in the .tcl file)
parameter MAX_BURST_COUNT_WIDTH = 2; // set by the .tcl file (hidden in GUI) = log2(MAX_BURST_COUNT) + 1
parameter PROGRAMMABLE_BURST_ENABLE = 0; // when enabled the user must set the burst count, if 0 is set then the value MAX_BURST_COUNT will be used instead
parameter BURST_WRAPPING_SUPPORT = 1; // will only be used when bursting is enabled. This cannot be enabled with programmable burst capabilities. Enabling it will make sure the master gets back into burst alignment (data width in bytes * maximum burst count alignment)
localparam FIFO_USE_MEMORY = 1; // set to 0 to use LEs instead, not exposed since FPGAs have a lot of memory these days
localparam BIG_ENDIAN_ACCESS = 0; // hiding this since it can blow your foot off if you are not careful and it's not tested. It's big endian with respect to the write master width and not necessarily to the width of the data type used by a host CPU.
// handy mask for seperating the word address from the byte address bits, so for 32 bit masters this mask is 0x3, for 64 bit masters it'll be 0x7
localparam LSB_MASK = {BYTE_ENABLE_WIDTH_LOG2{1'b1}};
//need to buffer the empty, eop, sop, and error bits. If these are not needed then the logic will be synthesized away
localparam FIFO_WIDTH = (DATA_WIDTH + 2 + NUMBER_OF_SYMBOLS_LOG2 + ERROR_WIDTH); // data, sop, eop, empty, and error bits
localparam ADDRESS_INCREMENT_WIDTH = (BYTE_ENABLE_WIDTH_LOG2 + MAX_BURST_COUNT_WIDTH + STRIDE_WIDTH);
localparam FIXED_STRIDE = 1'b1; // when stride isn't supported this will be the stride value used (i.e. sequential incrementing of the address)
input clk;
input reset;
// descriptor commands sink port
input [255:0] snk_command_data;
input snk_command_valid;
output reg snk_command_ready;
// response source port
output wire [255:0] src_response_data;
output reg src_response_valid;
input src_response_ready;
// data path sink port
input [DATA_WIDTH-1:0] snk_data;
input snk_valid;
output wire snk_ready;
input snk_sop;
input snk_eop;
input [NUMBER_OF_SYMBOLS_LOG2-1:0] snk_empty;
input [ERROR_WIDTH-1:0] snk_error;
// master inputs and outputs
input master_waitrequest;
output wire [ADDRESS_WIDTH-1:0] master_address;
output wire master_write;
output wire [BYTE_ENABLE_WIDTH-1:0] master_byteenable;
output wire [DATA_WIDTH-1:0] master_writedata;
output wire [MAX_BURST_COUNT_WIDTH-1:0] master_burstcount;
// internal wires and registers
wire [63:0] descriptor_address;
wire [31:0] descriptor_length;
wire [15:0] descriptor_stride;
wire descriptor_end_on_eop_enable;
wire [7:0] descriptor_programmable_burst_count;
reg [ADDRESS_WIDTH-1:0] address_counter;
wire [ADDRESS_WIDTH-1:0] address; // unfiltered version of master_address
wire write; // unfiltered version of master_write
reg [LENGTH_WIDTH-1:0] length_counter;
reg [STRIDE_WIDTH-1:0] stride_d1;
wire [STRIDE_WIDTH-1:0] stride_amount; // either set to be stride_d1 or hardcoded to 1 depending on the parameterization
reg descriptor_end_on_eop_enable_d1;
reg [MAX_BURST_COUNT_WIDTH-1:0] programmable_burst_count_d1;
wire [MAX_BURST_COUNT_WIDTH-1:0] maximum_burst_count;
reg [BYTE_ENABLE_WIDTH_LOG2-1:0] start_byte_address; // used to determine how far out of alignement the master started
reg first_access; // used to prevent extra writes when the unaligned access starts and ends during the same write
wire first_word_boundary_not_reached; // set when the first access doesn't reach the next word boundary
reg first_word_boundary_not_reached_d1;
wire increment_address; // enable the address incrementing
wire [ADDRESS_INCREMENT_WIDTH-1:0] address_increment; // amount of bytes to increment the address
wire [ADDRESS_INCREMENT_WIDTH-1:0] bytes_to_transfer;
wire short_first_access_enable; // when starting unaligned and the amount of data to transfer reaches the next word boundary
wire short_last_access_enable; // when address is aligned (can be an unaligned buffer transfer) but the amount of data doesn't reach the next word boundary
wire short_first_and_last_access_enable; // when starting unaligned and the amount of data to transfer doesn't reach the next word boundary
wire [ADDRESS_INCREMENT_WIDTH-1:0] short_first_access_size;
wire [ADDRESS_INCREMENT_WIDTH-1:0] short_last_access_size;
wire [ADDRESS_INCREMENT_WIDTH-1:0] short_first_and_last_access_size;
reg [ADDRESS_INCREMENT_WIDTH-1:0] bytes_to_transfer_mux;
wire [FIFO_WIDTH-1:0] fifo_write_data;
wire [FIFO_WIDTH-1:0] fifo_read_data;
wire [FIFO_DEPTH_LOG2-1:0] fifo_used;
wire fifo_write;
wire fifo_read;
wire fifo_empty;
wire fifo_full;
wire [DATA_WIDTH-1:0] fifo_read_data_rearranged; // if big endian support is enabled then this signal has the FIFO output byte lanes reversed
wire go;
wire done;
reg done_d1;
wire done_strobe;
wire [DATA_WIDTH-1:0] buffered_data;
wire [NUMBER_OF_SYMBOLS_LOG2-1:0] buffered_empty;
wire buffered_eop;
wire buffered_sop; // not wired to anything so synthesized away, included for debug purposes
wire [ERROR_WIDTH-1:0] buffered_error;
wire length_sync_reset; // syncronous reset for the length counter for eop support
reg [ACTUAL_BYTES_TRANSFERRED_WIDTH-1:0] actual_bytes_transferred_counter; // width will be in the range of 1-32
wire [31:0] response_actual_bytes_transferred;
wire early_termination;
reg early_termination_d1;
wire eop_enable;
reg [ERROR_WIDTH-1:0] error; // SRFF so that we don't loose any errors if EOP doesn't arrive right away
wire [7:0] response_error; // need to pad upper error bits with zeros if they are not present at the data streaming port
wire sw_stop_in;
wire sw_reset_in;
reg stopped; // SRFF to make sure we don't attempt to stop in the middle of a transfer
reg reset_taken; // FF to make sure we don't attempt to reset the master in the middle of a transfer
wire reset_taken_from_write_burst_control; // in the middle of a burst greater than one, the burst control block will assert this signal after the burst copmletes, 'reset_taken' will use this signal
wire stopped_from_write_burst_control; // in the middle of a burst greater than one, the burst control block will assert this signal after the burst completes, 'stopped' will use this signal
wire stop_state;
wire reset_delayed;
wire write_complete; // handy signal for determining when a write has occured and completed
wire write_stall_from_byte_enable_generator; // partial word access occuring which might take multiple write cycles to complete (or waitrequest has been asserted)
wire write_stall_from_write_burst_control; // when there isn't enough data buffered to start a burst this signal will be asserted
wire [BYTE_ENABLE_WIDTH-1:0] byteenable_masks [0:BYTE_ENABLE_WIDTH-1]; // a bunch of masks that will be provided to unsupported_byteenable
wire [BYTE_ENABLE_WIDTH-1:0] unsupported_byteenable; // input into the byte enable generation block which will take the unsupported byte enable and chop it up into supported transfers
wire [BYTE_ENABLE_WIDTH-1:0] supported_byteenable; // output from the byte enable generation block
wire extra_write; // when asserted master_write will be asserted but the FIFO will not be popped since it will not contain any more data for the transfer
wire st_to_mm_adapter_enable;
wire [BYTE_ENABLE_WIDTH_LOG2:0] packet_beat_size; // number of bytes coming in from the data stream when packet support is enabled
wire [BYTE_ENABLE_WIDTH_LOG2:0] packet_bytes_buffered;
reg [BYTE_ENABLE_WIDTH_LOG2:0] packet_bytes_buffered_d1; // represents the number of bytes buffered in the ST to MM adapter (only applicable for unaligned accesses)
reg eop_seen; // when the beat containing EOP has been popped from the fifo this bit will be set, it will be reset when done is asserted. It is used to determine if an extra write must occur (unaligned accesses only)
/********************************************* REGISTERS ****************************************************************************************/
// registering the stride control bit
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
stride_d1 <= 0;
end
else if (go == 1)
begin
stride_d1 <= descriptor_stride[STRIDE_WIDTH-1:0];
end
end
// registering the end on eop bit (will be optimized away if packet support is disabled)
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
descriptor_end_on_eop_enable_d1 <= 1'b0;
end
else if (go == 1)
begin
descriptor_end_on_eop_enable_d1 <= descriptor_end_on_eop_enable;
end
end
// registering the programmable burst count (will be optimized away if this support is disabled)
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
programmable_burst_count_d1 <= 0;
end
else if (go == 1)
begin
programmable_burst_count_d1 <= (descriptor_programmable_burst_count == 0)? MAX_BURST_COUNT : descriptor_programmable_burst_count;
end
end
// master address increment counter
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
address_counter <= 0;
end
else
begin
if (go == 1)
begin
address_counter <= descriptor_address[ADDRESS_WIDTH-1:0];
end
else if (increment_address == 1)
begin
address_counter <= address_counter + address_increment;
end
end
end
// master byte address, used to determine how far out of alignment the master began transfering data
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
start_byte_address <= 0;
end
else if (go == 1)
begin
start_byte_address <= descriptor_address[BYTE_ENABLE_WIDTH_LOG2-1:0];
end
end
// first_access will be asserted only for the first write of a transaction, this will be used to filter 'extra_write' for unaligned accesses
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
first_access <= 0;
end
else
begin
if (go == 1)
begin
first_access <= 1;
end
else if ((first_access == 1) & (increment_address == 1))
begin
first_access <= 0;
end
end
end
// this register is used to determine if the first word boundary will be reached
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
first_word_boundary_not_reached_d1 <= 0;
end
else if (go == 1)
begin
first_word_boundary_not_reached_d1 <= first_word_boundary_not_reached;
end
end
// master length logic, this will typically be the critical path followed by the FIFO
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
length_counter <= 0;
end
else
begin
if (length_sync_reset == 1) // when packet support is enabled the length register might roll over so this sync reset will prevent that from happening (it's also used when a soft reset is triggered)
begin
length_counter <= 0; // when EOP arrives need to stop counting, length=0 is the done condition
end
else if (go == 1)
begin
length_counter <= descriptor_length[LENGTH_WIDTH-1:0];
end
else if (increment_address == 1)
begin
length_counter <= length_counter - bytes_to_transfer; // not using address_increment because stride might be enabled
end
end
end
// master actual bytes transferred logic, this will only be used when packet support is enabled, otherwise the value will be 0
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
actual_bytes_transferred_counter <= 0;
end
else
begin
if ((go == 1) | (reset_taken == 1))
begin
actual_bytes_transferred_counter <= 0;
end
else if(increment_address == 1)
begin
actual_bytes_transferred_counter <= actual_bytes_transferred_counter + bytes_to_transfer;
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
done_d1 <= 1; // out of reset the master needs to be 'done' so that the done_strobe doesn't fire
end
else
begin
done_d1 <= done;
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
early_termination_d1 <= 0;
end
else
begin
early_termination_d1 <= early_termination;
end
end
generate
genvar l;
for(l = 0; l < ERROR_WIDTH; l = l + 1)
begin: error_SRFF
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
error[l] <= 0;
end
else
begin
if ((go == 1) | (reset_taken == 1))
begin
error[l] <= 0;
end
else if ((buffered_error[l] == 1) & (done == 0))
begin
error[l] <= 1;
end
end
end
end
endgenerate
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
snk_command_ready <= 1; // have to start ready to take commands
end
else
begin
if (go == 1)
begin
snk_command_ready <= 0;
end
else if (((done == 1) & (src_response_valid == 0)) | (reset_taken == 1)) // need to make sure the response is popped before accepting more commands
begin
snk_command_ready <= 1;
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
src_response_valid <= 0;
end
else
begin
if (reset_taken == 1)
begin
src_response_valid <= 0;
end
else if (done_strobe == 1)
begin
src_response_valid <= 1; // will be set only once
end
else if ((src_response_valid == 1) & (src_response_ready == 1))
begin
src_response_valid <= 0; // will be reset only once when the dispatcher captures the data
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
stopped <= 0;
end
else
begin
if ((sw_stop_in == 0) | (reset_taken == 1))
begin
stopped <= 0;
end
else if ((sw_stop_in == 1) & (((write_complete == 1) & (stopped_from_write_burst_control == 1)) | ((snk_command_ready == 1) | (master_write == 0))))
begin
stopped <= 1;
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
reset_taken <= 0;
end
else
begin
reset_taken <= (sw_reset_in == 1) & (((write_complete == 1) & (reset_taken_from_write_burst_control == 1)) | ((snk_command_ready == 1) | (master_write == 0)));
end
end
// eop_seen will be set when the last beat of a packet transfer has been popped from the fifo for ST to MM block flushing purposes (extra write)
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
eop_seen <= 0;
end
else
begin
if (done == 1)
begin
eop_seen <= 0;
end
else if ((buffered_eop == 1) & (write_complete == 1))
begin
eop_seen <= 1;
end
end
end
// when unaligned accesses are enabled packet_bytes_buffered_d1 is the number of bytes buffered in the ST to MM block from the previous beat
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
packet_bytes_buffered_d1 <= 0;
end
else
begin
if (go == 1)
begin
packet_bytes_buffered_d1 <= 0;
end
else if (write_complete == 1)
begin
packet_bytes_buffered_d1 <= packet_bytes_buffered;
end
end
end
/********************************************* END REGISTERS ************************************************************************************/
/********************************************* MODULE INSTANTIATIONS ****************************************************************************/
/* buffered sop, eop, empty, error, data (in that order). sop, eop, and empty are only used when packet support is enabled,
likewise error is only used when error support is enabled */
scfifo the_st_to_master_fifo (
.aclr (reset),
.clock (clk),
.data (fifo_write_data),
.full (fifo_full),
.empty (fifo_empty),
.q (fifo_read_data),
.rdreq (fifo_read),
.usedw (fifo_used),
.wrreq (fifo_write)
);
defparam the_st_to_master_fifo.lpm_width = FIFO_WIDTH;
defparam the_st_to_master_fifo.lpm_widthu = FIFO_DEPTH_LOG2;
defparam the_st_to_master_fifo.lpm_numwords = FIFO_DEPTH;
defparam the_st_to_master_fifo.lpm_showahead = "ON"; // slower but doesn't require complex control logic to time with waitrequest
defparam the_st_to_master_fifo.use_eab = (FIFO_USE_MEMORY == 1)? "ON" : "OFF";
defparam the_st_to_master_fifo.add_ram_output_register = (FIFO_SPEED_OPTIMIZATION == 1)? "ON" : "OFF";
defparam the_st_to_master_fifo.underflow_checking = "OFF";
defparam the_st_to_master_fifo.overflow_checking = "OFF";
/* This module will barrelshift the data from the FIFO when unaligned accesses is enabled (we are using
part of the FIFO word when off boundary). When unaligned accesses is disabled then the data passes
as wires. The byte enable generator might require multiple cycles to perform partial accesses so a
'stall' bit is used (triggers a stall like waitrequest)
*/
ST_to_MM_Adapter the_ST_to_MM_Adapter (
.clk (clk),
.reset (reset),
.enable (st_to_mm_adapter_enable),
.address (descriptor_address[ADDRESS_WIDTH-1:0]),
.start (go),
.waitrequest (master_waitrequest),
.stall (write_stall_from_byte_enable_generator | write_stall_from_write_burst_control),
.write_data (master_writedata),
.fifo_data (buffered_data),
.fifo_empty (fifo_empty),
.fifo_readack (fifo_read)
);
defparam the_ST_to_MM_Adapter.DATA_WIDTH = DATA_WIDTH;
defparam the_ST_to_MM_Adapter.BYTEENABLE_WIDTH_LOG2 = BYTE_ENABLE_WIDTH_LOG2;
defparam the_ST_to_MM_Adapter.ADDRESS_WIDTH = ADDRESS_WIDTH;
defparam the_ST_to_MM_Adapter.UNALIGNED_ACCESS_ENABLE = UNALIGNED_ACCESSES_ENABLE;
/* this block is responsible for presenting the fabric with supported byte enable combinations which can
take multiple cycles, if full word only support is enabled this block will reduce to wires during synthesis */
byte_enable_generator the_byte_enable_generator (
.clk (clk),
.reset (reset),
.write_in (write),
.byteenable_in (unsupported_byteenable),
.waitrequest_out (write_stall_from_byte_enable_generator),
.byteenable_out (supported_byteenable),
.waitrequest_in (master_waitrequest | write_stall_from_write_burst_control)
);
defparam the_byte_enable_generator.BYTEENABLE_WIDTH = BYTE_ENABLE_WIDTH;
// this block will be used to drive write, address, and burstcount to the fabric
write_burst_control the_write_burst_control (
.clk (clk),
.reset (reset),
.sw_reset (sw_reset_in),
.sw_stop (sw_stop_in),
.length (length_counter),
.eop_enabled (descriptor_end_on_eop_enable_d1),
.eop (snk_eop),
.ready (snk_ready),
.valid (snk_valid),
.early_termination (early_termination),
.address_in (address),
.write_in (write),
.max_burst_count (maximum_burst_count),
.write_fifo_used ({fifo_full,fifo_used}),
.waitrequest (master_waitrequest),
.short_first_access_enable (short_first_access_enable),
.short_last_access_enable (short_last_access_enable),
.short_first_and_last_access_enable (short_first_and_last_access_enable),
.address_out (master_address),
.write_out (master_write), // filtered version of 'write'
.burst_count (master_burstcount),
.stall (write_stall_from_write_burst_control),
.reset_taken (reset_taken_from_write_burst_control),
.stopped (stopped_from_write_burst_control)
);
defparam the_write_burst_control.BURST_ENABLE = BURST_ENABLE;
defparam the_write_burst_control.BURST_COUNT_WIDTH = MAX_BURST_COUNT_WIDTH;
defparam the_write_burst_control.WORD_SIZE = BYTE_ENABLE_WIDTH;
defparam the_write_burst_control.WORD_SIZE_LOG2 = (DATA_WIDTH == 8)? 0 : BYTE_ENABLE_WIDTH_LOG2; // need to make sure log2(word size) is 0 instead of 1 here when the data width is 8 bits
defparam the_write_burst_control.ADDRESS_WIDTH = ADDRESS_WIDTH;
defparam the_write_burst_control.LENGTH_WIDTH = LENGTH_WIDTH;
defparam the_write_burst_control.WRITE_FIFO_USED_WIDTH = FIFO_DEPTH_LOG2;
defparam the_write_burst_control.BURST_WRAPPING_SUPPORT = BURST_WRAPPING_SUPPORT;
/********************************************* END MODULE INSTANTIATIONS ************************************************************************/
/********************************************* CONTROL AND COMBINATIONAL SIGNALS ****************************************************************/
// breakout the descriptor information into more manageable names
assign descriptor_address = {snk_command_data[123:92], snk_command_data[31:0]}; // 64-bit addressing support
assign descriptor_length = snk_command_data[63:32];
assign descriptor_programmable_burst_count = snk_command_data[75:68];
assign descriptor_stride = snk_command_data[91:76];
assign descriptor_end_on_eop_enable = snk_command_data[64];
assign sw_stop_in = snk_command_data[66];
assign sw_reset_in = snk_command_data[67];
assign stride_amount = (STRIDE_ENABLE == 1)? stride_d1[STRIDE_WIDTH-1:0] : FIXED_STRIDE; // hardcoding to FIXED_STRIDE when stride capabilities are disabled
assign maximum_burst_count = (PROGRAMMABLE_BURST_ENABLE == 1)? programmable_burst_count_d1 : MAX_BURST_COUNT;
assign eop_enable = (PACKET_ENABLE == 1)? descriptor_end_on_eop_enable_d1 : 1'b0; // no eop or early termination support when packet support is disabled
assign done_strobe = (done == 1) & (done_d1 == 0) & (reset_taken == 0); // set_done asserts the done register so this strobe fires when the last write completes
assign response_error = (ERROR_ENABLE == 1)? error : 8'b00000000;
assign response_actual_bytes_transferred = (PACKET_ENABLE == 1)? actual_bytes_transferred_counter : 32'h00000000;
// transfer size amounts for special cases (starting unaligned, ending with a partial word, starting unaligned and ending with a partial word on the same write)
assign short_first_access_size = BYTE_ENABLE_WIDTH - start_byte_address;
assign short_last_access_size = (eop_enable == 1)? (packet_beat_size + packet_bytes_buffered_d1) : (length_counter & LSB_MASK);
assign short_first_and_last_access_size = (eop_enable == 1)? (BYTE_ENABLE_WIDTH - buffered_empty) : (length_counter & LSB_MASK);
/* special case transfer enables and counter increment values (address_counter, length_counter, and actual_bytes_transferred)
short_first_access_enable is for transfers that start aligned but reach the next word boundary
short_last_access_enable is for transfers that are not the first transfer but don't end with on a word boundary
short_first_and_last_access_enable is for transfers that start and end with a single transfer and don't end on a word boundary (may or may not be aligned)
*/
generate
if (UNALIGNED_ACCESSES_ENABLE == 1)
begin
// all three enables are mutually exclusive to provide one-hot encoding for the bytes to transfer mux
assign short_first_access_enable = (start_byte_address != 0) & (first_access == 1) & ((eop_enable == 1)? ((start_byte_address + BYTE_ENABLE_WIDTH - buffered_empty) >= BYTE_ENABLE_WIDTH) : (first_word_boundary_not_reached_d1 == 0));
assign short_last_access_enable = (first_access == 0) & ((eop_enable == 1)? ((packet_beat_size + packet_bytes_buffered_d1) < BYTE_ENABLE_WIDTH): (length_counter < BYTE_ENABLE_WIDTH));
assign short_first_and_last_access_enable = (first_access == 1) & ((eop_enable == 1)? ((start_byte_address + BYTE_ENABLE_WIDTH - buffered_empty) < BYTE_ENABLE_WIDTH) : (first_word_boundary_not_reached_d1 == 1));
assign bytes_to_transfer = bytes_to_transfer_mux;
assign address_increment = bytes_to_transfer_mux; // can't use stride when unaligned accesses are enabled
end
else if (ONLY_FULL_ACCESS_ENABLE == 1)
begin
assign short_first_access_enable = 0;
assign short_last_access_enable = 0;
assign short_first_and_last_access_enable = 0;
assign bytes_to_transfer = BYTE_ENABLE_WIDTH;
if (STRIDE_ENABLE == 1)
begin
assign address_increment = BYTE_ENABLE_WIDTH * stride_amount; // the byte address portion of the address_counter is grounded to make sure the address presented to the fabric is aligned
end
else
begin
assign address_increment = BYTE_ENABLE_WIDTH; // the byte address portion of the address_counter is grounded to make sure the address presented to the fabric is aligned
end
end
else // must be aligned but can end with any number of bytes
begin
assign short_first_access_enable = 0;
assign short_last_access_enable = (eop_enable == 1)? (buffered_eop == 1) : (length_counter < BYTE_ENABLE_WIDTH); // less than a word to transfer
assign short_first_and_last_access_enable = 0;
assign bytes_to_transfer = bytes_to_transfer_mux;
if (STRIDE_ENABLE == 1)
begin
assign address_increment = BYTE_ENABLE_WIDTH * stride_amount;
end
else
begin
assign address_increment = BYTE_ENABLE_WIDTH;
end
end
endgenerate
// the control logic ensures this mux is one-hot with the fall through being the typical full word aligned access
always @ (short_first_access_enable or short_last_access_enable or short_first_and_last_access_enable or short_first_access_size or short_last_access_size or short_first_and_last_access_size)
begin
case ({short_first_and_last_access_enable, short_last_access_enable, short_first_access_enable})
3'b001: bytes_to_transfer_mux = short_first_access_size; // unaligned and reaches the next word boundary
3'b010: bytes_to_transfer_mux = short_last_access_size; // aligned and does not reach the next word boundary
3'b100: bytes_to_transfer_mux = short_first_and_last_access_size; // unaligned and does not reach the next word boundary
default: bytes_to_transfer_mux = BYTE_ENABLE_WIDTH; // aligned and reaches the next word boundary (i.e. a full word transfer)
endcase
end
// Avalon-ST is network order (a.k.a. big endian) so we need to reverse the symbols before jamming them into the FIFO, changing the symbol width to something other than 8 might break something...
generate
genvar i;
for(i = 0; i < DATA_WIDTH; i = i + SYMBOL_WIDTH) // the data width is always a multiple of the symbol width
begin: symbol_swap
assign fifo_write_data[i +SYMBOL_WIDTH -1: i] = snk_data[DATA_WIDTH -i -1: DATA_WIDTH -i - SYMBOL_WIDTH];
end
endgenerate
// sticking the error, empty, eop, and eop bits at the top of the FIFO write data, flooring empty to zero when eop is not asserted (empty is only valid on eop cycles)
assign fifo_write_data[FIFO_WIDTH-1:DATA_WIDTH] = {snk_error, (snk_eop == 1)? snk_empty:0, snk_sop, snk_eop};
// swap the bytes if big endian is enabled (remember that this isn't tested so use at your own risk and make sure you understand the software impact this has)
generate
if(BIG_ENDIAN_ACCESS == 1)
begin
genvar j;
for(j=0; j < DATA_WIDTH; j = j + 8)
begin: byte_swap
assign fifo_read_data_rearranged[j +8 -1: j] = fifo_read_data[DATA_WIDTH -j -1: DATA_WIDTH -j - 8];
assign master_byteenable[j/8] = supported_byteenable[(DATA_WIDTH -j -1)/8];
end
end
else
begin
assign fifo_read_data_rearranged = fifo_read_data[DATA_WIDTH-1:0]; // little endian so no byte swapping necessary
assign master_byteenable = supported_byteenable; // dito
end
endgenerate
// fifo read data is in the format of {error, empty, sop, eop, data} with the following widths {ERROR_WIDTH, NUMBER_OF_SYMBOLS_LOG2, 1, 1, DATA_WIDTH}
assign buffered_data = fifo_read_data_rearranged;
assign buffered_error = fifo_read_data[DATA_WIDTH +2 +NUMBER_OF_SYMBOLS_LOG2 + ERROR_WIDTH -1: DATA_WIDTH +2 +NUMBER_OF_SYMBOLS_LOG2];
generate
if (PACKET_ENABLE == 1)
begin
assign buffered_eop = fifo_read_data[DATA_WIDTH];
assign buffered_sop = fifo_read_data[DATA_WIDTH +1];
if (ONLY_FULL_ACCESS_ENABLE == 1)
begin
assign buffered_empty = 0; // ignore the empty signal and assume it was a full beat
end
else
begin
assign buffered_empty = fifo_read_data[DATA_WIDTH +2 +NUMBER_OF_SYMBOLS_LOG2 -1: DATA_WIDTH +2]; // empty is packed into the upper FIFO bits
end
end
else
begin
assign buffered_empty = 0;
assign buffered_eop = 0;
assign buffered_sop = 0;
end
endgenerate
/* Generating mask bits based on the size of the transfer before the unaligned access adjustment. This is based on the
transfer size to determine how many byte enables would be asserted in the aligned case. Afterwards the
byte enables will be shifted left based on how far out of alignment the address counter is (should only happen for the
first transfer). If the data path is 32 bits wide then the following masks are generated:
Transfer Size Index Mask
1 0 0001
2 1 0011
3 2 0111
4 3 1111
Note that the index is just the transfer size minus one
*/
generate if (BYTE_ENABLE_WIDTH > 1)
begin
genvar k;
for (k = 0; k < BYTE_ENABLE_WIDTH; k = k + 1)
begin: byte_enable_loop
assign byteenable_masks[k] = { {(BYTE_ENABLE_WIDTH-k-1){1'b0}}, {(k+1){1'b1}} }; // Byte enable width - k zeros followed by k ones
end
end
else
begin
assign byteenable_masks[0] = 1'b1; // will be stubbed at top level
end
endgenerate
/* byteenable_mask is based on an aligned access determined by the transfer size. This value is then shifted
to the left by the unaligned offset (first transfer only) to compensate for the unaligned offset so that the
correct byte enables are enabled. When the accesses are aligned then no barrelshifting is needed and when full
accesses are used then all byte enables will be asserted always. */
generate if (ONLY_FULL_ACCESS_ENABLE == 1)
begin
assign unsupported_byteenable = {BYTE_ENABLE_WIDTH{1'b1}}; // always full accesses so the byte enables are all ones
end
else if (UNALIGNED_ACCESSES_ENABLE == 0)
begin
assign unsupported_byteenable = byteenable_masks[bytes_to_transfer_mux - 1]; // aligned so no unaligned adjustment required
end
else // unaligned case
begin
assign unsupported_byteenable = byteenable_masks[bytes_to_transfer_mux - 1] << (address_counter & LSB_MASK); // barrelshift adjusts for unaligned start address
end
endgenerate
generate if (BYTE_ENABLE_WIDTH > 1)
begin
assign address = address_counter & { {(ADDRESS_WIDTH-BYTE_ENABLE_WIDTH_LOG2){1'b1}}, {BYTE_ENABLE_WIDTH_LOG2{1'b0}} }; // masking LSBs (byte offsets) since the address counter might not be aligned for the first transfer
end
else
begin
assign address = address_counter; // don't need to mask any bits as the address will only advance one byte at a time
end
endgenerate
assign done = (length_counter == 0) | ((PACKET_ENABLE == 1) & (eop_enable == 1) & (eop_seen == 1) & (extra_write == 0));
assign packet_beat_size = (eop_seen == 1) ? 0 : (BYTE_ENABLE_WIDTH - buffered_empty); // when the eop arrives we can't add more to packet_bytes_buffered_d1
assign packet_bytes_buffered = packet_beat_size + packet_bytes_buffered_d1 - bytes_to_transfer;
// extra_write is only applicable when unaligned accesses are performed. This extra access gets the remaining data buffered in the ST to MM adapter block written to memory
assign extra_write = (UNALIGNED_ACCESSES_ENABLE == 1) & (((PACKET_ENABLE == 1) & (eop_enable == 1))?
((eop_seen == 1) & (packet_bytes_buffered_d1 != 0)) : // when packets are used if there are left over bytes buffered after eop is seen perform an extra write
((first_access == 0) & (start_byte_address != 0) & (short_last_access_enable == 1) & (start_byte_address >= length_counter[BYTE_ENABLE_WIDTH_LOG2-1:0]))); // non-packet transfer and there are extra bytes buffered so performing an extra access
assign first_word_boundary_not_reached = (descriptor_length < BYTE_ENABLE_WIDTH) & // length is less than the word size
(((descriptor_length & LSB_MASK) + (descriptor_address & LSB_MASK)) < BYTE_ENABLE_WIDTH); // start address + length doesn't reach the next word boundary (not used for packet transfers)
assign write = ((fifo_empty == 0) | (extra_write == 1)) & (done == 0) & (stopped == 0);
assign st_to_mm_adapter_enable = (done == 0) & (extra_write == 0);
assign write_complete = (write == 1) & (master_waitrequest == 0) & (write_stall_from_byte_enable_generator == 0) & (write_stall_from_write_burst_control == 0); // writing still occuring and no reasons to prevent the write cycle from completing
assign increment_address = ((write == 1) & (write_complete == 1)) & (stopped == 0);
assign go = (snk_command_valid == 1) & (snk_command_ready == 1); // go with be one cycle since done will be set to 0 on the next cycle (length will be non-zero)
assign snk_ready = (fifo_full == 0) & // need to make sure more streaming data doesn't come in when the FIFO is full
(((PACKET_ENABLE == 1) & (snk_sop == 1) & (fifo_empty == 0)) != 1); // need to make sure that only one packet is buffered at any given time (sop will continue to be asserted until the buffer is written out)
assign length_sync_reset = (((reset_taken == 1) | (early_termination_d1 == 1)) & (done == 0)) | (done_strobe == 1); // abrupt stop cases or packet transfer just completed (otherwise the length register will reach 0 by itself)
assign fifo_write = (snk_ready == 1) & (snk_valid == 1);
assign early_termination = (eop_enable == 1) & (write_complete == 1) & (length_counter < bytes_to_transfer); // packet transfer and the length counter is about to roll over so stop transfering
assign stop_state = stopped;
assign reset_delayed = (reset_taken == 0) & (sw_reset_in == 1);
assign src_response_data = {{212{1'b0}}, done_strobe, early_termination_d1, response_error, stop_state, reset_delayed, response_actual_bytes_transferred};
/********************************************* END CONTROL AND COMBINATIONAL SIGNALS ************************************************************/
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__MUX2I_0_V
`define SKY130_FD_SC_LP__MUX2I_0_V
/**
* mux2i: 2-input multiplexer, output inverted.
*
* Verilog wrapper for mux2i with size of 0 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__mux2i.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__mux2i_0 (
Y ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__mux2i base (
.Y(Y),
.A0(A0),
.A1(A1),
.S(S),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__mux2i_0 (
Y ,
A0,
A1,
S
);
output Y ;
input A0;
input A1;
input S ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__mux2i base (
.Y(Y),
.A0(A0),
.A1(A1),
.S(S)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__MUX2I_0_V
|
/* salsa_piped.v ... fully registered salsa core (column and row results regs)
*
* Copyright (c) 2013 kramble
* Derived from scrypt.c Copyright 2009 Colin Percival, 2011 ArtForz
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`timescale 1ns/1ps
`define IDX(x) (((x)+1)*(32)-1):((x)*(32))
module salsa (clk, feedback, B, Bx, Bo, X0out, X1out, Xaddr);
// Latency 9 clock cycles (4 col steps + 4 row + 1 sync), hence 4 salsa iterations in 36 cycles
input clk;
input feedback;
input [511:0]B;
input [511:0]Bx;
output [511:0]Bo;
output [511:0]X0out; // Pipelined B
output [511:0]X1out; // Pipelined Bx
output [9:0]Xaddr; // Address
wire [511:0]xx; // Initial xor
wire [511:0]xxd8; // Delayed 8 cycles
wire [511:0]xr; // Output of salsa core
reg [511:0]xrd; // Feedback (9th latency step to maintain sync with ram access)
wire [9:0]addr; // Address from salsa
reg [9:0]xxd7_addr;
// X0/X1 delays ... just to check timing, probably need to use a ram location to reduce routing congestion
reg [511:0]x0d1;
reg [511:0]x0d2;
reg [511:0]x0d3;
reg [511:0]x0d4;
reg [511:0]x0d5;
reg [511:0]x0d6;
reg [511:0]x0d7;
reg [511:0]x0d8;
reg [511:0]x1d1;
reg [511:0]x1d2;
reg [511:0]x1d3;
reg [511:0]x1d4;
reg [511:0]x1d5;
reg [511:0]x1d6;
reg [511:0]x1d7;
reg [511:0]x1d8;
assign X0out = x0d8;
assign X1out = x1d8;
salsa_core salsa1 (clk, feedback ? xrd : xx, xr, addr);
always @ (posedge clk)
begin
xrd <= xr;
x0d1 <= B;
x0d2 <= x0d1;
x0d3 <= x0d2;
x0d4 <= x0d3;
x0d5 <= x0d4;
x0d6 <= x0d5;
x0d7 <= x0d6;
x0d8 <= x0d7;
x1d1 <= Bx;
x1d2 <= x1d1;
x1d3 <= x1d2;
x1d4 <= x1d3;
x1d5 <= x1d4;
x1d6 <= x1d5;
x1d7 <= x1d6;
x1d8 <= x1d7;
xxd7_addr <= x0d6[9:0] ^ x1d6[9:0];
end
genvar i;
generate
for (i = 0; i < 16; i = i + 1) begin : XX
// Initial XOR. NB this adds to the propagation delay of the first salsa, may want register it.
assign xx[`IDX(i)] = B[`IDX(i)] ^ Bx[`IDX(i)];
assign xxd8[`IDX(i)] = x0d8[`IDX(i)] ^ x1d8[`IDX(i)]; // Could do one cycle early (in reg) to save an xor delay
// Final sum. NB Ouptut is at 8 cycle latency.
assign Bo[`IDX(i)] = xxd8[`IDX(i)] + xr[`IDX(i)];
end
endgenerate
assign Xaddr = xxd7_addr + addr;
endmodule
module salsa_core (clk, x, out, addr);
input clk;
input [511:0]x;
output [511:0]out;
output [9:0]addr;
// This is clunky due to my lack of verilog skills but it works so elegance can come later
// ... actually its now gotten quite ridiculous, see KLUDGE below
// Aliases for inputs
wire [31:0] x00;
wire [31:0] x01;
wire [31:0] x02;
wire [31:0] x03;
wire [31:0] x04;
wire [31:0] x05;
wire [31:0] x06;
wire [31:0] x07;
wire [31:0] x08;
wire [31:0] x09;
wire [31:0] x10;
wire [31:0] x11;
wire [31:0] x12;
wire [31:0] x13;
wire [31:0] x14;
wire [31:0] x15;
assign x00 = x[`IDX(0)];
assign x01 = x[`IDX(1)];
assign x02 = x[`IDX(2)];
assign x03 = x[`IDX(3)];
assign x04 = x[`IDX(4)];
assign x05 = x[`IDX(5)];
assign x06 = x[`IDX(6)];
assign x07 = x[`IDX(7)];
assign x08 = x[`IDX(8)];
assign x09 = x[`IDX(9)];
assign x10 = x[`IDX(10)];
assign x11 = x[`IDX(11)];
assign x12 = x[`IDX(12)];
assign x13 = x[`IDX(13)];
assign x14 = x[`IDX(14)];
assign x15 = x[`IDX(15)];
// Column & Row Results (yup, I wrote a program to generate these) ...
// Not all of these are used, but let the synthesizer take care of that for now
// TODO prune the unused ones, may be important with certain synth settings
// BEGIN KLUDGE
`include "sgen.inc" // .inc so it does not accidentally get compiled separately as .v
// END KLUDGE
wire [31:0]c00s; // Column sums
wire [31:0]c01s;
wire [31:0]c02s;
wire [31:0]c03s;
wire [31:0]c04s;
wire [31:0]c05s;
wire [31:0]c06s;
wire [31:0]c07s;
wire [31:0]c08s;
wire [31:0]c09s;
wire [31:0]c10s;
wire [31:0]c11s;
wire [31:0]c12s;
wire [31:0]c13s;
wire [31:0]c14s;
wire [31:0]c15s;
wire [31:0]r00s; // Row sums
wire [31:0]r01s;
wire [31:0]r02s;
wire [31:0]r03s;
wire [31:0]r04s;
wire [31:0]r05s;
wire [31:0]r06s;
wire [31:0]r07s;
wire [31:0]r08s;
wire [31:0]r09s;
wire [31:0]r10s;
wire [31:0]r11s;
wire [31:0]r12s;
wire [31:0]r13s;
wire [31:0]r14s;
wire [31:0]r15s;
wire [31:0]r00sx;
/* From scrypt.c
#define R(a,b) (((a) << (b)) | ((a) >> (32 - (b))))
for (i = 0; i < 8; i += 2) {
// Operate on columns
x04 ^= R(x00+x12, 7); x09 ^= R(x05+x01, 7); x14 ^= R(x10+x06, 7); x03 ^= R(x15+x11, 7);
x08 ^= R(x04+x00, 9); x13 ^= R(x09+x05, 9); x02 ^= R(x14+x10, 9); x07 ^= R(x03+x15, 9);
x12 ^= R(x08+x04,13); x01 ^= R(x13+x09,13); x06 ^= R(x02+x14,13); x11 ^= R(x07+x03,13);
x00 ^= R(x12+x08,18); x05 ^= R(x01+x13,18); x10 ^= R(x06+x02,18); x15 ^= R(x11+x07,18);
// Operate on rows
x01 ^= R(x00+x03, 7); x06 ^= R(x05+x04, 7); x11 ^= R(x10+x09, 7); x12 ^= R(x15+x14, 7);
x02 ^= R(x01+x00, 9); x07 ^= R(x06+x05, 9); x08 ^= R(x11+x10, 9); x13 ^= R(x12+x15, 9);
x03 ^= R(x02+x01,13); x04 ^= R(x07+x06,13); x09 ^= R(x08+x11,13); x14 ^= R(x13+x12,13);
x00 ^= R(x03+x02,18); x05 ^= R(x04+x07,18); x10 ^= R(x09+x08,18); x15 ^= R(x14+x13,18);
}
*/
// cols
assign c04s = x00 + x12;
assign c09s = x05 + x01;
assign c14s = x10 + x06;
assign c03s = x15 + x11;
assign c08s = c04 + x00d1;
assign c13s = c09 + x05d1;
assign c02s = c14 + x10d1;
assign c07s = c03 + x15d1;
assign c12s = c08 + c04d1;
assign c01s = c13 + c09d1;
assign c06s = c02 + c14d1;
assign c11s = c07 + c03d1;
assign c00s = c12 + c08d1;
assign c05s = c01 + c13d1;
assign c10s = c06 + c02d1;
assign c15s = c11 + c07d1;
// rows
assign r01s = c00 + c03d3;
assign r06s = c05 + c04d3;
assign r11s = c10 + c09d3;
assign r12s = c15 + c14d3;
assign r02s = r01 + c00d1;
assign r07s = r06 + c05d1;
assign r08s = r11 + c10d1;
assign r13s = r12 + c15d1;
assign r03s = r02 + r01d1;
assign r04s = r07 + r06d1;
assign r09s = r08 + r11d1;
assign r14s = r13 + r12d1;
assign r00s = r03 + r02d1;
assign r05s = r04 + r07d1;
assign r10s = r09 + r08d1;
assign r15s = r14 + r13d1;
// Hack to bring out address one cycle earlier
assign r00sx = c00d3 ^ { r00s[13:0], r00s[31:14] };
assign addr = r00sx[9:0];
assign out = { r15, r14d1, r13d2, r12d3, r11d3, r10, r09d1, r08d2, r07d2, r06d3, r05, r04d1, r03d1, r02d2, r01d3, r00 };
always @ (posedge clk)
begin
c04 <= x04 ^ { c04s[24:0], c04s[31:25] };
c09 <= x09 ^ { c09s[24:0], c09s[31:25] };
c14 <= x14 ^ { c14s[24:0], c14s[31:25] };
c03 <= x03 ^ { c03s[24:0], c03s[31:25] };
c08 <= x08d1 ^ { c08s[22:0], c08s[31:23] };
c13 <= x13d1 ^ { c13s[22:0], c13s[31:23] };
c02 <= x02d1 ^ { c02s[22:0], c02s[31:23] };
c07 <= x07d1 ^ { c07s[22:0], c07s[31:23] };
c12 <= x12d2 ^ { c12s[18:0], c12s[31:19] };
c01 <= x01d2 ^ { c01s[18:0], c01s[31:19] };
c06 <= x06d2 ^ { c06s[18:0], c06s[31:19] };
c11 <= x11d2 ^ { c11s[18:0], c11s[31:19] };
c00 <= x00d3 ^ { c00s[13:0], c00s[31:14] };
c05 <= x05d3 ^ { c05s[13:0], c05s[31:14] };
c10 <= x10d3 ^ { c10s[13:0], c10s[31:14] };
c15 <= x15d3 ^ { c15s[13:0], c15s[31:14] };
r01 <= c01d1 ^ { r01s[24:0], r01s[31:25] };
r06 <= c06d1 ^ { r06s[24:0], r06s[31:25] };
r11 <= c11d1 ^ { r11s[24:0], r11s[31:25] };
r12 <= c12d1 ^ { r12s[24:0], r12s[31:25] };
r02 <= c02d3 ^ { r02s[22:0], r02s[31:23] };
r07 <= c07d3 ^ { r07s[22:0], r07s[31:23] };
r08 <= c08d3 ^ { r08s[22:0], r08s[31:23] };
r13 <= c13d3 ^ { r13s[22:0], r13s[31:23] };
r03 <= c03d5 ^ { r03s[18:0], r03s[31:19] };
r04 <= c04d5 ^ { r04s[18:0], r04s[31:19] };
r09 <= c09d5 ^ { r09s[18:0], r09s[31:19] };
r14 <= c14d5 ^ { r14s[18:0], r14s[31:19] };
// r00 <= c00d3 ^ { r00s[13:0], r00s[31:14] };
r00 <= r00sx;
r05 <= c05d3 ^ { r05s[13:0], r05s[31:14] };
r10 <= c10d3 ^ { r10s[13:0], r10s[31:14] };
r15 <= c15d3 ^ { r15s[13:0], r15s[31:14] };
end
endmodule
|
// ============================================================================
// Copyright (c) 2010
// ============================================================================
//
// Permission:
//
//
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods.
// ============================================================================
//
// ReConfigurable Computing Group
//
// web: http://www.ecs.umass.edu/ece/tessier/rcg/
//
//
// ============================================================================
// Major Functions/Design Description:
//
//
//
// ============================================================================
// Revision History:
// ============================================================================
// Ver.: |Author: |Mod. Date: |Changes Made:
// V1.0 |RCG |05/10/2011 |
// ============================================================================
//include "NF_2.1_defines.v"
//include "registers.v"
//include "reg_defines_reference_router.v"
module ip_arp
#(parameter NUM_QUEUES = 8,
parameter LUT_DEPTH = `ROUTER_OP_LUT_ARP_TABLE_DEPTH,
parameter LUT_DEPTH_BITS = log2(LUT_DEPTH)
)
(// --- Interface to ip_arp
input [31:0] next_hop_ip,
input [NUM_QUEUES-1:0] lpm_output_port,
input lpm_vld,
input lpm_hit,
// --- interface to process block
output [47:0] next_hop_mac,
output [NUM_QUEUES-1:0] output_port,
output arp_mac_vld,
output arp_lookup_hit,
output lpm_lookup_hit,
input rd_arp_result,
// --- Interface to registers
// --- Read port
input [LUT_DEPTH_BITS-1:0] arp_rd_addr, // address in table to read
input arp_rd_req, // request a read
output [47:0] arp_rd_mac, // data read from the LUT at rd_addr
output [31:0] arp_rd_ip, // ip to match in the CAM
output arp_rd_ack, // pulses high
// --- Write port
input [LUT_DEPTH_BITS-1:0] arp_wr_addr,
input arp_wr_req,
input [47:0] arp_wr_mac,
input [31:0] arp_wr_ip, // data to match in the CAM
output arp_wr_ack,
// --- Misc
input reset,
input clk
);
function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction // log2
//--------------------- Internal Parameter-------------------------
//---------------------- Wires and regs----------------------------
wire cam_busy;
wire cam_match;
wire [LUT_DEPTH-1:0] cam_match_addr;
wire [31:0] cam_cmp_din, cam_cmp_data_mask;
wire [31:0] cam_din, cam_data_mask;
wire cam_we;
wire [LUT_DEPTH_BITS-1:0] cam_wr_addr;
wire [47:0] next_hop_mac_result;
wire empty;
reg [NUM_QUEUES-1:0] output_port_latched;
reg lpm_hit_latched;
//------------------------- Modules-------------------------------
// 1 cycle read latency, 2 cycles write latency
/*
bram_cam_unencoded_32x32 arp_cam
(
// Outputs
.busy (cam_busy),
.match (cam_match),
.match_addr (cam_match_addr),
// Inputs
.clk (clk),
.cmp_din (cam_cmp_din),
.din (cam_din),
.we (cam_we),
.wr_addr (cam_wr_addr));
*/
// wire cam_busy_signal_reg;
cam arp_cam
(
.reset(reset),
.wr_clk(clk),
.wr_en(cam_we),
.wr_key(cam_din),
.wr_index(cam_wr_addr),
.wr_erase_n(1'b1),
.rd_clk(clk),
.rd_en(lpm_vld),
.rd_key(cam_cmp_din),
.one_hot_addr(cam_match_addr),
.match_addr(),
.match(cam_match),
.multi_match(),
.index_reg(),
.cam_full(),
.multi_index()
);
//assign cam_busy = cam_busy_signal_reg;
//assign cam_busy = 1'b0;
localparam
IDLE_STATE_CAM = 2'b00,
FIRST_STATE_CAM = 2'b01,
SECOND_STATE_CAM = 2'b10;
reg [1:0] state_cam,state_cam_nxt;
reg cam_busy_signal_reg,cam_busy_signal_reg_next;
always @(posedge clk) begin
if (reset) begin
state_cam <= IDLE_STATE_CAM;
cam_busy_signal_reg <= 1'b0;
end
else begin
state_cam <= state_cam_nxt;
cam_busy_signal_reg <= cam_busy_signal_reg_next;
end // else
end
always @(*) begin
cam_busy_signal_reg_next = cam_busy_signal_reg;
state_cam_nxt = state_cam;
case (state_cam)
IDLE_STATE_CAM: begin
if (cam_we) begin
cam_busy_signal_reg_next = 1'b1;
state_cam_nxt = FIRST_STATE_CAM;
end
else
cam_busy_signal_reg_next = 1'b0;
end
FIRST_STATE_CAM: begin
cam_busy_signal_reg_next = 1'b1;
state_cam_nxt = SECOND_STATE_CAM;
end
SECOND_STATE_CAM: begin
cam_busy_signal_reg_next = 1'b0;
state_cam_nxt = IDLE_STATE_CAM;
end
endcase // case(state)
end
assign cam_busy = cam_busy_signal_reg;
unencoded_cam_lut_sm
#(.CMP_WIDTH(32), // IPv4 addr width
.DATA_WIDTH(48),
.LUT_DEPTH(LUT_DEPTH)
) cam_lut_sm
(// --- Interface for lookups
.lookup_req (lpm_vld),
.lookup_cmp_data (next_hop_ip),
.lookup_cmp_dmask (32'h0),
.lookup_ack (lookup_ack),
.lookup_hit (lookup_hit),
.lookup_data (next_hop_mac_result),
// --- Interface to registers
// --- Read port
.rd_addr (arp_rd_addr), // address in table to read
.rd_req (arp_rd_req), // request a read
.rd_data (arp_rd_mac), // data found for the entry
.rd_cmp_data (arp_rd_ip), // matching data for the entry
.rd_cmp_dmask (), // don't cares entry
.rd_ack (arp_rd_ack), // pulses high
// --- Write port
.wr_addr (arp_wr_addr),
.wr_req (arp_wr_req),
.wr_data (arp_wr_mac), // data found for the entry
.wr_cmp_data (arp_wr_ip), // matching data for the entry
.wr_cmp_dmask (32'h0), // don't cares for the entry
.wr_ack (arp_wr_ack),
// --- CAM interface
.cam_busy (cam_busy),
.cam_match (cam_match),
.cam_match_addr (cam_match_addr),
.cam_cmp_din (cam_cmp_din),
.cam_din (cam_din),
.cam_we (cam_we),
.cam_wr_addr (cam_wr_addr),
.cam_cmp_data_mask (cam_cmp_data_mask),
.cam_data_mask (cam_data_mask),
// --- Misc
.reset (reset),
.clk (clk));
fallthrough_small_fifo #(.WIDTH(50+NUM_QUEUES), .MAX_DEPTH_BITS (2))
arp_fifo
(.din ({next_hop_mac_result, output_port_latched, lookup_hit, lpm_hit_latched}), // Data in
.wr_en (lookup_ack), // Write enable
.rd_en (rd_arp_result), // Read the next word
.dout ({next_hop_mac, output_port, arp_lookup_hit, lpm_lookup_hit}),
.full (),
.nearly_full (),
.prog_full (),
.empty (empty),
.reset (reset),
.clk (clk)
);
//------------------------- Logic --------------------------------
assign arp_mac_vld = !empty;
always @(posedge clk) begin
if(reset) begin
output_port_latched <= 0;
lpm_hit_latched <= 0;
end
else if(lpm_vld) begin
output_port_latched <= lpm_output_port;
lpm_hit_latched <= lpm_hit;
end
end
endmodule // ip_arp
|
// test_simulation_techmap_and_19_tech.v
module f1_TECH_AND18(input [17:0] in, output out);
assign out = ∈
endmodule
module f1_TECH_AND4(input [3:0] in, output out);
assign out = ∈
endmodule
// test_simulation_techmap_and_5_tech.v
module f2_TECH_AND5(input [4:0] in, output out);
assign out = ∈
endmodule
// test_simulation_techmap_nand_19_tech.v
module f3_TECH_NAND18(input [17:0] in, output out);
assign out = ~(&in);
endmodule
module f3_TECH_NAND4(input [3:0] in, output out);
assign out = ~(&in);
endmodule
module f3_TECH_NAND2(input [1:0] in, output out);
assign out = ~(&in);
endmodule
// test_simulation_techmap_nand_2_tech.v
module f4_TECH_NAND18(input [17:0] in, output out);
assign out = ~(&in);
endmodule
module f4_TECH_NAND4(input [3:0] in, output out);
assign out = ~(&in);
endmodule
module f4_TECH_NAND2(input [1:0] in, output out);
assign out = ~(&in);
endmodule
// test_simulation_techmap_nand_5_tech.v
module f5_TECH_NAND18(input [17:0] in, output out);
assign out = ~(&in);
endmodule
module f5_TECH_NAND4(input [3:0] in, output out);
assign out = ~(&in);
endmodule
module f5_TECH_NAND2(input [1:0] in, output out);
assign out = ~(&in);
endmodule
// test_simulation_techmap_nor_19_tech.v
module f6_TECH_NOR18(input [17:0] in, output out);
assign out = ~(|in);
endmodule
module f6_TECH_NOR4(input [3:0] in, output out);
assign out = ~(|in);
endmodule
module f6_TECH_NOR2(input [1:0] in, output out);
assign out = ~(|in);
endmodule
// test_simulation_techmap_nor_2_tech.v
module f7_TECH_NOR18(input [17:0] in, output out);
assign out = ~(|in);
endmodule
module f7_TECH_NOR4(input [3:0] in, output out);
assign out = ~(|in);
endmodule
module f7_TECH_NOR2(input [1:0] in, output out);
assign out = ~(|in);
endmodule
// test_simulation_techmap_nor_5_tech.v
module f8_TECH_NOR18(input [17:0] in, output out);
assign out = ~(|in);
endmodule
module f8_TECH_NOR4(input [3:0] in, output out);
assign out = ~(|in);
endmodule
module f8_TECH_NOR2(input [1:0] in, output out);
assign out = ~(|in);
endmodule
// test_simulation_techmap_or_19_tech.v
module f9_TECH_OR18(input [17:0] in, output out);
assign out = |in;
endmodule
module f9_TECH_OR4(input [3:0] in, output out);
assign out = |in;
endmodule
// test_simulation_techmap_or_5_tech.v
module f10_TECH_OR5(input [4:0] in, output out);
assign out = |in;
endmodule
// test_simulation_techmap_xnor_2_tech.v
module f11_TECH_XOR5(input [4:0] in, output out);
assign out = in[0] ^ in[1] ^ in[2] ^ in[3] ^ in[4];
endmodule
module f11_TECH_XOR2(input [1:0] in, output out);
assign out = in[0] ^ in[1];
endmodule
// test_simulation_techmap_xnor_5_tech.v
module f12_TECH_XOR5(input [4:0] in, output out);
assign out = in[0] ^ in[1] ^ in[2] ^ in[3] ^ in[4];
endmodule
module f12_TECH_XOR2(input [1:0] in, output out);
assign out = in[0] ^ in[1];
endmodule
// test_simulation_techmap_xor_19_tech.v
module f13_TECH_XOR2(input [1:0] in, output out);
assign out = in[0] ^ in[1];
endmodule
// test_simulation_techmap_xor_2_tech.v
module f14_TECH_XOR5(input [4:0] in, output out);
assign out = in[0] ^ in[1] ^ in[2] ^ in[3] ^ in[4];
endmodule
module f14_TECH_XOR2(input [1:0] in, output out);
assign out = in[0] ^ in[1];
endmodule
// test_simulation_techmap_xor_5_tech.v
module f15_TECH_XOR5(input [4:0] in, output out);
assign out = in[0] ^ in[1] ^ in[2] ^ in[3] ^ in[4];
endmodule
module f15_TECH_XOR2(input [1:0] in, output out);
assign out = in[0] ^ in[1];
endmodule
|
//////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : Pixel Datapath
// File : pixel_dp.v
// Author : Jim MacLeod
// Created : 29-Dec-2005
// RCS File : $Source:$
// Status : $Id:$
//
//////////////////////////////////////////////////////////////////////////////
//
// Description :
//
//
/////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
//
//////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
//////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 10 ps
module pixel_dp
(
input reset,
input blank,
input pixclk,
input [23:0] pix_din,
input [2:0] pixformat,
input b8dcol,
input b16dcol,
input ziblin,
input fsf,
input b32dcol,
input display_cursor,
input p0_apply_cursor,
input p0_highlight,
input p0_translucent,
input [7:0] p0_red_cursor,
input [7:0] p0_grn_cursor,
input [7:0] p0_blu_cursor,
input [7:0] p0_red_pal,
input [7:0] p0_grn_pal,
input [7:0] p0_blu_pal,
input blankr,
input [7:0] pix_mask,
input blankb,
input blankg,
input ldi_normalvgsel, // 2X Horizontal Zoom in VGA
input vga_mode, // In VGA mode
output [7:0] p0_red_pal_adr,
output [7:0] p0_grn_pal_adr,
output [7:0] p0_blu_pal_adr,
output reg [7:0] p0_red,
output reg [7:0] p0_green,
output reg [7:0] p0_blue,
output reg blankx
);
reg [63:0] pix_reg, pix_reg1; // Pipeline pixel data
reg [7:0] vga_reg, vga_reg1; // Pipeline VGA data
reg blankl, blanks; // Pipeline blanks
reg [23:0] pix_reg3, pix_reg4;
reg [23:0] pix_stage1;
reg direct_mode;
reg b8bpp2;
reg b32bpp2;
reg bpp16_2, bpp16_4;
reg bpp16_5, bpp16_6, bpp16_7, bpp16_8;
reg vga_mode1;
reg b8bpp1, b16bpp1, b32bpp1;
reg bpp16_21, bpp16_41, bpp16_51;
reg bpp16_61, bpp16_71, bpp16_81;
reg [23:0] pixel_stage3; // Third stage pixel pipe
reg [23:0] rgb4_0, rgb4_1, rgb4_2, rgb4_3; // Pipelined pixels
reg [23:0] temp_store;
reg [7:0] pix_mask1, pix_mask2;
wire [7:0] select;
wire [7:0] pass_address;
reg [6:0] p0_sel_red, p0_sel_blu, p0_sel_grn;
reg [7:0] p0_red_cursor_d;
reg [7:0] p0_grn_cursor_d;
reg [7:0] p0_blu_cursor_d;
reg [7:0] p0_red_pal_d;
reg [7:0] p0_grn_pal_d;
reg [7:0] p0_blu_pal_d;
// Datapath Stage 1:
// handle the 64-bit and vga data in synchronization.
// latch the data in on the LCLK, and pass it thru 2 register set
// using the pix clk.
//
// No need to sync on blank signal. the data will be masked at the VDAC input
// using a synchronzed blanking decode.
// 3rd sync level
always @(posedge pixclk or negedge reset)
if (!reset) begin
pix_reg3 <= 24'b0;
pix_reg4 <= 24'b0;
pix_stage1 <= 24'b0;
end else begin
pix_reg3 <= pix_din; // Moved to one later because of REGRAM in CRT
pix_reg4 <=pix_reg3;
pix_stage1 <= pix_reg4;
end
always @(posedge pixclk or negedge reset)
if (!reset) begin
blankx <= 1'b0;
end else begin
blankx <= blank;
end
// Datapath stage 3:
// This pixel mux select the incoming pixel data
// and route it to the RGB bus level 1.
// The select lines are:
// 1. VGA Mode, selects VGA data
// 2. b8bpp selects 8 bit per pixel
// 3. b32bpp selects 32 bit per pixel
// Other conditions for sparse cases were removed.
// 4b. bpp16_2 selects mode 2 of 16 bits per pixel
// 4d. bpp16_4 selects mode 4 of 16 bits per pixel
// 4e. bpp16_5 selects mode 5 of 16 bits per pixel
// 4f. bpp16_6 selects mode 6 of 16 bits per pixel
// 4g. bpp16_7 selects mode 7 of 16 bits per pixel
// 4h. bpp16_8 selects mode 8 of 16 bits per pixel
// The data to be muxed is
// 1. vga data
// 2. pix_c(23-16), pix_b(15- 8) pix_a(7- 0)
// 5. Partion bits part(2-0)
always @(posedge pixclk or negedge reset) begin
if (!reset) begin
direct_mode <= 1'b0;
b8bpp2 <= 1'b0;
b32bpp2 <= 1'b0;
bpp16_2 <= 1'b0;
bpp16_4 <= 1'b0;
bpp16_5 <= 1'b0;
bpp16_6 <= 1'b0;
bpp16_7 <= 1'b0;
bpp16_8 <= 1'b0;
vga_mode1 <= 1'b0;
b8bpp1 <= 1'b0;
b16bpp1 <= 1'b0;
b32bpp1 <= 1'b0;
bpp16_21 <= 1'b0;
bpp16_41 <= 1'b0;
bpp16_51 <= 1'b0;
bpp16_61 <= 1'b0;
bpp16_71 <= 1'b0;
bpp16_81 <= 1'b0;
end else begin
direct_mode <= ((b8bpp2 & b8dcol) |
(b32bpp2 & b32dcol) |
bpp16_51 | bpp16_61 |
bpp16_71 | bpp16_81
) & ~vga_mode1 ;// vga mode is indirect mode
b8bpp2 <= b8bpp1 ;
b32bpp2 <= b32bpp1 ;
bpp16_2 <= bpp16_21 ;
bpp16_4 <= bpp16_41 ;
bpp16_5 <= bpp16_51 ;
bpp16_6 <= bpp16_61 ;
bpp16_7 <= bpp16_71 ;
bpp16_8 <= bpp16_81 ;
vga_mode1 <= vga_mode ;
b8bpp1 <= !pixformat[2] & pixformat[1] & pixformat[0];
b32bpp1 <= pixformat[2] & pixformat[1] & !pixformat[0];
b16bpp1 <= pixformat[2] & !pixformat[1] & !pixformat[0];
bpp16_21 <= b16bpp1 & (!b16dcol) & (!fsf);
bpp16_41 <= b16bpp1 & (!b16dcol) & ( fsf);
bpp16_51 <= b16bpp1 & ( b16dcol) & (!fsf) & ( !ziblin);
bpp16_61 <= b16bpp1 & ( b16dcol) & ( fsf) & ( !ziblin);
bpp16_71 <= b16bpp1 & ( b16dcol) & (!fsf) & ( ziblin);
bpp16_81 <= b16bpp1 & ( b16dcol) & ( fsf) & ( ziblin);
end
end
// parse pixels according to the modes.
assign select = {b8bpp2, b32bpp2, bpp16_2, bpp16_4, bpp16_5,
bpp16_6, bpp16_7, bpp16_8};
always @(posedge pixclk or negedge reset) begin
if (!reset) begin
pixel_stage3 <= 24'b0;
end else begin
casex (select)
8'b10000000: pixel_stage3 <= pix_stage1; // 8 Bpp
8'b01000000: pixel_stage3 <= pix_stage1; // 32 Bpp
// 16-2 bpp
8'b00100000: pixel_stage3 <= { 3'b0, pix_stage1[14:10], // P0 Red
3'b0, pix_stage1[9:5], // P0 Green
3'b0, pix_stage1[4:0]}; // P0 Blue
// 16-4 bpp
8'b00010000: pixel_stage3 <= { 3'b0, pix_stage1[15:11], // P0 Red
2'b0, pix_stage1[10:5], // P0 Green
3'b0, pix_stage1[4:0]}; // P0 Blue
// 16-5 bpp
8'b00001000: pixel_stage3 <= { pix_stage1[14:10], 3'b0, // P0 Red
pix_stage1[9:5], 3'b0, // P0 Green
pix_stage1[4:0], 3'b0}; // P0 Blue
// 16-6 bpp
8'b00000100: pixel_stage3 <= { pix_stage1[15:11], 3'b0, // P0 Red
pix_stage1[10:5], 2'b0, // P0 Green
pix_stage1[4:0], 3'b0}; // P0 Blue
// 16-7 bpp
8'b00000010: pixel_stage3 <= { pix_stage1[14:10],
pix_stage1[14:12], // P0 Red
pix_stage1[9:5],
pix_stage1[9:7], // P0 Green
pix_stage1[4:0],
pix_stage1[4:2]}; // P0 Blue
// 16-8 bpp
8'b00000001: pixel_stage3 <= { pix_stage1[15:11],
pix_stage1[15:13], // P0 Red
pix_stage1[10:5],
pix_stage1[10:9], // P0 Green
pix_stage1[4:0],
pix_stage1[4:2]}; // P0 Blue
// 8bpp greyscale
default: pixel_stage3 <= pix_stage1;
endcase
end
end
// Datapath stage 4:
// Generates the final rgb data to the VDAC output.
// added power management, zero address to palettes in direct mode.
// Problem: Highlight and Translucent Cursors were not coming on.
// wire act_high_d = display_cursor & highlight & direct_mode;
// wire act_high_id = display_cursor & highlight & !direct_mode;
// wire act_transl_d = display_cursor & translucent & direct_mode;
// wire act_transl_id = display_cursor & translucent & !direct_mode;
// Summary of changes:
// Remove [color]_pal_adr pipe stage. This causes the palette ram address to
// arrive one cycle earlier. The "toggle" signal to the odd/even palette
// address registers in ram_ctl.v is inverted to take advantage of the
// change in this module.
wire p0_act_cursor = display_cursor & p0_apply_cursor;
wire p0_act_high_d = display_cursor & p0_highlight & direct_mode;
wire p0_act_high_id = display_cursor & p0_highlight & !direct_mode;
wire p0_act_transl_d = display_cursor & p0_translucent & direct_mode;
wire p0_act_transl_id = display_cursor & p0_translucent & !direct_mode;
// added for power management, zero address to palettes in direct mode
assign pass_address = {8{!direct_mode}};
// generate pipilined cursor direct and indirect address
always @(posedge pixclk or negedge reset) begin
if (!reset) begin
rgb4_0 <= 24'b0;
rgb4_1 <= 24'b0;
rgb4_2 <= 24'b0;
rgb4_3 <= 24'b0;
pix_mask1 <= 8'b0; // Sync the CPU register
pix_mask2 <= 8'b0; // Sync the CPU register
end else begin
pix_mask1 <= pix_mask;
pix_mask2 <= pix_mask1;
rgb4_0 <= pixel_stage3;
rgb4_1 <= rgb4_0;
rgb4_2 <= rgb4_1;
rgb4_3 <= rgb4_2;
end
end // else: !if(!reset)
// Generate addresses for pixels
assign p0_blu_pal_adr = pixel_stage3[7:0] & pix_mask2[7:0] & pass_address;
assign p0_grn_pal_adr = pixel_stage3[15:8] & pix_mask2[7:0] & pass_address;
assign p0_red_pal_adr = pixel_stage3[23:16] & pix_mask2[7:0] & pass_address;
wire drmode = direct_mode & !blankr;
wire dbmode = direct_mode & !blankb;
wire dgmode = direct_mode & !blankg;
// Adding a pipe stage for timing
always @(posedge pixclk) begin
p0_sel_red <= {blankr, p0_act_cursor, p0_act_high_d, p0_act_high_id,
p0_act_transl_id, p0_act_transl_d, drmode};
p0_sel_blu <= {blankb, p0_act_cursor, p0_act_high_d, p0_act_high_id,
p0_act_transl_id, p0_act_transl_d, dbmode};
p0_sel_grn <= {blankg, p0_act_cursor, p0_act_high_d, p0_act_high_id,
p0_act_transl_id, p0_act_transl_d, dgmode};
p0_red_pal_d <= p0_red_pal;
p0_blu_pal_d <= p0_blu_pal;
p0_grn_pal_d <= p0_grn_pal;
p0_red_cursor_d <= p0_red_cursor;
p0_blu_cursor_d <= p0_blu_cursor;
p0_grn_cursor_d <= p0_grn_cursor;
end
always @(posedge pixclk or negedge reset) begin
if (!reset) begin
p0_red <= 8'b0;
p0_green <= 8'b0;
p0_blue <= 8'b0;
end else begin
casex (p0_sel_red)
7'b1xxxxxx : p0_red <= 8'b0;
7'b01xxxxx : p0_red <= p0_red_cursor_d;
7'b001xxxx : p0_red <= ~rgb4_3[23:16];
7'b0001xxx : p0_red <= ~p0_red_pal_d;
7'b00001xx : p0_red <= {p0_red_cursor_d[7], p0_red_pal_d[7:1]};
7'b000001x : p0_red <= {p0_red_cursor_d[7], rgb4_3[23:17]};
7'b0000001 : p0_red <= rgb4_3[23:16];
default : p0_red <= p0_red_pal_d;
endcase
casex (p0_sel_grn)
7'b1xxxxxx : p0_green <= 8'b0;
7'b01xxxxx : p0_green <= p0_grn_cursor_d;
7'b001xxxx : p0_green <= ~rgb4_3[15:8];
7'b0001xxx : p0_green <= ~p0_grn_pal_d;
7'b00001xx : p0_green <= {p0_grn_cursor_d[7], p0_grn_pal_d[7:1]};
7'b000001x : p0_green <= {p0_grn_cursor_d[7], rgb4_3[15:9]};
7'b0000001 : p0_green <= rgb4_3[15:8];
default : p0_green <= p0_grn_pal_d;
endcase
casex(p0_sel_blu)
7'b1xxxxxx : p0_blue <= 8'b0;
7'b01xxxxx : p0_blue <= p0_blu_cursor_d;
7'b001xxxx : p0_blue <= ~rgb4_3[7:0];
7'b0001xxx : p0_blue <= ~p0_blu_pal_d;
7'b00001xx : p0_blue <= {p0_blu_cursor_d[7], p0_blu_pal_d[7:1]};
7'b000001x : p0_blue <= {p0_blu_cursor_d[7], rgb4_3[7:1]};
7'b0000001 : p0_blue <= rgb4_3[7:0];
default : p0_blue <= p0_blu_pal_d;
endcase
end
end
endmodule // pixel_dp
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: fifo32_shallow.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 16.0.0 Build 211 04/27/2016 SJ Lite Edition
// ************************************************************
//Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus Prime License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo32_shallow (
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull);
input [31:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [31:0] q;
output rdempty;
output wrfull;
wire [31:0] sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire [31:0] q = sub_wire0[31:0];
wire rdempty = sub_wire1;
wire wrfull = sub_wire2;
dcfifo dcfifo_component (
.data (data),
.rdclk (rdclk),
.rdreq (rdreq),
.wrclk (wrclk),
.wrreq (wrreq),
.q (sub_wire0),
.rdempty (sub_wire1),
.wrfull (sub_wire2),
.aclr (),
.eccstatus (),
.rdfull (),
.rdusedw (),
.wrempty (),
.wrusedw ());
defparam
dcfifo_component.intended_device_family = "Cyclone IV E",
dcfifo_component.lpm_numwords = 4,
dcfifo_component.lpm_showahead = "OFF",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 32,
dcfifo_component.lpm_widthu = 2,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 4,
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.wrsync_delaypipe = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "4"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "32"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "32"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "2"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_shallow.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_shallow.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_shallow.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_shallow.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_shallow_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_shallow_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
/* 同步 FIFO 4*128 */
// 一种4bit 128深度的 同步FIFO设计
// @`13
// 2017年6月6日
// 哈尔滨工业大学（威海） EDA课程设计
// Final Ver 2017.6.13
// @`13
module fifo(clock, // 时钟信号 [默认使用50m Hz]
reset, // 重置信号 [低电平有效]
read, // 读信号 [低电平有效]
write, // 写信号 [低电平有效]
fifo_in, // FIFO 4位数据输入 [使用 4位 拨动开关输入
digitron_out, // 数码管输出 [使用 7位 共阳极数码管]
digitron_select, // 数码管片选信号 [低电平有效]
fifo_empty, // FIFO 空信号 [高电平有效]
fifo_full // FIFO 满信号 [高电平有效]
);
parameter DEPTH = 128; // 128 深
parameter DEPTH_BINARY = 7; // 深度的二进制位数
parameter WIDTH = 4; // 4bit宽
parameter MAX_CONT = 7'b1111111; // 计数器最大值127 [0~127]
// LED 灯的二进制表示
// 根据 《数字系统设计与Verilog DHL (6th Edition)》P153 所提供的7段数码管电路图
// 基于共阳极方式
/*
—— a
| | f b
—— g
| | e c
—— d
*/
// Len_N = abcdefg
// 使用一个七段数码管基于16进制显示 4bit 数据
parameter
digitron_0 = 7'b0000001,
digitron_1 = 7'b1001111,
digitron_2 = 7'b0010010,
digitron_3 = 7'b1111001,
digitron_4 = 7'b1001100,
digitron_5 = 7'b0100100,
digitron_6 = 7'b0100000,
digitron_7 = 7'b0001111,
digitron_8 = 7'b0000000,
digitron_9 = 7'b0000100,
digitron_a = 7'b0011000,
digitron_b = 7'b1100000,
digitron_c = 7'b0110001,
digitron_d = 7'b1000010,
digitron_e = 7'b1001111,
digitron_f = 7'b0110000;
input clock,reset,read,write; // 时钟，重置，读开关，写开关
input [WIDTH-1:0]fifo_in; // FIFO 数据输入
output [6:0] digitron_out; // 数码管 FIFO 数据输出
output fifo_empty,fifo_full; // 空标志,满标志
output digitron_select; // 数码管选择信号
reg digitron_select;
reg div; // 驱动信号
reg [23:0] clock_count; // 时钟计数器
reg [6:0] digitron_out; // 数据输出寄存器
reg [WIDTH-1:0]fifo_out; // 数据输出寄存器
reg [WIDTH-1:0]ram[DEPTH-1:0]; // 128深度 8宽度的 RAM 寄存器
reg [DEPTH_BINARY-1:0]read_ptr,write_ptr,counter; // 读指针，写指针，计数器 长度为2^7
wire fifo_empty,fifo_full; // 空标志,满标志
initial
begin // 初始化数据
counter = 0;
read_ptr = 0;
write_ptr = 0;
fifo_out = 0;
div = 0;
clock_count = 0;
digitron_out = digitron_8;
digitron_select = 0;
end
always@(posedge clock)
begin
if(clock_count == 24'b111111111111111111111111)
begin // 驱动信号生成
div =~ div;
clock_count <= 0;
end
else
begin // 使用一个接近1HZ的驱动信号
clock_count <= clock_count+1;
end
end
always@(posedge clock)
begin // 片选信号始终有效
digitron_select <= 1'b0;
end
assign fifo_empty = (counter == 0); // 空标志位赋值
assign fifo_full = (counter == DEPTH-1); // 满标志位赋值
always@(posedge div) // 时钟同步驱动
if(reset) // Reset 重置FIFO
begin
read_ptr = 0;
write_ptr = 0;
counter = 0;
digitron_out = digitron_8;
digitron_select = 0;
end
else
case({read,write}) // 相应读写开关
2'b00:; //没有读写指令
2'b01: //写指令，数据输入FIFO
begin
if (counter < DEPTH - 1) // 判断是否可写
begin
ram[write_ptr] = fifo_in;
counter = counter + 1;
write_ptr = (write_ptr == DEPTH-1)?0:write_ptr + 1;
end
end
2'b10: //读指令，数据读出FIFO
begin
if (counter > 0) // 判断是否可读
begin
fifo_out = ram[read_ptr];
case(fifo_out)
4'b0000 : digitron_out <= digitron_0;
4'b0001 : digitron_out <= digitron_1;
4'b0010 : digitron_out <= digitron_2;
4'b0011 : digitron_out <= digitron_3;
4'b0100 : digitron_out <= digitron_4;
4'b0101 : digitron_out <= digitron_5;
4'b0110 : digitron_out <= digitron_6;
4'b0111 : digitron_out <= digitron_7;
4'b1000 : digitron_out <= digitron_8;
4'b1001 : digitron_out <= digitron_9;
4'b1010 : digitron_out <= digitron_a;
4'b1011 : digitron_out <= digitron_b;
4'b1100 : digitron_out <= digitron_c;
4'b1101 : digitron_out <= digitron_d;
4'b1110 : digitron_out <= digitron_e;
4'b1111 : digitron_out <= digitron_f;
endcase
counter = counter - 1;
read_ptr = (read_ptr == DEPTH-1)?0:read_ptr + 1;
end
end
2'b11: //读写指令同时，数据可以直接输出
begin
if(counter == 0)
begin
fifo_out = fifo_in; // 直接输出
case(fifo_out) // todo : 去除case的冗余代码 2017.6.13
4'b0000 : digitron_out <= digitron_0;
4'b0001 : digitron_out <= digitron_1;
4'b0010 : digitron_out <= digitron_2;
4'b0011 : digitron_out <= digitron_3;
4'b0100 : digitron_out <= digitron_4;
4'b0101 : digitron_out <= digitron_5;
4'b0110 : digitron_out <= digitron_6;
4'b0111 : digitron_out <= digitron_7;
4'b1000 : digitron_out <= digitron_8;
4'b1001 : digitron_out <= digitron_9;
4'b1010 : digitron_out <= digitron_a;
4'b1011 : digitron_out <= digitron_b;
4'b1100 : digitron_out <= digitron_c;
4'b1101 : digitron_out <= digitron_d;
4'b1110 : digitron_out <= digitron_e;
4'b1111 : digitron_out <= digitron_f;
endcase
end
else
begin
ram[write_ptr]=fifo_in;
fifo_out=ram[read_ptr];
case(fifo_out) // todo : 去除case的冗余代码 2017.6.13
4'b0000 : digitron_out <= digitron_0;
4'b0001 : digitron_out <= digitron_1;
4'b0010 : digitron_out <= digitron_2;
4'b0011 : digitron_out <= digitron_3;
4'b0100 : digitron_out <= digitron_4;
4'b0101 : digitron_out <= digitron_5;
4'b0110 : digitron_out <= digitron_6;
4'b0111 : digitron_out <= digitron_7;
4'b1000 : digitron_out <= digitron_8;
4'b1001 : digitron_out <= digitron_9;
4'b1010 : digitron_out <= digitron_a;
4'b1011 : digitron_out <= digitron_b;
4'b1100 : digitron_out <= digitron_c;
4'b1101 : digitron_out <= digitron_d;
4'b1110 : digitron_out <= digitron_e;
4'b1111 : digitron_out <= digitron_f;
endcase
write_ptr=(write_ptr==DEPTH-1)?0:write_ptr+1;
read_ptr=(read_ptr==DEPTH-1)?0:write_ptr+1;
end
end
endcase
endmodule
// 一种信号去抖电路
// module debouncing(
// BJ_CLK, //采集时钟
// RESET, //系统复位信号 [低电平有效]
// BUTTON_IN, //按键输入信号
// BUTTON_OUT //消抖后的输出信号
// );
// input BJ_CLK;
// input RESET;
// input BUTTON_IN;
// output BUTTON_OUT;
// reg BUTTON_IN_Q, BUTTON_IN_2Q, BUTTON_IN_3Q;
// always @(posedge BJ_CLK or negedge RESET)
// begin
// if(~RESET)
// begin
// BUTTON_IN_Q <= 1'b1;
// BUTTON_IN_2Q <= 1'b1;
// BUTTON_IN_3Q <= 1'b1;
// end
// else
// begin
// BUTTON_IN_Q <= BUTTON_IN;
// BUTTON_IN_2Q <= BUTTON_IN_Q;
// BUTTON_IN_3Q <= BUTTON_IN_2Q;
// end
// end
// wire BUTTON_OUT = BUTTON_IN_2Q | BUTTON_IN_3Q;
// endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:50:49 09/24/2013
// Design Name: Contador
// Module Name: C:/Users/Fabian/Documents/GitHub/taller-diseno-digital/Lab3/laboratorio3/test_contador.v
// Project Name: laboratorio3
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Contador
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_contador;
// Inputs
reg enable_cuenta;
reg reset;
// Outputs
wire [3:0] mem_address;
// Instantiate the Unit Under Test (UUT)
Contador uut (
.enable_cuenta(enable_cuenta),
.reset(reset),
.mem_address(mem_address)
);
initial begin
// Initialize Inputs
enable_cuenta = 0;
reset = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
enable_cuenta = 1;
#10;
enable_cuenta = 0;
#10;
enable_cuenta = 1;
#10;
enable_cuenta = 0;
#10;
enable_cuenta = 1;
#10;
enable_cuenta = 0;
#10;
enable_cuenta = 1;
#10;
enable_cuenta = 0;
#10;
enable_cuenta = 1;
#10;
enable_cuenta = 0;
#10;
enable_cuenta = 1;
#10;
enable_cuenta = 0;
#10;
enable_cuenta = 1;
#10;
enable_cuenta = 0;
#10;
enable_cuenta = 1;
#10;
enable_cuenta = 0;
#10;
enable_cuenta = 1;
#10;
enable_cuenta = 0;
#10;
enable_cuenta = 1;
#10;
enable_cuenta = 0;
#10;
enable_cuenta = 1;
#10;
enable_cuenta = 0;
#10;
enable_cuenta = 1;
#10;
enable_cuenta = 0;
#10;
enable_cuenta = 1;
#10;
enable_cuenta = 0;
#10;
enable_cuenta = 1;
#10;
enable_cuenta = 0;
#10;
enable_cuenta = 1;
#10;
enable_cuenta = 0;
#10;
enable_cuenta = 1;
#10;
enable_cuenta = 0;
#10;
enable_cuenta = 1;
#10;
enable_cuenta = 0;
#10;
enable_cuenta = 1;
#10;
enable_cuenta = 0;
#10;
end
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_clk_cl_ctu_cmp.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module bw_clk_cl_ctu_cmp(/*AUTOARG*/
// Outputs
so, rclk, dbginit_l, cluster_grst_l,
// Inputs
si, se, grst_l, gdbginit_l, gclk, cluster_cken, arst_l, adbginit_l
);
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input adbginit_l; // To u_cluster_header of cluster_header.v
input arst_l; // To u_cluster_header of cluster_header.v
input cluster_cken; // To u_cluster_header of cluster_header.v
input gclk; // To u_cluster_header of cluster_header.v
input gdbginit_l; // To u_cluster_header of cluster_header.v
input grst_l; // To u_cluster_header of cluster_header.v
input se; // To u_cluster_header of cluster_header.v
input si; // To u_cluster_header of cluster_header.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output cluster_grst_l; // From u_cluster_header of cluster_header.v
output dbginit_l; // From u_cluster_header of cluster_header.v
output rclk; // From u_cluster_header of cluster_header.v
output so; // From u_cluster_header of cluster_header.v
// End of automatics
cluster_header_ctu u_cluster_header (/*AUTOINST*/
// Outputs
.dbginit_l(dbginit_l),
.cluster_grst_l(cluster_grst_l),
.rclk(rclk),
.so (so),
// Inputs
.gclk(gclk),
.cluster_cken(cluster_cken),
.arst_l(arst_l),
.grst_l(grst_l),
.adbginit_l(adbginit_l),
.gdbginit_l(gdbginit_l),
.si (si),
.se (se));
endmodule // cluster_header
// Local Variables:
// verilog-library-directories:("." "../../../common/rtl")
// verilog-auto-sense-defines-constant:t
// End:
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//Legal Notice: (C)2012 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_test_bench (
// inputs:
D_iw,
D_iw_op,
D_iw_opx,
D_valid,
E_alu_result,
E_mem_byte_en,
E_st_data,
E_valid,
F_pcb,
F_valid,
R_ctrl_exception,
R_ctrl_ld,
R_ctrl_ld_non_io,
R_dst_regnum,
R_wr_dst_reg,
W_bstatus_reg,
W_cmp_result,
W_estatus_reg,
W_ienable_reg,
W_ipending_reg,
W_mem_baddr,
W_rf_wr_data,
W_status_reg,
W_valid,
W_vinst,
W_wr_data,
av_ld_data_aligned_unfiltered,
clk,
d_address,
d_byteenable,
d_read,
d_write_nxt,
i_address,
i_read,
i_readdata,
i_waitrequest,
reset_n,
// outputs:
av_ld_data_aligned_filtered,
d_write,
test_has_ended
)
;
output [ 31: 0] av_ld_data_aligned_filtered;
output d_write;
output test_has_ended;
input [ 31: 0] D_iw;
input [ 5: 0] D_iw_op;
input [ 5: 0] D_iw_opx;
input D_valid;
input [ 31: 0] E_alu_result;
input [ 3: 0] E_mem_byte_en;
input [ 31: 0] E_st_data;
input E_valid;
input [ 16: 0] F_pcb;
input F_valid;
input R_ctrl_exception;
input R_ctrl_ld;
input R_ctrl_ld_non_io;
input [ 4: 0] R_dst_regnum;
input R_wr_dst_reg;
input W_bstatus_reg;
input W_cmp_result;
input W_estatus_reg;
input [ 31: 0] W_ienable_reg;
input [ 31: 0] W_ipending_reg;
input [ 19: 0] W_mem_baddr;
input [ 31: 0] W_rf_wr_data;
input W_status_reg;
input W_valid;
input [ 55: 0] W_vinst;
input [ 31: 0] W_wr_data;
input [ 31: 0] av_ld_data_aligned_unfiltered;
input clk;
input [ 19: 0] d_address;
input [ 3: 0] d_byteenable;
input d_read;
input d_write_nxt;
input [ 16: 0] i_address;
input i_read;
input [ 31: 0] i_readdata;
input i_waitrequest;
input reset_n;
wire D_op_add;
wire D_op_addi;
wire D_op_and;
wire D_op_andhi;
wire D_op_andi;
wire D_op_beq;
wire D_op_bge;
wire D_op_bgeu;
wire D_op_blt;
wire D_op_bltu;
wire D_op_bne;
wire D_op_br;
wire D_op_break;
wire D_op_bret;
wire D_op_call;
wire D_op_callr;
wire D_op_cmpeq;
wire D_op_cmpeqi;
wire D_op_cmpge;
wire D_op_cmpgei;
wire D_op_cmpgeu;
wire D_op_cmpgeui;
wire D_op_cmplt;
wire D_op_cmplti;
wire D_op_cmpltu;
wire D_op_cmpltui;
wire D_op_cmpne;
wire D_op_cmpnei;
wire D_op_crst;
wire D_op_custom;
wire D_op_div;
wire D_op_divu;
wire D_op_eret;
wire D_op_flushd;
wire D_op_flushda;
wire D_op_flushi;
wire D_op_flushp;
wire D_op_hbreak;
wire D_op_initd;
wire D_op_initda;
wire D_op_initi;
wire D_op_intr;
wire D_op_jmp;
wire D_op_jmpi;
wire D_op_ldb;
wire D_op_ldbio;
wire D_op_ldbu;
wire D_op_ldbuio;
wire D_op_ldh;
wire D_op_ldhio;
wire D_op_ldhu;
wire D_op_ldhuio;
wire D_op_ldl;
wire D_op_ldw;
wire D_op_ldwio;
wire D_op_mul;
wire D_op_muli;
wire D_op_mulxss;
wire D_op_mulxsu;
wire D_op_mulxuu;
wire D_op_nextpc;
wire D_op_nor;
wire D_op_opx;
wire D_op_or;
wire D_op_orhi;
wire D_op_ori;
wire D_op_rdctl;
wire D_op_rdprs;
wire D_op_ret;
wire D_op_rol;
wire D_op_roli;
wire D_op_ror;
wire D_op_rsv02;
wire D_op_rsv09;
wire D_op_rsv10;
wire D_op_rsv17;
wire D_op_rsv18;
wire D_op_rsv25;
wire D_op_rsv26;
wire D_op_rsv33;
wire D_op_rsv34;
wire D_op_rsv41;
wire D_op_rsv42;
wire D_op_rsv49;
wire D_op_rsv57;
wire D_op_rsv61;
wire D_op_rsv62;
wire D_op_rsv63;
wire D_op_rsvx00;
wire D_op_rsvx10;
wire D_op_rsvx15;
wire D_op_rsvx17;
wire D_op_rsvx21;
wire D_op_rsvx25;
wire D_op_rsvx33;
wire D_op_rsvx34;
wire D_op_rsvx35;
wire D_op_rsvx42;
wire D_op_rsvx43;
wire D_op_rsvx44;
wire D_op_rsvx47;
wire D_op_rsvx50;
wire D_op_rsvx51;
wire D_op_rsvx55;
wire D_op_rsvx56;
wire D_op_rsvx60;
wire D_op_rsvx63;
wire D_op_sll;
wire D_op_slli;
wire D_op_sra;
wire D_op_srai;
wire D_op_srl;
wire D_op_srli;
wire D_op_stb;
wire D_op_stbio;
wire D_op_stc;
wire D_op_sth;
wire D_op_sthio;
wire D_op_stw;
wire D_op_stwio;
wire D_op_sub;
wire D_op_sync;
wire D_op_trap;
wire D_op_wrctl;
wire D_op_wrprs;
wire D_op_xor;
wire D_op_xorhi;
wire D_op_xori;
wire [ 31: 0] av_ld_data_aligned_filtered;
wire av_ld_data_aligned_unfiltered_0_is_x;
wire av_ld_data_aligned_unfiltered_10_is_x;
wire av_ld_data_aligned_unfiltered_11_is_x;
wire av_ld_data_aligned_unfiltered_12_is_x;
wire av_ld_data_aligned_unfiltered_13_is_x;
wire av_ld_data_aligned_unfiltered_14_is_x;
wire av_ld_data_aligned_unfiltered_15_is_x;
wire av_ld_data_aligned_unfiltered_16_is_x;
wire av_ld_data_aligned_unfiltered_17_is_x;
wire av_ld_data_aligned_unfiltered_18_is_x;
wire av_ld_data_aligned_unfiltered_19_is_x;
wire av_ld_data_aligned_unfiltered_1_is_x;
wire av_ld_data_aligned_unfiltered_20_is_x;
wire av_ld_data_aligned_unfiltered_21_is_x;
wire av_ld_data_aligned_unfiltered_22_is_x;
wire av_ld_data_aligned_unfiltered_23_is_x;
wire av_ld_data_aligned_unfiltered_24_is_x;
wire av_ld_data_aligned_unfiltered_25_is_x;
wire av_ld_data_aligned_unfiltered_26_is_x;
wire av_ld_data_aligned_unfiltered_27_is_x;
wire av_ld_data_aligned_unfiltered_28_is_x;
wire av_ld_data_aligned_unfiltered_29_is_x;
wire av_ld_data_aligned_unfiltered_2_is_x;
wire av_ld_data_aligned_unfiltered_30_is_x;
wire av_ld_data_aligned_unfiltered_31_is_x;
wire av_ld_data_aligned_unfiltered_3_is_x;
wire av_ld_data_aligned_unfiltered_4_is_x;
wire av_ld_data_aligned_unfiltered_5_is_x;
wire av_ld_data_aligned_unfiltered_6_is_x;
wire av_ld_data_aligned_unfiltered_7_is_x;
wire av_ld_data_aligned_unfiltered_8_is_x;
wire av_ld_data_aligned_unfiltered_9_is_x;
reg d_write;
wire test_has_ended;
assign D_op_call = D_iw_op == 0;
assign D_op_jmpi = D_iw_op == 1;
assign D_op_ldbu = D_iw_op == 3;
assign D_op_addi = D_iw_op == 4;
assign D_op_stb = D_iw_op == 5;
assign D_op_br = D_iw_op == 6;
assign D_op_ldb = D_iw_op == 7;
assign D_op_cmpgei = D_iw_op == 8;
assign D_op_ldhu = D_iw_op == 11;
assign D_op_andi = D_iw_op == 12;
assign D_op_sth = D_iw_op == 13;
assign D_op_bge = D_iw_op == 14;
assign D_op_ldh = D_iw_op == 15;
assign D_op_cmplti = D_iw_op == 16;
assign D_op_initda = D_iw_op == 19;
assign D_op_ori = D_iw_op == 20;
assign D_op_stw = D_iw_op == 21;
assign D_op_blt = D_iw_op == 22;
assign D_op_ldw = D_iw_op == 23;
assign D_op_cmpnei = D_iw_op == 24;
assign D_op_flushda = D_iw_op == 27;
assign D_op_xori = D_iw_op == 28;
assign D_op_stc = D_iw_op == 29;
assign D_op_bne = D_iw_op == 30;
assign D_op_ldl = D_iw_op == 31;
assign D_op_cmpeqi = D_iw_op == 32;
assign D_op_ldbuio = D_iw_op == 35;
assign D_op_muli = D_iw_op == 36;
assign D_op_stbio = D_iw_op == 37;
assign D_op_beq = D_iw_op == 38;
assign D_op_ldbio = D_iw_op == 39;
assign D_op_cmpgeui = D_iw_op == 40;
assign D_op_ldhuio = D_iw_op == 43;
assign D_op_andhi = D_iw_op == 44;
assign D_op_sthio = D_iw_op == 45;
assign D_op_bgeu = D_iw_op == 46;
assign D_op_ldhio = D_iw_op == 47;
assign D_op_cmpltui = D_iw_op == 48;
assign D_op_initd = D_iw_op == 51;
assign D_op_orhi = D_iw_op == 52;
assign D_op_stwio = D_iw_op == 53;
assign D_op_bltu = D_iw_op == 54;
assign D_op_ldwio = D_iw_op == 55;
assign D_op_rdprs = D_iw_op == 56;
assign D_op_flushd = D_iw_op == 59;
assign D_op_xorhi = D_iw_op == 60;
assign D_op_rsv02 = D_iw_op == 2;
assign D_op_rsv09 = D_iw_op == 9;
assign D_op_rsv10 = D_iw_op == 10;
assign D_op_rsv17 = D_iw_op == 17;
assign D_op_rsv18 = D_iw_op == 18;
assign D_op_rsv25 = D_iw_op == 25;
assign D_op_rsv26 = D_iw_op == 26;
assign D_op_rsv33 = D_iw_op == 33;
assign D_op_rsv34 = D_iw_op == 34;
assign D_op_rsv41 = D_iw_op == 41;
assign D_op_rsv42 = D_iw_op == 42;
assign D_op_rsv49 = D_iw_op == 49;
assign D_op_rsv57 = D_iw_op == 57;
assign D_op_rsv61 = D_iw_op == 61;
assign D_op_rsv62 = D_iw_op == 62;
assign D_op_rsv63 = D_iw_op == 63;
assign D_op_eret = D_op_opx & (D_iw_opx == 1);
assign D_op_roli = D_op_opx & (D_iw_opx == 2);
assign D_op_rol = D_op_opx & (D_iw_opx == 3);
assign D_op_flushp = D_op_opx & (D_iw_opx == 4);
assign D_op_ret = D_op_opx & (D_iw_opx == 5);
assign D_op_nor = D_op_opx & (D_iw_opx == 6);
assign D_op_mulxuu = D_op_opx & (D_iw_opx == 7);
assign D_op_cmpge = D_op_opx & (D_iw_opx == 8);
assign D_op_bret = D_op_opx & (D_iw_opx == 9);
assign D_op_ror = D_op_opx & (D_iw_opx == 11);
assign D_op_flushi = D_op_opx & (D_iw_opx == 12);
assign D_op_jmp = D_op_opx & (D_iw_opx == 13);
assign D_op_and = D_op_opx & (D_iw_opx == 14);
assign D_op_cmplt = D_op_opx & (D_iw_opx == 16);
assign D_op_slli = D_op_opx & (D_iw_opx == 18);
assign D_op_sll = D_op_opx & (D_iw_opx == 19);
assign D_op_wrprs = D_op_opx & (D_iw_opx == 20);
assign D_op_or = D_op_opx & (D_iw_opx == 22);
assign D_op_mulxsu = D_op_opx & (D_iw_opx == 23);
assign D_op_cmpne = D_op_opx & (D_iw_opx == 24);
assign D_op_srli = D_op_opx & (D_iw_opx == 26);
assign D_op_srl = D_op_opx & (D_iw_opx == 27);
assign D_op_nextpc = D_op_opx & (D_iw_opx == 28);
assign D_op_callr = D_op_opx & (D_iw_opx == 29);
assign D_op_xor = D_op_opx & (D_iw_opx == 30);
assign D_op_mulxss = D_op_opx & (D_iw_opx == 31);
assign D_op_cmpeq = D_op_opx & (D_iw_opx == 32);
assign D_op_divu = D_op_opx & (D_iw_opx == 36);
assign D_op_div = D_op_opx & (D_iw_opx == 37);
assign D_op_rdctl = D_op_opx & (D_iw_opx == 38);
assign D_op_mul = D_op_opx & (D_iw_opx == 39);
assign D_op_cmpgeu = D_op_opx & (D_iw_opx == 40);
assign D_op_initi = D_op_opx & (D_iw_opx == 41);
assign D_op_trap = D_op_opx & (D_iw_opx == 45);
assign D_op_wrctl = D_op_opx & (D_iw_opx == 46);
assign D_op_cmpltu = D_op_opx & (D_iw_opx == 48);
assign D_op_add = D_op_opx & (D_iw_opx == 49);
assign D_op_break = D_op_opx & (D_iw_opx == 52);
assign D_op_hbreak = D_op_opx & (D_iw_opx == 53);
assign D_op_sync = D_op_opx & (D_iw_opx == 54);
assign D_op_sub = D_op_opx & (D_iw_opx == 57);
assign D_op_srai = D_op_opx & (D_iw_opx == 58);
assign D_op_sra = D_op_opx & (D_iw_opx == 59);
assign D_op_intr = D_op_opx & (D_iw_opx == 61);
assign D_op_crst = D_op_opx & (D_iw_opx == 62);
assign D_op_rsvx00 = D_op_opx & (D_iw_opx == 0);
assign D_op_rsvx10 = D_op_opx & (D_iw_opx == 10);
assign D_op_rsvx15 = D_op_opx & (D_iw_opx == 15);
assign D_op_rsvx17 = D_op_opx & (D_iw_opx == 17);
assign D_op_rsvx21 = D_op_opx & (D_iw_opx == 21);
assign D_op_rsvx25 = D_op_opx & (D_iw_opx == 25);
assign D_op_rsvx33 = D_op_opx & (D_iw_opx == 33);
assign D_op_rsvx34 = D_op_opx & (D_iw_opx == 34);
assign D_op_rsvx35 = D_op_opx & (D_iw_opx == 35);
assign D_op_rsvx42 = D_op_opx & (D_iw_opx == 42);
assign D_op_rsvx43 = D_op_opx & (D_iw_opx == 43);
assign D_op_rsvx44 = D_op_opx & (D_iw_opx == 44);
assign D_op_rsvx47 = D_op_opx & (D_iw_opx == 47);
assign D_op_rsvx50 = D_op_opx & (D_iw_opx == 50);
assign D_op_rsvx51 = D_op_opx & (D_iw_opx == 51);
assign D_op_rsvx55 = D_op_opx & (D_iw_opx == 55);
assign D_op_rsvx56 = D_op_opx & (D_iw_opx == 56);
assign D_op_rsvx60 = D_op_opx & (D_iw_opx == 60);
assign D_op_rsvx63 = D_op_opx & (D_iw_opx == 63);
assign D_op_opx = D_iw_op == 58;
assign D_op_custom = D_iw_op == 50;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d_write <= 0;
else
d_write <= d_write_nxt;
end
assign test_has_ended = 1'b0;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//Clearing 'X' data bits
assign av_ld_data_aligned_unfiltered_0_is_x = ^(av_ld_data_aligned_unfiltered[0]) === 1'bx;
assign av_ld_data_aligned_filtered[0] = (av_ld_data_aligned_unfiltered_0_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[0];
assign av_ld_data_aligned_unfiltered_1_is_x = ^(av_ld_data_aligned_unfiltered[1]) === 1'bx;
assign av_ld_data_aligned_filtered[1] = (av_ld_data_aligned_unfiltered_1_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[1];
assign av_ld_data_aligned_unfiltered_2_is_x = ^(av_ld_data_aligned_unfiltered[2]) === 1'bx;
assign av_ld_data_aligned_filtered[2] = (av_ld_data_aligned_unfiltered_2_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[2];
assign av_ld_data_aligned_unfiltered_3_is_x = ^(av_ld_data_aligned_unfiltered[3]) === 1'bx;
assign av_ld_data_aligned_filtered[3] = (av_ld_data_aligned_unfiltered_3_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[3];
assign av_ld_data_aligned_unfiltered_4_is_x = ^(av_ld_data_aligned_unfiltered[4]) === 1'bx;
assign av_ld_data_aligned_filtered[4] = (av_ld_data_aligned_unfiltered_4_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[4];
assign av_ld_data_aligned_unfiltered_5_is_x = ^(av_ld_data_aligned_unfiltered[5]) === 1'bx;
assign av_ld_data_aligned_filtered[5] = (av_ld_data_aligned_unfiltered_5_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[5];
assign av_ld_data_aligned_unfiltered_6_is_x = ^(av_ld_data_aligned_unfiltered[6]) === 1'bx;
assign av_ld_data_aligned_filtered[6] = (av_ld_data_aligned_unfiltered_6_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[6];
assign av_ld_data_aligned_unfiltered_7_is_x = ^(av_ld_data_aligned_unfiltered[7]) === 1'bx;
assign av_ld_data_aligned_filtered[7] = (av_ld_data_aligned_unfiltered_7_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[7];
assign av_ld_data_aligned_unfiltered_8_is_x = ^(av_ld_data_aligned_unfiltered[8]) === 1'bx;
assign av_ld_data_aligned_filtered[8] = (av_ld_data_aligned_unfiltered_8_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[8];
assign av_ld_data_aligned_unfiltered_9_is_x = ^(av_ld_data_aligned_unfiltered[9]) === 1'bx;
assign av_ld_data_aligned_filtered[9] = (av_ld_data_aligned_unfiltered_9_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[9];
assign av_ld_data_aligned_unfiltered_10_is_x = ^(av_ld_data_aligned_unfiltered[10]) === 1'bx;
assign av_ld_data_aligned_filtered[10] = (av_ld_data_aligned_unfiltered_10_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[10];
assign av_ld_data_aligned_unfiltered_11_is_x = ^(av_ld_data_aligned_unfiltered[11]) === 1'bx;
assign av_ld_data_aligned_filtered[11] = (av_ld_data_aligned_unfiltered_11_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[11];
assign av_ld_data_aligned_unfiltered_12_is_x = ^(av_ld_data_aligned_unfiltered[12]) === 1'bx;
assign av_ld_data_aligned_filtered[12] = (av_ld_data_aligned_unfiltered_12_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[12];
assign av_ld_data_aligned_unfiltered_13_is_x = ^(av_ld_data_aligned_unfiltered[13]) === 1'bx;
assign av_ld_data_aligned_filtered[13] = (av_ld_data_aligned_unfiltered_13_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[13];
assign av_ld_data_aligned_unfiltered_14_is_x = ^(av_ld_data_aligned_unfiltered[14]) === 1'bx;
assign av_ld_data_aligned_filtered[14] = (av_ld_data_aligned_unfiltered_14_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[14];
assign av_ld_data_aligned_unfiltered_15_is_x = ^(av_ld_data_aligned_unfiltered[15]) === 1'bx;
assign av_ld_data_aligned_filtered[15] = (av_ld_data_aligned_unfiltered_15_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[15];
assign av_ld_data_aligned_unfiltered_16_is_x = ^(av_ld_data_aligned_unfiltered[16]) === 1'bx;
assign av_ld_data_aligned_filtered[16] = (av_ld_data_aligned_unfiltered_16_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[16];
assign av_ld_data_aligned_unfiltered_17_is_x = ^(av_ld_data_aligned_unfiltered[17]) === 1'bx;
assign av_ld_data_aligned_filtered[17] = (av_ld_data_aligned_unfiltered_17_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[17];
assign av_ld_data_aligned_unfiltered_18_is_x = ^(av_ld_data_aligned_unfiltered[18]) === 1'bx;
assign av_ld_data_aligned_filtered[18] = (av_ld_data_aligned_unfiltered_18_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[18];
assign av_ld_data_aligned_unfiltered_19_is_x = ^(av_ld_data_aligned_unfiltered[19]) === 1'bx;
assign av_ld_data_aligned_filtered[19] = (av_ld_data_aligned_unfiltered_19_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[19];
assign av_ld_data_aligned_unfiltered_20_is_x = ^(av_ld_data_aligned_unfiltered[20]) === 1'bx;
assign av_ld_data_aligned_filtered[20] = (av_ld_data_aligned_unfiltered_20_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[20];
assign av_ld_data_aligned_unfiltered_21_is_x = ^(av_ld_data_aligned_unfiltered[21]) === 1'bx;
assign av_ld_data_aligned_filtered[21] = (av_ld_data_aligned_unfiltered_21_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[21];
assign av_ld_data_aligned_unfiltered_22_is_x = ^(av_ld_data_aligned_unfiltered[22]) === 1'bx;
assign av_ld_data_aligned_filtered[22] = (av_ld_data_aligned_unfiltered_22_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[22];
assign av_ld_data_aligned_unfiltered_23_is_x = ^(av_ld_data_aligned_unfiltered[23]) === 1'bx;
assign av_ld_data_aligned_filtered[23] = (av_ld_data_aligned_unfiltered_23_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[23];
assign av_ld_data_aligned_unfiltered_24_is_x = ^(av_ld_data_aligned_unfiltered[24]) === 1'bx;
assign av_ld_data_aligned_filtered[24] = (av_ld_data_aligned_unfiltered_24_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[24];
assign av_ld_data_aligned_unfiltered_25_is_x = ^(av_ld_data_aligned_unfiltered[25]) === 1'bx;
assign av_ld_data_aligned_filtered[25] = (av_ld_data_aligned_unfiltered_25_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[25];
assign av_ld_data_aligned_unfiltered_26_is_x = ^(av_ld_data_aligned_unfiltered[26]) === 1'bx;
assign av_ld_data_aligned_filtered[26] = (av_ld_data_aligned_unfiltered_26_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[26];
assign av_ld_data_aligned_unfiltered_27_is_x = ^(av_ld_data_aligned_unfiltered[27]) === 1'bx;
assign av_ld_data_aligned_filtered[27] = (av_ld_data_aligned_unfiltered_27_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[27];
assign av_ld_data_aligned_unfiltered_28_is_x = ^(av_ld_data_aligned_unfiltered[28]) === 1'bx;
assign av_ld_data_aligned_filtered[28] = (av_ld_data_aligned_unfiltered_28_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[28];
assign av_ld_data_aligned_unfiltered_29_is_x = ^(av_ld_data_aligned_unfiltered[29]) === 1'bx;
assign av_ld_data_aligned_filtered[29] = (av_ld_data_aligned_unfiltered_29_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[29];
assign av_ld_data_aligned_unfiltered_30_is_x = ^(av_ld_data_aligned_unfiltered[30]) === 1'bx;
assign av_ld_data_aligned_filtered[30] = (av_ld_data_aligned_unfiltered_30_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[30];
assign av_ld_data_aligned_unfiltered_31_is_x = ^(av_ld_data_aligned_unfiltered[31]) === 1'bx;
assign av_ld_data_aligned_filtered[31] = (av_ld_data_aligned_unfiltered_31_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[31];
always @(posedge clk)
begin
if (reset_n)
if (^(F_valid) === 1'bx)
begin
$write("%0d ns: ERROR: altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_test_bench/F_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(D_valid) === 1'bx)
begin
$write("%0d ns: ERROR: altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_test_bench/D_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(E_valid) === 1'bx)
begin
$write("%0d ns: ERROR: altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_test_bench/E_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(W_valid) === 1'bx)
begin
$write("%0d ns: ERROR: altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_test_bench/W_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid)
if (^(R_wr_dst_reg) === 1'bx)
begin
$write("%0d ns: ERROR: altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_test_bench/R_wr_dst_reg is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid & R_wr_dst_reg)
if (^(W_wr_data) === 1'bx)
begin
$write("%0d ns: ERROR: altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_test_bench/W_wr_data is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid & R_wr_dst_reg)
if (^(R_dst_regnum) === 1'bx)
begin
$write("%0d ns: ERROR: altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_test_bench/R_dst_regnum is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(d_write) === 1'bx)
begin
$write("%0d ns: ERROR: altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_test_bench/d_write is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (d_write)
if (^(d_byteenable) === 1'bx)
begin
$write("%0d ns: ERROR: altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_test_bench/d_byteenable is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (d_write | d_read)
if (^(d_address) === 1'bx)
begin
$write("%0d ns: ERROR: altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_test_bench/d_address is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(d_read) === 1'bx)
begin
$write("%0d ns: ERROR: altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_test_bench/d_read is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(i_read) === 1'bx)
begin
$write("%0d ns: ERROR: altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_test_bench/i_read is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (i_read)
if (^(i_address) === 1'bx)
begin
$write("%0d ns: ERROR: altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_test_bench/i_address is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (i_read & ~i_waitrequest)
if (^(i_readdata) === 1'bx)
begin
$write("%0d ns: ERROR: altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_test_bench/i_readdata is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid & R_ctrl_ld)
if (^(av_ld_data_aligned_unfiltered) === 1'bx)
begin
$write("%0d ns: WARNING: altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_test_bench/av_ld_data_aligned_unfiltered is 'x'\n", $time);
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid & R_wr_dst_reg)
if (^(W_wr_data) === 1'bx)
begin
$write("%0d ns: WARNING: altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_test_bench/W_wr_data is 'x'\n", $time);
end
end
reg [31:0] trace_handle; // for $fopen
initial
begin
trace_handle = $fopen("altera_mem_if_sequencer_cpu_cv_synth_cpu_inst.tr");
$fwrite(trace_handle, "version 3\nnumThreads 1\n");
end
always @(posedge clk)
begin
if ((~reset_n || (W_valid)) && ~test_has_ended)
$fwrite(trace_handle, "%0d ns: %0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h\n", $time, ~reset_n, F_pcb, 0, D_op_intr, D_op_hbreak, D_iw, ~(D_op_intr | D_op_hbreak), R_wr_dst_reg, R_dst_regnum, 0, W_rf_wr_data, W_mem_baddr, E_st_data, E_mem_byte_en, W_cmp_result, E_alu_result, W_status_reg, W_estatus_reg, W_bstatus_reg, W_ienable_reg, W_ipending_reg, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, R_ctrl_exception, 0, 0, 0, 0);
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
//
// assign av_ld_data_aligned_filtered = av_ld_data_aligned_unfiltered;
//
//synthesis read_comments_as_HDL off
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:07:10 01/18/2016
// Design Name: registers_memory
// Module Name: /home/avre/Documents/arquitectura/enero/instruction_memory/registers_memory_tb.v
// Project Name: instruction_memory
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: registers_memory
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module registers_memory_tb;
// Inputs
reg clk;
reg reset;
reg wr_en;
reg [4:0] w_addr;
reg [4:0] r_addr1;
reg [4:0] r_addr2;
reg [31:0] w_data;
// Outputs
wire [31:0] r_data1;
wire [31:0] r_data2;
// Instantiate the Unit Under Test (UUT)
registers_memory uut (
.clk(clk),
.reset(reset),
.wr_en(wr_en),
.w_addr(w_addr),
.r_addr1(r_addr1),
.r_addr2(r_addr2),
.w_data(w_data),
.r_data1(r_data1),
.r_data2(r_data2)
);
initial begin
// Initialize Inputs
clk = 0;
wr_en = 0;
w_addr = 0;
r_addr1 = 0;
r_addr2 = 1;
w_data = 0;
reset = 1;
// Wait 100 ns for global reset to finish
#100;
reset = 0;
wr_en = 1; //escribo
w_addr = 0;//escribo en el reg 0
w_data = 25;//dato que escribo en reg 0
#5 wr_en = 0; //leo
#10
wr_en = 1; //escribo
w_addr = 1;//escribo en el reg 1
r_addr1 = 0;//leo el reg 0
r_addr2 = 1;//leo el reg 0
w_data = 50;//dato que escribo en reg 0
#5 wr_en = 0; //leo
#10
wr_en = 1; //escribo
w_addr = 2;//escribo en el reg 1
w_data = 100;//dato que escribo en reg 0
#5 wr_en = 0; //leo
#10
wr_en = 1; //escribo
w_addr = 3;//escribo en el reg 1
w_data = 200;//dato que escribo en reg 0
#5 wr_en = 0; //leo
r_addr1 = 2;//leo el reg 0
r_addr2 = 3;//leo el reg 0
// Add stimulus here
end
always //clock eterno
begin
#1
clk=~clk;
end
endmodule
|
//*****************************************************************************
// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: cmd_prbs_gen.v
// /___/ /\ Date Last Modified:
// \ \ / \ Date Created:
// \___\/\___\
//
//Device: Spartan6
//Design Name: DDR/DDR2/DDR3/LPDDR
//Purpose: This moduel use LFSR to generate random address, isntructions
// or burst_length.
//Reference:
//Revision History: 1.1 7/9/2009 Added condition to zero out the LSB address bits according to
// DWIDTH and FAMILY. 7/9/2009
// 1.2 11/8/2010 Fixed the PRBS Address generation.
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v4_0_cmd_prbs_gen #
(
parameter TCQ = 100,
parameter FAMILY = "SPARTAN6",
parameter MEM_BURST_LEN = 8,
parameter ADDR_WIDTH = 29,
parameter DWIDTH = 32,
parameter PRBS_CMD = "ADDRESS", // "INSTR", "BLEN","ADDRESS"
parameter PRBS_WIDTH = 64, // 64,15,20
parameter SEED_WIDTH = 32, // 32,15,4
parameter PRBS_EADDR_MASK_POS = 32'hFFFFD000,
parameter PRBS_SADDR_MASK_POS = 32'h00002000,
parameter PRBS_EADDR = 32'h00002000,
parameter PRBS_SADDR = 32'h00002000
)
(
input clk_i,
input prbs_seed_init, // when high the prbs_x_seed will be loaded
input clk_en,
input [SEED_WIDTH-1:0] prbs_seed_i,
output[SEED_WIDTH-1:0] prbs_o // generated address
);
wire[ADDR_WIDTH - 1:0] ZEROS;
reg [SEED_WIDTH - 1:0] prbs;
reg [PRBS_WIDTH :1] lfsr_q;
assign ZEROS = 'b0;
function integer logb2;
input integer number;
integer i;
begin
i = number;
for(logb2=1; i>0; logb2=logb2+1)
i = i >> 1;
end
endfunction
//
//**************************************************************
//####################################################################################################################
// #
// #
// 64 taps: [64,63,61,60]: {{8'b01011000}, {56'b0}} #
// upper 32 bits are loadable #
// #
//
//
// ........................................................................................
// ^ ^ ^ ^ |
// | ____ | ___ ___ | ___ | ___ ___ ___ |
// | | | |---|<- | | | | |---|<- | | |---|<- | |...| | | | | The first 32 bits are parallel loadable.
// ----|64 |<--|xor|<-- |63 |-->|62 |-|xor|<--|61 |<-|xor|<--|60 |...|33 |<--|1|<<--
// |___| --- |___| |___| --- |___| --- |___|...|___| |___|
//
//
// <<-- shifting --
//#####################################################################################################################
// use SRLC32E for lower 32 stages and 32 registers for upper 32 stages.
// we need to provide 30 bits addres. SRLC32 has only one bit output.
// address seed will be loaded to upper 32 bits.
//
// parallel load and serial shift out to LFSR during INIT time
generate
if(PRBS_CMD == "ADDRESS" && PRBS_WIDTH == 64)
begin :gen64_taps
always @ (posedge clk_i) begin
if(prbs_seed_init) begin//reset it to a known good state to prevent it locks up
lfsr_q <= #TCQ {31'b0,prbs_seed_i};
end else if(clk_en) begin
lfsr_q[64] <= #TCQ lfsr_q[64] ^ lfsr_q[63];
lfsr_q[63] <= #TCQ lfsr_q[62];
lfsr_q[62] <= #TCQ lfsr_q[64] ^ lfsr_q[61];
lfsr_q[61] <= #TCQ lfsr_q[64] ^ lfsr_q[60];
lfsr_q[60:2] <= #TCQ lfsr_q[59:1];
lfsr_q[1] <= #TCQ lfsr_q[64];
end
end
always @(lfsr_q[32:1]) begin
prbs = lfsr_q[32:1];
end
end
//endgenerate
//generate
else if(PRBS_CMD == "ADDRESS" && PRBS_WIDTH == 32)
begin :gen32_taps
always @ (posedge clk_i) begin
if(prbs_seed_init) begin //reset it to a known good state to prevent it locks up
lfsr_q <= #TCQ {prbs_seed_i};
end else if(clk_en) begin
lfsr_q[32:9] <= #TCQ lfsr_q[31:8];
lfsr_q[8] <= #TCQ lfsr_q[32] ^ lfsr_q[7];
lfsr_q[7] <= #TCQ lfsr_q[32] ^ lfsr_q[6];
lfsr_q[6:4] <= #TCQ lfsr_q[5:3];
lfsr_q[3] <= #TCQ lfsr_q[32] ^ lfsr_q[2];
lfsr_q[2] <= #TCQ lfsr_q[1] ;
lfsr_q[1] <= #TCQ lfsr_q[32];
end
end
integer i;
always @(lfsr_q[32:1]) begin
if (FAMILY == "SPARTAN6" ) begin // for 32 bits
for(i = logb2(DWIDTH) + 1; i <= SEED_WIDTH - 1; i = i + 1)
if(PRBS_SADDR_MASK_POS[i] == 1)
prbs[i] = PRBS_SADDR[i] | lfsr_q[i+1];
else if(PRBS_EADDR_MASK_POS[i] == 1)
prbs[i] = PRBS_EADDR[i] & lfsr_q[i+1];
else
prbs[i] = lfsr_q[i+1];
prbs[logb2(DWIDTH ) :0] = {logb2(DWIDTH ) + 1{1'b0}};
end
else begin
for(i = logb2(MEM_BURST_LEN) - 2; i <= SEED_WIDTH - 1; i = i + 1)
// for(i = 3; i <= SEED_WIDTH - 1; i = i + 1)
// BL8: 0,8
//BL4: incremnt by 4
// for(i = 3; i <= SEED_WIDTH - 1; i = i + 1)
if(PRBS_SADDR_MASK_POS[i] == 1)
prbs[i] = PRBS_SADDR[i] | lfsr_q[i+1];
else if(PRBS_EADDR_MASK_POS[i] == 0)
prbs[i] = PRBS_EADDR[i] & lfsr_q[i+1];
else
prbs[i] = 1'b0;// lfsr_q[i+1];
// 3 1
prbs[logb2(MEM_BURST_LEN)-3:0] = 'b0;//{logb2(MEM_BURST_LEN) -3{1'b0}};
// prbs[2:0] = {3{1'b0}};
end
end
end
//endgenerate
//////////////////////////////////////////////////////////////////////////
//####################################################################################################################
// #
// #
// 15 taps: [15,14]: #
// #
// #
//
//
// .............................................................
// ^ ^ . ^
// | ____ | ___ ___ ___ ___ ___ |
// | | | |---|<- | | | | | |...| | | | |
// ----|15 |<--|xor|<-- |14 |<--|13 |<--|12 |...|2 |<--|1 |<<--
// |___| --- |___| |___| |___|...|___| |___|
//
//
// <<-- shifting --
//#####################################################################################################################
//generate
// if(PRBS_CMD == "INSTR" | PRBS_CMD == "BLEN")
else
begin :gen20_taps
always @(posedge clk_i) begin
if(prbs_seed_init) begin//reset it to a known good state to prevent it locks up
lfsr_q <= #TCQ {5'b0,prbs_seed_i[14:0]};
end else if(clk_en) begin
lfsr_q[20] <= #TCQ lfsr_q[19];
lfsr_q[19] <= #TCQ lfsr_q[18];
lfsr_q[18] <= #TCQ lfsr_q[20] ^lfsr_q[17];
lfsr_q[17:2] <= #TCQ lfsr_q[16:1];
lfsr_q[1] <= #TCQ lfsr_q[20];
end
end
always @ (lfsr_q[SEED_WIDTH - 1:1], ZEROS) begin
prbs = {ZEROS[SEED_WIDTH - 1:6],lfsr_q[6:1]};
end
end
endgenerate
assign prbs_o = prbs;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SLEEP_SERGATE_PLV_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__SLEEP_SERGATE_PLV_FUNCTIONAL_PP_V
/**
* sleep_sergate_plv: connect vpr to virtpwr when not in sleep mode.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__sleep_sergate_plv (
VIRTPWR,
SLEEP ,
VPWR ,
VPB ,
VNB
);
// Module ports
output VIRTPWR;
input SLEEP ;
input VPWR ;
input VPB ;
input VNB ;
// Local signals
wire vgnd ;
wire pwrgood_pp0_out_VIRTPWR;
// Name Output Other arguments
pulldown pulldown0 (vgnd );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_VIRTPWR, VPWR, VPWR, vgnd );
bufif0 bufif00 (VIRTPWR , pwrgood_pp0_out_VIRTPWR, SLEEP);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__SLEEP_SERGATE_PLV_FUNCTIONAL_PP_V |
// Copyright (c) 2012-2013 Ludvig Strigeus
// This program is GPL Licensed. See COPYING for the full license.
// CLK is 24Mhz. MCLK is divided by two (12Mhz). 24Mhz divide by 16 produces SCLK.
// Divide by 48 produces LRCK.
// produce LRCK = 32kHz. We output 16-bit samples, but internally the DAC
// is in 24-bit mode. SCLK ratio is 48 * 32kHz.
module SoundDriver(input CLK, input [15:0] write_data, input write_left, input write_right,
output AUD_MCLK, output AUD_LRCK, output AUD_SCK, output AUD_SDIN);
reg lrck;
reg [15:0] leftbuf;
reg [15:0] rightbuf;
reg [16:0] currbuf;
reg [3:0] sclk_div;
reg [4:0] bitcnt_24; // Counts 0-23
wire [4:0] bitcnt_24_new = bitcnt_24 + 1;
always @(posedge CLK) begin
// Buffer one sample of each channel.
if (write_left) leftbuf <= write_data;
if (write_right) rightbuf <= write_data;
// Divide 24MHz by 16 to produce the SCLK frequency (48 * 32000) as well
// as the 12MHz MCLK frequency.
sclk_div <= sclk_div + 1;
// Output new bits on the falling edge of MCLK so that values are
// stable once MCLK rises.
if (sclk_div == 4'b1111) begin
// This runs at the SCLK frequency. Output next bit.
currbuf <= {currbuf[15:0], 1'b0};
bitcnt_24 <= bitcnt_24_new;
if (bitcnt_24_new[4:3] == 2'b11) begin
bitcnt_24[4:3] <= 2'b00; // 24 -> 0
lrck <= !lrck;
currbuf[15:0] <= lrck ? leftbuf : rightbuf;
end
end
end
assign AUD_MCLK = sclk_div[0];
assign AUD_SCK = 1; // Internal emphasis turned off
assign AUD_SDIN = currbuf[16];
assign AUD_LRCK = lrck;
endmodule
|
//Copyright (C) 1991-2007 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module altpcierd_icm_fifo_lkahd #(
parameter RAMTYPE = "RAM_BLOCK_TYPE=M512",
parameter USEEAB = "ON",
parameter ALMOST_FULL = 10,
parameter NUMWORDS = 16,
parameter WIDTHU = 4
)(
aclr,
clock,
data,
rdreq,
wrreq,
almost_empty,
almost_full,
empty,
full,
q,
usedw);
input aclr;
input clock;
input [107:0] data;
input rdreq;
input wrreq;
output almost_empty;
output almost_full;
output empty;
output full;
output [107:0] q;
output [WIDTHU-1:0] usedw;
wire sub_wire0;
wire [WIDTHU-1:0] sub_wire1;
wire sub_wire2;
wire sub_wire3;
wire [107:0] sub_wire4;
wire sub_wire5;
wire almost_full = sub_wire0;
wire [WIDTHU-1:0] usedw = sub_wire1[WIDTHU-1:0];
wire empty = sub_wire2;
wire almost_empty = sub_wire3;
wire [107:0] q = sub_wire4[107:0];
wire full = sub_wire5;
scfifo # (
.add_ram_output_register ( "ON" ),
.almost_empty_value ( 3 ),
.almost_full_value ( ALMOST_FULL ),
.intended_device_family ( "Stratix II GX"),
.lpm_hint ( RAMTYPE ),
.lpm_numwords ( NUMWORDS ),
.lpm_showahead ( "ON" ),
.lpm_type ( "scfifo" ),
.lpm_width ( 108 ),
.lpm_widthu ( WIDTHU ),
.overflow_checking ( "OFF" ),
.underflow_checking ( "OFF" ),
.use_eab ( USEEAB )
) scfifo_component (
.rdreq (rdreq),
.aclr (aclr),
.clock (clock),
.wrreq (wrreq),
.data (data),
.almost_full (sub_wire0),
.usedw (sub_wire1),
.empty (sub_wire2),
.almost_empty (sub_wire3),
.q (sub_wire4),
.full (sub_wire5)
// synopsys translate_off
,
.sclr ()
// synopsys translate_on
);
endmodule
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module tracking_camera_system_sdram_0_input_efifo_module (
// inputs:
clk,
rd,
reset_n,
wr,
wr_data,
// outputs:
almost_empty,
almost_full,
empty,
full,
rd_data
)
;
output almost_empty;
output almost_full;
output empty;
output full;
output [ 40: 0] rd_data;
input clk;
input rd;
input reset_n;
input wr;
input [ 40: 0] wr_data;
wire almost_empty;
wire almost_full;
wire empty;
reg [ 1: 0] entries;
reg [ 40: 0] entry_0;
reg [ 40: 0] entry_1;
wire full;
reg rd_address;
reg [ 40: 0] rd_data;
wire [ 1: 0] rdwr;
reg wr_address;
assign rdwr = {rd, wr};
assign full = entries == 2;
assign almost_full = entries >= 1;
assign empty = entries == 0;
assign almost_empty = entries <= 1;
always @(entry_0 or entry_1 or rd_address)
begin
case (rd_address) // synthesis parallel_case full_case
1'd0: begin
rd_data = entry_0;
end // 1'd0
1'd1: begin
rd_data = entry_1;
end // 1'd1
default: begin
end // default
endcase // rd_address
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
wr_address <= 0;
rd_address <= 0;
entries <= 0;
end
else
case (rdwr) // synthesis parallel_case full_case
2'd1: begin
// Write data
if (!full)
begin
entries <= entries + 1;
wr_address <= (wr_address == 1) ? 0 : (wr_address + 1);
end
end // 2'd1
2'd2: begin
// Read data
if (!empty)
begin
entries <= entries - 1;
rd_address <= (rd_address == 1) ? 0 : (rd_address + 1);
end
end // 2'd2
2'd3: begin
wr_address <= (wr_address == 1) ? 0 : (wr_address + 1);
rd_address <= (rd_address == 1) ? 0 : (rd_address + 1);
end // 2'd3
default: begin
end // default
endcase // rdwr
end
always @(posedge clk)
begin
//Write data
if (wr & !full)
case (wr_address) // synthesis parallel_case full_case
1'd0: begin
entry_0 <= wr_data;
end // 1'd0
1'd1: begin
entry_1 <= wr_data;
end // 1'd1
default: begin
end // default
endcase // wr_address
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module tracking_camera_system_sdram_0 (
// inputs:
az_addr,
az_be_n,
az_cs,
az_data,
az_rd_n,
az_wr_n,
clk,
reset_n,
// outputs:
za_data,
za_valid,
za_waitrequest,
zs_addr,
zs_ba,
zs_cas_n,
zs_cke,
zs_cs_n,
zs_dq,
zs_dqm,
zs_ras_n,
zs_we_n
)
;
output [ 15: 0] za_data;
output za_valid;
output za_waitrequest;
output [ 11: 0] zs_addr;
output [ 1: 0] zs_ba;
output zs_cas_n;
output zs_cke;
output zs_cs_n;
inout [ 15: 0] zs_dq;
output [ 1: 0] zs_dqm;
output zs_ras_n;
output zs_we_n;
input [ 21: 0] az_addr;
input [ 1: 0] az_be_n;
input az_cs;
input [ 15: 0] az_data;
input az_rd_n;
input az_wr_n;
input clk;
input reset_n;
wire [ 23: 0] CODE;
reg ack_refresh_request;
reg [ 21: 0] active_addr;
wire [ 1: 0] active_bank;
reg active_cs_n;
reg [ 15: 0] active_data;
reg [ 1: 0] active_dqm;
reg active_rnw;
wire almost_empty;
wire almost_full;
wire bank_match;
wire [ 7: 0] cas_addr;
wire clk_en;
wire [ 3: 0] cmd_all;
wire [ 2: 0] cmd_code;
wire cs_n;
wire csn_decode;
wire csn_match;
wire [ 21: 0] f_addr;
wire [ 1: 0] f_bank;
wire f_cs_n;
wire [ 15: 0] f_data;
wire [ 1: 0] f_dqm;
wire f_empty;
reg f_pop;
wire f_rnw;
wire f_select;
wire [ 40: 0] fifo_read_data;
reg [ 11: 0] i_addr;
reg [ 3: 0] i_cmd;
reg [ 2: 0] i_count;
reg [ 2: 0] i_next;
reg [ 2: 0] i_refs;
reg [ 2: 0] i_state;
reg init_done;
reg [ 11: 0] m_addr /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;
reg [ 1: 0] m_bank /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;
reg [ 3: 0] m_cmd /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;
reg [ 2: 0] m_count;
reg [ 15: 0] m_data /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON ; FAST_OUTPUT_ENABLE_REGISTER=ON" */;
reg [ 1: 0] m_dqm /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;
reg [ 8: 0] m_next;
reg [ 8: 0] m_state;
reg oe /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_ENABLE_REGISTER=ON" */;
wire pending;
wire rd_strobe;
reg [ 2: 0] rd_valid;
reg [ 13: 0] refresh_counter;
reg refresh_request;
wire rnw_match;
wire row_match;
wire [ 23: 0] txt_code;
reg za_cannotrefresh;
reg [ 15: 0] za_data /* synthesis ALTERA_ATTRIBUTE = "FAST_INPUT_REGISTER=ON" */;
reg za_valid;
wire za_waitrequest;
wire [ 11: 0] zs_addr;
wire [ 1: 0] zs_ba;
wire zs_cas_n;
wire zs_cke;
wire zs_cs_n;
wire [ 15: 0] zs_dq;
wire [ 1: 0] zs_dqm;
wire zs_ras_n;
wire zs_we_n;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign {zs_cs_n, zs_ras_n, zs_cas_n, zs_we_n} = m_cmd;
assign zs_addr = m_addr;
assign zs_cke = clk_en;
assign zs_dq = oe?m_data:{16{1'bz}};
assign zs_dqm = m_dqm;
assign zs_ba = m_bank;
assign f_select = f_pop & pending;
assign f_cs_n = 1'b0;
assign cs_n = f_select ? f_cs_n : active_cs_n;
assign csn_decode = cs_n;
assign {f_rnw, f_addr, f_dqm, f_data} = fifo_read_data;
tracking_camera_system_sdram_0_input_efifo_module the_tracking_camera_system_sdram_0_input_efifo_module
(
.almost_empty (almost_empty),
.almost_full (almost_full),
.clk (clk),
.empty (f_empty),
.full (za_waitrequest),
.rd (f_select),
.rd_data (fifo_read_data),
.reset_n (reset_n),
.wr ((~az_wr_n | ~az_rd_n) & !za_waitrequest),
.wr_data ({az_wr_n, az_addr, az_wr_n ? 2'b0 : az_be_n, az_data})
);
assign f_bank = {f_addr[21],f_addr[8]};
// Refresh/init counter.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
refresh_counter <= 10000;
else if (refresh_counter == 0)
refresh_counter <= 1562;
else
refresh_counter <= refresh_counter - 1'b1;
end
// Refresh request signal.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
refresh_request <= 0;
else if (1)
refresh_request <= ((refresh_counter == 0) | refresh_request) & ~ack_refresh_request & init_done;
end
// Generate an Interrupt if two ref_reqs occur before one ack_refresh_request
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
za_cannotrefresh <= 0;
else if (1)
za_cannotrefresh <= (refresh_counter == 0) & refresh_request;
end
// Initialization-done flag.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
init_done <= 0;
else if (1)
init_done <= init_done | (i_state == 3'b101);
end
// **** Init FSM ****
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
i_state <= 3'b000;
i_next <= 3'b000;
i_cmd <= 4'b1111;
i_addr <= {12{1'b1}};
i_count <= {3{1'b0}};
end
else
begin
i_addr <= {12{1'b1}};
case (i_state) // synthesis parallel_case full_case
3'b000: begin
i_cmd <= 4'b1111;
i_refs <= 3'b0;
//Wait for refresh count-down after reset
if (refresh_counter == 0)
i_state <= 3'b001;
end // 3'b000
3'b001: begin
i_state <= 3'b011;
i_cmd <= {{1{1'b0}},3'h2};
i_count <= 1;
i_next <= 3'b010;
end // 3'b001
3'b010: begin
i_cmd <= {{1{1'b0}},3'h1};
i_refs <= i_refs + 1'b1;
i_state <= 3'b011;
i_count <= 7;
// Count up init_refresh_commands
if (i_refs == 3'h1)
i_next <= 3'b111;
else
i_next <= 3'b010;
end // 3'b010
3'b011: begin
i_cmd <= {{1{1'b0}},3'h7};
//WAIT til safe to Proceed...
if (i_count > 1)
i_count <= i_count - 1'b1;
else
i_state <= i_next;
end // 3'b011
3'b101: begin
i_state <= 3'b101;
end // 3'b101
3'b111: begin
i_state <= 3'b011;
i_cmd <= {{1{1'b0}},3'h0};
i_addr <= {{2{1'b0}},1'b0,2'b00,3'h3,4'h0};
i_count <= 4;
i_next <= 3'b101;
end // 3'b111
default: begin
i_state <= 3'b000;
end // default
endcase // i_state
end
end
assign active_bank = {active_addr[21],active_addr[8]};
assign csn_match = active_cs_n == f_cs_n;
assign rnw_match = active_rnw == f_rnw;
assign bank_match = active_bank == f_bank;
assign row_match = {active_addr[20 : 9]} == {f_addr[20 : 9]};
assign pending = csn_match && rnw_match && bank_match && row_match && !f_empty;
assign cas_addr = f_select ? { {4{1'b0}},f_addr[7 : 0] } : { {4{1'b0}},active_addr[7 : 0] };
// **** Main FSM ****
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
m_state <= 9'b000000001;
m_next <= 9'b000000001;
m_cmd <= 4'b1111;
m_bank <= 2'b00;
m_addr <= 12'b000000000000;
m_data <= 16'b0000000000000000;
m_dqm <= 2'b00;
m_count <= 3'b000;
ack_refresh_request <= 1'b0;
f_pop <= 1'b0;
oe <= 1'b0;
end
else
begin
f_pop <= 1'b0;
oe <= 1'b0;
case (m_state) // synthesis parallel_case full_case
9'b000000001: begin
//Wait for init-fsm to be done...
if (init_done)
begin
//Hold bus if another cycle ended to arf.
if (refresh_request)
m_cmd <= {{1{1'b0}},3'h7};
else
m_cmd <= 4'b1111;
ack_refresh_request <= 1'b0;
//Wait for a read/write request.
if (refresh_request)
begin
m_state <= 9'b001000000;
m_next <= 9'b010000000;
m_count <= 1;
active_cs_n <= 1'b1;
end
else if (!f_empty)
begin
f_pop <= 1'b1;
active_cs_n <= f_cs_n;
active_rnw <= f_rnw;
active_addr <= f_addr;
active_data <= f_data;
active_dqm <= f_dqm;
m_state <= 9'b000000010;
end
end
else
begin
m_addr <= i_addr;
m_state <= 9'b000000001;
m_next <= 9'b000000001;
m_cmd <= i_cmd;
end
end // 9'b000000001
9'b000000010: begin
m_state <= 9'b000000100;
m_cmd <= {csn_decode,3'h3};
m_bank <= active_bank;
m_addr <= active_addr[20 : 9];
m_data <= active_data;
m_dqm <= active_dqm;
m_count <= 2;
m_next <= active_rnw ? 9'b000001000 : 9'b000010000;
end // 9'b000000010
9'b000000100: begin
// precharge all if arf, else precharge csn_decode
if (m_next == 9'b010000000)
m_cmd <= {{1{1'b0}},3'h7};
else
m_cmd <= {csn_decode,3'h7};
//Count down til safe to Proceed...
if (m_count > 1)
m_count <= m_count - 1'b1;
else
m_state <= m_next;
end // 9'b000000100
9'b000001000: begin
m_cmd <= {csn_decode,3'h5};
m_bank <= f_select ? f_bank : active_bank;
m_dqm <= f_select ? f_dqm : active_dqm;
m_addr <= cas_addr;
//Do we have a transaction pending?
if (pending)
begin
//if we need to ARF, bail, else spin
if (refresh_request)
begin
m_state <= 9'b000000100;
m_next <= 9'b000000001;
m_count <= 2;
end
else
begin
f_pop <= 1'b1;
active_cs_n <= f_cs_n;
active_rnw <= f_rnw;
active_addr <= f_addr;
active_data <= f_data;
active_dqm <= f_dqm;
end
end
else
begin
//correctly end RD spin cycle if fifo mt
if (~pending & f_pop)
m_cmd <= {csn_decode,3'h7};
m_state <= 9'b100000000;
end
end // 9'b000001000
9'b000010000: begin
m_cmd <= {csn_decode,3'h4};
oe <= 1'b1;
m_data <= f_select ? f_data : active_data;
m_dqm <= f_select ? f_dqm : active_dqm;
m_bank <= f_select ? f_bank : active_bank;
m_addr <= cas_addr;
//Do we have a transaction pending?
if (pending)
begin
//if we need to ARF, bail, else spin
if (refresh_request)
begin
m_state <= 9'b000000100;
m_next <= 9'b000000001;
m_count <= 2;
end
else
begin
f_pop <= 1'b1;
active_cs_n <= f_cs_n;
active_rnw <= f_rnw;
active_addr <= f_addr;
active_data <= f_data;
active_dqm <= f_dqm;
end
end
else
begin
//correctly end WR spin cycle if fifo empty
if (~pending & f_pop)
begin
m_cmd <= {csn_decode,3'h7};
oe <= 1'b0;
end
m_state <= 9'b100000000;
end
end // 9'b000010000
9'b000100000: begin
m_cmd <= {csn_decode,3'h7};
//Count down til safe to Proceed...
if (m_count > 1)
m_count <= m_count - 1'b1;
else
begin
m_state <= 9'b001000000;
m_count <= 1;
end
end // 9'b000100000
9'b001000000: begin
m_state <= 9'b000000100;
m_addr <= {12{1'b1}};
// precharge all if arf, else precharge csn_decode
if (refresh_request)
m_cmd <= {{1{1'b0}},3'h2};
else
m_cmd <= {csn_decode,3'h2};
end // 9'b001000000
9'b010000000: begin
ack_refresh_request <= 1'b1;
m_state <= 9'b000000100;
m_cmd <= {{1{1'b0}},3'h1};
m_count <= 7;
m_next <= 9'b000000001;
end // 9'b010000000
9'b100000000: begin
m_cmd <= {csn_decode,3'h7};
//if we need to ARF, bail, else spin
if (refresh_request)
begin
m_state <= 9'b000000100;
m_next <= 9'b000000001;
m_count <= 1;
end
else //wait for fifo to have contents
if (!f_empty)
//Are we 'pending' yet?
if (csn_match && rnw_match && bank_match && row_match)
begin
m_state <= f_rnw ? 9'b000001000 : 9'b000010000;
f_pop <= 1'b1;
active_cs_n <= f_cs_n;
active_rnw <= f_rnw;
active_addr <= f_addr;
active_data <= f_data;
active_dqm <= f_dqm;
end
else
begin
m_state <= 9'b000100000;
m_next <= 9'b000000001;
m_count <= 1;
end
end // 9'b100000000
// synthesis translate_off
default: begin
m_state <= m_state;
m_cmd <= 4'b1111;
f_pop <= 1'b0;
oe <= 1'b0;
end // default
// synthesis translate_on
endcase // m_state
end
end
assign rd_strobe = m_cmd[2 : 0] == 3'h5;
//Track RD Req's based on cas_latency w/shift reg
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
rd_valid <= {3{1'b0}};
else
rd_valid <= (rd_valid << 1) | { {2{1'b0}}, rd_strobe };
end
// Register dq data.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
za_data <= 0;
else
za_data <= zs_dq;
end
// Delay za_valid to match registered data.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
za_valid <= 0;
else if (1)
za_valid <= rd_valid[2];
end
assign cmd_code = m_cmd[2 : 0];
assign cmd_all = m_cmd;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
initial
begin
$write("\n");
$write("This reference design requires a vendor simulation model.\n");
$write("To simulate accesses to SDRAM, you must:\n");
$write(" - Download the vendor model\n");
$write(" - Install the model in the system_sim directory\n");
$write(" - `include the vendor model in the the top-level system file,\n");
$write(" - Instantiate sdram simulation models and wire them to testbench signals\n");
$write(" - Be aware that you may have to disable some timing checks in the vendor model\n");
$write(" (because this simulation is zero-delay based)\n");
$write("\n");
end
assign txt_code = (cmd_code == 3'h0)? 24'h4c4d52 :
(cmd_code == 3'h1)? 24'h415246 :
(cmd_code == 3'h2)? 24'h505245 :
(cmd_code == 3'h3)? 24'h414354 :
(cmd_code == 3'h4)? 24'h205752 :
(cmd_code == 3'h5)? 24'h205244 :
(cmd_code == 3'h6)? 24'h425354 :
(cmd_code == 3'h7)? 24'h4e4f50 :
24'h424144;
assign CODE = &(cmd_all|4'h7) ? 24'h494e48 : txt_code;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : Graphics core top level
// File : graph_core.v
// Author : Jim MacLeod
// Created : 14-May-2011
// RCS File : $Source:$
// Status : $Id:$
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
// This is the top level of the Guru core graphics logic.
// This file encompasses the IP for the Guru series of Display controllers.
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
// U_HBI hbi_top Host interface (PCI)
// U_VGA vga_top IBM(TM) Compatible VGA core
// U_DE de_top Drawing engine
// U_DLP dlp_top Display List Processor
// U_DDR3 DDR3 DDR3 Memory interface
// u_crt crt_top Display interface
// u_ramdac ramdac Digital DAC
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 10ps
// Include the VGA core
`define INCLUDE_VGA 1
// Set to include 3D, otherwise will build 2D only
`define CORE_3D 1
// Use internal PLLs
`define PLL_INT 1
// Defined in Quartus and build file.
// 128 bit memory bus
// `define BYTE16
// 64 bit memory bus
//`define BYTE8
// 32 bit memory bus
//`define BYTE4
// To compile the internal FIFO's as RAM, use the following:
// `define RAM_FIFO_104x128 1
// `define RAM_FIFO_271x128 1
// TEMP REMOVE, `define RAM_FIFO_36x128 1
//`define RAM_FIFO_100x128 1
//`define RAM_FIFO_271x128 1
//`define RAM_FIFO_57x64 1
//`define RAM_FIFO_32x128a 1
//`define RAM_FIFO_32x64a 1
//`define RAM_SFIFO_39x128 1
//`define RAM_SFIFO_65x128 1
// DEFINES FOR CHIP CONFIGURATION.
// `define USE_EXT_PLL 1;
// `define USE_MC_64B 1;
// These defines replace the old straps that we used - inverted externally
//`define PCI_CLASS 1'b1; // Not VGA
`define PCI_CLASS 1'b0; // VGA
`define WINDOW_SIZE 2'b11;
`define EPROM_SIZE 1'b1;
`define MEM_TYPE 1'b1; // SDRAM/SGRAM
// `define MEM_TYPE 2'b11; // SDRAM/SGRAM
`define MEM_DENSITY 2'b11; // How much memory we have (32MB SDRAM)
// `define MEM_DENSITY 2'b10; // How much memory we have (16MB SDRAM)
`define IDAC_ENABLE 1'b1;
`define PCI 1'b1;
//`define SBSYS_ID_STRAP 6'h1; // 8MB
//`define SBSYS_ID_STRAP 6'h3; // 16MB
`define SBSYS_ID_STRAP 6'h7; // 32 MB
// Used to identify FPGA firmware version.
`define SBVEND_SEL_STRAP 1'b1;
// `define SBVEND_ID_STRAP 16'h010B;
// Added Signal TAP.
// `define SBVEND_ID_STRAP 16'h011B;
// Add BT clock in out.
// `define SBVEND_ID_STRAP 16'h012B;
// Remove BT clock in out.
// `define SBVEND_ID_STRAP 16'h013B;
// Fix 2D/3D switching, fixed NO AREA triangles.
// `define SBVEND_ID_STRAP 16'h104B;
// Fix 2D/3D switching, fixed NO AREA triangles.
// Change to PAL clock.
// `define SBVEND_ID_STRAP 16'h105B;
// Fixed 16BPP 3D bug.
// `define SBVEND_ID_STRAP 16'h200B;
// First release with textures, Z still not working, disabled.
// `define SBVEND_ID_STRAP 16'h300B;
// `define SBVEND_ID_STRAP 16'h302B;
// Fixed Hang in 2D core, pcbusy was disconnected.
// `define SBVEND_ID_STRAP 16'h303B;
// Fixed 3D/2D switching and Z buffer.
// `define SBVEND_ID_STRAP 16'h306B;
// `define SBVEND_ID_STRAP 16'h306B;
// `define SBVEND_ID_STRAP 16'h308B;
// Fixed Z-buffer and corruption, miss wired bit in pixel cache.
// `define SBVEND_ID_STRAP 16'h312B;
// `define SBVEND_ID_STRAP 16'h313B;
// Fixed filtering.
// `define SBVEND_ID_STRAP 16'h314B;
// Fixed 16 bit texturing problem.
// `define SBVEND_ID_STRAP 16'h315B;
// Fixed Float rounding problem in multiplier.
// `define SBVEND_ID_STRAP 16'h316B;
// Fixed texturing black spots and noise problem.
// `define SBVEND_ID_STRAP 16'h317B;
// Fixed CRT lock out problem.
// `define SBVEND_ID_STRAP 16'h318F;
// Fixed 780x780 problems.
// `define SBVEND_ID_STRAP 16'h319B;
// Fixed Resolution clock problem and mipmaps.
// `define SBVEND_ID_STRAP 16'h320B;
// Fixed Timing issue with mipmaps.
// `define SBVEND_ID_STRAP 16'h321B;
// Fixed another Timing issue with mipmaps.
// `define SBVEND_ID_STRAP 16'h322B;
// Fixed Blending.
// Fixed Color Keying
// Changed MIP Mapping to T2R4 Style LOD calculations.
// Set 780x780 pixel clock to 43.5MHz.
//`define SBVEND_ID_STRAP 16'h323B;
// Increased DDR3 Refresh speed..5MHz.
// `define SBVEND_ID_STRAP 16'h324B;
// Fixed 2D clipping problem.
// // This was causing texture corruption.
// `define SBVEND_ID_STRAP 16'h325B;
// Added Z cache, fixed setup engine/execution engine pipe line.
// Z Cache still has a slight problem.
// `define SBVEND_ID_STRAP 16'h326B;
// Continue performance work.
// `define SBVEND_ID_STRAP 16'h327B;
// Increased Memory speed to 333.
// FIxed Z always, should not read.
// Removed writes with all bytes masked.
// `define SBVEND_ID_STRAP 16'h328B;
// Change the DLP to request up to 8 pages.
// `define SBVEND_ID_STRAP 16'h329B;
// Just removed all signal tap.
// `define SBVEND_ID_STRAP 16'h330B;
// Changed mimaping and filtering.
// Still have ants.
// `define SBVEND_ID_STRAP 16'h331B;
// Added 8 more bits of precision for
// X, Y inputs to the interpolator.
// `define SBVEND_ID_STRAP 16'h332B;
// Fixed LOD calculations.
// `define SBVEND_ID_STRAP 16'h333B;
// Fixed LOD calculations.
// `define SBVEND_ID_STRAP 16'h336B;
// Fixed LOD negative U, V calculations.
// `define SBVEND_ID_STRAP 16'h338B;
// Fixed extended floating point in LOD U, V calculations.
// `define SBVEND_ID_STRAP 16'h339B;
// Fixed some timing problems, set MC clock to 300MHz.
// `define SBVEND_ID_STRAP 16'h340B;
// Change ARGB and FRsGsBs to fixed point
// interpolators, to save logic.
// `define SBVEND_ID_STRAP 16'h341B;
// Fixed Z/blending problem.
// `define SBVEND_ID_STRAP 16'h342B;
// Fixed Clipping Problem.
// `define SBVEND_ID_STRAP 16'h343B;
// Fixed Overflow problem.
//`define SBVEND_ID_STRAP 16'h344B;
// Fixed Overflow problem in PAL mode.
// Removed VGA core.
// `define SBVEND_ID_STRAP 16'h345B;
// Fixed black lines on left side.
// Connected BT_CLK to pixclk.
// `define SBVEND_ID_STRAP 16'h346B;
// Fix crt lock out during BLT.
// `define SBVEND_ID_STRAP 16'h347B;
// Fix DLP text mode.
// `define SBVEND_ID_STRAP 16'h348B;
// Removed Address extensions on DLP.
// NT driver was not clearing these and was causing
// corruption and hangs.
// `define SBVEND_ID_STRAP 16'h349B;
// Not Released.
// `define SBVEND_ID_STRAP 16'h350B;
// Fixed flashing one problem.
// DLP need to wait for cache.
// `define SBVEND_ID_STRAP 16'h351B;
// XXXXXXXXXXXXXXXXXXXXXXXXXX.
// `define SBVEND_ID_STRAP 16'h352B;
// Removed many warnings.
// `define SBVEND_ID_STRAP 16'h353B;
// `define SBVEND_ID_STRAP 16'h354B (NOT USED);
// Fixed triangles outside of window in the ATP.
// `define SBVEND_ID_STRAP 16'h355B;
// Fixed Z buffer problem which shows up in ATP.
// `define SBVEND_ID_STRAP 16'h356B;
//
////////////////////////////////////////////////////////////////////
//
// Major Release 359B.
//
// 1) Replace Clock synthesizer table with true clock generator.
// Using Altera PLL reconfiguration.
// 2) Fixed register read back and defaults.
// 3) Added 3D line command.
// 4) Fixed problem with display controller at 32 BPP.
// 5) Fixed problem with specular.
// 6) Fixed problem with TOM 2D benchmark.
//
`define SBVEND_ID_STRAP 16'h359B;
`define PAL_CLOCK 1
// Turn on VGA generated refreshes.
// `define VGA_REF 1
`ifdef CORE_3D
`include "define_3d.h"
`endif
module graph_core
#(parameter BYTES = 16,
parameter DE_ADDR = 32'h800, // DE Reg base address.
parameter XYW_ADDR = 32'h1000_0000 // DE Cache base address.
)
(
// PCI I/O
input hclock, // host clock input port
input hresetn, // host reset input port
input pframen, // address strobe/FRAME signal
input pirdyn, // Initiator ready signal
inout ptrdyn, // Target ready
inout pdevseln, // Device select
input pidsel, // Initialization Device Select
inout pintan, // Interrupt output
inout pstopn, // Stop output
inout ppar, // Parity output [31:0]
input preqn, // pci request to arbiter
input pgnntn, // pci grant from external arbiter
input [3:0] pcben, // Command, byte enable
inout [31:00] pad, // host address and data port
// Serial BIOS Interface.
input bios_rdat, // Serial bios input data.
output bios_clk, // Serial bios clock.
output bios_csn, // Serial bios chip select.
output bios_wrn, // Serial bios write enable.
output bios_hld, // Serial bios hold.
output bios_wdat, // Serial bios write data.
// Reference Clock
input pll_xbuf, // PLL XBUF input (Pixel Clock Ref).
input pll_xbuf1, // XBUF1, (DDR3 Clock Ref).
inout pll_sclk,
inout pll_sdat,
//
// Signals for the DVO,
//
output dvo_dclk, // DVI Transmitter Clock.
output dvo_hsync, // DVI Hsync out.
output dvo_vsync, // DVI Vsync or Csync out.
output dvo_de, // DVI Data Enable.
output [23:0] dvo_data, /* DVI/DAC Data output.
* For Single Edge DVI Data output.
* For Dual Edge DVI Data output.
* For Dual Edge Dual link DVI Data output.
* For DAC {RED[7:0], GRN[7:0], BLU[7:0]} = DVI_D[23:0].
*/
output dvo_bsel_scl, // I2C Clock
inout dvo_dsel_sda, // I2C Data
inout ddc_scl, // DDC2 "clock"
inout ddc_sda, // Datain from DDC1 compatible monitor
output dac_psaven, // Power Save Signal.
output dac_cblankn, // Composit Blank to DAC.
output dac_csyncn, // Composit Sync to DAC.
output dac_sog, // Sync On Green Output.
//
// Additional Signals for the BT868, PAL encoder.
//
input bt_clko, // Clock input from the BT868 (37.5/29.5) MHz.
output bt_clki, // Clock output to the BT868.
input bt_field, // Field input from the BT868.
output bt_hsyncn, // Hsync input from the BT868.
output bt_vsyncn, // Vsync input from the BT868.
output bt_blankn, // Blank input from the BT868.
output bt_pal, // 1 = PAL, 0 = NTSC.
//
// Jumper Settings for testing or internal configuration
// Special Function Pins.
//
input bt_clk_sel, // Selects between BT clock and 25MHz clock input.
input mb_32_sel, // Select 32MB of Memory.
input vga_en, // VGA class_strap enable/disable VGA.
input dual_enn, // Dual DVI Enable.
input m66_en, // PCI 66MHz Enable.
output ledn, // General purpose LED output.
// Test Pins which go to the Mictor Conectors.
input mictor_clke,
input mictor_clko,
input [15:0] mictor_de,
input [15:0] mictor_do,
output [19:0] gpio_3v,
// Memory outputs
output mem_odt,
output mem_cs_n,
output mem_cke,
output [13:0] mem_addr,
output [2:0] mem_ba,
output mem_ras_n,
output mem_cas_n,
output mem_we_n,
// output [BYTES/4-1:0] mem_dm,
inout mem_clk,
inout mem_clk_n,
output mem_reset_n,
`ifdef RTL_SIM
output [3:0] mem_dm,
inout [31:0] mem_dq,
inout [3:0] mem_dqs,
inout [3:0] mem_dqsn
`else
output [7:0] mem_dm,
inout [63:0] mem_dq,
inout [7:0] mem_dqs,
inout [7:0] mem_dqsn
`endif
);
// `include "define_2d"
wire bios_rdat_i;
wire hb_clk;
assign bios_wrn = 1'b0;
reg [25:0] LED_COUNTER;
always @(posedge hb_clk) LED_COUNTER <= LED_COUNTER + 26'h1;
assign ledn = LED_COUNTER[25];
wire bb_rstn; // Global soft reset
wire de_clk;
wire pll_sdat_oe;
wire pll_sclk_oe;
// From Drawing Engine
wire de_busy;
wire de_mem_read; // Read or write indicator to MC
wire de_mem_rmw; // Read modify write on a write
wire [31:0] de_address; // linear address
wire [3:0] de_wcnt; // Number of pages to request
wire [BYTES-1:0] de_pix_msk; // byte mask for data
wire [(BYTES*8)-1:0] de_pdo; // Data to MC
wire [(BYTES*4)-1:0] de_ado; // Data to MC
wire [1:0] de_ps_2; // Pixel Size
wire de_pc_empty; // empty flag from the PC FIFO
wire [3:0] de_bsrcr; // Source Blending Register
wire [2:0] de_bdstr; // Destination Blending Register
wire de_blend_en; // Blending Enabled
wire [1:0] de_blend_reg_en;// Blending Enabled
wire [7:0] de_bsrc_alpha; // Source Alpha register
wire [7:0] de_bdst_alpha; // Destination Alpha register
wire [3:0] de_rop; // de raster op select
wire [31:0] de_kcol; // key color
wire [2:0] de_kcnt; // keying control
wire de_pc_pop;
wire line_actv_4;
wire [6:0] mem_offset;
// Dual port ram interface for ded_ca_top.v
`ifdef BYTE16
wire [3:0] ca_enable;
`elsif BYTE8
wire [1:0] ca_enable;
`else
wire ca_enable;
`endif
wire [3:0] ca_byteena;
wire [4:0] hb_ram_addr;
wire de_push;
wire [(BYTES*8)-1:0] mc_read_data;
wire [4:0] ca_ram_addr0;
wire [4:0] ca_ram_addr1;
wire [(BYTES*8)-1:0] hb_dout_ram;
wire [(BYTES*8)-1:0] ca_dout0;
wire [(BYTES*8)-1:0] ca_dout1;
wire [4:0] z_ctrl_4;
wire [31:0] z_address_4;
wire [(BYTES*8)-1:0] z_out;
// From DLP
wire [8:2] dlp_adr; // Drawing engine address from DLP
wire de_wstrb; // DLP write strobe to DE
wire de_csn; // DLP chip select for DE
wire [3:0] de_ben; // BEN's from DLP to DE
wire [31:0] de_data; // Data from DLP to DE
wire [53:0] pp_rdback; // DLP register readback to host
wire [27:0] dlp_addr; // DLP address to MC
wire dlp_sen;
wire dlp_req; // DLP memory Controller Request
wire [4:0] dlp_wcnt; // DLP memory Controller Word Count.
wire [31:3] dlp_src_addr;
wire [25:3] dlp_dst_addr;
// From Memory Controller
wire de_popen;
wire de_last;
wire de_last4;
wire dlp_push;
wire dlp_mc_done;
wire dlp_ready;
wire [1:0] dqinclk;
wire mc_busy; // Memory controller is busy
wire mc_busy2; // Memory controller is busy
wire hb_de_busy; // DE busy to host
wire [7:0] ssro;
wire dis_push;
wire dis_rdy;
wire hb_pop;
wire hb_push;
wire hb_mem_rdy;
// Host interface signals
wire [13:2] hb_adr_de; // Drawing engine address from host
wire [8:2] hb_adr; // Host address
wire [31:0] hb_din; // Host data
wire [3:0] hb_ben; // Host bus byte enables
wire hb_write; // Host write enable
wire hb_wstrb; // Write Strobe to the DLP
wire csn_de_xyw; // XY Windows Chip Select
wire csn_de; // Drawing engine chip select
wire [31:0] de_hdout; // host bus read back data
wire [31:0] de_drout; // Drawing engine registers to HB
wire dlp_hold_start; // Hold the APB from writing the DLP
wire [3:0] sorg_upper; // Upper 4 bits of the text sorg
wire [2:0] de_hdf; // Host Data Format
wire ca_busy;
wire de_clp; // Clip indicator
wire de_deb; // Drawing engine busy
wire de_ddint_tog;
wire de_clint_tog;
wire [31:0] hb_ldata;
wire [31:0] vga_data;
wire vga_ack;
wire vga_ready_n;
wire csn_glb; // Global register Chip Select
wire [22:0] hb_org; // Host origin to MC
wire [127:0] hb_pdo; // Host data to MC
wire [15:0] hb_pix_msk; // Host Mask to MC
wire hb_mem_read; // Read or write to MC
wire hb_mem_req; // Issue a memory request to the MC
wire [1:0] hst_mw_addr;
wire phy_clk;
// assign mb_32_sel = 1'b1; // de_clk; // pll_xbuf;
// Wires - Once were straps
// wire [1:0] window_size_strap = {t2r4_mode, mb_32_sel};
wire [1:0] window_size_strap = 2'b11;
wire eprom_strap = `EPROM_SIZE
wire class_strap = vga_en;
wire [1:0] mem_dens_strap = 2'b11; // {t2r4_mode, mb_32_sel};
wire idac_strap = `IDAC_ENABLE
wire mem_type_strap = `MEM_TYPE
wire hbt_strap = `PCI
wire sbvend_sel_strap = `SBVEND_SEL_STRAP
wire [15:0] sbvend_id_strap = `SBVEND_ID_STRAP
wire [5:0] sbsys_id_strap = 6'h7; // (t2r4_mode & mb_32_sel) ? 6'h7 : // 32MBytes.
// (t2r4_mode & ~mb_32_sel) ? 6'h3 : // 16MBytes.
// (~t2r4_mode & mb_32_sel) ? 6'h9 : // 256MBytes (FIX ME).
// 6'h8; // 128MBytes (FIX ME).
// Wires - PCI
// wire frame_out_n;
// wire frame_oe_n;
// wire irdy_out_n;
// wire irdy_oe_n;
wire hb_ctrl_oe_n;
wire trdy_out_n;
wire devsel_oe_n;
wire devsel_out_n;
wire intrp_oe_n;
wire intrp_out_n;
wire par32_oe_n;
wire stop_out_n;
wire req_n;
wire c_be_oe_n;
wire par32_out;
wire ad_oe32_n;
wire [31:0] ad_out;
// MC Avalon Interfaces
wire local_ready;
wire [BYTES*8-1:0] local_rdata;
wire local_rdata_valid;
wire [24:0] local_address;
wire local_write_req;
wire local_read_req;
wire local_burstbegin;
wire [BYTES*8-1:0] local_wdata;
wire [BYTES-1:0] local_be;
wire [5:0] local_size;
wire init_done;
wire ddc_clk_0, ddc_clk_1;
wire ddc_en_0, ddc_en_1;
wire ddc_dat_dout_0, ddc_dat_dout_1;
wire pipeline_active;
wire pll_sdat_int, pll_sclk_int;
wire [11:0] crt_ptch;
wire [31:0] vga_ldata;
wire [22:0] vga_laddr;
wire [3:0] vga_lbe;
wire [31:0] mc_config2reg; // Configuration REG 2
// Wires - Parallel Port
wire [15:0] P_A; // Peripheral Address.
wire p_d_oe_n;
wire [7:0] p_d_out;
wire [1:0] bpp; // Bits per pixel
wire p_update;
wire [23:0] pll_params;
wire [1:0] int_fs;
wire [2:0] pixclksel;
wire [7:0] red;
wire [7:0] grn;
wire [7:0] blu;
wire pixclk;
wire [7:0] idac_rd_data; // Read data from ramdac registers
wire [23:0] pd_toidac; // Pixel data to internal RAMDAC
wire [13:0] hactive_regist;
wire [1:0] sereg;
wire [9:0] dis_x; // Display controller X address
wire [11:0] dis_y; // Display controller Y address
wire [4:0] dis_page; // Display controller page count upto 32
// From the VGA
wire [31:0] hst_data_out; // VGA read data for host
wire [2:0] vga_stat; // Decoder status
wire vga_push; // VGA read data push
wire vga_ready; // VGA request ready
wire v_clks;
wire [7:0] v_pd; // Pixel data to ramdac
wire v_blank;
wire v_hrtc;
wire v_vrtc;
wire [31:0] vdat_out; // VGA data to MC (unused)
wire mem_req; // VGA memory Request
wire vga_rd_wrn; // VGA RD=1, WR=0
wire [17:0] vga_addr; // MC request address
wire [3:0] vga_we; // VGA data byte mask
wire [31:0] vga_data_in;
wire vga_rstn; // VGA reset
// From CRT
wire [31:0] hdat_out_crt_vga;
wire hb_int_tog; // Horizontal interrupt
wire vb_int_tog; // Vertical interrupt
wire vblnkst2;
wire [20:0] crt_org; // CRT Origin to MC
wire dis_req; // CRT Request to MC
wire blank_toidac;
wire hcsync_toidac;
wire vsync_toidac;
wire ss_sel;
wire ss_line;
wire crt_rstn;
// Bus master interface from HBI
wire pci_mstr_en; // Hammer is a PCI master
wire de_pl_busy;
wire [4:0] flow_reg;
wire [31:2] pci_wr_addr;
wire [21:0] pcim_masks;
wire hbt_pci;
// From Bus Master
// wire [31:0] pcim_ad_out;
// wire pcim_ad_oe;
// wire [3:0] c_be_out;
// From RAMDAC.
wire rdac_hsync;
wire rdac_vsync;
wire rdac_cblankn;
wire temp_psave;
// Pixel Clocks
wire clk162p00; // 1600x1200 60Hz.
wire clk108p00; // 1280x1024 60Hz, 1152x864 75Hz.
wire clk65p00; // 1024x768 60Hz.
wire clk43p50; // 800x600 72Hz.
wire clk28p00; // 720x480 60Hz.
wire clk25p17; // 640x480 60Hz.
wire clk37p50;
wire vga_mode;
wire sync_ext;
wire pll_busy;
wire pll_write_param;
wire [3:0] pll_counter_type;
wire [2:0] pll_counter_param;
wire [8:0] pll_data_in;
wire pll_reconfig;
// Misc wires.
wire vga_mclock;
wire dac_reset_n;
wire hb_wstrb_de;
wire vga_req;
wire ldi_2xzoom;
wire vga_rdwr;
wire vga_mem_io;
wire idac_wr;
wire idac_rd;
wire idac_en;
wire mw_de_fip;
wire mw_dlp_fip;
wire enable_rbase_e_p;
wire pixclk_vga;
wire crtclock;
wire interrupt;
wire pix_locked;
wire mem_locked;
wire locked;
wire phy_reset_n;
wire clk100;
wire sys_locked;
wire pix_locked_37;
wire pix_locked_1;
wire pll_areset_in;
// TC wires.
wire mc_tc_push;
wire [(BYTES<<3)-1:0] mc_tc_data;
wire mc_tc_ack;
wire mc_tc_req;
wire [5:0] mc_tc_page;
wire [31:0] mc_tc_address;
wire [3:0] mc_dev_sel;
wire mc_pal_ack;
wire mc_pal_push;
wire mc_pal_req;
wire mc_pal_half;
wire [31:0] mc_pal_address;
wire ddr3_ready;
wire ddr3_rdata_valid;
wire ddr3_write_req;
wire ddr3_read_req;
wire ddr3_burstbegin;
wire [23:0] ddr3_address;
wire [4:0] ddr3_size;
wire [255:0] ddr3_rdata;
wire [255:0] ddr3_wdata;
wire [31:0] ddr3_be;
assign bt_pal = 1'b1; // 1 = PAL, 0 = NTSC.
assign dac_sog = 1'b0; // Sync On Green Output.
assign gpio_3v[19:1] = 19'h0;
assign gpio_3v[0] = init_done;
// assign pframen = (frame_oe_n) ? 1'bz : frame_out_n;
// assign pirdyn = (irdy_oe_n) ? 1'bz : irdy_out_n;
assign ptrdyn = (hb_ctrl_oe_n) ? 1'bz : trdy_out_n;
assign pdevseln = (devsel_oe_n) ? 1'bz : devsel_out_n;
assign pintan = (intrp_oe_n) ? 1'bz : intrp_out_n;
assign pstopn = (hb_ctrl_oe_n) ? 1'bz : stop_out_n;
//
// req_n must be tristated on reset pci 2.1 spec
//
// reg preqn_enable;
// always @(posedge hclock) preqn_enable <= bb_rstn;
// assign preqn = (preqn_enable) ? req_n : 1'bz;
// assign preqn = (bb_rstn) ? req_n : 1'bz;
// assign pcben[3:0] = (c_be_oe_n) ? 4'bzzzz : c_be_out;
assign ppar = (par32_oe_n) ? 1'bz : par32_out;
assign pad[31:24] = (ad_oe32_n) ? {8{1'bz}} : ad_out[31:24];
assign pad[23:16] = (ad_oe32_n) ? {8{1'bz}} : ad_out[23:16];
assign pad[15:8] = (ad_oe32_n) ? {8{1'bz}} : ad_out[15:8];
assign pad[7:0] = (ad_oe32_n) ? {8{1'bz}} : ad_out[7:0];
// DIGITAL Outputs
//
assign dvo_data = { red, grn, blu};
assign dvo_hsync = rdac_hsync;
assign dvo_vsync = rdac_vsync;
assign bt_hsyncn = rdac_hsync;
assign bt_vsyncn = rdac_vsync;
assign bt_blankn = rdac_cblankn;
assign dac_cblankn = rdac_cblankn;
assign dac_psaven = ~temp_psave; // CRT Power Save Signal.
assign dac_csyncn = 1'b1; // Composit Sync to DAC (for sync on green).
// assign dvo_dclk = ~pixclk;
bt_ddr_io u_dvo_ddr_io
(
.aclr (~bb_rstn),
.datain_h (1'b0),
.datain_l (1'b1),
.outclock (pixclk),
.dataout (dvo_dclk)
);
//////////////////////////////////////////////////////////////////
// DDC, I2C Muxing.
//
wire ddc_din = (ssro[7]) ? pll_sdat_int :
(ssro[0]) ? dvo_dsel_sda :
ddc_sda;
wire ddc_clkin = (ssro[7]) ? pll_sclk_int :
(ssro[0]) ? dvo_bsel_scl :
ddc_scl;
assign ddc_sda = (~ddc_dat_dout_0 | ssro[7] | ssro[0]) ? 1'bz : 1'b0;
assign ddc_scl = (~ddc_clk_0 | ssro[7] | ssro[0]) ? 1'bz : 1'b0;
assign dvo_dsel_sda = (~ddc_dat_dout_0 | ssro[7] | ~ssro[0]) ? 1'bz : 1'b0;
assign dvo_bsel_scl = (~ddc_clk_0 | ssro[7] | ~ssro[0]) ? 1'bz : 1'b0;
assign pll_sclk = (ssro[7] & ddc_clk_0) ? 1'b0 : (~ssro[7] & pll_sclk_oe) ? pll_sclk_int : 1'bz;
assign pll_sdat = (ssro[7] & ddc_dat_dout_0) ? 1'b0 : (~ssro[7] & pll_sdat_oe) ? pll_sdat_int : 1'bz;
// Needed for PCI 66MHz
/*
`ifndef RTL_SIM
pci_pll u_pci_pll
(
.areset (~hresetn),
.inclk0 (hclock),
.c0 (hb_clk),
.locked ()
);
`else
assign hb_clk = hclock;
`endif
*/
assign hb_clk = hclock;
// assign hb_clk = hclock;
assign ca_byteena = ~hb_ben;
hbi_top U_HBI
(
.devid_sel (2'b11),
.hb_clk (hb_clk),
.mclock (phy_clk),
.vga_mclock (vga_mclock),
.hreset_in_n (hresetn),
.hb_ad_bus (pad),
.hb_byte_ens (pcben),
.idsel (pidsel),
.frame_n (pframen),
.irdy_n (pirdyn),
.cmd_hdf (de_hdf),
.de_ca_busy (ca_busy),
.dda_int_tog (de_ddint_tog),
.cla_int_tog (de_clint_tog),
.clp_a (de_clp),
.deb_a (de_deb),
.draw_engine_a_dout (de_hdout),
.draw_engine_reg (de_drout),
.de_pipeln_activ (pipeline_active),
.vga_mem_last (vga_push),
.vga_mem_rdy (vga_ready),
.mcb (~de_pc_empty | ca_busy | mc_busy | mc_busy2), // fixme ????
.vb_int_tog (vb_int_tog),
.hb_int_tog (hb_int_tog),
.hdat_out_crt_vga (hdat_out_crt_vga),
.vga_decode_ctrl (vga_stat[1:0]),
.fis_io_en (vga_stat[2]),
.dlp_retry (pp_rdback[21]),
.busy_a (hb_de_busy),
.ddc1_dat_0 (ddc_din),
.ddc_clk_in_0 (ddc_clkin),
.ddc1_dat_1 (1'b0),
.ddc_clk_in_1 (1'b0),
.pd_in (p_d_out[7:0]),
.config_bus ({window_size_strap,
eprom_strap,
class_strap,
mem_dens_strap,
idac_strap,
mem_type_strap,
hbt_strap,
sbsys_id_strap,
sbvend_sel_strap,
sbvend_id_strap}),
.hst_push (hb_push),
.hst_pop (hb_pop),
.hst_mw_addr (hst_mw_addr),
.mc_ready_p (hb_mem_rdy),
.pix_in_dbus (mc_read_data),
.crt_vertical_intrp_n (dvo_vsync),
.soft_switch_in ({
1'b0,
1'b0,
1'b0,
dual_enn,
~vga_en,
1'b0,
1'b0, // mb_32_sel,
1'b0 // t2r4_mode
}),
.pci_ad_out (32'h0), // pcim_ad_out),
.pci_ad_oe (1'b0), // pcim_ad_oe),
.idac_data_in (idac_rd_data),
.c_be_out (4'h0), // c_be_out),
.vga_mode (vga_mode),
.bios_rdat (/*bios_rdat), */ bios_rdat_i), // FOR INTERNAL BIOS.
.m66_en (m66_en),
.hb_soft_reset_n (bb_rstn),
.dac_reset_n (dac_reset_n),
.hb_cycle_done_n (),
.ddc1_dat2_0 (ddc_dat_dout_0),
.ddc1_dat2_1 (ddc_dat_dout_1),
.sobn_n (),
.hbi_addr_in_p1 (hb_adr_de[13:2]),
.hbi_addr_in_p2 (hb_adr[8:2]),
.hbi_data_in (hb_din),
.hbi_be_in (hb_ben),
.hb_write (hb_write),
.trdy_n (trdy_out_n),
.stop_n (stop_out_n),
.ctrl_oe_n (hb_ctrl_oe_n),
.devsel_n (devsel_out_n),
.devsel_oe_n (devsel_oe_n),
.par32_out (par32_out),
.par32_oe_n (par32_oe_n),
.ad_oe32_n (ad_oe32_n),
.c_be_oe_n (c_be_oe_n),
.blkbird_dout (ad_out),
.interrupt_cnt (intrp_oe_n),
.interrupt_in (intrp_out_n),
.cs_xyw_a_n (csn_de_xyw),
.wr_en_p1 (hb_wstrb_de),
.wr_en_p2 (hb_wstrb),
.cs_draw_a_regs_n (csn_de),
.vga_mem_req (vga_req),
.dden (),
.cfg_reg2_mc (mc_config2reg[23:20]), // 21 no longer needed
.cfg_reg2_cn (mc_config2reg[7]),
.cfg_reg2_ref_cnt (mc_config2reg[6:5]), // no longer needed
.cfg_reg2_rcd (mc_config2reg[4]),
.cfg_reg2_jv (mc_config2reg[3]),
.cfg_reg2_tr (mc_config2reg[2]),
.cfg_reg2_sgr (mc_config2reg[1]),
// .vga_ctrl_dout (vga_controlreg[7:0]),
.ldi_2xzoom (ldi_2xzoom),
.vga_laddr (vga_laddr[22:0]),
.vga_ldata (vga_ldata[31:0]),
.vga_lbe (vga_lbe[3:0]),
.vga_rdwr (vga_rdwr),
.vga_mem_io (vga_mem_io),
.ddc1_clk_0 (ddc_clk_0),
.ddc1_en_0 (ddc_en_0),
.ddc1_clk_1 (ddc_clk_1),
.ddc1_en_1 (ddc_en_1),
.cs_global_regs_n (csn_glb),
.linear_origin (hb_org),
.hb_pdo (hb_pdo),
.mem_mask_bus (hb_pix_msk),
.read (hb_mem_read),
.hb_mc_request_p (hb_mem_req),
.pci_mstr_en (pci_mstr_en),
.de_pl_busy (de_pl_busy),
.flow_reg (flow_reg),
.pci_wr_addr (pci_wr_addr),
.pcim_masks (pcim_masks),
.pa (P_A),
.pd_out (p_d_out),
.pwr_n (),
.prd_n (),
.pcs_n (),
.poe_n (),
.pwe_n (),
.psft (),
.pd_oe_n (p_d_oe_n),
.idac_wr (idac_wr),
.idac_rd (idac_rd),
.cfg_reg2_ide (idac_en),
.mw_de_fip (mw_de_fip),
.mw_dlp_fip (mw_dlp_fip),
.enable_rbase_e_p (enable_rbase_e_p),
.se_clk_sel (),
.hb_ldata (hb_ldata),
.soft_switch_out (ssro),
.full (),
.bios_clk (bios_clk),
.bios_hld (bios_hld),
.bios_csn (bios_csn),
.bios_wdat (bios_wdat)
);
// DE cache RAMs
// dual_port_sim u_ram0[BYTES/4-1:0]
ram_32x32_dp_be u_ram0[BYTES/4-1:0]
(
.clock_a (hb_clk),
.data_a (hb_din),
.wren_a (ca_enable),
.byteena_a (ca_byteena),
.address_a (hb_ram_addr),
.clock_b (phy_clk),
.data_b (mc_read_data),
.address_b (ca_ram_addr0),
.wren_b (de_push),
.q_a (hb_dout_ram),
.q_b (ca_dout0)
);
// dual_port_sim u_ram4[BYTES/4-1:0]
ram_32x32_dp_be u_ram4[BYTES/4-1:0]
(
.clock_a (hb_clk),
.data_a (hb_din),
.wren_a (ca_enable),
.byteena_a (ca_byteena),
.address_a (hb_ram_addr),
.clock_b (phy_clk),
.data_b (mc_read_data),
.address_b (ca_ram_addr1),
.wren_b (de_push),
.q_a (),
.q_b (ca_dout1)
);
`ifdef INCLUDE_VGA
reg init_done_sync, init_done_v;
always @(posedge vga_mclock, negedge bb_rstn)
if (!bb_rstn) init_done_sync <= 1'b0;
else init_done_sync <= init_done;
always @(posedge vga_mclock, negedge bb_rstn)
if (!bb_rstn) init_done_v <= 1'b0;
else init_done_v <= init_done_sync;
vga_top U_VGA
(
.mclock (vga_mclock),
.resetn (bb_rstn),
.hclk (hb_clk),
.crtclk (pixclk),
.vga_req (vga_req),
.vga_rdwr (vga_rdwr),
.vga_mem (vga_mem_io),
.hst_byte (vga_lbe[3:0]),
.hst_addr (vga_laddr[22:0]),
.hst_din (vga_ldata[31:0]),
.mem_din (vga_data),
.sense_n (1'b0),
.mem_ack (vga_ack),
.mem_ready_n (vga_ready_n),
.vga_en (vga_mode),
.mem_ready (init_done_v),
.hst_dout (hst_data_out),
.vga_stat (vga_stat),
.vga_push (vga_push),
.vga_ready (vga_ready),
.v_clksel (v_clks),
.v_pd (v_pd),
.v_blank (v_blank),
.v_hrtc (v_hrtc),
.v_vrtc (v_vrtc),
.mem_req (mem_req),
.vga_rd_wrn (vga_rd_wrn),
.vga_addr (vga_addr),
.vga_we (vga_we),
.vga_data_in (vga_data_in)
);
`else
assign hst_data_out = 32'h0;
assign vga_stat = 3'h0;
assign vga_push = 1'b0;
assign vga_ready = 1'b0;
assign v_clks = 1'h0;
assign v_pd = 8'h0;
assign v_blank = 1'h0;
assign v_hrtc = 1'h0;
assign v_vrtc = 1'h0;
assign mem_req = 1'h0;
assign vga_rd_wrn = 1'h0;
assign vga_addr = 18'h0;
assign vga_we = 4'h0;
assign vga_data_in = 32'h0;
`endif
crt #(.disp_param(4'b0)) u_crt
(
.bpp (bpp),
.crtclock (crtclock),
.pixclock (pixclk),
.hclock (hb_clk),
.hreset (bb_rstn),
.hwr_in (hb_wstrb_de),
.hcs_in (csn_glb),
.hnben_in (hb_ben),
.hdat_in (hb_din),
.haddr (hb_adr_de[7:2]),
.vga_en (vga_mode),
.vga_din (v_pd),
.dlp_wradd (1'b0), //to be connected to DLP (write enable, active high)
.dlp_add (21'b0), //to be connected to DLP (display start address)
.hdat_in_aux (hst_data_out[31:0]),
.vid_win_pos (40'b0),
.ovnokey (1'b0), //from overlay module temp set to 0
.mcdc_ready (dis_rdy),
.mcpush (dis_push),
.mclock (phy_clk),
.datdc_in (mc_read_data),
// .datdc_in ({mc_read_data[111:96], mc_read_data[127:112],
// mc_read_data[79:64], mc_read_data[95:80],
// mc_read_data[47:32], mc_read_data[63:48],
// mc_read_data[15:0], mc_read_data[31:16]}),
.vga_blank (v_blank),
.vga_hsync (v_hrtc),
.vga_vsync (v_vrtc),
.disp_reg_rep (1'b0),
.disp_reg_crt (4'b0),
.hdat_out_crt_aux (hdat_out_crt_vga),
.hint_out_tog ({hb_int_tog,vb_int_tog}),
.vblnkst2 (vblnkst2),
.db_pitch_regist (crt_ptch[11:0]),
.displ_start_vs (crt_org[20:0]),
.mcdc_req (dis_req),
.mcdcyf (dis_y),
.mcdcx (dis_x),
.mcdcpg (dis_page),
.blank_toidac (blank_toidac),
.hcsync_toidac (hcsync_toidac),
.vsync_toidac (vsync_toidac),
.datdc_out (pd_toidac),
.fdp_on (/*fdp_on*/),
.syncsenable_regist (sereg),
.hactive_regist (hactive_regist)
);
/************************************************************/
/* INSTANTIATE THE BUS MASTERING UNIT PCI */
/************************************************************/
/*
pci_wom U_BM
(
.reset_n (bb_rstn),
.hb_clk (hb_clk),
.gnt_n (pgnntn),
//.hbi_addr (hb_adr[3:2]),
//.ad_in (pad[31:0]),
.irdy_in_n (pirdyn),
.frame_in_n (pframen),
.trdy_in_n (ptrdyn),
.stop_in_n (pstopn),
.devsel_in_n (pdevseln),
.dlp_busy (pp_rdback[21]),
.de_pl_busy (de_pl_busy),
.flow_rpb (flow_reg[4]),
.flow_prv (flow_reg[3]),
.flow_clp (flow_reg[2]),
.flow_mcb (flow_reg[1]),
.flow_deb (flow_reg[0]),
.v_blank (vblnkst2),
.vb_int_tog (vb_int_tog),
.hb_int_tog (hb_int_tog),
.pci_mstr_en (pci_mstr_en),
.pci_wr_addr (pci_wr_addr),
.pcim_masks (pcim_masks),
.pci_ad_out (pcim_ad_out),
.pci_ad_oe (pcim_ad_oe),
.c_be_out (c_be_out),
.irdy_n (irdy_out_n),
.pci_irdy_oe_n (irdy_oe_n),
.pci_req_out_n (req_n),
.frame_out_n (frame_out_n),
.frame_oe_n (frame_oe_n)
);
*/
/***************************************************************************/
/* INSTANTIATE THE RAMDAC */
/***************************************************************************/
ramdac u_ramdac
// Inputs.
(
.hclk (hb_clk),
.pixclk (pixclk),
.crtclock (crtclock),
.hresetn (dac_reset_n),
.wrn (idac_wr),
.rdn (idac_rd),
.rs (P_A[2:0]),
.cpu_din (p_d_out),
.ext_fs (v_clks),
.blank (blank_toidac),
.hsyncin (hcsync_toidac),
.vsyncin (vsync_toidac),
.pix_din (pd_toidac),
.idac_en (idac_en),
// .ldi_2xzoom (vga_controlreg[5]),
.ldi_2xzoom (ldi_2xzoom),
.fdp_on (1'b1),
// Outputs.
.bpp (bpp),
.vga_mode (vga_mode),
.dac_pwr (temp_psave),
.syncn2dac (),
.blanknr (),
.blankng (),
.blanknb (),
.sense (),
.cpu_dout (idac_rd_data),
.hsyncout (rdac_hsync),
.vsyncout (rdac_vsync),
.dac_cblankn (rdac_cblankn),
.p0_red (red),
.p0_green (grn),
.p0_blue (blu),
.pixs (),
.display_en (dvo_de),
// For Pix PLL
.pll_busy (pll_busy),
.pll_write_param (pll_write_param),
.pll_counter_type (pll_counter_type),
.pll_counter_param (pll_counter_param),
.pll_data_in (pll_data_in),
.pll_reconfig (pll_reconfig),
.pixclksel (pixclksel),
.int_fs (int_fs),
.sync_ext (sync_ext),
.pll_areset_in (pll_areset_in)
);
// assign ledn = ~vga_mode;
/**************************************************************************/
/* INSTANTIATE DRAWING ENGINE */
/**************************************************************************/
de_top
#
(
.BYTES (BYTES)
)
U_DE
(
.de_clk (de_clk),
.sys_locked (sys_locked),
.hb_clk (hb_clk),
.hb_rstn (bb_rstn),
.dlp_adr (dlp_adr[8:2]),
.hb_adr_bp1 (hb_adr_de[13:2]),
.hb_adr_bp2 (hb_adr[8:2]),
.hb_wstrb (de_wstrb),
.hb_ben (de_ben),
.hb_din (de_data), // from dlp no swizzle
.hb_csn_de (de_csn),
.hb_xyw_csn (csn_de_xyw),
.mclock (phy_clk),
.mc_popen (de_popen),
.mc_push (de_push),
.mc_eop (de_last),
.mc_eop4 (de_last4),
.de_pc_pop (de_pc_pop),
.dl_rdback (pp_rdback),
.mw_de_fip (mw_de_fip),
.hb_write (hb_write),
.mc_busy (mc_busy),
.busy_dlp (hb_de_busy),
// outputs
.hb_dout (de_hdout),
.dr_hbdout (de_drout),
.busy_hb (de_busy),
.interrupt (interrupt),
.dd_pixel_msk (de_pix_msk),
.dd_fb_out (de_pdo),
.dd_fb_a (de_ado),
.de_pc_empty (de_pc_empty),
.hdf_1 (de_hdf),
.ps_4 (de_ps_2),
.de_mc_address (de_address),
.de_mc_read (de_mem_read),
.de_mc_rmw (de_mem_rmw),
.de_mc_wcnt (de_wcnt),
.line_actv_4 (line_actv_4),
.bsrcr_4 (de_bsrcr),
.bdstr_4 (de_bdstr),
.blend_en_4 (de_blend_en),
.blend_reg_en_4 (de_blend_reg_en),
.bsrc_alpha_4 (de_bsrc_alpha),
.bdst_alpha_4 (de_bdst_alpha),
.rop_4 (de_rop),
.kcol_4 (de_kcol),
.key_ctrl_4 (de_kcnt),
.ca_enable (ca_enable),
.hb_ram_addr (hb_ram_addr),
.ca_ram_addr0 (ca_ram_addr0),
.ca_ram_addr1 (ca_ram_addr1),
.hb_dout_ram (hb_dout_ram),
.ca_dout0 (ca_dout0),
.ca_dout1 (ca_dout1),
.mem_offset (mem_offset),
.sorg_upper (sorg_upper),
.ca_busy (ca_busy),
.de_ddint_tog (de_ddint_tog),
.de_clint_tog (de_clint_tog),
.dx_clp (de_clp),
.dx_deb (de_deb),
.pipe_pending (pipeline_active),
.z_ctrl_4 (z_ctrl_4),
.z_address_4 (z_address_4),
.z_out (z_out),
// TC Signals To/from the Memory Controller.
// Inputs.
.mc_tc_push (mc_tc_push),
.mc_tc_data (mc_tc_data),
.mc_tc_ack (mc_tc_ack),
.mc_pal_ack (mc_pal_ack),
.mc_pal_push (mc_pal_push),
// Outputs.
.mc_tc_req (mc_tc_req),
.mc_tc_page (mc_tc_page),
.mc_tc_address (mc_tc_address),
.mc_pal_req (mc_pal_req),
.mc_pal_half (mc_pal_half),
.mc_pal_address (mc_pal_address)
);
/***************************************************************************/
/* INSTANTIATE THE PRE PROCESSOR BLOCK. */
/***************************************************************************/
dlp_top
#
(
.BYTES (BYTES)
)
U_DLP
(
.hb_clk (hb_clk),
.hb_rstn (bb_rstn),
.hb_adr (hb_adr[8:2]),
.hb_wstrb (hb_wstrb),
.hb_ben (hb_ben),
.hb_csn (csn_de),
.hb_din (hb_ldata),
.dlp_offset (mem_offset[6:3]),
.de_busy (de_busy),
.mclock (phy_clk),
.mc_rdy (dlp_ready),
.mc_push (dlp_push),
.mc_done (dlp_mc_done),
.pd_in (mc_read_data),
.v_sync_tog (vb_int_tog),
.cache_busy (mw_dlp_fip),
.sorg_upper (sorg_upper),
.de_adr (dlp_adr),
.de_wstrb (de_wstrb),
.de_csn (de_csn),
.de_ben (de_ben),
.de_data (de_data),
.dl_rdback (pp_rdback),
.mc_adr (dlp_addr),
.dl_sen (dlp_sen),
.dl_memreq (dlp_req),
.dlp_wcnt (dlp_wcnt),
.hb_de_busy (hb_de_busy),
.hold_start (dlp_hold_start)
);
/***************************************************************************/
/* INSTANTIATE THE MEMORY CONTROLLER. */
/***************************************************************************/
mc
#(
.BYTES (BYTES)
)
u_mc
(
.de_bdst_alpha (de_bdst_alpha),
.de_bdstr (de_bdstr),
.de_blend_en (de_blend_en),
.de_blend_reg_en (de_blend_reg_en),
.de_bsrc_alpha (de_bsrc_alpha),
.de_bsrcr (de_bsrcr),
.de_byte_mask (de_pix_msk),
.de_data (de_pdo),
.de_adata (de_ado),
.de_kcnt (de_kcnt),
.de_kcol (de_kcol),
.de_page (de_wcnt),
.de_pix (de_ps_2),
.de_read (de_mem_read),
.de_rmw (de_mem_rmw),
.de_rop (de_rop),
.de_address (de_address),
.de_pc_empty (de_pc_empty),
.de_pc_pop (de_pc_pop),
.line_actv_4 (line_actv_4),
.de_zen (z_ctrl_4[3]),
.de_zro (z_ctrl_4[4]),
.de_zop (z_ctrl_4[2:0]),
.de_zaddr (z_address_4),
.de_zdata (z_out),
.dlp_org (dlp_addr),
.dlp_req (dlp_req),
.dlp_wcnt (dlp_wcnt),
.hst_clock (hb_clk),
.hst_byte_mask (hb_pix_msk),
.hst_data (hb_pdo),
.hst_org (hb_org),
.hst_read (hb_mem_read),
.hst_req (hb_mem_req),
.pixclk (pixclk),
.crt_clock (crtclock),
.crt_req (dis_req),
.crt_org (crt_org),
.crt_page (dis_page),
.crt_ptch (crt_ptch),
.crt_x (dis_x),
.crt_y (dis_y),
.vga_mode (vga_mode),
.v_mclock (vga_mclock),
.vga_req (mem_req),
.vga_rd_wrn (vga_rd_wrn),
.vga_addr (vga_addr),
.vga_we (vga_we),
.vga_data_in (vga_data_in),
// From Texel Cache.
.tc_address (mc_tc_address),
.tc_page (mc_tc_page),
.tc_req (mc_tc_req),
// Palette
.pal_req (mc_pal_req),
.pal_half (mc_pal_half),
.pal_address (mc_pal_address),
.pal_ack (mc_pal_ack),
.pal_push (mc_pal_push),
.mclock (phy_clk),
.reset_n (phy_reset_n),
// .reset (bb_rstn),
// .reset (hresetn),
.de_popen (de_popen),
.de_push (de_push),
.de_last (de_last),
.de_last4 (de_last4),
.dlp_push (dlp_push),
.dlp_mc_done (dlp_mc_done),
.dlp_ready (dlp_ready),
.hst_pop (hb_pop),
.hst_push (hb_push),
.hst_rdy (hb_mem_rdy),
.hst_mw_addr (hst_mw_addr),
.read_data (mc_read_data),
.mcb (mc_busy),
.mc_busy (mc_busy2),
.crt_push (dis_push),
.crt_ready (dis_rdy),
.vga_data (vga_data),
.vga_ack (vga_ack),
.vga_ready_n (vga_ready_n),
// To Texel Cache.
.tc_ack (mc_tc_ack),
.tc_push (mc_tc_push),
.local_ready (local_ready),
.local_rdata (local_rdata),
.local_rdata_valid (local_rdata_valid),
.local_address (local_address),
.local_write_req (local_write_req),
.local_read_req (local_read_req),
.local_burstbegin (local_burstbegin),
.local_wdata (local_wdata),
.local_be (local_be),
.local_size (local_size),
.init_done (init_done),
.dev_sel (mc_dev_sel)
);
mc_cache u_mc_cache
(
.mclock (phy_clk),
.mc_rstn (phy_reset_n),
.mc_dev_sel (mc_dev_sel),
.mc_local_write_req (local_write_req),
.mc_local_read_req (local_read_req),
.mc_local_burstbegin (local_burstbegin),
.mc_local_address (local_address),
.mc_local_wdata (local_wdata),
.mc_local_be (local_be),
.mc_local_size (local_size),
.mc_local_ready (local_ready),
.mc_local_rdata (local_rdata),
.mc_local_rdata_valid (local_rdata_valid),
// to/from ddr3
.ddr3_ready (ddr3_ready),
.ddr3_rdata (ddr3_rdata),
.ddr3_rdata_valid (ddr3_rdata_valid),
.ddr3_write_req (ddr3_write_req),
.ddr3_read_req (ddr3_read_req),
.ddr3_burstbegin (ddr3_burstbegin),
.ddr3_address (ddr3_address),
.ddr3_wdata (ddr3_wdata),
.ddr3_be (ddr3_be),
.ddr3_size (ddr3_size)
);
// Outputs.
assign mc_tc_data = mc_read_data;
`ifdef FAST_MEM_FULL
avalon_fast_model U_DDR3
`else
ddr3_int U_DDR3
`endif
(
.local_address (ddr3_address),
.local_write_req (ddr3_write_req),
.local_read_req (ddr3_read_req),
.local_burstbegin (ddr3_burstbegin),
.local_wdata (ddr3_wdata),
.local_be (ddr3_be),
.local_size (ddr3_size),
.pll_ref_clk (pll_xbuf1),
.global_reset_n (bb_rstn),
// .pll_ref_clk (hclock),
// .global_reset_n (hresetn),
.soft_reset_n (1'b1),
.local_ready (ddr3_ready),
.local_rdata (ddr3_rdata),
.local_rdata_valid (ddr3_rdata_valid),
.reset_request_n (),
.mem_odt (mem_odt),
.mem_cs_n (mem_cs_n),
.mem_cke (mem_cke),
.mem_addr (mem_addr[12:0]),
.mem_ba (mem_ba),
.mem_ras_n (mem_ras_n),
.mem_cas_n (mem_cas_n),
.mem_we_n (mem_we_n),
.mem_dm (mem_dm),
.local_refresh_ack (),
.local_wdata_req (),
.local_init_done (init_done),
.mem_reset_n (mem_reset_n),
.dll_reference_clk (),
.dqs_delay_ctrl_export (),
.phy_clk (phy_clk),
.reset_phy_clk_n (phy_reset_n),
.aux_full_rate_clk (),
.aux_half_rate_clk (),
.mem_clk (mem_clk),
.mem_clk_n (mem_clk_n),
.mem_dq (mem_dq),
.mem_dqs (mem_dqs),
.mem_dqsn (mem_dqsn)
);
assign mem_addr[13] = 1'b0;
`ifdef EX_PLL
// External PLL Interface.
pll_intf u_pll_intf
(
.hclk (hb_clk),
.hresetn (bb_rstn),
.p_update (p_update),
.pll_params (pll_params),
.m66_en (1'b1),
.alt_pll_lock (1'b1),
// .p_update1 (1'b0),
// .pll_params1 (27'b0),
.sclk (pll_sclk_int),
.sdat (pll_sdat_int),
.sdat_oe (pll_sdat_oe),
.sclk_oe (pll_sclk_oe),
.shift_done (),
.ext_pll_locked ()
);
`else
assign pll_sclk_int = 1'b0;
assign pll_sdat_int = 1'b0;
assign pll_sdat_oe = 1'b0;
assign pll_sclk_oe = 1'b0;
`endif
`ifdef RTL_SIM
reg clk162p00_tmp;
reg clk108p00_tmp;
reg clk65p00_tmp;
reg clk43p50_tmp;
reg clk28p00_tmp;
reg clk25p17_tmp;
reg vga_mclock_tmp;
reg de_clk_tmp;
assign clk162p00 = clk162p00_tmp;
assign clk108p00 = clk108p00_tmp;
assign clk65p00 = clk65p00_tmp;
assign clk43p50 = clk43p50_tmp;
assign clk28p00 = clk28p00_tmp;
assign clk25p17 = clk25p17_tmp;
assign pix_locked = 1'b1;
assign vga_mclock = vga_mclock_tmp;
assign de_clk = de_clk_tmp;
assign mem_locked = 1'b1;
assign pixclk = clk28p00_tmp;
assign crtclock = clk28p00_tmp;
always begin
#3.08 clk162p00_tmp = 0;
#3.08 clk162p00_tmp = 1;
end
always begin
#4.63 clk108p00_tmp = 0;
#4.63 clk108p00_tmp = 1;
end
always begin
#7.69 clk65p00_tmp = 0;
#7.69 clk65p00_tmp = 1;
end
always begin
#11.50 clk43p50_tmp = 0;
#11.50 clk43p50_tmp = 1;
end
always begin
#17.86 clk28p00_tmp = 0;
#17.86 clk28p00_tmp = 1;
end
always begin
#19.86 clk25p17_tmp = 0;
#19.86 clk25p17_tmp = 1;
end
always begin
#10 vga_mclock_tmp = 0;
#10 vga_mclock_tmp = 1;
end
always begin
#5 de_clk_tmp = 0;
#5 de_clk_tmp = 1;
end
assign bt_clki = bt_clko;
assign sys_locked = 1'b1;
`else
///////////////////////////////////////////////////
// System PLL, xbuf_1 Clock source
//
sys_pll_rb u_sys_pll_rb
(
.areset (~bb_rstn),
.inclk0 (pll_xbuf), // 25.00Hz
.c0 (de_clk), //
.c1 (vga_mclock), //
.locked (sys_locked)
);
`ifdef PLL_INT
///////////////////////////////////////////////////
// Internal reconfigurable PLL.
//
clk_gen_ipll u_clk_gen_ipll
(
.hb_clk (hb_clk),
.hb_resetn (bb_rstn),
.refclk (bt_clko),
.bpp (bpp),
.vga_mode (vga_mode),
.write_param (pll_write_param),
.counter_type (pll_counter_type),
.counter_param (pll_counter_param),
.data_in (pll_data_in),
.reconfig (pll_reconfig),
.pll_areset_in (pll_areset_in),
.busy (pll_busy),
.pix_clk (pixclk),
.crt_clk (crtclock),
.pix_clk_vga (),
.pix_locked (pix_locked)
);
// assign bt_clki = pixclk;
bt_ddr_io u_bt_ddr_io
(
.aclr (~bb_rstn),
.datain_h (1'b1),
.datain_l (1'b0),
.outclock (pixclk),
.dataout (bt_clki)
);
`else
///////////////////////////////////////////////////
// Internal PLL with clock switch.
// Pixel Clock PLL
wire bt_clk_1x;
/*
// Generate the 37.5MHz from the 25MHz input
pll_25_37p5 u_pix_pll2
(
.areset (1'b0), // ~bb_rstn),
.inclk0 (pll_xbuf1), // 25.0MHz
.c0 (clk37p50), // 37.5MHz, 800x600 60Hz, 780x780 60hz.
.locked (pix_locked_37)
);
*/
pix_pll_bt u_pix_pll0
(
.areset (1'b0), // ~bb_rstn),
// .clkswitch (bt_clk_sel),
// .inclk0 (pll_xbuf), // clk37p50), // 25.5MHz or 37.5MHz
.inclk0 (bt_clko), // 29.5MHz or 37.5MHz
.c3 (clk65p00), // 1024x768 60Hz.
.c2 (clk25p17), // 640x480 60Hz.
.c1 (clk43p50), // 43.5MHz, 800x600 60Hz, 780x780 60hz.
.c0 (bt_clk_1x), // bt_clki), // 29.5MHz or 37.5MHz, 1X output.
.locked (pix_locked)
);
// Clock Switcher And PLLs.
wire pixclk_i;
/*
clk_gen u_clk_gen
(
.hb_clk (hb_clk),
.hb_resetn (hresetn),
// .pll_locked ((pix_locked & pix_locked_1)),
.pll_locked (1'b1), // pix_locked),
.pll_clocks ({
1'b0,
1'b0, // clk162p00, // 1600x1200 60Hz.
clk108p00, // 1280x1024 60Hz, 1152x864 75Hz.
clk65p00, // 1024x768 60Hz.
clk43p50, // 800x600, 780x780, 60Hz
1'b0 , // 720x480 60Hz.
clk25p17, // 640x480 60Hz.
bt_clk_1x // 1X 29.5MHz or 37.5MHz (PAL).
}),
.bpp (bpp),
.hactive_regist (hactive_regist),
.pixclksel (pixclksel),
.vga_mode (vga_mode),
.int_fs (int_fs),
.sync_ext (sync_ext),
.pix_clk (pixclk_i),
.pix_clk_vga (pixclk_vga),
.crt_clk (crtclock),
.locked (locked)
);
*/
wire [2:0] int_clk_sel;
clk_gen u_clk_gen
(
.hb_clk (hb_clk),
.hb_resetn (hresetn),
// .pll_locked ((pix_locked & pix_locked_1)),
.pll_locked (1'b1), // pix_locked),
.bpp (bpp),
.hactive_regist (hactive_regist),
.pixclksel (pixclksel),
.vga_mode (vga_mode),
.int_fs (int_fs),
.sync_ext (sync_ext),
.pix_clk (pixclk),
.crt_clk (crtclock),
.locked (locked),
.int_clk_sel (int_clk_sel)
);
clk_global u_clk_global
(
.clkselect (int_clk_sel[1:0]),
.inclk3x (clk65p00),
.inclk2x (clk43p50),
.inclk1x (clk25p17),
.inclk0x (bt_clk_1x),
.outclk (pixclk)
);
assign bt_clki = pixclk;
`endif
`endif
`ifdef INCLUDE_VGA
// The BIOS is compiled to fit in an internal memory to make life a little
// easier
bios_internal u_bios_internal
(
.hb_clk (hb_clk),
.hresetn (hresetn),
.bios_clk (bios_clk),
.bios_wdat (bios_wdat),
.bios_csn (bios_csn),
.bios_rdat (bios_rdat_i)
);
`else
`endif
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
// Date : Mon Sep 18 12:32:27 2017
// Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_0_sim_netlist.v
// Design : vio_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7k325tffg676-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "vio_0,vio,{}" *) (* X_CORE_INFO = "vio,Vivado 2016.3" *)
(* NotValidForBitStream *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(clk,
probe_in0,
probe_in1,
probe_in2,
probe_in3);
input clk;
input [0:0]probe_in0;
input [0:0]probe_in1;
input [0:0]probe_in2;
input [0:0]probe_in3;
wire clk;
wire [0:0]probe_in0;
wire [0:0]probe_in1;
wire [0:0]probe_in2;
wire [0:0]probe_in3;
wire [0:0]NLW_inst_probe_out0_UNCONNECTED;
wire [0:0]NLW_inst_probe_out1_UNCONNECTED;
wire [0:0]NLW_inst_probe_out10_UNCONNECTED;
wire [0:0]NLW_inst_probe_out100_UNCONNECTED;
wire [0:0]NLW_inst_probe_out101_UNCONNECTED;
wire [0:0]NLW_inst_probe_out102_UNCONNECTED;
wire [0:0]NLW_inst_probe_out103_UNCONNECTED;
wire [0:0]NLW_inst_probe_out104_UNCONNECTED;
wire [0:0]NLW_inst_probe_out105_UNCONNECTED;
wire [0:0]NLW_inst_probe_out106_UNCONNECTED;
wire [0:0]NLW_inst_probe_out107_UNCONNECTED;
wire [0:0]NLW_inst_probe_out108_UNCONNECTED;
wire [0:0]NLW_inst_probe_out109_UNCONNECTED;
wire [0:0]NLW_inst_probe_out11_UNCONNECTED;
wire [0:0]NLW_inst_probe_out110_UNCONNECTED;
wire [0:0]NLW_inst_probe_out111_UNCONNECTED;
wire [0:0]NLW_inst_probe_out112_UNCONNECTED;
wire [0:0]NLW_inst_probe_out113_UNCONNECTED;
wire [0:0]NLW_inst_probe_out114_UNCONNECTED;
wire [0:0]NLW_inst_probe_out115_UNCONNECTED;
wire [0:0]NLW_inst_probe_out116_UNCONNECTED;
wire [0:0]NLW_inst_probe_out117_UNCONNECTED;
wire [0:0]NLW_inst_probe_out118_UNCONNECTED;
wire [0:0]NLW_inst_probe_out119_UNCONNECTED;
wire [0:0]NLW_inst_probe_out12_UNCONNECTED;
wire [0:0]NLW_inst_probe_out120_UNCONNECTED;
wire [0:0]NLW_inst_probe_out121_UNCONNECTED;
wire [0:0]NLW_inst_probe_out122_UNCONNECTED;
wire [0:0]NLW_inst_probe_out123_UNCONNECTED;
wire [0:0]NLW_inst_probe_out124_UNCONNECTED;
wire [0:0]NLW_inst_probe_out125_UNCONNECTED;
wire [0:0]NLW_inst_probe_out126_UNCONNECTED;
wire [0:0]NLW_inst_probe_out127_UNCONNECTED;
wire [0:0]NLW_inst_probe_out128_UNCONNECTED;
wire [0:0]NLW_inst_probe_out129_UNCONNECTED;
wire [0:0]NLW_inst_probe_out13_UNCONNECTED;
wire [0:0]NLW_inst_probe_out130_UNCONNECTED;
wire [0:0]NLW_inst_probe_out131_UNCONNECTED;
wire [0:0]NLW_inst_probe_out132_UNCONNECTED;
wire [0:0]NLW_inst_probe_out133_UNCONNECTED;
wire [0:0]NLW_inst_probe_out134_UNCONNECTED;
wire [0:0]NLW_inst_probe_out135_UNCONNECTED;
wire [0:0]NLW_inst_probe_out136_UNCONNECTED;
wire [0:0]NLW_inst_probe_out137_UNCONNECTED;
wire [0:0]NLW_inst_probe_out138_UNCONNECTED;
wire [0:0]NLW_inst_probe_out139_UNCONNECTED;
wire [0:0]NLW_inst_probe_out14_UNCONNECTED;
wire [0:0]NLW_inst_probe_out140_UNCONNECTED;
wire [0:0]NLW_inst_probe_out141_UNCONNECTED;
wire [0:0]NLW_inst_probe_out142_UNCONNECTED;
wire [0:0]NLW_inst_probe_out143_UNCONNECTED;
wire [0:0]NLW_inst_probe_out144_UNCONNECTED;
wire [0:0]NLW_inst_probe_out145_UNCONNECTED;
wire [0:0]NLW_inst_probe_out146_UNCONNECTED;
wire [0:0]NLW_inst_probe_out147_UNCONNECTED;
wire [0:0]NLW_inst_probe_out148_UNCONNECTED;
wire [0:0]NLW_inst_probe_out149_UNCONNECTED;
wire [0:0]NLW_inst_probe_out15_UNCONNECTED;
wire [0:0]NLW_inst_probe_out150_UNCONNECTED;
wire [0:0]NLW_inst_probe_out151_UNCONNECTED;
wire [0:0]NLW_inst_probe_out152_UNCONNECTED;
wire [0:0]NLW_inst_probe_out153_UNCONNECTED;
wire [0:0]NLW_inst_probe_out154_UNCONNECTED;
wire [0:0]NLW_inst_probe_out155_UNCONNECTED;
wire [0:0]NLW_inst_probe_out156_UNCONNECTED;
wire [0:0]NLW_inst_probe_out157_UNCONNECTED;
wire [0:0]NLW_inst_probe_out158_UNCONNECTED;
wire [0:0]NLW_inst_probe_out159_UNCONNECTED;
wire [0:0]NLW_inst_probe_out16_UNCONNECTED;
wire [0:0]NLW_inst_probe_out160_UNCONNECTED;
wire [0:0]NLW_inst_probe_out161_UNCONNECTED;
wire [0:0]NLW_inst_probe_out162_UNCONNECTED;
wire [0:0]NLW_inst_probe_out163_UNCONNECTED;
wire [0:0]NLW_inst_probe_out164_UNCONNECTED;
wire [0:0]NLW_inst_probe_out165_UNCONNECTED;
wire [0:0]NLW_inst_probe_out166_UNCONNECTED;
wire [0:0]NLW_inst_probe_out167_UNCONNECTED;
wire [0:0]NLW_inst_probe_out168_UNCONNECTED;
wire [0:0]NLW_inst_probe_out169_UNCONNECTED;
wire [0:0]NLW_inst_probe_out17_UNCONNECTED;
wire [0:0]NLW_inst_probe_out170_UNCONNECTED;
wire [0:0]NLW_inst_probe_out171_UNCONNECTED;
wire [0:0]NLW_inst_probe_out172_UNCONNECTED;
wire [0:0]NLW_inst_probe_out173_UNCONNECTED;
wire [0:0]NLW_inst_probe_out174_UNCONNECTED;
wire [0:0]NLW_inst_probe_out175_UNCONNECTED;
wire [0:0]NLW_inst_probe_out176_UNCONNECTED;
wire [0:0]NLW_inst_probe_out177_UNCONNECTED;
wire [0:0]NLW_inst_probe_out178_UNCONNECTED;
wire [0:0]NLW_inst_probe_out179_UNCONNECTED;
wire [0:0]NLW_inst_probe_out18_UNCONNECTED;
wire [0:0]NLW_inst_probe_out180_UNCONNECTED;
wire [0:0]NLW_inst_probe_out181_UNCONNECTED;
wire [0:0]NLW_inst_probe_out182_UNCONNECTED;
wire [0:0]NLW_inst_probe_out183_UNCONNECTED;
wire [0:0]NLW_inst_probe_out184_UNCONNECTED;
wire [0:0]NLW_inst_probe_out185_UNCONNECTED;
wire [0:0]NLW_inst_probe_out186_UNCONNECTED;
wire [0:0]NLW_inst_probe_out187_UNCONNECTED;
wire [0:0]NLW_inst_probe_out188_UNCONNECTED;
wire [0:0]NLW_inst_probe_out189_UNCONNECTED;
wire [0:0]NLW_inst_probe_out19_UNCONNECTED;
wire [0:0]NLW_inst_probe_out190_UNCONNECTED;
wire [0:0]NLW_inst_probe_out191_UNCONNECTED;
wire [0:0]NLW_inst_probe_out192_UNCONNECTED;
wire [0:0]NLW_inst_probe_out193_UNCONNECTED;
wire [0:0]NLW_inst_probe_out194_UNCONNECTED;
wire [0:0]NLW_inst_probe_out195_UNCONNECTED;
wire [0:0]NLW_inst_probe_out196_UNCONNECTED;
wire [0:0]NLW_inst_probe_out197_UNCONNECTED;
wire [0:0]NLW_inst_probe_out198_UNCONNECTED;
wire [0:0]NLW_inst_probe_out199_UNCONNECTED;
wire [0:0]NLW_inst_probe_out2_UNCONNECTED;
wire [0:0]NLW_inst_probe_out20_UNCONNECTED;
wire [0:0]NLW_inst_probe_out200_UNCONNECTED;
wire [0:0]NLW_inst_probe_out201_UNCONNECTED;
wire [0:0]NLW_inst_probe_out202_UNCONNECTED;
wire [0:0]NLW_inst_probe_out203_UNCONNECTED;
wire [0:0]NLW_inst_probe_out204_UNCONNECTED;
wire [0:0]NLW_inst_probe_out205_UNCONNECTED;
wire [0:0]NLW_inst_probe_out206_UNCONNECTED;
wire [0:0]NLW_inst_probe_out207_UNCONNECTED;
wire [0:0]NLW_inst_probe_out208_UNCONNECTED;
wire [0:0]NLW_inst_probe_out209_UNCONNECTED;
wire [0:0]NLW_inst_probe_out21_UNCONNECTED;
wire [0:0]NLW_inst_probe_out210_UNCONNECTED;
wire [0:0]NLW_inst_probe_out211_UNCONNECTED;
wire [0:0]NLW_inst_probe_out212_UNCONNECTED;
wire [0:0]NLW_inst_probe_out213_UNCONNECTED;
wire [0:0]NLW_inst_probe_out214_UNCONNECTED;
wire [0:0]NLW_inst_probe_out215_UNCONNECTED;
wire [0:0]NLW_inst_probe_out216_UNCONNECTED;
wire [0:0]NLW_inst_probe_out217_UNCONNECTED;
wire [0:0]NLW_inst_probe_out218_UNCONNECTED;
wire [0:0]NLW_inst_probe_out219_UNCONNECTED;
wire [0:0]NLW_inst_probe_out22_UNCONNECTED;
wire [0:0]NLW_inst_probe_out220_UNCONNECTED;
wire [0:0]NLW_inst_probe_out221_UNCONNECTED;
wire [0:0]NLW_inst_probe_out222_UNCONNECTED;
wire [0:0]NLW_inst_probe_out223_UNCONNECTED;
wire [0:0]NLW_inst_probe_out224_UNCONNECTED;
wire [0:0]NLW_inst_probe_out225_UNCONNECTED;
wire [0:0]NLW_inst_probe_out226_UNCONNECTED;
wire [0:0]NLW_inst_probe_out227_UNCONNECTED;
wire [0:0]NLW_inst_probe_out228_UNCONNECTED;
wire [0:0]NLW_inst_probe_out229_UNCONNECTED;
wire [0:0]NLW_inst_probe_out23_UNCONNECTED;
wire [0:0]NLW_inst_probe_out230_UNCONNECTED;
wire [0:0]NLW_inst_probe_out231_UNCONNECTED;
wire [0:0]NLW_inst_probe_out232_UNCONNECTED;
wire [0:0]NLW_inst_probe_out233_UNCONNECTED;
wire [0:0]NLW_inst_probe_out234_UNCONNECTED;
wire [0:0]NLW_inst_probe_out235_UNCONNECTED;
wire [0:0]NLW_inst_probe_out236_UNCONNECTED;
wire [0:0]NLW_inst_probe_out237_UNCONNECTED;
wire [0:0]NLW_inst_probe_out238_UNCONNECTED;
wire [0:0]NLW_inst_probe_out239_UNCONNECTED;
wire [0:0]NLW_inst_probe_out24_UNCONNECTED;
wire [0:0]NLW_inst_probe_out240_UNCONNECTED;
wire [0:0]NLW_inst_probe_out241_UNCONNECTED;
wire [0:0]NLW_inst_probe_out242_UNCONNECTED;
wire [0:0]NLW_inst_probe_out243_UNCONNECTED;
wire [0:0]NLW_inst_probe_out244_UNCONNECTED;
wire [0:0]NLW_inst_probe_out245_UNCONNECTED;
wire [0:0]NLW_inst_probe_out246_UNCONNECTED;
wire [0:0]NLW_inst_probe_out247_UNCONNECTED;
wire [0:0]NLW_inst_probe_out248_UNCONNECTED;
wire [0:0]NLW_inst_probe_out249_UNCONNECTED;
wire [0:0]NLW_inst_probe_out25_UNCONNECTED;
wire [0:0]NLW_inst_probe_out250_UNCONNECTED;
wire [0:0]NLW_inst_probe_out251_UNCONNECTED;
wire [0:0]NLW_inst_probe_out252_UNCONNECTED;
wire [0:0]NLW_inst_probe_out253_UNCONNECTED;
wire [0:0]NLW_inst_probe_out254_UNCONNECTED;
wire [0:0]NLW_inst_probe_out255_UNCONNECTED;
wire [0:0]NLW_inst_probe_out26_UNCONNECTED;
wire [0:0]NLW_inst_probe_out27_UNCONNECTED;
wire [0:0]NLW_inst_probe_out28_UNCONNECTED;
wire [0:0]NLW_inst_probe_out29_UNCONNECTED;
wire [0:0]NLW_inst_probe_out3_UNCONNECTED;
wire [0:0]NLW_inst_probe_out30_UNCONNECTED;
wire [0:0]NLW_inst_probe_out31_UNCONNECTED;
wire [0:0]NLW_inst_probe_out32_UNCONNECTED;
wire [0:0]NLW_inst_probe_out33_UNCONNECTED;
wire [0:0]NLW_inst_probe_out34_UNCONNECTED;
wire [0:0]NLW_inst_probe_out35_UNCONNECTED;
wire [0:0]NLW_inst_probe_out36_UNCONNECTED;
wire [0:0]NLW_inst_probe_out37_UNCONNECTED;
wire [0:0]NLW_inst_probe_out38_UNCONNECTED;
wire [0:0]NLW_inst_probe_out39_UNCONNECTED;
wire [0:0]NLW_inst_probe_out4_UNCONNECTED;
wire [0:0]NLW_inst_probe_out40_UNCONNECTED;
wire [0:0]NLW_inst_probe_out41_UNCONNECTED;
wire [0:0]NLW_inst_probe_out42_UNCONNECTED;
wire [0:0]NLW_inst_probe_out43_UNCONNECTED;
wire [0:0]NLW_inst_probe_out44_UNCONNECTED;
wire [0:0]NLW_inst_probe_out45_UNCONNECTED;
wire [0:0]NLW_inst_probe_out46_UNCONNECTED;
wire [0:0]NLW_inst_probe_out47_UNCONNECTED;
wire [0:0]NLW_inst_probe_out48_UNCONNECTED;
wire [0:0]NLW_inst_probe_out49_UNCONNECTED;
wire [0:0]NLW_inst_probe_out5_UNCONNECTED;
wire [0:0]NLW_inst_probe_out50_UNCONNECTED;
wire [0:0]NLW_inst_probe_out51_UNCONNECTED;
wire [0:0]NLW_inst_probe_out52_UNCONNECTED;
wire [0:0]NLW_inst_probe_out53_UNCONNECTED;
wire [0:0]NLW_inst_probe_out54_UNCONNECTED;
wire [0:0]NLW_inst_probe_out55_UNCONNECTED;
wire [0:0]NLW_inst_probe_out56_UNCONNECTED;
wire [0:0]NLW_inst_probe_out57_UNCONNECTED;
wire [0:0]NLW_inst_probe_out58_UNCONNECTED;
wire [0:0]NLW_inst_probe_out59_UNCONNECTED;
wire [0:0]NLW_inst_probe_out6_UNCONNECTED;
wire [0:0]NLW_inst_probe_out60_UNCONNECTED;
wire [0:0]NLW_inst_probe_out61_UNCONNECTED;
wire [0:0]NLW_inst_probe_out62_UNCONNECTED;
wire [0:0]NLW_inst_probe_out63_UNCONNECTED;
wire [0:0]NLW_inst_probe_out64_UNCONNECTED;
wire [0:0]NLW_inst_probe_out65_UNCONNECTED;
wire [0:0]NLW_inst_probe_out66_UNCONNECTED;
wire [0:0]NLW_inst_probe_out67_UNCONNECTED;
wire [0:0]NLW_inst_probe_out68_UNCONNECTED;
wire [0:0]NLW_inst_probe_out69_UNCONNECTED;
wire [0:0]NLW_inst_probe_out7_UNCONNECTED;
wire [0:0]NLW_inst_probe_out70_UNCONNECTED;
wire [0:0]NLW_inst_probe_out71_UNCONNECTED;
wire [0:0]NLW_inst_probe_out72_UNCONNECTED;
wire [0:0]NLW_inst_probe_out73_UNCONNECTED;
wire [0:0]NLW_inst_probe_out74_UNCONNECTED;
wire [0:0]NLW_inst_probe_out75_UNCONNECTED;
wire [0:0]NLW_inst_probe_out76_UNCONNECTED;
wire [0:0]NLW_inst_probe_out77_UNCONNECTED;
wire [0:0]NLW_inst_probe_out78_UNCONNECTED;
wire [0:0]NLW_inst_probe_out79_UNCONNECTED;
wire [0:0]NLW_inst_probe_out8_UNCONNECTED;
wire [0:0]NLW_inst_probe_out80_UNCONNECTED;
wire [0:0]NLW_inst_probe_out81_UNCONNECTED;
wire [0:0]NLW_inst_probe_out82_UNCONNECTED;
wire [0:0]NLW_inst_probe_out83_UNCONNECTED;
wire [0:0]NLW_inst_probe_out84_UNCONNECTED;
wire [0:0]NLW_inst_probe_out85_UNCONNECTED;
wire [0:0]NLW_inst_probe_out86_UNCONNECTED;
wire [0:0]NLW_inst_probe_out87_UNCONNECTED;
wire [0:0]NLW_inst_probe_out88_UNCONNECTED;
wire [0:0]NLW_inst_probe_out89_UNCONNECTED;
wire [0:0]NLW_inst_probe_out9_UNCONNECTED;
wire [0:0]NLW_inst_probe_out90_UNCONNECTED;
wire [0:0]NLW_inst_probe_out91_UNCONNECTED;
wire [0:0]NLW_inst_probe_out92_UNCONNECTED;
wire [0:0]NLW_inst_probe_out93_UNCONNECTED;
wire [0:0]NLW_inst_probe_out94_UNCONNECTED;
wire [0:0]NLW_inst_probe_out95_UNCONNECTED;
wire [0:0]NLW_inst_probe_out96_UNCONNECTED;
wire [0:0]NLW_inst_probe_out97_UNCONNECTED;
wire [0:0]NLW_inst_probe_out98_UNCONNECTED;
wire [0:0]NLW_inst_probe_out99_UNCONNECTED;
wire [16:0]NLW_inst_sl_oport0_UNCONNECTED;
(* C_BUILD_REVISION = "0" *)
(* C_BUS_ADDR_WIDTH = "17" *)
(* C_BUS_DATA_WIDTH = "16" *)
(* C_CORE_INFO1 = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
(* C_CORE_INFO2 = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
(* C_CORE_MAJOR_VER = "2" *)
(* C_CORE_MINOR_ALPHA_VER = "97" *)
(* C_CORE_MINOR_VER = "0" *)
(* C_CORE_TYPE = "2" *)
(* C_CSE_DRV_VER = "1" *)
(* C_EN_PROBE_IN_ACTIVITY = "1" *)
(* C_EN_SYNCHRONIZATION = "1" *)
(* C_MAJOR_VERSION = "2013" *)
(* C_MAX_NUM_PROBE = "256" *)
(* C_MAX_WIDTH_PER_PROBE = "256" *)
(* C_MINOR_VERSION = "1" *)
(* C_NEXT_SLAVE = "0" *)
(* C_NUM_PROBE_IN = "4" *)
(* C_NUM_PROBE_OUT = "0" *)
(* C_PIPE_IFACE = "0" *)
(* C_PROBE_IN0_WIDTH = "1" *)
(* C_PROBE_IN100_WIDTH = "1" *)
(* C_PROBE_IN101_WIDTH = "1" *)
(* C_PROBE_IN102_WIDTH = "1" *)
(* C_PROBE_IN103_WIDTH = "1" *)
(* C_PROBE_IN104_WIDTH = "1" *)
(* C_PROBE_IN105_WIDTH = "1" *)
(* C_PROBE_IN106_WIDTH = "1" *)
(* C_PROBE_IN107_WIDTH = "1" *)
(* C_PROBE_IN108_WIDTH = "1" *)
(* C_PROBE_IN109_WIDTH = "1" *)
(* C_PROBE_IN10_WIDTH = "1" *)
(* C_PROBE_IN110_WIDTH = "1" *)
(* C_PROBE_IN111_WIDTH = "1" *)
(* C_PROBE_IN112_WIDTH = "1" *)
(* C_PROBE_IN113_WIDTH = "1" *)
(* C_PROBE_IN114_WIDTH = "1" *)
(* C_PROBE_IN115_WIDTH = "1" *)
(* C_PROBE_IN116_WIDTH = "1" *)
(* C_PROBE_IN117_WIDTH = "1" *)
(* C_PROBE_IN118_WIDTH = "1" *)
(* C_PROBE_IN119_WIDTH = "1" *)
(* C_PROBE_IN11_WIDTH = "1" *)
(* C_PROBE_IN120_WIDTH = "1" *)
(* C_PROBE_IN121_WIDTH = "1" *)
(* C_PROBE_IN122_WIDTH = "1" *)
(* C_PROBE_IN123_WIDTH = "1" *)
(* C_PROBE_IN124_WIDTH = "1" *)
(* C_PROBE_IN125_WIDTH = "1" *)
(* C_PROBE_IN126_WIDTH = "1" *)
(* C_PROBE_IN127_WIDTH = "1" *)
(* C_PROBE_IN128_WIDTH = "1" *)
(* C_PROBE_IN129_WIDTH = "1" *)
(* C_PROBE_IN12_WIDTH = "1" *)
(* C_PROBE_IN130_WIDTH = "1" *)
(* C_PROBE_IN131_WIDTH = "1" *)
(* C_PROBE_IN132_WIDTH = "1" *)
(* C_PROBE_IN133_WIDTH = "1" *)
(* C_PROBE_IN134_WIDTH = "1" *)
(* C_PROBE_IN135_WIDTH = "1" *)
(* C_PROBE_IN136_WIDTH = "1" *)
(* C_PROBE_IN137_WIDTH = "1" *)
(* C_PROBE_IN138_WIDTH = "1" *)
(* C_PROBE_IN139_WIDTH = "1" *)
(* C_PROBE_IN13_WIDTH = "1" *)
(* C_PROBE_IN140_WIDTH = "1" *)
(* C_PROBE_IN141_WIDTH = "1" *)
(* C_PROBE_IN142_WIDTH = "1" *)
(* C_PROBE_IN143_WIDTH = "1" *)
(* C_PROBE_IN144_WIDTH = "1" *)
(* C_PROBE_IN145_WIDTH = "1" *)
(* C_PROBE_IN146_WIDTH = "1" *)
(* C_PROBE_IN147_WIDTH = "1" *)
(* C_PROBE_IN148_WIDTH = "1" *)
(* C_PROBE_IN149_WIDTH = "1" *)
(* C_PROBE_IN14_WIDTH = "1" *)
(* C_PROBE_IN150_WIDTH = "1" *)
(* C_PROBE_IN151_WIDTH = "1" *)
(* C_PROBE_IN152_WIDTH = "1" *)
(* C_PROBE_IN153_WIDTH = "1" *)
(* C_PROBE_IN154_WIDTH = "1" *)
(* C_PROBE_IN155_WIDTH = "1" *)
(* C_PROBE_IN156_WIDTH = "1" *)
(* C_PROBE_IN157_WIDTH = "1" *)
(* C_PROBE_IN158_WIDTH = "1" *)
(* C_PROBE_IN159_WIDTH = "1" *)
(* C_PROBE_IN15_WIDTH = "1" *)
(* C_PROBE_IN160_WIDTH = "1" *)
(* C_PROBE_IN161_WIDTH = "1" *)
(* C_PROBE_IN162_WIDTH = "1" *)
(* C_PROBE_IN163_WIDTH = "1" *)
(* C_PROBE_IN164_WIDTH = "1" *)
(* C_PROBE_IN165_WIDTH = "1" *)
(* C_PROBE_IN166_WIDTH = "1" *)
(* C_PROBE_IN167_WIDTH = "1" *)
(* C_PROBE_IN168_WIDTH = "1" *)
(* C_PROBE_IN169_WIDTH = "1" *)
(* C_PROBE_IN16_WIDTH = "1" *)
(* C_PROBE_IN170_WIDTH = "1" *)
(* C_PROBE_IN171_WIDTH = "1" *)
(* C_PROBE_IN172_WIDTH = "1" *)
(* C_PROBE_IN173_WIDTH = "1" *)
(* C_PROBE_IN174_WIDTH = "1" *)
(* C_PROBE_IN175_WIDTH = "1" *)
(* C_PROBE_IN176_WIDTH = "1" *)
(* C_PROBE_IN177_WIDTH = "1" *)
(* C_PROBE_IN178_WIDTH = "1" *)
(* C_PROBE_IN179_WIDTH = "1" *)
(* C_PROBE_IN17_WIDTH = "1" *)
(* C_PROBE_IN180_WIDTH = "1" *)
(* C_PROBE_IN181_WIDTH = "1" *)
(* C_PROBE_IN182_WIDTH = "1" *)
(* C_PROBE_IN183_WIDTH = "1" *)
(* C_PROBE_IN184_WIDTH = "1" *)
(* C_PROBE_IN185_WIDTH = "1" *)
(* C_PROBE_IN186_WIDTH = "1" *)
(* C_PROBE_IN187_WIDTH = "1" *)
(* C_PROBE_IN188_WIDTH = "1" *)
(* C_PROBE_IN189_WIDTH = "1" *)
(* C_PROBE_IN18_WIDTH = "1" *)
(* C_PROBE_IN190_WIDTH = "1" *)
(* C_PROBE_IN191_WIDTH = "1" *)
(* C_PROBE_IN192_WIDTH = "1" *)
(* C_PROBE_IN193_WIDTH = "1" *)
(* C_PROBE_IN194_WIDTH = "1" *)
(* C_PROBE_IN195_WIDTH = "1" *)
(* C_PROBE_IN196_WIDTH = "1" *)
(* C_PROBE_IN197_WIDTH = "1" *)
(* C_PROBE_IN198_WIDTH = "1" *)
(* C_PROBE_IN199_WIDTH = "1" *)
(* C_PROBE_IN19_WIDTH = "1" *)
(* C_PROBE_IN1_WIDTH = "1" *)
(* C_PROBE_IN200_WIDTH = "1" *)
(* C_PROBE_IN201_WIDTH = "1" *)
(* C_PROBE_IN202_WIDTH = "1" *)
(* C_PROBE_IN203_WIDTH = "1" *)
(* C_PROBE_IN204_WIDTH = "1" *)
(* C_PROBE_IN205_WIDTH = "1" *)
(* C_PROBE_IN206_WIDTH = "1" *)
(* C_PROBE_IN207_WIDTH = "1" *)
(* C_PROBE_IN208_WIDTH = "1" *)
(* C_PROBE_IN209_WIDTH = "1" *)
(* C_PROBE_IN20_WIDTH = "1" *)
(* C_PROBE_IN210_WIDTH = "1" *)
(* C_PROBE_IN211_WIDTH = "1" *)
(* C_PROBE_IN212_WIDTH = "1" *)
(* C_PROBE_IN213_WIDTH = "1" *)
(* C_PROBE_IN214_WIDTH = "1" *)
(* C_PROBE_IN215_WIDTH = "1" *)
(* C_PROBE_IN216_WIDTH = "1" *)
(* C_PROBE_IN217_WIDTH = "1" *)
(* C_PROBE_IN218_WIDTH = "1" *)
(* C_PROBE_IN219_WIDTH = "1" *)
(* C_PROBE_IN21_WIDTH = "1" *)
(* C_PROBE_IN220_WIDTH = "1" *)
(* C_PROBE_IN221_WIDTH = "1" *)
(* C_PROBE_IN222_WIDTH = "1" *)
(* C_PROBE_IN223_WIDTH = "1" *)
(* C_PROBE_IN224_WIDTH = "1" *)
(* C_PROBE_IN225_WIDTH = "1" *)
(* C_PROBE_IN226_WIDTH = "1" *)
(* C_PROBE_IN227_WIDTH = "1" *)
(* C_PROBE_IN228_WIDTH = "1" *)
(* C_PROBE_IN229_WIDTH = "1" *)
(* C_PROBE_IN22_WIDTH = "1" *)
(* C_PROBE_IN230_WIDTH = "1" *)
(* C_PROBE_IN231_WIDTH = "1" *)
(* C_PROBE_IN232_WIDTH = "1" *)
(* C_PROBE_IN233_WIDTH = "1" *)
(* C_PROBE_IN234_WIDTH = "1" *)
(* C_PROBE_IN235_WIDTH = "1" *)
(* C_PROBE_IN236_WIDTH = "1" *)
(* C_PROBE_IN237_WIDTH = "1" *)
(* C_PROBE_IN238_WIDTH = "1" *)
(* C_PROBE_IN239_WIDTH = "1" *)
(* C_PROBE_IN23_WIDTH = "1" *)
(* C_PROBE_IN240_WIDTH = "1" *)
(* C_PROBE_IN241_WIDTH = "1" *)
(* C_PROBE_IN242_WIDTH = "1" *)
(* C_PROBE_IN243_WIDTH = "1" *)
(* C_PROBE_IN244_WIDTH = "1" *)
(* C_PROBE_IN245_WIDTH = "1" *)
(* C_PROBE_IN246_WIDTH = "1" *)
(* C_PROBE_IN247_WIDTH = "1" *)
(* C_PROBE_IN248_WIDTH = "1" *)
(* C_PROBE_IN249_WIDTH = "1" *)
(* C_PROBE_IN24_WIDTH = "1" *)
(* C_PROBE_IN250_WIDTH = "1" *)
(* C_PROBE_IN251_WIDTH = "1" *)
(* C_PROBE_IN252_WIDTH = "1" *)
(* C_PROBE_IN253_WIDTH = "1" *)
(* C_PROBE_IN254_WIDTH = "1" *)
(* C_PROBE_IN255_WIDTH = "1" *)
(* C_PROBE_IN25_WIDTH = "1" *)
(* C_PROBE_IN26_WIDTH = "1" *)
(* C_PROBE_IN27_WIDTH = "1" *)
(* C_PROBE_IN28_WIDTH = "1" *)
(* C_PROBE_IN29_WIDTH = "1" *)
(* C_PROBE_IN2_WIDTH = "1" *)
(* C_PROBE_IN30_WIDTH = "1" *)
(* C_PROBE_IN31_WIDTH = "1" *)
(* C_PROBE_IN32_WIDTH = "1" *)
(* C_PROBE_IN33_WIDTH = "1" *)
(* C_PROBE_IN34_WIDTH = "1" *)
(* C_PROBE_IN35_WIDTH = "1" *)
(* C_PROBE_IN36_WIDTH = "1" *)
(* C_PROBE_IN37_WIDTH = "1" *)
(* C_PROBE_IN38_WIDTH = "1" *)
(* C_PROBE_IN39_WIDTH = "1" *)
(* C_PROBE_IN3_WIDTH = "1" *)
(* C_PROBE_IN40_WIDTH = "1" *)
(* C_PROBE_IN41_WIDTH = "1" *)
(* C_PROBE_IN42_WIDTH = "1" *)
(* C_PROBE_IN43_WIDTH = "1" *)
(* C_PROBE_IN44_WIDTH = "1" *)
(* C_PROBE_IN45_WIDTH = "1" *)
(* C_PROBE_IN46_WIDTH = "1" *)
(* C_PROBE_IN47_WIDTH = "1" *)
(* C_PROBE_IN48_WIDTH = "1" *)
(* C_PROBE_IN49_WIDTH = "1" *)
(* C_PROBE_IN4_WIDTH = "1" *)
(* C_PROBE_IN50_WIDTH = "1" *)
(* C_PROBE_IN51_WIDTH = "1" *)
(* C_PROBE_IN52_WIDTH = "1" *)
(* C_PROBE_IN53_WIDTH = "1" *)
(* C_PROBE_IN54_WIDTH = "1" *)
(* C_PROBE_IN55_WIDTH = "1" *)
(* C_PROBE_IN56_WIDTH = "1" *)
(* C_PROBE_IN57_WIDTH = "1" *)
(* C_PROBE_IN58_WIDTH = "1" *)
(* C_PROBE_IN59_WIDTH = "1" *)
(* C_PROBE_IN5_WIDTH = "1" *)
(* C_PROBE_IN60_WIDTH = "1" *)
(* C_PROBE_IN61_WIDTH = "1" *)
(* C_PROBE_IN62_WIDTH = "1" *)
(* C_PROBE_IN63_WIDTH = "1" *)
(* C_PROBE_IN64_WIDTH = "1" *)
(* C_PROBE_IN65_WIDTH = "1" *)
(* C_PROBE_IN66_WIDTH = "1" *)
(* C_PROBE_IN67_WIDTH = "1" *)
(* C_PROBE_IN68_WIDTH = "1" *)
(* C_PROBE_IN69_WIDTH = "1" *)
(* C_PROBE_IN6_WIDTH = "1" *)
(* C_PROBE_IN70_WIDTH = "1" *)
(* C_PROBE_IN71_WIDTH = "1" *)
(* C_PROBE_IN72_WIDTH = "1" *)
(* C_PROBE_IN73_WIDTH = "1" *)
(* C_PROBE_IN74_WIDTH = "1" *)
(* C_PROBE_IN75_WIDTH = "1" *)
(* C_PROBE_IN76_WIDTH = "1" *)
(* C_PROBE_IN77_WIDTH = "1" *)
(* C_PROBE_IN78_WIDTH = "1" *)
(* C_PROBE_IN79_WIDTH = "1" *)
(* C_PROBE_IN7_WIDTH = "1" *)
(* C_PROBE_IN80_WIDTH = "1" *)
(* C_PROBE_IN81_WIDTH = "1" *)
(* C_PROBE_IN82_WIDTH = "1" *)
(* C_PROBE_IN83_WIDTH = "1" *)
(* C_PROBE_IN84_WIDTH = "1" *)
(* C_PROBE_IN85_WIDTH = "1" *)
(* C_PROBE_IN86_WIDTH = "1" *)
(* C_PROBE_IN87_WIDTH = "1" *)
(* C_PROBE_IN88_WIDTH = "1" *)
(* C_PROBE_IN89_WIDTH = "1" *)
(* C_PROBE_IN8_WIDTH = "1" *)
(* C_PROBE_IN90_WIDTH = "1" *)
(* C_PROBE_IN91_WIDTH = "1" *)
(* C_PROBE_IN92_WIDTH = "1" *)
(* C_PROBE_IN93_WIDTH = "1" *)
(* C_PROBE_IN94_WIDTH = "1" *)
(* C_PROBE_IN95_WIDTH = "1" *)
(* C_PROBE_IN96_WIDTH = "1" *)
(* C_PROBE_IN97_WIDTH = "1" *)
(* C_PROBE_IN98_WIDTH = "1" *)
(* C_PROBE_IN99_WIDTH = "1" *)
(* C_PROBE_IN9_WIDTH = "1" *)
(* C_PROBE_OUT0_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT0_WIDTH = "1" *)
(* C_PROBE_OUT100_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT100_WIDTH = "1" *)
(* C_PROBE_OUT101_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT101_WIDTH = "1" *)
(* C_PROBE_OUT102_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT102_WIDTH = "1" *)
(* C_PROBE_OUT103_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT103_WIDTH = "1" *)
(* C_PROBE_OUT104_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT104_WIDTH = "1" *)
(* C_PROBE_OUT105_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT105_WIDTH = "1" *)
(* C_PROBE_OUT106_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT106_WIDTH = "1" *)
(* C_PROBE_OUT107_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT107_WIDTH = "1" *)
(* C_PROBE_OUT108_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT108_WIDTH = "1" *)
(* C_PROBE_OUT109_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT109_WIDTH = "1" *)
(* C_PROBE_OUT10_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT10_WIDTH = "1" *)
(* C_PROBE_OUT110_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT110_WIDTH = "1" *)
(* C_PROBE_OUT111_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT111_WIDTH = "1" *)
(* C_PROBE_OUT112_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT112_WIDTH = "1" *)
(* C_PROBE_OUT113_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT113_WIDTH = "1" *)
(* C_PROBE_OUT114_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT114_WIDTH = "1" *)
(* C_PROBE_OUT115_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT115_WIDTH = "1" *)
(* C_PROBE_OUT116_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT116_WIDTH = "1" *)
(* C_PROBE_OUT117_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT117_WIDTH = "1" *)
(* C_PROBE_OUT118_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT118_WIDTH = "1" *)
(* C_PROBE_OUT119_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT119_WIDTH = "1" *)
(* C_PROBE_OUT11_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT11_WIDTH = "1" *)
(* C_PROBE_OUT120_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT120_WIDTH = "1" *)
(* C_PROBE_OUT121_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT121_WIDTH = "1" *)
(* C_PROBE_OUT122_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT122_WIDTH = "1" *)
(* C_PROBE_OUT123_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT123_WIDTH = "1" *)
(* C_PROBE_OUT124_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT124_WIDTH = "1" *)
(* C_PROBE_OUT125_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT125_WIDTH = "1" *)
(* C_PROBE_OUT126_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT126_WIDTH = "1" *)
(* C_PROBE_OUT127_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT127_WIDTH = "1" *)
(* C_PROBE_OUT128_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT128_WIDTH = "1" *)
(* C_PROBE_OUT129_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT129_WIDTH = "1" *)
(* C_PROBE_OUT12_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT12_WIDTH = "1" *)
(* C_PROBE_OUT130_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT130_WIDTH = "1" *)
(* C_PROBE_OUT131_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT131_WIDTH = "1" *)
(* C_PROBE_OUT132_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT132_WIDTH = "1" *)
(* C_PROBE_OUT133_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT133_WIDTH = "1" *)
(* C_PROBE_OUT134_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT134_WIDTH = "1" *)
(* C_PROBE_OUT135_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT135_WIDTH = "1" *)
(* C_PROBE_OUT136_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT136_WIDTH = "1" *)
(* C_PROBE_OUT137_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT137_WIDTH = "1" *)
(* C_PROBE_OUT138_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT138_WIDTH = "1" *)
(* C_PROBE_OUT139_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT139_WIDTH = "1" *)
(* C_PROBE_OUT13_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT13_WIDTH = "1" *)
(* C_PROBE_OUT140_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT140_WIDTH = "1" *)
(* C_PROBE_OUT141_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT141_WIDTH = "1" *)
(* C_PROBE_OUT142_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT142_WIDTH = "1" *)
(* C_PROBE_OUT143_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT143_WIDTH = "1" *)
(* C_PROBE_OUT144_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT144_WIDTH = "1" *)
(* C_PROBE_OUT145_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT145_WIDTH = "1" *)
(* C_PROBE_OUT146_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT146_WIDTH = "1" *)
(* C_PROBE_OUT147_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT147_WIDTH = "1" *)
(* C_PROBE_OUT148_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT148_WIDTH = "1" *)
(* C_PROBE_OUT149_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT149_WIDTH = "1" *)
(* C_PROBE_OUT14_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT14_WIDTH = "1" *)
(* C_PROBE_OUT150_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT150_WIDTH = "1" *)
(* C_PROBE_OUT151_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT151_WIDTH = "1" *)
(* C_PROBE_OUT152_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT152_WIDTH = "1" *)
(* C_PROBE_OUT153_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT153_WIDTH = "1" *)
(* C_PROBE_OUT154_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT154_WIDTH = "1" *)
(* C_PROBE_OUT155_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT155_WIDTH = "1" *)
(* C_PROBE_OUT156_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT156_WIDTH = "1" *)
(* C_PROBE_OUT157_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT157_WIDTH = "1" *)
(* C_PROBE_OUT158_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT158_WIDTH = "1" *)
(* C_PROBE_OUT159_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT159_WIDTH = "1" *)
(* C_PROBE_OUT15_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT15_WIDTH = "1" *)
(* C_PROBE_OUT160_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT160_WIDTH = "1" *)
(* C_PROBE_OUT161_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT161_WIDTH = "1" *)
(* C_PROBE_OUT162_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT162_WIDTH = "1" *)
(* C_PROBE_OUT163_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT163_WIDTH = "1" *)
(* C_PROBE_OUT164_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT164_WIDTH = "1" *)
(* C_PROBE_OUT165_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT165_WIDTH = "1" *)
(* C_PROBE_OUT166_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT166_WIDTH = "1" *)
(* C_PROBE_OUT167_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT167_WIDTH = "1" *)
(* C_PROBE_OUT168_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT168_WIDTH = "1" *)
(* C_PROBE_OUT169_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT169_WIDTH = "1" *)
(* C_PROBE_OUT16_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT16_WIDTH = "1" *)
(* C_PROBE_OUT170_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT170_WIDTH = "1" *)
(* C_PROBE_OUT171_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT171_WIDTH = "1" *)
(* C_PROBE_OUT172_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT172_WIDTH = "1" *)
(* C_PROBE_OUT173_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT173_WIDTH = "1" *)
(* C_PROBE_OUT174_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT174_WIDTH = "1" *)
(* C_PROBE_OUT175_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT175_WIDTH = "1" *)
(* C_PROBE_OUT176_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT176_WIDTH = "1" *)
(* C_PROBE_OUT177_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT177_WIDTH = "1" *)
(* C_PROBE_OUT178_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT178_WIDTH = "1" *)
(* C_PROBE_OUT179_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT179_WIDTH = "1" *)
(* C_PROBE_OUT17_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT17_WIDTH = "1" *)
(* C_PROBE_OUT180_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT180_WIDTH = "1" *)
(* C_PROBE_OUT181_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT181_WIDTH = "1" *)
(* C_PROBE_OUT182_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT182_WIDTH = "1" *)
(* C_PROBE_OUT183_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT183_WIDTH = "1" *)
(* C_PROBE_OUT184_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT184_WIDTH = "1" *)
(* C_PROBE_OUT185_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT185_WIDTH = "1" *)
(* C_PROBE_OUT186_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT186_WIDTH = "1" *)
(* C_PROBE_OUT187_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT187_WIDTH = "1" *)
(* C_PROBE_OUT188_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT188_WIDTH = "1" *)
(* C_PROBE_OUT189_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT189_WIDTH = "1" *)
(* C_PROBE_OUT18_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT18_WIDTH = "1" *)
(* C_PROBE_OUT190_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT190_WIDTH = "1" *)
(* C_PROBE_OUT191_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT191_WIDTH = "1" *)
(* C_PROBE_OUT192_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT192_WIDTH = "1" *)
(* C_PROBE_OUT193_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT193_WIDTH = "1" *)
(* C_PROBE_OUT194_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT194_WIDTH = "1" *)
(* C_PROBE_OUT195_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT195_WIDTH = "1" *)
(* C_PROBE_OUT196_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT196_WIDTH = "1" *)
(* C_PROBE_OUT197_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT197_WIDTH = "1" *)
(* C_PROBE_OUT198_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT198_WIDTH = "1" *)
(* C_PROBE_OUT199_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT199_WIDTH = "1" *)
(* C_PROBE_OUT19_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT19_WIDTH = "1" *)
(* C_PROBE_OUT1_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT1_WIDTH = "1" *)
(* C_PROBE_OUT200_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT200_WIDTH = "1" *)
(* C_PROBE_OUT201_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT201_WIDTH = "1" *)
(* C_PROBE_OUT202_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT202_WIDTH = "1" *)
(* C_PROBE_OUT203_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT203_WIDTH = "1" *)
(* C_PROBE_OUT204_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT204_WIDTH = "1" *)
(* C_PROBE_OUT205_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT205_WIDTH = "1" *)
(* C_PROBE_OUT206_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT206_WIDTH = "1" *)
(* C_PROBE_OUT207_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT207_WIDTH = "1" *)
(* C_PROBE_OUT208_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT208_WIDTH = "1" *)
(* C_PROBE_OUT209_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT209_WIDTH = "1" *)
(* C_PROBE_OUT20_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT20_WIDTH = "1" *)
(* C_PROBE_OUT210_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT210_WIDTH = "1" *)
(* C_PROBE_OUT211_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT211_WIDTH = "1" *)
(* C_PROBE_OUT212_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT212_WIDTH = "1" *)
(* C_PROBE_OUT213_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT213_WIDTH = "1" *)
(* C_PROBE_OUT214_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT214_WIDTH = "1" *)
(* C_PROBE_OUT215_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT215_WIDTH = "1" *)
(* C_PROBE_OUT216_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT216_WIDTH = "1" *)
(* C_PROBE_OUT217_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT217_WIDTH = "1" *)
(* C_PROBE_OUT218_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT218_WIDTH = "1" *)
(* C_PROBE_OUT219_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT219_WIDTH = "1" *)
(* C_PROBE_OUT21_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT21_WIDTH = "1" *)
(* C_PROBE_OUT220_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT220_WIDTH = "1" *)
(* C_PROBE_OUT221_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT221_WIDTH = "1" *)
(* C_PROBE_OUT222_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT222_WIDTH = "1" *)
(* C_PROBE_OUT223_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT223_WIDTH = "1" *)
(* C_PROBE_OUT224_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT224_WIDTH = "1" *)
(* C_PROBE_OUT225_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT225_WIDTH = "1" *)
(* C_PROBE_OUT226_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT226_WIDTH = "1" *)
(* C_PROBE_OUT227_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT227_WIDTH = "1" *)
(* C_PROBE_OUT228_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT228_WIDTH = "1" *)
(* C_PROBE_OUT229_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT229_WIDTH = "1" *)
(* C_PROBE_OUT22_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT22_WIDTH = "1" *)
(* C_PROBE_OUT230_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT230_WIDTH = "1" *)
(* C_PROBE_OUT231_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT231_WIDTH = "1" *)
(* C_PROBE_OUT232_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT232_WIDTH = "1" *)
(* C_PROBE_OUT233_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT233_WIDTH = "1" *)
(* C_PROBE_OUT234_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT234_WIDTH = "1" *)
(* C_PROBE_OUT235_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT235_WIDTH = "1" *)
(* C_PROBE_OUT236_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT236_WIDTH = "1" *)
(* C_PROBE_OUT237_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT237_WIDTH = "1" *)
(* C_PROBE_OUT238_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT238_WIDTH = "1" *)
(* C_PROBE_OUT239_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT239_WIDTH = "1" *)
(* C_PROBE_OUT23_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT23_WIDTH = "1" *)
(* C_PROBE_OUT240_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT240_WIDTH = "1" *)
(* C_PROBE_OUT241_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT241_WIDTH = "1" *)
(* C_PROBE_OUT242_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT242_WIDTH = "1" *)
(* C_PROBE_OUT243_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT243_WIDTH = "1" *)
(* C_PROBE_OUT244_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT244_WIDTH = "1" *)
(* C_PROBE_OUT245_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT245_WIDTH = "1" *)
(* C_PROBE_OUT246_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT246_WIDTH = "1" *)
(* C_PROBE_OUT247_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT247_WIDTH = "1" *)
(* C_PROBE_OUT248_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT248_WIDTH = "1" *)
(* C_PROBE_OUT249_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT249_WIDTH = "1" *)
(* C_PROBE_OUT24_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT24_WIDTH = "1" *)
(* C_PROBE_OUT250_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT250_WIDTH = "1" *)
(* C_PROBE_OUT251_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT251_WIDTH = "1" *)
(* C_PROBE_OUT252_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT252_WIDTH = "1" *)
(* C_PROBE_OUT253_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT253_WIDTH = "1" *)
(* C_PROBE_OUT254_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT254_WIDTH = "1" *)
(* C_PROBE_OUT255_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT255_WIDTH = "1" *)
(* C_PROBE_OUT25_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT25_WIDTH = "1" *)
(* C_PROBE_OUT26_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT26_WIDTH = "1" *)
(* C_PROBE_OUT27_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT27_WIDTH = "1" *)
(* C_PROBE_OUT28_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT28_WIDTH = "1" *)
(* C_PROBE_OUT29_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT29_WIDTH = "1" *)
(* C_PROBE_OUT2_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT2_WIDTH = "1" *)
(* C_PROBE_OUT30_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT30_WIDTH = "1" *)
(* C_PROBE_OUT31_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT31_WIDTH = "1" *)
(* C_PROBE_OUT32_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT32_WIDTH = "1" *)
(* C_PROBE_OUT33_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT33_WIDTH = "1" *)
(* C_PROBE_OUT34_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT34_WIDTH = "1" *)
(* C_PROBE_OUT35_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT35_WIDTH = "1" *)
(* C_PROBE_OUT36_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT36_WIDTH = "1" *)
(* C_PROBE_OUT37_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT37_WIDTH = "1" *)
(* C_PROBE_OUT38_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT38_WIDTH = "1" *)
(* C_PROBE_OUT39_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT39_WIDTH = "1" *)
(* C_PROBE_OUT3_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT3_WIDTH = "1" *)
(* C_PROBE_OUT40_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT40_WIDTH = "1" *)
(* C_PROBE_OUT41_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT41_WIDTH = "1" *)
(* C_PROBE_OUT42_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT42_WIDTH = "1" *)
(* C_PROBE_OUT43_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT43_WIDTH = "1" *)
(* C_PROBE_OUT44_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT44_WIDTH = "1" *)
(* C_PROBE_OUT45_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT45_WIDTH = "1" *)
(* C_PROBE_OUT46_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT46_WIDTH = "1" *)
(* C_PROBE_OUT47_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT47_WIDTH = "1" *)
(* C_PROBE_OUT48_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT48_WIDTH = "1" *)
(* C_PROBE_OUT49_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT49_WIDTH = "1" *)
(* C_PROBE_OUT4_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT4_WIDTH = "1" *)
(* C_PROBE_OUT50_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT50_WIDTH = "1" *)
(* C_PROBE_OUT51_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT51_WIDTH = "1" *)
(* C_PROBE_OUT52_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT52_WIDTH = "1" *)
(* C_PROBE_OUT53_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT53_WIDTH = "1" *)
(* C_PROBE_OUT54_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT54_WIDTH = "1" *)
(* C_PROBE_OUT55_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT55_WIDTH = "1" *)
(* C_PROBE_OUT56_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT56_WIDTH = "1" *)
(* C_PROBE_OUT57_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT57_WIDTH = "1" *)
(* C_PROBE_OUT58_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT58_WIDTH = "1" *)
(* C_PROBE_OUT59_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT59_WIDTH = "1" *)
(* C_PROBE_OUT5_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT5_WIDTH = "1" *)
(* C_PROBE_OUT60_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT60_WIDTH = "1" *)
(* C_PROBE_OUT61_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT61_WIDTH = "1" *)
(* C_PROBE_OUT62_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT62_WIDTH = "1" *)
(* C_PROBE_OUT63_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT63_WIDTH = "1" *)
(* C_PROBE_OUT64_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT64_WIDTH = "1" *)
(* C_PROBE_OUT65_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT65_WIDTH = "1" *)
(* C_PROBE_OUT66_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT66_WIDTH = "1" *)
(* C_PROBE_OUT67_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT67_WIDTH = "1" *)
(* C_PROBE_OUT68_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT68_WIDTH = "1" *)
(* C_PROBE_OUT69_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT69_WIDTH = "1" *)
(* C_PROBE_OUT6_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT6_WIDTH = "1" *)
(* C_PROBE_OUT70_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT70_WIDTH = "1" *)
(* C_PROBE_OUT71_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT71_WIDTH = "1" *)
(* C_PROBE_OUT72_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT72_WIDTH = "1" *)
(* C_PROBE_OUT73_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT73_WIDTH = "1" *)
(* C_PROBE_OUT74_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT74_WIDTH = "1" *)
(* C_PROBE_OUT75_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT75_WIDTH = "1" *)
(* C_PROBE_OUT76_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT76_WIDTH = "1" *)
(* C_PROBE_OUT77_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT77_WIDTH = "1" *)
(* C_PROBE_OUT78_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT78_WIDTH = "1" *)
(* C_PROBE_OUT79_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT79_WIDTH = "1" *)
(* C_PROBE_OUT7_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT7_WIDTH = "1" *)
(* C_PROBE_OUT80_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT80_WIDTH = "1" *)
(* C_PROBE_OUT81_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT81_WIDTH = "1" *)
(* C_PROBE_OUT82_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT82_WIDTH = "1" *)
(* C_PROBE_OUT83_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT83_WIDTH = "1" *)
(* C_PROBE_OUT84_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT84_WIDTH = "1" *)
(* C_PROBE_OUT85_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT85_WIDTH = "1" *)
(* C_PROBE_OUT86_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT86_WIDTH = "1" *)
(* C_PROBE_OUT87_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT87_WIDTH = "1" *)
(* C_PROBE_OUT88_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT88_WIDTH = "1" *)
(* C_PROBE_OUT89_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT89_WIDTH = "1" *)
(* C_PROBE_OUT8_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT8_WIDTH = "1" *)
(* C_PROBE_OUT90_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT90_WIDTH = "1" *)
(* C_PROBE_OUT91_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT91_WIDTH = "1" *)
(* C_PROBE_OUT92_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT92_WIDTH = "1" *)
(* C_PROBE_OUT93_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT93_WIDTH = "1" *)
(* C_PROBE_OUT94_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT94_WIDTH = "1" *)
(* C_PROBE_OUT95_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT95_WIDTH = "1" *)
(* C_PROBE_OUT96_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT96_WIDTH = "1" *)
(* C_PROBE_OUT97_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT97_WIDTH = "1" *)
(* C_PROBE_OUT98_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT98_WIDTH = "1" *)
(* C_PROBE_OUT99_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT99_WIDTH = "1" *)
(* C_PROBE_OUT9_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT9_WIDTH = "1" *)
(* C_USE_TEST_REG = "1" *)
(* C_XDEVICEFAMILY = "kintex7" *)
(* C_XLNX_HW_PROBE_INFO = "DEFAULT" *)
(* C_XSDB_SLAVE_TYPE = "33" *)
(* DONT_TOUCH *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
(* LC_HIGH_BIT_POS_PROBE_OUT0 = "16'b0000000000000000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT1 = "16'b0000000000000001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT10 = "16'b0000000000001010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT100 = "16'b0000000001100100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT101 = "16'b0000000001100101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT102 = "16'b0000000001100110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT103 = "16'b0000000001100111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT104 = "16'b0000000001101000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT105 = "16'b0000000001101001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT106 = "16'b0000000001101010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT107 = "16'b0000000001101011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT108 = "16'b0000000001101100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT109 = "16'b0000000001101101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT11 = "16'b0000000000001011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT110 = "16'b0000000001101110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT111 = "16'b0000000001101111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT112 = "16'b0000000001110000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT113 = "16'b0000000001110001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT114 = "16'b0000000001110010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT115 = "16'b0000000001110011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT116 = "16'b0000000001110100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT117 = "16'b0000000001110101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT118 = "16'b0000000001110110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT119 = "16'b0000000001110111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT12 = "16'b0000000000001100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT120 = "16'b0000000001111000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT121 = "16'b0000000001111001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT122 = "16'b0000000001111010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT123 = "16'b0000000001111011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT124 = "16'b0000000001111100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT125 = "16'b0000000001111101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT126 = "16'b0000000001111110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT127 = "16'b0000000001111111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT128 = "16'b0000000010000000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT129 = "16'b0000000010000001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT13 = "16'b0000000000001101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT130 = "16'b0000000010000010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT131 = "16'b0000000010000011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT132 = "16'b0000000010000100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT133 = "16'b0000000010000101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT134 = "16'b0000000010000110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT135 = "16'b0000000010000111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT136 = "16'b0000000010001000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT137 = "16'b0000000010001001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT138 = "16'b0000000010001010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT139 = "16'b0000000010001011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT14 = "16'b0000000000001110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT140 = "16'b0000000010001100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT141 = "16'b0000000010001101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT142 = "16'b0000000010001110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT143 = "16'b0000000010001111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT144 = "16'b0000000010010000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT145 = "16'b0000000010010001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT146 = "16'b0000000010010010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT147 = "16'b0000000010010011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT148 = "16'b0000000010010100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT149 = "16'b0000000010010101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT15 = "16'b0000000000001111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT150 = "16'b0000000010010110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT151 = "16'b0000000010010111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT152 = "16'b0000000010011000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT153 = "16'b0000000010011001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT154 = "16'b0000000010011010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT155 = "16'b0000000010011011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT156 = "16'b0000000010011100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT157 = "16'b0000000010011101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT158 = "16'b0000000010011110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT159 = "16'b0000000010011111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT16 = "16'b0000000000010000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT160 = "16'b0000000010100000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT161 = "16'b0000000010100001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT162 = "16'b0000000010100010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT163 = "16'b0000000010100011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT164 = "16'b0000000010100100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT165 = "16'b0000000010100101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT166 = "16'b0000000010100110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT167 = "16'b0000000010100111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT168 = "16'b0000000010101000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT169 = "16'b0000000010101001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT17 = "16'b0000000000010001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT170 = "16'b0000000010101010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT171 = "16'b0000000010101011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT172 = "16'b0000000010101100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT173 = "16'b0000000010101101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT174 = "16'b0000000010101110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT175 = "16'b0000000010101111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT176 = "16'b0000000010110000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT177 = "16'b0000000010110001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT178 = "16'b0000000010110010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT179 = "16'b0000000010110011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT18 = "16'b0000000000010010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT180 = "16'b0000000010110100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT181 = "16'b0000000010110101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT182 = "16'b0000000010110110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT183 = "16'b0000000010110111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT184 = "16'b0000000010111000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT185 = "16'b0000000010111001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT186 = "16'b0000000010111010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT187 = "16'b0000000010111011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT188 = "16'b0000000010111100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT189 = "16'b0000000010111101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT19 = "16'b0000000000010011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT190 = "16'b0000000010111110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT191 = "16'b0000000010111111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT192 = "16'b0000000011000000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT193 = "16'b0000000011000001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT194 = "16'b0000000011000010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT195 = "16'b0000000011000011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT196 = "16'b0000000011000100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT197 = "16'b0000000011000101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT198 = "16'b0000000011000110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT199 = "16'b0000000011000111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT2 = "16'b0000000000000010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT20 = "16'b0000000000010100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT200 = "16'b0000000011001000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT201 = "16'b0000000011001001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT202 = "16'b0000000011001010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT203 = "16'b0000000011001011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT204 = "16'b0000000011001100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT205 = "16'b0000000011001101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT206 = "16'b0000000011001110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT207 = "16'b0000000011001111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT208 = "16'b0000000011010000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT209 = "16'b0000000011010001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT21 = "16'b0000000000010101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT210 = "16'b0000000011010010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT211 = "16'b0000000011010011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT212 = "16'b0000000011010100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT213 = "16'b0000000011010101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT214 = "16'b0000000011010110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT215 = "16'b0000000011010111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT216 = "16'b0000000011011000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT217 = "16'b0000000011011001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT218 = "16'b0000000011011010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT219 = "16'b0000000011011011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT22 = "16'b0000000000010110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT220 = "16'b0000000011011100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT221 = "16'b0000000011011101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT222 = "16'b0000000011011110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT223 = "16'b0000000011011111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT224 = "16'b0000000011100000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT225 = "16'b0000000011100001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT226 = "16'b0000000011100010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT227 = "16'b0000000011100011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT228 = "16'b0000000011100100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT229 = "16'b0000000011100101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT23 = "16'b0000000000010111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT230 = "16'b0000000011100110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT231 = "16'b0000000011100111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT232 = "16'b0000000011101000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT233 = "16'b0000000011101001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT234 = "16'b0000000011101010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT235 = "16'b0000000011101011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT236 = "16'b0000000011101100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT237 = "16'b0000000011101101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT238 = "16'b0000000011101110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT239 = "16'b0000000011101111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT24 = "16'b0000000000011000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT240 = "16'b0000000011110000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT241 = "16'b0000000011110001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT242 = "16'b0000000011110010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT243 = "16'b0000000011110011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT244 = "16'b0000000011110100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT245 = "16'b0000000011110101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT246 = "16'b0000000011110110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT247 = "16'b0000000011110111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT248 = "16'b0000000011111000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT249 = "16'b0000000011111001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT25 = "16'b0000000000011001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT250 = "16'b0000000011111010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT251 = "16'b0000000011111011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT252 = "16'b0000000011111100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT253 = "16'b0000000011111101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT254 = "16'b0000000011111110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT255 = "16'b0000000011111111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT26 = "16'b0000000000011010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT27 = "16'b0000000000011011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT28 = "16'b0000000000011100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT29 = "16'b0000000000011101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT3 = "16'b0000000000000011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT30 = "16'b0000000000011110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT31 = "16'b0000000000011111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT32 = "16'b0000000000100000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT33 = "16'b0000000000100001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT34 = "16'b0000000000100010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT35 = "16'b0000000000100011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT36 = "16'b0000000000100100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT37 = "16'b0000000000100101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT38 = "16'b0000000000100110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT39 = "16'b0000000000100111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT4 = "16'b0000000000000100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT40 = "16'b0000000000101000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT41 = "16'b0000000000101001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT42 = "16'b0000000000101010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT43 = "16'b0000000000101011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT44 = "16'b0000000000101100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT45 = "16'b0000000000101101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT46 = "16'b0000000000101110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT47 = "16'b0000000000101111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT48 = "16'b0000000000110000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT49 = "16'b0000000000110001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT5 = "16'b0000000000000101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT50 = "16'b0000000000110010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT51 = "16'b0000000000110011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT52 = "16'b0000000000110100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT53 = "16'b0000000000110101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT54 = "16'b0000000000110110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT55 = "16'b0000000000110111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT56 = "16'b0000000000111000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT57 = "16'b0000000000111001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT58 = "16'b0000000000111010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT59 = "16'b0000000000111011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT6 = "16'b0000000000000110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT60 = "16'b0000000000111100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT61 = "16'b0000000000111101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT62 = "16'b0000000000111110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT63 = "16'b0000000000111111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT64 = "16'b0000000001000000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT65 = "16'b0000000001000001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT66 = "16'b0000000001000010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT67 = "16'b0000000001000011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT68 = "16'b0000000001000100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT69 = "16'b0000000001000101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT7 = "16'b0000000000000111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT70 = "16'b0000000001000110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT71 = "16'b0000000001000111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT72 = "16'b0000000001001000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT73 = "16'b0000000001001001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT74 = "16'b0000000001001010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT75 = "16'b0000000001001011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT76 = "16'b0000000001001100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT77 = "16'b0000000001001101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT78 = "16'b0000000001001110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT79 = "16'b0000000001001111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT8 = "16'b0000000000001000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT80 = "16'b0000000001010000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT81 = "16'b0000000001010001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT82 = "16'b0000000001010010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT83 = "16'b0000000001010011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT84 = "16'b0000000001010100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT85 = "16'b0000000001010101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT86 = "16'b0000000001010110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT87 = "16'b0000000001010111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT88 = "16'b0000000001011000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT89 = "16'b0000000001011001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT9 = "16'b0000000000001001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT90 = "16'b0000000001011010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT91 = "16'b0000000001011011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT92 = "16'b0000000001011100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT93 = "16'b0000000001011101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT94 = "16'b0000000001011110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT95 = "16'b0000000001011111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT96 = "16'b0000000001100000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT97 = "16'b0000000001100001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT98 = "16'b0000000001100010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT99 = "16'b0000000001100011" *)
(* LC_LOW_BIT_POS_PROBE_OUT0 = "16'b0000000000000000" *)
(* LC_LOW_BIT_POS_PROBE_OUT1 = "16'b0000000000000001" *)
(* LC_LOW_BIT_POS_PROBE_OUT10 = "16'b0000000000001010" *)
(* LC_LOW_BIT_POS_PROBE_OUT100 = "16'b0000000001100100" *)
(* LC_LOW_BIT_POS_PROBE_OUT101 = "16'b0000000001100101" *)
(* LC_LOW_BIT_POS_PROBE_OUT102 = "16'b0000000001100110" *)
(* LC_LOW_BIT_POS_PROBE_OUT103 = "16'b0000000001100111" *)
(* LC_LOW_BIT_POS_PROBE_OUT104 = "16'b0000000001101000" *)
(* LC_LOW_BIT_POS_PROBE_OUT105 = "16'b0000000001101001" *)
(* LC_LOW_BIT_POS_PROBE_OUT106 = "16'b0000000001101010" *)
(* LC_LOW_BIT_POS_PROBE_OUT107 = "16'b0000000001101011" *)
(* LC_LOW_BIT_POS_PROBE_OUT108 = "16'b0000000001101100" *)
(* LC_LOW_BIT_POS_PROBE_OUT109 = "16'b0000000001101101" *)
(* LC_LOW_BIT_POS_PROBE_OUT11 = "16'b0000000000001011" *)
(* LC_LOW_BIT_POS_PROBE_OUT110 = "16'b0000000001101110" *)
(* LC_LOW_BIT_POS_PROBE_OUT111 = "16'b0000000001101111" *)
(* LC_LOW_BIT_POS_PROBE_OUT112 = "16'b0000000001110000" *)
(* LC_LOW_BIT_POS_PROBE_OUT113 = "16'b0000000001110001" *)
(* LC_LOW_BIT_POS_PROBE_OUT114 = "16'b0000000001110010" *)
(* LC_LOW_BIT_POS_PROBE_OUT115 = "16'b0000000001110011" *)
(* LC_LOW_BIT_POS_PROBE_OUT116 = "16'b0000000001110100" *)
(* LC_LOW_BIT_POS_PROBE_OUT117 = "16'b0000000001110101" *)
(* LC_LOW_BIT_POS_PROBE_OUT118 = "16'b0000000001110110" *)
(* LC_LOW_BIT_POS_PROBE_OUT119 = "16'b0000000001110111" *)
(* LC_LOW_BIT_POS_PROBE_OUT12 = "16'b0000000000001100" *)
(* LC_LOW_BIT_POS_PROBE_OUT120 = "16'b0000000001111000" *)
(* LC_LOW_BIT_POS_PROBE_OUT121 = "16'b0000000001111001" *)
(* LC_LOW_BIT_POS_PROBE_OUT122 = "16'b0000000001111010" *)
(* LC_LOW_BIT_POS_PROBE_OUT123 = "16'b0000000001111011" *)
(* LC_LOW_BIT_POS_PROBE_OUT124 = "16'b0000000001111100" *)
(* LC_LOW_BIT_POS_PROBE_OUT125 = "16'b0000000001111101" *)
(* LC_LOW_BIT_POS_PROBE_OUT126 = "16'b0000000001111110" *)
(* LC_LOW_BIT_POS_PROBE_OUT127 = "16'b0000000001111111" *)
(* LC_LOW_BIT_POS_PROBE_OUT128 = "16'b0000000010000000" *)
(* LC_LOW_BIT_POS_PROBE_OUT129 = "16'b0000000010000001" *)
(* LC_LOW_BIT_POS_PROBE_OUT13 = "16'b0000000000001101" *)
(* LC_LOW_BIT_POS_PROBE_OUT130 = "16'b0000000010000010" *)
(* LC_LOW_BIT_POS_PROBE_OUT131 = "16'b0000000010000011" *)
(* LC_LOW_BIT_POS_PROBE_OUT132 = "16'b0000000010000100" *)
(* LC_LOW_BIT_POS_PROBE_OUT133 = "16'b0000000010000101" *)
(* LC_LOW_BIT_POS_PROBE_OUT134 = "16'b0000000010000110" *)
(* LC_LOW_BIT_POS_PROBE_OUT135 = "16'b0000000010000111" *)
(* LC_LOW_BIT_POS_PROBE_OUT136 = "16'b0000000010001000" *)
(* LC_LOW_BIT_POS_PROBE_OUT137 = "16'b0000000010001001" *)
(* LC_LOW_BIT_POS_PROBE_OUT138 = "16'b0000000010001010" *)
(* LC_LOW_BIT_POS_PROBE_OUT139 = "16'b0000000010001011" *)
(* LC_LOW_BIT_POS_PROBE_OUT14 = "16'b0000000000001110" *)
(* LC_LOW_BIT_POS_PROBE_OUT140 = "16'b0000000010001100" *)
(* LC_LOW_BIT_POS_PROBE_OUT141 = "16'b0000000010001101" *)
(* LC_LOW_BIT_POS_PROBE_OUT142 = "16'b0000000010001110" *)
(* LC_LOW_BIT_POS_PROBE_OUT143 = "16'b0000000010001111" *)
(* LC_LOW_BIT_POS_PROBE_OUT144 = "16'b0000000010010000" *)
(* LC_LOW_BIT_POS_PROBE_OUT145 = "16'b0000000010010001" *)
(* LC_LOW_BIT_POS_PROBE_OUT146 = "16'b0000000010010010" *)
(* LC_LOW_BIT_POS_PROBE_OUT147 = "16'b0000000010010011" *)
(* LC_LOW_BIT_POS_PROBE_OUT148 = "16'b0000000010010100" *)
(* LC_LOW_BIT_POS_PROBE_OUT149 = "16'b0000000010010101" *)
(* LC_LOW_BIT_POS_PROBE_OUT15 = "16'b0000000000001111" *)
(* LC_LOW_BIT_POS_PROBE_OUT150 = "16'b0000000010010110" *)
(* LC_LOW_BIT_POS_PROBE_OUT151 = "16'b0000000010010111" *)
(* LC_LOW_BIT_POS_PROBE_OUT152 = "16'b0000000010011000" *)
(* LC_LOW_BIT_POS_PROBE_OUT153 = "16'b0000000010011001" *)
(* LC_LOW_BIT_POS_PROBE_OUT154 = "16'b0000000010011010" *)
(* LC_LOW_BIT_POS_PROBE_OUT155 = "16'b0000000010011011" *)
(* LC_LOW_BIT_POS_PROBE_OUT156 = "16'b0000000010011100" *)
(* LC_LOW_BIT_POS_PROBE_OUT157 = "16'b0000000010011101" *)
(* LC_LOW_BIT_POS_PROBE_OUT158 = "16'b0000000010011110" *)
(* LC_LOW_BIT_POS_PROBE_OUT159 = "16'b0000000010011111" *)
(* LC_LOW_BIT_POS_PROBE_OUT16 = "16'b0000000000010000" *)
(* LC_LOW_BIT_POS_PROBE_OUT160 = "16'b0000000010100000" *)
(* LC_LOW_BIT_POS_PROBE_OUT161 = "16'b0000000010100001" *)
(* LC_LOW_BIT_POS_PROBE_OUT162 = "16'b0000000010100010" *)
(* LC_LOW_BIT_POS_PROBE_OUT163 = "16'b0000000010100011" *)
(* LC_LOW_BIT_POS_PROBE_OUT164 = "16'b0000000010100100" *)
(* LC_LOW_BIT_POS_PROBE_OUT165 = "16'b0000000010100101" *)
(* LC_LOW_BIT_POS_PROBE_OUT166 = "16'b0000000010100110" *)
(* LC_LOW_BIT_POS_PROBE_OUT167 = "16'b0000000010100111" *)
(* LC_LOW_BIT_POS_PROBE_OUT168 = "16'b0000000010101000" *)
(* LC_LOW_BIT_POS_PROBE_OUT169 = "16'b0000000010101001" *)
(* LC_LOW_BIT_POS_PROBE_OUT17 = "16'b0000000000010001" *)
(* LC_LOW_BIT_POS_PROBE_OUT170 = "16'b0000000010101010" *)
(* LC_LOW_BIT_POS_PROBE_OUT171 = "16'b0000000010101011" *)
(* LC_LOW_BIT_POS_PROBE_OUT172 = "16'b0000000010101100" *)
(* LC_LOW_BIT_POS_PROBE_OUT173 = "16'b0000000010101101" *)
(* LC_LOW_BIT_POS_PROBE_OUT174 = "16'b0000000010101110" *)
(* LC_LOW_BIT_POS_PROBE_OUT175 = "16'b0000000010101111" *)
(* LC_LOW_BIT_POS_PROBE_OUT176 = "16'b0000000010110000" *)
(* LC_LOW_BIT_POS_PROBE_OUT177 = "16'b0000000010110001" *)
(* LC_LOW_BIT_POS_PROBE_OUT178 = "16'b0000000010110010" *)
(* LC_LOW_BIT_POS_PROBE_OUT179 = "16'b0000000010110011" *)
(* LC_LOW_BIT_POS_PROBE_OUT18 = "16'b0000000000010010" *)
(* LC_LOW_BIT_POS_PROBE_OUT180 = "16'b0000000010110100" *)
(* LC_LOW_BIT_POS_PROBE_OUT181 = "16'b0000000010110101" *)
(* LC_LOW_BIT_POS_PROBE_OUT182 = "16'b0000000010110110" *)
(* LC_LOW_BIT_POS_PROBE_OUT183 = "16'b0000000010110111" *)
(* LC_LOW_BIT_POS_PROBE_OUT184 = "16'b0000000010111000" *)
(* LC_LOW_BIT_POS_PROBE_OUT185 = "16'b0000000010111001" *)
(* LC_LOW_BIT_POS_PROBE_OUT186 = "16'b0000000010111010" *)
(* LC_LOW_BIT_POS_PROBE_OUT187 = "16'b0000000010111011" *)
(* LC_LOW_BIT_POS_PROBE_OUT188 = "16'b0000000010111100" *)
(* LC_LOW_BIT_POS_PROBE_OUT189 = "16'b0000000010111101" *)
(* LC_LOW_BIT_POS_PROBE_OUT19 = "16'b0000000000010011" *)
(* LC_LOW_BIT_POS_PROBE_OUT190 = "16'b0000000010111110" *)
(* LC_LOW_BIT_POS_PROBE_OUT191 = "16'b0000000010111111" *)
(* LC_LOW_BIT_POS_PROBE_OUT192 = "16'b0000000011000000" *)
(* LC_LOW_BIT_POS_PROBE_OUT193 = "16'b0000000011000001" *)
(* LC_LOW_BIT_POS_PROBE_OUT194 = "16'b0000000011000010" *)
(* LC_LOW_BIT_POS_PROBE_OUT195 = "16'b0000000011000011" *)
(* LC_LOW_BIT_POS_PROBE_OUT196 = "16'b0000000011000100" *)
(* LC_LOW_BIT_POS_PROBE_OUT197 = "16'b0000000011000101" *)
(* LC_LOW_BIT_POS_PROBE_OUT198 = "16'b0000000011000110" *)
(* LC_LOW_BIT_POS_PROBE_OUT199 = "16'b0000000011000111" *)
(* LC_LOW_BIT_POS_PROBE_OUT2 = "16'b0000000000000010" *)
(* LC_LOW_BIT_POS_PROBE_OUT20 = "16'b0000000000010100" *)
(* LC_LOW_BIT_POS_PROBE_OUT200 = "16'b0000000011001000" *)
(* LC_LOW_BIT_POS_PROBE_OUT201 = "16'b0000000011001001" *)
(* LC_LOW_BIT_POS_PROBE_OUT202 = "16'b0000000011001010" *)
(* LC_LOW_BIT_POS_PROBE_OUT203 = "16'b0000000011001011" *)
(* LC_LOW_BIT_POS_PROBE_OUT204 = "16'b0000000011001100" *)
(* LC_LOW_BIT_POS_PROBE_OUT205 = "16'b0000000011001101" *)
(* LC_LOW_BIT_POS_PROBE_OUT206 = "16'b0000000011001110" *)
(* LC_LOW_BIT_POS_PROBE_OUT207 = "16'b0000000011001111" *)
(* LC_LOW_BIT_POS_PROBE_OUT208 = "16'b0000000011010000" *)
(* LC_LOW_BIT_POS_PROBE_OUT209 = "16'b0000000011010001" *)
(* LC_LOW_BIT_POS_PROBE_OUT21 = "16'b0000000000010101" *)
(* LC_LOW_BIT_POS_PROBE_OUT210 = "16'b0000000011010010" *)
(* LC_LOW_BIT_POS_PROBE_OUT211 = "16'b0000000011010011" *)
(* LC_LOW_BIT_POS_PROBE_OUT212 = "16'b0000000011010100" *)
(* LC_LOW_BIT_POS_PROBE_OUT213 = "16'b0000000011010101" *)
(* LC_LOW_BIT_POS_PROBE_OUT214 = "16'b0000000011010110" *)
(* LC_LOW_BIT_POS_PROBE_OUT215 = "16'b0000000011010111" *)
(* LC_LOW_BIT_POS_PROBE_OUT216 = "16'b0000000011011000" *)
(* LC_LOW_BIT_POS_PROBE_OUT217 = "16'b0000000011011001" *)
(* LC_LOW_BIT_POS_PROBE_OUT218 = "16'b0000000011011010" *)
(* LC_LOW_BIT_POS_PROBE_OUT219 = "16'b0000000011011011" *)
(* LC_LOW_BIT_POS_PROBE_OUT22 = "16'b0000000000010110" *)
(* LC_LOW_BIT_POS_PROBE_OUT220 = "16'b0000000011011100" *)
(* LC_LOW_BIT_POS_PROBE_OUT221 = "16'b0000000011011101" *)
(* LC_LOW_BIT_POS_PROBE_OUT222 = "16'b0000000011011110" *)
(* LC_LOW_BIT_POS_PROBE_OUT223 = "16'b0000000011011111" *)
(* LC_LOW_BIT_POS_PROBE_OUT224 = "16'b0000000011100000" *)
(* LC_LOW_BIT_POS_PROBE_OUT225 = "16'b0000000011100001" *)
(* LC_LOW_BIT_POS_PROBE_OUT226 = "16'b0000000011100010" *)
(* LC_LOW_BIT_POS_PROBE_OUT227 = "16'b0000000011100011" *)
(* LC_LOW_BIT_POS_PROBE_OUT228 = "16'b0000000011100100" *)
(* LC_LOW_BIT_POS_PROBE_OUT229 = "16'b0000000011100101" *)
(* LC_LOW_BIT_POS_PROBE_OUT23 = "16'b0000000000010111" *)
(* LC_LOW_BIT_POS_PROBE_OUT230 = "16'b0000000011100110" *)
(* LC_LOW_BIT_POS_PROBE_OUT231 = "16'b0000000011100111" *)
(* LC_LOW_BIT_POS_PROBE_OUT232 = "16'b0000000011101000" *)
(* LC_LOW_BIT_POS_PROBE_OUT233 = "16'b0000000011101001" *)
(* LC_LOW_BIT_POS_PROBE_OUT234 = "16'b0000000011101010" *)
(* LC_LOW_BIT_POS_PROBE_OUT235 = "16'b0000000011101011" *)
(* LC_LOW_BIT_POS_PROBE_OUT236 = "16'b0000000011101100" *)
(* LC_LOW_BIT_POS_PROBE_OUT237 = "16'b0000000011101101" *)
(* LC_LOW_BIT_POS_PROBE_OUT238 = "16'b0000000011101110" *)
(* LC_LOW_BIT_POS_PROBE_OUT239 = "16'b0000000011101111" *)
(* LC_LOW_BIT_POS_PROBE_OUT24 = "16'b0000000000011000" *)
(* LC_LOW_BIT_POS_PROBE_OUT240 = "16'b0000000011110000" *)
(* LC_LOW_BIT_POS_PROBE_OUT241 = "16'b0000000011110001" *)
(* LC_LOW_BIT_POS_PROBE_OUT242 = "16'b0000000011110010" *)
(* LC_LOW_BIT_POS_PROBE_OUT243 = "16'b0000000011110011" *)
(* LC_LOW_BIT_POS_PROBE_OUT244 = "16'b0000000011110100" *)
(* LC_LOW_BIT_POS_PROBE_OUT245 = "16'b0000000011110101" *)
(* LC_LOW_BIT_POS_PROBE_OUT246 = "16'b0000000011110110" *)
(* LC_LOW_BIT_POS_PROBE_OUT247 = "16'b0000000011110111" *)
(* LC_LOW_BIT_POS_PROBE_OUT248 = "16'b0000000011111000" *)
(* LC_LOW_BIT_POS_PROBE_OUT249 = "16'b0000000011111001" *)
(* LC_LOW_BIT_POS_PROBE_OUT25 = "16'b0000000000011001" *)
(* LC_LOW_BIT_POS_PROBE_OUT250 = "16'b0000000011111010" *)
(* LC_LOW_BIT_POS_PROBE_OUT251 = "16'b0000000011111011" *)
(* LC_LOW_BIT_POS_PROBE_OUT252 = "16'b0000000011111100" *)
(* LC_LOW_BIT_POS_PROBE_OUT253 = "16'b0000000011111101" *)
(* LC_LOW_BIT_POS_PROBE_OUT254 = "16'b0000000011111110" *)
(* LC_LOW_BIT_POS_PROBE_OUT255 = "16'b0000000011111111" *)
(* LC_LOW_BIT_POS_PROBE_OUT26 = "16'b0000000000011010" *)
(* LC_LOW_BIT_POS_PROBE_OUT27 = "16'b0000000000011011" *)
(* LC_LOW_BIT_POS_PROBE_OUT28 = "16'b0000000000011100" *)
(* LC_LOW_BIT_POS_PROBE_OUT29 = "16'b0000000000011101" *)
(* LC_LOW_BIT_POS_PROBE_OUT3 = "16'b0000000000000011" *)
(* LC_LOW_BIT_POS_PROBE_OUT30 = "16'b0000000000011110" *)
(* LC_LOW_BIT_POS_PROBE_OUT31 = "16'b0000000000011111" *)
(* LC_LOW_BIT_POS_PROBE_OUT32 = "16'b0000000000100000" *)
(* LC_LOW_BIT_POS_PROBE_OUT33 = "16'b0000000000100001" *)
(* LC_LOW_BIT_POS_PROBE_OUT34 = "16'b0000000000100010" *)
(* LC_LOW_BIT_POS_PROBE_OUT35 = "16'b0000000000100011" *)
(* LC_LOW_BIT_POS_PROBE_OUT36 = "16'b0000000000100100" *)
(* LC_LOW_BIT_POS_PROBE_OUT37 = "16'b0000000000100101" *)
(* LC_LOW_BIT_POS_PROBE_OUT38 = "16'b0000000000100110" *)
(* LC_LOW_BIT_POS_PROBE_OUT39 = "16'b0000000000100111" *)
(* LC_LOW_BIT_POS_PROBE_OUT4 = "16'b0000000000000100" *)
(* LC_LOW_BIT_POS_PROBE_OUT40 = "16'b0000000000101000" *)
(* LC_LOW_BIT_POS_PROBE_OUT41 = "16'b0000000000101001" *)
(* LC_LOW_BIT_POS_PROBE_OUT42 = "16'b0000000000101010" *)
(* LC_LOW_BIT_POS_PROBE_OUT43 = "16'b0000000000101011" *)
(* LC_LOW_BIT_POS_PROBE_OUT44 = "16'b0000000000101100" *)
(* LC_LOW_BIT_POS_PROBE_OUT45 = "16'b0000000000101101" *)
(* LC_LOW_BIT_POS_PROBE_OUT46 = "16'b0000000000101110" *)
(* LC_LOW_BIT_POS_PROBE_OUT47 = "16'b0000000000101111" *)
(* LC_LOW_BIT_POS_PROBE_OUT48 = "16'b0000000000110000" *)
(* LC_LOW_BIT_POS_PROBE_OUT49 = "16'b0000000000110001" *)
(* LC_LOW_BIT_POS_PROBE_OUT5 = "16'b0000000000000101" *)
(* LC_LOW_BIT_POS_PROBE_OUT50 = "16'b0000000000110010" *)
(* LC_LOW_BIT_POS_PROBE_OUT51 = "16'b0000000000110011" *)
(* LC_LOW_BIT_POS_PROBE_OUT52 = "16'b0000000000110100" *)
(* LC_LOW_BIT_POS_PROBE_OUT53 = "16'b0000000000110101" *)
(* LC_LOW_BIT_POS_PROBE_OUT54 = "16'b0000000000110110" *)
(* LC_LOW_BIT_POS_PROBE_OUT55 = "16'b0000000000110111" *)
(* LC_LOW_BIT_POS_PROBE_OUT56 = "16'b0000000000111000" *)
(* LC_LOW_BIT_POS_PROBE_OUT57 = "16'b0000000000111001" *)
(* LC_LOW_BIT_POS_PROBE_OUT58 = "16'b0000000000111010" *)
(* LC_LOW_BIT_POS_PROBE_OUT59 = "16'b0000000000111011" *)
(* LC_LOW_BIT_POS_PROBE_OUT6 = "16'b0000000000000110" *)
(* LC_LOW_BIT_POS_PROBE_OUT60 = "16'b0000000000111100" *)
(* LC_LOW_BIT_POS_PROBE_OUT61 = "16'b0000000000111101" *)
(* LC_LOW_BIT_POS_PROBE_OUT62 = "16'b0000000000111110" *)
(* LC_LOW_BIT_POS_PROBE_OUT63 = "16'b0000000000111111" *)
(* LC_LOW_BIT_POS_PROBE_OUT64 = "16'b0000000001000000" *)
(* LC_LOW_BIT_POS_PROBE_OUT65 = "16'b0000000001000001" *)
(* LC_LOW_BIT_POS_PROBE_OUT66 = "16'b0000000001000010" *)
(* LC_LOW_BIT_POS_PROBE_OUT67 = "16'b0000000001000011" *)
(* LC_LOW_BIT_POS_PROBE_OUT68 = "16'b0000000001000100" *)
(* LC_LOW_BIT_POS_PROBE_OUT69 = "16'b0000000001000101" *)
(* LC_LOW_BIT_POS_PROBE_OUT7 = "16'b0000000000000111" *)
(* LC_LOW_BIT_POS_PROBE_OUT70 = "16'b0000000001000110" *)
(* LC_LOW_BIT_POS_PROBE_OUT71 = "16'b0000000001000111" *)
(* LC_LOW_BIT_POS_PROBE_OUT72 = "16'b0000000001001000" *)
(* LC_LOW_BIT_POS_PROBE_OUT73 = "16'b0000000001001001" *)
(* LC_LOW_BIT_POS_PROBE_OUT74 = "16'b0000000001001010" *)
(* LC_LOW_BIT_POS_PROBE_OUT75 = "16'b0000000001001011" *)
(* LC_LOW_BIT_POS_PROBE_OUT76 = "16'b0000000001001100" *)
(* LC_LOW_BIT_POS_PROBE_OUT77 = "16'b0000000001001101" *)
(* LC_LOW_BIT_POS_PROBE_OUT78 = "16'b0000000001001110" *)
(* LC_LOW_BIT_POS_PROBE_OUT79 = "16'b0000000001001111" *)
(* LC_LOW_BIT_POS_PROBE_OUT8 = "16'b0000000000001000" *)
(* LC_LOW_BIT_POS_PROBE_OUT80 = "16'b0000000001010000" *)
(* LC_LOW_BIT_POS_PROBE_OUT81 = "16'b0000000001010001" *)
(* LC_LOW_BIT_POS_PROBE_OUT82 = "16'b0000000001010010" *)
(* LC_LOW_BIT_POS_PROBE_OUT83 = "16'b0000000001010011" *)
(* LC_LOW_BIT_POS_PROBE_OUT84 = "16'b0000000001010100" *)
(* LC_LOW_BIT_POS_PROBE_OUT85 = "16'b0000000001010101" *)
(* LC_LOW_BIT_POS_PROBE_OUT86 = "16'b0000000001010110" *)
(* LC_LOW_BIT_POS_PROBE_OUT87 = "16'b0000000001010111" *)
(* LC_LOW_BIT_POS_PROBE_OUT88 = "16'b0000000001011000" *)
(* LC_LOW_BIT_POS_PROBE_OUT89 = "16'b0000000001011001" *)
(* LC_LOW_BIT_POS_PROBE_OUT9 = "16'b0000000000001001" *)
(* LC_LOW_BIT_POS_PROBE_OUT90 = "16'b0000000001011010" *)
(* LC_LOW_BIT_POS_PROBE_OUT91 = "16'b0000000001011011" *)
(* LC_LOW_BIT_POS_PROBE_OUT92 = "16'b0000000001011100" *)
(* LC_LOW_BIT_POS_PROBE_OUT93 = "16'b0000000001011101" *)
(* LC_LOW_BIT_POS_PROBE_OUT94 = "16'b0000000001011110" *)
(* LC_LOW_BIT_POS_PROBE_OUT95 = "16'b0000000001011111" *)
(* LC_LOW_BIT_POS_PROBE_OUT96 = "16'b0000000001100000" *)
(* LC_LOW_BIT_POS_PROBE_OUT97 = "16'b0000000001100001" *)
(* LC_LOW_BIT_POS_PROBE_OUT98 = "16'b0000000001100010" *)
(* LC_LOW_BIT_POS_PROBE_OUT99 = "16'b0000000001100011" *)
(* LC_PROBE_IN_WIDTH_STRING = "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
(* LC_PROBE_OUT_HIGH_BIT_POS_STRING = "4096'b0000000011111111000000001111111000000000111111010000000011111100000000001111101100000000111110100000000011111001000000001111100000000000111101110000000011110110000000001111010100000000111101000000000011110011000000001111001000000000111100010000000011110000000000001110111100000000111011100000000011101101000000001110110000000000111010110000000011101010000000001110100100000000111010000000000011100111000000001110011000000000111001010000000011100100000000001110001100000000111000100000000011100001000000001110000000000000110111110000000011011110000000001101110100000000110111000000000011011011000000001101101000000000110110010000000011011000000000001101011100000000110101100000000011010101000000001101010000000000110100110000000011010010000000001101000100000000110100000000000011001111000000001100111000000000110011010000000011001100000000001100101100000000110010100000000011001001000000001100100000000000110001110000000011000110000000001100010100000000110001000000000011000011000000001100001000000000110000010000000011000000000000001011111100000000101111100000000010111101000000001011110000000000101110110000000010111010000000001011100100000000101110000000000010110111000000001011011000000000101101010000000010110100000000001011001100000000101100100000000010110001000000001011000000000000101011110000000010101110000000001010110100000000101011000000000010101011000000001010101000000000101010010000000010101000000000001010011100000000101001100000000010100101000000001010010000000000101000110000000010100010000000001010000100000000101000000000000010011111000000001001111000000000100111010000000010011100000000001001101100000000100110100000000010011001000000001001100000000000100101110000000010010110000000001001010100000000100101000000000010010011000000001001001000000000100100010000000010010000000000001000111100000000100011100000000010001101000000001000110000000000100010110000000010001010000000001000100100000000100010000000000010000111000000001000011000000000100001010000000010000100000000001000001100000000100000100000000010000001000000001000000000000000011111110000000001111110000000000111110100000000011111000000000001111011000000000111101000000000011110010000000001111000000000000111011100000000011101100000000001110101000000000111010000000000011100110000000001110010000000000111000100000000011100000000000001101111000000000110111000000000011011010000000001101100000000000110101100000000011010100000000001101001000000000110100000000000011001110000000001100110000000000110010100000000011001000000000001100011000000000110001000000000011000010000000001100000000000000101111100000000010111100000000001011101000000000101110000000000010110110000000001011010000000000101100100000000010110000000000001010111000000000101011000000000010101010000000001010100000000000101001100000000010100100000000001010001000000000101000000000000010011110000000001001110000000000100110100000000010011000000000001001011000000000100101000000000010010010000000001001000000000000100011100000000010001100000000001000101000000000100010000000000010000110000000001000010000000000100000100000000010000000000000000111111000000000011111000000000001111010000000000111100000000000011101100000000001110100000000000111001000000000011100000000000001101110000000000110110000000000011010100000000001101000000000000110011000000000011001000000000001100010000000000110000000000000010111100000000001011100000000000101101000000000010110000000000001010110000000000101010000000000010100100000000001010000000000000100111000000000010011000000000001001010000000000100100000000000010001100000000001000100000000000100001000000000010000000000000000111110000000000011110000000000001110100000000000111000000000000011011000000000001101000000000000110010000000000011000000000000001011100000000000101100000000000010101000000000001010000000000000100110000000000010010000000000001000100000000000100000000000000001111000000000000111000000000000011010000000000001100000000000000101100000000000010100000000000001001000000000000100000000000000001110000000000000110000000000000010100000000000001000000000000000011000000000000001000000000000000010000000000000000" *)
(* LC_PROBE_OUT_INIT_VAL_STRING = "256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
(* LC_PROBE_OUT_LOW_BIT_POS_STRING = "4096'b0000000011111111000000001111111000000000111111010000000011111100000000001111101100000000111110100000000011111001000000001111100000000000111101110000000011110110000000001111010100000000111101000000000011110011000000001111001000000000111100010000000011110000000000001110111100000000111011100000000011101101000000001110110000000000111010110000000011101010000000001110100100000000111010000000000011100111000000001110011000000000111001010000000011100100000000001110001100000000111000100000000011100001000000001110000000000000110111110000000011011110000000001101110100000000110111000000000011011011000000001101101000000000110110010000000011011000000000001101011100000000110101100000000011010101000000001101010000000000110100110000000011010010000000001101000100000000110100000000000011001111000000001100111000000000110011010000000011001100000000001100101100000000110010100000000011001001000000001100100000000000110001110000000011000110000000001100010100000000110001000000000011000011000000001100001000000000110000010000000011000000000000001011111100000000101111100000000010111101000000001011110000000000101110110000000010111010000000001011100100000000101110000000000010110111000000001011011000000000101101010000000010110100000000001011001100000000101100100000000010110001000000001011000000000000101011110000000010101110000000001010110100000000101011000000000010101011000000001010101000000000101010010000000010101000000000001010011100000000101001100000000010100101000000001010010000000000101000110000000010100010000000001010000100000000101000000000000010011111000000001001111000000000100111010000000010011100000000001001101100000000100110100000000010011001000000001001100000000000100101110000000010010110000000001001010100000000100101000000000010010011000000001001001000000000100100010000000010010000000000001000111100000000100011100000000010001101000000001000110000000000100010110000000010001010000000001000100100000000100010000000000010000111000000001000011000000000100001010000000010000100000000001000001100000000100000100000000010000001000000001000000000000000011111110000000001111110000000000111110100000000011111000000000001111011000000000111101000000000011110010000000001111000000000000111011100000000011101100000000001110101000000000111010000000000011100110000000001110010000000000111000100000000011100000000000001101111000000000110111000000000011011010000000001101100000000000110101100000000011010100000000001101001000000000110100000000000011001110000000001100110000000000110010100000000011001000000000001100011000000000110001000000000011000010000000001100000000000000101111100000000010111100000000001011101000000000101110000000000010110110000000001011010000000000101100100000000010110000000000001010111000000000101011000000000010101010000000001010100000000000101001100000000010100100000000001010001000000000101000000000000010011110000000001001110000000000100110100000000010011000000000001001011000000000100101000000000010010010000000001001000000000000100011100000000010001100000000001000101000000000100010000000000010000110000000001000010000000000100000100000000010000000000000000111111000000000011111000000000001111010000000000111100000000000011101100000000001110100000000000111001000000000011100000000000001101110000000000110110000000000011010100000000001101000000000000110011000000000011001000000000001100010000000000110000000000000010111100000000001011100000000000101101000000000010110000000000001010110000000000101010000000000010100100000000001010000000000000100111000000000010011000000000001001010000000000100100000000000010001100000000001000100000000000100001000000000010000000000000000111110000000000011110000000000001110100000000000111000000000000011011000000000001101000000000000110010000000000011000000000000001011100000000000101100000000000010101000000000001010000000000000100110000000000010010000000000001000100000000000100000000000000001111000000000000111000000000000011010000000000001100000000000000101100000000000010100000000000001001000000000000100000000000000001110000000000000110000000000000010100000000000001000000000000000011000000000000001000000000000000010000000000000000" *)
(* LC_PROBE_OUT_WIDTH_STRING = "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
(* LC_TOTAL_PROBE_IN_WIDTH = "4" *)
(* LC_TOTAL_PROBE_OUT_WIDTH = "0" *)
(* syn_noprune = "1" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio inst
(.clk(clk),
.probe_in0(probe_in0),
.probe_in1(probe_in1),
.probe_in10(1'b0),
.probe_in100(1'b0),
.probe_in101(1'b0),
.probe_in102(1'b0),
.probe_in103(1'b0),
.probe_in104(1'b0),
.probe_in105(1'b0),
.probe_in106(1'b0),
.probe_in107(1'b0),
.probe_in108(1'b0),
.probe_in109(1'b0),
.probe_in11(1'b0),
.probe_in110(1'b0),
.probe_in111(1'b0),
.probe_in112(1'b0),
.probe_in113(1'b0),
.probe_in114(1'b0),
.probe_in115(1'b0),
.probe_in116(1'b0),
.probe_in117(1'b0),
.probe_in118(1'b0),
.probe_in119(1'b0),
.probe_in12(1'b0),
.probe_in120(1'b0),
.probe_in121(1'b0),
.probe_in122(1'b0),
.probe_in123(1'b0),
.probe_in124(1'b0),
.probe_in125(1'b0),
.probe_in126(1'b0),
.probe_in127(1'b0),
.probe_in128(1'b0),
.probe_in129(1'b0),
.probe_in13(1'b0),
.probe_in130(1'b0),
.probe_in131(1'b0),
.probe_in132(1'b0),
.probe_in133(1'b0),
.probe_in134(1'b0),
.probe_in135(1'b0),
.probe_in136(1'b0),
.probe_in137(1'b0),
.probe_in138(1'b0),
.probe_in139(1'b0),
.probe_in14(1'b0),
.probe_in140(1'b0),
.probe_in141(1'b0),
.probe_in142(1'b0),
.probe_in143(1'b0),
.probe_in144(1'b0),
.probe_in145(1'b0),
.probe_in146(1'b0),
.probe_in147(1'b0),
.probe_in148(1'b0),
.probe_in149(1'b0),
.probe_in15(1'b0),
.probe_in150(1'b0),
.probe_in151(1'b0),
.probe_in152(1'b0),
.probe_in153(1'b0),
.probe_in154(1'b0),
.probe_in155(1'b0),
.probe_in156(1'b0),
.probe_in157(1'b0),
.probe_in158(1'b0),
.probe_in159(1'b0),
.probe_in16(1'b0),
.probe_in160(1'b0),
.probe_in161(1'b0),
.probe_in162(1'b0),
.probe_in163(1'b0),
.probe_in164(1'b0),
.probe_in165(1'b0),
.probe_in166(1'b0),
.probe_in167(1'b0),
.probe_in168(1'b0),
.probe_in169(1'b0),
.probe_in17(1'b0),
.probe_in170(1'b0),
.probe_in171(1'b0),
.probe_in172(1'b0),
.probe_in173(1'b0),
.probe_in174(1'b0),
.probe_in175(1'b0),
.probe_in176(1'b0),
.probe_in177(1'b0),
.probe_in178(1'b0),
.probe_in179(1'b0),
.probe_in18(1'b0),
.probe_in180(1'b0),
.probe_in181(1'b0),
.probe_in182(1'b0),
.probe_in183(1'b0),
.probe_in184(1'b0),
.probe_in185(1'b0),
.probe_in186(1'b0),
.probe_in187(1'b0),
.probe_in188(1'b0),
.probe_in189(1'b0),
.probe_in19(1'b0),
.probe_in190(1'b0),
.probe_in191(1'b0),
.probe_in192(1'b0),
.probe_in193(1'b0),
.probe_in194(1'b0),
.probe_in195(1'b0),
.probe_in196(1'b0),
.probe_in197(1'b0),
.probe_in198(1'b0),
.probe_in199(1'b0),
.probe_in2(probe_in2),
.probe_in20(1'b0),
.probe_in200(1'b0),
.probe_in201(1'b0),
.probe_in202(1'b0),
.probe_in203(1'b0),
.probe_in204(1'b0),
.probe_in205(1'b0),
.probe_in206(1'b0),
.probe_in207(1'b0),
.probe_in208(1'b0),
.probe_in209(1'b0),
.probe_in21(1'b0),
.probe_in210(1'b0),
.probe_in211(1'b0),
.probe_in212(1'b0),
.probe_in213(1'b0),
.probe_in214(1'b0),
.probe_in215(1'b0),
.probe_in216(1'b0),
.probe_in217(1'b0),
.probe_in218(1'b0),
.probe_in219(1'b0),
.probe_in22(1'b0),
.probe_in220(1'b0),
.probe_in221(1'b0),
.probe_in222(1'b0),
.probe_in223(1'b0),
.probe_in224(1'b0),
.probe_in225(1'b0),
.probe_in226(1'b0),
.probe_in227(1'b0),
.probe_in228(1'b0),
.probe_in229(1'b0),
.probe_in23(1'b0),
.probe_in230(1'b0),
.probe_in231(1'b0),
.probe_in232(1'b0),
.probe_in233(1'b0),
.probe_in234(1'b0),
.probe_in235(1'b0),
.probe_in236(1'b0),
.probe_in237(1'b0),
.probe_in238(1'b0),
.probe_in239(1'b0),
.probe_in24(1'b0),
.probe_in240(1'b0),
.probe_in241(1'b0),
.probe_in242(1'b0),
.probe_in243(1'b0),
.probe_in244(1'b0),
.probe_in245(1'b0),
.probe_in246(1'b0),
.probe_in247(1'b0),
.probe_in248(1'b0),
.probe_in249(1'b0),
.probe_in25(1'b0),
.probe_in250(1'b0),
.probe_in251(1'b0),
.probe_in252(1'b0),
.probe_in253(1'b0),
.probe_in254(1'b0),
.probe_in255(1'b0),
.probe_in26(1'b0),
.probe_in27(1'b0),
.probe_in28(1'b0),
.probe_in29(1'b0),
.probe_in3(probe_in3),
.probe_in30(1'b0),
.probe_in31(1'b0),
.probe_in32(1'b0),
.probe_in33(1'b0),
.probe_in34(1'b0),
.probe_in35(1'b0),
.probe_in36(1'b0),
.probe_in37(1'b0),
.probe_in38(1'b0),
.probe_in39(1'b0),
.probe_in4(1'b0),
.probe_in40(1'b0),
.probe_in41(1'b0),
.probe_in42(1'b0),
.probe_in43(1'b0),
.probe_in44(1'b0),
.probe_in45(1'b0),
.probe_in46(1'b0),
.probe_in47(1'b0),
.probe_in48(1'b0),
.probe_in49(1'b0),
.probe_in5(1'b0),
.probe_in50(1'b0),
.probe_in51(1'b0),
.probe_in52(1'b0),
.probe_in53(1'b0),
.probe_in54(1'b0),
.probe_in55(1'b0),
.probe_in56(1'b0),
.probe_in57(1'b0),
.probe_in58(1'b0),
.probe_in59(1'b0),
.probe_in6(1'b0),
.probe_in60(1'b0),
.probe_in61(1'b0),
.probe_in62(1'b0),
.probe_in63(1'b0),
.probe_in64(1'b0),
.probe_in65(1'b0),
.probe_in66(1'b0),
.probe_in67(1'b0),
.probe_in68(1'b0),
.probe_in69(1'b0),
.probe_in7(1'b0),
.probe_in70(1'b0),
.probe_in71(1'b0),
.probe_in72(1'b0),
.probe_in73(1'b0),
.probe_in74(1'b0),
.probe_in75(1'b0),
.probe_in76(1'b0),
.probe_in77(1'b0),
.probe_in78(1'b0),
.probe_in79(1'b0),
.probe_in8(1'b0),
.probe_in80(1'b0),
.probe_in81(1'b0),
.probe_in82(1'b0),
.probe_in83(1'b0),
.probe_in84(1'b0),
.probe_in85(1'b0),
.probe_in86(1'b0),
.probe_in87(1'b0),
.probe_in88(1'b0),
.probe_in89(1'b0),
.probe_in9(1'b0),
.probe_in90(1'b0),
.probe_in91(1'b0),
.probe_in92(1'b0),
.probe_in93(1'b0),
.probe_in94(1'b0),
.probe_in95(1'b0),
.probe_in96(1'b0),
.probe_in97(1'b0),
.probe_in98(1'b0),
.probe_in99(1'b0),
.probe_out0(NLW_inst_probe_out0_UNCONNECTED[0]),
.probe_out1(NLW_inst_probe_out1_UNCONNECTED[0]),
.probe_out10(NLW_inst_probe_out10_UNCONNECTED[0]),
.probe_out100(NLW_inst_probe_out100_UNCONNECTED[0]),
.probe_out101(NLW_inst_probe_out101_UNCONNECTED[0]),
.probe_out102(NLW_inst_probe_out102_UNCONNECTED[0]),
.probe_out103(NLW_inst_probe_out103_UNCONNECTED[0]),
.probe_out104(NLW_inst_probe_out104_UNCONNECTED[0]),
.probe_out105(NLW_inst_probe_out105_UNCONNECTED[0]),
.probe_out106(NLW_inst_probe_out106_UNCONNECTED[0]),
.probe_out107(NLW_inst_probe_out107_UNCONNECTED[0]),
.probe_out108(NLW_inst_probe_out108_UNCONNECTED[0]),
.probe_out109(NLW_inst_probe_out109_UNCONNECTED[0]),
.probe_out11(NLW_inst_probe_out11_UNCONNECTED[0]),
.probe_out110(NLW_inst_probe_out110_UNCONNECTED[0]),
.probe_out111(NLW_inst_probe_out111_UNCONNECTED[0]),
.probe_out112(NLW_inst_probe_out112_UNCONNECTED[0]),
.probe_out113(NLW_inst_probe_out113_UNCONNECTED[0]),
.probe_out114(NLW_inst_probe_out114_UNCONNECTED[0]),
.probe_out115(NLW_inst_probe_out115_UNCONNECTED[0]),
.probe_out116(NLW_inst_probe_out116_UNCONNECTED[0]),
.probe_out117(NLW_inst_probe_out117_UNCONNECTED[0]),
.probe_out118(NLW_inst_probe_out118_UNCONNECTED[0]),
.probe_out119(NLW_inst_probe_out119_UNCONNECTED[0]),
.probe_out12(NLW_inst_probe_out12_UNCONNECTED[0]),
.probe_out120(NLW_inst_probe_out120_UNCONNECTED[0]),
.probe_out121(NLW_inst_probe_out121_UNCONNECTED[0]),
.probe_out122(NLW_inst_probe_out122_UNCONNECTED[0]),
.probe_out123(NLW_inst_probe_out123_UNCONNECTED[0]),
.probe_out124(NLW_inst_probe_out124_UNCONNECTED[0]),
.probe_out125(NLW_inst_probe_out125_UNCONNECTED[0]),
.probe_out126(NLW_inst_probe_out126_UNCONNECTED[0]),
.probe_out127(NLW_inst_probe_out127_UNCONNECTED[0]),
.probe_out128(NLW_inst_probe_out128_UNCONNECTED[0]),
.probe_out129(NLW_inst_probe_out129_UNCONNECTED[0]),
.probe_out13(NLW_inst_probe_out13_UNCONNECTED[0]),
.probe_out130(NLW_inst_probe_out130_UNCONNECTED[0]),
.probe_out131(NLW_inst_probe_out131_UNCONNECTED[0]),
.probe_out132(NLW_inst_probe_out132_UNCONNECTED[0]),
.probe_out133(NLW_inst_probe_out133_UNCONNECTED[0]),
.probe_out134(NLW_inst_probe_out134_UNCONNECTED[0]),
.probe_out135(NLW_inst_probe_out135_UNCONNECTED[0]),
.probe_out136(NLW_inst_probe_out136_UNCONNECTED[0]),
.probe_out137(NLW_inst_probe_out137_UNCONNECTED[0]),
.probe_out138(NLW_inst_probe_out138_UNCONNECTED[0]),
.probe_out139(NLW_inst_probe_out139_UNCONNECTED[0]),
.probe_out14(NLW_inst_probe_out14_UNCONNECTED[0]),
.probe_out140(NLW_inst_probe_out140_UNCONNECTED[0]),
.probe_out141(NLW_inst_probe_out141_UNCONNECTED[0]),
.probe_out142(NLW_inst_probe_out142_UNCONNECTED[0]),
.probe_out143(NLW_inst_probe_out143_UNCONNECTED[0]),
.probe_out144(NLW_inst_probe_out144_UNCONNECTED[0]),
.probe_out145(NLW_inst_probe_out145_UNCONNECTED[0]),
.probe_out146(NLW_inst_probe_out146_UNCONNECTED[0]),
.probe_out147(NLW_inst_probe_out147_UNCONNECTED[0]),
.probe_out148(NLW_inst_probe_out148_UNCONNECTED[0]),
.probe_out149(NLW_inst_probe_out149_UNCONNECTED[0]),
.probe_out15(NLW_inst_probe_out15_UNCONNECTED[0]),
.probe_out150(NLW_inst_probe_out150_UNCONNECTED[0]),
.probe_out151(NLW_inst_probe_out151_UNCONNECTED[0]),
.probe_out152(NLW_inst_probe_out152_UNCONNECTED[0]),
.probe_out153(NLW_inst_probe_out153_UNCONNECTED[0]),
.probe_out154(NLW_inst_probe_out154_UNCONNECTED[0]),
.probe_out155(NLW_inst_probe_out155_UNCONNECTED[0]),
.probe_out156(NLW_inst_probe_out156_UNCONNECTED[0]),
.probe_out157(NLW_inst_probe_out157_UNCONNECTED[0]),
.probe_out158(NLW_inst_probe_out158_UNCONNECTED[0]),
.probe_out159(NLW_inst_probe_out159_UNCONNECTED[0]),
.probe_out16(NLW_inst_probe_out16_UNCONNECTED[0]),
.probe_out160(NLW_inst_probe_out160_UNCONNECTED[0]),
.probe_out161(NLW_inst_probe_out161_UNCONNECTED[0]),
.probe_out162(NLW_inst_probe_out162_UNCONNECTED[0]),
.probe_out163(NLW_inst_probe_out163_UNCONNECTED[0]),
.probe_out164(NLW_inst_probe_out164_UNCONNECTED[0]),
.probe_out165(NLW_inst_probe_out165_UNCONNECTED[0]),
.probe_out166(NLW_inst_probe_out166_UNCONNECTED[0]),
.probe_out167(NLW_inst_probe_out167_UNCONNECTED[0]),
.probe_out168(NLW_inst_probe_out168_UNCONNECTED[0]),
.probe_out169(NLW_inst_probe_out169_UNCONNECTED[0]),
.probe_out17(NLW_inst_probe_out17_UNCONNECTED[0]),
.probe_out170(NLW_inst_probe_out170_UNCONNECTED[0]),
.probe_out171(NLW_inst_probe_out171_UNCONNECTED[0]),
.probe_out172(NLW_inst_probe_out172_UNCONNECTED[0]),
.probe_out173(NLW_inst_probe_out173_UNCONNECTED[0]),
.probe_out174(NLW_inst_probe_out174_UNCONNECTED[0]),
.probe_out175(NLW_inst_probe_out175_UNCONNECTED[0]),
.probe_out176(NLW_inst_probe_out176_UNCONNECTED[0]),
.probe_out177(NLW_inst_probe_out177_UNCONNECTED[0]),
.probe_out178(NLW_inst_probe_out178_UNCONNECTED[0]),
.probe_out179(NLW_inst_probe_out179_UNCONNECTED[0]),
.probe_out18(NLW_inst_probe_out18_UNCONNECTED[0]),
.probe_out180(NLW_inst_probe_out180_UNCONNECTED[0]),
.probe_out181(NLW_inst_probe_out181_UNCONNECTED[0]),
.probe_out182(NLW_inst_probe_out182_UNCONNECTED[0]),
.probe_out183(NLW_inst_probe_out183_UNCONNECTED[0]),
.probe_out184(NLW_inst_probe_out184_UNCONNECTED[0]),
.probe_out185(NLW_inst_probe_out185_UNCONNECTED[0]),
.probe_out186(NLW_inst_probe_out186_UNCONNECTED[0]),
.probe_out187(NLW_inst_probe_out187_UNCONNECTED[0]),
.probe_out188(NLW_inst_probe_out188_UNCONNECTED[0]),
.probe_out189(NLW_inst_probe_out189_UNCONNECTED[0]),
.probe_out19(NLW_inst_probe_out19_UNCONNECTED[0]),
.probe_out190(NLW_inst_probe_out190_UNCONNECTED[0]),
.probe_out191(NLW_inst_probe_out191_UNCONNECTED[0]),
.probe_out192(NLW_inst_probe_out192_UNCONNECTED[0]),
.probe_out193(NLW_inst_probe_out193_UNCONNECTED[0]),
.probe_out194(NLW_inst_probe_out194_UNCONNECTED[0]),
.probe_out195(NLW_inst_probe_out195_UNCONNECTED[0]),
.probe_out196(NLW_inst_probe_out196_UNCONNECTED[0]),
.probe_out197(NLW_inst_probe_out197_UNCONNECTED[0]),
.probe_out198(NLW_inst_probe_out198_UNCONNECTED[0]),
.probe_out199(NLW_inst_probe_out199_UNCONNECTED[0]),
.probe_out2(NLW_inst_probe_out2_UNCONNECTED[0]),
.probe_out20(NLW_inst_probe_out20_UNCONNECTED[0]),
.probe_out200(NLW_inst_probe_out200_UNCONNECTED[0]),
.probe_out201(NLW_inst_probe_out201_UNCONNECTED[0]),
.probe_out202(NLW_inst_probe_out202_UNCONNECTED[0]),
.probe_out203(NLW_inst_probe_out203_UNCONNECTED[0]),
.probe_out204(NLW_inst_probe_out204_UNCONNECTED[0]),
.probe_out205(NLW_inst_probe_out205_UNCONNECTED[0]),
.probe_out206(NLW_inst_probe_out206_UNCONNECTED[0]),
.probe_out207(NLW_inst_probe_out207_UNCONNECTED[0]),
.probe_out208(NLW_inst_probe_out208_UNCONNECTED[0]),
.probe_out209(NLW_inst_probe_out209_UNCONNECTED[0]),
.probe_out21(NLW_inst_probe_out21_UNCONNECTED[0]),
.probe_out210(NLW_inst_probe_out210_UNCONNECTED[0]),
.probe_out211(NLW_inst_probe_out211_UNCONNECTED[0]),
.probe_out212(NLW_inst_probe_out212_UNCONNECTED[0]),
.probe_out213(NLW_inst_probe_out213_UNCONNECTED[0]),
.probe_out214(NLW_inst_probe_out214_UNCONNECTED[0]),
.probe_out215(NLW_inst_probe_out215_UNCONNECTED[0]),
.probe_out216(NLW_inst_probe_out216_UNCONNECTED[0]),
.probe_out217(NLW_inst_probe_out217_UNCONNECTED[0]),
.probe_out218(NLW_inst_probe_out218_UNCONNECTED[0]),
.probe_out219(NLW_inst_probe_out219_UNCONNECTED[0]),
.probe_out22(NLW_inst_probe_out22_UNCONNECTED[0]),
.probe_out220(NLW_inst_probe_out220_UNCONNECTED[0]),
.probe_out221(NLW_inst_probe_out221_UNCONNECTED[0]),
.probe_out222(NLW_inst_probe_out222_UNCONNECTED[0]),
.probe_out223(NLW_inst_probe_out223_UNCONNECTED[0]),
.probe_out224(NLW_inst_probe_out224_UNCONNECTED[0]),
.probe_out225(NLW_inst_probe_out225_UNCONNECTED[0]),
.probe_out226(NLW_inst_probe_out226_UNCONNECTED[0]),
.probe_out227(NLW_inst_probe_out227_UNCONNECTED[0]),
.probe_out228(NLW_inst_probe_out228_UNCONNECTED[0]),
.probe_out229(NLW_inst_probe_out229_UNCONNECTED[0]),
.probe_out23(NLW_inst_probe_out23_UNCONNECTED[0]),
.probe_out230(NLW_inst_probe_out230_UNCONNECTED[0]),
.probe_out231(NLW_inst_probe_out231_UNCONNECTED[0]),
.probe_out232(NLW_inst_probe_out232_UNCONNECTED[0]),
.probe_out233(NLW_inst_probe_out233_UNCONNECTED[0]),
.probe_out234(NLW_inst_probe_out234_UNCONNECTED[0]),
.probe_out235(NLW_inst_probe_out235_UNCONNECTED[0]),
.probe_out236(NLW_inst_probe_out236_UNCONNECTED[0]),
.probe_out237(NLW_inst_probe_out237_UNCONNECTED[0]),
.probe_out238(NLW_inst_probe_out238_UNCONNECTED[0]),
.probe_out239(NLW_inst_probe_out239_UNCONNECTED[0]),
.probe_out24(NLW_inst_probe_out24_UNCONNECTED[0]),
.probe_out240(NLW_inst_probe_out240_UNCONNECTED[0]),
.probe_out241(NLW_inst_probe_out241_UNCONNECTED[0]),
.probe_out242(NLW_inst_probe_out242_UNCONNECTED[0]),
.probe_out243(NLW_inst_probe_out243_UNCONNECTED[0]),
.probe_out244(NLW_inst_probe_out244_UNCONNECTED[0]),
.probe_out245(NLW_inst_probe_out245_UNCONNECTED[0]),
.probe_out246(NLW_inst_probe_out246_UNCONNECTED[0]),
.probe_out247(NLW_inst_probe_out247_UNCONNECTED[0]),
.probe_out248(NLW_inst_probe_out248_UNCONNECTED[0]),
.probe_out249(NLW_inst_probe_out249_UNCONNECTED[0]),
.probe_out25(NLW_inst_probe_out25_UNCONNECTED[0]),
.probe_out250(NLW_inst_probe_out250_UNCONNECTED[0]),
.probe_out251(NLW_inst_probe_out251_UNCONNECTED[0]),
.probe_out252(NLW_inst_probe_out252_UNCONNECTED[0]),
.probe_out253(NLW_inst_probe_out253_UNCONNECTED[0]),
.probe_out254(NLW_inst_probe_out254_UNCONNECTED[0]),
.probe_out255(NLW_inst_probe_out255_UNCONNECTED[0]),
.probe_out26(NLW_inst_probe_out26_UNCONNECTED[0]),
.probe_out27(NLW_inst_probe_out27_UNCONNECTED[0]),
.probe_out28(NLW_inst_probe_out28_UNCONNECTED[0]),
.probe_out29(NLW_inst_probe_out29_UNCONNECTED[0]),
.probe_out3(NLW_inst_probe_out3_UNCONNECTED[0]),
.probe_out30(NLW_inst_probe_out30_UNCONNECTED[0]),
.probe_out31(NLW_inst_probe_out31_UNCONNECTED[0]),
.probe_out32(NLW_inst_probe_out32_UNCONNECTED[0]),
.probe_out33(NLW_inst_probe_out33_UNCONNECTED[0]),
.probe_out34(NLW_inst_probe_out34_UNCONNECTED[0]),
.probe_out35(NLW_inst_probe_out35_UNCONNECTED[0]),
.probe_out36(NLW_inst_probe_out36_UNCONNECTED[0]),
.probe_out37(NLW_inst_probe_out37_UNCONNECTED[0]),
.probe_out38(NLW_inst_probe_out38_UNCONNECTED[0]),
.probe_out39(NLW_inst_probe_out39_UNCONNECTED[0]),
.probe_out4(NLW_inst_probe_out4_UNCONNECTED[0]),
.probe_out40(NLW_inst_probe_out40_UNCONNECTED[0]),
.probe_out41(NLW_inst_probe_out41_UNCONNECTED[0]),
.probe_out42(NLW_inst_probe_out42_UNCONNECTED[0]),
.probe_out43(NLW_inst_probe_out43_UNCONNECTED[0]),
.probe_out44(NLW_inst_probe_out44_UNCONNECTED[0]),
.probe_out45(NLW_inst_probe_out45_UNCONNECTED[0]),
.probe_out46(NLW_inst_probe_out46_UNCONNECTED[0]),
.probe_out47(NLW_inst_probe_out47_UNCONNECTED[0]),
.probe_out48(NLW_inst_probe_out48_UNCONNECTED[0]),
.probe_out49(NLW_inst_probe_out49_UNCONNECTED[0]),
.probe_out5(NLW_inst_probe_out5_UNCONNECTED[0]),
.probe_out50(NLW_inst_probe_out50_UNCONNECTED[0]),
.probe_out51(NLW_inst_probe_out51_UNCONNECTED[0]),
.probe_out52(NLW_inst_probe_out52_UNCONNECTED[0]),
.probe_out53(NLW_inst_probe_out53_UNCONNECTED[0]),
.probe_out54(NLW_inst_probe_out54_UNCONNECTED[0]),
.probe_out55(NLW_inst_probe_out55_UNCONNECTED[0]),
.probe_out56(NLW_inst_probe_out56_UNCONNECTED[0]),
.probe_out57(NLW_inst_probe_out57_UNCONNECTED[0]),
.probe_out58(NLW_inst_probe_out58_UNCONNECTED[0]),
.probe_out59(NLW_inst_probe_out59_UNCONNECTED[0]),
.probe_out6(NLW_inst_probe_out6_UNCONNECTED[0]),
.probe_out60(NLW_inst_probe_out60_UNCONNECTED[0]),
.probe_out61(NLW_inst_probe_out61_UNCONNECTED[0]),
.probe_out62(NLW_inst_probe_out62_UNCONNECTED[0]),
.probe_out63(NLW_inst_probe_out63_UNCONNECTED[0]),
.probe_out64(NLW_inst_probe_out64_UNCONNECTED[0]),
.probe_out65(NLW_inst_probe_out65_UNCONNECTED[0]),
.probe_out66(NLW_inst_probe_out66_UNCONNECTED[0]),
.probe_out67(NLW_inst_probe_out67_UNCONNECTED[0]),
.probe_out68(NLW_inst_probe_out68_UNCONNECTED[0]),
.probe_out69(NLW_inst_probe_out69_UNCONNECTED[0]),
.probe_out7(NLW_inst_probe_out7_UNCONNECTED[0]),
.probe_out70(NLW_inst_probe_out70_UNCONNECTED[0]),
.probe_out71(NLW_inst_probe_out71_UNCONNECTED[0]),
.probe_out72(NLW_inst_probe_out72_UNCONNECTED[0]),
.probe_out73(NLW_inst_probe_out73_UNCONNECTED[0]),
.probe_out74(NLW_inst_probe_out74_UNCONNECTED[0]),
.probe_out75(NLW_inst_probe_out75_UNCONNECTED[0]),
.probe_out76(NLW_inst_probe_out76_UNCONNECTED[0]),
.probe_out77(NLW_inst_probe_out77_UNCONNECTED[0]),
.probe_out78(NLW_inst_probe_out78_UNCONNECTED[0]),
.probe_out79(NLW_inst_probe_out79_UNCONNECTED[0]),
.probe_out8(NLW_inst_probe_out8_UNCONNECTED[0]),
.probe_out80(NLW_inst_probe_out80_UNCONNECTED[0]),
.probe_out81(NLW_inst_probe_out81_UNCONNECTED[0]),
.probe_out82(NLW_inst_probe_out82_UNCONNECTED[0]),
.probe_out83(NLW_inst_probe_out83_UNCONNECTED[0]),
.probe_out84(NLW_inst_probe_out84_UNCONNECTED[0]),
.probe_out85(NLW_inst_probe_out85_UNCONNECTED[0]),
.probe_out86(NLW_inst_probe_out86_UNCONNECTED[0]),
.probe_out87(NLW_inst_probe_out87_UNCONNECTED[0]),
.probe_out88(NLW_inst_probe_out88_UNCONNECTED[0]),
.probe_out89(NLW_inst_probe_out89_UNCONNECTED[0]),
.probe_out9(NLW_inst_probe_out9_UNCONNECTED[0]),
.probe_out90(NLW_inst_probe_out90_UNCONNECTED[0]),
.probe_out91(NLW_inst_probe_out91_UNCONNECTED[0]),
.probe_out92(NLW_inst_probe_out92_UNCONNECTED[0]),
.probe_out93(NLW_inst_probe_out93_UNCONNECTED[0]),
.probe_out94(NLW_inst_probe_out94_UNCONNECTED[0]),
.probe_out95(NLW_inst_probe_out95_UNCONNECTED[0]),
.probe_out96(NLW_inst_probe_out96_UNCONNECTED[0]),
.probe_out97(NLW_inst_probe_out97_UNCONNECTED[0]),
.probe_out98(NLW_inst_probe_out98_UNCONNECTED[0]),
.probe_out99(NLW_inst_probe_out99_UNCONNECTED[0]),
.sl_iport0({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.sl_oport0(NLW_inst_sl_oport0_UNCONNECTED[16:0]));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_decoder
(s_drdy_i,
\wr_en_reg[4]_0 ,
\wr_en_reg[4]_1 ,
\wr_en_reg[4]_2 ,
E,
s_do_i,
s_rst_o,
Q,
out,
s_daddr_o,
s_dwe_o,
s_den_o,
\Bus_Data_out_reg[11] );
output s_drdy_i;
output \wr_en_reg[4]_0 ;
output \wr_en_reg[4]_1 ;
output \wr_en_reg[4]_2 ;
output [0:0]E;
output [15:0]s_do_i;
input s_rst_o;
input [15:0]Q;
input out;
input [16:0]s_daddr_o;
input s_dwe_o;
input s_den_o;
input [11:0]\Bus_Data_out_reg[11] ;
wire [11:0]\Bus_Data_out_reg[11] ;
wire [0:0]E;
wire Hold_probe_in;
wire [15:0]Q;
wire clear_int;
wire committ_int;
wire [15:0]data_info_probe_in__67;
wire int_cnt_rst;
wire out;
wire [15:0]probe_out_modified;
wire rd_en_p1;
wire rd_en_p2;
wire [16:0]s_daddr_o;
wire s_den_o;
wire [15:0]s_do_i;
wire s_drdy_i;
wire s_dwe_o;
wire s_rst_o;
wire wr_control_reg;
wire \wr_en[2]_i_1_n_0 ;
wire \wr_en[2]_i_2_n_0 ;
wire \wr_en[4]_i_1_n_0 ;
wire \wr_en[4]_i_6_n_0 ;
wire \wr_en_reg[4]_0 ;
wire \wr_en_reg[4]_1 ;
wire \wr_en_reg[4]_2 ;
wire wr_probe_out_modified;
wire [2:0]xsdb_addr_2_0_p1;
wire [2:0]xsdb_addr_2_0_p2;
wire xsdb_addr_8_p1;
wire xsdb_addr_8_p2;
wire xsdb_drdy_i_1_n_0;
wire xsdb_rd;
wire xsdb_wr;
LUT6 #(
.INIT(64'hAF00AF000FC000C0))
\Bus_data_out[0]_i_1
(.I0(\Bus_Data_out_reg[11] [0]),
.I1(probe_out_modified[0]),
.I2(xsdb_addr_2_0_p2[2]),
.I3(xsdb_addr_2_0_p2[1]),
.I4(committ_int),
.I5(xsdb_addr_2_0_p2[0]),
.O(data_info_probe_in__67[0]));
LUT5 #(
.INIT(32'h88200020))
\Bus_data_out[10]_i_1
(.I0(xsdb_addr_2_0_p2[2]),
.I1(xsdb_addr_2_0_p2[0]),
.I2(probe_out_modified[10]),
.I3(xsdb_addr_2_0_p2[1]),
.I4(\Bus_Data_out_reg[11] [10]),
.O(data_info_probe_in__67[10]));
LUT5 #(
.INIT(32'h88200020))
\Bus_data_out[11]_i_1
(.I0(xsdb_addr_2_0_p2[2]),
.I1(xsdb_addr_2_0_p2[0]),
.I2(probe_out_modified[11]),
.I3(xsdb_addr_2_0_p2[1]),
.I4(\Bus_Data_out_reg[11] [11]),
.O(data_info_probe_in__67[11]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT4 #(
.INIT(16'h0020))
\Bus_data_out[12]_i_1
(.I0(xsdb_addr_2_0_p2[2]),
.I1(xsdb_addr_2_0_p2[1]),
.I2(probe_out_modified[12]),
.I3(xsdb_addr_2_0_p2[0]),
.O(data_info_probe_in__67[12]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT4 #(
.INIT(16'h0020))
\Bus_data_out[13]_i_1
(.I0(xsdb_addr_2_0_p2[2]),
.I1(xsdb_addr_2_0_p2[1]),
.I2(probe_out_modified[13]),
.I3(xsdb_addr_2_0_p2[0]),
.O(data_info_probe_in__67[13]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT4 #(
.INIT(16'h0020))
\Bus_data_out[14]_i_1
(.I0(xsdb_addr_2_0_p2[2]),
.I1(xsdb_addr_2_0_p2[1]),
.I2(probe_out_modified[14]),
.I3(xsdb_addr_2_0_p2[0]),
.O(data_info_probe_in__67[14]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT4 #(
.INIT(16'h0020))
\Bus_data_out[15]_i_1
(.I0(xsdb_addr_2_0_p2[2]),
.I1(xsdb_addr_2_0_p2[1]),
.I2(probe_out_modified[15]),
.I3(xsdb_addr_2_0_p2[0]),
.O(data_info_probe_in__67[15]));
LUT6 #(
.INIT(64'hA0000FC0A00000C0))
\Bus_data_out[1]_i_1
(.I0(\Bus_Data_out_reg[11] [1]),
.I1(probe_out_modified[1]),
.I2(xsdb_addr_2_0_p2[2]),
.I3(xsdb_addr_2_0_p2[1]),
.I4(xsdb_addr_2_0_p2[0]),
.I5(clear_int),
.O(data_info_probe_in__67[1]));
LUT6 #(
.INIT(64'hA0A000000F00CFCF))
\Bus_data_out[2]_i_1
(.I0(\Bus_Data_out_reg[11] [2]),
.I1(probe_out_modified[2]),
.I2(xsdb_addr_2_0_p2[2]),
.I3(int_cnt_rst),
.I4(xsdb_addr_2_0_p2[1]),
.I5(xsdb_addr_2_0_p2[0]),
.O(data_info_probe_in__67[2]));
LUT5 #(
.INIT(32'h88200020))
\Bus_data_out[3]_i_1
(.I0(xsdb_addr_2_0_p2[2]),
.I1(xsdb_addr_2_0_p2[0]),
.I2(probe_out_modified[3]),
.I3(xsdb_addr_2_0_p2[1]),
.I4(\Bus_Data_out_reg[11] [3]),
.O(data_info_probe_in__67[3]));
LUT5 #(
.INIT(32'h88200020))
\Bus_data_out[4]_i_1
(.I0(xsdb_addr_2_0_p2[2]),
.I1(xsdb_addr_2_0_p2[0]),
.I2(probe_out_modified[4]),
.I3(xsdb_addr_2_0_p2[1]),
.I4(\Bus_Data_out_reg[11] [4]),
.O(data_info_probe_in__67[4]));
LUT5 #(
.INIT(32'h88200020))
\Bus_data_out[5]_i_1
(.I0(xsdb_addr_2_0_p2[2]),
.I1(xsdb_addr_2_0_p2[0]),
.I2(probe_out_modified[5]),
.I3(xsdb_addr_2_0_p2[1]),
.I4(\Bus_Data_out_reg[11] [5]),
.O(data_info_probe_in__67[5]));
LUT5 #(
.INIT(32'h88200020))
\Bus_data_out[6]_i_1
(.I0(xsdb_addr_2_0_p2[2]),
.I1(xsdb_addr_2_0_p2[0]),
.I2(probe_out_modified[6]),
.I3(xsdb_addr_2_0_p2[1]),
.I4(\Bus_Data_out_reg[11] [6]),
.O(data_info_probe_in__67[6]));
LUT5 #(
.INIT(32'h88200020))
\Bus_data_out[7]_i_1
(.I0(xsdb_addr_2_0_p2[2]),
.I1(xsdb_addr_2_0_p2[0]),
.I2(probe_out_modified[7]),
.I3(xsdb_addr_2_0_p2[1]),
.I4(\Bus_Data_out_reg[11] [7]),
.O(data_info_probe_in__67[7]));
LUT5 #(
.INIT(32'h88200020))
\Bus_data_out[8]_i_1
(.I0(xsdb_addr_2_0_p2[2]),
.I1(xsdb_addr_2_0_p2[0]),
.I2(probe_out_modified[8]),
.I3(xsdb_addr_2_0_p2[1]),
.I4(\Bus_Data_out_reg[11] [8]),
.O(data_info_probe_in__67[8]));
LUT5 #(
.INIT(32'h88200020))
\Bus_data_out[9]_i_1
(.I0(xsdb_addr_2_0_p2[2]),
.I1(xsdb_addr_2_0_p2[0]),
.I2(probe_out_modified[9]),
.I3(xsdb_addr_2_0_p2[1]),
.I4(\Bus_Data_out_reg[11] [9]),
.O(data_info_probe_in__67[9]));
FDRE \Bus_data_out_reg[0]
(.C(out),
.CE(1'b1),
.D(data_info_probe_in__67[0]),
.Q(s_do_i[0]),
.R(xsdb_addr_8_p2));
FDRE \Bus_data_out_reg[10]
(.C(out),
.CE(1'b1),
.D(data_info_probe_in__67[10]),
.Q(s_do_i[10]),
.R(xsdb_addr_8_p2));
FDRE \Bus_data_out_reg[11]
(.C(out),
.CE(1'b1),
.D(data_info_probe_in__67[11]),
.Q(s_do_i[11]),
.R(xsdb_addr_8_p2));
FDRE \Bus_data_out_reg[12]
(.C(out),
.CE(1'b1),
.D(data_info_probe_in__67[12]),
.Q(s_do_i[12]),
.R(xsdb_addr_8_p2));
FDRE \Bus_data_out_reg[13]
(.C(out),
.CE(1'b1),
.D(data_info_probe_in__67[13]),
.Q(s_do_i[13]),
.R(xsdb_addr_8_p2));
FDRE \Bus_data_out_reg[14]
(.C(out),
.CE(1'b1),
.D(data_info_probe_in__67[14]),
.Q(s_do_i[14]),
.R(xsdb_addr_8_p2));
FDRE \Bus_data_out_reg[15]
(.C(out),
.CE(1'b1),
.D(data_info_probe_in__67[15]),
.Q(s_do_i[15]),
.R(xsdb_addr_8_p2));
FDRE \Bus_data_out_reg[1]
(.C(out),
.CE(1'b1),
.D(data_info_probe_in__67[1]),
.Q(s_do_i[1]),
.R(xsdb_addr_8_p2));
FDRE \Bus_data_out_reg[2]
(.C(out),
.CE(1'b1),
.D(data_info_probe_in__67[2]),
.Q(s_do_i[2]),
.R(xsdb_addr_8_p2));
FDRE \Bus_data_out_reg[3]
(.C(out),
.CE(1'b1),
.D(data_info_probe_in__67[3]),
.Q(s_do_i[3]),
.R(xsdb_addr_8_p2));
FDRE \Bus_data_out_reg[4]
(.C(out),
.CE(1'b1),
.D(data_info_probe_in__67[4]),
.Q(s_do_i[4]),
.R(xsdb_addr_8_p2));
FDRE \Bus_data_out_reg[5]
(.C(out),
.CE(1'b1),
.D(data_info_probe_in__67[5]),
.Q(s_do_i[5]),
.R(xsdb_addr_8_p2));
FDRE \Bus_data_out_reg[6]
(.C(out),
.CE(1'b1),
.D(data_info_probe_in__67[6]),
.Q(s_do_i[6]),
.R(xsdb_addr_8_p2));
FDRE \Bus_data_out_reg[7]
(.C(out),
.CE(1'b1),
.D(data_info_probe_in__67[7]),
.Q(s_do_i[7]),
.R(xsdb_addr_8_p2));
FDRE \Bus_data_out_reg[8]
(.C(out),
.CE(1'b1),
.D(data_info_probe_in__67[8]),
.Q(s_do_i[8]),
.R(xsdb_addr_8_p2));
FDRE \Bus_data_out_reg[9]
(.C(out),
.CE(1'b1),
.D(data_info_probe_in__67[9]),
.Q(s_do_i[9]),
.R(xsdb_addr_8_p2));
FDRE Hold_probe_in_reg
(.C(out),
.CE(wr_control_reg),
.D(Q[3]),
.Q(Hold_probe_in),
.R(s_rst_o));
FDRE clear_int_reg
(.C(out),
.CE(wr_control_reg),
.D(Q[1]),
.Q(clear_int),
.R(s_rst_o));
FDRE committ_int_reg
(.C(out),
.CE(wr_control_reg),
.D(Q[0]),
.Q(committ_int),
.R(s_rst_o));
FDRE int_cnt_rst_reg
(.C(out),
.CE(wr_control_reg),
.D(Q[2]),
.Q(int_cnt_rst),
.R(s_rst_o));
LUT1 #(
.INIT(2'h1))
\probe_in_reg[3]_i_1
(.I0(Hold_probe_in),
.O(E));
FDRE \probe_out_modified_reg[0]
(.C(out),
.CE(wr_probe_out_modified),
.D(Q[0]),
.Q(probe_out_modified[0]),
.R(clear_int));
FDRE \probe_out_modified_reg[10]
(.C(out),
.CE(wr_probe_out_modified),
.D(Q[10]),
.Q(probe_out_modified[10]),
.R(clear_int));
FDRE \probe_out_modified_reg[11]
(.C(out),
.CE(wr_probe_out_modified),
.D(Q[11]),
.Q(probe_out_modified[11]),
.R(clear_int));
FDRE \probe_out_modified_reg[12]
(.C(out),
.CE(wr_probe_out_modified),
.D(Q[12]),
.Q(probe_out_modified[12]),
.R(clear_int));
FDRE \probe_out_modified_reg[13]
(.C(out),
.CE(wr_probe_out_modified),
.D(Q[13]),
.Q(probe_out_modified[13]),
.R(clear_int));
FDRE \probe_out_modified_reg[14]
(.C(out),
.CE(wr_probe_out_modified),
.D(Q[14]),
.Q(probe_out_modified[14]),
.R(clear_int));
FDRE \probe_out_modified_reg[15]
(.C(out),
.CE(wr_probe_out_modified),
.D(Q[15]),
.Q(probe_out_modified[15]),
.R(clear_int));
FDRE \probe_out_modified_reg[1]
(.C(out),
.CE(wr_probe_out_modified),
.D(Q[1]),
.Q(probe_out_modified[1]),
.R(clear_int));
FDRE \probe_out_modified_reg[2]
(.C(out),
.CE(wr_probe_out_modified),
.D(Q[2]),
.Q(probe_out_modified[2]),
.R(clear_int));
FDRE \probe_out_modified_reg[3]
(.C(out),
.CE(wr_probe_out_modified),
.D(Q[3]),
.Q(probe_out_modified[3]),
.R(clear_int));
FDRE \probe_out_modified_reg[4]
(.C(out),
.CE(wr_probe_out_modified),
.D(Q[4]),
.Q(probe_out_modified[4]),
.R(clear_int));
FDRE \probe_out_modified_reg[5]
(.C(out),
.CE(wr_probe_out_modified),
.D(Q[5]),
.Q(probe_out_modified[5]),
.R(clear_int));
FDRE \probe_out_modified_reg[6]
(.C(out),
.CE(wr_probe_out_modified),
.D(Q[6]),
.Q(probe_out_modified[6]),
.R(clear_int));
FDRE \probe_out_modified_reg[7]
(.C(out),
.CE(wr_probe_out_modified),
.D(Q[7]),
.Q(probe_out_modified[7]),
.R(clear_int));
FDRE \probe_out_modified_reg[8]
(.C(out),
.CE(wr_probe_out_modified),
.D(Q[8]),
.Q(probe_out_modified[8]),
.R(clear_int));
FDRE \probe_out_modified_reg[9]
(.C(out),
.CE(wr_probe_out_modified),
.D(Q[9]),
.Q(probe_out_modified[9]),
.R(clear_int));
LUT2 #(
.INIT(4'h2))
rd_en_p1_i_1
(.I0(s_den_o),
.I1(s_dwe_o),
.O(xsdb_rd));
FDRE rd_en_p1_reg
(.C(out),
.CE(1'b1),
.D(xsdb_rd),
.Q(rd_en_p1),
.R(s_rst_o));
FDRE rd_en_p2_reg
(.C(out),
.CE(1'b1),
.D(rd_en_p1),
.Q(rd_en_p2),
.R(s_rst_o));
LUT6 #(
.INIT(64'h0000000000000002))
\wr_en[2]_i_1
(.I0(xsdb_wr),
.I1(s_daddr_o[2]),
.I2(\wr_en_reg[4]_0 ),
.I3(\wr_en_reg[4]_2 ),
.I4(\wr_en_reg[4]_1 ),
.I5(\wr_en[2]_i_2_n_0 ),
.O(\wr_en[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT2 #(
.INIT(4'hB))
\wr_en[2]_i_2
(.I0(s_daddr_o[0]),
.I1(s_daddr_o[1]),
.O(\wr_en[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000000000020000))
\wr_en[4]_i_1
(.I0(xsdb_wr),
.I1(\wr_en_reg[4]_0 ),
.I2(\wr_en_reg[4]_2 ),
.I3(\wr_en_reg[4]_1 ),
.I4(s_daddr_o[2]),
.I5(\wr_en[4]_i_6_n_0 ),
.O(\wr_en[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT2 #(
.INIT(4'h8))
\wr_en[4]_i_2
(.I0(s_den_o),
.I1(s_dwe_o),
.O(xsdb_wr));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\wr_en[4]_i_3
(.I0(s_daddr_o[15]),
.I1(s_daddr_o[16]),
.I2(s_daddr_o[13]),
.I3(s_daddr_o[14]),
.I4(s_daddr_o[4]),
.I5(s_daddr_o[3]),
.O(\wr_en_reg[4]_0 ));
LUT4 #(
.INIT(16'hFFFE))
\wr_en[4]_i_4
(.I0(s_daddr_o[6]),
.I1(s_daddr_o[5]),
.I2(s_daddr_o[8]),
.I3(s_daddr_o[7]),
.O(\wr_en_reg[4]_2 ));
LUT4 #(
.INIT(16'hFFFE))
\wr_en[4]_i_5
(.I0(s_daddr_o[10]),
.I1(s_daddr_o[9]),
.I2(s_daddr_o[12]),
.I3(s_daddr_o[11]),
.O(\wr_en_reg[4]_1 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT2 #(
.INIT(4'hE))
\wr_en[4]_i_6
(.I0(s_daddr_o[0]),
.I1(s_daddr_o[1]),
.O(\wr_en[4]_i_6_n_0 ));
FDRE \wr_en_reg[2]
(.C(out),
.CE(1'b1),
.D(\wr_en[2]_i_1_n_0 ),
.Q(wr_control_reg),
.R(1'b0));
FDRE \wr_en_reg[4]
(.C(out),
.CE(1'b1),
.D(\wr_en[4]_i_1_n_0 ),
.Q(wr_probe_out_modified),
.R(1'b0));
FDRE \xsdb_addr_2_0_p1_reg[0]
(.C(out),
.CE(1'b1),
.D(s_daddr_o[0]),
.Q(xsdb_addr_2_0_p1[0]),
.R(1'b0));
FDRE \xsdb_addr_2_0_p1_reg[1]
(.C(out),
.CE(1'b1),
.D(s_daddr_o[1]),
.Q(xsdb_addr_2_0_p1[1]),
.R(1'b0));
FDRE \xsdb_addr_2_0_p1_reg[2]
(.C(out),
.CE(1'b1),
.D(s_daddr_o[2]),
.Q(xsdb_addr_2_0_p1[2]),
.R(1'b0));
FDRE \xsdb_addr_2_0_p2_reg[0]
(.C(out),
.CE(1'b1),
.D(xsdb_addr_2_0_p1[0]),
.Q(xsdb_addr_2_0_p2[0]),
.R(1'b0));
FDRE \xsdb_addr_2_0_p2_reg[1]
(.C(out),
.CE(1'b1),
.D(xsdb_addr_2_0_p1[1]),
.Q(xsdb_addr_2_0_p2[1]),
.R(1'b0));
FDRE \xsdb_addr_2_0_p2_reg[2]
(.C(out),
.CE(1'b1),
.D(xsdb_addr_2_0_p1[2]),
.Q(xsdb_addr_2_0_p2[2]),
.R(1'b0));
FDRE xsdb_addr_8_p1_reg
(.C(out),
.CE(1'b1),
.D(s_daddr_o[8]),
.Q(xsdb_addr_8_p1),
.R(1'b0));
FDRE xsdb_addr_8_p2_reg
(.C(out),
.CE(1'b1),
.D(xsdb_addr_8_p1),
.Q(xsdb_addr_8_p2),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'hF8))
xsdb_drdy_i_1
(.I0(s_dwe_o),
.I1(s_den_o),
.I2(rd_en_p2),
.O(xsdb_drdy_i_1_n_0));
FDRE xsdb_drdy_reg
(.C(out),
.CE(1'b1),
.D(xsdb_drdy_i_1_n_0),
.Q(s_drdy_i),
.R(s_rst_o));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_probe_in_one
(Q,
out,
\wr_en[4]_i_3 ,
\wr_en[4]_i_4 ,
\wr_en[4]_i_5 ,
s_daddr_o,
s_dwe_o,
s_den_o,
E,
D,
clk,
s_rst_o);
output [11:0]Q;
input out;
input \wr_en[4]_i_3 ;
input \wr_en[4]_i_4 ;
input \wr_en[4]_i_5 ;
input [2:0]s_daddr_o;
input s_dwe_o;
input s_den_o;
input [0:0]E;
input [3:0]D;
input clk;
input s_rst_o;
wire [3:0]D;
wire \DECODER_INST/rd_en_int_7 ;
wire [0:0]E;
wire [11:0]Q;
wire Read_int;
wire Read_int_i_2_n_0;
wire clk;
(* async_reg = "true" *) wire [3:0]data_int_sync1;
(* async_reg = "true" *) wire [3:0]data_int_sync2;
wire \dn_activity[0]_i_1_n_0 ;
wire \dn_activity[1]_i_1_n_0 ;
wire \dn_activity[2]_i_1_n_0 ;
wire \dn_activity[3]_i_1_n_0 ;
wire \dn_activity_reg_n_0_[0] ;
wire \dn_activity_reg_n_0_[3] ;
wire out;
wire p_6_in;
wire p_9_in;
(* DONT_TOUCH *) wire [3:0]probe_in_reg;
(* MAX_FANOUT = "200" *) (* RTL_MAX_FANOUT = "found" *) wire read_done;
wire read_done_i_1_n_0;
wire [2:0]s_daddr_o;
wire s_den_o;
wire s_dwe_o;
wire s_rst_o;
wire \up_activity[0]_i_1_n_0 ;
wire \up_activity[1]_i_1_n_0 ;
wire \up_activity[2]_i_1_n_0 ;
wire \up_activity[3]_i_1_n_0 ;
wire \up_activity_reg_n_0_[0] ;
wire \up_activity_reg_n_0_[1] ;
wire \up_activity_reg_n_0_[2] ;
wire \up_activity_reg_n_0_[3] ;
wire \wr_en[4]_i_3 ;
wire \wr_en[4]_i_4 ;
wire \wr_en[4]_i_5 ;
FDRE \Bus_Data_out_reg[0]
(.C(out),
.CE(1'b1),
.D(data_int_sync2[0]),
.Q(Q[0]),
.R(1'b0));
FDRE \Bus_Data_out_reg[10]
(.C(out),
.CE(1'b1),
.D(p_9_in),
.Q(Q[10]),
.R(1'b0));
FDRE \Bus_Data_out_reg[11]
(.C(out),
.CE(1'b1),
.D(\dn_activity_reg_n_0_[3] ),
.Q(Q[11]),
.R(1'b0));
FDRE \Bus_Data_out_reg[1]
(.C(out),
.CE(1'b1),
.D(data_int_sync2[1]),
.Q(Q[1]),
.R(1'b0));
FDRE \Bus_Data_out_reg[2]
(.C(out),
.CE(1'b1),
.D(data_int_sync2[2]),
.Q(Q[2]),
.R(1'b0));
FDRE \Bus_Data_out_reg[3]
(.C(out),
.CE(1'b1),
.D(data_int_sync2[3]),
.Q(Q[3]),
.R(1'b0));
FDRE \Bus_Data_out_reg[4]
(.C(out),
.CE(1'b1),
.D(\up_activity_reg_n_0_[0] ),
.Q(Q[4]),
.R(1'b0));
FDRE \Bus_Data_out_reg[5]
(.C(out),
.CE(1'b1),
.D(\up_activity_reg_n_0_[1] ),
.Q(Q[5]),
.R(1'b0));
FDRE \Bus_Data_out_reg[6]
(.C(out),
.CE(1'b1),
.D(\up_activity_reg_n_0_[2] ),
.Q(Q[6]),
.R(1'b0));
FDRE \Bus_Data_out_reg[7]
(.C(out),
.CE(1'b1),
.D(\up_activity_reg_n_0_[3] ),
.Q(Q[7]),
.R(1'b0));
FDRE \Bus_Data_out_reg[8]
(.C(out),
.CE(1'b1),
.D(\dn_activity_reg_n_0_[0] ),
.Q(Q[8]),
.R(1'b0));
FDRE \Bus_Data_out_reg[9]
(.C(out),
.CE(1'b1),
.D(p_6_in),
.Q(Q[9]),
.R(1'b0));
LUT4 #(
.INIT(16'h0002))
Read_int_i_1
(.I0(Read_int_i_2_n_0),
.I1(\wr_en[4]_i_3 ),
.I2(\wr_en[4]_i_4 ),
.I3(\wr_en[4]_i_5 ),
.O(\DECODER_INST/rd_en_int_7 ));
LUT5 #(
.INIT(32'h00800000))
Read_int_i_2
(.I0(s_daddr_o[0]),
.I1(s_daddr_o[1]),
.I2(s_daddr_o[2]),
.I3(s_dwe_o),
.I4(s_den_o),
.O(Read_int_i_2_n_0));
FDRE Read_int_reg
(.C(out),
.CE(1'b1),
.D(\DECODER_INST/rd_en_int_7 ),
.Q(Read_int),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\data_int_sync1_reg[0]
(.C(out),
.CE(1'b1),
.D(probe_in_reg[0]),
.Q(data_int_sync1[0]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\data_int_sync1_reg[1]
(.C(out),
.CE(1'b1),
.D(probe_in_reg[1]),
.Q(data_int_sync1[1]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\data_int_sync1_reg[2]
(.C(out),
.CE(1'b1),
.D(probe_in_reg[2]),
.Q(data_int_sync1[2]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\data_int_sync1_reg[3]
(.C(out),
.CE(1'b1),
.D(probe_in_reg[3]),
.Q(data_int_sync1[3]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\data_int_sync2_reg[0]
(.C(out),
.CE(1'b1),
.D(data_int_sync1[0]),
.Q(data_int_sync2[0]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\data_int_sync2_reg[1]
(.C(out),
.CE(1'b1),
.D(data_int_sync1[1]),
.Q(data_int_sync2[1]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\data_int_sync2_reg[2]
(.C(out),
.CE(1'b1),
.D(data_int_sync1[2]),
.Q(data_int_sync2[2]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\data_int_sync2_reg[3]
(.C(out),
.CE(1'b1),
.D(data_int_sync1[3]),
.Q(data_int_sync2[3]),
.R(1'b0));
LUT3 #(
.INIT(8'hBA))
\dn_activity[0]_i_1
(.I0(\dn_activity_reg_n_0_[0] ),
.I1(data_int_sync1[0]),
.I2(data_int_sync2[0]),
.O(\dn_activity[0]_i_1_n_0 ));
LUT3 #(
.INIT(8'hBA))
\dn_activity[1]_i_1
(.I0(p_6_in),
.I1(data_int_sync1[1]),
.I2(data_int_sync2[1]),
.O(\dn_activity[1]_i_1_n_0 ));
LUT3 #(
.INIT(8'hBA))
\dn_activity[2]_i_1
(.I0(p_9_in),
.I1(data_int_sync1[2]),
.I2(data_int_sync2[2]),
.O(\dn_activity[2]_i_1_n_0 ));
LUT3 #(
.INIT(8'hBA))
\dn_activity[3]_i_1
(.I0(\dn_activity_reg_n_0_[3] ),
.I1(data_int_sync1[3]),
.I2(data_int_sync2[3]),
.O(\dn_activity[3]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\dn_activity_reg[0]
(.C(out),
.CE(1'b1),
.D(\dn_activity[0]_i_1_n_0 ),
.Q(\dn_activity_reg_n_0_[0] ),
.R(read_done));
FDRE #(
.INIT(1'b0))
\dn_activity_reg[1]
(.C(out),
.CE(1'b1),
.D(\dn_activity[1]_i_1_n_0 ),
.Q(p_6_in),
.R(read_done));
FDRE #(
.INIT(1'b0))
\dn_activity_reg[2]
(.C(out),
.CE(1'b1),
.D(\dn_activity[2]_i_1_n_0 ),
.Q(p_9_in),
.R(read_done));
FDRE #(
.INIT(1'b0))
\dn_activity_reg[3]
(.C(out),
.CE(1'b1),
.D(\dn_activity[3]_i_1_n_0 ),
.Q(\dn_activity_reg_n_0_[3] ),
.R(read_done));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\probe_in_reg_reg[0]
(.C(clk),
.CE(E),
.D(D[0]),
.Q(probe_in_reg[0]),
.R(1'b0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\probe_in_reg_reg[1]
(.C(clk),
.CE(E),
.D(D[1]),
.Q(probe_in_reg[1]),
.R(1'b0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\probe_in_reg_reg[2]
(.C(clk),
.CE(E),
.D(D[2]),
.Q(probe_in_reg[2]),
.R(1'b0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\probe_in_reg_reg[3]
(.C(clk),
.CE(E),
.D(D[3]),
.Q(probe_in_reg[3]),
.R(1'b0));
LUT3 #(
.INIT(8'h02))
read_done_i_1
(.I0(Read_int),
.I1(read_done),
.I2(s_rst_o),
.O(read_done_i_1_n_0));
(* RTL_MAX_FANOUT = "found" *)
FDRE read_done_reg
(.C(out),
.CE(1'b1),
.D(read_done_i_1_n_0),
.Q(read_done),
.R(1'b0));
LUT3 #(
.INIT(8'hBA))
\up_activity[0]_i_1
(.I0(\up_activity_reg_n_0_[0] ),
.I1(data_int_sync2[0]),
.I2(data_int_sync1[0]),
.O(\up_activity[0]_i_1_n_0 ));
LUT3 #(
.INIT(8'hBA))
\up_activity[1]_i_1
(.I0(\up_activity_reg_n_0_[1] ),
.I1(data_int_sync2[1]),
.I2(data_int_sync1[1]),
.O(\up_activity[1]_i_1_n_0 ));
LUT3 #(
.INIT(8'hBA))
\up_activity[2]_i_1
(.I0(\up_activity_reg_n_0_[2] ),
.I1(data_int_sync2[2]),
.I2(data_int_sync1[2]),
.O(\up_activity[2]_i_1_n_0 ));
LUT3 #(
.INIT(8'hBA))
\up_activity[3]_i_1
(.I0(\up_activity_reg_n_0_[3] ),
.I1(data_int_sync2[3]),
.I2(data_int_sync1[3]),
.O(\up_activity[3]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\up_activity_reg[0]
(.C(out),
.CE(1'b1),
.D(\up_activity[0]_i_1_n_0 ),
.Q(\up_activity_reg_n_0_[0] ),
.R(read_done));
FDRE #(
.INIT(1'b0))
\up_activity_reg[1]
(.C(out),
.CE(1'b1),
.D(\up_activity[1]_i_1_n_0 ),
.Q(\up_activity_reg_n_0_[1] ),
.R(read_done));
FDRE #(
.INIT(1'b0))
\up_activity_reg[2]
(.C(out),
.CE(1'b1),
.D(\up_activity[2]_i_1_n_0 ),
.Q(\up_activity_reg_n_0_[2] ),
.R(read_done));
FDRE #(
.INIT(1'b0))
\up_activity_reg[3]
(.C(out),
.CE(1'b1),
.D(\up_activity[3]_i_1_n_0 ),
.Q(\up_activity_reg_n_0_[3] ),
.R(read_done));
endmodule
(* C_BUILD_REVISION = "0" *) (* C_BUS_ADDR_WIDTH = "17" *) (* C_BUS_DATA_WIDTH = "16" *)
(* C_CORE_INFO1 = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) (* C_CORE_INFO2 = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) (* C_CORE_MAJOR_VER = "2" *)
(* C_CORE_MINOR_ALPHA_VER = "97" *) (* C_CORE_MINOR_VER = "0" *) (* C_CORE_TYPE = "2" *)
(* C_CSE_DRV_VER = "1" *) (* C_EN_PROBE_IN_ACTIVITY = "1" *) (* C_EN_SYNCHRONIZATION = "1" *)
(* C_MAJOR_VERSION = "2013" *) (* C_MAX_NUM_PROBE = "256" *) (* C_MAX_WIDTH_PER_PROBE = "256" *)
(* C_MINOR_VERSION = "1" *) (* C_NEXT_SLAVE = "0" *) (* C_NUM_PROBE_IN = "4" *)
(* C_NUM_PROBE_OUT = "0" *) (* C_PIPE_IFACE = "0" *) (* C_PROBE_IN0_WIDTH = "1" *)
(* C_PROBE_IN100_WIDTH = "1" *) (* C_PROBE_IN101_WIDTH = "1" *) (* C_PROBE_IN102_WIDTH = "1" *)
(* C_PROBE_IN103_WIDTH = "1" *) (* C_PROBE_IN104_WIDTH = "1" *) (* C_PROBE_IN105_WIDTH = "1" *)
(* C_PROBE_IN106_WIDTH = "1" *) (* C_PROBE_IN107_WIDTH = "1" *) (* C_PROBE_IN108_WIDTH = "1" *)
(* C_PROBE_IN109_WIDTH = "1" *) (* C_PROBE_IN10_WIDTH = "1" *) (* C_PROBE_IN110_WIDTH = "1" *)
(* C_PROBE_IN111_WIDTH = "1" *) (* C_PROBE_IN112_WIDTH = "1" *) (* C_PROBE_IN113_WIDTH = "1" *)
(* C_PROBE_IN114_WIDTH = "1" *) (* C_PROBE_IN115_WIDTH = "1" *) (* C_PROBE_IN116_WIDTH = "1" *)
(* C_PROBE_IN117_WIDTH = "1" *) (* C_PROBE_IN118_WIDTH = "1" *) (* C_PROBE_IN119_WIDTH = "1" *)
(* C_PROBE_IN11_WIDTH = "1" *) (* C_PROBE_IN120_WIDTH = "1" *) (* C_PROBE_IN121_WIDTH = "1" *)
(* C_PROBE_IN122_WIDTH = "1" *) (* C_PROBE_IN123_WIDTH = "1" *) (* C_PROBE_IN124_WIDTH = "1" *)
(* C_PROBE_IN125_WIDTH = "1" *) (* C_PROBE_IN126_WIDTH = "1" *) (* C_PROBE_IN127_WIDTH = "1" *)
(* C_PROBE_IN128_WIDTH = "1" *) (* C_PROBE_IN129_WIDTH = "1" *) (* C_PROBE_IN12_WIDTH = "1" *)
(* C_PROBE_IN130_WIDTH = "1" *) (* C_PROBE_IN131_WIDTH = "1" *) (* C_PROBE_IN132_WIDTH = "1" *)
(* C_PROBE_IN133_WIDTH = "1" *) (* C_PROBE_IN134_WIDTH = "1" *) (* C_PROBE_IN135_WIDTH = "1" *)
(* C_PROBE_IN136_WIDTH = "1" *) (* C_PROBE_IN137_WIDTH = "1" *) (* C_PROBE_IN138_WIDTH = "1" *)
(* C_PROBE_IN139_WIDTH = "1" *) (* C_PROBE_IN13_WIDTH = "1" *) (* C_PROBE_IN140_WIDTH = "1" *)
(* C_PROBE_IN141_WIDTH = "1" *) (* C_PROBE_IN142_WIDTH = "1" *) (* C_PROBE_IN143_WIDTH = "1" *)
(* C_PROBE_IN144_WIDTH = "1" *) (* C_PROBE_IN145_WIDTH = "1" *) (* C_PROBE_IN146_WIDTH = "1" *)
(* C_PROBE_IN147_WIDTH = "1" *) (* C_PROBE_IN148_WIDTH = "1" *) (* C_PROBE_IN149_WIDTH = "1" *)
(* C_PROBE_IN14_WIDTH = "1" *) (* C_PROBE_IN150_WIDTH = "1" *) (* C_PROBE_IN151_WIDTH = "1" *)
(* C_PROBE_IN152_WIDTH = "1" *) (* C_PROBE_IN153_WIDTH = "1" *) (* C_PROBE_IN154_WIDTH = "1" *)
(* C_PROBE_IN155_WIDTH = "1" *) (* C_PROBE_IN156_WIDTH = "1" *) (* C_PROBE_IN157_WIDTH = "1" *)
(* C_PROBE_IN158_WIDTH = "1" *) (* C_PROBE_IN159_WIDTH = "1" *) (* C_PROBE_IN15_WIDTH = "1" *)
(* C_PROBE_IN160_WIDTH = "1" *) (* C_PROBE_IN161_WIDTH = "1" *) (* C_PROBE_IN162_WIDTH = "1" *)
(* C_PROBE_IN163_WIDTH = "1" *) (* C_PROBE_IN164_WIDTH = "1" *) (* C_PROBE_IN165_WIDTH = "1" *)
(* C_PROBE_IN166_WIDTH = "1" *) (* C_PROBE_IN167_WIDTH = "1" *) (* C_PROBE_IN168_WIDTH = "1" *)
(* C_PROBE_IN169_WIDTH = "1" *) (* C_PROBE_IN16_WIDTH = "1" *) (* C_PROBE_IN170_WIDTH = "1" *)
(* C_PROBE_IN171_WIDTH = "1" *) (* C_PROBE_IN172_WIDTH = "1" *) (* C_PROBE_IN173_WIDTH = "1" *)
(* C_PROBE_IN174_WIDTH = "1" *) (* C_PROBE_IN175_WIDTH = "1" *) (* C_PROBE_IN176_WIDTH = "1" *)
(* C_PROBE_IN177_WIDTH = "1" *) (* C_PROBE_IN178_WIDTH = "1" *) (* C_PROBE_IN179_WIDTH = "1" *)
(* C_PROBE_IN17_WIDTH = "1" *) (* C_PROBE_IN180_WIDTH = "1" *) (* C_PROBE_IN181_WIDTH = "1" *)
(* C_PROBE_IN182_WIDTH = "1" *) (* C_PROBE_IN183_WIDTH = "1" *) (* C_PROBE_IN184_WIDTH = "1" *)
(* C_PROBE_IN185_WIDTH = "1" *) (* C_PROBE_IN186_WIDTH = "1" *) (* C_PROBE_IN187_WIDTH = "1" *)
(* C_PROBE_IN188_WIDTH = "1" *) (* C_PROBE_IN189_WIDTH = "1" *) (* C_PROBE_IN18_WIDTH = "1" *)
(* C_PROBE_IN190_WIDTH = "1" *) (* C_PROBE_IN191_WIDTH = "1" *) (* C_PROBE_IN192_WIDTH = "1" *)
(* C_PROBE_IN193_WIDTH = "1" *) (* C_PROBE_IN194_WIDTH = "1" *) (* C_PROBE_IN195_WIDTH = "1" *)
(* C_PROBE_IN196_WIDTH = "1" *) (* C_PROBE_IN197_WIDTH = "1" *) (* C_PROBE_IN198_WIDTH = "1" *)
(* C_PROBE_IN199_WIDTH = "1" *) (* C_PROBE_IN19_WIDTH = "1" *) (* C_PROBE_IN1_WIDTH = "1" *)
(* C_PROBE_IN200_WIDTH = "1" *) (* C_PROBE_IN201_WIDTH = "1" *) (* C_PROBE_IN202_WIDTH = "1" *)
(* C_PROBE_IN203_WIDTH = "1" *) (* C_PROBE_IN204_WIDTH = "1" *) (* C_PROBE_IN205_WIDTH = "1" *)
(* C_PROBE_IN206_WIDTH = "1" *) (* C_PROBE_IN207_WIDTH = "1" *) (* C_PROBE_IN208_WIDTH = "1" *)
(* C_PROBE_IN209_WIDTH = "1" *) (* C_PROBE_IN20_WIDTH = "1" *) (* C_PROBE_IN210_WIDTH = "1" *)
(* C_PROBE_IN211_WIDTH = "1" *) (* C_PROBE_IN212_WIDTH = "1" *) (* C_PROBE_IN213_WIDTH = "1" *)
(* C_PROBE_IN214_WIDTH = "1" *) (* C_PROBE_IN215_WIDTH = "1" *) (* C_PROBE_IN216_WIDTH = "1" *)
(* C_PROBE_IN217_WIDTH = "1" *) (* C_PROBE_IN218_WIDTH = "1" *) (* C_PROBE_IN219_WIDTH = "1" *)
(* C_PROBE_IN21_WIDTH = "1" *) (* C_PROBE_IN220_WIDTH = "1" *) (* C_PROBE_IN221_WIDTH = "1" *)
(* C_PROBE_IN222_WIDTH = "1" *) (* C_PROBE_IN223_WIDTH = "1" *) (* C_PROBE_IN224_WIDTH = "1" *)
(* C_PROBE_IN225_WIDTH = "1" *) (* C_PROBE_IN226_WIDTH = "1" *) (* C_PROBE_IN227_WIDTH = "1" *)
(* C_PROBE_IN228_WIDTH = "1" *) (* C_PROBE_IN229_WIDTH = "1" *) (* C_PROBE_IN22_WIDTH = "1" *)
(* C_PROBE_IN230_WIDTH = "1" *) (* C_PROBE_IN231_WIDTH = "1" *) (* C_PROBE_IN232_WIDTH = "1" *)
(* C_PROBE_IN233_WIDTH = "1" *) (* C_PROBE_IN234_WIDTH = "1" *) (* C_PROBE_IN235_WIDTH = "1" *)
(* C_PROBE_IN236_WIDTH = "1" *) (* C_PROBE_IN237_WIDTH = "1" *) (* C_PROBE_IN238_WIDTH = "1" *)
(* C_PROBE_IN239_WIDTH = "1" *) (* C_PROBE_IN23_WIDTH = "1" *) (* C_PROBE_IN240_WIDTH = "1" *)
(* C_PROBE_IN241_WIDTH = "1" *) (* C_PROBE_IN242_WIDTH = "1" *) (* C_PROBE_IN243_WIDTH = "1" *)
(* C_PROBE_IN244_WIDTH = "1" *) (* C_PROBE_IN245_WIDTH = "1" *) (* C_PROBE_IN246_WIDTH = "1" *)
(* C_PROBE_IN247_WIDTH = "1" *) (* C_PROBE_IN248_WIDTH = "1" *) (* C_PROBE_IN249_WIDTH = "1" *)
(* C_PROBE_IN24_WIDTH = "1" *) (* C_PROBE_IN250_WIDTH = "1" *) (* C_PROBE_IN251_WIDTH = "1" *)
(* C_PROBE_IN252_WIDTH = "1" *) (* C_PROBE_IN253_WIDTH = "1" *) (* C_PROBE_IN254_WIDTH = "1" *)
(* C_PROBE_IN255_WIDTH = "1" *) (* C_PROBE_IN25_WIDTH = "1" *) (* C_PROBE_IN26_WIDTH = "1" *)
(* C_PROBE_IN27_WIDTH = "1" *) (* C_PROBE_IN28_WIDTH = "1" *) (* C_PROBE_IN29_WIDTH = "1" *)
(* C_PROBE_IN2_WIDTH = "1" *) (* C_PROBE_IN30_WIDTH = "1" *) (* C_PROBE_IN31_WIDTH = "1" *)
(* C_PROBE_IN32_WIDTH = "1" *) (* C_PROBE_IN33_WIDTH = "1" *) (* C_PROBE_IN34_WIDTH = "1" *)
(* C_PROBE_IN35_WIDTH = "1" *) (* C_PROBE_IN36_WIDTH = "1" *) (* C_PROBE_IN37_WIDTH = "1" *)
(* C_PROBE_IN38_WIDTH = "1" *) (* C_PROBE_IN39_WIDTH = "1" *) (* C_PROBE_IN3_WIDTH = "1" *)
(* C_PROBE_IN40_WIDTH = "1" *) (* C_PROBE_IN41_WIDTH = "1" *) (* C_PROBE_IN42_WIDTH = "1" *)
(* C_PROBE_IN43_WIDTH = "1" *) (* C_PROBE_IN44_WIDTH = "1" *) (* C_PROBE_IN45_WIDTH = "1" *)
(* C_PROBE_IN46_WIDTH = "1" *) (* C_PROBE_IN47_WIDTH = "1" *) (* C_PROBE_IN48_WIDTH = "1" *)
(* C_PROBE_IN49_WIDTH = "1" *) (* C_PROBE_IN4_WIDTH = "1" *) (* C_PROBE_IN50_WIDTH = "1" *)
(* C_PROBE_IN51_WIDTH = "1" *) (* C_PROBE_IN52_WIDTH = "1" *) (* C_PROBE_IN53_WIDTH = "1" *)
(* C_PROBE_IN54_WIDTH = "1" *) (* C_PROBE_IN55_WIDTH = "1" *) (* C_PROBE_IN56_WIDTH = "1" *)
(* C_PROBE_IN57_WIDTH = "1" *) (* C_PROBE_IN58_WIDTH = "1" *) (* C_PROBE_IN59_WIDTH = "1" *)
(* C_PROBE_IN5_WIDTH = "1" *) (* C_PROBE_IN60_WIDTH = "1" *) (* C_PROBE_IN61_WIDTH = "1" *)
(* C_PROBE_IN62_WIDTH = "1" *) (* C_PROBE_IN63_WIDTH = "1" *) (* C_PROBE_IN64_WIDTH = "1" *)
(* C_PROBE_IN65_WIDTH = "1" *) (* C_PROBE_IN66_WIDTH = "1" *) (* C_PROBE_IN67_WIDTH = "1" *)
(* C_PROBE_IN68_WIDTH = "1" *) (* C_PROBE_IN69_WIDTH = "1" *) (* C_PROBE_IN6_WIDTH = "1" *)
(* C_PROBE_IN70_WIDTH = "1" *) (* C_PROBE_IN71_WIDTH = "1" *) (* C_PROBE_IN72_WIDTH = "1" *)
(* C_PROBE_IN73_WIDTH = "1" *) (* C_PROBE_IN74_WIDTH = "1" *) (* C_PROBE_IN75_WIDTH = "1" *)
(* C_PROBE_IN76_WIDTH = "1" *) (* C_PROBE_IN77_WIDTH = "1" *) (* C_PROBE_IN78_WIDTH = "1" *)
(* C_PROBE_IN79_WIDTH = "1" *) (* C_PROBE_IN7_WIDTH = "1" *) (* C_PROBE_IN80_WIDTH = "1" *)
(* C_PROBE_IN81_WIDTH = "1" *) (* C_PROBE_IN82_WIDTH = "1" *) (* C_PROBE_IN83_WIDTH = "1" *)
(* C_PROBE_IN84_WIDTH = "1" *) (* C_PROBE_IN85_WIDTH = "1" *) (* C_PROBE_IN86_WIDTH = "1" *)
(* C_PROBE_IN87_WIDTH = "1" *) (* C_PROBE_IN88_WIDTH = "1" *) (* C_PROBE_IN89_WIDTH = "1" *)
(* C_PROBE_IN8_WIDTH = "1" *) (* C_PROBE_IN90_WIDTH = "1" *) (* C_PROBE_IN91_WIDTH = "1" *)
(* C_PROBE_IN92_WIDTH = "1" *) (* C_PROBE_IN93_WIDTH = "1" *) (* C_PROBE_IN94_WIDTH = "1" *)
(* C_PROBE_IN95_WIDTH = "1" *) (* C_PROBE_IN96_WIDTH = "1" *) (* C_PROBE_IN97_WIDTH = "1" *)
(* C_PROBE_IN98_WIDTH = "1" *) (* C_PROBE_IN99_WIDTH = "1" *) (* C_PROBE_IN9_WIDTH = "1" *)
(* C_PROBE_OUT0_INIT_VAL = "1'b0" *) (* C_PROBE_OUT0_WIDTH = "1" *) (* C_PROBE_OUT100_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT100_WIDTH = "1" *) (* C_PROBE_OUT101_INIT_VAL = "1'b0" *) (* C_PROBE_OUT101_WIDTH = "1" *)
(* C_PROBE_OUT102_INIT_VAL = "1'b0" *) (* C_PROBE_OUT102_WIDTH = "1" *) (* C_PROBE_OUT103_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT103_WIDTH = "1" *) (* C_PROBE_OUT104_INIT_VAL = "1'b0" *) (* C_PROBE_OUT104_WIDTH = "1" *)
(* C_PROBE_OUT105_INIT_VAL = "1'b0" *) (* C_PROBE_OUT105_WIDTH = "1" *) (* C_PROBE_OUT106_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT106_WIDTH = "1" *) (* C_PROBE_OUT107_INIT_VAL = "1'b0" *) (* C_PROBE_OUT107_WIDTH = "1" *)
(* C_PROBE_OUT108_INIT_VAL = "1'b0" *) (* C_PROBE_OUT108_WIDTH = "1" *) (* C_PROBE_OUT109_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT109_WIDTH = "1" *) (* C_PROBE_OUT10_INIT_VAL = "1'b0" *) (* C_PROBE_OUT10_WIDTH = "1" *)
(* C_PROBE_OUT110_INIT_VAL = "1'b0" *) (* C_PROBE_OUT110_WIDTH = "1" *) (* C_PROBE_OUT111_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT111_WIDTH = "1" *) (* C_PROBE_OUT112_INIT_VAL = "1'b0" *) (* C_PROBE_OUT112_WIDTH = "1" *)
(* C_PROBE_OUT113_INIT_VAL = "1'b0" *) (* C_PROBE_OUT113_WIDTH = "1" *) (* C_PROBE_OUT114_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT114_WIDTH = "1" *) (* C_PROBE_OUT115_INIT_VAL = "1'b0" *) (* C_PROBE_OUT115_WIDTH = "1" *)
(* C_PROBE_OUT116_INIT_VAL = "1'b0" *) (* C_PROBE_OUT116_WIDTH = "1" *) (* C_PROBE_OUT117_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT117_WIDTH = "1" *) (* C_PROBE_OUT118_INIT_VAL = "1'b0" *) (* C_PROBE_OUT118_WIDTH = "1" *)
(* C_PROBE_OUT119_INIT_VAL = "1'b0" *) (* C_PROBE_OUT119_WIDTH = "1" *) (* C_PROBE_OUT11_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT11_WIDTH = "1" *) (* C_PROBE_OUT120_INIT_VAL = "1'b0" *) (* C_PROBE_OUT120_WIDTH = "1" *)
(* C_PROBE_OUT121_INIT_VAL = "1'b0" *) (* C_PROBE_OUT121_WIDTH = "1" *) (* C_PROBE_OUT122_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT122_WIDTH = "1" *) (* C_PROBE_OUT123_INIT_VAL = "1'b0" *) (* C_PROBE_OUT123_WIDTH = "1" *)
(* C_PROBE_OUT124_INIT_VAL = "1'b0" *) (* C_PROBE_OUT124_WIDTH = "1" *) (* C_PROBE_OUT125_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT125_WIDTH = "1" *) (* C_PROBE_OUT126_INIT_VAL = "1'b0" *) (* C_PROBE_OUT126_WIDTH = "1" *)
(* C_PROBE_OUT127_INIT_VAL = "1'b0" *) (* C_PROBE_OUT127_WIDTH = "1" *) (* C_PROBE_OUT128_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT128_WIDTH = "1" *) (* C_PROBE_OUT129_INIT_VAL = "1'b0" *) (* C_PROBE_OUT129_WIDTH = "1" *)
(* C_PROBE_OUT12_INIT_VAL = "1'b0" *) (* C_PROBE_OUT12_WIDTH = "1" *) (* C_PROBE_OUT130_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT130_WIDTH = "1" *) (* C_PROBE_OUT131_INIT_VAL = "1'b0" *) (* C_PROBE_OUT131_WIDTH = "1" *)
(* C_PROBE_OUT132_INIT_VAL = "1'b0" *) (* C_PROBE_OUT132_WIDTH = "1" *) (* C_PROBE_OUT133_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT133_WIDTH = "1" *) (* C_PROBE_OUT134_INIT_VAL = "1'b0" *) (* C_PROBE_OUT134_WIDTH = "1" *)
(* C_PROBE_OUT135_INIT_VAL = "1'b0" *) (* C_PROBE_OUT135_WIDTH = "1" *) (* C_PROBE_OUT136_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT136_WIDTH = "1" *) (* C_PROBE_OUT137_INIT_VAL = "1'b0" *) (* C_PROBE_OUT137_WIDTH = "1" *)
(* C_PROBE_OUT138_INIT_VAL = "1'b0" *) (* C_PROBE_OUT138_WIDTH = "1" *) (* C_PROBE_OUT139_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT139_WIDTH = "1" *) (* C_PROBE_OUT13_INIT_VAL = "1'b0" *) (* C_PROBE_OUT13_WIDTH = "1" *)
(* C_PROBE_OUT140_INIT_VAL = "1'b0" *) (* C_PROBE_OUT140_WIDTH = "1" *) (* C_PROBE_OUT141_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT141_WIDTH = "1" *) (* C_PROBE_OUT142_INIT_VAL = "1'b0" *) (* C_PROBE_OUT142_WIDTH = "1" *)
(* C_PROBE_OUT143_INIT_VAL = "1'b0" *) (* C_PROBE_OUT143_WIDTH = "1" *) (* C_PROBE_OUT144_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT144_WIDTH = "1" *) (* C_PROBE_OUT145_INIT_VAL = "1'b0" *) (* C_PROBE_OUT145_WIDTH = "1" *)
(* C_PROBE_OUT146_INIT_VAL = "1'b0" *) (* C_PROBE_OUT146_WIDTH = "1" *) (* C_PROBE_OUT147_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT147_WIDTH = "1" *) (* C_PROBE_OUT148_INIT_VAL = "1'b0" *) (* C_PROBE_OUT148_WIDTH = "1" *)
(* C_PROBE_OUT149_INIT_VAL = "1'b0" *) (* C_PROBE_OUT149_WIDTH = "1" *) (* C_PROBE_OUT14_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT14_WIDTH = "1" *) (* C_PROBE_OUT150_INIT_VAL = "1'b0" *) (* C_PROBE_OUT150_WIDTH = "1" *)
(* C_PROBE_OUT151_INIT_VAL = "1'b0" *) (* C_PROBE_OUT151_WIDTH = "1" *) (* C_PROBE_OUT152_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT152_WIDTH = "1" *) (* C_PROBE_OUT153_INIT_VAL = "1'b0" *) (* C_PROBE_OUT153_WIDTH = "1" *)
(* C_PROBE_OUT154_INIT_VAL = "1'b0" *) (* C_PROBE_OUT154_WIDTH = "1" *) (* C_PROBE_OUT155_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT155_WIDTH = "1" *) (* C_PROBE_OUT156_INIT_VAL = "1'b0" *) (* C_PROBE_OUT156_WIDTH = "1" *)
(* C_PROBE_OUT157_INIT_VAL = "1'b0" *) (* C_PROBE_OUT157_WIDTH = "1" *) (* C_PROBE_OUT158_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT158_WIDTH = "1" *) (* C_PROBE_OUT159_INIT_VAL = "1'b0" *) (* C_PROBE_OUT159_WIDTH = "1" *)
(* C_PROBE_OUT15_INIT_VAL = "1'b0" *) (* C_PROBE_OUT15_WIDTH = "1" *) (* C_PROBE_OUT160_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT160_WIDTH = "1" *) (* C_PROBE_OUT161_INIT_VAL = "1'b0" *) (* C_PROBE_OUT161_WIDTH = "1" *)
(* C_PROBE_OUT162_INIT_VAL = "1'b0" *) (* C_PROBE_OUT162_WIDTH = "1" *) (* C_PROBE_OUT163_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT163_WIDTH = "1" *) (* C_PROBE_OUT164_INIT_VAL = "1'b0" *) (* C_PROBE_OUT164_WIDTH = "1" *)
(* C_PROBE_OUT165_INIT_VAL = "1'b0" *) (* C_PROBE_OUT165_WIDTH = "1" *) (* C_PROBE_OUT166_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT166_WIDTH = "1" *) (* C_PROBE_OUT167_INIT_VAL = "1'b0" *) (* C_PROBE_OUT167_WIDTH = "1" *)
(* C_PROBE_OUT168_INIT_VAL = "1'b0" *) (* C_PROBE_OUT168_WIDTH = "1" *) (* C_PROBE_OUT169_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT169_WIDTH = "1" *) (* C_PROBE_OUT16_INIT_VAL = "1'b0" *) (* C_PROBE_OUT16_WIDTH = "1" *)
(* C_PROBE_OUT170_INIT_VAL = "1'b0" *) (* C_PROBE_OUT170_WIDTH = "1" *) (* C_PROBE_OUT171_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT171_WIDTH = "1" *) (* C_PROBE_OUT172_INIT_VAL = "1'b0" *) (* C_PROBE_OUT172_WIDTH = "1" *)
(* C_PROBE_OUT173_INIT_VAL = "1'b0" *) (* C_PROBE_OUT173_WIDTH = "1" *) (* C_PROBE_OUT174_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT174_WIDTH = "1" *) (* C_PROBE_OUT175_INIT_VAL = "1'b0" *) (* C_PROBE_OUT175_WIDTH = "1" *)
(* C_PROBE_OUT176_INIT_VAL = "1'b0" *) (* C_PROBE_OUT176_WIDTH = "1" *) (* C_PROBE_OUT177_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT177_WIDTH = "1" *) (* C_PROBE_OUT178_INIT_VAL = "1'b0" *) (* C_PROBE_OUT178_WIDTH = "1" *)
(* C_PROBE_OUT179_INIT_VAL = "1'b0" *) (* C_PROBE_OUT179_WIDTH = "1" *) (* C_PROBE_OUT17_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT17_WIDTH = "1" *) (* C_PROBE_OUT180_INIT_VAL = "1'b0" *) (* C_PROBE_OUT180_WIDTH = "1" *)
(* C_PROBE_OUT181_INIT_VAL = "1'b0" *) (* C_PROBE_OUT181_WIDTH = "1" *) (* C_PROBE_OUT182_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT182_WIDTH = "1" *) (* C_PROBE_OUT183_INIT_VAL = "1'b0" *) (* C_PROBE_OUT183_WIDTH = "1" *)
(* C_PROBE_OUT184_INIT_VAL = "1'b0" *) (* C_PROBE_OUT184_WIDTH = "1" *) (* C_PROBE_OUT185_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT185_WIDTH = "1" *) (* C_PROBE_OUT186_INIT_VAL = "1'b0" *) (* C_PROBE_OUT186_WIDTH = "1" *)
(* C_PROBE_OUT187_INIT_VAL = "1'b0" *) (* C_PROBE_OUT187_WIDTH = "1" *) (* C_PROBE_OUT188_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT188_WIDTH = "1" *) (* C_PROBE_OUT189_INIT_VAL = "1'b0" *) (* C_PROBE_OUT189_WIDTH = "1" *)
(* C_PROBE_OUT18_INIT_VAL = "1'b0" *) (* C_PROBE_OUT18_WIDTH = "1" *) (* C_PROBE_OUT190_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT190_WIDTH = "1" *) (* C_PROBE_OUT191_INIT_VAL = "1'b0" *) (* C_PROBE_OUT191_WIDTH = "1" *)
(* C_PROBE_OUT192_INIT_VAL = "1'b0" *) (* C_PROBE_OUT192_WIDTH = "1" *) (* C_PROBE_OUT193_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT193_WIDTH = "1" *) (* C_PROBE_OUT194_INIT_VAL = "1'b0" *) (* C_PROBE_OUT194_WIDTH = "1" *)
(* C_PROBE_OUT195_INIT_VAL = "1'b0" *) (* C_PROBE_OUT195_WIDTH = "1" *) (* C_PROBE_OUT196_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT196_WIDTH = "1" *) (* C_PROBE_OUT197_INIT_VAL = "1'b0" *) (* C_PROBE_OUT197_WIDTH = "1" *)
(* C_PROBE_OUT198_INIT_VAL = "1'b0" *) (* C_PROBE_OUT198_WIDTH = "1" *) (* C_PROBE_OUT199_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT199_WIDTH = "1" *) (* C_PROBE_OUT19_INIT_VAL = "1'b0" *) (* C_PROBE_OUT19_WIDTH = "1" *)
(* C_PROBE_OUT1_INIT_VAL = "1'b0" *) (* C_PROBE_OUT1_WIDTH = "1" *) (* C_PROBE_OUT200_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT200_WIDTH = "1" *) (* C_PROBE_OUT201_INIT_VAL = "1'b0" *) (* C_PROBE_OUT201_WIDTH = "1" *)
(* C_PROBE_OUT202_INIT_VAL = "1'b0" *) (* C_PROBE_OUT202_WIDTH = "1" *) (* C_PROBE_OUT203_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT203_WIDTH = "1" *) (* C_PROBE_OUT204_INIT_VAL = "1'b0" *) (* C_PROBE_OUT204_WIDTH = "1" *)
(* C_PROBE_OUT205_INIT_VAL = "1'b0" *) (* C_PROBE_OUT205_WIDTH = "1" *) (* C_PROBE_OUT206_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT206_WIDTH = "1" *) (* C_PROBE_OUT207_INIT_VAL = "1'b0" *) (* C_PROBE_OUT207_WIDTH = "1" *)
(* C_PROBE_OUT208_INIT_VAL = "1'b0" *) (* C_PROBE_OUT208_WIDTH = "1" *) (* C_PROBE_OUT209_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT209_WIDTH = "1" *) (* C_PROBE_OUT20_INIT_VAL = "1'b0" *) (* C_PROBE_OUT20_WIDTH = "1" *)
(* C_PROBE_OUT210_INIT_VAL = "1'b0" *) (* C_PROBE_OUT210_WIDTH = "1" *) (* C_PROBE_OUT211_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT211_WIDTH = "1" *) (* C_PROBE_OUT212_INIT_VAL = "1'b0" *) (* C_PROBE_OUT212_WIDTH = "1" *)
(* C_PROBE_OUT213_INIT_VAL = "1'b0" *) (* C_PROBE_OUT213_WIDTH = "1" *) (* C_PROBE_OUT214_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT214_WIDTH = "1" *) (* C_PROBE_OUT215_INIT_VAL = "1'b0" *) (* C_PROBE_OUT215_WIDTH = "1" *)
(* C_PROBE_OUT216_INIT_VAL = "1'b0" *) (* C_PROBE_OUT216_WIDTH = "1" *) (* C_PROBE_OUT217_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT217_WIDTH = "1" *) (* C_PROBE_OUT218_INIT_VAL = "1'b0" *) (* C_PROBE_OUT218_WIDTH = "1" *)
(* C_PROBE_OUT219_INIT_VAL = "1'b0" *) (* C_PROBE_OUT219_WIDTH = "1" *) (* C_PROBE_OUT21_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT21_WIDTH = "1" *) (* C_PROBE_OUT220_INIT_VAL = "1'b0" *) (* C_PROBE_OUT220_WIDTH = "1" *)
(* C_PROBE_OUT221_INIT_VAL = "1'b0" *) (* C_PROBE_OUT221_WIDTH = "1" *) (* C_PROBE_OUT222_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT222_WIDTH = "1" *) (* C_PROBE_OUT223_INIT_VAL = "1'b0" *) (* C_PROBE_OUT223_WIDTH = "1" *)
(* C_PROBE_OUT224_INIT_VAL = "1'b0" *) (* C_PROBE_OUT224_WIDTH = "1" *) (* C_PROBE_OUT225_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT225_WIDTH = "1" *) (* C_PROBE_OUT226_INIT_VAL = "1'b0" *) (* C_PROBE_OUT226_WIDTH = "1" *)
(* C_PROBE_OUT227_INIT_VAL = "1'b0" *) (* C_PROBE_OUT227_WIDTH = "1" *) (* C_PROBE_OUT228_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT228_WIDTH = "1" *) (* C_PROBE_OUT229_INIT_VAL = "1'b0" *) (* C_PROBE_OUT229_WIDTH = "1" *)
(* C_PROBE_OUT22_INIT_VAL = "1'b0" *) (* C_PROBE_OUT22_WIDTH = "1" *) (* C_PROBE_OUT230_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT230_WIDTH = "1" *) (* C_PROBE_OUT231_INIT_VAL = "1'b0" *) (* C_PROBE_OUT231_WIDTH = "1" *)
(* C_PROBE_OUT232_INIT_VAL = "1'b0" *) (* C_PROBE_OUT232_WIDTH = "1" *) (* C_PROBE_OUT233_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT233_WIDTH = "1" *) (* C_PROBE_OUT234_INIT_VAL = "1'b0" *) (* C_PROBE_OUT234_WIDTH = "1" *)
(* C_PROBE_OUT235_INIT_VAL = "1'b0" *) (* C_PROBE_OUT235_WIDTH = "1" *) (* C_PROBE_OUT236_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT236_WIDTH = "1" *) (* C_PROBE_OUT237_INIT_VAL = "1'b0" *) (* C_PROBE_OUT237_WIDTH = "1" *)
(* C_PROBE_OUT238_INIT_VAL = "1'b0" *) (* C_PROBE_OUT238_WIDTH = "1" *) (* C_PROBE_OUT239_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT239_WIDTH = "1" *) (* C_PROBE_OUT23_INIT_VAL = "1'b0" *) (* C_PROBE_OUT23_WIDTH = "1" *)
(* C_PROBE_OUT240_INIT_VAL = "1'b0" *) (* C_PROBE_OUT240_WIDTH = "1" *) (* C_PROBE_OUT241_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT241_WIDTH = "1" *) (* C_PROBE_OUT242_INIT_VAL = "1'b0" *) (* C_PROBE_OUT242_WIDTH = "1" *)
(* C_PROBE_OUT243_INIT_VAL = "1'b0" *) (* C_PROBE_OUT243_WIDTH = "1" *) (* C_PROBE_OUT244_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT244_WIDTH = "1" *) (* C_PROBE_OUT245_INIT_VAL = "1'b0" *) (* C_PROBE_OUT245_WIDTH = "1" *)
(* C_PROBE_OUT246_INIT_VAL = "1'b0" *) (* C_PROBE_OUT246_WIDTH = "1" *) (* C_PROBE_OUT247_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT247_WIDTH = "1" *) (* C_PROBE_OUT248_INIT_VAL = "1'b0" *) (* C_PROBE_OUT248_WIDTH = "1" *)
(* C_PROBE_OUT249_INIT_VAL = "1'b0" *) (* C_PROBE_OUT249_WIDTH = "1" *) (* C_PROBE_OUT24_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT24_WIDTH = "1" *) (* C_PROBE_OUT250_INIT_VAL = "1'b0" *) (* C_PROBE_OUT250_WIDTH = "1" *)
(* C_PROBE_OUT251_INIT_VAL = "1'b0" *) (* C_PROBE_OUT251_WIDTH = "1" *) (* C_PROBE_OUT252_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT252_WIDTH = "1" *) (* C_PROBE_OUT253_INIT_VAL = "1'b0" *) (* C_PROBE_OUT253_WIDTH = "1" *)
(* C_PROBE_OUT254_INIT_VAL = "1'b0" *) (* C_PROBE_OUT254_WIDTH = "1" *) (* C_PROBE_OUT255_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT255_WIDTH = "1" *) (* C_PROBE_OUT25_INIT_VAL = "1'b0" *) (* C_PROBE_OUT25_WIDTH = "1" *)
(* C_PROBE_OUT26_INIT_VAL = "1'b0" *) (* C_PROBE_OUT26_WIDTH = "1" *) (* C_PROBE_OUT27_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT27_WIDTH = "1" *) (* C_PROBE_OUT28_INIT_VAL = "1'b0" *) (* C_PROBE_OUT28_WIDTH = "1" *)
(* C_PROBE_OUT29_INIT_VAL = "1'b0" *) (* C_PROBE_OUT29_WIDTH = "1" *) (* C_PROBE_OUT2_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT2_WIDTH = "1" *) (* C_PROBE_OUT30_INIT_VAL = "1'b0" *) (* C_PROBE_OUT30_WIDTH = "1" *)
(* C_PROBE_OUT31_INIT_VAL = "1'b0" *) (* C_PROBE_OUT31_WIDTH = "1" *) (* C_PROBE_OUT32_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT32_WIDTH = "1" *) (* C_PROBE_OUT33_INIT_VAL = "1'b0" *) (* C_PROBE_OUT33_WIDTH = "1" *)
(* C_PROBE_OUT34_INIT_VAL = "1'b0" *) (* C_PROBE_OUT34_WIDTH = "1" *) (* C_PROBE_OUT35_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT35_WIDTH = "1" *) (* C_PROBE_OUT36_INIT_VAL = "1'b0" *) (* C_PROBE_OUT36_WIDTH = "1" *)
(* C_PROBE_OUT37_INIT_VAL = "1'b0" *) (* C_PROBE_OUT37_WIDTH = "1" *) (* C_PROBE_OUT38_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT38_WIDTH = "1" *) (* C_PROBE_OUT39_INIT_VAL = "1'b0" *) (* C_PROBE_OUT39_WIDTH = "1" *)
(* C_PROBE_OUT3_INIT_VAL = "1'b0" *) (* C_PROBE_OUT3_WIDTH = "1" *) (* C_PROBE_OUT40_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT40_WIDTH = "1" *) (* C_PROBE_OUT41_INIT_VAL = "1'b0" *) (* C_PROBE_OUT41_WIDTH = "1" *)
(* C_PROBE_OUT42_INIT_VAL = "1'b0" *) (* C_PROBE_OUT42_WIDTH = "1" *) (* C_PROBE_OUT43_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT43_WIDTH = "1" *) (* C_PROBE_OUT44_INIT_VAL = "1'b0" *) (* C_PROBE_OUT44_WIDTH = "1" *)
(* C_PROBE_OUT45_INIT_VAL = "1'b0" *) (* C_PROBE_OUT45_WIDTH = "1" *) (* C_PROBE_OUT46_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT46_WIDTH = "1" *) (* C_PROBE_OUT47_INIT_VAL = "1'b0" *) (* C_PROBE_OUT47_WIDTH = "1" *)
(* C_PROBE_OUT48_INIT_VAL = "1'b0" *) (* C_PROBE_OUT48_WIDTH = "1" *) (* C_PROBE_OUT49_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT49_WIDTH = "1" *) (* C_PROBE_OUT4_INIT_VAL = "1'b0" *) (* C_PROBE_OUT4_WIDTH = "1" *)
(* C_PROBE_OUT50_INIT_VAL = "1'b0" *) (* C_PROBE_OUT50_WIDTH = "1" *) (* C_PROBE_OUT51_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT51_WIDTH = "1" *) (* C_PROBE_OUT52_INIT_VAL = "1'b0" *) (* C_PROBE_OUT52_WIDTH = "1" *)
(* C_PROBE_OUT53_INIT_VAL = "1'b0" *) (* C_PROBE_OUT53_WIDTH = "1" *) (* C_PROBE_OUT54_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT54_WIDTH = "1" *) (* C_PROBE_OUT55_INIT_VAL = "1'b0" *) (* C_PROBE_OUT55_WIDTH = "1" *)
(* C_PROBE_OUT56_INIT_VAL = "1'b0" *) (* C_PROBE_OUT56_WIDTH = "1" *) (* C_PROBE_OUT57_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT57_WIDTH = "1" *) (* C_PROBE_OUT58_INIT_VAL = "1'b0" *) (* C_PROBE_OUT58_WIDTH = "1" *)
(* C_PROBE_OUT59_INIT_VAL = "1'b0" *) (* C_PROBE_OUT59_WIDTH = "1" *) (* C_PROBE_OUT5_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT5_WIDTH = "1" *) (* C_PROBE_OUT60_INIT_VAL = "1'b0" *) (* C_PROBE_OUT60_WIDTH = "1" *)
(* C_PROBE_OUT61_INIT_VAL = "1'b0" *) (* C_PROBE_OUT61_WIDTH = "1" *) (* C_PROBE_OUT62_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT62_WIDTH = "1" *) (* C_PROBE_OUT63_INIT_VAL = "1'b0" *) (* C_PROBE_OUT63_WIDTH = "1" *)
(* C_PROBE_OUT64_INIT_VAL = "1'b0" *) (* C_PROBE_OUT64_WIDTH = "1" *) (* C_PROBE_OUT65_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT65_WIDTH = "1" *) (* C_PROBE_OUT66_INIT_VAL = "1'b0" *) (* C_PROBE_OUT66_WIDTH = "1" *)
(* C_PROBE_OUT67_INIT_VAL = "1'b0" *) (* C_PROBE_OUT67_WIDTH = "1" *) (* C_PROBE_OUT68_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT68_WIDTH = "1" *) (* C_PROBE_OUT69_INIT_VAL = "1'b0" *) (* C_PROBE_OUT69_WIDTH = "1" *)
(* C_PROBE_OUT6_INIT_VAL = "1'b0" *) (* C_PROBE_OUT6_WIDTH = "1" *) (* C_PROBE_OUT70_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT70_WIDTH = "1" *) (* C_PROBE_OUT71_INIT_VAL = "1'b0" *) (* C_PROBE_OUT71_WIDTH = "1" *)
(* C_PROBE_OUT72_INIT_VAL = "1'b0" *) (* C_PROBE_OUT72_WIDTH = "1" *) (* C_PROBE_OUT73_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT73_WIDTH = "1" *) (* C_PROBE_OUT74_INIT_VAL = "1'b0" *) (* C_PROBE_OUT74_WIDTH = "1" *)
(* C_PROBE_OUT75_INIT_VAL = "1'b0" *) (* C_PROBE_OUT75_WIDTH = "1" *) (* C_PROBE_OUT76_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT76_WIDTH = "1" *) (* C_PROBE_OUT77_INIT_VAL = "1'b0" *) (* C_PROBE_OUT77_WIDTH = "1" *)
(* C_PROBE_OUT78_INIT_VAL = "1'b0" *) (* C_PROBE_OUT78_WIDTH = "1" *) (* C_PROBE_OUT79_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT79_WIDTH = "1" *) (* C_PROBE_OUT7_INIT_VAL = "1'b0" *) (* C_PROBE_OUT7_WIDTH = "1" *)
(* C_PROBE_OUT80_INIT_VAL = "1'b0" *) (* C_PROBE_OUT80_WIDTH = "1" *) (* C_PROBE_OUT81_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT81_WIDTH = "1" *) (* C_PROBE_OUT82_INIT_VAL = "1'b0" *) (* C_PROBE_OUT82_WIDTH = "1" *)
(* C_PROBE_OUT83_INIT_VAL = "1'b0" *) (* C_PROBE_OUT83_WIDTH = "1" *) (* C_PROBE_OUT84_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT84_WIDTH = "1" *) (* C_PROBE_OUT85_INIT_VAL = "1'b0" *) (* C_PROBE_OUT85_WIDTH = "1" *)
(* C_PROBE_OUT86_INIT_VAL = "1'b0" *) (* C_PROBE_OUT86_WIDTH = "1" *) (* C_PROBE_OUT87_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT87_WIDTH = "1" *) (* C_PROBE_OUT88_INIT_VAL = "1'b0" *) (* C_PROBE_OUT88_WIDTH = "1" *)
(* C_PROBE_OUT89_INIT_VAL = "1'b0" *) (* C_PROBE_OUT89_WIDTH = "1" *) (* C_PROBE_OUT8_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT8_WIDTH = "1" *) (* C_PROBE_OUT90_INIT_VAL = "1'b0" *) (* C_PROBE_OUT90_WIDTH = "1" *)
(* C_PROBE_OUT91_INIT_VAL = "1'b0" *) (* C_PROBE_OUT91_WIDTH = "1" *) (* C_PROBE_OUT92_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT92_WIDTH = "1" *) (* C_PROBE_OUT93_INIT_VAL = "1'b0" *) (* C_PROBE_OUT93_WIDTH = "1" *)
(* C_PROBE_OUT94_INIT_VAL = "1'b0" *) (* C_PROBE_OUT94_WIDTH = "1" *) (* C_PROBE_OUT95_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT95_WIDTH = "1" *) (* C_PROBE_OUT96_INIT_VAL = "1'b0" *) (* C_PROBE_OUT96_WIDTH = "1" *)
(* C_PROBE_OUT97_INIT_VAL = "1'b0" *) (* C_PROBE_OUT97_WIDTH = "1" *) (* C_PROBE_OUT98_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT98_WIDTH = "1" *) (* C_PROBE_OUT99_INIT_VAL = "1'b0" *) (* C_PROBE_OUT99_WIDTH = "1" *)
(* C_PROBE_OUT9_INIT_VAL = "1'b0" *) (* C_PROBE_OUT9_WIDTH = "1" *) (* C_USE_TEST_REG = "1" *)
(* C_XDEVICEFAMILY = "kintex7" *) (* C_XLNX_HW_PROBE_INFO = "DEFAULT" *) (* C_XSDB_SLAVE_TYPE = "33" *)
(* DowngradeIPIdentifiedWarnings = "yes" *) (* LC_HIGH_BIT_POS_PROBE_OUT0 = "16'b0000000000000000" *) (* LC_HIGH_BIT_POS_PROBE_OUT1 = "16'b0000000000000001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT10 = "16'b0000000000001010" *) (* LC_HIGH_BIT_POS_PROBE_OUT100 = "16'b0000000001100100" *) (* LC_HIGH_BIT_POS_PROBE_OUT101 = "16'b0000000001100101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT102 = "16'b0000000001100110" *) (* LC_HIGH_BIT_POS_PROBE_OUT103 = "16'b0000000001100111" *) (* LC_HIGH_BIT_POS_PROBE_OUT104 = "16'b0000000001101000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT105 = "16'b0000000001101001" *) (* LC_HIGH_BIT_POS_PROBE_OUT106 = "16'b0000000001101010" *) (* LC_HIGH_BIT_POS_PROBE_OUT107 = "16'b0000000001101011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT108 = "16'b0000000001101100" *) (* LC_HIGH_BIT_POS_PROBE_OUT109 = "16'b0000000001101101" *) (* LC_HIGH_BIT_POS_PROBE_OUT11 = "16'b0000000000001011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT110 = "16'b0000000001101110" *) (* LC_HIGH_BIT_POS_PROBE_OUT111 = "16'b0000000001101111" *) (* LC_HIGH_BIT_POS_PROBE_OUT112 = "16'b0000000001110000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT113 = "16'b0000000001110001" *) (* LC_HIGH_BIT_POS_PROBE_OUT114 = "16'b0000000001110010" *) (* LC_HIGH_BIT_POS_PROBE_OUT115 = "16'b0000000001110011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT116 = "16'b0000000001110100" *) (* LC_HIGH_BIT_POS_PROBE_OUT117 = "16'b0000000001110101" *) (* LC_HIGH_BIT_POS_PROBE_OUT118 = "16'b0000000001110110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT119 = "16'b0000000001110111" *) (* LC_HIGH_BIT_POS_PROBE_OUT12 = "16'b0000000000001100" *) (* LC_HIGH_BIT_POS_PROBE_OUT120 = "16'b0000000001111000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT121 = "16'b0000000001111001" *) (* LC_HIGH_BIT_POS_PROBE_OUT122 = "16'b0000000001111010" *) (* LC_HIGH_BIT_POS_PROBE_OUT123 = "16'b0000000001111011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT124 = "16'b0000000001111100" *) (* LC_HIGH_BIT_POS_PROBE_OUT125 = "16'b0000000001111101" *) (* LC_HIGH_BIT_POS_PROBE_OUT126 = "16'b0000000001111110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT127 = "16'b0000000001111111" *) (* LC_HIGH_BIT_POS_PROBE_OUT128 = "16'b0000000010000000" *) (* LC_HIGH_BIT_POS_PROBE_OUT129 = "16'b0000000010000001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT13 = "16'b0000000000001101" *) (* LC_HIGH_BIT_POS_PROBE_OUT130 = "16'b0000000010000010" *) (* LC_HIGH_BIT_POS_PROBE_OUT131 = "16'b0000000010000011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT132 = "16'b0000000010000100" *) (* LC_HIGH_BIT_POS_PROBE_OUT133 = "16'b0000000010000101" *) (* LC_HIGH_BIT_POS_PROBE_OUT134 = "16'b0000000010000110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT135 = "16'b0000000010000111" *) (* LC_HIGH_BIT_POS_PROBE_OUT136 = "16'b0000000010001000" *) (* LC_HIGH_BIT_POS_PROBE_OUT137 = "16'b0000000010001001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT138 = "16'b0000000010001010" *) (* LC_HIGH_BIT_POS_PROBE_OUT139 = "16'b0000000010001011" *) (* LC_HIGH_BIT_POS_PROBE_OUT14 = "16'b0000000000001110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT140 = "16'b0000000010001100" *) (* LC_HIGH_BIT_POS_PROBE_OUT141 = "16'b0000000010001101" *) (* LC_HIGH_BIT_POS_PROBE_OUT142 = "16'b0000000010001110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT143 = "16'b0000000010001111" *) (* LC_HIGH_BIT_POS_PROBE_OUT144 = "16'b0000000010010000" *) (* LC_HIGH_BIT_POS_PROBE_OUT145 = "16'b0000000010010001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT146 = "16'b0000000010010010" *) (* LC_HIGH_BIT_POS_PROBE_OUT147 = "16'b0000000010010011" *) (* LC_HIGH_BIT_POS_PROBE_OUT148 = "16'b0000000010010100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT149 = "16'b0000000010010101" *) (* LC_HIGH_BIT_POS_PROBE_OUT15 = "16'b0000000000001111" *) (* LC_HIGH_BIT_POS_PROBE_OUT150 = "16'b0000000010010110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT151 = "16'b0000000010010111" *) (* LC_HIGH_BIT_POS_PROBE_OUT152 = "16'b0000000010011000" *) (* LC_HIGH_BIT_POS_PROBE_OUT153 = "16'b0000000010011001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT154 = "16'b0000000010011010" *) (* LC_HIGH_BIT_POS_PROBE_OUT155 = "16'b0000000010011011" *) (* LC_HIGH_BIT_POS_PROBE_OUT156 = "16'b0000000010011100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT157 = "16'b0000000010011101" *) (* LC_HIGH_BIT_POS_PROBE_OUT158 = "16'b0000000010011110" *) (* LC_HIGH_BIT_POS_PROBE_OUT159 = "16'b0000000010011111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT16 = "16'b0000000000010000" *) (* LC_HIGH_BIT_POS_PROBE_OUT160 = "16'b0000000010100000" *) (* LC_HIGH_BIT_POS_PROBE_OUT161 = "16'b0000000010100001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT162 = "16'b0000000010100010" *) (* LC_HIGH_BIT_POS_PROBE_OUT163 = "16'b0000000010100011" *) (* LC_HIGH_BIT_POS_PROBE_OUT164 = "16'b0000000010100100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT165 = "16'b0000000010100101" *) (* LC_HIGH_BIT_POS_PROBE_OUT166 = "16'b0000000010100110" *) (* LC_HIGH_BIT_POS_PROBE_OUT167 = "16'b0000000010100111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT168 = "16'b0000000010101000" *) (* LC_HIGH_BIT_POS_PROBE_OUT169 = "16'b0000000010101001" *) (* LC_HIGH_BIT_POS_PROBE_OUT17 = "16'b0000000000010001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT170 = "16'b0000000010101010" *) (* LC_HIGH_BIT_POS_PROBE_OUT171 = "16'b0000000010101011" *) (* LC_HIGH_BIT_POS_PROBE_OUT172 = "16'b0000000010101100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT173 = "16'b0000000010101101" *) (* LC_HIGH_BIT_POS_PROBE_OUT174 = "16'b0000000010101110" *) (* LC_HIGH_BIT_POS_PROBE_OUT175 = "16'b0000000010101111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT176 = "16'b0000000010110000" *) (* LC_HIGH_BIT_POS_PROBE_OUT177 = "16'b0000000010110001" *) (* LC_HIGH_BIT_POS_PROBE_OUT178 = "16'b0000000010110010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT179 = "16'b0000000010110011" *) (* LC_HIGH_BIT_POS_PROBE_OUT18 = "16'b0000000000010010" *) (* LC_HIGH_BIT_POS_PROBE_OUT180 = "16'b0000000010110100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT181 = "16'b0000000010110101" *) (* LC_HIGH_BIT_POS_PROBE_OUT182 = "16'b0000000010110110" *) (* LC_HIGH_BIT_POS_PROBE_OUT183 = "16'b0000000010110111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT184 = "16'b0000000010111000" *) (* LC_HIGH_BIT_POS_PROBE_OUT185 = "16'b0000000010111001" *) (* LC_HIGH_BIT_POS_PROBE_OUT186 = "16'b0000000010111010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT187 = "16'b0000000010111011" *) (* LC_HIGH_BIT_POS_PROBE_OUT188 = "16'b0000000010111100" *) (* LC_HIGH_BIT_POS_PROBE_OUT189 = "16'b0000000010111101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT19 = "16'b0000000000010011" *) (* LC_HIGH_BIT_POS_PROBE_OUT190 = "16'b0000000010111110" *) (* LC_HIGH_BIT_POS_PROBE_OUT191 = "16'b0000000010111111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT192 = "16'b0000000011000000" *) (* LC_HIGH_BIT_POS_PROBE_OUT193 = "16'b0000000011000001" *) (* LC_HIGH_BIT_POS_PROBE_OUT194 = "16'b0000000011000010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT195 = "16'b0000000011000011" *) (* LC_HIGH_BIT_POS_PROBE_OUT196 = "16'b0000000011000100" *) (* LC_HIGH_BIT_POS_PROBE_OUT197 = "16'b0000000011000101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT198 = "16'b0000000011000110" *) (* LC_HIGH_BIT_POS_PROBE_OUT199 = "16'b0000000011000111" *) (* LC_HIGH_BIT_POS_PROBE_OUT2 = "16'b0000000000000010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT20 = "16'b0000000000010100" *) (* LC_HIGH_BIT_POS_PROBE_OUT200 = "16'b0000000011001000" *) (* LC_HIGH_BIT_POS_PROBE_OUT201 = "16'b0000000011001001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT202 = "16'b0000000011001010" *) (* LC_HIGH_BIT_POS_PROBE_OUT203 = "16'b0000000011001011" *) (* LC_HIGH_BIT_POS_PROBE_OUT204 = "16'b0000000011001100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT205 = "16'b0000000011001101" *) (* LC_HIGH_BIT_POS_PROBE_OUT206 = "16'b0000000011001110" *) (* LC_HIGH_BIT_POS_PROBE_OUT207 = "16'b0000000011001111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT208 = "16'b0000000011010000" *) (* LC_HIGH_BIT_POS_PROBE_OUT209 = "16'b0000000011010001" *) (* LC_HIGH_BIT_POS_PROBE_OUT21 = "16'b0000000000010101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT210 = "16'b0000000011010010" *) (* LC_HIGH_BIT_POS_PROBE_OUT211 = "16'b0000000011010011" *) (* LC_HIGH_BIT_POS_PROBE_OUT212 = "16'b0000000011010100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT213 = "16'b0000000011010101" *) (* LC_HIGH_BIT_POS_PROBE_OUT214 = "16'b0000000011010110" *) (* LC_HIGH_BIT_POS_PROBE_OUT215 = "16'b0000000011010111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT216 = "16'b0000000011011000" *) (* LC_HIGH_BIT_POS_PROBE_OUT217 = "16'b0000000011011001" *) (* LC_HIGH_BIT_POS_PROBE_OUT218 = "16'b0000000011011010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT219 = "16'b0000000011011011" *) (* LC_HIGH_BIT_POS_PROBE_OUT22 = "16'b0000000000010110" *) (* LC_HIGH_BIT_POS_PROBE_OUT220 = "16'b0000000011011100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT221 = "16'b0000000011011101" *) (* LC_HIGH_BIT_POS_PROBE_OUT222 = "16'b0000000011011110" *) (* LC_HIGH_BIT_POS_PROBE_OUT223 = "16'b0000000011011111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT224 = "16'b0000000011100000" *) (* LC_HIGH_BIT_POS_PROBE_OUT225 = "16'b0000000011100001" *) (* LC_HIGH_BIT_POS_PROBE_OUT226 = "16'b0000000011100010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT227 = "16'b0000000011100011" *) (* LC_HIGH_BIT_POS_PROBE_OUT228 = "16'b0000000011100100" *) (* LC_HIGH_BIT_POS_PROBE_OUT229 = "16'b0000000011100101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT23 = "16'b0000000000010111" *) (* LC_HIGH_BIT_POS_PROBE_OUT230 = "16'b0000000011100110" *) (* LC_HIGH_BIT_POS_PROBE_OUT231 = "16'b0000000011100111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT232 = "16'b0000000011101000" *) (* LC_HIGH_BIT_POS_PROBE_OUT233 = "16'b0000000011101001" *) (* LC_HIGH_BIT_POS_PROBE_OUT234 = "16'b0000000011101010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT235 = "16'b0000000011101011" *) (* LC_HIGH_BIT_POS_PROBE_OUT236 = "16'b0000000011101100" *) (* LC_HIGH_BIT_POS_PROBE_OUT237 = "16'b0000000011101101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT238 = "16'b0000000011101110" *) (* LC_HIGH_BIT_POS_PROBE_OUT239 = "16'b0000000011101111" *) (* LC_HIGH_BIT_POS_PROBE_OUT24 = "16'b0000000000011000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT240 = "16'b0000000011110000" *) (* LC_HIGH_BIT_POS_PROBE_OUT241 = "16'b0000000011110001" *) (* LC_HIGH_BIT_POS_PROBE_OUT242 = "16'b0000000011110010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT243 = "16'b0000000011110011" *) (* LC_HIGH_BIT_POS_PROBE_OUT244 = "16'b0000000011110100" *) (* LC_HIGH_BIT_POS_PROBE_OUT245 = "16'b0000000011110101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT246 = "16'b0000000011110110" *) (* LC_HIGH_BIT_POS_PROBE_OUT247 = "16'b0000000011110111" *) (* LC_HIGH_BIT_POS_PROBE_OUT248 = "16'b0000000011111000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT249 = "16'b0000000011111001" *) (* LC_HIGH_BIT_POS_PROBE_OUT25 = "16'b0000000000011001" *) (* LC_HIGH_BIT_POS_PROBE_OUT250 = "16'b0000000011111010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT251 = "16'b0000000011111011" *) (* LC_HIGH_BIT_POS_PROBE_OUT252 = "16'b0000000011111100" *) (* LC_HIGH_BIT_POS_PROBE_OUT253 = "16'b0000000011111101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT254 = "16'b0000000011111110" *) (* LC_HIGH_BIT_POS_PROBE_OUT255 = "16'b0000000011111111" *) (* LC_HIGH_BIT_POS_PROBE_OUT26 = "16'b0000000000011010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT27 = "16'b0000000000011011" *) (* LC_HIGH_BIT_POS_PROBE_OUT28 = "16'b0000000000011100" *) (* LC_HIGH_BIT_POS_PROBE_OUT29 = "16'b0000000000011101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT3 = "16'b0000000000000011" *) (* LC_HIGH_BIT_POS_PROBE_OUT30 = "16'b0000000000011110" *) (* LC_HIGH_BIT_POS_PROBE_OUT31 = "16'b0000000000011111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT32 = "16'b0000000000100000" *) (* LC_HIGH_BIT_POS_PROBE_OUT33 = "16'b0000000000100001" *) (* LC_HIGH_BIT_POS_PROBE_OUT34 = "16'b0000000000100010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT35 = "16'b0000000000100011" *) (* LC_HIGH_BIT_POS_PROBE_OUT36 = "16'b0000000000100100" *) (* LC_HIGH_BIT_POS_PROBE_OUT37 = "16'b0000000000100101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT38 = "16'b0000000000100110" *) (* LC_HIGH_BIT_POS_PROBE_OUT39 = "16'b0000000000100111" *) (* LC_HIGH_BIT_POS_PROBE_OUT4 = "16'b0000000000000100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT40 = "16'b0000000000101000" *) (* LC_HIGH_BIT_POS_PROBE_OUT41 = "16'b0000000000101001" *) (* LC_HIGH_BIT_POS_PROBE_OUT42 = "16'b0000000000101010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT43 = "16'b0000000000101011" *) (* LC_HIGH_BIT_POS_PROBE_OUT44 = "16'b0000000000101100" *) (* LC_HIGH_BIT_POS_PROBE_OUT45 = "16'b0000000000101101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT46 = "16'b0000000000101110" *) (* LC_HIGH_BIT_POS_PROBE_OUT47 = "16'b0000000000101111" *) (* LC_HIGH_BIT_POS_PROBE_OUT48 = "16'b0000000000110000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT49 = "16'b0000000000110001" *) (* LC_HIGH_BIT_POS_PROBE_OUT5 = "16'b0000000000000101" *) (* LC_HIGH_BIT_POS_PROBE_OUT50 = "16'b0000000000110010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT51 = "16'b0000000000110011" *) (* LC_HIGH_BIT_POS_PROBE_OUT52 = "16'b0000000000110100" *) (* LC_HIGH_BIT_POS_PROBE_OUT53 = "16'b0000000000110101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT54 = "16'b0000000000110110" *) (* LC_HIGH_BIT_POS_PROBE_OUT55 = "16'b0000000000110111" *) (* LC_HIGH_BIT_POS_PROBE_OUT56 = "16'b0000000000111000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT57 = "16'b0000000000111001" *) (* LC_HIGH_BIT_POS_PROBE_OUT58 = "16'b0000000000111010" *) (* LC_HIGH_BIT_POS_PROBE_OUT59 = "16'b0000000000111011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT6 = "16'b0000000000000110" *) (* LC_HIGH_BIT_POS_PROBE_OUT60 = "16'b0000000000111100" *) (* LC_HIGH_BIT_POS_PROBE_OUT61 = "16'b0000000000111101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT62 = "16'b0000000000111110" *) (* LC_HIGH_BIT_POS_PROBE_OUT63 = "16'b0000000000111111" *) (* LC_HIGH_BIT_POS_PROBE_OUT64 = "16'b0000000001000000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT65 = "16'b0000000001000001" *) (* LC_HIGH_BIT_POS_PROBE_OUT66 = "16'b0000000001000010" *) (* LC_HIGH_BIT_POS_PROBE_OUT67 = "16'b0000000001000011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT68 = "16'b0000000001000100" *) (* LC_HIGH_BIT_POS_PROBE_OUT69 = "16'b0000000001000101" *) (* LC_HIGH_BIT_POS_PROBE_OUT7 = "16'b0000000000000111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT70 = "16'b0000000001000110" *) (* LC_HIGH_BIT_POS_PROBE_OUT71 = "16'b0000000001000111" *) (* LC_HIGH_BIT_POS_PROBE_OUT72 = "16'b0000000001001000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT73 = "16'b0000000001001001" *) (* LC_HIGH_BIT_POS_PROBE_OUT74 = "16'b0000000001001010" *) (* LC_HIGH_BIT_POS_PROBE_OUT75 = "16'b0000000001001011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT76 = "16'b0000000001001100" *) (* LC_HIGH_BIT_POS_PROBE_OUT77 = "16'b0000000001001101" *) (* LC_HIGH_BIT_POS_PROBE_OUT78 = "16'b0000000001001110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT79 = "16'b0000000001001111" *) (* LC_HIGH_BIT_POS_PROBE_OUT8 = "16'b0000000000001000" *) (* LC_HIGH_BIT_POS_PROBE_OUT80 = "16'b0000000001010000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT81 = "16'b0000000001010001" *) (* LC_HIGH_BIT_POS_PROBE_OUT82 = "16'b0000000001010010" *) (* LC_HIGH_BIT_POS_PROBE_OUT83 = "16'b0000000001010011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT84 = "16'b0000000001010100" *) (* LC_HIGH_BIT_POS_PROBE_OUT85 = "16'b0000000001010101" *) (* LC_HIGH_BIT_POS_PROBE_OUT86 = "16'b0000000001010110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT87 = "16'b0000000001010111" *) (* LC_HIGH_BIT_POS_PROBE_OUT88 = "16'b0000000001011000" *) (* LC_HIGH_BIT_POS_PROBE_OUT89 = "16'b0000000001011001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT9 = "16'b0000000000001001" *) (* LC_HIGH_BIT_POS_PROBE_OUT90 = "16'b0000000001011010" *) (* LC_HIGH_BIT_POS_PROBE_OUT91 = "16'b0000000001011011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT92 = "16'b0000000001011100" *) (* LC_HIGH_BIT_POS_PROBE_OUT93 = "16'b0000000001011101" *) (* LC_HIGH_BIT_POS_PROBE_OUT94 = "16'b0000000001011110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT95 = "16'b0000000001011111" *) (* LC_HIGH_BIT_POS_PROBE_OUT96 = "16'b0000000001100000" *) (* LC_HIGH_BIT_POS_PROBE_OUT97 = "16'b0000000001100001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT98 = "16'b0000000001100010" *) (* LC_HIGH_BIT_POS_PROBE_OUT99 = "16'b0000000001100011" *) (* LC_LOW_BIT_POS_PROBE_OUT0 = "16'b0000000000000000" *)
(* LC_LOW_BIT_POS_PROBE_OUT1 = "16'b0000000000000001" *) (* LC_LOW_BIT_POS_PROBE_OUT10 = "16'b0000000000001010" *) (* LC_LOW_BIT_POS_PROBE_OUT100 = "16'b0000000001100100" *)
(* LC_LOW_BIT_POS_PROBE_OUT101 = "16'b0000000001100101" *) (* LC_LOW_BIT_POS_PROBE_OUT102 = "16'b0000000001100110" *) (* LC_LOW_BIT_POS_PROBE_OUT103 = "16'b0000000001100111" *)
(* LC_LOW_BIT_POS_PROBE_OUT104 = "16'b0000000001101000" *) (* LC_LOW_BIT_POS_PROBE_OUT105 = "16'b0000000001101001" *) (* LC_LOW_BIT_POS_PROBE_OUT106 = "16'b0000000001101010" *)
(* LC_LOW_BIT_POS_PROBE_OUT107 = "16'b0000000001101011" *) (* LC_LOW_BIT_POS_PROBE_OUT108 = "16'b0000000001101100" *) (* LC_LOW_BIT_POS_PROBE_OUT109 = "16'b0000000001101101" *)
(* LC_LOW_BIT_POS_PROBE_OUT11 = "16'b0000000000001011" *) (* LC_LOW_BIT_POS_PROBE_OUT110 = "16'b0000000001101110" *) (* LC_LOW_BIT_POS_PROBE_OUT111 = "16'b0000000001101111" *)
(* LC_LOW_BIT_POS_PROBE_OUT112 = "16'b0000000001110000" *) (* LC_LOW_BIT_POS_PROBE_OUT113 = "16'b0000000001110001" *) (* LC_LOW_BIT_POS_PROBE_OUT114 = "16'b0000000001110010" *)
(* LC_LOW_BIT_POS_PROBE_OUT115 = "16'b0000000001110011" *) (* LC_LOW_BIT_POS_PROBE_OUT116 = "16'b0000000001110100" *) (* LC_LOW_BIT_POS_PROBE_OUT117 = "16'b0000000001110101" *)
(* LC_LOW_BIT_POS_PROBE_OUT118 = "16'b0000000001110110" *) (* LC_LOW_BIT_POS_PROBE_OUT119 = "16'b0000000001110111" *) (* LC_LOW_BIT_POS_PROBE_OUT12 = "16'b0000000000001100" *)
(* LC_LOW_BIT_POS_PROBE_OUT120 = "16'b0000000001111000" *) (* LC_LOW_BIT_POS_PROBE_OUT121 = "16'b0000000001111001" *) (* LC_LOW_BIT_POS_PROBE_OUT122 = "16'b0000000001111010" *)
(* LC_LOW_BIT_POS_PROBE_OUT123 = "16'b0000000001111011" *) (* LC_LOW_BIT_POS_PROBE_OUT124 = "16'b0000000001111100" *) (* LC_LOW_BIT_POS_PROBE_OUT125 = "16'b0000000001111101" *)
(* LC_LOW_BIT_POS_PROBE_OUT126 = "16'b0000000001111110" *) (* LC_LOW_BIT_POS_PROBE_OUT127 = "16'b0000000001111111" *) (* LC_LOW_BIT_POS_PROBE_OUT128 = "16'b0000000010000000" *)
(* LC_LOW_BIT_POS_PROBE_OUT129 = "16'b0000000010000001" *) (* LC_LOW_BIT_POS_PROBE_OUT13 = "16'b0000000000001101" *) (* LC_LOW_BIT_POS_PROBE_OUT130 = "16'b0000000010000010" *)
(* LC_LOW_BIT_POS_PROBE_OUT131 = "16'b0000000010000011" *) (* LC_LOW_BIT_POS_PROBE_OUT132 = "16'b0000000010000100" *) (* LC_LOW_BIT_POS_PROBE_OUT133 = "16'b0000000010000101" *)
(* LC_LOW_BIT_POS_PROBE_OUT134 = "16'b0000000010000110" *) (* LC_LOW_BIT_POS_PROBE_OUT135 = "16'b0000000010000111" *) (* LC_LOW_BIT_POS_PROBE_OUT136 = "16'b0000000010001000" *)
(* LC_LOW_BIT_POS_PROBE_OUT137 = "16'b0000000010001001" *) (* LC_LOW_BIT_POS_PROBE_OUT138 = "16'b0000000010001010" *) (* LC_LOW_BIT_POS_PROBE_OUT139 = "16'b0000000010001011" *)
(* LC_LOW_BIT_POS_PROBE_OUT14 = "16'b0000000000001110" *) (* LC_LOW_BIT_POS_PROBE_OUT140 = "16'b0000000010001100" *) (* LC_LOW_BIT_POS_PROBE_OUT141 = "16'b0000000010001101" *)
(* LC_LOW_BIT_POS_PROBE_OUT142 = "16'b0000000010001110" *) (* LC_LOW_BIT_POS_PROBE_OUT143 = "16'b0000000010001111" *) (* LC_LOW_BIT_POS_PROBE_OUT144 = "16'b0000000010010000" *)
(* LC_LOW_BIT_POS_PROBE_OUT145 = "16'b0000000010010001" *) (* LC_LOW_BIT_POS_PROBE_OUT146 = "16'b0000000010010010" *) (* LC_LOW_BIT_POS_PROBE_OUT147 = "16'b0000000010010011" *)
(* LC_LOW_BIT_POS_PROBE_OUT148 = "16'b0000000010010100" *) (* LC_LOW_BIT_POS_PROBE_OUT149 = "16'b0000000010010101" *) (* LC_LOW_BIT_POS_PROBE_OUT15 = "16'b0000000000001111" *)
(* LC_LOW_BIT_POS_PROBE_OUT150 = "16'b0000000010010110" *) (* LC_LOW_BIT_POS_PROBE_OUT151 = "16'b0000000010010111" *) (* LC_LOW_BIT_POS_PROBE_OUT152 = "16'b0000000010011000" *)
(* LC_LOW_BIT_POS_PROBE_OUT153 = "16'b0000000010011001" *) (* LC_LOW_BIT_POS_PROBE_OUT154 = "16'b0000000010011010" *) (* LC_LOW_BIT_POS_PROBE_OUT155 = "16'b0000000010011011" *)
(* LC_LOW_BIT_POS_PROBE_OUT156 = "16'b0000000010011100" *) (* LC_LOW_BIT_POS_PROBE_OUT157 = "16'b0000000010011101" *) (* LC_LOW_BIT_POS_PROBE_OUT158 = "16'b0000000010011110" *)
(* LC_LOW_BIT_POS_PROBE_OUT159 = "16'b0000000010011111" *) (* LC_LOW_BIT_POS_PROBE_OUT16 = "16'b0000000000010000" *) (* LC_LOW_BIT_POS_PROBE_OUT160 = "16'b0000000010100000" *)
(* LC_LOW_BIT_POS_PROBE_OUT161 = "16'b0000000010100001" *) (* LC_LOW_BIT_POS_PROBE_OUT162 = "16'b0000000010100010" *) (* LC_LOW_BIT_POS_PROBE_OUT163 = "16'b0000000010100011" *)
(* LC_LOW_BIT_POS_PROBE_OUT164 = "16'b0000000010100100" *) (* LC_LOW_BIT_POS_PROBE_OUT165 = "16'b0000000010100101" *) (* LC_LOW_BIT_POS_PROBE_OUT166 = "16'b0000000010100110" *)
(* LC_LOW_BIT_POS_PROBE_OUT167 = "16'b0000000010100111" *) (* LC_LOW_BIT_POS_PROBE_OUT168 = "16'b0000000010101000" *) (* LC_LOW_BIT_POS_PROBE_OUT169 = "16'b0000000010101001" *)
(* LC_LOW_BIT_POS_PROBE_OUT17 = "16'b0000000000010001" *) (* LC_LOW_BIT_POS_PROBE_OUT170 = "16'b0000000010101010" *) (* LC_LOW_BIT_POS_PROBE_OUT171 = "16'b0000000010101011" *)
(* LC_LOW_BIT_POS_PROBE_OUT172 = "16'b0000000010101100" *) (* LC_LOW_BIT_POS_PROBE_OUT173 = "16'b0000000010101101" *) (* LC_LOW_BIT_POS_PROBE_OUT174 = "16'b0000000010101110" *)
(* LC_LOW_BIT_POS_PROBE_OUT175 = "16'b0000000010101111" *) (* LC_LOW_BIT_POS_PROBE_OUT176 = "16'b0000000010110000" *) (* LC_LOW_BIT_POS_PROBE_OUT177 = "16'b0000000010110001" *)
(* LC_LOW_BIT_POS_PROBE_OUT178 = "16'b0000000010110010" *) (* LC_LOW_BIT_POS_PROBE_OUT179 = "16'b0000000010110011" *) (* LC_LOW_BIT_POS_PROBE_OUT18 = "16'b0000000000010010" *)
(* LC_LOW_BIT_POS_PROBE_OUT180 = "16'b0000000010110100" *) (* LC_LOW_BIT_POS_PROBE_OUT181 = "16'b0000000010110101" *) (* LC_LOW_BIT_POS_PROBE_OUT182 = "16'b0000000010110110" *)
(* LC_LOW_BIT_POS_PROBE_OUT183 = "16'b0000000010110111" *) (* LC_LOW_BIT_POS_PROBE_OUT184 = "16'b0000000010111000" *) (* LC_LOW_BIT_POS_PROBE_OUT185 = "16'b0000000010111001" *)
(* LC_LOW_BIT_POS_PROBE_OUT186 = "16'b0000000010111010" *) (* LC_LOW_BIT_POS_PROBE_OUT187 = "16'b0000000010111011" *) (* LC_LOW_BIT_POS_PROBE_OUT188 = "16'b0000000010111100" *)
(* LC_LOW_BIT_POS_PROBE_OUT189 = "16'b0000000010111101" *) (* LC_LOW_BIT_POS_PROBE_OUT19 = "16'b0000000000010011" *) (* LC_LOW_BIT_POS_PROBE_OUT190 = "16'b0000000010111110" *)
(* LC_LOW_BIT_POS_PROBE_OUT191 = "16'b0000000010111111" *) (* LC_LOW_BIT_POS_PROBE_OUT192 = "16'b0000000011000000" *) (* LC_LOW_BIT_POS_PROBE_OUT193 = "16'b0000000011000001" *)
(* LC_LOW_BIT_POS_PROBE_OUT194 = "16'b0000000011000010" *) (* LC_LOW_BIT_POS_PROBE_OUT195 = "16'b0000000011000011" *) (* LC_LOW_BIT_POS_PROBE_OUT196 = "16'b0000000011000100" *)
(* LC_LOW_BIT_POS_PROBE_OUT197 = "16'b0000000011000101" *) (* LC_LOW_BIT_POS_PROBE_OUT198 = "16'b0000000011000110" *) (* LC_LOW_BIT_POS_PROBE_OUT199 = "16'b0000000011000111" *)
(* LC_LOW_BIT_POS_PROBE_OUT2 = "16'b0000000000000010" *) (* LC_LOW_BIT_POS_PROBE_OUT20 = "16'b0000000000010100" *) (* LC_LOW_BIT_POS_PROBE_OUT200 = "16'b0000000011001000" *)
(* LC_LOW_BIT_POS_PROBE_OUT201 = "16'b0000000011001001" *) (* LC_LOW_BIT_POS_PROBE_OUT202 = "16'b0000000011001010" *) (* LC_LOW_BIT_POS_PROBE_OUT203 = "16'b0000000011001011" *)
(* LC_LOW_BIT_POS_PROBE_OUT204 = "16'b0000000011001100" *) (* LC_LOW_BIT_POS_PROBE_OUT205 = "16'b0000000011001101" *) (* LC_LOW_BIT_POS_PROBE_OUT206 = "16'b0000000011001110" *)
(* LC_LOW_BIT_POS_PROBE_OUT207 = "16'b0000000011001111" *) (* LC_LOW_BIT_POS_PROBE_OUT208 = "16'b0000000011010000" *) (* LC_LOW_BIT_POS_PROBE_OUT209 = "16'b0000000011010001" *)
(* LC_LOW_BIT_POS_PROBE_OUT21 = "16'b0000000000010101" *) (* LC_LOW_BIT_POS_PROBE_OUT210 = "16'b0000000011010010" *) (* LC_LOW_BIT_POS_PROBE_OUT211 = "16'b0000000011010011" *)
(* LC_LOW_BIT_POS_PROBE_OUT212 = "16'b0000000011010100" *) (* LC_LOW_BIT_POS_PROBE_OUT213 = "16'b0000000011010101" *) (* LC_LOW_BIT_POS_PROBE_OUT214 = "16'b0000000011010110" *)
(* LC_LOW_BIT_POS_PROBE_OUT215 = "16'b0000000011010111" *) (* LC_LOW_BIT_POS_PROBE_OUT216 = "16'b0000000011011000" *) (* LC_LOW_BIT_POS_PROBE_OUT217 = "16'b0000000011011001" *)
(* LC_LOW_BIT_POS_PROBE_OUT218 = "16'b0000000011011010" *) (* LC_LOW_BIT_POS_PROBE_OUT219 = "16'b0000000011011011" *) (* LC_LOW_BIT_POS_PROBE_OUT22 = "16'b0000000000010110" *)
(* LC_LOW_BIT_POS_PROBE_OUT220 = "16'b0000000011011100" *) (* LC_LOW_BIT_POS_PROBE_OUT221 = "16'b0000000011011101" *) (* LC_LOW_BIT_POS_PROBE_OUT222 = "16'b0000000011011110" *)
(* LC_LOW_BIT_POS_PROBE_OUT223 = "16'b0000000011011111" *) (* LC_LOW_BIT_POS_PROBE_OUT224 = "16'b0000000011100000" *) (* LC_LOW_BIT_POS_PROBE_OUT225 = "16'b0000000011100001" *)
(* LC_LOW_BIT_POS_PROBE_OUT226 = "16'b0000000011100010" *) (* LC_LOW_BIT_POS_PROBE_OUT227 = "16'b0000000011100011" *) (* LC_LOW_BIT_POS_PROBE_OUT228 = "16'b0000000011100100" *)
(* LC_LOW_BIT_POS_PROBE_OUT229 = "16'b0000000011100101" *) (* LC_LOW_BIT_POS_PROBE_OUT23 = "16'b0000000000010111" *) (* LC_LOW_BIT_POS_PROBE_OUT230 = "16'b0000000011100110" *)
(* LC_LOW_BIT_POS_PROBE_OUT231 = "16'b0000000011100111" *) (* LC_LOW_BIT_POS_PROBE_OUT232 = "16'b0000000011101000" *) (* LC_LOW_BIT_POS_PROBE_OUT233 = "16'b0000000011101001" *)
(* LC_LOW_BIT_POS_PROBE_OUT234 = "16'b0000000011101010" *) (* LC_LOW_BIT_POS_PROBE_OUT235 = "16'b0000000011101011" *) (* LC_LOW_BIT_POS_PROBE_OUT236 = "16'b0000000011101100" *)
(* LC_LOW_BIT_POS_PROBE_OUT237 = "16'b0000000011101101" *) (* LC_LOW_BIT_POS_PROBE_OUT238 = "16'b0000000011101110" *) (* LC_LOW_BIT_POS_PROBE_OUT239 = "16'b0000000011101111" *)
(* LC_LOW_BIT_POS_PROBE_OUT24 = "16'b0000000000011000" *) (* LC_LOW_BIT_POS_PROBE_OUT240 = "16'b0000000011110000" *) (* LC_LOW_BIT_POS_PROBE_OUT241 = "16'b0000000011110001" *)
(* LC_LOW_BIT_POS_PROBE_OUT242 = "16'b0000000011110010" *) (* LC_LOW_BIT_POS_PROBE_OUT243 = "16'b0000000011110011" *) (* LC_LOW_BIT_POS_PROBE_OUT244 = "16'b0000000011110100" *)
(* LC_LOW_BIT_POS_PROBE_OUT245 = "16'b0000000011110101" *) (* LC_LOW_BIT_POS_PROBE_OUT246 = "16'b0000000011110110" *) (* LC_LOW_BIT_POS_PROBE_OUT247 = "16'b0000000011110111" *)
(* LC_LOW_BIT_POS_PROBE_OUT248 = "16'b0000000011111000" *) (* LC_LOW_BIT_POS_PROBE_OUT249 = "16'b0000000011111001" *) (* LC_LOW_BIT_POS_PROBE_OUT25 = "16'b0000000000011001" *)
(* LC_LOW_BIT_POS_PROBE_OUT250 = "16'b0000000011111010" *) (* LC_LOW_BIT_POS_PROBE_OUT251 = "16'b0000000011111011" *) (* LC_LOW_BIT_POS_PROBE_OUT252 = "16'b0000000011111100" *)
(* LC_LOW_BIT_POS_PROBE_OUT253 = "16'b0000000011111101" *) (* LC_LOW_BIT_POS_PROBE_OUT254 = "16'b0000000011111110" *) (* LC_LOW_BIT_POS_PROBE_OUT255 = "16'b0000000011111111" *)
(* LC_LOW_BIT_POS_PROBE_OUT26 = "16'b0000000000011010" *) (* LC_LOW_BIT_POS_PROBE_OUT27 = "16'b0000000000011011" *) (* LC_LOW_BIT_POS_PROBE_OUT28 = "16'b0000000000011100" *)
(* LC_LOW_BIT_POS_PROBE_OUT29 = "16'b0000000000011101" *) (* LC_LOW_BIT_POS_PROBE_OUT3 = "16'b0000000000000011" *) (* LC_LOW_BIT_POS_PROBE_OUT30 = "16'b0000000000011110" *)
(* LC_LOW_BIT_POS_PROBE_OUT31 = "16'b0000000000011111" *) (* LC_LOW_BIT_POS_PROBE_OUT32 = "16'b0000000000100000" *) (* LC_LOW_BIT_POS_PROBE_OUT33 = "16'b0000000000100001" *)
(* LC_LOW_BIT_POS_PROBE_OUT34 = "16'b0000000000100010" *) (* LC_LOW_BIT_POS_PROBE_OUT35 = "16'b0000000000100011" *) (* LC_LOW_BIT_POS_PROBE_OUT36 = "16'b0000000000100100" *)
(* LC_LOW_BIT_POS_PROBE_OUT37 = "16'b0000000000100101" *) (* LC_LOW_BIT_POS_PROBE_OUT38 = "16'b0000000000100110" *) (* LC_LOW_BIT_POS_PROBE_OUT39 = "16'b0000000000100111" *)
(* LC_LOW_BIT_POS_PROBE_OUT4 = "16'b0000000000000100" *) (* LC_LOW_BIT_POS_PROBE_OUT40 = "16'b0000000000101000" *) (* LC_LOW_BIT_POS_PROBE_OUT41 = "16'b0000000000101001" *)
(* LC_LOW_BIT_POS_PROBE_OUT42 = "16'b0000000000101010" *) (* LC_LOW_BIT_POS_PROBE_OUT43 = "16'b0000000000101011" *) (* LC_LOW_BIT_POS_PROBE_OUT44 = "16'b0000000000101100" *)
(* LC_LOW_BIT_POS_PROBE_OUT45 = "16'b0000000000101101" *) (* LC_LOW_BIT_POS_PROBE_OUT46 = "16'b0000000000101110" *) (* LC_LOW_BIT_POS_PROBE_OUT47 = "16'b0000000000101111" *)
(* LC_LOW_BIT_POS_PROBE_OUT48 = "16'b0000000000110000" *) (* LC_LOW_BIT_POS_PROBE_OUT49 = "16'b0000000000110001" *) (* LC_LOW_BIT_POS_PROBE_OUT5 = "16'b0000000000000101" *)
(* LC_LOW_BIT_POS_PROBE_OUT50 = "16'b0000000000110010" *) (* LC_LOW_BIT_POS_PROBE_OUT51 = "16'b0000000000110011" *) (* LC_LOW_BIT_POS_PROBE_OUT52 = "16'b0000000000110100" *)
(* LC_LOW_BIT_POS_PROBE_OUT53 = "16'b0000000000110101" *) (* LC_LOW_BIT_POS_PROBE_OUT54 = "16'b0000000000110110" *) (* LC_LOW_BIT_POS_PROBE_OUT55 = "16'b0000000000110111" *)
(* LC_LOW_BIT_POS_PROBE_OUT56 = "16'b0000000000111000" *) (* LC_LOW_BIT_POS_PROBE_OUT57 = "16'b0000000000111001" *) (* LC_LOW_BIT_POS_PROBE_OUT58 = "16'b0000000000111010" *)
(* LC_LOW_BIT_POS_PROBE_OUT59 = "16'b0000000000111011" *) (* LC_LOW_BIT_POS_PROBE_OUT6 = "16'b0000000000000110" *) (* LC_LOW_BIT_POS_PROBE_OUT60 = "16'b0000000000111100" *)
(* LC_LOW_BIT_POS_PROBE_OUT61 = "16'b0000000000111101" *) (* LC_LOW_BIT_POS_PROBE_OUT62 = "16'b0000000000111110" *) (* LC_LOW_BIT_POS_PROBE_OUT63 = "16'b0000000000111111" *)
(* LC_LOW_BIT_POS_PROBE_OUT64 = "16'b0000000001000000" *) (* LC_LOW_BIT_POS_PROBE_OUT65 = "16'b0000000001000001" *) (* LC_LOW_BIT_POS_PROBE_OUT66 = "16'b0000000001000010" *)
(* LC_LOW_BIT_POS_PROBE_OUT67 = "16'b0000000001000011" *) (* LC_LOW_BIT_POS_PROBE_OUT68 = "16'b0000000001000100" *) (* LC_LOW_BIT_POS_PROBE_OUT69 = "16'b0000000001000101" *)
(* LC_LOW_BIT_POS_PROBE_OUT7 = "16'b0000000000000111" *) (* LC_LOW_BIT_POS_PROBE_OUT70 = "16'b0000000001000110" *) (* LC_LOW_BIT_POS_PROBE_OUT71 = "16'b0000000001000111" *)
(* LC_LOW_BIT_POS_PROBE_OUT72 = "16'b0000000001001000" *) (* LC_LOW_BIT_POS_PROBE_OUT73 = "16'b0000000001001001" *) (* LC_LOW_BIT_POS_PROBE_OUT74 = "16'b0000000001001010" *)
(* LC_LOW_BIT_POS_PROBE_OUT75 = "16'b0000000001001011" *) (* LC_LOW_BIT_POS_PROBE_OUT76 = "16'b0000000001001100" *) (* LC_LOW_BIT_POS_PROBE_OUT77 = "16'b0000000001001101" *)
(* LC_LOW_BIT_POS_PROBE_OUT78 = "16'b0000000001001110" *) (* LC_LOW_BIT_POS_PROBE_OUT79 = "16'b0000000001001111" *) (* LC_LOW_BIT_POS_PROBE_OUT8 = "16'b0000000000001000" *)
(* LC_LOW_BIT_POS_PROBE_OUT80 = "16'b0000000001010000" *) (* LC_LOW_BIT_POS_PROBE_OUT81 = "16'b0000000001010001" *) (* LC_LOW_BIT_POS_PROBE_OUT82 = "16'b0000000001010010" *)
(* LC_LOW_BIT_POS_PROBE_OUT83 = "16'b0000000001010011" *) (* LC_LOW_BIT_POS_PROBE_OUT84 = "16'b0000000001010100" *) (* LC_LOW_BIT_POS_PROBE_OUT85 = "16'b0000000001010101" *)
(* LC_LOW_BIT_POS_PROBE_OUT86 = "16'b0000000001010110" *) (* LC_LOW_BIT_POS_PROBE_OUT87 = "16'b0000000001010111" *) (* LC_LOW_BIT_POS_PROBE_OUT88 = "16'b0000000001011000" *)
(* LC_LOW_BIT_POS_PROBE_OUT89 = "16'b0000000001011001" *) (* LC_LOW_BIT_POS_PROBE_OUT9 = "16'b0000000000001001" *) (* LC_LOW_BIT_POS_PROBE_OUT90 = "16'b0000000001011010" *)
(* LC_LOW_BIT_POS_PROBE_OUT91 = "16'b0000000001011011" *) (* LC_LOW_BIT_POS_PROBE_OUT92 = "16'b0000000001011100" *) (* LC_LOW_BIT_POS_PROBE_OUT93 = "16'b0000000001011101" *)
(* LC_LOW_BIT_POS_PROBE_OUT94 = "16'b0000000001011110" *) (* LC_LOW_BIT_POS_PROBE_OUT95 = "16'b0000000001011111" *) (* LC_LOW_BIT_POS_PROBE_OUT96 = "16'b0000000001100000" *)
(* LC_LOW_BIT_POS_PROBE_OUT97 = "16'b0000000001100001" *) (* LC_LOW_BIT_POS_PROBE_OUT98 = "16'b0000000001100010" *) (* LC_LOW_BIT_POS_PROBE_OUT99 = "16'b0000000001100011" *)
(* LC_PROBE_IN_WIDTH_STRING = "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) (* LC_PROBE_OUT_HIGH_BIT_POS_STRING = "4096'b0000000011111111000000001111111000000000111111010000000011111100000000001111101100000000111110100000000011111001000000001111100000000000111101110000000011110110000000001111010100000000111101000000000011110011000000001111001000000000111100010000000011110000000000001110111100000000111011100000000011101101000000001110110000000000111010110000000011101010000000001110100100000000111010000000000011100111000000001110011000000000111001010000000011100100000000001110001100000000111000100000000011100001000000001110000000000000110111110000000011011110000000001101110100000000110111000000000011011011000000001101101000000000110110010000000011011000000000001101011100000000110101100000000011010101000000001101010000000000110100110000000011010010000000001101000100000000110100000000000011001111000000001100111000000000110011010000000011001100000000001100101100000000110010100000000011001001000000001100100000000000110001110000000011000110000000001100010100000000110001000000000011000011000000001100001000000000110000010000000011000000000000001011111100000000101111100000000010111101000000001011110000000000101110110000000010111010000000001011100100000000101110000000000010110111000000001011011000000000101101010000000010110100000000001011001100000000101100100000000010110001000000001011000000000000101011110000000010101110000000001010110100000000101011000000000010101011000000001010101000000000101010010000000010101000000000001010011100000000101001100000000010100101000000001010010000000000101000110000000010100010000000001010000100000000101000000000000010011111000000001001111000000000100111010000000010011100000000001001101100000000100110100000000010011001000000001001100000000000100101110000000010010110000000001001010100000000100101000000000010010011000000001001001000000000100100010000000010010000000000001000111100000000100011100000000010001101000000001000110000000000100010110000000010001010000000001000100100000000100010000000000010000111000000001000011000000000100001010000000010000100000000001000001100000000100000100000000010000001000000001000000000000000011111110000000001111110000000000111110100000000011111000000000001111011000000000111101000000000011110010000000001111000000000000111011100000000011101100000000001110101000000000111010000000000011100110000000001110010000000000111000100000000011100000000000001101111000000000110111000000000011011010000000001101100000000000110101100000000011010100000000001101001000000000110100000000000011001110000000001100110000000000110010100000000011001000000000001100011000000000110001000000000011000010000000001100000000000000101111100000000010111100000000001011101000000000101110000000000010110110000000001011010000000000101100100000000010110000000000001010111000000000101011000000000010101010000000001010100000000000101001100000000010100100000000001010001000000000101000000000000010011110000000001001110000000000100110100000000010011000000000001001011000000000100101000000000010010010000000001001000000000000100011100000000010001100000000001000101000000000100010000000000010000110000000001000010000000000100000100000000010000000000000000111111000000000011111000000000001111010000000000111100000000000011101100000000001110100000000000111001000000000011100000000000001101110000000000110110000000000011010100000000001101000000000000110011000000000011001000000000001100010000000000110000000000000010111100000000001011100000000000101101000000000010110000000000001010110000000000101010000000000010100100000000001010000000000000100111000000000010011000000000001001010000000000100100000000000010001100000000001000100000000000100001000000000010000000000000000111110000000000011110000000000001110100000000000111000000000000011011000000000001101000000000000110010000000000011000000000000001011100000000000101100000000000010101000000000001010000000000000100110000000000010010000000000001000100000000000100000000000000001111000000000000111000000000000011010000000000001100000000000000101100000000000010100000000000001001000000000000100000000000000001110000000000000110000000000000010100000000000001000000000000000011000000000000001000000000000000010000000000000000" *) (* LC_PROBE_OUT_INIT_VAL_STRING = "256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
(* LC_PROBE_OUT_LOW_BIT_POS_STRING = "4096'b0000000011111111000000001111111000000000111111010000000011111100000000001111101100000000111110100000000011111001000000001111100000000000111101110000000011110110000000001111010100000000111101000000000011110011000000001111001000000000111100010000000011110000000000001110111100000000111011100000000011101101000000001110110000000000111010110000000011101010000000001110100100000000111010000000000011100111000000001110011000000000111001010000000011100100000000001110001100000000111000100000000011100001000000001110000000000000110111110000000011011110000000001101110100000000110111000000000011011011000000001101101000000000110110010000000011011000000000001101011100000000110101100000000011010101000000001101010000000000110100110000000011010010000000001101000100000000110100000000000011001111000000001100111000000000110011010000000011001100000000001100101100000000110010100000000011001001000000001100100000000000110001110000000011000110000000001100010100000000110001000000000011000011000000001100001000000000110000010000000011000000000000001011111100000000101111100000000010111101000000001011110000000000101110110000000010111010000000001011100100000000101110000000000010110111000000001011011000000000101101010000000010110100000000001011001100000000101100100000000010110001000000001011000000000000101011110000000010101110000000001010110100000000101011000000000010101011000000001010101000000000101010010000000010101000000000001010011100000000101001100000000010100101000000001010010000000000101000110000000010100010000000001010000100000000101000000000000010011111000000001001111000000000100111010000000010011100000000001001101100000000100110100000000010011001000000001001100000000000100101110000000010010110000000001001010100000000100101000000000010010011000000001001001000000000100100010000000010010000000000001000111100000000100011100000000010001101000000001000110000000000100010110000000010001010000000001000100100000000100010000000000010000111000000001000011000000000100001010000000010000100000000001000001100000000100000100000000010000001000000001000000000000000011111110000000001111110000000000111110100000000011111000000000001111011000000000111101000000000011110010000000001111000000000000111011100000000011101100000000001110101000000000111010000000000011100110000000001110010000000000111000100000000011100000000000001101111000000000110111000000000011011010000000001101100000000000110101100000000011010100000000001101001000000000110100000000000011001110000000001100110000000000110010100000000011001000000000001100011000000000110001000000000011000010000000001100000000000000101111100000000010111100000000001011101000000000101110000000000010110110000000001011010000000000101100100000000010110000000000001010111000000000101011000000000010101010000000001010100000000000101001100000000010100100000000001010001000000000101000000000000010011110000000001001110000000000100110100000000010011000000000001001011000000000100101000000000010010010000000001001000000000000100011100000000010001100000000001000101000000000100010000000000010000110000000001000010000000000100000100000000010000000000000000111111000000000011111000000000001111010000000000111100000000000011101100000000001110100000000000111001000000000011100000000000001101110000000000110110000000000011010100000000001101000000000000110011000000000011001000000000001100010000000000110000000000000010111100000000001011100000000000101101000000000010110000000000001010110000000000101010000000000010100100000000001010000000000000100111000000000010011000000000001001010000000000100100000000000010001100000000001000100000000000100001000000000010000000000000000111110000000000011110000000000001110100000000000111000000000000011011000000000001101000000000000110010000000000011000000000000001011100000000000101100000000000010101000000000001010000000000000100110000000000010010000000000001000100000000000100000000000000001111000000000000111000000000000011010000000000001100000000000000101100000000000010100000000000001001000000000000100000000000000001110000000000000110000000000000010100000000000001000000000000000011000000000000001000000000000000010000000000000000" *) (* LC_PROBE_OUT_WIDTH_STRING = "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) (* LC_TOTAL_PROBE_IN_WIDTH = "4" *)
(* LC_TOTAL_PROBE_OUT_WIDTH = "0" *) (* dont_touch = "true" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio
(clk,
probe_in0,
probe_in1,
probe_in2,
probe_in3,
probe_in4,
probe_in5,
probe_in6,
probe_in7,
probe_in8,
probe_in9,
probe_in10,
probe_in11,
probe_in12,
probe_in13,
probe_in14,
probe_in15,
probe_in16,
probe_in17,
probe_in18,
probe_in19,
probe_in20,
probe_in21,
probe_in22,
probe_in23,
probe_in24,
probe_in25,
probe_in26,
probe_in27,
probe_in28,
probe_in29,
probe_in30,
probe_in31,
probe_in32,
probe_in33,
probe_in34,
probe_in35,
probe_in36,
probe_in37,
probe_in38,
probe_in39,
probe_in40,
probe_in41,
probe_in42,
probe_in43,
probe_in44,
probe_in45,
probe_in46,
probe_in47,
probe_in48,
probe_in49,
probe_in50,
probe_in51,
probe_in52,
probe_in53,
probe_in54,
probe_in55,
probe_in56,
probe_in57,
probe_in58,
probe_in59,
probe_in60,
probe_in61,
probe_in62,
probe_in63,
probe_in64,
probe_in65,
probe_in66,
probe_in67,
probe_in68,
probe_in69,
probe_in70,
probe_in71,
probe_in72,
probe_in73,
probe_in74,
probe_in75,
probe_in76,
probe_in77,
probe_in78,
probe_in79,
probe_in80,
probe_in81,
probe_in82,
probe_in83,
probe_in84,
probe_in85,
probe_in86,
probe_in87,
probe_in88,
probe_in89,
probe_in90,
probe_in91,
probe_in92,
probe_in93,
probe_in94,
probe_in95,
probe_in96,
probe_in97,
probe_in98,
probe_in99,
probe_in100,
probe_in101,
probe_in102,
probe_in103,
probe_in104,
probe_in105,
probe_in106,
probe_in107,
probe_in108,
probe_in109,
probe_in110,
probe_in111,
probe_in112,
probe_in113,
probe_in114,
probe_in115,
probe_in116,
probe_in117,
probe_in118,
probe_in119,
probe_in120,
probe_in121,
probe_in122,
probe_in123,
probe_in124,
probe_in125,
probe_in126,
probe_in127,
probe_in128,
probe_in129,
probe_in130,
probe_in131,
probe_in132,
probe_in133,
probe_in134,
probe_in135,
probe_in136,
probe_in137,
probe_in138,
probe_in139,
probe_in140,
probe_in141,
probe_in142,
probe_in143,
probe_in144,
probe_in145,
probe_in146,
probe_in147,
probe_in148,
probe_in149,
probe_in150,
probe_in151,
probe_in152,
probe_in153,
probe_in154,
probe_in155,
probe_in156,
probe_in157,
probe_in158,
probe_in159,
probe_in160,
probe_in161,
probe_in162,
probe_in163,
probe_in164,
probe_in165,
probe_in166,
probe_in167,
probe_in168,
probe_in169,
probe_in170,
probe_in171,
probe_in172,
probe_in173,
probe_in174,
probe_in175,
probe_in176,
probe_in177,
probe_in178,
probe_in179,
probe_in180,
probe_in181,
probe_in182,
probe_in183,
probe_in184,
probe_in185,
probe_in186,
probe_in187,
probe_in188,
probe_in189,
probe_in190,
probe_in191,
probe_in192,
probe_in193,
probe_in194,
probe_in195,
probe_in196,
probe_in197,
probe_in198,
probe_in199,
probe_in200,
probe_in201,
probe_in202,
probe_in203,
probe_in204,
probe_in205,
probe_in206,
probe_in207,
probe_in208,
probe_in209,
probe_in210,
probe_in211,
probe_in212,
probe_in213,
probe_in214,
probe_in215,
probe_in216,
probe_in217,
probe_in218,
probe_in219,
probe_in220,
probe_in221,
probe_in222,
probe_in223,
probe_in224,
probe_in225,
probe_in226,
probe_in227,
probe_in228,
probe_in229,
probe_in230,
probe_in231,
probe_in232,
probe_in233,
probe_in234,
probe_in235,
probe_in236,
probe_in237,
probe_in238,
probe_in239,
probe_in240,
probe_in241,
probe_in242,
probe_in243,
probe_in244,
probe_in245,
probe_in246,
probe_in247,
probe_in248,
probe_in249,
probe_in250,
probe_in251,
probe_in252,
probe_in253,
probe_in254,
probe_in255,
sl_iport0,
sl_oport0,
probe_out0,
probe_out1,
probe_out2,
probe_out3,
probe_out4,
probe_out5,
probe_out6,
probe_out7,
probe_out8,
probe_out9,
probe_out10,
probe_out11,
probe_out12,
probe_out13,
probe_out14,
probe_out15,
probe_out16,
probe_out17,
probe_out18,
probe_out19,
probe_out20,
probe_out21,
probe_out22,
probe_out23,
probe_out24,
probe_out25,
probe_out26,
probe_out27,
probe_out28,
probe_out29,
probe_out30,
probe_out31,
probe_out32,
probe_out33,
probe_out34,
probe_out35,
probe_out36,
probe_out37,
probe_out38,
probe_out39,
probe_out40,
probe_out41,
probe_out42,
probe_out43,
probe_out44,
probe_out45,
probe_out46,
probe_out47,
probe_out48,
probe_out49,
probe_out50,
probe_out51,
probe_out52,
probe_out53,
probe_out54,
probe_out55,
probe_out56,
probe_out57,
probe_out58,
probe_out59,
probe_out60,
probe_out61,
probe_out62,
probe_out63,
probe_out64,
probe_out65,
probe_out66,
probe_out67,
probe_out68,
probe_out69,
probe_out70,
probe_out71,
probe_out72,
probe_out73,
probe_out74,
probe_out75,
probe_out76,
probe_out77,
probe_out78,
probe_out79,
probe_out80,
probe_out81,
probe_out82,
probe_out83,
probe_out84,
probe_out85,
probe_out86,
probe_out87,
probe_out88,
probe_out89,
probe_out90,
probe_out91,
probe_out92,
probe_out93,
probe_out94,
probe_out95,
probe_out96,
probe_out97,
probe_out98,
probe_out99,
probe_out100,
probe_out101,
probe_out102,
probe_out103,
probe_out104,
probe_out105,
probe_out106,
probe_out107,
probe_out108,
probe_out109,
probe_out110,
probe_out111,
probe_out112,
probe_out113,
probe_out114,
probe_out115,
probe_out116,
probe_out117,
probe_out118,
probe_out119,
probe_out120,
probe_out121,
probe_out122,
probe_out123,
probe_out124,
probe_out125,
probe_out126,
probe_out127,
probe_out128,
probe_out129,
probe_out130,
probe_out131,
probe_out132,
probe_out133,
probe_out134,
probe_out135,
probe_out136,
probe_out137,
probe_out138,
probe_out139,
probe_out140,
probe_out141,
probe_out142,
probe_out143,
probe_out144,
probe_out145,
probe_out146,
probe_out147,
probe_out148,
probe_out149,
probe_out150,
probe_out151,
probe_out152,
probe_out153,
probe_out154,
probe_out155,
probe_out156,
probe_out157,
probe_out158,
probe_out159,
probe_out160,
probe_out161,
probe_out162,
probe_out163,
probe_out164,
probe_out165,
probe_out166,
probe_out167,
probe_out168,
probe_out169,
probe_out170,
probe_out171,
probe_out172,
probe_out173,
probe_out174,
probe_out175,
probe_out176,
probe_out177,
probe_out178,
probe_out179,
probe_out180,
probe_out181,
probe_out182,
probe_out183,
probe_out184,
probe_out185,
probe_out186,
probe_out187,
probe_out188,
probe_out189,
probe_out190,
probe_out191,
probe_out192,
probe_out193,
probe_out194,
probe_out195,
probe_out196,
probe_out197,
probe_out198,
probe_out199,
probe_out200,
probe_out201,
probe_out202,
probe_out203,
probe_out204,
probe_out205,
probe_out206,
probe_out207,
probe_out208,
probe_out209,
probe_out210,
probe_out211,
probe_out212,
probe_out213,
probe_out214,
probe_out215,
probe_out216,
probe_out217,
probe_out218,
probe_out219,
probe_out220,
probe_out221,
probe_out222,
probe_out223,
probe_out224,
probe_out225,
probe_out226,
probe_out227,
probe_out228,
probe_out229,
probe_out230,
probe_out231,
probe_out232,
probe_out233,
probe_out234,
probe_out235,
probe_out236,
probe_out237,
probe_out238,
probe_out239,
probe_out240,
probe_out241,
probe_out242,
probe_out243,
probe_out244,
probe_out245,
probe_out246,
probe_out247,
probe_out248,
probe_out249,
probe_out250,
probe_out251,
probe_out252,
probe_out253,
probe_out254,
probe_out255);
input clk;
input [0:0]probe_in0;
input [0:0]probe_in1;
input [0:0]probe_in2;
input [0:0]probe_in3;
input [0:0]probe_in4;
input [0:0]probe_in5;
input [0:0]probe_in6;
input [0:0]probe_in7;
input [0:0]probe_in8;
input [0:0]probe_in9;
input [0:0]probe_in10;
input [0:0]probe_in11;
input [0:0]probe_in12;
input [0:0]probe_in13;
input [0:0]probe_in14;
input [0:0]probe_in15;
input [0:0]probe_in16;
input [0:0]probe_in17;
input [0:0]probe_in18;
input [0:0]probe_in19;
input [0:0]probe_in20;
input [0:0]probe_in21;
input [0:0]probe_in22;
input [0:0]probe_in23;
input [0:0]probe_in24;
input [0:0]probe_in25;
input [0:0]probe_in26;
input [0:0]probe_in27;
input [0:0]probe_in28;
input [0:0]probe_in29;
input [0:0]probe_in30;
input [0:0]probe_in31;
input [0:0]probe_in32;
input [0:0]probe_in33;
input [0:0]probe_in34;
input [0:0]probe_in35;
input [0:0]probe_in36;
input [0:0]probe_in37;
input [0:0]probe_in38;
input [0:0]probe_in39;
input [0:0]probe_in40;
input [0:0]probe_in41;
input [0:0]probe_in42;
input [0:0]probe_in43;
input [0:0]probe_in44;
input [0:0]probe_in45;
input [0:0]probe_in46;
input [0:0]probe_in47;
input [0:0]probe_in48;
input [0:0]probe_in49;
input [0:0]probe_in50;
input [0:0]probe_in51;
input [0:0]probe_in52;
input [0:0]probe_in53;
input [0:0]probe_in54;
input [0:0]probe_in55;
input [0:0]probe_in56;
input [0:0]probe_in57;
input [0:0]probe_in58;
input [0:0]probe_in59;
input [0:0]probe_in60;
input [0:0]probe_in61;
input [0:0]probe_in62;
input [0:0]probe_in63;
input [0:0]probe_in64;
input [0:0]probe_in65;
input [0:0]probe_in66;
input [0:0]probe_in67;
input [0:0]probe_in68;
input [0:0]probe_in69;
input [0:0]probe_in70;
input [0:0]probe_in71;
input [0:0]probe_in72;
input [0:0]probe_in73;
input [0:0]probe_in74;
input [0:0]probe_in75;
input [0:0]probe_in76;
input [0:0]probe_in77;
input [0:0]probe_in78;
input [0:0]probe_in79;
input [0:0]probe_in80;
input [0:0]probe_in81;
input [0:0]probe_in82;
input [0:0]probe_in83;
input [0:0]probe_in84;
input [0:0]probe_in85;
input [0:0]probe_in86;
input [0:0]probe_in87;
input [0:0]probe_in88;
input [0:0]probe_in89;
input [0:0]probe_in90;
input [0:0]probe_in91;
input [0:0]probe_in92;
input [0:0]probe_in93;
input [0:0]probe_in94;
input [0:0]probe_in95;
input [0:0]probe_in96;
input [0:0]probe_in97;
input [0:0]probe_in98;
input [0:0]probe_in99;
input [0:0]probe_in100;
input [0:0]probe_in101;
input [0:0]probe_in102;
input [0:0]probe_in103;
input [0:0]probe_in104;
input [0:0]probe_in105;
input [0:0]probe_in106;
input [0:0]probe_in107;
input [0:0]probe_in108;
input [0:0]probe_in109;
input [0:0]probe_in110;
input [0:0]probe_in111;
input [0:0]probe_in112;
input [0:0]probe_in113;
input [0:0]probe_in114;
input [0:0]probe_in115;
input [0:0]probe_in116;
input [0:0]probe_in117;
input [0:0]probe_in118;
input [0:0]probe_in119;
input [0:0]probe_in120;
input [0:0]probe_in121;
input [0:0]probe_in122;
input [0:0]probe_in123;
input [0:0]probe_in124;
input [0:0]probe_in125;
input [0:0]probe_in126;
input [0:0]probe_in127;
input [0:0]probe_in128;
input [0:0]probe_in129;
input [0:0]probe_in130;
input [0:0]probe_in131;
input [0:0]probe_in132;
input [0:0]probe_in133;
input [0:0]probe_in134;
input [0:0]probe_in135;
input [0:0]probe_in136;
input [0:0]probe_in137;
input [0:0]probe_in138;
input [0:0]probe_in139;
input [0:0]probe_in140;
input [0:0]probe_in141;
input [0:0]probe_in142;
input [0:0]probe_in143;
input [0:0]probe_in144;
input [0:0]probe_in145;
input [0:0]probe_in146;
input [0:0]probe_in147;
input [0:0]probe_in148;
input [0:0]probe_in149;
input [0:0]probe_in150;
input [0:0]probe_in151;
input [0:0]probe_in152;
input [0:0]probe_in153;
input [0:0]probe_in154;
input [0:0]probe_in155;
input [0:0]probe_in156;
input [0:0]probe_in157;
input [0:0]probe_in158;
input [0:0]probe_in159;
input [0:0]probe_in160;
input [0:0]probe_in161;
input [0:0]probe_in162;
input [0:0]probe_in163;
input [0:0]probe_in164;
input [0:0]probe_in165;
input [0:0]probe_in166;
input [0:0]probe_in167;
input [0:0]probe_in168;
input [0:0]probe_in169;
input [0:0]probe_in170;
input [0:0]probe_in171;
input [0:0]probe_in172;
input [0:0]probe_in173;
input [0:0]probe_in174;
input [0:0]probe_in175;
input [0:0]probe_in176;
input [0:0]probe_in177;
input [0:0]probe_in178;
input [0:0]probe_in179;
input [0:0]probe_in180;
input [0:0]probe_in181;
input [0:0]probe_in182;
input [0:0]probe_in183;
input [0:0]probe_in184;
input [0:0]probe_in185;
input [0:0]probe_in186;
input [0:0]probe_in187;
input [0:0]probe_in188;
input [0:0]probe_in189;
input [0:0]probe_in190;
input [0:0]probe_in191;
input [0:0]probe_in192;
input [0:0]probe_in193;
input [0:0]probe_in194;
input [0:0]probe_in195;
input [0:0]probe_in196;
input [0:0]probe_in197;
input [0:0]probe_in198;
input [0:0]probe_in199;
input [0:0]probe_in200;
input [0:0]probe_in201;
input [0:0]probe_in202;
input [0:0]probe_in203;
input [0:0]probe_in204;
input [0:0]probe_in205;
input [0:0]probe_in206;
input [0:0]probe_in207;
input [0:0]probe_in208;
input [0:0]probe_in209;
input [0:0]probe_in210;
input [0:0]probe_in211;
input [0:0]probe_in212;
input [0:0]probe_in213;
input [0:0]probe_in214;
input [0:0]probe_in215;
input [0:0]probe_in216;
input [0:0]probe_in217;
input [0:0]probe_in218;
input [0:0]probe_in219;
input [0:0]probe_in220;
input [0:0]probe_in221;
input [0:0]probe_in222;
input [0:0]probe_in223;
input [0:0]probe_in224;
input [0:0]probe_in225;
input [0:0]probe_in226;
input [0:0]probe_in227;
input [0:0]probe_in228;
input [0:0]probe_in229;
input [0:0]probe_in230;
input [0:0]probe_in231;
input [0:0]probe_in232;
input [0:0]probe_in233;
input [0:0]probe_in234;
input [0:0]probe_in235;
input [0:0]probe_in236;
input [0:0]probe_in237;
input [0:0]probe_in238;
input [0:0]probe_in239;
input [0:0]probe_in240;
input [0:0]probe_in241;
input [0:0]probe_in242;
input [0:0]probe_in243;
input [0:0]probe_in244;
input [0:0]probe_in245;
input [0:0]probe_in246;
input [0:0]probe_in247;
input [0:0]probe_in248;
input [0:0]probe_in249;
input [0:0]probe_in250;
input [0:0]probe_in251;
input [0:0]probe_in252;
input [0:0]probe_in253;
input [0:0]probe_in254;
input [0:0]probe_in255;
(* dont_touch = "true" *) input [36:0]sl_iport0;
(* dont_touch = "true" *) output [16:0]sl_oport0;
output [0:0]probe_out0;
output [0:0]probe_out1;
output [0:0]probe_out2;
output [0:0]probe_out3;
output [0:0]probe_out4;
output [0:0]probe_out5;
output [0:0]probe_out6;
output [0:0]probe_out7;
output [0:0]probe_out8;
output [0:0]probe_out9;
output [0:0]probe_out10;
output [0:0]probe_out11;
output [0:0]probe_out12;
output [0:0]probe_out13;
output [0:0]probe_out14;
output [0:0]probe_out15;
output [0:0]probe_out16;
output [0:0]probe_out17;
output [0:0]probe_out18;
output [0:0]probe_out19;
output [0:0]probe_out20;
output [0:0]probe_out21;
output [0:0]probe_out22;
output [0:0]probe_out23;
output [0:0]probe_out24;
output [0:0]probe_out25;
output [0:0]probe_out26;
output [0:0]probe_out27;
output [0:0]probe_out28;
output [0:0]probe_out29;
output [0:0]probe_out30;
output [0:0]probe_out31;
output [0:0]probe_out32;
output [0:0]probe_out33;
output [0:0]probe_out34;
output [0:0]probe_out35;
output [0:0]probe_out36;
output [0:0]probe_out37;
output [0:0]probe_out38;
output [0:0]probe_out39;
output [0:0]probe_out40;
output [0:0]probe_out41;
output [0:0]probe_out42;
output [0:0]probe_out43;
output [0:0]probe_out44;
output [0:0]probe_out45;
output [0:0]probe_out46;
output [0:0]probe_out47;
output [0:0]probe_out48;
output [0:0]probe_out49;
output [0:0]probe_out50;
output [0:0]probe_out51;
output [0:0]probe_out52;
output [0:0]probe_out53;
output [0:0]probe_out54;
output [0:0]probe_out55;
output [0:0]probe_out56;
output [0:0]probe_out57;
output [0:0]probe_out58;
output [0:0]probe_out59;
output [0:0]probe_out60;
output [0:0]probe_out61;
output [0:0]probe_out62;
output [0:0]probe_out63;
output [0:0]probe_out64;
output [0:0]probe_out65;
output [0:0]probe_out66;
output [0:0]probe_out67;
output [0:0]probe_out68;
output [0:0]probe_out69;
output [0:0]probe_out70;
output [0:0]probe_out71;
output [0:0]probe_out72;
output [0:0]probe_out73;
output [0:0]probe_out74;
output [0:0]probe_out75;
output [0:0]probe_out76;
output [0:0]probe_out77;
output [0:0]probe_out78;
output [0:0]probe_out79;
output [0:0]probe_out80;
output [0:0]probe_out81;
output [0:0]probe_out82;
output [0:0]probe_out83;
output [0:0]probe_out84;
output [0:0]probe_out85;
output [0:0]probe_out86;
output [0:0]probe_out87;
output [0:0]probe_out88;
output [0:0]probe_out89;
output [0:0]probe_out90;
output [0:0]probe_out91;
output [0:0]probe_out92;
output [0:0]probe_out93;
output [0:0]probe_out94;
output [0:0]probe_out95;
output [0:0]probe_out96;
output [0:0]probe_out97;
output [0:0]probe_out98;
output [0:0]probe_out99;
output [0:0]probe_out100;
output [0:0]probe_out101;
output [0:0]probe_out102;
output [0:0]probe_out103;
output [0:0]probe_out104;
output [0:0]probe_out105;
output [0:0]probe_out106;
output [0:0]probe_out107;
output [0:0]probe_out108;
output [0:0]probe_out109;
output [0:0]probe_out110;
output [0:0]probe_out111;
output [0:0]probe_out112;
output [0:0]probe_out113;
output [0:0]probe_out114;
output [0:0]probe_out115;
output [0:0]probe_out116;
output [0:0]probe_out117;
output [0:0]probe_out118;
output [0:0]probe_out119;
output [0:0]probe_out120;
output [0:0]probe_out121;
output [0:0]probe_out122;
output [0:0]probe_out123;
output [0:0]probe_out124;
output [0:0]probe_out125;
output [0:0]probe_out126;
output [0:0]probe_out127;
output [0:0]probe_out128;
output [0:0]probe_out129;
output [0:0]probe_out130;
output [0:0]probe_out131;
output [0:0]probe_out132;
output [0:0]probe_out133;
output [0:0]probe_out134;
output [0:0]probe_out135;
output [0:0]probe_out136;
output [0:0]probe_out137;
output [0:0]probe_out138;
output [0:0]probe_out139;
output [0:0]probe_out140;
output [0:0]probe_out141;
output [0:0]probe_out142;
output [0:0]probe_out143;
output [0:0]probe_out144;
output [0:0]probe_out145;
output [0:0]probe_out146;
output [0:0]probe_out147;
output [0:0]probe_out148;
output [0:0]probe_out149;
output [0:0]probe_out150;
output [0:0]probe_out151;
output [0:0]probe_out152;
output [0:0]probe_out153;
output [0:0]probe_out154;
output [0:0]probe_out155;
output [0:0]probe_out156;
output [0:0]probe_out157;
output [0:0]probe_out158;
output [0:0]probe_out159;
output [0:0]probe_out160;
output [0:0]probe_out161;
output [0:0]probe_out162;
output [0:0]probe_out163;
output [0:0]probe_out164;
output [0:0]probe_out165;
output [0:0]probe_out166;
output [0:0]probe_out167;
output [0:0]probe_out168;
output [0:0]probe_out169;
output [0:0]probe_out170;
output [0:0]probe_out171;
output [0:0]probe_out172;
output [0:0]probe_out173;
output [0:0]probe_out174;
output [0:0]probe_out175;
output [0:0]probe_out176;
output [0:0]probe_out177;
output [0:0]probe_out178;
output [0:0]probe_out179;
output [0:0]probe_out180;
output [0:0]probe_out181;
output [0:0]probe_out182;
output [0:0]probe_out183;
output [0:0]probe_out184;
output [0:0]probe_out185;
output [0:0]probe_out186;
output [0:0]probe_out187;
output [0:0]probe_out188;
output [0:0]probe_out189;
output [0:0]probe_out190;
output [0:0]probe_out191;
output [0:0]probe_out192;
output [0:0]probe_out193;
output [0:0]probe_out194;
output [0:0]probe_out195;
output [0:0]probe_out196;
output [0:0]probe_out197;
output [0:0]probe_out198;
output [0:0]probe_out199;
output [0:0]probe_out200;
output [0:0]probe_out201;
output [0:0]probe_out202;
output [0:0]probe_out203;
output [0:0]probe_out204;
output [0:0]probe_out205;
output [0:0]probe_out206;
output [0:0]probe_out207;
output [0:0]probe_out208;
output [0:0]probe_out209;
output [0:0]probe_out210;
output [0:0]probe_out211;
output [0:0]probe_out212;
output [0:0]probe_out213;
output [0:0]probe_out214;
output [0:0]probe_out215;
output [0:0]probe_out216;
output [0:0]probe_out217;
output [0:0]probe_out218;
output [0:0]probe_out219;
output [0:0]probe_out220;
output [0:0]probe_out221;
output [0:0]probe_out222;
output [0:0]probe_out223;
output [0:0]probe_out224;
output [0:0]probe_out225;
output [0:0]probe_out226;
output [0:0]probe_out227;
output [0:0]probe_out228;
output [0:0]probe_out229;
output [0:0]probe_out230;
output [0:0]probe_out231;
output [0:0]probe_out232;
output [0:0]probe_out233;
output [0:0]probe_out234;
output [0:0]probe_out235;
output [0:0]probe_out236;
output [0:0]probe_out237;
output [0:0]probe_out238;
output [0:0]probe_out239;
output [0:0]probe_out240;
output [0:0]probe_out241;
output [0:0]probe_out242;
output [0:0]probe_out243;
output [0:0]probe_out244;
output [0:0]probe_out245;
output [0:0]probe_out246;
output [0:0]probe_out247;
output [0:0]probe_out248;
output [0:0]probe_out249;
output [0:0]probe_out250;
output [0:0]probe_out251;
output [0:0]probe_out252;
output [0:0]probe_out253;
output [0:0]probe_out254;
output [0:0]probe_out255;
wire \<const0> ;
wire [11:0]Bus_Data_out;
wire DECODER_INST_n_1;
wire DECODER_INST_n_2;
wire DECODER_INST_n_3;
wire DECODER_INST_n_4;
wire [16:0]bus_addr;
(* DONT_TOUCH *) wire bus_clk;
wire \bus_data_int_reg_n_0_[0] ;
wire \bus_data_int_reg_n_0_[10] ;
wire \bus_data_int_reg_n_0_[11] ;
wire \bus_data_int_reg_n_0_[12] ;
wire \bus_data_int_reg_n_0_[13] ;
wire \bus_data_int_reg_n_0_[14] ;
wire \bus_data_int_reg_n_0_[15] ;
wire \bus_data_int_reg_n_0_[2] ;
wire \bus_data_int_reg_n_0_[3] ;
wire \bus_data_int_reg_n_0_[4] ;
wire \bus_data_int_reg_n_0_[5] ;
wire \bus_data_int_reg_n_0_[6] ;
wire \bus_data_int_reg_n_0_[7] ;
wire \bus_data_int_reg_n_0_[8] ;
wire \bus_data_int_reg_n_0_[9] ;
wire bus_den;
wire [15:0]bus_di;
wire [15:0]bus_do;
wire bus_drdy;
wire bus_dwe;
wire bus_rst;
wire clk;
wire p_0_in;
wire [0:0]probe_in0;
wire [0:0]probe_in1;
wire [0:0]probe_in2;
wire [0:0]probe_in3;
(* DONT_TOUCH *) wire [36:0]sl_iport0;
(* DONT_TOUCH *) wire [16:0]sl_oport0;
assign probe_out0[0] = \<const0> ;
assign probe_out1[0] = \<const0> ;
assign probe_out10[0] = \<const0> ;
assign probe_out100[0] = \<const0> ;
assign probe_out101[0] = \<const0> ;
assign probe_out102[0] = \<const0> ;
assign probe_out103[0] = \<const0> ;
assign probe_out104[0] = \<const0> ;
assign probe_out105[0] = \<const0> ;
assign probe_out106[0] = \<const0> ;
assign probe_out107[0] = \<const0> ;
assign probe_out108[0] = \<const0> ;
assign probe_out109[0] = \<const0> ;
assign probe_out11[0] = \<const0> ;
assign probe_out110[0] = \<const0> ;
assign probe_out111[0] = \<const0> ;
assign probe_out112[0] = \<const0> ;
assign probe_out113[0] = \<const0> ;
assign probe_out114[0] = \<const0> ;
assign probe_out115[0] = \<const0> ;
assign probe_out116[0] = \<const0> ;
assign probe_out117[0] = \<const0> ;
assign probe_out118[0] = \<const0> ;
assign probe_out119[0] = \<const0> ;
assign probe_out12[0] = \<const0> ;
assign probe_out120[0] = \<const0> ;
assign probe_out121[0] = \<const0> ;
assign probe_out122[0] = \<const0> ;
assign probe_out123[0] = \<const0> ;
assign probe_out124[0] = \<const0> ;
assign probe_out125[0] = \<const0> ;
assign probe_out126[0] = \<const0> ;
assign probe_out127[0] = \<const0> ;
assign probe_out128[0] = \<const0> ;
assign probe_out129[0] = \<const0> ;
assign probe_out13[0] = \<const0> ;
assign probe_out130[0] = \<const0> ;
assign probe_out131[0] = \<const0> ;
assign probe_out132[0] = \<const0> ;
assign probe_out133[0] = \<const0> ;
assign probe_out134[0] = \<const0> ;
assign probe_out135[0] = \<const0> ;
assign probe_out136[0] = \<const0> ;
assign probe_out137[0] = \<const0> ;
assign probe_out138[0] = \<const0> ;
assign probe_out139[0] = \<const0> ;
assign probe_out14[0] = \<const0> ;
assign probe_out140[0] = \<const0> ;
assign probe_out141[0] = \<const0> ;
assign probe_out142[0] = \<const0> ;
assign probe_out143[0] = \<const0> ;
assign probe_out144[0] = \<const0> ;
assign probe_out145[0] = \<const0> ;
assign probe_out146[0] = \<const0> ;
assign probe_out147[0] = \<const0> ;
assign probe_out148[0] = \<const0> ;
assign probe_out149[0] = \<const0> ;
assign probe_out15[0] = \<const0> ;
assign probe_out150[0] = \<const0> ;
assign probe_out151[0] = \<const0> ;
assign probe_out152[0] = \<const0> ;
assign probe_out153[0] = \<const0> ;
assign probe_out154[0] = \<const0> ;
assign probe_out155[0] = \<const0> ;
assign probe_out156[0] = \<const0> ;
assign probe_out157[0] = \<const0> ;
assign probe_out158[0] = \<const0> ;
assign probe_out159[0] = \<const0> ;
assign probe_out16[0] = \<const0> ;
assign probe_out160[0] = \<const0> ;
assign probe_out161[0] = \<const0> ;
assign probe_out162[0] = \<const0> ;
assign probe_out163[0] = \<const0> ;
assign probe_out164[0] = \<const0> ;
assign probe_out165[0] = \<const0> ;
assign probe_out166[0] = \<const0> ;
assign probe_out167[0] = \<const0> ;
assign probe_out168[0] = \<const0> ;
assign probe_out169[0] = \<const0> ;
assign probe_out17[0] = \<const0> ;
assign probe_out170[0] = \<const0> ;
assign probe_out171[0] = \<const0> ;
assign probe_out172[0] = \<const0> ;
assign probe_out173[0] = \<const0> ;
assign probe_out174[0] = \<const0> ;
assign probe_out175[0] = \<const0> ;
assign probe_out176[0] = \<const0> ;
assign probe_out177[0] = \<const0> ;
assign probe_out178[0] = \<const0> ;
assign probe_out179[0] = \<const0> ;
assign probe_out18[0] = \<const0> ;
assign probe_out180[0] = \<const0> ;
assign probe_out181[0] = \<const0> ;
assign probe_out182[0] = \<const0> ;
assign probe_out183[0] = \<const0> ;
assign probe_out184[0] = \<const0> ;
assign probe_out185[0] = \<const0> ;
assign probe_out186[0] = \<const0> ;
assign probe_out187[0] = \<const0> ;
assign probe_out188[0] = \<const0> ;
assign probe_out189[0] = \<const0> ;
assign probe_out19[0] = \<const0> ;
assign probe_out190[0] = \<const0> ;
assign probe_out191[0] = \<const0> ;
assign probe_out192[0] = \<const0> ;
assign probe_out193[0] = \<const0> ;
assign probe_out194[0] = \<const0> ;
assign probe_out195[0] = \<const0> ;
assign probe_out196[0] = \<const0> ;
assign probe_out197[0] = \<const0> ;
assign probe_out198[0] = \<const0> ;
assign probe_out199[0] = \<const0> ;
assign probe_out2[0] = \<const0> ;
assign probe_out20[0] = \<const0> ;
assign probe_out200[0] = \<const0> ;
assign probe_out201[0] = \<const0> ;
assign probe_out202[0] = \<const0> ;
assign probe_out203[0] = \<const0> ;
assign probe_out204[0] = \<const0> ;
assign probe_out205[0] = \<const0> ;
assign probe_out206[0] = \<const0> ;
assign probe_out207[0] = \<const0> ;
assign probe_out208[0] = \<const0> ;
assign probe_out209[0] = \<const0> ;
assign probe_out21[0] = \<const0> ;
assign probe_out210[0] = \<const0> ;
assign probe_out211[0] = \<const0> ;
assign probe_out212[0] = \<const0> ;
assign probe_out213[0] = \<const0> ;
assign probe_out214[0] = \<const0> ;
assign probe_out215[0] = \<const0> ;
assign probe_out216[0] = \<const0> ;
assign probe_out217[0] = \<const0> ;
assign probe_out218[0] = \<const0> ;
assign probe_out219[0] = \<const0> ;
assign probe_out22[0] = \<const0> ;
assign probe_out220[0] = \<const0> ;
assign probe_out221[0] = \<const0> ;
assign probe_out222[0] = \<const0> ;
assign probe_out223[0] = \<const0> ;
assign probe_out224[0] = \<const0> ;
assign probe_out225[0] = \<const0> ;
assign probe_out226[0] = \<const0> ;
assign probe_out227[0] = \<const0> ;
assign probe_out228[0] = \<const0> ;
assign probe_out229[0] = \<const0> ;
assign probe_out23[0] = \<const0> ;
assign probe_out230[0] = \<const0> ;
assign probe_out231[0] = \<const0> ;
assign probe_out232[0] = \<const0> ;
assign probe_out233[0] = \<const0> ;
assign probe_out234[0] = \<const0> ;
assign probe_out235[0] = \<const0> ;
assign probe_out236[0] = \<const0> ;
assign probe_out237[0] = \<const0> ;
assign probe_out238[0] = \<const0> ;
assign probe_out239[0] = \<const0> ;
assign probe_out24[0] = \<const0> ;
assign probe_out240[0] = \<const0> ;
assign probe_out241[0] = \<const0> ;
assign probe_out242[0] = \<const0> ;
assign probe_out243[0] = \<const0> ;
assign probe_out244[0] = \<const0> ;
assign probe_out245[0] = \<const0> ;
assign probe_out246[0] = \<const0> ;
assign probe_out247[0] = \<const0> ;
assign probe_out248[0] = \<const0> ;
assign probe_out249[0] = \<const0> ;
assign probe_out25[0] = \<const0> ;
assign probe_out250[0] = \<const0> ;
assign probe_out251[0] = \<const0> ;
assign probe_out252[0] = \<const0> ;
assign probe_out253[0] = \<const0> ;
assign probe_out254[0] = \<const0> ;
assign probe_out255[0] = \<const0> ;
assign probe_out26[0] = \<const0> ;
assign probe_out27[0] = \<const0> ;
assign probe_out28[0] = \<const0> ;
assign probe_out29[0] = \<const0> ;
assign probe_out3[0] = \<const0> ;
assign probe_out30[0] = \<const0> ;
assign probe_out31[0] = \<const0> ;
assign probe_out32[0] = \<const0> ;
assign probe_out33[0] = \<const0> ;
assign probe_out34[0] = \<const0> ;
assign probe_out35[0] = \<const0> ;
assign probe_out36[0] = \<const0> ;
assign probe_out37[0] = \<const0> ;
assign probe_out38[0] = \<const0> ;
assign probe_out39[0] = \<const0> ;
assign probe_out4[0] = \<const0> ;
assign probe_out40[0] = \<const0> ;
assign probe_out41[0] = \<const0> ;
assign probe_out42[0] = \<const0> ;
assign probe_out43[0] = \<const0> ;
assign probe_out44[0] = \<const0> ;
assign probe_out45[0] = \<const0> ;
assign probe_out46[0] = \<const0> ;
assign probe_out47[0] = \<const0> ;
assign probe_out48[0] = \<const0> ;
assign probe_out49[0] = \<const0> ;
assign probe_out5[0] = \<const0> ;
assign probe_out50[0] = \<const0> ;
assign probe_out51[0] = \<const0> ;
assign probe_out52[0] = \<const0> ;
assign probe_out53[0] = \<const0> ;
assign probe_out54[0] = \<const0> ;
assign probe_out55[0] = \<const0> ;
assign probe_out56[0] = \<const0> ;
assign probe_out57[0] = \<const0> ;
assign probe_out58[0] = \<const0> ;
assign probe_out59[0] = \<const0> ;
assign probe_out6[0] = \<const0> ;
assign probe_out60[0] = \<const0> ;
assign probe_out61[0] = \<const0> ;
assign probe_out62[0] = \<const0> ;
assign probe_out63[0] = \<const0> ;
assign probe_out64[0] = \<const0> ;
assign probe_out65[0] = \<const0> ;
assign probe_out66[0] = \<const0> ;
assign probe_out67[0] = \<const0> ;
assign probe_out68[0] = \<const0> ;
assign probe_out69[0] = \<const0> ;
assign probe_out7[0] = \<const0> ;
assign probe_out70[0] = \<const0> ;
assign probe_out71[0] = \<const0> ;
assign probe_out72[0] = \<const0> ;
assign probe_out73[0] = \<const0> ;
assign probe_out74[0] = \<const0> ;
assign probe_out75[0] = \<const0> ;
assign probe_out76[0] = \<const0> ;
assign probe_out77[0] = \<const0> ;
assign probe_out78[0] = \<const0> ;
assign probe_out79[0] = \<const0> ;
assign probe_out8[0] = \<const0> ;
assign probe_out80[0] = \<const0> ;
assign probe_out81[0] = \<const0> ;
assign probe_out82[0] = \<const0> ;
assign probe_out83[0] = \<const0> ;
assign probe_out84[0] = \<const0> ;
assign probe_out85[0] = \<const0> ;
assign probe_out86[0] = \<const0> ;
assign probe_out87[0] = \<const0> ;
assign probe_out88[0] = \<const0> ;
assign probe_out89[0] = \<const0> ;
assign probe_out9[0] = \<const0> ;
assign probe_out90[0] = \<const0> ;
assign probe_out91[0] = \<const0> ;
assign probe_out92[0] = \<const0> ;
assign probe_out93[0] = \<const0> ;
assign probe_out94[0] = \<const0> ;
assign probe_out95[0] = \<const0> ;
assign probe_out96[0] = \<const0> ;
assign probe_out97[0] = \<const0> ;
assign probe_out98[0] = \<const0> ;
assign probe_out99[0] = \<const0> ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_decoder DECODER_INST
(.\Bus_Data_out_reg[11] (Bus_Data_out),
.E(DECODER_INST_n_4),
.Q({\bus_data_int_reg_n_0_[15] ,\bus_data_int_reg_n_0_[14] ,\bus_data_int_reg_n_0_[13] ,\bus_data_int_reg_n_0_[12] ,\bus_data_int_reg_n_0_[11] ,\bus_data_int_reg_n_0_[10] ,\bus_data_int_reg_n_0_[9] ,\bus_data_int_reg_n_0_[8] ,\bus_data_int_reg_n_0_[7] ,\bus_data_int_reg_n_0_[6] ,\bus_data_int_reg_n_0_[5] ,\bus_data_int_reg_n_0_[4] ,\bus_data_int_reg_n_0_[3] ,\bus_data_int_reg_n_0_[2] ,p_0_in,\bus_data_int_reg_n_0_[0] }),
.out(bus_clk),
.s_daddr_o(bus_addr),
.s_den_o(bus_den),
.s_do_i(bus_do),
.s_drdy_i(bus_drdy),
.s_dwe_o(bus_dwe),
.s_rst_o(bus_rst),
.\wr_en_reg[4]_0 (DECODER_INST_n_1),
.\wr_en_reg[4]_1 (DECODER_INST_n_2),
.\wr_en_reg[4]_2 (DECODER_INST_n_3));
GND GND
(.G(\<const0> ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_probe_in_one PROBE_IN_INST
(.D({probe_in3,probe_in2,probe_in1,probe_in0}),
.E(DECODER_INST_n_4),
.Q(Bus_Data_out),
.clk(clk),
.out(bus_clk),
.s_daddr_o(bus_addr[2:0]),
.s_den_o(bus_den),
.s_dwe_o(bus_dwe),
.s_rst_o(bus_rst),
.\wr_en[4]_i_3 (DECODER_INST_n_1),
.\wr_en[4]_i_4 (DECODER_INST_n_3),
.\wr_en[4]_i_5 (DECODER_INST_n_2));
(* C_BUILD_REVISION = "0" *)
(* C_CORE_INFO1 = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
(* C_CORE_INFO2 = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
(* C_CORE_MAJOR_VER = "2" *)
(* C_CORE_MINOR_VER = "0" *)
(* C_CORE_TYPE = "2" *)
(* C_CSE_DRV_VER = "1" *)
(* C_MAJOR_VERSION = "2013" *)
(* C_MINOR_VERSION = "1" *)
(* C_NEXT_SLAVE = "0" *)
(* C_PIPE_IFACE = "0" *)
(* C_USE_TEST_REG = "1" *)
(* C_XDEVICEFAMILY = "kintex7" *)
(* C_XSDB_SLAVE_TYPE = "33" *)
(* DONT_TOUCH *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs U_XSDB_SLAVE
(.s_daddr_o(bus_addr),
.s_dclk_o(bus_clk),
.s_den_o(bus_den),
.s_di_o(bus_di),
.s_do_i(bus_do),
.s_drdy_i(bus_drdy),
.s_dwe_o(bus_dwe),
.s_rst_o(bus_rst),
.sl_iport_i(sl_iport0),
.sl_oport_o(sl_oport0));
FDRE \bus_data_int_reg[0]
(.C(bus_clk),
.CE(1'b1),
.D(bus_di[0]),
.Q(\bus_data_int_reg_n_0_[0] ),
.R(1'b0));
FDRE \bus_data_int_reg[10]
(.C(bus_clk),
.CE(1'b1),
.D(bus_di[10]),
.Q(\bus_data_int_reg_n_0_[10] ),
.R(1'b0));
FDRE \bus_data_int_reg[11]
(.C(bus_clk),
.CE(1'b1),
.D(bus_di[11]),
.Q(\bus_data_int_reg_n_0_[11] ),
.R(1'b0));
FDRE \bus_data_int_reg[12]
(.C(bus_clk),
.CE(1'b1),
.D(bus_di[12]),
.Q(\bus_data_int_reg_n_0_[12] ),
.R(1'b0));
FDRE \bus_data_int_reg[13]
(.C(bus_clk),
.CE(1'b1),
.D(bus_di[13]),
.Q(\bus_data_int_reg_n_0_[13] ),
.R(1'b0));
FDRE \bus_data_int_reg[14]
(.C(bus_clk),
.CE(1'b1),
.D(bus_di[14]),
.Q(\bus_data_int_reg_n_0_[14] ),
.R(1'b0));
FDRE \bus_data_int_reg[15]
(.C(bus_clk),
.CE(1'b1),
.D(bus_di[15]),
.Q(\bus_data_int_reg_n_0_[15] ),
.R(1'b0));
FDRE \bus_data_int_reg[1]
(.C(bus_clk),
.CE(1'b1),
.D(bus_di[1]),
.Q(p_0_in),
.R(1'b0));
FDRE \bus_data_int_reg[2]
(.C(bus_clk),
.CE(1'b1),
.D(bus_di[2]),
.Q(\bus_data_int_reg_n_0_[2] ),
.R(1'b0));
FDRE \bus_data_int_reg[3]
(.C(bus_clk),
.CE(1'b1),
.D(bus_di[3]),
.Q(\bus_data_int_reg_n_0_[3] ),
.R(1'b0));
FDRE \bus_data_int_reg[4]
(.C(bus_clk),
.CE(1'b1),
.D(bus_di[4]),
.Q(\bus_data_int_reg_n_0_[4] ),
.R(1'b0));
FDRE \bus_data_int_reg[5]
(.C(bus_clk),
.CE(1'b1),
.D(bus_di[5]),
.Q(\bus_data_int_reg_n_0_[5] ),
.R(1'b0));
FDRE \bus_data_int_reg[6]
(.C(bus_clk),
.CE(1'b1),
.D(bus_di[6]),
.Q(\bus_data_int_reg_n_0_[6] ),
.R(1'b0));
FDRE \bus_data_int_reg[7]
(.C(bus_clk),
.CE(1'b1),
.D(bus_di[7]),
.Q(\bus_data_int_reg_n_0_[7] ),
.R(1'b0));
FDRE \bus_data_int_reg[8]
(.C(bus_clk),
.CE(1'b1),
.D(bus_di[8]),
.Q(\bus_data_int_reg_n_0_[8] ),
.R(1'b0));
FDRE \bus_data_int_reg[9]
(.C(bus_clk),
.CE(1'b1),
.D(bus_di[9]),
.Q(\bus_data_int_reg_n_0_[9] ),
.R(1'b0));
endmodule
(* C_BUILD_REVISION = "0" *) (* C_CORE_INFO1 = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) (* C_CORE_INFO2 = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
(* C_CORE_MAJOR_VER = "2" *) (* C_CORE_MINOR_VER = "0" *) (* C_CORE_TYPE = "2" *)
(* C_CSE_DRV_VER = "1" *) (* C_MAJOR_VERSION = "2013" *) (* C_MINOR_VERSION = "1" *)
(* C_NEXT_SLAVE = "0" *) (* C_PIPE_IFACE = "0" *) (* C_USE_TEST_REG = "1" *)
(* C_XDEVICEFAMILY = "kintex7" *) (* C_XSDB_SLAVE_TYPE = "33" *) (* dont_touch = "true" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs
(s_rst_o,
s_dclk_o,
s_den_o,
s_dwe_o,
s_daddr_o,
s_di_o,
sl_oport_o,
s_do_i,
sl_iport_i,
s_drdy_i);
output s_rst_o;
output s_dclk_o;
output s_den_o;
output s_dwe_o;
output [16:0]s_daddr_o;
output [15:0]s_di_o;
output [16:0]sl_oport_o;
input [15:0]s_do_i;
input [36:0]sl_iport_i;
input s_drdy_i;
wire [8:0]reg_do;
wire \reg_do[10]_i_1_n_0 ;
wire \reg_do[10]_i_2_n_0 ;
wire \reg_do[15]_i_1_n_0 ;
wire \reg_do[1]_i_2_n_0 ;
wire \reg_do[2]_i_1_n_0 ;
wire \reg_do[3]_i_1_n_0 ;
wire \reg_do[4]_i_1_n_0 ;
wire \reg_do[5]_i_2_n_0 ;
wire \reg_do[6]_i_1_n_0 ;
wire \reg_do[7]_i_1_n_0 ;
wire \reg_do[8]_i_2_n_0 ;
wire \reg_do[9]_i_1_n_0 ;
wire \reg_do_reg_n_0_[0] ;
wire \reg_do_reg_n_0_[10] ;
wire \reg_do_reg_n_0_[11] ;
wire \reg_do_reg_n_0_[12] ;
wire \reg_do_reg_n_0_[13] ;
wire \reg_do_reg_n_0_[14] ;
wire \reg_do_reg_n_0_[15] ;
wire \reg_do_reg_n_0_[1] ;
wire \reg_do_reg_n_0_[2] ;
wire \reg_do_reg_n_0_[3] ;
wire \reg_do_reg_n_0_[4] ;
wire \reg_do_reg_n_0_[5] ;
wire \reg_do_reg_n_0_[6] ;
wire \reg_do_reg_n_0_[7] ;
wire \reg_do_reg_n_0_[8] ;
wire \reg_do_reg_n_0_[9] ;
wire reg_drdy;
wire reg_drdy_i_1_n_0;
wire [15:0]reg_test;
wire reg_test0;
wire s_den_o;
wire s_den_o_INST_0_i_1_n_0;
wire [15:0]s_do_i;
wire s_drdy_i;
wire [36:0]sl_iport_i;
wire [16:0]sl_oport_o;
assign s_daddr_o[16:0] = sl_iport_i[20:4];
assign s_dclk_o = sl_iport_i[1];
assign s_di_o[15:0] = sl_iport_i[36:21];
assign s_dwe_o = sl_iport_i[3];
assign s_rst_o = sl_iport_i[0];
LUT6 #(
.INIT(64'hBAAAFFFFAAAAAAAA))
\reg_do[0]_i_1
(.I0(\reg_do[5]_i_2_n_0 ),
.I1(sl_iport_i[4]),
.I2(reg_test[0]),
.I3(sl_iport_i[6]),
.I4(sl_iport_i[5]),
.I5(sl_iport_i[8]),
.O(reg_do[0]));
LUT3 #(
.INIT(8'h40))
\reg_do[10]_i_1
(.I0(sl_iport_i[5]),
.I1(\reg_do[8]_i_2_n_0 ),
.I2(sl_iport_i[4]),
.O(\reg_do[10]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'h0800))
\reg_do[10]_i_2
(.I0(\reg_do[8]_i_2_n_0 ),
.I1(sl_iport_i[5]),
.I2(sl_iport_i[4]),
.I3(reg_test[10]),
.O(\reg_do[10]_i_2_n_0 ));
LUT3 #(
.INIT(8'hF7))
\reg_do[15]_i_1
(.I0(\reg_do[8]_i_2_n_0 ),
.I1(sl_iport_i[5]),
.I2(sl_iport_i[4]),
.O(\reg_do[15]_i_1_n_0 ));
LUT5 #(
.INIT(32'h20220000))
\reg_do[1]_i_1
(.I0(sl_iport_i[5]),
.I1(sl_iport_i[4]),
.I2(reg_test[1]),
.I3(sl_iport_i[6]),
.I4(\reg_do[1]_i_2_n_0 ),
.O(reg_do[1]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h00800000))
\reg_do[1]_i_2
(.I0(sl_iport_i[8]),
.I1(sl_iport_i[10]),
.I2(sl_iport_i[11]),
.I3(sl_iport_i[7]),
.I4(sl_iport_i[9]),
.O(\reg_do[1]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'h0800))
\reg_do[2]_i_1
(.I0(\reg_do[8]_i_2_n_0 ),
.I1(sl_iport_i[5]),
.I2(sl_iport_i[4]),
.I3(reg_test[2]),
.O(\reg_do[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h0800))
\reg_do[3]_i_1
(.I0(\reg_do[8]_i_2_n_0 ),
.I1(sl_iport_i[5]),
.I2(sl_iport_i[4]),
.I3(reg_test[3]),
.O(\reg_do[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'h0800))
\reg_do[4]_i_1
(.I0(\reg_do[8]_i_2_n_0 ),
.I1(sl_iport_i[5]),
.I2(sl_iport_i[4]),
.I3(reg_test[4]),
.O(\reg_do[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF00800044))
\reg_do[5]_i_1
(.I0(sl_iport_i[6]),
.I1(sl_iport_i[8]),
.I2(reg_test[5]),
.I3(sl_iport_i[4]),
.I4(sl_iport_i[5]),
.I5(\reg_do[5]_i_2_n_0 ),
.O(reg_do[5]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'hBFFFFFFC))
\reg_do[5]_i_2
(.I0(sl_iport_i[7]),
.I1(sl_iport_i[8]),
.I2(sl_iport_i[11]),
.I3(sl_iport_i[10]),
.I4(sl_iport_i[9]),
.O(\reg_do[5]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h0800))
\reg_do[6]_i_1
(.I0(\reg_do[8]_i_2_n_0 ),
.I1(sl_iport_i[5]),
.I2(sl_iport_i[4]),
.I3(reg_test[6]),
.O(\reg_do[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'h0800))
\reg_do[7]_i_1
(.I0(\reg_do[8]_i_2_n_0 ),
.I1(sl_iport_i[5]),
.I2(sl_iport_i[4]),
.I3(reg_test[7]),
.O(\reg_do[7]_i_1_n_0 ));
LUT4 #(
.INIT(16'h2F00))
\reg_do[8]_i_1
(.I0(reg_test[8]),
.I1(sl_iport_i[4]),
.I2(sl_iport_i[5]),
.I3(\reg_do[8]_i_2_n_0 ),
.O(reg_do[8]));
LUT6 #(
.INIT(64'h2000000000000000))
\reg_do[8]_i_2
(.I0(sl_iport_i[9]),
.I1(sl_iport_i[7]),
.I2(sl_iport_i[11]),
.I3(sl_iport_i[10]),
.I4(sl_iport_i[8]),
.I5(sl_iport_i[6]),
.O(\reg_do[8]_i_2_n_0 ));
LUT5 #(
.INIT(32'h0C008000))
\reg_do[9]_i_1
(.I0(reg_test[9]),
.I1(\reg_do[1]_i_2_n_0 ),
.I2(sl_iport_i[6]),
.I3(sl_iport_i[5]),
.I4(sl_iport_i[4]),
.O(\reg_do[9]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\reg_do_reg[0]
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(reg_do[0]),
.Q(\reg_do_reg_n_0_[0] ),
.R(1'b0));
FDSE #(
.INIT(1'b0))
\reg_do_reg[10]
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(\reg_do[10]_i_2_n_0 ),
.Q(\reg_do_reg_n_0_[10] ),
.S(\reg_do[10]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\reg_do_reg[11]
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(reg_test[11]),
.Q(\reg_do_reg_n_0_[11] ),
.R(\reg_do[15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\reg_do_reg[12]
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(reg_test[12]),
.Q(\reg_do_reg_n_0_[12] ),
.R(\reg_do[15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\reg_do_reg[13]
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(reg_test[13]),
.Q(\reg_do_reg_n_0_[13] ),
.R(\reg_do[15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\reg_do_reg[14]
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(reg_test[14]),
.Q(\reg_do_reg_n_0_[14] ),
.R(\reg_do[15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\reg_do_reg[15]
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(reg_test[15]),
.Q(\reg_do_reg_n_0_[15] ),
.R(\reg_do[15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\reg_do_reg[1]
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(reg_do[1]),
.Q(\reg_do_reg_n_0_[1] ),
.R(1'b0));
FDSE #(
.INIT(1'b0))
\reg_do_reg[2]
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(\reg_do[2]_i_1_n_0 ),
.Q(\reg_do_reg_n_0_[2] ),
.S(\reg_do[10]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\reg_do_reg[3]
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(\reg_do[3]_i_1_n_0 ),
.Q(\reg_do_reg_n_0_[3] ),
.S(\reg_do[10]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\reg_do_reg[4]
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(\reg_do[4]_i_1_n_0 ),
.Q(\reg_do_reg_n_0_[4] ),
.S(\reg_do[10]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\reg_do_reg[5]
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(reg_do[5]),
.Q(\reg_do_reg_n_0_[5] ),
.R(1'b0));
FDSE #(
.INIT(1'b0))
\reg_do_reg[6]
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(\reg_do[6]_i_1_n_0 ),
.Q(\reg_do_reg_n_0_[6] ),
.S(\reg_do[10]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\reg_do_reg[7]
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(\reg_do[7]_i_1_n_0 ),
.Q(\reg_do_reg_n_0_[7] ),
.S(\reg_do[10]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\reg_do_reg[8]
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(reg_do[8]),
.Q(\reg_do_reg_n_0_[8] ),
.R(1'b0));
FDSE #(
.INIT(1'b0))
\reg_do_reg[9]
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(\reg_do[9]_i_1_n_0 ),
.Q(\reg_do_reg_n_0_[9] ),
.S(\reg_do[10]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0000000080000000))
reg_drdy_i_1
(.I0(sl_iport_i[2]),
.I1(s_den_o_INST_0_i_1_n_0),
.I2(sl_iport_i[12]),
.I3(sl_iport_i[13]),
.I4(sl_iport_i[14]),
.I5(sl_iport_i[0]),
.O(reg_drdy_i_1_n_0));
FDRE #(
.INIT(1'b0))
reg_drdy_reg
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(reg_drdy_i_1_n_0),
.Q(reg_drdy),
.R(1'b0));
LUT6 #(
.INIT(64'h8000000000000000))
\reg_test[15]_i_1
(.I0(sl_iport_i[3]),
.I1(sl_iport_i[2]),
.I2(sl_iport_i[14]),
.I3(sl_iport_i[13]),
.I4(sl_iport_i[12]),
.I5(s_den_o_INST_0_i_1_n_0),
.O(reg_test0));
FDRE #(
.INIT(1'b0))
\reg_test_reg[0]
(.C(sl_iport_i[1]),
.CE(reg_test0),
.D(sl_iport_i[21]),
.Q(reg_test[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\reg_test_reg[10]
(.C(sl_iport_i[1]),
.CE(reg_test0),
.D(sl_iport_i[31]),
.Q(reg_test[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\reg_test_reg[11]
(.C(sl_iport_i[1]),
.CE(reg_test0),
.D(sl_iport_i[32]),
.Q(reg_test[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\reg_test_reg[12]
(.C(sl_iport_i[1]),
.CE(reg_test0),
.D(sl_iport_i[33]),
.Q(reg_test[12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\reg_test_reg[13]
(.C(sl_iport_i[1]),
.CE(reg_test0),
.D(sl_iport_i[34]),
.Q(reg_test[13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\reg_test_reg[14]
(.C(sl_iport_i[1]),
.CE(reg_test0),
.D(sl_iport_i[35]),
.Q(reg_test[14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\reg_test_reg[15]
(.C(sl_iport_i[1]),
.CE(reg_test0),
.D(sl_iport_i[36]),
.Q(reg_test[15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\reg_test_reg[1]
(.C(sl_iport_i[1]),
.CE(reg_test0),
.D(sl_iport_i[22]),
.Q(reg_test[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\reg_test_reg[2]
(.C(sl_iport_i[1]),
.CE(reg_test0),
.D(sl_iport_i[23]),
.Q(reg_test[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\reg_test_reg[3]
(.C(sl_iport_i[1]),
.CE(reg_test0),
.D(sl_iport_i[24]),
.Q(reg_test[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\reg_test_reg[4]
(.C(sl_iport_i[1]),
.CE(reg_test0),
.D(sl_iport_i[25]),
.Q(reg_test[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\reg_test_reg[5]
(.C(sl_iport_i[1]),
.CE(reg_test0),
.D(sl_iport_i[26]),
.Q(reg_test[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\reg_test_reg[6]
(.C(sl_iport_i[1]),
.CE(reg_test0),
.D(sl_iport_i[27]),
.Q(reg_test[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\reg_test_reg[7]
(.C(sl_iport_i[1]),
.CE(reg_test0),
.D(sl_iport_i[28]),
.Q(reg_test[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\reg_test_reg[8]
(.C(sl_iport_i[1]),
.CE(reg_test0),
.D(sl_iport_i[29]),
.Q(reg_test[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\reg_test_reg[9]
(.C(sl_iport_i[1]),
.CE(reg_test0),
.D(sl_iport_i[30]),
.Q(reg_test[9]),
.R(1'b0));
LUT5 #(
.INIT(32'h2AAAAAAA))
s_den_o_INST_0
(.I0(sl_iport_i[2]),
.I1(sl_iport_i[14]),
.I2(sl_iport_i[13]),
.I3(sl_iport_i[12]),
.I4(s_den_o_INST_0_i_1_n_0),
.O(s_den_o));
LUT6 #(
.INIT(64'h8000000000000000))
s_den_o_INST_0_i_1
(.I0(sl_iport_i[15]),
.I1(sl_iport_i[16]),
.I2(sl_iport_i[17]),
.I3(sl_iport_i[18]),
.I4(sl_iport_i[20]),
.I5(sl_iport_i[19]),
.O(s_den_o_INST_0_i_1_n_0));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT2 #(
.INIT(4'hE))
\sl_oport_o[0]_INST_0
(.I0(s_drdy_i),
.I1(reg_drdy),
.O(sl_oport_o[0]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'hAC))
\sl_oport_o[10]_INST_0
(.I0(\reg_do_reg_n_0_[9] ),
.I1(s_do_i[9]),
.I2(reg_drdy),
.O(sl_oport_o[10]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'hAC))
\sl_oport_o[11]_INST_0
(.I0(\reg_do_reg_n_0_[10] ),
.I1(s_do_i[10]),
.I2(reg_drdy),
.O(sl_oport_o[11]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'hAC))
\sl_oport_o[12]_INST_0
(.I0(\reg_do_reg_n_0_[11] ),
.I1(s_do_i[11]),
.I2(reg_drdy),
.O(sl_oport_o[12]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'hAC))
\sl_oport_o[13]_INST_0
(.I0(\reg_do_reg_n_0_[12] ),
.I1(s_do_i[12]),
.I2(reg_drdy),
.O(sl_oport_o[13]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'hAC))
\sl_oport_o[14]_INST_0
(.I0(\reg_do_reg_n_0_[13] ),
.I1(s_do_i[13]),
.I2(reg_drdy),
.O(sl_oport_o[14]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'hAC))
\sl_oport_o[15]_INST_0
(.I0(\reg_do_reg_n_0_[14] ),
.I1(s_do_i[14]),
.I2(reg_drdy),
.O(sl_oport_o[15]));
LUT3 #(
.INIT(8'hAC))
\sl_oport_o[16]_INST_0
(.I0(\reg_do_reg_n_0_[15] ),
.I1(s_do_i[15]),
.I2(reg_drdy),
.O(sl_oport_o[16]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT3 #(
.INIT(8'hAC))
\sl_oport_o[1]_INST_0
(.I0(\reg_do_reg_n_0_[0] ),
.I1(s_do_i[0]),
.I2(reg_drdy),
.O(sl_oport_o[1]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT3 #(
.INIT(8'hAC))
\sl_oport_o[2]_INST_0
(.I0(\reg_do_reg_n_0_[1] ),
.I1(s_do_i[1]),
.I2(reg_drdy),
.O(sl_oport_o[2]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT3 #(
.INIT(8'hAC))
\sl_oport_o[3]_INST_0
(.I0(\reg_do_reg_n_0_[2] ),
.I1(s_do_i[2]),
.I2(reg_drdy),
.O(sl_oport_o[3]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'hAC))
\sl_oport_o[4]_INST_0
(.I0(\reg_do_reg_n_0_[3] ),
.I1(s_do_i[3]),
.I2(reg_drdy),
.O(sl_oport_o[4]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'hAC))
\sl_oport_o[5]_INST_0
(.I0(\reg_do_reg_n_0_[4] ),
.I1(s_do_i[4]),
.I2(reg_drdy),
.O(sl_oport_o[5]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'hAC))
\sl_oport_o[6]_INST_0
(.I0(\reg_do_reg_n_0_[5] ),
.I1(s_do_i[5]),
.I2(reg_drdy),
.O(sl_oport_o[6]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'hAC))
\sl_oport_o[7]_INST_0
(.I0(\reg_do_reg_n_0_[6] ),
.I1(s_do_i[6]),
.I2(reg_drdy),
.O(sl_oport_o[7]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'hAC))
\sl_oport_o[8]_INST_0
(.I0(\reg_do_reg_n_0_[7] ),
.I1(s_do_i[7]),
.I2(reg_drdy),
.O(sl_oport_o[8]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'hAC))
\sl_oport_o[9]_INST_0
(.I0(\reg_do_reg_n_0_[8] ),
.I1(s_do_i[8]),
.I2(reg_drdy),
.O(sl_oport_o[9]));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
(** * Stlc: The Simply Typed Lambda-Calculus *)
Require Export Types.
(* ###################################################################### *)
(** * The Simply Typed Lambda-Calculus *)
(** The simply typed lambda-calculus (STLC) is a tiny core calculus
embodying the key concept of _functional abstraction_, which shows
up in pretty much every real-world programming language in some
form (functions, procedures, methods, etc.).
We will follow exactly the same pattern as in the previous
chapter when formalizing this calculus (syntax, small-step
semantics, typing rules) and its main properties (progress and
preservation). The new technical challenges (which will take some
work to deal with) all arise from the mechanisms of _variable
binding_ and _substitution_. *)
(* ###################################################################### *)
(** ** Overview *)
(** The STLC is built on some collection of _base types_ -- booleans,
numbers, strings, etc. The exact choice of base types doesn't
matter -- the construction of the language and its theoretical
properties work out pretty much the same -- so for the sake of
brevity let's take just [Bool] for the moment. At the end of the
chapter we'll see how to add more base types, and in later
chapters we'll enrich the pure STLC with other useful constructs
like pairs, records, subtyping, and mutable state.
Starting from the booleans, we add three things:
- variables
- function abstractions
- application
This gives us the following collection of abstract syntax
constructors (written out here in informal BNF notation -- we'll
formalize it below).
*)
(** Informal concrete syntax:
t ::= x variable
| \x:T1.t2 abstraction
| t1 t2 application
| true constant true
| false constant false
| if t1 then t2 else t3 conditional
*)
(** The [\] symbol (backslash, in ascii) in a function abstraction
[\x:T1.t2] is generally written as a greek letter "lambda" (hence
the name of the calculus). The variable [x] is called the
_parameter_ to the function; the term [t2] is its _body_. The
annotation [:T] specifies the type of arguments that the function
can be applied to. *)
(** Some examples:
- [\x:Bool. x]
The identity function for booleans.
- [(\x:Bool. x) true]
The identity function for booleans, applied to the boolean [true].
- [\x:Bool. if x then false else true]
The boolean "not" function.
- [\x:Bool. true]
The constant function that takes every (boolean) argument to
[true]. *)
(**
- [\x:Bool. \y:Bool. x]
A two-argument function that takes two booleans and returns
the first one. (Note that, as in Coq, a two-argument function
is really a one-argument function whose body is also a
one-argument function.)
- [(\x:Bool. \y:Bool. x) false true]
A two-argument function that takes two booleans and returns
the first one, applied to the booleans [false] and [true].
Note that, as in Coq, application associates to the left --
i.e., this expression is parsed as [((\x:Bool. \y:Bool. x)
false) true].
- [\f:Bool->Bool. f (f true)]
A higher-order function that takes a _function_ [f] (from
booleans to booleans) as an argument, applies [f] to [true],
and applies [f] again to the result.
- [(\f:Bool->Bool. f (f true)) (\x:Bool. false)]
The same higher-order function, applied to the constantly
[false] function. *)
(** As the last several examples show, the STLC is a language of
_higher-order_ functions: we can write down functions that take
other functions as arguments and/or return other functions as
results.
Another point to note is that the STLC doesn't provide any
primitive syntax for defining _named_ functions -- all functions
are "anonymous." We'll see in chapter [MoreStlc] that it is easy
to add named functions to what we've got -- indeed, the
fundamental naming and binding mechanisms are exactly the same.
The _types_ of the STLC include [Bool], which classifies the
boolean constants [true] and [false] as well as more complex
computations that yield booleans, plus _arrow types_ that classify
functions. *)
(**
T ::= Bool
| T1 -> T2
For example:
- [\x:Bool. false] has type [Bool->Bool]
- [\x:Bool. x] has type [Bool->Bool]
- [(\x:Bool. x) true] has type [Bool]
- [\x:Bool. \y:Bool. x] has type [Bool->Bool->Bool] (i.e. [Bool -> (Bool->Bool)])
- [(\x:Bool. \y:Bool. x) false] has type [Bool->Bool]
- [(\x:Bool. \y:Bool. x) false true] has type [Bool]
*)
(* ###################################################################### *)
(** ** Syntax *)
Module STLC.
(* ################################### *)
(** *** Types *)
Inductive ty : Type :=
| TBool : ty
| TArrow : ty -> ty -> ty.
(* ################################### *)
(** *** Terms *)
Inductive tm : Type :=
| tvar : id -> tm
| tapp : tm -> tm -> tm
| tabs : id -> ty -> tm -> tm
| ttrue : tm
| tfalse : tm
| tif : tm -> tm -> tm -> tm.
Tactic Notation "t_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "tvar" | Case_aux c "tapp"
| Case_aux c "tabs" | Case_aux c "ttrue"
| Case_aux c "tfalse" | Case_aux c "tif" ].
(** Note that an abstraction [\x:T.t] (formally, [tabs x T t]) is
always annotated with the type [T] of its parameter, in contrast
to Coq (and other functional languages like ML, Haskell, etc.),
which use _type inference_ to fill in missing annotations. We're
not considering type inference here, to keep things simple. *)
(** Some examples... *)
Definition x := (Id 0).
Definition y := (Id 1).
Definition z := (Id 2).
Hint Unfold x.
Hint Unfold y.
Hint Unfold z.
(** [idB = \x:Bool. x] *)
Notation idB :=
(tabs x TBool (tvar x)).
(** [idBB = \x:Bool->Bool. x] *)
Notation idBB :=
(tabs x (TArrow TBool TBool) (tvar x)).
(** [idBBBB = \x:(Bool->Bool) -> (Bool->Bool). x] *)
Notation idBBBB :=
(tabs x (TArrow (TArrow TBool TBool)
(TArrow TBool TBool))
(tvar x)).
(** [k = \x:Bool. \y:Bool. x] *)
Notation k := (tabs x TBool (tabs y TBool (tvar x))).
(** [notB = \x:Bool. if x then false else true] *)
Notation notB := (tabs x TBool (tif (tvar x) tfalse ttrue)).
(** (We write these as [Notation]s rather than [Definition]s to make
things easier for [auto].) *)
(* ###################################################################### *)
(** ** Operational Semantics *)
(** To define the small-step semantics of STLC terms, we begin -- as
always -- by defining the set of values. Next, we define the
critical notions of _free variables_ and _substitution_, which are
used in the reduction rule for application expressions. And
finally we give the small-step relation itself. *)
(* ################################### *)
(** *** Values *)
(** To define the values of the STLC, we have a few cases to consider.
First, for the boolean part of the language, the situation is
clear: [true] and [false] are the only values. An [if]
expression is never a value. *)
(** Second, an application is clearly not a value: It represents a
function being invoked on some argument, which clearly still has
work left to do. *)
(** Third, for abstractions, we have a choice:
- We can say that [\x:T.t1] is a value only when [t1] is a
value -- i.e., only if the function's body has been
reduced (as much as it can be without knowing what argument it
is going to be applied to).
- Or we can say that [\x:T.t1] is always a value, no matter
whether [t1] is one or not -- in other words, we can say that
reduction stops at abstractions.
Coq, in its built-in functional programming langauge, makes the
first choice -- for example,
Eval simpl in (fun x:bool => 3 + 4)
yields [fun x:bool => 7].
Most real-world functional programming languages make the second
choice -- reduction of a function's body only begins when the
function is actually applied to an argument. We also make the
second choice here. *)
Inductive value : tm -> Prop :=
| v_abs : forall x T t,
value (tabs x T t)
| v_true :
value ttrue
| v_false :
value tfalse.
Hint Constructors value.
(** Finally, we must consider what constitutes a _complete_ program.
Intuitively, a "complete" program must not refer to any undefined
variables. We'll see shortly how to define the "free" variables
in a STLC term. A program is "closed", that is, it contains no
free variables.
*)
(** Having made the choice not to reduce under abstractions,
we don't need to worry about whether variables are values, since
we'll always be reducing programs "from the outside in," and that
means the [step] relation will always be working with closed
terms (ones with no free variables). *)
(* ###################################################################### *)
(** *** Substitution *)
(** Now we come to the heart of the STLC: the operation of
substituting one term for a variable in another term.
This operation will be used below to define the operational
semantics of function application, where we will need to
substitute the argument term for the function parameter in the
function's body. For example, we reduce
(\x:Bool. if x then true else x) false
to
if false then true else false
]]
by substituting [false] for the parameter [x] in the body of the
function.
In general, we need to be able to substitute some given
term [s] for occurrences of some variable [x] in another term [t].
In informal discussions, this is usually written [ [x:=s]t ] and
pronounced "substitute [x] with [s] in [t]." *)
(** Here are some examples:
- [[x:=true] (if x then x else false)] yields [if true then true else false]
- [[x:=true] x] yields [true]
- [[x:=true] (if x then x else y)] yields [if true then true else y]
- [[x:=true] y] yields [y]
- [[x:=true] false] yields [false] (vacuous substitution)
- [[x:=true] (\y:Bool. if y then x else false)] yields [\y:Bool. if y then true else false]
- [[x:=true] (\y:Bool. x)] yields [\y:Bool. true]
- [[x:=true] (\y:Bool. y)] yields [\y:Bool. y]
- [[x:=true] (\x:Bool. x)] yields [\x:Bool. x]
The last example is very important: substituting [x] with [true] in
[\x:Bool. x] does _not_ yield [\x:Bool. true]! The reason for
this is that the [x] in the body of [\x:Bool. x] is _bound_ by the
abstraction: it is a new, local name that just happens to be
spelled the same as some global name [x]. *)
(** Here is the definition, informally...
[x:=s]x = s
[x:=s]y = y if x <> y
[x:=s](\x:T11.t12) = \x:T11. t12
[x:=s](\y:T11.t12) = \y:T11. [x:=s]t12 if x <> y
[x:=s](t1 t2) = ([x:=s]t1) ([x:=s]t2)
[x:=s]true = true
[x:=s]false = false
[x:=s](if t1 then t2 else t3) =
if [x:=s]t1 then [x:=s]t2 else [x:=s]t3
]]
*)
(** ... and formally: *)
Reserved Notation "'[' x ':=' s ']' t" (at level 20).
Fixpoint subst (x:id) (s:tm) (t:tm) : tm :=
match t with
| tvar x' =>
if eq_id_dec x x' then s else t
| tabs x' T t1 =>
tabs x' T (if eq_id_dec x x' then t1 else ([x:=s] t1))
| tapp t1 t2 =>
tapp ([x:=s] t1) ([x:=s] t2)
| ttrue =>
ttrue
| tfalse =>
tfalse
| tif t1 t2 t3 =>
tif ([x:=s] t1) ([x:=s] t2) ([x:=s] t3)
end
where "'[' x ':=' s ']' t" := (subst x s t).
(** _Technical note_: Substitution becomes trickier to define if we
consider the case where [s], the term being substituted for a
variable in some other term, may itself contain free variables.
Since we are only interested here in defining the [step] relation
on closed terms (i.e., terms like [\x:Bool. x], that do not mention
variables are not bound by some enclosing lambda), we can skip
this extra complexity here, but it must be dealt with when
formalizing richer languages. *)
(** *** *)
(** **** Exercise: 3 stars (substi) *)
(** The definition that we gave above uses Coq's [Fixpoint] facility
to define substitution as a _function_. Suppose, instead, we
wanted to define substitution as an inductive _relation_ [substi].
We've begun the definition by providing the [Inductive] header and
one of the constructors; your job is to fill in the rest of the
constructors. *)
Inductive substi (s:tm) (x:id) : tm -> tm -> Prop :=
| s_var1 :
substi s x (tvar x) s
(* FILL IN HERE *)
.
Hint Constructors substi.
Theorem substi_correct : forall s x t t',
[x:=s]t = t' <-> substi s x t t'.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ################################### *)
(** *** Reduction *)
(** The small-step reduction relation for STLC now follows the same
pattern as the ones we have seen before. Intuitively, to reduce a
function application, we first reduce its left-hand side until it
becomes a literal function; then we reduce its right-hand
side (the argument) until it is also a value; and finally we
substitute the argument for the bound variable in the body of the
function. This last rule, written informally as
(\x:T.t12) v2 ==> [x:=v2]t12
is traditionally called "beta-reduction". *)
(**
value v2
---------------------------- (ST_AppAbs)
(\x:T.t12) v2 ==> [x:=v2]t12
t1 ==> t1'
---------------- (ST_App1)
t1 t2 ==> t1' t2
value v1
t2 ==> t2'
---------------- (ST_App2)
v1 t2 ==> v1 t2'
*)
(** ... plus the usual rules for booleans:
-------------------------------- (ST_IfTrue)
(if true then t1 else t2) ==> t1
--------------------------------- (ST_IfFalse)
(if false then t1 else t2) ==> t2
t1 ==> t1'
---------------------------------------------------- (ST_If)
(if t1 then t2 else t3) ==> (if t1' then t2 else t3)
*)
Reserved Notation "t1 '==>' t2" (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_AppAbs : forall x T t12 v2,
value v2 ->
(tapp (tabs x T t12) v2) ==> [x:=v2]t12
| ST_App1 : forall t1 t1' t2,
t1 ==> t1' ->
tapp t1 t2 ==> tapp t1' t2
| ST_App2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
tapp v1 t2 ==> tapp v1 t2'
| ST_IfTrue : forall t1 t2,
(tif ttrue t1 t2) ==> t1
| ST_IfFalse : forall t1 t2,
(tif tfalse t1 t2) ==> t2
| ST_If : forall t1 t1' t2 t3,
t1 ==> t1' ->
(tif t1 t2 t3) ==> (tif t1' t2 t3)
where "t1 '==>' t2" := (step t1 t2).
Tactic Notation "step_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ST_AppAbs" | Case_aux c "ST_App1"
| Case_aux c "ST_App2" | Case_aux c "ST_IfTrue"
| Case_aux c "ST_IfFalse" | Case_aux c "ST_If" ].
Hint Constructors step.
Notation multistep := (multi step).
Notation "t1 '==>*' t2" := (multistep t1 t2) (at level 40).
(* ##################################### *)
(* ##################################### *)
(** *** Examples *)
(** Example:
((\x:Bool->Bool. x) (\x:Bool. x)) ==>* (\x:Bool. x)
i.e.
(idBB idB) ==>* idB
*)
Lemma step_example1 :
(tapp idBB idB) ==>* idB.
Proof.
eapply multi_step.
apply ST_AppAbs.
apply v_abs.
simpl.
apply multi_refl. Qed.
(** Example:
((\x:Bool->Bool. x) ((\x:Bool->Bool. x) (\x:Bool. x)))
==>* (\x:Bool. x)
i.e.
(idBB (idBB idB)) ==>* idB.
*)
Lemma step_example2 :
(tapp idBB (tapp idBB idB)) ==>* idB.
Proof.
eapply multi_step.
apply ST_App2. auto.
apply ST_AppAbs. auto.
eapply multi_step.
apply ST_AppAbs. simpl. auto.
simpl. apply multi_refl. Qed.
(** Example:
((\x:Bool->Bool. x) (\x:Bool. if x then false
else true)) true)
==>* false
i.e.
((idBB notB) ttrue) ==>* tfalse.
*)
Lemma step_example3 :
tapp (tapp idBB notB) ttrue ==>* tfalse.
Proof.
eapply multi_step.
apply ST_App1. apply ST_AppAbs. auto. simpl.
eapply multi_step.
apply ST_AppAbs. auto. simpl.
eapply multi_step.
apply ST_IfTrue. apply multi_refl. Qed.
(** Example:
((\x:Bool -> Bool. x) ((\x:Bool. if x then false
else true) true))
==>* false
i.e.
(idBB (notB ttrue)) ==>* tfalse.
*)
Lemma step_example4 :
tapp idBB (tapp notB ttrue) ==>* tfalse.
Proof.
eapply multi_step.
apply ST_App2. auto.
apply ST_AppAbs. auto. simpl.
eapply multi_step.
apply ST_App2. auto.
apply ST_IfTrue.
eapply multi_step.
apply ST_AppAbs. auto. simpl.
apply multi_refl. Qed.
(** A more automatic proof *)
Lemma step_example1' :
(tapp idBB idB) ==>* idB.
Proof. normalize. Qed.
(** Again, we can use the [normalize] tactic from above to simplify
the proof. *)
Lemma step_example2' :
(tapp idBB (tapp idBB idB)) ==>* idB.
Proof.
normalize.
Qed.
Lemma step_example3' :
tapp (tapp idBB notB) ttrue ==>* tfalse.
Proof. normalize. Qed.
Lemma step_example4' :
tapp idBB (tapp notB ttrue) ==>* tfalse.
Proof. normalize. Qed.
(** **** Exercise: 2 stars (step_example3) *)
(** Try to do this one both with and without [normalize]. *)
Lemma step_example5 :
(tapp (tapp idBBBB idBB) idB)
==>* idB.
Proof.
(* FILL IN HERE *) Admitted.
(* FILL IN HERE *)
(** [] *)
(* ###################################################################### *)
(** ** Typing *)
(* ################################### *)
(** *** Contexts *)
(** _Question_: What is the type of the term "[x y]"?
_Answer_: It depends on the types of [x] and [y]!
I.e., in order to assign a type to a term, we need to know
what assumptions we should make about the types of its free
variables.
This leads us to a three-place "typing judgment", informally
written [Gamma |- t \in T], where [Gamma] is a
"typing context" -- a mapping from variables to their types. *)
(** We hide the definition of partial maps in a module since it is
actually defined in [SfLib]. *)
Module PartialMap.
Definition partial_map (A:Type) := id -> option A.
Definition empty {A:Type} : partial_map A := (fun _ => None).
(** Informally, we'll write [Gamma, x:T] for "extend the partial
function [Gamma] to also map [x] to [T]." Formally, we use the
function [extend] to add a binding to a partial map. *)
Definition extend {A:Type} (Gamma : partial_map A) (x:id) (T : A) :=
fun x' => if eq_id_dec x x' then Some T else Gamma x'.
Lemma extend_eq : forall A (ctxt: partial_map A) x T,
(extend ctxt x T) x = Some T.
Proof.
intros. unfold extend. rewrite eq_id. auto.
Qed.
Lemma extend_neq : forall A (ctxt: partial_map A) x1 T x2,
x2 <> x1 ->
(extend ctxt x2 T) x1 = ctxt x1.
Proof.
intros. unfold extend. rewrite neq_id; auto.
Qed.
End PartialMap.
Definition context := partial_map ty.
(* ################################### *)
(** *** Typing Relation *)
(**
Gamma x = T
-------------- (T_Var)
Gamma |- x \in T
Gamma , x:T11 |- t12 \in T12
---------------------------- (T_Abs)
Gamma |- \x:T11.t12 \in T11->T12
Gamma |- t1 \in T11->T12
Gamma |- t2 \in T11
---------------------- (T_App)
Gamma |- t1 t2 \in T12
-------------------- (T_True)
Gamma |- true \in Bool
--------------------- (T_False)
Gamma |- false \in Bool
Gamma |- t1 \in Bool Gamma |- t2 \in T Gamma |- t3 \in T
-------------------------------------------------------- (T_If)
Gamma |- if t1 then t2 else t3 \in T
We can read the three-place relation [Gamma |- t \in T] as:
"to the term [t] we can assign the type [T] using as types for
the free variables of [t] the ones specified in the context
[Gamma]." *)
Reserved Notation "Gamma '|-' t '\in' T" (at level 40).
Inductive has_type : context -> tm -> ty -> Prop :=
| T_Var : forall Gamma x T,
Gamma x = Some T ->
Gamma |- tvar x \in T
| T_Abs : forall Gamma x T11 T12 t12,
extend Gamma x T11 |- t12 \in T12 ->
Gamma |- tabs x T11 t12 \in TArrow T11 T12
| T_App : forall T11 T12 Gamma t1 t2,
Gamma |- t1 \in TArrow T11 T12 ->
Gamma |- t2 \in T11 ->
Gamma |- tapp t1 t2 \in T12
| T_True : forall Gamma,
Gamma |- ttrue \in TBool
| T_False : forall Gamma,
Gamma |- tfalse \in TBool
| T_If : forall t1 t2 t3 T Gamma,
Gamma |- t1 \in TBool ->
Gamma |- t2 \in T ->
Gamma |- t3 \in T ->
Gamma |- tif t1 t2 t3 \in T
where "Gamma '|-' t '\in' T" := (has_type Gamma t T).
Tactic Notation "has_type_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "T_Var" | Case_aux c "T_Abs"
| Case_aux c "T_App" | Case_aux c "T_True"
| Case_aux c "T_False" | Case_aux c "T_If" ].
Hint Constructors has_type.
(* ################################### *)
(** *** Examples *)
Example typing_example_1 :
empty |- tabs x TBool (tvar x) \in TArrow TBool TBool.
Proof.
apply T_Abs. apply T_Var. reflexivity. Qed.
(** Note that since we added the [has_type] constructors to the hints
database, auto can actually solve this one immediately. *)
Example typing_example_1' :
empty |- tabs x TBool (tvar x) \in TArrow TBool TBool.
Proof. auto. Qed.
(** Another example:
empty |- \x:A. \y:A->A. y (y x))
\in A -> (A->A) -> A.
*)
Example typing_example_2 :
empty |-
(tabs x TBool
(tabs y (TArrow TBool TBool)
(tapp (tvar y) (tapp (tvar y) (tvar x))))) \in
(TArrow TBool (TArrow (TArrow TBool TBool) TBool)).
Proof with auto using extend_eq.
apply T_Abs.
apply T_Abs.
eapply T_App. apply T_Var...
eapply T_App. apply T_Var...
apply T_Var...
Qed.
(** **** Exercise: 2 stars, optional (typing_example_2_full) *)
(** Prove the same result without using [auto], [eauto], or
[eapply]. *)
Example typing_example_2_full :
empty |-
(tabs x TBool
(tabs y (TArrow TBool TBool)
(tapp (tvar y) (tapp (tvar y) (tvar x))))) \in
(TArrow TBool (TArrow (TArrow TBool TBool) TBool)).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars (typing_example_3) *)
(** Formally prove the following typing derivation holds: *)
(**
empty |- \x:Bool->B. \y:Bool->Bool. \z:Bool.
y (x z)
\in T.
*)
Example typing_example_3 :
exists T,
empty |-
(tabs x (TArrow TBool TBool)
(tabs y (TArrow TBool TBool)
(tabs z TBool
(tapp (tvar y) (tapp (tvar x) (tvar z)))))) \in
T.
Proof with auto.
(* FILL IN HERE *) Admitted.
(** [] *)
(** We can also show that terms are _not_ typable. For example, let's
formally check that there is no typing derivation assigning a type
to the term [\x:Bool. \y:Bool, x y] -- i.e.,
~ exists T,
empty |- \x:Bool. \y:Bool, x y : T.
*)
Example typing_nonexample_1 :
~ exists T,
empty |-
(tabs x TBool
(tabs y TBool
(tapp (tvar x) (tvar y)))) \in
T.
Proof.
intros Hc. inversion Hc.
(* The [clear] tactic is useful here for tidying away bits of
the context that we're not going to need again. *)
inversion H. subst. clear H.
inversion H5. subst. clear H5.
inversion H4. subst. clear H4.
inversion H2. subst. clear H2.
inversion H5. subst. clear H5.
(* rewrite extend_neq in H1. rewrite extend_eq in H1. *)
inversion H1. Qed.
(** **** Exercise: 3 stars, optional (typing_nonexample_3) *)
(** Another nonexample:
~ (exists S, exists T,
empty |- \x:S. x x : T).
*)
Example typing_nonexample_3 :
~ (exists S, exists T,
empty |-
(tabs x S
(tapp (tvar x) (tvar x))) \in
T).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
End STLC.
(** $Date: 2014-12-31 11:17:56 -0500 (Wed, 31 Dec 2014) $ *)
|
// Copyright (c) 2014 Takashi Toyoshima <[email protected]>.
// All rights reserved. Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
module SevenSegmentLED(
i_data,
o_a,
o_b,
o_c,
o_d,
o_e,
o_f,
o_g);
input [3:0] i_data;
output o_a;
output o_b;
output o_c;
output o_d;
output o_e;
output o_f;
output o_g;
wire [6:0] w_out;
function [6:0] Decode;
input [3:0] data;
begin
case (i_data)
4'h0: Decode = 7'b0000001;
4'h1: Decode = 7'b1001111;
4'h2: Decode = 7'b0010010;
4'h3: Decode = 7'b0000110;
4'h4: Decode = 7'b1001100;
4'h5: Decode = 7'b0100100;
4'h6: Decode = 7'b0100000;
4'h7: Decode = 7'b0001111;
4'h8: Decode = 7'b0000000;
4'h9: Decode = 7'b0000100;
4'ha: Decode = 7'b0001000;
4'hb: Decode = 7'b1100000;
4'hc: Decode = 7'b0110001;
4'hd: Decode = 7'b1000010;
4'he: Decode = 7'b0110000;
4'hf: Decode = 7'b0111000;
endcase
end
endfunction // Decode
assign w_out = Decode(i_data);
assign o_a = w_out[6];
assign o_b = w_out[5];
assign o_c = w_out[4];
assign o_d = w_out[3];
assign o_e = w_out[2];
assign o_f = w_out[1];
assign o_g = w_out[0];
endmodule // SevenSegmentLED
|
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// Project : Series-7 Integrated Block for PCI Express
// File : PCIeGen2x8If128_pipe_wrapper.v
// Version : 3.2
//------------------------------------------------------------------------------
// Filename : pipe_wrapper.v
// Description : PIPE Wrapper for 7 Series Transceiver
// Version : 20.2
//------------------------------------------------------------------------------
//---------- PIPE Wrapper Hierarchy --------------------------------------------
// pipe_wrapper.v
// pipe_clock.v
// pipe_reset.v or gtp_pipe_reset.v
// qpll_reset.v
// * Generate GTXE2_CHANNEL for every lane.
// pipe_user.v
// pipe_rate.v or gtp_pipe_rate.v
// pipe_sync.v
// pipe_drp.v or gtp_pipe_drp.v
// pipe_eq.v
// rxeq_scan.v
// gt_wrapper.v
// GTXE2_CHANNEL or GTHE2_CHANNEL or GTPE2_CHANNEL
// GTXE2_COMMON or GTHE2_COMMON or GTPE2_CHANNEL
// * Generate GTXE2_COMMON for every quad.
// qpll_drp.v
// qpll_wrapper.v
//------------------------------------------------------------------------------
//---------- PIPE Wrapper Parameter Encoding -----------------------------------
// PCIE_SIM_MODE : "FALSE" = Normal mode (default)
// : "TRUE" = Simulation only
// PCIE_SIM_TX_EIDLE_DRIVE_LEVEL : "0", "1" (default), "X" simulation TX electrical idle drive level
// PCIE_GT_DEVICE : "GTX" (default)
// : "GTH"
// : "GTP"
// PCIE_USE_MODE : "1.0" = GTX IES 325T or GTP IES/GES use mode.
// : "1.1" = GTX IES 485T use mode.
// : "2.0" = GTH IES 690T use mode for 1.0 silicon.
// : "2.1" = GTH GES 690T use mode for 1.2 and 2.0 silicon. SW model use "2.0"
// : "3.0" = GTX GES 325T or 485T use mode (default).
// PCIE_PLL_SEL : "CPLL" (default)
// : "QPLL"
// PCIE_AUX_CDR_GEN3_EN : "FALSE" Use Primary CDR for Gen3 only (GTH 2.0)
// : "TRUE" Use AUX CDR for Gen3 only (default) (GTH 2.0)
// PCIE_LPM_DFE : "DFE" for Gen1/Gen2 only (GTX, GTH)
// : "LPM" for Gen1/Gen2 only (default) (GTX, GTH)
// PCIE_LPM_DFE_GEN3 : "DFE" for Gen3 only (GTX, GTH)
// : "LPM" for Gen3 only (default) (GTX, GTH)
// PCIE_EXT_CLK : "FALSE" = Use internal clock module(default)
// : "TRUE" = Use external clock module
// PCIE_POWER_SAVING : "FALSE" = Disable PLL power saving
// : "TRUE" = Enable PLL power saving (default)
// PCIE_ASYNC_EN : "FALSE" = Synchronous mode (default)
// : "TRUE" = Asynchronous mode.
// PCIE_TXBUF_EN : "FALSE" = TX buffer bypass for Gen1/Gen2 only (default)
// : "TRUE" = TX buffer use for Gen1/Gen2 only (for debug only)
// PCIE_RXBUF_EN : "FALSE" = RX buffer bypass for Gen3 only (not supported)
// : "TRUE" = RX buffer use for Gen3 only (default)
// PCIE_TXSYNC_MODE : 0 = Manual TX sync (default) (GTX, GTH)
// : 1 = Auto TX sync (GTH)
// PCIE_RXSYNC_MODE : 0 = Manual RX sync (default) (GTX, GTH)
// : 1 = Auto RX sync (GTH)
// PCIE_CHAN_BOND : 0 = One-Hop (default)
// : 1 = Daisy-Chain
// : 2 = Binary-Tree
// PCIE_CHAN_BOND_EN : "FALSE" = Channel bonding disable for Gen1/Gen2 only
// : "TRUE" = Channel bonding enable for Gen1/Gen2 only
// PCIE_LANE : 1 (default), 2, 4, or 8
// PCIE_LINK_SPEED : 1 = PCIe Gen1 Mode
// : 2 = PCIe Gen1/Gen2 Mode (default)
// : 3 = PCIe Gen1/Gen2/Gen3 Mode
// PCIE_REFCLK_FREQ : 0 = 100 MHz (default)
// : 1 = 125 MHz
// : 2 = 250 MHz
// PCIE_USERCLK[1/2]_FREQ : 0 = Disable user clock
// : 1 = 31.25 MHz
// : 2 = 62.50 MHz (default)
// : 3 = 125.00 MHz
// : 4 = 250.00 MHz
// : 5 = 500.00 MHz
// PCIE_TX_EIDLE_ASSERT_DELAY : 3'd0 to 3'd7 (default = 3'd4)
// PCIE_RXEQ_MODE_GEN3 : 0 = Return same TX coefficients
// : 1 = Return TX preset #5
// PCIE_OOBCLK_MODE : 0 = Reference clock
// : 1 = 62.50 MHz (default)
// : 2 = 50.00 MHz (requires 1 BUFG)
// PCIE_JTAG_MODE : 0 = Normal operation (default)
// : 1 = JTAG mode (for debug only)
// PCIE_DEBUG_MODE : 0 = Normal operation (default)
// : 1 = Debug mode (for debug only)
//------------------------------------------------------------------------------
//---------- Notes -------------------------------------------------------------
// Notes within the PIPE Wrapper RTL files are for internal use only.
// Data Width : This PIPE Wrapper supports a 32-bit [TX/RX]DATA interface.
// In Gen1/Gen2 modes, only 16-bits [15:0] are used.
// In Gen3 mode, all 32-bits are used.
//------------------------------------------------------------------------------
`timescale 1ns / 1ps
//---------- PIPE Wrapper ------------------------------------------------------
(* DowngradeIPIdentifiedWarnings = "yes" *)
module PCIeGen2x8If128_pipe_wrapper #
(
parameter PCIE_SIM_MODE = "FALSE", // PCIe sim mode
parameter PCIE_SIM_SPEEDUP = "FALSE", // PCIe sim speedup
parameter PCIE_SIM_TX_EIDLE_DRIVE_LEVEL = "1", // PCIe sim TX electrical idle drive level
parameter PCIE_GT_DEVICE = "GTX", // PCIe GT device
parameter PCIE_USE_MODE = "3.0", // PCIe use mode
parameter PCIE_PLL_SEL = "CPLL", // PCIe PLL select for Gen1/Gen2 (GTX/GTH) only
parameter PCIE_AUX_CDR_GEN3_EN = "TRUE", // PCIe AUX CDR for Gen3 (GTH 2.0) only
parameter PCIE_LPM_DFE = "LPM", // PCIe LPM or DFE mode for Gen1/Gen2 only
parameter PCIE_LPM_DFE_GEN3 = "DFE", // PCIe LPM or DFE mode for Gen3 only
parameter PCIE_EXT_CLK = "FALSE", // PCIe external clock
parameter PCIE_EXT_GT_COMMON = "FALSE", // PCIe external GT COMMON
parameter EXT_CH_GT_DRP = "FALSE", // PCIe external CH DRP
parameter TX_MARGIN_FULL_0 = 7'b1001111, // 1000 mV
parameter TX_MARGIN_FULL_1 = 7'b1001110, // 950 mV
parameter TX_MARGIN_FULL_2 = 7'b1001101, // 900 mV
parameter TX_MARGIN_FULL_3 = 7'b1001100, // 850 mV
parameter TX_MARGIN_FULL_4 = 7'b1000011, // 400 mV
parameter TX_MARGIN_LOW_0 = 7'b1000101, // 500 mV
parameter TX_MARGIN_LOW_1 = 7'b1000110 , // 450 mV
parameter TX_MARGIN_LOW_2 = 7'b1000011, // 400 mV
parameter TX_MARGIN_LOW_3 = 7'b1000010 , // 350 mV
parameter TX_MARGIN_LOW_4 = 7'b1000000 ,
parameter PCIE_POWER_SAVING = "TRUE", // PCIe power saving
parameter PCIE_ASYNC_EN = "FALSE", // PCIe async enable
parameter PCIE_TXBUF_EN = "FALSE", // PCIe TX buffer enable for Gen1/Gen2 only
parameter PCIE_RXBUF_EN = "TRUE", // PCIe RX buffer enable for Gen3 only
parameter PCIE_TXSYNC_MODE = 0, // PCIe TX sync mode
parameter PCIE_RXSYNC_MODE = 0, // PCIe RX sync mode
parameter PCIE_CHAN_BOND = 0, // PCIe channel bonding mode
parameter PCIE_CHAN_BOND_EN = "TRUE", // PCIe channel bonding enable for Gen1/Gen2 only
parameter PCIE_LANE = 8, // PCIe number of lanes
parameter PCIE_LINK_SPEED = 2, // PCIe link speed
parameter PCIE_REFCLK_FREQ = 0, // PCIe reference clock frequency
parameter PCIE_USERCLK1_FREQ = 5, // PCIe user clock 1 frequency
parameter PCIE_USERCLK2_FREQ = 4, // PCIe user clock 2 frequency
parameter PCIE_TX_EIDLE_ASSERT_DELAY = 3'd2, // PCIe TX electrical idle assert delay
parameter PCIE_RXEQ_MODE_GEN3 = 1, // PCIe RX equalization mode
parameter PCIE_OOBCLK_MODE = 1, // PCIe OOB clock mode
parameter PCIE_JTAG_MODE = 0, // PCIe JTAG mode
parameter PCIE_DEBUG_MODE = 0 // PCIe debug mode
)
//--------------------------------------
( // Gen1/Gen2 | Gen3
//--------------------------------------
//---------- PIPE Clock & Reset Ports ------------------
input PIPE_CLK, // Reference clock that drives MMCM
input PIPE_RESET_N, // PCLK | PCLK
output PIPE_PCLK, // Drives [TX/RX]USRCLK in Gen1/Gen2
// Drives TXUSRCLK in Gen3
// Drives RXUSRCLK in Gen3 async mode only
//---------- PIPE TX Data Ports ------------------------
input [(PCIE_LANE*32)-1:0]PIPE_TXDATA, // PCLK | PCLK
input [(PCIE_LANE*4)-1:0] PIPE_TXDATAK, // PCLK | PCLK
output [PCIE_LANE-1:0] PIPE_TXP, // Serial data
output [PCIE_LANE-1:0] PIPE_TXN, // Serial data
//---------- PIPE RX Data Ports ------------------------
input [PCIE_LANE-1:0] PIPE_RXP, // Serial data
input [PCIE_LANE-1:0] PIPE_RXN, // Serial data
output [(PCIE_LANE*32)-1:0]PIPE_RXDATA, // PCLK | RXUSRCLK
output [(PCIE_LANE*4)-1:0] PIPE_RXDATAK, // PCLK | RXUSRCLK
//---------- PIPE Command Ports ------------------------
input PIPE_TXDETECTRX, // PCLK | PCLK
input [PCIE_LANE-1:0] PIPE_TXELECIDLE, // PCLK | PCLK
input [PCIE_LANE-1:0] PIPE_TXCOMPLIANCE, // PCLK | PCLK
input [PCIE_LANE-1:0] PIPE_RXPOLARITY, // PCLK | RXUSRCLK
input [(PCIE_LANE*2)-1:0] PIPE_POWERDOWN, // PCLK | PCLK
input [ 1:0] PIPE_RATE, // PCLK | PCLK
//---------- PIPE Electrical Command Ports -------------
input [ 2:0] PIPE_TXMARGIN, // Async | Async
input PIPE_TXSWING, // Async | Async
input [PCIE_LANE-1:0] PIPE_TXDEEMPH, // Async/PCLK | Async/PCLK
input [(PCIE_LANE*2)-1:0] PIPE_TXEQ_CONTROL, // PCLK | PCLK
input [(PCIE_LANE*4)-1:0] PIPE_TXEQ_PRESET, // PCLK | PCLK
input [(PCIE_LANE*4)-1:0] PIPE_TXEQ_PRESET_DEFAULT,// PCLK | PCLK
input [(PCIE_LANE*6)-1:0] PIPE_TXEQ_DEEMPH, // PCLK | PCLK
input [(PCIE_LANE*2)-1:0] PIPE_RXEQ_CONTROL, // PCLK | PCLK
input [(PCIE_LANE*3)-1:0] PIPE_RXEQ_PRESET, // PCLK | PCLK
input [(PCIE_LANE*6)-1:0] PIPE_RXEQ_LFFS, // PCLK | PCLK
input [(PCIE_LANE*4)-1:0] PIPE_RXEQ_TXPRESET, // PCLK | PCLK
input [PCIE_LANE-1:0] PIPE_RXEQ_USER_EN, // PCLK | PCLK
input [(PCIE_LANE*18)-1:0]PIPE_RXEQ_USER_TXCOEFF, // PCLK | PCLK
input [PCIE_LANE-1:0] PIPE_RXEQ_USER_MODE, // PCLK | PCLK
output [ 5:0] PIPE_TXEQ_FS, // Async | Async
output [ 5:0] PIPE_TXEQ_LF, // Async | Async
output [(PCIE_LANE*18)-1:0]PIPE_TXEQ_COEFF, // PCLK | PCLK
output [PCIE_LANE-1:0] PIPE_TXEQ_DONE, // PCLK | PCLK
output [(PCIE_LANE*18)-1:0]PIPE_RXEQ_NEW_TXCOEFF, // PCLK | PCLK
output [PCIE_LANE-1:0] PIPE_RXEQ_LFFS_SEL, // PCLK | PCLK
output [PCIE_LANE-1:0] PIPE_RXEQ_ADAPT_DONE, // PCLK | PCLK
output [PCIE_LANE-1:0] PIPE_RXEQ_DONE, // PCLK | PCLK
//---------- PIPE Status Ports -------------------------
output [PCIE_LANE-1:0] PIPE_RXVALID, // PCLK | RXUSRCLK
output [PCIE_LANE-1:0] PIPE_PHYSTATUS, // PCLK | RXUSRCLK
output [PCIE_LANE-1:0] PIPE_PHYSTATUS_RST, // PCLK | RXUSRCLK
output [PCIE_LANE-1:0] PIPE_RXELECIDLE, // Async | Async
output [PCIE_LANE-1:0] PIPE_EYESCANDATAERROR, // Async | Async
output [(PCIE_LANE*3)-1:0] PIPE_RXSTATUS, // PCLK | RXUSRCLK
output [PCIE_LANE-1:0] PIPE_RXPMARESETDONE, // Async | Async
output [(PCIE_LANE*3)-1:0] PIPE_RXBUFSTATUS, // PCLK | RXUSRCLK
output [PCIE_LANE-1:0] PIPE_TXPHALIGNDONE, // Async | Async
output [PCIE_LANE-1:0] PIPE_TXPHINITDONE, // Async | Async
output [PCIE_LANE-1:0] PIPE_TXDLYSRESETDONE, // Async | Async
output [PCIE_LANE-1:0] PIPE_RXPHALIGNDONE, // Async | Async
output [PCIE_LANE-1:0] PIPE_RXDLYSRESETDONE, // Async | Async
output [PCIE_LANE-1:0] PIPE_RXSYNCDONE, // PCLK | RXUSRCLK
output [(PCIE_LANE*8)-1:0] PIPE_RXDISPERR, // PCLK | RXUSRCLK
output [(PCIE_LANE*8)-1:0] PIPE_RXNOTINTABLE, // PCLK | RXUSRCLK
output [PCIE_LANE-1:0] PIPE_RXCOMMADET, // PCLK | RXUSRCLK
//---------- PIPE User Ports ---------------------------
input PIPE_MMCM_RST_N, // Async | Async
input [PCIE_LANE-1:0] PIPE_RXSLIDE, // PCLK | RXUSRCLK
output [PCIE_LANE-1:0] PIPE_CPLL_LOCK, // Async | Async
output [(PCIE_LANE-1)>>2:0]PIPE_QPLL_LOCK, // Async | Async
output PIPE_PCLK_LOCK, // Async | Async
output [PCIE_LANE-1:0] PIPE_RXCDRLOCK, // Async | Async
output PIPE_USERCLK1, // Optional user clock
output PIPE_USERCLK2, // Optional user clock
output PIPE_RXUSRCLK, // RXUSRCLK
// Equivalent to PCLK in Gen1/Gen2
// Equivalent to RXOUTCLK[0] in Gen3
output [PCIE_LANE-1:0] PIPE_RXOUTCLK, // RX recovered clock (for debug only)
output [PCIE_LANE-1:0] PIPE_TXSYNC_DONE, // PCLK | PCLK
output [PCIE_LANE-1:0] PIPE_RXSYNC_DONE, // PCLK | PCLK
output [PCIE_LANE-1:0] PIPE_GEN3_RDY, // PCLK | RXUSRCLK
output [PCIE_LANE-1:0] PIPE_RXCHANISALIGNED,
output [PCIE_LANE-1:0] PIPE_ACTIVE_LANE,
// Shared Logic Internal
output INT_PCLK_OUT_SLAVE, // PCLK | PCLK
output INT_RXUSRCLK_OUT, // RXUSERCLK
output [PCIE_LANE-1:0 ] INT_RXOUTCLK_OUT, // RX recovered clock
output INT_DCLK_OUT, // DCLK | DCLK
output INT_USERCLK1_OUT, // Optional user clock
output INT_USERCLK2_OUT, // Optional user clock
output INT_OOBCLK_OUT, // OOB | OOB
output INT_MMCM_LOCK_OUT, // Async | Async
output [1:0] INT_QPLLLOCK_OUT,
output [1:0] INT_QPLLOUTCLK_OUT,
output [1:0] INT_QPLLOUTREFCLK_OUT,
input [PCIE_LANE-1:0] INT_PCLK_SEL_SLAVE,
// Shared Logic External
//---------- External Clock Ports ----------------------
input PIPE_PCLK_IN, // PCLK | PCLK
input PIPE_RXUSRCLK_IN, // RXUSERCLK
// Equivalent to PCLK in Gen1/Gen2
// Equivalent to RXOUTCLK[0] in Gen3
input [PCIE_LANE-1:0] PIPE_RXOUTCLK_IN, // RX recovered clock
input PIPE_DCLK_IN, // DCLK | DCLK
input PIPE_USERCLK1_IN, // Optional user clock
input PIPE_USERCLK2_IN, // Optional user clock
input PIPE_OOBCLK_IN, // OOB | OOB
input PIPE_MMCM_LOCK_IN, // Async | Async
output PIPE_TXOUTCLK_OUT, // PCLK | PCLK
output [PCIE_LANE-1:0] PIPE_RXOUTCLK_OUT, // RX recovered clock (for debug only)
output [PCIE_LANE-1:0] PIPE_PCLK_SEL_OUT, // PCLK | PCLK
output PIPE_GEN3_OUT, // PCLK | PCLK
//---------- External GT COMMON Ports ----------------------
input [11:0] QPLL_DRP_CRSCODE,
input [17:0] QPLL_DRP_FSM,
input [1:0] QPLL_DRP_DONE,
input [1:0] QPLL_DRP_RESET,
input [1:0] QPLL_QPLLLOCK,
input [1:0] QPLL_QPLLOUTCLK,
input [1:0] QPLL_QPLLOUTREFCLK,
output QPLL_QPLLPD,
output [1:0] QPLL_QPLLRESET,
output QPLL_DRP_CLK,
output QPLL_DRP_RST_N,
output QPLL_DRP_OVRD,
output QPLL_DRP_GEN3,
output QPLL_DRP_START,
//---------- TRANSCEIVER DEBUG -----------------------
input [ 2:0] PIPE_TXPRBSSEL, // PCLK | PCLK
input [ 2:0] PIPE_RXPRBSSEL, // PCLK | PCLK
input PIPE_TXPRBSFORCEERR, // PCLK | PCLK
input PIPE_RXPRBSCNTRESET, // PCLK | PCLK
input [ 2:0] PIPE_LOOPBACK, // PCLK | PCLK
output [PCIE_LANE-1:0] PIPE_RXPRBSERR, // PCLK | PCLK
input [PCIE_LANE-1:0] PIPE_TXINHIBIT, // PCLK | PCLK
//---------- FSM Ports ---------------------------------
output [4:0] PIPE_RST_FSM, // PCLK | PCLK
output [11:0] PIPE_QRST_FSM, // PCLK | PCLK
output [(PCIE_LANE*5)-1:0] PIPE_RATE_FSM, // PCLK | PCLK
output [(PCIE_LANE*6)-1:0] PIPE_SYNC_FSM_TX, // PCLK | PCLK
output [(PCIE_LANE*7)-1:0] PIPE_SYNC_FSM_RX, // PCLK | PCLK
output [(PCIE_LANE*7)-1:0] PIPE_DRP_FSM, // DCLK | DCLK
output [(PCIE_LANE*6)-1:0] PIPE_TXEQ_FSM, // PCLK | PCLK
output [(PCIE_LANE*6)-1:0] PIPE_RXEQ_FSM, // PCLK | PCLK
output [((((PCIE_LANE-1)>>2)+1)*9)-1:0]PIPE_QDRP_FSM, // DCLK | DCLK
output PIPE_RST_IDLE, // PCLK | PCLK
output PIPE_QRST_IDLE, // PCLK | PCLK
output PIPE_RATE_IDLE, // PCLK | PCLK
//----------- Channel DRP----------------------------
output EXT_CH_GT_DRPCLK,
input [(PCIE_LANE*9)-1:0] EXT_CH_GT_DRPADDR,
input [PCIE_LANE-1:0] EXT_CH_GT_DRPEN,
input [(PCIE_LANE*16)-1:0]EXT_CH_GT_DRPDI,
input [PCIE_LANE-1:0] EXT_CH_GT_DRPWE,
output [(PCIE_LANE*16)-1:0]EXT_CH_GT_DRPDO,
output [PCIE_LANE-1:0] EXT_CH_GT_DRPRDY,
//---------- JTAG Ports --------------------------------
input PIPE_JTAG_EN, // DCLK | DCLK
output [PCIE_LANE-1:0] PIPE_JTAG_RDY, // DCLK | DCLK
//---------- Debug Ports -------------------------------
output [PCIE_LANE-1:0] PIPE_DEBUG_0, // Async | Async
output [PCIE_LANE-1:0] PIPE_DEBUG_1, // Async | Async
output [PCIE_LANE-1:0] PIPE_DEBUG_2, // Async | Async
output [PCIE_LANE-1:0] PIPE_DEBUG_3, // Async | Async
output [PCIE_LANE-1:0] PIPE_DEBUG_4, // Async | Async
output [PCIE_LANE-1:0] PIPE_DEBUG_5, // Async | Async
output [PCIE_LANE-1:0] PIPE_DEBUG_6, // Async | Async
output [PCIE_LANE-1:0] PIPE_DEBUG_7, // Async | Async
output [PCIE_LANE-1:0] PIPE_DEBUG_8, // Async | Async
output [PCIE_LANE-1:0] PIPE_DEBUG_9, // Async | Async
output [31:0] PIPE_DEBUG, // Async | Async
output [(PCIE_LANE*15)-1:0] PIPE_DMONITOROUT // DMONITORCLK
);
//---------- Input Registers ---------------------------
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg reset_n_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg reset_n_reg2;
//---------- PIPE Clock Module Output ------------------
wire clk_pclk;
wire clk_rxusrclk;
wire [PCIE_LANE-1:0] clk_rxoutclk;
wire clk_dclk;
wire clk_oobclk;
wire clk_mmcm_lock;
//---------- PIPE Reset Module Output ------------------
wire rst_cpllreset;
wire rst_cpllpd;
wire rst_rxusrclk_reset;
wire rst_dclk_reset;
wire rst_gtreset;
wire rst_drp_start;
wire rst_drp_x16x20_mode;
wire rst_drp_x16;
wire rst_userrdy;
wire rst_txsync_start;
wire rst_idle;
wire [4:0] rst_fsm;
//------------------------------------------------------
wire gtp_rst_qpllreset; // GTP
wire gtp_rst_qpllpd; // GTP
//------------------------------------------------------
wire [(PCIE_LANE-1)>>2:0]qpllreset;
wire qpllpd;
//---------- QPLL Reset Module Output ------------------
wire qrst_ovrd;
wire qrst_drp_start;
wire qrst_qpllreset;
wire qrst_qpllpd;
wire qrst_idle;
wire [3:0] qrst_fsm;
//---------- PIPE_JTAG Master Module Output ------------
wire [(PCIE_LANE*37)-1:0] jtag_sl_iport;
wire [(PCIE_LANE*17)-1:0] jtag_sl_oport;
//---------- PIPE User Module Output -------------------
wire [PCIE_LANE-1:0] gt_txpmareset_i;
wire [PCIE_LANE-1:0] gt_rxpmareset_i;
wire [PCIE_LANE-1:0] user_oobclk;
wire [PCIE_LANE-1:0] user_resetovrd;
wire [PCIE_LANE-1:0] user_txpmareset;
wire [PCIE_LANE-1:0] user_rxpmareset;
wire [PCIE_LANE-1:0] user_rxcdrreset;
wire [PCIE_LANE-1:0] user_rxcdrfreqreset;
wire [PCIE_LANE-1:0] user_rxdfelpmreset;
wire [PCIE_LANE-1:0] user_eyescanreset;
wire [PCIE_LANE-1:0] user_txpcsreset;
wire [PCIE_LANE-1:0] user_rxpcsreset;
wire [PCIE_LANE-1:0] user_rxbufreset;
wire [PCIE_LANE-1:0] user_resetovrd_done;
wire [PCIE_LANE-1:0] user_active_lane;
wire [PCIE_LANE-1:0] user_resetdone /* synthesis syn_keep=1 */;
wire [PCIE_LANE-1:0] user_rxcdrlock;
wire [PCIE_LANE-1:0] user_rx_converge;
//---------- PIPE Rate Module Output -------------------
wire [PCIE_LANE-1:0] rate_cpllpd;
wire [PCIE_LANE-1:0] rate_qpllpd;
wire [PCIE_LANE-1:0] rate_cpllreset;
wire [PCIE_LANE-1:0] rate_qpllreset;
wire [PCIE_LANE-1:0] rate_txpmareset;
wire [PCIE_LANE-1:0] rate_rxpmareset;
wire [(PCIE_LANE*2)-1:0] rate_sysclksel;
wire [PCIE_LANE-1:0] rate_pclk_sel;
wire [PCIE_LANE-1:0] rate_drp_start;
wire [PCIE_LANE-1:0] rate_drp_x16x20_mode;
wire [PCIE_LANE-1:0] rate_drp_x16;
wire [PCIE_LANE-1:0] rate_gen3;
wire [(PCIE_LANE*3)-1:0] rate_rate;
wire [PCIE_LANE-1:0] rate_resetovrd_start;
wire [PCIE_LANE-1:0] rate_txsync_start;
wire [PCIE_LANE-1:0] rate_done;
wire [PCIE_LANE-1:0] rate_rxsync_start;
wire [PCIE_LANE-1:0] rate_rxsync;
wire [PCIE_LANE-1:0] rate_idle;
wire [(PCIE_LANE*5)-1:0] rate_fsm;
//---------- PIPE Sync Module Output -------------------
wire [PCIE_LANE-1:0] sync_txphdlyreset;
wire [PCIE_LANE-1:0] sync_txphalign;
wire [PCIE_LANE-1:0] sync_txphalignen;
wire [PCIE_LANE-1:0] sync_txphinit;
wire [PCIE_LANE-1:0] sync_txdlybypass;
wire [PCIE_LANE-1:0] sync_txdlysreset;
wire [PCIE_LANE-1:0] sync_txdlyen;
wire [PCIE_LANE-1:0] sync_txsync_done;
wire [(PCIE_LANE*6)-1:0] sync_fsm_tx;
wire [PCIE_LANE-1:0] sync_rxphalign;
wire [PCIE_LANE-1:0] sync_rxphalignen;
wire [PCIE_LANE-1:0] sync_rxdlybypass;
wire [PCIE_LANE-1:0] sync_rxdlysreset;
wire [PCIE_LANE-1:0] sync_rxdlyen;
wire [PCIE_LANE-1:0] sync_rxddien;
wire [PCIE_LANE-1:0] sync_rxsync_done;
wire [PCIE_LANE-1:0] sync_rxsync_donem;
wire [(PCIE_LANE*7)-1:0] sync_fsm_rx;
wire [PCIE_LANE-1:0] txdlysresetdone;
wire [PCIE_LANE-1:0] txphaligndone;
wire [PCIE_LANE-1:0] rxdlysresetdone;
wire [PCIE_LANE-1:0] rxphaligndone_s;
wire txsyncallin; // GTH
wire rxsyncallin; // GTH
//---------- PIPE DRP Module Output --------------------
wire [(PCIE_LANE*9)-1:0] drp_addr;
wire [PCIE_LANE-1:0] drp_en;
wire [(PCIE_LANE*16)-1:0]drp_di;
wire [PCIE_LANE-1:0] drp_we;
wire [PCIE_LANE-1:0] drp_done;
wire [(PCIE_LANE*3)-1:0] drp_fsm;
//---------- PIPE JTAG Slave Module Output--------------
wire [(PCIE_LANE*17)-1:0]jtag_sl_addr;
wire [PCIE_LANE-1:0] jtag_sl_den;
wire [PCIE_LANE-1:0] jtag_sl_en;
wire [(PCIE_LANE*16)-1:0]jtag_sl_di;
wire [PCIE_LANE-1:0] jtag_sl_we;
//---------- PIPE DRP MUX Output -----------------------
wire [(PCIE_LANE*9)-1:0] drp_mux_addr;
wire [PCIE_LANE-1:0] drp_mux_en;
wire [(PCIE_LANE*16)-1:0]drp_mux_di;
wire [PCIE_LANE-1:0] drp_mux_we;
//---------- PIPE EQ Module Output ---------------------
wire [PCIE_LANE-1:0] eq_txeq_deemph;
wire [(PCIE_LANE*5)-1:0] eq_txeq_precursor;
wire [(PCIE_LANE*7)-1:0] eq_txeq_maincursor;
wire [(PCIE_LANE*5)-1:0] eq_txeq_postcursor;
wire [PCIE_LANE-1:0] eq_rxeq_adapt_done;
//---------- PIPE DRP Module Output --------------------
wire [((((PCIE_LANE-1)>>2)+1)*8)-1:0] qdrp_addr;
wire [(PCIE_LANE-1)>>2:0] qdrp_en;
wire [((((PCIE_LANE-1)>>2)+1)*16)-1:0] qdrp_di;
wire [(PCIE_LANE-1)>>2:0] qdrp_we;
wire [(PCIE_LANE-1)>>2:0] qdrp_done;
wire [(PCIE_LANE-1)>>2:0] qdrp_qpllreset;
wire [((((PCIE_LANE-1)>>2)+1)*6)-1:0] qdrp_crscode;
wire [((((PCIE_LANE-1)>>2)+1)*9)-1:0] qdrp_fsm;
//---------- QPLL Wrapper Output -----------------------
wire [(PCIE_LANE-1)>>2:0] qpll_qplloutclk;
wire [(PCIE_LANE-1)>>2:0] qpll_qplloutrefclk;
wire [(PCIE_LANE-1)>>2:0] qpll_qplllock;
wire [((((PCIE_LANE-1)>>2)+1)*16)-1:0] qpll_do;
wire [(PCIE_LANE-1)>>2:0] qpll_rdy;
//---------- GTX Wrapper Output ------------------------
wire [PCIE_LANE-1:0] gt_txoutclk;
wire [PCIE_LANE-1:0] gt_rxoutclk;
wire [PCIE_LANE-1:0] gt_cplllock;
wire [PCIE_LANE-1:0] gt_rxcdrlock;
wire [PCIE_LANE-1:0] gt_txresetdone;
wire [PCIE_LANE-1:0] gt_rxresetdone;
wire [PCIE_LANE-1:0] gt_eyescandataerror;
wire [PCIE_LANE-1:0] gt_rxpmaresetdone;
wire [(PCIE_LANE*8)-1:0] gt_rxdisperr;
wire [(PCIE_LANE*8)-1:0] gt_rxnotintable;
wire [PCIE_LANE-1:0] gt_rxvalid;
wire [PCIE_LANE-1:0] gt_phystatus;
wire [(PCIE_LANE*3)-1:0] gt_rxstatus;
wire [(PCIE_LANE*3)-1:0] gt_rxbufstatus;
wire [PCIE_LANE-1:0] gt_rxelecidle;
wire [PCIE_LANE-1:0] gt_txratedone;
wire [PCIE_LANE-1:0] gt_rxratedone;
wire [(PCIE_LANE*16)-1:0]gt_do;
wire [PCIE_LANE-1:0] gt_rdy;
wire [PCIE_LANE-1:0] gt_txphinitdone;
wire [PCIE_LANE-1:0] gt_txdlysresetdone;
wire [PCIE_LANE-1:0] gt_txphaligndone;
wire [PCIE_LANE-1:0] gt_rxdlysresetdone;
wire [PCIE_LANE:0] gt_rxphaligndone; // Custom width for calculation
wire [PCIE_LANE-1:0] gt_txsyncout; // GTH
wire [PCIE_LANE-1:0] gt_txsyncdone; // GTH
wire [PCIE_LANE-1:0] gt_rxsyncout; // GTH
wire [PCIE_LANE-1:0] gt_rxsyncdone; // GTH
wire [PCIE_LANE-1:0] gt_rxcommadet;
wire [(PCIE_LANE*4)-1:0] gt_rxchariscomma;
wire [PCIE_LANE-1:0] gt_rxbyteisaligned;
wire [PCIE_LANE-1:0] gt_rxbyterealign;
wire [ 4:0] gt_rxchbondi [PCIE_LANE:0];
wire [(PCIE_LANE*3)-1:0] gt_rxchbondlevel;
wire [ 4:0] gt_rxchbondo [PCIE_LANE:0];
wire [PCIE_LANE-1:0] rxchbonden;
wire [PCIE_LANE-1:0] rxchbondmaster;
wire [PCIE_LANE-1:0] rxchbondslave;
wire [PCIE_LANE-1:0] oobclk;
//---------- TX EQ -------------------------------------
localparam TXEQ_FS = 6'd40; // TX equalization full swing
localparam TXEQ_LF = 6'd15; // TX equalization low frequency
//---------- Select JTAG Slave Type ----------------------------------------
localparam GC_XSDB_SLAVE_TYPE = (PCIE_GT_DEVICE == "GTP") ? 16'h0400 : (PCIE_GT_DEVICE == "GTH") ? 16'h004A : 16'h0046;
//---------- Generate Per-Lane Signals -----------------
genvar i; // Index for per-lane signals
//---------- Assignments -------------------------------------------------------
assign gt_rxchbondo[0] = 5'd0; // Initialize rxchbond for lane 0
assign gt_rxphaligndone[PCIE_LANE] = 1'd1; // Mot used
assign txsyncallin = &(gt_txphaligndone | (~user_active_lane));
assign rxsyncallin = &(gt_rxphaligndone | (~user_active_lane));
//---------- Reset Synchronizer ------------------------------------------------
always @ (posedge clk_pclk or negedge PIPE_RESET_N)
begin
if (!PIPE_RESET_N)
begin
reset_n_reg1 <= 1'd0;
reset_n_reg2 <= 1'd0;
end
else
begin
reset_n_reg1 <= 1'd1;
reset_n_reg2 <= reset_n_reg1;
end
end
//---------- PIPE Clock Module -------------------------------------------------
generate
begin : pipe_clock_int
PCIeGen2x8If128_pipe_clock #
(
.PCIE_ASYNC_EN (PCIE_ASYNC_EN), // PCIe async enable
.PCIE_TXBUF_EN (PCIE_TXBUF_EN), // PCIe TX buffer enable for Gen1/Gen2 only
.PCIE_LANE (PCIE_LANE), // PCIe number of lanes
.PCIE_LINK_SPEED (PCIE_LINK_SPEED), // PCIe link speed
.PCIE_REFCLK_FREQ (PCIE_REFCLK_FREQ), // PCIe reference clock frequency
.PCIE_USERCLK1_FREQ (PCIE_USERCLK1_FREQ), // PCIe user clock 1 frequency
.PCIE_USERCLK2_FREQ (PCIE_USERCLK2_FREQ), // PCIe user clock 2 frequency
.PCIE_OOBCLK_MODE (PCIE_OOBCLK_MODE), // PCIe OOB clock mode
.PCIE_DEBUG_MODE (PCIE_DEBUG_MODE) // PCIe debug mode
)
pipe_clock_i
(
//---------- Input -------------------------------------
.CLK_CLK (PIPE_CLK),
.CLK_TXOUTCLK (gt_txoutclk[0]), // Reference clock from lane 0
.CLK_RXOUTCLK_IN (gt_rxoutclk),
//.CLK_RST_N (1'b1),
.CLK_RST_N (PIPE_MMCM_RST_N), // Allow system reset for error recovery
.CLK_PCLK_SEL (rate_pclk_sel),
.CLK_PCLK_SEL_SLAVE (INT_PCLK_SEL_SLAVE ),
.CLK_GEN3 (rate_gen3[0]),
//---------- Output ------------------------------------
.CLK_PCLK (clk_pclk),
.CLK_PCLK_SLAVE (INT_PCLK_OUT_SLAVE),
.CLK_RXUSRCLK (clk_rxusrclk),
.CLK_RXOUTCLK_OUT (clk_rxoutclk),
.CLK_DCLK (clk_dclk),
.CLK_USERCLK1 (PIPE_USERCLK1),
.CLK_USERCLK2 (PIPE_USERCLK2),
.CLK_OOBCLK (clk_oobclk),
.CLK_MMCM_LOCK (clk_mmcm_lock)
);
assign INT_RXUSRCLK_OUT = clk_rxusrclk;
assign INT_RXOUTCLK_OUT = clk_rxoutclk;
assign INT_DCLK_OUT = clk_dclk;
assign INT_USERCLK1_OUT = PIPE_USERCLK1;
assign INT_USERCLK2_OUT = PIPE_USERCLK2;
assign INT_OOBCLK_OUT = clk_oobclk;
assign INT_MMCM_LOCK_OUT = clk_mmcm_lock;
end
endgenerate
//---------- PIPE Reset Module -------------------------------------------------
generate
if (PCIE_GT_DEVICE == "GTP")
begin : gtp_pipe_reset
//---------- GTP PIPE Reset Module -------------------------------------
PCIeGen2x8If128_gtp_pipe_reset #
(
.PCIE_SIM_SPEEDUP (PCIE_SIM_SPEEDUP), // PCIe sim mode
//.PCIE_PLL_SEL (PCIE_PLL_SEL), // removed for GTP
//.PCIE_POWER_SAVING (PCIE_POWER_SAVING), // removed for GTP
//.PCIE_TXBUF_EN (PCIE_TXBUF_EN), // PCIe TX buffer enable for Gen1/Gen2 only
.PCIE_LANE (PCIE_LANE) // PCIe number of lanes
)
gtp_pipe_reset_i
(
//---------- Input -----------------------------
.RST_CLK (clk_pclk),
.RST_RXUSRCLK (clk_rxusrclk),
.RST_DCLK (clk_dclk),
.RST_RST_N (reset_n_reg2),
.RST_DRP_DONE (drp_done),
.RST_RXPMARESETDONE (gt_rxpmaresetdone),
.RST_PLLLOCK (&qpll_qplllock),
//.RST_QPLL_IDLE (qrst_idle), // removed for GTP
.RST_RATE_IDLE (rate_idle),
.RST_RXCDRLOCK (user_rxcdrlock),
.RST_MMCM_LOCK (clk_mmcm_lock),
.RST_RESETDONE (user_resetdone),
.RST_PHYSTATUS (gt_phystatus),
.RST_TXSYNC_DONE (sync_txsync_done),
//---------- Output ----------------------------
.RST_CPLLRESET (rst_cpllreset),
.RST_CPLLPD (rst_cpllpd),
.RST_RXUSRCLK_RESET (rst_rxusrclk_reset),
.RST_DCLK_RESET (rst_dclk_reset),
.RST_GTRESET (rst_gtreset),
.RST_DRP_START (rst_drp_start),
.RST_DRP_X16 (rst_drp_x16),
.RST_USERRDY (rst_userrdy),
.RST_TXSYNC_START (rst_txsync_start),
.RST_IDLE (rst_idle),
.RST_FSM (rst_fsm)
);
//---------- Default ---------------------------------------------------
assign gtp_rst_qpllreset = rst_cpllreset;
assign gtp_rst_qpllpd = rst_cpllpd;
end
else
begin : pipe_reset
//---------- PIPE Reset Module -----------------------------------------
PCIeGen2x8If128_pipe_reset #
(
.PCIE_SIM_SPEEDUP (PCIE_SIM_SPEEDUP), // PCIe sim mode
.PCIE_GT_DEVICE (PCIE_GT_DEVICE), // PCIe GT Device
.PCIE_PLL_SEL (PCIE_PLL_SEL), // PCIe PLL select for Gen1/Gen2 only
.PCIE_POWER_SAVING (PCIE_POWER_SAVING), // PCIe power saving
.PCIE_TXBUF_EN (PCIE_TXBUF_EN), // PCIe TX buffer enable for Gen1/Gen2 only
.PCIE_LANE (PCIE_LANE) // PCIe number of lanes
)
pipe_reset_i
(
//---------- Input -----------------------------
.RST_CLK (clk_pclk),
.RST_RXUSRCLK (clk_rxusrclk),
.RST_DCLK (clk_dclk),
.RST_RST_N (reset_n_reg2),
.RST_DRP_DONE (drp_done),
.RST_RXPMARESETDONE (gt_rxpmaresetdone),
.RST_CPLLLOCK (gt_cplllock),
.RST_QPLL_IDLE (qrst_idle),
.RST_RATE_IDLE (rate_idle),
.RST_RXCDRLOCK (user_rxcdrlock),
.RST_MMCM_LOCK (clk_mmcm_lock),
.RST_RESETDONE (user_resetdone),
.RST_PHYSTATUS (gt_phystatus),
.RST_TXSYNC_DONE (sync_txsync_done),
//---------- Output ----------------------------
.RST_CPLLRESET (rst_cpllreset),
.RST_CPLLPD (rst_cpllpd),
.RST_RXUSRCLK_RESET (rst_rxusrclk_reset),
.RST_DCLK_RESET (rst_dclk_reset),
.RST_GTRESET (rst_gtreset),
.RST_DRP_START (rst_drp_start),
.RST_DRP_X16X20_MODE (rst_drp_x16x20_mode),
.RST_DRP_X16 (rst_drp_x16),
.RST_USERRDY (rst_userrdy),
.RST_TXSYNC_START (rst_txsync_start),
.RST_IDLE (rst_idle),
.RST_FSM (rst_fsm[4:0])
);
//---------- Default ---------------------------------------------------
assign gtp_rst_qpllreset = 1'd0;
assign gtp_rst_qpllpd = 1'd0;
end
endgenerate
//---------- QPLL Reset Module -------------------------------------------------
generate
if ((PCIE_LINK_SPEED == 3) || (PCIE_PLL_SEL == "QPLL"))
begin : qpll_reset
PCIeGen2x8If128_qpll_reset #
(
.PCIE_PLL_SEL (PCIE_PLL_SEL), // PCIe PLL select for Gen1/Gen2 only
.PCIE_POWER_SAVING (PCIE_POWER_SAVING),// PCIe power saving
.PCIE_LANE (PCIE_LANE) // PCIe number of lanes
)
qpll_reset_i
(
//---------- Input ---------------------------------
.QRST_CLK (clk_pclk),
.QRST_RST_N (reset_n_reg2),
.QRST_MMCM_LOCK (clk_mmcm_lock),
.QRST_CPLLLOCK (gt_cplllock),
.QRST_DRP_DONE (qdrp_done),
.QRST_QPLLLOCK (qpll_qplllock),
.QRST_RATE (PIPE_RATE),
.QRST_QPLLRESET_IN (rate_qpllreset),
.QRST_QPLLPD_IN (rate_qpllpd),
//---------- Output --------------------------------
.QRST_OVRD (qrst_ovrd),
.QRST_DRP_START (qrst_drp_start),
.QRST_QPLLRESET_OUT (qrst_qpllreset),
.QRST_QPLLPD_OUT (qrst_qpllpd),
.QRST_IDLE (qrst_idle),
.QRST_FSM (qrst_fsm)
);
end
else
//---------- QPLL Reset Defaults ---------------------------------------
begin : qpll_reset_disable
assign qrst_ovrd = 1'd0;
assign qrst_drp_start = 1'd0;
assign qrst_qpllreset = 1'd0;
assign qrst_qpllpd = 1'd0;
assign qrst_idle = 1'd0;
assign qrst_fsm = 1;
end
endgenerate
assign jtag_sl_iport = {PCIE_LANE{37'd0}};
//Reference Clock for CPLLPD Fix
wire gt_cpllpdrefclk;
BUFG cpllpd_refclk_inst (.I (PIPE_CLK), .O (gt_cpllpdrefclk));
//---------- Generate PIPE Lane ------------------------------------------------
generate for (i=0; i<PCIE_LANE; i=i+1)
begin : pipe_lane
//---------- PIPE User Module ----------------------------------------------
PCIeGen2x8If128_pipe_user #
(
.PCIE_USE_MODE (PCIE_USE_MODE),
.PCIE_OOBCLK_MODE (PCIE_OOBCLK_MODE)
)
pipe_user_i
(
//---------- Input ---------------------------------
.USER_TXUSRCLK (clk_pclk),
.USER_RXUSRCLK (clk_rxusrclk),
.USER_OOBCLK_IN (clk_oobclk),
.USER_RST_N (!rst_cpllreset),
.USER_RXUSRCLK_RST_N (!rst_rxusrclk_reset),
.USER_PCLK_SEL (rate_pclk_sel[i]),
.USER_RESETOVRD_START (rate_resetovrd_start[i]),
.USER_TXRESETDONE (gt_txresetdone[i]),
.USER_RXRESETDONE (gt_rxresetdone[i]),
.USER_TXELECIDLE (PIPE_TXELECIDLE[i]),
.USER_TXCOMPLIANCE (PIPE_TXCOMPLIANCE[i]),
.USER_RXCDRLOCK_IN (gt_rxcdrlock[i]),
.USER_RXVALID_IN (gt_rxvalid[i]),
.USER_RXSTATUS_IN (gt_rxstatus[(3*i)+2]),
.USER_PHYSTATUS_IN (gt_phystatus[i]),
.USER_RATE_DONE (rate_done[i]),
.USER_RST_IDLE (rst_idle),
.USER_RATE_RXSYNC (rate_rxsync[i]),
.USER_RATE_IDLE (rate_idle[i]),
.USER_RATE_GEN3 (rate_gen3[i]),
.USER_RXEQ_ADAPT_DONE (eq_rxeq_adapt_done[i]),
//---------- Output --------------------------------
.USER_OOBCLK (user_oobclk[i]),
.USER_RESETOVRD (user_resetovrd[i]),
.USER_TXPMARESET (user_txpmareset[i]),
.USER_RXPMARESET (user_rxpmareset[i]),
.USER_RXCDRRESET (user_rxcdrreset[i]),
.USER_RXCDRFREQRESET (user_rxcdrfreqreset[i]),
.USER_RXDFELPMRESET (user_rxdfelpmreset[i]),
.USER_EYESCANRESET (user_eyescanreset[i]),
.USER_TXPCSRESET (user_txpcsreset[i]),
.USER_RXPCSRESET (user_rxpcsreset[i]),
.USER_RXBUFRESET (user_rxbufreset[i]),
.USER_RESETOVRD_DONE (user_resetovrd_done[i]),
.USER_RESETDONE (user_resetdone[i]),
.USER_ACTIVE_LANE (user_active_lane[i]),
.USER_RXCDRLOCK_OUT (user_rxcdrlock[i]),
.USER_RXVALID_OUT (PIPE_RXVALID[i]),
.USER_PHYSTATUS_OUT (PIPE_PHYSTATUS[i]),
.USER_PHYSTATUS_RST (PIPE_PHYSTATUS_RST[i]),
.USER_GEN3_RDY (PIPE_GEN3_RDY[i]),
.USER_RX_CONVERGE (user_rx_converge[i])
);
//---------- GTP PIPE Rate Module ------------------------------------------
if (PCIE_GT_DEVICE == "GTP")
begin : gtp_pipe_rate
PCIeGen2x8If128_gtp_pipe_rate #
(
.PCIE_SIM_SPEEDUP (PCIE_SIM_SPEEDUP) // PCIe sim speedup
//.PCIE_USE_MODE (PCIE_USE_MODE), // removed for GTP
//.PCIE_PLL_SEL (PCIE_PLL_SEL), // removed for GTP
//.PCIE_POWER_SAVING (PCIE_POWER_SAVING), // removed for GTP
//.PCIE_ASYNC_EN (PCIE_ASYNC_EN), // removed for GTP
//.PCIE_TXBUF_EN (PCIE_TXBUF_EN), // removed for GTP
//.PCIE_RXBUF_EN (PCIE_RXBUF_EN) // removed for GTP
)
gtp_pipe_rate_i
(
//---------- Input -----------------------------
.RATE_CLK (clk_pclk),
.RATE_RST_N (!rst_cpllreset),
//.RATE_RST_IDLE (rst_idle), // removed for GTP
//.RATE_ACTIVE_LANE (user_active_lane[i]), // removed for GTP
.RATE_RATE_IN (PIPE_RATE),
//.RATE_CPLLLOCK (gt_cplllock[i]), // removed for GTP
//.RATE_QPLLLOCK (qpll_qplllock[i>>2]) // removed for GTP
//.RATE_MMCM_LOCK (clk_mmcm_lock), // removed for GTP
.RATE_DRP_DONE (drp_done[i]),
.RATE_RXPMARESETDONE (gt_rxpmaresetdone[i]),
//.RATE_TXRESETDONE (gt_txresetdone[i]), // removed for GTP
//.RATE_RXRESETDONE (gt_rxresetdone[i]), // removed for GTP
.RATE_TXRATEDONE (gt_txratedone[i]),
.RATE_RXRATEDONE (gt_rxratedone[i]),
.RATE_PHYSTATUS (gt_phystatus[i]),
//.RATE_RESETOVRD_DONE (user_resetovrd_done[i]), // removed for GTP
.RATE_TXSYNC_DONE (sync_txsync_done[i]),
//.RATE_RXSYNC_DONE (sync_rxsync_done[i]), // removed for GTP
//---------- Output ----------------------------
//.RATE_CPLLPD (rate_cpllpd[i]), // removed for GTP
//.RATE_QPLLPD (rate_qpllpd[i]), // removed for GTP
//.RATE_CPLLRESET (rate_cpllreset[i]), // removed for GTP
//.RATE_QPLLRESET (rate_qpllreset[i]), // removed for GTP
//.RATE_TXPMARESET (rate_txpmareset[i]), // removed for GTP
//.RATE_RXPMARESET (rate_rxpmareset[i]), // removed for GTP
//.RATE_SYSCLKSEL (rate_sysclksel[(2*i)+1:(2*i)]), // removed for GTP
.RATE_DRP_START (rate_drp_start[i]),
.RATE_DRP_X16 (rate_drp_x16[i]),
.RATE_PCLK_SEL (rate_pclk_sel[i]),
//.RATE_GEN3 (rate_gen3[i]), // removed for GTP
.RATE_RATE_OUT (rate_rate[(3*i)+2:(3*i)]),
//.RATE_RESETOVRD_START (rate_resetovrd_start[i]), // removed for GTP
.RATE_TXSYNC_START (rate_txsync_start[i]),
.RATE_DONE (rate_done[i]),
//.RATE_RXSYNC_START (rate_rxsync_start[i]), // removed for GTP
//.RATE_RXSYNC (rate_rxsync[i]), // removed for GTP
.RATE_IDLE (rate_idle[i]),
.RATE_FSM (rate_fsm[(5*i)+4:(5*i)])
);
//---------- Default for GTP -----------------------
assign rate_cpllpd[i] = 1'd0;
assign rate_qpllpd[i] = 1'd0;
assign rate_cpllreset[i] = 1'd0;
assign rate_qpllreset[i] = 1'd0;
assign rate_txpmareset[i] = 1'd0;
assign rate_rxpmareset[i] = 1'd0;
assign rate_sysclksel[(2*i)+1:(2*i)] = 2'b0;
assign rate_gen3[i] = 1'd0;
assign rate_resetovrd_start[i] = 1'd0;
assign rate_rxsync_start[i] = 1'd0;
assign rate_rxsync[i] = 1'd0;
end
else
begin : pipe_rate
//---------- PIPE Rate Module ----------------------------------------------
PCIeGen2x8If128_pipe_rate #
(
.PCIE_SIM_SPEEDUP (PCIE_SIM_SPEEDUP), // PCIe sim speedup
.PCIE_GT_DEVICE (PCIE_GT_DEVICE), // PCIe GT device
.PCIE_USE_MODE (PCIE_USE_MODE), // PCIe use mode
.PCIE_PLL_SEL (PCIE_PLL_SEL), // PCIe PLL select for Gen1/Gen2 only
.PCIE_POWER_SAVING (PCIE_POWER_SAVING),// PCIe power saving
.PCIE_ASYNC_EN (PCIE_ASYNC_EN), // PCIe async enable
.PCIE_TXBUF_EN (PCIE_TXBUF_EN), // PCIe TX buffer enable for Gen1/Gen2 only
.PCIE_RXBUF_EN (PCIE_RXBUF_EN) // PCIe RX buffer enable for Gen3 only
)
pipe_rate_i
(
//---------- Input ---------------------------------
.RATE_CLK (clk_pclk),
.RATE_RST_N (!rst_cpllreset),
.RATE_RST_IDLE (rst_idle),
.RATE_ACTIVE_LANE (user_active_lane[i]),
.RATE_RATE_IN (PIPE_RATE),
.RATE_CPLLLOCK (gt_cplllock[i]),
.RATE_QPLLLOCK (qpll_qplllock[i>>2]),
.RATE_MMCM_LOCK (clk_mmcm_lock),
.RATE_DRP_DONE (drp_done[i]),
.RATE_RXPMARESETDONE (gt_rxpmaresetdone[i]),
.RATE_TXRESETDONE (gt_txresetdone[i]),
.RATE_RXRESETDONE (gt_rxresetdone[i]),
.RATE_TXRATEDONE (gt_txratedone[i]),
.RATE_RXRATEDONE (gt_rxratedone[i]),
.RATE_PHYSTATUS (gt_phystatus[i]),
.RATE_RESETOVRD_DONE (user_resetovrd_done[i]),
.RATE_TXSYNC_DONE (sync_txsync_done[i]),
.RATE_RXSYNC_DONE (sync_rxsync_done[i]),
//---------- Output --------------------------------
.RATE_CPLLPD (rate_cpllpd[i]),
.RATE_QPLLPD (rate_qpllpd[i]),
.RATE_CPLLRESET (rate_cpllreset[i]),
.RATE_QPLLRESET (rate_qpllreset[i]),
.RATE_TXPMARESET (rate_txpmareset[i]),
.RATE_RXPMARESET (rate_rxpmareset[i]),
.RATE_SYSCLKSEL (rate_sysclksel[(2*i)+1:(2*i)]),
.RATE_DRP_START (rate_drp_start[i]),
.RATE_DRP_X16X20_MODE (rate_drp_x16x20_mode[i]),
.RATE_DRP_X16 (rate_drp_x16[i]),
.RATE_PCLK_SEL (rate_pclk_sel[i]),
.RATE_GEN3 (rate_gen3[i]),
.RATE_RATE_OUT (rate_rate[(3*i)+2:(3*i)]),
.RATE_RESETOVRD_START (rate_resetovrd_start[i]),
.RATE_TXSYNC_START (rate_txsync_start[i]),
.RATE_DONE (rate_done[i]),
.RATE_RXSYNC_START (rate_rxsync_start[i]),
.RATE_RXSYNC (rate_rxsync[i]),
.RATE_IDLE (rate_idle[i]),
.RATE_FSM (rate_fsm[(5*i)+4:(5*i)])
);
end
//---------- PIPE Sync Module ----------------------------------------------
PCIeGen2x8If128_pipe_sync #
(
.PCIE_GT_DEVICE (PCIE_GT_DEVICE), // PCIe GT Device
.PCIE_TXBUF_EN (PCIE_TXBUF_EN), // PCIe TX buffer enable for Gen1/Gen2 only
.PCIE_RXBUF_EN (PCIE_RXBUF_EN), // PCIe RX buffer enable for Gen3 only
.PCIE_TXSYNC_MODE (PCIE_TXSYNC_MODE), // PCIe TX sync mode
.PCIE_RXSYNC_MODE (PCIE_RXSYNC_MODE), // PCIe RX sync mode
.PCIE_LANE (PCIE_LANE), // PCIe lane
.PCIE_LINK_SPEED (PCIE_LINK_SPEED) // PCIe link speed
)
pipe_sync_i
(
//---------- Input ---------------------------------
.SYNC_CLK (clk_pclk),
.SYNC_RST_N (!rst_cpllreset),
.SYNC_SLAVE (i > 0),
.SYNC_GEN3 (rate_gen3[i]),
.SYNC_RATE_IDLE (rate_idle[i]),
.SYNC_MMCM_LOCK (clk_mmcm_lock),
.SYNC_RXELECIDLE (gt_rxelecidle[i]),
.SYNC_RXCDRLOCK (user_rxcdrlock[i]),
.SYNC_ACTIVE_LANE (user_active_lane[i]),
.SYNC_TXSYNC_START (rate_txsync_start[i] || rst_txsync_start),
.SYNC_TXPHINITDONE (&(gt_txphinitdone | (~user_active_lane))),
.SYNC_TXDLYSRESETDONE (txdlysresetdone[i]),
.SYNC_TXPHALIGNDONE (txphaligndone[i]),
.SYNC_TXSYNCDONE (gt_txsyncdone[i]), // GTH
.SYNC_RXSYNC_START (rate_rxsync_start[i]),
.SYNC_RXDLYSRESETDONE (rxdlysresetdone[i]),
.SYNC_RXPHALIGNDONE_M (gt_rxphaligndone[0]),
.SYNC_RXPHALIGNDONE_S (rxphaligndone_s[i]),
.SYNC_RXSYNC_DONEM_IN (sync_rxsync_donem[0]),
.SYNC_RXSYNCDONE (gt_rxsyncdone[i]), // GTH
//---------- Output --------------------------------
.SYNC_TXPHDLYRESET (sync_txphdlyreset[i]),
.SYNC_TXPHALIGN (sync_txphalign[i]),
.SYNC_TXPHALIGNEN (sync_txphalignen[i]),
.SYNC_TXPHINIT (sync_txphinit[i]),
.SYNC_TXDLYBYPASS (sync_txdlybypass[i]),
.SYNC_TXDLYSRESET (sync_txdlysreset[i]),
.SYNC_TXDLYEN (sync_txdlyen[i]),
.SYNC_TXSYNC_DONE (sync_txsync_done[i]),
.SYNC_FSM_TX (sync_fsm_tx[(6*i)+5:(6*i)]),
.SYNC_RXPHALIGN (sync_rxphalign[i]),
.SYNC_RXPHALIGNEN (sync_rxphalignen[i]),
.SYNC_RXDLYBYPASS (sync_rxdlybypass[i]),
.SYNC_RXDLYSRESET (sync_rxdlysreset[i]),
.SYNC_RXDLYEN (sync_rxdlyen[i]),
.SYNC_RXDDIEN (sync_rxddien[i]),
.SYNC_RXSYNC_DONEM_OUT (sync_rxsync_donem[i]),
.SYNC_RXSYNC_DONE (sync_rxsync_done[i]),
.SYNC_FSM_RX (sync_fsm_rx[(7*i)+6:(7*i)])
);
//---------- PIPE Sync Assignments -----------------------------------------
assign txdlysresetdone[i] = (PCIE_TXSYNC_MODE == 1) ? gt_txdlysresetdone[i] : >_txdlysresetdone;
assign txphaligndone[i] = (PCIE_TXSYNC_MODE == 1) ? gt_txphaligndone[i] : &(gt_txphaligndone | (~user_active_lane));
assign rxdlysresetdone[i] = (PCIE_RXSYNC_MODE == 1) ? gt_rxdlysresetdone[i] : >_rxdlysresetdone;
assign rxphaligndone_s[i] = (PCIE_LANE == 1) ? 1'd0 : >_rxphaligndone[PCIE_LANE:1];
//---------- GTP PIPE DRP Module -------------------------------------------
if (PCIE_GT_DEVICE == "GTP")
begin : gtp_pipe_drp
//---------- GTP PIPE DRP Module ---------------------------------------
PCIeGen2x8If128_gtp_pipe_drp
gtp_pipe_drp_i
(
//---------- Input ---------------------------------
.DRP_CLK (clk_dclk),
.DRP_RST_N (!rst_dclk_reset),
.DRP_X16 (rst_drp_x16 || rate_drp_x16[i]),
.DRP_START (rst_drp_start || rate_drp_start[i]),
.DRP_DO (gt_do[(16*i)+15:(16*i)]),
.DRP_RDY (gt_rdy[i]),
//---------- Output --------------------------------
.DRP_ADDR (drp_addr[(9*i)+8:(9*i)]),
.DRP_EN (drp_en[i]),
.DRP_DI (drp_di[(16*i)+15:(16*i)]),
.DRP_WE (drp_we[i]),
.DRP_DONE (drp_done[i]),
.DRP_FSM (drp_fsm[(3*i)+2:(3*i)])
);
end
else
begin : pipe_drp
//---------- PIPE DRP Module -------------------------------------------
PCIeGen2x8If128_pipe_drp #
(
.PCIE_GT_DEVICE (PCIE_GT_DEVICE), // PCIe GT device
.PCIE_USE_MODE (PCIE_USE_MODE), // PCIe use mode
.PCIE_PLL_SEL (PCIE_PLL_SEL), // PCIe PLL select for Gen1/Gen2 only
.PCIE_AUX_CDR_GEN3_EN (PCIE_AUX_CDR_GEN3_EN), // PCIe AUX CDR Gen3 enable
.PCIE_ASYNC_EN (PCIE_ASYNC_EN), // PCIe async enable
.PCIE_TXBUF_EN (PCIE_TXBUF_EN), // PCIe TX buffer enable for Gen1/Gen2 only
.PCIE_RXBUF_EN (PCIE_RXBUF_EN), // PCIe RX buffer enable for Gen3 only
.PCIE_TXSYNC_MODE (PCIE_TXSYNC_MODE), // PCIe TX sync mode
.PCIE_RXSYNC_MODE (PCIE_RXSYNC_MODE) // PCIe RX sync mode
)
pipe_drp_i
(
//---------- Input ---------------------------------
.DRP_CLK (clk_dclk),
.DRP_RST_N (!rst_dclk_reset),
.DRP_GTXRESET (rst_gtreset),
.DRP_RATE (PIPE_RATE),
.DRP_X16X20_MODE (rst_drp_x16x20_mode || rate_drp_x16x20_mode[i]),
.DRP_X16 (rst_drp_x16 || rate_drp_x16[i]),
.DRP_START (rst_drp_start || rate_drp_start[i]),
.DRP_DO (gt_do[(16*i)+15:(16*i)]),
.DRP_RDY (gt_rdy[i]),
//---------- Output --------------------------------
.DRP_ADDR (drp_addr[(9*i)+8:(9*i)]),
.DRP_EN (drp_en[i]),
.DRP_DI (drp_di[(16*i)+15:(16*i)]),
.DRP_WE (drp_we[i]),
.DRP_DONE (drp_done[i]),
.DRP_FSM (drp_fsm[(3*i)+2:(3*i)])
);
end
assign jtag_sl_oport[((i+1)*17)-1 : (i*17)] = 17'd0;
assign jtag_sl_addr[(17*i)+16:(17*i)] = 17'd0;
assign jtag_sl_den[i] = 1'd0;
assign jtag_sl_di[(16*i)+15:(16*i)] = 16'd0;
assign jtag_sl_we[i] = 1'd0;
//---------- Generate DRP MUX ----------------------------------------------
assign PIPE_JTAG_RDY[i] = (drp_fsm[(3*i)+2:(3*i)] == 3'b000);
assign jtag_sl_en[i] = (jtag_sl_addr[(17*i)+16:(17*i)+9] == 8'd0) ? jtag_sl_den[i] : 1'd0;
// Channel DRP
assign drp_mux_en[i] = (PIPE_JTAG_RDY[i] && EXT_CH_GT_DRP) ? EXT_CH_GT_DRPEN[i] : drp_en[i];
assign drp_mux_di[(16*i)+15:(16*i)] = (PIPE_JTAG_RDY[i] && EXT_CH_GT_DRP) ? EXT_CH_GT_DRPDI[(16*i)+15:(16*i)] : drp_di[(16*i)+15:(16*i)];
assign drp_mux_addr[(9*i)+8:(9*i)] = (PIPE_JTAG_RDY[i] && EXT_CH_GT_DRP) ? EXT_CH_GT_DRPADDR[(9*i)+8:(9*i)] : drp_addr[(9*i)+8:(9*i)];
assign drp_mux_we[i] = (PIPE_JTAG_RDY[i] && EXT_CH_GT_DRP) ? EXT_CH_GT_DRPWE[i] : drp_we[i];
//---------- Generate PIPE EQ ----------------------------------------------
if (PCIE_LINK_SPEED == 3)
begin : pipe_eq
//---------- PIPE EQ Module --------------------------------------------
PCIeGen2x8If128_pipe_eq #
(
.PCIE_SIM_MODE (PCIE_SIM_MODE), // PCIe sim mode
.PCIE_GT_DEVICE (PCIE_GT_DEVICE),
.PCIE_RXEQ_MODE_GEN3 (PCIE_RXEQ_MODE_GEN3) // PCIe RX equalization mode
)
pipe_eq_i
(
//---------- Input -----------------------------
.EQ_CLK (clk_pclk),
.EQ_RST_N (!rst_cpllreset),
.EQ_GEN3 (rate_gen3[i]),
.EQ_TXEQ_CONTROL (PIPE_TXEQ_CONTROL[(2*i)+1:(2*i)]),
.EQ_TXEQ_PRESET (PIPE_TXEQ_PRESET[(4*i)+3:(4*i)]),
.EQ_TXEQ_PRESET_DEFAULT (PIPE_TXEQ_PRESET_DEFAULT[(4*i)+3:(4*i)]),
.EQ_TXEQ_DEEMPH_IN (PIPE_TXEQ_DEEMPH[(6*i)+5:(6*i)]), // renamed
.EQ_RXEQ_CONTROL (PIPE_RXEQ_CONTROL[(2*i)+1:(2*i)]),
.EQ_RXEQ_PRESET (PIPE_RXEQ_PRESET[(3*i)+2:(3*i)]),
.EQ_RXEQ_LFFS (PIPE_RXEQ_LFFS[(6*i)+5:(6*i)]),
.EQ_RXEQ_TXPRESET (PIPE_RXEQ_TXPRESET[(4*i)+3:(4*i)]),
.EQ_RXEQ_USER_EN (PIPE_RXEQ_USER_EN[i]),
.EQ_RXEQ_USER_TXCOEFF (PIPE_RXEQ_USER_TXCOEFF[(18*i)+17:(18*i)]),
.EQ_RXEQ_USER_MODE (PIPE_RXEQ_USER_MODE[i]),
//---------- Output ----------------------------
.EQ_TXEQ_DEEMPH (eq_txeq_deemph[i]),
.EQ_TXEQ_PRECURSOR (eq_txeq_precursor[(5*i)+4:(5*i)]),
.EQ_TXEQ_MAINCURSOR (eq_txeq_maincursor[(7*i)+6:(7*i)]),
.EQ_TXEQ_POSTCURSOR (eq_txeq_postcursor[(5*i)+4:(5*i)]),
.EQ_TXEQ_DEEMPH_OUT (PIPE_TXEQ_COEFF[(18*i)+17:(18*i)]),// renamed
.EQ_TXEQ_DONE (PIPE_TXEQ_DONE[i]),
.EQ_TXEQ_FSM (PIPE_TXEQ_FSM[(6*i)+5:(6*i)]),
.EQ_RXEQ_NEW_TXCOEFF (PIPE_RXEQ_NEW_TXCOEFF[(18*i)+17:(18*i)]),
.EQ_RXEQ_LFFS_SEL (PIPE_RXEQ_LFFS_SEL[i]),
.EQ_RXEQ_ADAPT_DONE (eq_rxeq_adapt_done[i]),
.EQ_RXEQ_DONE (PIPE_RXEQ_DONE[i]),
.EQ_RXEQ_FSM (PIPE_RXEQ_FSM[(6*i)+5:(6*i)])
);
end
else
//---------- PIPE EQ Defaults ------------------------------------------
begin : pipe_eq_disable
assign eq_txeq_deemph[i] = 1'd0;
assign eq_txeq_precursor[(5*i)+4:(5*i)] = 5'h00;
assign eq_txeq_maincursor[(7*i)+6:(7*i)] = 7'h00;
assign eq_txeq_postcursor[(5*i)+4:(5*i)] = 5'h00;
assign eq_rxeq_adapt_done[i] = 1'd0;
assign PIPE_TXEQ_COEFF[(18*i)+17:(18*i)] = 18'd0;
assign PIPE_TXEQ_DONE[i] = 1'd0;
assign PIPE_TXEQ_FSM[(6*i)+5:(6*i)] = 6'd0;
assign PIPE_RXEQ_NEW_TXCOEFF[(18*i)+17:(18*i)] = 18'd0;
assign PIPE_RXEQ_LFFS_SEL[i] = 1'd0;
assign PIPE_RXEQ_ADAPT_DONE[i] = 1'd0;
assign PIPE_RXEQ_DONE[i] = 1'd0;
assign PIPE_RXEQ_FSM[(6*i)+5:(6*i)] = 6'd0;
end
//---------- Generate PIPE Common Per Quad for Gen3 ------------------------
if ((i%4)==0)
begin : pipe_quad
//---------- Generate QPLL Powerdown and Reset -------------------------
assign qpllpd = (PCIE_GT_DEVICE == "GTP") ? gtp_rst_qpllpd : qrst_qpllpd;
assign qpllreset[i>>2] = (PCIE_GT_DEVICE == "GTP") ? gtp_rst_qpllreset : (qrst_qpllreset || qdrp_qpllreset[i>>2]);
if ((PCIE_LINK_SPEED == 3) || (PCIE_PLL_SEL == "QPLL") || (PCIE_GT_DEVICE == "GTP"))
begin : gt_common_enabled
if (PCIE_EXT_GT_COMMON == "FALSE")
begin : gt_common_int
//---------- GT COMMON INTERNAL Module ---------------------------------------
PCIeGen2x8If128_gt_common #
(
.PCIE_SIM_MODE (PCIE_SIM_MODE), // PCIe sim mode
.PCIE_GT_DEVICE (PCIE_GT_DEVICE), // PCIe GT device
.PCIE_USE_MODE (PCIE_USE_MODE), // PCIe use mode
.PCIE_PLL_SEL (PCIE_PLL_SEL), // PCIe PLL select for Gen1/Gen2 only
.PCIE_REFCLK_FREQ (PCIE_REFCLK_FREQ) // PCIe reference clock frequency
)
gt_common_i
(
//---------- Input -------------------------
.CPLLPDREFCLK (gt_cpllpdrefclk),
.PIPE_CLK (PIPE_CLK),
.QPLL_QPLLPD (qpllpd),
.QPLL_QPLLRESET (qpllreset[i>>2]),
.QPLL_DRP_CLK (clk_dclk),
.QPLL_DRP_RST_N (rst_dclk_reset),
.QPLL_DRP_OVRD (qrst_ovrd),
.QPLL_DRP_GEN3 (&rate_gen3),
.QPLL_DRP_START (qrst_drp_start),
.QPLL_DRP_CRSCODE (qdrp_crscode[(6*(i>>2))+5:(6*(i>>2))]),
.QPLL_DRP_FSM (qdrp_fsm[(9*(i>>2))+8:(9*(i>>2))]),
.QPLL_DRP_DONE (qdrp_done[i>>2]),
.QPLL_DRP_RESET (qdrp_qpllreset[i>>2]),
.QPLL_QPLLOUTCLK (qpll_qplloutclk[i>>2]),
.QPLL_QPLLOUTREFCLK (qpll_qplloutrefclk[i>>2]),
.QPLL_QPLLLOCK (qpll_qplllock[i>>2])
);
assign QPLL_QPLLPD = 1'b0;
assign QPLL_QPLLRESET[i>>2] = 1'b0;
assign QPLL_DRP_CLK = 1'b0;
assign QPLL_DRP_RST_N = 1'b0;
assign QPLL_DRP_OVRD = 1'b0;
assign QPLL_DRP_GEN3 = 1'b0;
assign QPLL_DRP_START = 1'b0;
assign INT_QPLLLOCK_OUT[i>>2] = qpll_qplllock[i>>2] ;
assign INT_QPLLOUTREFCLK_OUT[i>>2] = qpll_qplloutrefclk[i>>2];
assign INT_QPLLOUTCLK_OUT[i>>2] = qpll_qplloutclk[i>>2];
end
else
begin : gt_common_ext
assign qdrp_done[i>>2] = QPLL_DRP_DONE[i>>2];
assign qdrp_qpllreset[i>>2] = QPLL_DRP_RESET[i>>2];
assign qdrp_crscode[(6*(i>>2))+5:(6*(i>>2))] = QPLL_DRP_CRSCODE[(6*(i>>2))+5:(6*(i>>2))];
assign qdrp_fsm[(9*(i>>2))+8:(9*(i>>2))] = QPLL_DRP_FSM[(9*(i>>2))+8:(9*(i>>2))];
assign qpll_qplloutclk[i>>2] = QPLL_QPLLOUTCLK[i>>2];
assign qpll_qplloutrefclk[i>>2] = QPLL_QPLLOUTREFCLK[i>>2];
assign qpll_qplllock[i>>2] = QPLL_QPLLLOCK[i>>2];
assign QPLL_QPLLPD = qpllpd;
assign QPLL_QPLLRESET[i>>2] = qpllreset[i>>2];
assign QPLL_DRP_CLK = clk_dclk;
assign QPLL_DRP_RST_N = rst_dclk_reset;
assign QPLL_DRP_OVRD = qrst_ovrd;
assign QPLL_DRP_GEN3 = &rate_gen3;
assign QPLL_DRP_START = qrst_drp_start;
assign INT_QPLLLOCK_OUT[i>>2] = 1'b0;
assign INT_QPLLOUTCLK_OUT[i>>2] = 1'b0;
assign INT_QPLLOUTREFCLK_OUT[i>>2] = 1'b0;
end
end
else
//---------- PIPE Common Defaults ----------------------------------
begin : gt_common_disabled
assign qdrp_done[i>>2] = 1'd0;
assign qdrp_crscode[(6*(i>>2))+5:(6*(i>>2))] = 6'd0;
assign qdrp_fsm[(9*(i>>2))+8:(9*(i>>2))] = 9'd0;
assign qpll_qplloutclk[i>>2] = 1'd0;
assign qpll_qplloutrefclk[i>>2] = 1'd0;
assign qpll_qplllock[i>>2] = 1'd0;
assign QPLL_QPLLPD = 1'b0;
assign QPLL_QPLLRESET[i>>2] = 1'b0;
assign QPLL_DRP_CLK = 1'b0;
assign QPLL_DRP_RST_N = 1'b0;
assign QPLL_DRP_OVRD = 1'b0;
assign QPLL_DRP_GEN3 = 1'b0;
assign QPLL_DRP_START = 1'b0;
assign INT_QPLLLOCK_OUT[i>>2] = 1'b0;
assign INT_QPLLOUTCLK_OUT[i>>2] = 1'b0;
assign INT_QPLLOUTREFCLK_OUT[i>>2] = 1'b0;
end
end
//---------- GT Wrapper ----------------------------------------------------
assign gt_txpmareset_i[i] = (user_txpmareset[i] || rate_txpmareset[i]);
assign gt_rxpmareset_i[i] = (user_rxpmareset[i] || rate_rxpmareset[i]);
PCIeGen2x8If128_gt_wrapper #
(
.PCIE_SIM_MODE (PCIE_SIM_MODE), // PCIe sim mode
.PCIE_SIM_SPEEDUP (PCIE_SIM_SPEEDUP), // PCIe sim speedup
.PCIE_SIM_TX_EIDLE_DRIVE_LEVEL (PCIE_SIM_TX_EIDLE_DRIVE_LEVEL), // PCIe sim TX electrical idle drive level
.PCIE_GT_DEVICE (PCIE_GT_DEVICE), // PCIe GT device
.PCIE_USE_MODE (PCIE_USE_MODE), // PCIe use mode
.PCIE_PLL_SEL (PCIE_PLL_SEL), // PCIe PLL select for Gen1/Gen2 only
.PCIE_LPM_DFE (PCIE_LPM_DFE), // PCIe LPM or DFE mode for Gen1/Gen2 only
.PCIE_LPM_DFE_GEN3 (PCIE_LPM_DFE_GEN3), // PCIe LPM or DFE mode for Gen3 only
.PCIE_ASYNC_EN (PCIE_ASYNC_EN), // PCIe async enable
.PCIE_TXBUF_EN (PCIE_TXBUF_EN), // PCIe TX buffer enable for Gen1/Gen2 only
.PCIE_TXSYNC_MODE (PCIE_TXSYNC_MODE), // PCIe TX sync mode
.PCIE_RXSYNC_MODE (PCIE_RXSYNC_MODE), // PCIe RX sync mode
.PCIE_CHAN_BOND (PCIE_CHAN_BOND), // PCIe Channel bonding mode
.PCIE_CHAN_BOND_EN (PCIE_CHAN_BOND_EN), // PCIe Channel bonding enable for Gen1/Gen2 only
.PCIE_LANE (PCIE_LANE), // PCIe number of lane
.PCIE_REFCLK_FREQ (PCIE_REFCLK_FREQ), // PCIe reference clock frequency
.PCIE_TX_EIDLE_ASSERT_DELAY (PCIE_TX_EIDLE_ASSERT_DELAY), // PCIe TX electrical idle assert delay
.PCIE_OOBCLK_MODE (PCIE_OOBCLK_MODE), // PCIe OOB clock mode
.TX_MARGIN_FULL_0 (TX_MARGIN_FULL_0),
.TX_MARGIN_FULL_1 (TX_MARGIN_FULL_1),
.TX_MARGIN_FULL_2 (TX_MARGIN_FULL_2),
.TX_MARGIN_FULL_3 (TX_MARGIN_FULL_3),
.TX_MARGIN_FULL_4 (TX_MARGIN_FULL_4),
.TX_MARGIN_LOW_0 (TX_MARGIN_LOW_0),
.TX_MARGIN_LOW_1 (TX_MARGIN_LOW_1),
.TX_MARGIN_LOW_2 (TX_MARGIN_LOW_2),
.TX_MARGIN_LOW_3 (TX_MARGIN_LOW_3),
.TX_MARGIN_LOW_4 (TX_MARGIN_LOW_4),
.PCIE_DEBUG_MODE (PCIE_DEBUG_MODE) // PCIe debug mode
)
gt_wrapper_i
(
//---------- GT User Ports -------------------------
.GT_MASTER (i == 0),
.GT_GEN3 (rate_gen3[i]),
.GT_RX_CONVERGE (&user_rx_converge),
//---------- GT Clock Ports ------------------------
.GT_GTREFCLK0 (PIPE_CLK),
.GT_QPLLCLK (qpll_qplloutclk[i>>2]),
.GT_QPLLREFCLK (qpll_qplloutrefclk[i>>2]),
.GT_TXUSRCLK (clk_pclk),
.GT_RXUSRCLK (clk_rxusrclk),
.GT_TXUSRCLK2 (clk_pclk),
.GT_RXUSRCLK2 (clk_rxusrclk),
.GT_OOBCLK (oobclk[i]),
.GT_TXSYSCLKSEL (rate_sysclksel[(2*i)+1:(2*i)]),
.GT_RXSYSCLKSEL (rate_sysclksel[(2*i)+1:(2*i)]),
.GT_CPLLPDREFCLK (gt_cpllpdrefclk),
.GT_TXOUTCLK (gt_txoutclk[i]),
.GT_RXOUTCLK (gt_rxoutclk[i]),
.GT_CPLLLOCK (gt_cplllock[i]),
.GT_RXCDRLOCK (gt_rxcdrlock[i]),
//---------- GT Reset Ports ------------------------
.GT_CPLLPD (rst_cpllpd || rate_cpllpd[i]),
.GT_CPLLRESET (rst_cpllreset || rate_cpllreset[i]),
.GT_TXUSERRDY (rst_userrdy),
.GT_RXUSERRDY (rst_userrdy),
.GT_RESETOVRD (user_resetovrd[i]),
.GT_GTTXRESET (rst_gtreset),
.GT_GTRXRESET (rst_gtreset),
.GT_TXPMARESET (gt_txpmareset_i[i]), // (user_txpmareset[i] || rate_txpmareset[i]),
.GT_RXPMARESET (gt_rxpmareset_i[i]), // (user_rxpmareset[i] || rate_rxpmareset[i]),
.GT_RXCDRRESET (user_rxcdrreset[i]),
.GT_RXCDRFREQRESET (user_rxcdrfreqreset[i]),
.GT_RXDFELPMRESET (user_rxdfelpmreset[i]),
.GT_EYESCANRESET (user_eyescanreset[i]),
.GT_TXPCSRESET (user_txpcsreset[i]),
.GT_RXPCSRESET (user_rxpcsreset[i]),
.GT_RXBUFRESET (user_rxbufreset[i]),
.GT_EYESCANDATAERROR (gt_eyescandataerror[i]),
.GT_TXRESETDONE (gt_txresetdone[i]),
.GT_RXRESETDONE (gt_rxresetdone[i]),
.GT_RXPMARESETDONE (gt_rxpmaresetdone[i]),
//---------- GT TX Data Ports ----------------------
.GT_TXDATA (PIPE_TXDATA[(32*i)+31:(32*i)]),
.GT_TXDATAK (PIPE_TXDATAK[(4*i)+3:(4*i)]),
.GT_TXP (PIPE_TXP[i]),
.GT_TXN (PIPE_TXN[i]),
//---------- GT RX Data Ports ----------------------
.GT_RXP (PIPE_RXP[i]),
.GT_RXN (PIPE_RXN[i]),
.GT_RXDATA (PIPE_RXDATA[(32*i)+31:(32*i)]),
.GT_RXDATAK (PIPE_RXDATAK[(4*i)+3:(4*i)]),
//---------- GT Command Ports ----------------------
.GT_TXDETECTRX (PIPE_TXDETECTRX),
.GT_TXELECIDLE (PIPE_TXELECIDLE[i]),
.GT_TXCOMPLIANCE (PIPE_TXCOMPLIANCE[i]),
.GT_RXPOLARITY (PIPE_RXPOLARITY[i]),
.GT_TXPOWERDOWN (PIPE_POWERDOWN[(2*i)+1:(2*i)]),
.GT_RXPOWERDOWN (PIPE_POWERDOWN[(2*i)+1:(2*i)]),
.GT_TXRATE (rate_rate[(3*i)+2:(3*i)]),
.GT_RXRATE (rate_rate[(3*i)+2:(3*i)]),
//---------- GT Electrical Command Ports -----------
.GT_TXMARGIN (PIPE_TXMARGIN),
.GT_TXSWING (PIPE_TXSWING),
.GT_TXDEEMPH (PIPE_TXDEEMPH[i]),
.GT_TXINHIBIT (PIPE_TXINHIBIT[i]),
.GT_TXPRECURSOR (eq_txeq_precursor[(5*i)+4:(5*i)]),
.GT_TXMAINCURSOR (eq_txeq_maincursor[(7*i)+6:(7*i)]),
.GT_TXPOSTCURSOR (eq_txeq_postcursor[(5*i)+4:(5*i)]),
//---------- GT Status Ports -----------------------
.GT_RXVALID (gt_rxvalid[i]),
.GT_PHYSTATUS (gt_phystatus[i]),
.GT_RXELECIDLE (gt_rxelecidle[i]),
.GT_RXSTATUS (gt_rxstatus[(3*i)+2:(3*i)]),
.GT_RXBUFSTATUS (gt_rxbufstatus[(3*i)+2:(3*i)]),
.GT_TXRATEDONE (gt_txratedone[i]),
.GT_RXRATEDONE (gt_rxratedone[i]),
.GT_RXDISPERR (gt_rxdisperr[(8*i)+7:(8*i)]),
.GT_RXNOTINTABLE (gt_rxnotintable[(8*i)+7:(8*i)]),
//---------- GT DRP Ports --------------------------
.GT_DRPCLK (clk_dclk),
.GT_DRPADDR (drp_mux_addr[(9*i)+8:(9*i)]),
.GT_DRPEN (drp_mux_en[i]),
.GT_DRPDI (drp_mux_di[(16*i)+15:(16*i)]),
.GT_DRPWE (drp_mux_we[i]),
.GT_DRPDO (gt_do[(16*i)+15:(16*i)]),
.GT_DRPRDY (gt_rdy[i]),
//---------- GT TX Sync Ports ----------------------
.GT_TXPHALIGN (sync_txphalign[i]),
.GT_TXPHALIGNEN (sync_txphalignen[i]),
.GT_TXPHINIT (sync_txphinit[i]),
.GT_TXDLYBYPASS (sync_txdlybypass[i]),
.GT_TXDLYSRESET (sync_txdlysreset[i]),
.GT_TXDLYEN (sync_txdlyen[i]),
.GT_TXDLYSRESETDONE (gt_txdlysresetdone[i]),
.GT_TXPHINITDONE (gt_txphinitdone[i]),
.GT_TXPHALIGNDONE (gt_txphaligndone[i]),
.GT_TXPHDLYRESET (sync_txphdlyreset[i]),
.GT_TXSYNCMODE (i == 0), // GTH, GTP
.GT_TXSYNCIN (gt_txsyncout[0]), // GTH, GTP
.GT_TXSYNCALLIN (txsyncallin), // GTH, GTP
.GT_TXSYNCOUT (gt_txsyncout[i]), // GTH, GTP
.GT_TXSYNCDONE (gt_txsyncdone[i]), // GTH, GTP
//---------- GT RX Sync Ports ----------------------
.GT_RXPHALIGN (sync_rxphalign[i]),
.GT_RXPHALIGNEN (sync_rxphalignen[i]),
.GT_RXDLYBYPASS (sync_rxdlybypass[i]),
.GT_RXDLYSRESET (sync_rxdlysreset[i]),
.GT_RXDLYEN (sync_rxdlyen[i]),
.GT_RXDDIEN (sync_rxddien[i]),
.GT_RXDLYSRESETDONE (gt_rxdlysresetdone[i]),
.GT_RXPHALIGNDONE (gt_rxphaligndone[i]),
.GT_RXSYNCMODE (i == 0), // GTH
.GT_RXSYNCIN (gt_rxsyncout[0]), // GTH
.GT_RXSYNCALLIN (rxsyncallin), // GTH
.GT_RXSYNCOUT (gt_rxsyncout[i]), // GTH
.GT_RXSYNCDONE (gt_rxsyncdone[i]), // GTH
//---------- GT Comma Alignment Ports --------------
.GT_RXSLIDE (PIPE_RXSLIDE[i]),
.GT_RXCOMMADET (gt_rxcommadet[i]),
.GT_RXCHARISCOMMA (gt_rxchariscomma[(4*i)+3:(4*i)]),
.GT_RXBYTEISALIGNED (gt_rxbyteisaligned[i]),
.GT_RXBYTEREALIGN (gt_rxbyterealign[i]),
//---------- GT Channel Bonding Ports --------------
.GT_RXCHANISALIGNED (PIPE_RXCHANISALIGNED[i]),
.GT_RXCHBONDEN (rxchbonden[i]),
.GT_RXCHBONDI (gt_rxchbondi[i]),
.GT_RXCHBONDLEVEL (gt_rxchbondlevel[(3*i)+2:(3*i)]),
.GT_RXCHBONDMASTER (rxchbondmaster[i]),
.GT_RXCHBONDSLAVE (rxchbondslave[i]),
.GT_RXCHBONDO (gt_rxchbondo[i+1]),
//---------- GT PRBS/Loopback Ports ----------------
.GT_TXPRBSSEL (PIPE_TXPRBSSEL),
.GT_RXPRBSSEL (PIPE_RXPRBSSEL),
.GT_TXPRBSFORCEERR (PIPE_TXPRBSFORCEERR),
.GT_RXPRBSCNTRESET (PIPE_RXPRBSCNTRESET),
.GT_LOOPBACK (PIPE_LOOPBACK),
.GT_RXPRBSERR (PIPE_RXPRBSERR[i]),
//---------- GT Debug Port -------------------------
.GT_DMONITOROUT (PIPE_DMONITOROUT[(15*i)+14:(15*i)])
);
//---------- GT Wrapper Assignments ----------------------------------------
assign oobclk[i] = (PCIE_OOBCLK_MODE == 1) ? user_oobclk[i] : clk_oobclk;
//---------- Channel Bonding Master Slave Enable ---------------------------
if (PCIE_CHAN_BOND_EN == "FALSE")
begin : channel_bonding_ms_disable
assign rxchbonden[i] = 1'd0;
assign rxchbondmaster[i] = 1'd0;
assign rxchbondslave[i] = 1'd0;
end
else
begin : channel_bonding_ms_enable
assign rxchbonden[i] = (PCIE_LANE > 1) && (PCIE_CHAN_BOND_EN == "TRUE") ? !rate_gen3[i] : 1'd0;
assign rxchbondmaster[i] = rate_gen3[i] ? 1'd0 : (i == 0);
assign rxchbondslave[i] = rate_gen3[i] ? 1'd0 : (i > 0);
end
//---------- Channel Bonding Input Connection ------------------------------
if (PCIE_CHAN_BOND_EN == "FALSE")
begin : channel_bonding_in_disable
assign gt_rxchbondi[i] = 5'd0;
assign gt_rxchbondlevel[(3*i)+2:(3*i)] = 3'd0;
end
else
begin : channel_bonding_in_enable
//---------- Channel Bonding (2: Binary-Tree) --------------------------
if (PCIE_CHAN_BOND == 2)
begin : channel_bonding_a
case (i)
//---------- Lane 0 --------------------------------
0 :
begin
assign gt_rxchbondi[0] = gt_rxchbondo[0];
assign gt_rxchbondlevel[2:0] = (PCIE_LANE == 4'd8) ? 3'd4 :
(PCIE_LANE > 4'd5) ? 3'd3 :
(PCIE_LANE > 4'd3) ? 3'd2 :
(PCIE_LANE > 4'd1) ? 3'd1 : 3'd0;
end
//---------- Lane 1 --------------------------------
1 :
begin
assign gt_rxchbondi[1] = gt_rxchbondo[1];
assign gt_rxchbondlevel[5:3] = (PCIE_LANE == 4'd8) ? 3'd3 :
(PCIE_LANE > 4'd5) ? 3'd2 :
(PCIE_LANE > 4'd3) ? 3'd1 : 3'd0;
end
//---------- Lane 2 --------------------------------
2 :
begin
assign gt_rxchbondi[2] = gt_rxchbondo[1];
assign gt_rxchbondlevel[8:6] = (PCIE_LANE == 4'd8) ? 3'd3 :
(PCIE_LANE > 4'd5) ? 3'd2 :
(PCIE_LANE > 4'd3) ? 3'd1 : 3'd0;
end
//---------- Lane 3 --------------------------------
3 :
begin
assign gt_rxchbondi[3] = gt_rxchbondo[3];
assign gt_rxchbondlevel[11:9] = (PCIE_LANE == 4'd8) ? 3'd2 :
(PCIE_LANE > 4'd5) ? 3'd1 : 3'd0;
end
//---------- Lane 4 --------------------------------
4 :
begin
assign gt_rxchbondi[4] = gt_rxchbondo[3];
assign gt_rxchbondlevel[14:12] = (PCIE_LANE == 4'd8) ? 3'd2 :
(PCIE_LANE > 4'd5) ? 3'd1 : 3'd0;
end
//---------- Lane 5 --------------------------------
5 :
begin
assign gt_rxchbondi[5] = gt_rxchbondo[5];
assign gt_rxchbondlevel[17:15] = (PCIE_LANE == 4'd8) ? 3'd1 : 3'd0;
end
//---------- Lane 6 --------------------------------
6 :
begin
assign gt_rxchbondi[6] = gt_rxchbondo[5];
assign gt_rxchbondlevel[20:18] = (PCIE_LANE == 4'd8) ? 3'd1 : 3'd0;
end
//---------- Lane 7 --------------------------------
7 :
begin
assign gt_rxchbondi[7] = gt_rxchbondo[7];
assign gt_rxchbondlevel[23:21] = 3'd0;
end
//---------- Default -------------------------------
default :
begin
assign gt_rxchbondi[i] = gt_rxchbondo[7];
assign gt_rxchbondlevel[(3*i)+2:(3*i)] = 3'd0;
end
endcase
end
//---------- Channel Bonding (0: One-Hop, 1: Daisy Chain) --------------
else
begin : channel_bonding_b
assign gt_rxchbondi[i] = (PCIE_CHAN_BOND == 1) ? gt_rxchbondo[i] : ((i == 0) ? gt_rxchbondo[0] : gt_rxchbondo[1]);
assign gt_rxchbondlevel[(3*i)+2:(3*i)] = (PCIE_CHAN_BOND == 1) ? (PCIE_LANE-1)-i : ((PCIE_LANE > 1) && (i == 0));
end
end
end
endgenerate
//---------- PIPE Wrapper Output -----------------------------------------------
assign PIPE_TXEQ_FS = 0;//TXEQ_FS;
assign PIPE_TXEQ_LF = 0;//TXEQ_LF;
assign PIPE_RXELECIDLE = gt_rxelecidle;
assign PIPE_RXSTATUS = gt_rxstatus;
assign PIPE_RXDISPERR = gt_rxdisperr;
assign PIPE_RXNOTINTABLE = gt_rxnotintable;
assign PIPE_RXPMARESETDONE = gt_rxpmaresetdone;
assign PIPE_RXBUFSTATUS = gt_rxbufstatus;
assign PIPE_TXPHALIGNDONE = gt_txphaligndone;
assign PIPE_TXPHINITDONE = gt_txphinitdone;
assign PIPE_TXDLYSRESETDONE = gt_txdlysresetdone;
assign PIPE_RXPHALIGNDONE = gt_rxphaligndone;
assign PIPE_RXDLYSRESETDONE = gt_rxdlysresetdone;
assign PIPE_RXSYNCDONE = gt_rxsyncdone;
assign PIPE_RXCOMMADET = gt_rxcommadet;
assign PIPE_QPLL_LOCK = qpll_qplllock;
assign PIPE_CPLL_LOCK = gt_cplllock;
assign PIPE_PCLK = clk_pclk;
assign PIPE_PCLK_LOCK = clk_mmcm_lock;
assign PIPE_RXCDRLOCK = 0;//user_rxcdrlock;
assign PIPE_RXUSRCLK = 0;//clk_rxusrclk;
assign PIPE_RXOUTCLK = 0;//clk_rxoutclk;
assign PIPE_TXSYNC_DONE = 0;//sync_txsync_done;
assign PIPE_RXSYNC_DONE = 0;//sync_rxsync_done;
assign PIPE_ACTIVE_LANE = 0;//user_active_lane;
assign PIPE_TXOUTCLK_OUT = gt_txoutclk[0];
assign PIPE_RXOUTCLK_OUT = gt_rxoutclk;
assign PIPE_PCLK_SEL_OUT = rate_pclk_sel;
assign PIPE_GEN3_OUT = rate_gen3[0];
assign PIPE_RXEQ_CONVERGE = user_rx_converge;
assign PIPE_RXEQ_ADAPT_DONE = (PCIE_GT_DEVICE == "GTP") ? {PCIE_LANE{1'd0}} : eq_rxeq_adapt_done;
assign PIPE_EYESCANDATAERROR = gt_eyescandataerror;
assign PIPE_RST_FSM = rst_fsm;
assign PIPE_QRST_FSM = qrst_fsm;
assign PIPE_RATE_FSM = rate_fsm;
assign PIPE_SYNC_FSM_TX = sync_fsm_tx;
assign PIPE_SYNC_FSM_RX = sync_fsm_rx;
assign PIPE_DRP_FSM = drp_fsm;
assign PIPE_QDRP_FSM = 0;//qdrp_fsm;
assign PIPE_RST_IDLE = &rst_idle;
assign PIPE_QRST_IDLE = &qrst_idle;
assign PIPE_RATE_IDLE = &rate_idle;
assign EXT_CH_GT_DRPDO = gt_do[(PCIE_LANE*16)-1:0];
assign EXT_CH_GT_DRPRDY = gt_rdy[(PCIE_LANE-1):0];
assign EXT_CH_GT_DRPCLK = clk_dclk;
assign PIPE_DEBUG_0 = (PCIE_DEBUG_MODE == 1) ? gt_txresetdone : {PCIE_LANE{1'b0}};
assign PIPE_DEBUG_1 = (PCIE_DEBUG_MODE == 1) ? gt_rxresetdone : {PCIE_LANE{1'b0}};
assign PIPE_DEBUG_2 = (PCIE_DEBUG_MODE == 1) ? gt_phystatus : {PCIE_LANE{1'b0}};
assign PIPE_DEBUG_3 = (PCIE_DEBUG_MODE == 1) ? gt_rxvalid : {PCIE_LANE{1'b0}};
assign PIPE_DEBUG_4 = (PCIE_DEBUG_MODE == 1) ? clk_dclk : {PCIE_LANE{1'b0}};
assign PIPE_DEBUG_5 = (PCIE_DEBUG_MODE == 1) ? drp_mux_en : {PCIE_LANE{1'b0}};
assign PIPE_DEBUG_6 = (PCIE_DEBUG_MODE == 1) ? drp_mux_we : {PCIE_LANE{1'b0}};
assign PIPE_DEBUG_7 = (PCIE_DEBUG_MODE == 1) ? gt_rdy : {PCIE_LANE{1'b0}};
assign PIPE_DEBUG_8 = (PCIE_DEBUG_MODE == 1) ? user_rx_converge : {PCIE_LANE{1'b0}};
assign PIPE_DEBUG_9 = (PCIE_DEBUG_MODE == 1) ? PIPE_TXELECIDLE : {PCIE_LANE{1'b0}};
assign PIPE_DEBUG[ 1:0] = (PCIE_DEBUG_MODE == 1) ? PIPE_TXEQ_CONTROL[1:0] : 2'd0;
assign PIPE_DEBUG[ 5:2] = (PCIE_DEBUG_MODE == 1) ? PIPE_TXEQ_PRESET[3:0] : 4'd0;
assign PIPE_DEBUG[31:6] = 26'd0;
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
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// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
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// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
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// (including loss of data, profits, goodwill, or any type of
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// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
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// applications related to the deployment of airbags, or any
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// (individually and collectively, "Critical
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// Applications, subject only to applicable laws and
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//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : arb_row_col.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// This block receives request to send row and column commands. These requests
// come the individual bank machines. The arbitration winner is selected
// and driven back to the bank machines.
//
// The CS enables are generated. For 2:1 mode, row commands are sent
// in the "0" phase, and column commands are sent in the "1" phase.
//
// In 2T mode, a further arbitration is performed between the row
// and column commands. The winner of this arbitration inhibits
// arbitration by the loser. The winner is allowed to arbitrate, the loser is
// blocked until the next state. The winning address command
// is repeated on both the "0" and the "1" phases and the CS
// is asserted for just the "1" phase.
`timescale 1 ps / 1 ps
module mig_7series_v1_8_arb_row_col #
(
parameter TCQ = 100,
parameter ADDR_CMD_MODE = "1T",
parameter CWL = 5,
parameter EARLY_WR_DATA_ADDR = "OFF",
parameter nBANK_MACHS = 4,
parameter nCK_PER_CLK = 2,
parameter nRAS = 37500, // ACT->PRE cmd period (CKs)
parameter nRCD = 12500, // ACT->R/W delay (CKs)
parameter nWR = 6 // Write recovery (CKs)
)
(/*AUTOARG*/
// Outputs
grant_row_r, grant_pre_r, sent_row, sending_row, sending_pre, grant_config_r,
rnk_config_strobe, rnk_config_valid_r, grant_col_r,
sending_col, sent_col, sent_col_r, grant_col_wr, send_cmd0_row, send_cmd0_col,
send_cmd1_row, send_cmd1_col, send_cmd2_row, send_cmd2_col, send_cmd2_pre,
send_cmd3_col, col_channel_offset, cs_en0, cs_en1, cs_en2, cs_en3,
insert_maint_r1, rnk_config_kill_rts_col,
// Inputs
clk, rst, rts_row, rts_pre, insert_maint_r, rts_col, rtc, col_rdy_wr
);
// Create a delay when switching ranks
localparam RNK2RNK_DLY = 12;
localparam RNK2RNK_DLY_CLKS =
(RNK2RNK_DLY / nCK_PER_CLK) + (RNK2RNK_DLY % nCK_PER_CLK ? 1 : 0);
input clk;
input rst;
input [nBANK_MACHS-1:0] rts_row;
input insert_maint_r;
input [nBANK_MACHS-1:0] rts_col;
reg [RNK2RNK_DLY_CLKS-1:0] rnk_config_strobe_r;
wire block_grant_row;
wire block_grant_col;
wire rnk_config_kill_rts_col_lcl =
RNK2RNK_DLY_CLKS > 0 ? |rnk_config_strobe_r : 1'b0;
output rnk_config_kill_rts_col;
assign rnk_config_kill_rts_col = rnk_config_kill_rts_col_lcl;
wire [nBANK_MACHS-1:0] col_request;
wire granted_col_ns = |col_request;
wire [nBANK_MACHS-1:0] row_request =
rts_row & {nBANK_MACHS{~insert_maint_r}};
wire granted_row_ns = |row_request;
generate
if (ADDR_CMD_MODE == "2T" && nCK_PER_CLK != 4) begin : row_col_2T_arb
assign col_request =
rts_col & {nBANK_MACHS{~(rnk_config_kill_rts_col_lcl || insert_maint_r)}};
// Give column command priority whenever previous state has no row request.
wire [1:0] row_col_grant;
wire [1:0] current_master = ~granted_row_ns ? 2'b10 : row_col_grant;
wire upd_last_master = ~granted_row_ns || |row_col_grant;
mig_7series_v1_8_round_robin_arb #
(.WIDTH (2))
row_col_arb0
(.grant_ns (),
.grant_r (row_col_grant),
.upd_last_master (upd_last_master),
.current_master (current_master),
.clk (clk),
.rst (rst),
.req ({granted_row_ns, granted_col_ns}),
.disable_grant (1'b0));
assign {block_grant_col, block_grant_row} = row_col_grant;
end
else begin : row_col_1T_arb
assign col_request = rts_col & {nBANK_MACHS{~rnk_config_kill_rts_col_lcl}};
assign block_grant_row = 1'b0;
assign block_grant_col = 1'b0;
end
endgenerate
// Row address/command arbitration.
wire[nBANK_MACHS-1:0] grant_row_r_lcl;
output wire[nBANK_MACHS-1:0] grant_row_r;
assign grant_row_r = grant_row_r_lcl;
reg granted_row_r;
always @(posedge clk) granted_row_r <= #TCQ granted_row_ns;
wire sent_row_lcl = granted_row_r && ~block_grant_row;
output wire sent_row;
assign sent_row = sent_row_lcl;
mig_7series_v1_8_round_robin_arb #
(.WIDTH (nBANK_MACHS))
row_arb0
(.grant_ns (),
.grant_r (grant_row_r_lcl[nBANK_MACHS-1:0]),
.upd_last_master (sent_row_lcl),
.current_master (grant_row_r_lcl[nBANK_MACHS-1:0]),
.clk (clk),
.rst (rst),
.req (row_request),
.disable_grant (1'b0));
output wire [nBANK_MACHS-1:0] sending_row;
assign sending_row = grant_row_r_lcl & {nBANK_MACHS{~block_grant_row}};
// Precharge arbitration for 4:1 mode
input [nBANK_MACHS-1:0] rts_pre;
output wire[nBANK_MACHS-1:0] grant_pre_r;
output wire [nBANK_MACHS-1:0] sending_pre;
wire sent_pre_lcl;
generate
if((nCK_PER_CLK == 4) && (ADDR_CMD_MODE != "2T")) begin : pre_4_1_1T_arb
reg granted_pre_r;
wire[nBANK_MACHS-1:0] grant_pre_r_lcl;
wire granted_pre_ns = |rts_pre;
assign grant_pre_r = grant_pre_r_lcl;
always @(posedge clk) granted_pre_r <= #TCQ granted_pre_ns;
assign sent_pre_lcl = granted_pre_r;
assign sending_pre = grant_pre_r_lcl;
mig_7series_v1_8_round_robin_arb #
(.WIDTH (nBANK_MACHS))
pre_arb0
(.grant_ns (),
.grant_r (grant_pre_r_lcl[nBANK_MACHS-1:0]),
.upd_last_master (sent_pre_lcl),
.current_master (grant_pre_r_lcl[nBANK_MACHS-1:0]),
.clk (clk),
.rst (rst),
.req (rts_pre),
.disable_grant (1'b0));
end
endgenerate
`ifdef MC_SVA
all_bank_machines_row_arb:
cover property (@(posedge clk) (~rst && &rts_row));
`endif
// Rank config arbitration.
input [nBANK_MACHS-1:0] rtc;
wire [nBANK_MACHS-1:0] grant_config_r_lcl;
output wire [nBANK_MACHS-1:0] grant_config_r;
assign grant_config_r = grant_config_r_lcl;
wire upd_rnk_config_last_master;
mig_7series_v1_8_round_robin_arb #
(.WIDTH (nBANK_MACHS))
config_arb0
(.grant_ns (),
.grant_r (grant_config_r_lcl[nBANK_MACHS-1:0]),
.upd_last_master (upd_rnk_config_last_master),
.current_master (grant_config_r_lcl[nBANK_MACHS-1:0]),
.clk (clk),
.rst (rst),
.req (rtc[nBANK_MACHS-1:0]),
.disable_grant (1'b0));
`ifdef MC_SVA
all_bank_machines_config_arb: cover property (@(posedge clk) (~rst && &rtc));
`endif
wire rnk_config_strobe_ns = ~rnk_config_strobe_r[0] && |rtc && ~granted_col_ns;
always @(posedge clk) rnk_config_strobe_r[0] <= #TCQ rnk_config_strobe_ns;
genvar i;
generate
for(i = 1; i < RNK2RNK_DLY_CLKS; i = i + 1)
always @(posedge clk)
rnk_config_strobe_r[i] <= #TCQ rnk_config_strobe_r[i-1];
endgenerate
output wire rnk_config_strobe;
assign rnk_config_strobe = rnk_config_strobe_r[0];
assign upd_rnk_config_last_master = rnk_config_strobe_r[0];
// Generate rnk_config_valid.
reg rnk_config_valid_r_lcl;
wire rnk_config_valid_ns;
assign rnk_config_valid_ns =
~rst && (rnk_config_valid_r_lcl || rnk_config_strobe_ns);
always @(posedge clk) rnk_config_valid_r_lcl <= #TCQ rnk_config_valid_ns;
output wire rnk_config_valid_r;
assign rnk_config_valid_r = rnk_config_valid_r_lcl;
// Column address/command arbitration.
wire [nBANK_MACHS-1:0] grant_col_r_lcl;
output wire [nBANK_MACHS-1:0] grant_col_r;
assign grant_col_r = grant_col_r_lcl;
reg granted_col_r;
always @(posedge clk) granted_col_r <= #TCQ granted_col_ns;
wire sent_col_lcl;
mig_7series_v1_8_round_robin_arb #
(.WIDTH (nBANK_MACHS))
col_arb0
(.grant_ns (),
.grant_r (grant_col_r_lcl[nBANK_MACHS-1:0]),
.upd_last_master (sent_col_lcl),
.current_master (grant_col_r_lcl[nBANK_MACHS-1:0]),
.clk (clk),
.rst (rst),
.req (col_request),
.disable_grant (1'b0));
`ifdef MC_SVA
all_bank_machines_col_arb:
cover property (@(posedge clk) (~rst && &rts_col));
`endif
output wire [nBANK_MACHS-1:0] sending_col;
assign sending_col = grant_col_r_lcl & {nBANK_MACHS{~block_grant_col}};
assign sent_col_lcl = granted_col_r && ~block_grant_col;
reg sent_col_lcl_r = 1'b0;
always @(posedge clk) sent_col_lcl_r <= #TCQ sent_col_lcl;
output wire sent_col;
assign sent_col = sent_col_lcl;
output wire sent_col_r;
assign sent_col_r = sent_col_lcl_r;
// If we need early wr_data_addr because ECC is on, arbitrate
// to see which bank machine might sent the next wr_data_addr;
input [nBANK_MACHS-1:0] col_rdy_wr;
output wire [nBANK_MACHS-1:0] grant_col_wr;
generate
if (EARLY_WR_DATA_ADDR == "OFF") begin : early_wr_addr_arb_off
assign grant_col_wr = {nBANK_MACHS{1'b0}};
end
else begin : early_wr_addr_arb_on
wire [nBANK_MACHS-1:0] grant_col_wr_raw;
mig_7series_v1_8_round_robin_arb #
(.WIDTH (nBANK_MACHS))
col_arb0
(.grant_ns (grant_col_wr_raw),
.grant_r (),
.upd_last_master (sent_col_lcl),
.current_master (grant_col_r_lcl[nBANK_MACHS-1:0]),
.clk (clk),
.rst (rst),
.req (col_rdy_wr),
.disable_grant (1'b0));
reg [nBANK_MACHS-1:0] grant_col_wr_r;
wire [nBANK_MACHS-1:0] grant_col_wr_ns = granted_col_ns
? grant_col_wr_raw
: grant_col_wr_r;
always @(posedge clk) grant_col_wr_r <= #TCQ grant_col_wr_ns;
assign grant_col_wr = grant_col_wr_ns;
end // block: early_wr_addr_arb_on
endgenerate
output reg send_cmd0_row = 1'b0;
output reg send_cmd0_col = 1'b0;
output reg send_cmd1_row = 1'b0;
output reg send_cmd1_col = 1'b0;
output reg send_cmd2_row = 1'b0;
output reg send_cmd2_col = 1'b0;
output reg send_cmd2_pre = 1'b0;
output reg send_cmd3_col = 1'b0;
output reg cs_en0 = 1'b0;
output reg cs_en1 = 1'b0;
output reg cs_en2 = 1'b0;
output reg cs_en3 = 1'b0;
output wire [5:0] col_channel_offset;
reg insert_maint_r1_lcl;
always @(posedge clk) insert_maint_r1_lcl <= #TCQ insert_maint_r;
output wire insert_maint_r1;
assign insert_maint_r1 = insert_maint_r1_lcl;
wire sent_row_or_maint = sent_row_lcl || insert_maint_r1_lcl;
reg sent_row_or_maint_r = 1'b0;
always @(posedge clk) sent_row_or_maint_r <= #TCQ sent_row_or_maint;
generate
case ({(nCK_PER_CLK == 4), (nCK_PER_CLK == 2), (ADDR_CMD_MODE == "2T")})
3'b000 : begin : one_one_not2T
end
3'b001 : begin : one_one_2T
end
3'b010 : begin : two_one_not2T
if(!(CWL % 2)) begin // Place column commands on slot 0 for even CWL
always @(sent_col_lcl) begin
cs_en0 = sent_col_lcl;
send_cmd0_col = sent_col_lcl;
end
always @(sent_row_or_maint) begin
cs_en1 = sent_row_or_maint;
send_cmd1_row = sent_row_or_maint;
end
assign col_channel_offset = 0;
end
else begin // Place column commands on slot 1 for odd CWL
always @(sent_row_or_maint) begin
cs_en0 = sent_row_or_maint;
send_cmd0_row = sent_row_or_maint;
end
always @(sent_col_lcl) begin
cs_en1 = sent_col_lcl;
send_cmd1_col = sent_col_lcl;
end
assign col_channel_offset = 1;
end
end
3'b011 : begin : two_one_2T
if(!(CWL % 2)) begin // Place column commands on slot 1->0 for even CWL
always @(sent_row_or_maint_r or sent_col_lcl_r)
cs_en0 = sent_row_or_maint_r || sent_col_lcl_r;
always @(sent_row_or_maint or sent_row_or_maint_r) begin
send_cmd0_row = sent_row_or_maint_r;
send_cmd1_row = sent_row_or_maint;
end
always @(sent_col_lcl or sent_col_lcl_r) begin
send_cmd0_col = sent_col_lcl_r;
send_cmd1_col = sent_col_lcl;
end
assign col_channel_offset = 0;
end
else begin // Place column commands on slot 0->1 for odd CWL
always @(sent_col_lcl or sent_row_or_maint)
cs_en1 = sent_row_or_maint || sent_col_lcl;
always @(sent_row_or_maint) begin
send_cmd0_row = sent_row_or_maint;
send_cmd1_row = sent_row_or_maint;
end
always @(sent_col_lcl) begin
send_cmd0_col = sent_col_lcl;
send_cmd1_col = sent_col_lcl;
end
assign col_channel_offset = 1;
end
end
3'b100 : begin : four_one_not2T
if(!(CWL % 2)) begin // Place column commands on slot 0 for even CWL
always @(sent_col_lcl) begin
cs_en0 = sent_col_lcl;
send_cmd0_col = sent_col_lcl;
end
always @(sent_row_or_maint) begin
cs_en1 = sent_row_or_maint;
send_cmd1_row = sent_row_or_maint;
end
assign col_channel_offset = 0;
end
else begin // Place column commands on slot 1 for odd CWL
always @(sent_row_or_maint) begin
cs_en0 = sent_row_or_maint;
send_cmd0_row = sent_row_or_maint;
end
always @(sent_col_lcl) begin
cs_en1 = sent_col_lcl;
send_cmd1_col = sent_col_lcl;
end
assign col_channel_offset = 1;
end
always @(sent_pre_lcl) begin
cs_en2 = sent_pre_lcl;
send_cmd2_pre = sent_pre_lcl;
end
end
3'b101 : begin : four_one_2T
if(!(CWL % 2)) begin // Place column commands on slot 3->0 for even CWL
always @(sent_col_lcl or sent_col_lcl_r) begin
cs_en0 = sent_col_lcl_r;
send_cmd0_col = sent_col_lcl_r;
send_cmd3_col = sent_col_lcl;
end
always @(sent_row_or_maint) begin
cs_en2 = sent_row_or_maint;
send_cmd1_row = sent_row_or_maint;
send_cmd2_row = sent_row_or_maint;
end
assign col_channel_offset = 0;
end
else begin // Place column commands on slot 2->3 for odd CWL
always @(sent_row_or_maint) begin
cs_en1 = sent_row_or_maint;
send_cmd0_row = sent_row_or_maint;
send_cmd1_row = sent_row_or_maint;
end
always @(sent_col_lcl) begin
cs_en3 = sent_col_lcl;
send_cmd2_col = sent_col_lcl;
send_cmd3_col = sent_col_lcl;
end
assign col_channel_offset = 3;
end
end
endcase
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__INV_PP_SYMBOL_V
`define SKY130_FD_SC_MS__INV_PP_SYMBOL_V
/**
* inv: Inverter.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__inv (
//# {{data|Data Signals}}
input A ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__INV_PP_SYMBOL_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module dma_core (
// dma interface
dma_clk,
dma_rst,
dma_valid,
dma_last,
dma_data,
dma_ready,
dma_ovf,
dma_unf,
dma_status,
dma_bw,
// data interface
adc_clk,
adc_rst,
adc_valid,
adc_data,
// processor interface
dma_start,
dma_stream,
dma_count);
// parameters
parameter DATA_WIDTH = 64;
localparam DW = DATA_WIDTH - 1;
localparam BUF_THRESHOLD_LO = 6'd3;
localparam BUF_THRESHOLD_HI = 6'd60;
localparam DATA_WIDTH_IN_BYTES = DATA_WIDTH/8;
// dma interface
input dma_clk;
input dma_rst;
output dma_valid;
output dma_last;
output [DW:0] dma_data;
input dma_ready;
output dma_ovf;
output dma_unf;
output dma_status;
output [31:0] dma_bw;
// data interface
input adc_clk;
input adc_rst;
input adc_valid;
input [DW:0] adc_data;
// processor interface
input dma_start;
input dma_stream;
input [31:0] dma_count;
// internal registers
reg dma_valid_int = 'd0;
reg dma_last_int = 'd0;
reg [DW:0] dma_data_int = 'd0;
reg dma_capture_enable = 'd0;
reg [31:0] dma_capture_count = 'd0;
reg dma_rd = 'd0;
reg [ 5:0] dma_raddr = 'd0;
reg dma_release_toggle_m1 = 'd0;
reg dma_release_toggle_m2 = 'd0;
reg dma_release_toggle_m3 = 'd0;
reg [ 5:0] dma_release_waddr = 'd0;
reg [ 5:0] dma_waddr_m1 = 'd0;
reg [ 5:0] dma_waddr_m2 = 'd0;
reg [ 5:0] dma_waddr = 'd0;
reg [ 5:0] dma_addr_diff = 'd0;
reg dma_almost_full = 'd0;
reg dma_almost_empty = 'd0;
reg dma_ovf = 'd0;
reg dma_unf = 'd0;
reg dma_resync = 'd0;
reg adc_wr = 'd0;
reg [ 5:0] adc_waddr = 'd0;
reg [ 5:0] adc_waddr_g = 'd0;
reg [ 3:0] adc_release_count = 'd0;
reg [DW:0] adc_wdata = 'd0;
reg adc_release_toggle = 'd0;
reg [ 5:0] adc_release_waddr = 'd0;
reg adc_resync_m1 = 'd0;
reg adc_resync_m2 = 'd0;
reg adc_resync = 'd0;
// internal signals
wire dma_rd_valid_s;
wire dma_last_s;
wire dma_ready_s;
wire dma_rd_s;
wire dma_release_s;
wire [ 6:0] dma_addr_diff_s;
wire dma_ovf_s;
wire dma_unf_s;
wire [DW:0] dma_rdata_s;
// binary to grey conversion
function [5:0] b2g;
input [5:0] b;
reg [5:0] g;
begin
g[5] = b[5];
g[4] = b[5] ^ b[4];
g[3] = b[4] ^ b[3];
g[2] = b[3] ^ b[2];
g[1] = b[2] ^ b[1];
g[0] = b[1] ^ b[0];
b2g = g;
end
endfunction
// grey to binary conversion
function [5:0] g2b;
input [5:0] g;
reg [5:0] b;
begin
b[5] = g[5];
b[4] = b[5] ^ g[4];
b[3] = b[4] ^ g[3];
b[2] = b[3] ^ g[2];
b[1] = b[2] ^ g[1];
b[0] = b[1] ^ g[0];
g2b = b;
end
endfunction
// dma read- user interface
assign dma_bw = DATA_WIDTH_IN_BYTES;
assign dma_status = dma_capture_enable;
always @(posedge dma_clk) begin
dma_valid_int <= dma_rd_valid_s;
dma_last_int <= dma_last_s;
dma_data_int <= dma_rdata_s;
end
// dma read- capture control signals
assign dma_rd_valid_s = dma_capture_enable & dma_rd;
assign dma_last_s = (dma_capture_count == dma_count) ? dma_rd_valid_s : 1'b0;
always @(posedge dma_clk) begin
if ((dma_stream == 1'b0) && (dma_last_s == 1'b1)) begin
dma_capture_enable <= 1'b0;
end else if (dma_start == 1'b1) begin
dma_capture_enable <= 1'b1;
end
if ((dma_capture_enable == 1'b0) || (dma_last_s == 1'b1)) begin
dma_capture_count <= dma_bw;
end else if (dma_rd == 1'b1) begin
dma_capture_count <= dma_capture_count + dma_bw;
end
end
// dma read- read data always and pass it to the external memory
assign dma_ready_s = (~dma_capture_enable) | dma_ready;
assign dma_rd_s = (dma_release_waddr == dma_raddr) ? 1'b0 : dma_ready_s;
always @(posedge dma_clk) begin
dma_rd <= dma_rd_s;
if ((dma_resync == 1'b1) || (dma_rst == 1'b1)) begin
dma_raddr <= 6'd0;
end else if (dma_rd_s == 1'b1) begin
dma_raddr <= dma_raddr + 1'b1;
end
end
// dma read- get bursts of adc data from the other side
assign dma_release_s = dma_release_toggle_m3 ^ dma_release_toggle_m2;
always @(posedge dma_clk) begin
if (dma_rst == 1'b1) begin
dma_release_toggle_m1 <= 'd0;
dma_release_toggle_m2 <= 'd0;
dma_release_toggle_m3 <= 'd0;
end else begin
dma_release_toggle_m1 <= adc_release_toggle;
dma_release_toggle_m2 <= dma_release_toggle_m1;
dma_release_toggle_m3 <= dma_release_toggle_m2;
end
if (dma_resync == 1'b1) begin
dma_release_waddr <= 6'd0;
end else if (dma_release_s == 1'b1) begin
dma_release_waddr <= adc_release_waddr;
end
end
// dma read- get free running write address for ovf/unf checking
assign dma_addr_diff_s = {1'b1, dma_waddr} - dma_raddr;
assign dma_ovf_s = (dma_addr_diff < BUF_THRESHOLD_LO) ? dma_almost_full : 1'b0;
assign dma_unf_s = (dma_addr_diff > BUF_THRESHOLD_HI) ? dma_almost_empty : 1'b0;
always @(posedge dma_clk) begin
if (dma_rst == 1'b1) begin
dma_waddr_m1 <= 'd0;
dma_waddr_m2 <= 'd0;
end else begin
dma_waddr_m1 <= adc_waddr_g;
dma_waddr_m2 <= dma_waddr_m1;
end
dma_waddr <= g2b(dma_waddr_m2);
dma_addr_diff <= dma_addr_diff_s[5:0];
if (dma_addr_diff > BUF_THRESHOLD_HI) begin
dma_almost_full <= 1'b1;
end else begin
dma_almost_full <= 1'b0;
end
if (dma_addr_diff < BUF_THRESHOLD_LO) begin
dma_almost_empty <= 1'b1;
end else begin
dma_almost_empty <= 1'b0;
end
dma_ovf <= dma_ovf_s;
dma_unf <= dma_unf_s;
dma_resync <= dma_ovf | dma_unf;
end
// adc write- used here to simply transfer data to the dma side
// address is released with a free running counter
always @(posedge adc_clk) begin
adc_wr <= adc_valid;
if ((adc_resync == 1'b1) || (adc_rst == 1'b1)) begin
adc_waddr <= 6'd0;
end else if (adc_wr == 1'b1) begin
adc_waddr <= adc_waddr + 1'b1;
end
adc_waddr_g <= b2g(adc_waddr);
adc_wdata <= adc_data;
adc_release_count <= adc_release_count + 1'b1;
if (adc_release_count == 4'hf) begin
adc_release_toggle <= ~adc_release_toggle;
adc_release_waddr <= adc_waddr;
end
if (adc_rst == 1'b1) begin
adc_resync_m1 <= 'd0;
adc_resync_m2 <= 'd0;
end else begin
adc_resync_m1 <= dma_resync;
adc_resync_m2 <= adc_resync_m1;
end
adc_resync <= adc_resync_m2;
end
// interface handler for ready
axis_inf #(.DATA_WIDTH(DATA_WIDTH)) i_axis_inf (
.clk (dma_clk),
.rst (dma_rst),
.valid (dma_valid_int),
.last (dma_last_int),
.data (dma_data_int),
.inf_valid (dma_valid),
.inf_last (dma_last),
.inf_data (dma_data),
.inf_ready (dma_ready));
// buffer (mainly for clock domain transfer)
mem #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(6)) i_mem (
.clka (adc_clk),
.wea (adc_wr),
.addra (adc_waddr),
.dina (adc_wdata),
.clkb (dma_clk),
.addrb (dma_raddr),
.doutb (dma_rdata_s));
endmodule
// ***************************************************************************
// ***************************************************************************
|
/////////////////////////////////////////////////////////////////////////
//
// pLIB
// D-FLIP-FLOPS
/////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////
// p_I_FD FD error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FD (Q,D,C,E);
parameter INIT=1'b0;
output Q;
input D;
input C;
input E;
wire Dtemp;
// Xilinx FD instance
defparam FD_z.INIT=INIT;
FD FD_z (.Q(Q),.D(Dtemp),.C(C));
// Error injection
xor (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FD FD error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FD (Q,D,C,E);
parameter INIT = 1'b0;
output Q;
input D;
input C;
input E;
wire Qtemp;
// Xilinx FD instance
FD #(.INIT(INIT)) FD_z (.Q(Qtemp),.D(D),.C(C));
// Error injection
xor (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FD_1 FD_1 error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FD_1 (Q,D,C,E);
output Q;
input D;
input C;
input E;
wire Dtemp;
// Xilinx FD instance
FD_1 FD_z (.Q(Q),.D(Dtemp),.C(C));
// Error injection
xor (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FD_1 FD_1 error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FD_1 (Q,D,C,E);
output Q;
input D;
input C;
input E;
wire Qtemp;
// Xilinx FD instance
FD_1 FD_z (.Q(Qtemp),.D(D),.C(C));
// Error injection
xor (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDC FDC error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDC (Q,D,C,CLR,E);
output Q;
input D;
input C;
input E;
input CLR;
wire Dtemp;
// Xilinx FD instance
FDC FD_z (.Q(Q),.D(Dtemp),.C(C),.CLR(CLR));
// Error injection
xor (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDC FDC error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDC (Q,D,C,CLR,E);
output Q;
input D;
input C;
input E;
input CLR;
wire Qtemp;
// Xilinx FD instance
FDC FD_z (.Q(Qtemp),.D(D),.C(C),.CLR(CLR));
// Error injection
xor (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDC_1 FDC_1 error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDC_1 (Q,D,C,CLR,E);
output Q;
input D;
input C;
input E;
input CLR;
wire Dtemp;
// Xilinx FD instance
FDC_1 FD_z (.Q(Q),.D(Dtemp),.C(C),.CLR(CLR));
// Error injection
xor (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDC_1 FDC_1 error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDC_1 (Q,D,C,CLR,E);
output Q;
input D;
input C;
input E;
input CLR;
wire Qtemp;
// Xilinx FD instance
FDC_1 FD_z (.Q(Qtemp),.D(D),.C(C),.CLR(CLR));
// Error injection
xor (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDCE FDCE error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDCE (Q,D,C,CLR,CE,E);
output Q;
input D;
input C;
input E;
input CLR;
input CE;
wire Dtemp;
// Xilinx FD instance
FDCE FD_z (.Q(Q),.D(Dtemp),.C(C),.CLR(CLR),.CE(CE));
// Error injection
xor (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDCE FDCE error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDCE (Q,D,C,CLR,CE,E);
output Q;
input D;
input C;
input E;
input CLR;
input CE;
wire Qtemp;
// Xilinx FD instance
FDCE FD_z (.Q(Qtemp),.D(D),.C(C),.CLR(CLR),.CE(CE));
// Error injection
xor (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDCE_1 FDCE error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDCE_1 (Q,D,C,CLR,CE,E);
output Q;
input D;
input C;
input E;
input CLR;
input CE;
wire Dtemp;
// Xilinx FD instance
FDCE_1 FD_z (.Q(Q),.D(Dtemp),.C(C),.CLR(CLR),.CE(CE));
// Error injection
xor (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDCE_1 FDCE_1 error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDCE_1 (Q,D,C,CLR,CE,E);
output Q;
input D;
input C;
input E;
input CLR;
input CE;
wire Qtemp;
// Xilinx FD instance
FDCE_1 FD_z (.Q(Qtemp),.D(D),.C(C),.CLR(CLR),.CE(CE));
// Error injection
xor (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDCP FDCP error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDCP (Q,D,C,CLR,PRE,E);
output Q;
input D;
input C;
input E;
input CLR;
input PRE;
wire Dtemp;
// Xilinx FD instance
FDCP FD_z (.Q(Q),.D(Dtemp),.C(C),.CLR(CLR),.PRE(PRE));
// Error injection
xor (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDCP FDCP error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDCP (Q,D,C,CLR,PRE,E);
output Q;
input D;
input C;
input E;
input CLR;
input PRE;
wire Qtemp;
// Xilinx FD instance
FDCP FD_z (.Q(Qtemp),.D(D),.C(C),.CLR(CLR),.PRE(PRE));
// Error injection
xor (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDCP_1 FDCP_1 error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDCP_1 (Q,D,C,CLR,PRE,E);
output Q;
input D;
input C;
input E;
input CLR;
input PRE;
wire Dtemp;
// Xilinx FD instance
FDCP_1 FD_z (.Q(Q),.D(Dtemp),.C(C),.CLR(CLR),.PRE(PRE));
// Error injection
xor (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDCP_1 FDCP_1 error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDCP_1 (Q,D,C,CLR,PRE,E);
output Q;
input D;
input C;
input E;
input CLR;
input PRE;
wire Qtemp;
// Xilinx FD instance
FDCP_1 FD_z (.Q(Qtemp),.D(D),.C(C),.CLR(CLR),.PRE(PRE));
// Error injection
xor (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDCPE FDCPE error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDCPE (Q,D,C,CLR,PRE,CE,E);
output Q;
input D;
input C;
input E;
input CLR;
input PRE;
input CE;
wire Dtemp;
// Xilinx FD instance
FDCPE FD_z (.Q(Q),.D(Dtemp),.C(C),.CLR(CLR),.PRE(PRE),.CE(CE));
// Error injection
xor (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDCPE FDCPE error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDCPE (Q,D,C,CLR,PRE,CE,E);
output Q;
input D;
input C;
input E;
input CLR;
input PRE;
input CE;
wire Qtemp;
// Xilinx FD instance
FDCPE FD_z (.Q(Qtemp),.D(D),.C(C),.CLR(CLR),.PRE(PRE),.CE(CE));
// Error injection
xor (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDCPE_1 FDCPE_1 error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDCPE_1 (Q,D,C,CLR,PRE,CE,E);
output Q;
input D;
input C;
input E;
input CLR;
input PRE;
input CE;
wire Dtemp;
// Xilinx FD instance
FDCPE_1 FD_z (.Q(Q),.D(Dtemp),.C(C),.CLR(CLR),.PRE(PRE),.CE(CE));
// Error injection
xor (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDCPE_1 FDCPE_1 error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDCPE_1 (Q,D,C,CLR,PRE,CE,E);
output Q;
input D;
input C;
input E;
input CLR;
input PRE;
input CE;
wire Qtemp;
// Xilinx FD instance
FDCPE_1 FD_z (.Q(Qtemp),.D(D),.C(C),.CLR(CLR),.PRE(PRE),.CE(CE));
// Error injection
xor (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDE FDE error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDE (Q,D,C,CE,E);
output Q;
input D;
input C;
input E;
input CE;
wire Dtemp;
// Xilinx FD instance
FDE FD_z (.Q(Q),.D(Dtemp),.C(C),.CE(CE));
// Error injection
xor (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDE FDE error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDE (Q,D,C,CE,E);
output Q;
input D;
input C;
input E;
input CE;
wire Qtemp;
// Xilinx FD instance
FDE FD_z (.Q(Qtemp),.D(D),.C(C),.CE(CE));
// Error injection
xor (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDE_1 FDE_1 error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDE_1 (Q,D,C,CE,E);
output Q;
input D;
input C;
input E;
input CE;
wire Dtemp;
// Xilinx FD instance
FDE_1 FD_z (.Q(Q),.D(Dtemp),.C(C),.CE(CE));
// Error injection
xor (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDE_1 FDE_1 error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDE_1 (Q,D,C,CE,E);
output Q;
input D;
input C;
input E;
input CE;
wire Qtemp;
// Xilinx FD instance
FDE_1 FD_z (.Q(Qtemp),.D(D),.C(C),.CE(CE));
// Error injection
xor (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDP FDP error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDP (Q,D,C,PRE,E);
output Q;
input D;
input C;
input E;
input PRE;
wire Dtemp;
// Xilinx FD instance
FDP FD_z (.Q(Q),.D(Dtemp),.C(C),.PRE(PRE));
// Error injection
xor (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDP FDP error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDP (Q,D,C,PRE,E);
output Q;
input D;
input C;
input E;
input PRE;
wire Qtemp;
// Xilinx FD instance
FDP FD_z (.Q(Qtemp),.D(D),.C(C),.PRE(PRE));
// Error injection
xor (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDP_1 FDP_1 error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDP_1 (Q,D,C,PRE,E);
output Q;
input D;
input C;
input E;
input PRE;
wire Dtemp;
// Xilinx FD instance
FDP_1 FD_z (.Q(Q),.D(Dtemp),.C(C),.PRE(PRE));
// Error injection
xor (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDP_1 FDP_1 error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDP_1 (Q,D,C,PRE,E);
output Q;
input D;
input C;
input E;
input PRE;
wire Qtemp;
// Xilinx FD instance
FDP_1 FD_z (.Q(Qtemp),.D(D),.C(C),.PRE(PRE));
// Error injection
xor (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDPE FDPE error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDPE (Q,D,C,PRE,CE,E);
output Q;
input D;
input C;
input E;
input PRE;
input CE;
wire Dtemp;
// Xilinx FD instance
FDPE FD_z (.Q(Q),.D(Dtemp),.C(C),.PRE(PRE),.CE(CE));
// Error injection
xor (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDPE FDPE error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDPE (Q,D,C,PRE,CE,E);
output Q;
input D;
input C;
input E;
input PRE;
input CE;
wire Qtemp;
// Xilinx FD instance
FDPE FD_z (.Q(Qtemp),.D(D),.C(C),.PRE(PRE),.CE(CE));
// Error injection
xor (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDPE_1 FDPE_1 error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDPE_1 (Q,D,C,PRE,CE,E);
output Q;
input D;
input C;
input E;
input PRE;
input CE;
wire Dtemp;
// Xilinx FD instance
FDPE_1 FD_z (.Q(Q),.D(Dtemp),.C(C),.PRE(PRE),.CE(CE));
// Error injection
xor (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDPE_1 FDPE_1 error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDPE_1 (Q,D,C,PRE,CE,E);
output Q;
input D;
input C;
input E;
input PRE;
input CE;
wire Qtemp;
// Xilinx FD instance
FDPE_1 FD_z (.Q(Qtemp),.D(D),.C(C),.PRE(PRE),.CE(CE));
// Error injection
xor (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDR FDR error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDR (Q,D,C,R,E);
output Q;
input D;
input C;
input E;
input R;
wire Dtemp;
// Xilinx FD instance
FDR FD_z (.Q(Q),.D(Dtemp),.C(C),.R(R));
// Error injection
xor (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDR FDR error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDR (Q,D,C,R,E);
parameter INIT=1'b0;
output Q;
input D;
input C;
input E;
input R;
wire Qtemp;
defparam FD_z.INIT=INIT;
// Xilinx FD instance
FDR FD_z (.Q(Qtemp),.D(D),.C(C),.R(R));
// Error injection
xor (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDR_1 FDR_1 error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDR_1 (Q,D,C,R,E);
output Q;
input D;
input C;
input E;
input R;
wire Dtemp;
// Xilinx FD instance
FDR_1 FD_z (.Q(Q),.D(Dtemp),.C(C),.R(R));
// Error injection
xor (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDR_1 FDR_1 error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDR_1 (Q,D,C,R,E);
output Q;
input D;
input C;
input E;
input R;
wire Qtemp;
// Xilinx FD instance
FDR_1 FD_z (.Q(Qtemp),.D(D),.C(C),.R(R));
// Error injection
xor (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDRE FDRE error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDRE (Q,D,C,R,CE,E);
output Q;
input D;
input C;
input E;
input R;
input CE;
wire Dtemp;
// Xilinx FD instance
FDRE FD_z (.Q(Q),.D(Dtemp),.C(C),.R(R),.CE(CE));
// Error injection
xor (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDRE FDRE error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDRE (Q,D,C,R,CE,E);
parameter INIT=1'b0;
output Q;
input D;
input C;
input E;
input R;
input CE;
wire Qtemp;
// Xilinx FD instance
FDRE #(.INIT(INIT)) FD_z (.Q(Qtemp),.D(D),.C(C),.R(R),.CE(CE));
// Error injection
xor (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDRE_1 FDRE_1 error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDRE_1 (Q,D,C,R,CE,E);
output Q;
input D;
input C;
input E;
input R;
input CE;
wire Dtemp;
// Xilinx FD instance
FDRE_1 FD_z (.Q(Q),.D(Dtemp),.C(C),.R(R),.CE(CE));
// Error injection
xor (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDRE_1 FDRE_1 error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDRE_1 (Q,D,C,R,CE,E);
output Q;
input D;
input C;
input E;
input R;
input CE;
wire Qtemp;
// Xilinx FD instance
FDRE_1 FD_z (.Q(Qtemp),.D(D),.C(C),.R(R),.CE(CE));
// Error injection
xor (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDRS FDRS error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDRS (Q,D,C,R,S,E);
output Q;
input D;
input C;
input E;
input R;
input S;
wire Dtemp;
// Xilinx FD instance
FDRS FD_z (.Q(Q),.D(Dtemp),.C(C),.R(R),.S(S));
// Error injection
xor (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDRS FDRS error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDRS (Q,D,C,R,S,E);
output Q;
input D;
input C;
input E;
input R;
input S;
wire Qtemp;
// Xilinx FD instance
FDRS FD_z (.Q(Qtemp),.D(D),.C(C),.R(R),.S(S));
// Error injection
xor (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDRS_1 FDRS_1 error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDRS_1 (Q,D,C,R,S,E);
output Q;
input D;
input C;
input E;
input R;
input S;
wire Dtemp;
// Xilinx FD instance
FDRS_1 FD_z (.Q(Q),.D(Dtemp),.C(C),.R(R),.S(S));
// Error injection
xor (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDRS_1 FDRS_1 error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDRS_1 (Q,D,C,R,S,E);
output Q;
input D;
input C;
input E;
input R;
input S;
wire Qtemp;
// Xilinx FD instance
FDRS_1 FD_z (.Q(Qtemp),.D(D),.C(C),.R(R),.S(S));
// Error injection
xor (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDRSE FDRS error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDRSE (Q,D,C,R,S,CE,E);
output Q;
input D;
input C;
input E;
input R;
input S;
input CE;
wire Dtemp;
// Xilinx FD instance
FDRSE FD_z (.Q(Q),.D(Dtemp),.C(C),.R(R),.S(S),.CE(CE));
// Error injection
xor (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDRSE FDRSE error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDRSE (Q,D,C,R,S,CE,E);
output Q;
input D;
input C;
input E;
input R;
input S;
input CE;
wire Qtemp;
// Xilinx FD instance
FDRSE FD_z (.Q(Qtemp),.D(D),.C(C),.R(R),.S(S),.CE(CE));
// Error injection
xor (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDRSE_1 FDRSE_1 error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDRSE_1 (Q,D,C,R,S,CE,E);
output Q;
input D;
input C;
input E;
input R;
input S;
input CE;
wire Dtemp;
// Xilinx FD instance
FDRSE_1 FD_z (.Q(Q),.D(Dtemp),.C(C),.R(R),.S(S),.CE(CE));
// Error injection
xor (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDRSE_1 FDRSE_1 error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDRSE_1 (Q,D,C,R,S,CE,E);
output Q;
input D;
input C;
input E;
input R;
input S;
input CE;
wire Qtemp;
// Xilinx FD instance
FDRSE_1 FD_z (.Q(Qtemp),.D(D),.C(C),.R(R),.S(S),.CE(CE));
// Error injection
xor (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDS FDS error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDS (Q,D,C,S,E);
output Q;
input D;
input C;
input E;
input S;
wire Dtemp;
// Xilinx FD instance
FDS FD_z (.Q(Q),.D(Dtemp),.C(C),.S(S));
// Error injection
xor (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDS FDS error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDS (Q,D,C,S,E);
output Q;
input D;
input C;
input E;
input S;
wire Qtemp;
// Xilinx FD instance
FDS FD_z (.Q(Qtemp),.D(D),.C(C),.S(S));
// Error injection
xor (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDS_1 FDS_1 error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDS_1 (Q,D,C,S,E);
output Q;
input D;
input C;
input E;
input S;
wire Dtemp;
// Xilinx FD instance
FDS_1 FD_z (.Q(Q),.D(Dtemp),.C(C),.S(S));
// Error injection
xor (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDS_1 FDS_1 error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDS_1 (Q,D,C,S,E);
output Q;
input D;
input C;
input E;
input S;
wire Qtemp;
// Xilinx FD instance
FDS_1 FD_z (.Q(Qtemp),.D(D),.C(C),.S(S));
// Error injection
xor (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDSE FDSE error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDSE (Q,D,C,S,CE,E);
output Q;
input D;
input C;
input E;
input S;
input CE;
wire Dtemp;
// Xilinx FD instance
FDSE FD_z (.Q(Q),.D(Dtemp),.C(C),.S(S),.CE(CE));
// Error injection
xor (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDSE FDSE error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDSE (Q,D,C,S,CE,E);
output Q;
input D;
input C;
input E;
input S;
input CE;
wire Qtemp;
// Xilinx FD instance
FDSE FD_z (.Q(Qtemp),.D(D),.C(C),.S(S),.CE(CE));
// Error injection
xor (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDSE_1 FDSE_1 error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDSE_1 (Q,D,C,S,CE,E);
output Q;
input D;
input C;
input E;
input S;
input CE;
wire Dtemp;
// Xilinx FD instance
FDSE_1 FD_z (.Q(Q),.D(Dtemp),.C(C),.S(S),.CE(CE));
// Error injection
xor (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDSE_1 FDSE_1 error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDSE_1 (Q,D,C,S,CE,E);
output Q;
input D;
input C;
input E;
input S;
input CE;
wire Qtemp;
// Xilinx FD instance
FDSE_1 FD_z (.Q(Qtemp),.D(D),.C(C),.S(S),.CE(CE));
// Error injection
xor (Q,Qtemp,E);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:29:35 03/29/2015
// Design Name:
// Module Name: regfileparam_behav
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module regfileparam_behav
#(parameter BITSIZE = 16,
parameter ADDSIZE = 4)
(output [BITSIZE-1:0] adat,
output [BITSIZE-1:0] bdat,
input [ADDSIZE-1:0] ra, // Read A Address
input [ADDSIZE-1:0] rb, // Read B Address
input [ADDSIZE-1:0] rw, // Write Address
input [BITSIZE-1:0] wdat,
input wren,
input clk, rst
);
integer i;
reg [BITSIZE-1:0] array_reg [2**ADDSIZE-1:0];
always @(posedge clk, negedge rst) begin
if(~rst) begin
for(i = 0; i < 2**ADDSIZE; i = i + 1) begin
array_reg[i] <= 0;
end
end
else if(wren) begin
array_reg[rw] <= wdat;
end
end
assign adat = array_reg[ra];
assign bdat = array_reg[rb];
endmodule
|
module stimulus (output reg A, B);
initial begin
{A, B} = 2'b00;
#10 {A, B} = 2'b01;
#10 {A, B} = 2'b10;
#10 {A, B} = 2'b11;
end
endmodule
module scoreboard (input Y, A, B);
function truth_table (input a, b);
reg [1:0] gate_operand;
reg gate_output;
begin
gate_operand[1:0] = {a, b};
case (gate_operand)
2'b00: gate_output = 1;
2'b01: gate_output = 1;
2'b10: gate_output = 1;
2'b11: gate_output = 0;
endcase
truth_table = gate_output;
end
endfunction
reg Y_t;
always @(A or B) begin
Y_t = truth_table (A, B);
#1;
//$display ("a = %b, b = %b, Y_s = %b, Y = %b", A, B, Y_s, Y);
if (Y_t !== Y) begin
$display("FAILED! - mismatch found for inputs %b and %b in NAND operation", A, B);
$finish;
end
end
endmodule
module test;
stimulus stim (A, B);
nand_gate duv (.a_i(A), .b_i(B), .c_o(Y) );
scoreboard mon (Y, A, B);
initial begin
#100;
$display("PASSED");
$finish;
end
endmodule
|
`timescale 1ns/100ps
// -----------------------------------------------------------------------------
// One-level up Hierarchical module
// -----------------------------------------------------------------------------
module a_h
// Verilog 2001 style
#(parameter M=5, N=3)
(
// Outputs
output [N-1:0] [M-1:0]a_o1 // From Ia of autoinst_sv_kulkarni_base.v
// End of automatics
// AUTOINPUT*/
);
/*AUTOWIRE*/
autoinst_sv_kulkarni_base
#(/*AUTOINSTPARAM*/)
Ia
(/*AUTOINST*/); // <---- BUG?
endmodule
// -----------------------------------------------------------------------------
// Top-level module or Testbench
// -----------------------------------------------------------------------------
module top;
parameter M=4;
parameter N=2;
wire [N-1:0] a_o1;
logic [N-1:0][M-1:0] a_i1;
logic temp;
/*AUTOWIRE*/
// Workaround to fix multi-dimensional port problem
// a) Set "verilog-auto-inst-vector = nil"
// b) ----> a_h AUTO_TEMPLATE ( .\(.*\) (\1), ); */
a_h #(/*AUTOINSTPARAM*/)
Ua_h
(/*AUTOINST*/); // <---- BUG?
// Stimulus
initial begin
a_i1 = { 4'h0, 4'h2 };
#5;
$display("Loop Init: a_i1 = { %h, %h } a_o1 = %h\n",
a_i1[1], a_i1[0], a_o1);
#5;
for (int i=0; i<1; i++) begin
for (int j=0; j<N; j++) begin
temp = 1'b0;
for (int k=0; k<M; k++) begin
a_i1[j][k] = temp;
temp = ~temp;
end
end
#5;
$display("Loop %0d: a_i1 = { %h, %h } a_o1 = %h\n",
i, a_i1[1], a_i1[0], a_o1);
#5;
end
end
endmodule
|
// (C) 2001-2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// --------------------------------------------------------------------------------
//| Avalon ST Idle Inserter
// --------------------------------------------------------------------------------
`timescale 1ns / 100ps
module altera_avalon_st_idle_inserter (
// Interface: clk
input clk,
input reset_n,
// Interface: ST in
output reg in_ready,
input in_valid,
input [7: 0] in_data,
// Interface: ST out
input out_ready,
output reg out_valid,
output reg [7: 0] out_data
);
// ---------------------------------------------------------------------
//| Signal Declarations
// ---------------------------------------------------------------------
reg received_esc;
wire escape_char, idle_char;
// ---------------------------------------------------------------------
//| Thingofamagick
// ---------------------------------------------------------------------
assign idle_char = (in_data == 8'h4a);
assign escape_char = (in_data == 8'h4d);
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
received_esc <= 0;
end else begin
if (in_valid & out_ready) begin
if ((idle_char | escape_char) & ~received_esc & out_ready) begin
received_esc <= 1;
end else begin
received_esc <= 0;
end
end
end
end
always @* begin
//we are always valid
out_valid = 1'b1;
in_ready = out_ready & (~in_valid | ((~idle_char & ~escape_char) | received_esc));
out_data = (~in_valid) ? 8'h4a : //if input is not valid, insert idle
(received_esc) ? in_data ^ 8'h20 : //escaped once, send data XOR'd
(idle_char | escape_char) ? 8'h4d : //input needs escaping, send escape_char
in_data; //send data
end
endmodule
|
/*
* For a non-blocking delay the last NB assign in the same thread
* at the same time must set the final result, but you are allowed
* to have multiple assignments in the queue.
*/
module top;
reg passed = 1'b1;
reg out;
real rout;
integer delay;
initial begin
out <= 1'b1;
out <= 1'b0;
rout <= 0.0;
rout <= 1.0;
#1;
if (out !== 1'b0) begin
$display("FAILED: zero delay, expected 1'b0, got %b", out);
passed = 1'b0;
end
if (rout != 1.0) begin
$display("FAILED: zero delay (real), expected 1.0, got %f", rout);
passed = 1'b0;
end
out <= #1 1'b0;
out <= #1 1'b1;
rout <= #1 0.0;
rout <= #1 2.0;
#2;
if (out !== 1'b1) begin
$display("FAILED: constant delay, expected 1'b1, got %b", out);
passed = 1'b0;
end
if (rout != 2.0) begin
$display("FAILED: constant delay (real), expected 2.0, got %f", rout);
passed = 1'b0;
end
delay = 2;
out <= #(delay) 1'b1;
out <= #(delay) 1'b0;
rout <= #(delay) 0.0;
rout <= #(delay) 3.0;
#(delay+1);
if (out !== 1'b0) begin
$display("FAILED: calculated delay, expected 1'b0, got %b", out);
passed = 1'b0;
end
if (rout != 3.0) begin
$display("FAILED: calculated delay (real), expected 3.0, got %f", rout);
passed = 1'b0;
end
out <= #1 1'b1;
out <= #3 1'b0;
out <= #5 1'b1;
rout <= #1 1.0;
rout <= #3 3.0;
rout <= #5 5.0;
#2;
if (out !== 1'b1) begin
$display("FAILED: first delay, expected 1'b1, got %b", out);
passed = 1'b0;
end
if (rout != 1.0) begin
$display("FAILED: first delay (real), expected 1.0, got %f", rout);
passed = 1'b0;
end
#2;
if (out !== 1'b0) begin
$display("FAILED: second delay, expected 1'b0, got %b", out);
passed = 1'b0;
end
if (rout != 3.0) begin
$display("FAILED: second delay (real), expected 3.0, got %f", rout);
passed = 1'b0;
end
#2;
if (out !== 1'b1) begin
$display("FAILED: third delay, expected 1'b1, got %b", out);
passed = 1'b0;
end
if (rout != 5.0) begin
$display("FAILED: third delay (real), expected 5.0, got %f", rout);
passed = 1'b0;
end
if (passed) $display("PASSED");
end
endmodule
|
`timescale 1 ns / 1 ps
module pmod_io_switch_v1_0 #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S00_AXI
parameter integer C_S00_AXI_DATA_WIDTH = 32,
parameter integer C_S00_AXI_ADDR_WIDTH = 4
)
(
// Users to add ports here
output wire [7:0] sw2pl_data_in,
input wire [7:0] pl2sw_data_o,
input wire [7:0] pl2sw_tri_o,
input wire [7:0] pmod2sw_data_in,
output wire [7:0] sw2pmod_data_out,
output wire [7:0] sw2pmod_tri_out,
output wire pwm_i_in,
input wire pwm_o_in,
input wire pwm_t_in,
output wire cap0_i_in,
input wire gen0_o_in,
input wire gen0_t_in,
output wire spick_i_in,
input wire spick_o_in,
input wire spick_t_in,
output wire miso_i_in,
input wire miso_o_in,
input wire miso_t_in,
output wire mosi_i_in,
input wire mosi_o_in,
input wire mosi_t_in,
output wire ss_i_in,
input wire ss_o_in,
input wire ss_t_in,
output wire sda_i_in,
input wire sda_o_in,
input wire sda_t_in,
output wire scl_i_in,
input wire scl_o_in,
input wire scl_t_in,
// User ports ends
// Do not modify the ports beyond this line
// Ports of Axi Slave Bus Interface S00_AXI
input wire s00_axi_aclk,
input wire s00_axi_aresetn,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
input wire [2 : 0] s00_axi_awprot,
input wire s00_axi_awvalid,
output wire s00_axi_awready,
input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
input wire s00_axi_wvalid,
output wire s00_axi_wready,
output wire [1 : 0] s00_axi_bresp,
output wire s00_axi_bvalid,
input wire s00_axi_bready,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
input wire [2 : 0] s00_axi_arprot,
input wire s00_axi_arvalid,
output wire s00_axi_arready,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
output wire [1 : 0] s00_axi_rresp,
output wire s00_axi_rvalid,
input wire s00_axi_rready
);
// Instantiation of Axi Bus Interface S00_AXI
pmod_io_switch_v1_0_S00_AXI # (
.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH)
) pmod_io_switch_v1_0_S00_AXI_inst (
.sw2pl_data_in(sw2pl_data_in),
.pl2sw_data_o(pl2sw_data_o),
.pl2sw_tri_o(pl2sw_tri_o),
.pmod2sw_data_in(pmod2sw_data_in),
.sw2pmod_data_out(sw2pmod_data_out),
.sw2pmod_tri_out(sw2pmod_tri_out),
// timer
.pwm_i_in(pwm_i_in),
.pwm_o_in(pwm_o_in),
.pwm_t_in(pwm_t_in),
.cap0_i_in(cap0_i_in),
.gen0_o_in(gen0_o_in),
.gen0_t_in(gen0_t_in),
// SPI channel
.spick_i_in(spick_i_in),
.spick_o_in(spick_o_in),
.spick_t_in(spick_t_in),
.miso_i_in(miso_i_in),
.miso_o_in(miso_o_in),
.miso_t_in(miso_t_in),
.mosi_i_in(mosi_i_in),
.mosi_o_in(mosi_o_in),
.mosi_t_in(mosi_t_in),
.ss_i_in(ss_i_in),
.ss_o_in(ss_o_in),
.ss_t_in(ss_t_in),
// I2C channel
.sda_i_in(sda_i_in),
.sda_o_in(sda_o_in),
.sda_t_in(sda_t_in),
.scl_i_in(scl_i_in),
.scl_o_in(scl_o_in),
.scl_t_in(scl_t_in),
.S_AXI_ACLK(s00_axi_aclk),
.S_AXI_ARESETN(s00_axi_aresetn),
.S_AXI_AWADDR(s00_axi_awaddr),
.S_AXI_AWPROT(s00_axi_awprot),
.S_AXI_AWVALID(s00_axi_awvalid),
.S_AXI_AWREADY(s00_axi_awready),
.S_AXI_WDATA(s00_axi_wdata),
.S_AXI_WSTRB(s00_axi_wstrb),
.S_AXI_WVALID(s00_axi_wvalid),
.S_AXI_WREADY(s00_axi_wready),
.S_AXI_BRESP(s00_axi_bresp),
.S_AXI_BVALID(s00_axi_bvalid),
.S_AXI_BREADY(s00_axi_bready),
.S_AXI_ARADDR(s00_axi_araddr),
.S_AXI_ARPROT(s00_axi_arprot),
.S_AXI_ARVALID(s00_axi_arvalid),
.S_AXI_ARREADY(s00_axi_arready),
.S_AXI_RDATA(s00_axi_rdata),
.S_AXI_RRESP(s00_axi_rresp),
.S_AXI_RVALID(s00_axi_rvalid),
.S_AXI_RREADY(s00_axi_rready)
);
// Add user logic here
// User logic ends
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__XNOR2_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__XNOR2_PP_BLACKBOX_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__xnor2 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__XNOR2_PP_BLACKBOX_V
|
//----------------------------------------------------------------------------
// Copyright (C) 2009 , Olivier Girard
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of the authors nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
// THE POSSIBILITY OF SUCH DAMAGE
//
//----------------------------------------------------------------------------
//
// *File Name: omsp_dbg.v
//
// *Module Description:
// Debug interface
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev: 175 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2013-01-30 22:21:42 +0100 (Mit, 30. Jän 2013) $
//----------------------------------------------------------------------------
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_defines.v"
`endif
module omsp_dbg (
// OUTPUTs
dbg_cpu_reset, // Reset CPU from debug interface
dbg_freeze, // Freeze peripherals
dbg_halt_cmd, // Halt CPU command
dbg_i2c_sda_out, // Debug interface: I2C SDA OUT
dbg_mem_addr, // Debug address for rd/wr access
dbg_mem_dout, // Debug unit data output
dbg_mem_en, // Debug unit memory enable
dbg_mem_wr, // Debug unit memory write
dbg_reg_wr, // Debug unit CPU register write
dbg_uart_txd, // Debug interface: UART TXD
// INPUTs
cpu_en_s, // Enable CPU code execution (synchronous)
cpu_id, // CPU ID
cpu_nr_inst, // Current oMSP instance number
cpu_nr_total, // Total number of oMSP instances-1
dbg_clk, // Debug unit clock
dbg_en_s, // Debug interface enable (synchronous)
dbg_halt_st, // Halt/Run status from CPU
dbg_i2c_addr, // Debug interface: I2C Address
dbg_i2c_broadcast, // Debug interface: I2C Broadcast Address (for multicore systems)
dbg_i2c_scl, // Debug interface: I2C SCL
dbg_i2c_sda_in, // Debug interface: I2C SDA IN
dbg_mem_din, // Debug unit Memory data input
dbg_reg_din, // Debug unit CPU register data input
dbg_rst, // Debug unit reset
dbg_uart_rxd, // Debug interface: UART RXD (asynchronous)
decode_noirq, // Frontend decode instruction
eu_mab, // Execution-Unit Memory address bus
eu_mb_en, // Execution-Unit Memory bus enable
eu_mb_wr, // Execution-Unit Memory bus write transfer
fe_mdb_in, // Frontend Memory data bus input
pc, // Program counter
puc_pnd_set // PUC pending set for the serial debug interface
);
// OUTPUTs
//=========
output dbg_cpu_reset; // Reset CPU from debug interface
output dbg_freeze; // Freeze peripherals
output dbg_halt_cmd; // Halt CPU command
output dbg_i2c_sda_out; // Debug interface: I2C SDA OUT
output [15:0] dbg_mem_addr; // Debug address for rd/wr access
output [15:0] dbg_mem_dout; // Debug unit data output
output dbg_mem_en; // Debug unit memory enable
output [1:0] dbg_mem_wr; // Debug unit memory write
output dbg_reg_wr; // Debug unit CPU register write
output dbg_uart_txd; // Debug interface: UART TXD
// INPUTs
//=========
input cpu_en_s; // Enable CPU code execution (synchronous)
input [31:0] cpu_id; // CPU ID
input [7:0] cpu_nr_inst; // Current oMSP instance number
input [7:0] cpu_nr_total; // Total number of oMSP instances-1
input dbg_clk; // Debug unit clock
input dbg_en_s; // Debug interface enable (synchronous)
input dbg_halt_st; // Halt/Run status from CPU
input [6:0] dbg_i2c_addr; // Debug interface: I2C Address
input [6:0] dbg_i2c_broadcast; // Debug interface: I2C Broadcast Address (for multicore systems)
input dbg_i2c_scl; // Debug interface: I2C SCL
input dbg_i2c_sda_in; // Debug interface: I2C SDA IN
input [15:0] dbg_mem_din; // Debug unit Memory data input
input [15:0] dbg_reg_din; // Debug unit CPU register data input
input dbg_rst; // Debug unit reset
input dbg_uart_rxd; // Debug interface: UART RXD (asynchronous)
input decode_noirq; // Frontend decode instruction
input [15:0] eu_mab; // Execution-Unit Memory address bus
input eu_mb_en; // Execution-Unit Memory bus enable
input [1:0] eu_mb_wr; // Execution-Unit Memory bus write transfer
input [15:0] fe_mdb_in; // Frontend Memory data bus input
input [15:0] pc; // Program counter
input puc_pnd_set; // PUC pending set for the serial debug interface
//=============================================================================
// 1) WIRE & PARAMETER DECLARATION
//=============================================================================
// Diverse wires and registers
wire [5:0] dbg_addr;
wire [15:0] dbg_din;
wire dbg_wr;
reg mem_burst;
wire dbg_reg_rd;
wire dbg_mem_rd;
reg dbg_mem_rd_dly;
wire dbg_swbrk;
wire dbg_rd;
reg dbg_rd_rdy;
wire mem_burst_rd;
wire mem_burst_wr;
wire brk0_halt;
wire brk0_pnd;
wire [15:0] brk0_dout;
wire brk1_halt;
wire brk1_pnd;
wire [15:0] brk1_dout;
wire brk2_halt;
wire brk2_pnd;
wire [15:0] brk2_dout;
wire brk3_halt;
wire brk3_pnd;
wire [15:0] brk3_dout;
// Number of registers
parameter NR_REG = 25;
// Register addresses
parameter CPU_ID_LO = 6'h00;
parameter CPU_ID_HI = 6'h01;
parameter CPU_CTL = 6'h02;
parameter CPU_STAT = 6'h03;
parameter MEM_CTL = 6'h04;
parameter MEM_ADDR = 6'h05;
parameter MEM_DATA = 6'h06;
parameter MEM_CNT = 6'h07;
`ifdef DBG_HWBRK_0
parameter BRK0_CTL = 6'h08;
parameter BRK0_STAT = 6'h09;
parameter BRK0_ADDR0 = 6'h0A;
parameter BRK0_ADDR1 = 6'h0B;
`endif
`ifdef DBG_HWBRK_1
parameter BRK1_CTL = 6'h0C;
parameter BRK1_STAT = 6'h0D;
parameter BRK1_ADDR0 = 6'h0E;
parameter BRK1_ADDR1 = 6'h0F;
`endif
`ifdef DBG_HWBRK_2
parameter BRK2_CTL = 6'h10;
parameter BRK2_STAT = 6'h11;
parameter BRK2_ADDR0 = 6'h12;
parameter BRK2_ADDR1 = 6'h13;
`endif
`ifdef DBG_HWBRK_3
parameter BRK3_CTL = 6'h14;
parameter BRK3_STAT = 6'h15;
parameter BRK3_ADDR0 = 6'h16;
parameter BRK3_ADDR1 = 6'h17;
`endif
parameter CPU_NR = 6'h18;
// Register one-hot decoder
parameter BASE_D = {{NR_REG-1{1'b0}}, 1'b1};
parameter CPU_ID_LO_D = (BASE_D << CPU_ID_LO);
parameter CPU_ID_HI_D = (BASE_D << CPU_ID_HI);
parameter CPU_CTL_D = (BASE_D << CPU_CTL);
parameter CPU_STAT_D = (BASE_D << CPU_STAT);
parameter MEM_CTL_D = (BASE_D << MEM_CTL);
parameter MEM_ADDR_D = (BASE_D << MEM_ADDR);
parameter MEM_DATA_D = (BASE_D << MEM_DATA);
parameter MEM_CNT_D = (BASE_D << MEM_CNT);
`ifdef DBG_HWBRK_0
parameter BRK0_CTL_D = (BASE_D << BRK0_CTL);
parameter BRK0_STAT_D = (BASE_D << BRK0_STAT);
parameter BRK0_ADDR0_D = (BASE_D << BRK0_ADDR0);
parameter BRK0_ADDR1_D = (BASE_D << BRK0_ADDR1);
`endif
`ifdef DBG_HWBRK_1
parameter BRK1_CTL_D = (BASE_D << BRK1_CTL);
parameter BRK1_STAT_D = (BASE_D << BRK1_STAT);
parameter BRK1_ADDR0_D = (BASE_D << BRK1_ADDR0);
parameter BRK1_ADDR1_D = (BASE_D << BRK1_ADDR1);
`endif
`ifdef DBG_HWBRK_2
parameter BRK2_CTL_D = (BASE_D << BRK2_CTL);
parameter BRK2_STAT_D = (BASE_D << BRK2_STAT);
parameter BRK2_ADDR0_D = (BASE_D << BRK2_ADDR0);
parameter BRK2_ADDR1_D = (BASE_D << BRK2_ADDR1);
`endif
`ifdef DBG_HWBRK_3
parameter BRK3_CTL_D = (BASE_D << BRK3_CTL);
parameter BRK3_STAT_D = (BASE_D << BRK3_STAT);
parameter BRK3_ADDR0_D = (BASE_D << BRK3_ADDR0);
parameter BRK3_ADDR1_D = (BASE_D << BRK3_ADDR1);
`endif
parameter CPU_NR_D = (BASE_D << CPU_NR);
//============================================================================
// 2) REGISTER DECODER
//============================================================================
// Select Data register during a burst
wire [5:0] dbg_addr_in = mem_burst ? MEM_DATA : dbg_addr;
// Register address decode
reg [NR_REG-1:0] reg_dec;
always @(dbg_addr_in)
case (dbg_addr_in)
CPU_ID_LO : reg_dec = CPU_ID_LO_D;
CPU_ID_HI : reg_dec = CPU_ID_HI_D;
CPU_CTL : reg_dec = CPU_CTL_D;
CPU_STAT : reg_dec = CPU_STAT_D;
MEM_CTL : reg_dec = MEM_CTL_D;
MEM_ADDR : reg_dec = MEM_ADDR_D;
MEM_DATA : reg_dec = MEM_DATA_D;
MEM_CNT : reg_dec = MEM_CNT_D;
`ifdef DBG_HWBRK_0
BRK0_CTL : reg_dec = BRK0_CTL_D;
BRK0_STAT : reg_dec = BRK0_STAT_D;
BRK0_ADDR0: reg_dec = BRK0_ADDR0_D;
BRK0_ADDR1: reg_dec = BRK0_ADDR1_D;
`endif
`ifdef DBG_HWBRK_1
BRK1_CTL : reg_dec = BRK1_CTL_D;
BRK1_STAT : reg_dec = BRK1_STAT_D;
BRK1_ADDR0: reg_dec = BRK1_ADDR0_D;
BRK1_ADDR1: reg_dec = BRK1_ADDR1_D;
`endif
`ifdef DBG_HWBRK_2
BRK2_CTL : reg_dec = BRK2_CTL_D;
BRK2_STAT : reg_dec = BRK2_STAT_D;
BRK2_ADDR0: reg_dec = BRK2_ADDR0_D;
BRK2_ADDR1: reg_dec = BRK2_ADDR1_D;
`endif
`ifdef DBG_HWBRK_3
BRK3_CTL : reg_dec = BRK3_CTL_D;
BRK3_STAT : reg_dec = BRK3_STAT_D;
BRK3_ADDR0: reg_dec = BRK3_ADDR0_D;
BRK3_ADDR1: reg_dec = BRK3_ADDR1_D;
`endif
CPU_NR : reg_dec = CPU_NR_D;
// pragma coverage off
default: reg_dec = {NR_REG{1'b0}};
// pragma coverage on
endcase
// Read/Write probes
wire reg_write = dbg_wr;
wire reg_read = 1'b1;
// Read/Write vectors
wire [NR_REG-1:0] reg_wr = reg_dec & {NR_REG{reg_write}};
wire [NR_REG-1:0] reg_rd = reg_dec & {NR_REG{reg_read}};
//=============================================================================
// 3) REGISTER: CORE INTERFACE
//=============================================================================
// CPU_ID Register
//-----------------
// -------------------------------------------------------------------
// CPU_ID_LO: | 15 14 13 12 11 10 9 | 8 7 6 5 4 | 3 | 2 1 0 |
// |----------------------------+-----------------+------+-------------|
// | PER_SPACE | USER_VERSION | ASIC | CPU_VERSION |
// --------------------------------------------------------------------
// CPU_ID_HI: | 15 14 13 12 11 10 | 9 8 7 6 5 4 3 2 1 | 0 |
// |----------------------------+-------------------------------+------|
// | PMEM_SIZE | DMEM_SIZE | MPY |
// -------------------------------------------------------------------
// This register is assigned in the SFR module
// CPU_NR Register
//-----------------
// -------------------------------------------------------------------
// | 15 14 13 12 11 10 9 8 | 7 6 5 4 3 2 1 0 |
// |---------------------------------+---------------------------------|
// | CPU_TOTAL_NR | CPU_INST_NR |
// -------------------------------------------------------------------
wire [15:0] cpu_nr = {cpu_nr_total, cpu_nr_inst};
// CPU_CTL Register
//-----------------------------------------------------------------------------
// 7 6 5 4 3 2 1 0
// Reserved CPU_RST RST_BRK_EN FRZ_BRK_EN SW_BRK_EN ISTEP RUN HALT
//-----------------------------------------------------------------------------
reg [6:3] cpu_ctl;
wire cpu_ctl_wr = reg_wr[CPU_CTL];
always @ (posedge dbg_clk or posedge dbg_rst)
`ifdef DBG_RST_BRK_EN
if (dbg_rst) cpu_ctl <= 4'h6;
`else
if (dbg_rst) cpu_ctl <= 4'h2;
`endif
else if (cpu_ctl_wr) cpu_ctl <= dbg_din[6:3];
wire [7:0] cpu_ctl_full = {1'b0, cpu_ctl, 3'b000};
wire halt_cpu = cpu_ctl_wr & dbg_din[`HALT] & ~dbg_halt_st;
wire run_cpu = cpu_ctl_wr & dbg_din[`RUN] & dbg_halt_st;
wire istep = cpu_ctl_wr & dbg_din[`ISTEP] & dbg_halt_st;
// CPU_STAT Register
//------------------------------------------------------------------------------------
// 7 6 5 4 3 2 1 0
// HWBRK3_PND HWBRK2_PND HWBRK1_PND HWBRK0_PND SWBRK_PND PUC_PND Res. HALT_RUN
//------------------------------------------------------------------------------------
reg [3:2] cpu_stat;
wire cpu_stat_wr = reg_wr[CPU_STAT];
wire [3:2] cpu_stat_set = {dbg_swbrk, puc_pnd_set};
wire [3:2] cpu_stat_clr = ~dbg_din[3:2];
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) cpu_stat <= 2'b00;
else if (cpu_stat_wr) cpu_stat <= ((cpu_stat & cpu_stat_clr) | cpu_stat_set);
else cpu_stat <= (cpu_stat | cpu_stat_set);
wire [7:0] cpu_stat_full = {brk3_pnd, brk2_pnd, brk1_pnd, brk0_pnd,
cpu_stat, 1'b0, dbg_halt_st};
//=============================================================================
// 4) REGISTER: MEMORY INTERFACE
//=============================================================================
// MEM_CTL Register
//-----------------------------------------------------------------------------
// 7 6 5 4 3 2 1 0
// Reserved B/W MEM/REG RD/WR START
//
// START : - 0 : Do nothing.
// - 1 : Initiate memory transfer.
//
// RD/WR : - 0 : Read access.
// - 1 : Write access.
//
// MEM/REG: - 0 : Memory access.
// - 1 : CPU Register access.
//
// B/W : - 0 : 16 bit access.
// - 1 : 8 bit access (not valid for CPU Registers).
//
//-----------------------------------------------------------------------------
reg [3:1] mem_ctl;
wire mem_ctl_wr = reg_wr[MEM_CTL];
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) mem_ctl <= 3'h0;
else if (mem_ctl_wr) mem_ctl <= dbg_din[3:1];
wire [7:0] mem_ctl_full = {4'b0000, mem_ctl, 1'b0};
reg mem_start;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) mem_start <= 1'b0;
else mem_start <= mem_ctl_wr & dbg_din[0];
wire mem_bw = mem_ctl[3];
// MEM_DATA Register
//------------------
reg [15:0] mem_data;
reg [15:0] mem_addr;
wire mem_access;
wire mem_data_wr = reg_wr[MEM_DATA];
wire [15:0] dbg_mem_din_bw = ~mem_bw ? dbg_mem_din :
mem_addr[0] ? {8'h00, dbg_mem_din[15:8]} :
{8'h00, dbg_mem_din[7:0]};
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) mem_data <= 16'h0000;
else if (mem_data_wr) mem_data <= dbg_din;
else if (dbg_reg_rd) mem_data <= dbg_reg_din;
else if (dbg_mem_rd_dly) mem_data <= dbg_mem_din_bw;
// MEM_ADDR Register
//------------------
reg [15:0] mem_cnt;
wire mem_addr_wr = reg_wr[MEM_ADDR];
wire dbg_mem_acc = (|dbg_mem_wr | (dbg_rd_rdy & ~mem_ctl[2]));
wire dbg_reg_acc = ( dbg_reg_wr | (dbg_rd_rdy & mem_ctl[2]));
wire [15:0] mem_addr_inc = (mem_cnt==16'h0000) ? 16'h0000 :
(mem_burst & dbg_mem_acc & ~mem_bw) ? 16'h0002 :
(mem_burst & (dbg_mem_acc | dbg_reg_acc)) ? 16'h0001 : 16'h0000;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) mem_addr <= 16'h0000;
else if (mem_addr_wr) mem_addr <= dbg_din;
else mem_addr <= mem_addr + mem_addr_inc;
// MEM_CNT Register
//------------------
wire mem_cnt_wr = reg_wr[MEM_CNT];
wire [15:0] mem_cnt_dec = (mem_cnt==16'h0000) ? 16'h0000 :
(mem_burst & (dbg_mem_acc | dbg_reg_acc)) ? 16'hffff : 16'h0000;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) mem_cnt <= 16'h0000;
else if (mem_cnt_wr) mem_cnt <= dbg_din;
else mem_cnt <= mem_cnt + mem_cnt_dec;
//=============================================================================
// 5) BREAKPOINTS / WATCHPOINTS
//=============================================================================
`ifdef DBG_HWBRK_0
// Hardware Breakpoint/Watchpoint Register read select
wire [3:0] brk0_reg_rd = {reg_rd[BRK0_ADDR1],
reg_rd[BRK0_ADDR0],
reg_rd[BRK0_STAT],
reg_rd[BRK0_CTL]};
// Hardware Breakpoint/Watchpoint Register write select
wire [3:0] brk0_reg_wr = {reg_wr[BRK0_ADDR1],
reg_wr[BRK0_ADDR0],
reg_wr[BRK0_STAT],
reg_wr[BRK0_CTL]};
omsp_dbg_hwbrk dbg_hwbr_0 (
// OUTPUTs
.brk_halt (brk0_halt), // Hardware breakpoint command
.brk_pnd (brk0_pnd), // Hardware break/watch-point pending
.brk_dout (brk0_dout), // Hardware break/watch-point register data input
// INPUTs
.brk_reg_rd (brk0_reg_rd), // Hardware break/watch-point register read select
.brk_reg_wr (brk0_reg_wr), // Hardware break/watch-point register write select
.dbg_clk (dbg_clk), // Debug unit clock
.dbg_din (dbg_din), // Debug register data input
.dbg_rst (dbg_rst), // Debug unit reset
.decode_noirq (decode_noirq), // Frontend decode instruction
.eu_mab (eu_mab), // Execution-Unit Memory address bus
.eu_mb_en (eu_mb_en), // Execution-Unit Memory bus enable
.eu_mb_wr (eu_mb_wr), // Execution-Unit Memory bus write transfer
.pc (pc) // Program counter
);
`else
assign brk0_halt = 1'b0;
assign brk0_pnd = 1'b0;
assign brk0_dout = 16'h0000;
`endif
`ifdef DBG_HWBRK_1
// Hardware Breakpoint/Watchpoint Register read select
wire [3:0] brk1_reg_rd = {reg_rd[BRK1_ADDR1],
reg_rd[BRK1_ADDR0],
reg_rd[BRK1_STAT],
reg_rd[BRK1_CTL]};
// Hardware Breakpoint/Watchpoint Register write select
wire [3:0] brk1_reg_wr = {reg_wr[BRK1_ADDR1],
reg_wr[BRK1_ADDR0],
reg_wr[BRK1_STAT],
reg_wr[BRK1_CTL]};
omsp_dbg_hwbrk dbg_hwbr_1 (
// OUTPUTs
.brk_halt (brk1_halt), // Hardware breakpoint command
.brk_pnd (brk1_pnd), // Hardware break/watch-point pending
.brk_dout (brk1_dout), // Hardware break/watch-point register data input
// INPUTs
.brk_reg_rd (brk1_reg_rd), // Hardware break/watch-point register read select
.brk_reg_wr (brk1_reg_wr), // Hardware break/watch-point register write select
.dbg_clk (dbg_clk), // Debug unit clock
.dbg_din (dbg_din), // Debug register data input
.dbg_rst (dbg_rst), // Debug unit reset
.decode_noirq (decode_noirq), // Frontend decode instruction
.eu_mab (eu_mab), // Execution-Unit Memory address bus
.eu_mb_en (eu_mb_en), // Execution-Unit Memory bus enable
.eu_mb_wr (eu_mb_wr), // Execution-Unit Memory bus write transfer
.pc (pc) // Program counter
);
`else
assign brk1_halt = 1'b0;
assign brk1_pnd = 1'b0;
assign brk1_dout = 16'h0000;
`endif
`ifdef DBG_HWBRK_2
// Hardware Breakpoint/Watchpoint Register read select
wire [3:0] brk2_reg_rd = {reg_rd[BRK2_ADDR1],
reg_rd[BRK2_ADDR0],
reg_rd[BRK2_STAT],
reg_rd[BRK2_CTL]};
// Hardware Breakpoint/Watchpoint Register write select
wire [3:0] brk2_reg_wr = {reg_wr[BRK2_ADDR1],
reg_wr[BRK2_ADDR0],
reg_wr[BRK2_STAT],
reg_wr[BRK2_CTL]};
omsp_dbg_hwbrk dbg_hwbr_2 (
// OUTPUTs
.brk_halt (brk2_halt), // Hardware breakpoint command
.brk_pnd (brk2_pnd), // Hardware break/watch-point pending
.brk_dout (brk2_dout), // Hardware break/watch-point register data input
// INPUTs
.brk_reg_rd (brk2_reg_rd), // Hardware break/watch-point register read select
.brk_reg_wr (brk2_reg_wr), // Hardware break/watch-point register write select
.dbg_clk (dbg_clk), // Debug unit clock
.dbg_din (dbg_din), // Debug register data input
.dbg_rst (dbg_rst), // Debug unit reset
.decode_noirq (decode_noirq), // Frontend decode instruction
.eu_mab (eu_mab), // Execution-Unit Memory address bus
.eu_mb_en (eu_mb_en), // Execution-Unit Memory bus enable
.eu_mb_wr (eu_mb_wr), // Execution-Unit Memory bus write transfer
.pc (pc) // Program counter
);
`else
assign brk2_halt = 1'b0;
assign brk2_pnd = 1'b0;
assign brk2_dout = 16'h0000;
`endif
`ifdef DBG_HWBRK_3
// Hardware Breakpoint/Watchpoint Register read select
wire [3:0] brk3_reg_rd = {reg_rd[BRK3_ADDR1],
reg_rd[BRK3_ADDR0],
reg_rd[BRK3_STAT],
reg_rd[BRK3_CTL]};
// Hardware Breakpoint/Watchpoint Register write select
wire [3:0] brk3_reg_wr = {reg_wr[BRK3_ADDR1],
reg_wr[BRK3_ADDR0],
reg_wr[BRK3_STAT],
reg_wr[BRK3_CTL]};
omsp_dbg_hwbrk dbg_hwbr_3 (
// OUTPUTs
.brk_halt (brk3_halt), // Hardware breakpoint command
.brk_pnd (brk3_pnd), // Hardware break/watch-point pending
.brk_dout (brk3_dout), // Hardware break/watch-point register data input
// INPUTs
.brk_reg_rd (brk3_reg_rd), // Hardware break/watch-point register read select
.brk_reg_wr (brk3_reg_wr), // Hardware break/watch-point register write select
.dbg_clk (dbg_clk), // Debug unit clock
.dbg_din (dbg_din), // Debug register data input
.dbg_rst (dbg_rst), // Debug unit reset
.decode_noirq (decode_noirq), // Frontend decode instruction
.eu_mab (eu_mab), // Execution-Unit Memory address bus
.eu_mb_en (eu_mb_en), // Execution-Unit Memory bus enable
.eu_mb_wr (eu_mb_wr), // Execution-Unit Memory bus write transfer
.pc (pc) // Program counter
);
`else
assign brk3_halt = 1'b0;
assign brk3_pnd = 1'b0;
assign brk3_dout = 16'h0000;
`endif
//============================================================================
// 6) DATA OUTPUT GENERATION
//============================================================================
wire [15:0] cpu_id_lo_rd = cpu_id[15:0] & {16{reg_rd[CPU_ID_LO]}};
wire [15:0] cpu_id_hi_rd = cpu_id[31:16] & {16{reg_rd[CPU_ID_HI]}};
wire [15:0] cpu_ctl_rd = {8'h00, cpu_ctl_full} & {16{reg_rd[CPU_CTL]}};
wire [15:0] cpu_stat_rd = {8'h00, cpu_stat_full} & {16{reg_rd[CPU_STAT]}};
wire [15:0] mem_ctl_rd = {8'h00, mem_ctl_full} & {16{reg_rd[MEM_CTL]}};
wire [15:0] mem_data_rd = mem_data & {16{reg_rd[MEM_DATA]}};
wire [15:0] mem_addr_rd = mem_addr & {16{reg_rd[MEM_ADDR]}};
wire [15:0] mem_cnt_rd = mem_cnt & {16{reg_rd[MEM_CNT]}};
wire [15:0] cpu_nr_rd = cpu_nr & {16{reg_rd[CPU_NR]}};
wire [15:0] dbg_dout = cpu_id_lo_rd |
cpu_id_hi_rd |
cpu_ctl_rd |
cpu_stat_rd |
mem_ctl_rd |
mem_data_rd |
mem_addr_rd |
mem_cnt_rd |
brk0_dout |
brk1_dout |
brk2_dout |
brk3_dout |
cpu_nr_rd;
// Tell UART/I2C interface that the data is ready to be read
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) dbg_rd_rdy <= 1'b0;
else if (mem_burst | mem_burst_rd) dbg_rd_rdy <= (dbg_reg_rd | dbg_mem_rd_dly);
else dbg_rd_rdy <= dbg_rd;
//============================================================================
// 7) CPU CONTROL
//============================================================================
// Reset CPU
//--------------------------
wire dbg_cpu_reset = cpu_ctl[`CPU_RST];
// Break after reset
//--------------------------
wire halt_rst = cpu_ctl[`RST_BRK_EN] & dbg_en_s & puc_pnd_set;
// Freeze peripherals
//--------------------------
wire dbg_freeze = dbg_halt_st & (cpu_ctl[`FRZ_BRK_EN] | ~cpu_en_s);
// Software break
//--------------------------
assign dbg_swbrk = (fe_mdb_in==`DBG_SWBRK_OP) & decode_noirq & cpu_ctl[`SW_BRK_EN];
// Single step
//--------------------------
reg [1:0] inc_step;
always @(posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) inc_step <= 2'b00;
else if (istep) inc_step <= 2'b11;
else inc_step <= {inc_step[0], 1'b0};
// Run / Halt
//--------------------------
reg halt_flag;
wire mem_halt_cpu;
wire mem_run_cpu;
wire halt_flag_clr = run_cpu | mem_run_cpu;
wire halt_flag_set = halt_cpu | halt_rst | dbg_swbrk | mem_halt_cpu |
brk0_halt | brk1_halt | brk2_halt | brk3_halt;
always @(posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) halt_flag <= 1'b0;
else if (halt_flag_clr) halt_flag <= 1'b0;
else if (halt_flag_set) halt_flag <= 1'b1;
wire dbg_halt_cmd = (halt_flag | halt_flag_set) & ~inc_step[1];
//============================================================================
// 8) MEMORY CONTROL
//============================================================================
// Control Memory bursts
//------------------------------
wire mem_burst_start = (mem_start & |mem_cnt);
wire mem_burst_end = ((dbg_wr | dbg_rd_rdy) & ~|mem_cnt);
// Detect when burst is on going
always @(posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) mem_burst <= 1'b0;
else if (mem_burst_start) mem_burst <= 1'b1;
else if (mem_burst_end) mem_burst <= 1'b0;
// Control signals for UART/I2C interface
assign mem_burst_rd = (mem_burst_start & ~mem_ctl[1]);
assign mem_burst_wr = (mem_burst_start & mem_ctl[1]);
// Trigger CPU Register or memory access during a burst
reg mem_startb;
always @(posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) mem_startb <= 1'b0;
else mem_startb <= (mem_burst & (dbg_wr | dbg_rd)) | mem_burst_rd;
// Combine single and burst memory start of sequence
wire mem_seq_start = ((mem_start & ~|mem_cnt) | mem_startb);
// Memory access state machine
//------------------------------
reg [1:0] mem_state;
reg [1:0] mem_state_nxt;
// State machine definition
parameter M_IDLE = 2'h0;
parameter M_SET_BRK = 2'h1;
parameter M_ACCESS_BRK = 2'h2;
parameter M_ACCESS = 2'h3;
// State transition
always @(mem_state or mem_seq_start or dbg_halt_st)
case (mem_state)
M_IDLE : mem_state_nxt = ~mem_seq_start ? M_IDLE :
dbg_halt_st ? M_ACCESS : M_SET_BRK;
M_SET_BRK : mem_state_nxt = dbg_halt_st ? M_ACCESS_BRK : M_SET_BRK;
M_ACCESS_BRK : mem_state_nxt = M_IDLE;
M_ACCESS : mem_state_nxt = M_IDLE;
// pragma coverage off
default : mem_state_nxt = M_IDLE;
// pragma coverage on
endcase
// State machine
always @(posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) mem_state <= M_IDLE;
else mem_state <= mem_state_nxt;
// Utility signals
assign mem_halt_cpu = (mem_state==M_IDLE) & (mem_state_nxt==M_SET_BRK);
assign mem_run_cpu = (mem_state==M_ACCESS_BRK) & (mem_state_nxt==M_IDLE);
assign mem_access = (mem_state==M_ACCESS) | (mem_state==M_ACCESS_BRK);
// Interface to CPU Registers and Memory bacbkone
//------------------------------------------------
assign dbg_mem_addr = mem_addr;
assign dbg_mem_dout = ~mem_bw ? mem_data :
mem_addr[0] ? {mem_data[7:0], 8'h00} :
{8'h00, mem_data[7:0]};
assign dbg_reg_wr = mem_access & mem_ctl[1] & mem_ctl[2];
assign dbg_reg_rd = mem_access & ~mem_ctl[1] & mem_ctl[2];
assign dbg_mem_en = mem_access & ~mem_ctl[2];
assign dbg_mem_rd = dbg_mem_en & ~mem_ctl[1];
wire [1:0] dbg_mem_wr_msk = ~mem_bw ? 2'b11 :
mem_addr[0] ? 2'b10 : 2'b01;
assign dbg_mem_wr = {2{dbg_mem_en & mem_ctl[1]}} & dbg_mem_wr_msk;
// It takes one additional cycle to read from Memory as from registers
always @(posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) dbg_mem_rd_dly <= 1'b0;
else dbg_mem_rd_dly <= dbg_mem_rd;
//=============================================================================
// 9) UART COMMUNICATION
//=============================================================================
`ifdef DBG_UART
omsp_dbg_uart dbg_uart_0 (
// OUTPUTs
.dbg_addr (dbg_addr), // Debug register address
.dbg_din (dbg_din), // Debug register data input
.dbg_rd (dbg_rd), // Debug register data read
.dbg_uart_txd (dbg_uart_txd), // Debug interface: UART TXD
.dbg_wr (dbg_wr), // Debug register data write
// INPUTs
.dbg_clk (dbg_clk), // Debug unit clock
.dbg_dout (dbg_dout), // Debug register data output
.dbg_rd_rdy (dbg_rd_rdy), // Debug register data is ready for read
.dbg_rst (dbg_rst), // Debug unit reset
.dbg_uart_rxd (dbg_uart_rxd), // Debug interface: UART RXD
.mem_burst (mem_burst), // Burst on going
.mem_burst_end (mem_burst_end), // End TX/RX burst
.mem_burst_rd (mem_burst_rd), // Start TX burst
.mem_burst_wr (mem_burst_wr), // Start RX burst
.mem_bw (mem_bw) // Burst byte width
);
`else
assign dbg_uart_txd = 1'b1;
`ifdef DBG_I2C
`else
assign dbg_addr = 6'h00;
assign dbg_din = 16'h0000;
assign dbg_rd = 1'b0;
assign dbg_wr = 1'b0;
`endif
`endif
//=============================================================================
// 10) I2C COMMUNICATION
//=============================================================================
`ifdef DBG_I2C
omsp_dbg_i2c dbg_i2c_0 (
// OUTPUTs
.dbg_addr (dbg_addr), // Debug register address
.dbg_din (dbg_din), // Debug register data input
.dbg_i2c_sda_out (dbg_i2c_sda_out), // Debug interface: I2C SDA OUT
.dbg_rd (dbg_rd), // Debug register data read
.dbg_wr (dbg_wr), // Debug register data write
// INPUTs
.dbg_clk (dbg_clk), // Debug unit clock
.dbg_dout (dbg_dout), // Debug register data output
.dbg_i2c_addr (dbg_i2c_addr), // Debug interface: I2C Address
.dbg_i2c_broadcast (dbg_i2c_broadcast), // Debug interface: I2C Broadcast Address (for multicore systems)
.dbg_i2c_scl (dbg_i2c_scl), // Debug interface: I2C SCL
.dbg_i2c_sda_in (dbg_i2c_sda_in), // Debug interface: I2C SDA IN
.dbg_rd_rdy (dbg_rd_rdy), // Debug register data is ready for read
.dbg_rst (dbg_rst), // Debug unit reset
.mem_burst (mem_burst), // Burst on going
.mem_burst_end (mem_burst_end), // End TX/RX burst
.mem_burst_rd (mem_burst_rd), // Start TX burst
.mem_burst_wr (mem_burst_wr), // Start RX burst
.mem_bw (mem_bw) // Burst byte width
);
`else
assign dbg_i2c_sda_out = 1'b1;
`endif
endmodule // omsp_dbg
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_undefines.v"
`endif
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: fifo_4kx16_dc.v
// Megafunction Name(s):
// dcfifo
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2006 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo_4kx16_dc (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdusedw,
wrfull,
wrusedw);
input aclr;
input [15:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [15:0] q;
output rdempty;
output [11:0] rdusedw;
output wrfull;
output [11:0] wrusedw;
wire sub_wire0;
wire [11:0] sub_wire1;
wire sub_wire2;
wire [15:0] sub_wire3;
wire [11:0] sub_wire4;
wire rdempty = sub_wire0;
wire [11:0] wrusedw = sub_wire1[11:0];
wire wrfull = sub_wire2;
wire [15:0] q = sub_wire3[15:0];
wire [11:0] rdusedw = sub_wire4[11:0];
dcfifo dcfifo_component (
.wrclk (wrclk),
.rdreq (rdreq),
.aclr (aclr),
.rdclk (rdclk),
.wrreq (wrreq),
.data (data),
.rdempty (sub_wire0),
.wrusedw (sub_wire1),
.wrfull (sub_wire2),
.q (sub_wire3),
.rdusedw (sub_wire4)
// synopsys translate_off
,
.wrempty (),
.rdfull ()
// synopsys translate_on
);
defparam
dcfifo_component.add_ram_output_register = "OFF",
dcfifo_component.clocks_are_synchronized = "FALSE",
dcfifo_component.intended_device_family = "Cyclone",
dcfifo_component.lpm_numwords = 4096,
dcfifo_component.lpm_showahead = "ON",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 16,
dcfifo_component.lpm_widthu = 12,
dcfifo_component.overflow_checking = "OFF",
dcfifo_component.underflow_checking = "OFF",
dcfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "4096"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "16"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE"
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//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
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// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
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//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: ddr_phy_oclkdelay_cal.v
// /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $
// \ \ / \ Date Created: Aug 03 2009
// \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose: Center write DQS in write DQ valid window using Phaser_Out Stage3
// delay
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v1_9_ddr_phy_oclkdelay_cal #
(
parameter TCQ = 100,
parameter tCK = 2500,
parameter nCK_PER_CLK = 4,
parameter DRAM_TYPE = "DDR3",
parameter DRAM_WIDTH = 8,
parameter DQS_CNT_WIDTH = 3,
parameter DQS_WIDTH = 8,
parameter DQ_WIDTH = 64,
parameter SIM_CAL_OPTION = "NONE",
parameter OCAL_EN = "ON"
)
(
input clk,
input rst,
// Start only after PO and PI FINE delay decremented
input oclk_init_delay_start,
input oclkdelay_calib_start,
input [5:0] oclkdelay_init_val,
// Detect write valid data edge during OCLKDELAY calib
input phy_rddata_en,
input [2*nCK_PER_CLK*DQ_WIDTH-1:0] rd_data,
// Precharge done status from ddr_phy_init
input prech_done,
// Write Level signals during OCLKDELAY calibration
input [6*DQS_WIDTH-1:0] wl_po_fine_cnt,
output reg wrlvl_final,
// Inc/dec Phaser_Out fine delay line
output reg po_stg3_incdec,
output reg po_en_stg3,
output reg po_stg23_sel,
output reg po_stg23_incdec,
output reg po_en_stg23,
// Completed initial delay increment
output oclk_init_delay_done,
output [DQS_CNT_WIDTH:0] oclkdelay_calib_cnt,
output reg oclk_prech_req,
output reg oclk_calib_resume,
output oclkdelay_calib_done,
output [255:0] dbg_phy_oclkdelay_cal,
output [16*DRAM_WIDTH-1:0] dbg_oclkdelay_rd_data
);
// Start with an initial delay of 0 on OCLKDELAY. This is required to
// detect two valid data edges when possible. Two edges cannot be
// detected if write DQ and DQS are exactly edge aligned at stage3 tap0.
localparam TAP_CNT = 0;
//(tCK <= 938) ? 13 :
//(tCK <= 1072) ? 14 :
//(tCK <= 1250) ? 15 :
//(tCK <= 1500) ? 16 : 17;
localparam WAIT_CNT = 15;
// Default set to TRUE because there can be a case where the ocal_rise_right_edge
// may not be detected if WRLVL stage2 tap value is large upto 63 and the initial
// DQS position is more than 225 degrees
localparam MINUS_32 = "TRUE";
localparam [4:0] OCAL_IDLE = 5'h00;
localparam [4:0] OCAL_NEW_DQS_WAIT = 5'h01;
localparam [4:0] OCAL_STG3_SEL = 5'h02;
localparam [4:0] OCAL_STG3_SEL_WAIT = 5'h03;
localparam [4:0] OCAL_STG3_EN_WAIT = 5'h04;
localparam [4:0] OCAL_STG3_DEC = 5'h05;
localparam [4:0] OCAL_STG3_WAIT = 5'h06;
localparam [4:0] OCAL_STG3_CALC = 5'h07;
localparam [4:0] OCAL_STG3_INC = 5'h08;
localparam [4:0] OCAL_STG3_INC_WAIT = 5'h09;
localparam [4:0] OCAL_STG2_SEL = 5'h0A;
localparam [4:0] OCAL_STG2_WAIT = 5'h0B;
localparam [4:0] OCAL_STG2_INC = 5'h0C;
localparam [4:0] OCAL_STG2_DEC = 5'h0D;
localparam [4:0] OCAL_STG2_DEC_WAIT = 5'h0E;
localparam [4:0] OCAL_NEXT_DQS = 5'h0F;
localparam [4:0] OCAL_NEW_DQS_READ = 5'h10;
localparam [4:0] OCAL_INC_DONE_WAIT = 5'h11;
localparam [4:0] OCAL_STG3_DEC_WAIT = 5'h12;
localparam [4:0] OCAL_DEC_DONE_WAIT = 5'h13;
localparam [4:0] OCAL_DONE = 5'h14;
integer i;
reg oclk_init_delay_start_r;
reg [3:0] count;
reg delay_done;
reg delay_done_r1;
reg delay_done_r2;
reg delay_done_r3;
reg delay_done_r4;
reg [5:0] delay_cnt_r;
reg po_stg3_dec;
wire [DQ_WIDTH-1:0] rd_data_rise0;
wire [DQ_WIDTH-1:0] rd_data_fall0;
wire [DQ_WIDTH-1:0] rd_data_rise1;
wire [DQ_WIDTH-1:0] rd_data_fall1;
wire [DQ_WIDTH-1:0] rd_data_rise2;
wire [DQ_WIDTH-1:0] rd_data_fall2;
wire [DQ_WIDTH-1:0] rd_data_rise3;
wire [DQ_WIDTH-1:0] rd_data_fall3;
reg [DQS_CNT_WIDTH:0] cnt_dqs_r;
reg [DQS_CNT_WIDTH:0] mux_sel_r;
reg [DRAM_WIDTH-1:0] sel_rd_rise0_r;
reg [DRAM_WIDTH-1:0] sel_rd_fall0_r;
reg [DRAM_WIDTH-1:0] sel_rd_rise1_r;
reg [DRAM_WIDTH-1:0] sel_rd_fall1_r;
reg [DRAM_WIDTH-1:0] sel_rd_rise2_r;
reg [DRAM_WIDTH-1:0] sel_rd_fall2_r;
reg [DRAM_WIDTH-1:0] sel_rd_rise3_r;
reg [DRAM_WIDTH-1:0] sel_rd_fall3_r;
reg [DRAM_WIDTH-1:0] prev_rd_rise0_r;
reg [DRAM_WIDTH-1:0] prev_rd_fall0_r;
reg [DRAM_WIDTH-1:0] prev_rd_rise1_r;
reg [DRAM_WIDTH-1:0] prev_rd_fall1_r;
reg [DRAM_WIDTH-1:0] prev_rd_rise2_r;
reg [DRAM_WIDTH-1:0] prev_rd_fall2_r;
reg [DRAM_WIDTH-1:0] prev_rd_rise3_r;
reg [DRAM_WIDTH-1:0] prev_rd_fall3_r;
reg rd_active_r;
reg rd_active_r1;
reg rd_active_r2;
reg rd_active_r3;
reg rd_active_r4;
reg [DRAM_WIDTH-1:0] pat_match_fall0_r;
reg pat_match_fall0_and_r;
reg [DRAM_WIDTH-1:0] pat_match_fall1_r;
reg pat_match_fall1_and_r;
reg [DRAM_WIDTH-1:0] pat_match_fall2_r;
reg pat_match_fall2_and_r;
reg [DRAM_WIDTH-1:0] pat_match_fall3_r;
reg pat_match_fall3_and_r;
reg [DRAM_WIDTH-1:0] pat_match_rise0_r;
reg pat_match_rise0_and_r;
reg [DRAM_WIDTH-1:0] pat_match_rise1_r;
reg pat_match_rise1_and_r;
reg [DRAM_WIDTH-1:0] pat_match_rise2_r;
reg pat_match_rise2_and_r;
reg [DRAM_WIDTH-1:0] pat_match_rise3_r;
reg pat_match_rise3_and_r;
reg pat_data_match_r;
reg pat_data_match_valid_r;
reg pat_data_match_valid_r1;
//reg [3:0] stable_stg3_cnt;
//reg stable_eye_r;
reg [3:0] stable_rise_stg3_cnt;
reg stable_rise_eye_r;
reg [3:0] stable_fall_stg3_cnt;
reg stable_fall_eye_r;
reg wait_cnt_en_r;
reg [3:0] wait_cnt_r;
reg cnt_next_state;
reg oclkdelay_calib_start_r;
reg [5:0] stg3_tap_cnt;
reg [5:0] stg3_incdec_limit;
reg stg3_dec2inc;
reg [5:0] stg2_tap_cnt;
reg [1:0] stg2_inc2_cnt;
reg [1:0] stg2_dec2_cnt;
reg [5:0] stg2_dec_cnt;
reg stg3_dec;
reg stg3_dec_r;
reg [4:0] ocal_state_r;
reg [4:0] ocal_state_r1;
reg [5:0] ocal_final_cnt_r;
reg ocal_final_cnt_r_calc;
reg [5:0] ocal_inc_cnt;
reg [5:0] ocal_dec_cnt;
reg ocal_stg3_inc_en;
reg ocal_rise_edge1_found;
reg ocal_rise_edge2_found;
reg ocal_rise_edge1_found_timing;
reg ocal_rise_edge2_found_timing;
reg [5:0] ocal_rise_edge1_taps;
reg [5:0] ocal_rise_edge2_taps;
reg [5:0] ocal_rise_right_edge;
reg ocal_fall_edge1_found;
reg ocal_fall_edge2_found;
reg [5:0] ocal_fall_edge1_taps;
reg [5:0] ocal_fall_edge2_taps;
reg [5:0] ocal_final_cnt_r_mux_a;
reg [5:0] ocal_final_cnt_r_mux_b;
reg [5:0] ocal_final_cnt_r_mux_c;
reg [5:0] ocal_final_cnt_r_mux_d;
reg ocal_byte_done;
reg ocal_wrlvl_done;
reg ocal_wrlvl_done_r;
(* keep = "true", max_fanout = 10 *) reg ocal_done_r /* synthesis syn_maxfan = 10 */;
reg [5:0] ocal_tap_cnt_r[0:DQS_WIDTH-1];
reg prech_done_r;
reg rise_win;
reg fall_win;
// timing registers
reg stg3_tap_cnt_eq_oclkdelay_init_val;
reg stg3_tap_cnt_eq_0;
//reg stg3_tap_cnt_gt_20;
reg stg3_tap_cnt_eq_63;
reg stg3_tap_cnt_less_oclkdelay_init_val;
reg stg3_limit;
wire [5:0] wl_po_fine_cnt_w[0:DQS_WIDTH-1];
//**************************************************************************
// Debug signals
//**************************************************************************
genvar dqs_i;
generate
for (dqs_i=0; dqs_i < DQS_WIDTH; dqs_i = dqs_i + 1) begin: oclkdelay_tap_cnt
assign dbg_phy_oclkdelay_cal[6*dqs_i+:6] = ocal_tap_cnt_r[dqs_i][5:0];
end
endgenerate
assign dbg_phy_oclkdelay_cal[57:54] = cnt_dqs_r;
assign dbg_phy_oclkdelay_cal[58] = ocal_rise_edge1_found_timing;
assign dbg_phy_oclkdelay_cal[59] = ocal_rise_edge2_found_timing;
assign dbg_phy_oclkdelay_cal[65:60] = ocal_rise_edge1_taps;
assign dbg_phy_oclkdelay_cal[71:66] = ocal_rise_edge2_taps;
assign dbg_phy_oclkdelay_cal[76:72] = ocal_state_r1;
assign dbg_phy_oclkdelay_cal[77] = pat_data_match_valid_r;
assign dbg_phy_oclkdelay_cal[78] = pat_data_match_r;
assign dbg_phy_oclkdelay_cal[84:79] = stg3_tap_cnt;
assign dbg_phy_oclkdelay_cal[88:85] = stable_rise_stg3_cnt;
assign dbg_phy_oclkdelay_cal[89] = stable_rise_eye_r;
assign dbg_phy_oclkdelay_cal[97:90] = prev_rd_rise0_r;
assign dbg_phy_oclkdelay_cal[105:98] = prev_rd_fall0_r;
assign dbg_phy_oclkdelay_cal[113:106] = prev_rd_rise1_r;
assign dbg_phy_oclkdelay_cal[121:114] = prev_rd_fall1_r;
assign dbg_phy_oclkdelay_cal[129:122] = prev_rd_rise2_r;
assign dbg_phy_oclkdelay_cal[137:130] = prev_rd_fall2_r;
assign dbg_phy_oclkdelay_cal[145:138] = prev_rd_rise3_r;
assign dbg_phy_oclkdelay_cal[153:146] = prev_rd_fall3_r;
assign dbg_phy_oclkdelay_cal[154] = rd_active_r;
assign dbg_phy_oclkdelay_cal[162:155] = sel_rd_rise0_r;
assign dbg_phy_oclkdelay_cal[170:163] = sel_rd_fall0_r;
assign dbg_phy_oclkdelay_cal[178:171] = sel_rd_rise1_r;
assign dbg_phy_oclkdelay_cal[186:179] = sel_rd_fall1_r;
assign dbg_phy_oclkdelay_cal[194:187] = sel_rd_rise2_r;
assign dbg_phy_oclkdelay_cal[202:195] = sel_rd_fall2_r;
assign dbg_phy_oclkdelay_cal[210:203] = sel_rd_rise3_r;
assign dbg_phy_oclkdelay_cal[218:211] = sel_rd_fall3_r;
assign dbg_phy_oclkdelay_cal[219+:6] = stg2_tap_cnt;
assign dbg_phy_oclkdelay_cal[225] = ocal_fall_edge1_found;
assign dbg_phy_oclkdelay_cal[226] = ocal_fall_edge2_found;
assign dbg_phy_oclkdelay_cal[232:227] = ocal_fall_edge1_taps;
assign dbg_phy_oclkdelay_cal[238:233] = ocal_fall_edge2_taps;
assign dbg_phy_oclkdelay_cal[244:239] = ocal_rise_right_edge;
assign dbg_phy_oclkdelay_cal[250:245] = 'd0;
assign dbg_phy_oclkdelay_cal[251] = stable_fall_eye_r;
assign dbg_phy_oclkdelay_cal[252] = rise_win;
assign dbg_phy_oclkdelay_cal[253] = fall_win;
assign dbg_oclkdelay_rd_data[DRAM_WIDTH*1 -1:0] = prev_rd_rise0_r;
assign dbg_oclkdelay_rd_data[DRAM_WIDTH*2 -1:DRAM_WIDTH*1] = prev_rd_fall0_r;
assign dbg_oclkdelay_rd_data[DRAM_WIDTH*3 -1:DRAM_WIDTH*2] = prev_rd_rise1_r;
assign dbg_oclkdelay_rd_data[DRAM_WIDTH*4 -1:DRAM_WIDTH*3] = prev_rd_fall1_r;
assign dbg_oclkdelay_rd_data[DRAM_WIDTH*5 -1:DRAM_WIDTH*4] = prev_rd_rise2_r;
assign dbg_oclkdelay_rd_data[DRAM_WIDTH*6 -1:DRAM_WIDTH*5] = prev_rd_fall2_r;
assign dbg_oclkdelay_rd_data[DRAM_WIDTH*7 -1:DRAM_WIDTH*6] = prev_rd_rise3_r;
assign dbg_oclkdelay_rd_data[DRAM_WIDTH*8 -1:DRAM_WIDTH*7] = prev_rd_fall3_r;
assign dbg_oclkdelay_rd_data[DRAM_WIDTH*9 -1:DRAM_WIDTH*8] = sel_rd_rise0_r;
assign dbg_oclkdelay_rd_data[DRAM_WIDTH*10 -1:DRAM_WIDTH*9] = sel_rd_fall0_r;
assign dbg_oclkdelay_rd_data[DRAM_WIDTH*11 -1:DRAM_WIDTH*10] = sel_rd_rise1_r;
assign dbg_oclkdelay_rd_data[DRAM_WIDTH*12 -1:DRAM_WIDTH*11] = sel_rd_fall1_r;
assign dbg_oclkdelay_rd_data[DRAM_WIDTH*13 -1:DRAM_WIDTH*12] = sel_rd_rise2_r;
assign dbg_oclkdelay_rd_data[DRAM_WIDTH*14 -1:DRAM_WIDTH*13] = sel_rd_fall2_r;
assign dbg_oclkdelay_rd_data[DRAM_WIDTH*15 -1:DRAM_WIDTH*14] = sel_rd_rise3_r;
assign dbg_oclkdelay_rd_data[DRAM_WIDTH*16 -1:DRAM_WIDTH*15] = sel_rd_fall3_r;
assign oclk_init_delay_done = ((SIM_CAL_OPTION == "FAST_CAL") || (DRAM_TYPE!="DDR3")) ? 1'b1 : delay_done_r4; //(SIM_CAL_OPTION != "NONE")
assign oclkdelay_calib_cnt = cnt_dqs_r;
assign oclkdelay_calib_done = (OCAL_EN == "ON") ? ocal_done_r : 1'b1;
always @(posedge clk)
oclk_init_delay_start_r <= #TCQ oclk_init_delay_start;
always @(posedge clk) begin
if (rst || po_stg3_dec)
count <= #TCQ WAIT_CNT;
else if (oclk_init_delay_start && (count > 'd0))
count <= #TCQ count - 1;
end
always @(posedge clk) begin
if (rst)
po_stg3_dec <= #TCQ 1'b0;
else if ((count == 'd1) && (delay_cnt_r != 'd0))
po_stg3_dec <= #TCQ 1'b1;
else
po_stg3_dec <= #TCQ 1'b0;
end
//po_stg3_incdec and po_en_stg3 asserted for all data byte lanes
always @(posedge clk) begin
if (rst) begin
po_stg3_incdec <= #TCQ 1'b0;
po_en_stg3 <= #TCQ 1'b0;
end else if (po_stg3_dec) begin
po_stg3_incdec <= #TCQ 1'b0;
po_en_stg3 <= #TCQ 1'b1;
end else begin
po_stg3_incdec <= #TCQ 1'b0;
po_en_stg3 <= #TCQ 1'b0;
end
end
// delay counter to count TAP_CNT cycles
always @(posedge clk) begin
// load delay counter with init value of TAP_CNT
if (rst)
delay_cnt_r <= #TCQ TAP_CNT;
else if (po_stg3_dec && (delay_cnt_r > 6'd0))
delay_cnt_r <= #TCQ delay_cnt_r - 1;
end
// when all the ctl_lanes have their output phase shifted by 1/4 cycle, delay shifting is done.
always @(posedge clk) begin
if (rst) begin
delay_done <= #TCQ 1'b0;
end else if ((TAP_CNT == 6'd0) || ((delay_cnt_r == 6'd1) &&
(count == 'd1))) begin
delay_done <= #TCQ 1'b1;
end
end
always @(posedge clk) begin
delay_done_r1 <= #TCQ delay_done;
delay_done_r2 <= #TCQ delay_done_r1;
delay_done_r3 <= #TCQ delay_done_r2;
delay_done_r4 <= #TCQ delay_done_r3;
end
//**************************************************************************
// OCLKDELAY Calibration
//**************************************************************************
generate
if (nCK_PER_CLK == 4) begin: gen_rd_data_div4
assign rd_data_rise0 = rd_data[DQ_WIDTH-1:0];
assign rd_data_fall0 = rd_data[2*DQ_WIDTH-1:DQ_WIDTH];
assign rd_data_rise1 = rd_data[3*DQ_WIDTH-1:2*DQ_WIDTH];
assign rd_data_fall1 = rd_data[4*DQ_WIDTH-1:3*DQ_WIDTH];
assign rd_data_rise2 = rd_data[5*DQ_WIDTH-1:4*DQ_WIDTH];
assign rd_data_fall2 = rd_data[6*DQ_WIDTH-1:5*DQ_WIDTH];
assign rd_data_rise3 = rd_data[7*DQ_WIDTH-1:6*DQ_WIDTH];
assign rd_data_fall3 = rd_data[8*DQ_WIDTH-1:7*DQ_WIDTH];
end else if (nCK_PER_CLK == 2) begin: gen_rd_data_div2
assign rd_data_rise0 = rd_data[DQ_WIDTH-1:0];
assign rd_data_fall0 = rd_data[2*DQ_WIDTH-1:DQ_WIDTH];
assign rd_data_rise1 = rd_data[3*DQ_WIDTH-1:2*DQ_WIDTH];
assign rd_data_fall1 = rd_data[4*DQ_WIDTH-1:3*DQ_WIDTH];
end
endgenerate
always @(posedge clk) begin
mux_sel_r <= #TCQ cnt_dqs_r;
oclkdelay_calib_start_r <= #TCQ oclkdelay_calib_start;
ocal_wrlvl_done_r <= #TCQ ocal_wrlvl_done;
rd_active_r <= #TCQ phy_rddata_en;
rd_active_r1 <= #TCQ rd_active_r;
rd_active_r2 <= #TCQ rd_active_r1;
rd_active_r3 <= #TCQ rd_active_r2;
rd_active_r4 <= #TCQ rd_active_r3;
stg3_dec_r <= #TCQ stg3_dec;
ocal_state_r1 <= #TCQ ocal_state_r;
end
// Register outputs for improved timing.
// All bits in selected DQS group are checked in aggregate
generate
genvar mux_j;
for (mux_j = 0; mux_j < DRAM_WIDTH; mux_j = mux_j + 1) begin: gen_mux_rd
always @(posedge clk) begin
if (phy_rddata_en) begin
sel_rd_rise0_r[mux_j] <= #TCQ rd_data_rise0[DRAM_WIDTH*mux_sel_r + mux_j];
sel_rd_fall0_r[mux_j] <= #TCQ rd_data_fall0[DRAM_WIDTH*mux_sel_r + mux_j];
sel_rd_rise1_r[mux_j] <= #TCQ rd_data_rise1[DRAM_WIDTH*mux_sel_r + mux_j];
sel_rd_fall1_r[mux_j] <= #TCQ rd_data_fall1[DRAM_WIDTH*mux_sel_r + mux_j];
sel_rd_rise2_r[mux_j] <= #TCQ rd_data_rise2[DRAM_WIDTH*mux_sel_r + mux_j];
sel_rd_fall2_r[mux_j] <= #TCQ rd_data_fall2[DRAM_WIDTH*mux_sel_r + mux_j];
sel_rd_rise3_r[mux_j] <= #TCQ rd_data_rise3[DRAM_WIDTH*mux_sel_r + mux_j];
sel_rd_fall3_r[mux_j] <= #TCQ rd_data_fall3[DRAM_WIDTH*mux_sel_r + mux_j];
end
end
end
endgenerate
always @(posedge clk)
if (((stg3_tap_cnt_eq_oclkdelay_init_val) && rd_active_r) |
rd_active_r4) begin
prev_rd_rise0_r <= #TCQ sel_rd_rise0_r;
prev_rd_fall0_r <= #TCQ sel_rd_fall0_r;
prev_rd_rise1_r <= #TCQ sel_rd_rise1_r;
prev_rd_fall1_r <= #TCQ sel_rd_fall1_r;
prev_rd_rise2_r <= #TCQ sel_rd_rise2_r;
prev_rd_fall2_r <= #TCQ sel_rd_fall2_r;
prev_rd_rise3_r <= #TCQ sel_rd_rise3_r;
prev_rd_fall3_r <= #TCQ sel_rd_fall3_r;
end
// Each bit of each byte is compared with previous data to
// detect an edge
generate
genvar pt_j;
if (nCK_PER_CLK == 4) begin: gen_pat_match_div4
always @(posedge clk) begin
if (rd_active_r) begin
rise_win <= #TCQ ((|sel_rd_rise0_r) | (|sel_rd_rise1_r) | (|sel_rd_rise2_r) | (|sel_rd_rise3_r));
fall_win <= #TCQ ((&sel_rd_rise0_r) & (&sel_rd_rise1_r) & (&sel_rd_rise2_r) & (&sel_rd_rise3_r));
end
end
for (pt_j = 0; pt_j < DRAM_WIDTH; pt_j = pt_j + 1) begin: gen_pat_match
always @(posedge clk) begin
if (sel_rd_rise0_r[pt_j] == prev_rd_rise0_r[pt_j])
pat_match_rise0_r[pt_j] <= #TCQ 1'b1;
else
pat_match_rise0_r[pt_j] <= #TCQ 1'b0;
if (sel_rd_fall0_r[pt_j] == prev_rd_fall0_r[pt_j])
pat_match_fall0_r[pt_j] <= #TCQ 1'b1;
else
pat_match_fall0_r[pt_j] <= #TCQ 1'b0;
if (sel_rd_rise1_r[pt_j] == prev_rd_rise1_r[pt_j])
pat_match_rise1_r[pt_j] <= #TCQ 1'b1;
else
pat_match_rise1_r[pt_j] <= #TCQ 1'b0;
if (sel_rd_fall1_r[pt_j] == prev_rd_fall1_r[pt_j])
pat_match_fall1_r[pt_j] <= #TCQ 1'b1;
else
pat_match_fall1_r[pt_j] <= #TCQ 1'b0;
if (sel_rd_rise2_r[pt_j] == prev_rd_rise2_r[pt_j])
pat_match_rise2_r[pt_j] <= #TCQ 1'b1;
else
pat_match_rise2_r[pt_j] <= #TCQ 1'b0;
if (sel_rd_fall2_r[pt_j] == prev_rd_fall2_r[pt_j])
pat_match_fall2_r[pt_j] <= #TCQ 1'b1;
else
pat_match_fall2_r[pt_j] <= #TCQ 1'b0;
if (sel_rd_rise3_r[pt_j] == prev_rd_rise3_r[pt_j])
pat_match_rise3_r[pt_j] <= #TCQ 1'b1;
else
pat_match_rise3_r[pt_j] <= #TCQ 1'b0;
if (sel_rd_fall3_r[pt_j] == prev_rd_fall3_r[pt_j])
pat_match_fall3_r[pt_j] <= #TCQ 1'b1;
else
pat_match_fall3_r[pt_j] <= #TCQ 1'b0;
end
end
always @(posedge clk) begin
pat_match_rise0_and_r <= #TCQ &pat_match_rise0_r;
pat_match_fall0_and_r <= #TCQ &pat_match_fall0_r;
pat_match_rise1_and_r <= #TCQ &pat_match_rise1_r;
pat_match_fall1_and_r <= #TCQ &pat_match_fall1_r;
pat_match_rise2_and_r <= #TCQ &pat_match_rise2_r;
pat_match_fall2_and_r <= #TCQ &pat_match_fall2_r;
pat_match_rise3_and_r <= #TCQ &pat_match_rise3_r;
pat_match_fall3_and_r <= #TCQ &pat_match_fall3_r;
pat_data_match_r <= #TCQ (//pat_match_rise0_and_r &&
//pat_match_fall0_and_r &&
pat_match_rise1_and_r &&
pat_match_fall1_and_r &&
pat_match_rise2_and_r &&
pat_match_fall2_and_r &&
pat_match_rise3_and_r &&
pat_match_fall3_and_r);
pat_data_match_valid_r <= #TCQ rd_active_r2;
end
always @(posedge clk)
pat_data_match_valid_r1 <= #TCQ pat_data_match_valid_r;
end else if (nCK_PER_CLK == 2) begin: gen_pat_match_div2
always @(posedge clk) begin
if (rd_active_r) begin
rise_win <= #TCQ ((|sel_rd_rise0_r) | (|sel_rd_rise1_r));
fall_win <= #TCQ ((&sel_rd_rise0_r) & (&sel_rd_rise1_r));
end
end
for (pt_j = 0; pt_j < DRAM_WIDTH; pt_j = pt_j + 1) begin: gen_pat_match
always @(posedge clk) begin
if (sel_rd_rise0_r[pt_j] == prev_rd_rise0_r[pt_j])
pat_match_rise0_r[pt_j] <= #TCQ 1'b1;
else
pat_match_rise0_r[pt_j] <= #TCQ 1'b0;
if (sel_rd_fall0_r[pt_j] == prev_rd_fall0_r[pt_j])
pat_match_fall0_r[pt_j] <= #TCQ 1'b1;
else
pat_match_fall0_r[pt_j] <= #TCQ 1'b0;
if (sel_rd_rise1_r[pt_j] == prev_rd_rise1_r[pt_j])
pat_match_rise1_r[pt_j] <= #TCQ 1'b1;
else
pat_match_rise1_r[pt_j] <= #TCQ 1'b0;
if (sel_rd_fall1_r[pt_j] == prev_rd_fall1_r[pt_j])
pat_match_fall1_r[pt_j] <= #TCQ 1'b1;
else
pat_match_fall1_r[pt_j] <= #TCQ 1'b0;
end
end
always @(posedge clk) begin
pat_match_rise0_and_r <= #TCQ &pat_match_rise0_r;
pat_match_fall0_and_r <= #TCQ &pat_match_fall0_r;
pat_match_rise1_and_r <= #TCQ &pat_match_rise1_r;
pat_match_fall1_and_r <= #TCQ &pat_match_fall1_r;
pat_data_match_r <= #TCQ (//pat_match_rise0_and_r &&
//pat_match_fall0_and_r &&
pat_match_rise1_and_r &&
pat_match_fall1_and_r);
pat_data_match_valid_r <= #TCQ rd_active_r2;
end
always @(posedge clk)
pat_data_match_valid_r1 <= #TCQ pat_data_match_valid_r;
end
endgenerate
// Stable count of 16 PO Stage3 taps at 2x the resolution of stage2 taps
// Required to inhibit false edge detection due to clock jitter
always @(posedge clk)begin
if (rst | (pat_data_match_valid_r & ~pat_data_match_r &
(ocal_state_r == OCAL_NEW_DQS_WAIT)) |
(ocal_state_r == OCAL_STG3_CALC))
stable_rise_stg3_cnt <= #TCQ 'd0;
else if ((!stg3_tap_cnt_eq_oclkdelay_init_val) &
pat_data_match_valid_r & pat_data_match_r &
(ocal_state_r == OCAL_NEW_DQS_WAIT) &
(stable_rise_stg3_cnt < 'd8) & ~rise_win)
stable_rise_stg3_cnt <= #TCQ stable_rise_stg3_cnt + 1;
end
always @(posedge clk) begin
if (rst | (stable_rise_stg3_cnt != 'd8))
stable_rise_eye_r <= #TCQ 1'b0;
else if (stable_rise_stg3_cnt == 'd8)
stable_rise_eye_r <= #TCQ 1'b1;
end
always @(posedge clk)begin
if (rst | (pat_data_match_valid_r & ~pat_data_match_r &
(ocal_state_r == OCAL_NEW_DQS_WAIT)) |
(ocal_state_r == OCAL_STG3_CALC))
stable_fall_stg3_cnt <= #TCQ 'd0;
else if ((!stg3_tap_cnt_eq_oclkdelay_init_val) &
pat_data_match_valid_r & pat_data_match_r &
(ocal_state_r == OCAL_NEW_DQS_WAIT) &
(stable_fall_stg3_cnt < 'd8) & fall_win)
stable_fall_stg3_cnt <= #TCQ stable_fall_stg3_cnt + 1;
end
always @(posedge clk) begin
if (rst | (stable_fall_stg3_cnt != 'd8))
stable_fall_eye_r <= #TCQ 1'b0;
else if (stable_fall_stg3_cnt == 'd8)
stable_fall_eye_r <= #TCQ 1'b1;
end
always @(posedge clk)
if ((ocal_state_r == OCAL_STG3_SEL_WAIT) ||
(ocal_state_r == OCAL_STG3_EN_WAIT) ||
(ocal_state_r == OCAL_STG3_WAIT) ||
(ocal_state_r == OCAL_STG3_INC_WAIT) ||
(ocal_state_r == OCAL_STG3_DEC_WAIT) ||
(ocal_state_r == OCAL_STG2_WAIT) ||
(ocal_state_r == OCAL_STG2_DEC_WAIT) ||
(ocal_state_r == OCAL_INC_DONE_WAIT) ||
(ocal_state_r == OCAL_DEC_DONE_WAIT))
wait_cnt_en_r <= #TCQ 1'b1;
else
wait_cnt_en_r <= #TCQ 1'b0;
always @(posedge clk)
if (!wait_cnt_en_r) begin
wait_cnt_r <= #TCQ 'b0;
cnt_next_state <= #TCQ 1'b0;
end else begin
if (wait_cnt_r != WAIT_CNT - 1) begin
wait_cnt_r <= #TCQ wait_cnt_r + 1;
cnt_next_state <= #TCQ 1'b0;
end else begin
// Need to reset to 0 to handle the case when there are two
// different WAIT states back-to-back
wait_cnt_r <= #TCQ 'b0;
cnt_next_state <= #TCQ 1'b1;
end
end
always @(posedge clk) begin
if (rst) begin
for (i=0; i < DQS_WIDTH; i = i + 1) begin: rst_ocal_tap_cnt
ocal_tap_cnt_r[i] <= #TCQ 'b0;
end
end else if (stg3_dec_r && ~stg3_dec)
ocal_tap_cnt_r[cnt_dqs_r][5:0] <= #TCQ stg3_tap_cnt;
end
always @(posedge clk) begin
if (rst || (ocal_state_r == OCAL_NEW_DQS_READ) ||
(ocal_state_r == OCAL_STG3_CALC) ||
(ocal_state_r == OCAL_DONE))
prech_done_r <= #TCQ 1'b0;
else if (prech_done)
prech_done_r <= #TCQ 1'b1;
end
// setting stg3_tap_cnt == oclkdelay_int_val
always @(posedge clk) begin
if (rst || (ocal_state_r == OCAL_NEXT_DQS)) begin
stg3_tap_cnt_eq_oclkdelay_init_val <= #TCQ 1'b1;
end else begin
if (ocal_state_r == OCAL_DONE)
stg3_tap_cnt_eq_oclkdelay_init_val <= #TCQ 1'b0;
else if (ocal_state_r == OCAL_STG3_DEC)
stg3_tap_cnt_eq_oclkdelay_init_val <= #TCQ (stg3_tap_cnt == oclkdelay_init_val+1);
else if (ocal_state_r == OCAL_STG3_INC)
stg3_tap_cnt_eq_oclkdelay_init_val <= #TCQ (stg3_tap_cnt == oclkdelay_init_val-1);
end // else: !if((rst || (ocal_state_r == OCAL_IDLE)) begin...
end // always @ (posedge clk)
// setting sg3_tap_cng > 20
// always @(posedge clk) begin
// if ((rst)|| (ocal_state_r == OCAL_NEXT_DQS)) begin
// stg3_tap_cnt_gt_20 <= #TCQ 1'b0;
// end else begin // if (rst)
// if (ocal_state_r == OCAL_STG3_DEC)
// stg3_tap_cnt_gt_20 <= #TCQ (stg3_tap_cnt >= 'd22);
// else if (ocal_state_r == OCAL_STG3_INC)
// stg3_tap_cnt_gt_20 <= #TCQ (stg3_tap_cnt >= 'd20);
// end // else: !if((rst || (ocal_state_r == OCAL_IDLE)) begin...
// end // always @ (posedge clk)
// setting sg3_tap_cnt == 0
always @(posedge clk) begin
if ((rst)|| (ocal_state_r == OCAL_NEXT_DQS) || (ocal_state_r == OCAL_STG3_INC) ) begin
stg3_tap_cnt_eq_0 <= #TCQ 1'b0;
end else begin // if (rst)
if (ocal_state_r == OCAL_STG3_DEC)
stg3_tap_cnt_eq_0 <= #TCQ (stg3_tap_cnt == 'd1);
end // else: !if((rst || (ocal_state_r == OCAL_IDLE)) begin...
end // always @ (posedge clk)
// setting sg3_tap_cnt == 63
always @(posedge clk) begin
if ((rst)|| (ocal_state_r == OCAL_NEXT_DQS)) begin
stg3_tap_cnt_eq_63 <= #TCQ 1'b0;
end else begin // if (rst)
if (ocal_state_r == OCAL_STG3_INC)
stg3_tap_cnt_eq_63 <= #TCQ (stg3_tap_cnt >= 'd62);
else if (ocal_state_r == OCAL_STG3_DEC)
stg3_tap_cnt_eq_63 <= #TCQ 1'b0;
end // else: !if((rst || (ocal_state_r == OCAL_IDLE)) begin...
end // always @ (posedge clk)
// setting sg3_tap_cnt < ocaldelay_init_val
always @(posedge clk) begin
if ((rst)|| (ocal_state_r == OCAL_NEXT_DQS)) begin
stg3_tap_cnt_less_oclkdelay_init_val <= #TCQ 1'b0;
end else begin // if (rst)
if (ocal_state_r == OCAL_STG3_DEC)
stg3_tap_cnt_less_oclkdelay_init_val <= #TCQ (stg3_tap_cnt <= oclkdelay_init_val);
else if (ocal_state_r == OCAL_STG3_INC)
stg3_tap_cnt_less_oclkdelay_init_val <= #TCQ (stg3_tap_cnt <= oclkdelay_init_val-2);
end // else: !if((rst || (ocal_state_r == OCAL_IDLE)) begin...
end // always @ (posedge clk)
// setting stg3_incdec_limit == 15
always @(posedge clk) begin
if (rst || (ocal_state_r == OCAL_NEXT_DQS) || (ocal_state_r == OCAL_DONE)) begin
stg3_limit <= #TCQ 1'b0;
end else if ((ocal_state_r == OCAL_STG3_WAIT) || (ocal_state_r == OCAL_STG2_WAIT)) begin
stg3_limit <= #TCQ (stg3_incdec_limit == 'd14);
end
end
// Registers feeding into the ocal_final_cnt_r computation
// Equation is in the form of ((A-B)/2) + C + D where the values taken are
// A = ocal_fall_edge_taps, ocal_rise_right_edge, stg3_tap_cnt or ocal_fall_edge2_taps
// B = ocal_fall_edge1_taps, ocal_rise_edge1_taps or '0'
// C = (stg3_tap_cnt - ocal_rise_right_edge), '0' or '1'
// D = '32' or '0'
always @(posedge clk) begin
if (rst || (ocal_state_r == OCAL_NEXT_DQS) || (ocal_state_r == OCAL_DONE))
ocal_final_cnt_r_mux_a <= #TCQ 'd0;
else if (|ocal_rise_right_edge) begin
if (ocal_fall_edge2_found && ocal_fall_edge1_found)
ocal_final_cnt_r_mux_a <= #TCQ ocal_fall_edge2_taps;
else
ocal_final_cnt_r_mux_a <= #TCQ ocal_rise_right_edge;
end else if (ocal_rise_edge2_found)
ocal_final_cnt_r_mux_a <= #TCQ ocal_rise_edge2_taps;
else if (~ocal_rise_edge2_found && ocal_rise_edge1_found)
ocal_final_cnt_r_mux_a <= #TCQ stg3_tap_cnt;
else if (ocal_fall_edge2_found && ocal_fall_edge1_found)
ocal_final_cnt_r_mux_a <= #TCQ ocal_fall_edge2_taps;
end
always @(posedge clk) begin
if (rst || (ocal_state_r == OCAL_NEXT_DQS) || (ocal_state_r == OCAL_DONE))
ocal_final_cnt_r_mux_b <= #TCQ 'd0;
else if (|ocal_rise_right_edge) begin
if (ocal_fall_edge2_found && ocal_fall_edge1_found)
ocal_final_cnt_r_mux_b <= #TCQ ocal_fall_edge1_taps;
else
ocal_final_cnt_r_mux_b <= #TCQ ocal_rise_edge1_taps;
end else if (ocal_rise_edge2_found && ocal_rise_edge1_found)
ocal_final_cnt_r_mux_b <= #TCQ ocal_rise_edge1_taps;
else if (ocal_rise_edge2_found && ~ocal_rise_edge1_found)
ocal_final_cnt_r_mux_b <= #TCQ 'd0;
else if (~ocal_rise_edge2_found && ocal_rise_edge1_found)
ocal_final_cnt_r_mux_b <= #TCQ ocal_rise_edge1_taps;
else if (ocal_fall_edge2_found && ocal_fall_edge1_found)
ocal_final_cnt_r_mux_b <= #TCQ ocal_fall_edge1_taps;
end
always @(posedge clk) begin
if (rst || (ocal_state_r == OCAL_NEXT_DQS) || (ocal_state_r == OCAL_DONE))
ocal_final_cnt_r_mux_c <= #TCQ 'd0;
else if (|ocal_rise_right_edge) begin
if (ocal_fall_edge2_found && ocal_fall_edge1_found)
ocal_final_cnt_r_mux_c <= #TCQ 'd1;
else
ocal_final_cnt_r_mux_c <= #TCQ (stg3_tap_cnt - ocal_rise_right_edge);
end else if (~ocal_rise_edge2_found && ocal_rise_edge1_found)
ocal_final_cnt_r_mux_c <= #TCQ 'd0;
else
ocal_final_cnt_r_mux_c <= #TCQ 'd1;
end
always @(posedge clk) begin
if (rst || (ocal_state_r == OCAL_NEXT_DQS) || (ocal_state_r == OCAL_DONE))
ocal_final_cnt_r_mux_d <= #TCQ 'd0;
else if (((|ocal_rise_right_edge) &&
(ocal_fall_edge2_found && ocal_fall_edge1_found)) ||
(ocal_fall_edge2_found && ocal_fall_edge1_found))
ocal_final_cnt_r_mux_d <= #TCQ 'd32;
else
ocal_final_cnt_r_mux_d <= #TCQ 'd0;
end
always @(posedge clk) begin
if (rst || (ocal_state_r == OCAL_NEXT_DQS) || (ocal_state_r == OCAL_DONE))
ocal_final_cnt_r <= #TCQ 'd0;
else if (ocal_state_r == OCAL_STG3_CALC)
ocal_final_cnt_r <= #TCQ ((ocal_final_cnt_r_mux_a - ocal_final_cnt_r_mux_b)>>1) +
ocal_final_cnt_r_mux_c + ocal_final_cnt_r_mux_d;
end
genvar dqs_q;
generate
for (dqs_q=0; dqs_q < DQS_WIDTH; dqs_q = dqs_q + 1) begin: tap_cnt_split
assign wl_po_fine_cnt_w[dqs_q] = wl_po_fine_cnt[6*dqs_q+:6];
end
endgenerate
// State Machine
always @(posedge clk) begin
if (rst) begin
ocal_state_r <= #TCQ OCAL_IDLE;
cnt_dqs_r <= #TCQ 'd0;
stg3_tap_cnt <= #TCQ oclkdelay_init_val;
stg3_incdec_limit <= #TCQ 'd0;
stg3_dec2inc <= #TCQ 1'b0;
stg2_tap_cnt <= #TCQ 'd0;
stg2_inc2_cnt <= #TCQ 2'b00;
stg2_dec2_cnt <= #TCQ 2'b00;
stg2_dec_cnt <= #TCQ 'd0;
stg3_dec <= #TCQ 1'b0;
wrlvl_final <= #TCQ 1'b0;
oclk_calib_resume <= #TCQ 1'b0;
oclk_prech_req <= #TCQ 1'b0;
ocal_inc_cnt <= #TCQ 'd0;
ocal_dec_cnt <= #TCQ 'd0;
ocal_stg3_inc_en <= #TCQ 1'b0;
ocal_rise_edge1_found <= #TCQ 1'b0;
ocal_rise_edge2_found <= #TCQ 1'b0;
ocal_rise_edge1_found_timing <= #TCQ 1'b0;
ocal_rise_edge2_found_timing <= #TCQ 1'b0;
ocal_rise_right_edge <= #TCQ 'd0;
ocal_rise_edge1_taps <= #TCQ 'd0;
ocal_rise_edge2_taps <= #TCQ 'd0;
ocal_fall_edge1_found <= #TCQ 1'b0;
ocal_fall_edge2_found <= #TCQ 1'b0;
ocal_fall_edge1_taps <= #TCQ 'd0;
ocal_fall_edge2_taps <= #TCQ 'd0;
ocal_byte_done <= #TCQ 1'b0;
ocal_wrlvl_done <= #TCQ 1'b0;
ocal_done_r <= #TCQ 1'b0;
po_stg23_sel <= #TCQ 1'b0;
po_en_stg23 <= #TCQ 1'b0;
po_stg23_incdec <= #TCQ 1'b0;
ocal_final_cnt_r_calc <= #TCQ 1'b0;
end else begin
case (ocal_state_r)
OCAL_IDLE: begin
if (oclkdelay_calib_start && ~oclkdelay_calib_start_r) begin
ocal_state_r <= #TCQ OCAL_NEW_DQS_WAIT;
stg3_tap_cnt <= #TCQ oclkdelay_init_val;
stg2_tap_cnt <= #TCQ wl_po_fine_cnt_w[cnt_dqs_r];
end
end
OCAL_NEW_DQS_READ: begin
oclk_prech_req <= #TCQ 1'b0;
oclk_calib_resume <= #TCQ 1'b0;
if (pat_data_match_valid_r)
ocal_state_r <= #TCQ OCAL_NEW_DQS_WAIT;
end
OCAL_NEW_DQS_WAIT: begin
oclk_calib_resume <= #TCQ 1'b0;
oclk_prech_req <= #TCQ 1'b0;
po_en_stg23 <= #TCQ 1'b0;
po_stg23_incdec <= #TCQ 1'b0;
if (pat_data_match_valid_r && !stg3_tap_cnt_eq_oclkdelay_init_val) begin
if ((stg3_limit && ~ocal_stg3_inc_en) ||
stg3_tap_cnt == 'd0) begin
// No write levling performed to avoid stage 2 coarse dec.
// Therefore stage 3 taps can only be decremented by an
// additional 15 taps after stage 2 taps reach 63.
ocal_state_r <= #TCQ OCAL_STG3_SEL;
ocal_stg3_inc_en <= #TCQ 1'b1;
stg3_incdec_limit <= #TCQ 'd0;
// An edge was detected
end else if (~pat_data_match_r) begin
// Sticky bit - asserted after we encounter an edge, although
// the current edge may not be considered the "first edge" this
// just means we found at least one edge
if (~ocal_stg3_inc_en) begin
if (|stable_fall_stg3_cnt && ~ocal_fall_edge1_found) begin
ocal_fall_edge1_found <= #TCQ 1'b1;
ocal_fall_edge1_taps <= #TCQ stg3_tap_cnt + 1;
end else begin
ocal_rise_edge1_found <= #TCQ 1'b1;
ocal_rise_edge1_found_timing <= #TCQ 1'b1;
end
end
// Sarting point was in the jitter region close to the right edge
if (~stable_rise_eye_r && ~ocal_stg3_inc_en) begin
ocal_rise_right_edge <= #TCQ stg3_tap_cnt;
ocal_state_r <= #TCQ OCAL_STG3_SEL;
// Starting point was in the valid window close to the right edge
// Or away from the right edge hence no stable_eye_r condition
// Or starting point was in the right jitter region and ocal_rise_right_edge
// is detected
end else if (ocal_stg3_inc_en) begin
// Both edges found
if (stable_fall_eye_r) begin
ocal_state_r <= #TCQ OCAL_STG3_CALC;
ocal_fall_edge2_found <= #TCQ 1'b1;
ocal_fall_edge2_taps <= #TCQ stg3_tap_cnt - 1;
end else begin
ocal_state_r <= #TCQ OCAL_STG3_CALC;
ocal_rise_edge2_found <= #TCQ 1'b1;
ocal_rise_edge2_found_timing <= #TCQ 1'b1;
ocal_rise_edge2_taps <= #TCQ stg3_tap_cnt - 1;
end
// Starting point in the valid window away from left edge
// Assuming starting point will not be in valid window close to
// left edge
end else if (stable_rise_eye_r) begin
ocal_rise_edge1_taps <= #TCQ stg3_tap_cnt + 1;
ocal_state_r <= #TCQ OCAL_STG3_SEL;
ocal_stg3_inc_en <= #TCQ 1'b1;
stg3_incdec_limit <= #TCQ 'd0;
end else
ocal_state_r <= #TCQ OCAL_STG3_SEL;
end else
ocal_state_r <= #TCQ OCAL_STG3_SEL;
end else if (stg3_tap_cnt_eq_oclkdelay_init_val)
ocal_state_r <= #TCQ OCAL_STG3_SEL;
else if ((stg3_limit && ocal_stg3_inc_en) ||
(stg3_tap_cnt_eq_63)) begin
ocal_state_r <= #TCQ OCAL_STG3_CALC;
stg3_incdec_limit <= #TCQ 'd0;
end
end
OCAL_STG3_SEL: begin
po_stg23_sel <= #TCQ 1'b1;
ocal_wrlvl_done <= #TCQ 1'b0;
ocal_state_r <= #TCQ OCAL_STG3_SEL_WAIT;
ocal_final_cnt_r_calc <= #TCQ 1'b0;
end
OCAL_STG3_SEL_WAIT: begin
if (cnt_next_state) begin
ocal_state_r <= #TCQ OCAL_STG3_EN_WAIT;
if (ocal_stg3_inc_en) begin
po_stg23_incdec <= #TCQ 1'b1;
if (stg3_tap_cnt_less_oclkdelay_init_val) begin
ocal_inc_cnt <= #TCQ oclkdelay_init_val - stg3_tap_cnt;
stg3_dec2inc <= #TCQ 1'b1;
oclk_prech_req <= #TCQ 1'b1;
end
end else begin
po_stg23_incdec <= #TCQ 1'b0;
if (stg3_dec)
ocal_dec_cnt <= #TCQ ocal_final_cnt_r;
end
end
end
OCAL_STG3_EN_WAIT: begin
if (cnt_next_state) begin
if (ocal_stg3_inc_en)
ocal_state_r <= #TCQ OCAL_STG3_INC;
else
ocal_state_r <= #TCQ OCAL_STG3_DEC;
end
end
OCAL_STG3_DEC: begin
po_en_stg23 <= #TCQ 1'b1;
stg3_tap_cnt <= #TCQ stg3_tap_cnt - 1;
if (ocal_dec_cnt == 1) begin
ocal_byte_done <= #TCQ 1'b1;
ocal_state_r <= #TCQ OCAL_DEC_DONE_WAIT;
ocal_dec_cnt <= #TCQ ocal_dec_cnt - 1;
end else if (ocal_dec_cnt > 'd0) begin
ocal_state_r <= #TCQ OCAL_STG3_DEC_WAIT;
ocal_dec_cnt <= #TCQ ocal_dec_cnt - 1;
end else
ocal_state_r <= #TCQ OCAL_STG3_WAIT;
end
OCAL_STG3_DEC_WAIT: begin
po_en_stg23 <= #TCQ 1'b0;
if (cnt_next_state) begin
if (ocal_dec_cnt > 'd0)
ocal_state_r <= #TCQ OCAL_STG3_DEC;
else
ocal_state_r <= #TCQ OCAL_DEC_DONE_WAIT;
end
end
OCAL_DEC_DONE_WAIT: begin
// Required to make sure that po_stg23_incdec
// de-asserts some time after de-assertion of
// po_en_stg23
po_en_stg23 <= #TCQ 1'b0;
if (cnt_next_state) begin
// Final stage 3 decrement completed, proceed
// to stage 2 tap decrement
ocal_state_r <= #TCQ OCAL_STG2_SEL;
po_stg23_incdec <= #TCQ 1'b0;
stg3_dec <= #TCQ 1'b0;
end
end
OCAL_STG3_WAIT: begin
po_en_stg23 <= #TCQ 1'b0;
if (cnt_next_state) begin
po_stg23_incdec <= #TCQ 1'b0;
if ((stg2_tap_cnt != 6'd63) || (stg2_tap_cnt != 6'd0))
ocal_state_r <= #TCQ OCAL_STG2_SEL;
else begin
oclk_calib_resume <= #TCQ 1'b1;
ocal_state_r <= #TCQ OCAL_NEW_DQS_WAIT;
stg3_incdec_limit <= #TCQ stg3_incdec_limit + 1;
end
end
end
OCAL_STG2_SEL: begin
po_stg23_sel <= #TCQ 1'b0;
po_en_stg23 <= #TCQ 1'b0;
po_stg23_incdec <= #TCQ 1'b0;
ocal_state_r <= #TCQ OCAL_STG2_WAIT;
stg2_inc2_cnt <= #TCQ 2'b01;
stg2_dec2_cnt <= #TCQ 2'b01;
end
OCAL_STG2_WAIT: begin
po_en_stg23 <= #TCQ 1'b0;
po_stg23_incdec <= #TCQ 1'b0;
if (cnt_next_state) begin
if (ocal_byte_done) begin
if (stg2_tap_cnt > 'd0) begin
// Decrement stage 2 taps to '0' before
// final write level is performed
ocal_state_r <= #TCQ OCAL_STG2_DEC;
stg2_dec_cnt <= #TCQ stg2_tap_cnt;
end else begin
ocal_state_r <= #TCQ OCAL_NEXT_DQS;
ocal_byte_done <= #TCQ 1'b0;
end
end else if (stg3_dec2inc && (stg2_tap_cnt > 'd0)) begin
// Decrement stage 2 tap to initial value before
// edge 2 detection begins
ocal_state_r <= #TCQ OCAL_STG2_DEC;
stg2_dec_cnt <= #TCQ stg2_tap_cnt - wl_po_fine_cnt_w[cnt_dqs_r];
end else if (~ocal_stg3_inc_en && (stg2_tap_cnt < 6'd63)) begin
// Increment stage 2 taps by 2 for every stage 3 tap decrement
// as part of edge 1 detection to avoid tDQSS violation between
// write DQS and CK
ocal_state_r <= #TCQ OCAL_STG2_INC;
end else if (ocal_stg3_inc_en && (stg2_tap_cnt > 6'd0)) begin
// Decrement stage 2 taps by 2 for every stage 3 tap increment
// as part of edge 2 detection to avoid tDQSS violation between
// write DQS and CK
ocal_state_r <= #TCQ OCAL_STG2_DEC;
end else begin
oclk_calib_resume <= #TCQ 1'b1;
ocal_state_r <= #TCQ OCAL_NEW_DQS_WAIT;
stg3_incdec_limit <= #TCQ stg3_incdec_limit + 1;
end
end
end
OCAL_STG2_INC: begin
po_en_stg23 <= #TCQ 1'b1;
po_stg23_incdec <= #TCQ 1'b1;
stg2_tap_cnt <= #TCQ stg2_tap_cnt + 1;
if (stg2_inc2_cnt > 2'b00) begin
stg2_inc2_cnt <= stg2_inc2_cnt - 1;
ocal_state_r <= #TCQ OCAL_STG2_WAIT;
end else if (stg2_tap_cnt == 6'd62) begin
ocal_state_r <= #TCQ OCAL_STG2_WAIT;
end else begin
oclk_calib_resume <= #TCQ 1'b1;
ocal_state_r <= #TCQ OCAL_NEW_DQS_WAIT;
end
end
OCAL_STG2_DEC: begin
po_en_stg23 <= #TCQ 1'b1;
po_stg23_incdec <= #TCQ 1'b0;
stg2_tap_cnt <= #TCQ stg2_tap_cnt - 1;
if (stg2_dec_cnt > 6'd0) begin
stg2_dec_cnt <= #TCQ stg2_dec_cnt - 1;
ocal_state_r <= #TCQ OCAL_STG2_DEC_WAIT;
end else if (stg2_dec2_cnt > 2'b00) begin
stg2_dec2_cnt <= stg2_dec2_cnt - 1;
ocal_state_r <= #TCQ OCAL_STG2_WAIT;
end else if (stg2_tap_cnt == 6'd1)
ocal_state_r <= #TCQ OCAL_STG2_WAIT;
else begin
oclk_calib_resume <= #TCQ 1'b1;
ocal_state_r <= #TCQ OCAL_NEW_DQS_WAIT;
end
end
OCAL_STG2_DEC_WAIT: begin
po_en_stg23 <= #TCQ 1'b0;
po_stg23_incdec <= #TCQ 1'b0;
if (cnt_next_state) begin
if (stg2_dec_cnt > 6'd0) begin
ocal_state_r <= #TCQ OCAL_STG2_DEC;
end else if (ocal_byte_done) begin
ocal_state_r <= #TCQ OCAL_NEXT_DQS;
ocal_byte_done <= #TCQ 1'b0;
end else if (prech_done_r && stg3_dec2inc) begin
stg3_dec2inc <= #TCQ 1'b0;
if (stg3_tap_cnt_eq_63)
ocal_state_r <= #TCQ OCAL_STG3_CALC;
else begin
ocal_state_r <= #TCQ OCAL_NEW_DQS_READ;
oclk_calib_resume <= #TCQ 1'b1;
end
end
end
end
OCAL_STG3_CALC: begin
if (ocal_final_cnt_r_calc) begin
ocal_state_r <= #TCQ OCAL_STG3_SEL;
stg3_dec <= #TCQ 1'b1;
ocal_stg3_inc_en <= #TCQ 1'b0;
end else
ocal_final_cnt_r_calc <= #TCQ 1'b1;
end
OCAL_STG3_INC: begin
po_en_stg23 <= #TCQ 1'b1;
stg3_tap_cnt <= #TCQ stg3_tap_cnt + 1;
if (ocal_inc_cnt > 'd0)
ocal_inc_cnt <= #TCQ ocal_inc_cnt - 1;
if (ocal_inc_cnt == 1)
ocal_state_r <= #TCQ OCAL_INC_DONE_WAIT;
else
ocal_state_r <= #TCQ OCAL_STG3_INC_WAIT;
end
OCAL_STG3_INC_WAIT: begin
po_en_stg23 <= #TCQ 1'b0;
po_stg23_incdec <= #TCQ 1'b1;
if (cnt_next_state) begin
if (ocal_inc_cnt > 'd0)
ocal_state_r <= #TCQ OCAL_STG3_INC;
else begin
ocal_state_r <= #TCQ OCAL_STG2_SEL;
po_stg23_incdec <= #TCQ 1'b0;
end
end
end
OCAL_INC_DONE_WAIT: begin
// Required to make sure that po_stg23_incdec
// de-asserts some time after de-assertion of
// po_en_stg23
po_en_stg23 <= #TCQ 1'b0;
oclk_prech_req <= #TCQ 1'b0;
if (cnt_next_state) begin
ocal_state_r <= #TCQ OCAL_STG2_SEL;
po_stg23_incdec <= #TCQ 1'b0;
end
end
OCAL_NEXT_DQS: begin
ocal_final_cnt_r_calc <= #TCQ 1'b0;
po_en_stg23 <= #TCQ 1'b0;
po_stg23_incdec <= #TCQ 1'b0;
stg3_tap_cnt <= #TCQ 6'd0;
ocal_rise_edge1_found <= #TCQ 1'b0;
ocal_rise_edge2_found <= #TCQ 1'b0;
ocal_rise_edge1_found_timing <= #TCQ 1'b0;
ocal_rise_edge2_found_timing <= #TCQ 1'b0;
ocal_rise_edge1_taps <= #TCQ 'd0;
ocal_rise_edge2_taps <= #TCQ 'd0;
ocal_rise_right_edge <= #TCQ 'd0;
ocal_fall_edge1_found <= #TCQ 1'b0;
ocal_fall_edge2_found <= #TCQ 1'b0;
ocal_fall_edge1_taps <= #TCQ 'd0;
ocal_fall_edge2_taps <= #TCQ 'd0;
stg3_incdec_limit <= #TCQ 'd0;
oclk_prech_req <= #TCQ 1'b1;
if (cnt_dqs_r == DQS_WIDTH-1)
wrlvl_final <= #TCQ 1'b1;
if (prech_done) begin
if (cnt_dqs_r == DQS_WIDTH-1)
// If the last DQS group was just finished,
// then end of calibration
ocal_state_r <= #TCQ OCAL_DONE;
else begin
// Continue to next DQS group
cnt_dqs_r <= #TCQ cnt_dqs_r + 1;
ocal_state_r <= #TCQ OCAL_NEW_DQS_READ;
stg3_tap_cnt <= #TCQ oclkdelay_init_val;
stg2_tap_cnt <= #TCQ wl_po_fine_cnt_w[cnt_dqs_r + 1'b1];
end
end
end
OCAL_DONE: begin
ocal_final_cnt_r_calc <= #TCQ 1'b0;
oclk_prech_req <= #TCQ 1'b0;
po_stg23_sel <= #TCQ 1'b0;
ocal_done_r <= #TCQ 1'b1;
end
endcase
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005-2007 by Wilson Snyder.
module t (/*AUTOARG*/);
reg [3:0] value;
reg [3:0] valuex;
// verilator lint_off CASEOVERLAP
// verilator lint_off CASEWITHX
// verilator lint_off CASEX
// Note for Verilator Xs must become zeros, or the Xs may match.
initial begin
value = 4'b1001;
valuex = 4'b1xxx;
case (value)
4'b1xxx: $stop;
4'b1???: $stop;
4'b1001: ;
default: $stop;
endcase
case (valuex)
4'b1???: $stop;
4'b1xxx: ;
4'b1001: ;
4'b1000: ; // 1xxx is mapped to this by Verilator -x-assign 0
default: $stop;
endcase
//
casex (value)
4'b100x: ;
default: $stop;
endcase
casex (value)
4'b100?: ;
default: $stop;
endcase
casex (valuex)
4'b100x: ;
default: $stop;
endcase
casex (valuex)
4'b100?: ;
default: $stop;
endcase
//
casez (value)
4'bxxxx: $stop;
4'b100?: ;
default: $stop;
endcase
casez (valuex)
4'b1xx?: ;
4'b100?: ; // 1xxx is mapped to this by Verilator -x-assign 0
default: $stop;
endcase
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_t
//
// Generated
// by: wig
// on: Thu Jun 22 05:51:07 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../highlow.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_t.v,v 1.3 2006/06/22 07:20:00 wig Exp $
// $Date: 2006/06/22 07:20:00 $
// $Log: ent_t.v,v $
// Revision 1.3 2006/06/22 07:20:00 wig
// Updated testcases and extended MixTest.pl to also verify number of created files.
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.89 2006/05/23 06:48:05 wig Exp
//
// Generator: mix_0.pl Revision: 1.45 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of ent_t
//
// No user `defines in this module
module ent_t
//
// Generated Module inst_t
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
wire mix_logic0_0;
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
assign mix_logic0_0 = 1'b0;
//
// Generated Instances and Port Mappings
//
// Generated Instance Port Map for inst_a
ent_a inst_a (
.low_bit_a(mix_logic0_0) // Ground bit port
);
// End of Generated Instance Port Map for inst_a
// Generated Instance Port Map for inst_b
ent_b inst_b (
);
// End of Generated Instance Port Map for inst_b
endmodule
//
// End of Generated Module rtl of ent_t
//
//
//!End of Module/s
// --------------------------------------------------------------
|
// Double pumped single precision floating point multiply
// Latency = 6 kernel clocks
// // (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// !!! WARNING !!!
// This core no longer works because the core is no longer fully high-capacity
// (and has a single staging register, which messes up things in the 2x clock
// domain). See acl_fp_custom_mul_hc.v and acl_fp_custom_mul_hc_core.v for
// details.
// !!! WARNING !!!
module acl_fp_custom_mul_hc_dbl_pumped
#( parameter WIDTH = 32 )
(
input logic clock,
input logic clock2x,
input logic resetn,
input logic valid_in,
input logic stall_in,
output logic valid_out,
output logic stall_out,
input logic [WIDTH-1:0] a1,
input logic [WIDTH-1:0] b1,
input logic [WIDTH-1:0] a2,
input logic [WIDTH-1:0] b2,
output logic [WIDTH-1:0] y1,
output logic [WIDTH-1:0] y2
);
localparam LATENCY = 6; // in "clock" cycles
// Prevent sharing of these registers across different instances
// (and even kernels!). The sharing may cause very long paths
// across the chip, which limits fmax of clock2x.
logic sel2x /* synthesis preserve */;
// This is for simulation purposes. Matches physical behavior where
// registers power up to zero.
initial
begin
sel2x = 1'b0;
end
always@(posedge clock2x)
sel2x <= ~sel2x; // either the same as clock or ~clock
// The block is high-capacity. Here are all of the
// valid_in/out, stall_in/out signals for all "clock" cycles.
//
// Index 1 corresponds to the first cycle.
typedef struct packed {
logic valid_in, valid_out;
logic stall_in, stall_out;
} stage_flow_control;
stage_flow_control s [1:LATENCY];
genvar i;
generate
for( i = 1; i <= LATENCY; i = i + 1 )
begin:stage
// valid_in
if( i == 1 )
assign s[i].valid_in = valid_in;
else
assign s[i].valid_in = s[i-1].valid_out;
// valid_out
always @(posedge clock or negedge resetn)
if( ~resetn )
s[i].valid_out <= 1'b0;
else if( ~s[i].stall_out )
s[i].valid_out <= s[i].valid_in;
// stall_in
if( i == LATENCY )
assign s[i].stall_in = stall_in;
else
assign s[i].stall_in = s[i+1].stall_out;
// stall_out
assign s[i].stall_out = s[i].valid_out & s[i].stall_in;
end
endgenerate
assign valid_out = s[LATENCY].valid_out;
assign stall_out = s[1].stall_out;
// Register before double pumping
logic [WIDTH-1:0] a1_reg;
logic [WIDTH-1:0] b1_reg;
logic [WIDTH-1:0] a2_reg;
logic [WIDTH-1:0] b2_reg;
always @(posedge clock)
if( ~s[1].stall_out )
begin
a1_reg <= a1;
a2_reg <= a2;
b1_reg <= b1;
b2_reg <= b2;
end
// Clock domain transfer
logic [WIDTH-1:0] a1_reg_2x;
logic [WIDTH-1:0] a2_reg_2x;
logic [WIDTH-1:0] b1_reg_2x;
logic [WIDTH-1:0] b2_reg_2x;
logic valid_out_2x;
always @(posedge clock2x)
if( ~s[2].stall_out )
begin
a1_reg_2x <= a1_reg;
a2_reg_2x <= a2_reg;
b1_reg_2x <= b1_reg;
b2_reg_2x <= b2_reg;
valid_out_2x <= s[1].valid_out;
end
// The multipler. Takes six "clock2x" cycles to complete
// (so takes 3 "clock" cycles to complete).
logic [WIDTH-1:0] fp_mul_inp_a;
logic [WIDTH-1:0] fp_mul_inp_b;
logic [WIDTH-1:0] fp_mul_res;
logic fp_mul_valid_out, fp_mul_stall_out;
assign fp_mul_inp_a = (sel2x) ? a2_reg_2x : a1_reg_2x;
assign fp_mul_inp_b = (sel2x) ? b2_reg_2x : b1_reg_2x;
acl_fp_custom_mul_hc the_mul(
.resetn(resetn),
.clock(clock2x),
.valid_in(valid_out_2x),
.stall_in(s[5].stall_out),
.valid_out(fp_mul_valid_out),
.stall_out(fp_mul_stall_out),
.dataa(fp_mul_inp_a),
.datab(fp_mul_inp_b),
.result(fp_mul_res));
// Track which set of inputs was selected in parallel with the
// multipler's pipeline. Track in the "clock2x" domain.
//
// There are six stages in this pipeline to correspond with the
// six stages in acl_fp_custom_mul_hc's pipeline.
logic sel_21, sel_22, sel_31, sel_32, sel_41, sel_42;
always @(posedge clock2x)
begin
if( ~s[2].stall_out ) // clock -> clock2x
begin
sel_21 <= sel2x;
sel_22 <= sel_21;
end
if( ~s[3].stall_out ) // clock -> clock2x
begin
sel_31 <= sel_22;
sel_32 <= sel_31;
end
if( ~s[4].stall_out ) // clock -> clock2x
begin
sel_41 <= sel_32;
sel_42 <= sel_41;
end
end
// Additional clock2x pipeline register to even things out
// and separate the results from the two inputs in preparation
// for the clock transfer back to the "clock" domain.
logic [31:0] res1_5, res2_5;
always @(posedge clock2x)
if( ~s[5].stall_out ) // clock -> clock2x
begin
if( sel_42 )
begin
// This is the result from the 2nd set of inputs.
res2_5 <= fp_mul_res;
end
else
begin
// This is the result from the 1st set of inputs.
res1_5 <= fp_mul_res;
end
end
// Output registers. Cross-clock path from clock2x -> clock.
always @(posedge clock)
begin
if( ~s[6].stall_out )
begin
y1 <= res1_5;
y2 <= res2_5;
end
end
endmodule
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2007 Corgan Enterprises LLC
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module lfsr(clk_i,rst_i,ena_i,strobe_i,mask_i,pn_o);
parameter width = 16;
input clk_i;
input rst_i;
input ena_i;
input strobe_i;
input [width-1:0] mask_i;
output pn_o;
reg [width-1:0] shifter;
wire parity = ^(shifter & mask_i);
always @(posedge clk_i)
if (rst_i | ~ena_i)
shifter <= #5 1;
else
if (strobe_i)
shifter <= #5 {shifter[width-2:0],parity};
assign pn_o = shifter[0];
endmodule // lfsr
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2020 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/);
logic in1 = 1;
logic [1:0] in2 = 2'b11;
logic [31:0] out;
logic [7:0] ones = 8'b11111111;
logic [9:0] ones10 = 10'b1111111111;
typedef logic [7:0] data_t;
typedef logic [9:0] ten_t;
ten_t out10;
// verilator lint_off WIDTH
initial begin
in1 = 1;
in2 = 0;
out = data_t'(in1 << in2);
if (out != 8'b1) $stop;
in2 = 1;
out = data_t'(in1 << in2);
if (out != 8'b10) $stop;
in2 = 2;
out = data_t'(in1 << in2);
if (out != 8'b100) $stop;
in2 = 3;
out = data_t'(in1 << in2);
if (out != 8'b1000) $stop;
// Check upper bits get cleared when cast
in2 = 3;
out = data_t'(ones << in2);
if (out != 8'b11111000) $stop;
in2 = 3;
out = data_t'(ones10 << in2);
if (out != 8'b11111000) $stop;
// bug2597
out = data_t'(10'h208 >> 2);
if (out != 8'h82) $stop;
out = data_t'(10'h208 >> 2);
if (out != 8'h82) $stop;
out = data_t'('h208 >> 2);
if (out != 8'h82) $stop;
out10 = ten_t'('h404 >> 2);
if (out10 != 10'h101) $stop;
$write("*-* All Finished *-*\n");
$finish();
end
endmodule
|
// (C) 2001-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/14.0/ip/merlin/altera_avalon_mm_clock_crossing_bridge/altera_avalon_mm_clock_crossing_bridge.v#1 $
// $Revision: #1 $
// $Date: 2014/02/16 $
// $Author: swbranch $
// --------------------------------------
// Avalon-MM clock crossing bridge
//
// Clock crosses MM commands and responses with the
// help of asynchronous FIFOs.
//
// This bridge will stop emitting read commands when
// too many read commands are in flight to avoid
// response FIFO overflow.
// --------------------------------------
`timescale 1 ns / 1 ns
module altera_avalon_mm_clock_crossing_bridge
#(
parameter DATA_WIDTH = 32,
parameter SYMBOL_WIDTH = 8,
parameter HDL_ADDR_WIDTH = 10,
parameter BURSTCOUNT_WIDTH = 1,
parameter COMMAND_FIFO_DEPTH = 4,
parameter RESPONSE_FIFO_DEPTH = 4,
parameter MASTER_SYNC_DEPTH = 2,
parameter SLAVE_SYNC_DEPTH = 2,
// --------------------------------------
// Derived parameters
// --------------------------------------
parameter BYTEEN_WIDTH = DATA_WIDTH / SYMBOL_WIDTH
)
(
input s0_clk,
input s0_reset,
input m0_clk,
input m0_reset,
output s0_waitrequest,
output [DATA_WIDTH-1:0] s0_readdata,
output s0_readdatavalid,
input [BURSTCOUNT_WIDTH-1:0] s0_burstcount,
input [DATA_WIDTH-1:0] s0_writedata,
input [HDL_ADDR_WIDTH-1:0] s0_address,
input s0_write,
input s0_read,
input [BYTEEN_WIDTH-1:0] s0_byteenable,
input s0_debugaccess,
input m0_waitrequest,
input [DATA_WIDTH-1:0] m0_readdata,
input m0_readdatavalid,
output [BURSTCOUNT_WIDTH-1:0] m0_burstcount,
output [DATA_WIDTH-1:0] m0_writedata,
output [HDL_ADDR_WIDTH-1:0] m0_address,
output m0_write,
output m0_read,
output [BYTEEN_WIDTH-1:0] m0_byteenable,
output m0_debugaccess
);
localparam CMD_WIDTH = BURSTCOUNT_WIDTH + DATA_WIDTH + HDL_ADDR_WIDTH
+ BYTEEN_WIDTH
+ 3; // read, write, debugaccess
localparam NUMSYMBOLS = DATA_WIDTH / SYMBOL_WIDTH;
localparam RSP_WIDTH = DATA_WIDTH;
localparam MAX_BURST = (1 << (BURSTCOUNT_WIDTH-1));
localparam COUNTER_WIDTH = log2ceil(RESPONSE_FIFO_DEPTH) + 1;
localparam NON_BURSTING = (MAX_BURST == 1);
localparam BURST_WORDS_W = BURSTCOUNT_WIDTH;
// --------------------------------------
// Signals
// --------------------------------------
wire [CMD_WIDTH-1:0] s0_cmd_payload;
wire [CMD_WIDTH-1:0] m0_cmd_payload;
wire s0_cmd_valid;
wire m0_cmd_valid;
wire m0_internal_write;
wire m0_internal_read;
wire s0_cmd_ready;
wire m0_cmd_ready;
reg [COUNTER_WIDTH-1:0] pending_read_count;
wire [COUNTER_WIDTH-1:0] space_avail;
wire stop_cmd;
reg stop_cmd_r;
wire m0_read_accepted;
wire m0_rsp_ready;
reg old_read;
wire [BURST_WORDS_W-1:0] m0_burstcount_words;
// --------------------------------------
// Command FIFO
// --------------------------------------
(* altera_attribute = "-name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON" *) altera_avalon_dc_fifo
#(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (CMD_WIDTH),
.FIFO_DEPTH (COMMAND_FIFO_DEPTH),
.WR_SYNC_DEPTH (MASTER_SYNC_DEPTH),
.RD_SYNC_DEPTH (SLAVE_SYNC_DEPTH),
.BACKPRESSURE_DURING_RESET (1)
)
cmd_fifo
(
.in_clk (s0_clk),
.in_reset_n (~s0_reset),
.out_clk (m0_clk),
.out_reset_n (~m0_reset),
.in_data (s0_cmd_payload),
.in_valid (s0_cmd_valid),
.in_ready (s0_cmd_ready),
.out_data (m0_cmd_payload),
.out_valid (m0_cmd_valid),
.out_ready (m0_cmd_ready),
.in_startofpacket (1'b0),
.in_endofpacket (1'b0),
.in_empty ('b0),
.in_error ('b0),
.in_channel ('b0),
.in_csr_address ('b0),
.in_csr_read ('b0),
.in_csr_write ('b0),
.in_csr_writedata (32'b0),
.out_csr_address ('b0),
.out_csr_read ('b0),
.out_csr_write ('b0),
.out_csr_writedata (32'b0)
);
// --------------------------------------
// Command payload
// --------------------------------------
assign s0_waitrequest = ~s0_cmd_ready;
assign s0_cmd_valid = s0_write | s0_read;
assign s0_cmd_payload = {s0_address,
s0_burstcount,
s0_read,
s0_write,
s0_writedata,
s0_byteenable,
s0_debugaccess};
assign {m0_address,
m0_burstcount,
m0_internal_read,
m0_internal_write,
m0_writedata,
m0_byteenable,
m0_debugaccess} = m0_cmd_payload;
assign m0_cmd_ready = ~m0_waitrequest &
~(m0_internal_read & stop_cmd_r & ~old_read);
assign m0_write = m0_internal_write & m0_cmd_valid;
assign m0_read = m0_internal_read & m0_cmd_valid & (~stop_cmd_r | old_read);
assign m0_read_accepted = m0_read & ~m0_waitrequest;
// ---------------------------------------------
// the non-bursting case
// ---------------------------------------------
generate if (NON_BURSTING)
begin
always @(posedge m0_clk, posedge m0_reset) begin
if (m0_reset) begin
pending_read_count <= 0;
end
else begin
if (m0_read_accepted & m0_readdatavalid)
pending_read_count <= pending_read_count;
else if (m0_readdatavalid)
pending_read_count <= pending_read_count - 1;
else if (m0_read_accepted)
pending_read_count <= pending_read_count + 1;
end
end
end
// ---------------------------------------------
// the bursting case
// ---------------------------------------------
else begin
assign m0_burstcount_words = m0_burstcount;
always @(posedge m0_clk, posedge m0_reset) begin
if (m0_reset) begin
pending_read_count <= 0;
end
else begin
if (m0_read_accepted & m0_readdatavalid)
pending_read_count <= pending_read_count +
m0_burstcount_words - 1;
else if (m0_readdatavalid)
pending_read_count <= pending_read_count - 1;
else if (m0_read_accepted)
pending_read_count <= pending_read_count +
m0_burstcount_words;
end
end
end
endgenerate
assign stop_cmd = (pending_read_count + 2*MAX_BURST) > space_avail;
always @(posedge m0_clk, posedge m0_reset) begin
if (m0_reset) begin
stop_cmd_r <= 1'b0;
old_read <= 1'b0;
end
else begin
stop_cmd_r <= stop_cmd;
old_read <= m0_read & m0_waitrequest;
end
end
// --------------------------------------
// Response FIFO
// --------------------------------------
(* altera_attribute = "-name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON" *) altera_avalon_dc_fifo
#(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (RSP_WIDTH),
.FIFO_DEPTH (RESPONSE_FIFO_DEPTH),
.WR_SYNC_DEPTH (SLAVE_SYNC_DEPTH),
.RD_SYNC_DEPTH (MASTER_SYNC_DEPTH),
.USE_SPACE_AVAIL_IF (1)
)
rsp_fifo
(
.in_clk (m0_clk),
.in_reset_n (~m0_reset),
.out_clk (s0_clk),
.out_reset_n (~s0_reset),
.in_data (m0_readdata),
.in_valid (m0_readdatavalid),
// ------------------------------------
// must never overflow, or we're in trouble
// (we cannot backpressure the response)
// ------------------------------------
.in_ready (m0_rsp_ready),
.out_data (s0_readdata),
.out_valid (s0_readdatavalid),
.out_ready (1'b1),
.space_avail_data (space_avail),
.in_startofpacket (1'b0),
.in_endofpacket (1'b0),
.in_empty ('b0),
.in_error ('b0),
.in_channel ('b0),
.in_csr_address ('b0),
.in_csr_read ('b0),
.in_csr_write ('b0),
.in_csr_writedata (32'b0),
.out_csr_address ('b0),
.out_csr_read ('b0),
.out_csr_write ('b0),
.out_csr_writedata (32'b0)
);
// synthesis translate_off
always @(posedge m0_clk) begin
if (~m0_rsp_ready & m0_readdatavalid) begin
$display("%t %m: internal error, response fifo overflow", $time);
end
if (pending_read_count > space_avail) begin
$display("%t %m: internal error, too many pending reads", $time);
end
end
// synthesis translate_on
// --------------------------------------------------
// Calculates the log2ceil of the input value
// --------------------------------------------------
function integer log2ceil;
input integer val;
integer i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule
|
`timescale 1ns/100ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
/**
* This is written by Zhiyang Ong
* for EE577b Homework 2, Question 2
*/
// Testbench for behavioral model for the decoder
// Import the modules that will be tested for in this testbench
`include "decoder4to16.v"
// IMPORTANT: To run this, try: ncverilog -f ee577bHw2q2.f +gui
module tb_decoder4to16();
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the arbiter
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUT
wire [15:1] dout;
// Declare "reg" signals: inputs to the DUT
reg [3:0] din;
/**
* Instantiate an instance of arbiter_LRU4 so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "arb"
*/
decoder4to16 dec4to16 (
// instance_name(signal name),
// Signal name can be the same as the instance name
din,dout);
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display(" << Starting the simulation >>");
din = 15'd0;
#1;
din = 15'd1;
// @ t=0,
#1;
din = 15'd2;
#1;
din = 15'd3;
#1;
din = 15'd4;
#1;
din = 15'd5;
#1;
din = 15'd6;
#1;
din = 15'd7;
#1;
din = 15'd8;
#1;
din = 15'd9;
#1;
din = 15'd10;
#1;
din = 15'd11;
#1;
din = 15'd12;
#1;
din = 15'd13;
#1;
din = 15'd14;
#1;
din = 15'd15;
#20;
$display(" << Finishing the simulation >>");
$finish;
end
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module ddr3_s4_uniphy_example_if0_p0_write_datapath(
pll_afi_clk,
reset_n,
force_oct_off,
phy_ddio_oct_ena,
afi_dqs_en,
afi_wdata,
afi_wdata_valid,
afi_dm,
phy_ddio_dq,
phy_ddio_dqs_en,
phy_ddio_wrdata_en,
phy_ddio_wrdata_mask
);
parameter MEM_ADDRESS_WIDTH = "";
parameter MEM_DM_WIDTH = "";
parameter MEM_CONTROL_WIDTH = "";
parameter MEM_DQ_WIDTH = "";
parameter MEM_READ_DQS_WIDTH = "";
parameter MEM_WRITE_DQS_WIDTH = "";
parameter AFI_ADDRESS_WIDTH = "";
parameter AFI_DATA_MASK_WIDTH = "";
parameter AFI_CONTROL_WIDTH = "";
parameter AFI_DATA_WIDTH = "";
parameter AFI_DQS_WIDTH = "";
parameter NUM_WRITE_PATH_FLOP_STAGES = "";
input pll_afi_clk;
input reset_n;
input [AFI_DQS_WIDTH-1:0] force_oct_off;
output [AFI_DQS_WIDTH-1:0] phy_ddio_oct_ena;
input [AFI_DQS_WIDTH-1:0] afi_dqs_en;
input [AFI_DATA_WIDTH-1:0] afi_wdata;
input [AFI_DQS_WIDTH-1:0] afi_wdata_valid;
input [AFI_DATA_MASK_WIDTH-1:0] afi_dm;
output [AFI_DATA_WIDTH-1:0] phy_ddio_dq;
output [AFI_DQS_WIDTH-1:0] phy_ddio_dqs_en;
output [AFI_DQS_WIDTH-1:0] phy_ddio_wrdata_en;
output [AFI_DATA_MASK_WIDTH-1:0] phy_ddio_wrdata_mask;
wire [AFI_DQS_WIDTH-1:0] phy_ddio_dqs_en_pre_shift;
wire [AFI_DATA_WIDTH-1:0] phy_ddio_dq_pre_shift;
wire [AFI_DQS_WIDTH-1:0] phy_ddio_wrdata_en_pre_shift;
wire [AFI_DATA_MASK_WIDTH-1:0] phy_ddio_wrdata_mask_pre_shift;
generate
genvar stage;
if (NUM_WRITE_PATH_FLOP_STAGES == 0)
begin
assign phy_ddio_dq_pre_shift = afi_wdata;
assign phy_ddio_dqs_en_pre_shift = afi_dqs_en;
assign phy_ddio_wrdata_en_pre_shift = afi_wdata_valid;
assign phy_ddio_wrdata_mask_pre_shift = afi_dm;
end
else
begin
reg [AFI_DATA_WIDTH-1:0] afi_wdata_r [NUM_WRITE_PATH_FLOP_STAGES-1:0];
reg [AFI_DQS_WIDTH-1:0] afi_wdata_valid_r [NUM_WRITE_PATH_FLOP_STAGES-1:0] /* synthesis dont_merge */;
reg [AFI_DQS_WIDTH-1:0] afi_dqs_en_r [NUM_WRITE_PATH_FLOP_STAGES-1:0];
// phy_ddio_wrdata_mask is tied low during calibration
// the purpose of the assignment is to avoid Quartus from connecting the signal to the sclr pin of the flop
// sclr pin is very slow and causes timing failures
(* altera_attribute = {"-name ALLOW_SYNCH_CTRL_USAGE OFF"}*) reg [AFI_DATA_MASK_WIDTH-1:0] afi_dm_r [NUM_WRITE_PATH_FLOP_STAGES-1:0];
always @(posedge pll_afi_clk)
begin
afi_wdata_r[0] <= afi_wdata;
afi_dqs_en_r[0] <= afi_dqs_en;
afi_wdata_valid_r[0] <= afi_wdata_valid;
afi_dm_r[0] <= afi_dm;
end
for (stage = 1; stage < NUM_WRITE_PATH_FLOP_STAGES; stage = stage + 1)
begin : stage_gen
always @(posedge pll_afi_clk)
begin
afi_wdata_r[stage] <= afi_wdata_r[stage-1];
afi_dqs_en_r[stage] <= afi_dqs_en_r[stage-1];
afi_wdata_valid_r[stage] <= afi_wdata_valid_r[stage-1];
afi_dm_r[stage] <= afi_dm_r[stage-1];
end
end
assign phy_ddio_dq_pre_shift = afi_wdata_r[NUM_WRITE_PATH_FLOP_STAGES-1];
assign phy_ddio_dqs_en_pre_shift = afi_dqs_en_r[NUM_WRITE_PATH_FLOP_STAGES-1];
assign phy_ddio_wrdata_en_pre_shift = afi_wdata_valid_r[NUM_WRITE_PATH_FLOP_STAGES-1];
assign phy_ddio_wrdata_mask_pre_shift = afi_dm_r[NUM_WRITE_PATH_FLOP_STAGES-1];
end
endgenerate
wire [AFI_DQS_WIDTH-1:0] oct_ena;
reg [MEM_WRITE_DQS_WIDTH-1:0] dqs_en_reg;
always @(posedge pll_afi_clk)
dqs_en_reg <= phy_ddio_dqs_en[AFI_DQS_WIDTH-1:MEM_WRITE_DQS_WIDTH];
assign oct_ena[AFI_DQS_WIDTH-1:MEM_WRITE_DQS_WIDTH] = ~phy_ddio_dqs_en[AFI_DQS_WIDTH-1:MEM_WRITE_DQS_WIDTH];
assign oct_ena[MEM_WRITE_DQS_WIDTH-1:0] = ~(phy_ddio_dqs_en[AFI_DQS_WIDTH-1:MEM_WRITE_DQS_WIDTH] | dqs_en_reg);
assign phy_ddio_oct_ena_pre_shift = oct_ena & ~force_oct_off;
assign phy_ddio_dq = phy_ddio_dq_pre_shift;
assign phy_ddio_wrdata_mask = phy_ddio_wrdata_mask_pre_shift;
assign phy_ddio_wrdata_en = phy_ddio_wrdata_en_pre_shift;
assign phy_ddio_dqs_en = phy_ddio_dqs_en_pre_shift;
assign phy_ddio_oct_ena = phy_ddio_oct_ena_pre_shift;
endmodule
|
/*
* Palette register file for VGA
* Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module vga_palette_regs (
input clk,
// VGA read interface
input [3:0] attr,
output reg [7:0] index,
// CPU interface
input [3:0] address,
input write,
output reg [7:0] read_data,
input [7:0] write_data
);
// Registers
reg [7:0] palette [0:15];
// Behaviour
// VGA read interface
always @(posedge clk) index <= palette[attr];
// CPU read interface
always @(posedge clk) read_data <= palette[address];
// CPU write interface
always @(posedge clk)
if (write) palette[address] <= write_data;
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized OR with generic_baseblocks_v2_1_carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_carry_or #
(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
)
(
input wire CIN,
input wire S,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL
assign COUT = CIN | S;
end else begin : USE_FPGA
wire S_n;
assign S_n = ~S;
MUXCY and_inst
(
.O (COUT),
.CI (CIN),
.DI (1'b1),
.S (S_n)
);
end
endgenerate
endmodule
|
module DLX ( clk, rst, iram_data, Data_out_fromRAM, addr_to_iram, read_op,
write_op, nibble, write_byte, Address_toRAM, Data_in );
input [31:0] iram_data;
input [31:0] Data_out_fromRAM;
output [31:0] addr_to_iram;
output [1:0] nibble;
output [31:0] Address_toRAM;
output [31:0] Data_in;
input clk, rst;
output read_op, write_op, write_byte;
wire n8641, n8642, n8643, n8644, n8645, n8646, n8647, n8648, n8649, n8650,
n8651, n8652, n8653, n8654, n8655, n8656, n8657, n8658, n8659, n8660,
n8661, n8662, n8663, n8664, n8665, n8666, n8667, n8668, n8669, n8670,
n8671, n8672, n8673, n8674, n8675, \u_DataPath/reg_write_i ,
\u_DataPath/jump_i , \u_DataPath/u_fetch/pc1/N3 ,
\u_DataPath/u_decode_unit/reg_file0/N154 ,
\u_DataPath/u_decode_unit/reg_file0/N153 ,
\u_DataPath/u_decode_unit/reg_file0/N152 ,
\u_DataPath/u_decode_unit/reg_file0/N151 ,
\u_DataPath/u_decode_unit/reg_file0/N150 ,
\u_DataPath/u_decode_unit/reg_file0/N149 ,
\u_DataPath/u_decode_unit/reg_file0/N148 ,
\u_DataPath/u_decode_unit/reg_file0/N147 ,
\u_DataPath/u_decode_unit/reg_file0/N146 ,
\u_DataPath/u_decode_unit/reg_file0/N145 ,
\u_DataPath/u_decode_unit/reg_file0/N144 ,
\u_DataPath/u_decode_unit/reg_file0/N143 ,
\u_DataPath/u_decode_unit/reg_file0/N142 ,
\u_DataPath/u_decode_unit/reg_file0/N141 ,
\u_DataPath/u_decode_unit/reg_file0/N140 ,
\u_DataPath/u_decode_unit/reg_file0/N139 ,
\u_DataPath/u_decode_unit/reg_file0/N138 ,
\u_DataPath/u_decode_unit/reg_file0/N137 ,
\u_DataPath/u_decode_unit/reg_file0/N136 ,
\u_DataPath/u_decode_unit/reg_file0/N135 ,
\u_DataPath/u_decode_unit/reg_file0/N134 ,
\u_DataPath/u_decode_unit/reg_file0/N133 ,
\u_DataPath/u_decode_unit/reg_file0/N132 ,
\u_DataPath/u_decode_unit/reg_file0/N131 ,
\u_DataPath/u_decode_unit/reg_file0/N130 ,
\u_DataPath/u_decode_unit/reg_file0/N129 ,
\u_DataPath/u_decode_unit/reg_file0/N128 ,
\u_DataPath/u_decode_unit/reg_file0/N127 ,
\u_DataPath/u_decode_unit/reg_file0/N126 ,
\u_DataPath/u_decode_unit/reg_file0/N125 ,
\u_DataPath/u_decode_unit/reg_file0/N92 ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][31] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][30] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][29] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][28] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][27] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][26] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][25] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][24] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][23] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][22] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][21] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][20] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][19] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][18] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][17] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][16] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][15] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][14] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][13] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][12] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][11] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][10] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][9] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][8] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][7] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][6] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][5] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][4] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][3] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][2] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][1] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][0] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][31] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][30] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][29] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][28] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][27] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][26] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][25] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][24] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][23] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][22] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][21] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][20] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][19] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][18] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][17] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][16] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][15] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][14] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][13] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][12] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][11] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][10] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][9] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][8] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][7] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][6] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][5] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][4] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][3] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][2] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][1] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][0] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][31] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][30] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][29] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][28] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][27] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][26] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][25] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][24] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][23] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][22] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][21] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][20] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][19] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][18] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][17] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][16] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][15] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][14] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][13] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][12] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][11] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][10] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][9] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][8] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][7] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][6] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][5] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][4] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][3] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][2] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][1] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][0] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][31] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][30] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][29] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][28] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][27] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][26] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][25] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][24] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][23] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][22] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][21] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][20] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][19] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][18] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][17] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][16] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][15] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][14] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][13] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][12] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][11] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][10] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][9] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][8] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][7] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][6] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][5] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][4] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][3] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][2] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][1] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][0] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][31] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][30] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][29] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][28] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][27] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][26] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][25] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][24] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][23] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][22] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][21] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][20] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][19] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][18] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][17] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][16] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][15] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][14] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][13] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][12] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][11] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][10] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][9] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][8] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][7] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][6] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][5] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][4] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][3] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][2] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][1] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][0] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][31] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][30] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][29] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][28] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][27] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][26] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][25] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][24] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][23] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][22] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][21] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][20] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][19] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][18] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][17] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][16] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][15] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][14] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][13] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][12] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][11] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][10] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][9] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][8] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][7] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][6] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][5] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][4] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][3] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][2] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][1] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][0] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][31] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][30] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][29] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][28] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][27] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][26] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][25] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][24] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][23] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][22] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][21] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][20] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][19] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][18] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][17] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][16] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][15] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][14] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][13] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][12] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][11] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][10] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][9] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][8] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][7] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][6] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][5] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][4] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][3] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][2] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][1] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][0] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][31] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][30] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][29] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][28] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][27] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][26] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][25] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][24] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][23] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][22] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][21] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][20] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][19] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][18] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][17] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][16] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][15] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][14] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][13] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][12] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][11] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][10] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][9] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][8] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][7] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][6] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][5] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][4] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][3] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][2] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][1] ,
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\u_DataPath/u_decode_unit/reg_file0/bank_register[26][30] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][29] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][28] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][27] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][26] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][25] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][24] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][23] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][22] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][21] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][20] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][19] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][18] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][17] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][16] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][15] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][14] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][13] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][12] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][11] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][10] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][9] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][8] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][7] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][6] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][5] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][4] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][3] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][2] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][1] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][0] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][31] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][30] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][29] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][28] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][27] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][26] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][25] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][24] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][23] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][22] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][21] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][20] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][19] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][18] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][17] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][16] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][15] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][14] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][13] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][12] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][11] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][10] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][9] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][8] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][7] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][6] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][5] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][4] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][3] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][2] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][1] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][0] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][31] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][30] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][29] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][28] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][27] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][26] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][25] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][24] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][23] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][22] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][21] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][20] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][19] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][18] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][17] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][16] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][15] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][14] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][13] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][12] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][11] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][10] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][9] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][8] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][7] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][6] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][5] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][4] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][3] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][2] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][1] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][0] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][31] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][30] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][29] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][28] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][27] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][26] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][25] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][24] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][23] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][22] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][21] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][20] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][19] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][18] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][17] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][16] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][15] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][14] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][13] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][12] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][11] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][10] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][9] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][8] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][7] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][6] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][5] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][4] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][3] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][2] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][1] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][0] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][31] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][30] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][29] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][28] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][27] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][26] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][25] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][24] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][23] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][22] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][21] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][20] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][19] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][18] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][17] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][16] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][15] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][14] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][13] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][12] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][11] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][10] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][9] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][8] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][7] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][6] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][5] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][4] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][3] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][2] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][1] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][0] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][31] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][30] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][29] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][28] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][27] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][26] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][25] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][24] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][23] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][22] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][21] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][20] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][19] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][18] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][17] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][16] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][15] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][14] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][13] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][12] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][11] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][10] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][9] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][8] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][7] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][6] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][5] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][4] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][3] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][2] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][1] ,
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][0] ,
\u_DataPath/u_idexreg/N184 , \u_DataPath/u_idexreg/N33 ,
\u_DataPath/u_idexreg/N31 , \u_DataPath/u_idexreg/N16 ,
\u_DataPath/u_idexreg/N15 , \u_DataPath/u_idexreg/N10 ,
\u_DataPath/u_idexreg/N3 , \u_DataPath/u_execute/ovf_i ,
\u_DataPath/u_execute/EXALU/N811 , \u_DataPath/u_execute/EXALU/N810 ,
\u_DataPath/u_exmemreg/N78 , \u_DataPath/u_memwbreg/N64 , n2733,
\lte_x_59/B[28] , \lte_x_59/B[26] , \lte_x_59/B[24] ,
\lte_x_59/B[22] , \lte_x_59/B[21] , \lte_x_59/B[18] ,
\lte_x_59/B[16] , \lte_x_59/B[15] , \lte_x_59/B[14] , \lte_x_59/B[9] ,
\lte_x_59/B[8] , \lte_x_59/B[7] , \lte_x_59/B[6] , \lte_x_59/B[5] ,
\lte_x_59/B[4] , \lte_x_59/B[3] , \lte_x_59/B[1] , \sub_x_53/A[30] ,
\sub_x_53/A[29] , \sub_x_53/A[27] , \sub_x_53/A[25] ,
\sub_x_53/A[23] , \sub_x_53/A[20] , \sub_x_53/A[17] , \sub_x_53/A[2] ,
\sub_x_53/A[0] , n2773, n2774, n2776, n2778, n2780, n2782, n2784,
n2787, n2789, n2791, n2793, n2795, n2797, n2799, n2801, n2803, n2805,
n2807, n2809, n2811, n2813, n2815, n2817, n2819, n2821, n2823, n2825,
n2829, n2831, n2833, n2835, n2838, n2840, n2842, n2843, n2844, n2845,
n2846, n2847, n2848, n2849, n2851, n2853, n2854, n2855, n2856, n2857,
n2858, n2859, n2860, n2864, n2865, n2866, n2867, n2869, n2870, n2871,
n2872, n2873, n2874, n2875, n2876, n2877, n2878, n2879, n2880, n2881,
n2882, n2883, n2884, n2885, n2886, n2887, n2888, n2889, n2890, n2891,
n2892, n2893, n2894, n2895, n2896, n2897, n2898, n2899, n2900, n2901,
n2902, n2903, n2904, n2905, n2906, n2907, n2908, n2909, n2910, n2911,
n2912, n2913, n2914, n2915, n2916, n2917, n2918, n2919, n2920, n2921,
n2922, n2923, n2924, n2925, n2926, n2927, n2928, n2929, n2930, n2931,
n2932, n2933, n2934, n2935, n2936, n2937, n2938, n2939, n2940, n2941,
n2942, n2943, n2944, n2945, n2946, n2947, n2948, n2949, n2950, n2951,
n2952, n2953, n2954, n2956, n2957, n2958, n2959, n2960, n2961, n2962,
n2963, n2964, n2965, n2966, n2968, n2969, n2970, n2971, n2972, n2973,
n2974, n2975, n2976, n2977, n2978, n2979, n2980, n2981, n2982, n2983,
n2984, n2985, n2986, n2987, n2988, n2989, n2993, n2994, n2995, n2996,
n2998, n2999, n3000, n3001, n3002, n3003, n3004, n3005, n3006, n3007,
n3008, n3009, n3010, n3011, n3012, n3013, n3014, n3015, n3016, n3018,
n3020, n3021, n3022, n3023, n3024, n3025, n3028, n3029, n3030, n3031,
n3032, n3033, n3034, n3035, n3036, n3037, n3038, n3039, n3040, n3041,
n3042, n3043, n3044, n3045, n3047, n3048, n3049, n3050, n3051, n3052,
n3053, n3054, n3055, n3056, n3057, n3058, n3059, n3060, n3061, n3062,
n3063, n3064, n3066, n3067, n3068, n3069, n3070, n3072, n3073, n3074,
n3075, n3076, n3077, n3079, n3080, n3081, n3082, n3084, n3085, n3086,
n3088, n3089, n3090, n3091, n3093, n3094, n3095, n3096, n3098, n3099,
n3100, n3101, n3103, n3104, n3105, n3106, n3107, n3108, n3109, n3110,
n3111, n3112, n3113, n3114, n3115, n3116, n3118, n3119, n3120, n3121,
n3122, n3123, n3124, n3125, n3126, n3127, n3128, n3129, n3130, n3131,
n3132, n3133, n3134, n3135, n3137, n3138, n3139, n3140, n3141, n3142,
n3143, n3144, n3145, n3146, n3147, n3148, n3150, n3151, n3152, n3153,
n3154, n3155, n3156, n3157, n3158, n3159, n3160, n3161, n3162, n3163,
n3164, n3166, n3167, n3168, n3169, n3170, n3171, n3172, n3173, n3175,
n3176, n3177, n3178, n3179, n3180, n3181, n3182, n3183, n3185, n3186,
n3187, n3188, n3189, n3190, n3191, n3192, n3193, n3194, n3195, n3196,
n3197, n3198, n3199, n3200, n3201, n3202, n3203, n3204, n3205, n3206,
n3207, n3208, n3209, n3210, n3212, n3213, n3214, n3215, n3216, n3217,
n3218, n3219, n3221, n3222, n3223, n3224, n3225, n3226, n3227, n3228,
n3229, n3230, n3231, n3232, n3233, n3234, n3235, n3236, n3237, n3238,
n3239, n3240, n3241, n3242, n3243, n3244, n3245, n3246, n3248, n3249,
n3250, n3251, n3252, n3253, n3254, n3255, n3256, n3257, n3259, n3260,
n3261, n3262, n3263, n3264, n3265, n3266, n3267, n3269, n3270, n3271,
n3272, n3273, n3274, n3275, n3276, n3277, n3278, n3279, n3280, n3281,
n3282, n3283, n3284, n3285, n3286, n3287, n3288, n3289, n3290, n3291,
n3292, n3293, n3294, n3295, n3296, n3298, n3299, n3300, n3301, n3302,
n3303, n3304, n3305, n3306, n3307, n3308, n3309, n3310, n3311, n3312,
n3313, n3314, n3315, n3316, n3317, n3318, n3319, n3320, n3321, n3322,
n3323, n3324, n3325, n3327, n3328, n3329, n3330, n3331, n3332, n3333,
n3334, n3335, n3336, n3337, n3338, n3339, n3340, n3341, n3342, n3343,
n3344, n3345, n3346, n3347, n3348, n3349, n3351, n3352, n3353, n3354,
n3355, n3356, n3357, n3358, n3359, n3360, n3361, n3362, n3363, n3364,
n3365, n3366, n3367, n3368, n3369, n3370, n3371, n3372, n3373, n3374,
n3375, n3376, n3377, n3378, n3379, n3380, n3381, n3382, n3383, n3384,
n3385, n3386, n3387, n3388, n3389, n3390, n3391, n3392, n3393, n3394,
n3395, n3396, n3397, n3398, n3399, n3400, n3401, n3402, n3403, n3404,
n3406, n3407, n3408, n3409, n3410, n3411, n3412, n3413, n3414, n3415,
n3416, n3417, n3418, n3419, n3420, n3421, n3422, n3423, n3424, n3425,
n3426, n3427, n3428, n3429, n3430, n3431, n3432, n3433, n3434, n3435,
n3436, n3437, n3438, n3439, n3440, n3441, n3442, n3443, n3444, n3445,
n3446, n3447, n3448, n3449, n3450, n3451, n3452, n3453, n3454, n3455,
n3456, n3457, n3458, n3459, n3460, n3461, n3462, n3463, n3464, n3465,
n3466, n3467, n3468, n3469, n3470, n3471, n3472, n3473, n3474, n3475,
n3476, n3477, n3478, n3479, n3480, n3481, n3482, n3483, n3484, n3485,
n3486, n3487, n3488, n3489, n3490, n3491, n3492, n3493, n3494, n3495,
n3496, n3497, n3498, n3499, n3500, n3501, n3502, n3503, n3504, n3505,
n3506, n3507, n3508, n3509, n3510, n3511, n3512, n3513, n3514, n3515,
n3516, n3517, n3518, n3519, n3520, n3521, n3522, n3523, n3524, n3525,
n3526, n3527, n3528, n3529, n3530, n3531, n3532, n3533, n3534, n3535,
n3536, n3537, n3538, n3539, n3540, n3541, n3542, n3543, n3544, n3545,
n3546, n3547, n3548, n3549, n3550, n3551, n3552, n3553, n3554, n3555,
n3556, n3557, n3558, n3559, n3560, n3561, n3562, n3563, n3564, n3565,
n3566, n3567, n3568, n3569, n3570, n3571, n3572, n3573, n3574, n3575,
n3576, n3577, n3578, n3579, n3580, n3581, n3582, n3583, n3584, n3585,
n3586, n3587, n3588, n3589, n3590, n3591, n3592, n3593, n3594, n3595,
n3596, n3597, n3598, n3599, n3600, n3601, n3602, n3603, n3604, n3605,
n3606, n3607, n3608, n3609, n3610, n3611, n3612, n3613, n3614, n3615,
n3616, n3617, n3618, n3619, n3620, n3621, n3622, n3623, n3624, n3625,
n3626, n3627, n3628, n3629, n3630, n3631, n3632, n3633, n3634, n3635,
n3636, n3637, n3638, n3639, n3640, n3641, n3642, n3643, n3644, n3645,
n3646, n3647, n3648, n3649, n3650, n3651, n3652, n3653, n3654, n3655,
n3656, n3657, n3658, n3659, n3660, n3661, n3662, n3663, n3664, n3665,
n3666, n3667, n3668, n3669, n3670, n3671, n3672, n3673, n3674, n3675,
n3676, n3677, n3678, n3679, n3680, n3681, n3682, n3683, n3684, n3685,
n3686, n3687, n3688, n3689, n3690, n3691, n3692, n3693, n3694, n3695,
n3696, n3697, n3698, n3699, n3700, n3701, n3702, n3703, n3704, n3705,
n3706, n3707, n3708, n3709, n3710, n3711, n3712, n3713, n3714, n3715,
n3716, n3717, n3718, n3719, n3720, n3721, n3722, n3723, n3724, n3725,
n3726, n3727, n3728, n3729, n3730, n3731, n3732, n3733, n3734, n3735,
n3736, n3737, n3738, n3739, n3740, n3741, n3742, n3743, n3744, n3745,
n3746, n3747, n3748, n3749, n3750, n3751, n3752, n3753, n3754, n3755,
n3756, n3757, n3758, n3759, n3760, n3761, n3762, n3763, n3764, n3765,
n3766, n3767, n3768, n3769, n3770, n3771, n3772, n3773, n3774, n3775,
n3776, n3777, n3778, n3779, n3780, n3781, n3782, n3783, n3784, n3785,
n3786, n3787, n3788, n3789, n3790, n3791, n3792, n3793, n3794, n3795,
n3796, n3797, n3798, n3799, n3800, n3801, n3802, n3803, n3804, n3805,
n3806, n3807, n3808, n3809, n3810, n3811, n3812, n3813, n3814, n3815,
n3816, n3817, n3818, n3819, n3820, n3821, n3822, n3823, n3824, n3825,
n3826, n3827, n3828, n3829, n3830, n3831, n3832, n3833, n3834, n3835,
n3836, n3837, n3838, n3839, n3840, n3841, n3842, n3843, n3844, n3845,
n3846, n3847, n3848, n3849, n3850, n3851, n3852, n3853, n3854, n3855,
n3856, n3857, n3858, n3859, n3860, n3861, n3862, n3863, n3864, n3865,
n3866, n3867, n3868, n3869, n3870, n3871, n3872, n3873, n3874, n3875,
n3876, n3877, n3878, n3879, n3880, n3881, n3882, n3883, n3884, n3885,
n3886, n3887, n3888, n3889, n3890, n3891, n3892, n3893, n3894, n3895,
n3896, n3897, n3898, n3899, n3902, n3903, n3904, n3905, n3906, n3907,
n3908, n3909, n3910, n3911, n3912, n3913, n3914, n3915, n3916, n3917,
n3918, n3919, n3920, n3921, n3922, n3923, n3924, n3925, n3926, n3927,
n3928, n3929, n3930, n3931, n3932, n3933, n3934, n3935, n3936, n3937,
n3938, n3939, n3940, n3941, n3942, n3943, n3944, n3945, n3946, n3947,
n3948, n3949, n3950, n3951, n3952, n3953, n3954, n3955, n3956, n3957,
n3958, n3959, n3960, n3961, n3962, n3963, n3964, n3965, n3966, n3967,
n3968, n3969, n3970, n3971, n3972, n3973, n3974, n3975, n3976, n3977,
n3978, n3979, n3980, n3981, n3982, n3983, n3984, n3985, n3986, n3987,
n3988, n3989, n3990, n3991, n3992, n3993, n3994, n3995, n3996, n3997,
n3998, n3999, n4000, n4001, n4002, n4003, n4004, n4005, n4006, n4007,
n4008, n4009, n4010, n4011, n4012, n4013, n4014, n4015, n4016, n4017,
n4018, n4019, n4020, n4021, n4022, n4023, n4024, n4025, n4026, n4027,
n4028, n4029, n4030, n4031, n4032, n4033, n4034, n4035, n4036, n4037,
n4038, n4039, n4040, n4041, n4042, n4043, n4044, n4045, n4046, n4047,
n4048, n4049, n4050, n4051, n4052, n4053, n4054, n4055, n4056, n4057,
n4058, n4059, n4060, n4061, n4062, n4063, n4064, n4065, n4066, n4067,
n4068, n4069, n4070, n4071, n4072, n4073, n4074, n4075, n4076, n4077,
n4078, n4079, n4080, n4081, n4082, n4083, n4084, n4085, n4086, n4087,
n4088, n4089, n4090, n4091, n4092, n4093, n4094, n4095, n4096, n4097,
n4098, n4099, n4100, n4101, n4102, n4103, n4104, n4105, n4106, n4107,
n4108, n4109, n4110, n4111, n4113, n4114, n4115, n4116, n4117, n4118,
n4119, n4120, n4121, n4122, n4123, n4124, n4125, n4126, n4128, n4129,
n4130, n4131, n4132, n4133, n4134, n4135, n4136, n4137, n4138, n4139,
n4140, n4141, n4142, n4143, n4144, n4145, n4146, n4147, n4148, n4149,
n4150, n4151, n4152, n4153, n4154, n4155, n4156, n4157, n4158, n4159,
n4160, n4161, n4162, n4163, n4164, n4165, n4166, n4167, n4168, n4169,
n4170, n4171, n4172, n4173, n4174, n4175, n4176, n4177, n4178, n4179,
n4180, n4181, n4182, n4183, n4184, n4185, n4186, n4187, n4188, n4189,
n4190, n4191, n4192, n4193, n4194, n4195, n4196, n4197, n4198, n4199,
n4200, n4201, n4202, n4203, n4204, n4205, n4206, n4207, n4208, n4209,
n4210, n4211, n4212, n4213, n4214, n4215, n4216, n4217, n4218, n4219,
n4220, n4221, n4222, n4223, n4224, n4225, n4226, n4227, n4228, n4229,
n4230, n4231, n4232, n4233, n4234, n4235, n4236, n4237, n4238, n4239,
n4240, n4241, n4242, n4243, n4244, n4245, n4246, n4247, n4248, n4249,
n4250, n4251, n4252, n4253, n4254, n4255, n4256, n4257, n4258, n4259,
n4260, n4261, n4262, n4263, n4264, n4265, n4266, n4267, n4268, n4269,
n4270, n4271, n4272, n4273, n4274, n4275, n4276, n4277, n4278, n4279,
n4280, n4281, n4282, n4283, n4284, n4285, n4286, n4287, n4288, n4289,
n4290, n4291, n4292, n4293, n4294, n4295, n4296, n4297, n4298, n4299,
n4300, n4301, n4302, n4303, n4304, n4305, n4306, n4307, n4308, n4309,
n4310, n4311, n4312, n4313, n4314, n4315, n4316, n4317, n4318, n4319,
n4320, n4321, n4322, n4323, n4324, n4325, n4326, n4327, n4328, n4329,
n4330, n4331, n4332, n4333, n4334, n4335, n4336, n4337, n4338, n4339,
n4340, n4341, n4342, n4343, n4344, n4345, n4346, n4347, n4348, n4349,
n4350, n4351, n4352, n4353, n4354, n4355, n4356, n4357, n4358, n4359,
n4360, n4361, n4362, n4363, n4364, n4365, n4366, n4367, n4368, n4369,
n4370, n4371, n4372, n4373, n4374, n4375, n4376, n4377, n4378, n4379,
n4380, n4381, n4382, n4383, n4384, n4385, n4386, n4387, n4388, n4389,
n4390, n4391, n4392, n4393, n4394, n4395, n4396, n4397, n4398, n4399,
n4400, n4401, n4402, n4403, n4404, n4405, n4406, n4407, n4408, n4409,
n4410, n4411, n4412, n4413, n4414, n4415, n4416, n4417, n4418, n4419,
n4420, n4421, n4422, n4423, n4424, n4425, n4426, n4427, n4428, n4429,
n4430, n4431, n4432, n4433, n4434, n4435, n4436, n4437, n4438, n4439,
n4440, n4441, n4442, n4443, n4444, n4445, n4446, n4447, n4448, n4449,
n4450, n4451, n4452, n4453, n4454, n4455, n4456, n4457, n4458, n4459,
n4460, n4461, n4462, n4463, n4464, n4465, n4466, n4467, n4468, n4469,
n4470, n4471, n4472, n4473, n4474, n4475, n4476, n4477, n4478, n4479,
n4480, n4481, n4482, n4483, n4484, n4485, n4486, n4487, n4488, n4489,
n4490, n4491, n4492, n4493, n4494, n4495, n4496, n4497, n4498, n4499,
n4500, n4501, n4502, n4503, n4504, n4505, n4506, n4507, n4508, n4509,
n4510, n4511, n4512, n4513, n4514, n4515, n4516, n4517, n4518, n4519,
n4520, n4521, n4522, n4523, n4524, n4525, n4526, n4527, n4528, n4529,
n4530, n4531, n4532, n4533, n4534, n4535, n4536, n4537, n4538, n4539,
n4540, n4541, n4542, n4543, n4544, n4545, n4546, n4547, n4548, n4549,
n4550, n4551, n4552, n4553, n4554, n4555, n4556, n4557, n4558, n4559,
n4560, n4561, n4562, n4563, n4564, n4565, n4566, n4567, n4568, n4569,
n4570, n4571, n4572, n4573, n4574, n4575, n4576, n4577, n4578, n4579,
n4580, n4581, n4582, n4583, n4584, n4585, n4586, n4587, n4588, n4589,
n4590, n4591, n4592, n4593, n4594, n4595, n4596, n4597, n4598, n4599,
n4600, n4601, n4602, n4603, n4604, n4605, n4606, n4607, n4608, n4609,
n4610, n4611, n4612, n4613, n4614, n4615, n4616, n4617, n4618, n4619,
n4620, n4621, n4622, n4623, n4624, n4625, n4626, n4627, n4628, n4629,
n4630, n4631, n4632, n4633, n4634, n4635, n4636, n4637, n4638, n4639,
n4640, n4641, n4642, n4643, n4644, n4645, n4646, n4647, n4648, n4649,
n4650, n4651, n4652, n4653, n4654, n4655, n4656, n4657, n4658, n4659,
n4660, n4661, n4662, n4663, n4664, n4665, n4666, n4667, n4668, n4669,
n4670, n4671, n4672, n4673, n4674, n4675, n4676, n4677, n4678, n4679,
n4680, n4681, n4682, n4683, n4684, n4685, n4686, n4687, n4688, n4689,
n4690, n4691, n4692, n4693, n4694, n4695, n4696, n4697, n4698, n4699,
n4700, n4701, n4702, n4703, n4704, n4705, n4706, n4707, n4708, n4709,
n4710, n4711, n4712, n4713, n4714, n4715, n4716, n4717, n4718, n4719,
n4720, n4721, n4722, n4723, n4724, n4725, n4726, n4727, n4728, n4729,
n4730, n4731, n4732, n4733, n4734, n4735, n4736, n4737, n4738, n4739,
n4740, n4741, n4742, n4743, n4744, n4745, n4746, n4747, n4748, n4749,
n4750, n4751, n4752, n4753, n4754, n4755, n4756, n4757, n4758, n4759,
n4760, n4761, n4762, n4763, n4764, n4765, n4766, n4767, n4768, n4769,
n4770, n4771, n4772, n4773, n4774, n4775, n4776, n4777, n4778, n4779,
n4780, n4781, n4782, n4783, n4784, n4785, n4786, n4787, n4788, n4789,
n4790, n4791, n4792, n4793, n4794, n4795, n4796, n4797, n4798, n4799,
n4800, n4801, n4802, n4803, n4804, n4805, n4806, n4807, n4808, n4809,
n4810, n4811, n4812, n4813, n4814, n4815, n4816, n4817, n4818, n4819,
n4820, n4821, n4823, n4824, n4825, n4826, n4827, n4829, n4830, n4831,
n4832, n4833, n4834, n4835, n4836, n4837, n4838, n4839, n4840, n4841,
n4842, n4843, n4844, n4845, n4846, n4847, n4848, n4849, n4850, n4851,
n4852, n4853, n4854, n4855, n4856, n4857, n4858, n4859, n4860, n4861,
n4862, n4863, n4864, n4865, n4866, n4867, n4868, n4869, n4870, n4871,
n4872, n4873, n4874, n4875, n4876, n4877, n4878, n4879, n4880, n4881,
n4882, n4883, n4884, n4885, n4886, n4887, n4888, n4889, n4890, n4891,
n4892, n4893, n4894, n4895, n4896, n4897, n4898, n4899, n4900, n4901,
n4902, n4903, n4904, n4905, n4906, n4907, n4908, n4909, n4910, n4911,
n4912, n4913, n4914, n4915, n4916, n4917, n4918, n4919, n4920, n4921,
n4922, n4923, n4924, n4925, n4926, n4927, n4928, n4929, n4930, n4931,
n4932, n4933, n4934, n4935, n4936, n4937, n4938, n4939, n4940, n4941,
n4942, n4943, n4944, n4945, n4946, n4947, n4948, n4949, n4950, n4951,
n4952, n4953, n4954, n4955, n4956, n4957, n4958, n4959, n4960, n4961,
n4962, n4963, n4964, n4965, n4966, n4967, n4968, n4969, n4970, n4971,
n4972, n4973, n4974, n4975, n4976, n4977, n4978, n4979, n4980, n4981,
n4982, n4983, n4984, n4985, n4986, n4987, n4988, n4989, n4990, n4991,
n4992, n4993, n4994, n4995, n4996, n4997, n4998, n4999, n5000, n5001,
n5002, n5003, n5004, n5005, n5006, n5007, n5008, n5009, n5010, n5011,
n5012, n5013, n5014, n5015, n5016, n5017, n5018, n5019, n5020, n5021,
n5022, n5023, n5024, n5025, n5026, n5027, n5028, n5029, n5030, n5031,
n5032, n5033, n5034, n5035, n5036, n5037, n5038, n5039, n5040, n5041,
n5042, n5043, n5044, n5045, n5046, n5047, n5048, n5049, n5050, n5051,
n5052, n5053, n5054, n5055, n5056, n5057, n5058, n5059, n5060, n5061,
n5062, n5063, n5064, n5065, n5066, n5067, n5068, n5069, n5070, n5071,
n5072, n5073, n5074, n5075, n5076, n5077, n5078, n5079, n5080, n5081,
n5082, n5083, n5084, n5085, n5086, n5087, n5088, n5089, n5090, n5091,
n5092, n5093, n5094, n5095, n5096, n5097, n5098, n5099, n5100, n5101,
n5102, n5103, n5104, n5105, n5106, n5107, n5108, n5109, n5110, n5111,
n5112, n5113, n5114, n5115, n5116, n5117, n5118, n5119, n5120, n5121,
n5122, n5123, n5124, n5125, n5126, n5127, n5128, n5129, n5130, n5131,
n5132, n5133, n5134, n5135, n5136, n5137, n5138, n5139, n5140, n5141,
n5142, n5143, n5144, n5145, n5146, n5147, n5148, n5149, n5150, n5151,
n5152, n5153, n5154, n5155, n5156, n5157, n5158, n5159, n5160, n5161,
n5162, n5163, n5164, n5165, n5166, n5167, n5168, n5169, n5170, n5171,
n5172, n5173, n5174, n5175, n5176, n5177, n5178, n5179, n5180, n5181,
n5182, n5183, n5184, n5185, n5186, n5187, n5188, n5189, n5190, n5191,
n5192, n5193, n5194, n5195, n5196, n5197, n5198, n5199, n5200, n5201,
n5202, n5203, n5204, n5205, n5206, n5207, n5208, n5209, n5210, n5211,
n5212, n5213, n5214, n5215, n5216, n5217, n5218, n5219, n5220, n5221,
n5222, n5224, n5225, n5226, n5227, n5228, n5229, n5231, n5232, n5233,
n5234, n5235, n5236, n5237, n5238, n5239, n5240, n5241, n5242, n5243,
n5244, n5245, n5246, n5247, n5248, n5249, n5250, n5251, n5252, n5253,
n5254, n5255, n5256, n5257, n5258, n5259, n5260, n5261, n5262, n5263,
n5264, n5265, n5266, n5267, n5268, n5269, n5270, n5271, n5272, n5273,
n5274, n5275, n5276, n5277, n5278, n5279, n5280, n5281, n5282, n5283,
n5284, n5285, n5286, n5287, n5288, n5289, n5290, n5291, n5292, n5293,
n5294, n5295, n5296, n5297, n5298, n5299, n5300, n5301, n5302, n5303,
n5304, n5305, n5306, n5307, n5308, n5309, n5310, n5311, n5312, n5313,
n5314, n5315, n5316, n5317, n5318, n5319, n5320, n5321, n5322, n5323,
n5324, n5325, n5326, n5327, n5328, n5329, n5330, n5331, n5332, n5333,
n5334, n5335, n5336, n5337, n5338, n5339, n5340, n5341, n5342, n5343,
n5344, n5345, n5346, n5347, n5348, n5349, n5350, n5351, n5352, n5353,
n5354, n5355, n5356, n5357, n5358, n5359, n5360, n5361, n5362, n5363,
n5364, n5365, n5366, n5367, n5368, n5369, n5370, n5371, n5372, n5373,
n5374, n5375, n5376, n5377, n5378, n5379, n5380, n5381, n5382, n5383,
n5384, n5385, n5386, n5387, n5388, n5389, n5390, n5391, n5392, n5393,
n5394, n5395, n5396, n5397, n5398, n5399, n5400, n5401, n5402, n5403,
n5404, n5405, n5406, n5407, n5408, n5409, n5410, n5411, n5412, n5413,
n5414, n5415, n5416, n5417, n5418, n5419, n5420, n5421, n5422, n5423,
n5424, n5425, n5426, n5427, n5428, n5429, n5430, n5431, n5432, n5433,
n5434, n5435, n5436, n5437, n5438, n5439, n5440, n5441, n5442, n5443,
n5444, n5445, n5446, n5447, n5448, n5449, n5450, n5451, n5452, n5453,
n5454, n5455, n5456, n5457, n5458, n5459, n5460, n5461, n5462, n5463,
n5464, n5465, n5466, n5467, n5468, n5469, n5470, n5471, n5472, n5473,
n5474, n5475, n5476, n5477, n5478, n5479, n5480, n5481, n5482, n5483,
n5484, n5485, n5486, n5487, n5488, n5489, n5490, n5491, n5492, n5493,
n5494, n5495, n5496, n5497, n5498, n5499, n5500, n5501, n5502, n5503,
n5504, n5505, n5506, n5507, n5508, n5509, n5510, n5511, n5512, n5513,
n5514, n5515, n5516, n5517, n5518, n5519, n5520, n5521, n5522, n5523,
n5524, n5525, n5526, n5527, n5528, n5529, n5530, n5531, n5532, n5533,
n5534, n5535, n5536, n5537, n5538, n5539, n5540, n5541, n5542, n5543,
n5544, n5545, n5546, n5547, n5548, n5549, n5550, n5551, n5552, n5553,
n5554, n5555, n5556, n5557, n5558, n5559, n5560, n5561, n5562, n5563,
n5564, n5565, n5566, n5567, n5568, n5569, n5570, n5571, n5572, n5573,
n5574, n5575, n5576, n5577, n5578, n5579, n5580, n5581, n5582, n5583,
n5584, n5585, n5586, n5587, n5588, n5589, n5590, n5591, n5592, n5593,
n5594, n5595, n5596, n5597, n5598, n5599, n5600, n5601, n5602, n5603,
n5604, n5605, n5606, n5607, n5608, n5609, n5610, n5611, n5612, n5613,
n5614, n5615, n5616, n5617, n5618, n5619, n5620, n5621, n5622, n5623,
n5624, n5625, n5626, n5627, n5628, n5629, n5630, n5631, n5632, n5633,
n5634, n5635, n5636, n5637, n5638, n5639, n5640, n5641, n5642, n5643,
n5644, n5645, n5646, n5647, n5648, n5649, n5651, n5652, n5653, n5654,
n5655, n5656, n5657, n5658, n5659, n5660, n5661, n5662, n5663, n5664,
n5665, n5666, n5667, n5668, n5669, n5670, n5671, n5672, n5673, n5674,
n5675, n5676, n5677, n5678, n5679, n5680, n5681, n5682, n5683, n5684,
n5685, n5686, n5687, n5688, n5689, n5690, n5691, n5692, n5693, n5694,
n5695, n5696, n5697, n5698, n5699, n5700, n5701, n5702, n5703, n5704,
n5705, n5706, n5707, n5708, n5709, n5710, n5711, n5712, n5713, n5714,
n5715, n5716, n5717, n5718, n5719, n5720, n5721, n5722, n5723, n5724,
n5725, n5726, n5727, n5728, n5729, n5730, n5731, n5732, n5733, n5734,
n5735, n5736, n5737, n5738, n5739, n5740, n5741, n5742, n5743, n5744,
n5745, n5746, n5747, n5748, n5749, n5750, n5751, n5752, n5753, n5755,
n5756, n5757, n5758, n5759, n5760, n5761, n5762, n5763, n5764, n5765,
n5766, n5767, n5768, n5769, n5770, n5771, n5772, n5773, n5774, n5775,
n5777, n5778, n5779, n5780, n5781, n5782, n5784, n5785, n5786, n5787,
n5788, n5789, n5790, n5791, n5793, n5794, n5795, n5796, n5797, n5798,
n5799, n5800, n5801, n5802, n5803, n5804, n5805, n5806, n5807, n5808,
n5809, n5810, n5811, n5812, n5813, n5814, n5815, n5816, n5817, n5818,
n5819, n5820, n5821, n5822, n5823, n5824, n5825, n5826, n5827, n5828,
n5830, n5831, n5832, n5833, n5834, n5835, n5836, n5837, n5838, n5839,
n5841, n5842, n5844, n5845, n5846, n5848, n5849, n5850, n5851, n5852,
n5853, n5854, n5855, n5856, n5857, n5858, n5859, n5860, n5861, n5863,
n5864, n5865, n5866, n5867, n5868, n5869, n5871, n5872, n5873, n5874,
n5875, n5876, n5877, n5878, n5879, n5880, n5881, n5882, n5883, n5884,
n5885, n5886, n5887, n5888, n5889, n5890, n5891, n5892, n5893, n5894,
n5896, n5897, n5898, n5899, n5900, n5901, n5902, n5903, n5904, n5905,
n5906, n5907, n5908, n5909, n5910, n5911, n5912, n5913, n5914, n5915,
n5916, n5917, n5918, n5919, n5920, n5921, n5922, n5923, n5924, n5925,
n5926, n5927, n5928, n5929, n5930, n5931, n5932, n5933, n5934, n5935,
n5936, n5937, n5938, n5939, n5940, n5941, n5942, n5943, n5944, n5945,
n5946, n5947, n5948, n5949, n5950, n5951, n5952, n5953, n5954, n5955,
n5956, n5957, n5958, n5959, n5960, n5961, n5962, n5963, n5964, n5965,
n5966, n5967, n5969, n5970, n5971, n5972, n5973, n5974, n5975, n5976,
n5977, n5978, n5979, n5980, n5981, n5982, n5983, n5984, n5985, n5986,
n5987, n5989, n5990, n5992, n5993, n5994, n5995, n5996, n5997, n5998,
n5999, n6000, n6001, n6002, n6003, n6004, n6005, n6006, n6007, n6008,
n6009, n6010, n6011, n6012, n6013, n6014, n6015, n6016, n6017, n6018,
n6019, n6020, n6021, n6022, n6023, n6024, n6025, n6026, n6027, n6028,
n6029, n6030, n6031, n6032, n6034, n6035, n6036, n6037, n6038, n6040,
n6041, n6042, n6043, n6044, n6045, n6046, n6047, n6048, n6049, n6050,
n6051, n6052, n6053, n6054, n6055, n6056, n6057, n6058, n6059, n6060,
n6061, n6062, n6063, n6064, n6065, n6066, n6067, n6068, n6069, n6070,
n6071, n6072, n6073, n6075, n6076, n6077, n6078, n6079, n6080, n6081,
n6082, n6083, n6084, n6085, n6087, n6088, n6089, n6090, n6091, n6092,
n6094, n6095, n6096, n6097, n6098, n6099, n6100, n6101, n6102, n6103,
n6104, n6105, n6106, n6107, n6108, n6109, n6110, n6111, n6112, n6113,
n6114, n6115, n6116, n6117, n6118, n6119, n6120, n6121, n6122, n6123,
n6124, n6125, n6126, n6127, n6128, n6129, n6130, n6131, n6132, n6133,
n6134, n6135, n6136, n6137, n6138, n6139, n6140, n6141, n6142, n6143,
n6144, n6145, n6146, n6147, n6148, n6149, n6150, n6151, n6152, n6153,
n6154, n6155, n6156, n6157, n6158, n6159, n6160, n6161, n6162, n6163,
n6164, n6165, n6166, n6167, n6168, n6169, n6170, n6171, n6172, n6173,
n6174, n6175, n6176, n6177, n6178, n6179, n6180, n6181, n6182, n6183,
n6184, n6185, n6186, n6187, n6188, n6189, n6190, n6191, n6192, n6193,
n6194, n6195, n6196, n6197, n6198, n6199, n6200, n6201, n6202, n6203,
n6204, n6205, n6206, n6207, n6208, n6209, n6210, n6211, n6212, n6213,
n6214, n6215, n6216, n6217, n6218, n6219, n6220, n6221, n6222, n6223,
n6224, n6225, n6226, n6227, n6228, n6229, n6230, n6231, n6232, n6233,
n6234, n6235, n6236, n6237, n6238, n6239, n6240, n6241, n6242, n6243,
n6244, n6245, n6246, n6247, n6248, n6249, n6250, n6251, n6252, n6253,
n6254, n6255, n6256, n6257, n6258, n6259, n6260, n6261, n6262, n6263,
n6264, n6265, n6266, n6267, n6268, n6269, n6270, n6271, n6272, n6273,
n6274, n6275, n6276, n6277, n6278, n6279, n6280, n6281, n6282, n6283,
n6284, n6285, n6286, n6287, n6288, n6289, n6290, n6291, n6292, n6293,
n6294, n6295, n6296, n6297, n6298, n6299, n6300, n6301, n6302, n6303,
n6304, n6305, n6306, n6307, n6308, n6309, n6310, n6311, n6312, n6313,
n6314, n6315, n6316, n6317, n6318, n6319, n6320, n6321, n6322, n6323,
n6324, n6325, n6326, n6327, n6328, n6329, n6330, n6331, n6332, n6333,
n6334, n6335, n6336, n6337, n6338, n6339, n6340, n6341, n6342, n6343,
n6344, n6345, n6346, n6347, n6348, n6349, n6350, n6351, n6352, n6353,
n6354, n6355, n6356, n6357, n6358, n6359, n6360, n6361, n6362, n6363,
n6364, n6366, n6367, n6368, n6369, n6370, n6371, n6372, n6373, n6374,
n6375, n6376, n6377, n6378, n6379, n6380, n6381, n6382, n6383, n6384,
n6385, n6386, n6387, n6388, n6389, n6390, n6391, n6392, n6393, n6394,
n6395, n6396, n6397, n6398, n6399, n6400, n6401, n6402, n6403, n6404,
n6405, n6406, n6407, n6408, n6409, n6410, n6411, n6412, n6413, n6414,
n6415, n6416, n6417, n6418, n6419, n6420, n6421, n6422, n6423, n6424,
n6425, n6426, n6427, n6428, n6429, n6430, n6431, n6432, n6433, n6434,
n6435, n6436, n6437, n6438, n6439, n6440, n6441, n6442, n6443, n6444,
n6445, n6446, n6447, n6448, n6449, n6450, n6451, n6452, n6453, n6454,
n6455, n6456, n6457, n6458, n6459, n6460, n6461, n6462, n6463, n6464,
n6465, n6466, n6467, n6468, n6469, n6470, n6471, n6472, n6473, n6474,
n6475, n6476, n6477, n6478, n6479, n6480, n6481, n6482, n6483, n6484,
n6485, n6486, n6487, n6488, n6489, n6490, n6491, n6492, n6493, n6494,
n6495, n6496, n6497, n6498, n6499, n6500, n6501, n6502, n6503, n6504,
n6505, n6506, n6507, n6508, n6509, n6510, n6511, n6512, n6513, n6514,
n6515, n6516, n6517, n6518, n6519, n6520, n6521, n6522, n6523, n6524,
n6525, n6526, n6527, n6528, n6529, n6530, n6531, n6532, n6533, n6534,
n6535, n6536, n6537, n6538, n6539, n6540, n6541, n6542, n6543, n6544,
n6545, n6546, n6547, n6548, n6549, n6550, n6551, n6552, n6553, n6554,
n6555, n6556, n6557, n6558, n6559, n6560, n6561, n6562, n6563, n6564,
n6565, n6566, n6567, n6568, n6569, n6570, n6571, n6572, n6573, n6574,
n6575, n6576, n6577, n6578, n6579, n6580, n6581, n6582, n6583, n6584,
n6585, n6586, n6587, n6588, n6589, n6590, n6591, n6592, n6593, n6594,
n6595, n6596, n6597, n6598, n6599, n6600, n6601, n6602, n6603, n6604,
n6605, n6606, n6607, n6608, n6609, n6610, n6611, n6612, n6613, n6614,
n6615, n6616, n6617, n6618, n6619, n6620, n6621, n6622, n6623, n6624,
n6625, n6626, n6627, n6628, n6629, n6630, n6631, n6632, n6633, n6634,
n6635, n6636, n6637, n6638, n6639, n6640, n6641, n6642, n6643, n6644,
n6645, n6646, n6647, n6648, n6649, n6650, n6651, n6652, n6653, n6654,
n6655, n6656, n6657, n6658, n6659, n6660, n6661, n6662, n6663, n6664,
n6665, n6666, n6667, n6668, n6669, n6670, n6671, n6672, n6673, n6674,
n6675, n6676, n6677, n6678, n6679, n6680, n6681, n6682, n6683, n6684,
n6685, n6686, n6687, n6688, n6689, n6690, n6691, n6692, n6693, n6694,
n6695, n6696, n6697, n6698, n6699, n6700, n6701, n6702, n6703, n6704,
n6705, n6706, n6707, n6708, n6709, n6710, n6711, n6712, n6713, n6714,
n6715, n6716, n6717, n6718, n6719, n6720, n6721, n6722, n6723, n6724,
n6725, n6726, n6727, n6728, n6729, n6730, n6731, n6732, n6733, n6734,
n6735, n6736, n6737, n6738, n6739, n6740, n6741, n6742, n6743, n6744,
n6745, n6746, n6747, n6748, n6749, n6750, n6751, n6752, n6753, n6754,
n6755, n6756, n6757, n6758, n6759, n6760, n6761, n6762, n6763, n6764,
n6765, n6766, n6767, n6768, n6769, n6770, n6771, n6772, n6773, n6774,
n6775, n6776, n6777, n6778, n6779, n6780, n6781, n6782, n6783, n6784,
n6785, n6786, n6787, n6788, n6789, n6790, n6791, n6792, n6793, n6794,
n6795, n6796, n6797, n6798, n6799, n6800, n6801, n6802, n6803, n6804,
n6805, n6806, n6807, n6808, n6809, n6810, n6811, n6812, n6813, n6814,
n6815, n6816, n6817, n6818, n6819, n6820, n6821, n6822, n6823, n6824,
n6825, n6826, n6827, n6828, n6829, n6830, n6831, n6832, n6833, n6834,
n6835, n6836, n6837, n6838, n6839, n6840, n6841, n6842, n6843, n6844,
n6845, n6846, n6847, n6848, n6849, n6850, n6851, n6852, n6853, n6854,
n6855, n6856, n6857, n6858, n6859, n6860, n6861, n6862, n6863, n6864,
n6865, n6866, n6867, n6868, n6869, n6870, n6871, n6872, n6873, n6874,
n6875, n6876, n6877, n6878, n6879, n6880, n6881, n6882, n6883, n6884,
n6885, n6886, n6887, n6888, n6889, n6890, n6891, n6892, n6893, n6894,
n6895, n6896, n6897, n6898, n6899, n6900, n6901, n6902, n6903, n6904,
n6905, n6906, n6907, n6908, n6909, n6910, n6911, n6912, n6913, n6914,
n6915, n6916, n6917, n6918, n6919, n6920, n6921, n6922, n6923, n6924,
n6925, n6926, n6927, n6929, n6930, n6931, n6932, n6933, n6934, n6935,
n6936, n6937, n6938, n6939, n6940, n6941, n6942, n6943, n6944, n6945,
n6946, n6947, n6948, n6949, n6950, n6951, n6952, n6953, n6954, n6955,
n6956, n6957, n6958, n6959, n6960, n6961, n6962, n6963, n6964, n6965,
n6966, n6967, n6968, n6969, n6970, n6971, n6972, n6973, n6974, n6975,
n6976, n6977, n6978, n6979, n6980, n6981, n6982, n6983, n6984, n6985,
n6986, n6987, n6988, n6989, n6990, n6991, n6992, n6993, n6994, n6995,
n6996, n6997, n6998, n6999, n7000, n7001, n7002, n7003, n7004, n7005,
n7006, n7007, n7008, n7009, n7010, n7011, n7012, n7013, n7014, n7015,
n7016, n7017, n7018, n7019, n7020, n7021, n7022, n7023, n7024, n7025,
n7026, n7027, n7028, n7029, n7030, n7031, n7032, n7033, n7034, n7035,
n7036, n7037, n7038, n7039, n7040, n7041, n7042, n7043, n7044, n7045,
n7046, n7047, n7048, n7049, n7050, n7051, n7052, n7053, n7054, n7055,
n7056, n7057, n7058, n7059, n7060, n7061, n7062, n7063, n7064, n7065,
n7066, n7067, n7068, n7069, n7070, n7071, n7072, n7073, n7074, n7075,
n7076, n7077, n7078, n7079, n7080, n7081, n7082, n7083, n7084, n7085,
n7086, n7087, n7088, n7089, n7090, n7091, n7092, n7093, n7094, n7095,
n7096, n7097, n7098, n7099, n7100, n7101, n7102, n7103, n7104, n7105,
n7106, n7107, n7108, n7109, n7110, n7111, n7112, n7113, n7114, n7115,
n7116, n7117, n7118, n7119, n7120, n7121, n7122, n7123, n7124, n7125,
n7126, n7127, n7128, n7129, n7130, n7131, n7132, n7133, n7134, n7135,
n7136, n7137, n7138, n7139, n7140, n7141, n7142, n7143, n7144, n7145,
n7146, n7147, n7148, n7149, n7150, n7151, n7152, n7153, n7154, n7155,
n7156, n7157, n7158, n7159, n7160, n7161, n7162, n7163, n7164, n7165,
n7166, n7167, n7168, n7169, n7170, n7171, n7172, n7173, n7174, n7175,
n7176, n7177, n7178, n7179, n7180, n7181, n7182, n7183, n7184, n7185,
n7186, n7187, n7188, n7189, n7190, n7191, n7192, n7193, n7194, n7195,
n7196, n7197, n7198, n7199, n7200, n7201, n7202, n7203, n7204, n7205,
n7206, n7207, n7208, n7209, n7210, n7211, n7212, n7213, n7214, n7215,
n7216, n7217, n7218, n7219, n7220, n7221, n7222, n7223, n7224, n7225,
n7226, n7227, n7228, n7229, n7230, n7231, n7232, n7233, n7234, n7235,
n7236, n7237, n7238, n7239, n7240, n7241, n7242, n7243, n7244, n7245,
n7246, n7247, n7248, n7249, n7250, n7251, n7252, n7253, n7254, n7255,
n7256, n7257, n7258, n7259, n7260, n7261, n7262, n7263, n7264, n7265,
n7266, n7267, n7268, n7269, n7270, n7271, n7272, n7273, n7274, n7275,
n7276, n7277, n7278, n7279, n7280, n7281, n7282, n7283, n7284, n7285,
n7286, n7287, n7288, n7289, n7290, n7291, n7292, n7293, n7294, n7295,
n7296, n7297, n7298, n7299, n7300, n7301, n7302, n7303, n7304, n7305,
n7306, n7307, n7308, n7309, n7310, n7311, n7312, n7313, n7314, n7315,
n7316, n7317, n7318, n7319, n7320, n7321, n7322, n7323, n7324, n7325,
n7326, n7327, n7328, n7329, n7330, n7331, n7332, n7333, n7334, n7335,
n7336, n7337, n7338, n7339, n7340, n7341, n7342, n7343, n7344, n7345,
n7346, n7347, n7348, n7349, n7350, n7351, n7352, n7353, n7354, n7355,
n7356, n7357, n7358, n7359, n7360, n7361, n7362, n7363, n7364, n7365,
n7366, n7367, n7368, n7369, n7370, n7371, n7372, n7373, n7374, n7375,
n7376, n7377, n7378, n7379, n7380, n7381, n7382, n7383, n7384, n7385,
n7386, n7387, n7388, n7389, n7390, n7391, n7392, n7393, n7394, n7395,
n7396, n7397, n7398, n7399, n7400, n7401, n7402, n7403, n7404, n7405,
n7406, n7407, n7408, n7409, n7410, n7411, n7412, n7413, n7414, n7415,
n7416, n7417, n7418, n7419, n7420, n7421, n7422, n7423, n7424, n7425,
n7426, n7427, n7428, n7429, n7430, n7431, n7432, n7433, n7434, n7435,
n7436, n7437, n7438, n7439, n7440, n7441, n7442, n7443, n7444, n7445,
n7446, n7447, n7448, n7449, n7450, n7451, n7452, n7453, n7454, n7455,
n7456, n7457, n7458, n7459, n7460, n7461, n7462, n7463, n7464, n7465,
n7466, n7467, n7468, n7469, n7470, n7471, n7472, n7473, n7474, n7475,
n7476, n7477, n7478, n7479, n7480, n7481, n7482, n7483, n7484, n7485,
n7486, n7487, n7488, n7489, n7490, n7491, n7492, n7493, n7494, n7495,
n7496, n7497, n7498, n7499, n7500, n7501, n7502, n7503, n7504, n7505,
n7506, n7507, n7508, n7509, n7510, n7511, n7512, n7513, n7514, n7515,
n7516, n7517, n7518, n7519, n7520, n7521, n7522, n7523, n7524, n7525,
n7526, n7527, n7528, n7529, n7530, n7531, n7532, n7533, n7534, n7535,
n7536, n7537, n7538, n7539, n7540, n7541, n7542, n7543, n7544, n7545,
n7546, n7547, n7548, n7549, n7550, n7551, n7552, n7553, n7554, n7555,
n7556, n7557, n7558, n7559, n7560, n7561, n7562, n7563, n7564, n7565,
n7566, n7567, n7568, n7569, n7570, n7571, n7572, n7573, n7574, n7575,
n7576, n7577, n7578, n7579, n7580, n7581, n7582, n7583, n7584, n7585,
n7586, n7587, n7588, n7589, n7590, n7591, n7592, n7593, n7594, n7595,
n7596, n7597, n7598, n7599, n7600, n7601, n7602, n7603, n7604, n7605,
n7606, n7607, n7608, n7609, n7610, n7611, n7612, n7613, n7614, n7615,
n7616, n7617, n7618, n7619, n7621, n7622, n7623, n7624, n7625, n7626,
n7627, n7628, n7629, n7630, n7631, n7633, n7634, n7635, n7636, n7637,
n7638, n7639, n7640, n7641, n7642, n7643, n7644, n7645, n7646, n7647,
n7648, n7649, n7650, n7652, n7653, n7654, n7655, n7657, n7658, n7659,
n7660, n7661, n7663, n7665, n7666, n7667, n7668, n7669, n7670, n7671,
n7672, n7673, n7674, n7676, n7677, n7678, n7679, n7680, n7682, n7683,
n7684, n7685, n7686, n7687, n7688, n7689, n7690, n7691, n7692, n7693,
n7694, n7695, n7696, n7697, n7698, n7699, n7700, n7701, n7702, n7703,
n7704, n7705, n7706, n7707, n7708, n7709, n7710, n7711, n7712, n7713,
n7714, n7715, n7716, n7717, n7718, n7719, n7720, n7721, n7722, n7723,
n7724, n7725, n7726, n7727, n7728, n7729, n7730, n7731, n7732, n7733,
n7734, n7735, n7736, n7737, n7738, n7739, n7740, n7741, n7742, n7743,
n7744, n7745, n7746, n7747, n7749, n7750, n7752, n7753, n7754, n7755,
n7756, n7757, n7758, n7759, n7760, n7761, n7762, n7763, n7764, n7765,
n7766, n7767, n7768, n7769, n7770, n7771, n7772, n7773, n7774, n7775,
n7776, n7777, n7778, n7779, n7780, n7781, n7782, n7783, n7784, n7785,
n7786, n7787, n7788, n7789, n7790, n7791, n7792, n7793, n7794, n7795,
n7796, n7797, n7798, n7799, n7800, n7801, n7802, n7803, n7833, n7834,
n7835, n7836, n7837, n7838, n7839, n7840, n7841, n7842, n7843, n7844,
n7845, n7846, n7847, n7848, n7849, n7850, n7851, n7852, n7853, n7854,
n7855, n7856, n7857, n7858, n7859, n7860, n7861, n7862, n7863, n7864,
n7865, n7866, n7867, n7868, n7869, n7870, n7871, n7872, n7873, n7874,
n7877, n7878, n7879, n7881, n7882, n7883, n7884, n7885, n7886, n7887,
n7888, n7889, n7890, n7891, n7892, n7893, n7894, n7895, n7896, n7897,
n7898, n7899, n7900, n7901, n7902, n7903, n7904, n7905, n7906, n7907,
n7908, n7913, n7914, n7915, n7916, n7917, n7918, n7920, n7921, n7922,
n7923, n7924, n7926, n7927, n7928, n7929, n7930, n7931, n7932, n7933,
n7934, n7935, n7936, n7937, n7938, n7939, n7940, n7941, n7942, n7943,
n7944, n7945, n7946, n7947, n7948, n7949, n7950, n7951, n7952, n7953,
n7954, n7955, n7956, n7957, n7958, n7959, n7960, n7961, n7962, n7963,
n7964, n7965, n7966, n7967, n7968, n7969, n7970, n7971, n7972, n7973,
n7974, n7975, n7976, n7977, n7978, n7979, n7980, n7981, n7982, n7983,
n7984, n7985, n7986, n7987, n7988, n7989, n7990, n7991, n7992, n7993,
n7994, n7995, n7996, n7997, n7998, n7999, n8000, n8001, n8002, n8003,
n8004, n8005, n8006, n8007, n8008, n8009, n8010, n8011, n8012, n8013,
n8014, n8015, n8016, n8017, n8018, n8019, n8020, n8021, n8022, n8023,
n8024, n8025, n8026, n8027, n8028, n8029, n8030, n8031, n8032, n8033,
n8034, n8035, n8036, n8037, n8038, n8039, n8040, n8041, n8042, n8043,
n8044, n8045, n8046, n8047, n8048, n8049, n8050, n8051, n8052, n8053,
n8054, n8055, n8056, n8057, n8058, n8059, n8061, n8062, n8063, n8064,
n8065, n8066, n8067, n8068, n8069, n8070, n8071, n8072, n8073, n8074,
n8075, n8076, n8077, n8078, n8079, n8080, n8081, n8082, n8083, n8084,
n8085, n8086, n8087, n8088, n8089, n8090, n8091, n8092, n8093, n8094,
n8095, n8096, n8097, n8098, n8099, n8100, n8101, n8102, n8103, n8104,
n8105, n8106, n8107, n8108, n8109, n8110, n8111, n8112, n8113, n8114,
n8115, n8116, n8117, n8118, n8119, n8120, n8121, n8122, n8123, n8124,
n8125, n8126, n8127, n8128, n8129, n8130, n8131, n8132, n8133, n8134,
n8135, n8136, n8137, n8138, n8139, n8140, n8141, n8142, n8143, n8144,
n8145, n8146, n8147, n8148, n8149, n8150, n8151, n8152, n8153, n8155,
n8156, n8157, n8158, n8159, n8160, n8161, n8162, n8163, n8164, n8165,
n8166, n8167, n8168, n8169, n8170, n8171, n8172, n8173, n8174, n8175,
n8176, n8177, n8178, n8179, n8180, n8181, n8182, n8183, n8184, n8185,
n8186, n8187, n8188, n8190, n8191, n8193, n8194, n8196, n8197, n8198,
n8200, n8202, n8204, n8205, n8206, n8208, n8209, n8211, n8212, n8213,
n8214, n8216, n8218, n8219, n8221, n8222, n8223, n8224, n8225, n8226,
n8227, n8228, n8229, n8230, n8231, n8233, n8234, n8235, n8236, n8238,
n8240, n8242, n8243, n8245, n8247, n8251, n8253, n8255, n8258, n8259,
n8260, n8261, n8262, n8263, n8264, n8265, n8266, n8267, n8268, n8269,
n8270, n8271, n8272, n8273, n8274, n8275, n8277, n8280, n8281, n8282,
n8283, n8284, n8285, n8286, n8287, n8288, n8289, n8290, n8291, n8292,
n8293, n8294, n8295, n8296, n8297, n8298, n8299, n8300, n8301, n8302,
n8303, n8304, n8305, n8306, n8307, n8308, n8309, n8310, n8311, n8312,
n8313, n8314, n8315, n8316, n8317, n8318, n8319, n8320, n8321, n8322,
n8323, n8324, n8325, n8326, n8327, n8328, n8329, n8330, n8331, n8332,
n8333, n8334, n8335, n8336, n8337, n8338, n8339, n8340, n8341, n8342,
n8343, n8344, n8345, n8346, n8347, n8348, n8349, n8350, n8351, n8352,
n8353, n8354, n8355, n8356, n8357, n8358, n8359, n8360, n8361, n8362,
n8363, n8364, n8365, n8366, n8367, n8368, n8369, n8370, n8371, n8372,
n8373, n8374, n8375, n8376, n8377, n8378, n8379, n8380, n8381, n8382,
n8383, n8384, n8385, n8386, n8387, n8388, n8389, n8390, n8391, n8392,
n8393, n8394, n8395, n8396, n8397, n8398, n8399, n8400, n8401, n8402,
n8403, n8404, n8405, n8406, n8407, n8408, n8409, n8410, n8411, n8412,
n8413, n8414, n8415, n8416, n8417, n8418, n8419, n8420, n8421, n8422,
n8423, n8424, n8425, n8426, n8427, n8428, n8429, n8430, n8431, n8432,
n8433, n8434, n8435, n8436, n8437, n8438, n8439, n8440, n8441, n8442,
n8443, n8444, n8445, n8446, n8447, n8448, n8449, n8450, n8451, n8452,
n8453, n8454, n8455, n8456, n8457, n8458, n8459, n8460, n8461, n8462,
n8463, n8464, n8465, n8466, n8467, n8468, n8469, n8470, n8471, n8472,
n8473, n8474, n8475, n8476, n8477, n8478, n8479, n8480, n8481, n8482,
n8483, n8484, n8485, n8486, n8487, n8488, n8489, n8490, n8491, n8492,
n8493, n8494, n8495, n8496, n8497, n8498, n8499, n8500, n8501, n8502,
n8503, n8504, n8505, n8506, n8507, n8508, n8509, n8510, n8511, n8512,
n8513, n8514, n8515, n8516, n8517, n8518, n8519, n8520, n8521, n8522,
n8523, n8524, n8525, n8526, n8527, n8528, n8529, n8530, n8531, n8532,
n8533, n8534, n8535, n8536, n8537, n8538, n8539, n8540, n8541, n8542,
n8543, n8544, n8545, n8546, n8547, n8548, n8549, n8550, n8551, n8552,
n8553, n8554, n8555, n8556, n8557, n8558, n8559, n8560, n8561, n8562,
n8563, n8564, n8565, n8566, n8567, n8568, n8569, n8570, n8571, n8572,
n8573, n8574, n8575, n8576, n8577, n8578, n8579, n8580, n8585, n8586,
n8587, n8588, n8589, n8591, n8593, n8594, n8595, n8596, n8597, n8598,
n8599, n8600, n8601, n8602, n8603, n8604, n8605, n8606, n8607, n8608,
n8609, n8610, n8611, n8612, n8613, n8614, n8616, n8618, n8620, n8621,
n8622, n8623, n8625, n8626, n8627, n8629, n8631, n8634, n8635, n8636,
n8676, n8677, n8678, n8679, n8680, n8681, n8682, n8683, n8684, n8685,
n8686, n8687, n8688, n8689, n8690, n8691, n8692, n8693, n8694, n8695,
n8696, n8697, n8698, n8699, n8700, n8701, n8702, n8703, n8704, n8705,
n8706, n8707, n8708, n8709, n8710, n8711, n8712, n8713, n8714, n8715,
n8716, n8717, n8718, n8719, n8720, n8721, n8722, n8723, n8724, n8725,
n8726, n8727, n8728, n8729, n8730, n8731, n8732, n8733, n8734, n8735,
n8736, n8737, n8738, n8739, n8740, n8741, n8742, n8743, n8744, n8745,
n8746, n8747, n8748, n8749, n8750, n8751, n8752, n8753, n8754, n8755,
n8756, n8757, n8758, n8759, n8760, n8761, n8762, n8763, n8764, n8765,
n8766, n8767, n8768, n8769, n8770, n8771, n8772, n8773, n8774, n8775,
n8776, n8777, n8778, n8779, n8780, n8781, n8782, n8783, n8784, n8785,
n8786, n8787, n8788, n8789, n8790, n8791, n8792, n8793, n8794, n8795,
n8796, n8797, n8798, n8799, n8800, n8801, n8802, n8803, n8804, n8805,
n8806, n8807, n8808, n8809, n8810, n8811, n8812, n8813, n8814, n8815,
n8816, n8817, n8818, n8819, n8820, n8821, n8822, n8823, n8824, n8825,
n8826, n8827, n8828, n8829, n8830, n8831, n8832, n8833, n8834, n8835,
n8836, n8837, n8838, n8839, n8840, n8841, n8842, n8843, n8844, n8845,
n8846, n8847, n8848, n8849, n8850, n8851, n8852, n8853, n8854, n8855,
n8856, n8857, n8858, n8859, n8860, n8861, n8862, n8863, n8864, n8865,
n8866, n8867, n8868, n8869, n8870, n8871, n8872, n8873, n8874, n8875,
n8876, n8877, n8878, n8879, n8880, n8881, n8882, n8883, n8884, n8885,
n8886, n8887, n8888, n8889, n8890, n8891, n8892, n8893, n8894, n8895,
n8896, n8897, n8898, n8899, n8900, n8901, n8902, n8903, n8904, n8905,
n8906, n8907, n8908, n8909, n8910, n8911, n8912, n8913, n8914, n8915,
n8916, n8917, n8918, n8919, n8920, n8921, n8922, n8923, n8924, n8925,
n8926, n8927, n8928, n8929, n8930, n8931, n8932, n8933, n8934, n8935,
n8936, n8937, n8938, n8939, n8940, n8941, n8942, n8943, n8944, n8945,
n8946, n8947, n8948, n8949, n8950, n8951, n8952, n8953, n8954, n8955,
n8956, n8957, n8958, n8959, n8960, n8961, n8962, n8963, n8964, n8965,
n8966, n8967, n8968, n8969, n8970, n8971, n8972, n8973, n8974, n8975,
n8976, n8977, n8978, n8979, n8980, n8981, n8982, n8983, n8984, n8985,
n8986, n8987, n8988, n8989, n8990, n8991, n8992, n8993, n8994, n8995,
n8996, n8997, n8998, n8999, n9000, n9001, n9002, n9003, n9004, n9005,
n9006, n9007, n9008, n9009, n9010, n9011, n9012, n9013, n9014, n9015,
n9016, n9017, n9018, n9019, n9020, n9021, n9022, n9023, n9024, n9025,
n9026, n9027, n9028, n9029, n9030, n9031, n9032, n9033, n9034, n9035,
n9036, n9037, n9038, n9039, n9040, n9041, n9042, n9043, n9044, n9045,
n9046, n9047, n9048, n9049, n9050, n9051, n9052, n9053, n9054, n9055,
n9056, n9057, n9058, n9059, n9060, n9061, n9062, n9063, n9064, n9065,
n9066, n9067, n9068, n9069, n9070, n9071, n9072, n9073, n9074, n9075,
n9076, n9077, n9078, n9079, n9080, n9081, n9082, n9083, n9084, n9085,
n9086, n9087, n9088, n9089, n9090, n9091, n9092, n9093, n9094, n9095,
n9096, n9097, n9098, n9099, n9100, n9101, n9102, n9103, n9104, n9105,
n9106, n9107, n9108, n9109, n9110, n9111, n9112, n9113, n9114, n9115,
n9116, n9117, n9118, n9119, n9120, n9121, n9122, n9123, n9124, n9125,
n9126, n9127, n9128, n9129, n9130, n9131, n9132, n9133, n9134, n9135,
n9136, n9137, n9138, n9139, n9140, n9141, n9142, n9143, n9144, n9145,
n9146, n9147, n9148, n9149, n9150, n9151, n9152, n9153, n9154, n9155,
n9156, n9157, n9158, n9159, n9160, n9161, n9162, n9163, n9164, n9165,
n9166, n9167, n9168, n9169, n9170, n9171, n9172, n9173, n9174, n9175,
n9176, n9177, n9178, n9179, n9180, n9181, n9182, n9183, n9184, n9185,
n9186, n9187, n9188, n9189, n9190, n9191, n9192, n9193, n9194, n9195,
n9196, n9197, n9198, n9199, n9200, n9201, n9202, n9203, n9204, n9205,
n9206, n9207, n9208, n9209, n9210, n9211, n9212, n9213, n9214, n9215,
n9216, n9217, n9218, n9219, n9220, n9221, n9222, n9223, n9224, n9225,
n9226, n9227, n9228, n9229, n9230, n9231, n9232, n9233, n9234, n9235,
n9236, n9237, n9238, n9239, n9240, n9241, n9242, n9243, n9244, n9245,
n9246, n9247, n9248, n9249, n9250, n9251, n9252, n9253, n9254, n9255,
n9256, n9257, n9258, n9259, n9260, n9261, n9262, n9263, n9264, n9265,
n9266, n9267, n9268, n9269, n9270, n9271, n9272, n9273, n9274, n9275,
n9276, n9277, n9278, n9279, n9280, n9281, n9282, n9283, n9284, n9285,
n9286, n9287, n9288, n9289, n9290, n9291, n9292, n9293, n9294, n9295,
n9296, n9297, n9298, n9299, n9300, n9301, n9302, n9303, n9304, n9305,
n9306, n9307, n9308, n9309, n9310, n9311, n9312, n9313, n9314, n9315,
n9316, n9317, n9318, n9319, n9320, n9321, n9322, n9323, n9324, n9325,
n9326, n9327, n9328, n9329, n9330, n9331, n9333, n9334, n9335, n9336,
n9337, n9338, n9339, n9340, n9341, n9342, n9343, n9344, n9345, n9346,
n9347, n9348, n9349, n9352, n9354, n9355, n9356, n9357, n9359, n9360,
n9361, n9362, n9364, n9365, n9366, n9367, n9368, n9369, n9370, n9371,
n9372, n9373, n9374, n9375, n9376, n9377, n9378, n9379, n9380, n9381,
n9382, n9383, n9384, n9385, n9386, n9387, n9388, n9389, n9390, n9391,
n9392, n9393, n9394, n9395, n9396, n9397, n9398, n9399, n9400, n9401,
n9402, n9403, n9404, n9405, n9406, n9407, n9408, n9409, n9410, n9411,
n9412, n9413, n9414, n9415, n9416, n9417, n9418, n9419, n9420, n9421,
n9422, n9423, n9424, n9425, n9426, n9427, n9428, n9429, n9431;
wire [5:0] opcode_i;
wire [4:0] \u_DataPath/regfile_addr_out_towb_i ;
wire [31:0] \u_DataPath/from_alu_data_out_i ;
wire [31:0] \u_DataPath/from_mem_data_out_i ;
wire [2:0] \u_DataPath/cw_towb_i ;
wire [4:0] \u_DataPath/RFaddr_out_memwb_i ;
wire [31:0] \u_DataPath/dataOut_exe_i ;
wire [2:0] \u_DataPath/cw_memwb_i ;
wire [31:0] \u_DataPath/mem_writedata_out_i ;
wire [10:0] \u_DataPath/cw_tomem_i ;
wire [31:0] \u_DataPath/toPC2_i ;
wire [10:0] \u_DataPath/cw_exmem_i ;
wire [4:0] \u_DataPath/rs_ex_i ;
wire [31:0] \u_DataPath/immediate_ext_ex_i ;
wire [31:0] \u_DataPath/data_read_ex_2_i ;
wire [31:0] \u_DataPath/data_read_ex_1_i ;
wire [31:0] \u_DataPath/pc_4_to_ex_i ;
wire [21:0] \u_DataPath/cw_to_ex_i ;
wire [31:0] \u_DataPath/immediate_ext_dec_i ;
wire [31:0] \u_DataPath/pc4_to_idexreg_i ;
wire [31:0] \u_DataPath/jaddr_i ;
wire [4:0] \u_DataPath/idex_rt_i ;
wire [31:0] \u_DataPath/pc_4_i ;
wire [31:0] \u_DataPath/branch_target_i ;
wire [31:0] \u_DataPath/jump_address_i ;
wire [1:0] \u_DataPath/u_decode_unit/hdu_0/current_state ;
wire [31:0] \u_DataPath/u_execute/psw_status_i ;
wire [31:0] \u_DataPath/u_execute/link_value_i ;
wire [31:0] \u_DataPath/u_execute/resAdd1_i ;
assign Address_toRAM[30] = 1'b0;
assign Address_toRAM[31] = 1'b0;
assign addr_to_iram[30] = 1'b0;
assign addr_to_iram[31] = 1'b0;
HS65_LH_CNIVX3 U151 ( .A(rst), .Z(n2733) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[9][31] (
.G(\u_DataPath/u_decode_unit/reg_file0/N146 ), .D(n7937), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][31] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[9][0] (
.G(\u_DataPath/u_decode_unit/reg_file0/N146 ), .D(n8000), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][0] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[9][1] (
.G(\u_DataPath/u_decode_unit/reg_file0/N146 ), .D(n8027), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][1] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[9][6] (
.G(\u_DataPath/u_decode_unit/reg_file0/N146 ), .D(n8018), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][6] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[9][18] (
.G(\u_DataPath/u_decode_unit/reg_file0/N146 ), .D(n7982), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][18] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[9][2] (
.G(\u_DataPath/u_decode_unit/reg_file0/N146 ), .D(n8030), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][2] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[9][17] (
.G(\u_DataPath/u_decode_unit/reg_file0/N146 ), .D(n7988), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][17] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[9][16] (
.G(\u_DataPath/u_decode_unit/reg_file0/N146 ), .D(n7955), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][16] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[9][20] (
.G(\u_DataPath/u_decode_unit/reg_file0/N146 ), .D(n7961), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][20] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[9][8] (
.G(\u_DataPath/u_decode_unit/reg_file0/N146 ), .D(n7940), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][8] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[9][4] (
.G(\u_DataPath/u_decode_unit/reg_file0/N146 ), .D(n8033), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][4] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[9][22] (
.G(\u_DataPath/u_decode_unit/reg_file0/N146 ), .D(n7979), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][22] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[9][28] (
.G(\u_DataPath/u_decode_unit/reg_file0/N146 ), .D(n7931), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][28] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[9][24] (
.G(\u_DataPath/u_decode_unit/reg_file0/N146 ), .D(n7985), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][24] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[9][9] (
.G(\u_DataPath/u_decode_unit/reg_file0/N146 ), .D(n8015), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][9] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[9][25] (
.G(\u_DataPath/u_decode_unit/reg_file0/N146 ), .D(n7994), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][25] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[9][5] (
.G(\u_DataPath/u_decode_unit/reg_file0/N146 ), .D(n8024), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][5] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[9][21] (
.G(\u_DataPath/u_decode_unit/reg_file0/N146 ), .D(n7967), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][21] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[9][29] (
.G(\u_DataPath/u_decode_unit/reg_file0/N146 ), .D(n8009), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][29] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[9][13] (
.G(\u_DataPath/u_decode_unit/reg_file0/N146 ), .D(n7958), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][13] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[9][7] (
.G(\u_DataPath/u_decode_unit/reg_file0/N146 ), .D(n7952), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][7] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[9][12] (
.G(\u_DataPath/u_decode_unit/reg_file0/N146 ), .D(n7970), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][12] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[10][30] (
.G(\u_DataPath/u_decode_unit/reg_file0/N145 ), .D(n8010), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][30] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[9][23] (
.G(\u_DataPath/u_decode_unit/reg_file0/N146 ), .D(n7997), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][23] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[9][26] (
.G(\u_DataPath/u_decode_unit/reg_file0/N146 ), .D(n8006), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][26] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[9][10] (
.G(\u_DataPath/u_decode_unit/reg_file0/N146 ), .D(n7946), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][10] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[9][3] (
.G(\u_DataPath/u_decode_unit/reg_file0/N146 ), .D(n8021), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][3] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[9][19] (
.G(\u_DataPath/u_decode_unit/reg_file0/N146 ), .D(n7964), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][19] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[9][11] (
.G(\u_DataPath/u_decode_unit/reg_file0/N146 ), .D(n7943), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][11] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[9][15] (
.G(\u_DataPath/u_decode_unit/reg_file0/N146 ), .D(n7973), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][15] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[9][14] (
.G(\u_DataPath/u_decode_unit/reg_file0/N146 ), .D(n7991), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][14] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[9][27] (
.G(\u_DataPath/u_decode_unit/reg_file0/N146 ), .D(n7928), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][27] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[19][31] (
.G(\u_DataPath/u_decode_unit/reg_file0/N136 ), .D(n7935), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][31] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[19][0] (
.G(\u_DataPath/u_decode_unit/reg_file0/N136 ), .D(n7998), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][0] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[19][1] (
.G(\u_DataPath/u_decode_unit/reg_file0/N136 ), .D(n8025), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][1] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[19][6] (
.G(\u_DataPath/u_decode_unit/reg_file0/N136 ), .D(n8016), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][6] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[19][18] (
.G(\u_DataPath/u_decode_unit/reg_file0/N136 ), .D(n7980), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][18] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[19][2] (
.G(\u_DataPath/u_decode_unit/reg_file0/N136 ), .D(n8029), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][2] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[19][17] (
.G(\u_DataPath/u_decode_unit/reg_file0/N136 ), .D(n7986), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][17] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[19][16] (
.G(\u_DataPath/u_decode_unit/reg_file0/N136 ), .D(n7953), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][16] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[19][20] (
.G(\u_DataPath/u_decode_unit/reg_file0/N136 ), .D(n7959), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][20] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[19][8] (
.G(\u_DataPath/u_decode_unit/reg_file0/N136 ), .D(n7938), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][8] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[19][4] (
.G(\u_DataPath/u_decode_unit/reg_file0/N136 ), .D(n8031), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][4] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[19][22] (
.G(\u_DataPath/u_decode_unit/reg_file0/N136 ), .D(n7977), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][22] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[19][28] (
.G(\u_DataPath/u_decode_unit/reg_file0/N136 ), .D(n7929), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][28] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[19][24] (
.G(\u_DataPath/u_decode_unit/reg_file0/N136 ), .D(n7983), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][24] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[19][9] (
.G(\u_DataPath/u_decode_unit/reg_file0/N136 ), .D(n8013), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][9] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[19][25] (
.G(\u_DataPath/u_decode_unit/reg_file0/N136 ), .D(n7992), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][25] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[19][5] (
.G(\u_DataPath/u_decode_unit/reg_file0/N136 ), .D(n8022), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][5] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[19][21] (
.G(\u_DataPath/u_decode_unit/reg_file0/N136 ), .D(n7965), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][21] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[19][29] (
.G(\u_DataPath/u_decode_unit/reg_file0/N136 ), .D(n8007), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][29] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[19][13] (
.G(\u_DataPath/u_decode_unit/reg_file0/N136 ), .D(n7956), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][13] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[19][7] (
.G(\u_DataPath/u_decode_unit/reg_file0/N136 ), .D(n7950), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][7] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[19][12] (
.G(\u_DataPath/u_decode_unit/reg_file0/N136 ), .D(n7968), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][12] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[19][30] (
.G(\u_DataPath/u_decode_unit/reg_file0/N136 ), .D(n8011), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][30] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[19][23] (
.G(\u_DataPath/u_decode_unit/reg_file0/N136 ), .D(n7995), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][23] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[19][26] (
.G(\u_DataPath/u_decode_unit/reg_file0/N136 ), .D(n8004), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][26] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[19][10] (
.G(\u_DataPath/u_decode_unit/reg_file0/N136 ), .D(n7944), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][10] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[19][3] (
.G(\u_DataPath/u_decode_unit/reg_file0/N136 ), .D(n8020), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][3] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[19][19] (
.G(\u_DataPath/u_decode_unit/reg_file0/N136 ), .D(n7962), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][19] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[19][11] (
.G(\u_DataPath/u_decode_unit/reg_file0/N136 ), .D(n7941), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][11] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[19][15] (
.G(\u_DataPath/u_decode_unit/reg_file0/N136 ), .D(n7971), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][15] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[19][14] (
.G(\u_DataPath/u_decode_unit/reg_file0/N136 ), .D(n7989), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][14] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[19][27] (
.G(\u_DataPath/u_decode_unit/reg_file0/N136 ), .D(n7926), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][27] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[27][31] (
.G(\u_DataPath/u_decode_unit/reg_file0/N128 ), .D(n7935), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][31] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[31][0] (
.G(\u_DataPath/u_decode_unit/reg_file0/N92 ), .D(n7998), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][0] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[27][0] (
.G(\u_DataPath/u_decode_unit/reg_file0/N128 ), .D(n7998), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][0] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[31][1] (
.G(\u_DataPath/u_decode_unit/reg_file0/N92 ), .D(n8025), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][1] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[27][1] (
.G(\u_DataPath/u_decode_unit/reg_file0/N128 ), .D(n8025), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][1] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[31][6] (
.G(\u_DataPath/u_decode_unit/reg_file0/N92 ), .D(n8016), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][6] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[27][6] (
.G(\u_DataPath/u_decode_unit/reg_file0/N128 ), .D(n8016), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][6] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[31][18] (
.G(\u_DataPath/u_decode_unit/reg_file0/N92 ), .D(n7980), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][18] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[27][18] (
.G(\u_DataPath/u_decode_unit/reg_file0/N128 ), .D(n7980), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][18] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[31][2] (
.G(\u_DataPath/u_decode_unit/reg_file0/N92 ), .D(n8028), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][2] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[27][2] (
.G(\u_DataPath/u_decode_unit/reg_file0/N128 ), .D(n8029), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][2] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[31][17] (
.G(\u_DataPath/u_decode_unit/reg_file0/N92 ), .D(n7986), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][17] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[27][17] (
.G(\u_DataPath/u_decode_unit/reg_file0/N128 ), .D(n7986), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][17] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[31][16] (
.G(\u_DataPath/u_decode_unit/reg_file0/N92 ), .D(n7953), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][16] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[27][16] (
.G(\u_DataPath/u_decode_unit/reg_file0/N128 ), .D(n7953), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][16] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[27][20] (
.G(\u_DataPath/u_decode_unit/reg_file0/N128 ), .D(n7959), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][20] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[31][8] (
.G(\u_DataPath/u_decode_unit/reg_file0/N92 ), .D(n7938), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][8] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[27][8] (
.G(\u_DataPath/u_decode_unit/reg_file0/N128 ), .D(n7938), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][8] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[31][4] (
.G(\u_DataPath/u_decode_unit/reg_file0/N92 ), .D(n8031), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][4] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[27][4] (
.G(\u_DataPath/u_decode_unit/reg_file0/N128 ), .D(n8031), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][4] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[31][22] (
.G(\u_DataPath/u_decode_unit/reg_file0/N92 ), .D(n7977), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][22] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[27][22] (
.G(\u_DataPath/u_decode_unit/reg_file0/N128 ), .D(n7977), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][22] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[31][28] (
.G(\u_DataPath/u_decode_unit/reg_file0/N92 ), .D(n7929), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][28] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[27][28] (
.G(\u_DataPath/u_decode_unit/reg_file0/N128 ), .D(n7929), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][28] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[31][24] (
.G(\u_DataPath/u_decode_unit/reg_file0/N92 ), .D(n7983), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][24] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[27][24] (
.G(\u_DataPath/u_decode_unit/reg_file0/N128 ), .D(n7983), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][24] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[31][9] (
.G(\u_DataPath/u_decode_unit/reg_file0/N92 ), .D(n8013), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][9] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[27][9] (
.G(\u_DataPath/u_decode_unit/reg_file0/N128 ), .D(n8013), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][9] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[31][25] (
.G(\u_DataPath/u_decode_unit/reg_file0/N92 ), .D(n7992), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][25] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[27][25] (
.G(\u_DataPath/u_decode_unit/reg_file0/N128 ), .D(n7992), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][25] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[31][5] (
.G(\u_DataPath/u_decode_unit/reg_file0/N92 ), .D(n8022), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][5] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[27][5] (
.G(\u_DataPath/u_decode_unit/reg_file0/N128 ), .D(n8022), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][5] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[31][21] (
.G(\u_DataPath/u_decode_unit/reg_file0/N92 ), .D(n7965), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][21] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[27][21] (
.G(\u_DataPath/u_decode_unit/reg_file0/N128 ), .D(n7965), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][21] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[31][29] (
.G(\u_DataPath/u_decode_unit/reg_file0/N92 ), .D(n8007), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][29] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[27][29] (
.G(\u_DataPath/u_decode_unit/reg_file0/N128 ), .D(n8007), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][29] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[31][13] (
.G(\u_DataPath/u_decode_unit/reg_file0/N92 ), .D(n7956), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][13] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[27][13] (
.G(\u_DataPath/u_decode_unit/reg_file0/N128 ), .D(n7956), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][13] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[31][7] (
.G(\u_DataPath/u_decode_unit/reg_file0/N92 ), .D(n7950), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][7] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[27][7] (
.G(\u_DataPath/u_decode_unit/reg_file0/N128 ), .D(n7950), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][7] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[27][12] (
.G(\u_DataPath/u_decode_unit/reg_file0/N128 ), .D(n7968), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][12] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[31][23] (
.G(\u_DataPath/u_decode_unit/reg_file0/N92 ), .D(n7995), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][23] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[27][23] (
.G(\u_DataPath/u_decode_unit/reg_file0/N128 ), .D(n7995), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][23] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[27][26] (
.G(\u_DataPath/u_decode_unit/reg_file0/N128 ), .D(n8004), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][26] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[31][10] (
.G(\u_DataPath/u_decode_unit/reg_file0/N92 ), .D(n7944), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][10] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[27][10] (
.G(\u_DataPath/u_decode_unit/reg_file0/N128 ), .D(n7944), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][10] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[31][3] (
.G(\u_DataPath/u_decode_unit/reg_file0/N92 ), .D(n8019), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][3] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[27][3] (
.G(\u_DataPath/u_decode_unit/reg_file0/N128 ), .D(n8019), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][3] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[31][19] (
.G(\u_DataPath/u_decode_unit/reg_file0/N92 ), .D(n7962), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][19] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[27][19] (
.G(\u_DataPath/u_decode_unit/reg_file0/N128 ), .D(n7962), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][19] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[31][11] (
.G(\u_DataPath/u_decode_unit/reg_file0/N92 ), .D(n7941), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][11] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[27][11] (
.G(\u_DataPath/u_decode_unit/reg_file0/N128 ), .D(n7941), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][11] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[31][15] (
.G(\u_DataPath/u_decode_unit/reg_file0/N92 ), .D(n7971), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][15] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[27][15] (
.G(\u_DataPath/u_decode_unit/reg_file0/N128 ), .D(n7971), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][15] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[27][14] (
.G(\u_DataPath/u_decode_unit/reg_file0/N128 ), .D(n7989), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][14] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[27][27] (
.G(\u_DataPath/u_decode_unit/reg_file0/N128 ), .D(n7926), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][27] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[4][30] (
.G(\u_DataPath/u_decode_unit/reg_file0/N151 ), .D(n8010), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][30] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[1][30] (
.G(\u_DataPath/u_decode_unit/reg_file0/N154 ), .D(n8010), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][30] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[18][31] (
.G(\u_DataPath/u_decode_unit/reg_file0/N137 ), .D(n7936), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][31] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[18][0] (
.G(\u_DataPath/u_decode_unit/reg_file0/N137 ), .D(n7999), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][0] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[18][1] (
.G(\u_DataPath/u_decode_unit/reg_file0/N137 ), .D(n8026), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][1] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[18][6] (
.G(\u_DataPath/u_decode_unit/reg_file0/N137 ), .D(n8017), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][6] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[18][18] (
.G(\u_DataPath/u_decode_unit/reg_file0/N137 ), .D(n7981), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][18] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[18][2] (
.G(\u_DataPath/u_decode_unit/reg_file0/N137 ), .D(n8028), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][2] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[18][17] (
.G(\u_DataPath/u_decode_unit/reg_file0/N137 ), .D(n7987), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][17] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[18][16] (
.G(\u_DataPath/u_decode_unit/reg_file0/N137 ), .D(n7954), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][16] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[18][20] (
.G(\u_DataPath/u_decode_unit/reg_file0/N137 ), .D(n7960), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][20] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[18][4] (
.G(\u_DataPath/u_decode_unit/reg_file0/N137 ), .D(n8032), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][4] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[18][22] (
.G(\u_DataPath/u_decode_unit/reg_file0/N137 ), .D(n7978), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][22] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[18][9] (
.G(\u_DataPath/u_decode_unit/reg_file0/N137 ), .D(n8014), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][9] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[18][25] (
.G(\u_DataPath/u_decode_unit/reg_file0/N137 ), .D(n7993), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][25] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[18][5] (
.G(\u_DataPath/u_decode_unit/reg_file0/N137 ), .D(n8023), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][5] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[18][21] (
.G(\u_DataPath/u_decode_unit/reg_file0/N137 ), .D(n7966), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][21] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[18][29] (
.G(\u_DataPath/u_decode_unit/reg_file0/N137 ), .D(n8008), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][29] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[18][13] (
.G(\u_DataPath/u_decode_unit/reg_file0/N137 ), .D(n7957), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][13] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[18][7] (
.G(\u_DataPath/u_decode_unit/reg_file0/N137 ), .D(n7951), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][7] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[18][12] (
.G(\u_DataPath/u_decode_unit/reg_file0/N137 ), .D(n7969), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][12] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[18][30] (
.G(\u_DataPath/u_decode_unit/reg_file0/N137 ), .D(n8012), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][30] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[18][23] (
.G(\u_DataPath/u_decode_unit/reg_file0/N137 ), .D(n7996), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][23] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[18][26] (
.G(\u_DataPath/u_decode_unit/reg_file0/N137 ), .D(n8005), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][26] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[18][10] (
.G(\u_DataPath/u_decode_unit/reg_file0/N137 ), .D(n7945), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][10] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[18][3] (
.G(\u_DataPath/u_decode_unit/reg_file0/N137 ), .D(n8019), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][3] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[18][11] (
.G(\u_DataPath/u_decode_unit/reg_file0/N137 ), .D(n7942), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][11] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[18][15] (
.G(\u_DataPath/u_decode_unit/reg_file0/N137 ), .D(n7972), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][15] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[18][14] (
.G(\u_DataPath/u_decode_unit/reg_file0/N137 ), .D(n7990), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][14] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[18][27] (
.G(\u_DataPath/u_decode_unit/reg_file0/N137 ), .D(n7927), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][27] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[4][31] (
.G(\u_DataPath/u_decode_unit/reg_file0/N151 ), .D(n7936), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][31] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[4][0] (
.G(\u_DataPath/u_decode_unit/reg_file0/N151 ), .D(n7999), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][0] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[4][1] (
.G(\u_DataPath/u_decode_unit/reg_file0/N151 ), .D(n8026), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][1] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[4][6] (
.G(\u_DataPath/u_decode_unit/reg_file0/N151 ), .D(n8017), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][6] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[4][18] (
.G(\u_DataPath/u_decode_unit/reg_file0/N151 ), .D(n7981), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][18] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[4][2] (
.G(\u_DataPath/u_decode_unit/reg_file0/N151 ), .D(n8029), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][2] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[4][17] (
.G(\u_DataPath/u_decode_unit/reg_file0/N151 ), .D(n7987), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][17] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[4][16] (
.G(\u_DataPath/u_decode_unit/reg_file0/N151 ), .D(n7954), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][16] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[4][20] (
.G(\u_DataPath/u_decode_unit/reg_file0/N151 ), .D(n7960), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][20] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[4][8] (
.G(\u_DataPath/u_decode_unit/reg_file0/N151 ), .D(n7939), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][8] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[4][4] (
.G(\u_DataPath/u_decode_unit/reg_file0/N151 ), .D(n8032), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][4] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[4][22] (
.G(\u_DataPath/u_decode_unit/reg_file0/N151 ), .D(n7978), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][22] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[4][28] (
.G(\u_DataPath/u_decode_unit/reg_file0/N151 ), .D(n7930), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][28] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[4][24] (
.G(\u_DataPath/u_decode_unit/reg_file0/N151 ), .D(n7984), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][24] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[4][9] (
.G(\u_DataPath/u_decode_unit/reg_file0/N151 ), .D(n8014), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][9] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[4][25] (
.G(\u_DataPath/u_decode_unit/reg_file0/N151 ), .D(n7993), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][25] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[4][5] (
.G(\u_DataPath/u_decode_unit/reg_file0/N151 ), .D(n8023), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][5] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[4][21] (
.G(\u_DataPath/u_decode_unit/reg_file0/N151 ), .D(n7966), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][21] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[4][29] (
.G(\u_DataPath/u_decode_unit/reg_file0/N151 ), .D(n8008), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][29] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[4][13] (
.G(\u_DataPath/u_decode_unit/reg_file0/N151 ), .D(n7957), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][13] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[4][7] (
.G(\u_DataPath/u_decode_unit/reg_file0/N151 ), .D(n7951), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][7] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[4][12] (
.G(\u_DataPath/u_decode_unit/reg_file0/N151 ), .D(n7969), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][12] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[4][23] (
.G(\u_DataPath/u_decode_unit/reg_file0/N151 ), .D(n7996), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][23] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[4][26] (
.G(\u_DataPath/u_decode_unit/reg_file0/N151 ), .D(n8005), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][26] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[4][10] (
.G(\u_DataPath/u_decode_unit/reg_file0/N151 ), .D(n7945), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][10] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[4][3] (
.G(\u_DataPath/u_decode_unit/reg_file0/N151 ), .D(n8020), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][3] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[4][19] (
.G(\u_DataPath/u_decode_unit/reg_file0/N151 ), .D(n7963), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][19] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[4][11] (
.G(\u_DataPath/u_decode_unit/reg_file0/N151 ), .D(n7942), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][11] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[4][15] (
.G(\u_DataPath/u_decode_unit/reg_file0/N151 ), .D(n7972), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][15] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[4][14] (
.G(\u_DataPath/u_decode_unit/reg_file0/N151 ), .D(n7990), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][14] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[4][27] (
.G(\u_DataPath/u_decode_unit/reg_file0/N151 ), .D(n7927), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][27] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[30][30] (
.G(\u_DataPath/u_decode_unit/reg_file0/N125 ), .D(n8012), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][30] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[25][30] (
.G(\u_DataPath/u_decode_unit/reg_file0/N130 ), .D(n8012), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][30] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[2][31] (
.G(\u_DataPath/u_decode_unit/reg_file0/N153 ), .D(n7937), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][31] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[2][0] (
.G(\u_DataPath/u_decode_unit/reg_file0/N153 ), .D(n8000), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][0] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[2][1] (
.G(\u_DataPath/u_decode_unit/reg_file0/N153 ), .D(n8027), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][1] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[2][6] (
.G(\u_DataPath/u_decode_unit/reg_file0/N153 ), .D(n8018), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][6] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[2][18] (
.G(\u_DataPath/u_decode_unit/reg_file0/N153 ), .D(n7982), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][18] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[2][2] (
.G(\u_DataPath/u_decode_unit/reg_file0/N153 ), .D(n8029), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][2] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[2][17] (
.G(\u_DataPath/u_decode_unit/reg_file0/N153 ), .D(n7988), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][17] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[2][16] (
.G(\u_DataPath/u_decode_unit/reg_file0/N153 ), .D(n7955), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][16] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[2][20] (
.G(\u_DataPath/u_decode_unit/reg_file0/N153 ), .D(n7961), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][20] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[2][8] (
.G(\u_DataPath/u_decode_unit/reg_file0/N153 ), .D(n7940), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][8] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[2][4] (
.G(\u_DataPath/u_decode_unit/reg_file0/N153 ), .D(n8033), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][4] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[2][22] (
.G(\u_DataPath/u_decode_unit/reg_file0/N153 ), .D(n7979), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][22] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[2][28] (
.G(\u_DataPath/u_decode_unit/reg_file0/N153 ), .D(n7931), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][28] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[2][24] (
.G(\u_DataPath/u_decode_unit/reg_file0/N153 ), .D(n7985), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][24] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[2][9] (
.G(\u_DataPath/u_decode_unit/reg_file0/N153 ), .D(n8015), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][9] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[2][25] (
.G(\u_DataPath/u_decode_unit/reg_file0/N153 ), .D(n7994), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][25] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[2][5] (
.G(\u_DataPath/u_decode_unit/reg_file0/N153 ), .D(n8024), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][5] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[2][21] (
.G(\u_DataPath/u_decode_unit/reg_file0/N153 ), .D(n7967), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][21] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[2][29] (
.G(\u_DataPath/u_decode_unit/reg_file0/N153 ), .D(n8009), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][29] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[2][13] (
.G(\u_DataPath/u_decode_unit/reg_file0/N153 ), .D(n7958), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][13] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[2][7] (
.G(\u_DataPath/u_decode_unit/reg_file0/N153 ), .D(n7952), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][7] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[2][12] (
.G(\u_DataPath/u_decode_unit/reg_file0/N153 ), .D(n7970), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][12] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[2][23] (
.G(\u_DataPath/u_decode_unit/reg_file0/N153 ), .D(n7997), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][23] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[2][26] (
.G(\u_DataPath/u_decode_unit/reg_file0/N153 ), .D(n8006), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][26] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[2][10] (
.G(\u_DataPath/u_decode_unit/reg_file0/N153 ), .D(n7946), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][10] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[2][3] (
.G(\u_DataPath/u_decode_unit/reg_file0/N153 ), .D(n8020), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][3] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[2][19] (
.G(\u_DataPath/u_decode_unit/reg_file0/N153 ), .D(n7964), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][19] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[2][11] (
.G(\u_DataPath/u_decode_unit/reg_file0/N153 ), .D(n7943), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][11] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[2][15] (
.G(\u_DataPath/u_decode_unit/reg_file0/N153 ), .D(n7973), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][15] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[2][14] (
.G(\u_DataPath/u_decode_unit/reg_file0/N153 ), .D(n7991), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][14] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[2][27] (
.G(\u_DataPath/u_decode_unit/reg_file0/N153 ), .D(n7928), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][27] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[23][31] (
.G(\u_DataPath/u_decode_unit/reg_file0/N132 ), .D(n7935), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][31] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[23][0] (
.G(\u_DataPath/u_decode_unit/reg_file0/N132 ), .D(n7998), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][0] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[23][1] (
.G(\u_DataPath/u_decode_unit/reg_file0/N132 ), .D(n8025), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][1] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[23][6] (
.G(\u_DataPath/u_decode_unit/reg_file0/N132 ), .D(n8016), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][6] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[23][18] (
.G(\u_DataPath/u_decode_unit/reg_file0/N132 ), .D(n7980), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][18] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[23][2] (
.G(\u_DataPath/u_decode_unit/reg_file0/N132 ), .D(n8028), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][2] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[23][16] (
.G(\u_DataPath/u_decode_unit/reg_file0/N132 ), .D(n7953), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][16] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[23][20] (
.G(\u_DataPath/u_decode_unit/reg_file0/N132 ), .D(n7959), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][20] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[23][8] (
.G(\u_DataPath/u_decode_unit/reg_file0/N132 ), .D(n7938), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][8] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[23][4] (
.G(\u_DataPath/u_decode_unit/reg_file0/N132 ), .D(n8031), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][4] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[23][22] (
.G(\u_DataPath/u_decode_unit/reg_file0/N132 ), .D(n7977), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][22] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[23][28] (
.G(\u_DataPath/u_decode_unit/reg_file0/N132 ), .D(n7929), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][28] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[23][24] (
.G(\u_DataPath/u_decode_unit/reg_file0/N132 ), .D(n7983), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][24] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[23][9] (
.G(\u_DataPath/u_decode_unit/reg_file0/N132 ), .D(n8013), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][9] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[23][25] (
.G(\u_DataPath/u_decode_unit/reg_file0/N132 ), .D(n7992), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][25] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[23][5] (
.G(\u_DataPath/u_decode_unit/reg_file0/N132 ), .D(n8022), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][5] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[23][21] (
.G(\u_DataPath/u_decode_unit/reg_file0/N132 ), .D(n7965), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][21] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[23][29] (
.G(\u_DataPath/u_decode_unit/reg_file0/N132 ), .D(n8007), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][29] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[23][13] (
.G(\u_DataPath/u_decode_unit/reg_file0/N132 ), .D(n7956), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][13] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[23][7] (
.G(\u_DataPath/u_decode_unit/reg_file0/N132 ), .D(n7950), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][7] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[23][12] (
.G(\u_DataPath/u_decode_unit/reg_file0/N132 ), .D(n7968), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][12] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[23][30] (
.G(\u_DataPath/u_decode_unit/reg_file0/N132 ), .D(n8011), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][30] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[23][23] (
.G(\u_DataPath/u_decode_unit/reg_file0/N132 ), .D(n7995), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][23] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[23][26] (
.G(\u_DataPath/u_decode_unit/reg_file0/N132 ), .D(n8004), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][26] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[23][10] (
.G(\u_DataPath/u_decode_unit/reg_file0/N132 ), .D(n7944), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][10] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[23][3] (
.G(\u_DataPath/u_decode_unit/reg_file0/N132 ), .D(n8019), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][3] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[23][19] (
.G(\u_DataPath/u_decode_unit/reg_file0/N132 ), .D(n7962), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][19] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[23][11] (
.G(\u_DataPath/u_decode_unit/reg_file0/N132 ), .D(n7941), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][11] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[23][15] (
.G(\u_DataPath/u_decode_unit/reg_file0/N132 ), .D(n7971), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][15] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[23][14] (
.G(\u_DataPath/u_decode_unit/reg_file0/N132 ), .D(n7989), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][14] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[23][27] (
.G(\u_DataPath/u_decode_unit/reg_file0/N132 ), .D(n7926), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][27] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[5][31] (
.G(\u_DataPath/u_decode_unit/reg_file0/N150 ), .D(n7937), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][31] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[5][0] (
.G(\u_DataPath/u_decode_unit/reg_file0/N150 ), .D(n8000), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][0] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[5][1] (
.G(\u_DataPath/u_decode_unit/reg_file0/N150 ), .D(n8027), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][1] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[5][6] (
.G(\u_DataPath/u_decode_unit/reg_file0/N150 ), .D(n8018), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][6] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[5][18] (
.G(\u_DataPath/u_decode_unit/reg_file0/N150 ), .D(n7982), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][18] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[5][2] (
.G(\u_DataPath/u_decode_unit/reg_file0/N150 ), .D(n8030), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][2] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[5][17] (
.G(\u_DataPath/u_decode_unit/reg_file0/N150 ), .D(n7988), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][17] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[5][16] (
.G(\u_DataPath/u_decode_unit/reg_file0/N150 ), .D(n7955), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][16] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[5][20] (
.G(\u_DataPath/u_decode_unit/reg_file0/N150 ), .D(n7961), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][20] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[5][8] (
.G(\u_DataPath/u_decode_unit/reg_file0/N150 ), .D(n7940), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][8] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[5][4] (
.G(\u_DataPath/u_decode_unit/reg_file0/N150 ), .D(n8033), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][4] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[5][22] (
.G(\u_DataPath/u_decode_unit/reg_file0/N150 ), .D(n7979), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][22] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[5][28] (
.G(\u_DataPath/u_decode_unit/reg_file0/N150 ), .D(n7931), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][28] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[5][24] (
.G(\u_DataPath/u_decode_unit/reg_file0/N150 ), .D(n7985), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][24] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[5][9] (
.G(\u_DataPath/u_decode_unit/reg_file0/N150 ), .D(n8015), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][9] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[5][25] (
.G(\u_DataPath/u_decode_unit/reg_file0/N150 ), .D(n7994), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][25] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[5][5] (
.G(\u_DataPath/u_decode_unit/reg_file0/N150 ), .D(n8024), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][5] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[5][21] (
.G(\u_DataPath/u_decode_unit/reg_file0/N150 ), .D(n7967), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][21] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[5][29] (
.G(\u_DataPath/u_decode_unit/reg_file0/N150 ), .D(n8009), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][29] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[5][13] (
.G(\u_DataPath/u_decode_unit/reg_file0/N150 ), .D(n7958), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][13] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[5][7] (
.G(\u_DataPath/u_decode_unit/reg_file0/N150 ), .D(n7952), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][7] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[5][12] (
.G(\u_DataPath/u_decode_unit/reg_file0/N150 ), .D(n7970), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][12] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[5][23] (
.G(\u_DataPath/u_decode_unit/reg_file0/N150 ), .D(n7997), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][23] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[5][26] (
.G(\u_DataPath/u_decode_unit/reg_file0/N150 ), .D(n8006), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][26] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[5][10] (
.G(\u_DataPath/u_decode_unit/reg_file0/N150 ), .D(n7946), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][10] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[5][3] (
.G(\u_DataPath/u_decode_unit/reg_file0/N150 ), .D(n8021), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][3] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[5][19] (
.G(\u_DataPath/u_decode_unit/reg_file0/N150 ), .D(n7964), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][19] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[5][11] (
.G(\u_DataPath/u_decode_unit/reg_file0/N150 ), .D(n7943), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][11] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[5][15] (
.G(\u_DataPath/u_decode_unit/reg_file0/N150 ), .D(n7973), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][15] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[5][14] (
.G(\u_DataPath/u_decode_unit/reg_file0/N150 ), .D(n7991), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][14] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[5][27] (
.G(\u_DataPath/u_decode_unit/reg_file0/N150 ), .D(n7928), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][27] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[5][30] (
.G(\u_DataPath/u_decode_unit/reg_file0/N150 ), .D(n8010), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][30] ) );
HS65_LH_LDHQX4 \u_DataPath/u_execute/EXALU/ovf_reg ( .G(
\u_DataPath/u_execute/EXALU/N810 ), .D(
\u_DataPath/u_execute/EXALU/N811 ), .Q(\u_DataPath/u_execute/ovf_i )
);
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[3][31] (
.G(\u_DataPath/u_decode_unit/reg_file0/N152 ), .D(n7936), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][31] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[3][0] (
.G(\u_DataPath/u_decode_unit/reg_file0/N152 ), .D(n7999), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][0] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[3][1] (
.G(\u_DataPath/u_decode_unit/reg_file0/N152 ), .D(n8026), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][1] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[3][6] (
.G(\u_DataPath/u_decode_unit/reg_file0/N152 ), .D(n8017), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][6] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[3][18] (
.G(\u_DataPath/u_decode_unit/reg_file0/N152 ), .D(n7981), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][18] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[3][2] (
.G(\u_DataPath/u_decode_unit/reg_file0/N152 ), .D(n8029), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][2] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[3][17] (
.G(\u_DataPath/u_decode_unit/reg_file0/N152 ), .D(n7987), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][17] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[3][16] (
.G(\u_DataPath/u_decode_unit/reg_file0/N152 ), .D(n7954), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][16] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[3][20] (
.G(\u_DataPath/u_decode_unit/reg_file0/N152 ), .D(n7960), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][20] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[3][8] (
.G(\u_DataPath/u_decode_unit/reg_file0/N152 ), .D(n7939), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][8] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[3][4] (
.G(\u_DataPath/u_decode_unit/reg_file0/N152 ), .D(n8032), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][4] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[3][22] (
.G(\u_DataPath/u_decode_unit/reg_file0/N152 ), .D(n7978), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][22] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[3][28] (
.G(\u_DataPath/u_decode_unit/reg_file0/N152 ), .D(n7930), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][28] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[3][24] (
.G(\u_DataPath/u_decode_unit/reg_file0/N152 ), .D(n7984), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][24] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[3][9] (
.G(\u_DataPath/u_decode_unit/reg_file0/N152 ), .D(n8014), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][9] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[3][25] (
.G(\u_DataPath/u_decode_unit/reg_file0/N152 ), .D(n7993), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][25] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[3][5] (
.G(\u_DataPath/u_decode_unit/reg_file0/N152 ), .D(n8023), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][5] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[3][21] (
.G(\u_DataPath/u_decode_unit/reg_file0/N152 ), .D(n7966), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][21] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[3][29] (
.G(\u_DataPath/u_decode_unit/reg_file0/N152 ), .D(n8008), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][29] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[3][13] (
.G(\u_DataPath/u_decode_unit/reg_file0/N152 ), .D(n7957), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][13] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[3][7] (
.G(\u_DataPath/u_decode_unit/reg_file0/N152 ), .D(n7951), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][7] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[3][12] (
.G(\u_DataPath/u_decode_unit/reg_file0/N152 ), .D(n7969), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][12] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[3][30] (
.G(\u_DataPath/u_decode_unit/reg_file0/N152 ), .D(n8010), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][30] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[3][23] (
.G(\u_DataPath/u_decode_unit/reg_file0/N152 ), .D(n7996), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][23] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[3][26] (
.G(\u_DataPath/u_decode_unit/reg_file0/N152 ), .D(n8005), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][26] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[3][10] (
.G(\u_DataPath/u_decode_unit/reg_file0/N152 ), .D(n7945), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][10] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[3][3] (
.G(\u_DataPath/u_decode_unit/reg_file0/N152 ), .D(n8020), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][3] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[3][19] (
.G(\u_DataPath/u_decode_unit/reg_file0/N152 ), .D(n7963), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][19] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[3][11] (
.G(\u_DataPath/u_decode_unit/reg_file0/N152 ), .D(n7942), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][11] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[3][15] (
.G(\u_DataPath/u_decode_unit/reg_file0/N152 ), .D(n7972), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][15] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[3][14] (
.G(\u_DataPath/u_decode_unit/reg_file0/N152 ), .D(n7990), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][14] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[3][27] (
.G(\u_DataPath/u_decode_unit/reg_file0/N152 ), .D(n7927), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][27] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[9][30] (
.G(\u_DataPath/u_decode_unit/reg_file0/N146 ), .D(n8011), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][30] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[8][30] (
.G(\u_DataPath/u_decode_unit/reg_file0/N147 ), .D(n8010), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][30] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[17][31] (
.G(\u_DataPath/u_decode_unit/reg_file0/N138 ), .D(n7936), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][31] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[17][0] (
.G(\u_DataPath/u_decode_unit/reg_file0/N138 ), .D(n7999), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][0] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[17][1] (
.G(\u_DataPath/u_decode_unit/reg_file0/N138 ), .D(n8026), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][1] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[17][6] (
.G(\u_DataPath/u_decode_unit/reg_file0/N138 ), .D(n8017), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][6] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[17][18] (
.G(\u_DataPath/u_decode_unit/reg_file0/N138 ), .D(n7981), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][18] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[17][2] (
.G(\u_DataPath/u_decode_unit/reg_file0/N138 ), .D(n8029), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][2] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[17][17] (
.G(\u_DataPath/u_decode_unit/reg_file0/N138 ), .D(n7987), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][17] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[17][16] (
.G(\u_DataPath/u_decode_unit/reg_file0/N138 ), .D(n7954), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][16] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[17][20] (
.G(\u_DataPath/u_decode_unit/reg_file0/N138 ), .D(n7960), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][20] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[17][8] (
.G(\u_DataPath/u_decode_unit/reg_file0/N138 ), .D(n7939), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][8] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[17][4] (
.G(\u_DataPath/u_decode_unit/reg_file0/N138 ), .D(n8032), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][4] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[17][22] (
.G(\u_DataPath/u_decode_unit/reg_file0/N138 ), .D(n7978), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][22] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[17][28] (
.G(\u_DataPath/u_decode_unit/reg_file0/N138 ), .D(n7930), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][28] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[17][24] (
.G(\u_DataPath/u_decode_unit/reg_file0/N138 ), .D(n7984), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][24] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[17][9] (
.G(\u_DataPath/u_decode_unit/reg_file0/N138 ), .D(n8014), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][9] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[17][25] (
.G(\u_DataPath/u_decode_unit/reg_file0/N138 ), .D(n7993), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][25] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[17][5] (
.G(\u_DataPath/u_decode_unit/reg_file0/N138 ), .D(n8023), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][5] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[17][21] (
.G(\u_DataPath/u_decode_unit/reg_file0/N138 ), .D(n7966), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][21] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[17][29] (
.G(\u_DataPath/u_decode_unit/reg_file0/N138 ), .D(n8008), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][29] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[17][13] (
.G(\u_DataPath/u_decode_unit/reg_file0/N138 ), .D(n7957), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][13] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[17][7] (
.G(\u_DataPath/u_decode_unit/reg_file0/N138 ), .D(n7951), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][7] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[17][12] (
.G(\u_DataPath/u_decode_unit/reg_file0/N138 ), .D(n7969), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][12] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[17][30] (
.G(\u_DataPath/u_decode_unit/reg_file0/N138 ), .D(n8012), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][30] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[17][23] (
.G(\u_DataPath/u_decode_unit/reg_file0/N138 ), .D(n7996), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][23] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[17][26] (
.G(\u_DataPath/u_decode_unit/reg_file0/N138 ), .D(n8005), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][26] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[17][10] (
.G(\u_DataPath/u_decode_unit/reg_file0/N138 ), .D(n7945), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][10] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[17][3] (
.G(\u_DataPath/u_decode_unit/reg_file0/N138 ), .D(n8020), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][3] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[17][19] (
.G(\u_DataPath/u_decode_unit/reg_file0/N138 ), .D(n7963), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][19] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[17][11] (
.G(\u_DataPath/u_decode_unit/reg_file0/N138 ), .D(n7942), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][11] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[17][15] (
.G(\u_DataPath/u_decode_unit/reg_file0/N138 ), .D(n7972), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][15] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[17][14] (
.G(\u_DataPath/u_decode_unit/reg_file0/N138 ), .D(n7990), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][14] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[17][27] (
.G(\u_DataPath/u_decode_unit/reg_file0/N138 ), .D(n7927), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][27] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[31][30] (
.G(\u_DataPath/u_decode_unit/reg_file0/N92 ), .D(n8011), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][30] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[27][30] (
.G(\u_DataPath/u_decode_unit/reg_file0/N128 ), .D(n8011), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][30] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[24][31] (
.G(\u_DataPath/u_decode_unit/reg_file0/N131 ), .D(n7935), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][31] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[26][31] (
.G(\u_DataPath/u_decode_unit/reg_file0/N129 ), .D(n7935), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][31] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[26][0] (
.G(\u_DataPath/u_decode_unit/reg_file0/N129 ), .D(n7998), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][0] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[24][0] (
.G(\u_DataPath/u_decode_unit/reg_file0/N131 ), .D(n7998), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][0] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[26][1] (
.G(\u_DataPath/u_decode_unit/reg_file0/N129 ), .D(n8025), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][1] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[24][1] (
.G(\u_DataPath/u_decode_unit/reg_file0/N131 ), .D(n8025), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][1] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[26][6] (
.G(\u_DataPath/u_decode_unit/reg_file0/N129 ), .D(n8016), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][6] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[24][6] (
.G(\u_DataPath/u_decode_unit/reg_file0/N131 ), .D(n8016), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][6] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[24][18] (
.G(\u_DataPath/u_decode_unit/reg_file0/N131 ), .D(n7980), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][18] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[26][2] (
.G(\u_DataPath/u_decode_unit/reg_file0/N129 ), .D(n8028), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][2] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[24][2] (
.G(\u_DataPath/u_decode_unit/reg_file0/N131 ), .D(n8028), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][2] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[24][17] (
.G(\u_DataPath/u_decode_unit/reg_file0/N131 ), .D(n7986), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][17] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[26][16] (
.G(\u_DataPath/u_decode_unit/reg_file0/N129 ), .D(n7953), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][16] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[24][16] (
.G(\u_DataPath/u_decode_unit/reg_file0/N131 ), .D(n7953), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][16] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[26][20] (
.G(\u_DataPath/u_decode_unit/reg_file0/N129 ), .D(n7959), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][20] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[24][20] (
.G(\u_DataPath/u_decode_unit/reg_file0/N131 ), .D(n7959), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][20] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[26][8] (
.G(\u_DataPath/u_decode_unit/reg_file0/N129 ), .D(n7938), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][8] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[24][8] (
.G(\u_DataPath/u_decode_unit/reg_file0/N131 ), .D(n7938), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][8] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[26][4] (
.G(\u_DataPath/u_decode_unit/reg_file0/N129 ), .D(n8031), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][4] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[24][4] (
.G(\u_DataPath/u_decode_unit/reg_file0/N131 ), .D(n8031), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][4] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[26][22] (
.G(\u_DataPath/u_decode_unit/reg_file0/N129 ), .D(n7977), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][22] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[24][22] (
.G(\u_DataPath/u_decode_unit/reg_file0/N131 ), .D(n7977), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][22] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[24][28] (
.G(\u_DataPath/u_decode_unit/reg_file0/N131 ), .D(n7929), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][28] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[26][24] (
.G(\u_DataPath/u_decode_unit/reg_file0/N129 ), .D(n7983), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][24] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[24][24] (
.G(\u_DataPath/u_decode_unit/reg_file0/N131 ), .D(n7983), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][24] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[24][9] (
.G(\u_DataPath/u_decode_unit/reg_file0/N131 ), .D(n8013), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][9] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[26][25] (
.G(\u_DataPath/u_decode_unit/reg_file0/N129 ), .D(n7992), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][25] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[24][25] (
.G(\u_DataPath/u_decode_unit/reg_file0/N131 ), .D(n7992), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][25] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[26][5] (
.G(\u_DataPath/u_decode_unit/reg_file0/N129 ), .D(n8022), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][5] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[24][5] (
.G(\u_DataPath/u_decode_unit/reg_file0/N131 ), .D(n8022), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][5] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[26][21] (
.G(\u_DataPath/u_decode_unit/reg_file0/N129 ), .D(n7965), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][21] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[24][21] (
.G(\u_DataPath/u_decode_unit/reg_file0/N131 ), .D(n7965), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][21] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[26][29] (
.G(\u_DataPath/u_decode_unit/reg_file0/N129 ), .D(n8007), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][29] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[24][29] (
.G(\u_DataPath/u_decode_unit/reg_file0/N131 ), .D(n8007), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][29] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[24][13] (
.G(\u_DataPath/u_decode_unit/reg_file0/N131 ), .D(n7956), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][13] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[24][7] (
.G(\u_DataPath/u_decode_unit/reg_file0/N131 ), .D(n7950), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][7] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[26][12] (
.G(\u_DataPath/u_decode_unit/reg_file0/N129 ), .D(n7968), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][12] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[24][12] (
.G(\u_DataPath/u_decode_unit/reg_file0/N131 ), .D(n7968), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][12] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[26][23] (
.G(\u_DataPath/u_decode_unit/reg_file0/N129 ), .D(n7995), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][23] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[24][23] (
.G(\u_DataPath/u_decode_unit/reg_file0/N131 ), .D(n7995), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][23] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[26][26] (
.G(\u_DataPath/u_decode_unit/reg_file0/N129 ), .D(n8004), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][26] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[24][26] (
.G(\u_DataPath/u_decode_unit/reg_file0/N131 ), .D(n8004), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][26] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[26][10] (
.G(\u_DataPath/u_decode_unit/reg_file0/N129 ), .D(n7944), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][10] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[24][10] (
.G(\u_DataPath/u_decode_unit/reg_file0/N131 ), .D(n7944), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][10] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[26][3] (
.G(\u_DataPath/u_decode_unit/reg_file0/N129 ), .D(n8019), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][3] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[24][3] (
.G(\u_DataPath/u_decode_unit/reg_file0/N131 ), .D(n8019), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][3] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[26][19] (
.G(\u_DataPath/u_decode_unit/reg_file0/N129 ), .D(n7962), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][19] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[24][19] (
.G(\u_DataPath/u_decode_unit/reg_file0/N131 ), .D(n7962), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][19] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[26][11] (
.G(\u_DataPath/u_decode_unit/reg_file0/N129 ), .D(n7941), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][11] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[24][11] (
.G(\u_DataPath/u_decode_unit/reg_file0/N131 ), .D(n7941), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][11] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[26][15] (
.G(\u_DataPath/u_decode_unit/reg_file0/N129 ), .D(n7971), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][15] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[24][15] (
.G(\u_DataPath/u_decode_unit/reg_file0/N131 ), .D(n7971), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][15] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[26][14] (
.G(\u_DataPath/u_decode_unit/reg_file0/N129 ), .D(n7989), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][14] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[24][14] (
.G(\u_DataPath/u_decode_unit/reg_file0/N131 ), .D(n7989), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][14] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[24][27] (
.G(\u_DataPath/u_decode_unit/reg_file0/N131 ), .D(n7926), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][27] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[12][31] (
.G(\u_DataPath/u_decode_unit/reg_file0/N143 ), .D(n7936), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][31] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[12][0] (
.G(\u_DataPath/u_decode_unit/reg_file0/N143 ), .D(n7999), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][0] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[12][1] (
.G(\u_DataPath/u_decode_unit/reg_file0/N143 ), .D(n8026), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][1] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[12][6] (
.G(\u_DataPath/u_decode_unit/reg_file0/N143 ), .D(n8017), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][6] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[12][18] (
.G(\u_DataPath/u_decode_unit/reg_file0/N143 ), .D(n7981), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][18] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[12][2] (
.G(\u_DataPath/u_decode_unit/reg_file0/N143 ), .D(n8030), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][2] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[12][17] (
.G(\u_DataPath/u_decode_unit/reg_file0/N143 ), .D(n7987), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][17] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[12][16] (
.G(\u_DataPath/u_decode_unit/reg_file0/N143 ), .D(n7954), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][16] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[12][20] (
.G(\u_DataPath/u_decode_unit/reg_file0/N143 ), .D(n7960), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][20] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[12][8] (
.G(\u_DataPath/u_decode_unit/reg_file0/N143 ), .D(n7939), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][8] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[12][4] (
.G(\u_DataPath/u_decode_unit/reg_file0/N143 ), .D(n8032), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][4] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[12][22] (
.G(\u_DataPath/u_decode_unit/reg_file0/N143 ), .D(n7978), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][22] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[12][28] (
.G(\u_DataPath/u_decode_unit/reg_file0/N143 ), .D(n7930), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][28] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[12][24] (
.G(\u_DataPath/u_decode_unit/reg_file0/N143 ), .D(n7984), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][24] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[12][9] (
.G(\u_DataPath/u_decode_unit/reg_file0/N143 ), .D(n8014), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][9] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[12][25] (
.G(\u_DataPath/u_decode_unit/reg_file0/N143 ), .D(n7993), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][25] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[12][5] (
.G(\u_DataPath/u_decode_unit/reg_file0/N143 ), .D(n8023), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][5] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[12][21] (
.G(\u_DataPath/u_decode_unit/reg_file0/N143 ), .D(n7966), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][21] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[12][29] (
.G(\u_DataPath/u_decode_unit/reg_file0/N143 ), .D(n8008), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][29] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[12][13] (
.G(\u_DataPath/u_decode_unit/reg_file0/N143 ), .D(n7957), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][13] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[12][7] (
.G(\u_DataPath/u_decode_unit/reg_file0/N143 ), .D(n7951), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][7] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[12][12] (
.G(\u_DataPath/u_decode_unit/reg_file0/N143 ), .D(n7969), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][12] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[12][23] (
.G(\u_DataPath/u_decode_unit/reg_file0/N143 ), .D(n7996), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][23] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[12][26] (
.G(\u_DataPath/u_decode_unit/reg_file0/N143 ), .D(n8005), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][26] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[12][10] (
.G(\u_DataPath/u_decode_unit/reg_file0/N143 ), .D(n7945), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][10] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[12][3] (
.G(\u_DataPath/u_decode_unit/reg_file0/N143 ), .D(n8021), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][3] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[12][19] (
.G(\u_DataPath/u_decode_unit/reg_file0/N143 ), .D(n7963), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][19] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[12][11] (
.G(\u_DataPath/u_decode_unit/reg_file0/N143 ), .D(n7942), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][11] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[12][15] (
.G(\u_DataPath/u_decode_unit/reg_file0/N143 ), .D(n7972), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][15] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[12][14] (
.G(\u_DataPath/u_decode_unit/reg_file0/N143 ), .D(n7990), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][14] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[12][27] (
.G(\u_DataPath/u_decode_unit/reg_file0/N143 ), .D(n7927), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][27] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[30][31] (
.G(\u_DataPath/u_decode_unit/reg_file0/N125 ), .D(n7935), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][31] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[25][31] (
.G(\u_DataPath/u_decode_unit/reg_file0/N130 ), .D(n7936), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][31] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[30][0] (
.G(\u_DataPath/u_decode_unit/reg_file0/N125 ), .D(n7998), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][0] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[25][0] (
.G(\u_DataPath/u_decode_unit/reg_file0/N130 ), .D(n7999), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][0] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[30][1] (
.G(\u_DataPath/u_decode_unit/reg_file0/N125 ), .D(n8025), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][1] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[25][1] (
.G(\u_DataPath/u_decode_unit/reg_file0/N130 ), .D(n8026), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][1] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[30][6] (
.G(\u_DataPath/u_decode_unit/reg_file0/N125 ), .D(n8016), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][6] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[25][6] (
.G(\u_DataPath/u_decode_unit/reg_file0/N130 ), .D(n8017), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][6] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[30][18] (
.G(\u_DataPath/u_decode_unit/reg_file0/N125 ), .D(n7980), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][18] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[25][18] (
.G(\u_DataPath/u_decode_unit/reg_file0/N130 ), .D(n7981), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][18] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[30][2] (
.G(\u_DataPath/u_decode_unit/reg_file0/N125 ), .D(n8028), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][2] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[25][2] (
.G(\u_DataPath/u_decode_unit/reg_file0/N130 ), .D(n8028), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][2] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[25][17] (
.G(\u_DataPath/u_decode_unit/reg_file0/N130 ), .D(n7987), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][17] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[30][16] (
.G(\u_DataPath/u_decode_unit/reg_file0/N125 ), .D(n7953), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][16] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[25][16] (
.G(\u_DataPath/u_decode_unit/reg_file0/N130 ), .D(n7954), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][16] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[30][20] (
.G(\u_DataPath/u_decode_unit/reg_file0/N125 ), .D(n7959), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][20] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[25][20] (
.G(\u_DataPath/u_decode_unit/reg_file0/N130 ), .D(n7960), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][20] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[30][8] (
.G(\u_DataPath/u_decode_unit/reg_file0/N125 ), .D(n7938), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][8] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[25][8] (
.G(\u_DataPath/u_decode_unit/reg_file0/N130 ), .D(n7939), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][8] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[25][4] (
.G(\u_DataPath/u_decode_unit/reg_file0/N130 ), .D(n8032), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][4] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[30][22] (
.G(\u_DataPath/u_decode_unit/reg_file0/N125 ), .D(n7977), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][22] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[25][22] (
.G(\u_DataPath/u_decode_unit/reg_file0/N130 ), .D(n7978), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][22] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[30][28] (
.G(\u_DataPath/u_decode_unit/reg_file0/N125 ), .D(n7929), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][28] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[25][28] (
.G(\u_DataPath/u_decode_unit/reg_file0/N130 ), .D(n7930), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][28] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[30][24] (
.G(\u_DataPath/u_decode_unit/reg_file0/N125 ), .D(n7983), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][24] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[25][24] (
.G(\u_DataPath/u_decode_unit/reg_file0/N130 ), .D(n7984), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][24] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[25][9] (
.G(\u_DataPath/u_decode_unit/reg_file0/N130 ), .D(n8014), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][9] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[30][25] (
.G(\u_DataPath/u_decode_unit/reg_file0/N125 ), .D(n7992), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][25] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[25][25] (
.G(\u_DataPath/u_decode_unit/reg_file0/N130 ), .D(n7993), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][25] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[30][5] (
.G(\u_DataPath/u_decode_unit/reg_file0/N125 ), .D(n8022), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][5] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[25][5] (
.G(\u_DataPath/u_decode_unit/reg_file0/N130 ), .D(n8023), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][5] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[30][21] (
.G(\u_DataPath/u_decode_unit/reg_file0/N125 ), .D(n7965), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][21] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[25][21] (
.G(\u_DataPath/u_decode_unit/reg_file0/N130 ), .D(n7966), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][21] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[30][29] (
.G(\u_DataPath/u_decode_unit/reg_file0/N125 ), .D(n8007), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][29] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[25][29] (
.G(\u_DataPath/u_decode_unit/reg_file0/N130 ), .D(n8008), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][29] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[25][13] (
.G(\u_DataPath/u_decode_unit/reg_file0/N130 ), .D(n7957), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][13] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[30][7] (
.G(\u_DataPath/u_decode_unit/reg_file0/N125 ), .D(n7950), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][7] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[25][7] (
.G(\u_DataPath/u_decode_unit/reg_file0/N130 ), .D(n7951), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][7] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[30][12] (
.G(\u_DataPath/u_decode_unit/reg_file0/N125 ), .D(n7968), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][12] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[25][12] (
.G(\u_DataPath/u_decode_unit/reg_file0/N130 ), .D(n7969), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][12] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[25][23] (
.G(\u_DataPath/u_decode_unit/reg_file0/N130 ), .D(n7996), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][23] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[30][26] (
.G(\u_DataPath/u_decode_unit/reg_file0/N125 ), .D(n8004), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][26] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[25][26] (
.G(\u_DataPath/u_decode_unit/reg_file0/N130 ), .D(n8005), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][26] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[30][10] (
.G(\u_DataPath/u_decode_unit/reg_file0/N125 ), .D(n7944), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][10] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[25][10] (
.G(\u_DataPath/u_decode_unit/reg_file0/N130 ), .D(n7945), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][10] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[25][3] (
.G(\u_DataPath/u_decode_unit/reg_file0/N130 ), .D(n8019), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][3] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[30][19] (
.G(\u_DataPath/u_decode_unit/reg_file0/N125 ), .D(n7962), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][19] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[25][19] (
.G(\u_DataPath/u_decode_unit/reg_file0/N130 ), .D(n7963), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][19] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[25][11] (
.G(\u_DataPath/u_decode_unit/reg_file0/N130 ), .D(n7942), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][11] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[30][15] (
.G(\u_DataPath/u_decode_unit/reg_file0/N125 ), .D(n7971), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][15] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[25][15] (
.G(\u_DataPath/u_decode_unit/reg_file0/N130 ), .D(n7972), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][15] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[30][14] (
.G(\u_DataPath/u_decode_unit/reg_file0/N125 ), .D(n7989), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][14] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[25][14] (
.G(\u_DataPath/u_decode_unit/reg_file0/N130 ), .D(n7990), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][14] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[30][27] (
.G(\u_DataPath/u_decode_unit/reg_file0/N125 ), .D(n7926), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][27] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[25][27] (
.G(\u_DataPath/u_decode_unit/reg_file0/N130 ), .D(n7927), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][27] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[13][31] (
.G(\u_DataPath/u_decode_unit/reg_file0/N142 ), .D(n7936), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][31] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[13][0] (
.G(\u_DataPath/u_decode_unit/reg_file0/N142 ), .D(n7999), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][0] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[13][1] (
.G(\u_DataPath/u_decode_unit/reg_file0/N142 ), .D(n8026), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][1] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[13][6] (
.G(\u_DataPath/u_decode_unit/reg_file0/N142 ), .D(n8017), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][6] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[13][18] (
.G(\u_DataPath/u_decode_unit/reg_file0/N142 ), .D(n7981), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][18] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[13][2] (
.G(\u_DataPath/u_decode_unit/reg_file0/N142 ), .D(n8029), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][2] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[13][17] (
.G(\u_DataPath/u_decode_unit/reg_file0/N142 ), .D(n7987), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][17] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[13][16] (
.G(\u_DataPath/u_decode_unit/reg_file0/N142 ), .D(n7954), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][16] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[13][20] (
.G(\u_DataPath/u_decode_unit/reg_file0/N142 ), .D(n7960), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][20] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[13][8] (
.G(\u_DataPath/u_decode_unit/reg_file0/N142 ), .D(n7939), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][8] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[13][4] (
.G(\u_DataPath/u_decode_unit/reg_file0/N142 ), .D(n8032), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][4] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[13][22] (
.G(\u_DataPath/u_decode_unit/reg_file0/N142 ), .D(n7978), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][22] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[13][28] (
.G(\u_DataPath/u_decode_unit/reg_file0/N142 ), .D(n7930), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][28] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[13][24] (
.G(\u_DataPath/u_decode_unit/reg_file0/N142 ), .D(n7984), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][24] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[13][9] (
.G(\u_DataPath/u_decode_unit/reg_file0/N142 ), .D(n8014), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][9] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[13][25] (
.G(\u_DataPath/u_decode_unit/reg_file0/N142 ), .D(n7993), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][25] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[13][5] (
.G(\u_DataPath/u_decode_unit/reg_file0/N142 ), .D(n8023), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][5] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[13][21] (
.G(\u_DataPath/u_decode_unit/reg_file0/N142 ), .D(n7966), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][21] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[13][29] (
.G(\u_DataPath/u_decode_unit/reg_file0/N142 ), .D(n8008), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][29] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[13][13] (
.G(\u_DataPath/u_decode_unit/reg_file0/N142 ), .D(n7957), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][13] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[13][7] (
.G(\u_DataPath/u_decode_unit/reg_file0/N142 ), .D(n7951), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][7] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[13][12] (
.G(\u_DataPath/u_decode_unit/reg_file0/N142 ), .D(n7969), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][12] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[13][30] (
.G(\u_DataPath/u_decode_unit/reg_file0/N142 ), .D(n8010), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][30] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[13][23] (
.G(\u_DataPath/u_decode_unit/reg_file0/N142 ), .D(n7996), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][23] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[13][26] (
.G(\u_DataPath/u_decode_unit/reg_file0/N142 ), .D(n8005), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][26] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[13][10] (
.G(\u_DataPath/u_decode_unit/reg_file0/N142 ), .D(n7945), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][10] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[13][3] (
.G(\u_DataPath/u_decode_unit/reg_file0/N142 ), .D(n8020), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][3] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[13][19] (
.G(\u_DataPath/u_decode_unit/reg_file0/N142 ), .D(n7963), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][19] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[13][11] (
.G(\u_DataPath/u_decode_unit/reg_file0/N142 ), .D(n7942), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][11] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[13][15] (
.G(\u_DataPath/u_decode_unit/reg_file0/N142 ), .D(n7972), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][15] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[13][14] (
.G(\u_DataPath/u_decode_unit/reg_file0/N142 ), .D(n7990), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][14] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[13][27] (
.G(\u_DataPath/u_decode_unit/reg_file0/N142 ), .D(n7927), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][27] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[10][31] (
.G(\u_DataPath/u_decode_unit/reg_file0/N145 ), .D(n7937), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][31] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[11][31] (
.G(\u_DataPath/u_decode_unit/reg_file0/N144 ), .D(n7937), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][31] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[11][0] (
.G(\u_DataPath/u_decode_unit/reg_file0/N144 ), .D(n8000), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][0] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[10][0] (
.G(\u_DataPath/u_decode_unit/reg_file0/N145 ), .D(n8000), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][0] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[11][1] (
.G(\u_DataPath/u_decode_unit/reg_file0/N144 ), .D(n8027), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][1] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[10][1] (
.G(\u_DataPath/u_decode_unit/reg_file0/N145 ), .D(n8027), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][1] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[11][6] (
.G(\u_DataPath/u_decode_unit/reg_file0/N144 ), .D(n8018), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][6] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[10][6] (
.G(\u_DataPath/u_decode_unit/reg_file0/N145 ), .D(n8018), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][6] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[11][18] (
.G(\u_DataPath/u_decode_unit/reg_file0/N144 ), .D(n7982), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][18] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[10][18] (
.G(\u_DataPath/u_decode_unit/reg_file0/N145 ), .D(n7982), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][18] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[11][2] (
.G(\u_DataPath/u_decode_unit/reg_file0/N144 ), .D(n8030), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][2] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[10][2] (
.G(\u_DataPath/u_decode_unit/reg_file0/N145 ), .D(n8030), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][2] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[11][17] (
.G(\u_DataPath/u_decode_unit/reg_file0/N144 ), .D(n7988), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][17] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[10][17] (
.G(\u_DataPath/u_decode_unit/reg_file0/N145 ), .D(n7988), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][17] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[11][16] (
.G(\u_DataPath/u_decode_unit/reg_file0/N144 ), .D(n7955), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][16] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[10][16] (
.G(\u_DataPath/u_decode_unit/reg_file0/N145 ), .D(n7955), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][16] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[11][20] (
.G(\u_DataPath/u_decode_unit/reg_file0/N144 ), .D(n7961), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][20] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[10][20] (
.G(\u_DataPath/u_decode_unit/reg_file0/N145 ), .D(n7961), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][20] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[11][8] (
.G(\u_DataPath/u_decode_unit/reg_file0/N144 ), .D(n7940), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][8] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[10][8] (
.G(\u_DataPath/u_decode_unit/reg_file0/N145 ), .D(n7940), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][8] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[11][4] (
.G(\u_DataPath/u_decode_unit/reg_file0/N144 ), .D(n8033), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][4] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[10][4] (
.G(\u_DataPath/u_decode_unit/reg_file0/N145 ), .D(n8033), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][4] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[11][22] (
.G(\u_DataPath/u_decode_unit/reg_file0/N144 ), .D(n7979), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][22] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[10][22] (
.G(\u_DataPath/u_decode_unit/reg_file0/N145 ), .D(n7979), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][22] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[11][28] (
.G(\u_DataPath/u_decode_unit/reg_file0/N144 ), .D(n7931), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][28] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[10][28] (
.G(\u_DataPath/u_decode_unit/reg_file0/N145 ), .D(n7931), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][28] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[11][24] (
.G(\u_DataPath/u_decode_unit/reg_file0/N144 ), .D(n7985), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][24] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[10][24] (
.G(\u_DataPath/u_decode_unit/reg_file0/N145 ), .D(n7985), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][24] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[11][9] (
.G(\u_DataPath/u_decode_unit/reg_file0/N144 ), .D(n8015), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][9] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[10][9] (
.G(\u_DataPath/u_decode_unit/reg_file0/N145 ), .D(n8015), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][9] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[11][25] (
.G(\u_DataPath/u_decode_unit/reg_file0/N144 ), .D(n7994), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][25] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[10][25] (
.G(\u_DataPath/u_decode_unit/reg_file0/N145 ), .D(n7994), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][25] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[11][5] (
.G(\u_DataPath/u_decode_unit/reg_file0/N144 ), .D(n8024), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][5] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[10][5] (
.G(\u_DataPath/u_decode_unit/reg_file0/N145 ), .D(n8024), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][5] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[11][21] (
.G(\u_DataPath/u_decode_unit/reg_file0/N144 ), .D(n7967), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][21] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[10][21] (
.G(\u_DataPath/u_decode_unit/reg_file0/N145 ), .D(n7967), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][21] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[11][29] (
.G(\u_DataPath/u_decode_unit/reg_file0/N144 ), .D(n8009), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][29] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[10][29] (
.G(\u_DataPath/u_decode_unit/reg_file0/N145 ), .D(n8009), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][29] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[11][13] (
.G(\u_DataPath/u_decode_unit/reg_file0/N144 ), .D(n7958), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][13] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[10][13] (
.G(\u_DataPath/u_decode_unit/reg_file0/N145 ), .D(n7958), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][13] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[11][7] (
.G(\u_DataPath/u_decode_unit/reg_file0/N144 ), .D(n7952), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][7] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[10][7] (
.G(\u_DataPath/u_decode_unit/reg_file0/N145 ), .D(n7952), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][7] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[11][12] (
.G(\u_DataPath/u_decode_unit/reg_file0/N144 ), .D(n7970), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][12] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[10][12] (
.G(\u_DataPath/u_decode_unit/reg_file0/N145 ), .D(n7970), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][12] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[11][30] (
.G(\u_DataPath/u_decode_unit/reg_file0/N144 ), .D(n8010), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][30] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[11][23] (
.G(\u_DataPath/u_decode_unit/reg_file0/N144 ), .D(n7997), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][23] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[10][23] (
.G(\u_DataPath/u_decode_unit/reg_file0/N145 ), .D(n7997), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][23] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[11][26] (
.G(\u_DataPath/u_decode_unit/reg_file0/N144 ), .D(n8006), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][26] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[10][26] (
.G(\u_DataPath/u_decode_unit/reg_file0/N145 ), .D(n8006), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][26] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[11][10] (
.G(\u_DataPath/u_decode_unit/reg_file0/N144 ), .D(n7946), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][10] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[10][10] (
.G(\u_DataPath/u_decode_unit/reg_file0/N145 ), .D(n7946), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][10] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[11][3] (
.G(\u_DataPath/u_decode_unit/reg_file0/N144 ), .D(n8021), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][3] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[10][3] (
.G(\u_DataPath/u_decode_unit/reg_file0/N145 ), .D(n8021), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][3] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[11][19] (
.G(\u_DataPath/u_decode_unit/reg_file0/N144 ), .D(n7964), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][19] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[10][19] (
.G(\u_DataPath/u_decode_unit/reg_file0/N145 ), .D(n7964), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][19] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[11][11] (
.G(\u_DataPath/u_decode_unit/reg_file0/N144 ), .D(n7943), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][11] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[10][11] (
.G(\u_DataPath/u_decode_unit/reg_file0/N145 ), .D(n7943), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][11] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[11][15] (
.G(\u_DataPath/u_decode_unit/reg_file0/N144 ), .D(n7973), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][15] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[10][15] (
.G(\u_DataPath/u_decode_unit/reg_file0/N145 ), .D(n7973), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][15] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[11][14] (
.G(\u_DataPath/u_decode_unit/reg_file0/N144 ), .D(n7991), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][14] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[10][14] (
.G(\u_DataPath/u_decode_unit/reg_file0/N145 ), .D(n7991), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][14] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[11][27] (
.G(\u_DataPath/u_decode_unit/reg_file0/N144 ), .D(n7928), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][27] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[10][27] (
.G(\u_DataPath/u_decode_unit/reg_file0/N145 ), .D(n7928), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][27] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[1][31] (
.G(\u_DataPath/u_decode_unit/reg_file0/N154 ), .D(n7936), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][31] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[7][31] (
.G(\u_DataPath/u_decode_unit/reg_file0/N148 ), .D(n7936), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][31] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[7][0] (
.G(\u_DataPath/u_decode_unit/reg_file0/N148 ), .D(n7999), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][0] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[1][0] (
.G(\u_DataPath/u_decode_unit/reg_file0/N154 ), .D(n7999), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][0] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[7][1] (
.G(\u_DataPath/u_decode_unit/reg_file0/N148 ), .D(n8026), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][1] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[1][1] (
.G(\u_DataPath/u_decode_unit/reg_file0/N154 ), .D(n8026), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][1] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[7][6] (
.G(\u_DataPath/u_decode_unit/reg_file0/N148 ), .D(n8017), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][6] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[1][6] (
.G(\u_DataPath/u_decode_unit/reg_file0/N154 ), .D(n8017), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][6] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[7][18] (
.G(\u_DataPath/u_decode_unit/reg_file0/N148 ), .D(n7981), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][18] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[1][18] (
.G(\u_DataPath/u_decode_unit/reg_file0/N154 ), .D(n7981), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][18] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[7][2] (
.G(\u_DataPath/u_decode_unit/reg_file0/N148 ), .D(n8029), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][2] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[1][2] (
.G(\u_DataPath/u_decode_unit/reg_file0/N154 ), .D(n8029), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][2] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[7][17] (
.G(\u_DataPath/u_decode_unit/reg_file0/N148 ), .D(n7987), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][17] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[1][17] (
.G(\u_DataPath/u_decode_unit/reg_file0/N154 ), .D(n7987), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][17] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[7][16] (
.G(\u_DataPath/u_decode_unit/reg_file0/N148 ), .D(n7954), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][16] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[1][16] (
.G(\u_DataPath/u_decode_unit/reg_file0/N154 ), .D(n7954), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][16] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[7][20] (
.G(\u_DataPath/u_decode_unit/reg_file0/N148 ), .D(n7960), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][20] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[1][20] (
.G(\u_DataPath/u_decode_unit/reg_file0/N154 ), .D(n7960), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][20] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[7][8] (
.G(\u_DataPath/u_decode_unit/reg_file0/N148 ), .D(n7939), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][8] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[1][8] (
.G(\u_DataPath/u_decode_unit/reg_file0/N154 ), .D(n7939), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][8] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[7][4] (
.G(\u_DataPath/u_decode_unit/reg_file0/N148 ), .D(n8032), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][4] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[1][4] (
.G(\u_DataPath/u_decode_unit/reg_file0/N154 ), .D(n8032), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][4] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[7][22] (
.G(\u_DataPath/u_decode_unit/reg_file0/N148 ), .D(n7978), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][22] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[1][22] (
.G(\u_DataPath/u_decode_unit/reg_file0/N154 ), .D(n7978), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][22] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[7][28] (
.G(\u_DataPath/u_decode_unit/reg_file0/N148 ), .D(n7930), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][28] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[1][28] (
.G(\u_DataPath/u_decode_unit/reg_file0/N154 ), .D(n7930), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][28] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[7][24] (
.G(\u_DataPath/u_decode_unit/reg_file0/N148 ), .D(n7984), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][24] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[1][24] (
.G(\u_DataPath/u_decode_unit/reg_file0/N154 ), .D(n7984), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][24] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[7][9] (
.G(\u_DataPath/u_decode_unit/reg_file0/N148 ), .D(n8014), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][9] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[1][9] (
.G(\u_DataPath/u_decode_unit/reg_file0/N154 ), .D(n8014), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][9] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[7][25] (
.G(\u_DataPath/u_decode_unit/reg_file0/N148 ), .D(n7993), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][25] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[1][25] (
.G(\u_DataPath/u_decode_unit/reg_file0/N154 ), .D(n7993), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][25] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[7][5] (
.G(\u_DataPath/u_decode_unit/reg_file0/N148 ), .D(n8023), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][5] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[1][5] (
.G(\u_DataPath/u_decode_unit/reg_file0/N154 ), .D(n8023), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][5] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[7][21] (
.G(\u_DataPath/u_decode_unit/reg_file0/N148 ), .D(n7966), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][21] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[1][21] (
.G(\u_DataPath/u_decode_unit/reg_file0/N154 ), .D(n7966), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][21] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[7][29] (
.G(\u_DataPath/u_decode_unit/reg_file0/N148 ), .D(n8008), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][29] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[1][29] (
.G(\u_DataPath/u_decode_unit/reg_file0/N154 ), .D(n8008), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][29] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[7][13] (
.G(\u_DataPath/u_decode_unit/reg_file0/N148 ), .D(n7957), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][13] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[1][13] (
.G(\u_DataPath/u_decode_unit/reg_file0/N154 ), .D(n7957), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][13] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[7][7] (
.G(\u_DataPath/u_decode_unit/reg_file0/N148 ), .D(n7951), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][7] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[1][7] (
.G(\u_DataPath/u_decode_unit/reg_file0/N154 ), .D(n7951), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][7] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[7][12] (
.G(\u_DataPath/u_decode_unit/reg_file0/N148 ), .D(n7969), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][12] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[1][12] (
.G(\u_DataPath/u_decode_unit/reg_file0/N154 ), .D(n7969), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][12] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[7][23] (
.G(\u_DataPath/u_decode_unit/reg_file0/N148 ), .D(n7996), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][23] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[1][23] (
.G(\u_DataPath/u_decode_unit/reg_file0/N154 ), .D(n7996), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][23] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[7][26] (
.G(\u_DataPath/u_decode_unit/reg_file0/N148 ), .D(n8005), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][26] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[1][26] (
.G(\u_DataPath/u_decode_unit/reg_file0/N154 ), .D(n8005), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][26] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[7][10] (
.G(\u_DataPath/u_decode_unit/reg_file0/N148 ), .D(n7945), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][10] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[1][10] (
.G(\u_DataPath/u_decode_unit/reg_file0/N154 ), .D(n7945), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][10] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[7][3] (
.G(\u_DataPath/u_decode_unit/reg_file0/N148 ), .D(n8020), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][3] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[1][3] (
.G(\u_DataPath/u_decode_unit/reg_file0/N154 ), .D(n8020), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][3] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[7][19] (
.G(\u_DataPath/u_decode_unit/reg_file0/N148 ), .D(n7963), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][19] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[1][19] (
.G(\u_DataPath/u_decode_unit/reg_file0/N154 ), .D(n7963), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][19] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[7][11] (
.G(\u_DataPath/u_decode_unit/reg_file0/N148 ), .D(n7942), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][11] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[1][11] (
.G(\u_DataPath/u_decode_unit/reg_file0/N154 ), .D(n7942), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][11] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[7][15] (
.G(\u_DataPath/u_decode_unit/reg_file0/N148 ), .D(n7972), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][15] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[1][15] (
.G(\u_DataPath/u_decode_unit/reg_file0/N154 ), .D(n7972), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][15] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[7][14] (
.G(\u_DataPath/u_decode_unit/reg_file0/N148 ), .D(n7990), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][14] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[1][14] (
.G(\u_DataPath/u_decode_unit/reg_file0/N154 ), .D(n7990), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][14] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[7][27] (
.G(\u_DataPath/u_decode_unit/reg_file0/N148 ), .D(n7927), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][27] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[1][27] (
.G(\u_DataPath/u_decode_unit/reg_file0/N154 ), .D(n7927), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][27] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[29][30] (
.G(\u_DataPath/u_decode_unit/reg_file0/N126 ), .D(n8012), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][30] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[20][31] (
.G(\u_DataPath/u_decode_unit/reg_file0/N135 ), .D(n7935), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][31] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[20][0] (
.G(\u_DataPath/u_decode_unit/reg_file0/N135 ), .D(n7998), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][0] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[20][1] (
.G(\u_DataPath/u_decode_unit/reg_file0/N135 ), .D(n8025), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][1] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[20][6] (
.G(\u_DataPath/u_decode_unit/reg_file0/N135 ), .D(n8016), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][6] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[20][18] (
.G(\u_DataPath/u_decode_unit/reg_file0/N135 ), .D(n7980), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][18] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[20][2] (
.G(\u_DataPath/u_decode_unit/reg_file0/N135 ), .D(n8029), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][2] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[20][17] (
.G(\u_DataPath/u_decode_unit/reg_file0/N135 ), .D(n7986), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][17] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[20][16] (
.G(\u_DataPath/u_decode_unit/reg_file0/N135 ), .D(n7953), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][16] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[20][20] (
.G(\u_DataPath/u_decode_unit/reg_file0/N135 ), .D(n7959), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][20] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[20][8] (
.G(\u_DataPath/u_decode_unit/reg_file0/N135 ), .D(n7938), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][8] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[20][4] (
.G(\u_DataPath/u_decode_unit/reg_file0/N135 ), .D(n8031), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][4] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[20][22] (
.G(\u_DataPath/u_decode_unit/reg_file0/N135 ), .D(n7977), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][22] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[20][28] (
.G(\u_DataPath/u_decode_unit/reg_file0/N135 ), .D(n7929), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][28] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[20][24] (
.G(\u_DataPath/u_decode_unit/reg_file0/N135 ), .D(n7983), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][24] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[20][9] (
.G(\u_DataPath/u_decode_unit/reg_file0/N135 ), .D(n8013), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][9] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[20][25] (
.G(\u_DataPath/u_decode_unit/reg_file0/N135 ), .D(n7992), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][25] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[20][5] (
.G(\u_DataPath/u_decode_unit/reg_file0/N135 ), .D(n8022), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][5] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[20][21] (
.G(\u_DataPath/u_decode_unit/reg_file0/N135 ), .D(n7965), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][21] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[20][29] (
.G(\u_DataPath/u_decode_unit/reg_file0/N135 ), .D(n8007), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][29] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[20][13] (
.G(\u_DataPath/u_decode_unit/reg_file0/N135 ), .D(n7956), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][13] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[20][7] (
.G(\u_DataPath/u_decode_unit/reg_file0/N135 ), .D(n7950), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][7] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[20][12] (
.G(\u_DataPath/u_decode_unit/reg_file0/N135 ), .D(n7968), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][12] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[20][30] (
.G(\u_DataPath/u_decode_unit/reg_file0/N135 ), .D(n8011), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][30] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[20][23] (
.G(\u_DataPath/u_decode_unit/reg_file0/N135 ), .D(n7995), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][23] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[20][26] (
.G(\u_DataPath/u_decode_unit/reg_file0/N135 ), .D(n8004), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][26] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[20][10] (
.G(\u_DataPath/u_decode_unit/reg_file0/N135 ), .D(n7944), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][10] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[20][3] (
.G(\u_DataPath/u_decode_unit/reg_file0/N135 ), .D(n8020), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][3] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[20][19] (
.G(\u_DataPath/u_decode_unit/reg_file0/N135 ), .D(n7962), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][19] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[20][11] (
.G(\u_DataPath/u_decode_unit/reg_file0/N135 ), .D(n7941), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][11] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[20][15] (
.G(\u_DataPath/u_decode_unit/reg_file0/N135 ), .D(n7971), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][15] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[20][14] (
.G(\u_DataPath/u_decode_unit/reg_file0/N135 ), .D(n7989), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][14] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[20][27] (
.G(\u_DataPath/u_decode_unit/reg_file0/N135 ), .D(n7926), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][27] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[6][31] (
.G(\u_DataPath/u_decode_unit/reg_file0/N149 ), .D(n7936), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][31] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[6][0] (
.G(\u_DataPath/u_decode_unit/reg_file0/N149 ), .D(n7999), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][0] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[6][1] (
.G(\u_DataPath/u_decode_unit/reg_file0/N149 ), .D(n8026), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][1] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[6][6] (
.G(\u_DataPath/u_decode_unit/reg_file0/N149 ), .D(n8017), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][6] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[6][18] (
.G(\u_DataPath/u_decode_unit/reg_file0/N149 ), .D(n7981), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][18] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[6][2] (
.G(\u_DataPath/u_decode_unit/reg_file0/N149 ), .D(n8030), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][2] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[6][17] (
.G(\u_DataPath/u_decode_unit/reg_file0/N149 ), .D(n7987), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][17] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[6][16] (
.G(\u_DataPath/u_decode_unit/reg_file0/N149 ), .D(n7954), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][16] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[6][20] (
.G(\u_DataPath/u_decode_unit/reg_file0/N149 ), .D(n7960), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][20] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[6][8] (
.G(\u_DataPath/u_decode_unit/reg_file0/N149 ), .D(n7939), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][8] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[6][4] (
.G(\u_DataPath/u_decode_unit/reg_file0/N149 ), .D(n8032), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][4] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[6][22] (
.G(\u_DataPath/u_decode_unit/reg_file0/N149 ), .D(n7978), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][22] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[6][28] (
.G(\u_DataPath/u_decode_unit/reg_file0/N149 ), .D(n7930), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][28] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[6][24] (
.G(\u_DataPath/u_decode_unit/reg_file0/N149 ), .D(n7984), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][24] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[6][9] (
.G(\u_DataPath/u_decode_unit/reg_file0/N149 ), .D(n8014), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][9] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[6][25] (
.G(\u_DataPath/u_decode_unit/reg_file0/N149 ), .D(n7993), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][25] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[6][5] (
.G(\u_DataPath/u_decode_unit/reg_file0/N149 ), .D(n8023), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][5] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[6][21] (
.G(\u_DataPath/u_decode_unit/reg_file0/N149 ), .D(n7966), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][21] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[6][29] (
.G(\u_DataPath/u_decode_unit/reg_file0/N149 ), .D(n8008), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][29] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[6][13] (
.G(\u_DataPath/u_decode_unit/reg_file0/N149 ), .D(n7957), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][13] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[6][7] (
.G(\u_DataPath/u_decode_unit/reg_file0/N149 ), .D(n7951), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][7] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[6][12] (
.G(\u_DataPath/u_decode_unit/reg_file0/N149 ), .D(n7969), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][12] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[14][30] (
.G(\u_DataPath/u_decode_unit/reg_file0/N141 ), .D(n8010), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][30] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[6][30] (
.G(\u_DataPath/u_decode_unit/reg_file0/N149 ), .D(n8010), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][30] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[2][30] (
.G(\u_DataPath/u_decode_unit/reg_file0/N153 ), .D(n8011), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][30] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[6][23] (
.G(\u_DataPath/u_decode_unit/reg_file0/N149 ), .D(n7996), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][23] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[6][26] (
.G(\u_DataPath/u_decode_unit/reg_file0/N149 ), .D(n8005), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][26] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[6][10] (
.G(\u_DataPath/u_decode_unit/reg_file0/N149 ), .D(n7945), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][10] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[6][3] (
.G(\u_DataPath/u_decode_unit/reg_file0/N149 ), .D(n8021), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][3] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[6][19] (
.G(\u_DataPath/u_decode_unit/reg_file0/N149 ), .D(n7963), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][19] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[6][11] (
.G(\u_DataPath/u_decode_unit/reg_file0/N149 ), .D(n7942), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][11] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[6][15] (
.G(\u_DataPath/u_decode_unit/reg_file0/N149 ), .D(n7972), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][15] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[6][14] (
.G(\u_DataPath/u_decode_unit/reg_file0/N149 ), .D(n7990), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][14] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[6][27] (
.G(\u_DataPath/u_decode_unit/reg_file0/N149 ), .D(n7927), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][27] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[15][31] (
.G(\u_DataPath/u_decode_unit/reg_file0/N140 ), .D(n7937), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][31] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[15][0] (
.G(\u_DataPath/u_decode_unit/reg_file0/N140 ), .D(n8000), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][0] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[15][1] (
.G(\u_DataPath/u_decode_unit/reg_file0/N140 ), .D(n8027), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][1] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[15][6] (
.G(\u_DataPath/u_decode_unit/reg_file0/N140 ), .D(n8018), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][6] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[15][18] (
.G(\u_DataPath/u_decode_unit/reg_file0/N140 ), .D(n7982), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][18] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[15][2] (
.G(\u_DataPath/u_decode_unit/reg_file0/N140 ), .D(n8030), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][2] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[15][17] (
.G(\u_DataPath/u_decode_unit/reg_file0/N140 ), .D(n7988), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][17] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[15][16] (
.G(\u_DataPath/u_decode_unit/reg_file0/N140 ), .D(n7955), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][16] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[15][20] (
.G(\u_DataPath/u_decode_unit/reg_file0/N140 ), .D(n7961), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][20] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[15][8] (
.G(\u_DataPath/u_decode_unit/reg_file0/N140 ), .D(n7940), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][8] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[15][4] (
.G(\u_DataPath/u_decode_unit/reg_file0/N140 ), .D(n8033), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][4] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[15][22] (
.G(\u_DataPath/u_decode_unit/reg_file0/N140 ), .D(n7979), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][22] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[15][28] (
.G(\u_DataPath/u_decode_unit/reg_file0/N140 ), .D(n7931), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][28] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[15][24] (
.G(\u_DataPath/u_decode_unit/reg_file0/N140 ), .D(n7985), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][24] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[15][9] (
.G(\u_DataPath/u_decode_unit/reg_file0/N140 ), .D(n8015), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][9] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[15][25] (
.G(\u_DataPath/u_decode_unit/reg_file0/N140 ), .D(n7994), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][25] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[15][5] (
.G(\u_DataPath/u_decode_unit/reg_file0/N140 ), .D(n8024), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][5] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[15][21] (
.G(\u_DataPath/u_decode_unit/reg_file0/N140 ), .D(n7967), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][21] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[15][29] (
.G(\u_DataPath/u_decode_unit/reg_file0/N140 ), .D(n8009), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][29] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[15][13] (
.G(\u_DataPath/u_decode_unit/reg_file0/N140 ), .D(n7958), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][13] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[15][7] (
.G(\u_DataPath/u_decode_unit/reg_file0/N140 ), .D(n7952), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][7] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[15][12] (
.G(\u_DataPath/u_decode_unit/reg_file0/N140 ), .D(n7970), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][12] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[15][30] (
.G(\u_DataPath/u_decode_unit/reg_file0/N140 ), .D(n8011), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][30] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[15][23] (
.G(\u_DataPath/u_decode_unit/reg_file0/N140 ), .D(n7997), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][23] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[15][26] (
.G(\u_DataPath/u_decode_unit/reg_file0/N140 ), .D(n8006), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][26] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[15][10] (
.G(\u_DataPath/u_decode_unit/reg_file0/N140 ), .D(n7946), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][10] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[15][3] (
.G(\u_DataPath/u_decode_unit/reg_file0/N140 ), .D(n8021), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][3] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[15][19] (
.G(\u_DataPath/u_decode_unit/reg_file0/N140 ), .D(n7964), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][19] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[15][11] (
.G(\u_DataPath/u_decode_unit/reg_file0/N140 ), .D(n7943), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][11] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[15][15] (
.G(\u_DataPath/u_decode_unit/reg_file0/N140 ), .D(n7973), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][15] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[15][14] (
.G(\u_DataPath/u_decode_unit/reg_file0/N140 ), .D(n7991), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][14] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[15][27] (
.G(\u_DataPath/u_decode_unit/reg_file0/N140 ), .D(n7928), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][27] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[8][31] (
.G(\u_DataPath/u_decode_unit/reg_file0/N147 ), .D(n7936), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][31] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[16][31] (
.G(\u_DataPath/u_decode_unit/reg_file0/N139 ), .D(n7935), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][31] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[16][0] (
.G(\u_DataPath/u_decode_unit/reg_file0/N139 ), .D(n7998), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][0] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[8][0] (
.G(\u_DataPath/u_decode_unit/reg_file0/N147 ), .D(n7999), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][0] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[16][1] (
.G(\u_DataPath/u_decode_unit/reg_file0/N139 ), .D(n8025), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][1] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[8][1] (
.G(\u_DataPath/u_decode_unit/reg_file0/N147 ), .D(n8026), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][1] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[16][6] (
.G(\u_DataPath/u_decode_unit/reg_file0/N139 ), .D(n8016), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][6] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[8][6] (
.G(\u_DataPath/u_decode_unit/reg_file0/N147 ), .D(n8017), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][6] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[16][18] (
.G(\u_DataPath/u_decode_unit/reg_file0/N139 ), .D(n7980), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][18] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[8][18] (
.G(\u_DataPath/u_decode_unit/reg_file0/N147 ), .D(n7981), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][18] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[16][2] (
.G(\u_DataPath/u_decode_unit/reg_file0/N139 ), .D(n8028), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][2] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[8][2] (
.G(\u_DataPath/u_decode_unit/reg_file0/N147 ), .D(n8029), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][2] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[16][17] (
.G(\u_DataPath/u_decode_unit/reg_file0/N139 ), .D(n7986), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][17] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[8][17] (
.G(\u_DataPath/u_decode_unit/reg_file0/N147 ), .D(n7987), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][17] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[16][16] (
.G(\u_DataPath/u_decode_unit/reg_file0/N139 ), .D(n7953), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][16] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[8][16] (
.G(\u_DataPath/u_decode_unit/reg_file0/N147 ), .D(n7954), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][16] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[16][20] (
.G(\u_DataPath/u_decode_unit/reg_file0/N139 ), .D(n7959), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][20] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[8][20] (
.G(\u_DataPath/u_decode_unit/reg_file0/N147 ), .D(n7960), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][20] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[16][8] (
.G(\u_DataPath/u_decode_unit/reg_file0/N139 ), .D(n7938), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][8] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[8][8] (
.G(\u_DataPath/u_decode_unit/reg_file0/N147 ), .D(n7939), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][8] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[16][4] (
.G(\u_DataPath/u_decode_unit/reg_file0/N139 ), .D(n8031), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][4] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[8][4] (
.G(\u_DataPath/u_decode_unit/reg_file0/N147 ), .D(n8032), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][4] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[16][22] (
.G(\u_DataPath/u_decode_unit/reg_file0/N139 ), .D(n7977), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][22] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[8][22] (
.G(\u_DataPath/u_decode_unit/reg_file0/N147 ), .D(n7978), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][22] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[16][28] (
.G(\u_DataPath/u_decode_unit/reg_file0/N139 ), .D(n7929), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][28] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[8][28] (
.G(\u_DataPath/u_decode_unit/reg_file0/N147 ), .D(n7930), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][28] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[16][24] (
.G(\u_DataPath/u_decode_unit/reg_file0/N139 ), .D(n7983), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][24] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[8][24] (
.G(\u_DataPath/u_decode_unit/reg_file0/N147 ), .D(n7984), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][24] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[16][9] (
.G(\u_DataPath/u_decode_unit/reg_file0/N139 ), .D(n8013), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][9] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[8][9] (
.G(\u_DataPath/u_decode_unit/reg_file0/N147 ), .D(n8014), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][9] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[16][25] (
.G(\u_DataPath/u_decode_unit/reg_file0/N139 ), .D(n7992), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][25] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[8][25] (
.G(\u_DataPath/u_decode_unit/reg_file0/N147 ), .D(n7993), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][25] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[16][5] (
.G(\u_DataPath/u_decode_unit/reg_file0/N139 ), .D(n8022), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][5] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[8][5] (
.G(\u_DataPath/u_decode_unit/reg_file0/N147 ), .D(n8023), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][5] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[16][21] (
.G(\u_DataPath/u_decode_unit/reg_file0/N139 ), .D(n7965), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][21] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[8][21] (
.G(\u_DataPath/u_decode_unit/reg_file0/N147 ), .D(n7966), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][21] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[16][29] (
.G(\u_DataPath/u_decode_unit/reg_file0/N139 ), .D(n8007), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][29] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[8][29] (
.G(\u_DataPath/u_decode_unit/reg_file0/N147 ), .D(n8008), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][29] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[16][13] (
.G(\u_DataPath/u_decode_unit/reg_file0/N139 ), .D(n7956), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][13] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[8][13] (
.G(\u_DataPath/u_decode_unit/reg_file0/N147 ), .D(n7957), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][13] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[16][7] (
.G(\u_DataPath/u_decode_unit/reg_file0/N139 ), .D(n7950), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][7] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[8][7] (
.G(\u_DataPath/u_decode_unit/reg_file0/N147 ), .D(n7951), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][7] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[16][12] (
.G(\u_DataPath/u_decode_unit/reg_file0/N139 ), .D(n7968), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][12] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[8][12] (
.G(\u_DataPath/u_decode_unit/reg_file0/N147 ), .D(n7969), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][12] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[16][30] (
.G(\u_DataPath/u_decode_unit/reg_file0/N139 ), .D(n8012), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][30] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[12][30] (
.G(\u_DataPath/u_decode_unit/reg_file0/N143 ), .D(n8010), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][30] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[16][23] (
.G(\u_DataPath/u_decode_unit/reg_file0/N139 ), .D(n7995), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][23] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[8][23] (
.G(\u_DataPath/u_decode_unit/reg_file0/N147 ), .D(n7996), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][23] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[16][26] (
.G(\u_DataPath/u_decode_unit/reg_file0/N139 ), .D(n8004), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][26] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[8][26] (
.G(\u_DataPath/u_decode_unit/reg_file0/N147 ), .D(n8005), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][26] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[16][10] (
.G(\u_DataPath/u_decode_unit/reg_file0/N139 ), .D(n7944), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][10] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[8][10] (
.G(\u_DataPath/u_decode_unit/reg_file0/N147 ), .D(n7945), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][10] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[16][3] (
.G(\u_DataPath/u_decode_unit/reg_file0/N139 ), .D(n8019), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][3] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[8][3] (
.G(\u_DataPath/u_decode_unit/reg_file0/N147 ), .D(n8020), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][3] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[16][19] (
.G(\u_DataPath/u_decode_unit/reg_file0/N139 ), .D(n7962), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][19] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[8][19] (
.G(\u_DataPath/u_decode_unit/reg_file0/N147 ), .D(n7963), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][19] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[16][11] (
.G(\u_DataPath/u_decode_unit/reg_file0/N139 ), .D(n7941), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][11] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[8][11] (
.G(\u_DataPath/u_decode_unit/reg_file0/N147 ), .D(n7942), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][11] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[16][15] (
.G(\u_DataPath/u_decode_unit/reg_file0/N139 ), .D(n7971), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][15] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[8][15] (
.G(\u_DataPath/u_decode_unit/reg_file0/N147 ), .D(n7972), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][15] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[16][14] (
.G(\u_DataPath/u_decode_unit/reg_file0/N139 ), .D(n7989), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][14] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[8][14] (
.G(\u_DataPath/u_decode_unit/reg_file0/N147 ), .D(n7990), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][14] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[16][27] (
.G(\u_DataPath/u_decode_unit/reg_file0/N139 ), .D(n7926), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][27] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[8][27] (
.G(\u_DataPath/u_decode_unit/reg_file0/N147 ), .D(n7927), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][27] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[26][30] (
.G(\u_DataPath/u_decode_unit/reg_file0/N129 ), .D(n8011), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][30] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[24][30] (
.G(\u_DataPath/u_decode_unit/reg_file0/N131 ), .D(n8011), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][30] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[14][31] (
.G(\u_DataPath/u_decode_unit/reg_file0/N141 ), .D(n7937), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][31] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[14][0] (
.G(\u_DataPath/u_decode_unit/reg_file0/N141 ), .D(n8000), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][0] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[14][1] (
.G(\u_DataPath/u_decode_unit/reg_file0/N141 ), .D(n8027), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][1] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[14][6] (
.G(\u_DataPath/u_decode_unit/reg_file0/N141 ), .D(n8018), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][6] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[14][18] (
.G(\u_DataPath/u_decode_unit/reg_file0/N141 ), .D(n7982), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][18] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[14][2] (
.G(\u_DataPath/u_decode_unit/reg_file0/N141 ), .D(n8030), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][2] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[14][17] (
.G(\u_DataPath/u_decode_unit/reg_file0/N141 ), .D(n7988), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][17] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[14][16] (
.G(\u_DataPath/u_decode_unit/reg_file0/N141 ), .D(n7955), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][16] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[14][20] (
.G(\u_DataPath/u_decode_unit/reg_file0/N141 ), .D(n7961), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][20] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[14][8] (
.G(\u_DataPath/u_decode_unit/reg_file0/N141 ), .D(n7940), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][8] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[14][4] (
.G(\u_DataPath/u_decode_unit/reg_file0/N141 ), .D(n8033), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][4] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[14][22] (
.G(\u_DataPath/u_decode_unit/reg_file0/N141 ), .D(n7979), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][22] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[14][28] (
.G(\u_DataPath/u_decode_unit/reg_file0/N141 ), .D(n7931), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][28] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[14][24] (
.G(\u_DataPath/u_decode_unit/reg_file0/N141 ), .D(n7985), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][24] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[14][9] (
.G(\u_DataPath/u_decode_unit/reg_file0/N141 ), .D(n8015), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][9] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[14][25] (
.G(\u_DataPath/u_decode_unit/reg_file0/N141 ), .D(n7994), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][25] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[14][5] (
.G(\u_DataPath/u_decode_unit/reg_file0/N141 ), .D(n8024), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][5] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[14][21] (
.G(\u_DataPath/u_decode_unit/reg_file0/N141 ), .D(n7967), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][21] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[14][29] (
.G(\u_DataPath/u_decode_unit/reg_file0/N141 ), .D(n8009), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][29] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[14][13] (
.G(\u_DataPath/u_decode_unit/reg_file0/N141 ), .D(n7958), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][13] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[14][7] (
.G(\u_DataPath/u_decode_unit/reg_file0/N141 ), .D(n7952), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][7] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[14][12] (
.G(\u_DataPath/u_decode_unit/reg_file0/N141 ), .D(n7970), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][12] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[14][23] (
.G(\u_DataPath/u_decode_unit/reg_file0/N141 ), .D(n7997), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][23] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[14][26] (
.G(\u_DataPath/u_decode_unit/reg_file0/N141 ), .D(n8006), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][26] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[14][10] (
.G(\u_DataPath/u_decode_unit/reg_file0/N141 ), .D(n7946), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][10] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[14][3] (
.G(\u_DataPath/u_decode_unit/reg_file0/N141 ), .D(n8021), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][3] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[14][19] (
.G(\u_DataPath/u_decode_unit/reg_file0/N141 ), .D(n7964), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][19] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[14][11] (
.G(\u_DataPath/u_decode_unit/reg_file0/N141 ), .D(n7943), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][11] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[14][15] (
.G(\u_DataPath/u_decode_unit/reg_file0/N141 ), .D(n7973), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][15] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[14][14] (
.G(\u_DataPath/u_decode_unit/reg_file0/N141 ), .D(n7991), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][14] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[14][27] (
.G(\u_DataPath/u_decode_unit/reg_file0/N141 ), .D(n7928), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][27] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[21][31] (
.G(\u_DataPath/u_decode_unit/reg_file0/N134 ), .D(n7935), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][31] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[21][0] (
.G(\u_DataPath/u_decode_unit/reg_file0/N134 ), .D(n7998), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][0] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[21][1] (
.G(\u_DataPath/u_decode_unit/reg_file0/N134 ), .D(n8025), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][1] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[21][6] (
.G(\u_DataPath/u_decode_unit/reg_file0/N134 ), .D(n8016), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][6] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[21][18] (
.G(\u_DataPath/u_decode_unit/reg_file0/N134 ), .D(n7980), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][18] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[21][2] (
.G(\u_DataPath/u_decode_unit/reg_file0/N134 ), .D(n8028), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][2] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[21][17] (
.G(\u_DataPath/u_decode_unit/reg_file0/N134 ), .D(n7986), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][17] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[21][16] (
.G(\u_DataPath/u_decode_unit/reg_file0/N134 ), .D(n7953), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][16] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[21][20] (
.G(\u_DataPath/u_decode_unit/reg_file0/N134 ), .D(n7959), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][20] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[21][8] (
.G(\u_DataPath/u_decode_unit/reg_file0/N134 ), .D(n7938), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][8] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[21][4] (
.G(\u_DataPath/u_decode_unit/reg_file0/N134 ), .D(n8031), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][4] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[21][22] (
.G(\u_DataPath/u_decode_unit/reg_file0/N134 ), .D(n7977), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][22] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[21][28] (
.G(\u_DataPath/u_decode_unit/reg_file0/N134 ), .D(n7929), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][28] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[21][24] (
.G(\u_DataPath/u_decode_unit/reg_file0/N134 ), .D(n7983), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][24] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[21][9] (
.G(\u_DataPath/u_decode_unit/reg_file0/N134 ), .D(n8013), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][9] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[21][25] (
.G(\u_DataPath/u_decode_unit/reg_file0/N134 ), .D(n7992), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][25] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[21][5] (
.G(\u_DataPath/u_decode_unit/reg_file0/N134 ), .D(n8022), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][5] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[21][21] (
.G(\u_DataPath/u_decode_unit/reg_file0/N134 ), .D(n7965), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][21] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[21][29] (
.G(\u_DataPath/u_decode_unit/reg_file0/N134 ), .D(n8007), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][29] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[21][13] (
.G(\u_DataPath/u_decode_unit/reg_file0/N134 ), .D(n7956), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][13] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[21][7] (
.G(\u_DataPath/u_decode_unit/reg_file0/N134 ), .D(n7950), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][7] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[21][12] (
.G(\u_DataPath/u_decode_unit/reg_file0/N134 ), .D(n7968), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][12] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[21][30] (
.G(\u_DataPath/u_decode_unit/reg_file0/N134 ), .D(n8011), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][30] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[21][23] (
.G(\u_DataPath/u_decode_unit/reg_file0/N134 ), .D(n7995), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][23] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[21][26] (
.G(\u_DataPath/u_decode_unit/reg_file0/N134 ), .D(n8004), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][26] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[21][10] (
.G(\u_DataPath/u_decode_unit/reg_file0/N134 ), .D(n7944), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][10] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[21][3] (
.G(\u_DataPath/u_decode_unit/reg_file0/N134 ), .D(n8019), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][3] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[21][19] (
.G(\u_DataPath/u_decode_unit/reg_file0/N134 ), .D(n7962), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][19] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[21][11] (
.G(\u_DataPath/u_decode_unit/reg_file0/N134 ), .D(n7941), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][11] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[21][15] (
.G(\u_DataPath/u_decode_unit/reg_file0/N134 ), .D(n7971), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][15] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[21][14] (
.G(\u_DataPath/u_decode_unit/reg_file0/N134 ), .D(n7989), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][14] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[21][27] (
.G(\u_DataPath/u_decode_unit/reg_file0/N134 ), .D(n7926), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][27] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[22][31] (
.G(\u_DataPath/u_decode_unit/reg_file0/N133 ), .D(n7935), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][31] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[28][31] (
.G(\u_DataPath/u_decode_unit/reg_file0/N127 ), .D(n7935), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][31] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[22][11] (
.G(\u_DataPath/u_decode_unit/reg_file0/N133 ), .D(n7941), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][11] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[29][0] (
.G(\u_DataPath/u_decode_unit/reg_file0/N126 ), .D(n7999), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][0] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[22][0] (
.G(\u_DataPath/u_decode_unit/reg_file0/N133 ), .D(n7998), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][0] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[29][1] (
.G(\u_DataPath/u_decode_unit/reg_file0/N126 ), .D(n8026), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][1] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[22][1] (
.G(\u_DataPath/u_decode_unit/reg_file0/N133 ), .D(n8025), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][1] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[22][9] (
.G(\u_DataPath/u_decode_unit/reg_file0/N133 ), .D(n8013), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][9] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[29][6] (
.G(\u_DataPath/u_decode_unit/reg_file0/N126 ), .D(n8017), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][6] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[28][6] (
.G(\u_DataPath/u_decode_unit/reg_file0/N127 ), .D(n8016), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][6] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[22][6] (
.G(\u_DataPath/u_decode_unit/reg_file0/N133 ), .D(n8016), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][6] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[29][18] (
.G(\u_DataPath/u_decode_unit/reg_file0/N126 ), .D(n7981), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][18] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[28][18] (
.G(\u_DataPath/u_decode_unit/reg_file0/N127 ), .D(n7980), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][18] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[22][18] (
.G(\u_DataPath/u_decode_unit/reg_file0/N133 ), .D(n7980), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][18] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[29][31] (
.G(\u_DataPath/u_decode_unit/reg_file0/N126 ), .D(n7936), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][31] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[29][2] (
.G(\u_DataPath/u_decode_unit/reg_file0/N126 ), .D(n8028), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][2] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[28][2] (
.G(\u_DataPath/u_decode_unit/reg_file0/N127 ), .D(n8028), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][2] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[22][2] (
.G(\u_DataPath/u_decode_unit/reg_file0/N133 ), .D(n8029), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][2] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[28][17] (
.G(\u_DataPath/u_decode_unit/reg_file0/N127 ), .D(n7986), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][17] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[22][17] (
.G(\u_DataPath/u_decode_unit/reg_file0/N133 ), .D(n7986), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][17] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[29][16] (
.G(\u_DataPath/u_decode_unit/reg_file0/N126 ), .D(n7954), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][16] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[28][16] (
.G(\u_DataPath/u_decode_unit/reg_file0/N127 ), .D(n7953), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][16] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[22][16] (
.G(\u_DataPath/u_decode_unit/reg_file0/N133 ), .D(n7953), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][16] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[29][20] (
.G(\u_DataPath/u_decode_unit/reg_file0/N126 ), .D(n7960), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][20] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[22][20] (
.G(\u_DataPath/u_decode_unit/reg_file0/N133 ), .D(n7959), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][20] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[29][8] (
.G(\u_DataPath/u_decode_unit/reg_file0/N126 ), .D(n7939), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][8] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[28][8] (
.G(\u_DataPath/u_decode_unit/reg_file0/N127 ), .D(n7938), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][8] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[22][8] (
.G(\u_DataPath/u_decode_unit/reg_file0/N133 ), .D(n7938), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][8] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[29][4] (
.G(\u_DataPath/u_decode_unit/reg_file0/N126 ), .D(n8032), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][4] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[28][4] (
.G(\u_DataPath/u_decode_unit/reg_file0/N127 ), .D(n8031), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][4] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[22][4] (
.G(\u_DataPath/u_decode_unit/reg_file0/N133 ), .D(n8031), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][4] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[29][22] (
.G(\u_DataPath/u_decode_unit/reg_file0/N126 ), .D(n7978), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][22] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[22][22] (
.G(\u_DataPath/u_decode_unit/reg_file0/N133 ), .D(n7977), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][22] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[29][28] (
.G(\u_DataPath/u_decode_unit/reg_file0/N126 ), .D(n7930), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][28] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[28][28] (
.G(\u_DataPath/u_decode_unit/reg_file0/N127 ), .D(n7929), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][28] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[22][28] (
.G(\u_DataPath/u_decode_unit/reg_file0/N133 ), .D(n7929), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][28] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[29][24] (
.G(\u_DataPath/u_decode_unit/reg_file0/N126 ), .D(n7984), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][24] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[22][24] (
.G(\u_DataPath/u_decode_unit/reg_file0/N133 ), .D(n7983), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][24] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[29][9] (
.G(\u_DataPath/u_decode_unit/reg_file0/N126 ), .D(n8014), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][9] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[28][9] (
.G(\u_DataPath/u_decode_unit/reg_file0/N127 ), .D(n8013), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][9] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[29][25] (
.G(\u_DataPath/u_decode_unit/reg_file0/N126 ), .D(n7993), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][25] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[28][25] (
.G(\u_DataPath/u_decode_unit/reg_file0/N127 ), .D(n7992), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][25] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[22][25] (
.G(\u_DataPath/u_decode_unit/reg_file0/N133 ), .D(n7992), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][25] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[29][5] (
.G(\u_DataPath/u_decode_unit/reg_file0/N126 ), .D(n8023), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][5] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[28][5] (
.G(\u_DataPath/u_decode_unit/reg_file0/N127 ), .D(n8022), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][5] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[22][5] (
.G(\u_DataPath/u_decode_unit/reg_file0/N133 ), .D(n8022), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][5] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[22][21] (
.G(\u_DataPath/u_decode_unit/reg_file0/N133 ), .D(n7965), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][21] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[29][29] (
.G(\u_DataPath/u_decode_unit/reg_file0/N126 ), .D(n8008), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][29] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[28][29] (
.G(\u_DataPath/u_decode_unit/reg_file0/N127 ), .D(n8007), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][29] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[22][29] (
.G(\u_DataPath/u_decode_unit/reg_file0/N133 ), .D(n8007), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][29] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[28][13] (
.G(\u_DataPath/u_decode_unit/reg_file0/N127 ), .D(n7956), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][13] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[22][13] (
.G(\u_DataPath/u_decode_unit/reg_file0/N133 ), .D(n7956), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][13] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[29][7] (
.G(\u_DataPath/u_decode_unit/reg_file0/N126 ), .D(n7951), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][7] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[28][7] (
.G(\u_DataPath/u_decode_unit/reg_file0/N127 ), .D(n7950), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][7] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[22][7] (
.G(\u_DataPath/u_decode_unit/reg_file0/N133 ), .D(n7950), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][7] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[29][12] (
.G(\u_DataPath/u_decode_unit/reg_file0/N126 ), .D(n7969), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][12] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[28][12] (
.G(\u_DataPath/u_decode_unit/reg_file0/N127 ), .D(n7968), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][12] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[22][12] (
.G(\u_DataPath/u_decode_unit/reg_file0/N133 ), .D(n7968), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][12] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[22][30] (
.G(\u_DataPath/u_decode_unit/reg_file0/N133 ), .D(n8012), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][30] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[29][23] (
.G(\u_DataPath/u_decode_unit/reg_file0/N126 ), .D(n7996), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][23] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[22][23] (
.G(\u_DataPath/u_decode_unit/reg_file0/N133 ), .D(n7995), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][23] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[29][26] (
.G(\u_DataPath/u_decode_unit/reg_file0/N126 ), .D(n8005), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][26] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[28][26] (
.G(\u_DataPath/u_decode_unit/reg_file0/N127 ), .D(n8004), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][26] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[22][26] (
.G(\u_DataPath/u_decode_unit/reg_file0/N133 ), .D(n8004), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][26] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[29][10] (
.G(\u_DataPath/u_decode_unit/reg_file0/N126 ), .D(n7945), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][10] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[28][10] (
.G(\u_DataPath/u_decode_unit/reg_file0/N127 ), .D(n7944), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][10] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[22][10] (
.G(\u_DataPath/u_decode_unit/reg_file0/N133 ), .D(n7944), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][10] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[29][3] (
.G(\u_DataPath/u_decode_unit/reg_file0/N126 ), .D(n8019), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][3] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[28][3] (
.G(\u_DataPath/u_decode_unit/reg_file0/N127 ), .D(n8019), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][3] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[22][3] (
.G(\u_DataPath/u_decode_unit/reg_file0/N133 ), .D(n8020), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][3] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[29][19] (
.G(\u_DataPath/u_decode_unit/reg_file0/N126 ), .D(n7963), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][19] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[28][19] (
.G(\u_DataPath/u_decode_unit/reg_file0/N127 ), .D(n7962), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][19] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[22][19] (
.G(\u_DataPath/u_decode_unit/reg_file0/N133 ), .D(n7962), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][19] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[29][11] (
.G(\u_DataPath/u_decode_unit/reg_file0/N126 ), .D(n7942), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][11] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[29][15] (
.G(\u_DataPath/u_decode_unit/reg_file0/N126 ), .D(n7972), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][15] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[28][15] (
.G(\u_DataPath/u_decode_unit/reg_file0/N127 ), .D(n7971), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][15] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[22][15] (
.G(\u_DataPath/u_decode_unit/reg_file0/N133 ), .D(n7971), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][15] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[22][14] (
.G(\u_DataPath/u_decode_unit/reg_file0/N133 ), .D(n7989), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][14] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[28][27] (
.G(\u_DataPath/u_decode_unit/reg_file0/N127 ), .D(n7926), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][27] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[22][27] (
.G(\u_DataPath/u_decode_unit/reg_file0/N133 ), .D(n7926), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][27] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[0][31] (
.G(rst), .D(n7937), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][31] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[0][0] (
.G(rst), .D(n8000), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][0] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[0][1] (
.G(rst), .D(n8027), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][1] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[0][6] (
.G(rst), .D(n8018), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][6] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[0][18] (
.G(rst), .D(n7982), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][18] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[0][2] (
.G(rst), .D(n8028), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][2] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[0][17] (
.G(rst), .D(n7988), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][17] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[0][16] (
.G(rst), .D(n7955), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][16] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[0][20] (
.G(rst), .D(n7961), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][20] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[0][8] (
.G(rst), .D(n7940), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][8] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[0][4] (
.G(rst), .D(n8033), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][4] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[0][22] (
.G(rst), .D(n7979), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][22] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[0][28] (
.G(rst), .D(n7931), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][28] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[0][24] (
.G(rst), .D(n7985), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][24] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[0][9] (
.G(rst), .D(n8015), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][9] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[0][25] (
.G(rst), .D(n7994), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][25] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[0][5] (
.G(rst), .D(n8024), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][5] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[0][21] (
.G(rst), .D(n7967), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][21] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[0][29] (
.G(rst), .D(n8009), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][29] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[0][13] (
.G(rst), .D(n7958), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][13] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[0][7] (
.G(rst), .D(n7952), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][7] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[0][12] (
.G(rst), .D(n7970), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][12] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[0][30] (
.G(rst), .D(n8011), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][30] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[0][23] (
.G(rst), .D(n7997), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][23] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[0][26] (
.G(rst), .D(n8006), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][26] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[0][10] (
.G(rst), .D(n7946), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][10] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[0][3] (
.G(rst), .D(n8020), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][3] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[0][19] (
.G(rst), .D(n7964), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][19] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[0][11] (
.G(rst), .D(n7943), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][11] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[0][15] (
.G(rst), .D(n7973), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][15] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[0][14] (
.G(rst), .D(n7991), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][14] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[0][27] (
.G(rst), .D(n7928), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][27] ) );
HS65_LH_LDHQX9 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[7][30] (
.G(\u_DataPath/u_decode_unit/reg_file0/N148 ), .D(n8010), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][30] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[31][31] (
.G(\u_DataPath/u_decode_unit/reg_file0/N92 ), .D(n7935), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][31] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[31][20] (
.G(\u_DataPath/u_decode_unit/reg_file0/N92 ), .D(n7959), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][20] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[31][26] (
.G(\u_DataPath/u_decode_unit/reg_file0/N92 ), .D(n8004), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][26] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[18][28] (
.G(\u_DataPath/u_decode_unit/reg_file0/N137 ), .D(n7930), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][28] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[18][19] (
.G(\u_DataPath/u_decode_unit/reg_file0/N137 ), .D(n7963), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][19] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[23][17] (
.G(\u_DataPath/u_decode_unit/reg_file0/N132 ), .D(n7986), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][17] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[26][18] (
.G(\u_DataPath/u_decode_unit/reg_file0/N129 ), .D(n7980), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][18] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[26][13] (
.G(\u_DataPath/u_decode_unit/reg_file0/N129 ), .D(n7956), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][13] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[30][4] (
.G(\u_DataPath/u_decode_unit/reg_file0/N125 ), .D(n8031), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][4] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[30][3] (
.G(\u_DataPath/u_decode_unit/reg_file0/N125 ), .D(n8019), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][3] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[28][1] (
.G(\u_DataPath/u_decode_unit/reg_file0/N127 ), .D(n8025), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][1] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[29][21] (
.G(\u_DataPath/u_decode_unit/reg_file0/N126 ), .D(n7966), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][21] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[29][27] (
.G(\u_DataPath/u_decode_unit/reg_file0/N126 ), .D(n7927), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][27] ) );
HS65_LL_IVX18 U3438 ( .A(n3118), .Z(addr_to_iram[26]) );
HS65_LH_IVX40 U3462 ( .A(n2782), .Z(addr_to_iram[17]) );
HS65_LH_IVX40 U3463 ( .A(n2823), .Z(addr_to_iram[9]) );
HS65_LH_IVX40 U3464 ( .A(n2825), .Z(addr_to_iram[25]) );
HS65_LH_IVX40 U3466 ( .A(n2829), .Z(addr_to_iram[7]) );
HS65_LH_IVX40 U3467 ( .A(n2831), .Z(addr_to_iram[18]) );
HS65_LH_IVX40 U3468 ( .A(n2833), .Z(addr_to_iram[8]) );
HS65_LH_IVX40 U3469 ( .A(n2835), .Z(addr_to_iram[6]) );
HS65_LH_NOR4ABX2 U3470 ( .A(n6806), .B(n6805), .C(n6804), .D(n6803), .Z(
n8183) );
HS65_LH_NOR4ABX2 U3471 ( .A(n6846), .B(n6845), .C(n6844), .D(n6843), .Z(
n8156) );
HS65_LL_OR2ABX35 U3473 ( .A(n2981), .B(n2994), .Z(write_op) );
HS65_LH_IVX9 U3474 ( .A(n3003), .Z(n2787) );
HS65_LH_IVX9 U3475 ( .A(n3004), .Z(n2793) );
HS65_LH_IVX9 U3476 ( .A(n2993), .Z(n2809) );
HS65_LH_IVX9 U3477 ( .A(n3006), .Z(n2805) );
HS65_LH_IVX9 U3478 ( .A(n3005), .Z(n2803) );
HS65_LH_IVX9 U3479 ( .A(n3007), .Z(n2807) );
HS65_LH_IVX9 U3480 ( .A(n8687), .Z(\u_DataPath/pc_4_i [2]) );
HS65_LH_IVX9 U3481 ( .A(n2989), .Z(n2789) );
HS65_LH_IVX9 U3482 ( .A(n2987), .Z(n2791) );
HS65_LH_IVX9 U3483 ( .A(n3001), .Z(n2795) );
HS65_LH_IVX9 U3484 ( .A(n3000), .Z(n2797) );
HS65_LH_IVX9 U3485 ( .A(n3002), .Z(n2799) );
HS65_LH_IVX9 U3486 ( .A(n2996), .Z(n2813) );
HS65_LH_IVX9 U3487 ( .A(n2999), .Z(n2815) );
HS65_LH_IVX9 U3488 ( .A(n2995), .Z(n2817) );
HS65_LH_IVX9 U3489 ( .A(n8671), .Z(n2774) );
HS65_LH_IVX9 U3490 ( .A(n8675), .Z(n2776) );
HS65_LH_IVX9 U3491 ( .A(n8673), .Z(n2778) );
HS65_LH_IVX9 U3492 ( .A(n8672), .Z(n2819) );
HS65_LH_IVX9 U3493 ( .A(n8674), .Z(n2821) );
HS65_LH_IVX9 U3494 ( .A(n3013), .Z(n2838) );
HS65_LH_IVX9 U3495 ( .A(n2998), .Z(n2811) );
HS65_LH_IVX9 U3496 ( .A(n8692), .Z(n2782) );
HS65_LH_IVX9 U3497 ( .A(n8703), .Z(n2825) );
HS65_LH_IVX9 U3498 ( .A(n8679), .Z(n2823) );
HS65_LH_IVX9 U3500 ( .A(n8678), .Z(n2829) );
HS65_LH_IVX9 U3501 ( .A(n8697), .Z(n2831) );
HS65_LH_IVX9 U3502 ( .A(n8681), .Z(n2833) );
HS65_LH_IVX9 U3503 ( .A(n8680), .Z(n2835) );
HS65_LH_IVX9 U3504 ( .A(n8684), .Z(n7745) );
HS65_LH_IVX9 U3505 ( .A(n8686), .Z(n3126) );
HS65_LH_IVX9 U3506 ( .A(n8685), .Z(n7669) );
HS65_LH_AOI21X2 U3507 ( .A(n7631), .B(n5707), .C(n5706), .Z(n5709) );
HS65_LH_NOR2AX3 U3517 ( .A(\u_DataPath/dataOut_exe_i [29]), .B(n3116), .Z(
n2988) );
HS65_LH_NOR2AX3 U3518 ( .A(n8748), .B(n3115), .Z(n2998) );
HS65_LH_AOI21X2 U3519 ( .A(n6011), .B(n6083), .C(n6010), .Z(n6065) );
HS65_LH_IVX9 U3520 ( .A(n8713), .Z(n2780) );
HS65_LH_AOI21X2 U3521 ( .A(n6117), .B(n6119), .C(n5943), .Z(n2876) );
HS65_LL_NAND3AX6 U3522 ( .A(n5676), .B(n8478), .C(n5675), .Z(n5677) );
HS65_LH_BFX9 U3523 ( .A(n7096), .Z(n7902) );
HS65_LH_BFX9 U3528 ( .A(n7320), .Z(n7587) );
HS65_LH_BFX9 U3529 ( .A(n7330), .Z(n7600) );
HS65_LH_BFX9 U3530 ( .A(n7332), .Z(n7602) );
HS65_LH_BFX9 U3531 ( .A(n7317), .Z(n7585) );
HS65_LH_BFX9 U3532 ( .A(n6675), .Z(n7318) );
HS65_LH_BFX9 U3533 ( .A(n7311), .Z(n7579) );
HS65_LH_AOI21X2 U3534 ( .A(Data_out_fromRAM[15]), .B(n8271), .C(n7344), .Z(
n7345) );
HS65_LH_BFX9 U3535 ( .A(n6382), .Z(n7291) );
HS65_LH_BFX9 U3537 ( .A(n6681), .Z(n7523) );
HS65_LH_NOR2X6 U3541 ( .A(n6348), .B(n2878), .Z(n7578) );
HS65_LH_NOR2X6 U3542 ( .A(n6147), .B(n6153), .Z(n6617) );
HS65_LH_NOR2X6 U3543 ( .A(n6150), .B(n6147), .Z(n6162) );
HS65_LH_NOR2X6 U3545 ( .A(n6153), .B(n6140), .Z(n6635) );
HS65_LH_NOR2X6 U3546 ( .A(n6353), .B(n6352), .Z(n6967) );
HS65_LH_NOR2X6 U3548 ( .A(n6349), .B(n6332), .Z(n7311) );
HS65_LH_NOR2X6 U3549 ( .A(n6350), .B(n6331), .Z(n7317) );
HS65_LL_NAND2X4 U3550 ( .A(n4282), .B(n4281), .Z(n4453) );
HS65_LL_NAND3X5 U3551 ( .A(n7083), .B(n7082), .C(n7081), .Z(n7306) );
HS65_LH_AOI21X2 U3552 ( .A(n8056), .B(n7697), .C(n7636), .Z(n7776) );
HS65_LH_NOR2AX3 U3553 ( .A(n9111), .B(n7076), .Z(n7083) );
HS65_LL_AOI21X2 U3554 ( .A(n7115), .B(n7614), .C(n7613), .Z(n8034) );
HS65_LH_AND2X4 U3556 ( .A(\u_DataPath/jaddr_i [20]), .B(
\u_DataPath/jaddr_i [19]), .Z(n6347) );
HS65_LH_NOR4ABX2 U3558 ( .A(\u_DataPath/cw_to_ex_i [1]), .B(n5488), .C(n5571), .D(n5353), .Z(n5372) );
HS65_LL_OAI12X2 U3559 ( .A(n5539), .B(n5538), .C(n5537), .Z(n5593) );
HS65_LHS_XNOR2X3 U3560 ( .A(n4045), .B(n4044), .Z(n4046) );
HS65_LH_OAI12X3 U3561 ( .A(n3935), .B(n4929), .C(n4085), .Z(n3847) );
HS65_LH_NOR4ABX2 U3562 ( .A(n5289), .B(n5344), .C(n5350), .D(n5288), .Z(
n5368) );
HS65_LH_IVX9 U3563 ( .A(\u_DataPath/jaddr_i [21]), .Z(n8163) );
HS65_LH_IVX9 U3564 ( .A(\u_DataPath/jaddr_i [23]), .Z(n8165) );
HS65_LH_IVX9 U3565 ( .A(write_byte), .Z(n2981) );
HS65_LL_AOI21X2 U3566 ( .A(n4431), .B(n4363), .C(n4362), .Z(n4364) );
HS65_LH_OAI12X3 U3568 ( .A(n4090), .B(n4929), .C(n4089), .Z(n4091) );
HS65_LL_NOR3X4 U3569 ( .A(n5528), .B(n5527), .C(n5513), .Z(n5559) );
HS65_LH_AOI12X2 U3573 ( .A(n5299), .B(n4017), .C(n5466), .Z(n5301) );
HS65_LH_AOI21X2 U3574 ( .A(n5632), .B(n5630), .C(n5629), .Z(n5636) );
HS65_LH_IVX9 U3576 ( .A(n5144), .Z(n4954) );
HS65_LH_AOI21X2 U3577 ( .A(n5575), .B(n5015), .C(n5014), .Z(n5016) );
HS65_LH_OAI21X2 U3578 ( .A(n5071), .B(n5070), .C(n5069), .Z(n5072) );
HS65_LH_NAND3X5 U3579 ( .A(n5479), .B(n5478), .C(n5477), .Z(n5480) );
HS65_LL_AOI21X2 U3580 ( .A(n5586), .B(n5009), .C(n5585), .Z(n5010) );
HS65_LL_OAI21X2 U3583 ( .A(n5152), .B(n5616), .C(n4167), .Z(n4168) );
HS65_LH_IVX9 U3586 ( .A(n5661), .Z(n4855) );
HS65_LL_NOR2X6 U3589 ( .A(n4502), .B(n4863), .Z(n4951) );
HS65_LH_AOI21X2 U3590 ( .A(n3521), .B(n4588), .C(n3830), .Z(n3831) );
HS65_LH_IVX9 U3592 ( .A(n4939), .Z(n6123) );
HS65_LH_AOI21X2 U3594 ( .A(n2849), .B(n4588), .C(n3904), .Z(n4496) );
HS65_LH_AOI21X2 U3595 ( .A(n5732), .B(n5758), .C(n5731), .Z(n5799) );
HS65_LH_IVX9 U3596 ( .A(n3935), .Z(n3482) );
HS65_LH_AOI21X2 U3597 ( .A(n5805), .B(n5807), .C(n5734), .Z(n5735) );
HS65_LH_IVX9 U3598 ( .A(n3426), .Z(n4502) );
HS65_LH_NOR2X6 U3599 ( .A(n4534), .B(n4581), .Z(n5207) );
HS65_LL_NAND2X7 U3600 ( .A(n4949), .B(n4836), .Z(n5646) );
HS65_LH_NAND2X7 U3601 ( .A(\u_DataPath/u_idexreg/N3 ), .B(n4550), .Z(n5249)
);
HS65_LL_NAND2X7 U3602 ( .A(n3643), .B(n3642), .Z(n4614) );
HS65_LL_NAND2X7 U3604 ( .A(n2851), .B(n4581), .Z(n4341) );
HS65_LH_AOI21X2 U3605 ( .A(n6010), .B(n5936), .C(n5935), .Z(n6000) );
HS65_LH_IVX9 U3608 ( .A(\lte_x_59/B[28] ), .Z(n4724) );
HS65_LH_NAND2X7 U3609 ( .A(n3431), .B(n5032), .Z(n4534) );
HS65_LL_NAND2X7 U3610 ( .A(n3490), .B(n3489), .Z(n4632) );
HS65_LL_NOR2X6 U3611 ( .A(\lte_x_59/B[21] ), .B(n5418), .Z(n4371) );
HS65_LH_NOR2X9 U3612 ( .A(n2840), .B(n7623), .Z(n5571) );
HS65_LH_NAND2X7 U3613 ( .A(n5021), .B(\lte_x_59/B[16] ), .Z(n4846) );
HS65_LH_NAND2X7 U3614 ( .A(\sub_x_53/A[20] ), .B(n4699), .Z(n4425) );
HS65_LH_OAI12X3 U3615 ( .A(n2860), .B(n2856), .C(n3963), .Z(n4257) );
HS65_LH_AOI21X2 U3616 ( .A(n5844), .B(n5720), .C(n5719), .Z(n5832) );
HS65_LH_AOI21X2 U3617 ( .A(n5761), .B(n5728), .C(n5727), .Z(n5729) );
HS65_LH_AOI21X2 U3618 ( .A(n5833), .B(n5722), .C(n5721), .Z(n5723) );
HS65_LH_AOI21X2 U3619 ( .A(n5811), .B(n5813), .C(n5733), .Z(n5800) );
HS65_LL_NAND2AX7 U3620 ( .A(n3546), .B(n3545), .Z(n4344) );
HS65_LH_IVX9 U3621 ( .A(\lte_x_59/B[5] ), .Z(n5041) );
HS65_LH_NAND2X7 U3622 ( .A(\lte_x_59/B[7] ), .B(n5030), .Z(n4624) );
HS65_LH_IVX9 U3625 ( .A(\lte_x_59/B[26] ), .Z(n5568) );
HS65_LL_NAND2X5 U3626 ( .A(n3474), .B(n5104), .Z(n4038) );
HS65_LL_IVX9 U3628 ( .A(n3101), .Z(\sub_x_53/A[25] ) );
HS65_LL_IVX18 U3632 ( .A(n3756), .Z(n4588) );
HS65_LH_NAND2X7 U3634 ( .A(\lte_x_59/B[5] ), .B(n5040), .Z(n4107) );
HS65_LL_NOR2AX6 U3635 ( .A(n3077), .B(n3076), .Z(\sub_x_53/A[29] ) );
HS65_LL_NOR2X6 U3637 ( .A(\sub_x_53/A[17] ), .B(n5001), .Z(n3558) );
HS65_LH_IVX9 U3640 ( .A(n2845), .Z(n2857) );
HS65_LH_OAI12X3 U3642 ( .A(n8355), .B(n3409), .C(n3094), .Z(n3095) );
HS65_LH_NOR2AX3 U3644 ( .A(n5054), .B(n2871), .Z(n4902) );
HS65_LH_AO31X9 U3646 ( .A(n8393), .B(n2866), .C(n9376), .D(n3419), .Z(n5032)
);
HS65_LL_IVX4 U3648 ( .A(n4969), .Z(n3059) );
HS65_LL_NOR2X6 U3649 ( .A(n3064), .B(n3063), .Z(\lte_x_59/B[1] ) );
HS65_LH_NOR2X6 U3650 ( .A(n3187), .B(n3186), .Z(n3432) );
HS65_LL_NOR2X6 U3652 ( .A(n3240), .B(n3239), .Z(n3474) );
HS65_LL_OAI12X6 U3653 ( .A(n3192), .B(n2894), .C(n3191), .Z(n5231) );
HS65_LL_OAI12X6 U3656 ( .A(n3224), .B(n3223), .C(n3222), .Z(n5373) );
HS65_LL_BFX9 U3657 ( .A(n3333), .Z(n3264) );
HS65_LH_IVX18 U3658 ( .A(n3082), .Z(n3403) );
HS65_LL_AOI21X2 U3660 ( .A(n3404), .B(n9385), .C(n3025), .Z(n7854) );
HS65_LH_IVX18 U3661 ( .A(n4712), .Z(n2874) );
HS65_LLS_XOR2X3 U3665 ( .A(n2940), .B(n2846), .Z(n2964) );
HS65_LL_NAND3X3 U3666 ( .A(n2941), .B(n7343), .C(n7089), .Z(n3052) );
HS65_LL_IVX9 U3668 ( .A(n7084), .Z(n2846) );
HS65_LL_NAND2X7 U3670 ( .A(\lte_x_59/B[5] ), .B(n4665), .Z(n4143) );
HS65_LL_IVX4 U3671 ( .A(n4657), .Z(n3339) );
HS65_LL_CBI4I1X5 U3673 ( .A(n5685), .B(n7853), .C(n7872), .D(n5684), .Z(
n7862) );
HS65_LL_IVX4 U3675 ( .A(n5694), .Z(n5675) );
HS65_LL_NAND2X14 U3676 ( .A(n3308), .B(n3310), .Z(n4712) );
HS65_LL_IVX9 U3677 ( .A(n3008), .Z(n7089) );
HS65_LH_NAND3X2 U3680 ( .A(n7089), .B(n9031), .C(n9078), .Z(n2773) );
HS65_LH_IVX13 U3684 ( .A(n8693), .Z(n7758) );
HS65_LH_NAND2X2 U3685 ( .A(\u_DataPath/dataOut_exe_i [1]), .B(nibble[0]),
.Z(n8575) );
HS65_LH_IVX9 U3686 ( .A(n2988), .Z(n2801) );
HS65_LL_NOR2AX25 U3687 ( .A(\u_DataPath/dataOut_exe_i [28]), .B(n3116), .Z(
Address_toRAM[26]) );
HS65_LL_NOR2AX3 U3688 ( .A(\u_DataPath/dataOut_exe_i [12]), .B(n2986), .Z(
n3005) );
HS65_LL_NOR2AX3 U3690 ( .A(\u_DataPath/dataOut_exe_i [10]), .B(n2986), .Z(
n3007) );
HS65_LH_NAND2X2 U3692 ( .A(addr_to_iram[12]), .B(addr_to_iram[13]), .Z(n7676) );
HS65_LH_NAND2X2 U3695 ( .A(n8704), .B(addr_to_iram[15]), .Z(n7648) );
HS65_LL_NOR2AX25 U3696 ( .A(\u_DataPath/dataOut_exe_i [13]), .B(n2986), .Z(
Address_toRAM[11]) );
HS65_LL_NOR2AX25 U3697 ( .A(\u_DataPath/dataOut_exe_i [27]), .B(n3116), .Z(
Address_toRAM[25]) );
HS65_LL_NOR2AX25 U3698 ( .A(n8728), .B(n3115), .Z(Data_in[31]) );
HS65_LH_NOR2X2 U3702 ( .A(n5476), .B(n5522), .Z(n5515) );
HS65_LH_OAI21X3 U3703 ( .A(n4926), .B(n3932), .C(n3934), .Z(n3477) );
HS65_LH_CNIVX3 U3704 ( .A(n3395), .Z(n3290) );
HS65_LH_NOR2X2 U3705 ( .A(n4724), .B(n5423), .Z(n5505) );
HS65_LH_NAND2X2 U3706 ( .A(n2858), .B(n2864), .Z(n3871) );
HS65_LH_CNIVX3 U3707 ( .A(n8547), .Z(n3161) );
HS65_LH_NAND2X2 U3709 ( .A(n4717), .B(n9342), .Z(n3195) );
HS65_LH_OAI21X3 U3710 ( .A(n4664), .B(n4637), .C(n4663), .Z(n5389) );
HS65_LH_NOR3X1 U3711 ( .A(n5082), .B(n5081), .C(n5080), .Z(n5114) );
HS65_LH_NAND2X2 U3715 ( .A(n4714), .B(n8518), .Z(n3254) );
HS65_LH_NAND2X2 U3716 ( .A(\lte_x_59/B[24] ), .B(n5180), .Z(n5209) );
HS65_LH_OAI21X3 U3717 ( .A(n5621), .B(n5620), .C(n5619), .Z(n5622) );
HS65_LH_CNIVX3 U3719 ( .A(n3427), .Z(n5659) );
HS65_LH_OAI21X3 U3720 ( .A(n6058), .B(n5957), .C(n5959), .Z(n5929) );
HS65_LH_NAND2X2 U3723 ( .A(n4295), .B(n5210), .Z(n4296) );
HS65_LH_CNIVX3 U3724 ( .A(n5405), .Z(n5476) );
HS65_LH_IVX9 U3725 ( .A(n5618), .Z(n5241) );
HS65_LH_NAND2X2 U3726 ( .A(\sub_x_53/A[20] ), .B(n4551), .Z(n3819) );
HS65_LH_CNIVX3 U3727 ( .A(n5128), .Z(n3773) );
HS65_LL_IVX2 U3728 ( .A(n4250), .Z(n5261) );
HS65_LH_NOR2X2 U3729 ( .A(n9030), .B(n9223), .Z(n6038) );
HS65_LH_NOR2X2 U3730 ( .A(n3905), .B(n4954), .Z(n3906) );
HS65_LH_CNIVX3 U3731 ( .A(n5400), .Z(n5466) );
HS65_LH_NAND2X2 U3732 ( .A(n3448), .B(n5469), .Z(n3449) );
HS65_LH_OAI21X3 U3733 ( .A(n5627), .B(n3702), .C(n5435), .Z(n3703) );
HS65_LH_CNIVX3 U3734 ( .A(n4230), .Z(n4303) );
HS65_LH_AOI12X2 U3735 ( .A(\lte_x_59/B[28] ), .B(n4588), .C(n3439), .Z(n3440) );
HS65_LH_CNIVX3 U3738 ( .A(n4849), .Z(n5203) );
HS65_LH_NOR2X2 U3739 ( .A(n5646), .B(n5645), .Z(n5669) );
HS65_LH_CNIVX3 U3740 ( .A(n4457), .Z(n4430) );
HS65_LH_NAND2X2 U3742 ( .A(\u_DataPath/jaddr_i [19]), .B(n6326), .Z(n6331)
);
HS65_LHS_XNOR2X3 U3743 ( .A(\u_DataPath/jaddr_i [18]), .B(n8967), .Z(n7101)
);
HS65_LH_OAI21X3 U3744 ( .A(n5730), .B(n5759), .C(n5729), .Z(n5731) );
HS65_LH_NAND2X2 U3745 ( .A(n7670), .B(n7649), .Z(n7650) );
HS65_LH_CNIVX3 U3746 ( .A(n6014), .Z(n5937) );
HS65_LH_NAND2X2 U3747 ( .A(n9185), .B(n9230), .Z(n6006) );
HS65_LH_NAND2X2 U3748 ( .A(n9183), .B(n9232), .Z(n5978) );
HS65_LH_NOR2X2 U3749 ( .A(n5987), .B(n5990), .Z(n5961) );
HS65_LH_NOR2X2 U3752 ( .A(n4502), .B(n4495), .Z(n4506) );
HS65_LH_NAND2X2 U3754 ( .A(n4084), .B(n4086), .Z(n3848) );
HS65_LH_NOR2X2 U3755 ( .A(n7713), .B(n7711), .Z(n5168) );
HS65_LH_NOR2X6 U3757 ( .A(n6153), .B(n6139), .Z(n6376) );
HS65_LH_BFX9 U3758 ( .A(n9373), .Z(n7580) );
HS65_LH_NAND3X2 U3760 ( .A(n7103), .B(n7102), .C(n7101), .Z(n7111) );
HS65_LH_NOR2X2 U3761 ( .A(n9341), .B(n9207), .Z(n5748) );
HS65_LH_NOR2X2 U3762 ( .A(n9181), .B(n9226), .Z(n5756) );
HS65_LH_NAND2X2 U3763 ( .A(n9173), .B(n9231), .Z(n5876) );
HS65_LH_CNIVX3 U3764 ( .A(n8915), .Z(n8268) );
HS65_LH_NAND2X2 U3765 ( .A(n7659), .B(n7684), .Z(n7673) );
HS65_LH_NOR2X2 U3766 ( .A(n7795), .B(n7794), .Z(n7307) );
HS65_LH_NAND2X2 U3767 ( .A(n4189), .B(n8571), .Z(n4190) );
HS65_LH_NOR2X2 U3768 ( .A(n8825), .B(n3341), .Z(n3177) );
HS65_LH_NAND2X2 U3769 ( .A(n9173), .B(n9231), .Z(n6075) );
HS65_LH_NAND2X2 U3770 ( .A(n8297), .B(n3407), .Z(n3104) );
HS65_LH_NOR2X2 U3771 ( .A(n8848), .B(n3341), .Z(n3159) );
HS65_LH_CNIVX3 U3772 ( .A(\u_DataPath/dataOut_exe_i [19]), .Z(n3188) );
HS65_LH_OAI21X3 U3774 ( .A(n4019), .B(n3815), .C(n4018), .Z(n4020) );
HS65_LH_OAI21X3 U3778 ( .A(n4349), .B(n4363), .C(n4949), .Z(n4095) );
HS65_LH_NAND2X2 U3782 ( .A(n5285), .B(n4483), .Z(n4484) );
HS65_LH_NAND2X2 U3783 ( .A(n5689), .B(n7723), .Z(n7714) );
HS65_LH_NAND2X2 U3784 ( .A(n9039), .B(n9116), .Z(n6100) );
HS65_LH_CNIVX3 U3785 ( .A(n7707), .Z(n7787) );
HS65_LH_NOR2X2 U3787 ( .A(n8172), .B(\u_DataPath/immediate_ext_dec_i [4]),
.Z(n8076) );
HS65_LH_NOR2X2 U3788 ( .A(n7668), .B(n7644), .Z(n7665) );
HS65_LH_AOI12X3 U3789 ( .A(n6053), .B(n6055), .C(n5944), .Z(n5945) );
HS65_LH_NOR2X2 U3790 ( .A(n5795), .B(n5798), .Z(n5808) );
HS65_LH_CNIVX3 U3791 ( .A(n5799), .Z(n5868) );
HS65_LH_NAND2X2 U3792 ( .A(n9179), .B(n9225), .Z(n5885) );
HS65_LHS_XNOR2X3 U3793 ( .A(n9235), .B(n8268), .Z(n2980) );
HS65_LH_NOR2X2 U3794 ( .A(n8480), .B(n7874), .Z(n7872) );
HS65_LH_NAND2X2 U3795 ( .A(n8697), .B(n7767), .Z(n7768) );
HS65_LH_CNIVX3 U3796 ( .A(n8235), .Z(n8287) );
HS65_LH_CNIVX3 U3800 ( .A(n8306), .Z(n3274) );
HS65_LHS_XNOR2X3 U3801 ( .A(n7724), .B(n7723), .Z(
\u_DataPath/u_execute/link_value_i [14]) );
HS65_LH_NOR2X2 U3802 ( .A(n8480), .B(n8306), .Z(n8600) );
HS65_LH_CNIVX3 U3804 ( .A(n8394), .Z(n3412) );
HS65_LH_NOR2X2 U3805 ( .A(n8480), .B(n8258), .Z(n8591) );
HS65_LHS_XNOR2X3 U3806 ( .A(n7709), .B(n7708), .Z(
\u_DataPath/u_execute/link_value_i [7]) );
HS65_LH_MUXI21X5 U3809 ( .D0(n3175), .D1(n9383), .S0(
\u_DataPath/cw_towb_i [0]), .Z(n8385) );
HS65_LHS_XNOR2X3 U3810 ( .A(n3517), .B(n3516), .Z(n3571) );
HS65_LH_NOR3X1 U3811 ( .A(n7094), .B(n7093), .C(n7092), .Z(n7095) );
HS65_LH_NAND2X2 U3812 ( .A(n9035), .B(n9115), .Z(n6049) );
HS65_LH_CNIVX3 U3814 ( .A(n8114), .Z(n8091) );
HS65_LH_NAND2X2 U3815 ( .A(\u_DataPath/immediate_ext_dec_i [0]), .B(n8157),
.Z(n8115) );
HS65_LH_NOR2X2 U3816 ( .A(n9082), .B(n7734), .Z(n8038) );
HS65_LHS_XNOR2X3 U3817 ( .A(n5881), .B(n5880), .Z(\u_DataPath/toPC2_i [9])
);
HS65_LH_NAND2X2 U3818 ( .A(n3470), .B(\u_DataPath/cw_to_ex_i [2]), .Z(n7617)
);
HS65_LH_NOR2X2 U3821 ( .A(n8844), .B(n4712), .Z(n8500) );
HS65_LH_CNIVX3 U3822 ( .A(n8600), .Z(n7974) );
HS65_LH_AND2X4 U3823 ( .A(n3311), .B(n3310), .Z(n3312) );
HS65_LH_CNIVX3 U3824 ( .A(n8586), .Z(n7932) );
HS65_LH_NOR2X2 U3826 ( .A(n3062), .B(n9401), .Z(n8485) );
HS65_LH_CNIVX3 U3827 ( .A(n8608), .Z(n8001) );
HS65_LH_NAND3X2 U3829 ( .A(n9005), .B(n8965), .C(n8091), .Z(n8093) );
HS65_LH_CNIVX3 U3830 ( .A(\u_DataPath/immediate_ext_dec_i [2]), .Z(n8090) );
HS65_LHS_XNOR2X3 U3833 ( .A(n7667), .B(n7666), .Z(\u_DataPath/pc_4_i [7]) );
HS65_LHS_XNOR2X3 U3834 ( .A(n3125), .B(n7672), .Z(\u_DataPath/pc_4_i [15])
);
HS65_LH_CNIVX3 U3835 ( .A(\u_DataPath/jaddr_i [22]), .Z(n8164) );
HS65_LH_NAND2X2 U3836 ( .A(n9084), .B(n9082), .Z(n8056) );
HS65_LH_NAND2X2 U3837 ( .A(n7616), .B(n7615), .Z(n8160) );
HS65_LH_OAI21X3 U3838 ( .A(n9137), .B(n8828), .C(n7847), .Z(
\u_DataPath/dataOut_exe_i [1]) );
HS65_LH_OAI22X1 U3840 ( .A(n9272), .B(n9270), .C(n9119), .D(n8752), .Z(
\u_DataPath/data_read_ex_2_i [15]) );
HS65_LH_OAI21X2 U3842 ( .A(n9189), .B(n9026), .C(n8445), .Z(
\u_DataPath/dataOut_exe_i [29]) );
HS65_LH_OAI22X1 U3844 ( .A(n7917), .B(n8431), .C(n7916), .D(n8430), .Z(
\u_DataPath/data_read_ex_1_i [4]) );
HS65_LH_OAI21X3 U3846 ( .A(n9190), .B(n8903), .C(n8312), .Z(
\u_DataPath/dataOut_exe_i [6]) );
HS65_LH_CNIVX3 U3848 ( .A(n8064), .Z(n8627) );
HS65_LH_NOR2X2 U3851 ( .A(n9168), .B(n9050), .Z(\u_DataPath/u_idexreg/N16 )
);
HS65_LH_CNIVX3 U3853 ( .A(n8240), .Z(\u_DataPath/branch_target_i [27]) );
HS65_LH_CNIVX3 U3854 ( .A(n8259), .Z(\u_DataPath/branch_target_i [10]) );
HS65_LL_OR2X9 U3855 ( .A(n3411), .B(n3410), .Z(n2840) );
HS65_LH_IVX13 U3857 ( .A(\lte_x_59/B[6] ), .Z(n2848) );
HS65_LL_NOR2X13 U3858 ( .A(n3250), .B(n3249), .Z(n2842) );
HS65_LL_OR2X9 U3859 ( .A(n3073), .B(n3072), .Z(n2843) );
HS65_LL_IVX9 U3860 ( .A(\sub_x_53/A[23] ), .Z(n2860) );
HS65_LLS_XNOR2X3 U3861 ( .A(n4160), .B(n4159), .Z(n2844) );
HS65_LL_AND2X18 U3862 ( .A(n5136), .B(n3401), .Z(n2845) );
HS65_LL_NOR3X4 U3864 ( .A(n5165), .B(n5164), .C(n5683), .Z(n7852) );
HS65_LL_NAND3AX13 U3865 ( .A(n2939), .B(n2938), .C(n2937), .Z(n3308) );
HS65_LL_NAND2X4 U3867 ( .A(n8468), .B(n8465), .Z(n4790) );
HS65_LL_AOI12X6 U3868 ( .A(n7631), .B(n4174), .C(n4173), .Z(n8465) );
HS65_LL_NAND3X3 U3869 ( .A(n4857), .B(n4744), .C(n4743), .Z(n4745) );
HS65_LL_NAND3X5 U3871 ( .A(n5561), .B(n5560), .C(n5559), .Z(n5591) );
HS65_LL_AOI12X2 U3874 ( .A(n5606), .B(n3499), .C(n3498), .Z(n3500) );
HS65_LL_NOR2X6 U3878 ( .A(n3320), .B(n3319), .Z(\lte_x_59/B[6] ) );
HS65_LL_NAND2X5 U3879 ( .A(n4365), .B(n4364), .Z(n4366) );
HS65_LL_NAND3X5 U3880 ( .A(n4361), .B(n4360), .C(n4359), .Z(n4362) );
HS65_LL_NAND2AX7 U3881 ( .A(n3551), .B(n2899), .Z(n4886) );
HS65_LL_NOR2X3 U3882 ( .A(n4755), .B(n4754), .Z(n4756) );
HS65_LL_NAND3X5 U3883 ( .A(n3487), .B(n3486), .C(n4593), .Z(n3490) );
HS65_LL_BFX9 U3885 ( .A(n3432), .Z(n2849) );
HS65_LL_OAI12X2 U3886 ( .A(n3366), .B(n5179), .C(n4940), .Z(n4941) );
HS65_LH_OAI112X3 U3887 ( .A(n5334), .B(n5301), .C(n5405), .D(n5479), .Z(
n5308) );
HS65_LL_NOR2X6 U3888 ( .A(\lte_x_59/B[1] ), .B(n4805), .Z(n4823) );
HS65_LLS_XNOR2X3 U3889 ( .A(\lte_x_59/B[1] ), .B(n4805), .Z(n4808) );
HS65_LL_IVX9 U3890 ( .A(n2840), .Z(n2851) );
HS65_LL_NOR2X3 U3891 ( .A(n8355), .B(n9401), .Z(n8525) );
HS65_LL_NOR2X3 U3892 ( .A(n5241), .B(n5240), .Z(n5242) );
HS65_LL_NOR2X6 U3896 ( .A(n3770), .B(n3769), .Z(n4522) );
HS65_LL_AOI12X2 U3897 ( .A(n4587), .B(\lte_x_59/B[15] ), .C(n3982), .Z(n3983) );
HS65_LL_NAND2X5 U3898 ( .A(\lte_x_59/B[4] ), .B(n5032), .Z(n4477) );
HS65_LL_OAI21X3 U3899 ( .A(n5646), .B(n4180), .C(n3660), .Z(n3661) );
HS65_LL_OAI211X3 U3900 ( .A(n5226), .B(n5646), .C(n4586), .D(n4585), .Z(
n4602) );
HS65_LL_NOR2X6 U3901 ( .A(n3773), .B(n3772), .Z(n4513) );
HS65_LL_AOI12X2 U3902 ( .A(n5526), .B(n5525), .C(n5524), .Z(n5538) );
HS65_LL_OAI21X3 U3903 ( .A(n5485), .B(n5337), .C(n5336), .Z(n5338) );
HS65_LL_AOI12X2 U3906 ( .A(n4551), .B(n3521), .C(n4153), .Z(n3455) );
HS65_LL_IVX9 U3907 ( .A(n3521), .Z(n4671) );
HS65_LL_IVX9 U3908 ( .A(n4966), .Z(n2873) );
HS65_LL_NAND2X14 U3909 ( .A(n3967), .B(n2872), .Z(n5152) );
HS65_LL_IVX9 U3912 ( .A(\sub_x_53/A[20] ), .Z(n4700) );
HS65_LLS_XNOR2X3 U3913 ( .A(\sub_x_53/A[20] ), .B(n4699), .Z(n4768) );
HS65_LL_AOI12X2 U3915 ( .A(\lte_x_59/B[7] ), .B(n4588), .C(n3670), .Z(n3920)
);
HS65_LL_IVX2 U3916 ( .A(\lte_x_59/B[7] ), .Z(n5031) );
HS65_LL_NOR2X13 U3917 ( .A(n3200), .B(n3199), .Z(\sub_x_53/A[17] ) );
HS65_LH_IVX13 U3918 ( .A(n5568), .Z(n2853) );
HS65_LL_IVX9 U3919 ( .A(\lte_x_59/B[26] ), .Z(n2854) );
HS65_LL_NAND2X7 U3920 ( .A(n4970), .B(n4974), .Z(n5423) );
HS65_LL_OAI211X1 U3921 ( .A(n5572), .B(n5571), .C(n5570), .D(n5569), .Z(
n5573) );
HS65_LL_NOR2X3 U3922 ( .A(n5571), .B(n4230), .Z(n5453) );
HS65_LL_OAI21X2 U3923 ( .A(n5450), .B(n5571), .C(n5449), .Z(n5451) );
HS65_LL_AOI112X4 U3925 ( .A(\lte_x_59/B[21] ), .B(n4351), .C(n3667), .D(
n3666), .Z(n4185) );
HS65_LL_AOI12X2 U3926 ( .A(\lte_x_59/B[21] ), .B(n4544), .C(n3903), .Z(n4497) );
HS65_LL_OAI21X2 U3928 ( .A(n5388), .B(n5387), .C(n4143), .Z(n5391) );
HS65_LL_IVX9 U3932 ( .A(n2843), .Z(n2858) );
HS65_LL_IVX9 U3933 ( .A(n4674), .Z(n5376) );
HS65_LL_NAND3X5 U3934 ( .A(n3837), .B(n3836), .C(n3835), .Z(n4839) );
HS65_LL_AOI12X6 U3935 ( .A(n3618), .B(n4879), .C(n3617), .Z(n5610) );
HS65_LLS_XNOR2X3 U3936 ( .A(n2849), .B(n5231), .Z(n5232) );
HS65_LLS_XNOR2X3 U3937 ( .A(\sub_x_53/A[0] ), .B(n5136), .Z(n5141) );
HS65_LL_IVX4 U3941 ( .A(n5691), .Z(n3224) );
HS65_LL_OAI21X2 U3942 ( .A(n4573), .B(n5383), .C(n5090), .Z(n5384) );
HS65_LL_AOI12X6 U3943 ( .A(n5672), .B(n5671), .C(n5670), .Z(n5673) );
HS65_LL_AOI12X2 U3945 ( .A(\lte_x_59/B[4] ), .B(n4551), .C(n3400), .Z(n3875)
);
HS65_LLS_XNOR2X3 U3947 ( .A(\lte_x_59/B[8] ), .B(n5373), .Z(n4762) );
HS65_LL_NOR2X6 U3949 ( .A(\lte_x_59/B[5] ), .B(n5040), .Z(n4105) );
HS65_LL_NAND2X4 U3950 ( .A(\lte_x_59/B[5] ), .B(n2864), .Z(n4542) );
HS65_LL_NAND2X5 U3951 ( .A(n3379), .B(n5632), .Z(n3375) );
HS65_LL_NAND2X7 U3952 ( .A(n3751), .B(n3383), .Z(n4330) );
HS65_LL_OAI21X3 U3953 ( .A(n5405), .B(n4049), .C(n4050), .Z(n4917) );
HS65_LL_IVX4 U3954 ( .A(n3474), .Z(n5105) );
HS65_LL_NAND2X4 U3957 ( .A(n4385), .B(n4382), .Z(n4121) );
HS65_LL_NAND2X4 U3959 ( .A(n4836), .B(n4886), .Z(n4382) );
HS65_LL_AOI12X2 U3960 ( .A(\lte_x_59/B[6] ), .B(n4588), .C(n3764), .Z(n3765)
);
HS65_LL_NAND3X3 U3963 ( .A(n8429), .B(n8875), .C(n8896), .Z(
\u_DataPath/dataOut_exe_i [0]) );
HS65_LH_NAND2X2 U3964 ( .A(\u_DataPath/u_execute/ovf_i ), .B(n2733), .Z(
n8423) );
HS65_LL_OAI12X3 U3967 ( .A(n9189), .B(n8901), .C(n8416), .Z(
\u_DataPath/dataOut_exe_i [28]) );
HS65_LL_OAI12X3 U3969 ( .A(n9190), .B(n8900), .C(n8328), .Z(
\u_DataPath/dataOut_exe_i [25]) );
HS65_LL_NAND2X4 U3970 ( .A(n8419), .B(n8899), .Z(
\u_DataPath/dataOut_exe_i [31]) );
HS65_LL_OAI12X3 U3971 ( .A(n9189), .B(n8891), .C(n8359), .Z(
\u_DataPath/dataOut_exe_i [23]) );
HS65_LL_CNIVX3 U3972 ( .A(n5598), .Z(n5599) );
HS65_LL_AOI12X4 U3973 ( .A(n5285), .B(n3628), .C(n3627), .Z(n8478) );
HS65_LL_OAI12X3 U3974 ( .A(n5602), .B(n5598), .C(n4243), .Z(n7841) );
HS65_LL_NAND3X2 U3975 ( .A(n3569), .B(n3568), .C(n3567), .Z(n3570) );
HS65_LL_IVX2 U3977 ( .A(n8464), .Z(n4793) );
HS65_LH_NAND2AX7 U3980 ( .A(n5705), .B(n5704), .Z(n5706) );
HS65_LL_OAI21X2 U3983 ( .A(n5633), .B(n3636), .C(n3635), .Z(n3637) );
HS65_LL_OAI21X2 U3984 ( .A(n3806), .B(n2859), .C(n3805), .Z(n3807) );
HS65_LH_NOR2X6 U3985 ( .A(n5490), .B(n5489), .Z(n5494) );
HS65_LH_IVX4 U3986 ( .A(n2859), .Z(n4297) );
HS65_LH_AOI21X6 U3987 ( .A(n5195), .B(n4238), .C(n4237), .Z(n4239) );
HS65_LH_NOR2X5 U3988 ( .A(n4995), .B(n4994), .Z(n5118) );
HS65_LH_IVX4 U3990 ( .A(n4948), .Z(n4533) );
HS65_LH_CNIVX3 U3991 ( .A(n5250), .Z(n5251) );
HS65_LH_AOI12X2 U3992 ( .A(n3389), .B(n5195), .C(n3388), .Z(n3390) );
HS65_LH_IVX7 U3993 ( .A(n4236), .Z(n4237) );
HS65_LH_NAND2X2 U3994 ( .A(n4512), .B(n5614), .Z(n4150) );
HS65_LL_NAND2X2 U3995 ( .A(n5615), .B(n4388), .Z(n4405) );
HS65_LH_IVX7 U3996 ( .A(n5616), .Z(n5623) );
HS65_LH_AOI21X4 U3997 ( .A(n5029), .B(n5020), .C(n5019), .Z(n5078) );
HS65_LH_IVX18 U3998 ( .A(n4879), .Z(n4929) );
HS65_LH_AOI31X3 U3999 ( .A(n5582), .B(n5581), .C(n5580), .D(n5579), .Z(n5589) );
HS65_LH_NAND3X5 U4001 ( .A(n4431), .B(n5321), .C(n4430), .Z(n3469) );
HS65_LL_NAND3X3 U4003 ( .A(n4010), .B(n4009), .C(n4008), .Z(n4536) );
HS65_LH_CNIVX3 U4004 ( .A(n4816), .Z(n4830) );
HS65_LH_NAND2X7 U4005 ( .A(n5208), .B(n5210), .Z(n3621) );
HS65_LH_AOI13X3 U4006 ( .A(n4845), .B(n4879), .C(n3618), .D(n3561), .Z(n3562) );
HS65_LH_NOR2X3 U4007 ( .A(n5201), .B(n5200), .Z(n5202) );
HS65_LH_NAND2X4 U4008 ( .A(n4086), .B(n3482), .Z(n4090) );
HS65_LH_AOI12X2 U4009 ( .A(n5309), .B(n5308), .C(n5307), .Z(n5339) );
HS65_LH_OAI12X3 U4010 ( .A(n5646), .B(n3966), .C(n3965), .Z(n3977) );
HS65_LH_IVX4 U4012 ( .A(n4606), .Z(n3727) );
HS65_LH_IVX4 U4014 ( .A(n5194), .Z(n5197) );
HS65_LH_NAND2X7 U4015 ( .A(n5192), .B(n5194), .Z(n3578) );
HS65_LH_NAND2X5 U4016 ( .A(n3426), .B(n4164), .Z(n5616) );
HS65_LH_NAND2X7 U4017 ( .A(n4930), .B(n3482), .Z(n4931) );
HS65_LH_OAI21X3 U4018 ( .A(n5226), .B(n3427), .C(n3711), .Z(n3730) );
HS65_LH_NOR2X6 U4019 ( .A(n5528), .B(n5527), .Z(n5584) );
HS65_LH_NOR2X6 U4020 ( .A(n3606), .B(n3605), .Z(n3607) );
HS65_LH_NAND2X5 U4021 ( .A(n3389), .B(n5194), .Z(n3391) );
HS65_LH_NAND2X5 U4022 ( .A(n4270), .B(n4269), .Z(n4271) );
HS65_LH_OAI12X3 U4024 ( .A(n4855), .B(n5620), .C(n4268), .Z(n4274) );
HS65_LH_OAI12X3 U4025 ( .A(n4855), .B(n4522), .C(n4521), .Z(n4532) );
HS65_LH_AOI21X2 U4026 ( .A(n4942), .B(n4839), .C(n3857), .Z(n3886) );
HS65_LH_OAI21X3 U4027 ( .A(n4803), .B(n5176), .C(n4133), .Z(n4137) );
HS65_LH_NOR2X5 U4028 ( .A(n4232), .B(n4330), .Z(n4238) );
HS65_LH_NAND2X5 U4029 ( .A(n5306), .B(n5305), .Z(n5307) );
HS65_LH_NAND2X7 U4030 ( .A(n5520), .B(n5515), .Z(n5541) );
HS65_LH_NOR2X6 U4031 ( .A(n5146), .B(n3858), .Z(n3859) );
HS65_LH_OAI21X3 U4032 ( .A(n5177), .B(n4838), .C(n4837), .Z(n4844) );
HS65_LH_NOR2X5 U4033 ( .A(n5018), .B(n5000), .Z(n5029) );
HS65_LH_NAND3X5 U4034 ( .A(n3776), .B(n3775), .C(n3774), .Z(n3777) );
HS65_LH_NAND2X5 U4035 ( .A(n5659), .B(n5206), .Z(n3428) );
HS65_LH_NOR2X2 U4037 ( .A(n4673), .B(n4684), .Z(n4694) );
HS65_LH_OAI21X3 U4038 ( .A(n4730), .B(n4729), .C(n4728), .Z(n4731) );
HS65_LH_IVX4 U4040 ( .A(n5542), .Z(n5106) );
HS65_LH_IVX9 U4041 ( .A(n4330), .Z(n3389) );
HS65_LH_NAND2X4 U4043 ( .A(n5564), .B(n5346), .Z(n5350) );
HS65_LH_NAND2X5 U4044 ( .A(n4497), .B(n4496), .Z(n4616) );
HS65_LH_NAND2X4 U4045 ( .A(n3426), .B(n4344), .Z(n3587) );
HS65_LL_CNIVX3 U4046 ( .A(n5211), .Z(n5212) );
HS65_LH_AO12X9 U4048 ( .A(n4041), .B(n4040), .C(n4039), .Z(n4042) );
HS65_LH_IVX9 U4050 ( .A(n4515), .Z(n5620) );
HS65_LH_IVX4 U4051 ( .A(n4610), .Z(n3865) );
HS65_LH_NOR2X5 U4052 ( .A(n4954), .B(n3555), .Z(n4874) );
HS65_LH_NAND3X3 U4054 ( .A(n3426), .B(n5672), .C(n4344), .Z(n3581) );
HS65_LH_NOR2X5 U4055 ( .A(n5241), .B(n5172), .Z(n3438) );
HS65_LH_IVX4 U4057 ( .A(n4304), .Z(n4307) );
HS65_LHS_XOR2X6 U4058 ( .A(n4574), .B(n4540), .Z(n4569) );
HS65_LH_NAND3X5 U4059 ( .A(n2864), .B(n6123), .C(n4806), .Z(n4807) );
HS65_LH_OAI21X3 U4060 ( .A(n5176), .B(n5135), .C(n5134), .Z(n5150) );
HS65_LH_NAND2X4 U4061 ( .A(n5618), .B(n5644), .Z(n4521) );
HS65_LH_IVX7 U4062 ( .A(n5644), .Z(n5645) );
HS65_LH_NAND2X7 U4063 ( .A(n4211), .B(n4290), .Z(n4220) );
HS65_LH_IVX4 U4064 ( .A(n4497), .Z(n4498) );
HS65_LH_CNIVX3 U4065 ( .A(n4500), .Z(n4501) );
HS65_LH_NOR2X6 U4066 ( .A(n4924), .B(n3936), .Z(n3939) );
HS65_LH_IVX9 U4067 ( .A(n5274), .Z(n4245) );
HS65_LH_IVX7 U4068 ( .A(n4016), .Z(n3950) );
HS65_LH_NOR3X2 U4070 ( .A(n4502), .B(n5152), .C(n4197), .Z(n4028) );
HS65_LH_NAND2X5 U4071 ( .A(n5270), .B(n3197), .Z(n5279) );
HS65_LH_NOR3X4 U4072 ( .A(n3783), .B(n3820), .C(n3782), .Z(n4526) );
HS65_LH_IVX4 U4075 ( .A(n4702), .Z(n4703) );
HS65_LH_NAND2X5 U4076 ( .A(n5286), .B(n5572), .Z(n5287) );
HS65_LH_NAND2X7 U4077 ( .A(n5572), .B(n4727), .Z(n4730) );
HS65_LH_IVX7 U4078 ( .A(n5507), .Z(n5510) );
HS65_LH_IVX4 U4079 ( .A(n4761), .Z(n3451) );
HS65_LH_NOR2X3 U4081 ( .A(n4939), .B(n4938), .Z(n4946) );
HS65_LH_NOR2X2 U4082 ( .A(n5421), .B(n5441), .Z(n5429) );
HS65_LH_OAI31X5 U4083 ( .A(n5133), .B(n5139), .C(n5132), .D(n5131), .Z(n5134) );
HS65_LH_IVX7 U4085 ( .A(n4488), .Z(n4489) );
HS65_LH_AOI21X6 U4086 ( .A(\lte_x_59/B[28] ), .B(n2864), .C(n3548), .Z(n3586) );
HS65_LH_IVX4 U4088 ( .A(n4930), .Z(n3936) );
HS65_LH_IVX7 U4089 ( .A(n5269), .Z(n3197) );
HS65_LH_NAND2X4 U4091 ( .A(n3559), .B(n3472), .Z(n3565) );
HS65_LH_NOR2X6 U4092 ( .A(\lte_x_59/B[28] ), .B(n5423), .Z(n4320) );
HS65_LH_NOR2X2 U4093 ( .A(n4630), .B(n4626), .Z(n4633) );
HS65_LH_NAND2X4 U4094 ( .A(n3474), .B(n2864), .Z(n4590) );
HS65_LH_NAND2X7 U4095 ( .A(n4930), .B(n3478), .Z(n3481) );
HS65_LH_AOI21X4 U4096 ( .A(n3478), .B(n4927), .C(n3477), .Z(n3479) );
HS65_LH_NOR2X6 U4097 ( .A(n3474), .B(n3359), .Z(n3949) );
HS65_LH_IVX7 U4098 ( .A(n3819), .Z(n3824) );
HS65_LH_NAND2X5 U4100 ( .A(n3832), .B(n3956), .Z(n3460) );
HS65_LH_OAI12X3 U4101 ( .A(n5356), .B(n5363), .C(n5292), .Z(n5586) );
HS65_LH_NAND2X7 U4102 ( .A(n3763), .B(n5127), .Z(n3766) );
HS65_LH_IVX4 U4104 ( .A(n3840), .Z(n3768) );
HS65_LH_NAND2X4 U4106 ( .A(n5234), .B(n5233), .Z(n5235) );
HS65_LH_NAND2X5 U4107 ( .A(n5256), .B(n5255), .Z(n5265) );
HS65_LH_OAI12X3 U4108 ( .A(n3749), .B(n3629), .C(n5443), .Z(n5444) );
HS65_LH_NAND2X2 U4109 ( .A(n4373), .B(n4372), .Z(n4379) );
HS65_LH_IVX9 U4110 ( .A(n5319), .Z(n5465) );
HS65_LH_NOR2X5 U4112 ( .A(n4765), .B(n4764), .Z(n4766) );
HS65_LH_NAND2X7 U4113 ( .A(\lte_x_59/B[28] ), .B(n3129), .Z(n4331) );
HS65_LH_IVX4 U4116 ( .A(n3838), .Z(n3434) );
HS65_LH_NOR2X5 U4117 ( .A(n4742), .B(n4741), .Z(n4743) );
HS65_LH_OAI21X3 U4120 ( .A(n4795), .B(n4671), .C(n4062), .Z(n3645) );
HS65_LH_IVX9 U4121 ( .A(n4507), .Z(n4197) );
HS65_LH_OAI12X3 U4123 ( .A(n4675), .B(n5129), .C(n3644), .Z(n3646) );
HS65_LH_NOR2X5 U4125 ( .A(n4682), .B(n5129), .Z(n4156) );
HS65_LH_IVX4 U4126 ( .A(n4034), .Z(n4035) );
HS65_LH_NAND2X7 U4127 ( .A(\lte_x_59/B[9] ), .B(n4587), .Z(n3870) );
HS65_LH_NAND2X5 U4128 ( .A(\lte_x_59/B[22] ), .B(n4551), .Z(n3963) );
HS65_LH_CNIVX3 U4130 ( .A(n5254), .Z(n5255) );
HS65_LH_IVX4 U4131 ( .A(n5232), .Z(n5233) );
HS65_LH_IVX4 U4132 ( .A(n4084), .Z(n4088) );
HS65_LH_CNIVX3 U4133 ( .A(n4371), .Z(n4372) );
HS65_LH_NAND2X5 U4134 ( .A(\sub_x_53/A[30] ), .B(n4966), .Z(n4289) );
HS65_LH_NAND2AX7 U4136 ( .A(n5320), .B(n2864), .Z(n5127) );
HS65_LL_OAI21X2 U4137 ( .A(n5258), .B(n5254), .C(n5256), .Z(n3496) );
HS65_LH_NAND2X4 U4138 ( .A(\lte_x_59/B[4] ), .B(n4544), .Z(n3763) );
HS65_LH_IVX4 U4139 ( .A(n4924), .Z(n4925) );
HS65_LH_IVX4 U4142 ( .A(n3800), .Z(n3801) );
HS65_LH_NOR2X6 U4143 ( .A(n4711), .B(n5129), .Z(n3548) );
HS65_LH_IVX4 U4144 ( .A(n5509), .Z(n5364) );
HS65_LH_NAND2X7 U4145 ( .A(\sub_x_53/A[30] ), .B(n4587), .Z(n3544) );
HS65_LH_NOR2X6 U4146 ( .A(n4637), .B(n4643), .Z(n3353) );
HS65_LH_NOR2X5 U4147 ( .A(n4700), .B(n4699), .Z(n5471) );
HS65_LH_NOR2X3 U4148 ( .A(n4986), .B(n5005), .Z(n5355) );
HS65_LH_IVX9 U4149 ( .A(n5531), .Z(n5511) );
HS65_LH_IVX4 U4150 ( .A(n4740), .Z(n4741) );
HS65_LH_NAND2X4 U4153 ( .A(n5004), .B(n5231), .Z(n5534) );
HS65_LH_IVX9 U4154 ( .A(n4672), .Z(n5294) );
HS65_LH_IVX7 U4155 ( .A(n5396), .Z(n5335) );
HS65_LH_NAND2X5 U4156 ( .A(n4671), .B(n5048), .Z(n5516) );
HS65_LH_IVX4 U4158 ( .A(n4768), .Z(n4441) );
HS65_LH_NAND2X4 U4159 ( .A(\lte_x_59/B[16] ), .B(n4551), .Z(n3839) );
HS65_LH_NOR2X3 U4161 ( .A(n3529), .B(n5022), .Z(n4850) );
HS65_LH_IVX9 U4162 ( .A(n5193), .Z(n3576) );
HS65_LH_IVX7 U4163 ( .A(n4774), .Z(n3610) );
HS65_LH_NAND2X5 U4164 ( .A(n5397), .B(n3231), .Z(n3853) );
HS65_LH_NAND2X5 U4165 ( .A(\lte_x_59/B[16] ), .B(n4985), .Z(n5506) );
HS65_LH_NAND2X7 U4166 ( .A(\u_DataPath/u_idexreg/N3 ), .B(n4512), .Z(n4939)
);
HS65_LH_IVX18 U4168 ( .A(n4726), .Z(\sub_x_53/A[30] ) );
HS65_LL_NOR2X2 U4169 ( .A(\lte_x_59/B[24] ), .B(n3382), .Z(n3575) );
HS65_LH_NAND2AX7 U4170 ( .A(\lte_x_59/B[14] ), .B(n5061), .Z(n4672) );
HS65_LH_IVX4 U4172 ( .A(n5095), .Z(n5096) );
HS65_LH_IVX4 U4173 ( .A(n5327), .Z(n5097) );
HS65_LL_BFX9 U4175 ( .A(n3547), .Z(\sub_x_53/A[27] ) );
HS65_LH_NAND2X7 U4176 ( .A(n2853), .B(n3384), .Z(n3749) );
HS65_LH_IVX4 U4177 ( .A(n4573), .Z(n4661) );
HS65_LL_NAND2X4 U4179 ( .A(\lte_x_59/B[18] ), .B(n5005), .Z(n5258) );
HS65_LH_NOR2X5 U4180 ( .A(n2849), .B(n5231), .Z(n5254) );
HS65_LH_NAND2X4 U4181 ( .A(n4624), .B(n4623), .Z(n4635) );
HS65_LL_CNBFX10 U4182 ( .A(n2856), .Z(n4583) );
HS65_LL_IVX18 U4184 ( .A(n3756), .Z(n4551) );
HS65_LH_OAI22X4 U4185 ( .A(n7096), .B(n8353), .C(n7900), .D(n8349), .Z(
\u_DataPath/data_read_ex_2_i [22]) );
HS65_LH_OAI22X4 U4186 ( .A(n7096), .B(n8343), .C(n7900), .D(n8338), .Z(
\u_DataPath/data_read_ex_2_i [13]) );
HS65_LH_OAI22X4 U4187 ( .A(n7096), .B(n8348), .C(n7900), .D(n8344), .Z(
\u_DataPath/data_read_ex_2_i [11]) );
HS65_LH_OAI22X4 U4188 ( .A(n7096), .B(n8337), .C(n7900), .D(n8331), .Z(
\u_DataPath/data_read_ex_2_i [9]) );
HS65_LL_NOR2X6 U4190 ( .A(n3061), .B(n3060), .Z(\lte_x_59/B[21] ) );
HS65_LH_IVX7 U4191 ( .A(n4769), .Z(n4553) );
HS65_LL_NOR2X6 U4194 ( .A(n3266), .B(n3265), .Z(n3521) );
HS65_LH_CNIVX3 U4195 ( .A(n4596), .Z(n4561) );
HS65_LL_IVX4 U4196 ( .A(n5104), .Z(n3359) );
HS65_LH_IVX18 U4199 ( .A(n5652), .Z(\lte_x_59/B[22] ) );
HS65_LH_IVX18 U4200 ( .A(n5054), .Z(\lte_x_59/B[9] ) );
HS65_LH_OAI22X6 U4201 ( .A(n3264), .B(\u_DataPath/dataOut_exe_i [27]), .C(
n8374), .D(n3409), .Z(n3107) );
HS65_LH_NOR2X3 U4204 ( .A(n9167), .B(n8916), .Z(\u_DataPath/cw_exmem_i [4])
);
HS65_LL_NOR2X3 U4205 ( .A(n3118), .B(n7770), .Z(n7780) );
HS65_LL_NAND3X5 U4206 ( .A(n2903), .B(n3081), .C(n3080), .Z(n5054) );
HS65_LHS_XOR2X3 U4207 ( .A(n3118), .B(n7770), .Z(\u_DataPath/pc_4_i [28]) );
HS65_LL_NAND2X5 U4209 ( .A(n8272), .B(n8298), .Z(n8452) );
HS65_LH_AO22X9 U4210 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][18] ), .B(n7587),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[12][18] ), .D(
n7586), .Z(n6335) );
HS65_LH_AO22X9 U4211 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][18] ), .B(n7517),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[4][18] ), .D(
n7318), .Z(n6336) );
HS65_LH_AO22X9 U4212 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][25] ), .B(n7578),
.C(n7310), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][25] ), .Z(n7037)
);
HS65_LH_AO22X9 U4214 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][25] ), .B(n6747),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[4][25] ), .D(
n7318), .Z(n7041) );
HS65_LH_AO22X9 U4215 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][9] ), .B(n7578),
.C(n7310), .D(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][9] ), .Z(n7017) );
HS65_LH_AOI22X3 U4216 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][9] ), .B(n7273),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[29][9] ), .D(
n6625), .Z(n7129) );
HS65_LH_AOI22X3 U4219 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][9] ), .B(n7165),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[28][9] ), .D(
n6624), .Z(n7130) );
HS65_LH_AOI22X3 U4220 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][18] ), .B(n7525),
.C(n7594), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][18] ), .Z(n6343)
);
HS65_LH_AO22X9 U4222 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][9] ), .B(n6747),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[4][9] ), .D(n7318), .Z(n7021) );
HS65_LH_AO22X9 U4223 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][19] ), .B(n6747),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[4][19] ), .D(
n7318), .Z(n6749) );
HS65_LH_AOI22X3 U4224 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][31] ), .B(n7415),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[10][31] ), .D(
n2891), .Z(n6674) );
HS65_LH_AOI22X3 U4226 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][21] ), .B(n7603),
.C(n6966), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][21] ), .Z(n7606)
);
HS65_LH_AO22X9 U4227 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][26] ), .B(n7517),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[4][26] ), .D(
n7318), .Z(n7322) );
HS65_LH_AOI22X3 U4228 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][23] ), .B(n7273),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[29][23] ), .D(
n6625), .Z(n6231) );
HS65_LH_AOI22X3 U4229 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][29] ), .B(n7603),
.C(n6966), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][29] ), .Z(n7531)
);
HS65_LH_AO22X9 U4230 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][10] ), .B(n7517),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[4][10] ), .D(
n7318), .Z(n7209) );
HS65_LH_AOI22X3 U4234 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][5] ), .B(n7585),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[1][5] ), .D(n6957), .Z(n6705) );
HS65_LH_AOI22X3 U4237 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][31] ), .B(n7585),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[1][31] ), .D(
n6957), .Z(n6678) );
HS65_LH_AO22X9 U4238 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][8] ), .B(n7517),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[4][8] ), .D(n7318), .Z(n6772) );
HS65_LH_AOI22X3 U4239 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][8] ), .B(n7585),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[1][8] ), .D(n6957), .Z(n6773) );
HS65_LH_AOI22X3 U4240 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][17] ), .B(n7585),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[1][17] ), .D(
n6957), .Z(n6813) );
HS65_LH_AOI22X3 U4241 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][16] ), .B(n7603),
.C(n6966), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][16] ), .Z(n7551)
);
HS65_LH_AOI22X3 U4242 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][20] ), .B(n7603),
.C(n6966), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][20] ), .Z(n7485)
);
HS65_LH_AOI22X3 U4245 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][2] ), .B(n6754),
.C(n7594), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][2] ), .Z(n6962)
);
HS65_LH_AO22X9 U4246 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][15] ), .B(n7517),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[4][15] ), .D(
n7318), .Z(n7189) );
HS65_LH_AOI22X3 U4247 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][24] ), .B(n7603),
.C(n6966), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][24] ), .Z(n7571)
);
HS65_LH_AO22X9 U4249 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][11] ), .B(n7578),
.C(n7310), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][11] ), .Z(n7057)
);
HS65_LH_AO22X9 U4251 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][11] ), .B(n6747),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[4][11] ), .D(
n7318), .Z(n7061) );
HS65_LH_AOI22X3 U4253 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][4] ), .B(n6376),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[21][4] ), .D(
n7285), .Z(n6639) );
HS65_LH_AO22X9 U4254 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][4] ), .B(n7283),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[20][4] ), .D(
n7282), .Z(n6641) );
HS65_LH_AOI22X3 U4255 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][27] ), .B(n7603),
.C(n6966), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][27] ), .Z(n7465)
);
HS65_LH_AO22X9 U4257 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][22] ), .B(n6747),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[4][22] ), .D(
n7318), .Z(n7001) );
HS65_LH_AO22X9 U4258 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][22] ), .B(n7578),
.C(n7310), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][22] ), .Z(n6997)
);
HS65_LH_AOI22X3 U4262 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][12] ), .B(n7585),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[1][12] ), .D(
n6957), .Z(n6793) );
HS65_LH_AOI22X3 U4263 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][7] ), .B(n7585),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[1][7] ), .D(n6957), .Z(n6725) );
HS65_LH_AOI22X3 U4265 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][30] ), .B(n7273),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[29][30] ), .D(
n6625), .Z(n6136) );
HS65_LH_AO22X9 U4267 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][12] ), .B(n7517),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[4][12] ), .D(
n7318), .Z(n6792) );
HS65_LH_AO22X9 U4268 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][13] ), .B(n6747),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[4][13] ), .D(
n7318), .Z(n6981) );
HS65_LH_AOI22X4 U4272 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][30] ), .B(n7602),
.C(n7601), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][30] ), .Z(n7409)
);
HS65_LH_AOI22X4 U4273 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][30] ), .B(n7600),
.C(n7599), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][30] ), .Z(n7410)
);
HS65_LH_AO22X9 U4275 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][7] ), .B(n7517),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[4][7] ), .D(n7318), .Z(n6724) );
HS65_LH_AOI22X3 U4276 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][0] ), .B(n7603),
.C(n6966), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][0] ), .Z(n7445)
);
HS65_LH_AOI22X3 U4277 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][7] ), .B(n7415),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[10][7] ), .D(
n2891), .Z(n6722) );
HS65_LH_AO22X9 U4278 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][6] ), .B(n7517),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[4][6] ), .D(n7318), .Z(n7249) );
HS65_LH_AO22X9 U4279 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][13] ), .B(n7277),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[25][13] ), .D(
n6629), .Z(n7166) );
HS65_LL_AOI12X4 U4280 ( .A(n6105), .B(n6107), .C(n5941), .Z(n5974) );
HS65_LL_OAI12X2 U4282 ( .A(n8266), .B(n3340), .C(n3104), .Z(n3105) );
HS65_LH_IVX9 U4283 ( .A(n8497), .Z(n3323) );
HS65_LH_NOR2X6 U4284 ( .A(n8867), .B(n3341), .Z(n3342) );
HS65_LH_NOR2X6 U4285 ( .A(n3275), .B(n8522), .Z(n3276) );
HS65_LH_NOR2X2 U4286 ( .A(rst), .B(n8554), .Z(
\u_DataPath/mem_writedata_out_i [25]) );
HS65_LH_NOR2X6 U4289 ( .A(n8861), .B(n3341), .Z(n3064) );
HS65_LL_NAND3X3 U4291 ( .A(n8135), .B(n8134), .C(n8318), .Z(n8301) );
HS65_LL_IVX9 U4293 ( .A(n4712), .Z(n3291) );
HS65_LH_NOR2X6 U4294 ( .A(n3274), .B(n7868), .Z(n8522) );
HS65_LH_NAND2X5 U4295 ( .A(n4714), .B(n8524), .Z(n3275) );
HS65_LH_NOR2X6 U4296 ( .A(n8243), .B(n7868), .Z(n8547) );
HS65_LH_NAND2X4 U4297 ( .A(n8044), .B(n8043), .Z(opcode_i[0]) );
HS65_LH_NAND2X5 U4298 ( .A(n4714), .B(n8553), .Z(n3141) );
HS65_LH_NAND2X4 U4299 ( .A(n8044), .B(n8036), .Z(opcode_i[2]) );
HS65_LL_NOR2X3 U4302 ( .A(n3119), .B(n7759), .Z(n7704) );
HS65_LH_BFX18 U4303 ( .A(n8483), .Z(n7922) );
HS65_LL_AOI12X4 U4305 ( .A(\u_DataPath/dataOut_exe_i [0]), .B(n8573), .C(
n8133), .Z(n8318) );
HS65_LH_BFX18 U4306 ( .A(n8483), .Z(n7923) );
HS65_LH_AOI21X6 U4308 ( .A(n2896), .B(n3299), .C(n3298), .Z(n3300) );
HS65_LH_NAND2X7 U4309 ( .A(n3260), .B(n2866), .Z(n8514) );
HS65_LH_NAND2X7 U4310 ( .A(n2896), .B(n3257), .Z(n6125) );
HS65_LH_NAND2X4 U4312 ( .A(n3307), .B(n3407), .Z(n3304) );
HS65_LH_NOR2X5 U4313 ( .A(n7854), .B(n9401), .Z(n8528) );
HS65_LH_NOR2X6 U4315 ( .A(\u_DataPath/dataOut_exe_i [21]), .B(n8390), .Z(
n8541) );
HS65_LH_AOI21X2 U4316 ( .A(n6016), .B(n6083), .C(n6015), .Z(n6017) );
HS65_LH_NAND2X4 U4317 ( .A(n8574), .B(n3407), .Z(n3344) );
HS65_LH_NAND2X5 U4320 ( .A(n4213), .B(n7869), .Z(n8565) );
HS65_LH_OAI12X3 U4323 ( .A(n8177), .B(n8132), .C(n2733), .Z(n8133) );
HS65_LL_NAND2X4 U4324 ( .A(n9213), .B(n7118), .Z(n7796) );
HS65_LH_NAND2X4 U4325 ( .A(n9112), .B(n8576), .Z(n8134) );
HS65_LH_AOI12X2 U4326 ( .A(n5808), .B(n5868), .C(n5807), .Z(n5809) );
HS65_LH_NAND2X5 U4327 ( .A(n3127), .B(n3407), .Z(n4971) );
HS65_LH_OAI21X2 U4328 ( .A(n7762), .B(n7761), .C(n7760), .Z(n8124) );
HS65_LH_NAND2X4 U4330 ( .A(n3193), .B(n7802), .Z(n8533) );
HS65_LL_NAND2X21 U4332 ( .A(n2733), .B(n8034), .Z(
\u_DataPath/u_fetch/pc1/N3 ) );
HS65_LL_OAI12X3 U4333 ( .A(n5736), .B(n5799), .C(n5735), .Z(n5904) );
HS65_LL_BFX27 U4334 ( .A(n7802), .Z(n7869) );
HS65_LL_IVX9 U4335 ( .A(n3333), .Z(n3407) );
HS65_LH_NOR2X5 U4336 ( .A(n7724), .B(n7720), .Z(n7721) );
HS65_LH_NAND2X4 U4337 ( .A(n3256), .B(n7802), .Z(n8515) );
HS65_LH_IVX7 U4338 ( .A(n2879), .Z(n3110) );
HS65_LH_NAND2X5 U4339 ( .A(n8680), .B(n7746), .Z(n7747) );
HS65_LH_IVX9 U4340 ( .A(n7614), .Z(n7615) );
HS65_LH_NOR2X5 U4341 ( .A(n7834), .B(n3968), .Z(n4192) );
HS65_LH_IVX7 U4342 ( .A(n7903), .Z(n4243) );
HS65_LL_IVX18 U4343 ( .A(n3308), .Z(n7802) );
HS65_LHS_XNOR2X3 U4344 ( .A(n6104), .B(n6103), .Z(
\u_DataPath/u_execute/resAdd1_i [3]) );
HS65_LH_IVX7 U4347 ( .A(n3111), .Z(n8577) );
HS65_LL_NAND2X5 U4349 ( .A(n2981), .B(n3111), .Z(n3114) );
HS65_LHS_XOR2X3 U4350 ( .A(n7788), .B(n7787), .Z(
\u_DataPath/u_execute/link_value_i [6]) );
HS65_LH_NOR2X5 U4351 ( .A(n5932), .B(n5964), .Z(n5934) );
HS65_LH_NOR2X6 U4352 ( .A(n7680), .B(n7741), .Z(n7746) );
HS65_LL_NOR2X5 U4355 ( .A(n6349), .B(n6333), .Z(n6746) );
HS65_LH_CNIVX3 U4356 ( .A(n5798), .Z(n5802) );
HS65_LH_IVX7 U4357 ( .A(n7676), .Z(n7678) );
HS65_LH_CNIVX3 U4358 ( .A(n8284), .Z(\u_DataPath/branch_target_i [0]) );
HS65_LH_NOR2X6 U4359 ( .A(n5730), .B(n5760), .Z(n5732) );
HS65_LH_NOR3X4 U4360 ( .A(\u_DataPath/immediate_ext_dec_i [2]), .B(n8162),
.C(n7703), .Z(n8098) );
HS65_LH_NAND2X5 U4361 ( .A(n2733), .B(n8266), .Z(n8304) );
HS65_LH_NAND2X4 U4362 ( .A(n2733), .B(n8255), .Z(n8293) );
HS65_LH_IVX4 U4363 ( .A(n8380), .Z(n4207) );
HS65_LH_AOI21X6 U4364 ( .A(n6051), .B(n5922), .C(n5921), .Z(n6034) );
HS65_LH_NAND2X5 U4365 ( .A(n8316), .B(n2733), .Z(n8321) );
HS65_LH_NAND2X5 U4368 ( .A(n2733), .B(n8243), .Z(n8362) );
HS65_LH_NAND2X4 U4370 ( .A(n2733), .B(\u_DataPath/toPC2_i [0]), .Z(n8284) );
HS65_LH_IVX9 U4371 ( .A(n8323), .Z(n8537) );
HS65_LH_NAND2X5 U4372 ( .A(n2733), .B(n8176), .Z(n8422) );
HS65_LH_NAND2X4 U4373 ( .A(n2733), .B(n8339), .Z(n8343) );
HS65_LH_NAND2X5 U4374 ( .A(n2733), .B(n8374), .Z(n8378) );
HS65_LH_NAND2X4 U4375 ( .A(n2733), .B(n8394), .Z(n8434) );
HS65_LH_NAND2X5 U4376 ( .A(n2733), .B(n8364), .Z(n8367) );
HS65_LH_NAND2X5 U4377 ( .A(n2733), .B(n8355), .Z(n8358) );
HS65_LH_NAND2X5 U4378 ( .A(n2733), .B(n8550), .Z(n8372) );
HS65_LH_OAI21X6 U4379 ( .A(n3404), .B(n3023), .C(n3022), .Z(n5716) );
HS65_LH_IVX4 U4380 ( .A(n5844), .Z(n5898) );
HS65_LH_NAND2X4 U4381 ( .A(n2733), .B(n8332), .Z(n8337) );
HS65_LH_IVX4 U4382 ( .A(n5757), .Z(n5763) );
HS65_LH_IVX4 U4383 ( .A(n5761), .Z(n5762) );
HS65_LH_CNIVX3 U4385 ( .A(n5779), .Z(n5782) );
HS65_LH_NAND2X4 U4386 ( .A(n2733), .B(n8389), .Z(n8404) );
HS65_LH_IVX9 U4387 ( .A(n4175), .Z(n3288) );
HS65_LH_NAND2X5 U4389 ( .A(n2733), .B(n8393), .Z(n8431) );
HS65_LL_NOR3X2 U4391 ( .A(\u_DataPath/cw_to_ex_i [15]), .B(n8755), .C(n8263),
.Z(n8451) );
HS65_LH_NOR2X2 U4393 ( .A(n8065), .B(rst), .Z(
\u_DataPath/regfile_addr_out_towb_i [2]) );
HS65_LH_NOR2X5 U4395 ( .A(n8042), .B(rst), .Z(\u_DataPath/idex_rt_i [3]) );
HS65_LH_IVX4 U4397 ( .A(n5687), .Z(n5689) );
HS65_LH_NOR2X2 U4398 ( .A(n8108), .B(rst), .Z(
\u_DataPath/regfile_addr_out_towb_i [0]) );
HS65_LH_NOR2X3 U4399 ( .A(n8574), .B(rst), .Z(n8579) );
HS65_LL_NAND2X5 U4401 ( .A(\u_DataPath/jaddr_i [16]), .B(n8153), .Z(n6353)
);
HS65_LH_NAND2X5 U4402 ( .A(n2733), .B(n8311), .Z(n8314) );
HS65_LH_CNIVX3 U4403 ( .A(n7725), .Z(n7789) );
HS65_LH_NOR2X2 U4405 ( .A(n8063), .B(rst), .Z(
\u_DataPath/regfile_addr_out_towb_i [3]) );
HS65_LH_IVX4 U4406 ( .A(n5820), .Z(n5866) );
HS65_LH_NAND2X2 U4407 ( .A(\u_DataPath/cw_to_ex_i [2]), .B(n7834), .Z(n4786)
);
HS65_LH_IVX7 U4408 ( .A(\u_DataPath/dataOut_exe_i [24]), .Z(n3140) );
HS65_LH_IVX4 U4409 ( .A(\u_DataPath/immediate_ext_dec_i [0]), .Z(n8130) );
HS65_LH_IVX4 U4410 ( .A(n9077), .Z(n2943) );
HS65_LH_NAND2X5 U4412 ( .A(n2733), .B(\u_DataPath/immediate_ext_dec_i [10]),
.Z(n8182) );
HS65_LH_NAND2X5 U4413 ( .A(n9177), .B(n9229), .Z(n5877) );
HS65_LH_NAND2X5 U4416 ( .A(n2733), .B(\u_DataPath/immediate_ext_dec_i [9]),
.Z(n8185) );
HS65_LH_NAND2X5 U4417 ( .A(n9030), .B(n9223), .Z(n5838) );
HS65_LH_NAND2X5 U4418 ( .A(n9343), .B(n9221), .Z(n5819) );
HS65_LH_NAND2X7 U4419 ( .A(n9223), .B(n9219), .Z(n4001) );
HS65_LH_NOR2X6 U4420 ( .A(n9341), .B(n9218), .Z(n5795) );
HS65_LH_NAND2X2 U4421 ( .A(n2733), .B(\u_DataPath/pc4_to_idexreg_i [2]), .Z(
n8228) );
HS65_LH_NAND2X2 U4422 ( .A(n2733), .B(\u_DataPath/pc4_to_idexreg_i [0]), .Z(
n8230) );
HS65_LH_NAND2X5 U4424 ( .A(n2733), .B(\u_DataPath/immediate_ext_dec_i [8]),
.Z(n8186) );
HS65_LH_IVX7 U4425 ( .A(\u_DataPath/dataOut_exe_i [18]), .Z(n3193) );
HS65_LH_NOR2X6 U4427 ( .A(n9267), .B(n9228), .Z(n5786) );
HS65_LH_NOR3X3 U4428 ( .A(n8755), .B(n9151), .C(\u_DataPath/cw_to_ex_i [15]),
.Z(n8264) );
HS65_LH_NAND2X5 U4430 ( .A(n2733), .B(\u_DataPath/immediate_ext_dec_i [7]),
.Z(n8179) );
HS65_LH_IVX4 U4431 ( .A(n8876), .Z(n4715) );
HS65_LH_IVX9 U4432 ( .A(\u_DataPath/dataOut_exe_i [25]), .Z(n3132) );
HS65_LH_NAND2X5 U4433 ( .A(n2733), .B(\u_DataPath/immediate_ext_dec_i [6]),
.Z(n8187) );
HS65_LH_NAND2X2 U4435 ( .A(n2733), .B(\u_DataPath/pc4_to_idexreg_i [20]),
.Z(n8205) );
HS65_LH_NAND2X2 U4436 ( .A(n2733), .B(n9427), .Z(n8196) );
HS65_LH_IVX7 U4437 ( .A(n9236), .Z(n2975) );
HS65_LH_NAND2X2 U4438 ( .A(n2733), .B(\u_DataPath/pc4_to_idexreg_i [6]), .Z(
n8224) );
HS65_LH_IVX7 U4439 ( .A(\u_DataPath/dataOut_exe_i [13]), .Z(n3252) );
HS65_LH_IVX7 U4440 ( .A(\u_DataPath/dataOut_exe_i [4]), .Z(n8574) );
HS65_LH_IVX9 U4441 ( .A(\u_DataPath/from_mem_data_out_i [1]), .Z(n3021) );
HS65_LH_NAND2X2 U4442 ( .A(n2733), .B(\u_DataPath/pc4_to_idexreg_i [19]),
.Z(n8206) );
HS65_LH_NAND2X2 U4443 ( .A(n2733), .B(\u_DataPath/pc4_to_idexreg_i [27]),
.Z(n8194) );
HS65_LH_NOR2X5 U4444 ( .A(n8943), .B(n9210), .Z(n6026) );
HS65_LH_NAND2X2 U4445 ( .A(n2733), .B(\u_DataPath/pc4_to_idexreg_i [7]), .Z(
n8223) );
HS65_LH_NAND2X2 U4446 ( .A(n2733), .B(\u_DataPath/pc4_to_idexreg_i [8]), .Z(
n8222) );
HS65_LH_NAND2X2 U4447 ( .A(n2733), .B(n9426), .Z(n8208) );
HS65_LH_NAND2X2 U4448 ( .A(n2733), .B(n9425), .Z(n8193) );
HS65_LH_NAND2X2 U4449 ( .A(n2733), .B(\u_DataPath/pc4_to_idexreg_i [17]),
.Z(n8209) );
HS65_LH_NAND2X2 U4450 ( .A(n2733), .B(n9424), .Z(n8211) );
HS65_LH_IVX7 U4451 ( .A(\u_DataPath/dataOut_exe_i [11]), .Z(n3232) );
HS65_LH_NAND2X2 U4452 ( .A(n2733), .B(n9423), .Z(n8221) );
HS65_LH_NAND2X2 U4455 ( .A(n2733), .B(\u_DataPath/pc4_to_idexreg_i [29]),
.Z(n8191) );
HS65_LH_NAND2X7 U4456 ( .A(n8968), .B(n9217), .Z(n5997) );
HS65_LH_NAND2X2 U4457 ( .A(n2733), .B(\u_DataPath/pc4_to_idexreg_i [10]),
.Z(n8219) );
HS65_LH_NAND2X7 U4458 ( .A(n9077), .B(n9218), .Z(n6063) );
HS65_LH_NAND2X2 U4459 ( .A(n2733), .B(n9422), .Z(n8218) );
HS65_LH_NAND2X2 U4460 ( .A(n2733), .B(n9421), .Z(n8190) );
HS65_LH_NAND2X2 U4461 ( .A(n2733), .B(n9419), .Z(n8216) );
HS65_LH_IVX7 U4462 ( .A(\u_DataPath/dataOut_exe_i [10]), .Z(n3242) );
HS65_LH_NAND2X2 U4463 ( .A(n2733), .B(\u_DataPath/pc4_to_idexreg_i [13]),
.Z(n8214) );
HS65_LH_NAND2X2 U4464 ( .A(n2733), .B(\u_DataPath/pc4_to_idexreg_i [15]),
.Z(n8212) );
HS65_LH_IVX4 U4465 ( .A(n9226), .Z(n7724) );
HS65_LH_NAND2X2 U4466 ( .A(n2733), .B(\u_DataPath/pc4_to_idexreg_i [31]),
.Z(n8289) );
HS65_LH_NAND2X2 U4467 ( .A(n2733), .B(\u_DataPath/pc4_to_idexreg_i [14]),
.Z(n8213) );
HS65_LH_NAND2X2 U4468 ( .A(n2733), .B(\u_DataPath/pc4_to_idexreg_i [1]), .Z(
n8229) );
HS65_LH_IVX9 U4469 ( .A(n8724), .Z(n3345) );
HS65_LH_NAND2X5 U4470 ( .A(n9033), .B(n9215), .Z(n6099) );
HS65_LH_NAND2X7 U4471 ( .A(n8913), .B(n9219), .Z(n6094) );
HS65_LH_NAND2X2 U4472 ( .A(n2733), .B(n9420), .Z(n8200) );
HS65_LH_IVX2 U4474 ( .A(n9116), .Z(\u_DataPath/u_execute/link_value_i [2])
);
HS65_LH_NAND2X7 U4475 ( .A(n9030), .B(n9223), .Z(n6040) );
HS65_LH_NAND2X2 U4476 ( .A(n2733), .B(\u_DataPath/pc4_to_idexreg_i [3]), .Z(
n8227) );
HS65_LH_NAND2X2 U4477 ( .A(n2733), .B(n9429), .Z(n8202) );
HS65_LH_NAND2X2 U4478 ( .A(n2733), .B(\u_DataPath/pc4_to_idexreg_i [25]),
.Z(n8197) );
HS65_LH_NAND2X2 U4479 ( .A(n2733), .B(\u_DataPath/pc4_to_idexreg_i [4]), .Z(
n8226) );
HS65_LH_NAND2X2 U4480 ( .A(n2733), .B(n9428), .Z(n8204) );
HS65_LH_IVX4 U4481 ( .A(n9230), .Z(n7793) );
HS65_LH_NAND2X2 U4483 ( .A(n2733), .B(\u_DataPath/pc4_to_idexreg_i [5]), .Z(
n8225) );
HS65_LH_NAND2X2 U4484 ( .A(n2733), .B(\u_DataPath/pc4_to_idexreg_i [24]),
.Z(n8198) );
HS65_LH_IVX7 U4487 ( .A(\u_DataPath/dataOut_exe_i [5]), .Z(n3336) );
HS65_LL_IVX7 U4489 ( .A(\u_DataPath/jaddr_i [16]), .Z(n8152) );
HS65_LH_IVX2 U4490 ( .A(Data_out_fromRAM[30]), .Z(n8402) );
HS65_LH_IVX2 U4491 ( .A(Data_out_fromRAM[29]), .Z(n8447) );
HS65_LH_IVX2 U4493 ( .A(Data_out_fromRAM[24]), .Z(n8370) );
HS65_LH_IVX2 U4494 ( .A(Data_out_fromRAM[27]), .Z(n8376) );
HS65_LH_IVX2 U4495 ( .A(Data_out_fromRAM[26]), .Z(n8319) );
HS65_LH_IVX2 U4496 ( .A(Data_out_fromRAM[25]), .Z(n8335) );
HS65_LH_OAI12X6 U4497 ( .A(n5715), .B(n5714), .C(n5713), .Z(n7860) );
HS65_LL_NAND2X4 U4498 ( .A(n7907), .B(n5694), .Z(n7855) );
HS65_LL_NAND2X2 U4499 ( .A(n7858), .B(n9063), .Z(
\u_DataPath/dataOut_exe_i [19]) );
HS65_LL_OAI12X3 U4501 ( .A(n9189), .B(n9001), .C(n8395), .Z(
\u_DataPath/dataOut_exe_i [30]) );
HS65_LL_OAI12X3 U4502 ( .A(n9189), .B(n8895), .C(n8398), .Z(
\u_DataPath/dataOut_exe_i [14]) );
HS65_LL_NAND2X2 U4503 ( .A(n7845), .B(n9060), .Z(
\u_DataPath/dataOut_exe_i [21]) );
HS65_LL_OAI12X3 U4505 ( .A(n9189), .B(n8889), .C(n8405), .Z(
\u_DataPath/dataOut_exe_i [17]) );
HS65_LL_AOI21X2 U4508 ( .A(n5643), .B(n5642), .C(n5641), .Z(n5674) );
HS65_LH_NAND2X7 U4509 ( .A(n7843), .B(n9062), .Z(
\u_DataPath/dataOut_exe_i [18]) );
HS65_LL_OAI12X3 U4510 ( .A(n9189), .B(n9059), .C(n8409), .Z(
\u_DataPath/dataOut_exe_i [20]) );
HS65_LL_NOR2AX3 U4511 ( .A(n4912), .B(n4911), .Z(n8474) );
HS65_LL_NAND2X2 U4512 ( .A(n4910), .B(n4909), .Z(n4911) );
HS65_LL_NAND2X2 U4513 ( .A(n3695), .B(n3694), .Z(n3696) );
HS65_LH_AOI21X6 U4514 ( .A(n5643), .B(n4280), .C(n4279), .Z(n4281) );
HS65_LH_NAND2X7 U4515 ( .A(n5643), .B(n3624), .Z(n3625) );
HS65_LH_NAND2X7 U4518 ( .A(n5643), .B(n3742), .Z(n3743) );
HS65_LL_NAND3X3 U4519 ( .A(n3998), .B(n3997), .C(n3996), .Z(n3999) );
HS65_LH_NAND2X7 U4520 ( .A(n5643), .B(n3693), .Z(n3694) );
HS65_LHS_XNOR2X6 U4521 ( .A(n4429), .B(n4428), .Z(n4450) );
HS65_LL_OAI21X2 U4522 ( .A(n5633), .B(n4240), .C(n4239), .Z(n4241) );
HS65_LH_AOI21X6 U4523 ( .A(n5285), .B(n4569), .C(n4568), .Z(n8464) );
HS65_LH_OAI12X3 U4524 ( .A(n4377), .B(n2859), .C(n4376), .Z(n4378) );
HS65_LL_OAI21X2 U4525 ( .A(n2859), .B(n3739), .C(n3738), .Z(n3740) );
HS65_LH_OAI12X3 U4527 ( .A(n3706), .B(n5633), .C(n3705), .Z(n3707) );
HS65_LHS_XOR2X3 U4529 ( .A(n4847), .B(n2859), .Z(n4861) );
HS65_LH_NOR2AX3 U4530 ( .A(n5672), .B(n5251), .Z(n5252) );
HS65_LL_OAI21X2 U4531 ( .A(n2859), .B(n4224), .C(n4223), .Z(n4225) );
HS65_LL_OAI21X2 U4532 ( .A(n3621), .B(n2859), .C(n3620), .Z(n3622) );
HS65_LH_AOI21X6 U4533 ( .A(n5285), .B(n4605), .C(n4604), .Z(n8463) );
HS65_LH_AOI12X2 U4534 ( .A(n3634), .B(n5195), .C(n3633), .Z(n3635) );
HS65_LH_OAI21X3 U4535 ( .A(n4993), .B(n4992), .C(n4991), .Z(n4994) );
HS65_LH_IVX4 U4536 ( .A(n4473), .Z(n4446) );
HS65_LL_AOI21X2 U4537 ( .A(n5492), .B(n4781), .C(n5122), .Z(n5159) );
HS65_LH_IVX4 U4538 ( .A(n5559), .Z(n5539) );
HS65_LH_IVX4 U4539 ( .A(n5210), .Z(n5213) );
HS65_LH_NAND2X5 U4541 ( .A(n3688), .B(n5210), .Z(n3690) );
HS65_LH_NAND3X3 U4543 ( .A(n5515), .B(n4050), .C(n5526), .Z(n5110) );
HS65_LH_OAI21X3 U4546 ( .A(n4751), .B(n5656), .C(n3771), .Z(n3787) );
HS65_LL_OAI12X3 U4550 ( .A(n4085), .B(n3481), .C(n3479), .Z(n3617) );
HS65_LH_NAND2X4 U4551 ( .A(n4222), .B(n5210), .Z(n4224) );
HS65_LH_NAND2X4 U4552 ( .A(n5429), .B(n5458), .Z(n5461) );
HS65_LH_NAND2X4 U4553 ( .A(n5029), .B(n5028), .Z(n5076) );
HS65_LH_NAND2X4 U4555 ( .A(n4528), .B(n4164), .Z(n3767) );
HS65_LL_IVX4 U4558 ( .A(n4928), .Z(n4085) );
HS65_LH_NAND2X4 U4560 ( .A(n3737), .B(n2867), .Z(n3739) );
HS65_LH_NAND2X4 U4562 ( .A(n3704), .B(n5631), .Z(n3706) );
HS65_LH_NAND2X5 U4563 ( .A(n4916), .B(n3897), .Z(n3899) );
HS65_LH_NAND2X4 U4564 ( .A(n5131), .B(n4578), .Z(n3914) );
HS65_LH_NAND2AX7 U4565 ( .A(n4689), .B(n4688), .Z(n4693) );
HS65_LH_OAI12X3 U4566 ( .A(n5147), .B(n5146), .C(n5145), .Z(n5148) );
HS65_LH_NAND2X7 U4567 ( .A(n5488), .B(n5487), .Z(n5489) );
HS65_LH_NAND3X5 U4568 ( .A(n4757), .B(n4945), .C(n4756), .Z(n4758) );
HS65_LH_IVX9 U4569 ( .A(n4522), .Z(n5666) );
HS65_LH_NAND2X4 U4570 ( .A(n4396), .B(n4395), .Z(n4397) );
HS65_LH_NOR2X6 U4571 ( .A(n4913), .B(n3282), .Z(n3897) );
HS65_LH_OAI12X3 U4572 ( .A(n5456), .B(n5455), .C(n5454), .Z(n5457) );
HS65_LH_NOR2X5 U4574 ( .A(n5456), .B(n5428), .Z(n5458) );
HS65_LH_NOR2X3 U4575 ( .A(n4955), .B(n5146), .Z(n4956) );
HS65_LH_OAI211X4 U4577 ( .A(n5656), .B(n4613), .C(n4612), .D(n4611), .Z(
n4620) );
HS65_LH_OAI21X3 U4579 ( .A(n5412), .B(n5411), .C(n5410), .Z(n5413) );
HS65_LH_NOR2X3 U4580 ( .A(n5646), .B(n4119), .Z(n4123) );
HS65_LH_NOR2X5 U4581 ( .A(n4220), .B(n4317), .Z(n4222) );
HS65_LH_NAND2X5 U4582 ( .A(n5661), .B(n5174), .Z(n5175) );
HS65_LH_AOI12X2 U4583 ( .A(n4476), .B(n4632), .C(n4109), .Z(n4110) );
HS65_LH_IVX7 U4584 ( .A(n4391), .Z(n3522) );
HS65_LH_IVX7 U4586 ( .A(n4291), .Z(n4292) );
HS65_LH_NAND3X3 U4587 ( .A(n5237), .B(n5236), .C(n5235), .Z(n5238) );
HS65_LH_NAND2X5 U4588 ( .A(n3792), .B(n3791), .Z(n3793) );
HS65_LH_OAI21X3 U4589 ( .A(n5646), .B(n4522), .C(n4267), .Z(n4275) );
HS65_LH_IVX9 U4590 ( .A(n3913), .Z(n4578) );
HS65_LH_NOR3X4 U4591 ( .A(n4710), .B(n4730), .C(n4709), .Z(n4733) );
HS65_LH_NAND2X5 U4592 ( .A(n5643), .B(n4599), .Z(n4600) );
HS65_LH_IVX7 U4593 ( .A(n4332), .Z(n3388) );
HS65_LH_AOI22X4 U4594 ( .A(n5131), .B(n4157), .C(n4887), .D(n4950), .Z(n4171) );
HS65_LH_NAND2X4 U4595 ( .A(n5661), .B(n5203), .Z(n3461) );
HS65_LH_NAND2X4 U4597 ( .A(n5618), .B(n5243), .Z(n3712) );
HS65_LH_IVX4 U4598 ( .A(n4185), .Z(n3723) );
HS65_LH_NOR2X6 U4599 ( .A(n5510), .B(n5583), .Z(n5536) );
HS65_LH_IVX9 U4604 ( .A(n4176), .Z(n5240) );
HS65_LH_IVX7 U4605 ( .A(n5505), .Z(n5562) );
HS65_LH_IVX9 U4608 ( .A(n4393), .Z(n4889) );
HS65_LH_NOR2X5 U4609 ( .A(n4320), .B(n4317), .Z(n4322) );
HS65_LH_NOR2X3 U4610 ( .A(n4333), .B(n4330), .Z(n4335) );
HS65_LH_AOI22X3 U4612 ( .A(n4508), .B(n4344), .C(n4516), .D(n4120), .Z(n3557) );
HS65_LH_NAND2X7 U4613 ( .A(n4015), .B(n4017), .Z(n3952) );
HS65_LH_IVX7 U4615 ( .A(n4290), .Z(n4293) );
HS65_LH_NOR2X5 U4617 ( .A(n3800), .B(n3685), .Z(n3688) );
HS65_LH_IVX9 U4618 ( .A(n3905), .Z(n4007) );
HS65_LH_NOR2X5 U4621 ( .A(n3747), .B(n3631), .Z(n3634) );
HS65_LH_NAND3X3 U4622 ( .A(n4672), .B(n5517), .C(n5296), .Z(n5333) );
HS65_LL_AOI21X2 U4623 ( .A(n5208), .B(n5211), .C(n3619), .Z(n3620) );
HS65_LH_NAND2X5 U4624 ( .A(n5453), .B(n5424), .Z(n5456) );
HS65_LH_NOR3X3 U4626 ( .A(n5522), .B(n5542), .C(n5099), .Z(n5100) );
HS65_LH_NAND2X5 U4627 ( .A(n4774), .B(n4773), .Z(n4775) );
HS65_LH_IVX9 U4628 ( .A(n4317), .Z(n3505) );
HS65_LH_OAI21X3 U4630 ( .A(n3863), .B(n3862), .C(n5229), .Z(n3864) );
HS65_LH_OAI211X3 U4631 ( .A(n5360), .B(n5359), .C(n5358), .D(n5478), .Z(
n5369) );
HS65_LH_NAND2X7 U4632 ( .A(n3574), .B(n3573), .Z(n3580) );
HS65_LH_CNIVX3 U4635 ( .A(n3375), .Z(n3210) );
HS65_LH_NAND2X4 U4636 ( .A(n5446), .B(n5427), .Z(n5428) );
HS65_LH_NAND2X5 U4639 ( .A(n3684), .B(n3683), .Z(n3692) );
HS65_LH_IVX7 U4640 ( .A(n4038), .Z(n4039) );
HS65_LH_NAND3X5 U4641 ( .A(n4591), .B(n4590), .C(n4589), .Z(n4617) );
HS65_LH_IVX9 U4642 ( .A(n4426), .Z(n5607) );
HS65_LH_IVX9 U4644 ( .A(n4835), .Z(n4468) );
HS65_LH_AOI22X3 U4645 ( .A(n9349), .B(n5321), .C(n5131), .D(n4584), .Z(n4585) );
HS65_LH_IVX4 U4646 ( .A(n4894), .Z(n3598) );
HS65_LH_AOI12X2 U4647 ( .A(n3586), .B(n3585), .C(n4581), .Z(n3588) );
HS65_LH_NAND3X3 U4648 ( .A(n5469), .B(n5468), .C(n5467), .Z(n5470) );
HS65_LH_NOR2X3 U4649 ( .A(n4643), .B(n4639), .Z(n4646) );
HS65_LH_NAND2X7 U4650 ( .A(n3650), .B(n3649), .Z(n3651) );
HS65_LH_IVX4 U4651 ( .A(n4496), .Z(n4499) );
HS65_LH_OA12X9 U4652 ( .A(n5656), .B(n4945), .C(n4944), .Z(n2898) );
HS65_LH_AOI12X2 U4654 ( .A(n5139), .B(n5229), .C(n5138), .Z(n5140) );
HS65_LH_NOR2X3 U4655 ( .A(n4134), .B(n4939), .Z(n4610) );
HS65_LH_NOR2X5 U4656 ( .A(n5627), .B(n3701), .Z(n3704) );
HS65_LH_IVX7 U4657 ( .A(n5499), .Z(n5563) );
HS65_LH_NAND2X4 U4658 ( .A(n5547), .B(n5091), .Z(n5474) );
HS65_LH_NOR3X4 U4660 ( .A(n4772), .B(n4771), .C(n4770), .Z(n4773) );
HS65_LH_NOR2X3 U4661 ( .A(n4328), .B(n4333), .Z(n5424) );
HS65_LH_NAND2X7 U4662 ( .A(n3615), .B(n3614), .Z(n3623) );
HS65_LH_NAND2X5 U4663 ( .A(n3750), .B(n3383), .Z(n3387) );
HS65_LH_NOR2X6 U4664 ( .A(n3640), .B(n3639), .Z(n3643) );
HS65_LH_NOR2X5 U4666 ( .A(n5389), .B(n4667), .Z(n4668) );
HS65_LH_NAND2X7 U4667 ( .A(n4154), .B(n3867), .Z(n3863) );
HS65_LH_IVX4 U4668 ( .A(n5514), .Z(n5520) );
HS65_LH_NAND2X7 U4669 ( .A(n4542), .B(n4462), .Z(n3862) );
HS65_LH_IVX7 U4670 ( .A(n5083), .Z(n5304) );
HS65_LH_NAND2X7 U4671 ( .A(n5344), .B(n5564), .Z(n4720) );
HS65_LH_OAI12X3 U4672 ( .A(n5183), .B(n5182), .C(n5181), .Z(n5184) );
HS65_LH_IVX4 U4673 ( .A(n4580), .Z(n4552) );
HS65_LH_IVX4 U4675 ( .A(n5545), .Z(n5557) );
HS65_LH_NAND2X5 U4676 ( .A(n3529), .B(n3444), .Z(n4488) );
HS65_LH_NOR2X6 U4677 ( .A(n5363), .B(n5471), .Z(n5507) );
HS65_LH_NAND2X4 U4679 ( .A(n5300), .B(n5516), .Z(n5479) );
HS65_LH_NAND2X4 U4680 ( .A(n5357), .B(n5356), .Z(n5478) );
HS65_LH_NOR2X6 U4681 ( .A(n4984), .B(n4582), .Z(n3982) );
HS65_LH_IVX4 U4682 ( .A(n4462), .Z(n4464) );
HS65_LH_IVX4 U4683 ( .A(n4059), .Z(n3535) );
HS65_LH_OAI12X3 U4684 ( .A(n2848), .B(n4795), .C(n3524), .Z(n3528) );
HS65_LH_IVX7 U4686 ( .A(n4027), .Z(n4031) );
HS65_LH_NAND2X5 U4687 ( .A(n3749), .B(n3748), .Z(n3755) );
HS65_LH_IVX7 U4688 ( .A(n3867), .Z(n3868) );
HS65_LH_IVX7 U4689 ( .A(n4289), .Z(n4218) );
HS65_LH_IVX4 U4690 ( .A(n3956), .Z(n3957) );
HS65_LH_NAND2X5 U4692 ( .A(n5531), .B(n5293), .Z(n3517) );
HS65_LH_IVX9 U4693 ( .A(n5571), .Z(n4727) );
HS65_LH_NAND2X7 U4694 ( .A(n3544), .B(n3543), .Z(n3546) );
HS65_LH_NAND2X4 U4695 ( .A(n5534), .B(n5356), .Z(n5360) );
HS65_LH_IVX4 U4696 ( .A(n5500), .Z(n5501) );
HS65_LH_NAND2X4 U4698 ( .A(n5437), .B(n5420), .Z(n5441) );
HS65_LH_NAND2X5 U4699 ( .A(n4060), .B(n4059), .Z(n4064) );
HS65_LH_OAI21X3 U4700 ( .A(n3756), .B(n2854), .C(n3758), .Z(n4255) );
HS65_LH_NAND3X5 U4702 ( .A(n5232), .B(n4808), .C(n4739), .Z(n4746) );
HS65_LH_NAND2X5 U4703 ( .A(n4062), .B(n4061), .Z(n4063) );
HS65_LH_IVX4 U4704 ( .A(n3682), .Z(n3683) );
HS65_LH_NOR2X6 U4706 ( .A(n4811), .B(n4582), .Z(n3400) );
HS65_LH_IVX9 U4709 ( .A(n5450), .Z(n4231) );
HS65_LH_IVX9 U4710 ( .A(n5183), .Z(n5139) );
HS65_LH_IVX7 U4711 ( .A(n4022), .Z(n4024) );
HS65_LH_IVX4 U4714 ( .A(n5502), .Z(n5012) );
HS65_LH_NAND2X4 U4716 ( .A(\sub_x_53/A[29] ), .B(n4587), .Z(n3441) );
HS65_LH_NAND2X7 U4717 ( .A(n5387), .B(n5324), .Z(n5464) );
HS65_LH_IVX4 U4718 ( .A(n4340), .Z(n4066) );
HS65_LH_NAND2X7 U4719 ( .A(n2854), .B(n5567), .Z(n5344) );
HS65_LH_IVX9 U4720 ( .A(n4374), .Z(n4424) );
HS65_LH_IVX9 U4721 ( .A(n4627), .Z(n4629) );
HS65_LH_NOR2X6 U4722 ( .A(\sub_x_53/A[29] ), .B(n5447), .Z(n4328) );
HS65_LH_NAND2X5 U4724 ( .A(n5509), .B(n5508), .Z(n5583) );
HS65_LH_NOR2AX3 U4725 ( .A(n5136), .B(\sub_x_53/A[0] ), .Z(n5035) );
HS65_LH_NAND2X4 U4726 ( .A(n4628), .B(n4158), .Z(n4160) );
HS65_LH_NAND2X7 U4727 ( .A(\lte_x_59/B[1] ), .B(n4587), .Z(n5128) );
HS65_LH_NAND2X5 U4728 ( .A(n4819), .B(n4818), .Z(n4820) );
HS65_LH_NAND2X4 U4729 ( .A(\sub_x_53/A[30] ), .B(n2873), .Z(n5450) );
HS65_LH_NAND2X5 U4730 ( .A(n5098), .B(n5552), .Z(n5556) );
HS65_LH_IVX7 U4731 ( .A(n4425), .Z(n4375) );
HS65_LH_NAND2X5 U4732 ( .A(n5097), .B(n5096), .Z(n5545) );
HS65_LH_NAND2X5 U4733 ( .A(\lte_x_59/B[24] ), .B(n4544), .Z(n3964) );
HS65_LH_NOR2X3 U4734 ( .A(n3698), .B(n5627), .Z(n5437) );
HS65_LH_NOR2X6 U4735 ( .A(n4675), .B(n4674), .Z(n5514) );
HS65_LH_CNIVX3 U4736 ( .A(n4407), .Z(n4408) );
HS65_LH_IVX7 U4737 ( .A(n4846), .Z(n3561) );
HS65_LH_NAND2X7 U4738 ( .A(\sub_x_53/A[27] ), .B(n2845), .Z(n3758) );
HS65_LL_NOR2X2 U4739 ( .A(n5254), .B(n4250), .Z(n3497) );
HS65_LHS_XOR2X3 U4740 ( .A(n5747), .B(n5746), .Z(\u_DataPath/toPC2_i [28])
);
HS65_LH_IVX9 U4741 ( .A(n5530), .Z(n5295) );
HS65_LH_NOR2X6 U4743 ( .A(n4144), .B(n4100), .Z(n4638) );
HS65_LH_IVX9 U4745 ( .A(n3641), .Z(n4794) );
HS65_LL_NAND2X4 U4746 ( .A(\sub_x_53/A[25] ), .B(n3593), .Z(n3615) );
HS65_LH_IVX9 U4747 ( .A(\sub_x_53/A[0] ), .Z(n4660) );
HS65_LH_NOR2X6 U4748 ( .A(\sub_x_53/A[25] ), .B(n3593), .Z(n3613) );
HS65_LH_IVX9 U4749 ( .A(n4144), .Z(n4099) );
HS65_LH_IVX9 U4750 ( .A(n3558), .Z(n3472) );
HS65_LH_IVX4 U4751 ( .A(n3893), .Z(n4678) );
HS65_LH_NAND2X5 U4752 ( .A(\sub_x_53/A[27] ), .B(n4588), .Z(n3650) );
HS65_LH_NOR2X6 U4753 ( .A(\sub_x_53/A[0] ), .B(n5123), .Z(n4821) );
HS65_LH_IVX9 U4754 ( .A(n3616), .Z(n5208) );
HS65_LL_IVX4 U4756 ( .A(n4516), .Z(n4842) );
HS65_LL_NAND2X4 U4757 ( .A(n3236), .B(n3238), .Z(n3239) );
HS65_LH_IVX9 U4759 ( .A(\lte_x_59/B[21] ), .Z(n4701) );
HS65_LH_NOR2X6 U4760 ( .A(n2858), .B(n5398), .Z(n4011) );
HS65_LH_NAND2X7 U4761 ( .A(\lte_x_59/B[9] ), .B(n2871), .Z(n4904) );
HS65_LH_NOR2X6 U4763 ( .A(\lte_x_59/B[22] ), .B(n2869), .Z(n5627) );
HS65_LH_NAND3X3 U4765 ( .A(n2851), .B(n5136), .C(n4805), .Z(n4340) );
HS65_LH_NOR2X6 U4766 ( .A(\sub_x_53/A[20] ), .B(n4699), .Z(n4374) );
HS65_LH_NOR2X5 U4767 ( .A(\lte_x_59/B[15] ), .B(n4677), .Z(n5406) );
HS65_LH_IVX4 U4769 ( .A(n5361), .Z(n5508) );
HS65_LH_IVX4 U4770 ( .A(\lte_x_59/B[14] ), .Z(n4676) );
HS65_LL_OAI21X2 U4772 ( .A(n4105), .B(n4477), .C(n4107), .Z(n4627) );
HS65_LH_IVX4 U4773 ( .A(n4817), .Z(n4818) );
HS65_LH_IVX9 U4774 ( .A(\lte_x_59/B[18] ), .Z(n4986) );
HS65_LH_NAND2X7 U4775 ( .A(n4477), .B(n4476), .Z(n4478) );
HS65_LH_NAND2X7 U4776 ( .A(\sub_x_53/A[17] ), .B(n5001), .Z(n3559) );
HS65_LH_NAND2X7 U4777 ( .A(n4481), .B(n4480), .Z(n4482) );
HS65_LH_NAND2X4 U4778 ( .A(n5234), .B(n4553), .Z(n4554) );
HS65_LH_OAI22X3 U4779 ( .A(n8906), .B(n9186), .C(n9140), .D(n8759), .Z(
\u_DataPath/data_read_ex_1_i [10]) );
HS65_LH_OAI22X3 U4781 ( .A(n7306), .B(n8168), .C(n7914), .D(n8167), .Z(
\u_DataPath/data_read_ex_1_i [1]) );
HS65_LH_OAI22X3 U4782 ( .A(n7306), .B(n8275), .C(n7914), .D(n8274), .Z(
\u_DataPath/data_read_ex_1_i [8]) );
HS65_LH_OAI22X3 U4783 ( .A(n7306), .B(n8321), .C(n7914), .D(n8320), .Z(
\u_DataPath/data_read_ex_1_i [26]) );
HS65_LH_OAI22X3 U4784 ( .A(n7306), .B(n8434), .C(n7914), .D(n8174), .Z(
\u_DataPath/data_read_ex_1_i [3]) );
HS65_LH_OAI22X3 U4785 ( .A(n7306), .B(n8314), .C(n7914), .D(n8313), .Z(
\u_DataPath/data_read_ex_1_i [6]) );
HS65_LH_OAI22X3 U4787 ( .A(n7306), .B(n8293), .C(n7914), .D(n8292), .Z(
\u_DataPath/data_read_ex_1_i [12]) );
HS65_LH_OAI22X3 U4788 ( .A(n7306), .B(n8304), .C(n7914), .D(n8303), .Z(
\u_DataPath/data_read_ex_1_i [7]) );
HS65_LH_OAI22X3 U4789 ( .A(n7306), .B(n8326), .C(n7914), .D(n8325), .Z(
\u_DataPath/data_read_ex_1_i [19]) );
HS65_LH_IVX18 U4790 ( .A(n4683), .Z(n5398) );
HS65_LH_IVX9 U4791 ( .A(n4823), .Z(n3486) );
HS65_LH_NAND2X7 U4793 ( .A(n8258), .B(n3237), .Z(n3238) );
HS65_LH_IVX4 U4794 ( .A(n4763), .Z(n4592) );
HS65_LH_NOR2X5 U4795 ( .A(n5656), .B(n4762), .Z(n3879) );
HS65_LL_NOR2X6 U4796 ( .A(n3159), .B(n3158), .Z(\sub_x_53/A[23] ) );
HS65_LH_IVX7 U4797 ( .A(n4637), .Z(n3330) );
HS65_LH_IVX9 U4798 ( .A(n4100), .Z(n4480) );
HS65_LH_IVX9 U4800 ( .A(n4481), .Z(n4102) );
HS65_LL_NOR2X3 U4802 ( .A(n3108), .B(n3107), .Z(n3547) );
HS65_LH_OAI22X6 U4803 ( .A(n3264), .B(\u_DataPath/dataOut_exe_i [23]), .C(
n8243), .D(n3409), .Z(n3158) );
HS65_LL_OAI12X6 U4804 ( .A(n3173), .B(n2905), .C(n3172), .Z(n5654) );
HS65_LL_IVX7 U4805 ( .A(n3401), .Z(n3399) );
HS65_LH_NAND2X5 U4806 ( .A(\sub_x_53/A[2] ), .B(n5088), .Z(n4595) );
HS65_LH_IVX4 U4807 ( .A(n8563), .Z(\u_DataPath/mem_writedata_out_i [28]) );
HS65_LH_IVX9 U4809 ( .A(n5231), .Z(n3372) );
HS65_LL_OAI12X3 U4810 ( .A(n7854), .B(n3409), .C(n3198), .Z(n3199) );
HS65_LH_IVX9 U4811 ( .A(n5422), .Z(n5447) );
HS65_LL_AOI12X4 U4812 ( .A(n6113), .B(n6115), .C(n5942), .Z(n5955) );
HS65_LL_IVX27 U4813 ( .A(n3270), .Z(n3409) );
HS65_LL_NAND2X2 U4815 ( .A(n3251), .B(n8517), .Z(n3255) );
HS65_LH_NAND3X3 U4816 ( .A(n8562), .B(n8566), .C(n8561), .Z(n8563) );
HS65_LL_NOR2X6 U4818 ( .A(n7799), .B(n7798), .Z(n7122) );
HS65_LH_AOI22X3 U4819 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][24] ), .B(n7265),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[11][24] ), .D(
n6363), .Z(n6287) );
HS65_LH_AOI22X3 U4821 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][25] ), .B(n7165),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[28][25] ), .D(
n6624), .Z(n7150) );
HS65_LH_AO22X9 U4822 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][19] ), .B(n7283),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[20][19] ), .D(
n7282), .Z(n6526) );
HS65_LH_AOI22X3 U4823 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][24] ), .B(n7165),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[28][24] ), .D(
n6624), .Z(n6292) );
HS65_LH_AO22X9 U4824 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][7] ), .B(n7283),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[20][7] ), .D(
n7282), .Z(n6446) );
HS65_LH_AOI22X3 U4825 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][12] ), .B(n7603),
.C(n7333), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][12] ), .Z(n6800)
);
HS65_LH_AOI22X3 U4826 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][10] ), .B(n2887),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[22][10] ), .D(
n7171), .Z(n6402) );
HS65_LH_AOI22X3 U4827 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][22] ), .B(n7165),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[28][22] ), .D(
n6624), .Z(n6272) );
HS65_LH_AOI22X3 U4828 ( .A(n6745), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][29] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][29] ), .D(n7516),
.Z(n7521) );
HS65_LH_AOI22X3 U4829 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][8] ), .B(n7604),
.C(n7334), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][8] ), .Z(n6779)
);
HS65_LH_AO22X9 U4830 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][29] ), .B(n7580),
.C(n7579), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][29] ), .Z(n7512)
);
HS65_LH_AOI22X3 U4834 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][4] ), .B(n6941),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[7][4] ), .D(n6384), .Z(n6643) );
HS65_LH_AOI22X3 U4835 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][24] ), .B(n6376),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[21][24] ), .D(
n7285), .Z(n6294) );
HS65_LH_AOI22X3 U4836 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][29] ), .B(n7286),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[21][29] ), .D(
n7285), .Z(n7288) );
HS65_LH_AOI22X3 U4838 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][22] ), .B(n7265),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[11][22] ), .D(
n6363), .Z(n6267) );
HS65_LH_AOI22X3 U4839 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][30] ), .B(n7165),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[28][30] ), .D(
n6624), .Z(n6137) );
HS65_LH_AO22X9 U4840 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][28] ), .B(n7283),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[20][28] ), .D(
n7282), .Z(n6918) );
HS65_LH_AO22X9 U4841 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][29] ), .B(n7600),
.C(n7599), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][29] ), .Z(n7533)
);
HS65_LH_AOI22X3 U4844 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][30] ), .B(n6376),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[21][30] ), .D(
n7285), .Z(n6142) );
HS65_LH_AO22X9 U4845 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][20] ), .B(n7600),
.C(n7599), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][20] ), .Z(n7487)
);
HS65_LH_AOI22X3 U4847 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][30] ), .B(n6377),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[22][30] ), .D(
n7171), .Z(n6141) );
HS65_LH_AOI22X3 U4849 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][8] ), .B(n7603),
.C(n7333), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][8] ), .Z(n6780)
);
HS65_LH_AOI22X3 U4850 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][30] ), .B(n6941),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[7][30] ), .D(
n6384), .Z(n6155) );
HS65_LH_AOI22X3 U4851 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][24] ), .B(n6377),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[22][24] ), .D(
n7171), .Z(n6293) );
HS65_LH_AOI22X3 U4852 ( .A(n7434), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][1] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][1] ), .D(n7516),
.Z(n6834) );
HS65_LH_AO22X9 U4853 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][3] ), .B(n7580),
.C(n7579), .D(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][3] ), .Z(n7387) );
HS65_LH_AO22X9 U4854 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][15] ), .B(n7283),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[20][15] ), .D(
n7282), .Z(n6381) );
HS65_LH_AO22X9 U4856 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][0] ), .B(n7600),
.C(n7599), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][0] ), .Z(n7447)
);
HS65_LH_AO22X9 U4857 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][3] ), .B(n7429),
.C(n6952), .D(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][3] ), .Z(n7388) );
HS65_LH_AOI22X3 U4858 ( .A(n7428), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][3] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][3] ), .D(n6740),
.Z(n7389) );
HS65_LH_AO22X9 U4859 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][28] ), .B(n7580),
.C(n7579), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][28] ), .Z(n7492)
);
HS65_LH_AOI22X3 U4861 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][23] ), .B(n7265),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[11][23] ), .D(
n2888), .Z(n6227) );
HS65_LH_AOI22X3 U4862 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][16] ), .B(n7165),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[28][16] ), .D(
n6624), .Z(n6170) );
HS65_LH_AO22X9 U4865 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][21] ), .B(n7600),
.C(n7599), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][21] ), .Z(n7608)
);
HS65_LH_AO22X9 U4866 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][23] ), .B(n7170),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[23][23] ), .D(
n6637), .Z(n6235) );
HS65_LH_AO22X9 U4867 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][3] ), .B(n7522),
.C(n6752), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][3] ), .Z(n7398)
);
HS65_LH_AO22X9 U4869 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][23] ), .B(n7293),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[13][23] ), .D(
n7292), .Z(n6239) );
HS65_LH_AO22X9 U4871 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][28] ), .B(n7600),
.C(n7599), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][28] ), .Z(n7507)
);
HS65_LH_AOI22X3 U4873 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][23] ), .B(n7415),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[10][23] ), .D(
n6670), .Z(n7227) );
HS65_LH_AO22X9 U4875 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][24] ), .B(n7600),
.C(n7599), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][24] ), .Z(n7573)
);
HS65_LH_AO22X9 U4876 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][0] ), .B(n7602),
.C(n7601), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][0] ), .Z(n7446)
);
HS65_LH_AOI22X3 U4879 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][23] ), .B(n7165),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[28][23] ), .D(
n6624), .Z(n6232) );
HS65_LH_AOI22X3 U4881 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][26] ), .B(n7604),
.C(n7334), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][26] ), .Z(n7335)
);
HS65_LH_AO22X9 U4882 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][28] ), .B(n7429),
.C(n6952), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][28] ), .Z(n7493)
);
HS65_LH_AOI22X3 U4883 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][12] ), .B(n7604),
.C(n7334), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][12] ), .Z(n6799)
);
HS65_LH_AO22X9 U4884 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][0] ), .B(n7580),
.C(n7579), .D(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][0] ), .Z(n7430) );
HS65_LH_AOI22X3 U4885 ( .A(n7434), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][5] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][5] ), .D(n7516),
.Z(n6706) );
HS65_LH_AO22X9 U4887 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][16] ), .B(n7600),
.C(n7599), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][16] ), .Z(n7553)
);
HS65_LH_AOI22X3 U4890 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][26] ), .B(n7603),
.C(n7333), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][26] ), .Z(n7336)
);
HS65_LH_AOI22X3 U4891 ( .A(n7428), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][28] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][28] ), .D(n6740),
.Z(n7494) );
HS65_LH_AOI22X3 U4892 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][21] ), .B(n7273),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[29][21] ), .D(
n6625), .Z(n6191) );
HS65_LH_AOI22X3 U4893 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][5] ), .B(n7297),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[0][5] ), .D(n6942), .Z(n6943) );
HS65_LH_AO22X9 U4899 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][28] ), .B(n7602),
.C(n7601), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][28] ), .Z(n7506)
);
HS65_LH_AOI22X3 U4900 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][0] ), .B(n7585),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[1][0] ), .D(n2889), .Z(n7437) );
HS65_LH_AOI22X3 U4901 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][27] ), .B(n7165),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[28][27] ), .D(
n6624), .Z(n6212) );
HS65_LH_AOI22X3 U4903 ( .A(n6745), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][28] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][28] ), .D(n7516),
.Z(n7499) );
HS65_LH_AOI22X3 U4904 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][22] ), .B(n6377),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[22][22] ), .D(
n7171), .Z(n6273) );
HS65_LH_AOI22X3 U4907 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][11] ), .B(n7165),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[28][11] ), .D(
n6624), .Z(n6252) );
HS65_LH_AO22X9 U4908 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][24] ), .B(n7580),
.C(n7579), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][24] ), .Z(n7558)
);
HS65_LH_AOI22X3 U4910 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][11] ), .B(n7265),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[11][11] ), .D(
n6363), .Z(n6247) );
HS65_LH_AOI22X3 U4911 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][13] ), .B(n2887),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[22][13] ), .D(
n7171), .Z(n7172) );
HS65_LH_AOI22X3 U4912 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][4] ), .B(n7265),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[11][4] ), .D(
n2888), .Z(n6622) );
HS65_LH_AOI22X3 U4913 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][13] ), .B(n7286),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[21][13] ), .D(
n7285), .Z(n7173) );
HS65_LH_AOI22X3 U4914 ( .A(n7434), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][31] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][31] ), .D(n7516),
.Z(n6679) );
HS65_LH_AO22X9 U4916 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][11] ), .B(n7293),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[13][11] ), .D(
n7292), .Z(n6259) );
HS65_LH_AO22X9 U4918 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][11] ), .B(n7170),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[23][11] ), .D(
n6637), .Z(n6255) );
HS65_LH_AO22X9 U4919 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][0] ), .B(n7283),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[20][0] ), .D(
n7282), .Z(n6425) );
HS65_LH_AOI22X3 U4920 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][13] ), .B(n7265),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[11][13] ), .D(
n6363), .Z(n7163) );
HS65_LH_AOI22X3 U4922 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][14] ), .B(n6377),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[22][14] ), .D(
n7171), .Z(n6313) );
HS65_LH_AOI22X3 U4924 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][6] ), .B(n7604),
.C(n7334), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][6] ), .Z(n7256)
);
HS65_LH_AOI22X3 U4926 ( .A(n7434), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][12] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][12] ), .D(n7516),
.Z(n6794) );
HS65_LH_AO22X9 U4929 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][14] ), .B(n7580),
.C(n7579), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][14] ), .Z(n7367)
);
HS65_LH_AOI22X3 U4930 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][6] ), .B(n7603),
.C(n7333), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][6] ), .Z(n7257)
);
HS65_LH_AO22X9 U4931 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][14] ), .B(n7170),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[23][14] ), .D(
n6637), .Z(n6315) );
HS65_LH_AOI22X3 U4932 ( .A(n6745), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][14] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][14] ), .D(n7516),
.Z(n7374) );
HS65_LH_AOI22X3 U4935 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][15] ), .B(n7604),
.C(n7334), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][15] ), .Z(n7196)
);
HS65_LH_AO22X9 U4937 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][27] ), .B(n7600),
.C(n7599), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][27] ), .Z(n7467)
);
HS65_LH_AOI22X3 U4939 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][15] ), .B(n7603),
.C(n7333), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][15] ), .Z(n7197)
);
HS65_LH_AO22X9 U4940 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][9] ), .B(n7170),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[23][9] ), .D(
n6637), .Z(n7133) );
HS65_LH_AOI22X3 U4941 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][14] ), .B(n7165),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[28][14] ), .D(
n6624), .Z(n6312) );
HS65_LH_AOI22X3 U4943 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][22] ), .B(n6376),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[21][22] ), .D(
n7285), .Z(n6274) );
HS65_LH_AOI22X3 U4946 ( .A(n7434), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][17] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][17] ), .D(n7516),
.Z(n6814) );
HS65_LH_AO22X9 U4947 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][10] ), .B(n7283),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[20][10] ), .D(
n7282), .Z(n6405) );
HS65_LH_AOI22X3 U4950 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][12] ), .B(n7524),
.C(n7593), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][12] ), .Z(n6796)
);
HS65_LH_AOI22X3 U4952 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][17] ), .B(n7297),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[0][17] ), .D(
n6942), .Z(n6899) );
HS65_LH_AO22X9 U4953 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][20] ), .B(n7283),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[20][20] ), .D(
n7282), .Z(n6858) );
HS65_LH_AOI22X3 U4954 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][29] ), .B(n6595),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[14][29] ), .D(
n7264), .Z(n7271) );
HS65_LH_AOI22X3 U4955 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][29] ), .B(n7265),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[11][29] ), .D(
n6363), .Z(n7270) );
HS65_LH_AO22X9 U4958 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][6] ), .B(n7283),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[20][6] ), .D(
n7282), .Z(n6486) );
HS65_LL_NAND2X5 U4959 ( .A(n9209), .B(n7120), .Z(n7798) );
HS65_LL_NAND3X2 U4960 ( .A(n3261), .B(n6125), .C(n8514), .Z(n3262) );
HS65_LH_NOR2X6 U4961 ( .A(n3233), .B(n8510), .Z(n3234) );
HS65_LH_IVX9 U4962 ( .A(n8505), .Z(n3228) );
HS65_LH_NAND3X3 U4963 ( .A(n8535), .B(n8566), .C(n8534), .Z(n8536) );
HS65_LHS_XNOR2X3 U4964 ( .A(n5913), .B(n5912), .Z(\u_DataPath/toPC2_i [23])
);
HS65_LH_NAND2X7 U4965 ( .A(n7678), .B(n7677), .Z(n7754) );
HS65_LL_AOI12X4 U4966 ( .A(n5910), .B(n5912), .C(n5738), .Z(n5770) );
HS65_LH_NAND2X7 U4968 ( .A(n3152), .B(n2874), .Z(n8556) );
HS65_LH_NAND2X7 U4970 ( .A(n3143), .B(n2874), .Z(n8552) );
HS65_LH_NAND2AX7 U4971 ( .A(n8567), .B(n8568), .Z(n4210) );
HS65_LL_NOR2X3 U4972 ( .A(n8854), .B(n3403), .Z(n3187) );
HS65_LL_NOR2X6 U4973 ( .A(n8235), .B(n7921), .Z(n8482) );
HS65_LH_BFX18 U4974 ( .A(n8288), .Z(n7898) );
HS65_LH_NOR2X5 U4975 ( .A(n8722), .B(n4712), .Z(n8567) );
HS65_LL_OAI12X3 U4978 ( .A(n5824), .B(n5827), .C(n5826), .Z(n5912) );
HS65_LL_NOR2X5 U4979 ( .A(n7797), .B(n7796), .Z(n7120) );
HS65_LH_NAND2X4 U4980 ( .A(n8044), .B(n8035), .Z(opcode_i[4]) );
HS65_LH_NAND2X7 U4981 ( .A(n4207), .B(n2866), .Z(n8568) );
HS65_LH_NOR2X5 U4983 ( .A(n8316), .B(n7868), .Z(n8555) );
HS65_LHS_XOR2X3 U4984 ( .A(n7753), .B(n7752), .Z(\u_DataPath/pc_4_i [12]) );
HS65_LHS_XOR2X3 U4985 ( .A(n5774), .B(n5773), .Z(\u_DataPath/toPC2_i [12])
);
HS65_LL_NOR2X5 U4987 ( .A(n8049), .B(n8117), .Z(n8635) );
HS65_LH_NAND2X5 U4988 ( .A(n4714), .B(n8512), .Z(n3233) );
HS65_LL_NOR3X2 U4989 ( .A(n3413), .B(n8394), .C(n7868), .Z(n3315) );
HS65_LH_IVX9 U4990 ( .A(n8509), .Z(n3244) );
HS65_LH_NAND2X5 U4991 ( .A(n7884), .B(\u_DataPath/u_execute/resAdd1_i [16]),
.Z(n7865) );
HS65_LH_NOR2X5 U4992 ( .A(n8835), .B(n4712), .Z(n8497) );
HS65_LL_AOI12X2 U4993 ( .A(n8119), .B(n8118), .C(n8117), .Z(n8128) );
HS65_LH_NOR2X6 U4994 ( .A(n8266), .B(n7868), .Z(n8501) );
HS65_LH_CNIVX3 U4995 ( .A(n4654), .Z(n8495) );
HS65_LHS_XOR2X3 U4996 ( .A(n6008), .B(n6007), .Z(
\u_DataPath/u_execute/resAdd1_i [12]) );
HS65_LH_NOR2X6 U4997 ( .A(\u_DataPath/dataOut_exe_i [27]), .B(n8390), .Z(
n8558) );
HS65_LH_NOR2X5 U4998 ( .A(n8387), .B(n9401), .Z(n8531) );
HS65_LH_NOR2X6 U5000 ( .A(\u_DataPath/dataOut_exe_i [20]), .B(n8390), .Z(
n8538) );
HS65_LH_NAND2X4 U5001 ( .A(n4213), .B(n3407), .Z(n3075) );
HS65_LH_IVX18 U5002 ( .A(\u_DataPath/u_fetch/pc1/N3 ), .Z(n8483) );
HS65_LH_NAND2X7 U5003 ( .A(n3170), .B(n7869), .Z(n8546) );
HS65_LL_NOR2AX3 U5006 ( .A(n3055), .B(n3054), .Z(n3056) );
HS65_LH_NAND2X2 U5007 ( .A(n9376), .B(n8572), .Z(n4188) );
HS65_LL_AOI12X4 U5008 ( .A(n5902), .B(n5904), .C(n5737), .Z(n5827) );
HS65_LH_NAND2X7 U5009 ( .A(n3232), .B(n7869), .Z(n8512) );
HS65_LL_NAND2X2 U5010 ( .A(n9376), .B(n8492), .Z(n3313) );
HS65_LL_OA12X9 U5011 ( .A(n2932), .B(n3045), .C(n3333), .Z(n3082) );
HS65_LH_NAND2X4 U5012 ( .A(n3321), .B(n7802), .Z(n8499) );
HS65_LL_NOR2X5 U5014 ( .A(n7653), .B(n7650), .Z(n7661) );
HS65_LH_NAND2X7 U5018 ( .A(n6013), .B(n6016), .Z(n5939) );
HS65_LH_IVX18 U5019 ( .A(n4829), .Z(n7631) );
HS65_LH_IVX4 U5020 ( .A(n5167), .Z(n7710) );
HS65_LH_NAND2X7 U5021 ( .A(n5805), .B(n5808), .Z(n5736) );
HS65_LLS_XOR2X3 U5022 ( .A(n8969), .B(n7089), .Z(n3057) );
HS65_LH_IVX7 U5023 ( .A(n5716), .Z(n3062) );
HS65_LL_NOR2X3 U5024 ( .A(n6350), .B(n6342), .Z(n6683) );
HS65_LL_NOR2X5 U5025 ( .A(n2886), .B(n6149), .Z(n6619) );
HS65_LH_IVX7 U5026 ( .A(n7905), .Z(n7837) );
HS65_LL_NOR2X5 U5027 ( .A(n4287), .B(n4286), .Z(n5167) );
HS65_LL_OAI21X3 U5028 ( .A(n5926), .B(n6034), .C(n5925), .Z(n5962) );
HS65_LL_NAND2X5 U5029 ( .A(n9111), .B(n3052), .Z(n8262) );
HS65_LL_OAI21X3 U5030 ( .A(n5724), .B(n5832), .C(n5723), .Z(n5758) );
HS65_LL_NOR2X6 U5031 ( .A(n6349), .B(n6341), .Z(n6682) );
HS65_LL_NOR2X5 U5033 ( .A(n6348), .B(n6342), .Z(n6752) );
HS65_LL_NOR2X5 U5034 ( .A(n6150), .B(n6132), .Z(n6626) );
HS65_LH_NAND2X4 U5035 ( .A(n5959), .B(n5958), .Z(n5970) );
HS65_LL_NOR2X5 U5036 ( .A(n6148), .B(n6132), .Z(n6625) );
HS65_LH_NAND2X5 U5037 ( .A(n5924), .B(n6036), .Z(n5926) );
HS65_LL_NOR2X3 U5039 ( .A(n8961), .B(n2959), .Z(n2938) );
HS65_LL_NOR2X5 U5041 ( .A(n2886), .B(n6152), .Z(n6382) );
HS65_LH_NOR2X5 U5043 ( .A(n8480), .B(n8383), .Z(n8586) );
HS65_LH_NAND2X4 U5044 ( .A(n5885), .B(n5831), .Z(n5835) );
HS65_LL_NOR2X6 U5045 ( .A(n2885), .B(n6139), .Z(n6636) );
HS65_LL_NAND2X2 U5048 ( .A(addr_to_iram[16]), .B(n8692), .Z(n7657) );
HS65_LH_NAND2X5 U5049 ( .A(n2733), .B(n8391), .Z(n8415) );
HS65_LH_NAND2X4 U5051 ( .A(n6063), .B(n6062), .Z(n6068) );
HS65_LH_NAND2X7 U5052 ( .A(addr_to_iram[10]), .B(n8698), .Z(n7647) );
HS65_LH_NAND2X4 U5053 ( .A(n2733), .B(n8488), .Z(n8444) );
HS65_LH_NAND2X5 U5054 ( .A(n2733), .B(n8387), .Z(n8457) );
HS65_LH_NAND2X4 U5055 ( .A(n5819), .B(n5818), .Z(n5823) );
HS65_LH_IVX7 U5056 ( .A(n2937), .Z(n3041) );
HS65_LH_NAND2AX4 U5058 ( .A(n8480), .B(n4175), .Z(n7840) );
HS65_LH_CNIVX3 U5059 ( .A(n8136), .Z(\u_DataPath/cw_memwb_i [0]) );
HS65_LH_CNIVX3 U5060 ( .A(n8111), .Z(\u_DataPath/cw_tomem_i [8]) );
HS65_LH_CNIVX3 U5061 ( .A(n8112), .Z(\u_DataPath/cw_tomem_i [7]) );
HS65_LH_CNIVX3 U5062 ( .A(n8110), .Z(\u_DataPath/cw_tomem_i [6]) );
HS65_LH_CNIVX3 U5063 ( .A(n8481), .Z(\u_DataPath/cw_tomem_i [0]) );
HS65_LH_CNIVX3 U5064 ( .A(n8233), .Z(\u_DataPath/jump_i ) );
HS65_LH_IVX9 U5065 ( .A(n6054), .Z(n5944) );
HS65_LH_NAND2X7 U5066 ( .A(\u_DataPath/jaddr_i [22]), .B(n8163), .Z(n2885)
);
HS65_LH_NAND2X7 U5067 ( .A(n3021), .B(n3404), .Z(n3022) );
HS65_LH_CNIVX3 U5068 ( .A(n8218), .Z(\u_DataPath/pc_4_to_ex_i [11]) );
HS65_LH_CNIVX3 U5069 ( .A(n8221), .Z(\u_DataPath/pc_4_to_ex_i [9]) );
HS65_LH_NAND3X5 U5070 ( .A(n2947), .B(n3030), .C(n8139), .Z(n2949) );
HS65_LH_CNIVX3 U5071 ( .A(n8216), .Z(\u_DataPath/pc_4_to_ex_i [12]) );
HS65_LH_CNIVX3 U5072 ( .A(n8222), .Z(\u_DataPath/pc_4_to_ex_i [8]) );
HS65_LH_CNIVX3 U5073 ( .A(n8214), .Z(\u_DataPath/pc_4_to_ex_i [13]) );
HS65_LL_NAND4ABX3 U5074 ( .A(n8766), .B(n8763), .C(n2936), .D(n8107), .Z(
n2937) );
HS65_LH_CNIVX3 U5075 ( .A(n8223), .Z(\u_DataPath/pc_4_to_ex_i [7]) );
HS65_LH_CNIVX3 U5076 ( .A(n8213), .Z(\u_DataPath/pc_4_to_ex_i [14]) );
HS65_LH_CNIVX3 U5077 ( .A(n8224), .Z(\u_DataPath/pc_4_to_ex_i [6]) );
HS65_LH_CNIVX3 U5078 ( .A(n8212), .Z(\u_DataPath/pc_4_to_ex_i [15]) );
HS65_LH_CNIVX3 U5079 ( .A(n8225), .Z(\u_DataPath/pc_4_to_ex_i [5]) );
HS65_LH_CNIVX3 U5080 ( .A(n8211), .Z(\u_DataPath/pc_4_to_ex_i [16]) );
HS65_LH_CNIVX3 U5081 ( .A(n8209), .Z(\u_DataPath/pc_4_to_ex_i [17]) );
HS65_LH_CNIVX3 U5082 ( .A(n8208), .Z(\u_DataPath/pc_4_to_ex_i [18]) );
HS65_LH_CNIVX3 U5083 ( .A(n8226), .Z(\u_DataPath/pc_4_to_ex_i [4]) );
HS65_LH_CNIVX3 U5084 ( .A(n8206), .Z(\u_DataPath/pc_4_to_ex_i [19]) );
HS65_LH_CNIVX3 U5085 ( .A(n8205), .Z(\u_DataPath/pc_4_to_ex_i [20]) );
HS65_LH_CNIVX3 U5086 ( .A(n8204), .Z(\u_DataPath/pc_4_to_ex_i [21]) );
HS65_LH_CNIVX3 U5087 ( .A(n8227), .Z(\u_DataPath/pc_4_to_ex_i [3]) );
HS65_LH_NAND2X5 U5088 ( .A(n5859), .B(n5858), .Z(n5861) );
HS65_LH_CNIVX3 U5089 ( .A(n8219), .Z(\u_DataPath/pc_4_to_ex_i [10]) );
HS65_LH_CNIVX3 U5090 ( .A(n8202), .Z(\u_DataPath/pc_4_to_ex_i [22]) );
HS65_LH_CNIVX3 U5091 ( .A(n8229), .Z(\u_DataPath/u_execute/link_value_i [1])
);
HS65_LH_CNIVX3 U5093 ( .A(n8200), .Z(\u_DataPath/pc_4_to_ex_i [23]) );
HS65_LH_CNIVX3 U5094 ( .A(n8198), .Z(\u_DataPath/pc_4_to_ex_i [24]) );
HS65_LH_CNIVX3 U5095 ( .A(n8197), .Z(\u_DataPath/pc_4_to_ex_i [25]) );
HS65_LH_CNIVX3 U5097 ( .A(n8196), .Z(\u_DataPath/pc_4_to_ex_i [26]) );
HS65_LH_CNIVX3 U5098 ( .A(n8194), .Z(\u_DataPath/pc_4_to_ex_i [27]) );
HS65_LL_NAND2X7 U5099 ( .A(n3030), .B(n8139), .Z(n7618) );
HS65_LH_CNIVX3 U5100 ( .A(n8193), .Z(\u_DataPath/pc_4_to_ex_i [28]) );
HS65_LH_CNIVX3 U5101 ( .A(n8191), .Z(\u_DataPath/pc_4_to_ex_i [29]) );
HS65_LH_CNIVX3 U5102 ( .A(n8190), .Z(\u_DataPath/pc_4_to_ex_i [30]) );
HS65_LH_CNIVX3 U5103 ( .A(n8289), .Z(\u_DataPath/pc_4_to_ex_i [31]) );
HS65_LH_IVX44 U5105 ( .A(n3123), .Z(addr_to_iram[12]) );
HS65_LH_NOR2X6 U5106 ( .A(n6038), .B(n6041), .Z(n6036) );
HS65_LH_NOR2X5 U5107 ( .A(n6097), .B(n6102), .Z(n5922) );
HS65_LH_NOR2X5 U5109 ( .A(n5894), .B(n5899), .Z(n5720) );
HS65_LH_NOR2X6 U5110 ( .A(n7725), .B(n4001), .Z(n7707) );
HS65_LH_NOR2X6 U5111 ( .A(n5817), .B(n5820), .Z(n5814) );
HS65_LH_CNIVX3 U5112 ( .A(n9224), .Z(n7722) );
HS65_LH_NOR2X6 U5113 ( .A(\u_DataPath/jaddr_i [18]), .B(
\u_DataPath/jaddr_i [20]), .Z(n6326) );
HS65_LL_IVX7 U5116 ( .A(\u_DataPath/jaddr_i [17]), .Z(n8153) );
HS65_LH_IVX4 U5117 ( .A(\u_DataPath/dataOut_exe_i [26]), .Z(n3153) );
HS65_LH_NAND2X7 U5118 ( .A(n8969), .B(n9216), .Z(n6014) );
HS65_LH_IVX4 U5119 ( .A(n9205), .Z(n7308) );
HS65_LH_NOR2X5 U5121 ( .A(n8911), .B(n9208), .Z(n5971) );
HS65_LH_OR2X9 U5123 ( .A(n8944), .B(n9213), .Z(n6109) );
HS65_LH_IVX9 U5124 ( .A(n8967), .Z(n2940) );
HS65_LH_IVX4 U5125 ( .A(\u_DataPath/dataOut_exe_i [30]), .Z(n4208) );
HS65_LH_IVX9 U5126 ( .A(n8966), .Z(n2950) );
HS65_LL_NOR2X3 U5127 ( .A(n8761), .B(n8764), .Z(n2936) );
HS65_LH_NAND2X7 U5128 ( .A(n9037), .B(n9212), .Z(n6047) );
HS65_LH_IVX4 U5130 ( .A(\u_DataPath/dataOut_exe_i [23]), .Z(n3160) );
HS65_LH_IVX9 U5131 ( .A(n8766), .Z(n8170) );
HS65_LH_NAND2X5 U5135 ( .A(n9228), .B(n9230), .Z(n4284) );
HS65_LH_NAND2X7 U5138 ( .A(n9231), .B(n9229), .Z(n4002) );
HS65_LHS_XNOR2X3 U5139 ( .A(\u_DataPath/jaddr_i [20]), .B(n8968), .Z(n7102)
);
HS65_LH_IVX4 U5140 ( .A(\u_DataPath/dataOut_exe_i [15]), .Z(n3273) );
HS65_LH_NAND2X4 U5142 ( .A(n9039), .B(n9116), .Z(n5897) );
HS65_LH_CNIVX3 U5145 ( .A(n9221), .Z(n7717) );
HS65_LH_NAND2X5 U5146 ( .A(n9035), .B(n9115), .Z(n5850) );
HS65_LH_IVX4 U5147 ( .A(\u_DataPath/dataOut_exe_i [6]), .Z(n3321) );
HS65_LH_IVX9 U5148 ( .A(\u_DataPath/dataOut_exe_i [16]), .Z(n3205) );
HS65_LH_NOR2X5 U5150 ( .A(opcode_i[3]), .B(opcode_i[5]), .Z(n7642) );
HS65_LH_NAND2X7 U5156 ( .A(n7856), .B(n9074), .Z(
\u_DataPath/dataOut_exe_i [22]) );
HS65_LL_IVX2 U5157 ( .A(n5681), .Z(n5165) );
HS65_LL_IVX4 U5158 ( .A(n5679), .Z(n4834) );
HS65_LL_OAI12X3 U5159 ( .A(n9189), .B(n9073), .C(n8369), .Z(
\u_DataPath/dataOut_exe_i [24]) );
HS65_LL_NAND2X4 U5161 ( .A(n5674), .B(n5673), .Z(n5694) );
HS65_LL_IVX2 U5163 ( .A(n5699), .Z(n5283) );
HS65_LL_AO12X4 U5165 ( .A(n5160), .B(n5159), .C(n5158), .Z(n5710) );
HS65_LL_NAND2X2 U5166 ( .A(n7907), .B(n5699), .Z(n7857) );
HS65_LL_NAND4ABX3 U5167 ( .A(n4453), .B(n5166), .C(n8471), .D(n8470), .Z(
n4454) );
HS65_LL_AOI21X3 U5168 ( .A(n5285), .B(n3746), .C(n3745), .Z(n8459) );
HS65_LL_AOI21X3 U5169 ( .A(n7631), .B(n3813), .C(n3812), .Z(n8460) );
HS65_LL_NAND2X2 U5170 ( .A(n7907), .B(n4453), .Z(n7842) );
HS65_LL_AOI12X4 U5171 ( .A(n5285), .B(n3571), .C(n3570), .Z(n8470) );
HS65_LL_OAI12X3 U5172 ( .A(n5118), .B(n5117), .C(n5116), .Z(n5160) );
HS65_LH_NAND2X7 U5173 ( .A(n7907), .B(n5686), .Z(n7850) );
HS65_LL_NAND2X2 U5174 ( .A(n7907), .B(n5166), .Z(n7844) );
HS65_LL_NAND2X2 U5175 ( .A(n5268), .B(n5267), .Z(n5282) );
HS65_LL_NAND2X2 U5177 ( .A(n3811), .B(n3810), .Z(n3812) );
HS65_LL_NAND2X2 U5178 ( .A(n4228), .B(n4227), .Z(n5602) );
HS65_LL_NOR2AX3 U5179 ( .A(n4452), .B(n4451), .Z(n8471) );
HS65_LH_AOI21X6 U5180 ( .A(n7631), .B(n4000), .C(n3999), .Z(n8472) );
HS65_LL_NAND3X2 U5182 ( .A(n4096), .B(n4095), .C(n4094), .Z(n4097) );
HS65_LL_NAND2X2 U5183 ( .A(n3507), .B(n3506), .Z(n3508) );
HS65_LL_NAND2X2 U5184 ( .A(n3946), .B(n3945), .Z(n3947) );
HS65_LL_AOI21X4 U5185 ( .A(n5285), .B(n4141), .C(n4140), .Z(n8468) );
HS65_LH_NAND2X7 U5186 ( .A(n5643), .B(n4093), .Z(n4094) );
HS65_LL_OAI21X2 U5188 ( .A(n4863), .B(n5153), .C(n4862), .Z(n4867) );
HS65_LH_NAND2X7 U5189 ( .A(n5643), .B(n5266), .Z(n5267) );
HS65_LL_AOI211X3 U5190 ( .A(n3852), .B(n5285), .C(n3851), .D(n3850), .Z(
n8476) );
HS65_LH_NAND2X7 U5191 ( .A(n7631), .B(n4057), .Z(n4098) );
HS65_LL_NAND2X2 U5192 ( .A(n5157), .B(n5156), .Z(n5158) );
HS65_LLS_XNOR2X3 U5193 ( .A(n4253), .B(n4252), .Z(n4280) );
HS65_LL_NOR2AX3 U5194 ( .A(n4487), .B(n4486), .Z(n8466) );
HS65_LL_NAND2AX4 U5195 ( .A(n4139), .B(n4138), .Z(n4140) );
HS65_LHS_XNOR2X6 U5197 ( .A(n4092), .B(n4091), .Z(n4093) );
HS65_LLS_XNOR2X3 U5198 ( .A(n3565), .B(n3564), .Z(n3566) );
HS65_LH_IVX9 U5199 ( .A(n4312), .Z(n4313) );
HS65_LHS_XNOR2X6 U5201 ( .A(n5199), .B(n5198), .Z(n5222) );
HS65_LHS_XNOR2X6 U5202 ( .A(n4326), .B(n4325), .Z(n4327) );
HS65_LH_NAND2X7 U5203 ( .A(n7631), .B(n3902), .Z(n3948) );
HS65_LL_NOR3X1 U5204 ( .A(n3795), .B(n3794), .C(n3793), .Z(n3796) );
HS65_LH_NOR2AX3 U5205 ( .A(n3931), .B(n3930), .Z(n3946) );
HS65_LH_AOI22X6 U5206 ( .A(n9100), .B(n9368), .C(n9187), .D(n8852), .Z(n8297) );
HS65_LH_OAI12X3 U5209 ( .A(n5611), .B(n2859), .C(n5609), .Z(n5612) );
HS65_LH_CNIVX3 U5210 ( .A(n8463), .Z(n4791) );
HS65_LL_NOR2X2 U5211 ( .A(n5634), .B(n5633), .Z(n5635) );
HS65_LL_NAND3X2 U5213 ( .A(n3886), .B(n3885), .C(n3884), .Z(n3887) );
HS65_LL_NOR3X1 U5214 ( .A(n3717), .B(n3716), .C(n3715), .Z(n3729) );
HS65_LL_NOR3X1 U5215 ( .A(n3542), .B(n3541), .C(n3540), .Z(n3569) );
HS65_LL_NAND4ABX3 U5216 ( .A(n4653), .B(n4652), .C(n4651), .D(n4650), .Z(
n8467) );
HS65_LH_NOR3X4 U5217 ( .A(n4898), .B(n4897), .C(n4896), .Z(n4899) );
HS65_LL_OAI12X3 U5218 ( .A(n3992), .B(n4929), .C(n3991), .Z(n3993) );
HS65_LH_IVX9 U5219 ( .A(n4536), .Z(n7838) );
HS65_LL_NOR3X1 U5220 ( .A(n4076), .B(n4075), .C(n4074), .Z(n4096) );
HS65_LL_IVX2 U5222 ( .A(n4781), .Z(n5119) );
HS65_LL_NOR3X1 U5223 ( .A(n3989), .B(n3988), .C(n3987), .Z(n3997) );
HS65_LL_OAI12X2 U5224 ( .A(n4929), .B(n3941), .C(n3940), .Z(n3942) );
HS65_LH_NOR2AX3 U5225 ( .A(n4054), .B(n4053), .Z(n4055) );
HS65_LL_NOR2X2 U5226 ( .A(n4137), .B(n4136), .Z(n4138) );
HS65_LH_NAND2X4 U5229 ( .A(n3804), .B(n5210), .Z(n3806) );
HS65_LL_NAND2X2 U5231 ( .A(n5643), .B(n4636), .Z(n4651) );
HS65_LH_NAND2X2 U5233 ( .A(n5615), .B(n4535), .Z(n4278) );
HS65_LL_NOR3X1 U5234 ( .A(n3978), .B(n3977), .C(n3976), .Z(n3998) );
HS65_LH_NAND2X5 U5235 ( .A(n5615), .B(n5614), .Z(n5626) );
HS65_LH_NAND2AX7 U5236 ( .A(n4880), .B(n4879), .Z(n4881) );
HS65_LH_OAI21X3 U5238 ( .A(n3539), .B(n5646), .C(n3538), .Z(n3540) );
HS65_LH_OAI21X3 U5239 ( .A(n3713), .B(n4607), .C(n3712), .Z(n3716) );
HS65_LL_NOR3X1 U5240 ( .A(n5150), .B(n5149), .C(n5148), .Z(n5151) );
HS65_LH_NAND2X7 U5242 ( .A(n7631), .B(n4908), .Z(n4909) );
HS65_LH_NOR2X3 U5243 ( .A(n5152), .B(n4895), .Z(n4896) );
HS65_LH_NAND2X4 U5244 ( .A(n4424), .B(n2867), .Z(n4377) );
HS65_LH_NAND2X4 U5245 ( .A(n4919), .B(n4916), .Z(n4921) );
HS65_LH_NAND2X7 U5248 ( .A(n7631), .B(n3854), .Z(n3890) );
HS65_LH_NOR3X4 U5249 ( .A(n4760), .B(n4759), .C(n4758), .Z(n4779) );
HS65_LH_NAND2X5 U5250 ( .A(n4555), .B(n4554), .Z(n4556) );
HS65_LH_NAND2X5 U5254 ( .A(n5632), .B(n5631), .Z(n5634) );
HS65_LH_OAI12X3 U5255 ( .A(n5241), .B(n4391), .C(n4390), .Z(n4403) );
HS65_LH_AOI12X2 U5257 ( .A(n4930), .B(n4928), .C(n4927), .Z(n4933) );
HS65_LH_NOR2X5 U5258 ( .A(n5621), .B(n5226), .Z(n5227) );
HS65_LH_NOR2X5 U5260 ( .A(n3427), .B(n5204), .Z(n5205) );
HS65_LL_NOR3X1 U5261 ( .A(n4458), .B(n5321), .C(n4457), .Z(n4475) );
HS65_LH_AOI21X2 U5263 ( .A(n3939), .B(n4928), .C(n3938), .Z(n3940) );
HS65_LH_NAND2X5 U5264 ( .A(n4942), .B(n4164), .Z(n3980) );
HS65_LL_NAND3X2 U5266 ( .A(n4265), .B(n4262), .C(n4260), .Z(n4535) );
HS65_LH_NAND2X4 U5267 ( .A(n4417), .B(n5631), .Z(n4411) );
HS65_LH_OAI12X3 U5268 ( .A(n4670), .B(n4669), .C(n4668), .Z(n4695) );
HS65_LH_NAND2X4 U5269 ( .A(n3751), .B(n5194), .Z(n3753) );
HS65_LH_OAI21X3 U5272 ( .A(n5646), .B(n4889), .C(n4888), .Z(n4898) );
HS65_LH_NOR2X3 U5273 ( .A(n5621), .B(n5240), .Z(n3675) );
HS65_LH_OAI22X3 U5274 ( .A(n4954), .B(n4579), .C(n5146), .D(n3913), .Z(n4603) );
HS65_LH_IVX7 U5276 ( .A(n4232), .Z(n4233) );
HS65_LH_NAND2X7 U5277 ( .A(n2733), .B(\u_DataPath/toPC2_i [31]), .Z(n8234)
);
HS65_LH_NOR3X3 U5279 ( .A(n4795), .B(n5249), .C(n4163), .Z(n3537) );
HS65_LH_NOR2X5 U5280 ( .A(n4293), .B(n4317), .Z(n4295) );
HS65_LH_OAI21X3 U5281 ( .A(n4767), .B(n5656), .C(n4529), .Z(n4530) );
HS65_LH_AOI22X3 U5282 ( .A(n5229), .B(n4515), .C(n4951), .D(n4560), .Z(n4152) );
HS65_LH_IVX7 U5283 ( .A(n4839), .Z(n5200) );
HS65_LL_NAND2X2 U5284 ( .A(n4385), .B(n4384), .Z(n4386) );
HS65_LH_NAND2X4 U5285 ( .A(n4887), .B(n4148), .Z(n3965) );
HS65_LH_NAND2X4 U5287 ( .A(n5131), .B(n4560), .Z(n3961) );
HS65_LH_NAND3X5 U5288 ( .A(n4031), .B(n4030), .C(n4029), .Z(n4032) );
HS65_LH_NAND2X4 U5289 ( .A(n5661), .B(n4389), .Z(n4347) );
HS65_LH_AOI21X2 U5290 ( .A(n5618), .B(n5658), .C(n3973), .Z(n3974) );
HS65_LH_NAND3X5 U5291 ( .A(n5566), .B(n4723), .C(n4722), .Z(n4732) );
HS65_LH_OAI12X3 U5294 ( .A(n4307), .B(n4332), .C(n4306), .Z(n4308) );
HS65_LH_NOR2X3 U5295 ( .A(n5621), .B(n4609), .Z(n3717) );
HS65_LH_NAND3X5 U5296 ( .A(n3866), .B(n3865), .C(n3864), .Z(n3883) );
HS65_LH_OAI21X3 U5297 ( .A(n5182), .B(n4117), .C(n3601), .Z(n3606) );
HS65_LH_AOI12X2 U5298 ( .A(n4417), .B(n5630), .C(n4409), .Z(n4410) );
HS65_LL_NAND3X3 U5299 ( .A(n3491), .B(n4625), .C(n4632), .Z(n3492) );
HS65_LH_OAI12X3 U5300 ( .A(n5646), .B(n4353), .C(n4352), .Z(n4354) );
HS65_LH_NAND2X4 U5301 ( .A(n5661), .B(n5243), .Z(n3647) );
HS65_LH_IVX9 U5305 ( .A(n3923), .Z(n5243) );
HS65_LL_AOI12X2 U5306 ( .A(n4806), .B(n5672), .C(n4437), .Z(n4438) );
HS65_LH_NOR3X4 U5308 ( .A(n5466), .B(n5465), .C(n5464), .Z(n5495) );
HS65_LH_IVX4 U5309 ( .A(n4262), .Z(n4263) );
HS65_LH_NAND2X7 U5310 ( .A(n4038), .B(n4041), .Z(n3994) );
HS65_LL_NAND2X2 U5311 ( .A(n4016), .B(n3362), .Z(n3363) );
HS65_LH_NAND2X5 U5312 ( .A(n4516), .B(n4344), .Z(n4385) );
HS65_LH_NAND3X3 U5313 ( .A(n5335), .B(n5313), .C(n5402), .Z(n4673) );
HS65_LH_IVX7 U5314 ( .A(n4319), .Z(n3504) );
HS65_LH_IVX9 U5315 ( .A(n4435), .Z(n5206) );
HS65_LH_NOR3X3 U5317 ( .A(n5571), .B(n5471), .C(n5470), .Z(n5472) );
HS65_LH_IVX4 U5319 ( .A(n4868), .Z(n4803) );
HS65_LH_NAND2AX7 U5320 ( .A(n3473), .B(n3497), .Z(n4427) );
HS65_LH_NOR2X5 U5321 ( .A(n4954), .B(n4468), .Z(n3857) );
HS65_LH_OAI12X3 U5322 ( .A(n9352), .B(n3424), .C(n5423), .Z(n3429) );
HS65_LH_IVX9 U5324 ( .A(n4806), .Z(n4163) );
HS65_LL_AOI21X2 U5326 ( .A(n3804), .B(n5211), .C(n3803), .Z(n3805) );
HS65_LH_NOR2X5 U5327 ( .A(n5287), .B(n5342), .Z(n5352) );
HS65_LH_NAND2X4 U5328 ( .A(n4942), .B(n4344), .Z(n4058) );
HS65_LH_NAND2X5 U5329 ( .A(n5131), .B(n4132), .Z(n4133) );
HS65_LL_NAND2X2 U5330 ( .A(n4040), .B(n3480), .Z(n3475) );
HS65_LH_NAND2X7 U5331 ( .A(n4303), .B(n4304), .Z(n4232) );
HS65_LH_NAND2X7 U5332 ( .A(n4259), .B(n4258), .Z(n4950) );
HS65_LH_OAI21X3 U5333 ( .A(n4939), .B(n4894), .C(n4893), .Z(n4897) );
HS65_LH_NAND2AX7 U5334 ( .A(n4217), .B(n4316), .Z(n4291) );
HS65_LH_NAND2X4 U5335 ( .A(n4528), .B(n4344), .Z(n4346) );
HS65_LH_NOR2X5 U5336 ( .A(n5176), .B(n4558), .Z(n4559) );
HS65_LH_OAI12X3 U5337 ( .A(n4078), .B(n4077), .C(n4836), .Z(n4079) );
HS65_LL_IVX2 U5339 ( .A(n4101), .Z(n4645) );
HS65_LH_NOR2X6 U5341 ( .A(n4077), .B(n4078), .Z(n4391) );
HS65_LH_OAI12X3 U5343 ( .A(n3800), .B(n3686), .C(n3802), .Z(n3687) );
HS65_LH_NOR3X4 U5345 ( .A(n5186), .B(n5185), .C(n5184), .Z(n5187) );
HS65_LH_NOR3X4 U5346 ( .A(n4747), .B(n4746), .C(n4745), .Z(n4780) );
HS65_LH_AOI22X3 U5347 ( .A(n5234), .B(n4592), .C(n4951), .D(n4617), .Z(n4601) );
HS65_LH_NAND2X7 U5349 ( .A(n4318), .B(n3471), .Z(n3509) );
HS65_LH_IVX9 U5350 ( .A(n3872), .Z(n5177) );
HS65_LH_OAI12X3 U5351 ( .A(n4913), .B(n3895), .C(n4915), .Z(n3896) );
HS65_LH_IVX9 U5352 ( .A(n3555), .Z(n4873) );
HS65_LH_AOI21X2 U5354 ( .A(n4490), .B(n5672), .C(n5649), .Z(n3655) );
HS65_LH_OAI211X5 U5356 ( .A(n4671), .B(n4582), .C(n4129), .D(n4128), .Z(
n4868) );
HS65_LL_NAND3X3 U5357 ( .A(n3441), .B(n3440), .C(n4340), .Z(n3872) );
HS65_LH_NAND2X5 U5358 ( .A(n3910), .B(n3909), .Z(n3911) );
HS65_LH_NOR2X3 U5359 ( .A(n5603), .B(n3734), .Z(n3737) );
HS65_LH_OAI12X2 U5360 ( .A(n5603), .B(n3735), .C(n5605), .Z(n3736) );
HS65_LH_NOR3X4 U5361 ( .A(n3596), .B(n3908), .C(n3595), .Z(n4355) );
HS65_LH_NAND2X5 U5362 ( .A(n5229), .B(n5170), .Z(n5171) );
HS65_LH_NOR2X3 U5364 ( .A(n4314), .B(n4318), .Z(n4217) );
HS65_LH_OAI12X3 U5367 ( .A(n4596), .B(n2897), .C(n4595), .Z(n4597) );
HS65_LH_NOR2X6 U5368 ( .A(n4064), .B(n4063), .Z(n4113) );
HS65_LH_NOR2X6 U5369 ( .A(n3460), .B(n3459), .Z(n4849) );
HS65_LH_NAND2X7 U5371 ( .A(n2733), .B(\u_DataPath/toPC2_i [29]), .Z(n8238)
);
HS65_LL_NAND3X3 U5373 ( .A(n3870), .B(n3959), .C(n3790), .Z(n5660) );
HS65_LH_NAND3X5 U5374 ( .A(n4753), .B(n4752), .C(n4751), .Z(n4759) );
HS65_LH_NAND3X3 U5375 ( .A(n4763), .B(n4762), .C(n4761), .Z(n4777) );
HS65_LH_NAND3X5 U5376 ( .A(n5188), .B(n4767), .C(n4766), .Z(n4776) );
HS65_LH_OAI21X3 U5377 ( .A(n2843), .B(n5129), .C(n4590), .Z(n4077) );
HS65_LH_NAND2X7 U5378 ( .A(n4316), .B(n4315), .Z(n4326) );
HS65_LH_NOR2X5 U5379 ( .A(n5399), .B(n5298), .Z(n5402) );
HS65_LH_NOR2X5 U5380 ( .A(n4320), .B(n4314), .Z(n4290) );
HS65_LL_AOI21X2 U5381 ( .A(n4538), .B(n3318), .C(n3317), .Z(n4101) );
HS65_LH_OAI12X3 U5382 ( .A(n4924), .B(n3937), .C(n4926), .Z(n3938) );
HS65_LL_NOR2X2 U5383 ( .A(n4034), .B(n3990), .Z(n3480) );
HS65_LH_NAND2X4 U5384 ( .A(n5229), .B(n4356), .Z(n3604) );
HS65_LL_OAI21X2 U5385 ( .A(n3376), .B(n5179), .C(n5178), .Z(n4437) );
HS65_LH_IVX7 U5386 ( .A(n4800), .Z(n4132) );
HS65_LH_NAND2X5 U5387 ( .A(n3934), .B(n3933), .Z(n3943) );
HS65_LH_NOR2X6 U5388 ( .A(n4011), .B(n3949), .Z(n3362) );
HS65_LL_IVX4 U5389 ( .A(n3949), .Z(n4017) );
HS65_LH_CBI4I1X5 U5390 ( .A(n5499), .B(n5572), .C(n5503), .D(n5569), .Z(
n5488) );
HS65_LL_NAND3X3 U5392 ( .A(n3985), .B(n3871), .C(n3760), .Z(n5617) );
HS65_LL_NOR2X3 U5394 ( .A(n3415), .B(n4134), .Z(n4806) );
HS65_LL_NAND2X4 U5396 ( .A(n3503), .B(n3804), .Z(n4317) );
HS65_LH_IVX7 U5397 ( .A(n3920), .Z(n3671) );
HS65_LH_IVX9 U5398 ( .A(n5257), .Z(n3473) );
HS65_LH_NAND2X5 U5399 ( .A(n5103), .B(n5400), .Z(n5542) );
HS65_LH_NOR3X4 U5400 ( .A(n4465), .B(n4464), .C(n4463), .Z(n5135) );
HS65_LH_NOR2X6 U5401 ( .A(n3646), .B(n3645), .Z(n3923) );
HS65_LH_NOR2X5 U5402 ( .A(n4690), .B(n4702), .Z(n4708) );
HS65_LH_NOR2X5 U5405 ( .A(n4796), .B(n4582), .Z(n3669) );
HS65_LH_AOI211X3 U5406 ( .A(n5234), .B(n4750), .C(n4027), .D(n3826), .Z(
n3828) );
HS65_LL_NOR2X2 U5407 ( .A(n3932), .B(n4924), .Z(n3478) );
HS65_LH_NAND2X7 U5408 ( .A(n2892), .B(n5295), .Z(n4864) );
HS65_LH_NAND2X5 U5409 ( .A(n4904), .B(n4903), .Z(n4907) );
HS65_LH_NAND3X3 U5410 ( .A(n5502), .B(n5442), .C(n5582), .Z(n4977) );
HS65_LH_NAND3X3 U5412 ( .A(n4769), .B(n5141), .C(n4768), .Z(n4770) );
HS65_LH_NAND2X7 U5413 ( .A(n3474), .B(n3359), .Z(n5400) );
HS65_LH_NOR2X6 U5414 ( .A(\lte_x_59/B[28] ), .B(n3129), .Z(n4333) );
HS65_LH_NAND2X4 U5415 ( .A(n5292), .B(n5356), .Z(n4690) );
HS65_LH_IVX7 U5417 ( .A(n3820), .Z(n3822) );
HS65_LH_NAND2X7 U5419 ( .A(\lte_x_59/B[28] ), .B(n5423), .Z(n4318) );
HS65_LH_OA12X9 U5420 ( .A(n5126), .B(n4823), .C(n4824), .Z(n2897) );
HS65_LH_AOI12X2 U5421 ( .A(n5261), .B(n5260), .C(n5259), .Z(n5262) );
HS65_LH_NAND2X7 U5423 ( .A(n4229), .B(n5569), .Z(n4242) );
HS65_LH_NAND2X4 U5424 ( .A(\lte_x_59/B[28] ), .B(n4587), .Z(n3649) );
HS65_LH_NAND2X5 U5425 ( .A(n4878), .B(n4877), .Z(n4884) );
HS65_LH_IVX4 U5427 ( .A(n3613), .Z(n3614) );
HS65_LH_IVX4 U5429 ( .A(n4314), .Z(n4315) );
HS65_LH_AOI21X2 U5430 ( .A(n4943), .B(n4942), .C(n4941), .Z(n4944) );
HS65_LH_NOR2X6 U5431 ( .A(n4131), .B(n4130), .Z(n4800) );
HS65_LH_NAND2X5 U5432 ( .A(n4083), .B(n4082), .Z(n4092) );
HS65_LH_IVX7 U5433 ( .A(n5300), .Z(n5103) );
HS65_LH_IVX4 U5434 ( .A(n3572), .Z(n3573) );
HS65_LL_NAND2X2 U5435 ( .A(n5209), .B(n5208), .Z(n5215) );
HS65_LH_IVX7 U5436 ( .A(n4040), .Z(n3991) );
HS65_LL_NOR2X3 U5437 ( .A(n3629), .B(n3747), .Z(n3383) );
HS65_LH_IVX4 U5439 ( .A(n3594), .Z(n3596) );
HS65_LH_OAI12X3 U5440 ( .A(n5362), .B(n5364), .C(n5290), .Z(n5585) );
HS65_LH_OAI22X4 U5441 ( .A(n5130), .B(n3756), .C(n4660), .D(n5129), .Z(n3772) );
HS65_LH_IVX7 U5442 ( .A(n4049), .Z(n3267) );
HS65_LH_IVX9 U5444 ( .A(n4117), .Z(n4892) );
HS65_LH_NAND2X4 U5445 ( .A(n5193), .B(n5192), .Z(n5199) );
HS65_LH_NAND2X5 U5447 ( .A(n4418), .B(n4417), .Z(n4422) );
HS65_LH_NAND2X7 U5448 ( .A(n3802), .B(n3801), .Z(n3808) );
HS65_LH_NAND2X4 U5449 ( .A(n4425), .B(n4424), .Z(n4429) );
HS65_LH_OAI12X3 U5451 ( .A(n3893), .B(n5530), .C(n5506), .Z(n5473) );
HS65_LH_NAND2X4 U5455 ( .A(n5192), .B(n5290), .Z(n5366) );
HS65_LHS_XOR2X6 U5456 ( .A(n5126), .B(n4825), .Z(n4826) );
HS65_LH_NOR2X3 U5457 ( .A(n5004), .B(n2857), .Z(n3954) );
HS65_LH_NAND2X4 U5458 ( .A(\lte_x_59/B[14] ), .B(n2864), .Z(n4022) );
HS65_LH_CNIVX3 U5459 ( .A(n3731), .Z(n3732) );
HS65_LH_OAI22X3 U5461 ( .A(n4671), .B(n2856), .C(n3756), .D(n2843), .Z(n4023) );
HS65_LH_NAND2X5 U5462 ( .A(\sub_x_53/A[23] ), .B(n4588), .Z(n3718) );
HS65_LL_OAI22X3 U5464 ( .A(n3756), .B(n4726), .C(n2840), .D(n4583), .Z(n4943) );
HS65_LH_NAND2X2 U5465 ( .A(\lte_x_59/B[8] ), .B(n2864), .Z(n3674) );
HS65_LH_NAND2X5 U5468 ( .A(n2842), .B(n4588), .Z(n4060) );
HS65_LL_NOR2X2 U5470 ( .A(n7834), .B(n2840), .Z(n3420) );
HS65_LH_NOR2X6 U5471 ( .A(n5320), .B(n5129), .Z(n4798) );
HS65_LH_IVX9 U5474 ( .A(n4887), .Z(n5146) );
HS65_LH_OAI21X3 U5475 ( .A(n3365), .B(n5179), .C(n3825), .Z(n3826) );
HS65_LH_NOR2X3 U5476 ( .A(n4675), .B(n2856), .Z(n3830) );
HS65_LH_NAND2X4 U5478 ( .A(n4594), .B(n4593), .Z(n4598) );
HS65_LH_NOR2X3 U5479 ( .A(n2840), .B(n4193), .Z(n4194) );
HS65_LH_NAND2X7 U5480 ( .A(\lte_x_59/B[24] ), .B(n4551), .Z(n3837) );
HS65_LH_NAND2X7 U5481 ( .A(\sub_x_53/A[25] ), .B(n2845), .Z(n3836) );
HS65_LH_IVX7 U5482 ( .A(n4418), .Z(n4409) );
HS65_LH_NOR2X6 U5483 ( .A(n4984), .B(n5129), .Z(n3907) );
HS65_LH_IVX4 U5484 ( .A(n5419), .Z(n4417) );
HS65_LH_NAND2X4 U5486 ( .A(\lte_x_59/B[16] ), .B(n2864), .Z(n4061) );
HS65_LH_NAND2X5 U5487 ( .A(\lte_x_59/B[21] ), .B(n4587), .Z(n3821) );
HS65_LH_NAND2X5 U5488 ( .A(n4595), .B(n4561), .Z(n4562) );
HS65_LH_IVX9 U5489 ( .A(n4951), .Z(n5176) );
HS65_LH_IVX9 U5490 ( .A(n4341), .Z(n4490) );
HS65_LH_NAND2X7 U5491 ( .A(\sub_x_53/A[0] ), .B(n4551), .Z(n5183) );
HS65_LH_OAI21X3 U5492 ( .A(n2871), .B(n5179), .C(n4890), .Z(n4891) );
HS65_LH_IVX4 U5493 ( .A(n4757), .Z(n4033) );
HS65_LH_IVX9 U5495 ( .A(n3846), .Z(n4086) );
HS65_LH_IVX7 U5500 ( .A(n5272), .Z(n5273) );
HS65_LH_NAND2X5 U5503 ( .A(\sub_x_53/A[29] ), .B(n4588), .Z(n3545) );
HS65_LH_IVX7 U5504 ( .A(n5258), .Z(n5259) );
HS65_LH_NAND2X7 U5505 ( .A(n7866), .B(n9065), .Z(
\u_DataPath/jump_address_i [16]) );
HS65_LH_NOR2X5 U5506 ( .A(n5656), .B(n5655), .Z(n5657) );
HS65_LH_NAND2X5 U5507 ( .A(n4206), .B(n4205), .Z(n4226) );
HS65_LH_NAND2X4 U5508 ( .A(n5313), .B(n5544), .Z(n5325) );
HS65_LH_NAND2X5 U5511 ( .A(\sub_x_53/A[25] ), .B(n5425), .Z(n3574) );
HS65_LH_IVX9 U5512 ( .A(n4143), .Z(n3354) );
HS65_LH_NAND2X7 U5513 ( .A(n2733), .B(\u_DataPath/toPC2_i [27]), .Z(n8240)
);
HS65_LH_NAND2X4 U5515 ( .A(n2840), .B(n7623), .Z(n5449) );
HS65_LH_NAND2X7 U5517 ( .A(n2860), .B(n4967), .Z(n5290) );
HS65_LH_OAI12X6 U5518 ( .A(n4719), .B(n4718), .C(\sub_x_53/A[25] ), .Z(n5502) );
HS65_LH_NOR2X5 U5519 ( .A(n4981), .B(n5180), .Z(n5500) );
HS65_LH_IVX9 U5522 ( .A(n4905), .Z(n3231) );
HS65_LH_NAND2X5 U5524 ( .A(\sub_x_53/A[29] ), .B(n5422), .Z(n4316) );
HS65_LH_NOR2X6 U5526 ( .A(\sub_x_53/A[29] ), .B(n5422), .Z(n4314) );
HS65_LH_NAND2X4 U5528 ( .A(n5327), .B(n5544), .Z(n4666) );
HS65_LH_NOR2X6 U5530 ( .A(\sub_x_53/A[30] ), .B(n2873), .Z(n4230) );
HS65_LH_OAI22X4 U5532 ( .A(n7917), .B(n8404), .C(n7915), .D(n8403), .Z(
\u_DataPath/data_read_ex_1_i [14]) );
HS65_LH_OAI22X4 U5533 ( .A(n7917), .B(n8343), .C(n7915), .D(n8342), .Z(
\u_DataPath/data_read_ex_1_i [13]) );
HS65_LH_OAI22X4 U5534 ( .A(n7902), .B(n8293), .C(n7899), .D(n8183), .Z(
\u_DataPath/data_read_ex_2_i [12]) );
HS65_LH_OAI22X4 U5535 ( .A(n7917), .B(n8362), .C(n7915), .D(n8361), .Z(
\u_DataPath/data_read_ex_1_i [23]) );
HS65_LH_OAI22X4 U5536 ( .A(n7902), .B(n8415), .C(n7899), .D(n8171), .Z(
\u_DataPath/data_read_ex_2_i [5]) );
HS65_LH_OAI22X4 U5537 ( .A(n7917), .B(n8372), .C(n7915), .D(n8371), .Z(
\u_DataPath/data_read_ex_1_i [24]) );
HS65_LH_OAI22X4 U5538 ( .A(n7917), .B(n8353), .C(n7915), .D(n8352), .Z(
\u_DataPath/data_read_ex_1_i [22]) );
HS65_LH_OAI22X4 U5539 ( .A(n7902), .B(n8304), .C(n7899), .D(n8180), .Z(
\u_DataPath/data_read_ex_2_i [7]) );
HS65_LH_OAI22X4 U5540 ( .A(n7902), .B(n8457), .C(n7901), .D(n8386), .Z(
\u_DataPath/data_read_ex_2_i [18]) );
HS65_LH_OAI22X4 U5541 ( .A(n7902), .B(n8326), .C(n7900), .D(n8322), .Z(
\u_DataPath/data_read_ex_2_i [19]) );
HS65_LH_OAI22X4 U5542 ( .A(n7917), .B(n8378), .C(n7915), .D(n8377), .Z(
\u_DataPath/data_read_ex_1_i [27]) );
HS65_LH_OAI22X4 U5543 ( .A(n7902), .B(n8168), .C(n7899), .D(n8156), .Z(
\u_DataPath/data_read_ex_2_i [1]) );
HS65_LH_OAI22X4 U5544 ( .A(n7902), .B(n8362), .C(n7899), .D(n8178), .Z(
\u_DataPath/data_read_ex_2_i [23]) );
HS65_LH_OAI22X4 U5545 ( .A(n7917), .B(n8358), .C(n7915), .D(n8357), .Z(
\u_DataPath/data_read_ex_1_i [16]) );
HS65_LH_OAI22X4 U5546 ( .A(n7902), .B(n8408), .C(n7899), .D(n8175), .Z(
\u_DataPath/data_read_ex_2_i [17]) );
HS65_LH_OAI22X4 U5547 ( .A(n7917), .B(n8367), .C(n7915), .D(n8366), .Z(
\u_DataPath/data_read_ex_1_i [21]) );
HS65_LH_OAI22X4 U5548 ( .A(n7902), .B(n8321), .C(n7900), .D(n8315), .Z(
\u_DataPath/data_read_ex_2_i [26]) );
HS65_LH_OAI22X4 U5549 ( .A(n7902), .B(n8314), .C(n7899), .D(n8310), .Z(
\u_DataPath/data_read_ex_2_i [6]) );
HS65_LH_OAI22X4 U5550 ( .A(n7917), .B(n8397), .C(n7915), .D(n8396), .Z(
\u_DataPath/data_read_ex_1_i [30]) );
HS65_LH_OAI22X4 U5551 ( .A(n7902), .B(n8330), .C(n7900), .D(n8327), .Z(
\u_DataPath/data_read_ex_2_i [25]) );
HS65_LH_OAI22X4 U5552 ( .A(n7902), .B(n8422), .C(n7899), .D(n8158), .Z(
\u_DataPath/data_read_ex_2_i [31]) );
HS65_LH_OAI22X4 U5553 ( .A(n7917), .B(n8348), .C(n7915), .D(n8347), .Z(
\u_DataPath/data_read_ex_1_i [11]) );
HS65_LH_OAI22X4 U5554 ( .A(n9272), .B(n9186), .C(n9119), .D(n8753), .Z(
\u_DataPath/data_read_ex_2_i [10]) );
HS65_LH_OAI22X4 U5555 ( .A(n7902), .B(n8275), .C(n7899), .D(n8261), .Z(
\u_DataPath/data_read_ex_2_i [8]) );
HS65_LH_NOR2X5 U5556 ( .A(n4575), .B(n4570), .Z(n3318) );
HS65_LH_IVX4 U5557 ( .A(n4477), .Z(n4109) );
HS65_LH_NAND2X7 U5558 ( .A(\lte_x_59/B[14] ), .B(n3366), .Z(n4915) );
HS65_LH_NOR2X6 U5559 ( .A(\sub_x_53/A[23] ), .B(n5417), .Z(n3698) );
HS65_LL_IVX7 U5560 ( .A(n3272), .Z(\lte_x_59/B[15] ) );
HS65_LL_NOR2X5 U5561 ( .A(\lte_x_59/B[16] ), .B(n4985), .Z(n5530) );
HS65_LH_NOR2X6 U5562 ( .A(\lte_x_59/B[22] ), .B(n5654), .Z(n5603) );
HS65_LH_NAND2X5 U5563 ( .A(\sub_x_53/A[23] ), .B(n5417), .Z(n3700) );
HS65_LH_NAND2X7 U5564 ( .A(n2842), .B(n5376), .Z(n4050) );
HS65_LH_NOR2X6 U5565 ( .A(n3365), .B(n3521), .Z(n3814) );
HS65_LH_NOR2X3 U5567 ( .A(n5320), .B(n3756), .Z(n3639) );
HS65_LH_NAND2X7 U5568 ( .A(\lte_x_59/B[21] ), .B(n5418), .Z(n4373) );
HS65_LH_NAND2X7 U5569 ( .A(\lte_x_59/B[22] ), .B(n5654), .Z(n5605) );
HS65_LH_NAND2X7 U5571 ( .A(\lte_x_59/B[6] ), .B(n2865), .Z(n4641) );
HS65_LH_NAND2X7 U5572 ( .A(\sub_x_53/A[20] ), .B(n3376), .Z(n4418) );
HS65_LH_NOR2X6 U5573 ( .A(\sub_x_53/A[23] ), .B(n4967), .Z(n3731) );
HS65_LH_NAND2X7 U5574 ( .A(\sub_x_53/A[23] ), .B(n4967), .Z(n3733) );
HS65_LH_NAND2X7 U5575 ( .A(n2858), .B(n5398), .Z(n4013) );
HS65_LH_NAND2X5 U5576 ( .A(n5373), .B(n4682), .Z(n5313) );
HS65_LH_IVX9 U5577 ( .A(n3788), .Z(n5615) );
HS65_LH_NAND2X7 U5579 ( .A(n2853), .B(n5567), .Z(n3802) );
HS65_LH_IVX9 U5580 ( .A(\lte_x_59/B[16] ), .Z(n5022) );
HS65_LH_NOR2X6 U5582 ( .A(\lte_x_59/B[9] ), .B(n5053), .Z(n4876) );
HS65_LH_NAND2X7 U5583 ( .A(\lte_x_59/B[14] ), .B(n5061), .Z(n4926) );
HS65_LH_NAND2X7 U5586 ( .A(n2842), .B(n4674), .Z(n4083) );
HS65_LH_NAND2X7 U5587 ( .A(\lte_x_59/B[6] ), .B(n4147), .Z(n4628) );
HS65_LH_NOR2X6 U5588 ( .A(n4674), .B(n2842), .Z(n4081) );
HS65_LH_NAND2X7 U5589 ( .A(n3521), .B(n5048), .Z(n4084) );
HS65_LHS_XNOR2X3 U5590 ( .A(n5909), .B(n5908), .Z(\u_DataPath/toPC2_i [27])
);
HS65_LL_NOR2X3 U5592 ( .A(\lte_x_59/B[14] ), .B(n5061), .Z(n4924) );
HS65_LH_NOR2X3 U5593 ( .A(n4726), .B(n4795), .Z(n3648) );
HS65_LH_NAND2X7 U5594 ( .A(\lte_x_59/B[24] ), .B(n3382), .Z(n5193) );
HS65_LHS_XNOR2X6 U5595 ( .A(n7308), .B(n7307), .Z(
\u_DataPath/u_execute/link_value_i [28]) );
HS65_LH_NOR2X6 U5596 ( .A(\lte_x_59/B[24] ), .B(n5180), .Z(n3616) );
HS65_LH_NOR2X6 U5597 ( .A(n3521), .B(n5048), .Z(n3846) );
HS65_LH_NAND2X7 U5598 ( .A(n3521), .B(n3365), .Z(n5405) );
HS65_LH_NOR2X6 U5599 ( .A(n2858), .B(n4683), .Z(n4034) );
HS65_LH_OA12X9 U5600 ( .A(n4595), .B(n3488), .C(n4594), .Z(n3489) );
HS65_LH_NAND2X7 U5601 ( .A(n2858), .B(n4683), .Z(n4036) );
HS65_LH_NAND2X5 U5602 ( .A(n4431), .B(n4516), .Z(n5182) );
HS65_LH_IVX7 U5603 ( .A(n3488), .Z(n4593) );
HS65_LH_NAND2X7 U5604 ( .A(\lte_x_59/B[9] ), .B(n5053), .Z(n4878) );
HS65_LH_NOR2X5 U5605 ( .A(n4581), .B(n3788), .Z(n4528) );
HS65_LH_IVX9 U5606 ( .A(n8242), .Z(\u_DataPath/branch_target_i [25]) );
HS65_LH_NOR2X6 U5607 ( .A(n4105), .B(n4108), .Z(n4625) );
HS65_LHS_XOR2X3 U5608 ( .A(n5752), .B(n5751), .Z(\u_DataPath/toPC2_i [26])
);
HS65_LH_IVX9 U5609 ( .A(\lte_x_59/B[1] ), .Z(n4811) );
HS65_LH_NAND2X7 U5611 ( .A(\lte_x_59/B[4] ), .B(n3352), .Z(n4481) );
HS65_LH_IVX9 U5612 ( .A(n5418), .Z(n3377) );
HS65_LH_NOR2X6 U5613 ( .A(\lte_x_59/B[4] ), .B(n3352), .Z(n4100) );
HS65_LH_IVX9 U5615 ( .A(n5001), .Z(n2870) );
HS65_LL_NOR2X5 U5616 ( .A(n2925), .B(n3271), .Z(n3272) );
HS65_LH_IVX9 U5618 ( .A(n5061), .Z(n3366) );
HS65_LH_NAND2AX7 U5619 ( .A(n4534), .B(n3426), .Z(n3427) );
HS65_LL_IVX4 U5620 ( .A(n5152), .Z(n4512) );
HS65_LL_NOR2X2 U5621 ( .A(\lte_x_59/B[7] ), .B(n5312), .Z(n4637) );
HS65_LL_NOR2X6 U5622 ( .A(n3177), .B(n3176), .Z(\sub_x_53/A[20] ) );
HS65_LH_NAND2X7 U5624 ( .A(n2733), .B(\u_DataPath/toPC2_i [25]), .Z(n8242)
);
HS65_LH_NAND2X5 U5626 ( .A(\lte_x_59/B[8] ), .B(n5373), .Z(n4882) );
HS65_LL_OR2X18 U5627 ( .A(n3399), .B(n5136), .Z(n3756) );
HS65_LH_NOR2X6 U5628 ( .A(\lte_x_59/B[4] ), .B(n5032), .Z(n4108) );
HS65_LH_IVX9 U5630 ( .A(n5423), .Z(n3129) );
HS65_LH_NOR2X6 U5631 ( .A(\lte_x_59/B[8] ), .B(n5373), .Z(n4880) );
HS65_LH_NAND2X7 U5633 ( .A(\lte_x_59/B[3] ), .B(n5089), .Z(n4572) );
HS65_LH_IVX9 U5634 ( .A(n4838), .Z(n4508) );
HS65_LH_NAND2X5 U5635 ( .A(\lte_x_59/B[3] ), .B(n5321), .Z(n4594) );
HS65_LH_NAND2X7 U5636 ( .A(n7834), .B(n4550), .Z(n3788) );
HS65_LH_NOR2X6 U5640 ( .A(\lte_x_59/B[7] ), .B(n5030), .Z(n4622) );
HS65_LHS_XNOR2X3 U5641 ( .A(n6116), .B(n6115), .Z(
\u_DataPath/u_execute/resAdd1_i [26]) );
HS65_LH_IVX9 U5642 ( .A(\u_DataPath/u_idexreg/N16 ), .Z(n8101) );
HS65_LH_IVX9 U5643 ( .A(n8253), .Z(\u_DataPath/branch_target_i [14]) );
HS65_LH_IVX9 U5644 ( .A(n8245), .Z(\u_DataPath/branch_target_i [23]) );
HS65_LHS_XNOR2X3 U5645 ( .A(n5917), .B(n5916), .Z(\u_DataPath/toPC2_i [25])
);
HS65_LL_AOI12X4 U5646 ( .A(n5914), .B(n5916), .C(n5739), .Z(n5751) );
HS65_LL_NAND2X5 U5647 ( .A(n3148), .B(n3147), .Z(n4976) );
HS65_LH_IVX9 U5648 ( .A(n9052), .Z(n8104) );
HS65_LL_NAND2X4 U5649 ( .A(n8710), .B(n7780), .Z(n7784) );
HS65_LL_NAND2X5 U5653 ( .A(n3145), .B(n3144), .Z(n5180) );
HS65_LH_OAI22X6 U5654 ( .A(n3264), .B(\u_DataPath/dataOut_exe_i [24]), .C(
n8550), .D(n3409), .Z(n3138) );
HS65_LH_NOR2X5 U5655 ( .A(n8426), .B(n3409), .Z(n3074) );
HS65_LL_NAND2X5 U5656 ( .A(n3183), .B(n3182), .Z(n5418) );
HS65_LL_OAI22X3 U5659 ( .A(n3264), .B(\u_DataPath/dataOut_exe_i [11]), .C(
n8345), .D(n3409), .Z(n3072) );
HS65_LH_OAI22X6 U5661 ( .A(n3264), .B(\u_DataPath/dataOut_exe_i [13]), .C(
n8339), .D(n3409), .Z(n3249) );
HS65_LH_IVX9 U5662 ( .A(n5425), .Z(n4997) );
HS65_LL_IVX9 U5663 ( .A(n5321), .Z(n5089) );
HS65_LH_AOI22X3 U5665 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][2] ), .B(n2887),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[22][2] ), .D(
n7171), .Z(n6563) );
HS65_LH_AO22X9 U5666 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][2] ), .B(n7283),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[20][2] ), .D(
n6635), .Z(n6566) );
HS65_LH_AO22X9 U5667 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][13] ), .B(n7600),
.C(n7599), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][13] ), .Z(n6991)
);
HS65_LH_AO22X9 U5668 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][13] ), .B(n7602),
.C(n7601), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][13] ), .Z(n6990)
);
HS65_LH_AOI22X3 U5669 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][9] ), .B(n7286),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[21][9] ), .D(
n7285), .Z(n7132) );
HS65_LH_AOI22X3 U5670 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][13] ), .B(n6754),
.C(n7594), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][13] ), .Z(n6984)
);
HS65_LH_AOI22X3 U5671 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][31] ), .B(n7286),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[21][31] ), .D(
n7285), .Z(n6876) );
HS65_LH_AOI22X3 U5673 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][5] ), .B(n7265),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[11][5] ), .D(
n2888), .Z(n6931) );
HS65_LH_AOI22X3 U5674 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][13] ), .B(n7603),
.C(n7333), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][13] ), .Z(n6989)
);
HS65_LH_AOI22X3 U5675 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][22] ), .B(n7604),
.C(n7334), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][22] ), .Z(n7008)
);
HS65_LH_AOI22X3 U5676 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][5] ), .B(n6595),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[14][5] ), .D(
n7264), .Z(n6932) );
HS65_LH_AO22X9 U5677 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][4] ), .B(n7600),
.C(n7599), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][4] ), .Z(n7362)
);
HS65_LH_AOI22X3 U5679 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][13] ), .B(n7604),
.C(n7334), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][13] ), .Z(n6988)
);
HS65_LH_AOI22X3 U5680 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][8] ), .B(n2887),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[22][8] ), .D(
n7171), .Z(n6463) );
HS65_LH_AOI22X3 U5681 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][17] ), .B(n7265),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[11][17] ), .D(
n2888), .Z(n6889) );
HS65_LH_AO22X9 U5682 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][25] ), .B(n7600),
.C(n7599), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][25] ), .Z(n7051)
);
HS65_LH_AO22X9 U5683 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][14] ), .B(n7429),
.C(n6952), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][14] ), .Z(n7368)
);
HS65_LH_AO22X9 U5685 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][31] ), .B(n7283),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[20][31] ), .D(
n7282), .Z(n6878) );
HS65_LH_AO22X9 U5686 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][11] ), .B(n7580),
.C(n7579), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][11] ), .Z(n7056)
);
HS65_LH_AO22X9 U5687 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][2] ), .B(n7602),
.C(n7601), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][2] ), .Z(n6970)
);
HS65_LH_AO22X9 U5689 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][24] ), .B(n7602),
.C(n7601), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][24] ), .Z(n7572)
);
HS65_LH_AO22X9 U5690 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][2] ), .B(n7600),
.C(n7599), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][2] ), .Z(n6971)
);
HS65_LH_AO22X9 U5692 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][8] ), .B(n7522),
.C(n7439), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][8] ), .Z(n6778)
);
HS65_LH_AOI22X3 U5693 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][26] ), .B(n2887),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[22][26] ), .D(
n7171), .Z(n6503) );
HS65_LH_AO22X9 U5694 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][9] ), .B(n7293),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[13][9] ), .D(
n7292), .Z(n7137) );
HS65_LH_AOI22X3 U5695 ( .A(n7434), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][6] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][6] ), .D(n7516),
.Z(n7251) );
HS65_LH_AO22X9 U5696 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][17] ), .B(n7283),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[20][17] ), .D(
n7282), .Z(n6898) );
HS65_LH_AO22X9 U5697 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][22] ), .B(n7587),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[12][22] ), .D(
n7586), .Z(n7000) );
HS65_LH_AOI22X3 U5698 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][9] ), .B(n2887),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[22][9] ), .D(
n7171), .Z(n7131) );
HS65_LH_AOI22X3 U5699 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][17] ), .B(n7286),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[21][17] ), .D(
n7285), .Z(n6896) );
HS65_LH_AO22X9 U5700 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][21] ), .B(n7602),
.C(n7601), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][21] ), .Z(n7607)
);
HS65_LH_AO22X9 U5701 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][13] ), .B(n7587),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[12][13] ), .D(
n7586), .Z(n6980) );
HS65_LH_AOI22X3 U5702 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][31] ), .B(n7265),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[11][31] ), .D(
n6363), .Z(n6869) );
HS65_LH_AO22X9 U5703 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][25] ), .B(n7602),
.C(n7601), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][25] ), .Z(n7050)
);
HS65_LH_AOI22X3 U5705 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][17] ), .B(n6595),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[14][17] ), .D(
n7264), .Z(n6890) );
HS65_LH_AO22X9 U5706 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][2] ), .B(n7580),
.C(n7579), .D(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][2] ), .Z(n6953) );
HS65_LH_AO22X9 U5707 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][21] ), .B(n7580),
.C(n7579), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][21] ), .Z(n7581)
);
HS65_LH_AO22X9 U5712 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][13] ), .B(n7580),
.C(n7579), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][13] ), .Z(n6976)
);
HS65_LH_AO22X9 U5714 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][25] ), .B(n7587),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[12][25] ), .D(
n7586), .Z(n7040) );
HS65_LH_AO22X9 U5716 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][16] ), .B(n7580),
.C(n7579), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][16] ), .Z(n7538)
);
HS65_LH_AOI22X3 U5717 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][28] ), .B(n7585),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[1][28] ), .D(
n2889), .Z(n7498) );
HS65_LH_AO22X9 U5718 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][6] ), .B(n6927),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][6] ), .D(n7266), .Z(n6476) );
HS65_LH_AOI22X3 U5719 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][28] ), .B(n6371),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[29][28] ), .D(
n7272), .Z(n6913) );
HS65_LH_AO22X9 U5720 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][15] ), .B(n7429),
.C(n7310), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][15] ), .Z(n7185)
);
HS65_LH_AOI22X3 U5721 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][28] ), .B(n7265),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[11][28] ), .D(
n2888), .Z(n6909) );
HS65_LH_AO22X9 U5722 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][6] ), .B(n6426),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][6] ), .D(n7291), .Z(n6490) );
HS65_LH_AOI22X3 U5724 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][6] ), .B(n2887),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[22][6] ), .D(
n7171), .Z(n6483) );
HS65_LH_AOI22X3 U5726 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][15] ), .B(n7286),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[21][15] ), .D(
n7285), .Z(n6379) );
HS65_LH_AOI22X3 U5727 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][28] ), .B(n7286),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[21][28] ), .D(
n7285), .Z(n6916) );
HS65_LH_AOI22X3 U5728 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][15] ), .B(n2887),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[22][15] ), .D(
n7171), .Z(n6378) );
HS65_LH_AO22X9 U5729 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][23] ), .B(n7522),
.C(n7439), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][23] ), .Z(n7235)
);
HS65_LH_AO22X9 U5730 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][25] ), .B(n7580),
.C(n7579), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][25] ), .Z(n7036)
);
HS65_LH_AOI22X3 U5732 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][25] ), .B(n7604),
.C(n7334), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][25] ), .Z(n7048)
);
HS65_LH_AOI22X3 U5733 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][29] ), .B(n7585),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[1][29] ), .D(
n2889), .Z(n7520) );
HS65_LH_AOI22X3 U5734 ( .A(n7434), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][23] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][23] ), .D(n7516),
.Z(n7231) );
HS65_LH_AOI22X3 U5735 ( .A(n7434), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][15] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][15] ), .D(n7516),
.Z(n7191) );
HS65_LH_AOI22X3 U5736 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][9] ), .B(n7265),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[11][9] ), .D(
n6363), .Z(n7125) );
HS65_LH_AO22X9 U5737 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][29] ), .B(n7429),
.C(n6952), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][29] ), .Z(n7513)
);
HS65_LH_AO22X9 U5738 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][14] ), .B(n7600),
.C(n7599), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][14] ), .Z(n7382)
);
HS65_LH_AOI22X3 U5739 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][28] ), .B(n6595),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[14][28] ), .D(
n7264), .Z(n6910) );
HS65_LH_AO22X9 U5740 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][31] ), .B(n7522),
.C(n7439), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][31] ), .Z(n6688)
);
HS65_LH_AO22X9 U5741 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][14] ), .B(n7522),
.C(n7439), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][14] ), .Z(n7378)
);
HS65_LH_AOI22X3 U5742 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][29] ), .B(n7415),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[10][29] ), .D(
n2891), .Z(n7515) );
HS65_LH_AOI22X3 U5743 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][25] ), .B(n6754),
.C(n7594), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][25] ), .Z(n7044)
);
HS65_LH_AOI22X3 U5745 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][28] ), .B(n7415),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[10][28] ), .D(
n2891), .Z(n7495) );
HS65_LH_AO22X9 U5747 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][22] ), .B(n7600),
.C(n7599), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][22] ), .Z(n7011)
);
HS65_LH_AO22X9 U5748 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][22] ), .B(n7602),
.C(n7601), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][22] ), .Z(n7010)
);
HS65_LH_AO22X9 U5749 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][9] ), .B(n7587),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[12][9] ), .D(
n7586), .Z(n7020) );
HS65_LH_AO22X9 U5750 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][20] ), .B(n7293),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[13][20] ), .D(
n7292), .Z(n6861) );
HS65_LH_AO22X9 U5752 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][3] ), .B(n7170),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[23][3] ), .D(
n7284), .Z(n6585) );
HS65_LH_AOI22X3 U5753 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][3] ), .B(n2887),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[22][3] ), .D(
n7171), .Z(n6583) );
HS65_LH_AOI22X3 U5754 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][30] ), .B(n6754),
.C(n7594), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][30] ), .Z(n7420)
);
HS65_LH_AOI22X3 U5756 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][20] ), .B(n7297),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[0][20] ), .D(
n6942), .Z(n6859) );
HS65_LH_AO22X9 U5757 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][18] ), .B(n7429),
.C(n7310), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][18] ), .Z(n6328)
);
HS65_LH_AOI22X3 U5758 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][19] ), .B(n7524),
.C(n7593), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][19] ), .Z(n6756)
);
HS65_LH_AO22X9 U5759 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][7] ), .B(n7522),
.C(n7439), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][7] ), .Z(n6730)
);
HS65_LH_AO22X9 U5761 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][5] ), .B(n7522),
.C(n7439), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][5] ), .Z(n6710)
);
HS65_LH_AOI22X3 U5762 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][20] ), .B(n6371),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[29][20] ), .D(
n7272), .Z(n6853) );
HS65_LH_AO22X9 U5763 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][19] ), .B(n7600),
.C(n7599), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][19] ), .Z(n6762)
);
HS65_LH_AO22X9 U5765 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][18] ), .B(n7283),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[20][18] ), .D(
n7282), .Z(n6661) );
HS65_LH_AO22X9 U5766 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][19] ), .B(n7602),
.C(n7601), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][19] ), .Z(n6761)
);
HS65_LH_AOI22X3 U5767 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][18] ), .B(n6376),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[21][18] ), .D(
n7285), .Z(n6659) );
HS65_LH_AOI22X3 U5768 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][18] ), .B(n6377),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[22][18] ), .D(
n6172), .Z(n6658) );
HS65_LH_AOI22X3 U5769 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][19] ), .B(n7603),
.C(n7333), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][19] ), .Z(n6760)
);
HS65_LH_AOI22X3 U5770 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][19] ), .B(n7604),
.C(n7334), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][19] ), .Z(n6759)
);
HS65_LH_AOI22X3 U5771 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][20] ), .B(n7286),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[21][20] ), .D(
n7285), .Z(n6856) );
HS65_LH_AOI22X3 U5772 ( .A(n7428), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][18] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][18] ), .D(n6740),
.Z(n6329) );
HS65_LH_AOI22X3 U5773 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][7] ), .B(n2887),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[22][7] ), .D(
n7171), .Z(n6443) );
HS65_LH_AO22X9 U5774 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][3] ), .B(n7600),
.C(n7599), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][3] ), .Z(n7402)
);
HS65_LH_AOI22X3 U5775 ( .A(n7434), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][0] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][0] ), .D(n7516),
.Z(n7438) );
HS65_LH_AOI22X3 U5776 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][9] ), .B(n7604),
.C(n7334), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][9] ), .Z(n7028)
);
HS65_LH_AOI22X3 U5777 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][10] ), .B(n7415),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[10][10] ), .D(
n6670), .Z(n7207) );
HS65_LH_AOI22X3 U5779 ( .A(n7428), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][0] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][0] ), .D(n6740),
.Z(n7432) );
HS65_LH_AOI22X3 U5780 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][10] ), .B(n7297),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[0][10] ), .D(
n6942), .Z(n6406) );
HS65_LH_AOI22X3 U5781 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][20] ), .B(n7585),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[1][20] ), .D(
n2889), .Z(n7478) );
HS65_LH_AOI22X3 U5782 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][12] ), .B(n2887),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[22][12] ), .D(
n7171), .Z(n6543) );
HS65_LH_AOI22X3 U5783 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][22] ), .B(n7603),
.C(n7333), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][22] ), .Z(n7009)
);
HS65_LH_AO22X9 U5784 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][12] ), .B(n7283),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[20][12] ), .D(
n7282), .Z(n6546) );
HS65_LH_AOI22X3 U5785 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][10] ), .B(n7286),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[21][10] ), .D(
n7285), .Z(n6403) );
HS65_LH_AOI22X3 U5787 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][3] ), .B(n7415),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[10][3] ), .D(
n2891), .Z(n7390) );
HS65_LH_AO22X9 U5788 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][20] ), .B(n7602),
.C(n7601), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][20] ), .Z(n7486)
);
HS65_LH_AO22X9 U5789 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][18] ), .B(n7600),
.C(n7599), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][18] ), .Z(n6357)
);
HS65_LH_AO22X9 U5790 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][18] ), .B(n7602),
.C(n7601), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][18] ), .Z(n6356)
);
HS65_LH_AOI22X3 U5791 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][18] ), .B(n7603),
.C(n7333), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][18] ), .Z(n6355)
);
HS65_LH_AOI22X3 U5792 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][9] ), .B(n6754),
.C(n7594), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][9] ), .Z(n7024)
);
HS65_LH_AOI22X3 U5793 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][18] ), .B(n7604),
.C(n7334), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][18] ), .Z(n6354)
);
HS65_LH_AO22X9 U5794 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][4] ), .B(n7580),
.C(n7579), .D(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][4] ), .Z(n7347) );
HS65_LH_AO22X9 U5795 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][9] ), .B(n7600),
.C(n7599), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][9] ), .Z(n7031)
);
HS65_LH_AOI22X3 U5797 ( .A(n7434), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][10] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][10] ), .D(n7516),
.Z(n7211) );
HS65_LH_AOI22X3 U5798 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][3] ), .B(n7585),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[1][3] ), .D(n2889), .Z(n7393) );
HS65_LH_AO22X9 U5799 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][20] ), .B(n7580),
.C(n7579), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][20] ), .Z(n7472)
);
HS65_LH_AO22X9 U5800 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][9] ), .B(n7602),
.C(n7601), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][9] ), .Z(n7030)
);
HS65_LH_AOI22X3 U5802 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][9] ), .B(n7603),
.C(n7333), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][9] ), .Z(n7029)
);
HS65_LH_AO22X9 U5804 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][19] ), .B(n7580),
.C(n7579), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][19] ), .Z(n6741)
);
HS65_LH_AO22X9 U5805 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][4] ), .B(n7587),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[12][4] ), .D(
n7586), .Z(n7351) );
HS65_LH_AO22X9 U5806 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][27] ), .B(n7580),
.C(n7579), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][27] ), .Z(n7452)
);
HS65_LH_AO22X9 U5808 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][27] ), .B(n7587),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[12][27] ), .D(
n7586), .Z(n7456) );
HS65_LH_AO22X9 U5809 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][27] ), .B(n7602),
.C(n7601), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][27] ), .Z(n7466)
);
HS65_LH_AOI22X3 U5810 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][11] ), .B(n7604),
.C(n7334), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][11] ), .Z(n7068)
);
HS65_LH_AO22X9 U5812 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][11] ), .B(n7602),
.C(n7601), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][11] ), .Z(n7070)
);
HS65_LH_AO22X9 U5813 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][11] ), .B(n7600),
.C(n7599), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][11] ), .Z(n7071)
);
HS65_LH_AOI22X3 U5814 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][11] ), .B(n6754),
.C(n7594), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][11] ), .Z(n7064)
);
HS65_LH_AO22X9 U5817 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][11] ), .B(n7587),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[12][11] ), .D(
n7586), .Z(n7060) );
HS65_LH_AO22X9 U5818 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][19] ), .B(n7587),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[12][19] ), .D(
n7586), .Z(n6748) );
HS65_LH_AOI22X3 U5819 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][20] ), .B(n7265),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[11][20] ), .D(
n2888), .Z(n6849) );
HS65_LH_AO22X9 U5820 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][16] ), .B(n7602),
.C(n7601), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][16] ), .Z(n7552)
);
HS65_LH_AOI22X3 U5822 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][20] ), .B(n6595),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[14][20] ), .D(
n7264), .Z(n6850) );
HS65_LH_NOR2X6 U5823 ( .A(opcode_i[5]), .B(n8046), .Z(n8636) );
HS65_LL_OAI12X3 U5824 ( .A(n5971), .B(n5974), .C(n5973), .Z(n6115) );
HS65_LH_NOR2X6 U5825 ( .A(n8794), .B(n9050), .Z(\u_DataPath/cw_exmem_i [3])
);
HS65_LH_NOR2X6 U5827 ( .A(n9168), .B(n9049), .Z(\u_DataPath/u_idexreg/N15 )
);
HS65_LH_OAI21X3 U5828 ( .A(n8871), .B(n9012), .C(n8767), .Z(n8105) );
HS65_LH_NOR2X6 U5829 ( .A(n8884), .B(n9051), .Z(n8438) );
HS65_LL_NAND2X4 U5830 ( .A(n3431), .B(n3430), .Z(n4458) );
HS65_LH_NOR2X6 U5831 ( .A(n8834), .B(n3341), .Z(n3058) );
HS65_LH_NOR2X6 U5832 ( .A(n8821), .B(n3341), .Z(n4973) );
HS65_LH_NOR2X6 U5833 ( .A(n8859), .B(n3341), .Z(n3150) );
HS65_LH_NAND2X7 U5834 ( .A(n8556), .B(n3155), .Z(n3156) );
HS65_LH_NOR2X5 U5835 ( .A(n8841), .B(n3403), .Z(n3108) );
HS65_LH_NOR2X6 U5837 ( .A(n8838), .B(n3341), .Z(n3096) );
HS65_LL_NAND2X2 U5838 ( .A(n3181), .B(n8543), .Z(n3182) );
HS65_LH_IVX9 U5839 ( .A(n8545), .Z(n3173) );
HS65_LH_NOR2X6 U5840 ( .A(n3122), .B(n7754), .Z(n7679) );
HS65_LL_OAI12X3 U5841 ( .A(n5767), .B(n5770), .C(n5769), .Z(n5916) );
HS65_LHS_XOR2X3 U5843 ( .A(n5771), .B(n5770), .Z(\u_DataPath/toPC2_i [24])
);
HS65_LH_NAND2X7 U5844 ( .A(n2733), .B(\u_DataPath/toPC2_i [23]), .Z(n8245)
);
HS65_LH_NAND2X7 U5845 ( .A(n2733), .B(\u_DataPath/toPC2_i [14]), .Z(n8253)
);
HS65_LL_NAND2X11 U5846 ( .A(n3303), .B(n3302), .Z(n5088) );
HS65_LH_NAND2X7 U5847 ( .A(n3234), .B(n8511), .Z(n3235) );
HS65_LH_NOR2X6 U5848 ( .A(n9400), .B(n3341), .Z(n3269) );
HS65_LL_IVX9 U5850 ( .A(n3340), .Z(n3270) );
HS65_LH_NAND2X7 U5851 ( .A(n8577), .B(n8318), .Z(n8300) );
HS65_LH_IVX9 U5852 ( .A(n7764), .Z(n7755) );
HS65_LH_NAND2X7 U5853 ( .A(n8038), .B(n8039), .Z(n8068) );
HS65_LH_AOI31X3 U5855 ( .A(n8086), .B(\u_DataPath/immediate_ext_dec_i [1]),
.C(n8635), .D(n8085), .Z(n8087) );
HS65_LH_IVX9 U5856 ( .A(n8277), .Z(\u_DataPath/branch_target_i [7]) );
HS65_LH_IVX9 U5857 ( .A(n8260), .Z(\u_DataPath/branch_target_i [9]) );
HS65_LH_IVX7 U5858 ( .A(n8045), .Z(n8046) );
HS65_LH_IVX9 U5859 ( .A(n8251), .Z(\u_DataPath/branch_target_i [16]) );
HS65_LH_IVX9 U5860 ( .A(n8247), .Z(\u_DataPath/branch_target_i [21]) );
HS65_LH_NAND2AX7 U5861 ( .A(\u_DataPath/data_read_ex_2_i [10]), .B(n2874),
.Z(n8508) );
HS65_LH_NOR2X6 U5862 ( .A(n8393), .B(n3340), .Z(n3343) );
HS65_LL_NAND2X4 U5863 ( .A(n3286), .B(n2874), .Z(n3287) );
HS65_LH_NAND2X7 U5864 ( .A(n8040), .B(n8039), .Z(n8069) );
HS65_LH_IVX7 U5865 ( .A(n8519), .Z(n3280) );
HS65_LH_OAI21X3 U5867 ( .A(n8125), .B(n8124), .C(n8635), .Z(n8127) );
HS65_LH_OAI21X3 U5868 ( .A(n8075), .B(n8125), .C(n8635), .Z(n8080) );
HS65_LH_NOR2X6 U5869 ( .A(n8389), .B(n7868), .Z(n8519) );
HS65_LH_IVX9 U5870 ( .A(n8188), .Z(n8288) );
HS65_LH_NAND2X7 U5871 ( .A(n2733), .B(\u_DataPath/toPC2_i [16]), .Z(n8251)
);
HS65_LH_NAND2X7 U5872 ( .A(n2733), .B(\u_DataPath/toPC2_i [21]), .Z(n8247)
);
HS65_LL_NAND3X13 U5873 ( .A(n3333), .B(n3057), .C(n3056), .Z(n3340) );
HS65_LL_BFX9 U5875 ( .A(n8483), .Z(n7921) );
HS65_LHS_XOR2X3 U5876 ( .A(n5828), .B(n5827), .Z(\u_DataPath/toPC2_i [22])
);
HS65_LH_NOR2X6 U5877 ( .A(n8037), .B(n8117), .Z(n8039) );
HS65_LH_NOR2X6 U5878 ( .A(n8041), .B(n8117), .Z(n8045) );
HS65_LH_NAND2X7 U5879 ( .A(n2733), .B(\u_DataPath/toPC2_i [10]), .Z(n8259)
);
HS65_LH_NOR2X6 U5880 ( .A(n8047), .B(n8117), .Z(n8634) );
HS65_LH_NAND2X7 U5881 ( .A(n2733), .B(\u_DataPath/toPC2_i [9]), .Z(n8260) );
HS65_LH_NAND2X7 U5882 ( .A(n2733), .B(\u_DataPath/toPC2_i [7]), .Z(n8277) );
HS65_LH_NOR2X6 U5883 ( .A(n7715), .B(n7714), .Z(n7716) );
HS65_LH_NOR2X6 U5884 ( .A(n8385), .B(n7868), .Z(n8539) );
HS65_LH_OAI211X3 U5885 ( .A(n8488), .B(n7868), .C(n8487), .D(n8566), .Z(
n8489) );
HS65_LH_NOR2X6 U5886 ( .A(n8345), .B(n7868), .Z(n8510) );
HS65_LH_NAND2X4 U5888 ( .A(n4714), .B(n8535), .Z(n3190) );
HS65_LH_NOR2X6 U5889 ( .A(n3241), .B(n7868), .Z(n8507) );
HS65_LH_IVX9 U5891 ( .A(n7671), .Z(n7677) );
HS65_LH_NOR2X6 U5892 ( .A(n8339), .B(n7868), .Z(n8516) );
HS65_LH_NAND2X7 U5893 ( .A(n3127), .B(n7869), .Z(n8562) );
HS65_LH_IVX9 U5896 ( .A(n5791), .Z(n5773) );
HS65_LH_NAND2X7 U5897 ( .A(n8566), .B(n7306), .Z(n8456) );
HS65_LH_NAND2X7 U5898 ( .A(n3140), .B(n7869), .Z(n8553) );
HS65_LH_NAND2X7 U5899 ( .A(n3153), .B(n7869), .Z(n8557) );
HS65_LHS_XNOR2X6 U5900 ( .A(n5702), .B(n5701), .Z(n5703) );
HS65_LH_NOR2X6 U5901 ( .A(n8830), .B(n7869), .Z(n3215) );
HS65_LH_NAND2X7 U5902 ( .A(n7661), .B(n7660), .Z(n7759) );
HS65_LHS_XNOR2X3 U5903 ( .A(n7713), .B(n7712), .Z(
\u_DataPath/u_execute/link_value_i [20]) );
HS65_LH_NAND2X7 U5904 ( .A(n8267), .B(n7869), .Z(n5692) );
HS65_LH_NAND2X7 U5905 ( .A(n3201), .B(n7869), .Z(n8530) );
HS65_LH_NAND2X7 U5906 ( .A(n3225), .B(n3407), .Z(n3080) );
HS65_LH_NOR2X6 U5907 ( .A(n8863), .B(n7869), .Z(n3226) );
HS65_LH_NAND2X7 U5908 ( .A(n3205), .B(n3407), .Z(n3094) );
HS65_LH_AOI12X2 U5909 ( .A(n6081), .B(n6083), .C(n6023), .Z(n6024) );
HS65_LH_NAND2X7 U5910 ( .A(n3242), .B(n7869), .Z(n8509) );
HS65_LH_NOR2X6 U5911 ( .A(n8849), .B(n7869), .Z(n3257) );
HS65_LH_NAND2X4 U5912 ( .A(n4714), .B(n8527), .Z(n3206) );
HS65_LH_IVX9 U5913 ( .A(n5992), .Z(n6007) );
HS65_LH_NAND2X7 U5915 ( .A(n3252), .B(n7869), .Z(n8518) );
HS65_LH_NAND2X7 U5916 ( .A(n3273), .B(n7869), .Z(n8524) );
HS65_LH_NAND2X7 U5917 ( .A(n3188), .B(n7869), .Z(n8535) );
HS65_LH_NAND2X7 U5919 ( .A(n3336), .B(n7869), .Z(n8496) );
HS65_LH_NAND2X7 U5920 ( .A(n2733), .B(\u_DataPath/u_fetch/pc1/N3 ), .Z(n8188) );
HS65_LH_NOR2X5 U5921 ( .A(n8842), .B(n7869), .Z(n3189) );
HS65_LH_NAND2X7 U5922 ( .A(n7670), .B(n7749), .Z(n7671) );
HS65_LH_NAND2X7 U5923 ( .A(n2733), .B(\u_DataPath/toPC2_i [3]), .Z(n8281) );
HS65_LL_OAI12X3 U5924 ( .A(n2879), .B(n3114), .C(n3113), .Z(n8576) );
HS65_LH_NAND2X7 U5925 ( .A(n2733), .B(\u_DataPath/toPC2_i [4]), .Z(n8280) );
HS65_LH_IVX9 U5927 ( .A(n7739), .Z(n8161) );
HS65_LH_IVX9 U5928 ( .A(n7720), .Z(n7723) );
HS65_LH_NAND2X5 U5929 ( .A(n3205), .B(n7802), .Z(n8527) );
HS65_LH_NOR2X6 U5931 ( .A(n3120), .B(n7673), .Z(n7660) );
HS65_LH_NAND2X7 U5932 ( .A(n3307), .B(n7802), .Z(n8492) );
HS65_LHS_XOR2X6 U5933 ( .A(n7793), .B(n7792), .Z(
\u_DataPath/u_execute/link_value_i [12]) );
HS65_LH_NAND2X7 U5934 ( .A(\u_DataPath/dataOut_exe_i [4]), .B(n7802), .Z(
n3347) );
HS65_LHS_XOR2X6 U5935 ( .A(n4005), .B(n4004), .Z(n4006) );
HS65_LH_IVX9 U5936 ( .A(n5999), .Z(n6083) );
HS65_LH_NAND3X5 U5937 ( .A(\u_DataPath/dataOut_exe_i [0]), .B(n4714), .C(
n7802), .Z(n3283) );
HS65_LH_NOR2X3 U5938 ( .A(n8833), .B(n7802), .Z(n3134) );
HS65_LH_NOR2X6 U5941 ( .A(n7691), .B(n7637), .Z(n7739) );
HS65_LH_IVX9 U5943 ( .A(n5962), .Z(n6077) );
HS65_LH_NAND2X7 U5944 ( .A(n7730), .B(n7729), .Z(n7792) );
HS65_LHS_XNOR2X6 U5946 ( .A(n7727), .B(n7729), .Z(
\u_DataPath/u_execute/link_value_i [10]) );
HS65_LH_IVX9 U5947 ( .A(n7903), .Z(n5713) );
HS65_LH_NAND2X5 U5948 ( .A(n9229), .B(n7781), .Z(n7782) );
HS65_LH_IVX9 U5949 ( .A(n5758), .Z(n5878) );
HS65_LHS_XNOR2X6 U5950 ( .A(n5901), .B(n5900), .Z(\u_DataPath/toPC2_i [3])
);
HS65_LHS_XNOR2X6 U5951 ( .A(n6096), .B(n6095), .Z(
\u_DataPath/u_execute/resAdd1_i [4]) );
HS65_LL_NAND2AX7 U5952 ( .A(n3044), .B(n3043), .Z(n3333) );
HS65_LL_NOR3X4 U5953 ( .A(n2984), .B(n9113), .C(n7640), .Z(n2879) );
HS65_LH_IVX18 U5954 ( .A(n5234), .Z(n5656) );
HS65_LL_NOR2X5 U5955 ( .A(n2964), .B(n8262), .Z(n3131) );
HS65_LL_AOI31X4 U5956 ( .A(n2965), .B(n2961), .C(n2912), .D(n2964), .Z(n3216) );
HS65_LH_IVX9 U5958 ( .A(n7905), .Z(n7904) );
HS65_LH_NAND3X5 U5960 ( .A(n2846), .B(n9031), .C(n2946), .Z(n3010) );
HS65_LH_IVX18 U5961 ( .A(n7906), .Z(n7903) );
HS65_LH_NAND2X4 U5964 ( .A(n9111), .B(n7085), .Z(n7094) );
HS65_LH_NOR2X6 U5965 ( .A(n7694), .B(n7775), .Z(n7691) );
HS65_LH_IVX9 U5966 ( .A(n7690), .Z(n7777) );
HS65_LH_NAND2X7 U5968 ( .A(n2733), .B(n7854), .Z(n8408) );
HS65_LH_NOR2X6 U5969 ( .A(n7652), .B(n7647), .Z(n7670) );
HS65_LL_NOR2X5 U5971 ( .A(n3450), .B(n3449), .Z(n5234) );
HS65_LH_NAND2X7 U5972 ( .A(n2733), .B(n8345), .Z(n8348) );
HS65_LH_NOR2X6 U5973 ( .A(n5995), .B(n5998), .Z(n6016) );
HS65_LL_NOR2X5 U5974 ( .A(n6150), .B(n6140), .Z(n6637) );
HS65_LL_NAND2X7 U5975 ( .A(n7114), .B(n7113), .Z(n7614) );
HS65_LH_NAND2X7 U5976 ( .A(n8269), .B(n2980), .Z(n3111) );
HS65_LH_IVX9 U5979 ( .A(n3314), .Z(n3413) );
HS65_LH_NOR2X6 U5980 ( .A(n7718), .B(n7787), .Z(n7781) );
HS65_LL_NOR3X4 U5981 ( .A(n3042), .B(n3041), .C(n3040), .Z(n3043) );
HS65_LH_IVX7 U5983 ( .A(n3048), .Z(n3049) );
HS65_LH_BFX18 U5984 ( .A(n8282), .Z(n7882) );
HS65_LH_NAND2X7 U5985 ( .A(n5930), .B(n5961), .Z(n5932) );
HS65_LL_NAND2X4 U5987 ( .A(n4713), .B(n9037), .Z(n3395) );
HS65_LH_NAND2X2 U5988 ( .A(n4713), .B(n9343), .Z(n3164) );
HS65_LH_OR2X9 U5989 ( .A(\u_DataPath/jaddr_i [18]), .B(n2880), .Z(n6341) );
HS65_LH_NAND2X4 U5990 ( .A(n4717), .B(n9343), .Z(n4209) );
HS65_LHS_XNOR2X3 U5991 ( .A(\u_DataPath/jaddr_i [20]), .B(n7618), .Z(n7087)
);
HS65_LH_IVX9 U5992 ( .A(n8446), .Z(n7907) );
HS65_LH_IVX7 U5993 ( .A(n5961), .Z(n5967) );
HS65_LL_NAND3X3 U5994 ( .A(n2935), .B(n2957), .C(n2963), .Z(n2939) );
HS65_LH_NAND2X7 U5995 ( .A(n4285), .B(n5688), .Z(n4286) );
HS65_LH_IVX9 U5996 ( .A(n8591), .Z(n7947) );
HS65_LL_NOR2X2 U5997 ( .A(n2959), .B(n2958), .Z(n2965) );
HS65_LL_NOR2X5 U5998 ( .A(n6334), .B(n6353), .Z(n6745) );
HS65_LH_NAND2X7 U6000 ( .A(n5811), .B(n5814), .Z(n5798) );
HS65_LL_NOR2X5 U6001 ( .A(n6147), .B(n2886), .Z(n6362) );
HS65_LH_NAND2X7 U6002 ( .A(n5728), .B(n5757), .Z(n5730) );
HS65_LH_NAND2X7 U6003 ( .A(n5853), .B(n5718), .Z(n5742) );
HS65_LH_IVX7 U6005 ( .A(n8393), .Z(n3418) );
HS65_LH_NAND2X7 U6006 ( .A(n5726), .B(n5779), .Z(n5760) );
HS65_LL_NOR2X5 U6008 ( .A(n6348), .B(n6334), .Z(n6739) );
HS65_LH_NAND2X4 U6009 ( .A(n4717), .B(n9341), .Z(n3145) );
HS65_LL_NOR2X5 U6010 ( .A(n6334), .B(n6349), .Z(n6951) );
HS65_LH_NAND2X5 U6011 ( .A(n5722), .B(n5834), .Z(n5724) );
HS65_LH_NAND2X7 U6013 ( .A(n2733), .B(n8265), .Z(n8275) );
HS65_LH_IVX4 U6014 ( .A(n7665), .Z(n7741) );
HS65_LH_NAND2X7 U6016 ( .A(\u_DataPath/jaddr_i [25]), .B(n6138), .Z(n6140)
);
HS65_LL_NOR2X3 U6017 ( .A(n6349), .B(n6352), .Z(n6689) );
HS65_LH_NAND2X7 U6019 ( .A(n2733), .B(n8426), .Z(n8449) );
HS65_LH_NAND2X7 U6020 ( .A(n2733), .B(n8380), .Z(n8397) );
HS65_LH_NAND2X7 U6021 ( .A(n2733), .B(n8385), .Z(n8412) );
HS65_LH_IVX9 U6022 ( .A(n7776), .Z(n8084) );
HS65_LH_NAND2X7 U6025 ( .A(n4713), .B(n8913), .Z(n3346) );
HS65_LH_NAND2X7 U6026 ( .A(n7695), .B(n7773), .Z(n7775) );
HS65_LH_IVX9 U6027 ( .A(n8446), .Z(n7906) );
HS65_LH_NAND2X7 U6029 ( .A(addr_to_iram[4]), .B(n8682), .Z(n7680) );
HS65_LH_NAND2X7 U6032 ( .A(n5928), .B(n5980), .Z(n5964) );
HS65_LH_NAND2X7 U6033 ( .A(n4717), .B(n9039), .Z(n3303) );
HS65_LH_NAND2X7 U6035 ( .A(n5936), .B(n6011), .Z(n5998) );
HS65_LH_NAND2X7 U6036 ( .A(n2733), .B(n8427), .Z(n8330) );
HS65_LH_NAND2X7 U6037 ( .A(n2733), .B(n8323), .Z(n8326) );
HS65_LH_IVX7 U6040 ( .A(n8446), .Z(n7905) );
HS65_LH_NAND2X7 U6041 ( .A(n2733), .B(n8350), .Z(n8353) );
HS65_LH_IVX9 U6042 ( .A(n8051), .Z(n8067) );
HS65_LH_IVX9 U6043 ( .A(n8231), .Z(n8282) );
HS65_LH_NOR2X6 U6044 ( .A(n5957), .B(n5960), .Z(n5930) );
HS65_LH_NAND2X7 U6045 ( .A(\u_DataPath/jaddr_i [22]), .B(n8163), .Z(n2886)
);
HS65_LH_NAND2X7 U6046 ( .A(n5920), .B(n5919), .Z(n5946) );
HS65_LL_NAND2X7 U6047 ( .A(n8153), .B(n8152), .Z(n6350) );
HS65_LH_IVX9 U6048 ( .A(n8052), .Z(n8629) );
HS65_LH_NOR2X6 U6049 ( .A(n5882), .B(n5887), .Z(n5722) );
HS65_LL_NAND2X7 U6050 ( .A(\u_DataPath/jaddr_i [17]), .B(n8152), .Z(n6349)
);
HS65_LH_NOR2X6 U6051 ( .A(n8090), .B(rst), .Z(
\u_DataPath/immediate_ext_ex_i [2]) );
HS65_LH_NAND2X7 U6052 ( .A(n8566), .B(n8264), .Z(n8446) );
HS65_LH_NAND2X7 U6054 ( .A(n7697), .B(n8055), .Z(n7734) );
HS65_LH_NOR2X6 U6055 ( .A(n8131), .B(rst), .Z(n8621) );
HS65_LH_NOR2X6 U6056 ( .A(n8157), .B(rst), .Z(
\u_DataPath/immediate_ext_ex_i [1]) );
HS65_LH_NOR2X6 U6058 ( .A(opcode_i[5]), .B(n8070), .Z(n7773) );
HS65_LH_NOR2X5 U6059 ( .A(\u_DataPath/dataOut_exe_i [0]), .B(n8177), .Z(
n3113) );
HS65_LH_NOR2X6 U6061 ( .A(n6073), .B(n6078), .Z(n5980) );
HS65_LH_NAND2X7 U6062 ( .A(n8165), .B(n6131), .Z(n6133) );
HS65_LH_NOR2X6 U6063 ( .A(n6019), .B(n6022), .Z(n6011) );
HS65_LH_NAND2X7 U6064 ( .A(n9084), .B(n7643), .Z(n7694) );
HS65_LH_NOR2X6 U6065 ( .A(n8130), .B(rst), .Z(
\u_DataPath/immediate_ext_ex_i [0]) );
HS65_LH_NOR2X6 U6066 ( .A(n5976), .B(n5979), .Z(n5928) );
HS65_LL_NAND2X7 U6067 ( .A(\u_DataPath/jaddr_i [21]), .B(n8164), .Z(n6148)
);
HS65_LH_NAND2X7 U6068 ( .A(n2977), .B(n2976), .Z(n2982) );
HS65_LH_IVX9 U6069 ( .A(n8050), .Z(n8631) );
HS65_LH_NAND2X7 U6071 ( .A(\u_DataPath/jaddr_i [19]), .B(n6326), .Z(n2878)
);
HS65_LH_IVX44 U6072 ( .A(n3125), .Z(addr_to_iram[13]) );
HS65_LH_IVX9 U6073 ( .A(n8062), .Z(n8623) );
HS65_LH_IVX9 U6074 ( .A(n8187), .Z(\u_DataPath/u_idexreg/N31 ) );
HS65_LH_IVX9 U6076 ( .A(n5915), .Z(n5739) );
HS65_LH_NAND2X7 U6077 ( .A(n7105), .B(n7104), .Z(n7110) );
HS65_LH_IVX9 U6078 ( .A(n5812), .Z(n5733) );
HS65_LL_NAND2X2 U6079 ( .A(n3037), .B(n3036), .Z(n3039) );
HS65_LH_NAND2X7 U6080 ( .A(n7116), .B(n9234), .Z(n8236) );
HS65_LL_IVX18 U6081 ( .A(n7758), .Z(addr_to_iram[16]) );
HS65_LH_IVX9 U6082 ( .A(n8186), .Z(\u_DataPath/u_idexreg/N33 ) );
HS65_LH_NOR2X6 U6083 ( .A(n4002), .B(n7718), .Z(n4003) );
HS65_LH_IVX9 U6084 ( .A(n8179), .Z(\u_DataPath/immediate_ext_ex_i [7]) );
HS65_LH_NOR2X6 U6085 ( .A(n4284), .B(n7728), .Z(n5688) );
HS65_LH_IVX9 U6086 ( .A(n8185), .Z(\u_DataPath/immediate_ext_ex_i [9]) );
HS65_LH_IVX9 U6088 ( .A(n8182), .Z(\u_DataPath/immediate_ext_ex_i [10]) );
HS65_LH_IVX9 U6089 ( .A(n5911), .Z(n5738) );
HS65_LH_IVX9 U6090 ( .A(n5903), .Z(n5737) );
HS65_LH_NAND2X7 U6091 ( .A(n7100), .B(n7099), .Z(n7112) );
HS65_LH_NOR2X6 U6092 ( .A(n4283), .B(n5687), .Z(n4285) );
HS65_LH_NOR2X6 U6093 ( .A(n5874), .B(n5879), .Z(n5779) );
HS65_LH_IVX9 U6095 ( .A(n5859), .Z(n5741) );
HS65_LH_NOR2X6 U6096 ( .A(n6061), .B(n6066), .Z(n5936) );
HS65_LH_IVX44 U6098 ( .A(n7742), .Z(addr_to_iram[4]) );
HS65_LH_NOR2X6 U6099 ( .A(n8162), .B(rst), .Z(
\u_DataPath/immediate_ext_ex_i [3]) );
HS65_LH_NOR2X6 U6100 ( .A(n5775), .B(n5778), .Z(n5726) );
HS65_LH_IVX9 U6101 ( .A(n6110), .Z(n5940) );
HS65_LH_NOR2X2 U6102 ( .A(n8170), .B(rst), .Z(
\u_DataPath/regfile_addr_out_towb_i [1]) );
HS65_LH_IVX9 U6103 ( .A(n6106), .Z(n5941) );
HS65_LH_IVX9 U6104 ( .A(n6114), .Z(n5942) );
HS65_LH_NOR2X6 U6105 ( .A(n5786), .B(n5772), .Z(n5757) );
HS65_LH_IVX7 U6107 ( .A(n6082), .Z(n6023) );
HS65_LH_NAND2X7 U6108 ( .A(n5852), .B(n5851), .Z(n5857) );
HS65_LH_IVX9 U6109 ( .A(n6118), .Z(n5943) );
HS65_LH_NOR2X6 U6110 ( .A(n8172), .B(rst), .Z(
\u_DataPath/immediate_ext_ex_i [5]) );
HS65_LH_IVX44 U6111 ( .A(n7753), .Z(addr_to_iram[10]) );
HS65_LH_NOR2X6 U6112 ( .A(n5753), .B(n5756), .Z(n5728) );
HS65_LH_NOR2X5 U6114 ( .A(n8911), .B(n9204), .Z(n5947) );
HS65_LH_IVX9 U6117 ( .A(\u_DataPath/dataOut_exe_i [31]), .Z(n4187) );
HS65_LH_NAND2X4 U6119 ( .A(n9037), .B(n9212), .Z(n5848) );
HS65_LH_OR2X9 U6120 ( .A(n8969), .B(n9216), .Z(n6013) );
HS65_LH_OR2X9 U6123 ( .A(n8911), .B(n9203), .Z(n6053) );
HS65_LH_NAND2X7 U6124 ( .A(n8942), .B(n9222), .Z(n6082) );
HS65_LH_NAND2X7 U6127 ( .A(n9227), .B(n9225), .Z(n7718) );
HS65_LH_NOR2X6 U6128 ( .A(n9347), .B(rst), .Z(n8066) );
HS65_LH_NAND2X4 U6129 ( .A(n9033), .B(n9215), .Z(n5896) );
HS65_LH_IVX9 U6138 ( .A(\u_DataPath/immediate_ext_dec_i [1]), .Z(n8157) );
HS65_LL_OR2X9 U6144 ( .A(\u_DataPath/jaddr_i [22]), .B(
\u_DataPath/jaddr_i [21]), .Z(n6153) );
HS65_LL_NAND2X7 U6146 ( .A(\u_DataPath/jaddr_i [21]), .B(
\u_DataPath/jaddr_i [22]), .Z(n6150) );
HS65_LH_IVX9 U6149 ( .A(\u_DataPath/immediate_ext_dec_i [5]), .Z(n8172) );
HS65_LH_IVX9 U6154 ( .A(\u_DataPath/dataOut_exe_i [22]), .Z(n3170) );
HS65_LL_NAND2X5 U6155 ( .A(\u_DataPath/jaddr_i [16]), .B(
\u_DataPath/jaddr_i [17]), .Z(n6348) );
HS65_LH_IVX7 U6156 ( .A(n9035), .Z(n3284) );
HS65_LH_NOR2X6 U6157 ( .A(\u_DataPath/jaddr_i [23]), .B(
\u_DataPath/jaddr_i [24]), .Z(n6145) );
HS65_LH_IVX9 U6158 ( .A(\u_DataPath/cw_to_ex_i [19]), .Z(n7874) );
HS65_LH_OR2X9 U6159 ( .A(n9004), .B(n9209), .Z(n6105) );
HS65_LH_IVX7 U6160 ( .A(n8944), .Z(n3029) );
HS65_LH_IVX9 U6161 ( .A(\u_DataPath/dataOut_exe_i [2]), .Z(n3296) );
HS65_LH_IVX9 U6162 ( .A(n9206), .Z(n7795) );
HS65_LH_IVX9 U6165 ( .A(n9208), .Z(n7799) );
HS65_LH_IVX9 U6166 ( .A(n8911), .Z(n3031) );
HS65_LH_OR2X9 U6167 ( .A(n8911), .B(n9207), .Z(n6113) );
HS65_LH_IVX9 U6168 ( .A(n9210), .Z(n7797) );
HS65_LH_IVX9 U6169 ( .A(n9216), .Z(n5696) );
HS65_LH_NOR2X5 U6170 ( .A(n8911), .B(n9206), .Z(n5952) );
HS65_LH_IVX9 U6171 ( .A(n9217), .Z(n7713) );
HS65_LH_NAND2X7 U6172 ( .A(n9218), .B(n9220), .Z(n7711) );
HS65_LH_NAND2X7 U6175 ( .A(n9116), .B(n9215), .Z(n7725) );
HS65_LH_NOR2X3 U6176 ( .A(n8913), .B(n9219), .Z(n5839) );
HS65_LH_IVX9 U6177 ( .A(\u_DataPath/immediate_ext_dec_i [3]), .Z(n8162) );
HS65_LH_NOR2X6 U6178 ( .A(n8910), .B(rst), .Z(n8283) );
HS65_LH_IVX9 U6180 ( .A(opcode_i[3]), .Z(n8070) );
HS65_LH_NAND2X7 U6181 ( .A(n8911), .B(n9208), .Z(n5973) );
HS65_LH_NAND2X7 U6182 ( .A(n2733), .B(\u_DataPath/immediate_ext_dec_i [12]),
.Z(n8052) );
HS65_LH_NAND2X7 U6183 ( .A(n8911), .B(n9207), .Z(n6114) );
HS65_LH_NAND2X7 U6184 ( .A(n8911), .B(n9206), .Z(n5954) );
HS65_LH_NAND2X7 U6185 ( .A(n8685), .B(n8684), .Z(n7644) );
HS65_LH_NAND2X7 U6186 ( .A(n8680), .B(n8678), .Z(n7645) );
HS65_LH_NAND2X7 U6187 ( .A(n9181), .B(n9226), .Z(n5863) );
HS65_LH_NAND2X7 U6188 ( .A(n8911), .B(n9205), .Z(n6118) );
HS65_LH_NOR2X6 U6189 ( .A(\u_DataPath/dataOut_exe_i [0]), .B(
\u_DataPath/dataOut_exe_i [1]), .Z(n3112) );
HS65_LH_NAND2X7 U6191 ( .A(n8911), .B(n9204), .Z(n5949) );
HS65_LH_IVX9 U6192 ( .A(\u_DataPath/dataOut_exe_i [14]), .Z(n3278) );
HS65_LH_NAND2X7 U6193 ( .A(n9343), .B(n9203), .Z(n5853) );
HS65_LH_NAND2X7 U6194 ( .A(n8681), .B(n8679), .Z(n7652) );
HS65_LH_NAND2X7 U6195 ( .A(n2733), .B(\u_DataPath/immediate_ext_dec_i [13]),
.Z(n8064) );
HS65_LH_NAND2X7 U6197 ( .A(n9145), .B(n9224), .Z(n5755) );
HS65_LH_NAND2X7 U6198 ( .A(n8911), .B(n9203), .Z(n6054) );
HS65_LH_NAND2X7 U6200 ( .A(n9342), .B(n9204), .Z(n5859) );
HS65_LH_IVX9 U6201 ( .A(n9235), .Z(n2977) );
HS65_LH_IVX9 U6204 ( .A(n9082), .Z(n7643) );
HS65_LH_NAND2X7 U6206 ( .A(n9343), .B(n9205), .Z(n5745) );
HS65_LH_NAND2X7 U6207 ( .A(n2733), .B(\u_DataPath/immediate_ext_dec_i [14]),
.Z(n8062) );
HS65_LHS_XNOR2X3 U6209 ( .A(\u_DataPath/jaddr_i [24]), .B(n9077), .Z(n7106)
);
HS65_LH_NAND2X7 U6211 ( .A(n9342), .B(n9222), .Z(n5867) );
HS65_LH_IVX9 U6212 ( .A(opcode_i[1]), .Z(n7697) );
HS65_LH_NAND2X7 U6214 ( .A(n9342), .B(n9206), .Z(n5907) );
HS65_LHS_XNOR2X3 U6216 ( .A(\u_DataPath/jaddr_i [23]), .B(n8967), .Z(n7107)
);
HS65_LH_NAND2X7 U6218 ( .A(n8706), .B(n8708), .Z(n7686) );
HS65_LH_NAND2X7 U6220 ( .A(n9341), .B(n9207), .Z(n5750) );
HS65_LH_NAND2X7 U6221 ( .A(n8705), .B(n8697), .Z(n7658) );
HS65_LHS_XNOR2X3 U6223 ( .A(\u_DataPath/jaddr_i [25]), .B(n8968), .Z(n7105)
);
HS65_LH_NAND2X7 U6224 ( .A(n9341), .B(n9208), .Z(n5915) );
HS65_LH_NAND2X7 U6225 ( .A(n9343), .B(n9220), .Z(n5812) );
HS65_LH_NAND2X7 U6226 ( .A(n9343), .B(n9209), .Z(n5769) );
HS65_LH_NAND2X7 U6227 ( .A(n2733), .B(\u_DataPath/immediate_ext_dec_i [15]),
.Z(n8159) );
HS65_LH_NAND2X7 U6229 ( .A(n9341), .B(n9210), .Z(n5911) );
HS65_LH_IVX9 U6231 ( .A(\u_DataPath/jaddr_i [24]), .Z(n8151) );
HS65_LH_IVX9 U6232 ( .A(\u_DataPath/dataOut_exe_i [9]), .Z(n3225) );
HS65_LH_NAND2X7 U6233 ( .A(n9343), .B(n9213), .Z(n5826) );
HS65_LH_NAND2X7 U6236 ( .A(n9341), .B(n9217), .Z(n5806) );
HS65_LH_IVX9 U6237 ( .A(n8932), .Z(n7115) );
HS65_LH_NOR2X6 U6238 ( .A(\u_DataPath/cw_exmem_i [6]), .B(
\u_DataPath/cw_exmem_i [4]), .Z(n7098) );
HS65_LH_NAND2X7 U6240 ( .A(n9343), .B(n9216), .Z(n5903) );
HS65_LH_IVX9 U6241 ( .A(n9084), .Z(n8055) );
HS65_LH_NOR2X5 U6242 ( .A(n9075), .B(n8960), .Z(n2941) );
HS65_LL_IVX4 U6243 ( .A(n9075), .Z(n2942) );
HS65_LH_NAND2X7 U6244 ( .A(n9004), .B(n9209), .Z(n6106) );
HS65_LH_IVX7 U6245 ( .A(\u_DataPath/from_mem_data_out_i [5]), .Z(n3331) );
HS65_LH_NAND2X7 U6248 ( .A(n8944), .B(n9213), .Z(n6110) );
HS65_LH_NAND2X7 U6250 ( .A(n8943), .B(n9210), .Z(n6028) );
HS65_LL_IVX7 U6251 ( .A(n8960), .Z(n8139) );
HS65_LH_IVX9 U6253 ( .A(n9068), .Z(n7695) );
HS65_LH_NAND2X7 U6254 ( .A(n9267), .B(n9228), .Z(n5788) );
HS65_LH_NAND2X7 U6255 ( .A(n2733), .B(\u_DataPath/immediate_ext_dec_i [11]),
.Z(n8050) );
HS65_LH_IVX9 U6258 ( .A(Data_out_fromRAM[7]), .Z(n8302) );
HS65_LL_AOI21X2 U6259 ( .A(n7852), .B(n7853), .C(n7862), .Z(
\u_DataPath/u_exmemreg/N78 ) );
HS65_LL_NAND3AX6 U6260 ( .A(n5680), .B(\u_DataPath/cw_to_ex_i [19]), .C(
n4834), .Z(n5164) );
HS65_LH_OAI12X3 U6261 ( .A(n9190), .B(n9028), .C(n8340), .Z(
\u_DataPath/dataOut_exe_i [13]) );
HS65_LL_NAND4ABX6 U6263 ( .A(n4791), .B(n4790), .C(n4789), .D(n4788), .Z(
n4792) );
HS65_LL_NAND2X4 U6264 ( .A(n4370), .B(n8469), .Z(n4455) );
HS65_LL_NAND2AX4 U6267 ( .A(n5282), .B(n5281), .Z(n5699) );
HS65_LL_NOR2AX3 U6268 ( .A(n4098), .B(n4097), .Z(n8477) );
HS65_LL_NAND2AX4 U6270 ( .A(n3744), .B(n3743), .Z(n3745) );
HS65_LH_OAI12X3 U6271 ( .A(n9189), .B(n8853), .C(n8290), .Z(
\u_DataPath/dataOut_exe_i [12]) );
HS65_LH_OAI12X3 U6272 ( .A(n9189), .B(n8887), .C(n8413), .Z(
\u_DataPath/dataOut_exe_i [5]) );
HS65_LL_AOI22X1 U6278 ( .A(n8947), .B(n9365), .C(n9187), .D(n9090), .Z(n8267) );
HS65_LH_NAND2X7 U6279 ( .A(n5285), .B(n4423), .Z(n4452) );
HS65_LH_OAI12X3 U6281 ( .A(n9189), .B(n9058), .C(n8435), .Z(
\u_DataPath/dataOut_exe_i [4]) );
HS65_LL_CNIVX3 U6282 ( .A(n8466), .Z(n5680) );
HS65_LH_NAND2X7 U6283 ( .A(n5643), .B(n3809), .Z(n3810) );
HS65_LL_NAND3X2 U6286 ( .A(n5210), .B(n3505), .C(n3495), .Z(n3507) );
HS65_LHS_XNOR2X6 U6287 ( .A(n5265), .B(n5264), .Z(n5266) );
HS65_LHS_XNOR2X6 U6288 ( .A(n3808), .B(n3807), .Z(n3809) );
HS65_LLS_XNOR2X3 U6289 ( .A(n3741), .B(n3740), .Z(n3742) );
HS65_LL_NAND2X4 U6290 ( .A(n3612), .B(n3611), .Z(n3626) );
HS65_LH_CNIVX3 U6291 ( .A(n8467), .Z(n4789) );
HS65_LH_OAI12X3 U6292 ( .A(n3690), .B(n2859), .C(n3689), .Z(n3691) );
HS65_LLS_XOR2X3 U6293 ( .A(n4056), .B(n4055), .Z(n4057) );
HS65_LH_NOR2AX3 U6294 ( .A(n4879), .B(n4931), .Z(n4932) );
HS65_LL_OAI21X2 U6296 ( .A(n3391), .B(n5633), .C(n3390), .Z(n3392) );
HS65_LL_OA112X4 U6299 ( .A(n5152), .B(n4830), .C(n4831), .D(n2926), .Z(n7848) );
HS65_LL_OAI21X3 U6300 ( .A(n4420), .B(n5633), .C(n4419), .Z(n4421) );
HS65_LL_NAND2X2 U6301 ( .A(n3563), .B(n3562), .Z(n3564) );
HS65_LL_NAND3X2 U6302 ( .A(n5115), .B(n5114), .C(n5113), .Z(n5116) );
HS65_LH_OAI21X3 U6303 ( .A(n3753), .B(n5633), .C(n3752), .Z(n3754) );
HS65_LL_OAI21X3 U6304 ( .A(n5530), .B(n5633), .C(n2892), .Z(n3516) );
HS65_LH_NAND2X7 U6305 ( .A(n4882), .B(n4881), .Z(n4883) );
HS65_LL_OA12X18 U6306 ( .A(n2929), .B(n3815), .C(n2895), .Z(n5633) );
HS65_LL_AOI12X2 U6307 ( .A(n4309), .B(n5195), .C(n4308), .Z(n4310) );
HS65_LH_IVX7 U6308 ( .A(n5195), .Z(n5196) );
HS65_LL_NAND2X2 U6309 ( .A(n5483), .B(n5482), .Z(n5490) );
HS65_LH_NOR3X4 U6312 ( .A(n3592), .B(n3591), .C(n3590), .Z(n3612) );
HS65_LH_NOR2X5 U6313 ( .A(n4088), .B(n4087), .Z(n4089) );
HS65_LH_NAND2X4 U6314 ( .A(n4845), .B(n3617), .Z(n3563) );
HS65_LH_NOR3X4 U6315 ( .A(n4403), .B(n4402), .C(n4401), .Z(n4404) );
HS65_LH_AOI21X2 U6316 ( .A(n6123), .B(n6122), .C(n6121), .Z(n8437) );
HS65_LH_NOR2AX3 U6320 ( .A(n4235), .B(n4234), .Z(n4236) );
HS65_LL_NOR2X2 U6321 ( .A(n5060), .B(n5059), .Z(n5070) );
HS65_LH_OAI21X3 U6322 ( .A(n4119), .B(n4855), .C(n3523), .Z(n3542) );
HS65_LL_NOR3X1 U6323 ( .A(n3883), .B(n3882), .C(n3881), .Z(n3884) );
HS65_LL_NOR2X2 U6324 ( .A(n5481), .B(n5480), .Z(n5483) );
HS65_LH_OAI21X3 U6325 ( .A(n5226), .B(n4855), .C(n3914), .Z(n3929) );
HS65_LH_OAI12X3 U6326 ( .A(n4921), .B(n3815), .C(n4920), .Z(n4922) );
HS65_LH_NOR2AX3 U6328 ( .A(n4086), .B(n4085), .Z(n4087) );
HS65_LL_NAND3X3 U6329 ( .A(n4780), .B(n4779), .C(n4778), .Z(n4781) );
HS65_LH_AOI12X2 U6330 ( .A(n4043), .B(n4879), .C(n4042), .Z(n4044) );
HS65_LH_NOR2X6 U6331 ( .A(n4844), .B(n4843), .Z(n5153) );
HS65_LH_NAND2X2 U6333 ( .A(n5285), .B(n5284), .Z(n5597) );
HS65_LH_OAI21X3 U6334 ( .A(n4744), .B(n5656), .C(n4272), .Z(n4273) );
HS65_LL_NAND3X2 U6336 ( .A(n3678), .B(n3677), .C(n3676), .Z(n3679) );
HS65_LH_NAND2X4 U6340 ( .A(n3618), .B(n4879), .Z(n3493) );
HS65_LL_OA12X4 U6341 ( .A(n3816), .B(n3370), .C(n3369), .Z(n2895) );
HS65_LH_NAND3X3 U6342 ( .A(n4179), .B(n4178), .C(n4177), .Z(n4204) );
HS65_LH_AOI21X2 U6343 ( .A(n5234), .B(n4765), .C(n4354), .Z(n4360) );
HS65_LL_OAI12X2 U6344 ( .A(n5102), .B(n5101), .C(n5100), .Z(n5111) );
HS65_LH_IVX9 U6345 ( .A(n3589), .Z(n4895) );
HS65_LH_OAI12X3 U6346 ( .A(n3462), .B(n5621), .C(n3461), .Z(n3463) );
HS65_LH_NAND2X4 U6348 ( .A(n3426), .B(n4504), .Z(n4607) );
HS65_LH_OAI21X3 U6350 ( .A(n4954), .B(n3962), .C(n3961), .Z(n3978) );
HS65_LH_OAI21X3 U6352 ( .A(n4220), .B(n4319), .C(n4219), .Z(n4221) );
HS65_LH_OAI21X3 U6353 ( .A(n3975), .B(n5656), .C(n3974), .Z(n3976) );
HS65_LH_NAND3AX6 U6357 ( .A(n5664), .B(n5663), .C(n5662), .Z(n5665) );
HS65_LH_NAND2X7 U6358 ( .A(n4149), .B(n4162), .Z(n5614) );
HS65_LH_NOR3X3 U6359 ( .A(n5089), .B(n4458), .C(n4457), .Z(n3845) );
HS65_LL_OAI12X2 U6361 ( .A(n5018), .B(n5017), .C(n5016), .Z(n5019) );
HS65_LH_OAI21X3 U6362 ( .A(n5182), .B(n5226), .C(n3647), .Z(n3681) );
HS65_LH_CNIVX3 U6363 ( .A(n5577), .Z(n5581) );
HS65_LH_OAI21X3 U6364 ( .A(n4954), .B(n4953), .C(n4952), .Z(n4957) );
HS65_LH_OAI21X3 U6365 ( .A(n5177), .B(n4842), .C(n4432), .Z(n4433) );
HS65_LH_NAND2X7 U6369 ( .A(n4051), .B(n4916), .Z(n4052) );
HS65_LH_NAND2X5 U6370 ( .A(n6123), .B(n4381), .Z(n4135) );
HS65_LH_NOR2AX3 U6371 ( .A(n4072), .B(n4071), .Z(n4073) );
HS65_LH_AOI21X2 U6373 ( .A(n4951), .B(n5142), .C(n3859), .Z(n3885) );
HS65_LH_NAND2AX7 U6374 ( .A(n4121), .B(n4384), .Z(n4388) );
HS65_LL_NOR2X2 U6375 ( .A(n3375), .B(n4419), .Z(n3381) );
HS65_LH_IVX9 U6376 ( .A(n8234), .Z(\u_DataPath/branch_target_i [31]) );
HS65_LH_NAND2X7 U6377 ( .A(n3557), .B(n3556), .Z(n4816) );
HS65_LH_OAI12X3 U6378 ( .A(n5200), .B(n4842), .C(n4841), .Z(n4843) );
HS65_LH_NAND3X3 U6379 ( .A(n3917), .B(n3916), .C(n3915), .Z(n3918) );
HS65_LH_NOR3X3 U6380 ( .A(n4581), .B(n5152), .C(n4025), .Z(n4026) );
HS65_LH_OAI21X3 U6381 ( .A(n3584), .B(n3101), .C(n3583), .Z(n3591) );
HS65_LH_CNIVX3 U6382 ( .A(n5486), .Z(n5305) );
HS65_LH_NAND2X4 U6383 ( .A(n5174), .B(n5229), .Z(n3827) );
HS65_LH_IVX9 U6384 ( .A(n4025), .Z(n4504) );
HS65_LH_OAI21X3 U6386 ( .A(n4737), .B(n5656), .C(n4392), .Z(n4402) );
HS65_LH_NOR2X5 U6387 ( .A(n3762), .B(n3599), .Z(n3600) );
HS65_LH_NOR3X1 U6388 ( .A(n5476), .B(n5511), .C(n5475), .Z(n5477) );
HS65_LH_NAND2X4 U6389 ( .A(n4887), .B(n4873), .Z(n4124) );
HS65_LL_NOR3X1 U6390 ( .A(n4777), .B(n4776), .C(n4775), .Z(n4778) );
HS65_LH_AOI22X3 U6391 ( .A(n4887), .B(n4839), .C(n4951), .D(n4835), .Z(n3842) );
HS65_LL_NAND2AX4 U6393 ( .A(n3476), .B(n3475), .Z(n4928) );
HS65_LH_AOI22X3 U6394 ( .A(n5144), .B(n4616), .C(n4887), .D(n4007), .Z(n4008) );
HS65_LH_AOI22X3 U6395 ( .A(n5229), .B(n4176), .C(n5618), .D(n4614), .Z(n4009) );
HS65_LL_AOI22X1 U6396 ( .A(\sub_x_53/A[30] ), .B(n4493), .C(n5672), .D(n4492), .Z(n5704) );
HS65_LH_IVX9 U6397 ( .A(n4420), .Z(n5631) );
HS65_LH_OAI21X3 U6398 ( .A(n5653), .B(n5652), .C(n5651), .Z(n5664) );
HS65_LH_AOI21X2 U6399 ( .A(n5659), .B(n5658), .C(n5657), .Z(n5663) );
HS65_LH_OAI21X3 U6400 ( .A(n4749), .B(n5656), .C(n4461), .Z(n4471) );
HS65_LH_NAND2X4 U6401 ( .A(n4951), .B(n5143), .Z(n4466) );
HS65_LHS_XNOR2X6 U6403 ( .A(n4478), .B(n4632), .Z(n4479) );
HS65_LHS_XOR2X6 U6404 ( .A(n3853), .B(n3815), .Z(n3854) );
HS65_LH_AOI21X2 U6405 ( .A(n3505), .B(n5211), .C(n3504), .Z(n3506) );
HS65_LL_OAI112X1 U6406 ( .A(n4954), .B(n4070), .C(n4069), .D(n4068), .Z(
n4071) );
HS65_LH_AOI21X2 U6407 ( .A(n4491), .B(n4508), .C(n4263), .Z(n4264) );
HS65_LH_OAI21X3 U6408 ( .A(n4740), .B(n5656), .C(n4058), .Z(n4076) );
HS65_LL_IVX4 U6409 ( .A(n3894), .Z(n4916) );
HS65_LH_NAND3X3 U6410 ( .A(n5509), .B(n4705), .C(n4704), .Z(n4706) );
HS65_LL_AOI12X2 U6411 ( .A(n4937), .B(n4887), .C(n2901), .Z(n4555) );
HS65_LH_OAI21X3 U6412 ( .A(n4439), .B(n4700), .C(n4438), .Z(n4440) );
HS65_LH_NOR2X6 U6414 ( .A(n3878), .B(n3877), .Z(n5204) );
HS65_LH_NAND2X5 U6416 ( .A(n5618), .B(n5206), .Z(n4856) );
HS65_LH_OAI12X3 U6417 ( .A(n4499), .B(n4498), .C(n4836), .Z(n4511) );
HS65_LH_IVX9 U6418 ( .A(n4614), .Z(n5226) );
HS65_LH_OAI21X3 U6420 ( .A(n3534), .B(n5656), .C(n3533), .Z(n3541) );
HS65_LL_NOR2X2 U6421 ( .A(n4992), .B(n4977), .Z(n5115) );
HS65_LH_OAI21X3 U6422 ( .A(n4117), .B(n4838), .C(n4079), .Z(n4349) );
HS65_LH_NAND2X4 U6423 ( .A(n4951), .B(n4937), .Z(n3986) );
HS65_LH_NAND2X5 U6424 ( .A(n4836), .B(n4148), .Z(n4162) );
HS65_LH_OAI21X3 U6425 ( .A(n5188), .B(n5656), .C(n5187), .Z(n5189) );
HS65_LH_NAND2X4 U6427 ( .A(n4951), .B(n4950), .Z(n4952) );
HS65_LH_AOI22X3 U6428 ( .A(n5234), .B(n4764), .C(n5144), .D(n4937), .Z(n4151) );
HS65_LL_NAND2X4 U6429 ( .A(n4037), .B(n3480), .Z(n3935) );
HS65_LH_NAND2AX7 U6430 ( .A(n4946), .B(n2898), .Z(n4947) );
HS65_LH_IVX9 U6431 ( .A(n4919), .Z(n3282) );
HS65_LL_NAND3X3 U6432 ( .A(n3985), .B(n3984), .C(n3983), .Z(n4937) );
HS65_LH_NAND2X4 U6433 ( .A(n5659), .B(n4872), .Z(n3583) );
HS65_LH_AOI21X2 U6434 ( .A(n3737), .B(n5607), .C(n3736), .Z(n3738) );
HS65_LH_AND2X4 U6436 ( .A(n2733), .B(\u_DataPath/toPC2_i [30]), .Z(
\u_DataPath/branch_target_i [30]) );
HS65_LL_NAND2X2 U6437 ( .A(n3875), .B(n3876), .Z(n3402) );
HS65_LH_IVX9 U6439 ( .A(n4513), .Z(n5658) );
HS65_LH_NOR2X6 U6440 ( .A(n4255), .B(n4254), .Z(n4955) );
HS65_LL_NAND2AX4 U6441 ( .A(n3458), .B(n3457), .Z(n5174) );
HS65_LH_OAI21X3 U6442 ( .A(n5656), .B(n5141), .C(n5140), .Z(n5149) );
HS65_LL_NAND3X2 U6443 ( .A(n3960), .B(n3959), .C(n3958), .Z(n4560) );
HS65_LH_NAND2X4 U6444 ( .A(n5661), .B(n5617), .Z(n3761) );
HS65_LH_NAND2X4 U6448 ( .A(n4516), .B(n4872), .Z(n4080) );
HS65_LH_NAND2X2 U6449 ( .A(n4887), .B(n4886), .Z(n4888) );
HS65_LH_OAI12X3 U6451 ( .A(n4681), .B(n4680), .C(n4679), .Z(n4689) );
HS65_LH_AOI21X2 U6452 ( .A(n5618), .B(n4393), .C(n3532), .Z(n3533) );
HS65_LH_NAND2X2 U6453 ( .A(n3426), .B(n5660), .Z(n4519) );
HS65_LH_OAI12X3 U6454 ( .A(n4575), .B(n4574), .C(n4573), .Z(n4576) );
HS65_LH_AOI21X2 U6455 ( .A(n4017), .B(n4016), .C(n5466), .Z(n4018) );
HS65_LH_NAND2X4 U6456 ( .A(n5144), .B(n5142), .Z(n4467) );
HS65_LH_AND2X4 U6457 ( .A(n5234), .B(n3451), .Z(n3452) );
HS65_LL_AO12X4 U6461 ( .A(n5274), .B(n3374), .C(n3373), .Z(n5630) );
HS65_LH_AOI21X2 U6462 ( .A(n5582), .B(n5580), .C(n5013), .Z(n5017) );
HS65_LL_NOR2AX3 U6463 ( .A(n3921), .B(n3671), .Z(n4609) );
HS65_LH_IVX9 U6464 ( .A(n8238), .Z(\u_DataPath/branch_target_i [29]) );
HS65_LH_NAND2X5 U6465 ( .A(n3426), .B(n4120), .Z(n4384) );
HS65_LL_OAI12X2 U6466 ( .A(n5081), .B(n5011), .C(n5010), .Z(n5020) );
HS65_LH_AOI22X3 U6467 ( .A(n5131), .B(n5142), .C(n4942), .D(n3872), .Z(n3843) );
HS65_LH_OAI12X3 U6468 ( .A(n3969), .B(n3757), .C(n5672), .Z(n3799) );
HS65_LH_IVX4 U6469 ( .A(n3876), .Z(n3877) );
HS65_LH_NAND2X4 U6470 ( .A(n5443), .B(n3630), .Z(n3638) );
HS65_LL_IVX2 U6471 ( .A(n4014), .Z(n3246) );
HS65_LH_NAND3X2 U6472 ( .A(n4852), .B(n4851), .C(n5178), .Z(n4853) );
HS65_LH_NAND2AX7 U6473 ( .A(n3520), .B(n3519), .Z(n4872) );
HS65_LH_OAI21X2 U6475 ( .A(n2873), .B(n5179), .C(n5178), .Z(n4527) );
HS65_LL_NOR2X2 U6476 ( .A(n3483), .B(n4629), .Z(n3484) );
HS65_LL_NOR2X3 U6477 ( .A(n3863), .B(n3862), .Z(n4435) );
HS65_LL_NAND2X4 U6478 ( .A(n3586), .B(n3585), .Z(n4120) );
HS65_LH_AOI21X2 U6479 ( .A(n5275), .B(n5274), .C(n5273), .Z(n5276) );
HS65_LL_NOR2X2 U6481 ( .A(n4257), .B(n4256), .Z(n4953) );
HS65_LH_OAI12X3 U6482 ( .A(n4015), .B(n4011), .C(n4013), .Z(n3364) );
HS65_LL_NAND3X3 U6483 ( .A(n4591), .B(n3674), .C(n3673), .Z(n4176) );
HS65_LL_NAND2X4 U6484 ( .A(n5304), .B(n3893), .Z(n5522) );
HS65_LH_NAND3X3 U6485 ( .A(n3531), .B(n5178), .C(n3530), .Z(n3532) );
HS65_LL_NOR3X1 U6486 ( .A(n3434), .B(n3982), .C(n3433), .Z(n5172) );
HS65_LH_NAND2X7 U6487 ( .A(n5009), .B(n5507), .Z(n5081) );
HS65_LH_NAND2X4 U6488 ( .A(n5270), .B(n5467), .Z(n5082) );
HS65_LL_NOR2X2 U6489 ( .A(n4524), .B(n3834), .Z(n3835) );
HS65_LH_OAI12X3 U6491 ( .A(n4725), .B(n4795), .C(n3759), .Z(n4254) );
HS65_LH_NAND3X3 U6492 ( .A(n3972), .B(n3971), .C(n3970), .Z(n3973) );
HS65_LH_OAI21X3 U6494 ( .A(n4197), .B(n4196), .C(n4195), .Z(n4198) );
HS65_LH_OAI21X3 U6495 ( .A(n4798), .B(n4797), .C(n5131), .Z(n4799) );
HS65_LH_IVX4 U6497 ( .A(n3841), .Z(n3781) );
HS65_LH_NAND2X5 U6498 ( .A(n5434), .B(n4408), .Z(n4413) );
HS65_LH_NAND2X5 U6499 ( .A(n3474), .B(n3359), .Z(n4015) );
HS65_LH_AOI21X6 U6500 ( .A(\sub_x_53/A[2] ), .B(n2864), .C(n4798), .Z(n3519)
);
HS65_LH_NAND2X4 U6502 ( .A(n4143), .B(n4099), .Z(n4104) );
HS65_LL_OAI12X3 U6503 ( .A(n2892), .B(n3515), .C(n5531), .Z(n5274) );
HS65_LH_NAND2X4 U6505 ( .A(n4013), .B(n4012), .Z(n4021) );
HS65_LH_NAND2X4 U6508 ( .A(n3733), .B(n3732), .Z(n3741) );
HS65_LL_OAI12X2 U6509 ( .A(n5269), .B(n5272), .C(n5270), .Z(n3373) );
HS65_LH_CBI4I1X5 U6510 ( .A(n4102), .B(n4099), .C(n3354), .D(n3353), .Z(
n3356) );
HS65_LH_OAI211X3 U6511 ( .A(n5652), .B(n4582), .C(n3603), .D(n3602), .Z(
n4356) );
HS65_LH_NAND2X4 U6512 ( .A(n4915), .B(n4914), .Z(n4923) );
HS65_LL_AOI12X3 U6513 ( .A(n3497), .B(n5260), .C(n3496), .Z(n4426) );
HS65_LL_NAND2AX4 U6514 ( .A(n3351), .B(n4638), .Z(n3358) );
HS65_LH_NOR2X6 U6515 ( .A(n3613), .B(n3616), .Z(n3804) );
HS65_LH_NAND2X4 U6516 ( .A(n5605), .B(n5604), .Z(n5613) );
HS65_LH_NAND2X4 U6517 ( .A(n4846), .B(n4845), .Z(n4847) );
HS65_LH_CNIVX3 U6518 ( .A(n4037), .Z(n3992) );
HS65_LH_NAND2X4 U6520 ( .A(n3474), .B(n4544), .Z(n3457) );
HS65_LH_NAND2X2 U6521 ( .A(n4572), .B(n4571), .Z(n4577) );
HS65_LH_OAI12X3 U6522 ( .A(n4581), .B(n4580), .C(n3529), .Z(n4804) );
HS65_LH_AOI21X6 U6523 ( .A(\sub_x_53/A[2] ), .B(n4544), .C(n4541), .Z(n3876)
);
HS65_LH_CNIVX3 U6524 ( .A(n4927), .Z(n3937) );
HS65_LH_NAND2X4 U6525 ( .A(n5275), .B(n5271), .Z(n5277) );
HS65_LH_NAND2X4 U6526 ( .A(n4507), .B(n4516), .Z(n4608) );
HS65_LH_IVX7 U6527 ( .A(n3491), .Z(n3483) );
HS65_LH_NAND2X4 U6528 ( .A(n3833), .B(n3984), .Z(n3770) );
HS65_LH_CNIVX3 U6529 ( .A(n3907), .Z(n3664) );
HS65_LH_IVX9 U6533 ( .A(n3969), .Z(n4134) );
HS65_LH_NOR2X3 U6534 ( .A(n4795), .B(n4660), .Z(n3640) );
HS65_LH_OAI21X3 U6535 ( .A(n4981), .B(n4795), .C(n3603), .Z(n3551) );
HS65_LH_AOI21X2 U6536 ( .A(\sub_x_53/A[17] ), .B(n4588), .C(n3552), .Z(n3554) );
HS65_LL_NOR2X3 U6537 ( .A(n4725), .B(n5422), .Z(n5499) );
HS65_LH_AOI21X2 U6540 ( .A(n5192), .B(n5364), .C(n5500), .Z(n5365) );
HS65_LH_IVX4 U6542 ( .A(n5271), .Z(n4246) );
HS65_LL_NAND2X2 U6544 ( .A(n5516), .B(n5297), .Z(n5334) );
HS65_LL_OAI12X3 U6545 ( .A(n5947), .B(n5950), .C(n5949), .Z(n6055) );
HS65_LH_NAND2X4 U6546 ( .A(n4107), .B(n4106), .Z(n4111) );
HS65_LH_IVX9 U6548 ( .A(n5342), .Z(n5569) );
HS65_LH_NAND2X4 U6549 ( .A(\lte_x_59/B[21] ), .B(n4551), .Z(n3550) );
HS65_LLS_XOR2X3 U6550 ( .A(n5951), .B(n2876), .Z(
\u_DataPath/u_execute/resAdd1_i [29]) );
HS65_LH_NAND2X4 U6552 ( .A(n4700), .B(n4699), .Z(n5356) );
HS65_LH_OAI12X3 U6553 ( .A(n4425), .B(n4371), .C(n4373), .Z(n5606) );
HS65_LH_NAND2X4 U6555 ( .A(n4701), .B(n5418), .Z(n5292) );
HS65_LH_NOR2X3 U6559 ( .A(n5311), .B(n5299), .Z(n5540) );
HS65_LH_NAND2X4 U6561 ( .A(\lte_x_59/B[5] ), .B(n4588), .Z(n3518) );
HS65_LL_NOR2X3 U6562 ( .A(n4622), .B(n4630), .Z(n3491) );
HS65_LH_NOR2X6 U6563 ( .A(n4880), .B(n4876), .Z(n4037) );
HS65_LH_CNIVX3 U6564 ( .A(n5624), .Z(n3713) );
HS65_LH_OAI12X3 U6566 ( .A(n5605), .B(n3731), .C(n3733), .Z(n3498) );
HS65_LH_NAND2X4 U6569 ( .A(\lte_x_59/B[6] ), .B(n4544), .Z(n4462) );
HS65_LH_OAI22X3 U6570 ( .A(n5179), .B(n2865), .C(n2848), .D(n4165), .Z(n4166) );
HS65_LL_NOR2X2 U6571 ( .A(n5310), .B(n5095), .Z(n5552) );
HS65_LH_IVX9 U6573 ( .A(n3575), .Z(n5192) );
HS65_LH_OAI22X3 U6574 ( .A(n4682), .B(n4795), .C(n5129), .D(n5031), .Z(n4131) );
HS65_LH_IVX9 U6575 ( .A(\sub_x_53/A[29] ), .Z(n4725) );
HS65_LH_NAND2X4 U6576 ( .A(n4675), .B(n4674), .Z(n5517) );
HS65_LH_NAND2X4 U6577 ( .A(n4663), .B(n3330), .Z(n4648) );
HS65_LH_NAND2X4 U6578 ( .A(\lte_x_59/B[16] ), .B(n4587), .Z(n3910) );
HS65_LH_NOR2X6 U6579 ( .A(\lte_x_59/B[15] ), .B(n5062), .Z(n3932) );
HS65_LH_IVX9 U6580 ( .A(n4244), .Z(n5275) );
HS65_LH_NAND2X7 U6581 ( .A(\lte_x_59/B[15] ), .B(n5062), .Z(n3934) );
HS65_LH_NOR2X5 U6582 ( .A(n4341), .B(n4939), .Z(n4027) );
HS65_LH_NOR2AX3 U6583 ( .A(n4587), .B(n2848), .Z(n3670) );
HS65_LL_OAI12X2 U6586 ( .A(n4144), .B(n4481), .C(n4143), .Z(n4640) );
HS65_LH_OAI12X3 U6587 ( .A(n4573), .B(n4570), .C(n4572), .Z(n3317) );
HS65_LH_NAND2X4 U6588 ( .A(n4882), .B(n3855), .Z(n3856) );
HS65_LH_CNIVX3 U6589 ( .A(n4081), .Z(n4082) );
HS65_LH_NOR2X6 U6590 ( .A(n4371), .B(n4374), .Z(n5608) );
HS65_LL_NOR2X3 U6592 ( .A(n3515), .B(n5530), .Z(n5271) );
HS65_LH_IVX9 U6593 ( .A(n3814), .Z(n4051) );
HS65_LH_CNIVX3 U6596 ( .A(n5503), .Z(n5504) );
HS65_LL_NOR2X3 U6597 ( .A(n3846), .B(n4081), .Z(n4930) );
HS65_LH_NAND2X2 U6599 ( .A(\lte_x_59/B[15] ), .B(n4588), .Z(n3644) );
HS65_LL_AOI12X3 U6600 ( .A(\sub_x_53/A[27] ), .B(n3385), .C(n5343), .Z(n5582) );
HS65_LH_IVX9 U6601 ( .A(n3560), .Z(n4845) );
HS65_LH_NAND2X4 U6602 ( .A(\lte_x_59/B[14] ), .B(n4587), .Z(n4062) );
HS65_LH_IVX9 U6604 ( .A(n5207), .Z(n5621) );
HS65_LL_NOR2X2 U6606 ( .A(n3698), .B(n5627), .Z(n3379) );
HS65_LH_OAI22X4 U6608 ( .A(n7917), .B(n8449), .C(n7916), .D(n8448), .Z(
\u_DataPath/data_read_ex_1_i [29]) );
HS65_LH_OAI22X4 U6609 ( .A(n7917), .B(n8415), .C(n7916), .D(n8414), .Z(
\u_DataPath/data_read_ex_1_i [5]) );
HS65_LH_OAI22X4 U6610 ( .A(n7917), .B(n8412), .C(n7916), .D(n8411), .Z(
\u_DataPath/data_read_ex_1_i [20]) );
HS65_LH_OAI22X4 U6611 ( .A(n7917), .B(n8457), .C(n7916), .D(n8455), .Z(
\u_DataPath/data_read_ex_1_i [18]) );
HS65_LH_OAI22X4 U6612 ( .A(n7917), .B(n8422), .C(n7916), .D(n8421), .Z(
\u_DataPath/data_read_ex_1_i [31]) );
HS65_LH_OAI22X4 U6613 ( .A(n7917), .B(n8408), .C(n7916), .D(n8407), .Z(
\u_DataPath/data_read_ex_1_i [17]) );
HS65_LH_OAI22X4 U6614 ( .A(n7917), .B(n7932), .C(n7916), .D(n8418), .Z(
\u_DataPath/data_read_ex_1_i [28]) );
HS65_LH_NOR2X6 U6615 ( .A(\lte_x_59/B[18] ), .B(n3371), .Z(n4244) );
HS65_LH_NAND2X4 U6616 ( .A(n5130), .B(n5088), .Z(n5318) );
HS65_LL_NAND2X4 U6617 ( .A(n5249), .B(n3788), .Z(n5624) );
HS65_LL_NOR2AX3 U6621 ( .A(n2848), .B(n4147), .Z(n4630) );
HS65_LH_NAND2X4 U6622 ( .A(n9188), .B(n9093), .Z(n7866) );
HS65_LL_NAND2X4 U6627 ( .A(n4726), .B(n4966), .Z(n5572) );
HS65_LH_NAND2X5 U6629 ( .A(n2849), .B(n5231), .Z(n5256) );
HS65_LH_OAI21X3 U6630 ( .A(n3352), .B(n5179), .C(n4459), .Z(n4460) );
HS65_LH_NAND2X4 U6631 ( .A(n2851), .B(n7627), .Z(n4229) );
HS65_LH_NOR2X6 U6633 ( .A(\lte_x_59/B[21] ), .B(n3377), .Z(n4407) );
HS65_LH_IVX9 U6634 ( .A(n3547), .Z(n4711) );
HS65_LH_NAND2X4 U6635 ( .A(\sub_x_53/A[17] ), .B(n2870), .Z(n5531) );
HS65_LL_AOI12X2 U6639 ( .A(n6117), .B(n6119), .C(n5943), .Z(n5950) );
HS65_LL_NOR2X3 U6640 ( .A(\lte_x_59/B[5] ), .B(n4665), .Z(n4144) );
HS65_LL_NOR2X5 U6641 ( .A(n4863), .B(n4838), .Z(n4887) );
HS65_LH_NOR2X3 U6642 ( .A(n4147), .B(n2848), .Z(n5310) );
HS65_LL_NOR2X3 U6643 ( .A(\lte_x_59/B[14] ), .B(n3366), .Z(n4913) );
HS65_LH_NAND2X5 U6644 ( .A(\sub_x_53/A[23] ), .B(n5417), .Z(n5509) );
HS65_LH_NOR4ABX2 U6645 ( .A(n6995), .B(n6994), .C(n6993), .D(n6992), .Z(
n8338) );
HS65_LH_NOR4ABX2 U6646 ( .A(n7035), .B(n7034), .C(n7033), .D(n7032), .Z(
n8331) );
HS65_LH_NOR4ABX2 U6647 ( .A(n7055), .B(n7054), .C(n7053), .D(n7052), .Z(
n8327) );
HS65_LH_NOR4ABX2 U6648 ( .A(n7075), .B(n7074), .C(n7073), .D(n7072), .Z(
n8344) );
HS65_LH_NOR4ABX2 U6649 ( .A(n7015), .B(n7014), .C(n7013), .D(n7012), .Z(
n8349) );
HS65_LH_NOR4ABX2 U6650 ( .A(n6361), .B(n6360), .C(n6359), .D(n6358), .Z(
n8386) );
HS65_LH_NOR4ABX2 U6651 ( .A(n6766), .B(n6765), .C(n6764), .D(n6763), .Z(
n8322) );
HS65_LL_NOR2X6 U6653 ( .A(n3151), .B(n3150), .Z(\lte_x_59/B[26] ) );
HS65_LH_IVX9 U6655 ( .A(n5567), .Z(n3384) );
HS65_LH_IVX9 U6656 ( .A(n5040), .Z(n4665) );
HS65_LL_NAND2X4 U6660 ( .A(n8383), .B(n3237), .Z(n4969) );
HS65_LHS_XOR2X3 U6665 ( .A(n5956), .B(n5955), .Z(
\u_DataPath/u_execute/resAdd1_i [27]) );
HS65_LL_OAI12X3 U6668 ( .A(n5748), .B(n5751), .C(n5750), .Z(n5908) );
HS65_LH_OAI211X4 U6669 ( .A(n9243), .B(n8880), .C(n8295), .D(n9086), .Z(
\u_DataPath/from_mem_data_out_i [10]) );
HS65_LL_OAI12X2 U6672 ( .A(n8964), .B(n8088), .C(n8829), .Z(
\u_DataPath/cw_to_ex_i [4]) );
HS65_LL_OR2X9 U6674 ( .A(n3100), .B(n3099), .Z(n3101) );
HS65_LH_NAND2X4 U6676 ( .A(n3352), .B(\lte_x_59/B[4] ), .Z(n5387) );
HS65_LH_IVX9 U6677 ( .A(\sub_x_53/A[2] ), .Z(n5130) );
HS65_LH_NAND2X7 U6678 ( .A(\lte_x_59/B[1] ), .B(n4805), .Z(n4824) );
HS65_LH_NOR2X5 U6679 ( .A(\lte_x_59/B[3] ), .B(n5321), .Z(n3488) );
HS65_LL_NOR2X6 U6680 ( .A(n3091), .B(n3090), .Z(\lte_x_59/B[14] ) );
HS65_LH_NOR2X5 U6681 ( .A(n9167), .B(n8104), .Z(\u_DataPath/cw_to_ex_i [19])
);
HS65_LH_IVX7 U6682 ( .A(n5136), .Z(n5123) );
HS65_LH_NAND2X4 U6683 ( .A(n5652), .B(n5654), .Z(n5362) );
HS65_LL_IVX7 U6684 ( .A(\lte_x_59/B[8] ), .Z(n4682) );
HS65_LL_OAI12X3 U6688 ( .A(n8176), .B(n3409), .C(n3408), .Z(n3410) );
HS65_LH_AO22X9 U6689 ( .A(n8820), .B(n9138), .C(n9326), .D(n9153), .Z(
\u_DataPath/jaddr_i [23]) );
HS65_LL_NAND2X5 U6690 ( .A(n4191), .B(n4190), .Z(n7623) );
HS65_LH_IVX9 U6691 ( .A(n5048), .Z(n3365) );
HS65_LH_AO22X9 U6692 ( .A(n8819), .B(n9252), .C(n9327), .D(n9153), .Z(
\u_DataPath/jaddr_i [24]) );
HS65_LL_OAI22X3 U6693 ( .A(n3264), .B(\u_DataPath/dataOut_exe_i [19]), .C(
n8323), .D(n3409), .Z(n3186) );
HS65_LL_OAI22X3 U6695 ( .A(n3264), .B(\u_DataPath/dataOut_exe_i [18]), .C(
n8387), .D(n3409), .Z(n3085) );
HS65_LH_IVX4 U6696 ( .A(\u_DataPath/u_idexreg/N15 ), .Z(n8072) );
HS65_LL_OAI12X6 U6697 ( .A(n3255), .B(n3254), .C(n3253), .Z(n4674) );
HS65_LHS_XNOR2X3 U6698 ( .A(n7119), .B(n7122), .Z(
\u_DataPath/u_execute/link_value_i [26]) );
HS65_LL_OAI12X3 U6699 ( .A(n8389), .B(n3409), .C(n3089), .Z(n3090) );
HS65_LL_NAND2AX7 U6700 ( .A(n2923), .B(n3281), .Z(n5061) );
HS65_LH_AO22X9 U6702 ( .A(n8818), .B(n9252), .C(n9318), .D(n9069), .Z(
\u_DataPath/immediate_ext_dec_i [15]) );
HS65_LH_IVX9 U6703 ( .A(n4534), .Z(n4431) );
HS65_LL_NAND2AX7 U6709 ( .A(n3169), .B(n3168), .Z(n5652) );
HS65_LH_AO22X9 U6711 ( .A(n8817), .B(n9138), .C(n9324), .D(n9153), .Z(
\u_DataPath/jaddr_i [21]) );
HS65_LH_AO22X9 U6712 ( .A(n8816), .B(n9138), .C(n9323), .D(n9153), .Z(
\u_DataPath/jaddr_i [20]) );
HS65_LL_NOR2X9 U6713 ( .A(n3316), .B(n3315), .Z(n5321) );
HS65_LH_BFX18 U6715 ( .A(n9086), .Z(n7913) );
HS65_LL_NAND2X5 U6716 ( .A(n3180), .B(n3179), .Z(n4699) );
HS65_LH_OAI22X6 U6717 ( .A(n3264), .B(\u_DataPath/dataOut_exe_i [20]), .C(
n8385), .D(n3409), .Z(n3176) );
HS65_LH_AOI22X3 U6720 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][8] ), .B(n6595),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[14][8] ), .D(
n7264), .Z(n6458) );
HS65_LH_AO22X9 U6722 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][4] ), .B(n7602),
.C(n7601), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][4] ), .Z(n7361)
);
HS65_LH_AOI22X3 U6723 ( .A(n7434), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][20] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][20] ), .D(n7516),
.Z(n7479) );
HS65_LH_AOI22X3 U6724 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][16] ), .B(n7585),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[1][16] ), .D(
n2889), .Z(n7544) );
HS65_LH_AOI22X3 U6726 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][6] ), .B(n7297),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[0][6] ), .D(n6942), .Z(n6487) );
HS65_LH_AOI22X3 U6728 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][27] ), .B(n7585),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[1][27] ), .D(
n2889), .Z(n7458) );
HS65_LH_AOI22X3 U6730 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][6] ), .B(n6595),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[14][6] ), .D(
n7264), .Z(n6478) );
HS65_LH_AO22X9 U6731 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][6] ), .B(n9374),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[6][6] ), .D(n7267), .Z(n6475) );
HS65_LH_AOI22X3 U6733 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][8] ), .B(n7297),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[0][8] ), .D(n6942), .Z(n6467) );
HS65_LH_AOI22X3 U6736 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][24] ), .B(n7585),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[1][24] ), .D(
n2889), .Z(n7564) );
HS65_LH_AOI22X3 U6737 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][2] ), .B(n6595),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[14][2] ), .D(
n7264), .Z(n6558) );
HS65_LH_AOI22X3 U6738 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][24] ), .B(n7415),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[10][24] ), .D(
n2891), .Z(n7561) );
HS65_LH_AOI22X3 U6739 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][2] ), .B(n7297),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[0][2] ), .D(n6942), .Z(n6567) );
HS65_LH_AOI22X3 U6740 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][2] ), .B(n7415),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[10][2] ), .D(
n6670), .Z(n6956) );
HS65_LH_AOI22X3 U6742 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][19] ), .B(n6595),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[14][19] ), .D(
n7264), .Z(n6518) );
HS65_LH_AOI22X3 U6743 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][19] ), .B(n7297),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[0][19] ), .D(
n6942), .Z(n6527) );
HS65_LH_AO22X9 U6747 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][25] ), .B(n7293),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[13][25] ), .D(
n7292), .Z(n7155) );
HS65_LH_AOI22X3 U6748 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][25] ), .B(n7265),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[11][25] ), .D(
n6363), .Z(n7145) );
HS65_LH_AOI22X3 U6750 ( .A(n7434), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][18] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][18] ), .D(n7516),
.Z(n6338) );
HS65_LH_AO22X9 U6751 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][30] ), .B(n7585),
.C(n6957), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][30] ), .Z(n7411)
);
HS65_LH_AO22X9 U6752 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][1] ), .B(n6927),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][1] ), .D(n9372), .Z(n6597) );
HS65_LH_AOI22X3 U6754 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][30] ), .B(n7586),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[7][30] ), .D(
n7587), .Z(n7414) );
HS65_LH_AOI22X3 U6755 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][1] ), .B(n6595),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[14][1] ), .D(
n7264), .Z(n6599) );
HS65_LH_AOI22X3 U6756 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][10] ), .B(n6595),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[14][10] ), .D(
n7264), .Z(n6397) );
HS65_LH_AOI22X3 U6758 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][7] ), .B(n6595),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[14][7] ), .D(
n7264), .Z(n6438) );
HS65_LH_AOI22X3 U6759 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][7] ), .B(n7297),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[0][7] ), .D(n6942), .Z(n6447) );
HS65_LH_AOI22X3 U6760 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][0] ), .B(n6595),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[14][0] ), .D(
n7264), .Z(n6417) );
HS65_LH_AOI22X3 U6761 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][12] ), .B(n7297),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[0][12] ), .D(
n6942), .Z(n6547) );
HS65_LH_AOI22X3 U6762 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][12] ), .B(n6595),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[14][12] ), .D(
n7264), .Z(n6538) );
HS65_LH_AOI22X3 U6764 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][1] ), .B(n7297),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[0][1] ), .D(n6942), .Z(n6609) );
HS65_LH_AOI22X3 U6765 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][26] ), .B(n7297),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[0][26] ), .D(
n6942), .Z(n6507) );
HS65_LH_AOI22X3 U6766 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][0] ), .B(n7297),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[0][0] ), .D(n6942), .Z(n6427) );
HS65_LH_BFX18 U6767 ( .A(n8482), .Z(n7918) );
HS65_LH_NAND2X7 U6771 ( .A(n8540), .B(n3178), .Z(n3179) );
HS65_LL_NAND4ABX3 U6772 ( .A(n8558), .B(n4713), .C(n3146), .D(n8560), .Z(
n3147) );
HS65_LH_NOR2X5 U6773 ( .A(rst), .B(n8503), .Z(
\u_DataPath/mem_writedata_out_i [8]) );
HS65_LH_NAND2X5 U6776 ( .A(n7871), .B(n7870), .Z(
\u_DataPath/mem_writedata_out_i [0]) );
HS65_LH_AO22X9 U6780 ( .A(n9254), .B(n8815), .C(n9240), .D(n8984), .Z(
\u_DataPath/pc4_to_idexreg_i [14]) );
HS65_LH_AO22X9 U6781 ( .A(n9254), .B(n8814), .C(n9240), .D(n9097), .Z(
\u_DataPath/pc4_to_idexreg_i [15]) );
HS65_LH_AO22X9 U6782 ( .A(n9254), .B(n8813), .C(n9240), .D(n8979), .Z(
\u_DataPath/pc4_to_idexreg_i [19]) );
HS65_LH_IVX9 U6783 ( .A(n5032), .Z(n3352) );
HS65_LH_AO22X9 U6784 ( .A(n9254), .B(n8812), .C(n9240), .D(n8985), .Z(
\u_DataPath/pc4_to_idexreg_i [20]) );
HS65_LL_IVX4 U6785 ( .A(n5030), .Z(n5312) );
HS65_LL_OAI12X5 U6786 ( .A(n4216), .B(n4215), .C(n4214), .Z(n5422) );
HS65_LH_NOR2X6 U6787 ( .A(n8846), .B(n3341), .Z(n3139) );
HS65_LH_AO22X9 U6788 ( .A(n9254), .B(n8811), .C(n9273), .D(n9240), .Z(
\u_DataPath/pc4_to_idexreg_i [2]) );
HS65_LH_AO22X9 U6789 ( .A(n9254), .B(n8810), .C(n9240), .D(n8970), .Z(
\u_DataPath/pc4_to_idexreg_i [3]) );
HS65_LL_AOI12X4 U6790 ( .A(n3082), .B(n3335), .C(n3334), .Z(\lte_x_59/B[5] )
);
HS65_LH_AO22X9 U6791 ( .A(n9254), .B(n8809), .C(n9240), .D(n8971), .Z(
\u_DataPath/pc4_to_idexreg_i [5]) );
HS65_LH_AO22X9 U6792 ( .A(n9254), .B(n8808), .C(n8688), .D(n9240), .Z(
\u_DataPath/pc4_to_idexreg_i [1]) );
HS65_LH_AO22X9 U6794 ( .A(n9254), .B(n8806), .C(n9240), .D(n9098), .Z(
\u_DataPath/pc4_to_idexreg_i [7]) );
HS65_LH_AO22X9 U6795 ( .A(n9254), .B(n8805), .C(n9240), .D(n9010), .Z(
\u_DataPath/pc4_to_idexreg_i [8]) );
HS65_LL_OAI12X3 U6798 ( .A(n4210), .B(n2909), .C(n4209), .Z(n4966) );
HS65_LH_AO22X9 U6802 ( .A(n9254), .B(n8803), .C(n9240), .D(n8981), .Z(
\u_DataPath/pc4_to_idexreg_i [13]) );
HS65_LH_IVX7 U6803 ( .A(n8053), .Z(n8054) );
HS65_LH_IVX7 U6805 ( .A(n8059), .Z(\u_DataPath/cw_exmem_i [9]) );
HS65_LH_NOR2AX6 U6806 ( .A(n3314), .B(n3414), .Z(n3316) );
HS65_LH_NOR2X6 U6807 ( .A(n8858), .B(n3341), .Z(n3306) );
HS65_LH_NOR2X6 U6808 ( .A(n8836), .B(n3341), .Z(n3061) );
HS65_LL_NAND2X2 U6809 ( .A(n2927), .B(n8552), .Z(n3144) );
HS65_LH_AO22X9 U6810 ( .A(n9254), .B(n8802), .C(n9240), .D(n8980), .Z(
\u_DataPath/pc4_to_idexreg_i [25]) );
HS65_LH_NAND2X7 U6811 ( .A(n3276), .B(n8523), .Z(n3277) );
HS65_LH_NOR2X6 U6814 ( .A(n8856), .B(n3403), .Z(n3266) );
HS65_LL_NAND3X2 U6815 ( .A(n3279), .B(n3280), .C(n8520), .Z(n3281) );
HS65_LH_OR2X9 U6816 ( .A(\u_DataPath/data_read_ex_1_i [10]), .B(n3341), .Z(
n3236) );
HS65_LL_NOR2X3 U6817 ( .A(n3338), .B(n7863), .Z(n4657) );
HS65_LH_NAND2AX7 U6818 ( .A(n8839), .B(n3291), .Z(n8548) );
HS65_LH_NAND2AX7 U6820 ( .A(n8866), .B(n2874), .Z(n8545) );
HS65_LL_NAND3X5 U6821 ( .A(n2879), .B(n8576), .C(n8318), .Z(n8401) );
HS65_LL_NAND2X2 U6822 ( .A(n3221), .B(n5692), .Z(n3223) );
HS65_LH_NAND2AX7 U6823 ( .A(\u_DataPath/data_read_ex_2_i [15]), .B(n2874),
.Z(n8523) );
HS65_LL_NAND2AX4 U6824 ( .A(n3301), .B(n3300), .Z(n3302) );
HS65_LH_NAND2AX7 U6825 ( .A(n8843), .B(n3291), .Z(n8532) );
HS65_LL_NOR3X1 U6826 ( .A(n4713), .B(n8538), .C(n8539), .Z(n3178) );
HS65_LH_NAND2AX7 U6827 ( .A(n8720), .B(n2874), .Z(n8540) );
HS65_LL_NOR2X2 U6828 ( .A(n3154), .B(n8555), .Z(n3155) );
HS65_LH_NAND2AX7 U6829 ( .A(n8721), .B(n3291), .Z(n8560) );
HS65_LH_NAND2AX7 U6830 ( .A(n8832), .B(n2874), .Z(n8571) );
HS65_LL_OAI22X3 U6832 ( .A(n3062), .B(n3340), .C(
\u_DataPath/dataOut_exe_i [1]), .D(n3264), .Z(n3063) );
HS65_LH_NAND2AX7 U6833 ( .A(n8718), .B(n3291), .Z(n8526) );
HS65_LH_NAND2AX7 U6834 ( .A(n8837), .B(n3291), .Z(n8529) );
HS65_LL_NAND2X7 U6835 ( .A(n2733), .B(n7902), .Z(n8443) );
HS65_LL_AOI12X2 U6836 ( .A(n3142), .B(n2866), .C(n3141), .Z(n2927) );
HS65_LL_NAND2X4 U6838 ( .A(n8703), .B(n7704), .Z(n7770) );
HS65_LH_NAND2AX7 U6839 ( .A(n8717), .B(n2874), .Z(n8543) );
HS65_LL_MUXI21X2 U6841 ( .D0(n8554), .D1(n4715), .S0(n4717), .Z(n3593) );
HS65_LH_NAND2AX7 U6842 ( .A(n8865), .B(n2874), .Z(n8517) );
HS65_LH_AOI22X4 U6843 ( .A(n8383), .B(n2866), .C(n3128), .D(n3291), .Z(n8561) );
HS65_LH_NAND2AX7 U6844 ( .A(n8723), .B(n3291), .Z(n8520) );
HS65_LH_NAND2X5 U6845 ( .A(n9084), .B(n8634), .Z(n8059) );
HS65_LL_NOR2X5 U6846 ( .A(n3313), .B(n3312), .Z(n3414) );
HS65_LL_NOR2X2 U6847 ( .A(n4188), .B(n8570), .Z(n4189) );
HS65_LL_NOR2X2 U6848 ( .A(n3206), .B(n8525), .Z(n3207) );
HS65_LH_NOR2X5 U6849 ( .A(n7673), .B(n7757), .Z(n7674) );
HS65_LH_NOR2AX3 U6852 ( .A(n4714), .B(n5693), .Z(n3221) );
HS65_LH_NAND2X7 U6853 ( .A(n3215), .B(n2896), .Z(n5691) );
HS65_LH_NAND2X4 U6854 ( .A(n4714), .B(n8569), .Z(n2909) );
HS65_LH_NOR2X5 U6855 ( .A(n3123), .B(n7671), .Z(n7672) );
HS65_LH_NOR2X6 U6858 ( .A(n7657), .B(n7757), .Z(n7767) );
HS65_LL_OAI12X12 U6859 ( .A(n3010), .B(n8148), .C(n2733), .Z(
\u_DataPath/u_decode_unit/reg_file0/N129 ) );
HS65_LH_NAND2X4 U6861 ( .A(n4714), .B(n8565), .Z(n4215) );
HS65_LL_OAI12X12 U6862 ( .A(n3009), .B(n8148), .C(n2733), .Z(
\u_DataPath/u_decode_unit/reg_file0/N92 ) );
HS65_LH_NAND2X4 U6863 ( .A(n9376), .B(n8496), .Z(n3338) );
HS65_LL_OAI12X12 U6864 ( .A(n8147), .B(n8148), .C(n2733), .Z(
\u_DataPath/u_decode_unit/reg_file0/N127 ) );
HS65_LH_NOR2X6 U6865 ( .A(n7685), .B(n7757), .Z(n7764) );
HS65_LH_NAND2X7 U6871 ( .A(n3278), .B(n3407), .Z(n3089) );
HS65_LH_NAND2X4 U6872 ( .A(n4714), .B(n8533), .Z(n3194) );
HS65_LL_NAND2X4 U6873 ( .A(n9376), .B(n8486), .Z(n3394) );
HS65_LHS_XNOR2X6 U6874 ( .A(n5869), .B(n5868), .Z(\u_DataPath/toPC2_i [16])
);
HS65_LH_NAND2X4 U6875 ( .A(n7869), .B(n8621), .Z(n7871) );
HS65_LH_NAND2X4 U6876 ( .A(n8235), .B(\u_DataPath/u_fetch/pc1/N3 ), .Z(n8044) );
HS65_LL_NOR2X2 U6877 ( .A(n8488), .B(n9401), .Z(n3301) );
HS65_LH_AND2X4 U6878 ( .A(\u_DataPath/dataOut_exe_i [15]), .B(n3407), .Z(
n3271) );
HS65_LH_NAND2X7 U6879 ( .A(n9376), .B(n8487), .Z(n3298) );
HS65_LH_IVX7 U6880 ( .A(n8280), .Z(\u_DataPath/branch_target_i [4]) );
HS65_LH_IVX7 U6881 ( .A(n8281), .Z(\u_DataPath/branch_target_i [3]) );
HS65_LH_NAND2X4 U6882 ( .A(n9376), .B(n8502), .Z(n3329) );
HS65_LHS_XNOR2X6 U6883 ( .A(n7732), .B(n7731), .Z(
\u_DataPath/u_execute/link_value_i [13]) );
HS65_LHS_XNOR2X6 U6884 ( .A(n7722), .B(n7721), .Z(
\u_DataPath/u_execute/link_value_i [15]) );
HS65_LH_IVX18 U6885 ( .A(n4548), .Z(n5648) );
HS65_LH_AOI12X2 U6887 ( .A(n6069), .B(n6071), .C(n5984), .Z(n5985) );
HS65_LHS_XNOR2X6 U6888 ( .A(n6080), .B(n6079), .Z(
\u_DataPath/u_execute/resAdd1_i [9]) );
HS65_LL_NAND2AX4 U6889 ( .A(n3034), .B(n3033), .Z(n3045) );
HS65_LL_NAND2X7 U6890 ( .A(n2733), .B(n8160), .Z(n8117) );
HS65_LH_AOI12X2 U6891 ( .A(n6002), .B(n6083), .C(n6001), .Z(n6003) );
HS65_LHS_XNOR2X6 U6893 ( .A(n6084), .B(n6083), .Z(
\u_DataPath/u_execute/resAdd1_i [16]) );
HS65_LH_OAI12X3 U6894 ( .A(n5983), .B(n6077), .C(n5982), .Z(n6071) );
HS65_LH_NOR2X5 U6895 ( .A(n5700), .B(n7710), .Z(n5701) );
HS65_LH_IVX9 U6896 ( .A(n7653), .Z(n7749) );
HS65_LH_NOR2X5 U6897 ( .A(n7711), .B(n7710), .Z(n7712) );
HS65_LH_NAND2X5 U6898 ( .A(n3160), .B(n7802), .Z(n8549) );
HS65_LH_OAI12X3 U6899 ( .A(n5964), .B(n6077), .C(n5963), .Z(n5992) );
HS65_LH_NOR2X3 U6900 ( .A(n8847), .B(n7802), .Z(n3337) );
HS65_LL_NAND2X5 U6901 ( .A(n3131), .B(n3217), .Z(n3310) );
HS65_LL_NOR2AX3 U6902 ( .A(n3032), .B(n8262), .Z(n3033) );
HS65_LH_OAI12X3 U6903 ( .A(n6078), .B(n6077), .C(n6076), .Z(n6079) );
HS65_LH_OAI12X3 U6904 ( .A(n5782), .B(n5878), .C(n5781), .Z(n5872) );
HS65_LL_NAND2X5 U6905 ( .A(n3217), .B(n3131), .Z(n2896) );
HS65_LH_OAI12X3 U6906 ( .A(n5879), .B(n5878), .C(n5877), .Z(n5880) );
HS65_LH_NOR2X3 U6909 ( .A(n8092), .B(n7762), .Z(n8075) );
HS65_LL_OAI12X3 U6910 ( .A(n5939), .B(n5999), .C(n5938), .Z(n6111) );
HS65_LH_NAND2X4 U6911 ( .A(n9114), .B(n9369), .Z(n8429) );
HS65_LH_IVX4 U6912 ( .A(n7692), .Z(n7682) );
HS65_LHS_XNOR2X6 U6913 ( .A(n5893), .B(n5892), .Z(\u_DataPath/toPC2_i [4])
);
HS65_LL_NOR4ABX9 U6914 ( .A(n2954), .B(n2953), .C(n2952), .D(n2951), .Z(
n3217) );
HS65_LL_NAND2X4 U6915 ( .A(n3057), .B(n3028), .Z(n2932) );
HS65_LH_NOR2X6 U6917 ( .A(n7834), .B(n3442), .Z(n3431) );
HS65_LHS_XNOR2X6 U6918 ( .A(n2835), .B(n7746), .Z(\u_DataPath/pc_4_i [8]) );
HS65_LH_IVX7 U6919 ( .A(n7684), .Z(n7685) );
HS65_LH_AOI21X6 U6920 ( .A(n5934), .B(n5962), .C(n5933), .Z(n5999) );
HS65_LH_NAND3X5 U6921 ( .A(n7698), .B(n7697), .C(n7777), .Z(n8083) );
HS65_LL_AOI12X2 U6922 ( .A(n6013), .B(n6015), .C(n5937), .Z(n5938) );
HS65_LH_NAND2X5 U6924 ( .A(n7091), .B(n7090), .Z(n7092) );
HS65_LL_NAND2X2 U6925 ( .A(n9111), .B(n3049), .Z(n3051) );
HS65_LH_NOR2X3 U6926 ( .A(n8086), .B(n8098), .Z(n7762) );
HS65_LH_NOR2X5 U6929 ( .A(n7788), .B(n7787), .Z(n7708) );
HS65_LH_NAND2X4 U6930 ( .A(n3395), .B(n5716), .Z(n3398) );
HS65_LL_NOR2X2 U6932 ( .A(n3048), .B(n3054), .Z(n3032) );
HS65_LH_NAND3X3 U6933 ( .A(n3011), .B(n9076), .C(n9078), .Z(n3012) );
HS65_LH_OAI12X3 U6934 ( .A(n5899), .B(n5898), .C(n5897), .Z(n5900) );
HS65_LHS_XOR2X6 U6935 ( .A(n8943), .B(n2846), .Z(n3028) );
HS65_LL_NAND2X4 U6936 ( .A(n2945), .B(n2944), .Z(n2954) );
HS65_LL_NOR2AX3 U6937 ( .A(n2733), .B(n5716), .Z(n7861) );
HS65_LL_NOR2X5 U6938 ( .A(n6348), .B(n6341), .Z(n6680) );
HS65_LH_NOR2X5 U6939 ( .A(n8090), .B(n7700), .Z(n8097) );
HS65_LL_NOR2X5 U6940 ( .A(n6148), .B(n6140), .Z(n6171) );
HS65_LL_NOR2X5 U6941 ( .A(n6350), .B(n6341), .Z(n6754) );
HS65_LH_NOR2X5 U6942 ( .A(n7742), .B(n7741), .Z(n7666) );
HS65_LH_OAI12X3 U6944 ( .A(n6102), .B(n6101), .C(n6100), .Z(n6103) );
HS65_LL_NOR2X5 U6945 ( .A(n6146), .B(n6140), .Z(n6172) );
HS65_LH_NAND2X4 U6946 ( .A(n5769), .B(n5768), .Z(n5771) );
HS65_LH_NOR3X4 U6947 ( .A(n9233), .B(n8236), .C(rst), .Z(n8285) );
HS65_LL_AOI21X2 U6948 ( .A(n5981), .B(n5928), .C(n5927), .Z(n5963) );
HS65_LH_NAND2X4 U6949 ( .A(n5826), .B(n5825), .Z(n5828) );
HS65_LH_NAND2X4 U6950 ( .A(n5750), .B(n5749), .Z(n5752) );
HS65_LH_NAND2X4 U6951 ( .A(n6082), .B(n6081), .Z(n6084) );
HS65_LH_NOR3X4 U6952 ( .A(n9236), .B(n9237), .C(n7638), .Z(n8269) );
HS65_LH_NAND2X4 U6953 ( .A(n5788), .B(n5787), .Z(n5794) );
HS65_LH_NOR2X5 U6954 ( .A(n2975), .B(n7638), .Z(n2978) );
HS65_LH_IVX7 U6955 ( .A(n8115), .Z(n8123) );
HS65_LL_NOR2X3 U6959 ( .A(n6349), .B(n2878), .Z(n6670) );
HS65_LL_NOR2X5 U6960 ( .A(n6150), .B(n6151), .Z(n2888) );
HS65_LH_NAND2X4 U6961 ( .A(n6075), .B(n5875), .Z(n6080) );
HS65_LH_NAND2X4 U6962 ( .A(n5973), .B(n5972), .Z(n5975) );
HS65_LL_NOR2X3 U6965 ( .A(n6350), .B(n6332), .Z(n6740) );
HS65_LH_NAND2X4 U6966 ( .A(n6028), .B(n6027), .Z(n6030) );
HS65_LH_NAND2X4 U6968 ( .A(n6100), .B(n6050), .Z(n6052) );
HS65_LH_NAND2X4 U6969 ( .A(n4717), .B(n9343), .Z(n4214) );
HS65_LH_NAND2X4 U6970 ( .A(n5954), .B(n5953), .Z(n5956) );
HS65_LH_NAND2X4 U6972 ( .A(n4717), .B(n9341), .Z(n4970) );
HS65_LL_NOR2X5 U6973 ( .A(n6348), .B(n6332), .Z(n6747) );
HS65_LH_NAND3X5 U6974 ( .A(n2847), .B(n3008), .C(n7086), .Z(n3009) );
HS65_LH_IVX7 U6976 ( .A(n5965), .Z(n5966) );
HS65_LHS_XNOR2X6 U6977 ( .A(n7669), .B(n7743), .Z(\u_DataPath/pc_4_i [4]) );
HS65_LHS_XNOR2X3 U6978 ( .A(n7726), .B(n7789), .Z(
\u_DataPath/u_execute/link_value_i [4]) );
HS65_LH_NAND2X4 U6979 ( .A(n4713), .B(n9341), .Z(n3204) );
HS65_LH_NAND2X4 U6980 ( .A(n6094), .B(n5890), .Z(n6096) );
HS65_LL_NOR2X5 U6981 ( .A(n6148), .B(n6139), .Z(n2887) );
HS65_LL_NAND2AX4 U6983 ( .A(n3039), .B(n3038), .Z(n3042) );
HS65_LH_MUXI21X2 U6985 ( .D0(n3406), .D1(n9395), .S0(n3404), .Z(n8176) );
HS65_LH_NAND3X5 U6986 ( .A(n9237), .B(n2975), .C(n2973), .Z(n2974) );
HS65_LH_NOR2X6 U6987 ( .A(n3121), .B(n7686), .Z(n7659) );
HS65_LL_NAND2X4 U6989 ( .A(\u_DataPath/jaddr_i [24]), .B(n6126), .Z(n6151)
);
HS65_LH_NOR2X6 U6990 ( .A(\u_DataPath/jaddr_i [24]), .B(n8165), .Z(n6138) );
HS65_LL_OR3X4 U6991 ( .A(n8165), .B(n8151), .C(\u_DataPath/jaddr_i [25]),
.Z(n6147) );
HS65_LH_NOR2X5 U6992 ( .A(n8162), .B(n8074), .Z(n8086) );
HS65_LLS_XNOR2X3 U6993 ( .A(n8944), .B(n8170), .Z(n3040) );
HS65_LL_NAND2X4 U6994 ( .A(\u_DataPath/jaddr_i [25]), .B(n6145), .Z(n6139)
);
HS65_LH_NAND2X4 U6995 ( .A(n6118), .B(n6117), .Z(n6120) );
HS65_LHS_XNOR2X3 U6996 ( .A(n9116), .B(n7706), .Z(
\u_DataPath/u_execute/link_value_i [3]) );
HS65_LH_MUXI21X2 U6997 ( .D0(n2956), .D1(n9394), .S0(n3404), .Z(n8364) );
HS65_LH_NOR2X3 U6998 ( .A(\u_DataPath/immediate_ext_dec_i [3]), .B(n8090),
.Z(n8121) );
HS65_LH_IVX4 U6999 ( .A(n8159), .Z(n8625) );
HS65_LH_NAND3X5 U7000 ( .A(n9082), .B(n9068), .C(n7642), .Z(n7688) );
HS65_LH_NAND2X5 U7001 ( .A(opcode_i[5]), .B(n7695), .Z(n8037) );
HS65_LH_NOR2X3 U7004 ( .A(n8151), .B(rst), .Z(\u_DataPath/rs_ex_i [3]) );
HS65_LH_NAND3X3 U7005 ( .A(n9082), .B(n7696), .C(n7695), .Z(n8041) );
HS65_LH_NOR2X5 U7007 ( .A(\u_DataPath/immediate_ext_dec_i [0]), .B(n8162),
.Z(n8096) );
HS65_LL_MUXI21X2 U7008 ( .D0(n3212), .D1(n9396), .S0(
\u_DataPath/cw_towb_i [0]), .Z(n8265) );
HS65_LH_NAND2X4 U7009 ( .A(n6114), .B(n6113), .Z(n6116) );
HS65_LH_IVX4 U7011 ( .A(n5855), .Z(n5718) );
HS65_LH_NAND2X4 U7013 ( .A(n5915), .B(n5914), .Z(n5917) );
HS65_LH_NAND2X4 U7016 ( .A(n5911), .B(n5910), .Z(n5913) );
HS65_LH_NOR2X6 U7017 ( .A(n7834), .B(n5491), .Z(n3421) );
HS65_LH_OAI12X3 U7018 ( .A(n6006), .B(n5987), .C(n5989), .Z(n5965) );
HS65_LL_NAND2X5 U7019 ( .A(n3030), .B(n2946), .Z(n3008) );
HS65_LL_NAND3X2 U7020 ( .A(\u_DataPath/cw_to_ex_i [4]), .B(n5492), .C(n5491),
.Z(n5493) );
HS65_LH_OAI12X3 U7021 ( .A(n6064), .B(n2875), .C(n6063), .Z(n5935) );
HS65_LH_NOR2X5 U7023 ( .A(n5836), .B(n5839), .Z(n5834) );
HS65_LH_NOR2X6 U7024 ( .A(n6085), .B(n6090), .Z(n5924) );
HS65_LL_OAI12X2 U7025 ( .A(n5850), .B(n5846), .C(n5848), .Z(n5844) );
HS65_LH_OAI12X3 U7026 ( .A(n6088), .B(n6085), .C(n6087), .Z(n5923) );
HS65_LH_NAND2X4 U7027 ( .A(n5907), .B(n5906), .Z(n5909) );
HS65_LL_NAND2AX7 U7029 ( .A(n9078), .B(n3030), .Z(n7084) );
HS65_LH_OAI12X3 U7030 ( .A(n6076), .B(n6073), .C(n6075), .Z(n5981) );
HS65_LH_IVX7 U7031 ( .A(n5867), .Z(n5821) );
HS65_LH_NAND2AX7 U7032 ( .A(n8480), .B(n9347), .Z(n8051) );
HS65_LH_NOR2X5 U7033 ( .A(n8942), .B(n9222), .Z(n6022) );
HS65_LH_NOR2X3 U7034 ( .A(\u_DataPath/jaddr_i [23]), .B(
\u_DataPath/jaddr_i [25]), .Z(n6126) );
HS65_LH_MUX21X4 U7035 ( .D0(n8908), .D1(\u_DataPath/from_mem_data_out_i [6]),
.S0(\u_DataPath/cw_towb_i [0]), .Z(n8311) );
HS65_LH_NOR2X3 U7036 ( .A(opcode_i[5]), .B(n9068), .Z(n7735) );
HS65_LH_NOR2X5 U7039 ( .A(\u_DataPath/jaddr_i [18]), .B(
\u_DataPath/jaddr_i [19]), .Z(n6339) );
HS65_LH_NOR2X5 U7040 ( .A(n9342), .B(n9209), .Z(n5767) );
HS65_LH_NOR2X5 U7041 ( .A(n9341), .B(n9213), .Z(n5824) );
HS65_LH_NOR2X3 U7042 ( .A(\u_DataPath/immediate_ext_dec_i [5]), .B(
\u_DataPath/immediate_ext_dec_i [4]), .Z(n8120) );
HS65_LL_NOR2X3 U7043 ( .A(n9341), .B(n9221), .Z(n5817) );
HS65_LH_NOR2X5 U7044 ( .A(n9341), .B(n9222), .Z(n5820) );
HS65_LH_IVX9 U7046 ( .A(n7835), .Z(n7116) );
HS65_LH_NAND2X4 U7047 ( .A(\u_DataPath/immediate_ext_dec_i [5]), .B(
\u_DataPath/immediate_ext_dec_i [4]), .Z(n8074) );
HS65_LH_NOR2X5 U7053 ( .A(n9175), .B(n9227), .Z(n5882) );
HS65_LH_NOR2X3 U7054 ( .A(n9037), .B(n9212), .Z(n6045) );
HS65_LLS_XNOR2X3 U7055 ( .A(n8761), .B(n9004), .Z(n3036) );
HS65_LH_NAND2X7 U7056 ( .A(n9179), .B(n9225), .Z(n6088) );
HS65_LH_NAND2X7 U7057 ( .A(n9175), .B(n9227), .Z(n6087) );
HS65_LLS_XNOR2X3 U7058 ( .A(n8763), .B(n8942), .Z(n2960) );
HS65_LLS_XNOR2X3 U7059 ( .A(n9077), .B(n8761), .Z(n2957) );
HS65_LLS_XNOR2X3 U7060 ( .A(n8764), .B(n8967), .Z(n2963) );
HS65_LH_IVX9 U7061 ( .A(n8762), .Z(n8107) );
HS65_LH_NAND2X7 U7062 ( .A(n9177), .B(n9229), .Z(n6076) );
HS65_LH_NAND2X7 U7064 ( .A(n9171), .B(n9214), .Z(n6070) );
HS65_LL_OAI21X2 U7065 ( .A(\u_DataPath/cw_towb_i [1]), .B(n9075), .C(n9077),
.Z(n2944) );
HS65_LL_IVX7 U7066 ( .A(n9076), .Z(n2946) );
HS65_LH_NAND2X7 U7067 ( .A(n9232), .B(n9214), .Z(n7728) );
HS65_LH_NAND2X7 U7068 ( .A(n9267), .B(n9228), .Z(n5989) );
HS65_LH_NAND2X4 U7070 ( .A(n9342), .B(n9202), .Z(n5852) );
HS65_LH_NOR2X5 U7071 ( .A(n9343), .B(n9203), .Z(n5855) );
HS65_LH_NOR2X5 U7072 ( .A(n9145), .B(n9224), .Z(n5957) );
HS65_LH_NOR2X5 U7073 ( .A(n9343), .B(n9205), .Z(n5743) );
HS65_LH_NOR2X5 U7074 ( .A(n8968), .B(n9217), .Z(n5995) );
HS65_LH_NOR2X6 U7075 ( .A(n8966), .B(n9221), .Z(n6019) );
HS65_LH_OR2X9 U7076 ( .A(n9342), .B(n9206), .Z(n5906) );
HS65_LH_NAND2X7 U7077 ( .A(n8966), .B(n9221), .Z(n6021) );
HS65_LH_NOR2X5 U7078 ( .A(n9179), .B(n9225), .Z(n5887) );
HS65_LH_NAND3X5 U7079 ( .A(opcode_i[3]), .B(opcode_i[5]), .C(n9068), .Z(
n7636) );
HS65_LH_IVX9 U7080 ( .A(n9113), .Z(n2983) );
HS65_LL_NOR2X3 U7081 ( .A(n9237), .B(n8915), .Z(n2976) );
HS65_LL_NAND3AX6 U7083 ( .A(n4833), .B(n4832), .C(n7848), .Z(n5679) );
HS65_LL_NAND3AX3 U7084 ( .A(n5602), .B(n8479), .C(n8458), .Z(n5676) );
HS65_LL_IVX4 U7086 ( .A(n5710), .Z(n5711) );
HS65_LL_NOR2AX3 U7087 ( .A(n5709), .B(n5708), .Z(n7859) );
HS65_LH_OAI12X3 U7088 ( .A(n9190), .B(n8888), .C(n8294), .Z(
\u_DataPath/dataOut_exe_i [10]) );
HS65_LH_NAND2X4 U7089 ( .A(n5285), .B(n5707), .Z(n4370) );
HS65_LL_AO12X4 U7091 ( .A(n5285), .B(n5222), .C(n5221), .Z(n5224) );
HS65_LL_NAND2AX4 U7092 ( .A(n4961), .B(n4960), .Z(n4962) );
HS65_LH_NAND3X3 U7093 ( .A(n5704), .B(n8462), .C(n4537), .Z(n4833) );
HS65_LL_NAND2AX4 U7094 ( .A(n3626), .B(n3625), .Z(n3627) );
HS65_LH_CBI4I1X5 U7095 ( .A(n8883), .B(n9201), .C(n9239), .D(n7836), .Z(
\u_DataPath/dataOut_exe_i [11]) );
HS65_LH_AND2X9 U7096 ( .A(n5285), .B(n7626), .Z(n5598) );
HS65_LHS_XNOR2X6 U7099 ( .A(n2915), .B(n4313), .Z(n5707) );
HS65_LLS_XNOR2X3 U7101 ( .A(n2914), .B(n4300), .Z(n4301) );
HS65_LL_AO12X4 U7102 ( .A(n4367), .B(n5285), .C(n4366), .Z(n4368) );
HS65_LLS_XNOR2X3 U7103 ( .A(n4413), .B(n4412), .Z(n4414) );
HS65_LLS_XNOR2X3 U7105 ( .A(n3580), .B(n3579), .Z(n3628) );
HS65_LL_AO12X4 U7106 ( .A(n5643), .B(n4450), .C(n4449), .Z(n4451) );
HS65_LHS_XNOR2X6 U7107 ( .A(n4935), .B(n4934), .Z(n4936) );
HS65_LL_NOR3X1 U7108 ( .A(n5705), .B(n4536), .C(n6121), .Z(n4537) );
HS65_LH_NOR2AX3 U7110 ( .A(n3799), .B(n3798), .Z(n3811) );
HS65_LL_AND3X4 U7111 ( .A(n4901), .B(n4900), .C(n4899), .Z(n4910) );
HS65_LL_NAND2X2 U7113 ( .A(n5217), .B(n4327), .Z(n4369) );
HS65_LH_NAND2X7 U7115 ( .A(n5643), .B(n3566), .Z(n3567) );
HS65_LLS_XNOR2X3 U7116 ( .A(n4242), .B(n4241), .Z(n7626) );
HS65_LL_NAND2X2 U7117 ( .A(n4448), .B(n4447), .Z(n4449) );
HS65_LL_AND3X4 U7118 ( .A(n5368), .B(n5341), .C(n5340), .Z(n2920) );
HS65_LH_NAND2AX7 U7119 ( .A(n3797), .B(n3796), .Z(n3798) );
HS65_LL_OAI21X3 U7120 ( .A(n4246), .B(n5633), .C(n4245), .Z(n4247) );
HS65_LLS_XNOR2X3 U7122 ( .A(n4379), .B(n4378), .Z(n4380) );
HS65_LLS_XNOR2X3 U7123 ( .A(n2907), .B(n9338), .Z(n3902) );
HS65_LL_NAND2AX4 U7124 ( .A(n5076), .B(n5075), .Z(n5077) );
HS65_LL_OAI12X3 U7125 ( .A(n5277), .B(n5633), .C(n5276), .Z(n5278) );
HS65_LHS_XNOR2X6 U7126 ( .A(n3623), .B(n3622), .Z(n3624) );
HS65_LL_OAI12X3 U7127 ( .A(n5633), .B(n4337), .C(n4336), .Z(n4338) );
HS65_LL_NOR2AX3 U7128 ( .A(n4933), .B(n4932), .Z(n4934) );
HS65_LLS_XNOR2X3 U7129 ( .A(n4226), .B(n4225), .Z(n7622) );
HS65_LH_CBI4I1X5 U7130 ( .A(n8882), .B(n8894), .C(n9189), .D(n8436), .Z(
\u_DataPath/dataOut_exe_i [2]) );
HS65_LH_OAI21X3 U7131 ( .A(n3578), .B(n5633), .C(n3577), .Z(n3579) );
HS65_LL_OAI12X3 U7132 ( .A(n4311), .B(n5633), .C(n4310), .Z(n4312) );
HS65_LH_NAND2AX7 U7133 ( .A(n5593), .B(n5592), .Z(n5594) );
HS65_LL_OAI12X3 U7134 ( .A(n4411), .B(n5633), .C(n4410), .Z(n4412) );
HS65_LL_OAI12X3 U7135 ( .A(n5197), .B(n5633), .C(n5196), .Z(n5198) );
HS65_LL_NAND3AX3 U7136 ( .A(n4172), .B(n4171), .C(n4170), .Z(n4173) );
HS65_LL_NAND2X2 U7137 ( .A(n5339), .B(n5338), .Z(n5340) );
HS65_LL_OAI12X3 U7138 ( .A(n5213), .B(n2859), .C(n5212), .Z(n5214) );
HS65_LL_NAND2X2 U7139 ( .A(n5372), .B(n5371), .Z(n5596) );
HS65_LL_NAND2AX4 U7140 ( .A(n3467), .B(n3466), .Z(n3468) );
HS65_LHS_XNOR2X6 U7142 ( .A(n3943), .B(n3942), .Z(n3944) );
HS65_LHS_XNOR2X6 U7143 ( .A(n3994), .B(n3993), .Z(n3995) );
HS65_LL_AO12X4 U7144 ( .A(n5074), .B(n5073), .C(n5072), .Z(n5075) );
HS65_LL_OAI12X3 U7145 ( .A(n3473), .B(n2859), .C(n4251), .Z(n4252) );
HS65_LL_OAI12X3 U7146 ( .A(n5263), .B(n2859), .C(n5262), .Z(n5264) );
HS65_LL_NOR2AX3 U7147 ( .A(n5591), .B(n5590), .Z(n5592) );
HS65_LL_NAND3X2 U7148 ( .A(n4278), .B(n4277), .C(n4276), .Z(n4279) );
HS65_LLS_XNOR2X3 U7149 ( .A(n4923), .B(n4922), .Z(n4963) );
HS65_LL_NAND2AX4 U7151 ( .A(n5669), .B(n5668), .Z(n5670) );
HS65_LL_NAND3AX3 U7152 ( .A(n3730), .B(n3729), .C(n3728), .Z(n3744) );
HS65_LLS_XNOR2X3 U7153 ( .A(n2906), .B(n3817), .Z(n3852) );
HS65_LL_OAI21X2 U7155 ( .A(n5152), .B(n4473), .C(n4472), .Z(n4474) );
HS65_LL_NOR2AX3 U7156 ( .A(n4388), .B(n5152), .Z(n4122) );
HS65_LL_NAND4X4 U7158 ( .A(n4567), .B(n4566), .C(n4565), .D(n4564), .Z(n4568) );
HS65_LL_AOI21X2 U7159 ( .A(n3751), .B(n5195), .C(n3750), .Z(n3752) );
HS65_LL_NAND2AX4 U7162 ( .A(n4520), .B(n4519), .Z(n4948) );
HS65_LL_NAND2X2 U7163 ( .A(n5589), .B(n5588), .Z(n5590) );
HS65_LL_OR3X4 U7164 ( .A(n4860), .B(n4859), .C(n4858), .Z(n2902) );
HS65_LL_NAND3AX3 U7165 ( .A(n3929), .B(n3928), .C(n3927), .Z(n3930) );
HS65_LH_OAI12X3 U7166 ( .A(n4387), .B(n4386), .C(n5672), .Z(n4406) );
HS65_LL_NAND3X2 U7167 ( .A(n5112), .B(n5111), .C(n5110), .Z(n5113) );
HS65_LL_NAND3X2 U7168 ( .A(n4152), .B(n4151), .C(n4150), .Z(n4172) );
HS65_LL_NAND3AX3 U7169 ( .A(n3787), .B(n3786), .C(n3785), .Z(n3794) );
HS65_LH_AOI21X2 U7170 ( .A(n5624), .B(n5623), .C(n5622), .Z(n5625) );
HS65_LL_AOI22X1 U7171 ( .A(n6123), .B(n5250), .C(n4512), .D(n5248), .Z(n8462) );
HS65_LL_AOI21X2 U7174 ( .A(n4222), .B(n5211), .C(n4221), .Z(n4223) );
HS65_LL_NAND3X2 U7175 ( .A(n5584), .B(n5536), .C(n5535), .Z(n5537) );
HS65_LH_OA12X4 U7176 ( .A(n3894), .B(n3815), .C(n3816), .Z(n3817) );
HS65_LH_NOR4ABX2 U7177 ( .A(n5335), .B(n4017), .C(n5334), .D(n5333), .Z(
n5336) );
HS65_LH_OAI21X3 U7178 ( .A(n3981), .B(n5152), .C(n3980), .Z(n3988) );
HS65_LH_NAND3X3 U7179 ( .A(n3655), .B(n3429), .C(n3428), .Z(n3467) );
HS65_LL_NAND3X2 U7181 ( .A(n4980), .B(n4979), .C(n4978), .Z(n4995) );
HS65_LL_CB4I1X4 U7182 ( .A(n4695), .B(n4694), .C(n4693), .D(n4692), .Z(n4784) );
HS65_LH_OAI21X3 U7184 ( .A(n5646), .B(n4849), .C(n4848), .Z(n4860) );
HS65_LH_AOI21X2 U7185 ( .A(n5207), .B(n5206), .C(n5205), .Z(n5219) );
HS65_LH_AOI21X2 U7186 ( .A(n5659), .B(n5239), .C(n3675), .Z(n3676) );
HS65_LL_NAND4ABX3 U7187 ( .A(n4621), .B(n4620), .C(n4619), .D(n4618), .Z(
n4652) );
HS65_LH_NAND3X3 U7188 ( .A(n3655), .B(n3654), .C(n3653), .Z(n3680) );
HS65_LH_OAI21X3 U7189 ( .A(n4753), .B(n5656), .C(n4135), .Z(n4136) );
HS65_LH_NAND3X3 U7190 ( .A(n4431), .B(n5089), .C(n4430), .Z(n4448) );
HS65_LH_OAI21X3 U7191 ( .A(n4812), .B(n4811), .C(n4810), .Z(n4813) );
HS65_LL_NAND2X2 U7192 ( .A(n4518), .B(n4517), .Z(n4520) );
HS65_LH_OAI21X3 U7193 ( .A(n5177), .B(n5176), .C(n5175), .Z(n5190) );
HS65_LH_NAND2X4 U7195 ( .A(n4309), .B(n5194), .Z(n4311) );
HS65_LL_AOI12X2 U7196 ( .A(n4516), .B(n4515), .C(n4514), .Z(n4518) );
HS65_LLS_XOR2X3 U7198 ( .A(n4104), .B(n4103), .Z(n4141) );
HS65_LL_NAND3X2 U7199 ( .A(n4202), .B(n4201), .C(n4200), .Z(n4203) );
HS65_LL_NAND2X2 U7200 ( .A(n5352), .B(n5351), .Z(n5482) );
HS65_LL_OR2X4 U7201 ( .A(n3894), .B(n3370), .Z(n2929) );
HS65_LH_NOR2AX3 U7203 ( .A(n5058), .B(n5057), .Z(n5059) );
HS65_LL_NAND3X2 U7204 ( .A(n5297), .B(n5109), .C(n5108), .Z(n5526) );
HS65_LLS_XOR2X3 U7205 ( .A(n4146), .B(n4145), .Z(n4174) );
HS65_LH_IVX9 U7206 ( .A(n4918), .Z(n3816) );
HS65_LH_AOI21X2 U7207 ( .A(n4951), .B(n4875), .C(n4874), .Z(n4901) );
HS65_LH_NAND2X4 U7209 ( .A(n4007), .B(n4836), .Z(n4606) );
HS65_LLS_XOR2X3 U7211 ( .A(n4648), .B(n4647), .Z(n4649) );
HS65_LH_AOI21X2 U7212 ( .A(n3778), .B(n5658), .C(n3777), .Z(n3786) );
HS65_LH_AOI21X2 U7213 ( .A(n5234), .B(n4033), .C(n4032), .Z(n4048) );
HS65_LH_AOI21X2 U7214 ( .A(n5131), .B(n4615), .C(n4026), .Z(n2931) );
HS65_LL_NOR2AX6 U7215 ( .A(n3482), .B(n3481), .Z(n3618) );
HS65_LH_AOI21X2 U7216 ( .A(n5144), .B(n4560), .C(n4559), .Z(n4565) );
HS65_LH_CNIVX3 U7219 ( .A(n5174), .Z(n3462) );
HS65_LH_AOI21X2 U7220 ( .A(n4887), .B(n4875), .C(n4809), .Z(n4810) );
HS65_LH_AOI21X2 U7221 ( .A(n5229), .B(n5658), .C(n4547), .Z(n4567) );
HS65_LH_NAND2X4 U7222 ( .A(n3634), .B(n5194), .Z(n3636) );
HS65_LH_IVX9 U7226 ( .A(n5630), .Z(n4419) );
HS65_LH_NAND3X3 U7227 ( .A(n5563), .B(n5574), .C(n5562), .Z(n5577) );
HS65_LH_AOI21X2 U7228 ( .A(n5575), .B(n5574), .C(n5573), .Z(n5576) );
HS65_LH_OAI21X3 U7229 ( .A(n4134), .B(n4795), .C(n4163), .Z(n4381) );
HS65_LH_AOI21X2 U7230 ( .A(n5304), .B(n5303), .C(n5302), .Z(n5486) );
HS65_LH_IVX9 U7231 ( .A(n4955), .Z(n4164) );
HS65_LH_AOI21X2 U7232 ( .A(n4625), .B(n4632), .C(n4627), .Z(n4159) );
HS65_LH_AOI21X2 U7234 ( .A(n4508), .B(n4943), .C(n4261), .Z(n4260) );
HS65_LL_OR2X4 U7235 ( .A(n3485), .B(n3484), .Z(n2924) );
HS65_LL_NAND2AX4 U7236 ( .A(n3246), .B(n3362), .Z(n3894) );
HS65_LH_IVX4 U7237 ( .A(n4558), .Z(n4157) );
HS65_LL_OAI12X2 U7238 ( .A(n5046), .B(n5045), .C(n5044), .Z(n5074) );
HS65_LL_NOR2AX3 U7239 ( .A(n3453), .B(n3452), .Z(n3454) );
HS65_LH_OAI21X3 U7240 ( .A(n4808), .B(n5656), .C(n4807), .Z(n4809) );
HS65_LH_AOI21X2 U7241 ( .A(n3704), .B(n5630), .C(n3703), .Z(n3705) );
HS65_LH_NOR2X5 U7242 ( .A(n4307), .B(n4330), .Z(n4309) );
HS65_LL_NAND2X2 U7246 ( .A(n4996), .B(n5015), .Z(n5018) );
HS65_LH_CNIVX3 U7247 ( .A(n3804), .Z(n3685) );
HS65_LH_AOI21X2 U7248 ( .A(n4424), .B(n5607), .C(n4375), .Z(n4376) );
HS65_LL_OAI112X1 U7249 ( .A(n5554), .B(n5553), .C(n5552), .D(n5551), .Z(
n5555) );
HS65_LH_AOI21X2 U7250 ( .A(n5618), .B(n4892), .C(n4891), .Z(n4893) );
HS65_LH_AOI21X2 U7251 ( .A(n4943), .B(n4528), .C(n4527), .Z(n4529) );
HS65_LH_CNIVX3 U7252 ( .A(n5366), .Z(n5291) );
HS65_LL_NOR2X2 U7253 ( .A(n5646), .B(n5172), .Z(n4434) );
HS65_LL_AOI21X2 U7254 ( .A(n9352), .B(n5567), .C(n5649), .Z(n3774) );
HS65_LH_AOI21X2 U7256 ( .A(n9349), .B(n5654), .C(n5649), .Z(n5651) );
HS65_LH_IVX7 U7257 ( .A(n4872), .Z(n4119) );
HS65_LH_AND2X4 U7258 ( .A(n3893), .B(n3892), .Z(n2907) );
HS65_LL_NOR2AX3 U7259 ( .A(n3652), .B(n3651), .Z(n4025) );
HS65_LH_OAI21X3 U7260 ( .A(n5176), .B(n4800), .C(n4799), .Z(n4815) );
HS65_LH_AOI21X2 U7261 ( .A(n3921), .B(n3920), .C(n5241), .Z(n3925) );
HS65_LL_NOR2AX3 U7262 ( .A(n3912), .B(n3911), .Z(n3913) );
HS65_LH_CNIVX3 U7263 ( .A(n5464), .Z(n5330) );
HS65_LL_OAI12X2 U7264 ( .A(n5441), .B(n5440), .C(n5439), .Z(n5459) );
HS65_LH_CNIVX3 U7265 ( .A(n4886), .Z(n4070) );
HS65_LH_AOI21X2 U7266 ( .A(n5608), .B(n5607), .C(n5606), .Z(n5609) );
HS65_LL_OAI12X2 U7267 ( .A(n5499), .B(n5346), .C(n5286), .Z(n5575) );
HS65_LH_AOI21X2 U7268 ( .A(n5234), .B(n3662), .C(n3661), .Z(n3678) );
HS65_LH_NAND2AX7 U7269 ( .A(n3766), .B(n3765), .Z(n4515) );
HS65_LH_OAI12X3 U7270 ( .A(n4915), .B(n3891), .C(n3893), .Z(n3367) );
HS65_LLS_XOR2X3 U7271 ( .A(n9202), .B(n7800), .Z(
\u_DataPath/u_execute/link_value_i [31]) );
HS65_LL_NAND3X3 U7272 ( .A(n3821), .B(n3781), .C(n3780), .Z(n5644) );
HS65_LH_AND2X4 U7273 ( .A(n5435), .B(n5628), .Z(n2917) );
HS65_LH_NAND2X7 U7274 ( .A(n3499), .B(n5608), .Z(n3501) );
HS65_LL_OAI12X3 U7276 ( .A(n4257), .B(n4256), .C(n3426), .Z(n4262) );
HS65_LH_OAI12X3 U7277 ( .A(n4630), .B(n4629), .C(n4628), .Z(n4631) );
HS65_LH_NAND3X5 U7278 ( .A(n3833), .B(n3832), .C(n3831), .Z(n5142) );
HS65_LL_NAND2AX4 U7279 ( .A(n3528), .B(n3527), .Z(n4393) );
HS65_LH_CNIVX3 U7280 ( .A(n4748), .Z(n3919) );
HS65_LH_NAND2AX4 U7281 ( .A(n3981), .B(n5615), .Z(n3792) );
HS65_LHS_XOR2X6 U7282 ( .A(n5742), .B(n5854), .Z(\u_DataPath/toPC2_i [30])
);
HS65_LL_NOR2AX3 U7283 ( .A(n3197), .B(n4244), .Z(n3374) );
HS65_LL_NAND2X4 U7284 ( .A(n4724), .B(n5423), .Z(n5346) );
HS65_LL_AOI22X1 U7286 ( .A(n8868), .B(n9180), .C(n9368), .D(n8869), .Z(n8395) );
HS65_LL_OAI12X3 U7287 ( .A(n5193), .B(n3572), .C(n3574), .Z(n3750) );
HS65_LH_AOI31X2 U7288 ( .A(n2854), .B(n5567), .C(n5566), .D(n5565), .Z(n5578) );
HS65_LL_NAND3X2 U7289 ( .A(n4061), .B(n3664), .C(n3663), .Z(n5228) );
HS65_LH_OAI12X3 U7290 ( .A(n4038), .B(n4034), .C(n4036), .Z(n3476) );
HS65_LH_AOI21X2 U7292 ( .A(n4587), .B(n2858), .C(n3957), .Z(n3958) );
HS65_LH_AOI21X2 U7293 ( .A(n4975), .B(n4974), .C(n5499), .Z(n4996) );
HS65_LH_NOR2AX3 U7294 ( .A(n3231), .B(n4902), .Z(n4014) );
HS65_LL_NAND2AX4 U7295 ( .A(n3361), .B(n4904), .Z(n4016) );
HS65_LL_NOR2X3 U7297 ( .A(\sub_x_53/A[25] ), .B(n5425), .Z(n3572) );
HS65_LH_AOI21X2 U7298 ( .A(n3426), .B(n4066), .C(n3969), .Z(n4894) );
HS65_LH_NAND2X4 U7299 ( .A(n3700), .B(n3699), .Z(n3708) );
HS65_LH_NAND2X4 U7300 ( .A(n4641), .B(n4142), .Z(n4146) );
HS65_LL_AOI22X1 U7301 ( .A(\sub_x_53/A[25] ), .B(n4551), .C(n2845), .D(
\lte_x_59/B[24] ), .Z(n3602) );
HS65_LL_AOI22X1 U7302 ( .A(n8868), .B(n9266), .C(n9365), .D(n8870), .Z(n8445) );
HS65_LH_NAND2X4 U7303 ( .A(n7631), .B(n5124), .Z(n5157) );
HS65_LL_NOR2X2 U7304 ( .A(n3731), .B(n5603), .Z(n3499) );
HS65_LH_AOI21X2 U7305 ( .A(n9352), .B(n4674), .C(n4067), .Z(n4069) );
HS65_LH_NAND2AX4 U7307 ( .A(n4643), .B(n3330), .Z(n3351) );
HS65_LL_OAI12X3 U7309 ( .A(n4882), .B(n4876), .C(n4878), .Z(n4040) );
HS65_LH_AO22X9 U7310 ( .A(n8905), .B(n9188), .C(n9133), .D(n8998), .Z(
\u_DataPath/jump_address_i [28]) );
HS65_LL_AOI12X2 U7311 ( .A(n4824), .B(n5126), .C(n4596), .Z(n3487) );
HS65_LH_NAND2X4 U7312 ( .A(n5258), .B(n5261), .Z(n4253) );
HS65_LH_AOI31X2 U7313 ( .A(\sub_x_53/A[25] ), .B(n5345), .C(n5344), .D(n5343), .Z(n5349) );
HS65_LH_AND2X4 U7315 ( .A(n4036), .B(n4035), .Z(n4045) );
HS65_LH_AOI31X2 U7316 ( .A(\lte_x_59/B[7] ), .B(n5313), .C(n5312), .D(n5311),
.Z(n5314) );
HS65_LH_OAI21X2 U7317 ( .A(n5435), .B(n3698), .C(n5509), .Z(n5436) );
HS65_LHS_XNOR2X6 U7318 ( .A(n5861), .B(n5860), .Z(\u_DataPath/toPC2_i [29])
);
HS65_LL_NOR2X2 U7319 ( .A(n4968), .B(n5361), .Z(n5009) );
HS65_LH_AOI21X2 U7320 ( .A(n4551), .B(\lte_x_59/B[15] ), .C(n3907), .Z(n3912) );
HS65_LH_OAI21X3 U7321 ( .A(n5318), .B(n5037), .C(n5317), .Z(n5554) );
HS65_LHS_XNOR2X6 U7323 ( .A(n6056), .B(n6055), .Z(
\u_DataPath/u_execute/resAdd1_i [30]) );
HS65_LH_OAI21X2 U7324 ( .A(n5065), .B(n5064), .C(n5063), .Z(n5066) );
HS65_LH_AOI21X2 U7325 ( .A(n4551), .B(\sub_x_53/A[25] ), .C(n3549), .Z(n3585) );
HS65_LH_OAI22X3 U7326 ( .A(n7306), .B(n8337), .C(n7915), .D(n8336), .Z(
\u_DataPath/data_read_ex_1_i [9]) );
HS65_LH_OAI22X3 U7327 ( .A(n7306), .B(n8330), .C(n7915), .D(n8329), .Z(
\u_DataPath/data_read_ex_1_i [25]) );
HS65_LH_OAI22X3 U7328 ( .A(n7306), .B(n8444), .C(n7914), .D(n8173), .Z(
\u_DataPath/data_read_ex_1_i [2]) );
HS65_LH_AND2X4 U7329 ( .A(\lte_x_59/B[9] ), .B(n2864), .Z(n4153) );
HS65_LH_AO22X9 U7330 ( .A(n9255), .B(n9188), .C(n9133), .D(n9013), .Z(
\u_DataPath/jump_address_i [9]) );
HS65_LH_AO222X4 U7331 ( .A(\u_DataPath/pc_4_i [31]), .B(n7896), .C(n7887),
.D(n9165), .E(n7893), .F(n9403), .Z(n8641) );
HS65_LH_OAI22X3 U7334 ( .A(n4981), .B(n5129), .C(n2854), .D(n3756), .Z(n3782) );
HS65_LL_OAI12X3 U7335 ( .A(n4418), .B(n4407), .C(n5434), .Z(n5629) );
HS65_LH_OR2X4 U7336 ( .A(\sub_x_53/A[0] ), .B(n5136), .Z(n5125) );
HS65_LH_NAND3X2 U7337 ( .A(\u_DataPath/cw_to_ex_i [1]), .B(n5531), .C(n5506),
.Z(n5080) );
HS65_LH_NOR2X5 U7338 ( .A(n2858), .B(n5398), .Z(n5399) );
HS65_LL_NOR2X2 U7339 ( .A(n5430), .B(n4244), .Z(n5432) );
HS65_LL_NOR2X3 U7340 ( .A(n5419), .B(n4407), .Z(n5632) );
HS65_LL_OR2X4 U7341 ( .A(n5021), .B(n5022), .Z(n2892) );
HS65_LH_NOR2AX3 U7343 ( .A(n4682), .B(n3360), .Z(n4905) );
HS65_LL_NOR2X3 U7344 ( .A(n2843), .B(n4683), .Z(n5300) );
HS65_LH_NOR2X5 U7345 ( .A(n4676), .B(n5061), .Z(n5083) );
HS65_LH_NAND2X5 U7346 ( .A(n5031), .B(n5030), .Z(n5544) );
HS65_LH_NOR2X3 U7347 ( .A(n5320), .B(n5321), .Z(n5037) );
HS65_LH_NOR2X5 U7348 ( .A(n4811), .B(n4805), .Z(n5548) );
HS65_LH_NOR2X5 U7349 ( .A(n5031), .B(n5030), .Z(n5095) );
HS65_LH_NAND2X5 U7350 ( .A(n3101), .B(n4997), .Z(n5289) );
HS65_LH_NOR2X5 U7351 ( .A(n4711), .B(n4976), .Z(n5347) );
HS65_LL_NOR2X2 U7352 ( .A(n4701), .B(n5418), .Z(n5363) );
HS65_LH_NOR2AX3 U7353 ( .A(n5004), .B(n3372), .Z(n5269) );
HS65_LH_OAI12X3 U7354 ( .A(n4628), .B(n4622), .C(n4624), .Z(n3485) );
HS65_LL_NAND2X4 U7355 ( .A(\sub_x_53/A[0] ), .B(n5136), .Z(n5126) );
HS65_LH_NOR4ABX2 U7357 ( .A(n7406), .B(n7405), .C(n7404), .D(n7403), .Z(
n8433) );
HS65_LH_NOR4ABX2 U7358 ( .A(n7471), .B(n7470), .C(n7469), .D(n7468), .Z(
n8373) );
HS65_LH_NOR4ABX2 U7359 ( .A(n7386), .B(n7385), .C(n7384), .D(n7383), .Z(
n8388) );
HS65_LH_NOR4ABX2 U7360 ( .A(n7451), .B(n7450), .C(n7449), .D(n7448), .Z(
n8155) );
HS65_LH_NOR4ABX2 U7361 ( .A(n7557), .B(n7556), .C(n7555), .D(n7554), .Z(
n8354) );
HS65_LH_NOR4ABX2 U7362 ( .A(n7612), .B(n7611), .C(n7610), .D(n7609), .Z(
n8363) );
HS65_LH_NOR4ABX2 U7363 ( .A(n6204), .B(n6203), .C(n6202), .D(n6201), .Z(
n8366) );
HS65_LH_NOR4ABX2 U7364 ( .A(n6494), .B(n6493), .C(n6492), .D(n6491), .Z(
n8313) );
HS65_LH_NOR4ABX2 U7365 ( .A(n6325), .B(n6324), .C(n6323), .D(n6322), .Z(
n8403) );
HS65_LH_NOR4ABX2 U7366 ( .A(n7366), .B(n7365), .C(n7364), .D(n7363), .Z(
n8392) );
HS65_LH_NOR4ABX2 U7367 ( .A(n7537), .B(n7536), .C(n7535), .D(n7534), .Z(
n8381) );
HS65_LH_NOR4ABX2 U7368 ( .A(n7577), .B(n7576), .C(n7575), .D(n7574), .Z(
n8368) );
HS65_LH_NOR4ABX2 U7369 ( .A(n6975), .B(n6974), .C(n6973), .D(n6972), .Z(
n8442) );
HS65_LH_NOR4ABX2 U7370 ( .A(n6304), .B(n6303), .C(n6302), .D(n6301), .Z(
n8371) );
HS65_LH_NOR4ABX2 U7371 ( .A(n7491), .B(n7490), .C(n7489), .D(n7488), .Z(
n8384) );
HS65_LH_NOR4ABX2 U7372 ( .A(n6161), .B(n6160), .C(n6159), .D(n6158), .Z(
n8396) );
HS65_LH_NOR4ABX2 U7373 ( .A(n6284), .B(n6283), .C(n6282), .D(n6281), .Z(
n8352) );
HS65_LH_NOR4ABX2 U7374 ( .A(n7427), .B(n7426), .C(n7425), .D(n7424), .Z(
n8379) );
HS65_LH_NOR4ABX2 U7375 ( .A(n7511), .B(n7510), .C(n7509), .D(n7508), .Z(
n8382) );
HS65_LH_AO22X9 U7377 ( .A(n8997), .B(n9188), .C(n9133), .D(n9011), .Z(
\u_DataPath/jump_address_i [7]) );
HS65_LH_OR2X4 U7380 ( .A(n2851), .B(n7623), .Z(n4205) );
HS65_LH_AO22X9 U7382 ( .A(n9022), .B(n9188), .C(n9133), .D(n8948), .Z(
\u_DataPath/jump_address_i [14]) );
HS65_LH_NOR2X5 U7383 ( .A(\sub_x_53/A[2] ), .B(n5088), .Z(n4596) );
HS65_LH_AO22X9 U7384 ( .A(n9055), .B(n9188), .C(n9133), .D(n8934), .Z(
\u_DataPath/jump_address_i [24]) );
HS65_LH_AO22X9 U7388 ( .A(n9260), .B(n9188), .C(n9133), .D(n9054), .Z(
\u_DataPath/jump_address_i [26]) );
HS65_LH_AO222X4 U7389 ( .A(n7896), .B(\u_DataPath/pc_4_i [30]), .C(n7893),
.D(\u_DataPath/jump_address_i [30]), .E(n9025), .F(n7887), .Z(n8642)
);
HS65_LH_IVX9 U7390 ( .A(n4550), .Z(n4863) );
HS65_LL_NOR2X3 U7391 ( .A(n4726), .B(n4966), .Z(n5503) );
HS65_LH_IVX9 U7392 ( .A(\lte_x_59/B[4] ), .Z(n4796) );
HS65_LH_AOI21X2 U7400 ( .A(n5648), .B(n4147), .C(n5647), .Z(n4165) );
HS65_LH_IVX9 U7402 ( .A(n4458), .Z(n4949) );
HS65_LL_NOR2AX6 U7403 ( .A(n5088), .B(n3425), .Z(n3426) );
HS65_LH_NOR2X6 U7406 ( .A(n7785), .B(n7784), .Z(n7786) );
HS65_LL_OAI12X3 U7407 ( .A(n5952), .B(n5955), .C(n5954), .Z(n6119) );
HS65_LH_OAI21X3 U7410 ( .A(n9246), .B(n8453), .C(n9086), .Z(
\u_DataPath/from_mem_data_out_i [28]) );
HS65_LL_NOR2X6 U7416 ( .A(n3106), .B(n3105), .Z(\lte_x_59/B[7] ) );
HS65_LH_IVX9 U7417 ( .A(n4699), .Z(n3376) );
HS65_LL_AO12X4 U7418 ( .A(n3274), .B(n3270), .C(n3269), .Z(n2925) );
HS65_LH_IVX9 U7419 ( .A(n4967), .Z(n5417) );
HS65_LH_AO222X4 U7420 ( .A(n7896), .B(\u_DataPath/pc_4_i [24]), .C(n7893),
.D(\u_DataPath/jump_address_i [24]), .E(n8931), .F(n7887), .Z(n8648)
);
HS65_LHS_XOR2X3 U7421 ( .A(n7795), .B(n7794), .Z(
\u_DataPath/u_execute/link_value_i [27]) );
HS65_LH_AO222X4 U7422 ( .A(n7896), .B(\u_DataPath/pc_4_i [29]), .C(n7893),
.D(n9417), .E(n9164), .F(n7887), .Z(n8643) );
HS65_LH_AO222X4 U7423 ( .A(n7895), .B(\u_DataPath/pc_4_i [17]), .C(n7892),
.D(n9406), .E(n8928), .F(n7888), .Z(n8655) );
HS65_LH_IVX9 U7424 ( .A(n5021), .Z(n4985) );
HS65_LH_AO22X9 U7425 ( .A(n9254), .B(n8797), .C(n9240), .D(n8992), .Z(
\u_DataPath/pc4_to_idexreg_i [24]) );
HS65_LH_AO22X9 U7426 ( .A(n9254), .B(n8796), .C(n9132), .D(n8993), .Z(
\u_DataPath/pc4_to_idexreg_i [29]) );
HS65_LH_AO22X9 U7427 ( .A(n9254), .B(n8795), .C(n9240), .D(n8994), .Z(
\u_DataPath/pc4_to_idexreg_i [17]) );
HS65_LL_NAND2AX7 U7428 ( .A(n2922), .B(n3277), .Z(n5062) );
HS65_LH_AOI22X3 U7430 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][18] ), .B(n7524),
.C(n6683), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][18] ), .Z(n6344)
);
HS65_LH_OAI22X6 U7431 ( .A(n3264), .B(\u_DataPath/dataOut_exe_i [21]), .C(
n8364), .D(n3409), .Z(n3060) );
HS65_LL_NAND2X5 U7432 ( .A(n3164), .B(n3163), .Z(n4967) );
HS65_LH_IVX9 U7433 ( .A(n5654), .Z(n2869) );
HS65_LH_NOR2X5 U7434 ( .A(n9399), .B(n3341), .Z(n3066) );
HS65_LH_AO22X9 U7435 ( .A(n8793), .B(n9138), .C(n9331), .D(n9153), .Z(
opcode_i[3]) );
HS65_LH_AO22X9 U7436 ( .A(n8792), .B(n9138), .C(n9329), .D(n9153), .Z(
opcode_i[1]) );
HS65_LH_NAND2X4 U7437 ( .A(n9281), .B(n8399), .Z(n8273) );
HS65_LH_NAND2X4 U7438 ( .A(n9282), .B(n8399), .Z(n8334) );
HS65_LH_AO22X9 U7439 ( .A(n8791), .B(n9252), .C(n9317), .D(n9069), .Z(
\u_DataPath/immediate_ext_dec_i [14]) );
HS65_LH_NAND2X4 U7440 ( .A(n9283), .B(n8399), .Z(n8295) );
HS65_LH_AO22X9 U7441 ( .A(n8790), .B(n9252), .C(n9316), .D(n9069), .Z(
\u_DataPath/immediate_ext_dec_i [13]) );
HS65_LH_NAND2X4 U7442 ( .A(n9284), .B(n8399), .Z(n8346) );
HS65_LH_AO22X9 U7443 ( .A(n8789), .B(n9252), .C(n9315), .D(n9069), .Z(
\u_DataPath/immediate_ext_dec_i [12]) );
HS65_LH_AO22X9 U7444 ( .A(n8788), .B(n9252), .C(n9314), .D(n9069), .Z(
\u_DataPath/immediate_ext_dec_i [11]) );
HS65_LH_NAND2X4 U7446 ( .A(n9286), .B(n8399), .Z(n8341) );
HS65_LH_NAND2X4 U7447 ( .A(n9287), .B(n8399), .Z(n8400) );
HS65_LH_NAND2X4 U7448 ( .A(n9288), .B(n8399), .Z(n8308) );
HS65_LH_AO22X9 U7449 ( .A(n8787), .B(n9252), .C(n9321), .D(n9141), .Z(
\u_DataPath/jaddr_i [18]) );
HS65_LH_BFX9 U7451 ( .A(n8443), .Z(n7901) );
HS65_LHS_XNOR2X6 U7452 ( .A(n7705), .B(n7780), .Z(\u_DataPath/pc_4_i [29])
);
HS65_LH_AO222X4 U7453 ( .A(n7895), .B(\u_DataPath/pc_4_i [22]), .C(n7892),
.D(\u_DataPath/jump_address_i [22]), .E(n8929), .F(n7887), .Z(n8650)
);
HS65_LL_OR2X4 U7455 ( .A(n8800), .B(n3341), .Z(n2903) );
HS65_LH_AO222X4 U7457 ( .A(n7896), .B(\u_DataPath/pc_4_i [28]), .C(n7893),
.D(\u_DataPath/jump_address_i [28]), .E(n8941), .F(n7887), .Z(n8644)
);
HS65_LH_OAI22X6 U7458 ( .A(n3264), .B(\u_DataPath/dataOut_exe_i [12]), .C(
n8255), .D(n3409), .Z(n3265) );
HS65_LL_NAND2X5 U7459 ( .A(n3263), .B(n3262), .Z(n5048) );
HS65_LH_AO22X9 U7460 ( .A(n8785), .B(n9138), .C(n9322), .D(n9153), .Z(
\u_DataPath/jaddr_i [19]) );
HS65_LH_AO22X9 U7462 ( .A(n8784), .B(n9253), .C(n9310), .D(n9142), .Z(
\u_DataPath/immediate_ext_dec_i [7]) );
HS65_LH_AO22X9 U7463 ( .A(n8783), .B(n9253), .C(n9311), .D(n9142), .Z(
\u_DataPath/immediate_ext_dec_i [8]) );
HS65_LH_AO22X9 U7465 ( .A(n8781), .B(n9253), .C(n9313), .D(n9142), .Z(
\u_DataPath/immediate_ext_dec_i [10]) );
HS65_LH_AO22X9 U7467 ( .A(n8779), .B(n9252), .C(n9308), .D(n9069), .Z(
\u_DataPath/immediate_ext_dec_i [5]) );
HS65_LH_AO22X9 U7468 ( .A(n8778), .B(n9252), .C(n9309), .D(n9069), .Z(
\u_DataPath/immediate_ext_dec_i [6]) );
HS65_LH_AO222X4 U7469 ( .A(n7895), .B(\u_DataPath/pc_4_i [23]), .C(n7892),
.D(n9414), .E(n9197), .F(n7887), .Z(n8649) );
HS65_LH_NAND2X7 U7470 ( .A(n9207), .B(n7122), .Z(n7794) );
HS65_LH_AO222X4 U7471 ( .A(n7895), .B(\u_DataPath/pc_4_i [21]), .C(n7892),
.D(n9405), .E(n9193), .F(n7887), .Z(n8651) );
HS65_LH_AO222X4 U7472 ( .A(n7895), .B(\u_DataPath/pc_4_i [16]), .C(n7892),
.D(\u_DataPath/jump_address_i [16]), .E(n9194), .F(n7888), .Z(n8656)
);
HS65_LHS_XNOR2X6 U7474 ( .A(n3121), .B(n7687), .Z(\u_DataPath/pc_4_i [24])
);
HS65_LH_AO22X9 U7475 ( .A(n8776), .B(n9252), .C(n9303), .D(n9069), .Z(
\u_DataPath/immediate_ext_dec_i [0]) );
HS65_LH_AO22X9 U7477 ( .A(n8772), .B(n9252), .C(n9306), .D(n9069), .Z(
\u_DataPath/immediate_ext_dec_i [3]) );
HS65_LHS_XOR2X6 U7479 ( .A(n7769), .B(n7768), .Z(\u_DataPath/pc_4_i [21]) );
HS65_LHS_XOR2X3 U7481 ( .A(n5975), .B(n5974), .Z(
\u_DataPath/u_execute/resAdd1_i [25]) );
HS65_LH_OAI21X3 U7482 ( .A(n8494), .B(n8390), .C(n8493), .Z(
\u_DataPath/mem_writedata_out_i [4]) );
HS65_LHS_XOR2X6 U7483 ( .A(n7766), .B(n7765), .Z(\u_DataPath/pc_4_i [23]) );
HS65_LL_AO12X4 U7484 ( .A(n3414), .B(n8491), .C(n3413), .Z(n3425) );
HS65_LL_NAND3AX3 U7485 ( .A(n3162), .B(n3161), .C(n8548), .Z(n3163) );
HS65_LHS_XOR2X6 U7486 ( .A(n7756), .B(n7755), .Z(\u_DataPath/pc_4_i [22]) );
HS65_LHS_XOR2X3 U7487 ( .A(n7799), .B(n7798), .Z(
\u_DataPath/u_execute/link_value_i [25]) );
HS65_LL_OR2X4 U7488 ( .A(n3171), .B(n8544), .Z(n2905) );
HS65_LH_AO222X4 U7489 ( .A(n7896), .B(\u_DataPath/pc_4_i [27]), .C(n7893),
.D(n9416), .E(n9264), .F(n7887), .Z(n8645) );
HS65_LH_BFX9 U7490 ( .A(n8482), .Z(n7920) );
HS65_LH_NOR3X2 U7491 ( .A(n8773), .B(n9099), .C(n8114), .Z(n8129) );
HS65_LH_NOR2X3 U7492 ( .A(n9083), .B(n8916), .Z(\u_DataPath/cw_exmem_i [6])
);
HS65_LHS_XOR2X6 U7493 ( .A(n3122), .B(n7754), .Z(\u_DataPath/pc_4_i [16]) );
HS65_LL_NOR3X1 U7495 ( .A(n8775), .B(n9169), .C(n8114), .Z(n8082) );
HS65_LL_NOR3X1 U7496 ( .A(n8771), .B(n9003), .C(n8114), .Z(n8106) );
HS65_LL_NAND3X3 U7497 ( .A(n4714), .B(n8562), .C(n8561), .Z(n4974) );
HS65_LL_OA31X4 U7498 ( .A(n9401), .B(n3288), .C(n4713), .D(n3287), .Z(n2910)
);
HS65_LL_NAND2AX4 U7499 ( .A(n3194), .B(n8532), .Z(n3196) );
HS65_LL_NAND3AX3 U7501 ( .A(n3228), .B(n3227), .C(n6124), .Z(n3229) );
HS65_LL_OAI22X3 U7502 ( .A(n3333), .B(\u_DataPath/dataOut_exe_i [6]), .C(
n8311), .D(n3340), .Z(n3319) );
HS65_LHS_XNOR2X6 U7503 ( .A(n2831), .B(n7767), .Z(\u_DataPath/pc_4_i [20])
);
HS65_LHS_XNOR2X6 U7504 ( .A(n3123), .B(n7677), .Z(\u_DataPath/pc_4_i [14])
);
HS65_LHS_XNOR2X3 U7505 ( .A(n7121), .B(n7120), .Z(
\u_DataPath/u_execute/link_value_i [24]) );
HS65_LH_NAND2X7 U7506 ( .A(n3292), .B(n3291), .Z(n3397) );
HS65_LHS_XNOR2X6 U7507 ( .A(n6068), .B(n6067), .Z(
\u_DataPath/u_execute/resAdd1_i [19]) );
HS65_LL_OAI22X3 U7508 ( .A(n3264), .B(\u_DataPath/dataOut_exe_i [8]), .C(
n8265), .D(n3340), .Z(n3213) );
HS65_LL_OAI12X12 U7509 ( .A(n8141), .B(n8147), .C(n2733), .Z(
\u_DataPath/u_decode_unit/reg_file0/N151 ) );
HS65_LH_NAND2X5 U7510 ( .A(n2896), .B(n3189), .Z(n8534) );
HS65_LHS_XNOR2X6 U7511 ( .A(n9357), .B(n7655), .Z(\u_DataPath/pc_4_i [13])
);
HS65_LL_OAI13X5 U7512 ( .A(n3329), .B(n8501), .C(n8500), .D(n3328), .Z(n5030) );
HS65_LH_AND2X4 U7513 ( .A(n4714), .B(n8521), .Z(n3279) );
HS65_LL_OAI12X18 U7514 ( .A(n8147), .B(n8150), .C(n2733), .Z(
\u_DataPath/u_decode_unit/reg_file0/N135 ) );
HS65_LH_NAND2X4 U7515 ( .A(n8566), .B(n8484), .Z(n7870) );
HS65_LL_OAI12X12 U7516 ( .A(n8145), .B(n8148), .C(n2733), .Z(
\u_DataPath/u_decode_unit/reg_file0/N125 ) );
HS65_LL_OAI12X18 U7517 ( .A(n3009), .B(n8150), .C(n2733), .Z(
\u_DataPath/u_decode_unit/reg_file0/N132 ) );
HS65_LH_BFX9 U7518 ( .A(n8456), .Z(n7914) );
HS65_LL_OAI12X18 U7519 ( .A(n3010), .B(n8150), .C(n2733), .Z(
\u_DataPath/u_decode_unit/reg_file0/N137 ) );
HS65_LH_NAND3X3 U7520 ( .A(\u_DataPath/immediate_ext_dec_i [2]), .B(n8120),
.C(n8635), .Z(n8077) );
HS65_LH_AOI12X2 U7521 ( .A(n6057), .B(n6059), .C(n5764), .Z(n5969) );
HS65_LHS_XNOR2X6 U7522 ( .A(n3120), .B(n7674), .Z(\u_DataPath/pc_4_i [25])
);
HS65_LL_NAND2AX4 U7523 ( .A(n7878), .B(n4212), .Z(n4216) );
HS65_LL_NOR3X1 U7525 ( .A(n8542), .B(n4713), .C(n8541), .Z(n3181) );
HS65_LH_BFX9 U7526 ( .A(n8456), .Z(n7916) );
HS65_LH_BFX9 U7527 ( .A(n8456), .Z(n7915) );
HS65_LL_OAI12X12 U7528 ( .A(n3012), .B(n8148), .C(n2733), .Z(
\u_DataPath/u_decode_unit/reg_file0/N126 ) );
HS65_LL_NOR4ABX2 U7529 ( .A(n8269), .B(n8318), .C(n9235), .D(n8268), .Z(
n8272) );
HS65_LH_OAI21X3 U7530 ( .A(n8098), .B(n8097), .C(n8635), .Z(n8094) );
HS65_LL_NOR2AX3 U7532 ( .A(n3219), .B(n3218), .Z(n5693) );
HS65_LH_BFX9 U7533 ( .A(n8287), .Z(n7896) );
HS65_LH_BFX9 U7535 ( .A(n8287), .Z(n7894) );
HS65_LL_OAI21X2 U7536 ( .A(n3284), .B(n4714), .C(n3283), .Z(n3289) );
HS65_LH_OAI12X3 U7537 ( .A(n5763), .B(n5773), .C(n5762), .Z(n5864) );
HS65_LL_NAND2X7 U7538 ( .A(n7306), .B(n7095), .Z(n7096) );
HS65_LH_OAI12X3 U7539 ( .A(n6066), .B(n6065), .C(n6064), .Z(n6067) );
HS65_LHS_XOR2X3 U7540 ( .A(n6030), .B(n6029), .Z(
\u_DataPath/u_execute/resAdd1_i [23]) );
HS65_LH_BFX9 U7541 ( .A(n8287), .Z(n7895) );
HS65_LH_AND2X4 U7542 ( .A(n8537), .B(n2866), .Z(n2894) );
HS65_LL_OAI12X3 U7543 ( .A(n6026), .B(n6029), .C(n6028), .Z(n6107) );
HS65_LL_NAND2AX4 U7544 ( .A(n8332), .B(n2866), .Z(n8505) );
HS65_LL_OA12X4 U7545 ( .A(n4713), .B(n3347), .C(n3346), .Z(n3348) );
HS65_LHS_XOR2X3 U7546 ( .A(n3119), .B(n7759), .Z(\u_DataPath/pc_4_i [26]) );
HS65_LH_BFX9 U7547 ( .A(n8483), .Z(n7924) );
HS65_LHS_XOR2X3 U7548 ( .A(n7797), .B(n7796), .Z(
\u_DataPath/u_execute/link_value_i [23]) );
HS65_LH_NOR2X3 U7549 ( .A(n8719), .B(n4712), .Z(n7878) );
HS65_LL_NAND3X3 U7550 ( .A(n8143), .B(n7619), .C(n7618), .Z(n8148) );
HS65_LH_NOR2X5 U7552 ( .A(n8716), .B(n7802), .Z(n3299) );
HS65_LH_IVX9 U7553 ( .A(n7661), .Z(n7757) );
HS65_LL_AOI12X6 U7554 ( .A(n8161), .B(n8160), .C(n8159), .Z(
\u_DataPath/u_idexreg/N184 ) );
HS65_LH_NAND2X4 U7556 ( .A(n8297), .B(n7802), .Z(n8502) );
HS65_LH_NAND2X7 U7557 ( .A(n3110), .B(n8132), .Z(n8573) );
HS65_LH_NAND2X4 U7559 ( .A(n4187), .B(n7802), .Z(n8572) );
HS65_LH_NOR2X5 U7560 ( .A(n8176), .B(n9401), .Z(n8570) );
HS65_LH_AOI12X2 U7561 ( .A(n5814), .B(n5868), .C(n5813), .Z(n5815) );
HS65_LH_NAND2X4 U7562 ( .A(n8681), .B(n7749), .Z(n7750) );
HS65_LH_NOR2X3 U7563 ( .A(n8364), .B(n9401), .Z(n8542) );
HS65_LH_NOR2X3 U7564 ( .A(n8350), .B(n9401), .Z(n8544) );
HS65_LH_AOI12X2 U7565 ( .A(n6005), .B(n5791), .C(n5790), .Z(n5793) );
HS65_LH_NAND2X5 U7566 ( .A(n3225), .B(n7802), .Z(n8506) );
HS65_LH_OR2X4 U7567 ( .A(n8426), .B(n9401), .Z(n4212) );
HS65_LH_AOI12X2 U7569 ( .A(n6069), .B(n5872), .C(n5984), .Z(n5784) );
HS65_LHS_XNOR2X6 U7570 ( .A(n5889), .B(n5888), .Z(\u_DataPath/toPC2_i [7])
);
HS65_LH_NOR2X3 U7571 ( .A(n8374), .B(n9401), .Z(n8559) );
HS65_LH_AOI12X2 U7572 ( .A(n6005), .B(n5992), .C(n5790), .Z(n5993) );
HS65_LH_AOI31X3 U7573 ( .A(n9117), .B(n9334), .C(n8714), .D(n8424), .Z(n7847) );
HS65_LH_OAI12X3 U7574 ( .A(n5887), .B(n5886), .C(n5885), .Z(n5888) );
HS65_LH_IVX9 U7576 ( .A(n8425), .Z(n8132) );
HS65_LL_NAND2X2 U7578 ( .A(n3217), .B(n3216), .Z(n3218) );
HS65_LL_NOR4ABX2 U7579 ( .A(n3053), .B(n3052), .C(n3051), .D(n3034), .Z(
n3055) );
HS65_LL_NAND2X7 U7581 ( .A(n8566), .B(n2877), .Z(n8235) );
HS65_LHS_XOR2X3 U7582 ( .A(n5700), .B(n7710), .Z(n4288) );
HS65_LH_NAND2X4 U7585 ( .A(n9214), .B(n7729), .Z(n4004) );
HS65_LH_BFX9 U7586 ( .A(n7886), .Z(n7887) );
HS65_LH_AOI12X2 U7587 ( .A(n5834), .B(n5892), .C(n5833), .Z(n5886) );
HS65_LH_BFX9 U7588 ( .A(n7886), .Z(n7888) );
HS65_LH_AOI31X2 U7589 ( .A(opcode_i[1]), .B(n9084), .C(n7771), .D(n7309),
.Z(n8119) );
HS65_LH_AOI12X2 U7590 ( .A(n6036), .B(n6095), .C(n6035), .Z(n6089) );
HS65_LH_BFX9 U7592 ( .A(n6683), .Z(n7593) );
HS65_LH_BFX9 U7593 ( .A(n7886), .Z(n7889) );
HS65_LH_BFX9 U7594 ( .A(n6746), .Z(n7516) );
HS65_LH_BFX9 U7595 ( .A(n6172), .Z(n7171) );
HS65_LH_IVX9 U7596 ( .A(n7861), .Z(n8168) );
HS65_LH_BFX9 U7597 ( .A(n6754), .Z(n7525) );
HS65_LH_BFX9 U7600 ( .A(n6635), .Z(n7282) );
HS65_LH_BFX9 U7602 ( .A(n6680), .Z(n7522) );
HS65_LH_BFX9 U7603 ( .A(n6171), .Z(n7285) );
HS65_LH_BFX9 U7607 ( .A(n6739), .Z(n7428) );
HS65_LH_BFX9 U7608 ( .A(n6634), .Z(n7283) );
HS65_LH_BFX9 U7609 ( .A(n8285), .Z(n7886) );
HS65_LL_NOR2X5 U7610 ( .A(n6353), .B(n6333), .Z(n6952) );
HS65_LL_OAI21X2 U7611 ( .A(n5932), .B(n5963), .C(n5931), .Z(n5933) );
HS65_LH_BFX9 U7612 ( .A(n7578), .Z(n7429) );
HS65_LH_BFX9 U7613 ( .A(n6689), .Z(n7603) );
HS65_LHS_XOR2X6 U7614 ( .A(n7745), .B(n7744), .Z(\u_DataPath/pc_4_i [5]) );
HS65_LH_BFX9 U7615 ( .A(n6364), .Z(n6927) );
HS65_LH_OAI211X3 U7617 ( .A(n8089), .B(n7702), .C(n7701), .D(n7700), .Z(
n8125) );
HS65_LH_BFX9 U7618 ( .A(n6745), .Z(n7434) );
HS65_LH_BFX9 U7619 ( .A(n6627), .Z(n7274) );
HS65_LH_BFX9 U7620 ( .A(n7296), .Z(n6942) );
HS65_LH_BFX9 U7621 ( .A(n6625), .Z(n7272) );
HS65_LH_BFX9 U7622 ( .A(n6376), .Z(n7286) );
HS65_LH_IVX9 U7624 ( .A(n7639), .Z(n7640) );
HS65_LH_OAI12X3 U7625 ( .A(n5795), .B(n5800), .C(n5797), .Z(n5807) );
HS65_LL_CB4I1X4 U7626 ( .A(n7834), .B(n5491), .C(n3421), .D(n3422), .Z(n3443) );
HS65_LHS_XOR2X3 U7627 ( .A(\u_DataPath/jaddr_i [16]), .B(n7089), .Z(n7091)
);
HS65_LH_BFX9 U7628 ( .A(n6636), .Z(n7170) );
HS65_LH_BFX9 U7629 ( .A(n6385), .Z(n7297) );
HS65_LH_CBI4I1X5 U7630 ( .A(n9084), .B(n7697), .C(n7688), .D(n8084), .Z(
n7637) );
HS65_LH_IVX4 U7631 ( .A(n5800), .Z(n5801) );
HS65_LH_CNIVX3 U7632 ( .A(n7906), .Z(n7849) );
HS65_LH_BFX9 U7633 ( .A(n6966), .Z(n7333) );
HS65_LHS_XOR2X6 U7634 ( .A(n8163), .B(n7089), .Z(n7077) );
HS65_LH_BFX9 U7635 ( .A(n6967), .Z(n7334) );
HS65_LH_NOR2X2 U7636 ( .A(n9233), .B(n7117), .Z(n7879) );
HS65_LH_BFX9 U7637 ( .A(n6951), .Z(n7415) );
HS65_LH_BFX9 U7638 ( .A(n8282), .Z(n7881) );
HS65_LH_BFX9 U7639 ( .A(n8451), .Z(n7908) );
HS65_LH_NAND2X4 U7640 ( .A(n5863), .B(n6057), .Z(n5865) );
HS65_LH_IVX4 U7641 ( .A(n5780), .Z(n5781) );
HS65_LH_NAND2X4 U7642 ( .A(n6058), .B(n6057), .Z(n6060) );
HS65_LL_NOR2X5 U7643 ( .A(n6148), .B(n6133), .Z(n6629) );
HS65_LH_NAND2X4 U7645 ( .A(n6064), .B(n6009), .Z(n6012) );
HS65_LH_NAND2X4 U7646 ( .A(n6040), .B(n5837), .Z(n6044) );
HS65_LLS_XNOR2X3 U7647 ( .A(n7618), .B(n3031), .Z(n3054) );
HS65_LH_NAND2X4 U7648 ( .A(n5876), .B(n5875), .Z(n5881) );
HS65_LH_NAND2X4 U7649 ( .A(n8685), .B(n7743), .Z(n7744) );
HS65_LH_BFX9 U7650 ( .A(n7890), .Z(n7891) );
HS65_LH_BFX9 U7652 ( .A(n7890), .Z(n7893) );
HS65_LH_NAND2X4 U7653 ( .A(n5896), .B(n6098), .Z(n5901) );
HS65_LH_NAND2X4 U7654 ( .A(n5848), .B(n6046), .Z(n5849) );
HS65_LL_NOR2X5 U7655 ( .A(n6153), .B(n6133), .Z(n6370) );
HS65_LHS_XNOR2X6 U7656 ( .A(n8166), .B(n7618), .Z(n7079) );
HS65_LH_NAND2X4 U7657 ( .A(n5897), .B(n6050), .Z(n5845) );
HS65_LH_NAND2X4 U7658 ( .A(n5789), .B(n6005), .Z(n5774) );
HS65_LL_NOR2X5 U7659 ( .A(n2885), .B(n6133), .Z(n6371) );
HS65_LH_NAND2X4 U7661 ( .A(n6070), .B(n6069), .Z(n6072) );
HS65_LL_NOR2X5 U7662 ( .A(n2886), .B(n6132), .Z(n6627) );
HS65_LH_IVX7 U7664 ( .A(n5121), .Z(n4787) );
HS65_LH_CNIVX3 U7665 ( .A(n8350), .Z(n3167) );
HS65_LH_NAND2X4 U7666 ( .A(n5871), .B(n6069), .Z(n5873) );
HS65_LH_OR2X9 U7667 ( .A(n3345), .B(n4713), .Z(n3349) );
HS65_LL_NOR2X5 U7668 ( .A(n2885), .B(n6151), .Z(n6364) );
HS65_LH_AND2X4 U7669 ( .A(n3327), .B(n9183), .Z(n2921) );
HS65_LL_NAND2AX4 U7670 ( .A(n7619), .B(n2943), .Z(n2945) );
HS65_LH_CNIVX3 U7671 ( .A(n8550), .Z(n3142) );
HS65_LH_NAND2X4 U7672 ( .A(n5978), .B(n5977), .Z(n5986) );
HS65_LH_NAND2X4 U7673 ( .A(n5797), .B(n5796), .Z(n5804) );
HS65_LH_NAND2X4 U7674 ( .A(n5997), .B(n5996), .Z(n6004) );
HS65_LH_NAND2X4 U7678 ( .A(n9219), .B(n7789), .Z(n7790) );
HS65_LH_IVX4 U7679 ( .A(n5981), .Z(n5982) );
HS65_LH_NAND2X4 U7680 ( .A(n5838), .B(n5837), .Z(n5842) );
HS65_LH_NAND2X4 U7681 ( .A(n6006), .B(n6005), .Z(n6008) );
HS65_LH_NAND2X4 U7682 ( .A(n6088), .B(n5831), .Z(n6037) );
HS65_LL_NOR2X5 U7683 ( .A(n6148), .B(n6147), .Z(n6383) );
HS65_LH_NAND2X4 U7684 ( .A(n5891), .B(n5890), .Z(n5893) );
HS65_LH_NAND2X4 U7685 ( .A(n6021), .B(n6020), .Z(n6025) );
HS65_LLS_XNOR2X3 U7687 ( .A(n9004), .B(n7619), .Z(n3050) );
HS65_LH_NAND3X3 U7688 ( .A(n8096), .B(n8157), .C(n8076), .Z(n7700) );
HS65_LL_AND2X4 U7690 ( .A(n2949), .B(n2948), .Z(n2952) );
HS65_LH_NAND2X4 U7691 ( .A(n6087), .B(n5883), .Z(n6092) );
HS65_LH_NAND2X4 U7692 ( .A(n5755), .B(n5958), .Z(n5766) );
HS65_LH_BFX9 U7693 ( .A(n7890), .Z(n7892) );
HS65_LLS_XNOR2X3 U7694 ( .A(\u_DataPath/jaddr_i [19]), .B(n7619), .Z(n7090)
);
HS65_LLS_XNOR2X3 U7695 ( .A(n3029), .B(n7086), .Z(n3048) );
HS65_LH_NAND2X4 U7696 ( .A(n5745), .B(n5744), .Z(n5747) );
HS65_LL_NAND2AX7 U7698 ( .A(n9031), .B(n3030), .Z(n7086) );
HS65_LH_NAND2X4 U7699 ( .A(n6014), .B(n6013), .Z(n6018) );
HS65_LH_NAND2X4 U7700 ( .A(n5903), .B(n5902), .Z(n5905) );
HS65_LL_MUXI21X2 U7701 ( .D0(n3016), .D1(n3015), .S0(n3404), .Z(n4175) );
HS65_LH_NOR2AX3 U7702 ( .A(n3024), .B(n3404), .Z(n3025) );
HS65_LL_AND2X4 U7703 ( .A(n2962), .B(n2960), .Z(n2935) );
HS65_LH_IVX4 U7704 ( .A(n6022), .Z(n6081) );
HS65_LH_NAND2X4 U7705 ( .A(n5806), .B(n5805), .Z(n5810) );
HS65_LL_AND2X4 U7706 ( .A(\u_DataPath/cw_memwb_i [2]), .B(n2960), .Z(n2961)
);
HS65_LH_MUXI21X5 U7707 ( .D0(n3098), .D1(n9377), .S0(
\u_DataPath/cw_towb_i [0]), .Z(n8427) );
HS65_LL_NAND2X5 U7708 ( .A(n3030), .B(n2942), .Z(n7619) );
HS65_LH_MUXI21X2 U7709 ( .D0(n3166), .D1(n9380), .S0(
\u_DataPath/cw_towb_i [0]), .Z(n8350) );
HS65_LH_MUXI21X2 U7711 ( .D0(n8914), .D1(
\u_DataPath/from_mem_data_out_i [28]), .S0(n3404), .Z(n8383) );
HS65_LH_OAI12X3 U7713 ( .A(n5877), .B(n5874), .C(n5876), .Z(n5780) );
HS65_LH_OAI12X3 U7714 ( .A(n6082), .B(n6019), .C(n6021), .Z(n6010) );
HS65_LHS_XNOR2X3 U7715 ( .A(n8687), .B(n3126), .Z(\u_DataPath/pc_4_i [3]) );
HS65_LH_OAI12X3 U7716 ( .A(n5871), .B(n5775), .C(n5777), .Z(n5725) );
HS65_LH_NOR2X3 U7718 ( .A(n7613), .B(n8932), .Z(n7616) );
HS65_LH_BFX9 U7719 ( .A(n8286), .Z(n7890) );
HS65_LH_OAI12X3 U7720 ( .A(n5897), .B(n5894), .C(n5896), .Z(n5719) );
HS65_LH_BFX9 U7721 ( .A(n8283), .Z(n7883) );
HS65_LH_NOR2X3 U7722 ( .A(n8163), .B(rst), .Z(\u_DataPath/rs_ex_i [0]) );
HS65_LH_NOR2X3 U7723 ( .A(n2881), .B(rst), .Z(\u_DataPath/idex_rt_i [4]) );
HS65_LH_OAI12X3 U7724 ( .A(n5891), .B(n5836), .C(n5838), .Z(n5833) );
HS65_LH_NOR2X3 U7725 ( .A(n8184), .B(rst), .Z(\u_DataPath/idex_rt_i [2]) );
HS65_LH_NOR2X3 U7726 ( .A(n8153), .B(rst), .Z(\u_DataPath/idex_rt_i [1]) );
HS65_LH_OAI12X3 U7728 ( .A(n6100), .B(n6097), .C(n6099), .Z(n5921) );
HS65_LH_OAI12X3 U7729 ( .A(n6094), .B(n6038), .C(n6040), .Z(n6035) );
HS65_LH_OAI12X3 U7730 ( .A(n5885), .B(n5882), .C(n5884), .Z(n5721) );
HS65_LH_IVX9 U7731 ( .A(n3470), .Z(n3416) );
HS65_LH_OAI12X3 U7732 ( .A(n5863), .B(n5753), .C(n5755), .Z(n5727) );
HS65_LL_OR2X4 U7733 ( .A(\u_DataPath/jaddr_i [19]), .B(n2881), .Z(n2880) );
HS65_LH_NAND2X7 U7735 ( .A(n2983), .B(n2984), .Z(n7638) );
HS65_LH_NAND2X4 U7736 ( .A(n5812), .B(n5811), .Z(n5816) );
HS65_LL_NAND2AX4 U7737 ( .A(\u_DataPath/jaddr_i [20]), .B(n6339), .Z(n6332)
);
HS65_LH_BFX9 U7738 ( .A(n8283), .Z(n7884) );
HS65_LH_NAND2AX7 U7739 ( .A(n8480), .B(n9151), .Z(n8263) );
HS65_LH_NAND2AX7 U7740 ( .A(n8480), .B(n8910), .Z(n8231) );
HS65_LH_OR2X9 U7741 ( .A(n9343), .B(n9217), .Z(n5805) );
HS65_LH_NOR2X3 U7742 ( .A(n9235), .B(n8915), .Z(n2973) );
HS65_LH_IVX9 U7744 ( .A(\u_DataPath/dataOut_exe_i [3]), .Z(n3307) );
HS65_LHS_XNOR2X6 U7747 ( .A(\u_DataPath/jaddr_i [19]), .B(n9077), .Z(n7100)
);
HS65_LH_CNIVX3 U7748 ( .A(\u_DataPath/dataOut_exe_i [0]), .Z(n8131) );
HS65_LL_IVX4 U7750 ( .A(\u_DataPath/cw_to_ex_i [3]), .Z(n5491) );
HS65_LH_IVX4 U7752 ( .A(n9225), .Z(n7788) );
HS65_LH_CNIVX3 U7753 ( .A(\u_DataPath/cw_to_ex_i [4]), .Z(n3448) );
HS65_LH_OR2X9 U7754 ( .A(n9341), .B(n9220), .Z(n5811) );
HS65_LL_IVX4 U7755 ( .A(\u_DataPath/cw_to_ex_i [2]), .Z(n5492) );
HS65_LH_NOR2X5 U7757 ( .A(n9033), .B(n9215), .Z(n6097) );
HS65_LH_NOR2X5 U7758 ( .A(n9039), .B(n9116), .Z(n6102) );
HS65_LH_OR2X9 U7759 ( .A(n9341), .B(n9204), .Z(n5858) );
HS65_LH_OR2X4 U7761 ( .A(n9035), .B(n9115), .Z(n5717) );
HS65_LH_IVX9 U7762 ( .A(\u_DataPath/jaddr_i [18]), .Z(n8184) );
HS65_LH_NOR2X5 U7765 ( .A(n8967), .B(n9220), .Z(n6066) );
HS65_LH_NOR2X3 U7766 ( .A(n9077), .B(n9218), .Z(n6061) );
HS65_LH_IVX9 U7767 ( .A(n8961), .Z(\u_DataPath/cw_memwb_i [2]) );
HS65_LH_OR2X9 U7768 ( .A(n9342), .B(n9208), .Z(n5914) );
HS65_LH_NOR2X5 U7769 ( .A(n9181), .B(n9226), .Z(n5960) );
HS65_LH_IVX7 U7770 ( .A(n8682), .Z(n7667) );
HS65_LH_IVX9 U7772 ( .A(n8700), .Z(n3120) );
HS65_LLS_XNOR2X3 U7773 ( .A(n8966), .B(n8766), .Z(n2962) );
HS65_LH_NOR2X5 U7774 ( .A(n9183), .B(n9232), .Z(n5976) );
HS65_LH_NOR2X5 U7775 ( .A(n9171), .B(n9214), .Z(n5979) );
HS65_LH_NOR2X5 U7777 ( .A(n9185), .B(n9230), .Z(n5990) );
HS65_LH_IVX4 U7778 ( .A(n9222), .Z(n7715) );
HS65_LL_NOR2AX3 U7781 ( .A(n3267), .B(n3814), .Z(n4919) );
HS65_LL_NAND4ABX3 U7782 ( .A(n4603), .B(n4602), .C(n4601), .D(n4600), .Z(
n4604) );
HS65_LL_AO12X4 U7783 ( .A(n3030), .B(n8139), .C(n2947), .Z(n2948) );
HS65_LLS_XNOR2X3 U7785 ( .A(n4248), .B(n4247), .Z(n4249) );
HS65_LH_NOR2X2 U7786 ( .A(n9077), .B(n9218), .Z(n2875) );
HS65_LH_CBI4I6X2 U7787 ( .A(n9346), .B(n5417), .C(n3529), .D(n2860), .Z(
n3709) );
HS65_LH_CNIVX3 U7788 ( .A(n9215), .Z(n7706) );
HS65_LL_NOR2AX3 U7789 ( .A(n3472), .B(n3560), .Z(n5257) );
HS65_LLS_XNOR2X3 U7790 ( .A(n8943), .B(n2847), .Z(n3053) );
HS65_LLS_XNOR2X3 U7791 ( .A(n8151), .B(n7619), .Z(n7078) );
HS65_LLS_XNOR2X3 U7792 ( .A(n8763), .B(n8969), .Z(n3035) );
HS65_LL_AOI12X2 U7794 ( .A(n5297), .B(n5466), .C(n5300), .Z(n4685) );
HS65_LL_NOR2X2 U7795 ( .A(n5041), .B(n4583), .Z(n3764) );
HS65_LL_NAND3X2 U7796 ( .A(n5534), .B(n5533), .C(n5532), .Z(n5535) );
HS65_LL_AOI12X2 U7797 ( .A(n4431), .B(n4204), .C(n4203), .Z(n4228) );
HS65_LL_AND3X4 U7798 ( .A(n4708), .B(n5432), .C(n5416), .Z(n2904) );
HS65_LLS_XNOR2X3 U7799 ( .A(n4021), .B(n4020), .Z(n5284) );
HS65_LL_NAND2X2 U7800 ( .A(n3426), .B(n4839), .Z(n4432) );
HS65_LL_OA22X4 U7801 ( .A(n3264), .B(\u_DataPath/dataOut_exe_i [30]), .C(
n8380), .D(n3409), .Z(n2916) );
HS65_LLS_XNOR2X3 U7802 ( .A(n4907), .B(n4906), .Z(n4908) );
HS65_LLS_XNOR2X3 U7803 ( .A(n5613), .B(n5612), .Z(n5642) );
HS65_LL_NOR2X2 U7804 ( .A(n4333), .B(n4328), .Z(n4304) );
HS65_LL_NOR2AX3 U7805 ( .A(n4297), .B(n4296), .Z(n4298) );
HS65_LL_NAND2X7 U7806 ( .A(n3230), .B(n3229), .Z(n5053) );
HS65_LL_NAND3X2 U7807 ( .A(n5450), .B(n4996), .C(n5449), .Z(n4992) );
HS65_LL_NOR2X3 U7808 ( .A(\lte_x_59/B[9] ), .B(n2871), .Z(n5396) );
HS65_LH_CNIVX3 U7810 ( .A(n9231), .Z(n7783) );
HS65_LL_NAND3X2 U7811 ( .A(n5534), .B(n5533), .C(n4988), .Z(n4989) );
HS65_LL_IVX2 U7812 ( .A(n5355), .Z(n5467) );
HS65_LL_AOI12X2 U7813 ( .A(n5068), .B(n5067), .C(n5066), .Z(n5069) );
HS65_LH_AOI21X2 U7815 ( .A(\lte_x_59/B[28] ), .B(n4488), .C(n3447), .Z(n3453) );
HS65_LH_CNIVX3 U7817 ( .A(n5081), .Z(n4990) );
HS65_LH_OAI21X2 U7818 ( .A(n3515), .B(n4987), .C(n5529), .Z(n4988) );
HS65_LH_CBI4I1X3 U7820 ( .A(n5587), .B(n5586), .C(n5585), .D(n5584), .Z(
n5588) );
HS65_LH_CBI4I1X3 U7821 ( .A(n5370), .B(n5369), .C(n5484), .D(n5368), .Z(
n5371) );
HS65_LH_CNIVX3 U7822 ( .A(n5482), .Z(n5353) );
HS65_LHS_XOR2X3 U7823 ( .A(n4985), .B(\lte_x_59/B[16] ), .Z(n4857) );
HS65_LH_NOR2X6 U7824 ( .A(n2840), .B(n5089), .Z(n3969) );
HS65_LH_CNIVX3 U7825 ( .A(n3803), .Z(n3686) );
HS65_LH_OAI21X3 U7826 ( .A(n4502), .B(n4889), .C(n4080), .Z(n4363) );
HS65_LH_BFX9 U7827 ( .A(n6690), .Z(n7604) );
HS65_LH_AOI22X1 U7828 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][27] ), .B(n6617),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[14][27] ), .D(
n6362), .Z(n6208) );
HS65_LH_AOI22X1 U7829 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][11] ), .B(n6617),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[14][11] ), .D(
n6362), .Z(n6248) );
HS65_LH_AOI22X1 U7831 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][26] ), .B(n7525),
.C(n7594), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][26] ), .Z(n7325)
);
HS65_LH_AOI22X1 U7832 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][23] ), .B(n6617),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[14][23] ), .D(
n6362), .Z(n6228) );
HS65_LH_AOI22X1 U7833 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][25] ), .B(n6617),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[14][25] ), .D(
n6362), .Z(n7146) );
HS65_LH_AOI22X1 U7834 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][28] ), .B(n7297),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[0][28] ), .D(
n7296), .Z(n6919) );
HS65_LH_BFX9 U7835 ( .A(n6684), .Z(n7594) );
HS65_LH_NOR2X6 U7836 ( .A(n6153), .B(n6152), .Z(n7296) );
HS65_LH_AOI22X1 U7837 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][17] ), .B(n7525),
.C(n7594), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][17] ), .Z(n6815)
);
HS65_LH_AOI22X1 U7838 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][17] ), .B(n7415),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[10][17] ), .D(
n2891), .Z(n6810) );
HS65_LH_AOI22X1 U7839 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][18] ), .B(n7297),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[0][18] ), .D(
n7296), .Z(n6662) );
HS65_LH_BFX9 U7840 ( .A(n6753), .Z(n7524) );
HS65_LH_AOI22X1 U7841 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][1] ), .B(n7525),
.C(n7594), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][1] ), .Z(n6835)
);
HS65_LH_AO22X4 U7842 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][1] ), .B(n7517),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[4][1] ), .D(n7318), .Z(n6832) );
HS65_LH_BFX9 U7843 ( .A(n7295), .Z(n6941) );
HS65_LH_AOI22X1 U7844 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][31] ), .B(n7297),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[0][31] ), .D(
n7296), .Z(n6879) );
HS65_LH_NOR2X6 U7845 ( .A(n6348), .B(n6333), .Z(n7320) );
HS65_LL_NOR2AX3 U7847 ( .A(n3075), .B(n3074), .Z(n3077) );
HS65_LH_AOI312X2 U7848 ( .A(opcode_i[1]), .B(n7777), .C(n7693), .D(n9082),
.E(n7692), .F(n7691), .Z(n8102) );
HS65_LH_OAI21X2 U7849 ( .A(n7697), .B(n8055), .C(n9082), .Z(n7683) );
HS65_LH_CNIVX3 U7850 ( .A(n4655), .Z(n4656) );
HS65_LH_CBI4I6X2 U7851 ( .A(n5549), .B(n5548), .C(n5547), .D(n5546), .Z(
n5553) );
HS65_LL_NOR2AX3 U7852 ( .A(n5504), .B(n5571), .Z(n5574) );
HS65_LL_NOR2AX3 U7853 ( .A(n2853), .B(n5567), .Z(n5343) );
HS65_LH_NOR2X2 U7854 ( .A(n4973), .B(n4972), .Z(n4975) );
HS65_LH_AOI22X1 U7855 ( .A(n4717), .B(n4715), .C(n4714), .D(n3133), .Z(n4716) );
HS65_LH_CBI4I6X2 U7856 ( .A(n5332), .B(n5331), .C(n5330), .D(n5329), .Z(
n5337) );
HS65_LH_NAND3X2 U7857 ( .A(n5328), .B(n5327), .C(n5326), .Z(n5329) );
HS65_LH_NAND2X2 U7858 ( .A(n9376), .B(n8549), .Z(n3162) );
HS65_LL_NAND2AX4 U7859 ( .A(n3588), .B(n3587), .Z(n3589) );
HS65_LH_OAI22X1 U7860 ( .A(n5041), .B(n4583), .C(n3756), .D(n4796), .Z(n4463) );
HS65_LH_NOR2AX3 U7861 ( .A(n2864), .B(n5004), .Z(n3841) );
HS65_LH_NOR2X2 U7862 ( .A(n9346), .B(n4724), .Z(n3424) );
HS65_LH_NOR4ABX2 U7863 ( .A(n5293), .B(n5275), .C(n5360), .D(n5354), .Z(
n5341) );
HS65_LH_CNIVX3 U7864 ( .A(n5352), .Z(n5288) );
HS65_LHS_XOR2X3 U7865 ( .A(\lte_x_59/B[7] ), .B(n5030), .Z(n4771) );
HS65_LH_CNIVX3 U7866 ( .A(n4876), .Z(n4877) );
HS65_LL_NAND4ABX3 U7867 ( .A(n3841), .B(n3840), .C(n3839), .D(n3838), .Z(
n4835) );
HS65_LH_NAND2X7 U7869 ( .A(n7665), .B(n7646), .Z(n7653) );
HS65_LH_CNIVX3 U7870 ( .A(n3629), .Z(n3630) );
HS65_LH_AOI22X1 U7872 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][27] ), .B(n7604),
.C(n6967), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][27] ), .Z(n7464)
);
HS65_LH_AOI22X1 U7873 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][14] ), .B(n6617),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[14][14] ), .D(
n6362), .Z(n6308) );
HS65_LH_AOI22X1 U7874 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][14] ), .B(n7524),
.C(n6683), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][14] ), .Z(n7376)
);
HS65_LH_AOI22X1 U7875 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][3] ), .B(n7525),
.C(n7594), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][3] ), .Z(n7395)
);
HS65_LH_AOI22X1 U7876 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][10] ), .B(n7524),
.C(n6683), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][10] ), .Z(n7213)
);
HS65_LH_AO22X4 U7877 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][30] ), .B(n2891),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[14][30] ), .D(
n7415), .Z(n7418) );
HS65_LH_AOI22X1 U7878 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][13] ), .B(n6617),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[14][13] ), .D(
n6362), .Z(n7164) );
HS65_LH_AOI22X1 U7879 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][29] ), .B(n7604),
.C(n6967), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][29] ), .Z(n7530)
);
HS65_LH_CBI4I1X3 U7880 ( .A(n5648), .B(n5422), .C(n4488), .D(
\sub_x_53/A[29] ), .Z(n4361) );
HS65_LH_AOI22X1 U7882 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][21] ), .B(n6617),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[14][21] ), .D(
n6362), .Z(n6188) );
HS65_LH_AOI22X1 U7883 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][21] ), .B(n7604),
.C(n6967), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][21] ), .Z(n7605)
);
HS65_LH_AOI22X1 U7884 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][21] ), .B(n6754),
.C(n7594), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][21] ), .Z(n7595)
);
HS65_LH_AOI22X1 U7885 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][5] ), .B(n7524),
.C(n6683), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][5] ), .Z(n6708)
);
HS65_LH_AOI22X1 U7886 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][24] ), .B(n6617),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[14][24] ), .D(
n6362), .Z(n6288) );
HS65_LH_AOI22X1 U7887 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][24] ), .B(n7604),
.C(n6967), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][24] ), .Z(n7570)
);
HS65_LH_AOI22X1 U7888 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][28] ), .B(n7525),
.C(n7594), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][28] ), .Z(n7500)
);
HS65_LH_AOI22X1 U7889 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][28] ), .B(n7604),
.C(n6967), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][28] ), .Z(n7504)
);
HS65_LH_AOI22X1 U7890 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][16] ), .B(n7604),
.C(n6967), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][16] ), .Z(n7550)
);
HS65_LH_AOI22X1 U7891 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][16] ), .B(n6754),
.C(n7594), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][16] ), .Z(n7546)
);
HS65_LH_AOI22X1 U7892 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][6] ), .B(n7524),
.C(n6683), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][6] ), .Z(n7253)
);
HS65_LH_BFX9 U7893 ( .A(n7319), .Z(n7586) );
HS65_LH_BFX9 U7894 ( .A(n7329), .Z(n7599) );
HS65_LH_BFX9 U7895 ( .A(n7331), .Z(n7601) );
HS65_LH_AOI22X1 U7896 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][0] ), .B(n7604),
.C(n6967), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][0] ), .Z(n7444)
);
HS65_LH_AOI22X1 U7897 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][0] ), .B(n7524),
.C(n7593), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][0] ), .Z(n7441)
);
HS65_LH_NOR2X2 U7898 ( .A(\u_DataPath/immediate_ext_dec_i [0]), .B(n8157),
.Z(n8122) );
HS65_LH_NAND2X2 U7899 ( .A(\u_DataPath/jaddr_i [22]), .B(n8163), .Z(n6146)
);
HS65_LH_AO22X4 U7905 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][27] ), .B(n6317),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[13][27] ), .D(
n7292), .Z(n6219) );
HS65_LH_AOI22X1 U7906 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][27] ), .B(n6385),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[0][27] ), .D(
n7296), .Z(n6217) );
HS65_LH_AO22X4 U7907 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][27] ), .B(n2884),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][27] ), .D(
n6382), .Z(n6220) );
HS65_LH_AO22X4 U7908 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][27] ), .B(n6634),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[20][27] ), .D(
n6635), .Z(n6216) );
HS65_LH_AOI22X1 U7909 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][27] ), .B(n6377),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[22][27] ), .D(
n6172), .Z(n6213) );
HS65_LH_AO22X4 U7910 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][27] ), .B(n9374),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[6][27] ), .D(
n6619), .Z(n6205) );
HS65_LH_AOI22X1 U7911 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][27] ), .B(n6162),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[11][27] ), .D(
n6363), .Z(n6207) );
HS65_LH_AO22X4 U7912 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][27] ), .B(n6628),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[25][27] ), .D(
n6629), .Z(n6209) );
HS65_LH_AO22X4 U7913 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][27] ), .B(n6626),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[30][27] ), .D(
n6627), .Z(n6210) );
HS65_LH_AOI22X1 U7914 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][15] ), .B(n6162),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[11][15] ), .D(
n2888), .Z(n6368) );
HS65_LH_AOI22X1 U7915 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][15] ), .B(n6371),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[29][15] ), .D(
n7272), .Z(n6374) );
HS65_LH_AOI22X1 U7916 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][15] ), .B(n6370),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[28][15] ), .D(
n6600), .Z(n6375) );
HS65_LH_AO22X4 U7917 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][15] ), .B(n6628),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[25][15] ), .D(
n7276), .Z(n6372) );
HS65_LH_AO22X4 U7918 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][15] ), .B(n6317),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[13][15] ), .D(
n6383), .Z(n6388) );
HS65_LH_AO22X4 U7919 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][15] ), .B(n6636),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[23][15] ), .D(
n7284), .Z(n6380) );
HS65_LH_AOI22X1 U7920 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][11] ), .B(n6385),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[0][11] ), .D(
n7296), .Z(n6257) );
HS65_LH_AO22X4 U7921 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][11] ), .B(n2884),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][11] ), .D(
n6382), .Z(n6260) );
HS65_LH_AO22X4 U7922 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][11] ), .B(n6634),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[20][11] ), .D(
n6635), .Z(n6256) );
HS65_LH_AOI22X1 U7923 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][11] ), .B(n6377),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[22][11] ), .D(
n6172), .Z(n6253) );
HS65_LH_AO22X4 U7924 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][11] ), .B(n9375),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[6][11] ), .D(
n6619), .Z(n6245) );
HS65_LH_AO22X4 U7925 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][11] ), .B(n6628),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[25][11] ), .D(
n6629), .Z(n6249) );
HS65_LH_AO22X4 U7926 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][11] ), .B(n6626),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[30][11] ), .D(
n6627), .Z(n6250) );
HS65_LH_AOI22X1 U7927 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][19] ), .B(n6162),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[11][19] ), .D(
n2888), .Z(n6517) );
HS65_LH_AOI22X1 U7928 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][19] ), .B(n6371),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[29][19] ), .D(
n7272), .Z(n6521) );
HS65_LH_AOI22X1 U7929 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][19] ), .B(n6370),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[28][19] ), .D(
n6600), .Z(n6522) );
HS65_LH_AO22X4 U7930 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][19] ), .B(n6628),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[25][19] ), .D(
n7276), .Z(n6519) );
HS65_LH_AO22X4 U7931 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][19] ), .B(n6317),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[13][19] ), .D(
n6383), .Z(n6529) );
HS65_LH_AOI22X1 U7932 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][19] ), .B(n7286),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[21][19] ), .D(
n6171), .Z(n6524) );
HS65_LH_AO22X4 U7933 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][19] ), .B(n6636),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[23][19] ), .D(
n7284), .Z(n6525) );
HS65_LH_AOI22X1 U7934 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][3] ), .B(n6162),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[11][3] ), .D(
n2888), .Z(n6577) );
HS65_LH_AOI22X1 U7935 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][3] ), .B(n6371),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[29][3] ), .D(
n6625), .Z(n6581) );
HS65_LH_AOI22X1 U7936 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][3] ), .B(n6370),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[28][3] ), .D(
n6600), .Z(n6582) );
HS65_LH_AO22X4 U7937 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][3] ), .B(n6628),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[25][3] ), .D(
n7276), .Z(n6579) );
HS65_LH_AO22X4 U7938 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][3] ), .B(n6317),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[13][3] ), .D(
n6383), .Z(n6589) );
HS65_LH_AOI22X1 U7939 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][3] ), .B(n7286),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[21][3] ), .D(
n6171), .Z(n6584) );
HS65_LH_AO22X4 U7940 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][3] ), .B(n6634),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[20][3] ), .D(
n7282), .Z(n6586) );
HS65_LH_AOI22X1 U7941 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][10] ), .B(n6162),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[11][10] ), .D(
n2888), .Z(n6396) );
HS65_LH_AOI22X1 U7942 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][10] ), .B(n6371),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[29][10] ), .D(
n7272), .Z(n6400) );
HS65_LH_AOI22X1 U7943 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][10] ), .B(n6370),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[28][10] ), .D(
n6600), .Z(n6401) );
HS65_LH_AO22X4 U7944 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][10] ), .B(n6628),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[25][10] ), .D(
n7276), .Z(n6398) );
HS65_LH_AO22X4 U7945 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][10] ), .B(n6317),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[13][10] ), .D(
n6383), .Z(n6408) );
HS65_LH_AO22X4 U7946 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][10] ), .B(n6636),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[23][10] ), .D(
n7284), .Z(n6404) );
HS65_LH_AOI22X1 U7947 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][26] ), .B(n6162),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[11][26] ), .D(
n2888), .Z(n6497) );
HS65_LH_AOI22X1 U7948 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][26] ), .B(n6371),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[29][26] ), .D(
n7272), .Z(n6501) );
HS65_LH_AOI22X1 U7949 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][26] ), .B(n6370),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[28][26] ), .D(
n6600), .Z(n6502) );
HS65_LH_AO22X4 U7950 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][26] ), .B(n6628),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[25][26] ), .D(
n7276), .Z(n6499) );
HS65_LH_AO22X4 U7951 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][26] ), .B(n6317),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[13][26] ), .D(
n6383), .Z(n6509) );
HS65_LH_AOI22X1 U7952 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][26] ), .B(n7286),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[21][26] ), .D(
n6171), .Z(n6504) );
HS65_LH_AO22X4 U7953 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][26] ), .B(n6636),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[23][26] ), .D(
n7284), .Z(n6505) );
HS65_LH_AOI22X1 U7954 ( .A(n6745), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][26] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][26] ), .D(n6746),
.Z(n7324) );
HS65_LH_AO22X4 U7955 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][26] ), .B(n7320),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[12][26] ), .D(
n7319), .Z(n7321) );
HS65_LH_AOI22X1 U7956 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][26] ), .B(n6951),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[10][26] ), .D(
n6670), .Z(n7316) );
HS65_LH_AOI22X1 U7957 ( .A(n6739), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][26] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][26] ), .D(n6740),
.Z(n7315) );
HS65_LH_AO22X4 U7958 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][26] ), .B(n7578),
.C(n7310), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][26] ), .Z(n7314)
);
HS65_LH_AO22X4 U7959 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][26] ), .B(n9373),
.C(n7311), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][26] ), .Z(n7313)
);
HS65_LH_AO22X4 U7960 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][26] ), .B(n7523),
.C(n7592), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][26] ), .Z(n7327)
);
HS65_LH_AOI22X1 U7961 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][26] ), .B(n7524),
.C(n7593), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][26] ), .Z(n7326)
);
HS65_LH_AO22X4 U7962 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][26] ), .B(n7332),
.C(n7331), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][26] ), .Z(n7337)
);
HS65_LH_AO22X4 U7963 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][26] ), .B(n7330),
.C(n7329), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][26] ), .Z(n7338)
);
HS65_LH_AOI22X1 U7964 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][23] ), .B(n6385),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[0][23] ), .D(
n7296), .Z(n6237) );
HS65_LH_AO22X4 U7965 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][23] ), .B(n2884),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][23] ), .D(
n6382), .Z(n6240) );
HS65_LH_AO22X4 U7966 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][23] ), .B(n6634),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[20][23] ), .D(
n6635), .Z(n6236) );
HS65_LH_AOI22X1 U7967 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][23] ), .B(n6377),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[22][23] ), .D(
n6172), .Z(n6233) );
HS65_LH_AO22X4 U7968 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][23] ), .B(n9374),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[6][23] ), .D(
n6619), .Z(n6225) );
HS65_LH_AO22X4 U7969 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][23] ), .B(n6628),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[25][23] ), .D(
n6629), .Z(n6229) );
HS65_LH_AO22X4 U7970 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][23] ), .B(n6626),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[30][23] ), .D(
n6627), .Z(n6230) );
HS65_LH_AOI22X1 U7971 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][12] ), .B(n6162),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[11][12] ), .D(
n2888), .Z(n6537) );
HS65_LH_AOI22X1 U7972 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][12] ), .B(n6371),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[29][12] ), .D(
n6625), .Z(n6541) );
HS65_LH_AOI22X1 U7973 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][12] ), .B(n6370),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[28][12] ), .D(
n6600), .Z(n6542) );
HS65_LH_AO22X4 U7974 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][12] ), .B(n6628),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[25][12] ), .D(
n7276), .Z(n6539) );
HS65_LH_AO22X4 U7975 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][12] ), .B(n6317),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[13][12] ), .D(
n6383), .Z(n6549) );
HS65_LH_AOI22X1 U7976 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][12] ), .B(n7286),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[21][12] ), .D(
n6171), .Z(n6544) );
HS65_LH_AO22X4 U7977 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][12] ), .B(n6636),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[23][12] ), .D(
n7284), .Z(n6545) );
HS65_LH_AOI22X1 U7978 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][7] ), .B(n6162),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[11][7] ), .D(
n2888), .Z(n6437) );
HS65_LH_AOI22X1 U7979 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][7] ), .B(n6371),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[29][7] ), .D(
n7272), .Z(n6441) );
HS65_LH_AOI22X1 U7980 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][7] ), .B(n6370),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[28][7] ), .D(
n6600), .Z(n6442) );
HS65_LH_AO22X4 U7981 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][7] ), .B(n6628),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[25][7] ), .D(
n7276), .Z(n6439) );
HS65_LH_AO22X4 U7982 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][7] ), .B(n6317),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[13][7] ), .D(
n6383), .Z(n6449) );
HS65_LH_AOI22X1 U7983 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][7] ), .B(n7286),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[21][7] ), .D(
n6171), .Z(n6444) );
HS65_LH_AO22X4 U7984 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][7] ), .B(n6636),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[23][7] ), .D(
n7284), .Z(n6445) );
HS65_LH_AOI22X1 U7985 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][29] ), .B(n7273),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[29][29] ), .D(
n7272), .Z(n7280) );
HS65_LH_AOI22X1 U7986 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][29] ), .B(n6370),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[28][29] ), .D(
n6600), .Z(n7281) );
HS65_LH_AO22X4 U7987 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][29] ), .B(n6636),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[23][29] ), .D(
n7284), .Z(n7289) );
HS65_LH_AOI22X1 U7988 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][29] ), .B(n2887),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[22][29] ), .D(
n6172), .Z(n7287) );
HS65_LH_AO22X4 U7989 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][29] ), .B(n7293),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[13][29] ), .D(
n7292), .Z(n7300) );
HS65_LH_AOI22X1 U7990 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][29] ), .B(n7297),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[0][29] ), .D(
n7296), .Z(n7298) );
HS65_LH_AOI22X1 U7991 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][5] ), .B(n6371),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[29][5] ), .D(
n7272), .Z(n6935) );
HS65_LH_AOI22X1 U7992 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][5] ), .B(n6370),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[28][5] ), .D(
n6600), .Z(n6936) );
HS65_LH_AO22X4 U7993 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][5] ), .B(n6636),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[23][5] ), .D(
n7284), .Z(n6939) );
HS65_LH_AOI22X1 U7994 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][5] ), .B(n2887),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[22][5] ), .D(
n6172), .Z(n6937) );
HS65_LH_AO22X4 U7995 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][5] ), .B(n6426),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][5] ), .D(n6382), .Z(n6946) );
HS65_LH_AO22X4 U7996 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][5] ), .B(n7293),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[13][5] ), .D(
n6383), .Z(n6945) );
HS65_LH_AO22X4 U7997 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][25] ), .B(n6377),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[22][25] ), .D(
n7171), .Z(n2883) );
HS65_LH_AO22X4 U7998 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][25] ), .B(n6634),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[20][25] ), .D(
n6635), .Z(n7152) );
HS65_LH_AO22X4 U7999 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][25] ), .B(n7170),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[23][25] ), .D(
n6637), .Z(n7151) );
HS65_LH_AO22X4 U8000 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][25] ), .B(n6376),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[21][25] ), .D(
n7285), .Z(n2882) );
HS65_LH_AO22X4 U8001 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][25] ), .B(n6626),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[30][25] ), .D(
n6627), .Z(n7148) );
HS65_LH_AOI22X1 U8002 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][25] ), .B(n6385),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[0][25] ), .D(
n7296), .Z(n7153) );
HS65_LH_AO22X4 U8003 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][25] ), .B(n9374),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[6][25] ), .D(
n6619), .Z(n7143) );
HS65_LH_AOI22X1 U8004 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][9] ), .B(n6617),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[14][9] ), .D(
n6362), .Z(n7126) );
HS65_LH_AO22X4 U8005 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][9] ), .B(n9375),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[6][9] ), .D(n6619), .Z(n7123) );
HS65_LH_AO22X4 U8006 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][9] ), .B(n6626),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[30][9] ), .D(
n6627), .Z(n7128) );
HS65_LH_AO22X4 U8007 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][9] ), .B(n6634),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[20][9] ), .D(
n6635), .Z(n7134) );
HS65_LH_AOI22X1 U8008 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][9] ), .B(n7297),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[0][9] ), .D(n7296), .Z(n7135) );
HS65_LH_AOI22X1 U8009 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][28] ), .B(n6370),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[28][28] ), .D(
n6624), .Z(n6914) );
HS65_LH_AO22X4 U8010 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][28] ), .B(n6636),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[23][28] ), .D(
n7284), .Z(n6917) );
HS65_LH_AOI22X1 U8011 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][28] ), .B(n2887),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[22][28] ), .D(
n6172), .Z(n6915) );
HS65_LH_AOI22X1 U8012 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][4] ), .B(n6371),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[29][4] ), .D(
n7272), .Z(n6632) );
HS65_LH_AOI22X1 U8013 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][4] ), .B(n7165),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[28][4] ), .D(
n6600), .Z(n6633) );
HS65_LH_AO22X4 U8014 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][4] ), .B(n6636),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[23][4] ), .D(
n7284), .Z(n6640) );
HS65_LH_AOI22X1 U8015 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][4] ), .B(n6377),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[22][4] ), .D(
n6172), .Z(n6638) );
HS65_LH_AOI22X1 U8016 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][4] ), .B(n6385),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[0][4] ), .D(n7296), .Z(n6642) );
HS65_LH_AO22X4 U8017 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][4] ), .B(n7293),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[13][4] ), .D(
n7292), .Z(n6644) );
HS65_LH_AOI22X1 U8018 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][4] ), .B(n6595),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[14][4] ), .D(
n6362), .Z(n6623) );
HS65_LH_AOI22X1 U8019 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][8] ), .B(n6162),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[11][8] ), .D(
n2888), .Z(n6457) );
HS65_LH_AOI22X1 U8020 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][8] ), .B(n6371),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[29][8] ), .D(
n7272), .Z(n6461) );
HS65_LH_AO22X4 U8021 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][8] ), .B(n6628),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[25][8] ), .D(
n7276), .Z(n6459) );
HS65_LH_AO22X4 U8022 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][8] ), .B(n6317),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[13][8] ), .D(
n6383), .Z(n6469) );
HS65_LH_AOI22X1 U8023 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][8] ), .B(n7286),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[21][8] ), .D(
n6171), .Z(n6464) );
HS65_LH_AO22X4 U8024 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][8] ), .B(n6636),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[23][8] ), .D(
n7284), .Z(n6465) );
HS65_LH_AOI22X1 U8025 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][20] ), .B(n6370),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[28][20] ), .D(
n6624), .Z(n6854) );
HS65_LH_AO22X4 U8026 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][20] ), .B(n6636),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[23][20] ), .D(
n7284), .Z(n6857) );
HS65_LH_AOI22X1 U8027 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][20] ), .B(n2887),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[22][20] ), .D(
n6172), .Z(n6855) );
HS65_LH_AOI22X1 U8028 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][16] ), .B(n6385),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[0][16] ), .D(
n7296), .Z(n6177) );
HS65_LH_AO22X4 U8029 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][16] ), .B(n2884),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][16] ), .D(
n6382), .Z(n6180) );
HS65_LH_AO22X4 U8030 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][16] ), .B(n6634),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[20][16] ), .D(
n6635), .Z(n6176) );
HS65_LH_AOI22X1 U8031 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][16] ), .B(n6377),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[22][16] ), .D(
n6172), .Z(n6173) );
HS65_LH_AOI22X1 U8032 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][16] ), .B(n6376),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[21][16] ), .D(
n6171), .Z(n6174) );
HS65_LH_AO22X4 U8033 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][16] ), .B(n9375),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[6][16] ), .D(
n6619), .Z(n6163) );
HS65_LH_AOI22X1 U8034 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][16] ), .B(n6162),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[11][16] ), .D(
n6363), .Z(n6165) );
HS65_LH_AO22X4 U8035 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][16] ), .B(n6628),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[25][16] ), .D(
n6629), .Z(n6167) );
HS65_LH_AO22X4 U8036 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][16] ), .B(n6626),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[30][16] ), .D(
n6627), .Z(n6168) );
HS65_LH_AOI22X1 U8037 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][17] ), .B(n6371),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[29][17] ), .D(
n7272), .Z(n6893) );
HS65_LH_AO22X4 U8038 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][17] ), .B(n6636),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[23][17] ), .D(
n7284), .Z(n6897) );
HS65_LH_AOI22X1 U8039 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][17] ), .B(n2887),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[22][17] ), .D(
n6172), .Z(n6895) );
HS65_LH_AO22X4 U8040 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][17] ), .B(n6426),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][17] ), .D(
n6382), .Z(n6902) );
HS65_LH_AO22X4 U8041 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][17] ), .B(n7293),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[13][17] ), .D(
n6383), .Z(n6901) );
HS65_LH_AO22X4 U8042 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][17] ), .B(n6747),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[4][17] ), .D(
n7318), .Z(n6812) );
HS65_LH_AO22X4 U8043 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][17] ), .B(n7320),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[12][17] ), .D(
n7319), .Z(n6811) );
HS65_LH_AOI22X1 U8044 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][17] ), .B(n6689),
.C(n6966), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][17] ), .Z(n6820)
);
HS65_LH_AOI22X1 U8045 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][17] ), .B(n6690),
.C(n6967), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][17] ), .Z(n6819)
);
HS65_LH_AO22X4 U8046 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][17] ), .B(n7330),
.C(n7329), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][17] ), .Z(n6822)
);
HS65_LH_AO22X4 U8047 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][17] ), .B(n7332),
.C(n7331), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][17] ), .Z(n6821)
);
HS65_LH_AO22X4 U8048 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][17] ), .B(n7523),
.C(n7592), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][17] ), .Z(n6817)
);
HS65_LH_AOI22X1 U8049 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][17] ), .B(n7524),
.C(n7593), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][17] ), .Z(n6816)
);
HS65_LH_AO22X4 U8050 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][17] ), .B(n9373),
.C(n7311), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][17] ), .Z(n6807)
);
HS65_LH_AO22X4 U8051 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][17] ), .B(n7429),
.C(n6952), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][17] ), .Z(n6808)
);
HS65_LH_AOI22X1 U8052 ( .A(n7428), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][17] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][17] ), .D(n6740),
.Z(n6809) );
HS65_LH_AOI22X1 U8053 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][2] ), .B(n6162),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[11][2] ), .D(
n2888), .Z(n6557) );
HS65_LH_AOI22X1 U8054 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][2] ), .B(n6371),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[29][2] ), .D(
n7272), .Z(n6561) );
HS65_LH_AO22X4 U8055 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][2] ), .B(n6317),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[13][2] ), .D(
n6383), .Z(n6569) );
HS65_LH_AO22X4 U8056 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][2] ), .B(n6636),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[23][2] ), .D(
n6637), .Z(n6565) );
HS65_LH_AOI22X1 U8057 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][18] ), .B(n6371),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[29][18] ), .D(
n7272), .Z(n6656) );
HS65_LH_AOI22X1 U8058 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][18] ), .B(n7165),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[28][18] ), .D(
n6624), .Z(n6657) );
HS65_LH_AO22X4 U8059 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][18] ), .B(n6636),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[23][18] ), .D(
n7284), .Z(n6660) );
HS65_LH_AOI22X1 U8060 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][18] ), .B(n6595),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[14][18] ), .D(
n6362), .Z(n6653) );
HS65_LH_AO22X4 U8061 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][18] ), .B(n6426),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][18] ), .D(
n6382), .Z(n6665) );
HS65_LH_AO22X4 U8062 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][18] ), .B(n7293),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[13][18] ), .D(
n6383), .Z(n6664) );
HS65_LH_AOI22X1 U8063 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][1] ), .B(n6162),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[11][1] ), .D(
n2888), .Z(n6598) );
HS65_LH_AOI22X1 U8064 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][1] ), .B(n6371),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[29][1] ), .D(
n6625), .Z(n6603) );
HS65_LH_AO22X4 U8065 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][1] ), .B(n6626),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[30][1] ), .D(
n6627), .Z(n6602) );
HS65_LH_AO22X4 U8066 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][1] ), .B(n6317),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[13][1] ), .D(
n6383), .Z(n6611) );
HS65_LH_AO22X4 U8067 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][1] ), .B(n6636),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[23][1] ), .D(
n6637), .Z(n6607) );
HS65_LH_AO22X4 U8068 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][1] ), .B(n6634),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[20][1] ), .D(
n6635), .Z(n6608) );
HS65_LH_AOI22X1 U8069 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][1] ), .B(n7286),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[21][1] ), .D(
n6171), .Z(n6606) );
HS65_LH_AOI22X1 U8070 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][1] ), .B(n7415),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[10][1] ), .D(
n6670), .Z(n6830) );
HS65_LH_AOI22X1 U8071 ( .A(n7428), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][1] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][1] ), .D(n6740),
.Z(n6829) );
HS65_LH_AO22X4 U8072 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][1] ), .B(n7429),
.C(n6952), .D(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][1] ), .Z(n6828) );
HS65_LH_AO22X4 U8073 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][1] ), .B(n9373),
.C(n7311), .D(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][1] ), .Z(n6827) );
HS65_LH_AOI22X1 U8074 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][1] ), .B(n6689),
.C(n6966), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][1] ), .Z(n6840)
);
HS65_LH_AOI22X1 U8075 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][1] ), .B(n6690),
.C(n6967), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][1] ), .Z(n6839)
);
HS65_LH_AO22X4 U8076 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][1] ), .B(n7330),
.C(n7329), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][1] ), .Z(n6842)
);
HS65_LH_AO22X4 U8077 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][1] ), .B(n7332),
.C(n7331), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][1] ), .Z(n6841)
);
HS65_LH_AOI22X1 U8078 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][1] ), .B(n7524),
.C(n6683), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][1] ), .Z(n6836)
);
HS65_LH_AO22X4 U8079 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][1] ), .B(n7320),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[12][1] ), .D(
n7319), .Z(n6831) );
HS65_LH_AOI22X1 U8080 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][0] ), .B(n6162),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[11][0] ), .D(
n2888), .Z(n6416) );
HS65_LH_AOI22X1 U8081 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][0] ), .B(n6371),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[29][0] ), .D(
n7272), .Z(n6420) );
HS65_LH_AO22X4 U8082 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][0] ), .B(n6628),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[25][0] ), .D(
n7276), .Z(n6418) );
HS65_LH_AO22X4 U8083 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][0] ), .B(n6317),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[13][0] ), .D(
n6383), .Z(n6429) );
HS65_LH_AOI22X1 U8084 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][0] ), .B(n7286),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[21][0] ), .D(
n6171), .Z(n6423) );
HS65_LH_AO22X4 U8085 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][0] ), .B(n6636),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[23][0] ), .D(
n7284), .Z(n6424) );
HS65_LH_NOR2X2 U8086 ( .A(n7738), .B(n7775), .Z(n7763) );
HS65_LH_CBI4I1X3 U8087 ( .A(n8098), .B(n8122), .C(n8097), .D(n8635), .Z(
n8099) );
HS65_LH_AO22X4 U8088 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][31] ), .B(n6636),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[23][31] ), .D(
n7284), .Z(n6877) );
HS65_LH_AOI22X1 U8089 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][31] ), .B(n2887),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[22][31] ), .D(
n6172), .Z(n6875) );
HS65_LH_AO22X4 U8090 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][31] ), .B(n6426),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][31] ), .D(
n6382), .Z(n6882) );
HS65_LH_AO22X4 U8091 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][31] ), .B(n7293),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[13][31] ), .D(
n6383), .Z(n6881) );
HS65_LH_NOR2X2 U8093 ( .A(n2842), .B(n5376), .Z(n5404) );
HS65_LH_NAND2X2 U8094 ( .A(n5105), .B(n5104), .Z(n5052) );
HS65_LH_OAI21X2 U8095 ( .A(n5313), .B(n5299), .C(n5055), .Z(n5058) );
HS65_LH_NAND2X2 U8096 ( .A(n5054), .B(n5053), .Z(n5055) );
HS65_LH_NAND2X2 U8097 ( .A(n4676), .B(n5061), .Z(n5065) );
HS65_LH_NOR2X2 U8098 ( .A(n5062), .B(n3272), .Z(n5064) );
HS65_LH_NOR2X2 U8099 ( .A(n5300), .B(n5047), .Z(n5056) );
HS65_LH_NOR2X2 U8100 ( .A(n5105), .B(n5104), .Z(n5047) );
HS65_LH_NOR2X2 U8101 ( .A(n5083), .B(n5064), .Z(n5067) );
HS65_LH_NOR2X2 U8102 ( .A(n5004), .B(n5231), .Z(n5357) );
HS65_LH_NOR2X2 U8103 ( .A(\lte_x_59/B[3] ), .B(n5089), .Z(n5383) );
HS65_LH_NOR2X2 U8104 ( .A(n5136), .B(n4660), .Z(n5091) );
HS65_LH_NOR2X2 U8105 ( .A(n5652), .B(n5654), .Z(n5361) );
HS65_LH_NOR2X2 U8106 ( .A(n2849), .B(n3372), .Z(n5430) );
HS65_LH_NAND2X2 U8107 ( .A(\lte_x_59/B[3] ), .B(n5089), .Z(n5090) );
HS65_LH_NOR2X2 U8108 ( .A(\u_DataPath/cw_to_ex_i [1]), .B(n7834), .Z(n5570)
);
HS65_LH_CNIVX3 U8109 ( .A(n5564), .Z(n5565) );
HS65_LH_CNIVX3 U8110 ( .A(n5325), .Z(n5326) );
HS65_LH_NAND2X2 U8111 ( .A(n5041), .B(n5040), .Z(n5328) );
HS65_LH_AOI21X2 U8112 ( .A(n5549), .B(n5547), .C(n5465), .Z(n5331) );
HS65_LH_NOR2X2 U8113 ( .A(n4575), .B(n5383), .Z(n5385) );
HS65_LH_OAI12X3 U8114 ( .A(n4817), .B(n5382), .C(n4819), .Z(n5386) );
HS65_LH_NOR2X2 U8115 ( .A(n5123), .B(\sub_x_53/A[0] ), .Z(n5382) );
HS65_LH_NOR2X2 U8116 ( .A(n5380), .B(n4637), .Z(n5390) );
HS65_LH_NOR2X2 U8117 ( .A(n2865), .B(\lte_x_59/B[6] ), .Z(n5380) );
HS65_LH_NOR2X2 U8118 ( .A(n5388), .B(n4100), .Z(n5381) );
HS65_LH_NAND2X2 U8119 ( .A(\lte_x_59/B[8] ), .B(n3360), .Z(n5397) );
HS65_LH_NAND2X2 U8120 ( .A(\lte_x_59/B[9] ), .B(n2871), .Z(n5395) );
HS65_LH_OAI21X2 U8121 ( .A(n5405), .B(n5404), .C(n4050), .Z(n5409) );
HS65_LH_OAI21X2 U8122 ( .A(n4915), .B(n5406), .C(n3893), .Z(n5407) );
HS65_LH_OAI21X2 U8123 ( .A(n5400), .B(n5399), .C(n4013), .Z(n5401) );
HS65_LH_NOR2X2 U8124 ( .A(n5404), .B(n5377), .Z(n5378) );
HS65_LH_NOR2X2 U8125 ( .A(n3521), .B(n3365), .Z(n5377) );
HS65_LH_OAI21X2 U8126 ( .A(n5272), .B(n5430), .C(n5270), .Z(n5431) );
HS65_LH_OAI21X2 U8127 ( .A(n5506), .B(n3515), .C(n5531), .Z(n5433) );
HS65_LH_OAI21X2 U8128 ( .A(n4418), .B(n4407), .C(n5434), .Z(n5438) );
HS65_LH_NAND2X2 U8129 ( .A(\sub_x_53/A[29] ), .B(n5447), .Z(n5448) );
HS65_LH_NAND2X2 U8130 ( .A(\sub_x_53/A[27] ), .B(n3385), .Z(n5443) );
HS65_LH_NOR2X2 U8131 ( .A(n5419), .B(n4407), .Z(n5420) );
HS65_LH_NOR2X2 U8132 ( .A(\sub_x_53/A[20] ), .B(n3376), .Z(n5419) );
HS65_LH_NAND2X2 U8134 ( .A(n5514), .B(n4672), .Z(n5303) );
HS65_LH_NAND2X2 U8135 ( .A(n5270), .B(n4244), .Z(n5533) );
HS65_LH_NAND2X2 U8137 ( .A(n5022), .B(n5021), .Z(n5003) );
HS65_LH_NAND2X2 U8138 ( .A(n4984), .B(n5001), .Z(n5002) );
HS65_LH_OAI21X2 U8139 ( .A(n5357), .B(n5006), .C(n5534), .Z(n5007) );
HS65_LH_NAND2X2 U8140 ( .A(n4986), .B(n5005), .Z(n5006) );
HS65_LH_OAI21X2 U8141 ( .A(n5344), .B(n5347), .C(n5564), .Z(n5013) );
HS65_LH_NOR2X2 U8142 ( .A(n5342), .B(n5503), .Z(n5015) );
HS65_LH_OAI21X3 U8143 ( .A(n5192), .B(n5012), .C(n5289), .Z(n5580) );
HS65_LH_AOI21X2 U8144 ( .A(n5098), .B(n5552), .C(n5043), .Z(n5044) );
HS65_LH_OAI21X2 U8145 ( .A(n5327), .B(n5095), .C(n5544), .Z(n5043) );
HS65_LH_NAND2X2 U8146 ( .A(n5552), .B(n5034), .Z(n5046) );
HS65_LH_NOR2X2 U8147 ( .A(n5042), .B(n5033), .Z(n5034) );
HS65_LH_AOI21X2 U8148 ( .A(n5039), .B(n5038), .C(n5554), .Z(n5045) );
HS65_LH_NOR2X2 U8149 ( .A(n5036), .B(n5037), .Z(n5038) );
HS65_LH_OAI21X2 U8150 ( .A(n5549), .B(n5548), .C(n5547), .Z(n5039) );
HS65_LH_OAI21X2 U8151 ( .A(n5052), .B(n5300), .C(n5297), .Z(n5060) );
HS65_LH_OAI21X2 U8153 ( .A(n5516), .B(n5514), .C(n5517), .Z(n5068) );
HS65_LH_NAND2X2 U8154 ( .A(n5062), .B(n3272), .Z(n5063) );
HS65_LH_NAND2X2 U8155 ( .A(n5540), .B(n5056), .Z(n5051) );
HS65_LH_NAND2X2 U8156 ( .A(n5050), .B(n5067), .Z(n5071) );
HS65_LH_NOR2X2 U8157 ( .A(n5049), .B(n5514), .Z(n5050) );
HS65_LH_NOR2X2 U8158 ( .A(n4671), .B(n5048), .Z(n5049) );
HS65_LH_NOR2X2 U8159 ( .A(n5022), .B(n5021), .Z(n5024) );
HS65_LH_NOR2X2 U8160 ( .A(n4984), .B(n5001), .Z(n5023) );
HS65_LH_NOR2X2 U8161 ( .A(n5357), .B(n5355), .Z(n5025) );
HS65_LH_NAND3X2 U8163 ( .A(n5540), .B(n5405), .C(n4050), .Z(n5099) );
HS65_LH_OAI21X2 U8164 ( .A(n5093), .B(n5092), .C(n5552), .Z(n5094) );
HS65_LH_NOR2X2 U8165 ( .A(n5548), .B(n5091), .Z(n5093) );
HS65_LH_NAND3X2 U8166 ( .A(n5318), .B(n5547), .C(n5317), .Z(n5092) );
HS65_LH_NOR2X2 U8167 ( .A(n2860), .B(n4967), .Z(n4968) );
HS65_LH_CNIVX3 U8168 ( .A(n5142), .Z(n5147) );
HS65_LH_OAI21X2 U8170 ( .A(n5130), .B(n5129), .C(n5128), .Z(n5132) );
HS65_LHS_XNOR2X3 U8171 ( .A(\lte_x_59/B[28] ), .B(n5423), .Z(n4761) );
HS65_LH_NAND2X2 U8172 ( .A(\lte_x_59/B[7] ), .B(n4351), .Z(n3524) );
HS65_LH_NOR2X2 U8173 ( .A(n4682), .B(n4583), .Z(n3525) );
HS65_LH_AND2X4 U8174 ( .A(n9376), .B(n8499), .Z(n3322) );
HS65_LH_AOI21X2 U8176 ( .A(n3446), .B(n3445), .C(n5646), .Z(n3447) );
HS65_LH_CNIVX3 U8177 ( .A(n3834), .Z(n3446) );
HS65_LH_NOR2X2 U8178 ( .A(n5373), .B(n4682), .Z(n5311) );
HS65_LH_NAND2X2 U8180 ( .A(n2843), .B(n4683), .Z(n5297) );
HS65_LH_NAND2X2 U8181 ( .A(\lte_x_59/B[7] ), .B(n5312), .Z(n4663) );
HS65_LH_NAND2X2 U8182 ( .A(n2865), .B(\lte_x_59/B[6] ), .Z(n4664) );
HS65_LH_CBI4I6X2 U8183 ( .A(n5387), .B(n5388), .C(n4143), .D(n4666), .Z(
n4667) );
HS65_LH_AND3X4 U8185 ( .A(n5322), .B(n4658), .C(n5317), .Z(n4659) );
HS65_LH_CNIVX3 U8186 ( .A(n5388), .Z(n4658) );
HS65_LH_CNIVX3 U8187 ( .A(n5583), .Z(n5587) );
HS65_LH_CNIVX3 U8188 ( .A(n5544), .Z(n5558) );
HS65_LH_CNIVX3 U8189 ( .A(n5540), .Z(n5543) );
HS65_LH_CNIVX3 U8190 ( .A(n5506), .Z(n5512) );
HS65_LH_CNIVX3 U8191 ( .A(n5541), .Z(n5525) );
HS65_LH_AOI21X2 U8192 ( .A(n5520), .B(n5519), .C(n5518), .Z(n5523) );
HS65_LH_CNIVX3 U8193 ( .A(n5516), .Z(n5519) );
HS65_LH_CNIVX3 U8194 ( .A(n5517), .Z(n5518) );
HS65_LH_CBI4I1X3 U8195 ( .A(n5531), .B(n5530), .C(n3515), .D(n5529), .Z(
n5532) );
HS65_LH_NAND3X2 U8196 ( .A(n5105), .B(n5104), .C(n5103), .Z(n5109) );
HS65_LH_CBI4I1X3 U8197 ( .A(n5107), .B(n5468), .C(n5396), .D(n5106), .Z(
n5108) );
HS65_LH_CNIVX3 U8199 ( .A(n5302), .Z(n5296) );
HS65_LH_CNIVX3 U8200 ( .A(n5310), .Z(n5316) );
HS65_LH_NAND2X2 U8201 ( .A(n5327), .B(n3354), .Z(n5315) );
HS65_LH_CNIVX3 U8202 ( .A(n5473), .Z(n5306) );
HS65_LH_NAND2X2 U8204 ( .A(n5390), .B(n5381), .Z(n5394) );
HS65_LH_AOI21X2 U8205 ( .A(n5386), .B(n5385), .C(n5384), .Z(n5393) );
HS65_LH_AOI21X2 U8206 ( .A(n5391), .B(n5390), .C(n5389), .Z(n5392) );
HS65_LH_AOI21X2 U8207 ( .A(n5403), .B(n5402), .C(n5401), .Z(n5411) );
HS65_LH_AOI21X2 U8208 ( .A(n5409), .B(n5408), .C(n5407), .Z(n5410) );
HS65_LH_OAI21X2 U8209 ( .A(n5397), .B(n5396), .C(n5395), .Z(n5403) );
HS65_LH_NOR2X2 U8210 ( .A(n5379), .B(n5412), .Z(n5415) );
HS65_LH_NAND2X2 U8211 ( .A(n5375), .B(n5402), .Z(n5379) );
HS65_LH_NOR2X2 U8212 ( .A(n5374), .B(n5396), .Z(n5375) );
HS65_LH_NOR2X2 U8213 ( .A(\lte_x_59/B[8] ), .B(n3360), .Z(n5374) );
HS65_LH_AOI21X2 U8214 ( .A(n5446), .B(n5445), .C(n5444), .Z(n5455) );
HS65_LH_AOI21X2 U8215 ( .A(n5453), .B(n5452), .C(n5451), .Z(n5454) );
HS65_LH_OAI21X2 U8216 ( .A(n5442), .B(n3572), .C(n5502), .Z(n5445) );
HS65_LH_NAND2X2 U8217 ( .A(n5416), .B(n5432), .Z(n5421) );
HS65_LH_NOR2X2 U8218 ( .A(n5426), .B(n3572), .Z(n5427) );
HS65_LH_AOI21X2 U8220 ( .A(n5347), .B(n5346), .C(n5505), .Z(n5348) );
HS65_LH_CNIVX3 U8221 ( .A(n5471), .Z(n5358) );
HS65_LH_AOI21X2 U8222 ( .A(n5275), .B(n5511), .C(n5355), .Z(n5359) );
HS65_LH_NAND2X2 U8223 ( .A(n5363), .B(n5362), .Z(n5367) );
HS65_LH_CNIVX3 U8224 ( .A(n5354), .Z(n5370) );
HS65_LH_NOR3X1 U8225 ( .A(\sub_x_53/A[30] ), .B(n2873), .C(n5342), .Z(n4964)
);
HS65_LH_AOI21X2 U8226 ( .A(n4983), .B(n5582), .C(n5013), .Z(n4993) );
HS65_LH_OAI21X2 U8227 ( .A(\sub_x_53/A[25] ), .B(n5345), .C(n4982), .Z(n4983) );
HS65_LH_NAND3X2 U8228 ( .A(n4981), .B(n5502), .C(n5180), .Z(n4982) );
HS65_LH_NAND3X2 U8229 ( .A(n5450), .B(n5449), .C(n5575), .Z(n4979) );
HS65_LH_AOI21X2 U8230 ( .A(n5008), .B(n5025), .C(n5007), .Z(n5011) );
HS65_LH_OAI21X2 U8231 ( .A(n5003), .B(n5023), .C(n5002), .Z(n5008) );
HS65_LH_NAND2X2 U8232 ( .A(n5582), .B(n4999), .Z(n5000) );
HS65_LH_NOR2X2 U8233 ( .A(n5500), .B(n4998), .Z(n4999) );
HS65_LH_NOR2X2 U8234 ( .A(n3101), .B(n4997), .Z(n4998) );
HS65_LH_OAI21X2 U8235 ( .A(n5342), .B(n5572), .C(n4229), .Z(n5014) );
HS65_LH_NOR2X2 U8236 ( .A(n5051), .B(n5071), .Z(n5073) );
HS65_LH_NOR2X2 U8237 ( .A(n5027), .B(n5081), .Z(n5028) );
HS65_LH_NAND2X2 U8238 ( .A(n5026), .B(n5025), .Z(n5027) );
HS65_LH_NOR2X2 U8239 ( .A(n5024), .B(n5023), .Z(n5026) );
HS65_LH_AOI21X2 U8240 ( .A(n5087), .B(n5086), .C(n5085), .Z(n5112) );
HS65_LH_NOR2X2 U8241 ( .A(n5084), .B(n5516), .Z(n5086) );
HS65_LH_CNIVX3 U8242 ( .A(n5522), .Z(n5087) );
HS65_LH_OAI21X2 U8243 ( .A(n5522), .B(n5517), .C(n5521), .Z(n5085) );
HS65_LL_NOR3X1 U8244 ( .A(n5550), .B(n5384), .C(n5094), .Z(n5102) );
HS65_LL_NAND3X2 U8245 ( .A(n5544), .B(n5545), .C(n5556), .Z(n5101) );
HS65_LHS_XOR2X3 U8246 ( .A(\lte_x_59/B[22] ), .B(n5654), .Z(n4772) );
HS65_LH_NOR2X2 U8247 ( .A(n5646), .B(n4526), .Z(n3784) );
HS65_LH_NAND2X2 U8248 ( .A(n5618), .B(n5666), .Z(n3771) );
HS65_LH_CNIVX3 U8249 ( .A(n5182), .Z(n3778) );
HS65_LH_AOI21X2 U8250 ( .A(n9352), .B(n4997), .C(n5649), .Z(n3601) );
HS65_LH_CNIVX3 U8251 ( .A(n4120), .Z(n3599) );
HS65_LHS_XNOR2X3 U8252 ( .A(\sub_x_53/A[27] ), .B(n4976), .Z(n4739) );
HS65_LHS_XNOR2X3 U8253 ( .A(n5062), .B(\lte_x_59/B[15] ), .Z(n4748) );
HS65_LHS_XOR2X3 U8254 ( .A(n5398), .B(n2858), .Z(n4757) );
HS65_LH_CBI4I1X3 U8255 ( .A(n3582), .B(n5231), .C(n5647), .D(n2849), .Z(
n5236) );
HS65_LH_AOI21X2 U8256 ( .A(n9352), .B(n5231), .C(n5649), .Z(n5237) );
HS65_LL_NAND2AX4 U8257 ( .A(n3190), .B(n8534), .Z(n3192) );
HS65_LHS_XNOR2X3 U8258 ( .A(n5104), .B(n5105), .Z(n4754) );
HS65_LH_AOI21X2 U8259 ( .A(n9352), .B(n4967), .C(n5649), .Z(n3721) );
HS65_LHS_XOR2X3 U8260 ( .A(\sub_x_53/A[23] ), .B(n4967), .Z(n4755) );
HS65_LH_NAND2X2 U8261 ( .A(n4836), .B(n5617), .Z(n4517) );
HS65_LL_AND2X4 U8262 ( .A(\lte_x_59/B[18] ), .B(n2864), .Z(n3908) );
HS65_LH_NAND2X2 U8263 ( .A(n4887), .B(n4120), .Z(n4068) );
HS65_LH_CBI4I6X2 U8264 ( .A(n9346), .B(n5376), .C(n3529), .D(n4675), .Z(
n4067) );
HS65_LH_AOI21X2 U8265 ( .A(n3529), .B(n3860), .C(n4682), .Z(n3861) );
HS65_LH_NAND2X2 U8266 ( .A(n5648), .B(n5373), .Z(n3860) );
HS65_LH_AOI21X2 U8267 ( .A(n5648), .B(n4699), .C(n5647), .Z(n4439) );
HS65_LH_AOI21X2 U8268 ( .A(n9349), .B(n5021), .C(n4850), .Z(n4852) );
HS65_LHS_XNOR2X3 U8269 ( .A(n5001), .B(n4984), .Z(n4742) );
HS65_LLS_XNOR2X3 U8270 ( .A(n8764), .B(n8943), .Z(n3037) );
HS65_LHS_XNOR2X6 U8271 ( .A(\sub_x_53/A[2] ), .B(n5088), .Z(n4769) );
HS65_LH_AND2X4 U8272 ( .A(\u_DataPath/jaddr_i [25]), .B(
\u_DataPath/jaddr_i [24]), .Z(n6131) );
HS65_LH_AOI112X2 U8273 ( .A(n5648), .B(n7623), .C(n4192), .D(n3443), .Z(
n4193) );
HS65_LHS_XNOR2X3 U8274 ( .A(n2851), .B(n7623), .Z(n4738) );
HS65_LH_OAI22X1 U8275 ( .A(n2854), .B(n4583), .C(n3756), .D(n4711), .Z(n3656) );
HS65_LH_OAI22X1 U8276 ( .A(n4981), .B(n4795), .C(n5129), .D(n3101), .Z(n3657) );
HS65_LH_CNIVX3 U8278 ( .A(n5286), .Z(n4710) );
HS65_LH_NAND3X2 U8279 ( .A(n5270), .B(n4698), .C(n4697), .Z(n4707) );
HS65_LH_NAND3X2 U8280 ( .A(\lte_x_59/B[18] ), .B(n5534), .C(n3371), .Z(n4698) );
HS65_LH_OAI21X2 U8281 ( .A(n5511), .B(n4696), .C(n5432), .Z(n4697) );
HS65_LH_NOR2X2 U8282 ( .A(n5506), .B(n3515), .Z(n4696) );
HS65_LH_NAND3X2 U8283 ( .A(\lte_x_59/B[22] ), .B(n2869), .C(n5290), .Z(n4705) );
HS65_LH_CBI4I1X3 U8284 ( .A(n5471), .B(n5292), .C(n5363), .D(n4703), .Z(
n4704) );
HS65_LH_AOI21X2 U8285 ( .A(n5286), .B(n5505), .C(n5499), .Z(n4729) );
HS65_LH_AOI21X2 U8286 ( .A(n5503), .B(n4727), .C(n5342), .Z(n4728) );
HS65_LH_CBI4I1X3 U8287 ( .A(n5500), .B(n5289), .C(n5012), .D(n4721), .Z(
n4722) );
HS65_LH_CNIVX3 U8288 ( .A(n4720), .Z(n4721) );
HS65_LH_CNIVX3 U8289 ( .A(n5408), .Z(n4681) );
HS65_LH_AOI21X2 U8290 ( .A(n5517), .B(n5476), .C(n5514), .Z(n4680) );
HS65_LH_AOI21X2 U8291 ( .A(n3892), .B(n5083), .C(n4678), .Z(n4679) );
HS65_LH_CB4I6X4 U8292 ( .A(n4687), .B(n4686), .C(n4685), .D(n4684), .Z(n4688) );
HS65_LH_CNIVX3 U8293 ( .A(n5402), .Z(n4686) );
HS65_LH_AOI21X2 U8294 ( .A(n5311), .B(n5335), .C(n5299), .Z(n4687) );
HS65_LH_NAND4ABX3 U8295 ( .A(n4720), .B(n4691), .C(n5346), .D(n5572), .Z(
n4735) );
HS65_LH_NAND2AX4 U8296 ( .A(n4666), .B(n4659), .Z(n4670) );
HS65_LH_NAND2X2 U8298 ( .A(n7834), .B(n5463), .Z(n5497) );
HS65_LH_NOR3X1 U8299 ( .A(n5571), .B(n4965), .C(n4964), .Z(n4980) );
HS65_LHS_XNOR2X3 U8300 ( .A(\sub_x_53/A[0] ), .B(n5123), .Z(n5124) );
HS65_LH_NAND3X2 U8301 ( .A(\u_DataPath/u_idexreg/N3 ), .B(n5121), .C(n5120),
.Z(n5122) );
HS65_LH_NAND2X2 U8302 ( .A(n4836), .B(n5672), .Z(n3762) );
HS65_LH_AOI21X2 U8303 ( .A(n5648), .B(n3593), .C(n5647), .Z(n3584) );
HS65_LH_AOI21X2 U8304 ( .A(n9352), .B(n4976), .C(n3659), .Z(n3660) );
HS65_LH_AOI21X2 U8305 ( .A(n3529), .B(n3658), .C(n4711), .Z(n3659) );
HS65_LH_NAND2X2 U8306 ( .A(n5648), .B(n4976), .Z(n3658) );
HS65_LH_CNIVX3 U8307 ( .A(n4739), .Z(n3662) );
HS65_LH_NOR2X2 U8308 ( .A(n5173), .B(n4185), .Z(n3668) );
HS65_LH_CNIVX3 U8309 ( .A(n3751), .Z(n3631) );
HS65_LH_CNIVX3 U8310 ( .A(n3750), .Z(n3632) );
HS65_LH_AND2X4 U8311 ( .A(n3170), .B(n3407), .Z(n2911) );
HS65_LH_AOI21X2 U8312 ( .A(n5965), .B(n5930), .C(n5929), .Z(n5931) );
HS65_LH_CBI4I1X3 U8313 ( .A(n3582), .B(n5062), .C(n5647), .D(
\lte_x_59/B[15] ), .Z(n3916) );
HS65_LH_NAND2X2 U8314 ( .A(n4507), .B(n4942), .Z(n3915) );
HS65_LH_AOI21X2 U8315 ( .A(n9352), .B(n5062), .C(n5649), .Z(n3917) );
HS65_LH_OAI21X2 U8316 ( .A(n3923), .B(n5646), .C(n3922), .Z(n3924) );
HS65_LH_NAND2X2 U8317 ( .A(n4887), .B(n4504), .Z(n3926) );
HS65_LH_AOI21X2 U8318 ( .A(n3897), .B(n4918), .C(n3896), .Z(n3898) );
HS65_LH_NAND2X2 U8320 ( .A(n4017), .B(n4014), .Z(n4019) );
HS65_LH_CBI4I1X3 U8321 ( .A(n4683), .B(n5648), .C(n5647), .D(n2858), .Z(
n4030) );
HS65_LH_AOI21X2 U8322 ( .A(n9349), .B(n4683), .C(n4028), .Z(n4029) );
HS65_LH_NAND2X2 U8323 ( .A(n5261), .B(n5257), .Z(n5263) );
HS65_LH_CNIVX3 U8324 ( .A(n4494), .Z(n4495) );
HS65_LH_CBI4I1X3 U8325 ( .A(n5648), .B(n5104), .C(n5647), .D(n3474), .Z(
n3970) );
HS65_LH_CNIVX3 U8326 ( .A(n5660), .Z(n3966) );
HS65_LH_CNIVX3 U8327 ( .A(n4950), .Z(n3962) );
HS65_LH_CNIVX3 U8328 ( .A(n4755), .Z(n3725) );
HS65_LH_AOI21X2 U8329 ( .A(n3710), .B(n5615), .C(n3709), .Z(n3711) );
HS65_LH_CNIVX3 U8330 ( .A(n4608), .Z(n3710) );
HS65_LH_CNIVX3 U8331 ( .A(n5606), .Z(n3735) );
HS65_LH_CNIVX3 U8333 ( .A(n5632), .Z(n3701) );
HS65_LHS_XNOR2X3 U8334 ( .A(n4671), .B(n5048), .Z(n4750) );
HS65_LH_CNIVX3 U8335 ( .A(n4625), .Z(n4626) );
HS65_LH_CNIVX3 U8336 ( .A(n4640), .Z(n4642) );
HS65_LH_AOI21X2 U8337 ( .A(n4581), .B(n4341), .C(n5249), .Z(n4342) );
HS65_LL_AOI21X2 U8338 ( .A(n9349), .B(n5422), .C(n5649), .Z(n4352) );
HS65_LHS_XOR2X3 U8340 ( .A(\sub_x_53/A[29] ), .B(n5422), .Z(n4765) );
HS65_LH_AOI21X2 U8341 ( .A(n5618), .B(n4394), .C(n4358), .Z(n4359) );
HS65_LH_CNIVX3 U8342 ( .A(n4356), .Z(n4357) );
HS65_LH_NAND2X2 U8343 ( .A(n5194), .B(n4335), .Z(n4337) );
HS65_LH_AOI21X2 U8344 ( .A(n5659), .B(n4892), .C(n4397), .Z(n4398) );
HS65_LH_AOI21X2 U8345 ( .A(n9349), .B(n5418), .C(n5649), .Z(n4395) );
HS65_LH_NAND2X2 U8346 ( .A(n5229), .B(n4394), .Z(n4399) );
HS65_LH_NAND2X2 U8347 ( .A(n5661), .B(n4393), .Z(n4400) );
HS65_LH_CNIVX3 U8348 ( .A(n4105), .Z(n4106) );
HS65_LH_AOI21X2 U8350 ( .A(n9349), .B(n5040), .C(n4115), .Z(n4116) );
HS65_LHS_XNOR2X3 U8352 ( .A(\lte_x_59/B[5] ), .B(n5040), .Z(n4753) );
HS65_LH_AND2X4 U8353 ( .A(n4714), .B(n8506), .Z(n3227) );
HS65_LH_CNIVX3 U8354 ( .A(n4902), .Z(n4903) );
HS65_LH_CNIVX3 U8355 ( .A(n3823), .Z(n3436) );
HS65_LH_OAI21X2 U8356 ( .A(n5004), .B(n2856), .C(n3819), .Z(n3433) );
HS65_LH_AOI21X2 U8357 ( .A(n5648), .B(n5654), .C(n5647), .Z(n5653) );
HS65_LH_NAND2X2 U8358 ( .A(n5608), .B(n2867), .Z(n5611) );
HS65_LH_AOI21X2 U8359 ( .A(n5139), .B(n5618), .C(n3879), .Z(n3880) );
HS65_LH_AOI21X2 U8360 ( .A(n9352), .B(n5373), .C(n3861), .Z(n3866) );
HS65_LH_AOI21X2 U8362 ( .A(n5234), .B(n4441), .C(n4440), .Z(n4442) );
HS65_LH_AOI21X2 U8363 ( .A(n5207), .B(n4892), .C(n3537), .Z(n3538) );
HS65_LH_CNIVX3 U8365 ( .A(n4542), .Z(n4543) );
HS65_LH_CBI4I6X2 U8366 ( .A(n9346), .B(n3415), .C(n3529), .D(n5130), .Z(
n4549) );
HS65_LH_CNIVX3 U8367 ( .A(n4630), .Z(n4158) );
HS65_LHS_XNOR2X3 U8368 ( .A(\lte_x_59/B[6] ), .B(n2865), .Z(n4764) );
HS65_LH_CNIVX3 U8369 ( .A(n3955), .Z(n3960) );
HS65_LLS_XNOR2X3 U8370 ( .A(n2947), .B(n8762), .Z(n2959) );
HS65_LH_CNIVX3 U8371 ( .A(n2957), .Z(n2958) );
HS65_LH_NOR2X6 U8372 ( .A(n9236), .B(n2982), .Z(n7639) );
HS65_LH_AOI21X2 U8374 ( .A(n9352), .B(n7623), .C(n4194), .Z(n4195) );
HS65_LH_AOI21X2 U8375 ( .A(n4182), .B(n4181), .C(n5646), .Z(n4183) );
HS65_LH_AOI21X2 U8376 ( .A(\lte_x_59/B[28] ), .B(n2864), .C(n4507), .Z(n4181) );
HS65_LH_AOI21X2 U8379 ( .A(n4211), .B(n4291), .C(n4218), .Z(n4219) );
HS65_LHS_XNOR2X3 U8380 ( .A(n8942), .B(\u_DataPath/jaddr_i [16]), .Z(n7103)
);
HS65_LH_AOI21X2 U8381 ( .A(n5229), .B(n4892), .C(n4801), .Z(n4802) );
HS65_LH_AOI21X2 U8382 ( .A(n5648), .B(n4805), .C(n4804), .Z(n4812) );
HS65_LH_OAI21X2 U8383 ( .A(n4796), .B(n4795), .C(n4794), .Z(n4797) );
HS65_LH_CNIVX3 U8384 ( .A(n4333), .Z(n3130) );
HS65_LL_NOR2AX3 U8385 ( .A(n2904), .B(n4735), .Z(n4692) );
HS65_LH_NOR2X2 U8386 ( .A(n5491), .B(\u_DataPath/cw_to_ex_i [4]), .Z(n5121)
);
HS65_LL_AOI21X2 U8388 ( .A(n5192), .B(n5195), .C(n3576), .Z(n3577) );
HS65_LH_NOR2X6 U8389 ( .A(n9078), .B(n9031), .Z(n7343) );
HS65_LH_CNIVX3 U8390 ( .A(n4913), .Z(n4914) );
HS65_LH_AOI21X2 U8392 ( .A(n4919), .B(n4918), .C(n4917), .Z(n4920) );
HS65_LL_NOR3AX2 U8393 ( .A(n3926), .B(n3925), .C(n3924), .Z(n3927) );
HS65_LH_AOI21X2 U8394 ( .A(n5234), .B(n3919), .C(n3918), .Z(n3928) );
HS65_LH_AOI21X2 U8395 ( .A(n4951), .B(n4616), .C(n3906), .Z(n3931) );
HS65_LH_CNIVX3 U8396 ( .A(n4011), .Z(n4012) );
HS65_LH_CNIVX3 U8397 ( .A(n4570), .Z(n4571) );
HS65_LH_AOI21X2 U8398 ( .A(n4508), .B(n4507), .C(n4506), .Z(n4509) );
HS65_LH_CNIVX3 U8400 ( .A(n4938), .Z(n4492) );
HS65_LH_AND2X4 U8401 ( .A(n5405), .B(n4051), .Z(n2906) );
HS65_LH_CNIVX3 U8404 ( .A(n4771), .Z(n4613) );
HS65_LH_AOI21X2 U8405 ( .A(n9352), .B(n5030), .C(n4610), .Z(n4611) );
HS65_LH_OAI22X1 U8406 ( .A(n4954), .B(n3913), .C(n4609), .D(n5646), .Z(n4621) );
HS65_LH_OAI21X2 U8407 ( .A(n4113), .B(n5201), .C(n4065), .Z(n4075) );
HS65_LH_AOI21X2 U8409 ( .A(n5618), .B(n5203), .C(n5202), .Z(n5220) );
HS65_LH_OAI21X2 U8410 ( .A(n3382), .B(n5179), .C(n5178), .Z(n5185) );
HS65_LH_NAND2X2 U8412 ( .A(n4516), .B(n4491), .Z(n4161) );
HS65_LHS_XOR2X3 U8413 ( .A(n3856), .B(n4929), .Z(n3888) );
HS65_LH_CNIVX3 U8414 ( .A(n4880), .Z(n3855) );
HS65_LH_NAND2X2 U8415 ( .A(n4836), .B(n4835), .Z(n4837) );
HS65_LH_CNIVX3 U8416 ( .A(n4575), .Z(n4539) );
HS65_LH_AOI21X2 U8417 ( .A(n4546), .B(n4545), .C(n5201), .Z(n4547) );
HS65_LH_CNIVX3 U8418 ( .A(n4541), .Z(n4546) );
HS65_LH_AOI21X2 U8419 ( .A(\lte_x_59/B[4] ), .B(n4544), .C(n4543), .Z(n4545)
);
HS65_LH_NOR2AX3 U8420 ( .A(n4557), .B(n4556), .Z(n4566) );
HS65_LH_AOI21X2 U8421 ( .A(n9352), .B(n5088), .C(n4549), .Z(n4557) );
HS65_LH_CNIVX3 U8422 ( .A(n4643), .Z(n4142) );
HS65_LH_IVX9 U8423 ( .A(n3409), .Z(n3237) );
HS65_LH_NOR2X2 U8424 ( .A(n9084), .B(n9082), .Z(n7693) );
HS65_LH_AOI21X2 U8425 ( .A(n9082), .B(n7734), .C(n7690), .Z(n7692) );
HS65_LH_NAND2X2 U8427 ( .A(n4836), .B(n5243), .Z(n4177) );
HS65_LH_AOI21X2 U8428 ( .A(n5661), .B(n5228), .C(n4186), .Z(n4201) );
HS65_LH_AOI21X2 U8430 ( .A(n5234), .B(n4199), .C(n4198), .Z(n4200) );
HS65_LH_NAND2X2 U8431 ( .A(n2851), .B(n7623), .Z(n4206) );
HS65_LH_IVX9 U8432 ( .A(n8683), .Z(n7742) );
HS65_LH_IVX9 U8433 ( .A(n8695), .Z(n7753) );
HS65_LH_IVX9 U8434 ( .A(n8694), .Z(n3123) );
HS65_LH_IVX9 U8435 ( .A(n8699), .Z(n3125) );
HS65_LH_IVX9 U8437 ( .A(n8709), .Z(n3124) );
HS65_LH_IVX9 U8438 ( .A(n8705), .Z(n7769) );
HS65_LH_IVX9 U8439 ( .A(n8708), .Z(n7756) );
HS65_LH_IVX9 U8440 ( .A(n8706), .Z(n7766) );
HS65_LH_IVX9 U8441 ( .A(n8711), .Z(n3121) );
HS65_LH_IVX9 U8442 ( .A(n8701), .Z(n3119) );
HS65_LH_IVX9 U8443 ( .A(n8707), .Z(n3118) );
HS65_LH_IVX9 U8444 ( .A(n8710), .Z(n7705) );
HS65_LH_IVX9 U8445 ( .A(n8712), .Z(n7785) );
HS65_LH_NOR3X1 U8446 ( .A(n7636), .B(n7778), .C(n7772), .Z(n7309) );
HS65_LH_CBI4I1X3 U8447 ( .A(n8116), .B(n7698), .C(n7689), .D(n7697), .Z(
n8118) );
HS65_LH_OAI22X1 U8448 ( .A(n7738), .B(n7690), .C(n9084), .D(n7688), .Z(n7689) );
HS65_LL_AND2X4 U8449 ( .A(n5682), .B(n5681), .Z(n5685) );
HS65_LL_NOR3AX2 U8450 ( .A(n7873), .B(n5680), .C(n5679), .Z(n5682) );
HS65_LLS_XNOR2X3 U8451 ( .A(n3393), .B(n3392), .Z(n3514) );
HS65_LLS_XNOR2X3 U8452 ( .A(n3638), .B(n3637), .Z(n3697) );
HS65_LH_IVX2 U8453 ( .A(n7622), .Z(n7621) );
HS65_LH_NAND3X2 U8454 ( .A(n7089), .B(n9031), .C(n9078), .Z(n8145) );
HS65_LH_NAND3X5 U8455 ( .A(n3011), .B(n9078), .C(n2946), .Z(n8147) );
HS65_LH_IVX9 U8456 ( .A(n7840), .Z(n8608) );
HS65_LH_OAI21X2 U8457 ( .A(n9084), .B(n7775), .C(n7774), .Z(n7779) );
HS65_LH_CNIVX3 U8459 ( .A(n6066), .Z(n6009) );
HS65_LH_CNIVX3 U8461 ( .A(n5947), .Z(n5948) );
HS65_LH_CNIVX3 U8463 ( .A(n8258), .Z(n3241) );
HS65_LH_CNIVX3 U8464 ( .A(n6061), .Z(n6062) );
HS65_LH_CNIVX3 U8465 ( .A(n5952), .Z(n5953) );
HS65_LH_AOI22X1 U8466 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][27] ), .B(n6754),
.C(n7594), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][27] ), .Z(n7460)
);
HS65_LH_AO22X4 U8467 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][27] ), .B(n6680),
.C(n6752), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][27] ), .Z(n7463)
);
HS65_LH_AO22X4 U8468 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][27] ), .B(n6681),
.C(n7592), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][27] ), .Z(n7462)
);
HS65_LH_AOI22X1 U8469 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][27] ), .B(n6753),
.C(n7593), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][27] ), .Z(n7461)
);
HS65_LH_AOI22X1 U8470 ( .A(n6745), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][27] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][27] ), .D(n6746),
.Z(n7459) );
HS65_LH_AO22X4 U8471 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][27] ), .B(n6747),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[4][27] ), .D(
n6675), .Z(n7457) );
HS65_LH_AO22X4 U8472 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][27] ), .B(n7578),
.C(n6952), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][27] ), .Z(n7453)
);
HS65_LH_AOI22X1 U8473 ( .A(n6739), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][27] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][27] ), .D(n2890),
.Z(n7454) );
HS65_LH_AO22X4 U8475 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][14] ), .B(n6626),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[30][14] ), .D(
n6627), .Z(n6310) );
HS65_LH_AO22X4 U8476 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][14] ), .B(n6628),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[25][14] ), .D(
n6629), .Z(n6309) );
HS65_LH_AO22X4 U8477 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][14] ), .B(n6317),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[13][14] ), .D(
n7292), .Z(n6320) );
HS65_LH_AOI22X1 U8478 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][14] ), .B(n6385),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[0][14] ), .D(
n7296), .Z(n6318) );
HS65_LH_AO22X4 U8479 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][14] ), .B(n2884),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][14] ), .D(
n6382), .Z(n6321) );
HS65_LH_AO22X4 U8480 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][14] ), .B(n6634),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[20][14] ), .D(
n6635), .Z(n6316) );
HS65_LH_AO22X4 U8481 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][14] ), .B(n9374),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[6][14] ), .D(
n6619), .Z(n6305) );
HS65_LH_AO22X4 U8482 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][14] ), .B(n6364),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][14] ), .D(
n9371), .Z(n6306) );
HS65_LH_AOI22X1 U8483 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][14] ), .B(n6162),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[11][14] ), .D(
n6363), .Z(n6307) );
HS65_LH_AO22X4 U8484 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][14] ), .B(n7587),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[12][14] ), .D(
n7586), .Z(n7371) );
HS65_LH_AO22X4 U8485 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][14] ), .B(n7517),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[4][14] ), .D(
n6675), .Z(n7372) );
HS65_LH_AOI22X1 U8486 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][14] ), .B(n6689),
.C(n6966), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][14] ), .Z(n7380)
);
HS65_LH_AOI22X1 U8487 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][14] ), .B(n6690),
.C(n6967), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][14] ), .Z(n7379)
);
HS65_LH_AOI22X1 U8488 ( .A(n6739), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][14] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][14] ), .D(n6740),
.Z(n7369) );
HS65_LH_AOI22X1 U8489 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][14] ), .B(n7525),
.C(n6684), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][14] ), .Z(n7375)
);
HS65_LH_AO22X4 U8490 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][15] ), .B(n7320),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[12][15] ), .D(
n7319), .Z(n7188) );
HS65_LH_AOI22X1 U8491 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][15] ), .B(n6951),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[10][15] ), .D(
n6670), .Z(n7187) );
HS65_LH_AOI22X1 U8492 ( .A(n7428), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][15] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][15] ), .D(n6740),
.Z(n7186) );
HS65_LH_AO22X4 U8493 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][15] ), .B(n9373),
.C(n7311), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][15] ), .Z(n7184)
);
HS65_LH_AO22X4 U8494 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][15] ), .B(n7332),
.C(n7331), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][15] ), .Z(n7198)
);
HS65_LH_AO22X4 U8495 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][15] ), .B(n7330),
.C(n7329), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][15] ), .Z(n7199)
);
HS65_LH_AOI22X1 U8496 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][15] ), .B(n7525),
.C(n6684), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][15] ), .Z(n7192)
);
HS65_LH_AO22X4 U8497 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][11] ), .B(n6680),
.C(n6752), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][11] ), .Z(n7067)
);
HS65_LH_AOI22X1 U8498 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][11] ), .B(n6753),
.C(n7593), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][11] ), .Z(n7065)
);
HS65_LH_AOI22X1 U8499 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][11] ), .B(n6951),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[10][11] ), .D(
n6670), .Z(n7059) );
HS65_LH_AOI22X1 U8500 ( .A(n6739), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][11] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][11] ), .D(n2890),
.Z(n7058) );
HS65_LH_AOI22X1 U8501 ( .A(n6745), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][11] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][11] ), .D(n6746),
.Z(n7063) );
HS65_LH_CNIVX3 U8502 ( .A(n9232), .Z(n4005) );
HS65_LH_AOI22X1 U8503 ( .A(n6745), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][19] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][19] ), .D(n6746),
.Z(n6751) );
HS65_LH_AOI22X1 U8504 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][19] ), .B(n6951),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[10][19] ), .D(
n6670), .Z(n6744) );
HS65_LH_AOI22X1 U8505 ( .A(n6739), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][19] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][19] ), .D(n2890),
.Z(n6743) );
HS65_LH_AO22X4 U8506 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][19] ), .B(n6680),
.C(n6752), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][19] ), .Z(n6758)
);
HS65_LH_CNIVX3 U8507 ( .A(n9218), .Z(n5702) );
HS65_LH_AO22X4 U8509 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][3] ), .B(n7587),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[12][3] ), .D(
n7586), .Z(n7391) );
HS65_LH_AO22X4 U8510 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][3] ), .B(n7517),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[4][3] ), .D(n6675), .Z(n7392) );
HS65_LH_AOI22X1 U8511 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][3] ), .B(n6689),
.C(n6966), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][3] ), .Z(n7400)
);
HS65_LH_AOI22X1 U8512 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][3] ), .B(n6690),
.C(n6967), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][3] ), .Z(n7399)
);
HS65_LH_AOI22X1 U8513 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][3] ), .B(n7524),
.C(n6683), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][3] ), .Z(n7396)
);
HS65_LH_AOI22X1 U8514 ( .A(n7428), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][10] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][10] ), .D(n6740),
.Z(n7206) );
HS65_LH_AO22X4 U8515 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][10] ), .B(n7578),
.C(n6952), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][10] ), .Z(n7205)
);
HS65_LH_AO22X4 U8516 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][10] ), .B(n9373),
.C(n7311), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][10] ), .Z(n7204)
);
HS65_LH_AOI22X1 U8517 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][10] ), .B(n6689),
.C(n6966), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][10] ), .Z(n7217)
);
HS65_LH_AOI22X1 U8518 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][10] ), .B(n6690),
.C(n6967), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][10] ), .Z(n7216)
);
HS65_LH_AO22X4 U8519 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][10] ), .B(n7330),
.C(n7329), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][10] ), .Z(n7219)
);
HS65_LH_AO22X4 U8520 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][10] ), .B(n7332),
.C(n7331), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][10] ), .Z(n7218)
);
HS65_LH_AOI22X1 U8521 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][10] ), .B(n7525),
.C(n6684), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][10] ), .Z(n7212)
);
HS65_LH_AO22X4 U8522 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][10] ), .B(n7320),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[12][10] ), .D(
n7319), .Z(n7208) );
HS65_LH_AOI22X1 U8523 ( .A(n7428), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][23] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][23] ), .D(n6740),
.Z(n7226) );
HS65_LH_AO22X4 U8524 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][23] ), .B(n7429),
.C(n6952), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][23] ), .Z(n7225)
);
HS65_LH_AO22X4 U8525 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][23] ), .B(n9373),
.C(n7311), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][23] ), .Z(n7224)
);
HS65_LH_AOI22X1 U8526 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][23] ), .B(n6689),
.C(n6966), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][23] ), .Z(n7237)
);
HS65_LH_AOI22X1 U8527 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][23] ), .B(n6690),
.C(n6967), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][23] ), .Z(n7236)
);
HS65_LH_AO22X4 U8528 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][23] ), .B(n7330),
.C(n7329), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][23] ), .Z(n7239)
);
HS65_LH_AO22X4 U8529 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][23] ), .B(n7332),
.C(n7331), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][23] ), .Z(n7238)
);
HS65_LH_AOI22X1 U8530 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][23] ), .B(n7525),
.C(n6684), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][23] ), .Z(n7232)
);
HS65_LH_AO22X4 U8531 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][23] ), .B(n7320),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[12][23] ), .D(
n7319), .Z(n7228) );
HS65_LH_AO22X4 U8532 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][30] ), .B(n6626),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[30][30] ), .D(
n6627), .Z(n6135) );
HS65_LH_AO22X4 U8533 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][30] ), .B(n6628),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[25][30] ), .D(
n6629), .Z(n6134) );
HS65_LH_AO22X4 U8534 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][30] ), .B(n6317),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[13][30] ), .D(
n7292), .Z(n6156) );
HS65_LH_AOI22X1 U8535 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][30] ), .B(n6385),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[0][30] ), .D(
n7296), .Z(n6154) );
HS65_LH_AO22X4 U8536 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][30] ), .B(n2884),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][30] ), .D(
n6382), .Z(n6157) );
HS65_LH_AO22X4 U8537 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][30] ), .B(n7170),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[23][30] ), .D(
n6637), .Z(n6143) );
HS65_LH_AO22X4 U8538 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][30] ), .B(n6634),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[20][30] ), .D(
n6635), .Z(n6144) );
HS65_LH_AO22X4 U8539 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][30] ), .B(n9375),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[6][30] ), .D(
n6619), .Z(n6127) );
HS65_LH_AO22X4 U8540 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][30] ), .B(n6364),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][30] ), .D(
n9371), .Z(n6128) );
HS65_LH_AOI22X1 U8541 ( .A(n6745), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][30] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][30] ), .D(n6746),
.Z(n7413) );
HS65_LH_AO22X4 U8542 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][30] ), .B(n6747),
.C(n6675), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][30] ), .Z(n7412)
);
HS65_LH_AO22X4 U8543 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][30] ), .B(n6689),
.C(n6966), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][30] ), .Z(n7408)
);
HS65_LH_AO22X4 U8544 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][30] ), .B(n6690),
.C(n6967), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][30] ), .Z(n7407)
);
HS65_LH_AOI22X1 U8545 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][30] ), .B(n6753),
.C(n7593), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][30] ), .Z(n7421)
);
HS65_LH_AO22X4 U8546 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][30] ), .B(n6680),
.C(n6752), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][30] ), .Z(n7423)
);
HS65_LH_AO22X4 U8547 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][30] ), .B(n7578),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][30] ), .D(
n6952), .Z(n7419) );
HS65_LH_AOI22X1 U8548 ( .A(n6739), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][30] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][30] ), .D(n2890),
.Z(n7416) );
HS65_LH_AND2X4 U8549 ( .A(n5450), .B(n4303), .Z(n2915) );
HS65_LH_AO22X4 U8550 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][12] ), .B(n7320),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[12][12] ), .D(
n7319), .Z(n6791) );
HS65_LH_AOI22X1 U8551 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][12] ), .B(n6951),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[10][12] ), .D(
n6670), .Z(n6790) );
HS65_LH_AOI22X1 U8552 ( .A(n7428), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][12] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][12] ), .D(n6740),
.Z(n6789) );
HS65_LH_AO22X4 U8553 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][12] ), .B(n7429),
.C(n7310), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][12] ), .Z(n6788)
);
HS65_LH_AO22X4 U8554 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][12] ), .B(n9373),
.C(n7311), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][12] ), .Z(n6787)
);
HS65_LH_AO22X4 U8555 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][12] ), .B(n7332),
.C(n7331), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][12] ), .Z(n6801)
);
HS65_LH_AO22X4 U8556 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][12] ), .B(n7330),
.C(n7329), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][12] ), .Z(n6802)
);
HS65_LH_AOI22X1 U8557 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][12] ), .B(n7525),
.C(n6684), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][12] ), .Z(n6795)
);
HS65_LH_AO22X4 U8558 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][7] ), .B(n7320),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[12][7] ), .D(
n7319), .Z(n6723) );
HS65_LH_AOI22X1 U8559 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][7] ), .B(n6689),
.C(n6966), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][7] ), .Z(n6732)
);
HS65_LH_AOI22X1 U8560 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][7] ), .B(n6690),
.C(n6967), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][7] ), .Z(n6731)
);
HS65_LH_AO22X4 U8561 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][7] ), .B(n7330),
.C(n7329), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][7] ), .Z(n6734)
);
HS65_LH_AO22X4 U8562 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][7] ), .B(n7332),
.C(n7331), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][7] ), .Z(n6733)
);
HS65_LH_AOI22X1 U8563 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][7] ), .B(n7525),
.C(n6684), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][7] ), .Z(n6727)
);
HS65_LH_AO22X4 U8564 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][7] ), .B(n9373),
.C(n7311), .D(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][7] ), .Z(n6719) );
HS65_LH_AO22X4 U8565 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][7] ), .B(n7429),
.C(n6952), .D(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][7] ), .Z(n6720) );
HS65_LH_AOI22X1 U8566 ( .A(n7428), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][7] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][7] ), .D(n6740),
.Z(n6721) );
HS65_LH_AOI22X1 U8567 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][13] ), .B(n7273),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[29][13] ), .D(
n6625), .Z(n7168) );
HS65_LH_AO22X4 U8568 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][13] ), .B(n6626),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[30][13] ), .D(
n6627), .Z(n7167) );
HS65_LH_AO22X4 U8569 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][13] ), .B(n2884),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][13] ), .D(
n6382), .Z(n7179) );
HS65_LH_AOI22X1 U8570 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][13] ), .B(n6385),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[0][13] ), .D(
n7296), .Z(n7176) );
HS65_LH_AO22X4 U8571 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][13] ), .B(n6634),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[20][13] ), .D(
n6635), .Z(n7175) );
HS65_LH_AO22X4 U8572 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][13] ), .B(n9374),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[6][13] ), .D(
n6619), .Z(n7161) );
HS65_LH_AO22X4 U8573 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][13] ), .B(n6364),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][13] ), .D(
n9372), .Z(n7162) );
HS65_LH_AO22X4 U8574 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][13] ), .B(n6680),
.C(n6752), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][13] ), .Z(n6987)
);
HS65_LH_AOI22X1 U8575 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][13] ), .B(n6753),
.C(n7593), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][13] ), .Z(n6985)
);
HS65_LH_AOI22X1 U8576 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][13] ), .B(n6951),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[10][13] ), .D(
n6670), .Z(n6979) );
HS65_LH_AOI22X1 U8577 ( .A(n6739), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][13] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][13] ), .D(n2890),
.Z(n6978) );
HS65_LH_AOI22X1 U8578 ( .A(n6745), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][13] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][13] ), .D(n6746),
.Z(n6983) );
HS65_LH_AOI22X1 U8579 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][29] ), .B(n7524),
.C(n6683), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][29] ), .Z(n7527)
);
HS65_LH_AOI22X1 U8580 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][29] ), .B(n7525),
.C(n6684), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][29] ), .Z(n7526)
);
HS65_LH_AO22X4 U8581 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][29] ), .B(n7587),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[12][29] ), .D(
n7586), .Z(n7518) );
HS65_LH_AO22X4 U8582 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][29] ), .B(n7517),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[4][29] ), .D(
n6675), .Z(n7519) );
HS65_LH_AOI22X1 U8583 ( .A(n6739), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][29] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][29] ), .D(n6740),
.Z(n7514) );
HS65_LH_AO22X4 U8584 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][21] ), .B(n6626),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[30][21] ), .D(
n6627), .Z(n6190) );
HS65_LH_AO22X4 U8585 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][21] ), .B(n6628),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[25][21] ), .D(
n6629), .Z(n6189) );
HS65_LH_AO22X4 U8586 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][21] ), .B(n6317),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[13][21] ), .D(
n7292), .Z(n6199) );
HS65_LH_AOI22X1 U8587 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][21] ), .B(n6385),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[0][21] ), .D(
n7296), .Z(n6197) );
HS65_LH_AO22X4 U8588 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][21] ), .B(n2884),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][21] ), .D(
n6382), .Z(n6200) );
HS65_LH_AOI22X1 U8589 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][21] ), .B(n6376),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[21][21] ), .D(
n6171), .Z(n6194) );
HS65_LH_AO22X4 U8590 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][21] ), .B(n6634),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[20][21] ), .D(
n6635), .Z(n6196) );
HS65_LH_AO22X4 U8591 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][21] ), .B(n9375),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[6][21] ), .D(
n6619), .Z(n6185) );
HS65_LH_AO22X4 U8592 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][21] ), .B(n6364),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][21] ), .D(
n9372), .Z(n6186) );
HS65_LH_AOI22X1 U8593 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][21] ), .B(n6162),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[11][21] ), .D(
n6363), .Z(n6187) );
HS65_LH_AOI22X1 U8594 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][21] ), .B(n6951),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[10][21] ), .D(
n2891), .Z(n7584) );
HS65_LH_AOI22X1 U8595 ( .A(n6739), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][21] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][21] ), .D(n2890),
.Z(n7583) );
HS65_LH_AO22X4 U8596 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][21] ), .B(n7578),
.C(n6952), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][21] ), .Z(n7582)
);
HS65_LH_AOI22X1 U8597 ( .A(n6745), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][21] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][21] ), .D(n6746),
.Z(n7591) );
HS65_LH_AO22X4 U8598 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][21] ), .B(n6747),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[4][21] ), .D(
n6675), .Z(n7589) );
HS65_LH_AOI22X1 U8599 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][21] ), .B(n6753),
.C(n7593), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][21] ), .Z(n7596)
);
HS65_LH_AO22X4 U8600 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][21] ), .B(n6681),
.C(n7592), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][21] ), .Z(n7597)
);
HS65_LH_AO22X4 U8601 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][21] ), .B(n6680),
.C(n6752), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][21] ), .Z(n7598)
);
HS65_LH_AOI22X1 U8602 ( .A(n7428), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][5] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][5] ), .D(n6740),
.Z(n6701) );
HS65_LH_AO22X4 U8603 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][5] ), .B(n7429),
.C(n6952), .D(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][5] ), .Z(n6700) );
HS65_LH_AO22X4 U8604 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][5] ), .B(n9373),
.C(n7311), .D(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][5] ), .Z(n6699) );
HS65_LH_AOI22X1 U8605 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][5] ), .B(n6689),
.C(n6966), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][5] ), .Z(n6712)
);
HS65_LH_AOI22X1 U8606 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][5] ), .B(n6690),
.C(n6967), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][5] ), .Z(n6711)
);
HS65_LH_AO22X4 U8607 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][5] ), .B(n7330),
.C(n7329), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][5] ), .Z(n6714)
);
HS65_LH_AO22X4 U8608 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][5] ), .B(n7332),
.C(n7331), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][5] ), .Z(n6713)
);
HS65_LH_AOI22X1 U8609 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][5] ), .B(n7525),
.C(n6684), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][5] ), .Z(n6707)
);
HS65_LH_AO22X4 U8610 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][5] ), .B(n7320),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[12][5] ), .D(
n7319), .Z(n6703) );
HS65_LH_AO22X4 U8611 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][25] ), .B(n6680),
.C(n6752), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][25] ), .Z(n7047)
);
HS65_LH_AOI22X1 U8612 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][25] ), .B(n6753),
.C(n7593), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][25] ), .Z(n7045)
);
HS65_LH_AOI22X1 U8613 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][25] ), .B(n6951),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[10][25] ), .D(
n6670), .Z(n7039) );
HS65_LH_AOI22X1 U8614 ( .A(n6739), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][25] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][25] ), .D(n2890),
.Z(n7038) );
HS65_LH_AOI22X1 U8615 ( .A(n6745), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][25] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][25] ), .D(n6746),
.Z(n7043) );
HS65_LH_AO22X4 U8616 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][9] ), .B(n6680),
.C(n6752), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][9] ), .Z(n7027)
);
HS65_LH_AOI22X1 U8617 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][9] ), .B(n6753),
.C(n7593), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][9] ), .Z(n7025)
);
HS65_LH_AOI22X1 U8618 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][9] ), .B(n6951),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[10][9] ), .D(
n6670), .Z(n7019) );
HS65_LH_AOI22X1 U8619 ( .A(n6739), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][9] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][9] ), .D(n2890),
.Z(n7018) );
HS65_LH_AOI22X1 U8620 ( .A(n6745), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][9] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][9] ), .D(n6746),
.Z(n7023) );
HS65_LH_AO22X4 U8621 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][24] ), .B(n6626),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[30][24] ), .D(
n6627), .Z(n6290) );
HS65_LH_AO22X4 U8622 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][24] ), .B(n6628),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[25][24] ), .D(
n6629), .Z(n6289) );
HS65_LH_AOI22X1 U8623 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][24] ), .B(n6385),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[0][24] ), .D(
n7296), .Z(n6297) );
HS65_LH_AO22X4 U8624 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][24] ), .B(n2884),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][24] ), .D(
n6382), .Z(n6300) );
HS65_LH_AO22X4 U8625 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][24] ), .B(n7170),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[23][24] ), .D(
n6637), .Z(n6295) );
HS65_LH_AO22X4 U8626 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][24] ), .B(n6634),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[20][24] ), .D(
n6635), .Z(n6296) );
HS65_LH_AO22X4 U8627 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][24] ), .B(n9374),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[6][24] ), .D(
n6619), .Z(n6285) );
HS65_LH_AO22X4 U8628 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][24] ), .B(n6364),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][24] ), .D(
n9371), .Z(n6286) );
HS65_LH_AO22X4 U8629 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][24] ), .B(n6680),
.C(n6752), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][24] ), .Z(n7569)
);
HS65_LH_AO22X4 U8630 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][24] ), .B(n6681),
.C(n7592), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][24] ), .Z(n7568)
);
HS65_LH_AOI22X1 U8631 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][24] ), .B(n6753),
.C(n7593), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][24] ), .Z(n7567)
);
HS65_LH_AOI22X1 U8632 ( .A(n6745), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][24] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][24] ), .D(n6746),
.Z(n7565) );
HS65_LH_AO22X4 U8633 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][24] ), .B(n6747),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[4][24] ), .D(
n6675), .Z(n7563) );
HS65_LH_AO22X4 U8634 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][24] ), .B(n7578),
.C(n7310), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][24] ), .Z(n7559)
);
HS65_LH_AOI22X1 U8635 ( .A(n6739), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][24] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][24] ), .D(n2890),
.Z(n7560) );
HS65_LH_AO22X4 U8636 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][28] ), .B(n7587),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[12][28] ), .D(
n7586), .Z(n7496) );
HS65_LH_AO22X4 U8637 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][28] ), .B(n7517),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[4][28] ), .D(
n6675), .Z(n7497) );
HS65_LH_AOI22X1 U8638 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][28] ), .B(n7524),
.C(n6683), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][28] ), .Z(n7501)
);
HS65_LH_AO22X4 U8639 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][22] ), .B(n6626),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[30][22] ), .D(
n6627), .Z(n6270) );
HS65_LH_AO22X4 U8640 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][22] ), .B(n6628),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[25][22] ), .D(
n6629), .Z(n6269) );
HS65_LH_AOI22X1 U8641 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][22] ), .B(n6385),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[0][22] ), .D(
n7296), .Z(n6277) );
HS65_LH_AO22X4 U8642 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][22] ), .B(n2884),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][22] ), .D(
n6382), .Z(n6280) );
HS65_LH_AO22X4 U8643 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][22] ), .B(n7170),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[23][22] ), .D(
n6637), .Z(n6275) );
HS65_LH_AO22X4 U8644 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][22] ), .B(n6634),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[20][22] ), .D(
n6635), .Z(n6276) );
HS65_LH_AO22X4 U8645 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][22] ), .B(n9375),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[6][22] ), .D(
n6619), .Z(n6265) );
HS65_LH_AO22X4 U8646 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][22] ), .B(n6364),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][22] ), .D(
n9372), .Z(n6266) );
HS65_LH_AO22X4 U8647 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][22] ), .B(n6680),
.C(n6752), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][22] ), .Z(n7007)
);
HS65_LH_AOI22X1 U8648 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][22] ), .B(n6753),
.C(n7593), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][22] ), .Z(n7005)
);
HS65_LH_AOI22X1 U8649 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][22] ), .B(n6951),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[10][22] ), .D(
n6670), .Z(n6999) );
HS65_LH_AOI22X1 U8650 ( .A(n6739), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][22] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][22] ), .D(n2890),
.Z(n6998) );
HS65_LH_AOI22X1 U8651 ( .A(n6745), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][22] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][22] ), .D(n6746),
.Z(n7003) );
HS65_LH_CNIVX3 U8652 ( .A(n9213), .Z(n5697) );
HS65_LH_AOI22X1 U8653 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][4] ), .B(n6690),
.C(n7334), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][4] ), .Z(n7359)
);
HS65_LH_AOI22X1 U8654 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][4] ), .B(n6689),
.C(n7333), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][4] ), .Z(n7360)
);
HS65_LH_AO22X4 U8655 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][4] ), .B(n6680),
.C(n6752), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][4] ), .Z(n7358)
);
HS65_LH_AOI22X1 U8656 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][4] ), .B(n6753),
.C(n6683), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][4] ), .Z(n7356)
);
HS65_LH_AO22X4 U8657 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][4] ), .B(n6681),
.C(n6682), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][4] ), .Z(n7357)
);
HS65_LH_AO22X4 U8658 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][4] ), .B(n7578),
.C(n6952), .D(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][4] ), .Z(n7348) );
HS65_LH_AOI22X1 U8659 ( .A(n6739), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][4] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][4] ), .D(n2890),
.Z(n7349) );
HS65_LH_AOI22X1 U8660 ( .A(n6745), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][4] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][4] ), .D(n6746),
.Z(n7354) );
HS65_LH_AO22X4 U8661 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][4] ), .B(n7517),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[4][4] ), .D(n6675), .Z(n7352) );
HS65_LH_AO22X4 U8662 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][8] ), .B(n7320),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[12][8] ), .D(
n7319), .Z(n6771) );
HS65_LH_AOI22X1 U8663 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][8] ), .B(n6951),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[10][8] ), .D(
n6670), .Z(n6770) );
HS65_LH_AOI22X1 U8664 ( .A(n7428), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][8] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][8] ), .D(n6740),
.Z(n6769) );
HS65_LH_AO22X4 U8665 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][8] ), .B(n7429),
.C(n7310), .D(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][8] ), .Z(n6768) );
HS65_LH_AO22X4 U8666 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][8] ), .B(n9373),
.C(n7311), .D(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][8] ), .Z(n6767) );
HS65_LH_AO22X4 U8667 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][8] ), .B(n7332),
.C(n7331), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][8] ), .Z(n6781)
);
HS65_LH_AO22X4 U8668 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][8] ), .B(n7330),
.C(n7329), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][8] ), .Z(n6782)
);
HS65_LH_AOI22X1 U8669 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][8] ), .B(n7525),
.C(n6684), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][8] ), .Z(n6775)
);
HS65_LH_AOI22X1 U8670 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][20] ), .B(n7524),
.C(n6683), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][20] ), .Z(n7481)
);
HS65_LH_AOI22X1 U8671 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][20] ), .B(n7525),
.C(n6684), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][20] ), .Z(n7480)
);
HS65_LH_AO22X4 U8672 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][20] ), .B(n7587),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[12][20] ), .D(
n7586), .Z(n7476) );
HS65_LH_AO22X4 U8673 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][20] ), .B(n7517),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[4][20] ), .D(
n6675), .Z(n7477) );
HS65_LH_AO22X4 U8674 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][20] ), .B(n7578),
.C(n6952), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][20] ), .Z(n7473)
);
HS65_LH_AOI22X1 U8675 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][16] ), .B(n6951),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[10][16] ), .D(
n2891), .Z(n7541) );
HS65_LH_AOI22X1 U8676 ( .A(n6739), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][16] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][16] ), .D(n2890),
.Z(n7540) );
HS65_LH_AO22X4 U8677 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][16] ), .B(n7578),
.C(n6952), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][16] ), .Z(n7539)
);
HS65_LH_AOI22X1 U8678 ( .A(n6745), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][16] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][16] ), .D(n6746),
.Z(n7545) );
HS65_LH_AO22X4 U8679 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][16] ), .B(n6747),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[4][16] ), .D(
n6675), .Z(n7543) );
HS65_LH_AOI22X1 U8680 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][16] ), .B(n6753),
.C(n7593), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][16] ), .Z(n7547)
);
HS65_LH_AO22X4 U8681 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][16] ), .B(n6681),
.C(n7592), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][16] ), .Z(n7548)
);
HS65_LH_AO22X4 U8682 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][16] ), .B(n6680),
.C(n6752), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][16] ), .Z(n7549)
);
HS65_LH_AOI22X1 U8683 ( .A(n6739), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][2] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][2] ), .D(n2890),
.Z(n6955) );
HS65_LH_AO22X4 U8684 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][2] ), .B(n7578),
.C(n6952), .D(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][2] ), .Z(n6954) );
HS65_LH_AOI22X1 U8685 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][2] ), .B(n6690),
.C(n7334), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][2] ), .Z(n6968)
);
HS65_LH_AOI22X1 U8686 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][2] ), .B(n6689),
.C(n7333), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][2] ), .Z(n6969)
);
HS65_LH_AOI22X1 U8687 ( .A(n6745), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][2] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][2] ), .D(n6746),
.Z(n6961) );
HS65_LH_AO22X4 U8688 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][2] ), .B(n7587),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[12][2] ), .D(
n7586), .Z(n6958) );
HS65_LH_AO22X4 U8689 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][2] ), .B(n6681),
.C(n6682), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][2] ), .Z(n6964)
);
HS65_LH_AOI22X1 U8690 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][2] ), .B(n6753),
.C(n6683), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][2] ), .Z(n6963)
);
HS65_LH_AO22X4 U8691 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][2] ), .B(n6680),
.C(n6752), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][2] ), .Z(n6965)
);
HS65_LH_CNIVX3 U8692 ( .A(n4261), .Z(n4266) );
HS65_LH_AOI22X1 U8693 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][18] ), .B(n6951),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[10][18] ), .D(
n6670), .Z(n6330) );
HS65_LH_CNIVX3 U8694 ( .A(n9220), .Z(n5700) );
HS65_LH_AOI22X1 U8695 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][6] ), .B(n6162),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[11][6] ), .D(
n2888), .Z(n6477) );
HS65_LH_AOI22X1 U8696 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][6] ), .B(n6371),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[29][6] ), .D(
n7272), .Z(n6481) );
HS65_LH_AO22X4 U8697 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][6] ), .B(n6628),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[25][6] ), .D(
n7276), .Z(n6479) );
HS65_LH_AO22X4 U8698 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][6] ), .B(n6317),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[13][6] ), .D(
n6383), .Z(n6489) );
HS65_LH_AOI22X1 U8699 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][6] ), .B(n7286),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[21][6] ), .D(
n6171), .Z(n6484) );
HS65_LH_AO22X4 U8700 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][6] ), .B(n6636),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[23][6] ), .D(
n7284), .Z(n6485) );
HS65_LH_AO22X4 U8701 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][6] ), .B(n7320),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[12][6] ), .D(
n7319), .Z(n7248) );
HS65_LH_AOI22X1 U8702 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][6] ), .B(n6951),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[10][6] ), .D(
n6670), .Z(n7247) );
HS65_LH_AOI22X1 U8703 ( .A(n7428), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][6] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][6] ), .D(n6740),
.Z(n7246) );
HS65_LH_AO22X4 U8704 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][6] ), .B(n9373),
.C(n7311), .D(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][6] ), .Z(n7244) );
HS65_LH_AO22X4 U8705 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][6] ), .B(n7332),
.C(n7331), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][6] ), .Z(n7258)
);
HS65_LH_AO22X4 U8706 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][6] ), .B(n7330),
.C(n7329), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][6] ), .Z(n7259)
);
HS65_LH_AOI22X1 U8707 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][6] ), .B(n7525),
.C(n6684), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][6] ), .Z(n7252)
);
HS65_LH_AO22X4 U8708 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][0] ), .B(n7587),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[12][0] ), .D(
n7586), .Z(n7435) );
HS65_LH_AO22X4 U8709 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][0] ), .B(n7517),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[4][0] ), .D(n6675), .Z(n7436) );
HS65_LH_AOI22X1 U8710 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][0] ), .B(n6951),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[10][0] ), .D(
n6670), .Z(n7433) );
HS65_LH_AOI22X1 U8711 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][0] ), .B(n7525),
.C(n6684), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][0] ), .Z(n7440)
);
HS65_LH_CNIVX3 U8712 ( .A(n7638), .Z(n7641) );
HS65_LH_NAND2X2 U8713 ( .A(\u_DataPath/immediate_ext_dec_i [2]), .B(
\u_DataPath/immediate_ext_dec_i [0]), .Z(n8089) );
HS65_LH_AO22X4 U8714 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][31] ), .B(n7320),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[12][31] ), .D(
n7319), .Z(n6676) );
HS65_LH_AOI22X1 U8715 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][31] ), .B(n6689),
.C(n6966), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][31] ), .Z(n6692)
);
HS65_LH_AOI22X1 U8716 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][31] ), .B(n6690),
.C(n6967), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][31] ), .Z(n6691)
);
HS65_LH_AO22X4 U8717 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][31] ), .B(n7330),
.C(n7329), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][31] ), .Z(n6694)
);
HS65_LH_AO22X4 U8718 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][31] ), .B(n7332),
.C(n7331), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][31] ), .Z(n6693)
);
HS65_LH_AOI22X1 U8719 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][31] ), .B(n7525),
.C(n6684), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][31] ), .Z(n6685)
);
HS65_LH_AO22X4 U8720 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][31] ), .B(n9373),
.C(n7311), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][31] ), .Z(n6671)
);
HS65_LH_AO22X4 U8721 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][31] ), .B(n7429),
.C(n6952), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][31] ), .Z(n6672)
);
HS65_LH_AOI22X1 U8722 ( .A(n7428), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][31] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][31] ), .D(n6740),
.Z(n6673) );
HS65_LHS_XOR2X3 U8723 ( .A(n7742), .B(n7741), .Z(\u_DataPath/pc_4_i [6]) );
HS65_LHS_XOR2X3 U8724 ( .A(n7758), .B(n7757), .Z(\u_DataPath/pc_4_i [18]) );
HS65_LH_BFX9 U8725 ( .A(n8288), .Z(n7897) );
HS65_LH_CNIVX3 U8726 ( .A(n8117), .Z(n8058) );
HS65_LH_OR2X4 U8727 ( .A(n8911), .B(n9202), .Z(n5919) );
HS65_LH_IVX2 U8728 ( .A(Data_out_fromRAM[31]), .Z(n8420) );
HS65_LH_IVX44 U8736 ( .A(n8270), .Z(nibble[0]) );
HS65_LH_IVX40 U8737 ( .A(\u_DataPath/pc_4_i [2]), .Z(addr_to_iram[0]) );
HS65_LH_IVX40 U8738 ( .A(n7669), .Z(addr_to_iram[2]) );
HS65_LH_IVX40 U8739 ( .A(n7745), .Z(addr_to_iram[3]) );
HS65_LH_IVX40 U8740 ( .A(n7667), .Z(addr_to_iram[5]) );
HS65_LH_IVX40 U8741 ( .A(n7769), .Z(addr_to_iram[19]) );
HS65_LH_IVX40 U8742 ( .A(n7756), .Z(addr_to_iram[20]) );
HS65_LH_IVX40 U8743 ( .A(n7766), .Z(addr_to_iram[21]) );
HS65_LH_IVX40 U8744 ( .A(n7705), .Z(addr_to_iram[27]) );
HS65_LH_NAND2AX4 U8745 ( .A(n8480), .B(n9110), .Z(n8048) );
HS65_LH_AO22X4 U8746 ( .A(n9185), .B(n8067), .C(n8966), .D(n8066), .Z(
\u_DataPath/RFaddr_out_memwb_i [1]) );
HS65_LH_AO22X4 U8747 ( .A(n8765), .B(n9252), .C(n9325), .D(n9153), .Z(
\u_DataPath/jaddr_i [22]) );
HS65_LH_NAND2AX4 U8748 ( .A(n8480), .B(\u_DataPath/cw_exmem_i [10]), .Z(
n7833) );
HS65_LH_CNIVX3 U8749 ( .A(n8761), .Z(n8063) );
HS65_LH_CNIVX3 U8750 ( .A(n8764), .Z(n8065) );
HS65_LH_NOR2X2 U8751 ( .A(n8177), .B(rst), .Z(n8580) );
HS65_LH_NAND2AX4 U8752 ( .A(n8480), .B(n9238), .Z(n8137) );
HS65_LH_AO222X4 U8753 ( .A(n7896), .B(\u_DataPath/pc_4_i [26]), .C(n7893),
.D(\u_DataPath/jump_address_i [26]), .E(n8940), .F(n7887), .Z(n8646)
);
HS65_LH_AO222X4 U8754 ( .A(n7896), .B(\u_DataPath/pc_4_i [25]), .C(n7893),
.D(n9415), .E(n9199), .F(n7887), .Z(n8647) );
HS65_LH_AO222X4 U8755 ( .A(n7895), .B(\u_DataPath/pc_4_i [15]), .C(n7892),
.D(n9418), .E(n8930), .F(n7888), .Z(n8657) );
HS65_LH_AO222X4 U8756 ( .A(n7895), .B(\u_DataPath/pc_4_i [13]), .C(n7892),
.D(n9413), .E(n8919), .F(n7888), .Z(n8659) );
HS65_LH_AO222X4 U8757 ( .A(n7895), .B(\u_DataPath/pc_4_i [20]), .C(n7892),
.D(n9404), .E(n8926), .F(n7887), .Z(n8652) );
HS65_LH_NAND2X2 U8758 ( .A(n2733), .B(\u_DataPath/cw_memwb_i [2]), .Z(n8061)
);
HS65_LH_NOR2X2 U8759 ( .A(n8107), .B(rst), .Z(
\u_DataPath/regfile_addr_out_towb_i [4]) );
HS65_LH_CNIVX3 U8760 ( .A(n8763), .Z(n8108) );
HS65_LH_AO22X4 U8761 ( .A(n9267), .B(n8067), .C(n8967), .D(n8066), .Z(
\u_DataPath/RFaddr_out_memwb_i [2]) );
HS65_LH_AO22X4 U8762 ( .A(n9183), .B(n8067), .C(n8942), .D(n8066), .Z(
\u_DataPath/RFaddr_out_memwb_i [0]) );
HS65_LH_AO22X4 U8763 ( .A(n9145), .B(n8067), .C(n8968), .D(n8066), .Z(
\u_DataPath/RFaddr_out_memwb_i [4]) );
HS65_LH_AO22X4 U8764 ( .A(n9181), .B(n8067), .C(n9077), .D(n8066), .Z(
\u_DataPath/RFaddr_out_memwb_i [3]) );
HS65_LH_AOI22X1 U8765 ( .A(n8868), .B(n9184), .C(n9365), .D(n9057), .Z(n8416) );
HS65_LH_NAND3X2 U8766 ( .A(n2733), .B(n8715), .C(\u_DataPath/cw_to_ex_i [15]), .Z(n8428) );
HS65_LH_AOI22X1 U8768 ( .A(n8868), .B(n9170), .C(n9365), .D(n9020), .Z(n8317) );
HS65_LH_CNIVX3 U8769 ( .A(n9207), .Z(n7119) );
HS65_LH_AOI22X1 U8770 ( .A(n8868), .B(n9172), .C(n9369), .D(n8987), .Z(n8328) );
HS65_LH_OAI21X3 U8771 ( .A(n9189), .B(n8902), .C(n8375), .Z(
\u_DataPath/dataOut_exe_i [27]) );
HS65_LH_AOI22X1 U8772 ( .A(n8868), .B(n9182), .C(n9366), .D(n8996), .Z(n8375) );
HS65_LL_OAI21X12 U8773 ( .A(n3009), .B(n8140), .C(n2733), .Z(
\u_DataPath/u_decode_unit/reg_file0/N140 ) );
HS65_LL_OAI21X12 U8774 ( .A(n8140), .B(n2773), .C(n2733), .Z(
\u_DataPath/u_decode_unit/reg_file0/N141 ) );
HS65_LL_OAI21X12 U8775 ( .A(n8140), .B(n8147), .C(n2733), .Z(
\u_DataPath/u_decode_unit/reg_file0/N143 ) );
HS65_LL_OAI21X12 U8776 ( .A(n8140), .B(n3010), .C(n2733), .Z(
\u_DataPath/u_decode_unit/reg_file0/N145 ) );
HS65_LHS_XOR2X3 U8777 ( .A(n6037), .B(n6089), .Z(
\u_DataPath/u_execute/resAdd1_i [6]) );
HS65_LHS_XOR2X3 U8778 ( .A(n6012), .B(n6065), .Z(
\u_DataPath/u_execute/resAdd1_i [18]) );
HS65_LHS_XOR2X3 U8779 ( .A(n6025), .B(n6024), .Z(
\u_DataPath/u_execute/resAdd1_i [17]) );
HS65_LHS_XOR2X3 U8780 ( .A(n6004), .B(n6003), .Z(
\u_DataPath/u_execute/resAdd1_i [20]) );
HS65_LH_NAND3AX3 U8781 ( .A(n5693), .B(n5692), .C(n5691), .Z(n8503) );
HS65_LHS_XOR2X3 U8782 ( .A(n6032), .B(n6077), .Z(
\u_DataPath/u_execute/resAdd1_i [8]) );
HS65_LH_NAND2X2 U8783 ( .A(n6110), .B(n6109), .Z(n6112) );
HS65_LH_NAND2X2 U8784 ( .A(n6106), .B(n6105), .Z(n6108) );
HS65_LHS_XOR2X3 U8786 ( .A(n6044), .B(n6043), .Z(
\u_DataPath/u_execute/resAdd1_i [5]) );
HS65_LHS_XOR2X3 U8787 ( .A(n6018), .B(n6017), .Z(
\u_DataPath/u_execute/resAdd1_i [21]) );
HS65_LHS_XOR2X3 U8788 ( .A(n5994), .B(n5993), .Z(
\u_DataPath/u_execute/resAdd1_i [13]) );
HS65_LH_CNIVX3 U8789 ( .A(n6125), .Z(n8513) );
HS65_LH_AO22X9 U8790 ( .A(n9258), .B(n9188), .C(n9133), .D(n8999), .Z(
\u_DataPath/jump_address_i [30]) );
HS65_LHS_XNOR2X3 U8791 ( .A(n6072), .B(n6071), .Z(
\u_DataPath/u_execute/resAdd1_i [10]) );
HS65_LH_AOI21X2 U8792 ( .A(n2866), .B(n8537), .C(n8536), .Z(
\u_DataPath/mem_writedata_out_i [19]) );
HS65_LHS_XOR2X3 U8793 ( .A(n5986), .B(n5985), .Z(
\u_DataPath/u_execute/resAdd1_i [11]) );
HS65_LH_NOR4ABX2 U8794 ( .A(n6224), .B(n6223), .C(n6222), .D(n6221), .Z(
n8377) );
HS65_LHS_XOR2X3 U8795 ( .A(n5970), .B(n5969), .Z(
\u_DataPath/u_execute/resAdd1_i [15]) );
HS65_LHS_XNOR2X3 U8796 ( .A(n6060), .B(n6059), .Z(
\u_DataPath/u_execute/resAdd1_i [14]) );
HS65_LH_NOR4ABX2 U8797 ( .A(n6393), .B(n6392), .C(n6391), .D(n6390), .Z(
n8309) );
HS65_LH_NOR4ABX2 U8798 ( .A(n6264), .B(n6263), .C(n6262), .D(n6261), .Z(
n8347) );
HS65_LH_NOR4ABX2 U8799 ( .A(n6534), .B(n6533), .C(n6532), .D(n6531), .Z(
n8325) );
HS65_LH_NOR4ABX2 U8801 ( .A(n6594), .B(n6593), .C(n6592), .D(n6591), .Z(
n8174) );
HS65_LH_NOR4ABX2 U8802 ( .A(n6413), .B(n6412), .C(n6411), .D(n6410), .Z(
n8296) );
HS65_LH_CNIVX3 U8803 ( .A(n9214), .Z(n7727) );
HS65_LH_NOR4ABX2 U8804 ( .A(n6514), .B(n6513), .C(n6512), .D(n6511), .Z(
n8320) );
HS65_LH_NOR4ABX2 U8805 ( .A(n6244), .B(n6243), .C(n6242), .D(n6241), .Z(
n8361) );
HS65_LH_AOI22X1 U8806 ( .A(n8868), .B(n9174), .C(n9368), .D(n8975), .Z(n8359) );
HS65_LH_NOR4ABX2 U8807 ( .A(n6554), .B(n6553), .C(n6552), .D(n6551), .Z(
n8292) );
HS65_LH_NOR4ABX2 U8808 ( .A(n6454), .B(n6453), .C(n6452), .D(n6451), .Z(
n8303) );
HS65_LH_CNIVX3 U8809 ( .A(n9227), .Z(n7709) );
HS65_LH_CNIVX3 U8810 ( .A(n9228), .Z(n7732) );
HS65_LH_NOR4ABX2 U8811 ( .A(n6950), .B(n6949), .C(n6948), .D(n6947), .Z(
n8414) );
HS65_LH_AOI22X1 U8813 ( .A(n8868), .B(n9176), .C(n9369), .D(n8983), .Z(n8369) );
HS65_LH_CNIVX3 U8814 ( .A(n9209), .Z(n7121) );
HS65_LH_NOR4ABX2 U8815 ( .A(n6926), .B(n6925), .C(n6924), .D(n6923), .Z(
n8418) );
HS65_LH_AOI22X1 U8816 ( .A(n8868), .B(n9178), .C(n9365), .D(n8938), .Z(n7856) );
HS65_LH_CBI4I1X3 U8817 ( .A(n2874), .B(n8724), .C(n7846), .D(n8566), .Z(
n8493) );
HS65_LH_AO22X9 U8818 ( .A(n8872), .B(n9188), .C(n9133), .D(n9041), .Z(
\u_DataPath/jump_address_i [4]) );
HS65_LH_NOR4ABX2 U8819 ( .A(n6649), .B(n6648), .C(n6647), .D(n6646), .Z(
n8430) );
HS65_LH_CNIVX3 U8820 ( .A(n9219), .Z(n7726) );
HS65_LH_NOR4ABX2 U8821 ( .A(n6474), .B(n6473), .C(n6472), .D(n6471), .Z(
n8274) );
HS65_LHS_XNOR2X3 U8822 ( .A(n7719), .B(n7781), .Z(
\u_DataPath/u_execute/link_value_i [8]) );
HS65_LH_CNIVX3 U8823 ( .A(n9229), .Z(n7719) );
HS65_LH_NOR4ABX2 U8824 ( .A(n6866), .B(n6865), .C(n6864), .D(n6863), .Z(
n8411) );
HS65_LH_AOI22X1 U8825 ( .A(n8868), .B(n8912), .C(n9366), .D(n9046), .Z(n8409) );
HS65_LH_NOR4ABX2 U8826 ( .A(n6184), .B(n6183), .C(n6182), .D(n6181), .Z(
n8357) );
HS65_LHS_XOR2X3 U8828 ( .A(n7715), .B(n7714), .Z(n5690) );
HS65_LH_NOR4ABX2 U8829 ( .A(n6906), .B(n6905), .C(n6904), .D(n6903), .Z(
n8407) );
HS65_LH_AOI22X1 U8830 ( .A(n8868), .B(n9036), .C(n9366), .D(n9017), .Z(n8405) );
HS65_LH_AOI21X2 U8831 ( .A(n2874), .B(n8490), .C(n8489), .Z(
\u_DataPath/mem_writedata_out_i [2]) );
HS65_LH_AO22X9 U8832 ( .A(n9188), .B(n9021), .C(n9133), .D(n8945), .Z(
\u_DataPath/jump_address_i [2]) );
HS65_LHS_XOR2X3 U8833 ( .A(n6052), .B(n6101), .Z(
\u_DataPath/u_execute/resAdd1_i [2]) );
HS65_LH_NOR4ABX2 U8834 ( .A(n6574), .B(n6573), .C(n6572), .D(n6571), .Z(
n8173) );
HS65_LH_NOR4ABX2 U8835 ( .A(n6669), .B(n6668), .C(n6667), .D(n6666), .Z(
n8455) );
HS65_LH_MX41X4 U8836 ( .D0(n8441), .S0(n9280), .D1(n8440), .S1(n9295), .D2(
n9302), .S2(n8439), .D3(n8438), .S3(n9287), .Z(
\u_DataPath/from_mem_data_out_i [6]) );
HS65_LH_MX41X4 U8837 ( .D0(n8441), .S0(n9279), .D1(n8440), .S1(n9294), .D2(
n9301), .S2(n8439), .D3(n8438), .S3(n9286), .Z(
\u_DataPath/from_mem_data_out_i [5]) );
HS65_LH_MX41X4 U8838 ( .D0(n8441), .S0(n9278), .D1(n8440), .S1(n9293), .D2(
n9300), .S2(n8439), .D3(n8438), .S3(n9285), .Z(
\u_DataPath/from_mem_data_out_i [4]) );
HS65_LH_MX41X4 U8839 ( .D0(n8441), .S0(n9277), .D1(n8440), .S1(n9292), .D2(
n9299), .S2(n8439), .D3(n8438), .S3(n9284), .Z(
\u_DataPath/from_mem_data_out_i [3]) );
HS65_LH_MX41X4 U8840 ( .D0(n8441), .S0(n9276), .D1(n8440), .S1(n9291), .D2(
n9298), .S2(n8439), .D3(n8438), .S3(n9283), .Z(
\u_DataPath/from_mem_data_out_i [2]) );
HS65_LH_AO22X9 U8841 ( .A(n9133), .B(n8935), .C(n9188), .D(n9105), .Z(
\u_DataPath/jump_address_i [1]) );
HS65_LH_NOR4ABX2 U8843 ( .A(n6616), .B(n6615), .C(n6614), .D(n6613), .Z(
n8167) );
HS65_LH_OR2X4 U8846 ( .A(n9035), .B(n9115), .Z(n5918) );
HS65_LH_NOR4ABX2 U8847 ( .A(n6434), .B(n6433), .C(n6432), .D(n6431), .Z(
n8169) );
HS65_LH_NOR4ABX2 U8848 ( .A(n6886), .B(n6885), .C(n6884), .D(n6883), .Z(
n8421) );
HS65_LH_AO22X4 U8849 ( .A(n8757), .B(n9138), .C(n9320), .D(n9153), .Z(
\u_DataPath/jaddr_i [17]) );
HS65_LH_NOR2X2 U8850 ( .A(n8164), .B(rst), .Z(\u_DataPath/rs_ex_i [1]) );
HS65_LH_NOR2X2 U8851 ( .A(n8165), .B(rst), .Z(\u_DataPath/rs_ex_i [2]) );
HS65_LH_AO22X4 U8852 ( .A(n8756), .B(n9252), .C(n9328), .D(n9153), .Z(
\u_DataPath/jaddr_i [25]) );
HS65_LH_NAND2AX4 U8853 ( .A(n8480), .B(\u_DataPath/u_idexreg/N10 ), .Z(n8136) );
HS65_LH_NAND2AX4 U8854 ( .A(n8480), .B(\u_DataPath/u_idexreg/N16 ), .Z(n8111) );
HS65_LH_NAND2AX4 U8855 ( .A(n8480), .B(\u_DataPath/cw_exmem_i [5]), .Z(n8113) );
HS65_LH_NAND2AX4 U8856 ( .A(n8480), .B(\u_DataPath/u_idexreg/N15 ), .Z(n8112) );
HS65_LH_NAND2AX4 U8857 ( .A(n8480), .B(\u_DataPath/cw_exmem_i [4]), .Z(n8109) );
HS65_LH_NOR4ABX4 U8858 ( .A(opcode_i[1]), .B(n8116), .C(n8056), .D(n8117),
.Z(\u_DataPath/cw_to_ex_i [17]) );
HS65_LH_NAND2AX4 U8859 ( .A(n8480), .B(\u_DataPath/cw_exmem_i [6]), .Z(n8110) );
HS65_LH_NAND2AX4 U8860 ( .A(n8480), .B(n9052), .Z(n8481) );
HS65_LH_NAND2AX4 U8861 ( .A(n8480), .B(n9048), .Z(n8233) );
HS65_LH_NOR2X2 U8862 ( .A(n8152), .B(rst), .Z(\u_DataPath/idex_rt_i [0]) );
HS65_LH_AO22X4 U8863 ( .A(n8754), .B(n9138), .C(n9319), .D(n9153), .Z(
\u_DataPath/jaddr_i [16]) );
HS65_LH_AND2X4 U8864 ( .A(n2733), .B(\u_DataPath/toPC2_i [28]), .Z(
\u_DataPath/branch_target_i [28]) );
HS65_LH_CNIVX3 U8865 ( .A(n5743), .Z(n5744) );
HS65_LH_AND2X4 U8866 ( .A(n2733), .B(\u_DataPath/toPC2_i [26]), .Z(
\u_DataPath/branch_target_i [26]) );
HS65_LHS_XOR2X3 U8867 ( .A(n5810), .B(n5809), .Z(\u_DataPath/toPC2_i [20])
);
HS65_LHS_XOR2X3 U8868 ( .A(n5804), .B(n5803), .Z(\u_DataPath/toPC2_i [19])
);
HS65_LHS_XOR2X3 U8869 ( .A(n5816), .B(n5815), .Z(\u_DataPath/toPC2_i [18])
);
HS65_LHS_XOR2X3 U8870 ( .A(n5823), .B(n5822), .Z(\u_DataPath/toPC2_i [17])
);
HS65_LHS_XOR2X3 U8871 ( .A(n5766), .B(n5765), .Z(\u_DataPath/toPC2_i [15])
);
HS65_LH_AOI12X2 U8872 ( .A(n6057), .B(n5864), .C(n5764), .Z(n5765) );
HS65_LHS_XNOR2X3 U8873 ( .A(n5865), .B(n5864), .Z(\u_DataPath/toPC2_i [14])
);
HS65_LHS_XOR2X3 U8874 ( .A(n5794), .B(n5793), .Z(\u_DataPath/toPC2_i [13])
);
HS65_LHS_XOR2X3 U8875 ( .A(n5785), .B(n5784), .Z(\u_DataPath/toPC2_i [11])
);
HS65_LHS_XNOR2X3 U8876 ( .A(n5873), .B(n5872), .Z(\u_DataPath/toPC2_i [10])
);
HS65_LHS_XOR2X3 U8877 ( .A(n5830), .B(n5878), .Z(\u_DataPath/toPC2_i [8]) );
HS65_LHS_XOR2X3 U8879 ( .A(n5835), .B(n5886), .Z(\u_DataPath/toPC2_i [6]) );
HS65_LHS_XOR2X3 U8881 ( .A(n5842), .B(n5841), .Z(\u_DataPath/toPC2_i [5]) );
HS65_LHS_XOR2X3 U8882 ( .A(n5845), .B(n5898), .Z(\u_DataPath/toPC2_i [2]) );
HS65_LL_NOR4ABX2 U8885 ( .A(n7243), .B(n7242), .C(n7241), .D(n7240), .Z(
n8178) );
HS65_LL_NOR4ABX2 U8887 ( .A(n7342), .B(n7341), .C(n7340), .D(n7339), .Z(
n8315) );
HS65_LL_NOR4ABX2 U8889 ( .A(n7263), .B(n7262), .C(n7261), .D(n7260), .Z(
n8310) );
HS65_LLS_XNOR2X3 U8892 ( .A(n4422), .B(n4421), .Z(n4423) );
HS65_LL_AND2X4 U8893 ( .A(n4714), .B(n8515), .Z(n3261) );
HS65_LH_AOI22X1 U8894 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][4] ), .B(n6754),
.C(n6684), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][4] ), .Z(n7355)
);
HS65_LH_NOR2X6 U8895 ( .A(n6353), .B(n6332), .Z(n2889) );
HS65_LH_NOR2X6 U8896 ( .A(n6350), .B(n6332), .Z(n2890) );
HS65_LH_NOR2X6 U8897 ( .A(n6349), .B(n2878), .Z(n2891) );
HS65_LH_AOI22X1 U8898 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][23] ), .B(n6376),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[21][23] ), .D(
n6171), .Z(n6234) );
HS65_LH_AOI22X1 U8899 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][27] ), .B(n6376),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[21][27] ), .D(
n6171), .Z(n6214) );
HS65_LL_NOR3AX9 U8901 ( .A(n3344), .B(n3343), .C(n3342), .Z(\lte_x_59/B[4] )
);
HS65_LH_NOR2X2 U8902 ( .A(n3474), .B(n3359), .Z(n5298) );
HS65_LL_NAND4ABX3 U8903 ( .A(n3824), .B(n3823), .C(n3822), .D(n3821), .Z(
n4840) );
HS65_LH_NOR2X2 U8904 ( .A(\lte_x_59/B[24] ), .B(n3382), .Z(n5426) );
HS65_LH_AND3X4 U8905 ( .A(n4836), .B(\sub_x_53/A[2] ), .C(n4552), .Z(n2901)
);
HS65_LL_NOR2AX3 U8906 ( .A(n3554), .B(n3553), .Z(n3555) );
HS65_LL_AND2X4 U8907 ( .A(n9205), .B(n7307), .Z(n2908) );
HS65_LL_AND2X4 U8908 ( .A(n2963), .B(n2962), .Z(n2912) );
HS65_LL_OR2X4 U8909 ( .A(n8798), .B(n3403), .Z(n2913) );
HS65_LL_AND2X4 U8910 ( .A(n4289), .B(n4211), .Z(n2914) );
HS65_LL_AND2X4 U8911 ( .A(n4714), .B(n8530), .Z(n2919) );
HS65_LL_AND2X4 U8912 ( .A(n3327), .B(n9145), .Z(n2922) );
HS65_LH_AND2X4 U8913 ( .A(n4717), .B(n9181), .Z(n2923) );
HS65_LH_IVX9 U8915 ( .A(n7802), .Z(n8390) );
HS65_LLS_XNOR2X3 U8916 ( .A(n3008), .B(n8942), .Z(n2953) );
HS65_LLS_XNOR2X3 U8917 ( .A(n7086), .B(n2950), .Z(n2951) );
HS65_LL_AND2ABX18 U8919 ( .A(n7638), .B(n2974), .Z(write_byte) );
HS65_LL_AND2X18 U8920 ( .A(n8879), .B(write_op), .Z(Data_in[4]) );
HS65_LL_NOR2AX25 U8921 ( .A(\u_DataPath/dataOut_exe_i [31]), .B(n3116), .Z(
Address_toRAM[29]) );
HS65_LL_NOR2AX25 U8922 ( .A(\u_DataPath/dataOut_exe_i [9]), .B(n2986), .Z(
Address_toRAM[7]) );
HS65_LL_NOR2AX25 U8923 ( .A(\u_DataPath/dataOut_exe_i [7]), .B(n2986), .Z(
Address_toRAM[5]) );
HS65_LL_NOR2AX25 U8924 ( .A(\u_DataPath/dataOut_exe_i [14]), .B(n2986), .Z(
Address_toRAM[12]) );
HS65_LL_NOR2AX25 U8925 ( .A(\u_DataPath/dataOut_exe_i [16]), .B(n2986), .Z(
Address_toRAM[14]) );
HS65_LL_NOR2AX25 U8926 ( .A(n8738), .B(n2994), .Z(Data_in[16]) );
HS65_LL_NOR2AX25 U8927 ( .A(n8739), .B(n2994), .Z(Data_in[14]) );
HS65_LL_NOR2AX25 U8928 ( .A(n8730), .B(n2994), .Z(Data_in[12]) );
HS65_LL_NOR2AX25 U8929 ( .A(n8735), .B(n2994), .Z(Data_in[11]) );
HS65_LL_NOR2AX25 U8930 ( .A(n8741), .B(n2994), .Z(Data_in[10]) );
HS65_LL_NOR2AX25 U8931 ( .A(n8734), .B(n2994), .Z(Data_in[15]) );
HS65_LL_NOR2AX25 U8932 ( .A(n8740), .B(n2994), .Z(Data_in[17]) );
HS65_LL_NOR2AX25 U8933 ( .A(n8746), .B(n2994), .Z(Data_in[21]) );
HS65_LL_NOR2AX25 U8934 ( .A(n8747), .B(n2994), .Z(Data_in[20]) );
HS65_LL_NOR2AX25 U8935 ( .A(\u_DataPath/dataOut_exe_i [15]), .B(n2986), .Z(
Address_toRAM[13]) );
HS65_LL_NOR2AX25 U8936 ( .A(\u_DataPath/dataOut_exe_i [17]), .B(n2986), .Z(
Address_toRAM[15]) );
HS65_LL_NOR2AX25 U8937 ( .A(\u_DataPath/dataOut_exe_i [26]), .B(n3116), .Z(
Address_toRAM[24]) );
HS65_LH_IVX2 U8939 ( .A(n7086), .Z(n3011) );
HS65_LL_AND2X18 U8940 ( .A(n9018), .B(write_op), .Z(Data_in[0]) );
HS65_LH_OAI22X1 U8941 ( .A(n3285), .B(n4712), .C(n3288), .D(n9401), .Z(n8484) );
HS65_LH_MUXI21X2 U8942 ( .D0(n3018), .D1(n9379), .S0(n3404), .Z(n8243) );
HS65_LH_MUXI21X2 U8943 ( .D0(n3020), .D1(n9393), .S0(
\u_DataPath/cw_towb_i [0]), .Z(n8374) );
HS65_LH_NAND2X7 U8944 ( .A(\u_DataPath/cw_memwb_i [2]), .B(n3035), .Z(n3044)
);
HS65_LLS_XNOR2X3 U8945 ( .A(n8762), .B(n8911), .Z(n3038) );
HS65_LH_MUXI21X2 U8946 ( .D0(n3047), .D1(n9392), .S0(n3404), .Z(n8380) );
HS65_LH_AND2X4 U8947 ( .A(\u_DataPath/dataOut_exe_i [0]), .B(n3407), .Z(
n3068) );
HS65_LH_NOR2X6 U8948 ( .A(n8831), .B(n3341), .Z(n3073) );
HS65_LH_NOR2X6 U8949 ( .A(n8826), .B(n3341), .Z(n3076) );
HS65_LH_MUXI21X2 U8950 ( .D0(n3079), .D1(n9398), .S0(
\u_DataPath/cw_towb_i [0]), .Z(n8332) );
HS65_LH_MUXI21X2 U8951 ( .D0(n3084), .D1(n9391), .S0(
\u_DataPath/cw_towb_i [0]), .Z(n8387) );
HS65_LH_NOR2X6 U8952 ( .A(n8851), .B(n3341), .Z(n3091) );
HS65_LH_MUXI21X2 U8953 ( .D0(n3088), .D1(n9382), .S0(n3404), .Z(n8389) );
HS65_LH_MUXI21X2 U8954 ( .D0(n3093), .D1(n9390), .S0(n3404), .Z(n8355) );
HS65_LH_NOR2X6 U8955 ( .A(n8855), .B(n3403), .Z(n3106) );
HS65_LH_MUXI21X2 U8956 ( .D0(n3103), .D1(n9378), .S0(n3404), .Z(n8266) );
HS65_LL_AO112X18 U8957 ( .A(n8578), .B(n3112), .C(n2879), .D(n8577), .Z(
read_op) );
HS65_LL_OR2ABX18 U8958 ( .A(n8576), .B(n8575), .Z(nibble[1]) );
HS65_LL_NOR2AX25 U8959 ( .A(\u_DataPath/dataOut_exe_i [6]), .B(n2986), .Z(
Address_toRAM[4]) );
HS65_LL_NOR2AX25 U8960 ( .A(\u_DataPath/dataOut_exe_i [5]), .B(n2986), .Z(
Address_toRAM[3]) );
HS65_LL_NOR2AX25 U8961 ( .A(\u_DataPath/dataOut_exe_i [3]), .B(n2986), .Z(
Address_toRAM[1]) );
HS65_LL_NOR2AX25 U8962 ( .A(\u_DataPath/dataOut_exe_i [19]), .B(n3116), .Z(
Address_toRAM[17]) );
HS65_LL_NOR2AX25 U8963 ( .A(\u_DataPath/dataOut_exe_i [18]), .B(n3116), .Z(
Address_toRAM[16]) );
HS65_LL_NOR2AX25 U8964 ( .A(\u_DataPath/dataOut_exe_i [2]), .B(n3116), .Z(
Address_toRAM[0]) );
HS65_LL_NOR2AX25 U8965 ( .A(n8733), .B(n3115), .Z(Data_in[26]) );
HS65_LL_NOR2AX25 U8966 ( .A(n9085), .B(n3115), .Z(Data_in[25]) );
HS65_LL_NOR2AX25 U8967 ( .A(n8732), .B(n3115), .Z(Data_in[24]) );
HS65_LL_AND2ABX18 U8968 ( .A(n8574), .B(n3116), .Z(Address_toRAM[2]) );
HS65_LH_IVX40 U8969 ( .A(n3126), .Z(addr_to_iram[1]) );
HS65_LL_AND2X18 U8970 ( .A(n8731), .B(write_op), .Z(Data_in[5]) );
HS65_LL_AND2X18 U8971 ( .A(n8744), .B(write_op), .Z(Data_in[1]) );
HS65_LL_AND2X18 U8972 ( .A(n8745), .B(write_op), .Z(Data_in[7]) );
HS65_LL_AND2X18 U8973 ( .A(n8725), .B(write_op), .Z(Data_in[3]) );
HS65_LL_AND2X18 U8974 ( .A(n8873), .B(write_op), .Z(Data_in[2]) );
HS65_LL_AND2X18 U8975 ( .A(n8743), .B(write_op), .Z(Data_in[6]) );
HS65_LH_BFX18 U8978 ( .A(n9376), .Z(n4714) );
HS65_LH_NOR2X6 U8980 ( .A(n3572), .B(n3575), .Z(n3751) );
HS65_LH_MUXI21X2 U8981 ( .D0(n7877), .D1(n9388), .S0(
\u_DataPath/cw_towb_i [0]), .Z(n8316) );
HS65_LL_MUXI21X2 U8982 ( .D0(n3185), .D1(n9387), .S0(
\u_DataPath/cw_towb_i [0]), .Z(n8323) );
HS65_LH_IVX9 U8983 ( .A(n5005), .Z(n3371) );
HS65_LH_NOR2X6 U8984 ( .A(n8822), .B(n3403), .Z(n3200) );
HS65_LH_NOR2X6 U8985 ( .A(\sub_x_53/A[17] ), .B(n2870), .Z(n3515) );
HS65_LH_NOR2X6 U8986 ( .A(n8860), .B(n3403), .Z(n3214) );
HS65_LH_NOR2X2 U8987 ( .A(n8265), .B(n8262), .Z(n3219) );
HS65_LH_MUXI21X2 U8989 ( .D0(n3248), .D1(n9397), .S0(n3404), .Z(n8339) );
HS65_LH_MUXI21X2 U8990 ( .D0(n3259), .D1(n9381), .S0(
\u_DataPath/cw_towb_i [0]), .Z(n8255) );
HS65_LH_MUXI21X2 U8991 ( .D0(n8909), .D1(
\u_DataPath/from_mem_data_out_i [15]), .S0(\u_DataPath/cw_towb_i [0]),
.Z(n8306) );
HS65_LH_NOR2X6 U8992 ( .A(n8840), .B(n3290), .Z(n3292) );
HS65_LL_OAI22X3 U8993 ( .A(n3333), .B(\u_DataPath/dataOut_exe_i [2]), .C(
n8488), .D(n3340), .Z(n3295) );
HS65_LH_NAND2X7 U8994 ( .A(n3296), .B(n7802), .Z(n8487) );
HS65_LH_AND2X4 U8995 ( .A(n3309), .B(n3308), .Z(n3311) );
HS65_LH_NOR2X6 U8996 ( .A(n8857), .B(n3403), .Z(n3320) );
HS65_LH_AND2X4 U8998 ( .A(n2896), .B(n3337), .Z(n7863) );
HS65_LH_NAND2X7 U8999 ( .A(\lte_x_59/B[18] ), .B(n3371), .Z(n5272) );
HS65_LH_NAND2X7 U9000 ( .A(n2849), .B(n3372), .Z(n5270) );
HS65_LH_MUX21I1X3 U9001 ( .D0(n3402), .D1(n5183), .S0(n5088), .Z(n4457) );
HS65_LH_NOR2X6 U9002 ( .A(n8823), .B(n3403), .Z(n3411) );
HS65_LL_NOR2AX3 U9003 ( .A(n2866), .B(n3418), .Z(n7846) );
HS65_LH_AOI22X1 U9004 ( .A(\sub_x_53/A[23] ), .B(n4587), .C(n2864), .D(
\lte_x_59/B[21] ), .Z(n3435) );
HS65_LH_NOR2X2 U9005 ( .A(n4726), .B(n2893), .Z(n3439) );
HS65_LH_NAND3X2 U9006 ( .A(n4551), .B(n4836), .C(n4949), .Z(n3444) );
HS65_LH_AOI22X1 U9007 ( .A(\sub_x_53/A[27] ), .B(n4587), .C(n3789), .D(
\sub_x_53/A[25] ), .Z(n3445) );
HS65_LH_NAND2X7 U9008 ( .A(n5321), .B(n5088), .Z(n4838) );
HS65_LH_OAI21X3 U9009 ( .A(n3272), .B(n2857), .C(n3839), .Z(n3459) );
HS65_LH_NOR2AX3 U9010 ( .A(n3469), .B(n3468), .Z(n3512) );
HS65_LH_CNIVX3 U9012 ( .A(n3617), .Z(n3494) );
HS65_LH_NAND2X2 U9014 ( .A(\lte_x_59/B[9] ), .B(n4551), .Z(n3526) );
HS65_LH_NAND3X2 U9015 ( .A(\sub_x_53/A[17] ), .B(n3582), .C(n5001), .Z(n3531) );
HS65_LH_CBI4I1X3 U9016 ( .A(n9352), .B(n5001), .C(\sub_x_53/A[17] ), .D(
n5647), .Z(n3530) );
HS65_LH_OAI21X3 U9017 ( .A(n5621), .B(n4889), .C(n3604), .Z(n3605) );
HS65_LH_NOR2AX3 U9018 ( .A(\sub_x_53/A[2] ), .B(n2857), .Z(n3641) );
HS65_LH_OA12X9 U9019 ( .A(n5129), .B(n4811), .C(n4794), .Z(n3642) );
HS65_LH_NOR2X6 U9020 ( .A(n2840), .B(n3756), .Z(n4507) );
HS65_LH_NAND3X2 U9022 ( .A(n4836), .B(n5624), .C(n4504), .Z(n3653) );
HS65_LH_AOI22X1 U9023 ( .A(n2849), .B(n4588), .C(n4587), .D(\lte_x_59/B[18] ), .Z(n3663) );
HS65_LH_AOI21X2 U9024 ( .A(n5618), .B(n5228), .C(n3668), .Z(n3677) );
HS65_LL_NOR3X1 U9025 ( .A(n3681), .B(n3680), .C(n3679), .Z(n3695) );
HS65_LLS_XNOR2X3 U9026 ( .A(n3692), .B(n3691), .Z(n3693) );
HS65_LLS_XNOR2X3 U9027 ( .A(n3708), .B(n3707), .Z(n3746) );
HS65_LH_OAI21X3 U9028 ( .A(n5240), .B(n4855), .C(n3714), .Z(n3715) );
HS65_LH_CNIVX3 U9029 ( .A(n5608), .Z(n3734) );
HS65_LLS_XNOR2X3 U9030 ( .A(n3755), .B(n3754), .Z(n3813) );
HS65_LH_MUXI21X2 U9031 ( .D0(n4726), .D1(n2840), .S0(n3756), .Z(n4491) );
HS65_LHS_XNOR2X3 U9032 ( .A(n2853), .B(n5567), .Z(n4751) );
HS65_LH_OAI21X3 U9033 ( .A(n4986), .B(n3756), .C(n3768), .Z(n3769) );
HS65_LH_NAND3X2 U9034 ( .A(n3582), .B(n2853), .C(n5567), .Z(n3776) );
HS65_LH_NAND2X2 U9035 ( .A(n5647), .B(n2853), .Z(n3775) );
HS65_LH_AND2X4 U9036 ( .A(\lte_x_59/B[7] ), .B(n3789), .Z(n4465) );
HS65_LH_NAND2X2 U9037 ( .A(n5207), .B(n5660), .Z(n3791) );
HS65_LH_CBI4I1X3 U9038 ( .A(n3582), .B(n5048), .C(n5647), .D(n3521), .Z(
n3825) );
HS65_LH_NAND2X7 U9039 ( .A(n4836), .B(n4550), .Z(n5201) );
HS65_LHS_XNOR2X6 U9041 ( .A(n3848), .B(n3847), .Z(n3849) );
HS65_LH_CNIVX3 U9042 ( .A(n5143), .Z(n3874) );
HS65_LH_NAND3X2 U9043 ( .A(n4512), .B(n3426), .C(n3872), .Z(n3873) );
HS65_LH_NAND3X2 U9044 ( .A(n4949), .B(n3426), .C(n4176), .Z(n3922) );
HS65_LH_CNIVX3 U9045 ( .A(n4754), .Z(n3975) );
HS65_LH_NAND3X2 U9046 ( .A(n4192), .B(n5032), .C(n3969), .Z(n3972) );
HS65_LH_NAND2X2 U9047 ( .A(n9352), .B(n5104), .Z(n3971) );
HS65_LH_IVX9 U9048 ( .A(n4287), .Z(n7729) );
HS65_LH_AND2X4 U9049 ( .A(n4041), .B(n4037), .Z(n4043) );
HS65_LHS_XNOR2X3 U9050 ( .A(n4674), .B(n2842), .Z(n4740) );
HS65_LH_AOI22X1 U9051 ( .A(n4516), .B(n5239), .C(n4508), .D(n4614), .Z(n4179) );
HS65_LH_NAND2X2 U9052 ( .A(n3426), .B(n4176), .Z(n4178) );
HS65_LH_AOI22X1 U9053 ( .A(\sub_x_53/A[30] ), .B(n4587), .C(n4351), .D(
\sub_x_53/A[29] ), .Z(n4182) );
HS65_LH_CNIVX3 U9054 ( .A(n4738), .Z(n4199) );
HS65_LLS_XNOR2X3 U9055 ( .A(n5005), .B(\lte_x_59/B[18] ), .Z(n4744) );
HS65_LH_CBI4I1X3 U9056 ( .A(n5648), .B(n5005), .C(n5647), .D(
\lte_x_59/B[18] ), .Z(n4270) );
HS65_LL_AOI22X1 U9057 ( .A(n8868), .B(n9038), .C(n9366), .D(n8972), .Z(n7843) );
HS65_LLS_XNOR2X3 U9058 ( .A(n4339), .B(n4338), .Z(n4367) );
HS65_LH_NAND2X2 U9059 ( .A(n4340), .B(n4341), .Z(n4343) );
HS65_LH_OAI22X1 U9060 ( .A(n2854), .B(n4795), .C(n2857), .D(n4724), .Z(n4350) );
HS65_LHS_XNOR2X3 U9061 ( .A(\lte_x_59/B[21] ), .B(n5418), .Z(n4737) );
HS65_LH_NAND2X2 U9062 ( .A(n5207), .B(n4872), .Z(n4392) );
HS65_LH_CBI4I1X3 U9063 ( .A(n5648), .B(n5418), .C(n5647), .D(
\lte_x_59/B[21] ), .Z(n4396) );
HS65_LL_NAND3X2 U9064 ( .A(n4400), .B(n4399), .C(n4398), .Z(n4401) );
HS65_LHS_XNOR2X3 U9065 ( .A(\lte_x_59/B[4] ), .B(n5032), .Z(n4749) );
HS65_LH_CBI4I1X3 U9066 ( .A(n5648), .B(n2872), .C(n3443), .D(\lte_x_59/B[4] ), .Z(n4459) );
HS65_LH_NOR2X2 U9067 ( .A(n4513), .B(n4838), .Z(n4514) );
HS65_LH_OAI22X1 U9068 ( .A(n4725), .B(n4583), .C(n5129), .D(n4724), .Z(n4523) );
HS65_LHS_XNOR2X6 U9069 ( .A(\sub_x_53/A[30] ), .B(n4966), .Z(n4767) );
HS65_LH_NOR2AX3 U9070 ( .A(n4535), .B(n5152), .Z(n6121) );
HS65_LH_NAND2X2 U9071 ( .A(n4551), .B(n4550), .Z(n4580) );
HS65_LH_NAND2X2 U9072 ( .A(n5217), .B(n4563), .Z(n4564) );
HS65_LLS_XNOR2X3 U9073 ( .A(n4577), .B(n4576), .Z(n4605) );
HS65_LH_CBI4I1X3 U9074 ( .A(n5648), .B(n5321), .C(n4804), .D(\lte_x_59/B[3] ), .Z(n4586) );
HS65_LH_OAI222X2 U9075 ( .A(n4796), .B(n4583), .C(n2848), .D(n4582), .E(
n2893), .F(n5041), .Z(n4584) );
HS65_LHS_XNOR2X3 U9076 ( .A(\lte_x_59/B[3] ), .B(n5321), .Z(n4763) );
HS65_LH_AOI22X1 U9077 ( .A(\lte_x_59/B[7] ), .B(n4588), .C(n4587), .D(
\lte_x_59/B[8] ), .Z(n4589) );
HS65_LH_CBI4I1X3 U9078 ( .A(n3582), .B(n5030), .C(n5647), .D(\lte_x_59/B[7] ), .Z(n4612) );
HS65_LH_CNIVX3 U9079 ( .A(n4638), .Z(n4639) );
HS65_LH_NAND2X5 U9080 ( .A(n5032), .B(n4796), .Z(n5322) );
HS65_LH_CB4I1X9 U9081 ( .A(n4657), .B(n8495), .C(n4656), .D(n5041), .Z(n5388) );
HS65_LH_NAND2X7 U9083 ( .A(n4711), .B(n4976), .Z(n5564) );
HS65_LH_NAND2X7 U9084 ( .A(n4725), .B(n5422), .Z(n5286) );
HS65_LH_NAND4ABX3 U9085 ( .A(n5426), .B(n5571), .C(n5286), .D(n5289), .Z(
n4691) );
HS65_LH_NAND3X2 U9086 ( .A(n3384), .B(n2853), .C(n5564), .Z(n4723) );
HS65_LH_NOR3X1 U9087 ( .A(n4713), .B(n8833), .C(n4712), .Z(n4719) );
HS65_LH_OAI31X1 U9088 ( .A(n4717), .B(n8427), .C(n7868), .D(n4716), .Z(n4718) );
HS65_LHS_XNOR2X3 U9089 ( .A(\lte_x_59/B[9] ), .B(n5053), .Z(n4870) );
HS65_LHS_XNOR2X3 U9090 ( .A(n5061), .B(\lte_x_59/B[14] ), .Z(n4945) );
HS65_LHS_XNOR2X3 U9091 ( .A(\lte_x_59/B[24] ), .B(n5180), .Z(n5188) );
HS65_LH_NOR3X4 U9092 ( .A(n4815), .B(n4814), .C(n4813), .Z(n4831) );
HS65_LH_NAND3X2 U9093 ( .A(n5021), .B(n3582), .C(\lte_x_59/B[16] ), .Z(n4851) );
HS65_LH_OAI21X3 U9094 ( .A(n4855), .B(n5204), .C(n4854), .Z(n4859) );
HS65_LH_OAI21X3 U9095 ( .A(n4857), .B(n5656), .C(n4856), .Z(n4858) );
HS65_LLS_XOR2X6 U9096 ( .A(n4864), .B(n5633), .Z(n4865) );
HS65_LH_NAND2X7 U9097 ( .A(n7631), .B(n4865), .Z(n4866) );
HS65_LH_OAI21X3 U9098 ( .A(n4870), .B(n5656), .C(n4869), .Z(n4871) );
HS65_LH_CBI4I1X3 U9099 ( .A(n5648), .B(n5053), .C(n5647), .D(\lte_x_59/B[9] ), .Z(n4890) );
HS65_LH_CBI4I1X3 U9100 ( .A(n5648), .B(n5061), .C(n3443), .D(
\lte_x_59/B[14] ), .Z(n4940) );
HS65_LH_NAND2X2 U9101 ( .A(\lte_x_59/B[24] ), .B(n3382), .Z(n5442) );
HS65_LH_CBI4I1X3 U9102 ( .A(n5009), .B(n5586), .C(n5585), .D(n5115), .Z(
n4978) );
HS65_LH_NOR3AX2 U9103 ( .A(n5022), .B(n5023), .C(n4985), .Z(n4987) );
HS65_LH_NOR2X3 U9104 ( .A(n5041), .B(n5040), .Z(n5042) );
HS65_LH_NOR2X2 U9105 ( .A(n4796), .B(n5032), .Z(n5033) );
HS65_LH_NOR2X2 U9106 ( .A(n5088), .B(n5130), .Z(n5036) );
HS65_LH_OAI21X3 U9107 ( .A(n5322), .B(n5042), .C(n5328), .Z(n5098) );
HS65_LH_AND2X4 U9109 ( .A(n5126), .B(n5125), .Z(n5155) );
HS65_LH_CBI4I1X3 U9110 ( .A(n5648), .B(n5136), .C(n3443), .D(\sub_x_53/A[0] ), .Z(n5137) );
HS65_LH_NAND2X7 U9111 ( .A(n5168), .B(n5167), .Z(n5695) );
HS65_LHS_XOR2X3 U9112 ( .A(n5696), .B(n5695), .Z(n5169) );
HS65_LH_CBI4I1X3 U9113 ( .A(n5648), .B(n5180), .C(n5647), .D(
\lte_x_59/B[24] ), .Z(n5181) );
HS65_LH_NAND3X3 U9116 ( .A(n5292), .B(n5362), .C(n5291), .Z(n5354) );
HS65_LH_NOR2X2 U9118 ( .A(n5321), .B(n5320), .Z(n5323) );
HS65_LH_AOI21X2 U9119 ( .A(n5433), .B(n5432), .C(n5431), .Z(n5440) );
HS65_LH_NAND2X2 U9120 ( .A(\lte_x_59/B[21] ), .B(n3377), .Z(n5434) );
HS65_LH_NAND2X2 U9121 ( .A(\lte_x_59/B[22] ), .B(n2869), .Z(n5435) );
HS65_LH_AOI21X2 U9122 ( .A(n5438), .B(n5437), .C(n5436), .Z(n5439) );
HS65_LL_AOI12X2 U9123 ( .A(n5495), .B(n5494), .C(n5493), .Z(n5496) );
HS65_LH_NAND3X5 U9124 ( .A(n5574), .B(n5582), .C(n5562), .Z(n5527) );
HS65_LH_NAND4ABX3 U9125 ( .A(n5512), .B(n5511), .C(n5529), .D(n5536), .Z(
n5513) );
HS65_LL_NAND4ABX3 U9126 ( .A(n5558), .B(n5557), .C(n5556), .D(n5555), .Z(
n5560) );
HS65_LH_OAI21X3 U9127 ( .A(n5578), .B(n5577), .C(n5576), .Z(n5579) );
HS65_LHS_XNOR2X3 U9128 ( .A(\lte_x_59/B[22] ), .B(n5654), .Z(n5655) );
HS65_LHS_XNOR2X3 U9129 ( .A(n5697), .B(n7118), .Z(n5698) );
HS65_LL_AOI22X1 U9130 ( .A(n8868), .B(n9032), .C(n9369), .D(n9047), .Z(n7858) );
HS65_LH_AND2X4 U9131 ( .A(n5850), .B(n5717), .Z(\u_DataPath/toPC2_i [0]) );
HS65_LH_CNIVX3 U9132 ( .A(n5748), .Z(n5749) );
HS65_LH_CNIVX3 U9133 ( .A(n5767), .Z(n5768) );
HS65_LH_CNIVX3 U9134 ( .A(n5817), .Z(n5818) );
HS65_LH_AOI21X2 U9136 ( .A(n5890), .B(n5892), .C(n6042), .Z(n5841) );
HS65_LHS_XOR2X3 U9137 ( .A(n5850), .B(n5849), .Z(\u_DataPath/toPC2_i [1]) );
HS65_LH_OR2X4 U9138 ( .A(n9341), .B(n9202), .Z(n5851) );
HS65_LLS_XNOR2X3 U9139 ( .A(n5857), .B(n5856), .Z(\u_DataPath/toPC2_i [31])
);
HS65_LHS_XNOR2X3 U9140 ( .A(n5905), .B(n5904), .Z(\u_DataPath/toPC2_i [21])
);
HS65_LH_AND2X4 U9141 ( .A(n6049), .B(n5918), .Z(
\u_DataPath/u_execute/resAdd1_i [0]) );
HS65_LH_CNIVX3 U9145 ( .A(n5971), .Z(n5972) );
HS65_LH_CNIVX3 U9146 ( .A(n5995), .Z(n5996) );
HS65_LH_CNIVX3 U9147 ( .A(n5998), .Z(n6002) );
HS65_LH_CNIVX3 U9148 ( .A(n6026), .Z(n6027) );
HS65_LH_AOI21X2 U9149 ( .A(n5890), .B(n6095), .C(n6042), .Z(n6043) );
HS65_LHS_XOR2X3 U9150 ( .A(n6049), .B(n6048), .Z(
\u_DataPath/u_execute/resAdd1_i [1]) );
HS65_LH_NAND2X2 U9152 ( .A(n6099), .B(n6098), .Z(n6104) );
HS65_LHS_XNOR2X3 U9153 ( .A(n6108), .B(n6107), .Z(
\u_DataPath/u_execute/resAdd1_i [24]) );
HS65_LHS_XNOR2X3 U9154 ( .A(n6112), .B(n6111), .Z(
\u_DataPath/u_execute/resAdd1_i [22]) );
HS65_LH_AOI22X1 U9155 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][30] ), .B(n6617),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[14][30] ), .D(
n6362), .Z(n6130) );
HS65_LH_BFX9 U9156 ( .A(n6162), .Z(n7265) );
HS65_LH_NOR2X6 U9157 ( .A(n6150), .B(n6151), .Z(n6363) );
HS65_LH_NOR4ABX2 U9158 ( .A(n6130), .B(n6129), .C(n6128), .D(n6127), .Z(
n6161) );
HS65_LH_BFX9 U9159 ( .A(n6370), .Z(n7165) );
HS65_LH_BFX9 U9160 ( .A(n6371), .Z(n7273) );
HS65_LH_NOR2X13 U9161 ( .A(n6150), .B(n6133), .Z(n6628) );
HS65_LH_NOR4ABX2 U9162 ( .A(n6137), .B(n6136), .C(n6135), .D(n6134), .Z(
n6160) );
HS65_LH_NOR2X6 U9163 ( .A(n6148), .B(n6139), .Z(n6377) );
HS65_LH_NAND4ABX3 U9164 ( .A(n6144), .B(n6143), .C(n6142), .D(n6141), .Z(
n6159) );
HS65_LH_BFX9 U9165 ( .A(n6383), .Z(n7292) );
HS65_LH_NOR2X6 U9166 ( .A(n6150), .B(n6152), .Z(n7295) );
HS65_LH_NOR2X6 U9167 ( .A(n6153), .B(n6151), .Z(n6385) );
HS65_LH_NAND4ABX3 U9168 ( .A(n6157), .B(n6156), .C(n6155), .D(n6154), .Z(
n6158) );
HS65_LH_AOI22X1 U9169 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][16] ), .B(n6617),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[14][16] ), .D(
n6362), .Z(n6166) );
HS65_LH_AO22X9 U9170 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][16] ), .B(n6364),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][16] ), .D(
n9371), .Z(n6164) );
HS65_LH_NOR4ABX2 U9171 ( .A(n6166), .B(n6165), .C(n6164), .D(n6163), .Z(
n6184) );
HS65_LH_NOR4ABX2 U9172 ( .A(n6170), .B(n6169), .C(n6168), .D(n6167), .Z(
n6183) );
HS65_LH_NAND4ABX3 U9173 ( .A(n6176), .B(n6175), .C(n6174), .D(n6173), .Z(
n6182) );
HS65_LH_AO22X9 U9174 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][16] ), .B(n6317),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[13][16] ), .D(
n7292), .Z(n6179) );
HS65_LH_AOI22X1 U9175 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][16] ), .B(n7295),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[7][16] ), .D(
n6384), .Z(n6178) );
HS65_LH_NAND4ABX3 U9176 ( .A(n6180), .B(n6179), .C(n6178), .D(n6177), .Z(
n6181) );
HS65_LH_NOR4ABX2 U9177 ( .A(n6188), .B(n6187), .C(n6186), .D(n6185), .Z(
n6204) );
HS65_LH_NOR4ABX2 U9178 ( .A(n6192), .B(n6191), .C(n6190), .D(n6189), .Z(
n6203) );
HS65_LH_NAND4ABX3 U9179 ( .A(n6196), .B(n6195), .C(n6194), .D(n6193), .Z(
n6202) );
HS65_LH_AOI22X1 U9180 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][21] ), .B(n7295),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[7][21] ), .D(
n6384), .Z(n6198) );
HS65_LH_NAND4ABX3 U9181 ( .A(n6200), .B(n6199), .C(n6198), .D(n6197), .Z(
n6201) );
HS65_LH_AO22X9 U9182 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][27] ), .B(n6364),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][27] ), .D(
n9371), .Z(n6206) );
HS65_LH_NOR4ABX2 U9183 ( .A(n6208), .B(n6207), .C(n6206), .D(n6205), .Z(
n6224) );
HS65_LH_NOR4ABX2 U9184 ( .A(n6212), .B(n6211), .C(n6210), .D(n6209), .Z(
n6223) );
HS65_LH_NAND4ABX3 U9185 ( .A(n6216), .B(n6215), .C(n6214), .D(n6213), .Z(
n6222) );
HS65_LH_AOI22X1 U9186 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][27] ), .B(n7295),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[7][27] ), .D(
n6384), .Z(n6218) );
HS65_LH_NAND4ABX3 U9187 ( .A(n6220), .B(n6219), .C(n6218), .D(n6217), .Z(
n6221) );
HS65_LH_AO22X9 U9188 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][23] ), .B(n6364),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][23] ), .D(
n9372), .Z(n6226) );
HS65_LH_NOR4ABX2 U9189 ( .A(n6228), .B(n6227), .C(n6226), .D(n6225), .Z(
n6244) );
HS65_LH_NOR4ABX2 U9190 ( .A(n6232), .B(n6231), .C(n6230), .D(n6229), .Z(
n6243) );
HS65_LH_NAND4ABX3 U9191 ( .A(n6236), .B(n6235), .C(n6234), .D(n6233), .Z(
n6242) );
HS65_LH_BFX9 U9192 ( .A(n6317), .Z(n7293) );
HS65_LH_AOI22X1 U9193 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][23] ), .B(n7295),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[7][23] ), .D(
n6384), .Z(n6238) );
HS65_LH_NAND4ABX3 U9194 ( .A(n6240), .B(n6239), .C(n6238), .D(n6237), .Z(
n6241) );
HS65_LH_AO22X9 U9195 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][11] ), .B(n6364),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][11] ), .D(
n9372), .Z(n6246) );
HS65_LH_NOR4ABX2 U9196 ( .A(n6248), .B(n6247), .C(n6246), .D(n6245), .Z(
n6264) );
HS65_LH_NOR4ABX2 U9197 ( .A(n6252), .B(n6251), .C(n6250), .D(n6249), .Z(
n6263) );
HS65_LH_NAND4ABX3 U9198 ( .A(n6256), .B(n6255), .C(n6254), .D(n6253), .Z(
n6262) );
HS65_LH_AOI22X1 U9199 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][11] ), .B(n7295),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[7][11] ), .D(
n6384), .Z(n6258) );
HS65_LH_NAND4ABX3 U9200 ( .A(n6260), .B(n6259), .C(n6258), .D(n6257), .Z(
n6261) );
HS65_LH_AOI22X1 U9201 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][22] ), .B(n6617),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[14][22] ), .D(
n6362), .Z(n6268) );
HS65_LH_NOR4ABX2 U9202 ( .A(n6268), .B(n6267), .C(n6266), .D(n6265), .Z(
n6284) );
HS65_LH_NOR4ABX2 U9203 ( .A(n6272), .B(n6271), .C(n6270), .D(n6269), .Z(
n6283) );
HS65_LH_NAND4ABX3 U9204 ( .A(n6276), .B(n6275), .C(n6274), .D(n6273), .Z(
n6282) );
HS65_LH_AOI22X1 U9205 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][22] ), .B(n7295),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[7][22] ), .D(
n6384), .Z(n6278) );
HS65_LH_NAND4ABX3 U9206 ( .A(n6280), .B(n6279), .C(n6278), .D(n6277), .Z(
n6281) );
HS65_LH_NOR4ABX2 U9207 ( .A(n6288), .B(n6287), .C(n6286), .D(n6285), .Z(
n6304) );
HS65_LH_NOR4ABX2 U9208 ( .A(n6292), .B(n6291), .C(n6290), .D(n6289), .Z(
n6303) );
HS65_LH_NAND4ABX3 U9209 ( .A(n6296), .B(n6295), .C(n6294), .D(n6293), .Z(
n6302) );
HS65_LH_AOI22X1 U9210 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][24] ), .B(n7295),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[7][24] ), .D(
n6384), .Z(n6298) );
HS65_LH_NAND4ABX3 U9211 ( .A(n6300), .B(n6299), .C(n6298), .D(n6297), .Z(
n6301) );
HS65_LH_NOR4ABX2 U9212 ( .A(n6308), .B(n6307), .C(n6306), .D(n6305), .Z(
n6325) );
HS65_LH_NOR4ABX2 U9213 ( .A(n6312), .B(n6311), .C(n6310), .D(n6309), .Z(
n6324) );
HS65_LH_NAND4ABX3 U9214 ( .A(n6316), .B(n6315), .C(n6314), .D(n6313), .Z(
n6323) );
HS65_LH_AOI22X1 U9215 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][14] ), .B(n7295),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[7][14] ), .D(
n6384), .Z(n6319) );
HS65_LH_NAND4ABX3 U9216 ( .A(n6321), .B(n6320), .C(n6319), .D(n6318), .Z(
n6322) );
HS65_LH_NAND3X5 U9217 ( .A(\u_DataPath/jaddr_i [19]), .B(
\u_DataPath/jaddr_i [18]), .C(n2881), .Z(n6334) );
HS65_LH_NOR2X6 U9218 ( .A(\u_DataPath/jaddr_i [19]), .B(n8184), .Z(n6340) );
HS65_LH_NOR4ABX2 U9220 ( .A(n6330), .B(n6329), .C(n6328), .D(n6327), .Z(
n6361) );
HS65_LH_NOR2X6 U9221 ( .A(n6353), .B(n6332), .Z(n6957) );
HS65_LH_AOI22X1 U9222 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][18] ), .B(n7317),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[1][18] ), .D(
n6957), .Z(n6337) );
HS65_LH_BFX9 U9223 ( .A(n6747), .Z(n7517) );
HS65_LH_NOR2X6 U9224 ( .A(n6350), .B(n6333), .Z(n6675) );
HS65_LH_NOR2X6 U9225 ( .A(n6350), .B(n6334), .Z(n7319) );
HS65_LH_NOR4ABX2 U9226 ( .A(n6338), .B(n6337), .C(n6336), .D(n6335), .Z(
n6360) );
HS65_LH_NAND2X7 U9227 ( .A(\u_DataPath/jaddr_i [20]), .B(n6340), .Z(n6342)
);
HS65_LH_AO22X9 U9228 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][18] ), .B(n7522),
.C(n6752), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][18] ), .Z(n6346)
);
HS65_LH_NOR2X6 U9230 ( .A(n6353), .B(n6342), .Z(n6753) );
HS65_LH_NOR2X6 U9231 ( .A(n6349), .B(n6342), .Z(n6684) );
HS65_LH_NAND4ABX3 U9232 ( .A(n6346), .B(n6345), .C(n6344), .D(n6343), .Z(
n6359) );
HS65_LH_NAND2X7 U9233 ( .A(n8184), .B(n6347), .Z(n6351) );
HS65_LH_NOR2X6 U9234 ( .A(n6348), .B(n6351), .Z(n7330) );
HS65_LH_NOR2X6 U9235 ( .A(n6349), .B(n6351), .Z(n7329) );
HS65_LH_NAND2X7 U9236 ( .A(\u_DataPath/jaddr_i [18]), .B(n6347), .Z(n6352)
);
HS65_LH_NOR2X6 U9237 ( .A(n6348), .B(n6352), .Z(n7332) );
HS65_LH_NOR2X6 U9238 ( .A(n6350), .B(n6351), .Z(n7331) );
HS65_LH_NOR2X6 U9239 ( .A(n6353), .B(n6351), .Z(n6690) );
HS65_LH_NAND4ABX3 U9240 ( .A(n6357), .B(n6356), .C(n6355), .D(n6354), .Z(
n6358) );
HS65_LH_BFX9 U9241 ( .A(n6617), .Z(n6595) );
HS65_LH_BFX9 U9242 ( .A(n6362), .Z(n7264) );
HS65_LH_AO22X9 U9243 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][15] ), .B(n6927),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][15] ), .D(
n7266), .Z(n6367) );
HS65_LH_AO22X9 U9244 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][15] ), .B(n9375),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[6][15] ), .D(
n7267), .Z(n6366) );
HS65_LH_NOR4ABX2 U9245 ( .A(n6369), .B(n6368), .C(n6367), .D(n6366), .Z(
n6393) );
HS65_LH_AO22X9 U9247 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][15] ), .B(n7275),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[30][15] ), .D(
n7274), .Z(n6373) );
HS65_LH_NOR4ABX2 U9248 ( .A(n6375), .B(n6374), .C(n6373), .D(n6372), .Z(
n6392) );
HS65_LH_NAND4ABX3 U9249 ( .A(n6381), .B(n6380), .C(n6379), .D(n6378), .Z(
n6391) );
HS65_LH_AO22X9 U9250 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][15] ), .B(n2884),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][15] ), .D(
n7291), .Z(n6389) );
HS65_LH_BFX9 U9251 ( .A(n6384), .Z(n7294) );
HS65_LH_NAND4ABX3 U9252 ( .A(n6389), .B(n6388), .C(n6387), .D(n6386), .Z(
n6390) );
HS65_LH_AO22X9 U9253 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][10] ), .B(n6927),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][10] ), .D(
n7266), .Z(n6395) );
HS65_LH_AO22X9 U9254 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][10] ), .B(n9374),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[6][10] ), .D(
n7267), .Z(n6394) );
HS65_LH_NOR4ABX2 U9255 ( .A(n6397), .B(n6396), .C(n6395), .D(n6394), .Z(
n6413) );
HS65_LH_AO22X9 U9256 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][10] ), .B(n7275),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[30][10] ), .D(
n7274), .Z(n6399) );
HS65_LH_NOR4ABX2 U9257 ( .A(n6401), .B(n6400), .C(n6399), .D(n6398), .Z(
n6412) );
HS65_LH_NAND4ABX3 U9258 ( .A(n6405), .B(n6404), .C(n6403), .D(n6402), .Z(
n6411) );
HS65_LH_NAND4ABX3 U9260 ( .A(n6409), .B(n6408), .C(n6407), .D(n6406), .Z(
n6410) );
HS65_LH_AO22X9 U9261 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][0] ), .B(n6927),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][0] ), .D(n7266), .Z(n6415) );
HS65_LH_AO22X9 U9262 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][0] ), .B(n9375),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[6][0] ), .D(n7267), .Z(n6414) );
HS65_LH_NOR4ABX2 U9263 ( .A(n6417), .B(n6416), .C(n6415), .D(n6414), .Z(
n6434) );
HS65_LH_AOI22X1 U9264 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][0] ), .B(n6370),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[28][0] ), .D(
n6600), .Z(n6421) );
HS65_LH_AO22X9 U9265 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][0] ), .B(n7275),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[30][0] ), .D(
n7274), .Z(n6419) );
HS65_LH_NOR4ABX2 U9266 ( .A(n6421), .B(n6420), .C(n6419), .D(n6418), .Z(
n6433) );
HS65_LH_NAND4ABX3 U9267 ( .A(n6425), .B(n6424), .C(n6423), .D(n6422), .Z(
n6432) );
HS65_LH_AOI22X3 U9269 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][0] ), .B(n6941),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[7][0] ), .D(n7294), .Z(n6428) );
HS65_LH_NAND4ABX3 U9270 ( .A(n6430), .B(n6429), .C(n6428), .D(n6427), .Z(
n6431) );
HS65_LH_AO22X9 U9271 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][7] ), .B(n6927),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][7] ), .D(n7266), .Z(n6436) );
HS65_LH_NOR4ABX2 U9273 ( .A(n6438), .B(n6437), .C(n6436), .D(n6435), .Z(
n6454) );
HS65_LH_AO22X9 U9274 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][7] ), .B(n7275),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[30][7] ), .D(
n7274), .Z(n6440) );
HS65_LH_NOR4ABX2 U9275 ( .A(n6442), .B(n6441), .C(n6440), .D(n6439), .Z(
n6453) );
HS65_LH_NAND4ABX3 U9276 ( .A(n6446), .B(n6445), .C(n6444), .D(n6443), .Z(
n6452) );
HS65_LH_AOI22X3 U9278 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][7] ), .B(n6941),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[7][7] ), .D(n7294), .Z(n6448) );
HS65_LH_NAND4ABX3 U9279 ( .A(n6450), .B(n6449), .C(n6448), .D(n6447), .Z(
n6451) );
HS65_LH_AO22X9 U9280 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][8] ), .B(n6927),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][8] ), .D(n7266), .Z(n6456) );
HS65_LH_NOR4ABX2 U9282 ( .A(n6458), .B(n6457), .C(n6456), .D(n6455), .Z(
n6474) );
HS65_LH_AOI22X1 U9283 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][8] ), .B(n6370),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[28][8] ), .D(
n6600), .Z(n6462) );
HS65_LH_AO22X9 U9284 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][8] ), .B(n7275),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[30][8] ), .D(
n7274), .Z(n6460) );
HS65_LH_NOR4ABX2 U9285 ( .A(n6462), .B(n6461), .C(n6460), .D(n6459), .Z(
n6473) );
HS65_LH_NAND4ABX3 U9286 ( .A(n6466), .B(n6465), .C(n6464), .D(n6463), .Z(
n6472) );
HS65_LH_AO22X9 U9287 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][8] ), .B(n6426),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][8] ), .D(n7291), .Z(n6470) );
HS65_LH_AOI22X3 U9288 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][8] ), .B(n6941),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[7][8] ), .D(n7294), .Z(n6468) );
HS65_LH_NAND4ABX3 U9289 ( .A(n6470), .B(n6469), .C(n6468), .D(n6467), .Z(
n6471) );
HS65_LH_NOR4ABX2 U9290 ( .A(n6478), .B(n6477), .C(n6476), .D(n6475), .Z(
n6494) );
HS65_LH_AOI22X1 U9291 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][6] ), .B(n6370),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[28][6] ), .D(
n6600), .Z(n6482) );
HS65_LH_NOR4ABX2 U9292 ( .A(n6482), .B(n6481), .C(n6480), .D(n6479), .Z(
n6493) );
HS65_LH_NAND4ABX3 U9293 ( .A(n6486), .B(n6485), .C(n6484), .D(n6483), .Z(
n6492) );
HS65_LH_NAND4ABX3 U9294 ( .A(n6490), .B(n6489), .C(n6488), .D(n6487), .Z(
n6491) );
HS65_LH_AO22X9 U9295 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][26] ), .B(n6927),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][26] ), .D(
n7266), .Z(n6496) );
HS65_LH_AO22X9 U9296 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][26] ), .B(n9375),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[6][26] ), .D(
n7267), .Z(n6495) );
HS65_LH_NOR4ABX2 U9297 ( .A(n6498), .B(n6497), .C(n6496), .D(n6495), .Z(
n6514) );
HS65_LH_AO22X9 U9298 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][26] ), .B(n7275),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[30][26] ), .D(
n7274), .Z(n6500) );
HS65_LH_NOR4ABX2 U9299 ( .A(n6502), .B(n6501), .C(n6500), .D(n6499), .Z(
n6513) );
HS65_LH_NAND4ABX3 U9300 ( .A(n6506), .B(n6505), .C(n6504), .D(n6503), .Z(
n6512) );
HS65_LH_AO22X9 U9301 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][26] ), .B(n2884),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][26] ), .D(
n7291), .Z(n6510) );
HS65_LH_AOI22X3 U9302 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][26] ), .B(n6941),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[7][26] ), .D(
n7294), .Z(n6508) );
HS65_LH_NAND4ABX3 U9303 ( .A(n6510), .B(n6509), .C(n6508), .D(n6507), .Z(
n6511) );
HS65_LH_AO22X9 U9304 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][19] ), .B(n6927),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][19] ), .D(
n7266), .Z(n6516) );
HS65_LH_NOR4ABX2 U9306 ( .A(n6518), .B(n6517), .C(n6516), .D(n6515), .Z(
n6534) );
HS65_LH_AO22X9 U9307 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][19] ), .B(n7275),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[30][19] ), .D(
n7274), .Z(n6520) );
HS65_LH_NOR4ABX2 U9308 ( .A(n6522), .B(n6521), .C(n6520), .D(n6519), .Z(
n6533) );
HS65_LH_NAND4ABX3 U9309 ( .A(n6526), .B(n6525), .C(n6524), .D(n6523), .Z(
n6532) );
HS65_LH_AO22X9 U9310 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][19] ), .B(n6426),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][19] ), .D(
n7291), .Z(n6530) );
HS65_LH_AOI22X3 U9311 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][19] ), .B(n6941),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[7][19] ), .D(
n7294), .Z(n6528) );
HS65_LH_NAND4ABX3 U9312 ( .A(n6530), .B(n6529), .C(n6528), .D(n6527), .Z(
n6531) );
HS65_LH_AO22X9 U9313 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][12] ), .B(n6927),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][12] ), .D(
n7266), .Z(n6536) );
HS65_LH_NOR4ABX2 U9315 ( .A(n6538), .B(n6537), .C(n6536), .D(n6535), .Z(
n6554) );
HS65_LH_AO22X9 U9316 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][12] ), .B(n7275),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[30][12] ), .D(
n7274), .Z(n6540) );
HS65_LH_NOR4ABX2 U9317 ( .A(n6542), .B(n6541), .C(n6540), .D(n6539), .Z(
n6553) );
HS65_LH_NAND4ABX3 U9318 ( .A(n6546), .B(n6545), .C(n6544), .D(n6543), .Z(
n6552) );
HS65_LH_AOI22X3 U9320 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][12] ), .B(n6941),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[7][12] ), .D(
n7294), .Z(n6548) );
HS65_LH_NAND4ABX3 U9321 ( .A(n6550), .B(n6549), .C(n6548), .D(n6547), .Z(
n6551) );
HS65_LH_AO22X9 U9322 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][2] ), .B(n6927),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][2] ), .D(n9371), .Z(n6556) );
HS65_LH_NOR4ABX2 U9324 ( .A(n6558), .B(n6557), .C(n6556), .D(n6555), .Z(
n6574) );
HS65_LH_AOI22X1 U9325 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][2] ), .B(n6370),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[28][2] ), .D(
n6600), .Z(n6562) );
HS65_LH_AO22X9 U9326 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][2] ), .B(n7275),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[30][2] ), .D(
n6627), .Z(n6560) );
HS65_LH_AO22X9 U9327 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][2] ), .B(n7277),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[25][2] ), .D(
n6629), .Z(n6559) );
HS65_LH_NOR4ABX2 U9328 ( .A(n6562), .B(n6561), .C(n6560), .D(n6559), .Z(
n6573) );
HS65_LH_NAND4ABX3 U9329 ( .A(n6566), .B(n6565), .C(n6564), .D(n6563), .Z(
n6572) );
HS65_LH_AO22X9 U9330 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][2] ), .B(n6426),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][2] ), .D(n7291), .Z(n6570) );
HS65_LH_AOI22X3 U9331 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][2] ), .B(n6941),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[7][2] ), .D(n7294), .Z(n6568) );
HS65_LH_NAND4ABX3 U9332 ( .A(n6570), .B(n6569), .C(n6568), .D(n6567), .Z(
n6571) );
HS65_LH_AO22X9 U9333 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][3] ), .B(n6927),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][3] ), .D(n7266), .Z(n6576) );
HS65_LH_AO22X9 U9334 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][3] ), .B(n9374),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[6][3] ), .D(n7267), .Z(n6575) );
HS65_LH_NOR4ABX2 U9335 ( .A(n6578), .B(n6577), .C(n6576), .D(n6575), .Z(
n6594) );
HS65_LH_NOR4ABX2 U9336 ( .A(n6582), .B(n6581), .C(n6580), .D(n6579), .Z(
n6593) );
HS65_LH_NAND4ABX3 U9337 ( .A(n6586), .B(n6585), .C(n6584), .D(n6583), .Z(
n6592) );
HS65_LH_AO22X9 U9338 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][3] ), .B(n6426),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][3] ), .D(n7291), .Z(n6590) );
HS65_LH_AOI22X3 U9339 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][3] ), .B(n6941),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[7][3] ), .D(n7294), .Z(n6588) );
HS65_LH_NAND4ABX3 U9340 ( .A(n6590), .B(n6589), .C(n6588), .D(n6587), .Z(
n6591) );
HS65_LH_AO22X9 U9341 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][1] ), .B(n9374),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[6][1] ), .D(n6619), .Z(n6596) );
HS65_LH_NOR4ABX2 U9342 ( .A(n6599), .B(n6598), .C(n6597), .D(n6596), .Z(
n6616) );
HS65_LH_AO22X9 U9343 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][1] ), .B(n7277),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[25][1] ), .D(
n6629), .Z(n6601) );
HS65_LH_NOR4ABX2 U9344 ( .A(n6604), .B(n6603), .C(n6602), .D(n6601), .Z(
n6615) );
HS65_LH_NAND4ABX3 U9345 ( .A(n6608), .B(n6607), .C(n6606), .D(n6605), .Z(
n6614) );
HS65_LH_AO22X9 U9346 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][1] ), .B(n6426),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][1] ), .D(n7291), .Z(n6612) );
HS65_LH_AOI22X3 U9347 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][1] ), .B(n6941),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[7][1] ), .D(n7294), .Z(n6610) );
HS65_LH_NAND4ABX3 U9348 ( .A(n6612), .B(n6611), .C(n6610), .D(n6609), .Z(
n6613) );
HS65_LH_BFX9 U9349 ( .A(n9370), .Z(n7266) );
HS65_LH_AO22X9 U9350 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][4] ), .B(n6927),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][4] ), .D(n7266), .Z(n6621) );
HS65_LH_BFX9 U9351 ( .A(n6619), .Z(n7267) );
HS65_LH_NOR4ABX2 U9353 ( .A(n6623), .B(n6622), .C(n6621), .D(n6620), .Z(
n6649) );
HS65_LH_BFX9 U9354 ( .A(n6626), .Z(n7275) );
HS65_LH_AO22X9 U9355 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][4] ), .B(n7275),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[30][4] ), .D(
n7274), .Z(n6631) );
HS65_LH_BFX9 U9356 ( .A(n6628), .Z(n7277) );
HS65_LH_BFX9 U9357 ( .A(n6629), .Z(n7276) );
HS65_LH_AO22X9 U9358 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][4] ), .B(n7277),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[25][4] ), .D(
n7276), .Z(n6630) );
HS65_LH_NOR4ABX2 U9359 ( .A(n6633), .B(n6632), .C(n6631), .D(n6630), .Z(
n6648) );
HS65_LH_NAND4ABX3 U9360 ( .A(n6641), .B(n6640), .C(n6639), .D(n6638), .Z(
n6647) );
HS65_LH_NAND4ABX3 U9362 ( .A(n6645), .B(n6644), .C(n6643), .D(n6642), .Z(
n6646) );
HS65_LH_AO22X9 U9363 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][18] ), .B(n6927),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][18] ), .D(
n7266), .Z(n6651) );
HS65_LH_AO22X9 U9364 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][18] ), .B(n9374),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[6][18] ), .D(
n7267), .Z(n6650) );
HS65_LH_NOR4ABX2 U9365 ( .A(n6653), .B(n6652), .C(n6651), .D(n6650), .Z(
n6669) );
HS65_LH_AO22X9 U9367 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][18] ), .B(n7277),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[25][18] ), .D(
n7276), .Z(n6654) );
HS65_LH_NOR4ABX2 U9368 ( .A(n6657), .B(n6656), .C(n6655), .D(n6654), .Z(
n6668) );
HS65_LH_NAND4ABX3 U9369 ( .A(n6661), .B(n6660), .C(n6659), .D(n6658), .Z(
n6667) );
HS65_LH_AOI22X3 U9370 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][18] ), .B(n6941),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[7][18] ), .D(
n7294), .Z(n6663) );
HS65_LH_NAND4ABX3 U9371 ( .A(n6665), .B(n6664), .C(n6663), .D(n6662), .Z(
n6666) );
HS65_LH_NOR4ABX2 U9372 ( .A(n6674), .B(n6673), .C(n6672), .D(n6671), .Z(
n6698) );
HS65_LH_NOR4ABX2 U9373 ( .A(n6679), .B(n6678), .C(n6677), .D(n6676), .Z(
n6697) );
HS65_LH_BFX9 U9374 ( .A(n6752), .Z(n7439) );
HS65_LH_NAND4ABX3 U9375 ( .A(n6688), .B(n6687), .C(n6686), .D(n6685), .Z(
n6696) );
HS65_LH_NAND4ABX3 U9376 ( .A(n6694), .B(n6693), .C(n6692), .D(n6691), .Z(
n6695) );
HS65_LH_NOR4ABX2 U9378 ( .A(n6702), .B(n6701), .C(n6700), .D(n6699), .Z(
n6718) );
HS65_LH_NOR4ABX2 U9379 ( .A(n6706), .B(n6705), .C(n6704), .D(n6703), .Z(
n6717) );
HS65_LH_NAND4ABX3 U9380 ( .A(n6710), .B(n6709), .C(n6708), .D(n6707), .Z(
n6716) );
HS65_LH_NAND4ABX3 U9381 ( .A(n6714), .B(n6713), .C(n6712), .D(n6711), .Z(
n6715) );
HS65_LH_NOR4ABX2 U9383 ( .A(n6722), .B(n6721), .C(n6720), .D(n6719), .Z(
n6738) );
HS65_LH_NOR4ABX2 U9384 ( .A(n6726), .B(n6725), .C(n6724), .D(n6723), .Z(
n6737) );
HS65_LH_NAND4ABX3 U9385 ( .A(n6730), .B(n6729), .C(n6728), .D(n6727), .Z(
n6736) );
HS65_LH_NAND4ABX3 U9386 ( .A(n6734), .B(n6733), .C(n6732), .D(n6731), .Z(
n6735) );
HS65_LH_NOR4ABX2 U9388 ( .A(n6744), .B(n6743), .C(n6742), .D(n6741), .Z(
n6766) );
HS65_LH_AOI22X1 U9389 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][19] ), .B(n7317),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[1][19] ), .D(
n6957), .Z(n6750) );
HS65_LH_NOR4ABX2 U9390 ( .A(n6751), .B(n6750), .C(n6749), .D(n6748), .Z(
n6765) );
HS65_LH_NAND4ABX3 U9391 ( .A(n6758), .B(n6757), .C(n6756), .D(n6755), .Z(
n6764) );
HS65_LH_NAND4ABX3 U9392 ( .A(n6762), .B(n6761), .C(n6760), .D(n6759), .Z(
n6763) );
HS65_LH_NOR4ABX2 U9393 ( .A(n6770), .B(n6769), .C(n6768), .D(n6767), .Z(
n6786) );
HS65_LH_NOR4ABX2 U9394 ( .A(n6774), .B(n6773), .C(n6772), .D(n6771), .Z(
n6785) );
HS65_LH_NAND4ABX3 U9395 ( .A(n6778), .B(n6777), .C(n6776), .D(n6775), .Z(
n6784) );
HS65_LH_NAND4ABX3 U9396 ( .A(n6782), .B(n6781), .C(n6780), .D(n6779), .Z(
n6783) );
HS65_LL_NOR4ABX2 U9397 ( .A(n6786), .B(n6785), .C(n6784), .D(n6783), .Z(
n8261) );
HS65_LH_NOR4ABX2 U9398 ( .A(n6790), .B(n6789), .C(n6788), .D(n6787), .Z(
n6806) );
HS65_LH_NOR4ABX2 U9399 ( .A(n6794), .B(n6793), .C(n6792), .D(n6791), .Z(
n6805) );
HS65_LH_NAND4ABX3 U9400 ( .A(n6798), .B(n6797), .C(n6796), .D(n6795), .Z(
n6804) );
HS65_LH_NAND4ABX3 U9401 ( .A(n6802), .B(n6801), .C(n6800), .D(n6799), .Z(
n6803) );
HS65_LH_NOR4ABX2 U9402 ( .A(n6810), .B(n6809), .C(n6808), .D(n6807), .Z(
n6826) );
HS65_LH_NOR4ABX2 U9403 ( .A(n6814), .B(n6813), .C(n6812), .D(n6811), .Z(
n6825) );
HS65_LH_NAND4ABX3 U9404 ( .A(n6818), .B(n6817), .C(n6816), .D(n6815), .Z(
n6824) );
HS65_LH_NAND4ABX3 U9405 ( .A(n6822), .B(n6821), .C(n6820), .D(n6819), .Z(
n6823) );
HS65_LH_NOR4ABX2 U9407 ( .A(n6830), .B(n6829), .C(n6828), .D(n6827), .Z(
n6846) );
HS65_LH_NOR4ABX2 U9408 ( .A(n6834), .B(n6833), .C(n6832), .D(n6831), .Z(
n6845) );
HS65_LH_NAND4ABX3 U9409 ( .A(n6838), .B(n6837), .C(n6836), .D(n6835), .Z(
n6844) );
HS65_LH_NAND4ABX3 U9410 ( .A(n6842), .B(n6841), .C(n6840), .D(n6839), .Z(
n6843) );
HS65_LH_AO22X9 U9412 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][20] ), .B(n9375),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[6][20] ), .D(
n7267), .Z(n6847) );
HS65_LH_NOR4ABX2 U9413 ( .A(n6850), .B(n6849), .C(n6848), .D(n6847), .Z(
n6866) );
HS65_LH_AO22X9 U9414 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][20] ), .B(n7275),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[30][20] ), .D(
n7274), .Z(n6852) );
HS65_LH_NOR4ABX2 U9416 ( .A(n6854), .B(n6853), .C(n6852), .D(n6851), .Z(
n6865) );
HS65_LH_NAND4ABX3 U9417 ( .A(n6858), .B(n6857), .C(n6856), .D(n6855), .Z(
n6864) );
HS65_LH_AO22X9 U9418 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][20] ), .B(n6426),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][20] ), .D(
n7291), .Z(n6862) );
HS65_LH_AOI22X3 U9419 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][20] ), .B(n6941),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[7][20] ), .D(
n7294), .Z(n6860) );
HS65_LH_NAND4ABX3 U9420 ( .A(n6862), .B(n6861), .C(n6860), .D(n6859), .Z(
n6863) );
HS65_LH_AO22X9 U9421 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][31] ), .B(n6364),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][31] ), .D(
n7266), .Z(n6868) );
HS65_LH_AO22X9 U9422 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][31] ), .B(n9375),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[6][31] ), .D(
n7267), .Z(n6867) );
HS65_LH_NOR4ABX2 U9423 ( .A(n6870), .B(n6869), .C(n6868), .D(n6867), .Z(
n6886) );
HS65_LH_AOI22X1 U9424 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][31] ), .B(n6370),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[28][31] ), .D(
n6600), .Z(n6874) );
HS65_LH_AO22X9 U9425 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][31] ), .B(n7275),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[30][31] ), .D(
n7274), .Z(n6872) );
HS65_LH_AO22X9 U9426 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][31] ), .B(n7277),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[25][31] ), .D(
n7276), .Z(n6871) );
HS65_LH_NOR4ABX2 U9427 ( .A(n6874), .B(n6873), .C(n6872), .D(n6871), .Z(
n6885) );
HS65_LH_NAND4ABX3 U9428 ( .A(n6878), .B(n6877), .C(n6876), .D(n6875), .Z(
n6884) );
HS65_LH_NAND4ABX3 U9429 ( .A(n6882), .B(n6881), .C(n6880), .D(n6879), .Z(
n6883) );
HS65_LH_AO22X9 U9430 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][17] ), .B(n6927),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][17] ), .D(
n7266), .Z(n6888) );
HS65_LH_NOR4ABX2 U9432 ( .A(n6890), .B(n6889), .C(n6888), .D(n6887), .Z(
n6906) );
HS65_LH_AOI22X1 U9433 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][17] ), .B(n6370),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[28][17] ), .D(
n6600), .Z(n6894) );
HS65_LH_AO22X9 U9434 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][17] ), .B(n7275),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[30][17] ), .D(
n7274), .Z(n6892) );
HS65_LH_AO22X9 U9435 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][17] ), .B(n7277),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[25][17] ), .D(
n7276), .Z(n6891) );
HS65_LH_NOR4ABX2 U9436 ( .A(n6894), .B(n6893), .C(n6892), .D(n6891), .Z(
n6905) );
HS65_LH_NAND4ABX3 U9437 ( .A(n6898), .B(n6897), .C(n6896), .D(n6895), .Z(
n6904) );
HS65_LH_NAND4ABX3 U9439 ( .A(n6902), .B(n6901), .C(n6900), .D(n6899), .Z(
n6903) );
HS65_LH_AO22X9 U9440 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][28] ), .B(n6927),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][28] ), .D(
n7266), .Z(n6908) );
HS65_LH_NOR4ABX2 U9442 ( .A(n6910), .B(n6909), .C(n6908), .D(n6907), .Z(
n6926) );
HS65_LH_AO22X9 U9443 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][28] ), .B(n7275),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[30][28] ), .D(
n7274), .Z(n6912) );
HS65_LH_AO22X9 U9444 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][28] ), .B(n7277),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[25][28] ), .D(
n7276), .Z(n6911) );
HS65_LH_NOR4ABX2 U9445 ( .A(n6914), .B(n6913), .C(n6912), .D(n6911), .Z(
n6925) );
HS65_LH_NAND4ABX3 U9446 ( .A(n6918), .B(n6917), .C(n6916), .D(n6915), .Z(
n6924) );
HS65_LH_AO22X9 U9447 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][28] ), .B(n6426),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][28] ), .D(
n7291), .Z(n6922) );
HS65_LH_AOI22X3 U9448 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][28] ), .B(n6941),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[7][28] ), .D(
n7294), .Z(n6920) );
HS65_LH_NAND4ABX3 U9449 ( .A(n6922), .B(n6921), .C(n6920), .D(n6919), .Z(
n6923) );
HS65_LH_AO22X9 U9450 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][5] ), .B(n6927),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][5] ), .D(n7266), .Z(n6930) );
HS65_LH_AO22X9 U9451 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][5] ), .B(n9375),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[6][5] ), .D(n7267), .Z(n6929) );
HS65_LH_NOR4ABX2 U9452 ( .A(n6932), .B(n6931), .C(n6930), .D(n6929), .Z(
n6950) );
HS65_LH_AO22X9 U9453 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][5] ), .B(n7275),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[30][5] ), .D(
n7274), .Z(n6934) );
HS65_LH_AO22X9 U9454 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][5] ), .B(n7277),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[25][5] ), .D(
n7276), .Z(n6933) );
HS65_LH_NOR4ABX2 U9455 ( .A(n6936), .B(n6935), .C(n6934), .D(n6933), .Z(
n6949) );
HS65_LH_NAND4ABX3 U9456 ( .A(n6940), .B(n6939), .C(n6938), .D(n6937), .Z(
n6948) );
HS65_LH_AOI22X3 U9457 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][5] ), .B(n6941),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[7][5] ), .D(n7294), .Z(n6944) );
HS65_LH_NAND4ABX3 U9458 ( .A(n6946), .B(n6945), .C(n6944), .D(n6943), .Z(
n6947) );
HS65_LH_NOR4ABX2 U9459 ( .A(n6956), .B(n6955), .C(n6954), .D(n6953), .Z(
n6975) );
HS65_LH_NOR4ABX2 U9460 ( .A(n6961), .B(n6960), .C(n6959), .D(n6958), .Z(
n6974) );
HS65_LH_NAND4ABX3 U9461 ( .A(n6965), .B(n6964), .C(n6963), .D(n6962), .Z(
n6973) );
HS65_LH_NAND4ABX3 U9462 ( .A(n6971), .B(n6970), .C(n6969), .D(n6968), .Z(
n6972) );
HS65_LH_NOR4ABX2 U9463 ( .A(n6979), .B(n6978), .C(n6977), .D(n6976), .Z(
n6995) );
HS65_LH_AOI22X1 U9464 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][13] ), .B(n7317),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[1][13] ), .D(
n6957), .Z(n6982) );
HS65_LH_NOR4ABX2 U9465 ( .A(n6983), .B(n6982), .C(n6981), .D(n6980), .Z(
n6994) );
HS65_LH_NAND4ABX3 U9466 ( .A(n6987), .B(n6986), .C(n6985), .D(n6984), .Z(
n6993) );
HS65_LH_NAND4ABX3 U9467 ( .A(n6991), .B(n6990), .C(n6989), .D(n6988), .Z(
n6992) );
HS65_LH_NOR4ABX2 U9468 ( .A(n6999), .B(n6998), .C(n6997), .D(n6996), .Z(
n7015) );
HS65_LH_AOI22X1 U9469 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][22] ), .B(n7317),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[1][22] ), .D(
n6957), .Z(n7002) );
HS65_LH_NOR4ABX2 U9470 ( .A(n7003), .B(n7002), .C(n7001), .D(n7000), .Z(
n7014) );
HS65_LH_NAND4ABX3 U9471 ( .A(n7007), .B(n7006), .C(n7005), .D(n7004), .Z(
n7013) );
HS65_LH_NAND4ABX3 U9472 ( .A(n7011), .B(n7010), .C(n7009), .D(n7008), .Z(
n7012) );
HS65_LH_NOR4ABX2 U9473 ( .A(n7019), .B(n7018), .C(n7017), .D(n7016), .Z(
n7035) );
HS65_LH_AOI22X1 U9474 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][9] ), .B(n7317),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[1][9] ), .D(n6957), .Z(n7022) );
HS65_LH_NOR4ABX2 U9475 ( .A(n7023), .B(n7022), .C(n7021), .D(n7020), .Z(
n7034) );
HS65_LH_NAND4ABX3 U9476 ( .A(n7027), .B(n7026), .C(n7025), .D(n7024), .Z(
n7033) );
HS65_LH_NAND4ABX3 U9477 ( .A(n7031), .B(n7030), .C(n7029), .D(n7028), .Z(
n7032) );
HS65_LH_NOR4ABX2 U9478 ( .A(n7039), .B(n7038), .C(n7037), .D(n7036), .Z(
n7055) );
HS65_LH_AOI22X1 U9479 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][25] ), .B(n7317),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[1][25] ), .D(
n6957), .Z(n7042) );
HS65_LH_NOR4ABX2 U9480 ( .A(n7043), .B(n7042), .C(n7041), .D(n7040), .Z(
n7054) );
HS65_LH_NAND4ABX3 U9481 ( .A(n7047), .B(n7046), .C(n7045), .D(n7044), .Z(
n7053) );
HS65_LH_NAND4ABX3 U9482 ( .A(n7051), .B(n7050), .C(n7049), .D(n7048), .Z(
n7052) );
HS65_LH_NOR4ABX2 U9483 ( .A(n7059), .B(n7058), .C(n7057), .D(n7056), .Z(
n7075) );
HS65_LH_AOI22X1 U9484 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][11] ), .B(n7317),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[1][11] ), .D(
n6957), .Z(n7062) );
HS65_LH_NOR4ABX2 U9485 ( .A(n7063), .B(n7062), .C(n7061), .D(n7060), .Z(
n7074) );
HS65_LH_NAND4ABX3 U9486 ( .A(n7067), .B(n7066), .C(n7065), .D(n7064), .Z(
n7073) );
HS65_LH_NAND4ABX3 U9487 ( .A(n7071), .B(n7070), .C(n7069), .D(n7068), .Z(
n7072) );
HS65_LH_NOR2X6 U9488 ( .A(n7078), .B(n7077), .Z(n7082) );
HS65_LH_NOR2X6 U9489 ( .A(n7080), .B(n7079), .Z(n7081) );
HS65_LH_NAND2X7 U9491 ( .A(n7088), .B(n7087), .Z(n7093) );
HS65_LH_NOR2X6 U9492 ( .A(\u_DataPath/cw_exmem_i [5]), .B(
\u_DataPath/cw_exmem_i [3]), .Z(n7097) );
HS65_LH_NAND2X7 U9493 ( .A(n7098), .B(n7097), .Z(n7114) );
HS65_LH_NOR2X2 U9494 ( .A(n8426), .B(n9401), .Z(n8564) );
HS65_LH_AO22X9 U9495 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][9] ), .B(n6364),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][9] ), .D(n9371), .Z(n7124) );
HS65_LH_NOR4ABX2 U9496 ( .A(n7126), .B(n7125), .C(n7124), .D(n7123), .Z(
n7142) );
HS65_LH_NOR4ABX2 U9498 ( .A(n7130), .B(n7129), .C(n7128), .D(n7127), .Z(
n7141) );
HS65_LH_NAND4ABX3 U9499 ( .A(n7134), .B(n7133), .C(n7132), .D(n7131), .Z(
n7140) );
HS65_LH_AOI22X1 U9501 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][9] ), .B(n7295),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[7][9] ), .D(n7294), .Z(n7136) );
HS65_LH_NAND4ABX3 U9502 ( .A(n7138), .B(n7137), .C(n7136), .D(n7135), .Z(
n7139) );
HS65_LH_NOR4ABX2 U9503 ( .A(n7142), .B(n7141), .C(n7140), .D(n7139), .Z(
n8336) );
HS65_LH_AO22X9 U9504 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][25] ), .B(n6364),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][25] ), .D(
n9372), .Z(n7144) );
HS65_LH_NOR4ABX2 U9505 ( .A(n7146), .B(n7145), .C(n7144), .D(n7143), .Z(
n7160) );
HS65_LH_NOR4ABX2 U9507 ( .A(n7150), .B(n7149), .C(n7148), .D(n7147), .Z(
n7159) );
HS65_LH_AO22X9 U9508 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][25] ), .B(n6426),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][25] ), .D(
n7291), .Z(n7156) );
HS65_LH_AOI22X1 U9509 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][25] ), .B(n7295),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[7][25] ), .D(
n6384), .Z(n7154) );
HS65_LH_NAND4ABX3 U9510 ( .A(n7156), .B(n7155), .C(n7154), .D(n7153), .Z(
n7157) );
HS65_LH_NOR4ABX2 U9511 ( .A(n7160), .B(n7159), .C(n7158), .D(n7157), .Z(
n8329) );
HS65_LH_NOR4ABX2 U9512 ( .A(n7164), .B(n7163), .C(n7162), .D(n7161), .Z(
n7183) );
HS65_LH_NOR4ABX2 U9513 ( .A(n7169), .B(n7168), .C(n7167), .D(n7166), .Z(
n7182) );
HS65_LH_NAND4ABX3 U9514 ( .A(n7175), .B(n7174), .C(n7173), .D(n7172), .Z(
n7181) );
HS65_LH_AOI22X1 U9515 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][13] ), .B(n7295),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[7][13] ), .D(
n6384), .Z(n7177) );
HS65_LH_NAND4ABX3 U9516 ( .A(n7179), .B(n7178), .C(n7177), .D(n7176), .Z(
n7180) );
HS65_LH_NOR4ABX2 U9517 ( .A(n7183), .B(n7182), .C(n7181), .D(n7180), .Z(
n8342) );
HS65_LH_NOR4ABX2 U9518 ( .A(n7187), .B(n7186), .C(n7185), .D(n7184), .Z(
n7203) );
HS65_LH_AOI22X1 U9519 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][15] ), .B(n7317),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[1][15] ), .D(
n6957), .Z(n7190) );
HS65_LH_NOR4ABX2 U9520 ( .A(n7191), .B(n7190), .C(n7189), .D(n7188), .Z(
n7202) );
HS65_LH_NAND4ABX3 U9521 ( .A(n7195), .B(n7194), .C(n7193), .D(n7192), .Z(
n7201) );
HS65_LH_NAND4ABX3 U9522 ( .A(n7199), .B(n7198), .C(n7197), .D(n7196), .Z(
n7200) );
HS65_LH_NOR4ABX2 U9523 ( .A(n7207), .B(n7206), .C(n7205), .D(n7204), .Z(
n7223) );
HS65_LH_AOI22X1 U9524 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][10] ), .B(n7317),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[1][10] ), .D(
n6957), .Z(n7210) );
HS65_LH_NOR4ABX2 U9525 ( .A(n7211), .B(n7210), .C(n7209), .D(n7208), .Z(
n7222) );
HS65_LH_NAND4ABX3 U9526 ( .A(n7215), .B(n7214), .C(n7213), .D(n7212), .Z(
n7221) );
HS65_LH_NAND4ABX3 U9527 ( .A(n7219), .B(n7218), .C(n7217), .D(n7216), .Z(
n7220) );
HS65_LH_NOR4ABX2 U9528 ( .A(n7227), .B(n7226), .C(n7225), .D(n7224), .Z(
n7243) );
HS65_LH_AOI22X1 U9529 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][23] ), .B(n7317),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[1][23] ), .D(
n6957), .Z(n7230) );
HS65_LH_NOR4ABX2 U9530 ( .A(n7231), .B(n7230), .C(n7229), .D(n7228), .Z(
n7242) );
HS65_LH_NAND4ABX3 U9531 ( .A(n7235), .B(n7234), .C(n7233), .D(n7232), .Z(
n7241) );
HS65_LH_NAND4ABX3 U9532 ( .A(n7239), .B(n7238), .C(n7237), .D(n7236), .Z(
n7240) );
HS65_LH_NOR4ABX2 U9533 ( .A(n7247), .B(n7246), .C(n7245), .D(n7244), .Z(
n7263) );
HS65_LH_AOI22X1 U9534 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][6] ), .B(n7317),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[1][6] ), .D(n6957), .Z(n7250) );
HS65_LH_NOR4ABX2 U9535 ( .A(n7251), .B(n7250), .C(n7249), .D(n7248), .Z(
n7262) );
HS65_LH_NAND4ABX3 U9536 ( .A(n7255), .B(n7254), .C(n7253), .D(n7252), .Z(
n7261) );
HS65_LH_NAND4ABX3 U9537 ( .A(n7259), .B(n7258), .C(n7257), .D(n7256), .Z(
n7260) );
HS65_LH_AO22X9 U9538 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][29] ), .B(n6364),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][29] ), .D(
n7266), .Z(n7269) );
HS65_LH_NOR4ABX2 U9540 ( .A(n7271), .B(n7270), .C(n7269), .D(n7268), .Z(
n7305) );
HS65_LH_AO22X9 U9541 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][29] ), .B(n7275),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[30][29] ), .D(
n7274), .Z(n7279) );
HS65_LH_AO22X9 U9542 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][29] ), .B(n7277),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[25][29] ), .D(
n7276), .Z(n7278) );
HS65_LH_NOR4ABX2 U9543 ( .A(n7281), .B(n7280), .C(n7279), .D(n7278), .Z(
n7304) );
HS65_LH_NAND4ABX3 U9544 ( .A(n7290), .B(n7289), .C(n7288), .D(n7287), .Z(
n7303) );
HS65_LH_AO22X9 U9545 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][29] ), .B(n6426),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][29] ), .D(
n7291), .Z(n7301) );
HS65_LH_AOI22X1 U9546 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][29] ), .B(n7295),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[7][29] ), .D(
n7294), .Z(n7299) );
HS65_LH_NAND4ABX3 U9547 ( .A(n7301), .B(n7300), .C(n7299), .D(n7298), .Z(
n7302) );
HS65_LH_NOR4ABX2 U9548 ( .A(n7305), .B(n7304), .C(n7303), .D(n7302), .Z(
n8448) );
HS65_LH_NOR2X2 U9549 ( .A(n8550), .B(n9401), .Z(n8551) );
HS65_LH_CNIVX3 U9550 ( .A(n7694), .Z(n7772) );
HS65_LH_NOR4ABX2 U9551 ( .A(n7316), .B(n7315), .C(n7314), .D(n7313), .Z(
n7342) );
HS65_LH_AOI22X1 U9552 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][26] ), .B(n7317),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[1][26] ), .D(
n6957), .Z(n7323) );
HS65_LH_NOR4ABX2 U9553 ( .A(n7324), .B(n7323), .C(n7322), .D(n7321), .Z(
n7341) );
HS65_LH_NAND4ABX3 U9554 ( .A(n7328), .B(n7327), .C(n7326), .D(n7325), .Z(
n7340) );
HS65_LH_NAND4ABX3 U9555 ( .A(n7338), .B(n7337), .C(n7336), .D(n7335), .Z(
n7339) );
HS65_LH_NAND2X2 U9556 ( .A(n7343), .B(n7089), .Z(n8146) );
HS65_LH_NOR4ABX2 U9559 ( .A(n7350), .B(n7349), .C(n7348), .D(n7347), .Z(
n7366) );
HS65_LH_NOR4ABX2 U9560 ( .A(n7354), .B(n7353), .C(n7352), .D(n7351), .Z(
n7365) );
HS65_LH_NAND4ABX3 U9561 ( .A(n7358), .B(n7357), .C(n7356), .D(n7355), .Z(
n7364) );
HS65_LH_NAND4ABX3 U9562 ( .A(n7362), .B(n7361), .C(n7360), .D(n7359), .Z(
n7363) );
HS65_LH_NOR4ABX2 U9563 ( .A(n7370), .B(n7369), .C(n7368), .D(n7367), .Z(
n7386) );
HS65_LH_NOR4ABX2 U9564 ( .A(n7374), .B(n7373), .C(n7372), .D(n7371), .Z(
n7385) );
HS65_LH_NAND4ABX3 U9565 ( .A(n7378), .B(n7377), .C(n7376), .D(n7375), .Z(
n7384) );
HS65_LH_NAND4ABX3 U9566 ( .A(n7382), .B(n7381), .C(n7380), .D(n7379), .Z(
n7383) );
HS65_LH_NOR4ABX2 U9567 ( .A(n7390), .B(n7389), .C(n7388), .D(n7387), .Z(
n7406) );
HS65_LH_NOR4ABX2 U9568 ( .A(n7394), .B(n7393), .C(n7392), .D(n7391), .Z(
n7405) );
HS65_LH_NAND4ABX3 U9569 ( .A(n7398), .B(n7397), .C(n7396), .D(n7395), .Z(
n7404) );
HS65_LH_NAND4ABX3 U9570 ( .A(n7402), .B(n7401), .C(n7400), .D(n7399), .Z(
n7403) );
HS65_LH_NOR4ABX2 U9571 ( .A(n7410), .B(n7409), .C(n7408), .D(n7407), .Z(
n7427) );
HS65_LH_NOR4ABX2 U9572 ( .A(n7414), .B(n7413), .C(n7412), .D(n7411), .Z(
n7426) );
HS65_LH_NAND4ABX3 U9573 ( .A(n7419), .B(n7418), .C(n7417), .D(n7416), .Z(
n7425) );
HS65_LH_NAND4ABX3 U9574 ( .A(n7423), .B(n7422), .C(n7421), .D(n7420), .Z(
n7424) );
HS65_LH_NOR4ABX2 U9575 ( .A(n7433), .B(n7432), .C(n7431), .D(n7430), .Z(
n7451) );
HS65_LH_NOR4ABX2 U9576 ( .A(n7438), .B(n7437), .C(n7436), .D(n7435), .Z(
n7450) );
HS65_LH_NAND4ABX3 U9577 ( .A(n7443), .B(n7442), .C(n7441), .D(n7440), .Z(
n7449) );
HS65_LH_NAND4ABX3 U9578 ( .A(n7447), .B(n7446), .C(n7445), .D(n7444), .Z(
n7448) );
HS65_LH_NOR4ABX2 U9579 ( .A(n7455), .B(n7454), .C(n7453), .D(n7452), .Z(
n7471) );
HS65_LH_NOR4ABX2 U9580 ( .A(n7459), .B(n7458), .C(n7457), .D(n7456), .Z(
n7470) );
HS65_LH_NAND4ABX3 U9581 ( .A(n7463), .B(n7462), .C(n7461), .D(n7460), .Z(
n7469) );
HS65_LH_NAND4ABX3 U9582 ( .A(n7467), .B(n7466), .C(n7465), .D(n7464), .Z(
n7468) );
HS65_LH_AOI22X1 U9583 ( .A(n6739), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][20] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[0][20] ), .D(n6740),
.Z(n7474) );
HS65_LH_NOR4ABX2 U9584 ( .A(n7475), .B(n7474), .C(n7473), .D(n7472), .Z(
n7491) );
HS65_LH_NOR4ABX2 U9585 ( .A(n7479), .B(n7478), .C(n7477), .D(n7476), .Z(
n7490) );
HS65_LH_NAND4ABX3 U9586 ( .A(n7483), .B(n7482), .C(n7481), .D(n7480), .Z(
n7489) );
HS65_LH_NAND4ABX3 U9587 ( .A(n7487), .B(n7486), .C(n7485), .D(n7484), .Z(
n7488) );
HS65_LH_NOR4ABX2 U9588 ( .A(n7495), .B(n7494), .C(n7493), .D(n7492), .Z(
n7511) );
HS65_LH_NOR4ABX2 U9589 ( .A(n7499), .B(n7498), .C(n7497), .D(n7496), .Z(
n7510) );
HS65_LH_NAND4ABX3 U9590 ( .A(n7503), .B(n7502), .C(n7501), .D(n7500), .Z(
n7509) );
HS65_LH_NAND4ABX3 U9591 ( .A(n7507), .B(n7506), .C(n7505), .D(n7504), .Z(
n7508) );
HS65_LH_NOR4ABX2 U9592 ( .A(n7515), .B(n7514), .C(n7513), .D(n7512), .Z(
n7537) );
HS65_LH_NOR4ABX2 U9593 ( .A(n7521), .B(n7520), .C(n7519), .D(n7518), .Z(
n7536) );
HS65_LH_NAND4ABX3 U9594 ( .A(n7529), .B(n7528), .C(n7527), .D(n7526), .Z(
n7535) );
HS65_LH_NAND4ABX3 U9595 ( .A(n7533), .B(n7532), .C(n7531), .D(n7530), .Z(
n7534) );
HS65_LH_NOR4ABX2 U9596 ( .A(n7541), .B(n7540), .C(n7539), .D(n7538), .Z(
n7557) );
HS65_LH_NOR4ABX2 U9597 ( .A(n7545), .B(n7544), .C(n7543), .D(n7542), .Z(
n7556) );
HS65_LH_NAND4ABX3 U9598 ( .A(n7549), .B(n7548), .C(n7547), .D(n7546), .Z(
n7555) );
HS65_LH_NAND4ABX3 U9599 ( .A(n7553), .B(n7552), .C(n7551), .D(n7550), .Z(
n7554) );
HS65_LH_NOR4ABX2 U9600 ( .A(n7561), .B(n7560), .C(n7559), .D(n7558), .Z(
n7577) );
HS65_LH_NOR4ABX2 U9601 ( .A(n7565), .B(n7564), .C(n7563), .D(n7562), .Z(
n7576) );
HS65_LH_NAND4ABX3 U9602 ( .A(n7569), .B(n7568), .C(n7567), .D(n7566), .Z(
n7575) );
HS65_LH_NAND4ABX3 U9603 ( .A(n7573), .B(n7572), .C(n7571), .D(n7570), .Z(
n7574) );
HS65_LH_NOR4ABX2 U9604 ( .A(n7584), .B(n7583), .C(n7582), .D(n7581), .Z(
n7612) );
HS65_LH_NOR4ABX2 U9605 ( .A(n7591), .B(n7590), .C(n7589), .D(n7588), .Z(
n7611) );
HS65_LH_NAND4ABX3 U9606 ( .A(n7598), .B(n7597), .C(n7596), .D(n7595), .Z(
n7610) );
HS65_LH_NAND4ABX3 U9607 ( .A(n7608), .B(n7607), .C(n7606), .D(n7605), .Z(
n7609) );
HS65_LH_NOR2X2 U9608 ( .A(\u_DataPath/u_idexreg/N3 ), .B(n7617), .Z(
\u_DataPath/u_execute/EXALU/N810 ) );
HS65_LH_IVX2 U9609 ( .A(n7618), .Z(n8138) );
HS65_LH_IVX2 U9610 ( .A(n7619), .Z(n8142) );
HS65_LH_NOR2AX3 U9611 ( .A(n9076), .B(n2847), .Z(n7733) );
HS65_LH_NAND2X2 U9612 ( .A(n7733), .B(n9031), .Z(n8149) );
HS65_LH_NOR2X2 U9613 ( .A(n2851), .B(n7621), .Z(n7625) );
HS65_LH_NOR2X2 U9614 ( .A(n7622), .B(n2840), .Z(n7624) );
HS65_LH_MUXI21X2 U9615 ( .D0(n7625), .D1(n7624), .S0(n7623), .Z(n7635) );
HS65_LH_NAND2X2 U9616 ( .A(n7626), .B(n2840), .Z(n7629) );
HS65_LH_NOR2X2 U9617 ( .A(n7626), .B(n2840), .Z(n7628) );
HS65_LH_MUX21I1X3 U9618 ( .D0(n7629), .D1(n7628), .S0(n7627), .Z(n7630) );
HS65_LH_NAND2X2 U9619 ( .A(n7631), .B(n7630), .Z(n7633) );
HS65_LH_CBI4I6X2 U9620 ( .A(n7635), .B(n7634), .C(n7633), .D(
\u_DataPath/u_idexreg/N3 ), .Z(\u_DataPath/u_execute/EXALU/N811 ) );
HS65_LH_CNIVX3 U9621 ( .A(\u_DataPath/jaddr_i [19]), .Z(n8042) );
HS65_LH_IVX2 U9622 ( .A(n8716), .Z(n8490) );
HS65_LH_IVX2 U9624 ( .A(Data_out_fromRAM[18]), .Z(n8454) );
HS65_LH_IVX2 U9625 ( .A(Data_out_fromRAM[19]), .Z(n8324) );
HS65_LH_IVX2 U9626 ( .A(Data_out_fromRAM[22]), .Z(n8351) );
HS65_LH_IVX2 U9627 ( .A(Data_out_fromRAM[16]), .Z(n8356) );
HS65_LH_IVX2 U9628 ( .A(Data_out_fromRAM[17]), .Z(n8406) );
HS65_LH_NOR2X6 U9631 ( .A(n7648), .B(n7676), .Z(n7649) );
HS65_LH_CNIVX3 U9632 ( .A(n7652), .Z(n7654) );
HS65_LH_NOR2X2 U9635 ( .A(opcode_i[1]), .B(opcode_i[3]), .Z(n7696) );
HS65_LH_CNIVX3 U9636 ( .A(n8086), .Z(n7702) );
HS65_LH_NOR3X1 U9637 ( .A(\u_DataPath/immediate_ext_dec_i [2]), .B(
\u_DataPath/immediate_ext_dec_i [3]), .C(n8092), .Z(n7699) );
HS65_LH_NAND2X2 U9638 ( .A(n8076), .B(n7699), .Z(n7701) );
HS65_LH_CNIVX3 U9639 ( .A(n8076), .Z(n7703) );
HS65_LH_NAND4ABX3 U9640 ( .A(opcode_i[3]), .B(n9082), .C(n7735), .D(n7778),
.Z(n8049) );
HS65_LH_NOR3X1 U9641 ( .A(\u_DataPath/immediate_ext_dec_i [2]), .B(
\u_DataPath/immediate_ext_dec_i [3]), .C(
\u_DataPath/immediate_ext_dec_i [10]), .Z(n7737) );
HS65_LH_NOR2X2 U9642 ( .A(\u_DataPath/immediate_ext_dec_i [8]), .B(
\u_DataPath/immediate_ext_dec_i [9]), .Z(n7736) );
HS65_LH_NAND4ABX3 U9643 ( .A(\u_DataPath/immediate_ext_dec_i [6]), .B(
\u_DataPath/immediate_ext_dec_i [7]), .C(n7737), .D(n7736), .Z(n8073)
);
HS65_LH_NAND4ABX3 U9644 ( .A(n7763), .B(n7740), .C(n7739), .D(n8083), .Z(
n8057) );
HS65_LH_NAND4ABX3 U9646 ( .A(n8123), .B(n8122), .C(n8121), .D(n8120), .Z(
n7760) );
HS65_LH_AOI21X2 U9647 ( .A(n7772), .B(n7777), .C(n7763), .Z(n8100) );
HS65_LH_AOI21X2 U9648 ( .A(n7773), .B(n7772), .C(n7771), .Z(n7774) );
HS65_LH_AOI222X2 U9649 ( .A(n7779), .B(opcode_i[1]), .C(n7778), .D(n7777),
.E(n9084), .F(n7776), .Z(n8081) );
HS65_LH_HA1X4 U9650 ( .A0(n2908), .B0(n9204), .CO(n7801), .S0(
\u_DataPath/u_execute/link_value_i [29]) );
HS65_LH_HA1X4 U9651 ( .A0(n7801), .B0(n9203), .CO(n7800), .S0(
\u_DataPath/u_execute/link_value_i [30]) );
HS65_LH_NOR2X2 U9652 ( .A(n8840), .B(n7802), .Z(n7803) );
HS65_LH_AND2X4 U9653 ( .A(n2896), .B(n7803), .Z(n7864) );
HS65_LL_OAI21X18 U9655 ( .A(n3009), .B(n8141), .C(n2733), .Z(
\u_DataPath/u_decode_unit/reg_file0/N148 ) );
HS65_LL_OAI21X18 U9656 ( .A(n3010), .B(n8141), .C(n2733), .Z(
\u_DataPath/u_decode_unit/reg_file0/N153 ) );
HS65_LL_OAI21X12 U9657 ( .A(n8141), .B(n2773), .C(n2733), .Z(
\u_DataPath/u_decode_unit/reg_file0/N149 ) );
HS65_LL_OAI21X12 U9658 ( .A(n8150), .B(n8145), .C(n2733), .Z(
\u_DataPath/u_decode_unit/reg_file0/N133 ) );
HS65_LL_OAI21X12 U9659 ( .A(n8150), .B(n3012), .C(n2733), .Z(
\u_DataPath/u_decode_unit/reg_file0/N134 ) );
HS65_LL_OAI21X12 U9660 ( .A(n8141), .B(n3012), .C(n2733), .Z(
\u_DataPath/u_decode_unit/reg_file0/N150 ) );
HS65_LL_OAI21X12 U9661 ( .A(n8140), .B(n3012), .C(n2733), .Z(
\u_DataPath/u_decode_unit/reg_file0/N142 ) );
HS65_LH_NOR2X2 U9662 ( .A(rst), .B(n8160), .Z(
\u_DataPath/u_decode_unit/hdu_0/current_state [1]) );
HS65_LH_BFX18 U9663 ( .A(n8443), .Z(n7899) );
HS65_LH_BFX18 U9664 ( .A(n8443), .Z(n7900) );
HS65_LH_NAND3X3 U9665 ( .A(n8142), .B(n8143), .C(n8139), .Z(n8141) );
HS65_LH_NAND3X2 U9666 ( .A(n9075), .B(n8138), .C(n8143), .Z(n8140) );
HS65_LH_AND2X4 U9667 ( .A(n2733), .B(\u_DataPath/toPC2_i [24]), .Z(
\u_DataPath/branch_target_i [24]) );
HS65_LH_NOR4ABX2 U9668 ( .A(n8566), .B(n8565), .C(n8564), .D(n7878), .Z(
\u_DataPath/mem_writedata_out_i [29]) );
HS65_LH_NOR4ABX2 U9669 ( .A(n8566), .B(n8560), .C(n8559), .D(n8558), .Z(
\u_DataPath/mem_writedata_out_i [27]) );
HS65_LH_NOR4ABX2 U9670 ( .A(n8566), .B(n8540), .C(n8539), .D(n8538), .Z(
\u_DataPath/mem_writedata_out_i [20]) );
HS65_LH_NOR4ABX2 U9671 ( .A(n8566), .B(n8543), .C(n8542), .D(n8541), .Z(
\u_DataPath/mem_writedata_out_i [21]) );
HS65_LH_AND2X4 U9674 ( .A(n2733), .B(\u_DataPath/toPC2_i [15]), .Z(
\u_DataPath/branch_target_i [15]) );
HS65_LH_AO222X4 U9675 ( .A(n7895), .B(\u_DataPath/pc_4_i [12]), .C(n7892),
.D(n9412), .E(n8917), .F(n7888), .Z(n8660) );
HS65_LH_AO222X4 U9676 ( .A(n7895), .B(\u_DataPath/pc_4_i [14]), .C(n7892),
.D(\u_DataPath/jump_address_i [14]), .E(n9198), .F(n7888), .Z(n8658)
);
HS65_LH_AO222X4 U9677 ( .A(n7895), .B(\u_DataPath/pc_4_i [18]), .C(n7892),
.D(n9411), .E(n8927), .F(n7887), .Z(n8654) );
HS65_LH_AO222X4 U9678 ( .A(n7895), .B(\u_DataPath/pc_4_i [19]), .C(n7892),
.D(\u_DataPath/jump_address_i [19]), .E(n8925), .F(n7887), .Z(n8653)
);
HS65_LH_NOR3AX4 U9679 ( .A(n8755), .B(rst), .C(\u_DataPath/cw_to_ex_i [15]),
.Z(n8450) );
HS65_LH_NOR4ABX2 U9680 ( .A(n8566), .B(n8502), .C(n8501), .D(n8500), .Z(
\u_DataPath/mem_writedata_out_i [7]) );
HS65_LH_NOR4ABX2 U9681 ( .A(n8566), .B(n8486), .C(n7864), .D(n8485), .Z(
\u_DataPath/mem_writedata_out_i [1]) );
HS65_LH_NOR4ABX2 U9682 ( .A(n8566), .B(n8499), .C(n8498), .D(n8497), .Z(
\u_DataPath/mem_writedata_out_i [6]) );
HS65_LH_NOR4ABX2 U9683 ( .A(n8518), .B(n8517), .C(n8516), .D(rst), .Z(
\u_DataPath/mem_writedata_out_i [13]) );
HS65_LH_NOR4ABX2 U9684 ( .A(n8509), .B(n8508), .C(n8507), .D(rst), .Z(
\u_DataPath/mem_writedata_out_i [10]) );
HS65_LH_NOR4ABX2 U9685 ( .A(n8530), .B(n8529), .C(n8528), .D(rst), .Z(
\u_DataPath/mem_writedata_out_i [17]) );
HS65_LH_NOR4ABX2 U9686 ( .A(n8521), .B(n8520), .C(n8519), .D(rst), .Z(
\u_DataPath/mem_writedata_out_i [14]) );
HS65_LH_NOR4ABX2 U9687 ( .A(n8527), .B(n8526), .C(n8525), .D(rst), .Z(
\u_DataPath/mem_writedata_out_i [16]) );
HS65_LH_NOR4ABX2 U9688 ( .A(n8533), .B(n8532), .C(n8531), .D(rst), .Z(
\u_DataPath/mem_writedata_out_i [18]) );
HS65_LH_NOR4ABX2 U9689 ( .A(n8549), .B(n8548), .C(n8547), .D(rst), .Z(
\u_DataPath/mem_writedata_out_i [23]) );
HS65_LH_NOR4ABX2 U9690 ( .A(n8512), .B(n8511), .C(n8510), .D(rst), .Z(
\u_DataPath/mem_writedata_out_i [11]) );
HS65_LH_NOR4ABX2 U9691 ( .A(n8524), .B(n8523), .C(n8522), .D(rst), .Z(
\u_DataPath/mem_writedata_out_i [15]) );
HS65_LH_NOR4ABX2 U9692 ( .A(n8557), .B(n8556), .C(n8555), .D(rst), .Z(
\u_DataPath/mem_writedata_out_i [26]) );
HS65_LH_NOR4ABX2 U9693 ( .A(n8553), .B(n8552), .C(rst), .D(n8551), .Z(
\u_DataPath/mem_writedata_out_i [24]) );
HS65_LH_NOR4ABX2 U9694 ( .A(n8496), .B(n8495), .C(n7863), .D(rst), .Z(
\u_DataPath/mem_writedata_out_i [5]) );
HS65_LH_NOR4ABX2 U9695 ( .A(n8515), .B(n8514), .C(n8513), .D(rst), .Z(
\u_DataPath/mem_writedata_out_i [12]) );
HS65_LH_NOR4ABX2 U9696 ( .A(n8569), .B(n8568), .C(n8567), .D(rst), .Z(
\u_DataPath/mem_writedata_out_i [30]) );
HS65_LH_NOR4ABX2 U9697 ( .A(n8572), .B(n8571), .C(n8570), .D(rst), .Z(
\u_DataPath/mem_writedata_out_i [31]) );
HS65_LH_NOR4ABX2 U9698 ( .A(n8546), .B(n8545), .C(n8544), .D(rst), .Z(
\u_DataPath/mem_writedata_out_i [22]) );
HS65_LH_AND2X4 U9699 ( .A(n2733), .B(\u_DataPath/toPC2_i [22]), .Z(
\u_DataPath/branch_target_i [22]) );
HS65_LH_AND2X4 U9700 ( .A(n2733), .B(\u_DataPath/toPC2_i [17]), .Z(
\u_DataPath/branch_target_i [17]) );
HS65_LH_AND2X4 U9701 ( .A(n2733), .B(\u_DataPath/toPC2_i [18]), .Z(
\u_DataPath/branch_target_i [18]) );
HS65_LH_AND2X4 U9702 ( .A(n2733), .B(\u_DataPath/toPC2_i [20]), .Z(
\u_DataPath/branch_target_i [20]) );
HS65_LH_AND2X4 U9703 ( .A(n2733), .B(\u_DataPath/toPC2_i [19]), .Z(
\u_DataPath/branch_target_i [19]) );
HS65_LH_NOR2X2 U9704 ( .A(n8262), .B(rst), .Z(n8143) );
HS65_LH_BFX4 U9705 ( .A(n8609), .Z(n8004) );
HS65_LH_BFX4 U9706 ( .A(n8607), .Z(n7995) );
HS65_LH_BFX4 U9707 ( .A(n8599), .Z(n7968) );
HS65_LH_BFX4 U9708 ( .A(n8593), .Z(n7950) );
HS65_LH_BFX4 U9709 ( .A(n8595), .Z(n7956) );
HS65_LH_BFX4 U9710 ( .A(n8610), .Z(n8007) );
HS65_LH_BFX4 U9711 ( .A(n8598), .Z(n7965) );
HS65_LH_BFX4 U9712 ( .A(n8616), .Z(n8022) );
HS65_LH_BFX4 U9713 ( .A(n8606), .Z(n7992) );
HS65_LH_BFX4 U9714 ( .A(n8612), .Z(n8013) );
HS65_LH_BFX4 U9715 ( .A(n8603), .Z(n7983) );
HS65_LH_BFX4 U9716 ( .A(n8601), .Z(n7977) );
HS65_LH_BFX4 U9717 ( .A(n8622), .Z(n8031) );
HS65_LH_BFX4 U9718 ( .A(n8588), .Z(n7938) );
HS65_LH_BFX4 U9719 ( .A(n8596), .Z(n7959) );
HS65_LH_BFX4 U9720 ( .A(n8594), .Z(n7953) );
HS65_LH_BFX4 U9721 ( .A(n8604), .Z(n7986) );
HS65_LH_BFX4 U9722 ( .A(n8620), .Z(n8028) );
HS65_LH_BFX4 U9723 ( .A(n8602), .Z(n7980) );
HS65_LH_BFX4 U9724 ( .A(n8613), .Z(n8016) );
HS65_LH_BFX4 U9725 ( .A(n8618), .Z(n8025) );
HS65_LH_BFX4 U9726 ( .A(n8611), .Z(n8011) );
HS65_LH_BFX4 U9727 ( .A(n8611), .Z(n8012) );
HS65_LH_BFX4 U9728 ( .A(n8587), .Z(n7935) );
HS65_LH_CNIVX3 U9729 ( .A(n8608), .Z(n8003) );
HS65_LH_BFX4 U9730 ( .A(n8585), .Z(n7928) );
HS65_LH_BFX4 U9731 ( .A(n8605), .Z(n7991) );
HS65_LH_BFX4 U9732 ( .A(n8589), .Z(n7943) );
HS65_LH_BFX4 U9733 ( .A(n8597), .Z(n7964) );
HS65_LH_BFX4 U9734 ( .A(n8614), .Z(n8021) );
HS65_LH_BFX4 U9735 ( .A(n8609), .Z(n8006) );
HS65_LH_BFX4 U9736 ( .A(n8607), .Z(n7997) );
HS65_LH_BFX4 U9737 ( .A(n8599), .Z(n7970) );
HS65_LH_BFX4 U9738 ( .A(n8614), .Z(n8019) );
HS65_LH_BFX4 U9739 ( .A(n8597), .Z(n7962) );
HS65_LH_BFX4 U9740 ( .A(n8589), .Z(n7941) );
HS65_LH_CNIVX3 U9741 ( .A(n8600), .Z(n7976) );
HS65_LH_BFX4 U9742 ( .A(n8605), .Z(n7989) );
HS65_LH_BFX4 U9743 ( .A(n8585), .Z(n7926) );
HS65_LH_BFX4 U9744 ( .A(n8587), .Z(n7936) );
HS65_LH_CNIVX3 U9745 ( .A(n8608), .Z(n8002) );
HS65_LH_BFX4 U9746 ( .A(n8618), .Z(n8026) );
HS65_LH_BFX4 U9747 ( .A(n8613), .Z(n8017) );
HS65_LH_BFX4 U9748 ( .A(n8602), .Z(n7981) );
HS65_LH_BFX4 U9749 ( .A(n8620), .Z(n8029) );
HS65_LH_BFX4 U9750 ( .A(n8604), .Z(n7987) );
HS65_LH_BFX4 U9751 ( .A(n8594), .Z(n7954) );
HS65_LH_BFX4 U9752 ( .A(n8596), .Z(n7960) );
HS65_LH_BFX4 U9753 ( .A(n8588), .Z(n7939) );
HS65_LH_BFX4 U9754 ( .A(n8622), .Z(n8032) );
HS65_LH_BFX4 U9755 ( .A(n8601), .Z(n7978) );
HS65_LH_BFX4 U9756 ( .A(n8603), .Z(n7984) );
HS65_LH_BFX4 U9757 ( .A(n8612), .Z(n8014) );
HS65_LH_BFX4 U9758 ( .A(n8606), .Z(n7993) );
HS65_LH_BFX4 U9759 ( .A(n8616), .Z(n8023) );
HS65_LH_BFX4 U9760 ( .A(n8598), .Z(n7966) );
HS65_LH_BFX4 U9761 ( .A(n8610), .Z(n8008) );
HS65_LH_BFX4 U9762 ( .A(n8595), .Z(n7957) );
HS65_LH_BFX4 U9763 ( .A(n8593), .Z(n7951) );
HS65_LH_BFX4 U9764 ( .A(n8599), .Z(n7969) );
HS65_LH_CNIVX3 U9765 ( .A(n8293), .Z(n8599) );
HS65_LH_BFX4 U9766 ( .A(n8611), .Z(n8010) );
HS65_LH_CNIVX3 U9767 ( .A(n8397), .Z(n8611) );
HS65_LH_BFX4 U9768 ( .A(n8607), .Z(n7996) );
HS65_LH_CNIVX3 U9769 ( .A(n8362), .Z(n8607) );
HS65_LH_BFX4 U9770 ( .A(n8609), .Z(n8005) );
HS65_LH_CNIVX3 U9771 ( .A(n8321), .Z(n8609) );
HS65_LH_CNIVX3 U9772 ( .A(n8591), .Z(n7948) );
HS65_LH_BFX4 U9773 ( .A(n8614), .Z(n8020) );
HS65_LH_CNIVX3 U9774 ( .A(n8434), .Z(n8614) );
HS65_LH_BFX4 U9775 ( .A(n8597), .Z(n7963) );
HS65_LH_CNIVX3 U9776 ( .A(n8326), .Z(n8597) );
HS65_LH_BFX4 U9777 ( .A(n8589), .Z(n7942) );
HS65_LH_CNIVX3 U9778 ( .A(n8348), .Z(n8589) );
HS65_LH_CNIVX3 U9779 ( .A(n8600), .Z(n7975) );
HS65_LH_BFX4 U9780 ( .A(n8605), .Z(n7990) );
HS65_LH_CNIVX3 U9781 ( .A(n8404), .Z(n8605) );
HS65_LH_BFX4 U9782 ( .A(n8585), .Z(n7927) );
HS65_LH_CNIVX3 U9783 ( .A(n8378), .Z(n8585) );
HS65_LH_BFX4 U9784 ( .A(n8587), .Z(n7937) );
HS65_LH_CNIVX3 U9785 ( .A(n8422), .Z(n8587) );
HS65_LH_BFX4 U9786 ( .A(n8618), .Z(n8027) );
HS65_LH_CNIVX3 U9787 ( .A(n8168), .Z(n8618) );
HS65_LH_CNIVX3 U9788 ( .A(n8591), .Z(n7949) );
HS65_LH_BFX4 U9789 ( .A(n8613), .Z(n8018) );
HS65_LH_CNIVX3 U9790 ( .A(n8314), .Z(n8613) );
HS65_LH_BFX4 U9791 ( .A(n8593), .Z(n7952) );
HS65_LH_CNIVX3 U9792 ( .A(n8304), .Z(n8593) );
HS65_LH_BFX4 U9793 ( .A(n8595), .Z(n7958) );
HS65_LH_CNIVX3 U9794 ( .A(n8343), .Z(n8595) );
HS65_LH_BFX4 U9795 ( .A(n8610), .Z(n8009) );
HS65_LH_CNIVX3 U9796 ( .A(n8449), .Z(n8610) );
HS65_LH_BFX4 U9797 ( .A(n8598), .Z(n7967) );
HS65_LH_CNIVX3 U9798 ( .A(n8367), .Z(n8598) );
HS65_LH_BFX4 U9799 ( .A(n8602), .Z(n7982) );
HS65_LH_CNIVX3 U9800 ( .A(n8457), .Z(n8602) );
HS65_LH_BFX4 U9801 ( .A(n8616), .Z(n8024) );
HS65_LH_CNIVX3 U9802 ( .A(n8415), .Z(n8616) );
HS65_LH_BFX4 U9803 ( .A(n8606), .Z(n7994) );
HS65_LH_CNIVX3 U9804 ( .A(n8330), .Z(n8606) );
HS65_LH_BFX4 U9805 ( .A(n8612), .Z(n8015) );
HS65_LH_CNIVX3 U9806 ( .A(n8337), .Z(n8612) );
HS65_LH_BFX4 U9807 ( .A(n8603), .Z(n7985) );
HS65_LH_CNIVX3 U9808 ( .A(n8372), .Z(n8603) );
HS65_LH_BFX4 U9809 ( .A(n8596), .Z(n7961) );
HS65_LH_CNIVX3 U9810 ( .A(n8412), .Z(n8596) );
HS65_LH_BFX4 U9811 ( .A(n8622), .Z(n8033) );
HS65_LH_CNIVX3 U9812 ( .A(n8431), .Z(n8622) );
HS65_LH_BFX4 U9813 ( .A(n8604), .Z(n7988) );
HS65_LH_CNIVX3 U9814 ( .A(n8408), .Z(n8604) );
HS65_LH_BFX4 U9815 ( .A(n8620), .Z(n8030) );
HS65_LH_CNIVX3 U9816 ( .A(n8444), .Z(n8620) );
HS65_LH_BFX4 U9817 ( .A(n8594), .Z(n7955) );
HS65_LH_CNIVX3 U9818 ( .A(n8358), .Z(n8594) );
HS65_LH_BFX4 U9819 ( .A(n8588), .Z(n7940) );
HS65_LH_CNIVX3 U9820 ( .A(n8275), .Z(n8588) );
HS65_LH_BFX4 U9821 ( .A(n8601), .Z(n7979) );
HS65_LH_CNIVX3 U9822 ( .A(n8353), .Z(n8601) );
HS65_LH_AND2X4 U9823 ( .A(n2733), .B(\u_DataPath/toPC2_i [1]), .Z(
\u_DataPath/branch_target_i [1]) );
HS65_LH_NOR4ABX2 U9824 ( .A(n8506), .B(n8505), .C(n8504), .D(rst), .Z(
\u_DataPath/mem_writedata_out_i [9]) );
HS65_LH_AND2X4 U9825 ( .A(n2733), .B(\u_DataPath/toPC2_i [2]), .Z(
\u_DataPath/branch_target_i [2]) );
HS65_LH_NOR4ABX2 U9826 ( .A(n8492), .B(n8491), .C(n3312), .D(rst), .Z(
\u_DataPath/mem_writedata_out_i [3]) );
HS65_LH_NOR2X2 U9827 ( .A(rst), .B(n8034), .Z(
\u_DataPath/u_decode_unit/hdu_0/current_state [0]) );
HS65_LH_AND2X4 U9828 ( .A(n2733), .B(\u_DataPath/toPC2_i [5]), .Z(
\u_DataPath/branch_target_i [5]) );
HS65_LH_AND2X4 U9829 ( .A(n2733), .B(\u_DataPath/toPC2_i [6]), .Z(
\u_DataPath/branch_target_i [6]) );
HS65_LH_AND2X4 U9830 ( .A(n2733), .B(\u_DataPath/toPC2_i [8]), .Z(
\u_DataPath/branch_target_i [8]) );
HS65_LH_AND2X4 U9831 ( .A(n2733), .B(\u_DataPath/toPC2_i [13]), .Z(
\u_DataPath/branch_target_i [13]) );
HS65_LH_AND2X4 U9832 ( .A(n2733), .B(\u_DataPath/toPC2_i [11]), .Z(
\u_DataPath/branch_target_i [11]) );
HS65_LH_AND2X4 U9833 ( .A(n2733), .B(\u_DataPath/toPC2_i [12]), .Z(
\u_DataPath/branch_target_i [12]) );
HS65_LH_OAI12X6 U9834 ( .A(n8140), .B(n8149), .C(n2733), .Z(
\u_DataPath/u_decode_unit/reg_file0/N144 ) );
HS65_LH_OAI12X6 U9835 ( .A(n8141), .B(n8149), .C(n2733), .Z(
\u_DataPath/u_decode_unit/reg_file0/N152 ) );
HS65_LH_OAI12X6 U9836 ( .A(n8144), .B(n8150), .C(n2733), .Z(
\u_DataPath/u_decode_unit/reg_file0/N138 ) );
HS65_LH_OAI12X6 U9837 ( .A(n8144), .B(n8148), .C(n2733), .Z(
\u_DataPath/u_decode_unit/reg_file0/N130 ) );
HS65_LH_OAI12X6 U9838 ( .A(n8146), .B(n8148), .C(n2733), .Z(
\u_DataPath/u_decode_unit/reg_file0/N131 ) );
HS65_LH_OAI12X6 U9839 ( .A(n8140), .B(n8144), .C(n2733), .Z(
\u_DataPath/u_decode_unit/reg_file0/N146 ) );
HS65_LH_OAI12X6 U9840 ( .A(n8149), .B(n8150), .C(n2733), .Z(
\u_DataPath/u_decode_unit/reg_file0/N136 ) );
HS65_LH_OAI12X6 U9841 ( .A(n8144), .B(n8141), .C(n2733), .Z(
\u_DataPath/u_decode_unit/reg_file0/N154 ) );
HS65_LH_OAI12X6 U9842 ( .A(n8140), .B(n8146), .C(n2733), .Z(
\u_DataPath/u_decode_unit/reg_file0/N147 ) );
HS65_LH_OAI12X6 U9843 ( .A(n8146), .B(n8150), .C(n2733), .Z(
\u_DataPath/u_decode_unit/reg_file0/N139 ) );
HS65_LH_NAND3X5 U9844 ( .A(n8960), .B(n8142), .C(n8143), .Z(n8150) );
HS65_LH_OAI12X6 U9845 ( .A(n8149), .B(n8148), .C(n2733), .Z(
\u_DataPath/u_decode_unit/reg_file0/N128 ) );
HS65_LH_CNIVX3 U9846 ( .A(n7934), .Z(n7929) );
HS65_LH_CNIVX3 U9847 ( .A(n8586), .Z(n7934) );
HS65_LH_CNIVX3 U9848 ( .A(n8003), .Z(n7998) );
HS65_LH_CNIVX3 U9849 ( .A(n7974), .Z(n7973) );
HS65_LH_CNIVX3 U9850 ( .A(n7947), .Z(n7946) );
HS65_LH_CNIVX3 U9851 ( .A(n7976), .Z(n7971) );
HS65_LH_CNIVX3 U9852 ( .A(n8002), .Z(n7999) );
HS65_LH_CNIVX3 U9853 ( .A(n7933), .Z(n7930) );
HS65_LH_CNIVX3 U9854 ( .A(n8586), .Z(n7933) );
HS65_LH_CNIVX3 U9855 ( .A(n7948), .Z(n7945) );
HS65_LH_CNIVX3 U9856 ( .A(n7975), .Z(n7972) );
HS65_LH_CNIVX3 U9857 ( .A(n8001), .Z(n8000) );
HS65_LH_CNIVX3 U9858 ( .A(n7949), .Z(n7944) );
HS65_LH_CNIVX3 U9859 ( .A(n7932), .Z(n7931) );
HS65_LH_CNIVX3 U9860 ( .A(n8423), .Z(\u_DataPath/u_execute/psw_status_i [1])
);
HS65_LH_CNIVX3 U9864 ( .A(n8228), .Z(\u_DataPath/pc_4_to_ex_i [2]) );
HS65_LH_CNIVX3 U9865 ( .A(n8230), .Z(\u_DataPath/u_execute/link_value_i [0])
);
HS65_LH_CNIVX3 U9866 ( .A(n8113), .Z(\u_DataPath/cw_tomem_i [5]) );
HS65_LH_CNIVX3 U9867 ( .A(n8109), .Z(\u_DataPath/cw_tomem_i [4]) );
HS65_LH_CNIVX3 U9868 ( .A(n8061), .Z(\u_DataPath/reg_write_i ) );
HS65_LH_CNIVX3 U9869 ( .A(n8263), .Z(\u_DataPath/cw_memwb_i [1]) );
HS65_LH_CNIVX3 U9870 ( .A(n8579), .Z(n8494) );
HS65_LL_OAI22X1 U9871 ( .A(n7096), .B(n8431), .C(n7901), .D(n8392), .Z(
\u_DataPath/data_read_ex_2_i [4]) );
HS65_LL_OAI22X1 U9872 ( .A(n7096), .B(n8404), .C(n7901), .D(n8388), .Z(
\u_DataPath/data_read_ex_2_i [14]) );
HS65_LL_OAI22X1 U9873 ( .A(n7096), .B(n8434), .C(n7901), .D(n8433), .Z(
\u_DataPath/data_read_ex_2_i [3]) );
HS65_LH_NAND2X7 U9875 ( .A(opcode_i[5]), .B(n8045), .Z(n8053) );
HS65_LL_OAI22X1 U9876 ( .A(n7096), .B(n8397), .C(n7900), .D(n8379), .Z(
\u_DataPath/data_read_ex_2_i [30]) );
HS65_LL_OAI22X1 U9877 ( .A(n7902), .B(n8001), .C(n7899), .D(n8155), .Z(
\u_DataPath/data_read_ex_2_i [0]) );
HS65_LL_OAI22X1 U9878 ( .A(n7096), .B(n8378), .C(n7900), .D(n8373), .Z(
\u_DataPath/data_read_ex_2_i [27]) );
HS65_LL_OAI22X1 U9879 ( .A(n7096), .B(n8412), .C(n7901), .D(n8384), .Z(
\u_DataPath/data_read_ex_2_i [20]) );
HS65_LL_OAI22X1 U9880 ( .A(n7096), .B(n7932), .C(n7901), .D(n8382), .Z(
\u_DataPath/data_read_ex_2_i [28]) );
HS65_LL_OAI22X1 U9881 ( .A(n7096), .B(n8449), .C(n7901), .D(n8381), .Z(
\u_DataPath/data_read_ex_2_i [29]) );
HS65_LL_OAI22X1 U9882 ( .A(n7096), .B(n8358), .C(n7900), .D(n8354), .Z(
\u_DataPath/data_read_ex_2_i [16]) );
HS65_LL_OAI22X1 U9883 ( .A(n7096), .B(n8372), .C(n7900), .D(n8368), .Z(
\u_DataPath/data_read_ex_2_i [24]) );
HS65_LL_OAI22X1 U9884 ( .A(n7096), .B(n8367), .C(n7900), .D(n8363), .Z(
\u_DataPath/data_read_ex_2_i [21]) );
HS65_LH_OAI211X3 U9885 ( .A(n8696), .B(n9012), .C(n8885), .D(n8079), .Z(
\u_DataPath/cw_to_ex_i [1]) );
HS65_LL_OAI22X1 U9888 ( .A(n7096), .B(n8444), .C(n7901), .D(n8442), .Z(
\u_DataPath/data_read_ex_2_i [2]) );
HS65_LH_NOR2AX3 U9889 ( .A(n9233), .B(rst), .Z(n8286) );
HS65_LH_IVX9 U9890 ( .A(n8480), .Z(n7873) );
HS65_LH_NOR2AX3 U9891 ( .A(\u_DataPath/cw_exmem_i [3]), .B(rst), .Z(
\u_DataPath/cw_tomem_i [3]) );
HS65_LH_NOR2AX3 U9892 ( .A(\u_DataPath/dataOut_exe_i [31]), .B(rst), .Z(
\u_DataPath/from_alu_data_out_i [31]) );
HS65_LH_NOR2AX3 U9893 ( .A(\u_DataPath/dataOut_exe_i [17]), .B(rst), .Z(
\u_DataPath/from_alu_data_out_i [17]) );
HS65_LH_NOR2AX3 U9894 ( .A(\u_DataPath/dataOut_exe_i [16]), .B(rst), .Z(
\u_DataPath/from_alu_data_out_i [16]) );
HS65_LH_NOR2AX3 U9895 ( .A(\u_DataPath/dataOut_exe_i [22]), .B(rst), .Z(
\u_DataPath/from_alu_data_out_i [22]) );
HS65_LH_NOR2AX3 U9896 ( .A(\u_DataPath/dataOut_exe_i [28]), .B(rst), .Z(
\u_DataPath/from_alu_data_out_i [28]) );
HS65_LH_NOR2AX3 U9897 ( .A(\u_DataPath/dataOut_exe_i [9]), .B(rst), .Z(
\u_DataPath/from_alu_data_out_i [9]) );
HS65_LH_NOR2AX3 U9898 ( .A(\u_DataPath/dataOut_exe_i [7]), .B(rst), .Z(
\u_DataPath/from_alu_data_out_i [7]) );
HS65_LH_NOR2AX3 U9899 ( .A(\u_DataPath/dataOut_exe_i [3]), .B(rst), .Z(
\u_DataPath/from_alu_data_out_i [3]) );
HS65_LH_NOR2AX3 U9900 ( .A(\u_DataPath/dataOut_exe_i [29]), .B(rst), .Z(
\u_DataPath/from_alu_data_out_i [29]) );
HS65_LH_NOR2AX3 U9901 ( .A(\u_DataPath/dataOut_exe_i [14]), .B(rst), .Z(
\u_DataPath/from_alu_data_out_i [14]) );
HS65_LH_NOR2AX3 U9902 ( .A(\u_DataPath/immediate_ext_dec_i [4]), .B(rst),
.Z(\u_DataPath/immediate_ext_ex_i [4]) );
HS65_LH_NOR2X6 U9903 ( .A(n8166), .B(rst), .Z(n8626) );
HS65_LH_AND2X4 U9904 ( .A(n9068), .B(n8634), .Z(\u_DataPath/cw_to_ex_i [20])
);
HS65_LH_MUXI21X2 U9905 ( .D0(n9084), .D1(iram_data[26]), .S0(
\u_DataPath/u_fetch/pc1/N3 ), .Z(n8043) );
HS65_LH_MUXI21X2 U9906 ( .D0(n9082), .D1(iram_data[28]), .S0(
\u_DataPath/u_fetch/pc1/N3 ), .Z(n8036) );
HS65_LH_MUXI21X2 U9907 ( .D0(n9068), .D1(iram_data[30]), .S0(
\u_DataPath/u_fetch/pc1/N3 ), .Z(n8035) );
HS65_LH_NOR2AX3 U9908 ( .A(\u_DataPath/dataOut_exe_i [15]), .B(rst), .Z(
\u_DataPath/from_alu_data_out_i [15]) );
HS65_LH_NOR2AX3 U9909 ( .A(\u_DataPath/dataOut_exe_i [6]), .B(rst), .Z(
\u_DataPath/from_alu_data_out_i [6]) );
HS65_LH_NOR2AX3 U9910 ( .A(\u_DataPath/dataOut_exe_i [5]), .B(rst), .Z(
\u_DataPath/from_alu_data_out_i [5]) );
HS65_LH_NOR2AX3 U9911 ( .A(\u_DataPath/dataOut_exe_i [23]), .B(rst), .Z(
\u_DataPath/from_alu_data_out_i [23]) );
HS65_LH_NOR2AX3 U9912 ( .A(\u_DataPath/dataOut_exe_i [30]), .B(rst), .Z(
\u_DataPath/from_alu_data_out_i [30]) );
HS65_LH_NOR2AX3 U9913 ( .A(\u_DataPath/dataOut_exe_i [8]), .B(rst), .Z(
\u_DataPath/from_alu_data_out_i [8]) );
HS65_LH_NOR2AX3 U9914 ( .A(\u_DataPath/dataOut_exe_i [26]), .B(rst), .Z(
\u_DataPath/u_memwbreg/N64 ) );
HS65_LH_NOR2AX3 U9915 ( .A(\u_DataPath/dataOut_exe_i [24]), .B(rst), .Z(
\u_DataPath/from_alu_data_out_i [24]) );
HS65_LH_NOR2AX3 U9916 ( .A(\u_DataPath/dataOut_exe_i [2]), .B(rst), .Z(
\u_DataPath/from_alu_data_out_i [2]) );
HS65_LH_NOR2AX3 U9917 ( .A(\u_DataPath/dataOut_exe_i [19]), .B(rst), .Z(
\u_DataPath/from_alu_data_out_i [19]) );
HS65_LH_NOR2AX3 U9918 ( .A(\u_DataPath/dataOut_exe_i [18]), .B(rst), .Z(
\u_DataPath/from_alu_data_out_i [18]) );
HS65_LH_NOR2AX3 U9919 ( .A(\u_DataPath/dataOut_exe_i [12]), .B(rst), .Z(
\u_DataPath/from_alu_data_out_i [12]) );
HS65_LH_NOR2AX3 U9920 ( .A(\u_DataPath/dataOut_exe_i [25]), .B(rst), .Z(
\u_DataPath/from_alu_data_out_i [25]) );
HS65_LH_NOR2AX3 U9921 ( .A(\u_DataPath/dataOut_exe_i [13]), .B(rst), .Z(
\u_DataPath/from_alu_data_out_i [13]) );
HS65_LH_NOR2AX3 U9922 ( .A(\u_DataPath/dataOut_exe_i [11]), .B(rst), .Z(
\u_DataPath/from_alu_data_out_i [11]) );
HS65_LH_NOR2AX3 U9923 ( .A(\u_DataPath/dataOut_exe_i [21]), .B(rst), .Z(
\u_DataPath/from_alu_data_out_i [21]) );
HS65_LH_NOR2AX3 U9924 ( .A(\u_DataPath/dataOut_exe_i [27]), .B(rst), .Z(
\u_DataPath/from_alu_data_out_i [27]) );
HS65_LH_NOR2AX3 U9925 ( .A(\u_DataPath/dataOut_exe_i [20]), .B(rst), .Z(
\u_DataPath/from_alu_data_out_i [20]) );
HS65_LH_NOR2AX3 U9926 ( .A(\u_DataPath/dataOut_exe_i [10]), .B(rst), .Z(
\u_DataPath/from_alu_data_out_i [10]) );
HS65_LH_AO22X4 U9927 ( .A(n8580), .B(n8425), .C(n8621), .D(n8573), .Z(
\u_DataPath/u_execute/psw_status_i [0]) );
HS65_LH_AO222X4 U9928 ( .A(n7894), .B(n8691), .C(n7891), .D(
\u_DataPath/jump_address_i [0]), .E(n9250), .F(n7889), .Z(
\u_DataPath/pc_4_i [0]) );
HS65_LH_AO222X4 U9929 ( .A(n7894), .B(n8689), .C(n7891), .D(
\u_DataPath/jump_address_i [1]), .E(n8924), .F(n7889), .Z(
\u_DataPath/pc_4_i [1]) );
HS65_LH_AO222X4 U9930 ( .A(n7894), .B(\u_DataPath/pc_4_i [2]), .C(n7891),
.D(\u_DataPath/jump_address_i [2]), .E(n8923), .F(n7889), .Z(n8670) );
HS65_LH_BFX4 U9931 ( .A(n8283), .Z(n7885) );
HS65_LH_AO222X4 U9932 ( .A(n7894), .B(\u_DataPath/pc_4_i [3]), .C(n7891),
.D(\u_DataPath/jump_address_i [3]), .E(n9147), .F(n7889), .Z(n8669) );
HS65_LH_AO222X4 U9933 ( .A(n7894), .B(\u_DataPath/pc_4_i [4]), .C(n7891),
.D(\u_DataPath/jump_address_i [4]), .E(n9148), .F(n7888), .Z(n8668) );
HS65_LH_AO222X4 U9934 ( .A(n7894), .B(\u_DataPath/pc_4_i [5]), .C(n7891),
.D(n9409), .E(n8922), .F(n7888), .Z(n8667) );
HS65_LH_AO222X4 U9935 ( .A(n7894), .B(\u_DataPath/pc_4_i [6]), .C(n7891),
.D(n9410), .E(n8921), .F(n7888), .Z(n8666) );
HS65_LH_AO222X4 U9937 ( .A(n7894), .B(\u_DataPath/pc_4_i [7]), .C(n7891),
.D(\u_DataPath/jump_address_i [7]), .E(n9196), .F(n7888), .Z(n8665) );
HS65_LH_AO222X4 U9938 ( .A(n7894), .B(\u_DataPath/pc_4_i [10]), .C(n7891),
.D(\u_DataPath/jump_address_i [10]), .E(n9263), .F(n7888), .Z(n8662)
);
HS65_LH_AO222X4 U9939 ( .A(n7894), .B(\u_DataPath/pc_4_i [8]), .C(n7891),
.D(n9408), .E(n8920), .F(n7888), .Z(n8664) );
HS65_LH_AO222X4 U9940 ( .A(n7894), .B(\u_DataPath/pc_4_i [11]), .C(n7891),
.D(n9407), .E(n8918), .F(n7888), .Z(n8661) );
HS65_LH_AO222X4 U9941 ( .A(n7894), .B(\u_DataPath/pc_4_i [9]), .C(n7891),
.D(\u_DataPath/jump_address_i [9]), .E(n9195), .F(n7888), .Z(n8663) );
HS65_LH_AOI21X2 U9946 ( .A(n8084), .B(n8083), .C(n8117), .Z(n8085) );
HS65_LH_CNIVX27 U9948 ( .A(rst), .Z(n8566) );
HS65_LH_CNIVX27 U9949 ( .A(n2733), .Z(n8480) );
HS65_LL_DFPQX4 clk_r_REG0_S1 ( .D(n2733), .CP(clk), .Q(n9334) );
HS65_LL_DFPQX4 clk_r_REG648_S1 ( .D(Data_out_fromRAM[30]), .CP(clk), .Q(
n9302) );
HS65_LL_DFPQX4 clk_r_REG650_S1 ( .D(Data_out_fromRAM[29]), .CP(clk), .Q(
n9301) );
HS65_LL_DFPQX4 clk_r_REG652_S1 ( .D(Data_out_fromRAM[28]), .CP(clk), .Q(
n9300) );
HS65_LL_DFPQX4 clk_r_REG654_S1 ( .D(Data_out_fromRAM[27]), .CP(clk), .Q(
n9299) );
HS65_LL_DFPQX4 clk_r_REG656_S1 ( .D(Data_out_fromRAM[26]), .CP(clk), .Q(
n9298) );
HS65_LL_DFPQX4 clk_r_REG658_S1 ( .D(Data_out_fromRAM[25]), .CP(clk), .Q(
n9297) );
HS65_LL_DFPQX4 clk_r_REG663_S1 ( .D(Data_out_fromRAM[22]), .CP(clk), .Q(
n9295) );
HS65_LL_DFPQX4 clk_r_REG667_S1 ( .D(Data_out_fromRAM[20]), .CP(clk), .Q(
n9293) );
HS65_LL_DFPQX4 clk_r_REG669_S1 ( .D(Data_out_fromRAM[19]), .CP(clk), .Q(
n9292) );
HS65_LL_DFPQX4 clk_r_REG671_S1 ( .D(Data_out_fromRAM[18]), .CP(clk), .Q(
n9291) );
HS65_LL_DFPQX4 clk_r_REG673_S1 ( .D(Data_out_fromRAM[17]), .CP(clk), .Q(
n9290) );
HS65_LL_DFPQX4 clk_r_REG675_S1 ( .D(Data_out_fromRAM[16]), .CP(clk), .Q(
n9289) );
HS65_LL_DFPQX4 clk_r_REG677_S1 ( .D(Data_out_fromRAM[15]), .CP(clk), .Q(
n9288) );
HS65_LL_DFPQX4 clk_r_REG678_S1 ( .D(Data_out_fromRAM[14]), .CP(clk), .Q(
n9287) );
HS65_LL_DFPQX4 clk_r_REG679_S1 ( .D(Data_out_fromRAM[13]), .CP(clk), .Q(
n9286) );
HS65_LL_DFPQX4 clk_r_REG680_S1 ( .D(Data_out_fromRAM[12]), .CP(clk), .Q(
n9285) );
HS65_LL_DFPQX4 clk_r_REG681_S1 ( .D(Data_out_fromRAM[11]), .CP(clk), .Q(
n9284) );
HS65_LL_DFPQX4 clk_r_REG682_S1 ( .D(Data_out_fromRAM[10]), .CP(clk), .Q(
n9283) );
HS65_LL_DFPQX4 clk_r_REG683_S1 ( .D(Data_out_fromRAM[9]), .CP(clk), .Q(n9282) );
HS65_LL_DFPQX4 clk_r_REG684_S1 ( .D(Data_out_fromRAM[8]), .CP(clk), .Q(n9281) );
HS65_LL_DFPQX4 clk_r_REG688_S1 ( .D(Data_out_fromRAM[4]), .CP(clk), .Q(n9278) );
HS65_LL_DFPQX4 clk_r_REG689_S1 ( .D(Data_out_fromRAM[3]), .CP(clk), .Q(n9277) );
HS65_LL_DFPQX4 clk_r_REG690_S1 ( .D(Data_out_fromRAM[2]), .CP(clk), .Q(n9276) );
HS65_LL_DFPQX4 clk_r_REG691_S1 ( .D(Data_out_fromRAM[1]), .CP(clk), .Q(n9275) );
HS65_LL_DFPQX4 clk_r_REG692_S1 ( .D(Data_out_fromRAM[0]), .CP(clk), .Q(n9274) );
HS65_LL_DFPQX4 clk_r_REG446_S2 ( .D(n7902), .CP(clk), .Q(n9272) );
HS65_LL_DFPQX4 clk_r_REG337_S2 ( .D(\sub_x_53/A[25] ), .CP(clk), .Q(n9271)
);
HS65_LL_DFPQX4 clk_r_REG346_S1 ( .D(n7974), .CP(clk), .Q(n9270) );
HS65_LL_DFPQX4 clk_r_REG389_S1 ( .D(n8001), .CP(clk), .Q(n9269) );
HS65_LL_DFPQX4 clk_r_REG662_S1 ( .D(n8360), .CP(clk), .Q(n9268) );
HS65_LL_DFPQX4 clk_r_REG605_S1 ( .D(n8627), .CP(clk), .Q(n9267) );
HS65_LL_DFPQX4 clk_r_REG606_S2 ( .D(n9267), .CP(clk), .Q(n9266) );
HS65_LL_DFPQX4 clk_r_REG173_S1 ( .D(\u_DataPath/branch_target_i [27]), .CP(
clk), .Q(n9264) );
HS65_LL_DFPQX4 clk_r_REG116_S1 ( .D(\u_DataPath/branch_target_i [10]), .CP(
clk), .Q(n9263) );
HS65_LL_DFPQX4 clk_r_REG277_S3 ( .D(n2853), .CP(clk), .Q(n9260) );
HS65_LL_DFPQX4 clk_r_REG38_S2 ( .D(n2858), .CP(clk), .Q(n9259) );
HS65_LL_DFPQX4 clk_r_REG406_S3 ( .D(\sub_x_53/A[30] ), .CP(clk), .Q(n9258)
);
HS65_LL_DFPQX4 clk_r_REG412_S2 ( .D(\sub_x_53/A[27] ), .CP(clk), .Q(n9257)
);
HS65_LL_DFPQX4 clk_r_REG333_S2 ( .D(\lte_x_59/B[22] ), .CP(clk), .Q(n9256)
);
HS65_LL_DFPQX4 clk_r_REG110_S2 ( .D(\lte_x_59/B[9] ), .CP(clk), .Q(n9255) );
HS65_LL_DFPRQX4 clk_r_REG615_S1 ( .D(n7922), .CP(clk), .RN(n7879), .Q(n9254)
);
HS65_LL_DFPQX4 clk_r_REG452_S2 ( .D(n8578), .CP(clk), .Q(n9251) );
HS65_LL_DFPQX4 clk_r_REG433_S1 ( .D(\u_DataPath/branch_target_i [0]), .CP(
clk), .Q(n9250) );
HS65_LL_DFPQX4 clk_r_REG374_S2 ( .D(\u_DataPath/u_execute/link_value_i [2]),
.CP(clk), .Q(n9249) );
HS65_LL_DFPQX4 clk_r_REG649_S1 ( .D(n8402), .CP(clk), .Q(n9248) );
HS65_LL_DFPQX4 clk_r_REG651_S1 ( .D(n8447), .CP(clk), .Q(n9247) );
HS65_LL_DFPQX4 clk_r_REG661_S1 ( .D(n8370), .CP(clk), .Q(n9245) );
HS65_LL_DFPQX4 clk_r_REG655_S1 ( .D(n8376), .CP(clk), .Q(n9244) );
HS65_LL_DFPQX4 clk_r_REG659_S1 ( .D(n8335), .CP(clk), .Q(n9242) );
HS65_LL_DFPQX4 clk_r_REG354_S2 ( .D(\u_DataPath/mem_writedata_out_i [28]),
.CP(clk), .Q(n9241) );
HS65_LL_DFPRQX4 clk_r_REG513_S1 ( .D(n7898), .CP(clk), .RN(n9361), .Q(n9240)
);
HS65_LL_DFPQX4 clk_r_REG469_S4 ( .D(n7837), .CP(clk), .Q(n9239) );
HS65_LL_DFPQX4 clk_r_REG449_S1 ( .D(\u_DataPath/cw_memwb_i [0]), .CP(clk),
.Q(n9238) );
HS65_LL_DFPQX4 clk_r_REG484_S1 ( .D(\u_DataPath/cw_tomem_i [8]), .CP(clk),
.Q(n9237) );
HS65_LL_DFPQX4 clk_r_REG479_S1 ( .D(\u_DataPath/cw_tomem_i [7]), .CP(clk),
.Q(n9236) );
HS65_LL_DFPQX4 clk_r_REG510_S1 ( .D(\u_DataPath/cw_tomem_i [6]), .CP(clk),
.Q(n9235) );
HS65_LL_DFPQX4 clk_r_REG518_S1 ( .D(\u_DataPath/cw_tomem_i [0]), .CP(clk),
.Q(n9234) );
HS65_LL_DFPQX4 clk_r_REG473_S1 ( .D(\u_DataPath/jump_i ), .CP(clk), .Q(n9233) );
HS65_LL_DFPQX4 clk_r_REG266_S1 ( .D(\u_DataPath/pc_4_to_ex_i [11]), .CP(clk),
.Q(n9232) );
HS65_LL_DFPQX4 clk_r_REG259_S1 ( .D(\u_DataPath/pc_4_to_ex_i [12]), .CP(clk),
.Q(n9230) );
HS65_LL_DFPQX4 clk_r_REG313_S1 ( .D(\u_DataPath/pc_4_to_ex_i [8]), .CP(clk),
.Q(n9229) );
HS65_LL_DFPQX4 clk_r_REG126_S1 ( .D(\u_DataPath/pc_4_to_ex_i [13]), .CP(clk),
.Q(n9228) );
HS65_LL_DFPQX4 clk_r_REG319_S1 ( .D(\u_DataPath/pc_4_to_ex_i [7]), .CP(clk),
.Q(n9227) );
HS65_LL_DFPQX4 clk_r_REG132_S1 ( .D(\u_DataPath/pc_4_to_ex_i [14]), .CP(clk),
.Q(n9226) );
HS65_LL_DFPQX4 clk_r_REG308_S1 ( .D(\u_DataPath/pc_4_to_ex_i [6]), .CP(clk),
.Q(n9225) );
HS65_LL_DFPQX4 clk_r_REG251_S1 ( .D(\u_DataPath/pc_4_to_ex_i [15]), .CP(clk),
.Q(n9224) );
HS65_LL_DFPQX4 clk_r_REG327_S1 ( .D(\u_DataPath/pc_4_to_ex_i [5]), .CP(clk),
.Q(n9223) );
HS65_LL_DFPQX4 clk_r_REG244_S1 ( .D(\u_DataPath/pc_4_to_ex_i [16]), .CP(clk),
.Q(n9222) );
HS65_LL_DFPQX4 clk_r_REG237_S1 ( .D(\u_DataPath/pc_4_to_ex_i [17]), .CP(clk),
.Q(n9221) );
HS65_LL_DFPQX4 clk_r_REG216_S1 ( .D(\u_DataPath/pc_4_to_ex_i [18]), .CP(clk),
.Q(n9220) );
HS65_LL_DFPQX4 clk_r_REG299_S1 ( .D(\u_DataPath/pc_4_to_ex_i [4]), .CP(clk),
.Q(n9219) );
HS65_LL_DFPQX4 clk_r_REG224_S1 ( .D(\u_DataPath/pc_4_to_ex_i [19]), .CP(clk),
.Q(n9218) );
HS65_LL_DFPQX4 clk_r_REG229_S1 ( .D(\u_DataPath/pc_4_to_ex_i [20]), .CP(clk),
.Q(n9217) );
HS65_LL_DFPQX4 clk_r_REG5_S1 ( .D(\u_DataPath/pc_4_to_ex_i [3]), .CP(clk),
.Q(n9215) );
HS65_LL_DFPQX4 clk_r_REG120_S1 ( .D(\u_DataPath/pc_4_to_ex_i [10]), .CP(clk),
.Q(n9214) );
HS65_LL_DFPQX4 clk_r_REG156_S1 ( .D(\u_DataPath/pc_4_to_ex_i [22]), .CP(clk),
.Q(n9213) );
HS65_LL_DFPQX4 clk_r_REG367_S1 ( .D(\u_DataPath/u_execute/link_value_i [1]),
.CP(clk), .Q(n9212) );
HS65_LL_DFPQX4 clk_r_REG209_S1 ( .D(\u_DataPath/pc_4_to_ex_i [23]), .CP(clk),
.Q(n9210) );
HS65_LL_DFPQX4 clk_r_REG161_S1 ( .D(\u_DataPath/pc_4_to_ex_i [24]), .CP(clk),
.Q(n9209) );
HS65_LL_DFPQX4 clk_r_REG166_S1 ( .D(\u_DataPath/pc_4_to_ex_i [25]), .CP(clk),
.Q(n9208) );
HS65_LL_DFPQX4 clk_r_REG171_S1 ( .D(\u_DataPath/pc_4_to_ex_i [26]), .CP(clk),
.Q(n9207) );
HS65_LL_DFPQX4 clk_r_REG177_S1 ( .D(\u_DataPath/pc_4_to_ex_i [27]), .CP(clk),
.Q(n9206) );
HS65_LL_DFPQX4 clk_r_REG183_S1 ( .D(\u_DataPath/pc_4_to_ex_i [28]), .CP(clk),
.Q(n9205) );
HS65_LL_DFPQX4 clk_r_REG200_S1 ( .D(\u_DataPath/pc_4_to_ex_i [29]), .CP(clk),
.Q(n9204) );
HS65_LL_DFPQX4 clk_r_REG188_S1 ( .D(\u_DataPath/pc_4_to_ex_i [30]), .CP(clk),
.Q(n9203) );
HS65_LL_DFPQX4 clk_r_REG193_S1 ( .D(\u_DataPath/pc_4_to_ex_i [31]), .CP(clk),
.Q(n9202) );
HS65_LL_DFPQX4 clk_r_REG343_S3 ( .D(\lte_x_59/B[15] ), .CP(clk), .Q(n9200)
);
HS65_LL_DFPQX4 clk_r_REG203_S1 ( .D(\u_DataPath/branch_target_i [25]), .CP(
clk), .Q(n9199) );
HS65_LL_DFPQX4 clk_r_REG128_S1 ( .D(\u_DataPath/branch_target_i [14]), .CP(
clk), .Q(n9198) );
HS65_LL_DFPQX4 clk_r_REG210_S1 ( .D(\u_DataPath/branch_target_i [23]), .CP(
clk), .Q(n9197) );
HS65_LL_DFPQX4 clk_r_REG315_S1 ( .D(\u_DataPath/branch_target_i [7]), .CP(
clk), .Q(n9196) );
HS65_LL_DFPQX4 clk_r_REG240_S1 ( .D(\u_DataPath/branch_target_i [16]), .CP(
clk), .Q(n9194) );
HS65_LL_DFPQX4 clk_r_REG135_S1 ( .D(\u_DataPath/branch_target_i [21]), .CP(
clk), .Q(n9193) );
HS65_LL_DFPRQX4 clk_r_REG535_S1 ( .D(n7921), .CP(clk), .RN(n9354), .Q(n9191)
);
HS65_LL_DFPQX4 clk_r_REG468_S4 ( .D(n7904), .CP(clk), .Q(n9190) );
HS65_LL_DFPQX4 clk_r_REG471_S4 ( .D(n7903), .CP(clk), .Q(n9189) );
HS65_LL_DFPQX4 clk_r_REG462_S1 ( .D(n7882), .CP(clk), .Q(n9188) );
HS65_LL_DFPQX4 clk_r_REG472_S4 ( .D(n7907), .CP(clk), .Q(n9187) );
HS65_LL_DFPQX4 clk_r_REG602_S1 ( .D(n8629), .CP(clk), .Q(n9185) );
HS65_LL_DFPQX4 clk_r_REG603_S2 ( .D(n9185), .CP(clk), .Q(n9184) );
HS65_LL_DFPQX4 clk_r_REG599_S1 ( .D(n8631), .CP(clk), .Q(n9183) );
HS65_LL_DFPQX4 clk_r_REG600_S2 ( .D(n9183), .CP(clk), .Q(n9182) );
HS65_LL_DFPQX4 clk_r_REG608_S1 ( .D(n8623), .CP(clk), .Q(n9181) );
HS65_LL_DFPQX4 clk_r_REG609_S2 ( .D(n9181), .CP(clk), .Q(n9180) );
HS65_LL_DFPQX4 clk_r_REG588_S1 ( .D(\u_DataPath/u_idexreg/N31 ), .CP(clk),
.Q(n9179) );
HS65_LL_DFPQX4 clk_r_REG545_S1 ( .D(\u_DataPath/u_idexreg/N33 ), .CP(clk),
.Q(n9177) );
HS65_LL_DFPQX4 clk_r_REG546_S2 ( .D(n9177), .CP(clk), .Q(n9176) );
HS65_LL_DFPQX4 clk_r_REG542_S1 ( .D(\u_DataPath/immediate_ext_ex_i [7]),
.CP(clk), .Q(n9175) );
HS65_LL_DFPQX4 clk_r_REG543_S2 ( .D(n9175), .CP(clk), .Q(n9174) );
HS65_LL_DFPQX4 clk_r_REG548_S1 ( .D(\u_DataPath/immediate_ext_ex_i [9]),
.CP(clk), .Q(n9173) );
HS65_LL_DFPQX4 clk_r_REG549_S2 ( .D(n9173), .CP(clk), .Q(n9172) );
HS65_LL_DFPQX4 clk_r_REG552_S2 ( .D(n9171), .CP(clk), .Q(n9170) );
HS65_LL_DFPQX4 clk_r_REG571_S3 ( .D(n8162), .CP(clk), .Q(n9169) );
HS65_LL_DFPQX4 clk_r_REG527_S2 ( .D(n8070), .CP(clk), .Q(n9168) );
HS65_LL_DFPQX4 clk_r_REG509_S3 ( .D(n8055), .CP(clk), .Q(n9167) );
HS65_LL_DFPQX4 clk_r_REG685_S1 ( .D(n8302), .CP(clk), .Q(n9166) );
HS65_LL_DFPQX4 clk_r_REG194_S1 ( .D(\u_DataPath/branch_target_i [31]), .CP(
clk), .Q(n9165) );
HS65_LL_DFPQX4 clk_r_REG201_S1 ( .D(\u_DataPath/branch_target_i [29]), .CP(
clk), .Q(n9164) );
HS65_LL_DFPRQX4 clk_r_REG555_S2 ( .D(n7918), .CP(clk), .RN(n9356), .Q(n9153)
);
HS65_LL_DFPQX4 clk_r_REG442_S3 ( .D(n8054), .CP(clk), .Q(n9152) );
HS65_LL_DFPQX4 clk_r_REG464_S3 ( .D(\u_DataPath/cw_exmem_i [9]), .CP(clk),
.Q(n9151) );
HS65_LL_DFPQX4 clk_r_REG385_S3 ( .D(n8271), .CP(clk), .Q(n9150) );
HS65_LL_DFPQX4 clk_r_REG489_S3 ( .D(n8095), .CP(clk), .Q(n9149) );
HS65_LL_DFPQX4 clk_r_REG322_S1 ( .D(\u_DataPath/branch_target_i [4]), .CP(
clk), .Q(n9148) );
HS65_LL_DFPQX4 clk_r_REG611_S1 ( .D(n8625), .CP(clk), .Q(n9145) );
HS65_LL_DFPQX4 clk_r_REG612_S2 ( .D(n9145), .CP(clk), .Q(n9144) );
HS65_LL_DFPRQX4 clk_r_REG538_S2 ( .D(n7920), .CP(clk), .RN(n9355), .Q(n9141)
);
HS65_LL_DFPQX4 clk_r_REG448_S2 ( .D(n7914), .CP(clk), .Q(n9140) );
HS65_LL_DFPRQX4 clk_r_REG514_S1 ( .D(n7924), .CP(clk), .RN(n9354), .Q(n9138)
);
HS65_LL_DFPQX4 clk_r_REG470_S4 ( .D(n7849), .CP(clk), .Q(n9137) );
HS65_LL_DFPQX4 clk_r_REG461_S1 ( .D(n7881), .CP(clk), .Q(n9136) );
HS65_LL_DFPQX4 clk_r_REG467_S1 ( .D(n7908), .CP(clk), .Q(n9135) );
HS65_LL_DFPQX4 clk_r_REG460_S1 ( .D(n7883), .CP(clk), .Q(n9134) );
HS65_LL_DFPQX4 clk_r_REG459_S1 ( .D(n7884), .CP(clk), .Q(n9133) );
HS65_LL_DFPRQX4 clk_r_REG511_S1 ( .D(n7897), .CP(clk), .RN(n9355), .Q(n9131)
);
HS65_LL_DFPQX4 clk_r_REG647_S1 ( .D(n8420), .CP(clk), .Q(n9129) );
HS65_LL_DFPQX4 clk_r_REG383_S3 ( .D(n8299), .CP(clk), .Q(n9127) );
HS65_LL_DFPQX4 clk_r_REG666_S1 ( .D(n8365), .CP(clk), .Q(n9126) );
HS65_LL_DFPQX4 clk_r_REG672_S1 ( .D(n8454), .CP(clk), .Q(n9125) );
HS65_LL_DFPQX4 clk_r_REG670_S1 ( .D(n8324), .CP(clk), .Q(n9124) );
HS65_LL_DFPQX4 clk_r_REG664_S1 ( .D(n8351), .CP(clk), .Q(n9123) );
HS65_LL_DFPQX4 clk_r_REG676_S1 ( .D(n8356), .CP(clk), .Q(n9122) );
HS65_LL_DFPQX4 clk_r_REG674_S1 ( .D(n8406), .CP(clk), .Q(n9121) );
HS65_LL_DFPQX4 clk_r_REG668_S1 ( .D(n8410), .CP(clk), .Q(n9120) );
HS65_LL_DFPQX4 clk_r_REG447_S1 ( .D(n7899), .CP(clk), .Q(n9119) );
HS65_LL_DFPQX4 clk_r_REG45_S1 ( .D(\u_DataPath/u_execute/psw_status_i [1]),
.CP(clk), .Q(n9118) );
HS65_LL_DFPQX4 clk_r_REG373_S1 ( .D(\u_DataPath/pc_4_to_ex_i [2]), .CP(clk),
.Q(n9116) );
HS65_LL_DFPQX4 clk_r_REG430_S1 ( .D(\u_DataPath/u_execute/link_value_i [0]),
.CP(clk), .Q(n9115) );
HS65_LL_DFPQX4 clk_r_REG444_S1 ( .D(\u_DataPath/reg_write_i ), .CP(clk), .Q(
n9111) );
HS65_LL_DFPQX4 clk_r_REG465_S1 ( .D(\u_DataPath/cw_memwb_i [1]), .CP(clk),
.Q(n9110) );
HS65_LL_DFPQX4 clk_r_REG458_S1 ( .D(n7885), .CP(clk), .Q(n9109) );
HS65_LL_DFPRQX4 clk_r_REG191_S4 ( .D(\u_DataPath/pc_4_i [31]), .CP(clk),
.RN(n9361), .Q(n9108) );
HS65_LL_DFPQX4 clk_r_REG68_S2 ( .D(\sub_x_53/A[29] ), .CP(clk), .Q(n9107) );
HS65_LL_DFPQX4 clk_r_REG26_S3 ( .D(\lte_x_59/B[18] ), .CP(clk), .Q(n9106) );
HS65_LL_DFPQX4 clk_r_REG52_S2 ( .D(\lte_x_59/B[1] ), .CP(clk), .Q(n9105) );
HS65_LL_DFPQX4 clk_r_REG350_S2 ( .D(n3474), .CP(clk), .Q(n9104) );
HS65_LL_DFPQX4 clk_r_REG394_S3 ( .D(n8575), .CP(clk), .Q(n9103) );
HS65_LL_DFPQX4 clk_r_REG594_S3 ( .D(n8076), .CP(clk), .Q(n9102) );
HS65_LL_DFPQX4 clk_r_REG134_S2 ( .D(\u_DataPath/u_execute/link_value_i [14]),
.CP(clk), .Q(n9101) );
HS65_LL_DFPQX4 clk_r_REG301_S2 ( .D(\u_DataPath/u_execute/link_value_i [7]),
.CP(clk), .Q(n9100) );
HS65_LL_DFPQX4 clk_r_REG581_S3 ( .D(n8115), .CP(clk), .Q(n9099) );
HS65_LL_DFPQX4 clk_r_REG347_S3 ( .D(n2842), .CP(clk), .Q(n9096) );
HS65_LL_DFPQX4 clk_r_REG92_S2 ( .D(\sub_x_53/A[17] ), .CP(clk), .Q(n9094) );
HS65_LL_DFPQX4 clk_r_REG417_S2 ( .D(\lte_x_59/B[16] ), .CP(clk), .Q(n9093)
);
HS65_LL_DFPQX4 clk_r_REG10_S3 ( .D(\sub_x_53/A[0] ), .CP(clk), .Q(n9092) );
HS65_LL_DFPQX4 clk_r_REG403_S4 ( .D(\lte_x_59/B[8] ), .CP(clk), .Q(n9091) );
HS65_LL_DFPQX4 clk_r_REG32_S3 ( .D(n7867), .CP(clk), .Q(n9090) );
HS65_LL_DFPQX4 clk_r_REG107_S4 ( .D(\lte_x_59/B[21] ), .CP(clk), .Q(n9089)
);
HS65_LL_DFPQX4 clk_r_REG421_S3 ( .D(n3521), .CP(clk), .Q(n9088) );
HS65_LL_DFPRQX4 clk_r_REG181_S4 ( .D(\u_DataPath/pc_4_i [28]), .CP(clk),
.RN(n8677), .Q(n9087) );
HS65_LL_DFPQX4 clk_r_REG384_S3 ( .D(n8452), .CP(clk), .Q(n9086) );
HS65_LL_DFPQX4 clk_r_REG339_S1 ( .D(\u_DataPath/mem_writedata_out_i [25]),
.CP(clk), .Q(n9085) );
HS65_LL_DFPQX4 clk_r_REG508_S3 ( .D(n9084), .CP(clk), .Q(n9083) );
HS65_LL_DFPQX4 clk_r_REG375_S2 ( .D(\u_DataPath/u_execute/resAdd1_i [3]),
.CP(clk), .Q(n9080) );
HS65_LL_DFPQX4 clk_r_REG303_S2 ( .D(\u_DataPath/u_execute/link_value_i [6]),
.CP(clk), .Q(n9079) );
HS65_LL_DFPQX4 clk_r_REG503_S1 ( .D(\u_DataPath/regfile_addr_out_towb_i [2]),
.CP(clk), .Q(n9078) );
HS65_LL_DFPQX4 clk_r_REG530_S1 ( .D(\u_DataPath/idex_rt_i [3]), .CP(clk),
.Q(n9077) );
HS65_LL_DFPQX4 clk_r_REG501_S1 ( .D(\u_DataPath/regfile_addr_out_towb_i [0]),
.CP(clk), .Q(n9076) );
HS65_LL_DFPQX4 clk_r_REG497_S1 ( .D(\u_DataPath/regfile_addr_out_towb_i [3]),
.CP(clk), .Q(n9075) );
HS65_LL_DFPQX4 clk_r_REG85_S2 ( .D(n7855), .CP(clk), .Q(n9074) );
HS65_LL_DFPQX4 clk_r_REG79_S3 ( .D(n8458), .CP(clk), .Q(n9073) );
HS65_LL_DFPQX4 clk_r_REG108_S2 ( .D(n8474), .CP(clk), .Q(n9072) );
HS65_LL_DFPQX4 clk_r_REG100_S3 ( .D(\sub_x_53/A[23] ), .CP(clk), .Q(n9071)
);
HS65_LL_DFPRQX4 clk_r_REG175_S3 ( .D(\u_DataPath/pc_4_i [27]), .CP(clk),
.RN(n9361), .Q(n9070) );
HS65_LL_DFPQX4 clk_r_REG246_S2 ( .D(n7865), .CP(clk), .Q(n9065) );
HS65_LL_DFPQX4 clk_r_REG93_S2 ( .D(n7857), .CP(clk), .Q(n9063) );
HS65_LL_DFPQX4 clk_r_REG24_S2 ( .D(n7842), .CP(clk), .Q(n9062) );
HS65_LL_DFPQX4 clk_r_REG20_S2 ( .D(n7850), .CP(clk), .Q(n9061) );
HS65_LL_DFPQX4 clk_r_REG104_S3 ( .D(n7844), .CP(clk), .Q(n9060) );
HS65_LL_DFPQX4 clk_r_REG95_S3 ( .D(n8471), .CP(clk), .Q(n9059) );
HS65_LL_DFPQX4 clk_r_REG87_S2 ( .D(n8466), .CP(clk), .Q(n9058) );
HS65_LL_DFPQX4 clk_r_REG97_S4 ( .D(\sub_x_53/A[20] ), .CP(clk), .Q(n9056) );
HS65_LL_DFPQX4 clk_r_REG340_S4 ( .D(\lte_x_59/B[24] ), .CP(clk), .Q(n9055)
);
HS65_LL_DFPQX4 clk_r_REG167_S2 ( .D(\u_DataPath/u_execute/resAdd1_i [26]),
.CP(clk), .Q(n9054) );
HS65_LL_DFPQX4 clk_r_REG8_S2 ( .D(\lte_x_59/B[3] ), .CP(clk), .Q(n9053) );
HS65_LL_DFPQX4 clk_r_REG517_S2 ( .D(n8636), .CP(clk), .Q(n9052) );
HS65_LL_DFPQX4 clk_r_REG393_S3 ( .D(n8300), .CP(clk), .Q(n9051) );
HS65_LL_DFPQX4 clk_r_REG483_S3 ( .D(n8068), .CP(clk), .Q(n9050) );
HS65_LL_DFPQX4 clk_r_REG477_S3 ( .D(n8069), .CP(clk), .Q(n9049) );
HS65_LL_DFPQX4 clk_r_REG456_S3 ( .D(n8634), .CP(clk), .Q(n9048) );
HS65_LL_DFPQX4 clk_r_REG218_S2 ( .D(n5703), .CP(clk), .Q(n9047) );
HS65_LL_DFPQX4 clk_r_REG219_S2 ( .D(\u_DataPath/u_execute/link_value_i [20]),
.CP(clk), .Q(n9046) );
HS65_LL_DFPQX4 clk_r_REG115_S2 ( .D(\u_DataPath/u_execute/link_value_i [9]),
.CP(clk), .Q(n9045) );
HS65_LL_DFPQX4 clk_r_REG260_S2 ( .D(\u_DataPath/u_execute/link_value_i [12]),
.CP(clk), .Q(n9044) );
HS65_LL_DFPQX4 clk_r_REG267_S2 ( .D(n4006), .CP(clk), .Q(n9043) );
HS65_LL_DFPQX4 clk_r_REG330_S2 ( .D(\u_DataPath/u_execute/resAdd1_i [4]),
.CP(clk), .Q(n9041) );
HS65_LL_DFPQX4 clk_r_REG328_S2 ( .D(\u_DataPath/u_execute/link_value_i [5]),
.CP(clk), .Q(n9040) );
HS65_LL_DFPQX4 clk_r_REG567_S1 ( .D(\u_DataPath/immediate_ext_ex_i [2]),
.CP(clk), .Q(n9039) );
HS65_LL_DFPQX4 clk_r_REG568_S2 ( .D(n9039), .CP(clk), .Q(n9038) );
HS65_LL_DFPQX4 clk_r_REG579_S1 ( .D(\u_DataPath/immediate_ext_ex_i [1]),
.CP(clk), .Q(n9037) );
HS65_LL_DFPQX4 clk_r_REG580_S2 ( .D(n9037), .CP(clk), .Q(n9036) );
HS65_LL_DFPQX4 clk_r_REG586_S2 ( .D(n9035), .CP(clk), .Q(n9034) );
HS65_LL_DFPQX4 clk_r_REG574_S1 ( .D(\u_DataPath/immediate_ext_ex_i [3]),
.CP(clk), .Q(n9033) );
HS65_LL_DFPQX4 clk_r_REG575_S2 ( .D(n9033), .CP(clk), .Q(n9032) );
HS65_LL_DFPQX4 clk_r_REG505_S1 ( .D(\u_DataPath/regfile_addr_out_towb_i [1]),
.CP(clk), .Q(n9031) );
HS65_LL_DFPQX4 clk_r_REG592_S1 ( .D(\u_DataPath/immediate_ext_ex_i [5]),
.CP(clk), .Q(n9030) );
HS65_LL_DFPQX4 clk_r_REG593_S2 ( .D(n9030), .CP(clk), .Q(n9029) );
HS65_LL_DFPQX4 clk_r_REG73_S2 ( .D(n8477), .CP(clk), .Q(n9028) );
HS65_LL_DFPQX4 clk_r_REG63_S2 ( .D(n8469), .CP(clk), .Q(n9026) );
HS65_LL_DFPQX4 clk_r_REG195_S1 ( .D(\u_DataPath/branch_target_i [30]), .CP(
clk), .Q(n9025) );
HS65_LL_DFPQX4 clk_r_REG196_S2 ( .D(\u_DataPath/u_execute/resAdd1_i [29]),
.CP(clk), .Q(n9024) );
HS65_LL_DFPQX4 clk_r_REG178_S2 ( .D(\u_DataPath/u_execute/resAdd1_i [27]),
.CP(clk), .Q(n9023) );
HS65_LL_DFPQX4 clk_r_REG19_S2 ( .D(\lte_x_59/B[14] ), .CP(clk), .Q(n9022) );
HS65_LL_DFPQX4 clk_r_REG41_S3 ( .D(\sub_x_53/A[2] ), .CP(clk), .Q(n9021) );
HS65_LL_DFPQX4 clk_r_REG34_S1 ( .D(\u_DataPath/mem_writedata_out_i [8]),
.CP(clk), .Q(n9019) );
HS65_LL_DFPQX4 clk_r_REG388_S3 ( .D(\u_DataPath/mem_writedata_out_i [0]),
.CP(clk), .Q(n9018) );
HS65_LL_DFPQX4 clk_r_REG238_S2 ( .D(\u_DataPath/u_execute/link_value_i [17]),
.CP(clk), .Q(n9017) );
HS65_LL_DFPQX4 clk_r_REG463_S3 ( .D(n8059), .CP(clk), .Q(n9016) );
HS65_LL_DFPQX4 clk_r_REG127_S2 ( .D(\u_DataPath/u_execute/link_value_i [13]),
.CP(clk), .Q(n9015) );
HS65_LL_DFPQX4 clk_r_REG133_S2 ( .D(\u_DataPath/u_execute/link_value_i [15]),
.CP(clk), .Q(n9014) );
HS65_LL_DFPQX4 clk_r_REG271_S2 ( .D(\u_DataPath/u_execute/resAdd1_i [9]),
.CP(clk), .Q(n9013) );
HS65_LL_DFPQX4 clk_r_REG616_S1 ( .D(n8117), .CP(clk), .Q(n9012) );
HS65_LL_DFPQX4 clk_r_REG320_S2 ( .D(\u_DataPath/u_execute/resAdd1_i [7]),
.CP(clk), .Q(n9011) );
HS65_LL_DFPQX4 clk_r_REG300_S2 ( .D(\u_DataPath/u_execute/link_value_i [4]),
.CP(clk), .Q(n9008) );
HS65_LL_DFPQX4 clk_r_REG6_S2 ( .D(\u_DataPath/u_execute/link_value_i [3]),
.CP(clk), .Q(n9006) );
HS65_LL_DFPQX4 clk_r_REG566_S3 ( .D(n8121), .CP(clk), .Q(n9005) );
HS65_LL_DFPQX4 clk_r_REG558_S1 ( .D(\u_DataPath/rs_ex_i [3]), .CP(clk), .Q(
n9004) );
HS65_LL_DFPQX4 clk_r_REG572_S3 ( .D(n8096), .CP(clk), .Q(n9003) );
HS65_LL_DFPQX4 clk_r_REG30_S2 ( .D(n7859), .CP(clk), .Q(n9001) );
HS65_LL_DFPQX4 clk_r_REG148_S2 ( .D(\u_DataPath/u_execute/link_value_i [31]),
.CP(clk), .Q(n9000) );
HS65_LL_DFPQX4 clk_r_REG184_S2 ( .D(\u_DataPath/u_execute/resAdd1_i [30]),
.CP(clk), .Q(n8999) );
HS65_LL_DFPQX4 clk_r_REG179_S2 ( .D(\u_DataPath/u_execute/resAdd1_i [28]),
.CP(clk), .Q(n8998) );
HS65_LL_DFPQX4 clk_r_REG425_S2 ( .D(\lte_x_59/B[7] ), .CP(clk), .Q(n8997) );
HS65_LL_DFPQX4 clk_r_REG145_S2 ( .D(\u_DataPath/u_execute/link_value_i [27]),
.CP(clk), .Q(n8996) );
HS65_LL_DFPRQX4 clk_r_REG159_S4 ( .D(\u_DataPath/pc_4_i [24]), .CP(clk),
.RN(n8677), .Q(n8992) );
HS65_LL_DFPRQX4 clk_r_REG137_S3 ( .D(\u_DataPath/pc_4_i [21]), .CP(clk),
.RN(n9354), .Q(n8991) );
HS65_LL_DFPQX4 clk_r_REG162_S2 ( .D(\u_DataPath/u_execute/resAdd1_i [25]),
.CP(clk), .Q(n8990) );
HS65_LL_DFPRQX4 clk_r_REG207_S4 ( .D(\u_DataPath/pc_4_i [23]), .CP(clk),
.RN(n9361), .Q(n8989) );
HS65_LL_DFPQX4 clk_r_REG144_S2 ( .D(\u_DataPath/u_execute/link_value_i [25]),
.CP(clk), .Q(n8987) );
HS65_LL_DFPRQX4 clk_r_REG242_S3 ( .D(\u_DataPath/pc_4_i [16]), .CP(clk),
.RN(n8677), .Q(n8986) );
HS65_LL_DFPRQX4 clk_r_REG227_S3 ( .D(\u_DataPath/pc_4_i [20]), .CP(clk),
.RN(n9361), .Q(n8985) );
HS65_LL_DFPQX4 clk_r_REG143_S2 ( .D(\u_DataPath/u_execute/link_value_i [24]),
.CP(clk), .Q(n8983) );
HS65_LL_DFPQX4 clk_r_REG231_S2 ( .D(\u_DataPath/u_execute/resAdd1_i [19]),
.CP(clk), .Q(n8982) );
HS65_LL_DFPRQX4 clk_r_REG124_S3 ( .D(\u_DataPath/pc_4_i [13]), .CP(clk),
.RN(n9361), .Q(n8981) );
HS65_LL_DFPRQX4 clk_r_REG264_S3 ( .D(\u_DataPath/pc_4_i [11]), .CP(clk),
.RN(n9361), .Q(n8978) );
HS65_LL_DFPQX4 clk_r_REG205_S2 ( .D(\u_DataPath/u_execute/resAdd1_i [23]),
.CP(clk), .Q(n8977) );
HS65_LL_DFPQX4 clk_r_REG142_S2 ( .D(\u_DataPath/u_execute/link_value_i [23]),
.CP(clk), .Q(n8975) );
HS65_LL_DFPRQX4 clk_r_REG118_S3 ( .D(\u_DataPath/pc_4_i [10]), .CP(clk),
.RN(n2877), .Q(n8974) );
HS65_LL_DFPQX4 clk_r_REG217_S2 ( .D(n4288), .CP(clk), .Q(n8972) );
HS65_LL_DFPQX4 clk_r_REG522_S1 ( .D(\u_DataPath/rs_ex_i [0]), .CP(clk), .Q(
n8969) );
HS65_LL_DFPQX4 clk_r_REG524_S1 ( .D(\u_DataPath/idex_rt_i [4]), .CP(clk),
.Q(n8968) );
HS65_LL_DFPQX4 clk_r_REG554_S1 ( .D(\u_DataPath/idex_rt_i [2]), .CP(clk),
.Q(n8967) );
HS65_LL_DFPQX4 clk_r_REG532_S1 ( .D(\u_DataPath/idex_rt_i [1]), .CP(clk),
.Q(n8966) );
HS65_LL_DFPQX4 clk_r_REG578_S3 ( .D(n8092), .CP(clk), .Q(n8965) );
HS65_LL_DFPQX4 clk_r_REG565_S3 ( .D(n8089), .CP(clk), .Q(n8964) );
HS65_LL_DFPRQX4 clk_r_REG306_S3 ( .D(\u_DataPath/pc_4_i [6]), .CP(clk), .RN(
n9361), .Q(n8963) );
HS65_LL_DFPRQX4 clk_r_REG214_S3 ( .D(\u_DataPath/pc_4_i [18]), .CP(clk),
.RN(n2877), .Q(n8962) );
HS65_LL_DFPQX4 clk_r_REG443_S1 ( .D(n7833), .CP(clk), .Q(n8961) );
HS65_LL_DFPQX4 clk_r_REG499_S1 ( .D(\u_DataPath/regfile_addr_out_towb_i [4]),
.CP(clk), .Q(n8960) );
HS65_LL_DFPQX4 clk_r_REG232_S2 ( .D(\u_DataPath/u_execute/resAdd1_i [18]),
.CP(clk), .Q(n8958) );
HS65_LL_DFPQX4 clk_r_REG239_S2 ( .D(\u_DataPath/u_execute/resAdd1_i [17]),
.CP(clk), .Q(n8957) );
HS65_LL_DFPQX4 clk_r_REG230_S2 ( .D(\u_DataPath/u_execute/resAdd1_i [20]),
.CP(clk), .Q(n8956) );
HS65_LL_DFPQX4 clk_r_REG314_S2 ( .D(\u_DataPath/u_execute/resAdd1_i [8]),
.CP(clk), .Q(n8955) );
HS65_LL_DFPQX4 clk_r_REG329_S2 ( .D(\u_DataPath/u_execute/resAdd1_i [5]),
.CP(clk), .Q(n8954) );
HS65_LL_DFPQX4 clk_r_REG151_S2 ( .D(\u_DataPath/u_execute/resAdd1_i [21]),
.CP(clk), .Q(n8953) );
HS65_LL_DFPQX4 clk_r_REG254_S2 ( .D(\u_DataPath/u_execute/resAdd1_i [13]),
.CP(clk), .Q(n8952) );
HS65_LL_DFPQX4 clk_r_REG269_S2 ( .D(\u_DataPath/u_execute/resAdd1_i [10]),
.CP(clk), .Q(n8951) );
HS65_LL_DFPQX4 clk_r_REG252_S2 ( .D(\u_DataPath/u_execute/resAdd1_i [15]),
.CP(clk), .Q(n8949) );
HS65_LL_DFPQX4 clk_r_REG253_S2 ( .D(\u_DataPath/u_execute/resAdd1_i [14]),
.CP(clk), .Q(n8948) );
HS65_LL_DFPQX4 clk_r_REG302_S2 ( .D(\u_DataPath/u_execute/link_value_i [8]),
.CP(clk), .Q(n8947) );
HS65_LL_DFPQX4 clk_r_REG245_S2 ( .D(n5690), .CP(clk), .Q(n8946) );
HS65_LL_DFPQX4 clk_r_REG369_S2 ( .D(\u_DataPath/u_execute/resAdd1_i [2]),
.CP(clk), .Q(n8945) );
HS65_LL_DFPQX4 clk_r_REG560_S1 ( .D(\u_DataPath/rs_ex_i [1]), .CP(clk), .Q(
n8944) );
HS65_LL_DFPQX4 clk_r_REG520_S1 ( .D(\u_DataPath/rs_ex_i [2]), .CP(clk), .Q(
n8943) );
HS65_LL_DFPQX4 clk_r_REG534_S1 ( .D(\u_DataPath/idex_rt_i [0]), .CP(clk),
.Q(n8942) );
HS65_LL_DFPQX4 clk_r_REG202_S1 ( .D(\u_DataPath/branch_target_i [28]), .CP(
clk), .Q(n8941) );
HS65_LL_DFPQX4 clk_r_REG172_S1 ( .D(\u_DataPath/branch_target_i [26]), .CP(
clk), .Q(n8940) );
HS65_LL_DFPQX4 clk_r_REG140_S2 ( .D(n5169), .CP(clk), .Q(n8939) );
HS65_LL_DFPQX4 clk_r_REG141_S2 ( .D(n5698), .CP(clk), .Q(n8938) );
HS65_LL_DFPQX4 clk_r_REG432_S2 ( .D(\u_DataPath/u_execute/resAdd1_i [0]),
.CP(clk), .Q(n8937) );
HS65_LL_DFPQX4 clk_r_REG189_S2 ( .D(\u_DataPath/u_execute/resAdd1_i [31]),
.CP(clk), .Q(n8936) );
HS65_LL_DFPQX4 clk_r_REG157_S2 ( .D(\u_DataPath/u_execute/resAdd1_i [24]),
.CP(clk), .Q(n8934) );
HS65_LL_DFPQX4 clk_r_REG152_S2 ( .D(\u_DataPath/u_execute/resAdd1_i [22]),
.CP(clk), .Q(n8933) );
HS65_LL_DFPQX4 clk_r_REG453_S1 ( .D(
\u_DataPath/u_decode_unit/hdu_0/current_state [1]), .CP(clk), .Q(n8932) );
HS65_LL_DFPQX4 clk_r_REG204_S1 ( .D(\u_DataPath/branch_target_i [24]), .CP(
clk), .Q(n8931) );
HS65_LL_DFPQX4 clk_r_REG247_S1 ( .D(\u_DataPath/branch_target_i [15]), .CP(
clk), .Q(n8930) );
HS65_LL_DFPQX4 clk_r_REG233_S1 ( .D(\u_DataPath/branch_target_i [17]), .CP(
clk), .Q(n8928) );
HS65_LL_DFPQX4 clk_r_REG212_S1 ( .D(\u_DataPath/branch_target_i [18]), .CP(
clk), .Q(n8927) );
HS65_LL_DFPQX4 clk_r_REG225_S1 ( .D(\u_DataPath/branch_target_i [20]), .CP(
clk), .Q(n8926) );
HS65_LL_DFPQX4 clk_r_REG220_S1 ( .D(\u_DataPath/branch_target_i [19]), .CP(
clk), .Q(n8925) );
HS65_LL_DFPQX4 clk_r_REG379_S1 ( .D(\u_DataPath/branch_target_i [1]), .CP(
clk), .Q(n8924) );
HS65_LL_DFPQX4 clk_r_REG376_S1 ( .D(\u_DataPath/branch_target_i [2]), .CP(
clk), .Q(n8923) );
HS65_LL_DFPQX4 clk_r_REG323_S1 ( .D(\u_DataPath/branch_target_i [5]), .CP(
clk), .Q(n8922) );
HS65_LL_DFPQX4 clk_r_REG304_S1 ( .D(\u_DataPath/branch_target_i [6]), .CP(
clk), .Q(n8921) );
HS65_LL_DFPQX4 clk_r_REG309_S1 ( .D(\u_DataPath/branch_target_i [8]), .CP(
clk), .Q(n8920) );
HS65_LL_DFPQX4 clk_r_REG262_S1 ( .D(\u_DataPath/branch_target_i [11]), .CP(
clk), .Q(n8918) );
HS65_LL_DFPQX4 clk_r_REG255_S1 ( .D(\u_DataPath/branch_target_i [12]), .CP(
clk), .Q(n8917) );
HS65_LL_DFPQX4 clk_r_REG441_S3 ( .D(n8053), .CP(clk), .Q(n8916) );
HS65_LL_DFPQX4 clk_r_REG62_S1 ( .D(\u_DataPath/from_alu_data_out_i [28]),
.CP(clk), .Q(n8914) );
HS65_LL_DFPQX4 clk_r_REG596_S1 ( .D(\u_DataPath/immediate_ext_ex_i [4]),
.CP(clk), .Q(n8913) );
HS65_LL_DFPQX4 clk_r_REG597_S2 ( .D(n8913), .CP(clk), .Q(n8912) );
HS65_LL_DFPQX4 clk_r_REG457_S3 ( .D(\u_DataPath/cw_to_ex_i [20]), .CP(clk),
.Q(n8910) );
HS65_LL_DFPQX4 clk_r_REG77_S1 ( .D(\u_DataPath/from_alu_data_out_i [15]),
.CP(clk), .Q(n8909) );
HS65_LL_DFPQX4 clk_r_REG71_S1 ( .D(\u_DataPath/from_alu_data_out_i [10]),
.CP(clk), .Q(n8907) );
HS65_LL_DFPQX4 clk_r_REG445_S2 ( .D(n7306), .CP(clk), .Q(n8906) );
HS65_LL_DFPQX4 clk_r_REG355_S2 ( .D(\lte_x_59/B[28] ), .CP(clk), .Q(n8905)
);
HS65_LL_DFPQX4 clk_r_REG47_S3 ( .D(\u_DataPath/dataOut_exe_i [1]), .CP(clk),
.Q(n8904) );
HS65_LL_DFPQX4 clk_r_REG58_S4 ( .D(n8465), .CP(clk), .Q(n8903) );
HS65_LL_DFPQX4 clk_r_REG27_S3 ( .D(n8461), .CP(clk), .Q(n8902) );
HS65_LL_DFPQX4 clk_r_REG82_S2 ( .D(n8478), .CP(clk), .Q(n8900) );
HS65_LL_DFPQX4 clk_r_REG42_S3 ( .D(n7841), .CP(clk), .Q(n8899) );
HS65_LL_DFPQX4 clk_r_REG391_S3 ( .D(n8301), .CP(clk), .Q(n8898) );
HS65_LL_DFPQX4 clk_r_REG392_S3 ( .D(n8318), .CP(clk), .Q(n8897) );
HS65_LL_DFPQX4 clk_r_REG9_S2 ( .D(n7860), .CP(clk), .Q(n8896) );
HS65_LL_DFPQX4 clk_r_REG17_S2 ( .D(n8475), .CP(clk), .Q(n8895) );
HS65_LL_DFPQX4 clk_r_REG53_S3 ( .D(n8463), .CP(clk), .Q(n8893) );
HS65_LL_DFPQX4 clk_r_REG476_S3 ( .D(n8128), .CP(clk), .Q(n8892) );
HS65_LL_DFPQX4 clk_r_REG98_S2 ( .D(n8459), .CP(clk), .Q(n8891) );
HS65_LL_DFPQX4 clk_r_REG102_S2 ( .D(n8460), .CP(clk), .Q(n8890) );
HS65_LL_DFPQX4 clk_r_REG89_S3 ( .D(n8470), .CP(clk), .Q(n8889) );
HS65_LL_DFPQX4 clk_r_REG70_S2 ( .D(n8472), .CP(clk), .Q(n8888) );
HS65_LL_DFPQX4 clk_r_REG55_S3 ( .D(n8468), .CP(clk), .Q(n8887) );
HS65_LL_DFPQX4 clk_r_REG495_S3 ( .D(n8127), .CP(clk), .Q(n8886) );
HS65_LL_DFPQX4 clk_r_REG494_S3 ( .D(n8080), .CP(clk), .Q(n8885) );
HS65_LL_DFPQX4 clk_r_REG382_S3 ( .D(n8576), .CP(clk), .Q(n8884) );
HS65_LL_DFPQNX27 clk_r_REG1_S1 ( .D(\u_DataPath/u_exmemreg/N78 ), .CP(clk),
.QN(n7835) );
HS65_LL_DFPQX4 clk_r_REG35_S2 ( .D(n7839), .CP(clk), .Q(n8883) );
HS65_LL_DFPQX4 clk_r_REG69_S2 ( .D(n8437), .CP(clk), .Q(n8882) );
HS65_LL_DFPQX4 clk_r_REG57_S4 ( .D(\lte_x_59/B[5] ), .CP(clk), .Q(n8881) );
HS65_LL_DFPQX4 clk_r_REG390_S3 ( .D(n8401), .CP(clk), .Q(n8880) );
HS65_LL_DFPQX4 clk_r_REG294_S1 ( .D(\u_DataPath/mem_writedata_out_i [4]),
.CP(clk), .Q(n8879) );
HS65_LL_DFPQX4 clk_r_REG493_S3 ( .D(n8077), .CP(clk), .Q(n8878) );
HS65_LL_DFPQX4 clk_r_REG492_S3 ( .D(n8094), .CP(clk), .Q(n8877) );
HS65_LL_DFPQX4 clk_r_REG50_S1 ( .D(n8428), .CP(clk), .Q(n8875) );
HS65_LL_DFPQX4 clk_r_REG290_S2 ( .D(\u_DataPath/mem_writedata_out_i [19]),
.CP(clk), .Q(n8874) );
HS65_LL_DFPQX4 clk_r_REG398_S2 ( .D(\u_DataPath/mem_writedata_out_i [2]),
.CP(clk), .Q(n8873) );
HS65_LL_DFPQX4 clk_r_REG295_S2 ( .D(\lte_x_59/B[4] ), .CP(clk), .Q(n8872) );
HS65_LL_DFPQX4 clk_r_REG475_S3 ( .D(n8100), .CP(clk), .Q(n8871) );
HS65_LL_DFPQX4 clk_r_REG147_S2 ( .D(\u_DataPath/u_execute/link_value_i [30]),
.CP(clk), .Q(n8869) );
HS65_LL_DFPQX4 clk_r_REG487_S1 ( .D(n8450), .CP(clk), .Q(n8868) );
HS65_LL_DFPQX4 clk_r_REG332_S1 ( .D(\u_DataPath/data_read_ex_1_i [4]), .CP(
clk), .Q(n8867) );
HS65_LL_DFPQX4 clk_r_REG336_S1 ( .D(\u_DataPath/data_read_ex_2_i [22]), .CP(
clk), .Q(n8866) );
HS65_LL_DFPQX4 clk_r_REG349_S1 ( .D(\u_DataPath/data_read_ex_2_i [13]), .CP(
clk), .Q(n8865) );
HS65_LL_DFPQX4 clk_r_REG401_S1 ( .D(\u_DataPath/data_read_ex_2_i [11]), .CP(
clk), .Q(n8864) );
HS65_LL_DFPQX4 clk_r_REG274_S1 ( .D(\u_DataPath/data_read_ex_2_i [9]), .CP(
clk), .Q(n8863) );
HS65_LL_DFPQX4 clk_r_REG51_S1 ( .D(\u_DataPath/data_read_ex_1_i [1]), .CP(
clk), .Q(n8861) );
HS65_LL_DFPQX4 clk_r_REG404_S1 ( .D(\u_DataPath/data_read_ex_1_i [8]), .CP(
clk), .Q(n8860) );
HS65_LL_DFPQX4 clk_r_REG280_S1 ( .D(\u_DataPath/data_read_ex_1_i [26]), .CP(
clk), .Q(n8859) );
HS65_LL_DFPQX4 clk_r_REG439_S1 ( .D(\u_DataPath/data_read_ex_1_i [3]), .CP(
clk), .Q(n8858) );
HS65_LL_DFPQX4 clk_r_REG360_S1 ( .D(\u_DataPath/data_read_ex_1_i [6]), .CP(
clk), .Q(n8857) );
HS65_LL_DFPQX4 clk_r_REG422_S1 ( .D(\u_DataPath/data_read_ex_1_i [12]), .CP(
clk), .Q(n8856) );
HS65_LL_DFPQX4 clk_r_REG424_S1 ( .D(\u_DataPath/data_read_ex_1_i [7]), .CP(
clk), .Q(n8855) );
HS65_LL_DFPQX4 clk_r_REG288_S1 ( .D(\u_DataPath/data_read_ex_1_i [19]), .CP(
clk), .Q(n8854) );
HS65_LL_DFPQX4 clk_r_REG14_S2 ( .D(n8476), .CP(clk), .Q(n8853) );
HS65_LL_DFPQX4 clk_r_REG11_S3 ( .D(n8467), .CP(clk), .Q(n8852) );
HS65_LL_DFPQX4 clk_r_REG420_S1 ( .D(\u_DataPath/data_read_ex_1_i [14]), .CP(
clk), .Q(n8851) );
HS65_LL_DFPQX4 clk_r_REG348_S1 ( .D(\u_DataPath/data_read_ex_1_i [13]), .CP(
clk), .Q(n8850) );
HS65_LL_DFPQX4 clk_r_REG423_S1 ( .D(\u_DataPath/data_read_ex_2_i [12]), .CP(
clk), .Q(n8849) );
HS65_LL_DFPQX4 clk_r_REG362_S1 ( .D(\u_DataPath/data_read_ex_2_i [5]), .CP(
clk), .Q(n8847) );
HS65_LL_DFPQX4 clk_r_REG342_S1 ( .D(\u_DataPath/data_read_ex_1_i [24]), .CP(
clk), .Q(n8846) );
HS65_LL_DFPQX4 clk_r_REG335_S1 ( .D(\u_DataPath/data_read_ex_1_i [22]), .CP(
clk), .Q(n8845) );
HS65_LL_DFPQX4 clk_r_REG426_S1 ( .D(\u_DataPath/data_read_ex_2_i [7]), .CP(
clk), .Q(n8844) );
HS65_LL_DFPQX4 clk_r_REG414_S1 ( .D(\u_DataPath/data_read_ex_2_i [18]), .CP(
clk), .Q(n8843) );
HS65_LL_DFPQX4 clk_r_REG289_S1 ( .D(\u_DataPath/data_read_ex_2_i [19]), .CP(
clk), .Q(n8842) );
HS65_LL_DFPQX4 clk_r_REG411_S1 ( .D(\u_DataPath/data_read_ex_1_i [27]), .CP(
clk), .Q(n8841) );
HS65_LL_DFPQX4 clk_r_REG380_S1 ( .D(\u_DataPath/data_read_ex_2_i [1]), .CP(
clk), .Q(n8840) );
HS65_LL_DFPQX4 clk_r_REG281_S1 ( .D(\u_DataPath/data_read_ex_2_i [23]), .CP(
clk), .Q(n8839) );
HS65_LL_DFPQX4 clk_r_REG416_S1 ( .D(\u_DataPath/data_read_ex_1_i [16]), .CP(
clk), .Q(n8838) );
HS65_LL_DFPQX4 clk_r_REG291_S1 ( .D(\u_DataPath/data_read_ex_2_i [17]), .CP(
clk), .Q(n8837) );
HS65_LL_DFPQX4 clk_r_REG276_S1 ( .D(\u_DataPath/data_read_ex_1_i [21]), .CP(
clk), .Q(n8836) );
HS65_LL_DFPQX4 clk_r_REG359_S1 ( .D(\u_DataPath/data_read_ex_2_i [6]), .CP(
clk), .Q(n8835) );
HS65_LL_DFPQX4 clk_r_REG338_S1 ( .D(\u_DataPath/data_read_ex_2_i [25]), .CP(
clk), .Q(n8833) );
HS65_LL_DFPQX4 clk_r_REG397_S1 ( .D(\u_DataPath/data_read_ex_2_i [31]), .CP(
clk), .Q(n8832) );
HS65_LL_DFPQX4 clk_r_REG37_S1 ( .D(\u_DataPath/data_read_ex_1_i [11]), .CP(
clk), .Q(n8831) );
HS65_LL_DFPQX4 clk_r_REG405_S1 ( .D(\u_DataPath/data_read_ex_2_i [8]), .CP(
clk), .Q(n8830) );
HS65_LL_DFPQX4 clk_r_REG488_S3 ( .D(n8087), .CP(clk), .Q(n8829) );
HS65_LL_DFPQX4 clk_r_REG54_S3 ( .D(n7848), .CP(clk), .Q(n8828) );
HS65_LL_DFPRQX4 clk_r_REG192_S5 ( .D(\u_DataPath/pc4_to_idexreg_i [31]),
.CP(clk), .RN(n8676), .Q(n8827) );
HS65_LL_DFPQX4 clk_r_REG67_S1 ( .D(\u_DataPath/data_read_ex_1_i [29]), .CP(
clk), .Q(n8826) );
HS65_LL_DFPQX4 clk_r_REG286_S1 ( .D(\u_DataPath/data_read_ex_1_i [20]), .CP(
clk), .Q(n8825) );
HS65_LL_DFPQX4 clk_r_REG413_S1 ( .D(\u_DataPath/data_read_ex_1_i [18]), .CP(
clk), .Q(n8824) );
HS65_LL_DFPQX4 clk_r_REG396_S1 ( .D(\u_DataPath/data_read_ex_1_i [31]), .CP(
clk), .Q(n8823) );
HS65_LL_DFPQX4 clk_r_REG91_S1 ( .D(\u_DataPath/data_read_ex_1_i [17]), .CP(
clk), .Q(n8822) );
HS65_LL_DFPQX4 clk_r_REG357_S2 ( .D(\u_DataPath/data_read_ex_1_i [28]), .CP(
clk), .Q(n8821) );
HS65_LL_DFPRQX4 clk_r_REG610_S3 ( .D(\u_DataPath/immediate_ext_dec_i [15]),
.CP(clk), .RN(n9354), .Q(n8818) );
HS65_LL_DFPRQX4 clk_r_REG131_S4 ( .D(\u_DataPath/pc4_to_idexreg_i [14]),
.CP(clk), .RN(n8676), .Q(n8815) );
HS65_LL_DFPRQX4 clk_r_REG250_S4 ( .D(\u_DataPath/pc4_to_idexreg_i [15]),
.CP(clk), .RN(n9361), .Q(n8814) );
HS65_LL_DFPRQX4 clk_r_REG372_S3 ( .D(\u_DataPath/pc4_to_idexreg_i [2]), .CP(
clk), .RN(n2877), .Q(n8811) );
HS65_LL_DFPRQX4 clk_r_REG4_S3 ( .D(\u_DataPath/pc4_to_idexreg_i [3]), .CP(
clk), .RN(n9361), .Q(n8810) );
HS65_LL_DFPQX4 clk_r_REG88_S3 ( .D(n8462), .CP(clk), .Q(n8801) );
HS65_LL_DFPQX4 clk_r_REG273_S1 ( .D(\u_DataPath/data_read_ex_1_i [9]), .CP(
clk), .Q(n8800) );
HS65_LL_DFPQX4 clk_r_REG84_S1 ( .D(\u_DataPath/data_read_ex_1_i [25]), .CP(
clk), .Q(n8799) );
HS65_LL_DFPQX4 clk_r_REG400_S1 ( .D(\u_DataPath/data_read_ex_1_i [2]), .CP(
clk), .Q(n8798) );
HS65_LL_DFPRQX4 clk_r_REG199_S5 ( .D(\u_DataPath/pc4_to_idexreg_i [29]),
.CP(clk), .RN(n9361), .Q(n8796) );
HS65_LL_DFPRQX4 clk_r_REG236_S4 ( .D(\u_DataPath/pc4_to_idexreg_i [17]),
.CP(clk), .RN(n8676), .Q(n8795) );
HS65_LL_DFPQX4 clk_r_REG526_S2 ( .D(opcode_i[3]), .CP(clk), .Q(n8794) );
HS65_LL_DFPRQX4 clk_r_REG607_S3 ( .D(\u_DataPath/immediate_ext_dec_i [14]),
.CP(clk), .RN(n9354), .Q(n8791) );
HS65_LL_DFPRQX4 clk_r_REG601_S3 ( .D(\u_DataPath/immediate_ext_dec_i [12]),
.CP(clk), .RN(n9354), .Q(n8789) );
HS65_LL_DFPRQX4 clk_r_REG598_S3 ( .D(\u_DataPath/immediate_ext_dec_i [11]),
.CP(clk), .RN(n9354), .Q(n8788) );
HS65_LL_DFPRQX4 clk_r_REG595_S3 ( .D(\u_DataPath/immediate_ext_dec_i [4]),
.CP(clk), .RN(n9354), .Q(n8780) );
HS65_LL_DFPRQX4 clk_r_REG590_S3 ( .D(\u_DataPath/immediate_ext_dec_i [5]),
.CP(clk), .RN(n9354), .Q(n8779) );
HS65_LL_DFPRQX4 clk_r_REG587_S3 ( .D(\u_DataPath/immediate_ext_dec_i [6]),
.CP(clk), .RN(n9354), .Q(n8778) );
HS65_LL_DFPQX4 clk_r_REG584_S3 ( .D(\u_DataPath/immediate_ext_dec_i [0]),
.CP(clk), .Q(n8777) );
HS65_LL_DFPRQX4 clk_r_REG583_S3 ( .D(\u_DataPath/immediate_ext_dec_i [0]),
.CP(clk), .RN(n9354), .Q(n8776) );
HS65_LL_DFPQX4 clk_r_REG577_S3 ( .D(\u_DataPath/immediate_ext_dec_i [1]),
.CP(clk), .Q(n8775) );
HS65_LL_DFPRQX4 clk_r_REG576_S3 ( .D(\u_DataPath/immediate_ext_dec_i [1]),
.CP(clk), .RN(n9354), .Q(n8774) );
HS65_LL_DFPRQX4 clk_r_REG569_S3 ( .D(\u_DataPath/immediate_ext_dec_i [3]),
.CP(clk), .RN(n9354), .Q(n8772) );
HS65_LL_DFPQX4 clk_r_REG564_S3 ( .D(\u_DataPath/immediate_ext_dec_i [2]),
.CP(clk), .Q(n8771) );
HS65_LL_DFPRQX4 clk_r_REG563_S3 ( .D(\u_DataPath/immediate_ext_dec_i [2]),
.CP(clk), .RN(n9354), .Q(n8770) );
HS65_LL_DFPQX4 clk_r_REG491_S3 ( .D(n8099), .CP(clk), .Q(n8767) );
HS65_LL_DFPQX4 clk_r_REG504_S1 ( .D(\u_DataPath/RFaddr_out_memwb_i [1]),
.CP(clk), .Q(n8766) );
HS65_LL_DFPQX4 clk_r_REG502_S1 ( .D(\u_DataPath/RFaddr_out_memwb_i [2]),
.CP(clk), .Q(n8764) );
HS65_LL_DFPQX4 clk_r_REG500_S1 ( .D(\u_DataPath/RFaddr_out_memwb_i [0]),
.CP(clk), .Q(n8763) );
HS65_LL_DFPQX4 clk_r_REG498_S1 ( .D(\u_DataPath/RFaddr_out_memwb_i [4]),
.CP(clk), .Q(n8762) );
HS65_LL_DFPQX4 clk_r_REG496_S1 ( .D(\u_DataPath/RFaddr_out_memwb_i [3]),
.CP(clk), .Q(n8761) );
HS65_LL_DFPQX4 clk_r_REG78_S2 ( .D(n8309), .CP(clk), .Q(n8760) );
HS65_LL_DFPQX4 clk_r_REG352_S2 ( .D(n8296), .CP(clk), .Q(n8759) );
HS65_LL_DFPQX4 clk_r_REG386_S2 ( .D(n8169), .CP(clk), .Q(n8758) );
HS65_LL_DFPRQX4 clk_r_REG561_S3 ( .D(\u_DataPath/jaddr_i [25]), .CP(clk),
.RN(n9354), .Q(n8756) );
HS65_LL_DFPQX4 clk_r_REG486_S3 ( .D(\u_DataPath/cw_to_ex_i [17]), .CP(clk),
.Q(n8755) );
HS65_LL_DFPRQX4 clk_r_REG533_S2 ( .D(\u_DataPath/jaddr_i [16]), .CP(clk),
.RN(n9354), .Q(n8754) );
HS65_LL_DFPQX4 clk_r_REG351_S2 ( .D(n8181), .CP(clk), .Q(n8753) );
HS65_LL_DFPQX4 clk_r_REG344_S2 ( .D(n8305), .CP(clk), .Q(n8752) );
HS65_LL_DFPQX4 clk_r_REG481_S3 ( .D(n8057), .CP(clk), .Q(n8750) );
HS65_LL_DFPQX4 clk_r_REG65_S2 ( .D(\u_DataPath/mem_writedata_out_i [29]),
.CP(clk), .Q(n8749) );
HS65_LL_DFPQX4 clk_r_REG285_S2 ( .D(\u_DataPath/mem_writedata_out_i [20]),
.CP(clk), .Q(n8747) );
HS65_LL_DFPQX4 clk_r_REG106_S2 ( .D(\u_DataPath/mem_writedata_out_i [21]),
.CP(clk), .Q(n8746) );
HS65_LL_DFPQX4 clk_r_REG13_S2 ( .D(\u_DataPath/mem_writedata_out_i [7]),
.CP(clk), .Q(n8745) );
HS65_LL_DFPQX4 clk_r_REG381_S2 ( .D(\u_DataPath/mem_writedata_out_i [1]),
.CP(clk), .Q(n8744) );
HS65_LL_DFPQX4 clk_r_REG358_S2 ( .D(\u_DataPath/mem_writedata_out_i [6]),
.CP(clk), .Q(n8743) );
HS65_LL_DFPQX4 clk_r_REG75_S1 ( .D(\u_DataPath/mem_writedata_out_i [13]),
.CP(clk), .Q(n8742) );
HS65_LL_DFPQX4 clk_r_REG72_S1 ( .D(\u_DataPath/mem_writedata_out_i [10]),
.CP(clk), .Q(n8741) );
HS65_LL_DFPQX4 clk_r_REG418_S1 ( .D(\u_DataPath/mem_writedata_out_i [14]),
.CP(clk), .Q(n8739) );
HS65_LL_DFPQX4 clk_r_REG23_S1 ( .D(\u_DataPath/mem_writedata_out_i [16]),
.CP(clk), .Q(n8738) );
HS65_LL_DFPQX4 clk_r_REG415_S1 ( .D(\u_DataPath/mem_writedata_out_i [18]),
.CP(clk), .Q(n8737) );
HS65_LL_DFPQX4 clk_r_REG282_S1 ( .D(\u_DataPath/mem_writedata_out_i [23]),
.CP(clk), .Q(n8736) );
HS65_LL_DFPQX4 clk_r_REG402_S1 ( .D(\u_DataPath/mem_writedata_out_i [11]),
.CP(clk), .Q(n8735) );
HS65_LL_DFPQX4 clk_r_REG345_S1 ( .D(\u_DataPath/mem_writedata_out_i [15]),
.CP(clk), .Q(n8734) );
HS65_LL_DFPQX4 clk_r_REG278_S1 ( .D(\u_DataPath/mem_writedata_out_i [26]),
.CP(clk), .Q(n8733) );
HS65_LL_DFPQX4 clk_r_REG363_S1 ( .D(\u_DataPath/mem_writedata_out_i [5]),
.CP(clk), .Q(n8731) );
HS65_LL_DFPQX4 clk_r_REG16_S1 ( .D(\u_DataPath/mem_writedata_out_i [12]),
.CP(clk), .Q(n8730) );
HS65_LL_DFPQX4 clk_r_REG408_S1 ( .D(\u_DataPath/mem_writedata_out_i [30]),
.CP(clk), .Q(n8729) );
HS65_LL_DFPQX4 clk_r_REG44_S1 ( .D(\u_DataPath/mem_writedata_out_i [31]),
.CP(clk), .Q(n8728) );
HS65_LL_DFPQX4 clk_r_REG334_S1 ( .D(\u_DataPath/mem_writedata_out_i [22]),
.CP(clk), .Q(n8727) );
HS65_LL_DFPQX4 clk_r_REG272_S1 ( .D(\u_DataPath/mem_writedata_out_i [9]),
.CP(clk), .Q(n8726) );
HS65_LL_DFPQX4 clk_r_REG331_S1 ( .D(\u_DataPath/data_read_ex_2_i [4]), .CP(
clk), .Q(n8724) );
HS65_LL_DFPQX4 clk_r_REG419_S1 ( .D(\u_DataPath/data_read_ex_2_i [14]), .CP(
clk), .Q(n8723) );
HS65_LL_DFPQX4 clk_r_REG407_S1 ( .D(\u_DataPath/data_read_ex_2_i [30]), .CP(
clk), .Q(n8722) );
HS65_LL_DFPQX4 clk_r_REG410_S1 ( .D(\u_DataPath/data_read_ex_2_i [27]), .CP(
clk), .Q(n8721) );
HS65_LL_DFPQX4 clk_r_REG284_S1 ( .D(\u_DataPath/data_read_ex_2_i [20]), .CP(
clk), .Q(n8720) );
HS65_LL_DFPQX4 clk_r_REG66_S1 ( .D(\u_DataPath/data_read_ex_2_i [29]), .CP(
clk), .Q(n8719) );
HS65_LL_DFPQX4 clk_r_REG22_S1 ( .D(\u_DataPath/data_read_ex_2_i [16]), .CP(
clk), .Q(n8718) );
HS65_LL_DFPQX4 clk_r_REG275_S1 ( .D(\u_DataPath/data_read_ex_2_i [21]), .CP(
clk), .Q(n8717) );
HS65_LL_DFPQX4 clk_r_REG399_S1 ( .D(\u_DataPath/data_read_ex_2_i [2]), .CP(
clk), .Q(n8716) );
HS65_LL_DFPQX4 clk_r_REG49_S1 ( .D(\u_DataPath/u_execute/psw_status_i [0]),
.CP(clk), .Q(n8715) );
HS65_LL_DFPQX4 clk_r_REG480_S3 ( .D(n8102), .CP(clk), .Q(n8702) );
HS65_LL_DFPQX4 clk_r_REG474_S3 ( .D(n8081), .CP(clk), .Q(n8696) );
HS65_LH_IVX2 U3797 ( .A(n9330), .Z(n8676) );
HS65_LH_IVX2 U3799 ( .A(n9330), .Z(n8677) );
HS65_LH_IVX2 U5114 ( .A(n2877), .Z(n9330) );
HS65_LH_DFPHQX4 clk_r_REG190_S3 ( .D(n8641), .E(\u_DataPath/u_fetch/pc1/N3 ),
.CP(clk), .Q(n8713) );
HS65_LH_DFPRQX4 clk_r_REG537_S2 ( .D(n8482), .CP(clk), .RN(n9356), .Q(n9069)
);
HS65_LH_DFPRQX4 clk_r_REG428_S2 ( .D(n8691), .CP(clk), .RN(n8676), .Q(n8690)
);
HS65_LH_DFPRQX4 clk_r_REG365_S2 ( .D(n8689), .CP(clk), .RN(n9361), .Q(n8688)
);
HS65_LH_DFPRQX4 clk_r_REG646_S1 ( .D(iram_data[0]), .CP(clk), .RN(n9355),
.Q(n9303) );
HS65_LH_DFPRQX4 clk_r_REG645_S1 ( .D(iram_data[1]), .CP(clk), .RN(n9356),
.Q(n9304) );
HS65_LH_DFPRQX4 clk_r_REG644_S1 ( .D(iram_data[2]), .CP(clk), .RN(n9355),
.Q(n9305) );
HS65_LH_DFPRQX4 clk_r_REG643_S1 ( .D(iram_data[3]), .CP(clk), .RN(n9356),
.Q(n9306) );
HS65_LH_DFPRQX4 clk_r_REG642_S1 ( .D(iram_data[4]), .CP(clk), .RN(n9355),
.Q(n9307) );
HS65_LH_DFPRQX4 clk_r_REG641_S1 ( .D(iram_data[5]), .CP(clk), .RN(n9356),
.Q(n9308) );
HS65_LH_DFPRQX4 clk_r_REG640_S1 ( .D(iram_data[6]), .CP(clk), .RN(n9355),
.Q(n9309) );
HS65_LH_DFPRQX4 clk_r_REG638_S1 ( .D(iram_data[8]), .CP(clk), .RN(n9354),
.Q(n9311) );
HS65_LH_DFPRQX4 clk_r_REG637_S1 ( .D(iram_data[9]), .CP(clk), .RN(n9361),
.Q(n9312) );
HS65_LH_DFPRQX4 clk_r_REG635_S1 ( .D(iram_data[11]), .CP(clk), .RN(n9356),
.Q(n9314) );
HS65_LH_DFPRQX4 clk_r_REG634_S1 ( .D(iram_data[12]), .CP(clk), .RN(n9355),
.Q(n9315) );
HS65_LH_DFPRQX4 clk_r_REG633_S1 ( .D(iram_data[13]), .CP(clk), .RN(n9356),
.Q(n9316) );
HS65_LH_DFPRQX4 clk_r_REG632_S1 ( .D(iram_data[14]), .CP(clk), .RN(n9355),
.Q(n9317) );
HS65_LH_DFPRQX4 clk_r_REG631_S1 ( .D(iram_data[15]), .CP(clk), .RN(n9356),
.Q(n9318) );
HS65_LH_DFPRQX4 clk_r_REG630_S1 ( .D(iram_data[16]), .CP(clk), .RN(n9355),
.Q(n9319) );
HS65_LH_DFPRQX4 clk_r_REG629_S1 ( .D(iram_data[17]), .CP(clk), .RN(n9356),
.Q(n9320) );
HS65_LH_DFPRQX4 clk_r_REG628_S1 ( .D(iram_data[18]), .CP(clk), .RN(n9355),
.Q(n9321) );
HS65_LH_DFPRQX4 clk_r_REG627_S1 ( .D(iram_data[19]), .CP(clk), .RN(n9356),
.Q(n9322) );
HS65_LH_DFPRQX4 clk_r_REG626_S1 ( .D(iram_data[20]), .CP(clk), .RN(n9355),
.Q(n9323) );
HS65_LH_DFPRQX4 clk_r_REG625_S1 ( .D(iram_data[21]), .CP(clk), .RN(n9356),
.Q(n9324) );
HS65_LH_DFPRQX4 clk_r_REG624_S1 ( .D(iram_data[22]), .CP(clk), .RN(n9355),
.Q(n9325) );
HS65_LH_DFPRQX4 clk_r_REG623_S1 ( .D(iram_data[23]), .CP(clk), .RN(n9356),
.Q(n9326) );
HS65_LH_DFPRQX4 clk_r_REG622_S1 ( .D(iram_data[24]), .CP(clk), .RN(n9355),
.Q(n9327) );
HS65_LH_DFPRQX4 clk_r_REG621_S1 ( .D(iram_data[25]), .CP(clk), .RN(n9356),
.Q(n9328) );
HS65_LH_DFPRQX4 clk_r_REG620_S1 ( .D(iram_data[27]), .CP(clk), .RN(n9355),
.Q(n9329) );
HS65_LH_DFPRQX4 clk_r_REG619_S1 ( .D(iram_data[29]), .CP(clk), .RN(n9356),
.Q(n9331) );
HS65_LH_DFPRQX4 clk_r_REG544_S3 ( .D(\u_DataPath/immediate_ext_dec_i [8]),
.CP(clk), .RN(n8676), .Q(n8783) );
HS65_LH_DFPRQX4 clk_r_REG547_S3 ( .D(\u_DataPath/immediate_ext_dec_i [9]),
.CP(clk), .RN(n9361), .Q(n8782) );
HS65_LH_DFPRQX4 clk_r_REG155_S5 ( .D(n9429), .CP(clk), .RN(n9355), .Q(n9159)
);
HS65_LH_DFPRQX4 clk_r_REG138_S4 ( .D(n9428), .CP(clk), .RN(n9356), .Q(n9163)
);
HS65_LH_DFPRQX4 clk_r_REG516_S2 ( .D(opcode_i[5]), .CP(clk), .RN(n8676), .Q(
n8786) );
HS65_LH_DFPRQX4 clk_r_REG265_S4 ( .D(n9422), .CP(clk), .RN(n9361), .Q(n9158)
);
HS65_LH_DFPRQX4 clk_r_REG215_S4 ( .D(n9426), .CP(clk), .RN(n8676), .Q(n9156)
);
HS65_LH_DFPRQX4 clk_r_REG208_S5 ( .D(n9420), .CP(clk), .RN(n9361), .Q(n9161)
);
HS65_LH_DFPRQX4 clk_r_REG170_S5 ( .D(n9427), .CP(clk), .RN(n8676), .Q(n9155)
);
HS65_LH_DFPRQX4 clk_r_REG113_S5 ( .D(n9423), .CP(clk), .RN(n9361), .Q(n9157)
);
HS65_LH_DFPRQX4 clk_r_REG519_S2 ( .D(\u_DataPath/jaddr_i [23]), .CP(clk),
.RN(n9355), .Q(n8820) );
HS65_LH_DFPRQX4 clk_r_REG525_S2 ( .D(opcode_i[3]), .CP(clk), .RN(n9355), .Q(
n8793) );
HS65_LH_DFPRQX4 clk_r_REG528_S2 ( .D(opcode_i[1]), .CP(clk), .RN(n9356), .Q(
n8792) );
HS65_LH_DFPRQX4 clk_r_REG521_S2 ( .D(\u_DataPath/jaddr_i [21]), .CP(clk),
.RN(n9356), .Q(n8817) );
HS65_LH_DFPRQX4 clk_r_REG557_S3 ( .D(\u_DataPath/jaddr_i [24]), .CP(clk),
.RN(n9355), .Q(n8819) );
HS65_LH_DFPRQX4 clk_r_REG553_S3 ( .D(\u_DataPath/jaddr_i [18]), .CP(clk),
.RN(n9356), .Q(n8787) );
HS65_LH_DFPRQX4 clk_r_REG523_S2 ( .D(\u_DataPath/jaddr_i [20]), .CP(clk),
.RN(n9355), .Q(n8816) );
HS65_LH_DFPRQX4 clk_r_REG297_S4 ( .D(\u_DataPath/pc_4_i [4]), .CP(clk), .RN(
n8676), .Q(n9009) );
HS65_LH_DFPRQX4 clk_r_REG529_S2 ( .D(\u_DataPath/jaddr_i [19]), .CP(clk),
.RN(n9356), .Q(n8785) );
HS65_LH_DFPRQX4 clk_r_REG531_S2 ( .D(\u_DataPath/jaddr_i [17]), .CP(clk),
.RN(n9355), .Q(n8757) );
HS65_LH_DFPRQX4 clk_r_REG326_S4 ( .D(\u_DataPath/pc4_to_idexreg_i [5]), .CP(
clk), .RN(n9361), .Q(n8809) );
HS65_LH_DFPRQX4 clk_r_REG307_S4 ( .D(\u_DataPath/pc4_to_idexreg_i [6]), .CP(
clk), .RN(n8676), .Q(n8807) );
HS65_LH_DFPRQX4 clk_r_REG298_S5 ( .D(\u_DataPath/pc4_to_idexreg_i [4]), .CP(
clk), .RN(n9361), .Q(n8768) );
HS65_LH_DFPSQX4 clk_r_REG507_S2 ( .D(opcode_i[0]), .CP(clk), .SN(n7879), .Q(
n9084) );
HS65_LH_DFPSQX4 clk_r_REG455_S2 ( .D(opcode_i[2]), .CP(clk), .SN(n7879), .Q(
n9082) );
HS65_LH_DFPSQX4 clk_r_REG440_S2 ( .D(opcode_i[4]), .CP(clk), .SN(n7879), .Q(
n9068) );
HS65_LH_DFPHQX4 clk_r_REG427_S1 ( .D(\u_DataPath/pc_4_i [0]), .E(
\u_DataPath/u_fetch/pc1/N3 ), .CP(clk), .Q(n8691) );
HS65_LH_DFPHQX4 clk_r_REG370_S1 ( .D(n8670), .E(\u_DataPath/u_fetch/pc1/N3 ),
.CP(clk), .Q(n8687) );
HS65_LH_DFPHQX4 clk_r_REG364_S1 ( .D(\u_DataPath/pc_4_i [1]), .E(
\u_DataPath/u_fetch/pc1/N3 ), .CP(clk), .Q(n8689) );
HS65_LH_DFPHQX4 clk_r_REG324_S2 ( .D(n8667), .E(\u_DataPath/u_fetch/pc1/N3 ),
.CP(clk), .Q(n8684) );
HS65_LH_DFPHQX4 clk_r_REG316_S2 ( .D(n8665), .E(\u_DataPath/u_fetch/pc1/N3 ),
.CP(clk), .Q(n8682) );
HS65_LH_DFPHQX4 clk_r_REG310_S2 ( .D(n8664), .E(\u_DataPath/u_fetch/pc1/N3 ),
.CP(clk), .Q(n8680) );
HS65_LH_DFPHQX4 clk_r_REG305_S2 ( .D(n8666), .E(\u_DataPath/u_fetch/pc1/N3 ),
.CP(clk), .Q(n8683) );
HS65_LH_DFPHQX4 clk_r_REG296_S3 ( .D(n8668), .E(\u_DataPath/u_fetch/pc1/N3 ),
.CP(clk), .Q(n8685) );
HS65_LH_DFPHQX4 clk_r_REG263_S2 ( .D(n8661), .E(\u_DataPath/u_fetch/pc1/N3 ),
.CP(clk), .Q(n8679) );
HS65_LH_DFPHQX4 clk_r_REG117_S2 ( .D(n8662), .E(\u_DataPath/u_fetch/pc1/N3 ),
.CP(clk), .Q(n8681) );
HS65_LH_DFPHQX4 clk_r_REG111_S3 ( .D(n8663), .E(\u_DataPath/u_fetch/pc1/N3 ),
.CP(clk), .Q(n8678) );
HS65_LH_DFPHQX4 clk_r_REG2_S1 ( .D(n8669), .E(\u_DataPath/u_fetch/pc1/N3 ),
.CP(clk), .Q(n8686) );
HS65_LH_DFPHQX4 clk_r_REG256_S2 ( .D(n8660), .E(\u_DataPath/u_fetch/pc1/N3 ),
.CP(clk), .Q(n8695) );
HS65_LH_DFPHQX4 clk_r_REG129_S2 ( .D(n8658), .E(\u_DataPath/u_fetch/pc1/N3 ),
.CP(clk), .Q(n8694) );
HS65_LH_DFPHQX4 clk_r_REG123_S2 ( .D(n8659), .E(\u_DataPath/u_fetch/pc1/N3 ),
.CP(clk), .Q(n8698) );
HS65_LH_DFPHQX4 clk_r_REG213_S2 ( .D(n8654), .E(\u_DataPath/u_fetch/pc1/N3 ),
.CP(clk), .Q(n8693) );
HS65_LH_DFPHQX4 clk_r_REG168_S3 ( .D(n8646), .E(\u_DataPath/u_fetch/pc1/N3 ),
.CP(clk), .Q(n8701) );
HS65_LH_DFPHQX4 clk_r_REG248_S2 ( .D(n8657), .E(\u_DataPath/u_fetch/pc1/N3 ),
.CP(clk), .Q(n8699) );
HS65_LH_DFPHQX4 clk_r_REG174_S2 ( .D(n8645), .E(\u_DataPath/u_fetch/pc1/N3 ),
.CP(clk), .Q(n8703) );
HS65_LH_DFPHQX4 clk_r_REG241_S2 ( .D(n8656), .E(\u_DataPath/u_fetch/pc1/N3 ),
.CP(clk), .Q(n8704) );
HS65_LH_DFPHQX4 clk_r_REG221_S2 ( .D(n8653), .E(\u_DataPath/u_fetch/pc1/N3 ),
.CP(clk), .Q(n8692) );
HS65_LH_DFPHQX4 clk_r_REG163_S3 ( .D(n8647), .E(\u_DataPath/u_fetch/pc1/N3 ),
.CP(clk), .Q(n8700) );
HS65_LH_DFPHQX4 clk_r_REG226_S2 ( .D(n8652), .E(\u_DataPath/u_fetch/pc1/N3 ),
.CP(clk), .Q(n8697) );
HS65_LH_DFPHQX4 clk_r_REG180_S3 ( .D(n8644), .E(\u_DataPath/u_fetch/pc1/N3 ),
.CP(clk), .Q(n8707) );
HS65_LH_DFPHQX4 clk_r_REG234_S2 ( .D(n8655), .E(\u_DataPath/u_fetch/pc1/N3 ),
.CP(clk), .Q(n8709) );
HS65_LH_DFPHQX4 clk_r_REG153_S3 ( .D(n8650), .E(\u_DataPath/u_fetch/pc1/N3 ),
.CP(clk), .Q(n8708) );
HS65_LH_DFPHQX4 clk_r_REG197_S3 ( .D(n8643), .E(\u_DataPath/u_fetch/pc1/N3 ),
.CP(clk), .Q(n8710) );
HS65_LH_DFPHQX4 clk_r_REG206_S3 ( .D(n8649), .E(\u_DataPath/u_fetch/pc1/N3 ),
.CP(clk), .Q(n8706) );
HS65_LH_DFPHQX4 clk_r_REG158_S3 ( .D(n8648), .E(\u_DataPath/u_fetch/pc1/N3 ),
.CP(clk), .Q(n8711) );
HS65_LH_DFPHQX4 clk_r_REG185_S3 ( .D(n8642), .E(\u_DataPath/u_fetch/pc1/N3 ),
.CP(clk), .Q(n8712) );
HS65_LH_DFPHQX4 clk_r_REG136_S2 ( .D(n8651), .E(\u_DataPath/u_fetch/pc1/N3 ),
.CP(clk), .Q(n8705) );
HS65_LH_DFPQX4 clk_r_REG46_S2 ( .D(n9118), .CP(clk), .Q(n9117) );
HS65_LL_DFPQNX4 clk_r_REG466_S1 ( .D(n8048), .CP(clk), .QN(
\u_DataPath/cw_towb_i [1]) );
HS65_LH_DFPQX9 clk_r_REG436_S3 ( .D(nibble[0]), .CP(clk), .Q(n9128) );
HS65_LL_DFPRQX9 clk_r_REG613_S1 ( .D(n7923), .CP(clk), .RN(n9356), .Q(n9252)
);
HS65_LL_DFPQX9 clk_r_REG562_S1 ( .D(n8626), .CP(clk), .Q(n8911) );
HS65_LH_DFPQX9 clk_r_REG541_S3 ( .D(n8073), .CP(clk), .Q(n8751) );
HS65_LH_DFPQX9 clk_r_REG591_S3 ( .D(n8074), .CP(clk), .Q(n9002) );
HS65_LH_DFPQX9 clk_r_REG582_S3 ( .D(n8123), .CP(clk), .Q(n9146) );
HS65_LH_DFPQX9 clk_r_REG482_S4 ( .D(\u_DataPath/u_idexreg/N184 ), .CP(clk),
.Q(n8876) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[31][12] (
.G(\u_DataPath/u_decode_unit/reg_file0/N92 ), .D(n7968), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][12] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[31][14] (
.G(\u_DataPath/u_decode_unit/reg_file0/N92 ), .D(n7989), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][14] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[18][8] (
.G(\u_DataPath/u_decode_unit/reg_file0/N137 ), .D(n7939), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][8] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[26][28] (
.G(\u_DataPath/u_decode_unit/reg_file0/N129 ), .D(n7929), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][28] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[26][7] (
.G(\u_DataPath/u_decode_unit/reg_file0/N129 ), .D(n7950), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][7] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[30][13] (
.G(\u_DataPath/u_decode_unit/reg_file0/N125 ), .D(n7956), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][13] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[30][11] (
.G(\u_DataPath/u_decode_unit/reg_file0/N125 ), .D(n7941), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][11] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[28][30] (
.G(\u_DataPath/u_decode_unit/reg_file0/N127 ), .D(n8012), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][30] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[28][20] (
.G(\u_DataPath/u_decode_unit/reg_file0/N127 ), .D(n7959), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][20] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[28][24] (
.G(\u_DataPath/u_decode_unit/reg_file0/N127 ), .D(n7983), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][24] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[29][13] (
.G(\u_DataPath/u_decode_unit/reg_file0/N126 ), .D(n7957), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][13] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[28][14] (
.G(\u_DataPath/u_decode_unit/reg_file0/N127 ), .D(n7989), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][14] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[29][14] (
.G(\u_DataPath/u_decode_unit/reg_file0/N126 ), .D(n7990), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][14] ) );
HS65_LH_DFPQX4 clk_r_REG665_S1 ( .D(Data_out_fromRAM[21]), .CP(clk), .Q(
n9294) );
HS65_LH_DFPQX4 clk_r_REG687_S1 ( .D(Data_out_fromRAM[5]), .CP(clk), .Q(n9279) );
HS65_LH_DFPQX4 clk_r_REG287_S3 ( .D(n2849), .CP(clk), .Q(n9262) );
HS65_LH_DFPQX4 clk_r_REG653_S1 ( .D(n8417), .CP(clk), .Q(n9246) );
HS65_LH_DFPQX4 clk_r_REG114_S1 ( .D(\u_DataPath/pc_4_to_ex_i [9]), .CP(clk),
.Q(n9231) );
HS65_LH_DFPQX4 clk_r_REG139_S1 ( .D(\u_DataPath/pc_4_to_ex_i [21]), .CP(clk),
.Q(n9216) );
HS65_LH_DFPQX4 clk_r_REG101_S3 ( .D(n7838), .CP(clk), .Q(n9201) );
HS65_LH_DFPQX4 clk_r_REG353_S1 ( .D(n7947), .CP(clk), .Q(n9186) );
HS65_LH_DFPQX4 clk_r_REG551_S1 ( .D(\u_DataPath/immediate_ext_ex_i [10]),
.CP(clk), .Q(n9171) );
HS65_LH_DFPQX4 clk_r_REG377_S1 ( .D(\u_DataPath/branch_target_i [3]), .CP(
clk), .Q(n9147) );
HS65_LH_DFPQX4 clk_r_REG617_S1 ( .D(n8058), .CP(clk), .Q(n9130) );
HS65_LH_DFPQX4 clk_r_REG478_S1 ( .D(\u_DataPath/cw_tomem_i [5]), .CP(clk),
.Q(n9113) );
HS65_LH_DFPRQX9 clk_r_REG317_S3 ( .D(\u_DataPath/pc_4_i [7]), .CP(clk), .RN(
n9362), .Q(n9098) );
HS65_LH_DFPQX4 clk_r_REG261_S2 ( .D(\u_DataPath/u_execute/resAdd1_i [12]),
.CP(clk), .Q(n9064) );
HS65_LH_DFPQX4 clk_r_REG585_S1 ( .D(\u_DataPath/immediate_ext_ex_i [0]),
.CP(clk), .Q(n9035) );
HS65_LH_DFPQX4 clk_r_REG150_S2 ( .D(\u_DataPath/u_execute/link_value_i [26]),
.CP(clk), .Q(n9020) );
HS65_LH_DFPRQX4 clk_r_REG112_S4 ( .D(\u_DataPath/pc_4_i [9]), .CP(clk), .RN(
n2877), .Q(n8973) );
HS65_LH_DFPQX4 clk_r_REG321_S2 ( .D(\u_DataPath/u_execute/resAdd1_i [6]),
.CP(clk), .Q(n8959) );
HS65_LH_DFPQX4 clk_r_REG211_S1 ( .D(\u_DataPath/branch_target_i [22]), .CP(
clk), .Q(n8929) );
HS65_LH_DFPQX4 clk_r_REG485_S1 ( .D(\u_DataPath/cw_tomem_i [3]), .CP(clk),
.Q(n8915) );
HS65_LH_DFPQX4 clk_r_REG59_S1 ( .D(\u_DataPath/from_alu_data_out_i [6]),
.CP(clk), .Q(n8908) );
HS65_LH_DFPQNX4 clk_r_REG28_S1 ( .D(\u_DataPath/from_alu_data_out_i [27]),
.CP(clk), .QN(n3020) );
HS65_LH_DFPQX4 clk_r_REG39_S2 ( .D(n8464), .CP(clk), .Q(n8894) );
HS65_LH_DFPQX4 clk_r_REG283_S1 ( .D(\u_DataPath/data_read_ex_1_i [23]), .CP(
clk), .Q(n8848) );
HS65_LH_DFPQX4 clk_r_REG409_S1 ( .D(\u_DataPath/data_read_ex_1_i [30]), .CP(
clk), .Q(n8834) );
HS65_LH_DFPRQX4 clk_r_REG160_S5 ( .D(\u_DataPath/pc4_to_idexreg_i [24]),
.CP(clk), .RN(n9361), .Q(n8797) );
HS65_LH_DFPQX4 clk_r_REG570_S3 ( .D(\u_DataPath/immediate_ext_dec_i [3]),
.CP(clk), .Q(n8773) );
HS65_LH_DFPQX4 clk_r_REG292_S1 ( .D(\u_DataPath/mem_writedata_out_i [17]),
.CP(clk), .Q(n8740) );
HS65_LH_DFPQX4 clk_r_REG438_S1 ( .D(\u_DataPath/mem_writedata_out_i [3]),
.CP(clk), .Q(n8725) );
HS65_LH_DFPQX4 clk_r_REG506_S4 ( .D(\u_DataPath/cw_to_ex_i [15]), .CP(clk),
.Q(n8714) );
HS65_LH_DFPRQX9 clk_r_REG318_S4 ( .D(\u_DataPath/pc4_to_idexreg_i [7]), .CP(
clk), .RN(n9360), .Q(n8806) );
HS65_LH_DFPRQX9 clk_r_REG3_S2 ( .D(\u_DataPath/pc_4_i [3]), .CP(clk), .RN(
n9360), .Q(n8970) );
HS65_LH_DFPRQX9 clk_r_REG187_S5 ( .D(n9421), .CP(clk), .RN(n9360), .Q(n9143)
);
HS65_LH_DFPRQX9 clk_r_REG258_S4 ( .D(n9419), .CP(clk), .RN(n9360), .Q(n9265)
);
HS65_LH_DFPRQX9 clk_r_REG550_S3 ( .D(\u_DataPath/immediate_ext_dec_i [10]),
.CP(clk), .RN(n9360), .Q(n8781) );
HS65_LH_DFPRQX9 clk_r_REG371_S2 ( .D(\u_DataPath/pc_4_i [2]), .CP(clk), .RN(
n9360), .Q(n9273) );
HS65_LH_DFPRQX9 clk_r_REG223_S4 ( .D(\u_DataPath/pc4_to_idexreg_i [19]),
.CP(clk), .RN(n9360), .Q(n8813) );
HS65_LH_DFPRQX9 clk_r_REG165_S5 ( .D(\u_DataPath/pc4_to_idexreg_i [25]),
.CP(clk), .RN(n9360), .Q(n8802) );
HS65_LH_DFPRQX9 clk_r_REG119_S4 ( .D(\u_DataPath/pc4_to_idexreg_i [10]),
.CP(clk), .RN(n9360), .Q(n8804) );
HS65_LH_DFPRQX9 clk_r_REG325_S3 ( .D(\u_DataPath/pc_4_i [5]), .CP(clk), .RN(
n9360), .Q(n8971) );
HS65_LH_DFPRQX9 clk_r_REG311_S3 ( .D(\u_DataPath/pc_4_i [8]), .CP(clk), .RN(
n9360), .Q(n9010) );
HS65_LH_DFPRQX9 clk_r_REG130_S3 ( .D(\u_DataPath/pc_4_i [14]), .CP(clk),
.RN(n9360), .Q(n8984) );
HS65_LH_DFPRQX9 clk_r_REG249_S3 ( .D(\u_DataPath/pc_4_i [15]), .CP(clk),
.RN(n9360), .Q(n9097) );
HS65_LH_DFPRQX9 clk_r_REG164_S4 ( .D(\u_DataPath/pc_4_i [25]), .CP(clk),
.RN(n9360), .Q(n8980) );
HS65_LH_DFPRQX9 clk_r_REG198_S4 ( .D(\u_DataPath/pc_4_i [29]), .CP(clk),
.RN(n9360), .Q(n8993) );
HS65_LH_DFPRQX9 clk_r_REG536_S1 ( .D(n7921), .CP(clk), .RN(n9360), .Q(n9192)
);
HS65_LH_DFPRQX9 clk_r_REG515_S1 ( .D(n7924), .CP(clk), .RN(n9360), .Q(n9139)
);
HS65_LH_DFPRQX9 clk_r_REG556_S2 ( .D(n7918), .CP(clk), .RN(n9360), .Q(n9154)
);
HS65_LH_DFPRQX9 clk_r_REG636_S1 ( .D(iram_data[10]), .CP(clk), .RN(n9360),
.Q(n9313) );
HS65_LH_DFPRQX9 clk_r_REG312_S4 ( .D(\u_DataPath/pc4_to_idexreg_i [8]), .CP(
clk), .RN(n9362), .Q(n8805) );
HS65_LH_DFPRQX9 clk_r_REG429_S3 ( .D(\u_DataPath/pc4_to_idexreg_i [0]), .CP(
clk), .RN(n9362), .Q(n8862) );
HS65_LH_DFPRQX9 clk_r_REG182_S5 ( .D(n9425), .CP(clk), .RN(n9362), .Q(n9160)
);
HS65_LH_DFPRQX9 clk_r_REG243_S4 ( .D(n9424), .CP(clk), .RN(n9362), .Q(n9162)
);
HS65_LH_DFPRQX9 clk_r_REG540_S3 ( .D(\u_DataPath/immediate_ext_dec_i [7]),
.CP(clk), .RN(n9362), .Q(n8784) );
HS65_LH_DFPRQX9 clk_r_REG228_S4 ( .D(\u_DataPath/pc4_to_idexreg_i [20]),
.CP(clk), .RN(n9362), .Q(n8812) );
HS65_LH_DFPRQX9 clk_r_REG176_S4 ( .D(\u_DataPath/pc4_to_idexreg_i [27]),
.CP(clk), .RN(n9362), .Q(n8769) );
HS65_LH_DFPRQX9 clk_r_REG125_S4 ( .D(\u_DataPath/pc4_to_idexreg_i [13]),
.CP(clk), .RN(n9362), .Q(n8803) );
HS65_LH_DFPRQX9 clk_r_REG366_S3 ( .D(\u_DataPath/pc4_to_idexreg_i [1]), .CP(
clk), .RN(n9362), .Q(n8808) );
HS65_LH_DFPRQX9 clk_r_REG257_S3 ( .D(\u_DataPath/pc_4_i [12]), .CP(clk),
.RN(n9362), .Q(n9067) );
HS65_LH_DFPRQX9 clk_r_REG169_S4 ( .D(\u_DataPath/pc_4_i [26]), .CP(clk),
.RN(n9362), .Q(n8976) );
HS65_LH_DFPRQX9 clk_r_REG222_S3 ( .D(\u_DataPath/pc_4_i [19]), .CP(clk),
.RN(n9362), .Q(n8979) );
HS65_LH_DFPRQX9 clk_r_REG235_S3 ( .D(\u_DataPath/pc_4_i [17]), .CP(clk),
.RN(n9362), .Q(n8994) );
HS65_LH_DFPRQX9 clk_r_REG186_S4 ( .D(\u_DataPath/pc_4_i [30]), .CP(clk),
.RN(n9362), .Q(n8995) );
HS65_LH_DFPRQX9 clk_r_REG614_S1 ( .D(n7923), .CP(clk), .RN(n9362), .Q(n9253)
);
HS65_LH_DFPRQX9 clk_r_REG539_S2 ( .D(n7920), .CP(clk), .RN(n9362), .Q(n9142)
);
HS65_LH_DFPRQX9 clk_r_REG618_S1 ( .D(iram_data[31]), .CP(clk), .RN(n9362),
.Q(n9333) );
HS65_LH_DFPRQX9 clk_r_REG639_S1 ( .D(iram_data[7]), .CP(clk), .RN(n9362),
.Q(n9310) );
HS65_LL_IVX18 U3679 ( .A(\u_DataPath/cw_towb_i [1]), .Z(n3030) );
HS65_LH_IVX9 U4423 ( .A(n8968), .Z(n2947) );
HS65_LH_DFPQNX4 clk_r_REG33_S1 ( .D(\u_DataPath/from_alu_data_out_i [8]),
.CP(clk), .QN(n3212) );
HS65_LH_DFPQNX4 clk_r_REG109_S1 ( .D(\u_DataPath/from_alu_data_out_i [9]),
.CP(clk), .QN(n3079) );
HS65_LH_DFPQNX4 clk_r_REG434_S1 ( .D(n8621), .CP(clk), .QN(n3016) );
HS65_LL_DFPQNX4 clk_r_REG36_S1 ( .D(\u_DataPath/from_alu_data_out_i [11]),
.CP(clk), .QN(n3069) );
HS65_LH_DFPQNX4 clk_r_REG90_S1 ( .D(\u_DataPath/from_alu_data_out_i [17]),
.CP(clk), .QN(n3024) );
HS65_LH_DFPQNX4 clk_r_REG74_S1 ( .D(\u_DataPath/from_alu_data_out_i [13]),
.CP(clk), .QN(n3248) );
HS65_LH_CBI4I1X5 U3841 ( .A(n8801), .B(n8893), .C(n9189), .D(n8432), .Z(
\u_DataPath/dataOut_exe_i [3]) );
HS65_LH_IVX18 U4322 ( .A(n9401), .Z(n2866) );
HS65_LH_DFPQNX4 clk_r_REG15_S1 ( .D(\u_DataPath/from_alu_data_out_i [12]),
.CP(clk), .QN(n3259) );
HS65_LL_DFPQNX4 clk_r_REG437_S1 ( .D(\u_DataPath/data_read_ex_2_i [3]), .CP(
clk), .QN(n3309) );
HS65_LH_DFPQNX4 clk_r_REG43_S1 ( .D(\u_DataPath/from_alu_data_out_i [31]),
.CP(clk), .QN(n3406) );
HS65_LH_DFPQNX4 clk_r_REG21_S1 ( .D(\u_DataPath/from_alu_data_out_i [16]),
.CP(clk), .QN(n3093) );
HS65_LH_DFPQNX4 clk_r_REG86_S1 ( .D(\u_DataPath/from_alu_data_out_i [22]),
.CP(clk), .QN(n3166) );
HS65_LH_DFPQNX4 clk_r_REG18_S1 ( .D(\u_DataPath/from_alu_data_out_i [14]),
.CP(clk), .QN(n3088) );
HS65_LH_DFPQNX4 clk_r_REG31_S1 ( .D(\u_DataPath/from_alu_data_out_i [30]),
.CP(clk), .QN(n3047) );
HS65_LH_DFPQNX4 clk_r_REG94_S1 ( .D(\u_DataPath/from_alu_data_out_i [19]),
.CP(clk), .QN(n3185) );
HS65_LH_DFPQNX4 clk_r_REG96_S1 ( .D(\u_DataPath/from_alu_data_out_i [20]),
.CP(clk), .QN(n3175) );
HS65_LH_DFPQNX4 clk_r_REG293_S1 ( .D(n8579), .CP(clk), .QN(n2972) );
HS65_LH_DFPQNX4 clk_r_REG40_S1 ( .D(\u_DataPath/from_alu_data_out_i [2]),
.CP(clk), .QN(n2934) );
HS65_LH_DFPQNX4 clk_r_REG12_S1 ( .D(\u_DataPath/from_alu_data_out_i [7]),
.CP(clk), .QN(n3103) );
HS65_LH_DFPQNX4 clk_r_REG64_S1 ( .D(\u_DataPath/from_alu_data_out_i [29]),
.CP(clk), .QN(n2968) );
HS65_LH_DFPQNX4 clk_r_REG99_S1 ( .D(\u_DataPath/from_alu_data_out_i [23]),
.CP(clk), .QN(n3018) );
HS65_LH_DFPQNX4 clk_r_REG103_S1 ( .D(\u_DataPath/u_memwbreg/N64 ), .CP(clk),
.QN(n7877) );
HS65_LH_DFPQNX4 clk_r_REG105_S1 ( .D(\u_DataPath/from_alu_data_out_i [21]),
.CP(clk), .QN(n2956) );
HS65_LH_DFPQNX4 clk_r_REG80_S1 ( .D(\u_DataPath/from_alu_data_out_i [24]),
.CP(clk), .QN(n3137) );
HS65_LH_DFPQNX4 clk_r_REG7_S1 ( .D(\u_DataPath/from_alu_data_out_i [3]),
.CP(clk), .QN(n2970) );
HS65_LH_DFPQNX4 clk_r_REG56_S1 ( .D(\u_DataPath/from_alu_data_out_i [5]),
.CP(clk), .QN(n3332) );
HS65_LL_NAND2AX14 U3939 ( .A(n3289), .B(n2910), .Z(n5136) );
HS65_LL_IVX18 U4300 ( .A(n3082), .Z(n3341) );
HS65_LH_DFPQNX4 clk_r_REG25_S1 ( .D(\u_DataPath/from_alu_data_out_i [18]),
.CP(clk), .QN(n3084) );
HS65_LH_DFPQNX4 clk_r_REG83_S1 ( .D(\u_DataPath/from_alu_data_out_i [25]),
.CP(clk), .QN(n3098) );
HS65_LH_NAND3AX6 U3714 ( .A(n8507), .B(n9376), .C(n8508), .Z(n3245) );
HS65_LH_IVX9 U3930 ( .A(n2845), .Z(n2855) );
HS65_LL_DFPQNX4 clk_r_REG279_S1 ( .D(\u_DataPath/data_read_ex_2_i [26]),
.CP(clk), .QN(n3152) );
HS65_LL_DFPQNX4 clk_r_REG341_S1 ( .D(\u_DataPath/data_read_ex_2_i [24]),
.CP(clk), .QN(n3143) );
HS65_LL_DFPQNX4 clk_r_REG361_S1 ( .D(\u_DataPath/data_read_ex_1_i [5]), .CP(
clk), .QN(n3335) );
HS65_LL_DFPQNX4 clk_r_REG356_S2 ( .D(\u_DataPath/data_read_ex_2_i [28]),
.CP(clk), .QN(n3128) );
HS65_LH_NAND2AX7 U4801 ( .A(n3058), .B(n2916), .Z(n4726) );
HS65_LL_AOI21X2 U6685 ( .A(n4175), .B(n3237), .C(n3066), .Z(n3067) );
HS65_LL_NAND2AX7 U3938 ( .A(n3068), .B(n3067), .Z(\sub_x_53/A[0] ) );
HS65_LL_NOR2AX6 U6694 ( .A(n2913), .B(n3295), .Z(\sub_x_53/A[2] ) );
HS65_LL_NOR2X6 U5629 ( .A(n3139), .B(n3138), .Z(\lte_x_59/B[24] ) );
HS65_LL_IVX18 U3931 ( .A(n2845), .Z(n2856) );
HS65_LL_IVX9 U4762 ( .A(n2855), .Z(n4587) );
HS65_LH_IVX9 U3929 ( .A(n3432), .Z(n5004) );
HS65_LH_NOR2X9 U3955 ( .A(n3474), .B(n5104), .Z(n3990) );
HS65_LH_IVX9 U4755 ( .A(\lte_x_59/B[24] ), .Z(n4981) );
HS65_LH_IVX9 U7378 ( .A(\lte_x_59/B[3] ), .Z(n5320) );
HS65_LH_OAI12X3 U5426 ( .A(n3101), .B(n4795), .C(n3964), .Z(n4256) );
HS65_LH_IVX9 U3607 ( .A(n4836), .Z(n4581) );
HS65_LH_OAI12X3 U5416 ( .A(n2854), .B(n4795), .C(n3719), .Z(n4500) );
HS65_LH_OAI12X3 U3713 ( .A(n4084), .B(n4081), .C(n4083), .Z(n4927) );
HS65_LH_IVX9 U5614 ( .A(n7623), .Z(n7627) );
HS65_LH_AOI21X2 U4124 ( .A(n3474), .B(n4587), .C(n3672), .Z(n3673) );
HS65_LL_AND2X4 U3674 ( .A(n3356), .B(n3355), .Z(n3357) );
HS65_LH_OAI12X3 U5525 ( .A(n4846), .B(n3558), .C(n3559), .Z(n5260) );
HS65_LH_AOI21X2 U4105 ( .A(n2842), .B(n4587), .C(n3955), .Z(n3760) );
HS65_LL_NOR2X6 U4183 ( .A(n2851), .B(n7627), .Z(n5342) );
HS65_LH_AOI21X2 U7697 ( .A(n6035), .B(n5924), .C(n5923), .Z(n5925) );
HS65_LH_IVX9 U4764 ( .A(n5201), .Z(n5131) );
HS65_LL_NOR2X6 U4758 ( .A(n3818), .B(n4863), .Z(n5144) );
HS65_LL_NOR2AX6 U5259 ( .A(n2867), .B(n3501), .Z(n5210) );
HS65_LL_AOI21X2 U3893 ( .A(n4836), .B(n4491), .C(n4490), .Z(n4938) );
HS65_LL_AOI21X2 U3962 ( .A(n4836), .B(n4840), .C(n4433), .Z(n4473) );
HS65_LH_AOI21X2 U4039 ( .A(n5672), .B(n3598), .C(n3597), .Z(n3608) );
HS65_LHS_XNOR2X3 U7745 ( .A(\u_DataPath/jaddr_i [22]), .B(n8966), .Z(n7104)
);
HS65_LL_XNOR2X4 U3786 ( .A(n8164), .B(n7086), .Z(n7080) );
HS65_LHS_XNOR2X3 U7689 ( .A(n8165), .B(n2847), .Z(n7076) );
HS65_LHS_XNOR2X3 U7663 ( .A(\u_DataPath/jaddr_i [18]), .B(n2847), .Z(n7085)
);
HS65_LH_DFPQNX9 clk_r_REG454_S1 ( .D(
\u_DataPath/u_decode_unit/hdu_0/current_state [0]), .CP(clk), .QN(
n7613) );
HS65_LH_NOR2X6 U7651 ( .A(n6150), .B(n6139), .Z(n6634) );
HS65_LH_NOR2X6 U3759 ( .A(n6150), .B(n6149), .Z(n6384) );
HS65_LH_NOR2AX3 U6856 ( .A(n8729), .B(n3115), .Z(n2995) );
HS65_LH_NOR2AX3 U3681 ( .A(n8736), .B(n2994), .Z(n8671) );
HS65_LH_NOR2AX3 U3683 ( .A(n8737), .B(n2994), .Z(n8673) );
HS65_LH_NOR2AX3 U3693 ( .A(n8727), .B(n2994), .Z(n8672) );
HS65_LH_NOR2AX3 U3701 ( .A(n8874), .B(n2994), .Z(n3013) );
HS65_LH_NOR2AX3 U3691 ( .A(\u_DataPath/dataOut_exe_i [11]), .B(n2986), .Z(
n2993) );
HS65_LH_NOR2AX3 U6775 ( .A(\u_DataPath/dataOut_exe_i [21]), .B(n3116), .Z(
n3001) );
HS65_LH_NOR2AX3 U6769 ( .A(\u_DataPath/dataOut_exe_i [22]), .B(n3116), .Z(
n2989) );
HS65_LH_NOR2AX3 U6770 ( .A(\u_DataPath/dataOut_exe_i [25]), .B(n3116), .Z(
n2987) );
HS65_LH_NOR2AX3 U6774 ( .A(\u_DataPath/dataOut_exe_i [24]), .B(n3116), .Z(
n3004) );
HS65_LH_NOR2AX3 U6777 ( .A(\u_DataPath/dataOut_exe_i [20]), .B(n3116), .Z(
n3000) );
HS65_LH_NOR2AX3 U6779 ( .A(\u_DataPath/dataOut_exe_i [30]), .B(n3116), .Z(
n3002) );
HS65_LH_AOI21X2 U6280 ( .A(n5284), .B(n5285), .C(n4302), .Z(n7839) );
HS65_LL_NAND2X7 U3946 ( .A(n3204), .B(n3203), .Z(n5001) );
HS65_LL_AOI12X2 U4319 ( .A(n6109), .B(n6111), .C(n5940), .Z(n6029) );
HS65_LH_NOR2AX3 U6857 ( .A(n8749), .B(n3115), .Z(n2999) );
HS65_LH_NOR2AX3 U6860 ( .A(n9241), .B(n3115), .Z(n2996) );
HS65_LH_IVX9 U3434 ( .A(n8698), .Z(n9357) );
HS65_LL_NOR2X6 U3437 ( .A(n6153), .B(n6149), .Z(n6317) );
HS65_LL_AOI21X2 U3446 ( .A(\lte_x_59/B[18] ), .B(n4588), .C(n3954), .Z(n4258) );
HS65_LL_NOR2X6 U3447 ( .A(n5152), .B(n4581), .Z(n4942) );
HS65_LH_IVX18 U3448 ( .A(n5173), .Z(n5667) );
HS65_LL_NAND2X7 U3465 ( .A(n4949), .B(n3426), .Z(n5173) );
HS65_LL_OAI21X3 U3499 ( .A(n8427), .B(n9401), .C(n3135), .Z(n8554) );
HS65_LL_IVX18 U3508 ( .A(n2893), .Z(n4351) );
HS65_LL_NOR2X2 U3509 ( .A(n9401), .B(n8311), .Z(n8498) );
HS65_LL_MUXI21X2 U3511 ( .D0(n2934), .D1(n2933), .S0(
\u_DataPath/cw_towb_i [0]), .Z(n8488) );
HS65_LL_IVX18 U3512 ( .A(n9376), .Z(n4713) );
HS65_LL_IVX18 U3516 ( .A(n3119), .Z(addr_to_iram[24]) );
HS65_LH_IVX40 U3526 ( .A(n9357), .Z(addr_to_iram[11]) );
HS65_LL_NAND2X7 U3538 ( .A(\u_DataPath/dataOut_exe_i [0]), .B(n3114), .Z(
n8270) );
HS65_LL_AOI12X9 U3540 ( .A(n5858), .B(n5860), .C(n5741), .Z(n5854) );
HS65_LL_NOR2X6 U3547 ( .A(n6153), .B(n6132), .Z(n6624) );
HS65_LL_OAI21X12 U3555 ( .A(n5743), .B(n5746), .C(n5745), .Z(n5860) );
HS65_LL_AOI21X6 U3567 ( .A(n5285), .B(n3514), .C(n3513), .Z(n8479) );
HS65_LL_NOR2AX3 U3570 ( .A(n5225), .B(n5224), .Z(n8458) );
HS65_LL_NAND3X5 U3571 ( .A(n4416), .B(n2900), .C(n4415), .Z(n5166) );
HS65_LL_AND3X4 U3572 ( .A(n4406), .B(n4405), .C(n4404), .Z(n2900) );
HS65_LL_NAND2X7 U3575 ( .A(\u_DataPath/jaddr_i [23]), .B(n6131), .Z(n6132)
);
HS65_LL_AOI21X6 U3581 ( .A(n5285), .B(n4963), .C(n4962), .Z(n8475) );
HS65_LH_NAND4ABX3 U3582 ( .A(n3845), .B(n3844), .C(n3843), .D(n3842), .Z(
n3851) );
HS65_LH_OAI21X3 U3584 ( .A(n5462), .B(n5461), .C(n5460), .Z(n5498) );
HS65_LL_AOI21X2 U3585 ( .A(n5234), .B(n3610), .C(n3609), .Z(n3611) );
HS65_LL_OAI12X3 U3587 ( .A(n2859), .B(n4324), .C(n4323), .Z(n4325) );
HS65_LL_NOR4ABX2 U3591 ( .A(n4959), .B(n4958), .C(n4957), .D(n4956), .Z(
n4960) );
HS65_LL_NOR2AX3 U3593 ( .A(n5253), .B(n5252), .Z(n5268) );
HS65_LH_AOI21X2 U3603 ( .A(n5667), .B(n5666), .C(n5665), .Z(n5668) );
HS65_LH_AOI21X2 U3606 ( .A(n5667), .B(n4184), .C(n4183), .Z(n4202) );
HS65_LH_OAI12X3 U3623 ( .A(n3246), .B(n3815), .C(n3950), .Z(n3951) );
HS65_LH_NOR2AX3 U3624 ( .A(n5217), .B(n4936), .Z(n4961) );
HS65_LH_NAND3X3 U3627 ( .A(n3608), .B(n2930), .C(n3607), .Z(n3609) );
HS65_LH_AOI21X2 U3629 ( .A(n5618), .B(n4389), .C(n3600), .Z(n2930) );
HS65_LL_OAI21X2 U3630 ( .A(n7634), .B(n9339), .C(n4126), .Z(n4139) );
HS65_LH_AOI21X2 U3631 ( .A(n5667), .B(n5644), .C(n3784), .Z(n3785) );
HS65_LL_NOR2AX3 U3633 ( .A(n5636), .B(n5635), .Z(n5637) );
HS65_LL_AOI21X2 U3636 ( .A(n4480), .B(n4645), .C(n4102), .Z(n4103) );
HS65_LH_AOI21X2 U3638 ( .A(n5667), .B(n5203), .C(n4434), .Z(n4444) );
HS65_LH_AOI21X2 U3641 ( .A(n5618), .B(n5174), .C(n4436), .Z(n4443) );
HS65_LL_AOI21X2 U3643 ( .A(n5629), .B(n3379), .C(n3378), .Z(n3380) );
HS65_LL_AOI21X2 U3645 ( .A(n6123), .B(n5671), .C(n4168), .Z(n4169) );
HS65_LL_AOI21X2 U3651 ( .A(n4259), .B(n4258), .C(n4581), .Z(n4261) );
HS65_LL_NOR4ABX4 U3655 ( .A(n4125), .B(n4124), .C(n4123), .D(n4122), .Z(
n4126) );
HS65_LH_AOI21X2 U3659 ( .A(n3893), .B(n5294), .C(n5406), .Z(n5521) );
HS65_LL_AOI21X2 U3663 ( .A(\sub_x_53/A[20] ), .B(n4544), .C(n3953), .Z(n4259) );
HS65_LL_NOR2X6 U3664 ( .A(n4965), .B(n3416), .Z(n5285) );
HS65_LH_AOI21X2 U3667 ( .A(\lte_x_59/B[22] ), .B(n4588), .C(n3779), .Z(n3780) );
HS65_LH_NAND3X5 U3669 ( .A(n3837), .B(n3436), .C(n3435), .Z(n5170) );
HS65_LH_AOI21X2 U3672 ( .A(n5667), .B(n5658), .C(n4166), .Z(n4167) );
HS65_LL_CNIVX7 U3678 ( .A(n5249), .Z(n5672) );
HS65_LL_AND2X4 U3682 ( .A(n4949), .B(n4508), .Z(n5661) );
HS65_LL_NAND2AX14 U3689 ( .A(n2924), .B(n3492), .Z(n4879) );
HS65_LL_OA12X9 U3694 ( .A(n4101), .B(n3358), .C(n3357), .Z(n3815) );
HS65_LL_CNIVX7 U3708 ( .A(n5178), .Z(n5649) );
HS65_LH_AOI21X2 U3712 ( .A(\lte_x_59/B[5] ), .B(n4544), .C(n3669), .Z(n3921)
);
HS65_LL_IVX9 U3722 ( .A(n3529), .Z(n5647) );
HS65_LH_IVX27 U3737 ( .A(n3789), .Z(n4582) );
HS65_LL_IVX9 U3741 ( .A(n4795), .Z(n3789) );
HS65_LL_BFX9 U3751 ( .A(n2893), .Z(n5129) );
HS65_LL_NAND2X21 U3753 ( .A(n3399), .B(n5136), .Z(n4795) );
HS65_LL_IVX9 U3756 ( .A(n3430), .Z(n2872) );
HS65_LH_IVX9 U3773 ( .A(n4147), .Z(n2865) );
HS65_LL_NOR2X6 U3775 ( .A(n3417), .B(n3416), .Z(n3967) );
HS65_LL_OAI12X6 U3776 ( .A(n3196), .B(n8531), .C(n3195), .Z(n5005) );
HS65_LL_NAND2X7 U3777 ( .A(n3209), .B(n3208), .Z(n5021) );
HS65_LH_NOR2X13 U3780 ( .A(n3306), .B(n3305), .Z(\lte_x_59/B[3] ) );
HS65_LL_OAI12X6 U3781 ( .A(n3325), .B(n8498), .C(n3324), .Z(n4147) );
HS65_LL_OAI21X3 U3798 ( .A(n8394), .B(n3340), .C(n3304), .Z(n3305) );
HS65_LL_AOI21X2 U3803 ( .A(n3167), .B(n3270), .C(n2911), .Z(n3168) );
HS65_LL_CNIVX7 U3807 ( .A(\u_DataPath/u_idexreg/N3 ), .Z(n7834) );
HS65_LH_AOI21X2 U3813 ( .A(n2896), .B(n3134), .C(n3133), .Z(n3135) );
HS65_LL_OAI12X6 U3819 ( .A(n3245), .B(n3244), .C(n3243), .Z(n5104) );
HS65_LL_NAND4ABX3 U3820 ( .A(n8129), .B(n8892), .C(n8886), .D(n8126), .Z(
\u_DataPath/u_idexreg/N3 ) );
HS65_LL_MUXI21X5 U3825 ( .D0(n2970), .D1(n2969), .S0(
\u_DataPath/cw_towb_i [0]), .Z(n8394) );
HS65_LL_MUXI21X2 U3831 ( .D0(n3332), .D1(n3331), .S0(n3404), .Z(n8391) );
HS65_LH_OAI12X3 U3832 ( .A(n9190), .B(n8890), .C(n8317), .Z(
\u_DataPath/dataOut_exe_i [26]) );
HS65_LH_MUXI21X2 U3839 ( .D0(n8907), .D1(
\u_DataPath/from_mem_data_out_i [10]), .S0(\u_DataPath/cw_towb_i [0]),
.Z(n8258) );
HS65_LL_OAI12X3 U3843 ( .A(n8777), .B(n8114), .C(n8878), .Z(n8078) );
HS65_LL_OAI21X2 U3845 ( .A(n8702), .B(n9012), .C(n8101), .Z(n8103) );
HS65_LH_OAI12X3 U3849 ( .A(n9190), .B(n9072), .C(n8333), .Z(
\u_DataPath/dataOut_exe_i [9]) );
HS65_LL_OAI13X5 U3850 ( .A(n8904), .B(n9051), .C(n9081), .D(n8880), .Z(n8440) );
HS65_LL_OAI12X3 U3852 ( .A(n9051), .B(n9103), .C(n8898), .Z(n8441) );
HS65_LL_AOI21X6 U3863 ( .A(n9130), .B(n8750), .C(\u_DataPath/u_idexreg/N10 ),
.Z(n8071) );
HS65_LL_OR3X9 U3866 ( .A(\u_DataPath/cw_exmem_i [5]), .B(
\u_DataPath/cw_exmem_i [3]), .C(n9152), .Z(\u_DataPath/u_idexreg/N10 )
);
HS65_LH_IVX2 U3870 ( .A(n5056), .Z(n5057) );
HS65_LH_OAI21X2 U3872 ( .A(n5123), .B(n5179), .C(n5137), .Z(n5138) );
HS65_LH_NAND3X2 U3873 ( .A(n4971), .B(n4970), .C(n4969), .Z(n4972) );
HS65_LH_NAND2X2 U3875 ( .A(n5144), .B(n5143), .Z(n5145) );
HS65_LH_NAND2X2 U3876 ( .A(n5387), .B(n4143), .Z(n5550) );
HS65_LH_IVX2 U3884 ( .A(n4997), .Z(n5345) );
HS65_LH_NOR2X2 U3895 ( .A(n3285), .B(n4713), .Z(n3286) );
HS65_LH_NAND2X2 U3904 ( .A(n4714), .B(n8557), .Z(n3154) );
HS65_LH_IVX2 U3905 ( .A(n4750), .Z(n4752) );
HS65_LH_IVX2 U3910 ( .A(n5550), .Z(n5551) );
HS65_LH_IVX2 U3911 ( .A(n5313), .Z(n5107) );
HS65_LH_IVX2 U3914 ( .A(n5035), .Z(n5549) );
HS65_LH_IVX2 U3940 ( .A(n8528), .Z(n3202) );
HS65_LH_NAND2X2 U3944 ( .A(n5320), .B(n5321), .Z(n5317) );
HS65_LH_NAND2X2 U3956 ( .A(n4738), .B(n4737), .Z(n4747) );
HS65_LH_NAND2X2 U3968 ( .A(n5323), .B(n5322), .Z(n5324) );
HS65_LH_NAND2X2 U3976 ( .A(n5408), .B(n5378), .Z(n5412) );
HS65_LH_NAND3X2 U3978 ( .A(n5322), .B(n5318), .C(n5317), .Z(n5332) );
HS65_LH_IVX2 U3979 ( .A(n8559), .Z(n3146) );
HS65_LH_AOI21X2 U3981 ( .A(n4351), .B(\sub_x_53/A[27] ), .C(n4350), .Z(n4353) );
HS65_LH_IVX2 U3982 ( .A(n8516), .Z(n3251) );
HS65_LH_NAND2X2 U3989 ( .A(n2849), .B(n4351), .Z(n3594) );
HS65_LH_IVX2 U4002 ( .A(n5627), .Z(n5628) );
HS65_LH_NAND2X2 U4011 ( .A(n4713), .B(n9030), .Z(n4655) );
HS65_LH_NAND2X2 U4013 ( .A(n2842), .B(n2864), .Z(n3956) );
HS65_LH_IVX2 U4023 ( .A(n5347), .Z(n5566) );
HS65_LH_NAND2X2 U4036 ( .A(n5290), .B(n5362), .Z(n4702) );
HS65_LH_OAI21X2 U4047 ( .A(n5523), .B(n5522), .C(n5521), .Z(n5524) );
HS65_LH_IVX2 U4049 ( .A(n5333), .Z(n5309) );
HS65_LL_IVX2 U4053 ( .A(n5209), .Z(n3619) );
HS65_LH_NOR2X2 U4056 ( .A(n3657), .B(n3656), .Z(n4180) );
HS65_LH_NAND2X2 U4069 ( .A(\lte_x_59/B[7] ), .B(n2845), .Z(n4154) );
HS65_LH_OAI21X2 U4073 ( .A(n4524), .B(n4523), .C(n5229), .Z(n4525) );
HS65_LH_NAND2X2 U4074 ( .A(n3327), .B(n9267), .Z(n3253) );
HS65_LH_IVX2 U4080 ( .A(n4355), .Z(n4394) );
HS65_LH_NOR2X2 U4084 ( .A(n5005), .B(\lte_x_59/B[18] ), .Z(n4250) );
HS65_LH_IVX2 U4087 ( .A(n3875), .Z(n3878) );
HS65_LH_NOR2X2 U4090 ( .A(n2854), .B(n2893), .Z(n3834) );
HS65_LH_AOI21X2 U4103 ( .A(\sub_x_53/A[29] ), .B(n4544), .C(n3648), .Z(n3652) );
HS65_LH_IVX2 U4114 ( .A(n3990), .Z(n4041) );
HS65_LH_IVX2 U4115 ( .A(n5629), .Z(n3702) );
HS65_LH_IVX2 U4119 ( .A(n3908), .Z(n3909) );
HS65_LH_IVX2 U4129 ( .A(n4180), .Z(n4184) );
HS65_LH_IVX2 U4135 ( .A(n4320), .Z(n3471) );
HS65_LH_NAND2X2 U4140 ( .A(\lte_x_59/B[14] ), .B(n4588), .Z(n3985) );
HS65_LHS_XNOR2X3 U4141 ( .A(\u_DataPath/jaddr_i [17]), .B(n8966), .Z(n7099)
);
HS65_LH_OAI21X2 U4152 ( .A(n4344), .B(n4343), .C(n4342), .Z(n4345) );
HS65_LH_IVX2 U4157 ( .A(n3932), .Z(n3933) );
HS65_LH_IVX2 U4160 ( .A(n4108), .Z(n4476) );
HS65_LH_NAND2X2 U4171 ( .A(n3426), .B(n4840), .Z(n4841) );
HS65_LH_AOI22X1 U4174 ( .A(n3474), .B(n4587), .C(n4551), .D(\lte_x_59/B[9] ),
.Z(n4128) );
HS65_LH_OA12X4 U4178 ( .A(n4641), .B(n4637), .C(n4663), .Z(n3355) );
HS65_LH_IVX2 U4189 ( .A(n5806), .Z(n5734) );
HS65_LH_NOR2X2 U4192 ( .A(n2843), .B(n3756), .Z(n3672) );
HS65_LH_NAND2X2 U4193 ( .A(n4824), .B(n3486), .Z(n4825) );
HS65_LH_OAI21X2 U4198 ( .A(n4643), .B(n4642), .C(n4641), .Z(n4644) );
HS65_LH_NAND2X2 U4202 ( .A(\lte_x_59/B[14] ), .B(n4544), .Z(n3832) );
HS65_LH_NOR2X6 U4208 ( .A(n6353), .B(n6341), .Z(n6681) );
HS65_LH_NAND2X2 U4231 ( .A(n4943), .B(n3426), .Z(n3981) );
HS65_LH_IVX2 U4235 ( .A(n4389), .Z(n3539) );
HS65_LH_OAI21X2 U4244 ( .A(n3762), .B(n4955), .C(n3761), .Z(n3797) );
HS65_LH_NAND2X2 U4260 ( .A(n4926), .B(n4925), .Z(n4935) );
HS65_LH_NAND2X2 U4261 ( .A(n4238), .B(n5194), .Z(n4240) );
HS65_LH_OAI21X2 U4266 ( .A(n4391), .B(n4855), .C(n3581), .Z(n3592) );
HS65_LH_NAND3X2 U4271 ( .A(n3426), .B(n4507), .C(n5615), .Z(n3654) );
HS65_LH_AOI21X2 U4274 ( .A(n5780), .B(n5726), .C(n5725), .Z(n5759) );
HS65_LH_OR2X4 U4281 ( .A(\sub_x_53/A[30] ), .B(n4966), .Z(n4211) );
HS65_LH_NAND3X2 U4287 ( .A(n4347), .B(n4346), .C(n4345), .Z(n4348) );
HS65_LH_NOR2X2 U4290 ( .A(n4052), .B(n3815), .Z(n4053) );
HS65_LH_NAND2X4 U4292 ( .A(n3374), .B(n5271), .Z(n4420) );
HS65_LH_NOR2X2 U4301 ( .A(n4134), .B(n5249), .Z(n5186) );
HS65_LH_NAND2X2 U4307 ( .A(n7631), .B(n5638), .Z(n5639) );
HS65_LH_OAI21X2 U4314 ( .A(n3874), .B(n5201), .C(n3873), .Z(n3882) );
HS65_LL_NOR3X4 U4318 ( .A(n9150), .B(n9128), .C(n9051), .Z(n8439) );
HS65_LH_NAND2X14 U4329 ( .A(n9251), .B(n8897), .Z(n8453) );
HS65_LH_NAND2X2 U4331 ( .A(n3415), .B(n5321), .Z(n3818) );
HS65_LH_XNOR2X4 U4346 ( .A(\u_DataPath/jaddr_i [17]), .B(n7086), .Z(n7088)
);
HS65_LH_AO22X4 U4353 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][2] ), .B(n7517),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[4][2] ), .D(n7318), .Z(n6959) );
HS65_LH_AO22X4 U4367 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][21] ), .B(n7587),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[12][21] ), .D(
n7586), .Z(n7588) );
HS65_LH_AOI22X1 U4369 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][24] ), .B(n6754),
.C(n7594), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][24] ), .Z(n7566)
);
HS65_LH_AO22X4 U4384 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][29] ), .B(n7602),
.C(n7601), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][29] ), .Z(n7532)
);
HS65_LH_AOI22X1 U4388 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][28] ), .B(n7603),
.C(n6966), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][28] ), .Z(n7505)
);
HS65_LH_AOI22X1 U4390 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[25][20] ), .B(n7604),
.C(n7334), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][20] ), .Z(n7484)
);
HS65_LH_AOI22X1 U4394 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][20] ), .B(n7415),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[10][20] ), .D(
n2891), .Z(n7475) );
HS65_LH_AOI22X1 U4396 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][27] ), .B(n7415),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[10][27] ), .D(
n2891), .Z(n7455) );
HS65_LH_AO22X4 U4400 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][0] ), .B(n7429),
.C(n7310), .D(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][0] ), .Z(n7431) );
HS65_LH_AOI22X1 U4404 ( .A(n6745), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][3] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][3] ), .D(n7516),
.Z(n7394) );
HS65_LH_AOI22X1 U4411 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][14] ), .B(n7585),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[1][14] ), .D(
n2889), .Z(n7373) );
HS65_LH_AOI22X1 U4414 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][4] ), .B(n7585),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[1][4] ), .D(n2889), .Z(n7353) );
HS65_LH_BFX4 U4415 ( .A(n6952), .Z(n7310) );
HS65_LH_BFX4 U4426 ( .A(n6682), .Z(n7592) );
HS65_LH_NOR2X5 U4429 ( .A(n6148), .B(n6152), .Z(n2884) );
HS65_LH_BFX4 U4453 ( .A(n6624), .Z(n6600) );
HS65_LH_AOI22X1 U4473 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][2] ), .B(n7286),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[21][2] ), .D(
n6171), .Z(n6564) );
HS65_LH_AO22X4 U4482 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][25] ), .B(n7277),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[25][25] ), .D(
n6629), .Z(n7147) );
HS65_LH_AO22X4 U4485 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][9] ), .B(n6426),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][9] ), .D(n7291), .Z(n7138) );
HS65_LH_AO22X4 U4486 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][28] ), .B(n9374),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[6][28] ), .D(
n7267), .Z(n6907) );
HS65_LH_AO22X4 U4488 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][17] ), .B(n9374),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[6][17] ), .D(
n7267), .Z(n6887) );
HS65_LH_AOI22X1 U4506 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][31] ), .B(n7273),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[29][31] ), .D(
n7272), .Z(n6873) );
HS65_LH_AO22X4 U4507 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][18] ), .B(n7275),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[30][18] ), .D(
n7274), .Z(n6655) );
HS65_LH_AO22X4 U4516 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][20] ), .B(n7277),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[25][20] ), .D(
n7276), .Z(n6851) );
HS65_LH_AO22X4 U4526 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][5] ), .B(n7283),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[20][5] ), .D(
n7282), .Z(n6940) );
HS65_LH_AO22X4 U4528 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][29] ), .B(n7283),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[20][29] ), .D(
n7282), .Z(n7290) );
HS65_LH_AOI22X1 U4540 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][8] ), .B(n7524),
.C(n7593), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][8] ), .Z(n6776)
);
HS65_LH_AOI22X1 U4544 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][11] ), .B(n6376),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[21][11] ), .D(
n7285), .Z(n6254) );
HS65_LH_AOI22X1 U4547 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][31] ), .B(n7524),
.C(n7593), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][31] ), .Z(n6686)
);
HS65_LH_AOI22X1 U4548 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][25] ), .B(n7603),
.C(n7333), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][25] ), .Z(n7049)
);
HS65_LH_AO22X4 U4549 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][6] ), .B(n7429),
.C(n7310), .D(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][6] ), .Z(n7245) );
HS65_LH_AOI22X1 U4554 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][21] ), .B(n6377),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[22][21] ), .D(
n7171), .Z(n6193) );
HS65_LH_AOI22X1 U4556 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][21] ), .B(n7165),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[28][21] ), .D(
n6624), .Z(n6192) );
HS65_LH_AOI22X1 U4557 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][16] ), .B(n7273),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[29][16] ), .D(
n6625), .Z(n6169) );
HS65_LH_AO22X4 U4561 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][23] ), .B(n7517),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[4][23] ), .D(
n7318), .Z(n7229) );
HS65_LH_AO22X4 U4585 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][1] ), .B(n7522),
.C(n7439), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][1] ), .Z(n6838)
);
HS65_LH_AO22X4 U4596 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][27] ), .B(n7170),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[23][27] ), .D(
n6637), .Z(n6215) );
HS65_LH_AOI22X1 U4600 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][19] ), .B(n7525),
.C(n7594), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][19] ), .Z(n6755)
);
HS65_LH_AOI22X1 U4601 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][7] ), .B(n7524),
.C(n7593), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][7] ), .Z(n6728)
);
HS65_LH_AO22X4 U4603 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][22] ), .B(n7293),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[13][22] ), .D(
n7292), .Z(n6279) );
HS65_LH_AO22X4 U4614 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][24] ), .B(n7293),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[13][24] ), .D(
n7292), .Z(n6299) );
HS65_LH_AO22X4 U4616 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][5] ), .B(n7523),
.C(n6682), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][5] ), .Z(n6709)
);
HS65_LH_AOI22X1 U4619 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][5] ), .B(n7415),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[10][5] ), .D(
n6670), .Z(n6702) );
HS65_LH_AO22X4 U4620 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][13] ), .B(n7293),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[13][13] ), .D(
n7292), .Z(n7178) );
HS65_LH_AOI22X1 U4629 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][13] ), .B(n7165),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[28][13] ), .D(
n6624), .Z(n7169) );
HS65_LH_AOI22X1 U4634 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][14] ), .B(n7273),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[29][14] ), .D(
n6625), .Z(n6311) );
HS65_LH_AO22X4 U4637 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][19] ), .B(n9374),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[6][19] ), .D(
n7267), .Z(n6515) );
HS65_LH_AO22X4 U4643 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][7] ), .B(n9375),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[6][7] ), .D(n7267), .Z(n6435) );
HS65_LH_AO22X4 U4659 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][12] ), .B(n9375),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[6][12] ), .D(
n7267), .Z(n6535) );
HS65_LH_AO22X4 U4665 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][6] ), .B(n7275),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[30][6] ), .D(
n7274), .Z(n6480) );
HS65_LH_AO22X4 U4674 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][3] ), .B(n6626),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[30][3] ), .D(
n7274), .Z(n6580) );
HS65_LH_AO22X4 U4678 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][26] ), .B(n7283),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[20][26] ), .D(
n7282), .Z(n6506) );
HS65_LH_AO22X4 U4685 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][8] ), .B(n7283),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[20][8] ), .D(
n7282), .Z(n6466) );
HS65_LH_AOI22X1 U4691 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][1] ), .B(n2887),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[22][1] ), .D(
n7171), .Z(n6605) );
HS65_LH_AOI22X1 U4697 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][11] ), .B(n7603),
.C(n7333), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][11] ), .Z(n7069)
);
HS65_LH_NOR2AX3 U4707 ( .A(n3069), .B(\u_DataPath/cw_towb_i [0]), .Z(n3070)
);
HS65_LH_AO22X4 U4708 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][13] ), .B(n7578),
.C(n7310), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][13] ), .Z(n6977)
);
HS65_LH_AO22X4 U4712 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][22] ), .B(n7580),
.C(n7579), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][22] ), .Z(n6996)
);
HS65_LH_AO22X4 U4713 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][4] ), .B(n9374),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[6][4] ), .D(n7267), .Z(n6620) );
HS65_LH_IVX2 U4715 ( .A(n3050), .Z(n3034) );
HS65_LH_IVX2 U4723 ( .A(n4579), .Z(n4615) );
HS65_LH_NOR2X2 U4742 ( .A(n4939), .B(n3979), .Z(n3989) );
HS65_LH_IVX2 U4744 ( .A(n3515), .Z(n5293) );
HS65_LH_IVX2 U4771 ( .A(n3698), .Z(n3699) );
HS65_LH_NOR2X3 U4780 ( .A(\sub_x_53/A[2] ), .B(n3415), .Z(n4575) );
HS65_LH_AOI21X2 U4786 ( .A(n4949), .B(n4948), .C(n4947), .Z(n4958) );
HS65_LH_OAI21X2 U4792 ( .A(n5760), .B(n5878), .C(n5759), .Z(n5791) );
HS65_LH_IVX2 U4799 ( .A(n5795), .Z(n5796) );
HS65_LH_OR2X4 U4808 ( .A(n9342), .B(n9216), .Z(n5902) );
HS65_LH_IVX2 U4814 ( .A(n5907), .Z(n5740) );
HS65_LH_NAND2X2 U4817 ( .A(n9185), .B(n9230), .Z(n5789) );
HS65_LH_NOR2X2 U4831 ( .A(n7645), .B(n7680), .Z(n7646) );
HS65_LH_NOR2X2 U4833 ( .A(n9173), .B(n9231), .Z(n5874) );
HS65_LH_NAND2X2 U4837 ( .A(n4050), .B(n3267), .Z(n4056) );
HS65_LH_NAND2X2 U4843 ( .A(n5217), .B(n4885), .Z(n4900) );
HS65_LH_IVX2 U4860 ( .A(n8262), .Z(n2966) );
HS65_LH_NOR3X1 U4863 ( .A(\u_DataPath/dataOut_exe_i [1]), .B(n8360), .C(
n8270), .Z(n7344) );
HS65_LH_NAND2X2 U4872 ( .A(n5867), .B(n5866), .Z(n5869) );
HS65_LH_OAI22X1 U4874 ( .A(n3264), .B(\u_DataPath/dataOut_exe_i [26]), .C(
n8316), .D(n3409), .Z(n3151) );
HS65_LH_NAND2X2 U4878 ( .A(n4713), .B(n9342), .Z(n4191) );
HS65_LH_NAND2X2 U4886 ( .A(n9368), .B(n9008), .Z(n8435) );
HS65_LH_NAND2X2 U4888 ( .A(n8687), .B(n8686), .Z(n7668) );
HS65_LH_IVX2 U4906 ( .A(n8255), .Z(n3260) );
HS65_LH_IVX2 U4909 ( .A(\u_DataPath/dataOut_exe_i [17]), .Z(n3201) );
HS65_LH_AOI22X1 U4917 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][15] ), .B(n7524),
.C(n7593), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][15] ), .Z(n7193)
);
HS65_LH_AO22X4 U4925 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][10] ), .B(n7523),
.C(n7592), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][10] ), .Z(n7214)
);
HS65_LH_AO22X4 U4927 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][0] ), .B(n6426),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][0] ), .D(n7291), .Z(n6430) );
HS65_LH_AOI22X1 U4928 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][10] ), .B(n6941),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[7][10] ), .D(
n7294), .Z(n6407) );
HS65_LH_AOI22X1 U4936 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][15] ), .B(n7297),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[0][15] ), .D(
n6942), .Z(n6386) );
HS65_LH_AOI22X1 U4938 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][15] ), .B(n6595),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[14][15] ), .D(
n7264), .Z(n6369) );
HS65_LH_MUXI21X2 U4942 ( .D0(n2968), .D1(n9384), .S0(
\u_DataPath/cw_towb_i [0]), .Z(n8426) );
HS65_LH_AOI21X2 U4948 ( .A(n3404), .B(n9386), .C(n3070), .Z(n8345) );
HS65_LH_NAND2X2 U4956 ( .A(n9068), .B(n7773), .Z(n7690) );
HS65_LH_OAI21X2 U4967 ( .A(n4255), .B(n4254), .C(n4516), .Z(n4265) );
HS65_LH_IVX2 U4976 ( .A(n8056), .Z(n7698) );
HS65_LH_IVX2 U4977 ( .A(n4538), .Z(n4574) );
HS65_LL_OA12X4 U4982 ( .A(n7634), .B(n2844), .C(n4169), .Z(n4170) );
HS65_LH_AOI22X1 U4986 ( .A(n8868), .B(n9029), .C(n9369), .D(n8939), .Z(n7845) );
HS65_LH_NAND2X2 U4999 ( .A(n5777), .B(n5977), .Z(n5785) );
HS65_LH_AOI21X2 U5004 ( .A(n5802), .B(n5868), .C(n5801), .Z(n5803) );
HS65_LH_OAI21X2 U5005 ( .A(n6049), .B(n6045), .C(n6047), .Z(n6051) );
HS65_LH_IVX2 U5013 ( .A(n5980), .Z(n5983) );
HS65_LH_IVX2 U5015 ( .A(n6000), .Z(n6001) );
HS65_LH_NAND2X2 U5016 ( .A(n7707), .B(n4003), .Z(n4287) );
HS65_LH_MUXI21X5 U5017 ( .D0(n3137), .D1(n9389), .S0(
\u_DataPath/cw_towb_i [0]), .Z(n8550) );
HS65_LH_NAND2X2 U5032 ( .A(n3201), .B(n3407), .Z(n3198) );
HS65_LH_AOI22X1 U5040 ( .A(n4951), .B(n4578), .C(n5667), .D(n5239), .Z(n4010) );
HS65_LH_NOR2X2 U5046 ( .A(n8845), .B(n3341), .Z(n3169) );
HS65_LH_OAI22X1 U5047 ( .A(n3264), .B(\u_DataPath/dataOut_exe_i [25]), .C(
n8427), .D(n3409), .Z(n3099) );
HS65_LH_NOR2AX3 U5050 ( .A(n8726), .B(n2994), .Z(n8675) );
HS65_LH_NOR2AX3 U5057 ( .A(n8742), .B(n2994), .Z(n8674) );
HS65_LH_NOR2AX3 U5092 ( .A(\u_DataPath/dataOut_exe_i [8]), .B(n2986), .Z(
n3006) );
HS65_LH_NOR2AX3 U5096 ( .A(\u_DataPath/dataOut_exe_i [23]), .B(n3116), .Z(
n3003) );
HS65_LH_IVX2 U5104 ( .A(n9112), .Z(n2984) );
HS65_LH_AO22X4 U5115 ( .A(n9262), .B(n9188), .C(n9133), .D(n8982), .Z(
\u_DataPath/jump_address_i [19]) );
HS65_LH_AO22X4 U5122 ( .A(n9104), .B(n9188), .C(n9133), .D(n8951), .Z(
\u_DataPath/jump_address_i [10]) );
HS65_LH_IVX2 U5129 ( .A(n7668), .Z(n7743) );
HS65_LH_NAND2X2 U5132 ( .A(n2985), .B(n3109), .Z(n8425) );
HS65_LH_NAND2X2 U5133 ( .A(n3412), .B(n2866), .Z(n8491) );
HS65_LH_NAND2X2 U5134 ( .A(n4208), .B(n7869), .Z(n8569) );
HS65_LH_NAND2X2 U5136 ( .A(n3278), .B(n7869), .Z(n8521) );
HS65_LL_NAND3X2 U5141 ( .A(n4511), .B(n4510), .C(n4509), .Z(n5248) );
HS65_LH_OA12X4 U5143 ( .A(n4829), .B(n9402), .C(n4827), .Z(n2926) );
HS65_LH_NOR4ABX2 U5144 ( .A(n6826), .B(n6825), .C(n6824), .D(n6823), .Z(
n8175) );
HS65_LH_NOR4ABX2 U5151 ( .A(n6718), .B(n6717), .C(n6716), .D(n6715), .Z(
n8171) );
HS65_LH_AOI31X2 U5152 ( .A(n4608), .B(n4607), .C(n4606), .D(n5152), .Z(n4653) );
HS65_LH_BFX4 U5153 ( .A(n7306), .Z(n7917) );
HS65_LH_NOR2X2 U5154 ( .A(n7641), .B(n7640), .Z(n8135) );
HS65_LH_NOR2X2 U5155 ( .A(n5696), .B(n5695), .Z(n7118) );
HS65_LH_OAI21X2 U5160 ( .A(n5967), .B(n6007), .C(n5966), .Z(n6059) );
HS65_LH_NAND2X2 U5162 ( .A(n6076), .B(n6031), .Z(n6032) );
HS65_LH_NOR2X2 U5164 ( .A(n7758), .B(n7757), .Z(n7663) );
HS65_LH_NAND2X2 U5176 ( .A(n8708), .B(n7764), .Z(n7765) );
HS65_LH_NAND2X2 U5181 ( .A(n6054), .B(n6053), .Z(n6056) );
HS65_LH_NOR2X2 U5187 ( .A(n7793), .B(n7792), .Z(n7731) );
HS65_LH_NAND2X2 U5196 ( .A(n5949), .B(n5948), .Z(n5951) );
HS65_LH_IVX2 U5200 ( .A(n6034), .Z(n6095) );
HS65_LH_NOR2X2 U5212 ( .A(n7697), .B(n7694), .Z(n8040) );
HS65_LH_NOR2X2 U5221 ( .A(n4475), .B(n4474), .Z(n4487) );
HS65_LH_AOI21X2 U5227 ( .A(n5667), .B(n4872), .C(n4871), .Z(n4912) );
HS65_LH_NOR2X2 U5228 ( .A(\u_DataPath/dataOut_exe_i [10]), .B(n3264), .Z(
n3240) );
HS65_LH_OAI211X1 U5230 ( .A(n8302), .B(n8575), .C(n7346), .D(n7345), .Z(
n8298) );
HS65_LH_NAND3X2 U5232 ( .A(n9113), .B(n2984), .C(n7639), .Z(n3109) );
HS65_LH_NAND2AX4 U5241 ( .A(n9031), .B(n7733), .Z(n8144) );
HS65_LH_NAND2X4 U5246 ( .A(n7851), .B(n9061), .Z(
\u_DataPath/dataOut_exe_i [16]) );
HS65_LH_AO22X4 U5247 ( .A(n9254), .B(n8768), .C(n9132), .D(n9009), .Z(
\u_DataPath/pc4_to_idexreg_i [4]) );
HS65_LH_AO22X4 U5251 ( .A(n8786), .B(n9139), .C(n9333), .D(n9154), .Z(
opcode_i[5]) );
HS65_LH_NOR4ABX2 U5252 ( .A(n7203), .B(n7202), .C(n7201), .D(n7200), .Z(
n8305) );
HS65_LH_AO22X4 U5253 ( .A(n9254), .B(n8769), .C(n9240), .D(n9070), .Z(
\u_DataPath/pc4_to_idexreg_i [27]) );
HS65_LH_AO22X4 U5256 ( .A(n8780), .B(n9252), .C(n9307), .D(n9069), .Z(
\u_DataPath/immediate_ext_dec_i [4]) );
HS65_LH_AO22X4 U5262 ( .A(n9254), .B(n8804), .C(n9240), .D(n8974), .Z(
\u_DataPath/pc4_to_idexreg_i [10]) );
HS65_LH_AO22X4 U5265 ( .A(n9254), .B(n8827), .C(n9240), .D(n9108), .Z(
\u_DataPath/pc4_to_idexreg_i [31]) );
HS65_LHS_XOR2X3 U5271 ( .A(n5946), .B(n5945), .Z(
\u_DataPath/u_execute/resAdd1_i [31]) );
HS65_LH_NAND2X2 U5275 ( .A(\u_DataPath/immediate_ext_dec_i [0]), .B(
\u_DataPath/immediate_ext_dec_i [1]), .Z(n8092) );
HS65_LHS_XNOR2X3 U5278 ( .A(n2782), .B(n7663), .Z(\u_DataPath/pc_4_i [19])
);
HS65_LHS_XNOR2X3 U5286 ( .A(n3124), .B(n7679), .Z(\u_DataPath/pc_4_i [17])
);
HS65_LHS_XNOR2X3 U5292 ( .A(n6092), .B(n6091), .Z(
\u_DataPath/u_execute/resAdd1_i [7]) );
HS65_LL_NOR2AX6 U5302 ( .A(n4369), .B(n4368), .Z(n8469) );
HS65_LHS_XOR2X3 U5303 ( .A(n7783), .B(n7782), .Z(
\u_DataPath/u_execute/link_value_i [9]) );
HS65_LHS_XNOR2X3 U5304 ( .A(n2825), .B(n7704), .Z(\u_DataPath/pc_4_i [27])
);
HS65_LH_IVX2 U5307 ( .A(Data_out_fromRAM[20]), .Z(n8410) );
HS65_LH_IVX2 U5316 ( .A(Data_out_fromRAM[21]), .Z(n8365) );
HS65_LH_IVX2 U5318 ( .A(n7740), .Z(n8095) );
HS65_LH_NOR2X2 U5323 ( .A(n9175), .B(n9227), .Z(n6085) );
HS65_LH_IVX2 U5325 ( .A(n5882), .Z(n5883) );
HS65_LH_NOR2X2 U5338 ( .A(n9145), .B(n9224), .Z(n5753) );
HS65_LH_IVX2 U5340 ( .A(n5957), .Z(n5958) );
HS65_LH_NOR2X2 U5342 ( .A(n9033), .B(n9215), .Z(n5894) );
HS65_LH_IVX2 U5348 ( .A(n6097), .Z(n6098) );
HS65_LH_NOR2X2 U5353 ( .A(n9179), .B(n9225), .Z(n6090) );
HS65_LH_IVX2 U5363 ( .A(n5887), .Z(n5831) );
HS65_LH_NOR2X2 U5365 ( .A(n8913), .B(n9219), .Z(n6041) );
HS65_LH_IVX2 U5366 ( .A(n5839), .Z(n5890) );
HS65_LH_OR2X4 U5370 ( .A(n6148), .B(n6151), .Z(n9335) );
HS65_LH_OR2X4 U5372 ( .A(n9002), .B(n8751), .Z(n9336) );
HS65_LH_OR2X4 U5391 ( .A(n9344), .B(n9345), .Z(n9337) );
HS65_LH_NOR2X2 U5393 ( .A(n9267), .B(n9228), .Z(n5987) );
HS65_LH_IVX2 U5403 ( .A(n5786), .Z(n5787) );
HS65_LH_IVX2 U5404 ( .A(n5960), .Z(n6057) );
HS65_LH_NAND2X2 U5411 ( .A(n9181), .B(n9226), .Z(n6058) );
HS65_LH_IVX2 U5418 ( .A(n5863), .Z(n5764) );
HS65_LH_NOR2X2 U5422 ( .A(n9039), .B(n9116), .Z(n5899) );
HS65_LH_IVX2 U5428 ( .A(n6102), .Z(n6050) );
HS65_LH_IVX2 U5438 ( .A(n5836), .Z(n5837) );
HS65_LH_NOR2X2 U5443 ( .A(n9177), .B(n9229), .Z(n5879) );
HS65_LH_IVX2 U5446 ( .A(n6078), .Z(n6031) );
HS65_LH_NAND2X2 U5450 ( .A(n9171), .B(n9214), .Z(n5871) );
HS65_LH_IVX2 U5452 ( .A(n6070), .Z(n5984) );
HS65_LH_NOR2X2 U5454 ( .A(n9171), .B(n9214), .Z(n5778) );
HS65_LH_IVX2 U5460 ( .A(n5979), .Z(n6069) );
HS65_LH_NAND2X2 U5463 ( .A(n8913), .B(n9219), .Z(n5891) );
HS65_LH_IVX2 U5466 ( .A(n6094), .Z(n6042) );
HS65_LH_IVX2 U5467 ( .A(n5285), .Z(n4829) );
HS65_LH_NOR2X2 U5469 ( .A(n9183), .B(n9232), .Z(n5775) );
HS65_LH_IVX2 U5472 ( .A(n5976), .Z(n5977) );
HS65_LH_IVX2 U5477 ( .A(n5789), .Z(n5790) );
HS65_LH_NOR2X2 U5485 ( .A(n9185), .B(n9230), .Z(n5772) );
HS65_LH_IVX2 U5494 ( .A(n5990), .Z(n6005) );
HS65_LH_NOR2X2 U5497 ( .A(n9037), .B(n9212), .Z(n5846) );
HS65_LH_IVX2 U5498 ( .A(n6045), .Z(n6046) );
HS65_LH_NOR2X2 U5499 ( .A(n9173), .B(n9231), .Z(n6073) );
HS65_LH_IVX2 U5501 ( .A(n5874), .Z(n5875) );
HS65_LH_OA12X4 U5502 ( .A(n3899), .B(n3815), .C(n3898), .Z(n9338) );
HS65_LHS_XNOR2X3 U5509 ( .A(n4111), .B(n4110), .Z(n9339) );
HS65_LH_IVX9 U5510 ( .A(n8876), .Z(n9340) );
HS65_LH_IVX9 U5514 ( .A(n9340), .Z(n9341) );
HS65_LH_IVX9 U5516 ( .A(n9340), .Z(n9342) );
HS65_LH_IVX9 U5520 ( .A(n9340), .Z(n9343) );
HS65_LH_NOR2X2 U5521 ( .A(n9336), .B(n9337), .Z(\u_DataPath/cw_to_ex_i [15])
);
HS65_LH_CNIVX3 U5523 ( .A(n9347), .Z(n9344) );
HS65_LH_CNIVX3 U5527 ( .A(n9146), .Z(n9345) );
HS65_LH_IVX2 U5529 ( .A(n3582), .Z(n9346) );
HS65_LL_NOR2X6 U5566 ( .A(n5491), .B(n3423), .Z(n3582) );
HS65_LH_IVX9 U5570 ( .A(n3582), .Z(n4548) );
HS65_LH_AOI21X6 U5581 ( .A(n5643), .B(n4861), .C(n2902), .Z(n4862) );
HS65_LL_BFX9 U5584 ( .A(n5179), .Z(n9348) );
HS65_LH_AOI12X3 U5591 ( .A(n9349), .B(n5005), .C(n5649), .Z(n4269) );
HS65_LH_NAND3X5 U5610 ( .A(n4990), .B(n5115), .C(n4989), .Z(n4991) );
HS65_LL_IVX2 U5617 ( .A(n5082), .Z(n5529) );
HS65_LH_NOR2X2 U5625 ( .A(n8824), .B(n3403), .Z(n3086) );
HS65_LH_OAI21X2 U5637 ( .A(n4905), .B(n3815), .C(n5397), .Z(n4906) );
HS65_LH_IVX7 U5658 ( .A(n9330), .Z(n9354) );
HS65_LH_IVX7 U5660 ( .A(n9330), .Z(n9355) );
HS65_LH_IVX7 U5664 ( .A(n9330), .Z(n9356) );
HS65_LHS_XOR2X3 U5678 ( .A(addr_to_iram[29]), .B(n7786), .Z(
\u_DataPath/pc_4_i [31]) );
HS65_LH_IVX44 U5688 ( .A(n2780), .Z(addr_to_iram[29]) );
HS65_LH_IVX44 U5691 ( .A(n3124), .Z(addr_to_iram[15]) );
HS65_LH_IVX2 U5704 ( .A(n8677), .Z(n9359) );
HS65_LH_IVX4 U5713 ( .A(n9359), .Z(n9360) );
HS65_LH_IVX7 U5715 ( .A(n9359), .Z(n9361) );
HS65_LH_IVX4 U5731 ( .A(n9359), .Z(n9362) );
HS65_LH_IVX9 U5760 ( .A(n9135), .Z(n9364) );
HS65_LH_IVX9 U5778 ( .A(n9364), .Z(n9365) );
HS65_LH_IVX9 U5811 ( .A(n9364), .Z(n9366) );
HS65_LH_IVX9 U5815 ( .A(n9135), .Z(n9367) );
HS65_LH_IVX9 U5816 ( .A(n9367), .Z(n9368) );
HS65_LH_IVX9 U5826 ( .A(n9367), .Z(n9369) );
HS65_LH_AOI21X2 U5836 ( .A(n9007), .B(n9347), .C(n8082), .Z(n8088) );
HS65_LL_OR2X18 U5854 ( .A(n3401), .B(n5136), .Z(n2893) );
HS65_LH_OAI21X2 U5866 ( .A(n3427), .B(n5620), .C(n3767), .Z(n3795) );
HS65_LH_OAI21X3 U5874 ( .A(n5173), .B(n5620), .C(n3986), .Z(n3987) );
HS65_LL_NAND3X5 U5887 ( .A(n2931), .B(n4048), .C(n4047), .Z(n4302) );
HS65_LH_OAI21X2 U5890 ( .A(n2848), .B(n3756), .C(n4154), .Z(n4155) );
HS65_LH_NAND2X7 U5894 ( .A(n5643), .B(n4046), .Z(n4047) );
HS65_LH_IVX9 U5895 ( .A(n5088), .Z(n3415) );
HS65_LL_NAND4ABX6 U5914 ( .A(n5601), .B(n5600), .C(n8460), .D(n5599), .Z(
n5678) );
HS65_LL_AOI12X2 U5930 ( .A(n5415), .B(n5414), .C(n5413), .Z(n5462) );
HS65_LH_AOI21X6 U5939 ( .A(n5459), .B(n5458), .C(n5457), .Z(n5460) );
HS65_LH_NOR2X6 U5940 ( .A(\sub_x_53/A[27] ), .B(n3385), .Z(n3629) );
HS65_LL_IVX2 U5942 ( .A(n4976), .Z(n3385) );
HS65_LL_NAND2X2 U5957 ( .A(n4714), .B(n8546), .Z(n3171) );
HS65_LL_NOR3AX9 U5959 ( .A(n4456), .B(n4455), .C(n4454), .Z(n5681) );
HS65_LL_AOI21X2 U5963 ( .A(n4295), .B(n5211), .C(n4294), .Z(n4299) );
HS65_LL_NAND2AX14 U5967 ( .A(n3381), .B(n3380), .Z(n5195) );
HS65_LL_CNIVX3 U5970 ( .A(n5714), .Z(n4788) );
HS65_LL_NOR3X7 U5978 ( .A(n4787), .B(n4786), .C(n4785), .Z(n5714) );
HS65_LL_NAND3X3 U5982 ( .A(n2919), .B(n3202), .C(n8529), .Z(n3203) );
HS65_LL_OAI12X6 U5986 ( .A(n3501), .B(n4426), .C(n3500), .Z(n5211) );
HS65_LL_NOR2X2 U6012 ( .A(\sub_x_53/A[27] ), .B(n4976), .Z(n3682) );
HS65_LL_OAI21X2 U6015 ( .A(n4736), .B(n4735), .C(n4734), .Z(n4783) );
HS65_LL_BFX4 U6018 ( .A(n6618), .Z(n9370) );
HS65_LH_BFX9 U6024 ( .A(n6618), .Z(n9371) );
HS65_LH_BFX2 U6030 ( .A(n6618), .Z(n9372) );
HS65_LL_NOR2X2 U6031 ( .A(n6148), .B(n6149), .Z(n6618) );
HS65_LL_AOI22X3 U6034 ( .A(\lte_x_59/B[1] ), .B(n4588), .C(n4587), .D(
\sub_x_53/A[0] ), .Z(n4117) );
HS65_LH_BFX9 U6039 ( .A(n7312), .Z(n9373) );
HS65_LH_NOR2X2 U6053 ( .A(n6353), .B(n6331), .Z(n7312) );
HS65_LH_NOR2X2 U6060 ( .A(n5530), .B(n3515), .Z(n5416) );
HS65_LH_NAND2X7 U6070 ( .A(n3420), .B(n4512), .Z(n5178) );
HS65_LH_AOI12X3 U6087 ( .A(n5207), .B(n5658), .C(n4271), .Z(n4272) );
HS65_LH_AOI21X2 U6094 ( .A(n4051), .B(n4918), .C(n5476), .Z(n4054) );
HS65_LL_NAND2AX7 U6097 ( .A(n3364), .B(n3363), .Z(n4918) );
HS65_LL_AOI21X2 U6113 ( .A(n5195), .B(n4335), .C(n4334), .Z(n4336) );
HS65_LL_NOR2AX6 U6115 ( .A(n3387), .B(n3386), .Z(n4332) );
HS65_LL_OAI21X2 U6116 ( .A(n3749), .B(n3629), .C(n5443), .Z(n3386) );
HS65_LL_NOR2X6 U6118 ( .A(\lte_x_59/B[15] ), .B(n4677), .Z(n3891) );
HS65_LH_IVX9 U6121 ( .A(n3891), .Z(n3892) );
HS65_LH_NOR2X6 U6122 ( .A(n3891), .B(n4913), .Z(n3368) );
HS65_LH_OAI12X3 U6126 ( .A(n5435), .B(n3698), .C(n3700), .Z(n3378) );
HS65_LH_OAI21X2 U6131 ( .A(n4671), .B(n4583), .C(n4060), .Z(n4078) );
HS65_LH_OAI22X1 U6132 ( .A(n2848), .B(n4583), .C(n3756), .D(n5041), .Z(n4130) );
HS65_LH_OA12X4 U6134 ( .A(n5652), .B(n4583), .C(n3550), .Z(n2899) );
HS65_LH_OAI22X1 U6135 ( .A(n5652), .B(n4583), .C(n3756), .D(n2860), .Z(n3666) );
HS65_LL_NOR2X2 U6136 ( .A(n2843), .B(n4583), .Z(n3456) );
HS65_LL_NOR2X2 U6137 ( .A(n4986), .B(n4583), .Z(n3552) );
HS65_LL_NOR2X2 U6139 ( .A(n5320), .B(n4583), .Z(n4541) );
HS65_LH_OAI22X1 U6140 ( .A(n4700), .B(n4583), .C(n3756), .D(n4701), .Z(n3595) );
HS65_LL_OAI12X2 U6141 ( .A(n4583), .B(n4796), .C(n3518), .Z(n3520) );
HS65_LL_OAI21X2 U6142 ( .A(n4583), .B(n4981), .C(n3718), .Z(n4494) );
HS65_LL_NOR2X2 U6143 ( .A(n4700), .B(n4583), .Z(n3904) );
HS65_LL_NOR2X2 U6145 ( .A(n4984), .B(n4583), .Z(n3840) );
HS65_LH_NOR2X6 U6147 ( .A(n2854), .B(n4583), .Z(n3549) );
HS65_LL_NAND2X7 U6150 ( .A(n3890), .B(n3889), .Z(n7867) );
HS65_LH_OAI21X2 U6152 ( .A(n4293), .B(n4319), .C(n4292), .Z(n4294) );
HS65_LL_AOI12X3 U6153 ( .A(n3803), .B(n3503), .C(n3502), .Z(n4319) );
HS65_LH_OAI12X3 U6163 ( .A(n3802), .B(n3682), .C(n3684), .Z(n3502) );
HS65_LL_OAI12X3 U6164 ( .A(n5209), .B(n3613), .C(n3615), .Z(n3803) );
HS65_LL_NAND2X4 U6174 ( .A(n2881), .B(n6340), .Z(n6333) );
HS65_LL_AOI12X2 U6179 ( .A(n4733), .B(n4732), .C(n4731), .Z(n4734) );
HS65_LL_NOR3X2 U6190 ( .A(n4275), .B(n4274), .C(n4273), .Z(n4276) );
HS65_LL_NAND2X2 U6196 ( .A(n5661), .B(n5660), .Z(n5662) );
HS65_LH_NAND2X2 U6199 ( .A(n5618), .B(n5660), .Z(n4268) );
HS65_LL_NOR3X1 U6202 ( .A(n4156), .B(n4153), .C(n4155), .Z(n4558) );
HS65_LH_NOR2X2 U6203 ( .A(n5652), .B(n2893), .Z(n3823) );
HS65_LL_NOR2X2 U6205 ( .A(n4465), .B(n4156), .Z(n3790) );
HS65_LL_NOR2X2 U6208 ( .A(n4671), .B(n2893), .Z(n3955) );
HS65_LL_IVX9 U6210 ( .A(n2893), .Z(n4544) );
HS65_LL_OA12X9 U6213 ( .A(n5498), .B(n5497), .C(n5496), .Z(n5595) );
HS65_LL_NOR2X2 U6215 ( .A(n8794), .B(n9049), .Z(\u_DataPath/cw_exmem_i [5])
);
HS65_LL_NAND2AX4 U6217 ( .A(n5640), .B(n5639), .Z(n5641) );
HS65_LLS_XNOR2X3 U6219 ( .A(n2917), .B(n5637), .Z(n5638) );
HS65_LL_NOR2X3 U6230 ( .A(n5397), .B(n4902), .Z(n3361) );
HS65_LL_CNIVX3 U6234 ( .A(n5373), .Z(n3360) );
HS65_LL_NAND2X4 U6235 ( .A(n5078), .B(n5077), .Z(n5079) );
HS65_LH_IVX9 U6246 ( .A(\sub_x_53/A[17] ), .Z(n4984) );
HS65_LH_NAND2X7 U6247 ( .A(n5667), .B(n4389), .Z(n4390) );
HS65_LL_NAND3X3 U6249 ( .A(n3910), .B(n4022), .C(n3536), .Z(n4389) );
HS65_LH_AOI12X3 U6257 ( .A(\sub_x_53/A[17] ), .B(n4588), .C(n3535), .Z(n3536) );
HS65_LH_AOI12X3 U6262 ( .A(n4431), .B(n4349), .C(n4348), .Z(n4365) );
HS65_LH_IVX9 U6265 ( .A(n9335), .Z(n9374) );
HS65_LH_IVX9 U6266 ( .A(n9335), .Z(n9375) );
HS65_LL_NOR2X2 U6269 ( .A(n4494), .B(n4500), .Z(n3905) );
HS65_LH_AOI12X3 U6274 ( .A(n4516), .B(n4504), .C(n4503), .Z(n4510) );
HS65_LL_NAND2X2 U6276 ( .A(\lte_x_59/B[18] ), .B(n4351), .Z(n3838) );
HS65_LL_NOR2X2 U6277 ( .A(n4502), .B(n4501), .Z(n4503) );
HS65_LH_NAND2X2 U6284 ( .A(n2858), .B(n4351), .Z(n4129) );
HS65_LL_AOI211X1 U6285 ( .A(n2842), .B(n4351), .C(n4024), .D(n4023), .Z(
n4579) );
HS65_LH_NAND2X2 U6297 ( .A(\lte_x_59/B[9] ), .B(n4351), .Z(n4591) );
HS65_LH_NAND2X2 U6298 ( .A(n2851), .B(n4351), .Z(n3543) );
HS65_LH_NAND2X2 U6310 ( .A(\lte_x_59/B[16] ), .B(n4351), .Z(n3984) );
HS65_LH_NAND2X2 U6311 ( .A(\lte_x_59/B[15] ), .B(n4351), .Z(n4059) );
HS65_LL_NAND2X2 U6317 ( .A(\sub_x_53/A[25] ), .B(n4351), .Z(n3719) );
HS65_LL_NAND2X4 U6332 ( .A(\lte_x_59/B[28] ), .B(n4351), .Z(n3759) );
HS65_LH_OAI21X3 U6335 ( .A(n5394), .B(n5393), .C(n5392), .Z(n5414) );
HS65_LL_NAND2X2 U6337 ( .A(n3327), .B(n9179), .Z(n3324) );
HS65_LH_NAND2X2 U6338 ( .A(n3327), .B(n9343), .Z(n3157) );
HS65_LL_NAND2X2 U6339 ( .A(n3327), .B(n9171), .Z(n3243) );
HS65_LH_NAND2X2 U6347 ( .A(n3327), .B(n9342), .Z(n3148) );
HS65_LH_NAND2X2 U6349 ( .A(n3327), .B(n9343), .Z(n3209) );
HS65_LH_NAND2X2 U6355 ( .A(n3327), .B(n9342), .Z(n3172) );
HS65_LH_NAND2X2 U6356 ( .A(n3327), .B(n9342), .Z(n3180) );
HS65_LH_NAND2X2 U6360 ( .A(n3327), .B(n9185), .Z(n3263) );
HS65_LH_NAND2X2 U6366 ( .A(n3327), .B(n9173), .Z(n3230) );
HS65_LL_NAND2X2 U6367 ( .A(n3327), .B(n9175), .Z(n3328) );
HS65_LH_NAND2X2 U6372 ( .A(n3327), .B(n9341), .Z(n3191) );
HS65_LL_NAND2X4 U6392 ( .A(n3327), .B(n9033), .Z(n3314) );
HS65_LL_NOR3X1 U6402 ( .A(n4471), .B(n4470), .C(n4469), .Z(n4472) );
HS65_LL_OAI12X3 U6413 ( .A(n4468), .B(n5146), .C(n4467), .Z(n4469) );
HS65_LH_AOI12X2 U6426 ( .A(n3474), .B(n4544), .C(n3868), .Z(n3869) );
HS65_LL_NAND2AX4 U6435 ( .A(n5473), .B(n5472), .Z(n5481) );
HS65_LL_NAND2X2 U6438 ( .A(n4805), .B(n4811), .Z(n5547) );
HS65_LL_AOI12X2 U6447 ( .A(n5615), .B(n5248), .C(n5247), .Z(n5253) );
HS65_LH_NOR2X2 U6450 ( .A(n4806), .B(n4506), .Z(n4505) );
HS65_LH_NAND2X2 U6459 ( .A(n5448), .B(n4329), .Z(n4339) );
HS65_LH_IVX2 U6460 ( .A(n4305), .Z(n4306) );
HS65_LH_AOI12X6 U6474 ( .A(n4303), .B(n4305), .C(n4231), .Z(n4235) );
HS65_LL_OAI12X2 U6480 ( .A(n4331), .B(n4328), .C(n5448), .Z(n5452) );
HS65_LL_OAI12X2 U6490 ( .A(n4331), .B(n4328), .C(n5448), .Z(n4305) );
HS65_LL_NAND2X4 U6493 ( .A(n9369), .B(n9042), .Z(n8294) );
HS65_LL_IVX4 U6496 ( .A(\u_DataPath/dataOut_exe_i [29]), .Z(n4213) );
HS65_LL_NAND2X2 U6501 ( .A(n9366), .B(n9079), .Z(n8312) );
HS65_LL_NAND2X2 U6504 ( .A(n9368), .B(n9006), .Z(n8432) );
HS65_LL_NAND2X4 U6507 ( .A(n9368), .B(n9101), .Z(n8398) );
HS65_LL_NAND2X4 U6519 ( .A(n9366), .B(n9043), .Z(n7836) );
HS65_LL_NAND2X4 U6530 ( .A(n9365), .B(n9044), .Z(n8290) );
HS65_LL_NAND2X4 U6531 ( .A(n9366), .B(n9015), .Z(n8340) );
HS65_LL_NAND2X4 U6532 ( .A(n8166), .B(n6138), .Z(n6149) );
HS65_LL_AOI22X3 U6538 ( .A(n8868), .B(n9034), .C(n9368), .D(n8946), .Z(n7851) );
HS65_LL_NAND2X2 U6539 ( .A(n9369), .B(n9014), .Z(n8307) );
HS65_LL_NAND2X2 U6547 ( .A(n9365), .B(n9249), .Z(n8436) );
HS65_LL_NAND2X2 U6551 ( .A(n9369), .B(n9045), .Z(n8333) );
HS65_LL_NAND2X4 U6554 ( .A(n4322), .B(n5210), .Z(n4324) );
HS65_LL_AOI21X2 U6556 ( .A(n4322), .B(n5211), .C(n4321), .Z(n4323) );
HS65_LL_NOR2X6 U6557 ( .A(n3682), .B(n3800), .Z(n3503) );
HS65_LL_NOR2X5 U6558 ( .A(n2853), .B(n5567), .Z(n3800) );
HS65_LL_NAND2X11 U6560 ( .A(n3157), .B(n3156), .Z(n5567) );
HS65_LL_NOR3X4 U6565 ( .A(n5486), .B(n5485), .C(n5484), .Z(n5487) );
HS65_LL_CBI4I1X3 U6567 ( .A(n5508), .B(n5367), .C(n5366), .D(n5365), .Z(
n5484) );
HS65_LL_AOI12X2 U6568 ( .A(n5643), .B(n5155), .C(n5154), .Z(n5156) );
HS65_LL_OAI12X2 U6572 ( .A(n5153), .B(n5152), .C(n5151), .Z(n5154) );
HS65_LL_IVX7 U6585 ( .A(n5646), .Z(n5229) );
HS65_LL_NOR2X2 U6591 ( .A(\lte_x_59/B[3] ), .B(n5089), .Z(n4570) );
HS65_LL_AOI12X2 U6594 ( .A(n4638), .B(n4645), .C(n4640), .Z(n4145) );
HS65_LL_CNIVX3 U6595 ( .A(n9376), .Z(n3327) );
HS65_LL_CNIVX3 U6598 ( .A(n3593), .Z(n5425) );
HS65_LL_AND2X4 U6603 ( .A(n3132), .B(n7802), .Z(n3133) );
HS65_LL_AOI21X2 U6605 ( .A(n5229), .B(n3723), .C(n3722), .Z(n3724) );
HS65_LL_AOI12X2 U6618 ( .A(n3727), .B(n5624), .C(n3726), .Z(n3728) );
HS65_LH_OAI21X2 U6619 ( .A(n3725), .B(n5656), .C(n3724), .Z(n3726) );
HS65_LL_MUXI21X5 U6620 ( .D0(n2972), .D1(n2971), .S0(
\u_DataPath/cw_towb_i [0]), .Z(n8393) );
HS65_LL_CNIVX3 U6623 ( .A(\u_DataPath/from_mem_data_out_i [4]), .Z(n2971) );
HS65_LL_NAND3X2 U6624 ( .A(n4163), .B(n4162), .C(n4161), .Z(n5671) );
HS65_LL_NAND2X5 U6625 ( .A(n8177), .B(n7802), .Z(n8486) );
HS65_LL_IVX7 U6626 ( .A(n4953), .Z(n4148) );
HS65_LH_AOI12X2 U6628 ( .A(n5144), .B(n4875), .C(n4118), .Z(n4125) );
HS65_LL_IVX4 U6632 ( .A(n4113), .Z(n4875) );
HS65_LH_OAI21X2 U6636 ( .A(n5173), .B(n4117), .C(n4116), .Z(n4118) );
HS65_LL_AOI21X2 U6637 ( .A(n3529), .B(n4114), .C(n5041), .Z(n4115) );
HS65_LL_NAND2X2 U6638 ( .A(n5648), .B(n5040), .Z(n4114) );
HS65_LL_OAI21X3 U6652 ( .A(n4821), .B(n4817), .C(n4819), .Z(n4538) );
HS65_LL_NAND2X4 U6654 ( .A(\lte_x_59/B[1] ), .B(n3294), .Z(n4819) );
HS65_LL_NOR2X5 U6657 ( .A(\lte_x_59/B[1] ), .B(n3294), .Z(n4817) );
HS65_LH_IVX2 U6658 ( .A(n4805), .Z(n3294) );
HS65_LL_AOI21X4 U6659 ( .A(n5624), .B(n4446), .C(n4445), .Z(n4447) );
HS65_LL_NAND3X5 U6661 ( .A(n4444), .B(n4443), .C(n4442), .Z(n4445) );
HS65_LH_NOR2X2 U6662 ( .A(n4855), .B(n4435), .Z(n4436) );
HS65_LL_AND2ABX9 U6663 ( .A(n4458), .B(n4842), .Z(n5618) );
HS65_LL_NOR3X7 U6664 ( .A(n4782), .B(n4783), .C(n4784), .Z(n4785) );
HS65_LL_NAND3X3 U6666 ( .A(n5516), .B(n5517), .C(n5408), .Z(n4684) );
HS65_LL_NOR2X5 U6667 ( .A(n5406), .B(n5294), .Z(n5408) );
HS65_LL_OAI112X1 U6670 ( .A(n9129), .B(n8880), .C(n8308), .D(n9086), .Z(
\u_DataPath/from_mem_data_out_i [15]) );
HS65_LLS_XOR2X3 U6671 ( .A(n4635), .B(n4634), .Z(n4636) );
HS65_LL_AOI12X2 U6675 ( .A(n4633), .B(n4632), .C(n4631), .Z(n4634) );
HS65_LL_AOI12X12 U6687 ( .A(n5906), .B(n5908), .C(n5740), .Z(n5746) );
HS65_LL_OAI12X2 U6701 ( .A(n5855), .B(n5854), .C(n5853), .Z(n5856) );
HS65_LH_OAI21X3 U6704 ( .A(n5867), .B(n5817), .C(n5819), .Z(n5813) );
HS65_LL_NOR2X3 U6705 ( .A(n3629), .B(n3747), .Z(n5446) );
HS65_LL_NOR2AX3 U6706 ( .A(n4233), .B(n4332), .Z(n4234) );
HS65_LH_OAI21X2 U6707 ( .A(n3747), .B(n3632), .C(n3749), .Z(n3633) );
HS65_LH_OAI12X2 U6708 ( .A(n4333), .B(n4332), .C(n4331), .Z(n4334) );
HS65_LL_NOR2X6 U6710 ( .A(n2853), .B(n3384), .Z(n3747) );
HS65_LL_NAND2AX7 U6714 ( .A(n7634), .B(n7622), .Z(n4227) );
HS65_LL_NAND2AX4 U6718 ( .A(n7634), .B(n4380), .Z(n4416) );
HS65_LL_AND2X4 U6719 ( .A(n5217), .B(n4301), .Z(n5708) );
HS65_LL_NAND2X2 U6721 ( .A(n5217), .B(n3510), .Z(n3511) );
HS65_LL_AND2X4 U6734 ( .A(n5217), .B(n3849), .Z(n3850) );
HS65_LL_NAND2X2 U6741 ( .A(n5217), .B(n3944), .Z(n3945) );
HS65_LL_NAND2X4 U6745 ( .A(n5217), .B(n3995), .Z(n3996) );
HS65_LH_NAND2X2 U6753 ( .A(n5217), .B(n4479), .Z(n4485) );
HS65_LL_IVX9 U6768 ( .A(n7634), .Z(n5643) );
HS65_LL_CNIVX3 U6778 ( .A(n5217), .Z(n7634) );
HS65_LH_NAND2X2 U6796 ( .A(\u_DataPath/cw_to_ex_i [3]), .B(n5492), .Z(n3450)
);
HS65_LL_NOR2X2 U6797 ( .A(\u_DataPath/cw_to_ex_i [3]), .B(
\u_DataPath/cw_to_ex_i [4]), .Z(n3470) );
HS65_LL_NAND2X5 U6799 ( .A(n7631), .B(n5280), .Z(n5281) );
HS65_LLS_XNOR2X6 U6800 ( .A(n5279), .B(n5278), .Z(n5280) );
HS65_LL_MX41X4 U6801 ( .D0(n8440), .S0(n9289), .D1(n8441), .S1(n9274), .D2(
n8439), .S2(n9296), .D3(n8438), .S3(n9281), .Z(
\u_DataPath/from_mem_data_out_i [0]) );
HS65_LL_OAI21X2 U6804 ( .A(n4534), .B(n4533), .C(n2928), .Z(n5705) );
HS65_LL_NOR3X4 U6812 ( .A(n4532), .B(n4531), .C(n4530), .Z(n2928) );
HS65_LH_IVX9 U6813 ( .A(\u_DataPath/from_mem_data_out_i [0]), .Z(n3015) );
HS65_LL_NOR2X2 U6819 ( .A(n4700), .B(n5129), .Z(n3779) );
HS65_LL_NAND2X7 U6840 ( .A(\lte_x_59/B[15] ), .B(n4677), .Z(n3893) );
HS65_LH_CNIVX7 U6850 ( .A(n5062), .Z(n4677) );
HS65_LL_NAND3X2 U6851 ( .A(n8775), .B(n9169), .C(n8078), .Z(n8079) );
HS65_LL_NOR2X9 U6867 ( .A(\u_DataPath/cw_to_ex_i [4]), .B(n5120), .Z(n3422)
);
HS65_LH_IVX9 U6868 ( .A(n3422), .Z(n3423) );
HS65_LL_NAND2X4 U6870 ( .A(n5491), .B(n3422), .Z(n3442) );
HS65_LL_NAND3X2 U6916 ( .A(n5090), .B(n5474), .C(n5319), .Z(n4662) );
HS65_LL_NOR2X3 U6923 ( .A(n4661), .B(n5548), .Z(n5319) );
HS65_LL_NAND2X5 U6927 ( .A(\sub_x_53/A[2] ), .B(n3415), .Z(n4573) );
HS65_LL_OAI12X2 U6928 ( .A(n5546), .B(n5318), .C(n4662), .Z(n4669) );
HS65_LL_NAND2X2 U6931 ( .A(n5090), .B(n4573), .Z(n5546) );
HS65_LL_IVX7 U6943 ( .A(\u_DataPath/from_mem_data_out_i [2]), .Z(n2933) );
HS65_LL_NAND2X7 U6957 ( .A(n3512), .B(n3511), .Z(n3513) );
HS65_LLS_XNOR2X6 U6963 ( .A(n3509), .B(n3508), .Z(n3510) );
HS65_LL_IVX7 U6964 ( .A(\u_DataPath/from_mem_data_out_i [3]), .Z(n2969) );
HS65_LL_OAI22X1 U6971 ( .A(n3333), .B(\u_DataPath/dataOut_exe_i [5]), .C(
n8391), .D(n3340), .Z(n3334) );
HS65_LH_NOR2X5 U6975 ( .A(n8391), .B(n9401), .Z(n4654) );
HS65_LLS_XNOR2X3 U6984 ( .A(n4884), .B(n4883), .Z(n4885) );
HS65_LL_NOR3X4 U6988 ( .A(n3465), .B(n3464), .C(n3463), .Z(n3466) );
HS65_LL_NAND2AX4 U7002 ( .A(n3438), .B(n3437), .Z(n3465) );
HS65_LL_OAI31X2 U7006 ( .A(n5177), .B(n4581), .C(n3713), .D(n3454), .Z(n3464) );
HS65_LH_NAND2X5 U7010 ( .A(n5170), .B(n5667), .Z(n3437) );
HS65_LL_NOR3X4 U7012 ( .A(\u_DataPath/u_idexreg/N15 ), .B(n8103), .C(
\u_DataPath/u_idexreg/N10 ), .Z(n8126) );
HS65_LH_NAND2X7 U7014 ( .A(n7631), .B(n4414), .Z(n4415) );
HS65_LL_NOR2X3 U7015 ( .A(\lte_x_59/B[6] ), .B(n2865), .Z(n4643) );
HS65_LL_NAND2X4 U7037 ( .A(n3323), .B(n3322), .Z(n3325) );
HS65_LL_NAND3X5 U7045 ( .A(n5220), .B(n5219), .C(n5218), .Z(n5221) );
HS65_LL_NAND2X4 U7048 ( .A(n5217), .B(n5216), .Z(n5218) );
HS65_LL_NOR2X5 U7049 ( .A(\lte_x_59/B[16] ), .B(n5021), .Z(n3560) );
HS65_LL_NAND2X5 U7051 ( .A(n3207), .B(n8526), .Z(n3208) );
HS65_LLS_XNOR2X3 U7063 ( .A(n5215), .B(n5214), .Z(n5216) );
HS65_LL_NAND2X4 U7069 ( .A(n5672), .B(n6122), .Z(n4277) );
HS65_LL_NAND3X5 U7082 ( .A(n4266), .B(n4265), .C(n4264), .Z(n6122) );
HS65_LL_AND2X4 U7085 ( .A(n9211), .B(n9366), .Z(n8424) );
HS65_LL_CNIVX7 U7097 ( .A(\u_DataPath/dataOut_exe_i [1]), .Z(n8177) );
HS65_LL_NOR2X3 U7098 ( .A(n4701), .B(n4582), .Z(n3953) );
HS65_LL_NAND2X7 U7100 ( .A(n8166), .B(n6145), .Z(n6152) );
HS65_LH_IVX2 U7104 ( .A(\u_DataPath/jaddr_i [25]), .Z(n8166) );
HS65_LL_AND2ABX18 U7109 ( .A(n3425), .B(n5088), .Z(n4836) );
HS65_LL_AOI21X2 U7114 ( .A(n5661), .B(n5239), .C(n5238), .Z(n5245) );
HS65_LL_IVX7 U7121 ( .A(n4609), .Z(n5239) );
HS65_LL_AOI21X2 U7154 ( .A(n5229), .B(n5228), .C(n5227), .Z(n5246) );
HS65_LL_NAND3AX6 U7160 ( .A(n3829), .B(n3828), .C(n3827), .Z(n3844) );
HS65_LL_CNIVX3 U7161 ( .A(n4840), .Z(n3858) );
HS65_LL_NOR2AX3 U7172 ( .A(n3789), .B(n2860), .Z(n3820) );
HS65_LLS_XNOR2X3 U7173 ( .A(n4482), .B(n4645), .Z(n4483) );
HS65_LL_AOI21X2 U7180 ( .A(n4646), .B(n4645), .C(n4644), .Z(n4647) );
HS65_LL_OAI21X2 U7183 ( .A(n3394), .B(n8485), .C(n3395), .Z(n3293) );
HS65_LL_MX41X4 U7194 ( .D0(n8441), .S0(n9275), .D1(n8440), .S1(n9290), .D2(
n9297), .S2(n8439), .D3(n8438), .S3(n9282), .Z(
\u_DataPath/from_mem_data_out_i [1]) );
HS65_LL_NAND4ABX3 U7197 ( .A(n8106), .B(n8105), .C(n8104), .D(n8126), .Z(
\u_DataPath/cw_to_ex_i [2]) );
HS65_LL_NAND2X2 U7208 ( .A(n5667), .B(n3522), .Z(n3523) );
HS65_LL_NOR2X2 U7210 ( .A(\u_DataPath/cw_to_ex_i [1]), .B(n5079), .Z(n5117)
);
HS65_LH_OAI21X2 U7217 ( .A(n5173), .B(n5204), .C(n3880), .Z(n3881) );
HS65_LH_AOI22X1 U7218 ( .A(n4951), .B(n4615), .C(n5667), .D(n4614), .Z(n4619) );
HS65_LH_NAND2X2 U7223 ( .A(n5667), .B(n5228), .Z(n3714) );
HS65_LL_NOR2X2 U7224 ( .A(\u_DataPath/cw_to_ex_i [1]), .B(n5119), .Z(n4782)
);
HS65_LL_NAND2X2 U7225 ( .A(n5667), .B(n5174), .Z(n4848) );
HS65_LH_NOR2X2 U7233 ( .A(n5173), .B(n4357), .Z(n4358) );
HS65_LL_OAI21X2 U7245 ( .A(n5173), .B(n4526), .C(n4525), .Z(n4531) );
HS65_LL_NAND2X2 U7255 ( .A(n5667), .B(n5617), .Z(n4267) );
HS65_LH_OAI22X1 U7275 ( .A(n4435), .B(n5173), .C(n4954), .D(n3858), .Z(n3829) );
HS65_LL_NOR2X2 U7285 ( .A(n5173), .B(n4355), .Z(n3597) );
HS65_LL_AOI12X2 U7306 ( .A(n5667), .B(n5243), .C(n5242), .Z(n5244) );
HS65_LL_NAND2X2 U7308 ( .A(\u_DataPath/cw_to_ex_i [1]), .B(
\u_DataPath/cw_to_ex_i [2]), .Z(n4965) );
HS65_LL_NOR2X2 U7314 ( .A(\u_DataPath/u_idexreg/N3 ), .B(n5463), .Z(n5469)
);
HS65_LL_NOR2X2 U7333 ( .A(\u_DataPath/cw_to_ex_i [1]), .B(n7617), .Z(n5217)
);
HS65_LL_NAND2X4 U7356 ( .A(n5463), .B(n5492), .Z(n5120) );
HS65_LL_NAND2X4 U7376 ( .A(\u_DataPath/cw_to_ex_i [1]), .B(n5492), .Z(n3417)
);
HS65_LL_IVX2 U7379 ( .A(\u_DataPath/cw_to_ex_i [1]), .Z(n5463) );
HS65_LH_IVX2 U7381 ( .A(n8704), .Z(n3122) );
HS65_LL_AND3X18 U7386 ( .A(n8101), .B(n8072), .C(n8071), .Z(n9376) );
HS65_LL_OA12X4 U7387 ( .A(n9242), .B(n8453), .C(n7913), .Z(n9377) );
HS65_LH_OA222X4 U7393 ( .A(n9166), .B(n8898), .C(n9051), .D(n9127), .E(n8880), .F(n9268), .Z(n9378) );
HS65_LL_OA12X4 U7394 ( .A(n9268), .B(n8453), .C(n7913), .Z(n9379) );
HS65_LL_OA12X4 U7395 ( .A(n9123), .B(n8453), .C(n7913), .Z(n9380) );
HS65_LH_IVX2 U7396 ( .A(n8267), .Z(\u_DataPath/dataOut_exe_i [8]) );
HS65_LL_OA112X4 U7397 ( .A(n9246), .B(n8880), .C(n8291), .D(n9086), .Z(n9381) );
HS65_LL_OA12X4 U7399 ( .A(n9120), .B(n8453), .C(n9086), .Z(n9383) );
HS65_LL_OA12X4 U7401 ( .A(n9247), .B(n8453), .C(n9086), .Z(n9384) );
HS65_LL_OA12X4 U7404 ( .A(n9121), .B(n8453), .C(n7913), .Z(n9385) );
HS65_LL_OA112X4 U7405 ( .A(n9244), .B(n8880), .C(n8346), .D(n9086), .Z(n9386) );
HS65_LL_OA12X4 U7408 ( .A(n9124), .B(n8453), .C(n7913), .Z(n9387) );
HS65_LL_OA12X4 U7409 ( .A(n9243), .B(n8453), .C(n9086), .Z(n9388) );
HS65_LH_OA12X9 U7411 ( .A(n9245), .B(n8453), .C(n7913), .Z(n9389) );
HS65_LL_OA12X4 U7413 ( .A(n9125), .B(n8453), .C(n7913), .Z(n9391) );
HS65_LL_OA12X4 U7414 ( .A(n9248), .B(n8453), .C(n7913), .Z(n9392) );
HS65_LL_OA12X4 U7415 ( .A(n9244), .B(n8453), .C(n7913), .Z(n9393) );
HS65_LL_OA12X4 U7450 ( .A(n9126), .B(n8453), .C(n7913), .Z(n9394) );
HS65_LL_OA12X4 U7454 ( .A(n9129), .B(n8453), .C(n9086), .Z(n9395) );
HS65_LL_OA112X4 U7456 ( .A(n8880), .B(n9245), .C(n8273), .D(n9086), .Z(n9396) );
HS65_LH_IVX2 U7461 ( .A(n8297), .Z(\u_DataPath/dataOut_exe_i [7]) );
HS65_LL_OA112X4 U7466 ( .A(n9247), .B(n8880), .C(n8341), .D(n9086), .Z(n9397) );
HS65_LL_OA112X4 U7473 ( .A(n9242), .B(n8880), .C(n8334), .D(n9086), .Z(n9398) );
HS65_LH_OA22X4 U7480 ( .A(n8906), .B(n9269), .C(n9140), .D(n8758), .Z(n9399)
);
HS65_LH_OA22X4 U7494 ( .A(n8906), .B(n9270), .C(n9140), .D(n8760), .Z(n9400)
);
HS65_LL_OR3ABCX35 U7500 ( .A(n3217), .B(n2966), .C(n3216), .Z(n9401) );
HS65_LH_IVX18 U7524 ( .A(n2846), .Z(n2847) );
HS65_LLS_XNOR2X3 U7531 ( .A(n4821), .B(n4820), .Z(n9402) );
HS65_LH_AO22X4 U7551 ( .A(n9261), .B(n9136), .C(n9134), .D(n8936), .Z(n9403)
);
HS65_LH_AO22X4 U7555 ( .A(n9056), .B(n9136), .C(n9134), .D(n8956), .Z(n9404)
);
HS65_LH_AO22X4 U7575 ( .A(n9089), .B(n9136), .C(n9134), .D(n8953), .Z(n9405)
);
HS65_LH_AO22X4 U7577 ( .A(n9094), .B(n9136), .C(n9134), .D(n8957), .Z(n9406)
);
HS65_LH_AO22X4 U7583 ( .A(n9259), .B(n9136), .C(n9134), .D(n8950), .Z(n9407)
);
HS65_LH_AO22X4 U7584 ( .A(n9091), .B(n9136), .C(n9134), .D(n8955), .Z(n9408)
);
HS65_LH_AO22X4 U7591 ( .A(n8881), .B(n9136), .C(n9134), .D(n8954), .Z(n9409)
);
HS65_LH_AO22X4 U7598 ( .A(n9095), .B(n9136), .C(n9134), .D(n8959), .Z(n9410)
);
HS65_LH_AO22X4 U7599 ( .A(n9106), .B(n9136), .C(n9134), .D(n8958), .Z(n9411)
);
HS65_LH_AO22X4 U7604 ( .A(n9088), .B(n9136), .C(n9134), .D(n9064), .Z(n9412)
);
HS65_LH_AO22X4 U7605 ( .A(n9096), .B(n9136), .C(n9134), .D(n8952), .Z(n9413)
);
HS65_LH_AO22X4 U7606 ( .A(n9071), .B(n9136), .C(n9133), .D(n8977), .Z(n9414)
);
HS65_LH_AO22X4 U7660 ( .A(n9271), .B(n9188), .C(n9133), .D(n8990), .Z(n9415)
);
HS65_LH_AO22X4 U7676 ( .A(n9257), .B(n9188), .C(n9133), .D(n9023), .Z(n9416)
);
HS65_LH_AO22X4 U7677 ( .A(n9107), .B(n9188), .C(n9133), .D(n9024), .Z(n9417)
);
HS65_LH_AO22X4 U7686 ( .A(n9136), .B(n9200), .C(n9134), .D(n8949), .Z(n9418)
);
HS65_LH_IVX7 U7710 ( .A(n8704), .Z(n2784) );
HS65_LH_AO22X4 U7727 ( .A(n9192), .B(n9265), .C(n9132), .D(n9067), .Z(n9419)
);
HS65_LH_AO22X4 U7734 ( .A(n9192), .B(n9161), .C(n9132), .D(n8989), .Z(n9420)
);
HS65_LH_AO22X4 U7743 ( .A(n9192), .B(n9143), .C(n9132), .D(n8995), .Z(n9421)
);
HS65_LH_AO22X4 U7746 ( .A(n9192), .B(n9158), .C(n9132), .D(n8978), .Z(n9422)
);
HS65_LH_AO22X4 U7749 ( .A(n9192), .B(n9157), .C(n9132), .D(n8973), .Z(n9423)
);
HS65_LH_AO22X4 U7751 ( .A(n9192), .B(n9162), .C(n9132), .D(n8986), .Z(n9424)
);
HS65_LH_AO22X4 U7763 ( .A(n9192), .B(n9160), .C(n9132), .D(n9087), .Z(n9425)
);
HS65_LH_AO22X4 U7764 ( .A(n9192), .B(n9156), .C(n9132), .D(n8962), .Z(n9426)
);
HS65_LH_AO22X4 U7771 ( .A(n9192), .B(n9155), .C(n9132), .D(n8976), .Z(n9427)
);
HS65_LH_AO22X4 U7776 ( .A(n9191), .B(n9163), .C(n9131), .D(n8991), .Z(n9428)
);
HS65_LH_AO22X4 U7779 ( .A(n9191), .B(n9159), .C(n9131), .D(n8988), .Z(n9429)
);
HS65_LH_NOR2X2 U7780 ( .A(n9233), .B(n7117), .Z(n2877) );
HS65_LH_NAND4ABX3 U7809 ( .A(n9347), .B(n8755), .C(n9016), .D(n8071), .Z(
\u_DataPath/cw_exmem_i [10]) );
HS65_LL_DFPQX9 clk_r_REG490_S3 ( .D(n8635), .CP(clk), .Q(n9066) );
HS65_LL_OAI211X5 U3847 ( .A(n9149), .B(n9012), .C(n8877), .D(n8093), .Z(
\u_DataPath/cw_to_ex_i [3]) );
HS65_LL_NAND2AX7 U6275 ( .A(n4867), .B(n4866), .Z(n5686) );
HS65_LH_DFPQX4 clk_r_REG48_S1 ( .D(n8580), .CP(clk), .Q(n3023) );
HS65_LH_DFPQX4 clk_r_REG435_S3 ( .D(n8270), .CP(clk), .Q(n9081) );
HS65_LL_DFPQX4 clk_r_REG387_S2 ( .D(\u_DataPath/data_read_ex_2_i [0]), .CP(
clk), .Q(n9431) );
HS65_LH_DFPQX4 clk_r_REG431_S2 ( .D(n9115), .CP(clk), .Q(n9114) );
HS65_LL_DFPQNX9 clk_r_REG450_S1 ( .D(n8137), .CP(clk), .QN(
\u_DataPath/cw_towb_i [0]) );
HS65_LH_DFPQX9 clk_r_REG76_S2 ( .D(n8473), .CP(clk), .Q(n9027) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[31][27] (
.G(\u_DataPath/u_decode_unit/reg_file0/N92 ), .D(n7926), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][27] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[18][24] (
.G(\u_DataPath/u_decode_unit/reg_file0/N137 ), .D(n7984), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][24] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[26][17] (
.G(\u_DataPath/u_decode_unit/reg_file0/N129 ), .D(n7986), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][17] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[26][9] (
.G(\u_DataPath/u_decode_unit/reg_file0/N129 ), .D(n8013), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][9] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[26][27] (
.G(\u_DataPath/u_decode_unit/reg_file0/N129 ), .D(n7926), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][27] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[30][17] (
.G(\u_DataPath/u_decode_unit/reg_file0/N125 ), .D(n7986), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][17] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[30][9] (
.G(\u_DataPath/u_decode_unit/reg_file0/N125 ), .D(n8013), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][9] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[30][23] (
.G(\u_DataPath/u_decode_unit/reg_file0/N125 ), .D(n7995), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[30][23] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[28][0] (
.G(\u_DataPath/u_decode_unit/reg_file0/N127 ), .D(n7998), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][0] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[29][17] (
.G(\u_DataPath/u_decode_unit/reg_file0/N126 ), .D(n7987), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[29][17] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[28][22] (
.G(\u_DataPath/u_decode_unit/reg_file0/N127 ), .D(n7977), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][22] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[28][21] (
.G(\u_DataPath/u_decode_unit/reg_file0/N127 ), .D(n7965), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][21] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[28][23] (
.G(\u_DataPath/u_decode_unit/reg_file0/N127 ), .D(n7995), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][23] ) );
HS65_LH_LDHQX4 \u_DataPath/u_decode_unit/reg_file0/bank_register_reg[28][11] (
.G(\u_DataPath/u_decode_unit/reg_file0/N127 ), .D(n7941), .Q(
\u_DataPath/u_decode_unit/reg_file0/bank_register[28][11] ) );
HS65_LH_DFPQX4 clk_r_REG660_S1 ( .D(Data_out_fromRAM[24]), .CP(clk), .Q(
n9296) );
HS65_LH_DFPQX4 clk_r_REG686_S1 ( .D(Data_out_fromRAM[6]), .CP(clk), .Q(n9280) );
HS65_LH_DFPQX4 clk_r_REG395_S2 ( .D(n2851), .CP(clk), .Q(n9261) );
HS65_LH_DFPQX9 clk_r_REG657_S1 ( .D(n8319), .CP(clk), .Q(n9243) );
HS65_LH_DFPQX4 clk_r_REG368_S2 ( .D(n9212), .CP(clk), .Q(n9211) );
HS65_LH_DFPQX4 clk_r_REG270_S1 ( .D(\u_DataPath/branch_target_i [9]), .CP(
clk), .Q(n9195) );
HS65_LH_DFPQX4 clk_r_REG589_S2 ( .D(n9179), .CP(clk), .Q(n9178) );
HS65_LH_DFPRQX4 clk_r_REG512_S1 ( .D(n7897), .CP(clk), .RN(n7879), .Q(n9132)
);
HS65_LH_DFPQX4 clk_r_REG451_S1 ( .D(\u_DataPath/cw_tomem_i [4]), .CP(clk),
.Q(n9112) );
HS65_LH_DFPQX4 clk_r_REG60_S5 ( .D(\lte_x_59/B[6] ), .CP(clk), .Q(n9095) );
HS65_LH_DFPQX4 clk_r_REG149_S2 ( .D(\u_DataPath/u_execute/link_value_i [28]),
.CP(clk), .Q(n9057) );
HS65_LH_DFPQX4 clk_r_REG121_S2 ( .D(\u_DataPath/u_execute/link_value_i [10]),
.CP(clk), .Q(n9042) );
HS65_LH_DFPQX4 clk_r_REG573_S3 ( .D(n8086), .CP(clk), .Q(n9007) );
HS65_LH_DFPRQX4 clk_r_REG154_S4 ( .D(\u_DataPath/pc_4_i [22]), .CP(clk),
.RN(n9354), .Q(n8988) );
HS65_LH_DFPQX4 clk_r_REG268_S2 ( .D(\u_DataPath/u_execute/resAdd1_i [11]),
.CP(clk), .Q(n8950) );
HS65_LH_DFPQX4 clk_r_REG378_S2 ( .D(\u_DataPath/u_execute/resAdd1_i [1]),
.CP(clk), .Q(n8935) );
HS65_LH_DFPQX4 clk_r_REG122_S1 ( .D(\u_DataPath/branch_target_i [13]), .CP(
clk), .Q(n8919) );
HS65_LH_DFPQX4 clk_r_REG61_S5 ( .D(n8479), .CP(clk), .Q(n8901) );
HS65_LH_DFPQX4 clk_r_REG146_S2 ( .D(\u_DataPath/u_execute/link_value_i [29]),
.CP(clk), .Q(n8870) );
HS65_LH_DFPRQX4 clk_r_REG604_S3 ( .D(\u_DataPath/immediate_ext_dec_i [13]),
.CP(clk), .RN(n9354), .Q(n8790) );
HS65_LH_DFPRQX4 clk_r_REG559_S3 ( .D(\u_DataPath/jaddr_i [22]), .CP(clk),
.RN(n9354), .Q(n8765) );
HS65_LH_DFPQX4 clk_r_REG29_S2 ( .D(\u_DataPath/mem_writedata_out_i [27]),
.CP(clk), .Q(n8748) );
HS65_LH_DFPQX4 clk_r_REG81_S1 ( .D(\u_DataPath/mem_writedata_out_i [24]),
.CP(clk), .Q(n8732) );
HS65_LL_IVX9 U3856 ( .A(n8898), .Z(n8399) );
HS65_LL_NAND2X7 U7793 ( .A(n9102), .B(n9066), .Z(n8114) );
HS65_LH_OAI12X3 U6125 ( .A(n9190), .B(n9027), .C(n8307), .Z(
\u_DataPath/dataOut_exe_i [15]) );
HS65_LL_BFX18 U4321 ( .A(n9401), .Z(n7868) );
HS65_LL_NOR2X6 U3948 ( .A(n3214), .B(n3213), .Z(\lte_x_59/B[8] ) );
HS65_LL_OAI12X3 U3808 ( .A(n3349), .B(n4712), .C(n3348), .Z(n3419) );
HS65_LH_IVX9 U6106 ( .A(n5053), .Z(n2871) );
HS65_LL_OAI12X6 U6982 ( .A(n4654), .B(n3339), .C(n4655), .Z(n5040) );
HS65_LL_AOI21X2 U6075 ( .A(n9376), .B(n7846), .C(n3419), .Z(n3430) );
HS65_LL_NOR3AX9 U3639 ( .A(n4971), .B(n4973), .C(n3059), .Z(\lte_x_59/B[28] ) );
HS65_LL_NOR2X6 U5623 ( .A(n3086), .B(n3085), .Z(\lte_x_59/B[18] ) );
HS65_LL_AND2ABX18 U3927 ( .A(n3096), .B(n3095), .Z(\lte_x_59/B[16] ) );
HS65_LL_NAND2X7 U5585 ( .A(n3421), .B(n3422), .Z(n5179) );
HS65_LL_IVX9 U3750 ( .A(n3443), .Z(n3529) );
HS65_LL_IVX27 U3472 ( .A(n4795), .Z(n2864) );
HS65_LH_IVX9 U6673 ( .A(n5180), .Z(n3382) );
HS65_LH_NOR2AX6 U3718 ( .A(n3967), .B(n2872), .Z(n4550) );
HS65_LL_NOR2AX6 U3894 ( .A(n3210), .B(n4420), .Z(n5194) );
HS65_LH_NOR2AX3 U3700 ( .A(n9019), .B(n2994), .Z(n3014) );
HS65_LL_IVX18 U3452 ( .A(n2774), .Z(Data_in[23]) );
HS65_LL_IVX18 U3453 ( .A(n2776), .Z(Data_in[9]) );
HS65_LL_IVX18 U3454 ( .A(n2778), .Z(Data_in[18]) );
HS65_LL_IVX18 U3459 ( .A(n2819), .Z(Data_in[22]) );
HS65_LL_IVX18 U3460 ( .A(n2821), .Z(Data_in[13]) );
HS65_LL_IVX18 U3461 ( .A(n2838), .Z(Data_in[19]) );
HS65_LL_CNBFX14 U3699 ( .A(n3014), .Z(Data_in[8]) );
HS65_LL_IVX18 U3439 ( .A(n2787), .Z(Address_toRAM[21]) );
HS65_LL_IVX18 U3440 ( .A(n2789), .Z(Address_toRAM[20]) );
HS65_LL_IVX18 U3441 ( .A(n2791), .Z(Address_toRAM[23]) );
HS65_LL_IVX18 U3442 ( .A(n2793), .Z(Address_toRAM[22]) );
HS65_LL_IVX18 U3443 ( .A(n2795), .Z(Address_toRAM[19]) );
HS65_LL_IVX18 U3444 ( .A(n2797), .Z(Address_toRAM[18]) );
HS65_LL_IVX18 U3445 ( .A(n2799), .Z(Address_toRAM[28]) );
HS65_LL_IVX18 U3450 ( .A(n2801), .Z(Address_toRAM[27]) );
HS65_LL_IVX18 U3456 ( .A(n2805), .Z(Address_toRAM[6]) );
HS65_LL_IVX18 U3458 ( .A(n2809), .Z(Address_toRAM[9]) );
HS65_LL_IVX18 U3451 ( .A(n2811), .Z(Data_in[27]) );
HS65_LL_IVX18 U3524 ( .A(n2815), .Z(Data_in[29]) );
HS65_LL_IVX18 U3525 ( .A(n2813), .Z(Data_in[28]) );
HS65_LL_IVX18 U3527 ( .A(n2817), .Z(Data_in[30]) );
HS65_LL_IVX18 U3455 ( .A(n2803), .Z(Address_toRAM[10]) );
HS65_LL_IVX18 U3457 ( .A(n2807), .Z(Address_toRAM[8]) );
HS65_LL_IVX18 U3449 ( .A(n2784), .Z(addr_to_iram[14]) );
HS65_LL_NAND2X7 U6252 ( .A(n3395), .B(n3394), .Z(n3396) );
HS65_LH_BFX35 U3435 ( .A(n2986), .Z(n3116) );
HS65_LL_IVX18 U3436 ( .A(n3120), .Z(addr_to_iram[23]) );
HS65_LL_IVX18 U3510 ( .A(n7785), .Z(addr_to_iram[28]) );
HS65_LL_IVX18 U3513 ( .A(n3121), .Z(addr_to_iram[22]) );
HS65_LH_BFX9 U3514 ( .A(n2994), .Z(n3115) );
HS65_LL_NAND2X14 U3515 ( .A(n3112), .B(n2979), .Z(n2994) );
HS65_LH_AND2ABX27 U3536 ( .A(n3114), .B(n8573), .Z(n2986) );
HS65_LL_AOI21X2 U3539 ( .A(n5643), .B(n3888), .C(n3887), .Z(n3889) );
HS65_LH_OAI21X3 U3544 ( .A(n5201), .B(n5135), .C(n4466), .Z(n4470) );
HS65_LL_CNBFX21 U3557 ( .A(n5610), .Z(n2859) );
HS65_LH_IVX9 U3588 ( .A(n9348), .Z(n9349) );
HS65_LL_NOR2AX3 U3647 ( .A(n3415), .B(n5089), .Z(n4516) );
HS65_LH_NOR2X6 U3654 ( .A(n2842), .B(n5376), .Z(n4049) );
HS65_LL_OAI211X8 U3662 ( .A(n7868), .B(n3398), .C(n3397), .D(n3396), .Z(
n3401) );
HS65_LH_IVX2 U3721 ( .A(n5127), .Z(n5133) );
HS65_LH_IVX2 U3736 ( .A(n5474), .Z(n5475) );
HS65_LH_IVX2 U3779 ( .A(n4050), .Z(n5084) );
HS65_LH_NAND2X2 U3828 ( .A(n3892), .B(n5295), .Z(n5302) );
HS65_LH_IVX2 U3877 ( .A(n3967), .Z(n3968) );
HS65_LH_IVX2 U3924 ( .A(n5299), .Z(n5468) );
HS65_LH_IVX2 U3958 ( .A(n5186), .Z(n3720) );
HS65_LH_NAND2X4 U3961 ( .A(n4147), .B(n2848), .Z(n5327) );
HS65_LH_NAND3X2 U3965 ( .A(n4749), .B(n4870), .C(n4748), .Z(n4760) );
HS65_LH_NAND3X2 U3966 ( .A(n5563), .B(n5502), .C(n5501), .Z(n5528) );
HS65_LH_OAI21X2 U4000 ( .A(n5350), .B(n5349), .C(n5348), .Z(n5351) );
HS65_LH_IVX2 U4042 ( .A(n3665), .Z(n3667) );
HS65_LH_IVX2 U4099 ( .A(n3836), .Z(n3783) );
HS65_LH_NAND2X2 U4111 ( .A(n4717), .B(n9342), .Z(n3183) );
HS65_LH_OR2X4 U4118 ( .A(n4700), .B(n4795), .Z(n3665) );
HS65_LH_NAND2X2 U4122 ( .A(n5618), .B(n5617), .Z(n5619) );
HS65_LH_IVX2 U4151 ( .A(n4917), .Z(n3895) );
HS65_LH_NAND2X2 U4167 ( .A(\sub_x_53/A[23] ), .B(n4351), .Z(n3603) );
HS65_LH_NAND2X2 U4197 ( .A(n3721), .B(n3720), .Z(n3722) );
HS65_LH_IVX2 U4203 ( .A(n5346), .Z(n4709) );
HS65_LH_NOR3X1 U4213 ( .A(n5543), .B(n5542), .C(n5541), .Z(n5561) );
HS65_LH_CBI4I1X3 U4217 ( .A(n5316), .B(n5315), .C(n5325), .D(n5314), .Z(
n5485) );
HS65_LH_IVX2 U4218 ( .A(n4528), .Z(n4196) );
HS65_LH_NAND2X2 U4221 ( .A(n3494), .B(n3493), .Z(n3495) );
HS65_LH_NOR2AX3 U4225 ( .A(n3526), .B(n3525), .Z(n3527) );
HS65_LH_AOI21X2 U4232 ( .A(n5207), .B(n5139), .C(n4853), .Z(n4854) );
HS65_LH_NAND2X2 U4233 ( .A(n3665), .B(n3594), .Z(n3553) );
HS65_LH_NAND2X2 U4236 ( .A(n3327), .B(n9177), .Z(n3222) );
HS65_LH_NAND2X2 U4243 ( .A(n3482), .B(n3939), .Z(n3941) );
HS65_LHS_XNOR2X3 U4248 ( .A(n8942), .B(\u_DataPath/jaddr_i [21]), .Z(n7108)
);
HS65_LH_NOR2X2 U4250 ( .A(n5652), .B(n4582), .Z(n3903) );
HS65_LH_NOR2X2 U4252 ( .A(n4711), .B(n4582), .Z(n4524) );
HS65_LH_NOR2X2 U4256 ( .A(n5241), .B(n4185), .Z(n4186) );
HS65_LH_NAND2X2 U4259 ( .A(\sub_x_53/A[27] ), .B(n4976), .Z(n3684) );
HS65_LH_AOI21X2 U4264 ( .A(n3368), .B(n4917), .C(n3367), .Z(n3369) );
HS65_LH_NAND2X2 U4269 ( .A(n4516), .B(n4943), .Z(n4149) );
HS65_LH_NAND2X2 U4270 ( .A(n9221), .B(n9222), .Z(n4283) );
HS65_LH_OAI21X2 U4288 ( .A(n4320), .B(n4319), .C(n4318), .Z(n4321) );
HS65_LH_OAI21X2 U4304 ( .A(n4066), .B(n4490), .C(n6123), .Z(n4072) );
HS65_LH_AOI21X2 U4311 ( .A(n6123), .B(n4806), .C(n4460), .Z(n4461) );
HS65_LH_IVX2 U4345 ( .A(n4381), .Z(n4383) );
HS65_LH_IVX2 U4348 ( .A(n5260), .Z(n4251) );
HS65_LL_NAND3X2 U4354 ( .A(n5246), .B(n5245), .C(n5244), .Z(n5247) );
HS65_LH_NAND2AX4 U4366 ( .A(n3456), .B(n3455), .Z(n3458) );
HS65_LH_IVX2 U4392 ( .A(n5603), .Z(n5604) );
HS65_LH_OAI21X2 U4434 ( .A(n5789), .B(n5786), .C(n5788), .Z(n5761) );
HS65_LH_NAND2X2 U4454 ( .A(n3474), .B(n4588), .Z(n3959) );
HS65_LH_NAND3X2 U4492 ( .A(n7108), .B(n7107), .C(n7106), .Z(n7109) );
HS65_LH_NOR2X2 U4500 ( .A(n5179), .B(n3294), .Z(n4801) );
HS65_LH_IVX2 U4504 ( .A(n4622), .Z(n4623) );
HS65_LH_NAND2X2 U4517 ( .A(\lte_x_59/B[15] ), .B(n2864), .Z(n3833) );
HS65_LH_NAND2X2 U4542 ( .A(n3426), .B(n4491), .Z(n3979) );
HS65_LH_IVX2 U4545 ( .A(n4742), .Z(n3534) );
HS65_LH_IVX2 U4559 ( .A(n3979), .Z(n3757) );
HS65_LL_AOI12X2 U4573 ( .A(n4708), .B(n4707), .C(n4706), .Z(n4736) );
HS65_LH_NOR2X2 U4576 ( .A(n3788), .B(n4895), .Z(n3590) );
HS65_LH_OAI21X2 U4578 ( .A(n6070), .B(n5976), .C(n5978), .Z(n5927) );
HS65_LH_OAI21X2 U4602 ( .A(n2873), .B(n9346), .C(n4489), .Z(n4493) );
HS65_LH_IVX2 U4606 ( .A(n4328), .Z(n4329) );
HS65_LH_NAND2X2 U4607 ( .A(n4873), .B(n4951), .Z(n4065) );
HS65_LH_NAND2X2 U4611 ( .A(n4383), .B(n4382), .Z(n4387) );
HS65_LH_NAND2X2 U4625 ( .A(n5272), .B(n5275), .Z(n4248) );
HS65_LH_NAND2X2 U4633 ( .A(n9285), .B(n8399), .Z(n8291) );
HS65_LH_NAND2X2 U4638 ( .A(n9175), .B(n9227), .Z(n5884) );
HS65_LH_AO22X4 U4653 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][0] ), .B(n7522),
.C(n7439), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][0] ), .Z(n7443)
);
HS65_LH_AO22X4 U4701 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][28] ), .B(n7522),
.C(n6752), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][28] ), .Z(n7503)
);
HS65_LH_AOI22X1 U4705 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][5] ), .B(n7286),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[21][5] ), .D(
n7285), .Z(n6938) );
HS65_LH_AO22X4 U4768 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][24] ), .B(n7587),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[12][24] ), .D(
n7586), .Z(n7562) );
HS65_LH_AO22X4 U4820 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][26] ), .B(n7522),
.C(n6752), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][26] ), .Z(n7328)
);
HS65_LH_AO22X4 U4832 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][3] ), .B(n7602),
.C(n7601), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][3] ), .Z(n7401)
);
HS65_LH_NOR2X2 U4842 ( .A(n7658), .B(n7657), .Z(n7684) );
HS65_LH_AOI22X1 U4846 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][30] ), .B(n7265),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[11][30] ), .D(
n2888), .Z(n6129) );
HS65_LH_IVX2 U4848 ( .A(n5824), .Z(n5825) );
HS65_LH_OAI22X1 U4855 ( .A(n7112), .B(n7111), .C(n7110), .D(n7109), .Z(n7113) );
HS65_LH_AOI22X1 U4864 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][2] ), .B(n7585),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[1][2] ), .D(n2889), .Z(n6960) );
HS65_LH_AOI22X1 U4868 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][21] ), .B(n7585),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[1][21] ), .D(
n2889), .Z(n7590) );
HS65_LH_AO22X4 U4870 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[7][16] ), .B(n7587),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[12][16] ), .D(
n7586), .Z(n7542) );
HS65_LH_AO22X4 U4877 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][29] ), .B(n7522),
.C(n6752), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][29] ), .Z(n7529)
);
HS65_LH_AO22X4 U4880 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][20] ), .B(n7522),
.C(n7439), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][20] ), .Z(n7483)
);
HS65_LH_AOI22X1 U4889 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][30] ), .B(n7580),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][30] ), .D(
n7579), .Z(n7417) );
HS65_LH_AO22X4 U4894 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[31][14] ), .B(n7602),
.C(n7601), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][14] ), .Z(n7381)
);
HS65_LH_AOI22X1 U4895 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][14] ), .B(n7415),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[10][14] ), .D(
n2891), .Z(n7370) );
HS65_LH_AOI22X1 U4896 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[14][4] ), .B(n7415),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[10][4] ), .D(
n2891), .Z(n7350) );
HS65_LH_NOR2X6 U4897 ( .A(n6350), .B(n6352), .Z(n6966) );
HS65_LH_NOR2X9 U4898 ( .A(n6148), .B(n6152), .Z(n6426) );
HS65_LH_BFX4 U4902 ( .A(n6637), .Z(n7284) );
HS65_LH_AO22X4 U4905 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][2] ), .B(n9375),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[6][2] ), .D(n6619), .Z(n6555) );
HS65_LH_AOI22X1 U4915 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][25] ), .B(n7273),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[29][25] ), .D(
n6625), .Z(n7149) );
HS65_LH_AO22X4 U4921 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[27][9] ), .B(n7277),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[25][9] ), .D(
n6629), .Z(n7127) );
HS65_LH_AO22X4 U4923 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[4][28] ), .B(n7293),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[13][28] ), .D(
n7292), .Z(n6921) );
HS65_LH_AOI22X1 U4933 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][17] ), .B(n6941),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[7][17] ), .D(
n7294), .Z(n6900) );
HS65_LH_AOI22X1 U4934 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][31] ), .B(n6941),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[7][31] ), .D(
n6384), .Z(n6880) );
HS65_LH_AOI22X1 U4944 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][31] ), .B(n6595),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[14][31] ), .D(
n7264), .Z(n6870) );
HS65_LH_AOI22X1 U4945 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[15][18] ), .B(n7265),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[11][18] ), .D(
n2888), .Z(n6652) );
HS65_LH_AO22X4 U4949 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[10][20] ), .B(n6927),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[5][20] ), .D(
n7266), .Z(n6848) );
HS65_LH_AO22X4 U4951 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][29] ), .B(n9375),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[6][29] ), .D(
n7267), .Z(n7268) );
HS65_LH_AOI22X1 U4957 ( .A(n3426), .B(n4886), .C(n4836), .D(n4873), .Z(n3556) );
HS65_LH_AOI22X1 U4969 ( .A(n7434), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][8] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][8] ), .D(n7516),
.Z(n6774) );
HS65_LH_AOI22X1 U5038 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][11] ), .B(n7273),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[29][11] ), .D(
n6625), .Z(n6251) );
HS65_LH_AO22X4 U5042 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][31] ), .B(n7517),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[4][31] ), .D(
n7318), .Z(n6677) );
HS65_LH_AO22X4 U5108 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][6] ), .B(n7522),
.C(n7439), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][6] ), .Z(n7255)
);
HS65_LH_AO22X4 U5120 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][21] ), .B(n7170),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[23][21] ), .D(
n6637), .Z(n6195) );
HS65_LH_AO22X4 U5137 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][17] ), .B(n7522),
.C(n7439), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][17] ), .Z(n6818)
);
HS65_LH_AO22X4 U5149 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][16] ), .B(n7170),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[23][16] ), .D(
n6637), .Z(n6175) );
HS65_LH_AOI22X1 U5207 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[21][23] ), .B(n7524),
.C(n7593), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[20][23] ), .Z(n7233)
);
HS65_LH_AOI22X1 U5208 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][1] ), .B(n7585),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[1][1] ), .D(n2889), .Z(n6833) );
HS65_LH_AOI22X1 U5237 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][27] ), .B(n7273),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[29][27] ), .D(
n6625), .Z(n6211) );
HS65_LH_AO22X4 U5270 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[11][19] ), .B(n7578),
.C(n7310), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[5][19] ), .Z(n6742)
);
HS65_LH_AO22X4 U5293 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][18] ), .B(n7580),
.C(n7579), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[2][18] ), .Z(n6327)
);
HS65_LH_AOI22X1 U5344 ( .A(n7434), .B(
\u_DataPath/u_decode_unit/reg_file0/bank_register[13][7] ), .C(
\u_DataPath/u_decode_unit/reg_file0/bank_register[6][7] ), .D(n7516),
.Z(n6726) );
HS65_LH_AOI22X1 U5355 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][22] ), .B(n7273),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[29][22] ), .D(
n6625), .Z(n6271) );
HS65_LH_AOI22X1 U5395 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[26][24] ), .B(n7273),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[29][24] ), .D(
n6625), .Z(n6291) );
HS65_LH_AO22X4 U5453 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][5] ), .B(n7517),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[4][5] ), .D(n7318), .Z(n6704) );
HS65_LH_AO22X4 U5473 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][12] ), .B(n7522),
.C(n7439), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][12] ), .Z(n6798)
);
HS65_LH_AO22X4 U5496 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][13] ), .B(n7170),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[23][13] ), .D(
n6637), .Z(n7174) );
HS65_LH_AOI22X1 U5531 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][14] ), .B(n6376),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[21][14] ), .D(
n7285), .Z(n6314) );
HS65_LH_AOI22X1 U5578 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][19] ), .B(n2887),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[22][19] ), .D(
n7171), .Z(n6523) );
HS65_LH_AO22X4 U5632 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][7] ), .B(n6426),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][7] ), .D(n7291), .Z(n6450) );
HS65_LH_AO22X4 U5638 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][12] ), .B(n6426),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][12] ), .D(
n7291), .Z(n6550) );
HS65_LH_AOI22X1 U5639 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][6] ), .B(n6941),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[7][6] ), .D(n7294), .Z(n6488) );
HS65_LH_AOI22X1 U5650 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[8][3] ), .B(n7297),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[0][3] ), .D(n6942), .Z(n6587) );
HS65_LH_AOI22X1 U5651 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][3] ), .B(n6595),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[14][3] ), .D(
n7264), .Z(n6578) );
HS65_LH_AOI22X1 U5652 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[12][26] ), .B(n6595),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[14][26] ), .D(
n7264), .Z(n6498) );
HS65_LH_AO22X4 U5657 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][8] ), .B(n9374),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[6][8] ), .D(n7267), .Z(n6455) );
HS65_LH_AOI22X1 U5672 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[24][1] ), .B(n6370),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[28][1] ), .D(
n6600), .Z(n6604) );
HS65_LH_AO22X4 U5684 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[9][9] ), .B(n7580),
.C(n7579), .D(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][9] ), .Z(n7016) );
HS65_LH_AOI22X1 U5708 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[16][22] ), .B(n6754),
.C(n7594), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[22][22] ), .Z(n7004)
);
HS65_LH_AO22X4 U5709 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][4] ), .B(n6426),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][4] ), .D(n7291), .Z(n6645) );
HS65_LH_IVX2 U5710 ( .A(n3747), .Z(n3748) );
HS65_LH_NAND2X2 U5711 ( .A(n5131), .B(n4937), .Z(n4959) );
HS65_LH_NAND2X2 U5723 ( .A(n9183), .B(n9232), .Z(n5777) );
HS65_LH_NAND2X2 U5725 ( .A(n9342), .B(n9218), .Z(n5797) );
HS65_LH_OR2X4 U5744 ( .A(n9342), .B(n9210), .Z(n5910) );
HS65_LH_NAND2X2 U5746 ( .A(n9224), .B(n9226), .Z(n5687) );
HS65_LH_NOR2X2 U5751 ( .A(n9030), .B(n9223), .Z(n5836) );
HS65_LH_NOR2AX3 U5755 ( .A(n4299), .B(n4298), .Z(n4300) );
HS65_LH_OA112X4 U5764 ( .A(n9248), .B(n8880), .C(n8400), .D(n9086), .Z(n9382) );
HS65_LH_IVX2 U5786 ( .A(n4073), .Z(n4074) );
HS65_LH_NAND2X2 U5796 ( .A(n5131), .B(n4868), .Z(n4869) );
HS65_LH_OA12X4 U5801 ( .A(n9122), .B(n8453), .C(n7913), .Z(n9390) );
HS65_LH_IVX2 U5803 ( .A(n5832), .Z(n5892) );
HS65_LH_NAND2X2 U5807 ( .A(n5884), .B(n5883), .Z(n5889) );
HS65_LH_NAND2X2 U5821 ( .A(n4187), .B(n3407), .Z(n3408) );
HS65_LH_NAND2X2 U5842 ( .A(n4573), .B(n4539), .Z(n4540) );
HS65_LH_NAND3X2 U5849 ( .A(n2977), .B(n2978), .C(n2976), .Z(n2985) );
HS65_LH_NAND2X2 U5918 ( .A(n2896), .B(n3226), .Z(n6124) );
HS65_LH_IVX2 U5926 ( .A(\u_DataPath/dataOut_exe_i [12]), .Z(n3256) );
HS65_LH_AO22X4 U5945 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][15] ), .B(n7522),
.C(n7439), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][15] ), .Z(n7195)
);
HS65_LH_AO22X4 U5962 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[19][10] ), .B(n7522),
.C(n7439), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[23][10] ), .Z(n7215)
);
HS65_LH_AOI22X1 U5977 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][0] ), .B(n2887),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[22][0] ), .D(
n7171), .Z(n6422) );
HS65_LH_AO22X4 U5999 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[1][10] ), .B(n2884),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[2][10] ), .D(
n7291), .Z(n6409) );
HS65_LH_AOI22X1 U6004 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[3][15] ), .B(n6941),
.C(\u_DataPath/u_decode_unit/reg_file0/bank_register[7][15] ), .D(
n7294), .Z(n6387) );
HS65_LH_OR4X4 U6007 ( .A(n7152), .B(n7151), .C(n2882), .D(n2883), .Z(n7158)
);
HS65_LH_NAND2X2 U6023 ( .A(n5643), .B(n4826), .Z(n4827) );
HS65_LH_OAI21X2 U6028 ( .A(n4803), .B(n4954), .C(n4802), .Z(n4814) );
HS65_LH_AOI22X1 U6038 ( .A(n5131), .B(n4617), .C(n4887), .D(n4616), .Z(n4618) );
HS65_LH_IVX2 U6057 ( .A(n7693), .Z(n7738) );
HS65_LH_IVX2 U6130 ( .A(n8122), .Z(n7761) );
HS65_LH_NAND2X2 U6133 ( .A(n5624), .B(n4816), .Z(n3568) );
HS65_LH_IVX2 U6148 ( .A(n7688), .Z(n7771) );
HS65_LL_OAI112X3 U6151 ( .A(n2920), .B(n5596), .C(n5595), .D(n5594), .Z(
n5712) );
HS65_LH_NAND2X2 U6173 ( .A(n4331), .B(n3130), .Z(n3393) );
HS65_LH_IVX2 U6222 ( .A(\u_DataPath/dataOut_exe_i [28]), .Z(n3127) );
HS65_LH_NAND2X2 U6228 ( .A(n5877), .B(n6031), .Z(n5830) );
HS65_LH_AOI21X2 U6239 ( .A(n5866), .B(n5868), .C(n5821), .Z(n5822) );
HS65_LH_NAND2X2 U6256 ( .A(n8911), .B(n9202), .Z(n5920) );
HS65_LH_NAND2X2 U6273 ( .A(n9145), .B(n9224), .Z(n5959) );
HS65_LH_OAI21X2 U6295 ( .A(n5995), .B(n6000), .C(n5997), .Z(n6015) );
HS65_LH_IVX2 U6318 ( .A(n6019), .Z(n6020) );
HS65_LH_NAND2X2 U6319 ( .A(n8967), .B(n9220), .Z(n6064) );
HS65_LH_NOR2X2 U6327 ( .A(n9177), .B(n9229), .Z(n6078) );
HS65_LH_OR2X4 U6351 ( .A(n8911), .B(n9205), .Z(n6117) );
HS65_LH_IVX2 U6354 ( .A(n7728), .Z(n7730) );
HS65_LH_NAND2X2 U6368 ( .A(n7631), .B(n4249), .Z(n4282) );
HS65_LH_OAI21X2 U6385 ( .A(n5173), .B(n5172), .C(n5171), .Z(n5191) );
HS65_LH_NAND2X2 U6415 ( .A(n5688), .B(n7729), .Z(n7720) );
HS65_LH_NAND3X2 U6419 ( .A(Data_out_fromRAM[31]), .B(n8270), .C(n8576), .Z(
n7346) );
HS65_LH_OR2X4 U6445 ( .A(n8332), .B(n3340), .Z(n3081) );
HS65_LH_NOR2X2 U6446 ( .A(n8799), .B(n3403), .Z(n3100) );
HS65_LH_NAND2X2 U6458 ( .A(n9365), .B(n9040), .Z(n8413) );
HS65_LH_AOI22X1 U6506 ( .A(n8868), .B(n9144), .C(n9368), .D(n9000), .Z(n8419) );
HS65_LH_IVX2 U6541 ( .A(n2985), .Z(n2979) );
HS65_LH_NAND2X2 U6543 ( .A(n7654), .B(n7749), .Z(n7752) );
HS65_LH_AO22X4 U6584 ( .A(n9256), .B(n9188), .C(n9133), .D(n8933), .Z(
\u_DataPath/jump_address_i [22]) );
HS65_LH_AO22X4 U6607 ( .A(n9053), .B(n9188), .C(n9133), .D(n9080), .Z(
\u_DataPath/jump_address_i [3]) );
HS65_LH_AO22X4 U6686 ( .A(n8937), .B(n9109), .C(n9188), .D(n9092), .Z(
\u_DataPath/jump_address_i [0]) );
HS65_LH_IVX2 U6725 ( .A(n7734), .Z(n7778) );
HS65_LH_IVX2 U6727 ( .A(n6124), .Z(n8504) );
HS65_LH_NAND2AX4 U6729 ( .A(n8864), .B(n3291), .Z(n8511) );
HS65_LH_IVX2 U6732 ( .A(n7775), .Z(n8116) );
HS65_LL_NAND3X2 U6735 ( .A(n4505), .B(n4511), .C(n4510), .Z(n5250) );
HS65_LH_NOR4ABX2 U6744 ( .A(n6698), .B(n6697), .C(n6696), .D(n6695), .Z(
n8158) );
HS65_LH_NOR4ABX2 U6746 ( .A(n6738), .B(n6737), .C(n6736), .D(n6735), .Z(
n8180) );
HS65_LH_NAND2X2 U6749 ( .A(n7631), .B(n4649), .Z(n4650) );
HS65_LHS_XNOR2X3 U6757 ( .A(n3952), .B(n3951), .Z(n4000) );
HS65_LH_NAND2X4 U6763 ( .A(n5712), .B(n5711), .Z(n5715) );
HS65_LH_NAND2X2 U6793 ( .A(n6047), .B(n6046), .Z(n6048) );
HS65_LH_IVX2 U6831 ( .A(n6051), .Z(n6101) );
HS65_LH_NAND2X2 U6837 ( .A(n5989), .B(n5787), .Z(n5994) );
HS65_LH_NOR2X2 U6866 ( .A(n7753), .B(n7752), .Z(n7655) );
HS65_LH_NOR2X2 U6869 ( .A(n7686), .B(n7755), .Z(n7687) );
HS65_LH_OAI21X2 U6886 ( .A(n6090), .B(n6089), .C(n6088), .Z(n6091) );
HS65_LH_IVX2 U6892 ( .A(n9223), .Z(n7791) );
HS65_LH_NAND3X2 U6907 ( .A(opcode_i[1]), .B(n7643), .C(n7642), .Z(n8047) );
HS65_LH_NAND2X2 U6908 ( .A(n4485), .B(n4484), .Z(n4486) );
HS65_LH_NOR3X1 U6956 ( .A(n5191), .B(n5190), .C(n5189), .Z(n5225) );
HS65_LH_NOR2X2 U6958 ( .A(n8850), .B(n3403), .Z(n3250) );
HS65_LH_OAI21X2 U6967 ( .A(n7775), .B(n7683), .C(n7682), .Z(n7740) );
HS65_LH_IVX2 U7003 ( .A(n8236), .Z(n7117) );
HS65_LHS_XOR2X3 U7022 ( .A(n7785), .B(n7784), .Z(\u_DataPath/pc_4_i [30]) );
HS65_LH_AO22X4 U7028 ( .A(n9192), .B(n8862), .C(n8690), .D(n9240), .Z(
\u_DataPath/pc4_to_idexreg_i [0]) );
HS65_LHS_XOR2X3 U7038 ( .A(n2829), .B(n7747), .Z(\u_DataPath/pc_4_i [9]) );
HS65_LH_IVX2 U7050 ( .A(Data_out_fromRAM[28]), .Z(n8417) );
HS65_LH_AO22X4 U7052 ( .A(n9254), .B(n8807), .C(n9240), .D(n8963), .Z(
\u_DataPath/pc4_to_idexreg_i [6]) );
HS65_LH_AO22X4 U7090 ( .A(n8782), .B(n9253), .C(n9312), .D(n9142), .Z(
\u_DataPath/immediate_ext_dec_i [9]) );
HS65_LH_NOR4ABX2 U7112 ( .A(n7223), .B(n7222), .C(n7221), .D(n7220), .Z(
n8181) );
HS65_LH_AO22X4 U7141 ( .A(n8770), .B(n9252), .C(n9305), .D(n9069), .Z(
\u_DataPath/immediate_ext_dec_i [2]) );
HS65_LH_AO22X4 U7150 ( .A(n8774), .B(n9252), .C(n9304), .D(n9069), .Z(
\u_DataPath/immediate_ext_dec_i [1]) );
HS65_LHS_XNOR2X3 U7157 ( .A(n2833), .B(n7749), .Z(\u_DataPath/pc_4_i [10])
);
HS65_LHS_XOR2X3 U7202 ( .A(n2823), .B(n7750), .Z(\u_DataPath/pc_4_i [11]) );
HS65_LHS_XNOR2X3 U7243 ( .A(n6120), .B(n6119), .Z(
\u_DataPath/u_execute/resAdd1_i [28]) );
HS65_LHS_XNOR2X3 U7244 ( .A(n7717), .B(n7716), .Z(
\u_DataPath/u_execute/link_value_i [17]) );
HS65_LHS_XOR2X3 U7291 ( .A(n7791), .B(n7790), .Z(
\u_DataPath/u_execute/link_value_i [5]) );
HS65_LH_IVX2 U7296 ( .A(n8298), .Z(n8299) );
HS65_LH_IVX2 U7322 ( .A(n8576), .Z(n8271) );
HS65_LH_IVX2 U7332 ( .A(n3109), .Z(n8578) );
HS65_LH_IVX2 U7342 ( .A(Data_out_fromRAM[23]), .Z(n8360) );
HS65_LH_IVX18 U7385 ( .A(n2842), .Z(n4675) );
HS65_LH_NAND2X7 U7398 ( .A(n5626), .B(n5625), .Z(n5640) );
HS65_LL_NAND3X6 U7412 ( .A(n8476), .B(n8477), .C(n2918), .Z(n5163) );
HS65_LH_NAND2AX4 U7429 ( .A(n3282), .B(n3368), .Z(n3370) );
HS65_LL_AND2X4 U7445 ( .A(n8473), .B(n8472), .Z(n2918) );
HS65_LL_NOR2AX6 U7464 ( .A(n3948), .B(n3947), .Z(n8473) );
HS65_LL_NAND2AX7 U7476 ( .A(n2921), .B(n3235), .Z(n4683) );
HS65_LL_OAI21X2 U7478 ( .A(n4427), .B(n2859), .C(n4426), .Z(n4428) );
HS65_LL_CNBFX17 U7534 ( .A(\u_DataPath/cw_towb_i [0]), .Z(n3404) );
HS65_LH_IVX9 U7558 ( .A(n9431), .Z(n3285) );
HS65_LL_NAND2X7 U7568 ( .A(n7874), .B(n5683), .Z(n5684) );
HS65_LL_NOR2X9 U7580 ( .A(n5678), .B(n5677), .Z(n7853) );
HS65_LL_NOR2X6 U7601 ( .A(n4793), .B(n4792), .Z(n4832) );
HS65_LHS_XOR2X3 U7616 ( .A(n4562), .B(n2897), .Z(n4563) );
HS65_LL_NAND2X4 U7623 ( .A(n5597), .B(n5712), .Z(n5600) );
HS65_LL_NAND3X6 U7644 ( .A(n8461), .B(n8459), .C(n5283), .Z(n5601) );
HS65_LL_BFX9 U7675 ( .A(n9066), .Z(n9347) );
HS65_LL_NAND2AX21 U7712 ( .A(n5163), .B(n5162), .Z(n5683) );
HS65_LHS_XOR2X3 U7717 ( .A(n3101), .B(n4997), .Z(n4774) );
HS65_LL_AOI21X6 U7756 ( .A(n5285), .B(n3697), .C(n3696), .Z(n8461) );
HS65_LH_AO22X4 U7760 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][15] ), .B(n7523),
.C(n7592), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][15] ), .Z(n7194)
);
HS65_LH_AO22X4 U7784 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][8] ), .B(n7523),
.C(n6682), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][8] ), .Z(n6777)
);
HS65_LH_AO22X4 U7814 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][23] ), .B(n7523),
.C(n6682), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][23] ), .Z(n7234)
);
HS65_LH_AO22X4 U7816 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][6] ), .B(n7523),
.C(n7592), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][6] ), .Z(n7254)
);
HS65_LH_AO22X4 U7819 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][31] ), .B(n7523),
.C(n7592), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][31] ), .Z(n6687)
);
HS65_LH_AO22X4 U7830 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][7] ), .B(n7523),
.C(n7592), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][7] ), .Z(n6729)
);
HS65_LH_AO22X4 U7846 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][30] ), .B(n6681),
.C(n7592), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][30] ), .Z(n7422)
);
HS65_LH_AO22X4 U7868 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][20] ), .B(n7523),
.C(n6682), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][20] ), .Z(n7482)
);
HS65_LH_AO22X4 U7871 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][3] ), .B(n7523),
.C(n6682), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][3] ), .Z(n7397)
);
HS65_LH_AO22X4 U7881 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][28] ), .B(n7523),
.C(n6682), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][28] ), .Z(n7502)
);
HS65_LH_AO22X4 U7900 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][14] ), .B(n7523),
.C(n6682), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][14] ), .Z(n7377)
);
HS65_LH_AO22X4 U7901 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][29] ), .B(n7523),
.C(n6682), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][29] ), .Z(n7528)
);
HS65_LH_AO22X4 U7902 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][0] ), .B(n7523),
.C(n6682), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][0] ), .Z(n7442)
);
HS65_LH_AO22X4 U7903 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][13] ), .B(n6681),
.C(n7592), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][13] ), .Z(n6986)
);
HS65_LH_AO22X4 U7904 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][22] ), .B(n6681),
.C(n7592), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][22] ), .Z(n7006)
);
HS65_LH_AO22X4 U8092 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][9] ), .B(n6681),
.C(n7592), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][9] ), .Z(n7026)
);
HS65_LH_AO22X4 U8133 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][11] ), .B(n6681),
.C(n7592), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][11] ), .Z(n7066)
);
HS65_LH_AO22X4 U8136 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][25] ), .B(n6681),
.C(n7592), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][25] ), .Z(n7046)
);
HS65_LH_AO22X4 U8152 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][19] ), .B(n6681),
.C(n7592), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][19] ), .Z(n6757)
);
HS65_LH_AO22X4 U8162 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][18] ), .B(n7523),
.C(n6682), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][18] ), .Z(n6345)
);
HS65_LH_AO22X4 U8169 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][12] ), .B(n7523),
.C(n6682), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][12] ), .Z(n6797)
);
HS65_LH_AO22X4 U8175 ( .A(
\u_DataPath/u_decode_unit/reg_file0/bank_register[17][1] ), .B(n7523),
.C(n6682), .D(
\u_DataPath/u_decode_unit/reg_file0/bank_register[18][1] ), .Z(n6837)
);
HS65_LHS_XNOR2X3 U8179 ( .A(n4598), .B(n4597), .Z(n4599) );
HS65_LL_AND2X9 U8184 ( .A(n3397), .B(n3293), .Z(n4805) );
HS65_LL_NOR2X5 U8198 ( .A(n5161), .B(n5710), .Z(n5162) );
HS65_LL_NAND3AX6 U8203 ( .A(n5686), .B(n8474), .C(n8475), .Z(n5161) );
HS65_LL_NOR3X4 U8219 ( .A(n7867), .B(n4302), .C(n5708), .Z(n4456) );
HS65_LH_NAND2X7 U8277 ( .A(\lte_x_59/B[8] ), .B(n4551), .Z(n3867) );
HS65_LH_AOI12X2 U8297 ( .A(n3688), .B(n5211), .C(n3687), .Z(n3689) );
HS65_LL_CNIVX7 U8319 ( .A(n4427), .Z(n2867) );
HS65_LH_IVX4 U8332 ( .A(n9348), .Z(n9352) );
HS65_LH_IVX7 U8339 ( .A(n9376), .Z(n4717) );
HS65_LH_CNIVX3 U8349 ( .A(\u_DataPath/jaddr_i [20]), .Z(n2881) );
HS65_LH_NOR2X5 U8351 ( .A(n5054), .B(n5053), .Z(n5299) );
HS65_LL_NAND3X2 U8361 ( .A(n3871), .B(n3870), .C(n3869), .Z(n5143) );
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_crc.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// - Novan Hartadi ([email protected]) ////
//// - Mahmud Galela ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.3 2001/06/19 18:16:40 mohor
// TxClk changed to MTxClk (as discribed in the documentation).
// Crc changed so only one file can be used instead of two.
//
// Revision 1.2 2001/06/19 10:38:07 mohor
// Minor changes in header.
//
// Revision 1.1 2001/06/19 10:27:57 mohor
// TxEthMAC initial release.
//
//
//
`include "timescale.v"
module eth_crc (Clk, Reset, Data, Enable, Initialize, Crc, CrcError);
parameter Tp = 1;
input Clk;
input Reset;
input [3:0] Data;
input Enable;
input Initialize;
output [31:0] Crc;
output CrcError;
reg [31:0] Crc;
wire [31:0] CrcNext;
assign CrcNext[0] = Enable & (Data[0] ^ Crc[28]);
assign CrcNext[1] = Enable & (Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29]);
assign CrcNext[2] = Enable & (Data[2] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[30]);
assign CrcNext[3] = Enable & (Data[3] ^ Data[2] ^ Data[1] ^ Crc[29] ^ Crc[30] ^ Crc[31]);
assign CrcNext[4] = (Enable & (Data[3] ^ Data[2] ^ Data[0] ^ Crc[28] ^ Crc[30] ^ Crc[31])) ^ Crc[0];
assign CrcNext[5] = (Enable & (Data[3] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[31])) ^ Crc[1];
assign CrcNext[6] = (Enable & (Data[2] ^ Data[1] ^ Crc[29] ^ Crc[30])) ^ Crc[ 2];
assign CrcNext[7] = (Enable & (Data[3] ^ Data[2] ^ Data[0] ^ Crc[28] ^ Crc[30] ^ Crc[31])) ^ Crc[3];
assign CrcNext[8] = (Enable & (Data[3] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[31])) ^ Crc[4];
assign CrcNext[9] = (Enable & (Data[2] ^ Data[1] ^ Crc[29] ^ Crc[30])) ^ Crc[5];
assign CrcNext[10] = (Enable & (Data[3] ^ Data[2] ^ Data[0] ^ Crc[28] ^ Crc[30] ^ Crc[31])) ^ Crc[6];
assign CrcNext[11] = (Enable & (Data[3] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[31])) ^ Crc[7];
assign CrcNext[12] = (Enable & (Data[2] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[30])) ^ Crc[8];
assign CrcNext[13] = (Enable & (Data[3] ^ Data[2] ^ Data[1] ^ Crc[29] ^ Crc[30] ^ Crc[31])) ^ Crc[9];
assign CrcNext[14] = (Enable & (Data[3] ^ Data[2] ^ Crc[30] ^ Crc[31])) ^ Crc[10];
assign CrcNext[15] = (Enable & (Data[3] ^ Crc[31])) ^ Crc[11];
assign CrcNext[16] = (Enable & (Data[0] ^ Crc[28])) ^ Crc[12];
assign CrcNext[17] = (Enable & (Data[1] ^ Crc[29])) ^ Crc[13];
assign CrcNext[18] = (Enable & (Data[2] ^ Crc[30])) ^ Crc[14];
assign CrcNext[19] = (Enable & (Data[3] ^ Crc[31])) ^ Crc[15];
assign CrcNext[20] = Crc[16];
assign CrcNext[21] = Crc[17];
assign CrcNext[22] = (Enable & (Data[0] ^ Crc[28])) ^ Crc[18];
assign CrcNext[23] = (Enable & (Data[1] ^ Data[0] ^ Crc[29] ^ Crc[28])) ^ Crc[19];
assign CrcNext[24] = (Enable & (Data[2] ^ Data[1] ^ Crc[30] ^ Crc[29])) ^ Crc[20];
assign CrcNext[25] = (Enable & (Data[3] ^ Data[2] ^ Crc[31] ^ Crc[30])) ^ Crc[21];
assign CrcNext[26] = (Enable & (Data[3] ^ Data[0] ^ Crc[31] ^ Crc[28])) ^ Crc[22];
assign CrcNext[27] = (Enable & (Data[1] ^ Crc[29])) ^ Crc[23];
assign CrcNext[28] = (Enable & (Data[2] ^ Crc[30])) ^ Crc[24];
assign CrcNext[29] = (Enable & (Data[3] ^ Crc[31])) ^ Crc[25];
assign CrcNext[30] = Crc[26];
assign CrcNext[31] = Crc[27];
always @ (posedge Clk or posedge Reset)
begin
if (Reset)
Crc <= #1 32'hffffffff;
else
if(Initialize)
Crc <= #Tp 32'hffffffff;
else
Crc <= #Tp CrcNext;
end
assign CrcError = Crc[31:0] != 32'hc704dd7b; // CRC not equal to magic number
endmodule
|
module \$__NX_PDP16K (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
parameter CFG_ABITS = 9;
parameter CFG_DBITS = 36;
parameter CFG_ENABLE_A = 4;
parameter CLKPOL2 = 1;
parameter CLKPOL3 = 1;
parameter [18431:0] INIT = 18432'b0;
parameter _TECHMAP_BITS_CONNMAP_ = 8;
parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_CLK2_ = 0;
parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_CLK3_ = 0;
input CLK2;
input CLK3;
input [CFG_ABITS-1:0] A1ADDR;
input [CFG_DBITS-1:0] A1DATA;
input [CFG_ENABLE_A-1:0] A1EN;
input [CFG_ABITS-1:0] B1ADDR;
output [CFG_DBITS-1:0] B1DATA;
input B1EN;
// Address is left justified, in x18 and above lower bits are byte enables
localparam A_SHIFT =
(CFG_DBITS == 36) ? 5 :
(CFG_DBITS == 18) ? 4 :
(CFG_DBITS == 9) ? 3 :
(CFG_DBITS == 4) ? 2 :
(CFG_DBITS == 2) ? 1 :
0;
// Different primitives needed for single vs dual clock case
localparam SINGLE_CLOCK = (_TECHMAP_CONNMAP_CLK2_ == _TECHMAP_CONNMAP_CLK3_);
localparam WIDTH = $sformatf("X%d", CFG_DBITS);
wire [13:0] ra, wa;
wire [35:0] rd, wd;
assign ra = {B1ADDR, {A_SHIFT{1'b1}}};
generate
if (CFG_ENABLE_A > 1)
assign wa = {A1ADDR, {(A_SHIFT-CFG_ENABLE_A){1'b1}}, A1EN};
else
assign wa = {A1ADDR, {A_SHIFT{1'b1}}};
endgenerate
assign wd = A1DATA;
assign B1DATA = rd[CFG_DBITS-1:0];
wire wck, rck;
generate
if (CLKPOL2)
assign wck = CLK2;
else
INV wck_inv_i (.A(CLK2), .Z(wck));
if (CLKPOL3)
assign rck = CLK3;
else
INV wck_inv_i (.A(CLK3), .Z(rck));
endgenerate
wire we = |A1EN;
localparam INIT_CHUNK_SIZE = (CFG_DBITS <= 4) ? 256 : 288;
function [319:0] permute_init;
input [INIT_CHUNK_SIZE-1:0] chunk;
integer i;
begin
if (CFG_DBITS <= 4) begin
for (i = 0; i < 32; i = i + 1'b1)
permute_init[i * 10 +: 10] = {2'b00, chunk[i * 8 +: 8]};
end else begin
for (i = 0; i < 32; i = i + 1'b1)
permute_init[i * 10 +: 10] = {1'b0, chunk[i * 9 +: 9]};
end
end
endfunction
generate
if (SINGLE_CLOCK) begin
PDPSC16K #(
.DATA_WIDTH_W(WIDTH),
.DATA_WIDTH_R(WIDTH),
.OUTREG("BYPASSED"),
.ECC("DISABLED"),
.GSR("DISABLED"),
`include "brams_init.vh"
) _TECHMAP_REPLACE_ (
.CLK(wck), .RST(1'b0),
.DI(wd), .ADW(wa), .CEW(we), .CSW(3'b111),
.ADR(ra), .DO(rd), .CER(B1EN), .CSR(3'b111)
);
end else begin
PDP16K #(
.DATA_WIDTH_W(WIDTH),
.DATA_WIDTH_R(WIDTH),
.OUTREG("BYPASSED"),
.ECC("DISABLED"),
.GSR("DISABLED"),
`include "brams_init.vh"
) _TECHMAP_REPLACE_ (
.CLKW(wck), .CLKR(rck), .RST(1'b0),
.DI(wd), .ADW(wa), .CEW(we), .CSW(3'b111),
.ADR(ra), .DO(rd), .CER(B1EN), .CSR(3'b111)
);
end
endgenerate
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk, fastclk
);
input clk;
input fastclk; // surefire lint_off_line UDDIXN
integer _mode; initial _mode=0;
reg [31:0] ord1; initial ord1 = 32'h1111;
wire [31:0] ord2;
reg [31:0] ord3;
wire [31:0] ord4;
wire [31:0] ord5;
wire [31:0] ord6;
wire [31:0] ord7;
// verilator lint_off UNOPT
t_chg_a a (
.a(ord1), .a_p1(ord2),
.b(ord4), .b_p1(ord5),
.c(ord3), .c_p1(ord4),
.d(ord6), .d_p1(ord7)
);
// surefire lint_off ASWEMB
assign ord6 = ord5 + 1;
// verilator lint_on UNOPT
always @ (/*AS*/ord2) ord3 = ord2 + 1;
always @ (fastclk) begin // surefire lint_off_line ALWLTR ALWMTR
if (_mode==1) begin
//$write("[%0t] t_chg: %d: Values: %x %x %x %x %x %x %x\n",$time,fastclk,ord1,ord2,ord3,ord4,ord5,ord6,ord7);
//if (ord2 == 2 && ord7 != 7) $stop;
end
end
always @ (posedge clk) begin
if (_mode==0) begin
$write("[%0t] t_chg: Running\n", $time);
_mode<=1;
ord1 <= 1;
end
else if (_mode==1) begin
_mode<=2;
if (ord7 !== 7) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module t_chg_a (/*AUTOARG*/
// Outputs
a_p1, b_p1, c_p1, d_p1,
// Inputs
a, b, c, d
);
input [31:0] a; output [31:0] a_p1; wire [31:0] a_p1 = a + 1;
input [31:0] b; output [31:0] b_p1; wire [31:0] b_p1 = b + 1;
input [31:0] c; output [31:0] c_p1; wire [31:0] c_p1 = c + 1;
input [31:0] d; output [31:0] d_p1; wire [31:0] d_p1 = d + 1;
endmodule
|
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
module Streaminner(
input clock,
input reset,
input io_input_enable,
input io_input_ctr_done,
input io_input_forever,
input io_input_rst,
input io_input_hasStreamIns,
input [31:0] io_input_nextState,
input [31:0] io_input_initState,
input io_input_doneCondition,
output io_output_done,
output io_output_ctr_en,
output io_output_ctr_inc,
output io_output_rst_en,
output [31:0] io_output_state
);
reg _T_32;
reg [31:0] _GEN_4;
wire _T_35;
wire _T_36;
wire _T_40;
reg _GEN_0;
reg [31:0] _GEN_5;
reg _GEN_1;
reg [31:0] _GEN_6;
reg _GEN_2;
reg [31:0] _GEN_7;
reg [31:0] _GEN_3;
reg [31:0] _GEN_8;
assign io_output_done = _T_40;
assign io_output_ctr_en = _GEN_0;
assign io_output_ctr_inc = _GEN_1;
assign io_output_rst_en = _GEN_2;
assign io_output_state = _GEN_3;
assign _T_35 = io_input_hasStreamIns ? 1'h1 : io_input_enable;
assign _T_36 = io_input_ctr_done & _T_35;
assign _T_40 = io_input_forever ? 1'h0 : _T_36;
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifndef verilator
#0.002 begin end
`endif
`ifdef RANDOMIZE_REG_INIT
_GEN_4 = {1{$random}};
_T_32 = _GEN_4[0:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_GEN_5 = {1{$random}};
_GEN_0 = _GEN_5[0:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_GEN_6 = {1{$random}};
_GEN_1 = _GEN_6[0:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_GEN_7 = {1{$random}};
_GEN_2 = _GEN_7[0:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_GEN_8 = {1{$random}};
_GEN_3 = _GEN_8[31:0];
`endif
end
`endif
always @(posedge clock) begin
if (reset) begin
_T_32 <= 1'h0;
end
end
endmodule
module SRFF_sp(
input clock,
input reset,
input io_input_set,
input io_input_reset,
input io_input_asyn_reset,
output io_output_data
);
reg _T_14;
reg [31:0] _GEN_0;
wire _T_18;
wire _T_19;
wire _T_20;
wire _T_22;
assign io_output_data = _T_22;
assign _T_18 = io_input_reset ? 1'h0 : _T_14;
assign _T_19 = io_input_set ? 1'h1 : _T_18;
assign _T_20 = io_input_asyn_reset ? 1'h0 : _T_19;
assign _T_22 = io_input_asyn_reset ? 1'h0 : _T_14;
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifndef verilator
#0.002 begin end
`endif
`ifdef RANDOMIZE_REG_INIT
_GEN_0 = {1{$random}};
_T_14 = _GEN_0[0:0];
`endif
end
`endif
always @(posedge clock) begin
if (reset) begin
_T_14 <= 1'h0;
end else begin
if (io_input_asyn_reset) begin
_T_14 <= 1'h0;
end else begin
if (io_input_set) begin
_T_14 <= 1'h1;
end else begin
if (io_input_reset) begin
_T_14 <= 1'h0;
end
end
end
end
end
endmodule
module AccelTop(
input clock,
input reset,
input io_enable,
output io_done,
input [23:0] io_stream_in_data,
input io_stream_in_startofpacket,
input io_stream_in_endofpacket,
input [1:0] io_stream_in_empty,
input io_stream_in_valid,
input io_stream_out_ready,
output io_stream_in_ready,
output [15:0] io_stream_out_data,
output io_stream_out_startofpacket,
output io_stream_out_endofpacket,
output io_stream_out_empty,
output io_stream_out_valid,
output [31:0] io_led_stream_out_data,
input [31:0] io_switch_stream_in_data
);
wire x264_ready;
wire x264_valid;
wire x265_ready;
wire x265_valid;
wire x266_ready;
wire x266_valid;
wire RootController_ctr_en;
wire RootController_datapath_en;
wire [15:0] x274_tuple;
wire [14:0] x282_tuple;
wire [15:0] x266_data;
wire [15:0] converted_data;
wire _T_80;
wire _T_81;
wire _T_83;
wire _T_84;
wire [15:0] _GEN_1;
wire _GEN_2;
wire _GEN_3;
wire [1:0] _GEN_4;
wire _T_86;
wire _T_87;
wire _T_88;
wire _T_89;
wire RootController_en;
wire RootController_sm_clock;
wire RootController_sm_reset;
wire RootController_sm_io_input_enable;
wire RootController_sm_io_input_ctr_done;
wire RootController_sm_io_input_forever;
wire RootController_sm_io_input_rst;
wire RootController_sm_io_input_hasStreamIns;
wire [31:0] RootController_sm_io_input_nextState;
wire [31:0] RootController_sm_io_input_initState;
wire RootController_sm_io_input_doneCondition;
wire RootController_sm_io_output_done;
wire RootController_sm_io_output_ctr_en;
wire RootController_sm_io_output_ctr_inc;
wire RootController_sm_io_output_rst_en;
wire [31:0] RootController_sm_io_output_state;
wire _T_90;
wire _T_91;
reg _T_96;
reg [31:0] _GEN_20;
wire done_latch_clock;
wire done_latch_reset;
wire done_latch_io_input_set;
wire done_latch_io_input_reset;
wire done_latch_io_input_asyn_reset;
wire done_latch_io_output_data;
wire _T_107;
wire x270;
wire [4:0] x271_apply;
wire [5:0] x272_apply;
wire [4:0] x273_apply;
wire [10:0] _T_116;
wire [15:0] _T_117;
wire [7:0] x275_number;
wire x275_debug_overflow;
wire [7:0] x276_number;
wire x276_debug_overflow;
wire [8:0] _T_131_number;
wire _T_131_debug_overflow;
wire [8:0] _T_137_number;
wire _T_137_debug_overflow;
wire [8:0] _T_143_number;
wire _T_143_debug_overflow;
wire _T_149;
wire _T_151;
wire [8:0] _T_153;
wire [8:0] _T_158;
wire _T_162;
wire _T_164;
wire [8:0] _T_166;
wire [8:0] _T_171;
wire [9:0] _T_172;
wire [8:0] _T_173;
wire [7:0] x277_sumx275_x276_number;
wire x277_sumx275_x276_debug_overflow;
wire _T_182;
wire _T_184;
wire [7:0] _T_186;
wire _T_189;
wire [7:0] _T_190;
wire [7:0] x278_number;
wire x278_debug_overflow;
wire [8:0] _T_199_number;
wire _T_199_debug_overflow;
wire [8:0] _T_205_number;
wire _T_205_debug_overflow;
wire [8:0] _T_211_number;
wire _T_211_debug_overflow;
wire _T_217;
wire _T_219;
wire [8:0] _T_221;
wire [8:0] _T_226;
wire _T_230;
wire _T_232;
wire [8:0] _T_234;
wire [8:0] _T_239;
wire [9:0] _T_240;
wire [8:0] _T_241;
wire [7:0] x279_sumx277_x278_number;
wire x279_sumx277_x278_debug_overflow;
wire _T_250;
wire _T_252;
wire [7:0] _T_254;
wire _T_257;
wire [7:0] _T_258;
wire [31:0] _T_263_number;
wire _T_263_debug_overflow;
wire [31:0] _GEN_5;
wire [7:0] _T_266;
wire [31:0] x280_number;
wire x280_debug_overflow;
wire [4:0] x281_number;
wire x281_debug_overflow;
wire [9:0] _T_280;
wire [14:0] _T_281;
wire [15:0] x283;
reg [31:0] _GEN_0;
reg [31:0] _GEN_21;
reg [31:0] _GEN_6;
reg [31:0] _GEN_22;
reg _GEN_7;
reg [31:0] _GEN_23;
reg _GEN_8;
reg [31:0] _GEN_24;
reg _GEN_9;
reg [31:0] _GEN_25;
reg _GEN_10;
reg [31:0] _GEN_26;
reg _GEN_11;
reg [31:0] _GEN_27;
reg _GEN_12;
reg [31:0] _GEN_28;
reg _GEN_13;
reg [31:0] _GEN_29;
reg _GEN_14;
reg [31:0] _GEN_30;
reg _GEN_15;
reg [31:0] _GEN_31;
reg _GEN_16;
reg [31:0] _GEN_32;
reg _GEN_17;
reg [31:0] _GEN_33;
reg _GEN_18;
reg [31:0] _GEN_34;
reg _GEN_19;
reg [31:0] _GEN_35;
Streaminner RootController_sm (
.clock(RootController_sm_clock),
.reset(RootController_sm_reset),
.io_input_enable(RootController_sm_io_input_enable),
.io_input_ctr_done(RootController_sm_io_input_ctr_done),
.io_input_forever(RootController_sm_io_input_forever),
.io_input_rst(RootController_sm_io_input_rst),
.io_input_hasStreamIns(RootController_sm_io_input_hasStreamIns),
.io_input_nextState(RootController_sm_io_input_nextState),
.io_input_initState(RootController_sm_io_input_initState),
.io_input_doneCondition(RootController_sm_io_input_doneCondition),
.io_output_done(RootController_sm_io_output_done),
.io_output_ctr_en(RootController_sm_io_output_ctr_en),
.io_output_ctr_inc(RootController_sm_io_output_ctr_inc),
.io_output_rst_en(RootController_sm_io_output_rst_en),
.io_output_state(RootController_sm_io_output_state)
);
SRFF_sp done_latch (
.clock(done_latch_clock),
.reset(done_latch_reset),
.io_input_set(done_latch_io_input_set),
.io_input_reset(done_latch_io_input_reset),
.io_input_asyn_reset(done_latch_io_input_asyn_reset),
.io_output_data(done_latch_io_output_data)
);
assign io_done = done_latch_io_output_data;
assign io_stream_in_ready = x265_ready;
assign io_stream_out_data = _GEN_1;
assign io_stream_out_startofpacket = _GEN_2;
assign io_stream_out_endofpacket = _GEN_3;
assign io_stream_out_empty = _GEN_4[0];
assign io_stream_out_valid = x266_valid;
assign io_led_stream_out_data = {{31'd0}, io_stream_in_ready};
assign x264_ready = _T_107;
assign x264_valid = 1'h1;
assign x265_ready = _T_107;
assign x265_valid = io_stream_in_valid;
assign x266_ready = io_stream_out_ready;
assign x266_valid = _T_107;
assign RootController_ctr_en = RootController_sm_io_output_done;
assign RootController_datapath_en = _T_91;
assign x274_tuple = _T_117;
assign x282_tuple = _T_281;
assign x266_data = x283;
assign converted_data = x266_data;
assign _T_80 = ~ io_stream_out_valid;
assign _T_81 = io_stream_out_ready | _T_80;
assign _T_83 = reset == 1'h0;
assign _T_84 = _T_83 & _T_81;
assign _GEN_1 = _T_84 ? converted_data : 16'h0;
assign _GEN_2 = _T_84 ? io_stream_in_startofpacket : 1'h0;
assign _GEN_3 = _T_84 ? io_stream_in_endofpacket : 1'h0;
assign _GEN_4 = _T_84 ? io_stream_in_empty : 2'h0;
assign _T_86 = io_done == 1'h0;
assign _T_87 = io_enable & _T_86;
assign _T_88 = _T_87 & x266_ready;
assign _T_89 = _T_88 & x265_valid;
assign RootController_en = _T_89 & x264_valid;
assign RootController_sm_clock = clock;
assign RootController_sm_reset = reset;
assign RootController_sm_io_input_enable = RootController_en;
assign RootController_sm_io_input_ctr_done = _T_96;
assign RootController_sm_io_input_forever = 1'h1;
assign RootController_sm_io_input_rst = reset;
assign RootController_sm_io_input_hasStreamIns = 1'h1;
assign RootController_sm_io_input_nextState = _GEN_0;
assign RootController_sm_io_input_initState = _GEN_6;
assign RootController_sm_io_input_doneCondition = _GEN_7;
assign _T_90 = ~ RootController_ctr_en;
assign _T_91 = RootController_en & _T_90;
assign done_latch_clock = clock;
assign done_latch_reset = reset;
assign done_latch_io_input_set = RootController_ctr_en;
assign done_latch_io_input_reset = reset;
assign done_latch_io_input_asyn_reset = reset;
assign _T_107 = RootController_en & RootController_datapath_en;
assign x270 = 32'h4 < io_switch_stream_in_data;
assign x271_apply = io_stream_in_data[23:19];
assign x272_apply = io_stream_in_data[15:10];
assign x273_apply = io_stream_in_data[7:3];
assign _T_116 = {x271_apply,x272_apply};
assign _T_117 = {_T_116,x273_apply};
assign x275_number = {{3'd0}, x271_apply};
assign x275_debug_overflow = _GEN_8;
assign x276_number = {{2'd0}, x272_apply};
assign x276_debug_overflow = _GEN_9;
assign _T_131_number = _T_173;
assign _T_131_debug_overflow = _GEN_10;
assign _T_137_number = _T_153;
assign _T_137_debug_overflow = _GEN_11;
assign _T_143_number = _T_166;
assign _T_143_debug_overflow = _GEN_12;
assign _T_149 = 1'h0;
assign _T_151 = _T_149;
assign _T_153 = _T_158;
assign _T_158 = {1'h0,x275_number};
assign _T_162 = 1'h0;
assign _T_164 = _T_162;
assign _T_166 = _T_171;
assign _T_171 = {1'h0,x276_number};
assign _T_172 = _T_137_number + _T_143_number;
assign _T_173 = _T_172[8:0];
assign x277_sumx275_x276_number = _T_186;
assign x277_sumx275_x276_debug_overflow = _T_189;
assign _T_182 = 1'h0;
assign _T_184 = _T_182;
assign _T_186 = _T_190;
assign _T_189 = _T_131_number[8];
assign _T_190 = _T_131_number[7:0];
assign x278_number = {{3'd0}, x273_apply};
assign x278_debug_overflow = _GEN_13;
assign _T_199_number = _T_241;
assign _T_199_debug_overflow = _GEN_14;
assign _T_205_number = _T_221;
assign _T_205_debug_overflow = _GEN_15;
assign _T_211_number = _T_234;
assign _T_211_debug_overflow = _GEN_16;
assign _T_217 = 1'h0;
assign _T_219 = _T_217;
assign _T_221 = _T_226;
assign _T_226 = {1'h0,x277_sumx275_x276_number};
assign _T_230 = 1'h0;
assign _T_232 = _T_230;
assign _T_234 = _T_239;
assign _T_239 = {1'h0,x278_number};
assign _T_240 = _T_205_number + _T_211_number;
assign _T_241 = _T_240[8:0];
assign x279_sumx277_x278_number = _T_254;
assign x279_sumx277_x278_debug_overflow = _T_257;
assign _T_250 = 1'h0;
assign _T_252 = _T_250;
assign _T_254 = _T_258;
assign _T_257 = _T_199_number[8];
assign _T_258 = _T_199_number[7:0];
assign _T_263_number = 32'h3;
assign _T_263_debug_overflow = _GEN_17;
assign _GEN_5 = {{24'd0}, x279_sumx277_x278_number};
assign _T_266 = _GEN_5 / _T_263_number;
assign x280_number = {{24'd0}, _T_266};
assign x280_debug_overflow = _GEN_18;
assign x281_number = x280_number[4:0];
assign x281_debug_overflow = _GEN_19;
assign _T_280 = {x281_number,x281_number};
assign _T_281 = {_T_280,x281_number};
assign x283 = x270 ? x274_tuple : {{1'd0}, x282_tuple};
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifndef verilator
#0.002 begin end
`endif
`ifdef RANDOMIZE_REG_INIT
_GEN_20 = {1{$random}};
_T_96 = _GEN_20[0:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_GEN_21 = {1{$random}};
_GEN_0 = _GEN_21[31:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_GEN_22 = {1{$random}};
_GEN_6 = _GEN_22[31:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_GEN_23 = {1{$random}};
_GEN_7 = _GEN_23[0:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_GEN_24 = {1{$random}};
_GEN_8 = _GEN_24[0:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_GEN_25 = {1{$random}};
_GEN_9 = _GEN_25[0:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_GEN_26 = {1{$random}};
_GEN_10 = _GEN_26[0:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_GEN_27 = {1{$random}};
_GEN_11 = _GEN_27[0:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_GEN_28 = {1{$random}};
_GEN_12 = _GEN_28[0:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_GEN_29 = {1{$random}};
_GEN_13 = _GEN_29[0:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_GEN_30 = {1{$random}};
_GEN_14 = _GEN_30[0:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_GEN_31 = {1{$random}};
_GEN_15 = _GEN_31[0:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_GEN_32 = {1{$random}};
_GEN_16 = _GEN_32[0:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_GEN_33 = {1{$random}};
_GEN_17 = _GEN_33[0:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_GEN_34 = {1{$random}};
_GEN_18 = _GEN_34[0:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_GEN_35 = {1{$random}};
_GEN_19 = _GEN_35[0:0];
`endif
end
`endif
always @(posedge clock) begin
if (reset) begin
_T_96 <= 1'h0;
end else begin
_T_96 <= _T_91;
end
end
endmodule
module FF(
input clock,
input reset,
input [63:0] io_in,
input [63:0] io_init,
output [63:0] io_out,
input io_enable
);
wire [63:0] d;
reg [63:0] ff;
reg [63:0] _GEN_0;
wire _T_13;
wire [63:0] _GEN_1;
assign io_out = ff;
assign d = _GEN_1;
assign _T_13 = io_enable == 1'h0;
assign _GEN_1 = _T_13 ? ff : io_in;
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifndef verilator
#0.002 begin end
`endif
`ifdef RANDOMIZE_REG_INIT
_GEN_0 = {2{$random}};
ff = _GEN_0[63:0];
`endif
end
`endif
always @(posedge clock) begin
if (reset) begin
ff <= io_init;
end else begin
ff <= d;
end
end
endmodule
module MuxN(
input clock,
input reset,
input [63:0] io_ins_0,
input [63:0] io_ins_1,
input io_sel,
output [63:0] io_out
);
wire [63:0] _GEN_0;
wire [63:0] _GEN_1;
assign io_out = _GEN_0;
assign _GEN_0 = _GEN_1;
assign _GEN_1 = io_sel ? io_ins_1 : io_ins_0;
endmodule
module RegFile(
input clock,
input reset,
input io_raddr,
input io_wen,
input io_waddr,
input [63:0] io_wdata,
output [63:0] io_rdata,
output [63:0] io_argIns_0,
output [63:0] io_argIns_1,
output io_argOuts_0_ready,
input io_argOuts_0_valid,
input [63:0] io_argOuts_0_bits
);
wire regs_0_clock;
wire regs_0_reset;
wire [63:0] regs_0_io_in;
wire [63:0] regs_0_io_init;
wire [63:0] regs_0_io_out;
wire regs_0_io_enable;
wire _T_50;
wire _T_51;
wire regs_1_clock;
wire regs_1_reset;
wire [63:0] regs_1_io_in;
wire [63:0] regs_1_io_init;
wire [63:0] regs_1_io_out;
wire regs_1_io_enable;
wire _T_55;
wire _T_59;
wire [63:0] _T_63;
wire rport_clock;
wire rport_reset;
wire [63:0] rport_io_ins_0;
wire [63:0] rport_io_ins_1;
wire rport_io_sel;
wire [63:0] rport_io_out;
wire [63:0] regOuts_0;
wire [63:0] regOuts_1;
wire [63:0] _T_73_0;
wire [63:0] _T_73_1;
reg _GEN_0;
reg [31:0] _GEN_1;
FF regs_0 (
.clock(regs_0_clock),
.reset(regs_0_reset),
.io_in(regs_0_io_in),
.io_init(regs_0_io_init),
.io_out(regs_0_io_out),
.io_enable(regs_0_io_enable)
);
FF regs_1 (
.clock(regs_1_clock),
.reset(regs_1_reset),
.io_in(regs_1_io_in),
.io_init(regs_1_io_init),
.io_out(regs_1_io_out),
.io_enable(regs_1_io_enable)
);
MuxN rport (
.clock(rport_clock),
.reset(rport_reset),
.io_ins_0(rport_io_ins_0),
.io_ins_1(rport_io_ins_1),
.io_sel(rport_io_sel),
.io_out(rport_io_out)
);
assign io_rdata = rport_io_out;
assign io_argIns_0 = _T_73_0;
assign io_argIns_1 = _T_73_1;
assign io_argOuts_0_ready = _GEN_0;
assign regs_0_clock = clock;
assign regs_0_reset = reset;
assign regs_0_io_in = io_wdata;
assign regs_0_io_init = 64'h0;
assign regs_0_io_enable = _T_51;
assign _T_50 = io_waddr == 1'h0;
assign _T_51 = io_wen & _T_50;
assign regs_1_clock = clock;
assign regs_1_reset = reset;
assign regs_1_io_in = _T_63;
assign regs_1_io_init = 64'h0;
assign regs_1_io_enable = _T_59;
assign _T_55 = io_wen & io_waddr;
assign _T_59 = _T_55 ? _T_55 : io_argOuts_0_valid;
assign _T_63 = _T_55 ? io_wdata : io_argOuts_0_bits;
assign rport_clock = clock;
assign rport_reset = reset;
assign rport_io_ins_0 = regOuts_0;
assign rport_io_ins_1 = regOuts_1;
assign rport_io_sel = io_raddr;
assign regOuts_0 = regs_0_io_out;
assign regOuts_1 = regs_1_io_out;
assign _T_73_0 = regOuts_0;
assign _T_73_1 = regOuts_1;
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifndef verilator
#0.002 begin end
`endif
`ifdef RANDOMIZE_REG_INIT
_GEN_1 = {1{$random}};
_GEN_0 = _GEN_1[0:0];
`endif
end
`endif
endmodule
module FF_2(
input clock,
input reset,
input io_in,
input io_init,
output io_out,
input io_enable
);
wire d;
reg ff;
reg [31:0] _GEN_0;
wire _T_13;
wire _GEN_1;
assign io_out = ff;
assign d = _GEN_1;
assign _T_13 = io_enable == 1'h0;
assign _GEN_1 = _T_13 ? ff : io_in;
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifndef verilator
#0.002 begin end
`endif
`ifdef RANDOMIZE_REG_INIT
_GEN_0 = {1{$random}};
ff = _GEN_0[0:0];
`endif
end
`endif
always @(posedge clock) begin
if (reset) begin
ff <= io_init;
end else begin
ff <= d;
end
end
endmodule
module Depulser(
input clock,
input reset,
input io_in,
input io_rst,
output io_out
);
wire r_clock;
wire r_reset;
wire r_io_in;
wire r_io_init;
wire r_io_out;
wire r_io_enable;
wire _T_9;
wire _T_11;
FF_2 r (
.clock(r_clock),
.reset(r_reset),
.io_in(r_io_in),
.io_init(r_io_init),
.io_out(r_io_out),
.io_enable(r_io_enable)
);
assign io_out = r_io_out;
assign r_clock = clock;
assign r_reset = reset;
assign r_io_in = _T_9;
assign r_io_init = 1'h0;
assign r_io_enable = _T_11;
assign _T_9 = io_rst ? 1'h0 : io_in;
assign _T_11 = io_in | io_rst;
endmodule
module FIFOArbiter(
input clock,
input reset,
output [63:0] io_deq_0,
output [63:0] io_deq_1,
output [63:0] io_deq_2,
output [63:0] io_deq_3,
output [63:0] io_deq_4,
output [63:0] io_deq_5,
output [63:0] io_deq_6,
output [63:0] io_deq_7,
output [63:0] io_deq_8,
output [63:0] io_deq_9,
output [63:0] io_deq_10,
output [63:0] io_deq_11,
output [63:0] io_deq_12,
output [63:0] io_deq_13,
output [63:0] io_deq_14,
output [63:0] io_deq_15,
input io_deqVld,
output io_empty,
output io_forceTag_ready,
input io_forceTag_valid,
input io_forceTag_bits,
output io_tag,
input io_config_chainWrite,
input io_config_chainRead
);
wire tagFF_clock;
wire tagFF_reset;
wire tagFF_io_in;
wire tagFF_io_init;
wire tagFF_io_out;
wire tagFF_io_enable;
wire [63:0] _T_162_0;
wire [63:0] _T_162_1;
wire [63:0] _T_162_2;
wire [63:0] _T_162_3;
wire [63:0] _T_162_4;
wire [63:0] _T_162_5;
wire [63:0] _T_162_6;
wire [63:0] _T_162_7;
wire [63:0] _T_162_8;
wire [63:0] _T_162_9;
wire [63:0] _T_162_10;
wire [63:0] _T_162_11;
wire [63:0] _T_162_12;
wire [63:0] _T_162_13;
wire [63:0] _T_162_14;
wire [63:0] _T_162_15;
reg _GEN_0;
reg [31:0] _GEN_3;
reg _GEN_1;
reg [31:0] _GEN_4;
reg _GEN_2;
reg [31:0] _GEN_5;
FF_2 tagFF (
.clock(tagFF_clock),
.reset(tagFF_reset),
.io_in(tagFF_io_in),
.io_init(tagFF_io_init),
.io_out(tagFF_io_out),
.io_enable(tagFF_io_enable)
);
assign io_deq_0 = _T_162_0;
assign io_deq_1 = _T_162_1;
assign io_deq_2 = _T_162_2;
assign io_deq_3 = _T_162_3;
assign io_deq_4 = _T_162_4;
assign io_deq_5 = _T_162_5;
assign io_deq_6 = _T_162_6;
assign io_deq_7 = _T_162_7;
assign io_deq_8 = _T_162_8;
assign io_deq_9 = _T_162_9;
assign io_deq_10 = _T_162_10;
assign io_deq_11 = _T_162_11;
assign io_deq_12 = _T_162_12;
assign io_deq_13 = _T_162_13;
assign io_deq_14 = _T_162_14;
assign io_deq_15 = _T_162_15;
assign io_empty = 1'h1;
assign io_forceTag_ready = _GEN_0;
assign io_tag = 1'h0;
assign tagFF_clock = clock;
assign tagFF_reset = reset;
assign tagFF_io_in = _GEN_1;
assign tagFF_io_init = 1'h0;
assign tagFF_io_enable = _GEN_2;
assign _T_162_0 = 64'h0;
assign _T_162_1 = 64'h0;
assign _T_162_2 = 64'h0;
assign _T_162_3 = 64'h0;
assign _T_162_4 = 64'h0;
assign _T_162_5 = 64'h0;
assign _T_162_6 = 64'h0;
assign _T_162_7 = 64'h0;
assign _T_162_8 = 64'h0;
assign _T_162_9 = 64'h0;
assign _T_162_10 = 64'h0;
assign _T_162_11 = 64'h0;
assign _T_162_12 = 64'h0;
assign _T_162_13 = 64'h0;
assign _T_162_14 = 64'h0;
assign _T_162_15 = 64'h0;
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifndef verilator
#0.002 begin end
`endif
`ifdef RANDOMIZE_REG_INIT
_GEN_3 = {1{$random}};
_GEN_0 = _GEN_3[0:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_GEN_4 = {1{$random}};
_GEN_1 = _GEN_4[0:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_GEN_5 = {1{$random}};
_GEN_2 = _GEN_5[0:0];
`endif
end
`endif
endmodule
module FIFOArbiter_1(
input clock,
input reset,
output io_deq_0,
output io_deq_1,
output io_deq_2,
output io_deq_3,
output io_deq_4,
output io_deq_5,
output io_deq_6,
output io_deq_7,
output io_deq_8,
output io_deq_9,
output io_deq_10,
output io_deq_11,
output io_deq_12,
output io_deq_13,
output io_deq_14,
output io_deq_15,
input io_deqVld,
output io_empty,
output io_forceTag_ready,
input io_forceTag_valid,
input io_forceTag_bits,
output io_tag,
input io_config_chainWrite,
input io_config_chainRead
);
wire tagFF_clock;
wire tagFF_reset;
wire tagFF_io_in;
wire tagFF_io_init;
wire tagFF_io_out;
wire tagFF_io_enable;
wire _T_162_0;
wire _T_162_1;
wire _T_162_2;
wire _T_162_3;
wire _T_162_4;
wire _T_162_5;
wire _T_162_6;
wire _T_162_7;
wire _T_162_8;
wire _T_162_9;
wire _T_162_10;
wire _T_162_11;
wire _T_162_12;
wire _T_162_13;
wire _T_162_14;
wire _T_162_15;
reg _GEN_0;
reg [31:0] _GEN_3;
reg _GEN_1;
reg [31:0] _GEN_4;
reg _GEN_2;
reg [31:0] _GEN_5;
FF_2 tagFF (
.clock(tagFF_clock),
.reset(tagFF_reset),
.io_in(tagFF_io_in),
.io_init(tagFF_io_init),
.io_out(tagFF_io_out),
.io_enable(tagFF_io_enable)
);
assign io_deq_0 = _T_162_0;
assign io_deq_1 = _T_162_1;
assign io_deq_2 = _T_162_2;
assign io_deq_3 = _T_162_3;
assign io_deq_4 = _T_162_4;
assign io_deq_5 = _T_162_5;
assign io_deq_6 = _T_162_6;
assign io_deq_7 = _T_162_7;
assign io_deq_8 = _T_162_8;
assign io_deq_9 = _T_162_9;
assign io_deq_10 = _T_162_10;
assign io_deq_11 = _T_162_11;
assign io_deq_12 = _T_162_12;
assign io_deq_13 = _T_162_13;
assign io_deq_14 = _T_162_14;
assign io_deq_15 = _T_162_15;
assign io_empty = 1'h1;
assign io_forceTag_ready = _GEN_0;
assign io_tag = 1'h0;
assign tagFF_clock = clock;
assign tagFF_reset = reset;
assign tagFF_io_in = _GEN_1;
assign tagFF_io_init = 1'h0;
assign tagFF_io_enable = _GEN_2;
assign _T_162_0 = 1'h0;
assign _T_162_1 = 1'h0;
assign _T_162_2 = 1'h0;
assign _T_162_3 = 1'h0;
assign _T_162_4 = 1'h0;
assign _T_162_5 = 1'h0;
assign _T_162_6 = 1'h0;
assign _T_162_7 = 1'h0;
assign _T_162_8 = 1'h0;
assign _T_162_9 = 1'h0;
assign _T_162_10 = 1'h0;
assign _T_162_11 = 1'h0;
assign _T_162_12 = 1'h0;
assign _T_162_13 = 1'h0;
assign _T_162_14 = 1'h0;
assign _T_162_15 = 1'h0;
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifndef verilator
#0.002 begin end
`endif
`ifdef RANDOMIZE_REG_INIT
_GEN_3 = {1{$random}};
_GEN_0 = _GEN_3[0:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_GEN_4 = {1{$random}};
_GEN_1 = _GEN_4[0:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_GEN_5 = {1{$random}};
_GEN_2 = _GEN_5[0:0];
`endif
end
`endif
endmodule
module FIFOArbiter_2(
input clock,
input reset,
output [31:0] io_deq_0,
output [31:0] io_deq_1,
output [31:0] io_deq_2,
output [31:0] io_deq_3,
output [31:0] io_deq_4,
output [31:0] io_deq_5,
output [31:0] io_deq_6,
output [31:0] io_deq_7,
output [31:0] io_deq_8,
output [31:0] io_deq_9,
output [31:0] io_deq_10,
output [31:0] io_deq_11,
output [31:0] io_deq_12,
output [31:0] io_deq_13,
output [31:0] io_deq_14,
output [31:0] io_deq_15,
input io_deqVld,
output io_empty,
output io_forceTag_ready,
input io_forceTag_valid,
input io_forceTag_bits,
output io_tag,
input io_config_chainWrite,
input io_config_chainRead
);
wire tagFF_clock;
wire tagFF_reset;
wire tagFF_io_in;
wire tagFF_io_init;
wire tagFF_io_out;
wire tagFF_io_enable;
wire [31:0] _T_162_0;
wire [31:0] _T_162_1;
wire [31:0] _T_162_2;
wire [31:0] _T_162_3;
wire [31:0] _T_162_4;
wire [31:0] _T_162_5;
wire [31:0] _T_162_6;
wire [31:0] _T_162_7;
wire [31:0] _T_162_8;
wire [31:0] _T_162_9;
wire [31:0] _T_162_10;
wire [31:0] _T_162_11;
wire [31:0] _T_162_12;
wire [31:0] _T_162_13;
wire [31:0] _T_162_14;
wire [31:0] _T_162_15;
reg _GEN_0;
reg [31:0] _GEN_3;
reg _GEN_1;
reg [31:0] _GEN_4;
reg _GEN_2;
reg [31:0] _GEN_5;
FF_2 tagFF (
.clock(tagFF_clock),
.reset(tagFF_reset),
.io_in(tagFF_io_in),
.io_init(tagFF_io_init),
.io_out(tagFF_io_out),
.io_enable(tagFF_io_enable)
);
assign io_deq_0 = _T_162_0;
assign io_deq_1 = _T_162_1;
assign io_deq_2 = _T_162_2;
assign io_deq_3 = _T_162_3;
assign io_deq_4 = _T_162_4;
assign io_deq_5 = _T_162_5;
assign io_deq_6 = _T_162_6;
assign io_deq_7 = _T_162_7;
assign io_deq_8 = _T_162_8;
assign io_deq_9 = _T_162_9;
assign io_deq_10 = _T_162_10;
assign io_deq_11 = _T_162_11;
assign io_deq_12 = _T_162_12;
assign io_deq_13 = _T_162_13;
assign io_deq_14 = _T_162_14;
assign io_deq_15 = _T_162_15;
assign io_empty = 1'h1;
assign io_forceTag_ready = _GEN_0;
assign io_tag = 1'h0;
assign tagFF_clock = clock;
assign tagFF_reset = reset;
assign tagFF_io_in = _GEN_1;
assign tagFF_io_init = 1'h0;
assign tagFF_io_enable = _GEN_2;
assign _T_162_0 = 32'h0;
assign _T_162_1 = 32'h0;
assign _T_162_2 = 32'h0;
assign _T_162_3 = 32'h0;
assign _T_162_4 = 32'h0;
assign _T_162_5 = 32'h0;
assign _T_162_6 = 32'h0;
assign _T_162_7 = 32'h0;
assign _T_162_8 = 32'h0;
assign _T_162_9 = 32'h0;
assign _T_162_10 = 32'h0;
assign _T_162_11 = 32'h0;
assign _T_162_12 = 32'h0;
assign _T_162_13 = 32'h0;
assign _T_162_14 = 32'h0;
assign _T_162_15 = 32'h0;
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifndef verilator
#0.002 begin end
`endif
`ifdef RANDOMIZE_REG_INIT
_GEN_3 = {1{$random}};
_GEN_0 = _GEN_3[0:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_GEN_4 = {1{$random}};
_GEN_1 = _GEN_4[0:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_GEN_5 = {1{$random}};
_GEN_2 = _GEN_5[0:0];
`endif
end
`endif
endmodule
module FIFOArbiterWidthConvert(
input clock,
input reset,
output [31:0] io_deq_0,
output [31:0] io_deq_1,
output [31:0] io_deq_2,
output [31:0] io_deq_3,
output [31:0] io_deq_4,
output [31:0] io_deq_5,
output [31:0] io_deq_6,
output [31:0] io_deq_7,
output [31:0] io_deq_8,
output [31:0] io_deq_9,
output [31:0] io_deq_10,
output [31:0] io_deq_11,
output [31:0] io_deq_12,
output [31:0] io_deq_13,
output [31:0] io_deq_14,
output [31:0] io_deq_15,
input io_deqVld,
output io_empty,
output io_forceTag_ready,
input io_forceTag_valid,
input io_forceTag_bits,
output io_tag
);
wire tagFF_clock;
wire tagFF_reset;
wire tagFF_io_in;
wire tagFF_io_init;
wire tagFF_io_out;
wire tagFF_io_enable;
wire [31:0] _T_79_0;
wire [31:0] _T_79_1;
wire [31:0] _T_79_2;
wire [31:0] _T_79_3;
wire [31:0] _T_79_4;
wire [31:0] _T_79_5;
wire [31:0] _T_79_6;
wire [31:0] _T_79_7;
wire [31:0] _T_79_8;
wire [31:0] _T_79_9;
wire [31:0] _T_79_10;
wire [31:0] _T_79_11;
wire [31:0] _T_79_12;
wire [31:0] _T_79_13;
wire [31:0] _T_79_14;
wire [31:0] _T_79_15;
reg _GEN_0;
reg [31:0] _GEN_3;
reg _GEN_1;
reg [31:0] _GEN_4;
reg _GEN_2;
reg [31:0] _GEN_5;
FF_2 tagFF (
.clock(tagFF_clock),
.reset(tagFF_reset),
.io_in(tagFF_io_in),
.io_init(tagFF_io_init),
.io_out(tagFF_io_out),
.io_enable(tagFF_io_enable)
);
assign io_deq_0 = _T_79_0;
assign io_deq_1 = _T_79_1;
assign io_deq_2 = _T_79_2;
assign io_deq_3 = _T_79_3;
assign io_deq_4 = _T_79_4;
assign io_deq_5 = _T_79_5;
assign io_deq_6 = _T_79_6;
assign io_deq_7 = _T_79_7;
assign io_deq_8 = _T_79_8;
assign io_deq_9 = _T_79_9;
assign io_deq_10 = _T_79_10;
assign io_deq_11 = _T_79_11;
assign io_deq_12 = _T_79_12;
assign io_deq_13 = _T_79_13;
assign io_deq_14 = _T_79_14;
assign io_deq_15 = _T_79_15;
assign io_empty = 1'h1;
assign io_forceTag_ready = _GEN_0;
assign io_tag = 1'h0;
assign tagFF_clock = clock;
assign tagFF_reset = reset;
assign tagFF_io_in = _GEN_1;
assign tagFF_io_init = 1'h0;
assign tagFF_io_enable = _GEN_2;
assign _T_79_0 = 32'h0;
assign _T_79_1 = 32'h0;
assign _T_79_2 = 32'h0;
assign _T_79_3 = 32'h0;
assign _T_79_4 = 32'h0;
assign _T_79_5 = 32'h0;
assign _T_79_6 = 32'h0;
assign _T_79_7 = 32'h0;
assign _T_79_8 = 32'h0;
assign _T_79_9 = 32'h0;
assign _T_79_10 = 32'h0;
assign _T_79_11 = 32'h0;
assign _T_79_12 = 32'h0;
assign _T_79_13 = 32'h0;
assign _T_79_14 = 32'h0;
assign _T_79_15 = 32'h0;
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifndef verilator
#0.002 begin end
`endif
`ifdef RANDOMIZE_REG_INIT
_GEN_3 = {1{$random}};
_GEN_0 = _GEN_3[0:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_GEN_4 = {1{$random}};
_GEN_1 = _GEN_4[0:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_GEN_5 = {1{$random}};
_GEN_2 = _GEN_5[0:0];
`endif
end
`endif
endmodule
module FF_8(
input clock,
input reset,
input [31:0] io_in,
input [31:0] io_init,
output [31:0] io_out,
input io_enable
);
wire [31:0] d;
reg [31:0] ff;
reg [31:0] _GEN_0;
wire _T_13;
wire [31:0] _GEN_1;
assign io_out = ff;
assign d = _GEN_1;
assign _T_13 = io_enable == 1'h0;
assign _GEN_1 = _T_13 ? ff : io_in;
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifndef verilator
#0.002 begin end
`endif
`ifdef RANDOMIZE_REG_INIT
_GEN_0 = {1{$random}};
ff = _GEN_0[31:0];
`endif
end
`endif
always @(posedge clock) begin
if (reset) begin
ff <= io_init;
end else begin
ff <= d;
end
end
endmodule
module Counter(
input clock,
input reset,
input [31:0] io_max,
input [31:0] io_stride,
output [31:0] io_out,
output [31:0] io_next,
input io_reset,
input io_enable,
input io_saturate,
output io_done
);
wire reg$_clock;
wire reg$_reset;
wire [31:0] reg$_io_in;
wire [31:0] reg$_io_init;
wire [31:0] reg$_io_out;
wire reg$_io_enable;
wire _T_18;
wire [32:0] count;
wire [32:0] _GEN_2;
wire [33:0] _T_20;
wire [32:0] newval;
wire [32:0] _GEN_3;
wire isMax;
wire [32:0] _T_21;
wire [32:0] next;
wire _T_23;
wire [32:0] _GEN_1;
wire _T_24;
FF_8 reg$ (
.clock(reg$_clock),
.reset(reg$_reset),
.io_in(reg$_io_in),
.io_init(reg$_io_init),
.io_out(reg$_io_out),
.io_enable(reg$_io_enable)
);
assign io_out = count[31:0];
assign io_next = next[31:0];
assign io_done = _T_24;
assign reg$_clock = clock;
assign reg$_reset = reset;
assign reg$_io_in = _GEN_1[31:0];
assign reg$_io_init = 32'h0;
assign reg$_io_enable = _T_18;
assign _T_18 = io_reset | io_enable;
assign count = {1'h0,reg$_io_out};
assign _GEN_2 = {{1'd0}, io_stride};
assign _T_20 = count + _GEN_2;
assign newval = _T_20[32:0];
assign _GEN_3 = {{1'd0}, io_max};
assign isMax = newval >= _GEN_3;
assign _T_21 = io_saturate ? count : 33'h0;
assign next = isMax ? _T_21 : newval;
assign _T_23 = io_reset == 1'h0;
assign _GEN_1 = _T_23 ? next : 33'h0;
assign _T_24 = io_enable & isMax;
endmodule
module FF_9(
input clock,
input reset,
input [10:0] io_in,
input [10:0] io_init,
output [10:0] io_out,
input io_enable
);
wire [10:0] d;
reg [10:0] ff;
reg [31:0] _GEN_0;
wire _T_13;
wire [10:0] _GEN_1;
assign io_out = ff;
assign d = _GEN_1;
assign _T_13 = io_enable == 1'h0;
assign _GEN_1 = _T_13 ? ff : io_in;
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifndef verilator
#0.002 begin end
`endif
`ifdef RANDOMIZE_REG_INIT
_GEN_0 = {1{$random}};
ff = _GEN_0[10:0];
`endif
end
`endif
always @(posedge clock) begin
if (reset) begin
ff <= io_init;
end else begin
ff <= d;
end
end
endmodule
module Counter_1(
input clock,
input reset,
input [10:0] io_max,
input [10:0] io_stride,
output [10:0] io_out,
output [10:0] io_next,
input io_reset,
input io_enable,
input io_saturate,
output io_done
);
wire reg$_clock;
wire reg$_reset;
wire [10:0] reg$_io_in;
wire [10:0] reg$_io_init;
wire [10:0] reg$_io_out;
wire reg$_io_enable;
wire _T_18;
wire [11:0] count;
wire [11:0] _GEN_2;
wire [12:0] _T_20;
wire [11:0] newval;
wire [11:0] _GEN_3;
wire isMax;
wire [11:0] _T_21;
wire [11:0] next;
wire _T_23;
wire [11:0] _GEN_1;
wire _T_24;
FF_9 reg$ (
.clock(reg$_clock),
.reset(reg$_reset),
.io_in(reg$_io_in),
.io_init(reg$_io_init),
.io_out(reg$_io_out),
.io_enable(reg$_io_enable)
);
assign io_out = count[10:0];
assign io_next = next[10:0];
assign io_done = _T_24;
assign reg$_clock = clock;
assign reg$_reset = reset;
assign reg$_io_in = _GEN_1[10:0];
assign reg$_io_init = 11'h0;
assign reg$_io_enable = _T_18;
assign _T_18 = io_reset | io_enable;
assign count = {1'h0,reg$_io_out};
assign _GEN_2 = {{1'd0}, io_stride};
assign _T_20 = count + _GEN_2;
assign newval = _T_20[11:0];
assign _GEN_3 = {{1'd0}, io_max};
assign isMax = newval >= _GEN_3;
assign _T_21 = io_saturate ? count : 12'h0;
assign next = isMax ? _T_21 : newval;
assign _T_23 = io_reset == 1'h0;
assign _GEN_1 = _T_23 ? next : 12'h0;
assign _T_24 = io_enable & isMax;
endmodule
module MAGCore(
input clock,
input reset,
input io_dram_cmd_ready,
output io_dram_cmd_valid,
output [63:0] io_dram_cmd_bits_addr,
output io_dram_cmd_bits_isWr,
output [31:0] io_dram_cmd_bits_tag,
output [31:0] io_dram_cmd_bits_streamId,
output [31:0] io_dram_cmd_bits_wdata_0,
output [31:0] io_dram_cmd_bits_wdata_1,
output [31:0] io_dram_cmd_bits_wdata_2,
output [31:0] io_dram_cmd_bits_wdata_3,
output [31:0] io_dram_cmd_bits_wdata_4,
output [31:0] io_dram_cmd_bits_wdata_5,
output [31:0] io_dram_cmd_bits_wdata_6,
output [31:0] io_dram_cmd_bits_wdata_7,
output [31:0] io_dram_cmd_bits_wdata_8,
output [31:0] io_dram_cmd_bits_wdata_9,
output [31:0] io_dram_cmd_bits_wdata_10,
output [31:0] io_dram_cmd_bits_wdata_11,
output [31:0] io_dram_cmd_bits_wdata_12,
output [31:0] io_dram_cmd_bits_wdata_13,
output [31:0] io_dram_cmd_bits_wdata_14,
output [31:0] io_dram_cmd_bits_wdata_15,
output io_dram_resp_ready,
input io_dram_resp_valid,
input [31:0] io_dram_resp_bits_rdata_0,
input [31:0] io_dram_resp_bits_rdata_1,
input [31:0] io_dram_resp_bits_rdata_2,
input [31:0] io_dram_resp_bits_rdata_3,
input [31:0] io_dram_resp_bits_rdata_4,
input [31:0] io_dram_resp_bits_rdata_5,
input [31:0] io_dram_resp_bits_rdata_6,
input [31:0] io_dram_resp_bits_rdata_7,
input [31:0] io_dram_resp_bits_rdata_8,
input [31:0] io_dram_resp_bits_rdata_9,
input [31:0] io_dram_resp_bits_rdata_10,
input [31:0] io_dram_resp_bits_rdata_11,
input [31:0] io_dram_resp_bits_rdata_12,
input [31:0] io_dram_resp_bits_rdata_13,
input [31:0] io_dram_resp_bits_rdata_14,
input [31:0] io_dram_resp_bits_rdata_15,
input [31:0] io_dram_resp_bits_tag,
input [31:0] io_dram_resp_bits_streamId,
input io_config_scatterGather
);
wire addrFifo_clock;
wire addrFifo_reset;
wire [63:0] addrFifo_io_deq_0;
wire [63:0] addrFifo_io_deq_1;
wire [63:0] addrFifo_io_deq_2;
wire [63:0] addrFifo_io_deq_3;
wire [63:0] addrFifo_io_deq_4;
wire [63:0] addrFifo_io_deq_5;
wire [63:0] addrFifo_io_deq_6;
wire [63:0] addrFifo_io_deq_7;
wire [63:0] addrFifo_io_deq_8;
wire [63:0] addrFifo_io_deq_9;
wire [63:0] addrFifo_io_deq_10;
wire [63:0] addrFifo_io_deq_11;
wire [63:0] addrFifo_io_deq_12;
wire [63:0] addrFifo_io_deq_13;
wire [63:0] addrFifo_io_deq_14;
wire [63:0] addrFifo_io_deq_15;
wire addrFifo_io_deqVld;
wire addrFifo_io_empty;
wire addrFifo_io_forceTag_ready;
wire addrFifo_io_forceTag_valid;
wire addrFifo_io_forceTag_bits;
wire addrFifo_io_tag;
wire addrFifo_io_config_chainWrite;
wire addrFifo_io_config_chainRead;
wire addrFifoConfig_chainWrite;
wire addrFifoConfig_chainRead;
wire _T_84;
wire [57:0] burstAddrs_0;
wire isWrFifo_clock;
wire isWrFifo_reset;
wire isWrFifo_io_deq_0;
wire isWrFifo_io_deq_1;
wire isWrFifo_io_deq_2;
wire isWrFifo_io_deq_3;
wire isWrFifo_io_deq_4;
wire isWrFifo_io_deq_5;
wire isWrFifo_io_deq_6;
wire isWrFifo_io_deq_7;
wire isWrFifo_io_deq_8;
wire isWrFifo_io_deq_9;
wire isWrFifo_io_deq_10;
wire isWrFifo_io_deq_11;
wire isWrFifo_io_deq_12;
wire isWrFifo_io_deq_13;
wire isWrFifo_io_deq_14;
wire isWrFifo_io_deq_15;
wire isWrFifo_io_deqVld;
wire isWrFifo_io_empty;
wire isWrFifo_io_forceTag_ready;
wire isWrFifo_io_forceTag_valid;
wire isWrFifo_io_forceTag_bits;
wire isWrFifo_io_tag;
wire isWrFifo_io_config_chainWrite;
wire isWrFifo_io_config_chainRead;
wire isWrFifoConfig_chainWrite;
wire isWrFifoConfig_chainRead;
wire sizeFifo_clock;
wire sizeFifo_reset;
wire [31:0] sizeFifo_io_deq_0;
wire [31:0] sizeFifo_io_deq_1;
wire [31:0] sizeFifo_io_deq_2;
wire [31:0] sizeFifo_io_deq_3;
wire [31:0] sizeFifo_io_deq_4;
wire [31:0] sizeFifo_io_deq_5;
wire [31:0] sizeFifo_io_deq_6;
wire [31:0] sizeFifo_io_deq_7;
wire [31:0] sizeFifo_io_deq_8;
wire [31:0] sizeFifo_io_deq_9;
wire [31:0] sizeFifo_io_deq_10;
wire [31:0] sizeFifo_io_deq_11;
wire [31:0] sizeFifo_io_deq_12;
wire [31:0] sizeFifo_io_deq_13;
wire [31:0] sizeFifo_io_deq_14;
wire [31:0] sizeFifo_io_deq_15;
wire sizeFifo_io_deqVld;
wire sizeFifo_io_empty;
wire sizeFifo_io_forceTag_ready;
wire sizeFifo_io_forceTag_valid;
wire sizeFifo_io_forceTag_bits;
wire sizeFifo_io_tag;
wire sizeFifo_io_config_chainWrite;
wire sizeFifo_io_config_chainRead;
wire sizeFifoConfig_chainWrite;
wire sizeFifoConfig_chainRead;
wire [25:0] _T_102;
wire [5:0] _T_103;
wire _T_105;
wire [25:0] _GEN_0;
wire [26:0] _T_106;
wire [25:0] sizeInBursts;
wire wdataFifo_clock;
wire wdataFifo_reset;
wire [31:0] wdataFifo_io_deq_0;
wire [31:0] wdataFifo_io_deq_1;
wire [31:0] wdataFifo_io_deq_2;
wire [31:0] wdataFifo_io_deq_3;
wire [31:0] wdataFifo_io_deq_4;
wire [31:0] wdataFifo_io_deq_5;
wire [31:0] wdataFifo_io_deq_6;
wire [31:0] wdataFifo_io_deq_7;
wire [31:0] wdataFifo_io_deq_8;
wire [31:0] wdataFifo_io_deq_9;
wire [31:0] wdataFifo_io_deq_10;
wire [31:0] wdataFifo_io_deq_11;
wire [31:0] wdataFifo_io_deq_12;
wire [31:0] wdataFifo_io_deq_13;
wire [31:0] wdataFifo_io_deq_14;
wire [31:0] wdataFifo_io_deq_15;
wire wdataFifo_io_deqVld;
wire wdataFifo_io_empty;
wire wdataFifo_io_forceTag_ready;
wire wdataFifo_io_forceTag_valid;
wire wdataFifo_io_forceTag_bits;
wire wdataFifo_io_tag;
wire wrPhase_clock;
wire wrPhase_reset;
wire wrPhase_io_input_set;
wire wrPhase_io_input_reset;
wire wrPhase_io_input_asyn_reset;
wire wrPhase_io_output_data;
wire _T_107;
wire _T_108;
wire _T_109;
wire _T_110;
wire _T_111;
wire _T_112;
wire _T_114;
wire burstVld;
wire issued;
wire issuedFF_clock;
wire issuedFF_reset;
wire issuedFF_io_in;
wire issuedFF_io_init;
wire issuedFF_io_out;
wire issuedFF_io_enable;
wire _T_117;
wire _T_118;
wire _T_119;
wire [1:0] _T_123;
wire [1:0] _T_124;
wire _T_125;
wire burstCounter_clock;
wire burstCounter_reset;
wire [31:0] burstCounter_io_max;
wire [31:0] burstCounter_io_stride;
wire [31:0] burstCounter_io_out;
wire [31:0] burstCounter_io_next;
wire burstCounter_io_reset;
wire burstCounter_io_enable;
wire burstCounter_io_saturate;
wire burstCounter_io_done;
wire [25:0] _T_129;
wire _T_132;
wire _T_133;
wire _T_134;
wire _T_135;
wire _T_136;
wire burstTagCounter_clock;
wire burstTagCounter_reset;
wire [10:0] burstTagCounter_io_max;
wire [10:0] burstTagCounter_io_stride;
wire [10:0] burstTagCounter_io_out;
wire [10:0] burstTagCounter_io_next;
wire burstTagCounter_io_reset;
wire burstTagCounter_io_enable;
wire burstTagCounter_io_saturate;
wire burstTagCounter_io_done;
wire _T_147;
wire _T_148;
wire _T_150;
wire tagOut_streamTag;
wire [30:0] tagOut_burstTag;
wire [57:0] _T_156;
wire [57:0] _GEN_1;
wire [58:0] _T_157;
wire [57:0] _T_158;
wire [63:0] _T_160;
wire [31:0] _T_161;
wire _T_163;
reg _T_166;
reg [31:0] _GEN_7;
wire _T_173;
wire [31:0] issuedTag;
reg _GEN_2;
reg [31:0] _GEN_8;
reg _GEN_3;
reg [31:0] _GEN_9;
reg _GEN_4;
reg [31:0] _GEN_10;
reg _GEN_5;
reg [31:0] _GEN_11;
reg _GEN_6;
reg [31:0] _GEN_12;
FIFOArbiter addrFifo (
.clock(addrFifo_clock),
.reset(addrFifo_reset),
.io_deq_0(addrFifo_io_deq_0),
.io_deq_1(addrFifo_io_deq_1),
.io_deq_2(addrFifo_io_deq_2),
.io_deq_3(addrFifo_io_deq_3),
.io_deq_4(addrFifo_io_deq_4),
.io_deq_5(addrFifo_io_deq_5),
.io_deq_6(addrFifo_io_deq_6),
.io_deq_7(addrFifo_io_deq_7),
.io_deq_8(addrFifo_io_deq_8),
.io_deq_9(addrFifo_io_deq_9),
.io_deq_10(addrFifo_io_deq_10),
.io_deq_11(addrFifo_io_deq_11),
.io_deq_12(addrFifo_io_deq_12),
.io_deq_13(addrFifo_io_deq_13),
.io_deq_14(addrFifo_io_deq_14),
.io_deq_15(addrFifo_io_deq_15),
.io_deqVld(addrFifo_io_deqVld),
.io_empty(addrFifo_io_empty),
.io_forceTag_ready(addrFifo_io_forceTag_ready),
.io_forceTag_valid(addrFifo_io_forceTag_valid),
.io_forceTag_bits(addrFifo_io_forceTag_bits),
.io_tag(addrFifo_io_tag),
.io_config_chainWrite(addrFifo_io_config_chainWrite),
.io_config_chainRead(addrFifo_io_config_chainRead)
);
FIFOArbiter_1 isWrFifo (
.clock(isWrFifo_clock),
.reset(isWrFifo_reset),
.io_deq_0(isWrFifo_io_deq_0),
.io_deq_1(isWrFifo_io_deq_1),
.io_deq_2(isWrFifo_io_deq_2),
.io_deq_3(isWrFifo_io_deq_3),
.io_deq_4(isWrFifo_io_deq_4),
.io_deq_5(isWrFifo_io_deq_5),
.io_deq_6(isWrFifo_io_deq_6),
.io_deq_7(isWrFifo_io_deq_7),
.io_deq_8(isWrFifo_io_deq_8),
.io_deq_9(isWrFifo_io_deq_9),
.io_deq_10(isWrFifo_io_deq_10),
.io_deq_11(isWrFifo_io_deq_11),
.io_deq_12(isWrFifo_io_deq_12),
.io_deq_13(isWrFifo_io_deq_13),
.io_deq_14(isWrFifo_io_deq_14),
.io_deq_15(isWrFifo_io_deq_15),
.io_deqVld(isWrFifo_io_deqVld),
.io_empty(isWrFifo_io_empty),
.io_forceTag_ready(isWrFifo_io_forceTag_ready),
.io_forceTag_valid(isWrFifo_io_forceTag_valid),
.io_forceTag_bits(isWrFifo_io_forceTag_bits),
.io_tag(isWrFifo_io_tag),
.io_config_chainWrite(isWrFifo_io_config_chainWrite),
.io_config_chainRead(isWrFifo_io_config_chainRead)
);
FIFOArbiter_2 sizeFifo (
.clock(sizeFifo_clock),
.reset(sizeFifo_reset),
.io_deq_0(sizeFifo_io_deq_0),
.io_deq_1(sizeFifo_io_deq_1),
.io_deq_2(sizeFifo_io_deq_2),
.io_deq_3(sizeFifo_io_deq_3),
.io_deq_4(sizeFifo_io_deq_4),
.io_deq_5(sizeFifo_io_deq_5),
.io_deq_6(sizeFifo_io_deq_6),
.io_deq_7(sizeFifo_io_deq_7),
.io_deq_8(sizeFifo_io_deq_8),
.io_deq_9(sizeFifo_io_deq_9),
.io_deq_10(sizeFifo_io_deq_10),
.io_deq_11(sizeFifo_io_deq_11),
.io_deq_12(sizeFifo_io_deq_12),
.io_deq_13(sizeFifo_io_deq_13),
.io_deq_14(sizeFifo_io_deq_14),
.io_deq_15(sizeFifo_io_deq_15),
.io_deqVld(sizeFifo_io_deqVld),
.io_empty(sizeFifo_io_empty),
.io_forceTag_ready(sizeFifo_io_forceTag_ready),
.io_forceTag_valid(sizeFifo_io_forceTag_valid),
.io_forceTag_bits(sizeFifo_io_forceTag_bits),
.io_tag(sizeFifo_io_tag),
.io_config_chainWrite(sizeFifo_io_config_chainWrite),
.io_config_chainRead(sizeFifo_io_config_chainRead)
);
FIFOArbiterWidthConvert wdataFifo (
.clock(wdataFifo_clock),
.reset(wdataFifo_reset),
.io_deq_0(wdataFifo_io_deq_0),
.io_deq_1(wdataFifo_io_deq_1),
.io_deq_2(wdataFifo_io_deq_2),
.io_deq_3(wdataFifo_io_deq_3),
.io_deq_4(wdataFifo_io_deq_4),
.io_deq_5(wdataFifo_io_deq_5),
.io_deq_6(wdataFifo_io_deq_6),
.io_deq_7(wdataFifo_io_deq_7),
.io_deq_8(wdataFifo_io_deq_8),
.io_deq_9(wdataFifo_io_deq_9),
.io_deq_10(wdataFifo_io_deq_10),
.io_deq_11(wdataFifo_io_deq_11),
.io_deq_12(wdataFifo_io_deq_12),
.io_deq_13(wdataFifo_io_deq_13),
.io_deq_14(wdataFifo_io_deq_14),
.io_deq_15(wdataFifo_io_deq_15),
.io_deqVld(wdataFifo_io_deqVld),
.io_empty(wdataFifo_io_empty),
.io_forceTag_ready(wdataFifo_io_forceTag_ready),
.io_forceTag_valid(wdataFifo_io_forceTag_valid),
.io_forceTag_bits(wdataFifo_io_forceTag_bits),
.io_tag(wdataFifo_io_tag)
);
SRFF_sp wrPhase (
.clock(wrPhase_clock),
.reset(wrPhase_reset),
.io_input_set(wrPhase_io_input_set),
.io_input_reset(wrPhase_io_input_reset),
.io_input_asyn_reset(wrPhase_io_input_asyn_reset),
.io_output_data(wrPhase_io_output_data)
);
FF_2 issuedFF (
.clock(issuedFF_clock),
.reset(issuedFF_reset),
.io_in(issuedFF_io_in),
.io_init(issuedFF_io_init),
.io_out(issuedFF_io_out),
.io_enable(issuedFF_io_enable)
);
Counter burstCounter (
.clock(burstCounter_clock),
.reset(burstCounter_reset),
.io_max(burstCounter_io_max),
.io_stride(burstCounter_io_stride),
.io_out(burstCounter_io_out),
.io_next(burstCounter_io_next),
.io_reset(burstCounter_io_reset),
.io_enable(burstCounter_io_enable),
.io_saturate(burstCounter_io_saturate),
.io_done(burstCounter_io_done)
);
Counter_1 burstTagCounter (
.clock(burstTagCounter_clock),
.reset(burstTagCounter_reset),
.io_max(burstTagCounter_io_max),
.io_stride(burstTagCounter_io_stride),
.io_out(burstTagCounter_io_out),
.io_next(burstTagCounter_io_next),
.io_reset(burstTagCounter_io_reset),
.io_enable(burstTagCounter_io_enable),
.io_saturate(burstTagCounter_io_saturate),
.io_done(burstTagCounter_io_done)
);
assign io_dram_cmd_valid = _T_173;
assign io_dram_cmd_bits_addr = _T_160;
assign io_dram_cmd_bits_isWr = isWrFifo_io_deq_0;
assign io_dram_cmd_bits_tag = _T_161;
assign io_dram_cmd_bits_streamId = {{31'd0}, tagOut_streamTag};
assign io_dram_cmd_bits_wdata_0 = wdataFifo_io_deq_0;
assign io_dram_cmd_bits_wdata_1 = wdataFifo_io_deq_1;
assign io_dram_cmd_bits_wdata_2 = wdataFifo_io_deq_2;
assign io_dram_cmd_bits_wdata_3 = wdataFifo_io_deq_3;
assign io_dram_cmd_bits_wdata_4 = wdataFifo_io_deq_4;
assign io_dram_cmd_bits_wdata_5 = wdataFifo_io_deq_5;
assign io_dram_cmd_bits_wdata_6 = wdataFifo_io_deq_6;
assign io_dram_cmd_bits_wdata_7 = wdataFifo_io_deq_7;
assign io_dram_cmd_bits_wdata_8 = wdataFifo_io_deq_8;
assign io_dram_cmd_bits_wdata_9 = wdataFifo_io_deq_9;
assign io_dram_cmd_bits_wdata_10 = wdataFifo_io_deq_10;
assign io_dram_cmd_bits_wdata_11 = wdataFifo_io_deq_11;
assign io_dram_cmd_bits_wdata_12 = wdataFifo_io_deq_12;
assign io_dram_cmd_bits_wdata_13 = wdataFifo_io_deq_13;
assign io_dram_cmd_bits_wdata_14 = wdataFifo_io_deq_14;
assign io_dram_cmd_bits_wdata_15 = wdataFifo_io_deq_15;
assign io_dram_resp_ready = 1'h1;
assign addrFifo_clock = clock;
assign addrFifo_reset = reset;
assign addrFifo_io_deqVld = burstCounter_io_done;
assign addrFifo_io_forceTag_valid = 1'h0;
assign addrFifo_io_forceTag_bits = _GEN_2;
assign addrFifo_io_config_chainWrite = addrFifoConfig_chainWrite;
assign addrFifo_io_config_chainRead = addrFifoConfig_chainRead;
assign addrFifoConfig_chainWrite = _T_84;
assign addrFifoConfig_chainRead = 1'h1;
assign _T_84 = ~ io_config_scatterGather;
assign burstAddrs_0 = addrFifo_io_deq_0[63:6];
assign isWrFifo_clock = clock;
assign isWrFifo_reset = reset;
assign isWrFifo_io_deqVld = burstCounter_io_done;
assign isWrFifo_io_forceTag_valid = 1'h0;
assign isWrFifo_io_forceTag_bits = _GEN_3;
assign isWrFifo_io_config_chainWrite = isWrFifoConfig_chainWrite;
assign isWrFifo_io_config_chainRead = isWrFifoConfig_chainRead;
assign isWrFifoConfig_chainWrite = 1'h1;
assign isWrFifoConfig_chainRead = 1'h1;
assign sizeFifo_clock = clock;
assign sizeFifo_reset = reset;
assign sizeFifo_io_deqVld = burstCounter_io_done;
assign sizeFifo_io_forceTag_valid = 1'h0;
assign sizeFifo_io_forceTag_bits = _GEN_4;
assign sizeFifo_io_config_chainWrite = sizeFifoConfig_chainWrite;
assign sizeFifo_io_config_chainRead = sizeFifoConfig_chainRead;
assign sizeFifoConfig_chainWrite = 1'h1;
assign sizeFifoConfig_chainRead = 1'h1;
assign _T_102 = sizeFifo_io_deq_0[31:6];
assign _T_103 = sizeFifo_io_deq_0[5:0];
assign _T_105 = _T_103 != 6'h0;
assign _GEN_0 = {{25'd0}, _T_105};
assign _T_106 = _T_102 + _GEN_0;
assign sizeInBursts = _T_106[25:0];
assign wdataFifo_clock = clock;
assign wdataFifo_reset = reset;
assign wdataFifo_io_deqVld = _T_150;
assign wdataFifo_io_forceTag_valid = 1'h1;
assign wdataFifo_io_forceTag_bits = _T_125;
assign wrPhase_clock = clock;
assign wrPhase_reset = reset;
assign wrPhase_io_input_set = _T_163;
assign wrPhase_io_input_reset = _T_166;
assign wrPhase_io_input_asyn_reset = _GEN_5;
assign _T_107 = ~ sizeFifo_io_empty;
assign _T_108 = ~ isWrFifo_io_empty;
assign _T_109 = isWrFifo_io_deq_0;
assign _T_110 = _T_108 & _T_109;
assign _T_111 = wrPhase_io_output_data | _T_110;
assign _T_112 = ~ wdataFifo_io_empty;
assign _T_114 = _T_111 ? _T_112 : 1'h1;
assign burstVld = _T_107 & _T_114;
assign issued = 1'h0;
assign issuedFF_clock = clock;
assign issuedFF_reset = reset;
assign issuedFF_io_in = _T_119;
assign issuedFF_io_init = 1'h0;
assign issuedFF_io_enable = 1'h1;
assign _T_117 = ~ io_dram_resp_valid;
assign _T_118 = burstVld & io_dram_cmd_ready;
assign _T_119 = issued ? _T_117 : _T_118;
assign _T_123 = addrFifo_io_tag - 1'h0;
assign _T_124 = $unsigned(_T_123);
assign _T_125 = _T_124[0:0];
assign burstCounter_clock = clock;
assign burstCounter_reset = reset;
assign burstCounter_io_max = {{6'd0}, _T_129};
assign burstCounter_io_stride = 32'h1;
assign burstCounter_io_reset = 1'h0;
assign burstCounter_io_enable = _T_136;
assign burstCounter_io_saturate = 1'h0;
assign _T_129 = io_config_scatterGather ? 26'h1 : sizeInBursts;
assign _T_132 = ~ addrFifo_io_empty;
assign _T_133 = io_config_scatterGather ? _T_132 : burstVld;
assign _T_134 = _T_133 & io_dram_cmd_ready;
assign _T_135 = ~ issued;
assign _T_136 = _T_134 & _T_135;
assign burstTagCounter_clock = clock;
assign burstTagCounter_reset = reset;
assign burstTagCounter_io_max = 11'h400;
assign burstTagCounter_io_stride = 11'h1;
assign burstTagCounter_io_reset = 1'h0;
assign burstTagCounter_io_enable = _T_136;
assign burstTagCounter_io_saturate = _GEN_6;
assign _T_147 = burstVld & isWrFifo_io_deq_0;
assign _T_148 = _T_147 & io_dram_cmd_ready;
assign _T_150 = _T_148 & _T_135;
assign tagOut_streamTag = addrFifo_io_tag;
assign tagOut_burstTag = _T_156[30:0];
assign _T_156 = io_config_scatterGather ? burstAddrs_0 : {{47'd0}, burstTagCounter_io_out};
assign _GEN_1 = {{26'd0}, burstCounter_io_out};
assign _T_157 = burstAddrs_0 + _GEN_1;
assign _T_158 = _T_157[57:0];
assign _T_160 = {_T_158,6'h0};
assign _T_161 = {tagOut_streamTag,tagOut_burstTag};
assign _T_163 = _T_108 & isWrFifo_io_deq_0;
assign _T_173 = burstVld & _T_135;
assign issuedTag = 32'h0;
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifndef verilator
#0.002 begin end
`endif
`ifdef RANDOMIZE_REG_INIT
_GEN_7 = {1{$random}};
_T_166 = _GEN_7[0:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_GEN_8 = {1{$random}};
_GEN_2 = _GEN_8[0:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_GEN_9 = {1{$random}};
_GEN_3 = _GEN_9[0:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_GEN_10 = {1{$random}};
_GEN_4 = _GEN_10[0:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_GEN_11 = {1{$random}};
_GEN_5 = _GEN_11[0:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_GEN_12 = {1{$random}};
_GEN_6 = _GEN_12[0:0];
`endif
end
`endif
always @(posedge clock) begin
if (reset) begin
_T_166 <= 1'h0;
end else begin
_T_166 <= burstVld;
end
end
endmodule
module Fringe(
input clock,
input reset,
input io_raddr,
input io_wen,
input io_waddr,
input [63:0] io_wdata,
output [63:0] io_rdata,
output io_enable,
input io_done,
input io_dram_cmd_ready,
output io_dram_cmd_valid,
output [63:0] io_dram_cmd_bits_addr,
output io_dram_cmd_bits_isWr,
output [31:0] io_dram_cmd_bits_tag,
output [31:0] io_dram_cmd_bits_streamId,
output [31:0] io_dram_cmd_bits_wdata_0,
output [31:0] io_dram_cmd_bits_wdata_1,
output [31:0] io_dram_cmd_bits_wdata_2,
output [31:0] io_dram_cmd_bits_wdata_3,
output [31:0] io_dram_cmd_bits_wdata_4,
output [31:0] io_dram_cmd_bits_wdata_5,
output [31:0] io_dram_cmd_bits_wdata_6,
output [31:0] io_dram_cmd_bits_wdata_7,
output [31:0] io_dram_cmd_bits_wdata_8,
output [31:0] io_dram_cmd_bits_wdata_9,
output [31:0] io_dram_cmd_bits_wdata_10,
output [31:0] io_dram_cmd_bits_wdata_11,
output [31:0] io_dram_cmd_bits_wdata_12,
output [31:0] io_dram_cmd_bits_wdata_13,
output [31:0] io_dram_cmd_bits_wdata_14,
output [31:0] io_dram_cmd_bits_wdata_15,
output io_dram_resp_ready,
input io_dram_resp_valid,
input [31:0] io_dram_resp_bits_rdata_0,
input [31:0] io_dram_resp_bits_rdata_1,
input [31:0] io_dram_resp_bits_rdata_2,
input [31:0] io_dram_resp_bits_rdata_3,
input [31:0] io_dram_resp_bits_rdata_4,
input [31:0] io_dram_resp_bits_rdata_5,
input [31:0] io_dram_resp_bits_rdata_6,
input [31:0] io_dram_resp_bits_rdata_7,
input [31:0] io_dram_resp_bits_rdata_8,
input [31:0] io_dram_resp_bits_rdata_9,
input [31:0] io_dram_resp_bits_rdata_10,
input [31:0] io_dram_resp_bits_rdata_11,
input [31:0] io_dram_resp_bits_rdata_12,
input [31:0] io_dram_resp_bits_rdata_13,
input [31:0] io_dram_resp_bits_rdata_14,
input [31:0] io_dram_resp_bits_rdata_15,
input [31:0] io_dram_resp_bits_tag,
input [31:0] io_dram_resp_bits_streamId,
input io_genericStreamOutTop_ready,
output io_genericStreamOutTop_valid,
output [31:0] io_genericStreamOutTop_bits_data,
output [31:0] io_genericStreamOutTop_bits_tag,
output io_genericStreamOutTop_bits_last,
output io_genericStreamInTop_ready,
input io_genericStreamInTop_valid,
input [31:0] io_genericStreamInTop_bits_data,
input [31:0] io_genericStreamInTop_bits_tag,
input io_genericStreamInTop_bits_last
);
wire regs_clock;
wire regs_reset;
wire regs_io_raddr;
wire regs_io_wen;
wire regs_io_waddr;
wire [63:0] regs_io_wdata;
wire [63:0] regs_io_rdata;
wire [63:0] regs_io_argIns_0;
wire [63:0] regs_io_argIns_1;
wire regs_io_argOuts_0_ready;
wire regs_io_argOuts_0_valid;
wire [63:0] regs_io_argOuts_0_bits;
wire _T_171;
wire _T_172;
wire _T_173;
wire _T_174;
wire depulser_clock;
wire depulser_reset;
wire depulser_io_in;
wire depulser_io_rst;
wire depulser_io_out;
wire [63:0] _T_175;
wire status_ready;
wire status_valid;
wire [63:0] status_bits;
wire [63:0] _GEN_0;
wire [63:0] _T_190;
wire mag_clock;
wire mag_reset;
wire mag_io_dram_cmd_ready;
wire mag_io_dram_cmd_valid;
wire [63:0] mag_io_dram_cmd_bits_addr;
wire mag_io_dram_cmd_bits_isWr;
wire [31:0] mag_io_dram_cmd_bits_tag;
wire [31:0] mag_io_dram_cmd_bits_streamId;
wire [31:0] mag_io_dram_cmd_bits_wdata_0;
wire [31:0] mag_io_dram_cmd_bits_wdata_1;
wire [31:0] mag_io_dram_cmd_bits_wdata_2;
wire [31:0] mag_io_dram_cmd_bits_wdata_3;
wire [31:0] mag_io_dram_cmd_bits_wdata_4;
wire [31:0] mag_io_dram_cmd_bits_wdata_5;
wire [31:0] mag_io_dram_cmd_bits_wdata_6;
wire [31:0] mag_io_dram_cmd_bits_wdata_7;
wire [31:0] mag_io_dram_cmd_bits_wdata_8;
wire [31:0] mag_io_dram_cmd_bits_wdata_9;
wire [31:0] mag_io_dram_cmd_bits_wdata_10;
wire [31:0] mag_io_dram_cmd_bits_wdata_11;
wire [31:0] mag_io_dram_cmd_bits_wdata_12;
wire [31:0] mag_io_dram_cmd_bits_wdata_13;
wire [31:0] mag_io_dram_cmd_bits_wdata_14;
wire [31:0] mag_io_dram_cmd_bits_wdata_15;
wire mag_io_dram_resp_ready;
wire mag_io_dram_resp_valid;
wire [31:0] mag_io_dram_resp_bits_rdata_0;
wire [31:0] mag_io_dram_resp_bits_rdata_1;
wire [31:0] mag_io_dram_resp_bits_rdata_2;
wire [31:0] mag_io_dram_resp_bits_rdata_3;
wire [31:0] mag_io_dram_resp_bits_rdata_4;
wire [31:0] mag_io_dram_resp_bits_rdata_5;
wire [31:0] mag_io_dram_resp_bits_rdata_6;
wire [31:0] mag_io_dram_resp_bits_rdata_7;
wire [31:0] mag_io_dram_resp_bits_rdata_8;
wire [31:0] mag_io_dram_resp_bits_rdata_9;
wire [31:0] mag_io_dram_resp_bits_rdata_10;
wire [31:0] mag_io_dram_resp_bits_rdata_11;
wire [31:0] mag_io_dram_resp_bits_rdata_12;
wire [31:0] mag_io_dram_resp_bits_rdata_13;
wire [31:0] mag_io_dram_resp_bits_rdata_14;
wire [31:0] mag_io_dram_resp_bits_rdata_15;
wire [31:0] mag_io_dram_resp_bits_tag;
wire [31:0] mag_io_dram_resp_bits_streamId;
wire mag_io_config_scatterGather;
wire magConfig_scatterGather;
reg _GEN_1;
reg [31:0] _GEN_7;
reg [31:0] _GEN_2;
reg [31:0] _GEN_8;
reg [31:0] _GEN_3;
reg [31:0] _GEN_9;
reg _GEN_4;
reg [31:0] _GEN_10;
reg _GEN_5;
reg [31:0] _GEN_11;
reg _GEN_6;
reg [31:0] _GEN_12;
RegFile regs (
.clock(regs_clock),
.reset(regs_reset),
.io_raddr(regs_io_raddr),
.io_wen(regs_io_wen),
.io_waddr(regs_io_waddr),
.io_wdata(regs_io_wdata),
.io_rdata(regs_io_rdata),
.io_argIns_0(regs_io_argIns_0),
.io_argIns_1(regs_io_argIns_1),
.io_argOuts_0_ready(regs_io_argOuts_0_ready),
.io_argOuts_0_valid(regs_io_argOuts_0_valid),
.io_argOuts_0_bits(regs_io_argOuts_0_bits)
);
Depulser depulser (
.clock(depulser_clock),
.reset(depulser_reset),
.io_in(depulser_io_in),
.io_rst(depulser_io_rst),
.io_out(depulser_io_out)
);
MAGCore mag (
.clock(mag_clock),
.reset(mag_reset),
.io_dram_cmd_ready(mag_io_dram_cmd_ready),
.io_dram_cmd_valid(mag_io_dram_cmd_valid),
.io_dram_cmd_bits_addr(mag_io_dram_cmd_bits_addr),
.io_dram_cmd_bits_isWr(mag_io_dram_cmd_bits_isWr),
.io_dram_cmd_bits_tag(mag_io_dram_cmd_bits_tag),
.io_dram_cmd_bits_streamId(mag_io_dram_cmd_bits_streamId),
.io_dram_cmd_bits_wdata_0(mag_io_dram_cmd_bits_wdata_0),
.io_dram_cmd_bits_wdata_1(mag_io_dram_cmd_bits_wdata_1),
.io_dram_cmd_bits_wdata_2(mag_io_dram_cmd_bits_wdata_2),
.io_dram_cmd_bits_wdata_3(mag_io_dram_cmd_bits_wdata_3),
.io_dram_cmd_bits_wdata_4(mag_io_dram_cmd_bits_wdata_4),
.io_dram_cmd_bits_wdata_5(mag_io_dram_cmd_bits_wdata_5),
.io_dram_cmd_bits_wdata_6(mag_io_dram_cmd_bits_wdata_6),
.io_dram_cmd_bits_wdata_7(mag_io_dram_cmd_bits_wdata_7),
.io_dram_cmd_bits_wdata_8(mag_io_dram_cmd_bits_wdata_8),
.io_dram_cmd_bits_wdata_9(mag_io_dram_cmd_bits_wdata_9),
.io_dram_cmd_bits_wdata_10(mag_io_dram_cmd_bits_wdata_10),
.io_dram_cmd_bits_wdata_11(mag_io_dram_cmd_bits_wdata_11),
.io_dram_cmd_bits_wdata_12(mag_io_dram_cmd_bits_wdata_12),
.io_dram_cmd_bits_wdata_13(mag_io_dram_cmd_bits_wdata_13),
.io_dram_cmd_bits_wdata_14(mag_io_dram_cmd_bits_wdata_14),
.io_dram_cmd_bits_wdata_15(mag_io_dram_cmd_bits_wdata_15),
.io_dram_resp_ready(mag_io_dram_resp_ready),
.io_dram_resp_valid(mag_io_dram_resp_valid),
.io_dram_resp_bits_rdata_0(mag_io_dram_resp_bits_rdata_0),
.io_dram_resp_bits_rdata_1(mag_io_dram_resp_bits_rdata_1),
.io_dram_resp_bits_rdata_2(mag_io_dram_resp_bits_rdata_2),
.io_dram_resp_bits_rdata_3(mag_io_dram_resp_bits_rdata_3),
.io_dram_resp_bits_rdata_4(mag_io_dram_resp_bits_rdata_4),
.io_dram_resp_bits_rdata_5(mag_io_dram_resp_bits_rdata_5),
.io_dram_resp_bits_rdata_6(mag_io_dram_resp_bits_rdata_6),
.io_dram_resp_bits_rdata_7(mag_io_dram_resp_bits_rdata_7),
.io_dram_resp_bits_rdata_8(mag_io_dram_resp_bits_rdata_8),
.io_dram_resp_bits_rdata_9(mag_io_dram_resp_bits_rdata_9),
.io_dram_resp_bits_rdata_10(mag_io_dram_resp_bits_rdata_10),
.io_dram_resp_bits_rdata_11(mag_io_dram_resp_bits_rdata_11),
.io_dram_resp_bits_rdata_12(mag_io_dram_resp_bits_rdata_12),
.io_dram_resp_bits_rdata_13(mag_io_dram_resp_bits_rdata_13),
.io_dram_resp_bits_rdata_14(mag_io_dram_resp_bits_rdata_14),
.io_dram_resp_bits_rdata_15(mag_io_dram_resp_bits_rdata_15),
.io_dram_resp_bits_tag(mag_io_dram_resp_bits_tag),
.io_dram_resp_bits_streamId(mag_io_dram_resp_bits_streamId),
.io_config_scatterGather(mag_io_config_scatterGather)
);
assign io_rdata = regs_io_rdata;
assign io_enable = _T_174;
assign io_dram_cmd_valid = mag_io_dram_cmd_valid;
assign io_dram_cmd_bits_addr = mag_io_dram_cmd_bits_addr;
assign io_dram_cmd_bits_isWr = mag_io_dram_cmd_bits_isWr;
assign io_dram_cmd_bits_tag = mag_io_dram_cmd_bits_tag;
assign io_dram_cmd_bits_streamId = mag_io_dram_cmd_bits_streamId;
assign io_dram_cmd_bits_wdata_0 = mag_io_dram_cmd_bits_wdata_0;
assign io_dram_cmd_bits_wdata_1 = mag_io_dram_cmd_bits_wdata_1;
assign io_dram_cmd_bits_wdata_2 = mag_io_dram_cmd_bits_wdata_2;
assign io_dram_cmd_bits_wdata_3 = mag_io_dram_cmd_bits_wdata_3;
assign io_dram_cmd_bits_wdata_4 = mag_io_dram_cmd_bits_wdata_4;
assign io_dram_cmd_bits_wdata_5 = mag_io_dram_cmd_bits_wdata_5;
assign io_dram_cmd_bits_wdata_6 = mag_io_dram_cmd_bits_wdata_6;
assign io_dram_cmd_bits_wdata_7 = mag_io_dram_cmd_bits_wdata_7;
assign io_dram_cmd_bits_wdata_8 = mag_io_dram_cmd_bits_wdata_8;
assign io_dram_cmd_bits_wdata_9 = mag_io_dram_cmd_bits_wdata_9;
assign io_dram_cmd_bits_wdata_10 = mag_io_dram_cmd_bits_wdata_10;
assign io_dram_cmd_bits_wdata_11 = mag_io_dram_cmd_bits_wdata_11;
assign io_dram_cmd_bits_wdata_12 = mag_io_dram_cmd_bits_wdata_12;
assign io_dram_cmd_bits_wdata_13 = mag_io_dram_cmd_bits_wdata_13;
assign io_dram_cmd_bits_wdata_14 = mag_io_dram_cmd_bits_wdata_14;
assign io_dram_cmd_bits_wdata_15 = mag_io_dram_cmd_bits_wdata_15;
assign io_dram_resp_ready = mag_io_dram_resp_ready;
assign io_genericStreamOutTop_valid = _GEN_1;
assign io_genericStreamOutTop_bits_data = _GEN_2;
assign io_genericStreamOutTop_bits_tag = _GEN_3;
assign io_genericStreamOutTop_bits_last = _GEN_4;
assign io_genericStreamInTop_ready = _GEN_5;
assign regs_clock = clock;
assign regs_reset = reset;
assign regs_io_raddr = io_raddr;
assign regs_io_wen = io_wen;
assign regs_io_waddr = io_waddr;
assign regs_io_wdata = io_wdata;
assign regs_io_argOuts_0_valid = status_valid;
assign regs_io_argOuts_0_bits = status_bits;
assign _T_171 = regs_io_argIns_0[0];
assign _T_172 = regs_io_argIns_1[0];
assign _T_173 = ~ _T_172;
assign _T_174 = _T_171 & _T_173;
assign depulser_clock = clock;
assign depulser_reset = reset;
assign depulser_io_in = io_done;
assign depulser_io_rst = _T_175[0];
assign _T_175 = ~ regs_io_argIns_0;
assign status_ready = _GEN_6;
assign status_valid = depulser_io_out;
assign status_bits = _T_190;
assign _GEN_0 = {{63'd0}, depulser_io_out};
assign _T_190 = regs_io_argIns_0 & _GEN_0;
assign mag_clock = clock;
assign mag_reset = reset;
assign mag_io_dram_cmd_ready = io_dram_cmd_ready;
assign mag_io_dram_resp_valid = io_dram_resp_valid;
assign mag_io_dram_resp_bits_rdata_0 = io_dram_resp_bits_rdata_0;
assign mag_io_dram_resp_bits_rdata_1 = io_dram_resp_bits_rdata_1;
assign mag_io_dram_resp_bits_rdata_2 = io_dram_resp_bits_rdata_2;
assign mag_io_dram_resp_bits_rdata_3 = io_dram_resp_bits_rdata_3;
assign mag_io_dram_resp_bits_rdata_4 = io_dram_resp_bits_rdata_4;
assign mag_io_dram_resp_bits_rdata_5 = io_dram_resp_bits_rdata_5;
assign mag_io_dram_resp_bits_rdata_6 = io_dram_resp_bits_rdata_6;
assign mag_io_dram_resp_bits_rdata_7 = io_dram_resp_bits_rdata_7;
assign mag_io_dram_resp_bits_rdata_8 = io_dram_resp_bits_rdata_8;
assign mag_io_dram_resp_bits_rdata_9 = io_dram_resp_bits_rdata_9;
assign mag_io_dram_resp_bits_rdata_10 = io_dram_resp_bits_rdata_10;
assign mag_io_dram_resp_bits_rdata_11 = io_dram_resp_bits_rdata_11;
assign mag_io_dram_resp_bits_rdata_12 = io_dram_resp_bits_rdata_12;
assign mag_io_dram_resp_bits_rdata_13 = io_dram_resp_bits_rdata_13;
assign mag_io_dram_resp_bits_rdata_14 = io_dram_resp_bits_rdata_14;
assign mag_io_dram_resp_bits_rdata_15 = io_dram_resp_bits_rdata_15;
assign mag_io_dram_resp_bits_tag = io_dram_resp_bits_tag;
assign mag_io_dram_resp_bits_streamId = io_dram_resp_bits_streamId;
assign mag_io_config_scatterGather = magConfig_scatterGather;
assign magConfig_scatterGather = 1'h0;
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifndef verilator
#0.002 begin end
`endif
`ifdef RANDOMIZE_REG_INIT
_GEN_7 = {1{$random}};
_GEN_1 = _GEN_7[0:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_GEN_8 = {1{$random}};
_GEN_2 = _GEN_8[31:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_GEN_9 = {1{$random}};
_GEN_3 = _GEN_9[31:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_GEN_10 = {1{$random}};
_GEN_4 = _GEN_10[0:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_GEN_11 = {1{$random}};
_GEN_5 = _GEN_11[0:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_GEN_12 = {1{$random}};
_GEN_6 = _GEN_12[0:0];
`endif
end
`endif
endmodule
module FringeDE1SoC(
input clock,
input reset,
output [31:0] io_S_AVALON_readdata,
input [15:0] io_S_AVALON_address,
input io_S_AVALON_chipselect,
input io_S_AVALON_write_n,
input [31:0] io_S_AVALON_writedata,
output io_enable,
input io_done
);
wire fringeCommon_clock;
wire fringeCommon_reset;
wire fringeCommon_io_raddr;
wire fringeCommon_io_wen;
wire fringeCommon_io_waddr;
wire [63:0] fringeCommon_io_wdata;
wire [63:0] fringeCommon_io_rdata;
wire fringeCommon_io_enable;
wire fringeCommon_io_done;
wire fringeCommon_io_dram_cmd_ready;
wire fringeCommon_io_dram_cmd_valid;
wire [63:0] fringeCommon_io_dram_cmd_bits_addr;
wire fringeCommon_io_dram_cmd_bits_isWr;
wire [31:0] fringeCommon_io_dram_cmd_bits_tag;
wire [31:0] fringeCommon_io_dram_cmd_bits_streamId;
wire [31:0] fringeCommon_io_dram_cmd_bits_wdata_0;
wire [31:0] fringeCommon_io_dram_cmd_bits_wdata_1;
wire [31:0] fringeCommon_io_dram_cmd_bits_wdata_2;
wire [31:0] fringeCommon_io_dram_cmd_bits_wdata_3;
wire [31:0] fringeCommon_io_dram_cmd_bits_wdata_4;
wire [31:0] fringeCommon_io_dram_cmd_bits_wdata_5;
wire [31:0] fringeCommon_io_dram_cmd_bits_wdata_6;
wire [31:0] fringeCommon_io_dram_cmd_bits_wdata_7;
wire [31:0] fringeCommon_io_dram_cmd_bits_wdata_8;
wire [31:0] fringeCommon_io_dram_cmd_bits_wdata_9;
wire [31:0] fringeCommon_io_dram_cmd_bits_wdata_10;
wire [31:0] fringeCommon_io_dram_cmd_bits_wdata_11;
wire [31:0] fringeCommon_io_dram_cmd_bits_wdata_12;
wire [31:0] fringeCommon_io_dram_cmd_bits_wdata_13;
wire [31:0] fringeCommon_io_dram_cmd_bits_wdata_14;
wire [31:0] fringeCommon_io_dram_cmd_bits_wdata_15;
wire fringeCommon_io_dram_resp_ready;
wire fringeCommon_io_dram_resp_valid;
wire [31:0] fringeCommon_io_dram_resp_bits_rdata_0;
wire [31:0] fringeCommon_io_dram_resp_bits_rdata_1;
wire [31:0] fringeCommon_io_dram_resp_bits_rdata_2;
wire [31:0] fringeCommon_io_dram_resp_bits_rdata_3;
wire [31:0] fringeCommon_io_dram_resp_bits_rdata_4;
wire [31:0] fringeCommon_io_dram_resp_bits_rdata_5;
wire [31:0] fringeCommon_io_dram_resp_bits_rdata_6;
wire [31:0] fringeCommon_io_dram_resp_bits_rdata_7;
wire [31:0] fringeCommon_io_dram_resp_bits_rdata_8;
wire [31:0] fringeCommon_io_dram_resp_bits_rdata_9;
wire [31:0] fringeCommon_io_dram_resp_bits_rdata_10;
wire [31:0] fringeCommon_io_dram_resp_bits_rdata_11;
wire [31:0] fringeCommon_io_dram_resp_bits_rdata_12;
wire [31:0] fringeCommon_io_dram_resp_bits_rdata_13;
wire [31:0] fringeCommon_io_dram_resp_bits_rdata_14;
wire [31:0] fringeCommon_io_dram_resp_bits_rdata_15;
wire [31:0] fringeCommon_io_dram_resp_bits_tag;
wire [31:0] fringeCommon_io_dram_resp_bits_streamId;
wire fringeCommon_io_genericStreamOutTop_ready;
wire fringeCommon_io_genericStreamOutTop_valid;
wire [31:0] fringeCommon_io_genericStreamOutTop_bits_data;
wire [31:0] fringeCommon_io_genericStreamOutTop_bits_tag;
wire fringeCommon_io_genericStreamOutTop_bits_last;
wire fringeCommon_io_genericStreamInTop_ready;
wire fringeCommon_io_genericStreamInTop_valid;
wire [31:0] fringeCommon_io_genericStreamInTop_bits_data;
wire [31:0] fringeCommon_io_genericStreamInTop_bits_tag;
wire fringeCommon_io_genericStreamInTop_bits_last;
wire _T_46;
wire _T_47;
reg _GEN_0;
reg [31:0] _GEN_25;
reg _GEN_1;
reg [31:0] _GEN_26;
reg [31:0] _GEN_2;
reg [31:0] _GEN_27;
reg [31:0] _GEN_3;
reg [31:0] _GEN_28;
reg [31:0] _GEN_4;
reg [31:0] _GEN_29;
reg [31:0] _GEN_5;
reg [31:0] _GEN_30;
reg [31:0] _GEN_6;
reg [31:0] _GEN_31;
reg [31:0] _GEN_7;
reg [31:0] _GEN_32;
reg [31:0] _GEN_8;
reg [31:0] _GEN_33;
reg [31:0] _GEN_9;
reg [31:0] _GEN_34;
reg [31:0] _GEN_10;
reg [31:0] _GEN_35;
reg [31:0] _GEN_11;
reg [31:0] _GEN_36;
reg [31:0] _GEN_12;
reg [31:0] _GEN_37;
reg [31:0] _GEN_13;
reg [31:0] _GEN_38;
reg [31:0] _GEN_14;
reg [31:0] _GEN_39;
reg [31:0] _GEN_15;
reg [31:0] _GEN_40;
reg [31:0] _GEN_16;
reg [31:0] _GEN_41;
reg [31:0] _GEN_17;
reg [31:0] _GEN_42;
reg [31:0] _GEN_18;
reg [31:0] _GEN_43;
reg [31:0] _GEN_19;
reg [31:0] _GEN_44;
reg _GEN_20;
reg [31:0] _GEN_45;
reg _GEN_21;
reg [31:0] _GEN_46;
reg [31:0] _GEN_22;
reg [31:0] _GEN_47;
reg [31:0] _GEN_23;
reg [31:0] _GEN_48;
reg _GEN_24;
reg [31:0] _GEN_49;
Fringe fringeCommon (
.clock(fringeCommon_clock),
.reset(fringeCommon_reset),
.io_raddr(fringeCommon_io_raddr),
.io_wen(fringeCommon_io_wen),
.io_waddr(fringeCommon_io_waddr),
.io_wdata(fringeCommon_io_wdata),
.io_rdata(fringeCommon_io_rdata),
.io_enable(fringeCommon_io_enable),
.io_done(fringeCommon_io_done),
.io_dram_cmd_ready(fringeCommon_io_dram_cmd_ready),
.io_dram_cmd_valid(fringeCommon_io_dram_cmd_valid),
.io_dram_cmd_bits_addr(fringeCommon_io_dram_cmd_bits_addr),
.io_dram_cmd_bits_isWr(fringeCommon_io_dram_cmd_bits_isWr),
.io_dram_cmd_bits_tag(fringeCommon_io_dram_cmd_bits_tag),
.io_dram_cmd_bits_streamId(fringeCommon_io_dram_cmd_bits_streamId),
.io_dram_cmd_bits_wdata_0(fringeCommon_io_dram_cmd_bits_wdata_0),
.io_dram_cmd_bits_wdata_1(fringeCommon_io_dram_cmd_bits_wdata_1),
.io_dram_cmd_bits_wdata_2(fringeCommon_io_dram_cmd_bits_wdata_2),
.io_dram_cmd_bits_wdata_3(fringeCommon_io_dram_cmd_bits_wdata_3),
.io_dram_cmd_bits_wdata_4(fringeCommon_io_dram_cmd_bits_wdata_4),
.io_dram_cmd_bits_wdata_5(fringeCommon_io_dram_cmd_bits_wdata_5),
.io_dram_cmd_bits_wdata_6(fringeCommon_io_dram_cmd_bits_wdata_6),
.io_dram_cmd_bits_wdata_7(fringeCommon_io_dram_cmd_bits_wdata_7),
.io_dram_cmd_bits_wdata_8(fringeCommon_io_dram_cmd_bits_wdata_8),
.io_dram_cmd_bits_wdata_9(fringeCommon_io_dram_cmd_bits_wdata_9),
.io_dram_cmd_bits_wdata_10(fringeCommon_io_dram_cmd_bits_wdata_10),
.io_dram_cmd_bits_wdata_11(fringeCommon_io_dram_cmd_bits_wdata_11),
.io_dram_cmd_bits_wdata_12(fringeCommon_io_dram_cmd_bits_wdata_12),
.io_dram_cmd_bits_wdata_13(fringeCommon_io_dram_cmd_bits_wdata_13),
.io_dram_cmd_bits_wdata_14(fringeCommon_io_dram_cmd_bits_wdata_14),
.io_dram_cmd_bits_wdata_15(fringeCommon_io_dram_cmd_bits_wdata_15),
.io_dram_resp_ready(fringeCommon_io_dram_resp_ready),
.io_dram_resp_valid(fringeCommon_io_dram_resp_valid),
.io_dram_resp_bits_rdata_0(fringeCommon_io_dram_resp_bits_rdata_0),
.io_dram_resp_bits_rdata_1(fringeCommon_io_dram_resp_bits_rdata_1),
.io_dram_resp_bits_rdata_2(fringeCommon_io_dram_resp_bits_rdata_2),
.io_dram_resp_bits_rdata_3(fringeCommon_io_dram_resp_bits_rdata_3),
.io_dram_resp_bits_rdata_4(fringeCommon_io_dram_resp_bits_rdata_4),
.io_dram_resp_bits_rdata_5(fringeCommon_io_dram_resp_bits_rdata_5),
.io_dram_resp_bits_rdata_6(fringeCommon_io_dram_resp_bits_rdata_6),
.io_dram_resp_bits_rdata_7(fringeCommon_io_dram_resp_bits_rdata_7),
.io_dram_resp_bits_rdata_8(fringeCommon_io_dram_resp_bits_rdata_8),
.io_dram_resp_bits_rdata_9(fringeCommon_io_dram_resp_bits_rdata_9),
.io_dram_resp_bits_rdata_10(fringeCommon_io_dram_resp_bits_rdata_10),
.io_dram_resp_bits_rdata_11(fringeCommon_io_dram_resp_bits_rdata_11),
.io_dram_resp_bits_rdata_12(fringeCommon_io_dram_resp_bits_rdata_12),
.io_dram_resp_bits_rdata_13(fringeCommon_io_dram_resp_bits_rdata_13),
.io_dram_resp_bits_rdata_14(fringeCommon_io_dram_resp_bits_rdata_14),
.io_dram_resp_bits_rdata_15(fringeCommon_io_dram_resp_bits_rdata_15),
.io_dram_resp_bits_tag(fringeCommon_io_dram_resp_bits_tag),
.io_dram_resp_bits_streamId(fringeCommon_io_dram_resp_bits_streamId),
.io_genericStreamOutTop_ready(fringeCommon_io_genericStreamOutTop_ready),
.io_genericStreamOutTop_valid(fringeCommon_io_genericStreamOutTop_valid),
.io_genericStreamOutTop_bits_data(fringeCommon_io_genericStreamOutTop_bits_data),
.io_genericStreamOutTop_bits_tag(fringeCommon_io_genericStreamOutTop_bits_tag),
.io_genericStreamOutTop_bits_last(fringeCommon_io_genericStreamOutTop_bits_last),
.io_genericStreamInTop_ready(fringeCommon_io_genericStreamInTop_ready),
.io_genericStreamInTop_valid(fringeCommon_io_genericStreamInTop_valid),
.io_genericStreamInTop_bits_data(fringeCommon_io_genericStreamInTop_bits_data),
.io_genericStreamInTop_bits_tag(fringeCommon_io_genericStreamInTop_bits_tag),
.io_genericStreamInTop_bits_last(fringeCommon_io_genericStreamInTop_bits_last)
);
assign io_S_AVALON_readdata = fringeCommon_io_rdata[31:0];
assign io_enable = fringeCommon_io_enable;
assign fringeCommon_clock = clock;
assign fringeCommon_reset = reset;
assign fringeCommon_io_raddr = io_S_AVALON_address[0];
assign fringeCommon_io_wen = _T_47;
assign fringeCommon_io_waddr = io_S_AVALON_address[0];
assign fringeCommon_io_wdata = {{32'd0}, io_S_AVALON_writedata};
assign fringeCommon_io_done = io_done;
assign fringeCommon_io_dram_cmd_ready = _GEN_0;
assign fringeCommon_io_dram_resp_valid = _GEN_1;
assign fringeCommon_io_dram_resp_bits_rdata_0 = _GEN_2;
assign fringeCommon_io_dram_resp_bits_rdata_1 = _GEN_3;
assign fringeCommon_io_dram_resp_bits_rdata_2 = _GEN_4;
assign fringeCommon_io_dram_resp_bits_rdata_3 = _GEN_5;
assign fringeCommon_io_dram_resp_bits_rdata_4 = _GEN_6;
assign fringeCommon_io_dram_resp_bits_rdata_5 = _GEN_7;
assign fringeCommon_io_dram_resp_bits_rdata_6 = _GEN_8;
assign fringeCommon_io_dram_resp_bits_rdata_7 = _GEN_9;
assign fringeCommon_io_dram_resp_bits_rdata_8 = _GEN_10;
assign fringeCommon_io_dram_resp_bits_rdata_9 = _GEN_11;
assign fringeCommon_io_dram_resp_bits_rdata_10 = _GEN_12;
assign fringeCommon_io_dram_resp_bits_rdata_11 = _GEN_13;
assign fringeCommon_io_dram_resp_bits_rdata_12 = _GEN_14;
assign fringeCommon_io_dram_resp_bits_rdata_13 = _GEN_15;
assign fringeCommon_io_dram_resp_bits_rdata_14 = _GEN_16;
assign fringeCommon_io_dram_resp_bits_rdata_15 = _GEN_17;
assign fringeCommon_io_dram_resp_bits_tag = _GEN_18;
assign fringeCommon_io_dram_resp_bits_streamId = _GEN_19;
assign fringeCommon_io_genericStreamOutTop_ready = _GEN_20;
assign fringeCommon_io_genericStreamInTop_valid = _GEN_21;
assign fringeCommon_io_genericStreamInTop_bits_data = _GEN_22;
assign fringeCommon_io_genericStreamInTop_bits_tag = _GEN_23;
assign fringeCommon_io_genericStreamInTop_bits_last = _GEN_24;
assign _T_46 = ~ io_S_AVALON_write_n;
assign _T_47 = _T_46 & io_S_AVALON_chipselect;
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifndef verilator
#0.002 begin end
`endif
`ifdef RANDOMIZE_REG_INIT
_GEN_25 = {1{$random}};
_GEN_0 = _GEN_25[0:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_GEN_26 = {1{$random}};
_GEN_1 = _GEN_26[0:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_GEN_27 = {1{$random}};
_GEN_2 = _GEN_27[31:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_GEN_28 = {1{$random}};
_GEN_3 = _GEN_28[31:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_GEN_29 = {1{$random}};
_GEN_4 = _GEN_29[31:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_GEN_30 = {1{$random}};
_GEN_5 = _GEN_30[31:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_GEN_31 = {1{$random}};
_GEN_6 = _GEN_31[31:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_GEN_32 = {1{$random}};
_GEN_7 = _GEN_32[31:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_GEN_33 = {1{$random}};
_GEN_8 = _GEN_33[31:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_GEN_34 = {1{$random}};
_GEN_9 = _GEN_34[31:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_GEN_35 = {1{$random}};
_GEN_10 = _GEN_35[31:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_GEN_36 = {1{$random}};
_GEN_11 = _GEN_36[31:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_GEN_37 = {1{$random}};
_GEN_12 = _GEN_37[31:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_GEN_38 = {1{$random}};
_GEN_13 = _GEN_38[31:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_GEN_39 = {1{$random}};
_GEN_14 = _GEN_39[31:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_GEN_40 = {1{$random}};
_GEN_15 = _GEN_40[31:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_GEN_41 = {1{$random}};
_GEN_16 = _GEN_41[31:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_GEN_42 = {1{$random}};
_GEN_17 = _GEN_42[31:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_GEN_43 = {1{$random}};
_GEN_18 = _GEN_43[31:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_GEN_44 = {1{$random}};
_GEN_19 = _GEN_44[31:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_GEN_45 = {1{$random}};
_GEN_20 = _GEN_45[0:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_GEN_46 = {1{$random}};
_GEN_21 = _GEN_46[0:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_GEN_47 = {1{$random}};
_GEN_22 = _GEN_47[31:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_GEN_48 = {1{$random}};
_GEN_23 = _GEN_48[31:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_GEN_49 = {1{$random}};
_GEN_24 = _GEN_49[0:0];
`endif
end
`endif
endmodule
module Top(
input clock,
input reset,
input io_raddr,
input io_wen,
input io_waddr,
input io_wdata,
output io_rdata,
output [31:0] io_S_AVALON_readdata,
input [15:0] io_S_AVALON_address,
input io_S_AVALON_chipselect,
input io_S_AVALON_write_n,
input [31:0] io_S_AVALON_writedata,
input [23:0] io_S_STREAM_stream_in_data,
input io_S_STREAM_stream_in_startofpacket,
input io_S_STREAM_stream_in_endofpacket,
input [1:0] io_S_STREAM_stream_in_empty,
input io_S_STREAM_stream_in_valid,
input io_S_STREAM_stream_out_ready,
output io_S_STREAM_stream_in_ready,
output [15:0] io_S_STREAM_stream_out_data,
output io_S_STREAM_stream_out_startofpacket,
output io_S_STREAM_stream_out_endofpacket,
output io_S_STREAM_stream_out_empty,
output io_S_STREAM_stream_out_valid,
output [3:0] io_LEDR_STREAM_address,
output io_LEDR_STREAM_chipselect,
output [31:0] io_LEDR_STREAM_writedata,
output io_LEDR_STREAM_write_n,
output [31:0] io_SWITCHES_STREAM_address,
input [31:0] io_SWITCHES_STREAM_readdata,
output io_SWITCHES_STREAM_read
);
wire _T_65;
wire _T_70;
wire _T_77;
wire accel_clock;
wire accel_reset;
wire accel_io_enable;
wire accel_io_done;
wire [23:0] accel_io_stream_in_data;
wire accel_io_stream_in_startofpacket;
wire accel_io_stream_in_endofpacket;
wire [1:0] accel_io_stream_in_empty;
wire accel_io_stream_in_valid;
wire accel_io_stream_out_ready;
wire accel_io_stream_in_ready;
wire [15:0] accel_io_stream_out_data;
wire accel_io_stream_out_startofpacket;
wire accel_io_stream_out_endofpacket;
wire accel_io_stream_out_empty;
wire accel_io_stream_out_valid;
wire [31:0] accel_io_led_stream_out_data;
wire [31:0] accel_io_switch_stream_in_data;
wire FringeDE1SoC_clock;
wire FringeDE1SoC_reset;
wire [31:0] FringeDE1SoC_io_S_AVALON_readdata;
wire [15:0] FringeDE1SoC_io_S_AVALON_address;
wire FringeDE1SoC_io_S_AVALON_chipselect;
wire FringeDE1SoC_io_S_AVALON_write_n;
wire [31:0] FringeDE1SoC_io_S_AVALON_writedata;
wire FringeDE1SoC_io_enable;
wire FringeDE1SoC_io_done;
reg _GEN_0;
reg [31:0] _GEN_4;
reg _GEN_1;
reg [31:0] _GEN_5;
reg _GEN_2;
reg [31:0] _GEN_6;
reg _GEN_3;
reg [31:0] _GEN_7;
AccelTop accel (
.clock(accel_clock),
.reset(accel_reset),
.io_enable(accel_io_enable),
.io_done(accel_io_done),
.io_stream_in_data(accel_io_stream_in_data),
.io_stream_in_startofpacket(accel_io_stream_in_startofpacket),
.io_stream_in_endofpacket(accel_io_stream_in_endofpacket),
.io_stream_in_empty(accel_io_stream_in_empty),
.io_stream_in_valid(accel_io_stream_in_valid),
.io_stream_out_ready(accel_io_stream_out_ready),
.io_stream_in_ready(accel_io_stream_in_ready),
.io_stream_out_data(accel_io_stream_out_data),
.io_stream_out_startofpacket(accel_io_stream_out_startofpacket),
.io_stream_out_endofpacket(accel_io_stream_out_endofpacket),
.io_stream_out_empty(accel_io_stream_out_empty),
.io_stream_out_valid(accel_io_stream_out_valid),
.io_led_stream_out_data(accel_io_led_stream_out_data),
.io_switch_stream_in_data(accel_io_switch_stream_in_data)
);
FringeDE1SoC FringeDE1SoC (
.clock(FringeDE1SoC_clock),
.reset(FringeDE1SoC_reset),
.io_S_AVALON_readdata(FringeDE1SoC_io_S_AVALON_readdata),
.io_S_AVALON_address(FringeDE1SoC_io_S_AVALON_address),
.io_S_AVALON_chipselect(FringeDE1SoC_io_S_AVALON_chipselect),
.io_S_AVALON_write_n(FringeDE1SoC_io_S_AVALON_write_n),
.io_S_AVALON_writedata(FringeDE1SoC_io_S_AVALON_writedata),
.io_enable(FringeDE1SoC_io_enable),
.io_done(FringeDE1SoC_io_done)
);
assign io_rdata = _GEN_0;
assign io_S_AVALON_readdata = FringeDE1SoC_io_S_AVALON_readdata;
assign io_S_STREAM_stream_in_ready = accel_io_stream_in_ready;
assign io_S_STREAM_stream_out_data = accel_io_stream_out_data;
assign io_S_STREAM_stream_out_startofpacket = accel_io_stream_out_startofpacket;
assign io_S_STREAM_stream_out_endofpacket = accel_io_stream_out_endofpacket;
assign io_S_STREAM_stream_out_empty = accel_io_stream_out_empty;
assign io_S_STREAM_stream_out_valid = accel_io_stream_out_valid;
assign io_LEDR_STREAM_address = 4'h0;
assign io_LEDR_STREAM_chipselect = 1'h1;
assign io_LEDR_STREAM_writedata = accel_io_led_stream_out_data;
assign io_LEDR_STREAM_write_n = 1'h0;
assign io_SWITCHES_STREAM_address = 32'h0;
assign io_SWITCHES_STREAM_read = 1'h0;
assign _T_65 = _GEN_1;
assign _T_70 = _GEN_2;
assign _T_77 = _GEN_3;
assign accel_clock = clock;
assign accel_reset = reset;
assign accel_io_enable = FringeDE1SoC_io_enable;
assign accel_io_stream_in_data = io_S_STREAM_stream_in_data;
assign accel_io_stream_in_startofpacket = io_S_STREAM_stream_in_startofpacket;
assign accel_io_stream_in_endofpacket = io_S_STREAM_stream_in_endofpacket;
assign accel_io_stream_in_empty = io_S_STREAM_stream_in_empty;
assign accel_io_stream_in_valid = io_S_STREAM_stream_in_valid;
assign accel_io_stream_out_ready = io_S_STREAM_stream_out_ready;
assign accel_io_switch_stream_in_data = io_SWITCHES_STREAM_readdata;
assign FringeDE1SoC_clock = clock;
assign FringeDE1SoC_reset = reset;
assign FringeDE1SoC_io_S_AVALON_address = io_S_AVALON_address;
assign FringeDE1SoC_io_S_AVALON_chipselect = io_S_AVALON_chipselect;
assign FringeDE1SoC_io_S_AVALON_write_n = io_S_AVALON_write_n;
assign FringeDE1SoC_io_S_AVALON_writedata = io_S_AVALON_writedata;
assign FringeDE1SoC_io_done = accel_io_done;
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifndef verilator
#0.002 begin end
`endif
`ifdef RANDOMIZE_REG_INIT
_GEN_4 = {1{$random}};
_GEN_0 = _GEN_4[0:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_GEN_5 = {1{$random}};
_GEN_1 = _GEN_5[0:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_GEN_6 = {1{$random}};
_GEN_2 = _GEN_6[0:0];
`endif
`ifdef RANDOMIZE_REG_INIT
_GEN_7 = {1{$random}};
_GEN_3 = _GEN_7[0:0];
`endif
end
`endif
endmodule
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_ocm_mem.v
*
* Date : 2012-11
*
* Description : Mimics OCM model
*
*****************************************************************************/
module processing_system7_bfm_v2_0_ocm_mem();
`include "processing_system7_bfm_v2_0_local_params.v"
parameter mem_size = 32'h4_0000; /// 256 KB
parameter mem_addr_width = clogb2(mem_size/mem_width);
reg [data_width-1:0] ocm_memory [0:(mem_size/mem_width)-1]; /// 256 KB memory
/* preload memory from file */
task automatic pre_load_mem_from_file;
input [(max_chars*8)-1:0] file_name;
input [addr_width-1:0] start_addr;
input [int_width-1:0] no_of_bytes;
$readmemh(file_name,ocm_memory,start_addr>>shft_addr_bits);
endtask
/* preload memory with some random data */
task automatic pre_load_mem;
input [1:0] data_type;
input [addr_width-1:0] start_addr;
input [int_width-1:0] no_of_bytes;
integer i;
reg [mem_addr_width-1:0] addr;
begin
addr = start_addr >> shft_addr_bits;
for (i = 0; i < no_of_bytes; i = i + mem_width) begin
case(data_type)
ALL_RANDOM : ocm_memory[addr] = $random;
ALL_ZEROS : ocm_memory[addr] = 32'h0000_0000;
ALL_ONES : ocm_memory[addr] = 32'hFFFF_FFFF;
default : ocm_memory[addr] = $random;
endcase
addr = addr+1;
end
end
endtask
/* Write memory */
task write_mem;
input [max_burst_bits-1 :0] data;
input [addr_width-1:0] start_addr;
input [max_burst_bytes_width:0] no_of_bytes;
reg [mem_addr_width-1:0] addr;
reg [max_burst_bits-1 :0] wr_temp_data;
reg [data_width-1:0] pre_pad_data,post_pad_data,temp_data;
integer bytes_left;
integer pre_pad_bytes;
integer post_pad_bytes;
begin
addr = start_addr >> shft_addr_bits;
wr_temp_data = data;
`ifdef XLNX_INT_DBG
$display("[%0d] : %0s : Writing OCM Memory starting address (0x%0h) with %0d bytes.\n Data (0x%0h)",$time, DISP_INT_INFO, start_addr, no_of_bytes, data);
`endif
temp_data = wr_temp_data[data_width-1:0];
bytes_left = no_of_bytes;
/* when the no. of bytes to be updated is less than mem_width */
if(bytes_left < mem_width) begin
/* first data word in the burst , if unaligned address, the adjust the wr_data accordingly for first write*/
if(start_addr[shft_addr_bits-1:0] > 0) begin
temp_data = ocm_memory[addr];
pre_pad_bytes = mem_width - start_addr[shft_addr_bits-1:0];
repeat(pre_pad_bytes) temp_data = temp_data << 8;
repeat(pre_pad_bytes) begin
temp_data = temp_data >> 8;
temp_data[data_width-1:data_width-8] = wr_temp_data[7:0];
wr_temp_data = wr_temp_data >> 8;
end
bytes_left = bytes_left + pre_pad_bytes;
end
/* This is needed for post padding the data ...*/
post_pad_bytes = mem_width - bytes_left;
post_pad_data = ocm_memory[addr];
repeat(post_pad_bytes) temp_data = temp_data << 8;
repeat(bytes_left) post_pad_data = post_pad_data >> 8;
repeat(post_pad_bytes) begin
temp_data = temp_data >> 8;
temp_data[data_width-1:data_width-8] = post_pad_data[7:0];
post_pad_data = post_pad_data >> 8;
end
ocm_memory[addr] = temp_data;
end else begin
/* first data word in the burst , if unaligned address, the adjust the wr_data accordingly for first write*/
if(start_addr[shft_addr_bits-1:0] > 0) begin
temp_data = ocm_memory[addr];
pre_pad_bytes = mem_width - start_addr[shft_addr_bits-1:0];
repeat(pre_pad_bytes) temp_data = temp_data << 8;
repeat(pre_pad_bytes) begin
temp_data = temp_data >> 8;
temp_data[data_width-1:data_width-8] = wr_temp_data[7:0];
wr_temp_data = wr_temp_data >> 8;
bytes_left = bytes_left -1;
end
end else begin
wr_temp_data = wr_temp_data >> data_width;
bytes_left = bytes_left - mem_width;
end
/* first data word end */
ocm_memory[addr] = temp_data;
addr = addr + 1;
while(bytes_left > (mem_width-1) ) begin /// for unaliged address necessary to check for mem_wd-1 , accordingly we have to pad post bytes.
ocm_memory[addr] = wr_temp_data[data_width-1:0];
addr = addr+1;
wr_temp_data = wr_temp_data >> data_width;
bytes_left = bytes_left - mem_width;
end
post_pad_data = ocm_memory[addr];
post_pad_bytes = mem_width - bytes_left;
/* This is needed for last transfer in unaliged burst */
if(bytes_left > 0) begin
temp_data = wr_temp_data[data_width-1:0];
repeat(post_pad_bytes) temp_data = temp_data << 8;
repeat(bytes_left) post_pad_data = post_pad_data >> 8;
repeat(post_pad_bytes) begin
temp_data = temp_data >> 8;
temp_data[data_width-1:data_width-8] = post_pad_data[7:0];
post_pad_data = post_pad_data >> 8;
end
ocm_memory[addr] = temp_data;
end
end
`ifdef XLNX_INT_DBG $display("[%0d] : %0s : DONE -> Writing OCM Memory starting address (0x%0h)",$time, DISP_INT_INFO, start_addr );
`endif
end
endtask
/* read_memory */
task read_mem;
output[max_burst_bits-1 :0] data;
input [addr_width-1:0] start_addr;
input [max_burst_bytes_width:0] no_of_bytes;
integer i;
reg [mem_addr_width-1:0] addr;
reg [data_width-1:0] temp_rd_data;
reg [max_burst_bits-1:0] temp_data;
integer pre_bytes;
integer bytes_left;
begin
addr = start_addr >> shft_addr_bits;
pre_bytes = start_addr[shft_addr_bits-1:0];
bytes_left = no_of_bytes;
`ifdef XLNX_INT_DBG
$display("[%0d] : %0s : Reading OCM Memory starting address (0x%0h) -> %0d bytes",$time, DISP_INT_INFO, start_addr,no_of_bytes );
`endif
/* Get first data ... if unaligned address */
temp_data[max_burst_bits-1 : max_burst_bits-data_width] = ocm_memory[addr];
if(no_of_bytes < mem_width ) begin
temp_data = temp_data >> (pre_bytes * 8);
repeat(max_burst_bytes - mem_width)
temp_data = temp_data >> 8;
end else begin
bytes_left = bytes_left - (mem_width - pre_bytes);
addr = addr+1;
/* Got first data */
while (bytes_left > (mem_width-1) ) begin
temp_data = temp_data >> data_width;
temp_data[max_burst_bits-1 : max_burst_bits-data_width] = ocm_memory[addr];
addr = addr+1;
bytes_left = bytes_left - mem_width;
end
/* Get last valid data in the burst*/
temp_rd_data = ocm_memory[addr];
while(bytes_left > 0) begin
temp_data = temp_data >> 8;
temp_data[max_burst_bits-1 : max_burst_bits-8] = temp_rd_data[7:0];
temp_rd_data = temp_rd_data >> 8;
bytes_left = bytes_left - 1;
end
/* align to the brst_byte length */
repeat(max_burst_bytes - no_of_bytes)
temp_data = temp_data >> 8;
end
data = temp_data;
`ifdef XLNX_INT_DBG
$display("[%0d] : %0s : DONE -> Reading OCM Memory starting address (0x%0h), Data returned(0x%0h)",$time, DISP_INT_INFO, start_addr, data );
`endif
end
endtask
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module logicblock_add(clock, resetn,
i_dataa, i_dataa_valid, o_dataa_stall,
i_datab, i_datab_valid, o_datab_stall,
o_dataout, o_dataout_valid, i_stall);
parameter DATA_WIDTH = 32;
parameter FIFO_DEPTH = 64;
input clock, resetn;
input [DATA_WIDTH-1:0] i_dataa;
input [DATA_WIDTH-1:0] i_datab;
input i_dataa_valid, i_datab_valid;
output o_dataa_stall, o_datab_stall;
output [DATA_WIDTH-1:0] o_dataout;
output o_dataout_valid;
input i_stall;
wire [DATA_WIDTH-1:0] dataa;
wire [DATA_WIDTH-1:0] datab;
wire is_fifo_a_valid;
wire is_fifo_b_valid;
wire is_stalled;
vfabric_buffered_fifo fifo_a ( .clock(clock), .resetn(resetn),
.data_in(i_dataa), .data_out(dataa), .valid_in(i_dataa_valid),
.valid_out( is_fifo_a_valid ), .stall_in(is_stalled), .stall_out(o_dataa_stall) );
defparam fifo_a.DATA_WIDTH = DATA_WIDTH;
defparam fifo_a.DEPTH = FIFO_DEPTH;
vfabric_buffered_fifo fifo_b ( .clock(clock), .resetn(resetn),
.data_in(i_datab), .data_out(datab), .valid_in(i_datab_valid),
.valid_out( is_fifo_b_valid ), .stall_in(is_stalled), .stall_out(o_datab_stall) );
defparam fifo_b.DATA_WIDTH = DATA_WIDTH;
defparam fifo_b.DEPTH = FIFO_DEPTH;
assign is_stalled = ~(is_fifo_a_valid & is_fifo_b_valid & ~i_stall);
assign o_dataout = dataa + datab;
assign o_dataout_valid = is_fifo_a_valid & is_fifo_b_valid;
endmodule
|
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