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(** * ImpCEvalFun: Evaluation Function for Imp *)
(* #################################### *)
(** * Evaluation Function *)
Require Import Imp.
(** Here's a first try at an evaluation function for commands,
omitting [WHILE]. *)
Fixpoint ceval_step1 (st : state) (c : com) : state :=
match c with
| SKIP =>
st
| l ::= a1 =>
update st l (aeval st a1)
| c1 ;; c2 =>
let st' := ceval_step1 st c1 in
ceval_step1 st' c2
| IFB b THEN c1 ELSE c2 FI =>
if (beval st b)
then ceval_step1 st c1
else ceval_step1 st c2
| WHILE b1 DO c1 END =>
st (* bogus *)
end.
(** In a traditional functional programming language like ML or
Haskell we could write the WHILE case as follows:
<<
| WHILE b1 DO c1 END =>
if (beval st b1)
then ceval_step1 st (c1;; WHILE b1 DO c1 END)
else st
>>
Coq doesn't accept such a definition ([Error: Cannot guess
decreasing argument of fix]) because the function we want to
define is not guaranteed to terminate. Indeed, the changed
[ceval_step1] function applied to the [loop] program from [Imp.v] would
never terminate. Since Coq is not just a functional programming
language, but also a consistent logic, any potentially
non-terminating function needs to be rejected. Here is an
invalid(!) Coq program showing what would go wrong if Coq allowed
non-terminating recursive functions:
<<
Fixpoint loop_false (n : nat) : False := loop_false n.
>>
That is, propositions like [False] would become
provable (e.g. [loop_false 0] would be a proof of [False]), which
would be a disaster for Coq's logical consistency.
Thus, because it doesn't terminate on all inputs, the full version
of [ceval_step1] cannot be written in Coq -- at least not
without one additional trick... *)
(** Second try, using an extra numeric argument as a "step index" to
ensure that evaluation always terminates. *)
Fixpoint ceval_step2 (st : state) (c : com) (i : nat) : state :=
match i with
| O => empty_state
| S i' =>
match c with
| SKIP =>
st
| l ::= a1 =>
update st l (aeval st a1)
| c1 ;; c2 =>
let st' := ceval_step2 st c1 i' in
ceval_step2 st' c2 i'
| IFB b THEN c1 ELSE c2 FI =>
if (beval st b)
then ceval_step2 st c1 i'
else ceval_step2 st c2 i'
| WHILE b1 DO c1 END =>
if (beval st b1)
then let st' := ceval_step2 st c1 i' in
ceval_step2 st' c i'
else st
end
end.
(** _Note_: It is tempting to think that the index [i] here is
counting the "number of steps of evaluation." But if you look
closely you'll see that this is not the case: for example, in the
rule for sequencing, the same [i] is passed to both recursive
calls. Understanding the exact way that [i] is treated will be
important in the proof of [ceval__ceval_step], which is given as
an exercise below. *)
(** Third try, returning an [option state] instead of just a [state]
so that we can distinguish between normal and abnormal
termination. *)
Fixpoint ceval_step3 (st : state) (c : com) (i : nat)
: option state :=
match i with
| O => None
| S i' =>
match c with
| SKIP =>
Some st
| l ::= a1 =>
Some (update st l (aeval st a1))
| c1 ;; c2 =>
match (ceval_step3 st c1 i') with
| Some st' => ceval_step3 st' c2 i'
| None => None
end
| IFB b THEN c1 ELSE c2 FI =>
if (beval st b)
then ceval_step3 st c1 i'
else ceval_step3 st c2 i'
| WHILE b1 DO c1 END =>
if (beval st b1)
then match (ceval_step3 st c1 i') with
| Some st' => ceval_step3 st' c i'
| None => None
end
else Some st
end
end.
(** We can improve the readability of this definition by introducing a
bit of auxiliary notation to hide the "plumbing" involved in
repeatedly matching against optional states. *)
Notation "'LETOPT' x <== e1 'IN' e2"
:= (match e1 with
| Some x => e2
| None => None
end)
(right associativity, at level 60).
Fixpoint ceval_step (st : state) (c : com) (i : nat)
: option state :=
match i with
| O => None
| S i' =>
match c with
| SKIP =>
Some st
| l ::= a1 =>
Some (update st l (aeval st a1))
| c1 ;; c2 =>
LETOPT st' <== ceval_step st c1 i' IN
ceval_step st' c2 i'
| IFB b THEN c1 ELSE c2 FI =>
if (beval st b)
then ceval_step st c1 i'
else ceval_step st c2 i'
| WHILE b1 DO c1 END =>
if (beval st b1)
then LETOPT st' <== ceval_step st c1 i' IN
ceval_step st' c i'
else Some st
end
end.
Definition test_ceval (st:state) (c:com) :=
match ceval_step st c 500 with
| None => None
| Some st => Some (st X, st Y, st Z)
end.
(* Eval compute in
(test_ceval empty_state
(X ::= ANum 2;;
IFB BLe (AId X) (ANum 1)
THEN Y ::= ANum 3
ELSE Z ::= ANum 4
FI)).
====>
Some (2, 0, 4) *)
(** **** Exercise: 2 stars (pup_to_n) *)
(** Write an Imp program that sums the numbers from [1] to
[X] (inclusive: [1 + 2 + ... + X]) in the variable [Y]. Make sure
your solution satisfies the test that follows. *)
Definition pup_to_n : com :=
(* FILL IN HERE *) admit.
(*
Example pup_to_n_1 :
test_ceval (update empty_state X 5) pup_to_n
= Some (0, 15, 0).
Proof. reflexivity. Qed.
*)
(** [] *)
(** **** Exercise: 2 stars, optional (peven) *)
(** Write a [While] program that sets [Z] to [0] if [X] is even and
sets [Z] to [1] otherwise. Use [ceval_test] to test your
program. *)
(* FILL IN HERE *)
(** [] *)
(* ################################################################ *)
(** * Equivalence of Relational and Step-Indexed Evaluation *)
(** As with arithmetic and boolean expressions, we'd hope that
the two alternative definitions of evaluation actually boil down
to the same thing. This section shows that this is the case.
Make sure you understand the statements of the theorems and can
follow the structure of the proofs. *)
Theorem ceval_step__ceval: forall c st st',
(exists i, ceval_step st c i = Some st') ->
c / st || st'.
Proof.
intros c st st' H.
inversion H as [i E].
clear H.
generalize dependent st'.
generalize dependent st.
generalize dependent c.
induction i as [| i' ].
Case "i = 0 -- contradictory".
intros c st st' H. inversion H.
Case "i = S i'".
intros c st st' H.
com_cases (destruct c) SCase;
simpl in H; inversion H; subst; clear H.
SCase "SKIP". apply E_Skip.
SCase "::=". apply E_Ass. reflexivity.
SCase ";;".
destruct (ceval_step st c1 i') eqn:Heqr1.
SSCase "Evaluation of r1 terminates normally".
apply E_Seq with s.
apply IHi'. rewrite Heqr1. reflexivity.
apply IHi'. simpl in H1. assumption.
SSCase "Otherwise -- contradiction".
inversion H1.
SCase "IFB".
destruct (beval st b) eqn:Heqr.
SSCase "r = true".
apply E_IfTrue. rewrite Heqr. reflexivity.
apply IHi'. assumption.
SSCase "r = false".
apply E_IfFalse. rewrite Heqr. reflexivity.
apply IHi'. assumption.
SCase "WHILE". destruct (beval st b) eqn :Heqr.
SSCase "r = true".
destruct (ceval_step st c i') eqn:Heqr1.
SSSCase "r1 = Some s".
apply E_WhileLoop with s. rewrite Heqr. reflexivity.
apply IHi'. rewrite Heqr1. reflexivity.
apply IHi'. simpl in H1. assumption.
SSSCase "r1 = None".
inversion H1.
SSCase "r = false".
inversion H1.
apply E_WhileEnd.
rewrite <- Heqr. subst. reflexivity. Qed.
(** **** Exercise: 4 stars (ceval_step__ceval_inf) *)
(** Write an informal proof of [ceval_step__ceval], following the
usual template. (The template for case analysis on an inductively
defined value should look the same as for induction, except that
there is no induction hypothesis.) Make your proof communicate
the main ideas to a human reader; do not simply transcribe the
steps of the formal proof.
(* FILL IN HERE *)
[]
*)
Theorem ceval_step_more: forall i1 i2 st st' c,
i1 <= i2 ->
ceval_step st c i1 = Some st' ->
ceval_step st c i2 = Some st'.
Proof.
induction i1 as [|i1']; intros i2 st st' c Hle Hceval.
Case "i1 = 0".
simpl in Hceval. inversion Hceval.
Case "i1 = S i1'".
destruct i2 as [|i2']. inversion Hle.
assert (Hle': i1' <= i2') by omega.
com_cases (destruct c) SCase.
SCase "SKIP".
simpl in Hceval. inversion Hceval.
reflexivity.
SCase "::=".
simpl in Hceval. inversion Hceval.
reflexivity.
SCase ";;".
simpl in Hceval. simpl.
destruct (ceval_step st c1 i1') eqn:Heqst1'o.
SSCase "st1'o = Some".
apply (IHi1' i2') in Heqst1'o; try assumption.
rewrite Heqst1'o. simpl. simpl in Hceval.
apply (IHi1' i2') in Hceval; try assumption.
SSCase "st1'o = None".
inversion Hceval.
SCase "IFB".
simpl in Hceval. simpl.
destruct (beval st b); apply (IHi1' i2') in Hceval; assumption.
SCase "WHILE".
simpl in Hceval. simpl.
destruct (beval st b); try assumption.
destruct (ceval_step st c i1') eqn: Heqst1'o.
SSCase "st1'o = Some".
apply (IHi1' i2') in Heqst1'o; try assumption.
rewrite -> Heqst1'o. simpl. simpl in Hceval.
apply (IHi1' i2') in Hceval; try assumption.
SSCase "i1'o = None".
simpl in Hceval. inversion Hceval. Qed.
(** **** Exercise: 3 stars (ceval__ceval_step) *)
(** Finish the following proof. You'll need [ceval_step_more] in a
few places, as well as some basic facts about [<=] and [plus]. *)
Theorem ceval__ceval_step: forall c st st',
c / st || st' ->
exists i, ceval_step st c i = Some st'.
Proof.
intros c st st' Hce.
ceval_cases (induction Hce) Case.
(* FILL IN HERE *) Admitted.
(** [] *)
Theorem ceval_and_ceval_step_coincide: forall c st st',
c / st || st'
<-> exists i, ceval_step st c i = Some st'.
Proof.
intros c st st'.
split. apply ceval__ceval_step. apply ceval_step__ceval.
Qed.
(* ####################################################### *)
(** * Determinism of Evaluation (Simpler Proof) *)
(** Here's a slicker proof showing that the evaluation relation is
deterministic, using the fact that the relational and step-indexed
definition of evaluation are the same. *)
Theorem ceval_deterministic' : forall c st st1 st2,
c / st || st1 ->
c / st || st2 ->
st1 = st2.
Proof.
intros c st st1 st2 He1 He2.
apply ceval__ceval_step in He1.
apply ceval__ceval_step in He2.
inversion He1 as [i1 E1].
inversion He2 as [i2 E2].
apply ceval_step_more with (i2 := i1 + i2) in E1.
apply ceval_step_more with (i2 := i1 + i2) in E2.
rewrite E1 in E2. inversion E2. reflexivity.
omega. omega. Qed.
(** $Date: 2014-12-31 11:17:56 -0500 (Wed, 31 Dec 2014) $ *)
|
//-----------------------------------------------------------------------------
// system_stub.v
//-----------------------------------------------------------------------------
module system_stub
(
processing_system7_0_MIO,
processing_system7_0_PS_SRSTB_pin,
processing_system7_0_PS_CLK_pin,
processing_system7_0_PS_PORB_pin,
processing_system7_0_DDR_Clk,
processing_system7_0_DDR_Clk_n,
processing_system7_0_DDR_CKE,
processing_system7_0_DDR_CS_n,
processing_system7_0_DDR_RAS_n,
processing_system7_0_DDR_CAS_n,
processing_system7_0_DDR_WEB_pin,
processing_system7_0_DDR_BankAddr,
processing_system7_0_DDR_Addr,
processing_system7_0_DDR_ODT,
processing_system7_0_DDR_DRSTB,
processing_system7_0_DDR_DQ,
processing_system7_0_DDR_DM,
processing_system7_0_DDR_DQS,
processing_system7_0_DDR_DQS_n,
processing_system7_0_DDR_VRN,
processing_system7_0_DDR_VRP,
processing_system7_0_M_AXI_GP1_ARESETN_pin,
processing_system7_0_S_AXI_HP1_ARESETN_pin,
processing_system7_0_FCLK_CLK3_pin,
processing_system7_0_FCLK_CLK0_pin,
processing_system7_0_M_AXI_GP1_ARVALID_pin,
processing_system7_0_M_AXI_GP1_AWVALID_pin,
processing_system7_0_M_AXI_GP1_BREADY_pin,
processing_system7_0_M_AXI_GP1_RREADY_pin,
processing_system7_0_M_AXI_GP1_WLAST_pin,
processing_system7_0_M_AXI_GP1_WVALID_pin,
processing_system7_0_M_AXI_GP1_ARID_pin,
processing_system7_0_M_AXI_GP1_AWID_pin,
processing_system7_0_M_AXI_GP1_WID_pin,
processing_system7_0_M_AXI_GP1_ARBURST_pin,
processing_system7_0_M_AXI_GP1_ARLOCK_pin,
processing_system7_0_M_AXI_GP1_ARSIZE_pin,
processing_system7_0_M_AXI_GP1_AWBURST_pin,
processing_system7_0_M_AXI_GP1_AWLOCK_pin,
processing_system7_0_M_AXI_GP1_AWSIZE_pin,
processing_system7_0_M_AXI_GP1_ARPROT_pin,
processing_system7_0_M_AXI_GP1_AWPROT_pin,
processing_system7_0_M_AXI_GP1_ARADDR_pin,
processing_system7_0_M_AXI_GP1_AWADDR_pin,
processing_system7_0_M_AXI_GP1_WDATA_pin,
processing_system7_0_M_AXI_GP1_ARCACHE_pin,
processing_system7_0_M_AXI_GP1_ARLEN_pin,
processing_system7_0_M_AXI_GP1_ARQOS_pin,
processing_system7_0_M_AXI_GP1_AWCACHE_pin,
processing_system7_0_M_AXI_GP1_AWLEN_pin,
processing_system7_0_M_AXI_GP1_AWQOS_pin,
processing_system7_0_M_AXI_GP1_WSTRB_pin,
processing_system7_0_M_AXI_GP1_ACLK_pin,
processing_system7_0_M_AXI_GP1_ARREADY_pin,
processing_system7_0_M_AXI_GP1_AWREADY_pin,
processing_system7_0_M_AXI_GP1_BVALID_pin,
processing_system7_0_M_AXI_GP1_RLAST_pin,
processing_system7_0_M_AXI_GP1_RVALID_pin,
processing_system7_0_M_AXI_GP1_WREADY_pin,
processing_system7_0_M_AXI_GP1_BID_pin,
processing_system7_0_M_AXI_GP1_RID_pin,
processing_system7_0_M_AXI_GP1_BRESP_pin,
processing_system7_0_M_AXI_GP1_RRESP_pin,
processing_system7_0_M_AXI_GP1_RDATA_pin,
processing_system7_0_S_AXI_HP1_ARREADY_pin,
processing_system7_0_S_AXI_HP1_AWREADY_pin,
processing_system7_0_S_AXI_HP1_BVALID_pin,
processing_system7_0_S_AXI_HP1_RLAST_pin,
processing_system7_0_S_AXI_HP1_RVALID_pin,
processing_system7_0_S_AXI_HP1_WREADY_pin,
processing_system7_0_S_AXI_HP1_BRESP_pin,
processing_system7_0_S_AXI_HP1_RRESP_pin,
processing_system7_0_S_AXI_HP1_BID_pin,
processing_system7_0_S_AXI_HP1_RID_pin,
processing_system7_0_S_AXI_HP1_RDATA_pin,
processing_system7_0_S_AXI_HP1_ACLK_pin,
processing_system7_0_S_AXI_HP1_ARVALID_pin,
processing_system7_0_S_AXI_HP1_AWVALID_pin,
processing_system7_0_S_AXI_HP1_BREADY_pin,
processing_system7_0_S_AXI_HP1_RREADY_pin,
processing_system7_0_S_AXI_HP1_WLAST_pin,
processing_system7_0_S_AXI_HP1_WVALID_pin,
processing_system7_0_S_AXI_HP1_ARBURST_pin,
processing_system7_0_S_AXI_HP1_ARLOCK_pin,
processing_system7_0_S_AXI_HP1_ARSIZE_pin,
processing_system7_0_S_AXI_HP1_AWBURST_pin,
processing_system7_0_S_AXI_HP1_AWLOCK_pin,
processing_system7_0_S_AXI_HP1_AWSIZE_pin,
processing_system7_0_S_AXI_HP1_ARPROT_pin,
processing_system7_0_S_AXI_HP1_AWPROT_pin,
processing_system7_0_S_AXI_HP1_ARADDR_pin,
processing_system7_0_S_AXI_HP1_AWADDR_pin,
processing_system7_0_S_AXI_HP1_ARCACHE_pin,
processing_system7_0_S_AXI_HP1_ARLEN_pin,
processing_system7_0_S_AXI_HP1_ARQOS_pin,
processing_system7_0_S_AXI_HP1_AWCACHE_pin,
processing_system7_0_S_AXI_HP1_AWLEN_pin,
processing_system7_0_S_AXI_HP1_AWQOS_pin,
processing_system7_0_S_AXI_HP1_ARID_pin,
processing_system7_0_S_AXI_HP1_AWID_pin,
processing_system7_0_S_AXI_HP1_WID_pin,
processing_system7_0_S_AXI_HP1_WDATA_pin,
processing_system7_0_S_AXI_HP1_WSTRB_pin,
processing_system7_0_I2C0_SDA_pin,
processing_system7_0_I2C0_SCL_pin,
processing_system7_0_GPIO_I_pin,
processing_system7_0_GPIO_O_pin,
processing_system7_0_GPIO_T_pin
);
inout [53:0] processing_system7_0_MIO;
input processing_system7_0_PS_SRSTB_pin;
input processing_system7_0_PS_CLK_pin;
input processing_system7_0_PS_PORB_pin;
inout processing_system7_0_DDR_Clk;
inout processing_system7_0_DDR_Clk_n;
inout processing_system7_0_DDR_CKE;
inout processing_system7_0_DDR_CS_n;
inout processing_system7_0_DDR_RAS_n;
inout processing_system7_0_DDR_CAS_n;
output processing_system7_0_DDR_WEB_pin;
inout [2:0] processing_system7_0_DDR_BankAddr;
inout [14:0] processing_system7_0_DDR_Addr;
inout processing_system7_0_DDR_ODT;
inout processing_system7_0_DDR_DRSTB;
inout [31:0] processing_system7_0_DDR_DQ;
inout [3:0] processing_system7_0_DDR_DM;
inout [3:0] processing_system7_0_DDR_DQS;
inout [3:0] processing_system7_0_DDR_DQS_n;
inout processing_system7_0_DDR_VRN;
inout processing_system7_0_DDR_VRP;
output processing_system7_0_M_AXI_GP1_ARESETN_pin;
output processing_system7_0_S_AXI_HP1_ARESETN_pin;
output processing_system7_0_FCLK_CLK3_pin;
output processing_system7_0_FCLK_CLK0_pin;
output processing_system7_0_M_AXI_GP1_ARVALID_pin;
output processing_system7_0_M_AXI_GP1_AWVALID_pin;
output processing_system7_0_M_AXI_GP1_BREADY_pin;
output processing_system7_0_M_AXI_GP1_RREADY_pin;
output processing_system7_0_M_AXI_GP1_WLAST_pin;
output processing_system7_0_M_AXI_GP1_WVALID_pin;
output [11:0] processing_system7_0_M_AXI_GP1_ARID_pin;
output [11:0] processing_system7_0_M_AXI_GP1_AWID_pin;
output [11:0] processing_system7_0_M_AXI_GP1_WID_pin;
output [1:0] processing_system7_0_M_AXI_GP1_ARBURST_pin;
output [1:0] processing_system7_0_M_AXI_GP1_ARLOCK_pin;
output [2:0] processing_system7_0_M_AXI_GP1_ARSIZE_pin;
output [1:0] processing_system7_0_M_AXI_GP1_AWBURST_pin;
output [1:0] processing_system7_0_M_AXI_GP1_AWLOCK_pin;
output [2:0] processing_system7_0_M_AXI_GP1_AWSIZE_pin;
output [2:0] processing_system7_0_M_AXI_GP1_ARPROT_pin;
output [2:0] processing_system7_0_M_AXI_GP1_AWPROT_pin;
output [31:0] processing_system7_0_M_AXI_GP1_ARADDR_pin;
output [31:0] processing_system7_0_M_AXI_GP1_AWADDR_pin;
output [31:0] processing_system7_0_M_AXI_GP1_WDATA_pin;
output [3:0] processing_system7_0_M_AXI_GP1_ARCACHE_pin;
output [3:0] processing_system7_0_M_AXI_GP1_ARLEN_pin;
output [3:0] processing_system7_0_M_AXI_GP1_ARQOS_pin;
output [3:0] processing_system7_0_M_AXI_GP1_AWCACHE_pin;
output [3:0] processing_system7_0_M_AXI_GP1_AWLEN_pin;
output [3:0] processing_system7_0_M_AXI_GP1_AWQOS_pin;
output [3:0] processing_system7_0_M_AXI_GP1_WSTRB_pin;
input processing_system7_0_M_AXI_GP1_ACLK_pin;
input processing_system7_0_M_AXI_GP1_ARREADY_pin;
input processing_system7_0_M_AXI_GP1_AWREADY_pin;
input processing_system7_0_M_AXI_GP1_BVALID_pin;
input processing_system7_0_M_AXI_GP1_RLAST_pin;
input processing_system7_0_M_AXI_GP1_RVALID_pin;
input processing_system7_0_M_AXI_GP1_WREADY_pin;
input [11:0] processing_system7_0_M_AXI_GP1_BID_pin;
input [11:0] processing_system7_0_M_AXI_GP1_RID_pin;
input [1:0] processing_system7_0_M_AXI_GP1_BRESP_pin;
input [1:0] processing_system7_0_M_AXI_GP1_RRESP_pin;
input [31:0] processing_system7_0_M_AXI_GP1_RDATA_pin;
output processing_system7_0_S_AXI_HP1_ARREADY_pin;
output processing_system7_0_S_AXI_HP1_AWREADY_pin;
output processing_system7_0_S_AXI_HP1_BVALID_pin;
output processing_system7_0_S_AXI_HP1_RLAST_pin;
output processing_system7_0_S_AXI_HP1_RVALID_pin;
output processing_system7_0_S_AXI_HP1_WREADY_pin;
output [1:0] processing_system7_0_S_AXI_HP1_BRESP_pin;
output [1:0] processing_system7_0_S_AXI_HP1_RRESP_pin;
output [5:0] processing_system7_0_S_AXI_HP1_BID_pin;
output [5:0] processing_system7_0_S_AXI_HP1_RID_pin;
output [63:0] processing_system7_0_S_AXI_HP1_RDATA_pin;
input processing_system7_0_S_AXI_HP1_ACLK_pin;
input processing_system7_0_S_AXI_HP1_ARVALID_pin;
input processing_system7_0_S_AXI_HP1_AWVALID_pin;
input processing_system7_0_S_AXI_HP1_BREADY_pin;
input processing_system7_0_S_AXI_HP1_RREADY_pin;
input processing_system7_0_S_AXI_HP1_WLAST_pin;
input processing_system7_0_S_AXI_HP1_WVALID_pin;
input [1:0] processing_system7_0_S_AXI_HP1_ARBURST_pin;
input [1:0] processing_system7_0_S_AXI_HP1_ARLOCK_pin;
input [2:0] processing_system7_0_S_AXI_HP1_ARSIZE_pin;
input [1:0] processing_system7_0_S_AXI_HP1_AWBURST_pin;
input [1:0] processing_system7_0_S_AXI_HP1_AWLOCK_pin;
input [2:0] processing_system7_0_S_AXI_HP1_AWSIZE_pin;
input [2:0] processing_system7_0_S_AXI_HP1_ARPROT_pin;
input [2:0] processing_system7_0_S_AXI_HP1_AWPROT_pin;
input [31:0] processing_system7_0_S_AXI_HP1_ARADDR_pin;
input [31:0] processing_system7_0_S_AXI_HP1_AWADDR_pin;
input [3:0] processing_system7_0_S_AXI_HP1_ARCACHE_pin;
input [3:0] processing_system7_0_S_AXI_HP1_ARLEN_pin;
input [3:0] processing_system7_0_S_AXI_HP1_ARQOS_pin;
input [3:0] processing_system7_0_S_AXI_HP1_AWCACHE_pin;
input [3:0] processing_system7_0_S_AXI_HP1_AWLEN_pin;
input [3:0] processing_system7_0_S_AXI_HP1_AWQOS_pin;
input [5:0] processing_system7_0_S_AXI_HP1_ARID_pin;
input [5:0] processing_system7_0_S_AXI_HP1_AWID_pin;
input [5:0] processing_system7_0_S_AXI_HP1_WID_pin;
input [63:0] processing_system7_0_S_AXI_HP1_WDATA_pin;
input [7:0] processing_system7_0_S_AXI_HP1_WSTRB_pin;
inout processing_system7_0_I2C0_SDA_pin;
inout processing_system7_0_I2C0_SCL_pin;
input [47:0] processing_system7_0_GPIO_I_pin;
output [47:0] processing_system7_0_GPIO_O_pin;
output [47:0] processing_system7_0_GPIO_T_pin;
(* BOX_TYPE = "user_black_box" *)
system
system_i (
.processing_system7_0_MIO ( processing_system7_0_MIO ),
.processing_system7_0_PS_SRSTB_pin ( processing_system7_0_PS_SRSTB_pin ),
.processing_system7_0_PS_CLK_pin ( processing_system7_0_PS_CLK_pin ),
.processing_system7_0_PS_PORB_pin ( processing_system7_0_PS_PORB_pin ),
.processing_system7_0_DDR_Clk ( processing_system7_0_DDR_Clk ),
.processing_system7_0_DDR_Clk_n ( processing_system7_0_DDR_Clk_n ),
.processing_system7_0_DDR_CKE ( processing_system7_0_DDR_CKE ),
.processing_system7_0_DDR_CS_n ( processing_system7_0_DDR_CS_n ),
.processing_system7_0_DDR_RAS_n ( processing_system7_0_DDR_RAS_n ),
.processing_system7_0_DDR_CAS_n ( processing_system7_0_DDR_CAS_n ),
.processing_system7_0_DDR_WEB_pin ( processing_system7_0_DDR_WEB_pin ),
.processing_system7_0_DDR_BankAddr ( processing_system7_0_DDR_BankAddr ),
.processing_system7_0_DDR_Addr ( processing_system7_0_DDR_Addr ),
.processing_system7_0_DDR_ODT ( processing_system7_0_DDR_ODT ),
.processing_system7_0_DDR_DRSTB ( processing_system7_0_DDR_DRSTB ),
.processing_system7_0_DDR_DQ ( processing_system7_0_DDR_DQ ),
.processing_system7_0_DDR_DM ( processing_system7_0_DDR_DM ),
.processing_system7_0_DDR_DQS ( processing_system7_0_DDR_DQS ),
.processing_system7_0_DDR_DQS_n ( processing_system7_0_DDR_DQS_n ),
.processing_system7_0_DDR_VRN ( processing_system7_0_DDR_VRN ),
.processing_system7_0_DDR_VRP ( processing_system7_0_DDR_VRP ),
.processing_system7_0_M_AXI_GP1_ARESETN_pin ( processing_system7_0_M_AXI_GP1_ARESETN_pin ),
.processing_system7_0_S_AXI_HP1_ARESETN_pin ( processing_system7_0_S_AXI_HP1_ARESETN_pin ),
.processing_system7_0_FCLK_CLK3_pin ( processing_system7_0_FCLK_CLK3_pin ),
.processing_system7_0_FCLK_CLK0_pin ( processing_system7_0_FCLK_CLK0_pin ),
.processing_system7_0_M_AXI_GP1_ARVALID_pin ( processing_system7_0_M_AXI_GP1_ARVALID_pin ),
.processing_system7_0_M_AXI_GP1_AWVALID_pin ( processing_system7_0_M_AXI_GP1_AWVALID_pin ),
.processing_system7_0_M_AXI_GP1_BREADY_pin ( processing_system7_0_M_AXI_GP1_BREADY_pin ),
.processing_system7_0_M_AXI_GP1_RREADY_pin ( processing_system7_0_M_AXI_GP1_RREADY_pin ),
.processing_system7_0_M_AXI_GP1_WLAST_pin ( processing_system7_0_M_AXI_GP1_WLAST_pin ),
.processing_system7_0_M_AXI_GP1_WVALID_pin ( processing_system7_0_M_AXI_GP1_WVALID_pin ),
.processing_system7_0_M_AXI_GP1_ARID_pin ( processing_system7_0_M_AXI_GP1_ARID_pin ),
.processing_system7_0_M_AXI_GP1_AWID_pin ( processing_system7_0_M_AXI_GP1_AWID_pin ),
.processing_system7_0_M_AXI_GP1_WID_pin ( processing_system7_0_M_AXI_GP1_WID_pin ),
.processing_system7_0_M_AXI_GP1_ARBURST_pin ( processing_system7_0_M_AXI_GP1_ARBURST_pin ),
.processing_system7_0_M_AXI_GP1_ARLOCK_pin ( processing_system7_0_M_AXI_GP1_ARLOCK_pin ),
.processing_system7_0_M_AXI_GP1_ARSIZE_pin ( processing_system7_0_M_AXI_GP1_ARSIZE_pin ),
.processing_system7_0_M_AXI_GP1_AWBURST_pin ( processing_system7_0_M_AXI_GP1_AWBURST_pin ),
.processing_system7_0_M_AXI_GP1_AWLOCK_pin ( processing_system7_0_M_AXI_GP1_AWLOCK_pin ),
.processing_system7_0_M_AXI_GP1_AWSIZE_pin ( processing_system7_0_M_AXI_GP1_AWSIZE_pin ),
.processing_system7_0_M_AXI_GP1_ARPROT_pin ( processing_system7_0_M_AXI_GP1_ARPROT_pin ),
.processing_system7_0_M_AXI_GP1_AWPROT_pin ( processing_system7_0_M_AXI_GP1_AWPROT_pin ),
.processing_system7_0_M_AXI_GP1_ARADDR_pin ( processing_system7_0_M_AXI_GP1_ARADDR_pin ),
.processing_system7_0_M_AXI_GP1_AWADDR_pin ( processing_system7_0_M_AXI_GP1_AWADDR_pin ),
.processing_system7_0_M_AXI_GP1_WDATA_pin ( processing_system7_0_M_AXI_GP1_WDATA_pin ),
.processing_system7_0_M_AXI_GP1_ARCACHE_pin ( processing_system7_0_M_AXI_GP1_ARCACHE_pin ),
.processing_system7_0_M_AXI_GP1_ARLEN_pin ( processing_system7_0_M_AXI_GP1_ARLEN_pin ),
.processing_system7_0_M_AXI_GP1_ARQOS_pin ( processing_system7_0_M_AXI_GP1_ARQOS_pin ),
.processing_system7_0_M_AXI_GP1_AWCACHE_pin ( processing_system7_0_M_AXI_GP1_AWCACHE_pin ),
.processing_system7_0_M_AXI_GP1_AWLEN_pin ( processing_system7_0_M_AXI_GP1_AWLEN_pin ),
.processing_system7_0_M_AXI_GP1_AWQOS_pin ( processing_system7_0_M_AXI_GP1_AWQOS_pin ),
.processing_system7_0_M_AXI_GP1_WSTRB_pin ( processing_system7_0_M_AXI_GP1_WSTRB_pin ),
.processing_system7_0_M_AXI_GP1_ACLK_pin ( processing_system7_0_M_AXI_GP1_ACLK_pin ),
.processing_system7_0_M_AXI_GP1_ARREADY_pin ( processing_system7_0_M_AXI_GP1_ARREADY_pin ),
.processing_system7_0_M_AXI_GP1_AWREADY_pin ( processing_system7_0_M_AXI_GP1_AWREADY_pin ),
.processing_system7_0_M_AXI_GP1_BVALID_pin ( processing_system7_0_M_AXI_GP1_BVALID_pin ),
.processing_system7_0_M_AXI_GP1_RLAST_pin ( processing_system7_0_M_AXI_GP1_RLAST_pin ),
.processing_system7_0_M_AXI_GP1_RVALID_pin ( processing_system7_0_M_AXI_GP1_RVALID_pin ),
.processing_system7_0_M_AXI_GP1_WREADY_pin ( processing_system7_0_M_AXI_GP1_WREADY_pin ),
.processing_system7_0_M_AXI_GP1_BID_pin ( processing_system7_0_M_AXI_GP1_BID_pin ),
.processing_system7_0_M_AXI_GP1_RID_pin ( processing_system7_0_M_AXI_GP1_RID_pin ),
.processing_system7_0_M_AXI_GP1_BRESP_pin ( processing_system7_0_M_AXI_GP1_BRESP_pin ),
.processing_system7_0_M_AXI_GP1_RRESP_pin ( processing_system7_0_M_AXI_GP1_RRESP_pin ),
.processing_system7_0_M_AXI_GP1_RDATA_pin ( processing_system7_0_M_AXI_GP1_RDATA_pin ),
.processing_system7_0_S_AXI_HP1_ARREADY_pin ( processing_system7_0_S_AXI_HP1_ARREADY_pin ),
.processing_system7_0_S_AXI_HP1_AWREADY_pin ( processing_system7_0_S_AXI_HP1_AWREADY_pin ),
.processing_system7_0_S_AXI_HP1_BVALID_pin ( processing_system7_0_S_AXI_HP1_BVALID_pin ),
.processing_system7_0_S_AXI_HP1_RLAST_pin ( processing_system7_0_S_AXI_HP1_RLAST_pin ),
.processing_system7_0_S_AXI_HP1_RVALID_pin ( processing_system7_0_S_AXI_HP1_RVALID_pin ),
.processing_system7_0_S_AXI_HP1_WREADY_pin ( processing_system7_0_S_AXI_HP1_WREADY_pin ),
.processing_system7_0_S_AXI_HP1_BRESP_pin ( processing_system7_0_S_AXI_HP1_BRESP_pin ),
.processing_system7_0_S_AXI_HP1_RRESP_pin ( processing_system7_0_S_AXI_HP1_RRESP_pin ),
.processing_system7_0_S_AXI_HP1_BID_pin ( processing_system7_0_S_AXI_HP1_BID_pin ),
.processing_system7_0_S_AXI_HP1_RID_pin ( processing_system7_0_S_AXI_HP1_RID_pin ),
.processing_system7_0_S_AXI_HP1_RDATA_pin ( processing_system7_0_S_AXI_HP1_RDATA_pin ),
.processing_system7_0_S_AXI_HP1_ACLK_pin ( processing_system7_0_S_AXI_HP1_ACLK_pin ),
.processing_system7_0_S_AXI_HP1_ARVALID_pin ( processing_system7_0_S_AXI_HP1_ARVALID_pin ),
.processing_system7_0_S_AXI_HP1_AWVALID_pin ( processing_system7_0_S_AXI_HP1_AWVALID_pin ),
.processing_system7_0_S_AXI_HP1_BREADY_pin ( processing_system7_0_S_AXI_HP1_BREADY_pin ),
.processing_system7_0_S_AXI_HP1_RREADY_pin ( processing_system7_0_S_AXI_HP1_RREADY_pin ),
.processing_system7_0_S_AXI_HP1_WLAST_pin ( processing_system7_0_S_AXI_HP1_WLAST_pin ),
.processing_system7_0_S_AXI_HP1_WVALID_pin ( processing_system7_0_S_AXI_HP1_WVALID_pin ),
.processing_system7_0_S_AXI_HP1_ARBURST_pin ( processing_system7_0_S_AXI_HP1_ARBURST_pin ),
.processing_system7_0_S_AXI_HP1_ARLOCK_pin ( processing_system7_0_S_AXI_HP1_ARLOCK_pin ),
.processing_system7_0_S_AXI_HP1_ARSIZE_pin ( processing_system7_0_S_AXI_HP1_ARSIZE_pin ),
.processing_system7_0_S_AXI_HP1_AWBURST_pin ( processing_system7_0_S_AXI_HP1_AWBURST_pin ),
.processing_system7_0_S_AXI_HP1_AWLOCK_pin ( processing_system7_0_S_AXI_HP1_AWLOCK_pin ),
.processing_system7_0_S_AXI_HP1_AWSIZE_pin ( processing_system7_0_S_AXI_HP1_AWSIZE_pin ),
.processing_system7_0_S_AXI_HP1_ARPROT_pin ( processing_system7_0_S_AXI_HP1_ARPROT_pin ),
.processing_system7_0_S_AXI_HP1_AWPROT_pin ( processing_system7_0_S_AXI_HP1_AWPROT_pin ),
.processing_system7_0_S_AXI_HP1_ARADDR_pin ( processing_system7_0_S_AXI_HP1_ARADDR_pin ),
.processing_system7_0_S_AXI_HP1_AWADDR_pin ( processing_system7_0_S_AXI_HP1_AWADDR_pin ),
.processing_system7_0_S_AXI_HP1_ARCACHE_pin ( processing_system7_0_S_AXI_HP1_ARCACHE_pin ),
.processing_system7_0_S_AXI_HP1_ARLEN_pin ( processing_system7_0_S_AXI_HP1_ARLEN_pin ),
.processing_system7_0_S_AXI_HP1_ARQOS_pin ( processing_system7_0_S_AXI_HP1_ARQOS_pin ),
.processing_system7_0_S_AXI_HP1_AWCACHE_pin ( processing_system7_0_S_AXI_HP1_AWCACHE_pin ),
.processing_system7_0_S_AXI_HP1_AWLEN_pin ( processing_system7_0_S_AXI_HP1_AWLEN_pin ),
.processing_system7_0_S_AXI_HP1_AWQOS_pin ( processing_system7_0_S_AXI_HP1_AWQOS_pin ),
.processing_system7_0_S_AXI_HP1_ARID_pin ( processing_system7_0_S_AXI_HP1_ARID_pin ),
.processing_system7_0_S_AXI_HP1_AWID_pin ( processing_system7_0_S_AXI_HP1_AWID_pin ),
.processing_system7_0_S_AXI_HP1_WID_pin ( processing_system7_0_S_AXI_HP1_WID_pin ),
.processing_system7_0_S_AXI_HP1_WDATA_pin ( processing_system7_0_S_AXI_HP1_WDATA_pin ),
.processing_system7_0_S_AXI_HP1_WSTRB_pin ( processing_system7_0_S_AXI_HP1_WSTRB_pin ),
.processing_system7_0_I2C0_SDA_pin ( processing_system7_0_I2C0_SDA_pin ),
.processing_system7_0_I2C0_SCL_pin ( processing_system7_0_I2C0_SCL_pin ),
.processing_system7_0_GPIO_I_pin ( processing_system7_0_GPIO_I_pin ),
.processing_system7_0_GPIO_O_pin ( processing_system7_0_GPIO_O_pin ),
.processing_system7_0_GPIO_T_pin ( processing_system7_0_GPIO_T_pin )
);
endmodule
|
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Logic Core: PCI Express Megacore Function
// Company: Altera Corporation.
// www.altera.com
// Author: IPBU SIO Group
//
// Description: Altera PCI Express MegaCore function clk phase alignment
// module for S4GX ES silicon
//
// Copyright 2009 Altera Corporation. All rights reserved. This source code
// is highly confidential and proprietary information of Altera and is being
// provided in accordance with and subject to the protections of a
// Non-Disclosure Agreement which governs its use and disclosure. Altera
// products and services are protected under numerous U.S. and foreign patents,
// maskwork rights, copyrights and other intellectual property laws. Altera
// assumes no responsibility or liability arising out of the application or use
// of this source code.
//
// For Best Viewing Set tab stops to 4 spaces.
//
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
module altpcie_pclk_align
(
rst,
clock,
offset,
onestep,
onestep_dir,
PCLK_Master,
PCLK_Slave,
PhaseUpDown,
PhaseStep,
PhaseDone,
AlignLock,
pcie_sw_in,
pcie_sw_out
);
input rst;
input clock;
input [7:0] offset;
input onestep;
input onestep_dir;
input PCLK_Master;
input PCLK_Slave;
input PhaseDone;
output PhaseUpDown;
output PhaseStep;
output AlignLock;
input pcie_sw_in;
output pcie_sw_out;
reg PhaseUpDown;
reg PhaseStep;
reg AlignLock;
localparam DREG_SIZE = 16;
localparam BIAS_ONE = 1;
reg [3:0] align_sm;
localparam INIT = 0;
localparam EVAL = 1;
localparam ADVC = 2;
localparam DELY = 3;
localparam BACK = 4;
localparam ERR = 5;
localparam DONE = 6;
localparam MNUL = 7;
// debug txt
reg [4 * 8 -1 :0] align_sm_txt;
always@(align_sm)
case(align_sm)
INIT: align_sm_txt = "init";
EVAL: align_sm_txt = "eval";
ADVC: align_sm_txt = "advc";
DELY: align_sm_txt = "dely";
BACK: align_sm_txt = "back";
ERR: align_sm_txt = "err";
DONE: align_sm_txt = "done";
MNUL: align_sm_txt = "mnul";
endcase
reg [DREG_SIZE-1: 0] delay_reg;
integer i;
reg all_zero;
reg all_one;
reg chk_req;
wire chk_ack;
reg [4:0] chk_cnt;
reg chk_ack_r;
reg chk_ack_rr;
reg chk_ok;
// controls
reg found_zero; // found all zeros
reg found_meta; // found metastable region
reg found_one; // found all ones
reg [7:0] window_cnt; // count the number of taps between all zero and all ones
reg clr_window_cnt;
reg inc_window_cnt;
reg dec_window_cnt;
reg half_window_cnt;
reg [1:0] retrain_cnt;
reg pcie_sw_r;
reg pcie_sw_rr;
reg pcie_sw_out;
assign chk_ack = chk_cnt[4];
always @ (posedge PCLK_Master or posedge rst)
begin
if (rst)
begin
delay_reg <= {DREG_SIZE{1'b0}};
all_zero <= 1'b1;
all_one <= 1'b0;
chk_cnt <= 0;
end
else
begin
delay_reg[0] <= PCLK_Slave;
for (i = 1; i < DREG_SIZE; i = i + 1)
delay_reg[i] <= delay_reg[i-1];
// discount the first two flops which are sync flops
if (chk_cnt == 5'h10)
begin
all_zero <= ~|delay_reg[DREG_SIZE-1:2];
all_one <= &delay_reg[DREG_SIZE-1:2];
end
// handshake with slow clock
if (chk_req & (chk_cnt == 5'h1f))
chk_cnt <= 0;
else if (chk_cnt == 5'h1f)
chk_cnt <= chk_cnt;
else
chk_cnt <= chk_cnt + 1;
end
end
always @ (posedge clock or posedge rst)
begin
if (rst)
begin
align_sm <= INIT;
chk_req <= 0;
chk_ack_r <= 0;
chk_ack_rr <= 0;
chk_ok <= 0;
found_zero <= 0;
found_meta <= 0;
found_one <= 0;
PhaseUpDown <= 0;
PhaseStep <= 0;
window_cnt <= 8'h00;
clr_window_cnt <= 0;
inc_window_cnt <= 0;
dec_window_cnt <= 0;
half_window_cnt <= 0;
AlignLock <= 0;
retrain_cnt <= 0;
end
else
begin
chk_ack_r <= chk_ack;
chk_ack_rr <= chk_ack_r;
if ((chk_ack_rr == 0) & (chk_ack_r == 1))
chk_ok <= 1;
else
chk_ok <= 0;
if (align_sm == DONE)
AlignLock <= 1'b1;
if (clr_window_cnt)
window_cnt <= offset;
else if (window_cnt == 8'hff)
window_cnt <= window_cnt;
else if (inc_window_cnt)
window_cnt <= window_cnt + 1;
else if (dec_window_cnt & (window_cnt > 0))
window_cnt <= window_cnt - 1;
else if (half_window_cnt)
window_cnt <= {1'b0,window_cnt[7:1]};
// limit the number of retrains
if (retrain_cnt == 2'b11)
retrain_cnt <= retrain_cnt;
else if (align_sm == ERR)
retrain_cnt <= retrain_cnt + 1;
case (align_sm)
INIT:
begin
chk_req <= 1;
align_sm <= EVAL;
clr_window_cnt <= 1;
end
EVAL:
if (chk_ok)
begin
chk_req <= 0;
clr_window_cnt <= 0;
casex ({found_zero,found_meta,found_one})
3'b000 : // init case
begin
if (all_zero)
begin
found_zero <= 1;
PhaseUpDown <= 0;
PhaseStep <= 1;
align_sm <= ADVC;
end
else if (all_one)
begin
found_one <= 1;
PhaseUpDown <= 1;
PhaseStep <= 1;
align_sm <= DELY;
end
else
begin
found_meta <= 1;
PhaseUpDown <= 0;
PhaseStep <= 1;
align_sm <= ADVC;
end
end
3'b010 : // metasable, delay till get all zero
begin
if (all_zero)
begin
found_zero <= 1;
PhaseUpDown <= 0;
PhaseStep <= 1;
align_sm <= ADVC;
inc_window_cnt <= 1;
end
else
begin
PhaseUpDown <= 1;
PhaseStep <= 1;
align_sm <= DELY;
end
end
3'b110 : // look for all one and compute window
begin
if (all_one)
begin
found_one <= 1;
PhaseStep <= 1;
align_sm <= BACK;
if (BIAS_ONE)
begin
clr_window_cnt <= 1;
PhaseUpDown <= 0;
end
else
begin
PhaseUpDown <= 1;
half_window_cnt <= 1;
end
end
else
begin
PhaseUpDown <= 0;
PhaseStep <= 1;
align_sm <= ADVC;
inc_window_cnt <= 1;
end
end
3'b100 : // keep advancing to look for metasable phase
begin
PhaseUpDown <= 0;
PhaseStep <= 1;
align_sm <= ADVC;
if (all_zero == 0) // got either metsable or ones and found the window edge
begin
found_meta <= 1;
inc_window_cnt <= 1;
end
end
3'b001 : // keep delaying to look for metasable phase
begin
PhaseUpDown <= 1;
PhaseStep <= 1;
align_sm <= DELY;
if (all_one == 0) // got either metsable or ones and found the window edge
begin
found_meta <= 1;
inc_window_cnt <= 1;
end
end
3'b011 : // look for all zero and compute window
begin
if (all_zero)
begin
found_zero <= 1;
PhaseStep <= 1;
PhaseUpDown <= 0;
align_sm <= BACK;
if (BIAS_ONE == 0) // if bias to one, go back all the way
half_window_cnt <= 1;
else
inc_window_cnt <= 1;
end
else
begin
PhaseUpDown <= 1;
PhaseStep <= 1;
align_sm <= DELY;
inc_window_cnt <= 1;
end
end
3'b111 : // middling the setup hold window
begin
if (window_cnt > 0)
begin
PhaseStep <= 1;
align_sm <= BACK;
dec_window_cnt <= 1;
end
else
align_sm <= DONE;
end
3'b101 : // error case should never happen
begin
align_sm <= ERR;
clr_window_cnt <= 1;
found_zero <= 0;
found_one <= 0;
found_meta <= 0;
end
endcase
end
ADVC:
begin
inc_window_cnt <= 0;
if (PhaseDone == 0)
begin
PhaseStep <= 0;
chk_req <= 1;
align_sm <= EVAL;
end
end
DELY:
begin
inc_window_cnt <= 0;
if (PhaseDone == 0)
begin
PhaseStep <= 0;
chk_req <= 1;
align_sm <= EVAL;
end
end
BACK:
begin
half_window_cnt <= 0;
dec_window_cnt <= 0;
inc_window_cnt <= 0;
clr_window_cnt <= 0;
if (PhaseDone == 0)
begin
PhaseStep <= 0;
chk_req <= 1;
align_sm <= EVAL;
end
end
DONE:
begin
if (onestep) // manual adjust
begin
align_sm <= MNUL;
PhaseStep <= 1;
PhaseUpDown <= onestep_dir;
end
end
MNUL:
if (PhaseDone == 0)
begin
PhaseStep <= 0;
align_sm <= DONE;
end
ERR:
begin
clr_window_cnt <= 0;
align_sm <= INIT;
end
default:
align_sm <= INIT;
endcase
end
end
// synchronization for pcie_sw
always @ (posedge PCLK_Master or posedge rst)
begin
if (rst)
begin
pcie_sw_r <= 0;
pcie_sw_rr <= 0;
pcie_sw_out <= 0;
end
else
begin
pcie_sw_r <= pcie_sw_in;
pcie_sw_rr <= pcie_sw_r;
pcie_sw_out <= pcie_sw_rr;
end
end
endmodule
|
module MemAlu(
/* verilator lint_off UNUSED */
clk,
mode,
baseAddr,
idxAddr,
idxDisp,
outAddr
);
input clk;
input[2:0] mode;
input[63:0] baseAddr;
input[31:0] idxAddr;
input[31:0] idxDisp;
output[63:0] outAddr;
reg[31:0] tIdxAddr;
reg[63:0] tIdxAddr2;
reg[63:0] tOutAddr;
parameter[2:0] MD_NONE = 3'b000;
parameter[2:0] MD_BYTE = 3'b001;
parameter[2:0] MD_WORD = 3'b010;
parameter[2:0] MD_DWORD = 3'b011;
parameter[2:0] MD_QWORD = 3'b100;
parameter[2:0] MD_OWORD = 3'b101;
parameter[2:0] MD_MOV = 3'b111;
parameter[63:0] NULL_ADDR = 64'h0000_0000_0000_0000;
parameter[63:0] NEG_ADDR = 64'hFFFF_FFFF_0000_0000;
always @ (mode) begin
tIdxAddr = idxAddr+idxDisp;
// tIdxAddr2 = tIdxAddr[31] ?
// (tIdxAddr|NEG_ADDR) :
// (tIdxAddr|NULL_ADDR);
tIdxAddr2[31:0] = tIdxAddr;
tIdxAddr2[63:32] = tIdxAddr[31] ?
32'hFFFF_FFFF :
32'h0000_0000 ;
case(mode)
MD_BYTE: begin
tOutAddr = baseAddr+tIdxAddr2;
end
MD_WORD: begin
tOutAddr = baseAddr+tIdxAddr2*2;
end
MD_DWORD: begin
tOutAddr = baseAddr+tIdxAddr2*4;
end
MD_QWORD: begin
tOutAddr = baseAddr+tIdxAddr2*8;
end
MD_OWORD: begin
tOutAddr = baseAddr+tIdxAddr2*16;
end
MD_MOV: begin
tOutAddr = baseAddr;
end
default: begin
tOutAddr = NULL_ADDR;
end
endcase
outAddr = tOutAddr;
end
//always @ (posedge clk) begin
// outAddr <= tOutAddr;
//end
endmodule
|
`timescale 1ns/10ps
module tb_mathsop;
reg clock, reset;
reg [15:0] x;
wire [15:0] ym1, ym2, yb1, yb2, yc1, yc2;
initial begin
$dumpfile("vcd/mathsop.vcd");
$dumpvars(0, tb_mathsop);
end
initial begin
$from_myhdl(clock, reset, x);
$to_myhdl(ym1, ym2, yb1, yb2, yc1, yc2);
end
/** the myhdl verilog */
mm_sop1 dut_myhdl1(.clock(clock), .reset(reset),
.x(x), .y(ym1));
mm_sop2 dut_myhdl2(.clock(clock), .reset(reset),
.x(x), .y(ym2));
/** the bluespec verilog (wrapper) */
mkSOP1 dut_bsv1(.CLK(clock), .RST_N(reset),
.write_x(x), .read(yb1));
mkSOP2 dut_bsv2(.CLK(clock), .RST_N(reset),
.write_x(x), .read(yb2));
/** the chisel verilog */
// chisel use active high reset
wire mc_reset = ~reset;
mc_sop1 dut_chisel1(.clk(clock), .reset(mc_reset),
.io_x(x), .io_y(yc1));
//mc_sop2 dut_chisel2(.clk(clock), .reset(mc_reset),
// .io_x(x), .io_y(yc1));
endmodule
|
//#############################################################################
//# Purpose: MIO Transmit Datapath #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module mtx # ( parameter PW = 104, // fifo width
parameter AW = 32, // fifo width
parameter IOW = 8, // I./O data width
parameter FIFO_DEPTH = 16, // fifo depth
parameter TARGET = "GENERIC" // fifo target
)
(// reset, clk, cfg
input clk, // main core clock
input io_clk, // clock for tx logic
input nreset, // async active low reset
input tx_en, // transmit enable
input ddr_mode, // configure mio in ddr mode
input lsbfirst, // send bits lsb first
input emode, //emesh mode
input [1:0] iowidth,//input width
// status
output tx_empty, // tx fifo is empty
output tx_full, // tx fifo is full (should never happen!)
output tx_prog_full,// tx is getting full (stop sending!)
// data to transmit
input access_in, // fifo data valid
input [PW-1:0] packet_in, // fifo packet
output wait_out, // wait pushback for fifo
// IO interface (90 deg clock supplied outside this block)
output tx_access, // access signal for IO
output [IOW-1:0] tx_packet, // packet for IO
input tx_wait // pushback from IO
);
//###############
//# LOCAL WIRES
//###############
// End of automatics
/*AUTOINPUT*/
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [63:0] io_packet; // From mtx_fifo of mtx_fifo.v
wire [7:0] io_valid; // From mtx_fifo of mtx_fifo.v
wire io_wait; // From mtx_io of mtx_io.v
// End of automatics
//########################################
//# Synchronization FIFO
//########################################
mtx_fifo #(.PW(PW),
.AW(AW),
.FIFO_DEPTH(FIFO_DEPTH),
.TARGET(TARGET))
mtx_fifo (/*AUTOINST*/
// Outputs
.wait_out (wait_out),
.io_packet (io_packet[63:0]),
.io_valid (io_valid[7:0]),
// Inputs
.clk (clk),
.io_clk (io_clk),
.nreset (nreset),
.tx_en (tx_en),
.emode (emode),
.access_in (access_in),
.packet_in (packet_in[PW-1:0]),
.io_wait (io_wait));
//########################################
//# IO Logic (DDR, shift register)
//########################################
mtx_io #(.IOW(IOW))
mtx_io (/*AUTOINST*/
// Outputs
.tx_packet (tx_packet[IOW-1:0]),
.tx_access (tx_access),
.io_wait (io_wait),
// Inputs
.nreset (nreset),
.io_clk (io_clk),
.ddr_mode (ddr_mode),
.iowidth (iowidth[1:0]),
.tx_wait (tx_wait),
.io_valid (io_valid[7:0]),
.io_packet (io_packet[IOW-1:0]));
endmodule // mtx
// Local Variables:
// verilog-library-directories:("." "../../common/hdl")
// End:
|
// _________________________________________________________________________
//
// Author: Ajay Dubey, IP Apps engineering
// __________________________________________________________________________
module avalon_st_traffic_controller (
input wire avl_mm_read ,
input wire avl_mm_write ,
output wire avl_mm_waitrequest,
input wire[23:0] avl_mm_baddress ,
output wire[31:0] avl_mm_readdata ,
input wire[31:0] avl_mm_writedata ,
input wire clk_in ,
input wire reset_n ,
input wire[39:0] mac_rx_status_data ,
input wire mac_rx_status_valid ,
input wire mac_rx_status_error ,
input wire stop_mon ,
output wire mon_active ,
output wire mon_done ,
output wire mon_error ,
output wire[63:0] avl_st_tx_data ,
output wire[2:0] avl_st_tx_empty ,
output wire avl_st_tx_eop ,
output wire avl_st_tx_error ,
input wire avl_st_tx_rdy ,
output wire avl_st_tx_sop ,
output wire avl_st_tx_val ,
input wire[63:0] avl_st_rx_data ,
input wire[2:0] avl_st_rx_empty ,
input wire avl_st_rx_eop ,
input wire [5:0] avl_st_rx_error ,
output wire avl_st_rx_rdy ,
input wire avl_st_rx_sop ,
input wire avl_st_rx_val
);
// ________________________________________________
// traffic generator
wire avl_st_rx_lpmx_mon_eop;
wire[5:0] avl_st_rx_lpmx_mon_error;
wire avl_st_rx_mon_lpmx_rdy;
wire avl_st_rx_lpmx_mon_sop;
wire avl_st_rx_lpmx_mon_val;
wire[63:0] avl_st_rx_lpmx_mon_data;
wire[2:0] avl_st_rx_lpmx_mon_empty;
wire[23:0] avl_mm_address = {2'b00, avl_mm_baddress[23:2]}; // byte to word address
wire[31:0] avl_mm_readdata_gen, avl_mm_readdata_mon;
wire blk_sel_gen = (avl_mm_address[23:16] == 8'd0);
wire blk_sel_mon = (avl_mm_address[23:16] == 8'd1);
wire waitrequest_gen, waitrequest_mon;
assign avl_mm_waitrequest = blk_sel_gen?waitrequest_gen:blk_sel_mon? waitrequest_mon:1'b0;
assign avl_mm_readdata = blk_sel_gen? avl_mm_readdata_gen:blk_sel_mon? avl_mm_readdata_mon:32'd0;
wire gen_lpbk;
wire sync_reset;
// _______________________________________________________________
traffic_reset_sync reset_sync
// _______________________________________________________________
( .clk (clk_in),
.data_in (1'b0),
.reset (~reset_n),
.data_out (sync_reset)
);
// _______________________________________________________________
avalon_st_gen GEN (
// _______________________________________________________________
.clk (clk_in), // Tx clock
.reset (sync_reset), // Reset signal
.address (avl_mm_address[7:0]), // Avalon-MM Address
.write (avl_mm_write & blk_sel_gen), // Avalon-MM Write Strobe
.writedata (avl_mm_writedata), // Avalon-MM Write Data
.read (avl_mm_read & blk_sel_gen), // Avalon-MM Read Strobe
.readdata (avl_mm_readdata_gen), // Avalon-MM Read Data
.waitrequest (waitrequest_gen),
.tx_data (avl_st_tx_data), // Avalon-ST Data
.tx_valid (avl_st_tx_val), // Avalon-ST Valid
.tx_sop (avl_st_tx_sop), // Avalon-ST StartOfPacket
.tx_eop (avl_st_tx_eop), // Avalon-ST EndOfPacket
.tx_empty (avl_st_tx_empty), // Avalon-ST Empty
.tx_error (avl_st_tx_error), // Avalon-ST Error
.tx_ready (avl_st_tx_rdy)
);
// ___________________________________________________________________
avalon_st_mon MON (
// ___________________________________________________________________
.clk (clk_in ), // RX clock
.reset (sync_reset ), // Reset Signal
.avalon_mm_address (avl_mm_address[7:0]), // Avalon-MM Address
.avalon_mm_write (avl_mm_write & blk_sel_mon), // Avalon-MM Write Strobe
.avalon_mm_writedata (avl_mm_writedata), // Avalon-MM write Data
.avalon_mm_read (avl_mm_read & blk_sel_mon), // Avalon-MM Read Strobe
.avalon_mm_waitrequest (waitrequest_mon),
.avalon_mm_readdata (avl_mm_readdata_mon), // Avalon-MM Read Data
.mac_rx_status_valid (mac_rx_status_valid),
.mac_rx_status_error (mac_rx_status_error),
.mac_rx_status_data (mac_rx_status_data),
.stop_mon (stop_mon),
.mon_active (mon_active),
.mon_done (mon_done),
.mon_error (mon_error),
.gen_lpbk (gen_lpbk),
.avalon_st_rx_data (avl_st_rx_data), // Avalon-ST RX Data
.avalon_st_rx_valid (avl_st_rx_val), // Avalon-ST RX Valid
.avalon_st_rx_sop (avl_st_rx_sop), // Avalon-ST RX StartOfPacket
.avalon_st_rx_eop (avl_st_rx_eop), // Avalon-ST RX EndOfPacket
.avalon_st_rx_empty (avl_st_rx_empty), // Avalon-ST RX Data Empty
.avalon_st_rx_error (avl_st_rx_error), // Avalon-ST RX Error
.avalon_st_rx_ready (avl_st_rx_rdy) // Avalon-ST RX Ready Output
);
// ___________________________________________________________________
endmodule
// ____________________________________________________________________________________________
// reset synchronizer
// ____________________________________________________________________________________________
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module traffic_reset_sync ( clk, data_in, reset, data_out) ;
output data_out;
input clk;
input data_in;
input reset;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-from \"*\"} CUT=ON ; PRESERVE_REGISTER=ON ; SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg data_out /* synthesis ALTERA_ATTRIBUTE = "PRESERVE_REGISTER=ON ; SUPPRESS_DA_RULE_INTERNAL=R101" */;
always @(posedge clk or posedge reset)
begin
if (reset == 1) data_in_d1 <= 1;
else data_in_d1 <= data_in;
end
always @(posedge clk or posedge reset)
begin
if (reset == 1) data_out <= 1;
else data_out <= data_in_d1;
end
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: ddr_phy_v2_3_phy_ocd_po_cntlr.v
// /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $
// \ \ / \ Date Created: Aug 03 2009
// \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose: Manipulates phaser out stg2f and stg3 on behalf of
// scan and DQS centering.
//
// Maintains a shadow of the phaser out stg2f and stg3 tap settings.
// The stg3 shadow is 6 bits, just like the phaser out. stg2f is
// 8 bits. This allows the po_cntlr to track how far past the stg2f
// saturation points we have gone when stepping to the limits of stg3.
// This way we're can stay in sync when we step back from the saturation
// limits.
//
// Looks at the edge values and determines which case has been
// detected by the scan. Uses the results to drive the centering.
//
// Main state machine waits until it sees reset_scan go to zero. While
// waiting it is writing the initialzation values to the stg2 and stg3
// shadows. When reset_scan goes low, taps_set is pulsed. This
// tells the sampling block to begin sampling. When the sampling
// block has finished sampling this setting of the phaser out taps,
// is signals by setting samp_done. When the main state machine
// sees samp_done it sets the next value in the phaser out and
// waits for the phaser out to be ready before beginning the next
// sample.
//
// Turns out phy_init is sensitive to the length of the ocal_num_samples_done
// pulse. Something like a precharge and activate time. Added feature
// to resume_wait to wait at least 32 cycles between assertion and
// subsequent deassertion of ocal_num_samples_done.
//
// Also turns out phy_init needs help to get into consistent
// starting state for complex cal. This can be done by preseting
// ocal_num_samples_done to one. Then waiting for 32 fabric clocks,
// turn off _done and then assert _resume.
//
// Scanning algorithm.
//
// Phaser manipulation algoritm.
//
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v2_3_ddr_phy_ocd_po_cntlr #
(parameter DQS_CNT_WIDTH = 3,
parameter DQS_WIDTH = 8,
parameter nCK_PER_CLK = 4,
parameter TCQ = 100)
(/*AUTOARG*/
// Outputs
scan_done, ocal_num_samples_done_r, oclkdelay_center_calib_start,
oclkdelay_center_calib_done, oclk_center_write_resume, ocd2stg2_inc,
ocd2stg2_dec, ocd2stg3_inc, ocd2stg3_dec, stg3, simp_stg3_final,
cmplx_stg3_final, simp_stg3_final_sel, ninety_offsets,
scanning_right, ocd_ktap_left, ocd_ktap_right, ocd_edge_detect_rdy,
taps_set, use_noise_window, ocal_scan_win_not_found,
// Inputs
clk, rst, reset_scan, oclkdelay_init_val, lim2ocal_stg3_right_lim,
lim2ocal_stg3_left_lim, complex_oclkdelay_calib_start,
po_counter_read_val, oclkdelay_calib_cnt, mmcm_edge_detect_done,
mmcm_lbclk_edge_aligned, poc_backup, phy_rddata_en_3, zero2fuzz,
fuzz2zero, oneeighty2fuzz, fuzz2oneeighty, z2f, f2z, o2f, f2o,
scan_right, samp_done, wl_po_fine_cnt_sel, po_rdy
);
input clk;
input rst;
input reset_scan;
reg scan_done_r;
output scan_done;
assign scan_done = scan_done_r;
output [5:0] simp_stg3_final_sel;
reg cmplx_samples_done_ns, cmplx_samples_done_r;
always @(posedge clk) cmplx_samples_done_r <= #TCQ cmplx_samples_done_ns;
output ocal_num_samples_done_r;
assign ocal_num_samples_done_r = cmplx_samples_done_r;
// Write Level signals during OCLKDELAY calibration
input [5:0] oclkdelay_init_val;
input [5:0] lim2ocal_stg3_right_lim;
input [5:0] lim2ocal_stg3_left_lim;
input complex_oclkdelay_calib_start;
reg oclkdelay_center_calib_start_ns, oclkdelay_center_calib_start_r;
always @(posedge clk) oclkdelay_center_calib_start_r <= #TCQ oclkdelay_center_calib_start_ns;
output oclkdelay_center_calib_start;
assign oclkdelay_center_calib_start = oclkdelay_center_calib_start_r;
reg oclkdelay_center_calib_done_ns, oclkdelay_center_calib_done_r;
always @(posedge clk) oclkdelay_center_calib_done_r <= #TCQ oclkdelay_center_calib_done_ns;
output oclkdelay_center_calib_done;
assign oclkdelay_center_calib_done = oclkdelay_center_calib_done_r;
reg oclk_center_write_resume_ns, oclk_center_write_resume_r;
always @(posedge clk) oclk_center_write_resume_r <= #TCQ oclk_center_write_resume_ns;
output oclk_center_write_resume;
assign oclk_center_write_resume = oclk_center_write_resume_r;
reg ocd2stg2_inc_r, ocd2stg2_dec_r, ocd2stg3_inc_r, ocd2stg3_dec_r;
output ocd2stg2_inc, ocd2stg2_dec, ocd2stg3_inc, ocd2stg3_dec;
assign ocd2stg2_inc = ocd2stg2_inc_r;
assign ocd2stg2_dec = ocd2stg2_dec_r;
assign ocd2stg3_inc = ocd2stg3_inc_r;
assign ocd2stg3_dec = ocd2stg3_dec_r;
// Remember, two stage 2 steps for every stg 3 step. And we need a sign bit.
reg [8:0] stg2_ns, stg2_r;
always @(posedge clk) stg2_r <= #TCQ stg2_ns;
reg [5:0] stg3_ns, stg3_r;
always @(posedge clk) stg3_r <= #TCQ stg3_ns;
output [5:0] stg3;
assign stg3 = stg3_r;
input [5:0] wl_po_fine_cnt_sel;
input [8:0] po_counter_read_val;
reg [5:0] po_counter_read_val_r;
always @(posedge clk) po_counter_read_val_r <= #TCQ po_counter_read_val[5:0];
reg [DQS_WIDTH*6-1:0] simp_stg3_final_ns, simp_stg3_final_r, cmplx_stg3_final_ns, cmplx_stg3_final_r;
always @(posedge clk) simp_stg3_final_r <= #TCQ simp_stg3_final_ns;
always @(posedge clk) cmplx_stg3_final_r <= #TCQ cmplx_stg3_final_ns;
output [DQS_WIDTH*6-1:0] simp_stg3_final, cmplx_stg3_final;
assign simp_stg3_final = simp_stg3_final_r;
assign cmplx_stg3_final = cmplx_stg3_final_r;
input [DQS_CNT_WIDTH:0] oclkdelay_calib_cnt;
wire [DQS_WIDTH*6-1:0] simp_stg3_final_shft = simp_stg3_final_r >> oclkdelay_calib_cnt * 6;
assign simp_stg3_final_sel = simp_stg3_final_shft[5:0];
wire [5:0] stg3_init = complex_oclkdelay_calib_start ? simp_stg3_final_sel : oclkdelay_init_val;
wire signed [8:0] stg2_steps = stg3_r > stg3_init
? -9'sd2 * $signed({3'b0, (stg3_r - stg3_init)})
: 9'sd2 * $signed({3'b0, (stg3_init - stg3_r)});
wire signed [8:0] stg2_target_ns = $signed({3'b0, wl_po_fine_cnt_sel}) + stg2_steps;
reg signed [8:0] stg2_target_r;
always @ (posedge clk) stg2_target_r <= #TCQ stg2_target_ns;
reg [5:0] stg2_final_ns, stg2_final_r;
always @(posedge clk) stg2_final_r <= #TCQ stg2_final_ns;
always @(*) stg2_final_ns = stg2_target_r[8] == 1'b1
? 6'd0
: stg2_target_r > 9'd63
? 6'd63
: stg2_target_r[5:0];
wire final_stg2_inc = stg2_final_r > po_counter_read_val_r;
wire final_stg2_dec = stg2_final_r < po_counter_read_val_r;
wire left_lim = stg3_r == lim2ocal_stg3_left_lim;
wire right_lim = stg3_r == lim2ocal_stg3_right_lim;
reg [1:0] ninety_offsets_ns, ninety_offsets_r;
always @(posedge clk) ninety_offsets_r <= #TCQ ninety_offsets_ns;
output [1:0] ninety_offsets;
assign ninety_offsets = ninety_offsets_r;
reg scanning_right_ns, scanning_right_r;
always @(posedge clk) scanning_right_r <= #TCQ scanning_right_ns;
output scanning_right;
assign scanning_right = scanning_right_r;
reg ocd_ktap_left_ns, ocd_ktap_left_r, ocd_ktap_right_ns, ocd_ktap_right_r;
always @(posedge clk) ocd_ktap_left_r <= #TCQ ocd_ktap_left_ns;
always @(posedge clk) ocd_ktap_right_r <= #TCQ ocd_ktap_right_ns;
output ocd_ktap_left, ocd_ktap_right;
assign ocd_ktap_left = ocd_ktap_left_r;
assign ocd_ktap_right = ocd_ktap_right_r;
reg ocd_edge_detect_rdy_ns, ocd_edge_detect_rdy_r;
always @(posedge clk) ocd_edge_detect_rdy_r <= #TCQ ocd_edge_detect_rdy_ns;
output ocd_edge_detect_rdy;
assign ocd_edge_detect_rdy = ocd_edge_detect_rdy_r;
input mmcm_edge_detect_done;
input mmcm_lbclk_edge_aligned;
input poc_backup;
reg poc_backup_ns, poc_backup_r;
always @(posedge clk) poc_backup_r <= #TCQ poc_backup_ns;
reg taps_set_r;
output taps_set;
assign taps_set = taps_set_r;
input phy_rddata_en_3;
input [5:0] zero2fuzz, fuzz2zero, oneeighty2fuzz, fuzz2oneeighty;
input z2f, f2z, o2f, f2o;
wire zero = f2z && z2f;
wire noise = z2f && f2o;
wire oneeighty = f2o && o2f;
reg win_not_found;
reg [1:0] ninety_offsets_final;
reg [5:0] left, right, current_edge;
always @(*) begin
left = lim2ocal_stg3_left_lim;
right = lim2ocal_stg3_right_lim;
ninety_offsets_final = 2'd0;
win_not_found = 1'b0;
if (zero) begin
left = fuzz2zero;
right = zero2fuzz;
end
else if (noise) begin
left = zero2fuzz;
right = fuzz2oneeighty;
ninety_offsets_final = 2'd1;
end
else if (oneeighty) begin
left = fuzz2oneeighty;
right = oneeighty2fuzz;
ninety_offsets_final = 2'd2;
end
else if (z2f) begin
right = zero2fuzz;
end
else if (f2o) begin
left = fuzz2oneeighty;
ninety_offsets_final = 2'd2;
end
else if (f2z) begin
left = fuzz2zero;
end
else win_not_found = 1'b1;
current_edge = ocd_ktap_left_r ? left : right;
end // always @ begin
output use_noise_window;
assign use_noise_window = ninety_offsets == 2'd1;
reg ocal_scan_win_not_found_ns, ocal_scan_win_not_found_r;
always @(posedge clk) ocal_scan_win_not_found_r <= #TCQ ocal_scan_win_not_found_ns;
output ocal_scan_win_not_found;
assign ocal_scan_win_not_found = ocal_scan_win_not_found_r;
wire inc_po_ns = current_edge > stg3_r;
wire dec_po_ns = current_edge < stg3_r;
reg inc_po_r, dec_po_r;
always @(posedge clk) inc_po_r <= #TCQ inc_po_ns;
always @(posedge clk) dec_po_r <= #TCQ dec_po_ns;
input scan_right;
wire left_stop = left_lim || scan_right;
wire right_stop = right_lim || o2f;
reg [4:0] resume_wait_ns, resume_wait_r;
always @(posedge clk) resume_wait_r <= #TCQ resume_wait_ns;
wire resume_wait = |resume_wait_r;
reg po_done_ns, po_done_r;
always @(posedge clk) po_done_r <= #TCQ po_done_ns;
input samp_done;
input po_rdy;
reg up_ns, up_r;
always @(posedge clk) up_r <= #TCQ up_ns;
reg [1:0] two_ns, two_r;
always @(posedge clk) two_r <= #TCQ two_ns;
/* wire stg2_zero = ~|stg2_r;
wire [8:0] stg2_2_zero = stg2_r[8] ? 9'd0
: stg2_r > 9'd63
? 9'd63
: stg2_r; */
reg [3:0] sm_ns, sm_r;
always @(posedge clk) sm_r <= #TCQ sm_ns;
(* dont_touch = "true" *) reg phy_rddata_en_3_second_ns, phy_rddata_en_3_second_r;
always @(posedge clk) phy_rddata_en_3_second_r <= #TCQ phy_rddata_en_3_second_ns;
always @(*) phy_rddata_en_3_second_ns = ~reset_scan && (phy_rddata_en_3
? ~phy_rddata_en_3_second_r
: phy_rddata_en_3_second_r);
(* dont_touch = "true" *) wire use_samp_done = nCK_PER_CLK == 2 ? phy_rddata_en_3 && phy_rddata_en_3_second_r : phy_rddata_en_3;
reg po_center_wait;
reg po_slew;
reg po_finish_scan;
always @(*) begin
// Default next state assignments.
cmplx_samples_done_ns = cmplx_samples_done_r;
cmplx_stg3_final_ns = cmplx_stg3_final_r;
scanning_right_ns = scanning_right_r;
ninety_offsets_ns = ninety_offsets_r;
ocal_scan_win_not_found_ns = ocal_scan_win_not_found_r;
ocd_edge_detect_rdy_ns = ocd_edge_detect_rdy_r;
ocd_ktap_left_ns = ocd_ktap_left_r;
ocd_ktap_right_ns = ocd_ktap_right_r;
ocd2stg2_inc_r = 1'b0;
ocd2stg2_dec_r = 1'b0;
ocd2stg3_inc_r = 1'b0;
ocd2stg3_dec_r = 1'b0;
oclkdelay_center_calib_start_ns = oclkdelay_center_calib_start_r;
oclkdelay_center_calib_done_ns = 1'b0;
oclk_center_write_resume_ns = oclk_center_write_resume_r;
po_center_wait = 1'b0;
po_done_ns = po_done_r;
po_finish_scan = 1'b0;
po_slew = 1'b0;
poc_backup_ns = poc_backup_r;
scan_done_r = 1'b0;
simp_stg3_final_ns = simp_stg3_final_r;
sm_ns = sm_r;
taps_set_r = 1'b0;
up_ns = up_r;
stg2_ns = stg2_r;
stg3_ns = stg3_r;
two_ns = two_r;
resume_wait_ns = resume_wait_r;
if (rst == 1'b1) begin
// RESET next states
cmplx_samples_done_ns = 1'b0;
ocal_scan_win_not_found_ns = 1'b0;
ocd_ktap_left_ns = 1'b0;
ocd_ktap_right_ns = 1'b0;
ocd_edge_detect_rdy_ns = 1'b0;
oclk_center_write_resume_ns = 1'b0;
oclkdelay_center_calib_start_ns = 1'b0;
po_done_ns = 1'b1;
resume_wait_ns = 5'd0;
sm_ns = /*AK("READY")*/4'd0;
end else
// State based actions and next states.
case (sm_r)
/*AL("READY")*/4'd0:begin
poc_backup_ns = 1'b0;
stg2_ns = {3'b0, wl_po_fine_cnt_sel};
stg3_ns = stg3_init;
scanning_right_ns = 1'b0;
if (complex_oclkdelay_calib_start) cmplx_samples_done_ns = 1'b1;
if (!reset_scan && ~resume_wait) begin
cmplx_samples_done_ns = 1'b0;
ocal_scan_win_not_found_ns = 1'b0;
taps_set_r = 1'b1;
sm_ns = /*AK("SAMPLING")*/4'd1;
end
end
/*AL("SAMPLING")*/4'd1:begin
if (samp_done && use_samp_done) begin
if (complex_oclkdelay_calib_start) cmplx_samples_done_ns = 1'b1;
scanning_right_ns = scanning_right_r || left_stop;
if (right_stop && scanning_right_r) begin
oclkdelay_center_calib_start_ns = 1'b1;
ocd_ktap_left_ns = 1'b1;
ocal_scan_win_not_found_ns = win_not_found;
sm_ns = /*AK("SLEW_PO")*/4'd3;
end else begin
if (scanning_right_ns) ocd2stg3_inc_r = 1'b1;
else ocd2stg3_dec_r = 1'b1;
sm_ns = /*AK("PO_WAIT")*/4'd2;
end
end
end
/*AL("PO_WAIT")*/4'd2:begin
if (po_done_r && ~resume_wait) begin
taps_set_r = 1'b1;
sm_ns = /*AK("SAMPLING")*/4'd1;
cmplx_samples_done_ns = 1'b0;
end
end
/*AL("SLEW_PO")*/4'd3:begin
po_slew = 1'b1;
ninety_offsets_ns = |ninety_offsets_final ? 2'b01 : 2'b00;
if (~resume_wait) begin
if (po_done_r) begin
if (inc_po_r) ocd2stg3_inc_r = 1'b1;
else if (dec_po_r) ocd2stg3_dec_r = 1'b1;
else if (~resume_wait) begin
cmplx_samples_done_ns = 1'b0;
sm_ns = /*AK("ALIGN_EDGES")*/4'd4;
oclk_center_write_resume_ns = 1'b1;
end
end // if (po_done)
end
end // case: 3'd3
/*AL("ALIGN_EDGES")*/4'd4:
if (~resume_wait) begin
if (mmcm_edge_detect_done) begin
ocd_edge_detect_rdy_ns = 1'b0;
if (ocd_ktap_left_r) begin
ocd_ktap_left_ns = 1'b0;
ocd_ktap_right_ns = 1'b1;
oclk_center_write_resume_ns = 1'b0;
sm_ns = /*AK("SLEW_PO")*/4'd3;
end else if (ocd_ktap_right_r) begin
ocd_ktap_right_ns = 1'b0;
sm_ns = /*AK("WAIT_ONE")*/4'd5;
end else if (~mmcm_lbclk_edge_aligned) begin
sm_ns = /*AK("DQS_STOP_WAIT")*/4'd6;
oclk_center_write_resume_ns = 1'b0;
end else begin
if (ninety_offsets_r != ninety_offsets_final && ocd_edge_detect_rdy_r) begin
ninety_offsets_ns = ninety_offsets_r + 2'b01;
sm_ns = /*AK("WAIT_ONE")*/4'd5;
end else begin
oclk_center_write_resume_ns = 1'b0;
poc_backup_ns = poc_backup;
// stg2_ns = stg2_2_zero;
sm_ns = /*AK("FINISH_SCAN")*/4'd8;
end
end // else: !if(~mmcm_lbclk_edge_aligned)
end else ocd_edge_detect_rdy_ns = 1'b1;
end // if (~resume_wait)
/*AL("WAIT_ONE")*/4'd5:
sm_ns = /*AK("ALIGN_EDGES")*/4'd4;
/*AL("DQS_STOP_WAIT")*/4'd6:
if (~resume_wait) begin
ocd2stg3_dec_r = 1'b1;
sm_ns = /*AK("CENTER_PO_WAIT")*/4'd7;
end
/*AL("CENTER_PO_WAIT")*/4'd7: begin
po_center_wait = 1'b1; // Kludge to get around limitation of the AUTOs symbols.
if (po_done_r) begin
sm_ns = /*AK("ALIGN_EDGES")*/4'd4;
oclk_center_write_resume_ns = 1'b1;
end
end
/*AL("FINISH_SCAN")*/4'd8: begin
po_finish_scan = 1'b1;
if (resume_wait_r == 5'd1) begin
if (~poc_backup_r) begin
oclkdelay_center_calib_done_ns = 1'b1;
oclkdelay_center_calib_start_ns = 1'b0;
end
end
if (~resume_wait) begin
if (po_rdy)
if (poc_backup_r) begin
ocd2stg3_inc_r = 1'b1;
poc_backup_ns = 1'b0;
end
else if (~final_stg2_inc && ~final_stg2_dec) begin
if (complex_oclkdelay_calib_start) cmplx_stg3_final_ns[oclkdelay_calib_cnt*6+:6] = stg3_r;
else simp_stg3_final_ns[oclkdelay_calib_cnt*6+:6] = stg3_r;
sm_ns = /*AK("READY")*/4'd0;
scan_done_r = 1'b1;
end else begin
ocd2stg2_inc_r = final_stg2_inc;
ocd2stg2_dec_r = final_stg2_dec;
end
end // if (~resume_wait)
end // case: 4'd8
endcase // case (sm_r)
if (ocd2stg3_inc_r) begin
stg3_ns = stg3_r + 6'h1;
up_ns = 1'b0;
end
if (ocd2stg3_dec_r) begin
stg3_ns = stg3_r - 6'h1;
up_ns = 1'b1;
end
if (ocd2stg3_inc_r || ocd2stg3_dec_r) begin
po_done_ns = 1'b0;
two_ns = 2'b00;
end
if (~po_done_r)
if (po_rdy)
if (two_r == 2'b10 || po_center_wait || po_slew || po_finish_scan) po_done_ns = 1'b1;
else begin
two_ns = two_r + 2'b1;
if (up_r) begin
stg2_ns = stg2_r + 9'b1;
if (stg2_r >= 9'd0 && stg2_r < 9'd63) ocd2stg2_inc_r = 1'b1;
end else begin
stg2_ns = stg2_r - 9'b1;
if (stg2_r > 9'd0 && stg2_r <= 9'd63) ocd2stg2_dec_r = 1'b1;
end
end // else: !if(two_r == 2'b10)
if (ocd_ktap_left_ns && ~ocd_ktap_left_r) resume_wait_ns = 5'b1;
else if (oclk_center_write_resume_ns ^ oclk_center_write_resume_r) resume_wait_ns = 5'd15;
else if (cmplx_samples_done_ns & ~cmplx_samples_done_r ||
complex_oclkdelay_calib_start & reset_scan ||
poc_backup_r & ocd2stg3_inc_r) resume_wait_ns = 5'd31;
else if (|resume_wait_r) resume_wait_ns = resume_wait_r - 5'd1;
end // always @ begin
endmodule // mig_7series_v2_3_ddr_phy_ocd_po_cntlr
// Local Variables:
// verilog-autolabel-prefix: "4'd"
// End:
|
//////////////////////////////////////////////////////////////////////////////////
// AXI4LiteSlaveInterfaceReadChannel for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Kibin Park <[email protected]>
// Yong Ho Song <[email protected]>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Kibin Park <[email protected]>
//
// Project Name: Cosmos OpenSSD
// Design Name: AXI4Lite slave interface read channel
// Module Name: AXI4LiteSlaveInterfaceReadChannel
// File Name: AXI4LiteSlaveInterfaceReadChannel.v
//
// Version: v1.0.0
//
// Description: Read channel control for AXI4-Lite compliant slave interface
//
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module AXI4LiteSlaveInterfaceReadChannel
#
(
parameter AddressWidth = 32,
parameter DataWidth = 32
)
(
ACLK ,
ARESETN ,
ARVALID ,
ARREADY ,
ARADDR ,
ARPROT ,
RVALID ,
RREADY ,
RDATA ,
RRESP ,
oReadAddress ,
iReadData ,
oReadValid ,
iReadAck
);
input ACLK ;
input ARESETN ;
input ARVALID ;
output ARREADY ;
input [AddressWidth - 1:0] ARADDR ;
input [2:0] ARPROT ;
output RVALID ;
input RREADY ;
output [DataWidth - 1:0] RDATA ;
output [1:0] RRESP ;
output [AddressWidth - 1:0] oReadAddress ;
input [DataWidth - 1:0] iReadData ;
output oReadValid ;
input iReadAck ;
reg [AddressWidth - 1:0] rReadAddress ;
reg [DataWidth - 1:0] rReadData ;
localparam State_Idle = 2'b00;
localparam State_INCMDREQ = 2'b01;
localparam State_AXIRRESP = 2'b11;
reg [1:0] rCurState ;
reg [1:0] rNextState ;
always @ (posedge ACLK)
if (!ARESETN)
rCurState <= State_Idle;
else
rCurState <= rNextState;
always @ (*)
case (rCurState)
State_Idle:
rNextState <= (ARVALID)?State_INCMDREQ:State_Idle;
State_INCMDREQ:
rNextState <= (iReadAck)?State_AXIRRESP:State_INCMDREQ;
State_AXIRRESP:
rNextState <= (RREADY)?State_Idle:State_AXIRRESP;
default:
rNextState <= State_Idle;
endcase
assign ARREADY = (rCurState == State_Idle);
assign RVALID = (rCurState == State_AXIRRESP);
assign oReadValid = (rCurState == State_INCMDREQ);
always @ (posedge ACLK)
if (!ARESETN)
rReadAddress <= {(AddressWidth){1'b0}};
else
if (ARVALID)
rReadAddress <= ARADDR;
always @ (posedge ACLK)
if (!ARESETN)
rReadData <= {(DataWidth){1'b0}};
else
if ((rCurState == State_INCMDREQ) && iReadAck)
rReadData <= iReadData;
assign oReadAddress = rReadAddress;
assign RDATA = rReadData;
assign RRESP = 2'b0;
endmodule
|
module SPIFSM (
input Reset_n_i,
input Clk_i,
input In0_i,
input In1_i,
input In2_i,
input In3_i,
input In4_i,
input In5_i,
input In6_i,
input In7_i,
output Out0_o,
output Out1_o,
output Out2_o,
output Out3_o,
output Out4_o,
output Out5_o,
output Out6_o,
output Out7_o,
output Out8_o,
output Out9_o,
output Out10_o,
output Out11_o,
output Out12_o,
output Out13_o,
output Out14_o,
input CfgMode_i,
input CfgClk_i,
input CfgShift_i,
input CfgDataIn_i,
output CfgDataOut_o
);
wire [7:0] Input_s;
wire [14:0] Output_s;
wire ScanEnable_s;
wire ScanClk_s;
wire ScanDataIn_s;
wire ScanDataOut_s;
TRFSM #(
.InputWidth(8),
.OutputWidth(15),
.StateWidth(5),
.UseResetRow(0),
.NumRows0(5),
.NumRows1(10),
.NumRows2(10),
.NumRows3(5),
.NumRows4(5),
.NumRows5(0),
.NumRows6(0),
.NumRows7(0),
.NumRows8(0),
.NumRows9(0)
) TRFSM_1 (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.Input_i(Input_s),
.Output_o(Output_s),
.CfgMode_i(CfgMode_i),
.CfgClk_i(CfgClk_i),
.CfgShift_i(CfgShift_i),
.CfgDataIn_i(CfgDataIn_i),
.CfgDataOut_o(CfgDataOut_o),
.ScanEnable_i(ScanEnable_s),
.ScanClk_i(ScanClk_s),
.ScanDataIn_i(ScanDataIn_s),
.ScanDataOut_o(ScanDataOut_s)
);
assign Input_s = { In7_i, In6_i, In5_i, In4_i, In3_i, In2_i, In1_i, In0_i };
assign Out0_o = Output_s[0];
assign Out1_o = Output_s[1];
assign Out2_o = Output_s[2];
assign Out3_o = Output_s[3];
assign Out4_o = Output_s[4];
assign Out5_o = Output_s[5];
assign Out6_o = Output_s[6];
assign Out7_o = Output_s[7];
assign Out8_o = Output_s[8];
assign Out9_o = Output_s[9];
assign Out10_o = Output_s[10];
assign Out11_o = Output_s[11];
assign Out12_o = Output_s[12];
assign Out13_o = Output_s[13];
assign Out14_o = Output_s[14];
assign ScanEnable_s = 1'b0;
assign ScanClk_s = 1'b0;
assign ScanDataIn_s = 1'b0;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DLATCH_PR_PP_PKG_S_TB_V
`define SKY130_FD_SC_HS__UDP_DLATCH_PR_PP_PKG_S_TB_V
/**
* udp_dlatch$PR_pp$PKG$s: D-latch, gated clear direct / gate active
* high (Q output UDP)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__udp_dlatch_pr_pp_pkg_s.v"
module top();
// Inputs are registered
reg D;
reg RESET;
reg SLEEP_B;
reg KAPWR;
reg VGND;
reg VPWR;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
KAPWR = 1'bX;
RESET = 1'bX;
SLEEP_B = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 KAPWR = 1'b0;
#60 RESET = 1'b0;
#80 SLEEP_B = 1'b0;
#100 VGND = 1'b0;
#120 VPWR = 1'b0;
#140 D = 1'b1;
#160 KAPWR = 1'b1;
#180 RESET = 1'b1;
#200 SLEEP_B = 1'b1;
#220 VGND = 1'b1;
#240 VPWR = 1'b1;
#260 D = 1'b0;
#280 KAPWR = 1'b0;
#300 RESET = 1'b0;
#320 SLEEP_B = 1'b0;
#340 VGND = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VGND = 1'b1;
#420 SLEEP_B = 1'b1;
#440 RESET = 1'b1;
#460 KAPWR = 1'b1;
#480 D = 1'b1;
#500 VPWR = 1'bx;
#520 VGND = 1'bx;
#540 SLEEP_B = 1'bx;
#560 RESET = 1'bx;
#580 KAPWR = 1'bx;
#600 D = 1'bx;
end
// Create a clock
reg GATE;
initial
begin
GATE = 1'b0;
end
always
begin
#5 GATE = ~GATE;
end
sky130_fd_sc_hs__udp_dlatch$PR_pp$PKG$s dut (.D(D), .RESET(RESET), .SLEEP_B(SLEEP_B), .KAPWR(KAPWR), .VGND(VGND), .VPWR(VPWR), .Q(Q), .GATE(GATE));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DLATCH_PR_PP_PKG_S_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__FILL_DIODE_SYMBOL_V
`define SKY130_FD_SC_MS__FILL_DIODE_SYMBOL_V
/**
* fill_diode: Fill diode.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__fill_diode ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__FILL_DIODE_SYMBOL_V
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_5_axi_master.v
*
* Date : 2012-11
*
* Description : Model that acts as PS AXI Master port interface.
* It uses AXI3 Master BFM
*****************************************************************************/
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_5_axi_master (
M_RESETN,
M_ARVALID,
M_AWVALID,
M_BREADY,
M_RREADY,
M_WLAST,
M_WVALID,
M_ARID,
M_AWID,
M_WID,
M_ARBURST,
M_ARLOCK,
M_ARSIZE,
M_AWBURST,
M_AWLOCK,
M_AWSIZE,
M_ARPROT,
M_AWPROT,
M_ARADDR,
M_AWADDR,
M_WDATA,
M_ARCACHE,
M_ARLEN,
M_AWCACHE,
M_AWLEN,
M_ARQOS, // not connected to AXI BFM
M_AWQOS, // not connected to AXI BFM
M_WSTRB,
M_ACLK,
M_ARREADY,
M_AWREADY,
M_BVALID,
M_RLAST,
M_RVALID,
M_WREADY,
M_BID,
M_RID,
M_BRESP,
M_RRESP,
M_RDATA
);
parameter enable_this_port = 0;
parameter master_name = "Master";
parameter data_bus_width = 32;
parameter address_bus_width = 32;
parameter id_bus_width = 6;
parameter max_outstanding_transactions = 8;
parameter exclusive_access_supported = 0;
parameter EXCL_ID = 12'hC00;
`include "processing_system7_bfm_v2_0_5_local_params.v"
/* IDs for Masters
// l2m1 (CPU000)
12'b11_000_000_00_00
12'b11_010_000_00_00
12'b11_011_000_00_00
12'b11_100_000_00_00
12'b11_101_000_00_00
12'b11_110_000_00_00
12'b11_111_000_00_00
// l2m1 (CPU001)
12'b11_000_001_00_00
12'b11_010_001_00_00
12'b11_011_001_00_00
12'b11_100_001_00_00
12'b11_101_001_00_00
12'b11_110_001_00_00
12'b11_111_001_00_00
*/
input M_RESETN;
output M_ARVALID;
output M_AWVALID;
output M_BREADY;
output M_RREADY;
output M_WLAST;
output M_WVALID;
output [id_bus_width-1:0] M_ARID;
output [id_bus_width-1:0] M_AWID;
output [id_bus_width-1:0] M_WID;
output [axi_brst_type_width-1:0] M_ARBURST;
output [axi_lock_width-1:0] M_ARLOCK;
output [axi_size_width-1:0] M_ARSIZE;
output [axi_brst_type_width-1:0] M_AWBURST;
output [axi_lock_width-1:0] M_AWLOCK;
output [axi_size_width-1:0] M_AWSIZE;
output [axi_prot_width-1:0] M_ARPROT;
output [axi_prot_width-1:0] M_AWPROT;
output [address_bus_width-1:0] M_ARADDR;
output [address_bus_width-1:0] M_AWADDR;
output [data_bus_width-1:0] M_WDATA;
output [axi_cache_width-1:0] M_ARCACHE;
output [axi_len_width-1:0] M_ARLEN;
output [axi_qos_width-1:0] M_ARQOS; // not connected to AXI BFM
output [axi_cache_width-1:0] M_AWCACHE;
output [axi_len_width-1:0] M_AWLEN;
output [axi_qos_width-1:0] M_AWQOS; // not connected to AXI BFM
output [(data_bus_width/8)-1:0] M_WSTRB;
input M_ACLK;
input M_ARREADY;
input M_AWREADY;
input M_BVALID;
input M_RLAST;
input M_RVALID;
input M_WREADY;
input [id_bus_width-1:0] M_BID;
input [id_bus_width-1:0] M_RID;
input [axi_rsp_width-1:0] M_BRESP;
input [axi_rsp_width-1:0] M_RRESP;
input [data_bus_width-1:0] M_RDATA;
wire net_RESETN;
wire net_RVALID;
wire net_BVALID;
reg DEBUG_INFO = 1'b1;
reg STOP_ON_ERROR = 1'b1;
integer use_id_no = 0;
assign M_ARQOS = 'b0;
assign M_AWQOS = 'b0;
assign net_RESETN = M_RESETN; //ENABLE_THIS_PORT ? M_RESETN : 1'b0;
assign net_RVALID = enable_this_port ? M_RVALID : 1'b0;
assign net_BVALID = enable_this_port ? M_BVALID : 1'b0;
initial begin
if(DEBUG_INFO) begin
if(enable_this_port)
$display("[%0d] : %0s : %0s : Port is ENABLED.",$time, DISP_INFO, master_name);
else
$display("[%0d] : %0s : %0s : Port is DISABLED.",$time, DISP_INFO, master_name);
end
end
initial master.set_disable_reset_value_checks(1);
initial begin
repeat(2) @(posedge M_ACLK);
if(!enable_this_port) begin
master.set_channel_level_info(0);
master.set_function_level_info(0);
end
master.RESPONSE_TIMEOUT = 0;
end
cdn_axi3_master_bfm #(master_name,
data_bus_width,
address_bus_width,
id_bus_width,
max_outstanding_transactions,
exclusive_access_supported)
master (.ACLK (M_ACLK),
.ARESETn (net_RESETN), /// confirm this
// Write Address Channel
.AWID (M_AWID),
.AWADDR (M_AWADDR),
.AWLEN (M_AWLEN),
.AWSIZE (M_AWSIZE),
.AWBURST (M_AWBURST),
.AWLOCK (M_AWLOCK),
.AWCACHE (M_AWCACHE),
.AWPROT (M_AWPROT),
.AWVALID (M_AWVALID),
.AWREADY (M_AWREADY),
// Write Data Channel Signals.
.WID (M_WID),
.WDATA (M_WDATA),
.WSTRB (M_WSTRB),
.WLAST (M_WLAST),
.WVALID (M_WVALID),
.WREADY (M_WREADY),
// Write Response Channel Signals.
.BID (M_BID),
.BRESP (M_BRESP),
.BVALID (net_BVALID),
.BREADY (M_BREADY),
// Read Address Channel Signals.
.ARID (M_ARID),
.ARADDR (M_ARADDR),
.ARLEN (M_ARLEN),
.ARSIZE (M_ARSIZE),
.ARBURST (M_ARBURST),
.ARLOCK (M_ARLOCK),
.ARCACHE (M_ARCACHE),
.ARPROT (M_ARPROT),
.ARVALID (M_ARVALID),
.ARREADY (M_ARREADY),
// Read Data Channel Signals.
.RID (M_RID),
.RDATA (M_RDATA),
.RRESP (M_RRESP),
.RLAST (M_RLAST),
.RVALID (net_RVALID),
.RREADY (M_RREADY));
/* Call to BFM APIs */
task automatic read_burst(input [address_bus_width-1:0] addr,input [axi_len_width-1:0] len,input [axi_size_width-1:0] siz,input [axi_brst_type_width-1:0] burst,input [axi_lock_width-1:0] lck,input [axi_cache_width-1:0] cache,input [axi_prot_width-1:0] prot,output [(axi_mgp_data_width*axi_burst_len)-1:0] data, output [(axi_rsp_width*axi_burst_len)-1:0] response);
if(enable_this_port)begin
if(lck !== AXI_NRML)
master.READ_BURST(EXCL_ID,addr,len,siz,burst,lck,cache,prot,data,response);
else
master.READ_BURST(get_id(1),addr,len,siz,burst,lck,cache,prot,data,response);
end else begin
$display("[%0d] : %0s : %0s : Port is disabled. 'read_burst' will not be executed...",$time, DISP_ERR, master_name);
if(STOP_ON_ERROR) $stop;
end
endtask
task automatic write_burst(input [address_bus_width-1:0] addr,input [axi_len_width-1:0] len,input [axi_size_width-1:0] siz,input [axi_brst_type_width-1:0] burst,input [axi_lock_width-1:0] lck,input [axi_cache_width-1:0] cache,input [axi_prot_width-1:0] prot,input [(axi_mgp_data_width*axi_burst_len)-1:0] data,input integer datasize, output [axi_rsp_width-1:0] response);
if(enable_this_port)begin
if(lck !== AXI_NRML)
master.WRITE_BURST(EXCL_ID,addr,len,siz,burst,lck,cache,prot,data,datasize,response);
else
master.WRITE_BURST(get_id(1),addr,len,siz,burst,lck,cache,prot,data,datasize,response);
end else begin
$display("[%0d] : %0s : %0s : Port is disabled. 'write_burst' will not be executed...",$time, DISP_ERR, master_name);
if(STOP_ON_ERROR) $stop;
end
endtask
task automatic write_burst_concurrent(input [address_bus_width-1:0] addr,input [axi_len_width-1:0] len,input [axi_size_width-1:0] siz,input [axi_brst_type_width-1:0] burst,input [axi_lock_width-1:0] lck,input [axi_cache_width-1:0] cache,input [axi_prot_width-1:0] prot,input [(axi_mgp_data_width*axi_burst_len)-1:0] data,input integer datasize, output [axi_rsp_width-1:0] response);
if(enable_this_port)begin
if(lck !== AXI_NRML)
master.WRITE_BURST_CONCURRENT(EXCL_ID,addr,len,siz,burst,lck,cache,prot,data,datasize,response);
else
master.WRITE_BURST_CONCURRENT(get_id(1),addr,len,siz,burst,lck,cache,prot,data,datasize,response);
end else begin
$display("[%0d] : %0s : %0s : Port is disabled. 'write_burst_concurrent' will not be executed...",$time, DISP_ERR, master_name);
if(STOP_ON_ERROR) $stop;
end
endtask
/* local */
function automatic[id_bus_width-1:0] get_id;
input dummy;
begin
case(use_id_no)
// l2m1 (CPU000)
0 : get_id = 12'b11_000_000_00_00;
1 : get_id = 12'b11_010_000_00_00;
2 : get_id = 12'b11_011_000_00_00;
3 : get_id = 12'b11_100_000_00_00;
4 : get_id = 12'b11_101_000_00_00;
5 : get_id = 12'b11_110_000_00_00;
6 : get_id = 12'b11_111_000_00_00;
// l2m1 (CPU001)
7 : get_id = 12'b11_000_001_00_00;
8 : get_id = 12'b11_010_001_00_00;
9 : get_id = 12'b11_011_001_00_00;
10 : get_id = 12'b11_100_001_00_00;
11 : get_id = 12'b11_101_001_00_00;
12 : get_id = 12'b11_110_001_00_00;
13 : get_id = 12'b11_111_001_00_00;
endcase
if(use_id_no == 13)
use_id_no = 0;
else
use_id_no = use_id_no+1;
end
endfunction
/* Write data from file */
task automatic write_from_file;
input [(max_chars*8)-1:0] file_name;
input [addr_width-1:0] start_addr;
input [int_width-1:0] wr_size;
output [axi_rsp_width-1:0] response;
reg [axi_rsp_width-1:0] wresp,rwrsp;
reg [addr_width-1:0] addr;
reg [(axi_burst_len*data_bus_width)-1 : 0] wr_data;
integer bytes;
integer trnsfr_bytes;
integer wr_fd;
integer succ;
integer trnsfr_lngth;
reg concurrent;
reg [id_bus_width-1:0] wr_id;
reg [axi_size_width-1:0] siz;
reg [axi_brst_type_width-1:0] burst;
reg [axi_lock_width-1:0] lck;
reg [axi_cache_width-1:0] cache;
reg [axi_prot_width-1:0] prot;
begin
if(!enable_this_port) begin
$display("[%0d] : %0s : %0s : Port is disabled. 'write_from_file' will not be executed...",$time, DISP_ERR, master_name);
if(STOP_ON_ERROR) $stop;
end else begin
siz = 2;
burst = 1;
lck = 0;
cache = 0;
prot = 0;
addr = start_addr;
bytes = wr_size;
wresp = 0;
concurrent = $random;
if(bytes > (axi_burst_len * data_bus_width/8))
trnsfr_bytes = (axi_burst_len * data_bus_width/8);
else
trnsfr_bytes = bytes;
if(bytes > (axi_burst_len * data_bus_width/8))
trnsfr_lngth = axi_burst_len-1;
else if(bytes%(data_bus_width/8) == 0)
trnsfr_lngth = bytes/(data_bus_width/8) - 1;
else
trnsfr_lngth = bytes/(data_bus_width/8);
wr_id = get_id(1);
wr_fd = $fopen(file_name,"r");
while (bytes > 0) begin
repeat(axi_burst_len) begin /// get the data for 1 AXI burst transaction
wr_data = wr_data >> data_bus_width;
succ = $fscanf(wr_fd,"%h",wr_data[(axi_burst_len*data_bus_width)-1 :(axi_burst_len*data_bus_width)-data_bus_width ]); /// write as 4 bytes (data_bus_width) ..
end
if(concurrent)
master.WRITE_BURST_CONCURRENT(wr_id, addr, trnsfr_lngth, siz, burst, lck, cache, prot, wr_data, trnsfr_bytes, rwrsp);
else
master.WRITE_BURST(wr_id, addr, trnsfr_lngth, siz, burst, lck, cache, prot, wr_data, trnsfr_bytes, rwrsp);
bytes = bytes - trnsfr_bytes;
addr = addr + trnsfr_bytes;
if(bytes >= (axi_burst_len * data_bus_width/8) )
trnsfr_bytes = (axi_burst_len * data_bus_width/8); //
else
trnsfr_bytes = bytes;
if(bytes > (axi_burst_len * data_bus_width/8))
trnsfr_lngth = axi_burst_len-1;
else if(bytes%(data_bus_width/8) == 0)
trnsfr_lngth = bytes/(data_bus_width/8) - 1;
else
trnsfr_lngth = bytes/(data_bus_width/8);
wresp = wresp | rwrsp;
end /// while
response = wresp;
end
end
endtask
/* Read data to file */
task automatic read_to_file;
input [(max_chars*8)-1:0] file_name;
input [addr_width-1:0] start_addr;
input [int_width-1:0] rd_size;
output [axi_rsp_width-1:0] response;
reg [axi_rsp_width-1:0] rresp, rrrsp;
reg [addr_width-1:0] addr;
integer bytes;
integer trnsfr_lngth;
reg [(axi_burst_len*data_bus_width)-1 :0] rd_data;
integer rd_fd;
reg [id_bus_width-1:0] rd_id;
reg [axi_size_width-1:0] siz;
reg [axi_brst_type_width-1:0] burst;
reg [axi_lock_width-1:0] lck;
reg [axi_cache_width-1:0] cache;
reg [axi_prot_width-1:0] prot;
begin
if(!enable_this_port) begin
$display("[%0d] : %0s : %0s : Port is disabled. 'read_to_file' will not be executed...",$time, DISP_ERR, master_name);
if(STOP_ON_ERROR) $stop;
end else begin
siz = 2;
burst = 1;
lck = 0;
cache = 0;
prot = 0;
addr = start_addr;
rresp = 0;
bytes = rd_size;
rd_id = get_id(1'b1);
if(bytes > (axi_burst_len * data_bus_width/8))
trnsfr_lngth = axi_burst_len-1;
else if(bytes%(data_bus_width/8) == 0)
trnsfr_lngth = bytes/(data_bus_width/8) - 1;
else
trnsfr_lngth = bytes/(data_bus_width/8);
rd_fd = $fopen(file_name,"w");
while (bytes > 0) begin
master.READ_BURST(rd_id, addr, trnsfr_lngth, siz, burst, lck, cache, prot, rd_data, rrrsp);
repeat(trnsfr_lngth+1) begin
$fdisplayh(rd_fd,rd_data[data_bus_width-1:0]);
rd_data = rd_data >> data_bus_width;
end
addr = addr + (trnsfr_lngth+1)*4;
if(bytes >= (axi_burst_len * data_bus_width/8) )
bytes = bytes - (axi_burst_len * data_bus_width/8); //
else
bytes = 0;
if(bytes > (axi_burst_len * data_bus_width/8))
trnsfr_lngth = axi_burst_len-1;
else if(bytes%(data_bus_width/8) == 0)
trnsfr_lngth = bytes/(data_bus_width/8) - 1;
else
trnsfr_lngth = bytes/(data_bus_width/8);
rresp = rresp | rrrsp;
end /// while
response = rresp;
end
end
endtask
/* Write data (used for transfer size <= 128 Bytes */
task automatic write_data;
input [addr_width-1:0] start_addr;
input [max_transfer_bytes_width:0] wr_size;
input [(max_transfer_bytes*8)-1:0] w_data;
output [axi_rsp_width-1:0] response;
reg [axi_rsp_width-1:0] wresp,rwrsp;
reg [addr_width-1:0] addr;
reg [7:0] bytes,tmp_bytes;
integer trnsfr_bytes;
reg [(max_transfer_bytes*8)-1:0] wr_data;
integer trnsfr_lngth;
reg concurrent;
reg [id_bus_width-1:0] wr_id;
reg [axi_size_width-1:0] siz;
reg [axi_brst_type_width-1:0] burst;
reg [axi_lock_width-1:0] lck;
reg [axi_cache_width-1:0] cache;
reg [axi_prot_width-1:0] prot;
integer pad_bytes;
begin
if(!enable_this_port) begin
$display("[%0d] : %0s : %0s : Port is disabled. 'write_data' will not be executed...",$time, DISP_ERR, master_name);
if(STOP_ON_ERROR) $stop;
end else begin
addr = start_addr;
bytes = wr_size;
wresp = 0;
wr_data = w_data;
concurrent = $random;
siz = 2;
burst = 1;
lck = 0;
cache = 0;
prot = 0;
pad_bytes = start_addr[clogb2(data_bus_width/8)-1:0];
wr_id = get_id(1);
if(bytes+pad_bytes > (data_bus_width/8*axi_burst_len)) begin /// for unaligned address
trnsfr_bytes = (data_bus_width*axi_burst_len)/8 - pad_bytes;//start_addr[1:0];
trnsfr_lngth = axi_burst_len-1;
end else begin
trnsfr_bytes = bytes;
tmp_bytes = bytes + pad_bytes;//start_addr[1:0];
if(tmp_bytes%(data_bus_width/8) == 0)
trnsfr_lngth = tmp_bytes/(data_bus_width/8) - 1;
else
trnsfr_lngth = tmp_bytes/(data_bus_width/8);
end
while (bytes > 0) begin
if(concurrent)
master.WRITE_BURST_CONCURRENT(wr_id, addr, trnsfr_lngth, siz, burst, lck, cache, prot, wr_data[(axi_burst_len*data_bus_width)-1:0], trnsfr_bytes, rwrsp);
else
master.WRITE_BURST(wr_id, addr, trnsfr_lngth, siz, burst, lck, cache, prot, wr_data[(axi_burst_len*data_bus_width)-1:0], trnsfr_bytes, rwrsp);
wr_data = wr_data >> (trnsfr_bytes*8);
bytes = bytes - trnsfr_bytes;
addr = addr + trnsfr_bytes;
if(bytes > (axi_burst_len * data_bus_width/8)) begin
trnsfr_bytes = (axi_burst_len * data_bus_width/8) - pad_bytes;//start_addr[1:0];
trnsfr_lngth = axi_burst_len-1;
end else begin
trnsfr_bytes = bytes;
tmp_bytes = bytes + pad_bytes;//start_addr[1:0];
if(tmp_bytes%(data_bus_width/8) == 0)
trnsfr_lngth = tmp_bytes/(data_bus_width/8) - 1;
else
trnsfr_lngth = tmp_bytes/(data_bus_width/8);
end
wresp = wresp | rwrsp;
end /// while
response = wresp;
end
end
endtask
/* Read data (used for transfer size <= 128 Bytes */
task automatic read_data;
input [addr_width-1:0] start_addr;
input [max_transfer_bytes_width:0] rd_size;
output [(max_transfer_bytes*8)-1:0] r_data;
output [axi_rsp_width-1:0] response;
reg [axi_rsp_width-1:0] rresp,rdrsp;
reg [addr_width-1:0] addr;
reg [max_transfer_bytes_width:0] bytes,tmp_bytes;
integer trnsfr_bytes;
reg [(max_transfer_bytes*8)-1 : 0] rd_data;
reg [(axi_burst_len*data_bus_width)-1:0] rcv_rd_data;
integer total_rcvd_bytes;
integer trnsfr_lngth;
integer i;
reg [id_bus_width-1:0] rd_id;
reg [axi_size_width-1:0] siz;
reg [axi_brst_type_width-1:0] burst;
reg [axi_lock_width-1:0] lck;
reg [axi_cache_width-1:0] cache;
reg [axi_prot_width-1:0] prot;
integer pad_bytes;
begin
if(!enable_this_port) begin
$display("[%0d] : %0s : %0s : Port is disabled. 'read_data' will not be executed...",$time, DISP_ERR, master_name);
if(STOP_ON_ERROR) $stop;
end else begin
addr = start_addr;
bytes = rd_size;
rresp = 0;
total_rcvd_bytes = 0;
rd_data = 0;
rd_id = get_id(1'b1);
siz = 2;
burst = 1;
lck = 0;
cache = 0;
prot = 0;
pad_bytes = start_addr[clogb2(data_bus_width/8)-1:0];
if(bytes+ pad_bytes > (axi_burst_len * data_bus_width/8)) begin /// for unaligned address
trnsfr_bytes = (axi_burst_len * data_bus_width/8) - pad_bytes;//start_addr[1:0];
trnsfr_lngth = axi_burst_len-1;
end else begin
trnsfr_bytes = bytes;
tmp_bytes = bytes + pad_bytes;//start_addr[1:0];
if(tmp_bytes%(data_bus_width/8) == 0)
trnsfr_lngth = tmp_bytes/(data_bus_width/8) - 1;
else
trnsfr_lngth = tmp_bytes/(data_bus_width/8);
end
while (bytes > 0) begin
master.READ_BURST(rd_id,addr, trnsfr_lngth, siz, burst, lck, cache, prot, rcv_rd_data, rdrsp);
for(i = 0; i < trnsfr_bytes; i = i+1) begin
rd_data = rd_data >> 8;
rd_data[(max_transfer_bytes*8)-1 : (max_transfer_bytes*8)-8] = rcv_rd_data[7:0];
rcv_rd_data = rcv_rd_data >> 8;
total_rcvd_bytes = total_rcvd_bytes+1;
end
bytes = bytes - trnsfr_bytes;
addr = addr + trnsfr_bytes;
if(bytes > (axi_burst_len * data_bus_width/8)) begin
trnsfr_bytes = (axi_burst_len * data_bus_width/8) - pad_bytes;//start_addr[1:0];
trnsfr_lngth = 15;
end else begin
trnsfr_bytes = bytes;
tmp_bytes = bytes + pad_bytes;//start_addr[1:0];
if(tmp_bytes%(data_bus_width/8) == 0)
trnsfr_lngth = tmp_bytes/(data_bus_width/8) - 1;
else
trnsfr_lngth = tmp_bytes/(data_bus_width/8);
end
rresp = rresp | rdrsp;
end /// while
rd_data = rd_data >> (max_transfer_bytes - total_rcvd_bytes)*8;
r_data = rd_data;
response = rresp;
end
end
endtask
/* Wait Register Update in PL */
/* Issue a series of 1 burst length reads until the expected data pattern is received */
task automatic wait_reg_update;
input [addr_width-1:0] addri;
input [data_width-1:0] datai;
input [data_width-1:0] maski;
input [int_width-1:0] time_interval;
input [int_width-1:0] time_out;
output [data_width-1:0] data_o;
output upd_done;
reg [addr_width-1:0] addr;
reg [data_width-1:0] data_i;
reg [data_width-1:0] mask_i;
integer time_int;
integer timeout;
reg [axi_rsp_width-1:0] rdrsp;
reg [id_bus_width-1:0] rd_id;
reg [axi_size_width-1:0] siz;
reg [axi_brst_type_width-1:0] burst;
reg [axi_lock_width-1:0] lck;
reg [axi_cache_width-1:0] cache;
reg [axi_prot_width-1:0] prot;
reg [data_width-1:0] rcv_data;
integer trnsfr_lngth;
reg rd_loop;
reg timed_out;
integer i;
integer cycle_cnt;
begin
addr = addri;
data_i = datai;
mask_i = maski;
time_int = time_interval;
timeout = time_out;
timed_out = 0;
cycle_cnt = 0;
if(!enable_this_port) begin
$display("[%0d] : %0s : %0s : Port is disabled. 'wait_reg_update' will not be executed...",$time, DISP_ERR, master_name);
upd_done = 0;
if(STOP_ON_ERROR) $stop;
end else begin
rd_id = get_id(1'b1);
siz = 2;
burst = 1;
lck = 0;
cache = 0;
prot = 0;
trnsfr_lngth = 0;
rd_loop = 1;
fork
begin
while(!timed_out & rd_loop) begin
cycle_cnt = cycle_cnt + 1;
if(cycle_cnt >= timeout) timed_out = 1;
@(posedge M_ACLK);
end
end
begin
while (rd_loop) begin
if(DEBUG_INFO)
$display("[%0d] : %0s : %0s : Reading Register mapped at Address(0x%0h) ",$time, master_name, DISP_INFO, addr);
master.READ_BURST(rd_id,addr, trnsfr_lngth, siz, burst, lck, cache, prot, rcv_data, rdrsp);
if(DEBUG_INFO)
$display("[%0d] : %0s : %0s : Reading Register returned (0x%0h) ",$time, master_name, DISP_INFO, rcv_data);
if(((rcv_data & ~mask_i) === (data_i & ~mask_i)) | timed_out)
rd_loop = 0;
else
repeat(time_int) @(posedge M_ACLK);
end /// while
end
join
data_o = rcv_data & ~mask_i;
if(timed_out) begin
$display("[%0d] : %0s : %0s : 'wait_reg_update' timed out ... Register is not updated ",$time, DISP_ERR, master_name);
if(STOP_ON_ERROR) $stop;
end else
upd_done = 1;
end
end
endtask
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2016 by Adrian Wise.
// SPDX-License-Identifier: CC0-1.0
//bug1104
module t (input clk);
simple_bus sb_intf(clk);
simple_bus #(.DWIDTH(16)) wide_intf(clk);
mem mem(sb_intf.slave);
cpu cpu(sb_intf.master);
mem memW(wide_intf.slave);
cpu cpuW(wide_intf.master);
endmodule
interface simple_bus #(AWIDTH = 8, DWIDTH = 8)
(input logic clk); // Define the interface
logic req, gnt;
logic [AWIDTH-1:0] addr;
logic [DWIDTH-1:0] data;
modport slave( input req, addr, clk,
output gnt,
input data);
modport master(input gnt, clk,
output req, addr,
output data);
initial begin
if (DWIDTH != 16) $stop;
end
endinterface: simple_bus
module mem(interface a);
logic avail;
always @(posedge a.clk)
a.gnt <= a.req & avail;
initial begin
if ($bits(a.data) != 16) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
module cpu(interface b);
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized AND with generic_baseblocks_v2_1_carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_carry_and #
(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
)
(
input wire CIN,
input wire S,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL
assign COUT = CIN & S;
end else begin : USE_FPGA
MUXCY and_inst
(
.O (COUT),
.CI (CIN),
.DI (1'b0),
.S (S)
);
end
endgenerate
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - validate named blocks/disable stmt
//
// D: This code verifies both named blocks and the disable statement
// D: It is intended to be self checking.
//
module main ();
reg working;
reg timer;
initial
begin:my_block
working = 1;
#5;
working = 1;
#5;
working = 1;
#5;
working = 0;
#5;
end
initial
begin
#15;
disable my_block;
end
initial
begin
#20;
if(!working)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : V5-Block Plus for PCI Express
// File : cmm_errman_cnt_en.v
//--------------------------------------------------------------------------------
//--------------------------------------------------------------------------------
/***********************************************************************
Description:
This is the error counter module for tracking the outstanding
correctible/fatal. When overflow or underflow occurs, it remains at
either full scale (overflow) or zero (underflow) instead of rolling
over.
***********************************************************************/
`ifndef FFD
`define FFD 1
`endif
module cmm_errman_cnt_en (
count, // Outputs
index, // Inputs
inc_dec_b,
enable,
rst,
clk
);
output [3:0] count;
input [2:0] index; // ftl_num, nfl_num or cor_num
input inc_dec_b; // 1 = increment, 0 = decrement
input enable; // err_*_en
input rst;
input clk;
//******************************************************************//
// Reality check. //
//******************************************************************//
parameter FFD = 1; // clock to out delay model
//******************************************************************//
// There are 2 pipeline stages to help timing. //
// Stage 1: a simple add/subtract accumulator with no overflow or //
// underflow check. //
// Stage 2: underflow, overflow and counter enable are handled. //
//******************************************************************//
// Stage 1: count up or count down
reg [3:0] reg_cnt;
reg reg_extra;
reg reg_inc_dec_b;
reg reg_uflow;
//wire [3:0] cnt;
reg [3:0] cnt;
wire oflow;
wire uflow;
always @(posedge clk or posedge rst) begin
if (rst) {reg_extra, reg_cnt} <= #`FFD 5'b00000;
else if (~enable) {reg_extra, reg_cnt} <= #`FFD 5'b00000;
else if (inc_dec_b) {reg_extra, reg_cnt} <= #`FFD cnt + index;
else {reg_extra, reg_cnt} <= #`FFD cnt - index;
end
//assign cnt = oflow ? 4'hF : (uflow ? 4'h0 : reg_cnt);
always @(oflow or uflow or reg_cnt) begin
case ({oflow,uflow}) // synthesis full_case parallel_case
2'b11: cnt = 4'hF;
2'b10: cnt = 4'hF;
2'b01: cnt = 4'h0;
2'b00: cnt = reg_cnt;
endcase
end
always @(posedge clk or posedge rst) begin
if (rst) reg_inc_dec_b <= #`FFD 1'b0;
else reg_inc_dec_b <= #`FFD inc_dec_b;
end
assign oflow = reg_extra & reg_inc_dec_b;
always @(posedge clk or posedge rst) begin
if (rst)
reg_uflow <= #`FFD 1'b0;
else
//reg_uflow <= #`FFD (count == 4'b0000) & (index[2:0] != 3'b000) & ~inc_dec_b;
reg_uflow <= #`FFD ~|count & |index[2:0] & ~inc_dec_b;
end
assign uflow = reg_uflow;
// Stage 2: if overflow occurs, the counter is set to full scale;
// if underflow occurs, it is set to zero.
// if counter is not enable, it is set to zero.
reg [3:0] reg_count;
always @(posedge clk or posedge rst) begin
if (rst) reg_count <= #`FFD 4'b0000;
else if (~enable) reg_count <= #`FFD 4'b0000;
else if (oflow) reg_count <= #`FFD 4'b1111;
else if (uflow) reg_count <= #`FFD 4'b0000;
else reg_count <= #`FFD cnt;
end
assign count = reg_count;
//******************************************************************//
// //
//******************************************************************//
endmodule
|
module I2C_Controller
(
input iCLK,
input iRST_N,
input I2C_CLK,
input I2C_EN,
input [23:0] I2C_WDATA,
output I2C_SCLK,
inout I2C_SDAT,
input WR,
input GO,
output ACK,
output reg END,
output reg [7:0] I2C_RDATA
);
reg I2C_BIT;
reg SCLK;
reg [5:0] SD_COUNTER;
wire I2C_SCLK1 = (GO == 1 &&
((SD_COUNTER >= 5 && SD_COUNTER <=12 || SD_COUNTER == 14) ||
(SD_COUNTER >= 16 && SD_COUNTER <=23 || SD_COUNTER == 25) ||
(SD_COUNTER >= 27 && SD_COUNTER <=34 || SD_COUNTER == 36))) ? I2C_CLK : SCLK;
wire I2C_SCLK2 = (GO == 1 &&
((SD_COUNTER >= 5 && SD_COUNTER <=12 || SD_COUNTER == 14) ||
(SD_COUNTER >= 16 && SD_COUNTER <=23 || SD_COUNTER == 25) ||
(SD_COUNTER >= 33 && SD_COUNTER <=40 || SD_COUNTER == 42) ||
(SD_COUNTER >= 45 && SD_COUNTER <=52 || SD_COUNTER == 54))) ? I2C_CLK : SCLK;
assign I2C_SCLK = WR ? I2C_SCLK1 : I2C_SCLK2;
wire SDO1 = ((SD_COUNTER == 13 || SD_COUNTER == 14)||
(SD_COUNTER == 24 || SD_COUNTER == 25) ||
(SD_COUNTER == 35 || SD_COUNTER == 36)) ? 1'b0 : 1'b1;
wire SDO2 = ((SD_COUNTER == 13 || SD_COUNTER == 14)||
(SD_COUNTER == 24 || SD_COUNTER == 25) ||
(SD_COUNTER == 41 || SD_COUNTER == 42) ||
(SD_COUNTER >= 44 && SD_COUNTER <= 52)) ? 1'b0 : 1'b1;
wire SDO = WR ? SDO1 : SDO2;
assign I2C_SDAT = SDO ? I2C_BIT : 1'bz;
reg ACKW1, ACKW2, ACKW3;
reg ACKR1, ACKR2, ACKR3;
assign ACK = WR ? (ACKW1 | ACKW2 | ACKW3) : (ACKR1 | ACKR2 | ACKR3);
always @(posedge iCLK or negedge iRST_N)
begin
if (!iRST_N)
SD_COUNTER <= 6'b0;
else if(I2C_EN)
begin
if (GO == 0 || END == 1)
SD_COUNTER <= 6'b0;
else if (SD_COUNTER < 6'd63)
SD_COUNTER <= SD_COUNTER + 6'd1;
end
else
SD_COUNTER <= SD_COUNTER;
end
always @(posedge iCLK or negedge iRST_N)
begin
if(!iRST_N)
begin
SCLK <= 1;
I2C_BIT <= 1;
ACKW1 <= 1; ACKW2 <= 1; ACKW3 <= 1;
ACKR1 <= 1; ACKR2 <= 1; ACKR3 <= 1;
END <= 0;
I2C_RDATA <= 8'h0;
end
else if(I2C_EN)
begin
if(GO)
begin
if(WR)
begin
case(SD_COUNTER)
6'd0 : begin
SCLK <= 1;
I2C_BIT <= 1;
ACKW1 <= 1; ACKW2 <= 1; ACKW3 <= 1;
ACKR1 <= 1; ACKR2 <= 1; ACKR3 <= 1;
END <= 0;
end
6'd1 : begin
SCLK <= 1;
I2C_BIT <= 1;
ACKW1 <= 1; ACKW2 <= 1; ACKW3 <= 1;
END <= 0;
end
6'd2 : I2C_BIT <= 0;
6'd3 : SCLK <= 0;
6'd4 : I2C_BIT <= I2C_WDATA[23];
6'd5 : I2C_BIT <= I2C_WDATA[22];
6'd6 : I2C_BIT <= I2C_WDATA[21];
6'd7 : I2C_BIT <= I2C_WDATA[20];
6'd8 : I2C_BIT <= I2C_WDATA[19];
6'd9 : I2C_BIT <= I2C_WDATA[18];
6'd10 : I2C_BIT <= I2C_WDATA[17];
6'd11 : I2C_BIT <= I2C_WDATA[16];
6'd12 : I2C_BIT <= 0;
6'd13 : ACKW1 <= I2C_SDAT;
6'd14 : I2C_BIT <= 0;
6'd15 : I2C_BIT <= I2C_WDATA[15];
6'd16 : I2C_BIT <= I2C_WDATA[14];
6'd17 : I2C_BIT <= I2C_WDATA[13];
6'd18 : I2C_BIT <= I2C_WDATA[12];
6'd19 : I2C_BIT <= I2C_WDATA[11];
6'd20 : I2C_BIT <= I2C_WDATA[10];
6'd21 : I2C_BIT <= I2C_WDATA[9];
6'd22 : I2C_BIT <= I2C_WDATA[8];
6'd23 : I2C_BIT <= 0;
6'd24 : ACKW2 <= I2C_SDAT;
6'd25 : I2C_BIT <= 0;
6'd26 : I2C_BIT <= I2C_WDATA[7];
6'd27 : I2C_BIT <= I2C_WDATA[6];
6'd28 : I2C_BIT <= I2C_WDATA[5];
6'd29 : I2C_BIT <= I2C_WDATA[4];
6'd30 : I2C_BIT <= I2C_WDATA[3];
6'd31 : I2C_BIT <= I2C_WDATA[2];
6'd32 : I2C_BIT <= I2C_WDATA[1];
6'd33 : I2C_BIT <= I2C_WDATA[0];
6'd34 : I2C_BIT <= 0;
6'd35 : ACKW3 <= I2C_SDAT;
6'd36 : I2C_BIT <= 0;
6'd37 : begin SCLK <= 0; I2C_BIT <= 0; end
6'd38 : SCLK <= 1;
6'd39 : begin I2C_BIT <= 1; END <= 1; end
default : begin I2C_BIT <= 1; SCLK <= 1; end
endcase
end
else
begin
case(SD_COUNTER)
6'd0 : begin
SCLK <= 1;
I2C_BIT <= 1;
ACKW1 <= 1; ACKW2 <= 1; ACKW3 <= 1;
ACKR1 <= 1; ACKR2 <= 1; ACKR3 <= 1;
END <= 0;
end
6'd1 : begin
SCLK <= 1;
I2C_BIT <= 1;
ACKR1 <= 1; ACKR2 <= 1; ACKR3 <= 1;
END <= 0;
end
6'd2 : I2C_BIT <= 0;
6'd3 : SCLK <= 0;
6'd4 : I2C_BIT <= I2C_WDATA[23];
6'd5 : I2C_BIT <= I2C_WDATA[22];
6'd6 : I2C_BIT <= I2C_WDATA[21];
6'd7 : I2C_BIT <= I2C_WDATA[20];
6'd8 : I2C_BIT <= I2C_WDATA[19];
6'd9 : I2C_BIT <= I2C_WDATA[18];
6'd10 : I2C_BIT <= I2C_WDATA[17];
6'd11 : I2C_BIT <= I2C_WDATA[16];
6'd12 : I2C_BIT <= 0;
6'd13 : ACKR1 <= I2C_SDAT;
6'd14 : I2C_BIT <= 0;
6'd15 : I2C_BIT <= I2C_WDATA[15];
6'd16 : I2C_BIT <= I2C_WDATA[14];
6'd17 : I2C_BIT <= I2C_WDATA[13];
6'd18 : I2C_BIT <= I2C_WDATA[12];
6'd19 : I2C_BIT <= I2C_WDATA[11];
6'd20 : I2C_BIT <= I2C_WDATA[10];
6'd21 : I2C_BIT <= I2C_WDATA[9];
6'd22 : I2C_BIT <= I2C_WDATA[8];
6'd23 : I2C_BIT <= 0;
6'd24 : ACKR2 <= I2C_SDAT;
6'd25 : I2C_BIT <= 0;
6'd26 : begin SCLK <= 0; I2C_BIT <= 0; end
6'd27 : SCLK <= 1;
6'd28 : begin I2C_BIT <= 1; end
6'd29 : begin
SCLK <= 1;
I2C_BIT <= 1;
end
6'd30 : I2C_BIT <= 0;
6'd31 : SCLK <= 0;
6'd32 : I2C_BIT <= I2C_WDATA[23];
6'd33 : I2C_BIT <= I2C_WDATA[22];
6'd34 : I2C_BIT <= I2C_WDATA[21];
6'd35 : I2C_BIT <= I2C_WDATA[20];
6'd36 : I2C_BIT <= I2C_WDATA[19];
6'd37 : I2C_BIT <= I2C_WDATA[18];
6'd38 : I2C_BIT <= I2C_WDATA[17];
6'd39 : I2C_BIT <= 1'b1;
6'd40 : I2C_BIT <= 0;
6'd41 : ACKR3 <= I2C_SDAT;
6'd42 : I2C_BIT <= 0;
6'd43 : I2C_BIT <= 0;
6'd44 : I2C_BIT <= 0;
6'd45 : I2C_RDATA[7] <= I2C_SDAT;
6'd46 : I2C_RDATA[6] <= I2C_SDAT;
6'd47 : I2C_RDATA[5] <= I2C_SDAT;
6'd48 : I2C_RDATA[4] <= I2C_SDAT;
6'd49 : I2C_RDATA[3] <= I2C_SDAT;
6'd50 : I2C_RDATA[2] <= I2C_SDAT;
6'd51 : I2C_RDATA[1] <= I2C_SDAT;
6'd52 : I2C_RDATA[0] <= I2C_SDAT;
6'd53 : I2C_BIT <= 1;
6'd54 : I2C_BIT <= 0;
6'd55 : begin SCLK <= 0; I2C_BIT <= 0; end
6'd56 : SCLK <= 1;
6'd57 : begin I2C_BIT <= 1; END <= 1; end
default : begin I2C_BIT <= 1; SCLK <= 1; end
endcase
end
end
else
begin
SCLK <= 1;
I2C_BIT <= 1;
ACKW1 <= 1; ACKW2 <= 1; ACKW3 <= 1;
ACKR1 <= 1; ACKR2 <= 1; ACKR3 <= 1;
END <= 0;
I2C_RDATA <= I2C_RDATA;
end
end
end
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: ram_2clk_1w_1r.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: An inferrable RAM module. Dual clocks, 1 write port, 1
// read port. In Xilinx designs, specify RAM_STYLE="BLOCK"
// to use BRAM memory or RAM_STYLE="DISTRIBUTED" to use
// LUT memory.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
`include "functions.vh"
module ram_2clk_1w_1r
#(
parameter C_RAM_WIDTH = 32,
parameter C_RAM_DEPTH = 1024
)
(
input CLKA,
input CLKB,
input WEA,
input [clog2s(C_RAM_DEPTH)-1:0] ADDRA,
input [clog2s(C_RAM_DEPTH)-1:0] ADDRB,
input [C_RAM_WIDTH-1:0] DINA,
output [C_RAM_WIDTH-1:0] DOUTB
);
//Local parameters
localparam C_RAM_ADDR_BITS = clog2s(C_RAM_DEPTH);
reg [C_RAM_WIDTH-1:0] rRAM [C_RAM_DEPTH-1:0];
reg [C_RAM_WIDTH-1:0] rDout;
assign DOUTB = rDout;
always @(posedge CLKA) begin
if (WEA)
rRAM[ADDRA] <= #1 DINA;
end
always @(posedge CLKB) begin
rDout <= #1 rRAM[ADDRB];
end
endmodule
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003,2005 Matt Ettus
// Copyright (C) 2007 Corgan Enterprises LLC
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
// Clock, enable, and reset controls for whole system
module master_control
( input master_clk, input usbclk,
input wire [6:0] serial_addr, input wire [31:0] serial_data, input wire serial_strobe,
output tx_bus_reset, output rx_bus_reset,
output wire tx_dsp_reset, output wire rx_dsp_reset,
output wire enable_tx, output wire enable_rx,
output wire [7:0] interp_rate, output wire [7:0] decim_rate,
output tx_sample_strobe, output strobe_interp,
output rx_sample_strobe, output strobe_decim,
input tx_empty,
input wire [15:0] debug_0,input wire [15:0] debug_1,input wire [15:0] debug_2,input wire [15:0] debug_3,
output wire [15:0] reg_0, output wire [15:0] reg_1, output wire [15:0] reg_2, output wire [15:0] reg_3,
//the following output is for register reads only
output wire [11:0] atr_tx_delay, output wire [11:0] atr_rx_delay, output wire [7:0] master_controls,
output wire [3:0] debug_en,
output wire [15:0] atr_mask_0, output wire [15:0] atr_txval_0, output wire [15:0] atr_rxval_0,
output wire [15:0] atr_mask_1, output wire [15:0] atr_txval_1, output wire [15:0] atr_rxval_1,
output wire [15:0] atr_mask_2, output wire [15:0] atr_txval_2, output wire [15:0] atr_rxval_2,
output wire [15:0] atr_mask_3, output wire [15:0] atr_txval_3, output wire [15:0] atr_rxval_3,
output wire [7:0] txa_refclk, output wire [7:0] txb_refclk, output wire [7:0] rxa_refclk, output wire [7:0] rxb_refclk
);
// FIXME need a separate reset for all control settings
// Master Controls assignments
//wire [7:0] master_controls;
setting_reg #(`FR_MASTER_CTRL) sr_mstr_ctrl(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(master_controls));
assign enable_tx = master_controls[0];
assign enable_rx = master_controls[1];
assign tx_dsp_reset = master_controls[2];
assign rx_dsp_reset = master_controls[3];
// Unused - 4-7
// Strobe Generators
setting_reg #(`FR_INTERP_RATE) sr_interp(.clock(master_clk),.reset(tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(interp_rate));
setting_reg #(`FR_DECIM_RATE) sr_decim(.clock(master_clk),.reset(rx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(decim_rate));
strobe_gen da_strobe_gen
( .clock(master_clk),.reset(tx_dsp_reset),.enable(enable_tx),
.rate(8'd1),.strobe_in(1'b1),.strobe(tx_sample_strobe) );
strobe_gen tx_strobe_gen
( .clock(master_clk),.reset(tx_dsp_reset),.enable(enable_tx),
.rate(interp_rate),.strobe_in(tx_sample_strobe),.strobe(strobe_interp) );
assign rx_sample_strobe = 1'b1;
strobe_gen decim_strobe_gen
( .clock(master_clk),.reset(rx_dsp_reset),.enable(enable_rx),
.rate(decim_rate),.strobe_in(rx_sample_strobe),.strobe(strobe_decim) );
// Reset syncs for bus (usbclk) side
// The RX bus side reset isn't used, the TX bus side one may not be needed
reg tx_reset_bus_sync1, rx_reset_bus_sync1, tx_reset_bus_sync2, rx_reset_bus_sync2;
always @(posedge usbclk)
begin
tx_reset_bus_sync1 <= #1 tx_dsp_reset;
rx_reset_bus_sync1 <= #1 rx_dsp_reset;
tx_reset_bus_sync2 <= #1 tx_reset_bus_sync1;
rx_reset_bus_sync2 <= #1 rx_reset_bus_sync1;
end
assign tx_bus_reset = tx_reset_bus_sync2;
assign rx_bus_reset = rx_reset_bus_sync2;
//wire [7:0] txa_refclk, rxa_refclk, txb_refclk, rxb_refclk;
wire txaclk,txbclk,rxaclk,rxbclk;
//wire [3:0] debug_en;
wire [3:0] txcvr_ctrl;
wire [31:0] txcvr_rxlines, txcvr_txlines;
setting_reg #(`FR_TX_A_REFCLK) sr_txaref(.clock(master_clk),.reset(tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(txa_refclk));
setting_reg #(`FR_RX_A_REFCLK) sr_rxaref(.clock(master_clk),.reset(rx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(rxa_refclk));
setting_reg #(`FR_TX_B_REFCLK) sr_txbref(.clock(master_clk),.reset(tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(txb_refclk));
setting_reg #(`FR_RX_B_REFCLK) sr_rxbref(.clock(master_clk),.reset(rx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(rxb_refclk));
setting_reg #(`FR_DEBUG_EN) sr_debugen(.clock(master_clk),.reset(rx_dsp_reset|tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(debug_en));
clk_divider clk_div_0 (.reset(tx_dsp_reset),.in_clk(master_clk),.out_clk(txaclk),.ratio(txa_refclk[6:0]));
clk_divider clk_div_1 (.reset(rx_dsp_reset),.in_clk(master_clk),.out_clk(rxaclk),.ratio(rxa_refclk[6:0]));
clk_divider clk_div_2 (.reset(tx_dsp_reset),.in_clk(master_clk),.out_clk(txbclk),.ratio(txb_refclk[6:0]));
clk_divider clk_div_3 (.reset(rx_dsp_reset),.in_clk(master_clk),.out_clk(rxbclk),.ratio(rxb_refclk[6:0]));
reg [15:0] io_0_reg,io_1_reg,io_2_reg,io_3_reg;
// Upper 16 bits are mask for lower 16
always @(posedge master_clk)
if(serial_strobe)
case(serial_addr)
`FR_IO_0 : io_0_reg
<= #1 (io_0_reg & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] );
`FR_IO_1 : io_1_reg
<= #1 (io_1_reg & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] );
`FR_IO_2 : io_2_reg
<= #1 (io_2_reg & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] );
`FR_IO_3 : io_3_reg
<= #1 (io_3_reg & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] );
endcase // case(serial_addr)
wire transmit_now;
wire atr_ctl;
//wire [11:0] atr_tx_delay, atr_rx_delay;
//wire [15:0] atr_mask_0, atr_txval_0, atr_rxval_0, atr_mask_1, atr_txval_1, atr_rxval_1, atr_mask_2, atr_txval_2, atr_rxval_2, atr_mask_3, atr_txval_3, atr_rxval_3;
setting_reg #(`FR_ATR_MASK_0) sr_atr_mask_0(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_mask_0));
setting_reg #(`FR_ATR_TXVAL_0) sr_atr_txval_0(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_txval_0));
setting_reg #(`FR_ATR_RXVAL_0) sr_atr_rxval_0(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_rxval_0));
setting_reg #(`FR_ATR_MASK_1) sr_atr_mask_1(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_mask_1));
setting_reg #(`FR_ATR_TXVAL_1) sr_atr_txval_1(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_txval_1));
setting_reg #(`FR_ATR_RXVAL_1) sr_atr_rxval_1(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_rxval_1));
setting_reg #(`FR_ATR_MASK_2) sr_atr_mask_2(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_mask_2));
setting_reg #(`FR_ATR_TXVAL_2) sr_atr_txval_2(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_txval_2));
setting_reg #(`FR_ATR_RXVAL_2) sr_atr_rxval_2(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_rxval_2));
setting_reg #(`FR_ATR_MASK_3) sr_atr_mask_3(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_mask_3));
setting_reg #(`FR_ATR_TXVAL_3) sr_atr_txval_3(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_txval_3));
setting_reg #(`FR_ATR_RXVAL_3) sr_atr_rxval_3(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_rxval_3));
//setting_reg #(`FR_ATR_CTL) sr_atr_ctl(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_ctl));
setting_reg #(`FR_ATR_TX_DELAY) sr_atr_tx_delay(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_tx_delay));
setting_reg #(`FR_ATR_RX_DELAY) sr_atr_rx_delay(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_rx_delay));
assign atr_ctl = 1'b1;
atr_delay atr_delay(.clk_i(master_clk),.rst_i(tx_dsp_reset),.ena_i(atr_ctl),.tx_empty_i(tx_empty),
.tx_delay_i(atr_tx_delay),.rx_delay_i(atr_rx_delay),.atr_tx_o(transmit_now));
wire [15:0] atr_selected_0 = transmit_now ? atr_txval_0 : atr_rxval_0;
wire [15:0] io_0 = ({{16{atr_ctl}}} & atr_mask_0 & atr_selected_0) | (~({{16{atr_ctl}}} & atr_mask_0) & io_0_reg);
wire [15:0] atr_selected_1 = transmit_now ? atr_txval_1 : atr_rxval_1;
wire [15:0] io_1 = ({{16{atr_ctl}}} & atr_mask_1 & atr_selected_1) | (~({{16{atr_ctl}}} & atr_mask_1) & io_1_reg);
wire [15:0] atr_selected_2 = transmit_now ? atr_txval_2 : atr_rxval_2;
wire [15:0] io_2 = ({{16{atr_ctl}}} & atr_mask_2 & atr_selected_2) | (~({{16{atr_ctl}}} & atr_mask_2) & io_2_reg);
wire [15:0] atr_selected_3 = transmit_now ? atr_txval_3 : atr_rxval_3;
wire [15:0] io_3 = ({{16{atr_ctl}}} & atr_mask_3 & atr_selected_3) | (~({{16{atr_ctl}}} & atr_mask_3) & io_3_reg);
assign reg_0 = debug_en[0] ? debug_0 : txa_refclk[7] ? {io_0[15:1],txaclk} : io_0;
assign reg_1 = debug_en[1] ? debug_1 : rxa_refclk[7] ? {io_1[15:1],rxaclk} : io_1;
assign reg_2 = debug_en[2] ? debug_2 : txb_refclk[7] ? {io_2[15:1],txbclk} : io_2;
assign reg_3 = debug_en[3] ? debug_3 : rxb_refclk[7] ? {io_3[15:1],rxbclk} : io_3;
endmodule // master_control
|
//#############################################################################
//# Function: 6:1 one hot mux #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_mux6 #(parameter DW = 1 ) // width of mux
(
input sel5,
input sel4,
input sel3,
input sel2,
input sel1,
input sel0,
input [DW-1:0] in5,
input [DW-1:0] in4,
input [DW-1:0] in3,
input [DW-1:0] in2,
input [DW-1:0] in1,
input [DW-1:0] in0,
output [DW-1:0] out //selected data output
);
assign out[DW-1:0] = ({(DW){sel0}} & in0[DW-1:0] |
{(DW){sel1}} & in1[DW-1:0] |
{(DW){sel2}} & in2[DW-1:0] |
{(DW){sel3}} & in3[DW-1:0] |
{(DW){sel4}} & in4[DW-1:0] |
{(DW){sel5}} & in5[DW-1:0]);
endmodule // oh_mux6
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:06:26 10/22/2009
// Design Name:
// Module Name: data_processing
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module coupled_data_processing(
input clk,
input rst,
input slow_clk,
input [12:0] p2_sigma_in,
input [12:0] p2_delta_in,
input [12:0] p3_sigma_in,
input [12:0] p3_delta_in,
input store_strb,
input p2_bunch_strb,
input p3_bunch_strb,
input feedbck_en,
input delay_loop_en,
input const_dac_en,
input [12:0] const_dac_out,
input [6:0] p2_lut_dinb,
input [14:0] p2_lut_addrb,
input p2_lut_web,
input [6:0] p3_lut_dinb,
input [14:0] p3_lut_addrb,
input p3_lut_web,
input [12:0] b2_offset,
input [12:0] b3_offset,
input [6:0] fir_k1,
output [6:0] p2_lut_doutb,
output [6:0] p3_lut_doutb,
output reg [12:0] amp_drive,
output reg dac_en
);
// synthesis attribute dontkeep of amp_drive is "true";
// **** Synchronise the bunch offsets and weight factors ****
reg [12:0] b2_offset_a, b2_offset_b, b3_offset_a, b3_offset_b;
reg [12:0] b2_offset_c, b2_offset_d, b3_offset_c, b3_offset_d;
reg [6:0] fir_k1_a, fir_k1_b;
always @(posedge clk or posedge rst) begin
if (rst) begin
b2_offset_a <= 0;
b3_offset_a <= 0;
b2_offset_b <= 0;
b3_offset_b <= 0;
b2_offset_c <= 0;
b3_offset_c <= 0;
b2_offset_d <= 0;
b3_offset_d <= 0;
fir_k1_a <= 0;
fir_k1_b <= 0;
end else begin
b2_offset_a <= b2_offset;
b3_offset_a <= b3_offset;
b2_offset_b <= b2_offset_a;
b3_offset_b <= b3_offset_a;
b2_offset_c <= b2_offset_b;
b3_offset_c <= b3_offset_b;
b2_offset_d <= b2_offset_c;
b3_offset_d <= b3_offset_c;
fir_k1_a <= fir_k1;
fir_k1_b <= fir_k1_a;
end
end
// **** Strobe chain s ****
//
// The incoming bunch strobes are passed through a register chain, allowing
// various enables to be set at the correct time. Finally they are used
// to clock the DAC
//
// The P3 strobe arrives latest, and is used to drive the FB loop and DAC.
// The P2 strobe is used to calculate the P2 component of the kick, then added
// into the P3 delay loop and into the FIR tap calculator
wire zero_strb;
reg p3_bunch_strb_a, p3_bunch_strb_b, p3_bunch_strb_c, p3_bunch_strb_d, p3_bunch_strb_e, p3_bunch_strb_f, p3_bunch_strb_g, p3_bunch_strb_h;
always @(posedge clk or posedge rst) begin
if (rst) begin
p3_bunch_strb_a <= 0;
p3_bunch_strb_b <= 0;
p3_bunch_strb_c <= 0;
p3_bunch_strb_d <= 0;
p3_bunch_strb_e <= 0;
p3_bunch_strb_f <= 0;
p3_bunch_strb_g <= 0;
p3_bunch_strb_h <= 0;
end else begin
p3_bunch_strb_a <= p3_bunch_strb | zero_strb;
// synthesis attribute shreg_extract of p3_bunch_strb_a is "no";
p3_bunch_strb_b <= p3_bunch_strb_a;
// synthesis attribute shreg_extract of p3_bunch_strb_b is "no";
p3_bunch_strb_c <= p3_bunch_strb_b;
// synthesis attribute shreg_extract of p3_bunch_strb_c is "no";
p3_bunch_strb_d <= p3_bunch_strb_c;
// synthesis attribute shreg_extract of p3_bunch_strb_d is "no";
p3_bunch_strb_e <= p3_bunch_strb_d;
// synthesis attribute shreg_extract of p3_bunch_strb_e is "no";
p3_bunch_strb_f <= p3_bunch_strb_e;
// synthesis attribute shreg_extract of p3_bunch_strb_f is "no";
p3_bunch_strb_g <= p3_bunch_strb_f;
// synthesis attribute shreg_extract of p3_bunch_strb_g is "no";
p3_bunch_strb_h <= p3_bunch_strb_g;
// synthesis attribute shreg_extract of p3_bunch_strb_h is "no";
end
end
reg p2_bunch_strb_a, p2_bunch_strb_b, p2_bunch_strb_c, p2_bunch_strb_d, p2_bunch_strb_e, p2_bunch_strb_f, p2_bunch_strb_g, p2_bunch_strb_h;
always @(posedge clk or posedge rst) begin
if (rst) begin
p2_bunch_strb_a <= 0;
p2_bunch_strb_b <= 0;
p2_bunch_strb_c <= 0;
p2_bunch_strb_d <= 0;
p2_bunch_strb_e <= 0;
p2_bunch_strb_f <= 0;
p2_bunch_strb_g <= 0;
p2_bunch_strb_h <= 0;
end else begin
p2_bunch_strb_a <= p2_bunch_strb | zero_strb;
// synthesis attribute shreg_extract of p2_bunch_strb_a is "no";
p2_bunch_strb_b <= p2_bunch_strb_a;
// synthesis attribute shreg_extract of p2_bunch_strb_b is "no";
p2_bunch_strb_c <= p2_bunch_strb_b;
// synthesis attribute shreg_extract of p2_bunch_strb_c is "no";
p2_bunch_strb_d <= p2_bunch_strb_c;
// synthesis attribute shreg_extract of p2_bunch_strb_d is "no";
p2_bunch_strb_e <= p2_bunch_strb_d;
// synthesis attribute shreg_extract of p2_bunch_strb_e is "no";
p2_bunch_strb_f <= p2_bunch_strb_e;
// synthesis attribute shreg_extract of p2_bunch_strb_f is "no";
p2_bunch_strb_g <= p2_bunch_strb_f;
// synthesis attribute shreg_extract of p2_bunch_strb_g is "no";
p2_bunch_strb_h <= p2_bunch_strb_g;
// synthesis attribute shreg_extract of p2_bunch_strb_h is "no";
end
end
// **** Monitor strobes ****
//
// Detect store_strb falling edge and 'inject' a zero_strb into the bunch_strb
// chain to zero the dac outside of active ring clock cycle
reg store_strb_a, store_strb_b;
always@(posedge clk or posedge rst) begin
if (rst) begin
store_strb_a <= 0;
store_strb_b <= 0;
end else begin
store_strb_a <= store_strb;
store_strb_b <= store_strb_a;
end
end
assign zero_strb = ~store_strb_a & store_strb_b;
// Count p3 bunch strobes
reg [1:0] bunch_count;
always @(posedge clk or posedge rst) begin
if (rst) begin
bunch_count <= 0;
end else begin
if (zero_strb) begin
bunch_count <= 0;
end else begin
if (p3_bunch_strb_g & store_strb) begin
bunch_count <= bunch_count + 1;
end
end
end
end
// ##########################################################################
// ###### Calculate P2 contribution to kick and store in p2_store_reg #######
// **** Instantiation of P2 LUT ****
//
// For charge normalisation, load 4096*const*(1/addra)
// For non-charge norm, load 4096*const for all locations
// The MS 7 bits of data port a are unused
wire [27:0] p2_lut_temp;
wire [20:0] p2_lut_out;
assign p2_lut_out = p2_lut_temp[20:0];
ram_13x28_15x7 p2_lut (
.clka(clk),
.dina(), // Bus [27 : 0]
.addra(p2_sigma_in), // Bus [12 : 0]
.wea(1'b0), // Bus [0 : 0]
.douta(p2_lut_temp), // Bus [27 : 0]
.clkb(slow_clk),
.dinb(p2_lut_dinb), // Bus [6 : 0]
.addrb(p2_lut_addrb), // Bus [14 : 0]
.web(p2_lut_web), // Bus [0 : 0]
.doutb(p2_lut_doutb)); // Bus [6 : 0]
// Register P2 LUT output
reg [20:0] p2_lut_reg;
always @(posedge clk) p2_lut_reg <= p2_lut_out;
// **** Pipeline the P2 difference signal during LUT operation ****
//
reg [12:0] p2_delta_a, p2_delta_b;
always @(posedge clk or posedge rst) begin
if (rst) begin
p2_delta_a <= 0;
p2_delta_b <= 0;
end else begin
p2_delta_a <= p2_delta_in;
// synthesis attribute shreg_extract of p2_delta_a is "no";
p2_delta_b <= p2_delta_a;
// synthesis attribute shreg_extract of p2_delta_b is "no";
end
end
// **** Instantiate P2 multiplier ****
//
// This multiplier forms the const*D/S from the P2 LUT output and difference,
// there is no delay loop. It's output is 48-bit and is stored in P2_store_reg
// Inputs 21-bit and 13-bit, plus a 48-bit carry in to the adder. 3 cycle latency
wire [47:0] p2_mac_out;
FB_MULT_ADD p2_mult_add (
.A_IN(p2_lut_reg),
.B_IN(p2_delta_b),
.CEMULTCARRYIN_IN(1'b0),
.CLK_IN(clk),
.C_IN(48'b0),
.P_OUT(p2_mac_out)
);
// Store the P2 contribution when the p2 bunch strobe reaches register 'e' in its chain
reg [47:0] p2_store_reg;
always @(posedge clk or posedge rst) begin
if (rst) begin
p2_store_reg <= 0;
end else begin
if (zero_strb) begin
p2_store_reg <= 48'b0;
end else begin
if (p2_bunch_strb_e & store_strb) begin
p2_store_reg <= p2_mac_out;
end
end
end
end
// ###########################################################################
// ###### Process P3 sum and difference signals ready for position calc ######
// **** Instantiation of p3 LUT ****
//
// For charge normalisation, load 4096*const*(1/addra)
// For non-charge norm, load 4096*const for all locations
// The MS 7 bits of data port a are unused
wire [27:0] p3_lut_temp;
wire [20:0] p3_lut_out;
assign p3_lut_out = p3_lut_temp[20:0];
ram_13x28_15x7 p3_lut (
.clka(clk),
.dina(), // Bus [27 : 0]
.addra(p3_sigma_in), // Bus [12 : 0]
.wea(1'b0), // Bus [0 : 0]
.douta(p3_lut_temp), // Bus [27 : 0]
.clkb(slow_clk),
.dinb(p3_lut_dinb), // Bus [6 : 0]
.addrb(p3_lut_addrb), // Bus [14 : 0]
.web(p3_lut_web), // Bus [0 : 0]
.doutb(p3_lut_doutb)); // Bus [6 : 0]
// Register p3 LUT output
reg [20:0] p3_lut_reg;
always @(posedge clk) p3_lut_reg <= p3_lut_out;
// **** Pipeline the p3 difference signal during LUT operation ****
reg [12:0] p3_delta_a, p3_delta_b;
always @(posedge clk or posedge rst) begin
if (rst) begin
p3_delta_a <= 0;
p3_delta_b <= 0;
end else begin
p3_delta_a <= p3_delta_in;
// synthesis attribute shreg_extract of p3_delta_a is "no";
p3_delta_b <= p3_delta_a;
// synthesis attribute shreg_extract of p3_delta_b is "no";
end
end
// ##########################################################################
// ####################### Calculate FB signal ##############################
//
// The P3 S and D are multiplied and added to the delay loop. The delay loop
// contains the P2 contribution, FIR correction and banana correction before P3
// signals arrive
//// **** Instantiate main P3 feedback multiplier/adder ****
////
//// This multiplier/adder forms the const*D/S from the P3 LUT output and difference,
//// then adds in the value of the delay loop. It's output is 48-bit and goes
//// on to form the feedback signal
//// Inputs 21-bit and 13-bit, plus a 48-bit carry in to the adder. 3 cycle latency
wire [47:0] delay_loop_out;
wire [47:0] fb_mac_out;
FB_MULT_ADD feedback_mult_add (
.A_IN(p3_lut_reg),
.B_IN(p3_delta_b),
.CEMULTCARRYIN_IN(1'b0),
.CLK_IN(clk),
.C_IN(delay_loop_out),
.P_OUT(fb_mac_out)
);
// ##########################################################################
// ####################### Calculate FIR tap input ##########################
//
// The scaled P2 and P3 positions used to calculate the kick are stored in fir_tap1
// ready to be scaled and added into the feedback's delay loop
// This is done in parallel so the latency through the FB loop itself can be minimal
// **** Instantiate P3 multiplier for FIR ****
//
// This multiplier forms the const*D/S from the P3 LUT output and difference,
// and the P2 store is added in. Output shifted down then stored in fir_tap1
wire [47:0] fir_mult_out;
FB_MULT_ADD fir_mult_add (
.A_IN(p3_lut_reg),
.B_IN(p3_delta_b),
.CEMULTCARRYIN_IN(1'b0),
.CLK_IN(clk),
.C_IN(p2_store_reg),
.P_OUT(fir_mult_out)
);
// **** Store delay loop and FIR 1st tap in their registers ****
//
// Register the fb multiplier/adder output in the delay loop and FIR multiplier
// output in the fir_tap1 register. Do so when bunch strobe is at stage 'e' of its
// pipeline
//
// Reset registers on zero_strobe
//
// Note the FIR1 is divided by 64. This factor returns after multiplication,
// as k1 is a 7-bit twos comp fractional value scaled to -64 to 63.
// It is also saturated at 25 bits before multiplication
//
reg [47:0] delay_loop;
reg [41:0] fir_tap1;
always @(posedge clk or posedge rst) begin
if (rst) begin
delay_loop <= 0;
fir_tap1 <= 0;
end else begin
if (zero_strb) begin
delay_loop <= 48'b0;
fir_tap1 <= 29'b0;
end else begin
if (p3_bunch_strb_e & store_strb) begin
if (delay_loop_en) begin
delay_loop <= fb_mac_out;
end else begin
delay_loop <= 48'b0;
end
fir_tap1 <= fir_mult_out[47:6];
// //Divide by 64 and saturate
// if (fir_mult_out[47]) begin
// // -ve.
// if ( (~fir_mult_out[46:35]) == 12'b0) begin
// fir_tap1 <= fir_mult_out[35:6];
// end else begin
// fir_tap1 <= 30'd536870912;
// end
// end else begin
// // +ve.
// if ( (fir_mult_out[46:35]) == 12'b0) begin
// fir_tap1 <= fir_mult_out[35:6];
// end else begin
// fir_tap1 <= 30'd268435455;
// end
// end
end
end
end
end
// ******* Scale the FIR tap 1 with k1 *********
// FIR_SCALE_MULT A: 30 B:7 Out: 36 3 cycle latency
wire [48:0] fir_scale_mult_out;
//FIR_SCALE_MULT fir_scaling_multiplier (
// .A_IN(fir_tap1),
// .B_IN(fir_k1_b),
// .CARRYIN_IN(1'b0),
// .CE_IN(1'b1),
// .CLK_IN(clk),
// .P_OUT(fir_scale_mult_out)
// );
// FIR_SCALE: 2 DSP48s, 4 cycle latency (optimal). 42 bit x 7 bit = 49 bit output
FIR_SCALE fir_scaling_multiplier (
.clk(clk),
.a(fir_tap1), // Bus [41 : 0]
.b(fir_k1_b), // Bus [6 : 0]
.p(fir_scale_mult_out)); // Bus [48 : 0]
// ##########################################################################
// #################### Add banana cor. to fir value ########################
// Store current bunch correction in delay_loop_banana, left shift 12 to match
// delay loop scale factor and sign extend
reg [47:0] delay_loop_banana;
always @(posedge clk or posedge rst) begin
if (rst) begin
delay_loop_banana <= 0;
end else begin
case (bunch_count)
2'd0: begin
if (b2_offset_b[12]) begin
delay_loop_banana <= {23'd8388607, b2_offset_d, 12'b0};
end else begin
delay_loop_banana <= {23'd0, b2_offset_d, 12'b0};
end
end
2'd1: begin
if (b3_offset_b[12]) begin
delay_loop_banana <= {23'd8388607, b3_offset_d, 12'b0};
end else begin
delay_loop_banana <= {23'd0, b3_offset_d, 12'b0};
end
end
endcase
end
end
// Saturate fir tap at 48 bits
wire [47:0] fir_scaled_sat;
assign fir_scaled_sat = (fir_scale_mult_out[48] & ~fir_scale_mult_out[47]) ? {1'b1, 47'b0} :
(~fir_scale_mult_out[48] & fir_scale_mult_out[47]) ? {1'b0, 47'b1} :
fir_scale_mult_out[47:0];
// Add banana corr. to fir output (2 cycle latency)
wire [47:0] fir_plus_banana;
ADD_48_48 add_fir_banana (
.AB_IN(fir_scaled_sat),
.CEA2_IN(1'b1),
.CEB2_IN(1'b1),
.CEMULTCARRYIN_IN(0),
.CLK_IN(clk),
.C_IN(delay_loop_banana),
.P_OUT(fir_plus_banana)
);
// ##########################################################################
// #################### Add corrections to delay loop #######################
// Two cycle latency
wire [47:0] delay_loop_corr;
ADD_48_48 add_delay_loop (
.AB_IN(delay_loop),
.CEA2_IN(1'b1),
.CEB2_IN(1'b1),
.CEMULTCARRYIN_IN(0),
.CLK_IN(clk),
.C_IN(fir_plus_banana),
.P_OUT(delay_loop_corr)
);
// ##########################################################################
// #################### Add P2 contribution to delay loop ###################
//
// The P2 contribution to the kick will be ready in the delay loop when P3 signals
// hit their multiplier
// One cycle latency
ADD_48_48 add_p2_cont (
.AB_IN(p2_store_reg),
.CEA2_IN(1'b1),
.CEB2_IN(1'b1),
.CEMULTCARRYIN_IN(0),
.CLK_IN(clk),
.C_IN(delay_loop_corr),
.P_OUT(delay_loop_out)
);
// ##########################################################################
// ####################### Output feedback signal ###########################
// **** Perform overflow control ****
//
// The mac output now has its factor 4096 removed. The remaining 35 bits
// are checked and saturated at full-scale dac output.
// Adding factor 48'd2048 is equivelent to 0.5 decimal to round rather
// than truncate, and this is done in the delay loop prior
wire [35:0] fbck_sgnl1;
assign fbck_sgnl1 = fb_mac_out[47:12];
// Saturate the signal at 13 bits
reg [12:0] fbck_sgnl2;
always @(fbck_sgnl1) begin
fbck_sgnl2 = 0; //Prevent latch
if (fbck_sgnl1[35]) begin
// -ve.
if ( (~fbck_sgnl1[34:12]) == 23'b0) begin
fbck_sgnl2 = fbck_sgnl1[12:0];
end else begin
fbck_sgnl2 = 13'b1000000000000;
end
end else begin
// +ve.
if ( (fbck_sgnl1[34:12]) == 23'b0) begin
fbck_sgnl2 = fbck_sgnl1[12:0];
end else begin
fbck_sgnl2 = 13'b0111111111111;
end
end
end
// **** Form final dac code for amplifier drive ****
//
// Multiplex to allow constant output and again to allow zero output
wire [12:0] fbck_sgnl3, fbck_sgnl4;
assign fbck_sgnl3 = const_dac_en ? const_dac_out : fbck_sgnl2;
wire zero_output;
assign zero_output = (~store_strb | ~feedbck_en);
assign fbck_sgnl4 = zero_output ? 13'b0 : fbck_sgnl3;
// Register when strobe reaches e register
always @(posedge clk) if (p3_bunch_strb_e) amp_drive <= fbck_sgnl4;
// **** Produce DAC clock using the bunch strobe chain ****
//
// OR togther the two last registers in the chain
always @(posedge clk) dac_en <= p3_bunch_strb_f | p3_bunch_strb_g;
// synthesis attribute shreg_extract of dac_en is "no";
endmodule
// ########### This code is for an independent feedback loop 22 March 2010 #############
//module data_processing(
// input clk,
// input rst,
// input slow_clk,
// input [12:0] sigma_in,
// input [12:0] delta_in,
// input store_strb,
// input bunch_strb,
// input feedbck_en,
// input delay_loop_en,
// input const_dac_en,
// input [12:0] const_dac_out,
// input [6:0] lut_dinb,
// input [14:0] lut_addrb,
// input lut_web,
// input [12:0] b2_offset,
// input [12:0] b3_offset,
// input [5:0] fir_k1,
// output [6:0] lut_doutb,
// output reg [12:0] amp_drive,
// output reg dac_en
// );
//// synthesis attribute dontkeep of amp_drive is "true";
//
//// **** Synchronise the bunch offsets and weight factors ****
//reg [12:0] b2_offset_a, b2_offset_b, b3_offset_a, b3_offset_b;
//reg [12:0] b2_offset_c, b2_offset_d, b3_offset_c, b3_offset_d;
//reg [11:0] fir_k1_a, fir_k1_b;
//always @(posedge clk or posedge rst) begin
// if (rst) begin
// b2_offset_a <= 0;
// b3_offset_a <= 0;
// b2_offset_b <= 0;
// b3_offset_b <= 0;
// b2_offset_c <= 0;
// b3_offset_c <= 0;
// b2_offset_d <= 0;
// b3_offset_d <= 0;
// fir_k1_a <= 0;
// fir_k1_b <= 0;
// end else begin
// b2_offset_a <= b2_offset;
// b3_offset_a <= b3_offset;
// b2_offset_b <= b2_offset_a;
// b3_offset_b <= b3_offset_a;
// b2_offset_c <= b2_offset_b;
// b3_offset_c <= b3_offset_b;
// b2_offset_d <= b2_offset_c;
// b3_offset_d <= b3_offset_c;
// fir_k1_a <= fir_k1;
// fir_k1_b <= fir_k1_a;
// end
//end
//
//
//// **** Strobe chain ****
////
//// The incoming bunch strobes are passed through a register chain, allowing
//// various enables to be set at the correct time. Finally they are used
//// to clock the DAC
//wire zero_strb;
//reg bunch_strb_a, bunch_strb_b, bunch_strb_c, bunch_strb_d, bunch_strb_e, bunch_strb_f, bunch_strb_g, bunch_strb_h;
//always @(posedge clk or posedge rst) begin
// if (rst) begin
// bunch_strb_a <= 0;
// bunch_strb_b <= 0;
// bunch_strb_c <= 0;
// bunch_strb_d <= 0;
// bunch_strb_e <= 0;
// bunch_strb_f <= 0;
// bunch_strb_g <= 0;
// bunch_strb_h <= 0;
// end else begin
// bunch_strb_a <= bunch_strb | zero_strb;
// // synthesis attribute shreg_extract of bunch_strb_a is "no";
// bunch_strb_b <= bunch_strb_a;
// // synthesis attribute shreg_extract of bunch_strb_b is "no";
// bunch_strb_c <= bunch_strb_b;
// // synthesis attribute shreg_extract of bunch_strb_c is "no";
// bunch_strb_d <= bunch_strb_c;
// // synthesis attribute shreg_extract of bunch_strb_d is "no";
// bunch_strb_e <= bunch_strb_d;
// // synthesis attribute shreg_extract of bunch_strb_e is "no";
// bunch_strb_f <= bunch_strb_e;
// // synthesis attribute shreg_extract of bunch_strb_f is "no";
// bunch_strb_g <= bunch_strb_f;
// // synthesis attribute shreg_extract of bunch_strb_g is "no";
// bunch_strb_h <= bunch_strb_g;
// // synthesis attribute shreg_extract of bunch_strb_h is "no";
// end
//end
//
//
//// **** Monitor strobes ****
////
//// Detect store_strb falling edge and 'inject' a zero_strb into the bunch_strb
//// chain to zero the dac outside of active ring clock cycle
//reg store_strb_a, store_strb_b;
//always@(posedge clk or posedge rst) begin
// if (rst) begin
// store_strb_a <= 0;
// store_strb_b <= 0;
// end else begin
// store_strb_a <= store_strb;
// store_strb_b <= store_strb_a;
// end
//end
//assign zero_strb = ~store_strb_a & store_strb_b;
//
//// Count bunch strobes
//reg [1:0] bunch_count;
//always @(posedge clk or posedge rst) begin
// if (rst) begin
// bunch_count <= 0;
// end else begin
// if (zero_strb) begin
// bunch_count <= 0;
// end else begin
// if (bunch_strb_g & store_strb) begin
// bunch_count <= bunch_count + 1;
// end
// end
// end
//end
//
//
//// **** Instantiation of Gain LUT ****
////
//// For charge normalisation, load 4096*Gain*(1/addra)
//// For non-charge norm, load 4096*Gain for all locations
//// The MS 7 bits of data port a are unused
//wire [27:0] lut_temp;
//wire [20:0] lut_out;
//assign lut_out = lut_temp[20:0];
//ram_13x28_15x7 gain_lut (
// .clka(clk),
// .dina(), // Bus [27 : 0]
// .addra(sigma_in), // Bus [12 : 0]
// .wea(1'b0), // Bus [0 : 0]
// .douta(lut_temp), // Bus [27 : 0]
// .clkb(slow_clk),
// .dinb(lut_dinb), // Bus [6 : 0]
// .addrb(lut_addrb), // Bus [14 : 0]
// .web(lut_web), // Bus [0 : 0]
// .doutb(lut_doutb)); // Bus [6 : 0]
//
//// Register LUT output
//reg [20:0] lut_reg;
// // synthesis attribute dontkeep of lut_reg is "true";
//always @(posedge clk) lut_reg <= lut_out;
//
//
//// **** Pipeline the difference signal during LUT operation ****
////
//reg [12:0] delta_a, delta_b;
// // synthesis attribute dontkeep of delta_a is "true";
// // synthesis attribute dontkeep of delta_b is "true";
//always @(posedge clk or posedge rst) begin
// if (rst) begin
// delta_a <= 0;
// delta_b <= 0;
// end else begin
// delta_a <= delta_in;
// // synthesis attribute shreg_extract of delta_a is "no";
// delta_b <= delta_a;
// // synthesis attribute shreg_extract of delta_b is "no";
// end
//end
//
//
//// **** Instantiate main multiplier/adder ****
////
//// This multiplier/adder forms the G*D/S from the LUT output and difference,
//// then adds in the value of the delay loop. It's output is 48-bit and goes
//// on to form the feedback signal
//// Inputs 21-bit and 13-bit, plus a 48-bit carry in to the adder. 3 cycle latency
//
//wire [47:0] delay_loop_out;
//wire [47:0] mac_out;
//FB_MULT_ADD feedback_mult_add (
// .A_IN(lut_reg),
// .B_IN(delta_b),
// .CEMULTCARRYIN_IN(1'b0),
// .CLK_IN(clk),
// //.C_IN(delay_loop_out + 48'd2048), // 2048 is == 0.5 for rounding
// .C_IN(delay_loop_out),
// .P_OUT(mac_out)
// );
//
//
//// **** Instantiate the FIR multiplier ****
////
//// The FIR requires G*D/S to be stored without the delay loop addition
//// Since multipliers reqire the adder (so the multiplication result from the
//// feedback multiplier/adder can't be pulled out before the delay loop is added),
//// forming G*D/S in parallel means latency can be kept to a minimum in the feedback
//// chain
////
//// This multiplier as for the feedback muli/add but without the carry in.
//
//wire [35:0] fir_mult_out;
//FIR_MULT fir_multiplier (
// .A_IN(lut_reg),
// .B_IN(delta_b),
// .CEMULTCARRYIN_IN(1'b0),
// .CLK_IN(clk),
// .CARRYIN_IN(0),
// .P_OUT(fir_mult_out)
// );
//
//
//// **** Store delay loop and FIR 1st tap in their registers ****
////
//// Register the fb multiplier/adder output in the delay loop and FIR multiplier
//// output in the fir_tap1 register. Do so when bunch strobe is at stage 'c' of its
//// pipeline
////
//// Reset registers on zero_strobe
////
//// Note the FIR1 is divided by 64. This factor returns after multiplication,
//// as k1 is a fractional value scaled to 0-63.
////
//// Add 36'd32 (equiv. to 0.5 decimal) to FIR1 before division to round rather than truncate
////
//// Remove the rounding 2048 from mac out before storing to avoid compounding it
//// over succesive delay loop cycles
//reg [47:0] delay_loop;
//reg [29:0] fir_tap1;
////wire [35:0] fir_tap1_round;
////assign fir_tap1_round = 36'd32 + fir_mult_out;
//
//always @(posedge clk or posedge rst) begin
// if (rst) begin
// delay_loop <= 0;
// fir_tap1 <= 0;
// end else begin
// if (zero_strb) begin
// delay_loop <= 48'b0;
// fir_tap1 <= 30'b0;
// end else begin
// if (bunch_strb_e & store_strb) begin
// if (delay_loop_en) begin
// //delay_loop <= (mac_out + (-48'd2048));
// delay_loop <= mac_out;
// end else begin
// delay_loop <= 48'b0;
// end
// fir_tap1 <= fir_mult_out[35:6];
// end
// end
// end
//end
//
//
//// **** Add the banana correction to the output of the delay loop register ****
////
//// Add a constant to the delay loop depending on the bunch number. The constant
//// is left shifted by 12 to bring it up to the delay loop scale factor
//
//reg [47:0] delay_loop_banana;
////Additional register in delay loop for timing
//reg [47:0] delay_loop_banana_a;
//always @(posedge clk or posedge rst) begin
// if (rst) begin
// delay_loop_banana <= 0;
// delay_loop_banana_a <= 0;
// end else begin
// delay_loop_banana_a <= delay_loop_banana;
// case (bunch_count)
// 2'd0: begin
// if (b2_offset_b[12]) begin
// delay_loop_banana <= delay_loop + {23'd8388607, b2_offset_d, 12'b0};
// end else begin
// delay_loop_banana <= delay_loop + {23'd0, b2_offset_d, 12'b0};
// end
// end
// 2'd1: begin
// if (b3_offset_b[12]) begin
// delay_loop_banana <= delay_loop + {23'd8388607, b3_offset_d, 12'b0};
// end else begin
// delay_loop_banana <= delay_loop + {23'd0, b3_offset_d, 12'b0};
// end
// end
// endcase
// end
//end
//
//// **** Instantiate the delay loop multiplier / adder ****
////
//// This mult/add resides inside the delay loop. It multiplies the stored FIR tap1
//// value with the weighting factor k1, then sums the result with the contents
//// of the delay loop register (which has already been summed with the banana
//// correction). The output of this mult/add is the final delay loop output
////
//// The FIR input is capped at the maximum 30-bits. The k1 is 6-bit, a fractional
//// value scaled by 64 (+ve, must sign extend). Delay loop carry in is 48-bit. 3 cycle latency
//
//DELAY_MULT_ADD delay_loop_mult_add (
// .A_IN(fir_tap1),
// .B_IN({1'b0, fir_k1_b}),
// .CEMULTCARRYIN_IN(1'b0),
// .CLK_IN(clk),
// .C_IN(delay_loop_banana_a),
// .P_OUT(delay_loop_out)
// );
//
//
//// **** Perform overflow control ****
////
//// The mac output now has its factor 4096 removed. The remaining 35 bits
//// are checked and saturated at full-scale dac output.
//
//// Adding factor 48'd2048 is equivelent to 0.5 decimal to round rather
//// than truncate, and this is done in the delay loop prior
//
//wire [35:0] fbck_sgnl1;
//assign fbck_sgnl1 = mac_out[47:12];
//
//// Saturate the signal at 13 bits
//reg [12:0] fbck_sgnl2;
//always @(fbck_sgnl1) begin
// fbck_sgnl2 = 0; //Prevent latch
// if (fbck_sgnl1[35]) begin
// // -ve.
// if ( (~fbck_sgnl1[34:12]) == 23'b0) begin
// fbck_sgnl2 = fbck_sgnl1[12:0];
// end else begin
// fbck_sgnl2 = 13'b1000000000000;
// end
// end else begin
// // +ve.
// if ( (fbck_sgnl1[34:12]) == 23'b0) begin
// fbck_sgnl2 = fbck_sgnl1[12:0];
// end else begin
// fbck_sgnl2 = 13'b0111111111111;
// end
// end
//end
////wire [12:0] fbck_sgnl2;
////assign fbck_sgnl2 = fbck_sgnl1[12:0];
//
//// **** Form final dac code for amplifier drive ****
////
//// Multiplex to allow constant output and again to allow zero output
//wire [12:0] fbck_sgnl3, fbck_sgnl4;
//assign fbck_sgnl3 = const_dac_en ? const_dac_out : fbck_sgnl2;
//
//wire zero_output;
//assign zero_output = (~store_strb | ~feedbck_en);
//assign fbck_sgnl4 = zero_output ? 13'b0 : fbck_sgnl3;
//
//// Register when strobe reaches d register
//always @(posedge clk) if (bunch_strb_e) amp_drive <= fbck_sgnl4;
//
//
//// **** Produce DAC clock using the bunch strobe chain ****
////
//// OR togther the two last registers in the chain
//always @(posedge clk) dac_en <= bunch_strb_f | bunch_strb_g;
// // synthesis attribute shreg_extract of dac_en is "no";
//
//
//
//endmodule
//
|
// DESCRIPTION: Verilator: Verilog Test module
//
// Copyright 2010 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
`ifndef IVERILOG
import "DPI-C" context function int mon_check();
`endif
package somepackage;
int someint /*verilator public_flat_rw*/;
endpackage
module t (/*AUTOARG*/
// Inputs
clk
);
`ifdef USE_DOLLAR_C32
`systemc_header
extern "C" int mon_check();
`verilog
`endif
input clk;
integer status;
wire a, b, x;
A mod_a(/*AUTOINST*/
// Outputs
.x (x),
// Inputs
.clk (clk),
.a (a),
.b (b));
// Test loop
initial begin
`ifdef IVERILOG
status = $mon_check();
`elsif USE_DOLLAR_C32
status = $c32("mon_check()");
`else
status = mon_check();
`endif
if (status!=0) begin
$write("%%Error: t_vpi_module.cpp:%0d: C Test failed\n", status);
$stop;
end
$write("*-* All Finished *-*\n");
$finish;
end
endmodule : t
module A(/*AUTOARG*/
// Outputs
x,
// Inputs
clk, a, b
);
input clk;
input a, b;
output x;
wire y, c;
B mod_b(/*AUTOINST*/
// Outputs
.y (y),
// Inputs
.b (b),
.c (c));
C \mod_c. (/*AUTOINST*/
// Outputs
.x (x),
// Inputs
.clk (clk),
.a (a),
.y (y));
endmodule : A
module B(/*AUTOARG*/
// Outputs
y,
// Inputs
b, c
); /*verilator public_module*/
input b, c;
output reg y;
always @(*) begin : myproc
y = b ^ c;
end
endmodule
module C(/*AUTOARG*/
// Outputs
x,
// Inputs
clk, a, y
);
input clk;
input a, y;
output reg x /* verilator public_flat_rw */;
always @(posedge clk) begin
x <= a & y;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
`define INT_RANGE 31:0
`define INT_RANGE 31:0 // Duplicate identical defs are OK
`define INT_RANGE_MAX 31
`define VECTOR_RANGE 511:0
module t (clk);
// verilator lint_off WIDTH
parameter WIDTH = 16; // Must be a power of 2
parameter WIDTH_LOG2 = 4; // set to log2(WIDTH)
parameter USE_BS = 1; // set to 1 for enable
input clk;
function [`VECTOR_RANGE] func_tree_left;
input [`VECTOR_RANGE] x; // x[width-1:0] is the input vector
reg [`VECTOR_RANGE] flip;
begin
flip = 'd0;
func_tree_left = flip;
end
endfunction
reg [WIDTH-1:0] a; // value to be shifted
reg [WIDTH-1:0] tree_left;
always @(a) begin : barrel_shift
tree_left = func_tree_left (a);
end // barrel_shift
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
a = 5;
end
if (cyc==2) begin
$display ("%x\n",tree_left);
//if (tree_left != 'd15) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
// auto-generated by bsg_ascii_to_rom.py from /mnt/bsg/diskbits/dcjung/bsg/bsg_ip_cores/testing/bsg_noc/bsg_wormhole_router_adapter_in/trace.tr; do not modify
module bsg_trace_rom #(parameter `BSG_INV_PARAM(width_p), parameter `BSG_INV_PARAM(addr_width_p))
(input [addr_width_p-1:0] addr_i
,output logic [width_p-1:0] data_o
);
always_comb case(addr_i)
// ### test params #########
// #
// # payload = 17
// # len_width = 2
// # y = 2
// # x = 2
// #
// # padding = 17
// # flit = 6
// #
// ###########################
// # send packet
0: data_o = width_p ' (27'b0001_11100000110000101_10_00_11); // 0x0F06163
// # recv flits
1: data_o = width_p ' (27'b0010_000000000000000_01100011); // 0x1000063
2: data_o = width_p ' (27'b0010_000000000000000_01100001); // 0x1000061
3: data_o = width_p ' (27'b0010_000000000000000_01110000); // 0x1000070
// # send packet
4: data_o = width_p ' (27'b0001_00001100110011111_01_11_01); // 0x08667DD
// # recv flits
5: data_o = width_p ' (27'b0010_000000000000000_11011101); // 0x10000DD
6: data_o = width_p ' (27'b0010_000000000000000_01100111); // 0x1000067
// # send packet
7: data_o = width_p ' (27'b0001_00001100110011111_00_11_01); // 0x08667CD
// # recv flits
8: data_o = width_p ' (27'b0010_000000000000000_11001101); // 0x10000CD
// # done
9: data_o = width_p ' (27'b0011_00000000000000000_000000); // 0x1800000
default: data_o = 'X;
endcase
endmodule
`BSG_ABSTRACT_MODULE(bsg_trace_rom)
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate the ? operator
module main;
reg globvar;
reg [3:0] bvec,var1,var2,var3;
reg cond, a,b,out1,out2;
reg error;
initial
begin
error = 0;
bvec = 4'bzx10 ;
for(var1 = 0; var1 <= 3; var1 = var1 + 1)
for(var2 = 0; var2 <= 3; var2 = var2 + 1)
for(var3 = 0; var3 <= 3; var3 = var3 + 1)
begin
cond = bvec[var1];
a = bvec[var2];
b = bvec[var3];
out1 = cond ? a: b ;
if(cond) out2 = a ;
else out2 = b;
if(out1 != out2)
begin
$display("FAILED - %b %b %b %b %b",cond,a,b,out1,out2);
error = 1;
end
end
if(error == 0)
$display("PASSED");
end
endmodule // main
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
// Date : Mon Sep 18 12:32:27 2017
// Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub
// C:/Projects/srio_test/srio_test/srio_test.srcs/sources_1/ip/vio_0/vio_0_stub.v
// Design : vio_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7k325tffg676-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "vio,Vivado 2016.3" *)
module vio_0(clk, probe_in0, probe_in1, probe_in2, probe_in3)
/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[0:0],probe_in1[0:0],probe_in2[0:0],probe_in3[0:0]" */;
input clk;
input [0:0]probe_in0;
input [0:0]probe_in1;
input [0:0]probe_in2;
input [0:0]probe_in3;
endmodule
|
/**
* bp2wb_convertor.v
* DESCRIPTION: THIS MODULE ADAPTS BP MEMORY BUS TO 64-BIT WISHBONE
*/
module bp2wb_convertor
import bp_common_pkg::*;
import bp_me_pkg::*;
#(parameter bp_params_e bp_params_p = e_bp_unicore_no_l2_cfg
`declare_bp_proc_params(bp_params_p)
`declare_bp_bedrock_mem_if_widths(paddr_width_p, cce_block_width_p, lce_id_width_p, lce_assoc_p, cce)
// , parameter [paddr_width_p-1:0] dram_offset_p = '0
, localparam num_block_words_lp = cce_block_width_p / 64
, localparam num_block_bytes_lp = cce_block_width_p / 8
, localparam num_word_bytes_lp = dword_width_gp / 8 //gp correct?
, localparam block_offset_bits_lp = `BSG_SAFE_CLOG2(num_block_bytes_lp)
, localparam word_offset_bits_lp = `BSG_SAFE_CLOG2(num_block_words_lp)
, localparam byte_offset_bits_lp = `BSG_SAFE_CLOG2(num_word_bytes_lp)
, localparam wbone_data_width = 64
, localparam wbone_addr_ubound = paddr_width_p
, localparam mem_granularity = 64 //TODO: adapt selection bit parametrized
, localparam wbone_addr_lbound = 3 //`BSG_SAFE_CLOG2(wbone_data_width / mem_granularity) //dword granularity
, localparam total_datafetch_cycle_lp = cce_block_width_p / wbone_data_width
, localparam total_datafetch_cycle_width = `BSG_SAFE_CLOG2(total_datafetch_cycle_lp)
, localparam cached_addr_base = 32'h7000_0000//6000_0000 //32'h4000_4000//
)
( input clk_i
,(* mark_debug = "true" *) input reset_i
// BP side
,(* mark_debug = "true" *) input [cce_mem_msg_width_lp-1:0] mem_cmd_i
,(* mark_debug = "true" *) input mem_cmd_v_i
,(* mark_debug = "true" *) output mem_cmd_ready_o
, output [cce_mem_msg_width_lp-1:0] mem_resp_o
, (* mark_debug = "true" *) output mem_resp_v_o
, (* mark_debug = "true" *) input mem_resp_yumi_i
// Wishbone side
, (* mark_debug = "true" *) input [63:0] dat_i
, (* mark_debug = "true" *) output logic [63:0] dat_o
, (* mark_debug = "true" *) input ack_i
, input err_i
// , input rty_i
, (* mark_debug = "true" *) output logic [wbone_addr_ubound-wbone_addr_lbound-1:0] adr_o//TODO: Double check!!!
, (* mark_debug = "true" *) output logic stb_o
, output cyc_o
, output [7:0] sel_o //TODO: double check!!!
, (* mark_debug = "true" *) output we_o
, output [2:0] cti_o //TODO: hardwire in Litex
, output [1:0] bte_o //TODO: hardwire in Litex
, input rty_i //TODO: hardwire in Litex
);
`declare_bp_bedrock_mem_if(paddr_width_p, cce_block_width_p, lce_id_width_p, lce_assoc_p, cce);
//locals
(* mark_debug = "true" *) logic [total_datafetch_cycle_width:0] ack_ctr = 0;
(* mark_debug = "true" *) bp_bedrock_cce_mem_msg_s mem_cmd_cast_i, mem_resp_cast_o, mem_cmd_debug, mem_cmd_debug2;
(* mark_debug = "true" *) logic ready_li, v_li, stb_justgotack;
(* mark_debug = "true" *) logic [cce_block_width_p-1:0] data_lo;
(* mark_debug = "true" *) logic [cce_block_width_p-1:0] data_li;
(* mark_debug = "true" *) wire [paddr_width_p-1:0] mem_cmd_addr_l;
(* mark_debug = "true" *) logic set_stb;
//Handshaking between Wishbone and BlackParrot through convertor
//3.1.3:At every rising edge of [CLK_I] the terminating signal(ACK) is sampled. If it
//is asserted, then [STB_O] is negated.
assign ready_li = ( ack_ctr == 0 ) & !set_stb & !mem_resp_v_o;
assign mem_cmd_ready_o = ready_li;//!stb_o then ready to take!
// assign v_li = (ack_ctr == total_datafetch_cycle_lp-1);
assign mem_resp_v_o = v_li;
assign stb_o = (set_stb) && !stb_justgotack;
assign cyc_o = stb_o;
assign sel_o = mem_cmd_r.header.size == e_bedrock_msg_size_4 ? ('h0F << wr_byte_shift) : 'hFF;
assign cti_o = 0;
assign bte_o = 0;
initial begin
ack_ctr = 0;
end
//Flip stb after each ack--->RULE 3.20:
// Every time we get an ACK from WB, increment counter until the counter reaches to total_datafetch_cycle_lp
always_ff @(posedge clk_i)
begin
if(reset_i)
begin
ack_ctr <= 0;
set_stb <= 0;
v_li <=0;
end
// else if (v_li)
// begin
else if (mem_resp_yumi_i)
begin
v_li <= 0;
ack_ctr <= 0;
end
// end
else if (mem_cmd_v_i)
begin
//data_li <= 0;
set_stb <= 1;
v_li <= 0;
stb_justgotack <= 0;
end
else
begin
if (ack_i)//stb should be negated after ack
begin
stb_justgotack <= 1;
data_li[(ack_ctr*wbone_data_width) +: wbone_data_width] <= dat_i;
if ((ack_ctr == total_datafetch_cycle_lp-1) || (mem_cmd_addr_l < cached_addr_base && mem_cmd_r.header.msg_type == e_bedrock_mem_uc_wr )) //if uncached store, just one cycle is fine
begin
v_li <=1;
set_stb <= 0;
end
else
ack_ctr <= ack_ctr + 1;
end
else
begin
stb_justgotack <= 0;
v_li <=0;
end
end
end
//Packet Pass from BP to BP2WB
assign mem_cmd_cast_i = mem_cmd_i;
bp_bedrock_cce_mem_msg_s mem_cmd_r;
bsg_dff_reset_en
#(.width_p(cce_mem_msg_width_lp))
mshr_reg
(.clk_i(clk_i)
,.reset_i(reset_i)
,.en_i(mem_cmd_v_i)//when
,.data_i(mem_cmd_i)
,.data_o(mem_cmd_r)
);
//Addr && Data && Command Pass from BP2WB to WB
logic [wbone_addr_lbound-1:0] throw_away;
assign mem_cmd_addr_l = mem_cmd_r.header.addr;
assign data_lo = mem_cmd_r.data;
logic [39:0] mem_cmd_addr_l_zero64;
always_comb begin
if( mem_cmd_addr_l < cached_addr_base )
begin
adr_o = mem_cmd_addr_l[wbone_addr_ubound-1:wbone_addr_lbound];//no need to change address for uncached stores/loads
dat_o = mem_cmd_r.header.size == e_bedrock_msg_size_4 ? data_lo[(0*wbone_data_width) +: wbone_data_width] << rd_byte_offset*8 : data_lo[(0*wbone_data_width) +: wbone_data_width];//unchached data is stored in LS 64bits
end
else
begin
mem_cmd_addr_l_zero64 = mem_cmd_addr_l >> 6 << 6;
{adr_o,throw_away} = mem_cmd_addr_l_zero64 + (ack_ctr*8);//TODO:careful
dat_o = mem_cmd_r.header.size == e_bedrock_msg_size_4 ? data_lo[(ack_ctr*wbone_data_width) +: wbone_data_width] << rd_byte_offset*8 : data_lo[(ack_ctr*wbone_data_width) +: wbone_data_width];
end
end
assign we_o = (mem_cmd_r.header.msg_type inside {e_bedrock_mem_uc_wr, e_bedrock_mem_wr});
//Data Pass from BP2WB to BP
wire [cce_block_width_p-1:0] rd_word_offset = mem_cmd_r.header.addr[3+:3];
wire [cce_block_width_p-1:0] rd_byte_offset = mem_cmd_r.header.addr[0+:3];
wire [cce_block_width_p-1:0] wr_byte_shift = rd_byte_offset;
wire [cce_block_width_p-1:0] rd_bit_shift = rd_word_offset*64; // We rely on receiver to adjust bits
(* mark_debug = "true" *) wire [cce_block_width_p-1:0] data_li_resp = (mem_cmd_r.header.msg_type == e_bedrock_mem_uc_rd)
? data_li >> rd_bit_shift
: data_li;
assign mem_resp_cast_o = '{data : data_li_resp
,header :'{payload : mem_cmd_r.header.payload
,size : mem_cmd_r.header.size
,addr : mem_cmd_r.header.addr
,subop : mem_cmd_r.header.subop
,msg_type: mem_cmd_r.header.msg_type
}
};
assign mem_resp_o = mem_resp_cast_o;
/*********************************************/
/*DEBUG SECTION*/
/*wire [3:0] fake_msg_type;
wire [10:0] fake_payload;
wire [2:0] fake_size;
wire [39:0] fake_addr;
assign fake_payload = mem_cmd_r.header.payload;
assign fake_size = mem_cmd_r.header.size;
assign fake_addr = mem_cmd_r.header.addr;
assign fake_msg_type = mem_cmd_r.header.msg_type;
*/
/*(* mark_debug = "true" *) logic debug_wire;
initial begin
debug_wire = 0;
end
assign mem_cmd_debug = mem_cmd_i;
always_ff @(posedge clk_i)
debug_wire <= (ack_i && mem_cmd_debug.header.addr >= 32'h80000000);
always_ff @(posedge clk_i)
begin
if(mem_cmd_v_i && mem_cmd_debug.header.addr <= 32'h60000000)
begin
debug_wire <= 1;
// $display("addr == %x", mem_cmd_debug.header.addr);
end
/* if (mem_resp_v_o && debug_ctr < 64 && mem_cmd_debug.header.addr >= 32'h80000000)
begin
debug_gotdata[((debug_ctr-1)*512) +: 512] <= data_li_resp;
$display("data == %x", data_li_resp);
end*/
// end
wire [3:0] typean;
assign typean = mem_cmd_r.header.msg_type;
endmodule
|
//-------------------------------------------------------------------
//
// COPYRIGHT (C) 2014, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact : [email protected]
//
//-------------------------------------------------------------------
//
// Filename : fetch_cur_luma.v
// Author : Yufeng Bai
// Email : [email protected]
//
//-------------------------------------------------------------------
//
// Modified : 2015-09-02 by HLL
// Description : rotate by sys_start_i
// Modified : 2015-09-05 by HLL
// Description : intra supported
// Modified : 2015-09-07 by HLL
// Description : pre_intra supported
//
//-------------------------------------------------------------------
`include "enc_defines.v"
module fetch_cur_luma (
clk ,
rstn ,
sysif_start_i ,
sysif_type_i ,
pre_i_4x4_x_i ,
pre_i_4x4_y_i ,
pre_i_4x4_idx_i ,
pre_i_sel_i ,
pre_i_size_i ,
pre_i_rden_i ,
pre_i_pel_o ,
fime_cur_4x4_x_i ,
fime_cur_4x4_y_i ,
fime_cur_4x4_idx_i ,
fime_cur_sel_i ,
fime_cur_size_i ,
fime_cur_rden_i ,
fime_cur_pel_o ,
fme_cur_4x4_x_i ,
fme_cur_4x4_y_i ,
fme_cur_4x4_idx_i ,
fme_cur_sel_i ,
fme_cur_size_i ,
fme_cur_rden_i ,
fme_cur_pel_o ,
mc_cur_4x4_x_i ,
mc_cur_4x4_y_i ,
mc_cur_4x4_idx_i ,
mc_cur_sel_i ,
mc_cur_size_i ,
mc_cur_rden_i ,
mc_cur_pel_o ,
db_cur_4x4_x_i ,
db_cur_4x4_y_i ,
db_cur_4x4_idx_i ,
db_cur_sel_i ,
db_cur_size_i ,
db_cur_rden_i ,
db_cur_pel_o ,
ext_load_done_i ,
ext_load_data_i ,
ext_load_addr_i ,
ext_load_valid_i
);
// ********************************************
//
// PARAMETER DECLARATION
//
// ********************************************
parameter INTRA = 0 ,
INTER = 1 ;
// ********************************************
//
// INPUT / OUTPUT DECLARATION
//
// ********************************************
input [1-1:0] clk ; // clk signal
input [1-1:0] rstn ; // asynchronous reset
input sysif_start_i ;
input sysif_type_i ;
input [4-1 : 0] pre_i_4x4_x_i ; // pre_i current lcu x
input [4-1 : 0] pre_i_4x4_y_i ; // pre_i current lcu y
input [5-1 : 0] pre_i_4x4_idx_i ; // pre_i current lcu idx
input [1-1 : 0] pre_i_sel_i ; // pre_i current lcu chroma/luma sel
input [2-1 : 0] pre_i_size_i ; // pre_i current lcu size :4x4
input [1-1 : 0] pre_i_rden_i ; // pre_i current lcu read enable
output [32*`PIXEL_WIDTH-1 : 0] pre_i_pel_o ; // pre_i current lcu pixel
input [4-1:0] fime_cur_4x4_x_i ; // fime current lcu x
input [4-1:0] fime_cur_4x4_y_i ; // fime current lcu y
input [5-1:0] fime_cur_4x4_idx_i ; // fime current lcu idx
input [1-1:0] fime_cur_sel_i ; // fime current lcu chroma/luma sel
input [3-1:0] fime_cur_size_i ; // "fime current lcu size :4x4
input [1-1:0] fime_cur_rden_i ; // fime current lcu read enable
output [64*`PIXEL_WIDTH-1:0] fime_cur_pel_o ; // fime current lcu pixel
input [4-1:0] fme_cur_4x4_x_i ; // fme current lcu x
input [4-1:0] fme_cur_4x4_y_i ; // fme current lcu y
input [5-1:0] fme_cur_4x4_idx_i ; // fme current lcu idx
input [1-1:0] fme_cur_sel_i ; // fme current lcu chroma/luma sel
input [2-1:0] fme_cur_size_i ; // "fme current lcu size :4x4
input [1-1:0] fme_cur_rden_i ; // fme current lcu read enable
output [32*`PIXEL_WIDTH-1:0] fme_cur_pel_o ; // fme current lcu pixel
input [4-1:0] mc_cur_4x4_x_i ; // mc current lcu x
input [4-1:0] mc_cur_4x4_y_i ; // mc current lcu y
input [5-1:0] mc_cur_4x4_idx_i ; // mc current lcu idx
input [1-1:0] mc_cur_sel_i ; // mc current lcu chroma/luma sel
input [2-1:0] mc_cur_size_i ; // "mc current lcu size :4x4
input [1-1:0] mc_cur_rden_i ; // mc current lcu read enable
output [32*`PIXEL_WIDTH-1:0] mc_cur_pel_o ; // mc current lcu pixel
input [4-1:0] db_cur_4x4_x_i ; // db current lcu x
input [4-1:0] db_cur_4x4_y_i ; // db current lcu y
input [5-1:0] db_cur_4x4_idx_i ; // db current lcu idx
input [1-1:0] db_cur_sel_i ; // db current lcu chroma/luma sel
input [2-1:0] db_cur_size_i ; // "db current lcu size :4x4
input [1-1:0] db_cur_rden_i ; // db current lcu read enable
output [32*`PIXEL_WIDTH-1:0] db_cur_pel_o ; // db current lcu pixel
input [1-1:0] ext_load_done_i ; // load current lcu done
input [32*`PIXEL_WIDTH-1:0] ext_load_data_i ; // load current lcu data
input [7-1:0] ext_load_addr_i ;
input [1-1:0] ext_load_valid_i ; // load current lcu data valid
// ********************************************
//
// WIRE / REG DECLARATION
//
// ********************************************
reg [3-1:0] rotate ; // rotatation counter
reg duo_rotate ; // rotatation counter
reg [4-1:0] cur_00_4x4_x ;
reg [4-1:0] cur_00_4x4_y ;
reg [5-1:0] cur_00_idx ;
reg [1-1:0] cur_00_sel ;
reg [2-1:0] cur_00_size ;
reg [1-1:0] cur_00_ren ;
reg [32*`PIXEL_WIDTH-1:0] cur_00_pel ;
reg [4-1:0] cur_01_4x4_x ;
reg [4-1:0] cur_01_4x4_y ;
reg [5-1:0] cur_01_idx ;
reg [1-1:0] cur_01_sel ;
reg [2-1:0] cur_01_size ;
reg [1-1:0] cur_01_ren ;
reg [32*`PIXEL_WIDTH-1:0] cur_01_pel ;
reg [4-1:0] cur_02_4x4_x ;
reg [4-1:0] cur_02_4x4_y ;
reg [5-1:0] cur_02_idx ;
reg [1-1:0] cur_02_sel ;
reg [2-1:0] cur_02_size ;
reg [1-1:0] cur_02_ren ;
reg [32*`PIXEL_WIDTH-1:0] cur_02_pel ;
reg [4-1:0] cur_03_4x4_x ;
reg [4-1:0] cur_03_4x4_y ;
reg [5-1:0] cur_03_idx ;
reg [1-1:0] cur_03_sel ;
reg [2-1:0] cur_03_size ;
reg [1-1:0] cur_03_ren ;
reg [32*`PIXEL_WIDTH-1:0] cur_03_pel ;
reg [4-1:0] cur_04_4x4_x ;
reg [4-1:0] cur_04_4x4_y ;
reg [5-1:0] cur_04_idx ;
reg [1-1:0] cur_04_sel ;
reg [2-1:0] cur_04_size ;
reg [1-1:0] cur_04_ren ;
reg [32*`PIXEL_WIDTH-1:0] cur_04_pel ;
reg [4-1:0] cur_duo1_4x4_x ;
reg [4-1:0] cur_duo1_4x4_y ;
reg [5-1:0] cur_duo1_idx ;
reg [1-1:0] cur_duo1_sel ;
reg [2-1:0] cur_duo1_size ;
reg [1-1:0] cur_duo1_ren ;
reg [32*`PIXEL_WIDTH-1:0] cur_duo1_pel ;
reg [4-1:0] cur_duo2_4x4_x ;
reg [4-1:0] cur_duo2_4x4_y ;
reg [5-1:0] cur_duo2_idx ;
reg [1-1:0] cur_duo2_sel ;
reg [2-1:0] cur_duo2_size ;
reg [1-1:0] cur_duo2_ren ;
reg [32*`PIXEL_WIDTH-1:0] cur_duo2_pel ;
reg cur_00_wen;
reg [7:0] cur_00_waddr;
reg [32*`PIXEL_WIDTH-1:0] cur_00_wdata;
wire [32*`PIXEL_WIDTH-1:0] cur_00_rdata;
reg cur_01_wen;
reg [7:0] cur_01_waddr;
reg [32*`PIXEL_WIDTH-1:0] cur_01_wdata;
wire [32*`PIXEL_WIDTH-1:0] cur_01_rdata;
reg cur_02_wen;
reg [7:0] cur_02_waddr;
reg [32*`PIXEL_WIDTH-1:0] cur_02_wdata;
wire [32*`PIXEL_WIDTH-1:0] cur_02_rdata;
reg cur_03_wen;
reg [7:0] cur_03_waddr;
reg [32*`PIXEL_WIDTH-1:0] cur_03_wdata;
wire [32*`PIXEL_WIDTH-1:0] cur_03_rdata;
reg cur_04_wen;
reg [7:0] cur_04_waddr;
reg [32*`PIXEL_WIDTH-1:0] cur_04_wdata;
wire [32*`PIXEL_WIDTH-1:0] cur_04_rdata;
//fime
reg [32*`PIXEL_WIDTH-1:0] fime_cur_pel0, fime_cur_pel1;
reg cur_duo1_wen;
reg [7:0] cur_duo1_waddr;
reg [32*`PIXEL_WIDTH-1:0] cur_duo1_wdata;
wire [32*`PIXEL_WIDTH-1:0] cur_duo1_rdata;
reg cur_duo2_wen;
reg [7:0] cur_duo2_waddr;
reg [32*`PIXEL_WIDTH-1:0] cur_duo2_wdata;
wire [32*`PIXEL_WIDTH-1:0] cur_duo2_rdata;
//output
reg [32*`PIXEL_WIDTH-1:0] fme_cur_pel_o ; // fme current lcu pixel
reg [32*`PIXEL_WIDTH-1:0] mc_cur_pel_o ; // fme current lcu pixel
reg [32*`PIXEL_WIDTH-1:0] db_cur_pel_o ; // fme current lcu pixel
reg [32*`PIXEL_WIDTH-1:0] pre_i_pel_o ; // fme current lcu pixel
// ********************************************
//
// Combinational Logic
//
// ********************************************
// ********************************************
//
// Sequential Logic
//
// ********************************************
always @(posedge clk or negedge rstn ) begin
if( !rstn ) begin
rotate <= 0 ;
duo_rotate <= 0 ;
end
else if( sysif_start_i ) begin
duo_rotate <= ~duo_rotate ;
if( rotate == 4 )
rotate <= 0 ;
else begin
rotate <= rotate + 1 ;
end
end
end
/*
always @ (posedge clk or negedge rstn) begin
if(~rstn) begin
ext_load_addr_i <= 'd0;
end
else if(ext_load_valid_i) begin
ext_load_addr_i <= ext_load_addr_i + 'd1;
end
end
*/
// cur_00
always @ (*) begin
case (rotate)
'd0: begin
cur_00_wen = ext_load_valid_i;
cur_00_waddr = ext_load_addr_i;
cur_00_wdata = ext_load_data_i;
cur_00_ren = 'b0;
cur_00_sel = 'b0;
cur_00_size = 'b0;
cur_00_4x4_x = 'b0;
cur_00_4x4_y = 'b0;
cur_00_idx = 'b0;
end
'd1: begin
cur_00_wen = 'b0;
cur_00_waddr = 'b0;
cur_00_wdata = 'b0;
cur_00_ren = ( sysif_type_i==INTRA ) ? pre_i_rden_i : fime_cur_rden_i ;
cur_00_sel = ( sysif_type_i==INTRA ) ? pre_i_sel_i : fime_cur_sel_i ;
cur_00_size = ( sysif_type_i==INTRA ) ? pre_i_size_i : fime_cur_size_i ;
cur_00_4x4_x = ( sysif_type_i==INTRA ) ? pre_i_4x4_x_i : fime_cur_4x4_x_i ;
cur_00_4x4_y = ( sysif_type_i==INTRA ) ? pre_i_4x4_y_i : fime_cur_4x4_y_i ;
cur_00_idx = ( sysif_type_i==INTRA ) ? pre_i_4x4_idx_i : fime_cur_4x4_idx_i ;
end
'd2: begin
cur_00_wen = 'b0;
cur_00_waddr = 'b0;
cur_00_wdata = 'b0;
cur_00_ren = ( sysif_type_i==INTRA ) ? mc_cur_rden_i : fme_cur_rden_i ;
cur_00_sel = ( sysif_type_i==INTRA ) ? mc_cur_sel_i : fme_cur_sel_i ;
cur_00_size = ( sysif_type_i==INTRA ) ? mc_cur_size_i : fme_cur_size_i ;
cur_00_4x4_x = ( sysif_type_i==INTRA ) ? mc_cur_4x4_x_i : fme_cur_4x4_x_i ;
cur_00_4x4_y = ( sysif_type_i==INTRA ) ? mc_cur_4x4_y_i : fme_cur_4x4_y_i ;
cur_00_idx = ( sysif_type_i==INTRA ) ? mc_cur_4x4_idx_i : fme_cur_4x4_idx_i ;
end
'd3: begin
cur_00_wen = 'b0;
cur_00_waddr = 'b0;
cur_00_wdata = 'b0;
cur_00_ren = mc_cur_rden_i;
cur_00_sel = mc_cur_sel_i ;
cur_00_size = mc_cur_size_i;
cur_00_4x4_x = mc_cur_4x4_x_i;
cur_00_4x4_y = mc_cur_4x4_y_i;
cur_00_idx = mc_cur_4x4_idx_i;
end
'd4: begin
cur_00_wen = 'b0;
cur_00_waddr = 'b0;
cur_00_wdata = 'b0;
cur_00_ren = db_cur_rden_i;
cur_00_sel = db_cur_sel_i ;
cur_00_size = db_cur_size_i;
cur_00_4x4_x = db_cur_4x4_x_i;
cur_00_4x4_y = db_cur_4x4_y_i;
cur_00_idx = db_cur_4x4_idx_i;
end
default: begin
cur_00_wen = 'b0;
cur_00_waddr = 'b0;
cur_00_wdata = 'b0;
cur_00_ren = 'b0;
cur_00_sel = 'b0;
cur_00_size = 'b0;
cur_00_4x4_x = 'b0;
cur_00_4x4_y = 'b0;
cur_00_idx = 'b0;
end
endcase
end
// cur_01
always @ (*) begin
case (rotate)
'd0: begin
cur_01_wen = 'b0;
cur_01_waddr = 'b0;
cur_01_wdata = 'b0;
cur_01_ren = db_cur_rden_i;
cur_01_sel = db_cur_sel_i ;
cur_01_size = db_cur_size_i;
cur_01_4x4_x = db_cur_4x4_x_i;
cur_01_4x4_y = db_cur_4x4_y_i;
cur_01_idx = db_cur_4x4_idx_i;
end
'd1: begin
cur_01_wen = ext_load_valid_i;
cur_01_waddr = ext_load_addr_i;
cur_01_wdata = ext_load_data_i;
cur_01_ren = 'b0;
cur_01_sel = 'b0;
cur_01_size = 'b0;
cur_01_4x4_x = 'b0;
cur_01_4x4_y = 'b0;
cur_01_idx = 'b0;
end
'd2: begin
cur_01_wen = 'b0;
cur_01_waddr = 'b0;
cur_01_wdata = 'b0;
cur_01_ren = ( sysif_type_i==INTRA ) ? pre_i_rden_i : fime_cur_rden_i ;
cur_01_sel = ( sysif_type_i==INTRA ) ? pre_i_sel_i : fime_cur_sel_i ;
cur_01_size = ( sysif_type_i==INTRA ) ? pre_i_size_i : fime_cur_size_i ;
cur_01_4x4_x = ( sysif_type_i==INTRA ) ? pre_i_4x4_x_i : fime_cur_4x4_x_i ;
cur_01_4x4_y = ( sysif_type_i==INTRA ) ? pre_i_4x4_y_i : fime_cur_4x4_y_i ;
cur_01_idx = ( sysif_type_i==INTRA ) ? pre_i_4x4_idx_i : fime_cur_4x4_idx_i ;
end
'd3: begin
cur_01_wen = 'b0;
cur_01_waddr = 'b0;
cur_01_wdata = 'b0;
cur_01_ren = ( sysif_type_i==INTRA ) ? mc_cur_rden_i : fme_cur_rden_i ;
cur_01_sel = ( sysif_type_i==INTRA ) ? mc_cur_sel_i : fme_cur_sel_i ;
cur_01_size = ( sysif_type_i==INTRA ) ? mc_cur_size_i : fme_cur_size_i ;
cur_01_4x4_x = ( sysif_type_i==INTRA ) ? mc_cur_4x4_x_i : fme_cur_4x4_x_i ;
cur_01_4x4_y = ( sysif_type_i==INTRA ) ? mc_cur_4x4_y_i : fme_cur_4x4_y_i ;
cur_01_idx = ( sysif_type_i==INTRA ) ? mc_cur_4x4_idx_i : fme_cur_4x4_idx_i ;
end
'd4: begin
cur_01_wen = 'b0;
cur_01_waddr = 'b0;
cur_01_wdata = 'b0;
cur_01_ren = mc_cur_rden_i;
cur_01_sel = mc_cur_sel_i ;
cur_01_size = mc_cur_size_i;
cur_01_4x4_x = mc_cur_4x4_x_i;
cur_01_4x4_y = mc_cur_4x4_y_i;
cur_01_idx = mc_cur_4x4_idx_i;
end
default: begin
cur_01_wen = 'b0;
cur_01_waddr = 'b0;
cur_01_wdata = 'b0;
cur_01_ren = 'b0;
cur_01_sel = 'b0;
cur_01_size = 'b0;
cur_01_4x4_x = 'b0;
cur_01_4x4_y = 'b0;
cur_01_idx = 'b0;
end
endcase
end
// cur_02
always @ (*) begin
case (rotate)
'd0: begin
cur_02_wen = 'b0;
cur_02_waddr = 'b0;
cur_02_wdata = 'b0;
cur_02_ren = mc_cur_rden_i;
cur_02_sel = mc_cur_sel_i ;
cur_02_size = mc_cur_size_i;
cur_02_4x4_x = mc_cur_4x4_x_i;
cur_02_4x4_y = mc_cur_4x4_y_i;
cur_02_idx = mc_cur_4x4_idx_i;
end
'd1: begin
cur_02_wen = 'b0;
cur_02_waddr = 'b0;
cur_02_wdata = 'b0;
cur_02_ren = db_cur_rden_i;
cur_02_sel = db_cur_sel_i ;
cur_02_size = db_cur_size_i;
cur_02_4x4_x = db_cur_4x4_x_i;
cur_02_4x4_y = db_cur_4x4_y_i;
cur_02_idx = db_cur_4x4_idx_i;
end
'd2: begin
cur_02_wen = ext_load_valid_i;
cur_02_waddr = ext_load_addr_i;
cur_02_wdata = ext_load_data_i;
cur_02_ren = 'b0;
cur_02_sel = 'b0;
cur_02_size = 'b0;
cur_02_4x4_x = 'b0;
cur_02_4x4_y = 'b0;
cur_02_idx = 'b0;
end
'd3: begin
cur_02_wen = 'b0;
cur_02_waddr = 'b0;
cur_02_wdata = 'b0;
cur_02_ren = ( sysif_type_i==INTRA ) ? pre_i_rden_i : fime_cur_rden_i ;
cur_02_sel = ( sysif_type_i==INTRA ) ? pre_i_sel_i : fime_cur_sel_i ;
cur_02_size = ( sysif_type_i==INTRA ) ? pre_i_size_i : fime_cur_size_i ;
cur_02_4x4_x = ( sysif_type_i==INTRA ) ? pre_i_4x4_x_i : fime_cur_4x4_x_i ;
cur_02_4x4_y = ( sysif_type_i==INTRA ) ? pre_i_4x4_y_i : fime_cur_4x4_y_i ;
cur_02_idx = ( sysif_type_i==INTRA ) ? pre_i_4x4_idx_i : fime_cur_4x4_idx_i ;
end
'd4: begin
cur_02_wen = 'b0;
cur_02_waddr = 'b0;
cur_02_wdata = 'b0;
cur_02_ren = ( sysif_type_i==INTRA ) ? mc_cur_rden_i : fme_cur_rden_i ;
cur_02_sel = ( sysif_type_i==INTRA ) ? mc_cur_sel_i : fme_cur_sel_i ;
cur_02_size = ( sysif_type_i==INTRA ) ? mc_cur_size_i : fme_cur_size_i ;
cur_02_4x4_x = ( sysif_type_i==INTRA ) ? mc_cur_4x4_x_i : fme_cur_4x4_x_i ;
cur_02_4x4_y = ( sysif_type_i==INTRA ) ? mc_cur_4x4_y_i : fme_cur_4x4_y_i ;
cur_02_idx = ( sysif_type_i==INTRA ) ? mc_cur_4x4_idx_i : fme_cur_4x4_idx_i ;
end
default: begin
cur_02_wen = 'b0;
cur_02_waddr = 'b0;
cur_02_wdata = 'b0;
cur_02_ren = 'b0;
cur_02_sel = 'b0;
cur_02_size = 'b0;
cur_02_4x4_x = 'b0;
cur_02_4x4_y = 'b0;
cur_02_idx = 'b0;
end
endcase
end
// cur_03
always @ (*) begin
case (rotate)
'd0: begin
cur_03_wen = 'b0;
cur_03_waddr = 'b0;
cur_03_wdata = 'b0;
cur_03_ren = ( sysif_type_i==INTRA ) ? mc_cur_rden_i : fme_cur_rden_i ;
cur_03_sel = ( sysif_type_i==INTRA ) ? mc_cur_sel_i : fme_cur_sel_i ;
cur_03_size = ( sysif_type_i==INTRA ) ? mc_cur_size_i : fme_cur_size_i ;
cur_03_4x4_x = ( sysif_type_i==INTRA ) ? mc_cur_4x4_x_i : fme_cur_4x4_x_i ;
cur_03_4x4_y = ( sysif_type_i==INTRA ) ? mc_cur_4x4_y_i : fme_cur_4x4_y_i ;
cur_03_idx = ( sysif_type_i==INTRA ) ? mc_cur_4x4_idx_i : fme_cur_4x4_idx_i ;
end
'd1: begin
cur_03_wen = 'b0;
cur_03_waddr = 'b0;
cur_03_wdata = 'b0;
cur_03_ren = mc_cur_rden_i;
cur_03_sel = mc_cur_sel_i ;
cur_03_size = mc_cur_size_i;
cur_03_4x4_x = mc_cur_4x4_x_i;
cur_03_4x4_y = mc_cur_4x4_y_i;
cur_03_idx = mc_cur_4x4_idx_i;
end
'd2: begin
cur_03_wen = 'b0;
cur_03_waddr = 'b0;
cur_03_wdata = 'b0;
cur_03_ren = db_cur_rden_i;
cur_03_sel = db_cur_sel_i ;
cur_03_size = db_cur_size_i;
cur_03_4x4_x = db_cur_4x4_x_i;
cur_03_4x4_y = db_cur_4x4_y_i;
cur_03_idx = db_cur_4x4_idx_i;
end
'd3: begin
cur_03_wen = ext_load_valid_i;
cur_03_waddr = ext_load_addr_i;
cur_03_wdata = ext_load_data_i;
cur_03_ren = 'b0;
cur_03_sel = 'b0;
cur_03_size = 'b0;
cur_03_4x4_x = 'b0;
cur_03_4x4_y = 'b0;
cur_03_idx = 'b0;
end
'd4: begin
cur_03_wen = 'b0;
cur_03_waddr = 'b0;
cur_03_wdata = 'b0;
cur_03_ren = ( sysif_type_i==INTRA ) ? pre_i_rden_i : fime_cur_rden_i ;
cur_03_sel = ( sysif_type_i==INTRA ) ? pre_i_sel_i : fime_cur_sel_i ;
cur_03_size = ( sysif_type_i==INTRA ) ? pre_i_size_i : fime_cur_size_i ;
cur_03_4x4_x = ( sysif_type_i==INTRA ) ? pre_i_4x4_x_i : fime_cur_4x4_x_i ;
cur_03_4x4_y = ( sysif_type_i==INTRA ) ? pre_i_4x4_y_i : fime_cur_4x4_y_i ;
cur_03_idx = ( sysif_type_i==INTRA ) ? pre_i_4x4_idx_i : fime_cur_4x4_idx_i ;
end
default: begin
cur_03_wen = 'b0;
cur_03_waddr = 'b0;
cur_03_wdata = 'b0;
cur_03_ren = 'b0;
cur_03_sel = 'b0;
cur_03_size = 'b0;
cur_03_4x4_x = 'b0;
cur_03_4x4_y = 'b0;
cur_03_idx = 'b0;
end
endcase
end
// cur_04
always @ (*) begin
case (rotate)
'd0: begin
cur_04_wen = 'b0;
cur_04_waddr = 'b0;
cur_04_wdata = 'b0;
cur_04_ren = ( sysif_type_i==INTRA ) ? pre_i_rden_i : fime_cur_rden_i ;
cur_04_sel = ( sysif_type_i==INTRA ) ? pre_i_sel_i : fime_cur_sel_i ;
cur_04_size = ( sysif_type_i==INTRA ) ? pre_i_size_i : fime_cur_size_i ;
cur_04_4x4_x = ( sysif_type_i==INTRA ) ? pre_i_4x4_x_i : fime_cur_4x4_x_i ;
cur_04_4x4_y = ( sysif_type_i==INTRA ) ? pre_i_4x4_y_i : fime_cur_4x4_y_i ;
cur_04_idx = ( sysif_type_i==INTRA ) ? pre_i_4x4_idx_i : fime_cur_4x4_idx_i ;
end
'd1: begin
cur_04_wen = 'b0;
cur_04_waddr = 'b0;
cur_04_wdata = 'b0;
cur_04_ren = ( sysif_type_i==INTRA ) ? mc_cur_rden_i : fme_cur_rden_i ;
cur_04_sel = ( sysif_type_i==INTRA ) ? mc_cur_sel_i : fme_cur_sel_i ;
cur_04_size = ( sysif_type_i==INTRA ) ? mc_cur_size_i : fme_cur_size_i ;
cur_04_4x4_x = ( sysif_type_i==INTRA ) ? mc_cur_4x4_x_i : fme_cur_4x4_x_i ;
cur_04_4x4_y = ( sysif_type_i==INTRA ) ? mc_cur_4x4_y_i : fme_cur_4x4_y_i ;
cur_04_idx = ( sysif_type_i==INTRA ) ? mc_cur_4x4_idx_i : fme_cur_4x4_idx_i ;
end
'd2: begin
cur_04_wen = 'b0;
cur_04_waddr = 'b0;
cur_04_wdata = 'b0;
cur_04_ren = mc_cur_rden_i;
cur_04_sel = mc_cur_sel_i ;
cur_04_size = mc_cur_size_i;
cur_04_4x4_x = mc_cur_4x4_x_i;
cur_04_4x4_y = mc_cur_4x4_y_i;
cur_04_idx = mc_cur_4x4_idx_i;
end
'd3: begin
cur_04_wen = 'b0;
cur_04_waddr = 'b0;
cur_04_wdata = 'b0;
cur_04_ren = fime_cur_rden_i;
cur_04_sel = fime_cur_sel_i ;
cur_04_size = fime_cur_size_i;
cur_04_4x4_x = fime_cur_4x4_x_i;
cur_04_4x4_y = fime_cur_4x4_y_i;
cur_04_idx = fime_cur_4x4_idx_i;
end
'd4: begin
cur_04_wen = ext_load_valid_i;
cur_04_waddr = ext_load_addr_i;
cur_04_wdata = ext_load_data_i;
cur_04_ren = 'b0;
cur_04_sel = 'b0;
cur_04_size = 'b0;
cur_04_4x4_x = 'b0;
cur_04_4x4_y = 'b0;
cur_04_idx = 'b0;
end
default: begin
cur_04_wen = 'b0;
cur_04_waddr = 'b0;
cur_04_wdata = 'b0;
cur_04_ren = 'b0;
cur_04_sel = 'b0;
cur_04_size = 'b0;
cur_04_4x4_x = 'b0;
cur_04_4x4_y = 'b0;
cur_04_idx = 'b0;
end
endcase
end
// cur_duo1
always @ (*) begin
case (duo_rotate)
'd0: begin
cur_duo1_wen = ext_load_valid_i;
cur_duo1_waddr = ext_load_addr_i;
cur_duo1_wdata = ext_load_data_i;
cur_duo1_ren = 'b0;
cur_duo1_sel = 'b0;
cur_duo1_size = 'b0;
cur_duo1_4x4_x = 'b0;
cur_duo1_4x4_y = 'b0;
cur_duo1_idx = 'b0;
end
'd1: begin
cur_duo1_wen = 'b0;
cur_duo1_waddr = 'b0;
cur_duo1_wdata = 'b0;
cur_duo1_ren = fime_cur_rden_i;
cur_duo1_sel = fime_cur_sel_i ;
cur_duo1_size = fime_cur_size_i;
cur_duo1_4x4_x = fime_cur_4x4_x_i + 'd8;
cur_duo1_4x4_y = fime_cur_4x4_y_i;
cur_duo1_idx = fime_cur_4x4_idx_i;
end
endcase
end
// cur_duo2
always @ (*) begin
case (duo_rotate)
'd0: begin
cur_duo2_wen = 'b0;
cur_duo2_waddr = 'b0;
cur_duo2_wdata = 'b0;
cur_duo2_ren = fime_cur_rden_i;
cur_duo2_sel = fime_cur_sel_i ;
cur_duo2_size = fime_cur_size_i;
cur_duo2_4x4_x = fime_cur_4x4_x_i + 'd8; //
cur_duo2_4x4_y = fime_cur_4x4_y_i;
cur_duo2_idx = fime_cur_4x4_idx_i;
end
'd1: begin
cur_duo2_wen = ext_load_valid_i;
cur_duo2_waddr = ext_load_addr_i;
cur_duo2_wdata = ext_load_data_i;
cur_duo2_ren = 'b0;
cur_duo2_sel = 'b0;
cur_duo2_size = 'b0;
cur_duo2_4x4_x = 'b0;
cur_duo2_4x4_y = 'b0;
cur_duo2_idx = 'b0;
end
endcase
end
always @ (*) begin
case (rotate)
'd0:begin
fime_cur_pel0 = cur_04_rdata ;
fme_cur_pel_o = cur_03_rdata ;
mc_cur_pel_o = ( sysif_type_i==INTRA ) ? cur_03_rdata : cur_02_rdata ;
db_cur_pel_o = cur_01_rdata ;
pre_i_pel_o = cur_04_rdata ;
end
'd1:begin
fime_cur_pel0 = cur_00_rdata ;
fme_cur_pel_o = cur_04_rdata ;
mc_cur_pel_o = ( sysif_type_i==INTRA ) ? cur_04_rdata : cur_03_rdata ;
db_cur_pel_o = cur_02_rdata ;
pre_i_pel_o = cur_00_rdata ;
end
'd2:begin
fime_cur_pel0 = cur_01_rdata ;
fme_cur_pel_o = cur_00_rdata ;
mc_cur_pel_o = ( sysif_type_i==INTRA ) ? cur_00_rdata : cur_04_rdata ;
db_cur_pel_o = cur_03_rdata ;
pre_i_pel_o = cur_01_rdata ;
end
'd3:begin
fime_cur_pel0 = cur_02_rdata ;
fme_cur_pel_o = cur_01_rdata ;
mc_cur_pel_o = ( sysif_type_i==INTRA ) ? cur_01_rdata : cur_00_rdata ;
db_cur_pel_o = cur_04_rdata ;
pre_i_pel_o = cur_02_rdata ;
end
'd4:begin
fime_cur_pel0 = cur_03_rdata ;
fme_cur_pel_o = cur_02_rdata ;
mc_cur_pel_o = ( sysif_type_i==INTRA ) ? cur_02_rdata : cur_01_rdata ;
db_cur_pel_o = cur_00_rdata ;
pre_i_pel_o = cur_03_rdata ;
end
default: begin
fime_cur_pel0 = 0 ;
fme_cur_pel_o = 0 ;
mc_cur_pel_o = 0 ;
db_cur_pel_o = 0 ;
pre_i_pel_o = 0 ;
end
endcase
end
always @ (*) begin
case (duo_rotate)
'd0:begin
fime_cur_pel1 = cur_duo2_rdata;
end
'd1:begin
fime_cur_pel1 = cur_duo1_rdata;
end
endcase
end
assign fime_cur_pel_o = {fime_cur_pel0,fime_cur_pel1};
// ********************************************
//
// Wrapper
//
// ********************************************
mem_lipo_1p cur00 (
.clk (clk ),
.rst_n (rstn ),
.a_wen_i (cur_00_wen ),
.a_addr_i (cur_00_waddr),
.a_wdata_i (cur_00_wdata),
.b_ren_i (cur_00_ren ),
.b_sel_i (cur_00_sel ),
.b_size_i (cur_00_size ),
.b_4x4_x_i (cur_00_4x4_x),
.b_4x4_y_i (cur_00_4x4_y),
.b_idx_i (cur_00_idx ),
.b_rdata_o (cur_00_rdata)
);
mem_lipo_1p cur01 (
.clk (clk ),
.rst_n (rstn ),
.a_wen_i (cur_01_wen ),
.a_addr_i (cur_01_waddr),
.a_wdata_i (cur_01_wdata),
.b_ren_i (cur_01_ren ),
.b_sel_i (cur_01_sel ),
.b_size_i (cur_01_size ),
.b_4x4_x_i (cur_01_4x4_x),
.b_4x4_y_i (cur_01_4x4_y),
.b_idx_i (cur_01_idx ),
.b_rdata_o (cur_01_rdata)
);
mem_lipo_1p cur02 (
.clk (clk ),
.rst_n (rstn),
.a_wen_i (cur_02_wen ),
.a_addr_i (cur_02_waddr),
.a_wdata_i (cur_02_wdata),
.b_ren_i (cur_02_ren ),
.b_sel_i (cur_02_sel ),
.b_size_i (cur_02_size ),
.b_4x4_x_i (cur_02_4x4_x),
.b_4x4_y_i (cur_02_4x4_y),
.b_idx_i (cur_02_idx ),
.b_rdata_o (cur_02_rdata)
);
mem_lipo_1p cur03 (
.clk (clk ),
.rst_n (rstn),
.a_wen_i (cur_03_wen ),
.a_addr_i (cur_03_waddr),
.a_wdata_i (cur_03_wdata),
.b_ren_i (cur_03_ren ),
.b_sel_i (cur_03_sel ),
.b_size_i (cur_03_size ),
.b_4x4_x_i (cur_03_4x4_x),
.b_4x4_y_i (cur_03_4x4_y),
.b_idx_i (cur_03_idx ),
.b_rdata_o (cur_03_rdata)
);
mem_lipo_1p cur04 (
.clk (clk ),
.rst_n (rstn),
.a_wen_i (cur_04_wen ),
.a_addr_i (cur_04_waddr),
.a_wdata_i (cur_04_wdata),
.b_ren_i (cur_04_ren ),
.b_sel_i (cur_04_sel ),
.b_size_i (cur_04_size ),
.b_4x4_x_i (cur_04_4x4_x),
.b_4x4_y_i (cur_04_4x4_y),
.b_idx_i (cur_04_idx ),
.b_rdata_o (cur_04_rdata)
);
mem_lipo_1p duo1 (
.clk (clk ),
.rst_n (rstn),
.a_wen_i (cur_duo1_wen ),
.a_addr_i (cur_duo1_waddr),
.a_wdata_i (cur_duo1_wdata),
.b_ren_i (cur_duo1_ren ),
.b_sel_i (cur_duo1_sel ),
.b_size_i (cur_duo1_size ),
.b_4x4_x_i (cur_duo1_4x4_x),
.b_4x4_y_i (cur_duo1_4x4_y),
.b_idx_i (cur_duo1_idx ),
.b_rdata_o (cur_duo1_rdata)
);
mem_lipo_1p duo2 (
.clk (clk ),
.rst_n (rstn),
.a_wen_i (cur_duo2_wen ),
.a_addr_i (cur_duo2_waddr),
.a_wdata_i (cur_duo2_wdata),
.b_ren_i (cur_duo2_ren ),
.b_sel_i (cur_duo2_sel ),
.b_size_i (cur_duo2_size ),
.b_4x4_x_i (cur_duo2_4x4_x),
.b_4x4_y_i (cur_duo2_4x4_y),
.b_idx_i (cur_duo2_idx ),
.b_rdata_o (cur_duo2_rdata)
);
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Mon Feb 13 23:24:41 2017
// Host : TheMosass-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_processing_system7_0_0_stub.v
// Design : design_1_processing_system7_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2016.4" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(GPIO_I, GPIO_O, GPIO_T, SDIO0_WP, TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT, TTC0_WAVE2_OUT, USB0_PORT_INDCTL, USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT, M_AXI_GP0_ARVALID, M_AXI_GP0_AWVALID, M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY, M_AXI_GP0_WLAST, M_AXI_GP0_WVALID, M_AXI_GP0_ARID, M_AXI_GP0_AWID,
M_AXI_GP0_WID, M_AXI_GP0_ARBURST, M_AXI_GP0_ARLOCK, M_AXI_GP0_ARSIZE, M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK, M_AXI_GP0_AWSIZE, M_AXI_GP0_ARPROT, M_AXI_GP0_AWPROT, M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR, M_AXI_GP0_WDATA, M_AXI_GP0_ARCACHE, M_AXI_GP0_ARLEN, M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE, M_AXI_GP0_AWLEN, M_AXI_GP0_AWQOS, M_AXI_GP0_WSTRB, M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY, M_AXI_GP0_AWREADY, M_AXI_GP0_BVALID, M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID, M_AXI_GP0_WREADY, M_AXI_GP0_BID, M_AXI_GP0_RID, M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP, M_AXI_GP0_RDATA, IRQ_F2P, FCLK_CLK0, FCLK_RESET0_N, MIO, DDR_CAS_n, DDR_CKE,
DDR_Clk_n, DDR_Clk, DDR_CS_n, DDR_DRSTB, DDR_ODT, DDR_RAS_n, DDR_WEB, DDR_BankAddr, DDR_Addr,
DDR_VRN, DDR_VRP, DDR_DM, DDR_DQ, DDR_DQS_n, DDR_DQS, PS_SRSTB, PS_CLK, PS_PORB)
/* synthesis syn_black_box black_box_pad_pin="GPIO_I[63:0],GPIO_O[63:0],GPIO_T[63:0],SDIO0_WP,TTC0_WAVE0_OUT,TTC0_WAVE1_OUT,TTC0_WAVE2_OUT,USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],IRQ_F2P[0:0],FCLK_CLK0,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB" */;
input [63:0]GPIO_I;
output [63:0]GPIO_O;
output [63:0]GPIO_T;
input SDIO0_WP;
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
output [1:0]USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11:0]M_AXI_GP0_ARID;
output [11:0]M_AXI_GP0_AWID;
output [11:0]M_AXI_GP0_WID;
output [1:0]M_AXI_GP0_ARBURST;
output [1:0]M_AXI_GP0_ARLOCK;
output [2:0]M_AXI_GP0_ARSIZE;
output [1:0]M_AXI_GP0_AWBURST;
output [1:0]M_AXI_GP0_AWLOCK;
output [2:0]M_AXI_GP0_AWSIZE;
output [2:0]M_AXI_GP0_ARPROT;
output [2:0]M_AXI_GP0_AWPROT;
output [31:0]M_AXI_GP0_ARADDR;
output [31:0]M_AXI_GP0_AWADDR;
output [31:0]M_AXI_GP0_WDATA;
output [3:0]M_AXI_GP0_ARCACHE;
output [3:0]M_AXI_GP0_ARLEN;
output [3:0]M_AXI_GP0_ARQOS;
output [3:0]M_AXI_GP0_AWCACHE;
output [3:0]M_AXI_GP0_AWLEN;
output [3:0]M_AXI_GP0_AWQOS;
output [3:0]M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11:0]M_AXI_GP0_BID;
input [11:0]M_AXI_GP0_RID;
input [1:0]M_AXI_GP0_BRESP;
input [1:0]M_AXI_GP0_RRESP;
input [31:0]M_AXI_GP0_RDATA;
input [0:0]IRQ_F2P;
output FCLK_CLK0;
output FCLK_RESET0_N;
inout [53:0]MIO;
inout DDR_CAS_n;
inout DDR_CKE;
inout DDR_Clk_n;
inout DDR_Clk;
inout DDR_CS_n;
inout DDR_DRSTB;
inout DDR_ODT;
inout DDR_RAS_n;
inout DDR_WEB;
inout [2:0]DDR_BankAddr;
inout [14:0]DDR_Addr;
inout DDR_VRN;
inout DDR_VRP;
inout [3:0]DDR_DM;
inout [31:0]DDR_DQ;
inout [3:0]DDR_DQS_n;
inout [3:0]DDR_DQS;
inout PS_SRSTB;
inout PS_CLK;
inout PS_PORB;
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_io_cmos2_pad_dn.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
/////////////////////////////////////////////////////////////////////////
/*
// CMOS2 PAD
*/
////////////////////////////////////////////////////////////////////////
`include "sys.h"
module bw_io_cmos2_pad_dn(oe ,data ,to_core ,pad ,por_l, vddo );
output to_core ;
input oe ;
input data ;
input por_l ;
inout pad ;
input vddo ;
supply1 vdd ;
supply0 vss ;
wire rcvr_data ;
wire por ;
wire pad_up ;
wire net58 ;
wire net59 ;
wire pad_dn_l ;
bw_io_cmos_edgelogic I2 (
.rcvr_data (rcvr_data ),
.to_core (to_core ),
.se (vss ),
.bsr_up (net58 ),
.bsr_dn_l (net59 ),
.pad_dn_l (pad_dn_l ),
.pad_up (pad_up ),
.oe (oe ),
.data (data ),
.por_l (por_l ),
.por (por ),
.bsr_data_to_core (vss ),
.bsr_mode (vss ) );
bw_io_hstl_drv I3 (
.cbu ({vss ,vss ,vss ,vss ,vdd ,vdd ,vdd ,vdd } ),
.cbd ({vss ,vss ,vss ,vss ,vdd ,vdd ,vdd ,vdd } ),
.por (por ),
.bsr_dn_l (vss ),
.bsr_up (vss ),
.pad_dn_l (pad_dn_l ),
.sel_data_n (vss ),
.pad_up (pad_up ),
.pad (pad ),
.vddo (vddo) );
bw_io_schmitt I41 (
.vddo (vddo ),
.out (rcvr_data ),
.in (pad ) );
bw_io_cmos2_term_dn I18 (
.vddo (vddo ),
.out (pad ) );
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// $Id$
//
// Module: vlan_adder.v
// Project: NF2.1 OpenFlow Switch
// Author: Jad Naous <[email protected]> / Tatsuya Yabe <[email protected]>
// Description: adds the VLAN tag if it finds it in a module header. If there
// are multiple ones, it only uses the first one it finds.
//
///////////////////////////////////////////////////////////////////////////////
module vlan_adder
#(parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH = DATA_WIDTH/8
)
(// --- Interface to the previous stage
input [DATA_WIDTH-1:0] in_data,
input [CTRL_WIDTH-1:0] in_ctrl,
input in_wr,
output in_rdy,
// --- Interface to the next stage
output reg [DATA_WIDTH-1:0] out_data,
output reg [CTRL_WIDTH-1:0] out_ctrl,
output reg out_wr,
input out_rdy,
// --- Misc
input reset,
input clk
);
`CEILDIV_FUNC
//------------------ Internal Parameters --------------------------
localparam NUM_STATES = 5;
localparam FIND_VLAN_HDR = 0,
WAIT_SOP = 1,
ADD_VLAN = 2,
WRITE_MODIFIED_PKT = 3,
WRITE_LAST_PKT = 4;
//---------------------- Wires/Regs -------------------------------
wire [DATA_WIDTH-1:0] fifo_data_out;
wire [CTRL_WIDTH-1:0] fifo_ctrl_out;
reg [15:0] vlan_tag_nxt, vlan_tag;
reg [31:0] latch_data_nxt, latch_data;
reg [7:0] latch_ctrl_nxt, latch_ctrl;
reg [NUM_STATES-1:0] process_state_nxt, process_state;
reg fifo_rd_en;
reg out_wr_nxt;
reg [DATA_WIDTH-1:0] out_data_nxt;
reg [CTRL_WIDTH-1:0] out_ctrl_nxt;
//----------------------- Modules ---------------------------------
fallthrough_small_fifo
#(.WIDTH(CTRL_WIDTH+DATA_WIDTH), .MAX_DEPTH_BITS(3))
input_fifo
(.din ({in_ctrl, in_data}), // Data in
.wr_en (in_wr), // Write enable
.rd_en (fifo_rd_en), // Read the next word
.dout ({fifo_ctrl_out, fifo_data_out}),
.full (),
.prog_full (),
.nearly_full (fifo_nearly_full),
.empty (fifo_empty),
.reset (reset),
.clk (clk)
);
//------------------------ Logic ----------------------------------
assign in_rdy = !fifo_nearly_full;
always @(*) begin
process_state_nxt = process_state;
fifo_rd_en = 0;
out_wr_nxt = 0;
out_data_nxt = fifo_data_out;
out_ctrl_nxt = fifo_ctrl_out;
vlan_tag_nxt = vlan_tag;
latch_data_nxt = latch_data;
latch_ctrl_nxt = latch_ctrl;
case (process_state)
FIND_VLAN_HDR: begin
if (out_rdy && !fifo_empty) begin
fifo_rd_en = 1;
if (fifo_ctrl_out == `VLAN_CTRL_WORD && fifo_data_out[31]==0) begin
out_wr_nxt = 0;
vlan_tag_nxt = fifo_data_out[15:0];
process_state_nxt = WAIT_SOP;
end
else if(fifo_ctrl_out == `VLAN_CTRL_WORD && fifo_data_out[31]==1) begin
out_wr_nxt = 0;
vlan_tag_nxt = 0;
end
else begin
out_wr_nxt = 1;
end
end
end // case: FIND_VLAN_HDR
WAIT_SOP: begin
if (out_rdy && !fifo_empty) begin
fifo_rd_en = 1;
out_wr_nxt = 1;
if (fifo_ctrl_out == `IO_QUEUE_STAGE_NUM) begin
// Increment byte-count and word-count since we will add vlan tags
out_data_nxt[`IOQ_BYTE_LEN_POS+15:`IOQ_BYTE_LEN_POS]
= fifo_data_out[`IOQ_BYTE_LEN_POS+15:`IOQ_BYTE_LEN_POS] + 4;
out_data_nxt[`IOQ_WORD_LEN_POS+15:`IOQ_WORD_LEN_POS]
= ceildiv((fifo_data_out[`IOQ_BYTE_LEN_POS+15:`IOQ_BYTE_LEN_POS] + 4), 8);
end
else if (fifo_ctrl_out == 0) begin
process_state_nxt = ADD_VLAN;
end
end
end // case: WAIT_SOP
ADD_VLAN: begin
if (out_rdy && !fifo_empty) begin
//insert vlan_tag into second word
fifo_rd_en = 1;
out_wr_nxt = 1;
if (fifo_ctrl_out == 0) begin
out_data_nxt = {fifo_data_out[63:32], `VLAN_ETHERTYPE, vlan_tag};
latch_data_nxt = fifo_data_out[31:0];
latch_ctrl_nxt = fifo_ctrl_out;
process_state_nxt = WRITE_MODIFIED_PKT;
end
// Abnormal condition.
// fifo_ctrl_out should be zero on this state but if it isn't
// then give up continueing and go back to initial state
else begin
process_state_nxt = FIND_VLAN_HDR;
end
end
end // case: ADD_VLAN
WRITE_MODIFIED_PKT: begin
if (out_rdy && !fifo_empty) begin
fifo_rd_en = 1;
out_wr_nxt = 1;
out_data_nxt = {latch_data, fifo_data_out[63:32]};
latch_data_nxt = fifo_data_out[31:0];
latch_ctrl_nxt = fifo_ctrl_out;
if (fifo_ctrl_out[7:4] != 0) begin
out_ctrl_nxt = (fifo_ctrl_out >> 4);
process_state_nxt = FIND_VLAN_HDR;
end
else if (fifo_ctrl_out[3:0] != 0) begin
out_ctrl_nxt = 0;
process_state_nxt = WRITE_LAST_PKT;
end
end
end // case: WRITE_MODIFIED_PKT
WRITE_LAST_PKT: begin
if (out_rdy) begin
out_wr_nxt = 1;
out_data_nxt = {latch_data, 32'h0};
out_ctrl_nxt = latch_ctrl << 4;
process_state_nxt = FIND_VLAN_HDR;
end
end // case: WRITE_LAST_PKT
default:process_state_nxt=FIND_VLAN_HDR;
endcase // case(process_state)
end // always @ (*)
always @(posedge clk) begin
if(reset) begin
process_state <= FIND_VLAN_HDR;
out_wr <= 0;
out_data <= 0;
out_ctrl <= 1;
latch_data <= 0;
latch_ctrl <= 0;
vlan_tag <= 0;
end
else begin
process_state <= process_state_nxt;
out_wr <= out_wr_nxt;
out_data <= out_data_nxt;
out_ctrl <= out_ctrl_nxt;
latch_data <= latch_data_nxt;
latch_ctrl <= latch_ctrl_nxt;
vlan_tag <= vlan_tag_nxt;
end // else: !if(reset)
end // always @ (posedge clk)
endmodule // vlan_remover
|
//////////////////////////////////////////////////////////////////////////////////
// NPCG_Toggle_way_CE_timer for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Ilyong Jung <[email protected]>
// Yong Ho Song <[email protected]>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Ilyong Jung <[email protected]>
//
// Project Name: Cosmos OpenSSD
// Design Name: NPCG_Toggle_way_CE_timer
// Module Name: NPCG_Toggle_way_CE_timer
// File Name: NPCG_Toggle_way_CE_timer.v
//
// Version: v1.0.0
//
// Description: Way chip enable timer
//
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module NPCG_Toggle_way_CE_timer
#
(
parameter NumberOfWays = 8
)
(
iSystemClock ,
iReset ,
iWorkingWay ,
ibCMDLast ,
ibCMDLast_SCC ,
iTargetWay ,
oCMDHold
);
input iSystemClock ;
input iReset ;
input [NumberOfWays - 1:0] iWorkingWay ;
input ibCMDLast ;
input ibCMDLast_SCC ;
input [NumberOfWays - 1:0] iTargetWay ;
output oCMDHold ;
wire wWay0_Deasserted ;
wire wWay1_Deasserted ;
wire wWay2_Deasserted ;
wire wWay3_Deasserted ;
wire wWay4_Deasserted ;
wire wWay5_Deasserted ;
wire wWay6_Deasserted ;
wire wWay7_Deasserted ;
reg [3:0] rWay0_Timer ;
reg [3:0] rWay1_Timer ;
reg [3:0] rWay2_Timer ;
reg [3:0] rWay3_Timer ;
reg [3:0] rWay4_Timer ;
reg [3:0] rWay5_Timer ;
reg [3:0] rWay6_Timer ;
reg [3:0] rWay7_Timer ;
wire wWay0_Ready ;
wire wWay1_Ready ;
wire wWay2_Ready ;
wire wWay3_Ready ;
wire wWay4_Ready ;
wire wWay5_Ready ;
wire wWay6_Ready ;
wire wWay7_Ready ;
wire wWay0_Targeted ;
wire wWay1_Targeted ;
wire wWay2_Targeted ;
wire wWay3_Targeted ;
wire wWay4_Targeted ;
wire wWay5_Targeted ;
wire wWay6_Targeted ;
wire wWay7_Targeted ;
assign wWay0_Deasserted = (~ibCMDLast_SCC) & ibCMDLast & iWorkingWay[0];
assign wWay1_Deasserted = (~ibCMDLast_SCC) & ibCMDLast & iWorkingWay[1];
assign wWay2_Deasserted = (~ibCMDLast_SCC) & ibCMDLast & iWorkingWay[2];
assign wWay3_Deasserted = (~ibCMDLast_SCC) & ibCMDLast & iWorkingWay[3];
assign wWay4_Deasserted = (~ibCMDLast_SCC) & ibCMDLast & iWorkingWay[4];
assign wWay5_Deasserted = (~ibCMDLast_SCC) & ibCMDLast & iWorkingWay[5];
assign wWay6_Deasserted = (~ibCMDLast_SCC) & ibCMDLast & iWorkingWay[6];
assign wWay7_Deasserted = (~ibCMDLast_SCC) & ibCMDLast & iWorkingWay[7];
assign wWay0_Ready = (rWay0_Timer[3:0] == 4'b1110); // 14 cycle -> 140 ns
assign wWay1_Ready = (rWay1_Timer[3:0] == 4'b1110);
assign wWay2_Ready = (rWay2_Timer[3:0] == 4'b1110);
assign wWay3_Ready = (rWay3_Timer[3:0] == 4'b1110);
assign wWay4_Ready = (rWay4_Timer[3:0] == 4'b1110);
assign wWay5_Ready = (rWay5_Timer[3:0] == 4'b1110);
assign wWay6_Ready = (rWay6_Timer[3:0] == 4'b1110);
assign wWay7_Ready = (rWay7_Timer[3:0] == 4'b1110);
always @ (posedge iSystemClock, posedge iReset) begin
if (iReset) begin
rWay0_Timer[3:0] <= 4'b1110;
rWay1_Timer[3:0] <= 4'b1110;
rWay2_Timer[3:0] <= 4'b1110;
rWay3_Timer[3:0] <= 4'b1110;
rWay4_Timer[3:0] <= 4'b1110;
rWay5_Timer[3:0] <= 4'b1110;
rWay6_Timer[3:0] <= 4'b1110;
rWay7_Timer[3:0] <= 4'b1110;
end else begin
rWay0_Timer[3:0] <= (wWay0_Deasserted)? 4'b0000:((wWay0_Ready)? (rWay0_Timer[3:0]):(rWay0_Timer[3:0] + 1'b1));
rWay1_Timer[3:0] <= (wWay1_Deasserted)? 4'b0000:((wWay1_Ready)? (rWay1_Timer[3:0]):(rWay1_Timer[3:0] + 1'b1));
rWay2_Timer[3:0] <= (wWay2_Deasserted)? 4'b0000:((wWay2_Ready)? (rWay2_Timer[3:0]):(rWay2_Timer[3:0] + 1'b1));
rWay3_Timer[3:0] <= (wWay3_Deasserted)? 4'b0000:((wWay3_Ready)? (rWay3_Timer[3:0]):(rWay3_Timer[3:0] + 1'b1));
rWay4_Timer[3:0] <= (wWay4_Deasserted)? 4'b0000:((wWay4_Ready)? (rWay4_Timer[3:0]):(rWay4_Timer[3:0] + 1'b1));
rWay5_Timer[3:0] <= (wWay5_Deasserted)? 4'b0000:((wWay5_Ready)? (rWay5_Timer[3:0]):(rWay5_Timer[3:0] + 1'b1));
rWay6_Timer[3:0] <= (wWay6_Deasserted)? 4'b0000:((wWay6_Ready)? (rWay6_Timer[3:0]):(rWay6_Timer[3:0] + 1'b1));
rWay7_Timer[3:0] <= (wWay7_Deasserted)? 4'b0000:((wWay7_Ready)? (rWay7_Timer[3:0]):(rWay7_Timer[3:0] + 1'b1));
end
end
assign wWay0_Targeted = iTargetWay[0];
assign wWay1_Targeted = iTargetWay[1];
assign wWay2_Targeted = iTargetWay[2];
assign wWay3_Targeted = iTargetWay[3];
assign wWay4_Targeted = iTargetWay[4];
assign wWay5_Targeted = iTargetWay[5];
assign wWay6_Targeted = iTargetWay[6];
assign wWay7_Targeted = iTargetWay[7];
assign oCMDHold = (wWay0_Targeted & (~wWay0_Ready)) |
(wWay1_Targeted & (~wWay1_Ready)) |
(wWay2_Targeted & (~wWay2_Ready)) |
(wWay3_Targeted & (~wWay3_Ready)) |
(wWay4_Targeted & (~wWay4_Ready)) |
(wWay5_Targeted & (~wWay5_Ready)) |
(wWay6_Targeted & (~wWay6_Ready)) |
(wWay7_Targeted & (~wWay7_Ready)) ;
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Original Author: Schuyler Eldridge
// Contact Point: Schuyler Eldridge ([email protected])
// button_debounce.v
// Created: 10/10/2009
// Modified: 3/20/2012
//
// Counter based debounce circuit originally written for EC551 (back
// in the day) and then modified (i.e. chagned entirely) into 3 always
// block format. This debouncer generates a signal that goes high for
// 1 clock cycle after the clock sees an asserted value on the button
// line. This action is then disabled until the counter hits a
// specified count value that is determined by the clock frequency and
// desired debounce frequency. An alternative implementation would not
// use a counter, but would use the shift register approach, looking
// for repeated matches (say 5) on the button line.
//
// Copyright (C) 2012 Schuyler Eldridge, Boston University
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module button_debounce
(
input clk, // clock
input reset_n, // asynchronous reset
input button, // bouncy button
output reg debounce // debounced 1-cycle signal
);
parameter
CLK_FREQUENCY = 66000000,
DEBOUNCE_HZ = 2;
// These parameters are specified such that you can choose any power
// of 2 frequency for a debouncer between 1 Hz and
// CLK_FREQUENCY. Note, that this will throw errors if you choose a
// non power of 2 frequency (i.e. count_value evaluates to some
// number / 3 which isn't interpreted as a logical right shift). I'm
// assuming this will not work for DEBOUNCE_HZ values less than 1,
// however, I'm uncertain of the value of a debouncer for fractional
// hertz button presses.
localparam
COUNT_VALUE = CLK_FREQUENCY / DEBOUNCE_HZ,
WAIT = 0,
FIRE = 1,
COUNT = 2;
reg [1:0] state, next_state;
reg [25:0] count;
always @ (posedge clk or negedge reset_n)
state <= (!reset_n) ? WAIT : next_state;
always @ (posedge clk or negedge reset_n) begin
if (!reset_n) begin
debounce <= 0;
count <= 0;
end
else begin
debounce <= 0;
count <= 0;
case (state)
WAIT: begin
end
FIRE: begin
debounce <= 1;
end
COUNT: begin
count <= count + 1;
end
endcase
end
end
always @ * begin
case (state)
WAIT: next_state = (button) ? FIRE : state;
FIRE: next_state = COUNT;
COUNT: next_state = (count > COUNT_VALUE - 1) ? WAIT : state;
default: next_state = WAIT;
endcase
end
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Project: Aurora 64B/66B
// Company: Xilinx
//
//
// (c) Copyright 2012 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
////////////////////////////////////////////////////////////////////////////////
//
// Module Common Reset CBCC
// Generated by Xilinx Aurora 64B66B
`timescale 1 ps / 1 ps
`define DLY #1
(* DowngradeIPIdentifiedWarnings="yes" *)
//***********************************Entity Declaration*******************************
module aurora_64b66b_25p4G_common_reset_cbcc
(
input enchansync,
input chan_bond_reset,
input reset,
input rd_clk,
input init_clk,
input cb_bit_err,
input user_clk,
output reg cbcc_fifo_reset_wr_clk,
output cbcc_fifo_reset_to_fifo_wr_clk,
output reg cbcc_data_srst = 1'b0,
output reg cbcc_fifo_reset_rd_clk,
output cbcc_fifo_reset_to_fifo_rd_clk,
output cbcc_only_reset_rd_clk,
(* shift_extract = "{no}" *) output reg cbcc_reset_cbstg2_rd_clk
);
//---- cbcc_only_reset_rd_clk ---{
aurora_64b66b_25p4G_rst_sync u_rst_sync_cbcc_only_reset_rd_clk
(
.prmry_in ( reset ),
.scndry_aclk ( rd_clk ),
.scndry_out ( cbcc_only_reset_rd_clk )
);
//---- cbcc_only_reset_rd_clk ---}
//-------------- Wire declaration----------------------------
wire fifo_reset_wr_sync3;
wire fifo_reset_comb;
(* shift_extract = "{no}" *) wire fifo_reset_comb_user_clk;
(* shift_extract = "{no}" *) wire fifo_reset_comb_read_clk;
//-------------- Register declaration----------------------------
reg fifo_reset_rd = 1'b1;
(* shift_extract = "{no}" *) reg reset_cbcc_comb = 1'b1;
(* shift_extract = "{no}" *) reg cbc_wr_if_reset = 1'b1;
wire chan_bond_reset_r2;
reg [3:0] cb_bit_err_ext_cnt; //used for pulse extension to avoid drc violations on fifo
//*********************************Main Body of Code***************************
//----- reset_cbcc_comb ----{
// Double synchronize CHAN_BOND_RESET to account for domain crossing.
aurora_64b66b_25p4G_cdc_sync
# (
.c_cdc_type (1), // 0 Pulse synchronizer, 1 level synchronizer 2 level synchronizer with ACK
.c_flop_input (0), // 1 Adds one flop stage to the input prmry_in signal
.c_reset_state (0), // 1 Reset needed for sync flops
.c_single_bit (1), // 1 single bit input.
.c_mtbf_stages (5) // Number of sync stages needed
) u_cdc_chan_bond_reset
(
.prmry_aclk (1'b0),
.prmry_rst_n (1'b1 ),
.prmry_in (chan_bond_reset),
.prmry_vect_in ('d0 ),
.scndry_aclk (user_clk ),
.scndry_rst_n (1'b1 ),
.prmry_ack ( ),
.scndry_out (chan_bond_reset_r2),
.scndry_vect_out ( )
);
always @(posedge user_clk)
begin
if(reset)
cb_bit_err_ext_cnt <= `DLY 4'd0;
else if(cb_bit_err)
cb_bit_err_ext_cnt <= `DLY 4'b1111;
else if(cb_bit_err_ext_cnt == 4'd0)
cb_bit_err_ext_cnt <= `DLY 4'd0;
else
cb_bit_err_ext_cnt <= `DLY cb_bit_err_ext_cnt - 1'b1;
end
always @(posedge user_clk)
begin
if(reset)
reset_cbcc_comb <= `DLY 1'b1;
else if(chan_bond_reset_r2)
reset_cbcc_comb <= `DLY 1'b1;
else if(cb_bit_err_ext_cnt != 4'd0)
reset_cbcc_comb <= `DLY 1'b1;
else
reset_cbcc_comb <= `DLY 1'b0;
end
//----- reset_cbcc_comb ----}
//---- cbcc_reset_cbstg2_rd_clk ---{
wire rst_cbcc_comb_rd_clk;
aurora_64b66b_25p4G_rst_sync u_rst_sync_rst_cbcc_rd_clk
(
.prmry_in ( reset_cbcc_comb ),
.scndry_aclk ( rd_clk ),
.scndry_out ( rst_cbcc_comb_rd_clk )
);
(* shift_extract = "{no}" *) reg rd_stg1 = 1'b1;
always @(posedge rd_clk)
begin
if(rst_cbcc_comb_rd_clk)
begin
rd_stg1 <= `DLY 1'b1;
cbcc_reset_cbstg2_rd_clk <= `DLY 1'b1;
end
else
begin
rd_stg1 <= `DLY rst_cbcc_comb_rd_clk;
cbcc_reset_cbstg2_rd_clk <= `DLY rd_stg1;
end
end
//---- cbcc_reset_cbstg2_rd_clk ---}
//----- fifo_reset_comb ----{
always @(posedge rd_clk)
begin
if(cbcc_reset_cbstg2_rd_clk)
fifo_reset_rd <= `DLY 1'b1;
else if(enchansync)
fifo_reset_rd <= `DLY 1'b0;
end
aurora_64b66b_25p4G_rst_sync u_rst_sync_r_sync3
(
.prmry_in ( fifo_reset_rd ),
.scndry_aclk ( user_clk ),
.scndry_out ( fifo_reset_wr_sync3 )
);
assign fifo_reset_comb = fifo_reset_wr_sync3 | reset_cbcc_comb;
//----- fifo_reset_comb ----}
//---- fifo_reset_comb_user_clk fifo_reset_comb_read_clk ---{
//below signal will go to fifo_reset_i generation , wr domain as well as rd domain logic
//--- emulating 9 stages for fifo_reset_comb_user_clk from fifo_reset_comb to account for data path delays
aurora_64b66b_25p4G_rst_sync #
(
.c_mtbf_stages (11)
)u_rst_sync_fifo_reset_user_clk
(
.prmry_in (fifo_reset_comb),
.scndry_aclk (user_clk ),
.scndry_out (fifo_reset_comb_user_clk)
);
aurora_64b66b_25p4G_rst_sync u_rst_sync_cbcc_fifo_reset_rd_clk
(
.prmry_in (fifo_reset_comb_user_clk),
.scndry_aclk (rd_clk),
.scndry_out (fifo_reset_comb_read_clk)
);
//---- fifo_reset_comb_user_clk fifo_reset_comb_read_clk ---}
//---- cbcc_fifo_reset_to_fifo_wr_clk ----{
wire fifo_reset_comb_user_clk_int;
reg fifo_reset_comb_user_clk_int_22q =1'b1;
aurora_64b66b_25p4G_rst_sync #
(
.c_mtbf_stages (21)
) u_rst_sync_fifo_reset_comb_user_clk_in
(
.prmry_in (fifo_reset_comb_user_clk),
.scndry_aclk (user_clk),
.scndry_out (fifo_reset_comb_user_clk_int)
);
always @(posedge user_clk)
begin
fifo_reset_comb_user_clk_int_22q <= `DLY fifo_reset_comb_user_clk_int;
end
aurora_64b66b_25p4G_rst_sync #
(
.c_mtbf_stages (9)
) u_rst_sync_reset_to_fifo_wr_clk
(
.prmry_in (fifo_reset_comb_user_clk_int_22q),
.scndry_aclk (user_clk),
.scndry_out (cbcc_fifo_reset_to_fifo_wr_clk)
);
reg dbg_srst_assert = 1'b0;
always @(posedge user_clk)
begin
dbg_srst_assert <= `DLY (fifo_reset_comb_user_clk_int_22q && !(fifo_reset_comb_user_clk_int));
end
localparam dbg_srst_high_period = 4'd11;
reg [3:0] dbg_extend_srst = 4'd11;
always @(posedge user_clk)
begin
if(dbg_srst_assert)
dbg_extend_srst <= `DLY 4'd0;
else if(dbg_extend_srst < dbg_srst_high_period)
dbg_extend_srst <= `DLY dbg_extend_srst + 1'b1;
end
always @(posedge user_clk)
begin
cbcc_data_srst <= `DLY dbg_srst_assert || (dbg_extend_srst < dbg_srst_high_period);
end
//---- cbcc_fifo_reset_to_fifo_wr_clk ----}
//---- cbcc_fifo_reset_to_fifo_rd_clk ----{
aurora_64b66b_25p4G_rst_sync #
(
.c_mtbf_stages (31)
) u_rst_sync_reset_to_fifo_rd_clk
(
.prmry_in (fifo_reset_comb_read_clk),
.scndry_aclk (rd_clk),
.scndry_out (cbcc_fifo_reset_to_fifo_rd_clk)
);
//---- cbcc_fifo_reset_to_fifo_rd_clk ----}
//---- cbcc_fifo_reset_wr_clk ---{
wire cbcc_fifo_reset_wr_clk_pre;
(* shift_extract = "{no}" *) reg cbcc_fifo_reset_to_fifo_wr_clk_dlyd = 1'b1;
always @(posedge user_clk)
begin
cbcc_fifo_reset_to_fifo_wr_clk_dlyd <= `DLY cbcc_fifo_reset_to_fifo_wr_clk;
end
always @(posedge user_clk)
begin
if(fifo_reset_comb_user_clk)
cbc_wr_if_reset <= 1'b1;
else if(!cbcc_fifo_reset_to_fifo_wr_clk & cbcc_fifo_reset_to_fifo_wr_clk_dlyd)
cbc_wr_if_reset <= 1'b0;
end
aurora_64b66b_25p4G_rst_sync u_rst_sync_reset_wr_clk
(
.prmry_in (cbc_wr_if_reset),
.scndry_aclk (user_clk),
.scndry_out (cbcc_fifo_reset_wr_clk_pre)
);
always @(posedge user_clk)
cbcc_fifo_reset_wr_clk <= `DLY cbcc_fifo_reset_wr_clk_pre;
//---- cbcc_fifo_reset_wr_clk ---}
//---- cbcc_fifo_reset_rd_clk ---{
wire cbcc_fifo_reset_rd_clk_pre;
(* shift_extract = "{no}" *) reg cbc_rd_if_reset = 1'b1;
(* shift_extract = "{no}" *) reg cbcc_fifo_reset_to_fifo_rd_clk_dlyd = 1'b1;
always @(posedge rd_clk)
begin
cbcc_fifo_reset_to_fifo_rd_clk_dlyd <= `DLY cbcc_fifo_reset_to_fifo_rd_clk;
end
always @(posedge rd_clk)
begin
if(fifo_reset_comb_read_clk)
cbc_rd_if_reset <= 1'b1;
else if(!cbcc_fifo_reset_to_fifo_rd_clk & cbcc_fifo_reset_to_fifo_rd_clk_dlyd)
cbc_rd_if_reset <= 1'b0;
end
aurora_64b66b_25p4G_rst_sync u_rst_sync_reset_rd_clk
(
.prmry_in (cbc_rd_if_reset),
.scndry_aclk (rd_clk),
.scndry_out (cbcc_fifo_reset_rd_clk_pre)
);
always @(posedge rd_clk)
cbcc_fifo_reset_rd_clk <= `DLY cbcc_fifo_reset_rd_clk_pre;
//---- cbcc_fifo_reset_rd_clk ---}
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLXBN_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__DLXBN_FUNCTIONAL_PP_V
/**
* dlxbn: Delay latch, inverted enable, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_hd__udp_dlatch_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__dlxbn (
Q ,
Q_N ,
D ,
GATE_N,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input D ;
input GATE_N;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire GATE ;
wire buf_Q;
// Delay Name Output Other arguments
not not0 (GATE , GATE_N );
sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N `UNIT_DELAY dlatch0 (buf_Q , D, GATE, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLXBN_FUNCTIONAL_PP_V |
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_7x_v1_8_pcie_pipe_misc.v
// Version : 1.7
//
// Description: Misc PIPE module for 7-Series PCIe Block
//
//
//
//--------------------------------------------------------------------------------
`timescale 1ps/1ps
module pcie_7x_v1_8_pcie_pipe_misc #
(
parameter PIPE_PIPELINE_STAGES = 0 // 0 - 0 stages, 1 - 1 stage, 2 - 2 stages
)
(
input wire pipe_tx_rcvr_det_i , // PIPE Tx Receiver Detect
input wire pipe_tx_reset_i , // PIPE Tx Reset
input wire pipe_tx_rate_i , // PIPE Tx Rate
input wire pipe_tx_deemph_i , // PIPE Tx Deemphasis
input wire [2:0] pipe_tx_margin_i , // PIPE Tx Margin
input wire pipe_tx_swing_i , // PIPE Tx Swing
output wire pipe_tx_rcvr_det_o , // Pipelined PIPE Tx Receiver Detect
output wire pipe_tx_reset_o , // Pipelined PIPE Tx Reset
output wire pipe_tx_rate_o , // Pipelined PIPE Tx Rate
output wire pipe_tx_deemph_o , // Pipelined PIPE Tx Deemphasis
output wire [2:0] pipe_tx_margin_o , // Pipelined PIPE Tx Margin
output wire pipe_tx_swing_o , // Pipelined PIPE Tx Swing
input wire pipe_clk , // PIPE Clock
input wire rst_n // Reset
);
//******************************************************************//
// Reality check. //
//******************************************************************//
parameter TCQ = 1; // clock to out delay model
reg pipe_tx_rcvr_det_q ;
reg pipe_tx_reset_q ;
reg pipe_tx_rate_q ;
reg pipe_tx_deemph_q ;
reg [2:0] pipe_tx_margin_q ;
reg pipe_tx_swing_q ;
reg pipe_tx_rcvr_det_qq ;
reg pipe_tx_reset_qq ;
reg pipe_tx_rate_qq ;
reg pipe_tx_deemph_qq ;
reg [2:0] pipe_tx_margin_qq ;
reg pipe_tx_swing_qq ;
generate
if (PIPE_PIPELINE_STAGES == 0) begin : pipe_stages_0
assign pipe_tx_rcvr_det_o = pipe_tx_rcvr_det_i;
assign pipe_tx_reset_o = pipe_tx_reset_i;
assign pipe_tx_rate_o = pipe_tx_rate_i;
assign pipe_tx_deemph_o = pipe_tx_deemph_i;
assign pipe_tx_margin_o = pipe_tx_margin_i;
assign pipe_tx_swing_o = pipe_tx_swing_i;
end // if (PIPE_PIPELINE_STAGES == 0)
else if (PIPE_PIPELINE_STAGES == 1) begin : pipe_stages_1
always @(posedge pipe_clk) begin
if (rst_n)
begin
pipe_tx_rcvr_det_q <= #TCQ 0;
pipe_tx_reset_q <= #TCQ 1'b1;
pipe_tx_rate_q <= #TCQ 0;
pipe_tx_deemph_q <= #TCQ 1'b1;
pipe_tx_margin_q <= #TCQ 0;
pipe_tx_swing_q <= #TCQ 0;
end
else
begin
pipe_tx_rcvr_det_q <= #TCQ pipe_tx_rcvr_det_i;
pipe_tx_reset_q <= #TCQ pipe_tx_reset_i;
pipe_tx_rate_q <= #TCQ pipe_tx_rate_i;
pipe_tx_deemph_q <= #TCQ pipe_tx_deemph_i;
pipe_tx_margin_q <= #TCQ pipe_tx_margin_i;
pipe_tx_swing_q <= #TCQ pipe_tx_swing_i;
end
end
assign pipe_tx_rcvr_det_o = pipe_tx_rcvr_det_q;
assign pipe_tx_reset_o = pipe_tx_reset_q;
assign pipe_tx_rate_o = pipe_tx_rate_q;
assign pipe_tx_deemph_o = pipe_tx_deemph_q;
assign pipe_tx_margin_o = pipe_tx_margin_q;
assign pipe_tx_swing_o = pipe_tx_swing_q;
end // if (PIPE_PIPELINE_STAGES == 1)
else if (PIPE_PIPELINE_STAGES == 2) begin : pipe_stages_2
always @(posedge pipe_clk) begin
if (rst_n)
begin
pipe_tx_rcvr_det_q <= #TCQ 0;
pipe_tx_reset_q <= #TCQ 1'b1;
pipe_tx_rate_q <= #TCQ 0;
pipe_tx_deemph_q <= #TCQ 1'b1;
pipe_tx_margin_q <= #TCQ 0;
pipe_tx_swing_q <= #TCQ 0;
pipe_tx_rcvr_det_qq <= #TCQ 0;
pipe_tx_reset_qq <= #TCQ 1'b1;
pipe_tx_rate_qq <= #TCQ 0;
pipe_tx_deemph_qq <= #TCQ 1'b1;
pipe_tx_margin_qq <= #TCQ 0;
pipe_tx_swing_qq <= #TCQ 0;
end
else
begin
pipe_tx_rcvr_det_q <= #TCQ pipe_tx_rcvr_det_i;
pipe_tx_reset_q <= #TCQ pipe_tx_reset_i;
pipe_tx_rate_q <= #TCQ pipe_tx_rate_i;
pipe_tx_deemph_q <= #TCQ pipe_tx_deemph_i;
pipe_tx_margin_q <= #TCQ pipe_tx_margin_i;
pipe_tx_swing_q <= #TCQ pipe_tx_swing_i;
pipe_tx_rcvr_det_qq <= #TCQ pipe_tx_rcvr_det_q;
pipe_tx_reset_qq <= #TCQ pipe_tx_reset_q;
pipe_tx_rate_qq <= #TCQ pipe_tx_rate_q;
pipe_tx_deemph_qq <= #TCQ pipe_tx_deemph_q;
pipe_tx_margin_qq <= #TCQ pipe_tx_margin_q;
pipe_tx_swing_qq <= #TCQ pipe_tx_swing_q;
end
end
assign pipe_tx_rcvr_det_o = pipe_tx_rcvr_det_qq;
assign pipe_tx_reset_o = pipe_tx_reset_qq;
assign pipe_tx_rate_o = pipe_tx_rate_qq;
assign pipe_tx_deemph_o = pipe_tx_deemph_qq;
assign pipe_tx_margin_o = pipe_tx_margin_qq;
assign pipe_tx_swing_o = pipe_tx_swing_qq;
end // if (PIPE_PIPELINE_STAGES == 2)
endgenerate
endmodule
|
`timescale 1ns/1ns
module usb_sof
(input c,
input c_12,
input start,
output done,
inout vp,
inout vm);
wire [4:0] crc5;
wire [31:0] sof_pkt = { crc5,
frame_number,
8'b10100101, // SOF PID
8'b11010101 };
wire [10:0] crc5_data_in =
{ frame_number[0], frame_number[1], frame_number[2], frame_number[3],
frame_number[4], frame_number[5], frame_number[6], frame_number[7],
frame_number[8], frame_number[9], frame_number[10] }; // abomination
wire crc5_en, crc5_rst;
usb_crc5 usb_crc5_inst
(.clk(c), .rst(crc5_rst),
.data_in(crc5_data_in), .crc_en(crc5_en), .crc_out(crc5));
localparam ST_IDLE = 4'd0;
localparam ST_CALC_CRC = 4'd1;
localparam ST_STX = 4'd2;
localparam ST_TX = 4'd3;
localparam SW=4, CW=5;
reg [CW+SW-1:0] ctrl;
wire [SW-1:0] state;
wire [SW-1:0] next_state = ctrl[SW+CW-1:CW];
r #(SW) state_r
(.c(c), .rst(1'b0), .en(1'b1), .d(next_state), .q(state));
wire cnt_rst;
wire cnt_en = 1'b1;
wire [7:0] cnt; // counter used by many states
r #(8) cnt_r(.c(c), .rst(cnt_rst), .en(cnt_en), .d(cnt + 1'b1), .q(cnt));
wire tx_load; // in c12 domain
wire tx_load_flag = state == ST_STX;
sync tx_load_r(.in(tx_load_flag), .clk(c_12), .out(tx_load));
wire [7:0] tx_cnt;
r #(8) tx_cnt_r
(.c(c_12), .rst(tx_load), .en(tx_cnt < 6'd32), .d(tx_cnt+1'b1), .q(tx_cnt));
wire [31:0] pkt_xclk;
sync #(32) pkt_xclk_r(.in(sof_pkt), .clk(c_12), .out(pkt_xclk));
wire [31:0] shift;
r #(32) shift_r
(.c(c_12), .rst(1'b0), .en(1'b1),
.d(tx_load ? pkt_xclk : {1'b0, shift[31:1]}), .q(shift));
assign vp = |tx_cnt & tx_cnt < 6'd32 ? shift[0] : 1'bz;
assign vm = |tx_cnt & tx_cnt < 6'd32 ? ~shift[0] : 1'bz;
always @* begin
case (state)
ST_IDLE:
if (start) ctrl = { ST_CALC_CRC, 5'b00000 };
else ctrl = { ST_IDLE , 5'b00000 };
ST_CALC_CRC: ctrl = { ST_STX , 5'b00000 };
ST_STX:
if (cnt == 8'd15) ctrl = { ST_TX , 5'b00000 };
else ctrl = { ST_STX , 5'b00000 };
ST_TX:
if (cnt == 8'd32) ctrl = { ST_IDLE , 5'b00010 };
else ctrl = { ST_TX , 5'b00000 };
default: ctrl = { ST_IDLE , 5'b00000 };
endcase
end
assign crc5_rst = state == ST_IDLE;
assign crc5_en = state == ST_CALC_CRC;
assign done = ctrl[1];
wire tx_en = ctrl[0];
endmodule
`ifdef TEST_USB_SOF
module tb();
wire c, c_12;
sim_clk #(125) clk_125(c);
sim_clk #(12) clk_12(c_12);
wire vp, vm;
reg start;
wire done;
usb_sof sof_inst(.*);
initial begin
start <= 1'b0;
$dumpfile("sof.lxt");
$dumpvars();
wait(~c);
wait(c);
wait(~c);
start <= 1'b1;
wait(c);
wait(~c);
start <= 1'b0;
wait(c);
wait(~c);
#10000;
wait(c);
wait(~c);
start <= 1'b1;
wait(c);
wait(~c);
start <= 1'b0;
wait(c);
wait(~c);
#10000;
$finish();
end
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFRTN_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__SDFRTN_PP_SYMBOL_V
/**
* sdfrtn: Scan delay flop, inverted reset, inverted clock,
* single output.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__sdfrtn (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET_B,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK_N ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFRTN_PP_SYMBOL_V
|
module fpu_tb ();
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire div_zero_o; // From DUT of fpu_arith.v
wire ine_o; // From DUT of fpu_arith.v
wire inf_o; // From DUT of fpu_arith.v
wire [32-1:0] output_o; // From DUT of fpu_arith.v
wire overflow_o; // From DUT of fpu_arith.v
wire qnan_o; // From DUT of fpu_arith.v
wire ready_o; // From DUT of fpu_arith.v
wire snan_o; // From DUT of fpu_arith.v
wire underflow_o; // From DUT of fpu_arith.v
wire zero_o; // From DUT of fpu_arith.v
// End of automatics
/*AUTOREGINPUT*/
// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
reg clk; // To DUT of fpu_arith.v
reg [2:0] fpu_op_i; // To DUT of fpu_arith.v
reg [32-1:0] opa_i; // To DUT of fpu_arith.v
reg [32-1:0] opb_i; // To DUT of fpu_arith.v
reg [1:0] rmode_i; // To DUT of fpu_arith.v
reg rst; // To DUT of fpu_arith.v
reg start_i; // To DUT of fpu_arith.v
// End of automatics
reg goahead;
fpu_arith DUT
(
// Outputs
.ready_o (ready_o),
.output_o (output_o[32-1:0]),
.ine_o (ine_o),
.overflow_o (overflow_o),
.underflow_o (underflow_o),
.div_zero_o (div_zero_o),
.inf_o (inf_o),
.zero_o (zero_o),
.qnan_o (qnan_o),
.snan_o (snan_o),
// Inputs
.clk (clk),
.rst (rst),
.opa_i (opa_i[32-1:0]),
.opb_i (opb_i[32-1:0]),
.fpu_op_i (fpu_op_i[2:0]),
.rmode_i (rmode_i[1:0]),
.start_i (start_i));
// Stimulus
// clock
initial begin
clk = 0;
while (1) begin
#40;
clk = ~clk;
end
end
// reset
initial begin
rst = 1;
#200;
rst = 0;
#10000;
$finish;
end
always @(posedge clk or posedge rst)
begin
if (rst)
begin
opa_i <= 'd0;
opb_i <= 'd0;
fpu_op_i <= 'd0;
rmode_i <= 'd0;
start_i <= 1'b0;
goahead <= 1'b1;
end
else
begin
if (goahead)
begin
opa_i <= $random;
opb_i <= $random;
fpu_op_i <= 3'd2;
rmode_i <= 2'd0;
start_i <= 1'b1;
end
else
begin
start_i <= 1'b0;
end
if (goahead)
goahead <= 1'b0;
else if (ready_o)
goahead <= 1'b1;
end // else: !if(rst)
end // always @ (posedge clk or posedge rst)
//waveforms
initial begin
if ($test$plusargs("dump_waveforms")) begin
$vcdpluson(0,fpu_tb);
//$vcdpluson(<level>,scope,<signal>);
//Lots of options for dumping waves
//(both system calls and run time arguments)
// http://read.pudn.com/downloads97/sourcecode/others/399556/vcs_0123.pdf
end
end
endmodule // fpu_tb
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A2111O_FUNCTIONAL_V
`define SKY130_FD_SC_HS__A2111O_FUNCTIONAL_V
/**
* a2111o: 2-input AND into first input of 4-input OR.
*
* X = ((A1 & A2) | B1 | C1 | D1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a2111o (
VPWR,
VGND,
X ,
A1 ,
A2 ,
B1 ,
C1 ,
D1
);
// Module ports
input VPWR;
input VGND;
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
// Local signals
wire C1 and0_out ;
wire or0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
or or0 (or0_out_X , C1, B1, and0_out, D1 );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A2111O_FUNCTIONAL_V |
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized COMPARATOR (against constant) with generic_baseblocks_v2_1_carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_comparator_sel_static #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter C_VALUE = 4'b0,
// Static value to compare against.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire S,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] B,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar bit_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 2;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_FIX_DATA_WIDTH-1:0] v_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign v_local = {C_VALUE, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = B;
assign v_local = C_VALUE;
end
// Instantiate one generic_baseblocks_v2_1_carry and per level.
for (bit_cnt = 0; bit_cnt < C_NUM_LUT ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[bit_cnt] = ( ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b0 ) ) |
( ( b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b1 ) );
// Instantiate each LUT level.
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[bit_cnt+1]),
.CIN (carry_local[bit_cnt]),
.S (sel[bit_cnt])
);
end // end for bit_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule
|
module prometheus_fx3_partial(
input rst_n,
input clk_100,
input partial_mode_selected,
input i_gpif_in_ch0_rdy_d,
input i_gpif_out_ch0_rdy_d,
output o_gpif_we_n_partial_,
output o_gpif_pkt_end_n_partial_,
output [31:0] data_out_partial
);
reg [2:0]current_partial_state;
reg [2:0]next_partial_state;
//parameters for PARTIAL mode state machine
parameter [2:0] partial_idle = 3'd0;
parameter [2:0] partial_wait_flagb = 3'd1;
parameter [2:0] partial_write = 3'd2;
parameter [2:0] partial_write_wr_delay = 3'd3;
parameter [2:0] partial_wait = 3'd4;
reg [3:0] strob_cnt;
reg strob;
reg [3:0] short_pkt_cnt;
reg [31:0]data_gen_partial;
reg o_gpif_pkt_end_n_prtl_;
assign o_gpif_we_n_partial_ = ((current_partial_state == partial_write) && (i_gpif_out_ch0_rdy_d == 1'b1)) ? 1'b0 : 1'b1;
//counters for short pkt
always @(posedge clk_100, negedge rst_n)begin
if(!rst_n)begin
short_pkt_cnt <= 4'd0;
end else if(current_partial_state == partial_idle)begin
short_pkt_cnt <= 4'd0;
end else if((current_partial_state == partial_write))begin
short_pkt_cnt <= short_pkt_cnt + 1'b1;
end
end
//counter to generate the strob for PARTIAL
always @(posedge clk_100, negedge rst_n)begin
if(!rst_n)begin
strob_cnt <= 4'd0;
end else if(current_partial_state == partial_idle)begin
strob_cnt <= 4'd0;
end else if(current_partial_state == partial_wait)begin
strob_cnt <= strob_cnt + 1'b1;
end
end
//Strob logic
always@(posedge clk_100, negedge rst_n)begin
if(!rst_n)begin
strob <= 1'b0;
end else if((current_partial_state == partial_wait) && (strob_cnt == 4'b0111)) begin
strob <= !strob;
end
end
always@(*)begin
if((partial_mode_selected) & (strob == 1'b1) & (short_pkt_cnt == 4'b1111))begin
o_gpif_pkt_end_n_prtl_ = 1'b0;
end else begin
o_gpif_pkt_end_n_prtl_ = 1'b1;
end
end
assign o_gpif_pkt_end_n_partial_ = o_gpif_pkt_end_n_prtl_;
//PARTIAL mode state machine
always @(posedge clk_100, negedge rst_n)begin
if(!rst_n)begin
current_partial_state <= partial_idle;
end else begin
current_partial_state <= next_partial_state;
end
end
//PARTIAL mode state machine combo
always @(*)begin
next_partial_state = current_partial_state;
case(current_partial_state)
partial_idle:begin
if((partial_mode_selected) & (i_gpif_in_ch0_rdy_d == 1'b1))begin
next_partial_state = partial_wait_flagb;
end else begin
next_partial_state = partial_idle;
end
end
partial_wait_flagb :begin
if (i_gpif_out_ch0_rdy_d == 1'b1)begin
next_partial_state = partial_write;
end else begin
next_partial_state = partial_wait_flagb;
end
end
partial_write:begin
if((i_gpif_out_ch0_rdy_d == 1'b0) | ((strob == 1'b1) & (short_pkt_cnt == 4'b1111)))begin
next_partial_state = partial_write_wr_delay;
end else begin
next_partial_state = partial_write;
end
end
partial_write_wr_delay:begin
next_partial_state = partial_wait;
end
partial_wait:begin
if(strob_cnt == 4'b0111)begin
next_partial_state = partial_idle;
end else begin
next_partial_state = partial_wait;
end
end
endcase
end
//data generator counter for Partial mode
always @(posedge clk_100, negedge rst_n)begin
if(!rst_n)begin
data_gen_partial <= 32'd0;
end else if((o_gpif_we_n_partial_ == 1'b0) & (partial_mode_selected)) begin
data_gen_partial <= data_gen_partial + 1;
end else if (!partial_mode_selected) begin
data_gen_partial <= 32'd0;
end
end
assign data_out_partial = data_gen_partial;
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// tx_queue.v. Derived from NetFPGA project.
// vim:set shiftwidth=3 softtabstop=3 expandtab:
// $Id: tx_queue.v 2080 2007-08-02 17:19:29Z grg $
//
// Module: tx_queue.v
// Project: NF2.1
// Description: Instantiates the speed matching FIFO that accepts
// packets from the core and sends it to the MAC
//
// On the read side is the 125/12.5/1.25MHz MAC clock which reads
// data 9 bits wide from the fifo (bit 8 is EOP).
//
///////////////////////////////////////////////////////////////////////////////
module tx_queue
#(
parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH = DATA_WIDTH/8,
parameter ENABLE_HEADER = 1,
parameter STAGE_NUMBER = 'hff,
parameter AXI_DATA_WIDTH = 32,
parameter AXI_KEEP_WIDTH = AXI_DATA_WIDTH/8
)
(input [DATA_WIDTH-1:0] in_data,
input [CTRL_WIDTH-1:0] in_ctrl,
input in_wr,
output in_rdy,
// --- MAC side signals (m_tx_axis_aclk domain)
input m_tx_axis_aclk,
output reg m_tx_axis_tvalid,
output [AXI_DATA_WIDTH - 1 : 0] m_tx_axis_tdata,
output reg m_tx_axis_tlast,
output reg [AXI_KEEP_WIDTH - 1 : 0] m_tx_axis_tkeep,
input m_tx_axis_tready,
// --- Register interface
input tx_queue_en,
output tx_pkt_sent,
output reg tx_pkt_stored,
output reg [11:0] tx_pkt_byte_cnt,
output reg tx_pkt_byte_cnt_vld,
output reg [9:0] tx_pkt_word_cnt,
// --- Misc
input reset,
input clk
);
// ------------ Internal Params --------
//state machine states (one-hot)
localparam IDLE = 1;
localparam WAIT_FOR_READY = 2;
localparam WAIT_FOR_EOP = 4;
localparam INPUT_IDLE = 1;
localparam INPUT_PKTS = 2;
// Number of packets waiting:
//
// 4096 / 64 = 64 = 2**6
//
// so, need 7 bits to represent the number of packets waiting
localparam NUM_PKTS_WAITING_WIDTH = 7;
// ------------- Regs/ wires -----------
wire [DATA_WIDTH+CTRL_WIDTH - 1 : 0] tx_fifo_din;
wire [AXI_DATA_WIDTH - 1 : 0] tx_fifo_out_data;
wire [AXI_KEEP_WIDTH - 1 : 0] tx_fifo_out_ctrl;
reg tx_fifo_rd_en;
wire tx_fifo_empty;
wire tx_fifo_almost_full;
reg reset_txclk;
reg pkt_sent_txclk; // pulses when a packet has been removed
reg [4:0] tx_mac_state_nxt, tx_mac_state;
reg m_tx_axis_tvalid_nxt;
reg tx_queue_en_txclk;
reg tx_queue_en_sync;
// synthesis attribute ASYNC_REG of tx_queue_en_sync is TRUE;
reg [NUM_PKTS_WAITING_WIDTH-1:0] txf_num_pkts_waiting;
wire txf_pkts_avail;
reg [4:0] tx_input_state, tx_input_state_nxt;
reg tx_fifo_wr_en;
reg need_clear_padding;
assign in_rdy = ~tx_fifo_almost_full;
//--------------------------------------------------------------
// synchronize
//--------------------------------------------------------------
// extend reset over to MAC domain
reg reset_long;
// synthesis attribute ASYNC_REG of reset_long is TRUE ;
always @(posedge clk) begin
if (reset) reset_long <= 1;
else if (reset_txclk) reset_long <= 0;
end
always @(posedge m_tx_axis_aclk) reset_txclk <= reset_long;
//---------------------------------------------------------------
// packet fifo input and output logic
//---------------------------------------------------------------
assign tx_fifo_din = {in_ctrl[7:4], in_data[63:32],in_ctrl[3:0], in_data[31:0]};
txfifo_512x72_to_36 gmac_tx_fifo
(
.din (tx_fifo_din),
.wr_en (tx_fifo_wr_en),
.wr_clk (clk),
.dout ({tx_fifo_out_ctrl,tx_fifo_out_data}),
.rd_en (tx_fifo_rd_en),
.rd_clk (m_tx_axis_aclk),
.empty (tx_fifo_empty),
.full (),
.almost_full(tx_fifo_almost_full),
.rst (reset)
);
// Reorder the output: AXI-S uses little endian, the User Data Path uses big endian
generate
genvar k;
for(k=0; k<AXI_KEEP_WIDTH; k=k+1) begin: reorder_endianness
assign m_tx_axis_tdata[8*k+:8] = tx_fifo_out_data[AXI_DATA_WIDTH-8-8*k+:8];
end
endgenerate
//----------------------------------------------------------
//input state machine.
//Following is in core clock domain (62MHz/125 MHz)
//----------------------------------------------------------
always @(*)begin
tx_fifo_wr_en = 0;
tx_pkt_stored = 0;
tx_pkt_byte_cnt = 0;
tx_pkt_byte_cnt_vld = 0;
tx_pkt_word_cnt = 0;
tx_input_state_nxt = tx_input_state;
case (tx_input_state)
INPUT_IDLE: begin
if(in_wr && in_ctrl == STAGE_NUMBER)begin
tx_pkt_byte_cnt = in_data[`IOQ_BYTE_LEN_POS +: 16];
tx_pkt_word_cnt = in_data[`IOQ_WORD_LEN_POS +: 16];
tx_pkt_byte_cnt_vld = 1'b1;
end
else if(in_wr && in_ctrl == 0)begin //just ignore other module header
tx_fifo_wr_en = 1'b1;
tx_input_state_nxt = INPUT_PKTS;
end
end
INPUT_PKTS: begin
if(in_wr)begin
tx_fifo_wr_en = 1'b1;
if(|in_ctrl) begin
tx_pkt_stored = 1'b1;
tx_input_state_nxt = INPUT_IDLE;
end
end
end
endcase
end
always @(posedge clk) begin
if(reset) begin
tx_input_state <= INPUT_IDLE;
end
else tx_input_state <= tx_input_state_nxt;
end
//---------------------------------------------------------------
//output state machine
// Following is in MAC clock domain (125MHz/12.5Mhz/1.25Mhz)
//---------------------------------------------------------------
// sync the enable signal from the core to the tx clock domains
always @(posedge m_tx_axis_aclk) begin
if(reset_txclk) begin
tx_queue_en_sync <= 0;
tx_queue_en_txclk <= 0;
end
else begin
tx_queue_en_sync <= tx_queue_en;
tx_queue_en_txclk <= tx_queue_en_sync;
end
end
always @* begin
tx_mac_state_nxt = tx_mac_state;
tx_fifo_rd_en = 1'b0;
m_tx_axis_tvalid_nxt = 1'b0;
pkt_sent_txclk = 1'b0;
case (tx_mac_state)
IDLE: if (txf_pkts_avail & !tx_fifo_empty & tx_queue_en_txclk ) begin
tx_fifo_rd_en = 1; // this will make DOUT of FIFO valid after the NEXT clock
m_tx_axis_tvalid_nxt = 1;
tx_mac_state_nxt = WAIT_FOR_READY;
end
WAIT_FOR_READY:begin
m_tx_axis_tvalid_nxt = 1;
if(m_tx_axis_tready)begin
tx_fifo_rd_en = 1;
tx_mac_state_nxt = WAIT_FOR_EOP;
end
end
WAIT_FOR_EOP: begin
m_tx_axis_tvalid_nxt = 1;
if(|tx_fifo_out_ctrl) begin
m_tx_axis_tvalid_nxt = 0;
tx_mac_state_nxt = IDLE;
if (need_clear_padding) begin // the last data byte was the last of the word so we are done.
tx_fifo_rd_en = 1;
end
else tx_fifo_rd_en = 0;
end
else if(m_tx_axis_tready)begin // Not EOP - keep reading!
tx_fifo_rd_en = 1;
//m_tx_axis_tvalid_nxt = 1;
end
end
endcase
end
always @(*)begin
if(tx_mac_state == WAIT_FOR_READY || tx_mac_state == WAIT_FOR_EOP)begin
case (tx_fifo_out_ctrl)
4'b1000: begin
m_tx_axis_tkeep = 4'b0001;
m_tx_axis_tlast = 1'b1;
end
4'b0100: begin
m_tx_axis_tkeep = 4'b0011;
m_tx_axis_tlast = 1'b1;
end
4'b0010: begin
m_tx_axis_tkeep = 4'b0111;
m_tx_axis_tlast = 1'b1;
end
4'b0001: begin
m_tx_axis_tkeep = 4'b1111;
m_tx_axis_tlast = 1'b1;
end
default: begin
m_tx_axis_tlast = 1'b0;
m_tx_axis_tkeep = 4'b1111;
end
endcase
end
else begin
m_tx_axis_tkeep = 1'b0;
m_tx_axis_tlast = 1'b0;
end
end
// update sequential elements
always @(posedge m_tx_axis_aclk) begin
if (reset_txclk) begin
tx_mac_state <= IDLE;
m_tx_axis_tvalid <= 0;
need_clear_padding <= 0;
end
else begin
tx_mac_state <= tx_mac_state_nxt;
m_tx_axis_tvalid <= m_tx_axis_tvalid_nxt;
if(tx_fifo_rd_en) need_clear_padding <= !need_clear_padding;
end
end // always @ (posedge m_tx_axis_aclk)
//-------------------------------------------------------------------
// stats
//-------------------------------------------------------------------
/* these modules move pulses from one clk domain to the other */
pulse_synchronizer tx_pkt_stored_sync
(.pulse_in_clkA (tx_pkt_stored),
.clkA (clk),
.pulse_out_clkB(pkt_stored_txclk),
.clkB (m_tx_axis_aclk),
.reset_clkA (reset),
.reset_clkB (reset_txclk));
pulse_synchronizer tx_pkt_sent_sync
(.pulse_in_clkA (pkt_sent_txclk),
.clkA (m_tx_axis_aclk),
.pulse_out_clkB(tx_pkt_sent),
.clkB (clk),
.reset_clkA (reset_txclk),
.reset_clkB (reset));
//stats
always @(posedge m_tx_axis_aclk) begin
if (reset_txclk) begin
txf_num_pkts_waiting <= 'h0;
end
else begin
case ({pkt_sent_txclk, pkt_stored_txclk})
2'b01 : txf_num_pkts_waiting <= txf_num_pkts_waiting + 1;
2'b10 : txf_num_pkts_waiting <= txf_num_pkts_waiting - 1;
default: begin end
endcase
end
end // always @ (posedge m_tx_axis_aclk)
assign txf_pkts_avail = (txf_num_pkts_waiting != 'h0);
endmodule // tx_queue
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NOR3_2_V
`define SKY130_FD_SC_HS__NOR3_2_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Verilog wrapper for nor3 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__nor3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__nor3_2 (
Y ,
A ,
B ,
C ,
VPWR,
VGND
);
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
sky130_fd_sc_hs__nor3 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__nor3_2 (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__nor3 base (
.Y(Y),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__NOR3_2_V
|
//////////////////////////////////////////////////////////////////////////////////
//
// This file is part of the N64 RGB/YPbPr DAC project.
//
// Copyright (C) 2015-2021 by Peter Bartmann <[email protected]>
//
// N64 RGB/YPbPr DAC is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
//////////////////////////////////////////////////////////////////////////////////
//
// Company: Circuit-Board.de
// Engineer: borti4938
//
// Module Name: register_sync_2
// Project Name: N64 Advanced RGB/YPbPr DAC Mod
// Target Devices: universial
// Tool versions: Altera Quartus Prime
// Description: generates a reset signal (low-active by default) with duration of
// two clock cycles
//
//////////////////////////////////////////////////////////////////////////////////
module register_sync_2 #(
parameter reg_width = 16,
parameter reg_preset = {reg_width{1'b0}},
parameter resync_stages = 3,
parameter check_valid_data = "ON",
parameter use_valid_o = "ON"
) (
nrst,
clk_i,
clk_i_en,
reg_i,
clk_o,
clk_o_en,
reg_o
);
input nrst;
input clk_i;
input clk_i_en;
input [reg_width-1:0] reg_i;
input clk_o;
input clk_o_en;
output reg [reg_width-1:0] reg_o;
// misc
localparam IN_STATE_IDATA_WAIT = 2'b00;
localparam IN_STATE_ORDY_WAIT = 2'b01;
localparam IN_STATE_OACK_WAIT = 2'b10;
localparam OUT_STATE_IDATA_WAIT = 2'b00;
localparam OUT_STATE_ICONF_WAIT0 = 2'b01;
localparam OUT_STATE_ICONF_WAIT1 = 2'b10;
localparam OUT_STATE_ROUND_WAIT = 2'b11;
integer int_idx;
// wire
wire nrst_i, nrst_o;
wire reg_o_buf_valid_check_w;
// regs
reg [resync_stages-1:0] rdy_fb_i;
reg [resync_stages-1:0] ack_fb_i;
reg [1:0] in_state;
reg [reg_width-1:0] reg_i_buf [0:1] /* synthesis ramstyle = "logic" */;
reg req_i;
reg conf_i;
reg [resync_stages-1:0] req_fwd_o;
reg [resync_stages-1:0] conf_fwd_o;
reg [1:0] out_state;
reg rdy_o;
reg ack_o;
reg [reg_width-1:0] reg_o_buf [0:resync_stages-1] /* synthesis ramstyle = "logic" */;
reg reg_o_buf_valid;
// rtl
// generate reset signals first
reset_generator reset_clk_i_u(
.clk(clk_i),
.clk_en(clk_i_en),
.async_nrst_i(nrst),
.rst_o(nrst_i)
);
reset_generator reset_clk_o_u(
.clk(clk_o),
.clk_en(clk_o_en),
.async_nrst_i(nrst),
.rst_o(nrst_o)
);
// transfer logic with handshake
always @(posedge clk_i or negedge nrst_i)
if (!nrst_i) begin
rdy_fb_i <= {resync_stages{1'b0}};
ack_fb_i <= {resync_stages{1'b0}};
in_state <= IN_STATE_IDATA_WAIT;
reg_i_buf[1] <= reg_preset;
reg_i_buf[0] <= reg_preset;
req_i <= 1'b0;
conf_i <= 1'b0;
end else if (clk_i_en) begin
rdy_fb_i <= {rdy_fb_i[resync_stages-2:0],rdy_o};
ack_fb_i <= {ack_fb_i[resync_stages-2:0],ack_o};
case (in_state)
IN_STATE_IDATA_WAIT:
if (reg_i_buf[0] != reg_i && !ack_fb_i[resync_stages-1]) begin
in_state <= IN_STATE_ORDY_WAIT;
reg_i_buf[0] <= reg_i;
req_i <= 1'b1;
end
IN_STATE_ORDY_WAIT:
if (rdy_fb_i[resync_stages-1]) begin
in_state <= IN_STATE_OACK_WAIT;
reg_i_buf[1] <= reg_i_buf[0];
req_i <= 1'b0;
conf_i <= 1'b1;
end
IN_STATE_OACK_WAIT:
if (ack_fb_i[resync_stages-1]) begin
in_state <= IN_STATE_IDATA_WAIT;
conf_i <= 1'b0;
end
default:
in_state <= IN_STATE_IDATA_WAIT;
endcase
end
generate
if (check_valid_data == "ON" && resync_stages >= 3)
assign reg_o_buf_valid_check_w = reg_o_buf[resync_stages-1] == reg_o_buf[resync_stages-2];
else
assign reg_o_buf_valid_check_w = 1'b1;
endgenerate
always @(posedge clk_o or negedge nrst_o)
if (!nrst_o) begin
req_fwd_o <= {resync_stages{1'b0}};
conf_fwd_o <= {resync_stages{1'b0}};
out_state <= OUT_STATE_IDATA_WAIT;
rdy_o <= 1'b0;
ack_o <= 1'b0;
for (int_idx = 0; int_idx < resync_stages; int_idx = int_idx + 1)
reg_o_buf[int_idx] <= reg_preset;
reg_o_buf_valid <= 1'b0;
end else if (clk_o_en) begin
req_fwd_o <= {req_fwd_o[resync_stages-2:0],req_i};
conf_fwd_o <= {conf_fwd_o[resync_stages-2:0],conf_i};
case (out_state)
OUT_STATE_IDATA_WAIT: begin
if (req_fwd_o[resync_stages-1]) begin
out_state <= OUT_STATE_ICONF_WAIT0;
rdy_o <= 1'b1;
end
reg_o_buf_valid <= 1'b0;
end
OUT_STATE_ICONF_WAIT0:
if (conf_fwd_o[resync_stages-1]) begin
out_state <= OUT_STATE_ICONF_WAIT1;
rdy_o <= 1'b0;
reg_o_buf[0] <= reg_i_buf[1];
end
OUT_STATE_ICONF_WAIT1: begin
out_state <= OUT_STATE_ROUND_WAIT;
ack_o <= 1'b1;
reg_o_buf[0] <= reg_i_buf[1];
end
OUT_STATE_ROUND_WAIT:
if (!conf_fwd_o[resync_stages-1] &&
reg_o_buf_valid_check_w) begin
out_state <= OUT_STATE_IDATA_WAIT;
ack_o <= 1'b0;
reg_o_buf_valid <= 1'b1;
end
default:
out_state <= OUT_STATE_IDATA_WAIT;
endcase
for (int_idx = 1; int_idx < resync_stages; int_idx = int_idx + 1)
reg_o_buf[int_idx] <= reg_o_buf[int_idx-1];
end
generate
if (use_valid_o == "ON") begin
always @(posedge clk_o or negedge nrst_o)
if (!nrst_o) begin
reg_o <= reg_preset;
end else if (clk_o_en) begin
if (reg_o_buf_valid)
reg_o <= reg_o_buf[resync_stages-1];
end
end else begin
always @(*)
reg_o <= reg_o_buf[resync_stages-1];
end
endgenerate
endmodule
|
/*
* Copyright (c) 2001 Stephan Boettcher <[email protected]>
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
// $Id: many_drivers.v,v 1.2 2001/07/21 02:30:44 stevewilliams Exp $
// $Log: many_drivers.v,v $
// Revision 1.2 2001/07/21 02:30:44 stevewilliams
// Get the expected blended values right.
//
// Revision 1.1 2001/07/18 01:22:26 sib4
// test for nets with many drivers
//
module test;
reg [66:0] in;
wire out;
buf (out, in[ 0]);
buf (out, in[ 1]);
buf (out, in[ 2]);
buf (out, in[ 3]);
buf (out, in[ 4]);
buf (out, in[ 5]);
buf (out, in[ 6]);
buf (out, in[ 7]);
buf (out, in[ 8]);
buf (out, in[ 9]);
buf (out, in[10]);
buf (out, in[11]);
buf (out, in[12]);
buf (out, in[13]);
buf (out, in[14]);
buf (out, in[15]);
buf (out, in[16]);
buf (out, in[17]);
buf (out, in[18]);
buf (out, in[19]);
buf (out, in[20]);
buf (out, in[21]);
buf (out, in[22]);
buf (out, in[23]);
buf (out, in[24]);
buf (out, in[25]);
buf (out, in[26]);
buf (out, in[27]);
buf (out, in[28]);
buf (out, in[29]);
buf (out, in[30]);
buf (out, in[31]);
buf (out, in[32]);
buf (out, in[33]);
buf (out, in[34]);
buf (out, in[35]);
buf (out, in[36]);
buf (out, in[37]);
buf (out, in[38]);
buf (out, in[39]);
buf (out, in[40]);
buf (out, in[41]);
buf (out, in[42]);
buf (out, in[43]);
buf (out, in[44]);
buf (out, in[45]);
buf (out, in[46]);
buf (out, in[47]);
buf (out, in[48]);
buf (out, in[49]);
buf (out, in[50]);
buf (out, in[51]);
buf (out, in[52]);
buf (out, in[53]);
buf (out, in[54]);
buf (out, in[55]);
buf (out, in[56]);
buf (out, in[57]);
buf (out, in[58]);
buf (out, in[59]);
buf (out, in[60]);
buf (out, in[61]);
buf (out, in[62]);
buf (out, in[63]);
buf (out, in[64]);
buf (out, in[65]);
buf (out, in[66]);
reg err;
// Verilog-XL yields out=x for all but the first two
initial
begin
err = 0;
in = 67'b0;
#1 $display("in=%b out=%b", in, out);
if (out!==1'b0) err = 1;
in = ~67'b0;
#1 $display("in=%b out=%b", in, out);
if (out!==1'b1) err = 1;
in = 67'bz;
#1 $display("in=%b out=%b", in, out);
if (out!==1'bx) err = 1;
in = 67'bx;
#1 $display("in=%b out=%b", in, out);
if (out!==1'bx) err = 1;
in = 67'h 5_55555555_55555555;
#1 $display("in=%b out=%b", in, out);
if (out!==1'bx) err = 1;
in = ~67'h 5_55555555_55555555;
#1 $display("in=%b out=%b", in, out);
if (out!==1'bx) err = 1;
in = 67'h 0_xxxxxxxx_00000000;
#1 $display("in=%b out=%b", in, out);
if (out!==1'bx) err = 1;
in = ~67'h 0_xxxxxxxx_00000000;
#1 $display("in=%b out=%b", in, out);
if (out!==1'bx) err = 1;
in = 67'h x_xxxxxxxx_00000000;
#1 $display("in=%b out=%b", in, out);
if (out!==1'bx) err = 1;
in = ~67'h x_xxxxxxxx_00000000;
#1 $display("in=%b out=%b", in, out);
if (out!==1'bx) err = 1;
in = 67'h x_55555555_55555555;
#1 $display("in=%b out=%b", in, out);
if (out!==1'bx) err = 1;
in = ~67'h x_55555555_55555555;
#1 $display("in=%b out=%b", in, out);
if (out!==1'bx) err = 1;
in = 67'h 1_ffffxxxx_00000000;
#1 $display("in=%b out=%b", in, out);
if (out!==1'bx) err = 1;
in = ~67'h 1_ffffxxxx_00000000;
#1 $display("in=%b out=%b", in, out);
if (out!==1'bx) err = 1;
if (err)
$display("FAILED");
else
$display("PASSED");
$finish;
end
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_7x_0_core_top_pcie_pipe_pipeline.v
// Version : 3.0
//
// Description: PIPE module for Virtex7 PCIe Block
//
//
//
//--------------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module pcie_7x_0_core_top_pcie_pipe_pipeline #
(
parameter LINK_CAP_MAX_LINK_WIDTH = 8,
parameter PIPE_PIPELINE_STAGES = 0 // 0 - 0 stages, 1 - 1 stage, 2 - 2 stages
)
(
// Pipe Per-Link Signals
input wire pipe_tx_rcvr_det_i ,
input wire pipe_tx_reset_i ,
input wire pipe_tx_rate_i ,
input wire pipe_tx_deemph_i ,
input wire [2:0] pipe_tx_margin_i ,
input wire pipe_tx_swing_i ,
output wire pipe_tx_rcvr_det_o ,
output wire pipe_tx_reset_o ,
output wire pipe_tx_rate_o ,
output wire pipe_tx_deemph_o ,
output wire [2:0] pipe_tx_margin_o ,
output wire pipe_tx_swing_o ,
// Pipe Per-Lane Signals - Lane 0
output wire [ 1:0] pipe_rx0_char_is_k_o ,
output wire [15:0] pipe_rx0_data_o ,
output wire pipe_rx0_valid_o ,
output wire pipe_rx0_chanisaligned_o ,
output wire [ 2:0] pipe_rx0_status_o ,
output wire pipe_rx0_phy_status_o ,
output wire pipe_rx0_elec_idle_o ,
input wire pipe_rx0_polarity_i ,
input wire pipe_tx0_compliance_i ,
input wire [ 1:0] pipe_tx0_char_is_k_i ,
input wire [15:0] pipe_tx0_data_i ,
input wire pipe_tx0_elec_idle_i ,
input wire [ 1:0] pipe_tx0_powerdown_i ,
input wire [ 1:0] pipe_rx0_char_is_k_i ,
input wire [15:0] pipe_rx0_data_i ,
input wire pipe_rx0_valid_i ,
input wire pipe_rx0_chanisaligned_i ,
input wire [ 2:0] pipe_rx0_status_i ,
input wire pipe_rx0_phy_status_i ,
input wire pipe_rx0_elec_idle_i ,
output wire pipe_rx0_polarity_o ,
output wire pipe_tx0_compliance_o ,
output wire [ 1:0] pipe_tx0_char_is_k_o ,
output wire [15:0] pipe_tx0_data_o ,
output wire pipe_tx0_elec_idle_o ,
output wire [ 1:0] pipe_tx0_powerdown_o ,
// Pipe Per-Lane Signals - Lane 1
output wire [ 1:0] pipe_rx1_char_is_k_o ,
output wire [15:0] pipe_rx1_data_o ,
output wire pipe_rx1_valid_o ,
output wire pipe_rx1_chanisaligned_o ,
output wire [ 2:0] pipe_rx1_status_o ,
output wire pipe_rx1_phy_status_o ,
output wire pipe_rx1_elec_idle_o ,
input wire pipe_rx1_polarity_i ,
input wire pipe_tx1_compliance_i ,
input wire [ 1:0] pipe_tx1_char_is_k_i ,
input wire [15:0] pipe_tx1_data_i ,
input wire pipe_tx1_elec_idle_i ,
input wire [ 1:0] pipe_tx1_powerdown_i ,
input wire [ 1:0] pipe_rx1_char_is_k_i ,
input wire [15:0] pipe_rx1_data_i ,
input wire pipe_rx1_valid_i ,
input wire pipe_rx1_chanisaligned_i ,
input wire [ 2:0] pipe_rx1_status_i ,
input wire pipe_rx1_phy_status_i ,
input wire pipe_rx1_elec_idle_i ,
output wire pipe_rx1_polarity_o ,
output wire pipe_tx1_compliance_o ,
output wire [ 1:0] pipe_tx1_char_is_k_o ,
output wire [15:0] pipe_tx1_data_o ,
output wire pipe_tx1_elec_idle_o ,
output wire [ 1:0] pipe_tx1_powerdown_o ,
// Pipe Per-Lane Signals - Lane 2
output wire [ 1:0] pipe_rx2_char_is_k_o ,
output wire [15:0] pipe_rx2_data_o ,
output wire pipe_rx2_valid_o ,
output wire pipe_rx2_chanisaligned_o ,
output wire [ 2:0] pipe_rx2_status_o ,
output wire pipe_rx2_phy_status_o ,
output wire pipe_rx2_elec_idle_o ,
input wire pipe_rx2_polarity_i ,
input wire pipe_tx2_compliance_i ,
input wire [ 1:0] pipe_tx2_char_is_k_i ,
input wire [15:0] pipe_tx2_data_i ,
input wire pipe_tx2_elec_idle_i ,
input wire [ 1:0] pipe_tx2_powerdown_i ,
input wire [ 1:0] pipe_rx2_char_is_k_i ,
input wire [15:0] pipe_rx2_data_i ,
input wire pipe_rx2_valid_i ,
input wire pipe_rx2_chanisaligned_i ,
input wire [ 2:0] pipe_rx2_status_i ,
input wire pipe_rx2_phy_status_i ,
input wire pipe_rx2_elec_idle_i ,
output wire pipe_rx2_polarity_o ,
output wire pipe_tx2_compliance_o ,
output wire [ 1:0] pipe_tx2_char_is_k_o ,
output wire [15:0] pipe_tx2_data_o ,
output wire pipe_tx2_elec_idle_o ,
output wire [ 1:0] pipe_tx2_powerdown_o ,
// Pipe Per-Lane Signals - Lane 3
output wire [ 1:0] pipe_rx3_char_is_k_o ,
output wire [15:0] pipe_rx3_data_o ,
output wire pipe_rx3_valid_o ,
output wire pipe_rx3_chanisaligned_o ,
output wire [ 2:0] pipe_rx3_status_o ,
output wire pipe_rx3_phy_status_o ,
output wire pipe_rx3_elec_idle_o ,
input wire pipe_rx3_polarity_i ,
input wire pipe_tx3_compliance_i ,
input wire [ 1:0] pipe_tx3_char_is_k_i ,
input wire [15:0] pipe_tx3_data_i ,
input wire pipe_tx3_elec_idle_i ,
input wire [ 1:0] pipe_tx3_powerdown_i ,
input wire [ 1:0] pipe_rx3_char_is_k_i ,
input wire [15:0] pipe_rx3_data_i ,
input wire pipe_rx3_valid_i ,
input wire pipe_rx3_chanisaligned_i ,
input wire [ 2:0] pipe_rx3_status_i ,
input wire pipe_rx3_phy_status_i ,
input wire pipe_rx3_elec_idle_i ,
output wire pipe_rx3_polarity_o ,
output wire pipe_tx3_compliance_o ,
output wire [ 1:0] pipe_tx3_char_is_k_o ,
output wire [15:0] pipe_tx3_data_o ,
output wire pipe_tx3_elec_idle_o ,
output wire [ 1:0] pipe_tx3_powerdown_o ,
// Pipe Per-Lane Signals - Lane 4
output wire [ 1:0] pipe_rx4_char_is_k_o ,
output wire [15:0] pipe_rx4_data_o ,
output wire pipe_rx4_valid_o ,
output wire pipe_rx4_chanisaligned_o ,
output wire [ 2:0] pipe_rx4_status_o ,
output wire pipe_rx4_phy_status_o ,
output wire pipe_rx4_elec_idle_o ,
input wire pipe_rx4_polarity_i ,
input wire pipe_tx4_compliance_i ,
input wire [ 1:0] pipe_tx4_char_is_k_i ,
input wire [15:0] pipe_tx4_data_i ,
input wire pipe_tx4_elec_idle_i ,
input wire [ 1:0] pipe_tx4_powerdown_i ,
input wire [ 1:0] pipe_rx4_char_is_k_i ,
input wire [15:0] pipe_rx4_data_i ,
input wire pipe_rx4_valid_i ,
input wire pipe_rx4_chanisaligned_i ,
input wire [ 2:0] pipe_rx4_status_i ,
input wire pipe_rx4_phy_status_i ,
input wire pipe_rx4_elec_idle_i ,
output wire pipe_rx4_polarity_o ,
output wire pipe_tx4_compliance_o ,
output wire [ 1:0] pipe_tx4_char_is_k_o ,
output wire [15:0] pipe_tx4_data_o ,
output wire pipe_tx4_elec_idle_o ,
output wire [ 1:0] pipe_tx4_powerdown_o ,
// Pipe Per-Lane Signals - Lane 5
output wire [ 1:0] pipe_rx5_char_is_k_o ,
output wire [15:0] pipe_rx5_data_o ,
output wire pipe_rx5_valid_o ,
output wire pipe_rx5_chanisaligned_o ,
output wire [ 2:0] pipe_rx5_status_o ,
output wire pipe_rx5_phy_status_o ,
output wire pipe_rx5_elec_idle_o ,
input wire pipe_rx5_polarity_i ,
input wire pipe_tx5_compliance_i ,
input wire [ 1:0] pipe_tx5_char_is_k_i ,
input wire [15:0] pipe_tx5_data_i ,
input wire pipe_tx5_elec_idle_i ,
input wire [ 1:0] pipe_tx5_powerdown_i ,
input wire [ 1:0] pipe_rx5_char_is_k_i ,
input wire [15:0] pipe_rx5_data_i ,
input wire pipe_rx5_valid_i ,
input wire pipe_rx5_chanisaligned_i ,
input wire [ 2:0] pipe_rx5_status_i ,
input wire pipe_rx5_phy_status_i ,
input wire pipe_rx5_elec_idle_i ,
output wire pipe_rx5_polarity_o ,
output wire pipe_tx5_compliance_o ,
output wire [ 1:0] pipe_tx5_char_is_k_o ,
output wire [15:0] pipe_tx5_data_o ,
output wire pipe_tx5_elec_idle_o ,
output wire [ 1:0] pipe_tx5_powerdown_o ,
// Pipe Per-Lane Signals - Lane 6
output wire [ 1:0] pipe_rx6_char_is_k_o ,
output wire [15:0] pipe_rx6_data_o ,
output wire pipe_rx6_valid_o ,
output wire pipe_rx6_chanisaligned_o ,
output wire [ 2:0] pipe_rx6_status_o ,
output wire pipe_rx6_phy_status_o ,
output wire pipe_rx6_elec_idle_o ,
input wire pipe_rx6_polarity_i ,
input wire pipe_tx6_compliance_i ,
input wire [ 1:0] pipe_tx6_char_is_k_i ,
input wire [15:0] pipe_tx6_data_i ,
input wire pipe_tx6_elec_idle_i ,
input wire [ 1:0] pipe_tx6_powerdown_i ,
input wire [ 1:0] pipe_rx6_char_is_k_i ,
input wire [15:0] pipe_rx6_data_i ,
input wire pipe_rx6_valid_i ,
input wire pipe_rx6_chanisaligned_i ,
input wire [ 2:0] pipe_rx6_status_i ,
input wire pipe_rx6_phy_status_i ,
input wire pipe_rx6_elec_idle_i ,
output wire pipe_rx6_polarity_o ,
output wire pipe_tx6_compliance_o ,
output wire [ 1:0] pipe_tx6_char_is_k_o ,
output wire [15:0] pipe_tx6_data_o ,
output wire pipe_tx6_elec_idle_o ,
output wire [ 1:0] pipe_tx6_powerdown_o ,
// Pipe Per-Lane Signals - Lane 7
output wire [ 1:0] pipe_rx7_char_is_k_o ,
output wire [15:0] pipe_rx7_data_o ,
output wire pipe_rx7_valid_o ,
output wire pipe_rx7_chanisaligned_o ,
output wire [ 2:0] pipe_rx7_status_o ,
output wire pipe_rx7_phy_status_o ,
output wire pipe_rx7_elec_idle_o ,
input wire pipe_rx7_polarity_i ,
input wire pipe_tx7_compliance_i ,
input wire [ 1:0] pipe_tx7_char_is_k_i ,
input wire [15:0] pipe_tx7_data_i ,
input wire pipe_tx7_elec_idle_i ,
input wire [ 1:0] pipe_tx7_powerdown_i ,
input wire [ 1:0] pipe_rx7_char_is_k_i ,
input wire [15:0] pipe_rx7_data_i ,
input wire pipe_rx7_valid_i ,
input wire pipe_rx7_chanisaligned_i ,
input wire [ 2:0] pipe_rx7_status_i ,
input wire pipe_rx7_phy_status_i ,
input wire pipe_rx7_elec_idle_i ,
output wire pipe_rx7_polarity_o ,
output wire pipe_tx7_compliance_o ,
output wire [ 1:0] pipe_tx7_char_is_k_o ,
output wire [15:0] pipe_tx7_data_o ,
output wire pipe_tx7_elec_idle_o ,
output wire [ 1:0] pipe_tx7_powerdown_o ,
// Non PIPE signals
input wire pipe_clk ,
input wire rst_n
);
//******************************************************************//
// Reality check. //
//******************************************************************//
//synthesis translate_off
// initial begin
// $display("[%t] %m LINK_CAP_MAX_LINK_WIDTH %0d PIPE_PIPELINE_STAGES %0d",
// $time, LINK_CAP_MAX_LINK_WIDTH, PIPE_PIPELINE_STAGES);
// end
//synthesis translate_on
generate
pcie_7x_0_core_top_pcie_pipe_misc # (
.PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)
)
pipe_misc_i (
.pipe_tx_rcvr_det_i(pipe_tx_rcvr_det_i),
.pipe_tx_reset_i(pipe_tx_reset_i),
.pipe_tx_rate_i(pipe_tx_rate_i),
.pipe_tx_deemph_i(pipe_tx_deemph_i),
.pipe_tx_margin_i(pipe_tx_margin_i),
.pipe_tx_swing_i(pipe_tx_swing_i),
.pipe_tx_rcvr_det_o(pipe_tx_rcvr_det_o),
.pipe_tx_reset_o(pipe_tx_reset_o),
.pipe_tx_rate_o(pipe_tx_rate_o),
.pipe_tx_deemph_o(pipe_tx_deemph_o),
.pipe_tx_margin_o(pipe_tx_margin_o),
.pipe_tx_swing_o(pipe_tx_swing_o) ,
.pipe_clk(pipe_clk),
.rst_n(rst_n)
);
pcie_7x_0_core_top_pcie_pipe_lane # (
.PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)
)
pipe_lane_0_i (
.pipe_rx_char_is_k_o(pipe_rx0_char_is_k_o),
.pipe_rx_data_o(pipe_rx0_data_o),
.pipe_rx_valid_o(pipe_rx0_valid_o),
.pipe_rx_chanisaligned_o(pipe_rx0_chanisaligned_o),
.pipe_rx_status_o(pipe_rx0_status_o),
.pipe_rx_phy_status_o(pipe_rx0_phy_status_o),
.pipe_rx_elec_idle_o(pipe_rx0_elec_idle_o),
.pipe_rx_polarity_i(pipe_rx0_polarity_i),
.pipe_tx_compliance_i(pipe_tx0_compliance_i),
.pipe_tx_char_is_k_i(pipe_tx0_char_is_k_i),
.pipe_tx_data_i(pipe_tx0_data_i),
.pipe_tx_elec_idle_i(pipe_tx0_elec_idle_i),
.pipe_tx_powerdown_i(pipe_tx0_powerdown_i),
.pipe_rx_char_is_k_i(pipe_rx0_char_is_k_i),
.pipe_rx_data_i(pipe_rx0_data_i),
.pipe_rx_valid_i(pipe_rx0_valid_i),
.pipe_rx_chanisaligned_i(pipe_rx0_chanisaligned_i),
.pipe_rx_status_i(pipe_rx0_status_i),
.pipe_rx_phy_status_i(pipe_rx0_phy_status_i),
.pipe_rx_elec_idle_i(pipe_rx0_elec_idle_i),
.pipe_rx_polarity_o(pipe_rx0_polarity_o),
.pipe_tx_compliance_o(pipe_tx0_compliance_o),
.pipe_tx_char_is_k_o(pipe_tx0_char_is_k_o),
.pipe_tx_data_o(pipe_tx0_data_o),
.pipe_tx_elec_idle_o(pipe_tx0_elec_idle_o),
.pipe_tx_powerdown_o(pipe_tx0_powerdown_o),
.pipe_clk(pipe_clk),
.rst_n(rst_n)
);
if (LINK_CAP_MAX_LINK_WIDTH >= 2) begin : pipe_2_lane
pcie_7x_0_core_top_pcie_pipe_lane # (
.PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)
)
pipe_lane_1_i (
.pipe_rx_char_is_k_o(pipe_rx1_char_is_k_o),
.pipe_rx_data_o(pipe_rx1_data_o),
.pipe_rx_valid_o(pipe_rx1_valid_o),
.pipe_rx_chanisaligned_o(pipe_rx1_chanisaligned_o),
.pipe_rx_status_o(pipe_rx1_status_o),
.pipe_rx_phy_status_o(pipe_rx1_phy_status_o),
.pipe_rx_elec_idle_o(pipe_rx1_elec_idle_o),
.pipe_rx_polarity_i(pipe_rx1_polarity_i),
.pipe_tx_compliance_i(pipe_tx1_compliance_i),
.pipe_tx_char_is_k_i(pipe_tx1_char_is_k_i),
.pipe_tx_data_i(pipe_tx1_data_i),
.pipe_tx_elec_idle_i(pipe_tx1_elec_idle_i),
.pipe_tx_powerdown_i(pipe_tx1_powerdown_i),
.pipe_rx_char_is_k_i(pipe_rx1_char_is_k_i),
.pipe_rx_data_i(pipe_rx1_data_i),
.pipe_rx_valid_i(pipe_rx1_valid_i),
.pipe_rx_chanisaligned_i(pipe_rx1_chanisaligned_i),
.pipe_rx_status_i(pipe_rx1_status_i),
.pipe_rx_phy_status_i(pipe_rx1_phy_status_i),
.pipe_rx_elec_idle_i(pipe_rx1_elec_idle_i),
.pipe_rx_polarity_o(pipe_rx1_polarity_o),
.pipe_tx_compliance_o(pipe_tx1_compliance_o),
.pipe_tx_char_is_k_o(pipe_tx1_char_is_k_o),
.pipe_tx_data_o(pipe_tx1_data_o),
.pipe_tx_elec_idle_o(pipe_tx1_elec_idle_o),
.pipe_tx_powerdown_o(pipe_tx1_powerdown_o),
.pipe_clk(pipe_clk),
.rst_n(rst_n)
);
end // if (LINK_CAP_MAX_LINK_WIDTH >= 2)
else
begin
assign pipe_rx1_char_is_k_o = 2'b00;
assign pipe_rx1_data_o = 16'h0000;
assign pipe_rx1_valid_o = 1'b0;
assign pipe_rx1_chanisaligned_o = 1'b0;
assign pipe_rx1_status_o = 3'b000;
assign pipe_rx1_phy_status_o = 1'b0;
assign pipe_rx1_elec_idle_o = 1'b1;
assign pipe_rx1_polarity_o = 1'b0;
assign pipe_tx1_compliance_o = 1'b0;
assign pipe_tx1_char_is_k_o = 2'b00;
assign pipe_tx1_data_o = 16'h0000;
assign pipe_tx1_elec_idle_o = 1'b1;
assign pipe_tx1_powerdown_o = 2'b00;
end // if !(LINK_CAP_MAX_LINK_WIDTH >= 2)
if (LINK_CAP_MAX_LINK_WIDTH >= 4) begin : pipe_4_lane
pcie_7x_0_core_top_pcie_pipe_lane # (
.PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)
)
pipe_lane_2_i (
.pipe_rx_char_is_k_o(pipe_rx2_char_is_k_o),
.pipe_rx_data_o(pipe_rx2_data_o),
.pipe_rx_valid_o(pipe_rx2_valid_o),
.pipe_rx_chanisaligned_o(pipe_rx2_chanisaligned_o),
.pipe_rx_status_o(pipe_rx2_status_o),
.pipe_rx_phy_status_o(pipe_rx2_phy_status_o),
.pipe_rx_elec_idle_o(pipe_rx2_elec_idle_o),
.pipe_rx_polarity_i(pipe_rx2_polarity_i),
.pipe_tx_compliance_i(pipe_tx2_compliance_i),
.pipe_tx_char_is_k_i(pipe_tx2_char_is_k_i),
.pipe_tx_data_i(pipe_tx2_data_i),
.pipe_tx_elec_idle_i(pipe_tx2_elec_idle_i),
.pipe_tx_powerdown_i(pipe_tx2_powerdown_i),
.pipe_rx_char_is_k_i(pipe_rx2_char_is_k_i),
.pipe_rx_data_i(pipe_rx2_data_i),
.pipe_rx_valid_i(pipe_rx2_valid_i),
.pipe_rx_chanisaligned_i(pipe_rx2_chanisaligned_i),
.pipe_rx_status_i(pipe_rx2_status_i),
.pipe_rx_phy_status_i(pipe_rx2_phy_status_i),
.pipe_rx_elec_idle_i(pipe_rx2_elec_idle_i),
.pipe_rx_polarity_o(pipe_rx2_polarity_o),
.pipe_tx_compliance_o(pipe_tx2_compliance_o),
.pipe_tx_char_is_k_o(pipe_tx2_char_is_k_o),
.pipe_tx_data_o(pipe_tx2_data_o),
.pipe_tx_elec_idle_o(pipe_tx2_elec_idle_o),
.pipe_tx_powerdown_o(pipe_tx2_powerdown_o),
.pipe_clk(pipe_clk),
.rst_n(rst_n)
);
pcie_7x_0_core_top_pcie_pipe_lane # (
.PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)
)
pipe_lane_3_i (
.pipe_rx_char_is_k_o(pipe_rx3_char_is_k_o),
.pipe_rx_data_o(pipe_rx3_data_o),
.pipe_rx_valid_o(pipe_rx3_valid_o),
.pipe_rx_chanisaligned_o(pipe_rx3_chanisaligned_o),
.pipe_rx_status_o(pipe_rx3_status_o),
.pipe_rx_phy_status_o(pipe_rx3_phy_status_o),
.pipe_rx_elec_idle_o(pipe_rx3_elec_idle_o),
.pipe_rx_polarity_i(pipe_rx3_polarity_i),
.pipe_tx_compliance_i(pipe_tx3_compliance_i),
.pipe_tx_char_is_k_i(pipe_tx3_char_is_k_i),
.pipe_tx_data_i(pipe_tx3_data_i),
.pipe_tx_elec_idle_i(pipe_tx3_elec_idle_i),
.pipe_tx_powerdown_i(pipe_tx3_powerdown_i),
.pipe_rx_char_is_k_i(pipe_rx3_char_is_k_i),
.pipe_rx_data_i(pipe_rx3_data_i),
.pipe_rx_valid_i(pipe_rx3_valid_i),
.pipe_rx_chanisaligned_i(pipe_rx3_chanisaligned_i),
.pipe_rx_status_i(pipe_rx3_status_i),
.pipe_rx_phy_status_i(pipe_rx3_phy_status_i),
.pipe_rx_elec_idle_i(pipe_rx3_elec_idle_i),
.pipe_rx_polarity_o(pipe_rx3_polarity_o),
.pipe_tx_compliance_o(pipe_tx3_compliance_o),
.pipe_tx_char_is_k_o(pipe_tx3_char_is_k_o),
.pipe_tx_data_o(pipe_tx3_data_o),
.pipe_tx_elec_idle_o(pipe_tx3_elec_idle_o),
.pipe_tx_powerdown_o(pipe_tx3_powerdown_o),
.pipe_clk(pipe_clk),
.rst_n(rst_n)
);
end // if (LINK_CAP_MAX_LINK_WIDTH >= 4)
else
begin
assign pipe_rx2_char_is_k_o = 2'b00;
assign pipe_rx2_data_o = 16'h0000;
assign pipe_rx2_valid_o = 1'b0;
assign pipe_rx2_chanisaligned_o = 1'b0;
assign pipe_rx2_status_o = 3'b000;
assign pipe_rx2_phy_status_o = 1'b0;
assign pipe_rx2_elec_idle_o = 1'b1;
assign pipe_rx2_polarity_o = 1'b0;
assign pipe_tx2_compliance_o = 1'b0;
assign pipe_tx2_char_is_k_o = 2'b00;
assign pipe_tx2_data_o = 16'h0000;
assign pipe_tx2_elec_idle_o = 1'b1;
assign pipe_tx2_powerdown_o = 2'b00;
assign pipe_rx3_char_is_k_o = 2'b00;
assign pipe_rx3_data_o = 16'h0000;
assign pipe_rx3_valid_o = 1'b0;
assign pipe_rx3_chanisaligned_o = 1'b0;
assign pipe_rx3_status_o = 3'b000;
assign pipe_rx3_phy_status_o = 1'b0;
assign pipe_rx3_elec_idle_o = 1'b1;
assign pipe_rx3_polarity_o = 1'b0;
assign pipe_tx3_compliance_o = 1'b0;
assign pipe_tx3_char_is_k_o = 2'b00;
assign pipe_tx3_data_o = 16'h0000;
assign pipe_tx3_elec_idle_o = 1'b1;
assign pipe_tx3_powerdown_o = 2'b00;
end // if !(LINK_CAP_MAX_LINK_WIDTH >= 4)
if (LINK_CAP_MAX_LINK_WIDTH >= 8) begin : pipe_8_lane
pcie_7x_0_core_top_pcie_pipe_lane # (
.PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)
)
pipe_lane_4_i (
.pipe_rx_char_is_k_o(pipe_rx4_char_is_k_o),
.pipe_rx_data_o(pipe_rx4_data_o),
.pipe_rx_valid_o(pipe_rx4_valid_o),
.pipe_rx_chanisaligned_o(pipe_rx4_chanisaligned_o),
.pipe_rx_status_o(pipe_rx4_status_o),
.pipe_rx_phy_status_o(pipe_rx4_phy_status_o),
.pipe_rx_elec_idle_o(pipe_rx4_elec_idle_o),
.pipe_rx_polarity_i(pipe_rx4_polarity_i),
.pipe_tx_compliance_i(pipe_tx4_compliance_i),
.pipe_tx_char_is_k_i(pipe_tx4_char_is_k_i),
.pipe_tx_data_i(pipe_tx4_data_i),
.pipe_tx_elec_idle_i(pipe_tx4_elec_idle_i),
.pipe_tx_powerdown_i(pipe_tx4_powerdown_i),
.pipe_rx_char_is_k_i(pipe_rx4_char_is_k_i),
.pipe_rx_data_i(pipe_rx4_data_i),
.pipe_rx_valid_i(pipe_rx4_valid_i),
.pipe_rx_chanisaligned_i(pipe_rx4_chanisaligned_i),
.pipe_rx_status_i(pipe_rx4_status_i),
.pipe_rx_phy_status_i(pipe_rx4_phy_status_i),
.pipe_rx_elec_idle_i(pipe_rx4_elec_idle_i),
.pipe_rx_polarity_o(pipe_rx4_polarity_o),
.pipe_tx_compliance_o(pipe_tx4_compliance_o),
.pipe_tx_char_is_k_o(pipe_tx4_char_is_k_o),
.pipe_tx_data_o(pipe_tx4_data_o),
.pipe_tx_elec_idle_o(pipe_tx4_elec_idle_o),
.pipe_tx_powerdown_o(pipe_tx4_powerdown_o),
.pipe_clk(pipe_clk),
.rst_n(rst_n)
);
pcie_7x_0_core_top_pcie_pipe_lane # (
.PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)
)
pipe_lane_5_i (
.pipe_rx_char_is_k_o(pipe_rx5_char_is_k_o),
.pipe_rx_data_o(pipe_rx5_data_o),
.pipe_rx_valid_o(pipe_rx5_valid_o),
.pipe_rx_chanisaligned_o(pipe_rx5_chanisaligned_o),
.pipe_rx_status_o(pipe_rx5_status_o),
.pipe_rx_phy_status_o(pipe_rx5_phy_status_o),
.pipe_rx_elec_idle_o(pipe_rx5_elec_idle_o),
.pipe_rx_polarity_i(pipe_rx5_polarity_i),
.pipe_tx_compliance_i(pipe_tx5_compliance_i),
.pipe_tx_char_is_k_i(pipe_tx5_char_is_k_i),
.pipe_tx_data_i(pipe_tx5_data_i),
.pipe_tx_elec_idle_i(pipe_tx5_elec_idle_i),
.pipe_tx_powerdown_i(pipe_tx5_powerdown_i),
.pipe_rx_char_is_k_i(pipe_rx5_char_is_k_i),
.pipe_rx_data_i(pipe_rx5_data_i),
.pipe_rx_valid_i(pipe_rx5_valid_i),
.pipe_rx_chanisaligned_i(pipe_rx5_chanisaligned_i),
.pipe_rx_status_i(pipe_rx5_status_i),
.pipe_rx_phy_status_i(pipe_rx5_phy_status_i),
.pipe_rx_elec_idle_i(pipe_rx5_elec_idle_i),
.pipe_rx_polarity_o(pipe_rx5_polarity_o),
.pipe_tx_compliance_o(pipe_tx5_compliance_o),
.pipe_tx_char_is_k_o(pipe_tx5_char_is_k_o),
.pipe_tx_data_o(pipe_tx5_data_o),
.pipe_tx_elec_idle_o(pipe_tx5_elec_idle_o),
.pipe_tx_powerdown_o(pipe_tx5_powerdown_o),
.pipe_clk(pipe_clk),
.rst_n(rst_n)
);
pcie_7x_0_core_top_pcie_pipe_lane # (
.PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)
)
pipe_lane_6_i (
.pipe_rx_char_is_k_o(pipe_rx6_char_is_k_o),
.pipe_rx_data_o(pipe_rx6_data_o),
.pipe_rx_valid_o(pipe_rx6_valid_o),
.pipe_rx_chanisaligned_o(pipe_rx6_chanisaligned_o),
.pipe_rx_status_o(pipe_rx6_status_o),
.pipe_rx_phy_status_o(pipe_rx6_phy_status_o),
.pipe_rx_elec_idle_o(pipe_rx6_elec_idle_o),
.pipe_rx_polarity_i(pipe_rx6_polarity_i),
.pipe_tx_compliance_i(pipe_tx6_compliance_i),
.pipe_tx_char_is_k_i(pipe_tx6_char_is_k_i),
.pipe_tx_data_i(pipe_tx6_data_i),
.pipe_tx_elec_idle_i(pipe_tx6_elec_idle_i),
.pipe_tx_powerdown_i(pipe_tx6_powerdown_i),
.pipe_rx_char_is_k_i(pipe_rx6_char_is_k_i),
.pipe_rx_data_i(pipe_rx6_data_i),
.pipe_rx_valid_i(pipe_rx6_valid_i),
.pipe_rx_chanisaligned_i(pipe_rx6_chanisaligned_i),
.pipe_rx_status_i(pipe_rx6_status_i),
.pipe_rx_phy_status_i(pipe_rx6_phy_status_i),
.pipe_rx_elec_idle_i(pipe_rx6_elec_idle_i),
.pipe_rx_polarity_o(pipe_rx6_polarity_o),
.pipe_tx_compliance_o(pipe_tx6_compliance_o),
.pipe_tx_char_is_k_o(pipe_tx6_char_is_k_o),
.pipe_tx_data_o(pipe_tx6_data_o),
.pipe_tx_elec_idle_o(pipe_tx6_elec_idle_o),
.pipe_tx_powerdown_o(pipe_tx6_powerdown_o),
.pipe_clk(pipe_clk),
.rst_n(rst_n)
);
pcie_7x_0_core_top_pcie_pipe_lane # (
.PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)
)
pipe_lane_7_i (
.pipe_rx_char_is_k_o(pipe_rx7_char_is_k_o),
.pipe_rx_data_o(pipe_rx7_data_o),
.pipe_rx_valid_o(pipe_rx7_valid_o),
.pipe_rx_chanisaligned_o(pipe_rx7_chanisaligned_o),
.pipe_rx_status_o(pipe_rx7_status_o),
.pipe_rx_phy_status_o(pipe_rx7_phy_status_o),
.pipe_rx_elec_idle_o(pipe_rx7_elec_idle_o),
.pipe_rx_polarity_i(pipe_rx7_polarity_i),
.pipe_tx_compliance_i(pipe_tx7_compliance_i),
.pipe_tx_char_is_k_i(pipe_tx7_char_is_k_i),
.pipe_tx_data_i(pipe_tx7_data_i),
.pipe_tx_elec_idle_i(pipe_tx7_elec_idle_i),
.pipe_tx_powerdown_i(pipe_tx7_powerdown_i),
.pipe_rx_char_is_k_i(pipe_rx7_char_is_k_i),
.pipe_rx_data_i(pipe_rx7_data_i),
.pipe_rx_valid_i(pipe_rx7_valid_i),
.pipe_rx_chanisaligned_i(pipe_rx7_chanisaligned_i),
.pipe_rx_status_i(pipe_rx7_status_i),
.pipe_rx_phy_status_i(pipe_rx7_phy_status_i),
.pipe_rx_elec_idle_i(pipe_rx7_elec_idle_i),
.pipe_rx_polarity_o(pipe_rx7_polarity_o),
.pipe_tx_compliance_o(pipe_tx7_compliance_o),
.pipe_tx_char_is_k_o(pipe_tx7_char_is_k_o),
.pipe_tx_data_o(pipe_tx7_data_o),
.pipe_tx_elec_idle_o(pipe_tx7_elec_idle_o),
.pipe_tx_powerdown_o(pipe_tx7_powerdown_o),
.pipe_clk(pipe_clk),
.rst_n(rst_n)
);
end // if (LINK_CAP_MAX_LINK_WIDTH >= 8)
else
begin
assign pipe_rx4_char_is_k_o = 2'b00;
assign pipe_rx4_data_o = 16'h0000;
assign pipe_rx4_valid_o = 1'b0;
assign pipe_rx4_chanisaligned_o = 1'b0;
assign pipe_rx4_status_o = 3'b000;
assign pipe_rx4_phy_status_o = 1'b0;
assign pipe_rx4_elec_idle_o = 1'b1;
assign pipe_rx4_polarity_o = 1'b0;
assign pipe_tx4_compliance_o = 1'b0;
assign pipe_tx4_char_is_k_o = 2'b00;
assign pipe_tx4_data_o = 16'h0000;
assign pipe_tx4_elec_idle_o = 1'b1;
assign pipe_tx4_powerdown_o = 2'b00;
assign pipe_rx5_char_is_k_o = 2'b00;
assign pipe_rx5_data_o = 16'h0000;
assign pipe_rx5_valid_o = 1'b0;
assign pipe_rx5_chanisaligned_o = 1'b0;
assign pipe_rx5_status_o = 3'b000;
assign pipe_rx5_phy_status_o = 1'b0;
assign pipe_rx5_elec_idle_o = 1'b1;
assign pipe_rx5_polarity_o = 1'b0;
assign pipe_tx5_compliance_o = 1'b0;
assign pipe_tx5_char_is_k_o = 2'b00;
assign pipe_tx5_data_o = 16'h0000;
assign pipe_tx5_elec_idle_o = 1'b1;
assign pipe_tx5_powerdown_o = 2'b00;
assign pipe_rx6_char_is_k_o = 2'b00;
assign pipe_rx6_data_o = 16'h0000;
assign pipe_rx6_valid_o = 1'b0;
assign pipe_rx6_chanisaligned_o = 1'b0;
assign pipe_rx6_status_o = 3'b000;
assign pipe_rx6_phy_status_o = 1'b0;
assign pipe_rx6_elec_idle_o = 1'b1;
assign pipe_rx6_polarity_o = 1'b0;
assign pipe_tx6_compliance_o = 1'b0;
assign pipe_tx6_char_is_k_o = 2'b00;
assign pipe_tx6_data_o = 16'h0000;
assign pipe_tx6_elec_idle_o = 1'b1;
assign pipe_tx6_powerdown_o = 2'b00;
assign pipe_rx7_char_is_k_o = 2'b00;
assign pipe_rx7_data_o = 16'h0000;
assign pipe_rx7_valid_o = 1'b0;
assign pipe_rx7_chanisaligned_o = 1'b0;
assign pipe_rx7_status_o = 3'b000;
assign pipe_rx7_phy_status_o = 1'b0;
assign pipe_rx7_elec_idle_o = 1'b1;
assign pipe_rx7_polarity_o = 1'b0;
assign pipe_tx7_compliance_o = 1'b0;
assign pipe_tx7_char_is_k_o = 2'b00;
assign pipe_tx7_data_o = 16'h0000;
assign pipe_tx7_elec_idle_o = 1'b1;
assign pipe_tx7_powerdown_o = 2'b00;
end // if !(LINK_CAP_MAX_LINK_WIDTH >= 8)
endgenerate
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:44:46 09/24/2013
// Design Name: Data_Parameters
// Module Name: C:/Users/Fabian/Documents/GitHub/taller-diseno-digital/Lab3/laboratorio3/test_data_parameters.v
// Project Name: laboratorio3
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Data_Parameters
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_data_parameters;
// Inputs
reg clock;
reg reset;
reg [3:0] mem_address;
reg write_value_reg_en;
reg [1:0] write_data_selector;
// Outputs
wire [3:0] write_value;
// Instantiate the Unit Under Test (UUT)
Data_Parameters uut (
.clock(clock),
.reset(reset),
.mem_address(mem_address),
.write_value_reg_en(write_value_reg_en),
.write_data_selector(write_data_selector),
.write_value(write_value)
);
initial begin
// Initialize Inputs
clock = 0;
reset = 0;
mem_address = 0;
write_value_reg_en = 0;
write_data_selector = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
|
// VGA_0.v
// This file was auto-generated as part of a SOPC Builder generate operation.
// If you edit it your changes will probably be lost.
`timescale 1 ps / 1 ps
module VGA_0 (
input wire iCLK, // clk.clk
output wire [9:0] VGA_R, // avalon_slave_0_export.export
output wire [9:0] VGA_G, // .export
output wire [9:0] VGA_B, // .export
output wire VGA_HS, // .export
output wire VGA_VS, // .export
output wire VGA_SYNC, // .export
output wire VGA_BLANK, // .export
output wire VGA_CLK, // .export
input wire iCLK_25, // .export
output wire [15:0] oDATA, // avalon_slave_0.readdata
input wire [15:0] iDATA, // .writedata
input wire [18:0] iADDR, // .address
input wire iWR, // .write
input wire iRD, // .read
input wire iCS, // .chipselect
input wire iRST_N // reset_n.reset_n
);
VGA_NIOS_CTRL #(
.RAM_SIZE (307200)
) vga_0 (
.iCLK (iCLK), // clk.clk
.VGA_R (VGA_R), // avalon_slave_0_export.export
.VGA_G (VGA_G), // .export
.VGA_B (VGA_B), // .export
.VGA_HS (VGA_HS), // .export
.VGA_VS (VGA_VS), // .export
.VGA_SYNC (VGA_SYNC), // .export
.VGA_BLANK (VGA_BLANK), // .export
.VGA_CLK (VGA_CLK), // .export
.iCLK_25 (iCLK_25), // .export
.oDATA (oDATA), // avalon_slave_0.readdata
.iDATA (iDATA), // .writedata
.iADDR (iADDR), // .address
.iWR (iWR), // .write
.iRD (iRD), // .read
.iCS (iCS), // .chipselect
.iRST_N (iRST_N) // reset_n.reset_n
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLYGATE4SD3_TB_V
`define SKY130_FD_SC_MS__DLYGATE4SD3_TB_V
/**
* dlygate4sd3: Delay Buffer 4-stage 0.50um length inner stage gates.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__dlygate4sd3.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_ms__dlygate4sd3 dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLYGATE4SD3_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFRTP_1_V
`define SKY130_FD_SC_HD__SDFRTP_1_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog wrapper for sdfrtp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__sdfrtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__sdfrtp_1 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__sdfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__sdfrtp_1 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__sdfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFRTP_1_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Iztok Jeras.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
// parameters for array sizes
localparam WA = 8; // address dimension size
localparam WB = 8; // bit dimension size
localparam NO = 10; // number of access events
// 2D packed arrays
logic [WA-1:0] [WB-1:0] array_bg; // big endian array
/* verilator lint_off LITENDIAN */
logic [0:WA-1] [0:WB-1] array_lt; // little endian array
/* verilator lint_on LITENDIAN */
integer cnt = 0;
// event counter
always @ (posedge clk) begin
cnt <= cnt + 1;
end
// finish report
always @ (posedge clk)
if ((cnt[30:2]==NO) && (cnt[1:0]==2'd0)) begin
$write("*-* All Finished *-*\n");
$finish;
end
// big endian
always @ (posedge clk)
if (cnt[1:0]==2'd0) begin
// initialize to defaaults (all bits to x)
if (cnt[30:2]==0) array_bg <= {WA *WB{1'bx} };
else if (cnt[30:2]==1) array_bg <= {WA{ {WB{1'bx}} }};
else if (cnt[30:2]==2) array_bg <= {WA{ {WB{1'bx}} }};
else if (cnt[30:2]==3) array_bg <= {WA{ {WB{1'bx}} }};
else if (cnt[30:2]==4) array_bg <= {WA{ {WB{1'bx}} }};
else if (cnt[30:2]==5) array_bg <= {WA{ {WB{1'bx}} }};
else if (cnt[30:2]==6) array_bg <= {WA{ {WB{1'bx}} }};
else if (cnt[30:2]==7) array_bg <= {WA{ {WB{1'bx}} }};
else if (cnt[30:2]==8) array_bg <= {WA{ {WB{1'bx}} }};
else if (cnt[30:2]==9) array_bg <= {WA{ {WB{1'bx}} }};
end else if (cnt[1:0]==2'd1) begin
// write value to array
if (cnt[30:2]==0) begin end
else if (cnt[30:2]==1) array_bg = {WA *WB +0{1'b1}};
else if (cnt[30:2]==2) array_bg [WA/2-1:0 ] = {WA/2*WB +0{1'b1}};
else if (cnt[30:2]==3) array_bg [WA -1:WA/2] = {WA/2*WB +0{1'b1}};
else if (cnt[30:2]==4) array_bg [ 0 ] = {1 *WB +0{1'b1}};
else if (cnt[30:2]==5) array_bg [WA -1 ] = {1 *WB +0{1'b1}};
else if (cnt[30:2]==6) array_bg [ 0 ][WB/2-1:0 ] = {1 *WB/2+0{1'b1}};
else if (cnt[30:2]==7) array_bg [WA -1 ][WB -1:WB/2] = {1 *WB/2+0{1'b1}};
else if (cnt[30:2]==8) array_bg [ 0 ][ 0 ] = {1 *1 +0{1'b1}};
else if (cnt[30:2]==9) array_bg [WA -1 ][WB -1 ] = {1 *1 +0{1'b1}};
end else if (cnt[1:0]==2'd2) begin
// check array value
if (cnt[30:2]==0) begin if (array_bg !== 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx) $stop(); end
else if (cnt[30:2]==1) begin if (array_bg !== 64'b1111111111111111111111111111111111111111111111111111111111111111) $stop(); end
else if (cnt[30:2]==2) begin if (array_bg !== 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx11111111111111111111111111111111) $stop(); end
else if (cnt[30:2]==3) begin if (array_bg !== 64'b11111111111111111111111111111111xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx) $stop(); end
else if (cnt[30:2]==4) begin if (array_bg !== 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx11111111) $stop(); end
else if (cnt[30:2]==5) begin if (array_bg !== 64'b11111111xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx) $stop(); end
else if (cnt[30:2]==6) begin if (array_bg !== 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1111) $stop(); end
else if (cnt[30:2]==7) begin if (array_bg !== 64'b1111xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx) $stop(); end
else if (cnt[30:2]==8) begin if (array_bg !== 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1) $stop(); end
else if (cnt[30:2]==9) begin if (array_bg !== 64'b1xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx) $stop(); end
end else if (cnt[1:0]==2'd3) begin
// read value from array (not a very good test for now)
if (cnt[30:2]==0) begin if (array_bg !== {WA *WB {1'bx}}) $stop(); end
else if (cnt[30:2]==1) begin if (array_bg !== {WA *WB +0{1'b1}}) $stop(); end
else if (cnt[30:2]==2) begin if (array_bg [WA/2-1:0 ] !== {WA/2*WB +0{1'b1}}) $stop(); end
else if (cnt[30:2]==3) begin if (array_bg [WA -1:WA/2] !== {WA/2*WB +0{1'b1}}) $stop(); end
else if (cnt[30:2]==4) begin if (array_bg [ 0 ] !== {1 *WB +0{1'b1}}) $stop(); end
else if (cnt[30:2]==5) begin if (array_bg [WA -1 ] !== {1 *WB +0{1'b1}}) $stop(); end
else if (cnt[30:2]==6) begin if (array_bg [ 0 ][WB/2-1:0 ] !== {1 *WB/2+0{1'b1}}) $stop(); end
else if (cnt[30:2]==7) begin if (array_bg [WA -1 ][WB -1:WB/2] !== {1 *WB/2+0{1'b1}}) $stop(); end
else if (cnt[30:2]==8) begin if (array_bg [ 0 ][ 0 ] !== {1 *1 +0{1'b1}}) $stop(); end
else if (cnt[30:2]==9) begin if (array_bg [WA -1 ][WB -1 ] !== {1 *1 +0{1'b1}}) $stop(); end
end
// little endian
always @ (posedge clk)
if (cnt[1:0]==2'd0) begin
// initialize to defaaults (all bits to x)
if (cnt[30:2]==0) array_lt <= {WA *WB{1'bx} };
else if (cnt[30:2]==1) array_lt <= {WA{ {WB{1'bx}} }};
else if (cnt[30:2]==2) array_lt <= {WA{ {WB{1'bx}} }};
else if (cnt[30:2]==3) array_lt <= {WA{ {WB{1'bx}} }};
else if (cnt[30:2]==4) array_lt <= {WA{ {WB{1'bx}} }};
else if (cnt[30:2]==5) array_lt <= {WA{ {WB{1'bx}} }};
else if (cnt[30:2]==6) array_lt <= {WA{ {WB{1'bx}} }};
else if (cnt[30:2]==7) array_lt <= {WA{ {WB{1'bx}} }};
else if (cnt[30:2]==8) array_lt <= {WA{ {WB{1'bx}} }};
else if (cnt[30:2]==9) array_lt <= {WA{ {WB{1'bx}} }};
end else if (cnt[1:0]==2'd1) begin
// write value to array
if (cnt[30:2]==0) begin end
else if (cnt[30:2]==1) array_lt = {WA *WB +0{1'b1}};
else if (cnt[30:2]==2) array_lt [0 :WA/2-1] = {WA/2*WB +0{1'b1}};
else if (cnt[30:2]==3) array_lt [WA/2:WA -1] = {WA/2*WB +0{1'b1}};
else if (cnt[30:2]==4) array_lt [0 ] = {1 *WB +0{1'b1}};
else if (cnt[30:2]==5) array_lt [ WA -1] = {1 *WB +0{1'b1}};
else if (cnt[30:2]==6) array_lt [0 ][0 :WB/2-1] = {1 *WB/2+0{1'b1}};
else if (cnt[30:2]==7) array_lt [ WA -1][WB/2:WB -1] = {1 *WB/2+0{1'b1}};
else if (cnt[30:2]==8) array_lt [0 ][0 ] = {1 *1 +0{1'b1}};
else if (cnt[30:2]==9) array_lt [ WA -1][ WB -1] = {1 *1 +0{1'b1}};
end else if (cnt[1:0]==2'd2) begin
// check array value
if (cnt[30:2]==0) begin if (array_lt !== 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx) $stop(); end
else if (cnt[30:2]==1) begin if (array_lt !== 64'b1111111111111111111111111111111111111111111111111111111111111111) $stop(); end
else if (cnt[30:2]==2) begin if (array_lt !== 64'b11111111111111111111111111111111xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx) $stop(); end
else if (cnt[30:2]==3) begin if (array_lt !== 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx11111111111111111111111111111111) $stop(); end
else if (cnt[30:2]==4) begin if (array_lt !== 64'b11111111xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx) $stop(); end
else if (cnt[30:2]==5) begin if (array_lt !== 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx11111111) $stop(); end
else if (cnt[30:2]==6) begin if (array_lt !== 64'b1111xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx) $stop(); end
else if (cnt[30:2]==7) begin if (array_lt !== 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1111) $stop(); end
else if (cnt[30:2]==8) begin if (array_lt !== 64'b1xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx) $stop(); end
else if (cnt[30:2]==9) begin if (array_lt !== 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1) $stop(); end
end else if (cnt[1:0]==2'd3) begin
// read value from array (not a very good test for now)
if (cnt[30:2]==0) begin if (array_lt !== {WA *WB {1'bx}}) $stop(); end
else if (cnt[30:2]==1) begin if (array_lt !== {WA *WB +0{1'b1}}) $stop(); end
else if (cnt[30:2]==2) begin if (array_lt [0 :WA/2-1] !== {WA/2*WB +0{1'b1}}) $stop(); end
else if (cnt[30:2]==3) begin if (array_lt [WA/2:WA -1] !== {WA/2*WB +0{1'b1}}) $stop(); end
else if (cnt[30:2]==4) begin if (array_lt [0 ] !== {1 *WB +0{1'b1}}) $stop(); end
else if (cnt[30:2]==5) begin if (array_lt [ WA -1] !== {1 *WB +0{1'b1}}) $stop(); end
else if (cnt[30:2]==6) begin if (array_lt [0 ][0 :WB/2-1] !== {1 *WB/2+0{1'b1}}) $stop(); end
else if (cnt[30:2]==7) begin if (array_lt [ WA -1][WB/2:WB -1] !== {1 *WB/2+0{1'b1}}) $stop(); end
else if (cnt[30:2]==8) begin if (array_lt [0 ][0 ] !== {1 *1 +0{1'b1}}) $stop(); end
else if (cnt[30:2]==9) begin if (array_lt [ WA -1][ WB -1] !== {1 *1 +0{1'b1}}) $stop(); end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFXBP_SYMBOL_V
`define SKY130_FD_SC_HD__DFXBP_SYMBOL_V
/**
* dfxbp: Delay flop, complementary outputs.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dfxbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFXBP_SYMBOL_V
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Wed Oct 19 15:08:46 2016
/////////////////////////////////////////////////////////////
module Oper_Start_In_2_W32 ( clk, rst, load_b_i, intAS, intDX, intDY, DMP_o,
DmP_o, zero_flag_o, real_op_o, sign_final_result_o );
input [31:0] intDX;
input [31:0] intDY;
output [30:0] DMP_o;
output [30:0] DmP_o;
input clk, rst, load_b_i, intAS;
output zero_flag_o, real_op_o, sign_final_result_o;
wire MRegister_n63, MRegister_n61, MRegister_n60, MRegister_n59,
MRegister_n58, MRegister_n57, MRegister_n56, MRegister_n55,
MRegister_n54, MRegister_n53, MRegister_n52, MRegister_n51,
MRegister_n50, MRegister_n49, MRegister_n48, MRegister_n47,
MRegister_n46, MRegister_n45, MRegister_n44, MRegister_n43,
MRegister_n42, MRegister_n41, MRegister_n40, MRegister_n39,
MRegister_n38, MRegister_n37, MRegister_n36, MRegister_n35,
MRegister_n34, MRegister_n33, MRegister_n32, MRegister_n31,
MRegister_n30, MRegister_n29, MRegister_n28, MRegister_n27,
MRegister_n26, MRegister_n25, MRegister_n24, MRegister_n23,
MRegister_n22, MRegister_n21, MRegister_n20, MRegister_n19,
MRegister_n18, MRegister_n17, MRegister_n16, MRegister_n15,
MRegister_n14, MRegister_n13, MRegister_n12, MRegister_n11,
MRegister_n10, MRegister_n9, MRegister_n8, MRegister_n7, MRegister_n6,
MRegister_n5, MRegister_n4, MRegister_n3, MRegister_n2, MRegister_n1,
mRegister_n135, mRegister_n134, mRegister_n133, mRegister_n132,
mRegister_n131, mRegister_n130, mRegister_n129, mRegister_n128,
mRegister_n127, mRegister_n126, mRegister_n125, mRegister_n124,
mRegister_n123, mRegister_n122, mRegister_n121, mRegister_n120,
mRegister_n119, mRegister_n118, mRegister_n117, mRegister_n116,
mRegister_n115, mRegister_n114, mRegister_n113, mRegister_n112,
mRegister_n111, mRegister_n110, mRegister_n109, mRegister_n108,
mRegister_n107, mRegister_n106, mRegister_n105, mRegister_n104,
mRegister_n103, mRegister_n102, mRegister_n101, mRegister_n100,
mRegister_n99, mRegister_n98, mRegister_n97, mRegister_n96,
mRegister_n95, mRegister_n94, mRegister_n93, mRegister_n92,
mRegister_n91, mRegister_n90, mRegister_n89, mRegister_n88,
mRegister_n87, mRegister_n86, mRegister_n85, mRegister_n84,
mRegister_n83, mRegister_n82, mRegister_n81, mRegister_n80,
mRegister_n79, mRegister_n78, mRegister_n77, mRegister_n76,
mRegister_n75, mRegister_n74, SignRegister_n5, SignRegister_n4, n152,
n153, n154, n155, n156, n157, n158, n159, n160, n161, n162, n163,
n164, n165, n166, n167, n168, n169, n170, n171, n172, n173, n174,
n175, n176, n177, n178, n179, n180, n181, n182, n183, n184, n185,
n186, n187, n188, n189, n190, n191, n192, n193, n194, n195, n196,
n197, n198, n199, n200, n201, n202, n203, n204, n205, n206, n207,
n208, n209, n210, n211, n212, n213, n214, n215, n216, n217, n218,
n219, n220, n221, n222, n223, n224, n225, n226, n227, n228, n229,
n230, n231, n232, n233, n234, n235, n236, n237, n238, n239, n240,
n241, n242, n243, n244, n245, n246, n247, n248, n249, n250, n251,
n252, n253, n254, n255, n256, n257, n258, n259, n260, n261, n262,
n263, n264, n265, n266, n267, n268, n269, n270, n271, n272, n273,
n274, n275, n276, n277, n278, n279, n280, n281, n282, n283, n284,
n285, n286, n287, n288, n289, n290, n291, n292, n293, n294, n295,
n296, n297, n298, n299, n300, n301, n302, n303, n304, n305, n306,
n307, n308, n309, n310, n311, n312, n313, n314, n315, n316, n317,
n318, n319, n320, n321, n322, n323, n324, n325, n326, n327, n328,
n329, n330, n331, n332, n333;
DFFRXLTS MRegister_Q_reg_0_ ( .D(MRegister_n32), .CK(clk), .RN(n331), .Q(
DMP_o[0]), .QN(MRegister_n1) );
DFFRXLTS MRegister_Q_reg_1_ ( .D(MRegister_n33), .CK(clk), .RN(n331), .Q(
DMP_o[1]), .QN(MRegister_n2) );
DFFRXLTS MRegister_Q_reg_2_ ( .D(MRegister_n34), .CK(clk), .RN(n331), .Q(
DMP_o[2]), .QN(MRegister_n3) );
DFFRXLTS MRegister_Q_reg_3_ ( .D(MRegister_n35), .CK(clk), .RN(n331), .Q(
DMP_o[3]), .QN(MRegister_n4) );
DFFRXLTS MRegister_Q_reg_4_ ( .D(MRegister_n36), .CK(clk), .RN(n333), .Q(
DMP_o[4]), .QN(MRegister_n5) );
DFFRXLTS MRegister_Q_reg_5_ ( .D(MRegister_n37), .CK(clk), .RN(n331), .Q(
DMP_o[5]), .QN(MRegister_n6) );
DFFRXLTS MRegister_Q_reg_7_ ( .D(MRegister_n39), .CK(clk), .RN(n333), .Q(
DMP_o[7]), .QN(MRegister_n8) );
DFFRXLTS MRegister_Q_reg_6_ ( .D(MRegister_n38), .CK(clk), .RN(n331), .Q(
DMP_o[6]), .QN(MRegister_n7) );
DFFRXLTS MRegister_Q_reg_8_ ( .D(MRegister_n40), .CK(clk), .RN(n333), .Q(
DMP_o[8]), .QN(MRegister_n9) );
DFFRXLTS MRegister_Q_reg_9_ ( .D(MRegister_n41), .CK(clk), .RN(n331), .Q(
DMP_o[9]), .QN(MRegister_n10) );
DFFRXLTS MRegister_Q_reg_14_ ( .D(MRegister_n46), .CK(clk), .RN(n330), .Q(
DMP_o[14]), .QN(MRegister_n15) );
DFFRXLTS MRegister_Q_reg_22_ ( .D(MRegister_n54), .CK(clk), .RN(n329), .Q(
DMP_o[22]), .QN(MRegister_n23) );
DFFRXLTS mRegister_Q_reg_6_ ( .D(mRegister_n98), .CK(clk), .RN(n152), .Q(
DmP_o[6]), .QN(mRegister_n129) );
DFFRXLTS mRegister_Q_reg_21_ ( .D(mRegister_n83), .CK(clk), .RN(n152), .Q(
DmP_o[21]), .QN(mRegister_n114) );
DFFRXLTS MRegister_Q_reg_10_ ( .D(MRegister_n42), .CK(clk), .RN(n330), .Q(
DMP_o[10]), .QN(MRegister_n11) );
DFFRXLTS MRegister_Q_reg_11_ ( .D(MRegister_n43), .CK(clk), .RN(n329), .Q(
DMP_o[11]), .QN(MRegister_n12) );
DFFRXLTS MRegister_Q_reg_12_ ( .D(MRegister_n44), .CK(clk), .RN(n330), .Q(
DMP_o[12]), .QN(MRegister_n13) );
DFFRXLTS MRegister_Q_reg_13_ ( .D(MRegister_n45), .CK(clk), .RN(n329), .Q(
DMP_o[13]), .QN(MRegister_n14) );
DFFRXLTS MRegister_Q_reg_15_ ( .D(MRegister_n47), .CK(clk), .RN(n329), .Q(
DMP_o[15]), .QN(MRegister_n16) );
DFFRXLTS MRegister_Q_reg_23_ ( .D(MRegister_n55), .CK(clk), .RN(n331), .Q(
DMP_o[23]), .QN(MRegister_n24) );
DFFRXLTS MRegister_Q_reg_24_ ( .D(MRegister_n56), .CK(clk), .RN(n330), .Q(
DMP_o[24]), .QN(MRegister_n25) );
DFFRXLTS MRegister_Q_reg_25_ ( .D(MRegister_n57), .CK(clk), .RN(n331), .Q(
DMP_o[25]), .QN(MRegister_n26) );
DFFRXLTS MRegister_Q_reg_16_ ( .D(MRegister_n48), .CK(clk), .RN(n329), .Q(
DMP_o[16]), .QN(MRegister_n17) );
DFFRXLTS MRegister_Q_reg_17_ ( .D(MRegister_n49), .CK(clk), .RN(n329), .Q(
DMP_o[17]), .QN(MRegister_n18) );
DFFRXLTS MRegister_Q_reg_18_ ( .D(MRegister_n50), .CK(clk), .RN(n329), .Q(
DMP_o[18]), .QN(MRegister_n19) );
DFFRXLTS MRegister_Q_reg_19_ ( .D(MRegister_n51), .CK(clk), .RN(n329), .Q(
DMP_o[19]), .QN(MRegister_n20) );
DFFRXLTS MRegister_Q_reg_26_ ( .D(MRegister_n58), .CK(clk), .RN(n329), .Q(
DMP_o[26]), .QN(MRegister_n27) );
DFFRXLTS MRegister_Q_reg_27_ ( .D(MRegister_n59), .CK(clk), .RN(n330), .Q(
DMP_o[27]), .QN(MRegister_n28) );
DFFRXLTS MRegister_Q_reg_28_ ( .D(MRegister_n60), .CK(clk), .RN(n330), .Q(
DMP_o[28]), .QN(MRegister_n29) );
DFFRXLTS MRegister_Q_reg_29_ ( .D(MRegister_n61), .CK(clk), .RN(n330), .Q(
DMP_o[29]), .QN(MRegister_n30) );
DFFRXLTS MRegister_Q_reg_20_ ( .D(MRegister_n52), .CK(clk), .RN(n330), .Q(
DMP_o[20]), .QN(MRegister_n21) );
DFFRXLTS MRegister_Q_reg_21_ ( .D(MRegister_n53), .CK(clk), .RN(n330), .Q(
DMP_o[21]), .QN(MRegister_n22) );
DFFRXLTS MRegister_Q_reg_30_ ( .D(MRegister_n63), .CK(clk), .RN(n330), .Q(
DMP_o[30]), .QN(MRegister_n31) );
DFFRXLTS mRegister_Q_reg_23_ ( .D(mRegister_n81), .CK(clk), .RN(n332), .Q(
DmP_o[23]), .QN(mRegister_n112) );
DFFRXLTS mRegister_Q_reg_24_ ( .D(mRegister_n80), .CK(clk), .RN(n332), .Q(
DmP_o[24]), .QN(mRegister_n111) );
DFFRXLTS mRegister_Q_reg_25_ ( .D(mRegister_n79), .CK(clk), .RN(n332), .Q(
DmP_o[25]), .QN(mRegister_n110) );
DFFRXLTS mRegister_Q_reg_26_ ( .D(mRegister_n78), .CK(clk), .RN(n332), .Q(
DmP_o[26]), .QN(mRegister_n109) );
DFFRXLTS mRegister_Q_reg_27_ ( .D(mRegister_n77), .CK(clk), .RN(n332), .Q(
DmP_o[27]), .QN(mRegister_n108) );
DFFRXLTS mRegister_Q_reg_28_ ( .D(mRegister_n76), .CK(clk), .RN(n332), .Q(
DmP_o[28]), .QN(mRegister_n107) );
DFFRXLTS mRegister_Q_reg_29_ ( .D(mRegister_n75), .CK(clk), .RN(n332), .Q(
DmP_o[29]), .QN(mRegister_n106) );
DFFRXLTS mRegister_Q_reg_0_ ( .D(mRegister_n104), .CK(clk), .RN(n333), .Q(
DmP_o[0]), .QN(mRegister_n135) );
DFFRXLTS mRegister_Q_reg_1_ ( .D(mRegister_n103), .CK(clk), .RN(n333), .Q(
DmP_o[1]), .QN(mRegister_n134) );
DFFRXLTS mRegister_Q_reg_2_ ( .D(mRegister_n102), .CK(clk), .RN(n333), .Q(
DmP_o[2]), .QN(mRegister_n133) );
DFFRXLTS mRegister_Q_reg_3_ ( .D(mRegister_n101), .CK(clk), .RN(n333), .Q(
DmP_o[3]), .QN(mRegister_n132) );
DFFRXLTS mRegister_Q_reg_4_ ( .D(mRegister_n100), .CK(clk), .RN(n152), .Q(
DmP_o[4]), .QN(mRegister_n131) );
DFFRXLTS mRegister_Q_reg_5_ ( .D(mRegister_n99), .CK(clk), .RN(n152), .Q(
DmP_o[5]), .QN(mRegister_n130) );
DFFRXLTS mRegister_Q_reg_7_ ( .D(mRegister_n97), .CK(clk), .RN(n152), .Q(
DmP_o[7]), .QN(mRegister_n128) );
DFFRXLTS mRegister_Q_reg_8_ ( .D(mRegister_n96), .CK(clk), .RN(n152), .Q(
DmP_o[8]), .QN(mRegister_n127) );
DFFRXLTS mRegister_Q_reg_9_ ( .D(mRegister_n95), .CK(clk), .RN(n329), .Q(
DmP_o[9]), .QN(mRegister_n126) );
DFFRXLTS mRegister_Q_reg_10_ ( .D(mRegister_n94), .CK(clk), .RN(n328), .Q(
DmP_o[10]), .QN(mRegister_n125) );
DFFRXLTS mRegister_Q_reg_11_ ( .D(mRegister_n93), .CK(clk), .RN(n328), .Q(
DmP_o[11]), .QN(mRegister_n124) );
DFFRXLTS mRegister_Q_reg_12_ ( .D(mRegister_n92), .CK(clk), .RN(n328), .Q(
DmP_o[12]), .QN(mRegister_n123) );
DFFRXLTS mRegister_Q_reg_13_ ( .D(mRegister_n91), .CK(clk), .RN(n328), .Q(
DmP_o[13]), .QN(mRegister_n122) );
DFFRXLTS mRegister_Q_reg_14_ ( .D(mRegister_n90), .CK(clk), .RN(n328), .Q(
DmP_o[14]), .QN(mRegister_n121) );
DFFRXLTS mRegister_Q_reg_15_ ( .D(mRegister_n89), .CK(clk), .RN(n328), .Q(
DmP_o[15]), .QN(mRegister_n120) );
DFFRXLTS mRegister_Q_reg_16_ ( .D(mRegister_n88), .CK(clk), .RN(n328), .Q(
DmP_o[16]), .QN(mRegister_n119) );
DFFRXLTS mRegister_Q_reg_17_ ( .D(mRegister_n87), .CK(clk), .RN(n328), .Q(
DmP_o[17]), .QN(mRegister_n118) );
DFFRXLTS mRegister_Q_reg_18_ ( .D(mRegister_n86), .CK(clk), .RN(n328), .Q(
DmP_o[18]), .QN(mRegister_n117) );
DFFRXLTS mRegister_Q_reg_19_ ( .D(mRegister_n85), .CK(clk), .RN(n333), .Q(
DmP_o[19]), .QN(mRegister_n116) );
DFFRXLTS mRegister_Q_reg_20_ ( .D(mRegister_n84), .CK(clk), .RN(n152), .Q(
DmP_o[20]), .QN(mRegister_n115) );
DFFRXLTS mRegister_Q_reg_22_ ( .D(mRegister_n82), .CK(clk), .RN(n328), .Q(
DmP_o[22]), .QN(mRegister_n113) );
DFFRXLTS mRegister_Q_reg_30_ ( .D(mRegister_n74), .CK(clk), .RN(n332), .Q(
DmP_o[30]), .QN(mRegister_n105) );
DFFRXLTS SignRegister_Q_reg_0_ ( .D(SignRegister_n4), .CK(clk), .RN(n331),
.Q(sign_final_result_o), .QN(SignRegister_n5) );
AOI211XLTS U218 ( .A0(n224), .A1(n207), .B0(n221), .C0(n225), .Y(n208) );
OAI211XLTS U219 ( .A0(n206), .A1(n230), .B0(n205), .C0(n222), .Y(n207) );
AOI211XLTS U220 ( .A0(intDY[5]), .A1(n253), .B0(n175), .C0(n172), .Y(n237)
);
OAI211XLTS U221 ( .A0(intDX[4]), .A1(n248), .B0(n171), .C0(n177), .Y(n172)
);
OAI221XLTS U222 ( .A0(n272), .A1(intDX[24]), .B0(n318), .B1(intDY[25]), .C0(
n160), .Y(n169) );
AOI211XLTS U223 ( .A0(intDY[21]), .A1(n296), .B0(n209), .C0(n159), .Y(n236)
);
OAI211XLTS U224 ( .A0(intDX[20]), .A1(n297), .B0(n158), .C0(n211), .Y(n159)
);
NOR2XLTS U225 ( .A(n281), .B(intDY[9]), .Y(n188) );
NOR2XLTS U226 ( .A(n276), .B(intDY[12]), .Y(n199) );
NOR2XLTS U227 ( .A(intDX[10]), .B(n260), .Y(n194) );
NAND4BXLTS U228 ( .AN(n200), .B(n202), .C(n197), .D(n192), .Y(n182) );
AOI211XLTS U229 ( .A0(n170), .A1(n157), .B0(n168), .C0(n162), .Y(n219) );
XOR2XLTS U230 ( .A(intAS), .B(intDY[31]), .Y(n240) );
NAND4XLTS U231 ( .A(n237), .B(n236), .C(n235), .D(n234), .Y(n291) );
CLKBUFX2TS U232 ( .A(n327), .Y(n282) );
NOR2XLTS U233 ( .A(intDX[11]), .B(n265), .Y(n195) );
AOI222XLTS U234 ( .A0(intDY[7]), .A1(n245), .B0(intDY[7]), .B1(n179), .C0(
n245), .C1(n179), .Y(n180) );
AOI31XLTS U235 ( .A0(intDX[0]), .A1(n229), .A2(n266), .B0(n232), .Y(n174) );
NOR4BXLTS U236 ( .AN(n164), .B(n163), .C(n162), .D(n161), .Y(n165) );
NOR2XLTS U237 ( .A(intDY[27]), .B(n314), .Y(n163) );
NOR2XLTS U238 ( .A(intDY[26]), .B(n316), .Y(n161) );
NOR2XLTS U239 ( .A(intDY[18]), .B(n290), .Y(n225) );
NOR2XLTS U240 ( .A(intDY[17]), .B(n302), .Y(n221) );
NOR2XLTS U241 ( .A(intDX[27]), .B(n315), .Y(n166) );
NOR2XLTS U242 ( .A(intDX[25]), .B(n321), .Y(n154) );
AOI222XLTS U243 ( .A0(intDY[23]), .A1(n283), .B0(intDY[23]), .B1(n213), .C0(
n283), .C1(n213), .Y(n214) );
NOR2XLTS U244 ( .A(intDY[29]), .B(n309), .Y(n162) );
NOR2XLTS U245 ( .A(intDY[28]), .B(n311), .Y(n168) );
NOR2XLTS U246 ( .A(intDX[2]), .B(n246), .Y(n228) );
OAI211XLTS U247 ( .A0(intDX[8]), .A1(n268), .B0(n187), .C0(n190), .Y(n184)
);
NAND4BXLTS U248 ( .AN(n225), .B(n224), .C(n223), .D(n222), .Y(n226) );
AOI211XLTS U249 ( .A0(intDY[0]), .A1(n267), .B0(n221), .C0(n220), .Y(n223)
);
CLKBUFX2TS U250 ( .A(n258), .Y(n287) );
CLKBUFX2TS U251 ( .A(n327), .Y(n258) );
CLKBUFX2TS U252 ( .A(n319), .Y(n278) );
INVX2TS U253 ( .A(n243), .Y(n319) );
NAND2X1TS U254 ( .A(n241), .B(n280), .Y(n327) );
CLKBUFX2TS U255 ( .A(n258), .Y(n322) );
CLKBUFX2TS U256 ( .A(n278), .Y(n274) );
XOR2XLTS U257 ( .A(n240), .B(intDX[31]), .Y(real_op_o) );
OAI211XLTS U258 ( .A0(n325), .A1(SignRegister_n5), .B0(n239), .C0(n238), .Y(
SignRegister_n4) );
NAND3XLTS U259 ( .A(n240), .B(n243), .C(n291), .Y(n238) );
AOI2BB2XLTS U260 ( .B0(intDY[18]), .B1(n243), .A0N(n290), .A1N(n288), .Y(
n242) );
NOR2XLTS U261 ( .A(intDY[8]), .B(n269), .Y(n191) );
AOI211XLTS U262 ( .A0(n191), .A1(n190), .B0(n189), .C0(n188), .Y(n193) );
NOR2XLTS U263 ( .A(intDY[4]), .B(n249), .Y(n178) );
OAI211XLTS U264 ( .A0(n199), .A1(n198), .B0(n197), .C0(n196), .Y(n201) );
AOI31XLTS U265 ( .A0(n203), .A1(n202), .A2(n201), .B0(n200), .Y(n204) );
AOI222XLTS U266 ( .A0(intDX[15]), .A1(n204), .B0(intDX[15]), .B1(n286), .C0(
n204), .C1(n286), .Y(n205) );
NOR2XLTS U267 ( .A(intDY[20]), .B(n298), .Y(n212) );
NOR2XLTS U268 ( .A(n270), .B(intDX[14]), .Y(n200) );
NOR4XLTS U269 ( .A(n194), .B(n184), .C(n183), .D(n182), .Y(n185) );
OAI211XLTS U270 ( .A0(intDY[8]), .A1(n269), .B0(n186), .C0(n185), .Y(n230)
);
NOR4BXLTS U271 ( .AN(n229), .B(n228), .C(n227), .D(n226), .Y(n233) );
NOR2BX1TS U272 ( .AN(n280), .B(n241), .Y(n243) );
OAI211XLTS U273 ( .A0(n219), .A1(n218), .B0(n217), .C0(n216), .Y(n241) );
NOR4BXLTS U274 ( .AN(n170), .B(n169), .C(n168), .D(n167), .Y(n235) );
CLKBUFX2TS U275 ( .A(n278), .Y(n304) );
CLKBUFX2TS U276 ( .A(n282), .Y(n288) );
CLKBUFX2TS U277 ( .A(n258), .Y(n277) );
INVX2TS U278 ( .A(rst), .Y(n152) );
OAI21XLTS U279 ( .A0(n280), .A1(MRegister_n19), .B0(n242), .Y(MRegister_n50)
);
CLKBUFX2TS U280 ( .A(n152), .Y(n332) );
CLKBUFX2TS U281 ( .A(n332), .Y(n328) );
CLKBUFX2TS U282 ( .A(n152), .Y(n333) );
CLKBUFX2TS U283 ( .A(n333), .Y(n331) );
CLKBUFX2TS U284 ( .A(n332), .Y(n329) );
CLKBUFX2TS U285 ( .A(n333), .Y(n330) );
CLKBUFX2TS U286 ( .A(load_b_i), .Y(n325) );
INVX2TS U287 ( .A(intDX[28]), .Y(n311) );
NAND2X1TS U288 ( .A(intDY[28]), .B(n311), .Y(n170) );
INVX2TS U289 ( .A(intDX[27]), .Y(n314) );
INVX2TS U290 ( .A(intDY[27]), .Y(n315) );
INVX2TS U291 ( .A(intDY[26]), .Y(n317) );
INVX2TS U292 ( .A(intDX[26]), .Y(n316) );
NAND2X1TS U293 ( .A(intDY[26]), .B(n316), .Y(n164) );
INVX2TS U294 ( .A(intDX[25]), .Y(n318) );
INVX2TS U295 ( .A(intDY[25]), .Y(n321) );
INVX2TS U296 ( .A(intDY[24]), .Y(n272) );
NAND2X1TS U297 ( .A(intDX[24]), .B(n272), .Y(n153) );
OAI22X1TS U298 ( .A0(intDY[25]), .A1(n318), .B0(n154), .B1(n153), .Y(n155)
);
AOI22X1TS U299 ( .A0(intDX[26]), .A1(n317), .B0(n164), .B1(n155), .Y(n156)
);
OAI22X1TS U300 ( .A0(intDY[27]), .A1(n314), .B0(n166), .B1(n156), .Y(n157)
);
INVX2TS U301 ( .A(intDX[29]), .Y(n309) );
INVX2TS U302 ( .A(intDY[30]), .Y(n308) );
INVX2TS U303 ( .A(intDY[29]), .Y(n310) );
OAI22X1TS U304 ( .A0(intDX[30]), .A1(n308), .B0(intDX[29]), .B1(n310), .Y(
n218) );
NAND2X1TS U305 ( .A(intDX[30]), .B(n308), .Y(n217) );
INVX2TS U306 ( .A(intDX[21]), .Y(n296) );
INVX2TS U307 ( .A(intDX[22]), .Y(n293) );
OAI22X1TS U308 ( .A0(intDY[21]), .A1(n296), .B0(intDY[22]), .B1(n293), .Y(
n209) );
INVX2TS U309 ( .A(intDY[20]), .Y(n297) );
INVX2TS U310 ( .A(intDY[23]), .Y(n284) );
INVX2TS U311 ( .A(intDX[23]), .Y(n283) );
AOI222XLTS U312 ( .A0(intDX[23]), .A1(n284), .B0(intDX[20]), .B1(n297), .C0(
n283), .C1(intDY[23]), .Y(n158) );
NAND2X1TS U313 ( .A(intDY[22]), .B(n293), .Y(n211) );
AOI22X1TS U314 ( .A0(n272), .A1(intDX[24]), .B0(n318), .B1(intDY[25]), .Y(
n160) );
NAND4BBX1TS U315 ( .AN(n218), .BN(n166), .C(n165), .D(n217), .Y(n167) );
INVX2TS U316 ( .A(intDX[16]), .Y(n306) );
INVX2TS U317 ( .A(intDX[17]), .Y(n302) );
AOI22X1TS U318 ( .A0(intDY[16]), .A1(n306), .B0(intDY[17]), .B1(n302), .Y(
n224) );
INVX2TS U319 ( .A(intDX[5]), .Y(n253) );
INVX2TS U320 ( .A(intDX[6]), .Y(n257) );
OAI22X1TS U321 ( .A0(intDY[5]), .A1(n253), .B0(intDY[6]), .B1(n257), .Y(n175) );
INVX2TS U322 ( .A(intDY[4]), .Y(n248) );
INVX2TS U323 ( .A(intDY[7]), .Y(n244) );
INVX2TS U324 ( .A(intDX[7]), .Y(n245) );
AOI222XLTS U325 ( .A0(intDX[7]), .A1(n244), .B0(intDX[4]), .B1(n248), .C0(
n245), .C1(intDY[7]), .Y(n171) );
NAND2X1TS U326 ( .A(intDY[6]), .B(n257), .Y(n177) );
INVX2TS U327 ( .A(intDX[1]), .Y(n255) );
NAND2X1TS U328 ( .A(intDY[1]), .B(n255), .Y(n229) );
INVX2TS U329 ( .A(intDY[0]), .Y(n266) );
INVX2TS U330 ( .A(intDX[2]), .Y(n247) );
OAI22X1TS U331 ( .A0(intDY[1]), .A1(n255), .B0(intDY[2]), .B1(n247), .Y(n232) );
INVX2TS U332 ( .A(intDY[2]), .Y(n246) );
INVX2TS U333 ( .A(intDY[3]), .Y(n250) );
INVX2TS U334 ( .A(intDX[3]), .Y(n251) );
AOI22X1TS U335 ( .A0(intDX[3]), .A1(intDY[3]), .B0(n250), .B1(n251), .Y(n231) );
NAND2X1TS U336 ( .A(intDX[3]), .B(n250), .Y(n173) );
OAI31X1TS U337 ( .A0(n174), .A1(n228), .A2(n231), .B0(n173), .Y(n181) );
INVX2TS U338 ( .A(intDX[4]), .Y(n249) );
NAND2X1TS U339 ( .A(intDY[5]), .B(n253), .Y(n176) );
AOI32X1TS U340 ( .A0(n178), .A1(n177), .A2(n176), .B0(n175), .B1(n177), .Y(
n179) );
AOI21X1TS U341 ( .A0(n237), .A1(n181), .B0(n180), .Y(n206) );
INVX2TS U342 ( .A(intDX[8]), .Y(n269) );
INVX2TS U343 ( .A(intDX[15]), .Y(n285) );
INVX2TS U344 ( .A(intDX[11]), .Y(n263) );
INVX2TS U345 ( .A(intDY[15]), .Y(n286) );
AOI222XLTS U346 ( .A0(intDY[15]), .A1(n285), .B0(intDY[11]), .B1(n263), .C0(
n286), .C1(intDX[15]), .Y(n186) );
INVX2TS U347 ( .A(intDY[10]), .Y(n260) );
INVX2TS U348 ( .A(intDY[8]), .Y(n268) );
NAND2X1TS U349 ( .A(intDX[10]), .B(n260), .Y(n187) );
INVX2TS U350 ( .A(intDX[9]), .Y(n281) );
NAND2X1TS U351 ( .A(intDY[9]), .B(n281), .Y(n190) );
INVX2TS U352 ( .A(intDX[12]), .Y(n276) );
NAND2X1TS U353 ( .A(intDY[12]), .B(n276), .Y(n196) );
INVX2TS U354 ( .A(intDY[14]), .Y(n270) );
NAND2X1TS U355 ( .A(intDX[14]), .B(n270), .Y(n203) );
NAND4BBX1TS U356 ( .AN(n188), .BN(n199), .C(n196), .D(n203), .Y(n183) );
INVX2TS U357 ( .A(intDY[13]), .Y(n326) );
NAND2X1TS U358 ( .A(intDX[13]), .B(n326), .Y(n202) );
INVX2TS U359 ( .A(intDX[13]), .Y(n323) );
NAND2X1TS U360 ( .A(intDY[13]), .B(n323), .Y(n197) );
INVX2TS U361 ( .A(intDY[11]), .Y(n265) );
NAND2X1TS U362 ( .A(intDX[11]), .B(n265), .Y(n192) );
INVX2TS U363 ( .A(n187), .Y(n189) );
OAI31X1TS U364 ( .A0(n195), .A1(n194), .A2(n193), .B0(n192), .Y(n198) );
INVX2TS U365 ( .A(intDY[16]), .Y(n303) );
NAND2X1TS U366 ( .A(intDX[16]), .B(n303), .Y(n222) );
INVX2TS U367 ( .A(intDX[18]), .Y(n290) );
INVX2TS U368 ( .A(intDY[19]), .Y(n299) );
INVX2TS U369 ( .A(intDY[18]), .Y(n289) );
OAI22X1TS U370 ( .A0(intDX[19]), .A1(n299), .B0(intDX[18]), .B1(n289), .Y(
n220) );
INVX2TS U371 ( .A(intDX[19]), .Y(n300) );
OAI22X1TS U372 ( .A0(n208), .A1(n220), .B0(intDY[19]), .B1(n300), .Y(n215)
);
INVX2TS U373 ( .A(intDX[20]), .Y(n298) );
NAND2X1TS U374 ( .A(intDY[21]), .B(n296), .Y(n210) );
AOI32X1TS U375 ( .A0(n212), .A1(n211), .A2(n210), .B0(n209), .B1(n211), .Y(
n213) );
AOI32X1TS U376 ( .A0(n236), .A1(n235), .A2(n215), .B0(n214), .B1(n235), .Y(
n216) );
OAI211XLTS U377 ( .A0(n240), .A1(n241), .B0(n325), .C0(intDX[31]), .Y(n239)
);
CLKBUFX2TS U378 ( .A(load_b_i), .Y(n280) );
INVX2TS U379 ( .A(intDX[0]), .Y(n267) );
OAI22X1TS U380 ( .A0(intDY[0]), .A1(n267), .B0(intDY[19]), .B1(n300), .Y(
n227) );
NOR4BXLTS U381 ( .AN(n233), .B(n232), .C(n231), .D(n230), .Y(n234) );
INVX2TS U382 ( .A(intDY[1]), .Y(n254) );
OAI222X1TS U383 ( .A0(n258), .A1(n254), .B0(n325), .B1(mRegister_n134), .C0(
n278), .C1(n255), .Y(mRegister_n103) );
OAI222X1TS U384 ( .A0(n258), .A1(n246), .B0(n325), .B1(mRegister_n133), .C0(
n278), .C1(n247), .Y(mRegister_n102) );
OAI222X1TS U385 ( .A0(n258), .A1(n250), .B0(n325), .B1(mRegister_n132), .C0(
n278), .C1(n251), .Y(mRegister_n101) );
OAI222X1TS U386 ( .A0(n258), .A1(n248), .B0(n325), .B1(mRegister_n131), .C0(
n278), .C1(n249), .Y(mRegister_n100) );
INVX2TS U387 ( .A(intDY[5]), .Y(n252) );
CLKBUFX2TS U388 ( .A(load_b_i), .Y(n262) );
OAI222X1TS U389 ( .A0(n258), .A1(n252), .B0(n262), .B1(mRegister_n130), .C0(
n278), .C1(n253), .Y(mRegister_n99) );
INVX2TS U390 ( .A(intDY[6]), .Y(n256) );
OAI222X1TS U391 ( .A0(n258), .A1(n256), .B0(n262), .B1(mRegister_n129), .C0(
n278), .C1(n257), .Y(mRegister_n98) );
OAI222X1TS U392 ( .A0(n258), .A1(n266), .B0(n325), .B1(mRegister_n135), .C0(
n278), .C1(n267), .Y(mRegister_n104) );
CLKBUFX2TS U393 ( .A(n319), .Y(n261) );
OAI222X1TS U394 ( .A0(n288), .A1(n244), .B0(n262), .B1(mRegister_n128), .C0(
n261), .C1(n245), .Y(mRegister_n97) );
CLKBUFX2TS U395 ( .A(load_b_i), .Y(n312) );
CLKBUFX2TS U396 ( .A(n319), .Y(n264) );
OAI222X1TS U397 ( .A0(n277), .A1(n245), .B0(n312), .B1(MRegister_n8), .C0(
n264), .C1(n244), .Y(MRegister_n39) );
OAI222X1TS U398 ( .A0(n277), .A1(n247), .B0(n312), .B1(MRegister_n3), .C0(
n264), .C1(n246), .Y(MRegister_n34) );
OAI222X1TS U399 ( .A0(n277), .A1(n249), .B0(n312), .B1(MRegister_n5), .C0(
n264), .C1(n248), .Y(MRegister_n36) );
OAI222X1TS U400 ( .A0(n277), .A1(n251), .B0(n312), .B1(MRegister_n4), .C0(
n264), .C1(n250), .Y(MRegister_n35) );
OAI222X1TS U401 ( .A0(n277), .A1(n253), .B0(n312), .B1(MRegister_n6), .C0(
n264), .C1(n252), .Y(MRegister_n37) );
OAI222X1TS U402 ( .A0(n322), .A1(n255), .B0(n312), .B1(MRegister_n2), .C0(
n264), .C1(n254), .Y(MRegister_n33) );
OAI222X1TS U403 ( .A0(n277), .A1(n257), .B0(n312), .B1(MRegister_n7), .C0(
n264), .C1(n256), .Y(MRegister_n38) );
INVX2TS U404 ( .A(intDX[14]), .Y(n271) );
OAI222X1TS U405 ( .A0(n287), .A1(n270), .B0(n262), .B1(mRegister_n121), .C0(
n261), .C1(n271), .Y(mRegister_n90) );
CLKBUFX2TS U406 ( .A(load_b_i), .Y(n320) );
OAI222X1TS U407 ( .A0(n287), .A1(n297), .B0(n320), .B1(mRegister_n115), .C0(
n261), .C1(n298), .Y(mRegister_n84) );
INVX2TS U408 ( .A(intDX[24]), .Y(n273) );
OAI222X1TS U409 ( .A0(n322), .A1(n272), .B0(n320), .B1(mRegister_n111), .C0(
n319), .C1(n273), .Y(mRegister_n80) );
OAI222X1TS U410 ( .A0(n287), .A1(n268), .B0(n262), .B1(mRegister_n127), .C0(
n261), .C1(n269), .Y(mRegister_n96) );
CLKBUFX2TS U411 ( .A(load_b_i), .Y(n305) );
OAI222X1TS U412 ( .A0(n277), .A1(n263), .B0(n305), .B1(MRegister_n12), .C0(
n264), .C1(n265), .Y(MRegister_n43) );
INVX2TS U413 ( .A(intDX[10]), .Y(n259) );
OAI222X1TS U414 ( .A0(n277), .A1(n259), .B0(n305), .B1(MRegister_n11), .C0(
n264), .C1(n260), .Y(MRegister_n42) );
OAI222X1TS U415 ( .A0(n287), .A1(n303), .B0(n262), .B1(mRegister_n119), .C0(
n261), .C1(n306), .Y(mRegister_n88) );
INVX2TS U416 ( .A(intDY[12]), .Y(n275) );
OAI222X1TS U417 ( .A0(n287), .A1(n275), .B0(n262), .B1(mRegister_n123), .C0(
n261), .C1(n276), .Y(mRegister_n92) );
OAI222X1TS U418 ( .A0(n287), .A1(n299), .B0(n320), .B1(mRegister_n116), .C0(
n261), .C1(n300), .Y(mRegister_n85) );
OAI222X1TS U419 ( .A0(n287), .A1(n260), .B0(n262), .B1(mRegister_n125), .C0(
n261), .C1(n259), .Y(mRegister_n94) );
INVX2TS U420 ( .A(intDY[17]), .Y(n301) );
OAI222X1TS U421 ( .A0(n287), .A1(n301), .B0(n262), .B1(mRegister_n118), .C0(
n261), .C1(n302), .Y(mRegister_n87) );
INVX2TS U422 ( .A(intDY[9]), .Y(n279) );
OAI222X1TS U423 ( .A0(n287), .A1(n279), .B0(n262), .B1(mRegister_n126), .C0(
n261), .C1(n281), .Y(mRegister_n95) );
OAI222X1TS U424 ( .A0(n277), .A1(n265), .B0(n325), .B1(mRegister_n124), .C0(
n264), .C1(n263), .Y(mRegister_n93) );
OAI222X1TS U425 ( .A0(n282), .A1(n267), .B0(n280), .B1(MRegister_n1), .C0(
n274), .C1(n266), .Y(MRegister_n32) );
OAI222X1TS U426 ( .A0(n288), .A1(n269), .B0(n280), .B1(MRegister_n9), .C0(
n274), .C1(n268), .Y(MRegister_n40) );
OAI222X1TS U427 ( .A0(n288), .A1(n271), .B0(n305), .B1(MRegister_n15), .C0(
n304), .C1(n270), .Y(MRegister_n46) );
CLKBUFX2TS U428 ( .A(load_b_i), .Y(n295) );
INVX2TS U429 ( .A(intDY[28]), .Y(n313) );
OAI222X1TS U430 ( .A0(n282), .A1(n311), .B0(n295), .B1(MRegister_n29), .C0(
n274), .C1(n313), .Y(MRegister_n60) );
OAI222X1TS U431 ( .A0(n282), .A1(n314), .B0(n295), .B1(MRegister_n28), .C0(
n274), .C1(n315), .Y(MRegister_n59) );
OAI222X1TS U432 ( .A0(n288), .A1(n309), .B0(n295), .B1(MRegister_n30), .C0(
n274), .C1(n310), .Y(MRegister_n61) );
OAI222X1TS U433 ( .A0(n282), .A1(n283), .B0(n295), .B1(MRegister_n24), .C0(
n274), .C1(n284), .Y(MRegister_n55) );
INVX2TS U434 ( .A(intDX[30]), .Y(n307) );
OAI222X1TS U435 ( .A0(n282), .A1(n307), .B0(n295), .B1(MRegister_n31), .C0(
n274), .C1(n308), .Y(MRegister_n63) );
OAI222X1TS U436 ( .A0(n282), .A1(n318), .B0(n295), .B1(MRegister_n26), .C0(
n274), .C1(n321), .Y(MRegister_n57) );
OAI222X1TS U437 ( .A0(n282), .A1(n273), .B0(n295), .B1(MRegister_n25), .C0(
n274), .C1(n272), .Y(MRegister_n56) );
OAI222X1TS U438 ( .A0(n282), .A1(n316), .B0(n295), .B1(MRegister_n27), .C0(
n274), .C1(n317), .Y(MRegister_n58) );
OAI222X1TS U439 ( .A0(n288), .A1(n285), .B0(n305), .B1(MRegister_n16), .C0(
n304), .C1(n286), .Y(MRegister_n47) );
OAI222X1TS U440 ( .A0(n277), .A1(n276), .B0(n305), .B1(MRegister_n13), .C0(
n304), .C1(n275), .Y(MRegister_n44) );
OAI222X1TS U441 ( .A0(n288), .A1(n323), .B0(n305), .B1(MRegister_n14), .C0(
n304), .C1(n326), .Y(MRegister_n45) );
CLKBUFX2TS U442 ( .A(n278), .Y(n324) );
OAI222X1TS U443 ( .A0(n282), .A1(n281), .B0(n280), .B1(MRegister_n10), .C0(
n324), .C1(n279), .Y(MRegister_n41) );
OAI222X1TS U444 ( .A0(n322), .A1(n284), .B0(n320), .B1(mRegister_n112), .C0(
n324), .C1(n283), .Y(mRegister_n81) );
OAI222X1TS U445 ( .A0(n288), .A1(n286), .B0(n325), .B1(mRegister_n120), .C0(
n324), .C1(n285), .Y(mRegister_n89) );
INVX2TS U446 ( .A(intDY[21]), .Y(n294) );
OAI222X1TS U447 ( .A0(n287), .A1(n294), .B0(n320), .B1(mRegister_n114), .C0(
n324), .C1(n296), .Y(mRegister_n83) );
INVX2TS U448 ( .A(intDY[22]), .Y(n292) );
OAI222X1TS U449 ( .A0(n322), .A1(n292), .B0(n320), .B1(mRegister_n113), .C0(
n324), .C1(n293), .Y(mRegister_n82) );
OAI222X1TS U450 ( .A0(n290), .A1(n324), .B0(n320), .B1(mRegister_n117), .C0(
n289), .C1(n288), .Y(mRegister_n86) );
NOR2BX1TS U451 ( .AN(real_op_o), .B(n291), .Y(zero_flag_o) );
OAI222X1TS U452 ( .A0(n327), .A1(n293), .B0(n295), .B1(MRegister_n23), .C0(
n304), .C1(n292), .Y(MRegister_n54) );
OAI222X1TS U453 ( .A0(n327), .A1(n296), .B0(n295), .B1(MRegister_n22), .C0(
n304), .C1(n294), .Y(MRegister_n53) );
OAI222X1TS U454 ( .A0(n327), .A1(n298), .B0(n305), .B1(MRegister_n21), .C0(
n304), .C1(n297), .Y(MRegister_n52) );
OAI222X1TS U455 ( .A0(n327), .A1(n300), .B0(n305), .B1(MRegister_n20), .C0(
n304), .C1(n299), .Y(MRegister_n51) );
OAI222X1TS U456 ( .A0(n327), .A1(n302), .B0(n305), .B1(MRegister_n18), .C0(
n304), .C1(n301), .Y(MRegister_n49) );
OAI222X1TS U457 ( .A0(n327), .A1(n306), .B0(n305), .B1(MRegister_n17), .C0(
n304), .C1(n303), .Y(MRegister_n48) );
OAI222X1TS U458 ( .A0(n322), .A1(n308), .B0(n312), .B1(mRegister_n105), .C0(
n319), .C1(n307), .Y(mRegister_n74) );
OAI222X1TS U459 ( .A0(n322), .A1(n310), .B0(n312), .B1(mRegister_n106), .C0(
n319), .C1(n309), .Y(mRegister_n75) );
OAI222X1TS U460 ( .A0(n322), .A1(n313), .B0(n312), .B1(mRegister_n107), .C0(
n319), .C1(n311), .Y(mRegister_n76) );
OAI222X1TS U461 ( .A0(n322), .A1(n315), .B0(n320), .B1(mRegister_n108), .C0(
n319), .C1(n314), .Y(mRegister_n77) );
OAI222X1TS U462 ( .A0(n322), .A1(n317), .B0(n320), .B1(mRegister_n109), .C0(
n319), .C1(n316), .Y(mRegister_n78) );
OAI222X1TS U463 ( .A0(n322), .A1(n321), .B0(n320), .B1(mRegister_n110), .C0(
n319), .C1(n318), .Y(mRegister_n79) );
OAI222X1TS U464 ( .A0(n327), .A1(n326), .B0(n325), .B1(mRegister_n122), .C0(
n324), .C1(n323), .Y(mRegister_n91) );
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:23:50 03/06/2017
// Design Name: DNlatch_NOR
// Module Name: D:/Projects/XilinxISE/HW1/Homework1/testDNlatch_NOR.v
// Project Name: Homework1
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: DNlatch_NOR
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module testDNlatch_NOR;
// Inputs
reg En;
reg D;
// Outputs
wire Q;
wire not_Q;
// Instantiate the DESIGN Under Test (DUT)
DNlatch_NOR dut (
.En(En),
.D(D),
.Q(Q),
.not_Q(not_Q)
);
initial begin
// Initialize Inputs
En = 1;
D = 0;
// Wait 100 ns for global reset to finish
#50;
En = 0;
D = 0;
#50;
En = 0;
D = 1;
#50;
En = 0;
D = 0;
#50;
En = 1;
D = 0;
#50;
En = 1;
D = 1;
#50;
En = 0;
D = 1;
#50;
En = 1;
D = 0;
#50;
En = 1;
D = 1;
// Add stimulus here
end
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Write Channel for ATC
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// w_atc
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
module processing_system7_v5_5_w_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_DATA_WIDTH = 64,
// Width of all DATA signals on SI and MI side of checker.
// Range: 64.
parameter integer C_AXI_WUSER_WIDTH = 1
// Width of AWUSER signals.
// Range: >= 1.
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface (In)
input wire cmd_w_valid,
input wire cmd_w_check,
input wire [C_AXI_ID_WIDTH-1:0] cmd_w_id,
output wire cmd_w_ready,
// Command Interface (Out)
output wire cmd_b_push,
output wire cmd_b_error,
output reg [C_AXI_ID_WIDTH-1:0] cmd_b_id,
input wire cmd_b_full,
// Slave Interface Write Port
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID,
input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input wire S_AXI_WLAST,
input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
// Master Interface Write Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID,
output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire M_AXI_WLAST,
output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY
);
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Detecttion.
wire any_strb_deasserted;
wire incoming_strb_issue;
reg first_word;
reg strb_issue;
// Data flow.
wire data_pop;
wire cmd_b_push_blocked;
reg cmd_b_push_i;
/////////////////////////////////////////////////////////////////////////////
// Detect error:
//
// Detect and accumulate error when a transaction shall be scanned for
// potential issues.
// Accumulation of error is restarted for each ne transaction.
//
/////////////////////////////////////////////////////////////////////////////
// Check stobe information
assign any_strb_deasserted = ( S_AXI_WSTRB != {C_AXI_DATA_WIDTH/8{1'b1}} );
assign incoming_strb_issue = cmd_w_valid & S_AXI_WVALID & cmd_w_check & any_strb_deasserted;
// Keep track of first word in a transaction.
always @ (posedge ACLK) begin
if (ARESET) begin
first_word <= 1'b1;
end else if ( data_pop ) begin
first_word <= S_AXI_WLAST;
end
end
// Keep track of error status.
always @ (posedge ACLK) begin
if (ARESET) begin
strb_issue <= 1'b0;
cmd_b_id <= {C_AXI_ID_WIDTH{1'b0}};
end else if ( data_pop ) begin
if ( first_word ) begin
strb_issue <= incoming_strb_issue;
end else begin
strb_issue <= incoming_strb_issue | strb_issue;
end
cmd_b_id <= cmd_w_id;
end
end
assign cmd_b_error = strb_issue;
/////////////////////////////////////////////////////////////////////////////
// Control command queue to B:
//
// Push command to B queue when all data for the transaction has flowed
// through.
// Delay pipelined command until there is room in the Queue.
//
/////////////////////////////////////////////////////////////////////////////
// Detect when data is popped.
assign data_pop = S_AXI_WVALID & M_AXI_WREADY & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked;
// Push command when last word in transfered (pipelined).
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_b_push_i <= 1'b0;
end else begin
cmd_b_push_i <= ( S_AXI_WLAST & data_pop ) | cmd_b_push_blocked;
end
end
// Detect if pipelined push is blocked.
assign cmd_b_push_blocked = cmd_b_push_i & cmd_b_full;
// Assign output.
assign cmd_b_push = cmd_b_push_i & ~cmd_b_full;
/////////////////////////////////////////////////////////////////////////////
// Transaction Throttling:
//
// Stall commands if FIFO is full or there is no valid command information
// from AW.
//
/////////////////////////////////////////////////////////////////////////////
// Propagate masked valid.
assign M_AXI_WVALID = S_AXI_WVALID & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked;
// Return ready with push back.
assign S_AXI_WREADY = M_AXI_WREADY & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked;
// End of burst.
assign cmd_w_ready = S_AXI_WVALID & M_AXI_WREADY & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked & S_AXI_WLAST;
/////////////////////////////////////////////////////////////////////////////
// Write propagation:
//
// All information is simply forwarded on from the SI- to MI-Side untouched.
//
/////////////////////////////////////////////////////////////////////////////
// 1:1 mapping.
assign M_AXI_WID = S_AXI_WID;
assign M_AXI_WDATA = S_AXI_WDATA;
assign M_AXI_WSTRB = S_AXI_WSTRB;
assign M_AXI_WLAST = S_AXI_WLAST;
assign M_AXI_WUSER = S_AXI_WUSER;
endmodule
|
`timescale 1 ns / 1 ps
module axis_interpolator #
(
parameter integer AXIS_TDATA_WIDTH = 32,
parameter integer CNTR_WIDTH = 32
)
(
// System signals
input wire aclk,
input wire aresetn,
input wire [CNTR_WIDTH-1:0] cfg_data,
// Slave side
output wire s_axis_tready,
input wire [AXIS_TDATA_WIDTH-1:0] s_axis_tdata,
input wire s_axis_tvalid,
// Master side
input wire m_axis_tready,
output wire [AXIS_TDATA_WIDTH-1:0] m_axis_tdata,
output wire m_axis_tvalid
);
reg [AXIS_TDATA_WIDTH-1:0] int_tdata_reg, int_tdata_next;
reg [CNTR_WIDTH-1:0] int_cntr_reg, int_cntr_next;
reg int_tvalid_reg, int_tvalid_next;
reg int_tready_reg, int_tready_next;
always @(posedge aclk)
begin
if(~aresetn)
begin
int_tdata_reg <= {(AXIS_TDATA_WIDTH){1'b0}};
int_tvalid_reg <= 1'b0;
int_tready_reg <= 1'b0;
int_cntr_reg <= {(CNTR_WIDTH){1'b0}};
end
else
begin
int_tdata_reg <= int_tdata_next;
int_tvalid_reg <= int_tvalid_next;
int_tready_reg <= int_tready_next;
int_cntr_reg <= int_cntr_next;
end
end
always @*
begin
int_tdata_next = int_tdata_reg;
int_tvalid_next = int_tvalid_reg;
int_tready_next = int_tready_reg;
int_cntr_next = int_cntr_reg;
if(s_axis_tvalid & ~int_tvalid_reg)
begin
int_tdata_next = s_axis_tdata;
int_tvalid_next = 1'b1;
int_tready_next = 1'b1;
end
if(m_axis_tready & int_tvalid_reg)
begin
if(int_cntr_reg < cfg_data)
begin
int_cntr_next = int_cntr_reg + 1'b1;
end
else
begin
int_cntr_next = {(CNTR_WIDTH){1'b0}};
int_tdata_next = s_axis_tdata;
int_tvalid_next = s_axis_tvalid;
int_tready_next = s_axis_tvalid;
end
end
if(s_axis_tvalid & int_tready_reg)
begin
int_tready_next = 1'b0;
end
end
assign s_axis_tready = int_tready_reg;
assign m_axis_tdata = int_tdata_reg;
assign m_axis_tvalid = int_tvalid_reg;
endmodule
|
module manage_rx(
clk,
reset_n,
////crc_check module interface///
pkt_wrreq,
pkt,
pkt_usedw,
valid_wrreq,
valid,
////pkt insert module interface ////
datapath_pkt_wrreq,
datapath_pkt,
datapath_pkt_usedw,
datapath_valid_wrreq,
datapath_valid,
//////command parse module interface/////////
command_data, //command [34:32]001:��ʾ���ݵ�һ�� 011:��ʾ�����м��� 010:��ʾ��������һ�� 111:��ʾ����ͷβͬ�� [31:0]:����
command_wr,
command_fifo_full,
sequence_d, //[15:0]:�������кţ�[16]:������Ч��־ 1��������Ч 0��������Ч �趪��
sequence_wr,
sequence_fifo_full,
PROXY_MAC,
PROXY_IP,
FPGA_MAC,
FPGA_IP,
proxy_addr_valid
);
input clk;
input reset_n;
////crc_check module interface///
input pkt_wrreq;
input[138:0] pkt;
output [7:0] pkt_usedw;
input valid_wrreq;
input valid;
////pkt insert module interface ////
output datapath_pkt_wrreq;
output[138:0] datapath_pkt;
input [7:0] datapath_pkt_usedw;
output datapath_valid_wrreq;
output datapath_valid;
//////command parse module interface/////////
output [34:0] command_data; //command [34:32]001:��ʾ���ݵ�һ�� 011:��ʾ�����м��� 010:��ʾ��������һ�� 111:��ʾ����ͷβͬ�� [31:0]:����
output command_wr;
input command_fifo_full;
output [16:0] sequence_d; //[15:0]:�������кţ�[16]:������Ч��־ 1��������Ч 0��������Ч �趪��
output sequence_wr;
input sequence_fifo_full;
output [47:0] PROXY_MAC;
output [31:0] PROXY_IP;
output proxy_addr_valid;
input [47:0] FPGA_MAC;
input [31:0] FPGA_IP;
reg datapath_pkt_wrreq;
reg[138:0] datapath_pkt;
reg datapath_valid_wrreq;
reg datapath_valid;
//////command parse module interface/////////
reg [34:0] command_data; //command [34:32]001:��ʾ���ݵ�һ�� 011:��ʾ�����м��� 010:��ʾ��������һ�� 111:��ʾ����ͷβͬ�� [31:0]:����
reg command_wr;
reg [16:0] sequence_d; //[15:0]:�������кţ�[16]:������Ч��־ 1��������Ч 0��������Ч �趪��
reg sequence_wr;
reg [47:0] PROXY_MAC;
reg [31:0] PROXY_IP;
reg proxy_addr_valid;
reg [47:0] S_MAC;//?MAC??
reg [31:0] S_IP; //?IP??
reg [47:0] D_MAC;//add by bhf in 2014.5.24
reg [7:0] protocol;//add by bhf in 2014.5.24
reg [138:0] first_pkt;//add by bhf in 2014.5.24
reg [138:0] second_pkt;//add by bhf in 2014.5.24
reg [138:0] third_pkt;//add by bhf in 2014.5.24
reg [15:0]packet_length;//coammand length
reg [15:0]dip_h16;
reg [138:0]pkt_reg;
reg fifo_wr_permit;
reg empty;
reg fifo_valid;
reg [3:0]state;
parameter idle_s = 4'h0,
command_smac_s = 4'h1,
command_type_s = 4'h2,
command_dip_s = 4'h3,
command0_s = 4'h4,
command1_s = 4'h5,
command2_s = 4'h6,
command3_s = 4'h7,
command4_s = 4'h8,
wr_datapath_s = 4'h9,
wait_s = 4'ha,
discard_s = 4'hb,
wr_fpkt_s = 4'hc,//add by bhf in 2014.5.24
wr_spkt_s = 4'hd,//add by bhf in 2014.5.24
wr_tpkt_s = 4'he;//add by bhf in 2014.5.24
always@(posedge clk or negedge reset_n)
begin
if(~reset_n)begin
datapath_pkt_wrreq <= 1'b0;
pkt_rdreq <= 1'b0;
valid_rdreq <= 1'b0;
empty <= 1'b0;
fifo_valid <= 1'b0;
datapath_valid_wrreq <= 1'b0;
command_wr <= 1'b0;
sequence_wr <= 1'b0;
proxy_addr_valid <= 1'b0;
state <= idle_s;
end
else begin
fifo_wr_permit <= ~(command_fifo_full | sequence_fifo_full);// 1:permit
empty <= valid_empty;
fifo_valid <= 1'b0;
case(state)
idle_s:begin
datapath_pkt_wrreq <= 1'b0;
datapath_valid_wrreq <= 1'b0;
command_wr <= 1'b0;
sequence_wr <= 1'b0;
if(valid_empty==1'b0)begin
if(valid_q==1'b0) begin//invalid pkt
pkt_rdreq<=1'b1;
valid_rdreq<=1'b1;
state <= discard_s;
end
else begin
if(fifo_wr_permit == 1'b1)begin
pkt_rdreq <=1'b1;
valid_rdreq <=1'b1;
state <= command_smac_s;
end
else begin//command fifo afull
pkt_rdreq<=1'b1;
valid_rdreq<=1'b1;
state <= discard_s;
end
end
end
else begin
state <= idle_s;
end
end
command_smac_s:begin
pkt_rdreq<=1'b1;
valid_rdreq <=1'b0;
first_pkt <= pkt_q;//add by bhf in 2014.5.24
D_MAC <= pkt_q[127:80];//add by bhf in 2014.5.24
S_MAC <= pkt_q[79:32];
state <= command_type_s;
end
command_type_s:begin
packet_length <= pkt_q[127:112] - 16'd26;
S_IP <= pkt_q[47:16];
dip_h16 <= pkt_q[15:0];
second_pkt <= pkt_q;//add by bhf in 2014.5.24
protocol <= pkt_q[71:64];//add by bhf in 2014.5.24
pkt_rdreq<=1'b1;
state <= command_dip_s;
end
command_dip_s:begin
pkt_rdreq<=1'b0;
third_pkt <= pkt_q;//add by bhf in 2014.5.24
pkt_reg <= pkt_q;
if(({dip_h16,pkt_q[127:112]}== FPGA_IP) && (D_MAC == FPGA_MAC) && (protocol == 8'd253))//NMAC okt,dest mac and ip is NetMagic
begin
sequence_d[15:0] <= pkt_q[95:80];
command_data[31:0] <= pkt_q[63:32];
command_wr <= 1'b1;
if(pkt_q[63:56]==8'h01)begin//establish
command_data[34:32] <= 3'b100;
PROXY_MAC <= S_MAC;
PROXY_IP <= S_IP;
proxy_addr_valid <= 1'b1;
sequence_d[16] <= 1'b1;
sequence_wr <= 1'b1;
if(pkt_q[138:136]==3'b110) begin
state<=wait_s;
end
else begin
pkt_rdreq<=1'b1;
state <= discard_s;
end
end
else if ((pkt_q[63:56]==8'h03) || (pkt_q[63:56]==8'h04)) begin//read or write
if(packet_length <= 16'h4)begin//only one cycle command
command_data[34:32] <= 3'b100;
command_wr <= 1'b1;
sequence_d[16] <= 1'b1; //????
sequence_wr <= 1'b1;
if(pkt_q[138:136]==3'b110) begin
state<=wait_s;
end
else begin
pkt_rdreq<=1'b1;
state <= discard_s;
end
end
else begin
command_data[34:32] <= 3'b001;
command_wr <= 1'b1;
sequence_wr <= 1'b0;
packet_length <= packet_length - 4'h4;
state <= command0_s;
end
end
else begin//other nmac pkt is to data path
state <= wr_fpkt_s;
end
end
else begin
state <= wr_fpkt_s;
end
end
wr_fpkt_s:begin
if(datapath_pkt_usedw <= 8'd161)begin
datapath_pkt_wrreq <= 1'b1;
datapath_pkt <= first_pkt;
state <= wr_spkt_s;
end
else begin
pkt_rdreq<=1'b1;
state <= discard_s;
end
end
wr_spkt_s:begin
datapath_pkt_wrreq <= 1'b1;
datapath_pkt <= second_pkt;
state <= wr_tpkt_s;
end
wr_tpkt_s:begin
datapath_pkt_wrreq <= 1'b1;
datapath_pkt <= third_pkt;
pkt_rdreq<=1'b1;
state <= wr_datapath_s;
end
command0_s:begin
if(packet_length <= 16'h4)begin
command_data[34:32] <= 3'b010;
command_data[31:0] <= pkt_reg[31:0];
command_wr <= 1'b1;
sequence_d[16] <= 1'b1;
sequence_wr <= 1'b1;
if(pkt_reg[138:136]==3'b110) begin
state<=wait_s;
end
else begin
pkt_rdreq<=1'b1;
state <= discard_s;
end
end
else begin
command_data[34:32] <= 3'b011;
command_data[31:0] <= pkt_reg[31:0];
command_wr <= 1'b1;
packet_length <= packet_length - 4'h4;
pkt_rdreq<=1'b1;
state <= command1_s;
end
end
command1_s:begin
pkt_rdreq<=1'b0;
pkt_reg <= pkt_q;
if(packet_length <= 16'h4)begin
command_data[34:32] <= 3'b010;
command_data[31:0] <= pkt_q[127:96];
command_wr <= 1'b1;
sequence_d[16] <= 1'b1;
sequence_wr <= 1'b1;
if(pkt_q[138:136]==3'b110) begin
state<=wait_s;
end
else begin
pkt_rdreq<=1'b1;
state <= discard_s;
end
end
else begin
command_data[34:32] <= 3'b011;
command_data[31:0] <= pkt_q[127:96];
command_wr <= 1'b1;
packet_length <= packet_length - 4'h4;
state <= command2_s;
end
end
command2_s:begin
if(packet_length <= 16'h4)begin
command_data[34:32] <= 3'b010;
command_data[31:0] <= pkt_reg[95:64];
command_wr <= 1'b1;
sequence_d[16] <= 1'b1;
sequence_wr <= 1'b1;
if(pkt_reg[138:136]==3'b110) begin
state<=wait_s;
end
else begin
pkt_rdreq<=1'b1;
state <= discard_s;
end
end
else begin
command_data[34:32] <= 3'b011;
command_data[31:0] <= pkt_reg[95:64];
command_wr <= 1'b1;
packet_length <= packet_length - 4'h4;
state <= command3_s;
end
end
command3_s:begin
if(packet_length <= 16'h4)begin
command_data[34:32] <= 3'b010;
command_data[31:0] <= pkt_reg[63:32];
command_wr <= 1'b1;
sequence_d[16] <= 1'b1;
sequence_wr <= 1'b1;
if(pkt_reg[138:136]==3'b110) begin
state<=wait_s;
end
else begin
pkt_rdreq<=1'b1;
state <= discard_s;
end
end
else begin
command_data[34:32] <= 3'b011;
command_data[31:0] <= pkt_reg[63:32];
command_wr <= 1'b1;
packet_length <= packet_length - 4'h4;
state <= command4_s;
end
end
command4_s:begin
if(packet_length <= 16'h4)begin
command_data[34:32] <= 3'b010;
command_data[31:0] <= pkt_reg[31:0];
command_wr <= 1'b1;
sequence_d[16] <= 1'b1;
sequence_wr <= 1'b1;
if(pkt_reg[138:136]==3'b110) begin
state<=wait_s;
end
else begin
pkt_rdreq<=1'b1;
state <= discard_s;
end
end
else begin
command_data[34:32] <= 3'b011;
command_data[31:0] <= pkt_reg[31:0];
command_wr <= 1'b1;
packet_length <= packet_length - 4'h4;
pkt_rdreq<=1'b1;
state <= command1_s;
end
end
wr_datapath_s:begin
valid_rdreq <= 1'b0;
datapath_pkt <= pkt_q;
datapath_pkt_wrreq <= 1'b1;
if(pkt_q[138:136]==3'b110)//tail;
begin
pkt_rdreq<=1'b0;
datapath_valid_wrreq <= 1'b1;
datapath_valid <= 1'b1;
state<=wait_s;
end
else begin
pkt_rdreq <= 1'b1;
state <= wr_datapath_s;
end
end
wait_s:begin//wait the fifo empty signal to 1
datapath_pkt_wrreq <= 1'b0;
pkt_rdreq <= 1'b0;
valid_rdreq <= 1'b0;
datapath_valid_wrreq <= 1'b0;
command_wr <= 1'b0;
sequence_wr <= 1'b0;
state <= idle_s;
end
discard_s:begin
datapath_pkt_wrreq <= 1'b0;
pkt_rdreq <= 1'b0;
valid_rdreq <= 1'b0;
datapath_valid_wrreq <= 1'b0;
command_wr <= 1'b0;
sequence_wr <= 1'b0;
if(pkt_q[138:136]==3'b110)//tail;
begin
pkt_rdreq<=1'b0;
state<=wait_s;
end
else
begin
pkt_rdreq<=1'b1;
state<=discard_s;
end
end
endcase
end
end
reg pkt_rdreq;
wire [138:0]pkt_q;
wire [7:0] pkt_usedw;
fifo_256_139 fifo_256_139_manage_rx(
.aclr(!reset_n),
.clock(clk),
.data(pkt),
.rdreq(pkt_rdreq),
.wrreq(pkt_wrreq),
.q(pkt_q),
.usedw(pkt_usedw)
);
reg valid_rdreq;
wire valid_q;
wire valid_empty;
fifo_64_1 fifo_64_1_manage_rx(
.aclr(!reset_n),
.clock(clk),
.data(valid),
.rdreq(valid_rdreq),
.wrreq(valid_wrreq),
.empty(valid_empty),
.q(valid_q)
);
endmodule |
/*
* Copyright (c) 2000 Yasuhisa Kato <[email protected]>
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
// Modified my [email protected] to be self-checking per the comments.
module main;
reg clk ;
initial begin clk = 0 ; forever #5 clk = ~clk ; end
initial #20 $finish;
wire w, ww, wr, w1, wwr, ww1, wr1, wwro, ww1o, wr1o ;
reg r, rw ;
reg error;
// z <- (z) = z
assign ww = w ; // z <- (z) = z
assign wr = r ; // x <- (z) = x
assign w1 = 'b1 ; // 1 <- (z) = 1
assign wwr = w & r ; // x <- z & x
assign ww1 = w & 'b1 ; // x <- z & 1
assign wr1 = r & 'b1 ; // x <- x & 1
assign wwro= w | r ; // x <- z | x
assign ww1o= w | 'b1 ; // 1 <- z | 1
assign wr1o= r | 'b1 ; // 1 <- x | 1
always @(posedge clk)
rw <= w ; // x <- (x) = z
always @(posedge clk)
begin
#1;
$display("%b %b %b %b %b %b %b : %b %b %b : %b %b",
w, ww, wr, w1, wwr, ww1, wr1, wwro, ww1o, wr1o, r, rw );
end
initial
begin
error = 0;
#19;
if(ww !== 1'bz) begin
error = 1;
$display("FAILED - ww s/b z, is %h",ww);
end
if(wr !== 1'bx) begin
error = 1;
$display("FAILED - wr s/b x, is %h",wr);
end
if(w1 !== 1'b1) begin
error = 1;
$display("FAILED - wr s/b 1, is %h",wr);
end
if(wwr !== 1'bx) begin
error = 1;
$display("FAILED - wwr s/b x, is %h",wwr);
end
if(ww1 !== 1'bx) begin
error = 1;
$display("FAILED - ww1 s/b x, is %h",ww1);
end
if(wr1 !== 1'bx) begin
error = 1;
$display("FAILED - wr1 s/b x, is %h",wr1);
end
if(wwro !== 1'bx) begin
error = 1;
$display("FAILED - wwro s/b 1, is %h",wwro);
end
if(wr1o !== 1'b1) begin
error = 1;
$display("FAILED - wr1o s/b 1, is %h",wr1o);
end
if(r !== 1'bx) begin
error = 1;
$display("FAILED - r s/b x, is %h",r);
end
if(r !== 1'bx) begin
error = 1;
$display("FAILED - r s/b x, is %h",r);
end
if(rw !== 1'bz) begin
error = 1;
$display("FAILED - rw s/b z, is %h",r);
end
if(error === 0)
$display("PASSED");
$finish;
end
endmodule
// *Initial Value Test*
// expected output - This according to XL
// z z x 1 x x x : x 1 1 : x x
// z z x 1 x x x : x 1 1 : x z
// ivl current result
// z z x 1 x z x : x 1 1 : x x
// z z x 1 x z x : x 1 1 : x z
|
/*
# ZUMA Open FPGA Overlay
# Alex Brant
# Email: [email protected]
# 2012
# LUTRAM wrapper
*/
`include "def_generated.v"
module elut_custom #(
parameter used = 0,
parameter [0:2**6-1] LUT_MASK={2**6{1'b0}}
) (
a,
d,
dpra,
clk,
we,
dpo,
qdpo_clk,
qdpo_rst,
qdpo);
input [5 : 0] a;
input [0 : 0] d;
input [5 : 0] dpra;
input clk;
input we;
input qdpo_clk;
input qdpo_rst;
output dpo;
output qdpo;
wire lut_output;
wire lut_registered_output;
//no plattform. just for a verificational build.
generate
if( used == 1)
begin
//we generate a lut and a latch
LUT_K #(
.K(6),
.LUT_MASK(LUT_MASK)
) verification_lut2 (
.in(dpra),
.out(lut_output)
);
DFF #(
.INITIAL_VALUE(1'b0)
) verification_latch (
.D(lut_output),
.Q(lut_registered_output),
.clock(qdpo_clk)
);
end
else
begin
assign lut_output = 1'b0;
assign lut_registered_output = 1'b0;
end
endgenerate
assign dpo = lut_output;
assign qdpo = lut_registered_output;
endmodule
|
// This module is a counter for credits, that every decimation_p
// credits it would assert token_o signal once.
// It also supports a ready_i signal which declares when it can
// assert token_o. For normal use it could be set to one.
`include "bsg_defines.v"
module bsg_credit_to_token #( parameter `BSG_INV_PARAM(decimation_p )
, parameter `BSG_INV_PARAM(max_val_p )
)
( input clk_i
, input reset_i
, input credit_i
, input ready_i
, output token_o
);
localparam counter_width_lp = `BSG_WIDTH(max_val_p);
localparam step_width_lp = `BSG_WIDTH(decimation_p);
logic [counter_width_lp-1:0] count;
logic [step_width_lp-1:0] up,down;
logic token_ready, token_almost_ready;
bsg_counter_up_down_variable #(.max_val_p(max_val_p)
,.init_val_p(0)
,.max_step_p(decimation_p)
) credit_counter
( .clk_i(clk_i)
, .reset_i(reset_i)
, .up_i(up)
, .down_i(down)
, .count_o(count)
);
// counting the number of credits, and each token would decrease the count
// by deciation_p.
assign up = {{(step_width_lp-1){1'b0}},credit_i};
assign down = token_o ? step_width_lp'($unsigned(decimation_p)) : step_width_lp'(0);
// if count is one less than decimation_p but credit_i is also asserted and
// ready signal is high, we don't need to wait for next time ready_i signal
// is asserted and we can send a token. In this condition count would be set
// to zero using down and up signal.
assign token_ready = (count >= decimation_p);
assign token_almost_ready = (count >= $unsigned(decimation_p-1));
assign token_o = ready_i & (token_ready | (token_almost_ready & credit_i));
endmodule
`BSG_ABSTRACT_MODULE(bsg_credit_to_token)
|
/*
*
* Copyright (c) 2013 [email protected]
*
*
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
/*
* Golden nonces are sent over UART, hex encoded, with new-lines between each
* result.
*
* New work is received over UART, hex encoded, little-endian, and with
* new-lines between each new piece of work.
*
* If using the getwork protocol, new work should be sent as follows (Python
* pseudo-code):
* uart_write (data[128:128+24] + midstate + '\n')
*
*/
module comm_uart # (
parameter comm_clk_frequency = 100000000,
parameter baud_rate = 115200
) (
input comm_clk,
input uart_rx,
output uart_tx,
input hash_clk,
input rx_new_golden_ticket,
input [31:0] rx_golden_ticket,
output reg tx_new_work = 1'b0,
output [255:0] tx_midstate,
output [95:0] tx_blockdata
);
localparam temperature_report_delay = comm_clk_frequency * 4; // Every 4 seconds
//-----------------------------------------------------------------------------
// Transfer golden tickets from hashing clock domain to comm clock domain.
//-----------------------------------------------------------------------------
reg fifo_rd = 1'b0;
wire fifo_full, fifo_empty;
wire [31:0] fifo_q;
golden_ticket_fifo golden_ticket_fifo_blk (
.wr_clk (hash_clk),
.din (rx_golden_ticket),
.wr_en (rx_new_golden_ticket & ~fifo_full),
.rd_clk (comm_clk),
.rd_en (fifo_rd),
.dout (fifo_q),
.full (fifo_full),
.empty (fifo_empty)
);
//-----------------------------------------------------------------------------
// UART Transmitter
//-----------------------------------------------------------------------------
reg uart_tx_new_byte = 1'b0;
reg [7:0] uart_tx_byte = 8'd0;
wire uart_tx_ready;
uart_transmitter # (
.comm_clk_frequency (comm_clk_frequency),
.baud_rate (baud_rate)
) uart_transmitter_blk (
.clk (comm_clk),
.uart_tx (uart_tx),
.rx_new_byte (uart_tx_new_byte),
.rx_byte (uart_tx_byte),
.tx_ready (uart_tx_ready)
);
//-----------------------------------------------------------------------------
// Temperature Measurement
//-----------------------------------------------------------------------------
wire [15:0] measured_temperature;
comm_temperature_measurement temperature_blk (
.clk (comm_clk),
.tx_temp (measured_temperature)
);
//-----------------------------------------------------------------------------
// Comm Clock Domain
//-----------------------------------------------------------------------------
reg [31:0] temperature_timeout = 32'd0;
reg [4:0] transmit_state = 5'b00001;
reg [31:0] outgoing_nonce = 32'd0;
reg [7:0] outgoing_state = 8'd0;
// Read golden tickets and output over UART.
always @ (posedge comm_clk)
begin
if (temperature_timeout != temperature_report_delay)
temperature_timeout <= temperature_timeout + 32'd1;
uart_tx_new_byte <= 1'b0;
fifo_rd <= 1'b0;
case (transmit_state)
5'b00001: if (!fifo_empty) begin
transmit_state <= 5'b00010;
fifo_rd <= 1'b1;
end
else if (temperature_timeout == temperature_report_delay)
begin
temperature_timeout <= 32'd0;
outgoing_nonce <= {measured_temperature, 16'h0000};
outgoing_state <= 8'h0F;
transmit_state <= 5'b10000;
end
5'b00010: transmit_state <= 5'b00100;
5'b00100: transmit_state <= 5'b01000;
5'b01000: begin
outgoing_nonce <= fifo_q;
outgoing_state <= 8'hFF;
transmit_state <= 5'b10000;
end
5'b10000: if (uart_tx_ready) begin
if (outgoing_state == 8'd0)
begin
transmit_state <= 5'b00001;
uart_tx_new_byte <= 1'b1;
uart_tx_byte <= 8'd10;
end
else
begin
outgoing_state <= {1'b0, outgoing_state[7:1]};
outgoing_nonce <= outgoing_nonce << 4;
uart_tx_new_byte <= 1'b1;
// Hex encode 4 bits of nonce
if (outgoing_nonce[31:28] < 10)
uart_tx_byte <= outgoing_nonce[31:28] + 8'd48;
else
uart_tx_byte <= outgoing_nonce[31:28] + 8'd65 - 8'd10;
end
end
default: transmit_state <= 5'b00001;
endcase
end
//-----------------------------------------------------------------------------
// Receive new work
//-----------------------------------------------------------------------------
wire uart_rx_new_byte;
wire [7:0] uart_rx_byte;
uart_receiver # (
.comm_clk_frequency (comm_clk_frequency),
.baud_rate (baud_rate)
) uart_receiver_blk (
.clk (comm_clk),
.uart_rx (uart_rx),
.tx_new_byte (uart_rx_new_byte),
.tx_byte (uart_rx_byte)
);
reg [351:0] job;
reg new_job_flag = 1'b0;
reg [256+96-1:0] incoming_work = 352'd0;
reg digit = 1'b0;
reg [3:0] uart_rx_hex, uart_last_digit;
always @ (posedge comm_clk)
begin
// Decode incoming UART byte as hexidecimal
if (uart_rx_byte >= "A" && uart_rx_byte <= "F")
uart_rx_hex = uart_rx_byte - "A" + 4'd10;
else if (uart_rx_byte >= "a" && uart_rx_byte <= "f")
uart_rx_hex = uart_rx_byte - "A" + 4'd10;
else
uart_rx_hex = uart_rx_byte - "0";
if (uart_rx_new_byte)
begin
uart_last_digit <= uart_rx_hex;
digit <= ~digit;
if (digit == 1'b1)
incoming_work <= {uart_last_digit, uart_rx_hex, incoming_work[351:8]};
if (uart_rx_byte == "\n")
begin
digit <= 1'b0;
job <= incoming_work;
new_job_flag <= ~new_job_flag;
end
end
end
// Transfer job from comm clock domain to hash clock domain
reg [351:0] job_meta0, job_meta1;
reg [2:0] new_job_meta;
always @ (posedge hash_clk)
begin
{job_meta1, job_meta0} <= {job_meta0, job};
new_job_meta <= {new_job_meta[1:0], new_job_flag};
if (new_job_meta[2] != new_job_meta[1])
tx_new_work <= 1'b1;
else
tx_new_work <= 1'b0;
end
assign {tx_midstate, tx_blockdata} = job_meta1;
endmodule
module comm_temperature_measurement (
input clk,
output reg [15:0] tx_temp
);
wire drdy;
wire [15:0] do;
xadc_temp_sensor xadc_blk (
.daddr_in (7'd0),
.dclk_in (clk),
.den_in (1'b1),
.di_in (16'd0),
.dwe_in (1'b0),
.vp_in (),
.vn_in (),
.busy_out (),
.channel_out (),
.do_out (do),
.drdy_out (drdy),
.eoc_out (),
.eos_out (),
.ot_out (),
.vccaux_alarm_out (),
.vccint_alarm_out (),
.user_temp_alarm_out (),
.alarm_out ()
);
always @ (posedge clk)
begin
if (drdy)
tx_temp <= do;
end
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Virtex-6 Integrated Block for PCI Express
// File : pcie_2_0_v6.v
// Version : 1.7
//-- Description: Solution wrapper for Virtex6 Hard Block for PCI Express
//--
//--
//--
//--------------------------------------------------------------------------------
`timescale 1ps/1ps
module pcie_2_0_v6 #(
parameter TCQ = 1,
parameter REF_CLK_FREQ = 0, // 0 - 100 MHz, 1 - 125 MHz, 2 - 250 MHz
parameter PIPE_PIPELINE_STAGES = 0, // 0 - 0 stages, 1 - 1 stage, 2 - 2 stages
parameter AER_BASE_PTR = 12'h128,
parameter AER_CAP_ECRC_CHECK_CAPABLE = "FALSE",
parameter AER_CAP_ECRC_GEN_CAPABLE = "FALSE",
parameter AER_CAP_ID = 16'h0001,
parameter AER_CAP_INT_MSG_NUM_MSI = 5'h0a,
parameter AER_CAP_INT_MSG_NUM_MSIX = 5'h15,
parameter AER_CAP_NEXTPTR = 12'h160,
parameter AER_CAP_ON = "FALSE",
parameter AER_CAP_PERMIT_ROOTERR_UPDATE = "TRUE",
parameter AER_CAP_VERSION = 4'h1,
parameter ALLOW_X8_GEN2 = "TRUE",
parameter BAR0 = 32'hffffff00,
parameter BAR1 = 32'hffff0000,
parameter BAR2 = 32'hffff000c,
parameter BAR3 = 32'hffffffff,
parameter BAR4 = 32'h00000000,
parameter BAR5 = 32'h00000000,
parameter CAPABILITIES_PTR = 8'h40,
parameter CARDBUS_CIS_POINTER = 32'h00000000,
parameter CLASS_CODE = 24'h000000,
parameter CMD_INTX_IMPLEMENTED = "TRUE",
parameter CPL_TIMEOUT_DISABLE_SUPPORTED = "FALSE",
parameter CPL_TIMEOUT_RANGES_SUPPORTED = 4'h0,
parameter CRM_MODULE_RSTS = 7'h00,
parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE = "TRUE",
parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE = "TRUE",
parameter DEV_CAP_ENDPOINT_L0S_LATENCY = 0,
parameter DEV_CAP_ENDPOINT_L1_LATENCY = 0,
parameter DEV_CAP_EXT_TAG_SUPPORTED = "TRUE",
parameter DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "FALSE",
parameter DEV_CAP_MAX_PAYLOAD_SUPPORTED = 2,
parameter DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT = 0,
parameter DEV_CAP_ROLE_BASED_ERROR = "TRUE",
parameter DEV_CAP_RSVD_14_12 = 0,
parameter DEV_CAP_RSVD_17_16 = 0,
parameter DEV_CAP_RSVD_31_29 = 0,
parameter DEV_CONTROL_AUX_POWER_SUPPORTED = "FALSE",
parameter DEVICE_ID = 16'h0007,
parameter DISABLE_ASPM_L1_TIMER = "FALSE",
parameter DISABLE_BAR_FILTERING = "FALSE",
parameter DISABLE_ID_CHECK = "FALSE",
parameter DISABLE_LANE_REVERSAL = "FALSE",
parameter DISABLE_RX_TC_FILTER = "FALSE",
parameter DISABLE_SCRAMBLING = "FALSE",
parameter DNSTREAM_LINK_NUM = 8'h00,
parameter DSN_BASE_PTR = 12'h100,
parameter DSN_CAP_ID = 16'h0003,
parameter DSN_CAP_NEXTPTR = 12'h000,
parameter DSN_CAP_ON = "TRUE",
parameter DSN_CAP_VERSION = 4'h1,
parameter ENABLE_MSG_ROUTE = 11'h000,
parameter ENABLE_RX_TD_ECRC_TRIM = "FALSE",
parameter ENTER_RVRY_EI_L0 = "TRUE",
parameter EXPANSION_ROM = 32'hfffff001,
parameter EXT_CFG_CAP_PTR = 6'h3f,
parameter EXT_CFG_XP_CAP_PTR = 10'h3ff,
parameter HEADER_TYPE = 8'h00,
parameter INFER_EI = 5'h00,
parameter INTERRUPT_PIN = 8'h01,
parameter IS_SWITCH = "FALSE",
parameter LAST_CONFIG_DWORD = 10'h042,
parameter LINK_CAP_ASPM_SUPPORT = 1,
parameter LINK_CAP_CLOCK_POWER_MANAGEMENT = "FALSE",
parameter LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP = "FALSE",
parameter LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP = "FALSE",
parameter LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7,
parameter LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7,
parameter LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7,
parameter LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7,
parameter LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7,
parameter LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7,
parameter LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7,
parameter LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7,
parameter LINK_CAP_MAX_LINK_SPEED = 4'h1,
parameter LINK_CAP_MAX_LINK_WIDTH = 6'h08,
parameter LINK_CAP_RSVD_23_22 = 0,
parameter LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE = "FALSE",
parameter LINK_CONTROL_RCB = 0,
parameter LINK_CTRL2_DEEMPHASIS = "FALSE",
parameter LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE = "FALSE",
parameter LINK_CTRL2_TARGET_LINK_SPEED = 4'h0,
parameter LINK_STATUS_SLOT_CLOCK_CONFIG = "TRUE",
parameter LL_ACK_TIMEOUT = 15'h0204,
parameter LL_ACK_TIMEOUT_EN = "FALSE",
parameter LL_ACK_TIMEOUT_FUNC = 0,
parameter LL_REPLAY_TIMEOUT = 15'h060d,
parameter LL_REPLAY_TIMEOUT_EN = "FALSE",
parameter LL_REPLAY_TIMEOUT_FUNC = 0,
parameter LTSSM_MAX_LINK_WIDTH = LINK_CAP_MAX_LINK_WIDTH,
parameter MSI_BASE_PTR = 8'h48,
parameter MSI_CAP_ID = 8'h05,
parameter MSI_CAP_MULTIMSGCAP = 0,
parameter MSI_CAP_MULTIMSG_EXTENSION = 0,
parameter MSI_CAP_NEXTPTR = 8'h60,
parameter MSI_CAP_ON = "FALSE",
parameter MSI_CAP_PER_VECTOR_MASKING_CAPABLE = "TRUE",
parameter MSI_CAP_64_BIT_ADDR_CAPABLE = "TRUE",
parameter MSIX_BASE_PTR = 8'h9c,
parameter MSIX_CAP_ID = 8'h11,
parameter MSIX_CAP_NEXTPTR = 8'h00,
parameter MSIX_CAP_ON = "FALSE",
parameter MSIX_CAP_PBA_BIR = 0,
parameter MSIX_CAP_PBA_OFFSET = 29'h00000050,
parameter MSIX_CAP_TABLE_BIR = 0,
parameter MSIX_CAP_TABLE_OFFSET = 29'h00000040,
parameter MSIX_CAP_TABLE_SIZE = 11'h000,
parameter N_FTS_COMCLK_GEN1 = 255,
parameter N_FTS_COMCLK_GEN2 = 255,
parameter N_FTS_GEN1 = 255,
parameter N_FTS_GEN2 = 255,
parameter PCIE_BASE_PTR = 8'h60,
parameter PCIE_CAP_CAPABILITY_ID = 8'h10,
parameter PCIE_CAP_CAPABILITY_VERSION = 4'h2,
parameter PCIE_CAP_DEVICE_PORT_TYPE = 4'h0,
parameter PCIE_CAP_INT_MSG_NUM = 5'h00,
parameter PCIE_CAP_NEXTPTR = 8'h00,
parameter PCIE_CAP_ON = "TRUE",
parameter PCIE_CAP_RSVD_15_14 = 0,
parameter PCIE_CAP_SLOT_IMPLEMENTED = "FALSE",
parameter PCIE_REVISION = 2,
parameter PGL0_LANE = 0,
parameter PGL1_LANE = 1,
parameter PGL2_LANE = 2,
parameter PGL3_LANE = 3,
parameter PGL4_LANE = 4,
parameter PGL5_LANE = 5,
parameter PGL6_LANE = 6,
parameter PGL7_LANE = 7,
parameter PL_AUTO_CONFIG = 0,
parameter PL_FAST_TRAIN = "FALSE",
parameter PM_BASE_PTR = 8'h40,
parameter PM_CAP_AUXCURRENT = 0,
parameter PM_CAP_DSI = "FALSE",
parameter PM_CAP_D1SUPPORT = "TRUE",
parameter PM_CAP_D2SUPPORT = "TRUE",
parameter PM_CAP_ID = 8'h01,
parameter PM_CAP_NEXTPTR = 8'h48,
parameter PM_CAP_ON = "TRUE",
parameter PM_CAP_PME_CLOCK = "FALSE",
parameter PM_CAP_PMESUPPORT = 5'h0f,
parameter PM_CAP_RSVD_04 = 0,
parameter PM_CAP_VERSION = 3,
parameter PM_CSR_BPCCEN = "FALSE",
parameter PM_CSR_B2B3 = "FALSE",
parameter PM_CSR_NOSOFTRST = "TRUE",
parameter PM_DATA_SCALE0 = 2'h1,
parameter PM_DATA_SCALE1 = 2'h1,
parameter PM_DATA_SCALE2 = 2'h1,
parameter PM_DATA_SCALE3 = 2'h1,
parameter PM_DATA_SCALE4 = 2'h1,
parameter PM_DATA_SCALE5 = 2'h1,
parameter PM_DATA_SCALE6 = 2'h1,
parameter PM_DATA_SCALE7 = 2'h1,
parameter PM_DATA0 = 8'h01,
parameter PM_DATA1 = 8'h01,
parameter PM_DATA2 = 8'h01,
parameter PM_DATA3 = 8'h01,
parameter PM_DATA4 = 8'h01,
parameter PM_DATA5 = 8'h01,
parameter PM_DATA6 = 8'h01,
parameter PM_DATA7 = 8'h01,
parameter RECRC_CHK = 0,
parameter RECRC_CHK_TRIM = "FALSE",
parameter REVISION_ID = 8'h00,
parameter ROOT_CAP_CRS_SW_VISIBILITY = "FALSE",
parameter SELECT_DLL_IF = "FALSE",
parameter SLOT_CAP_ATT_BUTTON_PRESENT = "FALSE",
parameter SLOT_CAP_ATT_INDICATOR_PRESENT = "FALSE",
parameter SLOT_CAP_ELEC_INTERLOCK_PRESENT = "FALSE",
parameter SLOT_CAP_HOTPLUG_CAPABLE = "FALSE",
parameter SLOT_CAP_HOTPLUG_SURPRISE = "FALSE",
parameter SLOT_CAP_MRL_SENSOR_PRESENT = "FALSE",
parameter SLOT_CAP_NO_CMD_COMPLETED_SUPPORT = "FALSE",
parameter SLOT_CAP_PHYSICAL_SLOT_NUM = 13'h0000,
parameter SLOT_CAP_POWER_CONTROLLER_PRESENT = "FALSE",
parameter SLOT_CAP_POWER_INDICATOR_PRESENT = "FALSE",
parameter SLOT_CAP_SLOT_POWER_LIMIT_SCALE = 0,
parameter SLOT_CAP_SLOT_POWER_LIMIT_VALUE = 8'h00,
parameter SPARE_BIT0 = 0,
parameter SPARE_BIT1 = 0,
parameter SPARE_BIT2 = 0,
parameter SPARE_BIT3 = 0,
parameter SPARE_BIT4 = 0,
parameter SPARE_BIT5 = 0,
parameter SPARE_BIT6 = 0,
parameter SPARE_BIT7 = 0,
parameter SPARE_BIT8 = 0,
parameter SPARE_BYTE0 = 8'h00,
parameter SPARE_BYTE1 = 8'h00,
parameter SPARE_BYTE2 = 8'h00,
parameter SPARE_BYTE3 = 8'h00,
parameter SPARE_WORD0 = 32'h00000000,
parameter SPARE_WORD1 = 32'h00000000,
parameter SPARE_WORD2 = 32'h00000000,
parameter SPARE_WORD3 = 32'h00000000,
parameter SUBSYSTEM_ID = 16'h0007,
parameter SUBSYSTEM_VENDOR_ID = 16'h10ee,
parameter TL_RBYPASS = "FALSE",
parameter TL_RX_RAM_RADDR_LATENCY = 0,
parameter TL_RX_RAM_RDATA_LATENCY = 2,
parameter TL_RX_RAM_WRITE_LATENCY = 0,
parameter TL_TFC_DISABLE = "FALSE",
parameter TL_TX_CHECKS_DISABLE = "FALSE",
parameter TL_TX_RAM_RADDR_LATENCY = 0,
parameter TL_TX_RAM_RDATA_LATENCY = 2,
parameter TL_TX_RAM_WRITE_LATENCY = 0,
parameter UPCONFIG_CAPABLE = "TRUE",
parameter UPSTREAM_FACING = "TRUE",
parameter EXIT_LOOPBACK_ON_EI = "TRUE",
parameter UR_INV_REQ = "TRUE",
parameter USER_CLK_FREQ = 3,
parameter VC_BASE_PTR = 12'h10c,
parameter VC_CAP_ID = 16'h0002,
parameter VC_CAP_NEXTPTR = 12'h000,
parameter VC_CAP_ON = "FALSE",
parameter VC_CAP_REJECT_SNOOP_TRANSACTIONS = "FALSE",
parameter VC_CAP_VERSION = 4'h1,
parameter VC0_CPL_INFINITE = "TRUE",
parameter VC0_RX_RAM_LIMIT = 13'h03ff,
parameter VC0_TOTAL_CREDITS_CD = 127,
parameter VC0_TOTAL_CREDITS_CH = 31,
parameter VC0_TOTAL_CREDITS_NPH = 12,
parameter VC0_TOTAL_CREDITS_PD = 288,
parameter VC0_TOTAL_CREDITS_PH = 32,
parameter VC0_TX_LASTPACKET = 31,
parameter VENDOR_ID = 16'h10ee,
parameter VSEC_BASE_PTR = 12'h160,
parameter VSEC_CAP_HDR_ID = 16'h1234,
parameter VSEC_CAP_HDR_LENGTH = 12'h018,
parameter VSEC_CAP_HDR_REVISION = 4'h1,
parameter VSEC_CAP_ID = 16'h000b,
parameter VSEC_CAP_IS_LINK_VISIBLE = "TRUE",
parameter VSEC_CAP_NEXTPTR = 12'h000,
parameter VSEC_CAP_ON = "FALSE",
parameter VSEC_CAP_VERSION = 4'h1
)
(
input [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] PCIEXPRXN,
input [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] PCIEXPRXP,
output [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] PCIEXPTXN,
output [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] PCIEXPTXP,
input SYSCLK,
input FUNDRSTN,
output TRNLNKUPN,
output TRNCLK,
output PHYRDYN,
output USERRSTN,
output RECEIVEDFUNCLVLRSTN,
output LNKCLKEN,
input SYSRSTN,
input PLRSTN,
input DLRSTN,
input TLRSTN,
input FUNCLVLRSTN,
input CMRSTN,
input CMSTICKYRSTN,
output [6:0] TRNRBARHITN,
output [127:0] TRNRD,
output TRNRECRCERRN,
output TRNREOFN,
output TRNRERRFWDN,
output [1:0] TRNRREMN,
output TRNRSOFN,
output TRNRSRCDSCN,
output TRNRSRCRDYN,
input TRNRDSTRDYN,
input TRNRNPOKN,
output [5:0] TRNTBUFAV,
output TRNTDLLPDSTRDYN,
output TRNTDSTRDYN,
output TRNTERRDROPN,
input [127:0] TRNTD,
input [31:0] TRNTDLLPDATA,
input TRNTDLLPSRCRDYN,
input TRNTECRCGENN,
input TRNTEOFN,
input TRNTERRFWDN,
input [1:0] TRNTREMN,
input TRNTSOFN,
input TRNTSRCDSCN,
input TRNTSRCRDYN,
input TRNTSTRN,
output [11:0] TRNFCCPLD,
output [7:0] TRNFCCPLH,
output [11:0] TRNFCNPD,
output [7:0] TRNFCNPH,
output [11:0] TRNFCPD,
output [7:0] TRNFCPH,
input [2:0] TRNFCSEL,
output CFGAERECRCCHECKEN,
output CFGAERECRCGENEN,
output CFGCOMMANDBUSMASTERENABLE,
output CFGCOMMANDINTERRUPTDISABLE,
output CFGCOMMANDIOENABLE,
output CFGCOMMANDMEMENABLE,
output CFGCOMMANDSERREN,
output CFGDEVCONTROLAUXPOWEREN,
output CFGDEVCONTROLCORRERRREPORTINGEN,
output CFGDEVCONTROLENABLERO,
output CFGDEVCONTROLEXTTAGEN,
output CFGDEVCONTROLFATALERRREPORTINGEN,
output [2:0] CFGDEVCONTROLMAXPAYLOAD,
output [2:0] CFGDEVCONTROLMAXREADREQ,
output CFGDEVCONTROLNONFATALREPORTINGEN,
output CFGDEVCONTROLNOSNOOPEN,
output CFGDEVCONTROLPHANTOMEN,
output CFGDEVCONTROLURERRREPORTINGEN,
output CFGDEVCONTROL2CPLTIMEOUTDIS,
output [3:0] CFGDEVCONTROL2CPLTIMEOUTVAL,
output CFGDEVSTATUSCORRERRDETECTED,
output CFGDEVSTATUSFATALERRDETECTED,
output CFGDEVSTATUSNONFATALERRDETECTED,
output CFGDEVSTATUSURDETECTED,
output [31:0] CFGDO,
output CFGERRAERHEADERLOGSETN,
output CFGERRCPLRDYN,
output [7:0] CFGINTERRUPTDO,
output [2:0] CFGINTERRUPTMMENABLE,
output CFGINTERRUPTMSIENABLE,
output CFGINTERRUPTMSIXENABLE,
output CFGINTERRUPTMSIXFM,
output CFGINTERRUPTRDYN,
output CFGLINKCONTROLRCB,
output [1:0] CFGLINKCONTROLASPMCONTROL,
output CFGLINKCONTROLAUTOBANDWIDTHINTEN,
output CFGLINKCONTROLBANDWIDTHINTEN,
output CFGLINKCONTROLCLOCKPMEN,
output CFGLINKCONTROLCOMMONCLOCK,
output CFGLINKCONTROLEXTENDEDSYNC,
output CFGLINKCONTROLHWAUTOWIDTHDIS,
output CFGLINKCONTROLLINKDISABLE,
output CFGLINKCONTROLRETRAINLINK,
output CFGLINKSTATUSAUTOBANDWIDTHSTATUS,
output CFGLINKSTATUSBANDWITHSTATUS,
output [1:0] CFGLINKSTATUSCURRENTSPEED,
output CFGLINKSTATUSDLLACTIVE,
output CFGLINKSTATUSLINKTRAINING,
output [3:0] CFGLINKSTATUSNEGOTIATEDWIDTH,
output [15:0] CFGMSGDATA,
output CFGMSGRECEIVED,
output CFGMSGRECEIVEDASSERTINTA,
output CFGMSGRECEIVEDASSERTINTB,
output CFGMSGRECEIVEDASSERTINTC,
output CFGMSGRECEIVEDASSERTINTD,
output CFGMSGRECEIVEDDEASSERTINTA,
output CFGMSGRECEIVEDDEASSERTINTB,
output CFGMSGRECEIVEDDEASSERTINTC,
output CFGMSGRECEIVEDDEASSERTINTD,
output CFGMSGRECEIVEDERRCOR,
output CFGMSGRECEIVEDERRFATAL,
output CFGMSGRECEIVEDERRNONFATAL,
output CFGMSGRECEIVEDPMASNAK,
output CFGMSGRECEIVEDPMETO,
output CFGMSGRECEIVEDPMETOACK,
output CFGMSGRECEIVEDPMPME,
output CFGMSGRECEIVEDSETSLOTPOWERLIMIT,
output CFGMSGRECEIVEDUNLOCK,
output [2:0] CFGPCIELINKSTATE,
output CFGPMCSRPMEEN,
output CFGPMCSRPMESTATUS,
output [1:0] CFGPMCSRPOWERSTATE,
output CFGPMRCVASREQL1N,
output CFGPMRCVENTERL1N,
output CFGPMRCVENTERL23N,
output CFGPMRCVREQACKN,
output CFGRDWRDONEN,
output CFGSLOTCONTROLELECTROMECHILCTLPULSE,
output CFGTRANSACTION,
output [6:0] CFGTRANSACTIONADDR,
output CFGTRANSACTIONTYPE,
output [6:0] CFGVCTCVCMAP,
input [3:0] CFGBYTEENN,
input [31:0] CFGDI,
input [7:0] CFGDSBUSNUMBER,
input [4:0] CFGDSDEVICENUMBER,
input [2:0] CFGDSFUNCTIONNUMBER,
input [63:0] CFGDSN,
input [9:0] CFGDWADDR,
input CFGERRACSN,
input [127:0] CFGERRAERHEADERLOG,
input CFGERRCORN,
input CFGERRCPLABORTN,
input CFGERRCPLTIMEOUTN,
input CFGERRCPLUNEXPECTN,
input CFGERRECRCN,
input CFGERRLOCKEDN,
input CFGERRPOSTEDN,
input [47:0] CFGERRTLPCPLHEADER,
input CFGERRURN,
input CFGINTERRUPTASSERTN,
input [7:0] CFGINTERRUPTDI,
input CFGINTERRUPTN,
input CFGPMDIRECTASPML1N,
input CFGPMSENDPMACKN,
input CFGPMSENDPMETON,
input CFGPMSENDPMNAKN,
input CFGPMTURNOFFOKN,
input CFGPMWAKEN,
input [7:0] CFGPORTNUMBER,
input CFGRDENN,
input CFGTRNPENDINGN,
input CFGWRENN,
input CFGWRREADONLYN,
input CFGWRRW1CASRWN,
output [2:0] PLINITIALLINKWIDTH,
output [1:0] PLLANEREVERSALMODE,
output PLLINKGEN2CAP,
output PLLINKPARTNERGEN2SUPPORTED,
output PLLINKUPCFGCAP,
output [5:0] PLLTSSMSTATE,
output PLPHYLNKUPN,
output PLRECEIVEDHOTRST,
output [1:0] PLRXPMSTATE,
output PLSELLNKRATE,
output [1:0] PLSELLNKWIDTH,
output [2:0] PLTXPMSTATE,
input PLDIRECTEDLINKAUTON,
input [1:0] PLDIRECTEDLINKCHANGE,
input PLDIRECTEDLINKSPEED,
input [1:0] PLDIRECTEDLINKWIDTH,
input PLDOWNSTREAMDEEMPHSOURCE,
input PLUPSTREAMPREFERDEEMPH,
input PLTRANSMITHOTRST,
output DBGSCLRA,
output DBGSCLRB,
output DBGSCLRC,
output DBGSCLRD,
output DBGSCLRE,
output DBGSCLRF,
output DBGSCLRG,
output DBGSCLRH,
output DBGSCLRI,
output DBGSCLRJ,
output DBGSCLRK,
output [63:0] DBGVECA,
output [63:0] DBGVECB,
output [11:0] DBGVECC,
output [11:0] PLDBGVEC,
input [1:0] DBGMODE,
input DBGSUBMODE,
input [2:0] PLDBGMODE,
output [15:0] PCIEDRPDO,
output PCIEDRPDRDY,
input PCIEDRPCLK,
input [8:0] PCIEDRPDADDR,
input PCIEDRPDEN,
input [15:0] PCIEDRPDI,
input PCIEDRPDWE,
output GTPLLLOCK,
input PIPECLK,
input USERCLK,
input BLOCKCLK,
input DRPCLK,
input CLOCKLOCKED,
output TxOutClk
);
// wire declarations
wire LL2BADDLLPERRN;
wire LL2BADTLPERRN;
wire LL2PROTOCOLERRN;
wire LL2REPLAYROERRN;
wire LL2REPLAYTOERRN;
wire LL2SUSPENDOKN;
wire LL2TFCINIT1SEQN;
wire LL2TFCINIT2SEQN;
wire [12:0] MIMRXRADDR;
wire MIMRXRCE;
wire MIMRXREN;
wire [12:0] MIMRXWADDR;
wire [67:0] MIMRXWDATA;
wire MIMRXWEN;
wire [12:0] MIMTXRADDR;
wire MIMTXRCE;
wire MIMTXREN;
wire [12:0] MIMTXWADDR;
wire [68:0] MIMTXWDATA;
wire MIMTXWEN;
wire PIPERX0POLARITY;
wire PIPERX1POLARITY;
wire PIPERX2POLARITY;
wire PIPERX3POLARITY;
wire PIPERX4POLARITY;
wire PIPERX5POLARITY;
wire PIPERX6POLARITY;
wire PIPERX7POLARITY;
wire PIPETXDEEMPH;
wire [2:0] PIPETXMARGIN;
wire PIPETXRATE;
wire PIPETXRCVRDET;
wire PIPETXRESET;
wire [1:0] PIPETX0CHARISK;
wire PIPETX0COMPLIANCE;
wire [15:0] PIPETX0DATA;
wire PIPETX0ELECIDLE;
wire [1:0] PIPETX0POWERDOWN;
wire [1:0] PIPETX1CHARISK;
wire PIPETX1COMPLIANCE;
wire [15:0] PIPETX1DATA;
wire PIPETX1ELECIDLE;
wire [1:0] PIPETX1POWERDOWN;
wire [1:0] PIPETX2CHARISK;
wire PIPETX2COMPLIANCE;
wire [15:0] PIPETX2DATA;
wire PIPETX2ELECIDLE;
wire [1:0] PIPETX2POWERDOWN;
wire [1:0] PIPETX3CHARISK;
wire PIPETX3COMPLIANCE;
wire [15:0] PIPETX3DATA;
wire PIPETX3ELECIDLE;
wire [1:0] PIPETX3POWERDOWN;
wire [1:0] PIPETX4CHARISK;
wire PIPETX4COMPLIANCE;
wire [15:0] PIPETX4DATA;
wire PIPETX4ELECIDLE;
wire [1:0] PIPETX4POWERDOWN;
wire [1:0] PIPETX5CHARISK;
wire PIPETX5COMPLIANCE;
wire [15:0] PIPETX5DATA;
wire PIPETX5ELECIDLE;
wire [1:0] PIPETX5POWERDOWN;
wire [1:0] PIPETX6CHARISK;
wire PIPETX6COMPLIANCE;
wire [15:0] PIPETX6DATA;
wire PIPETX6ELECIDLE;
wire [1:0] PIPETX6POWERDOWN;
wire [1:0] PIPETX7CHARISK;
wire PIPETX7COMPLIANCE;
wire [15:0] PIPETX7DATA;
wire PIPETX7ELECIDLE;
wire [1:0] PIPETX7POWERDOWN;
wire PL2LINKUPN;
wire PL2RECEIVERERRN;
wire PL2RECOVERYN;
wire PL2RXELECIDLE;
wire PL2SUSPENDOK;
wire TL2ASPMSUSPENDCREDITCHECKOKN;
wire TL2ASPMSUSPENDREQN;
wire TL2PPMSUSPENDOKN;
wire LL2SENDASREQL1N = 1'b1;
wire LL2SENDENTERL1N = 1'b1;
wire LL2SENDENTERL23N = 1'b1;
wire LL2SUSPENDNOWN = 1'b1;
wire LL2TLPRCVN = 1'b1;
wire [67:0] MIMRXRDATA;
wire [68:0] MIMTXRDATA;
wire [4:0] PL2DIRECTEDLSTATE = 5'b0;
wire TL2ASPMSUSPENDCREDITCHECKN;
wire TL2PPMSUSPENDREQN;
wire PIPERX0CHANISALIGNED;
wire [1:0] PIPERX0CHARISK;
wire [15:0] PIPERX0DATA;
wire PIPERX0ELECIDLE;
wire PIPERX0PHYSTATUS;
wire [2:0] PIPERX0STATUS;
wire PIPERX0VALID;
wire PIPERX1CHANISALIGNED;
wire [1:0] PIPERX1CHARISK;
wire [15:0] PIPERX1DATA;
wire PIPERX1ELECIDLE;
wire PIPERX1PHYSTATUS;
wire [2:0] PIPERX1STATUS;
wire PIPERX1VALID;
wire PIPERX2CHANISALIGNED;
wire [1:0] PIPERX2CHARISK;
wire [15:0] PIPERX2DATA;
wire PIPERX2ELECIDLE;
wire PIPERX2PHYSTATUS;
wire [2:0] PIPERX2STATUS;
wire PIPERX2VALID;
wire PIPERX3CHANISALIGNED;
wire [1:0] PIPERX3CHARISK;
wire [15:0] PIPERX3DATA;
wire PIPERX3ELECIDLE;
wire PIPERX3PHYSTATUS;
wire [2:0] PIPERX3STATUS;
wire PIPERX3VALID;
wire PIPERX4CHANISALIGNED;
wire [1:0] PIPERX4CHARISK;
wire [15:0] PIPERX4DATA;
wire PIPERX4ELECIDLE;
wire PIPERX4PHYSTATUS;
wire [2:0] PIPERX4STATUS;
wire PIPERX4VALID;
wire PIPERX5CHANISALIGNED;
wire [1:0] PIPERX5CHARISK;
wire [15:0] PIPERX5DATA;
wire PIPERX5ELECIDLE;
wire PIPERX5PHYSTATUS;
wire [2:0] PIPERX5STATUS;
wire PIPERX5VALID;
wire PIPERX6CHANISALIGNED;
wire [1:0] PIPERX6CHARISK;
wire [15:0] PIPERX6DATA;
wire PIPERX6ELECIDLE;
wire PIPERX6PHYSTATUS;
wire [2:0] PIPERX6STATUS;
wire PIPERX6VALID;
wire PIPERX7CHANISALIGNED;
wire [1:0] PIPERX7CHARISK;
wire [15:0] PIPERX7DATA;
wire PIPERX7ELECIDLE;
wire PIPERX7PHYSTATUS;
wire [2:0] PIPERX7STATUS;
wire PIPERX7VALID;
wire PIPERX0POLARITYGT;
wire PIPERX1POLARITYGT;
wire PIPERX2POLARITYGT;
wire PIPERX3POLARITYGT;
wire PIPERX4POLARITYGT;
wire PIPERX5POLARITYGT;
wire PIPERX6POLARITYGT;
wire PIPERX7POLARITYGT;
wire PIPETXDEEMPHGT;
wire [2:0] PIPETXMARGINGT;
wire PIPETXRATEGT;
wire PIPETXRCVRDETGT;
wire [1:0] PIPETX0CHARISKGT;
wire PIPETX0COMPLIANCEGT;
wire [15:0] PIPETX0DATAGT;
wire PIPETX0ELECIDLEGT;
wire [1:0] PIPETX0POWERDOWNGT;
wire [1:0] PIPETX1CHARISKGT;
wire PIPETX1COMPLIANCEGT;
wire [15:0] PIPETX1DATAGT;
wire PIPETX1ELECIDLEGT;
wire [1:0] PIPETX1POWERDOWNGT;
wire [1:0] PIPETX2CHARISKGT;
wire PIPETX2COMPLIANCEGT;
wire [15:0] PIPETX2DATAGT;
wire PIPETX2ELECIDLEGT;
wire [1:0] PIPETX2POWERDOWNGT;
wire [1:0] PIPETX3CHARISKGT;
wire PIPETX3COMPLIANCEGT;
wire [15:0] PIPETX3DATAGT;
wire PIPETX3ELECIDLEGT;
wire [1:0] PIPETX3POWERDOWNGT;
wire [1:0] PIPETX4CHARISKGT;
wire PIPETX4COMPLIANCEGT;
wire [15:0] PIPETX4DATAGT;
wire PIPETX4ELECIDLEGT;
wire [1:0] PIPETX4POWERDOWNGT;
wire [1:0] PIPETX5CHARISKGT;
wire PIPETX5COMPLIANCEGT;
wire [15:0] PIPETX5DATAGT;
wire PIPETX5ELECIDLEGT;
wire [1:0] PIPETX5POWERDOWNGT;
wire [1:0] PIPETX6CHARISKGT;
wire PIPETX6COMPLIANCEGT;
wire [15:0] PIPETX6DATAGT;
wire PIPETX6ELECIDLEGT;
wire [1:0] PIPETX6POWERDOWNGT;
wire [1:0] PIPETX7CHARISKGT;
wire PIPETX7COMPLIANCEGT;
wire [15:0] PIPETX7DATAGT;
wire PIPETX7ELECIDLEGT;
wire [1:0] PIPETX7POWERDOWNGT;
wire PIPERX0CHANISALIGNEDGT;
wire [1:0] PIPERX0CHARISKGT;
wire [15:0] PIPERX0DATAGT;
wire PIPERX0ELECIDLEGT;
wire PIPERX0PHYSTATUSGT;
wire [2:0] PIPERX0STATUSGT;
wire PIPERX0VALIDGT;
wire PIPERX1CHANISALIGNEDGT;
wire [1:0] PIPERX1CHARISKGT;
wire [15:0] PIPERX1DATAGT;
wire PIPERX1ELECIDLEGT;
wire PIPERX1PHYSTATUSGT;
wire [2:0] PIPERX1STATUSGT;
wire PIPERX1VALIDGT;
wire PIPERX2CHANISALIGNEDGT;
wire [1:0] PIPERX2CHARISKGT;
wire [15:0] PIPERX2DATAGT;
wire PIPERX2ELECIDLEGT;
wire PIPERX2PHYSTATUSGT;
wire [2:0] PIPERX2STATUSGT;
wire PIPERX2VALIDGT;
wire PIPERX3CHANISALIGNEDGT;
wire [1:0] PIPERX3CHARISKGT;
wire [15:0] PIPERX3DATAGT;
wire PIPERX3ELECIDLEGT;
wire PIPERX3PHYSTATUSGT;
wire [2:0] PIPERX3STATUSGT;
wire PIPERX3VALIDGT;
wire PIPERX4CHANISALIGNEDGT;
wire [1:0] PIPERX4CHARISKGT;
wire [15:0] PIPERX4DATAGT;
wire PIPERX4ELECIDLEGT;
wire PIPERX4PHYSTATUSGT;
wire [2:0] PIPERX4STATUSGT;
wire PIPERX4VALIDGT;
wire PIPERX5CHANISALIGNEDGT;
wire [1:0] PIPERX5CHARISKGT;
wire [15:0] PIPERX5DATAGT;
wire PIPERX5ELECIDLEGT;
wire PIPERX5PHYSTATUSGT;
wire [2:0] PIPERX5STATUSGT;
wire PIPERX5VALIDGT;
wire PIPERX6CHANISALIGNEDGT;
wire [1:0] PIPERX6CHARISKGT;
wire [15:0] PIPERX6DATAGT;
wire PIPERX6ELECIDLEGT;
wire PIPERX6PHYSTATUSGT;
wire [2:0] PIPERX6STATUSGT;
wire PIPERX6VALIDGT;
wire PIPERX7CHANISALIGNEDGT;
wire [1:0] PIPERX7CHARISKGT;
wire [15:0] PIPERX7DATAGT;
wire PIPERX7ELECIDLEGT;
wire PIPERX7PHYSTATUSGT;
wire [2:0] PIPERX7STATUSGT;
wire PIPERX7VALIDGT;
wire filter_pipe_upconfig_fix_3451;
wire [63:0] TRNTD_o;
wire [5:0] TRNTBUFAV_i;
wire [63:0] TRNRD_i;
wire [6:0] TRNRBARHITN_i;
wire TRNRECRCERRN_i;
wire TRNRSOFN_i;
wire TRNREOFN_i;
wire TRNRERRFWDN_i;
wire TRNRREMN_i;
wire TRNRSRCDSCN_i;
wire TRNRSRCRDYN_i;
wire TRNTDSTRDYN_i;
wire TRNTERRDROPN_i;
wire TRNTREMN_o;
wire [11:0] TRNFCCPLD_i;
wire [7:0] TRNFCCPLH_i;
wire [11:0] TRNFCNPD_i;
wire [7:0] TRNFCNPH_i;
wire [11:0] TRNFCPD_i;
wire [7:0] TRNFCPH_i;
wire [2:0] TRNFCSEL_o;
// ---CFG---
wire [2:0] CFGDEVCONTROLMAXPAYLOAD_blk;
wire [2:0] CFGDEVCONTROLMAXREADREQ_blk;
wire [3:0] CFGDEVCONTROL2CPLTIMEOUTVAL_blk;
wire [31:0] CFGDO_blk;
wire [7:0] CFGINTERRUPTDO_blk;
wire [2:0] CFGINTERRUPTMMENABLE_blk;
wire [1:0] CFGLINKCONTROLASPMCONTROL_blk;
wire [1:0] CFGLINKSTATUSCURRENTSPEED_blk;
wire [3:0] CFGLINKSTATUSNEGOTIATEDWIDTH_blk;
wire [15:0] CFGMSGDATA_blk;
wire [2:0] CFGPCIELINKSTATE_blk;
wire [3:0] CFGBYTEENN_blk;
wire [31:0] CFGDI_blk;
wire [63:0] CFGDSN_blk;
wire [9:0] CFGDWADDR_blk;
wire [47:0] CFGERRTLPCPLHEADER_blk;
wire [7:0] CFGINTERRUPTDI_blk;
wire [7:0] CFGPORTNUMBER_blk;
wire [1:0] CFGPMCSRPOWERSTATE_blk;
wire [6:0] CFGTRANSACTIONADDR_blk;
wire TRNLNKUPN_500;
wire TRNLNKUPN_500_d;
wire TRNLNKUPN_500_250;
wire TRNLNKUPN_250_d;
FDCP #(
.INIT(1'b1)
) TRNLNKUP_500_i (
.Q (TRNLNKUPN_500),
.D (TRNLNKUPN),
.C (BLOCKCLK),
.CLR (1'b0),
.PRE (1'b0)
);
FDCP #(
.INIT(1'b1)
) TRNLNKUP_500_d_i (
.Q (TRNLNKUPN_500_d),
.D (~TRNLNKUPN_500),
.C (BLOCKCLK),
.CLR (1'b0),
.PRE (1'b0)
);
FDCP #(
.INIT(1'b1)
) TRNLNKUP_500_250_i (
.Q (TRNLNKUPN_500_250),
.D (TRNLNKUPN_500),
.C (USERCLK),
.CLR (1'b0),
.PRE (1'b0)
);
FDCP #(
.INIT(1'b1)
) TRNLNKUP_250_i (
.Q (TRNLNKUPN_250_d),
.D (~TRNLNKUPN_500_250),
.C (USERCLK),
.CLR (1'b0),
.PRE (1'b0)
);
// Assignments to outputs
assign TRNCLK = USERCLK;
//-------------------------------------------------------
// Virtex6 PCI 128bit Interface Module
//-------------------------------------------------------
pcie_128_if #(
.TCQ( TCQ )
) pcie_128_if_i (
.USERCLK( USERCLK ), // 125/250Mhz
.BLOCKCLK( BLOCKCLK ), // 250/500Mhz
.rst_n_250( TRNLNKUPN_250_d ),
.rst_n_500( TRNLNKUPN_500_d ),
//////////////////
// to/from user //
//////////////////
.trn_rbar_hit_n_o ( TRNRBARHITN ),
.trn_rd_o ( TRNRD ),
.trn_recrc_err_n_o( TRNRECRCERRN ),
.trn_rsof_n_o ( TRNRSOFN ),
.trn_reof_n_o ( TRNREOFN ),
.trn_rerrfwd_n_o ( TRNRERRFWDN ),
.trn_rrem_n_o ( TRNRREMN ),
.trn_rsrc_dsc_n_o ( TRNRSRCDSCN ),
.trn_rsrc_rdy_n_o ( TRNRSRCRDYN ),
.trn_rdst_rdy_n_i ( TRNRDSTRDYN ),
.trn_rnpok_n_i ( TRNRNPOKN ),
.trn_tbuf_av_o ( TRNTBUFAV ),
.trn_tdst_rdy_n_o ( TRNTDSTRDYN ),
.trn_terr_drop_n_o( TRNTERRDROPN ),
.trn_td_i ( TRNTD ),
.trn_tecrc_gen_n_i( TRNTECRCGENN ),
.trn_terr_fwd_n_i ( TRNTERRFWDN ),
.trn_trem_n_i ( TRNTREMN ),
.trn_tsof_n_i ( TRNTSOFN ),
.trn_teof_n_i ( TRNTEOFN ),
.trn_tsrc_dsc_n_i ( TRNTSRCDSCN ),
.trn_tsrc_rdy_n_i ( TRNTSRCRDYN ),
.trn_tstr_n_i ( TRNTSTRN ),
.trn_fc_cpld_o ( TRNFCCPLD ),
.trn_fc_cplh_o ( TRNFCCPLH ),
.trn_fc_npd_o ( TRNFCNPD ),
.trn_fc_nph_o ( TRNFCNPH ),
.trn_fc_pd_o ( TRNFCPD ),
.trn_fc_ph_o ( TRNFCPH ),
.trn_fc_sel_i ( TRNFCSEL ),
////////////////
// to/from EP //
////////////////
.TRNRBARHITN_i ( TRNRBARHITN_i ),
.TRNRD_i ( TRNRD_i ),
.TRNRECRCERRN_i ( TRNRECRCERRN_i ),
.TRNRSOFN_i ( TRNRSOFN_i ),
.TRNREOFN_i ( TRNREOFN_i ),
.TRNRERRFWDN_i ( TRNRERRFWDN_i ),
.TRNRREMN_i ( TRNRREMN_i ),
.TRNRSRCDSCN_i ( TRNRSRCDSCN_i ),
.TRNRSRCRDYN_i ( TRNRSRCRDYN_i ),
.TRNRDSTRDYN_o ( TRNRDSTRDYN_o ),
.TRNRNPOKN_o ( TRNRNPOKN_o ),
.TRNTBUFAV_i ( TRNTBUFAV_i ),
.TRNTCFGREQN_i ( TRNTCFGREQN_i ),
.TRNTDSTRDYN_i ( TRNTDSTRDYN_i ),
.TRNTERRDROPN_i ( TRNTERRDROPN_i ),
.TRNTCFGGNTN_o ( TRNTCFGGNTN_o ),
.TRNTD_o ( TRNTD_o ),
.TRNTECRCGENN_o ( TRNTECRCGENN_o ),
.TRNTERRFWDN_o ( TRNTERRFWDN_o ),
.TRNTREMN_o ( TRNTREMN_o ),
.TRNTSOFN_o ( TRNTSOFN_o ),
.TRNTEOFN_o ( TRNTEOFN_o ),
.TRNTSRCDSCN_o ( TRNTSRCDSCN_o ),
.TRNTSRCRDYN_o ( TRNTSRCRDYN_o ),
.TRNTSTRN_o ( TRNTSTRN_o ),
.TRNFCCPLD_i ( TRNFCCPLD_i ),
.TRNFCCPLH_i ( TRNFCCPLH_i ),
.TRNFCNPD_i ( TRNFCNPD_i ),
.TRNFCNPH_i ( TRNFCNPH_i ),
.TRNFCPD_i ( TRNFCPD_i ),
.TRNFCPH_i ( TRNFCPH_i ),
.TRNFCSEL_o ( TRNFCSEL_o ),
// ------------------- CFG -------------------------------
.CFGCOMMANDBUSMASTERENABLE_i( CFGCOMMANDBUSMASTERENABLE_blk ),
.CFGCOMMANDINTERRUPTDISABLE_i( CFGCOMMANDINTERRUPTDISABLE_blk ),
.CFGCOMMANDIOENABLE_i( CFGCOMMANDIOENABLE_blk ),
.CFGCOMMANDMEMENABLE_i( CFGCOMMANDMEMENABLE_blk ),
.CFGCOMMANDSERREN_i( CFGCOMMANDSERREN_blk ),
.CFGDEVCONTROLAUXPOWEREN_i( CFGDEVCONTROLAUXPOWEREN_blk ),
.CFGDEVCONTROLCORRERRREPORTINGEN_i( CFGDEVCONTROLCORRERRREPORTINGEN_blk ),
.CFGDEVCONTROLENABLERO_i( CFGDEVCONTROLENABLERO_blk ),
.CFGDEVCONTROLEXTTAGEN_i( CFGDEVCONTROLEXTTAGEN_blk ),
.CFGDEVCONTROLFATALERRREPORTINGEN_i( CFGDEVCONTROLFATALERRREPORTINGEN_blk ),
.CFGDEVCONTROLMAXPAYLOAD_i( CFGDEVCONTROLMAXPAYLOAD_blk ),
.CFGDEVCONTROLMAXREADREQ_i( CFGDEVCONTROLMAXREADREQ_blk ),
.CFGDEVCONTROLNONFATALREPORTINGEN_i( CFGDEVCONTROLNONFATALREPORTINGEN_blk ),
.CFGDEVCONTROLNOSNOOPEN_i( CFGDEVCONTROLNOSNOOPEN_blk ),
.CFGDEVCONTROLPHANTOMEN_i( CFGDEVCONTROLPHANTOMEN_blk ),
.CFGDEVCONTROLURERRREPORTINGEN_i( CFGDEVCONTROLURERRREPORTINGEN_blk ),
.CFGDEVCONTROL2CPLTIMEOUTDIS_i( CFGDEVCONTROL2CPLTIMEOUTDIS_blk ),
.CFGDEVCONTROL2CPLTIMEOUTVAL_i( CFGDEVCONTROL2CPLTIMEOUTVAL_blk ),
.CFGDEVSTATUSCORRERRDETECTED_i( CFGDEVSTATUSCORRERRDETECTED_blk ),
.CFGDEVSTATUSFATALERRDETECTED_i( CFGDEVSTATUSFATALERRDETECTED_blk ),
.CFGDEVSTATUSNONFATALERRDETECTED_i( CFGDEVSTATUSNONFATALERRDETECTED_blk ),
.CFGDEVSTATUSURDETECTED_i( CFGDEVSTATUSURDETECTED_blk ),
.CFGDO_i( CFGDO_blk ),
.CFGERRCPLRDYN_i( CFGERRCPLRDYN_blk ),
.CFGINTERRUPTDO_i( CFGINTERRUPTDO_blk ),
.CFGINTERRUPTMMENABLE_i( CFGINTERRUPTMMENABLE_blk ),
.CFGINTERRUPTMSIENABLE_i( CFGINTERRUPTMSIENABLE_blk ),
.CFGINTERRUPTMSIXENABLE_i( CFGINTERRUPTMSIXENABLE_blk ),
.CFGINTERRUPTMSIXFM_i( CFGINTERRUPTMSIXFM_blk ),
.CFGINTERRUPTRDYN_i( CFGINTERRUPTRDYN_blk ),
.CFGLINKCONTROLRCB_i( CFGLINKCONTROLRCB_blk ),
.CFGLINKCONTROLASPMCONTROL_i( CFGLINKCONTROLASPMCONTROL_blk ),
.CFGLINKCONTROLAUTOBANDWIDTHINTEN_i( CFGLINKCONTROLAUTOBANDWIDTHINTEN_blk ),
.CFGLINKCONTROLBANDWIDTHINTEN_i( CFGLINKCONTROLBANDWIDTHINTEN_blk ),
.CFGLINKCONTROLCLOCKPMEN_i( CFGLINKCONTROLCLOCKPMEN_blk ),
.CFGLINKCONTROLCOMMONCLOCK_i( CFGLINKCONTROLCOMMONCLOCK_blk ),
.CFGLINKCONTROLEXTENDEDSYNC_i( CFGLINKCONTROLEXTENDEDSYNC_blk ),
.CFGLINKCONTROLHWAUTOWIDTHDIS_i( CFGLINKCONTROLHWAUTOWIDTHDIS_blk ),
.CFGLINKCONTROLLINKDISABLE_i( CFGLINKCONTROLLINKDISABLE_blk ),
.CFGLINKCONTROLRETRAINLINK_i( CFGLINKCONTROLRETRAINLINK_blk ),
.CFGLINKSTATUSAUTOBANDWIDTHSTATUS_i( CFGLINKSTATUSAUTOBANDWIDTHSTATUS_blk ),
.CFGLINKSTATUSBANDWITHSTATUS_i( CFGLINKSTATUSBANDWITHSTATUS_blk ),
.CFGLINKSTATUSCURRENTSPEED_i( CFGLINKSTATUSCURRENTSPEED_blk ),
.CFGLINKSTATUSDLLACTIVE_i( CFGLINKSTATUSDLLACTIVE_blk ),
.CFGLINKSTATUSLINKTRAINING_i( CFGLINKSTATUSLINKTRAINING_blk ),
.CFGLINKSTATUSNEGOTIATEDWIDTH_i( CFGLINKSTATUSNEGOTIATEDWIDTH_blk ),
.CFGMSGDATA_i( CFGMSGDATA_blk ),
.CFGMSGRECEIVED_i( CFGMSGRECEIVED_blk ),
.CFGMSGRECEIVEDPMETO_i( CFGMSGRECEIVEDPMETO_blk ),
.CFGPCIELINKSTATE_i( CFGPCIELINKSTATE_blk ),
.CFGPMCSRPMEEN_i( CFGPMCSRPMEEN_blk ),
.CFGPMCSRPMESTATUS_i( CFGPMCSRPMESTATUS_blk ),
.CFGPMCSRPOWERSTATE_i( CFGPMCSRPOWERSTATE_blk ),
.CFGRDWRDONEN_i( CFGRDWRDONEN_blk ),
.CFGMSGRECEIVEDSETSLOTPOWERLIMIT_i( CFGMSGRECEIVEDSETSLOTPOWERLIMIT_blk ),
.CFGMSGRECEIVEDUNLOCK_i( CFGMSGRECEIVEDUNLOCK_blk ),
.CFGMSGRECEIVEDPMASNAK_i( CFGMSGRECEIVEDPMASNAK_blk ),
.CFGPMRCVREQACKN_i( CFGPMRCVREQACKN_blk ),
.CFGTRANSACTION_i( CFGTRANSACTION_blk ),
.CFGTRANSACTIONADDR_i( CFGTRANSACTIONADDR_blk ),
.CFGTRANSACTIONTYPE_i( CFGTRANSACTIONTYPE_blk ),
.CFGBYTEENN_o( CFGBYTEENN_blk ),
.CFGDI_o( CFGDI_blk ),
.CFGDSN_o( CFGDSN_blk ),
.CFGDWADDR_o( CFGDWADDR_blk ),
.CFGERRACSN_o( CFGERRACSN_blk ),
.CFGERRCORN_o( CFGERRCORN_blk ),
.CFGERRCPLABORTN_o( CFGERRCPLABORTN_blk ),
.CFGERRCPLTIMEOUTN_o( CFGERRCPLTIMEOUTN_blk ),
.CFGERRCPLUNEXPECTN_o( CFGERRCPLUNEXPECTN_blk ),
.CFGERRECRCN_o( CFGERRECRCN_blk ),
.CFGERRLOCKEDN_o( CFGERRLOCKEDN_blk ),
.CFGERRPOSTEDN_o( CFGERRPOSTEDN_blk ),
.CFGERRTLPCPLHEADER_o( CFGERRTLPCPLHEADER_blk ),
.CFGERRURN_o( CFGERRURN_blk ),
.CFGINTERRUPTASSERTN_o( CFGINTERRUPTASSERTN_blk ),
.CFGINTERRUPTDI_o( CFGINTERRUPTDI_blk ),
.CFGINTERRUPTN_o( CFGINTERRUPTN_blk ),
.CFGPMDIRECTASPML1N_o( CFGPMDIRECTASPML1N_blk ),
.CFGPMSENDPMACKN_o( CFGPMSENDPMACKN_blk ),
.CFGPMSENDPMETON_o( CFGPMSENDPMETON_blk ),
.CFGPMSENDPMNAKN_o( CFGPMSENDPMNAKN_blk ),
.CFGPMTURNOFFOKN_o( CFGPMTURNOFFOKN_blk ),
.CFGPMWAKEN_o( CFGPMWAKEN_blk ),
.CFGPORTNUMBER_o( CFGPORTNUMBER_blk ),
.CFGRDENN_o( CFGRDENN_blk ),
.CFGTRNPENDINGN_o( CFGTRNPENDINGN_blk ),
.CFGWRENN_o( CFGWRENN_blk ),
.CFGWRREADONLYN_o( CFGWRREADONLYN_blk ),
.CFGWRRW1CASRWN_o( CFGWRRW1CASRWN_blk ),
//---------------------------------------
.CFGCOMMANDBUSMASTERENABLE_o( CFGCOMMANDBUSMASTERENABLE ),
.CFGCOMMANDINTERRUPTDISABLE_o( CFGCOMMANDINTERRUPTDISABLE ),
.CFGCOMMANDIOENABLE_o( CFGCOMMANDIOENABLE ),
.CFGCOMMANDMEMENABLE_o( CFGCOMMANDMEMENABLE ),
.CFGCOMMANDSERREN_o( CFGCOMMANDSERREN ),
.CFGDEVCONTROLAUXPOWEREN_o( CFGDEVCONTROLAUXPOWEREN ),
.CFGDEVCONTROLCORRERRREPORTINGEN_o( CFGDEVCONTROLCORRERRREPORTINGEN ),
.CFGDEVCONTROLENABLERO_o( CFGDEVCONTROLENABLERO ),
.CFGDEVCONTROLEXTTAGEN_o( CFGDEVCONTROLEXTTAGEN ),
.CFGDEVCONTROLFATALERRREPORTINGEN_o( CFGDEVCONTROLFATALERRREPORTINGEN ),
.CFGDEVCONTROLMAXPAYLOAD_o( CFGDEVCONTROLMAXPAYLOAD ),
.CFGDEVCONTROLMAXREADREQ_o( CFGDEVCONTROLMAXREADREQ ),
.CFGDEVCONTROLNONFATALREPORTINGEN_o( CFGDEVCONTROLNONFATALREPORTINGEN ),
.CFGDEVCONTROLNOSNOOPEN_o( CFGDEVCONTROLNOSNOOPEN ),
.CFGDEVCONTROLPHANTOMEN_o( CFGDEVCONTROLPHANTOMEN ),
.CFGDEVCONTROLURERRREPORTINGEN_o( CFGDEVCONTROLURERRREPORTINGEN ),
.CFGDEVCONTROL2CPLTIMEOUTDIS_o( CFGDEVCONTROL2CPLTIMEOUTDIS ),
.CFGDEVCONTROL2CPLTIMEOUTVAL_o( CFGDEVCONTROL2CPLTIMEOUTVAL ),
.CFGDEVSTATUSCORRERRDETECTED_o( CFGDEVSTATUSCORRERRDETECTED ),
.CFGDEVSTATUSFATALERRDETECTED_o( CFGDEVSTATUSFATALERRDETECTED ),
.CFGDEVSTATUSNONFATALERRDETECTED_o( CFGDEVSTATUSNONFATALERRDETECTED ),
.CFGDEVSTATUSURDETECTED_o( CFGDEVSTATUSURDETECTED ),
.CFGDO_o( CFGDO ),
.CFGERRCPLRDYN_o( CFGERRCPLRDYN ),
.CFGINTERRUPTDO_o( CFGINTERRUPTDO ),
.CFGINTERRUPTMMENABLE_o( CFGINTERRUPTMMENABLE ),
.CFGINTERRUPTMSIENABLE_o( CFGINTERRUPTMSIENABLE ),
.CFGINTERRUPTMSIXENABLE_o( CFGINTERRUPTMSIXENABLE ),
.CFGINTERRUPTMSIXFM_o( CFGINTERRUPTMSIXFM ),
.CFGINTERRUPTRDYN_o( CFGINTERRUPTRDYN ),
.CFGLINKCONTROLRCB_o( CFGLINKCONTROLRCB ),
.CFGLINKCONTROLASPMCONTROL_o( CFGLINKCONTROLASPMCONTROL ),
.CFGLINKCONTROLAUTOBANDWIDTHINTEN_o( CFGLINKCONTROLAUTOBANDWIDTHINTEN ),
.CFGLINKCONTROLBANDWIDTHINTEN_o( CFGLINKCONTROLBANDWIDTHINTEN ),
.CFGLINKCONTROLCLOCKPMEN_o( CFGLINKCONTROLCLOCKPMEN ),
.CFGLINKCONTROLCOMMONCLOCK_o( CFGLINKCONTROLCOMMONCLOCK ),
.CFGLINKCONTROLEXTENDEDSYNC_o( CFGLINKCONTROLEXTENDEDSYNC ),
.CFGLINKCONTROLHWAUTOWIDTHDIS_o( CFGLINKCONTROLHWAUTOWIDTHDIS ),
.CFGLINKCONTROLLINKDISABLE_o( CFGLINKCONTROLLINKDISABLE ),
.CFGLINKCONTROLRETRAINLINK_o( CFGLINKCONTROLRETRAINLINK ),
.CFGLINKSTATUSAUTOBANDWIDTHSTATUS_o( CFGLINKSTATUSAUTOBANDWIDTHSTATUS ),
.CFGLINKSTATUSBANDWITHSTATUS_o( CFGLINKSTATUSBANDWITHSTATUS ),
.CFGLINKSTATUSCURRENTSPEED_o( CFGLINKSTATUSCURRENTSPEED ),
.CFGLINKSTATUSDLLACTIVE_o( CFGLINKSTATUSDLLACTIVE ),
.CFGLINKSTATUSLINKTRAINING_o( CFGLINKSTATUSLINKTRAINING ),
.CFGLINKSTATUSNEGOTIATEDWIDTH_o( CFGLINKSTATUSNEGOTIATEDWIDTH ),
.CFGMSGDATA_o( CFGMSGDATA ),
.CFGMSGRECEIVED_o( CFGMSGRECEIVED ),
.CFGMSGRECEIVEDPMETO_o( CFGMSGRECEIVEDPMETO ),
.CFGPCIELINKSTATE_o( CFGPCIELINKSTATE ),
.CFGPMCSRPMEEN_o( CFGPMCSRPMEEN ),
.CFGPMCSRPMESTATUS_o( CFGPMCSRPMESTATUS ),
.CFGPMCSRPOWERSTATE_o( CFGPMCSRPOWERSTATE ),
.CFGRDWRDONEN_o( CFGRDWRDONEN ),
.CFGMSGRECEIVEDSETSLOTPOWERLIMIT_o( CFGMSGRECEIVEDSETSLOTPOWERLIMIT ),
.CFGMSGRECEIVEDUNLOCK_o( CFGMSGRECEIVEDUNLOCK ),
.CFGMSGRECEIVEDPMASNAK_o( CFGMSGRECEIVEDPMASNAK ),
.CFGPMRCVREQACKN_o( CFGPMRCVREQACKN ),
.CFGTRANSACTION_o( CFGTRANSACTION ),
.CFGTRANSACTIONADDR_o( CFGTRANSACTIONADDR ),
.CFGTRANSACTIONTYPE_o( CFGTRANSACTIONTYPE ),
.CFGBYTEENN_i( CFGBYTEENN ),
.CFGDI_i( CFGDI ),
.CFGDSN_i( CFGDSN ),
.CFGDWADDR_i( CFGDWADDR ),
.CFGERRACSN_i( CFGERRACSN ),
.CFGERRCORN_i( CFGERRCORN ),
.CFGERRCPLABORTN_i( CFGERRCPLABORTN ),
.CFGERRCPLTIMEOUTN_i( CFGERRCPLTIMEOUTN ),
.CFGERRCPLUNEXPECTN_i( CFGERRCPLUNEXPECTN ),
.CFGERRECRCN_i( CFGERRECRCN ),
.CFGERRLOCKEDN_i( CFGERRLOCKEDN ),
.CFGERRPOSTEDN_i( CFGERRPOSTEDN ),
.CFGERRTLPCPLHEADER_i( CFGERRTLPCPLHEADER ),
.CFGERRURN_i( CFGERRURN ),
.CFGINTERRUPTASSERTN_i( CFGINTERRUPTASSERTN ),
.CFGINTERRUPTDI_i( CFGINTERRUPTDI ),
.CFGINTERRUPTN_i( CFGINTERRUPTN ),
.CFGPMDIRECTASPML1N_i( CFGPMDIRECTASPML1N ),
.CFGPMSENDPMACKN_i( CFGPMSENDPMACKN ),
.CFGPMSENDPMETON_i( CFGPMSENDPMETON ),
.CFGPMSENDPMNAKN_i( CFGPMSENDPMNAKN ),
.CFGPMTURNOFFOKN_i( CFGPMTURNOFFOKN ),
.CFGPMWAKEN_i( CFGPMWAKEN ),
.CFGPORTNUMBER_i( CFGPORTNUMBER ),
.CFGRDENN_i( CFGRDENN ),
.CFGTRNPENDINGN_i( CFGTRNPENDINGN ),
.CFGWRENN_i( CFGWRENN ),
.CFGWRREADONLYN_i( CFGWRREADONLYN ),
.CFGWRRW1CASRWN_i( CFGWRRW1CASRWN )
);
//-------------------------------------------------------
// Virtex6 PCI Express Block Module
//-------------------------------------------------------
PCIE_2_0 #(
.AER_BASE_PTR ( AER_BASE_PTR ),
.AER_CAP_ECRC_CHECK_CAPABLE ( AER_CAP_ECRC_CHECK_CAPABLE ),
.AER_CAP_ECRC_GEN_CAPABLE ( AER_CAP_ECRC_GEN_CAPABLE ),
.AER_CAP_ID ( AER_CAP_ID ),
.AER_CAP_INT_MSG_NUM_MSI ( AER_CAP_INT_MSG_NUM_MSI ),
.AER_CAP_INT_MSG_NUM_MSIX ( AER_CAP_INT_MSG_NUM_MSIX ),
.AER_CAP_NEXTPTR ( AER_CAP_NEXTPTR ),
.AER_CAP_ON ( AER_CAP_ON ),
.AER_CAP_PERMIT_ROOTERR_UPDATE ( AER_CAP_PERMIT_ROOTERR_UPDATE ),
.AER_CAP_VERSION ( AER_CAP_VERSION ),
.ALLOW_X8_GEN2 ( ALLOW_X8_GEN2 ),
.BAR0 ( BAR0 ),
.BAR1 ( BAR1 ),
.BAR2 ( BAR2 ),
.BAR3 ( BAR3 ),
.BAR4 ( BAR4 ),
.BAR5 ( BAR5 ),
.CAPABILITIES_PTR ( CAPABILITIES_PTR ),
.CARDBUS_CIS_POINTER ( CARDBUS_CIS_POINTER ),
.CLASS_CODE ( CLASS_CODE ),
.CMD_INTX_IMPLEMENTED ( CMD_INTX_IMPLEMENTED ),
.CPL_TIMEOUT_DISABLE_SUPPORTED ( CPL_TIMEOUT_DISABLE_SUPPORTED ),
.CPL_TIMEOUT_RANGES_SUPPORTED ( CPL_TIMEOUT_RANGES_SUPPORTED ),
.CRM_MODULE_RSTS ( CRM_MODULE_RSTS ),
.DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE ( DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE ),
.DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE ( DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE ),
.DEV_CAP_ENDPOINT_L0S_LATENCY ( DEV_CAP_ENDPOINT_L0S_LATENCY ),
.DEV_CAP_ENDPOINT_L1_LATENCY ( DEV_CAP_ENDPOINT_L1_LATENCY ),
.DEV_CAP_EXT_TAG_SUPPORTED ( DEV_CAP_EXT_TAG_SUPPORTED ),
.DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE ( DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE ),
.DEV_CAP_MAX_PAYLOAD_SUPPORTED ( DEV_CAP_MAX_PAYLOAD_SUPPORTED ),
.DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT ( DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT ),
.DEV_CAP_ROLE_BASED_ERROR ( DEV_CAP_ROLE_BASED_ERROR ),
.DEV_CAP_RSVD_14_12 ( DEV_CAP_RSVD_14_12 ),
.DEV_CAP_RSVD_17_16 ( DEV_CAP_RSVD_17_16 ),
.DEV_CAP_RSVD_31_29 ( DEV_CAP_RSVD_31_29 ),
.DEV_CONTROL_AUX_POWER_SUPPORTED ( DEV_CONTROL_AUX_POWER_SUPPORTED ),
.DEVICE_ID ( DEVICE_ID ),
.DISABLE_ASPM_L1_TIMER ( DISABLE_ASPM_L1_TIMER ),
.DISABLE_BAR_FILTERING ( DISABLE_BAR_FILTERING ),
.DISABLE_ID_CHECK ( DISABLE_ID_CHECK ),
.DISABLE_LANE_REVERSAL ( DISABLE_LANE_REVERSAL ),
.DISABLE_RX_TC_FILTER ( DISABLE_RX_TC_FILTER ),
.DISABLE_SCRAMBLING ( DISABLE_SCRAMBLING ),
.DNSTREAM_LINK_NUM ( DNSTREAM_LINK_NUM ),
.DSN_BASE_PTR ( DSN_BASE_PTR ),
.DSN_CAP_ID ( DSN_CAP_ID ),
.DSN_CAP_NEXTPTR ( DSN_CAP_NEXTPTR ),
.DSN_CAP_ON ( DSN_CAP_ON ),
.DSN_CAP_VERSION ( DSN_CAP_VERSION ),
.ENABLE_MSG_ROUTE ( ENABLE_MSG_ROUTE ),
.ENABLE_RX_TD_ECRC_TRIM ( ENABLE_RX_TD_ECRC_TRIM ),
.ENTER_RVRY_EI_L0 ( ENTER_RVRY_EI_L0 ),
.EXPANSION_ROM ( EXPANSION_ROM ),
.EXT_CFG_CAP_PTR ( EXT_CFG_CAP_PTR ),
.EXT_CFG_XP_CAP_PTR ( EXT_CFG_XP_CAP_PTR ),
.HEADER_TYPE ( HEADER_TYPE ),
.INFER_EI ( INFER_EI ),
.INTERRUPT_PIN ( INTERRUPT_PIN ),
.IS_SWITCH ( IS_SWITCH ),
.LAST_CONFIG_DWORD ( LAST_CONFIG_DWORD ),
.LINK_CAP_ASPM_SUPPORT ( LINK_CAP_ASPM_SUPPORT ),
.LINK_CAP_CLOCK_POWER_MANAGEMENT ( LINK_CAP_CLOCK_POWER_MANAGEMENT ),
.LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP ( LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP ),
.LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP ( LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP ),
.LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 ( LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 ),
.LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 ( LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 ),
.LINK_CAP_L0S_EXIT_LATENCY_GEN1 ( LINK_CAP_L0S_EXIT_LATENCY_GEN1 ),
.LINK_CAP_L0S_EXIT_LATENCY_GEN2 ( LINK_CAP_L0S_EXIT_LATENCY_GEN2 ),
.LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 ( LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 ),
.LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 ( LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 ),
.LINK_CAP_L1_EXIT_LATENCY_GEN1 ( LINK_CAP_L1_EXIT_LATENCY_GEN1 ),
.LINK_CAP_L1_EXIT_LATENCY_GEN2 ( LINK_CAP_L1_EXIT_LATENCY_GEN2 ),
.LINK_CAP_MAX_LINK_SPEED ( LINK_CAP_MAX_LINK_SPEED ),
.LINK_CAP_MAX_LINK_WIDTH ( LINK_CAP_MAX_LINK_WIDTH ),
.LINK_CAP_RSVD_23_22 ( LINK_CAP_RSVD_23_22 ),
.LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE ( LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE ),
.LINK_CONTROL_RCB ( LINK_CONTROL_RCB ),
.LINK_CTRL2_DEEMPHASIS ( LINK_CTRL2_DEEMPHASIS ),
.LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE ( LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE ),
.LINK_CTRL2_TARGET_LINK_SPEED ( LINK_CTRL2_TARGET_LINK_SPEED ),
.LINK_STATUS_SLOT_CLOCK_CONFIG ( LINK_STATUS_SLOT_CLOCK_CONFIG ),
.LL_ACK_TIMEOUT ( LL_ACK_TIMEOUT ),
.LL_ACK_TIMEOUT_EN ( LL_ACK_TIMEOUT_EN ),
.LL_ACK_TIMEOUT_FUNC ( LL_ACK_TIMEOUT_FUNC ),
.LL_REPLAY_TIMEOUT ( LL_REPLAY_TIMEOUT ),
.LL_REPLAY_TIMEOUT_EN ( LL_REPLAY_TIMEOUT_EN ),
.LL_REPLAY_TIMEOUT_FUNC ( LL_REPLAY_TIMEOUT_FUNC ),
.LTSSM_MAX_LINK_WIDTH ( LTSSM_MAX_LINK_WIDTH ),
.MSI_BASE_PTR ( MSI_BASE_PTR ),
.MSI_CAP_ID ( MSI_CAP_ID ),
.MSI_CAP_MULTIMSGCAP ( MSI_CAP_MULTIMSGCAP ),
.MSI_CAP_MULTIMSG_EXTENSION ( MSI_CAP_MULTIMSG_EXTENSION ),
.MSI_CAP_NEXTPTR ( MSI_CAP_NEXTPTR ),
.MSI_CAP_ON ( MSI_CAP_ON ),
.MSI_CAP_PER_VECTOR_MASKING_CAPABLE ( MSI_CAP_PER_VECTOR_MASKING_CAPABLE ),
.MSI_CAP_64_BIT_ADDR_CAPABLE ( MSI_CAP_64_BIT_ADDR_CAPABLE ),
.MSIX_BASE_PTR ( MSIX_BASE_PTR ),
.MSIX_CAP_ID ( MSIX_CAP_ID ),
.MSIX_CAP_NEXTPTR ( MSIX_CAP_NEXTPTR ),
.MSIX_CAP_ON ( MSIX_CAP_ON ),
.MSIX_CAP_PBA_BIR ( MSIX_CAP_PBA_BIR ),
.MSIX_CAP_PBA_OFFSET ( MSIX_CAP_PBA_OFFSET ),
.MSIX_CAP_TABLE_BIR ( MSIX_CAP_TABLE_BIR ),
.MSIX_CAP_TABLE_OFFSET ( MSIX_CAP_TABLE_OFFSET ),
.MSIX_CAP_TABLE_SIZE ( MSIX_CAP_TABLE_SIZE ),
.N_FTS_COMCLK_GEN1 ( N_FTS_COMCLK_GEN1 ),
.N_FTS_COMCLK_GEN2 ( N_FTS_COMCLK_GEN2 ),
.N_FTS_GEN1 ( N_FTS_GEN1 ),
.N_FTS_GEN2 ( N_FTS_GEN2 ),
.PCIE_BASE_PTR ( PCIE_BASE_PTR ),
.PCIE_CAP_CAPABILITY_ID ( PCIE_CAP_CAPABILITY_ID ),
.PCIE_CAP_CAPABILITY_VERSION ( PCIE_CAP_CAPABILITY_VERSION ),
.PCIE_CAP_DEVICE_PORT_TYPE ( PCIE_CAP_DEVICE_PORT_TYPE ),
.PCIE_CAP_INT_MSG_NUM ( PCIE_CAP_INT_MSG_NUM ),
.PCIE_CAP_NEXTPTR ( PCIE_CAP_NEXTPTR ),
.PCIE_CAP_ON ( PCIE_CAP_ON ),
.PCIE_CAP_RSVD_15_14 ( PCIE_CAP_RSVD_15_14 ),
.PCIE_CAP_SLOT_IMPLEMENTED ( PCIE_CAP_SLOT_IMPLEMENTED ),
.PCIE_REVISION ( PCIE_REVISION ),
.PGL0_LANE ( PGL0_LANE ),
.PGL1_LANE ( PGL1_LANE ),
.PGL2_LANE ( PGL2_LANE ),
.PGL3_LANE ( PGL3_LANE ),
.PGL4_LANE ( PGL4_LANE ),
.PGL5_LANE ( PGL5_LANE ),
.PGL6_LANE ( PGL6_LANE ),
.PGL7_LANE ( PGL7_LANE ),
.PL_AUTO_CONFIG ( PL_AUTO_CONFIG ),
.PL_FAST_TRAIN ( PL_FAST_TRAIN ),
.PM_BASE_PTR ( PM_BASE_PTR ),
.PM_CAP_AUXCURRENT ( PM_CAP_AUXCURRENT ),
.PM_CAP_DSI ( PM_CAP_DSI ),
.PM_CAP_D1SUPPORT ( PM_CAP_D1SUPPORT ),
.PM_CAP_D2SUPPORT ( PM_CAP_D2SUPPORT ),
.PM_CAP_ID ( PM_CAP_ID ),
.PM_CAP_NEXTPTR ( PM_CAP_NEXTPTR ),
.PM_CAP_ON ( PM_CAP_ON ),
.PM_CAP_PME_CLOCK ( PM_CAP_PME_CLOCK ),
.PM_CAP_PMESUPPORT ( PM_CAP_PMESUPPORT ),
.PM_CAP_RSVD_04 ( PM_CAP_RSVD_04 ),
.PM_CAP_VERSION ( PM_CAP_VERSION ),
.PM_CSR_BPCCEN ( PM_CSR_BPCCEN ),
.PM_CSR_B2B3 ( PM_CSR_B2B3 ),
.PM_CSR_NOSOFTRST ( PM_CSR_NOSOFTRST ),
.PM_DATA_SCALE0 ( PM_DATA_SCALE0 ),
.PM_DATA_SCALE1 ( PM_DATA_SCALE1 ),
.PM_DATA_SCALE2 ( PM_DATA_SCALE2 ),
.PM_DATA_SCALE3 ( PM_DATA_SCALE3 ),
.PM_DATA_SCALE4 ( PM_DATA_SCALE4 ),
.PM_DATA_SCALE5 ( PM_DATA_SCALE5 ),
.PM_DATA_SCALE6 ( PM_DATA_SCALE6 ),
.PM_DATA_SCALE7 ( PM_DATA_SCALE7 ),
.PM_DATA0 ( PM_DATA0 ),
.PM_DATA1 ( PM_DATA1 ),
.PM_DATA2 ( PM_DATA2 ),
.PM_DATA3 ( PM_DATA3 ),
.PM_DATA4 ( PM_DATA4 ),
.PM_DATA5 ( PM_DATA5 ),
.PM_DATA6 ( PM_DATA6 ),
.PM_DATA7 ( PM_DATA7 ),
.RECRC_CHK ( RECRC_CHK ),
.RECRC_CHK_TRIM ( RECRC_CHK_TRIM ),
.REVISION_ID ( REVISION_ID ),
.ROOT_CAP_CRS_SW_VISIBILITY ( ROOT_CAP_CRS_SW_VISIBILITY ),
.SELECT_DLL_IF ( SELECT_DLL_IF ),
.SLOT_CAP_ATT_BUTTON_PRESENT ( SLOT_CAP_ATT_BUTTON_PRESENT ),
.SLOT_CAP_ATT_INDICATOR_PRESENT ( SLOT_CAP_ATT_INDICATOR_PRESENT ),
.SLOT_CAP_ELEC_INTERLOCK_PRESENT ( SLOT_CAP_ELEC_INTERLOCK_PRESENT ),
.SLOT_CAP_HOTPLUG_CAPABLE ( SLOT_CAP_HOTPLUG_CAPABLE ),
.SLOT_CAP_HOTPLUG_SURPRISE ( SLOT_CAP_HOTPLUG_SURPRISE ),
.SLOT_CAP_MRL_SENSOR_PRESENT ( SLOT_CAP_MRL_SENSOR_PRESENT ),
.SLOT_CAP_NO_CMD_COMPLETED_SUPPORT ( SLOT_CAP_NO_CMD_COMPLETED_SUPPORT ),
.SLOT_CAP_PHYSICAL_SLOT_NUM ( SLOT_CAP_PHYSICAL_SLOT_NUM ),
.SLOT_CAP_POWER_CONTROLLER_PRESENT ( SLOT_CAP_POWER_CONTROLLER_PRESENT ),
.SLOT_CAP_POWER_INDICATOR_PRESENT ( SLOT_CAP_POWER_INDICATOR_PRESENT ),
.SLOT_CAP_SLOT_POWER_LIMIT_SCALE ( SLOT_CAP_SLOT_POWER_LIMIT_SCALE ),
.SLOT_CAP_SLOT_POWER_LIMIT_VALUE ( SLOT_CAP_SLOT_POWER_LIMIT_VALUE ),
.SPARE_BIT0 ( SPARE_BIT0 ),
.SPARE_BIT1 ( SPARE_BIT1 ),
.SPARE_BIT2 ( SPARE_BIT2 ),
.SPARE_BIT3 ( SPARE_BIT3 ),
.SPARE_BIT4 ( SPARE_BIT4 ),
.SPARE_BIT5 ( SPARE_BIT5 ),
.SPARE_BIT6 ( SPARE_BIT6 ),
.SPARE_BIT7 ( SPARE_BIT7 ),
.SPARE_BIT8 ( SPARE_BIT8 ),
.SPARE_BYTE0 ( SPARE_BYTE0 ),
.SPARE_BYTE1 ( SPARE_BYTE1 ),
.SPARE_BYTE2 ( SPARE_BYTE2 ),
.SPARE_BYTE3 ( SPARE_BYTE3 ),
.SPARE_WORD0 ( SPARE_WORD0 ),
.SPARE_WORD1 ( SPARE_WORD1 ),
.SPARE_WORD2 ( SPARE_WORD2 ),
.SPARE_WORD3 ( SPARE_WORD3 ),
.SUBSYSTEM_ID ( SUBSYSTEM_ID ),
.SUBSYSTEM_VENDOR_ID ( SUBSYSTEM_VENDOR_ID ),
.TL_RBYPASS ( TL_RBYPASS ),
.TL_RX_RAM_RADDR_LATENCY ( TL_RX_RAM_RADDR_LATENCY ),
.TL_RX_RAM_RDATA_LATENCY ( TL_RX_RAM_RDATA_LATENCY ),
.TL_RX_RAM_WRITE_LATENCY ( TL_RX_RAM_WRITE_LATENCY ),
.TL_TFC_DISABLE ( TL_TFC_DISABLE ),
.TL_TX_CHECKS_DISABLE ( TL_TX_CHECKS_DISABLE ),
.TL_TX_RAM_RADDR_LATENCY ( TL_TX_RAM_RADDR_LATENCY ),
.TL_TX_RAM_RDATA_LATENCY ( TL_TX_RAM_RDATA_LATENCY ),
.TL_TX_RAM_WRITE_LATENCY ( TL_TX_RAM_WRITE_LATENCY ),
.UPCONFIG_CAPABLE ( UPCONFIG_CAPABLE ),
.UPSTREAM_FACING ( UPSTREAM_FACING ),
.EXIT_LOOPBACK_ON_EI ( EXIT_LOOPBACK_ON_EI ),
.UR_INV_REQ ( UR_INV_REQ ),
.USER_CLK_FREQ ( USER_CLK_FREQ ),
.VC_BASE_PTR ( VC_BASE_PTR ),
.VC_CAP_ID ( VC_CAP_ID ),
.VC_CAP_NEXTPTR ( VC_CAP_NEXTPTR ),
.VC_CAP_ON ( VC_CAP_ON ),
.VC_CAP_REJECT_SNOOP_TRANSACTIONS ( VC_CAP_REJECT_SNOOP_TRANSACTIONS ),
.VC_CAP_VERSION ( VC_CAP_VERSION ),
.VC0_CPL_INFINITE ( VC0_CPL_INFINITE ),
.VC0_RX_RAM_LIMIT ( VC0_RX_RAM_LIMIT ),
.VC0_TOTAL_CREDITS_CD ( VC0_TOTAL_CREDITS_CD ),
.VC0_TOTAL_CREDITS_CH ( VC0_TOTAL_CREDITS_CH ),
.VC0_TOTAL_CREDITS_NPH ( VC0_TOTAL_CREDITS_NPH ),
.VC0_TOTAL_CREDITS_PD ( VC0_TOTAL_CREDITS_PD ),
.VC0_TOTAL_CREDITS_PH ( VC0_TOTAL_CREDITS_PH ),
.VC0_TX_LASTPACKET ( VC0_TX_LASTPACKET ),
.VENDOR_ID ( VENDOR_ID ),
.VSEC_BASE_PTR ( VSEC_BASE_PTR ),
.VSEC_CAP_HDR_ID ( VSEC_CAP_HDR_ID ),
.VSEC_CAP_HDR_LENGTH ( VSEC_CAP_HDR_LENGTH ),
.VSEC_CAP_HDR_REVISION ( VSEC_CAP_HDR_REVISION ),
.VSEC_CAP_ID ( VSEC_CAP_ID ),
.VSEC_CAP_IS_LINK_VISIBLE ( VSEC_CAP_IS_LINK_VISIBLE ),
.VSEC_CAP_NEXTPTR ( VSEC_CAP_NEXTPTR ),
.VSEC_CAP_ON ( VSEC_CAP_ON ),
.VSEC_CAP_VERSION ( VSEC_CAP_VERSION )
)
pcie_block_i (
.CFGAERECRCCHECKEN ( CFGAERECRCCHECKEN ),
.CFGAERECRCGENEN ( CFGAERECRCGENEN ),
.CFGCOMMANDBUSMASTERENABLE ( CFGCOMMANDBUSMASTERENABLE_blk ),
.CFGCOMMANDINTERRUPTDISABLE ( CFGCOMMANDINTERRUPTDISABLE_blk ),
.CFGCOMMANDIOENABLE ( CFGCOMMANDIOENABLE_blk ),
.CFGCOMMANDMEMENABLE ( CFGCOMMANDMEMENABLE_blk ),
.CFGCOMMANDSERREN ( CFGCOMMANDSERREN_blk ),
.CFGDEVCONTROLAUXPOWEREN ( CFGDEVCONTROLAUXPOWEREN_blk ),
.CFGDEVCONTROLCORRERRREPORTINGEN ( CFGDEVCONTROLCORRERRREPORTINGEN_blk ),
.CFGDEVCONTROLENABLERO ( CFGDEVCONTROLENABLERO_blk ),
.CFGDEVCONTROLEXTTAGEN ( CFGDEVCONTROLEXTTAGEN_blk ),
.CFGDEVCONTROLFATALERRREPORTINGEN ( CFGDEVCONTROLFATALERRREPORTINGEN_blk ),
.CFGDEVCONTROLMAXPAYLOAD ( CFGDEVCONTROLMAXPAYLOAD_blk ),
.CFGDEVCONTROLMAXREADREQ ( CFGDEVCONTROLMAXREADREQ_blk ),
.CFGDEVCONTROLNONFATALREPORTINGEN ( CFGDEVCONTROLNONFATALREPORTINGEN_blk ),
.CFGDEVCONTROLNOSNOOPEN ( CFGDEVCONTROLNOSNOOPEN_blk ),
.CFGDEVCONTROLPHANTOMEN ( CFGDEVCONTROLPHANTOMEN_blk ),
.CFGDEVCONTROLURERRREPORTINGEN ( CFGDEVCONTROLURERRREPORTINGEN_blk ),
.CFGDEVCONTROL2CPLTIMEOUTDIS ( CFGDEVCONTROL2CPLTIMEOUTDIS_blk ),
.CFGDEVCONTROL2CPLTIMEOUTVAL ( CFGDEVCONTROL2CPLTIMEOUTVAL_blk ),
.CFGDEVSTATUSCORRERRDETECTED ( CFGDEVSTATUSCORRERRDETECTED_blk ),
.CFGDEVSTATUSFATALERRDETECTED ( CFGDEVSTATUSFATALERRDETECTED_blk ),
.CFGDEVSTATUSNONFATALERRDETECTED ( CFGDEVSTATUSNONFATALERRDETECTED_blk ),
.CFGDEVSTATUSURDETECTED ( CFGDEVSTATUSURDETECTED_blk ),
.CFGDO ( CFGDO_blk ),
.CFGERRAERHEADERLOGSETN ( CFGERRAERHEADERLOGSETN ),
.CFGERRCPLRDYN ( CFGERRCPLRDYN_blk ),
.CFGINTERRUPTDO ( CFGINTERRUPTDO_blk ),
.CFGINTERRUPTMMENABLE ( CFGINTERRUPTMMENABLE_blk ),
.CFGINTERRUPTMSIENABLE ( CFGINTERRUPTMSIENABLE_blk ),
.CFGINTERRUPTMSIXENABLE ( CFGINTERRUPTMSIXENABLE_blk ),
.CFGINTERRUPTMSIXFM ( CFGINTERRUPTMSIXFM_blk ),
.CFGINTERRUPTRDYN ( CFGINTERRUPTRDYN_blk ),
.CFGLINKCONTROLRCB ( CFGLINKCONTROLRCB_blk ),
.CFGLINKCONTROLASPMCONTROL ( CFGLINKCONTROLASPMCONTROL_blk ),
.CFGLINKCONTROLAUTOBANDWIDTHINTEN ( CFGLINKCONTROLAUTOBANDWIDTHINTEN_blk ),
.CFGLINKCONTROLBANDWIDTHINTEN ( CFGLINKCONTROLBANDWIDTHINTEN_blk ),
.CFGLINKCONTROLCLOCKPMEN ( CFGLINKCONTROLCLOCKPMEN_blk ),
.CFGLINKCONTROLCOMMONCLOCK ( CFGLINKCONTROLCOMMONCLOCK_blk ),
.CFGLINKCONTROLEXTENDEDSYNC ( CFGLINKCONTROLEXTENDEDSYNC_blk ),
.CFGLINKCONTROLHWAUTOWIDTHDIS ( CFGLINKCONTROLHWAUTOWIDTHDIS_blk ),
.CFGLINKCONTROLLINKDISABLE ( CFGLINKCONTROLLINKDISABLE_blk ),
.CFGLINKCONTROLRETRAINLINK ( CFGLINKCONTROLRETRAINLINK_blk ),
.CFGLINKSTATUSAUTOBANDWIDTHSTATUS ( CFGLINKSTATUSAUTOBANDWIDTHSTATUS_blk ),
.CFGLINKSTATUSBANDWITHSTATUS ( CFGLINKSTATUSBANDWITHSTATUS_blk ),
.CFGLINKSTATUSCURRENTSPEED ( CFGLINKSTATUSCURRENTSPEED_blk ),
.CFGLINKSTATUSDLLACTIVE ( CFGLINKSTATUSDLLACTIVE_blk ),
.CFGLINKSTATUSLINKTRAINING ( CFGLINKSTATUSLINKTRAINING_blk ),
.CFGLINKSTATUSNEGOTIATEDWIDTH ( CFGLINKSTATUSNEGOTIATEDWIDTH_blk ),
.CFGMSGDATA ( CFGMSGDATA_blk ),
.CFGMSGRECEIVED ( CFGMSGRECEIVED_blk ),
.CFGMSGRECEIVEDASSERTINTA ( CFGMSGRECEIVEDASSERTINTA ),
.CFGMSGRECEIVEDASSERTINTB ( CFGMSGRECEIVEDASSERTINTB ),
.CFGMSGRECEIVEDASSERTINTC ( CFGMSGRECEIVEDASSERTINTC ),
.CFGMSGRECEIVEDASSERTINTD ( CFGMSGRECEIVEDASSERTINTD ),
.CFGMSGRECEIVEDDEASSERTINTA ( CFGMSGRECEIVEDDEASSERTINTA ),
.CFGMSGRECEIVEDDEASSERTINTB ( CFGMSGRECEIVEDDEASSERTINTB ),
.CFGMSGRECEIVEDDEASSERTINTC ( CFGMSGRECEIVEDDEASSERTINTC ),
.CFGMSGRECEIVEDDEASSERTINTD ( CFGMSGRECEIVEDDEASSERTINTD ),
.CFGMSGRECEIVEDERRCOR ( CFGMSGRECEIVEDERRCOR ),
.CFGMSGRECEIVEDERRFATAL ( CFGMSGRECEIVEDERRFATAL ),
.CFGMSGRECEIVEDERRNONFATAL ( CFGMSGRECEIVEDERRNONFATAL ),
.CFGMSGRECEIVEDPMASNAK ( CFGMSGRECEIVEDPMASNAK_blk ),
.CFGMSGRECEIVEDPMETO ( CFGMSGRECEIVEDPMETO_blk ),
.CFGMSGRECEIVEDPMETOACK ( CFGMSGRECEIVEDPMETOACK ),
.CFGMSGRECEIVEDPMPME ( CFGMSGRECEIVEDPMPME ),
.CFGMSGRECEIVEDSETSLOTPOWERLIMIT ( CFGMSGRECEIVEDSETSLOTPOWERLIMIT_blk ),
.CFGMSGRECEIVEDUNLOCK ( CFGMSGRECEIVEDUNLOCK_blk ),
.CFGPCIELINKSTATE ( CFGPCIELINKSTATE_blk ),
.CFGPMRCVASREQL1N ( CFGPMRCVASREQL1N ),
.CFGPMRCVENTERL1N ( CFGPMRCVENTERL1N ),
.CFGPMRCVENTERL23N ( CFGPMRCVENTERL23N ),
.CFGPMRCVREQACKN ( CFGPMRCVREQACKN_blk ),
.CFGPMCSRPMEEN( CFGPMCSRPMEEN_blk ),
.CFGPMCSRPMESTATUS( CFGPMCSRPMESTATUS_blk ),
.CFGPMCSRPOWERSTATE( CFGPMCSRPOWERSTATE_blk ),
.CFGRDWRDONEN ( CFGRDWRDONEN_blk ),
.CFGSLOTCONTROLELECTROMECHILCTLPULSE ( CFGSLOTCONTROLELECTROMECHILCTLPULSE ),
.CFGTRANSACTION ( CFGTRANSACTION_blk ),
.CFGTRANSACTIONADDR ( CFGTRANSACTIONADDR_blk ),
.CFGTRANSACTIONTYPE ( CFGTRANSACTIONTYPE_blk ),
.CFGVCTCVCMAP ( CFGVCTCVCMAP ),
.DBGSCLRA ( DBGSCLRA ),
.DBGSCLRB ( DBGSCLRB ),
.DBGSCLRC ( DBGSCLRC ),
.DBGSCLRD ( DBGSCLRD ),
.DBGSCLRE ( DBGSCLRE ),
.DBGSCLRF ( DBGSCLRF ),
.DBGSCLRG ( DBGSCLRG ),
.DBGSCLRH ( DBGSCLRH ),
.DBGSCLRI ( DBGSCLRI ),
.DBGSCLRJ ( DBGSCLRJ ),
.DBGSCLRK ( DBGSCLRK ),
.DBGVECA ( DBGVECA ),
.DBGVECB ( DBGVECB ),
.DBGVECC ( DBGVECC ),
.DRPDO ( PCIEDRPDO ),
.DRPDRDY ( PCIEDRPDRDY ),
.LL2BADDLLPERRN ( LL2BADDLLPERRN ),
.LL2BADTLPERRN ( LL2BADTLPERRN ),
.LL2PROTOCOLERRN ( LL2PROTOCOLERRN ),
.LL2REPLAYROERRN ( LL2REPLAYROERRN ),
.LL2REPLAYTOERRN ( LL2REPLAYTOERRN ),
.LL2SUSPENDOKN ( LL2SUSPENDOKN ),
.LL2TFCINIT1SEQN ( LL2TFCINIT1SEQN ),
.LL2TFCINIT2SEQN ( LL2TFCINIT2SEQN ),
.MIMRXRADDR ( MIMRXRADDR ),
.MIMRXRCE ( MIMRXRCE ),
.MIMRXREN ( MIMRXREN ),
.MIMRXWADDR ( MIMRXWADDR ),
.MIMRXWDATA ( MIMRXWDATA ),
.MIMRXWEN ( MIMRXWEN ),
.MIMTXRADDR ( MIMTXRADDR ),
.MIMTXRCE ( MIMTXRCE ),
.MIMTXREN ( MIMTXREN ),
.MIMTXWADDR ( MIMTXWADDR ),
.MIMTXWDATA ( MIMTXWDATA ),
.MIMTXWEN ( MIMTXWEN ),
.PIPERX0POLARITY ( PIPERX0POLARITY ),
.PIPERX1POLARITY ( PIPERX1POLARITY ),
.PIPERX2POLARITY ( PIPERX2POLARITY ),
.PIPERX3POLARITY ( PIPERX3POLARITY ),
.PIPERX4POLARITY ( PIPERX4POLARITY ),
.PIPERX5POLARITY ( PIPERX5POLARITY ),
.PIPERX6POLARITY ( PIPERX6POLARITY ),
.PIPERX7POLARITY ( PIPERX7POLARITY ),
.PIPETXDEEMPH ( PIPETXDEEMPH ),
.PIPETXMARGIN ( PIPETXMARGIN ),
.PIPETXRATE ( PIPETXRATE ),
.PIPETXRCVRDET ( PIPETXRCVRDET ),
.PIPETXRESET ( PIPETXRESET ),
.PIPETX0CHARISK ( PIPETX0CHARISK ),
.PIPETX0COMPLIANCE ( PIPETX0COMPLIANCE ),
.PIPETX0DATA ( PIPETX0DATA ),
.PIPETX0ELECIDLE ( PIPETX0ELECIDLE ),
.PIPETX0POWERDOWN ( PIPETX0POWERDOWN ),
.PIPETX1CHARISK ( PIPETX1CHARISK ),
.PIPETX1COMPLIANCE ( PIPETX1COMPLIANCE ),
.PIPETX1DATA ( PIPETX1DATA ),
.PIPETX1ELECIDLE ( PIPETX1ELECIDLE ),
.PIPETX1POWERDOWN ( PIPETX1POWERDOWN ),
.PIPETX2CHARISK ( PIPETX2CHARISK ),
.PIPETX2COMPLIANCE ( PIPETX2COMPLIANCE ),
.PIPETX2DATA ( PIPETX2DATA ),
.PIPETX2ELECIDLE ( PIPETX2ELECIDLE ),
.PIPETX2POWERDOWN ( PIPETX2POWERDOWN ),
.PIPETX3CHARISK ( PIPETX3CHARISK ),
.PIPETX3COMPLIANCE ( PIPETX3COMPLIANCE ),
.PIPETX3DATA ( PIPETX3DATA ),
.PIPETX3ELECIDLE ( PIPETX3ELECIDLE ),
.PIPETX3POWERDOWN ( PIPETX3POWERDOWN ),
.PIPETX4CHARISK ( PIPETX4CHARISK ),
.PIPETX4COMPLIANCE ( PIPETX4COMPLIANCE ),
.PIPETX4DATA ( PIPETX4DATA ),
.PIPETX4ELECIDLE ( PIPETX4ELECIDLE ),
.PIPETX4POWERDOWN ( PIPETX4POWERDOWN ),
.PIPETX5CHARISK ( PIPETX5CHARISK ),
.PIPETX5COMPLIANCE ( PIPETX5COMPLIANCE ),
.PIPETX5DATA ( PIPETX5DATA ),
.PIPETX5ELECIDLE ( PIPETX5ELECIDLE ),
.PIPETX5POWERDOWN ( PIPETX5POWERDOWN ),
.PIPETX6CHARISK ( PIPETX6CHARISK ),
.PIPETX6COMPLIANCE ( PIPETX6COMPLIANCE ),
.PIPETX6DATA ( PIPETX6DATA ),
.PIPETX6ELECIDLE ( PIPETX6ELECIDLE ),
.PIPETX6POWERDOWN ( PIPETX6POWERDOWN ),
.PIPETX7CHARISK ( PIPETX7CHARISK ),
.PIPETX7COMPLIANCE ( PIPETX7COMPLIANCE ),
.PIPETX7DATA ( PIPETX7DATA ),
.PIPETX7ELECIDLE ( PIPETX7ELECIDLE ),
.PIPETX7POWERDOWN ( PIPETX7POWERDOWN ),
.PLDBGVEC ( PLDBGVEC ),
.PLINITIALLINKWIDTH ( PLINITIALLINKWIDTH ),
.PLLANEREVERSALMODE ( PLLANEREVERSALMODE ),
.PLLINKGEN2CAP ( PLLINKGEN2CAP ),
.PLLINKPARTNERGEN2SUPPORTED ( PLLINKPARTNERGEN2SUPPORTED ),
.PLLINKUPCFGCAP ( PLLINKUPCFGCAP ),
.PLLTSSMSTATE ( PLLTSSMSTATE ),
.PLPHYLNKUPN ( PLPHYLNKUPN ),
.PLRECEIVEDHOTRST ( PLRECEIVEDHOTRST ),
.PLRXPMSTATE ( PLRXPMSTATE ),
.PLSELLNKRATE ( PLSELLNKRATE ),
.PLSELLNKWIDTH ( PLSELLNKWIDTH ),
.PLTXPMSTATE ( PLTXPMSTATE ),
.PL2LINKUPN ( PL2LINKUPN ),
.PL2RECEIVERERRN ( PL2RECEIVERERRN ),
.PL2RECOVERYN ( PL2RECOVERYN ),
.PL2RXELECIDLE ( PL2RXELECIDLE ),
.PL2SUSPENDOK ( PL2SUSPENDOK ),
.RECEIVEDFUNCLVLRSTN ( RECEIVEDFUNCLVLRSTN ),
.LNKCLKEN ( LNKCLKEN ),
.TL2ASPMSUSPENDCREDITCHECKOKN ( TL2ASPMSUSPENDCREDITCHECKOKN ),
.TL2ASPMSUSPENDREQN ( TL2ASPMSUSPENDREQN ),
.TL2PPMSUSPENDOKN ( TL2PPMSUSPENDOKN ),
.TRNFCCPLD ( TRNFCCPLD_i ),
.TRNFCCPLH ( TRNFCCPLH_i ),
.TRNFCNPD ( TRNFCNPD_i ),
.TRNFCNPH ( TRNFCNPH_i ),
.TRNFCPD ( TRNFCPD_i ),
.TRNFCPH ( TRNFCPH_i ),
.TRNLNKUPN ( TRNLNKUPN ),
.TRNRBARHITN ( TRNRBARHITN_i ),
.TRNRD ( TRNRD_i ),
.TRNRDLLPDATA ( ),
.TRNRDLLPSRCRDYN ( TRNRDLLPSRCRDYN ),
.TRNRECRCERRN ( TRNRECRCERRN_i ),
.TRNREOFN ( TRNREOFN_i ),
.TRNRERRFWDN ( TRNRERRFWDN_i ),
.TRNRREMN ( TRNRREMN_i ),
.TRNRSOFN ( TRNRSOFN_i ),
.TRNRSRCDSCN ( TRNRSRCDSCN_i ),
.TRNRSRCRDYN ( TRNRSRCRDYN_i ),
.TRNTBUFAV ( TRNTBUFAV_i ),
.TRNTCFGREQN ( TRNTCFGREQN_i ),
.TRNTDLLPDSTRDYN ( TRNTDLLPDSTRDYN ),
.TRNTDSTRDYN ( TRNTDSTRDYN_i ),
.TRNTERRDROPN ( TRNTERRDROPN_i ),
.USERRSTN ( USERRSTN ),
.CFGBYTEENN ( CFGBYTEENN_blk ),
.CFGDI ( CFGDI_blk ),
.CFGDSBUSNUMBER ( CFGDSBUSNUMBER ),
.CFGDSDEVICENUMBER ( CFGDSDEVICENUMBER ),
.CFGDSFUNCTIONNUMBER ( CFGDSFUNCTIONNUMBER ),
.CFGDSN ( CFGDSN_blk ),
.CFGDWADDR ( CFGDWADDR_blk ),
.CFGERRACSN ( CFGERRACSN_blk ),
.CFGERRAERHEADERLOG ( CFGERRAERHEADERLOG ),
.CFGERRCORN ( CFGERRCORN_blk ),
.CFGERRCPLABORTN ( CFGERRCPLABORTN_blk ),
.CFGERRCPLTIMEOUTN ( CFGERRCPLTIMEOUTN_blk ),
.CFGERRCPLUNEXPECTN ( CFGERRCPLUNEXPECTN_blk ),
.CFGERRECRCN ( CFGERRECRCN_blk ),
.CFGERRLOCKEDN ( CFGERRLOCKEDN_blk ),
.CFGERRPOSTEDN ( CFGERRPOSTEDN_blk ),
.CFGERRTLPCPLHEADER ( CFGERRTLPCPLHEADER_blk ),
.CFGERRURN ( CFGERRURN_blk ),
.CFGINTERRUPTASSERTN ( CFGINTERRUPTASSERTN_blk ),
.CFGINTERRUPTDI ( CFGINTERRUPTDI_blk ),
.CFGINTERRUPTN ( CFGINTERRUPTN_blk ),
.CFGPMDIRECTASPML1N ( CFGPMDIRECTASPML1N_blk ),
.CFGPMSENDPMACKN ( CFGPMSENDPMACKN_blk ),
.CFGPMSENDPMETON ( CFGPMSENDPMETON_blk ),
.CFGPMSENDPMNAKN ( CFGPMSENDPMNAKN_blk ),
.CFGPMTURNOFFOKN ( CFGPMTURNOFFOKN_blk ),
.CFGPMWAKEN ( CFGPMWAKEN_blk ),
.CFGPORTNUMBER ( CFGPORTNUMBER_blk ),
.CFGRDENN ( CFGRDENN_blk ),
.CFGTRNPENDINGN ( CFGTRNPENDINGN_blk ),
.CFGWRENN ( CFGWRENN_blk ),
.CFGWRREADONLYN ( CFGWRREADONLYN_blk ),
.CFGWRRW1CASRWN ( CFGWRRW1CASRWN_blk ),
.CMRSTN ( CMRSTN ),
.CMSTICKYRSTN ( CMSTICKYRSTN ),
.DBGMODE ( DBGMODE ),
.DBGSUBMODE ( DBGSUBMODE ),
.DLRSTN ( DLRSTN ),
.DRPCLK ( PCIEDRPCLK ),
.DRPDADDR ( PCIEDRPDADDR ),
.DRPDEN ( PCIEDRPDEN ),
.DRPDI ( PCIEDRPDI ),
.DRPDWE ( PCIEDRPDWE ),
.FUNCLVLRSTN ( FUNCLVLRSTN ),
.LL2SENDASREQL1N ( LL2SENDASREQL1N ),
.LL2SENDENTERL1N ( LL2SENDENTERL1N ),
.LL2SENDENTERL23N ( LL2SENDENTERL23N ),
.LL2SUSPENDNOWN ( LL2SUSPENDNOWN ),
.LL2TLPRCVN ( LL2TLPRCVN ),
.MIMRXRDATA ( MIMRXRDATA ),
.MIMTXRDATA ( MIMTXRDATA ),
.PIPECLK ( PIPECLK ),
.PIPERX0CHANISALIGNED ( PIPERX0CHANISALIGNED ),
.PIPERX0CHARISK ( filter_pipe_upconfig_fix_3451 ? 2'b11 : PIPERX0CHARISK ),
.PIPERX0DATA ( PIPERX0DATA ),
.PIPERX0ELECIDLE ( PIPERX0ELECIDLE ),
.PIPERX0PHYSTATUS ( PIPERX0PHYSTATUS ),
.PIPERX0STATUS ( PIPERX0STATUS ),
.PIPERX0VALID ( PIPERX0VALID ),
.PIPERX1CHANISALIGNED ( PIPERX1CHANISALIGNED ),
.PIPERX1CHARISK ( filter_pipe_upconfig_fix_3451 ? 2'b11 : PIPERX1CHARISK ),
.PIPERX1DATA ( PIPERX1DATA ),
.PIPERX1ELECIDLE ( PIPERX1ELECIDLE ),
.PIPERX1PHYSTATUS ( PIPERX1PHYSTATUS ),
.PIPERX1STATUS ( PIPERX1STATUS ),
.PIPERX1VALID ( PIPERX1VALID ),
.PIPERX2CHANISALIGNED ( PIPERX2CHANISALIGNED ),
.PIPERX2CHARISK ( filter_pipe_upconfig_fix_3451 ? 2'b11 : PIPERX2CHARISK ),
.PIPERX2DATA ( PIPERX2DATA ),
.PIPERX2ELECIDLE ( PIPERX2ELECIDLE ),
.PIPERX2PHYSTATUS ( PIPERX2PHYSTATUS ),
.PIPERX2STATUS ( PIPERX2STATUS ),
.PIPERX2VALID ( PIPERX2VALID ),
.PIPERX3CHANISALIGNED ( PIPERX3CHANISALIGNED ),
.PIPERX3CHARISK ( filter_pipe_upconfig_fix_3451 ? 2'b11 : PIPERX3CHARISK ),
.PIPERX3DATA ( PIPERX3DATA ),
.PIPERX3ELECIDLE ( PIPERX3ELECIDLE ),
.PIPERX3PHYSTATUS ( PIPERX3PHYSTATUS ),
.PIPERX3STATUS ( PIPERX3STATUS ),
.PIPERX3VALID ( PIPERX3VALID ),
.PIPERX4CHANISALIGNED ( PIPERX4CHANISALIGNED ),
.PIPERX4CHARISK ( filter_pipe_upconfig_fix_3451 ? 2'b11 : PIPERX4CHARISK ),
.PIPERX4DATA ( PIPERX4DATA ),
.PIPERX4ELECIDLE ( PIPERX4ELECIDLE ),
.PIPERX4PHYSTATUS ( PIPERX4PHYSTATUS ),
.PIPERX4STATUS ( PIPERX4STATUS ),
.PIPERX4VALID ( PIPERX4VALID ),
.PIPERX5CHANISALIGNED ( PIPERX5CHANISALIGNED ),
.PIPERX5CHARISK ( filter_pipe_upconfig_fix_3451 ? 2'b11 : PIPERX5CHARISK ),
.PIPERX5DATA ( PIPERX5DATA ),
.PIPERX5ELECIDLE ( PIPERX5ELECIDLE ),
.PIPERX5PHYSTATUS ( PIPERX5PHYSTATUS ),
.PIPERX5STATUS ( PIPERX5STATUS ),
.PIPERX5VALID ( PIPERX5VALID ),
.PIPERX6CHANISALIGNED ( PIPERX6CHANISALIGNED ),
.PIPERX6CHARISK ( filter_pipe_upconfig_fix_3451 ? 2'b11 : PIPERX6CHARISK ),
.PIPERX6DATA ( PIPERX6DATA ),
.PIPERX6ELECIDLE ( PIPERX6ELECIDLE ),
.PIPERX6PHYSTATUS ( PIPERX6PHYSTATUS ),
.PIPERX6STATUS ( PIPERX6STATUS ),
.PIPERX6VALID ( PIPERX6VALID ),
.PIPERX7CHANISALIGNED ( PIPERX7CHANISALIGNED ),
.PIPERX7CHARISK ( filter_pipe_upconfig_fix_3451 ? 2'b11 : PIPERX7CHARISK ),
.PIPERX7DATA ( PIPERX7DATA ),
.PIPERX7ELECIDLE ( PIPERX7ELECIDLE ),
.PIPERX7PHYSTATUS ( PIPERX7PHYSTATUS ),
.PIPERX7STATUS ( PIPERX7STATUS ),
.PIPERX7VALID ( PIPERX7VALID ),
.PLDBGMODE ( PLDBGMODE ),
.PLDIRECTEDLINKAUTON ( PLDIRECTEDLINKAUTON ),
.PLDIRECTEDLINKCHANGE ( PLDIRECTEDLINKCHANGE ),
.PLDIRECTEDLINKSPEED ( PLDIRECTEDLINKSPEED ),
.PLDIRECTEDLINKWIDTH ( PLDIRECTEDLINKWIDTH ),
.PLDOWNSTREAMDEEMPHSOURCE ( PLDOWNSTREAMDEEMPHSOURCE ),
.PLRSTN ( PLRSTN ),
.PLTRANSMITHOTRST ( PLTRANSMITHOTRST ),
.PLUPSTREAMPREFERDEEMPH ( PLUPSTREAMPREFERDEEMPH ),
.PL2DIRECTEDLSTATE ( PL2DIRECTEDLSTATE ),
.SYSRSTN ( SYSRSTN ),
.TLRSTN ( TLRSTN ),
.TL2ASPMSUSPENDCREDITCHECKN ( 1'b1),
.TL2PPMSUSPENDREQN ( 1'b1 ),
.TRNFCSEL ( TRNFCSEL_o ),
.TRNRDSTRDYN ( TRNRDSTRDYN_o ),
.TRNRNPOKN ( TRNRNPOKN_o ),
.TRNTCFGGNTN ( TRNTCFGGNTN_o ),
.TRNTD ( TRNTD_o ),
.TRNTDLLPDATA ( TRNTDLLPDATA ),
.TRNTDLLPSRCRDYN ( TRNTDLLPSRCRDYN ),
.TRNTECRCGENN ( TRNTECRCGENN_o ),
.TRNTEOFN ( TRNTEOFN_o ),
.TRNTERRFWDN ( TRNTERRFWDN_o ),
.TRNTREMN ( TRNTREMN_o ),
.TRNTSOFN ( TRNTSOFN_o ),
.TRNTSRCDSCN ( TRNTSRCDSCN_o ),
.TRNTSRCRDYN ( TRNTSRCRDYN_o ),
.TRNTSTRN ( TRNTSTRN_o ),
.USERCLK ( BLOCKCLK )
);
//-------------------------------------------------------
// Virtex6 PIPE Module
//-------------------------------------------------------
pcie_pipe_v6 # (
.NO_OF_LANES(LINK_CAP_MAX_LINK_WIDTH),
.LINK_CAP_MAX_LINK_SPEED(LINK_CAP_MAX_LINK_SPEED),
.PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)
)
pcie_pipe_i (
// Pipe Per-Link Signals
.pipe_tx_rcvr_det_i (PIPETXRCVRDET),
.pipe_tx_reset_i (PIPETXRESET),
.pipe_tx_rate_i (PIPETXRATE),
.pipe_tx_deemph_i (PIPETXDEEMPH),
.pipe_tx_margin_i (PIPETXMARGIN),
.pipe_tx_swing_i (1'b0),
.pipe_tx_rcvr_det_o (PIPETXRCVRDETGT),
.pipe_tx_reset_o ( ),
.pipe_tx_rate_o (PIPETXRATEGT),
.pipe_tx_deemph_o (PIPETXDEEMPHGT),
.pipe_tx_margin_o (PIPETXMARGINGT),
.pipe_tx_swing_o ( ),
// Pipe Per-Lane Signals - Lane 0
.pipe_rx0_char_is_k_o (PIPERX0CHARISK ),
.pipe_rx0_data_o (PIPERX0DATA ),
.pipe_rx0_valid_o (PIPERX0VALID ),
.pipe_rx0_chanisaligned_o (PIPERX0CHANISALIGNED ),
.pipe_rx0_status_o (PIPERX0STATUS ),
.pipe_rx0_phy_status_o (PIPERX0PHYSTATUS ),
.pipe_rx0_elec_idle_i (PIPERX0ELECIDLEGT ),
.pipe_rx0_polarity_i (PIPERX0POLARITY ),
.pipe_tx0_compliance_i (PIPETX0COMPLIANCE ),
.pipe_tx0_char_is_k_i (PIPETX0CHARISK ),
.pipe_tx0_data_i (PIPETX0DATA ),
.pipe_tx0_elec_idle_i (PIPETX0ELECIDLE ),
.pipe_tx0_powerdown_i (PIPETX0POWERDOWN ),
.pipe_rx0_char_is_k_i (PIPERX0CHARISKGT ),
.pipe_rx0_data_i (PIPERX0DATAGT ),
.pipe_rx0_valid_i (PIPERX0VALIDGT ),
.pipe_rx0_chanisaligned_i (PIPERX0CHANISALIGNEDGT ),
.pipe_rx0_status_i (PIPERX0STATUSGT ),
.pipe_rx0_phy_status_i (PIPERX0PHYSTATUSGT ),
.pipe_rx0_elec_idle_o (PIPERX0ELECIDLE ),
.pipe_rx0_polarity_o (PIPERX0POLARITYGT ),
.pipe_tx0_compliance_o (PIPETX0COMPLIANCEGT ),
.pipe_tx0_char_is_k_o (PIPETX0CHARISKGT ),
.pipe_tx0_data_o (PIPETX0DATAGT ),
.pipe_tx0_elec_idle_o (PIPETX0ELECIDLEGT ),
.pipe_tx0_powerdown_o (PIPETX0POWERDOWNGT ),
// Pipe Per-Lane Signals - Lane 1
.pipe_rx1_char_is_k_o (PIPERX1CHARISK ),
.pipe_rx1_data_o (PIPERX1DATA ),
.pipe_rx1_valid_o (PIPERX1VALID ),
.pipe_rx1_chanisaligned_o (PIPERX1CHANISALIGNED ),
.pipe_rx1_status_o (PIPERX1STATUS ),
.pipe_rx1_phy_status_o (PIPERX1PHYSTATUS ),
.pipe_rx1_elec_idle_i (PIPERX1ELECIDLEGT ),
.pipe_rx1_polarity_i (PIPERX1POLARITY ),
.pipe_tx1_compliance_i (PIPETX1COMPLIANCE ),
.pipe_tx1_char_is_k_i (PIPETX1CHARISK ),
.pipe_tx1_data_i (PIPETX1DATA ),
.pipe_tx1_elec_idle_i (PIPETX1ELECIDLE ),
.pipe_tx1_powerdown_i (PIPETX1POWERDOWN ),
.pipe_rx1_char_is_k_i (PIPERX1CHARISKGT ),
.pipe_rx1_data_i (PIPERX1DATAGT ),
.pipe_rx1_valid_i (PIPERX1VALIDGT ),
.pipe_rx1_chanisaligned_i (PIPERX1CHANISALIGNEDGT ),
.pipe_rx1_status_i (PIPERX1STATUSGT ),
.pipe_rx1_phy_status_i (PIPERX1PHYSTATUSGT ),
.pipe_rx1_elec_idle_o (PIPERX1ELECIDLE ),
.pipe_rx1_polarity_o (PIPERX1POLARITYGT ),
.pipe_tx1_compliance_o (PIPETX1COMPLIANCEGT ),
.pipe_tx1_char_is_k_o (PIPETX1CHARISKGT ),
.pipe_tx1_data_o (PIPETX1DATAGT ),
.pipe_tx1_elec_idle_o (PIPETX1ELECIDLEGT ),
.pipe_tx1_powerdown_o (PIPETX1POWERDOWNGT ),
// Pipe Per-Lane Signals - Lane 2
.pipe_rx2_char_is_k_o (PIPERX2CHARISK ),
.pipe_rx2_data_o (PIPERX2DATA ),
.pipe_rx2_valid_o (PIPERX2VALID ),
.pipe_rx2_chanisaligned_o (PIPERX2CHANISALIGNED ),
.pipe_rx2_status_o (PIPERX2STATUS ),
.pipe_rx2_phy_status_o (PIPERX2PHYSTATUS ),
.pipe_rx2_elec_idle_i (PIPERX2ELECIDLEGT ),
.pipe_rx2_polarity_i (PIPERX2POLARITY ),
.pipe_tx2_compliance_i (PIPETX2COMPLIANCE ),
.pipe_tx2_char_is_k_i (PIPETX2CHARISK ),
.pipe_tx2_data_i (PIPETX2DATA ),
.pipe_tx2_elec_idle_i (PIPETX2ELECIDLE ),
.pipe_tx2_powerdown_i (PIPETX2POWERDOWN ),
.pipe_rx2_char_is_k_i (PIPERX2CHARISKGT ),
.pipe_rx2_data_i (PIPERX2DATAGT ),
.pipe_rx2_valid_i (PIPERX2VALIDGT ),
.pipe_rx2_chanisaligned_i (PIPERX2CHANISALIGNEDGT ),
.pipe_rx2_status_i (PIPERX2STATUSGT ),
.pipe_rx2_phy_status_i (PIPERX2PHYSTATUSGT ),
.pipe_rx2_elec_idle_o (PIPERX2ELECIDLE ),
.pipe_rx2_polarity_o (PIPERX2POLARITYGT ),
.pipe_tx2_compliance_o (PIPETX2COMPLIANCEGT ),
.pipe_tx2_char_is_k_o (PIPETX2CHARISKGT ),
.pipe_tx2_data_o (PIPETX2DATAGT ),
.pipe_tx2_elec_idle_o (PIPETX2ELECIDLEGT ),
.pipe_tx2_powerdown_o (PIPETX2POWERDOWNGT ),
// Pipe Per-Lane Signals - Lane 3
.pipe_rx3_char_is_k_o (PIPERX3CHARISK ),
.pipe_rx3_data_o (PIPERX3DATA ),
.pipe_rx3_valid_o (PIPERX3VALID ),
.pipe_rx3_chanisaligned_o (PIPERX3CHANISALIGNED ),
.pipe_rx3_status_o (PIPERX3STATUS ),
.pipe_rx3_phy_status_o (PIPERX3PHYSTATUS ),
.pipe_rx3_elec_idle_i (PIPERX3ELECIDLEGT ),
.pipe_rx3_polarity_i (PIPERX3POLARITY ),
.pipe_tx3_compliance_i (PIPETX3COMPLIANCE ),
.pipe_tx3_char_is_k_i (PIPETX3CHARISK ),
.pipe_tx3_data_i (PIPETX3DATA ),
.pipe_tx3_elec_idle_i (PIPETX3ELECIDLE ),
.pipe_tx3_powerdown_i (PIPETX3POWERDOWN ),
.pipe_rx3_char_is_k_i (PIPERX3CHARISKGT ),
.pipe_rx3_data_i (PIPERX3DATAGT ),
.pipe_rx3_valid_i (PIPERX3VALIDGT ),
.pipe_rx3_chanisaligned_i (PIPERX3CHANISALIGNEDGT ),
.pipe_rx3_status_i (PIPERX3STATUSGT ),
.pipe_rx3_phy_status_i (PIPERX3PHYSTATUSGT ),
.pipe_rx3_elec_idle_o (PIPERX3ELECIDLE ),
.pipe_rx3_polarity_o (PIPERX3POLARITYGT ),
.pipe_tx3_compliance_o (PIPETX3COMPLIANCEGT ),
.pipe_tx3_char_is_k_o (PIPETX3CHARISKGT ),
.pipe_tx3_data_o (PIPETX3DATAGT ),
.pipe_tx3_elec_idle_o (PIPETX3ELECIDLEGT ),
.pipe_tx3_powerdown_o (PIPETX3POWERDOWNGT ),
// Pipe Per-Lane Signals - Lane 4
.pipe_rx4_char_is_k_o (PIPERX4CHARISK ),
.pipe_rx4_data_o (PIPERX4DATA ),
.pipe_rx4_valid_o (PIPERX4VALID ),
.pipe_rx4_chanisaligned_o (PIPERX4CHANISALIGNED ),
.pipe_rx4_status_o (PIPERX4STATUS ),
.pipe_rx4_phy_status_o (PIPERX4PHYSTATUS ),
.pipe_rx4_elec_idle_i (PIPERX4ELECIDLEGT ),
.pipe_rx4_polarity_i (PIPERX4POLARITY ),
.pipe_tx4_compliance_i (PIPETX4COMPLIANCE ),
.pipe_tx4_char_is_k_i (PIPETX4CHARISK ),
.pipe_tx4_data_i (PIPETX4DATA ),
.pipe_tx4_elec_idle_i (PIPETX4ELECIDLE ),
.pipe_tx4_powerdown_i (PIPETX4POWERDOWN ),
.pipe_rx4_char_is_k_i (PIPERX4CHARISKGT ),
.pipe_rx4_data_i (PIPERX4DATAGT ),
.pipe_rx4_valid_i (PIPERX4VALIDGT ),
.pipe_rx4_chanisaligned_i (PIPERX4CHANISALIGNEDGT ),
.pipe_rx4_status_i (PIPERX4STATUSGT ),
.pipe_rx4_phy_status_i (PIPERX4PHYSTATUSGT ),
.pipe_rx4_elec_idle_o (PIPERX4ELECIDLE ),
.pipe_rx4_polarity_o (PIPERX4POLARITYGT ),
.pipe_tx4_compliance_o (PIPETX4COMPLIANCEGT ),
.pipe_tx4_char_is_k_o (PIPETX4CHARISKGT ),
.pipe_tx4_data_o (PIPETX4DATAGT ),
.pipe_tx4_elec_idle_o (PIPETX4ELECIDLEGT ),
.pipe_tx4_powerdown_o (PIPETX4POWERDOWNGT ),
// Pipe Per-Lane Signals - Lane 5
.pipe_rx5_char_is_k_o (PIPERX5CHARISK ),
.pipe_rx5_data_o (PIPERX5DATA ),
.pipe_rx5_valid_o (PIPERX5VALID ),
.pipe_rx5_chanisaligned_o (PIPERX5CHANISALIGNED ),
.pipe_rx5_status_o (PIPERX5STATUS ),
.pipe_rx5_phy_status_o (PIPERX5PHYSTATUS ),
.pipe_rx5_elec_idle_i (PIPERX5ELECIDLEGT ),
.pipe_rx5_polarity_i (PIPERX5POLARITY ),
.pipe_tx5_compliance_i (PIPETX5COMPLIANCE ),
.pipe_tx5_char_is_k_i (PIPETX5CHARISK ),
.pipe_tx5_data_i (PIPETX5DATA ),
.pipe_tx5_elec_idle_i (PIPETX5ELECIDLE ),
.pipe_tx5_powerdown_i (PIPETX5POWERDOWN ),
.pipe_rx5_char_is_k_i (PIPERX5CHARISKGT ),
.pipe_rx5_data_i (PIPERX5DATAGT ),
.pipe_rx5_valid_i (PIPERX5VALIDGT ),
.pipe_rx5_chanisaligned_i (PIPERX5CHANISALIGNEDGT ),
.pipe_rx5_status_i (PIPERX5STATUSGT ),
.pipe_rx5_phy_status_i (PIPERX5PHYSTATUSGT ),
.pipe_rx5_elec_idle_o (PIPERX5ELECIDLE ),
.pipe_rx5_polarity_o (PIPERX5POLARITYGT ),
.pipe_tx5_compliance_o (PIPETX5COMPLIANCEGT ),
.pipe_tx5_char_is_k_o (PIPETX5CHARISKGT ),
.pipe_tx5_data_o (PIPETX5DATAGT ),
.pipe_tx5_elec_idle_o (PIPETX5ELECIDLEGT ),
.pipe_tx5_powerdown_o (PIPETX5POWERDOWNGT ),
// Pipe Per-Lane Signals - Lane 6
.pipe_rx6_char_is_k_o (PIPERX6CHARISK ),
.pipe_rx6_data_o (PIPERX6DATA ),
.pipe_rx6_valid_o (PIPERX6VALID ),
.pipe_rx6_chanisaligned_o (PIPERX6CHANISALIGNED ),
.pipe_rx6_status_o (PIPERX6STATUS ),
.pipe_rx6_phy_status_o (PIPERX6PHYSTATUS ),
.pipe_rx6_elec_idle_i (PIPERX6ELECIDLEGT ),
.pipe_rx6_polarity_i (PIPERX6POLARITY ),
.pipe_tx6_compliance_i (PIPETX6COMPLIANCE ),
.pipe_tx6_char_is_k_i (PIPETX6CHARISK ),
.pipe_tx6_data_i (PIPETX6DATA ),
.pipe_tx6_elec_idle_i (PIPETX6ELECIDLE ),
.pipe_tx6_powerdown_i (PIPETX6POWERDOWN ),
.pipe_rx6_char_is_k_i (PIPERX6CHARISKGT ),
.pipe_rx6_data_i (PIPERX6DATAGT ),
.pipe_rx6_valid_i (PIPERX6VALIDGT ),
.pipe_rx6_chanisaligned_i (PIPERX6CHANISALIGNEDGT ),
.pipe_rx6_status_i (PIPERX6STATUSGT ),
.pipe_rx6_phy_status_i (PIPERX6PHYSTATUSGT ),
.pipe_rx6_elec_idle_o (PIPERX6ELECIDLE ),
.pipe_rx6_polarity_o (PIPERX6POLARITYGT ),
.pipe_tx6_compliance_o (PIPETX6COMPLIANCEGT ),
.pipe_tx6_char_is_k_o (PIPETX6CHARISKGT ),
.pipe_tx6_data_o (PIPETX6DATAGT ),
.pipe_tx6_elec_idle_o (PIPETX6ELECIDLEGT ),
.pipe_tx6_powerdown_o (PIPETX6POWERDOWNGT ),
// Pipe Per-Lane Signals - Lane 7
.pipe_rx7_char_is_k_o (PIPERX7CHARISK ),
.pipe_rx7_data_o (PIPERX7DATA ),
.pipe_rx7_valid_o (PIPERX7VALID ),
.pipe_rx7_chanisaligned_o (PIPERX7CHANISALIGNED ),
.pipe_rx7_status_o (PIPERX7STATUS ),
.pipe_rx7_phy_status_o (PIPERX7PHYSTATUS ),
.pipe_rx7_elec_idle_i (PIPERX7ELECIDLEGT ),
.pipe_rx7_polarity_i (PIPERX7POLARITY ),
.pipe_tx7_compliance_i (PIPETX7COMPLIANCE ),
.pipe_tx7_char_is_k_i (PIPETX7CHARISK ),
.pipe_tx7_data_i (PIPETX7DATA ),
.pipe_tx7_elec_idle_i (PIPETX7ELECIDLE ),
.pipe_tx7_powerdown_i (PIPETX7POWERDOWN ),
.pipe_rx7_char_is_k_i (PIPERX7CHARISKGT ),
.pipe_rx7_data_i (PIPERX7DATAGT ),
.pipe_rx7_valid_i (PIPERX7VALIDGT ),
.pipe_rx7_chanisaligned_i (PIPERX7CHANISALIGNEDGT ),
.pipe_rx7_status_i (PIPERX7STATUSGT ),
.pipe_rx7_phy_status_i (PIPERX7PHYSTATUSGT ),
.pipe_rx7_elec_idle_o (PIPERX7ELECIDLE ),
.pipe_rx7_polarity_o (PIPERX7POLARITYGT ),
.pipe_tx7_compliance_o (PIPETX7COMPLIANCEGT ),
.pipe_tx7_char_is_k_o (PIPETX7CHARISKGT ),
.pipe_tx7_data_o (PIPETX7DATAGT ),
.pipe_tx7_elec_idle_o (PIPETX7ELECIDLEGT ),
.pipe_tx7_powerdown_o (PIPETX7POWERDOWNGT ),
// Non PIPE signals
.pl_ltssm_state (PLLTSSMSTATE ),
.pipe_clk (PIPECLK ),
.rst_n (PHYRDYN )
);
//-------------------------------------------------------
// Virtex6 GTX Module
//-------------------------------------------------------
pcie_gtx_v6 #(
.NO_OF_LANES(LINK_CAP_MAX_LINK_WIDTH),
.LINK_CAP_MAX_LINK_SPEED(LINK_CAP_MAX_LINK_SPEED),
.REF_CLK_FREQ(REF_CLK_FREQ),
.PL_FAST_TRAIN(PL_FAST_TRAIN)
)
pcie_gt_i (
// Pipe Common Signals
.pipe_tx_rcvr_det (PIPETXRCVRDETGT ),
.pipe_tx_reset (1'b0 ),
.pipe_tx_rate (PIPETXRATEGT ),
.pipe_tx_deemph (PIPETXDEEMPHGT ),
.pipe_tx_margin (PIPETXMARGINGT ),
.pipe_tx_swing (1'b0),
// Pipe Per-Lane Signals - Lane 0
.pipe_rx0_char_is_k (PIPERX0CHARISKGT ),
.pipe_rx0_data (PIPERX0DATAGT ),
.pipe_rx0_valid (PIPERX0VALIDGT ),
.pipe_rx0_chanisaligned (PIPERX0CHANISALIGNEDGT ),
.pipe_rx0_status (PIPERX0STATUSGT ),
.pipe_rx0_phy_status (PIPERX0PHYSTATUSGT ),
.pipe_rx0_elec_idle (PIPERX0ELECIDLEGT ),
.pipe_rx0_polarity (PIPERX0POLARITYGT ),
.pipe_tx0_compliance (PIPETX0COMPLIANCEGT ),
.pipe_tx0_char_is_k (PIPETX0CHARISKGT ),
.pipe_tx0_data (PIPETX0DATAGT ),
.pipe_tx0_elec_idle (PIPETX0ELECIDLEGT ),
.pipe_tx0_powerdown (PIPETX0POWERDOWNGT ),
// Pipe Per-Lane Signals - Lane 1
.pipe_rx1_char_is_k (PIPERX1CHARISKGT ),
.pipe_rx1_data (PIPERX1DATAGT ),
.pipe_rx1_valid (PIPERX1VALIDGT ),
.pipe_rx1_chanisaligned (PIPERX1CHANISALIGNEDGT ),
.pipe_rx1_status (PIPERX1STATUSGT ),
.pipe_rx1_phy_status (PIPERX1PHYSTATUSGT ),
.pipe_rx1_elec_idle (PIPERX1ELECIDLEGT ),
.pipe_rx1_polarity (PIPERX1POLARITYGT ),
.pipe_tx1_compliance (PIPETX1COMPLIANCEGT ),
.pipe_tx1_char_is_k (PIPETX1CHARISKGT ),
.pipe_tx1_data (PIPETX1DATAGT ),
.pipe_tx1_elec_idle (PIPETX1ELECIDLEGT ),
.pipe_tx1_powerdown (PIPETX1POWERDOWNGT ),
// Pipe Per-Lane Signals - Lane 2
.pipe_rx2_char_is_k (PIPERX2CHARISKGT ),
.pipe_rx2_data (PIPERX2DATAGT ),
.pipe_rx2_valid (PIPERX2VALIDGT ),
.pipe_rx2_chanisaligned (PIPERX2CHANISALIGNEDGT ),
.pipe_rx2_status (PIPERX2STATUSGT ),
.pipe_rx2_phy_status (PIPERX2PHYSTATUSGT ),
.pipe_rx2_elec_idle (PIPERX2ELECIDLEGT ),
.pipe_rx2_polarity (PIPERX2POLARITYGT ),
.pipe_tx2_compliance (PIPETX2COMPLIANCEGT ),
.pipe_tx2_char_is_k (PIPETX2CHARISKGT ),
.pipe_tx2_data (PIPETX2DATAGT ),
.pipe_tx2_elec_idle (PIPETX2ELECIDLEGT ),
.pipe_tx2_powerdown (PIPETX2POWERDOWNGT ),
// Pipe Per-Lane Signals - Lane 3
.pipe_rx3_char_is_k (PIPERX3CHARISKGT ),
.pipe_rx3_data (PIPERX3DATAGT ),
.pipe_rx3_valid (PIPERX3VALIDGT ),
.pipe_rx3_chanisaligned (PIPERX3CHANISALIGNEDGT ),
.pipe_rx3_status (PIPERX3STATUSGT ),
.pipe_rx3_phy_status (PIPERX3PHYSTATUSGT ),
.pipe_rx3_elec_idle (PIPERX3ELECIDLEGT ),
.pipe_rx3_polarity (PIPERX3POLARITYGT ),
.pipe_tx3_compliance (PIPETX3COMPLIANCEGT ),
.pipe_tx3_char_is_k (PIPETX3CHARISKGT ),
.pipe_tx3_data (PIPETX3DATAGT ),
.pipe_tx3_elec_idle (PIPETX3ELECIDLEGT ),
.pipe_tx3_powerdown (PIPETX3POWERDOWNGT ),
// Pipe Per-Lane Signals - Lane 4
.pipe_rx4_char_is_k (PIPERX4CHARISKGT ),
.pipe_rx4_data (PIPERX4DATAGT ),
.pipe_rx4_valid (PIPERX4VALIDGT ),
.pipe_rx4_chanisaligned (PIPERX4CHANISALIGNEDGT ),
.pipe_rx4_status (PIPERX4STATUSGT ),
.pipe_rx4_phy_status (PIPERX4PHYSTATUSGT ),
.pipe_rx4_elec_idle (PIPERX4ELECIDLEGT ),
.pipe_rx4_polarity (PIPERX4POLARITYGT ),
.pipe_tx4_compliance (PIPETX4COMPLIANCEGT ),
.pipe_tx4_char_is_k (PIPETX4CHARISKGT ),
.pipe_tx4_data (PIPETX4DATAGT ),
.pipe_tx4_elec_idle (PIPETX4ELECIDLEGT ),
.pipe_tx4_powerdown (PIPETX4POWERDOWNGT ),
// Pipe Per-Lane Signals - Lane 5
.pipe_rx5_char_is_k (PIPERX5CHARISKGT ),
.pipe_rx5_data (PIPERX5DATAGT ),
.pipe_rx5_valid (PIPERX5VALIDGT ),
.pipe_rx5_chanisaligned (PIPERX5CHANISALIGNEDGT ),
.pipe_rx5_status (PIPERX5STATUSGT ),
.pipe_rx5_phy_status (PIPERX5PHYSTATUSGT ),
.pipe_rx5_elec_idle (PIPERX5ELECIDLEGT ),
.pipe_rx5_polarity (PIPERX5POLARITYGT ),
.pipe_tx5_compliance (PIPETX5COMPLIANCEGT ),
.pipe_tx5_char_is_k (PIPETX5CHARISKGT ),
.pipe_tx5_data (PIPETX5DATAGT ),
.pipe_tx5_elec_idle (PIPETX5ELECIDLEGT ),
.pipe_tx5_powerdown (PIPETX5POWERDOWNGT ),
// Pipe Per-Lane Signals - Lane 6
.pipe_rx6_char_is_k (PIPERX6CHARISKGT ),
.pipe_rx6_data (PIPERX6DATAGT ),
.pipe_rx6_valid (PIPERX6VALIDGT ),
.pipe_rx6_chanisaligned (PIPERX6CHANISALIGNEDGT ),
.pipe_rx6_status (PIPERX6STATUSGT ),
.pipe_rx6_phy_status (PIPERX6PHYSTATUSGT ),
.pipe_rx6_elec_idle (PIPERX6ELECIDLEGT ),
.pipe_rx6_polarity (PIPERX6POLARITYGT ),
.pipe_tx6_compliance (PIPETX6COMPLIANCEGT ),
.pipe_tx6_char_is_k (PIPETX6CHARISKGT ),
.pipe_tx6_data (PIPETX6DATAGT ),
.pipe_tx6_elec_idle (PIPETX6ELECIDLEGT ),
.pipe_tx6_powerdown (PIPETX6POWERDOWNGT ),
// Pipe Per-Lane Signals - Lane 7
.pipe_rx7_char_is_k (PIPERX7CHARISKGT ),
.pipe_rx7_data (PIPERX7DATAGT ),
.pipe_rx7_valid (PIPERX7VALIDGT ),
.pipe_rx7_chanisaligned (PIPERX7CHANISALIGNEDGT ),
.pipe_rx7_status (PIPERX7STATUSGT ),
.pipe_rx7_phy_status (PIPERX7PHYSTATUSGT ),
.pipe_rx7_elec_idle (PIPERX7ELECIDLEGT ),
.pipe_rx7_polarity (PIPERX7POLARITYGT ),
.pipe_tx7_compliance (PIPETX7COMPLIANCEGT ),
.pipe_tx7_char_is_k (PIPETX7CHARISKGT ),
.pipe_tx7_data (PIPETX7DATAGT ),
.pipe_tx7_elec_idle (PIPETX7ELECIDLEGT ),
.pipe_tx7_powerdown (PIPETX7POWERDOWNGT ),
// PCI Express Signals
.pci_exp_txn (PCIEXPTXN ),
.pci_exp_txp (PCIEXPTXP ),
.pci_exp_rxn (PCIEXPRXN ),
.pci_exp_rxp (PCIEXPRXP ),
// Non PIPE Signals
.sys_clk (SYSCLK ),
.sys_rst_n (FUNDRSTN ),
.pipe_clk (PIPECLK ),
.drp_clk (DRPCLK ),
.clock_locked (CLOCKLOCKED ),
.pl_ltssm_state (PLLTSSMSTATE ),
.gt_pll_lock (GTPLLLOCK ),
.phy_rdy_n (PHYRDYN ),
.TxOutClk (TxOutClk )
);
//-------------------------------------------------------
// PCI Express BRAM Module
//-------------------------------------------------------
pcie_bram_top_v6 #(
.DEV_CAP_MAX_PAYLOAD_SUPPORTED(DEV_CAP_MAX_PAYLOAD_SUPPORTED),
.VC0_TX_LASTPACKET(VC0_TX_LASTPACKET),
.TL_TX_RAM_RADDR_LATENCY(TL_TX_RAM_RADDR_LATENCY),
.TL_TX_RAM_RDATA_LATENCY(TL_TX_RAM_RDATA_LATENCY),
.TL_TX_RAM_WRITE_LATENCY(TL_TX_RAM_WRITE_LATENCY),
.VC0_RX_LIMIT(VC0_RX_RAM_LIMIT),
.TL_RX_RAM_RADDR_LATENCY(TL_RX_RAM_RADDR_LATENCY),
.TL_RX_RAM_RDATA_LATENCY(TL_RX_RAM_RDATA_LATENCY),
.TL_RX_RAM_WRITE_LATENCY(TL_RX_RAM_WRITE_LATENCY)
)
pcie_bram_i (
.user_clk_i( BLOCKCLK ),
.reset_i( 1'b0 ),
.mim_tx_waddr( MIMTXWADDR ),
.mim_tx_wen( MIMTXWEN ),
.mim_tx_ren( MIMTXREN ),
.mim_tx_rce( MIMTXRCE ),
.mim_tx_wdata( {3'b000, MIMTXWDATA} ),
.mim_tx_raddr( MIMTXRADDR ),
.mim_tx_rdata( MIMTXRDATA ),
.mim_rx_waddr( MIMRXWADDR ),
.mim_rx_wen( MIMRXWEN ),
.mim_rx_ren( MIMRXREN ),
.mim_rx_rce( MIMRXRCE ),
.mim_rx_wdata( {4'b0000, MIMRXWDATA} ),
.mim_rx_raddr( MIMRXRADDR ),
.mim_rx_rdata( MIMRXRDATA )
);
//-------------------------------------------------------
// PCI Express Port Workarounds
//-------------------------------------------------------
pcie_upconfig_fix_3451_v6 # (
.UPSTREAM_FACING ( UPSTREAM_FACING ),
.PL_FAST_TRAIN ( PL_FAST_TRAIN ),
.LINK_CAP_MAX_LINK_WIDTH ( LINK_CAP_MAX_LINK_WIDTH )
)
pcie_upconfig_fix_3451_v6_i (
.pipe_clk(PIPECLK),
.pl_phy_lnkup_n(PLPHYLNKUPN),
.pl_ltssm_state(PLLTSSMSTATE),
.pl_sel_lnk_rate(PLSELLNKRATE),
.pl_directed_link_change(PLDIRECTEDLINKCHANGE),
.cfg_link_status_negotiated_width(CFGLINKSTATUSNEGOTIATEDWIDTH),
.pipe_rx0_data(PIPERX0DATAGT[15:0]),
.pipe_rx0_char_isk(PIPERX0CHARISKGT[1:0]),
.filter_pipe(filter_pipe_upconfig_fix_3451)
);
endmodule
|
/*
* Copyright (c) 2001 Ted Bullen
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
// This code is released to Steve Williams for the Icarus Verilog compiler
// It can be used as desired !
// DEFINES
`define NRBITS 4 // Number of bits in each operand
// TOP MODULE
module testFunction();
// SIGNAL DECLARATIONS
reg clock;
reg [`NRBITS-1:0] a_in;
integer a_integer;
integer myint;
reg [`NRBITS:0] cycle_count; // Counts valid clock cycles
// Initialize inputs
initial begin
clock = 1;
cycle_count = 0;
# (16*200+15) $display("PASSED");
$finish;
end
// Generate the clock
always #100 clock = ~clock;
// Simulate
always @(negedge clock) begin
cycle_count = cycle_count + 1;
// Create inputs between 0 and all 1s
a_in = cycle_count[`NRBITS-1:0];
myint = a_in;
$display("a_in = %d, myint = %d", a_in, myint);
// Convert the unsigned numbers to signed numbers
a_integer = short_to_int(a_in);
if (myint !== a_integer)
begin
$display("ERROR ! %d !== %d", myint, a_integer);
$stop;
end
end
// Function to convert a reg of `NRBITS
// bits to a signed integer
function integer short_to_int;
input [`NRBITS-1:0] x;
begin
short_to_int = x;
$display("\tshort_to_int(%b) = %b", x, short_to_int);
end
endfunction
endmodule
|
//////////////////////////////////////////////////////////////////////////////////
// d_SC_deviders_s_lfs_XOR.v for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Jinwoo Jeong <[email protected]>
// Ilyong Jung <[email protected]>
// Yong Ho Song <[email protected]>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Jinwoo Jeong <[email protected]>
// Ilyong Jung <[email protected]>
//
// Project Name: Cosmos OpenSSD
// Design Name: BCH Page Decoder
// Module Name: d_SC_serial_lfs_XOR_***
// File Name: d_SC_deviders_s_lfs_XOR.v
//
// Version: v1.0.1-256B_T14
//
// Description: Serial linear feedback shift XOR for data area
//
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.0.1
// - minor modification for releasing
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`include "d_SC_parameters.vh"
`timescale 1ns / 1ps
module d_SC_serial_lfs_XOR_001(i_message, i_cur_remainder, o_nxt_remainder);
parameter [0:12] MIN_POLY = 13'b1001100100001;
input wire i_message;
input wire [`D_SC_GF_ORDER-1:0] i_cur_remainder;
output wire [`D_SC_GF_ORDER-1:0] o_nxt_remainder;
wire w_FB_term;
assign w_FB_term = i_cur_remainder[`D_SC_GF_ORDER-1];
assign o_nxt_remainder[0] = i_message ^ w_FB_term;
genvar i;
generate
for (i=1; i<`D_SC_GF_ORDER; i=i+1)
begin: linear_function
if (MIN_POLY[i] == 1)
begin
assign o_nxt_remainder[i] = i_cur_remainder[i-1] ^ w_FB_term;
end
else
begin
assign o_nxt_remainder[i] = i_cur_remainder[i-1];
end
end
endgenerate
endmodule
module d_SC_serial_lfs_XOR_003(i_message, i_cur_remainder, o_nxt_remainder);
parameter [0:12] MIN_POLY = 13'b1111010111001;
input wire i_message;
input wire [`D_SC_GF_ORDER-1:0] i_cur_remainder;
output wire [`D_SC_GF_ORDER-1:0] o_nxt_remainder;
wire w_FB_term;
assign w_FB_term = i_cur_remainder[`D_SC_GF_ORDER-1];
assign o_nxt_remainder[0] = i_message ^ w_FB_term;
genvar i;
generate
for (i=1; i<`D_SC_GF_ORDER; i=i+1)
begin: linear_function
if (MIN_POLY[i] == 1)
begin
assign o_nxt_remainder[i] = i_cur_remainder[i-1] ^ w_FB_term;
end
else
begin
assign o_nxt_remainder[i] = i_cur_remainder[i-1];
end
end
endgenerate
endmodule
module d_SC_serial_lfs_XOR_005(i_message, i_cur_remainder, o_nxt_remainder);
parameter [0:12] MIN_POLY = 13'b1000010100011;
input wire i_message;
input wire [`D_SC_GF_ORDER-1:0] i_cur_remainder;
output wire [`D_SC_GF_ORDER-1:0] o_nxt_remainder;
wire w_FB_term;
assign w_FB_term = i_cur_remainder[`D_SC_GF_ORDER-1];
assign o_nxt_remainder[0] = i_message ^ w_FB_term;
genvar i;
generate
for (i=1; i<`D_SC_GF_ORDER; i=i+1)
begin: linear_function
if (MIN_POLY[i] == 1)
begin
assign o_nxt_remainder[i] = i_cur_remainder[i-1] ^ w_FB_term;
end
else
begin
assign o_nxt_remainder[i] = i_cur_remainder[i-1];
end
end
endgenerate
endmodule
module d_SC_serial_lfs_XOR_007(i_message, i_cur_remainder, o_nxt_remainder);
parameter [0:12] MIN_POLY = 13'b1000010100101;
input wire i_message;
input wire [`D_SC_GF_ORDER-1:0] i_cur_remainder;
output wire [`D_SC_GF_ORDER-1:0] o_nxt_remainder;
wire w_FB_term;
assign w_FB_term = i_cur_remainder[`D_SC_GF_ORDER-1];
assign o_nxt_remainder[0] = i_message ^ w_FB_term;
genvar i;
generate
for (i=1; i<`D_SC_GF_ORDER; i=i+1)
begin: linear_function
if (MIN_POLY[i] == 1)
begin
assign o_nxt_remainder[i] = i_cur_remainder[i-1] ^ w_FB_term;
end
else
begin
assign o_nxt_remainder[i] = i_cur_remainder[i-1];
end
end
endgenerate
endmodule
module d_SC_serial_lfs_XOR_009(i_message, i_cur_remainder, o_nxt_remainder);
parameter [0:12] MIN_POLY = 13'b1101110001111;
input wire i_message;
input wire [`D_SC_GF_ORDER-1:0] i_cur_remainder;
output wire [`D_SC_GF_ORDER-1:0] o_nxt_remainder;
wire w_FB_term;
assign w_FB_term = i_cur_remainder[`D_SC_GF_ORDER-1];
assign o_nxt_remainder[0] = i_message ^ w_FB_term;
genvar i;
generate
for (i=1; i<`D_SC_GF_ORDER; i=i+1)
begin: linear_function
if (MIN_POLY[i] == 1)
begin
assign o_nxt_remainder[i] = i_cur_remainder[i-1] ^ w_FB_term;
end
else
begin
assign o_nxt_remainder[i] = i_cur_remainder[i-1];
end
end
endgenerate
endmodule
module d_SC_serial_lfs_XOR_011(i_message, i_cur_remainder, o_nxt_remainder);
parameter [0:12] MIN_POLY = 13'b1011100010101;
input wire i_message;
input wire [`D_SC_GF_ORDER-1:0] i_cur_remainder;
output wire [`D_SC_GF_ORDER-1:0] o_nxt_remainder;
wire w_FB_term;
assign w_FB_term = i_cur_remainder[`D_SC_GF_ORDER-1];
assign o_nxt_remainder[0] = i_message ^ w_FB_term;
genvar i;
generate
for (i=1; i<`D_SC_GF_ORDER; i=i+1)
begin: linear_function
if (MIN_POLY[i] == 1)
begin
assign o_nxt_remainder[i] = i_cur_remainder[i-1] ^ w_FB_term;
end
else
begin
assign o_nxt_remainder[i] = i_cur_remainder[i-1];
end
end
endgenerate
endmodule
module d_SC_serial_lfs_XOR_013(i_message, i_cur_remainder, o_nxt_remainder);
parameter [0:12] MIN_POLY = 13'b1010101001011;
input wire i_message;
input wire [`D_SC_GF_ORDER-1:0] i_cur_remainder;
output wire [`D_SC_GF_ORDER-1:0] o_nxt_remainder;
wire w_FB_term;
assign w_FB_term = i_cur_remainder[`D_SC_GF_ORDER-1];
assign o_nxt_remainder[0] = i_message ^ w_FB_term;
genvar i;
generate
for (i=1; i<`D_SC_GF_ORDER; i=i+1)
begin: linear_function
if (MIN_POLY[i] == 1)
begin
assign o_nxt_remainder[i] = i_cur_remainder[i-1] ^ w_FB_term;
end
else
begin
assign o_nxt_remainder[i] = i_cur_remainder[i-1];
end
end
endgenerate
endmodule
module d_SC_serial_lfs_XOR_015(i_message, i_cur_remainder, o_nxt_remainder);
parameter [0:12] MIN_POLY = 13'b1000011001111;
input wire i_message;
input wire [`D_SC_GF_ORDER-1:0] i_cur_remainder;
output wire [`D_SC_GF_ORDER-1:0] o_nxt_remainder;
wire w_FB_term;
assign w_FB_term = i_cur_remainder[`D_SC_GF_ORDER-1];
assign o_nxt_remainder[0] = i_message ^ w_FB_term;
genvar i;
generate
for (i=1; i<`D_SC_GF_ORDER; i=i+1)
begin: linear_function
if (MIN_POLY[i] == 1)
begin
assign o_nxt_remainder[i] = i_cur_remainder[i-1] ^ w_FB_term;
end
else
begin
assign o_nxt_remainder[i] = i_cur_remainder[i-1];
end
end
endgenerate
endmodule
module d_SC_serial_lfs_XOR_017(i_message, i_cur_remainder, o_nxt_remainder);
parameter [0:12] MIN_POLY = 13'b1011111000001;
input wire i_message;
input wire [`D_SC_GF_ORDER-1:0] i_cur_remainder;
output wire [`D_SC_GF_ORDER-1:0] o_nxt_remainder;
wire w_FB_term;
assign w_FB_term = i_cur_remainder[`D_SC_GF_ORDER-1];
assign o_nxt_remainder[0] = i_message ^ w_FB_term;
genvar i;
generate
for (i=1; i<`D_SC_GF_ORDER; i=i+1)
begin: linear_function
if (MIN_POLY[i] == 1)
begin
assign o_nxt_remainder[i] = i_cur_remainder[i-1] ^ w_FB_term;
end
else
begin
assign o_nxt_remainder[i] = i_cur_remainder[i-1];
end
end
endgenerate
endmodule
module d_SC_serial_lfs_XOR_019(i_message, i_cur_remainder, o_nxt_remainder);
parameter [0:12] MIN_POLY = 13'b1110010111011;
input wire i_message;
input wire [`D_SC_GF_ORDER-1:0] i_cur_remainder;
output wire [`D_SC_GF_ORDER-1:0] o_nxt_remainder;
wire w_FB_term;
assign w_FB_term = i_cur_remainder[`D_SC_GF_ORDER-1];
assign o_nxt_remainder[0] = i_message ^ w_FB_term;
genvar i;
generate
for (i=1; i<`D_SC_GF_ORDER; i=i+1)
begin: linear_function
if (MIN_POLY[i] == 1)
begin
assign o_nxt_remainder[i] = i_cur_remainder[i-1] ^ w_FB_term;
end
else
begin
assign o_nxt_remainder[i] = i_cur_remainder[i-1];
end
end
endgenerate
endmodule
module d_SC_serial_lfs_XOR_021(i_message, i_cur_remainder, o_nxt_remainder);
parameter [0:12] MIN_POLY = 13'b1000000110101;
input wire i_message;
input wire [`D_SC_GF_ORDER-1:0] i_cur_remainder;
output wire [`D_SC_GF_ORDER-1:0] o_nxt_remainder;
wire w_FB_term;
assign w_FB_term = i_cur_remainder[`D_SC_GF_ORDER-1];
assign o_nxt_remainder[0] = i_message ^ w_FB_term;
genvar i;
generate
for (i=1; i<`D_SC_GF_ORDER; i=i+1)
begin: linear_function
if (MIN_POLY[i] == 1)
begin
assign o_nxt_remainder[i] = i_cur_remainder[i-1] ^ w_FB_term;
end
else
begin
assign o_nxt_remainder[i] = i_cur_remainder[i-1];
end
end
endgenerate
endmodule
module d_SC_serial_lfs_XOR_023(i_message, i_cur_remainder, o_nxt_remainder);
parameter [0:12] MIN_POLY = 13'b1100111001001;
input wire i_message;
input wire [`D_SC_GF_ORDER-1:0] i_cur_remainder;
output wire [`D_SC_GF_ORDER-1:0] o_nxt_remainder;
wire w_FB_term;
assign w_FB_term = i_cur_remainder[`D_SC_GF_ORDER-1];
assign o_nxt_remainder[0] = i_message ^ w_FB_term;
genvar i;
generate
for (i=1; i<`D_SC_GF_ORDER; i=i+1)
begin: linear_function
if (MIN_POLY[i] == 1)
begin
assign o_nxt_remainder[i] = i_cur_remainder[i-1] ^ w_FB_term;
end
else
begin
assign o_nxt_remainder[i] = i_cur_remainder[i-1];
end
end
endgenerate
endmodule
module d_SC_serial_lfs_XOR_025(i_message, i_cur_remainder, o_nxt_remainder);
parameter [0:12] MIN_POLY = 13'b1100100101101;
input wire i_message;
input wire [`D_SC_GF_ORDER-1:0] i_cur_remainder;
output wire [`D_SC_GF_ORDER-1:0] o_nxt_remainder;
wire w_FB_term;
assign w_FB_term = i_cur_remainder[`D_SC_GF_ORDER-1];
assign o_nxt_remainder[0] = i_message ^ w_FB_term;
genvar i;
generate
for (i=1; i<`D_SC_GF_ORDER; i=i+1)
begin: linear_function
if (MIN_POLY[i] == 1)
begin
assign o_nxt_remainder[i] = i_cur_remainder[i-1] ^ w_FB_term;
end
else
begin
assign o_nxt_remainder[i] = i_cur_remainder[i-1];
end
end
endgenerate
endmodule
module d_SC_serial_lfs_XOR_027(i_message, i_cur_remainder, o_nxt_remainder);
parameter [0:12] MIN_POLY = 13'b1011101001111;
input wire i_message;
input wire [`D_SC_GF_ORDER-1:0] i_cur_remainder;
output wire [`D_SC_GF_ORDER-1:0] o_nxt_remainder;
wire w_FB_term;
assign w_FB_term = i_cur_remainder[`D_SC_GF_ORDER-1];
assign o_nxt_remainder[0] = i_message ^ w_FB_term;
genvar i;
generate
for (i=1; i<`D_SC_GF_ORDER; i=i+1)
begin: linear_function
if (MIN_POLY[i] == 1)
begin
assign o_nxt_remainder[i] = i_cur_remainder[i-1] ^ w_FB_term;
end
else
begin
assign o_nxt_remainder[i] = i_cur_remainder[i-1];
end
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFRTN_SYMBOL_V
`define SKY130_FD_SC_HD__DFRTN_SYMBOL_V
/**
* dfrtn: Delay flop, inverted reset, inverted clock,
* complementary outputs.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dfrtn (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input CLK_N
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFRTN_SYMBOL_V
|
// megafunction wizard: %ALTFP_ABS%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: ALTFP_ABS
// ============================================================
// File Name: acl_fp_abs.v
// Megafunction Name(s):
// ALTFP_ABS
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.0 Build 262 08/18/2010 SP 1 SJ Full Version
// ************************************************************
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//altfp_abs CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix IV" PIPELINE=1 WIDTH_EXP=8 WIDTH_MAN=23 clk_en clock data result
//VERSION_BEGIN 10.0SP1 cbx_altfp_abs 2010:08:18:21:07:09:SJ cbx_mgl 2010:08:18:21:11:11:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//synthesis_resources = reg 31
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_abs_altfp_abs_j3b
(
clk_en,
clock,
data,
result) ;
input clk_en;
input clock;
input [31:0] data;
output [31:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clk_en;
tri0 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg [30:0] result_pipe;
wire aclr;
wire [31:0] data_w;
wire gnd_w;
// synopsys translate_off
initial
result_pipe = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) result_pipe <= 31'b0;
else if (clk_en == 1'b1) result_pipe <= data_w[30:0];
assign
aclr = 1'b0,
data_w = {gnd_w, data[30:0]},
gnd_w = 1'b0,
result = {data_w[31], result_pipe[30:0]};
endmodule //acl_fp_abs_altfp_abs_j3b
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module acl_fp_fabs (
enable,
clock,
dataa,
result);
input enable;
input clock;
input [31:0] dataa;
output [31:0] result;
wire [31:0] sub_wire0;
wire [31:0] result = sub_wire0[31:0];
acl_fp_abs_altfp_abs_j3b acl_fp_abs_altfp_abs_j3b_component (
.clk_en (enable),
.clock (clock),
.data (dataa),
.result (sub_wire0));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "UNUSED"
// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altfp_abs"
// Retrieval info: CONSTANT: PIPELINE NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_EXP NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_MAN NUMERIC "23"
// Retrieval info: USED_PORT: clk_en 0 0 0 0 INPUT NODEFVAL "clk_en"
// Retrieval info: CONNECT: @clk_en 0 0 0 0 clk_en 0 0 0 0
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
// Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL "result[31..0]"
// Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_abs.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_abs.qip TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_abs.bsf TRUE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_abs_inst.v FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_abs_bb.v FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_abs.inc FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_abs.cmp FALSE TRUE
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.4 (win64) Build 1071353 Tue Nov 18 18:29:27 MST 2014
// Date : Tue Jun 30 17:04:31 2015
// Host : Vangelis-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// C:/Users/Vfor/Documents/GitHub/Minesweeper_Vivado/Minesweeper_Vivado.srcs/sources_1/ip/Instructions/Instructions_funcsim.v
// Design : Instructions
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a100tcsg324-3
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "blk_mem_gen_v8_2,Vivado 2014.4" *) (* CHECK_LICENSE_TYPE = "Instructions,blk_mem_gen_v8_2,{}" *)
(* core_generation_info = "Instructions,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=3,x_ipLanguage=VHDL,x_ipSimLanguage=VHDL,C_FAMILY=artix7,C_XDEVICEFAMILY=artix7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=3,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=Instructions.mif,C_INIT_FILE=Instructions.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=800,C_READ_WIDTH_A=800,C_WRITE_DEPTH_A=600,C_READ_DEPTH_A=600,C_ADDRA_WIDTH=10,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=800,C_READ_WIDTH_B=800,C_WRITE_DEPTH_B=600,C_READ_DEPTH_B=600,C_ADDRB_WIDTH=10,C_HAS_MEM_OUTPUT_REGS_A=1,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=22,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 60.4532 mW}" *)
(* NotValidForBitStream *)
module Instructions
(clka,
addra,
douta);
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) input clka;
input [9:0]addra;
output [799:0]douta;
wire [9:0]addra;
wire clka;
wire [799:0]douta;
wire NLW_U0_dbiterr_UNCONNECTED;
wire NLW_U0_s_axi_arready_UNCONNECTED;
wire NLW_U0_s_axi_awready_UNCONNECTED;
wire NLW_U0_s_axi_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_dbiterr_UNCONNECTED;
wire NLW_U0_s_axi_rlast_UNCONNECTED;
wire NLW_U0_s_axi_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_sbiterr_UNCONNECTED;
wire NLW_U0_s_axi_wready_UNCONNECTED;
wire NLW_U0_sbiterr_UNCONNECTED;
wire [799:0]NLW_U0_doutb_UNCONNECTED;
wire [9:0]NLW_U0_rdaddrecc_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_bid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
wire [9:0]NLW_U0_s_axi_rdaddrecc_UNCONNECTED;
wire [799:0]NLW_U0_s_axi_rdata_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_rid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
(* C_ADDRA_WIDTH = "10" *)
(* C_ADDRB_WIDTH = "10" *)
(* C_ALGORITHM = "1" *)
(* C_AXI_ID_WIDTH = "4" *)
(* C_AXI_SLAVE_TYPE = "0" *)
(* C_AXI_TYPE = "1" *)
(* C_BYTE_SIZE = "9" *)
(* C_COMMON_CLK = "0" *)
(* C_COUNT_18K_BRAM = "1" *)
(* C_COUNT_36K_BRAM = "22" *)
(* C_CTRL_ECC_ALGO = "NONE" *)
(* C_DEFAULT_DATA = "0" *)
(* C_DISABLE_WARN_BHV_COLL = "0" *)
(* C_DISABLE_WARN_BHV_RANGE = "0" *)
(* C_ELABORATION_DIR = "./" *)
(* C_ENABLE_32BIT_ADDRESS = "0" *)
(* C_EN_ECC_PIPE = "0" *)
(* C_EN_SLEEP_PIN = "0" *)
(* C_EST_POWER_SUMMARY = "Estimated Power for IP : 60.4532 mW" *)
(* C_FAMILY = "artix7" *)
(* C_HAS_AXI_ID = "0" *)
(* C_HAS_ENA = "0" *)
(* C_HAS_ENB = "0" *)
(* C_HAS_INJECTERR = "0" *)
(* C_HAS_MEM_OUTPUT_REGS_A = "1" *)
(* C_HAS_MEM_OUTPUT_REGS_B = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_A = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
(* C_HAS_REGCEA = "0" *)
(* C_HAS_REGCEB = "0" *)
(* C_HAS_RSTA = "0" *)
(* C_HAS_RSTB = "0" *)
(* C_HAS_SOFTECC_INPUT_REGS_A = "0" *)
(* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
(* C_INITA_VAL = "0" *)
(* C_INITB_VAL = "0" *)
(* C_INIT_FILE = "Instructions.mem" *)
(* C_INIT_FILE_NAME = "Instructions.mif" *)
(* C_INTERFACE_TYPE = "0" *)
(* C_LOAD_INIT_FILE = "1" *)
(* C_MEM_TYPE = "3" *)
(* C_MUX_PIPELINE_STAGES = "0" *)
(* C_PRIM_TYPE = "1" *)
(* C_READ_DEPTH_A = "600" *)
(* C_READ_DEPTH_B = "600" *)
(* C_READ_WIDTH_A = "800" *)
(* C_READ_WIDTH_B = "800" *)
(* C_RSTRAM_A = "0" *)
(* C_RSTRAM_B = "0" *)
(* C_RST_PRIORITY_A = "CE" *)
(* C_RST_PRIORITY_B = "CE" *)
(* C_SIM_COLLISION_CHECK = "ALL" *)
(* C_USE_BRAM_BLOCK = "0" *)
(* C_USE_BYTE_WEA = "0" *)
(* C_USE_BYTE_WEB = "0" *)
(* C_USE_DEFAULT_DATA = "0" *)
(* C_USE_ECC = "0" *)
(* C_USE_SOFTECC = "0" *)
(* C_WEA_WIDTH = "1" *)
(* C_WEB_WIDTH = "1" *)
(* C_WRITE_DEPTH_A = "600" *)
(* C_WRITE_DEPTH_B = "600" *)
(* C_WRITE_MODE_A = "WRITE_FIRST" *)
(* C_WRITE_MODE_B = "WRITE_FIRST" *)
(* C_WRITE_WIDTH_A = "800" *)
(* C_WRITE_WIDTH_B = "800" *)
(* C_XDEVICEFAMILY = "artix7" *)
(* DONT_TOUCH *)
(* downgradeipidentifiedwarnings = "yes" *)
Instructions_blk_mem_gen_v8_2__parameterized0 U0
(.addra(addra),
.addrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.clka(clka),
.clkb(1'b0),
.dbiterr(NLW_U0_dbiterr_UNCONNECTED),
.dina({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.dinb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.douta(douta),
.doutb(NLW_U0_doutb_UNCONNECTED[799:0]),
.eccpipece(1'b0),
.ena(1'b0),
.enb(1'b0),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.rdaddrecc(NLW_U0_rdaddrecc_UNCONNECTED[9:0]),
.regcea(1'b0),
.regceb(1'b0),
.rsta(1'b0),
.rstb(1'b0),
.s_aclk(1'b0),
.s_aresetn(1'b0),
.s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arburst({1'b0,1'b0}),
.s_axi_arid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
.s_axi_arsize({1'b0,1'b0,1'b0}),
.s_axi_arvalid(1'b0),
.s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awburst({1'b0,1'b0}),
.s_axi_awid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
.s_axi_awsize({1'b0,1'b0,1'b0}),
.s_axi_awvalid(1'b0),
.s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[3:0]),
.s_axi_bready(1'b0),
.s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
.s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
.s_axi_dbiterr(NLW_U0_s_axi_dbiterr_UNCONNECTED),
.s_axi_injectdbiterr(1'b0),
.s_axi_injectsbiterr(1'b0),
.s_axi_rdaddrecc(NLW_U0_s_axi_rdaddrecc_UNCONNECTED[9:0]),
.s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[799:0]),
.s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[3:0]),
.s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
.s_axi_rready(1'b0),
.s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
.s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
.s_axi_sbiterr(NLW_U0_s_axi_sbiterr_UNCONNECTED),
.s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wlast(1'b0),
.s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
.s_axi_wstrb(1'b0),
.s_axi_wvalid(1'b0),
.sbiterr(NLW_U0_sbiterr_UNCONNECTED),
.sleep(1'b0),
.wea(1'b0),
.web(1'b0));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *)
module Instructions_blk_mem_gen_generic_cstr
(douta,
clka,
addra);
output [799:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [799:0]douta;
Instructions_blk_mem_gen_prim_width \ramloop[0].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[17:0]));
Instructions_blk_mem_gen_prim_width__parameterized9 \ramloop[10].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[377:342]));
Instructions_blk_mem_gen_prim_width__parameterized10 \ramloop[11].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[413:378]));
Instructions_blk_mem_gen_prim_width__parameterized11 \ramloop[12].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[449:414]));
Instructions_blk_mem_gen_prim_width__parameterized12 \ramloop[13].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[485:450]));
Instructions_blk_mem_gen_prim_width__parameterized13 \ramloop[14].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[521:486]));
Instructions_blk_mem_gen_prim_width__parameterized14 \ramloop[15].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[557:522]));
Instructions_blk_mem_gen_prim_width__parameterized15 \ramloop[16].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[593:558]));
Instructions_blk_mem_gen_prim_width__parameterized16 \ramloop[17].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[629:594]));
Instructions_blk_mem_gen_prim_width__parameterized17 \ramloop[18].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[665:630]));
Instructions_blk_mem_gen_prim_width__parameterized18 \ramloop[19].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[701:666]));
Instructions_blk_mem_gen_prim_width__parameterized0 \ramloop[1].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[53:18]));
Instructions_blk_mem_gen_prim_width__parameterized19 \ramloop[20].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[737:702]));
Instructions_blk_mem_gen_prim_width__parameterized20 \ramloop[21].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[773:738]));
Instructions_blk_mem_gen_prim_width__parameterized21 \ramloop[22].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[799:774]));
Instructions_blk_mem_gen_prim_width__parameterized1 \ramloop[2].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[89:54]));
Instructions_blk_mem_gen_prim_width__parameterized2 \ramloop[3].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[125:90]));
Instructions_blk_mem_gen_prim_width__parameterized3 \ramloop[4].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[161:126]));
Instructions_blk_mem_gen_prim_width__parameterized4 \ramloop[5].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[197:162]));
Instructions_blk_mem_gen_prim_width__parameterized5 \ramloop[6].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[233:198]));
Instructions_blk_mem_gen_prim_width__parameterized6 \ramloop[7].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[269:234]));
Instructions_blk_mem_gen_prim_width__parameterized7 \ramloop[8].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[305:270]));
Instructions_blk_mem_gen_prim_width__parameterized8 \ramloop[9].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[341:306]));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module Instructions_blk_mem_gen_prim_width
(douta,
clka,
addra);
output [17:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [17:0]douta;
Instructions_blk_mem_gen_prim_wrapper_init \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module Instructions_blk_mem_gen_prim_width__parameterized0
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
Instructions_blk_mem_gen_prim_wrapper_init__parameterized0 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module Instructions_blk_mem_gen_prim_width__parameterized1
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
Instructions_blk_mem_gen_prim_wrapper_init__parameterized1 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module Instructions_blk_mem_gen_prim_width__parameterized10
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
Instructions_blk_mem_gen_prim_wrapper_init__parameterized10 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module Instructions_blk_mem_gen_prim_width__parameterized11
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
Instructions_blk_mem_gen_prim_wrapper_init__parameterized11 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module Instructions_blk_mem_gen_prim_width__parameterized12
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
Instructions_blk_mem_gen_prim_wrapper_init__parameterized12 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module Instructions_blk_mem_gen_prim_width__parameterized13
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
Instructions_blk_mem_gen_prim_wrapper_init__parameterized13 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module Instructions_blk_mem_gen_prim_width__parameterized14
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
Instructions_blk_mem_gen_prim_wrapper_init__parameterized14 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module Instructions_blk_mem_gen_prim_width__parameterized15
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
Instructions_blk_mem_gen_prim_wrapper_init__parameterized15 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module Instructions_blk_mem_gen_prim_width__parameterized16
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
Instructions_blk_mem_gen_prim_wrapper_init__parameterized16 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module Instructions_blk_mem_gen_prim_width__parameterized17
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
Instructions_blk_mem_gen_prim_wrapper_init__parameterized17 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module Instructions_blk_mem_gen_prim_width__parameterized18
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
Instructions_blk_mem_gen_prim_wrapper_init__parameterized18 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module Instructions_blk_mem_gen_prim_width__parameterized19
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
Instructions_blk_mem_gen_prim_wrapper_init__parameterized19 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module Instructions_blk_mem_gen_prim_width__parameterized2
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
Instructions_blk_mem_gen_prim_wrapper_init__parameterized2 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module Instructions_blk_mem_gen_prim_width__parameterized20
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
Instructions_blk_mem_gen_prim_wrapper_init__parameterized20 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module Instructions_blk_mem_gen_prim_width__parameterized21
(douta,
clka,
addra);
output [25:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [25:0]douta;
Instructions_blk_mem_gen_prim_wrapper_init__parameterized21 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module Instructions_blk_mem_gen_prim_width__parameterized3
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
Instructions_blk_mem_gen_prim_wrapper_init__parameterized3 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module Instructions_blk_mem_gen_prim_width__parameterized4
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
Instructions_blk_mem_gen_prim_wrapper_init__parameterized4 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module Instructions_blk_mem_gen_prim_width__parameterized5
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
Instructions_blk_mem_gen_prim_wrapper_init__parameterized5 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module Instructions_blk_mem_gen_prim_width__parameterized6
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
Instructions_blk_mem_gen_prim_wrapper_init__parameterized6 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module Instructions_blk_mem_gen_prim_width__parameterized7
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
Instructions_blk_mem_gen_prim_wrapper_init__parameterized7 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module Instructions_blk_mem_gen_prim_width__parameterized8
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
Instructions_blk_mem_gen_prim_wrapper_init__parameterized8 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module Instructions_blk_mem_gen_prim_width__parameterized9
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
Instructions_blk_mem_gen_prim_wrapper_init__parameterized9 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module Instructions_blk_mem_gen_prim_wrapper_init
(douta,
clka,
addra);
output [17:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [17:0]douta;
wire [15:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED ;
wire [1:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB18E1 #(
.DOA_REG(1),
.DOB_REG(0),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(18'h00000),
.INIT_B(18'h00000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(18),
.READ_WIDTH_B(18),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(18'h00000),
.SRVAL_B(18'h00000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(18),
.WRITE_WIDTH_B(18))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram
(.ADDRARDADDR({addra,1'b0,1'b0,1'b0,1'b0}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0}),
.DOADO({douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED [15:0]),
.DOPADOP({douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED [1:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.WEA({1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module Instructions_blk_mem_gen_prim_wrapper_init__parameterized0
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module Instructions_blk_mem_gen_prim_wrapper_init__parameterized1
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000044000044000044000000000000000000000),
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.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h003C000007F0000007F000000000000000000000000000000000000000000000),
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.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module Instructions_blk_mem_gen_prim_wrapper_init__parameterized10
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h4400000000000000111177777777770000000000000000000000000000000000),
.INITP_02(256'h99DDDDBB111100000221111FFFFFFFFFFFFFF000000000000000448888CCCCCC),
.INITP_03(256'h0448888CCCCCC4400000000000000FFFF777777FFDD444400000000000CCBBBB),
.INITP_04(256'h0000088999999999999990000000000000003377773333331100000000000000),
.INITP_05(256'h0000000221111333333333333330000000000000007766666666665544440000),
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.INITP_07(256'h00000000000000000000000000555566666666EEEE666666666666AAAA999900),
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.INIT_0C(256'h01C3870F01C3870F01C3870F01C3870F01C381FC01C381FC0000000000000000),
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.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module Instructions_blk_mem_gen_prim_wrapper_init__parameterized11
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h1100000000000000880000880022880000000000000000000000000000000000),
.INITP_02(256'h0022000000220000000000055555555555555445511000000000550000110000),
.INITP_03(256'h05555555555555511554400000000AA0000220000AA000000000000000000000),
.INITP_04(256'h0110000AA0000000000AA000000000000000220000000000AA00000000000000),
.INITP_05(256'h000000000000055444444444455444400000000000AA0000AA0000AA00000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h00000000000000000000000000DDDD999999999999DDDD999999998888CCCC00),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h1E3F00001E3F00001E3CF8001E3CF800F83C7800F83C78000000000000000000),
.INIT_0D(256'hF83C0000F83C0000003C0000003C0000003C0000003C0000FE3C0000FE3C0000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h1E3C1FF01E3C1FF01E3C00001E3C00001E3C00001E3C00000000000000000000),
.INIT_10(256'h1E3C00F01E3C00F01E3C1FC01E3C1FC01E3C78001E3C78001E3C78001E3C7800),
.INIT_11(256'h0000000000000000000000000000000007F07FC007F07FC01E3C00F01E3C00F0),
.INIT_12(256'h0700070000000700000007000000000000000000000000000000000000000000),
.INIT_13(256'h0700070007000700070007001FFC7F001FFC7F00070000000700000007000700),
.INIT_14(256'h01FC7FF007000700070007000700070007000700070007000700070007000700),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000001FC7FF0),
.INIT_16(256'h000F0000000F00000003F8000003F80000000000000000000000000000000000),
.INIT_17(256'h000F003F000F003F003FF800003FF800000F0000000F0000000F003F000F003F),
.INIT_18(256'h0000000000000000000F003F000F003F000F00F0000F00F0000F00F0000F00F0),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h1E0078F0F80FE03FF80FE03F0000000000000000000000000000000000000000),
.INIT_1B(256'h1E3C78F01E3C78F01E3C78F01E0FF8F01E0FF8F01E0078F01E0078F01E0078F0),
.INIT_1C(256'h0000000000000000000000000000000000000000F80FF83FF80FF83F1E3C78F0),
.INIT_1D(256'h0000070001C07F0001C07F0001C0000001C00000000000000000000000000000),
.INIT_1E(256'h01C0070001C0070001C0070001C0070001C007001FC007001FC0070000000700),
.INIT_1F(256'h000000001FFC7FF01FFC7FF001C0070001C0070001C0070001C0070001C00700),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'hF83FF800F83FF800000F0000000F0000000F0000000F00000000000000000000),
.INIT_22(256'h1E0F00001E0F00001E0F00001E0F00001E0F00001E0F00001E0F00001E0F0000),
.INIT_23(256'h000000000000000000000000000000001E03F8001E03F8001E0F00001E0F0000),
.INIT_24(256'h000F000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h1E0F00F01E0F00F01E0F00F0F83FF8F0F83FF8F0000F0000000F0000000F0000),
.INIT_26(256'hF803F83F1E0F00F01E0F00F01E0F00F01E0F00F01E0F00F01E0F00F01E0F00F0),
.INIT_27(256'h00000000000001FC000001FC0000000F0000000F0000000300000003F803F83F),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'hFE0FE000FE0FE0001E3C00001E3C00001E3C00001E3C0000F80FF800F80FF800),
.INIT_2A(256'h0000000000000000F83FE000F83FE00000007800000078000000780000007800),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h070078F01FFC1FC01FFC1FC00700000007000000070000000700000000000000),
.INIT_2D(256'h070078F0070078F0070078F0070078F0070078F0070078F0070078F0070078F0),
.INIT_2E(256'h000000000000000000000000000000000000000001FC1FC001FC1FC0070078F0),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h80FF00FF80FF00FFFFF0000FFFF0000FFFF0000FFFF0000F0000000000000000),
.INIT_39(256'h80FF07F080FF07F080FF07F080FF07F080FF07F080FF07F080FF00FF80FF00FF),
.INIT_3A(256'h80FF07FF80FF07FFFFF007F0FFF007F0FFF007F0FFF007F080FF07F080FF07F0),
.INIT_3B(256'h80FF07F080FF07F080FF07F080FF07F080FF07F080FF07F080FF07FF80FF07FF),
.INIT_3C(256'h0000000000000000FFF007F0FFF007F0FFF007F0FFF007F080FF07F080FF07F0),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module Instructions_blk_mem_gen_prim_wrapper_init__parameterized12
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h888888000022000066FFFF777777770000000000000000000000000000000000),
.INITP_02(256'hFFFFFFEE000000000000000FF111111111155110000000000000000000000000),
.INITP_03(256'h08899999999999911110000000000EEEEEEAAEEFFFF8888000000000002266EE),
.INITP_04(256'h000000077BBBBFFFFFF7700000000000000077CCCCCCCCCC6600000000000000),
.INITP_05(256'h0000000000000CC4444CCCCEEEE00000000000000066DDDDEEEEEE7700000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000088888CCCCCEEEEECCCCC888880000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h01C3870F01C3870F01C3870F01C3870F7F0387037F0387030000000000000000),
.INIT_0D(256'h7FC0FE037FC0FE03E1C3870FE1C3870FE1C3870FE1C3870F7FC3870F7FC3870F),
.INIT_0E(256'h0000000000000000000FE000000FE000000078000000780000001E0000001E00),
.INIT_0F(256'h8000000080000000800000008000000080000000800000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module Instructions_blk_mem_gen_prim_wrapper_init__parameterized13
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
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.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module Instructions_blk_mem_gen_prim_wrapper_init__parameterized14
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h6600000000000000664400001122666600000000000000000000000000000000),
.INITP_02(256'hEEEEEEEE000000000000000662222333333EE00000000022222266BBBBFFFFFF),
.INITP_03(256'h077BBBBFFFFFF660000000000000099999999999999888800000000000AAEEEE),
.INITP_04(256'h0000000999999990000990000000000000009999999900009900000000000000),
.INITP_05(256'h0000000888888FFCCCCCCCCCCCC0022000000000007777777777775544440000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h00FF000000FF0000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h000F07FF000F07FF000380000003800001C3800001C3800001C3800001C38000),
.INIT_0D(256'h01FF800001FF800001C0000001C0000000F0000000F00000003C0000003C0000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h7F03FE037F03FE03000000000000000000000000000000000000000000000000),
.INIT_10(256'hE003870FE003870FFFC3870FFFC3870FE1C3870FE1C3870FE1C3870FE1C3870F),
.INIT_11(256'h000380000003800000038000000380007F03FE037F03FE03E003870FE003870F),
.INIT_12(256'h7800000000000000000000000000000000000000000000000003800000038000),
.INIT_13(256'h780387007803870078038700FFC0FE00FFC0FE00780000007800000078000000),
.INIT_14(256'h1FC0FE00780380007803800078038000780380007803FF007803FF0078038700),
.INIT_15(256'h000000000000000000000000000000000000000000000000000000001FC0FE00),
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.INIT_17(256'hE1C38000E1C38000E1C38000E1C38000E1C38000E1C3800081C3800081C38000),
.INIT_18(256'h000000000000000080FF800080FF8000E1C38000E1C38000E1C38000E1C38000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h8000070F800001FC800001FC8000000080000000800000008000000000000000),
.INIT_1B(256'h8000070F8000070080000700800007008000070080000700800007008000070F),
.INIT_1C(256'h0000000000000000000000000000000000000000800001FC800001FC8000070F),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'hFFC38703E1C3870FE1C3870FE1C3870FE1C3870F7F03FE037F03FE0300000000),
.INIT_1F(256'h000000007F03870F7F03870FE0038700E0038700E0038700E0038700FFC38703),
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.INIT_23(256'h00000000000000000000000000000000800001FF800001FFE000070FE000070F),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000F0000000F0000000FE00001FCE00001FC000000000000000000000000),
.INIT_26(256'h800001FFE000070FE000070FE000070FE000070F800001FF800001FF0000000F),
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.INIT_29(256'h01C387FF01C387FF01C3870F01C3870F01C3870F01C3870F01FF01FC01FF01FC),
.INIT_2A(256'h000000000000000001C381FC01C381FC01C3870001C3870001C3870001C38700),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'hE1C07800FF007803FF00780300007800000078000003F8000003F80000000000),
.INIT_2D(256'hE1C0780FE1C0780FE1C0780FE1C07803E1C07803E1C07800E1C07800E1C07800),
.INIT_2E(256'hE0000000E0000000E0000000E0000000E0000000FF03FF03FF03FF03E1C0780F),
.INIT_2F(256'h00000000000000000000000000000000000000000000000000000000E0000000),
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.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module Instructions_blk_mem_gen_prim_wrapper_init__parameterized15
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h1100000000000000220000220000220000000000000000000000000000000000),
.INITP_02(256'h0000000000000000044000055000011000055000000000000000554400110000),
.INITP_03(256'h0550000000000550000000000000022000022220000002200000002222220000),
.INITP_04(256'h0000000880000880000AA000000000000000AA0000880000AA00000000000000),
.INITP_05(256'h0000000000000444444444444444444000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h00007800000078000000780000007800000FE000000FE0000000000000000000),
.INIT_0D(256'h000FF800000FF800003C7800003C7800003C7800003C7800000FF800000FF800),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h1E0F1FC01E0F1FC0000000000000000000000000000000000000000000000000),
.INIT_10(256'h1ECF78001ECF78001ECF7FF01ECF7FF01ECF78F01ECF78F01ECF78F01ECF78F0),
.INIT_11(256'h00000000000000000000000000000000073C1FC0073C1FC0073C7800073C7800),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h1E3C00F01E3C00F01E3C00F007FC1FC007FC1FC0000000000000000000000000),
.INIT_14(256'h07FC1FF01E3C78F01E3C78F01E3C78F01E3C78F01E3C1FF01E3C1FF01E3C00F0),
.INIT_15(256'h000000001FF000001FF00000003C0000003C0000003C0000003C000007FC1FF0),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h003C78F0003C78F0003C78F0003C78F0003C78F0003C78F0003C783F003C783F),
.INIT_18(256'h0000E0000000E000000FE03F000FE03F003C78F0003C78F0003C78F0003C78F0),
.INIT_19(256'h0000000000000000000000000000000000FF000000FF00000003800000038000),
.INIT_1A(256'h003F7803003C78FF003C78FF003C780F003C780F000FE003000FE00300000000),
.INIT_1B(256'h003C7803003C7803003C7803003CF803003CF803000FE003000FE003003F7803),
.INIT_1C(256'h0000000000000000000000000000000000000000000FE003000FE003003C7803),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h1E3C78F01E3C78F01E3C78F01E3C78F01E3C78F007F07FC007F07FC000000000),
.INIT_1F(256'h0000780007F07FC007F07FC01E3C78F01E3C78F01E3C78F01E3C78F01E3C78F0),
.INIT_20(256'h0000000000000000000000000000780000007800000078000000780000007800),
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.INIT_22(256'h000F0000000F0000FE0F003FFE0F003F1E0F00F01E0F00F01E0F00F01E0F00F0),
.INIT_23(256'h00000000000000000000000000000000F803F8FFF803F8FF000F0000000F0000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h1E3C78F01E3C78F01E3C78F0F83FE03FF83FE03F000000000000000000000000),
.INIT_26(256'hF83C78FF003C7800003C7800003C7800003C7800FE3C783FFE3C783F1E3C78F0),
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.INIT_2C(256'h070000001FFC00001FFC00000700000007000000070000000700000000000000),
.INIT_2D(256'h0700000007000000070000000700000007000000070000000700000007000000),
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.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module Instructions_blk_mem_gen_prim_wrapper_init__parameterized16
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h9900000000000000EE1111222222BB0000000000000000000000000000000000),
.INITP_02(256'hEEEEEE770000000000000009988EEEEEEEEFF00000000000000099CCCCFFFFFF),
.INITP_03(256'h0CC4444CCCCEEEE00000000000000AAAAAABBBBFFEE000000000000000669999),
.INITP_04(256'h022222266FFFFFFFFFF660000000002211113333333333333300000000000000),
.INITP_05(256'h0000000000000DD4444555577770000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h1E0000001E0000001E0000001E00000000000000000000000000000000000000),
.INIT_0C(256'h1E0380001E0380001E0380001E038000FE00FF00FE00FF000000000000000000),
.INIT_0D(256'hFFC3FE00FFC3FE001E0007001E0007001E0007001E0007001E00FE001E00FE00),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h80FF01FF80FF01FF000000000000000000000000000000000000000000000000),
.INIT_10(256'hE1C0000FE1C0000FE1FF81FCE1FF81FCE1C38700E1C38700E1C38700E1C38700),
.INIT_11(256'h00000000000000000000000000000000E0FF07FCE0FF07FCE1C0000FE1C0000F),
.INIT_12(256'h000000F0000000F0000000F00000000000000000000000000000000000000000),
.INIT_13(256'hE1C380F0E1C380F0E1C380F081C387F081C387F00000000000000000000000F0),
.INIT_14(256'hE03C07FFE0FF00F0E0FF00F0E1C380F0E1C380F0E1C380F0E1C380F0E1C380F0),
.INIT_15(256'h00000000000000000000000000000000000000000000000000000000E03C07FF),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'hFFC0FE00FFC0FE00E1C38000E1C38000E1C38000E1C380007F00FF007F00FF00),
.INIT_18(256'h00000000000000007F03FE007F03FE00E0000700E0000700E0000700E0000700),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'hE7C38700E1C0FE00E1C0FE000000000000000000000000000000000000000000),
.INIT_1B(256'hE0038000E0038000E0038000E003FF00E003FF00F8038700F8038700E7C38700),
.INIT_1C(256'h0000000000000000000000000000000000000000E000FE00E000FE00E0038000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'hE1C00000E1F00000E1F00000E1CF8000E1CF800081C3800081C3800000000000),
.INIT_1F(256'h0000000081C0000081C0000001C0000001C0000001C0000001C00000E1C00000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000FF030000FF03000000000000000000000000000000000000000000000000),
.INIT_22(256'h0003870F0003870F0003870F0003870F0003870F0003870F0003870F0003870F),
.INIT_23(256'h000007000000070000000700000007000000FF030000FF030003870F0003870F),
.INIT_24(256'h0000000000000000000000000000000000000000000000000003FE000003FE00),
.INIT_25(256'hE1C3870FE1C3870FE1C3870F7F03FE037F03FE03000000000000000000000000),
.INIT_26(256'h7F03FE03E1C3870FE1C3870FE1C3870FE1C3870FE1C3870FE1C3870FE1C3870F),
.INIT_27(256'h000000000003800000038000000380000003800000038000000380007F03FE03),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h01CF870001C381FF01C381FF0000000000000000000000000000000000000000),
.INIT_2D(256'h01C0000F01C0000F01C0000F01C001FC01C001FC01F0070001F0070001CF8700),
.INIT_2E(256'h0000000000000000000000000000000000000000E1C007FCE1C007FC01C0000F),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module Instructions_blk_mem_gen_prim_wrapper_init__parameterized17
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'hEE44662200000000440000440000440000000000000000000000000000000000),
.INITP_02(256'hDD99884400000000000000000000000000022000000000000000666666666666),
.INITP_03(256'h2AA0000880000880000000000000011000011000011000000000000000CC8899),
.INITP_04(256'h0000000440000440000440000000000000001100001100005500000000000222),
.INITP_05(256'h0000000000000000000002200000022000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h1E0000001E0000001E0000001E00000007FC000007FC00000000000000000000),
.INIT_0D(256'h1FF000001FF00000003C0000003C0000003C0000003C000007F0000007F00000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h9F3F80FF9F3F80FF070000000700000007038000070380000003800000038000),
.INIT_10(256'h070380F0070380F0670380F0670380F0670380F0670380F0670380F0670380F0),
.INIT_11(256'h00000000000000000000000000000000073FF8F0073FF8F0070380F0070380F0),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h003C7800003C7800003C7800003FE03F003FE03F000000000000000000000000),
.INIT_14(256'h003C783F003C78F0003C78F0003C78F0003C78F0003C783F003C783F003C7800),
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.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module Instructions_blk_mem_gen_prim_wrapper_init__parameterized18
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INITP_03(256'h8FFCCCCCCCCCCCC00220000000000DD5555DDDDFFFF000000000000000111111),
.INITP_04(256'h0000000111111119911111199000000000000000000000000000000000088888),
.INITP_05(256'h0000000000000EEEEEEFFFFFFEE8888000000000000000000000000000000000),
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.INIT_0D(256'h01C387FF01C387FF01C380F001C380F001C380F001C380F001C380F001C380F0),
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.INIT_1C(256'h000000000000000000000000000000000000000081C001FC81C001FC01C00700),
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.INIT_1E(256'hE1C07803E1C07800E1C07800E1C07800E1C07800FF007803FF00780300007800),
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.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module Instructions_blk_mem_gen_prim_wrapper_init__parameterized19
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h00000000000000000000000000000888888888888AA888800000000000000000),
.INITP_04(256'h0000000222222222222222222000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000111111111111111111000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'hE03C78F0E03FE03FE03FE03FE03C0000E03C0000FE3C0000FE3C000000000000),
.INIT_1B(256'hE03C78F0E03C78F0E03C78F0E03C78FFE03C78FFE03C78F0E03C78F0E03C78F0),
.INIT_1C(256'h0000000000000000000000000000000000000000E03C783FE03C783FE03C78F0),
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.INIT_25(256'h000380FF0003803C0003803C0003803C0003803C0003803C0003803C000FE00F),
.INIT_26(256'h000FE03C0003803C0003803C0003803C0003803C0003803C0003803C000380FF),
.INIT_27(256'h00000000000000000000000000000000000000000000000000000000000FE03C),
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.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h000007000000070000000700000007000000070000007FF000007FF000000000),
.INIT_2D(256'h0000070000000700000007000000070000000700000007000000070000000700),
.INIT_2E(256'h0000000000000000000000000000000000000000000007000000070000000700),
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.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module Instructions_blk_mem_gen_prim_wrapper_init__parameterized2
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000004444666666880000000000000000000000000000000000),
.INITP_02(256'h00000000000000000000000CC444444888844000000000000000000000000000),
.INITP_03(256'h444440000000000000000000000008800000066000000AA00000000000000000),
.INITP_04(256'h0000000884444666666000000000000000000000000000000000000000000004),
.INITP_05(256'h0000000000000CC44444488AA662200000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h79C3800079C3800079C3800079C38000E0FF0000E0FF00000000000000000000),
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.INIT_1C(256'h000000000000000000000000000000000000000080F0000080F0000000F00000),
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.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
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.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module Instructions_blk_mem_gen_prim_wrapper_init__parameterized20
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h00000000000000000000000000000000000000000000000F0000000F00000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module Instructions_blk_mem_gen_prim_wrapper_init__parameterized21
(douta,
clka,
addra);
output [25:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [25:0]douta;
wire \n_12_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram ;
wire \n_20_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram ;
wire \n_21_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram ;
wire \n_28_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram ;
wire \n_4_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram ;
wire \n_5_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram ;
wire \n_68_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram ;
wire \n_69_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram ;
wire \n_70_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram ;
wire \n_71_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\n_4_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram ,\n_5_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram ,douta[25:20],\n_12_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram ,douta[19:13],\n_20_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram ,\n_21_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram ,douta[12:7],\n_28_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram ,douta[6:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({\n_68_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram ,\n_69_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram ,\n_70_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram ,\n_71_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram }),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module Instructions_blk_mem_gen_prim_wrapper_init__parameterized3
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h5500000000880000AA0000220000AA0000000000000000000000000000000000),
.INITP_02(256'h0000008800000000000000011000011000055000000000000000110000110000),
.INITP_03(256'h0440000000000550000000000000088880000000000000000000000000AA2200),
.INITP_04(256'h0000000AAAAAAAAAAAAAA88AA220000000008888000000000000000000000000),
.INITP_05(256'h00000000000004444CCCCCCCCDD0044440000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h1E0078F31E0078F31E0078F31E0078F3FE0FE0FFFE0FE0FF0000000000000000),
.INIT_0D(256'hFE0FF8F0FE0FF8F01E3C78F31E3C78F31E3C78F31E3C78F31E0FF8F31E0FF8F3),
.INIT_0E(256'h0000000000000000F8000000F80000001E0000001E0000001E0000001E000000),
.INIT_0F(256'h1FF01FF01FF01FF0000000000000000000000000000000000000000000000000),
.INIT_10(256'h1E3C00F01E3C00F01E3C1FC01E3C1FC01E3C78001E3C78001E3C78001E3C7800),
.INIT_11(256'h000000000000000000000000000000001E3C7FC01E3C7FC01E3C00F01E3C00F0),
.INIT_12(256'h1E00000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h1E3C78F01E3C78F01E3C78F01FF01FC01FF01FC01E0000001E0000001E000000),
.INIT_14(256'h1E3C1FC01E3C78001E3C78001E3C78001E3C78001E3C7FF01E3C7FF01E3C78F0),
.INIT_15(256'h000000000000000000000000000000000000000000000000000000001E3C1FC0),
.INIT_16(256'h1E0000001E0000001E0000001E00000000000000000000000000000000000000),
.INIT_17(256'h1E0000001E0000001E0000001E0000001E0000001E000000FE000000FE000000),
.INIT_18(256'h0000000000000000FE03E000FE03E0001E03E0001E03E0001E0000001E000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000F0000000F0000000F0000000F0000000F0000003F0000003F00000000),
.INIT_1B(256'hF800000F0000000F0000000F0000000F0000000F0000000F0000000F0000000F),
.INIT_1C(256'h0000000000000000000000000000000000000000F800003FF800003FF800000F),
.INIT_1D(256'h0000780000007800000078000000000000000000000000000000000000000000),
.INIT_1E(256'h1E0078F01E0078F01E0078F01E3C78F01E3C78F007F07FC007F07FC000007800),
.INIT_1F(256'h0000000007F078F007F078F01E3C78F01E3C78F01E0078F01E0078F01E0078F0),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h00000000000000000000000000000000F8000000F8000000F8000000F8000000),
.INIT_24(256'h800380FF00038000000380000000000000000000000000000000000000000000),
.INIT_25(256'h8003800F8003800F8003800FFE3F800FFE3F800F8000000F8000000F800380FF),
.INIT_26(256'hFE3FF8FF8003800F8003800F8003800F8003800F8003800F8003800F8003800F),
.INIT_27(256'h00000000000000000000000000000000000000000000000000000000FE3FF8FF),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h01C0000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h81C078F09FC07FC09FC07FC0000000000000000001C0000001C0000001C00000),
.INIT_2D(256'h01C078F081C078F081C078F081C078F081C078F081C078F081C078F081C078F0),
.INIT_2E(256'h00000000000000000000000000000000000000001FFC78F01FFC78F001C078F0),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module Instructions_blk_mem_gen_prim_wrapper_init__parameterized4
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'hFF00000000000000448888CCCCCC440000000000000000000000000000000000),
.INITP_02(256'h8888CCEE000000000000000BB111111111177000000000000000BB1111111111),
.INITP_03(256'h01177777766EE9900000000000000FFFFFFFFFFFFFF111100000000000BB8888),
.INITP_04(256'h000000044CCCCCCCCCC44444400000000000FF3333333333AA00000000000000),
.INITP_05(256'h0000000000000999999991111990000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'hE1C0000FE1C0000FE1C0000FE1C0000F7F0000037F0000030000000000000000),
.INIT_0D(256'h7F0000037F000003E000000FE000000FE000000FE000000FFFC0000FFFC0000F),
.INIT_0E(256'h00000000000000000000000F0000000F00000000000000000000000000000000),
.INIT_0F(256'hE1FF81FCE1FF81FC00F0000000F0000000F0000000F000000000000000000000),
.INIT_10(256'h00F0070F00F0070F00F0070F00F0070F00F0070F00F0070F00F0070F00F0070F),
.INIT_11(256'h00000000000000000000000000000000E03F81FCE03F81FC00F0070F00F0070F),
.INIT_12(256'h00F0000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h00F0070000F0070F00F0070F01FF81FC01FF81FC00F0000000F0000000F00000),
.INIT_14(256'hE03F81FC00F0070F00F0070F00F0070000F0070000F0070000F0070000F00700),
.INIT_15(256'h00000000000000000000000000000000000000000000000000000000E03F81FC),
.INIT_16(256'h0000000000000000000078000000780000007800000078000000000000000000),
.INIT_17(256'hE000780FE000780FF800780FF800780FE7C0780FE7C0780FE1C3F803E1C3F803),
.INIT_18(256'h0000000000000000E003FF03E003FF03E000780FE000780FE000780FE000780F),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'hE1C38700FF00FF00FF00FF000000070000000700000007000000070000000000),
.INIT_1B(256'hE1C38700E1C38700E1C38700E1C38700E1C38700E1C38700E1C38700E1C38700),
.INIT_1C(256'h0000000000000000000000000000000000000000E1C0FF00E1C0FF00E1C38700),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h01C381FF01C3800F01C3800FE1C3800FE1C3800FE0FF01FCE0FF01FC00000000),
.INIT_1F(256'h0000000000FF01FF00FF01FF01C3870F01C3870F01C3870F01C3870F01C381FF),
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.INIT_21(256'hFE03FE00FE03FE0000000000000000001E0000001E0000001E0000001E000000),
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.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module Instructions_blk_mem_gen_prim_wrapper_init__parameterized5
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
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.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module Instructions_blk_mem_gen_prim_wrapper_init__parameterized6
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'hCC8888000000000088888888EE88880022000000000000000000000000000000),
.INITP_02(256'h777777DD44440000000000088888888CCCCCCCCCC00000000000CCCCCCCCCCCC),
.INITP_03(256'h066FFBBBBBBFF660000000000000099111199999999110000000000000FF7777),
.INITP_04(256'h0000000557777777777DD4444000000000009999999900009900000000000000),
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.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h003F8000003F8000000000000000000000000000000000000000000000000000),
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.INIT_10(256'hE1C0000FE1C0000FE1C0000FE1C0000FE1C0000FE1C0000FE1C0000FE1C0000F),
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.INIT_1E(256'hE003870FE003870FE003870FE1C3870FE1C3870F7F00FE037F00FE0300000000),
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.INIT_2E(256'h00000000000000000000000000000000000000007F03FF0F7F03FF0FE1C0780F),
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.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module Instructions_blk_mem_gen_prim_wrapper_init__parameterized7
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h1100000000000000000000000000880000000000000000000000000000000000),
.INITP_02(256'h0000008800000000000000055111111111111115500000000000550000110000),
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.INITP_04(256'h000000022000000000088000000000002222AA00008800008800000000000000),
.INITP_05(256'h0000000000000110000000000110000000000000000000000088002200000000),
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.INIT_0C(256'h1E0000F01E0000F01E0000F01E0000F0F800003FF800003F0000000000000000),
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.INIT_1C(256'h0000000000000000000000000000000000000000003FE03F003FE03F003C78F0),
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.INIT_1E(256'h07FC0000003C0000003C0000003C0000003C000007F0000007F0000000000000),
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.INIT_25(256'h1E3C78F31E3C78F31E3C78F3F83C78FFF83C78FF000000000000000000000000),
.INIT_26(256'h1E0FF8F01E3C78F31E3C78F31E3C78F31E3C78F31E3C78F31E3C78F31E3C78F3),
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.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module Instructions_blk_mem_gen_prim_wrapper_init__parameterized8
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h9900000000000000EE3333333333AA0000000000000000000000000000000000),
.INITP_02(256'h0000002200000000000000088CCCCEEEEEE88000000000111111991111999999),
.INITP_03(256'h0EE6666666666CC44440000000000663333333333EE000000000000000330000),
.INITP_04(256'h000000044CCCC44444444000000000888888FFCCCCCCCCCCCC00220000000000),
.INITP_05(256'h000000000000022226666222233000000000000000773333333333FF00000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h1E0000001E0000001E0000001E00000000000000000000000000000000000000),
.INIT_0C(256'h1E03870F1E03870F1E03870F1E03870FFE00FE0FFE00FE0F0000000000000000),
.INIT_0D(256'hFFC0FE0FFFC0FE0F1E03870F1E03870F1E03870F1E03870F1E03870F1E03870F),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h800007FC800007FC000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000070F0000070FE000070FE000070FE000070FE000070FE000070FE000070F),
.INIT_11(256'h00000700000007000000070000000700800007FC800007FC0000070F0000070F),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000070000000700),
.INIT_13(256'hE1C38000E1C38000E1C3800080FF000080FF0000000000000000000000000000),
.INIT_14(256'hE0FF0000E1C00000E1C00000E1C00000E1C00000E1FF8000E1FF8000E1C38000),
.INIT_15(256'h00000000000000000000000000000000000000000000000000000000E0FF0000),
.INIT_16(256'h0000000000000000000078000000780000007800000078000000000000000000),
.INIT_17(256'h0000780F0000780F0000780F0000780F0000780F0000780F0003F80F0003F80F),
.INIT_18(256'h00000000000000000003FF0F0003FF0F0000780F0000780F0000780F0000780F),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h78038700FFC0FE00FFC0FE007800000078000000780000007800000000000000),
.INIT_1B(256'h7803870078038700780387007803870078038700780387007803870078038700),
.INIT_1C(256'h00000000000000000000000000000000000000001FC0FE001FC0FE0078038700),
.INIT_1D(256'h01C0000001C0000001C000000000000000000000000000000000000000000000),
.INIT_1E(256'h01C3800001C3800001C3800001C3800001C38000E1FF0000E1FF000001C00000),
.INIT_1F(256'h00000000E1C38000E1C3800001C3800001C3800001C3800001C3800001C38000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'hFF007803FF00780300007800000078000003F8000003F8000000000000000000),
.INIT_22(256'hE1C0780FE1C0780FE1C07803E1C07803E1C07800E1C07800E1C07800E1C07800),
.INIT_23(256'hE0000000E0000000E0000000E0000000FF03FF03FF03FF03E1C0780FE1C0780F),
.INIT_24(256'h000000000000000000000000000000000000000000000000E0000000E0000000),
.INIT_25(256'h01C0000F01C0000F01C0000F7F00000F7F00000F000000000000000000000000),
.INIT_26(256'h7FC0000FE1C0000FE1C0000FE1C0000FE1C0000F7FC0000F7FC0000F01C0000F),
.INIT_27(256'h000000000000000000000000000000000000000000000000000000007FC0000F),
.INIT_28(256'h7800000078000000780000007800000000000000000000000000000000000000),
.INIT_29(256'h7803870F7803870F7803870F7803870F7803870F7803870FFFC3870FFFC3870F),
.INIT_2A(256'h00000000000000001FC0FF0F1FC0FF0F7803870F7803870F7803870F7803870F),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h00F3803C00F387FC00F387FC00F000FC00F000FC00F0003C00F0003C00000000),
.INIT_2D(256'h0003803C01FFE03C01FFE03C01C3803C01C3803C00F3803C00F3803C00F3803C),
.INIT_2E(256'h00000000000000000000000000000000000000000003803C0003803C0003803C),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module Instructions_blk_mem_gen_prim_wrapper_init__parameterized9
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'hAA88880000000000110000114400110000000000000000000000000000000000),
.INITP_02(256'h4400114400000000000000022000000000022000000000000000888888888888),
.INITP_03(256'h0AAAA66666666660022220000000044000044000044000000000000000440000),
.INITP_04(256'h0000000000000004400000000000000000004400000000004400000000000000),
.INITP_05(256'h0000000000000AA0000880000AA0000000000000004400004400004400000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h00000000000000000000000000AAAAAAAABBBB333333333333BBBBAAAAAAAA00),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h1F0078001F0078001EFC78001EFC78001E3C1FF01E3C1FF00000000000000000),
.INIT_0D(256'h1E007FC01E007FC01E0000F01E0000F01E0000F01E0000F01E001FC01E001FC0),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'hFE3FE03FFE3FE03F803C0000803C0000803C0000803C00000000000000000000),
.INIT_10(256'h803C78F0803C78F0803C78FF803C78FF803C78F0803C78F0803C78F0803C78F0),
.INIT_11(256'h00000000000000000000000000000000FE3C783FFE3C783F803C78F0803C78F0),
.INIT_12(256'h000F00F000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h000F00F0000F00F0000F00F0003FF8FF003FF8FF000F00F0000F00F0000F00F0),
.INIT_14(256'h0003F8F0000F00F0000F00F0000F00F0000F00F0000F00F0000F00F0000F00F0),
.INIT_15(256'h000000000000000000000000000000000000000000000000000000000003F8F0),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h1FFC78001FFC78001E3C7E001E3C7E001E3C79F01E3C79F007F078F007F078F0),
.INIT_18(256'h000000000000000007F0780007F078001E0078001E0078001E0078001E007800),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h1E00000007FC000007FC00000000000000000000000000000000000000000000),
.INIT_1B(256'h003C0000003C0000003C000007F0000007F000001E0000001E0000001E000000),
.INIT_1C(256'h00000000000000000000000000000000000000001FF000001FF00000003C0000),
.INIT_1D(256'h0000003C0003803C0003803C0003800000038000000000000000000000000000),
.INIT_1E(256'h6703803C6703803C6703803C6703803C6703803C073F80FF073F80FF0000003C),
.INIT_1F(256'h000000009E3FF80F9E3FF80F9E03803C9E03803C6703803C6703803C6703803C),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h07FC000007FC0000003C0000003C0000003C0000003C00000000000000000000),
.INIT_22(256'h1E3C00001E3C00001E3C00001E3C00001E3C00001E3C00001E3C00001E3C0000),
.INIT_23(256'h0000000000000000000000000000000007FC000007FC00001E3C00001E3C0000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h1F0000001EFC00001EFC00001E3C00001E3C0000000000000000000000000000),
.INIT_26(256'h1E0000001E0000001E0000001E0000001E0000001E0000001E0000001F000000),
.INIT_27(256'h000000000000000000000000000000000000000000000000000000001E000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h07F0000007F000001E0000001E0000001E0000001E00000007FC000007FC0000),
.INIT_2A(256'h00000000000000001FF000001FF00000003C0000003C0000003C0000003C0000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h1E0F0000F83FF800F83FF800000F0000000F0000000F0000000F000000000000),
.INIT_2D(256'h000F0000000F0000000F0000FE0F0000FE0F00001E0F00001E0F00001E0F0000),
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.INIT_3A(256'h003F87F0003F87F0003FFF00003FFF00003FFF00003FFF00003F87F0003F87F0),
.INIT_3B(256'hF83F80FFF83F80FFF83F87F0F83F87F0F83F87F0F83F87F0003F87F0003F87F0),
.INIT_3C(256'h0000000000000000803F80FF803F80FF803F80FF803F80FFF83F80FFF83F80FF),
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.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_top" *)
module Instructions_blk_mem_gen_top
(douta,
clka,
addra);
output [799:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [799:0]douta;
Instructions_blk_mem_gen_generic_cstr \valid.cstr
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_2" *) (* C_FAMILY = "artix7" *) (* C_XDEVICEFAMILY = "artix7" *)
(* C_ELABORATION_DIR = "./" *) (* C_INTERFACE_TYPE = "0" *) (* C_AXI_TYPE = "1" *)
(* C_AXI_SLAVE_TYPE = "0" *) (* C_USE_BRAM_BLOCK = "0" *) (* C_ENABLE_32BIT_ADDRESS = "0" *)
(* C_CTRL_ECC_ALGO = "NONE" *) (* C_HAS_AXI_ID = "0" *) (* C_AXI_ID_WIDTH = "4" *)
(* C_MEM_TYPE = "3" *) (* C_BYTE_SIZE = "9" *) (* C_ALGORITHM = "1" *)
(* C_PRIM_TYPE = "1" *) (* C_LOAD_INIT_FILE = "1" *) (* C_INIT_FILE_NAME = "Instructions.mif" *)
(* C_INIT_FILE = "Instructions.mem" *) (* C_USE_DEFAULT_DATA = "0" *) (* C_DEFAULT_DATA = "0" *)
(* C_HAS_RSTA = "0" *) (* C_RST_PRIORITY_A = "CE" *) (* C_RSTRAM_A = "0" *)
(* C_INITA_VAL = "0" *) (* C_HAS_ENA = "0" *) (* C_HAS_REGCEA = "0" *)
(* C_USE_BYTE_WEA = "0" *) (* C_WEA_WIDTH = "1" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *)
(* C_WRITE_WIDTH_A = "800" *) (* C_READ_WIDTH_A = "800" *) (* C_WRITE_DEPTH_A = "600" *)
(* C_READ_DEPTH_A = "600" *) (* C_ADDRA_WIDTH = "10" *) (* C_HAS_RSTB = "0" *)
(* C_RST_PRIORITY_B = "CE" *) (* C_RSTRAM_B = "0" *) (* C_INITB_VAL = "0" *)
(* C_HAS_ENB = "0" *) (* C_HAS_REGCEB = "0" *) (* C_USE_BYTE_WEB = "0" *)
(* C_WEB_WIDTH = "1" *) (* C_WRITE_MODE_B = "WRITE_FIRST" *) (* C_WRITE_WIDTH_B = "800" *)
(* C_READ_WIDTH_B = "800" *) (* C_WRITE_DEPTH_B = "600" *) (* C_READ_DEPTH_B = "600" *)
(* C_ADDRB_WIDTH = "10" *) (* C_HAS_MEM_OUTPUT_REGS_A = "1" *) (* C_HAS_MEM_OUTPUT_REGS_B = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_A = "0" *) (* C_HAS_MUX_OUTPUT_REGS_B = "0" *) (* C_MUX_PIPELINE_STAGES = "0" *)
(* C_HAS_SOFTECC_INPUT_REGS_A = "0" *) (* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *) (* C_USE_SOFTECC = "0" *)
(* C_USE_ECC = "0" *) (* C_EN_ECC_PIPE = "0" *) (* C_HAS_INJECTERR = "0" *)
(* C_SIM_COLLISION_CHECK = "ALL" *) (* C_COMMON_CLK = "0" *) (* C_DISABLE_WARN_BHV_COLL = "0" *)
(* C_EN_SLEEP_PIN = "0" *) (* C_DISABLE_WARN_BHV_RANGE = "0" *) (* C_COUNT_36K_BRAM = "22" *)
(* C_COUNT_18K_BRAM = "1" *) (* C_EST_POWER_SUMMARY = "Estimated Power for IP : 60.4532 mW" *) (* downgradeipidentifiedwarnings = "yes" *)
module Instructions_blk_mem_gen_v8_2__parameterized0
(clka,
rsta,
ena,
regcea,
wea,
addra,
dina,
douta,
clkb,
rstb,
enb,
regceb,
web,
addrb,
dinb,
doutb,
injectsbiterr,
injectdbiterr,
eccpipece,
sbiterr,
dbiterr,
rdaddrecc,
sleep,
s_aclk,
s_aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
s_axi_injectsbiterr,
s_axi_injectdbiterr,
s_axi_sbiterr,
s_axi_dbiterr,
s_axi_rdaddrecc);
input clka;
input rsta;
input ena;
input regcea;
input [0:0]wea;
input [9:0]addra;
input [799:0]dina;
output [799:0]douta;
input clkb;
input rstb;
input enb;
input regceb;
input [0:0]web;
input [9:0]addrb;
input [799:0]dinb;
output [799:0]doutb;
input injectsbiterr;
input injectdbiterr;
input eccpipece;
output sbiterr;
output dbiterr;
output [9:0]rdaddrecc;
input sleep;
input s_aclk;
input s_aresetn;
input [3:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input s_axi_awvalid;
output s_axi_awready;
input [799:0]s_axi_wdata;
input [0:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [3:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [3:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input s_axi_arvalid;
output s_axi_arready;
output [3:0]s_axi_rid;
output [799:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
input s_axi_injectsbiterr;
input s_axi_injectdbiterr;
output s_axi_sbiterr;
output s_axi_dbiterr;
output [9:0]s_axi_rdaddrecc;
wire \<const0> ;
wire [9:0]addra;
wire [9:0]addrb;
wire clka;
wire clkb;
wire [799:0]dina;
wire [799:0]dinb;
wire [799:0]douta;
wire eccpipece;
wire ena;
wire enb;
wire injectdbiterr;
wire injectsbiterr;
wire regcea;
wire regceb;
wire rsta;
wire rstb;
wire s_aclk;
wire s_aresetn;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [3:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire [2:0]s_axi_arsize;
wire s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [3:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire [2:0]s_axi_awsize;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_injectdbiterr;
wire s_axi_injectsbiterr;
wire s_axi_rready;
wire [799:0]s_axi_wdata;
wire s_axi_wlast;
wire [0:0]s_axi_wstrb;
wire s_axi_wvalid;
wire sleep;
wire [0:0]wea;
wire [0:0]web;
assign dbiterr = \<const0> ;
assign doutb[799] = \<const0> ;
assign doutb[798] = \<const0> ;
assign doutb[797] = \<const0> ;
assign doutb[796] = \<const0> ;
assign doutb[795] = \<const0> ;
assign doutb[794] = \<const0> ;
assign doutb[793] = \<const0> ;
assign doutb[792] = \<const0> ;
assign doutb[791] = \<const0> ;
assign doutb[790] = \<const0> ;
assign doutb[789] = \<const0> ;
assign doutb[788] = \<const0> ;
assign doutb[787] = \<const0> ;
assign doutb[786] = \<const0> ;
assign doutb[785] = \<const0> ;
assign doutb[784] = \<const0> ;
assign doutb[783] = \<const0> ;
assign doutb[782] = \<const0> ;
assign doutb[781] = \<const0> ;
assign doutb[780] = \<const0> ;
assign doutb[779] = \<const0> ;
assign doutb[778] = \<const0> ;
assign doutb[777] = \<const0> ;
assign doutb[776] = \<const0> ;
assign doutb[775] = \<const0> ;
assign doutb[774] = \<const0> ;
assign doutb[773] = \<const0> ;
assign doutb[772] = \<const0> ;
assign doutb[771] = \<const0> ;
assign doutb[770] = \<const0> ;
assign doutb[769] = \<const0> ;
assign doutb[768] = \<const0> ;
assign doutb[767] = \<const0> ;
assign doutb[766] = \<const0> ;
assign doutb[765] = \<const0> ;
assign doutb[764] = \<const0> ;
assign doutb[763] = \<const0> ;
assign doutb[762] = \<const0> ;
assign doutb[761] = \<const0> ;
assign doutb[760] = \<const0> ;
assign doutb[759] = \<const0> ;
assign doutb[758] = \<const0> ;
assign doutb[757] = \<const0> ;
assign doutb[756] = \<const0> ;
assign doutb[755] = \<const0> ;
assign doutb[754] = \<const0> ;
assign doutb[753] = \<const0> ;
assign doutb[752] = \<const0> ;
assign doutb[751] = \<const0> ;
assign doutb[750] = \<const0> ;
assign doutb[749] = \<const0> ;
assign doutb[748] = \<const0> ;
assign doutb[747] = \<const0> ;
assign doutb[746] = \<const0> ;
assign doutb[745] = \<const0> ;
assign doutb[744] = \<const0> ;
assign doutb[743] = \<const0> ;
assign doutb[742] = \<const0> ;
assign doutb[741] = \<const0> ;
assign doutb[740] = \<const0> ;
assign doutb[739] = \<const0> ;
assign doutb[738] = \<const0> ;
assign doutb[737] = \<const0> ;
assign doutb[736] = \<const0> ;
assign doutb[735] = \<const0> ;
assign doutb[734] = \<const0> ;
assign doutb[733] = \<const0> ;
assign doutb[732] = \<const0> ;
assign doutb[731] = \<const0> ;
assign doutb[730] = \<const0> ;
assign doutb[729] = \<const0> ;
assign doutb[728] = \<const0> ;
assign doutb[727] = \<const0> ;
assign doutb[726] = \<const0> ;
assign doutb[725] = \<const0> ;
assign doutb[724] = \<const0> ;
assign doutb[723] = \<const0> ;
assign doutb[722] = \<const0> ;
assign doutb[721] = \<const0> ;
assign doutb[720] = \<const0> ;
assign doutb[719] = \<const0> ;
assign doutb[718] = \<const0> ;
assign doutb[717] = \<const0> ;
assign doutb[716] = \<const0> ;
assign doutb[715] = \<const0> ;
assign doutb[714] = \<const0> ;
assign doutb[713] = \<const0> ;
assign doutb[712] = \<const0> ;
assign doutb[711] = \<const0> ;
assign doutb[710] = \<const0> ;
assign doutb[709] = \<const0> ;
assign doutb[708] = \<const0> ;
assign doutb[707] = \<const0> ;
assign doutb[706] = \<const0> ;
assign doutb[705] = \<const0> ;
assign doutb[704] = \<const0> ;
assign doutb[703] = \<const0> ;
assign doutb[702] = \<const0> ;
assign doutb[701] = \<const0> ;
assign doutb[700] = \<const0> ;
assign doutb[699] = \<const0> ;
assign doutb[698] = \<const0> ;
assign doutb[697] = \<const0> ;
assign doutb[696] = \<const0> ;
assign doutb[695] = \<const0> ;
assign doutb[694] = \<const0> ;
assign doutb[693] = \<const0> ;
assign doutb[692] = \<const0> ;
assign doutb[691] = \<const0> ;
assign doutb[690] = \<const0> ;
assign doutb[689] = \<const0> ;
assign doutb[688] = \<const0> ;
assign doutb[687] = \<const0> ;
assign doutb[686] = \<const0> ;
assign doutb[685] = \<const0> ;
assign doutb[684] = \<const0> ;
assign doutb[683] = \<const0> ;
assign doutb[682] = \<const0> ;
assign doutb[681] = \<const0> ;
assign doutb[680] = \<const0> ;
assign doutb[679] = \<const0> ;
assign doutb[678] = \<const0> ;
assign doutb[677] = \<const0> ;
assign doutb[676] = \<const0> ;
assign doutb[675] = \<const0> ;
assign doutb[674] = \<const0> ;
assign doutb[673] = \<const0> ;
assign doutb[672] = \<const0> ;
assign doutb[671] = \<const0> ;
assign doutb[670] = \<const0> ;
assign doutb[669] = \<const0> ;
assign doutb[668] = \<const0> ;
assign doutb[667] = \<const0> ;
assign doutb[666] = \<const0> ;
assign doutb[665] = \<const0> ;
assign doutb[664] = \<const0> ;
assign doutb[663] = \<const0> ;
assign doutb[662] = \<const0> ;
assign doutb[661] = \<const0> ;
assign doutb[660] = \<const0> ;
assign doutb[659] = \<const0> ;
assign doutb[658] = \<const0> ;
assign doutb[657] = \<const0> ;
assign doutb[656] = \<const0> ;
assign doutb[655] = \<const0> ;
assign doutb[654] = \<const0> ;
assign doutb[653] = \<const0> ;
assign doutb[652] = \<const0> ;
assign doutb[651] = \<const0> ;
assign doutb[650] = \<const0> ;
assign doutb[649] = \<const0> ;
assign doutb[648] = \<const0> ;
assign doutb[647] = \<const0> ;
assign doutb[646] = \<const0> ;
assign doutb[645] = \<const0> ;
assign doutb[644] = \<const0> ;
assign doutb[643] = \<const0> ;
assign doutb[642] = \<const0> ;
assign doutb[641] = \<const0> ;
assign doutb[640] = \<const0> ;
assign doutb[639] = \<const0> ;
assign doutb[638] = \<const0> ;
assign doutb[637] = \<const0> ;
assign doutb[636] = \<const0> ;
assign doutb[635] = \<const0> ;
assign doutb[634] = \<const0> ;
assign doutb[633] = \<const0> ;
assign doutb[632] = \<const0> ;
assign doutb[631] = \<const0> ;
assign doutb[630] = \<const0> ;
assign doutb[629] = \<const0> ;
assign doutb[628] = \<const0> ;
assign doutb[627] = \<const0> ;
assign doutb[626] = \<const0> ;
assign doutb[625] = \<const0> ;
assign doutb[624] = \<const0> ;
assign doutb[623] = \<const0> ;
assign doutb[622] = \<const0> ;
assign doutb[621] = \<const0> ;
assign doutb[620] = \<const0> ;
assign doutb[619] = \<const0> ;
assign doutb[618] = \<const0> ;
assign doutb[617] = \<const0> ;
assign doutb[616] = \<const0> ;
assign doutb[615] = \<const0> ;
assign doutb[614] = \<const0> ;
assign doutb[613] = \<const0> ;
assign doutb[612] = \<const0> ;
assign doutb[611] = \<const0> ;
assign doutb[610] = \<const0> ;
assign doutb[609] = \<const0> ;
assign doutb[608] = \<const0> ;
assign doutb[607] = \<const0> ;
assign doutb[606] = \<const0> ;
assign doutb[605] = \<const0> ;
assign doutb[604] = \<const0> ;
assign doutb[603] = \<const0> ;
assign doutb[602] = \<const0> ;
assign doutb[601] = \<const0> ;
assign doutb[600] = \<const0> ;
assign doutb[599] = \<const0> ;
assign doutb[598] = \<const0> ;
assign doutb[597] = \<const0> ;
assign doutb[596] = \<const0> ;
assign doutb[595] = \<const0> ;
assign doutb[594] = \<const0> ;
assign doutb[593] = \<const0> ;
assign doutb[592] = \<const0> ;
assign doutb[591] = \<const0> ;
assign doutb[590] = \<const0> ;
assign doutb[589] = \<const0> ;
assign doutb[588] = \<const0> ;
assign doutb[587] = \<const0> ;
assign doutb[586] = \<const0> ;
assign doutb[585] = \<const0> ;
assign doutb[584] = \<const0> ;
assign doutb[583] = \<const0> ;
assign doutb[582] = \<const0> ;
assign doutb[581] = \<const0> ;
assign doutb[580] = \<const0> ;
assign doutb[579] = \<const0> ;
assign doutb[578] = \<const0> ;
assign doutb[577] = \<const0> ;
assign doutb[576] = \<const0> ;
assign doutb[575] = \<const0> ;
assign doutb[574] = \<const0> ;
assign doutb[573] = \<const0> ;
assign doutb[572] = \<const0> ;
assign doutb[571] = \<const0> ;
assign doutb[570] = \<const0> ;
assign doutb[569] = \<const0> ;
assign doutb[568] = \<const0> ;
assign doutb[567] = \<const0> ;
assign doutb[566] = \<const0> ;
assign doutb[565] = \<const0> ;
assign doutb[564] = \<const0> ;
assign doutb[563] = \<const0> ;
assign doutb[562] = \<const0> ;
assign doutb[561] = \<const0> ;
assign doutb[560] = \<const0> ;
assign doutb[559] = \<const0> ;
assign doutb[558] = \<const0> ;
assign doutb[557] = \<const0> ;
assign doutb[556] = \<const0> ;
assign doutb[555] = \<const0> ;
assign doutb[554] = \<const0> ;
assign doutb[553] = \<const0> ;
assign doutb[552] = \<const0> ;
assign doutb[551] = \<const0> ;
assign doutb[550] = \<const0> ;
assign doutb[549] = \<const0> ;
assign doutb[548] = \<const0> ;
assign doutb[547] = \<const0> ;
assign doutb[546] = \<const0> ;
assign doutb[545] = \<const0> ;
assign doutb[544] = \<const0> ;
assign doutb[543] = \<const0> ;
assign doutb[542] = \<const0> ;
assign doutb[541] = \<const0> ;
assign doutb[540] = \<const0> ;
assign doutb[539] = \<const0> ;
assign doutb[538] = \<const0> ;
assign doutb[537] = \<const0> ;
assign doutb[536] = \<const0> ;
assign doutb[535] = \<const0> ;
assign doutb[534] = \<const0> ;
assign doutb[533] = \<const0> ;
assign doutb[532] = \<const0> ;
assign doutb[531] = \<const0> ;
assign doutb[530] = \<const0> ;
assign doutb[529] = \<const0> ;
assign doutb[528] = \<const0> ;
assign doutb[527] = \<const0> ;
assign doutb[526] = \<const0> ;
assign doutb[525] = \<const0> ;
assign doutb[524] = \<const0> ;
assign doutb[523] = \<const0> ;
assign doutb[522] = \<const0> ;
assign doutb[521] = \<const0> ;
assign doutb[520] = \<const0> ;
assign doutb[519] = \<const0> ;
assign doutb[518] = \<const0> ;
assign doutb[517] = \<const0> ;
assign doutb[516] = \<const0> ;
assign doutb[515] = \<const0> ;
assign doutb[514] = \<const0> ;
assign doutb[513] = \<const0> ;
assign doutb[512] = \<const0> ;
assign doutb[511] = \<const0> ;
assign doutb[510] = \<const0> ;
assign doutb[509] = \<const0> ;
assign doutb[508] = \<const0> ;
assign doutb[507] = \<const0> ;
assign doutb[506] = \<const0> ;
assign doutb[505] = \<const0> ;
assign doutb[504] = \<const0> ;
assign doutb[503] = \<const0> ;
assign doutb[502] = \<const0> ;
assign doutb[501] = \<const0> ;
assign doutb[500] = \<const0> ;
assign doutb[499] = \<const0> ;
assign doutb[498] = \<const0> ;
assign doutb[497] = \<const0> ;
assign doutb[496] = \<const0> ;
assign doutb[495] = \<const0> ;
assign doutb[494] = \<const0> ;
assign doutb[493] = \<const0> ;
assign doutb[492] = \<const0> ;
assign doutb[491] = \<const0> ;
assign doutb[490] = \<const0> ;
assign doutb[489] = \<const0> ;
assign doutb[488] = \<const0> ;
assign doutb[487] = \<const0> ;
assign doutb[486] = \<const0> ;
assign doutb[485] = \<const0> ;
assign doutb[484] = \<const0> ;
assign doutb[483] = \<const0> ;
assign doutb[482] = \<const0> ;
assign doutb[481] = \<const0> ;
assign doutb[480] = \<const0> ;
assign doutb[479] = \<const0> ;
assign doutb[478] = \<const0> ;
assign doutb[477] = \<const0> ;
assign doutb[476] = \<const0> ;
assign doutb[475] = \<const0> ;
assign doutb[474] = \<const0> ;
assign doutb[473] = \<const0> ;
assign doutb[472] = \<const0> ;
assign doutb[471] = \<const0> ;
assign doutb[470] = \<const0> ;
assign doutb[469] = \<const0> ;
assign doutb[468] = \<const0> ;
assign doutb[467] = \<const0> ;
assign doutb[466] = \<const0> ;
assign doutb[465] = \<const0> ;
assign doutb[464] = \<const0> ;
assign doutb[463] = \<const0> ;
assign doutb[462] = \<const0> ;
assign doutb[461] = \<const0> ;
assign doutb[460] = \<const0> ;
assign doutb[459] = \<const0> ;
assign doutb[458] = \<const0> ;
assign doutb[457] = \<const0> ;
assign doutb[456] = \<const0> ;
assign doutb[455] = \<const0> ;
assign doutb[454] = \<const0> ;
assign doutb[453] = \<const0> ;
assign doutb[452] = \<const0> ;
assign doutb[451] = \<const0> ;
assign doutb[450] = \<const0> ;
assign doutb[449] = \<const0> ;
assign doutb[448] = \<const0> ;
assign doutb[447] = \<const0> ;
assign doutb[446] = \<const0> ;
assign doutb[445] = \<const0> ;
assign doutb[444] = \<const0> ;
assign doutb[443] = \<const0> ;
assign doutb[442] = \<const0> ;
assign doutb[441] = \<const0> ;
assign doutb[440] = \<const0> ;
assign doutb[439] = \<const0> ;
assign doutb[438] = \<const0> ;
assign doutb[437] = \<const0> ;
assign doutb[436] = \<const0> ;
assign doutb[435] = \<const0> ;
assign doutb[434] = \<const0> ;
assign doutb[433] = \<const0> ;
assign doutb[432] = \<const0> ;
assign doutb[431] = \<const0> ;
assign doutb[430] = \<const0> ;
assign doutb[429] = \<const0> ;
assign doutb[428] = \<const0> ;
assign doutb[427] = \<const0> ;
assign doutb[426] = \<const0> ;
assign doutb[425] = \<const0> ;
assign doutb[424] = \<const0> ;
assign doutb[423] = \<const0> ;
assign doutb[422] = \<const0> ;
assign doutb[421] = \<const0> ;
assign doutb[420] = \<const0> ;
assign doutb[419] = \<const0> ;
assign doutb[418] = \<const0> ;
assign doutb[417] = \<const0> ;
assign doutb[416] = \<const0> ;
assign doutb[415] = \<const0> ;
assign doutb[414] = \<const0> ;
assign doutb[413] = \<const0> ;
assign doutb[412] = \<const0> ;
assign doutb[411] = \<const0> ;
assign doutb[410] = \<const0> ;
assign doutb[409] = \<const0> ;
assign doutb[408] = \<const0> ;
assign doutb[407] = \<const0> ;
assign doutb[406] = \<const0> ;
assign doutb[405] = \<const0> ;
assign doutb[404] = \<const0> ;
assign doutb[403] = \<const0> ;
assign doutb[402] = \<const0> ;
assign doutb[401] = \<const0> ;
assign doutb[400] = \<const0> ;
assign doutb[399] = \<const0> ;
assign doutb[398] = \<const0> ;
assign doutb[397] = \<const0> ;
assign doutb[396] = \<const0> ;
assign doutb[395] = \<const0> ;
assign doutb[394] = \<const0> ;
assign doutb[393] = \<const0> ;
assign doutb[392] = \<const0> ;
assign doutb[391] = \<const0> ;
assign doutb[390] = \<const0> ;
assign doutb[389] = \<const0> ;
assign doutb[388] = \<const0> ;
assign doutb[387] = \<const0> ;
assign doutb[386] = \<const0> ;
assign doutb[385] = \<const0> ;
assign doutb[384] = \<const0> ;
assign doutb[383] = \<const0> ;
assign doutb[382] = \<const0> ;
assign doutb[381] = \<const0> ;
assign doutb[380] = \<const0> ;
assign doutb[379] = \<const0> ;
assign doutb[378] = \<const0> ;
assign doutb[377] = \<const0> ;
assign doutb[376] = \<const0> ;
assign doutb[375] = \<const0> ;
assign doutb[374] = \<const0> ;
assign doutb[373] = \<const0> ;
assign doutb[372] = \<const0> ;
assign doutb[371] = \<const0> ;
assign doutb[370] = \<const0> ;
assign doutb[369] = \<const0> ;
assign doutb[368] = \<const0> ;
assign doutb[367] = \<const0> ;
assign doutb[366] = \<const0> ;
assign doutb[365] = \<const0> ;
assign doutb[364] = \<const0> ;
assign doutb[363] = \<const0> ;
assign doutb[362] = \<const0> ;
assign doutb[361] = \<const0> ;
assign doutb[360] = \<const0> ;
assign doutb[359] = \<const0> ;
assign doutb[358] = \<const0> ;
assign doutb[357] = \<const0> ;
assign doutb[356] = \<const0> ;
assign doutb[355] = \<const0> ;
assign doutb[354] = \<const0> ;
assign doutb[353] = \<const0> ;
assign doutb[352] = \<const0> ;
assign doutb[351] = \<const0> ;
assign doutb[350] = \<const0> ;
assign doutb[349] = \<const0> ;
assign doutb[348] = \<const0> ;
assign doutb[347] = \<const0> ;
assign doutb[346] = \<const0> ;
assign doutb[345] = \<const0> ;
assign doutb[344] = \<const0> ;
assign doutb[343] = \<const0> ;
assign doutb[342] = \<const0> ;
assign doutb[341] = \<const0> ;
assign doutb[340] = \<const0> ;
assign doutb[339] = \<const0> ;
assign doutb[338] = \<const0> ;
assign doutb[337] = \<const0> ;
assign doutb[336] = \<const0> ;
assign doutb[335] = \<const0> ;
assign doutb[334] = \<const0> ;
assign doutb[333] = \<const0> ;
assign doutb[332] = \<const0> ;
assign doutb[331] = \<const0> ;
assign doutb[330] = \<const0> ;
assign doutb[329] = \<const0> ;
assign doutb[328] = \<const0> ;
assign doutb[327] = \<const0> ;
assign doutb[326] = \<const0> ;
assign doutb[325] = \<const0> ;
assign doutb[324] = \<const0> ;
assign doutb[323] = \<const0> ;
assign doutb[322] = \<const0> ;
assign doutb[321] = \<const0> ;
assign doutb[320] = \<const0> ;
assign doutb[319] = \<const0> ;
assign doutb[318] = \<const0> ;
assign doutb[317] = \<const0> ;
assign doutb[316] = \<const0> ;
assign doutb[315] = \<const0> ;
assign doutb[314] = \<const0> ;
assign doutb[313] = \<const0> ;
assign doutb[312] = \<const0> ;
assign doutb[311] = \<const0> ;
assign doutb[310] = \<const0> ;
assign doutb[309] = \<const0> ;
assign doutb[308] = \<const0> ;
assign doutb[307] = \<const0> ;
assign doutb[306] = \<const0> ;
assign doutb[305] = \<const0> ;
assign doutb[304] = \<const0> ;
assign doutb[303] = \<const0> ;
assign doutb[302] = \<const0> ;
assign doutb[301] = \<const0> ;
assign doutb[300] = \<const0> ;
assign doutb[299] = \<const0> ;
assign doutb[298] = \<const0> ;
assign doutb[297] = \<const0> ;
assign doutb[296] = \<const0> ;
assign doutb[295] = \<const0> ;
assign doutb[294] = \<const0> ;
assign doutb[293] = \<const0> ;
assign doutb[292] = \<const0> ;
assign doutb[291] = \<const0> ;
assign doutb[290] = \<const0> ;
assign doutb[289] = \<const0> ;
assign doutb[288] = \<const0> ;
assign doutb[287] = \<const0> ;
assign doutb[286] = \<const0> ;
assign doutb[285] = \<const0> ;
assign doutb[284] = \<const0> ;
assign doutb[283] = \<const0> ;
assign doutb[282] = \<const0> ;
assign doutb[281] = \<const0> ;
assign doutb[280] = \<const0> ;
assign doutb[279] = \<const0> ;
assign doutb[278] = \<const0> ;
assign doutb[277] = \<const0> ;
assign doutb[276] = \<const0> ;
assign doutb[275] = \<const0> ;
assign doutb[274] = \<const0> ;
assign doutb[273] = \<const0> ;
assign doutb[272] = \<const0> ;
assign doutb[271] = \<const0> ;
assign doutb[270] = \<const0> ;
assign doutb[269] = \<const0> ;
assign doutb[268] = \<const0> ;
assign doutb[267] = \<const0> ;
assign doutb[266] = \<const0> ;
assign doutb[265] = \<const0> ;
assign doutb[264] = \<const0> ;
assign doutb[263] = \<const0> ;
assign doutb[262] = \<const0> ;
assign doutb[261] = \<const0> ;
assign doutb[260] = \<const0> ;
assign doutb[259] = \<const0> ;
assign doutb[258] = \<const0> ;
assign doutb[257] = \<const0> ;
assign doutb[256] = \<const0> ;
assign doutb[255] = \<const0> ;
assign doutb[254] = \<const0> ;
assign doutb[253] = \<const0> ;
assign doutb[252] = \<const0> ;
assign doutb[251] = \<const0> ;
assign doutb[250] = \<const0> ;
assign doutb[249] = \<const0> ;
assign doutb[248] = \<const0> ;
assign doutb[247] = \<const0> ;
assign doutb[246] = \<const0> ;
assign doutb[245] = \<const0> ;
assign doutb[244] = \<const0> ;
assign doutb[243] = \<const0> ;
assign doutb[242] = \<const0> ;
assign doutb[241] = \<const0> ;
assign doutb[240] = \<const0> ;
assign doutb[239] = \<const0> ;
assign doutb[238] = \<const0> ;
assign doutb[237] = \<const0> ;
assign doutb[236] = \<const0> ;
assign doutb[235] = \<const0> ;
assign doutb[234] = \<const0> ;
assign doutb[233] = \<const0> ;
assign doutb[232] = \<const0> ;
assign doutb[231] = \<const0> ;
assign doutb[230] = \<const0> ;
assign doutb[229] = \<const0> ;
assign doutb[228] = \<const0> ;
assign doutb[227] = \<const0> ;
assign doutb[226] = \<const0> ;
assign doutb[225] = \<const0> ;
assign doutb[224] = \<const0> ;
assign doutb[223] = \<const0> ;
assign doutb[222] = \<const0> ;
assign doutb[221] = \<const0> ;
assign doutb[220] = \<const0> ;
assign doutb[219] = \<const0> ;
assign doutb[218] = \<const0> ;
assign doutb[217] = \<const0> ;
assign doutb[216] = \<const0> ;
assign doutb[215] = \<const0> ;
assign doutb[214] = \<const0> ;
assign doutb[213] = \<const0> ;
assign doutb[212] = \<const0> ;
assign doutb[211] = \<const0> ;
assign doutb[210] = \<const0> ;
assign doutb[209] = \<const0> ;
assign doutb[208] = \<const0> ;
assign doutb[207] = \<const0> ;
assign doutb[206] = \<const0> ;
assign doutb[205] = \<const0> ;
assign doutb[204] = \<const0> ;
assign doutb[203] = \<const0> ;
assign doutb[202] = \<const0> ;
assign doutb[201] = \<const0> ;
assign doutb[200] = \<const0> ;
assign doutb[199] = \<const0> ;
assign doutb[198] = \<const0> ;
assign doutb[197] = \<const0> ;
assign doutb[196] = \<const0> ;
assign doutb[195] = \<const0> ;
assign doutb[194] = \<const0> ;
assign doutb[193] = \<const0> ;
assign doutb[192] = \<const0> ;
assign doutb[191] = \<const0> ;
assign doutb[190] = \<const0> ;
assign doutb[189] = \<const0> ;
assign doutb[188] = \<const0> ;
assign doutb[187] = \<const0> ;
assign doutb[186] = \<const0> ;
assign doutb[185] = \<const0> ;
assign doutb[184] = \<const0> ;
assign doutb[183] = \<const0> ;
assign doutb[182] = \<const0> ;
assign doutb[181] = \<const0> ;
assign doutb[180] = \<const0> ;
assign doutb[179] = \<const0> ;
assign doutb[178] = \<const0> ;
assign doutb[177] = \<const0> ;
assign doutb[176] = \<const0> ;
assign doutb[175] = \<const0> ;
assign doutb[174] = \<const0> ;
assign doutb[173] = \<const0> ;
assign doutb[172] = \<const0> ;
assign doutb[171] = \<const0> ;
assign doutb[170] = \<const0> ;
assign doutb[169] = \<const0> ;
assign doutb[168] = \<const0> ;
assign doutb[167] = \<const0> ;
assign doutb[166] = \<const0> ;
assign doutb[165] = \<const0> ;
assign doutb[164] = \<const0> ;
assign doutb[163] = \<const0> ;
assign doutb[162] = \<const0> ;
assign doutb[161] = \<const0> ;
assign doutb[160] = \<const0> ;
assign doutb[159] = \<const0> ;
assign doutb[158] = \<const0> ;
assign doutb[157] = \<const0> ;
assign doutb[156] = \<const0> ;
assign doutb[155] = \<const0> ;
assign doutb[154] = \<const0> ;
assign doutb[153] = \<const0> ;
assign doutb[152] = \<const0> ;
assign doutb[151] = \<const0> ;
assign doutb[150] = \<const0> ;
assign doutb[149] = \<const0> ;
assign doutb[148] = \<const0> ;
assign doutb[147] = \<const0> ;
assign doutb[146] = \<const0> ;
assign doutb[145] = \<const0> ;
assign doutb[144] = \<const0> ;
assign doutb[143] = \<const0> ;
assign doutb[142] = \<const0> ;
assign doutb[141] = \<const0> ;
assign doutb[140] = \<const0> ;
assign doutb[139] = \<const0> ;
assign doutb[138] = \<const0> ;
assign doutb[137] = \<const0> ;
assign doutb[136] = \<const0> ;
assign doutb[135] = \<const0> ;
assign doutb[134] = \<const0> ;
assign doutb[133] = \<const0> ;
assign doutb[132] = \<const0> ;
assign doutb[131] = \<const0> ;
assign doutb[130] = \<const0> ;
assign doutb[129] = \<const0> ;
assign doutb[128] = \<const0> ;
assign doutb[127] = \<const0> ;
assign doutb[126] = \<const0> ;
assign doutb[125] = \<const0> ;
assign doutb[124] = \<const0> ;
assign doutb[123] = \<const0> ;
assign doutb[122] = \<const0> ;
assign doutb[121] = \<const0> ;
assign doutb[120] = \<const0> ;
assign doutb[119] = \<const0> ;
assign doutb[118] = \<const0> ;
assign doutb[117] = \<const0> ;
assign doutb[116] = \<const0> ;
assign doutb[115] = \<const0> ;
assign doutb[114] = \<const0> ;
assign doutb[113] = \<const0> ;
assign doutb[112] = \<const0> ;
assign doutb[111] = \<const0> ;
assign doutb[110] = \<const0> ;
assign doutb[109] = \<const0> ;
assign doutb[108] = \<const0> ;
assign doutb[107] = \<const0> ;
assign doutb[106] = \<const0> ;
assign doutb[105] = \<const0> ;
assign doutb[104] = \<const0> ;
assign doutb[103] = \<const0> ;
assign doutb[102] = \<const0> ;
assign doutb[101] = \<const0> ;
assign doutb[100] = \<const0> ;
assign doutb[99] = \<const0> ;
assign doutb[98] = \<const0> ;
assign doutb[97] = \<const0> ;
assign doutb[96] = \<const0> ;
assign doutb[95] = \<const0> ;
assign doutb[94] = \<const0> ;
assign doutb[93] = \<const0> ;
assign doutb[92] = \<const0> ;
assign doutb[91] = \<const0> ;
assign doutb[90] = \<const0> ;
assign doutb[89] = \<const0> ;
assign doutb[88] = \<const0> ;
assign doutb[87] = \<const0> ;
assign doutb[86] = \<const0> ;
assign doutb[85] = \<const0> ;
assign doutb[84] = \<const0> ;
assign doutb[83] = \<const0> ;
assign doutb[82] = \<const0> ;
assign doutb[81] = \<const0> ;
assign doutb[80] = \<const0> ;
assign doutb[79] = \<const0> ;
assign doutb[78] = \<const0> ;
assign doutb[77] = \<const0> ;
assign doutb[76] = \<const0> ;
assign doutb[75] = \<const0> ;
assign doutb[74] = \<const0> ;
assign doutb[73] = \<const0> ;
assign doutb[72] = \<const0> ;
assign doutb[71] = \<const0> ;
assign doutb[70] = \<const0> ;
assign doutb[69] = \<const0> ;
assign doutb[68] = \<const0> ;
assign doutb[67] = \<const0> ;
assign doutb[66] = \<const0> ;
assign doutb[65] = \<const0> ;
assign doutb[64] = \<const0> ;
assign doutb[63] = \<const0> ;
assign doutb[62] = \<const0> ;
assign doutb[61] = \<const0> ;
assign doutb[60] = \<const0> ;
assign doutb[59] = \<const0> ;
assign doutb[58] = \<const0> ;
assign doutb[57] = \<const0> ;
assign doutb[56] = \<const0> ;
assign doutb[55] = \<const0> ;
assign doutb[54] = \<const0> ;
assign doutb[53] = \<const0> ;
assign doutb[52] = \<const0> ;
assign doutb[51] = \<const0> ;
assign doutb[50] = \<const0> ;
assign doutb[49] = \<const0> ;
assign doutb[48] = \<const0> ;
assign doutb[47] = \<const0> ;
assign doutb[46] = \<const0> ;
assign doutb[45] = \<const0> ;
assign doutb[44] = \<const0> ;
assign doutb[43] = \<const0> ;
assign doutb[42] = \<const0> ;
assign doutb[41] = \<const0> ;
assign doutb[40] = \<const0> ;
assign doutb[39] = \<const0> ;
assign doutb[38] = \<const0> ;
assign doutb[37] = \<const0> ;
assign doutb[36] = \<const0> ;
assign doutb[35] = \<const0> ;
assign doutb[34] = \<const0> ;
assign doutb[33] = \<const0> ;
assign doutb[32] = \<const0> ;
assign doutb[31] = \<const0> ;
assign doutb[30] = \<const0> ;
assign doutb[29] = \<const0> ;
assign doutb[28] = \<const0> ;
assign doutb[27] = \<const0> ;
assign doutb[26] = \<const0> ;
assign doutb[25] = \<const0> ;
assign doutb[24] = \<const0> ;
assign doutb[23] = \<const0> ;
assign doutb[22] = \<const0> ;
assign doutb[21] = \<const0> ;
assign doutb[20] = \<const0> ;
assign doutb[19] = \<const0> ;
assign doutb[18] = \<const0> ;
assign doutb[17] = \<const0> ;
assign doutb[16] = \<const0> ;
assign doutb[15] = \<const0> ;
assign doutb[14] = \<const0> ;
assign doutb[13] = \<const0> ;
assign doutb[12] = \<const0> ;
assign doutb[11] = \<const0> ;
assign doutb[10] = \<const0> ;
assign doutb[9] = \<const0> ;
assign doutb[8] = \<const0> ;
assign doutb[7] = \<const0> ;
assign doutb[6] = \<const0> ;
assign doutb[5] = \<const0> ;
assign doutb[4] = \<const0> ;
assign doutb[3] = \<const0> ;
assign doutb[2] = \<const0> ;
assign doutb[1] = \<const0> ;
assign doutb[0] = \<const0> ;
assign rdaddrecc[9] = \<const0> ;
assign rdaddrecc[8] = \<const0> ;
assign rdaddrecc[7] = \<const0> ;
assign rdaddrecc[6] = \<const0> ;
assign rdaddrecc[5] = \<const0> ;
assign rdaddrecc[4] = \<const0> ;
assign rdaddrecc[3] = \<const0> ;
assign rdaddrecc[2] = \<const0> ;
assign rdaddrecc[1] = \<const0> ;
assign rdaddrecc[0] = \<const0> ;
assign s_axi_arready = \<const0> ;
assign s_axi_awready = \<const0> ;
assign s_axi_bid[3] = \<const0> ;
assign s_axi_bid[2] = \<const0> ;
assign s_axi_bid[1] = \<const0> ;
assign s_axi_bid[0] = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_bvalid = \<const0> ;
assign s_axi_dbiterr = \<const0> ;
assign s_axi_rdaddrecc[9] = \<const0> ;
assign s_axi_rdaddrecc[8] = \<const0> ;
assign s_axi_rdaddrecc[7] = \<const0> ;
assign s_axi_rdaddrecc[6] = \<const0> ;
assign s_axi_rdaddrecc[5] = \<const0> ;
assign s_axi_rdaddrecc[4] = \<const0> ;
assign s_axi_rdaddrecc[3] = \<const0> ;
assign s_axi_rdaddrecc[2] = \<const0> ;
assign s_axi_rdaddrecc[1] = \<const0> ;
assign s_axi_rdaddrecc[0] = \<const0> ;
assign s_axi_rdata[799] = \<const0> ;
assign s_axi_rdata[798] = \<const0> ;
assign s_axi_rdata[797] = \<const0> ;
assign s_axi_rdata[796] = \<const0> ;
assign s_axi_rdata[795] = \<const0> ;
assign s_axi_rdata[794] = \<const0> ;
assign s_axi_rdata[793] = \<const0> ;
assign s_axi_rdata[792] = \<const0> ;
assign s_axi_rdata[791] = \<const0> ;
assign s_axi_rdata[790] = \<const0> ;
assign s_axi_rdata[789] = \<const0> ;
assign s_axi_rdata[788] = \<const0> ;
assign s_axi_rdata[787] = \<const0> ;
assign s_axi_rdata[786] = \<const0> ;
assign s_axi_rdata[785] = \<const0> ;
assign s_axi_rdata[784] = \<const0> ;
assign s_axi_rdata[783] = \<const0> ;
assign s_axi_rdata[782] = \<const0> ;
assign s_axi_rdata[781] = \<const0> ;
assign s_axi_rdata[780] = \<const0> ;
assign s_axi_rdata[779] = \<const0> ;
assign s_axi_rdata[778] = \<const0> ;
assign s_axi_rdata[777] = \<const0> ;
assign s_axi_rdata[776] = \<const0> ;
assign s_axi_rdata[775] = \<const0> ;
assign s_axi_rdata[774] = \<const0> ;
assign s_axi_rdata[773] = \<const0> ;
assign s_axi_rdata[772] = \<const0> ;
assign s_axi_rdata[771] = \<const0> ;
assign s_axi_rdata[770] = \<const0> ;
assign s_axi_rdata[769] = \<const0> ;
assign s_axi_rdata[768] = \<const0> ;
assign s_axi_rdata[767] = \<const0> ;
assign s_axi_rdata[766] = \<const0> ;
assign s_axi_rdata[765] = \<const0> ;
assign s_axi_rdata[764] = \<const0> ;
assign s_axi_rdata[763] = \<const0> ;
assign s_axi_rdata[762] = \<const0> ;
assign s_axi_rdata[761] = \<const0> ;
assign s_axi_rdata[760] = \<const0> ;
assign s_axi_rdata[759] = \<const0> ;
assign s_axi_rdata[758] = \<const0> ;
assign s_axi_rdata[757] = \<const0> ;
assign s_axi_rdata[756] = \<const0> ;
assign s_axi_rdata[755] = \<const0> ;
assign s_axi_rdata[754] = \<const0> ;
assign s_axi_rdata[753] = \<const0> ;
assign s_axi_rdata[752] = \<const0> ;
assign s_axi_rdata[751] = \<const0> ;
assign s_axi_rdata[750] = \<const0> ;
assign s_axi_rdata[749] = \<const0> ;
assign s_axi_rdata[748] = \<const0> ;
assign s_axi_rdata[747] = \<const0> ;
assign s_axi_rdata[746] = \<const0> ;
assign s_axi_rdata[745] = \<const0> ;
assign s_axi_rdata[744] = \<const0> ;
assign s_axi_rdata[743] = \<const0> ;
assign s_axi_rdata[742] = \<const0> ;
assign s_axi_rdata[741] = \<const0> ;
assign s_axi_rdata[740] = \<const0> ;
assign s_axi_rdata[739] = \<const0> ;
assign s_axi_rdata[738] = \<const0> ;
assign s_axi_rdata[737] = \<const0> ;
assign s_axi_rdata[736] = \<const0> ;
assign s_axi_rdata[735] = \<const0> ;
assign s_axi_rdata[734] = \<const0> ;
assign s_axi_rdata[733] = \<const0> ;
assign s_axi_rdata[732] = \<const0> ;
assign s_axi_rdata[731] = \<const0> ;
assign s_axi_rdata[730] = \<const0> ;
assign s_axi_rdata[729] = \<const0> ;
assign s_axi_rdata[728] = \<const0> ;
assign s_axi_rdata[727] = \<const0> ;
assign s_axi_rdata[726] = \<const0> ;
assign s_axi_rdata[725] = \<const0> ;
assign s_axi_rdata[724] = \<const0> ;
assign s_axi_rdata[723] = \<const0> ;
assign s_axi_rdata[722] = \<const0> ;
assign s_axi_rdata[721] = \<const0> ;
assign s_axi_rdata[720] = \<const0> ;
assign s_axi_rdata[719] = \<const0> ;
assign s_axi_rdata[718] = \<const0> ;
assign s_axi_rdata[717] = \<const0> ;
assign s_axi_rdata[716] = \<const0> ;
assign s_axi_rdata[715] = \<const0> ;
assign s_axi_rdata[714] = \<const0> ;
assign s_axi_rdata[713] = \<const0> ;
assign s_axi_rdata[712] = \<const0> ;
assign s_axi_rdata[711] = \<const0> ;
assign s_axi_rdata[710] = \<const0> ;
assign s_axi_rdata[709] = \<const0> ;
assign s_axi_rdata[708] = \<const0> ;
assign s_axi_rdata[707] = \<const0> ;
assign s_axi_rdata[706] = \<const0> ;
assign s_axi_rdata[705] = \<const0> ;
assign s_axi_rdata[704] = \<const0> ;
assign s_axi_rdata[703] = \<const0> ;
assign s_axi_rdata[702] = \<const0> ;
assign s_axi_rdata[701] = \<const0> ;
assign s_axi_rdata[700] = \<const0> ;
assign s_axi_rdata[699] = \<const0> ;
assign s_axi_rdata[698] = \<const0> ;
assign s_axi_rdata[697] = \<const0> ;
assign s_axi_rdata[696] = \<const0> ;
assign s_axi_rdata[695] = \<const0> ;
assign s_axi_rdata[694] = \<const0> ;
assign s_axi_rdata[693] = \<const0> ;
assign s_axi_rdata[692] = \<const0> ;
assign s_axi_rdata[691] = \<const0> ;
assign s_axi_rdata[690] = \<const0> ;
assign s_axi_rdata[689] = \<const0> ;
assign s_axi_rdata[688] = \<const0> ;
assign s_axi_rdata[687] = \<const0> ;
assign s_axi_rdata[686] = \<const0> ;
assign s_axi_rdata[685] = \<const0> ;
assign s_axi_rdata[684] = \<const0> ;
assign s_axi_rdata[683] = \<const0> ;
assign s_axi_rdata[682] = \<const0> ;
assign s_axi_rdata[681] = \<const0> ;
assign s_axi_rdata[680] = \<const0> ;
assign s_axi_rdata[679] = \<const0> ;
assign s_axi_rdata[678] = \<const0> ;
assign s_axi_rdata[677] = \<const0> ;
assign s_axi_rdata[676] = \<const0> ;
assign s_axi_rdata[675] = \<const0> ;
assign s_axi_rdata[674] = \<const0> ;
assign s_axi_rdata[673] = \<const0> ;
assign s_axi_rdata[672] = \<const0> ;
assign s_axi_rdata[671] = \<const0> ;
assign s_axi_rdata[670] = \<const0> ;
assign s_axi_rdata[669] = \<const0> ;
assign s_axi_rdata[668] = \<const0> ;
assign s_axi_rdata[667] = \<const0> ;
assign s_axi_rdata[666] = \<const0> ;
assign s_axi_rdata[665] = \<const0> ;
assign s_axi_rdata[664] = \<const0> ;
assign s_axi_rdata[663] = \<const0> ;
assign s_axi_rdata[662] = \<const0> ;
assign s_axi_rdata[661] = \<const0> ;
assign s_axi_rdata[660] = \<const0> ;
assign s_axi_rdata[659] = \<const0> ;
assign s_axi_rdata[658] = \<const0> ;
assign s_axi_rdata[657] = \<const0> ;
assign s_axi_rdata[656] = \<const0> ;
assign s_axi_rdata[655] = \<const0> ;
assign s_axi_rdata[654] = \<const0> ;
assign s_axi_rdata[653] = \<const0> ;
assign s_axi_rdata[652] = \<const0> ;
assign s_axi_rdata[651] = \<const0> ;
assign s_axi_rdata[650] = \<const0> ;
assign s_axi_rdata[649] = \<const0> ;
assign s_axi_rdata[648] = \<const0> ;
assign s_axi_rdata[647] = \<const0> ;
assign s_axi_rdata[646] = \<const0> ;
assign s_axi_rdata[645] = \<const0> ;
assign s_axi_rdata[644] = \<const0> ;
assign s_axi_rdata[643] = \<const0> ;
assign s_axi_rdata[642] = \<const0> ;
assign s_axi_rdata[641] = \<const0> ;
assign s_axi_rdata[640] = \<const0> ;
assign s_axi_rdata[639] = \<const0> ;
assign s_axi_rdata[638] = \<const0> ;
assign s_axi_rdata[637] = \<const0> ;
assign s_axi_rdata[636] = \<const0> ;
assign s_axi_rdata[635] = \<const0> ;
assign s_axi_rdata[634] = \<const0> ;
assign s_axi_rdata[633] = \<const0> ;
assign s_axi_rdata[632] = \<const0> ;
assign s_axi_rdata[631] = \<const0> ;
assign s_axi_rdata[630] = \<const0> ;
assign s_axi_rdata[629] = \<const0> ;
assign s_axi_rdata[628] = \<const0> ;
assign s_axi_rdata[627] = \<const0> ;
assign s_axi_rdata[626] = \<const0> ;
assign s_axi_rdata[625] = \<const0> ;
assign s_axi_rdata[624] = \<const0> ;
assign s_axi_rdata[623] = \<const0> ;
assign s_axi_rdata[622] = \<const0> ;
assign s_axi_rdata[621] = \<const0> ;
assign s_axi_rdata[620] = \<const0> ;
assign s_axi_rdata[619] = \<const0> ;
assign s_axi_rdata[618] = \<const0> ;
assign s_axi_rdata[617] = \<const0> ;
assign s_axi_rdata[616] = \<const0> ;
assign s_axi_rdata[615] = \<const0> ;
assign s_axi_rdata[614] = \<const0> ;
assign s_axi_rdata[613] = \<const0> ;
assign s_axi_rdata[612] = \<const0> ;
assign s_axi_rdata[611] = \<const0> ;
assign s_axi_rdata[610] = \<const0> ;
assign s_axi_rdata[609] = \<const0> ;
assign s_axi_rdata[608] = \<const0> ;
assign s_axi_rdata[607] = \<const0> ;
assign s_axi_rdata[606] = \<const0> ;
assign s_axi_rdata[605] = \<const0> ;
assign s_axi_rdata[604] = \<const0> ;
assign s_axi_rdata[603] = \<const0> ;
assign s_axi_rdata[602] = \<const0> ;
assign s_axi_rdata[601] = \<const0> ;
assign s_axi_rdata[600] = \<const0> ;
assign s_axi_rdata[599] = \<const0> ;
assign s_axi_rdata[598] = \<const0> ;
assign s_axi_rdata[597] = \<const0> ;
assign s_axi_rdata[596] = \<const0> ;
assign s_axi_rdata[595] = \<const0> ;
assign s_axi_rdata[594] = \<const0> ;
assign s_axi_rdata[593] = \<const0> ;
assign s_axi_rdata[592] = \<const0> ;
assign s_axi_rdata[591] = \<const0> ;
assign s_axi_rdata[590] = \<const0> ;
assign s_axi_rdata[589] = \<const0> ;
assign s_axi_rdata[588] = \<const0> ;
assign s_axi_rdata[587] = \<const0> ;
assign s_axi_rdata[586] = \<const0> ;
assign s_axi_rdata[585] = \<const0> ;
assign s_axi_rdata[584] = \<const0> ;
assign s_axi_rdata[583] = \<const0> ;
assign s_axi_rdata[582] = \<const0> ;
assign s_axi_rdata[581] = \<const0> ;
assign s_axi_rdata[580] = \<const0> ;
assign s_axi_rdata[579] = \<const0> ;
assign s_axi_rdata[578] = \<const0> ;
assign s_axi_rdata[577] = \<const0> ;
assign s_axi_rdata[576] = \<const0> ;
assign s_axi_rdata[575] = \<const0> ;
assign s_axi_rdata[574] = \<const0> ;
assign s_axi_rdata[573] = \<const0> ;
assign s_axi_rdata[572] = \<const0> ;
assign s_axi_rdata[571] = \<const0> ;
assign s_axi_rdata[570] = \<const0> ;
assign s_axi_rdata[569] = \<const0> ;
assign s_axi_rdata[568] = \<const0> ;
assign s_axi_rdata[567] = \<const0> ;
assign s_axi_rdata[566] = \<const0> ;
assign s_axi_rdata[565] = \<const0> ;
assign s_axi_rdata[564] = \<const0> ;
assign s_axi_rdata[563] = \<const0> ;
assign s_axi_rdata[562] = \<const0> ;
assign s_axi_rdata[561] = \<const0> ;
assign s_axi_rdata[560] = \<const0> ;
assign s_axi_rdata[559] = \<const0> ;
assign s_axi_rdata[558] = \<const0> ;
assign s_axi_rdata[557] = \<const0> ;
assign s_axi_rdata[556] = \<const0> ;
assign s_axi_rdata[555] = \<const0> ;
assign s_axi_rdata[554] = \<const0> ;
assign s_axi_rdata[553] = \<const0> ;
assign s_axi_rdata[552] = \<const0> ;
assign s_axi_rdata[551] = \<const0> ;
assign s_axi_rdata[550] = \<const0> ;
assign s_axi_rdata[549] = \<const0> ;
assign s_axi_rdata[548] = \<const0> ;
assign s_axi_rdata[547] = \<const0> ;
assign s_axi_rdata[546] = \<const0> ;
assign s_axi_rdata[545] = \<const0> ;
assign s_axi_rdata[544] = \<const0> ;
assign s_axi_rdata[543] = \<const0> ;
assign s_axi_rdata[542] = \<const0> ;
assign s_axi_rdata[541] = \<const0> ;
assign s_axi_rdata[540] = \<const0> ;
assign s_axi_rdata[539] = \<const0> ;
assign s_axi_rdata[538] = \<const0> ;
assign s_axi_rdata[537] = \<const0> ;
assign s_axi_rdata[536] = \<const0> ;
assign s_axi_rdata[535] = \<const0> ;
assign s_axi_rdata[534] = \<const0> ;
assign s_axi_rdata[533] = \<const0> ;
assign s_axi_rdata[532] = \<const0> ;
assign s_axi_rdata[531] = \<const0> ;
assign s_axi_rdata[530] = \<const0> ;
assign s_axi_rdata[529] = \<const0> ;
assign s_axi_rdata[528] = \<const0> ;
assign s_axi_rdata[527] = \<const0> ;
assign s_axi_rdata[526] = \<const0> ;
assign s_axi_rdata[525] = \<const0> ;
assign s_axi_rdata[524] = \<const0> ;
assign s_axi_rdata[523] = \<const0> ;
assign s_axi_rdata[522] = \<const0> ;
assign s_axi_rdata[521] = \<const0> ;
assign s_axi_rdata[520] = \<const0> ;
assign s_axi_rdata[519] = \<const0> ;
assign s_axi_rdata[518] = \<const0> ;
assign s_axi_rdata[517] = \<const0> ;
assign s_axi_rdata[516] = \<const0> ;
assign s_axi_rdata[515] = \<const0> ;
assign s_axi_rdata[514] = \<const0> ;
assign s_axi_rdata[513] = \<const0> ;
assign s_axi_rdata[512] = \<const0> ;
assign s_axi_rdata[511] = \<const0> ;
assign s_axi_rdata[510] = \<const0> ;
assign s_axi_rdata[509] = \<const0> ;
assign s_axi_rdata[508] = \<const0> ;
assign s_axi_rdata[507] = \<const0> ;
assign s_axi_rdata[506] = \<const0> ;
assign s_axi_rdata[505] = \<const0> ;
assign s_axi_rdata[504] = \<const0> ;
assign s_axi_rdata[503] = \<const0> ;
assign s_axi_rdata[502] = \<const0> ;
assign s_axi_rdata[501] = \<const0> ;
assign s_axi_rdata[500] = \<const0> ;
assign s_axi_rdata[499] = \<const0> ;
assign s_axi_rdata[498] = \<const0> ;
assign s_axi_rdata[497] = \<const0> ;
assign s_axi_rdata[496] = \<const0> ;
assign s_axi_rdata[495] = \<const0> ;
assign s_axi_rdata[494] = \<const0> ;
assign s_axi_rdata[493] = \<const0> ;
assign s_axi_rdata[492] = \<const0> ;
assign s_axi_rdata[491] = \<const0> ;
assign s_axi_rdata[490] = \<const0> ;
assign s_axi_rdata[489] = \<const0> ;
assign s_axi_rdata[488] = \<const0> ;
assign s_axi_rdata[487] = \<const0> ;
assign s_axi_rdata[486] = \<const0> ;
assign s_axi_rdata[485] = \<const0> ;
assign s_axi_rdata[484] = \<const0> ;
assign s_axi_rdata[483] = \<const0> ;
assign s_axi_rdata[482] = \<const0> ;
assign s_axi_rdata[481] = \<const0> ;
assign s_axi_rdata[480] = \<const0> ;
assign s_axi_rdata[479] = \<const0> ;
assign s_axi_rdata[478] = \<const0> ;
assign s_axi_rdata[477] = \<const0> ;
assign s_axi_rdata[476] = \<const0> ;
assign s_axi_rdata[475] = \<const0> ;
assign s_axi_rdata[474] = \<const0> ;
assign s_axi_rdata[473] = \<const0> ;
assign s_axi_rdata[472] = \<const0> ;
assign s_axi_rdata[471] = \<const0> ;
assign s_axi_rdata[470] = \<const0> ;
assign s_axi_rdata[469] = \<const0> ;
assign s_axi_rdata[468] = \<const0> ;
assign s_axi_rdata[467] = \<const0> ;
assign s_axi_rdata[466] = \<const0> ;
assign s_axi_rdata[465] = \<const0> ;
assign s_axi_rdata[464] = \<const0> ;
assign s_axi_rdata[463] = \<const0> ;
assign s_axi_rdata[462] = \<const0> ;
assign s_axi_rdata[461] = \<const0> ;
assign s_axi_rdata[460] = \<const0> ;
assign s_axi_rdata[459] = \<const0> ;
assign s_axi_rdata[458] = \<const0> ;
assign s_axi_rdata[457] = \<const0> ;
assign s_axi_rdata[456] = \<const0> ;
assign s_axi_rdata[455] = \<const0> ;
assign s_axi_rdata[454] = \<const0> ;
assign s_axi_rdata[453] = \<const0> ;
assign s_axi_rdata[452] = \<const0> ;
assign s_axi_rdata[451] = \<const0> ;
assign s_axi_rdata[450] = \<const0> ;
assign s_axi_rdata[449] = \<const0> ;
assign s_axi_rdata[448] = \<const0> ;
assign s_axi_rdata[447] = \<const0> ;
assign s_axi_rdata[446] = \<const0> ;
assign s_axi_rdata[445] = \<const0> ;
assign s_axi_rdata[444] = \<const0> ;
assign s_axi_rdata[443] = \<const0> ;
assign s_axi_rdata[442] = \<const0> ;
assign s_axi_rdata[441] = \<const0> ;
assign s_axi_rdata[440] = \<const0> ;
assign s_axi_rdata[439] = \<const0> ;
assign s_axi_rdata[438] = \<const0> ;
assign s_axi_rdata[437] = \<const0> ;
assign s_axi_rdata[436] = \<const0> ;
assign s_axi_rdata[435] = \<const0> ;
assign s_axi_rdata[434] = \<const0> ;
assign s_axi_rdata[433] = \<const0> ;
assign s_axi_rdata[432] = \<const0> ;
assign s_axi_rdata[431] = \<const0> ;
assign s_axi_rdata[430] = \<const0> ;
assign s_axi_rdata[429] = \<const0> ;
assign s_axi_rdata[428] = \<const0> ;
assign s_axi_rdata[427] = \<const0> ;
assign s_axi_rdata[426] = \<const0> ;
assign s_axi_rdata[425] = \<const0> ;
assign s_axi_rdata[424] = \<const0> ;
assign s_axi_rdata[423] = \<const0> ;
assign s_axi_rdata[422] = \<const0> ;
assign s_axi_rdata[421] = \<const0> ;
assign s_axi_rdata[420] = \<const0> ;
assign s_axi_rdata[419] = \<const0> ;
assign s_axi_rdata[418] = \<const0> ;
assign s_axi_rdata[417] = \<const0> ;
assign s_axi_rdata[416] = \<const0> ;
assign s_axi_rdata[415] = \<const0> ;
assign s_axi_rdata[414] = \<const0> ;
assign s_axi_rdata[413] = \<const0> ;
assign s_axi_rdata[412] = \<const0> ;
assign s_axi_rdata[411] = \<const0> ;
assign s_axi_rdata[410] = \<const0> ;
assign s_axi_rdata[409] = \<const0> ;
assign s_axi_rdata[408] = \<const0> ;
assign s_axi_rdata[407] = \<const0> ;
assign s_axi_rdata[406] = \<const0> ;
assign s_axi_rdata[405] = \<const0> ;
assign s_axi_rdata[404] = \<const0> ;
assign s_axi_rdata[403] = \<const0> ;
assign s_axi_rdata[402] = \<const0> ;
assign s_axi_rdata[401] = \<const0> ;
assign s_axi_rdata[400] = \<const0> ;
assign s_axi_rdata[399] = \<const0> ;
assign s_axi_rdata[398] = \<const0> ;
assign s_axi_rdata[397] = \<const0> ;
assign s_axi_rdata[396] = \<const0> ;
assign s_axi_rdata[395] = \<const0> ;
assign s_axi_rdata[394] = \<const0> ;
assign s_axi_rdata[393] = \<const0> ;
assign s_axi_rdata[392] = \<const0> ;
assign s_axi_rdata[391] = \<const0> ;
assign s_axi_rdata[390] = \<const0> ;
assign s_axi_rdata[389] = \<const0> ;
assign s_axi_rdata[388] = \<const0> ;
assign s_axi_rdata[387] = \<const0> ;
assign s_axi_rdata[386] = \<const0> ;
assign s_axi_rdata[385] = \<const0> ;
assign s_axi_rdata[384] = \<const0> ;
assign s_axi_rdata[383] = \<const0> ;
assign s_axi_rdata[382] = \<const0> ;
assign s_axi_rdata[381] = \<const0> ;
assign s_axi_rdata[380] = \<const0> ;
assign s_axi_rdata[379] = \<const0> ;
assign s_axi_rdata[378] = \<const0> ;
assign s_axi_rdata[377] = \<const0> ;
assign s_axi_rdata[376] = \<const0> ;
assign s_axi_rdata[375] = \<const0> ;
assign s_axi_rdata[374] = \<const0> ;
assign s_axi_rdata[373] = \<const0> ;
assign s_axi_rdata[372] = \<const0> ;
assign s_axi_rdata[371] = \<const0> ;
assign s_axi_rdata[370] = \<const0> ;
assign s_axi_rdata[369] = \<const0> ;
assign s_axi_rdata[368] = \<const0> ;
assign s_axi_rdata[367] = \<const0> ;
assign s_axi_rdata[366] = \<const0> ;
assign s_axi_rdata[365] = \<const0> ;
assign s_axi_rdata[364] = \<const0> ;
assign s_axi_rdata[363] = \<const0> ;
assign s_axi_rdata[362] = \<const0> ;
assign s_axi_rdata[361] = \<const0> ;
assign s_axi_rdata[360] = \<const0> ;
assign s_axi_rdata[359] = \<const0> ;
assign s_axi_rdata[358] = \<const0> ;
assign s_axi_rdata[357] = \<const0> ;
assign s_axi_rdata[356] = \<const0> ;
assign s_axi_rdata[355] = \<const0> ;
assign s_axi_rdata[354] = \<const0> ;
assign s_axi_rdata[353] = \<const0> ;
assign s_axi_rdata[352] = \<const0> ;
assign s_axi_rdata[351] = \<const0> ;
assign s_axi_rdata[350] = \<const0> ;
assign s_axi_rdata[349] = \<const0> ;
assign s_axi_rdata[348] = \<const0> ;
assign s_axi_rdata[347] = \<const0> ;
assign s_axi_rdata[346] = \<const0> ;
assign s_axi_rdata[345] = \<const0> ;
assign s_axi_rdata[344] = \<const0> ;
assign s_axi_rdata[343] = \<const0> ;
assign s_axi_rdata[342] = \<const0> ;
assign s_axi_rdata[341] = \<const0> ;
assign s_axi_rdata[340] = \<const0> ;
assign s_axi_rdata[339] = \<const0> ;
assign s_axi_rdata[338] = \<const0> ;
assign s_axi_rdata[337] = \<const0> ;
assign s_axi_rdata[336] = \<const0> ;
assign s_axi_rdata[335] = \<const0> ;
assign s_axi_rdata[334] = \<const0> ;
assign s_axi_rdata[333] = \<const0> ;
assign s_axi_rdata[332] = \<const0> ;
assign s_axi_rdata[331] = \<const0> ;
assign s_axi_rdata[330] = \<const0> ;
assign s_axi_rdata[329] = \<const0> ;
assign s_axi_rdata[328] = \<const0> ;
assign s_axi_rdata[327] = \<const0> ;
assign s_axi_rdata[326] = \<const0> ;
assign s_axi_rdata[325] = \<const0> ;
assign s_axi_rdata[324] = \<const0> ;
assign s_axi_rdata[323] = \<const0> ;
assign s_axi_rdata[322] = \<const0> ;
assign s_axi_rdata[321] = \<const0> ;
assign s_axi_rdata[320] = \<const0> ;
assign s_axi_rdata[319] = \<const0> ;
assign s_axi_rdata[318] = \<const0> ;
assign s_axi_rdata[317] = \<const0> ;
assign s_axi_rdata[316] = \<const0> ;
assign s_axi_rdata[315] = \<const0> ;
assign s_axi_rdata[314] = \<const0> ;
assign s_axi_rdata[313] = \<const0> ;
assign s_axi_rdata[312] = \<const0> ;
assign s_axi_rdata[311] = \<const0> ;
assign s_axi_rdata[310] = \<const0> ;
assign s_axi_rdata[309] = \<const0> ;
assign s_axi_rdata[308] = \<const0> ;
assign s_axi_rdata[307] = \<const0> ;
assign s_axi_rdata[306] = \<const0> ;
assign s_axi_rdata[305] = \<const0> ;
assign s_axi_rdata[304] = \<const0> ;
assign s_axi_rdata[303] = \<const0> ;
assign s_axi_rdata[302] = \<const0> ;
assign s_axi_rdata[301] = \<const0> ;
assign s_axi_rdata[300] = \<const0> ;
assign s_axi_rdata[299] = \<const0> ;
assign s_axi_rdata[298] = \<const0> ;
assign s_axi_rdata[297] = \<const0> ;
assign s_axi_rdata[296] = \<const0> ;
assign s_axi_rdata[295] = \<const0> ;
assign s_axi_rdata[294] = \<const0> ;
assign s_axi_rdata[293] = \<const0> ;
assign s_axi_rdata[292] = \<const0> ;
assign s_axi_rdata[291] = \<const0> ;
assign s_axi_rdata[290] = \<const0> ;
assign s_axi_rdata[289] = \<const0> ;
assign s_axi_rdata[288] = \<const0> ;
assign s_axi_rdata[287] = \<const0> ;
assign s_axi_rdata[286] = \<const0> ;
assign s_axi_rdata[285] = \<const0> ;
assign s_axi_rdata[284] = \<const0> ;
assign s_axi_rdata[283] = \<const0> ;
assign s_axi_rdata[282] = \<const0> ;
assign s_axi_rdata[281] = \<const0> ;
assign s_axi_rdata[280] = \<const0> ;
assign s_axi_rdata[279] = \<const0> ;
assign s_axi_rdata[278] = \<const0> ;
assign s_axi_rdata[277] = \<const0> ;
assign s_axi_rdata[276] = \<const0> ;
assign s_axi_rdata[275] = \<const0> ;
assign s_axi_rdata[274] = \<const0> ;
assign s_axi_rdata[273] = \<const0> ;
assign s_axi_rdata[272] = \<const0> ;
assign s_axi_rdata[271] = \<const0> ;
assign s_axi_rdata[270] = \<const0> ;
assign s_axi_rdata[269] = \<const0> ;
assign s_axi_rdata[268] = \<const0> ;
assign s_axi_rdata[267] = \<const0> ;
assign s_axi_rdata[266] = \<const0> ;
assign s_axi_rdata[265] = \<const0> ;
assign s_axi_rdata[264] = \<const0> ;
assign s_axi_rdata[263] = \<const0> ;
assign s_axi_rdata[262] = \<const0> ;
assign s_axi_rdata[261] = \<const0> ;
assign s_axi_rdata[260] = \<const0> ;
assign s_axi_rdata[259] = \<const0> ;
assign s_axi_rdata[258] = \<const0> ;
assign s_axi_rdata[257] = \<const0> ;
assign s_axi_rdata[256] = \<const0> ;
assign s_axi_rdata[255] = \<const0> ;
assign s_axi_rdata[254] = \<const0> ;
assign s_axi_rdata[253] = \<const0> ;
assign s_axi_rdata[252] = \<const0> ;
assign s_axi_rdata[251] = \<const0> ;
assign s_axi_rdata[250] = \<const0> ;
assign s_axi_rdata[249] = \<const0> ;
assign s_axi_rdata[248] = \<const0> ;
assign s_axi_rdata[247] = \<const0> ;
assign s_axi_rdata[246] = \<const0> ;
assign s_axi_rdata[245] = \<const0> ;
assign s_axi_rdata[244] = \<const0> ;
assign s_axi_rdata[243] = \<const0> ;
assign s_axi_rdata[242] = \<const0> ;
assign s_axi_rdata[241] = \<const0> ;
assign s_axi_rdata[240] = \<const0> ;
assign s_axi_rdata[239] = \<const0> ;
assign s_axi_rdata[238] = \<const0> ;
assign s_axi_rdata[237] = \<const0> ;
assign s_axi_rdata[236] = \<const0> ;
assign s_axi_rdata[235] = \<const0> ;
assign s_axi_rdata[234] = \<const0> ;
assign s_axi_rdata[233] = \<const0> ;
assign s_axi_rdata[232] = \<const0> ;
assign s_axi_rdata[231] = \<const0> ;
assign s_axi_rdata[230] = \<const0> ;
assign s_axi_rdata[229] = \<const0> ;
assign s_axi_rdata[228] = \<const0> ;
assign s_axi_rdata[227] = \<const0> ;
assign s_axi_rdata[226] = \<const0> ;
assign s_axi_rdata[225] = \<const0> ;
assign s_axi_rdata[224] = \<const0> ;
assign s_axi_rdata[223] = \<const0> ;
assign s_axi_rdata[222] = \<const0> ;
assign s_axi_rdata[221] = \<const0> ;
assign s_axi_rdata[220] = \<const0> ;
assign s_axi_rdata[219] = \<const0> ;
assign s_axi_rdata[218] = \<const0> ;
assign s_axi_rdata[217] = \<const0> ;
assign s_axi_rdata[216] = \<const0> ;
assign s_axi_rdata[215] = \<const0> ;
assign s_axi_rdata[214] = \<const0> ;
assign s_axi_rdata[213] = \<const0> ;
assign s_axi_rdata[212] = \<const0> ;
assign s_axi_rdata[211] = \<const0> ;
assign s_axi_rdata[210] = \<const0> ;
assign s_axi_rdata[209] = \<const0> ;
assign s_axi_rdata[208] = \<const0> ;
assign s_axi_rdata[207] = \<const0> ;
assign s_axi_rdata[206] = \<const0> ;
assign s_axi_rdata[205] = \<const0> ;
assign s_axi_rdata[204] = \<const0> ;
assign s_axi_rdata[203] = \<const0> ;
assign s_axi_rdata[202] = \<const0> ;
assign s_axi_rdata[201] = \<const0> ;
assign s_axi_rdata[200] = \<const0> ;
assign s_axi_rdata[199] = \<const0> ;
assign s_axi_rdata[198] = \<const0> ;
assign s_axi_rdata[197] = \<const0> ;
assign s_axi_rdata[196] = \<const0> ;
assign s_axi_rdata[195] = \<const0> ;
assign s_axi_rdata[194] = \<const0> ;
assign s_axi_rdata[193] = \<const0> ;
assign s_axi_rdata[192] = \<const0> ;
assign s_axi_rdata[191] = \<const0> ;
assign s_axi_rdata[190] = \<const0> ;
assign s_axi_rdata[189] = \<const0> ;
assign s_axi_rdata[188] = \<const0> ;
assign s_axi_rdata[187] = \<const0> ;
assign s_axi_rdata[186] = \<const0> ;
assign s_axi_rdata[185] = \<const0> ;
assign s_axi_rdata[184] = \<const0> ;
assign s_axi_rdata[183] = \<const0> ;
assign s_axi_rdata[182] = \<const0> ;
assign s_axi_rdata[181] = \<const0> ;
assign s_axi_rdata[180] = \<const0> ;
assign s_axi_rdata[179] = \<const0> ;
assign s_axi_rdata[178] = \<const0> ;
assign s_axi_rdata[177] = \<const0> ;
assign s_axi_rdata[176] = \<const0> ;
assign s_axi_rdata[175] = \<const0> ;
assign s_axi_rdata[174] = \<const0> ;
assign s_axi_rdata[173] = \<const0> ;
assign s_axi_rdata[172] = \<const0> ;
assign s_axi_rdata[171] = \<const0> ;
assign s_axi_rdata[170] = \<const0> ;
assign s_axi_rdata[169] = \<const0> ;
assign s_axi_rdata[168] = \<const0> ;
assign s_axi_rdata[167] = \<const0> ;
assign s_axi_rdata[166] = \<const0> ;
assign s_axi_rdata[165] = \<const0> ;
assign s_axi_rdata[164] = \<const0> ;
assign s_axi_rdata[163] = \<const0> ;
assign s_axi_rdata[162] = \<const0> ;
assign s_axi_rdata[161] = \<const0> ;
assign s_axi_rdata[160] = \<const0> ;
assign s_axi_rdata[159] = \<const0> ;
assign s_axi_rdata[158] = \<const0> ;
assign s_axi_rdata[157] = \<const0> ;
assign s_axi_rdata[156] = \<const0> ;
assign s_axi_rdata[155] = \<const0> ;
assign s_axi_rdata[154] = \<const0> ;
assign s_axi_rdata[153] = \<const0> ;
assign s_axi_rdata[152] = \<const0> ;
assign s_axi_rdata[151] = \<const0> ;
assign s_axi_rdata[150] = \<const0> ;
assign s_axi_rdata[149] = \<const0> ;
assign s_axi_rdata[148] = \<const0> ;
assign s_axi_rdata[147] = \<const0> ;
assign s_axi_rdata[146] = \<const0> ;
assign s_axi_rdata[145] = \<const0> ;
assign s_axi_rdata[144] = \<const0> ;
assign s_axi_rdata[143] = \<const0> ;
assign s_axi_rdata[142] = \<const0> ;
assign s_axi_rdata[141] = \<const0> ;
assign s_axi_rdata[140] = \<const0> ;
assign s_axi_rdata[139] = \<const0> ;
assign s_axi_rdata[138] = \<const0> ;
assign s_axi_rdata[137] = \<const0> ;
assign s_axi_rdata[136] = \<const0> ;
assign s_axi_rdata[135] = \<const0> ;
assign s_axi_rdata[134] = \<const0> ;
assign s_axi_rdata[133] = \<const0> ;
assign s_axi_rdata[132] = \<const0> ;
assign s_axi_rdata[131] = \<const0> ;
assign s_axi_rdata[130] = \<const0> ;
assign s_axi_rdata[129] = \<const0> ;
assign s_axi_rdata[128] = \<const0> ;
assign s_axi_rdata[127] = \<const0> ;
assign s_axi_rdata[126] = \<const0> ;
assign s_axi_rdata[125] = \<const0> ;
assign s_axi_rdata[124] = \<const0> ;
assign s_axi_rdata[123] = \<const0> ;
assign s_axi_rdata[122] = \<const0> ;
assign s_axi_rdata[121] = \<const0> ;
assign s_axi_rdata[120] = \<const0> ;
assign s_axi_rdata[119] = \<const0> ;
assign s_axi_rdata[118] = \<const0> ;
assign s_axi_rdata[117] = \<const0> ;
assign s_axi_rdata[116] = \<const0> ;
assign s_axi_rdata[115] = \<const0> ;
assign s_axi_rdata[114] = \<const0> ;
assign s_axi_rdata[113] = \<const0> ;
assign s_axi_rdata[112] = \<const0> ;
assign s_axi_rdata[111] = \<const0> ;
assign s_axi_rdata[110] = \<const0> ;
assign s_axi_rdata[109] = \<const0> ;
assign s_axi_rdata[108] = \<const0> ;
assign s_axi_rdata[107] = \<const0> ;
assign s_axi_rdata[106] = \<const0> ;
assign s_axi_rdata[105] = \<const0> ;
assign s_axi_rdata[104] = \<const0> ;
assign s_axi_rdata[103] = \<const0> ;
assign s_axi_rdata[102] = \<const0> ;
assign s_axi_rdata[101] = \<const0> ;
assign s_axi_rdata[100] = \<const0> ;
assign s_axi_rdata[99] = \<const0> ;
assign s_axi_rdata[98] = \<const0> ;
assign s_axi_rdata[97] = \<const0> ;
assign s_axi_rdata[96] = \<const0> ;
assign s_axi_rdata[95] = \<const0> ;
assign s_axi_rdata[94] = \<const0> ;
assign s_axi_rdata[93] = \<const0> ;
assign s_axi_rdata[92] = \<const0> ;
assign s_axi_rdata[91] = \<const0> ;
assign s_axi_rdata[90] = \<const0> ;
assign s_axi_rdata[89] = \<const0> ;
assign s_axi_rdata[88] = \<const0> ;
assign s_axi_rdata[87] = \<const0> ;
assign s_axi_rdata[86] = \<const0> ;
assign s_axi_rdata[85] = \<const0> ;
assign s_axi_rdata[84] = \<const0> ;
assign s_axi_rdata[83] = \<const0> ;
assign s_axi_rdata[82] = \<const0> ;
assign s_axi_rdata[81] = \<const0> ;
assign s_axi_rdata[80] = \<const0> ;
assign s_axi_rdata[79] = \<const0> ;
assign s_axi_rdata[78] = \<const0> ;
assign s_axi_rdata[77] = \<const0> ;
assign s_axi_rdata[76] = \<const0> ;
assign s_axi_rdata[75] = \<const0> ;
assign s_axi_rdata[74] = \<const0> ;
assign s_axi_rdata[73] = \<const0> ;
assign s_axi_rdata[72] = \<const0> ;
assign s_axi_rdata[71] = \<const0> ;
assign s_axi_rdata[70] = \<const0> ;
assign s_axi_rdata[69] = \<const0> ;
assign s_axi_rdata[68] = \<const0> ;
assign s_axi_rdata[67] = \<const0> ;
assign s_axi_rdata[66] = \<const0> ;
assign s_axi_rdata[65] = \<const0> ;
assign s_axi_rdata[64] = \<const0> ;
assign s_axi_rdata[63] = \<const0> ;
assign s_axi_rdata[62] = \<const0> ;
assign s_axi_rdata[61] = \<const0> ;
assign s_axi_rdata[60] = \<const0> ;
assign s_axi_rdata[59] = \<const0> ;
assign s_axi_rdata[58] = \<const0> ;
assign s_axi_rdata[57] = \<const0> ;
assign s_axi_rdata[56] = \<const0> ;
assign s_axi_rdata[55] = \<const0> ;
assign s_axi_rdata[54] = \<const0> ;
assign s_axi_rdata[53] = \<const0> ;
assign s_axi_rdata[52] = \<const0> ;
assign s_axi_rdata[51] = \<const0> ;
assign s_axi_rdata[50] = \<const0> ;
assign s_axi_rdata[49] = \<const0> ;
assign s_axi_rdata[48] = \<const0> ;
assign s_axi_rdata[47] = \<const0> ;
assign s_axi_rdata[46] = \<const0> ;
assign s_axi_rdata[45] = \<const0> ;
assign s_axi_rdata[44] = \<const0> ;
assign s_axi_rdata[43] = \<const0> ;
assign s_axi_rdata[42] = \<const0> ;
assign s_axi_rdata[41] = \<const0> ;
assign s_axi_rdata[40] = \<const0> ;
assign s_axi_rdata[39] = \<const0> ;
assign s_axi_rdata[38] = \<const0> ;
assign s_axi_rdata[37] = \<const0> ;
assign s_axi_rdata[36] = \<const0> ;
assign s_axi_rdata[35] = \<const0> ;
assign s_axi_rdata[34] = \<const0> ;
assign s_axi_rdata[33] = \<const0> ;
assign s_axi_rdata[32] = \<const0> ;
assign s_axi_rdata[31] = \<const0> ;
assign s_axi_rdata[30] = \<const0> ;
assign s_axi_rdata[29] = \<const0> ;
assign s_axi_rdata[28] = \<const0> ;
assign s_axi_rdata[27] = \<const0> ;
assign s_axi_rdata[26] = \<const0> ;
assign s_axi_rdata[25] = \<const0> ;
assign s_axi_rdata[24] = \<const0> ;
assign s_axi_rdata[23] = \<const0> ;
assign s_axi_rdata[22] = \<const0> ;
assign s_axi_rdata[21] = \<const0> ;
assign s_axi_rdata[20] = \<const0> ;
assign s_axi_rdata[19] = \<const0> ;
assign s_axi_rdata[18] = \<const0> ;
assign s_axi_rdata[17] = \<const0> ;
assign s_axi_rdata[16] = \<const0> ;
assign s_axi_rdata[15] = \<const0> ;
assign s_axi_rdata[14] = \<const0> ;
assign s_axi_rdata[13] = \<const0> ;
assign s_axi_rdata[12] = \<const0> ;
assign s_axi_rdata[11] = \<const0> ;
assign s_axi_rdata[10] = \<const0> ;
assign s_axi_rdata[9] = \<const0> ;
assign s_axi_rdata[8] = \<const0> ;
assign s_axi_rdata[7] = \<const0> ;
assign s_axi_rdata[6] = \<const0> ;
assign s_axi_rdata[5] = \<const0> ;
assign s_axi_rdata[4] = \<const0> ;
assign s_axi_rdata[3] = \<const0> ;
assign s_axi_rdata[2] = \<const0> ;
assign s_axi_rdata[1] = \<const0> ;
assign s_axi_rdata[0] = \<const0> ;
assign s_axi_rid[3] = \<const0> ;
assign s_axi_rid[2] = \<const0> ;
assign s_axi_rid[1] = \<const0> ;
assign s_axi_rid[0] = \<const0> ;
assign s_axi_rlast = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
assign s_axi_rvalid = \<const0> ;
assign s_axi_sbiterr = \<const0> ;
assign s_axi_wready = \<const0> ;
assign sbiterr = \<const0> ;
GND GND
(.G(\<const0> ));
Instructions_blk_mem_gen_v8_2_synth inst_blk_mem_gen
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_2_synth" *)
module Instructions_blk_mem_gen_v8_2_synth
(douta,
clka,
addra);
output [799:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [799:0]douta;
Instructions_blk_mem_gen_top \gnativebmg.native_blk_mem_gen
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:fifo_generator:10.0
// IP Revision: 128000
`timescale 1ns/1ps
module golden_ticket_fifo (
wr_clk,
rd_clk,
din,
wr_en,
rd_en,
dout,
full,
empty
);
input wr_clk;
input rd_clk;
input [31 : 0] din;
input wr_en;
input rd_en;
output [31 : 0] dout;
output full;
output empty;
fifo_generator_v10_0 #(
.C_COMMON_CLOCK(0),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(10),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(32),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(32),
.C_ENABLE_RLOCS(0),
.C_FAMILY("kintex7"),
.C_FULL_FLAGS_RST_VAL(0),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_INT_CLK(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(0),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(2),
.C_INIT_WR_PNTR_VAL(0),
.C_MEMORY_TYPE(1),
.C_MIF_FILE_NAME("BlankString"),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(2),
.C_PRELOAD_REGS(1),
.C_PRIM_FIFO_TYPE("1kx36"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(2),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(3),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(1021),
.C_PROG_FULL_THRESH_NEGATE_VAL(1020),
.C_PROG_FULL_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(10),
.C_RD_DEPTH(1024),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(10),
.C_UNDERFLOW_LOW(0),
.C_USE_DOUT_RST(0),
.C_USE_ECC(0),
.C_USE_EMBEDDED_REG(1),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(0),
.C_VALID_LOW(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(10),
.C_WR_DEPTH(1024),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(10),
.C_WR_RESPONSE_LATENCY(1),
.C_MSGON_VAL(1),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_SYNCHRONIZER_STAGE(2),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(0),
.C_HAS_AXI_WR_CHANNEL(0),
.C_HAS_AXI_RD_CHANNEL(0),
.C_HAS_SLAVE_CE(0),
.C_HAS_MASTER_CE(0),
.C_ADD_NGC_CONSTRAINT(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_AXI_ID_WIDTH(4),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(64),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_RUSER(0),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_HAS_AXIS_TDATA(0),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TUSER(0),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TKEEP(0),
.C_AXIS_TDATA_WIDTH(64),
.C_AXIS_TID_WIDTH(8),
.C_AXIS_TDEST_WIDTH(4),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(8),
.C_AXIS_TKEEP_WIDTH(8),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WRCH_TYPE(0),
.C_RACH_TYPE(0),
.C_RDCH_TYPE(0),
.C_AXIS_TYPE(0),
.C_IMPLEMENTATION_TYPE_WACH(1),
.C_IMPLEMENTATION_TYPE_WDCH(1),
.C_IMPLEMENTATION_TYPE_WRCH(1),
.C_IMPLEMENTATION_TYPE_RACH(1),
.C_IMPLEMENTATION_TYPE_RDCH(1),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_AXIS(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_DIN_WIDTH_WACH(32),
.C_DIN_WIDTH_WDCH(64),
.C_DIN_WIDTH_WRCH(2),
.C_DIN_WIDTH_RACH(32),
.C_DIN_WIDTH_RDCH(64),
.C_DIN_WIDTH_AXIS(1),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_AXIS(1024),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_PROG_FULL_TYPE_WACH(0),
.C_PROG_FULL_TYPE_WDCH(0),
.C_PROG_FULL_TYPE_WRCH(0),
.C_PROG_FULL_TYPE_RACH(0),
.C_PROG_FULL_TYPE_RDCH(0),
.C_PROG_FULL_TYPE_AXIS(0),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_EMPTY_TYPE_WACH(0),
.C_PROG_EMPTY_TYPE_WDCH(0),
.C_PROG_EMPTY_TYPE_WRCH(0),
.C_PROG_EMPTY_TYPE_RACH(0),
.C_PROG_EMPTY_TYPE_RDCH(0),
.C_PROG_EMPTY_TYPE_AXIS(0),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_AXIS(0)
) inst (
.backup(1'B0),
.backup_marker(1'B0),
.clk(1'B0),
.rst(1'B0),
.srst(1'B0),
.wr_clk(wr_clk),
.wr_rst(1'B0),
.rd_clk(rd_clk),
.rd_rst(1'B0),
.din(din),
.wr_en(wr_en),
.rd_en(rd_en),
.prog_empty_thresh(10'B0),
.prog_empty_thresh_assert(10'B0),
.prog_empty_thresh_negate(10'B0),
.prog_full_thresh(10'B0),
.prog_full_thresh_assert(10'B0),
.prog_full_thresh_negate(10'B0),
.int_clk(1'B0),
.injectdbiterr(1'B0),
.injectsbiterr(1'B0),
.dout(dout),
.full(full),
.almost_full(),
.wr_ack(),
.overflow(),
.empty(empty),
.almost_empty(),
.valid(),
.underflow(),
.data_count(),
.rd_data_count(),
.wr_data_count(),
.prog_full(),
.prog_empty(),
.sbiterr(),
.dbiterr(),
.m_aclk(1'B0),
.s_aclk(1'B0),
.s_aresetn(1'B0),
.m_aclk_en(1'B0),
.s_aclk_en(1'B0),
.s_axi_awid(4'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awlock(2'B0),
.s_axi_awcache(4'B0),
.s_axi_awprot(3'B0),
.s_axi_awqos(4'B0),
.s_axi_awregion(4'B0),
.s_axi_awuser(1'B0),
.s_axi_awvalid(1'B0),
.s_axi_awready(),
.s_axi_wid(4'B0),
.s_axi_wdata(64'B0),
.s_axi_wstrb(8'B0),
.s_axi_wlast(1'B0),
.s_axi_wuser(1'B0),
.s_axi_wvalid(1'B0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_buser(),
.s_axi_bvalid(),
.s_axi_bready(1'B0),
.m_axi_awid(),
.m_axi_awaddr(),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(),
.m_axi_awqos(),
.m_axi_awregion(),
.m_axi_awuser(),
.m_axi_awvalid(),
.m_axi_awready(1'B0),
.m_axi_wid(),
.m_axi_wdata(),
.m_axi_wstrb(),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(),
.m_axi_wready(1'B0),
.m_axi_bid(4'B0),
.m_axi_bresp(2'B0),
.m_axi_buser(1'B0),
.m_axi_bvalid(1'B0),
.m_axi_bready(),
.s_axi_arid(4'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arlock(2'B0),
.s_axi_arcache(4'B0),
.s_axi_arprot(3'B0),
.s_axi_arqos(4'B0),
.s_axi_arregion(4'B0),
.s_axi_aruser(1'B0),
.s_axi_arvalid(1'B0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_ruser(),
.s_axi_rvalid(),
.s_axi_rready(1'B0),
.m_axi_arid(),
.m_axi_araddr(),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(),
.m_axi_arqos(),
.m_axi_arregion(),
.m_axi_aruser(),
.m_axi_arvalid(),
.m_axi_arready(1'B0),
.m_axi_rid(4'B0),
.m_axi_rdata(64'B0),
.m_axi_rresp(2'B0),
.m_axi_rlast(1'B0),
.m_axi_ruser(1'B0),
.m_axi_rvalid(1'B0),
.m_axi_rready(),
.s_axis_tvalid(1'B0),
.s_axis_tready(),
.s_axis_tdata(64'B0),
.s_axis_tstrb(8'B0),
.s_axis_tkeep(8'B0),
.s_axis_tlast(1'B0),
.s_axis_tid(8'B0),
.s_axis_tdest(4'B0),
.s_axis_tuser(4'B0),
.m_axis_tvalid(),
.m_axis_tready(1'B0),
.m_axis_tdata(),
.m_axis_tstrb(),
.m_axis_tkeep(),
.m_axis_tlast(),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(),
.axi_aw_injectsbiterr(1'B0),
.axi_aw_injectdbiterr(1'B0),
.axi_aw_prog_full_thresh(4'B0),
.axi_aw_prog_empty_thresh(4'B0),
.axi_aw_data_count(),
.axi_aw_wr_data_count(),
.axi_aw_rd_data_count(),
.axi_aw_sbiterr(),
.axi_aw_dbiterr(),
.axi_aw_overflow(),
.axi_aw_underflow(),
.axi_aw_prog_full(),
.axi_aw_prog_empty(),
.axi_w_injectsbiterr(1'B0),
.axi_w_injectdbiterr(1'B0),
.axi_w_prog_full_thresh(10'B0),
.axi_w_prog_empty_thresh(10'B0),
.axi_w_data_count(),
.axi_w_wr_data_count(),
.axi_w_rd_data_count(),
.axi_w_sbiterr(),
.axi_w_dbiterr(),
.axi_w_overflow(),
.axi_w_underflow(),
.axi_b_injectsbiterr(1'B0),
.axi_w_prog_full(),
.axi_w_prog_empty(),
.axi_b_injectdbiterr(1'B0),
.axi_b_prog_full_thresh(4'B0),
.axi_b_prog_empty_thresh(4'B0),
.axi_b_data_count(),
.axi_b_wr_data_count(),
.axi_b_rd_data_count(),
.axi_b_sbiterr(),
.axi_b_dbiterr(),
.axi_b_overflow(),
.axi_b_underflow(),
.axi_ar_injectsbiterr(1'B0),
.axi_b_prog_full(),
.axi_b_prog_empty(),
.axi_ar_injectdbiterr(1'B0),
.axi_ar_prog_full_thresh(4'B0),
.axi_ar_prog_empty_thresh(4'B0),
.axi_ar_data_count(),
.axi_ar_wr_data_count(),
.axi_ar_rd_data_count(),
.axi_ar_sbiterr(),
.axi_ar_dbiterr(),
.axi_ar_overflow(),
.axi_ar_underflow(),
.axi_ar_prog_full(),
.axi_ar_prog_empty(),
.axi_r_injectsbiterr(1'B0),
.axi_r_injectdbiterr(1'B0),
.axi_r_prog_full_thresh(10'B0),
.axi_r_prog_empty_thresh(10'B0),
.axi_r_data_count(),
.axi_r_wr_data_count(),
.axi_r_rd_data_count(),
.axi_r_sbiterr(),
.axi_r_dbiterr(),
.axi_r_overflow(),
.axi_r_underflow(),
.axis_injectsbiterr(1'B0),
.axi_r_prog_full(),
.axi_r_prog_empty(),
.axis_injectdbiterr(1'B0),
.axis_prog_full_thresh(10'B0),
.axis_prog_empty_thresh(10'B0),
.axis_data_count(),
.axis_wr_data_count(),
.axis_rd_data_count(),
.axis_sbiterr(),
.axis_dbiterr(),
.axis_overflow(),
.axis_underflow(),
.axis_prog_full(),
.axis_prog_empty()
);
endmodule
|
(** * Extraction: Extracting ML from Coq *)
(* $Date: 2013-01-16 22:29:57 -0500 (Wed, 16 Jan 2013) $ *)
(** * Basic Extraction *)
(** In its simplest form, program extraction from Coq is completely straightforward. *)
(** First we say what language we want to extract into. Options are OCaml (the
most mature), Haskell (which mostly works), and Scheme (a bit out
of date). *)
Extraction Language Ocaml.
(** Now we load up the Coq environment with some definitions, either
directly or by importing them from other modules. *)
Require Import SfLib.
Require Import ImpCEvalFun.
(** Finally, we tell Coq the name of a definition to extract and the
name of a file to put the extracted code into. *)
Extraction "imp1.ml" ceval_step.
(** When Coq processes this command, it generates a file [imp1.ml]
containing an extracted version of [ceval_step], together with
everything that it recursively depends on. Have a look at this
file now. *)
(* ############################################################## *)
(** * Controlling Extraction of Specific Types *)
(** We can tell Coq to extract certain [Inductive] definitions to
specific OCaml types. For each one, we must say
- how the Coq type itself should be represented in OCaml, and
- how each constructor should be translated. *)
Extract Inductive bool => "bool" [ "true" "false" ].
(** Also, for non-enumeration types (where the constructors take
arguments), we give an OCaml expression that can be used as a
"recursor" over elements of the type. (Think Church numerals.) *)
Extract Inductive nat => "int"
[ "0" "(fun x -> x + 1)" ]
"(fun zero succ n ->
if n=0 then zero () else succ (n-1))".
(** We can also extract defined constants to specific OCaml terms or
operators. *)
Extract Constant plus => "( + )".
Extract Constant mult => "( * )".
Extract Constant beq_nat => "( = )".
(** Important: It is entirely _your responsibility_ to make sure that
the translations you're proving make sense. For example, it might
be tempting to include this one
Extract Constant minus => "( - )".
but doing so could lead to serious confusion! (Why?)
*)
Extraction "imp2.ml" ceval_step.
(** Have a look at the file [imp2.ml]. Notice how the fundamental
definitions have changed from [imp1.ml]. *)
(* ############################################################## *)
(** * A Complete Example *)
(** To use our extracted evaluator to run Imp programs, all we need to
add is a tiny driver program that calls the evaluator and somehow
prints out the result.
For simplicity, we'll print results by dumping out the first four
memory locations in the final state.
Also, to make it easier to type in examples, let's extract a
parser from the [ImpParser] Coq module. To do this, we need a few
more declarations to set up the right correspondence between Coq
strings and lists of OCaml characters. *)
Require Import Ascii String.
Extract Inductive ascii => char
[
"(* If this appears, you're using Ascii internals. Please don't *) (fun (b0,b1,b2,b3,b4,b5,b6,b7) -> let f b i = if b then 1 lsl i else 0 in Char.chr (f b0 0 + f b1 1 + f b2 2 + f b3 3 + f b4 4 + f b5 5 + f b6 6 + f b7 7))"
]
"(* If this appears, you're using Ascii internals. Please don't *) (fun f c -> let n = Char.code c in let h i = (n land (1 lsl i)) <> 0 in f (h 0) (h 1) (h 2) (h 3) (h 4) (h 5) (h 6) (h 7))".
Extract Constant zero => "'\000'".
Extract Constant one => "'\001'".
Extract Constant shift =>
"fun b c -> Char.chr (((Char.code c) lsl 1) land 255 + if b then 1 else 0)".
Extract Inlined Constant ascii_dec => "(=)".
(** We also need one more variant of booleans. *)
Extract Inductive sumbool => "bool" ["true" "false"].
(** The extraction is the same as always. *)
Require Import Imp.
Require Import ImpParser.
Extraction "imp.ml" empty_state ceval_step parse.
(** Now let's run our generated Imp evaluator. First, have a look at
[impdriver.ml]. (This was written by hand, not extracted.)
Next, compile the driver together with the extracted code and
execute it, as follows.
<<
ocamlc -w -20 -w -26 -o impdriver imp.mli imp.ml impdriver.ml
./impdriver
>>
(The [-w] flags to [ocamlc] are just there to suppress a few
spurious warnings.) *)
(* ############################################################## *)
(** * Discussion *)
(** Since we've proved that the [ceval_step] function behaves the same
as the [ceval] relation in an appropriate sense, the extracted
program can be viewed as a _certified_ Imp interpreter. (Of
course, the parser is not certified in any interesting sense,
since we didn't prove anything about it.) *)
|
//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_system_jtag_uart_sim_scfifo_w (
// inputs:
clk,
fifo_wdata,
fifo_wr,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
)
;
output fifo_FF;
output [ 7: 0] r_dat;
output wfifo_empty;
output [ 5: 0] wfifo_used;
input clk;
input [ 7: 0] fifo_wdata;
input fifo_wr;
wire fifo_FF;
wire [ 7: 0] r_dat;
wire wfifo_empty;
wire [ 5: 0] wfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
always @(posedge clk)
begin
if (fifo_wr)
$write("%c", fifo_wdata);
end
assign wfifo_used = {6{1'b0}};
assign r_dat = {8{1'b0}};
assign fifo_FF = 1'b0;
assign wfifo_empty = 1'b1;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_system_jtag_uart_scfifo_w (
// inputs:
clk,
fifo_clear,
fifo_wdata,
fifo_wr,
rd_wfifo,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
)
;
output fifo_FF;
output [ 7: 0] r_dat;
output wfifo_empty;
output [ 5: 0] wfifo_used;
input clk;
input fifo_clear;
input [ 7: 0] fifo_wdata;
input fifo_wr;
input rd_wfifo;
wire fifo_FF;
wire [ 7: 0] r_dat;
wire wfifo_empty;
wire [ 5: 0] wfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
soc_system_jtag_uart_sim_scfifo_w the_soc_system_jtag_uart_sim_scfifo_w
(
.clk (clk),
.fifo_FF (fifo_FF),
.fifo_wdata (fifo_wdata),
.fifo_wr (fifo_wr),
.r_dat (r_dat),
.wfifo_empty (wfifo_empty),
.wfifo_used (wfifo_used)
);
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// scfifo wfifo
// (
// .aclr (fifo_clear),
// .clock (clk),
// .data (fifo_wdata),
// .empty (wfifo_empty),
// .full (fifo_FF),
// .q (r_dat),
// .rdreq (rd_wfifo),
// .usedw (wfifo_used),
// .wrreq (fifo_wr)
// );
//
// defparam wfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
// wfifo.lpm_numwords = 64,
// wfifo.lpm_showahead = "OFF",
// wfifo.lpm_type = "scfifo",
// wfifo.lpm_width = 8,
// wfifo.lpm_widthu = 6,
// wfifo.overflow_checking = "OFF",
// wfifo.underflow_checking = "OFF",
// wfifo.use_eab = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_system_jtag_uart_sim_scfifo_r (
// inputs:
clk,
fifo_rd,
rst_n,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
)
;
output fifo_EF;
output [ 7: 0] fifo_rdata;
output rfifo_full;
output [ 5: 0] rfifo_used;
input clk;
input fifo_rd;
input rst_n;
reg [ 31: 0] bytes_left;
wire fifo_EF;
reg fifo_rd_d;
wire [ 7: 0] fifo_rdata;
wire new_rom;
wire [ 31: 0] num_bytes;
wire [ 6: 0] rfifo_entries;
wire rfifo_full;
wire [ 5: 0] rfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
// Generate rfifo_entries for simulation
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
begin
bytes_left <= 32'h0;
fifo_rd_d <= 1'b0;
end
else
begin
fifo_rd_d <= fifo_rd;
// decrement on read
if (fifo_rd_d)
bytes_left <= bytes_left - 1'b1;
// catch new contents
if (new_rom)
bytes_left <= num_bytes;
end
end
assign fifo_EF = bytes_left == 32'b0;
assign rfifo_full = bytes_left > 7'h40;
assign rfifo_entries = (rfifo_full) ? 7'h40 : bytes_left;
assign rfifo_used = rfifo_entries[5 : 0];
assign new_rom = 1'b0;
assign num_bytes = 32'b0;
assign fifo_rdata = 8'b0;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_system_jtag_uart_scfifo_r (
// inputs:
clk,
fifo_clear,
fifo_rd,
rst_n,
t_dat,
wr_rfifo,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
)
;
output fifo_EF;
output [ 7: 0] fifo_rdata;
output rfifo_full;
output [ 5: 0] rfifo_used;
input clk;
input fifo_clear;
input fifo_rd;
input rst_n;
input [ 7: 0] t_dat;
input wr_rfifo;
wire fifo_EF;
wire [ 7: 0] fifo_rdata;
wire rfifo_full;
wire [ 5: 0] rfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
soc_system_jtag_uart_sim_scfifo_r the_soc_system_jtag_uart_sim_scfifo_r
(
.clk (clk),
.fifo_EF (fifo_EF),
.fifo_rd (fifo_rd),
.fifo_rdata (fifo_rdata),
.rfifo_full (rfifo_full),
.rfifo_used (rfifo_used),
.rst_n (rst_n)
);
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// scfifo rfifo
// (
// .aclr (fifo_clear),
// .clock (clk),
// .data (t_dat),
// .empty (fifo_EF),
// .full (rfifo_full),
// .q (fifo_rdata),
// .rdreq (fifo_rd),
// .usedw (rfifo_used),
// .wrreq (wr_rfifo)
// );
//
// defparam rfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
// rfifo.lpm_numwords = 64,
// rfifo.lpm_showahead = "OFF",
// rfifo.lpm_type = "scfifo",
// rfifo.lpm_width = 8,
// rfifo.lpm_widthu = 6,
// rfifo.overflow_checking = "OFF",
// rfifo.underflow_checking = "OFF",
// rfifo.use_eab = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_system_jtag_uart (
// inputs:
av_address,
av_chipselect,
av_read_n,
av_write_n,
av_writedata,
clk,
rst_n,
// outputs:
av_irq,
av_readdata,
av_waitrequest,
dataavailable,
readyfordata
)
/* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R101,C106,D101,D103\"" */ ;
output av_irq;
output [ 31: 0] av_readdata;
output av_waitrequest;
output dataavailable;
output readyfordata;
input av_address;
input av_chipselect;
input av_read_n;
input av_write_n;
input [ 31: 0] av_writedata;
input clk;
input rst_n;
reg ac;
wire activity;
wire av_irq;
wire [ 31: 0] av_readdata;
reg av_waitrequest;
reg dataavailable;
reg fifo_AE;
reg fifo_AF;
wire fifo_EF;
wire fifo_FF;
wire fifo_clear;
wire fifo_rd;
wire [ 7: 0] fifo_rdata;
wire [ 7: 0] fifo_wdata;
reg fifo_wr;
reg ien_AE;
reg ien_AF;
wire ipen_AE;
wire ipen_AF;
reg pause_irq;
wire [ 7: 0] r_dat;
wire r_ena;
reg r_val;
wire rd_wfifo;
reg read_0;
reg readyfordata;
wire rfifo_full;
wire [ 5: 0] rfifo_used;
reg rvalid;
reg sim_r_ena;
reg sim_t_dat;
reg sim_t_ena;
reg sim_t_pause;
wire [ 7: 0] t_dat;
reg t_dav;
wire t_ena;
wire t_pause;
wire wfifo_empty;
wire [ 5: 0] wfifo_used;
reg woverflow;
wire wr_rfifo;
//avalon_jtag_slave, which is an e_avalon_slave
assign rd_wfifo = r_ena & ~wfifo_empty;
assign wr_rfifo = t_ena & ~rfifo_full;
assign fifo_clear = ~rst_n;
soc_system_jtag_uart_scfifo_w the_soc_system_jtag_uart_scfifo_w
(
.clk (clk),
.fifo_FF (fifo_FF),
.fifo_clear (fifo_clear),
.fifo_wdata (fifo_wdata),
.fifo_wr (fifo_wr),
.r_dat (r_dat),
.rd_wfifo (rd_wfifo),
.wfifo_empty (wfifo_empty),
.wfifo_used (wfifo_used)
);
soc_system_jtag_uart_scfifo_r the_soc_system_jtag_uart_scfifo_r
(
.clk (clk),
.fifo_EF (fifo_EF),
.fifo_clear (fifo_clear),
.fifo_rd (fifo_rd),
.fifo_rdata (fifo_rdata),
.rfifo_full (rfifo_full),
.rfifo_used (rfifo_used),
.rst_n (rst_n),
.t_dat (t_dat),
.wr_rfifo (wr_rfifo)
);
assign ipen_AE = ien_AE & fifo_AE;
assign ipen_AF = ien_AF & (pause_irq | fifo_AF);
assign av_irq = ipen_AE | ipen_AF;
assign activity = t_pause | t_ena;
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
pause_irq <= 1'b0;
else // only if fifo is not empty...
if (t_pause & ~fifo_EF)
pause_irq <= 1'b1;
else if (read_0)
pause_irq <= 1'b0;
end
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
begin
r_val <= 1'b0;
t_dav <= 1'b1;
end
else
begin
r_val <= r_ena & ~wfifo_empty;
t_dav <= ~rfifo_full;
end
end
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
begin
fifo_AE <= 1'b0;
fifo_AF <= 1'b0;
fifo_wr <= 1'b0;
rvalid <= 1'b0;
read_0 <= 1'b0;
ien_AE <= 1'b0;
ien_AF <= 1'b0;
ac <= 1'b0;
woverflow <= 1'b0;
av_waitrequest <= 1'b1;
end
else
begin
fifo_AE <= {fifo_FF,wfifo_used} <= 8;
fifo_AF <= (7'h40 - {rfifo_full,rfifo_used}) <= 8;
fifo_wr <= 1'b0;
read_0 <= 1'b0;
av_waitrequest <= ~(av_chipselect & (~av_write_n | ~av_read_n) & av_waitrequest);
if (activity)
ac <= 1'b1;
// write
if (av_chipselect & ~av_write_n & av_waitrequest)
// addr 1 is control; addr 0 is data
if (av_address)
begin
ien_AF <= av_writedata[0];
ien_AE <= av_writedata[1];
if (av_writedata[10] & ~activity)
ac <= 1'b0;
end
else
begin
fifo_wr <= ~fifo_FF;
woverflow <= fifo_FF;
end
// read
if (av_chipselect & ~av_read_n & av_waitrequest)
begin
// addr 1 is interrupt; addr 0 is data
if (~av_address)
rvalid <= ~fifo_EF;
read_0 <= ~av_address;
end
end
end
assign fifo_wdata = av_writedata[7 : 0];
assign fifo_rd = (av_chipselect & ~av_read_n & av_waitrequest & ~av_address) ? ~fifo_EF : 1'b0;
assign av_readdata = read_0 ? { {9{1'b0}},rfifo_full,rfifo_used,rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,fifo_rdata } : { {9{1'b0}},(7'h40 - {fifo_FF,wfifo_used}),rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,{6{1'b0}},ien_AE,ien_AF };
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
readyfordata <= 0;
else
readyfordata <= ~fifo_FF;
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
// Tie off Atlantic Interface signals not used for simulation
always @(posedge clk)
begin
sim_t_pause <= 1'b0;
sim_t_ena <= 1'b0;
sim_t_dat <= t_dav ? r_dat : {8{r_val}};
sim_r_ena <= 1'b0;
end
assign r_ena = sim_r_ena;
assign t_ena = sim_t_ena;
assign t_dat = sim_t_dat;
assign t_pause = sim_t_pause;
always @(fifo_EF)
begin
dataavailable = ~fifo_EF;
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// alt_jtag_atlantic soc_system_jtag_uart_alt_jtag_atlantic
// (
// .clk (clk),
// .r_dat (r_dat),
// .r_ena (r_ena),
// .r_val (r_val),
// .rst_n (rst_n),
// .t_dat (t_dat),
// .t_dav (t_dav),
// .t_ena (t_ena),
// .t_pause (t_pause)
// );
//
// defparam soc_system_jtag_uart_alt_jtag_atlantic.INSTANCE_ID = 0,
// soc_system_jtag_uart_alt_jtag_atlantic.LOG2_RXFIFO_DEPTH = 6,
// soc_system_jtag_uart_alt_jtag_atlantic.LOG2_TXFIFO_DEPTH = 6,
// soc_system_jtag_uart_alt_jtag_atlantic.SLD_AUTO_INSTANCE_INDEX = "YES";
//
// always @(posedge clk or negedge rst_n)
// begin
// if (rst_n == 0)
// dataavailable <= 0;
// else
// dataavailable <= ~fifo_EF;
// end
//
//
//synthesis read_comments_as_HDL off
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2004 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg signed [64+15:0] data;
integer i;
integer b;
reg signed [64+15:0] srs;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==2) begin
data <= 80'h0;
data[75] <= 1'b1;
data[10] <= 1'b1;
end
if (cyc==3) begin
for (i=0; i<85; i=i+1) begin
srs = data>>>i;
//$write (" %x >>> %d == %x\n",data,i,srs);
for (b=0; b<80; b=b+1) begin
if (srs[b] != (b==(75-i) || b==(10-i))) $stop;
end
end
end
if (cyc==10) begin
data <= 80'h0;
data[79] <= 1'b1;
data[10] <= 1'b1;
end
if (cyc==12) begin
for (i=0; i<85; i=i+1) begin
srs = data>>>i;
//$write (" %x >>> %d == %x\n",data,i,srs);
for (b=0; b<80; b=b+1) begin
if (srs[b] != (b>=(79-i) || b==(10-i))) $stop;
end
end
end
if (cyc==20) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// JPEG Quantization & Rounding Core ////
//// ////
//// Author: Richard Herveille ////
//// [email protected] ////
//// www.asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Richard Herveille ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: jpeg_qnr.v,v 1.3 2002/10/31 12:52:55 rherveille Exp $
//
// $Date: 2002/10/31 12:52:55 $
// $Revision: 1.3 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: jpeg_qnr.v,v $
// Revision 1.3 2002/10/31 12:52:55 rherveille
// *** empty log message ***
//
// Revision 1.2 2002/10/23 09:07:03 rherveille
// Improved many files.
// Fixed some bugs in Run-Length-Encoder.
// Removed dependency on ud_cnt and ro_cnt.
// Started (Motion)JPEG hardware encoder project.
//
//synopsys translate_off
//`include "timescale.v"
//synopsys translate_on
module jpeg_qnr(clk, ena, rst, dstrb, din, qnt_val, qnt_cnt, dout, douten);
//
// parameters
//
parameter d_width = 12;
parameter z_width = 2 * d_width;
//
// inputs & outputs
//
input clk; // system clock
input ena; // clock enable
input rst; // asynchronous active low reset
input dstrb; // present dstrb 1clk cycle before din
input [d_width-1:0] din; // data input
input [ 7:0] qnt_val; // quantization value
output [ 5:0] qnt_cnt; // sample number (get quantization value qnt_cnt)
output [10:0] dout; // data output
output douten;
//
// variables
//
wire [z_width-1:0] iz; // intermediate divident value
wire [d_width-1:0] id; // intermediate dividor value
wire [d_width :0] iq; // intermediate result divider
reg [d_width :0] rq; // rounded q-value
reg [d_width+3:0] dep;// data enable pipeline
// generate sample counter
reg [5:0] qnt_cnt;
wire dcnt = &qnt_cnt;
always @(posedge clk or negedge rst)
if (~rst)
qnt_cnt <= #1 6'h0;
else if (dstrb)
qnt_cnt <= #1 6'h0;
else if (ena)
qnt_cnt <= #1 qnt_cnt + 6'h1;
// generate intermediate dividor/divident values
assign id = { {(d_width - 8){1'b0}}, qnt_val};
assign iz = { {(z_width - d_width){din[d_width-1]}}, din};
// hookup division unit
div_su #(z_width)
divider (
.clk(clk),
.ena(ena),
.z(iz),
.d(id),
.q(iq),
.s(),
.div0(),
.ovf()
);
// round result to the nearest integer
always @(posedge clk)
if (ena)
if (iq[0])
if (iq[d_width])
rq <= #1 iq - 1'h1;
else
rq <= #1 iq + 1'h1;
else
rq <= #1 iq;
// assign dout signal
assign dout = rq[d_width -1: d_width-11];
// generate data-out enable signal
// This is a pipeline, data is not dependant on sample-count
integer n;
always @(posedge clk or negedge rst)
if (!rst)
dep <= #1 0;
else if(ena)
begin
dep[0] <= #1 dstrb;
for (n=1; n <= d_width +3; n = n +1)
dep[n] <= #1 dep[n-1];
end
assign douten = dep[d_width +3];
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O311AI_BEHAVIORAL_V
`define SKY130_FD_SC_LP__O311AI_BEHAVIORAL_V
/**
* o311ai: 3-input OR into 3-input NAND.
*
* Y = !((A1 | A2 | A3) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__o311ai (
Y ,
A1,
A2,
A3,
B1,
C1
);
// Module ports
output Y ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
nand nand0 (nand0_out_Y, C1, or0_out, B1);
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__O311AI_BEHAVIORAL_V |
// megafunction wizard: %ALTSQRT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: ALTSQRT
// ============================================================
// File Name: sqrt_43.v
// Megafunction Name(s):
// ALTSQRT
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.4 Build 182 03/12/2014 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module sqrt_43 (
clk,
ena,
radical,
q,
remainder);
input clk;
input ena;
input [42:0] radical;
output [21:0] q;
output [22:0] remainder;
wire [21:0] sub_wire0;
wire [22:0] sub_wire1;
wire [21:0] q = sub_wire0[21:0];
wire [22:0] remainder = sub_wire1[22:0];
altsqrt ALTSQRT_component (
.clk (clk),
.ena (ena),
.radical (radical),
.q (sub_wire0),
.remainder (sub_wire1)
// synopsys translate_off
,
.aclr ()
// synopsys translate_on
);
defparam
ALTSQRT_component.pipeline = 5,
ALTSQRT_component.q_port_width = 22,
ALTSQRT_component.r_port_width = 23,
ALTSQRT_component.width = 43;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: PIPELINE NUMERIC "5"
// Retrieval info: CONSTANT: Q_PORT_WIDTH NUMERIC "22"
// Retrieval info: CONSTANT: R_PORT_WIDTH NUMERIC "23"
// Retrieval info: CONSTANT: WIDTH NUMERIC "43"
// Retrieval info: USED_PORT: clk 0 0 0 0 INPUT NODEFVAL "clk"
// Retrieval info: USED_PORT: ena 0 0 0 0 INPUT NODEFVAL "ena"
// Retrieval info: USED_PORT: q 0 0 22 0 OUTPUT NODEFVAL "q[21..0]"
// Retrieval info: USED_PORT: radical 0 0 43 0 INPUT NODEFVAL "radical[42..0]"
// Retrieval info: USED_PORT: remainder 0 0 23 0 OUTPUT NODEFVAL "remainder[22..0]"
// Retrieval info: CONNECT: @clk 0 0 0 0 clk 0 0 0 0
// Retrieval info: CONNECT: @ena 0 0 0 0 ena 0 0 0 0
// Retrieval info: CONNECT: @radical 0 0 43 0 radical 0 0 43 0
// Retrieval info: CONNECT: q 0 0 22 0 @q 0 0 22 0
// Retrieval info: CONNECT: remainder 0 0 23 0 @remainder 0 0 23 0
// Retrieval info: GEN_FILE: TYPE_NORMAL sqrt_43.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sqrt_43.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sqrt_43.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sqrt_43.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sqrt_43_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sqrt_43_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
//
// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
//
//
//
//
// Ports:
// Name I/O size props
// mv_read O 32
// mav_write O 32
// CLK I 1 clock
// RST_N I 1 reset
// mav_write_misa I 28
// mav_write_wordxl I 32
// EN_reset I 1
// EN_mav_write I 1
//
// Combinational paths from inputs to outputs:
// (mav_write_misa, mav_write_wordxl) -> mav_write
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkCSR_MIE(CLK,
RST_N,
EN_reset,
mv_read,
mav_write_misa,
mav_write_wordxl,
EN_mav_write,
mav_write);
input CLK;
input RST_N;
// action method reset
input EN_reset;
// value method mv_read
output [31 : 0] mv_read;
// actionvalue method mav_write
input [27 : 0] mav_write_misa;
input [31 : 0] mav_write_wordxl;
input EN_mav_write;
output [31 : 0] mav_write;
// signals for module outputs
wire [31 : 0] mav_write, mv_read;
// register rg_mie
reg [11 : 0] rg_mie;
wire [11 : 0] rg_mie$D_IN;
wire rg_mie$EN;
// rule scheduling signals
wire CAN_FIRE_mav_write,
CAN_FIRE_reset,
WILL_FIRE_mav_write,
WILL_FIRE_reset;
// remaining internal signals
wire [11 : 0] mie__h88;
wire seie__h119, ssie__h113, stie__h116, ueie__h118, usie__h112, utie__h115;
// action method reset
assign CAN_FIRE_reset = 1'd1 ;
assign WILL_FIRE_reset = EN_reset ;
// value method mv_read
assign mv_read = { 20'd0, rg_mie } ;
// actionvalue method mav_write
assign mav_write = { 20'd0, mie__h88 } ;
assign CAN_FIRE_mav_write = 1'd1 ;
assign WILL_FIRE_mav_write = EN_mav_write ;
// register rg_mie
assign rg_mie$D_IN = EN_mav_write ? mie__h88 : 12'd0 ;
assign rg_mie$EN = EN_mav_write || EN_reset ;
// remaining internal signals
assign mie__h88 =
{ mav_write_wordxl[11],
1'b0,
seie__h119,
ueie__h118,
mav_write_wordxl[7],
1'b0,
stie__h116,
utie__h115,
mav_write_wordxl[3],
1'b0,
ssie__h113,
usie__h112 } ;
assign seie__h119 = mav_write_misa[18] && mav_write_wordxl[9] ;
assign ssie__h113 = mav_write_misa[18] && mav_write_wordxl[1] ;
assign stie__h116 = mav_write_misa[18] && mav_write_wordxl[5] ;
assign ueie__h118 = mav_write_misa[13] && mav_write_wordxl[8] ;
assign usie__h112 = mav_write_misa[13] && mav_write_wordxl[0] ;
assign utie__h115 = mav_write_misa[13] && mav_write_wordxl[4] ;
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
rg_mie <= `BSV_ASSIGNMENT_DELAY 12'd0;
end
else
begin
if (rg_mie$EN) rg_mie <= `BSV_ASSIGNMENT_DELAY rg_mie$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
rg_mie = 12'hAAA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
endmodule // mkCSR_MIE
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INPUTISO1N_TB_V
`define SKY130_FD_SC_LP__INPUTISO1N_TB_V
/**
* inputiso1n: Input isolation, inverted sleep.
*
* X = (A & SLEEP_B)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__inputiso1n.v"
module top();
// Inputs are registered
reg A;
reg SLEEP_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
SLEEP_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 SLEEP_B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 SLEEP_B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 SLEEP_B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 SLEEP_B = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 SLEEP_B = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_lp__inputiso1n dut (.A(A), .SLEEP_B(SLEEP_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__INPUTISO1N_TB_V
|
//-----------------------------------------------------------------------------
// ISO14443-A support for the Proxmark III
// Gerhard de Koning Gans, April 2008
//-----------------------------------------------------------------------------
module hi_iso14443a(
pck0, ck_1356meg, ck_1356megb,
pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
adc_d, adc_clk,
ssp_frame, ssp_din, ssp_dout, ssp_clk,
cross_hi, cross_lo,
dbg,
mod_type
);
input pck0, ck_1356meg, ck_1356megb;
output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
input [7:0] adc_d;
output adc_clk;
input ssp_dout;
output ssp_frame, ssp_din, ssp_clk;
input cross_hi, cross_lo;
output dbg;
input [2:0] mod_type;
reg ssp_clk;
reg ssp_frame;
reg fc_div_2;
always @(posedge ck_1356meg)
fc_div_2 = ~fc_div_2;
wire adc_clk;
assign adc_clk = ck_1356meg;
reg after_hysteresis, after_hysteresis_prev1, after_hysteresis_prev2, after_hysteresis_prev3;
reg [11:0] has_been_low_for;
reg [8:0] saw_deep_modulation;
reg [2:0] deep_counter;
reg deep_modulation;
always @(negedge adc_clk)
begin
if(& adc_d[7:6]) after_hysteresis <= 1'b1;
else if(~(| adc_d[7:4])) after_hysteresis <= 1'b0;
if(~(| adc_d[7:0]))
begin
if(deep_counter == 3'd7)
begin
deep_modulation <= 1'b1;
saw_deep_modulation <= 8'd0;
end
else
deep_counter <= deep_counter + 1;
end
else
begin
deep_counter <= 3'd0;
if(saw_deep_modulation == 8'd255)
deep_modulation <= 1'b0;
else
saw_deep_modulation <= saw_deep_modulation + 1;
end
if(after_hysteresis)
begin
has_been_low_for <= 7'b0;
end
else
begin
if(has_been_low_for == 12'd4095)
begin
has_been_low_for <= 12'd0;
after_hysteresis <= 1'b1;
end
else
has_been_low_for <= has_been_low_for + 1;
end
end
// Report every 4 subcarrier cycles
// 64 periods of carrier frequency => 6-bit counter [negedge_cnt]
reg [5:0] negedge_cnt;
reg bit1, bit2, bit3;
reg [3:0] count_ones;
reg [3:0] count_zeros;
wire [7:0] avg;
reg [7:0] lavg;
reg signed [12:0] step1;
reg signed [12:0] step2;
reg [7:0] stepsize;
reg curbit;
reg [12:0] average;
wire signed [9:0] dif;
// A register to send the results to the arm
reg signed [7:0] to_arm;
assign avg[7:0] = average[11:4];
assign dif = lavg - avg;
reg bit_to_arm;
reg fdt_indicator, fdt_elapsed;
reg [10:0] fdt_counter;
reg [47:0] mod_sig_buf;
wire mod_sig_buf_empty;
reg [5:0] mod_sig_ptr;
reg [3:0] mod_sig_flip;
reg mod_sig, mod_sig_coil;
reg temp_buffer_reset;
reg sendbit;
assign mod_sig_buf_empty = ~(|mod_sig_buf[47:0]);
reg [2:0] ssp_frame_counter;
// ADC data appears on the rising edge, so sample it on the falling edge
always @(negedge adc_clk)
begin
// last bit = 0 then fdt = 1172, in case of 0x26 (7-bit command, LSB first!)
// last bit = 1 then fdt = 1236, in case of 0x52 (7-bit command, LSB first!)
if(fdt_counter == 11'd740) fdt_indicator = 1'b1;
if(fdt_counter == 11'd1148)
begin
if(fdt_elapsed)
begin
if(negedge_cnt[3:0] == mod_sig_flip[3:0]) mod_sig_coil <= mod_sig;
end
else
begin
mod_sig_flip[3:0] <= negedge_cnt[3:0];
mod_sig_coil <= mod_sig;
fdt_elapsed = 1'b1;
fdt_indicator = 1'b0;
if(~(| mod_sig_ptr[5:0])) mod_sig_ptr <= 6'b001001;
else temp_buffer_reset = 1'b1; // fix position of the buffer pointer
end
end
else
begin
fdt_counter <= fdt_counter + 1;
end
if(& negedge_cnt[3:0])
begin
// When there is a dip in the signal and not in reader mode
if(~after_hysteresis && mod_sig_buf_empty && ~((mod_type == 3'b100) || (mod_type == 3'b011) || (mod_type == 3'b010))) // last condition to prevent reset
begin
fdt_counter <= 11'd0;
fdt_elapsed = 1'b0;
fdt_indicator = 1'b0;
temp_buffer_reset = 1'b0;
mod_sig_ptr <= 6'b000000;
end
lavg <= avg;
if(stepsize<16) stepsize = 8'd16;
if(dif>0)
begin
step1 = dif*3;
step2 = stepsize*2; // 3:2
if(step1>step2)
begin
curbit = 1'b0;
stepsize = dif;
end
end
else
begin
step1 = dif*3;
step1 = -step1;
step2 = stepsize*2;
if(step1>step2)
begin
curbit = 1'b1;
stepsize = -dif;
end
end
if(curbit)
begin
count_zeros <= 4'd0;
if(& count_ones[3:2])
begin
curbit = 1'b0; // suppressed signal
stepsize = 8'd24; // just a fine number
end
else
begin
count_ones <= count_ones + 1;
end
end
else
begin
count_ones <= 4'd0;
if(& count_zeros[3:0])
begin
stepsize = 8'd24;
end
else
begin
count_zeros <= count_zeros + 1;
end
end
// What do we communicate to the ARM
if(mod_type == 3'b001) sendbit = after_hysteresis;
else if(mod_type == 3'b010)
begin
if(fdt_counter > 11'd772) sendbit = mod_sig_coil;
else sendbit = fdt_indicator;
end
else if(mod_type == 3'b011) sendbit = curbit;
else sendbit = 1'b0;
end
if(~(| negedge_cnt[3:0])) average <= adc_d;
else average <= average + adc_d;
if(negedge_cnt == 7'd63)
begin
if(deep_modulation)
begin
to_arm <= {after_hysteresis_prev1,after_hysteresis_prev2,after_hysteresis_prev3,after_hysteresis,1'b0,1'b0,1'b0,1'b0};
end
else
begin
to_arm <= {after_hysteresis_prev1,after_hysteresis_prev2,after_hysteresis_prev3,after_hysteresis,bit1,bit2,bit3,curbit};
end
negedge_cnt <= 0;
end
else
begin
negedge_cnt <= negedge_cnt + 1;
end
if(negedge_cnt == 6'd15)
begin
after_hysteresis_prev1 <= after_hysteresis;
bit1 <= curbit;
end
if(negedge_cnt == 6'd31)
begin
after_hysteresis_prev2 <= after_hysteresis;
bit2 <= curbit;
end
if(negedge_cnt == 6'd47)
begin
after_hysteresis_prev3 <= after_hysteresis;
bit3 <= curbit;
end
if(mod_type != 3'b000)
begin
if(negedge_cnt[3:0] == 4'b1000)
begin
// The modulation signal of the tag
mod_sig_buf[47:0] <= {mod_sig_buf[46:1], ssp_dout, 1'b0};
if((ssp_dout || (| mod_sig_ptr[5:0])) && ~fdt_elapsed)
if(mod_sig_ptr == 6'b101110)
begin
mod_sig_ptr <= 6'b000000;
end
else mod_sig_ptr <= mod_sig_ptr + 1;
else if(fdt_elapsed && ~temp_buffer_reset)
begin
if(ssp_dout) temp_buffer_reset = 1'b1;
if(mod_sig_ptr == 6'b000010) mod_sig_ptr <= 6'b001001;
else mod_sig_ptr <= mod_sig_ptr - 1;
end
else
begin
// side effect: when ptr = 1 it will cancel the first 1 of every block of ones
if(~mod_sig_buf[mod_sig_ptr-1] && ~mod_sig_buf[mod_sig_ptr+1]) mod_sig = 1'b0;
else mod_sig = mod_sig_buf[mod_sig_ptr] & fdt_elapsed; // & fdt_elapsed was for direct relay to oe4
end
end
end
// SSP Clock and data
if(mod_type == 3'b000)
begin
if(negedge_cnt[2:0] == 3'b100)
ssp_clk <= 1'b0;
if(negedge_cnt[2:0] == 3'b000)
begin
ssp_clk <= 1'b1;
// Don't shift if we just loaded new data, obviously.
if(negedge_cnt != 7'd0)
begin
to_arm[7:1] <= to_arm[6:0];
end
end
if(negedge_cnt[5:4] == 2'b00)
ssp_frame = 1'b1;
else
ssp_frame = 1'b0;
bit_to_arm = to_arm[7];
end
else
begin
if(negedge_cnt[3:0] == 4'b1000) ssp_clk <= 1'b0;
if(negedge_cnt[3:0] == 4'b0111)
begin
if(ssp_frame_counter == 3'd7) ssp_frame_counter <= 3'd0;
else ssp_frame_counter <= ssp_frame_counter + 1;
end
if(negedge_cnt[3:0] == 4'b0000)
begin
ssp_clk <= 1'b1;
end
ssp_frame = (ssp_frame_counter == 3'd7);
bit_to_arm = sendbit;
end
end
assign ssp_din = bit_to_arm;
// Modulating carrier frequency is fc/16
wire modulating_carrier;
assign modulating_carrier = (mod_sig_coil & negedge_cnt[3] & (mod_type == 3'b010));
assign pwr_hi = (ck_1356megb & (((mod_type == 3'b100) & ~mod_sig_coil) || (mod_type == 3'b011)));
// This one is all LF, so doesn't matter
//assign pwr_oe2 = modulating_carrier;
assign pwr_oe2 = 1'b0;
// Toggle only one of these, since we are already producing much deeper
// modulation than a real tag would.
//assign pwr_oe1 = modulating_carrier;
assign pwr_oe1 = 1'b0;
assign pwr_oe4 = modulating_carrier;
//assign pwr_oe4 = 1'b0;
// This one is always on, so that we can watch the carrier.
//assign pwr_oe3 = modulating_carrier;
assign pwr_oe3 = 1'b0;
assign dbg = negedge_cnt[3];
// Unused.
assign pwr_lo = 1'b0;
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module logicblock_counter(clock, resetn, i_start, i_size,
o_dataout, o_dataout_valid, i_dataout_stall, i_counter_reset);
parameter DATA_WIDTH = 32;
input clock, resetn;
input i_start;
input [DATA_WIDTH-1:0] i_size;
output [DATA_WIDTH-1:0] o_dataout;
output o_dataout_valid;
input i_dataout_stall;
input i_counter_reset;
reg [DATA_WIDTH-1:0] counter;
always @(posedge clock or negedge resetn)
begin
if (~resetn)
begin
counter <= 32'h00000000;
end
else
begin
if (i_counter_reset)
begin
counter <= {DATA_WIDTH{1'b0}};
end
else if (i_start && ~i_dataout_stall && counter < i_size)
begin
counter <= counter + 1;
end
end
end
assign o_dataout = counter;
assign o_dataout_valid = i_start && !i_counter_reset && (counter < i_size);
endmodule
|
//
// Author: Pawel Szostek ([email protected])
// Date: 01.08.2011
`timescale 1ns/1ps
module stimulus (output reg [7:0] a);
parameter S = 20000;
int unsigned j,i;
initial begin
for(i=0; i<S; i=i+1) begin
#10;
a[7] <= inject();
a[6] <= inject();
a[5] <= inject();
a[4] <= inject();
a[3] <= inject();
a[2] <= inject();
a[1] <= inject();
a[0] <= inject();
end
end
function inject();
reg ret;
reg unsigned [3:0] temp;
temp[3:0] = $random % 16;
begin
if(temp >= 10)
ret = 1'b1;
else if(temp >= 4)
ret = 1'b0;
else if(temp >= 2)
ret = 1'bx;
else
ret = 1'b0;
inject = ret;
end
endfunction
endmodule
module main;
wire [7:0] i, o;
wire [0:7] o_vl;
dummy dummy_vhdl(o, i);
stimulus stim(i);
assign o_vl = i;
always @(i) begin
#1;
if(o !== o_vl) begin
$display("OUTPUT: ", o);
$display("INPUT: ", i);
$display("CORRECT: ", o_vl);
end
end
initial begin
#120000;
$display("PASSED");
$finish;
end
endmodule
|
/* verilator lint_off UNDRIVEN */
/* verilator lint_off UNUSED */
module axi_rom (
clk,rstn,
axi_ARVALID,
axi_ARREADY,
axi_AR,
axi_ARBURST,
axi_ARLEN,
axi_R,
axi_RVALID,
axi_RREADY,
axi_RLAST
);
input clk,rstn;
input axi_ARVALID,axi_RREADY;
output reg axi_ARREADY,axi_RVALID;
output reg axi_RLAST;
input [7:0] axi_ARLEN;
input [1:0] axi_ARBURST;
output [31:0] axi_R;
input [31:0] axi_AR;
reg [7:0] Mem [1023:0];
reg [31:0] Qint;
wire [9:0] A0;
reg [9:0] A1;
reg read_transaction;
reg burst_transaction;
reg [7:0] burstn;
reg [7:0] len;
assign A0 = {axi_AR[9:2],2'b00};
initial
begin
$readmemh("boot.mem" , Mem , 0);
end
// Read process
always @(posedge clk) Qint[ 7: 0] <= Mem[A1+0];
always @(posedge clk) Qint[15: 8] <= Mem[A1+1];
always @(posedge clk) Qint[23:16] <= Mem[A1+2];
always @(posedge clk) Qint[31:24] <= Mem[A1+3];
assign axi_R = Qint;
// control
always @(posedge clk or negedge rstn)
if (~rstn)
begin
axi_ARREADY <=0;
axi_RVALID <=0;
read_transaction <= 0;
burst_transaction <= 0;
burstn <= 0;
axi_RLAST <= 0;
end
else
begin
if (axi_ARVALID & ~read_transaction &~burst_transaction)
begin
axi_ARREADY <=1;
A1 <= A0;
if ((axi_ARLEN != 8'h0) && (axi_ARBURST == 2'b01)) begin len <= axi_ARLEN; burst_transaction <= 1; end else read_transaction <= 1 ;
end
else
begin
axi_ARREADY <=0;
end
if (axi_RREADY & read_transaction)
begin
axi_RVALID <= 1;
axi_RLAST <= 1;
read_transaction <=0;
end
else
if (axi_RREADY & burst_transaction)
begin
axi_RVALID <=1;
if (burstn == len) begin axi_RLAST <= 1; burst_transaction <=0; end
burstn <= burstn +1;
A1 <= A1 + 4;
end
else
begin
axi_RVALID <=0; axi_RLAST <= 0; burstn <=0;
end
end
endmodule
|
//Cells still in this file have INCOMPLETE simulation models, need to finish them
module GP_DCMP(input[7:0] INP, input[7:0] INN, input CLK, input PWRDN, output reg GREATER, output reg EQUAL);
parameter PWRDN_SYNC = 1'b0;
parameter CLK_EDGE = "RISING";
parameter GREATER_OR_EQUAL = 1'b0;
//TODO implement power-down mode
initial GREATER = 0;
initial EQUAL = 0;
wire clk_minv = (CLK_EDGE == "RISING") ? CLK : ~CLK;
always @(posedge clk_minv) begin
if(GREATER_OR_EQUAL)
GREATER <= (INP >= INN);
else
GREATER <= (INP > INN);
EQUAL <= (INP == INN);
end
endmodule
module GP_EDGEDET(input IN, output reg OUT);
parameter EDGE_DIRECTION = "RISING";
parameter DELAY_STEPS = 1;
parameter GLITCH_FILTER = 0;
//not implemented for simulation
endmodule
module GP_RCOSC(input PWRDN, output reg CLKOUT_HARDIP, output reg CLKOUT_FABRIC);
parameter PWRDN_EN = 0;
parameter AUTO_PWRDN = 0;
parameter HARDIP_DIV = 1;
parameter FABRIC_DIV = 1;
parameter OSC_FREQ = "25k";
initial CLKOUT_HARDIP = 0;
initial CLKOUT_FABRIC = 0;
//output dividers not implemented for simulation
//auto powerdown not implemented for simulation
always begin
if(PWRDN) begin
CLKOUT_HARDIP = 0;
CLKOUT_FABRIC = 0;
end
else begin
if(OSC_FREQ == "25k") begin
//half period of 25 kHz
#20000;
end
else begin
//half period of 2 MHz
#250;
end
CLKOUT_HARDIP = ~CLKOUT_HARDIP;
CLKOUT_FABRIC = ~CLKOUT_FABRIC;
end
end
endmodule
module GP_RINGOSC(input PWRDN, output reg CLKOUT_HARDIP, output reg CLKOUT_FABRIC);
parameter PWRDN_EN = 0;
parameter AUTO_PWRDN = 0;
parameter HARDIP_DIV = 1;
parameter FABRIC_DIV = 1;
initial CLKOUT_HARDIP = 0;
initial CLKOUT_FABRIC = 0;
//output dividers not implemented for simulation
//auto powerdown not implemented for simulation
always begin
if(PWRDN) begin
CLKOUT_HARDIP = 0;
CLKOUT_FABRIC = 0;
end
else begin
//half period of 27 MHz
#18.518;
CLKOUT_HARDIP = ~CLKOUT_HARDIP;
CLKOUT_FABRIC = ~CLKOUT_FABRIC;
end
end
endmodule
module GP_SPI(
input SCK,
inout SDAT,
input CSN,
input[7:0] TXD_HIGH,
input[7:0] TXD_LOW,
output reg[7:0] RXD_HIGH,
output reg[7:0] RXD_LOW,
output reg INT);
initial RXD_HIGH = 0;
initial RXD_LOW = 0;
initial INT = 0;
parameter DATA_WIDTH = 8; //byte or word width
parameter SPI_CPHA = 0; //SPI clock phase
parameter SPI_CPOL = 0; //SPI clock polarity
parameter DIRECTION = "INPUT"; //SPI data direction (either input to chip or output to host)
//parallel output to fabric not yet implemented
//TODO: write sim model
//TODO: SPI SDIO control... can we use ADC output while SPI is input??
//TODO: clock sync
endmodule
//keep constraint needed to prevent optimization since we have no outputs
(* keep *)
module GP_SYSRESET(input RST);
parameter RESET_MODE = "EDGE";
parameter EDGE_SPEED = 4;
//cannot simulate whole system reset
endmodule
|
/*
* These source files contain a hardware description of a network
* automatically generated by CONNECT (CONfigurable NEtwork Creation Tool).
*
* This product includes a hardware design developed by Carnegie Mellon
* University.
*
* Copyright (c) 2012 by Michael K. Papamichael, Carnegie Mellon University
*
* For more information, see the CONNECT project website at:
* http://www.ece.cmu.edu/~mpapamic/connect
*
* This design is provided for internal, non-commercial research use only,
* cannot be used for, or in support of, goods or services, and is not for
* redistribution, with or without modifications.
*
* You may not use the name "Carnegie Mellon University" or derivations
* thereof to endorse or promote products derived from this software.
*
* THE SOFTWARE IS PROVIDED "AS-IS" WITHOUT ANY WARRANTY OF ANY KIND, EITHER
* EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO ANY WARRANTY
* THAT THE SOFTWARE WILL CONFORM TO SPECIFICATIONS OR BE ERROR-FREE AND ANY
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* TITLE, OR NON-INFRINGEMENT. IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY
* BE LIABLE FOR ANY DAMAGES, INCLUDING BUT NOT LIMITED TO DIRECT, INDIRECT,
* SPECIAL OR CONSEQUENTIAL DAMAGES, ARISING OUT OF, RESULTING FROM, OR IN
* ANY WAY CONNECTED WITH THIS SOFTWARE (WHETHER OR NOT BASED UPON WARRANTY,
* CONTRACT, TORT OR OTHERWISE).
*
*/
//
// Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17)
//
// On Mon Sep 5 14:58:21 EDT 2016
//
// Method conflict info:
// Method: enq
// Conflict-free: deq, notEmpty, notFull
// Conflicts: enq
//
// Method: deq
// Conflict-free: enq, notEmpty, notFull
// Conflicts: deq
//
// Method: notEmpty
// Conflict-free: enq, deq, notEmpty, notFull
//
// Method: notFull
// Conflict-free: enq, deq, notEmpty, notFull
//
//
// Ports:
// Name I/O size props
// deq O 132
// notEmpty O 1 reg
// notFull O 1 reg
// CLK I 1 clock
// RST_N I 1 reset
// enq_data_in I 132
// EN_enq I 1
// EN_deq I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
module mkInputQueue(CLK,
RST_N,
enq_data_in,
EN_enq,
EN_deq,
deq,
notEmpty,
notFull);
input CLK;
input RST_N;
// action method enq
input [131 : 0] enq_data_in;
input EN_enq;
// actionvalue method deq
input EN_deq;
output [131 : 0] deq;
// value method notEmpty
output notEmpty;
// value method notFull
output notFull;
// signals for module outputs
wire [131 : 0] deq;
wire notEmpty, notFull;
// inlined wires
wire [2 : 0] inputQueue_ifc_mf_ifc_new_head$wget,
inputQueue_ifc_mf_ifc_new_tail$wget;
// register inputQueue_ifc_mf_ifc_heads
reg [2 : 0] inputQueue_ifc_mf_ifc_heads;
wire [2 : 0] inputQueue_ifc_mf_ifc_heads$D_IN;
wire inputQueue_ifc_mf_ifc_heads$EN;
// register inputQueue_ifc_mf_ifc_not_empty
reg inputQueue_ifc_mf_ifc_not_empty;
wire inputQueue_ifc_mf_ifc_not_empty$D_IN,
inputQueue_ifc_mf_ifc_not_empty$EN;
// register inputQueue_ifc_mf_ifc_not_full
reg inputQueue_ifc_mf_ifc_not_full;
wire inputQueue_ifc_mf_ifc_not_full$D_IN, inputQueue_ifc_mf_ifc_not_full$EN;
// register inputQueue_ifc_mf_ifc_tails
reg [2 : 0] inputQueue_ifc_mf_ifc_tails;
wire [2 : 0] inputQueue_ifc_mf_ifc_tails$D_IN;
wire inputQueue_ifc_mf_ifc_tails$EN;
// ports of submodule inputQueue_ifc_mf_ifc_fifoMem
wire [131 : 0] inputQueue_ifc_mf_ifc_fifoMem$D_IN,
inputQueue_ifc_mf_ifc_fifoMem$D_OUT;
wire [2 : 0] inputQueue_ifc_mf_ifc_fifoMem$ADDR_IN,
inputQueue_ifc_mf_ifc_fifoMem$ADDR_OUT;
wire inputQueue_ifc_mf_ifc_fifoMem$WE;
// remaining internal signals
wire [2 : 0] x__h1895, x__h2274;
wire inputQueue_ifc_mf_ifc_rdFIFO_whas_AND_inputQue_ETC___d28,
inputQueue_ifc_mf_ifc_wrFIFO_whas_AND_inputQue_ETC___d20;
// actionvalue method deq
assign deq = inputQueue_ifc_mf_ifc_fifoMem$D_OUT ;
// value method notEmpty
assign notEmpty = inputQueue_ifc_mf_ifc_not_empty ;
// value method notFull
assign notFull = inputQueue_ifc_mf_ifc_not_full ;
// submodule inputQueue_ifc_mf_ifc_fifoMem
RegFile_1port #( /*data_width*/ 32'd132,
/*addr_width*/ 32'd3) inputQueue_ifc_mf_ifc_fifoMem(.CLK(CLK),
.rst_n(RST_N),
.ADDR_IN(inputQueue_ifc_mf_ifc_fifoMem$ADDR_IN),
.ADDR_OUT(inputQueue_ifc_mf_ifc_fifoMem$ADDR_OUT),
.D_IN(inputQueue_ifc_mf_ifc_fifoMem$D_IN),
.WE(inputQueue_ifc_mf_ifc_fifoMem$WE),
.D_OUT(inputQueue_ifc_mf_ifc_fifoMem$D_OUT));
// inlined wires
assign inputQueue_ifc_mf_ifc_new_tail$wget =
inputQueue_ifc_mf_ifc_tails + 3'd1 ;
assign inputQueue_ifc_mf_ifc_new_head$wget =
inputQueue_ifc_mf_ifc_heads + 3'd1 ;
// register inputQueue_ifc_mf_ifc_heads
assign inputQueue_ifc_mf_ifc_heads$D_IN = x__h2274 ;
assign inputQueue_ifc_mf_ifc_heads$EN = EN_deq ;
// register inputQueue_ifc_mf_ifc_not_empty
assign inputQueue_ifc_mf_ifc_not_empty$D_IN = EN_enq && !EN_deq ;
assign inputQueue_ifc_mf_ifc_not_empty$EN =
EN_enq && !EN_deq ||
inputQueue_ifc_mf_ifc_rdFIFO_whas_AND_inputQue_ETC___d28 ;
// register inputQueue_ifc_mf_ifc_not_full
assign inputQueue_ifc_mf_ifc_not_full$D_IN =
!inputQueue_ifc_mf_ifc_wrFIFO_whas_AND_inputQue_ETC___d20 ;
assign inputQueue_ifc_mf_ifc_not_full$EN =
inputQueue_ifc_mf_ifc_wrFIFO_whas_AND_inputQue_ETC___d20 ||
EN_deq && !EN_enq ;
// register inputQueue_ifc_mf_ifc_tails
assign inputQueue_ifc_mf_ifc_tails$D_IN = x__h1895 ;
assign inputQueue_ifc_mf_ifc_tails$EN = EN_enq ;
// submodule inputQueue_ifc_mf_ifc_fifoMem
assign inputQueue_ifc_mf_ifc_fifoMem$ADDR_IN = inputQueue_ifc_mf_ifc_tails ;
assign inputQueue_ifc_mf_ifc_fifoMem$ADDR_OUT =
inputQueue_ifc_mf_ifc_heads ;
assign inputQueue_ifc_mf_ifc_fifoMem$D_IN = enq_data_in ;
assign inputQueue_ifc_mf_ifc_fifoMem$WE = EN_enq ;
// remaining internal signals
assign inputQueue_ifc_mf_ifc_rdFIFO_whas_AND_inputQue_ETC___d28 =
EN_deq && !EN_enq && x__h2274 == inputQueue_ifc_mf_ifc_tails ;
assign inputQueue_ifc_mf_ifc_wrFIFO_whas_AND_inputQue_ETC___d20 =
EN_enq && !EN_deq && x__h1895 == inputQueue_ifc_mf_ifc_heads ;
assign x__h1895 = EN_enq ? inputQueue_ifc_mf_ifc_new_tail$wget : 3'd0 ;
assign x__h2274 = EN_deq ? inputQueue_ifc_mf_ifc_new_head$wget : 3'd0 ;
// handling of inlined registers
always@(posedge CLK)
begin
if (!RST_N)
begin
inputQueue_ifc_mf_ifc_heads <= `BSV_ASSIGNMENT_DELAY 3'd0;
inputQueue_ifc_mf_ifc_not_empty <= `BSV_ASSIGNMENT_DELAY 1'd0;
inputQueue_ifc_mf_ifc_not_full <= `BSV_ASSIGNMENT_DELAY 1'd1;
inputQueue_ifc_mf_ifc_tails <= `BSV_ASSIGNMENT_DELAY 3'd0;
end
else
begin
if (inputQueue_ifc_mf_ifc_heads$EN)
inputQueue_ifc_mf_ifc_heads <= `BSV_ASSIGNMENT_DELAY
inputQueue_ifc_mf_ifc_heads$D_IN;
if (inputQueue_ifc_mf_ifc_not_empty$EN)
inputQueue_ifc_mf_ifc_not_empty <= `BSV_ASSIGNMENT_DELAY
inputQueue_ifc_mf_ifc_not_empty$D_IN;
if (inputQueue_ifc_mf_ifc_not_full$EN)
inputQueue_ifc_mf_ifc_not_full <= `BSV_ASSIGNMENT_DELAY
inputQueue_ifc_mf_ifc_not_full$D_IN;
if (inputQueue_ifc_mf_ifc_tails$EN)
inputQueue_ifc_mf_ifc_tails <= `BSV_ASSIGNMENT_DELAY
inputQueue_ifc_mf_ifc_tails$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
inputQueue_ifc_mf_ifc_heads = 3'h2;
inputQueue_ifc_mf_ifc_not_empty = 1'h0;
inputQueue_ifc_mf_ifc_not_full = 1'h0;
inputQueue_ifc_mf_ifc_tails = 3'h2;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N) if (EN_enq && !inputQueue_ifc_mf_ifc_not_full) $write("");
if (RST_N) if (EN_enq && !inputQueue_ifc_mf_ifc_not_full) $write("");
if (RST_N)
if (EN_enq && !inputQueue_ifc_mf_ifc_not_full)
$display("Dynamic assertion failed: \"MultiFIFOMem.bsv\", line 156, column 38\nEnqueing to full FIFO in MultiFIFOMem!");
if (RST_N) if (EN_enq && !inputQueue_ifc_mf_ifc_not_full) $finish(32'd0);
if (RST_N) if (EN_enq) $write("");
if (RST_N)
if (EN_deq && !inputQueue_ifc_mf_ifc_not_empty)
$display("Dynamic assertion failed: \"MultiFIFOMem.bsv\", line 190, column 40\nDequeing from empty FIFO in MultiFIFOMem!");
if (RST_N) if (EN_deq && !inputQueue_ifc_mf_ifc_not_empty) $finish(32'd0);
if (RST_N) if (EN_deq) $write("");
if (RST_N)
if (inputQueue_ifc_mf_ifc_wrFIFO_whas_AND_inputQue_ETC___d20)
$write("");
if (RST_N)
if (inputQueue_ifc_mf_ifc_rdFIFO_whas_AND_inputQue_ETC___d28)
$write("");
end
// synopsys translate_on
endmodule // mkInputQueue
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFSBP_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__SDFSBP_PP_BLACKBOX_V
/**
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
* complementary outputs.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__sdfsbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFSBP_PP_BLACKBOX_V
|
// usb_ft232.v
`timescale 1 ns / 1 ps
module usb_ft232
(
input clk,
input reset,
// FT232 interface
output wr_n,
output rd_n,
output oe_n,
inout [7:0]data,
input txe_n,
input rxf_n,
output siwu_n,
// tx fifo interface
output tx_read,
input [15:0]tx_data,
input [1:0]tx_mask,
input tx_ready,
// rx fifo interface
output reg rx_write,
output reg [15:0]rx_data,
output reg rx_mask,
input rx_ready
);
// === transmitter ========================================================
wire tx_ena;
wire tx_wait;
wire tx_skip;
reg tx_upper;
wire tx_is_send = tx_ready && !tx_mask[0];
wire tx_is_16bit = tx_ready && tx_mask[1];
// tx_data -> data transfer; flow control with tx_ena & tx_wait
wire wr = !txe_n && tx_ready && tx_ena && !tx_is_send;
assign wr_n = !wr;
assign oe_n = !wr_n;
assign tx_read = (wr && !tx_wait) || tx_skip;
assign data = oe_n ? (tx_upper ? tx_data[15:8] : tx_data[7:0]) : 8'hzz;
assign tx_skip = tx_is_send;
// 16 bit transfer
always @(posedge clk or posedge reset)
begin
if (reset) tx_upper <= 0;
else if (wr) tx_upper = tx_is_16bit && !tx_upper;
end
assign tx_wait = tx_is_16bit && !tx_upper;
// send immediate
reg tx_si;
reg tx_siwu;
reg [4:0]send_delay;
always @(posedge clk or posedge reset)
begin
if (reset)
begin
tx_si <= 0;
tx_siwu <= 0;
send_delay <= 0;
end
else
begin
if (tx_is_send && !tx_si) tx_si <= 1;
if (tx_si && (send_delay == 0)) tx_siwu <= 1;
if (tx_si && (send_delay == 16))
begin
tx_si <= 0;
tx_siwu <= 0;
end
if (tx_si || !(send_delay == 5'd0)) send_delay = send_delay + 5'b1;
end
end
assign siwu_n = !tx_siwu;
// === receiver ===========================================================
wire rx_ena;
wire rx_rd = !rxf_n && rx_ready && rx_ena;
reg rx_upper;
always @(posedge clk or posedge reset)
begin
if (reset)
begin
rx_upper <= 0;
rx_mask <= 0;
rx_write <= 0;
rx_data <= 0;
end
else if (rx_ready)
begin
rx_upper <= !rx_upper && rx_rd;
rx_mask <= rx_upper && rx_rd;
rx_write <= rx_upper;
if (rx_rd && !rx_upper) rx_data[7:0] <= data;
if (rx_rd && rx_upper) rx_data[15:8] <= data;
end
end
assign rd_n = !rx_rd;
// === priority logic =====================================================
assign tx_ena = !tx_si;
assign rx_ena = !(tx_ready && !txe_n);
endmodule
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
(* altera_attribute = "-name ALLOW_SYNCH_CTRL_USAGE ON;-name AUTO_CLOCK_ENABLE_RECOGNITION ON" *)
module nios_mem_if_ddr2_emif_0_p0_flop_mem(
wr_reset_n,
wr_clk,
wr_en,
wr_addr,
wr_data,
rd_reset_n,
rd_clk,
rd_en,
rd_addr,
rd_data
);
parameter WRITE_MEM_DEPTH = "";
parameter WRITE_ADDR_WIDTH = "";
parameter WRITE_DATA_WIDTH = "";
parameter READ_MEM_DEPTH = "";
parameter READ_ADDR_WIDTH = "";
parameter READ_DATA_WIDTH = "";
input wr_reset_n;
input wr_clk;
input wr_en;
input [WRITE_ADDR_WIDTH-1:0] wr_addr;
input [WRITE_DATA_WIDTH-1:0] wr_data;
input rd_reset_n;
input rd_clk;
input rd_en;
input [READ_ADDR_WIDTH-1:0] rd_addr;
output [READ_DATA_WIDTH-1:0] rd_data;
wire [WRITE_DATA_WIDTH*WRITE_MEM_DEPTH-1:0] all_data;
wire [READ_DATA_WIDTH-1:0] mux_data_out;
// declare a memory with WRITE_MEM_DEPTH entries
// each entry contains a data size of WRITE_DATA_WIDTH
reg [WRITE_DATA_WIDTH-1:0] data_stored [0:WRITE_MEM_DEPTH-1] /* synthesis syn_preserve = 1 */;
reg [READ_DATA_WIDTH-1:0] rd_data;
generate
genvar entry;
for (entry=0; entry < WRITE_MEM_DEPTH; entry=entry+1)
begin: mem_location
assign all_data[(WRITE_DATA_WIDTH*(entry+1)-1) : (WRITE_DATA_WIDTH*entry)] = data_stored[entry];
always @(posedge wr_clk or negedge wr_reset_n)
begin
if (~wr_reset_n) begin
data_stored[entry] <= {WRITE_DATA_WIDTH{1'b0}};
end else begin
if (wr_en) begin
if (entry == wr_addr) begin
data_stored[entry] <= wr_data;
end
end
end
end
end
endgenerate
// mux to select the correct output data based on read address
lpm_mux uread_mux(
.sel (rd_addr),
.data (all_data),
.result (mux_data_out)
// synopsys translate_off
,
.aclr (),
.clken (),
.clock ()
// synopsys translate_on
);
defparam uread_mux.lpm_size = READ_MEM_DEPTH;
defparam uread_mux.lpm_type = "LPM_MUX";
defparam uread_mux.lpm_width = READ_DATA_WIDTH;
defparam uread_mux.lpm_widths = READ_ADDR_WIDTH;
always @(posedge rd_clk or negedge rd_reset_n)
begin
if (~rd_reset_n) begin
rd_data <= {READ_DATA_WIDTH{1'b0}};
end else begin
rd_data <= mux_data_out;
end
end
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9643 (
// adc interface (clk, data, over-range)
adc_clk_in_p,
adc_clk_in_n,
adc_data_in_p,
adc_data_in_n,
adc_or_in_p,
adc_or_in_n,
// master-slave interface
adc_start_out,
dma_start_out,
adc_start_in,
dma_start_in,
// delay interface
delay_clk,
// dma interface
adc_dvalid,
adc_ddata,
adc_overflow,
// axi interface
s_axi_aclk,
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_awready,
s_axi_wvalid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wready,
s_axi_bvalid,
s_axi_bresp,
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arready,
s_axi_rvalid,
s_axi_rresp,
s_axi_rdata,
s_axi_rready,
// debug signals
adc_clk,
adc_mon_valid,
adc_mon_data);
parameter PCORE_ID = 0;
parameter PCORE_DEVICE_TYPE = 0;
parameter PCORE_IODELAY_GROUP = "adc_if_delay_group";
parameter C_S_AXI_MIN_SIZE = 32'hffff;
parameter C_BASEADDR = 32'hffffffff;
parameter C_HIGHADDR = 32'h00000000;
// adc interface (clk, data, over-range)
input adc_clk_in_p;
input adc_clk_in_n;
input [13:0] adc_data_in_p;
input [13:0] adc_data_in_n;
input adc_or_in_p;
input adc_or_in_n;
// master-slave interface
output adc_start_out;
output dma_start_out;
input adc_start_in;
input dma_start_in;
// delay interface
input delay_clk;
// dma interface
output adc_dvalid;
output [63:0] adc_ddata;
input adc_overflow;
// axi interface
input s_axi_aclk;
input s_axi_aresetn;
input s_axi_awvalid;
input [31:0] s_axi_awaddr;
output s_axi_awready;
input s_axi_wvalid;
input [31:0] s_axi_wdata;
input [ 3:0] s_axi_wstrb;
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
input s_axi_bready;
input s_axi_arvalid;
input [31:0] s_axi_araddr;
output s_axi_arready;
output s_axi_rvalid;
output [ 1:0] s_axi_rresp;
output [31:0] s_axi_rdata;
input s_axi_rready;
// debug signals
output adc_clk;
output adc_mon_valid;
output [59:0] adc_mon_data;
// internal registers
reg adc_start_out = 'd0;
reg [ 1:0] adc_data_cnt = 'd0;
reg adc_valid = 'd0;
reg [63:0] adc_data = 'd0;
reg up_adc_status_pn_err = 'd0;
reg up_adc_status_pn_oos = 'd0;
reg up_adc_status_or = 'd0;
reg [31:0] up_rdata = 'd0;
reg up_ack = 'd0;
// internal clocks & resets
wire adc_rst;
wire up_rstn;
wire up_clk;
// internal signals
wire adc_start_s;
wire dma_start_s;
wire [13:0] adc_data_a_s;
wire [13:0] adc_data_b_s;
wire adc_or_a_s;
wire adc_or_b_s;
wire [15:0] adc_dcfilter_data_a_s;
wire [15:0] adc_dcfilter_data_b_s;
wire [15:0] adc_channel_data_a_s;
wire [15:0] adc_channel_data_b_s;
wire adc_enable_a_s;
wire adc_enable_b_s;
wire up_adc_pn_err_a_s;
wire up_adc_pn_oos_a_s;
wire up_adc_or_a_s;
wire up_adc_pn_err_b_s;
wire up_adc_pn_oos_b_s;
wire up_adc_or_b_s;
wire adc_ddr_edgesel_s;
wire adc_pin_mode_s;
wire adc_status_s;
wire delay_rst_s;
wire delay_sel_s;
wire delay_rwn_s;
wire [ 7:0] delay_addr_s;
wire [ 4:0] delay_wdata_s;
wire [ 4:0] delay_rdata_s;
wire delay_ack_t_s;
wire delay_locked_s;
wire dma_valid_s;
wire dma_last_s;
wire [63:0] dma_data_s;
wire dma_ready_s;
wire dma_status_s;
wire up_sel_s;
wire up_wr_s;
wire [13:0] up_addr_s;
wire [31:0] up_wdata_s;
wire [31:0] up_adc_common_rdata_s;
wire up_adc_common_ack_s;
wire [31:0] up_adc_channel_rdata_a_s;
wire up_adc_channel_ack_a_s;
wire [31:0] up_adc_channel_rdata_b_s;
wire up_adc_channel_ack_b_s;
// signal name changes
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
// monitor signals
assign adc_mon_valid = 1'b1;
assign adc_mon_data[15: 0] = adc_channel_data_a_s;
assign adc_mon_data[31:16] = adc_channel_data_b_s;
assign adc_mon_data[45:32] = adc_data_a_s;
assign adc_mon_data[59:46] = adc_data_b_s;
// multiple instances synchronization
assign adc_start_s = (PCORE_ID == 32'd0) ? adc_start_out : adc_start_in;
assign dma_start_s = (PCORE_ID == 32'd0) ? dma_start_out : dma_start_in;
always @(posedge adc_clk) begin
if (adc_rst == 1'b1) begin
adc_start_out <= 1'b0;
end else begin
adc_start_out <= 1'b1;
end
end
// User Channels
// ----------------------------
// The default provided here has two channels. However, provisions are added to software
// to support up to 16 user channels (that is 14, if you keep these two as it is).
// The channels may implement any post processing- such as decimation or filtering.
// If using the same processor controls, an enable is provided for each channel.
// You may use this signal to control the write to the DMA interface.
// Also note that the data bitwidths may require padding or truncation to match the
// external DMA bus width. This design as it is, uses 64bits.
// THIS IS NOT A COMPLETE SOLUTION and individual needs may vary.
// adc channels - dma interface
always @(posedge adc_clk) begin
adc_data_cnt <= adc_data_cnt + 1'b1;
case ({adc_enable_b_s, adc_enable_a_s})
2'b11: begin // both I and Q
adc_valid <= adc_data_cnt[0] & adc_start_s;
adc_data <= {adc_channel_data_b_s, adc_channel_data_a_s, adc_data[63:32]};
end
2'b10: begin // Q only
adc_valid <= adc_data_cnt[0] & adc_data_cnt[1] & adc_start_s;
adc_data <= {adc_channel_data_b_s, adc_data[63:16]};
end
2'b01: begin // I only
adc_valid <= adc_data_cnt[0] & adc_data_cnt[1] & adc_start_s;
adc_data <= {adc_channel_data_a_s, adc_data[63:16]};
end
default: begin // no channels
adc_valid <= adc_start_s;
adc_data <= {4{16'hdead}};
end
endcase
end
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_adc_status_pn_err <= 'd0;
up_adc_status_pn_oos <= 'd0;
up_adc_status_or <= 'd0;
up_rdata <= 'd0;
up_ack <= 'd0;
end else begin
up_adc_status_pn_err <= up_adc_pn_err_a_s | up_adc_pn_err_b_s;
up_adc_status_pn_oos <= up_adc_pn_oos_a_s | up_adc_pn_oos_b_s;
up_adc_status_or <= up_adc_or_a_s | up_adc_or_b_s;
up_rdata <= up_adc_common_rdata_s | up_adc_channel_rdata_a_s | up_adc_channel_rdata_b_s;
up_ack <= up_adc_common_ack_s | up_adc_channel_ack_a_s | up_adc_channel_ack_b_s;
end
end
// channel
axi_ad9643_channel #(.IQSEL(0), .CHID(0)) i_channel_0 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_data (adc_data_a_s),
.adc_or (adc_or_a_s),
.adc_dcfilter_data_out (adc_dcfilter_data_a_s),
.adc_dcfilter_data_in (adc_dcfilter_data_b_s),
.adc_iqcor_data (adc_channel_data_a_s),
.adc_enable (adc_enable_a_s),
.up_adc_pn_err (up_adc_pn_err_a_s),
.up_adc_pn_oos (up_adc_pn_oos_a_s),
.up_adc_or (up_adc_or_a_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wdata (up_wdata_s),
.up_rdata (up_adc_channel_rdata_a_s),
.up_ack (up_adc_channel_ack_a_s));
// channel
axi_ad9643_channel #(.IQSEL(1), .CHID(1)) i_channel_1 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_data (adc_data_b_s),
.adc_or (adc_or_b_s),
.adc_dcfilter_data_out (adc_dcfilter_data_b_s),
.adc_dcfilter_data_in (adc_dcfilter_data_a_s),
.adc_iqcor_data (adc_channel_data_b_s),
.adc_enable (adc_enable_b_s),
.up_adc_pn_err (up_adc_pn_err_b_s),
.up_adc_pn_oos (up_adc_pn_oos_b_s),
.up_adc_or (up_adc_or_b_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wdata (up_wdata_s),
.up_rdata (up_adc_channel_rdata_b_s),
.up_ack (up_adc_channel_ack_b_s));
// main (dma interface)
assign adc_dvalid = adc_valid;
assign adc_ddata = adc_data;
// main (device interface)
axi_ad9643_if #(
.PCORE_DEVICE_TYPE (PCORE_DEVICE_TYPE),
.PCORE_IODELAY_GROUP (PCORE_IODELAY_GROUP))
i_if (
.adc_clk_in_p (adc_clk_in_p),
.adc_clk_in_n (adc_clk_in_n),
.adc_data_in_p (adc_data_in_p),
.adc_data_in_n (adc_data_in_n),
.adc_or_in_p (adc_or_in_p),
.adc_or_in_n (adc_or_in_n),
.adc_clk (adc_clk),
.adc_data_a (adc_data_a_s),
.adc_data_b (adc_data_b_s),
.adc_or_a (adc_or_a_s),
.adc_or_b (adc_or_b_s),
.adc_status (adc_status_s),
.adc_ddr_edgesel (adc_ddr_edgesel_s),
.adc_pin_mode (adc_pin_mode_s),
.delay_clk (delay_clk),
.delay_rst (delay_rst_s),
.delay_sel (delay_sel_s),
.delay_rwn (delay_rwn_s),
.delay_addr (delay_addr_s),
.delay_wdata (delay_wdata_s),
.delay_rdata (delay_rdata_s),
.delay_ack_t (delay_ack_t_s),
.delay_locked (delay_locked_s));
// common processor control
up_adc_common #(
.PCORE_ID(PCORE_ID),
.PCORE_VERSION(32'h00060061)
) i_up_adc_common (
.mmcm_rst (),
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_r1_mode (),
.adc_ddr_edgesel (adc_ddr_edgesel_s),
.adc_pin_mode (adc_pin_mode_s),
.adc_status (adc_status_s),
.adc_status_pn_err (up_adc_status_pn_err),
.adc_status_pn_oos (up_adc_status_pn_oos),
.adc_status_or (up_adc_status_or),
.adc_clk_ratio (32'd1),
.delay_clk (delay_clk),
.delay_rst (delay_rst_s),
.delay_sel (delay_sel_s),
.delay_rwn (delay_rwn_s),
.delay_addr (delay_addr_s),
.delay_wdata (delay_wdata_s),
.delay_rdata (delay_rdata_s),
.delay_ack_t (delay_ack_t_s),
.delay_locked (delay_locked_s),
.drp_clk (1'd0),
.drp_rst (),
.drp_sel (),
.drp_wr (),
.drp_addr (),
.drp_wdata (),
.drp_rdata (16'd0),
.drp_ack_t (1'd0),
.dma_clk (adc_clk),
.dma_start (dma_start_out),
.dma_stream (),
.dma_count (),
.dma_ovf (adc_overflow),
.dma_unf (1'b0),
.dma_bw (32'h00000008),
.dma_status (dma_status_s),
.up_usr_chanmax (),
.adc_usr_chanmax (8'd0),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wdata (up_wdata_s),
.up_rdata (up_adc_common_rdata_s),
.up_ack (up_adc_common_ack_s));
// up bus interface
up_axi #(
.PCORE_BASEADDR (C_BASEADDR),
.PCORE_HIGHADDR (C_HIGHADDR))
i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wdata (up_wdata_s),
.up_rdata (up_rdata),
.up_ack (up_ack));
endmodule
// ***************************************************************************
// ***************************************************************************
|
/*
Andrew Mattheisen
Zhiyang Ong
EE-577b 2007 fall
VITERBI DECODER
spd module
*/
`include "spdu.v"
`include "demux2to4.v"
`include "selector.v"
module spd (d0, d1, d2, d3, pm0, pm1, pm2, pm3, out, clk, reset);
// outputs
output out;
// inputs
input d0, d1, d2, d3;
input [3:0] pm0, pm1, pm2, pm3;
input clk, reset;
// wires
wire out;
wire selectord0, selectord1;
wire spdu0out0, spdu0out1, spdu0out2, spdu0out3;
wire spdu1out0, spdu1out1, spdu1out2, spdu1out3;
wire spdu2out0, spdu2out1, spdu2out2, spdu2out3;
wire spdu3out0, spdu3out1, spdu3out2, spdu3out3;
wire spdu4out0, spdu4out1, spdu4out2, spdu4out3;
wire spdu5out0, spdu5out1, spdu5out2, spdu5out3;
wire spdu6out0, spdu6out1, spdu6out2, spdu6out3;
wire spdu7out0, spdu7out1, spdu7out2, spdu7out3;
wire spdu8out0, spdu8out1, spdu8out2, spdu8out3;
wire spdu9out0, spdu9out1, spdu9out2, spdu9out3;
wire spdu10out0, spdu10out1, spdu10out2, spdu10out3;
wire spdu11out0, spdu11out1, spdu11out2, spdu11out3;
wire spdu12out0, spdu12out1, spdu12out2, spdu12out3;
wire spdu13out0, spdu13out1, spdu13out2, spdu13out3;
wire spdu14out0, spdu14out1, spdu14out2, spdu14out3;
spdu spdu0(1'b0,
1'b0,
1'b1,
1'b1, d0, d1, d2, d3,
spdu0out0,
spdu0out1,
spdu0out2,
spdu0out3, clk, reset);
spdu spdu1(spdu0out0,
spdu0out1,
spdu0out2,
spdu0out3, d0, d1, d2, d3,
spdu1out0,
spdu1out1,
spdu1out2,
spdu1out3, clk, reset);
spdu spdu2(spdu1out0,
spdu1out1,
spdu1out2,
spdu1out3, d0, d1, d2, d3,
spdu2out0,
spdu2out1,
spdu2out2,
spdu2out3, clk, reset);
spdu spdu3(spdu2out0,
spdu2out1,
spdu2out2,
spdu2out3, d0, d1, d2, d3,
spdu3out0,
spdu3out1,
spdu3out2,
spdu3out3, clk, reset);
spdu spdu4(spdu3out0,
spdu3out1,
spdu3out2,
spdu3out3, d0, d1, d2, d3,
spdu4out0,
spdu4out1,
spdu4out2,
spdu4out3, clk, reset);
spdu spdu5(spdu4out0,
spdu4out1,
spdu4out2,
spdu4out3, d0, d1, d2, d3,
spdu5out0,
spdu5out1,
spdu5out2,
spdu5out3, clk, reset);
spdu spdu6(spdu5out0,
spdu5out1,
spdu5out2,
spdu5out3, d0, d1, d2, d3,
spdu6out0,
spdu6out1,
spdu6out2,
spdu6out3, clk, reset);
spdu spdu7(spdu6out0,
spdu6out1,
spdu6out2,
spdu6out3, d0, d1, d2, d3,
spdu7out0,
spdu7out1,
spdu7out2,
spdu7out3, clk, reset);
spdu spdu8(spdu7out0,
spdu7out1,
spdu7out2,
spdu7out3, d0, d1, d2, d3,
spdu8out0,
spdu8out1,
spdu8out2,
spdu8out3, clk, reset);
spdu spdu9(spdu8out0,
spdu8out1,
spdu8out2,
spdu8out3, d0, d1, d2, d3,
spdu9out0,
spdu9out1,
spdu9out2,
spdu9out3, clk, reset);
spdu spdu10(spdu9out0,
spdu9out1,
spdu9out2,
spdu9out3, d0, d1, d2, d3,
spdu10out0,
spdu10out1,
spdu10out2,
spdu10out3, clk, reset);
spdu spdu11(spdu10out0,
spdu10out1,
spdu10out2,
spdu10out3, d0, d1, d2, d3,
spdu11out0,
spdu11out1,
spdu11out2,
spdu11out3, clk, reset);
spdu spdu12(spdu11out0,
spdu11out1,
spdu11out2,
spdu11out3, d0, d1, d2, d3,
spdu12out0,
spdu12out1,
spdu12out2,
spdu12out3, clk, reset);
spdu spdu13(spdu12out0,
spdu12out1,
spdu12out2,
spdu12out3, d0, d1, d2, d3,
spdu13out0,
spdu13out1,
spdu13out2,
spdu13out3, clk, reset);
spdu spdu14(spdu13out0,
spdu13out1,
spdu13out2,
spdu13out3, d0, d1, d2, d3,
spdu14out0,
spdu14out1,
spdu14out2,
spdu14out3, clk, reset);
selector selector1 (pm0, pm1, pm2, pm3, selectord0, selectord1);
demux demux1 (spdu14out0, spdu14out1, spdu14out2, spdu14out3,
selectord0, selectord1, out);
endmodule
|
// megafunction wizard: %LPM_ADD_SUB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_add_sub
// ============================================================
// File Name: mylpm_addsub.v
// Megafunction Name(s):
// lpm_add_sub
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
//Copyright (C) 1991-2003 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
module mylpm_addsub (
add_sub,
dataa,
datab,
clock,
result);
input add_sub;
input [15:0] dataa;
input [15:0] datab;
input clock;
output [15:0] result;
wire [15:0] sub_wire0;
wire [15:0] result = sub_wire0[15:0];
lpm_add_sub lpm_add_sub_component (
.dataa (dataa),
.add_sub (add_sub),
.datab (datab),
.clock (clock),
.result (sub_wire0));
defparam
lpm_add_sub_component.lpm_width = 16,
lpm_add_sub_component.lpm_direction = "UNUSED",
lpm_add_sub_component.lpm_type = "LPM_ADD_SUB",
lpm_add_sub_component.lpm_hint = "ONE_INPUT_IS_CONSTANT=NO",
lpm_add_sub_component.lpm_pipeline = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: nBit NUMERIC "16"
// Retrieval info: PRIVATE: Function NUMERIC "2"
// Retrieval info: PRIVATE: WhichConstant NUMERIC "0"
// Retrieval info: PRIVATE: ConstantA NUMERIC "0"
// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
// Retrieval info: PRIVATE: ValidCtA NUMERIC "0"
// Retrieval info: PRIVATE: ValidCtB NUMERIC "0"
// Retrieval info: PRIVATE: CarryIn NUMERIC "0"
// Retrieval info: PRIVATE: CarryOut NUMERIC "0"
// Retrieval info: PRIVATE: Overflow NUMERIC "0"
// Retrieval info: PRIVATE: Latency NUMERIC "1"
// Retrieval info: PRIVATE: aclr NUMERIC "0"
// Retrieval info: PRIVATE: clken NUMERIC "0"
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: LPM_DIRECTION STRING "UNUSED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ADD_SUB"
// Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=NO"
// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1"
// Retrieval info: USED_PORT: add_sub 0 0 0 0 INPUT NODEFVAL add_sub
// Retrieval info: USED_PORT: result 0 0 16 0 OUTPUT NODEFVAL result[15..0]
// Retrieval info: USED_PORT: dataa 0 0 16 0 INPUT NODEFVAL dataa[15..0]
// Retrieval info: USED_PORT: datab 0 0 16 0 INPUT NODEFVAL datab[15..0]
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: CONNECT: @add_sub 0 0 0 0 add_sub 0 0 0 0
// Retrieval info: CONNECT: result 0 0 16 0 @result 0 0 16 0
// Retrieval info: CONNECT: @dataa 0 0 16 0 dataa 0 0 16 0
// Retrieval info: CONNECT: @datab 0 0 16 0 datab 0 0 16 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
//////////////////////////////////////////////////////////////////
// //
// 8KBytes SRAM configured with boot software //
// //
// This file is part of the Amber project //
// http://www.opencores.org/project,amber //
// //
// Description //
// Holds just enough software to get the system going. //
// The boot loader fits into this 8KB embedded SRAM on the //
// FPGA and enables it to load large applications via the //
// serial port (UART) into the DDR3 memory //
// //
// Author(s): //
// - Conor Santifort, [email protected] //
// //
//////////////////////////////////////////////////////////////////
// //
// Copyright (C) 2010 Authors and OPENCORES.ORG //
// //
// This source file may be used and distributed without //
// restriction provided that this copyright statement is not //
// removed from the file and that any derivative work contains //
// the original copyright notice and the associated disclaimer. //
// //
// This source file is free software; you can redistribute it //
// and/or modify it under the terms of the GNU Lesser General //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any //
// later version. //
// //
// This source is distributed in the hope that it will be //
// useful, but WITHOUT ANY WARRANTY; without even the implied //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
// PURPOSE. See the GNU Lesser General Public License for more //
// details. //
// //
// You should have received a copy of the GNU Lesser General //
// Public License along with this source; if not, download it //
// from http://www.opencores.org/lgpl.shtml //
// //
//////////////////////////////////////////////////////////////////
module boot_mem128 #(
parameter WB_DWIDTH = 128,
parameter WB_SWIDTH = 16,
parameter MADDR_WIDTH = 10
)(
input i_wb_clk, // WISHBONE clock
input [31:0] i_wb_adr,
input [WB_SWIDTH-1:0] i_wb_sel,
input i_wb_we,
output [WB_DWIDTH-1:0] o_wb_dat,
input [WB_DWIDTH-1:0] i_wb_dat,
input i_wb_cyc,
input i_wb_stb,
output o_wb_ack,
output o_wb_err
);
wire start_write;
wire start_read;
wire [WB_DWIDTH-1:0] read_data;
wire [WB_DWIDTH-1:0] write_data;
wire [WB_SWIDTH-1:0] byte_enable;
wire [MADDR_WIDTH-1:0] address;
`ifdef AMBER_WISHBONE_DEBUG
reg [7:0] jitter_r = 8'h0f;
reg [1:0] start_read_r = 'd0;
`else
reg start_read_r = 'd0;
`endif
// Can't start a write while a read is completing. The ack for the read cycle
// needs to be sent first
`ifdef AMBER_WISHBONE_DEBUG
assign start_write = i_wb_stb && i_wb_we && !(|start_read_r) && jitter_r[0];
`else
assign start_write = i_wb_stb && i_wb_we && !(|start_read_r);
`endif
assign start_read = i_wb_stb && !i_wb_we && !(|start_read_r);
`ifdef AMBER_WISHBONE_DEBUG
always @( posedge i_wb_clk )
jitter_r <= {jitter_r[6:0], jitter_r[7] ^ jitter_r[4] ^ jitter_r[1]};
always @( posedge i_wb_clk )
if (start_read)
start_read_r <= {3'd0, start_read};
else if (o_wb_ack)
start_read_r <= 'd0;
else
start_read_r <= {start_read_r[2:0], start_read};
`else
always @( posedge i_wb_clk )
start_read_r <= start_read;
`endif
assign o_wb_err = 1'd0;
assign write_data = i_wb_dat;
assign byte_enable = i_wb_sel;
assign o_wb_dat = read_data;
assign address = i_wb_adr[MADDR_WIDTH+3:4];
`ifdef AMBER_WISHBONE_DEBUG
assign o_wb_ack = i_wb_stb && ( start_write || start_read_r[jitter_r[1]] );
`else
assign o_wb_ack = i_wb_stb && ( start_write || start_read_r );
`endif
// ------------------------------------------------------
// Instantiate SRAMs
// ------------------------------------------------------
//
`ifdef XILINX_FPGA
xs6_sram_1024x128_byte_en
#(
// This file holds a software image used for FPGA simulations
// This pre-processor syntax works with both the simulator
// and ISE, which I couldn't get to work with giving it the
// file name as a define.
`ifdef BOOT_MEM_PARAMS_FILE
`include `BOOT_MEM_PARAMS_FILE
`else
`ifdef BOOT_LOADER_ETHMAC
`include "boot-loader-ethmac_memparams128.v"
`else
// default file
`include "boot-loader_memparams128.v"
`endif
`endif
)
`endif
`ifndef XILINX_FPGA
generic_sram_byte_en
#(
.DATA_WIDTH ( WB_DWIDTH ),
.ADDRESS_WIDTH ( MADDR_WIDTH )
)
`endif
u_mem (
.i_clk ( i_wb_clk ),
.i_write_enable ( start_write ),
.i_byte_enable ( byte_enable ),
.i_address ( address ), // 1024 words, 128 bits
.o_read_data ( read_data ),
.i_write_data ( write_data )
);
// =======================================================================================
// =======================================================================================
// =======================================================================================
// Non-synthesizable debug code
// =======================================================================================
//synopsys translate_off
`ifdef XILINX_SPARTAN6_FPGA
`ifdef BOOT_MEM_PARAMS_FILE
initial
$display("Boot mem file is %s", `BOOT_MEM_PARAMS_FILE );
`endif
`endif
//synopsys translate_on
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2012.2
// Copyright (C) 2012 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module types_float_double_grp_fu_86_ACMP_dadd_2_io(
clk,
reset,
io_ce,
io_rdy,
io_a,
io_b,
io_result);
input clk;
input io_ce;
output io_rdy;
input reset;
input[64 - 1:0] io_a;
input[64 - 1:0] io_b;
output[64 - 1:0] io_result;
adder64fp m(
.clk(clk),
.ce(io_ce),
.rdy(io_rdy),
.a(io_a),
.b(io_b),
.operation(6'd0), //according to DSP core manual
.result(io_result));
endmodule
module adder64fp(
clk,
ce,
rdy,
a,
b,
operation,
result);
input clk;
input ce;
output rdy;
input [63 : 0] a;
input [63 : 0] b;
input [5 : 0] operation;
output [63 : 0] result;
//assign result = a + b;
//ACMP_dadd #(
//.ID( ID ),
//.NUM_STAGE( 16 ),
//.din0_WIDTH( din0_WIDTH ),
//.din1_WIDTH( din1_WIDTH ),
//.dout_WIDTH( dout_WIDTH ))
//ACMP_dadd_U(
// .clk( clk ),
// .reset( reset ),
// .ce( ce ),
// .din0( din0 ),
// .din1( din1 ),
// .dout( dout ));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A221OI_4_V
`define SKY130_FD_SC_MS__A221OI_4_V
/**
* a221oi: 2-input AND into first two inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | C1)
*
* Verilog wrapper for a221oi with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a221oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a221oi_4 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__a221oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a221oi_4 (
Y ,
A1,
A2,
B1,
B2,
C1
);
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__a221oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__A221OI_4_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2004 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg [63:0] rf;
reg [63:0] rf2;
reg [63:0] biu;
reg okidoki;
always @* begin
rf[63:32] = biu[63:32] & {32{okidoki}};
rf[31:0] = {32{okidoki}};
rf2 = rf;
rf2[31:0] = ~{32{okidoki}};
end
reg [31:0] src1, src0, sr, mask;
wire [31:0] dualasr
= ((| src1[31:4])
? {{16{src0[31]}}, {16{src0[15]}}}
: ( ( sr & {2{mask[31:16]}})
| ( {{16{src0[31]}}, {16{src0[15]}}}
& {2{~mask[31:16]}})));
wire [31:0] sl_mask
= (32'hffffffff << src1[4:0]);
wire [31:0] sr_mask
= {sl_mask[0], sl_mask[1],
sl_mask[2], sl_mask[3], sl_mask[4],
sl_mask[5], sl_mask[6], sl_mask[7],
sl_mask[8], sl_mask[9],
sl_mask[10], sl_mask[11],
sl_mask[12], sl_mask[13], sl_mask[14],
sl_mask[15], sl_mask[16],
sl_mask[17], sl_mask[18], sl_mask[19],
sl_mask[20], sl_mask[21],
sl_mask[22], sl_mask[23], sl_mask[24],
sl_mask[25], sl_mask[26],
sl_mask[27], sl_mask[28], sl_mask[29],
sl_mask[30], sl_mask[31]};
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
`ifdef TEST_VERBOSE
$write("%x %x %x %x %x\n", rf, rf2, dualasr, sl_mask, sr_mask);
`endif
if (cyc==1) begin
biu <= 64'h12451282_abadee00;
okidoki <= 1'b0;
src1 <= 32'h00000001;
src0 <= 32'h9a4f1235;
sr <= 32'h0f19f567;
mask <= 32'h7af07ab4;
end
if (cyc==2) begin
biu <= 64'h12453382_abad8801;
okidoki <= 1'b1;
if (rf != 64'h0) $stop;
if (rf2 != 64'h00000000ffffffff) $stop;
src1 <= 32'h0010000f;
src0 <= 32'h028aa336;
sr <= 32'h42ad0377;
mask <= 32'h1ab3b906;
if (dualasr != 32'h8f1f7060) $stop;
if (sl_mask != 32'hfffffffe) $stop;
if (sr_mask != 32'h7fffffff) $stop;
end
if (cyc==3) begin
biu <= 64'h12422382_77ad8802;
okidoki <= 1'b1;
if (rf != 64'h12453382ffffffff) $stop;
if (rf2 != 64'h1245338200000000) $stop;
src1 <= 32'h0000000f;
src0 <= 32'h5c158f71;
sr <= 32'h7076c40a;
mask <= 32'h33eb3d44;
if (dualasr != 32'h0000ffff) $stop;
if (sl_mask != 32'hffff8000) $stop;
if (sr_mask != 32'h0001ffff) $stop;
end
if (cyc==4) begin
if (rf != 64'h12422382ffffffff) $stop;
if (rf2 != 64'h1242238200000000) $stop;
if (dualasr != 32'h3062cc1e) $stop;
if (sl_mask != 32'hffff8000) $stop;
if (sr_mask != 32'h0001ffff) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
// --------------------------------------------------------------------
// Copyright (c) 2008 by Terasic Technologies Inc.
// --------------------------------------------------------------------
//
// Permission:
//
// Terasic grants permission to use and modify this code for use
// in synthesis for all Terasic Development Boards and Altera Development
// Kits made by Terasic. Other use of this code, including the selling
// ,duplication, or modification of any portion is strictly prohibited.
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods. Terasic provides no warranty regarding the use
// or functionality of this code.
//
// --------------------------------------------------------------------
//
// Terasic Technologies Inc
// 356 Fu-Shin E. Rd Sec. 1. JhuBei City,
// HsinChu County, Taiwan
// 302
//
// web: http://www.terasic.com/
// email: [email protected]
//
// --------------------------------------------------------------------
//
// Major Functions: command
//
// --------------------------------------------------------------------
//
// Revision History :
// --------------------------------------------------------------------
// Ver :| Author :| Mod. Date :| Changes Made:
// V1.0 :| Johnny Fan :| 08/04/22 :| Initial Revision
// --------------------------------------------------------------------
module command(
CLK,
RESET_N,
SADDR,
NOP,
READA,
WRITEA,
REFRESH,
PRECHARGE,
LOAD_MODE,
REF_REQ,
INIT_REQ,
PM_STOP,
PM_DONE,
REF_ACK,
CM_ACK,
OE,
SA,
BA,
CS_N,
CKE,
RAS_N,
CAS_N,
WE_N
);
`include "Sdram_Params.h"
input CLK; // System Clock
input RESET_N; // System Reset
input [`ASIZE-1:0] SADDR; // Address
input NOP; // Decoded NOP command
input READA; // Decoded READA command
input WRITEA; // Decoded WRITEA command
input REFRESH; // Decoded REFRESH command
input PRECHARGE; // Decoded PRECHARGE command
input LOAD_MODE; // Decoded LOAD_MODE command
input REF_REQ; // Hidden refresh request
input INIT_REQ; // Hidden initial request
input PM_STOP; // Page mode stop
input PM_DONE; // Page mode done
output REF_ACK; // Refresh request acknowledge
output CM_ACK; // Command acknowledge
output OE; // OE signal for data path module
output [11:0] SA; // SDRAM address
output [1:0] BA; // SDRAM bank address
output [1:0] CS_N; // SDRAM chip selects
output CKE; // SDRAM clock enable
output RAS_N; // SDRAM RAS
output CAS_N; // SDRAM CAS
output WE_N; // SDRAM WE_N
reg CM_ACK;
reg REF_ACK;
reg OE;
reg [11:0] SA;
reg [1:0] BA;
reg [1:0] CS_N;
reg CKE;
reg RAS_N;
reg CAS_N;
reg WE_N;
// Internal signals
reg do_reada;
reg do_writea;
reg do_refresh;
reg do_precharge;
reg do_load_mode;
reg do_initial;
reg command_done;
reg [7:0] command_delay;
reg [1:0] rw_shift;
reg do_act;
reg rw_flag;
reg do_rw;
reg [6:0] oe_shift;
reg oe1;
reg oe2;
reg oe3;
reg oe4;
reg [3:0] rp_shift;
reg rp_done;
reg ex_read;
reg ex_write;
wire [`ROWSIZE - 1:0] rowaddr;
wire [`COLSIZE - 1:0] coladdr;
wire [`BANKSIZE - 1:0] bankaddr;
assign rowaddr = SADDR[`ROWSTART + `ROWSIZE - 1: `ROWSTART]; // assignment of the row address bits from SADDR
assign coladdr = SADDR[`COLSTART + `COLSIZE - 1:`COLSTART]; // assignment of the column address bits
assign bankaddr = SADDR[`BANKSTART + `BANKSIZE - 1:`BANKSTART]; // assignment of the bank address bits
// This always block monitors the individual command lines and issues a command
// to the next stage if there currently another command already running.
always @(posedge CLK or negedge RESET_N)
begin
if (RESET_N == 0)
begin
do_reada <= 0;
do_writea <= 0;
do_refresh <= 0;
do_precharge <= 0;
do_load_mode <= 0;
do_initial <= 0;
command_done <= 0;
command_delay <= 0;
rw_flag <= 0;
rp_shift <= 0;
rp_done <= 0;
ex_read <= 0;
ex_write <= 0;
end
else
begin
// Issue the appropriate command if the sdram is not currently busy
if( INIT_REQ == 1 )
begin
do_reada <= 0;
do_writea <= 0;
do_refresh <= 0;
do_precharge <= 0;
do_load_mode <= 0;
do_initial <= 1;
command_done <= 0;
command_delay <= 0;
rw_flag <= 0;
rp_shift <= 0;
rp_done <= 0;
ex_read <= 0;
ex_write <= 0;
end
else
begin
do_initial <= 0;
if ((REF_REQ == 1 | REFRESH == 1) & command_done == 0 & do_refresh == 0 & rp_done == 0 // Refresh
& do_reada == 0 & do_writea == 0)
do_refresh <= 1;
else
do_refresh <= 0;
if ((READA == 1) & (command_done == 0) & (do_reada == 0) & (rp_done == 0) & (REF_REQ == 0)) // READA
begin
do_reada <= 1;
ex_read <= 1;
end
else
do_reada <= 0;
if ((WRITEA == 1) & (command_done == 0) & (do_writea == 0) & (rp_done == 0) & (REF_REQ == 0)) // WRITEA
begin
do_writea <= 1;
ex_write <= 1;
end
else
do_writea <= 0;
if ((PRECHARGE == 1) & (command_done == 0) & (do_precharge == 0)) // PRECHARGE
do_precharge <= 1;
else
do_precharge <= 0;
if ((LOAD_MODE == 1) & (command_done == 0) & (do_load_mode == 0)) // LOADMODE
do_load_mode <= 1;
else
do_load_mode <= 0;
// set command_delay shift register and command_done flag
// The command delay shift register is a timer that is used to ensure that
// the SDRAM devices have had sufficient time to finish the last command.
if ((do_refresh == 1) | (do_reada == 1) | (do_writea == 1) | (do_precharge == 1)
| (do_load_mode == 1))
begin
command_delay <= 8'b11111111;
command_done <= 1;
rw_flag <= do_reada;
end
else
begin
command_done <= command_delay[0]; // the command_delay shift operation
command_delay <= (command_delay>>1);
end
// start additional timer that is used for the refresh, writea, reada commands
if (command_delay[0] == 0 & command_done == 1)
begin
rp_shift <= 4'b1111;
rp_done <= 1;
end
else
begin
if(SC_PM == 0)
begin
rp_shift <= (rp_shift>>1);
rp_done <= rp_shift[0];
end
else
begin
if( (ex_read == 0) && (ex_write == 0) )
begin
rp_shift <= (rp_shift>>1);
rp_done <= rp_shift[0];
end
else
begin
if( PM_STOP==1 )
begin
rp_shift <= (rp_shift>>1);
rp_done <= rp_shift[0];
ex_read <= 1'b0;
ex_write <= 1'b0;
end
end
end
end
end
end
end
// logic that generates the OE signal for the data path module
// For normal burst write he duration of OE is dependent on the configured burst length.
// For page mode accesses(SC_PM=1) the OE signal is turned on at the start of the write command
// and is left on until a PRECHARGE(page burst terminate) is detected.
//
always @(posedge CLK or negedge RESET_N)
begin
if (RESET_N == 0)
begin
oe_shift <= 0;
oe1 <= 0;
oe2 <= 0;
OE <= 0;
end
else
begin
if (SC_PM == 0)
begin
if (do_writea == 1)
begin
if (SC_BL == 1) // Set the shift register to the appropriate
oe_shift <= 0; // value based on burst length.
else if (SC_BL == 2)
oe_shift <= 1;
else if (SC_BL == 4)
oe_shift <= 7;
else if (SC_BL == 8)
oe_shift <= 127;
oe1 <= 1;
end
else
begin
oe_shift <= (oe_shift>>1);
oe1 <= oe_shift[0];
oe2 <= oe1;
oe3 <= oe2;
oe4 <= oe3;
if (SC_RCD == 2)
OE <= oe3;
else
OE <= oe4;
end
end
else
begin
if (do_writea == 1) // OE generation for page mode accesses
oe4 <= 1;
else if (do_precharge == 1 | do_reada == 1 | do_refresh==1 | do_initial == 1 | PM_STOP==1 )
oe4 <= 0;
OE <= oe4;
end
end
end
// This always block tracks the time between the activate command and the
// subsequent WRITEA or READA command, RC. The shift register is set using
// the configuration register setting SC_RCD. The shift register is loaded with
// a single '1' with the position within the register dependent on SC_RCD.
// When the '1' is shifted out of the register it sets so_rw which triggers
// a writea or reada command
//
always @(posedge CLK or negedge RESET_N)
begin
if (RESET_N == 0)
begin
rw_shift <= 0;
do_rw <= 0;
end
else
begin
if ((do_reada == 1) | (do_writea == 1))
begin
if (SC_RCD == 1) // Set the shift register
do_rw <= 1;
else if (SC_RCD == 2)
rw_shift <= 1;
else if (SC_RCD == 3)
rw_shift <= 2;
end
else
begin
rw_shift <= (rw_shift>>1);
do_rw <= rw_shift[0];
end
end
end
// This always block generates the command acknowledge, CM_ACK, signal.
// It also generates the acknowledge signal, REF_ACK, that acknowledges
// a refresh request that was generated by the internal refresh timer circuit.
always @(posedge CLK or negedge RESET_N)
begin
if (RESET_N == 0)
begin
CM_ACK <= 0;
REF_ACK <= 0;
end
else
begin
if (do_refresh == 1 & REF_REQ == 1) // Internal refresh timer refresh request
REF_ACK <= 1;
else if ((do_refresh == 1) | (do_reada == 1) | (do_writea == 1) | (do_precharge == 1) // externa commands
| (do_load_mode))
CM_ACK <= 1;
else
begin
REF_ACK <= 0;
CM_ACK <= 0;
end
end
end
// This always block generates the address, cs, cke, and command signals(ras,cas,wen)
//
always @(posedge CLK ) begin
if (RESET_N==0) begin
SA <= 0;
BA <= 0;
CS_N <= 1;
RAS_N <= 1;
CAS_N <= 1;
WE_N <= 1;
CKE <= 0;
end
else begin
CKE <= 1;
// Generate SA
if (do_writea == 1 | do_reada == 1) // ACTIVATE command is being issued, so present the row address
SA <= rowaddr;
else
SA <= coladdr; // else alway present column address
if ((do_rw==1) | (do_precharge))
SA[10] <= !SC_PM; // set SA[10] for autoprecharge read/write or for a precharge all command
// don't set it if the controller is in page mode.
if (do_precharge==1 | do_load_mode==1)
BA <= 0; // Set BA=0 if performing a precharge or load_mode command
else
BA <= bankaddr[1:0]; // else set it with the appropriate address bits
if (do_refresh==1 | do_precharge==1 | do_load_mode==1 | do_initial==1)
CS_N <= 0; // Select both chip selects if performing
else // refresh, precharge(all) or load_mode
begin
CS_N[0] <= SADDR[`ASIZE-1]; // else set the chip selects based off of the
CS_N[1] <= ~SADDR[`ASIZE-1]; // msb address bit
end
if(do_load_mode==1)
SA <= {2'b00,SDR_CL,SDR_BT,SDR_BL};
//Generate the appropriate logic levels on RAS_N, CAS_N, and WE_N
//depending on the issued command.
//
if ( do_refresh==1 ) begin // Refresh: S=00, RAS=0, CAS=0, WE=1
RAS_N <= 0;
CAS_N <= 0;
WE_N <= 1;
end
else if ((do_precharge==1) & ((oe4 == 1) | (rw_flag == 1))) begin // burst terminate if write is active
RAS_N <= 1;
CAS_N <= 1;
WE_N <= 0;
end
else if (do_precharge==1) begin // Precharge All: S=00, RAS=0, CAS=1, WE=0
RAS_N <= 0;
CAS_N <= 1;
WE_N <= 0;
end
else if (do_load_mode==1) begin // Mode Write: S=00, RAS=0, CAS=0, WE=0
RAS_N <= 0;
CAS_N <= 0;
WE_N <= 0;
end
else if (do_reada == 1 | do_writea == 1) begin // Activate: S=01 or 10, RAS=0, CAS=1, WE=1
RAS_N <= 0;
CAS_N <= 1;
WE_N <= 1;
end
else if (do_rw == 1) begin // Read/Write: S=01 or 10, RAS=1, CAS=0, WE=0 or 1
RAS_N <= 1;
CAS_N <= 0;
WE_N <= rw_flag;
end
else if (do_initial ==1) begin
RAS_N <= 1;
CAS_N <= 1;
WE_N <= 1;
end
else begin // No Operation: RAS=1, CAS=1, WE=1
RAS_N <= 1;
CAS_N <= 1;
WE_N <= 1;
end
end
end
endmodule
|
`include "sd_defines.v"
//-------------------------
//-------------------------
module sd_cmd_phy (
input sd_clk,
input rst,
input cmd_dat_i,
output reg cmd_dat_o,
output reg cmd_oe_o,
output [1:0] sd_adr_o,
input [7:0] sd_dat_i,
output reg [7:0] sd_dat_o,
output reg sd_we_o,
output reg sd_re_o,
input [1:2] fifo_full,
input [1:2] fifo_empty,
output [1:0] start_dat_t,
output fifo_acces_token
);
//---------------Input ports---------------
`define WRITE_CMD 32'h18
`define READ_CMD 32'h11
reg [6:0] Response_Size;
`ifdef SIM
`define INIT_DELAY 64
`else
`define INIT_DELAY 64
`endif
`define tx_cmd_fifo_empty fifo_empty [1]
parameter SEND_SIZE = 48;
parameter CONTENT_SIZE = 40;
parameter NCR = 2 ;
`define Vector_Index_Write (CONTENT_SIZE-1-cmd_flow_cnt_write)
`define Bit_Nr_Write (SEND_SIZE-cmd_flow_cnt_write)
//FSM
parameter SIZE = 5;
parameter
INIT = 5'b00001,
IDLE = 5'b00010,
WRITE = 5'b00100,
BUFFER_WRITE = 5'b01000,
READ = 5'b10000;
reg [SIZE-1:0] state;
reg [SIZE-1:0] next_state;
reg [1:0] start_dat_t_read;
reg [1:0] start_dat_t_write;
reg [39:0] in_buffer;
reg [2:0] read_byte_cnt;
//
reg [7:0] cmd_flow_cnt_write;
reg [7:0] cmd_flow_cnt_read;
reg cmd_dat_internal;
//
reg big_resp;
reg crc_rst_write;
reg crc_en_write;
reg crc_in_write;
wire [6:0] crc_val_write;
reg [1:0] sd_adr_o_read;
reg [1:0] sd_adr_o_write;
reg crc_rst_read;
reg crc_en_read;
reg crc_in_read;
wire [6:0] crc_val_read;
reg crc_buffering_write;
reg block_write;
reg block_read;
reg in_buff_ptr;
reg out_buff_ptr;
reg [2:0] read_index_cnt;
reg [7:0] in_buff_0;
reg [7:0] in_buff_1;
reg [6:0] crc_in_buff;
reg [7:0] response_status;
reg [6:0] index_check;
reg add_token_read;
CRC_7 CRC_7_WRITE(
.BITVAL (crc_in_write),
.Enable (crc_en_write),
.CLK (sd_clk),
.RST (crc_rst_write),
.CRC (crc_val_write));
CRC_7 CRC_7_READ(
.BITVAL (crc_in_read),
.Enable (crc_en_read),
.CLK (sd_clk),
.RST (crc_rst_read),
.CRC (crc_val_read));
always @ (posedge sd_clk or posedge rst )
begin
if (rst) begin
cmd_dat_internal <=1'b1;
end
else begin
cmd_dat_internal<=cmd_dat_i;
end
end
always @ (state or cmd_flow_cnt_write or cmd_dat_internal or `tx_cmd_fifo_empty or read_byte_cnt or cmd_flow_cnt_write or cmd_flow_cnt_read )
begin : FSM_COMBO
next_state = 0;
case(state)
INIT: begin
if (cmd_flow_cnt_write >= `INIT_DELAY )begin
next_state = IDLE;
end
else begin
next_state = INIT;
end
end
IDLE: begin
if (!`tx_cmd_fifo_empty)
next_state =BUFFER_WRITE;
else if (!cmd_dat_internal)
next_state =READ;
else
next_state =IDLE;
end
BUFFER_WRITE: begin
if (read_byte_cnt>=5)
next_state = WRITE;
else
next_state =BUFFER_WRITE;
end
WRITE : begin
if (cmd_flow_cnt_write >= SEND_SIZE)
next_state = IDLE;
else
next_state = WRITE;
end
READ : begin
if (cmd_flow_cnt_read >= Response_Size+7)
next_state = IDLE;
else
next_state = READ;
end
default : next_state = INIT;
endcase
end
always @ (posedge sd_clk or posedge rst )
begin : FSM_SEQ
if (rst ) begin
state <= #1 INIT;
end
else begin
state <= #1 next_state;
end
end
reg fifo_acces_read,fifo_acces_write;
assign fifo_acces_token = fifo_acces_read | fifo_acces_write;
assign sd_adr_o = add_token_read ? sd_adr_o_read : sd_adr_o_write;
assign start_dat_t = add_token_read ? start_dat_t_read : start_dat_t_write;
reg tx_cmd_fifo_empty_tmp;
always @ (negedge sd_clk or posedge rst )
begin : OUTPUT_LOGIC
if (rst ) begin
crc_in_write=0;
crc_en_write=0;
crc_rst_write=0;
fifo_acces_write=0;
cmd_oe_o=1;
cmd_dat_o = 1;
crc_buffering_write=0;
sd_re_o<=0;
read_byte_cnt<=0;
block_read<=0;
sd_adr_o_write<=0;
cmd_flow_cnt_write=0;
start_dat_t_write<=0;
in_buffer<=0;
tx_cmd_fifo_empty_tmp<=0;
Response_Size<=40;
end
else begin
case(state)
INIT : begin
cmd_flow_cnt_write=cmd_flow_cnt_write+1;
cmd_oe_o=1;
cmd_dat_o = 1;
crc_buffering_write=0;
start_dat_t_write<=0;
end
IDLE: begin
cmd_flow_cnt_write=0;
cmd_oe_o=0;
// cmd_dat_o = 0;
start_dat_t_write<=0;
crc_in_write=0;
crc_en_write=0;
crc_rst_write=1;
read_byte_cnt<=0;
block_read<=0;
fifo_acces_write=0;
in_buffer<=0;
end
BUFFER_WRITE : begin
sd_re_o<=0;
fifo_acces_write=1;
tx_cmd_fifo_empty_tmp<=`tx_cmd_fifo_empty;
if (!tx_cmd_fifo_empty_tmp) begin
if(sd_re_o)
read_byte_cnt <= read_byte_cnt+1;
sd_adr_o_write <=0;
sd_re_o<=1;
if(sd_re_o) begin
case (read_byte_cnt) //If data is Avaible next cycle?
0: in_buffer[39:32] <=sd_dat_i;
1: in_buffer[31:24] <=sd_dat_i;
2: in_buffer[23:16] <=sd_dat_i;
3: in_buffer[15:8] <=sd_dat_i;
4: in_buffer[7:0] <=sd_dat_i;
endcase
if (in_buffer[39])
Response_Size<=127;
else
Response_Size<=40;
if (in_buffer[37:32] == `READ_CMD)
block_read<=1;
end
end
end
WRITE: begin
sd_re_o<=0;
cmd_oe_o=1;
cmd_dat_o = 1;
crc_en_write =0;
crc_rst_write=0;
crc_en_write=1;
if (crc_buffering_write==1) begin
cmd_oe_o =1;
if (`Bit_Nr_Write > 8 ) begin // 1->40 CMD, (41 >= CNT && CNT <=47) CRC, 48 stop_bit
if (cmd_flow_cnt_write==0)
cmd_dat_o = 0;
else
cmd_dat_o = in_buffer[`Vector_Index_Write];
if (`Bit_Nr_Write > 9 ) begin //1 step ahead
crc_in_write = in_buffer[`Vector_Index_Write-1];
end else begin
crc_en_write=0;
end
end
else if ( (`Bit_Nr_Write <=8) && (`Bit_Nr_Write >=2) ) begin
crc_en_write=0;
cmd_dat_o = crc_val_write[(`Bit_Nr_Write)-2];
if (block_read)
start_dat_t_write<=2'b10;
end
else begin
cmd_dat_o =1'b1;
end
cmd_flow_cnt_write=cmd_flow_cnt_write+1;
end
else begin //Pre load CRC
crc_buffering_write=1;
crc_in_write = 0;
end
end
endcase
end
end
always @ (posedge sd_clk or posedge rst )
begin
if (rst) begin
crc_rst_read=1;
crc_en_read=0;
crc_in_read=0;
cmd_flow_cnt_read=0;
response_status =0;
block_write=0;
index_check=0;
in_buff_ptr=0;
out_buff_ptr=0;
sd_adr_o_read<=0;
add_token_read=0;
in_buff_0<=0;
in_buff_1<=0;
read_index_cnt=0;
fifo_acces_read=0;
sd_dat_o<=0;
start_dat_t_read<=0;
sd_we_o<=0;
crc_in_buff=0;
end
else begin
case (state)
IDLE : begin
crc_en_read=0;
crc_rst_read=1;
cmd_flow_cnt_read=1;
index_check=0;
block_write=0;
in_buff_ptr=0;
out_buff_ptr=0;
add_token_read=0;
read_index_cnt=0;
sd_we_o<=0;
add_token_read=0;
fifo_acces_read=0;
start_dat_t_read<=0;
end
READ : begin
fifo_acces_read=1;
add_token_read=1; //Takes command over addres
crc_en_read=1;
crc_rst_read=0;
sd_we_o<=0;
if (in_buff_ptr != out_buff_ptr) begin
sd_adr_o_read <=1;
sd_we_o<=1;
if (in_buff_ptr)
sd_dat_o <=in_buff_0;
else
sd_dat_o <=in_buff_1;
out_buff_ptr=out_buff_ptr+1;
end
if (cmd_flow_cnt_read < (Response_Size))begin //40 First Bits
crc_in_read = cmd_dat_internal;
if (cmd_flow_cnt_read<8 ) begin //1+1+6 (S,T,Index)
index_check[7-cmd_flow_cnt_read] = cmd_dat_internal;
if (index_check[5:0] == `WRITE_CMD) begin
block_write=1;
end
end
else begin
if (!in_buff_ptr) begin
in_buff_0[7-read_index_cnt]<=cmd_dat_internal;
end
else begin
in_buff_1[7-read_index_cnt]<=cmd_dat_internal;
end
read_index_cnt=read_index_cnt+1;
if (read_index_cnt==0)
in_buff_ptr=in_buff_ptr+1;
end
end
else if ( cmd_flow_cnt_read - Response_Size <=6 ) begin //7-Crc Bit
crc_in_buff [(Response_Size+6)-(cmd_flow_cnt_read)] = cmd_dat_internal;
crc_en_read=0;
end
else begin //Commpare CRC read with calcualted.
if ((crc_in_buff != crc_val_read)) begin
response_status[0]=1;
end
else begin
response_status[0]=0;
end
sd_adr_o_read <=1;
sd_we_o<=1;
sd_dat_o<=response_status;
if (block_write)
start_dat_t_read<=2'b01;
end
cmd_flow_cnt_read = cmd_flow_cnt_read+1;
end
endcase
end
end
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 09:28:48 05/31/2011
// Design Name: upd77c25
// Module Name: /home/ikari/prj/sd2snes/verilog/sd2snes/updtest.tf
// Project Name: sd2snes
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: upd77c25
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module updtest;
// Inputs
reg [7:0] DI;
reg A0;
reg nCS;
reg nRD;
reg nWR;
reg RST;
reg CLK;
reg PGM_WR;
reg [23:0] PGM_DI;
reg [10:0] PGM_WR_ADDR;
reg DAT_WR;
reg [15:0] DAT_DI;
reg [9:0] DAT_WR_ADDR;
// debug
wire [15:0] SR;
wire [15:0] DR;
wire [10:0] PC;
wire [15:0] A;
wire [15:0] B;
wire [5:0] FL_A;
wire [5:0] FL_B;
// Outputs
wire [7:0] DO;
// variables
integer i;
// Instantiate the Unit Under Test (UUT)
upd77c25 uut (
.DI(DI),
.DO(DO),
.A0(A0),
.nCS(nCS),
.nRD(nRD),
.nWR(nWR),
.DP_nCS(1'b1),
.RST(RST),
.CLK(CLK),
.PGM_WR(PGM_WR),
.PGM_DI(PGM_DI),
.PGM_WR_ADDR(PGM_WR_ADDR),
.DAT_WR(DAT_WR),
.DAT_DI(DAT_DI),
.DAT_WR_ADDR(DAT_WR_ADDR),
.SR(SR),
.DR(DR),
.PC(PC),
.A(A),
.B(B),
.FL_A(FL_A),
.FL_B(FL_B)
);
initial begin
// Initialize Inputs
DI = 0;
A0 = 0;
nCS = 0;
nRD = 1;
nWR = 1;
RST = 1;
CLK = 0;
PGM_WR = 0;
PGM_DI = 0;
PGM_WR_ADDR = 0;
DAT_WR = 0;
DAT_DI = 0;
DAT_WR_ADDR = 0;
// Wait 100 ns for global reset to finish
#1000;
// Add stimulus here
nRD = 0;
#100 nRD = 1;
for (i=0; i < 1; i = i + 1) begin
#200 nRD = 0;
#200 nRD = 1;
end
#1000 DI = 8'h02;
nWR = 0;
#200 nWR = 1;
#3000 DI = 8'hc2;
for (i=0; i < 6; i = i + 1) begin
#400 nWR = 0;
#400 nWR = 1;
#400 nWR = 0;
#400 nWR = 1;
end
#15000;
#200 nWR = 0;
#200 nWR = 1;
#200 nWR = 0;
#200 nWR = 1;
#50000;
for (i=0; i < 10; i = i + 1) begin
#200 nRD = 0;
#200 nRD = 1;
end
#200 DI = 8'h06;
nWR = 0;
#200 nWR = 1;
#200 DI = 8'h7f;
for (i=0; i < 3; i = i + 1) begin
#400 nWR = 0;
#400 nWR = 1;
#400 nWR = 0;
#400 nWR = 1;
end
#15000;
for (i=0; i < 10; i = i + 1) begin
#200 nRD = 0;
#200 nRD = 1;
end
end
always #6 CLK = ~CLK;
endmodule
|
module sgpr(
lsu_source1_addr,
lsu_source2_addr,
lsu_dest_addr,
lsu_dest_data,
lsu_dest_wr_en,
lsu_instr_done_wfid,
lsu_instr_done,
lsu_source1_rd_en,
lsu_source2_rd_en,
simd0_rd_addr,
simd0_rd_en,
simd1_rd_addr,
simd1_rd_en,
simd2_rd_addr,
simd2_rd_en,
simd3_rd_addr,
simd3_rd_en,
simd0_wr_addr,
simd0_wr_en,
simd0_wr_data,
simd1_wr_addr,
simd1_wr_en,
simd1_wr_data,
simd2_wr_addr,
simd2_wr_en,
simd2_wr_data,
simd3_wr_addr,
simd3_wr_en,
simd3_wr_data,
simd0_wr_mask,
simd1_wr_mask,
simd2_wr_mask,
simd3_wr_mask,
simf0_rd_addr,
simf0_rd_en,
simf1_rd_addr,
simf1_rd_en,
simf2_rd_addr,
simf2_rd_en,
simf3_rd_addr,
simf3_rd_en,
simf0_wr_addr,
simf0_wr_en,
simf0_wr_data,
simf1_wr_addr,
simf1_wr_en,
simf1_wr_data,
simf2_wr_addr,
simf2_wr_en,
simf2_wr_data,
simf3_wr_addr,
simf3_wr_en,
simf3_wr_data,
simf0_wr_mask,
simf1_wr_mask,
simf2_wr_mask,
simf3_wr_mask,
salu_dest_data,
salu_dest_addr,
salu_dest_wr_en,
salu_source2_addr,
salu_source1_addr,
salu_instr_done_wfid,
salu_instr_done,
salu_source1_rd_en,
salu_source2_rd_en,
rfa_select_fu,
lsu_source1_data,
lsu_source2_data,
simd_rd_data,
simf_rd_data,
salu_source2_data,
salu_source1_data,
issue_alu_wr_done_wfid,
issue_alu_wr_done,
issue_alu_dest_reg_addr,
issue_alu_dest_reg_valid,
issue_lsu_instr_done_wfid,
issue_lsu_instr_done,
issue_lsu_dest_reg_addr,
issue_lsu_dest_reg_valid,
issue_valu_dest_reg_valid,
issue_valu_dest_addr,
clk,
`ifdef FPGA
clk_double,
`endif
rst
);
input clk;
`ifdef FPGA
input clk_double;
`endif
input rst;
input salu_source1_rd_en,
salu_source2_rd_en,
lsu_source1_rd_en,
lsu_source2_rd_en;
input lsu_instr_done, simd0_rd_en, simd1_rd_en, simd2_rd_en,
simd3_rd_en, simd0_wr_en, simd1_wr_en, simd2_wr_en, simd3_wr_en, simf0_rd_en,
simf1_rd_en, simf2_rd_en, simf3_rd_en, simf0_wr_en, simf1_wr_en, simf2_wr_en,
simf3_wr_en, salu_instr_done;
input [1:0] salu_dest_wr_en;
input [3:0] lsu_dest_wr_en;
input [5:0] lsu_instr_done_wfid, salu_instr_done_wfid;
input [8:0] lsu_source1_addr, lsu_source2_addr, lsu_dest_addr, simd0_rd_addr,
simd1_rd_addr, simd2_rd_addr, simd3_rd_addr, simd0_wr_addr, simd1_wr_addr,
simd2_wr_addr, simd3_wr_addr, simf0_rd_addr, simf1_rd_addr, simf2_rd_addr,
simf3_rd_addr, simf0_wr_addr, simf1_wr_addr, simf2_wr_addr, simf3_wr_addr,
salu_dest_addr, salu_source2_addr, salu_source1_addr;
input [15:0] rfa_select_fu;
input [127:0] lsu_dest_data;
input [63:0] simd0_wr_data, simd1_wr_data, simd2_wr_data, simd3_wr_data,
simf0_wr_data, simf1_wr_data, simf2_wr_data, simf3_wr_data,
salu_dest_data,
simd0_wr_mask, simd1_wr_mask, simd2_wr_mask, simd3_wr_mask,
simf0_wr_mask, simf1_wr_mask, simf2_wr_mask, simf3_wr_mask;
output issue_alu_wr_done, issue_lsu_instr_done, issue_valu_dest_reg_valid;
output [3:0] issue_lsu_dest_reg_valid;
output [1:0] issue_alu_dest_reg_valid;
output [5:0] issue_alu_wr_done_wfid, issue_lsu_instr_done_wfid;
output [8:0] issue_alu_dest_reg_addr, issue_lsu_dest_reg_addr, issue_valu_dest_addr;
output [31:0] lsu_source2_data, simd_rd_data, simf_rd_data;
output [63:0] salu_source2_data, salu_source1_data;
output [127:0] lsu_source1_data;
///////////////////////////////
//Your code goes here - beware: script does not recognize changes
// into files. It ovewrites everithing without mercy. Save your work before running the script
///////////////////////////////
wire dummy;
assign dummy = rst;
wire [31:0] simx_rd_data;
wire [8:0] simx_muxed_rd_addr;
wire [31:0] simx_muxed_rd_data;
wire simx_muxed_rd_en;
wire [3:0] simxlsu_muxed_wr_en;
wire [8:0] simxlsu_muxed_wr_addr;
wire [127:0] simxlsu_muxed_wr_data;
wire [63:0] simx_rd_old_data;
wire [127:0] simxlsu_wr_merged_data;
wire [127:0] simxlsu_muxed_wr_mask;
wire [3:0] simxlsu_muxed_wr_en_i;
wire [8:0] simxlsu_muxed_wr_addr_i;
wire [127:0] simxlsu_muxed_wr_data_i;
wire [127:0] simxlsu_muxed_wr_mask_i;
wire [8:0] final_port0_addr;
wire [8:0] final_port1_addr;
wire [127:0] final_port0_data;
wire [63:0] final_port1_data;
wire [127:0] port0_distribute_data;
wire [127:0] port1_distribute_data;
wire [127:0] simd0_wr_data_i, simd1_wr_data_i, simd2_wr_data_i, simd3_wr_data_i,
simf0_wr_data_i, simf1_wr_data_i, simf2_wr_data_i, simf3_wr_data_i;
wire [127:0] simd0_wr_mask_i, simd1_wr_mask_i, simd2_wr_mask_i, simd3_wr_mask_i,
simf0_wr_mask_i, simf1_wr_mask_i, simf2_wr_mask_i, simf3_wr_mask_i;
wire [3:0] simd0_wr_en_i, simd1_wr_en_i, simd2_wr_en_i, simd3_wr_en_i,
simf0_wr_en_i, simf1_wr_en_i, simf2_wr_en_i, simf3_wr_en_i;
assign simd0_wr_data_i = {simd0_wr_data, simd0_wr_data};
assign simd1_wr_data_i = {simd1_wr_data, simd1_wr_data};
assign simd2_wr_data_i = {simd2_wr_data, simd2_wr_data};
assign simd3_wr_data_i = {simd3_wr_data, simd3_wr_data};
assign simf0_wr_data_i = {simf0_wr_data, simf0_wr_data};
assign simf1_wr_data_i = {simf1_wr_data, simf1_wr_data};
assign simf2_wr_data_i = {simf2_wr_data, simf2_wr_data};
assign simf3_wr_data_i = {simf3_wr_data, simf3_wr_data};
assign simd0_wr_mask_i = {simd0_wr_mask, simd0_wr_mask};
assign simd1_wr_mask_i = {simd1_wr_mask, simd1_wr_mask};
assign simd2_wr_mask_i = {simd2_wr_mask, simd2_wr_mask};
assign simd3_wr_mask_i = {simd3_wr_mask, simd3_wr_mask};
assign simf0_wr_mask_i = {simf0_wr_mask, simf0_wr_mask};
assign simf1_wr_mask_i = {simf1_wr_mask, simf1_wr_mask};
assign simf2_wr_mask_i = {simf2_wr_mask, simf2_wr_mask};
assign simf3_wr_mask_i = {simf3_wr_mask, simf3_wr_mask};
assign simd0_wr_en_i = {4{simd0_wr_en}} & 4'b0011;
assign simd1_wr_en_i = {4{simd1_wr_en}} & 4'b0011;
assign simd2_wr_en_i = {4{simd2_wr_en}} & 4'b0011;
assign simd3_wr_en_i = {4{simd3_wr_en}} & 4'b0011;
assign simf0_wr_en_i = {4{simf0_wr_en}} & 4'b0011;
assign simf1_wr_en_i = {4{simf1_wr_en}} & 4'b0011;
assign simf2_wr_en_i = {4{simf2_wr_en}} & 4'b0011;
assign simf3_wr_en_i = {4{simf3_wr_en}} & 4'b0011;
assign issue_alu_wr_done_wfid = salu_instr_done_wfid;
assign issue_alu_wr_done = salu_instr_done;
assign issue_alu_dest_reg_addr = salu_dest_addr;
assign issue_alu_dest_reg_valid = salu_dest_wr_en;
assign issue_lsu_instr_done_wfid = lsu_instr_done_wfid;
assign issue_lsu_instr_done = lsu_instr_done;
assign issue_lsu_dest_reg_addr = lsu_dest_addr;
assign issue_lsu_dest_reg_valid = lsu_dest_wr_en;
//For writes from simx, read the old value using a ead port and modify only
//the bits specified by the wr mask
assign simxlsu_wr_merged_data = (simxlsu_muxed_wr_data_i &
simxlsu_muxed_wr_mask_i) |
({2{simx_rd_old_data}} &
(~simxlsu_muxed_wr_mask_i));
dff wr0_delay_flop[4+9+128+128-1:0]
(.q({simxlsu_muxed_wr_en_i, simxlsu_muxed_wr_addr_i,
simxlsu_muxed_wr_data_i,simxlsu_muxed_wr_mask_i}),
.d({simxlsu_muxed_wr_en, simxlsu_muxed_wr_addr,
simxlsu_muxed_wr_data,simxlsu_muxed_wr_mask}),
.clk(clk),
.rst(rst));
reg_512x32b_3r_2w sgpr_reg_file
(
.rd0_addr(final_port0_addr),
.rd0_data(final_port0_data),
.rd1_addr(final_port1_addr),
.rd1_data(final_port1_data),
.rd2_addr(simxlsu_muxed_wr_addr),
.rd2_data(simx_rd_old_data),
.wr0_en(simxlsu_muxed_wr_en_i),
.wr0_addr(simxlsu_muxed_wr_addr_i),
.wr0_data(simxlsu_wr_merged_data),
.wr1_en(salu_dest_wr_en),
.wr1_addr(salu_dest_addr),
.wr1_data(salu_dest_data),
.clk(clk)
`ifdef FPGA
,.clk_double(clk_double)
`endif
);
sgpr_simx_rd_port_mux simx_rd_port_mux
(
.port0_rd_en(simd0_rd_en),
.port0_rd_addr(simd0_rd_addr),
.port1_rd_en(simd1_rd_en),
.port1_rd_addr(simd1_rd_addr),
.port2_rd_en(simd2_rd_en),
.port2_rd_addr(simd2_rd_addr),
.port3_rd_en(simd3_rd_en),
.port3_rd_addr(simd3_rd_addr),
.port4_rd_en(simf0_rd_en),
.port4_rd_addr(simf0_rd_addr),
.port5_rd_en(simf1_rd_en),
.port5_rd_addr(simf1_rd_addr),
.port6_rd_en(simf2_rd_en),
.port6_rd_addr(simf2_rd_addr),
.port7_rd_en(simf3_rd_en),
.port7_rd_addr(simf3_rd_addr),
.port_rd_data(simx_rd_data),
.rd_addr(simx_muxed_rd_addr),
.rd_data(simx_muxed_rd_data),
.rd_en(simx_muxed_rd_en)
);
assign simd_rd_data = simx_rd_data;
assign simf_rd_data = simx_rd_data;
sgpr_3to1_rd_port_mux rd_port0_mux
(
.port0_rd_en(lsu_source1_rd_en),
.port0_rd_addr(lsu_source1_addr),
.port1_rd_en(1'b0),
.port1_rd_addr(9'b0),
.port2_rd_en(salu_source1_rd_en),
.port2_rd_addr(salu_source1_addr),
.port_rd_data(port0_distribute_data),
.rd_addr(final_port0_addr),
.rd_data(final_port0_data)
);
assign lsu_source1_data = port0_distribute_data;
assign salu_source1_data = port0_distribute_data[63:0];
sgpr_3to1_rd_port_mux rd_port1_mux
(
.port0_rd_en(lsu_source2_rd_en),
.port0_rd_addr(lsu_source2_addr),
.port1_rd_en(simx_muxed_rd_en),
.port1_rd_addr(simx_muxed_rd_addr),
.port2_rd_en(salu_source2_rd_en),
.port2_rd_addr(salu_source2_addr),
.port_rd_data(port1_distribute_data),
.rd_addr(final_port1_addr),
.rd_data({64'b0,final_port1_data})
);
assign lsu_source2_data = port1_distribute_data[31:0];
assign simx_muxed_rd_data = port1_distribute_data[31:0];
assign salu_source2_data = port1_distribute_data[63:0];
///////////////////////////////////////////
sgpr_simxlsu_wr_port_mux simx_wr_port_mux
(
.wr_port_select(rfa_select_fu),
.port0_wr_en(simd0_wr_en_i),
.port0_wr_addr(simd0_wr_addr),
.port0_wr_data(simd0_wr_data_i),
.port0_wr_mask(simd0_wr_mask_i),
.port1_wr_en(simd1_wr_en_i),
.port1_wr_addr(simd1_wr_addr),
.port1_wr_data(simd1_wr_data_i),
.port1_wr_mask(simd1_wr_mask_i),
.port2_wr_en(simd2_wr_en_i),
.port2_wr_addr(simd2_wr_addr),
.port2_wr_data(simd2_wr_data_i),
.port2_wr_mask(simd2_wr_mask_i),
.port3_wr_en(simd3_wr_en_i),
.port3_wr_addr(simd3_wr_addr),
.port3_wr_data(simd3_wr_data_i),
.port3_wr_mask(simd3_wr_mask_i),
.port4_wr_en(simf0_wr_en_i),
.port4_wr_addr(simf0_wr_addr),
.port4_wr_data(simf0_wr_data_i),
.port4_wr_mask(simf0_wr_mask_i),
.port5_wr_en(simf1_wr_en_i),
.port5_wr_addr(simf1_wr_addr),
.port5_wr_data(simf1_wr_data_i),
.port5_wr_mask(simf1_wr_mask_i),
.port6_wr_en(simf2_wr_en_i),
.port6_wr_addr(simf2_wr_addr),
.port6_wr_data(simf2_wr_data_i),
.port6_wr_mask(simf2_wr_mask_i),
.port7_wr_en(simf3_wr_en_i),
.port7_wr_addr(simf3_wr_addr),
.port7_wr_data(simf3_wr_data_i),
.port7_wr_mask(simf3_wr_mask_i),
.port8_wr_en(lsu_dest_wr_en),
.port8_wr_addr(lsu_dest_addr),
.port8_wr_data(lsu_dest_data),
.port8_wr_mask({128{1'b1}}),
.muxed_port_wr_en(simxlsu_muxed_wr_en),
.muxed_port_wr_addr(simxlsu_muxed_wr_addr),
.muxed_port_wr_data(simxlsu_muxed_wr_data),
.muxed_port_wr_mask(simxlsu_muxed_wr_mask)
);
assign issue_valu_dest_reg_valid = (|simxlsu_muxed_wr_en) & (~|lsu_dest_wr_en);
assign issue_valu_dest_addr = simxlsu_muxed_wr_addr;
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized COMPARATOR with generic_baseblocks_v2_1_carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_comparator_sel_mask #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire S,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] B,
input wire [C_DATA_WIDTH-1:0] M,
input wire [C_DATA_WIDTH-1:0] V,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar lut_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 1;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_FIX_DATA_WIDTH-1:0] m_local;
wire [C_FIX_DATA_WIDTH-1:0] v_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign m_local = {M, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign v_local = {V, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = B;
assign m_local = M;
assign v_local = V;
end
// Instantiate one generic_baseblocks_v2_1_carry and per level.
for (lut_cnt = 0; lut_cnt < C_NUM_LUT ; lut_cnt = lut_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[lut_cnt] = ( ( ( a_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ==
( v_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ) & ( S == 1'b0 ) ) |
( ( ( b_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ==
( v_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ) & ( S == 1'b1 ) );
// Instantiate each LUT level.
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[lut_cnt+1]),
.CIN (carry_local[lut_cnt]),
.S (sel[lut_cnt])
);
end // end for lut_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:00:08 11/01/2013
// Design Name: divider
// Module Name: C:/Users/Fabian/Documents/GitHub/taller-diseno-digital/Proyecto Final/proyecto-final/divider_test.v
// Project Name: proyecto-final
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: divider
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module divider_test;
// Inputs
reg in;
reg [3:0] N;
reg reset;
// Outputs
wire out;
// Instantiate the Unit Under Test (UUT)
divider uut (
.in(in),
.out(out),
.N(N),
.reset(reset)
);
initial begin
// Initialize Inputs
in = 0;
N = 0;
reset = 1;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
N = 2;
#1000;
reset = 0;
end
endmodule
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