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//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : PCIeGen2x8If128_qpll_drp.v
// Version : 3.2
//------------------------------------------------------------------------------
// Filename : qpll_drp.v
// Description : QPLL DRP Module for 7 Series Transceiver
// Version : 18.2
//------------------------------------------------------------------------------
`timescale 1ns / 1ps
//---------- QPLL DRP Module ---------------------------------------------------
(* DowngradeIPIdentifiedWarnings = "yes" *)
module PCIeGen2x8If128_qpll_drp #
(
parameter PCIE_GT_DEVICE = "GTX", // PCIe GT device
parameter PCIE_USE_MODE = "3.0", // PCIe use mode
parameter PCIE_PLL_SEL = "CPLL", // PCIe PLL select for Gen1/Gen2 only
parameter PCIE_REFCLK_FREQ = 0, // PCIe reference clock frequency
parameter LOAD_CNT_MAX = 2'd3, // Load max count
parameter INDEX_MAX = 3'd6 // Index max count
)
(
//---------- Input -------------------------------------
input DRP_CLK,
input DRP_RST_N,
input DRP_OVRD,
input DRP_GEN3,
input DRP_QPLLLOCK,
input DRP_START,
input [15:0] DRP_DO,
input DRP_RDY,
//---------- Output ------------------------------------
output [ 7:0] DRP_ADDR,
output DRP_EN,
output [15:0] DRP_DI,
output DRP_WE,
output DRP_DONE,
output DRP_QPLLRESET,
output [ 5:0] DRP_CRSCODE,
output [ 8:0] DRP_FSM
);
//---------- Input Registers ---------------------------
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg ovrd_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gen3_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg qplllock_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg start_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [15:0] do_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rdy_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg ovrd_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gen3_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg qplllock_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg start_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [15:0] do_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rdy_reg2;
//---------- Internal Signals --------------------------
reg [ 1:0] load_cnt = 2'd0;
reg [ 2:0] index = 3'd0;
reg mode = 1'd0;
reg [ 5:0] crscode = 6'd0;
//---------- Output Registers --------------------------
reg [ 7:0] addr = 8'd0;
reg [15:0] di = 16'd0;
reg done = 1'd0;
reg [ 8:0] fsm = 7'd1;
//---------- DRP Address -------------------------------
localparam ADDR_QPLL_FBDIV = 8'h36;
localparam ADDR_QPLL_CFG = 8'h32;
localparam ADDR_QPLL_LPF = 8'h31;
localparam ADDR_CRSCODE = 8'h88;
localparam ADDR_QPLL_COARSE_FREQ_OVRD = 8'h35;
localparam ADDR_QPLL_COARSE_FREQ_OVRD_EN = 8'h36;
localparam ADDR_QPLL_LOCK_CFG = 8'h34;
//---------- DRP Mask ----------------------------------
localparam MASK_QPLL_FBDIV = 16'b1111110000000000; // Unmask bit [ 9: 0]
localparam MASK_QPLL_CFG = 16'b1111111110111111; // Unmask bit [ 6]
localparam MASK_QPLL_LPF = 16'b1000011111111111; // Unmask bit [14:11]
localparam MASK_QPLL_COARSE_FREQ_OVRD = 16'b0000001111111111; // Unmask bit [15:10]
localparam MASK_QPLL_COARSE_FREQ_OVRD_EN = 16'b1111011111111111; // Unmask bit [ 11]
localparam MASK_QPLL_LOCK_CFG = 16'b1110011111111111; // Unmask bit [12:11]
//---------- DRP Data for Normal QPLLLOCK Mode ---------
localparam NORM_QPLL_COARSE_FREQ_OVRD = 16'b0000000000000000; // Coarse freq value
localparam NORM_QPLL_COARSE_FREQ_OVRD_EN = 16'b0000000000000000; // Normal QPLL lock
localparam NORM_QPLL_LOCK_CFG = 16'b0000000000000000; // Normal QPLL lock config
//---------- DRP Data for Optimize QPLLLOCK Mode -------
localparam OVRD_QPLL_COARSE_FREQ_OVRD = 16'b0000000000000000; // Coarse freq value
localparam OVRD_QPLL_COARSE_FREQ_OVRD_EN = 16'b0000100000000000; // Override QPLL lock
localparam OVRD_QPLL_LOCK_CFG = 16'b0000000000000000; // Override QPLL lock config
//---------- Select QPLL Feedback Divider --------------
// N = 100 for 100 MHz ref clk and 10Gb/s line rate
// N = 80 for 125 MHz ref clk and 10Gb/s line rate
// N = 40 for 250 MHz ref clk and 10Gb/s line rate
//------------------------------------------------------
// N = 80 for 100 MHz ref clk and 8Gb/s line rate
// N = 64 for 125 MHz ref clk and 8Gb/s line rate
// N = 32 for 250 MHz ref clk and 8Gb/s line rate
//------------------------------------------------------
localparam QPLL_FBDIV = (PCIE_REFCLK_FREQ == 2) && (PCIE_PLL_SEL == "QPLL") ? 16'b0000000010000000 :
(PCIE_REFCLK_FREQ == 1) && (PCIE_PLL_SEL == "QPLL") ? 16'b0000000100100000 :
(PCIE_REFCLK_FREQ == 0) && (PCIE_PLL_SEL == "QPLL") ? 16'b0000000101110000 :
(PCIE_REFCLK_FREQ == 2) && (PCIE_PLL_SEL == "CPLL") ? 16'b0000000001100000 :
(PCIE_REFCLK_FREQ == 1) && (PCIE_PLL_SEL == "CPLL") ? 16'b0000000011100000 : 16'b0000000100100000;
localparam GEN12_QPLL_FBDIV = (PCIE_REFCLK_FREQ == 2) ? 16'b0000000010000000 :
(PCIE_REFCLK_FREQ == 1) ? 16'b0000000100100000 : 16'b0000000101110000;
localparam GEN3_QPLL_FBDIV = (PCIE_REFCLK_FREQ == 2) ? 16'b0000000001100000 :
(PCIE_REFCLK_FREQ == 1) ? 16'b0000000011100000 : 16'b0000000100100000;
//---------- Select QPLL Configuration ---------------------------
// QPLL_CFG[6] = 0 for upper band
// = 1 for lower band
//----------------------------------------------------------------
localparam GEN12_QPLL_CFG = (PCIE_PLL_SEL == "QPLL") ? 16'b0000000000000000 : 16'b0000000001000000;
localparam GEN3_QPLL_CFG = 16'b0000000001000000;
//---------- Select QPLL LPF -------------------------------------
localparam GEN12_QPLL_LPF = (PCIE_PLL_SEL == "QPLL") ? 16'b0_0100_00000000000 : 16'b0_1101_00000000000;
localparam GEN3_QPLL_LPF = 16'b0_1101_00000000000;
//---------- DRP Data ----------------------------------
wire [15:0] data_qpll_fbdiv;
wire [15:0] data_qpll_cfg;
wire [15:0] data_qpll_lpf;
wire [15:0] data_qpll_coarse_freq_ovrd;
wire [15:0] data_qpll_coarse_freq_ovrd_en;
wire [15:0] data_qpll_lock_cfg;
//---------- FSM ---------------------------------------
localparam FSM_IDLE = 9'b000000001;
localparam FSM_LOAD = 9'b000000010;
localparam FSM_READ = 9'b000000100;
localparam FSM_RRDY = 9'b000001000;
localparam FSM_WRITE = 9'b000010000;
localparam FSM_WRDY = 9'b000100000;
localparam FSM_DONE = 9'b001000000;
localparam FSM_QPLLRESET = 9'b010000000;
localparam FSM_QPLLLOCK = 9'b100000000;
//---------- Input FF ----------------------------------------------------------
always @ (posedge DRP_CLK)
begin
if (!DRP_RST_N)
begin
//---------- 1st Stage FF --------------------------
ovrd_reg1 <= 1'd0;
gen3_reg1 <= 1'd0;
qplllock_reg1 <= 1'd0;
start_reg1 <= 1'd0;
do_reg1 <= 16'd0;
rdy_reg1 <= 1'd0;
//---------- 2nd Stage FF --------------------------
ovrd_reg2 <= 1'd0;
gen3_reg2 <= 1'd0;
qplllock_reg2 <= 1'd0;
start_reg2 <= 1'd0;
do_reg2 <= 16'd0;
rdy_reg2 <= 1'd0;
end
else
begin
//---------- 1st Stage FF --------------------------
ovrd_reg1 <= DRP_OVRD;
gen3_reg1 <= DRP_GEN3;
qplllock_reg1 <= DRP_QPLLLOCK;
start_reg1 <= DRP_START;
do_reg1 <= DRP_DO;
rdy_reg1 <= DRP_RDY;
//---------- 2nd Stage FF --------------------------
ovrd_reg2 <= ovrd_reg1;
gen3_reg2 <= gen3_reg1;
qplllock_reg2 <= qplllock_reg1;
start_reg2 <= start_reg1;
do_reg2 <= do_reg1;
rdy_reg2 <= rdy_reg1;
end
end
//---------- Select DRP Data ---------------------------------------------------
assign data_qpll_fbdiv = (gen3_reg2) ? GEN3_QPLL_FBDIV : GEN12_QPLL_FBDIV;
assign data_qpll_cfg = (gen3_reg2) ? GEN3_QPLL_CFG : GEN12_QPLL_CFG;
assign data_qpll_lpf = (gen3_reg2) ? GEN3_QPLL_LPF : GEN12_QPLL_LPF;
assign data_qpll_coarse_freq_ovrd = NORM_QPLL_COARSE_FREQ_OVRD;
assign data_qpll_coarse_freq_ovrd_en = (ovrd_reg2) ? OVRD_QPLL_COARSE_FREQ_OVRD_EN : NORM_QPLL_COARSE_FREQ_OVRD_EN;
assign data_qpll_lock_cfg = (ovrd_reg2) ? OVRD_QPLL_LOCK_CFG : NORM_QPLL_LOCK_CFG;
//---------- Load Counter ------------------------------------------------------
always @ (posedge DRP_CLK)
begin
if (!DRP_RST_N)
load_cnt <= 2'd0;
else
//---------- Increment Load Counter ----------------
if ((fsm == FSM_LOAD) && (load_cnt < LOAD_CNT_MAX))
load_cnt <= load_cnt + 2'd1;
//---------- Hold Load Counter ---------------------
else if ((fsm == FSM_LOAD) && (load_cnt == LOAD_CNT_MAX))
load_cnt <= load_cnt;
//---------- Reset Load Counter --------------------
else
load_cnt <= 2'd0;
end
//---------- Update DRP Address and Data ---------------------------------------
always @ (posedge DRP_CLK)
begin
if (!DRP_RST_N)
begin
addr <= 8'd0;
di <= 16'd0;
crscode <= 6'd0;
end
else
begin
case (index)
//--------------------------------------------------
3'd0 :
begin
addr <= ADDR_QPLL_FBDIV;
di <= (do_reg2 & MASK_QPLL_FBDIV) | (mode ? data_qpll_fbdiv : QPLL_FBDIV);
crscode <= crscode;
end
//--------------------------------------------------
3'd1 :
begin
addr <= ADDR_QPLL_CFG;
if (PCIE_GT_DEVICE == "GTX")
di <= (do_reg2 & MASK_QPLL_CFG) | data_qpll_cfg;
else
di <= (do_reg2 & 16'hFFFF) | data_qpll_cfg;
crscode <= crscode;
end
//--------------------------------------------------
3'd2 :
begin
addr <= ADDR_QPLL_LPF;
if (PCIE_GT_DEVICE == "GTX")
di <= (do_reg2 & MASK_QPLL_LPF) | data_qpll_lpf;
else
di <= (do_reg2 & 16'hFFFF) | data_qpll_lpf;
crscode <= crscode;
end
//--------------------------------------------------
3'd3 :
begin
addr <= ADDR_CRSCODE;
di <= do_reg2;
//---------- Latch CRS Code --------------------
if (ovrd_reg2)
crscode <= do_reg2[6:1];
else
crscode <= crscode;
end
//--------------------------------------------------
3'd4 :
begin
addr <= ADDR_QPLL_COARSE_FREQ_OVRD;
di <= (do_reg2 & MASK_QPLL_COARSE_FREQ_OVRD) | {(crscode - 6'd1), data_qpll_coarse_freq_ovrd[9:0]};
crscode <= crscode;
end
//--------------------------------------------------
3'd5 :
begin
addr <= ADDR_QPLL_COARSE_FREQ_OVRD_EN;
di <= (do_reg2 & MASK_QPLL_COARSE_FREQ_OVRD_EN) | data_qpll_coarse_freq_ovrd_en;
crscode <= crscode;
end
//--------------------------------------------------
3'd6 :
begin
addr <= ADDR_QPLL_LOCK_CFG;
di <= (do_reg2 & MASK_QPLL_LOCK_CFG) | data_qpll_lock_cfg;
crscode <= crscode;
end
//--------------------------------------------------
default :
begin
addr <= 8'd0;
di <= 16'd0;
crscode <= 6'd0;
end
endcase
end
end
//---------- QPLL DRP FSM ------------------------------------------------------
always @ (posedge DRP_CLK)
begin
if (!DRP_RST_N)
begin
fsm <= FSM_IDLE;
index <= 3'd0;
mode <= 1'd0;
done <= 1'd0;
end
else
begin
case (fsm)
//---------- Idle State ----------------------------
FSM_IDLE :
begin
if (start_reg2)
begin
fsm <= FSM_LOAD;
index <= 3'd0;
mode <= 1'd0;
done <= 1'd0;
end
else if ((gen3_reg2 != gen3_reg1) && (PCIE_PLL_SEL == "QPLL"))
begin
fsm <= FSM_LOAD;
index <= 3'd0;
mode <= 1'd1;
done <= 1'd0;
end
else
begin
fsm <= FSM_IDLE;
index <= 3'd0;
mode <= 1'd0;
done <= 1'd1;
end
end
//---------- Load DRP Address ---------------------
FSM_LOAD :
begin
fsm <= (load_cnt == LOAD_CNT_MAX) ? FSM_READ : FSM_LOAD;
index <= index;
mode <= mode;
done <= 1'd0;
end
//---------- Read DRP ------------------------------
FSM_READ :
begin
fsm <= FSM_RRDY;
index <= index;
mode <= mode;
done <= 1'd0;
end
//---------- Read DRP Ready ------------------------
FSM_RRDY :
begin
fsm <= (rdy_reg2 ? FSM_WRITE : FSM_RRDY);
index <= index;
mode <= mode;
done <= 1'd0;
end
//---------- Write DRP -----------------------------
FSM_WRITE :
begin
fsm <= FSM_WRDY;
index <= index;
mode <= mode;
done <= 1'd0;
end
//---------- Write DRP Ready -----------------------
FSM_WRDY :
begin
fsm <= (rdy_reg2 ? FSM_DONE : FSM_WRDY);
index <= index;
mode <= mode;
done <= 1'd0;
end
//---------- DRP Done ------------------------------
FSM_DONE :
begin
if ((index == INDEX_MAX) || (mode && (index == 3'd2)))
begin
fsm <= mode ? FSM_QPLLRESET : FSM_IDLE;
index <= 3'd0;
mode <= mode;
done <= 1'd0;
end
else
begin
fsm <= FSM_LOAD;
index <= index + 3'd1;
mode <= mode;
done <= 1'd0;
end
end
//---------- QPLL Reset ----------------------------
FSM_QPLLRESET :
begin
fsm <= !qplllock_reg2 ? FSM_QPLLLOCK : FSM_QPLLRESET;
index <= 3'd0;
mode <= mode;
done <= 1'd0;
end
//---------- QPLL Reset ----------------------------
FSM_QPLLLOCK :
begin
fsm <= qplllock_reg2 ? FSM_IDLE : FSM_QPLLLOCK;
index <= 3'd0;
mode <= mode;
done <= 1'd0;
end
//---------- Default State -------------------------
default :
begin
fsm <= FSM_IDLE;
index <= 3'd0;
mode <= 1'd0;
done <= 1'd0;
end
endcase
end
end
//---------- QPLL DRP Output ---------------------------------------------------
assign DRP_ADDR = addr;
assign DRP_EN = (fsm == FSM_READ) || (fsm == FSM_WRITE);
assign DRP_DI = di;
assign DRP_WE = (fsm == FSM_WRITE); // || (fsm == FSM_WRDY);
assign DRP_DONE = done;
assign DRP_QPLLRESET = (fsm == FSM_QPLLRESET);
assign DRP_CRSCODE = crscode;
assign DRP_FSM = fsm;
endmodule
|
// Model of FIFO in Altera
module fifo_1c_4k ( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
parameter width = 32;
parameter depth = 4096;
//`define rd_req 0; // Set this to 0 for rd_ack, 1 for rd_req
input [31:0] data;
input wrreq;
input rdreq;
input rdclk;
input wrclk;
input aclr;
output [31:0] q;
output rdfull;
output rdempty;
output [7:0] rdusedw;
output wrfull;
output wrempty;
output [7:0] wrusedw;
reg [width-1:0] mem [0:depth-1];
reg [7:0] rdptr;
reg [7:0] wrptr;
`ifdef rd_req
reg [width-1:0] q;
`else
wire [width-1:0] q;
`endif
reg [7:0] rdusedw;
reg [7:0] wrusedw;
integer i;
always @( aclr)
begin
wrptr <= #1 0;
rdptr <= #1 0;
for(i=0;i<depth;i=i+1)
mem[i] <= #1 0;
end
always @(posedge wrclk)
if(wrreq)
begin
wrptr <= #1 wrptr+1;
mem[wrptr] <= #1 data;
end
always @(posedge rdclk)
if(rdreq)
begin
rdptr <= #1 rdptr+1;
`ifdef rd_req
q <= #1 mem[rdptr];
`endif
end
`ifdef rd_req
`else
assign q = mem[rdptr];
`endif
// Fix these
always @(posedge wrclk)
wrusedw <= #1 wrptr - rdptr;
always @(posedge rdclk)
rdusedw <= #1 wrptr - rdptr;
endmodule // fifo_1c_4k
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2006 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=0;
reg [63:0] crc;
integer i;
reg [63:0] mem [7:0];
always @ (posedge clk) begin
if (cyc==1) begin
for (i=0; i<8; i=i+1) begin
mem[i] <= 64'h0;
end
end
else begin
mem[0] <= crc;
for (i=1; i<8; i=i+1) begin
mem[i] <= mem[i-1];
end
end
end
wire [63:0] outData = mem[7];
always @ (posedge clk) begin
//$write("[%0t] cyc==%0d crc=%b q=%x\n",$time, cyc, crc, outData);
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc==90) begin
if (outData != 64'h1265e3bddcd9bc27) $stop;
end
else if (cyc==91) begin
if (outData != 64'h24cbc77bb9b3784e) $stop;
end
else if (cyc==92) begin
end
else if (cyc==93) begin
end
else if (cyc==94) begin
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2015/03/12 11:16:23
// Design Name:
// Module Name: output_port_lookup_reg_master
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
/*
lut_actions_tmp[31:0] = reg_data;
lut_actions_tmp[63:32] = reg_data;
lut_actions_tmp[95:64] = reg_data;
lut_actions_tmp[127:96] = reg_data;
lut_actions_tmp[159:128] = reg_data;
lut_actions_tmp[191:160] = reg_data;
lut_actions_tmp[223:192] = reg_data;
lut_actions_tmp[255:224] = reg_data;
lut_actions_tmp[287:256] = reg_data;
lut_actions_tmp[319:288] = reg_data;
cam_data[prio][31:0] = reg_data;
cam_data[prio][63:32] = reg_data;
cam_data[prio][95:64] = reg_data;
cam_data_mask[prio][31:0] = reg_data;
cam_data_mask[prio][63:32] = reg_data;
cam_data_mask[prio][95:64] = reg_data;
cam_data_mask[prio][95:64] = reg_data;*/
//////////////////////////////////////////////////////////////////////////////////
module output_port_lookup_reg_master#
(
parameter CMP_WIDTH=64,
parameter LUT_DEPTH=16,
parameter LUT_DEPTH_BITS=log2(LUT_DEPTH),
parameter TABLE_NUM=2,
parameter CURRENT_TABLE_ID=0
)
(
input [31:0] data_output_port_lookup_i,
input [31:0] addr_output_port_lookup_i,
input req_output_port_lookup_i,
input rw_output_port_lookup_i,
output reg ack_output_port_lookup_o,
output reg[31:0] data_output_port_lookup_o,
output reg bram_cs,
output reg bram_we,
output reg [`PRIO_WIDTH-1:0]bram_addr,
output reg [319:0]lut_actions_in,
input [319:0]lut_actions_out,
output reg[`PRIO_WIDTH-1:0] tcam_addr_out,
output reg [CMP_WIDTH+31:0] tcam_data_out,
output reg [CMP_WIDTH-1:0] tcam_data_mask_out,
output reg tcam_we,
input [CMP_WIDTH+31:0] tcam_data_in,
input [CMP_WIDTH-1:0] tcam_data_mask_in,
output reg [LUT_DEPTH_BITS-1:0] counter_addr_out,
output reg counter_addr_rd,
input [31:0]pkt_counter_in,
input [31:0]byte_counter_in,
output reg[7:0] head_combine,
input clk,
input reset
);
function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction // log2
reg [`OPENFLOW_ACTION_WIDTH-1:0] lut_actions_tmp;
reg [CMP_WIDTH+31:0] tcam_data_tmp;
reg [CMP_WIDTH-1:0] tcam_data_mask_tmp;
reg [LUT_DEPTH_BITS-1:0]clear_count;
reg [3:0]deconcentrator_flag;
reg [4:0]cur_st,nxt_st;
localparam IDLE=0,
DECON=1,
LUT=2,
TCAM=3,
HEAD=4,
COUNTER=5,
COUNTER_ACK=6,
LUT_READ_PRE=7,
LUT_READ_RAM=8,
LUT_MOD_ACTION=9,
LUT_WRITE_RAM=10,
LUT_READ=11,
TCAM_MOD_DATA=12,
TCAM_WRITE_RAM=13,
TCAM_READ=14,
ACK_BLANK=15,
REG_DONE=16,
CLEAR=17;
always@(posedge clk)
if(reset) cur_st<=CLEAR;
else cur_st<=nxt_st;
always@(*)
begin
nxt_st=cur_st;
case(cur_st)
CLEAR:if(clear_count==LUT_DEPTH-1) nxt_st=IDLE;
IDLE:if(req_output_port_lookup_i) nxt_st=DECON;
DECON:
if(addr_output_port_lookup_i[`TABLE_ID_POS+`TABLE_ID_WIDTH-1:`TABLE_ID_POS]==CURRENT_TABLE_ID && addr_output_port_lookup_i[`PRIO_POS+`PRIO_WIDTH-1:`PRIO_POS]<LUT_DEPTH)
begin
if(deconcentrator_flag==`LUT_ACTION_TAG) nxt_st=LUT;
else if(deconcentrator_flag==`TCAM_TAG) nxt_st=TCAM;
else if(deconcentrator_flag==`HEAD_PARSER_TAG) nxt_st=HEAD;
else if(deconcentrator_flag==`FLOW_COUNTER) nxt_st=COUNTER;
else nxt_st=ACK_BLANK;
end
else nxt_st=ACK_BLANK;
LUT:nxt_st=LUT_READ_PRE;
LUT_READ_PRE:
if(rw_output_port_lookup_i==0)
nxt_st=LUT_MOD_ACTION;
else if(rw_output_port_lookup_i==1)
nxt_st=LUT_READ;
LUT_MOD_ACTION:nxt_st=LUT_WRITE_RAM;
LUT_WRITE_RAM:nxt_st=REG_DONE;
LUT_READ:nxt_st=REG_DONE;
TCAM:
if(rw_output_port_lookup_i==0)
nxt_st=TCAM_MOD_DATA;
else if(rw_output_port_lookup_i==1)
nxt_st=TCAM_READ;
TCAM_MOD_DATA:nxt_st= TCAM_WRITE_RAM;
TCAM_WRITE_RAM:nxt_st=REG_DONE;
TCAM_READ:nxt_st=REG_DONE;
COUNTER:nxt_st=COUNTER_ACK;
COUNTER_ACK:nxt_st=REG_DONE;
HEAD:nxt_st=REG_DONE;
ACK_BLANK:nxt_st=REG_DONE;
REG_DONE:nxt_st=IDLE;
default:nxt_st=IDLE;
endcase
end
always@(posedge clk)
if(reset)
clear_count<=0;
else if(cur_st==CLEAR)
clear_count<=clear_count+1;
always@(posedge clk)
if(cur_st==IDLE && req_output_port_lookup_i)
case(addr_output_port_lookup_i[`ACTION_POS+`ACTION_WIDTH-1:`ACTION_POS])
`OPENFLOW_WILDCARD_LOOKUP_ACTION_0_REG: deconcentrator_flag <= `LUT_ACTION_TAG;
`OPENFLOW_WILDCARD_LOOKUP_ACTION_1_REG: deconcentrator_flag <= `LUT_ACTION_TAG;
`OPENFLOW_WILDCARD_LOOKUP_ACTION_2_REG: deconcentrator_flag <= `LUT_ACTION_TAG;
`OPENFLOW_WILDCARD_LOOKUP_ACTION_3_REG: deconcentrator_flag <= `LUT_ACTION_TAG;
`OPENFLOW_WILDCARD_LOOKUP_ACTION_4_REG: deconcentrator_flag <= `LUT_ACTION_TAG;
`OPENFLOW_WILDCARD_LOOKUP_ACTION_5_REG: deconcentrator_flag <= `LUT_ACTION_TAG;
`OPENFLOW_WILDCARD_LOOKUP_ACTION_6_REG: deconcentrator_flag <= `LUT_ACTION_TAG;
`OPENFLOW_WILDCARD_LOOKUP_ACTION_7_REG: deconcentrator_flag <= `LUT_ACTION_TAG;
`OPENFLOW_WILDCARD_LOOKUP_ACTION_8_REG: deconcentrator_flag <= `LUT_ACTION_TAG;
`OPENFLOW_WILDCARD_LOOKUP_ACTION_9_REG: deconcentrator_flag <= `LUT_ACTION_TAG;
`OPENFLOW_WILDCARD_LOOKUP_CMP_0_REG: deconcentrator_flag <= `TCAM_TAG;
`OPENFLOW_WILDCARD_LOOKUP_CMP_1_REG: deconcentrator_flag <= `TCAM_TAG;
`OPENFLOW_WILDCARD_LOOKUP_CMP_2_REG: deconcentrator_flag <= `TCAM_TAG;
`OPENFLOW_WILDCARD_LOOKUP_CMP_MASK_0_REG: deconcentrator_flag <= `TCAM_TAG;
`OPENFLOW_WILDCARD_LOOKUP_CMP_MASK_1_REG: deconcentrator_flag <= `TCAM_TAG;
`OPENFLOW_WILDCARD_LOOKUP_CMP_MASK_2_REG: deconcentrator_flag <= `TCAM_TAG;
`OPENFLOW_WILDCARD_LOOKUP_HEAD_PARSER_REG: deconcentrator_flag <= `HEAD_PARSER_TAG;
`OPENFLOW_WILDCARD_LOOKUP_BYTE_COUNTER: deconcentrator_flag <= `FLOW_COUNTER;
`OPENFLOW_WILDCARD_LOOKUP_PKT_COUNTER: deconcentrator_flag <= `FLOW_COUNTER;
default:deconcentrator_flag<=4'hf;
endcase
else deconcentrator_flag <= 4'hf ;
always@(posedge clk)
if(reset)
lut_actions_tmp<=0;
else if(cur_st==LUT_MOD_ACTION)
begin
lut_actions_tmp=lut_actions_out;
case(addr_output_port_lookup_i[`ACTION_POS+`ACTION_WIDTH-1:`ACTION_POS])
`OPENFLOW_WILDCARD_LOOKUP_ACTION_0_REG: lut_actions_tmp[31:0] <=data_output_port_lookup_i;
`OPENFLOW_WILDCARD_LOOKUP_ACTION_1_REG: lut_actions_tmp[63:32] <=data_output_port_lookup_i;
`OPENFLOW_WILDCARD_LOOKUP_ACTION_2_REG: lut_actions_tmp[95:64] <=data_output_port_lookup_i;
`OPENFLOW_WILDCARD_LOOKUP_ACTION_3_REG: lut_actions_tmp[127:96] <=data_output_port_lookup_i;
`OPENFLOW_WILDCARD_LOOKUP_ACTION_4_REG: lut_actions_tmp[159:128] <=data_output_port_lookup_i;
`OPENFLOW_WILDCARD_LOOKUP_ACTION_5_REG: lut_actions_tmp[191:160] <=data_output_port_lookup_i;
`OPENFLOW_WILDCARD_LOOKUP_ACTION_6_REG: lut_actions_tmp[223:192] <=data_output_port_lookup_i;
`OPENFLOW_WILDCARD_LOOKUP_ACTION_7_REG: lut_actions_tmp[255:224] <=data_output_port_lookup_i;
`OPENFLOW_WILDCARD_LOOKUP_ACTION_8_REG: lut_actions_tmp[287:256] <=data_output_port_lookup_i;
`OPENFLOW_WILDCARD_LOOKUP_ACTION_9_REG: lut_actions_tmp[319:288] <=data_output_port_lookup_i;
default:lut_actions_tmp<=lut_actions_out;
endcase
end
always@(*)
if(reset) bram_cs=0;
else if(cur_st==CLEAR | cur_st==LUT | cur_st==LUT_WRITE_RAM) bram_cs=1;
else bram_cs=0;
always@(*)
if(reset) bram_we=0;
else if(cur_st==CLEAR | cur_st==LUT_WRITE_RAM) bram_we=1;
else bram_we=0;
always@(*)
if(reset) bram_addr=0;
else if(cur_st==CLEAR) bram_addr=clear_count;
else if(cur_st==LUT | cur_st==LUT_WRITE_RAM) bram_addr=addr_output_port_lookup_i[15:8];
else bram_addr=0;
always@(posedge clk)
lut_actions_in<=lut_actions_tmp;
always@(posedge clk)
if(reset)
ack_output_port_lookup_o<=0;
else if(cur_st==REG_DONE)
ack_output_port_lookup_o<=1;
else ack_output_port_lookup_o<=0;
always@(posedge clk)
if(reset)
tcam_addr_out<=0;
else if(cur_st==CLEAR)
tcam_addr_out<=clear_count;
else if(cur_st==TCAM | cur_st==TCAM_WRITE_RAM)
tcam_addr_out<=addr_output_port_lookup_i[`PRIO_WIDTH+`PRIO_POS-1:`PRIO_POS];
else tcam_addr_out<=0;
/*always@(*)
if(reset)
tcam_data_out=0;
else if(cur_st==TCAM_WRITE_RAM)
tcam_data_out=data_output_port_lookup_i;
else tcam_data_out=0;*/
always@(posedge clk)
if(reset)
tcam_we<=0;
else if(cur_st==TCAM_WRITE_RAM)
tcam_we<=1;
else tcam_we<=0;
always@(posedge clk)
if(reset)
tcam_data_out<=0;
else if(cur_st==TCAM_MOD_DATA)
tcam_data_out<=tcam_data_in;
else if(cur_st==TCAM_WRITE_RAM)
begin
if(CMP_WIDTH<=32)
case(addr_output_port_lookup_i[`ACTION_POS+`ACTION_WIDTH-1:`ACTION_POS])
`OPENFLOW_WILDCARD_LOOKUP_CMP_0_REG:tcam_data_out[31:0]<=data_output_port_lookup_i;
`OPENFLOW_WILDCARD_LOOKUP_CMP_1_REG:tcam_data_out[63:32]<=data_output_port_lookup_i;
default: tcam_data_out<=tcam_data_out;
endcase
else //(CMP_WIDTH<=64)
case(addr_output_port_lookup_i[`ACTION_POS+`ACTION_WIDTH-1:`ACTION_POS])
`OPENFLOW_WILDCARD_LOOKUP_CMP_0_REG:tcam_data_out[31:0]<=data_output_port_lookup_i;
`OPENFLOW_WILDCARD_LOOKUP_CMP_1_REG:tcam_data_out[63:32]<=data_output_port_lookup_i;
`OPENFLOW_WILDCARD_LOOKUP_CMP_2_REG:tcam_data_out[95:64]<=data_output_port_lookup_i;
default: tcam_data_out<=tcam_data_out;
endcase
end
always@(posedge clk)
if(reset)
tcam_data_mask_out<=0;
else if(cur_st==TCAM_MOD_DATA)
tcam_data_mask_out<=tcam_data_mask_in;
else if(cur_st==TCAM_WRITE_RAM)
begin
if(CMP_WIDTH<=32)
case(addr_output_port_lookup_i[`ACTION_POS+`ACTION_WIDTH-1:`ACTION_POS])
`OPENFLOW_WILDCARD_LOOKUP_CMP_MASK_0_REG:tcam_data_mask_out[31:0]<=data_output_port_lookup_i;
/*`OPENFLOW_WILDCARD_LOOKUP_CMP_MASK_1_REG:tcam_data_mask_out[63:32]<=data_output_port_lookup_i;
`OPENFLOW_WILDCARD_LOOKUP_CMP_MASK_2_REG:tcam_data_mask_out[95:64]<=data_output_port_lookup_i;*/
default: tcam_data_mask_out<=tcam_data_mask_out;
endcase
else
case(addr_output_port_lookup_i[`ACTION_POS+`ACTION_WIDTH-1:`ACTION_POS])
`OPENFLOW_WILDCARD_LOOKUP_CMP_MASK_0_REG:tcam_data_mask_out[31:0]<=data_output_port_lookup_i;
`OPENFLOW_WILDCARD_LOOKUP_CMP_MASK_1_REG:tcam_data_mask_out[63:32]<=data_output_port_lookup_i;
default: tcam_data_mask_out<=tcam_data_mask_out;
endcase
end
/*
`ifdef ONETS45
begin
always@(posedge clk)
if(reset)
data_output_port_lookup_o<=0;
else if(cur_st==LUT_READ)
case(addr_output_port_lookup_i[`ACTION_POS+`ACTION_WIDTH-1:`ACTION_POS])
`OPENFLOW_WILDCARD_LOOKUP_ACTION_0_REG: data_output_port_lookup_o<=lut_actions_out[31:0] ;
`OPENFLOW_WILDCARD_LOOKUP_ACTION_1_REG: data_output_port_lookup_o<=lut_actions_out[63:32] ;
`OPENFLOW_WILDCARD_LOOKUP_ACTION_2_REG: data_output_port_lookup_o<=lut_actions_out[95:64] ;
`OPENFLOW_WILDCARD_LOOKUP_ACTION_3_REG: data_output_port_lookup_o<=lut_actions_out[127:96] ;
`OPENFLOW_WILDCARD_LOOKUP_ACTION_4_REG: data_output_port_lookup_o<=lut_actions_out[159:128];
`OPENFLOW_WILDCARD_LOOKUP_ACTION_5_REG: data_output_port_lookup_o<=lut_actions_out[191:160];
`OPENFLOW_WILDCARD_LOOKUP_ACTION_6_REG: data_output_port_lookup_o<=lut_actions_out[223:192];
`OPENFLOW_WILDCARD_LOOKUP_ACTION_7_REG: data_output_port_lookup_o<=lut_actions_out[255:224];
`OPENFLOW_WILDCARD_LOOKUP_ACTION_8_REG: data_output_port_lookup_o<=lut_actions_out[287:256];
`OPENFLOW_WILDCARD_LOOKUP_ACTION_9_REG: data_output_port_lookup_o<=lut_actions_out[319:288];
default:data_output_port_lookup_o<=32'hdeadbeef;
endcase
else if(cur_st==TCAM_READ)
case(addr_output_port_lookup_i[`ACTION_POS+`ACTION_WIDTH-1:`ACTION_POS])
`OPENFLOW_WILDCARD_LOOKUP_CMP_MASK_0_REG:data_output_port_lookup_o<=tcam_data_in;
`OPENFLOW_WILDCARD_LOOKUP_CMP_MASK_1_REG:data_output_port_lookup_o<=tcam_data_in;
`OPENFLOW_WILDCARD_LOOKUP_CMP_MASK_2_REG:data_output_port_lookup_o<=tcam_data_in;
`OPENFLOW_WILDCARD_LOOKUP_CMP_0_REG:data_output_port_lookup_o<=tcam_data_in;
`OPENFLOW_WILDCARD_LOOKUP_CMP_1_REG:data_output_port_lookup_o<=tcam_data_in;
`OPENFLOW_WILDCARD_LOOKUP_CMP_2_REG:data_output_port_lookup_o<=tcam_data_in;
default: data_output_port_lookup_o<=32'hdeadbeef;
endcase
else if(cur_st==COUNTER_ACK)
case(addr_output_port_lookup_i[`ACTION_POS+`ACTION_WIDTH-1:`ACTION_POS])
`OPENFLOW_WILDCARD_LOOKUP_BYTE_COUNTER: data_output_port_lookup_o<=byte_counter_in;
`OPENFLOW_WILDCARD_LOOKUP_PKT_COUNTER: data_output_port_lookup_o<=pkt_counter_in;
default:data_output_port_lookup_o<=32'hdeadbeef;
endcase
else if(cur_st==HEAD)
data_output_port_lookup_o<=head_combine;
else if(cur_st==ACK_BLANK)
data_output_port_lookup_o<=32'hdeadbeef;
end
`elsif ONETS30
begin
always@(posedge clk)
if(reset)
data_output_port_lookup_o<=0;
else if(cur_st==LUT_READ)
case(addr_output_port_lookup_i[`ACTION_POS+`ACTION_WIDTH-1:`ACTION_POS])
`OPENFLOW_WILDCARD_LOOKUP_ACTION_0_REG: data_output_port_lookup_o<=lut_actions_out[31:0] ;
`OPENFLOW_WILDCARD_LOOKUP_ACTION_1_REG: data_output_port_lookup_o<=lut_actions_out[63:32] ;
`OPENFLOW_WILDCARD_LOOKUP_ACTION_2_REG: data_output_port_lookup_o<=lut_actions_out[95:64] ;
`OPENFLOW_WILDCARD_LOOKUP_ACTION_3_REG: data_output_port_lookup_o<=lut_actions_out[127:96] ;
`OPENFLOW_WILDCARD_LOOKUP_ACTION_4_REG: data_output_port_lookup_o<=lut_actions_out[159:128];
`OPENFLOW_WILDCARD_LOOKUP_ACTION_5_REG: data_output_port_lookup_o<=lut_actions_out[191:160];
`OPENFLOW_WILDCARD_LOOKUP_ACTION_6_REG: data_output_port_lookup_o<=lut_actions_out[223:192];
`OPENFLOW_WILDCARD_LOOKUP_ACTION_7_REG: data_output_port_lookup_o<=lut_actions_out[255:224];
`OPENFLOW_WILDCARD_LOOKUP_ACTION_8_REG: data_output_port_lookup_o<=lut_actions_out[287:256];
`OPENFLOW_WILDCARD_LOOKUP_ACTION_9_REG: data_output_port_lookup_o<=lut_actions_out[319:288];
default:data_output_port_lookup_o<=32'hdeadbeef;
endcase
else if(cur_st==TCAM_READ)
case(addr_output_port_lookup_i[`ACTION_POS+`ACTION_WIDTH-1:`ACTION_POS])
`OPENFLOW_WILDCARD_LOOKUP_CMP_MASK_0_REG:data_output_port_lookup_o<=tcam_data_in;
`OPENFLOW_WILDCARD_LOOKUP_CMP_MASK_1_REG:data_output_port_lookup_o<=tcam_data_in;
`OPENFLOW_WILDCARD_LOOKUP_CMP_MASK_2_REG:data_output_port_lookup_o<=tcam_data_in;
`OPENFLOW_WILDCARD_LOOKUP_CMP_0_REG:data_output_port_lookup_o<=tcam_data_in;
`OPENFLOW_WILDCARD_LOOKUP_CMP_1_REG:data_output_port_lookup_o<=tcam_data_in;
`OPENFLOW_WILDCARD_LOOKUP_CMP_2_REG:data_output_port_lookup_o<=tcam_data_in;
default: data_output_port_lookup_o<=32'hdeadbeef;
endcase
else if(cur_st==COUNTER_ACK)
case(addr_output_port_lookup_i[`ACTION_POS+`ACTION_WIDTH-1:`ACTION_POS])
`OPENFLOW_WILDCARD_LOOKUP_BYTE_COUNTER: data_output_port_lookup_o<=byte_counter_in;
`OPENFLOW_WILDCARD_LOOKUP_PKT_COUNTER: data_output_port_lookup_o<=pkt_counter_in;
default:data_output_port_lookup_o<=32'hdeadbeef;
endcase
else if(cur_st==HEAD)
data_output_port_lookup_o<=head_combine;
else if(cur_st==ACK_BLANK)
data_output_port_lookup_o<=32'hdeadbeef;
end
`elsif ONETS20
begin */
always@(posedge clk)
if(reset)
data_output_port_lookup_o<=0;
else if(cur_st==LUT_READ)
case(addr_output_port_lookup_i[`ACTION_POS+`ACTION_WIDTH-1:`ACTION_POS])
`OPENFLOW_WILDCARD_LOOKUP_ACTION_0_REG: data_output_port_lookup_o<=lut_actions_out[31:0] ;
`OPENFLOW_WILDCARD_LOOKUP_ACTION_1_REG: data_output_port_lookup_o<=lut_actions_out[63:32] ;
`OPENFLOW_WILDCARD_LOOKUP_ACTION_2_REG: data_output_port_lookup_o<=lut_actions_out[95:64] ;
`OPENFLOW_WILDCARD_LOOKUP_ACTION_3_REG: data_output_port_lookup_o<=lut_actions_out[127:96] ;
`OPENFLOW_WILDCARD_LOOKUP_ACTION_4_REG: data_output_port_lookup_o<=lut_actions_out[159:128];
`OPENFLOW_WILDCARD_LOOKUP_ACTION_5_REG: data_output_port_lookup_o<=lut_actions_out[191:160];
`OPENFLOW_WILDCARD_LOOKUP_ACTION_6_REG: data_output_port_lookup_o<=lut_actions_out[223:192];
`OPENFLOW_WILDCARD_LOOKUP_ACTION_7_REG: data_output_port_lookup_o<=lut_actions_out[255:224];
`OPENFLOW_WILDCARD_LOOKUP_ACTION_8_REG: data_output_port_lookup_o<=lut_actions_out[287:256];
`OPENFLOW_WILDCARD_LOOKUP_ACTION_9_REG: data_output_port_lookup_o<=lut_actions_out[319:288];
default:data_output_port_lookup_o<=32'hdeadbeef;
endcase
else if(cur_st==TCAM_READ)
case(addr_output_port_lookup_i[`ACTION_POS+`ACTION_WIDTH-1:`ACTION_POS])
`OPENFLOW_WILDCARD_LOOKUP_CMP_MASK_0_REG:data_output_port_lookup_o<=tcam_data_mask_in[31:0];
`OPENFLOW_WILDCARD_LOOKUP_CMP_MASK_1_REG:data_output_port_lookup_o<=tcam_data_mask_in[63:32];
//`OPENFLOW_WILDCARD_LOOKUP_CMP_MASK_2_REG:data_output_port_lookup_o<=tcam_data_mask_in[95:64];
`OPENFLOW_WILDCARD_LOOKUP_CMP_0_REG:data_output_port_lookup_o<=tcam_data_in[31:0];
`OPENFLOW_WILDCARD_LOOKUP_CMP_1_REG:data_output_port_lookup_o<=tcam_data_in[63:32];
`OPENFLOW_WILDCARD_LOOKUP_CMP_2_REG:data_output_port_lookup_o<=tcam_data_in[95:64];
default: data_output_port_lookup_o<=32'hdeadbeef;
endcase
else if(cur_st==COUNTER_ACK)
case(addr_output_port_lookup_i[`ACTION_POS+`ACTION_WIDTH-1:`ACTION_POS])
`OPENFLOW_WILDCARD_LOOKUP_BYTE_COUNTER: data_output_port_lookup_o<=byte_counter_in;
`OPENFLOW_WILDCARD_LOOKUP_PKT_COUNTER: data_output_port_lookup_o<=pkt_counter_in;
default:data_output_port_lookup_o<=32'hdeadbeef;
endcase
else if(cur_st==HEAD)
data_output_port_lookup_o<=head_combine;
else if(cur_st==ACK_BLANK)
data_output_port_lookup_o<=32'hdeadbeef;
/*end
`endif*/
always@(*)
if(reset)
counter_addr_out=0;
else if(cur_st==COUNTER)
counter_addr_out=addr_output_port_lookup_i[`PRIO_POS+`PRIO_WIDTH-1:`PRIO_POS];
else counter_addr_out=0;
always@(*)
if(reset)
counter_addr_rd=0;
else if(cur_st==COUNTER)
counter_addr_rd=1;
else counter_addr_rd=0;
always@(posedge clk)
if(reset)
head_combine<=0;
else if(cur_st==HEAD && rw_output_port_lookup_i==0)
head_combine<=data_output_port_lookup_i[7:0];
/*always@(posedge clk)
if(~rst)
begin
data_output_port_lookup_o<=0;
addr_output_port_lookup_o<=0;
req_output_port_lookup_o<=0;
rw_output_port_lookup_0_o<=0;
ack_output_port_lookup_o<=0;
end
else
begin
data_output_port_lookup_o<=data_output_port_lookup_i;
addr_output_port_lookup_o<=addr_output_port_lookup_i;
req_output_port_lookup_o<=req_output_port_lookup_i;
rw_output_port_lookup_0_o<=rw_output_port_lookup_0_i;
ack_output_port_lookup_o<=ack_output_port_lookup_i;
end */
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Wilson Snyder.
//bug456
typedef logic signed [34:0] rc_t;
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [34:0] rc = crc[34:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
logic o; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.o (o),
// Inputs
.rc (rc),
.clk (clk));
// Aggregate outputs into a single result vector
wire [63:0] result = {63'h0, o};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h7211d24a17b25ec9
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test( output logic o,
input rc_t rc,
input logic clk);
localparam RATIO = 2;
rc_t rc_d[RATIO:1];
always_ff @(posedge clk) begin
integer k;
rc_d[1] <= rc;
for( k=2; k<RATIO+1; k++ ) begin
rc_d[k] <= rc_d[k-1];
end
end // always_ff @
assign o = rc_d[RATIO] < 0;
endmodule
// Local Variables:
// verilog-typedef-regexp: "_t$"
// End:
|
/*
File: axi_slave_rd.v
This file is part of the Parallella FPGA Reference Design.
Copyright (C) 2013 Adapteva, Inc.
Contributed by Roman Trogan <[email protected]>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
//# Limitations:
//# 1. Read burst cannot cross single core boundaries
module axi_slave_rd (/*AUTOARG*/
// Outputs
arready, rid, rdata, rresp, rlast, rvalid, emesh_access_inb,
emesh_write_inb, emesh_datamode_inb, emesh_ctrlmode_inb,
emesh_dstaddr_inb, emesh_srcaddr_inb, emesh_data_inb,
emesh_wr_wait_inb,
// Inputs
aclk, eclk, reset, arid, araddr, arlen, arsize, arburst, arlock,
arcache, arprot, arvalid, rready, emesh_access_outb,
emesh_write_outb, emesh_datamode_outb, emesh_ctrlmode_outb,
emesh_dstaddr_outb, emesh_srcaddr_outb, emesh_data_outb,
emesh_rd_wait_outb
);
parameter SIDW = 12; //ID Width
parameter SAW = 32; //Address Bus Width
parameter SDW = 32; //Data Bus Width
parameter ACH = SAW+SIDW+5; //Width of all used Read Address Signals
parameter DFW = 4; //Data channel Fifo address width
parameter DCH = SDW+SIDW+1; //Width of all used Read Data Signals
//#########
//# Inputs
//#########
// global signals
input aclk; // clock source of the axi bus
input eclk; // clock source of emesh interface
input reset; // reset
//########################
//# Read address channel
//########################
input [SIDW-1:0] arid; //read address ID
input [SAW-1:0] araddr; //read address
input [3:0] arlen; //burst lenght (the number of data transfers)
input [2:0] arsize; //burst size (the size of each transfer)
input [1:0] arburst; //burst type
input [1:0] arlock; //lock type (atomic characteristics)
input [3:0] arcache; //memory type
input [2:0] arprot; //protection type
input arvalid; //write address valid
//########################
//# Read data channel
//########################
input rready; //read ready
//##############################
//# From the emesh interface
//##############################
input emesh_access_outb;
input emesh_write_outb;
input [1:0] emesh_datamode_outb;
input [3:0] emesh_ctrlmode_outb;
input [31:0] emesh_dstaddr_outb;
input [31:0] emesh_srcaddr_outb;
input [31:0] emesh_data_outb;
input emesh_rd_wait_outb;
//##########
//# Outputs
//##########
//########################
//# Read address channel
//########################
output arready;//read address ready
//########################
//# Read data channel
//########################
output [SIDW-1:0] rid; //read ID tag (must match arid of the transaction)
output [SDW-1:0] rdata;//read data
output [1:0] rresp; //read response
output rlast; //read last, indicates the last transfer in burst
output rvalid;//read valid
//##############################
//# To the emesh interface
//##############################
output emesh_access_inb;
output emesh_write_inb;
output [1:0] emesh_datamode_inb;
output [3:0] emesh_ctrlmode_inb;
output [31:0] emesh_dstaddr_inb;
output [31:0] emesh_srcaddr_inb;
output [31:0] emesh_data_inb;
output emesh_wr_wait_inb;
/*AUTOINPUT*/
/*AUTOWIRE*/
//#########
//# Regs
//#########
reg [3:0] tran_len;
reg tran_go_reg;
reg [SIDW+5:0] tran_info_reg;
reg tran_last_reg;
reg [31:0] dstaddr_reg;
reg [31:0] data_reg;
reg emesh_wr_access_reg;
reg [31:0] realgn_byte;
reg dch_fifo_empty_reg;
reg [DCH-1:0] dch_fifo_reg;
//#########
//# Wires
//#########
wire arready;
wire tran_go;
wire tran_stall;
wire tran_last_int;
wire tran_last;//Indicates last data of burst (out of fifo_dch)
wire [SAW-1:0] tran_addr;
wire [1:0] tran_mode;
wire [SIDW-1:0] arid_ec;
wire [3:0] arlen_ec;
wire [3:0] arlen_new;
wire arlen_dec;
wire [3:0] arlen_upd;
wire rd_last;
wire [2:0] dalgn_ctrl;
wire byte_tran;
wire hword_tran;
wire word_tran;
wire [SIDW+5:0] tran_info;
wire emesh_wr_access;
wire dch_fifo_full;
wire [2:0] realgn_ctrl;
wire [31:0] realgn_hword;
wire byte_realgn;
wire hword_realgn;
wire word_realgn;
wire [31:0] data_realgn;
wire [SIDW-1:0] tran_id;
wire last_tran;
wire [DCH-1:0] dch_fifo_in;
wire dch_fifo_wr;
wire dch_fifo_rd;
wire dch_fifo_empty;
wire [DCH-1:0] dch_fifo_out;
wire rvalid_rready;
wire dch_advance;
wire new_burst;
//#######################################
//# Address channel synchronization FIFO
//#######################################
/*axi_slave_addrch AUTO_TEMPLATE(.aclk (aclk),
.addr (araddr[]),
.ach_fifo_empty (),
.a\(.*\) (ar\1[]),
.new_addr_sel (new_burst),
);
*/
axi_slave_addrch axi_slave_addrch(/*AUTOINST*/
// Outputs
.aready (arready), // Templated
.ach_fifo_empty (), // Templated
.tran_addr (tran_addr[SAW-1:0]),
.tran_mode (tran_mode[1:0]),
.dalgn_ctrl (dalgn_ctrl[2:0]),
.byte_tran (byte_tran),
.hword_tran (hword_tran),
.word_tran (word_tran),
.aid_ec (arid_ec[SIDW-1:0]), // Templated
.alen_ec (arlen_ec[3:0]), // Templated
.new_addr_sel (new_burst), // Templated
// Inputs
.aclk (aclk), // Templated
.eclk (eclk),
.reset (reset),
.avalid (arvalid), // Templated
.addr (araddr[SAW-1:0]), // Templated
.aid (arid[SIDW-1:0]), // Templated
.alen (arlen[3:0]), // Templated
.asize (arsize[2:0]), // Templated
.aburst (arburst[1:0]), // Templated
.tran_last (tran_last),
.tran_stall (tran_stall),
.tran_go (tran_go));
//########################
//# AXI-EMESH conversion
//########################
assign tran_go = |(arlen_new[3:0]);
assign tran_last_int = dch_fifo_wr & last_tran;
assign tran_last = tran_last_reg & ~tran_stall;
always @ (posedge eclk or posedge reset)
if(reset)
tran_last_reg <= 1'b0;
else if(tran_last_int | ~tran_stall)
tran_last_reg <= tran_last_int;
always @ (posedge eclk or posedge reset)
if(reset)
tran_len[3:0] <= 4'b0000;
else if(tran_go & ~tran_stall)
tran_len[3:0] <= arlen_new[3:0];
always @ (posedge eclk or posedge reset)
if(reset)
tran_go_reg <= 1'b0;
else if(~tran_stall)
tran_go_reg <= tran_go;
assign arlen_dec = |(tran_len[3:0]);
assign arlen_upd[3:0] = {(4){arlen_dec}} & (tran_len[3:0] - 4'b0001);
assign arlen_new[3:0] = new_burst ? arlen_ec[3:0] : arlen_upd[3:0];
assign rd_last = (tran_len[3:0] == 4'b0001);
assign tran_info[SIDW+5:0] = {arid_ec[SIDW-1:0],dalgn_ctrl[2:0],byte_tran,
hword_tran,word_tran};
always @ (posedge eclk)
if(tran_go & ~tran_stall)
tran_info_reg[SIDW+5:0] <= tran_info[SIDW+5:0];
//#############################
//# Emesh transaction creation
//#############################
assign emesh_dstaddr_inb[31:0] = tran_addr[SAW-1:0];
assign emesh_srcaddr_inb[31:0] = {`AXI_COORD,{(13-SIDW){1'b0}},
tran_info_reg[SIDW+5:0], rd_last};
assign emesh_data_inb[31:0] = 32'h00000000;
assign emesh_datamode_inb[1:0] = tran_mode[1:0];
assign emesh_ctrlmode_inb[3:0] = 4'b0000;
assign emesh_write_inb = 1'b0;
assign emesh_access_inb = tran_go_reg & ~tran_stall;
//#######################################
//# Data channel synchronization FIFO
//#######################################
assign emesh_wr_wait_inb = dch_fifo_full;
//# Incoming transaction should be sampled to prevent timing issues
assign emesh_wr_access = emesh_access_outb & emesh_write_outb &
~emesh_wr_wait_inb;
always @ (posedge eclk)
if (emesh_wr_access)
dstaddr_reg[31:0] <= emesh_dstaddr_outb[31:0];
always @ (posedge eclk)
if (emesh_wr_access)
data_reg[31:0] <= emesh_data_outb[31:0];
always @ (posedge eclk or posedge reset)
if(reset)
emesh_wr_access_reg <= 1'b0;
else if(~emesh_wr_wait_inb)
emesh_wr_access_reg <= emesh_wr_access;
//# RID
assign tran_id[SIDW-1:0] = dstaddr_reg[SIDW+6:7];
//# Data Re-alignment from the EMESH protocol
assign realgn_ctrl[2:0] = dstaddr_reg[6:4];
assign byte_realgn = dstaddr_reg[3];
assign hword_realgn = dstaddr_reg[2];
assign word_realgn = dstaddr_reg[1];
//# Last transfer
assign last_tran = dstaddr_reg[0];
always @ (realgn_ctrl[1:0] or data_reg[7:0])
begin
casez (realgn_ctrl[1:0])
2'b00 : realgn_byte[31:0] = {{(24){1'b0}},data_reg[7:0] };
2'b01 : realgn_byte[31:0] = {{(16){1'b0}},data_reg[7:0],{( 8){1'b0}}};
2'b10 : realgn_byte[31:0] = {{(8){1'b0}},data_reg[7:0],{(16){1'b0}}};
2'b11 : realgn_byte[31:0] = {data_reg[7:0],{(24){1'b0}}};
default: realgn_byte[31:0] = {{(24){1'b0}},data_reg[7:0]};
endcase // casez (realgn_ctrl[1:0])
end
assign realgn_hword[31:0] = realgn_ctrl[1] ? {data_reg[15:0],{(16){1'b0}}} :
{{(16){1'b0}},data_reg[15:0]};
assign data_realgn[31:0] = byte_realgn ? realgn_byte[31:0] :
hword_realgn ? realgn_hword[31:0]:
data_reg[31:0];
assign dch_fifo_in[DCH-1:0] = {data_realgn[31:0],tran_id[SIDW-1:0],last_tran};
assign dch_fifo_wr = emesh_wr_access_reg & ~dch_fifo_full;
assign dch_fifo_rd = ~dch_fifo_empty & (~rvalid | rvalid_rready);
assign dch_advance = rvalid_rready | ~rvalid;
/*fifo AUTO_TEMPLATE(.rd_clk (aclk),
.wr_clk (eclk),
.wr_data (dch_fifo_in[DCH-1:0]),
.rd_data (dch_fifo_out[DCH-1:0]),
.rd_fifo_empty (dch_fifo_empty),
.wr_fifo_full (dch_fifo_full),
.wr_write (dch_fifo_wr),
.rd_read (dch_fifo_rd),
);
*/
fifo #(.DW(DCH), .AW(DFW)) fifo_dch(/*AUTOINST*/
// Outputs
.rd_data (dch_fifo_out[DCH-1:0]), // Templated
.rd_fifo_empty (dch_fifo_empty), // Templated
.wr_fifo_full (dch_fifo_full), // Templated
// Inputs
.reset (reset),
.wr_clk (eclk), // Templated
.rd_clk (aclk), // Templated
.wr_write (dch_fifo_wr), // Templated
.wr_data (dch_fifo_in[DCH-1:0]), // Templated
.rd_read (dch_fifo_rd)); // Templated
//# The data is sampled after exiting FIFO to prevent timing issues
always @ (posedge aclk or posedge reset)
if(reset)
dch_fifo_empty_reg <= 1'b1;
else if(dch_advance)
dch_fifo_empty_reg <= dch_fifo_empty;
always @ (posedge aclk)
if (dch_advance)
dch_fifo_reg[DCH-1:0] <= dch_fifo_out[DCH-1:0];
assign rid[SIDW-1:0] = dch_fifo_reg[SIDW:1];
assign rresp[1:0] = 2'b00;
assign rvalid = ~dch_fifo_empty_reg;
assign rvalid_rready = rvalid & rready;
assign rdata[SDW-1:0] = dch_fifo_reg[DCH-1:SIDW+1];
assign rlast = dch_fifo_reg[0];
//# Transaction Stall
assign tran_stall = emesh_rd_wait_outb;
endmodule // axi_slave_rd
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_system_cpu_s0_test_bench (
// inputs:
A_bstatus_reg,
A_ctrl_ld_non_io,
A_en,
A_estatus_reg,
A_status_reg,
A_valid,
A_wr_data_unfiltered,
A_wr_dst_reg,
E_add_br_to_taken_history_unfiltered,
E_valid,
M_bht_ptr_unfiltered,
M_bht_wr_data_unfiltered,
M_bht_wr_en_unfiltered,
M_mem_baddr,
M_target_pcb,
M_valid,
W_dst_regnum,
W_iw,
W_iw_op,
W_iw_opx,
W_pcb,
W_valid,
W_vinst,
W_wr_dst_reg,
clk,
d_address,
d_byteenable,
d_read,
d_write,
i_address,
i_read,
i_readdatavalid,
reset_n,
// outputs:
A_wr_data_filtered,
E_add_br_to_taken_history_filtered,
M_bht_ptr_filtered,
M_bht_wr_data_filtered,
M_bht_wr_en_filtered,
test_has_ended
)
;
output [ 31: 0] A_wr_data_filtered;
output E_add_br_to_taken_history_filtered;
output [ 7: 0] M_bht_ptr_filtered;
output [ 1: 0] M_bht_wr_data_filtered;
output M_bht_wr_en_filtered;
output test_has_ended;
input [ 31: 0] A_bstatus_reg;
input A_ctrl_ld_non_io;
input A_en;
input [ 31: 0] A_estatus_reg;
input [ 31: 0] A_status_reg;
input A_valid;
input [ 31: 0] A_wr_data_unfiltered;
input A_wr_dst_reg;
input E_add_br_to_taken_history_unfiltered;
input E_valid;
input [ 7: 0] M_bht_ptr_unfiltered;
input [ 1: 0] M_bht_wr_data_unfiltered;
input M_bht_wr_en_unfiltered;
input [ 27: 0] M_mem_baddr;
input [ 27: 0] M_target_pcb;
input M_valid;
input [ 4: 0] W_dst_regnum;
input [ 31: 0] W_iw;
input [ 5: 0] W_iw_op;
input [ 5: 0] W_iw_opx;
input [ 27: 0] W_pcb;
input W_valid;
input [ 55: 0] W_vinst;
input W_wr_dst_reg;
input clk;
input [ 27: 0] d_address;
input [ 3: 0] d_byteenable;
input d_read;
input d_write;
input [ 27: 0] i_address;
input i_read;
input i_readdatavalid;
input reset_n;
reg [ 27: 0] A_mem_baddr;
reg [ 27: 0] A_target_pcb;
wire [ 31: 0] A_wr_data_filtered;
wire A_wr_data_unfiltered_0_is_x;
wire A_wr_data_unfiltered_10_is_x;
wire A_wr_data_unfiltered_11_is_x;
wire A_wr_data_unfiltered_12_is_x;
wire A_wr_data_unfiltered_13_is_x;
wire A_wr_data_unfiltered_14_is_x;
wire A_wr_data_unfiltered_15_is_x;
wire A_wr_data_unfiltered_16_is_x;
wire A_wr_data_unfiltered_17_is_x;
wire A_wr_data_unfiltered_18_is_x;
wire A_wr_data_unfiltered_19_is_x;
wire A_wr_data_unfiltered_1_is_x;
wire A_wr_data_unfiltered_20_is_x;
wire A_wr_data_unfiltered_21_is_x;
wire A_wr_data_unfiltered_22_is_x;
wire A_wr_data_unfiltered_23_is_x;
wire A_wr_data_unfiltered_24_is_x;
wire A_wr_data_unfiltered_25_is_x;
wire A_wr_data_unfiltered_26_is_x;
wire A_wr_data_unfiltered_27_is_x;
wire A_wr_data_unfiltered_28_is_x;
wire A_wr_data_unfiltered_29_is_x;
wire A_wr_data_unfiltered_2_is_x;
wire A_wr_data_unfiltered_30_is_x;
wire A_wr_data_unfiltered_31_is_x;
wire A_wr_data_unfiltered_3_is_x;
wire A_wr_data_unfiltered_4_is_x;
wire A_wr_data_unfiltered_5_is_x;
wire A_wr_data_unfiltered_6_is_x;
wire A_wr_data_unfiltered_7_is_x;
wire A_wr_data_unfiltered_8_is_x;
wire A_wr_data_unfiltered_9_is_x;
wire E_add_br_to_taken_history_filtered;
wire [ 7: 0] M_bht_ptr_filtered;
wire [ 1: 0] M_bht_wr_data_filtered;
wire M_bht_wr_en_filtered;
wire W_op_add;
wire W_op_addi;
wire W_op_and;
wire W_op_andhi;
wire W_op_andi;
wire W_op_beq;
wire W_op_bge;
wire W_op_bgeu;
wire W_op_blt;
wire W_op_bltu;
wire W_op_bne;
wire W_op_br;
wire W_op_break;
wire W_op_bret;
wire W_op_call;
wire W_op_callr;
wire W_op_cmpeq;
wire W_op_cmpeqi;
wire W_op_cmpge;
wire W_op_cmpgei;
wire W_op_cmpgeu;
wire W_op_cmpgeui;
wire W_op_cmplt;
wire W_op_cmplti;
wire W_op_cmpltu;
wire W_op_cmpltui;
wire W_op_cmpne;
wire W_op_cmpnei;
wire W_op_crst;
wire W_op_custom;
wire W_op_div;
wire W_op_divu;
wire W_op_eret;
wire W_op_flushd;
wire W_op_flushda;
wire W_op_flushi;
wire W_op_flushp;
wire W_op_hbreak;
wire W_op_initd;
wire W_op_initda;
wire W_op_initi;
wire W_op_intr;
wire W_op_jmp;
wire W_op_jmpi;
wire W_op_ldb;
wire W_op_ldbio;
wire W_op_ldbu;
wire W_op_ldbuio;
wire W_op_ldh;
wire W_op_ldhio;
wire W_op_ldhu;
wire W_op_ldhuio;
wire W_op_ldl;
wire W_op_ldw;
wire W_op_ldwio;
wire W_op_mul;
wire W_op_muli;
wire W_op_mulxss;
wire W_op_mulxsu;
wire W_op_mulxuu;
wire W_op_nextpc;
wire W_op_nor;
wire W_op_opx;
wire W_op_or;
wire W_op_orhi;
wire W_op_ori;
wire W_op_rdctl;
wire W_op_rdprs;
wire W_op_ret;
wire W_op_rol;
wire W_op_roli;
wire W_op_ror;
wire W_op_rsv02;
wire W_op_rsv09;
wire W_op_rsv10;
wire W_op_rsv17;
wire W_op_rsv18;
wire W_op_rsv25;
wire W_op_rsv26;
wire W_op_rsv33;
wire W_op_rsv34;
wire W_op_rsv41;
wire W_op_rsv42;
wire W_op_rsv49;
wire W_op_rsv57;
wire W_op_rsv61;
wire W_op_rsv62;
wire W_op_rsv63;
wire W_op_rsvx00;
wire W_op_rsvx10;
wire W_op_rsvx15;
wire W_op_rsvx17;
wire W_op_rsvx21;
wire W_op_rsvx25;
wire W_op_rsvx33;
wire W_op_rsvx34;
wire W_op_rsvx35;
wire W_op_rsvx42;
wire W_op_rsvx43;
wire W_op_rsvx44;
wire W_op_rsvx47;
wire W_op_rsvx50;
wire W_op_rsvx51;
wire W_op_rsvx55;
wire W_op_rsvx56;
wire W_op_rsvx60;
wire W_op_rsvx63;
wire W_op_sll;
wire W_op_slli;
wire W_op_sra;
wire W_op_srai;
wire W_op_srl;
wire W_op_srli;
wire W_op_stb;
wire W_op_stbio;
wire W_op_stc;
wire W_op_sth;
wire W_op_sthio;
wire W_op_stw;
wire W_op_stwio;
wire W_op_sub;
wire W_op_sync;
wire W_op_trap;
wire W_op_wrctl;
wire W_op_wrprs;
wire W_op_xor;
wire W_op_xorhi;
wire W_op_xori;
wire test_has_ended;
assign W_op_call = W_iw_op == 0;
assign W_op_jmpi = W_iw_op == 1;
assign W_op_ldbu = W_iw_op == 3;
assign W_op_addi = W_iw_op == 4;
assign W_op_stb = W_iw_op == 5;
assign W_op_br = W_iw_op == 6;
assign W_op_ldb = W_iw_op == 7;
assign W_op_cmpgei = W_iw_op == 8;
assign W_op_ldhu = W_iw_op == 11;
assign W_op_andi = W_iw_op == 12;
assign W_op_sth = W_iw_op == 13;
assign W_op_bge = W_iw_op == 14;
assign W_op_ldh = W_iw_op == 15;
assign W_op_cmplti = W_iw_op == 16;
assign W_op_initda = W_iw_op == 19;
assign W_op_ori = W_iw_op == 20;
assign W_op_stw = W_iw_op == 21;
assign W_op_blt = W_iw_op == 22;
assign W_op_ldw = W_iw_op == 23;
assign W_op_cmpnei = W_iw_op == 24;
assign W_op_flushda = W_iw_op == 27;
assign W_op_xori = W_iw_op == 28;
assign W_op_stc = W_iw_op == 29;
assign W_op_bne = W_iw_op == 30;
assign W_op_ldl = W_iw_op == 31;
assign W_op_cmpeqi = W_iw_op == 32;
assign W_op_ldbuio = W_iw_op == 35;
assign W_op_muli = W_iw_op == 36;
assign W_op_stbio = W_iw_op == 37;
assign W_op_beq = W_iw_op == 38;
assign W_op_ldbio = W_iw_op == 39;
assign W_op_cmpgeui = W_iw_op == 40;
assign W_op_ldhuio = W_iw_op == 43;
assign W_op_andhi = W_iw_op == 44;
assign W_op_sthio = W_iw_op == 45;
assign W_op_bgeu = W_iw_op == 46;
assign W_op_ldhio = W_iw_op == 47;
assign W_op_cmpltui = W_iw_op == 48;
assign W_op_initd = W_iw_op == 51;
assign W_op_orhi = W_iw_op == 52;
assign W_op_stwio = W_iw_op == 53;
assign W_op_bltu = W_iw_op == 54;
assign W_op_ldwio = W_iw_op == 55;
assign W_op_rdprs = W_iw_op == 56;
assign W_op_flushd = W_iw_op == 59;
assign W_op_xorhi = W_iw_op == 60;
assign W_op_rsv02 = W_iw_op == 2;
assign W_op_rsv09 = W_iw_op == 9;
assign W_op_rsv10 = W_iw_op == 10;
assign W_op_rsv17 = W_iw_op == 17;
assign W_op_rsv18 = W_iw_op == 18;
assign W_op_rsv25 = W_iw_op == 25;
assign W_op_rsv26 = W_iw_op == 26;
assign W_op_rsv33 = W_iw_op == 33;
assign W_op_rsv34 = W_iw_op == 34;
assign W_op_rsv41 = W_iw_op == 41;
assign W_op_rsv42 = W_iw_op == 42;
assign W_op_rsv49 = W_iw_op == 49;
assign W_op_rsv57 = W_iw_op == 57;
assign W_op_rsv61 = W_iw_op == 61;
assign W_op_rsv62 = W_iw_op == 62;
assign W_op_rsv63 = W_iw_op == 63;
assign W_op_eret = W_op_opx & (W_iw_opx == 1);
assign W_op_roli = W_op_opx & (W_iw_opx == 2);
assign W_op_rol = W_op_opx & (W_iw_opx == 3);
assign W_op_flushp = W_op_opx & (W_iw_opx == 4);
assign W_op_ret = W_op_opx & (W_iw_opx == 5);
assign W_op_nor = W_op_opx & (W_iw_opx == 6);
assign W_op_mulxuu = W_op_opx & (W_iw_opx == 7);
assign W_op_cmpge = W_op_opx & (W_iw_opx == 8);
assign W_op_bret = W_op_opx & (W_iw_opx == 9);
assign W_op_ror = W_op_opx & (W_iw_opx == 11);
assign W_op_flushi = W_op_opx & (W_iw_opx == 12);
assign W_op_jmp = W_op_opx & (W_iw_opx == 13);
assign W_op_and = W_op_opx & (W_iw_opx == 14);
assign W_op_cmplt = W_op_opx & (W_iw_opx == 16);
assign W_op_slli = W_op_opx & (W_iw_opx == 18);
assign W_op_sll = W_op_opx & (W_iw_opx == 19);
assign W_op_wrprs = W_op_opx & (W_iw_opx == 20);
assign W_op_or = W_op_opx & (W_iw_opx == 22);
assign W_op_mulxsu = W_op_opx & (W_iw_opx == 23);
assign W_op_cmpne = W_op_opx & (W_iw_opx == 24);
assign W_op_srli = W_op_opx & (W_iw_opx == 26);
assign W_op_srl = W_op_opx & (W_iw_opx == 27);
assign W_op_nextpc = W_op_opx & (W_iw_opx == 28);
assign W_op_callr = W_op_opx & (W_iw_opx == 29);
assign W_op_xor = W_op_opx & (W_iw_opx == 30);
assign W_op_mulxss = W_op_opx & (W_iw_opx == 31);
assign W_op_cmpeq = W_op_opx & (W_iw_opx == 32);
assign W_op_divu = W_op_opx & (W_iw_opx == 36);
assign W_op_div = W_op_opx & (W_iw_opx == 37);
assign W_op_rdctl = W_op_opx & (W_iw_opx == 38);
assign W_op_mul = W_op_opx & (W_iw_opx == 39);
assign W_op_cmpgeu = W_op_opx & (W_iw_opx == 40);
assign W_op_initi = W_op_opx & (W_iw_opx == 41);
assign W_op_trap = W_op_opx & (W_iw_opx == 45);
assign W_op_wrctl = W_op_opx & (W_iw_opx == 46);
assign W_op_cmpltu = W_op_opx & (W_iw_opx == 48);
assign W_op_add = W_op_opx & (W_iw_opx == 49);
assign W_op_break = W_op_opx & (W_iw_opx == 52);
assign W_op_hbreak = W_op_opx & (W_iw_opx == 53);
assign W_op_sync = W_op_opx & (W_iw_opx == 54);
assign W_op_sub = W_op_opx & (W_iw_opx == 57);
assign W_op_srai = W_op_opx & (W_iw_opx == 58);
assign W_op_sra = W_op_opx & (W_iw_opx == 59);
assign W_op_intr = W_op_opx & (W_iw_opx == 61);
assign W_op_crst = W_op_opx & (W_iw_opx == 62);
assign W_op_rsvx00 = W_op_opx & (W_iw_opx == 0);
assign W_op_rsvx10 = W_op_opx & (W_iw_opx == 10);
assign W_op_rsvx15 = W_op_opx & (W_iw_opx == 15);
assign W_op_rsvx17 = W_op_opx & (W_iw_opx == 17);
assign W_op_rsvx21 = W_op_opx & (W_iw_opx == 21);
assign W_op_rsvx25 = W_op_opx & (W_iw_opx == 25);
assign W_op_rsvx33 = W_op_opx & (W_iw_opx == 33);
assign W_op_rsvx34 = W_op_opx & (W_iw_opx == 34);
assign W_op_rsvx35 = W_op_opx & (W_iw_opx == 35);
assign W_op_rsvx42 = W_op_opx & (W_iw_opx == 42);
assign W_op_rsvx43 = W_op_opx & (W_iw_opx == 43);
assign W_op_rsvx44 = W_op_opx & (W_iw_opx == 44);
assign W_op_rsvx47 = W_op_opx & (W_iw_opx == 47);
assign W_op_rsvx50 = W_op_opx & (W_iw_opx == 50);
assign W_op_rsvx51 = W_op_opx & (W_iw_opx == 51);
assign W_op_rsvx55 = W_op_opx & (W_iw_opx == 55);
assign W_op_rsvx56 = W_op_opx & (W_iw_opx == 56);
assign W_op_rsvx60 = W_op_opx & (W_iw_opx == 60);
assign W_op_rsvx63 = W_op_opx & (W_iw_opx == 63);
assign W_op_opx = W_iw_op == 58;
assign W_op_custom = W_iw_op == 50;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
A_target_pcb <= 0;
else if (A_en)
A_target_pcb <= M_target_pcb;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
A_mem_baddr <= 0;
else if (A_en)
A_mem_baddr <= M_mem_baddr;
end
//Propagating 'X' data bits
assign E_add_br_to_taken_history_filtered = E_add_br_to_taken_history_unfiltered;
//Propagating 'X' data bits
assign M_bht_wr_en_filtered = M_bht_wr_en_unfiltered;
//Propagating 'X' data bits
assign M_bht_wr_data_filtered = M_bht_wr_data_unfiltered;
//Propagating 'X' data bits
assign M_bht_ptr_filtered = M_bht_ptr_unfiltered;
assign test_has_ended = 1'b0;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//Clearing 'X' data bits
assign A_wr_data_unfiltered_0_is_x = ^(A_wr_data_unfiltered[0]) === 1'bx;
assign A_wr_data_filtered[0] = (A_wr_data_unfiltered_0_is_x & (A_ctrl_ld_non_io)) ? 1'b0 : A_wr_data_unfiltered[0];
assign A_wr_data_unfiltered_1_is_x = ^(A_wr_data_unfiltered[1]) === 1'bx;
assign A_wr_data_filtered[1] = (A_wr_data_unfiltered_1_is_x & (A_ctrl_ld_non_io)) ? 1'b0 : A_wr_data_unfiltered[1];
assign A_wr_data_unfiltered_2_is_x = ^(A_wr_data_unfiltered[2]) === 1'bx;
assign A_wr_data_filtered[2] = (A_wr_data_unfiltered_2_is_x & (A_ctrl_ld_non_io)) ? 1'b0 : A_wr_data_unfiltered[2];
assign A_wr_data_unfiltered_3_is_x = ^(A_wr_data_unfiltered[3]) === 1'bx;
assign A_wr_data_filtered[3] = (A_wr_data_unfiltered_3_is_x & (A_ctrl_ld_non_io)) ? 1'b0 : A_wr_data_unfiltered[3];
assign A_wr_data_unfiltered_4_is_x = ^(A_wr_data_unfiltered[4]) === 1'bx;
assign A_wr_data_filtered[4] = (A_wr_data_unfiltered_4_is_x & (A_ctrl_ld_non_io)) ? 1'b0 : A_wr_data_unfiltered[4];
assign A_wr_data_unfiltered_5_is_x = ^(A_wr_data_unfiltered[5]) === 1'bx;
assign A_wr_data_filtered[5] = (A_wr_data_unfiltered_5_is_x & (A_ctrl_ld_non_io)) ? 1'b0 : A_wr_data_unfiltered[5];
assign A_wr_data_unfiltered_6_is_x = ^(A_wr_data_unfiltered[6]) === 1'bx;
assign A_wr_data_filtered[6] = (A_wr_data_unfiltered_6_is_x & (A_ctrl_ld_non_io)) ? 1'b0 : A_wr_data_unfiltered[6];
assign A_wr_data_unfiltered_7_is_x = ^(A_wr_data_unfiltered[7]) === 1'bx;
assign A_wr_data_filtered[7] = (A_wr_data_unfiltered_7_is_x & (A_ctrl_ld_non_io)) ? 1'b0 : A_wr_data_unfiltered[7];
assign A_wr_data_unfiltered_8_is_x = ^(A_wr_data_unfiltered[8]) === 1'bx;
assign A_wr_data_filtered[8] = (A_wr_data_unfiltered_8_is_x & (A_ctrl_ld_non_io)) ? 1'b0 : A_wr_data_unfiltered[8];
assign A_wr_data_unfiltered_9_is_x = ^(A_wr_data_unfiltered[9]) === 1'bx;
assign A_wr_data_filtered[9] = (A_wr_data_unfiltered_9_is_x & (A_ctrl_ld_non_io)) ? 1'b0 : A_wr_data_unfiltered[9];
assign A_wr_data_unfiltered_10_is_x = ^(A_wr_data_unfiltered[10]) === 1'bx;
assign A_wr_data_filtered[10] = (A_wr_data_unfiltered_10_is_x & (A_ctrl_ld_non_io)) ? 1'b0 : A_wr_data_unfiltered[10];
assign A_wr_data_unfiltered_11_is_x = ^(A_wr_data_unfiltered[11]) === 1'bx;
assign A_wr_data_filtered[11] = (A_wr_data_unfiltered_11_is_x & (A_ctrl_ld_non_io)) ? 1'b0 : A_wr_data_unfiltered[11];
assign A_wr_data_unfiltered_12_is_x = ^(A_wr_data_unfiltered[12]) === 1'bx;
assign A_wr_data_filtered[12] = (A_wr_data_unfiltered_12_is_x & (A_ctrl_ld_non_io)) ? 1'b0 : A_wr_data_unfiltered[12];
assign A_wr_data_unfiltered_13_is_x = ^(A_wr_data_unfiltered[13]) === 1'bx;
assign A_wr_data_filtered[13] = (A_wr_data_unfiltered_13_is_x & (A_ctrl_ld_non_io)) ? 1'b0 : A_wr_data_unfiltered[13];
assign A_wr_data_unfiltered_14_is_x = ^(A_wr_data_unfiltered[14]) === 1'bx;
assign A_wr_data_filtered[14] = (A_wr_data_unfiltered_14_is_x & (A_ctrl_ld_non_io)) ? 1'b0 : A_wr_data_unfiltered[14];
assign A_wr_data_unfiltered_15_is_x = ^(A_wr_data_unfiltered[15]) === 1'bx;
assign A_wr_data_filtered[15] = (A_wr_data_unfiltered_15_is_x & (A_ctrl_ld_non_io)) ? 1'b0 : A_wr_data_unfiltered[15];
assign A_wr_data_unfiltered_16_is_x = ^(A_wr_data_unfiltered[16]) === 1'bx;
assign A_wr_data_filtered[16] = (A_wr_data_unfiltered_16_is_x & (A_ctrl_ld_non_io)) ? 1'b0 : A_wr_data_unfiltered[16];
assign A_wr_data_unfiltered_17_is_x = ^(A_wr_data_unfiltered[17]) === 1'bx;
assign A_wr_data_filtered[17] = (A_wr_data_unfiltered_17_is_x & (A_ctrl_ld_non_io)) ? 1'b0 : A_wr_data_unfiltered[17];
assign A_wr_data_unfiltered_18_is_x = ^(A_wr_data_unfiltered[18]) === 1'bx;
assign A_wr_data_filtered[18] = (A_wr_data_unfiltered_18_is_x & (A_ctrl_ld_non_io)) ? 1'b0 : A_wr_data_unfiltered[18];
assign A_wr_data_unfiltered_19_is_x = ^(A_wr_data_unfiltered[19]) === 1'bx;
assign A_wr_data_filtered[19] = (A_wr_data_unfiltered_19_is_x & (A_ctrl_ld_non_io)) ? 1'b0 : A_wr_data_unfiltered[19];
assign A_wr_data_unfiltered_20_is_x = ^(A_wr_data_unfiltered[20]) === 1'bx;
assign A_wr_data_filtered[20] = (A_wr_data_unfiltered_20_is_x & (A_ctrl_ld_non_io)) ? 1'b0 : A_wr_data_unfiltered[20];
assign A_wr_data_unfiltered_21_is_x = ^(A_wr_data_unfiltered[21]) === 1'bx;
assign A_wr_data_filtered[21] = (A_wr_data_unfiltered_21_is_x & (A_ctrl_ld_non_io)) ? 1'b0 : A_wr_data_unfiltered[21];
assign A_wr_data_unfiltered_22_is_x = ^(A_wr_data_unfiltered[22]) === 1'bx;
assign A_wr_data_filtered[22] = (A_wr_data_unfiltered_22_is_x & (A_ctrl_ld_non_io)) ? 1'b0 : A_wr_data_unfiltered[22];
assign A_wr_data_unfiltered_23_is_x = ^(A_wr_data_unfiltered[23]) === 1'bx;
assign A_wr_data_filtered[23] = (A_wr_data_unfiltered_23_is_x & (A_ctrl_ld_non_io)) ? 1'b0 : A_wr_data_unfiltered[23];
assign A_wr_data_unfiltered_24_is_x = ^(A_wr_data_unfiltered[24]) === 1'bx;
assign A_wr_data_filtered[24] = (A_wr_data_unfiltered_24_is_x & (A_ctrl_ld_non_io)) ? 1'b0 : A_wr_data_unfiltered[24];
assign A_wr_data_unfiltered_25_is_x = ^(A_wr_data_unfiltered[25]) === 1'bx;
assign A_wr_data_filtered[25] = (A_wr_data_unfiltered_25_is_x & (A_ctrl_ld_non_io)) ? 1'b0 : A_wr_data_unfiltered[25];
assign A_wr_data_unfiltered_26_is_x = ^(A_wr_data_unfiltered[26]) === 1'bx;
assign A_wr_data_filtered[26] = (A_wr_data_unfiltered_26_is_x & (A_ctrl_ld_non_io)) ? 1'b0 : A_wr_data_unfiltered[26];
assign A_wr_data_unfiltered_27_is_x = ^(A_wr_data_unfiltered[27]) === 1'bx;
assign A_wr_data_filtered[27] = (A_wr_data_unfiltered_27_is_x & (A_ctrl_ld_non_io)) ? 1'b0 : A_wr_data_unfiltered[27];
assign A_wr_data_unfiltered_28_is_x = ^(A_wr_data_unfiltered[28]) === 1'bx;
assign A_wr_data_filtered[28] = (A_wr_data_unfiltered_28_is_x & (A_ctrl_ld_non_io)) ? 1'b0 : A_wr_data_unfiltered[28];
assign A_wr_data_unfiltered_29_is_x = ^(A_wr_data_unfiltered[29]) === 1'bx;
assign A_wr_data_filtered[29] = (A_wr_data_unfiltered_29_is_x & (A_ctrl_ld_non_io)) ? 1'b0 : A_wr_data_unfiltered[29];
assign A_wr_data_unfiltered_30_is_x = ^(A_wr_data_unfiltered[30]) === 1'bx;
assign A_wr_data_filtered[30] = (A_wr_data_unfiltered_30_is_x & (A_ctrl_ld_non_io)) ? 1'b0 : A_wr_data_unfiltered[30];
assign A_wr_data_unfiltered_31_is_x = ^(A_wr_data_unfiltered[31]) === 1'bx;
assign A_wr_data_filtered[31] = (A_wr_data_unfiltered_31_is_x & (A_ctrl_ld_non_io)) ? 1'b0 : A_wr_data_unfiltered[31];
always @(posedge clk)
begin
if (reset_n)
if (^(W_wr_dst_reg) === 1'bx)
begin
$write("%0d ns: ERROR: soc_system_cpu_s0_test_bench/W_wr_dst_reg is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_wr_dst_reg)
if (^(W_dst_regnum) === 1'bx)
begin
$write("%0d ns: ERROR: soc_system_cpu_s0_test_bench/W_dst_regnum is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(W_valid) === 1'bx)
begin
$write("%0d ns: ERROR: soc_system_cpu_s0_test_bench/W_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid)
if (^(W_pcb) === 1'bx)
begin
$write("%0d ns: ERROR: soc_system_cpu_s0_test_bench/W_pcb is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid)
if (^(W_iw) === 1'bx)
begin
$write("%0d ns: ERROR: soc_system_cpu_s0_test_bench/W_iw is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(A_en) === 1'bx)
begin
$write("%0d ns: ERROR: soc_system_cpu_s0_test_bench/A_en is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(E_valid) === 1'bx)
begin
$write("%0d ns: ERROR: soc_system_cpu_s0_test_bench/E_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(M_valid) === 1'bx)
begin
$write("%0d ns: ERROR: soc_system_cpu_s0_test_bench/M_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(A_valid) === 1'bx)
begin
$write("%0d ns: ERROR: soc_system_cpu_s0_test_bench/A_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (A_valid & A_en & A_wr_dst_reg)
if (^(A_wr_data_unfiltered) === 1'bx)
begin
$write("%0d ns: WARNING: soc_system_cpu_s0_test_bench/A_wr_data_unfiltered is 'x'\n", $time);
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(A_status_reg) === 1'bx)
begin
$write("%0d ns: ERROR: soc_system_cpu_s0_test_bench/A_status_reg is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(A_estatus_reg) === 1'bx)
begin
$write("%0d ns: ERROR: soc_system_cpu_s0_test_bench/A_estatus_reg is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(A_bstatus_reg) === 1'bx)
begin
$write("%0d ns: ERROR: soc_system_cpu_s0_test_bench/A_bstatus_reg is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(i_read) === 1'bx)
begin
$write("%0d ns: ERROR: soc_system_cpu_s0_test_bench/i_read is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (i_read)
if (^(i_address) === 1'bx)
begin
$write("%0d ns: ERROR: soc_system_cpu_s0_test_bench/i_address is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(i_readdatavalid) === 1'bx)
begin
$write("%0d ns: ERROR: soc_system_cpu_s0_test_bench/i_readdatavalid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(d_write) === 1'bx)
begin
$write("%0d ns: ERROR: soc_system_cpu_s0_test_bench/d_write is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (d_write)
if (^(d_byteenable) === 1'bx)
begin
$write("%0d ns: ERROR: soc_system_cpu_s0_test_bench/d_byteenable is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (d_write | d_read)
if (^(d_address) === 1'bx)
begin
$write("%0d ns: ERROR: soc_system_cpu_s0_test_bench/d_address is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(d_read) === 1'bx)
begin
$write("%0d ns: ERROR: soc_system_cpu_s0_test_bench/d_read is 'x'\n", $time);
$stop;
end
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
//
// assign A_wr_data_filtered = A_wr_data_unfiltered;
//
//synthesis read_comments_as_HDL off
endmodule
|
/*
* Copyright (c) 2015-2018 The Ultiparc Project. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/*
* Coprocessor 0
*/
`include "uparc_cpu_config.vh"
`include "uparc_cpu_common.vh"
`include "uparc_cpu_const.vh"
/* Coprocessor 0 */
module uparc_coproc0(
clk,
nrst,
/* CU signals */
i_exec_stall,
i_mem_stall,
i_fetch_stall,
i_wait_stall,
o_decode_error,
i_except_start,
i_except_dly_slt,
i_except_raddr,
i_except_raddr_dly,
i_nullify_decode,
i_nullify_execute,
i_nullify_mem,
i_nullify_wb,
/* COP0 signals */
o_cop0_ivtbase,
o_cop0_ie,
o_cop0_intr_wait,
/* Fetched instruction */
i_instr,
/* Decoded instr */
o_cop0_op_p1,
o_cop0_cop_p1,
o_cop0_reg_no_p1,
o_cop0_reg_val_p1,
o_cop0_rt_no_p1,
/* Execute stage signals */
i_cop0_alu_result_p2
);
`include "uparc_reg_names.vh"
`include "uparc_decode_const.vh"
localparam [`UPARC_INSTR_WIDTH-1:0] NOP = 32'h0000_0000;
/* Coprocessor 0 register numbers */
localparam [`UPARC_REGNO_WIDTH-1:0] TSCLO = 5'h08;
localparam [`UPARC_REGNO_WIDTH-1:0] TSCHI = 5'h09;
localparam [`UPARC_REGNO_WIDTH-1:0] IVT = 5'h0A;
localparam [`UPARC_REGNO_WIDTH-1:0] PSR = 5'h0B;
localparam [`UPARC_REGNO_WIDTH-1:0] SR = 5'h0C;
localparam [`UPARC_REGNO_WIDTH-1:0] CAUSE = 5'h0D;
localparam [`UPARC_REGNO_WIDTH-1:0] EPC = 5'h0E;
localparam [`UPARC_REGNO_WIDTH-1:0] PRID = 5'h0F;
/* Inputs */
input wire clk;
input wire nrst;
/* CU signals */
input wire i_exec_stall;
input wire i_mem_stall;
input wire i_fetch_stall;
input wire i_wait_stall;
output reg o_decode_error;
input wire i_except_start;
input wire i_except_dly_slt;
input wire [`UPARC_ADDR_WIDTH-1:0] i_except_raddr;
input wire [`UPARC_ADDR_WIDTH-1:0] i_except_raddr_dly;
input wire i_nullify_decode;
input wire i_nullify_execute;
input wire i_nullify_mem;
input wire i_nullify_wb;
/* COP0 signals */
output wire [`UPARC_ADDR_WIDTH-11:0] o_cop0_ivtbase;
output wire o_cop0_ie;
output wire o_cop0_intr_wait;
/* Fetched instruction */
input wire [`UPARC_INSTR_WIDTH-1:0] i_instr;
/* Decoded instr */
output wire o_cop0_op_p1;
output wire [`UPARC_REGNO_WIDTH-1:0] o_cop0_cop_p1;
output wire [`UPARC_REGNO_WIDTH-1:0] o_cop0_reg_no_p1;
output reg [`UPARC_REG_WIDTH-1:0] o_cop0_reg_val_p1;
output wire [`UPARC_REGNO_WIDTH-1:0] o_cop0_rt_no_p1;
/* Execute stage signals */
input wire [`UPARC_REG_WIDTH-1:0] i_cop0_alu_result_p2;
wire core_stall = i_exec_stall || i_mem_stall || i_fetch_stall || i_wait_stall;
assign o_cop0_ivtbase = reg_ivt;
assign o_cop0_ie = reg_sr_ie;
assign o_cop0_intr_wait = intr_wait;
/* Coprocessor 0 registers */
reg [`UPARC_ADDR_WIDTH-11:0] reg_ivt; /* High 22 bits of IVT base (reg 0xA) */
reg reg_psr_ie; /* Copy of IE flag from Status register (reg 0xB) */
reg reg_sr_ie; /* IE flag from Status register (reg 0xC) */
reg reg_cause_bd; /* BD flag from Cause register (reg 0xD) */
reg [`UPARC_ADDR_WIDTH-1:0] reg_epc; /* Program counter on exception entrance (reg 0xE) */
wire [`UPARC_DATA_WIDTH-1:0] reg_prid; /* Processor ID R/O register (reg 0xF) */
assign reg_prid = `UPARC_PROCID_CODE;
reg [`UPARC_INSTR_WIDTH-1:0] instr; /* Instruction word */
reg intr_wait; /* Interrupt wait state */
/* Restore from exception state */
wire rfe = (cop_p2 == `UPARC_COP0_CO && cop_func_p2 == `UPARC_COP0_FUNC_RFE) ||
(cop_p3 == `UPARC_COP0_CO && cop_func_p3 == `UPARC_COP0_FUNC_RFE) ? 1'b1 : 1'b0;
/******************************* DECODE STAGE *********************************/
/* Instruction fields */
wire [5:0] op; /* Opcode */
wire [`UPARC_REGNO_WIDTH-1:0] cop; /* Coprocessor opcode */
wire [`UPARC_REGNO_WIDTH-1:0] rt; /* Source register 2 */
wire [`UPARC_REGNO_WIDTH-1:0] rd; /* Destination register */
wire [4:0] rsvd; /* Reserved field */
wire [5:0] func; /* Function */
assign op = instr[31:26];
assign cop = instr[25:21];
assign rt = instr[20:16];
assign rd = instr[15:11];
assign rsvd = instr[10:6];
assign func = instr[5:0];
/* Decoded fields */
wire cop_instr_p1;
wire [`UPARC_REGNO_WIDTH-1:0] cop_p1;
wire [`UPARC_REGNO_WIDTH-1:0] cop_rt_no_p1;
wire [`UPARC_REGNO_WIDTH-1:0] cop_reg_no_p1;
wire [5:0] cop_func_p1;
assign cop_instr_p1 = op == `UPARC_OP_COP0 ? 1'b1 : 1'b0;
assign cop_p1 = op == `UPARC_OP_COP0 ? cop : {(`UPARC_REGNO_WIDTH){1'b0}};
assign cop_rt_no_p1 = op == `UPARC_OP_COP0 ? rt : {(`UPARC_REGNO_WIDTH){1'b0}};
assign cop_reg_no_p1 = op == `UPARC_OP_COP0 ? rd : {(`UPARC_REGNO_WIDTH){1'b0}};
assign cop_func_p1 = op == `UPARC_OP_COP0 ? func : 6'b0;
/* Decode stage outputs */
assign o_cop0_op_p1 = cop_instr_p1;
assign o_cop0_cop_p1 = cop_p1 == `UPARC_COP0_MF || cop_p1 == `UPARC_COP0_MT ? cop_p1 :
{(`UPARC_REGNO_WIDTH){1'b0}};
assign o_cop0_rt_no_p1 = cop_rt_no_p1;
assign o_cop0_reg_no_p1 = cop_reg_no_p1;
/* Coprocessor 0 register value */
always @(*)
begin
o_cop0_reg_val_p1 = {(`UPARC_REG_WIDTH){1'b0}};
if(cop_instr_p1 && cop_p1 == `UPARC_COP0_MF)
begin
case(cop_reg_no_p1)
TSCLO: o_cop0_reg_val_p1 = tsc_latched_lo;
TSCHI: o_cop0_reg_val_p1 = tsc_latched_hi;
IVT: o_cop0_reg_val_p1 = { reg_ivt, 10'b0 };
PSR: o_cop0_reg_val_p1 = { {(`UPARC_REG_WIDTH-1){1'b0}}, reg_psr_ie };
SR: o_cop0_reg_val_p1 = { {(`UPARC_REG_WIDTH-1){1'b0}}, rfe ? reg_psr_ie : reg_sr_ie };
CAUSE: o_cop0_reg_val_p1 = { reg_cause_bd, {(`UPARC_REG_WIDTH-1){1'b0}} };
EPC: o_cop0_reg_val_p1 = reg_epc;
PRID: o_cop0_reg_val_p1 = reg_prid;
default: o_cop0_reg_val_p1 = {(`UPARC_REG_WIDTH){1'b0}};
endcase
end
end
/* Detect instruction format errors */
always @(*)
begin
o_decode_error = 1'b0;
if(cop_instr_p1)
begin
case(cop_p1)
`UPARC_COP0_MF,
`UPARC_COP0_MT: o_decode_error = |{ rsvd, func } ? 1'b1 : 1'b0;
`UPARC_COP0_CO: o_decode_error =
|{ rt, rd, rsvd } ||
(func != `UPARC_COP0_FUNC_RFE && func != `UPARC_COP0_FUNC_WAIT) ?
1'b1 : 1'b0;
default: o_decode_error = 1'b1;
endcase
end
end
/* Decode stage */
always @(posedge clk or negedge nrst)
begin
if(!nrst)
begin
instr <= NOP;
end
else if(!core_stall)
begin
instr <= !i_nullify_decode ? i_instr : NOP;
end
end
/****************************** EXECUTE STAGE *********************************/
reg cop_instr_p2;
reg [`UPARC_REGNO_WIDTH-1:0] cop_p2;
reg [`UPARC_REGNO_WIDTH-1:0] cop_reg_no_p2;
reg [5:0] cop_func_p2;
/* Execute stage */
always @(posedge clk or negedge nrst)
begin
if(!nrst)
begin
cop_instr_p2 <= 1'b0;
cop_p2 <= {(`UPARC_REGNO_WIDTH){1'b0}};
cop_reg_no_p2 <= {(`UPARC_REGNO_WIDTH){1'b0}};
cop_func_p2 <= 6'b0;
end
else if(!core_stall && !i_nullify_execute)
begin
cop_instr_p2 <= cop_instr_p1;
cop_p2 <= cop_p1;
cop_reg_no_p2 <= cop_reg_no_p1;
cop_func_p2 <= cop_func_p1;
end
else if(!core_stall)
begin
cop_instr_p2 <= 1'b0;
cop_p2 <= {(`UPARC_REGNO_WIDTH){1'b0}};
cop_reg_no_p2 <= {(`UPARC_REGNO_WIDTH){1'b0}};
cop_func_p2 <= 6'b0;
end
end
/******************************* MEMORY STAGE *********************************/
reg cop_instr_p3;
reg [`UPARC_REGNO_WIDTH-1:0] cop_p3;
reg [`UPARC_REGNO_WIDTH-1:0] cop_reg_no_p3;
reg [`UPARC_REG_WIDTH-1:0] cop_reg_val_p3;
reg [5:0] cop_func_p3;
/* Memory stage */
always @(posedge clk or negedge nrst)
begin
if(!nrst)
begin
cop_instr_p3 <= 1'b0;
cop_p3 <= {(`UPARC_REGNO_WIDTH){1'b0}};
cop_reg_no_p3 <= {(`UPARC_REGNO_WIDTH){1'b0}};
cop_reg_val_p3 <= {(`UPARC_REG_WIDTH){1'b0}};
cop_func_p3 <= 6'b0;
end
else if(!core_stall && !i_nullify_mem)
begin
cop_instr_p3 <= cop_instr_p2;
cop_p3 <= cop_p2;
cop_reg_no_p3 <= cop_reg_no_p2;
cop_reg_val_p3 <= i_cop0_alu_result_p2;
cop_func_p3 <= cop_func_p2;
end
else if(!core_stall)
begin
cop_instr_p3 <= 1'b0;
cop_p3 <= {(`UPARC_REGNO_WIDTH){1'b0}};
cop_reg_no_p3 <= {(`UPARC_REGNO_WIDTH){1'b0}};
cop_reg_val_p3 <= {(`UPARC_REG_WIDTH){1'b0}};
cop_func_p3 <= 6'b0;
end
end
/***************************** WRITEBACK STAGE ********************************/
/* Writeback stage */
always @(posedge clk or negedge nrst)
begin
if(!nrst)
begin
reg_ivt <= {(`UPARC_ADDR_WIDTH-10){1'b0}};
reg_psr_ie <= 1'b0;
reg_sr_ie <= 1'b0;
reg_cause_bd <= 1'b0;
reg_epc <= {(`UPARC_ADDR_WIDTH){1'b0}};
intr_wait <= 1'b0;
end
else if(!core_stall && !i_nullify_wb)
begin
if(cop_instr_p3 && cop_p3 == `UPARC_COP0_CO)
begin
case(cop_func_p3)
`UPARC_COP0_FUNC_RFE: begin
reg_sr_ie <= reg_psr_ie;
reg_psr_ie <= 1'b0;
end
`UPARC_COP0_FUNC_WAIT: begin
intr_wait <= 1'b1;
end
default: ;
endcase
end
else if(cop_instr_p3 && cop_p3 == `UPARC_COP0_MT)
begin
case(cop_reg_no_p3)
IVT: reg_ivt <= cop_reg_val_p3[`UPARC_REG_WIDTH-1:10];
PSR: reg_psr_ie <= cop_reg_val_p3[0];
SR: reg_sr_ie <= cop_reg_val_p3[0];
CAUSE: reg_cause_bd <= cop_reg_val_p3[31];
EPC: reg_epc <= cop_reg_val_p3;
default: ;
endcase
end
end
else if(!core_stall && i_except_start)
begin
reg_psr_ie <= reg_sr_ie;
reg_sr_ie <= 1'b0;
reg_cause_bd <= !i_except_dly_slt ? 1'b0 : 1'b1;
reg_epc <= !i_except_dly_slt ? i_except_raddr : i_except_raddr_dly;
intr_wait <= 1'b0;
end
end
/*************************** TIME STAMP COUNTER *******************************/
reg [2*`UPARC_REG_WIDTH-1:0] tsc_reg; /* Counter register */
reg [`UPARC_REG_WIDTH-1:0] tsc_latched_lo; /* Latched lower half */
reg [`UPARC_REG_WIDTH-1:0] tsc_latched_hi; /* Latched upper half */
/* Latch counter on read of lower half */
wire tsc_latch = (i_instr[31:26] == `UPARC_OP_COP0) &&
(i_instr[25:21] == `UPARC_COP0_MF) &&
(i_instr[15:11] == TSCLO) ? 1'b1 : 1'b0;
/* Counter */
always @(posedge clk or negedge nrst)
begin
if(!nrst)
begin
tsc_reg <= {(2*`UPARC_ADDR_WIDTH){1'b0}};
end
else
begin
tsc_reg <= tsc_reg + 1'b1;
end
end
/* Counter latch logic */
always @(posedge clk or negedge nrst)
begin
if(!nrst)
begin
tsc_latched_lo <= {(`UPARC_ADDR_WIDTH){1'b0}};
tsc_latched_hi <= {(`UPARC_ADDR_WIDTH){1'b0}};
end
else if(!core_stall && !i_nullify_decode && tsc_latch)
begin
tsc_latched_lo <= tsc_reg[`UPARC_REG_WIDTH-1:0];
tsc_latched_hi <= tsc_reg[2*`UPARC_REG_WIDTH-1:`UPARC_REG_WIDTH];
end
end
endmodule /* uparc_coproc0 */
|
//-----------------------------------------------------------------------------
// Copyright (C) 2014 iZsh <izsh at fail0verflow.com>
//
// This code is licensed to you under the terms of the GNU GPL, version 2 or,
// at your option, any later version. See the LICENSE.txt file for the text of
// the license.
//-----------------------------------------------------------------------------
// track min and max peak values (envelope follower)
//
// NB: the min value (resp. max value) is updated only when the next high peak
// (resp. low peak) is reached/detected, since you can't know it isn't a
// local minima (resp. maxima) until then.
// This also means the peaks are detected with an unpredictable delay.
// This algorithm therefore can't be used directly for realtime peak detections,
// but it can be used as a simple envelope follower.
module min_max_tracker(input clk, input [7:0] adc_d, input [7:0] threshold,
output [7:0] min, output [7:0] max);
reg [7:0] min_val = 255;
reg [7:0] max_val = 0;
reg [7:0] cur_min_val = 255;
reg [7:0] cur_max_val = 0;
reg [1:0] state = 0;
always @(posedge clk)
begin
case (state)
0:
begin
if (cur_max_val >= ({1'b0, adc_d} + threshold))
state <= 2;
else if (adc_d >= ({1'b0, cur_min_val} + threshold))
state <= 1;
if (cur_max_val <= adc_d)
cur_max_val <= adc_d;
else if (adc_d <= cur_min_val)
cur_min_val <= adc_d;
end
1:
begin
if (cur_max_val <= adc_d)
cur_max_val <= adc_d;
else if (({1'b0, adc_d} + threshold) <= cur_max_val) begin
state <= 2;
cur_min_val <= adc_d;
max_val <= cur_max_val;
end
end
2:
begin
if (adc_d <= cur_min_val)
cur_min_val <= adc_d;
else if (adc_d >= ({1'b0, cur_min_val} + threshold)) begin
state <= 1;
cur_max_val <= adc_d;
min_val <= cur_min_val;
end
end
endcase
end
assign min = min_val;
assign max = max_val;
endmodule
|
`timescale 100 ps / 100 ps
module tb_magnitude();
reg clk;
initial clk = 0;
always #10000 clk = ~clk;
wire [11:0] mag1, mag2;
reg [11:0] Y0, Y1, Y2, Y3;
magnitude magnitude_inst(.Y0(Y0), .Y1(Y1), .Y2(Y2), .Y3(Y3), .mag1(mag1), .mag2(mag2));
initial begin
@(posedge clk);
Y0 <= 12'b111111111101;
Y1 <= 12'b111111111110;
Y2 <= 12'b111111111111;
Y3 <= 12'b111111111110;
#10;
$display("Y0 = %d, Y1 = %d, Y2 = %d, Y3 = %d.", Y0, Y1, Y2, Y3);
@(posedge clk);
$display("mag1 = %d, mag2 = %d", mag1, mag2);
Y0 <= 12'b000000010110;
Y1 <= 12'b000001000100;
Y2 <= 12'b000001001110;
Y3 <= 12'b000011110011;
#10;
$display("Y0 = %d, Y1 = %d, Y2 = %d, Y3 = %d.", Y0, Y1, Y2, Y3);
@(posedge clk);
$display("mag1 = %d, mag2 = %d", mag1, mag2);
Y0 <= $random;
Y1 <= $random;
Y2 <= $random;
Y3 <= $random;
#10;
$display("Y0 = %d, Y1 = %d, Y2 = %d, Y3 = %d.", Y0, Y1, Y2, Y3);
@(posedge clk);
$display("mag1 = %d, mag2 = %d", mag1, mag2);
Y0 <= $random;
Y1 <= $random;
Y2 <= $random;
Y3 <= $random;
#10;
$display("Y0 = %d, Y1 = %d, Y2 = %d, Y3 = %d.", Y0, Y1, Y2, Y3);
@(posedge clk);
$display("mag1 = %d, mag2 = %d", mag1, mag2);
Y0 <= $random;
Y1 <= $random;
Y2 <= $random;
Y3 <= $random;
#10;
$display("Y0 = %d, Y1 = %d, Y2 = %d, Y3 = %d.", Y0, Y1, Y2, Y3);
@(posedge clk);
$display("mag1 = %d, mag2 = %d", mag1, mag2);
Y0 <= $random;
Y1 <= $random;
Y2 <= $random;
Y3 <= $random;
#10;
$display("Y0 = %d, Y1 = %d, Y2 = %d, Y3 = %d.", Y0, Y1, Y2, Y3);
@(posedge clk);
$display("mag1 = %d, mag2 = %d", mag1, mag2);
#1000 $finish;
end
endmodule
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O32AI_PP_SYMBOL_V
`define SKY130_FD_SC_LP__O32AI_PP_SYMBOL_V
/**
* o32ai: 3-input OR and 2-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & (B1 | B2))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__o32ai (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input B1 ,
input B2 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O32AI_PP_SYMBOL_V
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized Mux from 2:1 upto 16:1.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_mux #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_SEL_WIDTH = 4,
// Data width for comparator.
parameter integer C_DATA_WIDTH = 2
// Data width for comparator.
)
(
input wire [C_SEL_WIDTH-1:0] S,
input wire [(2**C_SEL_WIDTH)*C_DATA_WIDTH-1:0] A,
output wire [C_DATA_WIDTH-1:0] O
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar bit_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" || C_SEL_WIDTH < 3 ) begin : USE_RTL
assign O = A[(S)*C_DATA_WIDTH +: C_DATA_WIDTH];
end else begin : USE_FPGA
wire [C_DATA_WIDTH-1:0] C;
wire [C_DATA_WIDTH-1:0] D;
// Lower half recursively.
generic_baseblocks_v2_1_mux #
(
.C_FAMILY (C_FAMILY),
.C_SEL_WIDTH (C_SEL_WIDTH-1),
.C_DATA_WIDTH (C_DATA_WIDTH)
) mux_c_inst
(
.S (S[C_SEL_WIDTH-2:0]),
.A (A[(2**(C_SEL_WIDTH-1))*C_DATA_WIDTH-1 : 0]),
.O (C)
);
// Upper half recursively.
generic_baseblocks_v2_1_mux #
(
.C_FAMILY (C_FAMILY),
.C_SEL_WIDTH (C_SEL_WIDTH-1),
.C_DATA_WIDTH (C_DATA_WIDTH)
) mux_d_inst
(
.S (S[C_SEL_WIDTH-2:0]),
.A (A[(2**C_SEL_WIDTH)*C_DATA_WIDTH-1 : (2**(C_SEL_WIDTH-1))*C_DATA_WIDTH]),
.O (D)
);
// Generate instantiated generic_baseblocks_v2_1_mux components as required.
for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : NUM
if ( C_SEL_WIDTH == 4 ) begin : USE_F8
MUXF8 muxf8_inst
(
.I0 (C[bit_cnt]),
.I1 (D[bit_cnt]),
.S (S[C_SEL_WIDTH-1]),
.O (O[bit_cnt])
);
end else if ( C_SEL_WIDTH == 3 ) begin : USE_F7
MUXF7 muxf7_inst
(
.I0 (C[bit_cnt]),
.I1 (D[bit_cnt]),
.S (S[C_SEL_WIDTH-1]),
.O (O[bit_cnt])
);
end // C_SEL_WIDTH
end // end for bit_cnt
end
endgenerate
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:11:35 03/19/2015
// Design Name: fsm2
// Module Name: /home/lsriw/SR/Wojciech Gumula/repo/fsm2/tb_fsm2.v
// Project Name: fsm2
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: fsm2
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module load_file
(
output [7:0] out,
output send
);
integer file;
reg [7:0] c;
reg s;
reg [7:0] i = 0;
initial
begin
file=$fopen("data/input.data", "r");
for(i = 0; i < 16; i = i + 1)
begin
c=$fgetc(file);
s = 1;
#4;
s = 0;
#44;
end
$fclose(file);
end
assign out = c;
assign send = s;
endmodule
module save_file
(
input [7:0] c,
input received
);
integer file;
initial
begin
file=$fopen("data/output.ise", "wb");
repeat (16) begin
@(posedge received);
$fwrite(file, "%c", c);
end
$fwrite(file, "\n");
$fclose(file);
end
endmodule
module tb_fsm2;
// Inputs
reg clk;
reg rst; //reset jest wspólny dla uproszczenia układu
// Outputs
wire rxd;
wire [7:0] data;
wire [7:0] data_out;
wire received;
// Instantiate the Unit Under Test (UUT)
fsm2 uut (
.clk(clk),
.rst(rst),
.rxd(rxd),
.data(data_out),
.received(received)
);
fsm serial (
.clk(clk),
.send(send),
.data(data),
.txd(rxd),
.rst(rst)
);
load_file load (
.out(data),
.send(send)
);
save_file save (
.c(data_out),
.received(received)
);
initial begin
// Initialize Inputs
clk = 0;
rst = 0;
// Wait 100 ns for global reset to finish
#100;
end
always #2 clk = ~clk;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
wire one = '1;
wire z0 = 'z;
wire z1 = 'z;
wire z2 = 'z;
wire z3 = 'z;
wire tog = cyc[0];
// verilator lint_off PINMISSING
t_tri0 tri0a (.line(`__LINE__), .expval(1'b0)); // Pin missing
t_tri0 tri0b (.line(`__LINE__), .expval(1'b0), .tn());
t_tri0 tri0z (.line(`__LINE__), .expval(1'b0), .tn(z0));
t_tri0 tri0Z (.line(`__LINE__), .expval(1'b0), .tn(1'bz));
t_tri0 tri0c (.line(`__LINE__), .expval(1'b0), .tn(1'b0));
t_tri0 tri0d (.line(`__LINE__), .expval(1'b1), .tn(1'b1)); // Warning would be reasonable given tri0 connect
t_tri0 tri0e (.line(`__LINE__), .expval(1'b0), .tn(~one));
t_tri0 tri0f (.line(`__LINE__), .expval(1'b1), .tn(one));
t_tri0 tri0g (.line(`__LINE__), .expval(~cyc[0]), .tn(~tog));
t_tri0 tri0h (.line(`__LINE__), .expval(cyc[0]), .tn(tog));
t_tri1 tri1a (.line(`__LINE__), .expval(1'b1)); // Pin missing
t_tri1 tri1b (.line(`__LINE__), .expval(1'b1), .tn());
t_tri1 tri1z (.line(`__LINE__), .expval(1'b1), .tn(z1));
t_tri1 tri1Z (.line(`__LINE__), .expval(1'b1), .tn(1'bz));
t_tri1 tri1c (.line(`__LINE__), .expval(1'b0), .tn(1'b0)); // Warning would be reasonable given tri1 connect
t_tri1 tri1d (.line(`__LINE__), .expval(1'b1), .tn(1'b1));
t_tri1 tri1e (.line(`__LINE__), .expval(1'b0), .tn(~one));
t_tri1 tri1f (.line(`__LINE__), .expval(1'b1), .tn(one));
t_tri1 tri1g (.line(`__LINE__), .expval(~cyc[0]), .tn(~tog));
t_tri1 tri1h (.line(`__LINE__), .expval(cyc[0]), .tn(tog));
t_tri2 tri2a (.line(`__LINE__), .expval(1'b0)); // Pin missing
t_tri2 tri2b (.line(`__LINE__), .expval(1'b0), .tn());
t_tri2 tri2z (.line(`__LINE__), .expval(1'b0), .tn(z2));
t_tri2 tri2Z (.line(`__LINE__), .expval(1'b0), .tn(1'bz));
t_tri2 tri2c (.line(`__LINE__), .expval(1'b0), .tn(1'b0));
t_tri2 tri2d (.line(`__LINE__), .expval(1'b1), .tn(1'b1));
t_tri2 tri2e (.line(`__LINE__), .expval(1'b0), .tn(~one));
t_tri2 tri2f (.line(`__LINE__), .expval(1'b1), .tn(one));
t_tri2 tri2g (.line(`__LINE__), .expval(~cyc[0]), .tn(~tog));
t_tri2 tri2h (.line(`__LINE__), .expval(cyc[0]), .tn(tog));
t_tri3 tri3a (.line(`__LINE__), .expval(1'b1)); // Pin missing
t_tri3 tri3b (.line(`__LINE__), .expval(1'b1), .tn());
t_tri3 tri3z (.line(`__LINE__), .expval(1'b1), .tn(z3));
t_tri3 tri3Z (.line(`__LINE__), .expval(1'b1), .tn(1'bz));
t_tri3 tri3c (.line(`__LINE__), .expval(1'b0), .tn(1'b0));
t_tri3 tri3d (.line(`__LINE__), .expval(1'b1), .tn(1'b1));
t_tri3 tri3e (.line(`__LINE__), .expval(1'b0), .tn(~one));
t_tri3 tri3f (.line(`__LINE__), .expval(1'b1), .tn(one));
t_tri3 tri3g (.line(`__LINE__), .expval(~cyc[0]), .tn(~tog));
t_tri3 tri3h (.line(`__LINE__), .expval(cyc[0]), .tn(tog));
// verilator lint_on PINMISSING
// Test loop
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module t_tri0
(line, expval, tn);
input integer line;
input expval;
input tn; // Illegal to be inout; spec requires net connection to any inout
tri0 tn;
wire clk = t.clk;
always @(posedge clk) if (tn !== expval) begin
$display("%%Error: from line %0d got=%x exp=%x",line,tn,expval); $stop;
end
endmodule
module t_tri1
(line, expval, tn);
input integer line;
input expval;
input tn;
tri1 tn;
wire clk = t.clk;
always @(posedge clk) if (tn !== expval) begin
$display("%%Error: from line %0d got=%x exp=%x",line,tn,expval); $stop;
end
endmodule
module t_tri2
(line, expval, tn);
input integer line;
input expval;
input tn;
pulldown(tn);
wire clk = t.clk;
always @(posedge clk) if (tn !== expval) begin
$display("%%Error: from line %0d got=%x exp=%x",line,tn,expval); $stop;
end
endmodule
module t_tri3
(line, expval, tn);
input integer line;
input expval;
input tn;
pullup(tn);
wire clk = t.clk;
always @(negedge clk) if (tn !== expval) begin
$display("%%Error: from line %0d got=%x exp=%x",line,tn,expval); $stop;
end
endmodule
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_axi_slave.v
*
* Date : 2012-11
*
* Description : Model that acts as PS AXI Slave port interface.
* It uses AXI3 Slave BFM
*****************************************************************************/
module processing_system7_bfm_v2_0_axi_slave (
S_RESETN,
S_ARREADY,
S_AWREADY,
S_BVALID,
S_RLAST,
S_RVALID,
S_WREADY,
S_BRESP,
S_RRESP,
S_RDATA,
S_BID,
S_RID,
S_ACLK,
S_ARVALID,
S_AWVALID,
S_BREADY,
S_RREADY,
S_WLAST,
S_WVALID,
S_ARBURST,
S_ARLOCK,
S_ARSIZE,
S_AWBURST,
S_AWLOCK,
S_AWSIZE,
S_ARPROT,
S_AWPROT,
S_ARADDR,
S_AWADDR,
S_WDATA,
S_ARCACHE,
S_ARLEN,
S_AWCACHE,
S_AWLEN,
S_WSTRB,
S_ARID,
S_AWID,
S_WID,
S_AWQOS,
S_ARQOS,
SW_CLK,
WR_DATA_ACK_OCM,
WR_DATA_ACK_DDR,
WR_ADDR,
WR_DATA,
WR_BYTES,
WR_DATA_VALID_OCM,
WR_DATA_VALID_DDR,
WR_QOS,
RD_QOS,
RD_REQ_DDR,
RD_REQ_OCM,
RD_REQ_REG,
RD_ADDR,
RD_DATA_OCM,
RD_DATA_DDR,
RD_DATA_REG,
RD_BYTES,
RD_DATA_VALID_OCM,
RD_DATA_VALID_DDR,
RD_DATA_VALID_REG
);
parameter enable_this_port = 0;
parameter slave_name = "Slave";
parameter data_bus_width = 32;
parameter address_bus_width = 32;
parameter id_bus_width = 6;
parameter slave_base_address = 0;
parameter slave_high_address = 4;
parameter max_outstanding_transactions = 8;
parameter exclusive_access_supported = 0;
parameter max_wr_outstanding_transactions = 8;
parameter max_rd_outstanding_transactions = 8;
`include "processing_system7_bfm_v2_0_local_params.v"
/* Local parameters only for this module */
/* Internal counters that are used as Read/Write pointers to the fifo's that store all the transaction info on all channles.
This parameter is used to define the width of these pointers --> depending on Maximum outstanding transactions supported.
1-bit extra width than the no.of.bits needed to represent the outstanding transactions
Extra bit helps in generating the empty and full flags
*/
parameter int_wr_cntr_width = clogb2(max_wr_outstanding_transactions)+1;
parameter int_rd_cntr_width = clogb2(max_rd_outstanding_transactions)+1;
/* RESP data */
parameter rsp_fifo_bits = axi_rsp_width+id_bus_width;
parameter rsp_lsb = 0;
parameter rsp_msb = axi_rsp_width-1;
parameter rsp_id_lsb = rsp_msb + 1;
parameter rsp_id_msb = rsp_id_lsb + id_bus_width-1;
input S_RESETN;
output S_ARREADY;
output S_AWREADY;
output S_BVALID;
output S_RLAST;
output S_RVALID;
output S_WREADY;
output [axi_rsp_width-1:0] S_BRESP;
output [axi_rsp_width-1:0] S_RRESP;
output [data_bus_width-1:0] S_RDATA;
output [id_bus_width-1:0] S_BID;
output [id_bus_width-1:0] S_RID;
input S_ACLK;
input S_ARVALID;
input S_AWVALID;
input S_BREADY;
input S_RREADY;
input S_WLAST;
input S_WVALID;
input [axi_brst_type_width-1:0] S_ARBURST;
input [axi_lock_width-1:0] S_ARLOCK;
input [axi_size_width-1:0] S_ARSIZE;
input [axi_brst_type_width-1:0] S_AWBURST;
input [axi_lock_width-1:0] S_AWLOCK;
input [axi_size_width-1:0] S_AWSIZE;
input [axi_prot_width-1:0] S_ARPROT;
input [axi_prot_width-1:0] S_AWPROT;
input [address_bus_width-1:0] S_ARADDR;
input [address_bus_width-1:0] S_AWADDR;
input [data_bus_width-1:0] S_WDATA;
input [axi_cache_width-1:0] S_ARCACHE;
input [axi_cache_width-1:0] S_ARLEN;
input [axi_qos_width-1:0] S_ARQOS;
input [axi_cache_width-1:0] S_AWCACHE;
input [axi_len_width-1:0] S_AWLEN;
input [axi_qos_width-1:0] S_AWQOS;
input [(data_bus_width/8)-1:0] S_WSTRB;
input [id_bus_width-1:0] S_ARID;
input [id_bus_width-1:0] S_AWID;
input [id_bus_width-1:0] S_WID;
input SW_CLK;
input WR_DATA_ACK_DDR, WR_DATA_ACK_OCM;
output reg WR_DATA_VALID_DDR, WR_DATA_VALID_OCM;
output reg [max_burst_bits-1:0] WR_DATA;
output reg [addr_width-1:0] WR_ADDR;
output reg [max_burst_bytes_width:0] WR_BYTES;
output reg RD_REQ_OCM, RD_REQ_DDR, RD_REQ_REG;
output reg [addr_width-1:0] RD_ADDR;
input [max_burst_bits-1:0] RD_DATA_DDR,RD_DATA_OCM, RD_DATA_REG;
output reg[max_burst_bytes_width:0] RD_BYTES;
input RD_DATA_VALID_OCM,RD_DATA_VALID_DDR, RD_DATA_VALID_REG;
output reg [axi_qos_width-1:0] WR_QOS, RD_QOS;
wire net_ARVALID;
wire net_AWVALID;
wire net_WVALID;
real s_aclk_period;
cdn_axi3_slave_bfm #(slave_name,
data_bus_width,
address_bus_width,
id_bus_width,
slave_base_address,
(slave_high_address- slave_base_address),
max_outstanding_transactions,
0, ///MEMORY_MODEL_MODE,
exclusive_access_supported)
slave (.ACLK (S_ACLK),
.ARESETn (S_RESETN), /// confirm this
// Write Address Channel
.AWID (S_AWID),
.AWADDR (S_AWADDR),
.AWLEN (S_AWLEN),
.AWSIZE (S_AWSIZE),
.AWBURST (S_AWBURST),
.AWLOCK (S_AWLOCK),
.AWCACHE (S_AWCACHE),
.AWPROT (S_AWPROT),
.AWVALID (net_AWVALID),
.AWREADY (S_AWREADY),
// Write Data Channel Signals.
.WID (S_WID),
.WDATA (S_WDATA),
.WSTRB (S_WSTRB),
.WLAST (S_WLAST),
.WVALID (net_WVALID),
.WREADY (S_WREADY),
// Write Response Channel Signals.
.BID (S_BID),
.BRESP (S_BRESP),
.BVALID (S_BVALID),
.BREADY (S_BREADY),
// Read Address Channel Signals.
.ARID (S_ARID),
.ARADDR (S_ARADDR),
.ARLEN (S_ARLEN),
.ARSIZE (S_ARSIZE),
.ARBURST (S_ARBURST),
.ARLOCK (S_ARLOCK),
.ARCACHE (S_ARCACHE),
.ARPROT (S_ARPROT),
.ARVALID (net_ARVALID),
.ARREADY (S_ARREADY),
// Read Data Channel Signals.
.RID (S_RID),
.RDATA (S_RDATA),
.RRESP (S_RRESP),
.RLAST (S_RLAST),
.RVALID (S_RVALID),
.RREADY (S_RREADY));
/* Latency type and Debug/Error Control */
reg[1:0] latency_type = RANDOM_CASE;
reg DEBUG_INFO = 1;
reg STOP_ON_ERROR = 1'b1;
/* WR_FIFO stores 32-bit address, valid data and valid bytes for each AXI Write burst transaction */
reg [wr_fifo_data_bits-1:0] wr_fifo [0:max_wr_outstanding_transactions-1];
reg [int_wr_cntr_width-1:0] wr_fifo_wr_ptr = 0, wr_fifo_rd_ptr = 0;
wire wr_fifo_empty;
/* Store the awvalid receive time --- necessary for calculating the latency in sending the bresp*/
reg [7:0] aw_time_cnt = 0, bresp_time_cnt = 0;
real awvalid_receive_time[0:max_wr_outstanding_transactions]; // store the time when a new awvalid is received
reg awvalid_flag[0:max_wr_outstanding_transactions]; // indicates awvalid is received
/* Address Write Channel handshake*/
reg[int_wr_cntr_width-1:0] aw_cnt = 0;// count of awvalid
/* various FIFOs for storing the ADDR channel info */
reg [axi_size_width-1:0] awsize [0:max_wr_outstanding_transactions-1];
reg [axi_prot_width-1:0] awprot [0:max_wr_outstanding_transactions-1];
reg [axi_lock_width-1:0] awlock [0:max_wr_outstanding_transactions-1];
reg [axi_cache_width-1:0] awcache [0:max_wr_outstanding_transactions-1];
reg [axi_brst_type_width-1:0] awbrst [0:max_wr_outstanding_transactions-1];
reg [axi_len_width-1:0] awlen [0:max_wr_outstanding_transactions-1];
reg aw_flag [0:max_wr_outstanding_transactions-1];
reg [addr_width-1:0] awaddr [0:max_wr_outstanding_transactions-1];
reg [id_bus_width-1:0] awid [0:max_wr_outstanding_transactions-1];
reg [axi_qos_width-1:0] awqos [0:max_wr_outstanding_transactions-1];
wire aw_fifo_full; // indicates awvalid_fifo is full (max outstanding transactions reached)
/* internal fifos to store burst write data, ID & strobes*/
reg [(data_bus_width*axi_burst_len)-1:0] burst_data [0:max_wr_outstanding_transactions-1];
reg [max_burst_bytes_width:0] burst_valid_bytes [0:max_wr_outstanding_transactions-1]; /// total valid bytes received in a complete burst transfer
reg wlast_flag [0:max_wr_outstanding_transactions-1]; // flag to indicate WLAST received
wire wd_fifo_full;
/* Write Data Channel and Write Response handshake signals*/
reg [int_wr_cntr_width-1:0] wd_cnt = 0;
reg [(data_bus_width*axi_burst_len)-1:0] aligned_wr_data;
reg [addr_width-1:0] aligned_wr_addr;
reg [max_burst_bytes_width:0] valid_data_bytes;
reg [int_wr_cntr_width-1:0] wr_bresp_cnt = 0;
reg [axi_rsp_width-1:0] bresp;
reg [rsp_fifo_bits-1:0] fifo_bresp [0:max_wr_outstanding_transactions-1]; // store the ID and its corresponding response
reg enable_write_bresp;
reg [int_wr_cntr_width-1:0] rd_bresp_cnt = 0;
integer wr_latency_count;
reg wr_delayed;
wire bresp_fifo_empty;
/* states for managing read/write to WR_FIFO */
parameter SEND_DATA = 0, WAIT_ACK = 1;
reg state;
/* Qos*/
reg [axi_qos_width-1:0] ar_qos, aw_qos;
initial begin
if(DEBUG_INFO) begin
if(enable_this_port)
$display("[%0d] : %0s : %0s : Port is ENABLED.",$time, DISP_INFO, slave_name);
else
$display("[%0d] : %0s : %0s : Port is DISABLED.",$time, DISP_INFO, slave_name);
end
end
initial slave.set_disable_reset_value_checks(1);
initial begin
repeat(2) @(posedge S_ACLK);
if(!enable_this_port) begin
slave.set_channel_level_info(0);
slave.set_function_level_info(0);
end
slave.RESPONSE_TIMEOUT = 0;
end
/*--------------------------------------------------------------------------------*/
/* Set Latency type to be used */
task set_latency_type;
input[1:0] lat;
begin
if(enable_this_port)
latency_type = lat;
else begin
if(DEBUG_INFO)
$display("[%0d] : %0s : %0s : Port is disabled. 'Latency Profile' will not be set...",$time, DISP_WARN, slave_name);
end
end
endtask
/*--------------------------------------------------------------------------------*/
/* Set ARQoS to be used */
task set_arqos;
input[axi_qos_width-1:0] qos;
begin
if(enable_this_port)
ar_qos = qos;
else begin
if(DEBUG_INFO)
$display("[%0d] : %0s : %0s : Port is disabled. 'ARQOS' will not be set...",$time, DISP_WARN, slave_name);
end
end
endtask
/*--------------------------------------------------------------------------------*/
/* Set AWQoS to be used */
task set_awqos;
input[axi_qos_width-1:0] qos;
begin
if(enable_this_port)
aw_qos = qos;
else begin
if(DEBUG_INFO)
$display("[%0d] : %0s : %0s : Port is disabled. 'AWQOS' will not be set...",$time, DISP_WARN, slave_name);
end
end
endtask
/*--------------------------------------------------------------------------------*/
/* get the wr latency number */
function [31:0] get_wr_lat_number;
input dummy;
reg[1:0] temp;
begin
case(latency_type)
BEST_CASE : if(slave_name == axi_acp_name) get_wr_lat_number = acp_wr_min; else get_wr_lat_number = gp_wr_min;
AVG_CASE : if(slave_name == axi_acp_name) get_wr_lat_number = acp_wr_avg; else get_wr_lat_number = gp_wr_avg;
WORST_CASE : if(slave_name == axi_acp_name) get_wr_lat_number = acp_wr_max; else get_wr_lat_number = gp_wr_max;
default : begin // RANDOM_CASE
temp = $random;
case(temp)
2'b00 : if(slave_name == axi_acp_name) get_wr_lat_number = ($random()%10+ acp_wr_min); else get_wr_lat_number = ($random()%10+ gp_wr_min);
2'b01 : if(slave_name == axi_acp_name) get_wr_lat_number = ($random()%40+ acp_wr_avg); else get_wr_lat_number = ($random()%40+ gp_wr_avg);
default : if(slave_name == axi_acp_name) get_wr_lat_number = ($random()%60+ acp_wr_max); else get_wr_lat_number = ($random()%60+ gp_wr_max);
endcase
end
endcase
end
endfunction
/*--------------------------------------------------------------------------------*/
/* get the rd latency number */
function [31:0] get_rd_lat_number;
input dummy;
reg[1:0] temp;
begin
case(latency_type)
BEST_CASE : if(slave_name == axi_acp_name) get_rd_lat_number = acp_rd_min; else get_rd_lat_number = gp_rd_min;
AVG_CASE : if(slave_name == axi_acp_name) get_rd_lat_number = acp_rd_avg; else get_rd_lat_number = gp_rd_avg;
WORST_CASE : if(slave_name == axi_acp_name) get_rd_lat_number = acp_rd_max; else get_rd_lat_number = gp_rd_max;
default : begin // RANDOM_CASE
temp = $random;
case(temp)
2'b00 : if(slave_name == axi_acp_name) get_rd_lat_number = ($random()%10+ acp_rd_min); else get_rd_lat_number = ($random()%10+ gp_rd_min);
2'b01 : if(slave_name == axi_acp_name) get_rd_lat_number = ($random()%40+ acp_rd_avg); else get_rd_lat_number = ($random()%40+ gp_rd_avg);
default : if(slave_name == axi_acp_name) get_rd_lat_number = ($random()%60+ acp_rd_max); else get_rd_lat_number = ($random()%60+ gp_rd_max);
endcase
end
endcase
end
endfunction
/*--------------------------------------------------------------------------------*/
/* Store the Clock cycle time period */
always@(S_RESETN)
begin
if(S_RESETN) begin
@(posedge S_ACLK);
s_aclk_period = $time;
@(posedge S_ACLK);
s_aclk_period = $time - s_aclk_period;
end
end
/*--------------------------------------------------------------------------------*/
/* Check for any WRITE/READs when this port is disabled */
always@(S_AWVALID or S_WVALID or S_ARVALID)
begin
if((S_AWVALID | S_WVALID | S_ARVALID) && !enable_this_port) begin
$display("[%0d] : %0s : %0s : Port is disabled. AXI transaction is initiated on this port ...\nSimulation will halt ..",$time, DISP_ERR, slave_name);
$stop;
end
end
/*--------------------------------------------------------------------------------*/
assign net_ARVALID = enable_this_port ? S_ARVALID : 1'b0;
assign net_AWVALID = enable_this_port ? S_AWVALID : 1'b0;
assign net_WVALID = enable_this_port ? S_WVALID : 1'b0;
assign wr_fifo_empty = (wr_fifo_wr_ptr === wr_fifo_rd_ptr)?1'b1: 1'b0;
assign aw_fifo_full = ((aw_cnt[int_wr_cntr_width-1] !== rd_bresp_cnt[int_wr_cntr_width-1]) && (aw_cnt[int_wr_cntr_width-2:0] === rd_bresp_cnt[int_wr_cntr_width-2:0]))?1'b1 :1'b0; /// complete this
assign wd_fifo_full = ((wd_cnt[int_wr_cntr_width-1] !== rd_bresp_cnt[int_wr_cntr_width-1]) && (wd_cnt[int_wr_cntr_width-2:0] === rd_bresp_cnt[int_wr_cntr_width-2:0]))?1'b1 :1'b0; /// complete this
assign bresp_fifo_empty = (wr_bresp_cnt === rd_bresp_cnt)?1'b1:1'b0;
/* Store the awvalid receive time --- necessary for calculating the bresp latency */
always@(negedge S_RESETN or S_AWID or S_AWADDR or S_AWVALID )
begin
if(!S_RESETN)
aw_time_cnt <= 0;
else begin
if(S_AWVALID) begin
awvalid_receive_time[aw_time_cnt] <= $time;
awvalid_flag[aw_time_cnt] <= 1'b1;
aw_time_cnt <= aw_time_cnt + 1;
if(aw_time_cnt === max_wr_outstanding_transactions) aw_time_cnt <= 0;
end
end // else
end /// always
/*--------------------------------------------------------------------------------*/
always@(posedge S_ACLK)
begin
if(net_AWVALID && S_AWREADY) begin
if(S_AWQOS === 0) awqos[aw_cnt[int_wr_cntr_width-2:0]] = aw_qos;
else awqos[aw_cnt[int_wr_cntr_width-2:0]] = S_AWQOS;
end
end
/*--------------------------------------------------------------------------------*/
always@(aw_fifo_full)
begin
if(aw_fifo_full && DEBUG_INFO)
$display("[%0d] : %0s : %0s : Reached the maximum outstanding Write transactions limit (%0d). Blocking all future Write transactions until at least 1 of the outstanding Write transaction has completed.",$time, DISP_INFO, slave_name,max_wr_outstanding_transactions);
end
/*--------------------------------------------------------------------------------*/
/* Address Write Channel handshake*/
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN) begin
aw_cnt <= 0;
end else begin
if(!aw_fifo_full) begin
slave.RECEIVE_WRITE_ADDRESS(0,
id_invalid,
awaddr[aw_cnt[int_wr_cntr_width-2:0]],
awlen[aw_cnt[int_wr_cntr_width-2:0]],
awsize[aw_cnt[int_wr_cntr_width-2:0]],
awbrst[aw_cnt[int_wr_cntr_width-2:0]],
awlock[aw_cnt[int_wr_cntr_width-2:0]],
awcache[aw_cnt[int_wr_cntr_width-2:0]],
awprot[aw_cnt[int_wr_cntr_width-2:0]],
awid[aw_cnt[int_wr_cntr_width-2:0]]); /// sampled valid ID.
aw_flag[aw_cnt[int_wr_cntr_width-2:0]] <= 1;
aw_cnt <= aw_cnt + 1;
if(aw_cnt[int_wr_cntr_width-2:0] === (max_wr_outstanding_transactions-1)) begin
aw_cnt[int_wr_cntr_width-1] <= ~aw_cnt[int_wr_cntr_width-1];
aw_cnt[int_wr_cntr_width-2:0] <= 0;
end
end // if (!aw_fifo_full)
end /// if else
end /// always
/*--------------------------------------------------------------------------------*/
/* Write Data Channel Handshake */
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN) begin
wd_cnt <= 0;
end else begin
if(!wd_fifo_full && S_WVALID) begin
slave.RECEIVE_WRITE_BURST_NO_CHECKS(S_WID,
burst_data[wd_cnt[int_wr_cntr_width-2:0]],
burst_valid_bytes[wd_cnt[int_wr_cntr_width-2:0]]);
wlast_flag[wd_cnt[int_wr_cntr_width-2:0]] <= 1'b1;
wd_cnt <= wd_cnt + 1;
if(wd_cnt[int_wr_cntr_width-2:0] === (max_wr_outstanding_transactions-1)) begin
wd_cnt[int_wr_cntr_width-1] <= ~wd_cnt[int_wr_cntr_width-1];
wd_cnt[int_wr_cntr_width-2:0] <= 0;
end
end /// if
end /// else
end /// always
/*--------------------------------------------------------------------------------*/
/* Align the wrap data for write transaction */
task automatic get_wrap_aligned_wr_data;
output [(data_bus_width*axi_burst_len)-1:0] aligned_data;
output [addr_width-1:0] start_addr; /// aligned start address
input [addr_width-1:0] addr;
input [(data_bus_width*axi_burst_len)-1:0] b_data;
input [max_burst_bytes_width:0] v_bytes;
reg [(data_bus_width*axi_burst_len)-1:0] temp_data, wrp_data;
integer wrp_bytes;
integer i;
begin
start_addr = (addr/v_bytes) * v_bytes;
wrp_bytes = addr - start_addr;
wrp_data = b_data;
temp_data = 0;
wrp_data = wrp_data << ((data_bus_width*axi_burst_len) - (v_bytes*8));
while(wrp_bytes > 0) begin /// get the data that is wrapped
temp_data = temp_data << 8;
temp_data[7:0] = wrp_data[(data_bus_width*axi_burst_len)-1 : (data_bus_width*axi_burst_len)-8];
wrp_data = wrp_data << 8;
wrp_bytes = wrp_bytes - 1;
end
wrp_bytes = addr - start_addr;
wrp_data = b_data << (wrp_bytes*8);
aligned_data = (temp_data | wrp_data);
end
endtask
/*--------------------------------------------------------------------------------*/
/* Calculate the Response for each read/write transaction */
function [axi_rsp_width-1:0] calculate_resp;
input rd_wr; // indicates Read(1) or Write(0) transaction
input [addr_width-1:0] awaddr;
input [axi_prot_width-1:0] awprot;
reg [axi_rsp_width-1:0] rsp;
begin
rsp = AXI_OK;
/* Address Decode */
if(decode_address(awaddr) === INVALID_MEM_TYPE) begin
rsp = AXI_SLV_ERR; //slave error
$display("[%0d] : %0s : %0s : AXI Access to Invalid location(0x%0h) ",$time, DISP_ERR, slave_name, awaddr);
end
if(!rd_wr && decode_address(awaddr) === REG_MEM) begin
rsp = AXI_SLV_ERR; //slave error
$display("[%0d] : %0s : %0s : AXI Write to Register Map(0x%0h) is not supported ",$time, DISP_ERR, slave_name, awaddr);
end
if(secure_access_enabled && awprot[1])
rsp = AXI_DEC_ERR; // decode error
calculate_resp = rsp;
end
endfunction
/*--------------------------------------------------------------------------------*/
/* Store the Write response for each write transaction */
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN) begin
wr_bresp_cnt <= 0;
wr_fifo_wr_ptr <= 0;
end else begin
enable_write_bresp = aw_flag[wr_bresp_cnt[int_wr_cntr_width-2:0]] && wlast_flag[wr_bresp_cnt[int_wr_cntr_width-2:0]];
/* calculate bresp only when AWVALID && WLAST is received */
if(enable_write_bresp) begin
aw_flag[wr_bresp_cnt[int_wr_cntr_width-2:0]] <= 0;
wlast_flag[wr_bresp_cnt[int_wr_cntr_width-2:0]] <= 0;
bresp = calculate_resp(1'b0, awaddr[wr_bresp_cnt[int_wr_cntr_width-2:0]],awprot[wr_bresp_cnt[int_wr_cntr_width-2:0]]);
fifo_bresp[wr_bresp_cnt[int_wr_cntr_width-2:0]] <= {awid[wr_bresp_cnt[int_wr_cntr_width-2:0]],bresp};
/* Fill WR data FIFO */
if(bresp === AXI_OK) begin
if(awbrst[wr_bresp_cnt[int_wr_cntr_width-2:0]] === AXI_WRAP) begin /// wrap type? then align the data
get_wrap_aligned_wr_data(aligned_wr_data,aligned_wr_addr, awaddr[wr_bresp_cnt[int_wr_cntr_width-2:0]],burst_data[wr_bresp_cnt[int_wr_cntr_width-2:0]],burst_valid_bytes[wr_bresp_cnt[int_wr_cntr_width-2:0]]); /// gives wrapped start address
end else begin
aligned_wr_data = burst_data[wr_bresp_cnt[int_wr_cntr_width-2:0]];
aligned_wr_addr = awaddr[wr_bresp_cnt[int_wr_cntr_width-2:0]] ;
end
valid_data_bytes = burst_valid_bytes[wr_bresp_cnt[int_wr_cntr_width-2:0]];
end else
valid_data_bytes = 0;
wr_fifo[wr_fifo_wr_ptr[int_wr_cntr_width-2:0]] = {awqos[wr_bresp_cnt[int_wr_cntr_width-2:0]], aligned_wr_data, aligned_wr_addr, valid_data_bytes};
wr_fifo_wr_ptr = wr_fifo_wr_ptr + 1;
wr_bresp_cnt <= wr_bresp_cnt+1;
if(wr_bresp_cnt[int_wr_cntr_width-2:0] === (max_wr_outstanding_transactions-1)) begin
wr_bresp_cnt[int_wr_cntr_width-1] <= ~ wr_bresp_cnt[int_wr_cntr_width-1];
wr_bresp_cnt[int_wr_cntr_width-2:0] <= 0;
end
end
end // else
end // always
/*--------------------------------------------------------------------------------*/
/* Send Write Response Channel handshake */
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN) begin
rd_bresp_cnt <= 0;
wr_latency_count = get_wr_lat_number(1);
wr_delayed = 0;
bresp_time_cnt <= 0;
end else begin
wr_delayed = 1'b0;
if(awvalid_flag[bresp_time_cnt] && (($time - awvalid_receive_time[bresp_time_cnt])/s_aclk_period >= wr_latency_count))
wr_delayed = 1;
if(!bresp_fifo_empty && wr_delayed) begin
slave.SEND_WRITE_RESPONSE(fifo_bresp[rd_bresp_cnt[int_wr_cntr_width-2:0]][rsp_id_msb : rsp_id_lsb], // ID
fifo_bresp[rd_bresp_cnt[int_wr_cntr_width-2:0]][rsp_msb : rsp_lsb] // Response
);
wr_delayed = 0;
awvalid_flag[bresp_time_cnt] = 1'b0;
bresp_time_cnt <= bresp_time_cnt+1;
rd_bresp_cnt <= rd_bresp_cnt + 1;
if(rd_bresp_cnt[int_wr_cntr_width-2:0] === (max_wr_outstanding_transactions-1)) begin
rd_bresp_cnt[int_wr_cntr_width-1] <= ~ rd_bresp_cnt[int_wr_cntr_width-1];
rd_bresp_cnt[int_wr_cntr_width-2:0] <= 0;
end
if(bresp_time_cnt === max_wr_outstanding_transactions) begin
bresp_time_cnt <= 0;
end
wr_latency_count = get_wr_lat_number(1);
end
end // else
end//always
/*--------------------------------------------------------------------------------*/
/* Reading from the wr_fifo */
always@(negedge S_RESETN or posedge SW_CLK) begin
if(!S_RESETN) begin
WR_DATA_VALID_DDR = 1'b0;
WR_DATA_VALID_OCM = 1'b0;
wr_fifo_rd_ptr = 0;
state = SEND_DATA;
WR_QOS = 0;
end else begin
case(state)
SEND_DATA :begin
state = SEND_DATA;
WR_DATA_VALID_OCM = 0;
WR_DATA_VALID_DDR = 0;
if(!wr_fifo_empty) begin
WR_DATA = wr_fifo[wr_fifo_rd_ptr[int_wr_cntr_width-2:0]][wr_data_msb : wr_data_lsb];
WR_ADDR = wr_fifo[wr_fifo_rd_ptr[int_wr_cntr_width-2:0]][wr_addr_msb : wr_addr_lsb];
WR_BYTES = wr_fifo[wr_fifo_rd_ptr[int_wr_cntr_width-2:0]][wr_bytes_msb : wr_bytes_lsb];
WR_QOS = wr_fifo[wr_fifo_rd_ptr[int_wr_cntr_width-2:0]][wr_qos_msb : wr_qos_lsb];
state = WAIT_ACK;
case (decode_address(wr_fifo[wr_fifo_rd_ptr[int_wr_cntr_width-2:0]][wr_addr_msb : wr_addr_lsb]))
OCM_MEM : WR_DATA_VALID_OCM = 1;
DDR_MEM : WR_DATA_VALID_DDR = 1;
default : state = SEND_DATA;
endcase
wr_fifo_rd_ptr = wr_fifo_rd_ptr+1;
end
end
WAIT_ACK :begin
state = WAIT_ACK;
if(WR_DATA_ACK_OCM | WR_DATA_ACK_DDR) begin
WR_DATA_VALID_OCM = 1'b0;
WR_DATA_VALID_DDR = 1'b0;
state = SEND_DATA;
end
end
endcase
end
end
/*--------------------------------------------------------------------------------*/
/*-------------------------------- WRITE HANDSHAKE END ----------------------------------------*/
/*-------------------------------- READ HANDSHAKE ---------------------------------------------*/
/* READ CHANNELS */
/* Store the arvalid receive time --- necessary for calculating latency in sending the rresp latency */
reg [7:0] ar_time_cnt = 0,rresp_time_cnt = 0;
real arvalid_receive_time[0:max_rd_outstanding_transactions]; // store the time when a new arvalid is received
reg arvalid_flag[0:max_rd_outstanding_transactions]; // store the time when a new arvalid is received
reg [int_rd_cntr_width-1:0] ar_cnt = 0; // counter for arvalid info
/* various FIFOs for storing the ADDR channel info */
reg [axi_size_width-1:0] arsize [0:max_rd_outstanding_transactions-1];
reg [axi_prot_width-1:0] arprot [0:max_rd_outstanding_transactions-1];
reg [axi_brst_type_width-1:0] arbrst [0:max_rd_outstanding_transactions-1];
reg [axi_len_width-1:0] arlen [0:max_rd_outstanding_transactions-1];
reg [axi_cache_width-1:0] arcache [0:max_rd_outstanding_transactions-1];
reg [axi_lock_width-1:0] arlock [0:max_rd_outstanding_transactions-1];
reg ar_flag [0:max_rd_outstanding_transactions-1];
reg [addr_width-1:0] araddr [0:max_rd_outstanding_transactions-1];
reg [id_bus_width-1:0] arid [0:max_rd_outstanding_transactions-1];
reg [axi_qos_width-1:0] arqos [0:max_rd_outstanding_transactions-1];
wire ar_fifo_full; // indicates arvalid_fifo is full (max outstanding transactions reached)
reg [int_rd_cntr_width-1:0] rd_cnt = 0;
reg [int_rd_cntr_width-1:0] wr_rresp_cnt = 0;
reg [axi_rsp_width-1:0] rresp;
reg [rsp_fifo_bits-1:0] fifo_rresp [0:max_rd_outstanding_transactions-1]; // store the ID and its corresponding response
/* Send Read Response & Data Channel handshake */
integer rd_latency_count;
reg rd_delayed;
reg [max_burst_bits-1:0] read_fifo [0:max_rd_outstanding_transactions-1]; /// Store only AXI Burst Data ..
reg [int_rd_cntr_width-1:0] rd_fifo_wr_ptr = 0, rd_fifo_rd_ptr = 0;
wire read_fifo_full;
assign read_fifo_full = (rd_fifo_wr_ptr[int_rd_cntr_width-1] !== rd_fifo_rd_ptr[int_rd_cntr_width-1] && rd_fifo_wr_ptr[int_rd_cntr_width-2:0] === rd_fifo_rd_ptr[int_rd_cntr_width-2:0])?1'b1: 1'b0;
assign read_fifo_empty = (rd_fifo_wr_ptr === rd_fifo_rd_ptr)?1'b1: 1'b0;
assign ar_fifo_full = ((ar_cnt[int_rd_cntr_width-1] !== rd_cnt[int_rd_cntr_width-1]) && (ar_cnt[int_rd_cntr_width-2:0] === rd_cnt[int_rd_cntr_width-2:0]))?1'b1 :1'b0;
/* Store the arvalid receive time --- necessary for calculating the bresp latency */
always@(negedge S_RESETN or S_ARID or S_ARADDR or S_ARVALID )
begin
if(!S_RESETN)
ar_time_cnt <= 0;
else begin
if(S_ARVALID) begin
arvalid_receive_time[ar_time_cnt] <= $time;
arvalid_flag[ar_time_cnt] <= 1'b1;
ar_time_cnt <= ar_time_cnt + 1;
if(ar_time_cnt === max_rd_outstanding_transactions)
ar_time_cnt <= 0;
end
end // else
end /// always
/*--------------------------------------------------------------------------------*/
always@(posedge S_ACLK)
begin
if(net_ARVALID && S_ARREADY) begin
if(S_ARQOS === 0) arqos[aw_cnt[int_rd_cntr_width-2:0]] = ar_qos;
else arqos[aw_cnt[int_rd_cntr_width-2:0]] = S_ARQOS;
end
end
/*--------------------------------------------------------------------------------*/
always@(ar_fifo_full)
begin
if(ar_fifo_full && DEBUG_INFO)
$display("[%0d] : %0s : %0s : Reached the maximum outstanding Read transactions limit (%0d). Blocking all future Read transactions until at least 1 of the outstanding Read transaction has completed.",$time, DISP_INFO, slave_name,max_rd_outstanding_transactions);
end
/*--------------------------------------------------------------------------------*/
/* Address Read Channel handshake*/
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN) begin
ar_cnt <= 0;
end else begin
if(!ar_fifo_full) begin
slave.RECEIVE_READ_ADDRESS(0,
id_invalid,
araddr[ar_cnt[int_rd_cntr_width-2:0]],
arlen[ar_cnt[int_rd_cntr_width-2:0]],
arsize[ar_cnt[int_rd_cntr_width-2:0]],
arbrst[ar_cnt[int_rd_cntr_width-2:0]],
arlock[ar_cnt[int_rd_cntr_width-2:0]],
arcache[ar_cnt[int_rd_cntr_width-2:0]],
arprot[ar_cnt[int_rd_cntr_width-2:0]],
arid[ar_cnt[int_rd_cntr_width-2:0]]); /// sampled valid ID.
ar_flag[ar_cnt[int_rd_cntr_width-2:0]] <= 1'b1;
ar_cnt <= ar_cnt+1;
if(ar_cnt[int_rd_cntr_width-2:0] === max_rd_outstanding_transactions-1) begin
ar_cnt[int_rd_cntr_width-1] <= ~ ar_cnt[int_rd_cntr_width-1];
ar_cnt[int_rd_cntr_width-2:0] <= 0;
end
end /// if(!ar_fifo_full)
end /// if else
end /// always*/
/*--------------------------------------------------------------------------------*/
/* Align Wrap data for read transaction*/
task automatic get_wrap_aligned_rd_data;
output [(data_bus_width*axi_burst_len)-1:0] aligned_data;
input [addr_width-1:0] addr;
input [(data_bus_width*axi_burst_len)-1:0] b_data;
input [max_burst_bytes_width:0] v_bytes;
reg [addr_width-1:0] start_addr;
reg [(data_bus_width*axi_burst_len)-1:0] temp_data, wrp_data;
integer wrp_bytes;
integer i;
begin
start_addr = (addr/v_bytes) * v_bytes;
wrp_bytes = addr - start_addr;
wrp_data = b_data;
temp_data = 0;
while(wrp_bytes > 0) begin /// get the data that is wrapped
temp_data = temp_data >> 8;
temp_data[(data_bus_width*axi_burst_len)-1 : (data_bus_width*axi_burst_len)-8] = wrp_data[7:0];
wrp_data = wrp_data >> 8;
wrp_bytes = wrp_bytes - 1;
end
temp_data = temp_data >> ((data_bus_width*axi_burst_len) - (v_bytes*8));
wrp_bytes = addr - start_addr;
wrp_data = b_data >> (wrp_bytes*8);
aligned_data = (temp_data | wrp_data);
end
endtask
/*--------------------------------------------------------------------------------*/
parameter RD_DATA_REQ = 1'b0, WAIT_RD_VALID = 1'b1;
reg [addr_width-1:0] temp_read_address;
reg [max_burst_bytes_width:0] temp_rd_valid_bytes;
reg rd_fifo_state;
reg invalid_rd_req;
/* get the data from memory && also calculate the rresp*/
always@(negedge S_RESETN or posedge SW_CLK)
begin
if(!S_RESETN)begin
rd_fifo_wr_ptr <= 0;
wr_rresp_cnt <=0;
rd_fifo_state <= RD_DATA_REQ;
temp_rd_valid_bytes = 0;
temp_read_address <= 0;
RD_REQ_DDR <= 0;
RD_REQ_OCM <= 0;
RD_REQ_REG <= 0;
RD_QOS <= 0;
invalid_rd_req <= 0;
end else begin
case(rd_fifo_state)
RD_DATA_REQ : begin
rd_fifo_state <= RD_DATA_REQ;
RD_REQ_DDR <= 0;
RD_REQ_OCM <= 0;
RD_REQ_REG <= 0;
RD_QOS <= 0;
if(ar_flag[wr_rresp_cnt[int_rd_cntr_width-2:0]] && !read_fifo_full) begin
ar_flag[wr_rresp_cnt[int_rd_cntr_width-2:0]] <= 0;
rresp = calculate_resp(1'b1, araddr[wr_rresp_cnt[int_rd_cntr_width-2:0]],arprot[wr_rresp_cnt[int_rd_cntr_width-2:0]]);
fifo_rresp[wr_rresp_cnt[int_rd_cntr_width-2:0]] <= {arid[wr_rresp_cnt[int_rd_cntr_width-2:0]],rresp};
temp_rd_valid_bytes = (arlen[wr_rresp_cnt[int_rd_cntr_width-2:0]]+1)*(2**arsize[wr_rresp_cnt[int_rd_cntr_width-2:0]]);//data_bus_width/8;
if(arbrst[wr_rresp_cnt[int_rd_cntr_width-2:0]] === AXI_WRAP) /// wrap begin
temp_read_address = (araddr[wr_rresp_cnt[int_rd_cntr_width-2:0]]/temp_rd_valid_bytes) * temp_rd_valid_bytes;
else
temp_read_address = araddr[wr_rresp_cnt[int_rd_cntr_width-2:0]];
if(rresp === AXI_OK) begin
case(decode_address(temp_read_address))//decode_address(araddr[wr_rresp_cnt[int_rd_cntr_width-2:0]]);
OCM_MEM : RD_REQ_OCM <= 1;
DDR_MEM : RD_REQ_DDR <= 1;
REG_MEM : RD_REQ_REG <= 1;
default : invalid_rd_req <= 1;
endcase
end else
invalid_rd_req <= 1;
RD_QOS <= arqos[wr_rresp_cnt[int_rd_cntr_width-2:0]];
RD_ADDR <= temp_read_address; ///araddr[wr_rresp_cnt[int_rd_cntr_width-2:0]];
RD_BYTES <= temp_rd_valid_bytes;
rd_fifo_state <= WAIT_RD_VALID;
wr_rresp_cnt <= wr_rresp_cnt + 1;
if(wr_rresp_cnt[int_rd_cntr_width-2:0] === max_rd_outstanding_transactions-1) begin
wr_rresp_cnt[int_rd_cntr_width-1] <= ~ wr_rresp_cnt[int_rd_cntr_width-1];
wr_rresp_cnt[int_rd_cntr_width-2:0] <= 0;
end
end
end
WAIT_RD_VALID : begin
rd_fifo_state <= WAIT_RD_VALID;
if(RD_DATA_VALID_OCM | RD_DATA_VALID_DDR | RD_DATA_VALID_REG | invalid_rd_req) begin ///temp_dec == 2'b11) begin
if(RD_DATA_VALID_DDR)
read_fifo[rd_fifo_wr_ptr[int_rd_cntr_width-2:0]] <= RD_DATA_DDR;
else if(RD_DATA_VALID_OCM)
read_fifo[rd_fifo_wr_ptr[int_rd_cntr_width-2:0]] <= RD_DATA_OCM;
else if(RD_DATA_VALID_REG)
read_fifo[rd_fifo_wr_ptr[int_rd_cntr_width-2:0]] <= RD_DATA_REG;
else
read_fifo[rd_fifo_wr_ptr[int_rd_cntr_width-2:0]] <= 0;
rd_fifo_wr_ptr <= rd_fifo_wr_ptr + 1;
RD_REQ_DDR <= 0;
RD_REQ_OCM <= 0;
RD_REQ_REG <= 0;
RD_QOS <= 0;
invalid_rd_req <= 0;
rd_fifo_state <= RD_DATA_REQ;
end
end
endcase
end /// else
end /// always
/*--------------------------------------------------------------------------------*/
reg[max_burst_bytes_width:0] rd_v_b;
reg [(data_bus_width*axi_burst_len)-1:0] temp_read_data;
reg [(data_bus_width*axi_burst_len)-1:0] temp_wrap_data;
reg[(axi_rsp_width*axi_burst_len)-1:0] temp_read_rsp;
/* Read Data Channel handshake */
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN)begin
rd_fifo_rd_ptr <= 0;
rd_cnt <= 0;
rd_latency_count <= get_rd_lat_number(1);
rd_delayed = 0;
rresp_time_cnt <= 0;
rd_v_b = 0;
end else begin
if(arvalid_flag[rresp_time_cnt] && ((($time - arvalid_receive_time[rresp_time_cnt])/s_aclk_period) >= rd_latency_count))
rd_delayed = 1;
if(!read_fifo_empty && rd_delayed)begin
rd_delayed = 0;
arvalid_flag[rresp_time_cnt] = 1'b0;
rd_v_b = ((arlen[rd_cnt[int_rd_cntr_width-2:0]]+1)*(2**arsize[rd_cnt[int_rd_cntr_width-2:0]]));
temp_read_data = read_fifo[rd_fifo_rd_ptr[int_rd_cntr_width-2:0]];
rd_fifo_rd_ptr <= rd_fifo_rd_ptr+1;
if(arbrst[rd_cnt[int_rd_cntr_width-2:0]]=== AXI_WRAP) begin
get_wrap_aligned_rd_data(temp_wrap_data, araddr[rd_cnt[int_rd_cntr_width-2:0]], temp_read_data, rd_v_b);
temp_read_data = temp_wrap_data;
end
temp_read_rsp = 0;
repeat(axi_burst_len) begin
temp_read_rsp = temp_read_rsp >> axi_rsp_width;
temp_read_rsp[(axi_rsp_width*axi_burst_len)-1:(axi_rsp_width*axi_burst_len)-axi_rsp_width] = fifo_rresp[rd_cnt[int_rd_cntr_width-2:0]][rsp_msb : rsp_lsb];
end
slave.SEND_READ_BURST_RESP_CTRL(arid[rd_cnt[int_rd_cntr_width-2:0]],
araddr[rd_cnt[int_rd_cntr_width-2:0]],
arlen[rd_cnt[int_rd_cntr_width-2:0]],
arsize[rd_cnt[int_rd_cntr_width-2:0]],
arbrst[rd_cnt[int_rd_cntr_width-2:0]],
temp_read_data,
temp_read_rsp);
rd_cnt <= rd_cnt + 1;
rresp_time_cnt <= rresp_time_cnt+1;
if(rresp_time_cnt === max_rd_outstanding_transactions) rresp_time_cnt <= 0;
if(rd_cnt[int_rd_cntr_width-2:0] === (max_rd_outstanding_transactions-1)) begin
rd_cnt[int_rd_cntr_width-1] <= ~ rd_cnt[int_rd_cntr_width-1];
rd_cnt[int_rd_cntr_width-2:0] <= 0;
end
rd_latency_count <= get_rd_lat_number(1);
end
end /// else
end /// always
endmodule
|
/*+--------------------------------------------------------------------------
Copyright (c) 2015, Microsoft Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
`timescale 1ns / 1ps
///////////////////////////////////////////////////////////////////////////////
//
// Summary:
//
// The BIT_ALIGN_MACHINE module analyzes the data input of a single channel
// to determine the optimal clock/data relationship for that channel. By
// dynamically changing the delay of the data channel (with respect to the
// sampling clock), the machine places the sampling point at the center of
// the data eye.
//
//----------------------------------------------------------------
module RCB_FRL_BIT_ALIGN_MACHINE (
input RXCLKDIV,
input [7:0] RXDATA,
input RST,
input USE_BITSLIP,
input SAP,
output reg INC,
output reg ICE,
output reg BITSLIP,
output DATA_ALIGNED
);
reg COUNT;
reg UD;
reg STORE;
reg STORE_DATA_PREV;
reg COUNT_SAMPLE;
reg UD_SAMPLE;
reg [4:0] CURRENT_STATE;
reg [4:0] NEXT_STATE;
wire [6:0] COUNT_VALUE;
wire [6:0] HALF_DATA_EYE;
wire [7:0] RXDATA_PREV;
wire [6:0] COUNT_VALUE_SAMPLE;
wire [6:0] CVS;
wire [6:0] CVS_ADJUSTED;
wire [7:0] CHECK_PATTERN;
RCB_FRL_count_to_128 machine_counter_total(
.clk(RXCLKDIV),
.rst(RST),
.count(COUNT_SAMPLE),
.ud(UD_SAMPLE),
.counter_value(COUNT_VALUE_SAMPLE)
);
RCB_FRL_count_to_128 machine_counter(
.clk(RXCLKDIV),
.rst(RST),
.count(COUNT),
.ud(UD),
.counter_value(COUNT_VALUE)
);
RCB_FRL_seven_bit_reg_w_ce tap_reserve(
.Q(CVS),
.CLK(RXCLKDIV),
.CE(STORE),
.D(COUNT_VALUE),
.RST(RST)
);
FDR count_reg(.Q(DATA_ALIGNED), .C(RXCLKDIV), .D(DATA_ALIGNEDx), .R(RST));
//STORE ENTIRE DATA BUS FOR COMPARISON AFTER CHANGING DELAY
FDRE bit0(.Q(RXDATA_PREV[0]), .C(RXCLKDIV), .CE(STORE_DATA_PREV), .D(RXDATA[0]), .R(RST));
FDRE bit1(.Q(RXDATA_PREV[1]), .C(RXCLKDIV), .CE(STORE_DATA_PREV), .D(RXDATA[1]), .R(RST));
FDRE bit2(.Q(RXDATA_PREV[2]), .C(RXCLKDIV), .CE(STORE_DATA_PREV), .D(RXDATA[2]), .R(RST));
FDRE bit3(.Q(RXDATA_PREV[3]), .C(RXCLKDIV), .CE(STORE_DATA_PREV), .D(RXDATA[3]), .R(RST));
FDRE bit4(.Q(RXDATA_PREV[4]), .C(RXCLKDIV), .CE(STORE_DATA_PREV), .D(RXDATA[4]), .R(RST));
FDRE bit5(.Q(RXDATA_PREV[5]), .C(RXCLKDIV), .CE(STORE_DATA_PREV), .D(RXDATA[5]), .R(RST));
FDRE bit6(.Q(RXDATA_PREV[6]), .C(RXCLKDIV), .CE(STORE_DATA_PREV), .D(RXDATA[6]), .R(RST));
FDRE bit7(.Q(RXDATA_PREV[7]), .C(RXCLKDIV), .CE(STORE_DATA_PREV), .D(RXDATA[7]), .R(RST));
assign DATA_ALIGNEDx = (~CURRENT_STATE[4] & ~CURRENT_STATE[3] & CURRENT_STATE[2] & CURRENT_STATE[1] & CURRENT_STATE[0]);
//assign CHECK_PATTERN = 8'b11010010;
assign CHECK_PATTERN = 8'h5c; // training pattern for spartan6
//CVS IS A SNAPSHOT OF THE TAP COUNTER. IT'S VALUE IS THE SIZE OF THE DATA VALID WINDOW
//OUR INTENTION IS TO DECREMENT THE DELAY TO 1/2 THIS VALUE TO BE AT THE CENTER OF THE EYE.
//SINCE IT MAY BE POSSIBLE TO HAVE AN ODD COUNTER VALUE, THE HALVED VALUE WILL BE A DECIMAL.
//IN CASES WHERE CVS IS A DECIMAL, WE WILL ROUND UP. E.G CVS = 4.5, SO DECREMENT 5 TAPS.
//CVS_ADJUSTED AND HALF_DATA_EYE ARE FINE TUNED ADJUSTMENTS FOR OPTIMAL OPERATION AT HIGH RATES
assign CVS_ADJUSTED = CVS - 1; //THE ALGORITHM COUNTS ONE TAP BEYOND EYE, MUST BE REMOVED
assign HALF_DATA_EYE = {1'b0,CVS_ADJUSTED[6:1]} + CVS_ADJUSTED[0]; //THE CVS[0] FACTOR CAUSES A ROUND-UP
//CURRENT STATE LOGIC
always@(posedge RXCLKDIV or posedge RST) begin
if(RST == 1'b1) begin
CURRENT_STATE = 5'b00000;
end else begin
CURRENT_STATE = NEXT_STATE;
end
end
//NEXT_STATE LOGIC
always @(CURRENT_STATE or COUNT_VALUE or USE_BITSLIP or RXDATA or
CHECK_PATTERN or RXDATA_PREV or COUNT_VALUE_SAMPLE or SAP or HALF_DATA_EYE) begin
case(CURRENT_STATE)
5'b00000: begin
if (SAP == 1'b0) //RST STATE
NEXT_STATE <= 5'b00001;
else
NEXT_STATE <= 5'b00000;
end
5'b00001: begin //INITIAL STATE, SAMPLE TRAINING BIT
if (RXDATA_PREV != RXDATA)
NEXT_STATE <= 5'b01111;
else
NEXT_STATE <= 5'b01000;
end
5'b01000: begin //CHECK SAMPLE TO SEE IF IT IS ON A TRANSITION
if (RXDATA_PREV != RXDATA)
NEXT_STATE <= 5'b01111;
else if (COUNT_VALUE_SAMPLE > 7'b0001111)
NEXT_STATE <= 5'b01011;
else
NEXT_STATE <= 5'b01000;
end
5'b01111: begin //IF SAMPLED POINT IS TRANSITION, EDGE IS FOUND, SO INC DELAY TO EXIT TRANSITION
NEXT_STATE <= 5'b01101;
end
5'b01101: begin //WAIT 16 CYCLES WHILE APPLYING BITSLIP TO FIND CHECK_PATTERN
if (COUNT_VALUE_SAMPLE > 7'b0001110)
NEXT_STATE <= 5'b01111;
else if (RXDATA == CHECK_PATTERN) //IF CHECK_PATTERN IS FOUND, WE ARE CLOSE TO END OF TRANSITION
NEXT_STATE <= 5'b01100;
else
NEXT_STATE <= 5'b01101;
end
5'b01100: begin //IDLE (NEEDED FOR COUNTER RESET BEFORE NEXT STATE)
NEXT_STATE <= 5'b10000;
end
5'b10000: begin //IDLE (NEEDED FOR STABILIZATION)
NEXT_STATE <= 5'b00010;
end
5'b00010: begin //CHECK SAMPLE AGAIN TO SEE IF WE HAVE EXITED TRANSITION
if (COUNT_VALUE_SAMPLE < 7'b0000011) //ALLOW TIME FOR BITSLIP OP TO STABILIZE
NEXT_STATE <= 5'b00010;
else if (RXDATA_PREV != RXDATA)
NEXT_STATE <= 5'b01111;
else if (COUNT_VALUE_SAMPLE > 7'b1111110) //SCAN FOR STABILITY FOR 128 CYCLES
NEXT_STATE <= 5'b01110;
else
NEXT_STATE <= 5'b00010;
end
5'b01011: begin //INITIAL STATE WAS STABLE, SO INC ONCE TO SEARCH FOR TRANS
NEXT_STATE <= 5'b00100;
end
5'b00100: begin //WAIT 8 CYCLES, COMPARE RXDATA WITH PREVIOUS DATA
if (COUNT_VALUE_SAMPLE < 7'b0000111)
NEXT_STATE <= 5'b00100;
else if(RXDATA_PREV != RXDATA)
NEXT_STATE <= 5'b01111;
else
NEXT_STATE <= 5'b01011;
end
5'b01110: begin //DATA IS STABLE AFTER FINDING 1ST TRANS, COUNT 1 TO INCLUDE LAST INC
NEXT_STATE <= 5'b01001;
end
5'b01001: begin //INC ONCE TO LOOK FOR 2ND TRANS
NEXT_STATE <= 5'b00011;
end
5'b00011: begin //WAIT 8 CYCLES, COMPARE RXDATA WITH PREVIOUS DATA
if (COUNT_VALUE_SAMPLE < 7'b0000111)
NEXT_STATE <= 5'b00011;
else if(RXDATA_PREV != RXDATA)
NEXT_STATE <= 5'b10010;
else
NEXT_STATE <= 5'b01001;
end
5'b10010: begin //IDLE (NEEDED FOR COUNTER RESET BEFORE NEXT STATE)
NEXT_STATE <= 5'b01010;
end
5'b01010: begin //DECREMENT TO MIDDLE OF DATA EYE
if (COUNT_VALUE_SAMPLE < HALF_DATA_EYE-1)
NEXT_STATE <= 5'b01010;
else
NEXT_STATE <= 5'b00101;
end
5'b00101: begin //SAMPLE PATTERN 16 TIMES TO SEE IF WORD ALIGNMENT NEEDED
if(USE_BITSLIP == 1'b0)
NEXT_STATE <= 5'b00111;
else if(COUNT_VALUE < 7'h0F)
NEXT_STATE <= 5'b00101;
else if (RXDATA == CHECK_PATTERN)
NEXT_STATE <= 5'b00111;
else
NEXT_STATE <= 5'b00110;
end
5'b00110: begin //INITIATE 1 BITSLIP
NEXT_STATE <= 5'b00101;
end
5'b00111: begin
if (SAP == 1'b0) //TRAINING COMPLETE FOR THIS CHANNEL
NEXT_STATE <= 5'b00111;
else
NEXT_STATE <= 5'b00000;
end
default: NEXT_STATE <= 5'b00000;
endcase
end
//OUTPUT LOGIC
always @(CURRENT_STATE)
begin
case(CURRENT_STATE)
5'b00000: begin //RST STATE
INC = 1'b0;
ICE = 1'b0;
COUNT = 1'b0;
UD = 1'b0;
STORE = 1'b0;
STORE_DATA_PREV = 1'b1;
BITSLIP = 1'b0;
COUNT_SAMPLE = 1'b0;
UD_SAMPLE = 1'b0;
end
5'b00001: begin //INITIAL STATE, SAMPLE TRAINING BIT
INC = 1'b0;
ICE = 1'b0;
COUNT = 1'b0;
UD = 1'b0;
STORE = 1'b0;
STORE_DATA_PREV = 1'b1;
BITSLIP = 1'b0;
COUNT_SAMPLE = 1'b0;
UD_SAMPLE = 1'b0;
end
5'b01000: begin //CHECK SAMPLE TO SEE IF IT IS ON A TRANSITION
INC = 1'b0;
ICE = 1'b0;
COUNT = 1'b0;
UD = 1'b1;
STORE = 1'b0;
STORE_DATA_PREV = 1'b1;
BITSLIP = 1'b0;
COUNT_SAMPLE = 1'b1;
UD_SAMPLE = 1'b1;
end
5'b01111: begin //IF SAMPLED POINT IS TRANSITION, EDGE IS FOUND, SO INC DELAY TO EXIT TRANSITION
INC = 1'b1;
ICE = 1'b1;
COUNT = 1'b0;
UD = 1'b1;
STORE = 1'b0;
STORE_DATA_PREV = 1'b1;
BITSLIP = 1'b0;
COUNT_SAMPLE = 1'b0;
UD_SAMPLE = 1'b0;
end
5'b01101: begin //WAIT 16 CYCLES WHILE APPLYING BITSLIP TO FIND CHECK_PATTERN
INC = 1'b0;
ICE = 1'b0;
COUNT = 1'b0;
UD = 1'b1;
STORE = 1'b0;
STORE_DATA_PREV = 1'b1;
BITSLIP = 1'b1;
COUNT_SAMPLE = 1'b1;
UD_SAMPLE = 1'b1;
end
5'b01100: begin //IDLE (NEEDED FOR COUNTER RESET BEFORE NEXT STATE)
INC = 1'b0;
ICE = 1'b0;
COUNT = 1'b0;
UD = 1'b1;
STORE = 1'b0;
STORE_DATA_PREV = 1'b1;
BITSLIP = 1'b0;
COUNT_SAMPLE = 1'b0;
UD_SAMPLE = 1'b0;
end
5'b10000: begin //IDLE (NEEDED FOR STABILIZATION)
INC = 1'b0;
ICE = 1'b0;
COUNT = 1'b0;
UD = 1'b1;
STORE = 1'b0;
STORE_DATA_PREV = 1'b1;
BITSLIP = 1'b0;
COUNT_SAMPLE = 1'b0;
UD_SAMPLE = 1'b0;
end
5'b00010: begin //CHECK SAMPLE AGAIN TO SEE IF WE HAVE EXITED TRANSITION
INC = 1'b0;
ICE = 1'b0;
COUNT = 1'b0;
UD = 1'b1;
STORE = 1'b0;
STORE_DATA_PREV = 1'b1;
BITSLIP = 1'b0;
COUNT_SAMPLE = 1'b1;
UD_SAMPLE = 1'b1;
end
5'b01011: begin //INITIAL STATE WAS STABLE, SO INC ONCE TO SEARCH FOR TRANS
INC = 1'b1;
ICE = 1'b1;
COUNT = 1'b0;
UD = 1'b0;
STORE = 1'b0;
STORE_DATA_PREV = 1'b1;
BITSLIP = 1'b0;
COUNT_SAMPLE = 1'b0;
UD_SAMPLE = 1'b0;
end
5'b00100: begin //WAIT 8 CYCLES, COMPARE RXDATA WITH PREVIOUS DATA
INC = 1'b0;
ICE = 1'b0;
COUNT = 1'b0;
UD = 1'b0;
STORE = 1'b0;
STORE_DATA_PREV = 1'b0;
BITSLIP = 1'b0;
COUNT_SAMPLE = 1'b1;
UD_SAMPLE = 1'b1;
end
5'b01110: begin //DATA IS STABLE AFTER FINDING 1ST TRANS, COUNT 1 TO INCLUDE LAST INC
INC = 1'b0;
ICE = 1'b0;
COUNT = 1'b1;
UD = 1'b1;
STORE = 1'b0;
STORE_DATA_PREV = 1'b1;
BITSLIP = 1'b0;
COUNT_SAMPLE = 1'b0;
UD_SAMPLE = 1'b0;
end
5'b01001: begin //INC ONCE TO LOOK FOR 2ND TRANS
INC = 1'b1;
ICE = 1'b1;
COUNT = 1'b1;
UD = 1'b1;
STORE = 1'b0;
STORE_DATA_PREV = 1'b1;
BITSLIP = 1'b0;
COUNT_SAMPLE = 1'b0;
UD_SAMPLE = 1'b0;
end
5'b00011: begin //WAIT 8 CYCLES, COMPARE RXDATA WITH PREVIOUS DATA
INC = 1'b0;
ICE = 1'b0;
COUNT = 1'b0;
UD = 1'b1;
STORE = 1'b1;
STORE_DATA_PREV = 1'b0;
BITSLIP = 1'b0;
COUNT_SAMPLE = 1'b1;
UD_SAMPLE = 1'b1;
end
5'b10010: begin //IDLE (NEEDED FOR COUNTER RESET BEFORE NEXT STATE)
INC = 1'b0;
ICE = 1'b0;
COUNT = 1'b0;
UD = 1'b0;
STORE = 1'b0;
STORE_DATA_PREV = 1'b1;
BITSLIP = 1'b0;
COUNT_SAMPLE = 1'b0;
UD_SAMPLE = 1'b0;
end
5'b01010: begin //DECREMENT TO CENTER OF DATA EYE
INC = 1'b0;
ICE = 1'b1;
COUNT = 1'b0;
UD = 1'b0;
STORE = 1'b0;
STORE_DATA_PREV = 1'b1;
BITSLIP = 1'b0;
COUNT_SAMPLE = 1'b1;
UD_SAMPLE = 1'b1;
end
5'b00101: begin //SAMPLE PATTERN 16 TIMES TO SEE IF WORD ALIGNMENT NEEDED
INC = 1'b0;
ICE = 1'b0;
COUNT = 1'b1;
UD = 1'b1;
STORE = 1'b0;
STORE_DATA_PREV = 1'b1;
BITSLIP = 1'b0;
COUNT_SAMPLE = 1'b0;
UD_SAMPLE = 1'b0;
end
5'b00110: begin //INITIATE 1 BITSLIP
INC = 1'b0;
ICE = 1'b0;
COUNT = 1'b0;
UD = 1'b0;
STORE = 1'b0;
STORE_DATA_PREV = 1'b1;
BITSLIP = 1'b1;
COUNT_SAMPLE = 1'b0;
UD_SAMPLE = 1'b0;
end
5'b00111: begin //TRAINING COMPLETE ON THIS CHANNEL
INC = 1'b0;
ICE = 1'b0;
COUNT = 1'b0;
UD = 1'b0;
STORE = 1'b0;
STORE_DATA_PREV = 1'b1;
BITSLIP = 1'b0;
COUNT_SAMPLE = 1'b0;
UD_SAMPLE = 1'b0;
end
default: begin
INC = 1'b0;
ICE = 1'b0;
COUNT = 1'b0;
UD = 1'b0;
STORE = 1'b0;
STORE_DATA_PREV = 1'b1;
BITSLIP = 1'b0;
COUNT_SAMPLE = 1'b0;
UD_SAMPLE = 1'b0;
end
endcase
end
endmodule
`timescale 1 ns / 10 ps
module RCB_FRL_seven_bit_reg_w_ce(Q, CLK, CE, D, RST);
input [6:0] D;
input CLK, CE, RST;
output [6:0] Q;
FDRE bit0(.Q(Q[0]), .C(CLK), .CE(CE), .D(D[0]), .R(RST));
FDRE bit1(.Q(Q[1]), .C(CLK), .CE(CE), .D(D[1]), .R(RST));
FDRE bit2(.Q(Q[2]), .C(CLK), .CE(CE), .D(D[2]), .R(RST));
FDRE bit3(.Q(Q[3]), .C(CLK), .CE(CE), .D(D[3]), .R(RST));
FDRE bit4(.Q(Q[4]), .C(CLK), .CE(CE), .D(D[4]), .R(RST));
FDRE bit5(.Q(Q[5]), .C(CLK), .CE(CE), .D(D[5]), .R(RST));
FDRE bit6(.Q(Q[6]), .C(CLK), .CE(CE), .D(D[6]), .R(RST));
endmodule
|
//-----------------------------------------------------------------------------
// The way that we connect things when transmitting a command to an ISO
// 15693 tag, using 100% modulation only for now.
//
// Jonathan Westhues, April 2006
//-----------------------------------------------------------------------------
module hi_read_tx(
pck0, ck_1356meg, ck_1356megb,
pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
adc_d, adc_clk,
ssp_frame, ssp_din, ssp_dout, ssp_clk,
cross_hi, cross_lo,
dbg,
shallow_modulation
);
input pck0, ck_1356meg, ck_1356megb;
output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
input [7:0] adc_d;
output adc_clk;
input ssp_dout;
output ssp_frame, ssp_din, ssp_clk;
input cross_hi, cross_lo;
output dbg;
input shallow_modulation;
// The high-frequency stuff. For now, for testing, just bring out the carrier,
// and allow the ARM to modulate it over the SSP.
reg pwr_hi;
reg pwr_oe1;
reg pwr_oe2;
reg pwr_oe3;
reg pwr_oe4;
always @(ck_1356megb or ssp_dout or shallow_modulation)
begin
if(shallow_modulation)
begin
pwr_hi <= ck_1356megb;
pwr_oe1 <= ~ssp_dout;
pwr_oe2 <= ~ssp_dout;
pwr_oe3 <= ~ssp_dout;
pwr_oe4 <= 1'b0;
end
else
begin
pwr_hi <= ck_1356megb & ssp_dout;
pwr_oe1 <= 1'b0;
pwr_oe2 <= 1'b0;
pwr_oe3 <= 1'b0;
pwr_oe4 <= 1'b0;
end
end
// Then just divide the 13.56 MHz clock down to produce appropriate clocks
// for the synchronous serial port.
reg [6:0] hi_div_by_128;
always @(posedge ck_1356meg)
hi_div_by_128 <= hi_div_by_128 + 1;
assign ssp_clk = hi_div_by_128[6];
reg [2:0] hi_byte_div;
always @(negedge ssp_clk)
hi_byte_div <= hi_byte_div + 1;
assign ssp_frame = (hi_byte_div == 3'b000);
// Implement a hysteresis to give out the received signal on
// ssp_din. Sample at fc.
assign adc_clk = ck_1356meg;
// ADC data appears on the rising edge, so sample it on the falling edge
reg after_hysteresis;
always @(negedge adc_clk)
begin
if(& adc_d[7:0]) after_hysteresis <= 1'b1;
else if(~(| adc_d[7:0])) after_hysteresis <= 1'b0;
end
assign ssp_din = after_hysteresis;
assign pwr_lo = 1'b0;
assign dbg = ssp_din;
endmodule
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:processing_system7:5.5
// IP Revision: 3
(* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2016.4" *)
(* CHECK_LICENSE_TYPE = "sys_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}" *)
(* CORE_GENERATION_INFO = "sys_processing_system7_0_0,processing_system7_v5_5_processing_system7,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=processing_system7,x_ipVersion=5.5,x_ipCoreRevision=3,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_EN_EMIO_PJTAG=0,C_EN_EMIO_ENET0=0,C_EN_EMIO_ENET1=0,C_EN_EMIO_TRACE=0,C_INCLUDE_TRACE_BUFFER=0,C_TRACE_BUFFER_FIFO_SIZE=128,USE_TRACE_DATA_EDGE_DETECTOR=0,C_TRACE_PIPELINE_WIDTH=8,C_TRACE_BUFFER_CLOCK_DELAY=12,C_EMIO_GPIO_WIDTH=64,C_INCLUDE_ACP_TRANS_CHECK=0,C_\
USE_DEFAULT_ACP_USER_VAL=0,C_S_AXI_ACP_ARUSER_VAL=31,C_S_AXI_ACP_AWUSER_VAL=31,C_M_AXI_GP0_ID_WIDTH=12,C_M_AXI_GP0_ENABLE_STATIC_REMAP=0,C_M_AXI_GP1_ID_WIDTH=12,C_M_AXI_GP1_ENABLE_STATIC_REMAP=0,C_S_AXI_GP0_ID_WIDTH=6,C_S_AXI_GP1_ID_WIDTH=6,C_S_AXI_ACP_ID_WIDTH=3,C_S_AXI_HP0_ID_WIDTH=6,C_S_AXI_HP0_DATA_WIDTH=64,C_S_AXI_HP1_ID_WIDTH=6,C_S_AXI_HP1_DATA_WIDTH=64,C_S_AXI_HP2_ID_WIDTH=6,C_S_AXI_HP2_DATA_WIDTH=64,C_S_AXI_HP3_ID_WIDTH=6,C_S_AXI_HP3_DATA_WIDTH=64,C_M_AXI_GP0_THREAD_ID_WIDTH=12,C_M_AXI_G\
P1_THREAD_ID_WIDTH=12,C_NUM_F2P_INTR_INPUTS=1,C_IRQ_F2P_MODE=DIRECT,C_DQ_WIDTH=32,C_DQS_WIDTH=4,C_DM_WIDTH=4,C_MIO_PRIMITIVE=54,C_TRACE_INTERNAL_WIDTH=2,C_USE_AXI_NONSECURE=0,C_USE_M_AXI_GP0=1,C_USE_M_AXI_GP1=0,C_USE_S_AXI_GP0=0,C_USE_S_AXI_HP0=0,C_USE_S_AXI_HP1=0,C_USE_S_AXI_HP2=0,C_USE_S_AXI_HP3=0,C_USE_S_AXI_ACP=0,C_PS7_SI_REV=PRODUCTION,C_FCLK_CLK0_BUF=TRUE,C_FCLK_CLK1_BUF=FALSE,C_FCLK_CLK2_BUF=FALSE,C_FCLK_CLK3_BUF=FALSE,C_PACKAGE_NAME=clg484,C_GP0_EN_MODIFIABLE_TXN=0,C_GP1_EN_MODIFIABLE_TX\
N=0}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module sys_processing_system7_0_0 (
TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT,
USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
FCLK_CLK0,
FCLK_RESET0_N,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB
);
output wire TTC0_WAVE0_OUT;
output wire TTC0_WAVE1_OUT;
output wire TTC0_WAVE2_OUT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 PORT_INDCTL" *)
output wire [1 : 0] USB0_PORT_INDCTL;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRSELECT" *)
output wire USB0_VBUS_PWRSELECT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRFAULT" *)
input wire USB0_VBUS_PWRFAULT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARVALID" *)
output wire M_AXI_GP0_ARVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWVALID" *)
output wire M_AXI_GP0_AWVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BREADY" *)
output wire M_AXI_GP0_BREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RREADY" *)
output wire M_AXI_GP0_RREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WLAST" *)
output wire M_AXI_GP0_WLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WVALID" *)
output wire M_AXI_GP0_WVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARID" *)
output wire [11 : 0] M_AXI_GP0_ARID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWID" *)
output wire [11 : 0] M_AXI_GP0_AWID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WID" *)
output wire [11 : 0] M_AXI_GP0_WID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST" *)
output wire [1 : 0] M_AXI_GP0_ARBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLOCK" *)
output wire [1 : 0] M_AXI_GP0_ARLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARSIZE" *)
output wire [2 : 0] M_AXI_GP0_ARSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWBURST" *)
output wire [1 : 0] M_AXI_GP0_AWBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLOCK" *)
output wire [1 : 0] M_AXI_GP0_AWLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWSIZE" *)
output wire [2 : 0] M_AXI_GP0_AWSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARPROT" *)
output wire [2 : 0] M_AXI_GP0_ARPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWPROT" *)
output wire [2 : 0] M_AXI_GP0_AWPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR" *)
output wire [31 : 0] M_AXI_GP0_ARADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWADDR" *)
output wire [31 : 0] M_AXI_GP0_AWADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WDATA" *)
output wire [31 : 0] M_AXI_GP0_WDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARCACHE" *)
output wire [3 : 0] M_AXI_GP0_ARCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLEN" *)
output wire [3 : 0] M_AXI_GP0_ARLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARQOS" *)
output wire [3 : 0] M_AXI_GP0_ARQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWCACHE" *)
output wire [3 : 0] M_AXI_GP0_AWCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLEN" *)
output wire [3 : 0] M_AXI_GP0_AWLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWQOS" *)
output wire [3 : 0] M_AXI_GP0_AWQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB" *)
output wire [3 : 0] M_AXI_GP0_WSTRB;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK" *)
input wire M_AXI_GP0_ACLK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY" *)
input wire M_AXI_GP0_ARREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY" *)
input wire M_AXI_GP0_AWREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BVALID" *)
input wire M_AXI_GP0_BVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RLAST" *)
input wire M_AXI_GP0_RLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RVALID" *)
input wire M_AXI_GP0_RVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WREADY" *)
input wire M_AXI_GP0_WREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BID" *)
input wire [11 : 0] M_AXI_GP0_BID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID" *)
input wire [11 : 0] M_AXI_GP0_RID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP" *)
input wire [1 : 0] M_AXI_GP0_BRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP" *)
input wire [1 : 0] M_AXI_GP0_RRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA" *)
input wire [31 : 0] M_AXI_GP0_RDATA;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK" *)
output wire FCLK_CLK0;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST" *)
output wire FCLK_RESET0_N;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *)
inout wire [53 : 0] MIO;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *)
inout wire DDR_CAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CKE" *)
inout wire DDR_CKE;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_N" *)
inout wire DDR_Clk_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_P" *)
inout wire DDR_Clk;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CS_N" *)
inout wire DDR_CS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RESET_N" *)
inout wire DDR_DRSTB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ODT" *)
inout wire DDR_ODT;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RAS_N" *)
inout wire DDR_RAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR WE_N" *)
inout wire DDR_WEB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR BA" *)
inout wire [2 : 0] DDR_BankAddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ADDR" *)
inout wire [14 : 0] DDR_Addr;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN" *)
inout wire DDR_VRN;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP" *)
inout wire DDR_VRP;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DM" *)
inout wire [3 : 0] DDR_DM;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQ" *)
inout wire [31 : 0] DDR_DQ;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_N" *)
inout wire [3 : 0] DDR_DQS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_P" *)
inout wire [3 : 0] DDR_DQS;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB" *)
inout wire PS_SRSTB;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK" *)
inout wire PS_CLK;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB" *)
inout wire PS_PORB;
processing_system7_v5_5_processing_system7 #(
.C_EN_EMIO_PJTAG(0),
.C_EN_EMIO_ENET0(0),
.C_EN_EMIO_ENET1(0),
.C_EN_EMIO_TRACE(0),
.C_INCLUDE_TRACE_BUFFER(0),
.C_TRACE_BUFFER_FIFO_SIZE(128),
.USE_TRACE_DATA_EDGE_DETECTOR(0),
.C_TRACE_PIPELINE_WIDTH(8),
.C_TRACE_BUFFER_CLOCK_DELAY(12),
.C_EMIO_GPIO_WIDTH(64),
.C_INCLUDE_ACP_TRANS_CHECK(0),
.C_USE_DEFAULT_ACP_USER_VAL(0),
.C_S_AXI_ACP_ARUSER_VAL(31),
.C_S_AXI_ACP_AWUSER_VAL(31),
.C_M_AXI_GP0_ID_WIDTH(12),
.C_M_AXI_GP0_ENABLE_STATIC_REMAP(0),
.C_M_AXI_GP1_ID_WIDTH(12),
.C_M_AXI_GP1_ENABLE_STATIC_REMAP(0),
.C_S_AXI_GP0_ID_WIDTH(6),
.C_S_AXI_GP1_ID_WIDTH(6),
.C_S_AXI_ACP_ID_WIDTH(3),
.C_S_AXI_HP0_ID_WIDTH(6),
.C_S_AXI_HP0_DATA_WIDTH(64),
.C_S_AXI_HP1_ID_WIDTH(6),
.C_S_AXI_HP1_DATA_WIDTH(64),
.C_S_AXI_HP2_ID_WIDTH(6),
.C_S_AXI_HP2_DATA_WIDTH(64),
.C_S_AXI_HP3_ID_WIDTH(6),
.C_S_AXI_HP3_DATA_WIDTH(64),
.C_M_AXI_GP0_THREAD_ID_WIDTH(12),
.C_M_AXI_GP1_THREAD_ID_WIDTH(12),
.C_NUM_F2P_INTR_INPUTS(1),
.C_IRQ_F2P_MODE("DIRECT"),
.C_DQ_WIDTH(32),
.C_DQS_WIDTH(4),
.C_DM_WIDTH(4),
.C_MIO_PRIMITIVE(54),
.C_TRACE_INTERNAL_WIDTH(2),
.C_USE_AXI_NONSECURE(0),
.C_USE_M_AXI_GP0(1),
.C_USE_M_AXI_GP1(0),
.C_USE_S_AXI_GP0(0),
.C_USE_S_AXI_HP0(0),
.C_USE_S_AXI_HP1(0),
.C_USE_S_AXI_HP2(0),
.C_USE_S_AXI_HP3(0),
.C_USE_S_AXI_ACP(0),
.C_PS7_SI_REV("PRODUCTION"),
.C_FCLK_CLK0_BUF("TRUE"),
.C_FCLK_CLK1_BUF("FALSE"),
.C_FCLK_CLK2_BUF("FALSE"),
.C_FCLK_CLK3_BUF("FALSE"),
.C_PACKAGE_NAME("clg484"),
.C_GP0_EN_MODIFIABLE_TXN(0),
.C_GP1_EN_MODIFIABLE_TXN(0)
) inst (
.CAN0_PHY_TX(),
.CAN0_PHY_RX(1'B0),
.CAN1_PHY_TX(),
.CAN1_PHY_RX(1'B0),
.ENET0_GMII_TX_EN(),
.ENET0_GMII_TX_ER(),
.ENET0_MDIO_MDC(),
.ENET0_MDIO_O(),
.ENET0_MDIO_T(),
.ENET0_PTP_DELAY_REQ_RX(),
.ENET0_PTP_DELAY_REQ_TX(),
.ENET0_PTP_PDELAY_REQ_RX(),
.ENET0_PTP_PDELAY_REQ_TX(),
.ENET0_PTP_PDELAY_RESP_RX(),
.ENET0_PTP_PDELAY_RESP_TX(),
.ENET0_PTP_SYNC_FRAME_RX(),
.ENET0_PTP_SYNC_FRAME_TX(),
.ENET0_SOF_RX(),
.ENET0_SOF_TX(),
.ENET0_GMII_TXD(),
.ENET0_GMII_COL(1'B0),
.ENET0_GMII_CRS(1'B0),
.ENET0_GMII_RX_CLK(1'B0),
.ENET0_GMII_RX_DV(1'B0),
.ENET0_GMII_RX_ER(1'B0),
.ENET0_GMII_TX_CLK(1'B0),
.ENET0_MDIO_I(1'B0),
.ENET0_EXT_INTIN(1'B0),
.ENET0_GMII_RXD(8'B0),
.ENET1_GMII_TX_EN(),
.ENET1_GMII_TX_ER(),
.ENET1_MDIO_MDC(),
.ENET1_MDIO_O(),
.ENET1_MDIO_T(),
.ENET1_PTP_DELAY_REQ_RX(),
.ENET1_PTP_DELAY_REQ_TX(),
.ENET1_PTP_PDELAY_REQ_RX(),
.ENET1_PTP_PDELAY_REQ_TX(),
.ENET1_PTP_PDELAY_RESP_RX(),
.ENET1_PTP_PDELAY_RESP_TX(),
.ENET1_PTP_SYNC_FRAME_RX(),
.ENET1_PTP_SYNC_FRAME_TX(),
.ENET1_SOF_RX(),
.ENET1_SOF_TX(),
.ENET1_GMII_TXD(),
.ENET1_GMII_COL(1'B0),
.ENET1_GMII_CRS(1'B0),
.ENET1_GMII_RX_CLK(1'B0),
.ENET1_GMII_RX_DV(1'B0),
.ENET1_GMII_RX_ER(1'B0),
.ENET1_GMII_TX_CLK(1'B0),
.ENET1_MDIO_I(1'B0),
.ENET1_EXT_INTIN(1'B0),
.ENET1_GMII_RXD(8'B0),
.GPIO_I(64'B0),
.GPIO_O(),
.GPIO_T(),
.I2C0_SDA_I(1'B0),
.I2C0_SDA_O(),
.I2C0_SDA_T(),
.I2C0_SCL_I(1'B0),
.I2C0_SCL_O(),
.I2C0_SCL_T(),
.I2C1_SDA_I(1'B0),
.I2C1_SDA_O(),
.I2C1_SDA_T(),
.I2C1_SCL_I(1'B0),
.I2C1_SCL_O(),
.I2C1_SCL_T(),
.PJTAG_TCK(1'B0),
.PJTAG_TMS(1'B0),
.PJTAG_TDI(1'B0),
.PJTAG_TDO(),
.SDIO0_CLK(),
.SDIO0_CLK_FB(1'B0),
.SDIO0_CMD_O(),
.SDIO0_CMD_I(1'B0),
.SDIO0_CMD_T(),
.SDIO0_DATA_I(4'B0),
.SDIO0_DATA_O(),
.SDIO0_DATA_T(),
.SDIO0_LED(),
.SDIO0_CDN(1'B0),
.SDIO0_WP(1'B0),
.SDIO0_BUSPOW(),
.SDIO0_BUSVOLT(),
.SDIO1_CLK(),
.SDIO1_CLK_FB(1'B0),
.SDIO1_CMD_O(),
.SDIO1_CMD_I(1'B0),
.SDIO1_CMD_T(),
.SDIO1_DATA_I(4'B0),
.SDIO1_DATA_O(),
.SDIO1_DATA_T(),
.SDIO1_LED(),
.SDIO1_CDN(1'B0),
.SDIO1_WP(1'B0),
.SDIO1_BUSPOW(),
.SDIO1_BUSVOLT(),
.SPI0_SCLK_I(1'B0),
.SPI0_SCLK_O(),
.SPI0_SCLK_T(),
.SPI0_MOSI_I(1'B0),
.SPI0_MOSI_O(),
.SPI0_MOSI_T(),
.SPI0_MISO_I(1'B0),
.SPI0_MISO_O(),
.SPI0_MISO_T(),
.SPI0_SS_I(1'B0),
.SPI0_SS_O(),
.SPI0_SS1_O(),
.SPI0_SS2_O(),
.SPI0_SS_T(),
.SPI1_SCLK_I(1'B0),
.SPI1_SCLK_O(),
.SPI1_SCLK_T(),
.SPI1_MOSI_I(1'B0),
.SPI1_MOSI_O(),
.SPI1_MOSI_T(),
.SPI1_MISO_I(1'B0),
.SPI1_MISO_O(),
.SPI1_MISO_T(),
.SPI1_SS_I(1'B0),
.SPI1_SS_O(),
.SPI1_SS1_O(),
.SPI1_SS2_O(),
.SPI1_SS_T(),
.UART0_DTRN(),
.UART0_RTSN(),
.UART0_TX(),
.UART0_CTSN(1'B0),
.UART0_DCDN(1'B0),
.UART0_DSRN(1'B0),
.UART0_RIN(1'B0),
.UART0_RX(1'B1),
.UART1_DTRN(),
.UART1_RTSN(),
.UART1_TX(),
.UART1_CTSN(1'B0),
.UART1_DCDN(1'B0),
.UART1_DSRN(1'B0),
.UART1_RIN(1'B0),
.UART1_RX(1'B1),
.TTC0_WAVE0_OUT(TTC0_WAVE0_OUT),
.TTC0_WAVE1_OUT(TTC0_WAVE1_OUT),
.TTC0_WAVE2_OUT(TTC0_WAVE2_OUT),
.TTC0_CLK0_IN(1'B0),
.TTC0_CLK1_IN(1'B0),
.TTC0_CLK2_IN(1'B0),
.TTC1_WAVE0_OUT(),
.TTC1_WAVE1_OUT(),
.TTC1_WAVE2_OUT(),
.TTC1_CLK0_IN(1'B0),
.TTC1_CLK1_IN(1'B0),
.TTC1_CLK2_IN(1'B0),
.WDT_CLK_IN(1'B0),
.WDT_RST_OUT(),
.TRACE_CLK(1'B0),
.TRACE_CLK_OUT(),
.TRACE_CTL(),
.TRACE_DATA(),
.USB0_PORT_INDCTL(USB0_PORT_INDCTL),
.USB0_VBUS_PWRSELECT(USB0_VBUS_PWRSELECT),
.USB0_VBUS_PWRFAULT(USB0_VBUS_PWRFAULT),
.USB1_PORT_INDCTL(),
.USB1_VBUS_PWRSELECT(),
.USB1_VBUS_PWRFAULT(1'B0),
.SRAM_INTIN(1'B0),
.M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
.M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
.M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
.M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
.M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
.M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
.M_AXI_GP0_ARID(M_AXI_GP0_ARID),
.M_AXI_GP0_AWID(M_AXI_GP0_AWID),
.M_AXI_GP0_WID(M_AXI_GP0_WID),
.M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
.M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
.M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
.M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
.M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
.M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
.M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
.M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
.M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
.M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
.M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
.M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
.M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
.M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
.M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
.M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
.M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
.M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
.M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
.M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
.M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
.M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
.M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
.M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
.M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
.M_AXI_GP0_BID(M_AXI_GP0_BID),
.M_AXI_GP0_RID(M_AXI_GP0_RID),
.M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
.M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
.M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
.M_AXI_GP1_ARVALID(),
.M_AXI_GP1_AWVALID(),
.M_AXI_GP1_BREADY(),
.M_AXI_GP1_RREADY(),
.M_AXI_GP1_WLAST(),
.M_AXI_GP1_WVALID(),
.M_AXI_GP1_ARID(),
.M_AXI_GP1_AWID(),
.M_AXI_GP1_WID(),
.M_AXI_GP1_ARBURST(),
.M_AXI_GP1_ARLOCK(),
.M_AXI_GP1_ARSIZE(),
.M_AXI_GP1_AWBURST(),
.M_AXI_GP1_AWLOCK(),
.M_AXI_GP1_AWSIZE(),
.M_AXI_GP1_ARPROT(),
.M_AXI_GP1_AWPROT(),
.M_AXI_GP1_ARADDR(),
.M_AXI_GP1_AWADDR(),
.M_AXI_GP1_WDATA(),
.M_AXI_GP1_ARCACHE(),
.M_AXI_GP1_ARLEN(),
.M_AXI_GP1_ARQOS(),
.M_AXI_GP1_AWCACHE(),
.M_AXI_GP1_AWLEN(),
.M_AXI_GP1_AWQOS(),
.M_AXI_GP1_WSTRB(),
.M_AXI_GP1_ACLK(1'B0),
.M_AXI_GP1_ARREADY(1'B0),
.M_AXI_GP1_AWREADY(1'B0),
.M_AXI_GP1_BVALID(1'B0),
.M_AXI_GP1_RLAST(1'B0),
.M_AXI_GP1_RVALID(1'B0),
.M_AXI_GP1_WREADY(1'B0),
.M_AXI_GP1_BID(12'B0),
.M_AXI_GP1_RID(12'B0),
.M_AXI_GP1_BRESP(2'B0),
.M_AXI_GP1_RRESP(2'B0),
.M_AXI_GP1_RDATA(32'B0),
.S_AXI_GP0_ARREADY(),
.S_AXI_GP0_AWREADY(),
.S_AXI_GP0_BVALID(),
.S_AXI_GP0_RLAST(),
.S_AXI_GP0_RVALID(),
.S_AXI_GP0_WREADY(),
.S_AXI_GP0_BRESP(),
.S_AXI_GP0_RRESP(),
.S_AXI_GP0_RDATA(),
.S_AXI_GP0_BID(),
.S_AXI_GP0_RID(),
.S_AXI_GP0_ACLK(1'B0),
.S_AXI_GP0_ARVALID(1'B0),
.S_AXI_GP0_AWVALID(1'B0),
.S_AXI_GP0_BREADY(1'B0),
.S_AXI_GP0_RREADY(1'B0),
.S_AXI_GP0_WLAST(1'B0),
.S_AXI_GP0_WVALID(1'B0),
.S_AXI_GP0_ARBURST(2'B0),
.S_AXI_GP0_ARLOCK(2'B0),
.S_AXI_GP0_ARSIZE(3'B0),
.S_AXI_GP0_AWBURST(2'B0),
.S_AXI_GP0_AWLOCK(2'B0),
.S_AXI_GP0_AWSIZE(3'B0),
.S_AXI_GP0_ARPROT(3'B0),
.S_AXI_GP0_AWPROT(3'B0),
.S_AXI_GP0_ARADDR(32'B0),
.S_AXI_GP0_AWADDR(32'B0),
.S_AXI_GP0_WDATA(32'B0),
.S_AXI_GP0_ARCACHE(4'B0),
.S_AXI_GP0_ARLEN(4'B0),
.S_AXI_GP0_ARQOS(4'B0),
.S_AXI_GP0_AWCACHE(4'B0),
.S_AXI_GP0_AWLEN(4'B0),
.S_AXI_GP0_AWQOS(4'B0),
.S_AXI_GP0_WSTRB(4'B0),
.S_AXI_GP0_ARID(6'B0),
.S_AXI_GP0_AWID(6'B0),
.S_AXI_GP0_WID(6'B0),
.S_AXI_GP1_ARREADY(),
.S_AXI_GP1_AWREADY(),
.S_AXI_GP1_BVALID(),
.S_AXI_GP1_RLAST(),
.S_AXI_GP1_RVALID(),
.S_AXI_GP1_WREADY(),
.S_AXI_GP1_BRESP(),
.S_AXI_GP1_RRESP(),
.S_AXI_GP1_RDATA(),
.S_AXI_GP1_BID(),
.S_AXI_GP1_RID(),
.S_AXI_GP1_ACLK(1'B0),
.S_AXI_GP1_ARVALID(1'B0),
.S_AXI_GP1_AWVALID(1'B0),
.S_AXI_GP1_BREADY(1'B0),
.S_AXI_GP1_RREADY(1'B0),
.S_AXI_GP1_WLAST(1'B0),
.S_AXI_GP1_WVALID(1'B0),
.S_AXI_GP1_ARBURST(2'B0),
.S_AXI_GP1_ARLOCK(2'B0),
.S_AXI_GP1_ARSIZE(3'B0),
.S_AXI_GP1_AWBURST(2'B0),
.S_AXI_GP1_AWLOCK(2'B0),
.S_AXI_GP1_AWSIZE(3'B0),
.S_AXI_GP1_ARPROT(3'B0),
.S_AXI_GP1_AWPROT(3'B0),
.S_AXI_GP1_ARADDR(32'B0),
.S_AXI_GP1_AWADDR(32'B0),
.S_AXI_GP1_WDATA(32'B0),
.S_AXI_GP1_ARCACHE(4'B0),
.S_AXI_GP1_ARLEN(4'B0),
.S_AXI_GP1_ARQOS(4'B0),
.S_AXI_GP1_AWCACHE(4'B0),
.S_AXI_GP1_AWLEN(4'B0),
.S_AXI_GP1_AWQOS(4'B0),
.S_AXI_GP1_WSTRB(4'B0),
.S_AXI_GP1_ARID(6'B0),
.S_AXI_GP1_AWID(6'B0),
.S_AXI_GP1_WID(6'B0),
.S_AXI_ACP_ARREADY(),
.S_AXI_ACP_AWREADY(),
.S_AXI_ACP_BVALID(),
.S_AXI_ACP_RLAST(),
.S_AXI_ACP_RVALID(),
.S_AXI_ACP_WREADY(),
.S_AXI_ACP_BRESP(),
.S_AXI_ACP_RRESP(),
.S_AXI_ACP_BID(),
.S_AXI_ACP_RID(),
.S_AXI_ACP_RDATA(),
.S_AXI_ACP_ACLK(1'B0),
.S_AXI_ACP_ARVALID(1'B0),
.S_AXI_ACP_AWVALID(1'B0),
.S_AXI_ACP_BREADY(1'B0),
.S_AXI_ACP_RREADY(1'B0),
.S_AXI_ACP_WLAST(1'B0),
.S_AXI_ACP_WVALID(1'B0),
.S_AXI_ACP_ARID(3'B0),
.S_AXI_ACP_ARPROT(3'B0),
.S_AXI_ACP_AWID(3'B0),
.S_AXI_ACP_AWPROT(3'B0),
.S_AXI_ACP_WID(3'B0),
.S_AXI_ACP_ARADDR(32'B0),
.S_AXI_ACP_AWADDR(32'B0),
.S_AXI_ACP_ARCACHE(4'B0),
.S_AXI_ACP_ARLEN(4'B0),
.S_AXI_ACP_ARQOS(4'B0),
.S_AXI_ACP_AWCACHE(4'B0),
.S_AXI_ACP_AWLEN(4'B0),
.S_AXI_ACP_AWQOS(4'B0),
.S_AXI_ACP_ARBURST(2'B0),
.S_AXI_ACP_ARLOCK(2'B0),
.S_AXI_ACP_ARSIZE(3'B0),
.S_AXI_ACP_AWBURST(2'B0),
.S_AXI_ACP_AWLOCK(2'B0),
.S_AXI_ACP_AWSIZE(3'B0),
.S_AXI_ACP_ARUSER(5'B0),
.S_AXI_ACP_AWUSER(5'B0),
.S_AXI_ACP_WDATA(64'B0),
.S_AXI_ACP_WSTRB(8'B0),
.S_AXI_HP0_ARREADY(),
.S_AXI_HP0_AWREADY(),
.S_AXI_HP0_BVALID(),
.S_AXI_HP0_RLAST(),
.S_AXI_HP0_RVALID(),
.S_AXI_HP0_WREADY(),
.S_AXI_HP0_BRESP(),
.S_AXI_HP0_RRESP(),
.S_AXI_HP0_BID(),
.S_AXI_HP0_RID(),
.S_AXI_HP0_RDATA(),
.S_AXI_HP0_RCOUNT(),
.S_AXI_HP0_WCOUNT(),
.S_AXI_HP0_RACOUNT(),
.S_AXI_HP0_WACOUNT(),
.S_AXI_HP0_ACLK(1'B0),
.S_AXI_HP0_ARVALID(1'B0),
.S_AXI_HP0_AWVALID(1'B0),
.S_AXI_HP0_BREADY(1'B0),
.S_AXI_HP0_RDISSUECAP1_EN(1'B0),
.S_AXI_HP0_RREADY(1'B0),
.S_AXI_HP0_WLAST(1'B0),
.S_AXI_HP0_WRISSUECAP1_EN(1'B0),
.S_AXI_HP0_WVALID(1'B0),
.S_AXI_HP0_ARBURST(2'B0),
.S_AXI_HP0_ARLOCK(2'B0),
.S_AXI_HP0_ARSIZE(3'B0),
.S_AXI_HP0_AWBURST(2'B0),
.S_AXI_HP0_AWLOCK(2'B0),
.S_AXI_HP0_AWSIZE(3'B0),
.S_AXI_HP0_ARPROT(3'B0),
.S_AXI_HP0_AWPROT(3'B0),
.S_AXI_HP0_ARADDR(32'B0),
.S_AXI_HP0_AWADDR(32'B0),
.S_AXI_HP0_ARCACHE(4'B0),
.S_AXI_HP0_ARLEN(4'B0),
.S_AXI_HP0_ARQOS(4'B0),
.S_AXI_HP0_AWCACHE(4'B0),
.S_AXI_HP0_AWLEN(4'B0),
.S_AXI_HP0_AWQOS(4'B0),
.S_AXI_HP0_ARID(6'B0),
.S_AXI_HP0_AWID(6'B0),
.S_AXI_HP0_WID(6'B0),
.S_AXI_HP0_WDATA(64'B0),
.S_AXI_HP0_WSTRB(8'B0),
.S_AXI_HP1_ARREADY(),
.S_AXI_HP1_AWREADY(),
.S_AXI_HP1_BVALID(),
.S_AXI_HP1_RLAST(),
.S_AXI_HP1_RVALID(),
.S_AXI_HP1_WREADY(),
.S_AXI_HP1_BRESP(),
.S_AXI_HP1_RRESP(),
.S_AXI_HP1_BID(),
.S_AXI_HP1_RID(),
.S_AXI_HP1_RDATA(),
.S_AXI_HP1_RCOUNT(),
.S_AXI_HP1_WCOUNT(),
.S_AXI_HP1_RACOUNT(),
.S_AXI_HP1_WACOUNT(),
.S_AXI_HP1_ACLK(1'B0),
.S_AXI_HP1_ARVALID(1'B0),
.S_AXI_HP1_AWVALID(1'B0),
.S_AXI_HP1_BREADY(1'B0),
.S_AXI_HP1_RDISSUECAP1_EN(1'B0),
.S_AXI_HP1_RREADY(1'B0),
.S_AXI_HP1_WLAST(1'B0),
.S_AXI_HP1_WRISSUECAP1_EN(1'B0),
.S_AXI_HP1_WVALID(1'B0),
.S_AXI_HP1_ARBURST(2'B0),
.S_AXI_HP1_ARLOCK(2'B0),
.S_AXI_HP1_ARSIZE(3'B0),
.S_AXI_HP1_AWBURST(2'B0),
.S_AXI_HP1_AWLOCK(2'B0),
.S_AXI_HP1_AWSIZE(3'B0),
.S_AXI_HP1_ARPROT(3'B0),
.S_AXI_HP1_AWPROT(3'B0),
.S_AXI_HP1_ARADDR(32'B0),
.S_AXI_HP1_AWADDR(32'B0),
.S_AXI_HP1_ARCACHE(4'B0),
.S_AXI_HP1_ARLEN(4'B0),
.S_AXI_HP1_ARQOS(4'B0),
.S_AXI_HP1_AWCACHE(4'B0),
.S_AXI_HP1_AWLEN(4'B0),
.S_AXI_HP1_AWQOS(4'B0),
.S_AXI_HP1_ARID(6'B0),
.S_AXI_HP1_AWID(6'B0),
.S_AXI_HP1_WID(6'B0),
.S_AXI_HP1_WDATA(64'B0),
.S_AXI_HP1_WSTRB(8'B0),
.S_AXI_HP2_ARREADY(),
.S_AXI_HP2_AWREADY(),
.S_AXI_HP2_BVALID(),
.S_AXI_HP2_RLAST(),
.S_AXI_HP2_RVALID(),
.S_AXI_HP2_WREADY(),
.S_AXI_HP2_BRESP(),
.S_AXI_HP2_RRESP(),
.S_AXI_HP2_BID(),
.S_AXI_HP2_RID(),
.S_AXI_HP2_RDATA(),
.S_AXI_HP2_RCOUNT(),
.S_AXI_HP2_WCOUNT(),
.S_AXI_HP2_RACOUNT(),
.S_AXI_HP2_WACOUNT(),
.S_AXI_HP2_ACLK(1'B0),
.S_AXI_HP2_ARVALID(1'B0),
.S_AXI_HP2_AWVALID(1'B0),
.S_AXI_HP2_BREADY(1'B0),
.S_AXI_HP2_RDISSUECAP1_EN(1'B0),
.S_AXI_HP2_RREADY(1'B0),
.S_AXI_HP2_WLAST(1'B0),
.S_AXI_HP2_WRISSUECAP1_EN(1'B0),
.S_AXI_HP2_WVALID(1'B0),
.S_AXI_HP2_ARBURST(2'B0),
.S_AXI_HP2_ARLOCK(2'B0),
.S_AXI_HP2_ARSIZE(3'B0),
.S_AXI_HP2_AWBURST(2'B0),
.S_AXI_HP2_AWLOCK(2'B0),
.S_AXI_HP2_AWSIZE(3'B0),
.S_AXI_HP2_ARPROT(3'B0),
.S_AXI_HP2_AWPROT(3'B0),
.S_AXI_HP2_ARADDR(32'B0),
.S_AXI_HP2_AWADDR(32'B0),
.S_AXI_HP2_ARCACHE(4'B0),
.S_AXI_HP2_ARLEN(4'B0),
.S_AXI_HP2_ARQOS(4'B0),
.S_AXI_HP2_AWCACHE(4'B0),
.S_AXI_HP2_AWLEN(4'B0),
.S_AXI_HP2_AWQOS(4'B0),
.S_AXI_HP2_ARID(6'B0),
.S_AXI_HP2_AWID(6'B0),
.S_AXI_HP2_WID(6'B0),
.S_AXI_HP2_WDATA(64'B0),
.S_AXI_HP2_WSTRB(8'B0),
.S_AXI_HP3_ARREADY(),
.S_AXI_HP3_AWREADY(),
.S_AXI_HP3_BVALID(),
.S_AXI_HP3_RLAST(),
.S_AXI_HP3_RVALID(),
.S_AXI_HP3_WREADY(),
.S_AXI_HP3_BRESP(),
.S_AXI_HP3_RRESP(),
.S_AXI_HP3_BID(),
.S_AXI_HP3_RID(),
.S_AXI_HP3_RDATA(),
.S_AXI_HP3_RCOUNT(),
.S_AXI_HP3_WCOUNT(),
.S_AXI_HP3_RACOUNT(),
.S_AXI_HP3_WACOUNT(),
.S_AXI_HP3_ACLK(1'B0),
.S_AXI_HP3_ARVALID(1'B0),
.S_AXI_HP3_AWVALID(1'B0),
.S_AXI_HP3_BREADY(1'B0),
.S_AXI_HP3_RDISSUECAP1_EN(1'B0),
.S_AXI_HP3_RREADY(1'B0),
.S_AXI_HP3_WLAST(1'B0),
.S_AXI_HP3_WRISSUECAP1_EN(1'B0),
.S_AXI_HP3_WVALID(1'B0),
.S_AXI_HP3_ARBURST(2'B0),
.S_AXI_HP3_ARLOCK(2'B0),
.S_AXI_HP3_ARSIZE(3'B0),
.S_AXI_HP3_AWBURST(2'B0),
.S_AXI_HP3_AWLOCK(2'B0),
.S_AXI_HP3_AWSIZE(3'B0),
.S_AXI_HP3_ARPROT(3'B0),
.S_AXI_HP3_AWPROT(3'B0),
.S_AXI_HP3_ARADDR(32'B0),
.S_AXI_HP3_AWADDR(32'B0),
.S_AXI_HP3_ARCACHE(4'B0),
.S_AXI_HP3_ARLEN(4'B0),
.S_AXI_HP3_ARQOS(4'B0),
.S_AXI_HP3_AWCACHE(4'B0),
.S_AXI_HP3_AWLEN(4'B0),
.S_AXI_HP3_AWQOS(4'B0),
.S_AXI_HP3_ARID(6'B0),
.S_AXI_HP3_AWID(6'B0),
.S_AXI_HP3_WID(6'B0),
.S_AXI_HP3_WDATA(64'B0),
.S_AXI_HP3_WSTRB(8'B0),
.IRQ_P2F_DMAC_ABORT(),
.IRQ_P2F_DMAC0(),
.IRQ_P2F_DMAC1(),
.IRQ_P2F_DMAC2(),
.IRQ_P2F_DMAC3(),
.IRQ_P2F_DMAC4(),
.IRQ_P2F_DMAC5(),
.IRQ_P2F_DMAC6(),
.IRQ_P2F_DMAC7(),
.IRQ_P2F_SMC(),
.IRQ_P2F_QSPI(),
.IRQ_P2F_CTI(),
.IRQ_P2F_GPIO(),
.IRQ_P2F_USB0(),
.IRQ_P2F_ENET0(),
.IRQ_P2F_ENET_WAKE0(),
.IRQ_P2F_SDIO0(),
.IRQ_P2F_I2C0(),
.IRQ_P2F_SPI0(),
.IRQ_P2F_UART0(),
.IRQ_P2F_CAN0(),
.IRQ_P2F_USB1(),
.IRQ_P2F_ENET1(),
.IRQ_P2F_ENET_WAKE1(),
.IRQ_P2F_SDIO1(),
.IRQ_P2F_I2C1(),
.IRQ_P2F_SPI1(),
.IRQ_P2F_UART1(),
.IRQ_P2F_CAN1(),
.IRQ_F2P(1'B0),
.Core0_nFIQ(1'B0),
.Core0_nIRQ(1'B0),
.Core1_nFIQ(1'B0),
.Core1_nIRQ(1'B0),
.DMA0_DATYPE(),
.DMA0_DAVALID(),
.DMA0_DRREADY(),
.DMA1_DATYPE(),
.DMA1_DAVALID(),
.DMA1_DRREADY(),
.DMA2_DATYPE(),
.DMA2_DAVALID(),
.DMA2_DRREADY(),
.DMA3_DATYPE(),
.DMA3_DAVALID(),
.DMA3_DRREADY(),
.DMA0_ACLK(1'B0),
.DMA0_DAREADY(1'B0),
.DMA0_DRLAST(1'B0),
.DMA0_DRVALID(1'B0),
.DMA1_ACLK(1'B0),
.DMA1_DAREADY(1'B0),
.DMA1_DRLAST(1'B0),
.DMA1_DRVALID(1'B0),
.DMA2_ACLK(1'B0),
.DMA2_DAREADY(1'B0),
.DMA2_DRLAST(1'B0),
.DMA2_DRVALID(1'B0),
.DMA3_ACLK(1'B0),
.DMA3_DAREADY(1'B0),
.DMA3_DRLAST(1'B0),
.DMA3_DRVALID(1'B0),
.DMA0_DRTYPE(2'B0),
.DMA1_DRTYPE(2'B0),
.DMA2_DRTYPE(2'B0),
.DMA3_DRTYPE(2'B0),
.FCLK_CLK0(FCLK_CLK0),
.FCLK_CLK1(),
.FCLK_CLK2(),
.FCLK_CLK3(),
.FCLK_CLKTRIG0_N(1'B0),
.FCLK_CLKTRIG1_N(1'B0),
.FCLK_CLKTRIG2_N(1'B0),
.FCLK_CLKTRIG3_N(1'B0),
.FCLK_RESET0_N(FCLK_RESET0_N),
.FCLK_RESET1_N(),
.FCLK_RESET2_N(),
.FCLK_RESET3_N(),
.FTMD_TRACEIN_DATA(32'B0),
.FTMD_TRACEIN_VALID(1'B0),
.FTMD_TRACEIN_CLK(1'B0),
.FTMD_TRACEIN_ATID(4'B0),
.FTMT_F2P_TRIG_0(1'B0),
.FTMT_F2P_TRIGACK_0(),
.FTMT_F2P_TRIG_1(1'B0),
.FTMT_F2P_TRIGACK_1(),
.FTMT_F2P_TRIG_2(1'B0),
.FTMT_F2P_TRIGACK_2(),
.FTMT_F2P_TRIG_3(1'B0),
.FTMT_F2P_TRIGACK_3(),
.FTMT_F2P_DEBUG(32'B0),
.FTMT_P2F_TRIGACK_0(1'B0),
.FTMT_P2F_TRIG_0(),
.FTMT_P2F_TRIGACK_1(1'B0),
.FTMT_P2F_TRIG_1(),
.FTMT_P2F_TRIGACK_2(1'B0),
.FTMT_P2F_TRIG_2(),
.FTMT_P2F_TRIGACK_3(1'B0),
.FTMT_P2F_TRIG_3(),
.FTMT_P2F_DEBUG(),
.FPGA_IDLE_N(1'B0),
.EVENT_EVENTO(),
.EVENT_STANDBYWFE(),
.EVENT_STANDBYWFI(),
.EVENT_EVENTI(1'B0),
.DDR_ARB(4'B0),
.MIO(MIO),
.DDR_CAS_n(DDR_CAS_n),
.DDR_CKE(DDR_CKE),
.DDR_Clk_n(DDR_Clk_n),
.DDR_Clk(DDR_Clk),
.DDR_CS_n(DDR_CS_n),
.DDR_DRSTB(DDR_DRSTB),
.DDR_ODT(DDR_ODT),
.DDR_RAS_n(DDR_RAS_n),
.DDR_WEB(DDR_WEB),
.DDR_BankAddr(DDR_BankAddr),
.DDR_Addr(DDR_Addr),
.DDR_VRN(DDR_VRN),
.DDR_VRP(DDR_VRP),
.DDR_DM(DDR_DM),
.DDR_DQ(DDR_DQ),
.DDR_DQS_n(DDR_DQS_n),
.DDR_DQS(DDR_DQS),
.PS_SRSTB(PS_SRSTB),
.PS_CLK(PS_CLK),
.PS_PORB(PS_PORB)
);
endmodule
|
module bridge (
// EC/LIMB data bus
inout [7:0] limb_d,
input limb_start,
input limb_clk,
input limb_nrd,
output limb_nwait,
output limb_nreq,
// CPU bus
inout [31:0] cpu_d,
output cpu_nwait,
input cpu_naddr,
input cpu_nwr,
input [1:0] cpu_nreq,
output [1:0] cpu_nack,
output [1:0] cpu_nint,
output cpu_clk_out,
input cpu_clk_in,
// PCI bus
inout [31:0] pci_ad,
input [3:0] pci_nreq,
output [3:0] pci_ngnt,
input [3:0] pci_nint,
output [3:0] pci_cbe,
output pci_nframe,
input pci_ntrdy,
output pci_nirdy,
output pci_ndevsel,
input pci_nstop,
inout pci_nserr,
inout pci_nperr,
inout pci_nlock,
inout pci_parity,
output pci_clk,
// DDR3 SDRAM
inout [7:0] ddr_ndqs,
inout [7:0] ddr_pdqs,
output [2:0] ddr_ba,
output [15:0] ddr_addr,
output [7:0] ddr_dm,
output [1:0] ddr_nck,
output [1:0] ddr_pck,
output [1:0] ddr_cke,
output ddr_nwe,
output ddr_ncas,
output ddr_nras,
output [1:0] ddr_ns,
output [1:0] ddr_odt,
inout [63:0] ddr_dq,
input ddr_clk_in
);
assign pci_ad = 32'hZZZZZZZZ;
assign pci_nserr = 1'bZ;
assign pci_nperr = 1'bZ;
assign pci_nlock = 1'bZ;
assign pci_parity = 1'bZ;
assign pci_clk = 1'b0;
assign pci_ngnt = 4'hF;
assign pci_cbe = 4'hF;
assign pci_nframe = 1'b1;
assign pci_nirdy = 1'b1;
assign pci_ndevsel = 1'b1;
assign cpu_d = 32'hZZZZZZZZ;
assign cpu_nwait = 1'b1;
assign cpu_nack = 2'b11;
assign cpu_nint = 2'b11;
assign cpu_clk_out = 1'b0;
assign limb_nreq = 1'b0;
wire [31:0] gpio_in;
wire [31:0] gpio_out;
wire clk150;
wire clk75;
wire[2:0] ddr_cmd;
wire reset;
`define DEF_WISHBONE_WIRES(name) \
wire [35:0] wb_adr_``name; \
wire wb_we_``name; \
wire [3:0] wb_sel_``name; \
wire wb_stb_``name; \
wire wb_cyc_``name; \
wire [31:0] wb_dat_to_``name; \
wire [31:0] wb_dat_from_``name; \
wire wb_ack_``name;
`define DEF_WISHBONE_UNUSED(n) \
wire wb_ack_stb_``n;
`define CONNECT_MASTER(n, name) \
.m``n``_data_i(wb_dat_from_``name), \
.m``n``_data_o(wb_dat_to_``name), \
.m``n``_addr_i(wb_adr_``name), \
.m``n``_sel_i(wb_sel_``name), \
.m``n``_we_i(wb_we_``name), \
.m``n``_cyc_i(wb_cyc_``name), \
.m``n``_stb_i(wb_stb_``name), \
.m``n``_ack_o(wb_ack_``name)
`define UNUSED_MASTER(n) \
.m``n``_data_i(32'h00000000), \
.m``n``_addr_i(36'h000000000), \
.m``n``_sel_i(4'h0), \
.m``n``_we_i(1'b0), \
.m``n``_cyc_i(1'b0), \
.m``n``_stb_i(1'b0)
`define CONNECT_SLAVE(n, name) \
.s``n``_data_i(wb_dat_from_``name), \
.s``n``_data_o(wb_dat_to_``name), \
.s``n``_addr_o(wb_adr_``name), \
.s``n``_sel_o(wb_sel_``name), \
.s``n``_we_o(wb_we_``name), \
.s``n``_cyc_o(wb_cyc_``name), \
.s``n``_stb_o(wb_stb_``name), \
.s``n``_ack_i(wb_ack_``name), \
.s``n``_err_i(1'b0), \
.s``n``_rty_i(1'b0)
`define UNUSED_SLAVE(n) \
.s``n``_data_i(32'h00000000), \
.s``n``_ack_i(wb_ack_stb_``n), \
.s``n``_stb_o(wb_ack_stb_``n), \
.s``n``_err_i(1'b0), \
.s``n``_rty_i(1'b0)
`DEF_WISHBONE_WIRES(limb)
`DEF_WISHBONE_WIRES(blockram)
`DEF_WISHBONE_WIRES(dram)
`DEF_WISHBONE_WIRES(gpio)
`DEF_WISHBONE_UNUSED(1)
`DEF_WISHBONE_UNUSED(2)
`DEF_WISHBONE_UNUSED(3)
`DEF_WISHBONE_UNUSED(4)
`DEF_WISHBONE_UNUSED(5)
`DEF_WISHBONE_UNUSED(6)
`DEF_WISHBONE_UNUSED(7)
`DEF_WISHBONE_UNUSED(8)
`DEF_WISHBONE_UNUSED(9)
`DEF_WISHBONE_UNUSED(10)
`DEF_WISHBONE_UNUSED(11)
`DEF_WISHBONE_UNUSED(12)
`DEF_WISHBONE_UNUSED(13)
`DEF_WISHBONE_UNUSED(15)
wire [7:0] limb_d_out;
wire limb_d_oe;
//assign wb_adr = {wb_adr_full[3:0], 2'b00};
assign limb_d = limb_d_oe ? limb_d_out : 8'bZZZZZZZZ;
limb_interface limb_interface_inst (
.limb_d_in(limb_d),
.limb_d_out(limb_d_out),
.limb_d_oe(limb_d_oe),
.limb_clk(limb_clk),
.limb_nrd(limb_nrd),
.limb_start(limb_start),
.limb_nwait(limb_nwait),
.wb_adr_o(wb_adr_limb),
.wb_we_o(wb_we_limb),
.wb_sel_o(wb_sel_limb),
.wb_stb_o(wb_stb_limb),
.wb_cyc_o(wb_cyc_limb),
.wb_dat_o(wb_dat_from_limb),
.wb_dat_i(wb_dat_to_limb),
.wb_ack_i(wb_ack_limb),
.clk(clk75) );
wb_ram #( .ADDR_WIDTH(6) ) wb_ram_inst (
.clk(clk75),
.adr_i({wb_adr_blockram[3:0], 2'b00}),
.dat_i(wb_dat_to_blockram),
.dat_o(wb_dat_from_blockram),
.we_i(wb_we_blockram),
.sel_i(wb_sel_blockram),
.stb_i(wb_stb_blockram),
.ack_o(wb_ack_blockram),
.cyc_i(wb_cyc_blockram) );
wb_conmax_top #( .dw(32), .aw(36) ) wb_conmax_inst (
.clk_i(clk75),
.rst_i(1'b0),
`CONNECT_MASTER(0, limb),
`UNUSED_MASTER(1),
`UNUSED_MASTER(2),
`UNUSED_MASTER(3),
`UNUSED_MASTER(4),
`UNUSED_MASTER(5),
`UNUSED_MASTER(6),
`UNUSED_MASTER(7),
`CONNECT_SLAVE(0, blockram),
`CONNECT_SLAVE(1, gpio),
`UNUSED_SLAVE(2),
`UNUSED_SLAVE(3),
`UNUSED_SLAVE(4),
`UNUSED_SLAVE(5),
`UNUSED_SLAVE(6),
`UNUSED_SLAVE(7),
`UNUSED_SLAVE(8),
`UNUSED_SLAVE(9),
`UNUSED_SLAVE(10),
`UNUSED_SLAVE(11),
`UNUSED_SLAVE(12),
`UNUSED_SLAVE(13),
`CONNECT_SLAVE(14, dram),
`UNUSED_SLAVE(15)
);
wire drac_srd;
wire drac_swr;
wire [33:5] drac_sa;
wire [255:0] drac_swdat;
wire [31:0] drac_smsk;
wire [255:0] drac_srdat;
wire drac_srdy;
wire [2:0] drac_dbg_in;
wire [7:0] drac_dbg_out;
assign ddr_nras = ddr_cmd[2];
assign ddr_ncas = ddr_cmd[1];
assign ddr_nwe = ddr_cmd[0];
drac_wb_adapter drac_wb (
.drac_srd_o (drac_srd),
.drac_swr_o (drac_swr),
.drac_sa_o (drac_sa),
.drac_swdat_o (drac_swdat),
.drac_smsk_o (drac_smsk),
.drac_srdat_i (drac_srdat),
.drac_srdy_i (drac_srdy),
.clk150 (clk150),
.wb_adr_i (wb_adr_dram),
.wb_we_i (wb_we_dram),
.wb_sel_i (wb_sel_dram),
.wb_stb_i (wb_stb_dram),
.wb_cyc_i (wb_cyc_dram),
.wb_dat_i (wb_dat_to_dram),
.wb_dat_o (wb_dat_from_dram),
.wb_ack_o (wb_ack_dram),
.clk75 (clk75),
.reset (reset)
);
drac_ddr3 drac (
.ckin (ddr_clk_in), // should be 62.5 MHz
.ckout (clk150),
.ckouthalf (clk75),
.reset (reset),
.ddq (ddr_dq),
.dqsp (ddr_pdqs),
.dqsn (ddr_ndqs),
.ddm (ddr_dm),
.da (ddr_addr),
.dba (ddr_ba),
.dcmd (ddr_cmd),
.dce (ddr_cke),
.dcs (ddr_ns),
.dckp (ddr_pck),
.dckn (ddr_nck),
.dodt (ddr_odt),
.srd(drac_srd),
.swr(drac_swr),
.sa(drac_sa),
.swdat(drac_swdat),
.smsk(drac_smsk),
.srdat(drac_srdat),
.srdy(drac_srdy),
.dbg_out(drac_dbg_in),
.dbg_in(drac_dbg_out)
);
wb_simple_gpio gpio (
.wb_adr_i (wb_adr_gpio),
.wb_we_i (wb_we_gpio),
.wb_sel_i (wb_sel_gpio),
.wb_stb_i (wb_stb_gpio),
.wb_cyc_i (wb_cyc_gpio),
.wb_dat_i (wb_dat_to_gpio),
.wb_dat_o (wb_dat_from_gpio),
.wb_ack_o (wb_ack_gpio),
.gpio_in (gpio_in),
.gpio_out (gpio_out),
.clk (clk75)
);
assign gpio_in[7:0] = drac_dbg_out;
assign gpio_in[8] = reset;
assign drac_dbg_in = gpio_out[2:0];
endmodule
|
//==================================================================================================
// Filename : antares_cloz.v
// Created On : Thu Sep 3 16:03:13 2015
// Last Modified : Sat Nov 07 11:49:40 2015
// Revision : 1.0
// Author : Angel Terrones
// Company : Universidad Simón Bolívar
// Email : [email protected]
//
// Description : Count leading ones/zeros unit.
//==================================================================================================
module antares_cloz (
input [31:0] A,
output [5:0] clo_result,
output [5:0] clz_result
);
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg [5:0] clo_result;
reg [5:0] clz_result;
// End of automatics
//--------------------------------------------------------------------------
// Count Leading Ones
//--------------------------------------------------------------------------
always @(*) begin
casez (A)
32'b0zzz_zzzz_zzzz_zzzz_zzzz_zzzz_zzzz_zzzz : clo_result = 6'd0;
32'b10zz_zzzz_zzzz_zzzz_zzzz_zzzz_zzzz_zzzz : clo_result = 6'd1;
32'b110z_zzzz_zzzz_zzzz_zzzz_zzzz_zzzz_zzzz : clo_result = 6'd2;
32'b1110_zzzz_zzzz_zzzz_zzzz_zzzz_zzzz_zzzz : clo_result = 6'd3;
32'b1111_0zzz_zzzz_zzzz_zzzz_zzzz_zzzz_zzzz : clo_result = 6'd4;
32'b1111_10zz_zzzz_zzzz_zzzz_zzzz_zzzz_zzzz : clo_result = 6'd5;
32'b1111_110z_zzzz_zzzz_zzzz_zzzz_zzzz_zzzz : clo_result = 6'd6;
32'b1111_1110_zzzz_zzzz_zzzz_zzzz_zzzz_zzzz : clo_result = 6'd7;
32'b1111_1111_0zzz_zzzz_zzzz_zzzz_zzzz_zzzz : clo_result = 6'd8;
32'b1111_1111_10zz_zzzz_zzzz_zzzz_zzzz_zzzz : clo_result = 6'd9;
32'b1111_1111_110z_zzzz_zzzz_zzzz_zzzz_zzzz : clo_result = 6'd10;
32'b1111_1111_1110_zzzz_zzzz_zzzz_zzzz_zzzz : clo_result = 6'd11;
32'b1111_1111_1111_0zzz_zzzz_zzzz_zzzz_zzzz : clo_result = 6'd12;
32'b1111_1111_1111_10zz_zzzz_zzzz_zzzz_zzzz : clo_result = 6'd13;
32'b1111_1111_1111_110z_zzzz_zzzz_zzzz_zzzz : clo_result = 6'd14;
32'b1111_1111_1111_1110_zzzz_zzzz_zzzz_zzzz : clo_result = 6'd15;
32'b1111_1111_1111_1111_0zzz_zzzz_zzzz_zzzz : clo_result = 6'd16;
32'b1111_1111_1111_1111_10zz_zzzz_zzzz_zzzz : clo_result = 6'd17;
32'b1111_1111_1111_1111_110z_zzzz_zzzz_zzzz : clo_result = 6'd18;
32'b1111_1111_1111_1111_1110_zzzz_zzzz_zzzz : clo_result = 6'd19;
32'b1111_1111_1111_1111_1111_0zzz_zzzz_zzzz : clo_result = 6'd20;
32'b1111_1111_1111_1111_1111_10zz_zzzz_zzzz : clo_result = 6'd21;
32'b1111_1111_1111_1111_1111_110z_zzzz_zzzz : clo_result = 6'd22;
32'b1111_1111_1111_1111_1111_1110_zzzz_zzzz : clo_result = 6'd23;
32'b1111_1111_1111_1111_1111_1111_0zzz_zzzz : clo_result = 6'd24;
32'b1111_1111_1111_1111_1111_1111_10zz_zzzz : clo_result = 6'd25;
32'b1111_1111_1111_1111_1111_1111_110z_zzzz : clo_result = 6'd26;
32'b1111_1111_1111_1111_1111_1111_1110_zzzz : clo_result = 6'd27;
32'b1111_1111_1111_1111_1111_1111_1111_0zzz : clo_result = 6'd28;
32'b1111_1111_1111_1111_1111_1111_1111_10zz : clo_result = 6'd29;
32'b1111_1111_1111_1111_1111_1111_1111_110z : clo_result = 6'd30;
32'b1111_1111_1111_1111_1111_1111_1111_1110 : clo_result = 6'd31;
32'b1111_1111_1111_1111_1111_1111_1111_1111 : clo_result = 6'd32;
default : clo_result = 6'd0;
endcase // casez (A)
end // always @ (*)
//--------------------------------------------------------------------------
// Count Leading Zeros
//--------------------------------------------------------------------------
always @(*) begin
casez (A)
32'b1zzz_zzzz_zzzz_zzzz_zzzz_zzzz_zzzz_zzzz : clz_result = 6'd0;
32'b01zz_zzzz_zzzz_zzzz_zzzz_zzzz_zzzz_zzzz : clz_result = 6'd1;
32'b001z_zzzz_zzzz_zzzz_zzzz_zzzz_zzzz_zzzz : clz_result = 6'd2;
32'b0001_zzzz_zzzz_zzzz_zzzz_zzzz_zzzz_zzzz : clz_result = 6'd3;
32'b0000_1zzz_zzzz_zzzz_zzzz_zzzz_zzzz_zzzz : clz_result = 6'd4;
32'b0000_01zz_zzzz_zzzz_zzzz_zzzz_zzzz_zzzz : clz_result = 6'd5;
32'b0000_001z_zzzz_zzzz_zzzz_zzzz_zzzz_zzzz : clz_result = 6'd6;
32'b0000_0001_zzzz_zzzz_zzzz_zzzz_zzzz_zzzz : clz_result = 6'd7;
32'b0000_0000_1zzz_zzzz_zzzz_zzzz_zzzz_zzzz : clz_result = 6'd8;
32'b0000_0000_01zz_zzzz_zzzz_zzzz_zzzz_zzzz : clz_result = 6'd9;
32'b0000_0000_001z_zzzz_zzzz_zzzz_zzzz_zzzz : clz_result = 6'd10;
32'b0000_0000_0001_zzzz_zzzz_zzzz_zzzz_zzzz : clz_result = 6'd11;
32'b0000_0000_0000_1zzz_zzzz_zzzz_zzzz_zzzz : clz_result = 6'd12;
32'b0000_0000_0000_01zz_zzzz_zzzz_zzzz_zzzz : clz_result = 6'd13;
32'b0000_0000_0000_001z_zzzz_zzzz_zzzz_zzzz : clz_result = 6'd14;
32'b0000_0000_0000_0001_zzzz_zzzz_zzzz_zzzz : clz_result = 6'd15;
32'b0000_0000_0000_0000_1zzz_zzzz_zzzz_zzzz : clz_result = 6'd16;
32'b0000_0000_0000_0000_01zz_zzzz_zzzz_zzzz : clz_result = 6'd17;
32'b0000_0000_0000_0000_001z_zzzz_zzzz_zzzz : clz_result = 6'd18;
32'b0000_0000_0000_0000_0001_zzzz_zzzz_zzzz : clz_result = 6'd19;
32'b0000_0000_0000_0000_0000_1zzz_zzzz_zzzz : clz_result = 6'd20;
32'b0000_0000_0000_0000_0000_01zz_zzzz_zzzz : clz_result = 6'd21;
32'b0000_0000_0000_0000_0000_001z_zzzz_zzzz : clz_result = 6'd22;
32'b0000_0000_0000_0000_0000_0001_zzzz_zzzz : clz_result = 6'd23;
32'b0000_0000_0000_0000_0000_0000_1zzz_zzzz : clz_result = 6'd24;
32'b0000_0000_0000_0000_0000_0000_01zz_zzzz : clz_result = 6'd25;
32'b0000_0000_0000_0000_0000_0000_001z_zzzz : clz_result = 6'd26;
32'b0000_0000_0000_0000_0000_0000_0001_zzzz : clz_result = 6'd27;
32'b0000_0000_0000_0000_0000_0000_0000_1zzz : clz_result = 6'd28;
32'b0000_0000_0000_0000_0000_0000_0000_01zz : clz_result = 6'd29;
32'b0000_0000_0000_0000_0000_0000_0000_001z : clz_result = 6'd30;
32'b0000_0000_0000_0000_0000_0000_0000_0001 : clz_result = 6'd31;
32'b0000_0000_0000_0000_0000_0000_0000_0000 : clz_result = 6'd32;
default : clz_result = 6'd0;
endcase // casez (A)
end // always @ (*)
endmodule // antares_cloz
|
/////////////////////////////////////////////////////////////////////////
// Copyright (c) 2008 Xilinx, Inc. All rights reserved.
//
// XILINX CONFIDENTIAL PROPERTY
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Xilinx, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivitive work, nothing in this notice overrides the
// original author's license agreeement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// Xilinx, Inc.
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
/////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's Power Management ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// PM according to OR1K architectural specification. ////
//// ////
//// To Do: ////
//// - add support for dynamic clock gating ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_pm.v,v $
// Revision 1.1 2008/05/07 22:43:22 daughtry
// Initial Demo RTL check-in
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.8 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.7 2001/10/14 13:12:10 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:35 igorm
// no message
//
// Revision 1.2 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.1 2001/07/20 00:46:21 lampret
// Development version of RTL. Libraries are missing.
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_pm(
// RISC Internal Interface
clk, rst, pic_wakeup, spr_write, spr_addr, spr_dat_i, spr_dat_o,
// Power Management Interface
pm_clksd, pm_cpustall, pm_dc_gate, pm_ic_gate, pm_dmmu_gate,
pm_immu_gate, pm_tt_gate, pm_cpu_gate, pm_wakeup, pm_lvolt
);
//
// RISC Internal Interface
//
input clk; // Clock
input rst; // Reset
input pic_wakeup; // Wakeup from the PIC
input spr_write; // SPR Read/Write
input [31:0] spr_addr; // SPR Address
input [31:0] spr_dat_i; // SPR Write Data
output [31:0] spr_dat_o; // SPR Read Data
//
// Power Management Interface
//
input pm_cpustall; // Stall the CPU
output [3:0] pm_clksd; // Clock Slowdown factor
output pm_dc_gate; // Gate DCache clock
output pm_ic_gate; // Gate ICache clock
output pm_dmmu_gate; // Gate DMMU clock
output pm_immu_gate; // Gate IMMU clock
output pm_tt_gate; // Gate Tick Timer clock
output pm_cpu_gate; // Gate main RISC/CPU clock
output pm_wakeup; // Activate (de-gate) all clocks
output pm_lvolt; // Lower operating voltage
`ifdef OR1200_PM_IMPLEMENTED
//
// Power Management Register bits
//
reg [3:0] sdf; // Slow-down factor
reg dme; // Doze Mode Enable
reg sme; // Sleep Mode Enable
reg dcge; // Dynamic Clock Gating Enable
reg pm_cpustall_reg;
//
// Internal wires
//
wire pmr_sel; // PMR select
//
// PMR address decoder (partial decoder)
//
`ifdef OR1200_PM_PARTIAL_DECODING
assign pmr_sel = (spr_addr[`OR1200_SPR_GROUP_BITS] == `OR1200_SPRGRP_PM) ? 1'b1 : 1'b0;
`else
assign pmr_sel = ((spr_addr[`OR1200_SPR_GROUP_BITS] == `OR1200_SPRGRP_PM) &&
(spr_addr[`OR1200_SPR_OFS_BITS] == `OR1200_PM_OFS_PMR)) ? 1'b1 : 1'b0;
`endif
//
// Write to PMR and also PMR[DME]/PMR[SME] reset when
// pic_wakeup is asserted
//
always @(posedge clk or posedge rst)
if (rst)
{dcge, sme, dme, sdf} <= 7'b0;
else if (pmr_sel && spr_write) begin
sdf <= #1 spr_dat_i[`OR1200_PM_PMR_SDF];
dme <= #1 spr_dat_i[`OR1200_PM_PMR_DME];
sme <= #1 spr_dat_i[`OR1200_PM_PMR_SME];
dcge <= #1 spr_dat_i[`OR1200_PM_PMR_DCGE];
end
else if (pic_wakeup) begin
dme <= #1 1'b0;
sme <= #1 1'b0;
end
//
// Read PMR
//
`ifdef OR1200_PM_READREGS
assign spr_dat_o[`OR1200_PM_PMR_SDF] = sdf;
assign spr_dat_o[`OR1200_PM_PMR_DME] = dme;
assign spr_dat_o[`OR1200_PM_PMR_SME] = sme;
assign spr_dat_o[`OR1200_PM_PMR_DCGE] = dcge;
`ifdef OR1200_PM_UNUSED_ZERO
assign spr_dat_o[`OR1200_PM_PMR_UNUSED] = 25'b0;
`endif
`endif
//
// Generate pm_clksd
//
assign pm_clksd = sdf;
//
// Statically generate all clock gate outputs
// TODO: add dynamic clock gating feature
//
assign pm_cpu_gate = (dme | sme) & ~pic_wakeup;
assign pm_dc_gate = pm_cpu_gate;
assign pm_ic_gate = pm_cpu_gate;
assign pm_dmmu_gate = pm_cpu_gate;
assign pm_immu_gate = pm_cpu_gate;
assign pm_tt_gate = sme & ~pic_wakeup;
//
// Assert pm_wakeup when pic_wakeup is asserted
//
assign pm_wakeup = pic_wakeup;
//
// Assert pm_lvolt when pm_cpu_gate or pm_cpustall are asserted
//
always @(posedge clk or posedge rst)
if (rst)
pm_cpustall_reg <= 1'b0;
else
pm_cpustall_reg <= pm_cpustall;
assign pm_lvolt = pm_cpu_gate | pm_cpustall_reg;
`else
//
// When PM is not implemented, drive all outputs as would when PM is disabled
//
assign pm_clksd = 4'b0;
assign pm_cpu_gate = 1'b0;
assign pm_dc_gate = 1'b0;
assign pm_ic_gate = 1'b0;
assign pm_dmmu_gate = 1'b0;
assign pm_immu_gate = 1'b0;
assign pm_tt_gate = 1'b0;
assign pm_wakeup = 1'b1;
assign pm_lvolt = 1'b0;
//
// Read PMR
//
`ifdef OR1200_PM_READREGS
assign spr_dat_o[`OR1200_PM_PMR_SDF] = 4'b0;
assign spr_dat_o[`OR1200_PM_PMR_DME] = 1'b0;
assign spr_dat_o[`OR1200_PM_PMR_SME] = 1'b0;
assign spr_dat_o[`OR1200_PM_PMR_DCGE] = 1'b0;
`ifdef OR1200_PM_UNUSED_ZERO
assign spr_dat_o[`OR1200_PM_PMR_UNUSED] = 25'b0;
`endif
`endif
`endif
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: channel_64.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Represents a RIFFA channel. Contains a RX port and a
// TX port.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module channel_64 #(
parameter C_DATA_WIDTH = 9'd64,
parameter C_MAX_READ_REQ = 2, // Max read: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
// Local parameters
parameter C_RX_FIFO_DEPTH = 1024,
parameter C_TX_FIFO_DEPTH = 512,
parameter C_SG_FIFO_DEPTH = 1024,
parameter C_DATA_WORD_WIDTH = clog2((C_DATA_WIDTH/32)+1)
)
(
input CLK,
input RST,
input [2:0] CONFIG_MAX_READ_REQUEST_SIZE, // Maximum read payload: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
input [2:0] CONFIG_MAX_PAYLOAD_SIZE, // Maximum write payload: 000=128B, 001=256B, 010=512B, 011=1024B
input [31:0] PIO_DATA, // Single word programmed I/O data
input [C_DATA_WIDTH-1:0] ENG_DATA, // Main incoming data
output SG_RX_BUF_RECVD, // Scatter gather RX buffer completely read (ready for next if applicable)
input SG_RX_BUF_LEN_VALID, // Scatter gather RX buffer length valid
input SG_RX_BUF_ADDR_HI_VALID, // Scatter gather RX buffer high address valid
input SG_RX_BUF_ADDR_LO_VALID, // Scatter gather RX buffer low address valid
output SG_TX_BUF_RECVD, // Scatter gather TX buffer completely read (ready for next if applicable)
input SG_TX_BUF_LEN_VALID, // Scatter gather TX buffer length valid
input SG_TX_BUF_ADDR_HI_VALID, // Scatter gather TX buffer high address valid
input SG_TX_BUF_ADDR_LO_VALID, // Scatter gather TX buffer low address valid
input TXN_RX_LEN_VALID, // Read transaction length valid
input TXN_RX_OFF_LAST_VALID, // Read transaction offset/last valid
output [31:0] TXN_RX_DONE_LEN, // Read transaction actual transfer length
output TXN_RX_DONE, // Read transaction done
input TXN_RX_DONE_ACK, // Read transaction actual transfer length read
output TXN_TX, // Write transaction notification
input TXN_TX_ACK, // Write transaction acknowledged
output [31:0] TXN_TX_LEN, // Write transaction length
output [31:0] TXN_TX_OFF_LAST, // Write transaction offset/last
output [31:0] TXN_TX_DONE_LEN, // Write transaction actual transfer length
output TXN_TX_DONE, // Write transaction done
input TXN_TX_DONE_ACK, // Write transaction actual transfer length read
output RX_REQ, // Read request
input RX_REQ_ACK, // Read request accepted
output [1:0] RX_REQ_TAG, // Read request data tag
output [63:0] RX_REQ_ADDR, // Read request address
output [9:0] RX_REQ_LEN, // Read request length
output TX_REQ, // Outgoing write request
input TX_REQ_ACK, // Outgoing write request acknowledged
output [63:0] TX_ADDR, // Outgoing write high address
output [9:0] TX_LEN, // Outgoing write length (in 32 bit words)
output [C_DATA_WIDTH-1:0] TX_DATA, // Outgoing write data
input TX_DATA_REN, // Outgoing write data read enable
input TX_SENT, // Outgoing write complete
input [C_DATA_WORD_WIDTH-1:0] MAIN_DATA_EN, // Main incoming data enable
input MAIN_DONE, // Main incoming data complete
input MAIN_ERR, // Main incoming data completed with error
input [C_DATA_WORD_WIDTH-1:0] SG_RX_DATA_EN, // Scatter gather for RX incoming data enable
input SG_RX_DONE, // Scatter gather for RX incoming data complete
input SG_RX_ERR, // Scatter gather for RX incoming data completed with error
input [C_DATA_WORD_WIDTH-1:0] SG_TX_DATA_EN, // Scatter gather for TX incoming data enable
input SG_TX_DONE, // Scatter gather for TX incoming data complete
input SG_TX_ERR, // Scatter gather for TX incoming data completed with error
input CHNL_RX_CLK, // Channel read clock
output CHNL_RX, // Channel read receive signal
input CHNL_RX_ACK, // Channle read received signal
output CHNL_RX_LAST, // Channel last read
output [31:0] CHNL_RX_LEN, // Channel read length
output [30:0] CHNL_RX_OFF, // Channel read offset
output [C_DATA_WIDTH-1:0] CHNL_RX_DATA, // Channel read data
output CHNL_RX_DATA_VALID, // Channel read data valid
input CHNL_RX_DATA_REN, // Channel read data has been recieved
input CHNL_TX_CLK, // Channel write clock
input CHNL_TX, // Channel write receive signal
output CHNL_TX_ACK, // Channel write acknowledgement signal
input CHNL_TX_LAST, // Channel last write
input [31:0] CHNL_TX_LEN, // Channel write length (in 32 bit words)
input [30:0] CHNL_TX_OFF, // Channel write offset
input [C_DATA_WIDTH-1:0] CHNL_TX_DATA, // Channel write data
input CHNL_TX_DATA_VALID, // Channel write data valid
output CHNL_TX_DATA_REN // Channel write data has been recieved
);
`include "functions.vh"
wire [C_DATA_WIDTH-1:0] wTxSgData;
wire wTxSgDataEmpty;
wire wTxSgDataRen;
wire wTxSgDataErr;
wire wTxSgDataRst;
// Receiving port (data to the channel)
rx_port_64 #(
.C_DATA_WIDTH(C_DATA_WIDTH),
.C_MAIN_FIFO_DEPTH(C_RX_FIFO_DEPTH),
.C_SG_FIFO_DEPTH(C_SG_FIFO_DEPTH),
.C_MAX_READ_REQ(C_MAX_READ_REQ)
) rxPort (
.RST(RST),
.CLK(CLK),
.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE),
.SG_RX_BUF_RECVD(SG_RX_BUF_RECVD),
.SG_RX_BUF_DATA(PIO_DATA),
.SG_RX_BUF_LEN_VALID(SG_RX_BUF_LEN_VALID),
.SG_RX_BUF_ADDR_HI_VALID(SG_RX_BUF_ADDR_HI_VALID),
.SG_RX_BUF_ADDR_LO_VALID(SG_RX_BUF_ADDR_LO_VALID),
.SG_TX_BUF_RECVD(SG_TX_BUF_RECVD),
.SG_TX_BUF_DATA(PIO_DATA),
.SG_TX_BUF_LEN_VALID(SG_TX_BUF_LEN_VALID),
.SG_TX_BUF_ADDR_HI_VALID(SG_TX_BUF_ADDR_HI_VALID),
.SG_TX_BUF_ADDR_LO_VALID(SG_TX_BUF_ADDR_LO_VALID),
.SG_DATA(wTxSgData),
.SG_DATA_EMPTY(wTxSgDataEmpty),
.SG_DATA_REN(wTxSgDataRen),
.SG_RST(wTxSgDataRst),
.SG_ERR(wTxSgDataErr),
.TXN_DATA(PIO_DATA),
.TXN_LEN_VALID(TXN_RX_LEN_VALID),
.TXN_OFF_LAST_VALID(TXN_RX_OFF_LAST_VALID),
.TXN_DONE_LEN(TXN_RX_DONE_LEN),
.TXN_DONE(TXN_RX_DONE),
.TXN_DONE_ACK(TXN_RX_DONE_ACK),
.RX_REQ(RX_REQ),
.RX_REQ_ACK(RX_REQ_ACK),
.RX_REQ_TAG(RX_REQ_TAG),
.RX_REQ_ADDR(RX_REQ_ADDR),
.RX_REQ_LEN(RX_REQ_LEN),
.MAIN_DATA(ENG_DATA),
.MAIN_DATA_EN(MAIN_DATA_EN),
.MAIN_DONE(MAIN_DONE),
.MAIN_ERR(MAIN_ERR),
.SG_RX_DATA(ENG_DATA),
.SG_RX_DATA_EN(SG_RX_DATA_EN),
.SG_RX_DONE(SG_RX_DONE),
.SG_RX_ERR(SG_RX_ERR),
.SG_TX_DATA(ENG_DATA),
.SG_TX_DATA_EN(SG_TX_DATA_EN),
.SG_TX_DONE(SG_TX_DONE),
.SG_TX_ERR(SG_TX_ERR),
.CHNL_CLK(CHNL_RX_CLK),
.CHNL_RX(CHNL_RX),
.CHNL_RX_ACK(CHNL_RX_ACK),
.CHNL_RX_LAST(CHNL_RX_LAST),
.CHNL_RX_LEN(CHNL_RX_LEN),
.CHNL_RX_OFF(CHNL_RX_OFF),
.CHNL_RX_DATA(CHNL_RX_DATA),
.CHNL_RX_DATA_VALID(CHNL_RX_DATA_VALID),
.CHNL_RX_DATA_REN(CHNL_RX_DATA_REN)
);
// Sending port (data from the channel)
tx_port_64 #(
.C_DATA_WIDTH(C_DATA_WIDTH),
.C_FIFO_DEPTH(C_TX_FIFO_DEPTH)
) txPort (
.CLK(CLK),
.RST(RST),
.CONFIG_MAX_PAYLOAD_SIZE(CONFIG_MAX_PAYLOAD_SIZE),
.TXN(TXN_TX),
.TXN_ACK(TXN_TX_ACK),
.TXN_LEN(TXN_TX_LEN),
.TXN_OFF_LAST(TXN_TX_OFF_LAST),
.TXN_DONE_LEN(TXN_TX_DONE_LEN),
.TXN_DONE(TXN_TX_DONE),
.TXN_DONE_ACK(TXN_TX_DONE_ACK),
.SG_DATA(wTxSgData),
.SG_DATA_EMPTY(wTxSgDataEmpty),
.SG_DATA_REN(wTxSgDataRen),
.SG_RST(wTxSgDataRst),
.SG_ERR(wTxSgDataErr),
.TX_REQ(TX_REQ),
.TX_REQ_ACK(TX_REQ_ACK),
.TX_ADDR(TX_ADDR),
.TX_LEN(TX_LEN),
.TX_DATA(TX_DATA),
.TX_DATA_REN(TX_DATA_REN),
.TX_SENT(TX_SENT),
.CHNL_CLK(CHNL_TX_CLK),
.CHNL_TX(CHNL_TX),
.CHNL_TX_ACK(CHNL_TX_ACK),
.CHNL_TX_LAST(CHNL_TX_LAST),
.CHNL_TX_LEN(CHNL_TX_LEN),
.CHNL_TX_OFF(CHNL_TX_OFF),
.CHNL_TX_DATA(CHNL_TX_DATA),
.CHNL_TX_DATA_VALID(CHNL_TX_DATA_VALID),
.CHNL_TX_DATA_REN(CHNL_TX_DATA_REN)
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:32:42 03/12/2013
// Design Name:
// Module Name: butterfly_unit_radix4
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module butterfly_unit_radix4(
input clk,
input[15:0] cos0,
input[15:0] sin0,
input[15:0] cos1,
input[15:0] sin1,
input[15:0] cos2,
input[15:0] sin2,
input[15:0] x1_re,
input[15:0] x1_im,
input[15:0] x2_re,
input[15:0] x2_im,
input[15:0] x3_re,
input[15:0] x3_im,
input[15:0] x4_re,
input[15:0] x4_im,
output[15:0] p1_re,
output[15:0] p1_im,
output[15:0] p2_re,
output[15:0] p2_im,
output[15:0] p3_re,
output[15:0] p3_im,
output[15:0] p4_re,
output[15:0] p4_im
);
/**³Ë·¨Êä³ö**/
wire[15:0] X2_re;
wire[15:0] X2_im;
wire[15:0] X3_re;
wire[15:0] X3_im;
wire[15:0] X4_re;
wire[15:0] X4_im;
/**end**/
reg[15:0] X1_re_reg0 = 16'd0;
reg[15:0] X1_re_reg1 = 16'd0;
reg[15:0] X1_re_reg2 = 16'd0;
reg[15:0] X1_re_reg3 = 16'd0;
reg[15:0] X1_re_reg4 = 16'd0;
reg[15:0] X1_re_reg5 = 16'd0;
reg[15:0] X1_im_reg0 = 16'd0;
reg[15:0] X1_im_reg1 = 16'd0;
reg[15:0] X1_im_reg2 = 16'd0;
reg[15:0] X1_im_reg3 = 16'd0;
reg[15:0] X1_im_reg4 = 16'd0;
reg[15:0] X1_im_reg5 = 16'd0;
always @(posedge clk)
begin
X1_re_reg0 <= x1_re;
X1_im_reg0 <= x1_im;
X1_re_reg1 <= X1_re_reg0;
X1_im_reg1 <= X1_im_reg0;
X1_re_reg2 <= X1_re_reg1;
X1_im_reg2 <= X1_im_reg1;
X1_re_reg3 <= X1_re_reg2;
X1_im_reg3 <= X1_im_reg2;
X1_re_reg4 <= X1_re_reg3;
X1_im_reg4 <= X1_im_reg3;
X1_re_reg5 <= X1_re_reg4;
X1_im_reg5 <= X1_im_reg4;
end
complex_mul inst0_complex_mul(
.clk(clk),
.ar(cos0),
.ai(sin0),
.br(x2_re),
.bi(x2_im),
.pr(X2_re),
.pi(X2_im)
);
complex_mul inst1_complex_mul(
.clk(clk),
.ar(cos1),
.ai(sin1),
.br(x3_re),
.bi(x3_im),
.pr(X3_re),
.pi(X3_im)
);
complex_mul inst2_complex_mul(
.clk(clk),
.ar(cos2),
.ai(sin2),
.br(x4_re),
.bi(x4_im),
.pr(X4_re),
.pi(X4_im)
);
complex_add_radix_4 inst_complex_add_radix_4(
.clk(clk),
.x1_re(X1_re_reg5),
.x1_im(X1_im_reg5),
.x2_re(X2_re),
.x2_im(X2_im),
.x3_re(X3_re),
.x3_im(X3_im),
.x4_re(X4_re),
.x4_im(X4_im),
.re_0(p1_re),
.im_0(p1_im),
.re_1(p2_re),
.im_1(p2_im),
.re_2(p3_re),
.im_2(p3_im),
.re_3(p4_re),
.im_3(p4_im)
);
endmodule
|
//-----------------------------------------------------------------
// AltOR32
// Alternative Lightweight OpenRisc
// V2.1
// Ultra-Embedded.com
// Copyright 2011 - 2014
//
// Email: [email protected]
//
// License: LGPL
//-----------------------------------------------------------------
//
// Copyright (C) 2011 - 2014 Ultra-Embedded.com
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, write to the
// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
// Boston, MA 02111-1307 USA
//-----------------------------------------------------------------
//-----------------------------------------------------------------
// Includes
//-----------------------------------------------------------------
`include "altor32_defs.v"
//-----------------------------------------------------------------
// Module - Altera LPM register file
//-----------------------------------------------------------------
module altor32_regfile_alt
(
input clk_i /*verilator public*/,
input rst_i /*verilator public*/,
input wr_i /*verilator public*/,
input [4:0] ra_i /*verilator public*/,
input [4:0] rb_i /*verilator public*/,
input [4:0] rd_i /*verilator public*/,
output reg [31:0] reg_ra_o /*verilator public*/,
output reg [31:0] reg_rb_o /*verilator public*/,
input [31:0] reg_rd_i /*verilator public*/
);
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
parameter SUPPORT_32REGS = "ENABLED";
//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
wire clk_delayed_w;
wire [31:0] reg_ra_w;
wire [31:0] reg_rb_w;
wire write_enable_w;
reg [4:0] addr_q;
reg [31:0] data_q;
wire [31:0] ra_w;
wire [31:0] rb_w;
//-----------------------------------------------------------------
// Sync addr & data
//-----------------------------------------------------------------
always @ (posedge clk_i or posedge rst_i)
begin
if (rst_i)
begin
addr_q <= 5'b00000;
data_q <= 32'h00000000;
end
else
begin
addr_q <= rd_i;
data_q <= reg_rd_i;
end
end
//-----------------------------------------------------------------
// Register File (using lpm_ram_dp)
// Unfortunatly, LPM_RAM_DP primitives have synchronous read ports.
// As this core requires asynchronous/non-registered read ports,
// we have to invert the readclock edge to get close to what we
// require.
// This will have negative timing implications!
//-----------------------------------------------------------------
lpm_ram_dp
#(
.lpm_width(32),
.lpm_widthad(5),
.lpm_indata("REGISTERED"),
.lpm_outdata("UNREGISTERED"),
.lpm_rdaddress_control("REGISTERED"),
.lpm_wraddress_control("REGISTERED"),
.lpm_file("UNUSED"),
.lpm_type("lpm_ram_dp"),
.lpm_hint("UNUSED")
)
lpm1
(
.rdclock(clk_delayed_w),
.rdclken(1'b1),
.rdaddress(ra_i),
.rden(1'b1),
.data(reg_rd_i),
.wraddress(rd_i),
.wren(write_enable_w),
.wrclock(clk_i),
.wrclken(1'b1),
.q(ra_w)
);
lpm_ram_dp
#(
.lpm_width(32),
.lpm_widthad(5),
.lpm_indata("REGISTERED"),
.lpm_outdata("UNREGISTERED"),
.lpm_rdaddress_control("REGISTERED"),
.lpm_wraddress_control("REGISTERED"),
.lpm_file("UNUSED"),
.lpm_type("lpm_ram_dp"),
.lpm_hint("UNUSED")
)
lpm2
(
.rdclock(clk_delayed_w),
.rdclken(1'b1),
.rdaddress(rb_i),
.rden(1'b1),
.data(reg_rd_i),
.wraddress(rd_i),
.wren(write_enable_w),
.wrclock(clk_i),
.wrclken(1'b1),
.q(rb_w)
);
//-----------------------------------------------------------------
// Combinatorial Assignments
//-----------------------------------------------------------------
// Delayed clock
assign clk_delayed_w = !clk_i;
// Register read ports
always @ *
begin
if (ra_i == 5'b00000)
reg_ra_o = 32'h00000000;
else
reg_ra_o = reg_ra_w;
if (rb_i == 5'b00000)
reg_rb_o = 32'h00000000;
else
reg_rb_o = reg_rb_w;
end
assign write_enable_w = (rd_i != 5'b00000) & wr_i;
// Reads are bypassed during write-back
assign reg_ra_w = (ra_i != addr_q) ? ra_w : data_q;
assign reg_rb_w = (rb_i != addr_q) ? rb_w : data_q;
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_clk_cl_iobdg_cmp.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Module Name: iobdg clock macro
// Description: Clock macro that encapsulates the cluster header.
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
`include "iop.h"
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
module bw_clk_cl_iobdg_cmp (/*AUTOARG*/
// Outputs
so, rclk, dbginit_l, cluster_grst_l,
// Inputs
si, se, grst_l, gdbginit_l, gclk, cluster_cken, arst_l,
adbginit_l
);
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input adbginit_l; // To cluster_header of cluster_header.v
input arst_l; // To cluster_header of cluster_header.v
input cluster_cken; // To cluster_header of cluster_header.v
input gclk; // To cluster_header of cluster_header.v
input gdbginit_l; // To cluster_header of cluster_header.v
input grst_l; // To cluster_header of cluster_header.v
input se; // To cluster_header of cluster_header.v
input si; // To cluster_header of cluster_header.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output cluster_grst_l; // From cluster_header of cluster_header.v
output dbginit_l; // From cluster_header of cluster_header.v
output rclk; // From cluster_header of cluster_header.v
output so; // From cluster_header of cluster_header.v
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
// End of automatics
////////////////////////////////////////////////////////////////////////
// Code start here
////////////////////////////////////////////////////////////////////////
cluster_header cluster_header (/*AUTOINST*/
// Outputs
.dbginit_l(dbginit_l),
.cluster_grst_l(cluster_grst_l),
.rclk (rclk),
.so (so),
// Inputs
.gclk (gclk),
.cluster_cken(cluster_cken),
.arst_l(arst_l),
.grst_l(grst_l),
.adbginit_l(adbginit_l),
.gdbginit_l(gdbginit_l),
.si (si),
.se (se));
endmodule // bw_clk_cl_iobdg_cmp
// Local Variables:
// verilog-library-directories:("." "../../common/rtl")
// End:
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFRTP_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__DFRTP_FUNCTIONAL_V
/**
* dfrtp: Delay flop, inverted reset, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_pr/sky130_fd_sc_hvl__udp_dff_pr.v"
`celldefine
module sky130_fd_sc_hvl__dfrtp (
Q ,
CLK ,
D ,
RESET_B
);
// Module ports
output Q ;
input CLK ;
input D ;
input RESET_B;
// Local signals
wire buf_Q;
wire RESET;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_hvl__udp_dff$PR `UNIT_DELAY dff0 (buf_Q , D, CLK, RESET );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFRTP_FUNCTIONAL_V |
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//
// Top level module for in-order coalesced memory access.
//
// Properties - Coalesced: Yes, Ordered: Yes, Hazard-Safe: Yes, Pipelined: Yes
// (see lsu_top.v for details)
//
// Description: Requests are submitted as soon as possible to memory, stalled
// requests are coalesced with neighbouring requests if they
// access the same page of memory.
// Basic coalesced read unit:
// Accept read requests on the upstream interface. Requests are sent to
// the avalon bus as soon as they are recieved. If the avalon bus is
// stalling, requests to the same global-memory word are coalesced into
// a single request to improve efficiency.
//
// The request FIFO stores the byte-address to select the appropriate word
// out of the response data as well as an extra bit to indicate if the
// request is coalesced with the previous request or if a new request was
// made. The output port looks ahead to the next pending request to
// determine whether the current response data can be thrown away or
// must be kept to service the next coalesced request.
module lsu_basic_coalesced_read
(
clk, reset, o_stall, i_valid, i_address, i_stall, o_valid, o_readdata,
o_active, //Debugging signal
avm_address, avm_read, avm_readdata, avm_waitrequest, avm_byteenable,
avm_readdatavalid
);
/*************
* Parameters *
*************/
parameter AWIDTH=32; // Address width (32-bits for Avalon)
parameter WIDTH_BYTES=4; // Width of the memory access (bytes)
parameter MWIDTH_BYTES=32; // Width of the global memory bus (bytes)
parameter ALIGNMENT_ABITS=2; // Request address alignment (address bits)
parameter KERNEL_SIDE_MEM_LATENCY=32; // Determines the max number of live requests.
// Derived parameters
localparam WIDTH=8*WIDTH_BYTES;
localparam MWIDTH=8*MWIDTH_BYTES;
localparam BYTE_SELECT_BITS=$clog2(MWIDTH_BYTES);
localparam SEGMENT_SELECT_BITS=BYTE_SELECT_BITS-ALIGNMENT_ABITS;
localparam PAGE_SELECT_BITS=AWIDTH-BYTE_SELECT_BITS;
// Constants
localparam REQUEST_FIFO_DEPTH=2*KERNEL_SIDE_MEM_LATENCY;
/********
* Ports *
********/
// Standard global signals
input clk;
input reset;
// Upstream interface
output o_stall;
input i_valid;
input [AWIDTH-1:0] i_address;
// Downstream interface
input i_stall;
output o_valid;
output [WIDTH-1:0] o_readdata;
output o_active;
// Avalon interface
output [AWIDTH-1:0] avm_address;
output avm_read;
input [MWIDTH-1:0] avm_readdata;
input avm_waitrequest;
output [MWIDTH_BYTES-1:0] avm_byteenable;
input avm_readdatavalid;
/***************
* Architecture *
***************/
wire [PAGE_SELECT_BITS-1:0] page_addr;
wire [SEGMENT_SELECT_BITS:0] rf_data_in;
wire [BYTE_SELECT_BITS-1:0] byte_addr;
wire next_new_page;
wire c_stall;
wire c_new_page;
wire [PAGE_SELECT_BITS-1:0] c_req_addr;
wire c_req_valid;
wire rf_full;
wire rf_valid;
wire [SEGMENT_SELECT_BITS:0] rf_data;
wire rf_next_valid;
wire [SEGMENT_SELECT_BITS:0] rf_next_data;
wire rf_stall_in;
wire rm_stall;
wire rm_valid;
wire rm_active;
wire [MWIDTH-1:0] rm_data;
wire rm_stall_in;
// Coalescer - Groups subsequent requests together if they are compatible and
// the avalon bus is stalled.
assign page_addr = i_address[AWIDTH-1:BYTE_SELECT_BITS];
basic_coalescer #(
.PAGE_ADDR_WIDTH(PAGE_SELECT_BITS),
.TIMEOUT(MWIDTH/WIDTH)
) coalescer (
.clk(clk),
.reset(reset),
.i_page_addr(page_addr),
.i_valid(i_valid && !rf_full),
.o_stall(c_stall),
.o_new_page(c_new_page),
.o_req_addr(c_req_addr),
.o_req_valid(c_req_valid),
.i_stall(rm_stall)
);
// Response FIFO - Buffers the requests so they can be extracted from the
// wider memory bus. Stores the segment address to extract the requested
// word from the response data, and a bit indicating if the request comes
// from a new page.
generate if(SEGMENT_SELECT_BITS > 0)
begin
wire [SEGMENT_SELECT_BITS-1:0] segment_addr;
assign segment_addr = i_address[BYTE_SELECT_BITS-1:ALIGNMENT_ABITS];
assign rf_data_in = {c_new_page, segment_addr};
assign byte_addr = (rf_data[SEGMENT_SELECT_BITS-1:0] << ALIGNMENT_ABITS);
end
else
begin
assign rf_data_in = c_new_page;
assign byte_addr = {BYTE_SELECT_BITS{1'b0}};
end
endgenerate
lookahead_fifo #(
.WIDTH( SEGMENT_SELECT_BITS + 1 ),
.DEPTH( REQUEST_FIFO_DEPTH )
) request_fifo (
.clk(clk),
.reset(reset),
.i_data( rf_data_in ),
.i_valid( i_valid && !c_stall ),
.o_full(rf_full),
.i_stall(rf_stall_in),
.o_valid(rf_valid),
.o_data(rf_data),
.o_next_valid(rf_next_valid),
.o_next_data(rf_next_data)
);
// Read master - Handles pipelined read transactions through MM-Avalon.
lsu_pipelined_read #(
.AWIDTH( AWIDTH ),
.WIDTH_BYTES( MWIDTH_BYTES ),
.MWIDTH_BYTES( MWIDTH_BYTES ),
.ALIGNMENT_ABITS( BYTE_SELECT_BITS ),
.KERNEL_SIDE_MEM_LATENCY( KERNEL_SIDE_MEM_LATENCY ),
.USEOUTPUTFIFO(1),
.USEINPUTFIFO( 1 ), // Add the latency adjusting input fifos
.PIPELINE_INPUT( 1 ) // Let's add a pipline input to the input side just to help with Fmax
) read_master (
.clk(clk),
.reset(reset),
.o_stall(rm_stall),
.i_valid(c_req_valid),
.i_address({c_req_addr, {BYTE_SELECT_BITS{1'b0}}}),
.i_stall(rm_stall_in),
.o_valid(rm_valid),
.o_active(rm_active),
.o_readdata(rm_data),
.avm_address(avm_address),
.avm_read(avm_read),
.avm_readdata(avm_readdata),
.avm_waitrequest(avm_waitrequest),
.avm_byteenable(avm_byteenable),
.avm_readdatavalid(avm_readdatavalid)
);
// Control logic
// Highest bit of rf_next_data indicates whether this is a new avalon request
// (new page) or was coalesced into the previous request.
assign next_new_page = rf_next_data[SEGMENT_SELECT_BITS];
assign rm_stall_in = (!next_new_page && rf_next_valid) || rf_stall_in;
assign rf_stall_in = i_stall || !rm_valid;
// Output MUX
assign o_readdata = rm_data[8*byte_addr +: WIDTH];
// External control signals
assign o_stall = c_stall || rf_full;
assign o_valid = rm_valid && rf_valid;
assign o_active=rf_valid | rm_active;
endmodule
/******************************************************************************/
// Basic coalesced write unit:
// Accept write requests on the upstream interface. The avalon spec does
// not allow a request to change while it is being stalled, so the current
// request is registered in an output register stage and not modified.
// Subsequent requests are coalesced together as long as the output register
// stage is occupied (i.e. the avalon bus is stalling).
//
// TODO: The byte enable format is not actually compliant with the
// Avalon spec. Essentially we should not enable non-adjacent words in a write
// request. This is OK for the DDR Memory Controller as it accepts our
// non-compliant format. This needs to be investigated further.
module lsu_basic_coalesced_write
(
clk, reset, o_stall, i_valid, i_address, i_writedata, i_stall, o_valid, i_byteenable,
o_active, //Debugging signal
avm_address, avm_write, avm_writeack, avm_writedata, avm_byteenable, avm_waitrequest
);
/*************
* Parameters *
*************/
parameter AWIDTH=32; // Address width (32-bits for Avalon)
parameter WIDTH_BYTES=4; // Width of the memory access (bytes)
parameter MWIDTH_BYTES=32; // Width of the global memory bus (bytes)
parameter ALIGNMENT_ABITS=2; // Request address alignment (address bits)
parameter KERNEL_SIDE_MEM_LATENCY=32; // Memory latency in cycles
parameter USE_BYTE_EN;
// Derived parameters
localparam WIDTH=8*WIDTH_BYTES;
localparam MWIDTH=8*MWIDTH_BYTES;
localparam BYTE_SELECT_BITS=$clog2(MWIDTH_BYTES);
localparam SEGMENT_SELECT_BITS=BYTE_SELECT_BITS-ALIGNMENT_ABITS;
localparam PAGE_SELECT_BITS=AWIDTH-BYTE_SELECT_BITS;
localparam NUM_SEGMENTS=2**SEGMENT_SELECT_BITS;
localparam SEGMENT_WIDTH=8*(2**ALIGNMENT_ABITS);
localparam SEGMENT_WIDTH_BYTES=(2**ALIGNMENT_ABITS);
// Constants
localparam COUNTER_WIDTH=8; // Determines the max writes 'in-flight'
/********
* Ports *
********/
// Standard global signals
input clk;
input reset;
// Upstream interface
output o_stall;
input i_valid;
input [AWIDTH-1:0] i_address;
input [WIDTH-1:0] i_writedata;
// Downstream interface
input i_stall;
output o_valid;
output o_active;
// Avalon interface
output [AWIDTH-1:0] avm_address;
output avm_write;
input avm_writeack;
output [MWIDTH-1:0] avm_writedata;
output [MWIDTH_BYTES-1:0] avm_byteenable;
input avm_waitrequest;
input [WIDTH_BYTES-1:0] i_byteenable;
/***************
* Architecture *
***************/
wire input_accepted;
wire output_acknowledged;
wire write_accepted;
wire [PAGE_SELECT_BITS-1:0] page_addr;
wire c_new_page;
wire [PAGE_SELECT_BITS-1:0] c_req_addr;
wire c_req_valid;
wire c_stall;
reg [COUNTER_WIDTH-1:0] occ_counter;
reg [COUNTER_WIDTH-1:0] ack_counter;
reg [COUNTER_WIDTH-1:0] next_counter;
reg [COUNTER_WIDTH-1:0] or_next_counter;
wire [COUNTER_WIDTH-1:0] rf_count;
wire rf_read;
wire rf_empty;
wire rf_full;
reg [MWIDTH-1:0] wm_writedata;
reg [MWIDTH_BYTES-1:0] wm_byteenable;
reg [MWIDTH-1:0] wm_wide_wdata;
reg [MWIDTH_BYTES-1:0] wm_wide_be;
reg [MWIDTH-1:0] wm_wide_bite;
wire or_ready;
reg or_write;
reg [AWIDTH-1:0] or_address;
reg [MWIDTH-1:0] or_writedata;
reg [MWIDTH_BYTES-1:0] or_byteenable;
wire oc_full;
// Output register stage to store the next request
assign or_ready = !or_write || !avm_waitrequest;
always@(posedge clk or posedge reset)
begin
if(reset)
begin
or_write <= 1'b0;
or_address <= {AWIDTH{1'b0}};
or_writedata <= {MWIDTH{1'b0}};
or_byteenable <= {MWIDTH_BYTES{1'b0}};
or_next_counter <= {COUNTER_WIDTH{1'b0}};
end
else
begin
if(or_ready)
begin
or_write <= c_req_valid;
or_address <= (c_req_addr << BYTE_SELECT_BITS);
or_writedata <= wm_writedata;
or_byteenable <= wm_byteenable;
or_next_counter <= next_counter;
end
end
end
assign avm_address = or_address;
assign avm_write = or_write;
assign avm_writedata = or_writedata;
assign avm_byteenable = or_byteenable;
// The address components
assign page_addr = i_address[AWIDTH-1:BYTE_SELECT_BITS];
// Coalescer - Groups subsequent requests together if they are compatible
// and the output register stage is stalled
basic_coalescer #(
.PAGE_ADDR_WIDTH(PAGE_SELECT_BITS),
.TIMEOUT(MWIDTH/WIDTH)
) coalescer (
.clk(clk),
.reset(reset),
.i_page_addr(page_addr),
.i_valid(i_valid && !oc_full),
.o_stall(c_stall),
.o_new_page(c_new_page),
.o_req_addr(c_req_addr),
.o_req_valid(c_req_valid),
.i_stall(!or_ready)
);
// Writedata MUX
generate if( SEGMENT_SELECT_BITS > 0 )
begin
wire [SEGMENT_SELECT_BITS-1:0] segment_select;
assign segment_select = i_address[BYTE_SELECT_BITS-1:ALIGNMENT_ABITS];
always@(*)
begin
wm_wide_wdata = {MWIDTH{1'bx}};
wm_wide_wdata[segment_select*SEGMENT_WIDTH +: WIDTH] = i_writedata;
wm_wide_be = {MWIDTH_BYTES{1'b0}};
wm_wide_be[segment_select*SEGMENT_WIDTH_BYTES +: WIDTH_BYTES] = USE_BYTE_EN ? i_byteenable : {WIDTH_BYTES{1'b1}};
wm_wide_bite = {MWIDTH{1'b0}};
wm_wide_bite[segment_select*SEGMENT_WIDTH +: WIDTH] = {WIDTH{1'b1}};
end
end
else
begin
always@(*)
begin
wm_wide_wdata = {MWIDTH{1'bx}};
wm_wide_wdata[0 +: WIDTH] = i_writedata;
wm_wide_be = {MWIDTH_BYTES{1'b0}};
wm_wide_be[0 +: WIDTH_BYTES] = USE_BYTE_EN ? i_byteenable : {WIDTH_BYTES{1'b1}} ;
wm_wide_bite = {MWIDTH{1'b0}};
wm_wide_bite[0 +: WIDTH] = {WIDTH{1'b1}};
end
end
endgenerate
// Track the current write burst data - coalesce writes together until the
// output registers are ready for a new request.
always@(posedge clk or posedge reset)
begin
if(reset)
begin
wm_writedata <= {MWIDTH{1'b0}};
wm_byteenable <= {MWIDTH_BYTES{1'b0}};
end
else
begin
if(c_new_page)
begin
wm_writedata <= wm_wide_wdata;
wm_byteenable <= wm_wide_be;
end
else if(input_accepted)
begin
wm_writedata <= (wm_wide_wdata & wm_wide_bite) | (wm_writedata & ~wm_wide_bite);
wm_byteenable <= wm_wide_be | wm_byteenable;
end
end
end
// Write size tracker - track the number of threads represented by each pending write request
acl_ll_fifo #(
.WIDTH(COUNTER_WIDTH),
.DEPTH(KERNEL_SIDE_MEM_LATENCY+1)
) req_fifo (
.clk(clk),
.reset(reset),
.data_in( or_next_counter ),
.data_out( rf_count ),
.write( write_accepted && (!rf_empty || !avm_writeack) ),
.read( rf_read ),
.empty( rf_empty ),
.full( rf_full )
);
assign rf_read = avm_writeack && !rf_empty;
// Occupancy counter - track the number of successfully transmitted writes
// and the number of writes pending in the next request.
// occ_counter - the total occupancy (in threads) of the unit
// next_counter - the number of threads coalesced into the next transfer
// ack_counter - the number of pending threads with write completion acknowledged
assign input_accepted = i_valid && !o_stall;
assign write_accepted = avm_write && !avm_waitrequest;
assign output_acknowledged = o_valid && !i_stall;
always@(posedge clk or posedge reset)
begin
if(reset == 1'b1)
begin
occ_counter <= {COUNTER_WIDTH{1'b0}};
ack_counter <= {COUNTER_WIDTH{1'b0}};
next_counter <= {COUNTER_WIDTH{1'b0}};
end
else
begin
occ_counter <= occ_counter + input_accepted - output_acknowledged;
next_counter <= input_accepted + ((c_req_valid & or_ready) ? {COUNTER_WIDTH{1'b0}} : next_counter);
ack_counter <= ack_counter + ({COUNTER_WIDTH{avm_writeack}} & ( rf_empty ? or_next_counter : rf_count )) - output_acknowledged;
end
end
assign oc_full = (occ_counter == {COUNTER_WIDTH{1'b1}});
// Pipeline control signals
assign o_stall = oc_full || c_stall || rf_full;
assign o_valid = (ack_counter > {COUNTER_WIDTH{1'b0}});
assign o_active = (occ_counter != {COUNTER_WIDTH{1'b0}});
endmodule
/******************************************************************************/
/* RESPONSE FIFO */
// lookahead_fifo - A simple sc_fifo instantiation with an additional
// shift-register stage at the end to provide access to the next two data
// items.
module lookahead_fifo
(
clk, reset, i_data, i_valid, o_full, i_stall, o_valid, o_data,
o_next_valid, o_next_data
);
parameter WIDTH=32;
parameter DEPTH=32;
input clk;
input reset;
input [WIDTH-1:0] i_data;
input i_valid;
output o_full;
input i_stall;
output reg o_valid;
output reg [WIDTH-1:0] o_data;
output o_next_valid;
output [WIDTH-1:0] o_next_data;
wire sr_ready;
// Fifo
acl_data_fifo #(
.DATA_WIDTH(WIDTH),
.DEPTH(DEPTH),
.IMPL("ram_plus_reg")
) req_fifo (
.clock(clk),
.resetn(!reset),
.data_in( i_data ),
.data_out( o_next_data ),
.valid_in( i_valid ),
.valid_out( o_next_valid ),
.stall_in( !sr_ready ),
.stall_out( o_full )
);
// Shift-reg
assign sr_ready = !o_valid || !i_stall;
always@(posedge clk or posedge reset)
begin
if(reset)
begin
o_data <= {WIDTH{1'b0}};
o_valid <= 1'b0;
end
else
begin
o_valid <= sr_ready ? o_next_valid : o_valid;
o_data <= sr_ready ? o_next_data : o_data;
end
end
endmodule
/* BASIC COALESCING MODULE */
// basic_coalescer - Accept new inputs as long as the unit is not stalled,
// or the new request can be coalesced with the pending (stalled) request.
module basic_coalescer
(
clk, reset, i_page_addr, i_valid, o_stall, o_new_page, o_req_addr,
o_req_valid, i_stall
);
parameter PAGE_ADDR_WIDTH=32;
parameter TIMEOUT=8; // power of 2
input clk;
input reset;
input [PAGE_ADDR_WIDTH-1:0] i_page_addr;
input i_valid;
output o_stall;
output o_new_page;
output [PAGE_ADDR_WIDTH-1:0] o_req_addr;
output o_req_valid;
input i_stall;
reg [PAGE_ADDR_WIDTH-1:0] page_addr;
reg valid;
wire ready;
wire waiting;
wire match;
wire timeout;
reg [$clog2(TIMEOUT):0] timeout_counter;
assign timeout = timeout_counter[$clog2(TIMEOUT)];
// Internal signal logic
assign match = (i_page_addr == page_addr);
assign ready = !valid || !(i_stall || waiting);
assign waiting = !timeout && (!i_valid || match);
always@(posedge clk or posedge reset)
begin
if(reset)
begin
page_addr <= {PAGE_ADDR_WIDTH{1'b0}};
valid <= 1'b0;
timeout_counter <= '0;
end
else
begin
page_addr <= ready ? i_page_addr : page_addr;
valid <= ready ? i_valid : valid;
if( i_valid )
timeout_counter <= 'd1;
else if( valid && !timeout )
timeout_counter <= timeout_counter + 'd1;
end
end
// Outputs
assign o_stall = i_valid && !match && !ready;
assign o_new_page = ready;
assign o_req_addr = page_addr;
assign o_req_valid = valid && !waiting;
endmodule
|
/*
* Copyright (c) 2014 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
*/
`default_nettype none
module main;
class test_t;
reg [1:0] a;
reg [2:0] b;
function new (int ax, int bx);
begin
a = ax;
b = bx;
end
endfunction // new
endclass // test_t
test_t foo [0:3][0:7], tmp;
bit [3:0] idx1, idx2;
initial begin
for (idx1 = 0 ; idx1 < 4 ; idx1 = idx1+1) begin
for (idx2 = 0 ; idx2 <= 7 ; idx2 = idx2+1)
foo[idx1][idx2] = new(idx1,idx2);
end
foreach (foo[ia,ib]) begin
if (ia > 3 || ib > 7) begin
$display("FAILED -- index out of range: ia=%0d, ib=%0d", ia, ib);
$finish;
end
tmp = foo[ia][ib];
if (tmp.a !== ia[1:0] || tmp.b !== ib[2:0]) begin
$display("FAILED -- foo[%0d][%0d] == %b", ia, ib, {tmp.a, tmp.b});
$finish;
end
foo[ia][ib] = null;
end
for (idx1 = 0 ; idx1 < 4 ; idx1 = idx1+1) begin
for (idx2 = 0 ; idx2 <= 7 ; idx2 = idx2+1)
if (foo[idx1][idx2] != null) begin
$display("FAILED -- foreach failed to visit foo[%0d][%0d]", idx1,idx2);
$finish;
end
end
$display("PASSED");
end
endmodule // main
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t;
real n0; initial n0 = 0.0;
real n1; initial n1 = 1.0;
real n2; initial n2 = 0.1;
real n3; initial n3 = 1.2345e-15;
real n4; initial n4 = 2.579e+15;
reg [7:0] r8; initial r8 = 3;
initial begin
// Display formatting
$display("[%0t] e=%e e1=%1e e30=%3.0e e32=%3.2e", $time, n0,n0,n0,n0);
$display("[%0t] f=%f f1=%1e f30=%3.0e f32=%3.2e", $time, n0,n0,n0,n0);
$display("[%0t] g=%g g1=%1e g30=%3.0e g32=%3.2e", $time, n0,n0,n0,n0);
$display;
$display("[%0t] e=%e e1=%1e e30=%3.0e e32=%3.2e", $time, n1,n1,n1,n1);
$display("[%0t] f=%f f1=%1e f30=%3.0e f32=%3.2e", $time, n1,n1,n1,n1);
$display("[%0t] g=%g g1=%1e g30=%3.0e g32=%3.2e", $time, n1,n1,n1,n1);
$display;
$display("[%0t] e=%e e1=%1e e30=%3.0e e32=%3.2e", $time, n2,n2,n2,n2);
$display("[%0t] f=%f f1=%1e f30=%3.0e f32=%3.2e", $time, n2,n2,n2,n2);
$display("[%0t] g=%g g1=%1e g30=%3.0e g32=%3.2e", $time, n2,n2,n2,n2);
$display;
$display("[%0t] e=%e e1=%1e e30=%3.0e e32=%3.2e", $time, n3,n3,n3,n3);
$display("[%0t] f=%f f1=%1e f30=%3.0e f32=%3.2e", $time, n3,n3,n3,n3);
$display("[%0t] g=%g g1=%1e g30=%3.0e g32=%3.2e", $time, n3,n3,n3,n3);
$display;
$display("[%0t] e=%e e1=%1e e30=%3.0e e32=%3.2e", $time, n4,n4,n4,n4);
$display("[%0t] f=%f f1=%1e f30=%3.0e f32=%3.2e", $time, n4,n4,n4,n4);
$display("[%0t] g=%g g1=%1e g30=%3.0e g32=%3.2e", $time, n4,n4,n4,n4);
$display;
$display("r8=%d n1=%g n2=%g", r8, n1, n2);
$display("n1=%g n2=%g r8=%d", n1, n2, r8);
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
`include "../source/rcpu.v"
`include "../source/RAM2.v"
`timescale 1 us / 1 us
module testRCPU;
reg clk;
reg rst;
wire[31:0] addr;
wire[15:0] read;
wire[15:0] write;
wire we;
wire re;
wire ready;
RAM2 ram(
.clk (clk),
.rst (rst),
.addr (addr[15:0]),
.rdata (read),
.wdata (write),
.we (we),
.re (re),
.ready (ready)
);
rcpu cpu(
.clk (!clk),
.rst (rst),
.memAddr (addr),
.memRead (read),
.memWrite (write),
.memWE (we),
.memRE (re),
.memReady (ready)
);
integer i;
integer clocks = 0;
integer stalled = 0;
initial begin
$dumpfile ("../test.vcd");
$dumpvars (0);
$dumpvars (1, ram.memory[0]);
$dumpvars (1, ram.memory[1]);
for (i = 16'hD000; i>16'hCFE0; i = i - 1)
$dumpvars (1, ram.memory[i]);
end
always #5 clk = !clk;
always @ (posedge clk) begin
clocks <= clocks + 1;
if (cpu.stall)
stalled <= stalled + 1;
end
initial begin
clk = 0;
rst = 1;
#1 rst = 0; $readmemb("../fact.rcpu", ram.memory); #9
#10000 $finish;
end
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate casez/endcase w/ default
module main ();
reg error;
reg [2:0] val1,val2;
reg [2:0] result ;
always @( val1 )
casez (val1)
5'b0000z: result = 0;
5'b001z0: result = 1 ;
5'b01zz0: result = 2;
default: result = 4;
endcase
initial
begin
error = 0;
val1 = 5'b0000z ;
if(result !=0)
begin
$display("FAILED casez 3.10D - case (expr) lab1: ");
error = 1;
end
val1 = 5'b001z0;
if(result !=1)
begin
$display("FAILED casez 3.10D - case (expr) lab2: ");
error = 1;
end
val1 = 5'b1zzzz; // Should get no-action - expr = 3'b011
if(result !=4)
begin
$display("FAILED casez 3.10D - case (expr) lab1: ");
error = 1;
end
if(error == 0)
$display("PASSED");
end
endmodule // main
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A41O_SYMBOL_V
`define SKY130_FD_SC_LS__A41O_SYMBOL_V
/**
* a41o: 4-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3 & A4) | B1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a41o (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input A4,
input B1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A41O_SYMBOL_V
|
/*
Memory Tile Interface
Keeps a Code and Data buffer.
May attempt to perform external IO if address isn't in cache.
Address Bits
47: 0, Memory Address
59:48, Reserved
60, Disable Caching
*/
module MemTile2(
/* verilator lint_off UNUSED */
clock,
reset,
opRd,
opWr,
opMode,
memAddr,
rdValue,
wrValue,
iopRd,
imemAddr,
irdValue,
extAddr,
extData,
extOE,
extWR,
extHold,
extNotReady
);
input clock; //clock
input reset; //reset
/* Normal Memory */
input opRd; //read value
input opWr; //write value
input[2:0] opMode;
input[31:0] memAddr;
input[63:0] wrValue;
output[63:0] rdValue;
/* Instruction Memory */
input iopRd; //read value
input[31:0] imemAddr;
output[63:0] irdValue;
/* External Memory */
output[31:0] extAddr; //external memory address
inout[31:0] extData; //external memory data (read/write)
output extOE; //external output enable
output extWR; //external write
output extHold; //busy with external memory access
input extNotReady; //external access is not ready
reg[31:0] dTile[2047:0]; //data for data tiles
reg[25:0] dTileBase[127:0]; //base address of memory tile
//reg[ 9:0] dTileBaseHi[127:0]; //base address of memory tile
reg dTileBaseDty[127:0]; //base address of memory tile
reg[31:0] iTile[2047:0]; //data for instruction tiles
reg[25:0] iTileBase[127:0]; //base address of memory tile
//reg[ 9:0] iTileBaseHi[127:0]; //base address of memory tile
reg[10:0] dTileIdx;
reg[10:0] iTileIdx;
reg[10:0] dTileLimIdx;
reg[10:0] iTileLimIdx;
reg dTileMiss;
reg iTileMiss;
reg dTileMiss2;
reg iTileMiss2;
reg[31:0] dMemAddr;
reg[31:0] dMemAddrLim;
reg[31:0] iMemAddr;
reg[31:0] iMemAddrLim;
reg[95:0] rdtTBlock;
reg[95:0] rdtTBlock2;
reg[95:0] rdtValue;
reg[95:0] rdtValue2;
reg[95:0] rdtMask;
reg[95:0] rdtMask2;
reg[4:0] rdtShl;
reg[95:0] irdtTBlock;
reg[95:0] irdtValue;
reg[4:0] irdtShl;
reg[63:0] tDrdValue;
reg[63:0] tIrdValue;
parameter[2:0] MD_NONE = 3'b000;
parameter[2:0] MD_BYTE = 3'b001;
parameter[2:0] MD_WORD = 3'b010;
parameter[2:0] MD_DWORD = 3'b011;
parameter[2:0] MD_QWORD = 3'b100;
parameter[2:0] MD_OWORD = 3'b101;
parameter[2:0] MD_UBYTE = 3'b110;
parameter[2:0] MD_UWORD = 3'b111;
reg[25:0] reqLdTileBaseLo; //base address for requested tile load
reg[9:0] reqLdTileBaseHi; //base address for requested tile load
reg[6:0] reqLdTileIdx; //requested tile to be read into
reg reqLdTile; //loading a tile requested
reg reqLdITile; //request is for an instruction tile
reg reqLdSTile; //request save old tile
reg reqStTile; //store a tile requested
reg reqSyncTile;
reg reqNextSyncTile;
reg[6:0] reqSyncTileIdx; //requested tile to be read into
reg[6:0] reqNextSyncTileIdx; //requested tile to be read into
//assign extHold = reqLdTile || ldTileAct || resetAct;
assign extHold = reqLdTile || ldTileAct || ldTileDlyAct || resetAct;
assign rdValue = tDrdValue;
assign irdValue = tIrdValue;
reg[ 3:0] ldTileWIdx;
reg[ 3:0] ldTileNextWIdx;
reg[31:0] ldTileExtAddr; //external memory address
reg[10:0] ldTileIdx;
reg ldTileAct;
reg ldTileNextAct;
reg ldTileStAct;
reg ldTileNextStAct;
reg ldTileDlyAct;
reg ldTileNextDlyAct;
reg ldTileLastAct;
reg ldTileNextLastAct;
reg ldTileDn;
reg ldTileNextDn;
reg ldTileExtOE;
reg ldTileNextExtOE;
reg ldTileExtWR;
reg ldTileNextExtWR;
assign extOE = ldTileExtOE;
assign extWR = ldTileExtWR;
assign extAddr = ldTileExtAddr;
reg dTileOpWrOK;
reg resetAct;
reg resetNextAct;
reg[ 6:0] resetCurTile;
reg[ 6:0] resetNextTile;
reg[15:0] resetTOK;
always @ (opRd or opWr or iopRd)
// always @ (clock)
begin
dTileMiss = 0;
iTileMiss = 0;
dTileMiss2 = 0;
iTileMiss2 = 0;
reqLdTile = 0;
reqStTile = 0;
reqNextSyncTile = 0;
reqNextSyncTileIdx = 0;
if(opRd || opWr)
begin
dMemAddr = memAddr[31:0];
dMemAddrLim = dMemAddr+15;
dTileIdx = dMemAddr[12:2];
dTileLimIdx = dMemAddrLim[12:2];
dTileMiss = (dTileBase[dTileIdx[10:4]]!=dMemAddr[31:6]);
dTileMiss2 = (dTileBase[dTileLimIdx[10:4]]!=dMemAddrLim[31:6]);
// dTileMiss2 = 0;
// if(opRd && memAddr[60] && !ldTileDlyAct && !ldTileLastAct)
if(opRd && memAddr[29] && !ldTileDlyAct && !ldTileLastAct)
begin
dTileMiss = 1;
// dTileMiss2 = (dTileBase[dTileLimIdx[10:4]]!=dMemAddrLim[31:6]);
end
rdtShl[4:3] = memAddr[1:0];
rdtShl[2:0] = 3'b000;
rdtTBlock[31: 0]=dTile[dTileIdx ];
rdtTBlock[63:32]=dTile[dTileIdx+1];
rdtTBlock[95:64]=dTile[dTileIdx+2];
if(dTileMiss)
begin
// $display("dTileMiss");
reqLdTile = 1;
reqLdTileBaseLo = dMemAddr[31: 6];
reqLdTileIdx = dTileIdx[10: 4];
reqLdITile = 0;
reqLdSTile = dTileBaseDty[dTileIdx[10:4]];
end
else
if(dTileMiss2)
begin
// $display("dTileMiss2");
reqLdTile = 1;
reqLdTileBaseLo = dMemAddrLim[31: 6];
reqLdTileIdx = dTileLimIdx[10: 4];
reqLdITile = 0;
reqLdSTile = dTileBaseDty[dTileLimIdx[10:4]];
end
if(!dTileMiss && !dTileMiss2)
begin
if(reqSyncTile)
begin
reqStTile = 1;
reqLdTileBaseLo = dTileBase[reqSyncTileIdx];
reqLdTileIdx = reqSyncTileIdx;
reqLdITile = 0;
end
// if(opWr && (memAddr[60]!=memAddr[63]))
if(opWr && (memAddr[29]!=0))
begin
reqNextSyncTile = 1;
reqNextSyncTileIdx = dTileIdx[10: 4];
end
end
end
if(iopRd)
begin
iMemAddr = imemAddr[31:0];
iMemAddrLim = iMemAddr+7;
iTileIdx = iMemAddr[12:2];
iTileLimIdx = iMemAddrLim[12:2];
iTileMiss = (iTileBase[iTileIdx[10:4]]!=iMemAddr[31:6]);
iTileMiss2 = (iTileBase[iTileLimIdx[10:4]]!=iMemAddrLim[31:6]);
irdtShl[4:3] = imemAddr[1:0];
irdtShl[2:0] = 3'b000;
if(iTileMiss)
begin
// $display("iTileMiss");
reqLdTile = 1;
reqLdTileBaseLo = imemAddr[31: 6];
reqLdTileIdx = iTileIdx[10: 4];
reqLdITile = 1;
reqLdSTile = 0;
end
else
if(iTileMiss2)
begin
// $display("iTileMiss2");
reqLdTile = 1;
reqLdTileBaseLo = iMemAddrLim[31: 6];
reqLdTileIdx = iTileLimIdx[10: 4];
reqLdITile = 1;
reqLdSTile = 0;
end
else
begin
irdtTBlock[31: 0] = iTile[iTileIdx ];
irdtTBlock[63:32] = iTile[iTileIdx+1];
irdtTBlock[95:64] = iTile[iTileIdx+2];
irdtValue = irdtTBlock>>irdtShl;
tIrdValue[63:0] = irdtValue[63:0];
$display("iTileRd A=%X Ix=%X,Sh=%X Val=%X", imemAddr,
iTileIdx, irdtShl, tIrdValue);
end
end
ldTileNextDlyAct = ldTileAct;
ldTileNextLastAct = ldTileDlyAct;
if(reqLdTile || reqStTile || ldTileAct)
begin
if(ldTileAct==0)
begin
// ldTileWIdx =0;
ldTileNextWIdx=0;
// ldTileDn = 0;
ldTileNextDn = 0;
ldTileNextAct = 1;
ldTileIdx[10:4]=reqLdTileIdx[6:0];
ldTileIdx[ 3:0]=ldTileWIdx;
if(reqLdSTile || reqStTile)
begin
// $display("ldTileNextWIdx: Store");
ldTileNextStAct = 1;
ldTileNextExtOE = 0;
ldTileNextExtWR = 1;
ldTileExtAddr[31: 6] = dTileBase[ldTileIdx[10:4]][25:0];
ldTileExtAddr[ 5: 0] = 0;
end
else
begin
// $display("ldTileNextWIdx: Load");
ldTileNextStAct = 0;
ldTileNextExtOE = 1;
ldTileNextExtWR = 0;
ldTileExtAddr[31: 6] = reqLdTileBaseLo[25:0];
ldTileExtAddr[ 5: 0] = 0;
end
end
else
begin
ldTileNextDn = 0;
ldTileNextAct = 1;
ldTileNextStAct = ldTileStAct;
ldTileExtAddr[5:2]=ldTileWIdx;
ldTileIdx[10:4]=reqLdTileIdx[6:0];
ldTileIdx[ 3:0]=ldTileWIdx;
if(ldTileStAct)
extData = dTile[ldTileIdx];
if(ldTileDn)
begin
ldTileNextDn = 0;
ldTileNextAct = 0;
end
if(extNotReady)
begin
ldTileNextWIdx=ldTileWIdx;
end
else
begin
ldTileNextWIdx=ldTileWIdx+1;
if(ldTileNextWIdx==0)
begin
if(ldTileStAct)
begin
if(reqLdTile)
begin
// $display("ldTileNextWIdx: Store->Load");
ldTileNextAct = 1;
ldTileNextStAct = 0;
ldTileNextDn = 0;
ldTileNextExtOE = 1;
ldTileNextExtWR = 0;
// ldTileExtAddr[47:38] = reqLdTileBaseHi[9:0];
ldTileExtAddr[31: 6] = reqLdTileBaseLo[25:0];
end
else
begin
// $display("ldTileNextWIdx: Done");
ldTileNextAct = 1;
ldTileNextStAct = 0;
ldTileNextDn = 1;
ldTileNextExtOE = 0;
ldTileNextExtWR = 0;
end
end
else
begin
// $display("ldTileNextWIdx: Done");
ldTileNextAct = 1;
ldTileNextDn = 1;
ldTileNextExtOE = 0;
ldTileNextExtWR = 0;
end
end
end
end
end
// end
// always @ (clk)
// begin
if(resetAct)
begin
resetNextTile = resetCurTile+1;
if(resetNextTile==0)
resetNextAct=0;
end
else
if(reset || (resetTOK!=16'h1234))
begin
resetNextAct=1;
resetNextTile=0;
end
if(opRd)
begin
rdtValue=rdtTBlock>>rdtShl;
case(opMode)
MD_BYTE:
begin
tDrdValue[ 7:0]=rdtValue[7:0];
tDrdValue[63:8]=rdtValue[7]?
56'hFFFF_FFFF_FFFF_FF :
56'h0000_0000_0000_00 ;
end
MD_WORD:
begin
tDrdValue[15: 0]=rdtValue[15:0];
tDrdValue[63:16]=rdtValue[15]?
48'hFFFF_FFFF_FFFF :
48'h0000_0000_0000 ;
end
MD_DWORD:
begin
tDrdValue[31: 0]=rdtValue[31:0];
tDrdValue[63:32]=rdtValue[31]?
32'hFFFF_FFFF :
32'h0000_0000 ;
end
MD_QWORD:
begin
tDrdValue=rdtValue[63:0];
end
MD_UBYTE:
begin
tDrdValue[ 7:0]=rdtValue[7:0];
tDrdValue[63:8]=56'h0000_0000_0000_00 ;
end
MD_UWORD:
begin
tDrdValue[15: 0]=rdtValue[15:0];
tDrdValue[63:16]=48'h0000_0000_0000 ;
end
default:
begin
tDrdValue=rdtValue[63:0];
end
endcase
end
dTileOpWrOK = 0;
if(opWr && !reqLdTile && !ldTileAct)
begin
rdtTBlock2 = rdtTBlock;
case(opMode)
MD_BYTE:
case(memAddr[1:0])
0: rdtTBlock2[ 7: 0] = wrValue[7:0];
1: rdtTBlock2[15: 8] = wrValue[7:0];
2: rdtTBlock2[23:16] = wrValue[7:0];
3: rdtTBlock2[31:24] = wrValue[7:0];
endcase
MD_WORD:
case(memAddr[1:0])
0: rdtTBlock2[15: 0] = wrValue[15:0];
1: rdtTBlock2[23: 8] = wrValue[15:0];
2: rdtTBlock2[31:16] = wrValue[15:0];
3: rdtTBlock2[39:24] = wrValue[15:0];
endcase
MD_DWORD:
case(memAddr[1:0])
0: rdtTBlock2[31: 0] = wrValue[31:0];
1: rdtTBlock2[39: 8] = wrValue[31:0];
2: rdtTBlock2[47:16] = wrValue[31:0];
3: rdtTBlock2[55:24] = wrValue[31:0];
endcase
MD_QWORD:
case(memAddr[1:0])
0: rdtTBlock2[63: 0] = wrValue[63:0];
1: rdtTBlock2[71: 8] = wrValue[63:0];
2: rdtTBlock2[79:16] = wrValue[63:0];
3: rdtTBlock2[87:24] = wrValue[63:0];
endcase
default: begin end
endcase
dTileOpWrOK = 1;
end
end
always @ (posedge clock)
begin
resetAct <= resetNextAct;
resetCurTile <= resetNextTile;
if(resetAct)
begin
iTileBase[resetCurTile] <= 26'h3FF_FFFF;
dTileBase[resetCurTile] <= 26'h3FF_FFFF;
resetTOK <= 16'h1234;
end
else
begin
ldTileWIdx <= ldTileNextWIdx;
ldTileAct <= ldTileNextAct;
ldTileStAct <= ldTileNextStAct;
ldTileDlyAct <= ldTileNextDlyAct;
ldTileDn <= ldTileNextDn;
ldTileExtOE <= ldTileNextExtOE;
ldTileExtWR <= ldTileNextExtWR;
reqSyncTile <= reqNextSyncTile;
reqSyncTileIdx <= reqNextSyncTileIdx;
ldTileLastAct <= ldTileNextLastAct;
if(dTileOpWrOK && (!ldTileAct || ldTileDn))
begin
$display("Posedge Write CA=%03X CB=%04X BH=%08X BL=%08X",
dTileIdx, dTileIdx*4,
rdtTBlock2[63:32], rdtTBlock2[31: 0]);
dTile[dTileIdx ] <= rdtTBlock2[31: 0];
dTile[dTileIdx+1] <= rdtTBlock2[63:32];
dTile[dTileIdx+2] <= rdtTBlock2[95:64];
dTileBaseDty[dTileIdx[10:4]] <= 1;
dTileBaseDty[dTileLimIdx[10:4]] <= 1;
end
if(ldTileAct && !ldTileDn && !ldTileStAct)
begin
if(reqLdITile)
iTile[ldTileIdx] <= extData;
else
dTile[ldTileIdx] <= extData;
end
if(ldTileDn)
begin
if(reqLdITile)
begin
iTileBase[reqLdTileIdx[6:0]] <= reqLdTileBaseLo;
end
else
begin
dTileBase[reqLdTileIdx[6:0]] <= reqLdTileBaseLo;
dTileBaseDty[reqLdTileIdx[6:0]] <= 0;
end
end
end
end
endmodule
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_afi_slave.v
*
* Date : 2012-11
*
* Description : Model that acts as AFI port interface. It uses AXI3 Slave BFM
* from Cadence.
*****************************************************************************/
module processing_system7_bfm_v2_0_afi_slave (
S_RESETN,
S_ARREADY,
S_AWREADY,
S_BVALID,
S_RLAST,
S_RVALID,
S_WREADY,
S_BRESP,
S_RRESP,
S_RDATA,
S_BID,
S_RID,
S_ACLK,
S_ARVALID,
S_AWVALID,
S_BREADY,
S_RREADY,
S_WLAST,
S_WVALID,
S_ARBURST,
S_ARLOCK,
S_ARSIZE,
S_AWBURST,
S_AWLOCK,
S_AWSIZE,
S_ARPROT,
S_AWPROT,
S_ARADDR,
S_AWADDR,
S_WDATA,
S_ARCACHE,
S_ARLEN,
S_AWCACHE,
S_AWLEN,
S_WSTRB,
S_ARID,
S_AWID,
S_WID,
S_AWQOS,
S_ARQOS,
SW_CLK,
WR_DATA_ACK_OCM,
WR_DATA_ACK_DDR,
WR_ADDR,
WR_DATA,
WR_BYTES,
WR_DATA_VALID_OCM,
WR_DATA_VALID_DDR,
WR_QOS,
RD_REQ_DDR,
RD_REQ_OCM,
RD_ADDR,
RD_DATA_OCM,
RD_DATA_DDR,
RD_BYTES,
RD_QOS,
RD_DATA_VALID_OCM,
RD_DATA_VALID_DDR,
S_RDISSUECAP1_EN,
S_WRISSUECAP1_EN,
S_RCOUNT,
S_WCOUNT,
S_RACOUNT,
S_WACOUNT
);
parameter enable_this_port = 0;
parameter slave_name = "Slave";
parameter data_bus_width = 32;
parameter address_bus_width = 32;
parameter id_bus_width = 6;
parameter slave_base_address = 0;
parameter slave_high_address = 4;
parameter max_outstanding_transactions = 8;
parameter exclusive_access_supported = 0;
`include "processing_system7_bfm_v2_0_local_params.v"
/* Local parameters only for this module */
/* Internal counters that are used as Read/Write pointers to the fifo's that store all the transaction info on all channles.
This parameter is used to define the width of these pointers --> depending on Maximum outstanding transactions supported.
1-bit extra width than the no.of.bits needed to represent the outstanding transactions
Extra bit helps in generating the empty and full flags
*/
parameter int_cntr_width = clogb2(max_outstanding_transactions)+1;
/* RESP data */
parameter rsp_fifo_bits = axi_rsp_width+id_bus_width;
parameter rsp_lsb = 0;
parameter rsp_msb = axi_rsp_width-1;
parameter rsp_id_lsb = rsp_msb + 1;
parameter rsp_id_msb = rsp_id_lsb + id_bus_width-1;
input S_RESETN;
output S_ARREADY;
output S_AWREADY;
output S_BVALID;
output S_RLAST;
output S_RVALID;
output S_WREADY;
output [axi_rsp_width-1:0] S_BRESP;
output [axi_rsp_width-1:0] S_RRESP;
output [data_bus_width-1:0] S_RDATA;
output [id_bus_width-1:0] S_BID;
output [id_bus_width-1:0] S_RID;
input S_ACLK;
input S_ARVALID;
input S_AWVALID;
input S_BREADY;
input S_RREADY;
input S_WLAST;
input S_WVALID;
input [axi_brst_type_width-1:0] S_ARBURST;
input [axi_lock_width-1:0] S_ARLOCK;
input [axi_size_width-1:0] S_ARSIZE;
input [axi_brst_type_width-1:0] S_AWBURST;
input [axi_lock_width-1:0] S_AWLOCK;
input [axi_size_width-1:0] S_AWSIZE;
input [axi_prot_width-1:0] S_ARPROT;
input [axi_prot_width-1:0] S_AWPROT;
input [address_bus_width-1:0] S_ARADDR;
input [address_bus_width-1:0] S_AWADDR;
input [data_bus_width-1:0] S_WDATA;
input [axi_cache_width-1:0] S_ARCACHE;
input [axi_cache_width-1:0] S_ARLEN;
input [axi_qos_width-1:0] S_ARQOS;
input [axi_cache_width-1:0] S_AWCACHE;
input [axi_len_width-1:0] S_AWLEN;
input [axi_qos_width-1:0] S_AWQOS;
input [(data_bus_width/8)-1:0] S_WSTRB;
input [id_bus_width-1:0] S_ARID;
input [id_bus_width-1:0] S_AWID;
input [id_bus_width-1:0] S_WID;
input SW_CLK;
input WR_DATA_ACK_DDR, WR_DATA_ACK_OCM;
output WR_DATA_VALID_DDR, WR_DATA_VALID_OCM;
output [max_burst_bits-1:0] WR_DATA;
output [addr_width-1:0] WR_ADDR;
output [max_transfer_bytes_width:0] WR_BYTES;
output reg RD_REQ_OCM, RD_REQ_DDR;
output reg [addr_width-1:0] RD_ADDR;
input [max_burst_bits-1:0] RD_DATA_DDR,RD_DATA_OCM;
output reg[max_transfer_bytes_width:0] RD_BYTES;
input RD_DATA_VALID_OCM,RD_DATA_VALID_DDR;
output [axi_qos_width-1:0] WR_QOS;
output reg [axi_qos_width-1:0] RD_QOS;
input S_RDISSUECAP1_EN;
input S_WRISSUECAP1_EN;
output [7:0] S_RCOUNT;
output [7:0] S_WCOUNT;
output [2:0] S_RACOUNT;
output [5:0] S_WACOUNT;
wire net_ARVALID;
wire net_AWVALID;
wire net_WVALID;
real s_aclk_period;
cdn_axi3_slave_bfm #(slave_name,
data_bus_width,
address_bus_width,
id_bus_width,
slave_base_address,
(slave_high_address- slave_base_address),
max_outstanding_transactions,
0, ///MEMORY_MODEL_MODE,
exclusive_access_supported)
slave (.ACLK (S_ACLK),
.ARESETn (S_RESETN), /// confirm this
// Write Address Channel
.AWID (S_AWID),
.AWADDR (S_AWADDR),
.AWLEN (S_AWLEN),
.AWSIZE (S_AWSIZE),
.AWBURST (S_AWBURST),
.AWLOCK (S_AWLOCK),
.AWCACHE (S_AWCACHE),
.AWPROT (S_AWPROT),
.AWVALID (net_AWVALID),
.AWREADY (S_AWREADY),
// Write Data Channel Signals.
.WID (S_WID),
.WDATA (S_WDATA),
.WSTRB (S_WSTRB),
.WLAST (S_WLAST),
.WVALID (net_WVALID),
.WREADY (S_WREADY),
// Write Response Channel Signals.
.BID (S_BID),
.BRESP (S_BRESP),
.BVALID (S_BVALID),
.BREADY (S_BREADY),
// Read Address Channel Signals.
.ARID (S_ARID),
.ARADDR (S_ARADDR),
.ARLEN (S_ARLEN),
.ARSIZE (S_ARSIZE),
.ARBURST (S_ARBURST),
.ARLOCK (S_ARLOCK),
.ARCACHE (S_ARCACHE),
.ARPROT (S_ARPROT),
.ARVALID (net_ARVALID),
.ARREADY (S_ARREADY),
// Read Data Channel Signals.
.RID (S_RID),
.RDATA (S_RDATA),
.RRESP (S_RRESP),
.RLAST (S_RLAST),
.RVALID (S_RVALID),
.RREADY (S_RREADY));
wire wr_intr_fifo_full;
reg temp_wr_intr_fifo_full;
/* Interconnect WR_FIFO model instance */
processing_system7_bfm_v2_0_intr_wr_mem wr_intr_fifo(SW_CLK, S_RESETN, wr_intr_fifo_full, WR_DATA_ACK_OCM, WR_DATA_ACK_DDR, WR_ADDR, WR_DATA, WR_BYTES, WR_QOS, WR_DATA_VALID_OCM, WR_DATA_VALID_DDR);
/* Register the async 'full' signal to S_ACLK clock */
always@(posedge S_ACLK) temp_wr_intr_fifo_full = wr_intr_fifo_full;
/* Latency type and Debug/Error Control */
reg[1:0] latency_type = RANDOM_CASE;
reg DEBUG_INFO = 1;
reg STOP_ON_ERROR = 1'b1;
/* Internal nets/regs for calling slave BFM API's*/
reg [wr_afi_fifo_data_bits-1:0] wr_fifo [0:max_outstanding_transactions-1];
reg [int_cntr_width-1:0] wr_fifo_wr_ptr = 0, wr_fifo_rd_ptr = 0;
wire wr_fifo_empty;
/* Store the awvalid receive time --- necessary for calculating the bresp latency */
reg [7:0] aw_time_cnt = 0,bresp_time_cnt = 0;
real awvalid_receive_time[0:max_outstanding_transactions]; // store the time when a new awvalid is received
reg awvalid_flag[0:max_outstanding_transactions]; // store the time when a new awvalid is received
/* Address Write Channel handshake*/
reg[int_cntr_width-1:0] aw_cnt = 0;//
/* various FIFOs for storing the ADDR channel info */
reg [axi_size_width-1:0] awsize [0:max_outstanding_transactions-1];
reg [axi_prot_width-1:0] awprot [0:max_outstanding_transactions-1];
reg [axi_lock_width-1:0] awlock [0:max_outstanding_transactions-1];
reg [axi_cache_width-1:0] awcache [0:max_outstanding_transactions-1];
reg [axi_brst_type_width-1:0] awbrst [0:max_outstanding_transactions-1];
reg [axi_len_width-1:0] awlen [0:max_outstanding_transactions-1];
reg aw_flag [0:max_outstanding_transactions-1];
reg [addr_width-1:0] awaddr [0:max_outstanding_transactions-1];
reg [id_bus_width-1:0] awid [0:max_outstanding_transactions-1];
reg [axi_qos_width-1:0] awqos [0:max_outstanding_transactions-1];
wire aw_fifo_full; // indicates awvalid_fifo is full (max outstanding transactions reached)
/* internal fifos to store burst write data, ID & strobes*/
reg [(data_bus_width*axi_burst_len)-1:0] burst_data [0:max_outstanding_transactions-1];
reg [max_burst_bytes_width:0] burst_valid_bytes [0:max_outstanding_transactions-1]; /// total valid bytes received in a complete burst transfer
reg wlast_flag [0:max_outstanding_transactions-1]; // flag to indicate WLAST received
wire wd_fifo_full;
/* Write Data Channel and Write Response handshake signals*/
reg [int_cntr_width-1:0] wd_cnt = 0;
reg [(data_bus_width*axi_burst_len)-1:0] aligned_wr_data;
reg [addr_width-1:0] aligned_wr_addr;
reg [max_burst_bytes_width:0] valid_data_bytes;
reg [int_cntr_width-1:0] wr_bresp_cnt = 0;
reg [axi_rsp_width-1:0] bresp;
reg [rsp_fifo_bits-1:0] fifo_bresp [0:max_outstanding_transactions-1]; // store the ID and its corresponding response
reg enable_write_bresp;
reg [int_cntr_width-1:0] rd_bresp_cnt = 0;
integer wr_latency_count;
reg wr_delayed;
wire bresp_fifo_empty;
/* keep track of count values */
reg[7:0] wcount;
reg[5:0] wacount;
/* Qos*/
reg [axi_qos_width-1:0] ar_qos, aw_qos;
initial begin
if(DEBUG_INFO) begin
if(enable_this_port)
$display("[%0d] : %0s : %0s : Port is ENABLED.",$time, DISP_INFO, slave_name);
else
$display("[%0d] : %0s : %0s : Port is DISABLED.",$time, DISP_INFO, slave_name);
end
end
/*--------------------------------------------------------------------------------*/
/* Store the Clock cycle time period */
always@(S_RESETN)
begin
if(S_RESETN) begin
@(posedge S_ACLK);
s_aclk_period = $time;
@(posedge S_ACLK);
s_aclk_period = $time - s_aclk_period;
end
end
/*--------------------------------------------------------------------------------*/
initial slave.set_disable_reset_value_checks(1);
initial begin
repeat(2) @(posedge S_ACLK);
if(!enable_this_port) begin
slave.set_channel_level_info(0);
slave.set_function_level_info(0);
end
slave.RESPONSE_TIMEOUT = 0;
end
/*--------------------------------------------------------------------------------*/
/* Set Latency type to be used */
task set_latency_type;
input[1:0] lat;
begin
if(enable_this_port)
latency_type = lat;
else begin
//if(DEBUG_INFO)
$display("[%0d] : %0s : %0s : Port is disabled. 'Latency Profile' will not be set...",$time, DISP_WARN, slave_name);
end
end
endtask
/*--------------------------------------------------------------------------------*/
/* Set ARQoS to be used */
task set_arqos;
input[axi_qos_width-1:0] qos;
begin
if(enable_this_port)
ar_qos = qos;
else begin
if(DEBUG_INFO)
$display("[%0d] : %0s : %0s : Port is disabled. 'ARQOS' will not be set...",$time, DISP_WARN, slave_name);
end
end
endtask
/*--------------------------------------------------------------------------------*/
/* Set AWQoS to be used */
task set_awqos;
input[axi_qos_width-1:0] qos;
begin
if(enable_this_port)
aw_qos = qos;
else begin
if(DEBUG_INFO)
$display("[%0d] : %0s : %0s : Port is disabled. 'AWQOS' will not be set...",$time, DISP_WARN, slave_name);
end
end
endtask
/*--------------------------------------------------------------------------------*/
/* get the wr latency number */
function [31:0] get_wr_lat_number;
input dummy;
reg[1:0] temp;
begin
case(latency_type)
BEST_CASE : get_wr_lat_number = afi_wr_min;
AVG_CASE : get_wr_lat_number = afi_wr_avg;
WORST_CASE : get_wr_lat_number = afi_wr_max;
default : begin // RANDOM_CASE
temp = $random;
case(temp)
2'b00 : get_wr_lat_number = ($random()%10+ afi_wr_min);
2'b01 : get_wr_lat_number = ($random()%40+ afi_wr_avg);
default : get_wr_lat_number = ($random()%60+ afi_wr_max);
endcase
end
endcase
end
endfunction
/*--------------------------------------------------------------------------------*/
/* get the rd latency number */
function [31:0] get_rd_lat_number;
input dummy;
reg[1:0] temp;
begin
case(latency_type)
BEST_CASE : get_rd_lat_number = afi_rd_min;
AVG_CASE : get_rd_lat_number = afi_rd_avg;
WORST_CASE : get_rd_lat_number = afi_rd_max;
default : begin // RANDOM_CASE
temp = $random;
case(temp)
2'b00 : get_rd_lat_number = ($random()%10+ afi_rd_min);
2'b01 : get_rd_lat_number = ($random()%40+ afi_rd_avg);
default : get_rd_lat_number = ($random()%60+ afi_rd_max);
endcase
end
endcase
end
endfunction
/*--------------------------------------------------------------------------------*/
/* Check for any WRITE/READs when this port is disabled */
always@(S_AWVALID or S_WVALID or S_ARVALID)
begin
if((S_AWVALID | S_WVALID | S_ARVALID) && !enable_this_port) begin
$display("[%0d] : %0s : %0s : Port is disabled. AXI transaction is initiated on this port ...\nSimulation will halt ..",$time, DISP_ERR, slave_name);
$stop;
end
end
/*--------------------------------------------------------------------------------*/
assign net_ARVALID = enable_this_port ? S_ARVALID : 1'b0;
assign net_AWVALID = enable_this_port ? S_AWVALID : 1'b0;
assign net_WVALID = enable_this_port ? S_WVALID : 1'b0;
assign wr_fifo_empty = (wr_fifo_wr_ptr === wr_fifo_rd_ptr)?1'b1: 1'b0;
assign bresp_fifo_empty = (wr_bresp_cnt === rd_bresp_cnt)?1'b1:1'b0;
assign bresp_fifo_full = ((wr_bresp_cnt[int_cntr_width-1] !== rd_bresp_cnt[int_cntr_width-1]) && (wr_bresp_cnt[int_cntr_width-2:0] === rd_bresp_cnt[int_cntr_width-2:0]))?1'b1:1'b0;
assign S_WCOUNT = wcount;
assign S_WACOUNT = wacount;
// FIFO_STATUS (only if AFI port) 1- full
function automatic wrfifo_full ;
input [axi_len_width-1:0] fifo_space_exp;
integer fifo_space_left;
begin
fifo_space_left = afi_fifo_locations - wcount;
if(fifo_space_left < fifo_space_exp)
wrfifo_full = 1;
else
wrfifo_full = 0;
end
endfunction
/*--------------------------------------------------------------------------------*/
/* Store the awvalid receive time --- necessary for calculating the bresp latency */
always@(negedge S_RESETN or S_AWID or S_AWADDR or S_AWVALID )
begin
if(!S_RESETN)
aw_time_cnt <= 0;
else begin
if(S_AWVALID) begin
awvalid_receive_time[aw_time_cnt] <= $time;
awvalid_flag[aw_time_cnt] <= 1'b1;
aw_time_cnt <= aw_time_cnt + 1;
end
end // else
end /// always
/*--------------------------------------------------------------------------------*/
always@(posedge S_ACLK)
begin
if(net_AWVALID && S_AWREADY) begin
if(S_AWQOS === 0) awqos[aw_cnt[int_cntr_width-2:0]] = aw_qos;
else awqos[aw_cnt[int_cntr_width-2:0]] = S_AWQOS;
end
end
/* Address Write Channel handshake*/
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN) begin
aw_cnt <= 0;
wacount <= 0;
end else begin
if(S_AWVALID && !wrfifo_full(S_AWLEN+1)) begin
slave.RECEIVE_WRITE_ADDRESS(0,
id_invalid,
awaddr[aw_cnt[int_cntr_width-2:0]],
awlen[aw_cnt[int_cntr_width-2:0]],
awsize[aw_cnt[int_cntr_width-2:0]],
awbrst[aw_cnt[int_cntr_width-2:0]],
awlock[aw_cnt[int_cntr_width-2:0]],
awcache[aw_cnt[int_cntr_width-2:0]],
awprot[aw_cnt[int_cntr_width-2:0]],
awid[aw_cnt[int_cntr_width-2:0]]); /// sampled valid ID.
aw_flag[aw_cnt[int_cntr_width-2:0]] <= 1'b1;
aw_cnt <= aw_cnt + 1;
wacount <= wacount + 1;
end // if (!aw_fifo_full)
end /// if else
end /// always
/*--------------------------------------------------------------------------------*/
/* Write Data Channel Handshake */
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN) begin
wd_cnt <= 0;
end else begin
if(aw_flag[wd_cnt[int_cntr_width-2:0]]) begin
if(S_WVALID && !wrfifo_full(awlen[wd_cnt[int_cntr_width-2:0]] + 1)) begin
slave.RECEIVE_WRITE_BURST_NO_CHECKS(S_WID, burst_data[wd_cnt[int_cntr_width-2:0]], burst_valid_bytes[wd_cnt[int_cntr_width-2:0]]);
wlast_flag[wd_cnt[int_cntr_width-2:0]] <= 1'b1;
wd_cnt <= wd_cnt + 1;
end
end else begin
if(!wrfifo_full(axi_burst_len) && S_WVALID) begin
slave.RECEIVE_WRITE_BURST_NO_CHECKS(S_WID, burst_data[wd_cnt[int_cntr_width-2:0]], burst_valid_bytes[wd_cnt[int_cntr_width-2:0]]);
wlast_flag[wd_cnt[int_cntr_width-2:0]] <= 1'b1;
wd_cnt <= wd_cnt + 1;
end
end /// if
end /// else
end /// always
/*--------------------------------------------------------------------------------*/
/* Align the wrap data for write transaction */
task automatic get_wrap_aligned_wr_data;
output [(data_bus_width*axi_burst_len)-1:0] aligned_data;
output [addr_width-1:0] start_addr; /// aligned start address
input [addr_width-1:0] addr;
input [(data_bus_width*axi_burst_len)-1:0] b_data;
input [max_burst_bytes_width:0] v_bytes;
reg [(data_bus_width*axi_burst_len)-1:0] temp_data, wrp_data;
integer wrp_bytes;
integer i;
begin
start_addr = (addr/v_bytes) * v_bytes;
wrp_bytes = addr - start_addr;
wrp_data = b_data;
temp_data = 0;
wrp_data = wrp_data << ((data_bus_width*axi_burst_len) - (v_bytes*8));
while(wrp_bytes > 0) begin /// get the data that is wrapped
temp_data = temp_data << 8;
temp_data[7:0] = wrp_data[(data_bus_width*axi_burst_len)-1 : (data_bus_width*axi_burst_len)-8];
wrp_data = wrp_data << 8;
wrp_bytes = wrp_bytes - 1;
end
wrp_bytes = addr - start_addr;
wrp_data = b_data << (wrp_bytes*8);
aligned_data = (temp_data | wrp_data);
end
endtask
/*--------------------------------------------------------------------------------*/
/* Calculate the Response for each read/write transaction */
function [axi_rsp_width-1:0] calculate_resp;
input [addr_width-1:0] awaddr;
input [axi_prot_width-1:0] awprot;
reg [axi_rsp_width-1:0] rsp;
begin
rsp = AXI_OK;
/* Address Decode */
if(decode_address(awaddr) === INVALID_MEM_TYPE) begin
rsp = AXI_SLV_ERR; //slave error
$display("[%0d] : %0s : %0s : AXI Access to Invalid location(0x%0h) ",$time, DISP_ERR, slave_name, awaddr);
end
else if(decode_address(awaddr) === REG_MEM) begin
rsp = AXI_SLV_ERR; //slave error
$display("[%0d] : %0s : %0s : AXI Access to Register Map(0x%0h) is not allowed through this port.",$time, DISP_ERR, slave_name, awaddr);
end
if(secure_access_enabled && awprot[1])
rsp = AXI_DEC_ERR; // decode error
calculate_resp = rsp;
end
endfunction
/*--------------------------------------------------------------------------------*/
reg[max_burst_bits-1:0] temp_wr_data;
/* Store the Write response for each write transaction */
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN) begin
wr_fifo_wr_ptr <= 0;
wcount <= 0;
end else begin
enable_write_bresp = aw_flag[wr_fifo_wr_ptr[int_cntr_width-2:0]] && wlast_flag[wr_fifo_wr_ptr[int_cntr_width-2:0]];
/* calculate bresp only when AWVALID && WLAST is received */
if(enable_write_bresp) begin
aw_flag[wr_fifo_wr_ptr[int_cntr_width-2:0]] <= 0;
wlast_flag[wr_fifo_wr_ptr[int_cntr_width-2:0]] <= 0;
bresp = calculate_resp(awaddr[wr_fifo_wr_ptr[int_cntr_width-2:0]], awprot[wr_fifo_wr_ptr[int_cntr_width-2:0]]);
/* Fill AFI_WR_data FIFO */
if(bresp === AXI_OK ) begin
if(awbrst[wr_fifo_wr_ptr[int_cntr_width-2:0]]=== AXI_WRAP) begin /// wrap type? then align the data
get_wrap_aligned_wr_data(aligned_wr_data, aligned_wr_addr, awaddr[wr_fifo_wr_ptr[int_cntr_width-2:0]], burst_data[wr_fifo_wr_ptr[int_cntr_width-2:0]],burst_valid_bytes[wr_fifo_wr_ptr[int_cntr_width-2:0]]); /// gives wrapped start address
end else begin
aligned_wr_data = burst_data[wr_fifo_wr_ptr[int_cntr_width-2:0]];
aligned_wr_addr = awaddr[wr_fifo_wr_ptr[int_cntr_width-2:0]] ;
end
valid_data_bytes = burst_valid_bytes[wr_fifo_wr_ptr[int_cntr_width-2:0]];
end else
valid_data_bytes = 0;
temp_wr_data = aligned_wr_data;
wr_fifo[wr_fifo_wr_ptr[int_cntr_width-2:0]] = {awqos[wr_fifo_wr_ptr[int_cntr_width-2:0]], awlen[wr_fifo_wr_ptr[int_cntr_width-2:0]], awid[wr_fifo_wr_ptr[int_cntr_width-2:0]], bresp, temp_wr_data, aligned_wr_addr, valid_data_bytes};
wcount <= wcount + awlen[wr_fifo_wr_ptr[int_cntr_width-2:0]]+1;
wr_fifo_wr_ptr <= wr_fifo_wr_ptr + 1;
end
end // else
end // always
/*--------------------------------------------------------------------------------*/
/* Send Write Response Channel handshake */
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN) begin
rd_bresp_cnt <= 0;
wr_latency_count = get_wr_lat_number(1);
wr_delayed = 0;
bresp_time_cnt <= 0;
end else begin
wr_delayed = 1'b0;
if(awvalid_flag[bresp_time_cnt] && (($time - awvalid_receive_time[bresp_time_cnt])/s_aclk_period >= wr_latency_count))
wr_delayed = 1;
if(!bresp_fifo_empty && wr_delayed) begin
slave.SEND_WRITE_RESPONSE(fifo_bresp[rd_bresp_cnt[int_cntr_width-2:0]][rsp_id_msb : rsp_id_lsb], // ID
fifo_bresp[rd_bresp_cnt[int_cntr_width-2:0]][rsp_msb : rsp_lsb] // Response
);
wr_delayed = 0;
awvalid_flag[bresp_time_cnt] = 1'b0;
bresp_time_cnt <= bresp_time_cnt+1;
rd_bresp_cnt <= rd_bresp_cnt + 1;
wr_latency_count = get_wr_lat_number(1);
end
end // else
end//always
/*--------------------------------------------------------------------------------*/
/* Write Response Channel handshake */
reg wr_int_state;
/* Reading from the wr_fifo and sending to Interconnect fifo*/
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN) begin
wr_int_state <= 1'b0;
wr_bresp_cnt <= 0;
wr_fifo_rd_ptr <= 0;
end else begin
case(wr_int_state)
1'b0 : begin
wr_int_state <= 1'b0;
if(!temp_wr_intr_fifo_full && !bresp_fifo_full && !wr_fifo_empty) begin
wr_intr_fifo.write_mem({wr_fifo[wr_fifo_rd_ptr[int_cntr_width-2:0]][wr_afi_qos_msb:wr_afi_qos_lsb], wr_fifo[wr_fifo_rd_ptr[int_cntr_width-2:0]][wr_afi_data_msb:wr_afi_bytes_lsb]}); /// qos, data, address and valid_bytes
wr_int_state <= 1'b1;
/* start filling the write response fifo at the same time */
fifo_bresp[wr_bresp_cnt[int_cntr_width-2:0]] <= wr_fifo[wr_fifo_rd_ptr[int_cntr_width-2:0]][wr_afi_id_msb:wr_afi_rsp_lsb]; // ID and Resp
wcount <= wcount - (wr_fifo[wr_fifo_rd_ptr[int_cntr_width-2:0]][wr_afi_ln_msb:wr_afi_ln_lsb] + 1); /// burst length
wacount <= wacount - 1;
wr_fifo_rd_ptr <= wr_fifo_rd_ptr + 1;
wr_bresp_cnt <= wr_bresp_cnt+1;
end
end
1'b1 : begin
wr_int_state <= 0;
end
endcase
end
end
/*--------------------------------------------------------------------------------*/
/*-------------------------------- WRITE HANDSHAKE END ----------------------------------------*/
/*-------------------------------- READ HANDSHAKE ---------------------------------------------*/
/* READ CHANNELS */
/* Store the arvalid receive time --- necessary for calculating latency in sending the rresp latency */
reg [7:0] ar_time_cnt = 0,rresp_time_cnt = 0;
real arvalid_receive_time[0:max_outstanding_transactions]; // store the time when a new arvalid is received
reg arvalid_flag[0:max_outstanding_transactions]; // store the time when a new arvalid is received
reg [int_cntr_width-1:0] ar_cnt = 0;// counter for arvalid info
/* various FIFOs for storing the ADDR channel info */
reg [axi_size_width-1:0] arsize [0:max_outstanding_transactions-1];
reg [axi_prot_width-1:0] arprot [0:max_outstanding_transactions-1];
reg [axi_brst_type_width-1:0] arbrst [0:max_outstanding_transactions-1];
reg [axi_len_width-1:0] arlen [0:max_outstanding_transactions-1];
reg [axi_cache_width-1:0] arcache [0:max_outstanding_transactions-1];
reg [axi_lock_width-1:0] arlock [0:max_outstanding_transactions-1];
reg ar_flag [0:max_outstanding_transactions-1];
reg [addr_width-1:0] araddr [0:max_outstanding_transactions-1];
reg [id_bus_width-1:0] arid [0:max_outstanding_transactions-1];
reg [axi_qos_width-1:0] arqos [0:max_outstanding_transactions-1];
wire ar_fifo_full; // indicates arvalid_fifo is full (max outstanding transactions reached)
reg [int_cntr_width-1:0] wr_rresp_cnt = 0;
reg [axi_rsp_width-1:0] rresp;
reg [rsp_fifo_bits-1:0] fifo_rresp [0:max_outstanding_transactions-1]; // store the ID and its corresponding response
reg enable_write_rresp;
/* Send Read Response & Data Channel handshake */
integer rd_latency_count;
reg rd_delayed;
reg [rd_afi_fifo_bits-1:0] read_fifo[0:max_outstanding_transactions-1]; /// Read Burst Data, addr, size, burst, len, RID, RRESP, valid_bytes
reg [int_cntr_width-1:0] rd_fifo_wr_ptr = 0, rd_fifo_rd_ptr = 0;
wire read_fifo_full;
reg [7:0] rcount;
reg [2:0] racount;
wire rd_intr_fifo_full, rd_intr_fifo_empty;
wire read_fifo_empty;
/* signals to communicate with interconnect RD_FIFO model */
reg rd_req, invalid_rd_req;
/* REad control Info
56:25 : Address (32)
24:22 : Size (3)
21:20 : BRST (2)
19:16 : LEN (4)
15:10 : RID (6)
9:8 : RRSP (2)
7:0 : byte cnt (8)
*/
reg [rd_info_bits-1:0] read_control_info;
reg [(data_bus_width*axi_burst_len)-1:0] aligned_rd_data;
reg temp_rd_intr_fifo_empty;
processing_system7_bfm_v2_0_intr_rd_mem rd_intr_fifo(SW_CLK, S_RESETN, rd_intr_fifo_full, rd_intr_fifo_empty, rd_req, invalid_rd_req, read_control_info , RD_DATA_OCM, RD_DATA_DDR, RD_DATA_VALID_OCM, RD_DATA_VALID_DDR);
assign read_fifo_empty = (rd_fifo_wr_ptr === rd_fifo_rd_ptr)?1'b1: 1'b0;
assign S_RCOUNT = rcount;
assign S_RACOUNT = racount;
/* Register the asynch signal empty coming from Interconnect READ FIFO */
always@(posedge S_ACLK) temp_rd_intr_fifo_empty = rd_intr_fifo_empty;
// FIFO_STATUS (only if AFI port) 1- full
function automatic rdfifo_full ;
input [axi_len_width-1:0] fifo_space_exp;
integer fifo_space_left;
begin
fifo_space_left = afi_fifo_locations - rcount;
if(fifo_space_left < fifo_space_exp)
rdfifo_full = 1;
else
rdfifo_full = 0;
end
endfunction
/* Store the arvalid receive time --- necessary for calculating the bresp latency */
always@(negedge S_RESETN or S_ARID or S_ARADDR or S_ARVALID )
begin
if(!S_RESETN)
ar_time_cnt <= 0;
else begin
if(S_ARVALID) begin
arvalid_receive_time[ar_time_cnt] <= $time;
arvalid_flag[ar_time_cnt] <= 1'b1;
ar_time_cnt <= ar_time_cnt + 1;
end
end // else
end /// always
/*--------------------------------------------------------------------------------*/
always@(posedge S_ACLK)
begin
if(net_ARVALID && S_ARREADY) begin
if(S_ARQOS === 0) arqos[aw_cnt[int_cntr_width-2:0]] = ar_qos;
else arqos[aw_cnt[int_cntr_width-2:0]] = S_ARQOS;
end
end
/* Address Read Channel handshake*/
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN) begin
ar_cnt <= 0;
racount <= 0;
end else begin
if(S_ARVALID && !rdfifo_full(S_ARLEN+1)) begin /// if AFI read fifo is not full
slave.RECEIVE_READ_ADDRESS(0,
id_invalid,
araddr[ar_cnt[int_cntr_width-2:0]],
arlen[ar_cnt[int_cntr_width-2:0]],
arsize[ar_cnt[int_cntr_width-2:0]],
arbrst[ar_cnt[int_cntr_width-2:0]],
arlock[ar_cnt[int_cntr_width-2:0]],
arcache[ar_cnt[int_cntr_width-2:0]],
arprot[ar_cnt[int_cntr_width-2:0]],
arid[ar_cnt[int_cntr_width-2:0]]); /// sampled valid ID.
ar_flag[ar_cnt[int_cntr_width-2:0]] <= 1'b1;
ar_cnt <= ar_cnt+1;
racount <= racount + 1;
end /// if(!ar_fifo_full)
end /// if else
end /// always*/
/*--------------------------------------------------------------------------------*/
/* Align Wrap data for read transaction*/
task automatic get_wrap_aligned_rd_data;
output [(data_bus_width*axi_burst_len)-1:0] aligned_data;
input [addr_width-1:0] addr;
input [(data_bus_width*axi_burst_len)-1:0] b_data;
input [max_burst_bytes_width:0] v_bytes;
reg [addr_width-1:0] start_addr;
reg [(data_bus_width*axi_burst_len)-1:0] temp_data, wrp_data;
integer wrp_bytes;
integer i;
begin
start_addr = (addr/v_bytes) * v_bytes;
wrp_bytes = addr - start_addr;
wrp_data = b_data;
temp_data = 0;
while(wrp_bytes > 0) begin /// get the data that is wrapped
temp_data = temp_data >> 8;
temp_data[(data_bus_width*axi_burst_len)-1 : (data_bus_width*axi_burst_len)-8] = wrp_data[7:0];
wrp_data = wrp_data >> 8;
wrp_bytes = wrp_bytes - 1;
end
temp_data = temp_data >> ((data_bus_width*axi_burst_len) - (v_bytes*8));
wrp_bytes = addr - start_addr;
wrp_data = b_data >> (wrp_bytes*8);
aligned_data = (temp_data | wrp_data);
end
endtask
/*--------------------------------------------------------------------------------*/
parameter RD_DATA_REQ = 1'b0, WAIT_RD_VALID = 1'b1;
reg rd_fifo_state;
reg [addr_width-1:0] temp_read_address;
reg [max_burst_bytes_width:0] temp_rd_valid_bytes;
/* get the data from memory && also calculate the rresp*/
always@(negedge S_RESETN or posedge SW_CLK)
begin
if(!S_RESETN)begin
wr_rresp_cnt <=0;
rd_fifo_state <= RD_DATA_REQ;
temp_rd_valid_bytes = 0;
temp_read_address <= 0;
RD_REQ_DDR <= 1'b0;
RD_REQ_OCM <= 1'b0;
rd_req <= 0;
invalid_rd_req<= 0;
RD_QOS <= 0;
end else begin
case(rd_fifo_state)
RD_DATA_REQ : begin
rd_fifo_state <= RD_DATA_REQ;
RD_REQ_DDR <= 1'b0;
RD_REQ_OCM <= 1'b0;
invalid_rd_req <= 0;
if(ar_flag[wr_rresp_cnt[int_cntr_width-2:0]] && !rd_intr_fifo_full) begin /// check the rd_fifo_bytes, interconnect fifo full condition
ar_flag[wr_rresp_cnt[int_cntr_width-2:0]] <= 0;
rresp = calculate_resp(araddr[wr_rresp_cnt[int_cntr_width-2:0]],arprot[wr_rresp_cnt[int_cntr_width-2:0]]);
temp_rd_valid_bytes = (arlen[wr_rresp_cnt[int_cntr_width-2:0]]+1)*(2**arsize[wr_rresp_cnt[int_cntr_width-2:0]]);//data_bus_width/8;
if(arbrst[wr_rresp_cnt[int_cntr_width-2:0]] === AXI_WRAP) /// wrap begin
temp_read_address = (araddr[wr_rresp_cnt[int_cntr_width-2:0]]/temp_rd_valid_bytes) * temp_rd_valid_bytes;
else
temp_read_address = araddr[wr_rresp_cnt[int_cntr_width-2:0]];
if(rresp === AXI_OK) begin
case(decode_address(temp_read_address))//decode_address(araddr[wr_rresp_cnt[int_cntr_width-2:0]]);
OCM_MEM : RD_REQ_OCM <= 1;
DDR_MEM : RD_REQ_DDR <= 1;
default : invalid_rd_req <= 1;
endcase
end else
invalid_rd_req <= 1;
RD_ADDR <= temp_read_address; ///araddr[wr_rresp_cnt[int_cntr_width-2:0]];
RD_BYTES <= temp_rd_valid_bytes;
RD_QOS <= arqos[wr_rresp_cnt[int_cntr_width-2:0]];
rd_fifo_state <= WAIT_RD_VALID;
rd_req <= 1;
racount <= racount - 1;
read_control_info <= {araddr[wr_rresp_cnt[int_cntr_width-2:0]], arsize[wr_rresp_cnt[int_cntr_width-2:0]], arbrst[wr_rresp_cnt[int_cntr_width-2:0]], arlen[wr_rresp_cnt[int_cntr_width-2:0]], arid[wr_rresp_cnt[int_cntr_width-2:0]], rresp, temp_rd_valid_bytes };
wr_rresp_cnt <= wr_rresp_cnt + 1;
end
end
WAIT_RD_VALID : begin
rd_fifo_state <= WAIT_RD_VALID;
rd_req <= 0;
if(RD_DATA_VALID_OCM | RD_DATA_VALID_DDR | invalid_rd_req) begin ///temp_dec == 2'b11) begin
RD_REQ_DDR <= 1'b0;
RD_REQ_OCM <= 1'b0;
invalid_rd_req <= 0;
rd_fifo_state <= RD_DATA_REQ;
end
end
endcase
end /// else
end /// always
/*--------------------------------------------------------------------------------*/
/* thread to fill in the AFI RD_FIFO */
reg[rd_afi_fifo_bits-1:0] temp_rd_data;//Read Burst Data, addr, size, burst, len, RID, RRESP, valid bytes
reg tmp_state;
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN)begin
rd_fifo_wr_ptr <= 0;
rcount <= 0;
tmp_state <= 0;
end else begin
case(tmp_state)
0 : begin
tmp_state <= 0;
if(!temp_rd_intr_fifo_empty) begin
rd_intr_fifo.read_mem(temp_rd_data);
tmp_state <= 1;
end
end
1 : begin
tmp_state <= 1;
if(!rdfifo_full(temp_rd_data[rd_afi_ln_msb:rd_afi_ln_lsb]+1)) begin
read_fifo[rd_fifo_wr_ptr[int_cntr_width-2:0]] = temp_rd_data;
rd_fifo_wr_ptr = rd_fifo_wr_ptr + 1;
rcount <= rcount + temp_rd_data[rd_afi_ln_msb:rd_afi_ln_lsb]+1; /// Burst length
tmp_state <= 0;
end
end
endcase
end
end
/*--------------------------------------------------------------------------------*/
reg[max_burst_bytes_width:0] rd_v_b;
reg[rd_afi_fifo_bits-1:0] tmp_fifo_rd; /// Data, addr, size, burst, len, RID, RRESP,valid_bytes
reg[(data_bus_width*axi_burst_len)-1:0] temp_read_data;
reg[(axi_rsp_width*axi_burst_len)-1:0] temp_read_rsp;
/* Read Data Channel handshake */
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN)begin
rd_fifo_rd_ptr <= 0;
rd_latency_count <= get_rd_lat_number(1);
rd_delayed = 0;
rresp_time_cnt <= 0;
rd_v_b = 0;
end else begin
if(arvalid_flag[rresp_time_cnt] && ((($time - arvalid_receive_time[rresp_time_cnt])/s_aclk_period) >= rd_latency_count)) begin
rd_delayed = 1;
end
if(!read_fifo_empty && rd_delayed)begin
rd_delayed = 0;
arvalid_flag[rresp_time_cnt] = 1'b0;
tmp_fifo_rd = read_fifo[rd_fifo_rd_ptr[int_cntr_width-2:0]];
rd_v_b = (tmp_fifo_rd[rd_afi_ln_msb : rd_afi_ln_lsb]+1)*(2**tmp_fifo_rd[rd_afi_siz_msb : rd_afi_siz_lsb]);
temp_read_data = tmp_fifo_rd[rd_afi_data_msb : rd_afi_data_lsb];
if(tmp_fifo_rd[rd_afi_brst_msb : rd_afi_brst_lsb] === AXI_WRAP) begin
get_wrap_aligned_rd_data(aligned_rd_data, tmp_fifo_rd[rd_afi_addr_msb : rd_afi_addr_lsb], tmp_fifo_rd[rd_afi_data_msb : rd_afi_data_lsb], rd_v_b);
temp_read_data = aligned_rd_data;
end
temp_read_rsp = 0;
repeat(axi_burst_len) begin
temp_read_rsp = temp_read_rsp >> axi_rsp_width;
temp_read_rsp[(axi_rsp_width*axi_burst_len)-1:(axi_rsp_width*axi_burst_len)-axi_rsp_width] = tmp_fifo_rd[rd_afi_rsp_msb : rd_afi_rsp_lsb];
end
slave.SEND_READ_BURST_RESP_CTRL(tmp_fifo_rd[rd_afi_id_msb : rd_afi_id_lsb],
tmp_fifo_rd[rd_afi_addr_msb : rd_afi_addr_lsb],
tmp_fifo_rd[rd_afi_ln_msb : rd_afi_ln_lsb],
tmp_fifo_rd[rd_afi_siz_msb : rd_afi_siz_lsb],
tmp_fifo_rd[rd_afi_brst_msb : rd_afi_brst_lsb],
temp_read_data,
temp_read_rsp);
rcount <= rcount - (tmp_fifo_rd[rd_afi_ln_msb : rd_afi_ln_lsb]+ 1) ;
rresp_time_cnt <= rresp_time_cnt+1;
rd_latency_count <= get_rd_lat_number(1);
rd_fifo_rd_ptr <= rd_fifo_rd_ptr+1;
end
end /// else
end /// always
endmodule
|
`timescale 1ns/1ns
module usb_tx_ack
(input c,
input start,
output [7:0] sie_d,
output sie_dv);
`include "usb_pids.v"
localparam ST_IDLE = 3'd0;
localparam ST_SYNC = 3'd1;
localparam ST_PID = 3'd2;
localparam SW=4, CW=2;
reg [CW+SW-1:0] ctrl;
wire [SW-1:0] state;
wire [SW-1:0] next_state = ctrl[SW+CW-1:CW];
r #(SW) state_r
(.c(c), .rst(1'b0), .en(1'b1), .d(next_state), .q(state));
wire sie_d_sel;
wire [7:0] sie_mux_z;
gmux #(.DWIDTH(8), .SELWIDTH(1)) sie_d_gmux
(.d({PID_ACK, 8'b10000000}), .sel(sie_d_sel), .z(sie_mux_z));
wire [7:0] sie_d_i = sie_dv_i ? sie_mux_z : 8'h0;
always @* begin
case (state)
ST_IDLE:
if (start) ctrl = { ST_SYNC , 2'b01 };
else ctrl = { ST_IDLE , 2'b00 };
ST_SYNC: ctrl = { ST_PID , 2'b11 };
ST_PID: ctrl = { ST_IDLE , 2'b00 };
default: ctrl = { ST_IDLE , 2'b00 };
endcase
end
wire sie_dv_i = ctrl[0];
assign sie_d_sel = ctrl[1];
// help timing a bit
d1 #(8) sie_d1_d_r (.c(c), .d(sie_d_i ), .q(sie_d ));
d1 sie_d1_dv_r(.c(c), .d(sie_dv_i), .q(sie_dv));
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:04:14 06/30/2012
// Design Name:
// Module Name: MIO_BUS
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module MIO_BUS(input clk,
input rst,
input[3:0]BTN,
input[15:0]SW,
input mem_w,
input[31:0]Cpu_data2bus, //data from CPU
input[31:0]addr_bus,
input[31:0]ram_data_out,
input[15:0]led_out,
input[31:0]counter_out,
input counter0_out,
input counter1_out,
input counter2_out,
output reg[31:0]Cpu_data4bus, //write to CPU
output reg[31:0]ram_data_in, //from CPU write to Memory
output reg[9:0]ram_addr, //Memory Address signals
output reg data_ram_we,
output reg GPIOf0000000_we,
output reg GPIOe0000000_we,
output reg counter_we,
output reg[31:0]Peripheral_in
);
endmodule
|
module StreamBuffer(
input rst_n,
input pclk,
input fclk,
input start,
input din_valid,
output din_ready,
input [7:0] din,
output [63:0] dout,
output dout_valid,
input dout_ready,
output burst_valid,
output [10:0] fifo_cnt
);
reg running;
`REG(pclk, running, 0, start ? 1 : running)
wire de2fifo_valid;
wire de2fifo_ready;
wire [63:0] de2fifo_data;
deserializer #(.INLOGBITS(3), .OUTLOGBITS(6)) inst_deserial(
.clk(pclk),
.rst_n(rst_n),
.in_valid(din_valid && running),
.in_ready(din_ready),
.in_data(din[7:0]),
.out_valid(de2fifo_valid),
.out_ready(de2fifo_ready),
.out_data(de2fifo_data)
);
wire vfifo_full;
wire vfifo_empty;
wire [8:0] vfifo_count;
fifo_64w_64r_512d sfifo_inst (
.rst(!rst_n), // input rst
.wr_clk(pclk), // input wr_clk
.rd_clk(fclk), // input rd_clk
.din(de2fifo_data[63:0]), // input [63 : 0] din
.wr_en(de2fifo_valid), // input wr_en
.rd_en(dout_ready), // input rd_en
.dout(dout), // output [63 : 0] dout
.full(vfifo_full), // output full
.empty(vfifo_empty), // output empty
.rd_data_count(vfifo_count), // output [8 : 0] rd_data_count
.wr_data_count() // output [8 : 0] wr_data_count
);
assign de2fifo_ready = !vfifo_full;
// I need to guarentee that 16 data entries are read out always
assign burst_valid = (vfifo_count > 9'd25);
assign dout_valid = !vfifo_empty;
assign fifo_cnt = vfifo_count;
endmodule // Conf
|
module hdUnit(
d_raddr1, d_raddr2, d_addrselector, d_jr_or_exec, d_immonly, d_opcode, e_isLoad, e_wreg,
//nop_alu_stall, nop_lw_stall, nop_sw_stall, // this doesn't seem to be required for this
pc_stall, ifid_stall, idex_stall, inst_stall,
write_done
);
// d_addrselector is lhb_llb_regcon, it gives addr fof [11:8] in raddr2 when 1 OR [7:4] in raddr2 when 0
// jal or exec is jal || exec
// ! (jal || exec) will indicate sw instruction
// d_immonly is 1 for instructions which only use immediates or offsets and don't need to be stalled
input [3:0] d_raddr1;
input [3:0] d_raddr2;
input d_addrselector;
input d_jr_or_exec;
input d_immonly;
input [3:0] d_opcode;
input e_isLoad;
input [3:0] e_wreg;
input write_done;
output pc_stall;
output ifid_stall;
output idex_stall;
output inst_stall;
//reg [1:0] stallCount;
/*always @ (*)
begin
stallCount = (e_isLoad===1'b1 && d_immonly!==1'b1 && (
(d_addrselector===1'b1 && d_jr_or_exec!==1'b1 && (d_raddr1===e_wreg || d_raddr2===e_wreg)) ||//Check if instr in d is sw and whether it needs a stall
(d_addrselector===1'b1 && d_jr_or_exec===1'b1 && (d_raddr2===e_wreg)) || // JR or exec
(d_addrselector!==1'b1 && (d_raddr1===e_wreg || d_raddr2===e_wreg))
)) ? 2'b111 : stallCount;
if(stallCount>3'b00) begin
pc_stall_temp = 1'b1;
ifid_stall_temp = 1'b1;
stallCount = stallCount-1'b1;
end
else begin
pc_stall_temp = 1'b0;
ifid_stall_temp = 1'b0;
end
end*/
/*wire temp_r1_w;
assign temp_r1_w = (d_raddr1===e_wreg);
assign pc_stall = (write_done === 1'b1)? 1'b0 :(e_isLoad===1'b1 && d_immonly!==1'b1 && e_wreg!==4'b000 && (
(temp_r1_w===1'b1) // load
)) ? 1'b1 : 1'b0;
assign ifid_stall = (write_done === 1'b1)? 1'b0 :(e_isLoad===1'b1 && d_immonly!==1'b1 && e_wreg!==4'b000 && (
(temp_r1_w===1'b1) // load
)) ? 1'b1 : 1'b0;
assign idex_stall = (write_done === 1'b1)? 1'b0 :(e_isLoad===1'b1 && d_immonly!==1'b1 && e_wreg!==4'b000 && (
(temp_r1_w===1'b1) // load
)) ? 1'b1 : 1'b0;*/
assign pc_stall = (write_done === 1'b1)? 1'b0 :(e_isLoad===1'b1 && d_immonly!==1'b1 && e_wreg!==4'b000 && (
(d_opcode!==4'b1000 && d_addrselector===1'b1 && d_jr_or_exec!==1'b1 && (d_raddr1===e_wreg || d_raddr2===e_wreg)) ||//Check if instr in d is sw and whether it needs a stall
(d_opcode!==4'b1000 && d_addrselector===1'b1 && d_jr_or_exec===1'b1 && (d_raddr2===e_wreg)) || // JR or exec
(d_opcode!==4'b1000 && d_addrselector!==1'b1 && (d_raddr1===e_wreg || d_raddr2===e_wreg)) || // arith
(d_opcode===4'b1000 && d_addrselector!==1'b1 && d_raddr1===e_wreg) // load
)) ? 1'b1 : 1'b0;
assign ifid_stall = (write_done === 1'b1)? 1'b0 :(e_isLoad===1'b1 && d_immonly!==1'b1 && e_wreg!==4'b000 && (
(d_opcode!==4'b1000 && d_addrselector===1'b1 && d_jr_or_exec!==1'b1 && (d_raddr1===e_wreg || d_raddr2===e_wreg)) ||//Check if instr in d is sw and whether it needs a stall
(d_opcode!==4'b1000 && d_addrselector===1'b1 && d_jr_or_exec===1'b1 && (d_raddr2===e_wreg)) || // JR or exec
(d_opcode!==4'b1000 && d_opcode!==4'b1000 && d_addrselector!==1'b1 && (d_raddr1===e_wreg || d_raddr2===e_wreg)) || // arith
(d_opcode===4'b1000 && d_addrselector!==1'b1 && d_raddr1===e_wreg) // load
)) ? 1'b1 : 1'b0;
assign idex_stall = (write_done === 1'b1)? 1'b0 :(e_isLoad===1'b1 && d_immonly!==1'b1 && e_wreg!==4'b000 && (
(d_opcode!==4'b1000 && d_addrselector===1'b1 && d_jr_or_exec!==1'b1 && (d_raddr1===e_wreg || d_raddr2===e_wreg)) ||//Check if instr in d is sw and whether it needs a stall
(d_opcode!==4'b1000 && d_addrselector===1'b1 && d_jr_or_exec===1'b1 && (d_raddr2===e_wreg)) || // JR or exec
(d_opcode!==4'b1000 && d_addrselector!==1'b1 && (d_raddr1===e_wreg || d_raddr2===e_wreg)) || // arith
(d_opcode===4'b1000 && d_addrselector!==1'b1 && d_raddr1===e_wreg) // load
)) ? 1'b1 : 1'b0;
assign inst_stall = (write_done === 1'b1)? 1'b0 :(e_isLoad===1'b1 && d_immonly!==1'b1 && e_wreg!==4'b000 && (
(d_opcode!==4'b1000 && d_addrselector===1'b1 && d_jr_or_exec!==1'b1 && (d_raddr1===e_wreg || d_raddr2===e_wreg)) ||//Check if instr in d is sw and whether it needs a stall
(d_opcode!==4'b1000 && d_addrselector===1'b1 && d_jr_or_exec===1'b1 && (d_raddr2===e_wreg)) || // JR or exec
(d_opcode!==4'b1000 && d_addrselector!==1'b1 && (d_raddr1===e_wreg || d_raddr2===e_wreg)) || // arith
(d_opcode===4'b1000 && d_addrselector!==1'b1 && d_raddr1===e_wreg) // load
)) ? 1'b1 : 1'b0;
/// NOP also has to sent through the whole pipeline 3 times
endmodule
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: fifo32_256.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 16.0.0 Build 211 04/27/2016 SJ Lite Edition
// ************************************************************
//Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus Prime License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo32_256 (
clock,
data,
rdreq,
sclr,
wrreq,
empty,
full,
q);
input clock;
input [31:0] data;
input rdreq;
input sclr;
input wrreq;
output empty;
output full;
output [31:0] q;
wire sub_wire0;
wire sub_wire1;
wire [31:0] sub_wire2;
wire empty = sub_wire0;
wire full = sub_wire1;
wire [31:0] q = sub_wire2[31:0];
scfifo scfifo_component (
.clock (clock),
.data (data),
.rdreq (rdreq),
.sclr (sclr),
.wrreq (wrreq),
.empty (sub_wire0),
.full (sub_wire1),
.q (sub_wire2),
.aclr (),
.almost_empty (),
.almost_full (),
.eccstatus (),
.usedw ());
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.intended_device_family = "Cyclone IV E",
scfifo_component.lpm_numwords = 256,
scfifo_component.lpm_showahead = "OFF",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 32,
scfifo_component.lpm_widthu = 8,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "256"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "0"
// Retrieval info: PRIVATE: Width NUMERIC "32"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "32"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "1"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: sclr 0 0 0 0 INPUT NODEFVAL "sclr"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_256.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_256.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_256.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_256.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_256_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_256_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW: Function scope handling
//
// D: Validate scope handling of variables
//
module main ();
reg [3:0] global_reg;
reg [3:0] result;
function [3:0] my_func ;
input [3:0] a;
reg [3:0] global_reg;
begin
global_reg = a + a;
my_func = a + a;
end
endfunction
initial
begin
global_reg = 2;
result = my_func(global_reg);
if(result != 4)
begin
$display("FAILED - function didn't function!\n");
$finish ;
end
if(global_reg != 2)
begin
$display("FAILED - function scope problem!\n");
$finish ;
end
$display("PASSED\n");
$finish ;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__OR3_BLACKBOX_V
`define SKY130_FD_SC_HVL__OR3_BLACKBOX_V
/**
* or3: 3-input OR.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__or3 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__OR3_BLACKBOX_V
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : bank_mach.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// Top level bank machine block. A structural block instantiating the configured
// individual bank machines, and a common block that computes various items shared
// by all bank machines.
`timescale 1ps/1ps
module mig_7series_v2_3_bank_mach #
(
parameter TCQ = 100,
parameter EVEN_CWL_2T_MODE = "OFF",
parameter ADDR_CMD_MODE = "1T",
parameter BANK_WIDTH = 3,
parameter BM_CNT_WIDTH = 2,
parameter BURST_MODE = "8",
parameter COL_WIDTH = 12,
parameter CS_WIDTH = 4,
parameter CL = 5,
parameter CWL = 5,
parameter DATA_BUF_ADDR_WIDTH = 8,
parameter DRAM_TYPE = "DDR3",
parameter EARLY_WR_DATA_ADDR = "OFF",
parameter ECC = "OFF",
parameter LOW_IDLE_CNT = 1,
parameter nBANK_MACHS = 4,
parameter nCK_PER_CLK = 2,
parameter nCS_PER_RANK = 1,
parameter nOP_WAIT = 0,
parameter nRAS = 20,
parameter nRCD = 5,
parameter nRFC = 44,
parameter nRTP = 4,
parameter CKE_ODT_AUX = "FALSE", //Parameter to turn on/off the aux_out signal
parameter nRP = 10,
parameter nSLOTS = 2,
parameter nWR = 6,
parameter nXSDLL = 512,
parameter ORDERING = "NORM",
parameter RANK_BM_BV_WIDTH = 16,
parameter RANK_WIDTH = 2,
parameter RANKS = 4,
parameter ROW_WIDTH = 16,
parameter RTT_NOM = "40",
parameter RTT_WR = "120",
parameter STARVE_LIMIT = 2,
parameter SLOT_0_CONFIG = 8'b0000_0101,
parameter SLOT_1_CONFIG = 8'b0000_1010,
parameter tZQCS = 64
)
(/*AUTOARG*/
// Outputs
output accept, // From bank_common0 of bank_common.v
output accept_ns, // From bank_common0 of bank_common.v
output [BM_CNT_WIDTH-1:0] bank_mach_next, // From bank_common0 of bank_common.v
output [ROW_WIDTH-1:0] col_a, // From arb_mux0 of arb_mux.v
output [BANK_WIDTH-1:0] col_ba, // From arb_mux0 of arb_mux.v
output [DATA_BUF_ADDR_WIDTH-1:0] col_data_buf_addr,// From arb_mux0 of arb_mux.v
output col_periodic_rd, // From arb_mux0 of arb_mux.v
output [RANK_WIDTH-1:0] col_ra, // From arb_mux0 of arb_mux.v
output col_rmw, // From arb_mux0 of arb_mux.v
output col_rd_wr,
output [ROW_WIDTH-1:0] col_row, // From arb_mux0 of arb_mux.v
output col_size, // From arb_mux0 of arb_mux.v
output [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr,// From arb_mux0 of arb_mux.v
output wire [nCK_PER_CLK-1:0] mc_ras_n,
output wire [nCK_PER_CLK-1:0] mc_cas_n,
output wire [nCK_PER_CLK-1:0] mc_we_n,
output wire [nCK_PER_CLK*ROW_WIDTH-1:0] mc_address,
output wire [nCK_PER_CLK*BANK_WIDTH-1:0] mc_bank,
output wire [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mc_cs_n,
output wire [1:0] mc_odt,
output wire [nCK_PER_CLK-1:0] mc_cke,
output wire [3:0] mc_aux_out0,
output wire [3:0] mc_aux_out1,
output [2:0] mc_cmd,
output [5:0] mc_data_offset,
output [5:0] mc_data_offset_1,
output [5:0] mc_data_offset_2,
output [1:0] mc_cas_slot,
output insert_maint_r1, // From arb_mux0 of arb_mux.v
output maint_wip_r, // From bank_common0 of bank_common.v
output wire [nBANK_MACHS-1:0] sending_row,
output wire [nBANK_MACHS-1:0] sending_col,
output wire sent_col,
output wire sent_col_r,
output periodic_rd_ack_r,
output wire [RANK_BM_BV_WIDTH-1:0] act_this_rank_r,
output wire [RANK_BM_BV_WIDTH-1:0] wr_this_rank_r,
output wire [RANK_BM_BV_WIDTH-1:0] rd_this_rank_r,
output wire [(RANKS*nBANK_MACHS)-1:0] rank_busy_r,
output idle,
// Inputs
input [BANK_WIDTH-1:0] bank, // To bank0 of bank_cntrl.v
input [6*RANKS-1:0] calib_rddata_offset,
input [6*RANKS-1:0] calib_rddata_offset_1,
input [6*RANKS-1:0] calib_rddata_offset_2,
input clk, // To bank0 of bank_cntrl.v, ...
input [2:0] cmd, // To bank0 of bank_cntrl.v, ...
input [COL_WIDTH-1:0] col, // To bank0 of bank_cntrl.v
input [DATA_BUF_ADDR_WIDTH-1:0] data_buf_addr,// To bank0 of bank_cntrl.v
input init_calib_complete, // To bank_common0 of bank_common.v
input phy_rddata_valid, // To bank0 of bank_cntrl.v
input dq_busy_data, // To bank0 of bank_cntrl.v
input hi_priority, // To bank0 of bank_cntrl.v, ...
input [RANKS-1:0] inhbt_act_faw_r, // To bank0 of bank_cntrl.v
input [RANKS-1:0] inhbt_rd, // To bank0 of bank_cntrl.v
input [RANKS-1:0] inhbt_wr, // To bank0 of bank_cntrl.v
input [RANK_WIDTH-1:0] maint_rank_r, // To bank0 of bank_cntrl.v, ...
input maint_req_r, // To bank0 of bank_cntrl.v, ...
input maint_zq_r, // To bank0 of bank_cntrl.v, ...
input maint_sre_r, // To bank0 of bank_cntrl.v, ...
input maint_srx_r, // To bank0 of bank_cntrl.v, ...
input periodic_rd_r, // To bank_common0 of bank_common.v
input [RANK_WIDTH-1:0] periodic_rd_rank_r, // To bank0 of bank_cntrl.v
input phy_mc_ctl_full,
input phy_mc_cmd_full,
input phy_mc_data_full,
input [RANK_WIDTH-1:0] rank, // To bank0 of bank_cntrl.v
input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr, // To bank0 of bank_cntrl.v
input rd_rmw, // To bank0 of bank_cntrl.v
input [ROW_WIDTH-1:0] row, // To bank0 of bank_cntrl.v
input rst, // To bank0 of bank_cntrl.v, ...
input size, // To bank0 of bank_cntrl.v
input [7:0] slot_0_present, // To bank_common0 of bank_common.v, ...
input [7:0] slot_1_present, // To bank_common0 of bank_common.v, ...
input use_addr
);
function integer clogb2 (input integer size); // ceiling logb2
begin
size = size - 1;
for (clogb2=1; size>1; clogb2=clogb2+1)
size = size >> 1;
end
endfunction // clogb2
localparam RANK_VECT_INDX = (nBANK_MACHS *RANK_WIDTH) - 1;
localparam BANK_VECT_INDX = (nBANK_MACHS * BANK_WIDTH) - 1;
localparam ROW_VECT_INDX = (nBANK_MACHS * ROW_WIDTH) - 1;
localparam DATA_BUF_ADDR_VECT_INDX = (nBANK_MACHS * DATA_BUF_ADDR_WIDTH) - 1;
localparam nRAS_CLKS = (nCK_PER_CLK == 1) ? nRAS : (nCK_PER_CLK == 2) ? ((nRAS/2) + (nRAS % 2)) : ((nRAS/4) + ((nRAS%4) ? 1 : 0));
localparam nWTP = CWL + ((BURST_MODE == "4") ? 2 : 4) + nWR;
// Unless 2T mode, add one to nWTP_CLKS for 2:1 mode. This accounts for loss of
// one DRAM CK due to column command to row command fixed offset. In 2T mode,
// Add the remainder. In 4:1 mode, the fixed offset is -2. Add 2 unless in 2T
// mode, in which case we add 1 if the remainder exceeds the fixed offset.
localparam nWTP_CLKS = (nCK_PER_CLK == 1)
? nWTP :
(nCK_PER_CLK == 2)
? (nWTP/2) + ((ADDR_CMD_MODE == "2T") ? nWTP%2 : 1) :
(nWTP/4) + ((ADDR_CMD_MODE == "2T") ? (nWTP%4 > 2 ? 2 : 1) : 2);
localparam RAS_TIMER_WIDTH = clogb2(((nRAS_CLKS > nWTP_CLKS)
? nRAS_CLKS
: nWTP_CLKS) - 1);
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire accept_internal_r; // From bank_common0 of bank_common.v
wire accept_req; // From bank_common0 of bank_common.v
wire adv_order_q; // From bank_common0 of bank_common.v
wire [BM_CNT_WIDTH-1:0] idle_cnt; // From bank_common0 of bank_common.v
wire insert_maint_r; // From bank_common0 of bank_common.v
wire low_idle_cnt_r; // From bank_common0 of bank_common.v
wire maint_idle; // From bank_common0 of bank_common.v
wire [BM_CNT_WIDTH-1:0] order_cnt; // From bank_common0 of bank_common.v
wire periodic_rd_insert; // From bank_common0 of bank_common.v
wire [BM_CNT_WIDTH-1:0] rb_hit_busy_cnt; // From bank_common0 of bank_common.v
wire sent_row; // From arb_mux0 of arb_mux.v
wire was_priority; // From bank_common0 of bank_common.v
wire was_wr; // From bank_common0 of bank_common.v
// End of automatics
wire [RANK_WIDTH-1:0] rnk_config;
wire rnk_config_strobe;
wire rnk_config_kill_rts_col;
wire rnk_config_valid_r;
wire [nBANK_MACHS-1:0] rts_row;
wire [nBANK_MACHS-1:0] rts_col;
wire [nBANK_MACHS-1:0] rts_pre;
wire [nBANK_MACHS-1:0] col_rdy_wr;
wire [nBANK_MACHS-1:0] rtc;
wire [nBANK_MACHS-1:0] sending_pre;
wire [DATA_BUF_ADDR_VECT_INDX:0] req_data_buf_addr_r;
wire [nBANK_MACHS-1:0] req_size_r;
wire [RANK_VECT_INDX:0] req_rank_r;
wire [BANK_VECT_INDX:0] req_bank_r;
wire [ROW_VECT_INDX:0] req_row_r;
wire [ROW_VECT_INDX:0] col_addr;
wire [nBANK_MACHS-1:0] req_periodic_rd_r;
wire [nBANK_MACHS-1:0] req_wr_r;
wire [nBANK_MACHS-1:0] rd_wr_r;
wire [nBANK_MACHS-1:0] req_ras;
wire [nBANK_MACHS-1:0] req_cas;
wire [ROW_VECT_INDX:0] row_addr;
wire [nBANK_MACHS-1:0] row_cmd_wr;
wire [nBANK_MACHS-1:0] demand_priority;
wire [nBANK_MACHS-1:0] demand_act_priority;
wire [nBANK_MACHS-1:0] idle_ns;
wire [nBANK_MACHS-1:0] rb_hit_busy_r;
wire [nBANK_MACHS-1:0] bm_end;
wire [nBANK_MACHS-1:0] passing_open_bank;
wire [nBANK_MACHS-1:0] ordered_r;
wire [nBANK_MACHS-1:0] ordered_issued;
wire [nBANK_MACHS-1:0] rb_hit_busy_ns;
wire [nBANK_MACHS-1:0] maint_hit;
wire [nBANK_MACHS-1:0] idle_r;
wire [nBANK_MACHS-1:0] head_r;
wire [nBANK_MACHS-1:0] start_rcd;
wire [nBANK_MACHS-1:0] end_rtp;
wire [nBANK_MACHS-1:0] op_exit_req;
wire [nBANK_MACHS-1:0] op_exit_grant;
wire [nBANK_MACHS-1:0] start_pre_wait;
wire [(RAS_TIMER_WIDTH*nBANK_MACHS)-1:0] ras_timer_ns;
genvar ID;
generate for (ID=0; ID<nBANK_MACHS; ID=ID+1) begin:bank_cntrl
mig_7series_v2_3_bank_cntrl #
(/*AUTOINSTPARAM*/
// Parameters
.TCQ (TCQ),
.ADDR_CMD_MODE (ADDR_CMD_MODE),
.BANK_WIDTH (BANK_WIDTH),
.BM_CNT_WIDTH (BM_CNT_WIDTH),
.BURST_MODE (BURST_MODE),
.COL_WIDTH (COL_WIDTH),
.CWL (CWL),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.DRAM_TYPE (DRAM_TYPE),
.ECC (ECC),
.ID (ID),
.nBANK_MACHS (nBANK_MACHS),
.nCK_PER_CLK (nCK_PER_CLK),
.nOP_WAIT (nOP_WAIT),
.nRAS_CLKS (nRAS_CLKS),
.nRCD (nRCD),
.nRTP (nRTP),
.nRP (nRP),
.nWTP_CLKS (nWTP_CLKS),
.ORDERING (ORDERING),
.RANK_WIDTH (RANK_WIDTH),
.RANKS (RANKS),
.RAS_TIMER_WIDTH (RAS_TIMER_WIDTH),
.ROW_WIDTH (ROW_WIDTH),
.STARVE_LIMIT (STARVE_LIMIT))
bank0
(.demand_priority (demand_priority[ID]),
.demand_priority_in ({2{demand_priority}}),
.demand_act_priority (demand_act_priority[ID]),
.demand_act_priority_in ({2{demand_act_priority}}),
.rts_row (rts_row[ID]),
.rts_col (rts_col[ID]),
.rts_pre (rts_pre[ID]),
.col_rdy_wr (col_rdy_wr[ID]),
.rtc (rtc[ID]),
.sending_row (sending_row[ID]),
.sending_pre (sending_pre[ID]),
.sending_col (sending_col[ID]),
.req_data_buf_addr_r (req_data_buf_addr_r[(ID*DATA_BUF_ADDR_WIDTH)+:DATA_BUF_ADDR_WIDTH]),
.req_size_r (req_size_r[ID]),
.req_rank_r (req_rank_r[(ID*RANK_WIDTH)+:RANK_WIDTH]),
.req_bank_r (req_bank_r[(ID*BANK_WIDTH)+:BANK_WIDTH]),
.req_row_r (req_row_r[(ID*ROW_WIDTH)+:ROW_WIDTH]),
.col_addr (col_addr[(ID*ROW_WIDTH)+:ROW_WIDTH]),
.req_wr_r (req_wr_r[ID]),
.rd_wr_r (rd_wr_r[ID]),
.req_periodic_rd_r (req_periodic_rd_r[ID]),
.req_ras (req_ras[ID]),
.req_cas (req_cas[ID]),
.row_addr (row_addr[(ID*ROW_WIDTH)+:ROW_WIDTH]),
.row_cmd_wr (row_cmd_wr[ID]),
.act_this_rank_r (act_this_rank_r[(ID*RANKS)+:RANKS]),
.wr_this_rank_r (wr_this_rank_r[(ID*RANKS)+:RANKS]),
.rd_this_rank_r (rd_this_rank_r[(ID*RANKS)+:RANKS]),
.idle_ns (idle_ns[ID]),
.rb_hit_busy_r (rb_hit_busy_r[ID]),
.bm_end (bm_end[ID]),
.bm_end_in ({2{bm_end}}),
.passing_open_bank (passing_open_bank[ID]),
.passing_open_bank_in ({2{passing_open_bank}}),
.ordered_r (ordered_r[ID]),
.ordered_issued (ordered_issued[ID]),
.rb_hit_busy_ns (rb_hit_busy_ns[ID]),
.rb_hit_busy_ns_in ({2{rb_hit_busy_ns}}),
.maint_hit (maint_hit[ID]),
.req_rank_r_in ({2{req_rank_r}}),
.idle_r (idle_r[ID]),
.head_r (head_r[ID]),
.start_rcd (start_rcd[ID]),
.start_rcd_in ({2{start_rcd}}),
.end_rtp (end_rtp[ID]),
.op_exit_req (op_exit_req[ID]),
.op_exit_grant (op_exit_grant[ID]),
.start_pre_wait (start_pre_wait[ID]),
.ras_timer_ns (ras_timer_ns[(ID*RAS_TIMER_WIDTH)+:RAS_TIMER_WIDTH]),
.ras_timer_ns_in ({2{ras_timer_ns}}),
.rank_busy_r (rank_busy_r[ID*RANKS+:RANKS]),
/*AUTOINST*/
// Inputs
.accept_internal_r (accept_internal_r),
.accept_req (accept_req),
.adv_order_q (adv_order_q),
.bank (bank[BANK_WIDTH-1:0]),
.clk (clk),
.cmd (cmd[2:0]),
.col (col[COL_WIDTH-1:0]),
.data_buf_addr (data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.phy_rddata_valid (phy_rddata_valid),
.dq_busy_data (dq_busy_data),
.hi_priority (hi_priority),
.idle_cnt (idle_cnt[BM_CNT_WIDTH-1:0]),
.inhbt_act_faw_r (inhbt_act_faw_r[RANKS-1:0]),
.inhbt_rd (inhbt_rd[RANKS-1:0]),
.inhbt_wr (inhbt_wr[RANKS-1:0]),
.rnk_config (rnk_config[RANK_WIDTH-1:0]),
.rnk_config_strobe (rnk_config_strobe),
.rnk_config_kill_rts_col (rnk_config_kill_rts_col),
.rnk_config_valid_r (rnk_config_valid_r),
.low_idle_cnt_r (low_idle_cnt_r),
.maint_idle (maint_idle),
.maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]),
.maint_req_r (maint_req_r),
.maint_zq_r (maint_zq_r),
.maint_sre_r (maint_sre_r),
.order_cnt (order_cnt[BM_CNT_WIDTH-1:0]),
.periodic_rd_ack_r (periodic_rd_ack_r),
.periodic_rd_insert (periodic_rd_insert),
.periodic_rd_rank_r (periodic_rd_rank_r[RANK_WIDTH-1:0]),
.phy_mc_cmd_full (phy_mc_cmd_full),
.phy_mc_ctl_full (phy_mc_ctl_full),
.phy_mc_data_full (phy_mc_data_full),
.rank (rank[RANK_WIDTH-1:0]),
.rb_hit_busy_cnt (rb_hit_busy_cnt[BM_CNT_WIDTH-1:0]),
.rd_data_addr (rd_data_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.rd_rmw (rd_rmw),
.row (row[ROW_WIDTH-1:0]),
.rst (rst),
.sent_col (sent_col),
.sent_row (sent_row),
.size (size),
.use_addr (use_addr),
.was_priority (was_priority),
.was_wr (was_wr));
end
endgenerate
mig_7series_v2_3_bank_common #
(/*AUTOINSTPARAM*/
// Parameters
.TCQ (TCQ),
.BM_CNT_WIDTH (BM_CNT_WIDTH),
.LOW_IDLE_CNT (LOW_IDLE_CNT),
.nBANK_MACHS (nBANK_MACHS),
.nCK_PER_CLK (nCK_PER_CLK),
.nOP_WAIT (nOP_WAIT),
.nRFC (nRFC),
.nXSDLL (nXSDLL),
.RANK_WIDTH (RANK_WIDTH),
.RANKS (RANKS),
.CWL (CWL),
.tZQCS (tZQCS))
bank_common0
(.op_exit_grant (op_exit_grant[nBANK_MACHS-1:0]),
/*AUTOINST*/
// Outputs
.accept_internal_r (accept_internal_r),
.accept_ns (accept_ns),
.accept (accept),
.periodic_rd_insert (periodic_rd_insert),
.periodic_rd_ack_r (periodic_rd_ack_r),
.accept_req (accept_req),
.rb_hit_busy_cnt (rb_hit_busy_cnt[BM_CNT_WIDTH-1:0]),
.idle_cnt (idle_cnt[BM_CNT_WIDTH-1:0]),
.idle (idle),
.order_cnt (order_cnt[BM_CNT_WIDTH-1:0]),
.adv_order_q (adv_order_q),
.bank_mach_next (bank_mach_next[BM_CNT_WIDTH-1:0]),
.low_idle_cnt_r (low_idle_cnt_r),
.was_wr (was_wr),
.was_priority (was_priority),
.maint_wip_r (maint_wip_r),
.maint_idle (maint_idle),
.insert_maint_r (insert_maint_r),
// Inputs
.clk (clk),
.rst (rst),
.idle_ns (idle_ns[nBANK_MACHS-1:0]),
.init_calib_complete (init_calib_complete),
.periodic_rd_r (periodic_rd_r),
.use_addr (use_addr),
.rb_hit_busy_r (rb_hit_busy_r[nBANK_MACHS-1:0]),
.idle_r (idle_r[nBANK_MACHS-1:0]),
.ordered_r (ordered_r[nBANK_MACHS-1:0]),
.ordered_issued (ordered_issued[nBANK_MACHS-1:0]),
.head_r (head_r[nBANK_MACHS-1:0]),
.end_rtp (end_rtp[nBANK_MACHS-1:0]),
.passing_open_bank (passing_open_bank[nBANK_MACHS-1:0]),
.op_exit_req (op_exit_req[nBANK_MACHS-1:0]),
.start_pre_wait (start_pre_wait[nBANK_MACHS-1:0]),
.cmd (cmd[2:0]),
.hi_priority (hi_priority),
.maint_req_r (maint_req_r),
.maint_zq_r (maint_zq_r),
.maint_sre_r (maint_sre_r),
.maint_srx_r (maint_srx_r),
.maint_hit (maint_hit[nBANK_MACHS-1:0]),
.bm_end (bm_end[nBANK_MACHS-1:0]),
.slot_0_present (slot_0_present[7:0]),
.slot_1_present (slot_1_present[7:0]));
mig_7series_v2_3_arb_mux #
(/*AUTOINSTPARAM*/
// Parameters
.TCQ (TCQ),
.EVEN_CWL_2T_MODE (EVEN_CWL_2T_MODE),
.ADDR_CMD_MODE (ADDR_CMD_MODE),
.BANK_VECT_INDX (BANK_VECT_INDX),
.BANK_WIDTH (BANK_WIDTH),
.BURST_MODE (BURST_MODE),
.CS_WIDTH (CS_WIDTH),
.CL (CL),
.CWL (CWL),
.DATA_BUF_ADDR_VECT_INDX (DATA_BUF_ADDR_VECT_INDX),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.DRAM_TYPE (DRAM_TYPE),
.EARLY_WR_DATA_ADDR (EARLY_WR_DATA_ADDR),
.ECC (ECC),
.nBANK_MACHS (nBANK_MACHS),
.nCK_PER_CLK (nCK_PER_CLK),
.nCS_PER_RANK (nCS_PER_RANK),
.nRAS (nRAS),
.nRCD (nRCD),
.CKE_ODT_AUX (CKE_ODT_AUX),
.nSLOTS (nSLOTS),
.nWR (nWR),
.RANKS (RANKS),
.RANK_VECT_INDX (RANK_VECT_INDX),
.RANK_WIDTH (RANK_WIDTH),
.ROW_VECT_INDX (ROW_VECT_INDX),
.ROW_WIDTH (ROW_WIDTH),
.RTT_NOM (RTT_NOM),
.RTT_WR (RTT_WR),
.SLOT_0_CONFIG (SLOT_0_CONFIG),
.SLOT_1_CONFIG (SLOT_1_CONFIG))
arb_mux0
(.rts_col (rts_col[nBANK_MACHS-1:0]), // AUTOs wants to make this an input.
/*AUTOINST*/
// Outputs
.col_a (col_a[ROW_WIDTH-1:0]),
.col_ba (col_ba[BANK_WIDTH-1:0]),
.col_data_buf_addr (col_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.col_periodic_rd (col_periodic_rd),
.col_ra (col_ra[RANK_WIDTH-1:0]),
.col_rmw (col_rmw),
.col_rd_wr (col_rd_wr),
.col_row (col_row[ROW_WIDTH-1:0]),
.col_size (col_size),
.col_wr_data_buf_addr (col_wr_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.mc_bank (mc_bank),
.mc_address (mc_address),
.mc_ras_n (mc_ras_n),
.mc_cas_n (mc_cas_n),
.mc_we_n (mc_we_n),
.mc_cs_n (mc_cs_n),
.mc_odt (mc_odt),
.mc_cke (mc_cke),
.mc_aux_out0 (mc_aux_out0),
.mc_aux_out1 (mc_aux_out1),
.mc_cmd (mc_cmd),
.mc_data_offset (mc_data_offset),
.mc_data_offset_1 (mc_data_offset_1),
.mc_data_offset_2 (mc_data_offset_2),
.rnk_config (rnk_config[RANK_WIDTH-1:0]),
.rnk_config_valid_r (rnk_config_valid_r),
.mc_cas_slot (mc_cas_slot),
.sending_row (sending_row[nBANK_MACHS-1:0]),
.sending_pre (sending_pre[nBANK_MACHS-1:0]),
.sent_col (sent_col),
.sent_col_r (sent_col_r),
.sent_row (sent_row),
.sending_col (sending_col[nBANK_MACHS-1:0]),
.rnk_config_strobe (rnk_config_strobe),
.rnk_config_kill_rts_col (rnk_config_kill_rts_col),
.insert_maint_r1 (insert_maint_r1),
// Inputs
.init_calib_complete (init_calib_complete),
.calib_rddata_offset (calib_rddata_offset),
.calib_rddata_offset_1 (calib_rddata_offset_1),
.calib_rddata_offset_2 (calib_rddata_offset_2),
.col_addr (col_addr[ROW_VECT_INDX:0]),
.col_rdy_wr (col_rdy_wr[nBANK_MACHS-1:0]),
.insert_maint_r (insert_maint_r),
.maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]),
.maint_zq_r (maint_zq_r),
.maint_sre_r (maint_sre_r),
.maint_srx_r (maint_srx_r),
.rd_wr_r (rd_wr_r[nBANK_MACHS-1:0]),
.req_bank_r (req_bank_r[BANK_VECT_INDX:0]),
.req_cas (req_cas[nBANK_MACHS-1:0]),
.req_data_buf_addr_r (req_data_buf_addr_r[DATA_BUF_ADDR_VECT_INDX:0]),
.req_periodic_rd_r (req_periodic_rd_r[nBANK_MACHS-1:0]),
.req_rank_r (req_rank_r[RANK_VECT_INDX:0]),
.req_ras (req_ras[nBANK_MACHS-1:0]),
.req_row_r (req_row_r[ROW_VECT_INDX:0]),
.req_size_r (req_size_r[nBANK_MACHS-1:0]),
.req_wr_r (req_wr_r[nBANK_MACHS-1:0]),
.row_addr (row_addr[ROW_VECT_INDX:0]),
.row_cmd_wr (row_cmd_wr[nBANK_MACHS-1:0]),
.rts_row (rts_row[nBANK_MACHS-1:0]),
.rtc (rtc[nBANK_MACHS-1:0]),
.rts_pre (rts_pre[nBANK_MACHS-1:0]),
.slot_0_present (slot_0_present[7:0]),
.slot_1_present (slot_1_present[7:0]),
.clk (clk),
.rst (rst));
endmodule // bank_mach
|
//Copyright (C) 1991-2003 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
module bustri (
data,
enabledt,
tridata);
input [15:0] data;
input enabledt;
inout [15:0] tridata;
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2014 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2014.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / / _no_description_
// /___/ /\ Filename : RXTX_BITSLICE.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
//
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module RXTX_BITSLICE #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter ENABLE_PRE_EMPHASIS = "FALSE",
parameter FIFO_SYNC_MODE = "FALSE",
parameter [0:0] INIT = 1'b1,
parameter [0:0] IS_RX_CLK_INVERTED = 1'b0,
parameter [0:0] IS_RX_RST_DLY_INVERTED = 1'b0,
parameter [0:0] IS_RX_RST_INVERTED = 1'b0,
parameter [0:0] IS_TX_CLK_INVERTED = 1'b0,
parameter [0:0] IS_TX_RST_DLY_INVERTED = 1'b0,
parameter [0:0] IS_TX_RST_INVERTED = 1'b0,
parameter LOOPBACK = "FALSE",
parameter NATIVE_ODELAY_BYPASS = "FALSE",
parameter RX_DATA_TYPE = "DATA",
parameter integer RX_DATA_WIDTH = 8,
parameter RX_DELAY_FORMAT = "TIME",
parameter RX_DELAY_TYPE = "FIXED",
parameter integer RX_DELAY_VALUE = 0,
parameter real RX_REFCLK_FREQUENCY = 300.0,
parameter RX_UPDATE_MODE = "ASYNC",
parameter real SIM_VERSION = 2.0,
parameter TBYTE_CTL = "TBYTE_IN",
parameter integer TX_DATA_WIDTH = 8,
parameter TX_DELAY_FORMAT = "TIME",
parameter TX_DELAY_TYPE = "FIXED",
parameter integer TX_DELAY_VALUE = 0,
parameter TX_OUTPUT_PHASE_90 = "FALSE",
parameter real TX_REFCLK_FREQUENCY = 300.0,
parameter TX_UPDATE_MODE = "ASYNC"
)(
output FIFO_EMPTY,
output FIFO_WRCLK_OUT,
output O,
output [7:0] Q,
output [39:0] RX_BIT_CTRL_OUT,
output [8:0] RX_CNTVALUEOUT,
output [39:0] TX_BIT_CTRL_OUT,
output [8:0] TX_CNTVALUEOUT,
output T_OUT,
input [7:0] D,
input DATAIN,
input FIFO_RD_CLK,
input FIFO_RD_EN,
input [39:0] RX_BIT_CTRL_IN,
input RX_CE,
input RX_CLK,
input [8:0] RX_CNTVALUEIN,
input RX_EN_VTC,
input RX_INC,
input RX_LOAD,
input RX_RST,
input RX_RST_DLY,
input T,
input TBYTE_IN,
input [39:0] TX_BIT_CTRL_IN,
input TX_CE,
input TX_CLK,
input [8:0] TX_CNTVALUEIN,
input TX_EN_VTC,
input TX_INC,
input TX_LOAD,
input TX_RST,
input TX_RST_DLY
);
// define constants
localparam MODULE_NAME = "RXTX_BITSLICE";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
// include dynamic registers - XILINX test only
reg trig_attr = 1'b0;
`ifdef XIL_DR
`include "RXTX_BITSLICE_dr.v"
`else
localparam [40:1] ENABLE_PRE_EMPHASIS_REG = ENABLE_PRE_EMPHASIS;
localparam [40:1] FIFO_SYNC_MODE_REG = FIFO_SYNC_MODE;
localparam [0:0] INIT_REG = INIT;
localparam [0:0] IS_RX_CLK_INVERTED_REG = IS_RX_CLK_INVERTED;
localparam [0:0] IS_RX_RST_DLY_INVERTED_REG = IS_RX_RST_DLY_INVERTED;
localparam [0:0] IS_RX_RST_INVERTED_REG = IS_RX_RST_INVERTED;
localparam [0:0] IS_TX_CLK_INVERTED_REG = IS_TX_CLK_INVERTED;
localparam [0:0] IS_TX_RST_DLY_INVERTED_REG = IS_TX_RST_DLY_INVERTED;
localparam [0:0] IS_TX_RST_INVERTED_REG = IS_TX_RST_INVERTED;
localparam [40:1] LOOPBACK_REG = LOOPBACK;
localparam [40:1] NATIVE_ODELAY_BYPASS_REG = NATIVE_ODELAY_BYPASS;
localparam [112:1] RX_DATA_TYPE_REG = RX_DATA_TYPE;
localparam [3:0] RX_DATA_WIDTH_REG = RX_DATA_WIDTH;
localparam [40:1] RX_DELAY_FORMAT_REG = RX_DELAY_FORMAT;
localparam [64:1] RX_DELAY_TYPE_REG = RX_DELAY_TYPE;
localparam [10:0] RX_DELAY_VALUE_REG = RX_DELAY_VALUE;
localparam real RX_REFCLK_FREQUENCY_REG = RX_REFCLK_FREQUENCY;
localparam [48:1] RX_UPDATE_MODE_REG = RX_UPDATE_MODE;
localparam real SIM_VERSION_REG = SIM_VERSION;
localparam [64:1] TBYTE_CTL_REG = TBYTE_CTL;
localparam [3:0] TX_DATA_WIDTH_REG = TX_DATA_WIDTH;
localparam [40:1] TX_DELAY_FORMAT_REG = TX_DELAY_FORMAT;
localparam [64:1] TX_DELAY_TYPE_REG = TX_DELAY_TYPE;
localparam [10:0] TX_DELAY_VALUE_REG = TX_DELAY_VALUE;
localparam [40:1] TX_OUTPUT_PHASE_90_REG = TX_OUTPUT_PHASE_90;
localparam real TX_REFCLK_FREQUENCY_REG = TX_REFCLK_FREQUENCY;
localparam [48:1] TX_UPDATE_MODE_REG = TX_UPDATE_MODE;
`endif
localparam [40:1] DDR_DIS_DQS_REG = "TRUE";
localparam [0:0] RX_DC_ADJ_EN_REG = 1'b0;
localparam [2:0] RX_FDLY_REG = 3'b010;
localparam [40:1] RX_Q4_ROUTETHRU_REG = "FALSE";
localparam [40:1] RX_Q5_ROUTETHRU_REG = "FALSE";
localparam [40:1] TXRX_LOOPBACK_REG = "FALSE";
localparam [0:0] TX_DC_ADJ_EN_REG = 1'b0;
localparam [2:0] TX_FDLY_REG = 3'b010;
localparam [40:1] TX_Q_ROUTETHRU_REG = "FALSE";
localparam [40:1] TX_T_OUT_ROUTETHRU_REG = "FALSE";
localparam [40:1] XIPHY_BITSLICE_MODE_REG = "TRUE";
wire IS_RX_CLK_INVERTED_BIN;
wire IS_RX_RST_DLY_INVERTED_BIN;
wire IS_RX_RST_INVERTED_BIN;
wire IS_TX_CLK_INVERTED_BIN;
wire IS_TX_RST_DLY_INVERTED_BIN;
wire IS_TX_RST_INVERTED_BIN;
wire [63:0] RX_REFCLK_FREQUENCY_BIN;
wire [63:0] SIM_VERSION_BIN;
wire [63:0] TX_REFCLK_FREQUENCY_BIN;
`ifdef XIL_ATTR_TEST
reg attr_test = 1'b1;
`else
reg attr_test = 1'b0;
`endif
reg attr_err = 1'b0;
tri0 glblGSR = glbl.GSR;
wire IDELAY_DATAIN0_out;
wire IDELAY_DATAOUT_out;
wire ODELAY_DATAIN0_out;
wire ODELAY_DATAOUT_out;
wire FIFO_EMPTY_out;
wire FIFO_WRCLK_OUT_out;
wire O_out;
wire TX2RX_CASC_OUT_out;
wire T_OUT_out;
wire [39:0] RX_BIT_CTRL_OUT_out;
wire [39:0] TX_BIT_CTRL_OUT_out;
wire [7:0] Q_out;
wire [8:0] RX_CNTVALUEOUT_out;
wire [8:0] TX_CNTVALUEOUT_out;
wire FIFO_EMPTY_delay;
wire FIFO_WRCLK_OUT_delay;
wire O_delay;
wire T_OUT_delay;
wire [39:0] RX_BIT_CTRL_OUT_delay;
wire [39:0] TX_BIT_CTRL_OUT_delay;
wire [7:0] Q_delay;
wire [8:0] RX_CNTVALUEOUT_delay;
wire [8:0] TX_CNTVALUEOUT_delay;
wire DATAIN_in;
wire FIFO_RD_CLK_in;
wire FIFO_RD_EN_in;
wire IFD_CE_in;
wire OFD_CE_in;
wire RX2TX_CASC_RETURN_IN_in;
wire RX_CE_in;
wire RX_CLKDIV_in;
wire RX_CLK_C_B_in;
wire RX_CLK_C_in;
wire RX_CLK_in;
wire RX_DATAIN1_in;
wire RX_EN_VTC_in;
wire RX_INC_in;
wire RX_LOAD_in;
wire RX_RST_DLY_in;
wire RX_RST_in;
wire TBYTE_IN_in;
wire TX2RX_CASC_IN_in;
wire TX_CE_in;
wire TX_CLK_in;
wire TX_EN_VTC_in;
wire TX_INC_in;
wire TX_LOAD_in;
wire TX_OCLKDIV_in;
wire TX_OCLK_in;
wire TX_RST_DLY_in;
wire TX_RST_in;
wire T_in;
wire [39:0] RX_BIT_CTRL_IN_in;
wire [39:0] TX_BIT_CTRL_IN_in;
wire [7:0] D_in;
wire [8:0] RX_CNTVALUEIN_in;
wire [8:0] TX_CNTVALUEIN_in;
wire DATAIN_delay;
wire FIFO_RD_CLK_delay;
wire FIFO_RD_EN_delay;
wire RX_CE_delay;
wire RX_CLK_delay;
wire RX_EN_VTC_delay;
wire RX_INC_delay;
wire RX_LOAD_delay;
wire RX_RST_DLY_delay;
wire RX_RST_delay;
wire TBYTE_IN_delay;
wire TX_CE_delay;
wire TX_CLK_delay;
wire TX_EN_VTC_delay;
wire TX_INC_delay;
wire TX_LOAD_delay;
wire TX_RST_DLY_delay;
wire TX_RST_delay;
wire T_delay;
wire [39:0] RX_BIT_CTRL_IN_delay;
wire [39:0] TX_BIT_CTRL_IN_delay;
wire [7:0] D_delay;
wire [8:0] RX_CNTVALUEIN_delay;
wire [8:0] TX_CNTVALUEIN_delay;
assign #(out_delay) FIFO_EMPTY = FIFO_EMPTY_delay;
assign #(out_delay) FIFO_WRCLK_OUT = FIFO_WRCLK_OUT_delay;
assign #(out_delay) O = O_delay;
assign #(out_delay) Q = Q_delay;
assign #(out_delay) RX_BIT_CTRL_OUT = RX_BIT_CTRL_OUT_delay;
assign #(out_delay) RX_CNTVALUEOUT = (RX_EN_VTC_in === 1'b1) ? 9'bxxxxxxxxx : RX_CNTVALUEOUT_delay;
assign #(out_delay) TX_BIT_CTRL_OUT = TX_BIT_CTRL_OUT_delay;
assign #(out_delay) TX_CNTVALUEOUT = (TX_EN_VTC_in === 1'b1) ? 9'bxxxxxxxxx : TX_CNTVALUEOUT_delay;
assign #(out_delay) T_OUT = T_OUT_delay;
`ifdef XIL_TIMING
reg notifier;
`endif
`ifndef XIL_TIMING // inputs with timing checks
assign #(inclk_delay) FIFO_RD_CLK_delay = FIFO_RD_CLK;
assign #(inclk_delay) RX_CLK_delay = RX_CLK;
assign #(inclk_delay) TX_CLK_delay = TX_CLK;
assign #(in_delay) D_delay = D;
assign #(in_delay) FIFO_RD_EN_delay = FIFO_RD_EN;
assign #(in_delay) RX_CE_delay = RX_CE;
assign #(in_delay) RX_CNTVALUEIN_delay = RX_CNTVALUEIN;
assign #(in_delay) RX_INC_delay = RX_INC;
assign #(in_delay) RX_LOAD_delay = RX_LOAD;
assign #(in_delay) TX_CE_delay = TX_CE;
assign #(in_delay) TX_CNTVALUEIN_delay = TX_CNTVALUEIN;
assign #(in_delay) TX_INC_delay = TX_INC;
assign #(in_delay) TX_LOAD_delay = TX_LOAD;
`endif
// inputs with no timing checks
assign #(in_delay) DATAIN_delay = DATAIN;
assign #(in_delay) RX_BIT_CTRL_IN_delay = RX_BIT_CTRL_IN;
assign #(in_delay) RX_EN_VTC_delay = RX_EN_VTC;
assign #(in_delay) RX_RST_DLY_delay = RX_RST_DLY;
assign #(in_delay) RX_RST_delay = RX_RST;
assign #(in_delay) TBYTE_IN_delay = TBYTE_IN;
assign #(in_delay) TX_BIT_CTRL_IN_delay = TX_BIT_CTRL_IN;
assign #(in_delay) TX_EN_VTC_delay = TX_EN_VTC;
assign #(in_delay) TX_RST_DLY_delay = TX_RST_DLY;
assign #(in_delay) TX_RST_delay = TX_RST;
assign #(in_delay) T_delay = T;
assign FIFO_EMPTY_delay = FIFO_EMPTY_out;
assign FIFO_WRCLK_OUT_delay = FIFO_WRCLK_OUT_out;
assign O_delay = O_out;
assign Q_delay = Q_out;
assign RX_BIT_CTRL_OUT_delay = RX_BIT_CTRL_OUT_out;
assign RX_CNTVALUEOUT_delay = RX_CNTVALUEOUT_out;
assign TX_BIT_CTRL_OUT_delay = TX_BIT_CTRL_OUT_out;
assign TX_CNTVALUEOUT_delay = TX_CNTVALUEOUT_out;
assign T_OUT_delay = T_OUT_out;
assign DATAIN_in = DATAIN_delay;
assign D_in = D_delay;
assign FIFO_RD_CLK_in = FIFO_RD_CLK_delay;
assign FIFO_RD_EN_in = FIFO_RD_EN_delay;
assign RX_BIT_CTRL_IN_in = RX_BIT_CTRL_IN_delay;
assign RX_CE_in = RX_CE_delay;
assign RX_CLK_in = RX_CLK_delay ^ IS_RX_CLK_INVERTED_BIN;
assign RX_CNTVALUEIN_in = RX_CNTVALUEIN_delay;
assign RX_EN_VTC_in = RX_EN_VTC_delay;
assign RX_INC_in = RX_INC_delay;
assign RX_LOAD_in = RX_LOAD_delay;
assign RX_RST_DLY_in = RX_RST_DLY_delay ^ IS_RX_RST_DLY_INVERTED_BIN;
assign RX_RST_in = RX_RST_delay ^ IS_RX_RST_INVERTED_BIN;
assign TBYTE_IN_in = TBYTE_IN_delay;
assign TX_BIT_CTRL_IN_in = TX_BIT_CTRL_IN_delay;
assign TX_CE_in = TX_CE_delay;
assign TX_CLK_in = TX_CLK_delay ^ IS_TX_CLK_INVERTED_BIN;
assign TX_CNTVALUEIN_in = TX_CNTVALUEIN_delay;
assign TX_EN_VTC_in = TX_EN_VTC_delay;
assign TX_INC_in = TX_INC_delay;
assign TX_LOAD_in = TX_LOAD_delay;
assign TX_RST_DLY_in = TX_RST_DLY_delay ^ IS_TX_RST_DLY_INVERTED_BIN;
assign TX_RST_in = TX_RST_delay ^ IS_TX_RST_INVERTED_BIN;
assign T_in = T_delay;
assign IS_RX_CLK_INVERTED_BIN = IS_RX_CLK_INVERTED_REG;
assign IS_RX_RST_DLY_INVERTED_BIN = IS_RX_RST_DLY_INVERTED_REG;
assign IS_RX_RST_INVERTED_BIN = IS_RX_RST_INVERTED_REG;
assign IS_TX_CLK_INVERTED_BIN = IS_TX_CLK_INVERTED_REG;
assign IS_TX_RST_DLY_INVERTED_BIN = IS_TX_RST_DLY_INVERTED_REG;
assign IS_TX_RST_INVERTED_BIN = IS_TX_RST_INVERTED_REG;
assign RX_REFCLK_FREQUENCY_BIN = RX_REFCLK_FREQUENCY_REG * 1000;
assign SIM_VERSION_BIN = SIM_VERSION_REG * 1000;
assign TX_REFCLK_FREQUENCY_BIN = TX_REFCLK_FREQUENCY_REG * 1000;
initial begin
#1;
trig_attr = ~trig_attr;
end
always @ (trig_attr) begin
#1;
if ((attr_test == 1'b1) ||
((ENABLE_PRE_EMPHASIS_REG != "FALSE") &&
(ENABLE_PRE_EMPHASIS_REG != "TRUE"))) begin
$display("Error: [Unisim %s-102] ENABLE_PRE_EMPHASIS attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, ENABLE_PRE_EMPHASIS_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((FIFO_SYNC_MODE_REG != "FALSE") &&
(FIFO_SYNC_MODE_REG != "TRUE"))) begin
$display("Error: [Unisim %s-103] FIFO_SYNC_MODE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, FIFO_SYNC_MODE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_REG !== 1'b0) && (INIT_REG !== 1'b1))) begin
$display("Error: [Unisim %s-104] INIT attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, INIT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((IS_RX_CLK_INVERTED_REG !== 1'b0) && (IS_RX_CLK_INVERTED_REG !== 1'b1))) begin
$display("Error: [Unisim %s-105] IS_RX_CLK_INVERTED attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, IS_RX_CLK_INVERTED_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((IS_RX_RST_DLY_INVERTED_REG !== 1'b0) && (IS_RX_RST_DLY_INVERTED_REG !== 1'b1))) begin
$display("Error: [Unisim %s-106] IS_RX_RST_DLY_INVERTED attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, IS_RX_RST_DLY_INVERTED_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((IS_RX_RST_INVERTED_REG !== 1'b0) && (IS_RX_RST_INVERTED_REG !== 1'b1))) begin
$display("Error: [Unisim %s-107] IS_RX_RST_INVERTED attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, IS_RX_RST_INVERTED_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((IS_TX_CLK_INVERTED_REG !== 1'b0) && (IS_TX_CLK_INVERTED_REG !== 1'b1))) begin
$display("Error: [Unisim %s-108] IS_TX_CLK_INVERTED attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, IS_TX_CLK_INVERTED_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((IS_TX_RST_DLY_INVERTED_REG !== 1'b0) && (IS_TX_RST_DLY_INVERTED_REG !== 1'b1))) begin
$display("Error: [Unisim %s-109] IS_TX_RST_DLY_INVERTED attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, IS_TX_RST_DLY_INVERTED_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((IS_TX_RST_INVERTED_REG !== 1'b0) && (IS_TX_RST_INVERTED_REG !== 1'b1))) begin
$display("Error: [Unisim %s-110] IS_TX_RST_INVERTED attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, IS_TX_RST_INVERTED_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((LOOPBACK_REG != "FALSE") &&
(LOOPBACK_REG != "TRUE"))) begin
$display("Error: [Unisim %s-111] LOOPBACK attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, LOOPBACK_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((NATIVE_ODELAY_BYPASS_REG != "FALSE") &&
(NATIVE_ODELAY_BYPASS_REG != "TRUE"))) begin
$display("Error: [Unisim %s-112] NATIVE_ODELAY_BYPASS attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, NATIVE_ODELAY_BYPASS_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_DATA_TYPE_REG != "CLOCK") &&
(RX_DATA_TYPE_REG != "DATA") &&
(RX_DATA_TYPE_REG != "DATA_AND_CLOCK") &&
(RX_DATA_TYPE_REG != "SERIAL"))) begin
$display("Error: [Unisim %s-113] RX_DATA_TYPE attribute is set to %s. Legal values for this attribute are CLOCK, DATA, DATA_AND_CLOCK or SERIAL. Instance: %m", MODULE_NAME, RX_DATA_TYPE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_DATA_WIDTH_REG != 8) &&
(RX_DATA_WIDTH_REG != 4))) begin
$display("Error: [Unisim %s-114] RX_DATA_WIDTH attribute is set to %d. Legal values for this attribute are 8 or 4. Instance: %m", MODULE_NAME, RX_DATA_WIDTH_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_DELAY_FORMAT_REG != "TIME") &&
(RX_DELAY_FORMAT_REG != "COUNT"))) begin
$display("Error: [Unisim %s-116] RX_DELAY_FORMAT attribute is set to %s. Legal values for this attribute are TIME or COUNT. Instance: %m", MODULE_NAME, RX_DELAY_FORMAT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_DELAY_TYPE_REG != "FIXED") &&
(RX_DELAY_TYPE_REG != "VARIABLE") &&
(RX_DELAY_TYPE_REG != "VAR_LOAD"))) begin
$display("Error: [Unisim %s-117] RX_DELAY_TYPE attribute is set to %s. Legal values for this attribute are FIXED, VARIABLE or VAR_LOAD. Instance: %m", MODULE_NAME, RX_DELAY_TYPE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_DELAY_VALUE_REG < 0) || (RX_DELAY_VALUE_REG > 1250))) begin
$display("Error: [Unisim %s-118] RX_DELAY_VALUE attribute is set to %d. Legal values for this attribute are 0 to 1250. Instance: %m", MODULE_NAME, RX_DELAY_VALUE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_UPDATE_MODE_REG != "ASYNC") &&
(RX_UPDATE_MODE_REG != "MANUAL") &&
(RX_UPDATE_MODE_REG != "SYNC"))) begin
$display("Error: [Unisim %s-123] RX_UPDATE_MODE attribute is set to %s. Legal values for this attribute are ASYNC, MANUAL or SYNC. Instance: %m", MODULE_NAME, RX_UPDATE_MODE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TBYTE_CTL_REG != "TBYTE_IN") &&
(TBYTE_CTL_REG != "T"))) begin
$display("Error: [Unisim %s-125] TBYTE_CTL attribute is set to %s. Legal values for this attribute are TBYTE_IN or T. Instance: %m", MODULE_NAME, TBYTE_CTL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_DATA_WIDTH_REG != 8) &&
(TX_DATA_WIDTH_REG != 4))) begin
$display("Error: [Unisim %s-127] TX_DATA_WIDTH attribute is set to %d. Legal values for this attribute are 8 or 4. Instance: %m", MODULE_NAME, TX_DATA_WIDTH_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_DELAY_FORMAT_REG != "TIME") &&
(TX_DELAY_FORMAT_REG != "COUNT"))) begin
$display("Error: [Unisim %s-129] TX_DELAY_FORMAT attribute is set to %s. Legal values for this attribute are TIME or COUNT. Instance: %m", MODULE_NAME, TX_DELAY_FORMAT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_DELAY_TYPE_REG != "FIXED") &&
(TX_DELAY_TYPE_REG != "VARIABLE") &&
(TX_DELAY_TYPE_REG != "VAR_LOAD"))) begin
$display("Error: [Unisim %s-130] TX_DELAY_TYPE attribute is set to %s. Legal values for this attribute are FIXED, VARIABLE or VAR_LOAD. Instance: %m", MODULE_NAME, TX_DELAY_TYPE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_DELAY_VALUE_REG < 0) || (TX_DELAY_VALUE_REG > 1250))) begin
$display("Error: [Unisim %s-131] TX_DELAY_VALUE attribute is set to %d. Legal values for this attribute are 0 to 1250. Instance: %m", MODULE_NAME, TX_DELAY_VALUE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_OUTPUT_PHASE_90_REG != "FALSE") &&
(TX_OUTPUT_PHASE_90_REG != "TRUE"))) begin
$display("Error: [Unisim %s-133] TX_OUTPUT_PHASE_90 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, TX_OUTPUT_PHASE_90_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_UPDATE_MODE_REG != "ASYNC") &&
(TX_UPDATE_MODE_REG != "MANUAL") &&
(TX_UPDATE_MODE_REG != "SYNC"))) begin
$display("Error: [Unisim %s-137] TX_UPDATE_MODE attribute is set to %s. Legal values for this attribute are ASYNC, MANUAL or SYNC. Instance: %m", MODULE_NAME, TX_UPDATE_MODE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SIM_VERSION_REG != 2.0) &&
(SIM_VERSION_REG != 1.0))) begin
$display("Error: [Unisim %s-124] SIM_VERSION attribute is set to %f. Legal values for this attribute are 2.0 or 1.0. Instance: %m", MODULE_NAME, SIM_VERSION_REG);
attr_err = 1'b1;
end
if (RX_REFCLK_FREQUENCY_REG < 200.0 || RX_REFCLK_FREQUENCY_REG > 2400.0) begin
$display("Error: [Unisim %s-122] RX_REFCLK_FREQUENCY attribute is set to %f. Legal values for this attribute are 200.0 to 2400.0. Instance: %m", MODULE_NAME, RX_REFCLK_FREQUENCY_REG);
attr_err = 1'b1;
end
if (TX_REFCLK_FREQUENCY_REG < 200.0 || TX_REFCLK_FREQUENCY_REG > 2400.0) begin
$display("Error: [Unisim %s-135] TX_REFCLK_FREQUENCY attribute is set to %f. Legal values for this attribute are 200.0 to 2400.0. Instance: %m", MODULE_NAME, TX_REFCLK_FREQUENCY_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) $finish;
end
assign RX_CLKDIV_in = 1'b1; // tie off
assign RX_CLK_C_B_in = 1'b1; // tie off
assign RX_CLK_C_in = 1'b1; // tie off
assign TX_OCLKDIV_in = 1'b1; // tie off
assign TX_OCLK_in = 1'b1; // tie off
assign IFD_CE_in = 1'b0; // tie off
assign OFD_CE_in = 1'b0; // tie off
assign RX2TX_CASC_RETURN_IN_in = 1'b1; // tie off
assign RX_DATAIN1_in = 1'b0; // tie off
assign TX2RX_CASC_IN_in = 1'b1; // tie off
generate
if (SIM_VERSION == 2.0) begin : generate_block1
SIP_RXTX_BITSLICE_K2 SIP_RXTX_BITSLICE_INST (
.DDR_DIS_DQS (DDR_DIS_DQS_REG),
.ENABLE_PRE_EMPHASIS (ENABLE_PRE_EMPHASIS_REG),
.FIFO_SYNC_MODE (FIFO_SYNC_MODE_REG),
.INIT (INIT_REG),
.LOOPBACK (LOOPBACK_REG),
.NATIVE_ODELAY_BYPASS (NATIVE_ODELAY_BYPASS_REG),
.RX_DATA_TYPE (RX_DATA_TYPE_REG),
.RX_DATA_WIDTH (RX_DATA_WIDTH_REG),
.RX_DC_ADJ_EN (RX_DC_ADJ_EN_REG),
.RX_DELAY_FORMAT (RX_DELAY_FORMAT_REG),
.RX_DELAY_TYPE (RX_DELAY_TYPE_REG),
.RX_DELAY_VALUE (RX_DELAY_VALUE_REG),
.RX_FDLY (RX_FDLY_REG),
.RX_Q4_ROUTETHRU (RX_Q4_ROUTETHRU_REG),
.RX_Q5_ROUTETHRU (RX_Q5_ROUTETHRU_REG),
.RX_REFCLK_FREQUENCY (RX_REFCLK_FREQUENCY_BIN),
.RX_UPDATE_MODE (RX_UPDATE_MODE_REG),
.SIM_VERSION (SIM_VERSION_BIN),
.TBYTE_CTL (TBYTE_CTL_REG),
.TXRX_LOOPBACK (TXRX_LOOPBACK_REG),
.TX_DATA_WIDTH (TX_DATA_WIDTH_REG),
.TX_DC_ADJ_EN (TX_DC_ADJ_EN_REG),
.TX_DELAY_FORMAT (TX_DELAY_FORMAT_REG),
.TX_DELAY_TYPE (TX_DELAY_TYPE_REG),
.TX_DELAY_VALUE (TX_DELAY_VALUE_REG),
.TX_FDLY (TX_FDLY_REG),
.TX_OUTPUT_PHASE_90 (TX_OUTPUT_PHASE_90_REG),
.TX_Q_ROUTETHRU (TX_Q_ROUTETHRU_REG),
.TX_REFCLK_FREQUENCY (TX_REFCLK_FREQUENCY_BIN),
.TX_T_OUT_ROUTETHRU (TX_T_OUT_ROUTETHRU_REG),
.TX_UPDATE_MODE (TX_UPDATE_MODE_REG),
.XIPHY_BITSLICE_MODE (XIPHY_BITSLICE_MODE_REG),
.FIFO_EMPTY (FIFO_EMPTY_out),
.FIFO_WRCLK_OUT (FIFO_WRCLK_OUT_out),
.O (O_out),
.Q (Q_out),
.RX_BIT_CTRL_OUT (RX_BIT_CTRL_OUT_out),
.RX_CNTVALUEOUT (RX_CNTVALUEOUT_out),
.TX2RX_CASC_OUT (TX2RX_CASC_OUT_out),
.TX_BIT_CTRL_OUT (TX_BIT_CTRL_OUT_out),
.TX_CNTVALUEOUT (TX_CNTVALUEOUT_out),
.T_OUT (T_OUT_out),
.D (D_in),
.DATAIN (DATAIN_in),
.FIFO_RD_CLK (FIFO_RD_CLK_in),
.FIFO_RD_EN (FIFO_RD_EN_in),
.IFD_CE (IFD_CE_in),
.OFD_CE (OFD_CE_in),
.RX2TX_CASC_RETURN_IN (RX2TX_CASC_RETURN_IN_in),
.RX_BIT_CTRL_IN (RX_BIT_CTRL_IN_in),
.RX_CE (RX_CE_in),
.RX_CLK (RX_CLK_in),
.RX_CLKDIV (RX_CLKDIV_in),
.RX_CLK_C (RX_CLK_C_in),
.RX_CLK_C_B (RX_CLK_C_B_in),
.RX_CNTVALUEIN (RX_CNTVALUEIN_in),
.RX_DATAIN1 (RX_DATAIN1_in),
.RX_EN_VTC (RX_EN_VTC_in),
.RX_INC (RX_INC_in),
.RX_LOAD (RX_LOAD_in),
.RX_RST (RX_RST_in),
.RX_RST_DLY (RX_RST_DLY_in),
.T (T_in),
.TBYTE_IN (TBYTE_IN_in),
.TX2RX_CASC_IN (TX2RX_CASC_IN_in),
.TX_BIT_CTRL_IN (TX_BIT_CTRL_IN_in),
.TX_CE (TX_CE_in),
.TX_CLK (TX_CLK_in),
.TX_CNTVALUEIN (TX_CNTVALUEIN_in),
.TX_EN_VTC (TX_EN_VTC_in),
.TX_INC (TX_INC_in),
.TX_LOAD (TX_LOAD_in),
.TX_OCLK (TX_OCLK_in),
.TX_OCLKDIV (TX_OCLKDIV_in),
.TX_RST (TX_RST_in),
.TX_RST_DLY (TX_RST_DLY_in),
.SIM_IDELAY_DATAIN0(IDELAY_DATAIN0_out),
.SIM_IDELAY_DATAOUT(IDELAY_DATAOUT_out),
.SIM_ODELAY_DATAIN0(ODELAY_DATAIN0_out),
.SIM_ODELAY_DATAOUT(ODELAY_DATAOUT_out),
.GSR (glblGSR)
);
end else begin : generate_block1
SIP_RXTX_BITSLICE SIP_RXTX_BITSLICE_INST (
.DDR_DIS_DQS (DDR_DIS_DQS_REG),
.ENABLE_PRE_EMPHASIS (ENABLE_PRE_EMPHASIS_REG),
.FIFO_SYNC_MODE (FIFO_SYNC_MODE_REG),
.INIT (INIT_REG),
.LOOPBACK (LOOPBACK_REG),
.NATIVE_ODELAY_BYPASS (NATIVE_ODELAY_BYPASS_REG),
.RX_DATA_TYPE (RX_DATA_TYPE_REG),
.RX_DATA_WIDTH (RX_DATA_WIDTH_REG),
.RX_DC_ADJ_EN (RX_DC_ADJ_EN_REG),
.RX_DELAY_FORMAT (RX_DELAY_FORMAT_REG),
.RX_DELAY_TYPE (RX_DELAY_TYPE_REG),
.RX_DELAY_VALUE (RX_DELAY_VALUE_REG),
.RX_FDLY (RX_FDLY_REG),
.RX_Q4_ROUTETHRU (RX_Q4_ROUTETHRU_REG),
.RX_Q5_ROUTETHRU (RX_Q5_ROUTETHRU_REG),
.RX_REFCLK_FREQUENCY (RX_REFCLK_FREQUENCY_BIN),
.RX_UPDATE_MODE (RX_UPDATE_MODE_REG),
.SIM_VERSION (SIM_VERSION_BIN),
.TBYTE_CTL (TBYTE_CTL_REG),
.TXRX_LOOPBACK (TXRX_LOOPBACK_REG),
.TX_DATA_WIDTH (TX_DATA_WIDTH_REG),
.TX_DC_ADJ_EN (TX_DC_ADJ_EN_REG),
.TX_DELAY_FORMAT (TX_DELAY_FORMAT_REG),
.TX_DELAY_TYPE (TX_DELAY_TYPE_REG),
.TX_DELAY_VALUE (TX_DELAY_VALUE_REG),
.TX_FDLY (TX_FDLY_REG),
.TX_OUTPUT_PHASE_90 (TX_OUTPUT_PHASE_90_REG),
.TX_Q_ROUTETHRU (TX_Q_ROUTETHRU_REG),
.TX_REFCLK_FREQUENCY (TX_REFCLK_FREQUENCY_BIN),
.TX_T_OUT_ROUTETHRU (TX_T_OUT_ROUTETHRU_REG),
.TX_UPDATE_MODE (TX_UPDATE_MODE_REG),
.XIPHY_BITSLICE_MODE (XIPHY_BITSLICE_MODE_REG),
.FIFO_EMPTY (FIFO_EMPTY_out),
.FIFO_WRCLK_OUT (FIFO_WRCLK_OUT_out),
.O (O_out),
.Q (Q_out),
.RX_BIT_CTRL_OUT (RX_BIT_CTRL_OUT_out),
.RX_CNTVALUEOUT (RX_CNTVALUEOUT_out),
.TX2RX_CASC_OUT (TX2RX_CASC_OUT_out),
.TX_BIT_CTRL_OUT (TX_BIT_CTRL_OUT_out),
.TX_CNTVALUEOUT (TX_CNTVALUEOUT_out),
.T_OUT (T_OUT_out),
.D (D_in),
.DATAIN (DATAIN_in),
.FIFO_RD_CLK (FIFO_RD_CLK_in),
.FIFO_RD_EN (FIFO_RD_EN_in),
.IFD_CE (IFD_CE_in),
.OFD_CE (OFD_CE_in),
.RX2TX_CASC_RETURN_IN (RX2TX_CASC_RETURN_IN_in),
.RX_BIT_CTRL_IN (RX_BIT_CTRL_IN_in),
.RX_CE (RX_CE_in),
.RX_CLK (RX_CLK_in),
.RX_CLKDIV (RX_CLKDIV_in),
.RX_CLK_C (RX_CLK_C_in),
.RX_CLK_C_B (RX_CLK_C_B_in),
.RX_CNTVALUEIN (RX_CNTVALUEIN_in),
.RX_DATAIN1 (RX_DATAIN1_in),
.RX_EN_VTC (RX_EN_VTC_in),
.RX_INC (RX_INC_in),
.RX_LOAD (RX_LOAD_in),
.RX_RST (RX_RST_in),
.RX_RST_DLY (RX_RST_DLY_in),
.T (T_in),
.TBYTE_IN (TBYTE_IN_in),
.TX2RX_CASC_IN (TX2RX_CASC_IN_in),
.TX_BIT_CTRL_IN (TX_BIT_CTRL_IN_in),
.TX_CE (TX_CE_in),
.TX_CLK (TX_CLK_in),
.TX_CNTVALUEIN (TX_CNTVALUEIN_in),
.TX_EN_VTC (TX_EN_VTC_in),
.TX_INC (TX_INC_in),
.TX_LOAD (TX_LOAD_in),
.TX_OCLK (TX_OCLK_in),
.TX_OCLKDIV (TX_OCLKDIV_in),
.TX_RST (TX_RST_in),
.TX_RST_DLY (TX_RST_DLY_in),
.SIM_IDELAY_DATAIN0(IDELAY_DATAIN0_out),
.SIM_IDELAY_DATAOUT(IDELAY_DATAOUT_out),
.SIM_ODELAY_DATAIN0(ODELAY_DATAIN0_out),
.SIM_ODELAY_DATAOUT(ODELAY_DATAOUT_out),
.GSR (glblGSR)
);
end
endgenerate
specify
(DATAIN => Q[4]) = (0:0:0, 0:0:0);
(DATAIN => Q[5]) = (0:0:0, 0:0:0);
(DATAIN => RX_BIT_CTRL_OUT[9]) = (0:0:0, 0:0:0);
(D[0] => O) = (0:0:0, 0:0:0);
(D[1] => T_OUT) = (0:0:0, 0:0:0);
(FIFO_RD_CLK => FIFO_EMPTY) = (0:0:0, 0:0:0);
(FIFO_RD_CLK => Q[0]) = (0:0:0, 0:0:0);
(FIFO_RD_CLK => Q[1]) = (0:0:0, 0:0:0);
(FIFO_RD_CLK => Q[2]) = (0:0:0, 0:0:0);
(FIFO_RD_CLK => Q[3]) = (0:0:0, 0:0:0);
(FIFO_RD_CLK => Q[4]) = (0:0:0, 0:0:0);
(FIFO_RD_CLK => Q[5]) = (0:0:0, 0:0:0);
(FIFO_RD_CLK => Q[6]) = (0:0:0, 0:0:0);
(FIFO_RD_CLK => Q[7]) = (0:0:0, 0:0:0);
(RX_BIT_CTRL_IN[20] => FIFO_WRCLK_OUT) = (0:0:0, 0:0:0);
(RX_CLK => RX_CNTVALUEOUT[0]) = (0:0:0, 0:0:0);
(RX_CLK => RX_CNTVALUEOUT[1]) = (0:0:0, 0:0:0);
(RX_CLK => RX_CNTVALUEOUT[2]) = (0:0:0, 0:0:0);
(RX_CLK => RX_CNTVALUEOUT[3]) = (0:0:0, 0:0:0);
(RX_CLK => RX_CNTVALUEOUT[4]) = (0:0:0, 0:0:0);
(RX_CLK => RX_CNTVALUEOUT[5]) = (0:0:0, 0:0:0);
(RX_CLK => RX_CNTVALUEOUT[6]) = (0:0:0, 0:0:0);
(RX_CLK => RX_CNTVALUEOUT[7]) = (0:0:0, 0:0:0);
(RX_CLK => RX_CNTVALUEOUT[8]) = (0:0:0, 0:0:0);
(TX_CLK => TX_CNTVALUEOUT[0]) = (0:0:0, 0:0:0);
(TX_CLK => TX_CNTVALUEOUT[1]) = (0:0:0, 0:0:0);
(TX_CLK => TX_CNTVALUEOUT[2]) = (0:0:0, 0:0:0);
(TX_CLK => TX_CNTVALUEOUT[3]) = (0:0:0, 0:0:0);
(TX_CLK => TX_CNTVALUEOUT[4]) = (0:0:0, 0:0:0);
(TX_CLK => TX_CNTVALUEOUT[5]) = (0:0:0, 0:0:0);
(TX_CLK => TX_CNTVALUEOUT[6]) = (0:0:0, 0:0:0);
(TX_CLK => TX_CNTVALUEOUT[7]) = (0:0:0, 0:0:0);
(TX_CLK => TX_CNTVALUEOUT[8]) = (0:0:0, 0:0:0);
`ifdef XIL_TIMING
$period (negedge FIFO_RD_CLK, 0:0:0, notifier);
$period (negedge RX_BIT_CTRL_IN[20], 0:0:0, notifier);
$period (negedge RX_CLK, 0:0:0, notifier);
$period (negedge TX_BIT_CTRL_IN[25], 0:0:0, notifier);
$period (negedge TX_BIT_CTRL_IN[26], 0:0:0, notifier);
$period (negedge TX_CLK, 0:0:0, notifier);
$period (posedge FIFO_RD_CLK, 0:0:0, notifier);
$period (posedge RX_BIT_CTRL_IN[20], 0:0:0, notifier);
$period (posedge RX_CLK, 0:0:0, notifier);
$period (posedge TX_BIT_CTRL_IN[25], 0:0:0, notifier);
$period (posedge TX_BIT_CTRL_IN[26], 0:0:0, notifier);
$period (posedge TX_CLK, 0:0:0, notifier);
$recrem ( negedge RX_CE, negedge RX_CLK, 0:0:0, 0:0:0, notifier,,, RX_CE_delay, RX_CLK_delay);
$recrem ( negedge RX_CE, posedge RX_CLK, 0:0:0, 0:0:0, notifier,,, RX_CE_delay, RX_CLK_delay);
$recrem ( negedge RX_LOAD, negedge RX_CLK, 0:0:0, 0:0:0, notifier,,, RX_LOAD_delay, RX_CLK_delay);
$recrem ( negedge RX_LOAD, posedge RX_CLK, 0:0:0, 0:0:0, notifier,,, RX_LOAD_delay, RX_CLK_delay);
$recrem ( negedge TX_CE, negedge TX_CLK, 0:0:0, 0:0:0, notifier,,, TX_CE_delay, TX_CLK_delay);
$recrem ( negedge TX_CE, posedge TX_CLK, 0:0:0, 0:0:0, notifier,,, TX_CE_delay, TX_CLK_delay);
$recrem ( negedge TX_LOAD, negedge TX_CLK, 0:0:0, 0:0:0, notifier,,, TX_LOAD_delay, TX_CLK_delay);
$recrem ( negedge TX_LOAD, posedge TX_CLK, 0:0:0, 0:0:0, notifier,,, TX_LOAD_delay, TX_CLK_delay);
$recrem ( posedge RX_CE, negedge RX_CLK, 0:0:0, 0:0:0, notifier,,, RX_CE_delay, RX_CLK_delay);
$recrem ( posedge RX_CE, posedge RX_CLK, 0:0:0, 0:0:0, notifier,,, RX_CE_delay, RX_CLK_delay);
$recrem ( posedge RX_LOAD, negedge RX_CLK, 0:0:0, 0:0:0, notifier,,, RX_LOAD_delay, RX_CLK_delay);
$recrem ( posedge RX_LOAD, posedge RX_CLK, 0:0:0, 0:0:0, notifier,,, RX_LOAD_delay, RX_CLK_delay);
$recrem ( posedge TX_CE, negedge TX_CLK, 0:0:0, 0:0:0, notifier,,, TX_CE_delay, TX_CLK_delay);
$recrem ( posedge TX_CE, posedge TX_CLK, 0:0:0, 0:0:0, notifier,,, TX_CE_delay, TX_CLK_delay);
$recrem ( posedge TX_LOAD, negedge TX_CLK, 0:0:0, 0:0:0, notifier,,, TX_LOAD_delay, TX_CLK_delay);
$recrem ( posedge TX_LOAD, posedge TX_CLK, 0:0:0, 0:0:0, notifier,,, TX_LOAD_delay, TX_CLK_delay);
$setuphold (negedge RX_CLK, negedge RX_CE, 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, RX_CE_delay);
$setuphold (negedge RX_CLK, negedge RX_CNTVALUEIN[0], 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, RX_CNTVALUEIN_delay[0]);
$setuphold (negedge RX_CLK, negedge RX_CNTVALUEIN[1], 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, RX_CNTVALUEIN_delay[1]);
$setuphold (negedge RX_CLK, negedge RX_CNTVALUEIN[2], 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, RX_CNTVALUEIN_delay[2]);
$setuphold (negedge RX_CLK, negedge RX_CNTVALUEIN[3], 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, RX_CNTVALUEIN_delay[3]);
$setuphold (negedge RX_CLK, negedge RX_CNTVALUEIN[4], 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, RX_CNTVALUEIN_delay[4]);
$setuphold (negedge RX_CLK, negedge RX_CNTVALUEIN[5], 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, RX_CNTVALUEIN_delay[5]);
$setuphold (negedge RX_CLK, negedge RX_CNTVALUEIN[6], 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, RX_CNTVALUEIN_delay[6]);
$setuphold (negedge RX_CLK, negedge RX_CNTVALUEIN[7], 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, RX_CNTVALUEIN_delay[7]);
$setuphold (negedge RX_CLK, negedge RX_CNTVALUEIN[8], 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, RX_CNTVALUEIN_delay[8]);
$setuphold (negedge RX_CLK, negedge RX_INC, 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, RX_INC_delay);
$setuphold (negedge RX_CLK, negedge RX_LOAD, 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, RX_LOAD_delay);
$setuphold (negedge RX_CLK, posedge RX_CE, 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, RX_CE_delay);
$setuphold (negedge RX_CLK, posedge RX_CNTVALUEIN[0], 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, RX_CNTVALUEIN_delay[0]);
$setuphold (negedge RX_CLK, posedge RX_CNTVALUEIN[1], 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, RX_CNTVALUEIN_delay[1]);
$setuphold (negedge RX_CLK, posedge RX_CNTVALUEIN[2], 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, RX_CNTVALUEIN_delay[2]);
$setuphold (negedge RX_CLK, posedge RX_CNTVALUEIN[3], 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, RX_CNTVALUEIN_delay[3]);
$setuphold (negedge RX_CLK, posedge RX_CNTVALUEIN[4], 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, RX_CNTVALUEIN_delay[4]);
$setuphold (negedge RX_CLK, posedge RX_CNTVALUEIN[5], 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, RX_CNTVALUEIN_delay[5]);
$setuphold (negedge RX_CLK, posedge RX_CNTVALUEIN[6], 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, RX_CNTVALUEIN_delay[6]);
$setuphold (negedge RX_CLK, posedge RX_CNTVALUEIN[7], 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, RX_CNTVALUEIN_delay[7]);
$setuphold (negedge RX_CLK, posedge RX_CNTVALUEIN[8], 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, RX_CNTVALUEIN_delay[8]);
$setuphold (negedge RX_CLK, posedge RX_INC, 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, RX_INC_delay);
$setuphold (negedge RX_CLK, posedge RX_LOAD, 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, RX_LOAD_delay);
$setuphold (negedge TX_BIT_CTRL_IN[25], negedge D[0], 0:0:0, 0:0:0, notifier,,, TX_BIT_CTRL_IN_delay[25], D_delay[0]);
$setuphold (negedge TX_BIT_CTRL_IN[25], negedge D[1], 0:0:0, 0:0:0, notifier,,, TX_BIT_CTRL_IN_delay[25], D_delay[1]);
$setuphold (negedge TX_BIT_CTRL_IN[25], negedge D[2], 0:0:0, 0:0:0, notifier,,, TX_BIT_CTRL_IN_delay[25], D_delay[2]);
$setuphold (negedge TX_BIT_CTRL_IN[25], negedge D[3], 0:0:0, 0:0:0, notifier,,, TX_BIT_CTRL_IN_delay[25], D_delay[3]);
$setuphold (negedge TX_BIT_CTRL_IN[25], posedge D[0], 0:0:0, 0:0:0, notifier,,, TX_BIT_CTRL_IN_delay[25], D_delay[0]);
$setuphold (negedge TX_BIT_CTRL_IN[25], posedge D[1], 0:0:0, 0:0:0, notifier,,, TX_BIT_CTRL_IN_delay[25], D_delay[1]);
$setuphold (negedge TX_BIT_CTRL_IN[25], posedge D[2], 0:0:0, 0:0:0, notifier,,, TX_BIT_CTRL_IN_delay[25], D_delay[2]);
$setuphold (negedge TX_BIT_CTRL_IN[25], posedge D[3], 0:0:0, 0:0:0, notifier,,, TX_BIT_CTRL_IN_delay[25], D_delay[3]);
$setuphold (negedge TX_CLK, negedge TX_CE, 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_CE_delay);
$setuphold (negedge TX_CLK, negedge TX_CNTVALUEIN[0], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_CNTVALUEIN_delay[0]);
$setuphold (negedge TX_CLK, negedge TX_CNTVALUEIN[1], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_CNTVALUEIN_delay[1]);
$setuphold (negedge TX_CLK, negedge TX_CNTVALUEIN[2], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_CNTVALUEIN_delay[2]);
$setuphold (negedge TX_CLK, negedge TX_CNTVALUEIN[3], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_CNTVALUEIN_delay[3]);
$setuphold (negedge TX_CLK, negedge TX_CNTVALUEIN[4], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_CNTVALUEIN_delay[4]);
$setuphold (negedge TX_CLK, negedge TX_CNTVALUEIN[5], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_CNTVALUEIN_delay[5]);
$setuphold (negedge TX_CLK, negedge TX_CNTVALUEIN[6], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_CNTVALUEIN_delay[6]);
$setuphold (negedge TX_CLK, negedge TX_CNTVALUEIN[7], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_CNTVALUEIN_delay[7]);
$setuphold (negedge TX_CLK, negedge TX_CNTVALUEIN[8], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_CNTVALUEIN_delay[8]);
$setuphold (negedge TX_CLK, negedge TX_INC, 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_INC_delay);
$setuphold (negedge TX_CLK, negedge TX_LOAD, 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_LOAD_delay);
$setuphold (negedge TX_CLK, posedge TX_CE, 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_CE_delay);
$setuphold (negedge TX_CLK, posedge TX_CNTVALUEIN[0], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_CNTVALUEIN_delay[0]);
$setuphold (negedge TX_CLK, posedge TX_CNTVALUEIN[1], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_CNTVALUEIN_delay[1]);
$setuphold (negedge TX_CLK, posedge TX_CNTVALUEIN[2], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_CNTVALUEIN_delay[2]);
$setuphold (negedge TX_CLK, posedge TX_CNTVALUEIN[3], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_CNTVALUEIN_delay[3]);
$setuphold (negedge TX_CLK, posedge TX_CNTVALUEIN[4], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_CNTVALUEIN_delay[4]);
$setuphold (negedge TX_CLK, posedge TX_CNTVALUEIN[5], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_CNTVALUEIN_delay[5]);
$setuphold (negedge TX_CLK, posedge TX_CNTVALUEIN[6], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_CNTVALUEIN_delay[6]);
$setuphold (negedge TX_CLK, posedge TX_CNTVALUEIN[7], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_CNTVALUEIN_delay[7]);
$setuphold (negedge TX_CLK, posedge TX_CNTVALUEIN[8], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_CNTVALUEIN_delay[8]);
$setuphold (negedge TX_CLK, posedge TX_INC, 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_INC_delay);
$setuphold (negedge TX_CLK, posedge TX_LOAD, 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_LOAD_delay);
$setuphold (posedge FIFO_RD_CLK, negedge FIFO_RD_EN, 0:0:0, 0:0:0, notifier,,, FIFO_RD_CLK_delay, FIFO_RD_EN_delay);
$setuphold (posedge FIFO_RD_CLK, posedge FIFO_RD_EN, 0:0:0, 0:0:0, notifier,,, FIFO_RD_CLK_delay, FIFO_RD_EN_delay);
$setuphold (posedge RX_CLK, negedge RX_CE, 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, RX_CE_delay);
$setuphold (posedge RX_CLK, negedge RX_CNTVALUEIN[0], 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, RX_CNTVALUEIN_delay[0]);
$setuphold (posedge RX_CLK, negedge RX_CNTVALUEIN[1], 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, RX_CNTVALUEIN_delay[1]);
$setuphold (posedge RX_CLK, negedge RX_CNTVALUEIN[2], 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, RX_CNTVALUEIN_delay[2]);
$setuphold (posedge RX_CLK, negedge RX_CNTVALUEIN[3], 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, RX_CNTVALUEIN_delay[3]);
$setuphold (posedge RX_CLK, negedge RX_CNTVALUEIN[4], 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, RX_CNTVALUEIN_delay[4]);
$setuphold (posedge RX_CLK, negedge RX_CNTVALUEIN[5], 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, RX_CNTVALUEIN_delay[5]);
$setuphold (posedge RX_CLK, negedge RX_CNTVALUEIN[6], 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, RX_CNTVALUEIN_delay[6]);
$setuphold (posedge RX_CLK, negedge RX_CNTVALUEIN[7], 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, RX_CNTVALUEIN_delay[7]);
$setuphold (posedge RX_CLK, negedge RX_CNTVALUEIN[8], 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, RX_CNTVALUEIN_delay[8]);
$setuphold (posedge RX_CLK, negedge RX_INC, 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, RX_INC_delay);
$setuphold (posedge RX_CLK, negedge RX_LOAD, 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, RX_LOAD_delay);
$setuphold (posedge RX_CLK, posedge RX_CE, 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, RX_CE_delay);
$setuphold (posedge RX_CLK, posedge RX_CNTVALUEIN[0], 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, RX_CNTVALUEIN_delay[0]);
$setuphold (posedge RX_CLK, posedge RX_CNTVALUEIN[1], 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, RX_CNTVALUEIN_delay[1]);
$setuphold (posedge RX_CLK, posedge RX_CNTVALUEIN[2], 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, RX_CNTVALUEIN_delay[2]);
$setuphold (posedge RX_CLK, posedge RX_CNTVALUEIN[3], 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, RX_CNTVALUEIN_delay[3]);
$setuphold (posedge RX_CLK, posedge RX_CNTVALUEIN[4], 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, RX_CNTVALUEIN_delay[4]);
$setuphold (posedge RX_CLK, posedge RX_CNTVALUEIN[5], 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, RX_CNTVALUEIN_delay[5]);
$setuphold (posedge RX_CLK, posedge RX_CNTVALUEIN[6], 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, RX_CNTVALUEIN_delay[6]);
$setuphold (posedge RX_CLK, posedge RX_CNTVALUEIN[7], 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, RX_CNTVALUEIN_delay[7]);
$setuphold (posedge RX_CLK, posedge RX_CNTVALUEIN[8], 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, RX_CNTVALUEIN_delay[8]);
$setuphold (posedge RX_CLK, posedge RX_INC, 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, RX_INC_delay);
$setuphold (posedge RX_CLK, posedge RX_LOAD, 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, RX_LOAD_delay);
$setuphold (posedge TX_BIT_CTRL_IN[26], negedge D[0], 0:0:0, 0:0:0, notifier,,, TX_BIT_CTRL_IN_delay[26], D_delay[0]);
$setuphold (posedge TX_BIT_CTRL_IN[26], negedge D[1], 0:0:0, 0:0:0, notifier,,, TX_BIT_CTRL_IN_delay[26], D_delay[1]);
$setuphold (posedge TX_BIT_CTRL_IN[26], negedge D[2], 0:0:0, 0:0:0, notifier,,, TX_BIT_CTRL_IN_delay[26], D_delay[2]);
$setuphold (posedge TX_BIT_CTRL_IN[26], negedge D[3], 0:0:0, 0:0:0, notifier,,, TX_BIT_CTRL_IN_delay[26], D_delay[3]);
$setuphold (posedge TX_BIT_CTRL_IN[26], negedge D[4], 0:0:0, 0:0:0, notifier,,, TX_BIT_CTRL_IN_delay[26], D_delay[4]);
$setuphold (posedge TX_BIT_CTRL_IN[26], negedge D[5], 0:0:0, 0:0:0, notifier,,, TX_BIT_CTRL_IN_delay[26], D_delay[5]);
$setuphold (posedge TX_BIT_CTRL_IN[26], negedge D[6], 0:0:0, 0:0:0, notifier,,, TX_BIT_CTRL_IN_delay[26], D_delay[6]);
$setuphold (posedge TX_BIT_CTRL_IN[26], negedge D[7], 0:0:0, 0:0:0, notifier,,, TX_BIT_CTRL_IN_delay[26], D_delay[7]);
$setuphold (posedge TX_BIT_CTRL_IN[26], posedge D[0], 0:0:0, 0:0:0, notifier,,, TX_BIT_CTRL_IN_delay[26], D_delay[0]);
$setuphold (posedge TX_BIT_CTRL_IN[26], posedge D[1], 0:0:0, 0:0:0, notifier,,, TX_BIT_CTRL_IN_delay[26], D_delay[1]);
$setuphold (posedge TX_BIT_CTRL_IN[26], posedge D[2], 0:0:0, 0:0:0, notifier,,, TX_BIT_CTRL_IN_delay[26], D_delay[2]);
$setuphold (posedge TX_BIT_CTRL_IN[26], posedge D[3], 0:0:0, 0:0:0, notifier,,, TX_BIT_CTRL_IN_delay[26], D_delay[3]);
$setuphold (posedge TX_BIT_CTRL_IN[26], posedge D[4], 0:0:0, 0:0:0, notifier,,, TX_BIT_CTRL_IN_delay[26], D_delay[4]);
$setuphold (posedge TX_BIT_CTRL_IN[26], posedge D[5], 0:0:0, 0:0:0, notifier,,, TX_BIT_CTRL_IN_delay[26], D_delay[5]);
$setuphold (posedge TX_BIT_CTRL_IN[26], posedge D[6], 0:0:0, 0:0:0, notifier,,, TX_BIT_CTRL_IN_delay[26], D_delay[6]);
$setuphold (posedge TX_BIT_CTRL_IN[26], posedge D[7], 0:0:0, 0:0:0, notifier,,, TX_BIT_CTRL_IN_delay[26], D_delay[7]);
$setuphold (posedge TX_CLK, negedge TX_CE, 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_CE_delay);
$setuphold (posedge TX_CLK, negedge TX_CNTVALUEIN[0], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_CNTVALUEIN_delay[0]);
$setuphold (posedge TX_CLK, negedge TX_CNTVALUEIN[1], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_CNTVALUEIN_delay[1]);
$setuphold (posedge TX_CLK, negedge TX_CNTVALUEIN[2], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_CNTVALUEIN_delay[2]);
$setuphold (posedge TX_CLK, negedge TX_CNTVALUEIN[3], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_CNTVALUEIN_delay[3]);
$setuphold (posedge TX_CLK, negedge TX_CNTVALUEIN[4], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_CNTVALUEIN_delay[4]);
$setuphold (posedge TX_CLK, negedge TX_CNTVALUEIN[5], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_CNTVALUEIN_delay[5]);
$setuphold (posedge TX_CLK, negedge TX_CNTVALUEIN[6], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_CNTVALUEIN_delay[6]);
$setuphold (posedge TX_CLK, negedge TX_CNTVALUEIN[7], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_CNTVALUEIN_delay[7]);
$setuphold (posedge TX_CLK, negedge TX_CNTVALUEIN[8], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_CNTVALUEIN_delay[8]);
$setuphold (posedge TX_CLK, negedge TX_INC, 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_INC_delay);
$setuphold (posedge TX_CLK, negedge TX_LOAD, 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_LOAD_delay);
$setuphold (posedge TX_CLK, posedge TX_CE, 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_CE_delay);
$setuphold (posedge TX_CLK, posedge TX_CNTVALUEIN[0], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_CNTVALUEIN_delay[0]);
$setuphold (posedge TX_CLK, posedge TX_CNTVALUEIN[1], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_CNTVALUEIN_delay[1]);
$setuphold (posedge TX_CLK, posedge TX_CNTVALUEIN[2], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_CNTVALUEIN_delay[2]);
$setuphold (posedge TX_CLK, posedge TX_CNTVALUEIN[3], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_CNTVALUEIN_delay[3]);
$setuphold (posedge TX_CLK, posedge TX_CNTVALUEIN[4], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_CNTVALUEIN_delay[4]);
$setuphold (posedge TX_CLK, posedge TX_CNTVALUEIN[5], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_CNTVALUEIN_delay[5]);
$setuphold (posedge TX_CLK, posedge TX_CNTVALUEIN[6], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_CNTVALUEIN_delay[6]);
$setuphold (posedge TX_CLK, posedge TX_CNTVALUEIN[7], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_CNTVALUEIN_delay[7]);
$setuphold (posedge TX_CLK, posedge TX_CNTVALUEIN[8], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_CNTVALUEIN_delay[8]);
$setuphold (posedge TX_CLK, posedge TX_INC, 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_INC_delay);
$setuphold (posedge TX_CLK, posedge TX_LOAD, 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_LOAD_delay);
$width (negedge FIFO_RD_CLK, 0:0:0, 0, notifier);
$width (negedge RX_BIT_CTRL_IN[20], 0:0:0, 0, notifier);
$width (negedge RX_CLK, 0:0:0, 0, notifier);
$width (negedge TX_BIT_CTRL_IN[25], 0:0:0, 0, notifier);
$width (negedge TX_BIT_CTRL_IN[26], 0:0:0, 0, notifier);
$width (negedge TX_CLK, 0:0:0, 0, notifier);
$width (posedge FIFO_RD_CLK, 0:0:0, 0, notifier);
$width (posedge RX_BIT_CTRL_IN[20], 0:0:0, 0, notifier);
$width (posedge RX_CLK, 0:0:0, 0, notifier);
$width (posedge TX_BIT_CTRL_IN[25], 0:0:0, 0, notifier);
$width (posedge TX_BIT_CTRL_IN[26], 0:0:0, 0, notifier);
$width (posedge TX_CLK, 0:0:0, 0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
// Date : Mon Sep 18 13:00:13 2017
// Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ fifo_generator_0_sim_netlist.v
// Design : fifo_generator_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7k325tffg676-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "fifo_generator_0,fifo_generator_v13_1_2,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "fifo_generator_v13_1_2,Vivado 2016.3" *)
(* NotValidForBitStream *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(rst,
wr_clk,
rd_clk,
din,
wr_en,
rd_en,
dout,
full,
empty,
rd_data_count,
wr_data_count,
prog_full,
prog_empty);
input rst;
(* x_interface_info = "xilinx.com:signal:clock:1.0 write_clk CLK" *) input wr_clk;
(* x_interface_info = "xilinx.com:signal:clock:1.0 read_clk CLK" *) input rd_clk;
(* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA" *) input [63:0]din;
(* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN" *) input wr_en;
(* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN" *) input rd_en;
(* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA" *) output [63:0]dout;
(* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL" *) output full;
(* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY" *) output empty;
output [8:0]rd_data_count;
output [9:0]wr_data_count;
output prog_full;
output prog_empty;
wire [63:0]din;
wire [63:0]dout;
wire empty;
wire full;
wire prog_empty;
wire prog_full;
wire rd_clk;
wire [8:0]rd_data_count;
wire rd_en;
wire rst;
wire wr_clk;
wire [9:0]wr_data_count;
wire wr_en;
wire NLW_U0_almost_empty_UNCONNECTED;
wire NLW_U0_almost_full_UNCONNECTED;
wire NLW_U0_axi_ar_dbiterr_UNCONNECTED;
wire NLW_U0_axi_ar_overflow_UNCONNECTED;
wire NLW_U0_axi_ar_prog_empty_UNCONNECTED;
wire NLW_U0_axi_ar_prog_full_UNCONNECTED;
wire NLW_U0_axi_ar_sbiterr_UNCONNECTED;
wire NLW_U0_axi_ar_underflow_UNCONNECTED;
wire NLW_U0_axi_aw_dbiterr_UNCONNECTED;
wire NLW_U0_axi_aw_overflow_UNCONNECTED;
wire NLW_U0_axi_aw_prog_empty_UNCONNECTED;
wire NLW_U0_axi_aw_prog_full_UNCONNECTED;
wire NLW_U0_axi_aw_sbiterr_UNCONNECTED;
wire NLW_U0_axi_aw_underflow_UNCONNECTED;
wire NLW_U0_axi_b_dbiterr_UNCONNECTED;
wire NLW_U0_axi_b_overflow_UNCONNECTED;
wire NLW_U0_axi_b_prog_empty_UNCONNECTED;
wire NLW_U0_axi_b_prog_full_UNCONNECTED;
wire NLW_U0_axi_b_sbiterr_UNCONNECTED;
wire NLW_U0_axi_b_underflow_UNCONNECTED;
wire NLW_U0_axi_r_dbiterr_UNCONNECTED;
wire NLW_U0_axi_r_overflow_UNCONNECTED;
wire NLW_U0_axi_r_prog_empty_UNCONNECTED;
wire NLW_U0_axi_r_prog_full_UNCONNECTED;
wire NLW_U0_axi_r_sbiterr_UNCONNECTED;
wire NLW_U0_axi_r_underflow_UNCONNECTED;
wire NLW_U0_axi_w_dbiterr_UNCONNECTED;
wire NLW_U0_axi_w_overflow_UNCONNECTED;
wire NLW_U0_axi_w_prog_empty_UNCONNECTED;
wire NLW_U0_axi_w_prog_full_UNCONNECTED;
wire NLW_U0_axi_w_sbiterr_UNCONNECTED;
wire NLW_U0_axi_w_underflow_UNCONNECTED;
wire NLW_U0_axis_dbiterr_UNCONNECTED;
wire NLW_U0_axis_overflow_UNCONNECTED;
wire NLW_U0_axis_prog_empty_UNCONNECTED;
wire NLW_U0_axis_prog_full_UNCONNECTED;
wire NLW_U0_axis_sbiterr_UNCONNECTED;
wire NLW_U0_axis_underflow_UNCONNECTED;
wire NLW_U0_dbiterr_UNCONNECTED;
wire NLW_U0_m_axi_arvalid_UNCONNECTED;
wire NLW_U0_m_axi_awvalid_UNCONNECTED;
wire NLW_U0_m_axi_bready_UNCONNECTED;
wire NLW_U0_m_axi_rready_UNCONNECTED;
wire NLW_U0_m_axi_wlast_UNCONNECTED;
wire NLW_U0_m_axi_wvalid_UNCONNECTED;
wire NLW_U0_m_axis_tlast_UNCONNECTED;
wire NLW_U0_m_axis_tvalid_UNCONNECTED;
wire NLW_U0_overflow_UNCONNECTED;
wire NLW_U0_rd_rst_busy_UNCONNECTED;
wire NLW_U0_s_axi_arready_UNCONNECTED;
wire NLW_U0_s_axi_awready_UNCONNECTED;
wire NLW_U0_s_axi_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_rlast_UNCONNECTED;
wire NLW_U0_s_axi_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_wready_UNCONNECTED;
wire NLW_U0_s_axis_tready_UNCONNECTED;
wire NLW_U0_sbiterr_UNCONNECTED;
wire NLW_U0_underflow_UNCONNECTED;
wire NLW_U0_valid_UNCONNECTED;
wire NLW_U0_wr_ack_UNCONNECTED;
wire NLW_U0_wr_rst_busy_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_wr_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_wr_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_wr_data_count_UNCONNECTED;
wire [9:0]NLW_U0_data_count_UNCONNECTED;
wire [31:0]NLW_U0_m_axi_araddr_UNCONNECTED;
wire [1:0]NLW_U0_m_axi_arburst_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arcache_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_arid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_arlen_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_arlock_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_arprot_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arqos_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arregion_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_arsize_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_aruser_UNCONNECTED;
wire [31:0]NLW_U0_m_axi_awaddr_UNCONNECTED;
wire [1:0]NLW_U0_m_axi_awburst_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awcache_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_awlen_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awlock_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_awprot_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awqos_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awregion_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_awsize_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awuser_UNCONNECTED;
wire [63:0]NLW_U0_m_axi_wdata_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_wid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_wstrb_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_wuser_UNCONNECTED;
wire [7:0]NLW_U0_m_axis_tdata_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tdest_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tid_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tkeep_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tstrb_UNCONNECTED;
wire [3:0]NLW_U0_m_axis_tuser_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_bid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_buser_UNCONNECTED;
wire [63:0]NLW_U0_s_axi_rdata_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_rid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_ruser_UNCONNECTED;
(* C_ADD_NGC_CONSTRAINT = "0" *)
(* C_APPLICATION_TYPE_AXIS = "0" *)
(* C_APPLICATION_TYPE_RACH = "0" *)
(* C_APPLICATION_TYPE_RDCH = "0" *)
(* C_APPLICATION_TYPE_WACH = "0" *)
(* C_APPLICATION_TYPE_WDCH = "0" *)
(* C_APPLICATION_TYPE_WRCH = "0" *)
(* C_AXIS_TDATA_WIDTH = "8" *)
(* C_AXIS_TDEST_WIDTH = "1" *)
(* C_AXIS_TID_WIDTH = "1" *)
(* C_AXIS_TKEEP_WIDTH = "1" *)
(* C_AXIS_TSTRB_WIDTH = "1" *)
(* C_AXIS_TUSER_WIDTH = "4" *)
(* C_AXIS_TYPE = "0" *)
(* C_AXI_ADDR_WIDTH = "32" *)
(* C_AXI_ARUSER_WIDTH = "1" *)
(* C_AXI_AWUSER_WIDTH = "1" *)
(* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "64" *)
(* C_AXI_ID_WIDTH = "1" *)
(* C_AXI_LEN_WIDTH = "8" *)
(* C_AXI_LOCK_WIDTH = "1" *)
(* C_AXI_RUSER_WIDTH = "1" *)
(* C_AXI_TYPE = "1" *)
(* C_AXI_WUSER_WIDTH = "1" *)
(* C_COMMON_CLOCK = "0" *)
(* C_COUNT_TYPE = "0" *)
(* C_DATA_COUNT_WIDTH = "10" *)
(* C_DEFAULT_VALUE = "BlankString" *)
(* C_DIN_WIDTH = "64" *)
(* C_DIN_WIDTH_AXIS = "1" *)
(* C_DIN_WIDTH_RACH = "32" *)
(* C_DIN_WIDTH_RDCH = "64" *)
(* C_DIN_WIDTH_WACH = "1" *)
(* C_DIN_WIDTH_WDCH = "64" *)
(* C_DIN_WIDTH_WRCH = "2" *)
(* C_DOUT_RST_VAL = "0" *)
(* C_DOUT_WIDTH = "64" *)
(* C_ENABLE_RLOCS = "0" *)
(* C_ENABLE_RST_SYNC = "1" *)
(* C_EN_SAFETY_CKT = "0" *)
(* C_ERROR_INJECTION_TYPE = "0" *)
(* C_ERROR_INJECTION_TYPE_AXIS = "0" *)
(* C_ERROR_INJECTION_TYPE_RACH = "0" *)
(* C_ERROR_INJECTION_TYPE_RDCH = "0" *)
(* C_ERROR_INJECTION_TYPE_WACH = "0" *)
(* C_ERROR_INJECTION_TYPE_WDCH = "0" *)
(* C_ERROR_INJECTION_TYPE_WRCH = "0" *)
(* C_FAMILY = "kintex7" *)
(* C_FULL_FLAGS_RST_VAL = "1" *)
(* C_HAS_ALMOST_EMPTY = "0" *)
(* C_HAS_ALMOST_FULL = "0" *)
(* C_HAS_AXIS_TDATA = "1" *)
(* C_HAS_AXIS_TDEST = "0" *)
(* C_HAS_AXIS_TID = "0" *)
(* C_HAS_AXIS_TKEEP = "0" *)
(* C_HAS_AXIS_TLAST = "0" *)
(* C_HAS_AXIS_TREADY = "1" *)
(* C_HAS_AXIS_TSTRB = "0" *)
(* C_HAS_AXIS_TUSER = "1" *)
(* C_HAS_AXI_ARUSER = "0" *)
(* C_HAS_AXI_AWUSER = "0" *)
(* C_HAS_AXI_BUSER = "0" *)
(* C_HAS_AXI_ID = "0" *)
(* C_HAS_AXI_RD_CHANNEL = "1" *)
(* C_HAS_AXI_RUSER = "0" *)
(* C_HAS_AXI_WR_CHANNEL = "1" *)
(* C_HAS_AXI_WUSER = "0" *)
(* C_HAS_BACKUP = "0" *)
(* C_HAS_DATA_COUNT = "0" *)
(* C_HAS_DATA_COUNTS_AXIS = "0" *)
(* C_HAS_DATA_COUNTS_RACH = "0" *)
(* C_HAS_DATA_COUNTS_RDCH = "0" *)
(* C_HAS_DATA_COUNTS_WACH = "0" *)
(* C_HAS_DATA_COUNTS_WDCH = "0" *)
(* C_HAS_DATA_COUNTS_WRCH = "0" *)
(* C_HAS_INT_CLK = "0" *)
(* C_HAS_MASTER_CE = "0" *)
(* C_HAS_MEMINIT_FILE = "0" *)
(* C_HAS_OVERFLOW = "0" *)
(* C_HAS_PROG_FLAGS_AXIS = "0" *)
(* C_HAS_PROG_FLAGS_RACH = "0" *)
(* C_HAS_PROG_FLAGS_RDCH = "0" *)
(* C_HAS_PROG_FLAGS_WACH = "0" *)
(* C_HAS_PROG_FLAGS_WDCH = "0" *)
(* C_HAS_PROG_FLAGS_WRCH = "0" *)
(* C_HAS_RD_DATA_COUNT = "1" *)
(* C_HAS_RD_RST = "0" *)
(* C_HAS_RST = "1" *)
(* C_HAS_SLAVE_CE = "0" *)
(* C_HAS_SRST = "0" *)
(* C_HAS_UNDERFLOW = "0" *)
(* C_HAS_VALID = "0" *)
(* C_HAS_WR_ACK = "0" *)
(* C_HAS_WR_DATA_COUNT = "1" *)
(* C_HAS_WR_RST = "0" *)
(* C_IMPLEMENTATION_TYPE = "2" *)
(* C_IMPLEMENTATION_TYPE_AXIS = "1" *)
(* C_IMPLEMENTATION_TYPE_RACH = "1" *)
(* C_IMPLEMENTATION_TYPE_RDCH = "1" *)
(* C_IMPLEMENTATION_TYPE_WACH = "1" *)
(* C_IMPLEMENTATION_TYPE_WDCH = "1" *)
(* C_IMPLEMENTATION_TYPE_WRCH = "1" *)
(* C_INIT_WR_PNTR_VAL = "0" *)
(* C_INTERFACE_TYPE = "0" *)
(* C_MEMORY_TYPE = "1" *)
(* C_MIF_FILE_NAME = "BlankString" *)
(* C_MSGON_VAL = "1" *)
(* C_OPTIMIZATION_MODE = "0" *)
(* C_OVERFLOW_LOW = "0" *)
(* C_POWER_SAVING_MODE = "0" *)
(* C_PRELOAD_LATENCY = "1" *)
(* C_PRELOAD_REGS = "0" *)
(* C_PRIM_FIFO_TYPE = "1kx36" *)
(* C_PRIM_FIFO_TYPE_AXIS = "1kx18" *)
(* C_PRIM_FIFO_TYPE_RACH = "512x36" *)
(* C_PRIM_FIFO_TYPE_RDCH = "1kx36" *)
(* C_PRIM_FIFO_TYPE_WACH = "512x36" *)
(* C_PRIM_FIFO_TYPE_WDCH = "1kx36" *)
(* C_PRIM_FIFO_TYPE_WRCH = "512x36" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL = "313" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "1022" *)
(* C_PROG_EMPTY_THRESH_NEGATE_VAL = "314" *)
(* C_PROG_EMPTY_TYPE = "1" *)
(* C_PROG_EMPTY_TYPE_AXIS = "0" *)
(* C_PROG_EMPTY_TYPE_RACH = "0" *)
(* C_PROG_EMPTY_TYPE_RDCH = "0" *)
(* C_PROG_EMPTY_TYPE_WACH = "0" *)
(* C_PROG_EMPTY_TYPE_WDCH = "0" *)
(* C_PROG_EMPTY_TYPE_WRCH = "0" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL = "66" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *)
(* C_PROG_FULL_THRESH_NEGATE_VAL = "65" *)
(* C_PROG_FULL_TYPE = "1" *)
(* C_PROG_FULL_TYPE_AXIS = "0" *)
(* C_PROG_FULL_TYPE_RACH = "0" *)
(* C_PROG_FULL_TYPE_RDCH = "0" *)
(* C_PROG_FULL_TYPE_WACH = "0" *)
(* C_PROG_FULL_TYPE_WDCH = "0" *)
(* C_PROG_FULL_TYPE_WRCH = "0" *)
(* C_RACH_TYPE = "0" *)
(* C_RDCH_TYPE = "0" *)
(* C_RD_DATA_COUNT_WIDTH = "9" *)
(* C_RD_DEPTH = "1024" *)
(* C_RD_FREQ = "1" *)
(* C_RD_PNTR_WIDTH = "10" *)
(* C_REG_SLICE_MODE_AXIS = "0" *)
(* C_REG_SLICE_MODE_RACH = "0" *)
(* C_REG_SLICE_MODE_RDCH = "0" *)
(* C_REG_SLICE_MODE_WACH = "0" *)
(* C_REG_SLICE_MODE_WDCH = "0" *)
(* C_REG_SLICE_MODE_WRCH = "0" *)
(* C_SELECT_XPM = "0" *)
(* C_SYNCHRONIZER_STAGE = "2" *)
(* C_UNDERFLOW_LOW = "0" *)
(* C_USE_COMMON_OVERFLOW = "0" *)
(* C_USE_COMMON_UNDERFLOW = "0" *)
(* C_USE_DEFAULT_SETTINGS = "0" *)
(* C_USE_DOUT_RST = "1" *)
(* C_USE_ECC = "0" *)
(* C_USE_ECC_AXIS = "0" *)
(* C_USE_ECC_RACH = "0" *)
(* C_USE_ECC_RDCH = "0" *)
(* C_USE_ECC_WACH = "0" *)
(* C_USE_ECC_WDCH = "0" *)
(* C_USE_ECC_WRCH = "0" *)
(* C_USE_EMBEDDED_REG = "0" *)
(* C_USE_FIFO16_FLAGS = "0" *)
(* C_USE_FWFT_DATA_COUNT = "0" *)
(* C_USE_PIPELINE_REG = "0" *)
(* C_VALID_LOW = "0" *)
(* C_WACH_TYPE = "0" *)
(* C_WDCH_TYPE = "0" *)
(* C_WRCH_TYPE = "0" *)
(* C_WR_ACK_LOW = "0" *)
(* C_WR_DATA_COUNT_WIDTH = "10" *)
(* C_WR_DEPTH = "1024" *)
(* C_WR_DEPTH_AXIS = "1024" *)
(* C_WR_DEPTH_RACH = "16" *)
(* C_WR_DEPTH_RDCH = "1024" *)
(* C_WR_DEPTH_WACH = "16" *)
(* C_WR_DEPTH_WDCH = "1024" *)
(* C_WR_DEPTH_WRCH = "16" *)
(* C_WR_FREQ = "1" *)
(* C_WR_PNTR_WIDTH = "10" *)
(* C_WR_PNTR_WIDTH_AXIS = "10" *)
(* C_WR_PNTR_WIDTH_RACH = "4" *)
(* C_WR_PNTR_WIDTH_RDCH = "10" *)
(* C_WR_PNTR_WIDTH_WACH = "4" *)
(* C_WR_PNTR_WIDTH_WDCH = "10" *)
(* C_WR_PNTR_WIDTH_WRCH = "4" *)
(* C_WR_RESPONSE_LATENCY = "1" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 U0
(.almost_empty(NLW_U0_almost_empty_UNCONNECTED),
.almost_full(NLW_U0_almost_full_UNCONNECTED),
.axi_ar_data_count(NLW_U0_axi_ar_data_count_UNCONNECTED[4:0]),
.axi_ar_dbiterr(NLW_U0_axi_ar_dbiterr_UNCONNECTED),
.axi_ar_injectdbiterr(1'b0),
.axi_ar_injectsbiterr(1'b0),
.axi_ar_overflow(NLW_U0_axi_ar_overflow_UNCONNECTED),
.axi_ar_prog_empty(NLW_U0_axi_ar_prog_empty_UNCONNECTED),
.axi_ar_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_ar_prog_full(NLW_U0_axi_ar_prog_full_UNCONNECTED),
.axi_ar_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_ar_rd_data_count(NLW_U0_axi_ar_rd_data_count_UNCONNECTED[4:0]),
.axi_ar_sbiterr(NLW_U0_axi_ar_sbiterr_UNCONNECTED),
.axi_ar_underflow(NLW_U0_axi_ar_underflow_UNCONNECTED),
.axi_ar_wr_data_count(NLW_U0_axi_ar_wr_data_count_UNCONNECTED[4:0]),
.axi_aw_data_count(NLW_U0_axi_aw_data_count_UNCONNECTED[4:0]),
.axi_aw_dbiterr(NLW_U0_axi_aw_dbiterr_UNCONNECTED),
.axi_aw_injectdbiterr(1'b0),
.axi_aw_injectsbiterr(1'b0),
.axi_aw_overflow(NLW_U0_axi_aw_overflow_UNCONNECTED),
.axi_aw_prog_empty(NLW_U0_axi_aw_prog_empty_UNCONNECTED),
.axi_aw_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_aw_prog_full(NLW_U0_axi_aw_prog_full_UNCONNECTED),
.axi_aw_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_aw_rd_data_count(NLW_U0_axi_aw_rd_data_count_UNCONNECTED[4:0]),
.axi_aw_sbiterr(NLW_U0_axi_aw_sbiterr_UNCONNECTED),
.axi_aw_underflow(NLW_U0_axi_aw_underflow_UNCONNECTED),
.axi_aw_wr_data_count(NLW_U0_axi_aw_wr_data_count_UNCONNECTED[4:0]),
.axi_b_data_count(NLW_U0_axi_b_data_count_UNCONNECTED[4:0]),
.axi_b_dbiterr(NLW_U0_axi_b_dbiterr_UNCONNECTED),
.axi_b_injectdbiterr(1'b0),
.axi_b_injectsbiterr(1'b0),
.axi_b_overflow(NLW_U0_axi_b_overflow_UNCONNECTED),
.axi_b_prog_empty(NLW_U0_axi_b_prog_empty_UNCONNECTED),
.axi_b_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_b_prog_full(NLW_U0_axi_b_prog_full_UNCONNECTED),
.axi_b_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_b_rd_data_count(NLW_U0_axi_b_rd_data_count_UNCONNECTED[4:0]),
.axi_b_sbiterr(NLW_U0_axi_b_sbiterr_UNCONNECTED),
.axi_b_underflow(NLW_U0_axi_b_underflow_UNCONNECTED),
.axi_b_wr_data_count(NLW_U0_axi_b_wr_data_count_UNCONNECTED[4:0]),
.axi_r_data_count(NLW_U0_axi_r_data_count_UNCONNECTED[10:0]),
.axi_r_dbiterr(NLW_U0_axi_r_dbiterr_UNCONNECTED),
.axi_r_injectdbiterr(1'b0),
.axi_r_injectsbiterr(1'b0),
.axi_r_overflow(NLW_U0_axi_r_overflow_UNCONNECTED),
.axi_r_prog_empty(NLW_U0_axi_r_prog_empty_UNCONNECTED),
.axi_r_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_r_prog_full(NLW_U0_axi_r_prog_full_UNCONNECTED),
.axi_r_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_r_rd_data_count(NLW_U0_axi_r_rd_data_count_UNCONNECTED[10:0]),
.axi_r_sbiterr(NLW_U0_axi_r_sbiterr_UNCONNECTED),
.axi_r_underflow(NLW_U0_axi_r_underflow_UNCONNECTED),
.axi_r_wr_data_count(NLW_U0_axi_r_wr_data_count_UNCONNECTED[10:0]),
.axi_w_data_count(NLW_U0_axi_w_data_count_UNCONNECTED[10:0]),
.axi_w_dbiterr(NLW_U0_axi_w_dbiterr_UNCONNECTED),
.axi_w_injectdbiterr(1'b0),
.axi_w_injectsbiterr(1'b0),
.axi_w_overflow(NLW_U0_axi_w_overflow_UNCONNECTED),
.axi_w_prog_empty(NLW_U0_axi_w_prog_empty_UNCONNECTED),
.axi_w_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_w_prog_full(NLW_U0_axi_w_prog_full_UNCONNECTED),
.axi_w_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_w_rd_data_count(NLW_U0_axi_w_rd_data_count_UNCONNECTED[10:0]),
.axi_w_sbiterr(NLW_U0_axi_w_sbiterr_UNCONNECTED),
.axi_w_underflow(NLW_U0_axi_w_underflow_UNCONNECTED),
.axi_w_wr_data_count(NLW_U0_axi_w_wr_data_count_UNCONNECTED[10:0]),
.axis_data_count(NLW_U0_axis_data_count_UNCONNECTED[10:0]),
.axis_dbiterr(NLW_U0_axis_dbiterr_UNCONNECTED),
.axis_injectdbiterr(1'b0),
.axis_injectsbiterr(1'b0),
.axis_overflow(NLW_U0_axis_overflow_UNCONNECTED),
.axis_prog_empty(NLW_U0_axis_prog_empty_UNCONNECTED),
.axis_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axis_prog_full(NLW_U0_axis_prog_full_UNCONNECTED),
.axis_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axis_rd_data_count(NLW_U0_axis_rd_data_count_UNCONNECTED[10:0]),
.axis_sbiterr(NLW_U0_axis_sbiterr_UNCONNECTED),
.axis_underflow(NLW_U0_axis_underflow_UNCONNECTED),
.axis_wr_data_count(NLW_U0_axis_wr_data_count_UNCONNECTED[10:0]),
.backup(1'b0),
.backup_marker(1'b0),
.clk(1'b0),
.data_count(NLW_U0_data_count_UNCONNECTED[9:0]),
.dbiterr(NLW_U0_dbiterr_UNCONNECTED),
.din(din),
.dout(dout),
.empty(empty),
.full(full),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.int_clk(1'b0),
.m_aclk(1'b0),
.m_aclk_en(1'b0),
.m_axi_araddr(NLW_U0_m_axi_araddr_UNCONNECTED[31:0]),
.m_axi_arburst(NLW_U0_m_axi_arburst_UNCONNECTED[1:0]),
.m_axi_arcache(NLW_U0_m_axi_arcache_UNCONNECTED[3:0]),
.m_axi_arid(NLW_U0_m_axi_arid_UNCONNECTED[0]),
.m_axi_arlen(NLW_U0_m_axi_arlen_UNCONNECTED[7:0]),
.m_axi_arlock(NLW_U0_m_axi_arlock_UNCONNECTED[0]),
.m_axi_arprot(NLW_U0_m_axi_arprot_UNCONNECTED[2:0]),
.m_axi_arqos(NLW_U0_m_axi_arqos_UNCONNECTED[3:0]),
.m_axi_arready(1'b0),
.m_axi_arregion(NLW_U0_m_axi_arregion_UNCONNECTED[3:0]),
.m_axi_arsize(NLW_U0_m_axi_arsize_UNCONNECTED[2:0]),
.m_axi_aruser(NLW_U0_m_axi_aruser_UNCONNECTED[0]),
.m_axi_arvalid(NLW_U0_m_axi_arvalid_UNCONNECTED),
.m_axi_awaddr(NLW_U0_m_axi_awaddr_UNCONNECTED[31:0]),
.m_axi_awburst(NLW_U0_m_axi_awburst_UNCONNECTED[1:0]),
.m_axi_awcache(NLW_U0_m_axi_awcache_UNCONNECTED[3:0]),
.m_axi_awid(NLW_U0_m_axi_awid_UNCONNECTED[0]),
.m_axi_awlen(NLW_U0_m_axi_awlen_UNCONNECTED[7:0]),
.m_axi_awlock(NLW_U0_m_axi_awlock_UNCONNECTED[0]),
.m_axi_awprot(NLW_U0_m_axi_awprot_UNCONNECTED[2:0]),
.m_axi_awqos(NLW_U0_m_axi_awqos_UNCONNECTED[3:0]),
.m_axi_awready(1'b0),
.m_axi_awregion(NLW_U0_m_axi_awregion_UNCONNECTED[3:0]),
.m_axi_awsize(NLW_U0_m_axi_awsize_UNCONNECTED[2:0]),
.m_axi_awuser(NLW_U0_m_axi_awuser_UNCONNECTED[0]),
.m_axi_awvalid(NLW_U0_m_axi_awvalid_UNCONNECTED),
.m_axi_bid(1'b0),
.m_axi_bready(NLW_U0_m_axi_bready_UNCONNECTED),
.m_axi_bresp({1'b0,1'b0}),
.m_axi_buser(1'b0),
.m_axi_bvalid(1'b0),
.m_axi_rdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.m_axi_rid(1'b0),
.m_axi_rlast(1'b0),
.m_axi_rready(NLW_U0_m_axi_rready_UNCONNECTED),
.m_axi_rresp({1'b0,1'b0}),
.m_axi_ruser(1'b0),
.m_axi_rvalid(1'b0),
.m_axi_wdata(NLW_U0_m_axi_wdata_UNCONNECTED[63:0]),
.m_axi_wid(NLW_U0_m_axi_wid_UNCONNECTED[0]),
.m_axi_wlast(NLW_U0_m_axi_wlast_UNCONNECTED),
.m_axi_wready(1'b0),
.m_axi_wstrb(NLW_U0_m_axi_wstrb_UNCONNECTED[7:0]),
.m_axi_wuser(NLW_U0_m_axi_wuser_UNCONNECTED[0]),
.m_axi_wvalid(NLW_U0_m_axi_wvalid_UNCONNECTED),
.m_axis_tdata(NLW_U0_m_axis_tdata_UNCONNECTED[7:0]),
.m_axis_tdest(NLW_U0_m_axis_tdest_UNCONNECTED[0]),
.m_axis_tid(NLW_U0_m_axis_tid_UNCONNECTED[0]),
.m_axis_tkeep(NLW_U0_m_axis_tkeep_UNCONNECTED[0]),
.m_axis_tlast(NLW_U0_m_axis_tlast_UNCONNECTED),
.m_axis_tready(1'b0),
.m_axis_tstrb(NLW_U0_m_axis_tstrb_UNCONNECTED[0]),
.m_axis_tuser(NLW_U0_m_axis_tuser_UNCONNECTED[3:0]),
.m_axis_tvalid(NLW_U0_m_axis_tvalid_UNCONNECTED),
.overflow(NLW_U0_overflow_UNCONNECTED),
.prog_empty(prog_empty),
.prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_empty_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_empty_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full(prog_full),
.prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.rd_clk(rd_clk),
.rd_data_count(rd_data_count),
.rd_en(rd_en),
.rd_rst(1'b0),
.rd_rst_busy(NLW_U0_rd_rst_busy_UNCONNECTED),
.rst(rst),
.s_aclk(1'b0),
.s_aclk_en(1'b0),
.s_aresetn(1'b0),
.s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arburst({1'b0,1'b0}),
.s_axi_arcache({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arid(1'b0),
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arlock(1'b0),
.s_axi_arprot({1'b0,1'b0,1'b0}),
.s_axi_arqos({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
.s_axi_arregion({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arsize({1'b0,1'b0,1'b0}),
.s_axi_aruser(1'b0),
.s_axi_arvalid(1'b0),
.s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awburst({1'b0,1'b0}),
.s_axi_awcache({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awid(1'b0),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlock(1'b0),
.s_axi_awprot({1'b0,1'b0,1'b0}),
.s_axi_awqos({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
.s_axi_awregion({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awsize({1'b0,1'b0,1'b0}),
.s_axi_awuser(1'b0),
.s_axi_awvalid(1'b0),
.s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[0]),
.s_axi_bready(1'b0),
.s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
.s_axi_buser(NLW_U0_s_axi_buser_UNCONNECTED[0]),
.s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
.s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[63:0]),
.s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[0]),
.s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
.s_axi_rready(1'b0),
.s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
.s_axi_ruser(NLW_U0_s_axi_ruser_UNCONNECTED[0]),
.s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
.s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wid(1'b0),
.s_axi_wlast(1'b0),
.s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
.s_axi_wstrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wuser(1'b0),
.s_axi_wvalid(1'b0),
.s_axis_tdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axis_tdest(1'b0),
.s_axis_tid(1'b0),
.s_axis_tkeep(1'b0),
.s_axis_tlast(1'b0),
.s_axis_tready(NLW_U0_s_axis_tready_UNCONNECTED),
.s_axis_tstrb(1'b0),
.s_axis_tuser({1'b0,1'b0,1'b0,1'b0}),
.s_axis_tvalid(1'b0),
.sbiterr(NLW_U0_sbiterr_UNCONNECTED),
.sleep(1'b0),
.srst(1'b0),
.underflow(NLW_U0_underflow_UNCONNECTED),
.valid(NLW_U0_valid_UNCONNECTED),
.wr_ack(NLW_U0_wr_ack_UNCONNECTED),
.wr_clk(wr_clk),
.wr_data_count(wr_data_count),
.wr_en(wr_en),
.wr_rst(1'b0),
.wr_rst_busy(NLW_U0_wr_rst_busy_UNCONNECTED));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr
(dout,
wr_clk,
rd_clk,
E,
tmp_ram_rd_en,
out,
\gic0.gc0.count_d2_reg[9] ,
\gc0.count_d1_reg[9] ,
din);
output [63:0]dout;
input wr_clk;
input rd_clk;
input [0:0]E;
input tmp_ram_rd_en;
input [0:0]out;
input [9:0]\gic0.gc0.count_d2_reg[9] ;
input [9:0]\gc0.count_d1_reg[9] ;
input [63:0]din;
wire [0:0]E;
wire [63:0]din;
wire [63:0]dout;
wire [9:0]\gc0.count_d1_reg[9] ;
wire [9:0]\gic0.gc0.count_d2_reg[9] ;
wire [0:0]out;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width \ramloop[0].ram.r
(.E(E),
.din(din[35:0]),
.dout(dout[35:0]),
.\gc0.count_d1_reg[9] (\gc0.count_d1_reg[9] ),
.\gic0.gc0.count_d2_reg[9] (\gic0.gc0.count_d2_reg[9] ),
.out(out),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0 \ramloop[1].ram.r
(.E(E),
.din(din[63:36]),
.dout(dout[63:36]),
.\gc0.count_d1_reg[9] (\gc0.count_d1_reg[9] ),
.\gic0.gc0.count_d2_reg[9] (\gic0.gc0.count_d2_reg[9] ),
.out(out),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width
(dout,
wr_clk,
rd_clk,
E,
tmp_ram_rd_en,
out,
\gic0.gc0.count_d2_reg[9] ,
\gc0.count_d1_reg[9] ,
din);
output [35:0]dout;
input wr_clk;
input rd_clk;
input [0:0]E;
input tmp_ram_rd_en;
input [0:0]out;
input [9:0]\gic0.gc0.count_d2_reg[9] ;
input [9:0]\gc0.count_d1_reg[9] ;
input [35:0]din;
wire [0:0]E;
wire [35:0]din;
wire [35:0]dout;
wire [9:0]\gc0.count_d1_reg[9] ;
wire [9:0]\gic0.gc0.count_d2_reg[9] ;
wire [0:0]out;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper \prim_noinit.ram
(.E(E),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[9] (\gc0.count_d1_reg[9] ),
.\gic0.gc0.count_d2_reg[9] (\gic0.gc0.count_d2_reg[9] ),
.out(out),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0
(dout,
wr_clk,
rd_clk,
E,
tmp_ram_rd_en,
out,
\gic0.gc0.count_d2_reg[9] ,
\gc0.count_d1_reg[9] ,
din);
output [27:0]dout;
input wr_clk;
input rd_clk;
input [0:0]E;
input tmp_ram_rd_en;
input [0:0]out;
input [9:0]\gic0.gc0.count_d2_reg[9] ;
input [9:0]\gc0.count_d1_reg[9] ;
input [27:0]din;
wire [0:0]E;
wire [27:0]din;
wire [27:0]dout;
wire [9:0]\gc0.count_d1_reg[9] ;
wire [9:0]\gic0.gc0.count_d2_reg[9] ;
wire [0:0]out;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0 \prim_noinit.ram
(.E(E),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[9] (\gc0.count_d1_reg[9] ),
.\gic0.gc0.count_d2_reg[9] (\gic0.gc0.count_d2_reg[9] ),
.out(out),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper
(dout,
wr_clk,
rd_clk,
E,
tmp_ram_rd_en,
out,
\gic0.gc0.count_d2_reg[9] ,
\gc0.count_d1_reg[9] ,
din);
output [35:0]dout;
input wr_clk;
input rd_clk;
input [0:0]E;
input tmp_ram_rd_en;
input [0:0]out;
input [9:0]\gic0.gc0.count_d2_reg[9] ;
input [9:0]\gc0.count_d1_reg[9] ;
input [35:0]din;
wire [0:0]E;
wire [35:0]din;
wire [35:0]dout;
wire [9:0]\gc0.count_d1_reg[9] ;
wire [9:0]\gic0.gc0.count_d2_reg[9] ;
wire [0:0]out;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "INDEPENDENT" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\gic0.gc0.count_d2_reg[9] ,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,\gc0.count_d1_reg[9] ,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(wr_clk),
.CLKBWRCLK(rd_clk),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({din[34:27],din[25:18],din[16:9],din[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({din[35],din[26],din[17],din[8]}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({dout[34:27],dout[25:18],dout[16:9],dout[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({dout[35],dout[26],dout[17],dout[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(E),
.ENBWREN(tmp_ram_rd_en),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(out),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({E,E,E,E}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0
(dout,
wr_clk,
rd_clk,
E,
tmp_ram_rd_en,
out,
\gic0.gc0.count_d2_reg[9] ,
\gc0.count_d1_reg[9] ,
din);
output [27:0]dout;
input wr_clk;
input rd_clk;
input [0:0]E;
input tmp_ram_rd_en;
input [0:0]out;
input [9:0]\gic0.gc0.count_d2_reg[9] ;
input [9:0]\gc0.count_d1_reg[9] ;
input [27:0]din;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_53 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_61 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_69 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_77 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_89 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_90 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_91 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92 ;
wire [0:0]E;
wire [27:0]din;
wire [27:0]dout;
wire [9:0]\gc0.count_d1_reg[9] ;
wire [9:0]\gic0.gc0.count_d2_reg[9] ;
wire [0:0]out;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "INDEPENDENT" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\gic0.gc0.count_d2_reg[9] ,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,\gc0.count_d1_reg[9] ,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(wr_clk),
.CLKBWRCLK(rd_clk),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,din[27:21],1'b0,din[20:14],1'b0,din[13:7],1'b0,din[6:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_53 ,dout[27:21],\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_61 ,dout[20:14],\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_69 ,dout[13:7],\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_77 ,dout[6:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_89 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_90 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_91 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92 }),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(E),
.ENBWREN(tmp_ram_rd_en),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(out),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({E,E,E,E}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top
(dout,
wr_clk,
rd_clk,
E,
tmp_ram_rd_en,
out,
\gic0.gc0.count_d2_reg[9] ,
\gc0.count_d1_reg[9] ,
din);
output [63:0]dout;
input wr_clk;
input rd_clk;
input [0:0]E;
input tmp_ram_rd_en;
input [0:0]out;
input [9:0]\gic0.gc0.count_d2_reg[9] ;
input [9:0]\gc0.count_d1_reg[9] ;
input [63:0]din;
wire [0:0]E;
wire [63:0]din;
wire [63:0]dout;
wire [9:0]\gc0.count_d1_reg[9] ;
wire [9:0]\gic0.gc0.count_d2_reg[9] ;
wire [0:0]out;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr \valid.cstr
(.E(E),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[9] (\gc0.count_d1_reg[9] ),
.\gic0.gc0.count_d2_reg[9] (\gic0.gc0.count_d2_reg[9] ),
.out(out),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4
(dout,
wr_clk,
rd_clk,
E,
tmp_ram_rd_en,
out,
\gic0.gc0.count_d2_reg[9] ,
\gc0.count_d1_reg[9] ,
din);
output [63:0]dout;
input wr_clk;
input rd_clk;
input [0:0]E;
input tmp_ram_rd_en;
input [0:0]out;
input [9:0]\gic0.gc0.count_d2_reg[9] ;
input [9:0]\gc0.count_d1_reg[9] ;
input [63:0]din;
wire [0:0]E;
wire [63:0]din;
wire [63:0]dout;
wire [9:0]\gc0.count_d1_reg[9] ;
wire [9:0]\gic0.gc0.count_d2_reg[9] ;
wire [0:0]out;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth inst_blk_mem_gen
(.E(E),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[9] (\gc0.count_d1_reg[9] ),
.\gic0.gc0.count_d2_reg[9] (\gic0.gc0.count_d2_reg[9] ),
.out(out),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth
(dout,
wr_clk,
rd_clk,
E,
tmp_ram_rd_en,
out,
\gic0.gc0.count_d2_reg[9] ,
\gc0.count_d1_reg[9] ,
din);
output [63:0]dout;
input wr_clk;
input rd_clk;
input [0:0]E;
input tmp_ram_rd_en;
input [0:0]out;
input [9:0]\gic0.gc0.count_d2_reg[9] ;
input [9:0]\gc0.count_d1_reg[9] ;
input [63:0]din;
wire [0:0]E;
wire [63:0]din;
wire [63:0]dout;
wire [9:0]\gc0.count_d1_reg[9] ;
wire [9:0]\gic0.gc0.count_d2_reg[9] ;
wire [0:0]out;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top \gnbram.gnativebmg.native_blk_mem_gen
(.E(E),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[9] (\gc0.count_d1_reg[9] ),
.\gic0.gc0.count_d2_reg[9] (\gic0.gc0.count_d2_reg[9] ),
.out(out),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_x_pntrs
(v1_reg,
v1_reg_0,
D,
\rd_dc_i_reg[9] ,
v1_reg_1,
RD_PNTR_WR,
v1_reg_2,
Q,
\gc0.count_reg[9] ,
p_0_out,
\gic0.gc0.count_d1_reg[7] ,
\gic0.gc0.count_reg[9] ,
\gic0.gc0.count_d2_reg[9] ,
wr_clk,
AR,
rd_clk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );
output [4:0]v1_reg;
output [4:0]v1_reg_0;
output [8:0]D;
output [8:0]\rd_dc_i_reg[9] ;
output [3:0]v1_reg_1;
output [9:0]RD_PNTR_WR;
output [4:0]v1_reg_2;
input [9:0]Q;
input [9:0]\gc0.count_reg[9] ;
input p_0_out;
input [7:0]\gic0.gc0.count_d1_reg[7] ;
input [9:0]\gic0.gc0.count_reg[9] ;
input [9:0]\gic0.gc0.count_d2_reg[9] ;
input wr_clk;
input [0:0]AR;
input rd_clk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [0:0]AR;
wire [8:0]D;
wire [9:0]Q;
wire [9:0]RD_PNTR_WR;
wire [8:0]bin2gray;
wire [9:0]\gc0.count_reg[9] ;
wire \gdiff.diff_pntr_pad[10]_i_2_n_0 ;
wire \gdiff.diff_pntr_pad[10]_i_3_n_0 ;
wire \gdiff.diff_pntr_pad[4]_i_3_n_0 ;
wire \gdiff.diff_pntr_pad[4]_i_4_n_0 ;
wire \gdiff.diff_pntr_pad[4]_i_5_n_0 ;
wire \gdiff.diff_pntr_pad[4]_i_6_n_0 ;
wire \gdiff.diff_pntr_pad[8]_i_2_n_0 ;
wire \gdiff.diff_pntr_pad[8]_i_3_n_0 ;
wire \gdiff.diff_pntr_pad[8]_i_4_n_0 ;
wire \gdiff.diff_pntr_pad[8]_i_5_n_0 ;
wire \gdiff.diff_pntr_pad_reg[10]_i_1_n_3 ;
wire \gdiff.diff_pntr_pad_reg[4]_i_1_n_0 ;
wire \gdiff.diff_pntr_pad_reg[4]_i_1_n_1 ;
wire \gdiff.diff_pntr_pad_reg[4]_i_1_n_2 ;
wire \gdiff.diff_pntr_pad_reg[4]_i_1_n_3 ;
wire \gdiff.diff_pntr_pad_reg[8]_i_1_n_0 ;
wire \gdiff.diff_pntr_pad_reg[8]_i_1_n_1 ;
wire \gdiff.diff_pntr_pad_reg[8]_i_1_n_2 ;
wire \gdiff.diff_pntr_pad_reg[8]_i_1_n_3 ;
wire [7:0]\gic0.gc0.count_d1_reg[7] ;
wire [9:0]\gic0.gc0.count_d2_reg[9] ;
wire [9:0]\gic0.gc0.count_reg[9] ;
wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_1 ;
wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_2 ;
wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_3 ;
wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4 ;
wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_5 ;
wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_6 ;
wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_7 ;
wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_8 ;
wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_9 ;
wire \gnxpm_cdc.rd_pntr_gc[0]_i_1_n_0 ;
wire \gnxpm_cdc.rd_pntr_gc[1]_i_1_n_0 ;
wire \gnxpm_cdc.rd_pntr_gc[2]_i_1_n_0 ;
wire \gnxpm_cdc.rd_pntr_gc[3]_i_1_n_0 ;
wire \gnxpm_cdc.rd_pntr_gc[4]_i_1_n_0 ;
wire \gnxpm_cdc.rd_pntr_gc[5]_i_1_n_0 ;
wire \gnxpm_cdc.rd_pntr_gc[6]_i_1_n_0 ;
wire \gnxpm_cdc.rd_pntr_gc[7]_i_1_n_0 ;
wire \gnxpm_cdc.rd_pntr_gc[8]_i_1_n_0 ;
wire [7:0]gray2bin;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire p_0_out;
wire p_0_out_0;
wire [9:0]p_22_out;
wire [9:0]p_3_out;
wire [9:0]p_4_out;
wire [9:9]p_5_out;
wire [9:9]p_6_out;
wire rd_clk;
wire \rd_dc_i[3]_i_2_n_0 ;
wire \rd_dc_i[3]_i_3_n_0 ;
wire \rd_dc_i[3]_i_4_n_0 ;
wire \rd_dc_i[3]_i_5_n_0 ;
wire \rd_dc_i[7]_i_2_n_0 ;
wire \rd_dc_i[7]_i_3_n_0 ;
wire \rd_dc_i[7]_i_4_n_0 ;
wire \rd_dc_i[7]_i_5_n_0 ;
wire \rd_dc_i[9]_i_2_n_0 ;
wire \rd_dc_i[9]_i_3_n_0 ;
wire \rd_dc_i_reg[3]_i_1_n_0 ;
wire \rd_dc_i_reg[3]_i_1_n_1 ;
wire \rd_dc_i_reg[3]_i_1_n_2 ;
wire \rd_dc_i_reg[3]_i_1_n_3 ;
wire \rd_dc_i_reg[7]_i_1_n_0 ;
wire \rd_dc_i_reg[7]_i_1_n_1 ;
wire \rd_dc_i_reg[7]_i_1_n_2 ;
wire \rd_dc_i_reg[7]_i_1_n_3 ;
wire [8:0]\rd_dc_i_reg[9] ;
wire \rd_dc_i_reg[9]_i_1_n_3 ;
wire [9:0]rd_pntr_gc;
wire [4:0]v1_reg;
wire [4:0]v1_reg_0;
wire [3:0]v1_reg_1;
wire [4:0]v1_reg_2;
wire wr_clk;
wire [9:0]wr_pntr_gc;
wire [3:1]\NLW_gdiff.diff_pntr_pad_reg[10]_i_1_CO_UNCONNECTED ;
wire [3:2]\NLW_gdiff.diff_pntr_pad_reg[10]_i_1_O_UNCONNECTED ;
wire [0:0]\NLW_gdiff.diff_pntr_pad_reg[4]_i_1_O_UNCONNECTED ;
wire [0:0]\NLW_rd_dc_i_reg[3]_i_1_O_UNCONNECTED ;
wire [3:1]\NLW_rd_dc_i_reg[9]_i_1_CO_UNCONNECTED ;
wire [3:2]\NLW_rd_dc_i_reg[9]_i_1_O_UNCONNECTED ;
LUT2 #(
.INIT(4'h9))
\gdiff.diff_pntr_pad[10]_i_2
(.I0(p_22_out[9]),
.I1(Q[9]),
.O(\gdiff.diff_pntr_pad[10]_i_2_n_0 ));
LUT2 #(
.INIT(4'h9))
\gdiff.diff_pntr_pad[10]_i_3
(.I0(p_22_out[8]),
.I1(Q[8]),
.O(\gdiff.diff_pntr_pad[10]_i_3_n_0 ));
LUT2 #(
.INIT(4'h9))
\gdiff.diff_pntr_pad[4]_i_3
(.I0(p_22_out[3]),
.I1(Q[3]),
.O(\gdiff.diff_pntr_pad[4]_i_3_n_0 ));
LUT2 #(
.INIT(4'h9))
\gdiff.diff_pntr_pad[4]_i_4
(.I0(p_22_out[2]),
.I1(Q[2]),
.O(\gdiff.diff_pntr_pad[4]_i_4_n_0 ));
LUT2 #(
.INIT(4'h9))
\gdiff.diff_pntr_pad[4]_i_5
(.I0(p_22_out[1]),
.I1(Q[1]),
.O(\gdiff.diff_pntr_pad[4]_i_5_n_0 ));
LUT2 #(
.INIT(4'h9))
\gdiff.diff_pntr_pad[4]_i_6
(.I0(p_22_out[0]),
.I1(Q[0]),
.O(\gdiff.diff_pntr_pad[4]_i_6_n_0 ));
LUT2 #(
.INIT(4'h9))
\gdiff.diff_pntr_pad[8]_i_2
(.I0(p_22_out[7]),
.I1(Q[7]),
.O(\gdiff.diff_pntr_pad[8]_i_2_n_0 ));
LUT2 #(
.INIT(4'h9))
\gdiff.diff_pntr_pad[8]_i_3
(.I0(p_22_out[6]),
.I1(Q[6]),
.O(\gdiff.diff_pntr_pad[8]_i_3_n_0 ));
LUT2 #(
.INIT(4'h9))
\gdiff.diff_pntr_pad[8]_i_4
(.I0(p_22_out[5]),
.I1(Q[5]),
.O(\gdiff.diff_pntr_pad[8]_i_4_n_0 ));
LUT2 #(
.INIT(4'h9))
\gdiff.diff_pntr_pad[8]_i_5
(.I0(p_22_out[4]),
.I1(Q[4]),
.O(\gdiff.diff_pntr_pad[8]_i_5_n_0 ));
CARRY4 \gdiff.diff_pntr_pad_reg[10]_i_1
(.CI(\gdiff.diff_pntr_pad_reg[8]_i_1_n_0 ),
.CO({\NLW_gdiff.diff_pntr_pad_reg[10]_i_1_CO_UNCONNECTED [3:1],\gdiff.diff_pntr_pad_reg[10]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,p_22_out[8]}),
.O({\NLW_gdiff.diff_pntr_pad_reg[10]_i_1_O_UNCONNECTED [3:2],D[8:7]}),
.S({1'b0,1'b0,\gdiff.diff_pntr_pad[10]_i_2_n_0 ,\gdiff.diff_pntr_pad[10]_i_3_n_0 }));
CARRY4 \gdiff.diff_pntr_pad_reg[4]_i_1
(.CI(1'b0),
.CO({\gdiff.diff_pntr_pad_reg[4]_i_1_n_0 ,\gdiff.diff_pntr_pad_reg[4]_i_1_n_1 ,\gdiff.diff_pntr_pad_reg[4]_i_1_n_2 ,\gdiff.diff_pntr_pad_reg[4]_i_1_n_3 }),
.CYINIT(p_0_out),
.DI(p_22_out[3:0]),
.O({D[2:0],\NLW_gdiff.diff_pntr_pad_reg[4]_i_1_O_UNCONNECTED [0]}),
.S({\gdiff.diff_pntr_pad[4]_i_3_n_0 ,\gdiff.diff_pntr_pad[4]_i_4_n_0 ,\gdiff.diff_pntr_pad[4]_i_5_n_0 ,\gdiff.diff_pntr_pad[4]_i_6_n_0 }));
CARRY4 \gdiff.diff_pntr_pad_reg[8]_i_1
(.CI(\gdiff.diff_pntr_pad_reg[4]_i_1_n_0 ),
.CO({\gdiff.diff_pntr_pad_reg[8]_i_1_n_0 ,\gdiff.diff_pntr_pad_reg[8]_i_1_n_1 ,\gdiff.diff_pntr_pad_reg[8]_i_1_n_2 ,\gdiff.diff_pntr_pad_reg[8]_i_1_n_3 }),
.CYINIT(1'b0),
.DI(p_22_out[7:4]),
.O(D[6:3]),
.S({\gdiff.diff_pntr_pad[8]_i_2_n_0 ,\gdiff.diff_pntr_pad[8]_i_3_n_0 ,\gdiff.diff_pntr_pad[8]_i_4_n_0 ,\gdiff.diff_pntr_pad[8]_i_5_n_0 }));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1
(.I0(p_22_out[0]),
.I1(Q[0]),
.I2(p_22_out[1]),
.I3(Q[1]),
.O(v1_reg[0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1__0
(.I0(p_22_out[0]),
.I1(\gc0.count_reg[9] [0]),
.I2(p_22_out[1]),
.I3(\gc0.count_reg[9] [1]),
.O(v1_reg_0[0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1__1
(.I0(RD_PNTR_WR[0]),
.I1(\gic0.gc0.count_d1_reg[7] [0]),
.I2(RD_PNTR_WR[1]),
.I3(\gic0.gc0.count_d1_reg[7] [1]),
.O(v1_reg_1[0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1__2
(.I0(RD_PNTR_WR[0]),
.I1(\gic0.gc0.count_reg[9] [0]),
.I2(RD_PNTR_WR[1]),
.I3(\gic0.gc0.count_reg[9] [1]),
.O(v1_reg_2[0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1
(.I0(p_22_out[2]),
.I1(Q[2]),
.I2(p_22_out[3]),
.I3(Q[3]),
.O(v1_reg[1]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1__0
(.I0(p_22_out[2]),
.I1(\gc0.count_reg[9] [2]),
.I2(p_22_out[3]),
.I3(\gc0.count_reg[9] [3]),
.O(v1_reg_0[1]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1__1
(.I0(RD_PNTR_WR[2]),
.I1(\gic0.gc0.count_d1_reg[7] [2]),
.I2(RD_PNTR_WR[3]),
.I3(\gic0.gc0.count_d1_reg[7] [3]),
.O(v1_reg_1[1]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1__2
(.I0(RD_PNTR_WR[2]),
.I1(\gic0.gc0.count_reg[9] [2]),
.I2(RD_PNTR_WR[3]),
.I3(\gic0.gc0.count_reg[9] [3]),
.O(v1_reg_2[1]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1
(.I0(p_22_out[4]),
.I1(Q[4]),
.I2(p_22_out[5]),
.I3(Q[5]),
.O(v1_reg[2]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1__0
(.I0(p_22_out[4]),
.I1(\gc0.count_reg[9] [4]),
.I2(p_22_out[5]),
.I3(\gc0.count_reg[9] [5]),
.O(v1_reg_0[2]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1__1
(.I0(RD_PNTR_WR[4]),
.I1(\gic0.gc0.count_d1_reg[7] [4]),
.I2(RD_PNTR_WR[5]),
.I3(\gic0.gc0.count_d1_reg[7] [5]),
.O(v1_reg_1[2]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1__2
(.I0(RD_PNTR_WR[4]),
.I1(\gic0.gc0.count_reg[9] [4]),
.I2(RD_PNTR_WR[5]),
.I3(\gic0.gc0.count_reg[9] [5]),
.O(v1_reg_2[2]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1
(.I0(p_22_out[6]),
.I1(Q[6]),
.I2(p_22_out[7]),
.I3(Q[7]),
.O(v1_reg[3]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1__0
(.I0(p_22_out[6]),
.I1(\gc0.count_reg[9] [6]),
.I2(p_22_out[7]),
.I3(\gc0.count_reg[9] [7]),
.O(v1_reg_0[3]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1__1
(.I0(RD_PNTR_WR[6]),
.I1(\gic0.gc0.count_d1_reg[7] [6]),
.I2(RD_PNTR_WR[7]),
.I3(\gic0.gc0.count_d1_reg[7] [7]),
.O(v1_reg_1[3]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1__2
(.I0(RD_PNTR_WR[6]),
.I1(\gic0.gc0.count_reg[9] [6]),
.I2(RD_PNTR_WR[7]),
.I3(\gic0.gc0.count_reg[9] [7]),
.O(v1_reg_2[3]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[4].gms.ms_i_1
(.I0(p_22_out[8]),
.I1(Q[8]),
.I2(p_22_out[9]),
.I3(Q[9]),
.O(v1_reg[4]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[4].gms.ms_i_1__0
(.I0(p_22_out[8]),
.I1(\gc0.count_reg[9] [8]),
.I2(p_22_out[9]),
.I3(\gc0.count_reg[9] [9]),
.O(v1_reg_0[4]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[4].gms.ms_i_1__2
(.I0(RD_PNTR_WR[8]),
.I1(\gic0.gc0.count_reg[9] [8]),
.I2(RD_PNTR_WR[9]),
.I3(\gic0.gc0.count_reg[9] [9]),
.O(v1_reg_2[4]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized0 \gnxpm_cdc.gsync_stage[1].rd_stg_inst
(.D(p_3_out),
.Q(wr_pntr_gc),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.rd_clk(rd_clk));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized1 \gnxpm_cdc.gsync_stage[1].wr_stg_inst
(.AR(AR),
.D(p_4_out),
.Q(rd_pntr_gc),
.wr_clk(wr_clk));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized2 \gnxpm_cdc.gsync_stage[2].rd_stg_inst
(.D(p_3_out),
.\gnxpm_cdc.wr_pntr_bin_reg[8] ({p_0_out_0,gray2bin}),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.out(p_5_out),
.rd_clk(rd_clk));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized3 \gnxpm_cdc.gsync_stage[2].wr_stg_inst
(.AR(AR),
.D(p_4_out),
.\gnxpm_cdc.rd_pntr_bin_reg[8] ({\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_1 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_2 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_3 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_5 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_6 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_7 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_8 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_9 }),
.out(p_6_out),
.wr_clk(wr_clk));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[0]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_9 ),
.Q(RD_PNTR_WR[0]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[1]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_8 ),
.Q(RD_PNTR_WR[1]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[2]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_7 ),
.Q(RD_PNTR_WR[2]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[3]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_6 ),
.Q(RD_PNTR_WR[3]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[4]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_5 ),
.Q(RD_PNTR_WR[4]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[5]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4 ),
.Q(RD_PNTR_WR[5]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[6]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_3 ),
.Q(RD_PNTR_WR[6]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[7]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_2 ),
.Q(RD_PNTR_WR[7]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[8]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_1 ),
.Q(RD_PNTR_WR[8]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[9]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(p_6_out),
.Q(RD_PNTR_WR[9]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[0]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.O(\gnxpm_cdc.rd_pntr_gc[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[1]_i_1
(.I0(Q[1]),
.I1(Q[2]),
.O(\gnxpm_cdc.rd_pntr_gc[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[2]_i_1
(.I0(Q[2]),
.I1(Q[3]),
.O(\gnxpm_cdc.rd_pntr_gc[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[3]_i_1
(.I0(Q[3]),
.I1(Q[4]),
.O(\gnxpm_cdc.rd_pntr_gc[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[4]_i_1
(.I0(Q[4]),
.I1(Q[5]),
.O(\gnxpm_cdc.rd_pntr_gc[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[5]_i_1
(.I0(Q[5]),
.I1(Q[6]),
.O(\gnxpm_cdc.rd_pntr_gc[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[6]_i_1
(.I0(Q[6]),
.I1(Q[7]),
.O(\gnxpm_cdc.rd_pntr_gc[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[7]_i_1
(.I0(Q[7]),
.I1(Q[8]),
.O(\gnxpm_cdc.rd_pntr_gc[7]_i_1_n_0 ));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[8]_i_1
(.I0(Q[8]),
.I1(Q[9]),
.O(\gnxpm_cdc.rd_pntr_gc[8]_i_1_n_0 ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[0]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gnxpm_cdc.rd_pntr_gc[0]_i_1_n_0 ),
.Q(rd_pntr_gc[0]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[1]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gnxpm_cdc.rd_pntr_gc[1]_i_1_n_0 ),
.Q(rd_pntr_gc[1]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[2]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gnxpm_cdc.rd_pntr_gc[2]_i_1_n_0 ),
.Q(rd_pntr_gc[2]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[3]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gnxpm_cdc.rd_pntr_gc[3]_i_1_n_0 ),
.Q(rd_pntr_gc[3]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[4]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gnxpm_cdc.rd_pntr_gc[4]_i_1_n_0 ),
.Q(rd_pntr_gc[4]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[5]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gnxpm_cdc.rd_pntr_gc[5]_i_1_n_0 ),
.Q(rd_pntr_gc[5]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[6]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gnxpm_cdc.rd_pntr_gc[6]_i_1_n_0 ),
.Q(rd_pntr_gc[6]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[7]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gnxpm_cdc.rd_pntr_gc[7]_i_1_n_0 ),
.Q(rd_pntr_gc[7]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[8]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gnxpm_cdc.rd_pntr_gc[8]_i_1_n_0 ),
.Q(rd_pntr_gc[8]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[9]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[9]),
.Q(rd_pntr_gc[9]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[0]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(gray2bin[0]),
.Q(p_22_out[0]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[1]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(gray2bin[1]),
.Q(p_22_out[1]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[2]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(gray2bin[2]),
.Q(p_22_out[2]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[3]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(gray2bin[3]),
.Q(p_22_out[3]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[4]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(gray2bin[4]),
.Q(p_22_out[4]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[5]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(gray2bin[5]),
.Q(p_22_out[5]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[6]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(gray2bin[6]),
.Q(p_22_out[6]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[7]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(gray2bin[7]),
.Q(p_22_out[7]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[8]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(p_0_out_0),
.Q(p_22_out[8]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[9]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(p_5_out),
.Q(p_22_out[9]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[0]_i_1
(.I0(\gic0.gc0.count_d2_reg[9] [0]),
.I1(\gic0.gc0.count_d2_reg[9] [1]),
.O(bin2gray[0]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[1]_i_1
(.I0(\gic0.gc0.count_d2_reg[9] [1]),
.I1(\gic0.gc0.count_d2_reg[9] [2]),
.O(bin2gray[1]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[2]_i_1
(.I0(\gic0.gc0.count_d2_reg[9] [2]),
.I1(\gic0.gc0.count_d2_reg[9] [3]),
.O(bin2gray[2]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[3]_i_1
(.I0(\gic0.gc0.count_d2_reg[9] [3]),
.I1(\gic0.gc0.count_d2_reg[9] [4]),
.O(bin2gray[3]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[4]_i_1
(.I0(\gic0.gc0.count_d2_reg[9] [4]),
.I1(\gic0.gc0.count_d2_reg[9] [5]),
.O(bin2gray[4]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[5]_i_1
(.I0(\gic0.gc0.count_d2_reg[9] [5]),
.I1(\gic0.gc0.count_d2_reg[9] [6]),
.O(bin2gray[5]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[6]_i_1
(.I0(\gic0.gc0.count_d2_reg[9] [6]),
.I1(\gic0.gc0.count_d2_reg[9] [7]),
.O(bin2gray[6]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[7]_i_1
(.I0(\gic0.gc0.count_d2_reg[9] [7]),
.I1(\gic0.gc0.count_d2_reg[9] [8]),
.O(bin2gray[7]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[8]_i_1
(.I0(\gic0.gc0.count_d2_reg[9] [8]),
.I1(\gic0.gc0.count_d2_reg[9] [9]),
.O(bin2gray[8]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[0]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[0]),
.Q(wr_pntr_gc[0]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[1]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[1]),
.Q(wr_pntr_gc[1]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[2]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[2]),
.Q(wr_pntr_gc[2]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[3]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[3]),
.Q(wr_pntr_gc[3]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[4]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[4]),
.Q(wr_pntr_gc[4]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[5]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[5]),
.Q(wr_pntr_gc[5]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[6]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[6]),
.Q(wr_pntr_gc[6]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[7]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[7]),
.Q(wr_pntr_gc[7]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[8]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[8]),
.Q(wr_pntr_gc[8]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[9]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(\gic0.gc0.count_d2_reg[9] [9]),
.Q(wr_pntr_gc[9]));
LUT2 #(
.INIT(4'h9))
\rd_dc_i[3]_i_2
(.I0(p_22_out[3]),
.I1(Q[3]),
.O(\rd_dc_i[3]_i_2_n_0 ));
LUT2 #(
.INIT(4'h9))
\rd_dc_i[3]_i_3
(.I0(p_22_out[2]),
.I1(Q[2]),
.O(\rd_dc_i[3]_i_3_n_0 ));
LUT2 #(
.INIT(4'h9))
\rd_dc_i[3]_i_4
(.I0(p_22_out[1]),
.I1(Q[1]),
.O(\rd_dc_i[3]_i_4_n_0 ));
LUT2 #(
.INIT(4'h9))
\rd_dc_i[3]_i_5
(.I0(p_22_out[0]),
.I1(Q[0]),
.O(\rd_dc_i[3]_i_5_n_0 ));
LUT2 #(
.INIT(4'h9))
\rd_dc_i[7]_i_2
(.I0(p_22_out[7]),
.I1(Q[7]),
.O(\rd_dc_i[7]_i_2_n_0 ));
LUT2 #(
.INIT(4'h9))
\rd_dc_i[7]_i_3
(.I0(p_22_out[6]),
.I1(Q[6]),
.O(\rd_dc_i[7]_i_3_n_0 ));
LUT2 #(
.INIT(4'h9))
\rd_dc_i[7]_i_4
(.I0(p_22_out[5]),
.I1(Q[5]),
.O(\rd_dc_i[7]_i_4_n_0 ));
LUT2 #(
.INIT(4'h9))
\rd_dc_i[7]_i_5
(.I0(p_22_out[4]),
.I1(Q[4]),
.O(\rd_dc_i[7]_i_5_n_0 ));
LUT2 #(
.INIT(4'h9))
\rd_dc_i[9]_i_2
(.I0(p_22_out[9]),
.I1(Q[9]),
.O(\rd_dc_i[9]_i_2_n_0 ));
LUT2 #(
.INIT(4'h9))
\rd_dc_i[9]_i_3
(.I0(p_22_out[8]),
.I1(Q[8]),
.O(\rd_dc_i[9]_i_3_n_0 ));
CARRY4 \rd_dc_i_reg[3]_i_1
(.CI(1'b0),
.CO({\rd_dc_i_reg[3]_i_1_n_0 ,\rd_dc_i_reg[3]_i_1_n_1 ,\rd_dc_i_reg[3]_i_1_n_2 ,\rd_dc_i_reg[3]_i_1_n_3 }),
.CYINIT(1'b1),
.DI(p_22_out[3:0]),
.O({\rd_dc_i_reg[9] [2:0],\NLW_rd_dc_i_reg[3]_i_1_O_UNCONNECTED [0]}),
.S({\rd_dc_i[3]_i_2_n_0 ,\rd_dc_i[3]_i_3_n_0 ,\rd_dc_i[3]_i_4_n_0 ,\rd_dc_i[3]_i_5_n_0 }));
CARRY4 \rd_dc_i_reg[7]_i_1
(.CI(\rd_dc_i_reg[3]_i_1_n_0 ),
.CO({\rd_dc_i_reg[7]_i_1_n_0 ,\rd_dc_i_reg[7]_i_1_n_1 ,\rd_dc_i_reg[7]_i_1_n_2 ,\rd_dc_i_reg[7]_i_1_n_3 }),
.CYINIT(1'b0),
.DI(p_22_out[7:4]),
.O(\rd_dc_i_reg[9] [6:3]),
.S({\rd_dc_i[7]_i_2_n_0 ,\rd_dc_i[7]_i_3_n_0 ,\rd_dc_i[7]_i_4_n_0 ,\rd_dc_i[7]_i_5_n_0 }));
CARRY4 \rd_dc_i_reg[9]_i_1
(.CI(\rd_dc_i_reg[7]_i_1_n_0 ),
.CO({\NLW_rd_dc_i_reg[9]_i_1_CO_UNCONNECTED [3:1],\rd_dc_i_reg[9]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,p_22_out[8]}),
.O({\NLW_rd_dc_i_reg[9]_i_1_O_UNCONNECTED [3:2],\rd_dc_i_reg[9] [8:7]}),
.S({1'b0,1'b0,\rd_dc_i[9]_i_2_n_0 ,\rd_dc_i[9]_i_3_n_0 }));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare
(comp1,
\gnxpm_cdc.rd_pntr_bin_reg[6] ,
v1_reg_0);
output comp1;
input [3:0]\gnxpm_cdc.rd_pntr_bin_reg[6] ;
input [0:0]v1_reg_0;
wire carrynet_0;
wire carrynet_1;
wire carrynet_2;
wire carrynet_3;
wire comp1;
wire [3:0]\gnxpm_cdc.rd_pntr_bin_reg[6] ;
wire [0:0]v1_reg_0;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({carrynet_3,carrynet_2,carrynet_1,carrynet_0}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S(\gnxpm_cdc.rd_pntr_bin_reg[6] ));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(carrynet_3),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:1],comp1}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:1],1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:1],v1_reg_0}));
endmodule
(* ORIG_REF_NAME = "compare" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_3
(ram_full_fb_i_reg,
v1_reg,
out,
wr_en,
wr_rst_busy,
comp1);
output ram_full_fb_i_reg;
input [4:0]v1_reg;
input out;
input wr_en;
input wr_rst_busy;
input comp1;
wire carrynet_0;
wire carrynet_1;
wire carrynet_2;
wire carrynet_3;
wire comp1;
wire comp2;
wire out;
wire ram_full_fb_i_reg;
wire [4:0]v1_reg;
wire wr_en;
wire wr_rst_busy;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({carrynet_3,carrynet_2,carrynet_1,carrynet_0}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S(v1_reg[3:0]));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(carrynet_3),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:1],comp2}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:1],1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:1],v1_reg[4]}));
LUT5 #(
.INIT(32'h00FF0020))
ram_full_i_i_1
(.I0(comp2),
.I1(out),
.I2(wr_en),
.I3(wr_rst_busy),
.I4(comp1),
.O(ram_full_fb_i_reg));
endmodule
(* ORIG_REF_NAME = "compare" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_4
(ram_empty_fb_i_reg,
v1_reg,
rd_en,
out,
comp1);
output ram_empty_fb_i_reg;
input [4:0]v1_reg;
input rd_en;
input out;
input comp1;
wire carrynet_0;
wire carrynet_1;
wire carrynet_2;
wire carrynet_3;
wire comp0;
wire comp1;
wire out;
wire ram_empty_fb_i_reg;
wire rd_en;
wire [4:0]v1_reg;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({carrynet_3,carrynet_2,carrynet_1,carrynet_0}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S(v1_reg[3:0]));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(carrynet_3),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:1],comp0}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:1],1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:1],v1_reg[4]}));
LUT4 #(
.INIT(16'hAEAA))
ram_empty_i_i_1
(.I0(comp0),
.I1(rd_en),
.I2(out),
.I3(comp1),
.O(ram_empty_fb_i_reg));
endmodule
(* ORIG_REF_NAME = "compare" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_5
(comp1,
v1_reg_0);
output comp1;
input [4:0]v1_reg_0;
wire carrynet_0;
wire carrynet_1;
wire carrynet_2;
wire carrynet_3;
wire comp1;
wire [4:0]v1_reg_0;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({carrynet_3,carrynet_2,carrynet_1,carrynet_0}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S(v1_reg_0[3:0]));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(carrynet_3),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:1],comp1}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:1],1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:1],v1_reg_0[4]}));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo
(wr_rst_busy,
dout,
empty,
full,
rd_data_count,
wr_data_count,
prog_empty,
prog_full,
rd_en,
wr_clk,
rd_clk,
din,
rst,
wr_en);
output wr_rst_busy;
output [63:0]dout;
output empty;
output full;
output [8:0]rd_data_count;
output [9:0]wr_data_count;
output prog_empty;
output prog_full;
input rd_en;
input wr_clk;
input rd_clk;
input [63:0]din;
input rst;
input wr_en;
wire [63:0]din;
wire [63:0]dout;
wire empty;
wire full;
wire [4:0]\gras.rsts/c0/v1_reg ;
wire [4:0]\gras.rsts/c1/v1_reg ;
wire [3:0]\gwas.wsts/c1/v1_reg ;
wire [4:0]\gwas.wsts/c2/v1_reg ;
wire [9:1]minusOp;
wire p_0_out;
wire [9:0]p_0_out_0;
wire [9:0]p_12_out;
wire [7:0]p_13_out;
wire p_18_out;
wire [9:0]p_23_out;
wire p_2_out;
wire [10:2]plusOp;
wire prog_empty;
wire prog_full;
wire rd_clk;
wire [8:0]rd_data_count;
wire rd_en;
wire [9:0]rd_pntr_plus1;
wire [2:0]rd_rst_i;
wire rst;
wire rst_full_ff_i;
wire tmp_ram_rd_en;
wire wr_clk;
wire [9:0]wr_data_count;
wire wr_en;
wire [9:0]wr_pntr_plus2;
wire wr_rst_busy;
wire [1:0]wr_rst_i;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_x_pntrs \gntv_or_sync_fifo.gcx.clkx
(.AR(wr_rst_i[0]),
.D(plusOp),
.Q(p_0_out_0),
.RD_PNTR_WR(p_23_out),
.\gc0.count_reg[9] (rd_pntr_plus1),
.\gic0.gc0.count_d1_reg[7] (p_13_out),
.\gic0.gc0.count_d2_reg[9] (p_12_out),
.\gic0.gc0.count_reg[9] (wr_pntr_plus2),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (rd_rst_i[1]),
.p_0_out(p_0_out),
.rd_clk(rd_clk),
.\rd_dc_i_reg[9] (minusOp),
.v1_reg(\gras.rsts/c0/v1_reg ),
.v1_reg_0(\gras.rsts/c1/v1_reg ),
.v1_reg_1(\gwas.wsts/c1/v1_reg ),
.v1_reg_2(\gwas.wsts/c2/v1_reg ),
.wr_clk(wr_clk));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic \gntv_or_sync_fifo.gl0.rd
(.AR(rd_rst_i[2]),
.D(plusOp),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (p_0_out_0),
.Q(rd_pntr_plus1),
.empty(empty),
.\gnxpm_cdc.wr_pntr_bin_reg[8] (minusOp),
.out(p_2_out),
.p_0_out(p_0_out),
.prog_empty(prog_empty),
.rd_clk(rd_clk),
.rd_data_count(rd_data_count),
.rd_en(rd_en),
.v1_reg(\gras.rsts/c0/v1_reg ),
.v1_reg_0(\gras.rsts/c1/v1_reg ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic \gntv_or_sync_fifo.gl0.wr
(.AR(wr_rst_i[1]),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (p_12_out),
.E(p_18_out),
.Q(p_13_out),
.RD_PNTR_WR(p_23_out),
.full(full),
.\gic0.gc0.count_d1_reg[9] (wr_pntr_plus2),
.\gnxpm_cdc.rd_pntr_bin_reg[6] (\gwas.wsts/c1/v1_reg ),
.out(rst_full_ff_i),
.prog_full(prog_full),
.v1_reg(\gwas.wsts/c2/v1_reg ),
.wr_clk(wr_clk),
.wr_data_count(wr_data_count),
.wr_en(wr_en),
.wr_rst_busy(wr_rst_busy));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory \gntv_or_sync_fifo.mem
(.E(p_18_out),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[9] (p_0_out_0),
.\gic0.gc0.count_d2_reg[9] (p_12_out),
.out(rd_rst_i[0]),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_blk_ramfifo rstblk
(.\gc0.count_reg[1] (rd_rst_i),
.\grstd1.grst_full.grst_f.rst_d3_reg_0 (rst_full_ff_i),
.out(wr_rst_i),
.ram_empty_fb_i_reg(p_2_out),
.rd_clk(rd_clk),
.rd_en(rd_en),
.rst(rst),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk),
.wr_rst_busy(wr_rst_busy));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top
(wr_rst_busy,
dout,
empty,
full,
rd_data_count,
wr_data_count,
prog_empty,
prog_full,
rd_en,
wr_clk,
rd_clk,
din,
rst,
wr_en);
output wr_rst_busy;
output [63:0]dout;
output empty;
output full;
output [8:0]rd_data_count;
output [9:0]wr_data_count;
output prog_empty;
output prog_full;
input rd_en;
input wr_clk;
input rd_clk;
input [63:0]din;
input rst;
input wr_en;
wire [63:0]din;
wire [63:0]dout;
wire empty;
wire full;
wire prog_empty;
wire prog_full;
wire rd_clk;
wire [8:0]rd_data_count;
wire rd_en;
wire rst;
wire wr_clk;
wire [9:0]wr_data_count;
wire wr_en;
wire wr_rst_busy;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo \grf.rf
(.din(din),
.dout(dout),
.empty(empty),
.full(full),
.prog_empty(prog_empty),
.prog_full(prog_full),
.rd_clk(rd_clk),
.rd_data_count(rd_data_count),
.rd_en(rd_en),
.rst(rst),
.wr_clk(wr_clk),
.wr_data_count(wr_data_count),
.wr_en(wr_en),
.wr_rst_busy(wr_rst_busy));
endmodule
(* C_ADD_NGC_CONSTRAINT = "0" *) (* C_APPLICATION_TYPE_AXIS = "0" *) (* C_APPLICATION_TYPE_RACH = "0" *)
(* C_APPLICATION_TYPE_RDCH = "0" *) (* C_APPLICATION_TYPE_WACH = "0" *) (* C_APPLICATION_TYPE_WDCH = "0" *)
(* C_APPLICATION_TYPE_WRCH = "0" *) (* C_AXIS_TDATA_WIDTH = "8" *) (* C_AXIS_TDEST_WIDTH = "1" *)
(* C_AXIS_TID_WIDTH = "1" *) (* C_AXIS_TKEEP_WIDTH = "1" *) (* C_AXIS_TSTRB_WIDTH = "1" *)
(* C_AXIS_TUSER_WIDTH = "4" *) (* C_AXIS_TYPE = "0" *) (* C_AXI_ADDR_WIDTH = "32" *)
(* C_AXI_ARUSER_WIDTH = "1" *) (* C_AXI_AWUSER_WIDTH = "1" *) (* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "64" *) (* C_AXI_ID_WIDTH = "1" *) (* C_AXI_LEN_WIDTH = "8" *)
(* C_AXI_LOCK_WIDTH = "1" *) (* C_AXI_RUSER_WIDTH = "1" *) (* C_AXI_TYPE = "1" *)
(* C_AXI_WUSER_WIDTH = "1" *) (* C_COMMON_CLOCK = "0" *) (* C_COUNT_TYPE = "0" *)
(* C_DATA_COUNT_WIDTH = "10" *) (* C_DEFAULT_VALUE = "BlankString" *) (* C_DIN_WIDTH = "64" *)
(* C_DIN_WIDTH_AXIS = "1" *) (* C_DIN_WIDTH_RACH = "32" *) (* C_DIN_WIDTH_RDCH = "64" *)
(* C_DIN_WIDTH_WACH = "1" *) (* C_DIN_WIDTH_WDCH = "64" *) (* C_DIN_WIDTH_WRCH = "2" *)
(* C_DOUT_RST_VAL = "0" *) (* C_DOUT_WIDTH = "64" *) (* C_ENABLE_RLOCS = "0" *)
(* C_ENABLE_RST_SYNC = "1" *) (* C_EN_SAFETY_CKT = "0" *) (* C_ERROR_INJECTION_TYPE = "0" *)
(* C_ERROR_INJECTION_TYPE_AXIS = "0" *) (* C_ERROR_INJECTION_TYPE_RACH = "0" *) (* C_ERROR_INJECTION_TYPE_RDCH = "0" *)
(* C_ERROR_INJECTION_TYPE_WACH = "0" *) (* C_ERROR_INJECTION_TYPE_WDCH = "0" *) (* C_ERROR_INJECTION_TYPE_WRCH = "0" *)
(* C_FAMILY = "kintex7" *) (* C_FULL_FLAGS_RST_VAL = "1" *) (* C_HAS_ALMOST_EMPTY = "0" *)
(* C_HAS_ALMOST_FULL = "0" *) (* C_HAS_AXIS_TDATA = "1" *) (* C_HAS_AXIS_TDEST = "0" *)
(* C_HAS_AXIS_TID = "0" *) (* C_HAS_AXIS_TKEEP = "0" *) (* C_HAS_AXIS_TLAST = "0" *)
(* C_HAS_AXIS_TREADY = "1" *) (* C_HAS_AXIS_TSTRB = "0" *) (* C_HAS_AXIS_TUSER = "1" *)
(* C_HAS_AXI_ARUSER = "0" *) (* C_HAS_AXI_AWUSER = "0" *) (* C_HAS_AXI_BUSER = "0" *)
(* C_HAS_AXI_ID = "0" *) (* C_HAS_AXI_RD_CHANNEL = "1" *) (* C_HAS_AXI_RUSER = "0" *)
(* C_HAS_AXI_WR_CHANNEL = "1" *) (* C_HAS_AXI_WUSER = "0" *) (* C_HAS_BACKUP = "0" *)
(* C_HAS_DATA_COUNT = "0" *) (* C_HAS_DATA_COUNTS_AXIS = "0" *) (* C_HAS_DATA_COUNTS_RACH = "0" *)
(* C_HAS_DATA_COUNTS_RDCH = "0" *) (* C_HAS_DATA_COUNTS_WACH = "0" *) (* C_HAS_DATA_COUNTS_WDCH = "0" *)
(* C_HAS_DATA_COUNTS_WRCH = "0" *) (* C_HAS_INT_CLK = "0" *) (* C_HAS_MASTER_CE = "0" *)
(* C_HAS_MEMINIT_FILE = "0" *) (* C_HAS_OVERFLOW = "0" *) (* C_HAS_PROG_FLAGS_AXIS = "0" *)
(* C_HAS_PROG_FLAGS_RACH = "0" *) (* C_HAS_PROG_FLAGS_RDCH = "0" *) (* C_HAS_PROG_FLAGS_WACH = "0" *)
(* C_HAS_PROG_FLAGS_WDCH = "0" *) (* C_HAS_PROG_FLAGS_WRCH = "0" *) (* C_HAS_RD_DATA_COUNT = "1" *)
(* C_HAS_RD_RST = "0" *) (* C_HAS_RST = "1" *) (* C_HAS_SLAVE_CE = "0" *)
(* C_HAS_SRST = "0" *) (* C_HAS_UNDERFLOW = "0" *) (* C_HAS_VALID = "0" *)
(* C_HAS_WR_ACK = "0" *) (* C_HAS_WR_DATA_COUNT = "1" *) (* C_HAS_WR_RST = "0" *)
(* C_IMPLEMENTATION_TYPE = "2" *) (* C_IMPLEMENTATION_TYPE_AXIS = "1" *) (* C_IMPLEMENTATION_TYPE_RACH = "1" *)
(* C_IMPLEMENTATION_TYPE_RDCH = "1" *) (* C_IMPLEMENTATION_TYPE_WACH = "1" *) (* C_IMPLEMENTATION_TYPE_WDCH = "1" *)
(* C_IMPLEMENTATION_TYPE_WRCH = "1" *) (* C_INIT_WR_PNTR_VAL = "0" *) (* C_INTERFACE_TYPE = "0" *)
(* C_MEMORY_TYPE = "1" *) (* C_MIF_FILE_NAME = "BlankString" *) (* C_MSGON_VAL = "1" *)
(* C_OPTIMIZATION_MODE = "0" *) (* C_OVERFLOW_LOW = "0" *) (* C_POWER_SAVING_MODE = "0" *)
(* C_PRELOAD_LATENCY = "1" *) (* C_PRELOAD_REGS = "0" *) (* C_PRIM_FIFO_TYPE = "1kx36" *)
(* C_PRIM_FIFO_TYPE_AXIS = "1kx18" *) (* C_PRIM_FIFO_TYPE_RACH = "512x36" *) (* C_PRIM_FIFO_TYPE_RDCH = "1kx36" *)
(* C_PRIM_FIFO_TYPE_WACH = "512x36" *) (* C_PRIM_FIFO_TYPE_WDCH = "1kx36" *) (* C_PRIM_FIFO_TYPE_WRCH = "512x36" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL = "313" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "1022" *) (* C_PROG_EMPTY_THRESH_NEGATE_VAL = "314" *) (* C_PROG_EMPTY_TYPE = "1" *)
(* C_PROG_EMPTY_TYPE_AXIS = "0" *) (* C_PROG_EMPTY_TYPE_RACH = "0" *) (* C_PROG_EMPTY_TYPE_RDCH = "0" *)
(* C_PROG_EMPTY_TYPE_WACH = "0" *) (* C_PROG_EMPTY_TYPE_WDCH = "0" *) (* C_PROG_EMPTY_TYPE_WRCH = "0" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL = "66" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *) (* C_PROG_FULL_THRESH_NEGATE_VAL = "65" *) (* C_PROG_FULL_TYPE = "1" *)
(* C_PROG_FULL_TYPE_AXIS = "0" *) (* C_PROG_FULL_TYPE_RACH = "0" *) (* C_PROG_FULL_TYPE_RDCH = "0" *)
(* C_PROG_FULL_TYPE_WACH = "0" *) (* C_PROG_FULL_TYPE_WDCH = "0" *) (* C_PROG_FULL_TYPE_WRCH = "0" *)
(* C_RACH_TYPE = "0" *) (* C_RDCH_TYPE = "0" *) (* C_RD_DATA_COUNT_WIDTH = "9" *)
(* C_RD_DEPTH = "1024" *) (* C_RD_FREQ = "1" *) (* C_RD_PNTR_WIDTH = "10" *)
(* C_REG_SLICE_MODE_AXIS = "0" *) (* C_REG_SLICE_MODE_RACH = "0" *) (* C_REG_SLICE_MODE_RDCH = "0" *)
(* C_REG_SLICE_MODE_WACH = "0" *) (* C_REG_SLICE_MODE_WDCH = "0" *) (* C_REG_SLICE_MODE_WRCH = "0" *)
(* C_SELECT_XPM = "0" *) (* C_SYNCHRONIZER_STAGE = "2" *) (* C_UNDERFLOW_LOW = "0" *)
(* C_USE_COMMON_OVERFLOW = "0" *) (* C_USE_COMMON_UNDERFLOW = "0" *) (* C_USE_DEFAULT_SETTINGS = "0" *)
(* C_USE_DOUT_RST = "1" *) (* C_USE_ECC = "0" *) (* C_USE_ECC_AXIS = "0" *)
(* C_USE_ECC_RACH = "0" *) (* C_USE_ECC_RDCH = "0" *) (* C_USE_ECC_WACH = "0" *)
(* C_USE_ECC_WDCH = "0" *) (* C_USE_ECC_WRCH = "0" *) (* C_USE_EMBEDDED_REG = "0" *)
(* C_USE_FIFO16_FLAGS = "0" *) (* C_USE_FWFT_DATA_COUNT = "0" *) (* C_USE_PIPELINE_REG = "0" *)
(* C_VALID_LOW = "0" *) (* C_WACH_TYPE = "0" *) (* C_WDCH_TYPE = "0" *)
(* C_WRCH_TYPE = "0" *) (* C_WR_ACK_LOW = "0" *) (* C_WR_DATA_COUNT_WIDTH = "10" *)
(* C_WR_DEPTH = "1024" *) (* C_WR_DEPTH_AXIS = "1024" *) (* C_WR_DEPTH_RACH = "16" *)
(* C_WR_DEPTH_RDCH = "1024" *) (* C_WR_DEPTH_WACH = "16" *) (* C_WR_DEPTH_WDCH = "1024" *)
(* C_WR_DEPTH_WRCH = "16" *) (* C_WR_FREQ = "1" *) (* C_WR_PNTR_WIDTH = "10" *)
(* C_WR_PNTR_WIDTH_AXIS = "10" *) (* C_WR_PNTR_WIDTH_RACH = "4" *) (* C_WR_PNTR_WIDTH_RDCH = "10" *)
(* C_WR_PNTR_WIDTH_WACH = "4" *) (* C_WR_PNTR_WIDTH_WDCH = "10" *) (* C_WR_PNTR_WIDTH_WRCH = "4" *)
(* C_WR_RESPONSE_LATENCY = "1" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2
(backup,
backup_marker,
clk,
rst,
srst,
wr_clk,
wr_rst,
rd_clk,
rd_rst,
din,
wr_en,
rd_en,
prog_empty_thresh,
prog_empty_thresh_assert,
prog_empty_thresh_negate,
prog_full_thresh,
prog_full_thresh_assert,
prog_full_thresh_negate,
int_clk,
injectdbiterr,
injectsbiterr,
sleep,
dout,
full,
almost_full,
wr_ack,
overflow,
empty,
almost_empty,
valid,
underflow,
data_count,
rd_data_count,
wr_data_count,
prog_full,
prog_empty,
sbiterr,
dbiterr,
wr_rst_busy,
rd_rst_busy,
m_aclk,
s_aclk,
s_aresetn,
m_aclk_en,
s_aclk_en,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awregion,
s_axi_awuser,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wuser,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_buser,
s_axi_bvalid,
s_axi_bready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awqos,
m_axi_awregion,
m_axi_awuser,
m_axi_awvalid,
m_axi_awready,
m_axi_wid,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wuser,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_buser,
m_axi_bvalid,
m_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arregion,
s_axi_aruser,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_ruser,
s_axi_rvalid,
s_axi_rready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arqos,
m_axi_arregion,
m_axi_aruser,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_ruser,
m_axi_rvalid,
m_axi_rready,
s_axis_tvalid,
s_axis_tready,
s_axis_tdata,
s_axis_tstrb,
s_axis_tkeep,
s_axis_tlast,
s_axis_tid,
s_axis_tdest,
s_axis_tuser,
m_axis_tvalid,
m_axis_tready,
m_axis_tdata,
m_axis_tstrb,
m_axis_tkeep,
m_axis_tlast,
m_axis_tid,
m_axis_tdest,
m_axis_tuser,
axi_aw_injectsbiterr,
axi_aw_injectdbiterr,
axi_aw_prog_full_thresh,
axi_aw_prog_empty_thresh,
axi_aw_data_count,
axi_aw_wr_data_count,
axi_aw_rd_data_count,
axi_aw_sbiterr,
axi_aw_dbiterr,
axi_aw_overflow,
axi_aw_underflow,
axi_aw_prog_full,
axi_aw_prog_empty,
axi_w_injectsbiterr,
axi_w_injectdbiterr,
axi_w_prog_full_thresh,
axi_w_prog_empty_thresh,
axi_w_data_count,
axi_w_wr_data_count,
axi_w_rd_data_count,
axi_w_sbiterr,
axi_w_dbiterr,
axi_w_overflow,
axi_w_underflow,
axi_w_prog_full,
axi_w_prog_empty,
axi_b_injectsbiterr,
axi_b_injectdbiterr,
axi_b_prog_full_thresh,
axi_b_prog_empty_thresh,
axi_b_data_count,
axi_b_wr_data_count,
axi_b_rd_data_count,
axi_b_sbiterr,
axi_b_dbiterr,
axi_b_overflow,
axi_b_underflow,
axi_b_prog_full,
axi_b_prog_empty,
axi_ar_injectsbiterr,
axi_ar_injectdbiterr,
axi_ar_prog_full_thresh,
axi_ar_prog_empty_thresh,
axi_ar_data_count,
axi_ar_wr_data_count,
axi_ar_rd_data_count,
axi_ar_sbiterr,
axi_ar_dbiterr,
axi_ar_overflow,
axi_ar_underflow,
axi_ar_prog_full,
axi_ar_prog_empty,
axi_r_injectsbiterr,
axi_r_injectdbiterr,
axi_r_prog_full_thresh,
axi_r_prog_empty_thresh,
axi_r_data_count,
axi_r_wr_data_count,
axi_r_rd_data_count,
axi_r_sbiterr,
axi_r_dbiterr,
axi_r_overflow,
axi_r_underflow,
axi_r_prog_full,
axi_r_prog_empty,
axis_injectsbiterr,
axis_injectdbiterr,
axis_prog_full_thresh,
axis_prog_empty_thresh,
axis_data_count,
axis_wr_data_count,
axis_rd_data_count,
axis_sbiterr,
axis_dbiterr,
axis_overflow,
axis_underflow,
axis_prog_full,
axis_prog_empty);
input backup;
input backup_marker;
input clk;
input rst;
input srst;
input wr_clk;
input wr_rst;
input rd_clk;
input rd_rst;
input [63:0]din;
input wr_en;
input rd_en;
input [9:0]prog_empty_thresh;
input [9:0]prog_empty_thresh_assert;
input [9:0]prog_empty_thresh_negate;
input [9:0]prog_full_thresh;
input [9:0]prog_full_thresh_assert;
input [9:0]prog_full_thresh_negate;
input int_clk;
input injectdbiterr;
input injectsbiterr;
input sleep;
output [63:0]dout;
output full;
output almost_full;
output wr_ack;
output overflow;
output empty;
output almost_empty;
output valid;
output underflow;
output [9:0]data_count;
output [8:0]rd_data_count;
output [9:0]wr_data_count;
output prog_full;
output prog_empty;
output sbiterr;
output dbiterr;
output wr_rst_busy;
output rd_rst_busy;
input m_aclk;
input s_aclk;
input s_aresetn;
input m_aclk_en;
input s_aclk_en;
input [0:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awqos;
input [3:0]s_axi_awregion;
input [0:0]s_axi_awuser;
input s_axi_awvalid;
output s_axi_awready;
input [0:0]s_axi_wid;
input [63:0]s_axi_wdata;
input [7:0]s_axi_wstrb;
input s_axi_wlast;
input [0:0]s_axi_wuser;
input s_axi_wvalid;
output s_axi_wready;
output [0:0]s_axi_bid;
output [1:0]s_axi_bresp;
output [0:0]s_axi_buser;
output s_axi_bvalid;
input s_axi_bready;
output [0:0]m_axi_awid;
output [31:0]m_axi_awaddr;
output [7:0]m_axi_awlen;
output [2:0]m_axi_awsize;
output [1:0]m_axi_awburst;
output [0:0]m_axi_awlock;
output [3:0]m_axi_awcache;
output [2:0]m_axi_awprot;
output [3:0]m_axi_awqos;
output [3:0]m_axi_awregion;
output [0:0]m_axi_awuser;
output m_axi_awvalid;
input m_axi_awready;
output [0:0]m_axi_wid;
output [63:0]m_axi_wdata;
output [7:0]m_axi_wstrb;
output m_axi_wlast;
output [0:0]m_axi_wuser;
output m_axi_wvalid;
input m_axi_wready;
input [0:0]m_axi_bid;
input [1:0]m_axi_bresp;
input [0:0]m_axi_buser;
input m_axi_bvalid;
output m_axi_bready;
input [0:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arqos;
input [3:0]s_axi_arregion;
input [0:0]s_axi_aruser;
input s_axi_arvalid;
output s_axi_arready;
output [0:0]s_axi_rid;
output [63:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output [0:0]s_axi_ruser;
output s_axi_rvalid;
input s_axi_rready;
output [0:0]m_axi_arid;
output [31:0]m_axi_araddr;
output [7:0]m_axi_arlen;
output [2:0]m_axi_arsize;
output [1:0]m_axi_arburst;
output [0:0]m_axi_arlock;
output [3:0]m_axi_arcache;
output [2:0]m_axi_arprot;
output [3:0]m_axi_arqos;
output [3:0]m_axi_arregion;
output [0:0]m_axi_aruser;
output m_axi_arvalid;
input m_axi_arready;
input [0:0]m_axi_rid;
input [63:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rlast;
input [0:0]m_axi_ruser;
input m_axi_rvalid;
output m_axi_rready;
input s_axis_tvalid;
output s_axis_tready;
input [7:0]s_axis_tdata;
input [0:0]s_axis_tstrb;
input [0:0]s_axis_tkeep;
input s_axis_tlast;
input [0:0]s_axis_tid;
input [0:0]s_axis_tdest;
input [3:0]s_axis_tuser;
output m_axis_tvalid;
input m_axis_tready;
output [7:0]m_axis_tdata;
output [0:0]m_axis_tstrb;
output [0:0]m_axis_tkeep;
output m_axis_tlast;
output [0:0]m_axis_tid;
output [0:0]m_axis_tdest;
output [3:0]m_axis_tuser;
input axi_aw_injectsbiterr;
input axi_aw_injectdbiterr;
input [3:0]axi_aw_prog_full_thresh;
input [3:0]axi_aw_prog_empty_thresh;
output [4:0]axi_aw_data_count;
output [4:0]axi_aw_wr_data_count;
output [4:0]axi_aw_rd_data_count;
output axi_aw_sbiterr;
output axi_aw_dbiterr;
output axi_aw_overflow;
output axi_aw_underflow;
output axi_aw_prog_full;
output axi_aw_prog_empty;
input axi_w_injectsbiterr;
input axi_w_injectdbiterr;
input [9:0]axi_w_prog_full_thresh;
input [9:0]axi_w_prog_empty_thresh;
output [10:0]axi_w_data_count;
output [10:0]axi_w_wr_data_count;
output [10:0]axi_w_rd_data_count;
output axi_w_sbiterr;
output axi_w_dbiterr;
output axi_w_overflow;
output axi_w_underflow;
output axi_w_prog_full;
output axi_w_prog_empty;
input axi_b_injectsbiterr;
input axi_b_injectdbiterr;
input [3:0]axi_b_prog_full_thresh;
input [3:0]axi_b_prog_empty_thresh;
output [4:0]axi_b_data_count;
output [4:0]axi_b_wr_data_count;
output [4:0]axi_b_rd_data_count;
output axi_b_sbiterr;
output axi_b_dbiterr;
output axi_b_overflow;
output axi_b_underflow;
output axi_b_prog_full;
output axi_b_prog_empty;
input axi_ar_injectsbiterr;
input axi_ar_injectdbiterr;
input [3:0]axi_ar_prog_full_thresh;
input [3:0]axi_ar_prog_empty_thresh;
output [4:0]axi_ar_data_count;
output [4:0]axi_ar_wr_data_count;
output [4:0]axi_ar_rd_data_count;
output axi_ar_sbiterr;
output axi_ar_dbiterr;
output axi_ar_overflow;
output axi_ar_underflow;
output axi_ar_prog_full;
output axi_ar_prog_empty;
input axi_r_injectsbiterr;
input axi_r_injectdbiterr;
input [9:0]axi_r_prog_full_thresh;
input [9:0]axi_r_prog_empty_thresh;
output [10:0]axi_r_data_count;
output [10:0]axi_r_wr_data_count;
output [10:0]axi_r_rd_data_count;
output axi_r_sbiterr;
output axi_r_dbiterr;
output axi_r_overflow;
output axi_r_underflow;
output axi_r_prog_full;
output axi_r_prog_empty;
input axis_injectsbiterr;
input axis_injectdbiterr;
input [9:0]axis_prog_full_thresh;
input [9:0]axis_prog_empty_thresh;
output [10:0]axis_data_count;
output [10:0]axis_wr_data_count;
output [10:0]axis_rd_data_count;
output axis_sbiterr;
output axis_dbiterr;
output axis_overflow;
output axis_underflow;
output axis_prog_full;
output axis_prog_empty;
wire \<const0> ;
wire \<const1> ;
wire [63:0]din;
wire [63:0]dout;
wire empty;
wire full;
wire prog_empty;
wire prog_full;
wire rd_clk;
wire [8:0]rd_data_count;
wire rd_en;
wire rst;
wire wr_clk;
wire [9:0]wr_data_count;
wire wr_en;
wire wr_rst_busy;
assign almost_empty = \<const0> ;
assign almost_full = \<const0> ;
assign axi_ar_data_count[4] = \<const0> ;
assign axi_ar_data_count[3] = \<const0> ;
assign axi_ar_data_count[2] = \<const0> ;
assign axi_ar_data_count[1] = \<const0> ;
assign axi_ar_data_count[0] = \<const0> ;
assign axi_ar_dbiterr = \<const0> ;
assign axi_ar_overflow = \<const0> ;
assign axi_ar_prog_empty = \<const1> ;
assign axi_ar_prog_full = \<const0> ;
assign axi_ar_rd_data_count[4] = \<const0> ;
assign axi_ar_rd_data_count[3] = \<const0> ;
assign axi_ar_rd_data_count[2] = \<const0> ;
assign axi_ar_rd_data_count[1] = \<const0> ;
assign axi_ar_rd_data_count[0] = \<const0> ;
assign axi_ar_sbiterr = \<const0> ;
assign axi_ar_underflow = \<const0> ;
assign axi_ar_wr_data_count[4] = \<const0> ;
assign axi_ar_wr_data_count[3] = \<const0> ;
assign axi_ar_wr_data_count[2] = \<const0> ;
assign axi_ar_wr_data_count[1] = \<const0> ;
assign axi_ar_wr_data_count[0] = \<const0> ;
assign axi_aw_data_count[4] = \<const0> ;
assign axi_aw_data_count[3] = \<const0> ;
assign axi_aw_data_count[2] = \<const0> ;
assign axi_aw_data_count[1] = \<const0> ;
assign axi_aw_data_count[0] = \<const0> ;
assign axi_aw_dbiterr = \<const0> ;
assign axi_aw_overflow = \<const0> ;
assign axi_aw_prog_empty = \<const1> ;
assign axi_aw_prog_full = \<const0> ;
assign axi_aw_rd_data_count[4] = \<const0> ;
assign axi_aw_rd_data_count[3] = \<const0> ;
assign axi_aw_rd_data_count[2] = \<const0> ;
assign axi_aw_rd_data_count[1] = \<const0> ;
assign axi_aw_rd_data_count[0] = \<const0> ;
assign axi_aw_sbiterr = \<const0> ;
assign axi_aw_underflow = \<const0> ;
assign axi_aw_wr_data_count[4] = \<const0> ;
assign axi_aw_wr_data_count[3] = \<const0> ;
assign axi_aw_wr_data_count[2] = \<const0> ;
assign axi_aw_wr_data_count[1] = \<const0> ;
assign axi_aw_wr_data_count[0] = \<const0> ;
assign axi_b_data_count[4] = \<const0> ;
assign axi_b_data_count[3] = \<const0> ;
assign axi_b_data_count[2] = \<const0> ;
assign axi_b_data_count[1] = \<const0> ;
assign axi_b_data_count[0] = \<const0> ;
assign axi_b_dbiterr = \<const0> ;
assign axi_b_overflow = \<const0> ;
assign axi_b_prog_empty = \<const1> ;
assign axi_b_prog_full = \<const0> ;
assign axi_b_rd_data_count[4] = \<const0> ;
assign axi_b_rd_data_count[3] = \<const0> ;
assign axi_b_rd_data_count[2] = \<const0> ;
assign axi_b_rd_data_count[1] = \<const0> ;
assign axi_b_rd_data_count[0] = \<const0> ;
assign axi_b_sbiterr = \<const0> ;
assign axi_b_underflow = \<const0> ;
assign axi_b_wr_data_count[4] = \<const0> ;
assign axi_b_wr_data_count[3] = \<const0> ;
assign axi_b_wr_data_count[2] = \<const0> ;
assign axi_b_wr_data_count[1] = \<const0> ;
assign axi_b_wr_data_count[0] = \<const0> ;
assign axi_r_data_count[10] = \<const0> ;
assign axi_r_data_count[9] = \<const0> ;
assign axi_r_data_count[8] = \<const0> ;
assign axi_r_data_count[7] = \<const0> ;
assign axi_r_data_count[6] = \<const0> ;
assign axi_r_data_count[5] = \<const0> ;
assign axi_r_data_count[4] = \<const0> ;
assign axi_r_data_count[3] = \<const0> ;
assign axi_r_data_count[2] = \<const0> ;
assign axi_r_data_count[1] = \<const0> ;
assign axi_r_data_count[0] = \<const0> ;
assign axi_r_dbiterr = \<const0> ;
assign axi_r_overflow = \<const0> ;
assign axi_r_prog_empty = \<const1> ;
assign axi_r_prog_full = \<const0> ;
assign axi_r_rd_data_count[10] = \<const0> ;
assign axi_r_rd_data_count[9] = \<const0> ;
assign axi_r_rd_data_count[8] = \<const0> ;
assign axi_r_rd_data_count[7] = \<const0> ;
assign axi_r_rd_data_count[6] = \<const0> ;
assign axi_r_rd_data_count[5] = \<const0> ;
assign axi_r_rd_data_count[4] = \<const0> ;
assign axi_r_rd_data_count[3] = \<const0> ;
assign axi_r_rd_data_count[2] = \<const0> ;
assign axi_r_rd_data_count[1] = \<const0> ;
assign axi_r_rd_data_count[0] = \<const0> ;
assign axi_r_sbiterr = \<const0> ;
assign axi_r_underflow = \<const0> ;
assign axi_r_wr_data_count[10] = \<const0> ;
assign axi_r_wr_data_count[9] = \<const0> ;
assign axi_r_wr_data_count[8] = \<const0> ;
assign axi_r_wr_data_count[7] = \<const0> ;
assign axi_r_wr_data_count[6] = \<const0> ;
assign axi_r_wr_data_count[5] = \<const0> ;
assign axi_r_wr_data_count[4] = \<const0> ;
assign axi_r_wr_data_count[3] = \<const0> ;
assign axi_r_wr_data_count[2] = \<const0> ;
assign axi_r_wr_data_count[1] = \<const0> ;
assign axi_r_wr_data_count[0] = \<const0> ;
assign axi_w_data_count[10] = \<const0> ;
assign axi_w_data_count[9] = \<const0> ;
assign axi_w_data_count[8] = \<const0> ;
assign axi_w_data_count[7] = \<const0> ;
assign axi_w_data_count[6] = \<const0> ;
assign axi_w_data_count[5] = \<const0> ;
assign axi_w_data_count[4] = \<const0> ;
assign axi_w_data_count[3] = \<const0> ;
assign axi_w_data_count[2] = \<const0> ;
assign axi_w_data_count[1] = \<const0> ;
assign axi_w_data_count[0] = \<const0> ;
assign axi_w_dbiterr = \<const0> ;
assign axi_w_overflow = \<const0> ;
assign axi_w_prog_empty = \<const1> ;
assign axi_w_prog_full = \<const0> ;
assign axi_w_rd_data_count[10] = \<const0> ;
assign axi_w_rd_data_count[9] = \<const0> ;
assign axi_w_rd_data_count[8] = \<const0> ;
assign axi_w_rd_data_count[7] = \<const0> ;
assign axi_w_rd_data_count[6] = \<const0> ;
assign axi_w_rd_data_count[5] = \<const0> ;
assign axi_w_rd_data_count[4] = \<const0> ;
assign axi_w_rd_data_count[3] = \<const0> ;
assign axi_w_rd_data_count[2] = \<const0> ;
assign axi_w_rd_data_count[1] = \<const0> ;
assign axi_w_rd_data_count[0] = \<const0> ;
assign axi_w_sbiterr = \<const0> ;
assign axi_w_underflow = \<const0> ;
assign axi_w_wr_data_count[10] = \<const0> ;
assign axi_w_wr_data_count[9] = \<const0> ;
assign axi_w_wr_data_count[8] = \<const0> ;
assign axi_w_wr_data_count[7] = \<const0> ;
assign axi_w_wr_data_count[6] = \<const0> ;
assign axi_w_wr_data_count[5] = \<const0> ;
assign axi_w_wr_data_count[4] = \<const0> ;
assign axi_w_wr_data_count[3] = \<const0> ;
assign axi_w_wr_data_count[2] = \<const0> ;
assign axi_w_wr_data_count[1] = \<const0> ;
assign axi_w_wr_data_count[0] = \<const0> ;
assign axis_data_count[10] = \<const0> ;
assign axis_data_count[9] = \<const0> ;
assign axis_data_count[8] = \<const0> ;
assign axis_data_count[7] = \<const0> ;
assign axis_data_count[6] = \<const0> ;
assign axis_data_count[5] = \<const0> ;
assign axis_data_count[4] = \<const0> ;
assign axis_data_count[3] = \<const0> ;
assign axis_data_count[2] = \<const0> ;
assign axis_data_count[1] = \<const0> ;
assign axis_data_count[0] = \<const0> ;
assign axis_dbiterr = \<const0> ;
assign axis_overflow = \<const0> ;
assign axis_prog_empty = \<const1> ;
assign axis_prog_full = \<const0> ;
assign axis_rd_data_count[10] = \<const0> ;
assign axis_rd_data_count[9] = \<const0> ;
assign axis_rd_data_count[8] = \<const0> ;
assign axis_rd_data_count[7] = \<const0> ;
assign axis_rd_data_count[6] = \<const0> ;
assign axis_rd_data_count[5] = \<const0> ;
assign axis_rd_data_count[4] = \<const0> ;
assign axis_rd_data_count[3] = \<const0> ;
assign axis_rd_data_count[2] = \<const0> ;
assign axis_rd_data_count[1] = \<const0> ;
assign axis_rd_data_count[0] = \<const0> ;
assign axis_sbiterr = \<const0> ;
assign axis_underflow = \<const0> ;
assign axis_wr_data_count[10] = \<const0> ;
assign axis_wr_data_count[9] = \<const0> ;
assign axis_wr_data_count[8] = \<const0> ;
assign axis_wr_data_count[7] = \<const0> ;
assign axis_wr_data_count[6] = \<const0> ;
assign axis_wr_data_count[5] = \<const0> ;
assign axis_wr_data_count[4] = \<const0> ;
assign axis_wr_data_count[3] = \<const0> ;
assign axis_wr_data_count[2] = \<const0> ;
assign axis_wr_data_count[1] = \<const0> ;
assign axis_wr_data_count[0] = \<const0> ;
assign data_count[9] = \<const0> ;
assign data_count[8] = \<const0> ;
assign data_count[7] = \<const0> ;
assign data_count[6] = \<const0> ;
assign data_count[5] = \<const0> ;
assign data_count[4] = \<const0> ;
assign data_count[3] = \<const0> ;
assign data_count[2] = \<const0> ;
assign data_count[1] = \<const0> ;
assign data_count[0] = \<const0> ;
assign dbiterr = \<const0> ;
assign m_axi_araddr[31] = \<const0> ;
assign m_axi_araddr[30] = \<const0> ;
assign m_axi_araddr[29] = \<const0> ;
assign m_axi_araddr[28] = \<const0> ;
assign m_axi_araddr[27] = \<const0> ;
assign m_axi_araddr[26] = \<const0> ;
assign m_axi_araddr[25] = \<const0> ;
assign m_axi_araddr[24] = \<const0> ;
assign m_axi_araddr[23] = \<const0> ;
assign m_axi_araddr[22] = \<const0> ;
assign m_axi_araddr[21] = \<const0> ;
assign m_axi_araddr[20] = \<const0> ;
assign m_axi_araddr[19] = \<const0> ;
assign m_axi_araddr[18] = \<const0> ;
assign m_axi_araddr[17] = \<const0> ;
assign m_axi_araddr[16] = \<const0> ;
assign m_axi_araddr[15] = \<const0> ;
assign m_axi_araddr[14] = \<const0> ;
assign m_axi_araddr[13] = \<const0> ;
assign m_axi_araddr[12] = \<const0> ;
assign m_axi_araddr[11] = \<const0> ;
assign m_axi_araddr[10] = \<const0> ;
assign m_axi_araddr[9] = \<const0> ;
assign m_axi_araddr[8] = \<const0> ;
assign m_axi_araddr[7] = \<const0> ;
assign m_axi_araddr[6] = \<const0> ;
assign m_axi_araddr[5] = \<const0> ;
assign m_axi_araddr[4] = \<const0> ;
assign m_axi_araddr[3] = \<const0> ;
assign m_axi_araddr[2] = \<const0> ;
assign m_axi_araddr[1] = \<const0> ;
assign m_axi_araddr[0] = \<const0> ;
assign m_axi_arburst[1] = \<const0> ;
assign m_axi_arburst[0] = \<const0> ;
assign m_axi_arcache[3] = \<const0> ;
assign m_axi_arcache[2] = \<const0> ;
assign m_axi_arcache[1] = \<const0> ;
assign m_axi_arcache[0] = \<const0> ;
assign m_axi_arid[0] = \<const0> ;
assign m_axi_arlen[7] = \<const0> ;
assign m_axi_arlen[6] = \<const0> ;
assign m_axi_arlen[5] = \<const0> ;
assign m_axi_arlen[4] = \<const0> ;
assign m_axi_arlen[3] = \<const0> ;
assign m_axi_arlen[2] = \<const0> ;
assign m_axi_arlen[1] = \<const0> ;
assign m_axi_arlen[0] = \<const0> ;
assign m_axi_arlock[0] = \<const0> ;
assign m_axi_arprot[2] = \<const0> ;
assign m_axi_arprot[1] = \<const0> ;
assign m_axi_arprot[0] = \<const0> ;
assign m_axi_arqos[3] = \<const0> ;
assign m_axi_arqos[2] = \<const0> ;
assign m_axi_arqos[1] = \<const0> ;
assign m_axi_arqos[0] = \<const0> ;
assign m_axi_arregion[3] = \<const0> ;
assign m_axi_arregion[2] = \<const0> ;
assign m_axi_arregion[1] = \<const0> ;
assign m_axi_arregion[0] = \<const0> ;
assign m_axi_arsize[2] = \<const0> ;
assign m_axi_arsize[1] = \<const0> ;
assign m_axi_arsize[0] = \<const0> ;
assign m_axi_aruser[0] = \<const0> ;
assign m_axi_arvalid = \<const0> ;
assign m_axi_awaddr[31] = \<const0> ;
assign m_axi_awaddr[30] = \<const0> ;
assign m_axi_awaddr[29] = \<const0> ;
assign m_axi_awaddr[28] = \<const0> ;
assign m_axi_awaddr[27] = \<const0> ;
assign m_axi_awaddr[26] = \<const0> ;
assign m_axi_awaddr[25] = \<const0> ;
assign m_axi_awaddr[24] = \<const0> ;
assign m_axi_awaddr[23] = \<const0> ;
assign m_axi_awaddr[22] = \<const0> ;
assign m_axi_awaddr[21] = \<const0> ;
assign m_axi_awaddr[20] = \<const0> ;
assign m_axi_awaddr[19] = \<const0> ;
assign m_axi_awaddr[18] = \<const0> ;
assign m_axi_awaddr[17] = \<const0> ;
assign m_axi_awaddr[16] = \<const0> ;
assign m_axi_awaddr[15] = \<const0> ;
assign m_axi_awaddr[14] = \<const0> ;
assign m_axi_awaddr[13] = \<const0> ;
assign m_axi_awaddr[12] = \<const0> ;
assign m_axi_awaddr[11] = \<const0> ;
assign m_axi_awaddr[10] = \<const0> ;
assign m_axi_awaddr[9] = \<const0> ;
assign m_axi_awaddr[8] = \<const0> ;
assign m_axi_awaddr[7] = \<const0> ;
assign m_axi_awaddr[6] = \<const0> ;
assign m_axi_awaddr[5] = \<const0> ;
assign m_axi_awaddr[4] = \<const0> ;
assign m_axi_awaddr[3] = \<const0> ;
assign m_axi_awaddr[2] = \<const0> ;
assign m_axi_awaddr[1] = \<const0> ;
assign m_axi_awaddr[0] = \<const0> ;
assign m_axi_awburst[1] = \<const0> ;
assign m_axi_awburst[0] = \<const0> ;
assign m_axi_awcache[3] = \<const0> ;
assign m_axi_awcache[2] = \<const0> ;
assign m_axi_awcache[1] = \<const0> ;
assign m_axi_awcache[0] = \<const0> ;
assign m_axi_awid[0] = \<const0> ;
assign m_axi_awlen[7] = \<const0> ;
assign m_axi_awlen[6] = \<const0> ;
assign m_axi_awlen[5] = \<const0> ;
assign m_axi_awlen[4] = \<const0> ;
assign m_axi_awlen[3] = \<const0> ;
assign m_axi_awlen[2] = \<const0> ;
assign m_axi_awlen[1] = \<const0> ;
assign m_axi_awlen[0] = \<const0> ;
assign m_axi_awlock[0] = \<const0> ;
assign m_axi_awprot[2] = \<const0> ;
assign m_axi_awprot[1] = \<const0> ;
assign m_axi_awprot[0] = \<const0> ;
assign m_axi_awqos[3] = \<const0> ;
assign m_axi_awqos[2] = \<const0> ;
assign m_axi_awqos[1] = \<const0> ;
assign m_axi_awqos[0] = \<const0> ;
assign m_axi_awregion[3] = \<const0> ;
assign m_axi_awregion[2] = \<const0> ;
assign m_axi_awregion[1] = \<const0> ;
assign m_axi_awregion[0] = \<const0> ;
assign m_axi_awsize[2] = \<const0> ;
assign m_axi_awsize[1] = \<const0> ;
assign m_axi_awsize[0] = \<const0> ;
assign m_axi_awuser[0] = \<const0> ;
assign m_axi_awvalid = \<const0> ;
assign m_axi_bready = \<const0> ;
assign m_axi_rready = \<const0> ;
assign m_axi_wdata[63] = \<const0> ;
assign m_axi_wdata[62] = \<const0> ;
assign m_axi_wdata[61] = \<const0> ;
assign m_axi_wdata[60] = \<const0> ;
assign m_axi_wdata[59] = \<const0> ;
assign m_axi_wdata[58] = \<const0> ;
assign m_axi_wdata[57] = \<const0> ;
assign m_axi_wdata[56] = \<const0> ;
assign m_axi_wdata[55] = \<const0> ;
assign m_axi_wdata[54] = \<const0> ;
assign m_axi_wdata[53] = \<const0> ;
assign m_axi_wdata[52] = \<const0> ;
assign m_axi_wdata[51] = \<const0> ;
assign m_axi_wdata[50] = \<const0> ;
assign m_axi_wdata[49] = \<const0> ;
assign m_axi_wdata[48] = \<const0> ;
assign m_axi_wdata[47] = \<const0> ;
assign m_axi_wdata[46] = \<const0> ;
assign m_axi_wdata[45] = \<const0> ;
assign m_axi_wdata[44] = \<const0> ;
assign m_axi_wdata[43] = \<const0> ;
assign m_axi_wdata[42] = \<const0> ;
assign m_axi_wdata[41] = \<const0> ;
assign m_axi_wdata[40] = \<const0> ;
assign m_axi_wdata[39] = \<const0> ;
assign m_axi_wdata[38] = \<const0> ;
assign m_axi_wdata[37] = \<const0> ;
assign m_axi_wdata[36] = \<const0> ;
assign m_axi_wdata[35] = \<const0> ;
assign m_axi_wdata[34] = \<const0> ;
assign m_axi_wdata[33] = \<const0> ;
assign m_axi_wdata[32] = \<const0> ;
assign m_axi_wdata[31] = \<const0> ;
assign m_axi_wdata[30] = \<const0> ;
assign m_axi_wdata[29] = \<const0> ;
assign m_axi_wdata[28] = \<const0> ;
assign m_axi_wdata[27] = \<const0> ;
assign m_axi_wdata[26] = \<const0> ;
assign m_axi_wdata[25] = \<const0> ;
assign m_axi_wdata[24] = \<const0> ;
assign m_axi_wdata[23] = \<const0> ;
assign m_axi_wdata[22] = \<const0> ;
assign m_axi_wdata[21] = \<const0> ;
assign m_axi_wdata[20] = \<const0> ;
assign m_axi_wdata[19] = \<const0> ;
assign m_axi_wdata[18] = \<const0> ;
assign m_axi_wdata[17] = \<const0> ;
assign m_axi_wdata[16] = \<const0> ;
assign m_axi_wdata[15] = \<const0> ;
assign m_axi_wdata[14] = \<const0> ;
assign m_axi_wdata[13] = \<const0> ;
assign m_axi_wdata[12] = \<const0> ;
assign m_axi_wdata[11] = \<const0> ;
assign m_axi_wdata[10] = \<const0> ;
assign m_axi_wdata[9] = \<const0> ;
assign m_axi_wdata[8] = \<const0> ;
assign m_axi_wdata[7] = \<const0> ;
assign m_axi_wdata[6] = \<const0> ;
assign m_axi_wdata[5] = \<const0> ;
assign m_axi_wdata[4] = \<const0> ;
assign m_axi_wdata[3] = \<const0> ;
assign m_axi_wdata[2] = \<const0> ;
assign m_axi_wdata[1] = \<const0> ;
assign m_axi_wdata[0] = \<const0> ;
assign m_axi_wid[0] = \<const0> ;
assign m_axi_wlast = \<const0> ;
assign m_axi_wstrb[7] = \<const0> ;
assign m_axi_wstrb[6] = \<const0> ;
assign m_axi_wstrb[5] = \<const0> ;
assign m_axi_wstrb[4] = \<const0> ;
assign m_axi_wstrb[3] = \<const0> ;
assign m_axi_wstrb[2] = \<const0> ;
assign m_axi_wstrb[1] = \<const0> ;
assign m_axi_wstrb[0] = \<const0> ;
assign m_axi_wuser[0] = \<const0> ;
assign m_axi_wvalid = \<const0> ;
assign m_axis_tdata[7] = \<const0> ;
assign m_axis_tdata[6] = \<const0> ;
assign m_axis_tdata[5] = \<const0> ;
assign m_axis_tdata[4] = \<const0> ;
assign m_axis_tdata[3] = \<const0> ;
assign m_axis_tdata[2] = \<const0> ;
assign m_axis_tdata[1] = \<const0> ;
assign m_axis_tdata[0] = \<const0> ;
assign m_axis_tdest[0] = \<const0> ;
assign m_axis_tid[0] = \<const0> ;
assign m_axis_tkeep[0] = \<const0> ;
assign m_axis_tlast = \<const0> ;
assign m_axis_tstrb[0] = \<const0> ;
assign m_axis_tuser[3] = \<const0> ;
assign m_axis_tuser[2] = \<const0> ;
assign m_axis_tuser[1] = \<const0> ;
assign m_axis_tuser[0] = \<const0> ;
assign m_axis_tvalid = \<const0> ;
assign overflow = \<const0> ;
assign rd_rst_busy = \<const0> ;
assign s_axi_arready = \<const0> ;
assign s_axi_awready = \<const0> ;
assign s_axi_bid[0] = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_buser[0] = \<const0> ;
assign s_axi_bvalid = \<const0> ;
assign s_axi_rdata[63] = \<const0> ;
assign s_axi_rdata[62] = \<const0> ;
assign s_axi_rdata[61] = \<const0> ;
assign s_axi_rdata[60] = \<const0> ;
assign s_axi_rdata[59] = \<const0> ;
assign s_axi_rdata[58] = \<const0> ;
assign s_axi_rdata[57] = \<const0> ;
assign s_axi_rdata[56] = \<const0> ;
assign s_axi_rdata[55] = \<const0> ;
assign s_axi_rdata[54] = \<const0> ;
assign s_axi_rdata[53] = \<const0> ;
assign s_axi_rdata[52] = \<const0> ;
assign s_axi_rdata[51] = \<const0> ;
assign s_axi_rdata[50] = \<const0> ;
assign s_axi_rdata[49] = \<const0> ;
assign s_axi_rdata[48] = \<const0> ;
assign s_axi_rdata[47] = \<const0> ;
assign s_axi_rdata[46] = \<const0> ;
assign s_axi_rdata[45] = \<const0> ;
assign s_axi_rdata[44] = \<const0> ;
assign s_axi_rdata[43] = \<const0> ;
assign s_axi_rdata[42] = \<const0> ;
assign s_axi_rdata[41] = \<const0> ;
assign s_axi_rdata[40] = \<const0> ;
assign s_axi_rdata[39] = \<const0> ;
assign s_axi_rdata[38] = \<const0> ;
assign s_axi_rdata[37] = \<const0> ;
assign s_axi_rdata[36] = \<const0> ;
assign s_axi_rdata[35] = \<const0> ;
assign s_axi_rdata[34] = \<const0> ;
assign s_axi_rdata[33] = \<const0> ;
assign s_axi_rdata[32] = \<const0> ;
assign s_axi_rdata[31] = \<const0> ;
assign s_axi_rdata[30] = \<const0> ;
assign s_axi_rdata[29] = \<const0> ;
assign s_axi_rdata[28] = \<const0> ;
assign s_axi_rdata[27] = \<const0> ;
assign s_axi_rdata[26] = \<const0> ;
assign s_axi_rdata[25] = \<const0> ;
assign s_axi_rdata[24] = \<const0> ;
assign s_axi_rdata[23] = \<const0> ;
assign s_axi_rdata[22] = \<const0> ;
assign s_axi_rdata[21] = \<const0> ;
assign s_axi_rdata[20] = \<const0> ;
assign s_axi_rdata[19] = \<const0> ;
assign s_axi_rdata[18] = \<const0> ;
assign s_axi_rdata[17] = \<const0> ;
assign s_axi_rdata[16] = \<const0> ;
assign s_axi_rdata[15] = \<const0> ;
assign s_axi_rdata[14] = \<const0> ;
assign s_axi_rdata[13] = \<const0> ;
assign s_axi_rdata[12] = \<const0> ;
assign s_axi_rdata[11] = \<const0> ;
assign s_axi_rdata[10] = \<const0> ;
assign s_axi_rdata[9] = \<const0> ;
assign s_axi_rdata[8] = \<const0> ;
assign s_axi_rdata[7] = \<const0> ;
assign s_axi_rdata[6] = \<const0> ;
assign s_axi_rdata[5] = \<const0> ;
assign s_axi_rdata[4] = \<const0> ;
assign s_axi_rdata[3] = \<const0> ;
assign s_axi_rdata[2] = \<const0> ;
assign s_axi_rdata[1] = \<const0> ;
assign s_axi_rdata[0] = \<const0> ;
assign s_axi_rid[0] = \<const0> ;
assign s_axi_rlast = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
assign s_axi_ruser[0] = \<const0> ;
assign s_axi_rvalid = \<const0> ;
assign s_axi_wready = \<const0> ;
assign s_axis_tready = \<const0> ;
assign sbiterr = \<const0> ;
assign underflow = \<const0> ;
assign valid = \<const0> ;
assign wr_ack = \<const0> ;
GND GND
(.G(\<const0> ));
VCC VCC
(.P(\<const1> ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth inst_fifo_gen
(.din(din),
.dout(dout),
.empty(empty),
.full(full),
.prog_empty(prog_empty),
.prog_full(prog_full),
.rd_clk(rd_clk),
.rd_data_count(rd_data_count),
.rd_en(rd_en),
.rst(rst),
.wr_clk(wr_clk),
.wr_data_count(wr_data_count),
.wr_en(wr_en),
.wr_rst_busy(wr_rst_busy));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth
(wr_rst_busy,
dout,
empty,
full,
rd_data_count,
wr_data_count,
prog_empty,
prog_full,
rd_en,
wr_clk,
rd_clk,
din,
rst,
wr_en);
output wr_rst_busy;
output [63:0]dout;
output empty;
output full;
output [8:0]rd_data_count;
output [9:0]wr_data_count;
output prog_empty;
output prog_full;
input rd_en;
input wr_clk;
input rd_clk;
input [63:0]din;
input rst;
input wr_en;
wire [63:0]din;
wire [63:0]dout;
wire empty;
wire full;
wire prog_empty;
wire prog_full;
wire rd_clk;
wire [8:0]rd_data_count;
wire rd_en;
wire rst;
wire wr_clk;
wire [9:0]wr_data_count;
wire wr_en;
wire wr_rst_busy;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top \gconvfifo.rf
(.din(din),
.dout(dout),
.empty(empty),
.full(full),
.prog_empty(prog_empty),
.prog_full(prog_full),
.rd_clk(rd_clk),
.rd_data_count(rd_data_count),
.rd_en(rd_en),
.rst(rst),
.wr_clk(wr_clk),
.wr_data_count(wr_data_count),
.wr_en(wr_en),
.wr_rst_busy(wr_rst_busy));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory
(dout,
wr_clk,
rd_clk,
E,
tmp_ram_rd_en,
out,
\gic0.gc0.count_d2_reg[9] ,
\gc0.count_d1_reg[9] ,
din);
output [63:0]dout;
input wr_clk;
input rd_clk;
input [0:0]E;
input tmp_ram_rd_en;
input [0:0]out;
input [9:0]\gic0.gc0.count_d2_reg[9] ;
input [9:0]\gc0.count_d1_reg[9] ;
input [63:0]din;
wire [0:0]E;
wire [63:0]din;
wire [63:0]dout;
wire [9:0]\gc0.count_d1_reg[9] ;
wire [9:0]\gic0.gc0.count_d2_reg[9] ;
wire [0:0]out;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4 \gbm.gbmg.gbmga.ngecc.bmg
(.E(E),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[9] (\gc0.count_d1_reg[9] ),
.\gic0.gc0.count_d2_reg[9] (\gic0.gc0.count_d2_reg[9] ),
.out(out),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr
(Q,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ,
E,
rd_clk,
AR);
output [9:0]Q;
output [9:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
input [0:0]E;
input rd_clk;
input [0:0]AR;
wire [0:0]AR;
wire [9:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
wire [0:0]E;
wire [9:0]Q;
wire \gc0.count[9]_i_2_n_0 ;
wire [9:0]plusOp__0;
wire rd_clk;
LUT1 #(
.INIT(2'h1))
\gc0.count[0]_i_1
(.I0(Q[0]),
.O(plusOp__0[0]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT2 #(
.INIT(4'h6))
\gc0.count[1]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.O(plusOp__0[1]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'h78))
\gc0.count[2]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.I2(Q[2]),
.O(plusOp__0[2]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT4 #(
.INIT(16'h7F80))
\gc0.count[3]_i_1
(.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[3]),
.O(plusOp__0[3]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT5 #(
.INIT(32'h7FFF8000))
\gc0.count[4]_i_1
(.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[3]),
.I4(Q[4]),
.O(plusOp__0[4]));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\gc0.count[5]_i_1
(.I0(Q[3]),
.I1(Q[1]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[4]),
.I5(Q[5]),
.O(plusOp__0[5]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT2 #(
.INIT(4'h6))
\gc0.count[6]_i_1
(.I0(\gc0.count[9]_i_2_n_0 ),
.I1(Q[6]),
.O(plusOp__0[6]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'h78))
\gc0.count[7]_i_1
(.I0(\gc0.count[9]_i_2_n_0 ),
.I1(Q[6]),
.I2(Q[7]),
.O(plusOp__0[7]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT4 #(
.INIT(16'h7F80))
\gc0.count[8]_i_1
(.I0(Q[6]),
.I1(\gc0.count[9]_i_2_n_0 ),
.I2(Q[7]),
.I3(Q[8]),
.O(plusOp__0[8]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT5 #(
.INIT(32'h7FFF8000))
\gc0.count[9]_i_1
(.I0(Q[7]),
.I1(\gc0.count[9]_i_2_n_0 ),
.I2(Q[6]),
.I3(Q[8]),
.I4(Q[9]),
.O(plusOp__0[9]));
LUT6 #(
.INIT(64'h8000000000000000))
\gc0.count[9]_i_2
(.I0(Q[5]),
.I1(Q[3]),
.I2(Q[1]),
.I3(Q[0]),
.I4(Q[2]),
.I5(Q[4]),
.O(\gc0.count[9]_i_2_n_0 ));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[0]
(.C(rd_clk),
.CE(E),
.CLR(AR),
.D(Q[0]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [0]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[1]
(.C(rd_clk),
.CE(E),
.CLR(AR),
.D(Q[1]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [1]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[2]
(.C(rd_clk),
.CE(E),
.CLR(AR),
.D(Q[2]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [2]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[3]
(.C(rd_clk),
.CE(E),
.CLR(AR),
.D(Q[3]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [3]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[4]
(.C(rd_clk),
.CE(E),
.CLR(AR),
.D(Q[4]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [4]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[5]
(.C(rd_clk),
.CE(E),
.CLR(AR),
.D(Q[5]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [5]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[6]
(.C(rd_clk),
.CE(E),
.CLR(AR),
.D(Q[6]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [6]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[7]
(.C(rd_clk),
.CE(E),
.CLR(AR),
.D(Q[7]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [7]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[8]
(.C(rd_clk),
.CE(E),
.CLR(AR),
.D(Q[8]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [8]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[9]
(.C(rd_clk),
.CE(E),
.CLR(AR),
.D(Q[9]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [9]));
FDPE #(
.INIT(1'b1))
\gc0.count_reg[0]
(.C(rd_clk),
.CE(E),
.D(plusOp__0[0]),
.PRE(AR),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[1]
(.C(rd_clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[2]
(.C(rd_clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[3]
(.C(rd_clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[4]
(.C(rd_clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[5]
(.C(rd_clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[6]
(.C(rd_clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[7]
(.C(rd_clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[8]
(.C(rd_clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[9]
(.C(rd_clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[9]),
.Q(Q[9]));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_dc_as
(rd_data_count,
\gnxpm_cdc.wr_pntr_bin_reg[8] ,
rd_clk,
AR);
output [8:0]rd_data_count;
input [8:0]\gnxpm_cdc.wr_pntr_bin_reg[8] ;
input rd_clk;
input [0:0]AR;
wire [0:0]AR;
wire [8:0]\gnxpm_cdc.wr_pntr_bin_reg[8] ;
wire rd_clk;
wire [8:0]rd_data_count;
FDCE #(
.INIT(1'b0))
\rd_dc_i_reg[1]
(.C(rd_clk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.wr_pntr_bin_reg[8] [0]),
.Q(rd_data_count[0]));
FDCE #(
.INIT(1'b0))
\rd_dc_i_reg[2]
(.C(rd_clk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.wr_pntr_bin_reg[8] [1]),
.Q(rd_data_count[1]));
FDCE #(
.INIT(1'b0))
\rd_dc_i_reg[3]
(.C(rd_clk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.wr_pntr_bin_reg[8] [2]),
.Q(rd_data_count[2]));
FDCE #(
.INIT(1'b0))
\rd_dc_i_reg[4]
(.C(rd_clk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.wr_pntr_bin_reg[8] [3]),
.Q(rd_data_count[3]));
FDCE #(
.INIT(1'b0))
\rd_dc_i_reg[5]
(.C(rd_clk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.wr_pntr_bin_reg[8] [4]),
.Q(rd_data_count[4]));
FDCE #(
.INIT(1'b0))
\rd_dc_i_reg[6]
(.C(rd_clk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.wr_pntr_bin_reg[8] [5]),
.Q(rd_data_count[5]));
FDCE #(
.INIT(1'b0))
\rd_dc_i_reg[7]
(.C(rd_clk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.wr_pntr_bin_reg[8] [6]),
.Q(rd_data_count[6]));
FDCE #(
.INIT(1'b0))
\rd_dc_i_reg[8]
(.C(rd_clk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.wr_pntr_bin_reg[8] [7]),
.Q(rd_data_count[7]));
FDCE #(
.INIT(1'b0))
\rd_dc_i_reg[9]
(.C(rd_clk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.wr_pntr_bin_reg[8] [8]),
.Q(rd_data_count[8]));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic
(empty,
out,
prog_empty,
Q,
p_0_out,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ,
rd_data_count,
v1_reg,
v1_reg_0,
rd_clk,
AR,
rd_en,
D,
\gnxpm_cdc.wr_pntr_bin_reg[8] );
output empty;
output out;
output prog_empty;
output [9:0]Q;
output p_0_out;
output [9:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
output [8:0]rd_data_count;
input [4:0]v1_reg;
input [4:0]v1_reg_0;
input rd_clk;
input [0:0]AR;
input rd_en;
input [8:0]D;
input [8:0]\gnxpm_cdc.wr_pntr_bin_reg[8] ;
wire [0:0]AR;
wire [8:0]D;
wire [9:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
wire [9:0]Q;
wire empty;
wire [8:0]\gnxpm_cdc.wr_pntr_bin_reg[8] ;
wire \gras.rsts_n_2 ;
wire out;
wire p_0_out;
wire prog_empty;
wire rd_clk;
wire [8:0]rd_data_count;
wire rd_en;
wire [4:0]v1_reg;
wire [4:0]v1_reg_0;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_pe_as \gras.gpe.rdpe
(.AR(AR),
.D(D),
.out(out),
.prog_empty(prog_empty),
.rd_clk(rd_clk));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_dc_as \gras.grdc1.rdc
(.AR(AR),
.\gnxpm_cdc.wr_pntr_bin_reg[8] (\gnxpm_cdc.wr_pntr_bin_reg[8] ),
.rd_clk(rd_clk),
.rd_data_count(rd_data_count));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_as \gras.rsts
(.AR(AR),
.E(\gras.rsts_n_2 ),
.empty(empty),
.out(out),
.p_0_out(p_0_out),
.rd_clk(rd_clk),
.rd_en(rd_en),
.v1_reg(v1_reg),
.v1_reg_0(v1_reg_0));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr rpntr
(.AR(AR),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ),
.E(\gras.rsts_n_2 ),
.Q(Q),
.rd_clk(rd_clk));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_pe_as
(prog_empty,
rd_clk,
AR,
out,
D);
output prog_empty;
input rd_clk;
input [0:0]AR;
input out;
input [8:0]D;
wire [0:0]AR;
wire [8:0]D;
wire \gdiff.diff_pntr_pad_reg_n_0_[10] ;
wire \gdiff.diff_pntr_pad_reg_n_0_[2] ;
wire \gdiff.diff_pntr_pad_reg_n_0_[3] ;
wire \gdiff.diff_pntr_pad_reg_n_0_[4] ;
wire \gdiff.diff_pntr_pad_reg_n_0_[5] ;
wire \gdiff.diff_pntr_pad_reg_n_0_[6] ;
wire \gdiff.diff_pntr_pad_reg_n_0_[7] ;
wire \gdiff.diff_pntr_pad_reg_n_0_[8] ;
wire \gdiff.diff_pntr_pad_reg_n_0_[9] ;
wire \gpe1.prog_empty_i_i_1_n_0 ;
wire \gpe1.prog_empty_i_i_2_n_0 ;
wire \gpe1.prog_empty_i_i_3_n_0 ;
wire out;
wire prog_empty;
wire rd_clk;
FDCE #(
.INIT(1'b0))
\gdiff.diff_pntr_pad_reg[10]
(.C(rd_clk),
.CE(1'b1),
.CLR(AR),
.D(D[8]),
.Q(\gdiff.diff_pntr_pad_reg_n_0_[10] ));
FDCE #(
.INIT(1'b0))
\gdiff.diff_pntr_pad_reg[2]
(.C(rd_clk),
.CE(1'b1),
.CLR(AR),
.D(D[0]),
.Q(\gdiff.diff_pntr_pad_reg_n_0_[2] ));
FDCE #(
.INIT(1'b0))
\gdiff.diff_pntr_pad_reg[3]
(.C(rd_clk),
.CE(1'b1),
.CLR(AR),
.D(D[1]),
.Q(\gdiff.diff_pntr_pad_reg_n_0_[3] ));
FDCE #(
.INIT(1'b0))
\gdiff.diff_pntr_pad_reg[4]
(.C(rd_clk),
.CE(1'b1),
.CLR(AR),
.D(D[2]),
.Q(\gdiff.diff_pntr_pad_reg_n_0_[4] ));
FDCE #(
.INIT(1'b0))
\gdiff.diff_pntr_pad_reg[5]
(.C(rd_clk),
.CE(1'b1),
.CLR(AR),
.D(D[3]),
.Q(\gdiff.diff_pntr_pad_reg_n_0_[5] ));
FDCE #(
.INIT(1'b0))
\gdiff.diff_pntr_pad_reg[6]
(.C(rd_clk),
.CE(1'b1),
.CLR(AR),
.D(D[4]),
.Q(\gdiff.diff_pntr_pad_reg_n_0_[6] ));
FDCE #(
.INIT(1'b0))
\gdiff.diff_pntr_pad_reg[7]
(.C(rd_clk),
.CE(1'b1),
.CLR(AR),
.D(D[5]),
.Q(\gdiff.diff_pntr_pad_reg_n_0_[7] ));
FDCE #(
.INIT(1'b0))
\gdiff.diff_pntr_pad_reg[8]
(.C(rd_clk),
.CE(1'b1),
.CLR(AR),
.D(D[6]),
.Q(\gdiff.diff_pntr_pad_reg_n_0_[8] ));
FDCE #(
.INIT(1'b0))
\gdiff.diff_pntr_pad_reg[9]
(.C(rd_clk),
.CE(1'b1),
.CLR(AR),
.D(D[7]),
.Q(\gdiff.diff_pntr_pad_reg_n_0_[9] ));
LUT4 #(
.INIT(16'h88B8))
\gpe1.prog_empty_i_i_1
(.I0(prog_empty),
.I1(out),
.I2(\gpe1.prog_empty_i_i_2_n_0 ),
.I3(\gpe1.prog_empty_i_i_3_n_0 ),
.O(\gpe1.prog_empty_i_i_1_n_0 ));
LUT6 #(
.INIT(64'h7F7F7FFFFFFFFFFF))
\gpe1.prog_empty_i_i_2
(.I0(\gdiff.diff_pntr_pad_reg_n_0_[9] ),
.I1(\gdiff.diff_pntr_pad_reg_n_0_[4] ),
.I2(\gdiff.diff_pntr_pad_reg_n_0_[6] ),
.I3(\gdiff.diff_pntr_pad_reg_n_0_[3] ),
.I4(\gdiff.diff_pntr_pad_reg_n_0_[2] ),
.I5(\gdiff.diff_pntr_pad_reg_n_0_[5] ),
.O(\gpe1.prog_empty_i_i_2_n_0 ));
LUT4 #(
.INIT(16'hFAEA))
\gpe1.prog_empty_i_i_3
(.I0(\gdiff.diff_pntr_pad_reg_n_0_[10] ),
.I1(\gdiff.diff_pntr_pad_reg_n_0_[7] ),
.I2(\gdiff.diff_pntr_pad_reg_n_0_[9] ),
.I3(\gdiff.diff_pntr_pad_reg_n_0_[8] ),
.O(\gpe1.prog_empty_i_i_3_n_0 ));
FDPE #(
.INIT(1'b1))
\gpe1.prog_empty_i_reg
(.C(rd_clk),
.CE(1'b1),
.D(\gpe1.prog_empty_i_i_1_n_0 ),
.PRE(AR),
.Q(prog_empty));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_as
(empty,
out,
E,
p_0_out,
v1_reg,
v1_reg_0,
rd_clk,
AR,
rd_en);
output empty;
output out;
output [0:0]E;
output p_0_out;
input [4:0]v1_reg;
input [4:0]v1_reg_0;
input rd_clk;
input [0:0]AR;
input rd_en;
wire [0:0]AR;
wire [0:0]E;
wire c0_n_0;
wire comp1;
wire p_0_out;
(* DONT_TOUCH *) wire ram_empty_fb_i;
(* DONT_TOUCH *) wire ram_empty_i;
wire rd_clk;
wire rd_en;
wire [4:0]v1_reg;
wire [4:0]v1_reg_0;
assign empty = ram_empty_i;
assign out = ram_empty_fb_i;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_4 c0
(.comp1(comp1),
.out(ram_empty_fb_i),
.ram_empty_fb_i_reg(c0_n_0),
.rd_en(rd_en),
.v1_reg(v1_reg));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_5 c1
(.comp1(comp1),
.v1_reg_0(v1_reg_0));
LUT2 #(
.INIT(4'h2))
\gc0.count_d1[9]_i_1
(.I0(rd_en),
.I1(ram_empty_fb_i),
.O(E));
LUT2 #(
.INIT(4'hB))
\gdiff.diff_pntr_pad[4]_i_2
(.I0(ram_empty_fb_i),
.I1(rd_en),
.O(p_0_out));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_empty_fb_i_reg
(.C(rd_clk),
.CE(1'b1),
.D(c0_n_0),
.PRE(AR),
.Q(ram_empty_fb_i));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_empty_i_reg
(.C(rd_clk),
.CE(1'b1),
.D(c0_n_0),
.PRE(AR),
.Q(ram_empty_i));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_blk_ramfifo
(out,
\gc0.count_reg[1] ,
\grstd1.grst_full.grst_f.rst_d3_reg_0 ,
wr_rst_busy,
tmp_ram_rd_en,
rd_clk,
wr_clk,
rst,
ram_empty_fb_i_reg,
rd_en);
output [1:0]out;
output [2:0]\gc0.count_reg[1] ;
output \grstd1.grst_full.grst_f.rst_d3_reg_0 ;
output wr_rst_busy;
output tmp_ram_rd_en;
input rd_clk;
input wr_clk;
input rst;
input ram_empty_fb_i_reg;
input rd_en;
wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1 ;
wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1 ;
wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ;
wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ;
wire p_7_out;
wire p_8_out;
wire ram_empty_fb_i_reg;
wire rd_clk;
wire rd_en;
wire rd_rst_asreg;
(* DONT_TOUCH *) wire [2:0]rd_rst_reg;
wire rst;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d2;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d3;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_rd_reg1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_rd_reg2;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_wr_reg1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_wr_reg2;
wire tmp_ram_rd_en;
wire wr_clk;
wire wr_rst_asreg;
(* DONT_TOUCH *) wire [2:0]wr_rst_reg;
assign \gc0.count_reg[1] [2:0] = rd_rst_reg;
assign \grstd1.grst_full.grst_f.rst_d3_reg_0 = rst_d2;
assign out[1:0] = wr_rst_reg[1:0];
assign wr_rst_busy = rst_d3;
LUT3 #(
.INIT(8'hBA))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2
(.I0(rd_rst_reg[0]),
.I1(ram_empty_fb_i_reg),
.I2(rd_en),
.O(tmp_ram_rd_en));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d1_reg
(.C(wr_clk),
.CE(1'b1),
.D(1'b0),
.PRE(rst_wr_reg2),
.Q(rst_d1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d2_reg
(.C(wr_clk),
.CE(1'b1),
.D(rst_d1),
.PRE(rst_wr_reg2),
.Q(rst_d2));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d3_reg
(.C(wr_clk),
.CE(1'b1),
.D(rst_d2),
.PRE(rst_wr_reg2),
.Q(rst_d3));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst
(.in0(rd_rst_asreg),
.\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg (\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1 ),
.out(p_7_out),
.rd_clk(rd_clk));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst
(.in0(wr_rst_asreg),
.\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg (\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1 ),
.out(p_8_out),
.wr_clk(wr_clk));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst
(.AS(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ),
.in0(rd_rst_asreg),
.out(p_7_out),
.rd_clk(rd_clk));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst
(.AS(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ),
.in0(wr_rst_asreg),
.out(p_8_out),
.wr_clk(wr_clk));
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg
(.C(rd_clk),
.CE(1'b1),
.D(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1 ),
.PRE(rst_rd_reg2),
.Q(rd_rst_asreg));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]
(.C(rd_clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ),
.Q(rd_rst_reg[0]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]
(.C(rd_clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ),
.Q(rd_rst_reg[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]
(.C(rd_clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ),
.Q(rd_rst_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg
(.C(rd_clk),
.CE(1'b1),
.D(1'b0),
.PRE(rst),
.Q(rst_rd_reg1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg
(.C(rd_clk),
.CE(1'b1),
.D(rst_rd_reg1),
.PRE(rst),
.Q(rst_rd_reg2));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg
(.C(wr_clk),
.CE(1'b1),
.D(1'b0),
.PRE(rst),
.Q(rst_wr_reg1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg
(.C(wr_clk),
.CE(1'b1),
.D(rst_wr_reg1),
.PRE(rst),
.Q(rst_wr_reg2));
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg
(.C(wr_clk),
.CE(1'b1),
.D(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1 ),
.PRE(rst_wr_reg2),
.Q(wr_rst_asreg));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]
(.C(wr_clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ),
.Q(wr_rst_reg[0]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]
(.C(wr_clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ),
.Q(wr_rst_reg[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]
(.C(wr_clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ),
.Q(wr_rst_reg[2]));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff
(out,
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg ,
in0,
rd_clk);
output out;
output \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg ;
input [0:0]in0;
input rd_clk;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire [0:0]in0;
wire \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg ;
wire rd_clk;
assign out = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(rd_clk),
.CE(1'b1),
.D(in0),
.Q(Q_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1
(.I0(in0),
.I1(Q_reg),
.O(\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg ));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0
(out,
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg ,
in0,
wr_clk);
output out;
output \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg ;
input [0:0]in0;
input wr_clk;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire [0:0]in0;
wire \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg ;
wire wr_clk;
assign out = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(wr_clk),
.CE(1'b1),
.D(in0),
.Q(Q_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1
(.I0(in0),
.I1(Q_reg),
.O(\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg ));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1
(AS,
out,
rd_clk,
in0);
output [0:0]AS;
input out;
input rd_clk;
input [0:0]in0;
wire [0:0]AS;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire [0:0]in0;
wire out;
wire rd_clk;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(rd_clk),
.CE(1'b1),
.D(out),
.Q(Q_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1
(.I0(in0),
.I1(Q_reg),
.O(AS));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2
(AS,
out,
wr_clk,
in0);
output [0:0]AS;
input out;
input wr_clk;
input [0:0]in0;
wire [0:0]AS;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire [0:0]in0;
wire out;
wire wr_clk;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(wr_clk),
.CE(1'b1),
.D(out),
.Q(Q_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1
(.I0(in0),
.I1(Q_reg),
.O(AS));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized0
(D,
Q,
rd_clk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );
output [9:0]D;
input [9:0]Q;
input rd_clk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [9:0]Q;
(* async_reg = "true" *) (* msgon = "true" *) wire [9:0]Q_reg;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire rd_clk;
assign D[9:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[3]),
.Q(Q_reg[3]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[4]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[4]),
.Q(Q_reg[4]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[5]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[5]),
.Q(Q_reg[5]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[6]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[6]),
.Q(Q_reg[6]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[7]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[7]),
.Q(Q_reg[7]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[8]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[8]),
.Q(Q_reg[8]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[9]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[9]),
.Q(Q_reg[9]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized1
(D,
Q,
wr_clk,
AR);
output [9:0]D;
input [9:0]Q;
input wr_clk;
input [0:0]AR;
wire [0:0]AR;
wire [9:0]Q;
(* async_reg = "true" *) (* msgon = "true" *) wire [9:0]Q_reg;
wire wr_clk;
assign D[9:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(Q[0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(Q[1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(Q[2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(Q[3]),
.Q(Q_reg[3]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[4]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(Q[4]),
.Q(Q_reg[4]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[5]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(Q[5]),
.Q(Q_reg[5]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[6]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(Q[6]),
.Q(Q_reg[6]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[7]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(Q[7]),
.Q(Q_reg[7]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[8]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(Q[8]),
.Q(Q_reg[8]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[9]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(Q[9]),
.Q(Q_reg[9]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized2
(out,
\gnxpm_cdc.wr_pntr_bin_reg[8] ,
D,
rd_clk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );
output [0:0]out;
output [8:0]\gnxpm_cdc.wr_pntr_bin_reg[8] ;
input [9:0]D;
input rd_clk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [9:0]D;
(* async_reg = "true" *) (* msgon = "true" *) wire [9:0]Q_reg;
wire \gnxpm_cdc.wr_pntr_bin[0]_i_2_n_0 ;
wire \gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0 ;
wire \gnxpm_cdc.wr_pntr_bin[3]_i_2_n_0 ;
wire [8:0]\gnxpm_cdc.wr_pntr_bin_reg[8] ;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire rd_clk;
assign out[0] = Q_reg[9];
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[3]),
.Q(Q_reg[3]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[4]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[4]),
.Q(Q_reg[4]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[5]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[5]),
.Q(Q_reg[5]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[6]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[6]),
.Q(Q_reg[6]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[7]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[7]),
.Q(Q_reg[7]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[8]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[8]),
.Q(Q_reg[8]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[9]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[9]),
.Q(Q_reg[9]));
LUT5 #(
.INIT(32'h96696996))
\gnxpm_cdc.wr_pntr_bin[0]_i_1
(.I0(Q_reg[1]),
.I1(Q_reg[0]),
.I2(Q_reg[2]),
.I3(\gnxpm_cdc.wr_pntr_bin[0]_i_2_n_0 ),
.I4(\gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0 ),
.O(\gnxpm_cdc.wr_pntr_bin_reg[8] [0]));
LUT3 #(
.INIT(8'h96))
\gnxpm_cdc.wr_pntr_bin[0]_i_2
(.I0(Q_reg[4]),
.I1(Q_reg[3]),
.I2(Q_reg[9]),
.O(\gnxpm_cdc.wr_pntr_bin[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\gnxpm_cdc.wr_pntr_bin[1]_i_1
(.I0(Q_reg[2]),
.I1(Q_reg[9]),
.I2(Q_reg[3]),
.I3(Q_reg[4]),
.I4(\gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0 ),
.I5(Q_reg[1]),
.O(\gnxpm_cdc.wr_pntr_bin_reg[8] [1]));
LUT5 #(
.INIT(32'h96696996))
\gnxpm_cdc.wr_pntr_bin[2]_i_1
(.I0(\gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0 ),
.I1(Q_reg[4]),
.I2(Q_reg[3]),
.I3(Q_reg[9]),
.I4(Q_reg[2]),
.O(\gnxpm_cdc.wr_pntr_bin_reg[8] [2]));
LUT4 #(
.INIT(16'h6996))
\gnxpm_cdc.wr_pntr_bin[2]_i_2
(.I0(Q_reg[8]),
.I1(Q_reg[7]),
.I2(Q_reg[6]),
.I3(Q_reg[5]),
.O(\gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\gnxpm_cdc.wr_pntr_bin[3]_i_1
(.I0(Q_reg[9]),
.I1(Q_reg[3]),
.I2(Q_reg[4]),
.I3(\gnxpm_cdc.wr_pntr_bin[3]_i_2_n_0 ),
.I4(Q_reg[7]),
.I5(Q_reg[8]),
.O(\gnxpm_cdc.wr_pntr_bin_reg[8] [3]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_bin[3]_i_2
(.I0(Q_reg[5]),
.I1(Q_reg[6]),
.O(\gnxpm_cdc.wr_pntr_bin[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\gnxpm_cdc.wr_pntr_bin[4]_i_1
(.I0(Q_reg[6]),
.I1(Q_reg[4]),
.I2(Q_reg[5]),
.I3(Q_reg[9]),
.I4(Q_reg[7]),
.I5(Q_reg[8]),
.O(\gnxpm_cdc.wr_pntr_bin_reg[8] [4]));
LUT5 #(
.INIT(32'h96696996))
\gnxpm_cdc.wr_pntr_bin[5]_i_1
(.I0(Q_reg[7]),
.I1(Q_reg[5]),
.I2(Q_reg[6]),
.I3(Q_reg[9]),
.I4(Q_reg[8]),
.O(\gnxpm_cdc.wr_pntr_bin_reg[8] [5]));
LUT4 #(
.INIT(16'h6996))
\gnxpm_cdc.wr_pntr_bin[6]_i_1
(.I0(Q_reg[7]),
.I1(Q_reg[6]),
.I2(Q_reg[9]),
.I3(Q_reg[8]),
.O(\gnxpm_cdc.wr_pntr_bin_reg[8] [6]));
LUT3 #(
.INIT(8'h96))
\gnxpm_cdc.wr_pntr_bin[7]_i_1
(.I0(Q_reg[8]),
.I1(Q_reg[7]),
.I2(Q_reg[9]),
.O(\gnxpm_cdc.wr_pntr_bin_reg[8] [7]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_bin[8]_i_1
(.I0(Q_reg[8]),
.I1(Q_reg[9]),
.O(\gnxpm_cdc.wr_pntr_bin_reg[8] [8]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized3
(out,
\gnxpm_cdc.rd_pntr_bin_reg[8] ,
D,
wr_clk,
AR);
output [0:0]out;
output [8:0]\gnxpm_cdc.rd_pntr_bin_reg[8] ;
input [9:0]D;
input wr_clk;
input [0:0]AR;
wire [0:0]AR;
wire [9:0]D;
(* async_reg = "true" *) (* msgon = "true" *) wire [9:0]Q_reg;
wire \gnxpm_cdc.rd_pntr_bin[0]_i_2_n_0 ;
wire \gnxpm_cdc.rd_pntr_bin[2]_i_2_n_0 ;
wire \gnxpm_cdc.rd_pntr_bin[3]_i_2_n_0 ;
wire [8:0]\gnxpm_cdc.rd_pntr_bin_reg[8] ;
wire wr_clk;
assign out[0] = Q_reg[9];
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(D[0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(D[1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(D[2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(D[3]),
.Q(Q_reg[3]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[4]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(D[4]),
.Q(Q_reg[4]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[5]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(D[5]),
.Q(Q_reg[5]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[6]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(D[6]),
.Q(Q_reg[6]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[7]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(D[7]),
.Q(Q_reg[7]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[8]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(D[8]),
.Q(Q_reg[8]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[9]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(D[9]),
.Q(Q_reg[9]));
LUT5 #(
.INIT(32'h96696996))
\gnxpm_cdc.rd_pntr_bin[0]_i_1
(.I0(Q_reg[1]),
.I1(Q_reg[0]),
.I2(Q_reg[2]),
.I3(\gnxpm_cdc.rd_pntr_bin[0]_i_2_n_0 ),
.I4(\gnxpm_cdc.rd_pntr_bin[2]_i_2_n_0 ),
.O(\gnxpm_cdc.rd_pntr_bin_reg[8] [0]));
LUT3 #(
.INIT(8'h96))
\gnxpm_cdc.rd_pntr_bin[0]_i_2
(.I0(Q_reg[4]),
.I1(Q_reg[3]),
.I2(Q_reg[9]),
.O(\gnxpm_cdc.rd_pntr_bin[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\gnxpm_cdc.rd_pntr_bin[1]_i_1
(.I0(Q_reg[2]),
.I1(Q_reg[9]),
.I2(Q_reg[3]),
.I3(Q_reg[4]),
.I4(\gnxpm_cdc.rd_pntr_bin[2]_i_2_n_0 ),
.I5(Q_reg[1]),
.O(\gnxpm_cdc.rd_pntr_bin_reg[8] [1]));
LUT5 #(
.INIT(32'h96696996))
\gnxpm_cdc.rd_pntr_bin[2]_i_1
(.I0(\gnxpm_cdc.rd_pntr_bin[2]_i_2_n_0 ),
.I1(Q_reg[4]),
.I2(Q_reg[3]),
.I3(Q_reg[9]),
.I4(Q_reg[2]),
.O(\gnxpm_cdc.rd_pntr_bin_reg[8] [2]));
LUT4 #(
.INIT(16'h6996))
\gnxpm_cdc.rd_pntr_bin[2]_i_2
(.I0(Q_reg[8]),
.I1(Q_reg[7]),
.I2(Q_reg[6]),
.I3(Q_reg[5]),
.O(\gnxpm_cdc.rd_pntr_bin[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\gnxpm_cdc.rd_pntr_bin[3]_i_1
(.I0(Q_reg[9]),
.I1(Q_reg[3]),
.I2(Q_reg[4]),
.I3(\gnxpm_cdc.rd_pntr_bin[3]_i_2_n_0 ),
.I4(Q_reg[7]),
.I5(Q_reg[8]),
.O(\gnxpm_cdc.rd_pntr_bin_reg[8] [3]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_bin[3]_i_2
(.I0(Q_reg[5]),
.I1(Q_reg[6]),
.O(\gnxpm_cdc.rd_pntr_bin[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\gnxpm_cdc.rd_pntr_bin[4]_i_1
(.I0(Q_reg[6]),
.I1(Q_reg[4]),
.I2(Q_reg[5]),
.I3(Q_reg[9]),
.I4(Q_reg[7]),
.I5(Q_reg[8]),
.O(\gnxpm_cdc.rd_pntr_bin_reg[8] [4]));
LUT5 #(
.INIT(32'h96696996))
\gnxpm_cdc.rd_pntr_bin[5]_i_1
(.I0(Q_reg[7]),
.I1(Q_reg[5]),
.I2(Q_reg[6]),
.I3(Q_reg[9]),
.I4(Q_reg[8]),
.O(\gnxpm_cdc.rd_pntr_bin_reg[8] [5]));
LUT4 #(
.INIT(16'h6996))
\gnxpm_cdc.rd_pntr_bin[6]_i_1
(.I0(Q_reg[7]),
.I1(Q_reg[6]),
.I2(Q_reg[9]),
.I3(Q_reg[8]),
.O(\gnxpm_cdc.rd_pntr_bin_reg[8] [6]));
LUT3 #(
.INIT(8'h96))
\gnxpm_cdc.rd_pntr_bin[7]_i_1
(.I0(Q_reg[8]),
.I1(Q_reg[7]),
.I2(Q_reg[9]),
.O(\gnxpm_cdc.rd_pntr_bin_reg[8] [7]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_bin[8]_i_1
(.I0(Q_reg[8]),
.I1(Q_reg[9]),
.O(\gnxpm_cdc.rd_pntr_bin_reg[8] [8]));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr
(\wr_data_count_i_reg[9] ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ,
\gdiff.diff_pntr_pad_reg[10] ,
Q,
\wr_data_count_i_reg[7] ,
\gdiff.diff_pntr_pad_reg[8] ,
S,
\gdiff.diff_pntr_pad_reg[4] ,
\gic0.gc0.count_d1_reg[9]_0 ,
v1_reg,
RD_PNTR_WR,
E,
wr_clk,
AR);
output [1:0]\wr_data_count_i_reg[9] ;
output [9:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
output [1:0]\gdiff.diff_pntr_pad_reg[10] ;
output [8:0]Q;
output [3:0]\wr_data_count_i_reg[7] ;
output [3:0]\gdiff.diff_pntr_pad_reg[8] ;
output [3:0]S;
output [3:0]\gdiff.diff_pntr_pad_reg[4] ;
output [9:0]\gic0.gc0.count_d1_reg[9]_0 ;
output [0:0]v1_reg;
input [9:0]RD_PNTR_WR;
input [0:0]E;
input wr_clk;
input [0:0]AR;
wire [0:0]AR;
wire [9:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
wire [0:0]E;
wire [8:0]Q;
wire [9:0]RD_PNTR_WR;
wire [3:0]S;
wire [1:0]\gdiff.diff_pntr_pad_reg[10] ;
wire [3:0]\gdiff.diff_pntr_pad_reg[4] ;
wire [3:0]\gdiff.diff_pntr_pad_reg[8] ;
wire \gic0.gc0.count[9]_i_2_n_0 ;
wire [9:0]\gic0.gc0.count_d1_reg[9]_0 ;
wire [9:9]p_13_out;
wire [9:0]plusOp__1;
wire [0:0]v1_reg;
wire wr_clk;
wire [3:0]\wr_data_count_i_reg[7] ;
wire [1:0]\wr_data_count_i_reg[9] ;
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT1 #(
.INIT(2'h1))
\gic0.gc0.count[0]_i_1
(.I0(\gic0.gc0.count_d1_reg[9]_0 [0]),
.O(plusOp__1[0]));
LUT2 #(
.INIT(4'h6))
\gic0.gc0.count[1]_i_1
(.I0(\gic0.gc0.count_d1_reg[9]_0 [0]),
.I1(\gic0.gc0.count_d1_reg[9]_0 [1]),
.O(plusOp__1[1]));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT3 #(
.INIT(8'h78))
\gic0.gc0.count[2]_i_1
(.I0(\gic0.gc0.count_d1_reg[9]_0 [0]),
.I1(\gic0.gc0.count_d1_reg[9]_0 [1]),
.I2(\gic0.gc0.count_d1_reg[9]_0 [2]),
.O(plusOp__1[2]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT4 #(
.INIT(16'h7F80))
\gic0.gc0.count[3]_i_1
(.I0(\gic0.gc0.count_d1_reg[9]_0 [1]),
.I1(\gic0.gc0.count_d1_reg[9]_0 [0]),
.I2(\gic0.gc0.count_d1_reg[9]_0 [2]),
.I3(\gic0.gc0.count_d1_reg[9]_0 [3]),
.O(plusOp__1[3]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT5 #(
.INIT(32'h7FFF8000))
\gic0.gc0.count[4]_i_1
(.I0(\gic0.gc0.count_d1_reg[9]_0 [2]),
.I1(\gic0.gc0.count_d1_reg[9]_0 [0]),
.I2(\gic0.gc0.count_d1_reg[9]_0 [1]),
.I3(\gic0.gc0.count_d1_reg[9]_0 [3]),
.I4(\gic0.gc0.count_d1_reg[9]_0 [4]),
.O(plusOp__1[4]));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\gic0.gc0.count[5]_i_1
(.I0(\gic0.gc0.count_d1_reg[9]_0 [3]),
.I1(\gic0.gc0.count_d1_reg[9]_0 [1]),
.I2(\gic0.gc0.count_d1_reg[9]_0 [0]),
.I3(\gic0.gc0.count_d1_reg[9]_0 [2]),
.I4(\gic0.gc0.count_d1_reg[9]_0 [4]),
.I5(\gic0.gc0.count_d1_reg[9]_0 [5]),
.O(plusOp__1[5]));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT2 #(
.INIT(4'h9))
\gic0.gc0.count[6]_i_1
(.I0(\gic0.gc0.count[9]_i_2_n_0 ),
.I1(\gic0.gc0.count_d1_reg[9]_0 [6]),
.O(plusOp__1[6]));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'hB4))
\gic0.gc0.count[7]_i_1
(.I0(\gic0.gc0.count[9]_i_2_n_0 ),
.I1(\gic0.gc0.count_d1_reg[9]_0 [6]),
.I2(\gic0.gc0.count_d1_reg[9]_0 [7]),
.O(plusOp__1[7]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT4 #(
.INIT(16'hDF20))
\gic0.gc0.count[8]_i_1
(.I0(\gic0.gc0.count_d1_reg[9]_0 [6]),
.I1(\gic0.gc0.count[9]_i_2_n_0 ),
.I2(\gic0.gc0.count_d1_reg[9]_0 [7]),
.I3(\gic0.gc0.count_d1_reg[9]_0 [8]),
.O(plusOp__1[8]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT5 #(
.INIT(32'hF7FF0800))
\gic0.gc0.count[9]_i_1
(.I0(\gic0.gc0.count_d1_reg[9]_0 [8]),
.I1(\gic0.gc0.count_d1_reg[9]_0 [7]),
.I2(\gic0.gc0.count[9]_i_2_n_0 ),
.I3(\gic0.gc0.count_d1_reg[9]_0 [6]),
.I4(\gic0.gc0.count_d1_reg[9]_0 [9]),
.O(plusOp__1[9]));
LUT6 #(
.INIT(64'h7FFFFFFFFFFFFFFF))
\gic0.gc0.count[9]_i_2
(.I0(\gic0.gc0.count_d1_reg[9]_0 [5]),
.I1(\gic0.gc0.count_d1_reg[9]_0 [3]),
.I2(\gic0.gc0.count_d1_reg[9]_0 [1]),
.I3(\gic0.gc0.count_d1_reg[9]_0 [0]),
.I4(\gic0.gc0.count_d1_reg[9]_0 [2]),
.I5(\gic0.gc0.count_d1_reg[9]_0 [4]),
.O(\gic0.gc0.count[9]_i_2_n_0 ));
FDPE #(
.INIT(1'b1))
\gic0.gc0.count_d1_reg[0]
(.C(wr_clk),
.CE(E),
.D(\gic0.gc0.count_d1_reg[9]_0 [0]),
.PRE(AR),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[1]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d1_reg[9]_0 [1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[2]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d1_reg[9]_0 [2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[3]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d1_reg[9]_0 [3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[4]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d1_reg[9]_0 [4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[5]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d1_reg[9]_0 [5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[6]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d1_reg[9]_0 [6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[7]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d1_reg[9]_0 [7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[8]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d1_reg[9]_0 [8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[9]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d1_reg[9]_0 [9]),
.Q(p_13_out));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[0]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(Q[0]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [0]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[1]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(Q[1]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[2]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(Q[2]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[3]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(Q[3]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [3]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[4]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(Q[4]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [4]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[5]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(Q[5]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [5]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[6]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(Q[6]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [6]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[7]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(Q[7]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [7]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[8]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(Q[8]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [8]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[9]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(p_13_out),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [9]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[0]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(plusOp__1[0]),
.Q(\gic0.gc0.count_d1_reg[9]_0 [0]));
FDPE #(
.INIT(1'b1))
\gic0.gc0.count_reg[1]
(.C(wr_clk),
.CE(E),
.D(plusOp__1[1]),
.PRE(AR),
.Q(\gic0.gc0.count_d1_reg[9]_0 [1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[2]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(plusOp__1[2]),
.Q(\gic0.gc0.count_d1_reg[9]_0 [2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[3]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(plusOp__1[3]),
.Q(\gic0.gc0.count_d1_reg[9]_0 [3]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[4]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(plusOp__1[4]),
.Q(\gic0.gc0.count_d1_reg[9]_0 [4]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[5]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(plusOp__1[5]),
.Q(\gic0.gc0.count_d1_reg[9]_0 [5]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[6]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(plusOp__1[6]),
.Q(\gic0.gc0.count_d1_reg[9]_0 [6]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[7]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(plusOp__1[7]),
.Q(\gic0.gc0.count_d1_reg[9]_0 [7]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[8]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(plusOp__1[8]),
.Q(\gic0.gc0.count_d1_reg[9]_0 [8]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[9]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(plusOp__1[9]),
.Q(\gic0.gc0.count_d1_reg[9]_0 [9]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[4].gms.ms_i_1__1
(.I0(p_13_out),
.I1(RD_PNTR_WR[9]),
.I2(RD_PNTR_WR[8]),
.I3(Q[8]),
.O(v1_reg));
LUT2 #(
.INIT(4'h9))
minusOp_carry__0_i_1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [7]),
.I1(RD_PNTR_WR[7]),
.O(\wr_data_count_i_reg[7] [3]));
LUT2 #(
.INIT(4'h9))
minusOp_carry__0_i_2
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [6]),
.I1(RD_PNTR_WR[6]),
.O(\wr_data_count_i_reg[7] [2]));
LUT2 #(
.INIT(4'h9))
minusOp_carry__0_i_3
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [5]),
.I1(RD_PNTR_WR[5]),
.O(\wr_data_count_i_reg[7] [1]));
LUT2 #(
.INIT(4'h9))
minusOp_carry__0_i_4
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [4]),
.I1(RD_PNTR_WR[4]),
.O(\wr_data_count_i_reg[7] [0]));
LUT2 #(
.INIT(4'h9))
minusOp_carry__1_i_1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [9]),
.I1(RD_PNTR_WR[9]),
.O(\wr_data_count_i_reg[9] [1]));
LUT2 #(
.INIT(4'h9))
minusOp_carry__1_i_2
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [8]),
.I1(RD_PNTR_WR[8]),
.O(\wr_data_count_i_reg[9] [0]));
LUT2 #(
.INIT(4'h9))
minusOp_carry_i_1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [3]),
.I1(RD_PNTR_WR[3]),
.O(S[3]));
LUT2 #(
.INIT(4'h9))
minusOp_carry_i_2
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [2]),
.I1(RD_PNTR_WR[2]),
.O(S[2]));
LUT2 #(
.INIT(4'h9))
minusOp_carry_i_3
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [1]),
.I1(RD_PNTR_WR[1]),
.O(S[1]));
LUT2 #(
.INIT(4'h9))
minusOp_carry_i_4
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [0]),
.I1(RD_PNTR_WR[0]),
.O(S[0]));
LUT2 #(
.INIT(4'h9))
plusOp_carry__0_i_1
(.I0(Q[7]),
.I1(RD_PNTR_WR[7]),
.O(\gdiff.diff_pntr_pad_reg[8] [3]));
LUT2 #(
.INIT(4'h9))
plusOp_carry__0_i_2
(.I0(Q[6]),
.I1(RD_PNTR_WR[6]),
.O(\gdiff.diff_pntr_pad_reg[8] [2]));
LUT2 #(
.INIT(4'h9))
plusOp_carry__0_i_3
(.I0(Q[5]),
.I1(RD_PNTR_WR[5]),
.O(\gdiff.diff_pntr_pad_reg[8] [1]));
LUT2 #(
.INIT(4'h9))
plusOp_carry__0_i_4
(.I0(Q[4]),
.I1(RD_PNTR_WR[4]),
.O(\gdiff.diff_pntr_pad_reg[8] [0]));
LUT2 #(
.INIT(4'h9))
plusOp_carry__1_i_1
(.I0(p_13_out),
.I1(RD_PNTR_WR[9]),
.O(\gdiff.diff_pntr_pad_reg[10] [1]));
LUT2 #(
.INIT(4'h9))
plusOp_carry__1_i_2
(.I0(Q[8]),
.I1(RD_PNTR_WR[8]),
.O(\gdiff.diff_pntr_pad_reg[10] [0]));
LUT2 #(
.INIT(4'h9))
plusOp_carry_i_1
(.I0(Q[3]),
.I1(RD_PNTR_WR[3]),
.O(\gdiff.diff_pntr_pad_reg[4] [3]));
LUT2 #(
.INIT(4'h9))
plusOp_carry_i_2
(.I0(Q[2]),
.I1(RD_PNTR_WR[2]),
.O(\gdiff.diff_pntr_pad_reg[4] [2]));
LUT2 #(
.INIT(4'h9))
plusOp_carry_i_3
(.I0(Q[1]),
.I1(RD_PNTR_WR[1]),
.O(\gdiff.diff_pntr_pad_reg[4] [1]));
LUT2 #(
.INIT(4'h9))
plusOp_carry_i_4
(.I0(Q[0]),
.I1(RD_PNTR_WR[0]),
.O(\gdiff.diff_pntr_pad_reg[4] [0]));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_dc_as
(wr_data_count,
\gic0.gc0.count_d2_reg[8] ,
S,
\gic0.gc0.count_d2_reg[7] ,
\gic0.gc0.count_d2_reg[9] ,
wr_clk,
AR);
output [9:0]wr_data_count;
input [8:0]\gic0.gc0.count_d2_reg[8] ;
input [3:0]S;
input [3:0]\gic0.gc0.count_d2_reg[7] ;
input [1:0]\gic0.gc0.count_d2_reg[9] ;
input wr_clk;
input [0:0]AR;
wire [0:0]AR;
wire [3:0]S;
wire [3:0]\gic0.gc0.count_d2_reg[7] ;
wire [8:0]\gic0.gc0.count_d2_reg[8] ;
wire [1:0]\gic0.gc0.count_d2_reg[9] ;
wire minusOp_carry__0_n_0;
wire minusOp_carry__0_n_1;
wire minusOp_carry__0_n_2;
wire minusOp_carry__0_n_3;
wire minusOp_carry__0_n_4;
wire minusOp_carry__0_n_5;
wire minusOp_carry__0_n_6;
wire minusOp_carry__0_n_7;
wire minusOp_carry__1_n_3;
wire minusOp_carry__1_n_6;
wire minusOp_carry__1_n_7;
wire minusOp_carry_n_0;
wire minusOp_carry_n_1;
wire minusOp_carry_n_2;
wire minusOp_carry_n_3;
wire minusOp_carry_n_4;
wire minusOp_carry_n_5;
wire minusOp_carry_n_6;
wire minusOp_carry_n_7;
wire wr_clk;
wire [9:0]wr_data_count;
wire [3:1]NLW_minusOp_carry__1_CO_UNCONNECTED;
wire [3:2]NLW_minusOp_carry__1_O_UNCONNECTED;
CARRY4 minusOp_carry
(.CI(1'b0),
.CO({minusOp_carry_n_0,minusOp_carry_n_1,minusOp_carry_n_2,minusOp_carry_n_3}),
.CYINIT(1'b1),
.DI(\gic0.gc0.count_d2_reg[8] [3:0]),
.O({minusOp_carry_n_4,minusOp_carry_n_5,minusOp_carry_n_6,minusOp_carry_n_7}),
.S(S));
CARRY4 minusOp_carry__0
(.CI(minusOp_carry_n_0),
.CO({minusOp_carry__0_n_0,minusOp_carry__0_n_1,minusOp_carry__0_n_2,minusOp_carry__0_n_3}),
.CYINIT(1'b0),
.DI(\gic0.gc0.count_d2_reg[8] [7:4]),
.O({minusOp_carry__0_n_4,minusOp_carry__0_n_5,minusOp_carry__0_n_6,minusOp_carry__0_n_7}),
.S(\gic0.gc0.count_d2_reg[7] ));
CARRY4 minusOp_carry__1
(.CI(minusOp_carry__0_n_0),
.CO({NLW_minusOp_carry__1_CO_UNCONNECTED[3:1],minusOp_carry__1_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,\gic0.gc0.count_d2_reg[8] [8]}),
.O({NLW_minusOp_carry__1_O_UNCONNECTED[3:2],minusOp_carry__1_n_6,minusOp_carry__1_n_7}),
.S({1'b0,1'b0,\gic0.gc0.count_d2_reg[9] }));
FDCE #(
.INIT(1'b0))
\wr_data_count_i_reg[0]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(minusOp_carry_n_7),
.Q(wr_data_count[0]));
FDCE #(
.INIT(1'b0))
\wr_data_count_i_reg[1]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(minusOp_carry_n_6),
.Q(wr_data_count[1]));
FDCE #(
.INIT(1'b0))
\wr_data_count_i_reg[2]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(minusOp_carry_n_5),
.Q(wr_data_count[2]));
FDCE #(
.INIT(1'b0))
\wr_data_count_i_reg[3]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(minusOp_carry_n_4),
.Q(wr_data_count[3]));
FDCE #(
.INIT(1'b0))
\wr_data_count_i_reg[4]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(minusOp_carry__0_n_7),
.Q(wr_data_count[4]));
FDCE #(
.INIT(1'b0))
\wr_data_count_i_reg[5]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(minusOp_carry__0_n_6),
.Q(wr_data_count[5]));
FDCE #(
.INIT(1'b0))
\wr_data_count_i_reg[6]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(minusOp_carry__0_n_5),
.Q(wr_data_count[6]));
FDCE #(
.INIT(1'b0))
\wr_data_count_i_reg[7]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(minusOp_carry__0_n_4),
.Q(wr_data_count[7]));
FDCE #(
.INIT(1'b0))
\wr_data_count_i_reg[8]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(minusOp_carry__1_n_7),
.Q(wr_data_count[8]));
FDCE #(
.INIT(1'b0))
\wr_data_count_i_reg[9]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(minusOp_carry__1_n_6),
.Q(wr_data_count[9]));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic
(full,
E,
Q,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ,
prog_full,
\gic0.gc0.count_d1_reg[9] ,
wr_data_count,
\gnxpm_cdc.rd_pntr_bin_reg[6] ,
v1_reg,
wr_clk,
out,
RD_PNTR_WR,
wr_en,
wr_rst_busy,
AR);
output full;
output [0:0]E;
output [7:0]Q;
output [9:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
output prog_full;
output [9:0]\gic0.gc0.count_d1_reg[9] ;
output [9:0]wr_data_count;
input [3:0]\gnxpm_cdc.rd_pntr_bin_reg[6] ;
input [4:0]v1_reg;
input wr_clk;
input out;
input [9:0]RD_PNTR_WR;
input wr_en;
input wr_rst_busy;
input [0:0]AR;
wire [0:0]AR;
wire [9:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
wire [0:0]E;
wire [7:0]Q;
wire [9:0]RD_PNTR_WR;
wire [4:4]\c1/v1_reg ;
wire full;
wire [9:0]\gic0.gc0.count_d1_reg[9] ;
wire [3:0]\gnxpm_cdc.rd_pntr_bin_reg[6] ;
wire \gwas.wsts_n_1 ;
wire out;
wire [8:8]p_13_out;
wire prog_full;
wire [4:0]v1_reg;
wire wpntr_n_0;
wire wpntr_n_1;
wire wpntr_n_12;
wire wpntr_n_13;
wire wpntr_n_23;
wire wpntr_n_24;
wire wpntr_n_25;
wire wpntr_n_26;
wire wpntr_n_27;
wire wpntr_n_28;
wire wpntr_n_29;
wire wpntr_n_30;
wire wpntr_n_31;
wire wpntr_n_32;
wire wpntr_n_33;
wire wpntr_n_34;
wire wpntr_n_35;
wire wpntr_n_36;
wire wpntr_n_37;
wire wpntr_n_38;
wire wr_clk;
wire [9:0]wr_data_count;
wire wr_en;
wire wr_rst_busy;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_pf_as \gwas.gpf.wrpf
(.AR(AR),
.E(E),
.Q({p_13_out,Q}),
.S({wpntr_n_35,wpntr_n_36,wpntr_n_37,wpntr_n_38}),
.\gic0.gc0.count_d1_reg[7] ({wpntr_n_27,wpntr_n_28,wpntr_n_29,wpntr_n_30}),
.\gic0.gc0.count_d1_reg[9] ({wpntr_n_12,wpntr_n_13}),
.out(out),
.prog_full(prog_full),
.ram_full_fb_i_reg(\gwas.wsts_n_1 ),
.wr_clk(wr_clk),
.wr_rst_busy(wr_rst_busy));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_dc_as \gwas.gwdc0.wdc
(.AR(AR),
.S({wpntr_n_31,wpntr_n_32,wpntr_n_33,wpntr_n_34}),
.\gic0.gc0.count_d2_reg[7] ({wpntr_n_23,wpntr_n_24,wpntr_n_25,wpntr_n_26}),
.\gic0.gc0.count_d2_reg[8] (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [8:0]),
.\gic0.gc0.count_d2_reg[9] ({wpntr_n_0,wpntr_n_1}),
.wr_clk(wr_clk),
.wr_data_count(wr_data_count));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_as \gwas.wsts
(.E(E),
.full(full),
.\gnxpm_cdc.rd_pntr_bin_reg[6] (\gnxpm_cdc.rd_pntr_bin_reg[6] ),
.\grstd1.grst_full.grst_f.rst_d2_reg (out),
.out(\gwas.wsts_n_1 ),
.v1_reg(v1_reg),
.v1_reg_0(\c1/v1_reg ),
.wr_clk(wr_clk),
.wr_en(wr_en),
.wr_rst_busy(wr_rst_busy));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr wpntr
(.AR(AR),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ),
.E(E),
.Q({p_13_out,Q}),
.RD_PNTR_WR(RD_PNTR_WR),
.S({wpntr_n_31,wpntr_n_32,wpntr_n_33,wpntr_n_34}),
.\gdiff.diff_pntr_pad_reg[10] ({wpntr_n_12,wpntr_n_13}),
.\gdiff.diff_pntr_pad_reg[4] ({wpntr_n_35,wpntr_n_36,wpntr_n_37,wpntr_n_38}),
.\gdiff.diff_pntr_pad_reg[8] ({wpntr_n_27,wpntr_n_28,wpntr_n_29,wpntr_n_30}),
.\gic0.gc0.count_d1_reg[9]_0 (\gic0.gc0.count_d1_reg[9] ),
.v1_reg(\c1/v1_reg ),
.wr_clk(wr_clk),
.\wr_data_count_i_reg[7] ({wpntr_n_23,wpntr_n_24,wpntr_n_25,wpntr_n_26}),
.\wr_data_count_i_reg[9] ({wpntr_n_0,wpntr_n_1}));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_pf_as
(prog_full,
E,
Q,
S,
\gic0.gc0.count_d1_reg[7] ,
\gic0.gc0.count_d1_reg[9] ,
wr_clk,
out,
wr_rst_busy,
ram_full_fb_i_reg,
AR);
output prog_full;
input [0:0]E;
input [8:0]Q;
input [3:0]S;
input [3:0]\gic0.gc0.count_d1_reg[7] ;
input [1:0]\gic0.gc0.count_d1_reg[9] ;
input wr_clk;
input out;
input wr_rst_busy;
input ram_full_fb_i_reg;
input [0:0]AR;
wire [0:0]AR;
wire [0:0]E;
wire [8:0]Q;
wire [3:0]S;
wire [9:1]diff_pntr;
wire [3:0]\gic0.gc0.count_d1_reg[7] ;
wire [1:0]\gic0.gc0.count_d1_reg[9] ;
wire \gpf1.prog_full_i_i_1_n_0 ;
wire \gpf1.prog_full_i_i_2_n_0 ;
wire \gpf1.prog_full_i_i_3_n_0 ;
wire out;
wire plusOp_carry__0_n_0;
wire plusOp_carry__0_n_1;
wire plusOp_carry__0_n_2;
wire plusOp_carry__0_n_3;
wire plusOp_carry__0_n_4;
wire plusOp_carry__0_n_5;
wire plusOp_carry__0_n_6;
wire plusOp_carry__0_n_7;
wire plusOp_carry__1_n_3;
wire plusOp_carry__1_n_6;
wire plusOp_carry__1_n_7;
wire plusOp_carry_n_0;
wire plusOp_carry_n_1;
wire plusOp_carry_n_2;
wire plusOp_carry_n_3;
wire plusOp_carry_n_4;
wire plusOp_carry_n_5;
wire plusOp_carry_n_6;
wire prog_full;
wire ram_full_fb_i_reg;
wire wr_clk;
wire wr_rst_busy;
wire [0:0]NLW_plusOp_carry_O_UNCONNECTED;
wire [3:1]NLW_plusOp_carry__1_CO_UNCONNECTED;
wire [3:2]NLW_plusOp_carry__1_O_UNCONNECTED;
FDCE #(
.INIT(1'b0))
\gdiff.diff_pntr_pad_reg[10]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(plusOp_carry__1_n_6),
.Q(diff_pntr[9]));
FDCE #(
.INIT(1'b0))
\gdiff.diff_pntr_pad_reg[2]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(plusOp_carry_n_6),
.Q(diff_pntr[1]));
FDCE #(
.INIT(1'b0))
\gdiff.diff_pntr_pad_reg[3]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(plusOp_carry_n_5),
.Q(diff_pntr[2]));
FDCE #(
.INIT(1'b0))
\gdiff.diff_pntr_pad_reg[4]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(plusOp_carry_n_4),
.Q(diff_pntr[3]));
FDCE #(
.INIT(1'b0))
\gdiff.diff_pntr_pad_reg[5]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(plusOp_carry__0_n_7),
.Q(diff_pntr[4]));
FDCE #(
.INIT(1'b0))
\gdiff.diff_pntr_pad_reg[6]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(plusOp_carry__0_n_6),
.Q(diff_pntr[5]));
FDCE #(
.INIT(1'b0))
\gdiff.diff_pntr_pad_reg[7]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(plusOp_carry__0_n_5),
.Q(diff_pntr[6]));
FDCE #(
.INIT(1'b0))
\gdiff.diff_pntr_pad_reg[8]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(plusOp_carry__0_n_4),
.Q(diff_pntr[7]));
FDCE #(
.INIT(1'b0))
\gdiff.diff_pntr_pad_reg[9]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(plusOp_carry__1_n_7),
.Q(diff_pntr[8]));
LUT5 #(
.INIT(32'h0F070007))
\gpf1.prog_full_i_i_1
(.I0(\gpf1.prog_full_i_i_2_n_0 ),
.I1(\gpf1.prog_full_i_i_3_n_0 ),
.I2(wr_rst_busy),
.I3(ram_full_fb_i_reg),
.I4(prog_full),
.O(\gpf1.prog_full_i_i_1_n_0 ));
LUT6 #(
.INIT(64'h00000001FFFFFFFF))
\gpf1.prog_full_i_i_2
(.I0(diff_pntr[4]),
.I1(diff_pntr[5]),
.I2(diff_pntr[3]),
.I3(diff_pntr[2]),
.I4(diff_pntr[1]),
.I5(diff_pntr[6]),
.O(\gpf1.prog_full_i_i_2_n_0 ));
LUT3 #(
.INIT(8'h01))
\gpf1.prog_full_i_i_3
(.I0(diff_pntr[9]),
.I1(diff_pntr[8]),
.I2(diff_pntr[7]),
.O(\gpf1.prog_full_i_i_3_n_0 ));
FDPE #(
.INIT(1'b1))
\gpf1.prog_full_i_reg
(.C(wr_clk),
.CE(1'b1),
.D(\gpf1.prog_full_i_i_1_n_0 ),
.PRE(out),
.Q(prog_full));
CARRY4 plusOp_carry
(.CI(1'b0),
.CO({plusOp_carry_n_0,plusOp_carry_n_1,plusOp_carry_n_2,plusOp_carry_n_3}),
.CYINIT(E),
.DI(Q[3:0]),
.O({plusOp_carry_n_4,plusOp_carry_n_5,plusOp_carry_n_6,NLW_plusOp_carry_O_UNCONNECTED[0]}),
.S(S));
CARRY4 plusOp_carry__0
(.CI(plusOp_carry_n_0),
.CO({plusOp_carry__0_n_0,plusOp_carry__0_n_1,plusOp_carry__0_n_2,plusOp_carry__0_n_3}),
.CYINIT(1'b0),
.DI(Q[7:4]),
.O({plusOp_carry__0_n_4,plusOp_carry__0_n_5,plusOp_carry__0_n_6,plusOp_carry__0_n_7}),
.S(\gic0.gc0.count_d1_reg[7] ));
CARRY4 plusOp_carry__1
(.CI(plusOp_carry__0_n_0),
.CO({NLW_plusOp_carry__1_CO_UNCONNECTED[3:1],plusOp_carry__1_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,Q[8]}),
.O({NLW_plusOp_carry__1_O_UNCONNECTED[3:2],plusOp_carry__1_n_6,plusOp_carry__1_n_7}),
.S({1'b0,1'b0,\gic0.gc0.count_d1_reg[9] }));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_as
(full,
out,
E,
\gnxpm_cdc.rd_pntr_bin_reg[6] ,
v1_reg_0,
v1_reg,
wr_clk,
\grstd1.grst_full.grst_f.rst_d2_reg ,
wr_en,
wr_rst_busy);
output full;
output out;
output [0:0]E;
input [3:0]\gnxpm_cdc.rd_pntr_bin_reg[6] ;
input [0:0]v1_reg_0;
input [4:0]v1_reg;
input wr_clk;
input \grstd1.grst_full.grst_f.rst_d2_reg ;
input wr_en;
input wr_rst_busy;
wire [0:0]E;
wire c2_n_0;
wire comp1;
wire [3:0]\gnxpm_cdc.rd_pntr_bin_reg[6] ;
wire \grstd1.grst_full.grst_f.rst_d2_reg ;
(* DONT_TOUCH *) wire ram_full_fb_i;
(* DONT_TOUCH *) wire ram_full_i;
wire [4:0]v1_reg;
wire [0:0]v1_reg_0;
wire wr_clk;
wire wr_en;
wire wr_rst_busy;
assign full = ram_full_i;
assign out = ram_full_fb_i;
LUT2 #(
.INIT(4'h2))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1
(.I0(wr_en),
.I1(ram_full_fb_i),
.O(E));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare c1
(.comp1(comp1),
.\gnxpm_cdc.rd_pntr_bin_reg[6] (\gnxpm_cdc.rd_pntr_bin_reg[6] ),
.v1_reg_0(v1_reg_0));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_3 c2
(.comp1(comp1),
.out(ram_full_fb_i),
.ram_full_fb_i_reg(c2_n_0),
.v1_reg(v1_reg),
.wr_en(wr_en),
.wr_rst_busy(wr_rst_busy));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_full_fb_i_reg
(.C(wr_clk),
.CE(1'b1),
.D(c2_n_0),
.PRE(\grstd1.grst_full.grst_f.rst_d2_reg ),
.Q(ram_full_fb_i));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_full_i_reg
(.C(wr_clk),
.CE(1'b1),
.D(c2_n_0),
.PRE(\grstd1.grst_full.grst_f.rst_d2_reg ),
.Q(ram_full_i));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
/*
Filename: translation_layer.v
Version: 1.0
Verilog Standard: Verilog-2001
Description: The translation layer provides a uniform interface for all classic
PCIe interfaces, such as all Altera devices, and all Xilinx devices (pre VC709).
Notes: Any modifications to this file should meet the conditions set
forth in the "Trellis Style Guide"
Author: Dustin Richmond (@darichmond)
Co-Authors:
*/
`include "trellis.vh" // Defines the user-facing signal widths.
`include "xilinx.vh"
module translation_xilinx
#(
parameter C_PCI_DATA_WIDTH = 256
)
(
input CLK,
input RST_IN,
// Interface: Xilinx RX
input [C_PCI_DATA_WIDTH-1:0] M_AXIS_RX_TDATA,
input [(C_PCI_DATA_WIDTH/8)-1:0] M_AXIS_RX_TKEEP,
input M_AXIS_RX_TLAST,
input M_AXIS_RX_TVALID,
output M_AXIS_RX_TREADY,
input [`SIG_XIL_RX_TUSER_W-1:0] M_AXIS_RX_TUSER,
output RX_NP_OK,
output RX_NP_REQ,
// Interface: Xilinx TX
output [C_PCI_DATA_WIDTH-1:0] S_AXIS_TX_TDATA,
output [(C_PCI_DATA_WIDTH/8)-1:0] S_AXIS_TX_TKEEP,
output S_AXIS_TX_TLAST,
output S_AXIS_TX_TVALID,
input S_AXIS_TX_TREADY,
output [`SIG_XIL_TX_TUSER_W-1:0] S_AXIS_TX_TUSER,
output TX_CFG_GNT,
// Interface: Xilinx Configuration
input [`SIG_BUSID_W-1:0] CFG_BUS_NUMBER,
input [`SIG_DEVID_W-1:0] CFG_DEVICE_NUMBER,
input [`SIG_FNID_W-1:0] CFG_FUNCTION_NUMBER,
input [`SIG_CFGREG_W-1:0] CFG_COMMAND,
input [`SIG_CFGREG_W-1:0] CFG_DCOMMAND,
input [`SIG_CFGREG_W-1:0] CFG_LSTATUS,
input [`SIG_CFGREG_W-1:0] CFG_LCOMMAND,
// Interface: Xilinx Flow Control
input [`SIG_FC_CPLD_W-1:0] FC_CPLD,
input [`SIG_FC_CPLH_W-1:0] FC_CPLH,
output [`SIG_FC_SEL_W-1:0] FC_SEL,
// Interface: Xilinx Interrupt
input CFG_INTERRUPT_MSIEN,
input CFG_INTERRUPT_RDY,
output CFG_INTERRUPT,
// Interface: RX Classic
output [C_PCI_DATA_WIDTH-1:0] RX_TLP,
output RX_TLP_VALID,
output RX_TLP_START_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RX_TLP_START_OFFSET,
output RX_TLP_END_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RX_TLP_END_OFFSET,
output [`SIG_BARDECODE_W-1:0] RX_TLP_BAR_DECODE,
input RX_TLP_READY,
// Interface: TX Classic
output TX_TLP_READY,
input [C_PCI_DATA_WIDTH-1:0] TX_TLP,
input TX_TLP_VALID,
input TX_TLP_START_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TX_TLP_START_OFFSET,
input TX_TLP_END_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TX_TLP_END_OFFSET,
// Interface: Configuration
output [`SIG_CPLID_W-1:0] CONFIG_COMPLETER_ID,
output CONFIG_BUS_MASTER_ENABLE,
output [`SIG_LINKWIDTH_W-1:0] CONFIG_LINK_WIDTH,
output [`SIG_LINKRATE_W-1:0] CONFIG_LINK_RATE,
output [`SIG_MAXREAD_W-1:0] CONFIG_MAX_READ_REQUEST_SIZE,
output [`SIG_MAXPAYLOAD_W-1:0] CONFIG_MAX_PAYLOAD_SIZE,
output CONFIG_INTERRUPT_MSIENABLE,
output CONFIG_CPL_BOUNDARY_SEL,
// Interface: Flow Control
output [`SIG_FC_CPLD_W-1:0] CONFIG_MAX_CPL_DATA,
output [`SIG_FC_CPLH_W-1:0] CONFIG_MAX_CPL_HDR,
// Interface: Interrupt
output INTR_MSI_RDY, // High when interrupt is able to be sent
input INTR_MSI_REQUEST // High to request interrupt
);
/*
Notes on the Configuration Interface:
Link Width (cfg_lstatus[9:4]): 000001=x1, 000010=x2, 000100=x4, 001000=x8, 001100=x12, 010000=x16
Link Rate (cfg_lstatus[3:0]): 0001=2.5GT/s, 0010=5.0GT/s, 0011=8.0GT/s
Max Read Request Size (cfg_dcommand[14:12]): 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
Max Payload Size (cfg_dcommand[7:5]): 000=128B, 001=256B, 010=512B, 011=1024B
Bus Master Enable (cfg_command[2]): 1=Enabled, 0=Disabled
Read Completion Boundary (cfg_lcommand[3]): 0=64 bytes, 1=128 bytes
MSI Enable (cfg_msicsr[0]): 1=Enabled, 0=Disabled
Notes on the Flow Control Interface:
FC_CPLD (Xilinx) Receive credit limit for data
FC_CPLH (Xilinx) Receive credit limit for headers
FC_SEL (Xilinx Only) Selects the correct output on the FC_* signals
Notes on the TX Interface:
TX_CFG_GNT (Xilinx): 1=Always allow core to transmit internally generated TLPs
Notes on the RX Interface:
RX_NP_OK (Xilinx): 1=Always allow non posted transactions
*/
/*AUTOWIRE*/
reg rRxTlpValid;
reg rRxTlpEndFlag;
// Rx Interface (From PCIe Core)
assign RX_TLP = M_AXIS_RX_TDATA;
assign RX_TLP_VALID = M_AXIS_RX_TVALID;
// Rx Interface (To PCIe Core)
assign M_AXIS_RX_TREADY = RX_TLP_READY;
// TX Interface (From PCIe Core)
assign TX_TLP_READY = S_AXIS_TX_TREADY;
// TX Interface (TO PCIe Core)
assign S_AXIS_TX_TDATA = TX_TLP;
assign S_AXIS_TX_TVALID = TX_TLP_VALID;
assign S_AXIS_TX_TLAST = TX_TLP_END_FLAG;
// Configuration Interface
assign CONFIG_COMPLETER_ID = {CFG_BUS_NUMBER,CFG_DEVICE_NUMBER,CFG_FUNCTION_NUMBER};
assign CONFIG_BUS_MASTER_ENABLE = CFG_COMMAND[`CFG_COMMAND_BUSMSTR_R];
assign CONFIG_LINK_WIDTH = CFG_LSTATUS[`CFG_LSTATUS_LWIDTH_R];
assign CONFIG_LINK_RATE = CFG_LSTATUS[`CFG_LSTATUS_LRATE_R];
assign CONFIG_MAX_READ_REQUEST_SIZE = CFG_DCOMMAND[`CFG_DCOMMAND_MAXREQ_R];
assign CONFIG_MAX_PAYLOAD_SIZE = CFG_DCOMMAND[`CFG_DCOMMAND_MAXPAY_R];
assign CONFIG_INTERRUPT_MSIENABLE = CFG_INTERRUPT_MSIEN;
assign CONFIG_CPL_BOUNDARY_SEL = CFG_LCOMMAND[`CFG_LCOMMAND_RCB_R];
assign CONFIG_MAX_CPL_DATA = FC_CPLD;
assign CONFIG_MAX_CPL_HDR = FC_CPLH;
assign FC_SEL = `SIG_FC_SEL_RX_MAXALLOC_V;
assign RX_NP_OK = 1'b1;
assign RX_NP_REQ = 1'b1;
assign TX_CFG_GNT = 1'b1;
// Interrupt interface
assign CFG_INTERRUPT = INTR_MSI_REQUEST;
assign INTR_MSI_RDY = CFG_INTERRUPT_RDY;
generate
if (C_PCI_DATA_WIDTH == 9'd32) begin : gen_xilinx_32
assign RX_TLP_START_FLAG = ~rRxTlpValid | rRxTlpEndFlag;
assign RX_TLP_START_OFFSET = {clog2s(C_PCI_DATA_WIDTH/32){1'b0}};
assign RX_TLP_END_OFFSET = 0;
assign RX_TLP_END_FLAG = M_AXIS_RX_TLAST;
assign S_AXIS_TX_TKEEP = 4'hF;
end else if (C_PCI_DATA_WIDTH == 9'd64) begin : gen_xilinx_64
assign RX_TLP_START_FLAG = ~rRxTlpValid | rRxTlpEndFlag;
assign RX_TLP_START_OFFSET = {clog2s(C_PCI_DATA_WIDTH/32){1'b0}};
assign RX_TLP_END_OFFSET = M_AXIS_RX_TKEEP[4];
assign RX_TLP_END_FLAG = M_AXIS_RX_TLAST;
assign S_AXIS_TX_TKEEP = {{4{TX_TLP_END_OFFSET | ~TX_TLP_END_FLAG}},4'hF};
end else if (C_PCI_DATA_WIDTH == 9'd128) begin : gen_xilinx_128
assign RX_TLP_END_OFFSET = M_AXIS_RX_TUSER[20:19];
assign RX_TLP_END_FLAG = M_AXIS_RX_TUSER[21];
assign RX_TLP_START_FLAG = M_AXIS_RX_TUSER[14];
assign RX_TLP_START_OFFSET = M_AXIS_RX_TUSER[13:12];
assign S_AXIS_TX_TKEEP = {{4{~TX_TLP_END_FLAG | (TX_TLP_END_OFFSET == 2'b11)}},
{4{~TX_TLP_END_FLAG | (TX_TLP_END_OFFSET >= 2'b10)}},
{4{~TX_TLP_END_FLAG | (TX_TLP_END_OFFSET >= 2'b01)}},
{4{1'b1}}};// TODO: More efficient if we use masks...
end else if (C_PCI_DATA_WIDTH == 9'd256) begin : x256
// Not possible...
end
endgenerate
always @(posedge CLK) begin
rRxTlpValid <= RX_TLP_VALID;
rRxTlpEndFlag <= RX_TLP_END_FLAG;
end
endmodule // translation_layer
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFRTP_1_V
`define SKY130_FD_SC_MS__DFRTP_1_V
/**
* dfrtp: Delay flop, inverted reset, single output.
*
* Verilog wrapper for dfrtp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__dfrtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__dfrtp_1 (
Q ,
CLK ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_ms__dfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__dfrtp_1 (
Q ,
CLK ,
D ,
RESET_B
);
output Q ;
input CLK ;
input D ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__dfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFRTP_1_V
|
/*
* Copyright (c) 2001 Brendan J Simon <[email protected]>
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
// test case to show vector ordering bugs.
module test;
reg [4:0] foo40; // works great.
reg [0:4] foo04; // only works for time=0;
//reg [4:0] foo04;
reg [5:1] foo51; // never works.
//reg [4:0] foo51;
reg [1:5] foo15; // never works.
//reg [4:0] foo15;
initial begin
#102; $finish;
end
initial #1 begin
foo40 = 0;
foo04 = 0;
foo51 = 0;
foo15 = 0;
end
always #10 begin
foo40 <= foo40 + 1;
foo04 <= foo04 + 1;
foo51 <= foo51 + 1;
foo15 <= foo15 + 1;
end
always @(foo40) begin
$write("foo40=%8d\n", foo40);
end
always @(foo04) begin
$write(" foo04=%8d\n", foo04);
end
always @(foo51) begin
$write(" foo51=%8d\n", foo51);
end
always @(foo15) begin
$write(" foo15=%8d\n", foo15);
end
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2014 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2014.3
// \ \ Description : Xilinx Unified Simulation Library Component
// / / 36K-bit Configurable Synchronous Block RAM
// /___/ /\ Filename : RAMB36E2.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 02/28/2013 - intial from FIFO
// 03/09/2013 - update from various initial CR - collisions
// 03/19/2013 - 707443 - RDADDRECC not hooked up
// 03/22/2013 - sync5 yaml update, port ordering
// 03/25/2013 - 707719 - Add sync5 cascade feature
// 03/27/2013 - revert NO_CHANGE fix
// 04/04/2013 - 709962 - typo CASDOUTPA/PB vs CASDOUTAP/BP
// 04/23/2013 - PR683925 - add invertible pin support.
// 04/26/2013 - 714182 - RDADDRECC bits shifted by 1.
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module RAMB36E2 #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter CASCADE_ORDER_A = "NONE",
parameter CASCADE_ORDER_B = "NONE",
parameter CLOCK_DOMAINS = "INDEPENDENT",
parameter integer DOA_REG = 1,
parameter integer DOB_REG = 1,
parameter ENADDRENA = "FALSE",
parameter ENADDRENB = "FALSE",
parameter EN_ECC_PIPE = "FALSE",
parameter EN_ECC_READ = "FALSE",
parameter EN_ECC_WRITE = "FALSE",
parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INITP_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INITP_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INITP_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INITP_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INITP_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INITP_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INITP_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INITP_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_40 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_41 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_42 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_43 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_44 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_45 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_46 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_47 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_48 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_49 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_4A = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_4B = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_4C = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_4D = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_4E = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_4F = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_50 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_51 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_52 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_53 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_54 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_55 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_56 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_57 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_58 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_59 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_5A = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_5B = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_5C = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_5D = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_5E = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_5F = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_60 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_61 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_62 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_63 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_64 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_65 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_66 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_67 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_68 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_69 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_6A = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_6B = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_6C = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_6D = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_6E = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_6F = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_70 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_71 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_72 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_73 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_74 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_75 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_76 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_77 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_78 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_79 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_7A = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_7B = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_7C = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_7D = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_7E = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [255:0] INIT_7F = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter [35:0] INIT_A = 36'h000000000,
parameter [35:0] INIT_B = 36'h000000000,
parameter INIT_FILE = "NONE",
parameter [0:0] IS_CLKARDCLK_INVERTED = 1'b0,
parameter [0:0] IS_CLKBWRCLK_INVERTED = 1'b0,
parameter [0:0] IS_ENARDEN_INVERTED = 1'b0,
parameter [0:0] IS_ENBWREN_INVERTED = 1'b0,
parameter [0:0] IS_RSTRAMARSTRAM_INVERTED = 1'b0,
parameter [0:0] IS_RSTRAMB_INVERTED = 1'b0,
parameter [0:0] IS_RSTREGARSTREG_INVERTED = 1'b0,
parameter [0:0] IS_RSTREGB_INVERTED = 1'b0,
parameter RDADDRCHANGEA = "FALSE",
parameter RDADDRCHANGEB = "FALSE",
parameter integer READ_WIDTH_A = 0,
parameter integer READ_WIDTH_B = 0,
parameter RSTREG_PRIORITY_A = "RSTREG",
parameter RSTREG_PRIORITY_B = "RSTREG",
parameter SIM_COLLISION_CHECK = "ALL",
parameter SLEEP_ASYNC = "FALSE",
parameter [35:0] SRVAL_A = 36'h000000000,
parameter [35:0] SRVAL_B = 36'h000000000,
parameter WRITE_MODE_A = "NO_CHANGE",
parameter WRITE_MODE_B = "NO_CHANGE",
parameter integer WRITE_WIDTH_A = 0,
parameter integer WRITE_WIDTH_B = 0
)(
output [31:0] CASDOUTA,
output [31:0] CASDOUTB,
output [3:0] CASDOUTPA,
output [3:0] CASDOUTPB,
output CASOUTDBITERR,
output CASOUTSBITERR,
output DBITERR,
output [31:0] DOUTADOUT,
output [31:0] DOUTBDOUT,
output [3:0] DOUTPADOUTP,
output [3:0] DOUTPBDOUTP,
output [7:0] ECCPARITY,
output [8:0] RDADDRECC,
output SBITERR,
input [14:0] ADDRARDADDR,
input [14:0] ADDRBWRADDR,
input ADDRENA,
input ADDRENB,
input CASDIMUXA,
input CASDIMUXB,
input [31:0] CASDINA,
input [31:0] CASDINB,
input [3:0] CASDINPA,
input [3:0] CASDINPB,
input CASDOMUXA,
input CASDOMUXB,
input CASDOMUXEN_A,
input CASDOMUXEN_B,
input CASINDBITERR,
input CASINSBITERR,
input CASOREGIMUXA,
input CASOREGIMUXB,
input CASOREGIMUXEN_A,
input CASOREGIMUXEN_B,
input CLKARDCLK,
input CLKBWRCLK,
input [31:0] DINADIN,
input [31:0] DINBDIN,
input [3:0] DINPADINP,
input [3:0] DINPBDINP,
input ECCPIPECE,
input ENARDEN,
input ENBWREN,
input INJECTDBITERR,
input INJECTSBITERR,
input REGCEAREGCE,
input REGCEB,
input RSTRAMARSTRAM,
input RSTRAMB,
input RSTREGARSTREG,
input RSTREGB,
input SLEEP,
input [3:0] WEA,
input [7:0] WEBWE
);
// define constants
localparam MODULE_NAME = "RAMB36E2";
// Parameter encodings and registers
localparam CASCADE_ORDER_A_FIRST = 1;
localparam CASCADE_ORDER_A_LAST = 2;
localparam CASCADE_ORDER_A_MIDDLE = 3;
localparam CASCADE_ORDER_A_NONE = 0;
localparam CASCADE_ORDER_B_FIRST = 1;
localparam CASCADE_ORDER_B_LAST = 2;
localparam CASCADE_ORDER_B_MIDDLE = 3;
localparam CASCADE_ORDER_B_NONE = 0;
localparam CLOCK_DOMAINS_COMMON = 1;
localparam CLOCK_DOMAINS_INDEPENDENT = 0;
localparam DOA_REG_0 = 1;
localparam DOA_REG_1 = 0;
localparam DOB_REG_0 = 1;
localparam DOB_REG_1 = 0;
localparam ENADDRENA_FALSE = 0;
localparam ENADDRENA_TRUE = 1;
localparam ENADDRENB_FALSE = 0;
localparam ENADDRENB_TRUE = 1;
localparam EN_ECC_PIPE_FALSE = 0;
localparam EN_ECC_PIPE_TRUE = 1;
localparam EN_ECC_READ_FALSE = 0;
localparam EN_ECC_READ_TRUE = 1;
localparam EN_ECC_WRITE_FALSE = 0;
localparam EN_ECC_WRITE_TRUE = 1;
localparam RDADDRCHANGEA_FALSE = 0;
localparam RDADDRCHANGEA_TRUE = 1;
localparam RDADDRCHANGEB_FALSE = 0;
localparam RDADDRCHANGEB_TRUE = 1;
localparam READ_WIDTH_A_0 = 1;
localparam READ_WIDTH_A_1 = 1;
localparam READ_WIDTH_A_18 = 16;
localparam READ_WIDTH_A_2 = 2;
localparam READ_WIDTH_A_36 = 32;
localparam READ_WIDTH_A_4 = 4;
localparam READ_WIDTH_A_72 = 64;
localparam READ_WIDTH_A_9 = 8;
localparam READ_WIDTH_B_0 = 1;
localparam READ_WIDTH_B_1 = 1;
localparam READ_WIDTH_B_18 = 16;
localparam READ_WIDTH_B_2 = 2;
localparam READ_WIDTH_B_36 = 32;
localparam READ_WIDTH_B_4 = 4;
localparam READ_WIDTH_B_9 = 8;
localparam RSTREG_PRIORITY_A_REGCE = 1;
localparam RSTREG_PRIORITY_A_RSTREG = 0;
localparam RSTREG_PRIORITY_B_REGCE = 1;
localparam RSTREG_PRIORITY_B_RSTREG = 0;
localparam SIM_COLLISION_CHECK_ALL = 0;
localparam SIM_COLLISION_CHECK_GENERATE_X_ONLY = 1;
localparam SIM_COLLISION_CHECK_NONE = 2;
localparam SIM_COLLISION_CHECK_WARNING_ONLY = 3;
localparam SLEEP_ASYNC_FALSE = 0;
localparam SLEEP_ASYNC_TRUE = 1;
localparam WRITE_MODE_A_NO_CHANGE = 0;
localparam WRITE_MODE_A_READ_FIRST = 1;
localparam WRITE_MODE_A_WRITE_FIRST = 2;
localparam WRITE_MODE_B_NO_CHANGE = 0;
localparam WRITE_MODE_B_READ_FIRST = 1;
localparam WRITE_MODE_B_WRITE_FIRST = 2;
localparam WRITE_WIDTH_A_0 = 1;
localparam WRITE_WIDTH_A_1 = 1;
localparam WRITE_WIDTH_A_18 = 16;
localparam WRITE_WIDTH_A_2 = 2;
localparam WRITE_WIDTH_A_36 = 32;
localparam WRITE_WIDTH_A_4 = 4;
localparam WRITE_WIDTH_A_9 = 8;
localparam WRITE_WIDTH_B_0 = 1;
localparam WRITE_WIDTH_B_1 = 1;
localparam WRITE_WIDTH_B_18 = 16;
localparam WRITE_WIDTH_B_2 = 2;
localparam WRITE_WIDTH_B_36 = 32;
localparam WRITE_WIDTH_B_4 = 4;
localparam WRITE_WIDTH_B_72 = 64;
localparam WRITE_WIDTH_B_9 = 8;
// include dynamic registers - XILINX test only
reg trig_attr = 1'b0;
`ifdef XIL_DR
`include "RAMB36E2_dr.v"
`else
localparam [48:1] CASCADE_ORDER_A_REG = CASCADE_ORDER_A;
localparam [48:1] CASCADE_ORDER_B_REG = CASCADE_ORDER_B;
localparam [88:1] CLOCK_DOMAINS_REG = CLOCK_DOMAINS;
localparam [0:0] DOA_REG_REG = DOA_REG;
localparam [0:0] DOB_REG_REG = DOB_REG;
localparam [40:1] ENADDRENA_REG = ENADDRENA;
localparam [40:1] ENADDRENB_REG = ENADDRENB;
localparam [40:1] EN_ECC_PIPE_REG = EN_ECC_PIPE;
localparam [40:1] EN_ECC_READ_REG = EN_ECC_READ;
localparam [40:1] EN_ECC_WRITE_REG = EN_ECC_WRITE;
localparam [255:0] INITP_00_REG = INITP_00;
localparam [255:0] INITP_01_REG = INITP_01;
localparam [255:0] INITP_02_REG = INITP_02;
localparam [255:0] INITP_03_REG = INITP_03;
localparam [255:0] INITP_04_REG = INITP_04;
localparam [255:0] INITP_05_REG = INITP_05;
localparam [255:0] INITP_06_REG = INITP_06;
localparam [255:0] INITP_07_REG = INITP_07;
localparam [255:0] INITP_08_REG = INITP_08;
localparam [255:0] INITP_09_REG = INITP_09;
localparam [255:0] INITP_0A_REG = INITP_0A;
localparam [255:0] INITP_0B_REG = INITP_0B;
localparam [255:0] INITP_0C_REG = INITP_0C;
localparam [255:0] INITP_0D_REG = INITP_0D;
localparam [255:0] INITP_0E_REG = INITP_0E;
localparam [255:0] INITP_0F_REG = INITP_0F;
localparam [255:0] INIT_00_REG = INIT_00;
localparam [255:0] INIT_01_REG = INIT_01;
localparam [255:0] INIT_02_REG = INIT_02;
localparam [255:0] INIT_03_REG = INIT_03;
localparam [255:0] INIT_04_REG = INIT_04;
localparam [255:0] INIT_05_REG = INIT_05;
localparam [255:0] INIT_06_REG = INIT_06;
localparam [255:0] INIT_07_REG = INIT_07;
localparam [255:0] INIT_08_REG = INIT_08;
localparam [255:0] INIT_09_REG = INIT_09;
localparam [255:0] INIT_0A_REG = INIT_0A;
localparam [255:0] INIT_0B_REG = INIT_0B;
localparam [255:0] INIT_0C_REG = INIT_0C;
localparam [255:0] INIT_0D_REG = INIT_0D;
localparam [255:0] INIT_0E_REG = INIT_0E;
localparam [255:0] INIT_0F_REG = INIT_0F;
localparam [255:0] INIT_10_REG = INIT_10;
localparam [255:0] INIT_11_REG = INIT_11;
localparam [255:0] INIT_12_REG = INIT_12;
localparam [255:0] INIT_13_REG = INIT_13;
localparam [255:0] INIT_14_REG = INIT_14;
localparam [255:0] INIT_15_REG = INIT_15;
localparam [255:0] INIT_16_REG = INIT_16;
localparam [255:0] INIT_17_REG = INIT_17;
localparam [255:0] INIT_18_REG = INIT_18;
localparam [255:0] INIT_19_REG = INIT_19;
localparam [255:0] INIT_1A_REG = INIT_1A;
localparam [255:0] INIT_1B_REG = INIT_1B;
localparam [255:0] INIT_1C_REG = INIT_1C;
localparam [255:0] INIT_1D_REG = INIT_1D;
localparam [255:0] INIT_1E_REG = INIT_1E;
localparam [255:0] INIT_1F_REG = INIT_1F;
localparam [255:0] INIT_20_REG = INIT_20;
localparam [255:0] INIT_21_REG = INIT_21;
localparam [255:0] INIT_22_REG = INIT_22;
localparam [255:0] INIT_23_REG = INIT_23;
localparam [255:0] INIT_24_REG = INIT_24;
localparam [255:0] INIT_25_REG = INIT_25;
localparam [255:0] INIT_26_REG = INIT_26;
localparam [255:0] INIT_27_REG = INIT_27;
localparam [255:0] INIT_28_REG = INIT_28;
localparam [255:0] INIT_29_REG = INIT_29;
localparam [255:0] INIT_2A_REG = INIT_2A;
localparam [255:0] INIT_2B_REG = INIT_2B;
localparam [255:0] INIT_2C_REG = INIT_2C;
localparam [255:0] INIT_2D_REG = INIT_2D;
localparam [255:0] INIT_2E_REG = INIT_2E;
localparam [255:0] INIT_2F_REG = INIT_2F;
localparam [255:0] INIT_30_REG = INIT_30;
localparam [255:0] INIT_31_REG = INIT_31;
localparam [255:0] INIT_32_REG = INIT_32;
localparam [255:0] INIT_33_REG = INIT_33;
localparam [255:0] INIT_34_REG = INIT_34;
localparam [255:0] INIT_35_REG = INIT_35;
localparam [255:0] INIT_36_REG = INIT_36;
localparam [255:0] INIT_37_REG = INIT_37;
localparam [255:0] INIT_38_REG = INIT_38;
localparam [255:0] INIT_39_REG = INIT_39;
localparam [255:0] INIT_3A_REG = INIT_3A;
localparam [255:0] INIT_3B_REG = INIT_3B;
localparam [255:0] INIT_3C_REG = INIT_3C;
localparam [255:0] INIT_3D_REG = INIT_3D;
localparam [255:0] INIT_3E_REG = INIT_3E;
localparam [255:0] INIT_3F_REG = INIT_3F;
localparam [255:0] INIT_40_REG = INIT_40;
localparam [255:0] INIT_41_REG = INIT_41;
localparam [255:0] INIT_42_REG = INIT_42;
localparam [255:0] INIT_43_REG = INIT_43;
localparam [255:0] INIT_44_REG = INIT_44;
localparam [255:0] INIT_45_REG = INIT_45;
localparam [255:0] INIT_46_REG = INIT_46;
localparam [255:0] INIT_47_REG = INIT_47;
localparam [255:0] INIT_48_REG = INIT_48;
localparam [255:0] INIT_49_REG = INIT_49;
localparam [255:0] INIT_4A_REG = INIT_4A;
localparam [255:0] INIT_4B_REG = INIT_4B;
localparam [255:0] INIT_4C_REG = INIT_4C;
localparam [255:0] INIT_4D_REG = INIT_4D;
localparam [255:0] INIT_4E_REG = INIT_4E;
localparam [255:0] INIT_4F_REG = INIT_4F;
localparam [255:0] INIT_50_REG = INIT_50;
localparam [255:0] INIT_51_REG = INIT_51;
localparam [255:0] INIT_52_REG = INIT_52;
localparam [255:0] INIT_53_REG = INIT_53;
localparam [255:0] INIT_54_REG = INIT_54;
localparam [255:0] INIT_55_REG = INIT_55;
localparam [255:0] INIT_56_REG = INIT_56;
localparam [255:0] INIT_57_REG = INIT_57;
localparam [255:0] INIT_58_REG = INIT_58;
localparam [255:0] INIT_59_REG = INIT_59;
localparam [255:0] INIT_5A_REG = INIT_5A;
localparam [255:0] INIT_5B_REG = INIT_5B;
localparam [255:0] INIT_5C_REG = INIT_5C;
localparam [255:0] INIT_5D_REG = INIT_5D;
localparam [255:0] INIT_5E_REG = INIT_5E;
localparam [255:0] INIT_5F_REG = INIT_5F;
localparam [255:0] INIT_60_REG = INIT_60;
localparam [255:0] INIT_61_REG = INIT_61;
localparam [255:0] INIT_62_REG = INIT_62;
localparam [255:0] INIT_63_REG = INIT_63;
localparam [255:0] INIT_64_REG = INIT_64;
localparam [255:0] INIT_65_REG = INIT_65;
localparam [255:0] INIT_66_REG = INIT_66;
localparam [255:0] INIT_67_REG = INIT_67;
localparam [255:0] INIT_68_REG = INIT_68;
localparam [255:0] INIT_69_REG = INIT_69;
localparam [255:0] INIT_6A_REG = INIT_6A;
localparam [255:0] INIT_6B_REG = INIT_6B;
localparam [255:0] INIT_6C_REG = INIT_6C;
localparam [255:0] INIT_6D_REG = INIT_6D;
localparam [255:0] INIT_6E_REG = INIT_6E;
localparam [255:0] INIT_6F_REG = INIT_6F;
localparam [255:0] INIT_70_REG = INIT_70;
localparam [255:0] INIT_71_REG = INIT_71;
localparam [255:0] INIT_72_REG = INIT_72;
localparam [255:0] INIT_73_REG = INIT_73;
localparam [255:0] INIT_74_REG = INIT_74;
localparam [255:0] INIT_75_REG = INIT_75;
localparam [255:0] INIT_76_REG = INIT_76;
localparam [255:0] INIT_77_REG = INIT_77;
localparam [255:0] INIT_78_REG = INIT_78;
localparam [255:0] INIT_79_REG = INIT_79;
localparam [255:0] INIT_7A_REG = INIT_7A;
localparam [255:0] INIT_7B_REG = INIT_7B;
localparam [255:0] INIT_7C_REG = INIT_7C;
localparam [255:0] INIT_7D_REG = INIT_7D;
localparam [255:0] INIT_7E_REG = INIT_7E;
localparam [255:0] INIT_7F_REG = INIT_7F;
localparam [35:0] INIT_A_REG = INIT_A;
localparam [35:0] INIT_B_REG = INIT_B;
localparam INIT_FILE_REG = INIT_FILE;
localparam [0:0] IS_CLKARDCLK_INVERTED_REG = IS_CLKARDCLK_INVERTED;
localparam [0:0] IS_CLKBWRCLK_INVERTED_REG = IS_CLKBWRCLK_INVERTED;
localparam [0:0] IS_ENARDEN_INVERTED_REG = IS_ENARDEN_INVERTED;
localparam [0:0] IS_ENBWREN_INVERTED_REG = IS_ENBWREN_INVERTED;
localparam [0:0] IS_RSTRAMARSTRAM_INVERTED_REG = IS_RSTRAMARSTRAM_INVERTED;
localparam [0:0] IS_RSTRAMB_INVERTED_REG = IS_RSTRAMB_INVERTED;
localparam [0:0] IS_RSTREGARSTREG_INVERTED_REG = IS_RSTREGARSTREG_INVERTED;
localparam [0:0] IS_RSTREGB_INVERTED_REG = IS_RSTREGB_INVERTED;
localparam [40:1] RDADDRCHANGEA_REG = RDADDRCHANGEA;
localparam [40:1] RDADDRCHANGEB_REG = RDADDRCHANGEB;
localparam [6:0] READ_WIDTH_A_REG = READ_WIDTH_A;
localparam [5:0] READ_WIDTH_B_REG = READ_WIDTH_B;
localparam [48:1] RSTREG_PRIORITY_A_REG = RSTREG_PRIORITY_A;
localparam [48:1] RSTREG_PRIORITY_B_REG = RSTREG_PRIORITY_B;
localparam [120:1] SIM_COLLISION_CHECK_REG = SIM_COLLISION_CHECK;
localparam [40:1] SLEEP_ASYNC_REG = SLEEP_ASYNC;
localparam [35:0] SRVAL_A_REG = SRVAL_A;
localparam [35:0] SRVAL_B_REG = SRVAL_B;
localparam [88:1] WRITE_MODE_A_REG = WRITE_MODE_A;
localparam [88:1] WRITE_MODE_B_REG = WRITE_MODE_B;
localparam [5:0] WRITE_WIDTH_A_REG = WRITE_WIDTH_A;
localparam [6:0] WRITE_WIDTH_B_REG = WRITE_WIDTH_B;
`endif
wire [1:0] CASCADE_ORDER_A_BIN;
wire [1:0] CASCADE_ORDER_B_BIN;
wire CLOCK_DOMAINS_BIN;
wire DOA_REG_BIN;
wire DOB_REG_BIN;
wire ENADDRENA_BIN;
wire ENADDRENB_BIN;
wire EN_ECC_PIPE_BIN;
wire EN_ECC_READ_BIN;
wire EN_ECC_WRITE_BIN;
wire [255:0] INITP_BIN [0:15];
wire [255:0] INIT_BIN [0:127];
wire [35:0] INIT_A_BIN;
wire [35:0] INIT_B_BIN;
wire IS_CLKARDCLK_INVERTED_BIN;
wire IS_CLKBWRCLK_INVERTED_BIN;
wire IS_ENARDEN_INVERTED_BIN;
wire IS_ENBWREN_INVERTED_BIN;
wire IS_RSTRAMARSTRAM_INVERTED_BIN;
wire IS_RSTRAMB_INVERTED_BIN;
wire IS_RSTREGARSTREG_INVERTED_BIN;
wire IS_RSTREGB_INVERTED_BIN;
wire RDADDRCHANGEA_BIN;
wire RDADDRCHANGEB_BIN;
wire [6:0] READ_WIDTH_A_BIN;
wire [6:0] READ_WIDTH_B_BIN;
wire RSTREG_PRIORITY_A_BIN;
wire RSTREG_PRIORITY_B_BIN;
wire [1:0] SIM_COLLISION_CHECK_BIN;
wire SLEEP_ASYNC_BIN;
wire [35:0] SRVAL_A_BIN;
wire [35:0] SRVAL_B_BIN;
wire [1:0] WRITE_MODE_A_BIN;
wire [1:0] WRITE_MODE_B_BIN;
wire [6:0] WRITE_WIDTH_A_BIN;
wire [6:0] WRITE_WIDTH_B_BIN;
`ifdef XIL_ATTR_TEST
reg attr_test = 1'b1;
`else
reg attr_test = 1'b0;
`endif
reg attr_err = 1'b0;
tri0 glblGSR = glbl.GSR || trig_attr;
wire CASOUTDBITERR_out;
wire CASOUTSBITERR_out;
reg DBITERR_out;
reg SBITERR_out;
wire [31:0] CASDOUTA_out;
wire [31:0] CASDOUTB_out;
reg [31:0] DOUTADOUT_out;
reg [31:0] DOUTBDOUT_out;
wire [3:0] CASDOUTPA_out;
wire [3:0] CASDOUTPB_out;
reg [3:0] DOUTPADOUTP_out;
reg [3:0] DOUTPBDOUTP_out;
wire [7:0] ECCPARITY_out;
wire [8:0] RDADDRECC_out;
wire ADDRENA_in;
wire ADDRENB_in;
wire CASDIMUXA_in;
wire CASDIMUXB_in;
wire CASDOMUXA_in;
wire CASDOMUXB_in;
wire CASDOMUXEN_A_in;
wire CASDOMUXEN_B_in;
wire CASINDBITERR_in;
wire CASINSBITERR_in;
wire CASOREGIMUXA_in;
wire CASOREGIMUXB_in;
wire CASOREGIMUXEN_A_in;
wire CASOREGIMUXEN_B_in;
wire CLKARDCLK_in;
wire CLKBWRCLK_in;
wire ECCPIPECE_in;
wire ENARDEN_in;
wire ENBWREN_in;
wire INJECTDBITERR_in;
wire INJECTSBITERR_in;
wire REGCEAREGCE_in;
wire REGCEB_in;
wire RSTRAMARSTRAM_in;
wire RSTRAMB_in;
wire RSTREGARSTREG_in;
wire RSTREGB_in;
wire SLEEP_in;
reg [14:0] ADDRARDADDR_in;
reg [14:0] ADDRBWRADDR_in;
wire [31:0] CASDINA_in;
wire [31:0] CASDINB_in;
reg [31:0] DINADIN_in;
reg [31:0] DINBDIN_in;
wire [3:0] CASDINPA_in;
wire [3:0] CASDINPB_in;
reg [3:0] DINPADINP_in;
reg [3:0] DINPBDINP_in;
wire [3:0] WEA_in;
wire [7:0] WEBWE_in;
`ifdef XIL_TIMING
wire ADDRENA_delay;
wire ADDRENB_delay;
wire CASDIMUXA_delay;
wire CASDIMUXB_delay;
wire CASDOMUXA_delay;
wire CASDOMUXB_delay;
wire CASDOMUXEN_A_delay;
wire CASDOMUXEN_B_delay;
wire CASINDBITERR_delay;
wire CASINSBITERR_delay;
wire CASOREGIMUXA_delay;
wire CASOREGIMUXB_delay;
wire CASOREGIMUXEN_A_delay;
wire CASOREGIMUXEN_B_delay;
wire CLKARDCLK_delay;
wire CLKBWRCLK_delay;
wire ECCPIPECE_delay;
wire ENARDEN_delay;
wire ENBWREN_delay;
wire INJECTDBITERR_delay;
wire INJECTSBITERR_delay;
wire REGCEAREGCE_delay;
wire REGCEB_delay;
wire RSTRAMARSTRAM_delay;
wire RSTRAMB_delay;
wire RSTREGARSTREG_delay;
wire RSTREGB_delay;
wire SLEEP_delay;
wire [14:0] ADDRARDADDR_delay;
wire [14:0] ADDRBWRADDR_delay;
wire [31:0] CASDINA_delay;
wire [31:0] CASDINB_delay;
wire [31:0] DINADIN_delay;
wire [31:0] DINBDIN_delay;
wire [3:0] CASDINPA_delay;
wire [3:0] CASDINPB_delay;
wire [3:0] DINPADINP_delay;
wire [3:0] DINPBDINP_delay;
wire [3:0] WEA_delay;
wire [7:0] WEBWE_delay;
`endif
assign CASDOUTA = CASDOUTA_out;
assign CASDOUTB = CASDOUTB_out;
assign CASDOUTPA = CASDOUTPA_out;
assign CASDOUTPB = CASDOUTPB_out;
assign CASOUTDBITERR = CASOUTDBITERR_out;
assign CASOUTSBITERR = CASOUTSBITERR_out;
assign DBITERR = DBITERR_out;
assign DOUTADOUT = DOUTADOUT_out;
assign DOUTBDOUT = DOUTBDOUT_out;
assign DOUTPADOUTP = DOUTPADOUTP_out;
assign DOUTPBDOUTP = DOUTPBDOUTP_out;
assign ECCPARITY = ECCPARITY_out;
assign RDADDRECC = RDADDRECC_out;
assign SBITERR = SBITERR_out;
`ifdef XIL_TIMING
reg notifier;
`endif
`ifdef XIL_TIMING
always @ (*) ADDRARDADDR_in = ADDRARDADDR_delay;
always @ (*) ADDRBWRADDR_in = ADDRBWRADDR_delay;
assign ADDRENA_in = (ADDRENA === 1'bz) || ADDRENA_delay; // rv 1
assign ADDRENB_in = (ADDRENB === 1'bz) || ADDRENB_delay; // rv 1
assign CASDIMUXA_in = (CASDIMUXA !== 1'bz) && CASDIMUXA_delay; // rv 0
assign CASDIMUXB_in = (CASDIMUXB !== 1'bz) && CASDIMUXB_delay; // rv 0
assign CASDINA_in[0] = (CASDINA[0] !== 1'bz) && CASDINA_delay[0]; // rv 0
assign CASDINA_in[10] = (CASDINA[10] !== 1'bz) && CASDINA_delay[10]; // rv 0
assign CASDINA_in[11] = (CASDINA[11] !== 1'bz) && CASDINA_delay[11]; // rv 0
assign CASDINA_in[12] = (CASDINA[12] !== 1'bz) && CASDINA_delay[12]; // rv 0
assign CASDINA_in[13] = (CASDINA[13] !== 1'bz) && CASDINA_delay[13]; // rv 0
assign CASDINA_in[14] = (CASDINA[14] !== 1'bz) && CASDINA_delay[14]; // rv 0
assign CASDINA_in[15] = (CASDINA[15] !== 1'bz) && CASDINA_delay[15]; // rv 0
assign CASDINA_in[16] = (CASDINA[16] !== 1'bz) && CASDINA_delay[16]; // rv 0
assign CASDINA_in[17] = (CASDINA[17] !== 1'bz) && CASDINA_delay[17]; // rv 0
assign CASDINA_in[18] = (CASDINA[18] !== 1'bz) && CASDINA_delay[18]; // rv 0
assign CASDINA_in[19] = (CASDINA[19] !== 1'bz) && CASDINA_delay[19]; // rv 0
assign CASDINA_in[1] = (CASDINA[1] !== 1'bz) && CASDINA_delay[1]; // rv 0
assign CASDINA_in[20] = (CASDINA[20] !== 1'bz) && CASDINA_delay[20]; // rv 0
assign CASDINA_in[21] = (CASDINA[21] !== 1'bz) && CASDINA_delay[21]; // rv 0
assign CASDINA_in[22] = (CASDINA[22] !== 1'bz) && CASDINA_delay[22]; // rv 0
assign CASDINA_in[23] = (CASDINA[23] !== 1'bz) && CASDINA_delay[23]; // rv 0
assign CASDINA_in[24] = (CASDINA[24] !== 1'bz) && CASDINA_delay[24]; // rv 0
assign CASDINA_in[25] = (CASDINA[25] !== 1'bz) && CASDINA_delay[25]; // rv 0
assign CASDINA_in[26] = (CASDINA[26] !== 1'bz) && CASDINA_delay[26]; // rv 0
assign CASDINA_in[27] = (CASDINA[27] !== 1'bz) && CASDINA_delay[27]; // rv 0
assign CASDINA_in[28] = (CASDINA[28] !== 1'bz) && CASDINA_delay[28]; // rv 0
assign CASDINA_in[29] = (CASDINA[29] !== 1'bz) && CASDINA_delay[29]; // rv 0
assign CASDINA_in[2] = (CASDINA[2] !== 1'bz) && CASDINA_delay[2]; // rv 0
assign CASDINA_in[30] = (CASDINA[30] !== 1'bz) && CASDINA_delay[30]; // rv 0
assign CASDINA_in[31] = (CASDINA[31] !== 1'bz) && CASDINA_delay[31]; // rv 0
assign CASDINA_in[3] = (CASDINA[3] !== 1'bz) && CASDINA_delay[3]; // rv 0
assign CASDINA_in[4] = (CASDINA[4] !== 1'bz) && CASDINA_delay[4]; // rv 0
assign CASDINA_in[5] = (CASDINA[5] !== 1'bz) && CASDINA_delay[5]; // rv 0
assign CASDINA_in[6] = (CASDINA[6] !== 1'bz) && CASDINA_delay[6]; // rv 0
assign CASDINA_in[7] = (CASDINA[7] !== 1'bz) && CASDINA_delay[7]; // rv 0
assign CASDINA_in[8] = (CASDINA[8] !== 1'bz) && CASDINA_delay[8]; // rv 0
assign CASDINA_in[9] = (CASDINA[9] !== 1'bz) && CASDINA_delay[9]; // rv 0
assign CASDINB_in[0] = (CASDINB[0] !== 1'bz) && CASDINB_delay[0]; // rv 0
assign CASDINB_in[10] = (CASDINB[10] !== 1'bz) && CASDINB_delay[10]; // rv 0
assign CASDINB_in[11] = (CASDINB[11] !== 1'bz) && CASDINB_delay[11]; // rv 0
assign CASDINB_in[12] = (CASDINB[12] !== 1'bz) && CASDINB_delay[12]; // rv 0
assign CASDINB_in[13] = (CASDINB[13] !== 1'bz) && CASDINB_delay[13]; // rv 0
assign CASDINB_in[14] = (CASDINB[14] !== 1'bz) && CASDINB_delay[14]; // rv 0
assign CASDINB_in[15] = (CASDINB[15] !== 1'bz) && CASDINB_delay[15]; // rv 0
assign CASDINB_in[16] = (CASDINB[16] !== 1'bz) && CASDINB_delay[16]; // rv 0
assign CASDINB_in[17] = (CASDINB[17] !== 1'bz) && CASDINB_delay[17]; // rv 0
assign CASDINB_in[18] = (CASDINB[18] !== 1'bz) && CASDINB_delay[18]; // rv 0
assign CASDINB_in[19] = (CASDINB[19] !== 1'bz) && CASDINB_delay[19]; // rv 0
assign CASDINB_in[1] = (CASDINB[1] !== 1'bz) && CASDINB_delay[1]; // rv 0
assign CASDINB_in[20] = (CASDINB[20] !== 1'bz) && CASDINB_delay[20]; // rv 0
assign CASDINB_in[21] = (CASDINB[21] !== 1'bz) && CASDINB_delay[21]; // rv 0
assign CASDINB_in[22] = (CASDINB[22] !== 1'bz) && CASDINB_delay[22]; // rv 0
assign CASDINB_in[23] = (CASDINB[23] !== 1'bz) && CASDINB_delay[23]; // rv 0
assign CASDINB_in[24] = (CASDINB[24] !== 1'bz) && CASDINB_delay[24]; // rv 0
assign CASDINB_in[25] = (CASDINB[25] !== 1'bz) && CASDINB_delay[25]; // rv 0
assign CASDINB_in[26] = (CASDINB[26] !== 1'bz) && CASDINB_delay[26]; // rv 0
assign CASDINB_in[27] = (CASDINB[27] !== 1'bz) && CASDINB_delay[27]; // rv 0
assign CASDINB_in[28] = (CASDINB[28] !== 1'bz) && CASDINB_delay[28]; // rv 0
assign CASDINB_in[29] = (CASDINB[29] !== 1'bz) && CASDINB_delay[29]; // rv 0
assign CASDINB_in[2] = (CASDINB[2] !== 1'bz) && CASDINB_delay[2]; // rv 0
assign CASDINB_in[30] = (CASDINB[30] !== 1'bz) && CASDINB_delay[30]; // rv 0
assign CASDINB_in[31] = (CASDINB[31] !== 1'bz) && CASDINB_delay[31]; // rv 0
assign CASDINB_in[3] = (CASDINB[3] !== 1'bz) && CASDINB_delay[3]; // rv 0
assign CASDINB_in[4] = (CASDINB[4] !== 1'bz) && CASDINB_delay[4]; // rv 0
assign CASDINB_in[5] = (CASDINB[5] !== 1'bz) && CASDINB_delay[5]; // rv 0
assign CASDINB_in[6] = (CASDINB[6] !== 1'bz) && CASDINB_delay[6]; // rv 0
assign CASDINB_in[7] = (CASDINB[7] !== 1'bz) && CASDINB_delay[7]; // rv 0
assign CASDINB_in[8] = (CASDINB[8] !== 1'bz) && CASDINB_delay[8]; // rv 0
assign CASDINB_in[9] = (CASDINB[9] !== 1'bz) && CASDINB_delay[9]; // rv 0
assign CASDINPA_in[0] = (CASDINPA[0] !== 1'bz) && CASDINPA_delay[0]; // rv 0
assign CASDINPA_in[1] = (CASDINPA[1] !== 1'bz) && CASDINPA_delay[1]; // rv 0
assign CASDINPA_in[2] = (CASDINPA[2] !== 1'bz) && CASDINPA_delay[2]; // rv 0
assign CASDINPA_in[3] = (CASDINPA[3] !== 1'bz) && CASDINPA_delay[3]; // rv 0
assign CASDINPB_in[0] = (CASDINPB[0] !== 1'bz) && CASDINPB_delay[0]; // rv 0
assign CASDINPB_in[1] = (CASDINPB[1] !== 1'bz) && CASDINPB_delay[1]; // rv 0
assign CASDINPB_in[2] = (CASDINPB[2] !== 1'bz) && CASDINPB_delay[2]; // rv 0
assign CASDINPB_in[3] = (CASDINPB[3] !== 1'bz) && CASDINPB_delay[3]; // rv 0
assign CASDOMUXA_in = (CASDOMUXA !== 1'bz) && CASDOMUXA_delay; // rv 0
assign CASDOMUXB_in = (CASDOMUXB !== 1'bz) && CASDOMUXB_delay; // rv 0
assign CASDOMUXEN_A_in = (CASDOMUXEN_A === 1'bz) || CASDOMUXEN_A_delay; // rv 1
assign CASDOMUXEN_B_in = (CASDOMUXEN_B === 1'bz) || CASDOMUXEN_B_delay; // rv 1
assign CASINDBITERR_in = (CASINDBITERR !== 1'bz) && CASINDBITERR_delay; // rv 0
assign CASINSBITERR_in = (CASINSBITERR !== 1'bz) && CASINSBITERR_delay; // rv 0
assign CASOREGIMUXA_in = (CASOREGIMUXA !== 1'bz) && CASOREGIMUXA_delay; // rv 0
assign CASOREGIMUXB_in = (CASOREGIMUXB !== 1'bz) && CASOREGIMUXB_delay; // rv 0
assign CASOREGIMUXEN_A_in = (CASOREGIMUXEN_A === 1'bz) || CASOREGIMUXEN_A_delay; // rv 1
assign CASOREGIMUXEN_B_in = (CASOREGIMUXEN_B === 1'bz) || CASOREGIMUXEN_B_delay; // rv 1
assign CLKARDCLK_in = (CLKARDCLK !== 1'bz) && (CLKARDCLK_delay ^ IS_CLKARDCLK_INVERTED_BIN); // rv 0
assign CLKBWRCLK_in = (CLKBWRCLK !== 1'bz) && (CLKBWRCLK_delay ^ IS_CLKBWRCLK_INVERTED_BIN); // rv 0
always @ (*) DINADIN_in = DINADIN_delay;
always @ (*) DINBDIN_in = DINBDIN_delay;
always @ (*) DINPADINP_in = DINPADINP_delay;
always @ (*) DINPBDINP_in = DINPBDINP_delay;
assign ECCPIPECE_in = (ECCPIPECE === 1'bz) || ECCPIPECE_delay; // rv 1
assign ENARDEN_in = (ENARDEN !== 1'bz) && (ENARDEN_delay ^ IS_ENARDEN_INVERTED_BIN); // rv 0
assign ENBWREN_in = (ENBWREN !== 1'bz) && (ENBWREN_delay ^ IS_ENBWREN_INVERTED_BIN); // rv 0
assign INJECTDBITERR_in = (INJECTDBITERR !== 1'bz) && INJECTDBITERR_delay; // rv 0
assign INJECTSBITERR_in = (INJECTSBITERR !== 1'bz) && INJECTSBITERR_delay; // rv 0
assign REGCEAREGCE_in = (REGCEAREGCE === 1'bz) || REGCEAREGCE_delay; // rv 1
assign REGCEB_in = (REGCEB === 1'bz) || REGCEB_delay; // rv 1
assign RSTRAMARSTRAM_in = (RSTRAMARSTRAM !== 1'bz) && (RSTRAMARSTRAM_delay ^ IS_RSTRAMARSTRAM_INVERTED_BIN); // rv 0
assign RSTRAMB_in = (RSTRAMB !== 1'bz) && (RSTRAMB_delay ^ IS_RSTRAMB_INVERTED_BIN); // rv 0
assign RSTREGARSTREG_in = (RSTREGARSTREG !== 1'bz) && (RSTREGARSTREG_delay ^ IS_RSTREGARSTREG_INVERTED_BIN); // rv 0
assign RSTREGB_in = (RSTREGB !== 1'bz) && (RSTREGB_delay ^ IS_RSTREGB_INVERTED_BIN); // rv 0
assign SLEEP_in = (SLEEP !== 1'bz) && SLEEP_delay; // rv 0
assign WEA_in[0] = (WEA[0] === 1'bz) || WEA_delay[0]; // rv 1
assign WEA_in[1] = (WEA[1] === 1'bz) || WEA_delay[1]; // rv 1
assign WEA_in[2] = (WEA[2] === 1'bz) || WEA_delay[2]; // rv 1
assign WEA_in[3] = (WEA[3] === 1'bz) || WEA_delay[3]; // rv 1
assign WEBWE_in = WEBWE_delay;
`else
always @ (*) ADDRARDADDR_in = ADDRARDADDR;
always @ (*) ADDRBWRADDR_in = ADDRBWRADDR;
assign ADDRENA_in = (ADDRENA === 1'bz) || ADDRENA; // rv 1
assign ADDRENB_in = (ADDRENB === 1'bz) || ADDRENB; // rv 1
assign CASDIMUXA_in = (CASDIMUXA !== 1'bz) && CASDIMUXA; // rv 0
assign CASDIMUXB_in = (CASDIMUXB !== 1'bz) && CASDIMUXB; // rv 0
assign CASDINA_in[0] = (CASDINA[0] !== 1'bz) && CASDINA[0]; // rv 0
assign CASDINA_in[10] = (CASDINA[10] !== 1'bz) && CASDINA[10]; // rv 0
assign CASDINA_in[11] = (CASDINA[11] !== 1'bz) && CASDINA[11]; // rv 0
assign CASDINA_in[12] = (CASDINA[12] !== 1'bz) && CASDINA[12]; // rv 0
assign CASDINA_in[13] = (CASDINA[13] !== 1'bz) && CASDINA[13]; // rv 0
assign CASDINA_in[14] = (CASDINA[14] !== 1'bz) && CASDINA[14]; // rv 0
assign CASDINA_in[15] = (CASDINA[15] !== 1'bz) && CASDINA[15]; // rv 0
assign CASDINA_in[16] = (CASDINA[16] !== 1'bz) && CASDINA[16]; // rv 0
assign CASDINA_in[17] = (CASDINA[17] !== 1'bz) && CASDINA[17]; // rv 0
assign CASDINA_in[18] = (CASDINA[18] !== 1'bz) && CASDINA[18]; // rv 0
assign CASDINA_in[19] = (CASDINA[19] !== 1'bz) && CASDINA[19]; // rv 0
assign CASDINA_in[1] = (CASDINA[1] !== 1'bz) && CASDINA[1]; // rv 0
assign CASDINA_in[20] = (CASDINA[20] !== 1'bz) && CASDINA[20]; // rv 0
assign CASDINA_in[21] = (CASDINA[21] !== 1'bz) && CASDINA[21]; // rv 0
assign CASDINA_in[22] = (CASDINA[22] !== 1'bz) && CASDINA[22]; // rv 0
assign CASDINA_in[23] = (CASDINA[23] !== 1'bz) && CASDINA[23]; // rv 0
assign CASDINA_in[24] = (CASDINA[24] !== 1'bz) && CASDINA[24]; // rv 0
assign CASDINA_in[25] = (CASDINA[25] !== 1'bz) && CASDINA[25]; // rv 0
assign CASDINA_in[26] = (CASDINA[26] !== 1'bz) && CASDINA[26]; // rv 0
assign CASDINA_in[27] = (CASDINA[27] !== 1'bz) && CASDINA[27]; // rv 0
assign CASDINA_in[28] = (CASDINA[28] !== 1'bz) && CASDINA[28]; // rv 0
assign CASDINA_in[29] = (CASDINA[29] !== 1'bz) && CASDINA[29]; // rv 0
assign CASDINA_in[2] = (CASDINA[2] !== 1'bz) && CASDINA[2]; // rv 0
assign CASDINA_in[30] = (CASDINA[30] !== 1'bz) && CASDINA[30]; // rv 0
assign CASDINA_in[31] = (CASDINA[31] !== 1'bz) && CASDINA[31]; // rv 0
assign CASDINA_in[3] = (CASDINA[3] !== 1'bz) && CASDINA[3]; // rv 0
assign CASDINA_in[4] = (CASDINA[4] !== 1'bz) && CASDINA[4]; // rv 0
assign CASDINA_in[5] = (CASDINA[5] !== 1'bz) && CASDINA[5]; // rv 0
assign CASDINA_in[6] = (CASDINA[6] !== 1'bz) && CASDINA[6]; // rv 0
assign CASDINA_in[7] = (CASDINA[7] !== 1'bz) && CASDINA[7]; // rv 0
assign CASDINA_in[8] = (CASDINA[8] !== 1'bz) && CASDINA[8]; // rv 0
assign CASDINA_in[9] = (CASDINA[9] !== 1'bz) && CASDINA[9]; // rv 0
assign CASDINB_in[0] = (CASDINB[0] !== 1'bz) && CASDINB[0]; // rv 0
assign CASDINB_in[10] = (CASDINB[10] !== 1'bz) && CASDINB[10]; // rv 0
assign CASDINB_in[11] = (CASDINB[11] !== 1'bz) && CASDINB[11]; // rv 0
assign CASDINB_in[12] = (CASDINB[12] !== 1'bz) && CASDINB[12]; // rv 0
assign CASDINB_in[13] = (CASDINB[13] !== 1'bz) && CASDINB[13]; // rv 0
assign CASDINB_in[14] = (CASDINB[14] !== 1'bz) && CASDINB[14]; // rv 0
assign CASDINB_in[15] = (CASDINB[15] !== 1'bz) && CASDINB[15]; // rv 0
assign CASDINB_in[16] = (CASDINB[16] !== 1'bz) && CASDINB[16]; // rv 0
assign CASDINB_in[17] = (CASDINB[17] !== 1'bz) && CASDINB[17]; // rv 0
assign CASDINB_in[18] = (CASDINB[18] !== 1'bz) && CASDINB[18]; // rv 0
assign CASDINB_in[19] = (CASDINB[19] !== 1'bz) && CASDINB[19]; // rv 0
assign CASDINB_in[1] = (CASDINB[1] !== 1'bz) && CASDINB[1]; // rv 0
assign CASDINB_in[20] = (CASDINB[20] !== 1'bz) && CASDINB[20]; // rv 0
assign CASDINB_in[21] = (CASDINB[21] !== 1'bz) && CASDINB[21]; // rv 0
assign CASDINB_in[22] = (CASDINB[22] !== 1'bz) && CASDINB[22]; // rv 0
assign CASDINB_in[23] = (CASDINB[23] !== 1'bz) && CASDINB[23]; // rv 0
assign CASDINB_in[24] = (CASDINB[24] !== 1'bz) && CASDINB[24]; // rv 0
assign CASDINB_in[25] = (CASDINB[25] !== 1'bz) && CASDINB[25]; // rv 0
assign CASDINB_in[26] = (CASDINB[26] !== 1'bz) && CASDINB[26]; // rv 0
assign CASDINB_in[27] = (CASDINB[27] !== 1'bz) && CASDINB[27]; // rv 0
assign CASDINB_in[28] = (CASDINB[28] !== 1'bz) && CASDINB[28]; // rv 0
assign CASDINB_in[29] = (CASDINB[29] !== 1'bz) && CASDINB[29]; // rv 0
assign CASDINB_in[2] = (CASDINB[2] !== 1'bz) && CASDINB[2]; // rv 0
assign CASDINB_in[30] = (CASDINB[30] !== 1'bz) && CASDINB[30]; // rv 0
assign CASDINB_in[31] = (CASDINB[31] !== 1'bz) && CASDINB[31]; // rv 0
assign CASDINB_in[3] = (CASDINB[3] !== 1'bz) && CASDINB[3]; // rv 0
assign CASDINB_in[4] = (CASDINB[4] !== 1'bz) && CASDINB[4]; // rv 0
assign CASDINB_in[5] = (CASDINB[5] !== 1'bz) && CASDINB[5]; // rv 0
assign CASDINB_in[6] = (CASDINB[6] !== 1'bz) && CASDINB[6]; // rv 0
assign CASDINB_in[7] = (CASDINB[7] !== 1'bz) && CASDINB[7]; // rv 0
assign CASDINB_in[8] = (CASDINB[8] !== 1'bz) && CASDINB[8]; // rv 0
assign CASDINB_in[9] = (CASDINB[9] !== 1'bz) && CASDINB[9]; // rv 0
assign CASDINPA_in[0] = (CASDINPA[0] !== 1'bz) && CASDINPA[0]; // rv 0
assign CASDINPA_in[1] = (CASDINPA[1] !== 1'bz) && CASDINPA[1]; // rv 0
assign CASDINPA_in[2] = (CASDINPA[2] !== 1'bz) && CASDINPA[2]; // rv 0
assign CASDINPA_in[3] = (CASDINPA[3] !== 1'bz) && CASDINPA[3]; // rv 0
assign CASDINPB_in[0] = (CASDINPB[0] !== 1'bz) && CASDINPB[0]; // rv 0
assign CASDINPB_in[1] = (CASDINPB[1] !== 1'bz) && CASDINPB[1]; // rv 0
assign CASDINPB_in[2] = (CASDINPB[2] !== 1'bz) && CASDINPB[2]; // rv 0
assign CASDINPB_in[3] = (CASDINPB[3] !== 1'bz) && CASDINPB[3]; // rv 0
assign CASDOMUXA_in = (CASDOMUXA !== 1'bz) && CASDOMUXA; // rv 0
assign CASDOMUXB_in = (CASDOMUXB !== 1'bz) && CASDOMUXB; // rv 0
assign CASDOMUXEN_A_in = (CASDOMUXEN_A === 1'bz) || CASDOMUXEN_A; // rv 1
assign CASDOMUXEN_B_in = (CASDOMUXEN_B === 1'bz) || CASDOMUXEN_B; // rv 1
assign CASINDBITERR_in = (CASINDBITERR !== 1'bz) && CASINDBITERR; // rv 0
assign CASINSBITERR_in = (CASINSBITERR !== 1'bz) && CASINSBITERR; // rv 0
assign CASOREGIMUXA_in = (CASOREGIMUXA !== 1'bz) && CASOREGIMUXA; // rv 0
assign CASOREGIMUXB_in = (CASOREGIMUXB !== 1'bz) && CASOREGIMUXB; // rv 0
assign CASOREGIMUXEN_A_in = (CASOREGIMUXEN_A === 1'bz) || CASOREGIMUXEN_A; // rv 1
assign CASOREGIMUXEN_B_in = (CASOREGIMUXEN_B === 1'bz) || CASOREGIMUXEN_B; // rv 1
assign CLKARDCLK_in = (CLKARDCLK !== 1'bz) && (CLKARDCLK ^ IS_CLKARDCLK_INVERTED_BIN); // rv 0
assign CLKBWRCLK_in = (CLKBWRCLK !== 1'bz) && (CLKBWRCLK ^ IS_CLKBWRCLK_INVERTED_BIN); // rv 0
// always @ (CLKARDCLK) begin
// if ((CLKARDCLK === 1'bz) || // rv 0
// (CLKARDCLK === IS_CLKARDCLK_INVERTED_BIN)) CLKARDCLK_in = 1'b0;
// else CLKARDCLK_in = 1'b1;
// end
// always @ (CLKBWRCLK) begin
// if ((CLKBWRCLK === 1'bz) || // rv 0
// (CLKBWRCLK === IS_CLKBWRCLK_INVERTED_BIN)) CLKBWRCLK_in = 1'b0;
// else CLKBWRCLK_in = 1'b1;
// end
always @ (*) DINADIN_in = DINADIN;
always @ (*) DINBDIN_in = DINBDIN;
always @ (*) DINPADINP_in = DINPADINP;
always @ (*) DINPBDINP_in = DINPBDINP;
assign ECCPIPECE_in = (ECCPIPECE === 1'bz) || ECCPIPECE; // rv 1
assign ENARDEN_in = (ENARDEN !== 1'bz) && (ENARDEN ^ IS_ENARDEN_INVERTED_BIN); // rv 0
assign ENBWREN_in = (ENBWREN !== 1'bz) && (ENBWREN ^ IS_ENBWREN_INVERTED_BIN); // rv 0
assign INJECTDBITERR_in = (INJECTDBITERR !== 1'bz) && INJECTDBITERR; // rv 0
assign INJECTSBITERR_in = (INJECTSBITERR !== 1'bz) && INJECTSBITERR; // rv 0
assign REGCEAREGCE_in = (REGCEAREGCE === 1'bz) || REGCEAREGCE; // rv 1
assign REGCEB_in = (REGCEB === 1'bz) || REGCEB; // rv 1
assign RSTRAMARSTRAM_in = (RSTRAMARSTRAM !== 1'bz) && (RSTRAMARSTRAM ^ IS_RSTRAMARSTRAM_INVERTED_BIN); // rv 0
assign RSTRAMB_in = (RSTRAMB !== 1'bz) && (RSTRAMB ^ IS_RSTRAMB_INVERTED_BIN); // rv 0
assign RSTREGARSTREG_in = (RSTREGARSTREG !== 1'bz) && (RSTREGARSTREG ^ IS_RSTREGARSTREG_INVERTED_BIN); // rv 0
assign RSTREGB_in = (RSTREGB !== 1'bz) && (RSTREGB ^ IS_RSTREGB_INVERTED_BIN); // rv 0
assign SLEEP_in = (SLEEP !== 1'bz) && SLEEP; // rv 0
assign WEA_in[0] = (WEA[0] === 1'bz) || WEA[0]; // rv 1
assign WEA_in[1] = (WEA[1] === 1'bz) || WEA[1]; // rv 1
assign WEA_in[2] = (WEA[2] === 1'bz) || WEA[2]; // rv 1
assign WEA_in[3] = (WEA[3] === 1'bz) || WEA[3]; // rv 1
assign WEBWE_in = WEBWE;
`endif
// internal variables, signals, busses
localparam integer ADDR_WIDTH = 15;
localparam integer INIT_WIDTH = 72;
localparam integer D_WIDTH = 64;
localparam integer DP_WIDTH = 8;
localparam mem_width = 1;
localparam memp_width = 1;
localparam mem_depth = 32768+64;
localparam memp_depth = 4096+8;
localparam encode = 1'b1;
localparam decode = 1'b0;
integer t_coll_min = 50;
integer t_coll_max = 3000 - 49;
reg [255:0] INITP_TMP;
reg [255:0] INIT_TMP;
integer i=0;
integer j=0;
integer k=0;
integer ra=0;
integer raa=0;
integer raw=0;
integer wb=0;
integer rb=0;
integer rbb=0;
integer rbw=0;
integer wa=0;
integer rd_loops_a = 1;
integer wr_loops_a = 1;
integer rd_loops_b = 1;
integer rd_loops_f = 1;
integer wr_loops_b = 1;
localparam max_rd_loops = D_WIDTH;
localparam max_wr_loops = D_WIDTH;
reg INIT_MEM = 0;
wire WREN_ecc;
wire SLEEP_int;
reg SLEEP_reg = 1'b0;
reg SLEEP_reg1 = 1'b0;
wire RSTREG_A_int;
wire REGCE_A_int;
wire ADDRENA_int;
wire ADDRENB_int;
wire RSTREG_B_int;
wire REGCE_B_int;
reg CASDOMUXA_reg = 1'b0;
reg CASOREGIMUXA_reg = 1'b0;
reg CASDOMUXB_reg = 1'b0;
reg CASOREGIMUXB_reg = 1'b0;
wire CASDOMUXB_int;
wire INJECTDBITERR_int;
wire INJECTSBITERR_int;
reg [6:0] error_bit = 7'b0;
reg [DP_WIDTH-1:0] eccparity_reg = 8'h00;
wire [INIT_WIDTH-1:0] INIT_A_int;
wire [INIT_WIDTH-1:0] SRVAL_A_int;
wire [INIT_WIDTH/2-1:0] INIT_B_int;
wire [INIT_WIDTH/2-1:0] SRVAL_B_int;
wire mem_wr_en_a;
reg mem_wr_en_a_wf = 1'b0;
reg [D_WIDTH/2-1:0] mem_we_a;
reg [DP_WIDTH/2-1:0] memp_we_a;
wire [D_WIDTH/2-1:0] mem_rm_doutb;
wire [DP_WIDTH/2-1:0] memp_rm_doutb;
wire [D_WIDTH-1:0] mem_rm_a;
wire [D_WIDTH-1:0] mem_rm_b;
wire [D_WIDTH-1:0] mem_wm_a;
wire [D_WIDTH-1:0] mem_wm_b;
reg wr_data_matches = 0;
reg wr_a_data_matches_rd_b_data = 0;
reg wr_b_data_matches_rd_a_data = 0;
wire mem_wr_en_b;
reg mem_wr_en_b_wf = 1'b0;
reg [D_WIDTH-1:0] mem_we_b;
reg [DP_WIDTH-1:0] memp_we_b;
wire [D_WIDTH-1:0] mem_rm_douta;
wire [DP_WIDTH-1:0] memp_rm_douta;
wire mem_rd_en_a;
wire mem_rst_a;
reg first_read = 1'b0;
wire mem_rd_en_b;
wire mem_rst_b;
reg mem [0 : mem_depth-1];
reg [D_WIDTH/2-1 : 0] mem_wr_a;
reg wr_a_event = 1'b0;
reg wr_a_wf_event = 1'b0;
reg [D_WIDTH-1 : 0] ram_rd_a;
reg [D_WIDTH-1 : 0] mem_rd_a_wf;
reg [D_WIDTH-1 : 0] mem_wr_b;
reg wr_b_event = 1'b0;
reg wr_b_wf_event = 1'b0;
reg [D_WIDTH-1 : 0] mem_rd_b;
reg [D_WIDTH-1 : 0] mem_rd_b_rf;
reg [D_WIDTH-1 : 0] mem_rd_b_wf;
reg [D_WIDTH-1 : 0] mem_a_reg;
reg [D_WIDTH-1 : 0] mem_a_reg_mux;
reg [D_WIDTH-1 : 0] mem_a_lat;
reg [D_WIDTH-1 : 0] mem_a_pipe;
reg [D_WIDTH/2-1 : 0] mem_b_reg;
reg [D_WIDTH/2-1 : 0] mem_b_reg_mux;
reg [D_WIDTH/2-1 : 0] mem_b_lat;
reg memp [0 : memp_depth - 1];
reg [DP_WIDTH-1 : 0] memp_wr_a;
reg [DP_WIDTH-1 : 0] ramp_rd_a;
reg [DP_WIDTH-1 : 0] memp_rd_a_wf;
reg [DP_WIDTH-1 : 0] memp_wr_b;
reg [DP_WIDTH-1 : 0] memp_rd_b;
reg [DP_WIDTH-1 : 0] memp_rd_b_rf;
reg [DP_WIDTH-1 : 0] memp_rd_b_wf;
reg [DP_WIDTH-1 : 0] memp_a_reg;
reg [DP_WIDTH-1 : 0] memp_a_reg_mux;
reg [DP_WIDTH-1 : 0] memp_a_lat;
reg [DP_WIDTH-1 : 0] memp_a_out;
reg [DP_WIDTH-1 : 0] memp_a_pipe;
reg [DP_WIDTH/2-1 : 0] memp_b_reg;
reg [DP_WIDTH/2-1 : 0] memp_b_reg_mux;
reg [DP_WIDTH/2-1 : 0] memp_b_lat;
reg [DP_WIDTH/2-1 : 0] memp_b_out;
wire dbit_int;
wire sbit_int;
reg dbit_lat = 0;
reg sbit_lat = 0;
reg dbit_pipe = 0;
reg sbit_pipe = 0;
reg dbit_reg = 0;
reg sbit_reg = 0;
wire [8:0] r_a_ecc_ecc;
reg [8:0] r_a_ecc_lat = 9'b0;
reg [8:0] r_a_ecc_pipe = 9'b0;
reg [8:0] r_a_ecc_reg = 9'b0;
reg dbit_ecc;
reg sbit_ecc;
wire [ADDR_WIDTH-1:0] rd_addr_a_mask;
wire [ADDR_WIDTH-1:0] rd_addr_b_mask;
wire [ADDR_WIDTH-1:0] wr_addr_a_mask;
wire [ADDR_WIDTH-1:0] wr_addr_b_mask;
reg [ADDR_WIDTH-1:0] rd_addr_a = 0;
reg [ADDR_WIDTH-1:0] rd_addr_b = 0;
reg [ADDR_WIDTH-1:0] wr_addr_a = 0;
reg [ADDR_WIDTH-1:0] wr_addr_b = 0;
reg wr_a_rd_b_addr_coll = 1'b0;
reg wr_addr_coll = 1'b0;
reg wr_b_rd_a_addr_coll = 1'b0;
reg [7:0] synd_wr;
reg [7:0] synd_rd;
reg [7:0] synd_ecc;
wire sdp_mode;
wire sdp_mode_wr;
wire sdp_mode_rd;
// clk period for collision window variables
integer t_max_a=3000, t_max_b=3000;
reg clka_toggled=1'b0, clkb_toggled=1'b0;
reg clka_done=1'b0, clkb_done=1'b0;
reg clka_timeout=0, clkb_timeout=0;
wire clks_done;
reg en_clk_sync = 1'b0;
// define tasks, functions
function [7:0] fn_ecc (
input encode,
input [63:0] d_i,
input [7:0] dp_i
);
reg ecc_7;
begin
fn_ecc[0] = d_i[0] ^ d_i[1] ^ d_i[3] ^ d_i[4] ^ d_i[6] ^
d_i[8] ^ d_i[10] ^ d_i[11] ^ d_i[13] ^ d_i[15] ^
d_i[17] ^ d_i[19] ^ d_i[21] ^ d_i[23] ^ d_i[25] ^
d_i[26] ^ d_i[28] ^ d_i[30] ^ d_i[32] ^ d_i[34] ^
d_i[36] ^ d_i[38] ^ d_i[40] ^ d_i[42] ^ d_i[44] ^
d_i[46] ^ d_i[48] ^ d_i[50] ^ d_i[52] ^ d_i[54] ^
d_i[56] ^ d_i[57] ^ d_i[59] ^ d_i[61] ^ d_i[63];
fn_ecc[1] = d_i[0] ^ d_i[2] ^ d_i[3] ^ d_i[5] ^ d_i[6] ^
d_i[9] ^ d_i[10] ^ d_i[12] ^ d_i[13] ^ d_i[16] ^
d_i[17] ^ d_i[20] ^ d_i[21] ^ d_i[24] ^ d_i[25] ^
d_i[27] ^ d_i[28] ^ d_i[31] ^ d_i[32] ^ d_i[35] ^
d_i[36] ^ d_i[39] ^ d_i[40] ^ d_i[43] ^ d_i[44] ^
d_i[47] ^ d_i[48] ^ d_i[51] ^ d_i[52] ^ d_i[55] ^
d_i[56] ^ d_i[58] ^ d_i[59] ^ d_i[62] ^ d_i[63];
fn_ecc[2] = d_i[1] ^ d_i[2] ^ d_i[3] ^ d_i[7] ^ d_i[8] ^
d_i[9] ^ d_i[10] ^ d_i[14] ^ d_i[15] ^ d_i[16] ^
d_i[17] ^ d_i[22] ^ d_i[23] ^ d_i[24] ^ d_i[25] ^
d_i[29] ^ d_i[30] ^ d_i[31] ^ d_i[32] ^ d_i[37] ^
d_i[38] ^ d_i[39] ^ d_i[40] ^ d_i[45] ^ d_i[46] ^
d_i[47] ^ d_i[48] ^ d_i[53] ^ d_i[54] ^ d_i[55] ^
d_i[56] ^ d_i[60] ^ d_i[61] ^ d_i[62] ^ d_i[63];
fn_ecc[3] = d_i[4] ^ d_i[5] ^ d_i[6] ^ d_i[7] ^ d_i[8] ^
d_i[9] ^ d_i[10] ^ d_i[18] ^ d_i[19] ^ d_i[20] ^
d_i[21] ^ d_i[22] ^ d_i[23] ^ d_i[24] ^ d_i[25] ^
d_i[33] ^ d_i[34] ^ d_i[35] ^ d_i[36] ^ d_i[37] ^
d_i[38] ^ d_i[39] ^ d_i[40] ^ d_i[49] ^ d_i[50] ^
d_i[51] ^ d_i[52] ^ d_i[53] ^ d_i[54] ^ d_i[55] ^
d_i[56];
fn_ecc[4] = d_i[11] ^ d_i[12] ^ d_i[13] ^ d_i[14] ^ d_i[15] ^
d_i[16] ^ d_i[17] ^ d_i[18] ^ d_i[19] ^ d_i[20] ^
d_i[21] ^ d_i[22] ^ d_i[23] ^ d_i[24] ^ d_i[25] ^
d_i[41] ^ d_i[42] ^ d_i[43] ^ d_i[44] ^ d_i[45] ^
d_i[46] ^ d_i[47] ^ d_i[48] ^ d_i[49] ^ d_i[50] ^
d_i[51] ^ d_i[52] ^ d_i[53] ^ d_i[54] ^ d_i[55] ^
d_i[56];
fn_ecc[5] = d_i[26] ^ d_i[27] ^ d_i[28] ^ d_i[29] ^ d_i[30] ^
d_i[31] ^ d_i[32] ^ d_i[33] ^ d_i[34] ^ d_i[35] ^
d_i[36] ^ d_i[37] ^ d_i[38] ^ d_i[39] ^ d_i[40] ^
d_i[41] ^ d_i[42] ^ d_i[43] ^ d_i[44] ^ d_i[45] ^
d_i[46] ^ d_i[47] ^ d_i[48] ^ d_i[49] ^ d_i[50] ^
d_i[51] ^ d_i[52] ^ d_i[53] ^ d_i[54] ^ d_i[55] ^
d_i[56];
fn_ecc[6] = d_i[57] ^ d_i[58] ^ d_i[59] ^ d_i[60] ^ d_i[61] ^
d_i[62] ^ d_i[63];
ecc_7 = d_i[0] ^ d_i[1] ^ d_i[2] ^ d_i[3] ^ d_i[4] ^
d_i[5] ^ d_i[6] ^ d_i[7] ^ d_i[8] ^ d_i[9] ^
d_i[10] ^ d_i[11] ^ d_i[12] ^ d_i[13] ^ d_i[14] ^
d_i[15] ^ d_i[16] ^ d_i[17] ^ d_i[18] ^ d_i[19] ^
d_i[20] ^ d_i[21] ^ d_i[22] ^ d_i[23] ^ d_i[24] ^
d_i[25] ^ d_i[26] ^ d_i[27] ^ d_i[28] ^ d_i[29] ^
d_i[30] ^ d_i[31] ^ d_i[32] ^ d_i[33] ^ d_i[34] ^
d_i[35] ^ d_i[36] ^ d_i[37] ^ d_i[38] ^ d_i[39] ^
d_i[40] ^ d_i[41] ^ d_i[42] ^ d_i[43] ^ d_i[44] ^
d_i[45] ^ d_i[46] ^ d_i[47] ^ d_i[48] ^ d_i[49] ^
d_i[50] ^ d_i[51] ^ d_i[52] ^ d_i[53] ^ d_i[54] ^
d_i[55] ^ d_i[56] ^ d_i[57] ^ d_i[58] ^ d_i[59] ^
d_i[60] ^ d_i[61] ^ d_i[62] ^ d_i[63];
if (encode) begin
fn_ecc[7] = ecc_7 ^
fn_ecc[0] ^ fn_ecc[1] ^ fn_ecc[2] ^ fn_ecc[3] ^
fn_ecc[4] ^ fn_ecc[5] ^ fn_ecc[6];
end
else begin
fn_ecc[7] = ecc_7 ^
dp_i[0] ^ dp_i[1] ^ dp_i[2] ^ dp_i[3] ^
dp_i[4] ^ dp_i[5] ^ dp_i[6];
end
end
endfunction // fn_ecc
function [71:0] fn_cor_bit (
input [6:0] error_bit,
input [63:0] d_i,
input [7:0] dp_i
);
reg [71:0] cor_int;
begin
cor_int = {d_i[63:57], dp_i[6], d_i[56:26], dp_i[5], d_i[25:11], dp_i[4],
d_i[10:4], dp_i[3], d_i[3:1], dp_i[2], d_i[0], dp_i[1:0],
dp_i[7]};
cor_int[error_bit] = ~cor_int[error_bit];
fn_cor_bit = {cor_int[0], cor_int[64], cor_int[32], cor_int[16],
cor_int[8], cor_int[4], cor_int[2:1], cor_int[71:65],
cor_int[63:33], cor_int[31:17], cor_int[15:9],
cor_int[7:5], cor_int[3]};
end
endfunction // fn_cor_bit
assign mem_rst_a = RSTRAMARSTRAM_in;
assign mem_rst_b = sdp_mode ? RSTRAMARSTRAM_in : RSTRAMB_in;
assign INJECTDBITERR_int = (EN_ECC_WRITE_BIN == EN_ECC_WRITE_FALSE) ? 1'b0 :
INJECTDBITERR_in;
assign INJECTSBITERR_int = (EN_ECC_WRITE_BIN == EN_ECC_WRITE_FALSE) ? 1'b0 :
INJECTSBITERR_in || INJECTDBITERR_in;
wire [35:0] bit_err_pat;
assign bit_err_pat = INJECTDBITERR_int ? 36'h400000004 : INJECTSBITERR_int ? 36'h000000004 : 36'h0;
always @ (*) begin
if (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE)) && CASDIMUXA_in)
mem_wr_a = {32'h0, CASDINA_in};
else
mem_wr_a = {32'h0, DINADIN_in};
end
always @ (*) begin
if (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE)) && CASDIMUXA_in)
memp_wr_a = {4'h0, CASDINPA_in};
else
memp_wr_a = {4'h0, DINPADINP_in};
end
always @ (*) begin
if (INJECTDBITERR_int || INJECTSBITERR_int) begin
if (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST) ||
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE)) && CASDIMUXB_in)
mem_wr_b = {CASDINB_in, CASDINA_in} ^ {bit_err_pat, 28'h0};
else
mem_wr_b = {DINBDIN_in, DINADIN_in} ^ {bit_err_pat, 28'h0};
end
else if (WRITE_WIDTH_B_BIN == WRITE_WIDTH_B_72) begin
if (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST) ||
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE)) && CASDIMUXB_in)
mem_wr_b = {CASDINB_in, CASDINA_in};
else
mem_wr_b = {DINBDIN_in, DINADIN_in};
end
else begin
if (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST) ||
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE)) && CASDIMUXB_in)
mem_wr_b = {32'h0, CASDINB_in};
else
mem_wr_b = {32'b0, DINBDIN_in};
end
end
always @ (*) begin
if (EN_ECC_WRITE_BIN == EN_ECC_WRITE_TRUE) begin
memp_wr_b = synd_wr;
end
else if (WRITE_WIDTH_B_BIN == WRITE_WIDTH_B_72) begin
if (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST) ||
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE)) && CASDIMUXB_in)
memp_wr_b = {CASDINPB_in, CASDINPA_in};
else
memp_wr_b = {DINPBDINP_in, DINPADINP_in};
end
else begin
if (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST) ||
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE)) && CASDIMUXB_in)
memp_wr_b = {32'h0, CASDINPB_in};
else
memp_wr_b = {32'b0, DINPBDINP_in};
end
end
assign mem_wr_en_a = ~sdp_mode && ENARDEN_in && |WEA_in;
assign mem_rd_en_a = (WRITE_MODE_A_BIN == WRITE_MODE_A_NO_CHANGE) ?
ENARDEN_in && (~mem_wr_en_a || mem_rst_a) : ENARDEN_in;
assign mem_wr_en_b = ENBWREN_in && (sdp_mode ? |WEBWE_in : |WEBWE_in[DP_WIDTH/2-1:0]);
assign mem_rd_en_b = (WRITE_MODE_B_BIN == WRITE_MODE_B_NO_CHANGE) ?
~sdp_mode && ENBWREN_in && (~mem_wr_en_b || mem_rst_b) :
~sdp_mode && ENBWREN_in;
assign CASCADE_ORDER_A_BIN =
(CASCADE_ORDER_A_REG == "NONE") ? CASCADE_ORDER_A_NONE :
(CASCADE_ORDER_A_REG == "FIRST") ? CASCADE_ORDER_A_FIRST :
(CASCADE_ORDER_A_REG == "LAST") ? CASCADE_ORDER_A_LAST :
(CASCADE_ORDER_A_REG == "MIDDLE") ? CASCADE_ORDER_A_MIDDLE :
CASCADE_ORDER_A_NONE;
assign CASCADE_ORDER_B_BIN =
(CASCADE_ORDER_B_REG == "NONE") ? CASCADE_ORDER_B_NONE :
(CASCADE_ORDER_B_REG == "FIRST") ? CASCADE_ORDER_B_FIRST :
(CASCADE_ORDER_B_REG == "LAST") ? CASCADE_ORDER_B_LAST :
(CASCADE_ORDER_B_REG == "MIDDLE") ? CASCADE_ORDER_B_MIDDLE :
CASCADE_ORDER_B_NONE;
assign CLOCK_DOMAINS_BIN =
(CLOCK_DOMAINS_REG == "INDEPENDENT") ? CLOCK_DOMAINS_INDEPENDENT :
(CLOCK_DOMAINS_REG == "COMMON") ? CLOCK_DOMAINS_COMMON :
CLOCK_DOMAINS_INDEPENDENT;
assign DOA_REG_BIN =
(DOA_REG_REG == 1) ? DOA_REG_1 :
(DOA_REG_REG == 0) ? DOA_REG_0 :
DOA_REG_1;
assign DOB_REG_BIN =
(DOB_REG_REG == 1) ? DOB_REG_1 :
(DOB_REG_REG == 0) ? DOB_REG_0 :
DOB_REG_1;
assign ENADDRENA_BIN =
(ENADDRENA_REG == "FALSE") ? ENADDRENA_FALSE :
(ENADDRENA_REG == "TRUE") ? ENADDRENA_TRUE :
ENADDRENA_FALSE;
assign ENADDRENB_BIN =
(ENADDRENB_REG == "FALSE") ? ENADDRENB_FALSE :
(ENADDRENB_REG == "TRUE") ? ENADDRENB_TRUE :
ENADDRENB_FALSE;
assign EN_ECC_PIPE_BIN =
(EN_ECC_PIPE_REG == "FALSE") ? EN_ECC_PIPE_FALSE :
(EN_ECC_PIPE_REG == "TRUE") ? EN_ECC_PIPE_TRUE :
EN_ECC_PIPE_FALSE;
assign EN_ECC_READ_BIN =
(EN_ECC_READ_REG == "FALSE") ? EN_ECC_READ_FALSE :
(EN_ECC_READ_REG == "TRUE") ? EN_ECC_READ_TRUE :
EN_ECC_READ_FALSE;
assign EN_ECC_WRITE_BIN =
(EN_ECC_WRITE_REG == "FALSE") ? EN_ECC_WRITE_FALSE :
(EN_ECC_WRITE_REG == "TRUE") ? EN_ECC_WRITE_TRUE :
EN_ECC_WRITE_FALSE;
assign INITP_BIN['h00] = INITP_00_REG;
assign INITP_BIN['h01] = INITP_01_REG;
assign INITP_BIN['h02] = INITP_02_REG;
assign INITP_BIN['h03] = INITP_03_REG;
assign INITP_BIN['h04] = INITP_04_REG;
assign INITP_BIN['h05] = INITP_05_REG;
assign INITP_BIN['h06] = INITP_06_REG;
assign INITP_BIN['h07] = INITP_07_REG;
assign INITP_BIN['h08] = INITP_08_REG;
assign INITP_BIN['h09] = INITP_09_REG;
assign INITP_BIN['h0A] = INITP_0A_REG;
assign INITP_BIN['h0B] = INITP_0B_REG;
assign INITP_BIN['h0C] = INITP_0C_REG;
assign INITP_BIN['h0D] = INITP_0D_REG;
assign INITP_BIN['h0E] = INITP_0E_REG;
assign INITP_BIN['h0F] = INITP_0F_REG;
assign INIT_BIN['h00] = INIT_00_REG;
assign INIT_BIN['h01] = INIT_01_REG;
assign INIT_BIN['h02] = INIT_02_REG;
assign INIT_BIN['h03] = INIT_03_REG;
assign INIT_BIN['h04] = INIT_04_REG;
assign INIT_BIN['h05] = INIT_05_REG;
assign INIT_BIN['h06] = INIT_06_REG;
assign INIT_BIN['h07] = INIT_07_REG;
assign INIT_BIN['h08] = INIT_08_REG;
assign INIT_BIN['h09] = INIT_09_REG;
assign INIT_BIN['h0A] = INIT_0A_REG;
assign INIT_BIN['h0B] = INIT_0B_REG;
assign INIT_BIN['h0C] = INIT_0C_REG;
assign INIT_BIN['h0D] = INIT_0D_REG;
assign INIT_BIN['h0E] = INIT_0E_REG;
assign INIT_BIN['h0F] = INIT_0F_REG;
assign INIT_BIN['h10] = INIT_10_REG;
assign INIT_BIN['h11] = INIT_11_REG;
assign INIT_BIN['h12] = INIT_12_REG;
assign INIT_BIN['h13] = INIT_13_REG;
assign INIT_BIN['h14] = INIT_14_REG;
assign INIT_BIN['h15] = INIT_15_REG;
assign INIT_BIN['h16] = INIT_16_REG;
assign INIT_BIN['h17] = INIT_17_REG;
assign INIT_BIN['h18] = INIT_18_REG;
assign INIT_BIN['h19] = INIT_19_REG;
assign INIT_BIN['h1A] = INIT_1A_REG;
assign INIT_BIN['h1B] = INIT_1B_REG;
assign INIT_BIN['h1C] = INIT_1C_REG;
assign INIT_BIN['h1D] = INIT_1D_REG;
assign INIT_BIN['h1E] = INIT_1E_REG;
assign INIT_BIN['h1F] = INIT_1F_REG;
assign INIT_BIN['h20] = INIT_20_REG;
assign INIT_BIN['h21] = INIT_21_REG;
assign INIT_BIN['h22] = INIT_22_REG;
assign INIT_BIN['h23] = INIT_23_REG;
assign INIT_BIN['h24] = INIT_24_REG;
assign INIT_BIN['h25] = INIT_25_REG;
assign INIT_BIN['h26] = INIT_26_REG;
assign INIT_BIN['h27] = INIT_27_REG;
assign INIT_BIN['h28] = INIT_28_REG;
assign INIT_BIN['h29] = INIT_29_REG;
assign INIT_BIN['h2A] = INIT_2A_REG;
assign INIT_BIN['h2B] = INIT_2B_REG;
assign INIT_BIN['h2C] = INIT_2C_REG;
assign INIT_BIN['h2D] = INIT_2D_REG;
assign INIT_BIN['h2E] = INIT_2E_REG;
assign INIT_BIN['h2F] = INIT_2F_REG;
assign INIT_BIN['h30] = INIT_30_REG;
assign INIT_BIN['h31] = INIT_31_REG;
assign INIT_BIN['h32] = INIT_32_REG;
assign INIT_BIN['h33] = INIT_33_REG;
assign INIT_BIN['h34] = INIT_34_REG;
assign INIT_BIN['h35] = INIT_35_REG;
assign INIT_BIN['h36] = INIT_36_REG;
assign INIT_BIN['h37] = INIT_37_REG;
assign INIT_BIN['h38] = INIT_38_REG;
assign INIT_BIN['h39] = INIT_39_REG;
assign INIT_BIN['h3A] = INIT_3A_REG;
assign INIT_BIN['h3B] = INIT_3B_REG;
assign INIT_BIN['h3C] = INIT_3C_REG;
assign INIT_BIN['h3D] = INIT_3D_REG;
assign INIT_BIN['h3E] = INIT_3E_REG;
assign INIT_BIN['h3F] = INIT_3F_REG;
assign INIT_BIN['h40] = INIT_40_REG;
assign INIT_BIN['h41] = INIT_41_REG;
assign INIT_BIN['h42] = INIT_42_REG;
assign INIT_BIN['h43] = INIT_43_REG;
assign INIT_BIN['h44] = INIT_44_REG;
assign INIT_BIN['h45] = INIT_45_REG;
assign INIT_BIN['h46] = INIT_46_REG;
assign INIT_BIN['h47] = INIT_47_REG;
assign INIT_BIN['h48] = INIT_48_REG;
assign INIT_BIN['h49] = INIT_49_REG;
assign INIT_BIN['h4A] = INIT_4A_REG;
assign INIT_BIN['h4B] = INIT_4B_REG;
assign INIT_BIN['h4C] = INIT_4C_REG;
assign INIT_BIN['h4D] = INIT_4D_REG;
assign INIT_BIN['h4E] = INIT_4E_REG;
assign INIT_BIN['h4F] = INIT_4F_REG;
assign INIT_BIN['h50] = INIT_50_REG;
assign INIT_BIN['h51] = INIT_51_REG;
assign INIT_BIN['h52] = INIT_52_REG;
assign INIT_BIN['h53] = INIT_53_REG;
assign INIT_BIN['h54] = INIT_54_REG;
assign INIT_BIN['h55] = INIT_55_REG;
assign INIT_BIN['h56] = INIT_56_REG;
assign INIT_BIN['h57] = INIT_57_REG;
assign INIT_BIN['h58] = INIT_58_REG;
assign INIT_BIN['h59] = INIT_59_REG;
assign INIT_BIN['h5A] = INIT_5A_REG;
assign INIT_BIN['h5B] = INIT_5B_REG;
assign INIT_BIN['h5C] = INIT_5C_REG;
assign INIT_BIN['h5D] = INIT_5D_REG;
assign INIT_BIN['h5E] = INIT_5E_REG;
assign INIT_BIN['h5F] = INIT_5F_REG;
assign INIT_BIN['h60] = INIT_60_REG;
assign INIT_BIN['h61] = INIT_61_REG;
assign INIT_BIN['h62] = INIT_62_REG;
assign INIT_BIN['h63] = INIT_63_REG;
assign INIT_BIN['h64] = INIT_64_REG;
assign INIT_BIN['h65] = INIT_65_REG;
assign INIT_BIN['h66] = INIT_66_REG;
assign INIT_BIN['h67] = INIT_67_REG;
assign INIT_BIN['h68] = INIT_68_REG;
assign INIT_BIN['h69] = INIT_69_REG;
assign INIT_BIN['h6A] = INIT_6A_REG;
assign INIT_BIN['h6B] = INIT_6B_REG;
assign INIT_BIN['h6C] = INIT_6C_REG;
assign INIT_BIN['h6D] = INIT_6D_REG;
assign INIT_BIN['h6E] = INIT_6E_REG;
assign INIT_BIN['h6F] = INIT_6F_REG;
assign INIT_BIN['h70] = INIT_70_REG;
assign INIT_BIN['h71] = INIT_71_REG;
assign INIT_BIN['h72] = INIT_72_REG;
assign INIT_BIN['h73] = INIT_73_REG;
assign INIT_BIN['h74] = INIT_74_REG;
assign INIT_BIN['h75] = INIT_75_REG;
assign INIT_BIN['h76] = INIT_76_REG;
assign INIT_BIN['h77] = INIT_77_REG;
assign INIT_BIN['h78] = INIT_78_REG;
assign INIT_BIN['h79] = INIT_79_REG;
assign INIT_BIN['h7A] = INIT_7A_REG;
assign INIT_BIN['h7B] = INIT_7B_REG;
assign INIT_BIN['h7C] = INIT_7C_REG;
assign INIT_BIN['h7D] = INIT_7D_REG;
assign INIT_BIN['h7E] = INIT_7E_REG;
assign INIT_BIN['h7F] = INIT_7F_REG;
assign INIT_A_BIN = INIT_A_REG;
assign INIT_B_BIN = INIT_B_REG;
// assign INIT_FILE_BIN =
// (INIT_FILE_REG == "NONE") ? INIT_FILE_NONE :
// INIT_FILE_NONE;
assign IS_CLKARDCLK_INVERTED_BIN = IS_CLKARDCLK_INVERTED_REG;
assign IS_CLKBWRCLK_INVERTED_BIN = IS_CLKBWRCLK_INVERTED_REG;
assign IS_ENARDEN_INVERTED_BIN = IS_ENARDEN_INVERTED_REG;
assign IS_ENBWREN_INVERTED_BIN = IS_ENBWREN_INVERTED_REG;
assign IS_RSTRAMARSTRAM_INVERTED_BIN = IS_RSTRAMARSTRAM_INVERTED_REG;
assign IS_RSTRAMB_INVERTED_BIN = IS_RSTRAMB_INVERTED_REG;
assign IS_RSTREGARSTREG_INVERTED_BIN = IS_RSTREGARSTREG_INVERTED_REG;
assign IS_RSTREGB_INVERTED_BIN = IS_RSTREGB_INVERTED_REG;
assign RDADDRCHANGEA_BIN =
(RDADDRCHANGEA_REG == "FALSE") ? RDADDRCHANGEA_FALSE :
(RDADDRCHANGEA_REG == "TRUE") ? RDADDRCHANGEA_TRUE :
RDADDRCHANGEA_FALSE;
assign RDADDRCHANGEB_BIN =
(RDADDRCHANGEB_REG == "FALSE") ? RDADDRCHANGEB_FALSE :
(RDADDRCHANGEB_REG == "TRUE") ? RDADDRCHANGEB_TRUE :
RDADDRCHANGEB_FALSE;
assign READ_WIDTH_A_BIN =
(READ_WIDTH_A_REG == 0) ? READ_WIDTH_A_0 :
(READ_WIDTH_A_REG == 1) ? READ_WIDTH_A_1 :
(READ_WIDTH_A_REG == 2) ? READ_WIDTH_A_2 :
(READ_WIDTH_A_REG == 4) ? READ_WIDTH_A_4 :
(READ_WIDTH_A_REG == 9) ? READ_WIDTH_A_9 :
(READ_WIDTH_A_REG == 18) ? READ_WIDTH_A_18 :
(READ_WIDTH_A_REG == 36) ? READ_WIDTH_A_36 :
(READ_WIDTH_A_REG == 72) ? READ_WIDTH_A_72 :
READ_WIDTH_A_0;
assign READ_WIDTH_B_BIN =
(READ_WIDTH_B_REG == 0) ? READ_WIDTH_B_0 :
(READ_WIDTH_B_REG == 1) ? READ_WIDTH_B_1 :
(READ_WIDTH_B_REG == 2) ? READ_WIDTH_B_2 :
(READ_WIDTH_B_REG == 4) ? READ_WIDTH_B_4 :
(READ_WIDTH_B_REG == 9) ? READ_WIDTH_B_9 :
(READ_WIDTH_B_REG == 18) ? READ_WIDTH_B_18 :
(READ_WIDTH_B_REG == 36) ? READ_WIDTH_B_36 :
READ_WIDTH_B_0;
assign RSTREG_PRIORITY_A_BIN =
(RSTREG_PRIORITY_A_REG == "RSTREG") ? RSTREG_PRIORITY_A_RSTREG :
(RSTREG_PRIORITY_A_REG == "REGCE") ? RSTREG_PRIORITY_A_REGCE :
RSTREG_PRIORITY_A_RSTREG;
assign RSTREG_PRIORITY_B_BIN =
(RSTREG_PRIORITY_B_REG == "RSTREG") ? RSTREG_PRIORITY_B_RSTREG :
(RSTREG_PRIORITY_B_REG == "REGCE") ? RSTREG_PRIORITY_B_REGCE :
RSTREG_PRIORITY_B_RSTREG;
assign SIM_COLLISION_CHECK_BIN =
(SIM_COLLISION_CHECK_REG == "ALL") ? SIM_COLLISION_CHECK_ALL :
(SIM_COLLISION_CHECK_REG == "GENERATE_X_ONLY") ? SIM_COLLISION_CHECK_GENERATE_X_ONLY :
(SIM_COLLISION_CHECK_REG == "NONE") ? SIM_COLLISION_CHECK_NONE :
(SIM_COLLISION_CHECK_REG == "WARNING_ONLY") ? SIM_COLLISION_CHECK_WARNING_ONLY :
SIM_COLLISION_CHECK_ALL;
assign SLEEP_ASYNC_BIN =
(SLEEP_ASYNC_REG == "FALSE") ? SLEEP_ASYNC_FALSE :
(SLEEP_ASYNC_REG == "TRUE") ? SLEEP_ASYNC_TRUE :
SLEEP_ASYNC_FALSE;
assign SRVAL_A_BIN = SRVAL_A_REG;
assign SRVAL_B_BIN = SRVAL_B_REG;
assign WRITE_MODE_A_BIN =
(WRITE_MODE_A_REG == "NO_CHANGE") ? WRITE_MODE_A_NO_CHANGE :
(WRITE_MODE_A_REG == "READ_FIRST") ? WRITE_MODE_A_READ_FIRST :
(WRITE_MODE_A_REG == "WRITE_FIRST") ? WRITE_MODE_A_WRITE_FIRST :
WRITE_MODE_A_NO_CHANGE;
assign WRITE_MODE_B_BIN =
(WRITE_MODE_B_REG == "NO_CHANGE") ? WRITE_MODE_B_NO_CHANGE :
(WRITE_MODE_B_REG == "READ_FIRST") ? WRITE_MODE_B_READ_FIRST :
(WRITE_MODE_B_REG == "WRITE_FIRST") ? WRITE_MODE_B_WRITE_FIRST :
WRITE_MODE_B_NO_CHANGE;
assign WRITE_WIDTH_A_BIN =
(WRITE_WIDTH_A_REG == 0) ? WRITE_WIDTH_A_0 :
(WRITE_WIDTH_A_REG == 1) ? WRITE_WIDTH_A_1 :
(WRITE_WIDTH_A_REG == 2) ? WRITE_WIDTH_A_2 :
(WRITE_WIDTH_A_REG == 4) ? WRITE_WIDTH_A_4 :
(WRITE_WIDTH_A_REG == 9) ? WRITE_WIDTH_A_9 :
(WRITE_WIDTH_A_REG == 18) ? WRITE_WIDTH_A_18 :
(WRITE_WIDTH_A_REG == 36) ? WRITE_WIDTH_A_36 :
WRITE_WIDTH_A_0;
assign WRITE_WIDTH_B_BIN =
(WRITE_WIDTH_B_REG == 0) ? WRITE_WIDTH_B_0 :
(WRITE_WIDTH_B_REG == 1) ? WRITE_WIDTH_B_1 :
(WRITE_WIDTH_B_REG == 2) ? WRITE_WIDTH_B_2 :
(WRITE_WIDTH_B_REG == 4) ? WRITE_WIDTH_B_4 :
(WRITE_WIDTH_B_REG == 9) ? WRITE_WIDTH_B_9 :
(WRITE_WIDTH_B_REG == 18) ? WRITE_WIDTH_B_18 :
(WRITE_WIDTH_B_REG == 36) ? WRITE_WIDTH_B_36 :
(WRITE_WIDTH_B_REG == 72) ? WRITE_WIDTH_B_72 :
WRITE_WIDTH_B_0;
initial begin
#1;
trig_attr = 1'b1;
#100;
trig_attr = 1'b0;
end
always @ (posedge trig_attr) begin
if ((attr_test == 1'b1) ||
((CASCADE_ORDER_A_REG != "NONE") &&
(CASCADE_ORDER_A_REG != "FIRST") &&
(CASCADE_ORDER_A_REG != "LAST") &&
(CASCADE_ORDER_A_REG != "MIDDLE"))) begin
$display("Error: [Unisim %s-101] CASCADE_ORDER_A attribute is set to %s. Legal values for this attribute are NONE, FIRST, LAST or MIDDLE. Instance: %m", MODULE_NAME, CASCADE_ORDER_A_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CASCADE_ORDER_B_REG != "NONE") &&
(CASCADE_ORDER_B_REG != "FIRST") &&
(CASCADE_ORDER_B_REG != "LAST") &&
(CASCADE_ORDER_B_REG != "MIDDLE"))) begin
$display("Error: [Unisim %s-102] CASCADE_ORDER_B attribute is set to %s. Legal values for this attribute are NONE, FIRST, LAST or MIDDLE. Instance: %m", MODULE_NAME, CASCADE_ORDER_B_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLOCK_DOMAINS_REG != "INDEPENDENT") &&
(CLOCK_DOMAINS_REG != "COMMON"))) begin
$display("Error: [Unisim %s-103] CLOCK_DOMAINS attribute is set to %s. Legal values for this attribute are INDEPENDENT or COMMON. Instance: %m", MODULE_NAME, CLOCK_DOMAINS_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((DOA_REG_REG != 1) &&
(DOA_REG_REG != 0))) begin
$display("Error: [Unisim %s-104] DOA_REG attribute is set to %d. Legal values for this attribute are 1 or 0. Instance: %m", MODULE_NAME, DOA_REG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((DOB_REG_REG != 1) &&
(DOB_REG_REG != 0))) begin
$display("Error: [Unisim %s-105] DOB_REG attribute is set to %d. Legal values for this attribute are 1 or 0. Instance: %m", MODULE_NAME, DOB_REG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ENADDRENA_REG != "FALSE") &&
(ENADDRENA_REG != "TRUE"))) begin
$display("Error: [Unisim %s-106] ENADDRENA attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, ENADDRENA_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ENADDRENB_REG != "FALSE") &&
(ENADDRENB_REG != "TRUE"))) begin
$display("Error: [Unisim %s-107] ENADDRENB attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, ENADDRENB_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((EN_ECC_PIPE_REG != "FALSE") &&
(EN_ECC_PIPE_REG != "TRUE"))) begin
$display("Error: [Unisim %s-108] EN_ECC_PIPE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, EN_ECC_PIPE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((EN_ECC_READ_REG != "FALSE") &&
(EN_ECC_READ_REG != "TRUE"))) begin
$display("Error: [Unisim %s-109] EN_ECC_READ attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, EN_ECC_READ_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((EN_ECC_WRITE_REG != "FALSE") &&
(EN_ECC_WRITE_REG != "TRUE"))) begin
$display("Error: [Unisim %s-110] EN_ECC_WRITE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, EN_ECC_WRITE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INITP_00_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INITP_00_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-111] INITP_00 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INITP_00_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INITP_01_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INITP_01_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-112] INITP_01 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INITP_01_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INITP_02_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INITP_02_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-113] INITP_02 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INITP_02_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INITP_03_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INITP_03_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-114] INITP_03 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INITP_03_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INITP_04_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INITP_04_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-115] INITP_04 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INITP_04_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INITP_05_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INITP_05_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-116] INITP_05 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INITP_05_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INITP_06_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INITP_06_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-117] INITP_06 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INITP_06_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INITP_07_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INITP_07_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-118] INITP_07 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INITP_07_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INITP_08_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INITP_08_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-119] INITP_08 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INITP_08_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INITP_09_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INITP_09_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-120] INITP_09 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INITP_09_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INITP_0A_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INITP_0A_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-121] INITP_0A attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INITP_0A_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INITP_0B_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INITP_0B_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-122] INITP_0B attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INITP_0B_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INITP_0C_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INITP_0C_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-123] INITP_0C attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INITP_0C_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INITP_0D_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INITP_0D_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-124] INITP_0D attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INITP_0D_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INITP_0E_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INITP_0E_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-125] INITP_0E attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INITP_0E_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INITP_0F_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INITP_0F_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-126] INITP_0F attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INITP_0F_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_00_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_00_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-127] INIT_00 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_00_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_01_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_01_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-128] INIT_01 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_01_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_02_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_02_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-129] INIT_02 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_02_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_03_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_03_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-130] INIT_03 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_03_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_04_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_04_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-131] INIT_04 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_04_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_05_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_05_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-132] INIT_05 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_05_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_06_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_06_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-133] INIT_06 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_06_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_07_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_07_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-134] INIT_07 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_07_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_08_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_08_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-135] INIT_08 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_08_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_09_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_09_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-136] INIT_09 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_09_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_0A_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_0A_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-137] INIT_0A attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_0A_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_0B_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_0B_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-138] INIT_0B attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_0B_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_0C_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_0C_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-139] INIT_0C attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_0C_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_0D_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_0D_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-140] INIT_0D attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_0D_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_0E_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_0E_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-141] INIT_0E attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_0E_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_0F_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_0F_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-142] INIT_0F attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_0F_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_10_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_10_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-143] INIT_10 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_10_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_11_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_11_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-144] INIT_11 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_11_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_12_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_12_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-145] INIT_12 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_12_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_13_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_13_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-146] INIT_13 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_13_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_14_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_14_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-147] INIT_14 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_14_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_15_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_15_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-148] INIT_15 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_15_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_16_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_16_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-149] INIT_16 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_16_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_17_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_17_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-150] INIT_17 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_17_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_18_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_18_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-151] INIT_18 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_18_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_19_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_19_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-152] INIT_19 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_19_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_1A_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_1A_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-153] INIT_1A attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_1A_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_1B_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_1B_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-154] INIT_1B attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_1B_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_1C_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_1C_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-155] INIT_1C attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_1C_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_1D_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_1D_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-156] INIT_1D attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_1D_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_1E_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_1E_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-157] INIT_1E attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_1E_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_1F_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_1F_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-158] INIT_1F attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_1F_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_20_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_20_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-159] INIT_20 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_20_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_21_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_21_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-160] INIT_21 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_21_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_22_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_22_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-161] INIT_22 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_22_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_23_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_23_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-162] INIT_23 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_23_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_24_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_24_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-163] INIT_24 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_24_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_25_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_25_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-164] INIT_25 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_25_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_26_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_26_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-165] INIT_26 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_26_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_27_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_27_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-166] INIT_27 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_27_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_28_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_28_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-167] INIT_28 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_28_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_29_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_29_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-168] INIT_29 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_29_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_2A_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_2A_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-169] INIT_2A attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_2A_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_2B_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_2B_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-170] INIT_2B attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_2B_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_2C_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_2C_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-171] INIT_2C attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_2C_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_2D_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_2D_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-172] INIT_2D attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_2D_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_2E_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_2E_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-173] INIT_2E attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_2E_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_2F_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_2F_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-174] INIT_2F attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_2F_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_30_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_30_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-175] INIT_30 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_30_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_31_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_31_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-176] INIT_31 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_31_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_32_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_32_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-177] INIT_32 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_32_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_33_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_33_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-178] INIT_33 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_33_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_34_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_34_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-179] INIT_34 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_34_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_35_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_35_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-180] INIT_35 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_35_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_36_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_36_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-181] INIT_36 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_36_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_37_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_37_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-182] INIT_37 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_37_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_38_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_38_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-183] INIT_38 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_38_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_39_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_39_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-184] INIT_39 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_39_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_3A_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_3A_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-185] INIT_3A attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_3A_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_3B_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_3B_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-186] INIT_3B attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_3B_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_3C_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_3C_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-187] INIT_3C attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_3C_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_3D_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_3D_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-188] INIT_3D attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_3D_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_3E_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_3E_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-189] INIT_3E attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_3E_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_3F_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_3F_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-190] INIT_3F attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_3F_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_40_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_40_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-191] INIT_40 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_40_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_41_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_41_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-192] INIT_41 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_41_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_42_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_42_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-193] INIT_42 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_42_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_43_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_43_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-194] INIT_43 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_43_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_44_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_44_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-195] INIT_44 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_44_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_45_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_45_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-196] INIT_45 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_45_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_46_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_46_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-197] INIT_46 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_46_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_47_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_47_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-198] INIT_47 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_47_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_48_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_48_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-199] INIT_48 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_48_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_49_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_49_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-200] INIT_49 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_49_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_4A_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_4A_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-201] INIT_4A attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_4A_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_4B_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_4B_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-202] INIT_4B attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_4B_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_4C_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_4C_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-203] INIT_4C attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_4C_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_4D_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_4D_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-204] INIT_4D attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_4D_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_4E_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_4E_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-205] INIT_4E attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_4E_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_4F_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_4F_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-206] INIT_4F attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_4F_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_50_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_50_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-207] INIT_50 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_50_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_51_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_51_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-208] INIT_51 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_51_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_52_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_52_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-209] INIT_52 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_52_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_53_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_53_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-210] INIT_53 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_53_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_54_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_54_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-211] INIT_54 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_54_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_55_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_55_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-212] INIT_55 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_55_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_56_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_56_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-213] INIT_56 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_56_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_57_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_57_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-214] INIT_57 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_57_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_58_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_58_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-215] INIT_58 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_58_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_59_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_59_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-216] INIT_59 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_59_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_5A_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_5A_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-217] INIT_5A attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_5A_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_5B_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_5B_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-218] INIT_5B attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_5B_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_5C_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_5C_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-219] INIT_5C attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_5C_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_5D_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_5D_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-220] INIT_5D attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_5D_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_5E_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_5E_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-221] INIT_5E attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_5E_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_5F_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_5F_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-222] INIT_5F attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_5F_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_60_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_60_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-223] INIT_60 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_60_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_61_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_61_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-224] INIT_61 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_61_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_62_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_62_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-225] INIT_62 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_62_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_63_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_63_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-226] INIT_63 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_63_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_64_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_64_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-227] INIT_64 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_64_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_65_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_65_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-228] INIT_65 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_65_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_66_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_66_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-229] INIT_66 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_66_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_67_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_67_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-230] INIT_67 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_67_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_68_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_68_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-231] INIT_68 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_68_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_69_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_69_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-232] INIT_69 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_69_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_6A_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_6A_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-233] INIT_6A attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_6A_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_6B_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_6B_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-234] INIT_6B attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_6B_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_6C_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_6C_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-235] INIT_6C attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_6C_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_6D_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_6D_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-236] INIT_6D attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_6D_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_6E_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_6E_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-237] INIT_6E attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_6E_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_6F_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_6F_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-238] INIT_6F attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_6F_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_70_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_70_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-239] INIT_70 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_70_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_71_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_71_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-240] INIT_71 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_71_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_72_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_72_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-241] INIT_72 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_72_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_73_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_73_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-242] INIT_73 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_73_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_74_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_74_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-243] INIT_74 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_74_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_75_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_75_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-244] INIT_75 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_75_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_76_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_76_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-245] INIT_76 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_76_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_77_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_77_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-246] INIT_77 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_77_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_78_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_78_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-247] INIT_78 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_78_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_79_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_79_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-248] INIT_79 attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_79_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_7A_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_7A_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-249] INIT_7A attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_7A_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_7B_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_7B_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-250] INIT_7B attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_7B_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_7C_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_7C_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-251] INIT_7C attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_7C_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_7D_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_7D_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-252] INIT_7D attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_7D_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_7E_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_7E_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-253] INIT_7E attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_7E_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_7F_REG < 256'h0000000000000000000000000000000000000000000000000000000000000000) || (INIT_7F_REG > 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-254] INIT_7F attribute is set to %h. Legal values for this attribute are 256'h0000000000000000000000000000000000000000000000000000000000000000 to 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_7F_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_A_REG < 36'h000000000) || (INIT_A_REG > 36'hFFFFFFFFF))) begin
$display("Error: [Unisim %s-255] INIT_A attribute is set to %h. Legal values for this attribute are 36'h000000000 to 36'hFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_A_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_B_REG < 36'h000000000) || (INIT_B_REG > 36'hFFFFFFFFF))) begin
$display("Error: [Unisim %s-256] INIT_B attribute is set to %h. Legal values for this attribute are 36'h000000000 to 36'hFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_B_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_FILE_REG != "NONE"))) begin
$display("INFO: Unisim %s-257] The attribute INIT_FILE is set to (%s) but loading memory contents from a file is not yet supported. Instance: %m", MODULE_NAME, INIT_FILE_REG);
end
if ((attr_test == 1'b1) ||
((IS_CLKARDCLK_INVERTED_REG !== 1'b0) && (IS_CLKARDCLK_INVERTED_REG !== 1'b1))) begin
$display("Error: [Unisim %s-258] IS_CLKARDCLK_INVERTED attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, IS_CLKARDCLK_INVERTED_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((IS_CLKBWRCLK_INVERTED_REG !== 1'b0) && (IS_CLKBWRCLK_INVERTED_REG !== 1'b1))) begin
$display("Error: [Unisim %s-259] IS_CLKBWRCLK_INVERTED attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, IS_CLKBWRCLK_INVERTED_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((IS_ENARDEN_INVERTED_REG !== 1'b0) && (IS_ENARDEN_INVERTED_REG !== 1'b1))) begin
$display("Error: [Unisim %s-260] IS_ENARDEN_INVERTED attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, IS_ENARDEN_INVERTED_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((IS_ENBWREN_INVERTED_REG !== 1'b0) && (IS_ENBWREN_INVERTED_REG !== 1'b1))) begin
$display("Error: [Unisim %s-261] IS_ENBWREN_INVERTED attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, IS_ENBWREN_INVERTED_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((IS_RSTRAMARSTRAM_INVERTED_REG !== 1'b0) && (IS_RSTRAMARSTRAM_INVERTED_REG !== 1'b1))) begin
$display("Error: [Unisim %s-262] IS_RSTRAMARSTRAM_INVERTED attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, IS_RSTRAMARSTRAM_INVERTED_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((IS_RSTRAMB_INVERTED_REG !== 1'b0) && (IS_RSTRAMB_INVERTED_REG !== 1'b1))) begin
$display("Error: [Unisim %s-263] IS_RSTRAMB_INVERTED attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, IS_RSTRAMB_INVERTED_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((IS_RSTREGARSTREG_INVERTED_REG !== 1'b0) && (IS_RSTREGARSTREG_INVERTED_REG !== 1'b1))) begin
$display("Error: [Unisim %s-264] IS_RSTREGARSTREG_INVERTED attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, IS_RSTREGARSTREG_INVERTED_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((IS_RSTREGB_INVERTED_REG !== 1'b0) && (IS_RSTREGB_INVERTED_REG !== 1'b1))) begin
$display("Error: [Unisim %s-265] IS_RSTREGB_INVERTED attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, IS_RSTREGB_INVERTED_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RDADDRCHANGEA_REG != "FALSE") &&
(RDADDRCHANGEA_REG != "TRUE"))) begin
$display("Error: [Unisim %s-266] RDADDRCHANGEA attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, RDADDRCHANGEA_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RDADDRCHANGEB_REG != "FALSE") &&
(RDADDRCHANGEB_REG != "TRUE"))) begin
$display("Error: [Unisim %s-267] RDADDRCHANGEB attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, RDADDRCHANGEB_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((READ_WIDTH_A_REG != 0) &&
(READ_WIDTH_A_REG != 1) &&
(READ_WIDTH_A_REG != 2) &&
(READ_WIDTH_A_REG != 4) &&
(READ_WIDTH_A_REG != 9) &&
(READ_WIDTH_A_REG != 18) &&
(READ_WIDTH_A_REG != 36) &&
(READ_WIDTH_A_REG != 72))) begin
$display("Error: [Unisim %s-268] READ_WIDTH_A attribute is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18, 36 or 72. Instance: %m", MODULE_NAME, READ_WIDTH_A_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((READ_WIDTH_B_REG != 0) &&
(READ_WIDTH_B_REG != 1) &&
(READ_WIDTH_B_REG != 2) &&
(READ_WIDTH_B_REG != 4) &&
(READ_WIDTH_B_REG != 9) &&
(READ_WIDTH_B_REG != 18) &&
(READ_WIDTH_B_REG != 36))) begin
$display("Error: [Unisim %s-269] READ_WIDTH_B attribute is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36. Instance: %m", MODULE_NAME, READ_WIDTH_B_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RSTREG_PRIORITY_A_REG != "RSTREG") &&
(RSTREG_PRIORITY_A_REG != "REGCE"))) begin
$display("Error: [Unisim %s-270] RSTREG_PRIORITY_A attribute is set to %s. Legal values for this attribute are RSTREG or REGCE. Instance: %m", MODULE_NAME, RSTREG_PRIORITY_A_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RSTREG_PRIORITY_B_REG != "RSTREG") &&
(RSTREG_PRIORITY_B_REG != "REGCE"))) begin
$display("Error: [Unisim %s-271] RSTREG_PRIORITY_B attribute is set to %s. Legal values for this attribute are RSTREG or REGCE. Instance: %m", MODULE_NAME, RSTREG_PRIORITY_B_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SIM_COLLISION_CHECK_REG != "ALL") &&
(SIM_COLLISION_CHECK_REG != "GENERATE_X_ONLY") &&
(SIM_COLLISION_CHECK_REG != "NONE") &&
(SIM_COLLISION_CHECK_REG != "WARNING_ONLY"))) begin
$display("Error: [Unisim %s-272] SIM_COLLISION_CHECK attribute is set to %s. Legal values for this attribute are ALL, GENERATE_X_ONLY, NONE or WARNING_ONLY. Instance: %m", MODULE_NAME, SIM_COLLISION_CHECK_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SLEEP_ASYNC_REG != "FALSE") &&
(SLEEP_ASYNC_REG != "TRUE"))) begin
$display("Error: [Unisim %s-273] SLEEP_ASYNC attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, SLEEP_ASYNC_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SRVAL_A_REG < 36'h000000000) || (SRVAL_A_REG > 36'hFFFFFFFFF))) begin
$display("Error: [Unisim %s-274] SRVAL_A attribute is set to %h. Legal values for this attribute are 36'h000000000 to 36'hFFFFFFFFF. Instance: %m", MODULE_NAME, SRVAL_A_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SRVAL_B_REG < 36'h000000000) || (SRVAL_B_REG > 36'hFFFFFFFFF))) begin
$display("Error: [Unisim %s-275] SRVAL_B attribute is set to %h. Legal values for this attribute are 36'h000000000 to 36'hFFFFFFFFF. Instance: %m", MODULE_NAME, SRVAL_B_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((WRITE_MODE_A_REG != "NO_CHANGE") &&
(WRITE_MODE_A_REG != "READ_FIRST") &&
(WRITE_MODE_A_REG != "WRITE_FIRST"))) begin
$display("Error: [Unisim %s-276] WRITE_MODE_A attribute is set to %s. Legal values for this attribute are NO_CHANGE, READ_FIRST or WRITE_FIRST. Instance: %m", MODULE_NAME, WRITE_MODE_A_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((WRITE_MODE_B_REG != "NO_CHANGE") &&
(WRITE_MODE_B_REG != "READ_FIRST") &&
(WRITE_MODE_B_REG != "WRITE_FIRST"))) begin
$display("Error: [Unisim %s-277] WRITE_MODE_B attribute is set to %s. Legal values for this attribute are NO_CHANGE, READ_FIRST or WRITE_FIRST. Instance: %m", MODULE_NAME, WRITE_MODE_B_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((WRITE_WIDTH_A_REG != 0) &&
(WRITE_WIDTH_A_REG != 1) &&
(WRITE_WIDTH_A_REG != 2) &&
(WRITE_WIDTH_A_REG != 4) &&
(WRITE_WIDTH_A_REG != 9) &&
(WRITE_WIDTH_A_REG != 18) &&
(WRITE_WIDTH_A_REG != 36))) begin
$display("Error: [Unisim %s-278] WRITE_WIDTH_A attribute is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36. Instance: %m", MODULE_NAME, WRITE_WIDTH_A_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((WRITE_WIDTH_B_REG != 0) &&
(WRITE_WIDTH_B_REG != 1) &&
(WRITE_WIDTH_B_REG != 2) &&
(WRITE_WIDTH_B_REG != 4) &&
(WRITE_WIDTH_B_REG != 9) &&
(WRITE_WIDTH_B_REG != 18) &&
(WRITE_WIDTH_B_REG != 36) &&
(WRITE_WIDTH_B_REG != 72))) begin
$display("Error: [Unisim %s-279] WRITE_WIDTH_B attribute is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18, 36 or 72. Instance: %m", MODULE_NAME, WRITE_WIDTH_B_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) #100 $finish;
end
initial begin
INIT_MEM <= #100 1'b1;
INIT_MEM <= #200 1'b0;
end
assign rd_addr_a_mask =
(READ_WIDTH_A_REG == 0) ? {{ADDR_WIDTH-6{1'b1}}, 6'h3f} :
(READ_WIDTH_A_REG == 1) ? {{ADDR_WIDTH-6{1'b1}}, 6'h3f} :
(READ_WIDTH_A_REG == 2) ? {{ADDR_WIDTH-6{1'b1}}, 6'h3e} :
(READ_WIDTH_A_REG == 4) ? {{ADDR_WIDTH-6{1'b1}}, 6'h3c} :
(READ_WIDTH_A_REG == 9) ? {{ADDR_WIDTH-6{1'b1}}, 6'h38} :
(READ_WIDTH_A_REG == 18) ? {{ADDR_WIDTH-6{1'b1}}, 6'h30} :
(READ_WIDTH_A_REG == 36) ? {{ADDR_WIDTH-6{1'b1}}, 6'h20} :
(READ_WIDTH_A_REG == 72) ? {{ADDR_WIDTH-6{1'b1}}, 6'h00} :
{{ADDR_WIDTH-6{1'b1}}, 6'h3f};
assign rd_addr_b_mask =
(READ_WIDTH_B_REG == 0) ? {{ADDR_WIDTH-6{1'b1}}, 6'h3f} :
(READ_WIDTH_B_REG == 1) ? {{ADDR_WIDTH-6{1'b1}}, 6'h3f} :
(READ_WIDTH_B_REG == 2) ? {{ADDR_WIDTH-6{1'b1}}, 6'h3e} :
(READ_WIDTH_B_REG == 4) ? {{ADDR_WIDTH-6{1'b1}}, 6'h3c} :
(READ_WIDTH_B_REG == 9) ? {{ADDR_WIDTH-6{1'b1}}, 6'h38} :
(READ_WIDTH_B_REG == 18) ? {{ADDR_WIDTH-6{1'b1}}, 6'h30} :
(READ_WIDTH_B_REG == 36) ? {{ADDR_WIDTH-6{1'b1}}, 6'h20} :
(READ_WIDTH_B_REG == 72) ? {{ADDR_WIDTH-6{1'b1}}, 6'h00} :
{{ADDR_WIDTH-6{1'b1}}, 6'h3f};
assign wr_addr_a_mask =
(WRITE_WIDTH_A_REG == 0) ? {{ADDR_WIDTH-6{1'b1}}, 6'h3f} :
(WRITE_WIDTH_A_REG == 1) ? {{ADDR_WIDTH-6{1'b1}}, 6'h3f} :
(WRITE_WIDTH_A_REG == 2) ? {{ADDR_WIDTH-6{1'b1}}, 6'h3e} :
(WRITE_WIDTH_A_REG == 4) ? {{ADDR_WIDTH-6{1'b1}}, 6'h3c} :
(WRITE_WIDTH_A_REG == 9) ? {{ADDR_WIDTH-6{1'b1}}, 6'h38} :
(WRITE_WIDTH_A_REG == 18) ? {{ADDR_WIDTH-6{1'b1}}, 6'h30} :
(WRITE_WIDTH_A_REG == 36) ? {{ADDR_WIDTH-6{1'b1}}, 6'h20} :
(WRITE_WIDTH_A_REG == 72) ? {{ADDR_WIDTH-6{1'b1}}, 6'h00} :
{{ADDR_WIDTH-6{1'b1}}, 6'h3f};
assign wr_addr_b_mask =
(WRITE_WIDTH_B_REG == 0) ? {{ADDR_WIDTH-6{1'b1}}, 6'h3f} :
(WRITE_WIDTH_B_REG == 1) ? {{ADDR_WIDTH-6{1'b1}}, 6'h3f} :
(WRITE_WIDTH_B_REG == 2) ? {{ADDR_WIDTH-6{1'b1}}, 6'h3e} :
(WRITE_WIDTH_B_REG == 4) ? {{ADDR_WIDTH-6{1'b1}}, 6'h3c} :
(WRITE_WIDTH_B_REG == 9) ? {{ADDR_WIDTH-6{1'b1}}, 6'h38} :
(WRITE_WIDTH_B_REG == 18) ? {{ADDR_WIDTH-6{1'b1}}, 6'h30} :
(WRITE_WIDTH_B_REG == 36) ? {{ADDR_WIDTH-6{1'b1}}, 6'h20} :
(WRITE_WIDTH_B_REG == 72) ? {{ADDR_WIDTH-6{1'b1}}, 6'h00} :
{{ADDR_WIDTH-6{1'b1}}, 6'h3f};
always @(READ_WIDTH_A_BIN) rd_loops_a <= READ_WIDTH_A_BIN;
always @(READ_WIDTH_B_BIN) rd_loops_b <= READ_WIDTH_B_BIN;
always @(*) begin
if (READ_WIDTH_A_BIN > READ_WIDTH_B_BIN) rd_loops_f <= READ_WIDTH_A_BIN;
else rd_loops_f <= READ_WIDTH_B_BIN;
end
always @(WRITE_WIDTH_A_BIN) wr_loops_a <= WRITE_WIDTH_A_BIN;
always @(WRITE_WIDTH_B_BIN) wr_loops_b <= WRITE_WIDTH_B_BIN;
// determine clk period for collision window.
assign clks_done = clka_done && clkb_done;
initial begin
@(negedge glblGSR);
clka_timeout = 0;
clka_timeout <= #6000 1;
@(posedge CLKARDCLK_in or posedge clka_timeout);
if (~clka_timeout) begin
t_max_a = 0;
for (i=0;i<2000;i=i+1) begin
if (~clka_done) begin
if (CLKARDCLK_in) begin
#1;
t_max_a = t_max_a + 1;
end
else begin
t_max_a = t_max_a - 1;
clka_done = 1;
i = 2000;
end
end
end
end
clka_done = 1;
end
initial begin
@(posedge CLKARDCLK_in)
@(posedge CLKARDCLK_in)
clka_toggled = 1'b1;
end
initial begin
@(posedge CLKBWRCLK_in)
@(posedge CLKBWRCLK_in)
clkb_toggled = 1'b1;
end
initial begin
@(negedge glblGSR);
clkb_timeout = 0;
clkb_timeout <= #6000 1;
@(posedge CLKBWRCLK_in or posedge clkb_timeout);
if (~clkb_timeout) begin
t_max_b = 0;
for (j=0;j<2000;j=j+1) begin
if (~clkb_done) begin
if (CLKBWRCLK_in) begin
#1;
t_max_b = t_max_b + 1;
end
else begin
t_max_b = t_max_b - 1;
clkb_done = 1;
j = 2000;
end
end
end
end
clkb_done = 1;
end
initial begin
@(posedge clks_done);
if (((t_max_a > 50) && (t_max_a < 1500)) &&
((t_max_b == 0) || (t_max_a <= t_max_b))) t_coll_max = 2 * t_max_a - 49;
if (((t_max_b > 50) && (t_max_b < 1500)) &&
((t_max_a == 0) || (t_max_b < t_max_a))) t_coll_max = 2 * t_max_b - 49;
end
always @ (posedge CLKARDCLK_in) begin
if (glblGSR || (SLEEP_ASYNC_BIN == SLEEP_ASYNC_TRUE)) begin
SLEEP_reg <= 1'b0;
SLEEP_reg1 <= 1'b0;
end
else begin
{SLEEP_reg, SLEEP_reg1} <= {SLEEP_reg1, SLEEP_in};
end
end
assign SLEEP_int = SLEEP_reg1 || SLEEP_in;
assign sdp_mode_wr = (WRITE_WIDTH_B_BIN == WRITE_WIDTH_B_72) ? 1'b1 : 1'b0;
assign sdp_mode_rd = (READ_WIDTH_A_BIN == READ_WIDTH_A_72) ? 1'b1 : 1'b0;
assign sdp_mode = sdp_mode_rd || sdp_mode_wr;
assign REGCE_A_int = REGCEAREGCE_in;
assign REGCE_B_int = REGCEB_in;
assign RSTREG_A_int = (RSTREG_PRIORITY_A_BIN == RSTREG_PRIORITY_A_RSTREG) ?
RSTREGARSTREG_in : (RSTREGARSTREG_in && REGCEAREGCE_in);
assign RSTREG_B_int = (RSTREG_PRIORITY_B_BIN == RSTREG_PRIORITY_B_RSTREG) ?
RSTREGB_in : (RSTREGB_in && REGCEB_in);
assign ADDRENA_int = (ENADDRENA_BIN == ENADDRENA_TRUE) ? ADDRENA_in : 1'b1;
assign ADDRENB_int = (ENADDRENB_BIN == ENADDRENB_TRUE) ? ADDRENB_in : 1'b1;
assign WREN_ecc = ECCPIPECE_in && (EN_ECC_PIPE_BIN == EN_ECC_PIPE_TRUE) && first_read;
assign ECCPARITY_out = eccparity_reg;
assign RDADDRECC_out = (DOA_REG_BIN == DOA_REG_1) ? r_a_ecc_reg : r_a_ecc_ecc;
always @ (*) begin
if (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE)) && CASDOMUXA_reg) begin
SBITERR_out = CASINSBITERR_in;
DBITERR_out = CASINDBITERR_in;
end
else if (DOA_REG_BIN == DOA_REG_1) begin
SBITERR_out = sbit_reg;
DBITERR_out = dbit_reg;
end
else if (EN_ECC_PIPE_BIN == EN_ECC_PIPE_TRUE) begin
SBITERR_out = sbit_pipe;
DBITERR_out = dbit_pipe;
end
else begin
SBITERR_out = sbit_lat;
DBITERR_out = dbit_lat;
end
end
always @ (*) begin
if (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE)) && CASDOMUXA_reg) begin
DOUTADOUT_out = CASDINA_in;
DOUTPADOUTP_out = CASDINPA_in;
end
else if (DOA_REG_BIN == DOA_REG_1) begin
DOUTADOUT_out = mem_a_reg ^ mem_rm_douta;
DOUTPADOUTP_out = memp_a_reg ^ memp_rm_douta;
end
else if (mem_wr_en_a_wf) begin
DOUTADOUT_out = mem_rd_a_wf ^ mem_rm_douta;
DOUTPADOUTP_out = memp_rd_a_wf ^ memp_rm_douta;
end
else if (EN_ECC_PIPE_BIN == EN_ECC_PIPE_TRUE) begin
DOUTADOUT_out = mem_a_pipe ^ mem_rm_douta;
DOUTPADOUTP_out = memp_a_pipe ^ memp_rm_douta;
end
else begin
DOUTADOUT_out = mem_a_lat ^ mem_rm_douta;
DOUTPADOUTP_out = memp_a_lat ^ memp_rm_douta;
end
end
always @ (*) begin
if (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST) ||
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE)) && CASDOMUXB_int) begin
DOUTBDOUT_out = CASDINB_in;
DOUTPBDOUTP_out = CASDINPB_in;
end
else if (sdp_mode_rd) begin
if (DOA_REG_BIN == DOA_REG_1) begin
DOUTBDOUT_out = mem_a_reg[63:32] ^ mem_rm_douta[63:32];
DOUTPBDOUTP_out = memp_a_reg[7:4] ^ memp_rm_douta[7:4];
end
else if (mem_wr_en_a_wf) begin
DOUTBDOUT_out = mem_rd_a_wf[63:32] ^ mem_rm_douta[63:32];
DOUTPBDOUTP_out = memp_rd_a_wf[7:4] ^ memp_rm_douta[7:4];
end
else if (EN_ECC_PIPE_BIN == EN_ECC_PIPE_TRUE) begin
DOUTBDOUT_out = mem_a_pipe[63:32] ^ mem_rm_douta[63:32];
DOUTPBDOUTP_out = memp_a_pipe[7:4] ^ memp_rm_douta[7:4];
end
else begin
DOUTBDOUT_out = mem_a_lat[63:32] ^ mem_rm_douta[63:32];
DOUTPBDOUTP_out = memp_a_lat[7:4] ^ memp_rm_douta[7:4];
end
end
else begin
if (DOB_REG_BIN == DOB_REG_1) begin
DOUTBDOUT_out = mem_b_reg ^ mem_rm_doutb;
DOUTPBDOUTP_out = memp_b_reg ^ memp_rm_doutb;
end
else if (mem_wr_en_b_wf) begin
DOUTBDOUT_out = mem_rd_b_wf ^ mem_rm_doutb;
DOUTPBDOUTP_out = memp_rd_b_wf ^ memp_rm_doutb;
end
else begin
DOUTBDOUT_out = mem_b_lat ^ mem_rm_doutb;
DOUTPBDOUTP_out = memp_b_lat ^ memp_rm_doutb;
end
end
end
always @ (*) begin
if (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE)) &&
CASOREGIMUXA_reg) dbit_ecc = CASINDBITERR_in;
else if (EN_ECC_PIPE_BIN == EN_ECC_PIPE_TRUE) dbit_ecc = dbit_pipe;
else dbit_ecc = dbit_lat;
end
always @ (*) begin
if (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE)) &&
CASOREGIMUXA_reg) sbit_ecc = CASINSBITERR_in;
if (EN_ECC_PIPE_BIN == EN_ECC_PIPE_TRUE) sbit_ecc = sbit_pipe;
else sbit_ecc = sbit_lat;
end
assign r_a_ecc_ecc = (EN_ECC_PIPE_BIN == EN_ECC_PIPE_TRUE) ? r_a_ecc_pipe : r_a_ecc_lat;
assign INIT_A_int =
(READ_WIDTH_A_BIN <= READ_WIDTH_A_9) ? {{8{INIT_A_BIN[8]}}, {8{INIT_A_BIN[7:0]}}} :
(READ_WIDTH_A_BIN == READ_WIDTH_A_18) ? {{4{INIT_A_BIN[17:16]}}, {4{INIT_A_BIN[15:0]}}} :
(READ_WIDTH_A_BIN == READ_WIDTH_A_36) ? {{2{INIT_A_BIN[35:32]}}, {2{INIT_A_BIN[31:0]}}} :
{INIT_B_BIN[35:32],INIT_A_BIN[35:32],INIT_B_BIN[31:0],INIT_A_BIN[31:0]};
assign INIT_B_int =
(READ_WIDTH_B_BIN <= READ_WIDTH_B_9) ? {{4{INIT_B_BIN[8]}}, {4{INIT_B_BIN[7:0]}}} :
(READ_WIDTH_B_BIN == READ_WIDTH_B_18) ? {{2{INIT_B_BIN[17:16]}}, {2{INIT_B_BIN[15:0]}}} :
INIT_B_BIN;
assign SRVAL_A_int =
(READ_WIDTH_A_BIN <= READ_WIDTH_A_9) ? {{8{SRVAL_A_BIN[8]}}, {8{SRVAL_A_BIN[7:0]}}} :
(READ_WIDTH_A_BIN == READ_WIDTH_A_18) ? {{4{SRVAL_A_BIN[17:16]}}, {4{SRVAL_A_BIN[15:0]}}} :
(READ_WIDTH_A_BIN == READ_WIDTH_A_36) ? {{2{SRVAL_A_BIN[35:32]}}, {2{SRVAL_A_BIN[31:0]}}} :
{SRVAL_B_BIN[35:32],SRVAL_A_BIN[35:32],SRVAL_B_BIN[31:0],SRVAL_A_BIN[31:0]};
assign SRVAL_B_int =
(READ_WIDTH_B_BIN <= READ_WIDTH_B_9) ? {{4{SRVAL_B_BIN[8]}}, {4{SRVAL_B_BIN[7:0]}}} :
(READ_WIDTH_B_BIN == READ_WIDTH_B_18) ? {{2{SRVAL_B_BIN[17:16]}}, {2{SRVAL_B_BIN[15:0]}}} :
SRVAL_B_BIN;
// cascade out
assign CASDOUTA_out = ((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_FIRST) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE)) ?
DOUTADOUT_out : {D_WIDTH-1{1'b0}};
assign CASDOUTPA_out = ((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_FIRST) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE)) ?
DOUTPADOUTP_out : {DP_WIDTH-1{1'b0}};
assign CASDOUTB_out = ((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_FIRST) ||
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE)) ?
DOUTBDOUT_out : {D_WIDTH-1{1'b0}};
assign CASDOUTPB_out = ((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_FIRST) ||
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE)) ?
DOUTPBDOUTP_out : {DP_WIDTH-1{1'b0}};
assign CASOUTDBITERR_out = ((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_FIRST) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE)) ?
DBITERR_out : 1'b0;
assign CASOUTSBITERR_out = ((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_FIRST) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE)) ?
SBITERR_out : 1'b0;
// start model internals
// cascade control
always @ (posedge CLKARDCLK_in) begin
if (glblGSR) CASDOMUXA_reg <= 1'b0;
else if (CASDOMUXEN_A_in == 1'b1) CASDOMUXA_reg <= CASDOMUXA_in;
end
always @ (posedge CLKARDCLK_in) begin
if (glblGSR) CASOREGIMUXA_reg <= 1'b0;
else if (CASOREGIMUXEN_A_in == 1'b1) CASOREGIMUXA_reg <= CASOREGIMUXA_in;
end
assign CASDOMUXB_int = (READ_WIDTH_A_BIN == READ_WIDTH_A_72) ?
CASDOMUXA_reg : CASDOMUXB_reg;
always @ (posedge CLKBWRCLK_in) begin
if (glblGSR || sdp_mode) CASDOMUXB_reg <= 1'b0;
else if (CASDOMUXEN_B_in == 1'b1) CASDOMUXB_reg <= CASDOMUXB_in;
end
always @ (posedge CLKBWRCLK_in) begin
if (glblGSR || sdp_mode) CASOREGIMUXB_reg <= 1'b0;
else if (CASOREGIMUXEN_B_in == 1'b1) CASOREGIMUXB_reg <= CASOREGIMUXB_in;
end
// collison detection
reg coll_win_wr_clk_a_min = 1'b0;
reg coll_win_wr_clk_b_min = 1'b0;
reg coll_win_rd_clk_a_min = 1'b0;
reg coll_win_rd_clk_b_min = 1'b0;
reg coll_win_wr_clk_a_max = 1'b0;
reg coll_win_wr_clk_b_max = 1'b0;
reg coll_win_rd_clk_a_max = 1'b0;
reg coll_win_rd_clk_b_max = 1'b0;
reg wr_b_wr_a_coll = 1'b0;
reg wr_b_rd_a_coll = 1'b0;
reg rd_b_wr_a_coll = 1'b0;
reg wr_a_wr_b_coll = 1'b0;
reg wr_a_rd_b_coll = 1'b0;
reg rd_a_wr_b_coll = 1'b0;
wire coll_wr_sim;
wire coll_wr_b_wr_a;
wire coll_wr_b_rd_a_sim;
wire coll_wr_b_rd_a;
wire coll_rd_b_wr_a_sim;
wire coll_rd_b_wr_a;
wire coll_wr_a_wr_b;
wire coll_wr_a_rd_b_sim;
wire coll_wr_a_rd_b;
wire coll_rd_a_wr_b_sim;
wire coll_rd_a_wr_b;
assign coll_wr_sim = wr_addr_coll && coll_win_wr_clk_a_min && coll_win_wr_clk_b_min;
assign coll_wr_b_wr_a = wr_addr_coll && coll_win_wr_clk_b_min && ~coll_win_wr_clk_a_min && coll_win_wr_clk_a_max;
assign coll_wr_b_rd_a_sim = wr_b_rd_a_addr_coll && coll_win_wr_clk_b_min && coll_win_rd_clk_a_min;
assign coll_wr_b_rd_a = wr_b_rd_a_addr_coll && coll_win_wr_clk_b_min && ~coll_win_rd_clk_a_min && coll_win_rd_clk_a_max;
assign coll_rd_b_wr_a_sim = wr_a_rd_b_addr_coll && coll_win_rd_clk_b_min && coll_win_wr_clk_a_min;
assign coll_rd_b_wr_a = wr_a_rd_b_addr_coll && coll_win_rd_clk_b_min && ~coll_win_wr_clk_a_min && coll_win_wr_clk_a_max;
assign coll_wr_a_wr_b = wr_addr_coll && coll_win_wr_clk_a_min && ~coll_win_wr_clk_b_min && coll_win_wr_clk_b_max;
assign coll_wr_a_rd_b_sim = wr_a_rd_b_addr_coll && coll_win_wr_clk_a_min && coll_win_rd_clk_b_min;
assign coll_wr_a_rd_b = wr_a_rd_b_addr_coll && coll_win_wr_clk_a_min && ~coll_win_rd_clk_b_min && coll_win_rd_clk_b_max;
assign coll_rd_a_wr_b_sim = wr_b_rd_a_addr_coll && coll_win_rd_clk_a_min && coll_win_wr_clk_b_min;
assign coll_rd_a_wr_b = wr_b_rd_a_addr_coll && coll_win_rd_clk_a_min && ~coll_win_wr_clk_b_min && coll_win_wr_clk_b_max;
always @(posedge CLKARDCLK_in) begin
if (mem_wr_en_a === 1'b1 && ~glblGSR && clkb_toggled && (SIM_COLLISION_CHECK_BIN != SIM_COLLISION_CHECK_NONE) & ~sdp_mode) begin
coll_win_wr_clk_a_min <= 1'b1;
coll_win_wr_clk_a_max <= #99 1'b1;
coll_win_wr_clk_a_min <= #(t_coll_min) 1'b0;
coll_win_wr_clk_a_max <= #(t_coll_max) 1'b0;
end
end
always @(posedge coll_wr_sim) begin
if (~wr_data_matches) begin
if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_ALL) begin
$display("Error: [Unisim %s-1] Memory Collision at time %.3f ns.\nA simultaneous WRITE occured on port A (addr:%h data:%h) and port B (addr:%h data:%h).\nMemory contents at those locations have been corrupted. Instance: %m", MODULE_NAME, $time/1000.0, wr_addr_a, mem_wr_a, wr_addr_b, mem_wr_b);
wr_a_wr_b_coll <= #10 1'b1;
wr_a_wr_b_coll <= #100 1'b0;
end
else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_WARNING_ONLY)
$display("Error: [Unisim %s-2] Memory Collision at time %.3f ns.\nA simultaneous WRITE occured on port A (addr:%h data:%h) and port B (addr:%h data:%h). Instance: %m", MODULE_NAME, $time/1000.0, wr_addr_a, mem_wr_a, wr_addr_b, mem_wr_b);
else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_GENERATE_X_ONLY) begin
wr_a_wr_b_coll <= #10 1'b1;
wr_a_wr_b_coll <= #100 1'b0;
end
end
end
always @(posedge coll_wr_a_wr_b) begin
if (~wr_data_matches) begin
if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_ALL) begin
$display("Error: [Unisim %s-3] Memory Collision at time %.3f ns.\nA WRITE on port A (%h) occured during the WRITE window on port B (%h).\nMemory contents at those locations have been corrupted. Instance: %m", MODULE_NAME, $time/1000.0, wr_addr_a, wr_addr_b);
wr_a_wr_b_coll <= #10 1'b1;
wr_a_wr_b_coll <= #100 1'b0;
end
else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_WARNING_ONLY)
$display("Error: [Unisim %s-4] Memory Collision at time %.3f ns.\nA WRITE on port A (%h) occured during the WRITE window on port B (%h). Instance: %m", MODULE_NAME, $time/1000.0, wr_addr_a, wr_addr_b);
else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_GENERATE_X_ONLY) begin
wr_a_wr_b_coll <= #10 1'b1;
wr_a_wr_b_coll <= #100 1'b0;
end
end
end
always @(posedge coll_wr_a_rd_b_sim) begin
if (~wr_a_data_matches_rd_b_data && (WRITE_MODE_A_BIN != WRITE_MODE_A_READ_FIRST)) begin
if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_ALL) begin
$display("Error: [Unisim %s-5] Memory Collision at time %.3f ns.\nA simultaneous WRITE on port A (%h) occured during a READ on port B (%h).\nThe WRITE was successful but the READ may be corrupted. Instance: %m", MODULE_NAME, $time/1000.0, wr_addr_a, rd_addr_b);
wr_a_rd_b_coll <= #10 1'b1;
wr_a_rd_b_coll <= #100 1'b0;
end
else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_WARNING_ONLY)
$display("Error: [Unisim %s-6] Memory Collision at time %.3f ns.\nA simultaneous WRITE on port A (%h) occured during a READ on port B (%h). Instance: %m", MODULE_NAME, $time/1000.0, wr_addr_a, rd_addr_b);
else if (SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_GENERATE_X_ONLY) begin
wr_a_rd_b_coll <= #10 1'b1;
wr_a_rd_b_coll <= #100 1'b0;
end
end
end
always @(posedge coll_wr_a_rd_b) begin
if (~wr_a_data_matches_rd_b_data && (WRITE_MODE_A_BIN != WRITE_MODE_A_READ_FIRST)) begin
if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_ALL) begin
$display("Error: [Unisim %s-7] Memory Collision at time %.3f ns.\nA WRITE on port A (%h) occured during the READ window on port B (%h).\nThe WRITE was successful but the READ may be corrupted. Instance: %m", MODULE_NAME, $time/1000.0, wr_addr_a, rd_addr_b);
wr_a_rd_b_coll <= #10 1'b1;
wr_a_rd_b_coll <= #100 1'b0;
end
else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_WARNING_ONLY)
$display("Error: [Unisim %s-8] Memory Collision at time %.3f ns.\nA WRITE on port A (%h) occured during the READ window on port B (%h). Instance: %m", MODULE_NAME, $time/1000.0, wr_addr_a, rd_addr_b);
else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_GENERATE_X_ONLY) begin
wr_a_rd_b_coll <= #10 1'b1;
wr_a_rd_b_coll <= #100 1'b0;
end
end
end
always @(posedge CLKBWRCLK_in) begin
if (mem_wr_en_b === 1'b1 && ~glblGSR && clka_toggled && (SIM_COLLISION_CHECK_BIN != SIM_COLLISION_CHECK_NONE)) begin
coll_win_wr_clk_b_min <= 1'b1;
coll_win_wr_clk_b_max <= #99 1'b1;
coll_win_wr_clk_b_min <= #(t_coll_min) 1'b0;
coll_win_wr_clk_b_max <= #(t_coll_max) 1'b0;
end
end
always @(posedge coll_wr_b_wr_a) begin
if (~wr_data_matches) begin
if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_ALL) begin
$display("Error: [Unisim %s-9] Memory Collision at time %.3f ns.\nA WRITE on port B (%h) occured during the WRITE window on port A (%h).\nMemory contents at those locations have been corrupted. Instance: %m", MODULE_NAME, $time/1000.0, wr_addr_b, wr_addr_a);
wr_b_wr_a_coll <= #10 1'b1;
wr_b_wr_a_coll <= #100 1'b0;
end
else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_WARNING_ONLY)
$display("Error: [Unisim %s-10] Memory Collision at time %.3f ns.\nA WRITE on port B (%h) occured during the WRITE window on port A (%h). Instance: %m", MODULE_NAME, $time/1000.0, wr_addr_b, wr_addr_a);
else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_GENERATE_X_ONLY) begin
wr_b_wr_a_coll <= #10 1'b1;
wr_b_wr_a_coll <= #100 1'b0;
end
end
end
always @(posedge coll_wr_b_rd_a_sim) begin
if (~wr_b_data_matches_rd_a_data && (WRITE_MODE_B_BIN != WRITE_MODE_B_READ_FIRST)) begin
if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_ALL) begin
$display("Error: [Unisim %s-11] Memory Collision at time %.3f ns.\nA simultaneous WRITE on port B (%h) occured during a READ on port A (%h).\nThe WRITE was successful but the READ may be corrupted. Instance: %m", MODULE_NAME, $time/1000.0, wr_addr_b, rd_addr_a);
wr_b_rd_a_coll <= #10 1'b1;
wr_b_rd_a_coll <= #100 1'b0;
end
else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_WARNING_ONLY)
$display("Error: [Unisim %s-12] Memory Collision at time %.3f ns.\nA simultaneous WRITE on port B (%h) occured during a READ on port A (%h). Instance: %m", MODULE_NAME, $time/1000.0, wr_addr_b, rd_addr_a);
else if (SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_GENERATE_X_ONLY) begin
wr_b_rd_a_coll <= #10 1'b1;
wr_b_rd_a_coll <= #100 1'b0;
end
end
end
always @(posedge coll_wr_b_rd_a) begin
if (~wr_b_data_matches_rd_a_data && (WRITE_MODE_B_BIN != WRITE_MODE_B_READ_FIRST)) begin
if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_ALL) begin
$display("Error: [Unisim %s-13] Memory Collision at time %.3f ns.\nA WRITE on port B (%h) occured during the READ window on port A (%h).\nThe WRITE was successful but the READ may be corrupted. Instance: %m", MODULE_NAME, $time/1000.0, wr_addr_b, rd_addr_a);
wr_b_rd_a_coll <= #10 1'b1;
wr_b_rd_a_coll <= #100 1'b0;
end
else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_WARNING_ONLY)
$display("Error: [Unisim %s-14] Memory Collision at time %.3f ns.\nA WRITE on port B (%h) occured during the READ window on port A (%h). Instance: %m", MODULE_NAME, $time/1000.0, wr_addr_b, rd_addr_a);
else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_GENERATE_X_ONLY) begin
wr_b_rd_a_coll <= #10 1'b1;
wr_b_rd_a_coll <= #100 1'b0;
end
end
end
always @(posedge CLKARDCLK_in) begin
if (mem_rd_en_a === 1'b1 && ~glblGSR && clkb_toggled && (SIM_COLLISION_CHECK_BIN != SIM_COLLISION_CHECK_NONE)) begin
coll_win_rd_clk_a_min <= 1'b1;
coll_win_rd_clk_a_max <= #99 1'b1;
coll_win_rd_clk_a_min <= #(t_coll_min) 1'b0;
coll_win_rd_clk_a_max <= #(t_coll_max) 1'b0;
end
end
always @(posedge coll_rd_a_wr_b_sim) begin
if (~wr_b_data_matches_rd_a_data && (WRITE_MODE_B_BIN != WRITE_MODE_B_READ_FIRST)) begin
if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_ALL) begin
$display("Error: [Unisim %s-15] Memory Collision at time %.3f ns.\nA simultaneous READ on port A (%h) occured during a WRITE on port B (%h).\nThe WRITE was successful but the READ may be corrupted. Instance: %m", MODULE_NAME, $time/1000.0, rd_addr_a, wr_addr_b);
rd_a_wr_b_coll <= #10 1'b1;
rd_a_wr_b_coll <= #100 1'b0;
end
else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_WARNING_ONLY)
$display("Error: [Unisim %s-16] Memory Collision at time %.3f ns.\nA simultaneous READ on port A (%h) occured during a WRITE on port B (%h). Instance: %m", MODULE_NAME, $time/1000.0, rd_addr_a, wr_addr_b);
if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_GENERATE_X_ONLY) begin
rd_a_wr_b_coll <= #10 1'b1;
rd_a_wr_b_coll <= #100 1'b0;
end
end
end
always @(posedge coll_rd_a_wr_b) begin
if (~wr_b_data_matches_rd_a_data) begin
if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_ALL) begin
$display("Error: [Unisim %s-17] Memory Collision at time %.3f ns.\nA READ on port A (%h) occured during the WRITE window on port B (%h).\nThe WRITE was successful but the READ may be corrupted. Instance: %m", MODULE_NAME, $time/1000.0, rd_addr_a, wr_addr_b);
rd_a_wr_b_coll <= #10 1'b1;
rd_a_wr_b_coll <= #100 1'b0;
end
else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_WARNING_ONLY)
$display("Error: [Unisim %s-18] Memory Collision at time %.3f ns.\nA READ on port A (%h) occured during the WRITE window on port B (%h). Instance: %m", MODULE_NAME, $time/1000.0, rd_addr_a, wr_addr_b);
else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_GENERATE_X_ONLY) begin
rd_a_wr_b_coll <= #10 1'b1;
rd_a_wr_b_coll <= #100 1'b0;
end
end
end
always @(posedge CLKBWRCLK_in) begin
if (mem_rd_en_b === 1'b1 && ~glblGSR && clka_toggled && (SIM_COLLISION_CHECK_BIN != SIM_COLLISION_CHECK_NONE) && ~sdp_mode) begin
coll_win_rd_clk_b_min <= 1'b1;
coll_win_rd_clk_b_max <= #99 1'b1;
coll_win_rd_clk_b_min <= #(t_coll_min) 1'b0;
coll_win_rd_clk_b_max <= #(t_coll_max) 1'b0;
end
end
always @(posedge coll_rd_b_wr_a_sim) begin
if (~wr_a_data_matches_rd_b_data && (WRITE_MODE_A_BIN != WRITE_MODE_A_READ_FIRST)) begin
if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_ALL) begin
$display("Error: [Unisim %s-19] Memory Collision at time %.3f ns.\nA simultaneous READ on port B (%h) occured during a WRITE on port A (%h).\nThe WRITE was successful but the READ may be corrupted. Instance: %m", MODULE_NAME, $time/1000.0, rd_addr_b, wr_addr_a);
rd_b_wr_a_coll <= #10 1'b1;
rd_b_wr_a_coll <= #100 1'b0;
end
else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_WARNING_ONLY)
$display("Error: [Unisim %s-20] Memory Collision at time %.3f ns.\nA simultaneous READ on port B (%h) occured during a WRITE on port A (%h). Instance: %m", MODULE_NAME, $time/1000.0, rd_addr_b, wr_addr_a);
else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_GENERATE_X_ONLY) begin
rd_b_wr_a_coll <= #10 1'b1;
rd_b_wr_a_coll <= #100 1'b0;
end
end
end
always @(posedge coll_rd_b_wr_a) begin
if (~wr_a_data_matches_rd_b_data) begin
if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_ALL) begin
$display("Error: [Unisim %s-21] Memory Collision at time %.3f ns.\nA READ on port B (%h) occured during the WRITE window on port A (%h).\nThe WRITE was successful but the READ may be corrupted. Instance: %m", MODULE_NAME, $time/1000.0, rd_addr_b, wr_addr_a);
rd_b_wr_a_coll <= #10 1'b1;
rd_b_wr_a_coll <= #100 1'b0;
end
else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_WARNING_ONLY)
$display("Error: [Unisim %s-22] Memory Collision at time %.3f ns.\nA READ on port B (%h) occured during the WRITE window on port A (%h). Instance: %m", MODULE_NAME, $time/1000.0, rd_addr_b, wr_addr_a);
else if(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_GENERATE_X_ONLY) begin
rd_b_wr_a_coll <= #10 1'b1;
rd_b_wr_a_coll <= #100 1'b0;
end
end
end
// output register
always @ (*) begin
if (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE)) &&
CASOREGIMUXA_reg) mem_a_reg_mux = {CASDINB_in, CASDINA_in};
else if (mem_wr_en_a_wf) mem_a_reg_mux = mem_rd_a_wf;
else if (EN_ECC_PIPE_BIN == EN_ECC_PIPE_TRUE) mem_a_reg_mux = mem_a_pipe;
else mem_a_reg_mux = mem_a_lat;
end
always @ (*) begin
if (((CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_LAST) ||
(CASCADE_ORDER_A_BIN == CASCADE_ORDER_A_MIDDLE)) &&
CASOREGIMUXA_reg) memp_a_reg_mux = {CASDINPB_in, CASDINPA_in};
else if (mem_wr_en_a_wf) memp_a_reg_mux = memp_rd_a_wf;
else if (EN_ECC_PIPE_BIN == EN_ECC_PIPE_TRUE) memp_a_reg_mux = memp_a_pipe;
else memp_a_reg_mux = memp_a_lat;
end
always @ (posedge CLKARDCLK_in or posedge INIT_MEM or glblGSR) begin
if (glblGSR || INIT_MEM) begin
{memp_a_reg, mem_a_reg} <= INIT_A_int;
end
else if (RSTREG_A_int) begin
{memp_a_reg, mem_a_reg} <= SRVAL_A_int;
end
else if (REGCE_A_int) begin
mem_a_reg <= mem_a_reg_mux;
memp_a_reg <= memp_a_reg_mux;
end
end
always @ (*) begin
if (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST) ||
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE)) &&
CASOREGIMUXB_reg) mem_b_reg_mux = CASDINB_in;
else if (mem_wr_en_b_wf) mem_b_reg_mux = mem_rd_b_wf;
else mem_b_reg_mux = mem_b_lat;
end
always @ (*) begin
if (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST) ||
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE)) &&
CASOREGIMUXB_reg) memp_b_reg_mux = CASDINPB_in;
else if (mem_wr_en_b_wf) memp_b_reg_mux = memp_rd_b_wf;
else memp_b_reg_mux = memp_b_lat;
end
always @ (posedge CLKBWRCLK_in or posedge INIT_MEM or glblGSR) begin
if (glblGSR || INIT_MEM || sdp_mode) begin
{memp_b_reg, mem_b_reg} <= INIT_B_int;
end
else if (RSTREG_B_int) begin
{memp_b_reg, mem_b_reg} <= SRVAL_B_int;
end
else if (REGCE_B_int) begin
mem_b_reg <= mem_b_reg_mux;
memp_b_reg <= memp_b_reg_mux;
end
end
// bit err reg
always @ (posedge CLKARDCLK_in or glblGSR) begin
if (glblGSR || mem_rst_a) begin
dbit_reg <= 1'b0;
sbit_reg <= 1'b0;
r_a_ecc_reg <= 9'h0;
end
else if (REGCE_A_int) begin
dbit_reg <= dbit_ecc;
sbit_reg <= sbit_ecc;
r_a_ecc_reg <= r_a_ecc_ecc;
end
end
// ecc pipe register
always @ (posedge CLKARDCLK_in or posedge INIT_MEM or glblGSR) begin
if (glblGSR || INIT_MEM) begin
{memp_a_pipe, mem_a_pipe} <= INIT_A_int;
dbit_pipe <= 1'b0;
sbit_pipe <= 1'b0;
r_a_ecc_pipe <= 9'b0;
end
else if (WREN_ecc) begin
mem_a_pipe <= mem_a_lat;
memp_a_pipe <= memp_a_lat;
dbit_pipe <= dbit_lat;
sbit_pipe <= sbit_lat;
r_a_ecc_pipe <= r_a_ecc_lat;
end
end
// read engine
always @ (posedge CLKARDCLK_in) begin
if ((WRITE_MODE_A_BIN == WRITE_MODE_A_WRITE_FIRST) && ~sdp_mode && mem_rd_en_a && ~glblGSR) begin
mem_wr_en_a_wf <= mem_wr_en_a && ~mem_rst_a;
end
end
always @ (posedge CLKBWRCLK_in) begin
if ((WRITE_MODE_B_BIN == WRITE_MODE_B_WRITE_FIRST) && mem_rd_en_b && ~glblGSR) begin
mem_wr_en_b_wf <= mem_wr_en_b && ~mem_rst_b;
end
end
always @ (wr_a_wf_event or INIT_MEM) begin
if (~coll_rd_a_wr_b && ~coll_rd_a_wr_b_sim
&& ~coll_wr_b_rd_a && ~coll_wr_b_rd_a_sim) begin
for (raw=0;raw<rd_loops_f;raw=raw+1) begin
mem_rd_a_wf[raw] <= mem [rd_addr_a+raw];
end
if (rd_loops_f >= 8) begin
for (raw=0;raw<rd_loops_f/8;raw=raw+1) begin
memp_rd_a_wf[raw] <= memp [(rd_addr_a/8)+raw];
end
end
end
end
always @ (rd_addr_a or mem_rd_en_a or mem_rst_a or wr_a_event or wr_b_event or posedge coll_win_rd_clk_b_min or INIT_MEM) begin
if ((mem_rd_en_a || INIT_MEM) && ~mem_rst_a) begin
for (raa=0;raa<rd_loops_a;raa=raa+1) begin
ram_rd_a[raa] = mem [rd_addr_a+raa];
end
if (rd_loops_a >= 8) begin
for (raa=0;raa<rd_loops_a/8;raa=raa+1) begin
ramp_rd_a[raa] = memp [(rd_addr_a/8)+raa];
end
end
end
end
always @(posedge CLKARDCLK_in or posedge INIT_MEM or posedge glblGSR or posedge wr_b_rd_a_coll or posedge rd_a_wr_b_coll) begin
if (glblGSR || INIT_MEM) begin
for (ra=0;ra<rd_loops_a;ra=ra+1) begin
mem_a_lat[ra] <= INIT_A_int >> ra;
if (ra<rd_loops_a/8) begin
memp_a_lat[ra] <= INIT_A_int >> (D_WIDTH+ra);
end
end
first_read <= 1'b0;
end
else if (SLEEP_int && mem_rd_en_a) begin
$display("Error: [Unisim %s-23] DRC : READ on port A attempted while in SLEEP mode. Instance: %m.", MODULE_NAME);
for (ra=0;ra<rd_loops_a;ra=ra+1) begin
mem_a_lat[ra] <= 1'bx;
if (ra<rd_loops_a/8) begin
memp_a_lat[ra] <= 1'bx;
end
end
end
else if (mem_rst_a && mem_rd_en_a) begin
for (ra=0;ra<rd_loops_a;ra=ra+1) begin
mem_a_lat[ra] <= SRVAL_A_int >> ra;
if (ra<rd_loops_a/8) begin
memp_a_lat[ra] <= SRVAL_A_int >> (D_WIDTH+ra);
end
end
end
else if (rd_a_wr_b_coll) begin
if (~wr_b_data_matches_rd_a_data &&
((SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_ALL) ||
(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_GENERATE_X_ONLY))) begin
for (ra=0;ra<rd_loops_a;ra=ra+1) begin
mem_a_lat[ra] <= 1'bx;
if (ra<rd_loops_a/8) begin
memp_a_lat[ra] <= 1'bx;
end
end
end
end
else if (wr_b_rd_a_coll) begin
if ((WRITE_MODE_B_BIN != WRITE_MODE_B_READ_FIRST) && ~wr_b_data_matches_rd_a_data &&
((SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_ALL) ||
(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_GENERATE_X_ONLY))) begin
for (ra=0;ra<rd_loops_a;ra=ra+1) begin
mem_a_lat[ra] <= 1'bx;
if (ra<rd_loops_a/8) begin
memp_a_lat[ra] <= 1'bx;
end
end
end
end
else if (mem_rd_en_a) begin
if ((EN_ECC_READ_BIN == EN_ECC_READ_TRUE) && sbit_int) begin
if (wr_b_rd_a_addr_coll && coll_win_wr_clk_b_min && sdp_mode && (WRITE_MODE_B_BIN == WRITE_MODE_B_READ_FIRST)) begin
{memp_a_lat, mem_a_lat} <= fn_cor_bit(synd_ecc[6:0], mem_rd_b_rf, memp_rd_b_rf);
end
else begin
{memp_a_lat, mem_a_lat} <= fn_cor_bit(synd_ecc[6:0], ram_rd_a, ramp_rd_a);
end
end
else begin
if (wr_b_rd_a_addr_coll && coll_win_wr_clk_b_min && sdp_mode && (WRITE_MODE_B_BIN == WRITE_MODE_B_READ_FIRST)) begin
mem_a_lat <= mem_rd_b_rf;
memp_a_lat <= memp_rd_b_rf;
end
else begin
mem_a_lat <= ram_rd_a;
memp_a_lat <= ramp_rd_a;
end
end
first_read <= 1'b1;
end
end
always @ (wr_b_wf_event) begin
if (~(coll_rd_b_wr_a || coll_rd_b_wr_a_sim || coll_wr_a_rd_b || coll_wr_a_rd_b_sim)) begin
// for (rbw=0;rbw<max_rd_loops;rbw=rbw+1) begin
for (rbw=0;rbw<rd_loops_f;rbw=rbw+1) begin
mem_rd_b_wf[rbw] <= mem [rd_addr_b+rbw];
// if (rbw<max_rd_loops/8) begin
if (rbw<rd_loops_f/8) begin
memp_rd_b_wf[rbw] <= memp [(rd_addr_b/8)+rbw];
end
end
end
end
always @ (rd_addr_b or mem_rd_en_b or mem_rst_b or wr_b_event or wr_a_event or INIT_MEM) begin
if ((mem_rd_en_b || INIT_MEM) && ~mem_rst_b) begin
for (rbb=0;rbb<rd_loops_b;rbb=rbb+1) begin
mem_rd_b[rbb] <= mem [rd_addr_b+rbb];
if (rbb<rd_loops_b/8) begin
memp_rd_b[rbb] <= memp [(rd_addr_b/8)+rbb];
end
end
end
end
always @(posedge CLKBWRCLK_in or posedge INIT_MEM or posedge glblGSR or posedge wr_a_rd_b_coll or posedge rd_b_wr_a_coll) begin
if (glblGSR || INIT_MEM) begin
for (rb=0;rb<rd_loops_b;rb=rb+1) begin
mem_b_lat[rb] <= INIT_B_int >> rb;
if (rb<rd_loops_b/8) begin
memp_b_lat[rb] <= INIT_B_int >> (D_WIDTH/2+rb);
end
end
end
else if (SLEEP_int && mem_rd_en_b && ~sdp_mode) begin
$display("Error: [Unisim %s-24] DRC : READ on port B attempted while in SLEEP mode. Instance: %m.", MODULE_NAME);
for (rb=0;rb<rd_loops_b;rb=rb+1) begin
mem_b_lat[rb] <= 1'bx;
if (rb<rd_loops_b/8) begin
memp_b_lat[rb] <= 1'bx;
end
end
end
else if (mem_rst_b && mem_rd_en_b && ~sdp_mode) begin
for (rb=0;rb<rd_loops_b;rb=rb+1) begin
mem_b_lat[rb] <= SRVAL_B_int >> rb;
if (rb<rd_loops_b/8) begin
memp_b_lat[rb] <= SRVAL_B_int >> (D_WIDTH/2+rb);
end
end
end
else if (rd_b_wr_a_coll) begin
if (~wr_a_data_matches_rd_b_data &&
((SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_ALL) ||
(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_GENERATE_X_ONLY))) begin
for (rb=0;rb<rd_loops_b;rb=rb+1) begin
mem_b_lat[rb] <= 1'bx;
if (rb<rd_loops_b/8) begin
memp_b_lat[rb] <= 1'bx;
end
end
end
end
else if (wr_a_rd_b_coll) begin
if ((WRITE_MODE_A_BIN != WRITE_MODE_A_READ_FIRST) && ~wr_a_data_matches_rd_b_data &&
((SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_ALL) ||
(SIM_COLLISION_CHECK_BIN == SIM_COLLISION_CHECK_GENERATE_X_ONLY))) begin
for (rb=0;rb<rd_loops_b;rb=rb+1) begin
mem_b_lat[rb] <= 1'bx;
if (rb<rd_loops_b/8) begin
memp_b_lat[rb] <= 1'bx;
end
end
end
end
else if (mem_rd_en_b && ~sdp_mode) begin
mem_b_lat <= mem_rd_b[D_WIDTH/2-1:0];
memp_b_lat <= memp_rd_b[DP_WIDTH/2-1:0];
end
end
// write engine
always @ (posedge CLKARDCLK_in or posedge wr_a_wr_b_coll) begin
if (wr_a_wr_b_coll && ~glblGSR) begin
if (~wr_data_matches) begin
for (wa=0;wa<wr_loops_a;wa=wa+1) begin
if (mem_we_a[wa]) mem [wr_addr_a+wa] <= {mem_width{1'bx}};
if (wa<wr_loops_a/8) begin
if (memp_we_a[wa]) memp [(wr_addr_a/8)+wa] <= {memp_width{1'bx}};
end
end
end
end
else if (mem_wr_en_a && ~glblGSR && ~sdp_mode) begin
if (SLEEP_int) begin
$display("Error: [Unisim %s-25] DRC : WRITE on port A attempted while in SLEEP mode. Instance: %m.", MODULE_NAME);
end
else begin
for (wa=0;wa<wr_loops_a;wa=wa+1) begin
if (mem_we_a[wa]) begin
mem [wr_addr_a+wa] <= mem_wr_a[wa];
end
end
if (wr_loops_a >= 8) begin
for (wa=0;wa<wr_loops_a/8;wa=wa+1) begin
if (memp_we_a[wa]) begin
memp [(wr_addr_a/8)+wa] <= memp_wr_a[wa];
end
end
end
wr_a_event <= ~wr_a_event;
if (WRITE_MODE_A_BIN == WRITE_MODE_A_WRITE_FIRST) wr_a_wf_event <= ~wr_a_wf_event;
end
end
end
always @ (posedge CLKBWRCLK_in or posedge INIT_MEM or posedge wr_b_wr_a_coll) begin
if (INIT_MEM == 1'b1) begin
// initialize memory
for (j=0;j<128;j=j+1) begin
INIT_TMP = INIT_BIN[j];
for (i=0;i<256;i=i+1) begin
mem [j*256+i] <= INIT_TMP[i];
end
end
// initialize memory p
for (j=0;j<16;j=j+1) begin
INITP_TMP = INITP_BIN[j];
for (i=0;i<256;i=i+1) begin
memp [j*256+i] <= INITP_TMP[i];
end
end
end
else if (wr_b_wr_a_coll && ~glblGSR) begin
if (~wr_data_matches) begin
for (wb=0;wb<wr_loops_b;wb=wb+1) begin
if (mem_we_b[wb]) mem [wr_addr_b+wb] <= {mem_width{1'bx}};
if (wb<wr_loops_b/8) begin
if (memp_we_b[wb]) memp [(wr_addr_b/8)+wb] <= {memp_width{1'bx}};
end
end
end
end
else if (mem_wr_en_b && ~glblGSR) begin
if (SLEEP_int) begin
$display("Error: [Unisim %s-26] DRC : WRITE on port A attempted while in SLEEP mode. Instance %m.", MODULE_NAME);
end
else begin
// for (wb=0;wb<max_rd_loops;wb=wb+1) begin
for (wb=0;wb<rd_loops_f;wb=wb+1) begin
mem_rd_b_rf[wb] <= mem [rd_addr_b+wb];
// if (wb<max_rd_loops/8) begin
if (wb<rd_loops_f/8) begin
memp_rd_b_rf[wb] <= memp [rd_addr_b/8+wb];
end
end
for (wb=0;wb<wr_loops_b;wb=wb+1) begin
if (mem_we_b[wb]) begin
mem [wr_addr_b+wb] <= mem_wr_b[wb];
end
end
if (WRITE_WIDTH_B_BIN > WRITE_WIDTH_B_4) begin
for (wb=0;wb<wr_loops_b/8;wb=wb+1) begin
if (memp_we_b[wb]) begin
memp [(wr_addr_b/8)+wb] <= memp_wr_b[wb];
end
end
end
wr_b_event <= ~wr_b_event;
if (WRITE_MODE_B_BIN == WRITE_MODE_B_WRITE_FIRST) wr_b_wf_event <= ~wr_b_wf_event;
end
end
end
assign mem_rm_douta = sdp_mode_rd ? {D_WIDTH{1'b0}} : {D_WIDTH{1'bx}}<<rd_loops_a;
assign memp_rm_douta = sdp_mode_rd ? {DP_WIDTH{1'b0}} : {DP_WIDTH{1'bx}}<<rd_loops_a/8;
assign mem_rm_doutb = sdp_mode_rd ? {D_WIDTH/2{1'b0}} : {D_WIDTH{1'bx}}<<rd_loops_b;
assign memp_rm_doutb = sdp_mode_rd ? {DP_WIDTH/2{1'b0}} : {DP_WIDTH/2{1'bx}}<<rd_loops_b/8;
always @(ADDRARDADDR_in or CLKARDCLK_in or ADDRENA_int or coll_win_rd_clk_a_max or coll_win_wr_clk_a_max) begin
if (CLKARDCLK_in == 1'b0 && ADDRENA_int == 1'b1) begin
if (coll_win_rd_clk_a_max == 1'b0) rd_addr_a = ADDRARDADDR_in & rd_addr_a_mask;
if (coll_win_wr_clk_a_max == 1'b0) wr_addr_a = ADDRARDADDR_in & wr_addr_a_mask;
end
end
always @(ADDRBWRADDR_in or ADDRARDADDR_in or CLKBWRCLK_in or ADDRENB_int or coll_win_rd_clk_b_max or coll_win_wr_clk_b_max) begin
if (CLKBWRCLK_in == 1'b0 && ADDRENB_int == 1'b1) begin
if (sdp_mode == 1'b1) begin
if (coll_win_rd_clk_b_max == 1'b0) rd_addr_b = ADDRARDADDR_in & rd_addr_a_mask;
end
else begin
if (coll_win_rd_clk_b_max == 1'b0) rd_addr_b = ADDRBWRADDR_in & rd_addr_b_mask;
end
if (coll_win_wr_clk_b_max == 1'b0) wr_addr_b = ADDRBWRADDR_in & wr_addr_b_mask;
end
end
assign mem_rm_a = {D_WIDTH{1'b1}}>>(max_rd_loops-rd_loops_a);
assign mem_rm_b = {D_WIDTH{1'b1}}>>(max_rd_loops-rd_loops_b);
assign mem_wm_a = {D_WIDTH{1'b1}}>>(max_wr_loops-wr_loops_a);
assign mem_wm_b = {D_WIDTH{1'b1}}>>(max_wr_loops-wr_loops_b);
always @(*) begin
if (~sdp_mode && mem_wr_en_a && mem_rd_en_b && ~mem_wr_en_b && (SIM_COLLISION_CHECK_BIN != SIM_COLLISION_CHECK_NONE)) begin
if ((wr_addr_a & rd_addr_b_mask) == (rd_addr_b & wr_addr_a_mask)) wr_a_rd_b_addr_coll = 1'b1;
else wr_a_rd_b_addr_coll = 1'b0;
end
else wr_a_rd_b_addr_coll = 1'b0;
end
always @(*) begin
if (~sdp_mode && mem_wr_en_b && mem_wr_en_a && (SIM_COLLISION_CHECK_BIN != SIM_COLLISION_CHECK_NONE)) begin
if ((wr_addr_a & wr_addr_b_mask) == (wr_addr_b & wr_addr_a_mask)) wr_addr_coll = 1'b1;
else wr_addr_coll = 1'b0;
end
else wr_addr_coll = 1'b0;
end
always @(*) begin
if (mem_wr_en_b && mem_rd_en_a && ~mem_wr_en_a && (SIM_COLLISION_CHECK_BIN != SIM_COLLISION_CHECK_NONE)) begin
if ((wr_addr_b & rd_addr_a_mask) == (rd_addr_a & wr_addr_b_mask)) wr_b_rd_a_addr_coll = 1'b1;
else wr_b_rd_a_addr_coll = 1'b0;
end
else wr_b_rd_a_addr_coll = 1'b0;
end
always @ (WEA_in or glblGSR) begin
mem_we_a = {{8{WEA_in[3]}},{8{WEA_in[2]}},{8{WEA_in[1]}},{8{WEA_in[0]}}};
if (WRITE_WIDTH_A_BIN > WRITE_WIDTH_A_4) memp_we_a = WEA_in;
else memp_we_a = 4'b0;
end
always @ (WEBWE_in or glblGSR) begin
mem_we_b = {{8{WEBWE_in[7]}},{8{WEBWE_in[6]}},{8{WEBWE_in[5]}},{8{WEBWE_in[4]}},
{8{WEBWE_in[3]}},{8{WEBWE_in[2]}},{8{WEBWE_in[1]}},{8{WEBWE_in[0]}}};
if (WRITE_WIDTH_B_BIN > WRITE_WIDTH_B_4) memp_we_b = WEBWE_in;
else memp_we_b = 8'b0;
end
// eccparity is flopped
always @ (*) begin
if (EN_ECC_WRITE_BIN == EN_ECC_WRITE_FALSE) synd_wr = 8'b0;
else begin
if (((CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_LAST) ||
(CASCADE_ORDER_B_BIN == CASCADE_ORDER_B_MIDDLE)) && CASDIMUXB_in)
synd_wr = fn_ecc(encode, {CASDINB_in, CASDINA_in}, {CASDINPB_in, CASDINPA_in});
else
synd_wr = fn_ecc(encode, {DINBDIN_in, DINADIN_in}, {DINPBDINP_in, DINPADINP_in});
end
end
always @ (*) begin
if (EN_ECC_READ_BIN == EN_ECC_READ_TRUE) begin
if (wr_b_rd_a_addr_coll && coll_win_wr_clk_b_min && sdp_mode && (WRITE_MODE_B_BIN == WRITE_MODE_B_READ_FIRST))
synd_rd = fn_ecc(decode, mem_rd_b_rf, memp_rd_b_rf);
else
synd_rd = fn_ecc(decode, ram_rd_a, ramp_rd_a);
end
else synd_rd = 8'b0;
end
always @ (*) begin
if (EN_ECC_READ_BIN == EN_ECC_READ_TRUE) begin
if (wr_b_rd_a_addr_coll && coll_win_wr_clk_b_min && sdp_mode && (WRITE_MODE_B_BIN == WRITE_MODE_B_READ_FIRST))
synd_ecc = synd_rd ^ memp_rd_b_rf;
else
synd_ecc = synd_rd ^ ramp_rd_a;
end
else synd_ecc = 8'b0;
end
assign sbit_int = (|synd_ecc && synd_ecc[7]);
assign dbit_int = (|synd_ecc && ~synd_ecc[7]);
always @(posedge CLKARDCLK_in) begin
if (mem_rd_en_a && mem_rst_a) begin
sbit_lat <= 1'b0;
dbit_lat <= 1'b0;
error_bit <= 7'b0;
r_a_ecc_lat <= 9'b0;
end
else if (mem_rd_en_a && (EN_ECC_READ_BIN == EN_ECC_READ_TRUE)) begin
sbit_lat <= sbit_int;
dbit_lat <= dbit_int;
error_bit <= synd_ecc[6:0];
r_a_ecc_lat <= rd_addr_a[ADDR_WIDTH-1:ADDR_WIDTH-9];
end
end
// assign {memp_a_ecc_cor, mem_a_ecc_cor} = sbit_int ?
// fn_cor_bit(synd_ecc[6:0], mem_rd_a, memp_rd_a) :
// {memp_rd_a, mem_rd_a};
always @ (posedge CLKBWRCLK_in or glblGSR) begin
if(glblGSR || (EN_ECC_WRITE_BIN == EN_ECC_WRITE_FALSE))
eccparity_reg <= 8'h00;
else if (ENBWREN_in)
eccparity_reg <= synd_wr;
end
specify
(CASDINA *> CASDOUTA) = (0:0:0, 0:0:0);
(CASDINA *> DOUTADOUT) = (0:0:0, 0:0:0);
(CASDINB *> CASDOUTB) = (0:0:0, 0:0:0);
(CASDINB *> DOUTBDOUT) = (0:0:0, 0:0:0);
(CASDINPA *> CASDOUTPA) = (0:0:0, 0:0:0);
(CASDINPA *> DOUTPADOUTP) = (0:0:0, 0:0:0);
(CASDINPB *> CASDOUTPB) = (0:0:0, 0:0:0);
(CASDINPB *> DOUTPBDOUTP) = (0:0:0, 0:0:0);
(CASINDBITERR => CASOUTDBITERR) = (0:0:0, 0:0:0);
(CASINDBITERR => DBITERR) = (0:0:0, 0:0:0);
(CASINSBITERR => CASOUTSBITERR) = (0:0:0, 0:0:0);
(CASINSBITERR => SBITERR) = (0:0:0, 0:0:0);
(CLKARDCLK *> CASDOUTA) = (0:0:0, 0:0:0);
(CLKARDCLK *> CASDOUTB) = (0:0:0, 0:0:0);
(CLKARDCLK *> CASDOUTPA) = (0:0:0, 0:0:0);
(CLKARDCLK *> CASDOUTPB) = (0:0:0, 0:0:0);
(CLKARDCLK *> DOUTADOUT) = (0:0:0, 0:0:0);
(CLKARDCLK *> DOUTBDOUT) = (0:0:0, 0:0:0);
(CLKARDCLK *> DOUTPADOUTP) = (0:0:0, 0:0:0);
(CLKARDCLK *> DOUTPBDOUTP) = (0:0:0, 0:0:0);
(CLKARDCLK *> RDADDRECC) = (0:0:0, 0:0:0);
(CLKARDCLK => CASOUTDBITERR) = (0:0:0, 0:0:0);
(CLKARDCLK => CASOUTSBITERR) = (0:0:0, 0:0:0);
(CLKARDCLK => DBITERR) = (0:0:0, 0:0:0);
(CLKARDCLK => SBITERR) = (0:0:0, 0:0:0);
(CLKBWRCLK *> CASDOUTB) = (0:0:0, 0:0:0);
(CLKBWRCLK *> CASDOUTPB) = (0:0:0, 0:0:0);
(CLKBWRCLK *> DOUTBDOUT) = (0:0:0, 0:0:0);
(CLKBWRCLK *> DOUTPBDOUTP) = (0:0:0, 0:0:0);
(CLKBWRCLK *> ECCPARITY) = (0:0:0, 0:0:0);
`ifdef XIL_TIMING
$period (negedge CLKARDCLK, 0:0:0, notifier);
$period (negedge CLKBWRCLK, 0:0:0, notifier);
$period (posedge CLKARDCLK, 0:0:0, notifier);
$period (posedge CLKBWRCLK, 0:0:0, notifier);
$setuphold (negedge CLKARDCLK, negedge ADDRARDADDR, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, ADDRARDADDR_delay);
$setuphold (negedge CLKARDCLK, negedge ADDRBWRADDR, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, ADDRBWRADDR_delay);
$setuphold (negedge CLKARDCLK, negedge ADDRENA, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, ADDRENA_delay);
$setuphold (negedge CLKARDCLK, negedge ADDRENB, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, ADDRENB_delay);
$setuphold (negedge CLKARDCLK, negedge CASDIMUXA, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDIMUXA_delay);
$setuphold (negedge CLKARDCLK, negedge CASDIMUXB, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDIMUXB_delay);
$setuphold (negedge CLKARDCLK, negedge CASDINA, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDINA_delay);
$setuphold (negedge CLKARDCLK, negedge CASDINB, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDINB_delay);
$setuphold (negedge CLKARDCLK, negedge CASDINPA, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDINPA_delay);
$setuphold (negedge CLKARDCLK, negedge CASDINPB, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDINPB_delay);
$setuphold (negedge CLKARDCLK, negedge CASDOMUXA, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDOMUXA_delay);
$setuphold (negedge CLKARDCLK, negedge CASDOMUXB, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDOMUXB_delay);
$setuphold (negedge CLKARDCLK, negedge CASDOMUXEN_A, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDOMUXEN_A_delay);
$setuphold (negedge CLKARDCLK, negedge CASDOMUXEN_B, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDOMUXEN_B_delay);
$setuphold (negedge CLKARDCLK, negedge CASINDBITERR, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASINDBITERR_delay);
$setuphold (negedge CLKARDCLK, negedge CASINSBITERR, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASINSBITERR_delay);
$setuphold (negedge CLKARDCLK, negedge CASOREGIMUXA, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASOREGIMUXA_delay);
$setuphold (negedge CLKARDCLK, negedge CASOREGIMUXB, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASOREGIMUXB_delay);
$setuphold (negedge CLKARDCLK, negedge CASOREGIMUXEN_A, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASOREGIMUXEN_A_delay);
$setuphold (negedge CLKARDCLK, negedge CASOREGIMUXEN_B, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASOREGIMUXEN_B_delay);
$setuphold (negedge CLKARDCLK, negedge DINADIN, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, DINADIN_delay);
$setuphold (negedge CLKARDCLK, negedge DINBDIN, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, DINBDIN_delay);
$setuphold (negedge CLKARDCLK, negedge DINPADINP, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, DINPADINP_delay);
$setuphold (negedge CLKARDCLK, negedge ECCPIPECE, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, ECCPIPECE_delay);
$setuphold (negedge CLKARDCLK, negedge ENARDEN, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, ENARDEN_delay);
$setuphold (negedge CLKARDCLK, negedge ENBWREN, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, ENBWREN_delay);
$setuphold (negedge CLKARDCLK, negedge INJECTDBITERR, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, INJECTDBITERR_delay);
$setuphold (negedge CLKARDCLK, negedge INJECTSBITERR, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, INJECTSBITERR_delay);
$setuphold (negedge CLKARDCLK, negedge REGCEAREGCE, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, REGCEAREGCE_delay);
$setuphold (negedge CLKARDCLK, negedge REGCEB, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, REGCEB_delay);
$setuphold (negedge CLKARDCLK, negedge RSTRAMARSTRAM, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, RSTRAMARSTRAM_delay);
$setuphold (negedge CLKARDCLK, negedge RSTRAMB, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, RSTRAMB_delay);
$setuphold (negedge CLKARDCLK, negedge RSTREGARSTREG, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, RSTREGARSTREG_delay);
$setuphold (negedge CLKARDCLK, negedge RSTREGB, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, RSTREGB_delay);
$setuphold (negedge CLKARDCLK, negedge SLEEP, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, SLEEP_delay);
$setuphold (negedge CLKARDCLK, negedge WEA, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, WEA_delay);
$setuphold (negedge CLKARDCLK, negedge WEBWE, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, WEBWE_delay);
$setuphold (negedge CLKARDCLK, posedge ADDRARDADDR, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, ADDRARDADDR_delay);
$setuphold (negedge CLKARDCLK, posedge ADDRBWRADDR, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, ADDRBWRADDR_delay);
$setuphold (negedge CLKARDCLK, posedge ADDRENA, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, ADDRENA_delay);
$setuphold (negedge CLKARDCLK, posedge ADDRENB, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, ADDRENB_delay);
$setuphold (negedge CLKARDCLK, posedge CASDIMUXA, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDIMUXA_delay);
$setuphold (negedge CLKARDCLK, posedge CASDIMUXB, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDIMUXB_delay);
$setuphold (negedge CLKARDCLK, posedge CASDINA, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDINA_delay);
$setuphold (negedge CLKARDCLK, posedge CASDINB, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDINB_delay);
$setuphold (negedge CLKARDCLK, posedge CASDINPA, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDINPA_delay);
$setuphold (negedge CLKARDCLK, posedge CASDINPB, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDINPB_delay);
$setuphold (negedge CLKARDCLK, posedge CASDOMUXA, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDOMUXA_delay);
$setuphold (negedge CLKARDCLK, posedge CASDOMUXB, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDOMUXB_delay);
$setuphold (negedge CLKARDCLK, posedge CASDOMUXEN_A, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDOMUXEN_A_delay);
$setuphold (negedge CLKARDCLK, posedge CASDOMUXEN_B, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDOMUXEN_B_delay);
$setuphold (negedge CLKARDCLK, posedge CASINDBITERR, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASINDBITERR_delay);
$setuphold (negedge CLKARDCLK, posedge CASINSBITERR, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASINSBITERR_delay);
$setuphold (negedge CLKARDCLK, posedge CASOREGIMUXA, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASOREGIMUXA_delay);
$setuphold (negedge CLKARDCLK, posedge CASOREGIMUXB, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASOREGIMUXB_delay);
$setuphold (negedge CLKARDCLK, posedge CASOREGIMUXEN_A, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASOREGIMUXEN_A_delay);
$setuphold (negedge CLKARDCLK, posedge CASOREGIMUXEN_B, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASOREGIMUXEN_B_delay);
$setuphold (negedge CLKARDCLK, posedge DINADIN, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, DINADIN_delay);
$setuphold (negedge CLKARDCLK, posedge DINBDIN, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, DINBDIN_delay);
$setuphold (negedge CLKARDCLK, posedge DINPADINP, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, DINPADINP_delay);
$setuphold (negedge CLKARDCLK, posedge ECCPIPECE, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, ECCPIPECE_delay);
$setuphold (negedge CLKARDCLK, posedge ENARDEN, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, ENARDEN_delay);
$setuphold (negedge CLKARDCLK, posedge ENBWREN, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, ENBWREN_delay);
$setuphold (negedge CLKARDCLK, posedge INJECTDBITERR, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, INJECTDBITERR_delay);
$setuphold (negedge CLKARDCLK, posedge INJECTSBITERR, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, INJECTSBITERR_delay);
$setuphold (negedge CLKARDCLK, posedge REGCEAREGCE, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, REGCEAREGCE_delay);
$setuphold (negedge CLKARDCLK, posedge REGCEB, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, REGCEB_delay);
$setuphold (negedge CLKARDCLK, posedge RSTRAMARSTRAM, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, RSTRAMARSTRAM_delay);
$setuphold (negedge CLKARDCLK, posedge RSTRAMB, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, RSTRAMB_delay);
$setuphold (negedge CLKARDCLK, posedge RSTREGARSTREG, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, RSTREGARSTREG_delay);
$setuphold (negedge CLKARDCLK, posedge RSTREGB, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, RSTREGB_delay);
$setuphold (negedge CLKARDCLK, posedge SLEEP, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, SLEEP_delay);
$setuphold (negedge CLKARDCLK, posedge WEA, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, WEA_delay);
$setuphold (negedge CLKARDCLK, posedge WEBWE, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, WEBWE_delay);
$setuphold (negedge CLKBWRCLK, negedge ADDRARDADDR, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, ADDRARDADDR_delay);
$setuphold (negedge CLKBWRCLK, negedge ADDRBWRADDR, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, ADDRBWRADDR_delay);
$setuphold (negedge CLKBWRCLK, negedge ADDRENA, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, ADDRENA_delay);
$setuphold (negedge CLKBWRCLK, negedge ADDRENB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, ADDRENB_delay);
$setuphold (negedge CLKBWRCLK, negedge CASDIMUXA, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDIMUXA_delay);
$setuphold (negedge CLKBWRCLK, negedge CASDIMUXB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDIMUXB_delay);
$setuphold (negedge CLKBWRCLK, negedge CASDINA, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDINA_delay);
$setuphold (negedge CLKBWRCLK, negedge CASDINB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDINB_delay);
$setuphold (negedge CLKBWRCLK, negedge CASDINPA, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDINPA_delay);
$setuphold (negedge CLKBWRCLK, negedge CASDINPB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDINPB_delay);
$setuphold (negedge CLKBWRCLK, negedge CASDOMUXA, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDOMUXA_delay);
$setuphold (negedge CLKBWRCLK, negedge CASDOMUXB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDOMUXB_delay);
$setuphold (negedge CLKBWRCLK, negedge CASDOMUXEN_A, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDOMUXEN_A_delay);
$setuphold (negedge CLKBWRCLK, negedge CASDOMUXEN_B, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDOMUXEN_B_delay);
$setuphold (negedge CLKBWRCLK, negedge CASOREGIMUXA, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASOREGIMUXA_delay);
$setuphold (negedge CLKBWRCLK, negedge CASOREGIMUXB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASOREGIMUXB_delay);
$setuphold (negedge CLKBWRCLK, negedge CASOREGIMUXEN_A, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASOREGIMUXEN_A_delay);
$setuphold (negedge CLKBWRCLK, negedge CASOREGIMUXEN_B, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASOREGIMUXEN_B_delay);
$setuphold (negedge CLKBWRCLK, negedge DINADIN, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, DINADIN_delay);
$setuphold (negedge CLKBWRCLK, negedge DINBDIN, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, DINBDIN_delay);
$setuphold (negedge CLKBWRCLK, negedge DINPADINP, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, DINPADINP_delay);
$setuphold (negedge CLKBWRCLK, negedge DINPBDINP, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, DINPBDINP_delay);
$setuphold (negedge CLKBWRCLK, negedge ENARDEN, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, ENARDEN_delay);
$setuphold (negedge CLKBWRCLK, negedge ENBWREN, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, ENBWREN_delay);
$setuphold (negedge CLKBWRCLK, negedge INJECTDBITERR, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, INJECTDBITERR_delay);
$setuphold (negedge CLKBWRCLK, negedge INJECTSBITERR, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, INJECTSBITERR_delay);
$setuphold (negedge CLKBWRCLK, negedge REGCEAREGCE, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, REGCEAREGCE_delay);
$setuphold (negedge CLKBWRCLK, negedge REGCEB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, REGCEB_delay);
$setuphold (negedge CLKBWRCLK, negedge RSTRAMARSTRAM, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, RSTRAMARSTRAM_delay);
$setuphold (negedge CLKBWRCLK, negedge RSTRAMB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, RSTRAMB_delay);
$setuphold (negedge CLKBWRCLK, negedge RSTREGARSTREG, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, RSTREGARSTREG_delay);
$setuphold (negedge CLKBWRCLK, negedge RSTREGB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, RSTREGB_delay);
$setuphold (negedge CLKBWRCLK, negedge WEA, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, WEA_delay);
$setuphold (negedge CLKBWRCLK, negedge WEBWE, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, WEBWE_delay);
$setuphold (negedge CLKBWRCLK, posedge ADDRARDADDR, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, ADDRARDADDR_delay);
$setuphold (negedge CLKBWRCLK, posedge ADDRBWRADDR, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, ADDRBWRADDR_delay);
$setuphold (negedge CLKBWRCLK, posedge ADDRENA, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, ADDRENA_delay);
$setuphold (negedge CLKBWRCLK, posedge ADDRENB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, ADDRENB_delay);
$setuphold (negedge CLKBWRCLK, posedge CASDIMUXA, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDIMUXA_delay);
$setuphold (negedge CLKBWRCLK, posedge CASDIMUXB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDIMUXB_delay);
$setuphold (negedge CLKBWRCLK, posedge CASDINA, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDINA_delay);
$setuphold (negedge CLKBWRCLK, posedge CASDINB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDINB_delay);
$setuphold (negedge CLKBWRCLK, posedge CASDINPA, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDINPA_delay);
$setuphold (negedge CLKBWRCLK, posedge CASDINPB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDINPB_delay);
$setuphold (negedge CLKBWRCLK, posedge CASDOMUXA, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDOMUXA_delay);
$setuphold (negedge CLKBWRCLK, posedge CASDOMUXB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDOMUXB_delay);
$setuphold (negedge CLKBWRCLK, posedge CASDOMUXEN_A, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDOMUXEN_A_delay);
$setuphold (negedge CLKBWRCLK, posedge CASDOMUXEN_B, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDOMUXEN_B_delay);
$setuphold (negedge CLKBWRCLK, posedge CASOREGIMUXA, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASOREGIMUXA_delay);
$setuphold (negedge CLKBWRCLK, posedge CASOREGIMUXB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASOREGIMUXB_delay);
$setuphold (negedge CLKBWRCLK, posedge CASOREGIMUXEN_A, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASOREGIMUXEN_A_delay);
$setuphold (negedge CLKBWRCLK, posedge CASOREGIMUXEN_B, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASOREGIMUXEN_B_delay);
$setuphold (negedge CLKBWRCLK, posedge DINADIN, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, DINADIN_delay);
$setuphold (negedge CLKBWRCLK, posedge DINBDIN, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, DINBDIN_delay);
$setuphold (negedge CLKBWRCLK, posedge DINPADINP, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, DINPADINP_delay);
$setuphold (negedge CLKBWRCLK, posedge DINPBDINP, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, DINPBDINP_delay);
$setuphold (negedge CLKBWRCLK, posedge ENARDEN, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, ENARDEN_delay);
$setuphold (negedge CLKBWRCLK, posedge ENBWREN, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, ENBWREN_delay);
$setuphold (negedge CLKBWRCLK, posedge INJECTDBITERR, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, INJECTDBITERR_delay);
$setuphold (negedge CLKBWRCLK, posedge INJECTSBITERR, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, INJECTSBITERR_delay);
$setuphold (negedge CLKBWRCLK, posedge REGCEAREGCE, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, REGCEAREGCE_delay);
$setuphold (negedge CLKBWRCLK, posedge REGCEB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, REGCEB_delay);
$setuphold (negedge CLKBWRCLK, posedge RSTRAMARSTRAM, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, RSTRAMARSTRAM_delay);
$setuphold (negedge CLKBWRCLK, posedge RSTRAMB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, RSTRAMB_delay);
$setuphold (negedge CLKBWRCLK, posedge RSTREGARSTREG, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, RSTREGARSTREG_delay);
$setuphold (negedge CLKBWRCLK, posedge RSTREGB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, RSTREGB_delay);
$setuphold (negedge CLKBWRCLK, posedge WEA, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, WEA_delay);
$setuphold (negedge CLKBWRCLK, posedge WEBWE, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, WEBWE_delay);
$setuphold (posedge CLKARDCLK, negedge ADDRARDADDR, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, ADDRARDADDR_delay);
$setuphold (posedge CLKARDCLK, negedge ADDRBWRADDR, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, ADDRBWRADDR_delay);
$setuphold (posedge CLKARDCLK, negedge ADDRENA, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, ADDRENA_delay);
$setuphold (posedge CLKARDCLK, negedge ADDRENB, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, ADDRENB_delay);
$setuphold (posedge CLKARDCLK, negedge CASDIMUXA, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDIMUXA_delay);
$setuphold (posedge CLKARDCLK, negedge CASDIMUXB, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDIMUXB_delay);
$setuphold (posedge CLKARDCLK, negedge CASDINA, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDINA_delay);
$setuphold (posedge CLKARDCLK, negedge CASDINB, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDINB_delay);
$setuphold (posedge CLKARDCLK, negedge CASDINPA, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDINPA_delay);
$setuphold (posedge CLKARDCLK, negedge CASDINPB, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDINPB_delay);
$setuphold (posedge CLKARDCLK, negedge CASDOMUXA, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDOMUXA_delay);
$setuphold (posedge CLKARDCLK, negedge CASDOMUXB, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDOMUXB_delay);
$setuphold (posedge CLKARDCLK, negedge CASDOMUXEN_A, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDOMUXEN_A_delay);
$setuphold (posedge CLKARDCLK, negedge CASDOMUXEN_B, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDOMUXEN_B_delay);
$setuphold (posedge CLKARDCLK, negedge CASINDBITERR, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASINDBITERR_delay);
$setuphold (posedge CLKARDCLK, negedge CASINSBITERR, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASINSBITERR_delay);
$setuphold (posedge CLKARDCLK, negedge CASOREGIMUXA, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASOREGIMUXA_delay);
$setuphold (posedge CLKARDCLK, negedge CASOREGIMUXB, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASOREGIMUXB_delay);
$setuphold (posedge CLKARDCLK, negedge CASOREGIMUXEN_A, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASOREGIMUXEN_A_delay);
$setuphold (posedge CLKARDCLK, negedge CASOREGIMUXEN_B, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASOREGIMUXEN_B_delay);
$setuphold (posedge CLKARDCLK, negedge DINADIN, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, DINADIN_delay);
$setuphold (posedge CLKARDCLK, negedge DINBDIN, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, DINBDIN_delay);
$setuphold (posedge CLKARDCLK, negedge DINPADINP, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, DINPADINP_delay);
$setuphold (posedge CLKARDCLK, negedge ECCPIPECE, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, ECCPIPECE_delay);
$setuphold (posedge CLKARDCLK, negedge ENARDEN, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, ENARDEN_delay);
$setuphold (posedge CLKARDCLK, negedge ENBWREN, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, ENBWREN_delay);
$setuphold (posedge CLKARDCLK, negedge INJECTDBITERR, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, INJECTDBITERR_delay);
$setuphold (posedge CLKARDCLK, negedge INJECTSBITERR, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, INJECTSBITERR_delay);
$setuphold (posedge CLKARDCLK, negedge REGCEAREGCE, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, REGCEAREGCE_delay);
$setuphold (posedge CLKARDCLK, negedge REGCEB, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, REGCEB_delay);
$setuphold (posedge CLKARDCLK, negedge RSTRAMARSTRAM, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, RSTRAMARSTRAM_delay);
$setuphold (posedge CLKARDCLK, negedge RSTRAMB, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, RSTRAMB_delay);
$setuphold (posedge CLKARDCLK, negedge RSTREGARSTREG, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, RSTREGARSTREG_delay);
$setuphold (posedge CLKARDCLK, negedge RSTREGB, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, RSTREGB_delay);
$setuphold (posedge CLKARDCLK, negedge SLEEP, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, SLEEP_delay);
$setuphold (posedge CLKARDCLK, negedge WEA, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, WEA_delay);
$setuphold (posedge CLKARDCLK, negedge WEBWE, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, WEBWE_delay);
$setuphold (posedge CLKARDCLK, posedge ADDRARDADDR, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, ADDRARDADDR_delay);
$setuphold (posedge CLKARDCLK, posedge ADDRBWRADDR, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, ADDRBWRADDR_delay);
$setuphold (posedge CLKARDCLK, posedge ADDRENA, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, ADDRENA_delay);
$setuphold (posedge CLKARDCLK, posedge ADDRENB, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, ADDRENB_delay);
$setuphold (posedge CLKARDCLK, posedge CASDIMUXA, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDIMUXA_delay);
$setuphold (posedge CLKARDCLK, posedge CASDIMUXB, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDIMUXB_delay);
$setuphold (posedge CLKARDCLK, posedge CASDINA, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDINA_delay);
$setuphold (posedge CLKARDCLK, posedge CASDINB, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDINB_delay);
$setuphold (posedge CLKARDCLK, posedge CASDINPA, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDINPA_delay);
$setuphold (posedge CLKARDCLK, posedge CASDINPB, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDINPB_delay);
$setuphold (posedge CLKARDCLK, posedge CASDOMUXA, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDOMUXA_delay);
$setuphold (posedge CLKARDCLK, posedge CASDOMUXB, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDOMUXB_delay);
$setuphold (posedge CLKARDCLK, posedge CASDOMUXEN_A, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDOMUXEN_A_delay);
$setuphold (posedge CLKARDCLK, posedge CASDOMUXEN_B, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASDOMUXEN_B_delay);
$setuphold (posedge CLKARDCLK, posedge CASINDBITERR, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASINDBITERR_delay);
$setuphold (posedge CLKARDCLK, posedge CASINSBITERR, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASINSBITERR_delay);
$setuphold (posedge CLKARDCLK, posedge CASOREGIMUXA, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASOREGIMUXA_delay);
$setuphold (posedge CLKARDCLK, posedge CASOREGIMUXB, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASOREGIMUXB_delay);
$setuphold (posedge CLKARDCLK, posedge CASOREGIMUXEN_A, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASOREGIMUXEN_A_delay);
$setuphold (posedge CLKARDCLK, posedge CASOREGIMUXEN_B, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, CASOREGIMUXEN_B_delay);
$setuphold (posedge CLKARDCLK, posedge DINADIN, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, DINADIN_delay);
$setuphold (posedge CLKARDCLK, posedge DINBDIN, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, DINBDIN_delay);
$setuphold (posedge CLKARDCLK, posedge DINPADINP, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, DINPADINP_delay);
$setuphold (posedge CLKARDCLK, posedge ECCPIPECE, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, ECCPIPECE_delay);
$setuphold (posedge CLKARDCLK, posedge ENARDEN, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, ENARDEN_delay);
$setuphold (posedge CLKARDCLK, posedge ENBWREN, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, ENBWREN_delay);
$setuphold (posedge CLKARDCLK, posedge INJECTDBITERR, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, INJECTDBITERR_delay);
$setuphold (posedge CLKARDCLK, posedge INJECTSBITERR, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, INJECTSBITERR_delay);
$setuphold (posedge CLKARDCLK, posedge REGCEAREGCE, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, REGCEAREGCE_delay);
$setuphold (posedge CLKARDCLK, posedge REGCEB, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, REGCEB_delay);
$setuphold (posedge CLKARDCLK, posedge RSTRAMARSTRAM, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, RSTRAMARSTRAM_delay);
$setuphold (posedge CLKARDCLK, posedge RSTRAMB, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, RSTRAMB_delay);
$setuphold (posedge CLKARDCLK, posedge RSTREGARSTREG, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, RSTREGARSTREG_delay);
$setuphold (posedge CLKARDCLK, posedge RSTREGB, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, RSTREGB_delay);
$setuphold (posedge CLKARDCLK, posedge SLEEP, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, SLEEP_delay);
$setuphold (posedge CLKARDCLK, posedge WEA, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, WEA_delay);
$setuphold (posedge CLKARDCLK, posedge WEBWE, 0:0:0, 0:0:0, notifier,,, CLKARDCLK_delay, WEBWE_delay);
$setuphold (posedge CLKBWRCLK, negedge ADDRARDADDR, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, ADDRARDADDR_delay);
$setuphold (posedge CLKBWRCLK, negedge ADDRBWRADDR, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, ADDRBWRADDR_delay);
$setuphold (posedge CLKBWRCLK, negedge ADDRENA, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, ADDRENA_delay);
$setuphold (posedge CLKBWRCLK, negedge ADDRENB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, ADDRENB_delay);
$setuphold (posedge CLKBWRCLK, negedge CASDIMUXA, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDIMUXA_delay);
$setuphold (posedge CLKBWRCLK, negedge CASDIMUXB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDIMUXB_delay);
$setuphold (posedge CLKBWRCLK, negedge CASDINA, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDINA_delay);
$setuphold (posedge CLKBWRCLK, negedge CASDINB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDINB_delay);
$setuphold (posedge CLKBWRCLK, negedge CASDINPA, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDINPA_delay);
$setuphold (posedge CLKBWRCLK, negedge CASDINPB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDINPB_delay);
$setuphold (posedge CLKBWRCLK, negedge CASDOMUXA, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDOMUXA_delay);
$setuphold (posedge CLKBWRCLK, negedge CASDOMUXB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDOMUXB_delay);
$setuphold (posedge CLKBWRCLK, negedge CASDOMUXEN_A, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDOMUXEN_A_delay);
$setuphold (posedge CLKBWRCLK, negedge CASDOMUXEN_B, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDOMUXEN_B_delay);
$setuphold (posedge CLKBWRCLK, negedge CASOREGIMUXA, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASOREGIMUXA_delay);
$setuphold (posedge CLKBWRCLK, negedge CASOREGIMUXB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASOREGIMUXB_delay);
$setuphold (posedge CLKBWRCLK, negedge CASOREGIMUXEN_A, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASOREGIMUXEN_A_delay);
$setuphold (posedge CLKBWRCLK, negedge CASOREGIMUXEN_B, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASOREGIMUXEN_B_delay);
$setuphold (posedge CLKBWRCLK, negedge DINADIN, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, DINADIN_delay);
$setuphold (posedge CLKBWRCLK, negedge DINBDIN, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, DINBDIN_delay);
$setuphold (posedge CLKBWRCLK, negedge DINPADINP, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, DINPADINP_delay);
$setuphold (posedge CLKBWRCLK, negedge DINPBDINP, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, DINPBDINP_delay);
$setuphold (posedge CLKBWRCLK, negedge ENARDEN, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, ENARDEN_delay);
$setuphold (posedge CLKBWRCLK, negedge ENBWREN, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, ENBWREN_delay);
$setuphold (posedge CLKBWRCLK, negedge INJECTDBITERR, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, INJECTDBITERR_delay);
$setuphold (posedge CLKBWRCLK, negedge INJECTSBITERR, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, INJECTSBITERR_delay);
$setuphold (posedge CLKBWRCLK, negedge REGCEAREGCE, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, REGCEAREGCE_delay);
$setuphold (posedge CLKBWRCLK, negedge REGCEB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, REGCEB_delay);
$setuphold (posedge CLKBWRCLK, negedge RSTRAMARSTRAM, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, RSTRAMARSTRAM_delay);
$setuphold (posedge CLKBWRCLK, negedge RSTRAMB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, RSTRAMB_delay);
$setuphold (posedge CLKBWRCLK, negedge RSTREGARSTREG, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, RSTREGARSTREG_delay);
$setuphold (posedge CLKBWRCLK, negedge RSTREGB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, RSTREGB_delay);
$setuphold (posedge CLKBWRCLK, negedge WEA, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, WEA_delay);
$setuphold (posedge CLKBWRCLK, negedge WEBWE, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, WEBWE_delay);
$setuphold (posedge CLKBWRCLK, posedge ADDRARDADDR, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, ADDRARDADDR_delay);
$setuphold (posedge CLKBWRCLK, posedge ADDRBWRADDR, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, ADDRBWRADDR_delay);
$setuphold (posedge CLKBWRCLK, posedge ADDRENA, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, ADDRENA_delay);
$setuphold (posedge CLKBWRCLK, posedge ADDRENB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, ADDRENB_delay);
$setuphold (posedge CLKBWRCLK, posedge CASDIMUXA, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDIMUXA_delay);
$setuphold (posedge CLKBWRCLK, posedge CASDIMUXB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDIMUXB_delay);
$setuphold (posedge CLKBWRCLK, posedge CASDINA, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDINA_delay);
$setuphold (posedge CLKBWRCLK, posedge CASDINB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDINB_delay);
$setuphold (posedge CLKBWRCLK, posedge CASDINPA, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDINPA_delay);
$setuphold (posedge CLKBWRCLK, posedge CASDINPB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDINPB_delay);
$setuphold (posedge CLKBWRCLK, posedge CASDOMUXA, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDOMUXA_delay);
$setuphold (posedge CLKBWRCLK, posedge CASDOMUXB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDOMUXB_delay);
$setuphold (posedge CLKBWRCLK, posedge CASDOMUXEN_A, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDOMUXEN_A_delay);
$setuphold (posedge CLKBWRCLK, posedge CASDOMUXEN_B, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASDOMUXEN_B_delay);
$setuphold (posedge CLKBWRCLK, posedge CASOREGIMUXA, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASOREGIMUXA_delay);
$setuphold (posedge CLKBWRCLK, posedge CASOREGIMUXB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASOREGIMUXB_delay);
$setuphold (posedge CLKBWRCLK, posedge CASOREGIMUXEN_A, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASOREGIMUXEN_A_delay);
$setuphold (posedge CLKBWRCLK, posedge CASOREGIMUXEN_B, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, CASOREGIMUXEN_B_delay);
$setuphold (posedge CLKBWRCLK, posedge DINADIN, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, DINADIN_delay);
$setuphold (posedge CLKBWRCLK, posedge DINBDIN, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, DINBDIN_delay);
$setuphold (posedge CLKBWRCLK, posedge DINPADINP, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, DINPADINP_delay);
$setuphold (posedge CLKBWRCLK, posedge DINPBDINP, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, DINPBDINP_delay);
$setuphold (posedge CLKBWRCLK, posedge ENARDEN, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, ENARDEN_delay);
$setuphold (posedge CLKBWRCLK, posedge ENBWREN, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, ENBWREN_delay);
$setuphold (posedge CLKBWRCLK, posedge INJECTDBITERR, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, INJECTDBITERR_delay);
$setuphold (posedge CLKBWRCLK, posedge INJECTSBITERR, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, INJECTSBITERR_delay);
$setuphold (posedge CLKBWRCLK, posedge REGCEAREGCE, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, REGCEAREGCE_delay);
$setuphold (posedge CLKBWRCLK, posedge REGCEB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, REGCEB_delay);
$setuphold (posedge CLKBWRCLK, posedge RSTRAMARSTRAM, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, RSTRAMARSTRAM_delay);
$setuphold (posedge CLKBWRCLK, posedge RSTRAMB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, RSTRAMB_delay);
$setuphold (posedge CLKBWRCLK, posedge RSTREGARSTREG, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, RSTREGARSTREG_delay);
$setuphold (posedge CLKBWRCLK, posedge RSTREGB, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, RSTREGB_delay);
$setuphold (posedge CLKBWRCLK, posedge WEA, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, WEA_delay);
$setuphold (posedge CLKBWRCLK, posedge WEBWE, 0:0:0, 0:0:0, notifier,,, CLKBWRCLK_delay, WEBWE_delay);
$width (negedge CLKARDCLK, 0:0:0, 0, notifier);
$width (negedge CLKBWRCLK, 0:0:0, 0, notifier);
$width (posedge CLKARDCLK, 0:0:0, 0, notifier);
$width (posedge CLKBWRCLK, 0:0:0, 0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
|
/* ****************************************************************************
This Source Code Form is subject to the terms of the
Open Hardware Description License, v. 1.0. If a copy
of the OHDL was not distributed with this file, You
can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
Description: Data bus interface
All combinatorial outputs to pipeline
Dbus interface request signal out synchronous
32-bit specific
Copyright (C) 2012 Julius Baxter <[email protected]>
Copyright (C) 2013 Stefan Kristiansson <[email protected]>
***************************************************************************** */
`include "mor1kx-defines.v"
module mor1kx_lsu_cappuccino
#(
parameter FEATURE_DATACACHE = "NONE",
parameter OPTION_OPERAND_WIDTH = 32,
parameter OPTION_DCACHE_BLOCK_WIDTH = 5,
parameter OPTION_DCACHE_SET_WIDTH = 9,
parameter OPTION_DCACHE_WAYS = 2,
parameter OPTION_DCACHE_LIMIT_WIDTH = 32,
parameter OPTION_DCACHE_SNOOP = "NONE",
parameter FEATURE_DMMU = "NONE",
parameter FEATURE_DMMU_HW_TLB_RELOAD = "NONE",
parameter OPTION_DMMU_SET_WIDTH = 6,
parameter OPTION_DMMU_WAYS = 1,
parameter FEATURE_STORE_BUFFER = "ENABLED",
parameter OPTION_STORE_BUFFER_DEPTH_WIDTH = 8,
parameter FEATURE_ATOMIC = "ENABLED"
)
(
input clk,
input rst,
input padv_execute_i,
input padv_ctrl_i, // needed for dmmu spr
input decode_valid_i,
// calculated address from ALU
input [OPTION_OPERAND_WIDTH-1:0] exec_lsu_adr_i,
input [OPTION_OPERAND_WIDTH-1:0] ctrl_lsu_adr_i,
// register file B in (store operand)
input [OPTION_OPERAND_WIDTH-1:0] ctrl_rfb_i,
// from decode stage regs, indicate if load or store
input exec_op_lsu_load_i,
input exec_op_lsu_store_i,
input exec_op_lsu_atomic_i,
input ctrl_op_lsu_load_i,
input ctrl_op_lsu_store_i,
input ctrl_op_lsu_atomic_i,
input ctrl_op_msync_i,
input [1:0] ctrl_lsu_length_i,
input ctrl_lsu_zext_i,
// From control stage, exception PC for the store buffer input
input [OPTION_OPERAND_WIDTH-1:0] ctrl_epcr_i,
// The exception PC as it has went through the store buffer
output [OPTION_OPERAND_WIDTH-1:0] store_buffer_epcr_o,
output [OPTION_OPERAND_WIDTH-1:0] lsu_result_o,
output lsu_valid_o,
// exception output
output lsu_except_dbus_o,
output lsu_except_align_o,
output lsu_except_dtlb_miss_o,
output lsu_except_dpagefault_o,
// Indicator that the dbus exception came via the store buffer
output reg store_buffer_err_o,
// Atomic operation flag set/clear logic
output atomic_flag_set_o,
output atomic_flag_clear_o,
// stall signal for msync logic
output msync_stall_o,
// SPR interface
input [15:0] spr_bus_addr_i,
input spr_bus_we_i,
input spr_bus_stb_i,
input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_i,
output [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_dc_o,
output spr_bus_ack_dc_o,
output [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_dmmu_o,
output spr_bus_ack_dmmu_o,
input dc_enable_i,
input dmmu_enable_i,
input supervisor_mode_i,
// interface to data bus
output [OPTION_OPERAND_WIDTH-1:0] dbus_adr_o,
output reg dbus_req_o,
output [OPTION_OPERAND_WIDTH-1:0] dbus_dat_o,
output reg [3:0] dbus_bsel_o,
output dbus_we_o,
output dbus_burst_o,
input dbus_err_i,
input dbus_ack_i,
input [OPTION_OPERAND_WIDTH-1:0] dbus_dat_i,
input pipeline_flush_i,
input [31:0] snoop_adr_i,
input snoop_en_i
);
reg [OPTION_OPERAND_WIDTH-1:0] dbus_dat_aligned; // comb.
reg [OPTION_OPERAND_WIDTH-1:0] dbus_dat_extended; // comb.
reg access_done;
wire align_err_word;
wire align_err_short;
wire align_err;
wire except_align;
reg except_dbus;
reg dbus_ack;
reg dbus_err;
reg [OPTION_OPERAND_WIDTH-1:0] dbus_dat;
reg [OPTION_OPERAND_WIDTH-1:0] dbus_adr;
wire [OPTION_OPERAND_WIDTH-1:0] next_dbus_adr;
reg dbus_we;
reg [3:0] dbus_bsel;
wire dbus_access;
wire dbus_stall;
wire [OPTION_OPERAND_WIDTH-1:0] lsu_ldat;
wire [OPTION_OPERAND_WIDTH-1:0] lsu_sdat;
wire lsu_ack;
wire dc_err;
wire dc_ack;
wire [31:0] dc_ldat;
wire [31:0] dc_sdat;
wire [31:0] dc_adr;
wire [31:0] dc_adr_match;
wire dc_req;
wire dc_we;
wire [3:0] dc_bsel;
wire dc_access;
wire dc_refill_allowed;
wire dc_refill;
wire dc_refill_req;
wire dc_refill_done;
reg dc_enable_r;
wire dc_enabled;
wire ctrl_op_lsu;
// DMMU
wire tlb_miss;
wire pagefault;
wire [OPTION_OPERAND_WIDTH-1:0] dmmu_phys_addr;
wire except_dtlb_miss;
reg except_dtlb_miss_r;
wire except_dpagefault;
reg except_dpagefault_r;
wire dmmu_cache_inhibit;
wire tlb_reload_req;
wire tlb_reload_busy;
wire [OPTION_OPERAND_WIDTH-1:0] tlb_reload_addr;
wire tlb_reload_pagefault;
reg tlb_reload_ack;
reg [OPTION_OPERAND_WIDTH-1:0] tlb_reload_data;
wire tlb_reload_pagefault_clear;
reg tlb_reload_done;
// Store buffer
wire store_buffer_write;
wire store_buffer_read;
wire store_buffer_full;
wire store_buffer_empty;
wire [OPTION_OPERAND_WIDTH-1:0] store_buffer_radr;
wire [OPTION_OPERAND_WIDTH-1:0] store_buffer_wadr;
wire [OPTION_OPERAND_WIDTH-1:0] store_buffer_dat;
wire [OPTION_OPERAND_WIDTH/8-1:0] store_buffer_bsel;
wire store_buffer_atomic;
reg store_buffer_write_pending;
reg dbus_atomic;
reg last_write;
reg write_done;
// Atomic operations
reg [OPTION_OPERAND_WIDTH-1:0] atomic_addr;
reg atomic_reserve;
wire swa_success;
wire snoop_valid;
wire dc_snoop_hit;
// We have to mask out our snooped bus accesses
assign snoop_valid = (OPTION_DCACHE_SNOOP != "NONE") ?
snoop_en_i & !((snoop_adr_i == dbus_adr_o) & dbus_ack_i) :
0;
assign ctrl_op_lsu = ctrl_op_lsu_load_i | ctrl_op_lsu_store_i;
assign lsu_sdat = (ctrl_lsu_length_i == 2'b00) ? // byte access
{ctrl_rfb_i[7:0],ctrl_rfb_i[7:0],
ctrl_rfb_i[7:0],ctrl_rfb_i[7:0]} :
(ctrl_lsu_length_i == 2'b01) ? // halfword access
{ctrl_rfb_i[15:0],ctrl_rfb_i[15:0]} :
ctrl_rfb_i; // word access
assign align_err_word = |ctrl_lsu_adr_i[1:0];
assign align_err_short = ctrl_lsu_adr_i[0];
assign lsu_valid_o = (lsu_ack | access_done) & !tlb_reload_busy & !dc_snoop_hit;
assign lsu_except_dbus_o = except_dbus | store_buffer_err_o;
assign align_err = (ctrl_lsu_length_i == 2'b10) & align_err_word |
(ctrl_lsu_length_i == 2'b01) & align_err_short;
assign except_align = ctrl_op_lsu & align_err;
assign lsu_except_align_o = except_align & !pipeline_flush_i;
assign except_dtlb_miss = ctrl_op_lsu & tlb_miss & dmmu_enable_i &
!tlb_reload_busy;
assign lsu_except_dtlb_miss_o = except_dtlb_miss & !pipeline_flush_i;
assign except_dpagefault = ctrl_op_lsu & pagefault & dmmu_enable_i &
!tlb_reload_busy | tlb_reload_pagefault;
assign lsu_except_dpagefault_o = except_dpagefault & !pipeline_flush_i;
always @(posedge clk `OR_ASYNC_RST)
if (rst)
access_done <= 0;
else if (padv_execute_i)
access_done <= 0;
else if (lsu_ack)
access_done <= 1;
always @(posedge clk `OR_ASYNC_RST)
if (rst)
except_dbus <= 0;
else if (padv_execute_i | pipeline_flush_i)
except_dbus <= 0;
else if (dbus_err_i)
except_dbus <= 1;
always @(posedge clk `OR_ASYNC_RST)
if (rst)
except_dtlb_miss_r <= 0;
else if (padv_execute_i)
except_dtlb_miss_r <= 0;
else if (except_dtlb_miss)
except_dtlb_miss_r <= 1;
always @(posedge clk `OR_ASYNC_RST)
if (rst)
except_dpagefault_r <= 0;
else if (padv_execute_i)
except_dpagefault_r <= 0;
else if (except_dpagefault)
except_dpagefault_r <= 1;
always @(posedge clk `OR_ASYNC_RST)
if (rst)
store_buffer_err_o <= 0;
else if (pipeline_flush_i)
store_buffer_err_o <= 0;
else if (dbus_err_i & dbus_we_o)
store_buffer_err_o <= 1;
// Big endian bus mapping
always @(*)
case (ctrl_lsu_length_i)
2'b00: // byte access
case(ctrl_lsu_adr_i[1:0])
2'b00:
dbus_bsel = 4'b1000;
2'b01:
dbus_bsel = 4'b0100;
2'b10:
dbus_bsel = 4'b0010;
2'b11:
dbus_bsel = 4'b0001;
endcase
2'b01: // halfword access
case(ctrl_lsu_adr_i[1])
1'b0:
dbus_bsel = 4'b1100;
1'b1:
dbus_bsel = 4'b0011;
endcase
2'b10,
2'b11:
dbus_bsel = 4'b1111;
endcase
// Select part of read word
always @*
case(ctrl_lsu_adr_i[1:0])
2'b00:
dbus_dat_aligned = lsu_ldat;
2'b01:
dbus_dat_aligned = {lsu_ldat[23:0],8'd0};
2'b10:
dbus_dat_aligned = {lsu_ldat[15:0],16'd0};
2'b11:
dbus_dat_aligned = {lsu_ldat[7:0],24'd0};
endcase // case (ctrl_lsu_adr_i[1:0])
// Do appropriate extension
always @(*)
case({ctrl_lsu_zext_i, ctrl_lsu_length_i})
3'b100: // lbz
dbus_dat_extended = {24'd0,dbus_dat_aligned[31:24]};
3'b101: // lhz
dbus_dat_extended = {16'd0,dbus_dat_aligned[31:16]};
3'b000: // lbs
dbus_dat_extended = {{24{dbus_dat_aligned[31]}},
dbus_dat_aligned[31:24]};
3'b001: // lhs
dbus_dat_extended = {{16{dbus_dat_aligned[31]}},
dbus_dat_aligned[31:16]};
default:
dbus_dat_extended = dbus_dat_aligned;
endcase
assign lsu_result_o = dbus_dat_extended;
// Bus access logic
localparam [2:0]
IDLE = 3'd0,
READ = 3'd1,
WRITE = 3'd2,
TLB_RELOAD = 3'd3,
DC_REFILL = 3'd4;
reg [2:0] state;
assign dbus_access = (!dc_access | tlb_reload_busy | ctrl_op_lsu_store_i) &
(state != DC_REFILL) | (state == WRITE);
reg dc_refill_r;
always @(posedge clk)
dc_refill_r <= dc_refill;
wire store_buffer_ack;
assign store_buffer_ack = (FEATURE_STORE_BUFFER!="NONE") ?
store_buffer_write :
write_done;
assign lsu_ack = (ctrl_op_lsu_store_i | state == WRITE) ?
(store_buffer_ack & !ctrl_op_lsu_atomic_i |
write_done & ctrl_op_lsu_atomic_i) :
(dbus_access ? dbus_ack : dc_ack);
assign lsu_ldat = dbus_access ? dbus_dat : dc_ldat;
assign dbus_adr_o = dbus_adr;
assign dbus_dat_o = dbus_dat;
assign dbus_burst_o = (state == DC_REFILL) & !dc_refill_done;
//
// Slightly subtle, but if there is an atomic store coming out from the
// store buffer, and the link has been broken while it was waiting there,
// the bus access is still performed as a (discarded) read.
//
assign dbus_we_o = dbus_we & (!dbus_atomic | atomic_reserve);
assign next_dbus_adr = (OPTION_DCACHE_BLOCK_WIDTH == 5) ?
{dbus_adr[31:5], dbus_adr[4:0] + 5'd4} : // 32 byte
{dbus_adr[31:4], dbus_adr[3:0] + 4'd4}; // 16 byte
always @(posedge clk `OR_ASYNC_RST)
if (rst)
dbus_err <= 0;
else
dbus_err <= dbus_err_i;
always @(posedge clk) begin
dbus_ack <= 0;
write_done <= 0;
tlb_reload_ack <= 0;
tlb_reload_done <= 0;
case (state)
IDLE: begin
dbus_req_o <= 0;
dbus_we <= 0;
dbus_adr <= 0;
dbus_bsel_o <= 4'hf;
dbus_atomic <= 0;
last_write <= 0;
if (store_buffer_write | !store_buffer_empty) begin
state <= WRITE;
end else if (ctrl_op_lsu & dbus_access & !dc_refill & !dbus_ack &
!dbus_err & !except_dbus & !access_done &
!pipeline_flush_i) begin
if (tlb_reload_req) begin
dbus_adr <= tlb_reload_addr;
dbus_req_o <= 1;
state <= TLB_RELOAD;
end else if (dmmu_enable_i) begin
dbus_adr <= dmmu_phys_addr;
if (!tlb_miss & !pagefault & !except_align) begin
if (ctrl_op_lsu_load_i) begin
dbus_req_o <= 1;
dbus_bsel_o <= dbus_bsel;
state <= READ;
end
end
end else if (!except_align) begin
dbus_adr <= ctrl_lsu_adr_i;
if (ctrl_op_lsu_load_i) begin
dbus_req_o <= 1;
dbus_bsel_o <= dbus_bsel;
state <= READ;
end
end
end else if (dc_refill_req) begin
dbus_req_o <= 1;
dbus_adr <= dc_adr_match;
state <= DC_REFILL;
end
end
DC_REFILL: begin
dbus_req_o <= 1;
if (dbus_ack_i) begin
dbus_adr <= next_dbus_adr;
if (dc_refill_done) begin
dbus_req_o <= 0;
state <= IDLE;
end
end
// TODO: only abort on snoop-hits to refill address
if (dbus_err_i | dc_snoop_hit) begin
dbus_req_o <= 0;
state <= IDLE;
end
end
READ: begin
dbus_ack <= dbus_ack_i;
dbus_dat <= dbus_dat_i;
if (dbus_ack_i | dbus_err_i) begin
dbus_req_o <= 0;
state <= IDLE;
end
end
WRITE: begin
dbus_req_o <= 1;
dbus_we <= 1;
if (!dbus_req_o | dbus_ack_i & !last_write) begin
dbus_bsel_o <= store_buffer_bsel;
dbus_adr <= store_buffer_radr;
dbus_dat <= store_buffer_dat;
dbus_atomic <= store_buffer_atomic;
last_write <= store_buffer_empty;
end
if (store_buffer_write)
last_write <= 0;
if (last_write & dbus_ack_i | dbus_err_i) begin
dbus_req_o <= 0;
dbus_we <= 0;
if (!store_buffer_write) begin
state <= IDLE;
write_done <= 1;
end
end
end
TLB_RELOAD: begin
dbus_adr <= tlb_reload_addr;
tlb_reload_data <= dbus_dat_i;
tlb_reload_ack <= dbus_ack_i & tlb_reload_req;
if (!tlb_reload_req | dbus_err_i) begin
state <= IDLE;
tlb_reload_done <= 1;
end
dbus_req_o <= tlb_reload_req;
if (dbus_ack_i | tlb_reload_ack)
dbus_req_o <= 0;
end
default:
state <= IDLE;
endcase
if (rst)
state <= IDLE;
end
assign dbus_stall = tlb_reload_busy | except_align | except_dbus |
except_dtlb_miss | except_dpagefault |
pipeline_flush_i;
// Stall until the store buffer is empty
assign msync_stall_o = ctrl_op_msync_i & (state == WRITE);
generate
if (FEATURE_ATOMIC!="NONE") begin : atomic_gen
// Atomic operations logic
reg atomic_flag_set;
reg atomic_flag_clear;
always @(posedge clk `OR_ASYNC_RST)
if (rst)
atomic_reserve <= 0;
else if (pipeline_flush_i)
atomic_reserve <= 0;
else if (ctrl_op_lsu_store_i & ctrl_op_lsu_atomic_i & write_done ||
!ctrl_op_lsu_atomic_i & store_buffer_write &
(store_buffer_wadr == atomic_addr) ||
(snoop_valid & (snoop_adr_i == atomic_addr)))
atomic_reserve <= 0;
else if (ctrl_op_lsu_load_i & ctrl_op_lsu_atomic_i & padv_ctrl_i)
atomic_reserve <= !(snoop_valid & (snoop_adr_i == dc_adr_match));
always @(posedge clk)
if (ctrl_op_lsu_load_i & ctrl_op_lsu_atomic_i & padv_ctrl_i)
atomic_addr <= dc_adr_match;
assign swa_success = ctrl_op_lsu_store_i & ctrl_op_lsu_atomic_i &
atomic_reserve & (dbus_adr == atomic_addr);
always @(posedge clk)
if (padv_ctrl_i)
atomic_flag_set <= 0;
else if (write_done)
atomic_flag_set <= swa_success & lsu_valid_o;
always @(posedge clk)
if (padv_ctrl_i)
atomic_flag_clear <= 0;
else if (write_done)
atomic_flag_clear <= !swa_success & lsu_valid_o &
ctrl_op_lsu_atomic_i & ctrl_op_lsu_store_i;
assign atomic_flag_set_o = atomic_flag_set;
assign atomic_flag_clear_o = atomic_flag_clear;
end else begin
assign atomic_flag_set_o = 0;
assign atomic_flag_clear_o = 0;
assign swa_success = 0;
always @(posedge clk) begin
atomic_addr <= 0;
atomic_reserve <= 0;
end
end
endgenerate
// Store buffer logic
always @(posedge clk)
if (rst)
store_buffer_write_pending <= 0;
else if (store_buffer_write | pipeline_flush_i)
store_buffer_write_pending <= 0;
else if (ctrl_op_lsu_store_i & padv_ctrl_i & !dbus_stall &
(store_buffer_full | dc_refill | dc_refill_r | dc_snoop_hit))
store_buffer_write_pending <= 1;
assign store_buffer_write = (ctrl_op_lsu_store_i &
(padv_ctrl_i | tlb_reload_done) |
store_buffer_write_pending) &
!store_buffer_full & !dc_refill & !dc_refill_r &
!dbus_stall & !dc_snoop_hit;
generate
if (FEATURE_STORE_BUFFER!="NONE") begin : store_buffer_gen
assign store_buffer_read = (state == IDLE) & store_buffer_write |
(state == IDLE) & !store_buffer_empty |
(state == WRITE) & (dbus_ack_i | !dbus_req_o) &
(!store_buffer_empty | store_buffer_write) &
!last_write |
(state == WRITE) & last_write &
store_buffer_write;
mor1kx_store_buffer
#(
.DEPTH_WIDTH(OPTION_STORE_BUFFER_DEPTH_WIDTH),
.OPTION_OPERAND_WIDTH(OPTION_OPERAND_WIDTH)
)
mor1kx_store_buffer
(
.clk (clk),
.rst (rst),
.pc_i (ctrl_epcr_i),
.adr_i (store_buffer_wadr),
.dat_i (lsu_sdat),
.bsel_i (dbus_bsel),
.atomic_i (ctrl_op_lsu_atomic_i),
.write_i (store_buffer_write),
.pc_o (store_buffer_epcr_o),
.adr_o (store_buffer_radr),
.dat_o (store_buffer_dat),
.bsel_o (store_buffer_bsel),
.atomic_o (store_buffer_atomic),
.read_i (store_buffer_read),
.full_o (store_buffer_full),
.empty_o (store_buffer_empty)
);
end else begin
assign store_buffer_epcr_o = ctrl_epcr_i;
assign store_buffer_radr = store_buffer_wadr;
assign store_buffer_dat = lsu_sdat;
assign store_buffer_bsel = dbus_bsel;
assign store_buffer_empty = 1'b1;
reg store_buffer_full_r;
always @(posedge clk)
if (store_buffer_write)
store_buffer_full_r <= 1;
else if (write_done)
store_buffer_full_r <= 0;
assign store_buffer_full = store_buffer_full_r & !write_done;
end
endgenerate
assign store_buffer_wadr = dc_adr_match;
always @(posedge clk `OR_ASYNC_RST)
if (rst)
dc_enable_r <= 0;
else if (dc_enable_i & !dbus_req_o)
dc_enable_r <= 1;
else if (!dc_enable_i & !dc_refill)
dc_enable_r <= 0;
assign dc_enabled = dc_enable_i & dc_enable_r;
assign dc_adr = padv_execute_i &
(exec_op_lsu_load_i | exec_op_lsu_store_i) ?
exec_lsu_adr_i : ctrl_lsu_adr_i;
assign dc_adr_match = dmmu_enable_i ?
{dmmu_phys_addr[OPTION_OPERAND_WIDTH-1:2],2'b0} :
{ctrl_lsu_adr_i[OPTION_OPERAND_WIDTH-1:2],2'b0};
assign dc_req = ctrl_op_lsu & dc_access & !access_done & !dbus_stall &
!(dbus_atomic & dbus_we & !atomic_reserve);
assign dc_refill_allowed = !(ctrl_op_lsu_store_i | state == WRITE) &
!dc_snoop_hit & !snoop_valid;
generate
if (FEATURE_DATACACHE!="NONE") begin : dcache_gen
if (OPTION_DCACHE_LIMIT_WIDTH == OPTION_OPERAND_WIDTH) begin
assign dc_access = ctrl_op_lsu_store_i | dc_enabled &
!(dmmu_cache_inhibit & dmmu_enable_i);
end else if (OPTION_DCACHE_LIMIT_WIDTH < OPTION_OPERAND_WIDTH) begin
assign dc_access = ctrl_op_lsu_store_i | dc_enabled &
dc_adr_match[OPTION_OPERAND_WIDTH-1:
OPTION_DCACHE_LIMIT_WIDTH] == 0 &
!(dmmu_cache_inhibit & dmmu_enable_i);
end else begin
initial begin
$display("ERROR: OPTION_DCACHE_LIMIT_WIDTH > OPTION_OPERAND_WIDTH");
$finish();
end
end
assign dc_bsel = dbus_bsel;
assign dc_we = exec_op_lsu_store_i & !exec_op_lsu_atomic_i & padv_execute_i |
dbus_atomic & dbus_we_o & !write_done |
ctrl_op_lsu_store_i & tlb_reload_busy & !tlb_reload_req;
/* mor1kx_dcache AUTO_TEMPLATE (
.refill_o (dc_refill),
.refill_req_o (dc_refill_req),
.refill_done_o (dc_refill_done),
.cpu_err_o (dc_err),
.cpu_ack_o (dc_ack),
.cpu_dat_o (dc_ldat),
.spr_bus_dat_o (spr_bus_dat_dc_o),
.spr_bus_ack_o (spr_bus_ack_dc_o),
.snoop_hit_o (dc_snoop_hit),
// Inputs
.clk (clk),
.rst (rst),
.dc_dbus_err_i (dbus_err),
.dc_enable_i (dc_enabled),
.dc_access_i (dc_access),
.cpu_dat_i (lsu_sdat),
.cpu_adr_i (dc_adr),
.cpu_adr_match_i (dc_adr_match),
.cpu_req_i (dc_req),
.cpu_we_i (dc_we),
.cpu_bsel_i (dc_bsel),
.refill_allowed (dc_refill_allowed),
.wradr_i (dbus_adr),
.wrdat_i (dbus_dat_i),
.we_i (dbus_ack_i),
.snoop_valid_i (snoop_valid),
);*/
mor1kx_dcache
#(
.OPTION_OPERAND_WIDTH(OPTION_OPERAND_WIDTH),
.OPTION_DCACHE_BLOCK_WIDTH(OPTION_DCACHE_BLOCK_WIDTH),
.OPTION_DCACHE_SET_WIDTH(OPTION_DCACHE_SET_WIDTH),
.OPTION_DCACHE_WAYS(OPTION_DCACHE_WAYS),
.OPTION_DCACHE_LIMIT_WIDTH(OPTION_DCACHE_LIMIT_WIDTH),
.OPTION_DCACHE_SNOOP(OPTION_DCACHE_SNOOP)
)
mor1kx_dcache
(/*AUTOINST*/
// Outputs
.refill_o (dc_refill), // Templated
.refill_req_o (dc_refill_req), // Templated
.refill_done_o (dc_refill_done), // Templated
.cpu_err_o (dc_err), // Templated
.cpu_ack_o (dc_ack), // Templated
.cpu_dat_o (dc_ldat), // Templated
.snoop_hit_o (dc_snoop_hit), // Templated
.spr_bus_dat_o (spr_bus_dat_dc_o), // Templated
.spr_bus_ack_o (spr_bus_ack_dc_o), // Templated
// Inputs
.clk (clk), // Templated
.rst (rst), // Templated
.dc_dbus_err_i (dbus_err), // Templated
.dc_enable_i (dc_enabled), // Templated
.dc_access_i (dc_access), // Templated
.cpu_dat_i (lsu_sdat), // Templated
.cpu_adr_i (dc_adr), // Templated
.cpu_adr_match_i (dc_adr_match), // Templated
.cpu_req_i (dc_req), // Templated
.cpu_we_i (dc_we), // Templated
.cpu_bsel_i (dc_bsel), // Templated
.refill_allowed (dc_refill_allowed), // Templated
.wradr_i (dbus_adr), // Templated
.wrdat_i (dbus_dat_i), // Templated
.we_i (dbus_ack_i), // Templated
.snoop_adr_i (snoop_adr_i[31:0]),
.snoop_valid_i (snoop_valid), // Templated
.spr_bus_addr_i (spr_bus_addr_i[15:0]),
.spr_bus_we_i (spr_bus_we_i),
.spr_bus_stb_i (spr_bus_stb_i),
.spr_bus_dat_i (spr_bus_dat_i[OPTION_OPERAND_WIDTH-1:0]));
end else begin
assign dc_access = 0;
assign dc_refill = 0;
assign dc_refill_done = 0;
assign dc_refill_req = 0;
assign dc_err = 0;
assign dc_ack = 0;
assign dc_bsel = 0;
assign dc_we = 0;
assign dc_snoop_hit = 0;
end
endgenerate
generate
if (FEATURE_DMMU!="NONE") begin : dmmu_gen
wire [OPTION_OPERAND_WIDTH-1:0] virt_addr;
wire dmmu_spr_bus_stb;
wire dmmu_enable;
assign virt_addr = dc_adr;
// small hack to delay dmmu spr reads by one cycle
// ideally the spr accesses should work so that the address is presented
// in execute stage and the delayed data should be available in control
// stage, but this is not how things currently work.
assign dmmu_spr_bus_stb = spr_bus_stb_i & (!padv_ctrl_i | spr_bus_we_i);
assign tlb_reload_pagefault_clear = !ctrl_op_lsu; // use pipeline_flush_i?
assign dmmu_enable = dmmu_enable_i & !pipeline_flush_i;
/* mor1kx_dmmu AUTO_TEMPLATE (
.enable_i (dmmu_enable),
.phys_addr_o (dmmu_phys_addr),
.cache_inhibit_o (dmmu_cache_inhibit),
.op_store_i (ctrl_op_lsu_store_i),
.op_load_i (ctrl_op_lsu_load_i),
.tlb_miss_o (tlb_miss),
.pagefault_o (pagefault),
.tlb_reload_req_o (tlb_reload_req),
.tlb_reload_busy_o (tlb_reload_busy),
.tlb_reload_addr_o (tlb_reload_addr),
.tlb_reload_pagefault_o (tlb_reload_pagefault),
.tlb_reload_ack_i (tlb_reload_ack),
.tlb_reload_data_i (tlb_reload_data),
.tlb_reload_pagefault_clear_i (tlb_reload_pagefault_clear),
.spr_bus_dat_o (spr_bus_dat_dmmu_o),
.spr_bus_ack_o (spr_bus_ack_dmmu_o),
.spr_bus_stb_i (dmmu_spr_bus_stb),
.virt_addr_i (virt_addr),
.virt_addr_match_i (ctrl_lsu_adr_i),
); */
mor1kx_dmmu
#(
.FEATURE_DMMU_HW_TLB_RELOAD(FEATURE_DMMU_HW_TLB_RELOAD),
.OPTION_OPERAND_WIDTH(OPTION_OPERAND_WIDTH),
.OPTION_DMMU_SET_WIDTH(OPTION_DMMU_SET_WIDTH),
.OPTION_DMMU_WAYS(OPTION_DMMU_WAYS)
)
mor1kx_dmmu
(/*AUTOINST*/
// Outputs
.phys_addr_o (dmmu_phys_addr), // Templated
.cache_inhibit_o (dmmu_cache_inhibit), // Templated
.tlb_miss_o (tlb_miss), // Templated
.pagefault_o (pagefault), // Templated
.tlb_reload_req_o (tlb_reload_req), // Templated
.tlb_reload_busy_o (tlb_reload_busy), // Templated
.tlb_reload_addr_o (tlb_reload_addr), // Templated
.tlb_reload_pagefault_o (tlb_reload_pagefault), // Templated
.spr_bus_dat_o (spr_bus_dat_dmmu_o), // Templated
.spr_bus_ack_o (spr_bus_ack_dmmu_o), // Templated
// Inputs
.clk (clk),
.rst (rst),
.enable_i (dmmu_enable), // Templated
.virt_addr_i (virt_addr), // Templated
.virt_addr_match_i (ctrl_lsu_adr_i), // Templated
.op_store_i (ctrl_op_lsu_store_i), // Templated
.op_load_i (ctrl_op_lsu_load_i), // Templated
.supervisor_mode_i (supervisor_mode_i),
.tlb_reload_ack_i (tlb_reload_ack), // Templated
.tlb_reload_data_i (tlb_reload_data), // Templated
.tlb_reload_pagefault_clear_i (tlb_reload_pagefault_clear), // Templated
.spr_bus_addr_i (spr_bus_addr_i[15:0]),
.spr_bus_we_i (spr_bus_we_i),
.spr_bus_stb_i (dmmu_spr_bus_stb), // Templated
.spr_bus_dat_i (spr_bus_dat_i[OPTION_OPERAND_WIDTH-1:0]));
end else begin
assign dmmu_cache_inhibit = 0;
assign tlb_miss = 0;
assign pagefault = 0;
assign tlb_reload_busy = 0;
assign tlb_reload_req = 0;
assign tlb_reload_pagefault = 0;
end
endgenerate
endmodule // mor1kx_lsu_cappuccino
|
`define PORTS_P 3
`define BANKS_P 3
`define BANK_SIZE_P 1024
`define DATA_WIDTH_P 32 // multiple of 8
/*************************** TEST RATIONALE **********************************
The instantiated multi-port banked memory is completely written by data in the
format {<data_width/8>{<src port number>, <dest bank number>}. The written data
is read and tallied. Then this module tries to fill the memory completely with 1s
by setting mask_i to 111...1 to test the masking capability of UUT.
******************************************************************************/
module test_bsg;
#(
parameter data_width_p = `DATA_WIDTH_P,
parameter bank_size_p = `BANK_SIZE_P,
parameter ports_p = `PORTS_P,
parameter banks_p = `BANKS_P,
parameter lg_banks_p = `BSG_SAFE_CLOG2(banks_p),
parameter bank_addr_width_p = `BSG_SAFE_CLOG2(bank_size_p),
parameter addr_width_p = ((banks_p == 1) ? 0 : lg_banks_p)
+ bank_addr_width_p,
parameter cycle_time_p = 20,
parameter reset_cycles_lo_p=1,
parameter reset_cycles_hi_p=5
);
// clock and reset generation
wire clk;
wire reset;
bsg_nonsynth_clock_gen #( .cycle_time_p(cycle_time_p)
) clock_gen
( .o(clk)
);
bsg_nonsynth_reset_gen #( .num_clocks_p (1)
, .reset_cycles_lo_p(reset_cycles_lo_p)
, .reset_cycles_hi_p(reset_cycles_hi_p)
) reset_gen
( .clk_i (clk)
, .async_reset_o(reset)
);
/* TEST SIGNALS */
// input
logic [ports_p-1:0][0:0] test_input_v, test_input_w;
logic [ports_p-1:0][addr_width_p-1:0] test_input_addr, test_input_addr_r;
logic [ports_p-1:0][data_width_p-1:0] test_input_data;
logic [ports_p-1:0][(data_width_p>>3)-1:0] test_input_mask;
// output
logic [ports_p-1:0][0:0] test_output_yumi, test_output_v;
logic [ports_p-1:0][data_width_p-1:0] test_output_data;
/*always_ff @(negedge clk)
$strobe("v_i:%0p w_i:%0p addr_i:%b data_i:%b mask_i:%b\n"
, test_input_v, test_input_w, test_input_addr
, test_input_data, test_input_mask
, "v_o:%0p yumi_o:%0p data_o:%b\n"
, test_output_v, test_output_yumi, test_output_data
);*/
initial
begin
$display("\n");
$display("===========================================================");
$display("testing bsg_mem_banked_crossbar with ...");
$display("DATA_WIDTH : %0d", data_width_p);
$display("ADDR_WIDTH : %0d", addr_width_p);
$display("BANKS : %0d", banks_p);
$display("PORTS : %0d", ports_p);
$display("BANK_SIZE : %0d\n", bank_size_p);
end
/* TEST STIMULI */
logic [ports_p-1:0] finish_main_r, finish_mask_r;
logic [ports_p-1:0][lg_banks_p-1:0] bank_num, bank_num_r;
logic [ports_p-1:0][bank_addr_width_p-1:0] bank_addr;
genvar i;
for(i=0; i<ports_p; i=i+1)
begin
// address and control
assign test_input_addr[i] = (banks_p == 1) ?
bank_addr[i]
: {bank_num[i], bank_addr[i]};
always_ff @(posedge clk)
begin
if(reset)
begin
bank_num[i] <= 0;
bank_addr[i] <= i;
test_input_v[i] <= 1'b1;
test_input_w[i] <= 1'b1;
test_input_mask[i] <= {(data_width_p>>3){1'b1}}; // MBT
end
else
begin
if(test_output_yumi[i])
begin
if((bank_addr[i]+ports_p) < bank_size_p)
bank_addr[i] <= bank_addr[i] + ports_p;
else
begin
bank_addr[i] <= i;
bank_num[i] <= bank_num[i] + 1;
end
if((bank_num[i]==banks_p-1) & (bank_addr[i]+ports_p >= bank_size_p))
begin
test_input_v[i] <= test_input_w[i];
test_input_w[i] <= 1'b0;
bank_num[i] <= 0;
bank_addr[i] <= i;
end
end
if(~test_input_v[i] & ~finish_mask_r[i])
begin
test_input_v[i] <= 1'b1;
test_input_w[i] <= 1'b1;
test_input_mask[i] <= 0; // MBT
end
end
end
// data
assign test_input_data[i] = (test_input_mask[i])?
{(data_width_p/8){4'(i), 4'(bank_num[i])}}
:{data_width_p{1'b1}};
end
/* UUT */
bsg_mem_banked_crossbar #( .bank_size_p (bank_size_p)
,.num_ports_p (ports_p)
,.num_banks_p (banks_p)
,.data_width_p (data_width_p)
) UUT
( .clk_i (clk)
,.reset_i (reset)
,.reverse_pr_i(1'b0)
,.v_i (test_input_v)
,.w_i (test_input_w)
,.addr_i (test_input_addr)
,.data_i (test_input_data)
,.mask_i (test_input_mask)
,.yumi_o (test_output_yumi)
,.v_o (test_output_v)
,.data_o (test_output_data)
);
/* Verification */
always_ff @(posedge clk)
if(|test_input_v)
assert(|test_output_yumi)
else $error("Error at time: %d, no transaction in a cycle", $time);
for(i=0; i<ports_p; i=i+1)
begin
always_ff @(posedge clk)
begin
bank_num_r[i] <= bank_num[i];
test_input_addr_r[i] <= test_input_addr[i];
if(test_output_v[i] & ~reset)
assert(test_output_data[i] == {(data_width_p/8){4'(i), 4'(bank_num_r[i])}})
else $error("Error while accessing %b from port: %0d, data was %b", test_input_addr_r[i], i, test_output_data[i]);
end
end
/* FINISH */
for(i=0; i<ports_p; i=i+1)
always_ff @(posedge clk)
begin
if(reset)
begin
finish_main_r[i] <= 1'b0;
finish_mask_r[i] <= 1'b0;
end
else
begin
if(~test_input_v[i])
finish_main_r[i] <= 1'b1;
if(finish_main_r[i] & (~test_input_v[i]))
finish_mask_r[i] <= 1'b1;
end
end
always_ff @(posedge clk)
if((&finish_main_r) & (&finish_mask_r))
begin
$display("============================================================");
$finish;
end
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : mig_7series_v2_3_ddr_phy_tempmon.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Dec 20 2013
// \___\/\___\
//
//Device : 7 Series
//Design Name : DDR3 SDRAM
//Purpose : Monitors chip temperature via the XADC and adjusts the
// stage 2 tap values as appropriate.
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1 ps / 1 ps
module mig_7series_v2_3_ddr_phy_tempmon #
(
parameter TCQ = 100, // Register delay (simulation only)
// Temperature bands must be in order. To disable bands, set to extreme.
parameter TEMP_INCDEC = 1465, // Degrees C * 100 (14.65 * 100)
parameter TEMP_HYST = 1,
parameter TEMP_MIN_LIMIT = 12'h8ac,
parameter TEMP_MAX_LIMIT = 12'hca4
)
(
input clk, // Fabric clock
input rst, // System reset
input calib_complete, // Calibration complete
input tempmon_sample_en, // Signal to enable sampling
input [11:0] device_temp, // Current device temperature
output tempmon_pi_f_inc, // Increment PHASER_IN taps
output tempmon_pi_f_dec, // Decrement PHASER_IN taps
output tempmon_sel_pi_incdec // Assume control of PHASER_IN taps
);
// translate hysteresis into XADC units
localparam HYST_OFFSET = (TEMP_HYST * 4096) / 504;
localparam TEMP_INCDEC_OFFSET = ((TEMP_INCDEC * 4096) / 50400) ;
// Temperature sampler FSM encoding
localparam IDLE = 11'b000_0000_0001;
localparam INIT = 11'b000_0000_0010;
localparam FOUR_INC = 11'b000_0000_0100;
localparam THREE_INC = 11'b000_0000_1000;
localparam TWO_INC = 11'b000_0001_0000;
localparam ONE_INC = 11'b000_0010_0000;
localparam NEUTRAL = 11'b000_0100_0000;
localparam ONE_DEC = 11'b000_1000_0000;
localparam TWO_DEC = 11'b001_0000_0000;
localparam THREE_DEC = 11'b010_0000_0000;
localparam FOUR_DEC = 11'b100_0000_0000;
//===========================================================================
// Reg declarations
//===========================================================================
// Output port flops. Inc and dec are mutex.
reg pi_f_dec; // Flop output
reg pi_f_inc; // Flop output
reg pi_f_dec_nxt; // FSM output
reg pi_f_inc_nxt; // FSM output
// FSM state
reg [10:0] tempmon_state;
reg [10:0] tempmon_state_nxt;
// FSM output used to capture the initial device termperature
reg tempmon_state_init;
// Flag to indicate the initial device temperature is captured and normal operation can begin
reg tempmon_init_complete;
// Temperature band/state boundaries
reg [11:0] four_inc_max_limit;
reg [11:0] three_inc_max_limit;
reg [11:0] two_inc_max_limit;
reg [11:0] one_inc_max_limit;
reg [11:0] neutral_max_limit;
reg [11:0] one_dec_max_limit;
reg [11:0] two_dec_max_limit;
reg [11:0] three_dec_max_limit;
reg [11:0] three_inc_min_limit;
reg [11:0] two_inc_min_limit;
reg [11:0] one_inc_min_limit;
reg [11:0] neutral_min_limit;
reg [11:0] one_dec_min_limit;
reg [11:0] two_dec_min_limit;
reg [11:0] three_dec_min_limit;
reg [11:0] four_dec_min_limit;
reg [11:0] device_temp_init;
// Flops for capturing and storing the current device temperature
reg tempmon_sample_en_101;
reg tempmon_sample_en_102;
reg [11:0] device_temp_101;
reg [11:0] device_temp_capture_102;
reg update_temp_102;
// Flops for comparing temperature to max limits
reg temp_cmp_four_inc_max_102;
reg temp_cmp_three_inc_max_102;
reg temp_cmp_two_inc_max_102;
reg temp_cmp_one_inc_max_102;
reg temp_cmp_neutral_max_102;
reg temp_cmp_one_dec_max_102;
reg temp_cmp_two_dec_max_102;
reg temp_cmp_three_dec_max_102;
// Flops for comparing temperature to min limits
reg temp_cmp_three_inc_min_102;
reg temp_cmp_two_inc_min_102;
reg temp_cmp_one_inc_min_102;
reg temp_cmp_neutral_min_102;
reg temp_cmp_one_dec_min_102;
reg temp_cmp_two_dec_min_102;
reg temp_cmp_three_dec_min_102;
reg temp_cmp_four_dec_min_102;
//===========================================================================
// Overview and temperature band limits
//===========================================================================
// The main feature of the tempmon block is an FSM that tracks the temerature provided by the ADC and decides if the phaser needs to be adjusted. The FSM
// has nine temperature bands or states, centered around an initial device temperature. The name of each state is the net number of phaser increments or
// decrements that have been issued in getting to the state. There are two temperature boundaries or limits between adjacent states. These two boundaries are
// offset by a small amount to provide hysteresis. The max limits are the boundaries that are used to determine when to move to the next higher temperature state
// and decrement the phaser. The min limits determine when to move to the next lower temperature state and increment the phaser. The limits are calculated when
// the initial device temperature is taken, and will always be at fixed offsets from the initial device temperature. States with limits below 0C or above
// 125C will never be entered.
// Temperature lowest highest
// <------------------------------------------------------------------------------------------------------------------------------------------------>
//
// Temp four three two one neutral one two three four
// band/state inc inc inc inc dec dec dec dec
//
// Max limits |<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|
// Min limits |<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->| |
// | | | | | | |
// | | | | | | |
// three_inc_min_limit | HYST_OFFSET--->| |<-- | four_dec_min_limit |
// | device_temp_init |
// four_inc_max_limit three_dec_max_limit
// Boundaries for moving from lower temp bands to higher temp bands.
// Note that only three_dec_max_limit can roll over, assuming device_temp_init is between 0C and 125C and TEMP_INCDEC_OFFSET is 14.65C,
// and none of the min or max limits can roll under. So three_dec_max_limit has a check for being out of the 0x0 to 0xFFF range.
wire [11:0] four_inc_max_limit_nxt = device_temp_init - 7*TEMP_INCDEC_OFFSET; // upper boundary of lowest temp band
wire [11:0] three_inc_max_limit_nxt = device_temp_init - 5*TEMP_INCDEC_OFFSET;
wire [11:0] two_inc_max_limit_nxt = device_temp_init - 3*TEMP_INCDEC_OFFSET;
wire [11:0] one_inc_max_limit_nxt = device_temp_init - TEMP_INCDEC_OFFSET;
wire [11:0] neutral_max_limit_nxt = device_temp_init + TEMP_INCDEC_OFFSET; // upper boundary of init temp band
wire [11:0] one_dec_max_limit_nxt = device_temp_init + 3*TEMP_INCDEC_OFFSET;
wire [11:0] two_dec_max_limit_nxt = device_temp_init + 5*TEMP_INCDEC_OFFSET;
wire [12:0] three_dec_max_limit_tmp = device_temp_init + 7*TEMP_INCDEC_OFFSET; // upper boundary of 2nd highest temp band
wire [11:0] three_dec_max_limit_nxt = three_dec_max_limit_tmp[12] ? 12'hFFF : three_dec_max_limit_tmp[11:0];
// Boundaries for moving from higher temp bands to lower temp bands
wire [11:0] three_inc_min_limit_nxt = four_inc_max_limit - HYST_OFFSET; // lower boundary of 2nd lowest temp band
wire [11:0] two_inc_min_limit_nxt = three_inc_max_limit - HYST_OFFSET;
wire [11:0] one_inc_min_limit_nxt = two_inc_max_limit - HYST_OFFSET;
wire [11:0] neutral_min_limit_nxt = one_inc_max_limit - HYST_OFFSET; // lower boundary of init temp band
wire [11:0] one_dec_min_limit_nxt = neutral_max_limit - HYST_OFFSET;
wire [11:0] two_dec_min_limit_nxt = one_dec_max_limit - HYST_OFFSET;
wire [11:0] three_dec_min_limit_nxt = two_dec_max_limit - HYST_OFFSET;
wire [11:0] four_dec_min_limit_nxt = three_dec_max_limit - HYST_OFFSET; // lower boundary of highest temp band
//===========================================================================
// Capture device temperature
//===========================================================================
// There is a three stage pipeline used to capture temperature, calculate the next state
// of the FSM, and update the tempmon outputs.
//
// Stage 100 Inputs device_temp and tempmon_sample_en become valid and are flopped.
// Input device_temp is compared to ADC codes for 0C and 125C and limited
// at the flop input if needed.
//
// Stage 101 The flopped version of device_temp is compared to the FSM temperature band boundaries
// to determine if a state change is needed. State changes are only enabled on the
// rising edge of the flopped tempmon_sample_en signal. If there is a state change a phaser
// increment or decrement signal is generated and flopped.
//
// Stage 102 The flopped versions of the phaser inc/dec signals drive the module outputs.
// Limit device_temp to 0C to 125C and assign it to flop input device_temp_100
// temp C = ( ( ADC CODE * 503.975 ) / 4096 ) - 273.15
wire device_temp_high = device_temp > TEMP_MAX_LIMIT;
wire device_temp_low = device_temp < TEMP_MIN_LIMIT;
wire [11:0] device_temp_100 = ( { 12 { device_temp_high } } & TEMP_MAX_LIMIT )
| ( { 12 { device_temp_low } } & TEMP_MIN_LIMIT )
| ( { 12 { ~device_temp_high & ~device_temp_low } } & device_temp );
// Capture/hold the initial temperature used in setting temperature bands and set init complete flag
// to enable normal sample operation.
wire [11:0] device_temp_init_nxt = tempmon_state_init ? device_temp_101 : device_temp_init;
wire tempmon_init_complete_nxt = tempmon_state_init ? 1'b1 : tempmon_init_complete;
// Capture/hold the current temperature on the sample enable signal rising edge after init is complete.
// The captured current temp is not used functionaly. It is just useful for debug and waveform review.
wire update_temp_101 = tempmon_init_complete & ~tempmon_sample_en_102 & tempmon_sample_en_101;
wire [11:0] device_temp_capture_101 = update_temp_101 ? device_temp_101 : device_temp_capture_102;
//===========================================================================
// Generate FSM arc signals
//===========================================================================
// Temperature comparisons for increasing temperature.
wire temp_cmp_four_inc_max_101 = device_temp_101 >= four_inc_max_limit ;
wire temp_cmp_three_inc_max_101 = device_temp_101 >= three_inc_max_limit ;
wire temp_cmp_two_inc_max_101 = device_temp_101 >= two_inc_max_limit ;
wire temp_cmp_one_inc_max_101 = device_temp_101 >= one_inc_max_limit ;
wire temp_cmp_neutral_max_101 = device_temp_101 >= neutral_max_limit ;
wire temp_cmp_one_dec_max_101 = device_temp_101 >= one_dec_max_limit ;
wire temp_cmp_two_dec_max_101 = device_temp_101 >= two_dec_max_limit ;
wire temp_cmp_three_dec_max_101 = device_temp_101 >= three_dec_max_limit ;
// Temperature comparisons for decreasing temperature.
wire temp_cmp_three_inc_min_101 = device_temp_101 < three_inc_min_limit ;
wire temp_cmp_two_inc_min_101 = device_temp_101 < two_inc_min_limit ;
wire temp_cmp_one_inc_min_101 = device_temp_101 < one_inc_min_limit ;
wire temp_cmp_neutral_min_101 = device_temp_101 < neutral_min_limit ;
wire temp_cmp_one_dec_min_101 = device_temp_101 < one_dec_min_limit ;
wire temp_cmp_two_dec_min_101 = device_temp_101 < two_dec_min_limit ;
wire temp_cmp_three_dec_min_101 = device_temp_101 < three_dec_min_limit ;
wire temp_cmp_four_dec_min_101 = device_temp_101 < four_dec_min_limit ;
// FSM arcs for increasing temperature.
wire temp_gte_four_inc_max = update_temp_102 & temp_cmp_four_inc_max_102;
wire temp_gte_three_inc_max = update_temp_102 & temp_cmp_three_inc_max_102;
wire temp_gte_two_inc_max = update_temp_102 & temp_cmp_two_inc_max_102;
wire temp_gte_one_inc_max = update_temp_102 & temp_cmp_one_inc_max_102;
wire temp_gte_neutral_max = update_temp_102 & temp_cmp_neutral_max_102;
wire temp_gte_one_dec_max = update_temp_102 & temp_cmp_one_dec_max_102;
wire temp_gte_two_dec_max = update_temp_102 & temp_cmp_two_dec_max_102;
wire temp_gte_three_dec_max = update_temp_102 & temp_cmp_three_dec_max_102;
// FSM arcs for decreasing temperature.
wire temp_lte_three_inc_min = update_temp_102 & temp_cmp_three_inc_min_102;
wire temp_lte_two_inc_min = update_temp_102 & temp_cmp_two_inc_min_102;
wire temp_lte_one_inc_min = update_temp_102 & temp_cmp_one_inc_min_102;
wire temp_lte_neutral_min = update_temp_102 & temp_cmp_neutral_min_102;
wire temp_lte_one_dec_min = update_temp_102 & temp_cmp_one_dec_min_102;
wire temp_lte_two_dec_min = update_temp_102 & temp_cmp_two_dec_min_102;
wire temp_lte_three_dec_min = update_temp_102 & temp_cmp_three_dec_min_102;
wire temp_lte_four_dec_min = update_temp_102 & temp_cmp_four_dec_min_102;
//===========================================================================
// Implement FSM
//===========================================================================
// In addition to the nine temperature states, there are also IDLE and INIT states.
// The INIT state triggers the calculation of the temperature boundaries between the
// other states. After INIT, the FSM will always go to the NEUTRAL state. There is
// no timing restriction required between calib_complete and tempmon_sample_en.
always @(*) begin
tempmon_state_nxt = tempmon_state;
tempmon_state_init = 1'b0;
pi_f_inc_nxt = 1'b0;
pi_f_dec_nxt = 1'b0;
casez (tempmon_state)
IDLE: begin
if (calib_complete) tempmon_state_nxt = INIT;
end
INIT: begin
tempmon_state_nxt = NEUTRAL;
tempmon_state_init = 1'b1;
end
FOUR_INC: begin
if (temp_gte_four_inc_max) begin
tempmon_state_nxt = THREE_INC;
pi_f_dec_nxt = 1'b1;
end
end
THREE_INC: begin
if (temp_gte_three_inc_max) begin
tempmon_state_nxt = TWO_INC;
pi_f_dec_nxt = 1'b1;
end
else if (temp_lte_three_inc_min) begin
tempmon_state_nxt = FOUR_INC;
pi_f_inc_nxt = 1'b1;
end
end
TWO_INC: begin
if (temp_gte_two_inc_max) begin
tempmon_state_nxt = ONE_INC;
pi_f_dec_nxt = 1'b1;
end
else if (temp_lte_two_inc_min) begin
tempmon_state_nxt = THREE_INC;
pi_f_inc_nxt = 1'b1;
end
end
ONE_INC: begin
if (temp_gte_one_inc_max) begin
tempmon_state_nxt = NEUTRAL;
pi_f_dec_nxt = 1'b1;
end
else if (temp_lte_one_inc_min) begin
tempmon_state_nxt = TWO_INC;
pi_f_inc_nxt = 1'b1;
end
end
NEUTRAL: begin
if (temp_gte_neutral_max) begin
tempmon_state_nxt = ONE_DEC;
pi_f_dec_nxt = 1'b1;
end
else if (temp_lte_neutral_min) begin
tempmon_state_nxt = ONE_INC;
pi_f_inc_nxt = 1'b1;
end
end
ONE_DEC: begin
if (temp_gte_one_dec_max) begin
tempmon_state_nxt = TWO_DEC;
pi_f_dec_nxt = 1'b1;
end
else if (temp_lte_one_dec_min) begin
tempmon_state_nxt = NEUTRAL;
pi_f_inc_nxt = 1'b1;
end
end
TWO_DEC: begin
if (temp_gte_two_dec_max) begin
tempmon_state_nxt = THREE_DEC;
pi_f_dec_nxt = 1'b1;
end
else if (temp_lte_two_dec_min) begin
tempmon_state_nxt = ONE_DEC;
pi_f_inc_nxt = 1'b1;
end
end
THREE_DEC: begin
if (temp_gte_three_dec_max) begin
tempmon_state_nxt = FOUR_DEC;
pi_f_dec_nxt = 1'b1;
end
else if (temp_lte_three_dec_min) begin
tempmon_state_nxt = TWO_DEC;
pi_f_inc_nxt = 1'b1;
end
end
FOUR_DEC: begin
if (temp_lte_four_dec_min) begin
tempmon_state_nxt = THREE_DEC;
pi_f_inc_nxt = 1'b1;
end
end
default: begin
tempmon_state_nxt = IDLE;
end
endcase
end //always
//synopsys translate_off
reg [71:0] tempmon_state_name;
always @(*) casez (tempmon_state)
IDLE : tempmon_state_name = "IDLE";
INIT : tempmon_state_name = "INIT";
FOUR_INC : tempmon_state_name = "FOUR_INC";
THREE_INC : tempmon_state_name = "THREE_INC";
TWO_INC : tempmon_state_name = "TWO_INC";
ONE_INC : tempmon_state_name = "ONE_INC";
NEUTRAL : tempmon_state_name = "NEUTRAL";
ONE_DEC : tempmon_state_name = "ONE_DEC";
TWO_DEC : tempmon_state_name = "TWO_DEC";
THREE_DEC : tempmon_state_name = "THREE_DEC";
FOUR_DEC : tempmon_state_name = "FOUR_DEC";
default : tempmon_state_name = "BAD_STATE";
endcase
//synopsys translate_on
//===========================================================================
// Generate final output and implement flops
//===========================================================================
// Generate output
assign tempmon_pi_f_inc = pi_f_inc;
assign tempmon_pi_f_dec = pi_f_dec;
assign tempmon_sel_pi_incdec = pi_f_inc | pi_f_dec;
// Implement reset flops
always @(posedge clk) begin
if(rst) begin
tempmon_state <= #TCQ 11'b000_0000_0001;
pi_f_inc <= #TCQ 1'b0;
pi_f_dec <= #TCQ 1'b0;
four_inc_max_limit <= #TCQ 12'b0;
three_inc_max_limit <= #TCQ 12'b0;
two_inc_max_limit <= #TCQ 12'b0;
one_inc_max_limit <= #TCQ 12'b0;
neutral_max_limit <= #TCQ 12'b0;
one_dec_max_limit <= #TCQ 12'b0;
two_dec_max_limit <= #TCQ 12'b0;
three_dec_max_limit <= #TCQ 12'b0;
three_inc_min_limit <= #TCQ 12'b0;
two_inc_min_limit <= #TCQ 12'b0;
one_inc_min_limit <= #TCQ 12'b0;
neutral_min_limit <= #TCQ 12'b0;
one_dec_min_limit <= #TCQ 12'b0;
two_dec_min_limit <= #TCQ 12'b0;
three_dec_min_limit <= #TCQ 12'b0;
four_dec_min_limit <= #TCQ 12'b0;
device_temp_init <= #TCQ 12'b0;
tempmon_init_complete <= #TCQ 1'b0;
tempmon_sample_en_101 <= #TCQ 1'b0;
tempmon_sample_en_102 <= #TCQ 1'b0;
device_temp_101 <= #TCQ 12'b0;
device_temp_capture_102 <= #TCQ 12'b0;
end
else begin
tempmon_state <= #TCQ tempmon_state_nxt;
pi_f_inc <= #TCQ pi_f_inc_nxt;
pi_f_dec <= #TCQ pi_f_dec_nxt;
four_inc_max_limit <= #TCQ four_inc_max_limit_nxt;
three_inc_max_limit <= #TCQ three_inc_max_limit_nxt;
two_inc_max_limit <= #TCQ two_inc_max_limit_nxt;
one_inc_max_limit <= #TCQ one_inc_max_limit_nxt;
neutral_max_limit <= #TCQ neutral_max_limit_nxt;
one_dec_max_limit <= #TCQ one_dec_max_limit_nxt;
two_dec_max_limit <= #TCQ two_dec_max_limit_nxt;
three_dec_max_limit <= #TCQ three_dec_max_limit_nxt;
three_inc_min_limit <= #TCQ three_inc_min_limit_nxt;
two_inc_min_limit <= #TCQ two_inc_min_limit_nxt;
one_inc_min_limit <= #TCQ one_inc_min_limit_nxt;
neutral_min_limit <= #TCQ neutral_min_limit_nxt;
one_dec_min_limit <= #TCQ one_dec_min_limit_nxt;
two_dec_min_limit <= #TCQ two_dec_min_limit_nxt;
three_dec_min_limit <= #TCQ three_dec_min_limit_nxt;
four_dec_min_limit <= #TCQ four_dec_min_limit_nxt;
device_temp_init <= #TCQ device_temp_init_nxt;
tempmon_init_complete <= #TCQ tempmon_init_complete_nxt;
tempmon_sample_en_101 <= #TCQ tempmon_sample_en;
tempmon_sample_en_102 <= #TCQ tempmon_sample_en_101;
device_temp_101 <= #TCQ device_temp_100;
device_temp_capture_102 <= #TCQ device_temp_capture_101;
end
end
// Implement non-reset flops
always @(posedge clk) begin
temp_cmp_four_inc_max_102 <= #TCQ temp_cmp_four_inc_max_101;
temp_cmp_three_inc_max_102 <= #TCQ temp_cmp_three_inc_max_101;
temp_cmp_two_inc_max_102 <= #TCQ temp_cmp_two_inc_max_101;
temp_cmp_one_inc_max_102 <= #TCQ temp_cmp_one_inc_max_101;
temp_cmp_neutral_max_102 <= #TCQ temp_cmp_neutral_max_101;
temp_cmp_one_dec_max_102 <= #TCQ temp_cmp_one_dec_max_101;
temp_cmp_two_dec_max_102 <= #TCQ temp_cmp_two_dec_max_101;
temp_cmp_three_dec_max_102 <= #TCQ temp_cmp_three_dec_max_101;
temp_cmp_three_inc_min_102 <= #TCQ temp_cmp_three_inc_min_101;
temp_cmp_two_inc_min_102 <= #TCQ temp_cmp_two_inc_min_101;
temp_cmp_one_inc_min_102 <= #TCQ temp_cmp_one_inc_min_101;
temp_cmp_neutral_min_102 <= #TCQ temp_cmp_neutral_min_101;
temp_cmp_one_dec_min_102 <= #TCQ temp_cmp_one_dec_min_101;
temp_cmp_two_dec_min_102 <= #TCQ temp_cmp_two_dec_min_101;
temp_cmp_three_dec_min_102 <= #TCQ temp_cmp_three_dec_min_101;
temp_cmp_four_dec_min_102 <= #TCQ temp_cmp_four_dec_min_101;
update_temp_102 <= #TCQ update_temp_101;
end
endmodule
|
// ZX-Evo Base Configuration (c) NedoPC 2008,2009,2010,2011,2012,2013,2014
//
// 'PFD' design based on ZEK code
/*
This file is part of ZX-Evo Base Configuration firmware.
ZX-Evo Base Configuration firmware is free software:
you can redistribute it and/or modify it under the terms of
the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
ZX-Evo Base Configuration firmware is distributed in the hope that
it will be useful, but WITHOUT ANY WARRANTY; without even
the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
See the GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with ZX-Evo Base Configuration firmware.
If not, see <http://www.gnu.org/licenses/>.
*/
module fapch_zek
(
input wire fclk,
input wire rdat_n,
output reg vg_rclk,
output reg vg_rawr
);
reg [3:0] rdat_sr;
reg rawr_sync;
reg rdat_n_r;
always @ (posedge fclk)
begin
rdat_n_r <= rdat_n;
rdat_sr <= { rdat_sr[2:0], rdat_n_r };
if (rdat_sr == 4'hF || rdat_sr == 4'h0)
rawr_sync <= rdat_sr[3];
end
// rawr
reg [4:0] rawr_sr;
always @ (posedge fclk)
begin
rawr_sr <= { rawr_sr[3:0], rawr_sync };
vg_rawr <= !(rawr_sr[4] && !rawr_sr[0] ); // rawr 140ns
end
// rclk
reg [5:0] counter = 0;
wire[5:0] delta = 27 - counter;
wire[5:0] shift = { delta[5], delta[5], delta[4:1] }; // sign div
wire[5:0] inc = rawr_sr[1:0] == 2'b10 ? shift : 1;
always @ (posedge fclk)
begin
if (counter < 55)
counter <= counter + inc;
else
begin
counter <= 0;
vg_rclk = ~vg_rclk;
end
end
initial
vg_rclk = 0;
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: txc_engine_classic.v
// Version: 1.0
// Verilog Standard: Verilog-2001
// Description: The TXR Engine takes unformatted completions, formats
// these packets into "TLP's" or Transaction Layer Packets. These packets must
// meet max-request, max-payload, and payload termination requirements (see Read
// Completion Boundary). The TXR Engine does not check these requirements during
// operation, but may do so during simulation. This Engine is capable of
// operating at "line rate". This file also contains the txr_formatter module,
// which formats request headers.
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
`include "trellis.vh" // Defines the user-facing signal widths.
`include "tlp.vh" // Defines the endpoint-facing field widths in a TLP
module txr_engine_classic
#(parameter C_PCI_DATA_WIDTH = 128,
parameter C_PIPELINE_INPUT = 1,
parameter C_PIPELINE_OUTPUT = 0,
parameter C_MAX_PAYLOAD_DWORDS = 64,
parameter C_DEPTH_PACKETS = 10,
parameter C_VENDOR = "ALTERA")
(// Interface: Clocks
input CLK,
// Interface: Resets
input RST_IN, // Addition for RIFFA_RST
output DONE_TXR_RST,
// Interface: Configuration
input [`SIG_CPLID_W-1:0] CONFIG_COMPLETER_ID,
// Interface: TXR Classic
input TXR_TLP_READY,
output [C_PCI_DATA_WIDTH-1:0] TXR_TLP,
output TXR_TLP_VALID,
output TXR_TLP_START_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_TLP_START_OFFSET,
output TXR_TLP_END_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_TLP_END_OFFSET,
// Interface: TXR Engine
input TXR_DATA_VALID,
input [C_PCI_DATA_WIDTH-1:0] TXR_DATA,
input TXR_DATA_START_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_DATA_START_OFFSET,
input TXR_DATA_END_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_DATA_END_OFFSET,
output TXR_DATA_READY,
input TXR_META_VALID,
input [`SIG_FBE_W-1:0] TXR_META_FDWBE,
input [`SIG_LBE_W-1:0] TXR_META_LDWBE,
input [`SIG_ADDR_W-1:0] TXR_META_ADDR,
input [`SIG_LEN_W-1:0] TXR_META_LENGTH,
input [`SIG_TAG_W-1:0] TXR_META_TAG,
input [`SIG_TC_W-1:0] TXR_META_TC,
input [`SIG_ATTR_W-1:0] TXR_META_ATTR,
input [`SIG_TYPE_W-1:0] TXR_META_TYPE,
input TXR_META_EP,
output TXR_META_READY
);
localparam C_DATA_WIDTH = C_PCI_DATA_WIDTH;
localparam C_MAX_HDR_WIDTH = `TLP_MAXHDR_W;
localparam C_MAX_ALIGN_WIDTH = (C_VENDOR == "ALTERA") ? 32:
(C_VENDOR == "XILINX") ? 0 :
0;
localparam C_PIPELINE_FORMATTER_INPUT = C_PIPELINE_INPUT;
localparam C_PIPELINE_FORMATTER_OUTPUT = C_PIPELINE_OUTPUT;
localparam C_FORMATTER_DELAY = C_PIPELINE_FORMATTER_OUTPUT + C_PIPELINE_FORMATTER_INPUT;
/*AUTOWIRE*/
/*AUTOINPUT*/
///*AUTOOUTPUT*/
wire wTxHdrReady;
wire wTxHdrValid;
wire [C_MAX_HDR_WIDTH-1:0] wTxHdr;
wire [`SIG_TYPE_W-1:0] wTxType;
wire [`SIG_NONPAY_W-1:0] wTxHdrNonpayLen;
wire [`SIG_PACKETLEN_W-1:0] wTxHdrPacketLen;
wire [`SIG_LEN_W-1:0] wTxHdrPayloadLen;
wire wTxHdrNopayload;
assign DONE_TXR_RST = ~RST_IN;
txr_formatter_classic
#(
.C_PIPELINE_OUTPUT (C_PIPELINE_FORMATTER_OUTPUT),
.C_PIPELINE_INPUT (C_PIPELINE_FORMATTER_INPUT),
/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_MAX_HDR_WIDTH (C_MAX_HDR_WIDTH),
.C_MAX_ALIGN_WIDTH (C_MAX_ALIGN_WIDTH),
.C_VENDOR (C_VENDOR))
txr_formatter_inst
(
// Outputs
.TX_HDR_VALID (wTxHdrValid),
.TX_HDR (wTxHdr[C_MAX_HDR_WIDTH-1:0]),
.TX_HDR_NOPAYLOAD (wTxHdrNopayload),
.TX_HDR_PAYLOAD_LEN (wTxHdrPayloadLen[`SIG_LEN_W-1:0]),
.TX_HDR_NONPAY_LEN (wTxHdrNonpayLen[`SIG_NONPAY_W-1:0]),
.TX_HDR_PACKET_LEN (wTxHdrPacketLen[`SIG_PACKETLEN_W-1:0]),
// Inputs
.TX_HDR_READY (wTxHdrReady),
/*AUTOINST*/
// Outputs
.TXR_META_READY (TXR_META_READY),
// Inputs
.CLK (CLK),
.RST_IN (RST_IN),
.CONFIG_COMPLETER_ID (CONFIG_COMPLETER_ID[`SIG_CPLID_W-1:0]),
.TXR_META_VALID (TXR_META_VALID),
.TXR_META_FDWBE (TXR_META_FDWBE[`SIG_FBE_W-1:0]),
.TXR_META_LDWBE (TXR_META_LDWBE[`SIG_LBE_W-1:0]),
.TXR_META_ADDR (TXR_META_ADDR[`SIG_ADDR_W-1:0]),
.TXR_META_LENGTH (TXR_META_LENGTH[`SIG_LEN_W-1:0]),
.TXR_META_TAG (TXR_META_TAG[`SIG_TAG_W-1:0]),
.TXR_META_TC (TXR_META_TC[`SIG_TC_W-1:0]),
.TXR_META_ATTR (TXR_META_ATTR[`SIG_ATTR_W-1:0]),
.TXR_META_TYPE (TXR_META_TYPE[`SIG_TYPE_W-1:0]),
.TXR_META_EP (TXR_META_EP));
tx_engine
#(
.C_DATA_WIDTH (C_PCI_DATA_WIDTH),
/*AUTOINSTPARAM*/
// Parameters
.C_DEPTH_PACKETS (C_DEPTH_PACKETS),
.C_PIPELINE_INPUT (C_PIPELINE_INPUT),
.C_PIPELINE_OUTPUT (C_PIPELINE_OUTPUT),
.C_FORMATTER_DELAY (C_FORMATTER_DELAY),
.C_MAX_HDR_WIDTH (C_MAX_HDR_WIDTH),
.C_MAX_PAYLOAD_DWORDS (C_MAX_PAYLOAD_DWORDS),
.C_VENDOR (C_VENDOR))
txr_engine_inst
(
// Outputs
.TX_HDR_READY (wTxHdrReady),
.TX_DATA_READY (TXR_DATA_READY),
.TX_PKT (TXR_TLP[C_DATA_WIDTH-1:0]),
.TX_PKT_START_FLAG (TXR_TLP_START_FLAG),
.TX_PKT_START_OFFSET (TXR_TLP_START_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
.TX_PKT_END_FLAG (TXR_TLP_END_FLAG),
.TX_PKT_END_OFFSET (TXR_TLP_END_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
.TX_PKT_VALID (TXR_TLP_VALID),
// Inputs
.TX_HDR_VALID (wTxHdrValid),
.TX_HDR (wTxHdr[C_MAX_HDR_WIDTH-1:0]),
.TX_HDR_NOPAYLOAD (wTxHdrNopayload),
.TX_HDR_PAYLOAD_LEN (wTxHdrPayloadLen[`SIG_LEN_W-1:0]),
.TX_HDR_NONPAY_LEN (wTxHdrNonpayLen[`SIG_NONPAY_W-1:0]),
.TX_HDR_PACKET_LEN (wTxHdrPacketLen[`SIG_PACKETLEN_W-1:0]),
.TX_DATA_VALID (TXR_DATA_VALID),
.TX_DATA (TXR_DATA[C_DATA_WIDTH-1:0]),
.TX_DATA_START_FLAG (TXR_DATA_START_FLAG),
.TX_DATA_START_OFFSET (TXR_DATA_START_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
.TX_DATA_END_FLAG (TXR_DATA_END_FLAG),
.TX_DATA_END_OFFSET (TXR_DATA_END_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
.TX_PKT_READY (TXR_TLP_READY),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
endmodule
module txr_formatter_classic
#(
parameter C_PCI_DATA_WIDTH = 128,
parameter C_MAX_HDR_WIDTH = `TLP_MAXHDR_W,
parameter C_MAX_ALIGN_WIDTH = 32,
parameter C_PIPELINE_INPUT = 1,
parameter C_PIPELINE_OUTPUT = 1,
parameter C_VENDOR = "ALTERA"
)
(
// Interface: Clocks
input CLK,
// Interface: Resets
input RST_IN,
// Interface: Configuration
input [`SIG_CPLID_W-1:0] CONFIG_COMPLETER_ID,
// Interface: TXR
input TXR_META_VALID,
input [`SIG_FBE_W-1:0] TXR_META_FDWBE,
input [`SIG_LBE_W-1:0] TXR_META_LDWBE,
input [`SIG_ADDR_W-1:0] TXR_META_ADDR,
input [`SIG_LEN_W-1:0] TXR_META_LENGTH,
input [`SIG_TAG_W-1:0] TXR_META_TAG,
input [`SIG_TC_W-1:0] TXR_META_TC,
input [`SIG_ATTR_W-1:0] TXR_META_ATTR,
input [`SIG_TYPE_W-1:0] TXR_META_TYPE,
input TXR_META_EP,
output TXR_META_READY,
// Interface: TX HDR
output TX_HDR_VALID,
output [C_MAX_HDR_WIDTH-1:0] TX_HDR,
output [`SIG_LEN_W-1:0] TX_HDR_PAYLOAD_LEN,
output [`SIG_NONPAY_W-1:0] TX_HDR_NONPAY_LEN,
output [`SIG_PACKETLEN_W-1:0] TX_HDR_PACKET_LEN,
output TX_HDR_NOPAYLOAD,
input TX_HDR_READY
);
wire wWrReq;
wire [`TLP_FMT_W-1:0] wHdrLoFmt;
wire [63:0] wHdrLo;
wire [63:0] _wTxHdr;
wire wTxHdrReady;
wire wTxHdrValid;
wire [(`TLP_REQADDR_W/2)-1:0] wTxHdrAddr[1:0];
wire [(`TLP_REQADDR_W/2)-1:0] wTxHdrAddrDW0;
wire wTxHdr4DW;
wire wTxHdrAlignmentNeeded;
wire [C_MAX_HDR_WIDTH-1:0] wTxHdr;
wire [`SIG_TYPE_W-1:0] wTxType;
wire [`SIG_NONPAY_W-1:0] wTxHdrNonpayLen;
wire [`SIG_PACKETLEN_W-1:0] wTxHdrPacketLen;
wire [`SIG_LEN_W-1:0] wTxHdrPayloadLen;
wire wTxHdrNopayload;
assign wHdrLoFmt = {1'b0, TXR_META_TYPE[`TRLS_TYPE_PAY_I],1'bx};
// Reserved Fields
assign wHdrLo[`TLP_RSVD0_R] = `TLP_RSVD0_V;
assign wHdrLo[`TLP_ADDRTYPE_R] = `TLP_ADDRTYPE_W'b0;
assign wHdrLo[`TLP_TH_R] = `TLP_TH_W'b0;
assign wHdrLo[`TLP_RSVD1_R] = `TLP_RSVD1_V;
assign wHdrLo[`TLP_RSVD2_R] = `TLP_RSVD2_V;
// Generic Header Fields
assign wHdrLo[`TLP_LEN_R] = TXR_META_LENGTH;
assign wHdrLo[`TLP_EP_R] = TXR_META_EP;
assign wHdrLo[`TLP_TD_R] = `TLP_NODIGEST_V;
assign wHdrLo[`TLP_ATTR0_R] = TXR_META_ATTR[1:0];
assign wHdrLo[`TLP_ATTR1_R] = TXR_META_ATTR[2];
assign wHdrLo[`TLP_TYPE_R] = TXR_META_TYPE; // WORKAROUND
assign wHdrLo[`TLP_TC_R] = TXR_META_TC;
assign wHdrLo[`TLP_FMT_R] = wHdrLoFmt;
// Request Specific Fields
assign wHdrLo[`TLP_REQFBE_R] = TXR_META_FDWBE;
assign wHdrLo[`TLP_REQLBE_R] = TXR_META_LDWBE;
assign wHdrLo[`TLP_REQTAG_R] = TXR_META_TAG;
assign wHdrLo[`TLP_REQREQID_R] = CONFIG_COMPLETER_ID;
// Second header formatting stage
assign wTxHdr4DW = wTxHdrAddr[1] != 32'b0;
assign {wTxHdr[`TLP_FMT_R],wTxHdr[`TLP_TYPE_R]} = trellis_to_tlp_type(_wTxHdr[`TLP_TYPE_I +: `SIG_TYPE_W],wTxHdr4DW);
assign wTxHdr[`TLP_TYPE_I-1:0] = _wTxHdr[`TLP_TYPE_I-1:0];
assign wTxHdr[63:32] = _wTxHdr[63:32];
assign wTxHdr[127:64] = {wTxHdrAddr[~wTxHdr4DW],wTxHdrAddr[wTxHdr4DW]};
// Metadata, to the aligner
assign wTxHdrNopayload = ~wTxHdr[`TLP_PAYBIT_I];
assign wTxHdrAddrDW0 = wTxHdrAddr[0];
assign wTxHdrAlignmentNeeded = (wTxHdrAddrDW0[2] == wTxHdr4DW);
assign wTxHdrNonpayLen = {1'b0,{wTxHdr4DW,~wTxHdr4DW,~wTxHdr4DW}} + ((C_VENDOR == "ALTERA") ? {3'b0,(wTxHdrAlignmentNeeded & ~wTxHdrNopayload)}:0);
assign wTxHdrPayloadLen = wTxHdrNopayload ? 0 : wTxHdr[`TLP_LEN_R];
assign wTxHdrPacketLen = wTxHdrPayloadLen + wTxHdrNonpayLen;
pipeline
#(// Parameters
.C_DEPTH (C_PIPELINE_INPUT?1:0),
.C_WIDTH (C_MAX_HDR_WIDTH),
.C_USE_MEMORY (0)
/*AUTOINSTPARAM*/)
input_inst
(// Outputs
.WR_DATA_READY (TXR_META_READY),
.RD_DATA ({wTxHdrAddr[1],wTxHdrAddr[0],_wTxHdr[63:0]}),
.RD_DATA_VALID (wTxHdrValid),
// Inputs
.WR_DATA ({TXR_META_ADDR, wHdrLo}),
.WR_DATA_VALID (TXR_META_VALID),
.RD_DATA_READY (wTxHdrReady),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
pipeline
#(
// Parameters
.C_DEPTH (C_PIPELINE_OUTPUT?1:0),
.C_WIDTH (C_MAX_HDR_WIDTH+ 1 + `SIG_PACKETLEN_W + `SIG_LEN_W + `SIG_NONPAY_W),
.C_USE_MEMORY (0)
/*AUTOINSTPARAM*/)
output_inst
(
// Outputs
.WR_DATA_READY (wTxHdrReady),
.RD_DATA ({TX_HDR,TX_HDR_NOPAYLOAD,TX_HDR_PACKET_LEN,TX_HDR_PAYLOAD_LEN,TX_HDR_NONPAY_LEN}),
.RD_DATA_VALID (TX_HDR_VALID),
// Inputs
.WR_DATA ({wTxHdr,wTxHdrNopayload,wTxHdrPacketLen,wTxHdrPayloadLen,wTxHdrNonpayLen}),
.WR_DATA_VALID (wTxHdrValid),
.RD_DATA_READY (TX_HDR_READY),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
endmodule
// Local Variables:
// verilog-library-directories:("." "../../../common/" "../../common/")
// End:
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_hcmd_sq_arb # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
input pcie_user_clk,
input pcie_user_rst_n,
input [8:0] sq_rst_n,
input [8:0] sq_valid,
input [7:0] admin_sq_size,
input [7:0] io_sq1_size,
input [7:0] io_sq2_size,
input [7:0] io_sq3_size,
input [7:0] io_sq4_size,
input [7:0] io_sq5_size,
input [7:0] io_sq6_size,
input [7:0] io_sq7_size,
input [7:0] io_sq8_size,
input [C_PCIE_ADDR_WIDTH-1:2] admin_sq_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq1_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq2_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq3_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq4_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq5_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq6_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq7_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq8_bs_addr,
input [7:0] admin_sq_tail_ptr,
input [7:0] io_sq1_tail_ptr,
input [7:0] io_sq2_tail_ptr,
input [7:0] io_sq3_tail_ptr,
input [7:0] io_sq4_tail_ptr,
input [7:0] io_sq5_tail_ptr,
input [7:0] io_sq6_tail_ptr,
input [7:0] io_sq7_tail_ptr,
input [7:0] io_sq8_tail_ptr,
output arb_sq_rdy,
output [3:0] sq_qid,
output [C_PCIE_ADDR_WIDTH-1:2] hcmd_pcie_addr,
input sq_hcmd_ack
);
localparam S_ARB_HCMD = 5'b00001;
localparam S_LOAD_HEAD_PTR = 5'b00010;
localparam S_CALC_ADDR = 5'b00100;
localparam S_GNT_HCMD = 5'b01000;
localparam S_UPDATE_HEAD_PTR = 5'b10000;
reg [4:0] cur_state;
reg [4:0] next_state;
reg [7:0] r_admin_sq_head_ptr;
reg [7:0] r_io_sq1_head_ptr;
reg [7:0] r_io_sq2_head_ptr;
reg [7:0] r_io_sq3_head_ptr;
reg [7:0] r_io_sq4_head_ptr;
reg [7:0] r_io_sq5_head_ptr;
reg [7:0] r_io_sq6_head_ptr;
reg [7:0] r_io_sq7_head_ptr;
reg [7:0] r_io_sq8_head_ptr;
reg r_arb_sq_rdy;
reg [3:0] r_sq_qid;
reg [7:0] r_sq_head_ptr;
reg [C_PCIE_ADDR_WIDTH-1:2] r_hcmd_pcie_addr;
wire [8:0] w_sq_entry_valid;
wire w_sq_entry_valid_ok;
reg [8:0] r_sq_entry_valid;
wire [8:0] w_sq_valid_mask;
reg [8:0] r_sq_update_entry;
wire [8:0] w_sq_rst_n;
assign arb_sq_rdy = r_arb_sq_rdy;
assign sq_qid = r_sq_qid;
assign hcmd_pcie_addr = r_hcmd_pcie_addr;
assign w_sq_entry_valid[0] = (r_admin_sq_head_ptr != admin_sq_tail_ptr) & sq_valid[0];
assign w_sq_entry_valid[1] = (r_io_sq1_head_ptr != io_sq1_tail_ptr) & sq_valid[1];
assign w_sq_entry_valid[2] = (r_io_sq2_head_ptr != io_sq2_tail_ptr) & sq_valid[2];
assign w_sq_entry_valid[3] = (r_io_sq3_head_ptr != io_sq3_tail_ptr) & sq_valid[3];
assign w_sq_entry_valid[4] = (r_io_sq4_head_ptr != io_sq4_tail_ptr) & sq_valid[4];
assign w_sq_entry_valid[5] = (r_io_sq5_head_ptr != io_sq5_tail_ptr) & sq_valid[5];
assign w_sq_entry_valid[6] = (r_io_sq6_head_ptr != io_sq6_tail_ptr) & sq_valid[6];
assign w_sq_entry_valid[7] = (r_io_sq7_head_ptr != io_sq7_tail_ptr) & sq_valid[7];
assign w_sq_entry_valid[8] = (r_io_sq8_head_ptr != io_sq8_tail_ptr) & sq_valid[8];
assign w_sq_valid_mask = {r_sq_entry_valid[7:0], r_sq_entry_valid[8]};
assign w_sq_entry_valid_ok = ((w_sq_entry_valid[8:1] & w_sq_valid_mask[8:1]) != 0) | w_sq_entry_valid[0];
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0)
cur_state <= S_ARB_HCMD;
else
cur_state <= next_state;
end
always @ (*)
begin
case(cur_state)
S_ARB_HCMD: begin
if(w_sq_entry_valid_ok == 1)
next_state <= S_LOAD_HEAD_PTR;
else
next_state <= S_ARB_HCMD;
end
S_LOAD_HEAD_PTR: begin
next_state <= S_CALC_ADDR;
end
S_CALC_ADDR: begin
next_state <= S_GNT_HCMD;
end
S_GNT_HCMD: begin
if(sq_hcmd_ack == 1)
next_state <= S_UPDATE_HEAD_PTR;
else
next_state <= S_GNT_HCMD;
end
S_UPDATE_HEAD_PTR: begin
next_state <= S_ARB_HCMD;
end
default: begin
next_state <= S_ARB_HCMD;
end
endcase
end
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0) begin
r_sq_entry_valid <= 1;
end
else begin
case(cur_state)
S_ARB_HCMD: begin
if(w_sq_entry_valid[0] == 1)
r_sq_entry_valid <= 1;
else
r_sq_entry_valid <= w_sq_valid_mask;
end
S_LOAD_HEAD_PTR: begin
end
S_CALC_ADDR: begin
end
S_GNT_HCMD: begin
end
S_UPDATE_HEAD_PTR: begin
end
default: begin
end
endcase
end
end
always @ (posedge pcie_user_clk)
begin
case(cur_state)
S_ARB_HCMD: begin
end
S_LOAD_HEAD_PTR: begin
case(r_sq_entry_valid) // synthesis parallel_case full_case
9'b000000001: begin
r_hcmd_pcie_addr <= admin_sq_bs_addr;
r_sq_head_ptr <= r_admin_sq_head_ptr;
end
9'b000000010: begin
r_hcmd_pcie_addr <= io_sq1_bs_addr;
r_sq_head_ptr <= r_io_sq1_head_ptr;
end
9'b000000100: begin
r_hcmd_pcie_addr <= io_sq2_bs_addr;
r_sq_head_ptr <= r_io_sq2_head_ptr;
end
9'b000001000: begin
r_hcmd_pcie_addr <= io_sq3_bs_addr;
r_sq_head_ptr <= r_io_sq3_head_ptr;
end
9'b000010000: begin
r_hcmd_pcie_addr <= io_sq4_bs_addr;
r_sq_head_ptr <= r_io_sq4_head_ptr;
end
9'b000100000: begin
r_hcmd_pcie_addr <= io_sq5_bs_addr;
r_sq_head_ptr <= r_io_sq5_head_ptr;
end
9'b001000000: begin
r_hcmd_pcie_addr <= io_sq6_bs_addr;
r_sq_head_ptr <= r_io_sq6_head_ptr;
end
9'b010000000: begin
r_hcmd_pcie_addr <= io_sq7_bs_addr;
r_sq_head_ptr <= r_io_sq7_head_ptr;
end
9'b100000000: begin
r_hcmd_pcie_addr <= io_sq8_bs_addr;
r_sq_head_ptr <= r_io_sq8_head_ptr;
end
endcase
end
S_CALC_ADDR: begin
r_hcmd_pcie_addr <= r_hcmd_pcie_addr + {r_sq_head_ptr, 4'b0};
r_sq_head_ptr <= r_sq_head_ptr + 1;
end
S_GNT_HCMD: begin
end
S_UPDATE_HEAD_PTR: begin
end
default: begin
end
endcase
end
always @ (*)
begin
case(cur_state)
S_ARB_HCMD: begin
r_arb_sq_rdy <= 0;
r_sq_update_entry <= 0;
end
S_LOAD_HEAD_PTR: begin
r_arb_sq_rdy <= 0;
r_sq_update_entry <= 0;
end
S_CALC_ADDR: begin
r_arb_sq_rdy <= 0;
r_sq_update_entry <= 0;
end
S_GNT_HCMD: begin
r_arb_sq_rdy <= 1;
r_sq_update_entry <= 0;
end
S_UPDATE_HEAD_PTR: begin
r_arb_sq_rdy <= 0;
r_sq_update_entry <= r_sq_entry_valid;
end
default: begin
r_arb_sq_rdy <= 0;
r_sq_update_entry <= 0;
end
endcase
end
always @ (*)
begin
case(r_sq_entry_valid) // synthesis parallel_case full_case
9'b000000001: r_sq_qid <= 4'h0;
9'b000000010: r_sq_qid <= 4'h1;
9'b000000100: r_sq_qid <= 4'h2;
9'b000001000: r_sq_qid <= 4'h3;
9'b000010000: r_sq_qid <= 4'h4;
9'b000100000: r_sq_qid <= 4'h5;
9'b001000000: r_sq_qid <= 4'h6;
9'b010000000: r_sq_qid <= 4'h7;
9'b100000000: r_sq_qid <= 4'h8;
endcase
end
assign w_sq_rst_n[0] = pcie_user_rst_n & sq_rst_n[0];
assign w_sq_rst_n[1] = pcie_user_rst_n & sq_rst_n[1];
assign w_sq_rst_n[2] = pcie_user_rst_n & sq_rst_n[2];
assign w_sq_rst_n[3] = pcie_user_rst_n & sq_rst_n[3];
assign w_sq_rst_n[4] = pcie_user_rst_n & sq_rst_n[4];
assign w_sq_rst_n[5] = pcie_user_rst_n & sq_rst_n[5];
assign w_sq_rst_n[6] = pcie_user_rst_n & sq_rst_n[6];
assign w_sq_rst_n[7] = pcie_user_rst_n & sq_rst_n[7];
assign w_sq_rst_n[8] = pcie_user_rst_n & sq_rst_n[8];
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[0])
begin
if(w_sq_rst_n[0] == 0) begin
r_admin_sq_head_ptr <= 0;
end
else begin
if(r_sq_update_entry[0] == 1) begin
if(r_admin_sq_head_ptr == admin_sq_size) begin
r_admin_sq_head_ptr <= 0;
end
else begin
r_admin_sq_head_ptr <= r_sq_head_ptr;
end
end
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[1])
begin
if(w_sq_rst_n[1] == 0) begin
r_io_sq1_head_ptr <= 0;
end
else begin
if(r_sq_update_entry[1] == 1) begin
if(r_io_sq1_head_ptr == io_sq1_size) begin
r_io_sq1_head_ptr <= 0;
end
else begin
r_io_sq1_head_ptr <= r_sq_head_ptr;
end
end
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[2])
begin
if(w_sq_rst_n[2] == 0) begin
r_io_sq2_head_ptr <= 0;
end
else begin
if(r_sq_update_entry[2] == 1) begin
if(r_io_sq2_head_ptr == io_sq2_size) begin
r_io_sq2_head_ptr <= 0;
end
else begin
r_io_sq2_head_ptr <= r_sq_head_ptr;
end
end
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[3])
begin
if(w_sq_rst_n[3] == 0) begin
r_io_sq3_head_ptr <= 0;
end
else begin
if(r_sq_update_entry[3] == 1) begin
if(r_io_sq3_head_ptr == io_sq3_size) begin
r_io_sq3_head_ptr <= 0;
end
else begin
r_io_sq3_head_ptr <= r_sq_head_ptr;
end
end
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[4])
begin
if(w_sq_rst_n[4] == 0) begin
r_io_sq4_head_ptr <= 0;
end
else begin
if(r_sq_update_entry[4] == 1) begin
if(r_io_sq4_head_ptr == io_sq4_size) begin
r_io_sq4_head_ptr <= 0;
end
else begin
r_io_sq4_head_ptr <= r_sq_head_ptr;
end
end
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[5])
begin
if(w_sq_rst_n[5] == 0) begin
r_io_sq5_head_ptr <= 0;
end
else begin
if(r_sq_update_entry[5] == 1) begin
if(r_io_sq5_head_ptr == io_sq5_size) begin
r_io_sq5_head_ptr <= 0;
end
else begin
r_io_sq5_head_ptr <= r_sq_head_ptr;
end
end
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[6])
begin
if(w_sq_rst_n[6] == 0) begin
r_io_sq6_head_ptr <= 0;
end
else begin
if(r_sq_update_entry[6] == 1) begin
if(r_io_sq6_head_ptr == io_sq6_size) begin
r_io_sq6_head_ptr <= 0;
end
else begin
r_io_sq6_head_ptr <= r_sq_head_ptr;
end
end
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[7])
begin
if(w_sq_rst_n[7] == 0) begin
r_io_sq7_head_ptr <= 0;
end
else begin
if(r_sq_update_entry[7] == 1) begin
if(r_io_sq7_head_ptr == io_sq7_size) begin
r_io_sq7_head_ptr <= 0;
end
else begin
r_io_sq7_head_ptr <= r_sq_head_ptr;
end
end
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[8])
begin
if(w_sq_rst_n[8] == 0) begin
r_io_sq8_head_ptr <= 0;
end
else begin
if(r_sq_update_entry[8] == 1) begin
if(r_io_sq8_head_ptr == io_sq8_size) begin
r_io_sq8_head_ptr <= 0;
end
else begin
r_io_sq8_head_ptr <= r_sq_head_ptr;
end
end
end
end
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized COMPARATOR with generic_baseblocks_v2_1_carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_comparator_mask #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] B,
input wire [C_DATA_WIDTH-1:0] M,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar lut_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 2;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_FIX_DATA_WIDTH-1:0] m_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign m_local = {M, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = B;
assign m_local = M;
end
// Instantiate one generic_baseblocks_v2_1_carry and per level.
for (lut_cnt = 0; lut_cnt < C_NUM_LUT ; lut_cnt = lut_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[lut_cnt] = ( ( a_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ==
( b_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) );
// Instantiate each LUT level.
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[lut_cnt+1]),
.CIN (carry_local[lut_cnt]),
.S (sel[lut_cnt])
);
end // end for lut_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule
|
// (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
////////////////////////////////////////////////////////////
//
// axis to vector
// A generic module to unmerge all axis 'data' signals from payload.
// This is strictly wires, so no clk, reset, aclken, valid/ready are required.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// axis_infrastructure_v1_1_util_vector2axis
//
//--------------------------------------------------------------------------
`ifndef AXIS_INFRASTRUCTURE_V1_0_UTIL_VECTOR2AXIS_V
`define AXIS_INFRASTRUCTURE_V1_0_UTIL_VECTOR2AXIS_V
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axis_infrastructure_v1_1_util_vector2axis #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter integer C_TDATA_WIDTH = 32,
parameter integer C_TID_WIDTH = 1,
parameter integer C_TDEST_WIDTH = 1,
parameter integer C_TUSER_WIDTH = 1,
parameter integer C_TPAYLOAD_WIDTH = 44,
parameter [31:0] C_SIGNAL_SET = 32'hFF
// C_AXIS_SIGNAL_SET: each bit if enabled specifies which axis optional signals are present
// [0] => TREADY present
// [1] => TDATA present
// [2] => TSTRB present, TDATA must be present
// [3] => TKEEP present, TDATA must be present
// [4] => TLAST present
// [5] => TID present
// [6] => TDEST present
// [7] => TUSER present
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// outputs
input wire [C_TPAYLOAD_WIDTH-1:0] TPAYLOAD,
// inputs
output wire [C_TDATA_WIDTH-1:0] TDATA,
output wire [C_TDATA_WIDTH/8-1:0] TSTRB,
output wire [C_TDATA_WIDTH/8-1:0] TKEEP,
output wire TLAST,
output wire [C_TID_WIDTH-1:0] TID,
output wire [C_TDEST_WIDTH-1:0] TDEST,
output wire [C_TUSER_WIDTH-1:0] TUSER
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
`include "axis_infrastructure_v1_1_axis_infrastructure.vh"
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
localparam P_TDATA_INDX = f_get_tdata_indx(C_TDATA_WIDTH, C_TID_WIDTH,
C_TDEST_WIDTH, C_TUSER_WIDTH,
C_SIGNAL_SET);
localparam P_TSTRB_INDX = f_get_tstrb_indx(C_TDATA_WIDTH, C_TID_WIDTH,
C_TDEST_WIDTH, C_TUSER_WIDTH,
C_SIGNAL_SET);
localparam P_TKEEP_INDX = f_get_tkeep_indx(C_TDATA_WIDTH, C_TID_WIDTH,
C_TDEST_WIDTH, C_TUSER_WIDTH,
C_SIGNAL_SET);
localparam P_TLAST_INDX = f_get_tlast_indx(C_TDATA_WIDTH, C_TID_WIDTH,
C_TDEST_WIDTH, C_TUSER_WIDTH,
C_SIGNAL_SET);
localparam P_TID_INDX = f_get_tid_indx (C_TDATA_WIDTH, C_TID_WIDTH,
C_TDEST_WIDTH, C_TUSER_WIDTH,
C_SIGNAL_SET);
localparam P_TDEST_INDX = f_get_tdest_indx(C_TDATA_WIDTH, C_TID_WIDTH,
C_TDEST_WIDTH, C_TUSER_WIDTH,
C_SIGNAL_SET);
localparam P_TUSER_INDX = f_get_tuser_indx(C_TDATA_WIDTH, C_TID_WIDTH,
C_TDEST_WIDTH, C_TUSER_WIDTH,
C_SIGNAL_SET);
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
generate
if (C_SIGNAL_SET[G_INDX_SS_TDATA]) begin : gen_tdata
assign TDATA = TPAYLOAD[P_TDATA_INDX+:C_TDATA_WIDTH] ;
end
else begin : no_gen_tdata
assign TDATA = {C_TDATA_WIDTH{1'b0}};
end
if (C_SIGNAL_SET[G_INDX_SS_TSTRB]) begin : gen_tstrb
assign TSTRB = TPAYLOAD[P_TSTRB_INDX+:C_TDATA_WIDTH/8];
end
else begin : no_gen_tstrb
assign TSTRB = {(C_TDATA_WIDTH/8){1'b0}};
end
if (C_SIGNAL_SET[G_INDX_SS_TKEEP]) begin : gen_tkeep
assign TKEEP = TPAYLOAD[P_TKEEP_INDX+:C_TDATA_WIDTH/8];
end
else begin : no_gen_tkeep
assign TKEEP = {(C_TDATA_WIDTH/8){1'b0}};
end
if (C_SIGNAL_SET[G_INDX_SS_TLAST]) begin : gen_tlast
assign TLAST = TPAYLOAD[P_TLAST_INDX+:1] ;
end
else begin : no_gen_tlast
assign TLAST = 1'b0;
end
if (C_SIGNAL_SET[G_INDX_SS_TID]) begin : gen_tid
assign TID = TPAYLOAD[P_TID_INDX+:C_TID_WIDTH] ;
end
else begin : no_gen_tid
assign TID = {C_TID_WIDTH{1'b0}};
end
if (C_SIGNAL_SET[G_INDX_SS_TDEST]) begin : gen_tdest
assign TDEST = TPAYLOAD[P_TDEST_INDX+:C_TDEST_WIDTH] ;
end
else begin : no_gen_tdest
assign TDEST = {C_TDEST_WIDTH{1'b0}};
end
if (C_SIGNAL_SET[G_INDX_SS_TUSER]) begin : gen_tuser
assign TUSER = TPAYLOAD[P_TUSER_INDX+:C_TUSER_WIDTH] ;
end
else begin : no_gen_tuser
assign TUSER = {C_TUSER_WIDTH{1'b0}};
end
endgenerate
endmodule
`default_nettype wire
`endif
|
//
// Copyright (c) 2003 Steve Williams
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
module main;
parameter offset = 7.0;
time result;
initial begin
#9 result = $time + offset;
$display("result = %d", result);
if (result !== 64'd16) begin
$display("FAILED -- incorrect result");
$finish;
end
$display("PASSED");
$finish;
end
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_core_pcie_7x.v
// Version : 1.10
//
// Description: Solution wrapper for Virtex7 Hard Block for PCI Express
//
//
//
//--------------------------------------------------------------------------------
`ifndef PCIE_2LM
`timescale 1ps/1ps
module pcie_core_pcie_7x # (
// PCIE_2_1 params
parameter [11:0] AER_BASE_PTR = 12'h140,
parameter AER_CAP_ECRC_CHECK_CAPABLE = "FALSE",
parameter AER_CAP_ECRC_GEN_CAPABLE = "FALSE",
parameter [15:0] AER_CAP_ID = 16'h0001,
parameter AER_CAP_MULTIHEADER = "FALSE",
parameter [11:0] AER_CAP_NEXTPTR = 12'h178,
parameter AER_CAP_ON = "FALSE",
parameter [23:0] AER_CAP_OPTIONAL_ERR_SUPPORT = 24'h000000,
parameter AER_CAP_PERMIT_ROOTERR_UPDATE = "TRUE",
parameter [3:0] AER_CAP_VERSION = 4'h1,
parameter ALLOW_X8_GEN2 = "FALSE",
parameter [31:0] BAR0 = 32'hFFFFFF00,
parameter [31:0] BAR1 = 32'hFFFF0000,
parameter [31:0] BAR2 = 32'hFFFF000C,
parameter [31:0] BAR3 = 32'hFFFFFFFF,
parameter [31:0] BAR4 = 32'h00000000,
parameter [31:0] BAR5 = 32'h00000000,
parameter [7:0] CAPABILITIES_PTR = 8'h40,
parameter [31:0] CARDBUS_CIS_POINTER = 32'h00000000,
parameter CFG_ECRC_ERR_CPLSTAT = 0,
parameter [23:0] CLASS_CODE = 24'h000000,
parameter CMD_INTX_IMPLEMENTED = "TRUE",
parameter CPL_TIMEOUT_DISABLE_SUPPORTED = "FALSE",
parameter [3:0] CPL_TIMEOUT_RANGES_SUPPORTED = 4'h0,
parameter [6:0] CRM_MODULE_RSTS = 7'h00,
parameter C_DATA_WIDTH = 64,
parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1,
parameter KEEP_WIDTH = C_DATA_WIDTH / 8,
parameter DEV_CAP2_ARI_FORWARDING_SUPPORTED = "FALSE",
parameter DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED = "FALSE",
parameter DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED = "FALSE",
parameter DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED = "FALSE",
parameter DEV_CAP2_CAS128_COMPLETER_SUPPORTED = "FALSE",
parameter DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED = "FALSE",
parameter DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED = "FALSE",
parameter DEV_CAP2_LTR_MECHANISM_SUPPORTED = "FALSE",
parameter [1:0] DEV_CAP2_MAX_ENDEND_TLP_PREFIXES = 2'h0,
parameter DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING = "FALSE",
parameter [1:0] DEV_CAP2_TPH_COMPLETER_SUPPORTED = 2'h0,
parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE = "TRUE",
parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE = "TRUE",
parameter integer DEV_CAP_ENDPOINT_L0S_LATENCY = 0,
parameter integer DEV_CAP_ENDPOINT_L1_LATENCY = 0,
parameter DEV_CAP_EXT_TAG_SUPPORTED = "TRUE",
parameter DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "FALSE",
parameter integer DEV_CAP_MAX_PAYLOAD_SUPPORTED = 2,
parameter integer DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT = 0,
parameter DEV_CAP_ROLE_BASED_ERROR = "TRUE",
parameter integer DEV_CAP_RSVD_14_12 = 0,
parameter integer DEV_CAP_RSVD_17_16 = 0,
parameter integer DEV_CAP_RSVD_31_29 = 0,
parameter DEV_CONTROL_AUX_POWER_SUPPORTED = "FALSE",
parameter DEV_CONTROL_EXT_TAG_DEFAULT = "FALSE",
parameter DISABLE_ASPM_L1_TIMER = "FALSE",
parameter DISABLE_BAR_FILTERING = "FALSE",
parameter DISABLE_ERR_MSG = "FALSE",
parameter DISABLE_ID_CHECK = "FALSE",
parameter DISABLE_LANE_REVERSAL = "FALSE",
parameter DISABLE_LOCKED_FILTER = "FALSE",
parameter DISABLE_PPM_FILTER = "FALSE",
parameter DISABLE_RX_POISONED_RESP = "FALSE",
parameter DISABLE_RX_TC_FILTER = "FALSE",
parameter DISABLE_SCRAMBLING = "FALSE",
parameter [7:0] DNSTREAM_LINK_NUM = 8'h00,
parameter [11:0] DSN_BASE_PTR = 12'h100,
parameter [15:0] DSN_CAP_ID = 16'h0003,
parameter [11:0] DSN_CAP_NEXTPTR = 12'h10C,
parameter DSN_CAP_ON = "TRUE",
parameter [3:0] DSN_CAP_VERSION = 4'h1,
parameter [10:0] ENABLE_MSG_ROUTE = 11'h000,
parameter ENABLE_RX_TD_ECRC_TRIM = "FALSE",
parameter ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED = "FALSE",
parameter ENTER_RVRY_EI_L0 = "TRUE",
parameter EXIT_LOOPBACK_ON_EI = "TRUE",
parameter [31:0] EXPANSION_ROM = 32'hFFFFF001,
parameter [5:0] EXT_CFG_CAP_PTR = 6'h3F,
parameter [9:0] EXT_CFG_XP_CAP_PTR = 10'h3FF,
parameter [7:0] HEADER_TYPE = 8'h00,
parameter [4:0] INFER_EI = 5'h00,
parameter [7:0] INTERRUPT_PIN = 8'h01,
parameter INTERRUPT_STAT_AUTO = "TRUE",
parameter IS_SWITCH = "FALSE",
parameter [9:0] LAST_CONFIG_DWORD = 10'h3FF,
parameter LINK_CAP_ASPM_OPTIONALITY = "TRUE",
parameter integer LINK_CAP_ASPM_SUPPORT = 1,
parameter LINK_CAP_CLOCK_POWER_MANAGEMENT = "FALSE",
parameter LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP = "FALSE",
parameter integer LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7,
parameter integer LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7,
parameter integer LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7,
parameter integer LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7,
parameter integer LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7,
parameter integer LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7,
parameter integer LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7,
parameter integer LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7,
parameter LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP = "FALSE",
parameter [3:0] LINK_CAP_MAX_LINK_SPEED = 4'h1,
parameter [5:0] LINK_CAP_MAX_LINK_WIDTH = 6'h08,
parameter integer LINK_CAP_RSVD_23 = 0,
parameter LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE = "FALSE",
parameter integer LINK_CONTROL_RCB = 0,
parameter LINK_CTRL2_DEEMPHASIS = "FALSE",
parameter LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE = "FALSE",
parameter [3:0] LINK_CTRL2_TARGET_LINK_SPEED = 4'h2,
parameter LINK_STATUS_SLOT_CLOCK_CONFIG = "TRUE",
parameter [14:0] LL_ACK_TIMEOUT = 15'h0000,
parameter LL_ACK_TIMEOUT_EN = "FALSE",
parameter integer LL_ACK_TIMEOUT_FUNC = 0,
parameter [14:0] LL_REPLAY_TIMEOUT = 15'h0000,
parameter LL_REPLAY_TIMEOUT_EN = "FALSE",
parameter integer LL_REPLAY_TIMEOUT_FUNC = 0,
parameter [5:0] LTSSM_MAX_LINK_WIDTH = 6'h01,
parameter MPS_FORCE = "FALSE",
parameter [7:0] MSIX_BASE_PTR = 8'h9C,
parameter [7:0] MSIX_CAP_ID = 8'h11,
parameter [7:0] MSIX_CAP_NEXTPTR = 8'h00,
parameter MSIX_CAP_ON = "FALSE",
parameter integer MSIX_CAP_PBA_BIR = 0,
parameter [28:0] MSIX_CAP_PBA_OFFSET = 29'h00000050,
parameter integer MSIX_CAP_TABLE_BIR = 0,
parameter [28:0] MSIX_CAP_TABLE_OFFSET = 29'h00000040,
parameter [10:0] MSIX_CAP_TABLE_SIZE = 11'h000,
parameter [7:0] MSI_BASE_PTR = 8'h48,
parameter MSI_CAP_64_BIT_ADDR_CAPABLE = "TRUE",
parameter [7:0] MSI_CAP_ID = 8'h05,
parameter integer MSI_CAP_MULTIMSGCAP = 0,
parameter integer MSI_CAP_MULTIMSG_EXTENSION = 0,
parameter [7:0] MSI_CAP_NEXTPTR = 8'h60,
parameter MSI_CAP_ON = "FALSE",
parameter MSI_CAP_PER_VECTOR_MASKING_CAPABLE = "TRUE",
parameter integer N_FTS_COMCLK_GEN1 = 255,
parameter integer N_FTS_COMCLK_GEN2 = 255,
parameter integer N_FTS_GEN1 = 255,
parameter integer N_FTS_GEN2 = 255,
parameter [7:0] PCIE_BASE_PTR = 8'h60,
parameter [7:0] PCIE_CAP_CAPABILITY_ID = 8'h10,
parameter [3:0] PCIE_CAP_CAPABILITY_VERSION = 4'h2,
parameter [3:0] PCIE_CAP_DEVICE_PORT_TYPE = 4'h0,
parameter [7:0] PCIE_CAP_NEXTPTR = 8'h9C,
parameter PCIE_CAP_ON = "TRUE",
parameter integer PCIE_CAP_RSVD_15_14 = 0,
parameter PCIE_CAP_SLOT_IMPLEMENTED = "FALSE",
parameter integer PCIE_REVISION = 2,
parameter integer PL_AUTO_CONFIG = 0,
parameter PL_FAST_TRAIN = "FALSE",
parameter [14:0] PM_ASPML0S_TIMEOUT = 15'h0000,
parameter PM_ASPML0S_TIMEOUT_EN = "FALSE",
parameter integer PM_ASPML0S_TIMEOUT_FUNC = 0,
parameter PM_ASPM_FASTEXIT = "FALSE",
parameter [7:0] PM_BASE_PTR = 8'h40,
parameter integer PM_CAP_AUXCURRENT = 0,
parameter PM_CAP_D1SUPPORT = "TRUE",
parameter PM_CAP_D2SUPPORT = "TRUE",
parameter PM_CAP_DSI = "FALSE",
parameter [7:0] PM_CAP_ID = 8'h01,
parameter [7:0] PM_CAP_NEXTPTR = 8'h48,
parameter PM_CAP_ON = "TRUE",
parameter [4:0] PM_CAP_PMESUPPORT = 5'h0F,
parameter PM_CAP_PME_CLOCK = "FALSE",
parameter integer PM_CAP_RSVD_04 = 0,
parameter integer PM_CAP_VERSION = 3,
parameter PM_CSR_B2B3 = "FALSE",
parameter PM_CSR_BPCCEN = "FALSE",
parameter PM_CSR_NOSOFTRST = "TRUE",
parameter [7:0] PM_DATA0 = 8'h01,
parameter [7:0] PM_DATA1 = 8'h01,
parameter [7:0] PM_DATA2 = 8'h01,
parameter [7:0] PM_DATA3 = 8'h01,
parameter [7:0] PM_DATA4 = 8'h01,
parameter [7:0] PM_DATA5 = 8'h01,
parameter [7:0] PM_DATA6 = 8'h01,
parameter [7:0] PM_DATA7 = 8'h01,
parameter [1:0] PM_DATA_SCALE0 = 2'h1,
parameter [1:0] PM_DATA_SCALE1 = 2'h1,
parameter [1:0] PM_DATA_SCALE2 = 2'h1,
parameter [1:0] PM_DATA_SCALE3 = 2'h1,
parameter [1:0] PM_DATA_SCALE4 = 2'h1,
parameter [1:0] PM_DATA_SCALE5 = 2'h1,
parameter [1:0] PM_DATA_SCALE6 = 2'h1,
parameter [1:0] PM_DATA_SCALE7 = 2'h1,
parameter PM_MF = "FALSE",
parameter [11:0] RBAR_BASE_PTR = 12'h178,
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR0 = 5'h00,
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR1 = 5'h00,
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR2 = 5'h00,
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR3 = 5'h00,
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR4 = 5'h00,
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR5 = 5'h00,
parameter [15:0] RBAR_CAP_ID = 16'h0015,
parameter [2:0] RBAR_CAP_INDEX0 = 3'h0,
parameter [2:0] RBAR_CAP_INDEX1 = 3'h0,
parameter [2:0] RBAR_CAP_INDEX2 = 3'h0,
parameter [2:0] RBAR_CAP_INDEX3 = 3'h0,
parameter [2:0] RBAR_CAP_INDEX4 = 3'h0,
parameter [2:0] RBAR_CAP_INDEX5 = 3'h0,
parameter [11:0] RBAR_CAP_NEXTPTR = 12'h000,
parameter RBAR_CAP_ON = "FALSE",
parameter [31:0] RBAR_CAP_SUP0 = 32'h00000000,
parameter [31:0] RBAR_CAP_SUP1 = 32'h00000000,
parameter [31:0] RBAR_CAP_SUP2 = 32'h00000000,
parameter [31:0] RBAR_CAP_SUP3 = 32'h00000000,
parameter [31:0] RBAR_CAP_SUP4 = 32'h00000000,
parameter [31:0] RBAR_CAP_SUP5 = 32'h00000000,
parameter [3:0] RBAR_CAP_VERSION = 4'h1,
parameter [2:0] RBAR_NUM = 3'h1,
parameter integer RECRC_CHK = 0,
parameter RECRC_CHK_TRIM = "FALSE",
parameter ROOT_CAP_CRS_SW_VISIBILITY = "FALSE",
parameter [1:0] RP_AUTO_SPD = 2'h1,
parameter [4:0] RP_AUTO_SPD_LOOPCNT = 5'h1f,
parameter SELECT_DLL_IF = "FALSE",
parameter SIM_VERSION = "1.0",
parameter SLOT_CAP_ATT_BUTTON_PRESENT = "FALSE",
parameter SLOT_CAP_ATT_INDICATOR_PRESENT = "FALSE",
parameter SLOT_CAP_ELEC_INTERLOCK_PRESENT = "FALSE",
parameter SLOT_CAP_HOTPLUG_CAPABLE = "FALSE",
parameter SLOT_CAP_HOTPLUG_SURPRISE = "FALSE",
parameter SLOT_CAP_MRL_SENSOR_PRESENT = "FALSE",
parameter SLOT_CAP_NO_CMD_COMPLETED_SUPPORT = "FALSE",
parameter [12:0] SLOT_CAP_PHYSICAL_SLOT_NUM = 13'h0000,
parameter SLOT_CAP_POWER_CONTROLLER_PRESENT = "FALSE",
parameter SLOT_CAP_POWER_INDICATOR_PRESENT = "FALSE",
parameter integer SLOT_CAP_SLOT_POWER_LIMIT_SCALE = 0,
parameter [7:0] SLOT_CAP_SLOT_POWER_LIMIT_VALUE = 8'h00,
parameter integer SPARE_BIT0 = 0,
parameter integer SPARE_BIT1 = 0,
parameter integer SPARE_BIT2 = 0,
parameter integer SPARE_BIT3 = 0,
parameter integer SPARE_BIT4 = 0,
parameter integer SPARE_BIT5 = 0,
parameter integer SPARE_BIT6 = 0,
parameter integer SPARE_BIT7 = 0,
parameter integer SPARE_BIT8 = 0,
parameter [7:0] SPARE_BYTE0 = 8'h00,
parameter [7:0] SPARE_BYTE1 = 8'h00,
parameter [7:0] SPARE_BYTE2 = 8'h00,
parameter [7:0] SPARE_BYTE3 = 8'h00,
parameter [31:0] SPARE_WORD0 = 32'h00000000,
parameter [31:0] SPARE_WORD1 = 32'h00000000,
parameter [31:0] SPARE_WORD2 = 32'h00000000,
parameter [31:0] SPARE_WORD3 = 32'h00000000,
parameter SSL_MESSAGE_AUTO = "FALSE",
parameter TECRC_EP_INV = "FALSE",
parameter TL_RBYPASS = "FALSE",
parameter integer TL_RX_RAM_RADDR_LATENCY = 0,
parameter integer TL_RX_RAM_RDATA_LATENCY = 2,
parameter integer TL_RX_RAM_WRITE_LATENCY = 0,
parameter TL_TFC_DISABLE = "FALSE",
parameter TL_TX_CHECKS_DISABLE = "FALSE",
parameter integer TL_TX_RAM_RADDR_LATENCY = 0,
parameter integer TL_TX_RAM_RDATA_LATENCY = 2,
parameter integer TL_TX_RAM_WRITE_LATENCY = 0,
parameter TRN_DW = "FALSE",
parameter TRN_NP_FC = "FALSE",
parameter UPCONFIG_CAPABLE = "TRUE",
parameter UPSTREAM_FACING = "TRUE",
parameter UR_ATOMIC = "TRUE",
parameter UR_CFG1 = "TRUE",
parameter UR_INV_REQ = "TRUE",
parameter UR_PRS_RESPONSE = "TRUE",
parameter USER_CLK2_DIV2 = "FALSE",
parameter integer USER_CLK_FREQ = 3,
parameter USE_RID_PINS = "FALSE",
parameter VC0_CPL_INFINITE = "TRUE",
parameter [12:0] VC0_RX_RAM_LIMIT = 13'h03FF,
parameter integer VC0_TOTAL_CREDITS_CD = 127,
parameter integer VC0_TOTAL_CREDITS_CH = 31,
parameter integer VC0_TOTAL_CREDITS_NPD = 24,
parameter integer VC0_TOTAL_CREDITS_NPH = 12,
parameter integer VC0_TOTAL_CREDITS_PD = 288,
parameter integer VC0_TOTAL_CREDITS_PH = 32,
parameter integer VC0_TX_LASTPACKET = 31,
parameter [11:0] VC_BASE_PTR = 12'h10C,
parameter [15:0] VC_CAP_ID = 16'h0002,
parameter [11:0] VC_CAP_NEXTPTR = 12'h000,
parameter VC_CAP_ON = "FALSE",
parameter VC_CAP_REJECT_SNOOP_TRANSACTIONS = "FALSE",
parameter [3:0] VC_CAP_VERSION = 4'h1,
parameter [11:0] VSEC_BASE_PTR = 12'h128,
parameter [15:0] VSEC_CAP_HDR_ID = 16'h1234,
parameter [11:0] VSEC_CAP_HDR_LENGTH = 12'h018,
parameter [3:0] VSEC_CAP_HDR_REVISION = 4'h1,
parameter [15:0] VSEC_CAP_ID = 16'h000B,
parameter VSEC_CAP_IS_LINK_VISIBLE = "TRUE",
parameter [11:0] VSEC_CAP_NEXTPTR = 12'h140,
parameter VSEC_CAP_ON = "FALSE",
parameter [3:0] VSEC_CAP_VERSION = 4'h1
)
(
input wire [C_DATA_WIDTH-1:0] trn_td,
input wire [REM_WIDTH-1:0] trn_trem,
input wire trn_tsof,
input wire trn_teof,
input wire trn_tsrc_rdy,
input wire trn_tsrc_dsc,
input wire trn_terrfwd,
input wire trn_tecrc_gen,
input wire trn_tstr,
input wire trn_tcfg_gnt,
input wire trn_rdst_rdy,
input wire trn_rnp_req,
input wire trn_rfcp_ret,
input wire trn_rnp_ok,
input wire [2:0] trn_fc_sel,
input wire [31:0] trn_tdllp_data,
input wire trn_tdllp_src_rdy,
input wire ll2_tlp_rcv,
input wire ll2_send_enter_l1,
input wire ll2_send_enter_l23,
input wire ll2_send_as_req_l1,
input wire ll2_send_pm_ack,
input wire [4:0] pl2_directed_lstate,
input wire ll2_suspend_now,
input wire tl2_ppm_suspend_req,
input wire tl2_aspm_suspend_credit_check,
input wire [1:0] pl_directed_link_change,
input wire [1:0] pl_directed_link_width,
input wire pl_directed_link_speed,
input wire pl_directed_link_auton,
input wire pl_upstream_prefer_deemph,
input wire pl_downstream_deemph_source,
input wire pl_directed_ltssm_new_vld,
input wire [5:0] pl_directed_ltssm_new,
input wire pl_directed_ltssm_stall,
input wire [1:0] pipe_rx0_char_is_k,
input wire [1:0] pipe_rx1_char_is_k,
input wire [1:0] pipe_rx2_char_is_k,
input wire [1:0] pipe_rx3_char_is_k,
input wire [1:0] pipe_rx4_char_is_k,
input wire [1:0] pipe_rx5_char_is_k,
input wire [1:0] pipe_rx6_char_is_k,
input wire [1:0] pipe_rx7_char_is_k,
input wire pipe_rx0_valid,
input wire pipe_rx1_valid,
input wire pipe_rx2_valid,
input wire pipe_rx3_valid,
input wire pipe_rx4_valid,
input wire pipe_rx5_valid,
input wire pipe_rx6_valid,
input wire pipe_rx7_valid,
input wire [15:0] pipe_rx0_data,
input wire [15:0] pipe_rx1_data,
input wire [15:0] pipe_rx2_data,
input wire [15:0] pipe_rx3_data,
input wire [15:0] pipe_rx4_data,
input wire [15:0] pipe_rx5_data,
input wire [15:0] pipe_rx6_data,
input wire [15:0] pipe_rx7_data,
input wire pipe_rx0_chanisaligned,
input wire pipe_rx1_chanisaligned,
input wire pipe_rx2_chanisaligned,
input wire pipe_rx3_chanisaligned,
input wire pipe_rx4_chanisaligned,
input wire pipe_rx5_chanisaligned,
input wire pipe_rx6_chanisaligned,
input wire pipe_rx7_chanisaligned,
input wire [2:0] pipe_rx0_status,
input wire [2:0] pipe_rx1_status,
input wire [2:0] pipe_rx2_status,
input wire [2:0] pipe_rx3_status,
input wire [2:0] pipe_rx4_status,
input wire [2:0] pipe_rx5_status,
input wire [2:0] pipe_rx6_status,
input wire [2:0] pipe_rx7_status,
input wire pipe_rx0_phy_status,
input wire pipe_rx1_phy_status,
input wire pipe_rx2_phy_status,
input wire pipe_rx3_phy_status,
input wire pipe_rx4_phy_status,
input wire pipe_rx5_phy_status,
input wire pipe_rx6_phy_status,
input wire pipe_rx7_phy_status,
input wire pipe_rx0_elec_idle,
input wire pipe_rx1_elec_idle,
input wire pipe_rx2_elec_idle,
input wire pipe_rx3_elec_idle,
input wire pipe_rx4_elec_idle,
input wire pipe_rx5_elec_idle,
input wire pipe_rx6_elec_idle,
input wire pipe_rx7_elec_idle,
input wire pipe_clk,
input wire user_clk,
input wire user_clk2,
input wire user_clk_prebuf,
input wire user_clk_prebuf_en,
`ifdef B_TESTMODE
input wire scanmode_n,
input wire scanenable_n,
input wire edt_clk,
input wire edt_bypass,
input wire edt_update,
input wire edt_configuration,
input wire edt_single_bypass_chain,
input wire edt_channels_in1,
input wire edt_channels_in2,
input wire edt_channels_in3,
input wire edt_channels_in4,
input wire edt_channels_in5,
input wire edt_channels_in6,
input wire edt_channels_in7,
input wire edt_channels_in8,
input wire pmv_enable_n,
input wire [2:0] pmv_select,
input wire [1:0] pmv_divide,
`endif
input wire sys_rst_n,
input wire cm_rst_n,
input wire cm_sticky_rst_n,
input wire func_lvl_rst_n,
input wire tl_rst_n,
input wire dl_rst_n,
input wire pl_rst_n,
input wire pl_transmit_hot_rst,
// input wire cfg_reset,
// input wire gwe,
// input wire grestore,
// input wire ghigh,
input wire [31:0] cfg_mgmt_di,
input wire [3:0] cfg_mgmt_byte_en_n,
input wire [9:0] cfg_mgmt_dwaddr,
input wire cfg_mgmt_wr_rw1c_as_rw_n,
input wire cfg_mgmt_wr_readonly_n,
input wire cfg_mgmt_wr_en_n,
input wire cfg_mgmt_rd_en_n,
input wire cfg_err_malformed_n,
input wire cfg_err_cor_n,
input wire cfg_err_ur_n,
input wire cfg_err_ecrc_n,
input wire cfg_err_cpl_timeout_n,
input wire cfg_err_cpl_abort_n,
input wire cfg_err_cpl_unexpect_n,
input wire cfg_err_poisoned_n,
input wire cfg_err_acs_n,
input wire cfg_err_atomic_egress_blocked_n,
input wire cfg_err_mc_blocked_n,
input wire cfg_err_internal_uncor_n,
input wire cfg_err_internal_cor_n,
input wire cfg_err_posted_n,
input wire cfg_err_locked_n,
input wire cfg_err_norecovery_n,
input wire [127:0] cfg_err_aer_headerlog,
input wire [47:0] cfg_err_tlp_cpl_header,
input wire cfg_interrupt_n,
input wire [7:0] cfg_interrupt_di,
input wire cfg_interrupt_assert_n,
input wire cfg_interrupt_stat_n,
input wire [7:0] cfg_ds_bus_number,
input wire [4:0] cfg_ds_device_number,
input wire [2:0] cfg_ds_function_number,
input wire [7:0] cfg_port_number,
input wire cfg_pm_halt_aspm_l0s_n,
input wire cfg_pm_halt_aspm_l1_n,
input wire cfg_pm_force_state_en_n,
input wire [1:0] cfg_pm_force_state,
input wire cfg_pm_wake_n,
input wire cfg_pm_turnoff_ok_n,
input wire cfg_pm_send_pme_to_n,
input wire [4:0] cfg_pciecap_interrupt_msgnum,
input wire cfg_trn_pending_n,
input wire [2:0] cfg_force_mps,
input wire cfg_force_common_clock_off,
input wire cfg_force_extended_sync_on,
input wire [63:0] cfg_dsn,
input wire [4:0] cfg_aer_interrupt_msgnum,
input wire [15:0] cfg_dev_id,
input wire [15:0] cfg_vend_id,
input wire [7:0] cfg_rev_id,
input wire [15:0] cfg_subsys_id,
input wire [15:0] cfg_subsys_vend_id,
input wire drp_clk,
input wire drp_en,
input wire drp_we,
input wire [8:0] drp_addr,
input wire [15:0] drp_di,
input wire [1:0] dbg_mode,
input wire dbg_sub_mode,
input wire [2:0] pl_dbg_mode,
output wire trn_clk,
output wire trn_tdst_rdy,
output wire trn_terr_drop,
output wire [5:0] trn_tbuf_av,
output wire trn_tcfg_req,
output wire [C_DATA_WIDTH-1:0] trn_rd,
output wire [REM_WIDTH-1:0] trn_rrem,
output wire trn_rsof,
output wire trn_reof,
output wire trn_rsrc_rdy,
output wire trn_rsrc_dsc,
output wire trn_recrc_err,
output wire trn_rerrfwd,
output wire [7:0] trn_rbar_hit,
output wire trn_lnk_up,
output wire [7:0] trn_fc_ph,
output wire [11:0] trn_fc_pd,
output wire [7:0] trn_fc_nph,
output wire [11:0] trn_fc_npd,
output wire [7:0] trn_fc_cplh,
output wire [11:0] trn_fc_cpld,
output wire trn_tdllp_dst_rdy,
output wire [63:0] trn_rdllp_data,
output wire [1:0] trn_rdllp_src_rdy,
output wire ll2_tfc_init1_seq,
output wire ll2_tfc_init2_seq,
output wire pl2_suspend_ok,
output wire pl2_recovery,
output wire pl2_rx_elec_idle,
output wire [1:0] pl2_rx_pm_state,
output wire pl2_l0_req,
output wire ll2_suspend_ok,
output wire ll2_tx_idle,
output wire [4:0] ll2_link_status,
output wire tl2_ppm_suspend_ok,
output wire tl2_aspm_suspend_req,
output wire tl2_aspm_suspend_credit_check_ok,
output wire pl2_link_up,
output wire pl2_receiver_err,
output wire ll2_receiver_err,
output wire ll2_protocol_err,
output wire ll2_bad_tlp_err,
output wire ll2_bad_dllp_err,
output wire ll2_replay_ro_err,
output wire ll2_replay_to_err,
output wire [63:0] tl2_err_hdr,
output wire tl2_err_malformed,
output wire tl2_err_rxoverflow,
output wire tl2_err_fcpe,
output wire pl_sel_lnk_rate,
output wire [1:0] pl_sel_lnk_width,
output wire [5:0] pl_ltssm_state,
output wire [1:0] pl_lane_reversal_mode,
output wire pl_phy_lnk_up_n,
output wire [2:0] pl_tx_pm_state,
output wire [1:0] pl_rx_pm_state,
output wire pl_link_upcfg_cap,
output wire pl_link_gen2_cap,
output wire pl_link_partner_gen2_supported,
output wire [2:0] pl_initial_link_width,
output wire pl_directed_change_done,
output wire pipe_tx_rcvr_det,
output wire pipe_tx_reset,
output wire pipe_tx_rate,
output wire pipe_tx_deemph,
output wire [2:0] pipe_tx_margin,
output wire pipe_rx0_polarity,
output wire pipe_rx1_polarity,
output wire pipe_rx2_polarity,
output wire pipe_rx3_polarity,
output wire pipe_rx4_polarity,
output wire pipe_rx5_polarity,
output wire pipe_rx6_polarity,
output wire pipe_rx7_polarity,
output wire pipe_tx0_compliance,
output wire pipe_tx1_compliance,
output wire pipe_tx2_compliance,
output wire pipe_tx3_compliance,
output wire pipe_tx4_compliance,
output wire pipe_tx5_compliance,
output wire pipe_tx6_compliance,
output wire pipe_tx7_compliance,
output wire [1:0] pipe_tx0_char_is_k,
output wire [1:0] pipe_tx1_char_is_k,
output wire [1:0] pipe_tx2_char_is_k,
output wire [1:0] pipe_tx3_char_is_k,
output wire [1:0] pipe_tx4_char_is_k,
output wire [1:0] pipe_tx5_char_is_k,
output wire [1:0] pipe_tx6_char_is_k,
output wire [1:0] pipe_tx7_char_is_k,
output wire [15:0] pipe_tx0_data,
output wire [15:0] pipe_tx1_data,
output wire [15:0] pipe_tx2_data,
output wire [15:0] pipe_tx3_data,
output wire [15:0] pipe_tx4_data,
output wire [15:0] pipe_tx5_data,
output wire [15:0] pipe_tx6_data,
output wire [15:0] pipe_tx7_data,
output wire pipe_tx0_elec_idle,
output wire pipe_tx1_elec_idle,
output wire pipe_tx2_elec_idle,
output wire pipe_tx3_elec_idle,
output wire pipe_tx4_elec_idle,
output wire pipe_tx5_elec_idle,
output wire pipe_tx6_elec_idle,
output wire pipe_tx7_elec_idle,
output wire [1:0] pipe_tx0_powerdown,
output wire [1:0] pipe_tx1_powerdown,
output wire [1:0] pipe_tx2_powerdown,
output wire [1:0] pipe_tx3_powerdown,
output wire [1:0] pipe_tx4_powerdown,
output wire [1:0] pipe_tx5_powerdown,
output wire [1:0] pipe_tx6_powerdown,
output wire [1:0] pipe_tx7_powerdown,
`ifdef B_TESTMODE
output wire pmv_out,
`endif
output wire user_rst_n,
output wire pl_received_hot_rst,
output wire received_func_lvl_rst_n,
output wire lnk_clk_en,
output wire [31:0] cfg_mgmt_do,
output wire cfg_mgmt_rd_wr_done_n,
output wire cfg_err_aer_headerlog_set_n,
output wire cfg_err_cpl_rdy_n,
output wire cfg_interrupt_rdy_n,
output wire [2:0] cfg_interrupt_mmenable,
output wire cfg_interrupt_msienable,
output wire [7:0] cfg_interrupt_do,
output wire cfg_interrupt_msixenable,
output wire cfg_interrupt_msixfm,
output wire cfg_msg_received,
output wire [15:0] cfg_msg_data,
output wire cfg_msg_received_err_cor,
output wire cfg_msg_received_err_non_fatal,
output wire cfg_msg_received_err_fatal,
output wire cfg_msg_received_assert_int_a,
output wire cfg_msg_received_deassert_int_a,
output wire cfg_msg_received_assert_int_b,
output wire cfg_msg_received_deassert_int_b,
output wire cfg_msg_received_assert_int_c,
output wire cfg_msg_received_deassert_int_c,
output wire cfg_msg_received_assert_int_d,
output wire cfg_msg_received_deassert_int_d,
output wire cfg_msg_received_pm_pme,
output wire cfg_msg_received_pme_to_ack,
output wire cfg_msg_received_pme_to,
output wire cfg_msg_received_setslotpowerlimit,
output wire cfg_msg_received_unlock,
output wire cfg_msg_received_pm_as_nak,
output wire [2:0] cfg_pcie_link_state,
output wire cfg_pm_rcv_as_req_l1_n,
output wire cfg_pm_rcv_enter_l1_n,
output wire cfg_pm_rcv_enter_l23_n,
output wire cfg_pm_rcv_req_ack_n,
output wire [1:0] cfg_pmcsr_powerstate,
output wire cfg_pmcsr_pme_en,
output wire cfg_pmcsr_pme_status,
output wire cfg_transaction,
output wire cfg_transaction_type,
output wire [6:0] cfg_transaction_addr,
output wire cfg_command_io_enable,
output wire cfg_command_mem_enable,
output wire cfg_command_bus_master_enable,
output wire cfg_command_interrupt_disable,
output wire cfg_command_serr_en,
output wire cfg_bridge_serr_en,
output wire cfg_dev_status_corr_err_detected,
output wire cfg_dev_status_non_fatal_err_detected,
output wire cfg_dev_status_fatal_err_detected,
output wire cfg_dev_status_ur_detected,
output wire cfg_dev_control_corr_err_reporting_en,
output wire cfg_dev_control_non_fatal_reporting_en,
output wire cfg_dev_control_fatal_err_reporting_en,
output wire cfg_dev_control_ur_err_reporting_en,
output wire cfg_dev_control_enable_ro,
output wire [2:0] cfg_dev_control_max_payload,
output wire cfg_dev_control_ext_tag_en,
output wire cfg_dev_control_phantom_en,
output wire cfg_dev_control_aux_power_en,
output wire cfg_dev_control_no_snoop_en,
output wire [2:0] cfg_dev_control_max_read_req,
output wire [1:0] cfg_link_status_current_speed,
output wire [3:0] cfg_link_status_negotiated_width,
output wire cfg_link_status_link_training,
output wire cfg_link_status_dll_active,
output wire cfg_link_status_bandwidth_status,
output wire cfg_link_status_auto_bandwidth_status,
output wire [1:0] cfg_link_control_aspm_control,
output wire cfg_link_control_rcb,
output wire cfg_link_control_link_disable,
output wire cfg_link_control_retrain_link,
output wire cfg_link_control_common_clock,
output wire cfg_link_control_extended_sync,
output wire cfg_link_control_clock_pm_en,
output wire cfg_link_control_hw_auto_width_dis,
output wire cfg_link_control_bandwidth_int_en,
output wire cfg_link_control_auto_bandwidth_int_en,
output wire [3:0] cfg_dev_control2_cpl_timeout_val,
output wire cfg_dev_control2_cpl_timeout_dis,
output wire cfg_dev_control2_ari_forward_en,
output wire cfg_dev_control2_atomic_requester_en,
output wire cfg_dev_control2_atomic_egress_block,
output wire cfg_dev_control2_ido_req_en,
output wire cfg_dev_control2_ido_cpl_en,
output wire cfg_dev_control2_ltr_en,
output wire cfg_dev_control2_tlp_prefix_block,
output wire cfg_slot_control_electromech_il_ctl_pulse,
output wire cfg_root_control_syserr_corr_err_en,
output wire cfg_root_control_syserr_non_fatal_err_en,
output wire cfg_root_control_syserr_fatal_err_en,
output wire cfg_root_control_pme_int_en,
output wire cfg_aer_ecrc_check_en,
output wire cfg_aer_ecrc_gen_en,
output wire cfg_aer_rooterr_corr_err_reporting_en,
output wire cfg_aer_rooterr_non_fatal_err_reporting_en,
output wire cfg_aer_rooterr_fatal_err_reporting_en,
output wire cfg_aer_rooterr_corr_err_received,
output wire cfg_aer_rooterr_non_fatal_err_received,
output wire cfg_aer_rooterr_fatal_err_received,
output wire [6:0] cfg_vc_tcvc_map,
output wire drp_rdy,
output wire [15:0] drp_do,
output wire [63:0] dbg_vec_a,
output wire [63:0] dbg_vec_b,
output wire [11:0] dbg_vec_c,
output wire dbg_sclr_a,
output wire dbg_sclr_b,
output wire dbg_sclr_c,
output wire dbg_sclr_d,
output wire dbg_sclr_e,
output wire dbg_sclr_f,
output wire dbg_sclr_g,
output wire dbg_sclr_h,
output wire dbg_sclr_i,
output wire dbg_sclr_j,
output wire dbg_sclr_k,
output wire [11:0] pl_dbg_vec
// output wire [18:0] xil_unconn_out
);
localparam TCQ = 1;
wire [3:0] trn_tdst_rdy_bus;
// Assignments to outputs
assign trn_clk = user_clk2;
assign trn_tdst_rdy = trn_tdst_rdy_bus[0];
//----------------------------------------------------------------------//
// BRAM //
//----------------------------------------------------------------------//
// transmit bram interface
wire mim_tx_wen;
wire [12:0] mim_tx_waddr;
wire [68:0] mim_tx_wdata;
wire mim_tx_ren;
wire mim_tx_rce;
wire [12:0] mim_tx_raddr;
wire [68:0] mim_tx_rdata;
wire [2:0] unused_mim_tx_rdata;
// receive bram interface
wire mim_rx_wen;
wire [12:0] mim_rx_waddr;
wire [67:0] mim_rx_wdata;
wire mim_rx_ren;
wire mim_rx_rce;
wire [12:0] mim_rx_raddr;
wire [67:0] mim_rx_rdata;
wire [3:0] unused_mim_rx_rdata;
pcie_core_pcie_bram_top_7x #(
.LINK_CAP_MAX_LINK_SPEED ( LINK_CAP_MAX_LINK_SPEED ),
.LINK_CAP_MAX_LINK_WIDTH ( LINK_CAP_MAX_LINK_WIDTH ),
.DEV_CAP_MAX_PAYLOAD_SUPPORTED ( DEV_CAP_MAX_PAYLOAD_SUPPORTED ),
.VC0_TX_LASTPACKET ( VC0_TX_LASTPACKET ),
.TL_TX_RAM_RADDR_LATENCY ( TL_TX_RAM_RADDR_LATENCY ),
.TL_TX_RAM_RDATA_LATENCY ( TL_TX_RAM_RDATA_LATENCY ),
.TL_TX_RAM_WRITE_LATENCY ( TL_TX_RAM_WRITE_LATENCY ),
.VC0_RX_RAM_LIMIT ( VC0_RX_RAM_LIMIT ),
.TL_RX_RAM_RADDR_LATENCY ( TL_RX_RAM_RADDR_LATENCY ),
.TL_RX_RAM_RDATA_LATENCY ( TL_RX_RAM_RDATA_LATENCY ),
.TL_RX_RAM_WRITE_LATENCY ( TL_RX_RAM_WRITE_LATENCY )
) pcie_bram_top (
.user_clk_i ( user_clk ),
.reset_i ( 1'b0 ),
.mim_tx_waddr ( mim_tx_waddr ),
.mim_tx_wen ( mim_tx_wen ),
.mim_tx_ren ( mim_tx_ren ),
.mim_tx_rce ( 1'b1 ),
.mim_tx_wdata ( {3'b0, mim_tx_wdata} ),
.mim_tx_raddr ( mim_tx_raddr ),
.mim_tx_rdata ( {unused_mim_tx_rdata, mim_tx_rdata} ),
.mim_rx_waddr ( mim_rx_waddr ),
.mim_rx_wen ( mim_rx_wen ),
.mim_rx_ren ( mim_rx_ren ),
.mim_rx_rce ( 1'b1 ),
.mim_rx_wdata ( {4'b0, mim_rx_wdata} ),
.mim_rx_raddr ( mim_rx_raddr ),
.mim_rx_rdata ( {unused_mim_rx_rdata, mim_rx_rdata} )
);
//-------------------------------------------------------
// Virtex7 PCI Express Block Module
//-------------------------------------------------------
PCIE_2_1 #( // Verilog-2001
.AER_BASE_PTR ( AER_BASE_PTR ),
.AER_CAP_ECRC_CHECK_CAPABLE ( AER_CAP_ECRC_CHECK_CAPABLE ),
.AER_CAP_ECRC_GEN_CAPABLE ( AER_CAP_ECRC_GEN_CAPABLE ),
.AER_CAP_ID ( AER_CAP_ID ),
.AER_CAP_MULTIHEADER ( AER_CAP_MULTIHEADER ),
.AER_CAP_NEXTPTR ( AER_CAP_NEXTPTR ),
.AER_CAP_ON ( AER_CAP_ON ),
.AER_CAP_OPTIONAL_ERR_SUPPORT ( AER_CAP_OPTIONAL_ERR_SUPPORT ),
.AER_CAP_PERMIT_ROOTERR_UPDATE ( AER_CAP_PERMIT_ROOTERR_UPDATE ),
.AER_CAP_VERSION ( AER_CAP_VERSION ),
.ALLOW_X8_GEN2 ( ALLOW_X8_GEN2 ),
.BAR0 ( BAR0 ),
.BAR1 ( BAR1 ),
.BAR2 ( BAR2 ),
.BAR3 ( BAR3 ),
.BAR4 ( BAR4 ),
.BAR5 ( BAR5 ),
.CAPABILITIES_PTR ( CAPABILITIES_PTR ),
.CARDBUS_CIS_POINTER ( CARDBUS_CIS_POINTER ),
.CFG_ECRC_ERR_CPLSTAT ( CFG_ECRC_ERR_CPLSTAT ),
.CLASS_CODE ( CLASS_CODE ),
.CMD_INTX_IMPLEMENTED ( CMD_INTX_IMPLEMENTED ),
.CPL_TIMEOUT_DISABLE_SUPPORTED ( CPL_TIMEOUT_DISABLE_SUPPORTED ),
.CPL_TIMEOUT_RANGES_SUPPORTED ( CPL_TIMEOUT_RANGES_SUPPORTED ),
.CRM_MODULE_RSTS ( CRM_MODULE_RSTS ),
.DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE ( DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE ),
.DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE ( DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE ),
.DEV_CAP_ENDPOINT_L0S_LATENCY ( DEV_CAP_ENDPOINT_L0S_LATENCY ),
.DEV_CAP_ENDPOINT_L1_LATENCY ( DEV_CAP_ENDPOINT_L1_LATENCY ),
.DEV_CAP_EXT_TAG_SUPPORTED ( DEV_CAP_EXT_TAG_SUPPORTED ),
.DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE ( DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE ),
.DEV_CAP_MAX_PAYLOAD_SUPPORTED ( DEV_CAP_MAX_PAYLOAD_SUPPORTED ),
.DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT ( DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT ),
.DEV_CAP_ROLE_BASED_ERROR ( DEV_CAP_ROLE_BASED_ERROR ),
.DEV_CAP_RSVD_14_12 ( DEV_CAP_RSVD_14_12 ),
.DEV_CAP_RSVD_17_16 ( DEV_CAP_RSVD_17_16 ),
.DEV_CAP_RSVD_31_29 ( DEV_CAP_RSVD_31_29 ),
.DEV_CAP2_ARI_FORWARDING_SUPPORTED ( DEV_CAP2_ARI_FORWARDING_SUPPORTED ),
.DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED ( DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED ),
.DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED ( DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED ),
.DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED ( DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED ),
.DEV_CAP2_CAS128_COMPLETER_SUPPORTED ( DEV_CAP2_CAS128_COMPLETER_SUPPORTED ),
.DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED ( DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED ),
.DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED ( DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED ),
.DEV_CAP2_LTR_MECHANISM_SUPPORTED ( DEV_CAP2_LTR_MECHANISM_SUPPORTED ),
.DEV_CAP2_MAX_ENDEND_TLP_PREFIXES ( DEV_CAP2_MAX_ENDEND_TLP_PREFIXES ),
.DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING ( DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING ),
.DEV_CAP2_TPH_COMPLETER_SUPPORTED ( DEV_CAP2_TPH_COMPLETER_SUPPORTED ),
.DEV_CONTROL_AUX_POWER_SUPPORTED ( DEV_CONTROL_AUX_POWER_SUPPORTED ),
.DEV_CONTROL_EXT_TAG_DEFAULT ( DEV_CONTROL_EXT_TAG_DEFAULT ),
.DISABLE_ASPM_L1_TIMER ( DISABLE_ASPM_L1_TIMER ),
.DISABLE_BAR_FILTERING ( DISABLE_BAR_FILTERING ),
.DISABLE_ERR_MSG ( DISABLE_ERR_MSG ),
.DISABLE_ID_CHECK ( DISABLE_ID_CHECK ),
.DISABLE_LANE_REVERSAL ( DISABLE_LANE_REVERSAL ),
.DISABLE_LOCKED_FILTER ( DISABLE_LOCKED_FILTER ),
.DISABLE_PPM_FILTER ( DISABLE_PPM_FILTER ),
.DISABLE_RX_POISONED_RESP ( DISABLE_RX_POISONED_RESP ),
.DISABLE_RX_TC_FILTER ( DISABLE_RX_TC_FILTER ),
.DISABLE_SCRAMBLING ( DISABLE_SCRAMBLING ),
.DNSTREAM_LINK_NUM ( DNSTREAM_LINK_NUM ),
.DSN_BASE_PTR ( DSN_BASE_PTR ),
.DSN_CAP_ID ( DSN_CAP_ID ),
.DSN_CAP_NEXTPTR ( DSN_CAP_NEXTPTR ),
.DSN_CAP_ON ( DSN_CAP_ON ),
.DSN_CAP_VERSION ( DSN_CAP_VERSION ),
.ENABLE_MSG_ROUTE ( ENABLE_MSG_ROUTE ),
.ENABLE_RX_TD_ECRC_TRIM ( ENABLE_RX_TD_ECRC_TRIM ),
.ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED ( ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED ),
.ENTER_RVRY_EI_L0 ( ENTER_RVRY_EI_L0 ),
.EXIT_LOOPBACK_ON_EI ( EXIT_LOOPBACK_ON_EI ),
.EXPANSION_ROM ( EXPANSION_ROM ),
.EXT_CFG_CAP_PTR ( EXT_CFG_CAP_PTR ),
.EXT_CFG_XP_CAP_PTR ( EXT_CFG_XP_CAP_PTR ),
.HEADER_TYPE ( HEADER_TYPE ),
.INFER_EI ( INFER_EI ),
.INTERRUPT_PIN ( INTERRUPT_PIN ),
.INTERRUPT_STAT_AUTO ( INTERRUPT_STAT_AUTO ),
.IS_SWITCH ( IS_SWITCH ),
.LAST_CONFIG_DWORD ( LAST_CONFIG_DWORD ),
.LINK_CAP_ASPM_OPTIONALITY ( LINK_CAP_ASPM_OPTIONALITY ),
.LINK_CAP_ASPM_SUPPORT ( LINK_CAP_ASPM_SUPPORT ),
.LINK_CAP_CLOCK_POWER_MANAGEMENT ( LINK_CAP_CLOCK_POWER_MANAGEMENT ),
.LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP ( LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP ),
.LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP ( LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP ),
.LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 ( LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 ),
.LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 ( LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 ),
.LINK_CAP_L0S_EXIT_LATENCY_GEN1 ( LINK_CAP_L0S_EXIT_LATENCY_GEN1 ),
.LINK_CAP_L0S_EXIT_LATENCY_GEN2 ( LINK_CAP_L0S_EXIT_LATENCY_GEN2 ),
.LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 ( LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 ),
.LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 ( LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 ),
.LINK_CAP_L1_EXIT_LATENCY_GEN1 ( LINK_CAP_L1_EXIT_LATENCY_GEN1 ),
.LINK_CAP_L1_EXIT_LATENCY_GEN2 ( LINK_CAP_L1_EXIT_LATENCY_GEN2 ),
.LINK_CAP_MAX_LINK_SPEED ( LINK_CAP_MAX_LINK_SPEED ),
.LINK_CAP_MAX_LINK_WIDTH ( LINK_CAP_MAX_LINK_WIDTH ),
.LINK_CAP_RSVD_23 ( LINK_CAP_RSVD_23 ),
.LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE ( LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE ),
.LINK_CONTROL_RCB ( LINK_CONTROL_RCB ),
.LINK_CTRL2_DEEMPHASIS ( LINK_CTRL2_DEEMPHASIS ),
.LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE ( LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE ),
.LINK_CTRL2_TARGET_LINK_SPEED ( LINK_CTRL2_TARGET_LINK_SPEED ),
.LINK_STATUS_SLOT_CLOCK_CONFIG ( LINK_STATUS_SLOT_CLOCK_CONFIG ),
.LL_ACK_TIMEOUT ( LL_ACK_TIMEOUT ),
.LL_ACK_TIMEOUT_EN ( LL_ACK_TIMEOUT_EN ),
.LL_ACK_TIMEOUT_FUNC ( LL_ACK_TIMEOUT_FUNC ),
.LL_REPLAY_TIMEOUT ( LL_REPLAY_TIMEOUT ),
.LL_REPLAY_TIMEOUT_EN ( LL_REPLAY_TIMEOUT_EN ),
.LL_REPLAY_TIMEOUT_FUNC ( LL_REPLAY_TIMEOUT_FUNC ),
.LTSSM_MAX_LINK_WIDTH ( LTSSM_MAX_LINK_WIDTH ),
.MPS_FORCE ( MPS_FORCE ),
.MSI_BASE_PTR ( MSI_BASE_PTR ),
.MSI_CAP_ID ( MSI_CAP_ID ),
.MSI_CAP_MULTIMSG_EXTENSION ( MSI_CAP_MULTIMSG_EXTENSION ),
.MSI_CAP_MULTIMSGCAP ( MSI_CAP_MULTIMSGCAP ),
.MSI_CAP_NEXTPTR ( MSI_CAP_NEXTPTR ),
.MSI_CAP_ON ( MSI_CAP_ON ),
.MSI_CAP_PER_VECTOR_MASKING_CAPABLE ( MSI_CAP_PER_VECTOR_MASKING_CAPABLE ),
.MSI_CAP_64_BIT_ADDR_CAPABLE ( MSI_CAP_64_BIT_ADDR_CAPABLE ),
.MSIX_BASE_PTR ( MSIX_BASE_PTR ),
.MSIX_CAP_ID ( MSIX_CAP_ID ),
.MSIX_CAP_NEXTPTR ( MSIX_CAP_NEXTPTR ),
.MSIX_CAP_ON ( MSIX_CAP_ON ),
.MSIX_CAP_PBA_BIR ( MSIX_CAP_PBA_BIR ),
.MSIX_CAP_PBA_OFFSET ( MSIX_CAP_PBA_OFFSET ),
.MSIX_CAP_TABLE_BIR ( MSIX_CAP_TABLE_BIR ),
.MSIX_CAP_TABLE_OFFSET ( MSIX_CAP_TABLE_OFFSET ),
.MSIX_CAP_TABLE_SIZE ( MSIX_CAP_TABLE_SIZE ),
.N_FTS_COMCLK_GEN1 ( N_FTS_COMCLK_GEN1 ),
.N_FTS_COMCLK_GEN2 ( N_FTS_COMCLK_GEN2 ),
.N_FTS_GEN1 ( N_FTS_GEN1 ),
.N_FTS_GEN2 ( N_FTS_GEN2 ),
.PCIE_BASE_PTR ( PCIE_BASE_PTR ),
.PCIE_CAP_CAPABILITY_ID ( PCIE_CAP_CAPABILITY_ID ),
.PCIE_CAP_CAPABILITY_VERSION ( PCIE_CAP_CAPABILITY_VERSION ),
.PCIE_CAP_DEVICE_PORT_TYPE ( PCIE_CAP_DEVICE_PORT_TYPE ),
.PCIE_CAP_NEXTPTR ( PCIE_CAP_NEXTPTR ),
.PCIE_CAP_ON ( PCIE_CAP_ON ),
.PCIE_CAP_RSVD_15_14 ( PCIE_CAP_RSVD_15_14 ),
.PCIE_CAP_SLOT_IMPLEMENTED ( PCIE_CAP_SLOT_IMPLEMENTED ),
.PCIE_REVISION ( PCIE_REVISION ),
.PL_AUTO_CONFIG ( PL_AUTO_CONFIG ),
.PL_FAST_TRAIN ( PL_FAST_TRAIN ),
.PM_ASPML0S_TIMEOUT ( PM_ASPML0S_TIMEOUT ),
.PM_ASPML0S_TIMEOUT_EN ( PM_ASPML0S_TIMEOUT_EN ),
.PM_ASPML0S_TIMEOUT_FUNC ( PM_ASPML0S_TIMEOUT_FUNC ),
.PM_ASPM_FASTEXIT ( PM_ASPM_FASTEXIT ),
.PM_BASE_PTR ( PM_BASE_PTR ),
.PM_CAP_AUXCURRENT ( PM_CAP_AUXCURRENT ),
.PM_CAP_DSI ( PM_CAP_DSI ),
.PM_CAP_D1SUPPORT ( PM_CAP_D1SUPPORT ),
.PM_CAP_D2SUPPORT ( PM_CAP_D2SUPPORT ),
.PM_CAP_ID ( PM_CAP_ID ),
.PM_CAP_NEXTPTR ( PM_CAP_NEXTPTR ),
.PM_CAP_ON ( PM_CAP_ON ),
.PM_CAP_PME_CLOCK ( PM_CAP_PME_CLOCK ),
.PM_CAP_PMESUPPORT ( PM_CAP_PMESUPPORT ),
.PM_CAP_RSVD_04 ( PM_CAP_RSVD_04 ),
.PM_CAP_VERSION ( PM_CAP_VERSION ),
.PM_CSR_BPCCEN ( PM_CSR_BPCCEN ),
.PM_CSR_B2B3 ( PM_CSR_B2B3 ),
.PM_CSR_NOSOFTRST ( PM_CSR_NOSOFTRST ),
.PM_DATA_SCALE0 ( PM_DATA_SCALE0 ),
.PM_DATA_SCALE1 ( PM_DATA_SCALE1 ),
.PM_DATA_SCALE2 ( PM_DATA_SCALE2 ),
.PM_DATA_SCALE3 ( PM_DATA_SCALE3 ),
.PM_DATA_SCALE4 ( PM_DATA_SCALE4 ),
.PM_DATA_SCALE5 ( PM_DATA_SCALE5 ),
.PM_DATA_SCALE6 ( PM_DATA_SCALE6 ),
.PM_DATA_SCALE7 ( PM_DATA_SCALE7 ),
.PM_DATA0 ( PM_DATA0 ),
.PM_DATA1 ( PM_DATA1 ),
.PM_DATA2 ( PM_DATA2 ),
.PM_DATA3 ( PM_DATA3 ),
.PM_DATA4 ( PM_DATA4 ),
.PM_DATA5 ( PM_DATA5 ),
.PM_DATA6 ( PM_DATA6 ),
.PM_DATA7 ( PM_DATA7 ),
.PM_MF ( PM_MF ),
.RBAR_BASE_PTR ( RBAR_BASE_PTR ),
.RBAR_CAP_CONTROL_ENCODEDBAR0 ( RBAR_CAP_CONTROL_ENCODEDBAR0 ),
.RBAR_CAP_CONTROL_ENCODEDBAR1 ( RBAR_CAP_CONTROL_ENCODEDBAR1 ),
.RBAR_CAP_CONTROL_ENCODEDBAR2 ( RBAR_CAP_CONTROL_ENCODEDBAR2 ),
.RBAR_CAP_CONTROL_ENCODEDBAR3 ( RBAR_CAP_CONTROL_ENCODEDBAR3 ),
.RBAR_CAP_CONTROL_ENCODEDBAR4 ( RBAR_CAP_CONTROL_ENCODEDBAR4 ),
.RBAR_CAP_CONTROL_ENCODEDBAR5 ( RBAR_CAP_CONTROL_ENCODEDBAR5 ),
.RBAR_CAP_ID ( RBAR_CAP_ID ),
.RBAR_CAP_INDEX0 ( RBAR_CAP_INDEX0 ),
.RBAR_CAP_INDEX1 ( RBAR_CAP_INDEX1 ),
.RBAR_CAP_INDEX2 ( RBAR_CAP_INDEX2 ),
.RBAR_CAP_INDEX3 ( RBAR_CAP_INDEX3 ),
.RBAR_CAP_INDEX4 ( RBAR_CAP_INDEX4 ),
.RBAR_CAP_INDEX5 ( RBAR_CAP_INDEX5 ),
.RBAR_CAP_NEXTPTR ( RBAR_CAP_NEXTPTR ),
.RBAR_CAP_ON ( RBAR_CAP_ON ),
.RBAR_CAP_SUP0 ( RBAR_CAP_SUP0 ),
.RBAR_CAP_SUP1 ( RBAR_CAP_SUP1 ),
.RBAR_CAP_SUP2 ( RBAR_CAP_SUP2 ),
.RBAR_CAP_SUP3 ( RBAR_CAP_SUP3 ),
.RBAR_CAP_SUP4 ( RBAR_CAP_SUP4 ),
.RBAR_CAP_SUP5 ( RBAR_CAP_SUP5 ),
.RBAR_CAP_VERSION ( RBAR_CAP_VERSION ),
.RBAR_NUM ( RBAR_NUM ),
.RECRC_CHK ( RECRC_CHK ),
.RECRC_CHK_TRIM ( RECRC_CHK_TRIM ),
.ROOT_CAP_CRS_SW_VISIBILITY ( ROOT_CAP_CRS_SW_VISIBILITY ),
.RP_AUTO_SPD ( RP_AUTO_SPD ),
.RP_AUTO_SPD_LOOPCNT ( RP_AUTO_SPD_LOOPCNT ),
.SELECT_DLL_IF ( SELECT_DLL_IF ),
.SLOT_CAP_ATT_BUTTON_PRESENT ( SLOT_CAP_ATT_BUTTON_PRESENT ),
.SLOT_CAP_ATT_INDICATOR_PRESENT ( SLOT_CAP_ATT_INDICATOR_PRESENT ),
.SLOT_CAP_ELEC_INTERLOCK_PRESENT ( SLOT_CAP_ELEC_INTERLOCK_PRESENT ),
.SLOT_CAP_HOTPLUG_CAPABLE ( SLOT_CAP_HOTPLUG_CAPABLE ),
.SLOT_CAP_HOTPLUG_SURPRISE ( SLOT_CAP_HOTPLUG_SURPRISE ),
.SLOT_CAP_MRL_SENSOR_PRESENT ( SLOT_CAP_MRL_SENSOR_PRESENT ),
.SLOT_CAP_NO_CMD_COMPLETED_SUPPORT ( SLOT_CAP_NO_CMD_COMPLETED_SUPPORT ),
.SLOT_CAP_PHYSICAL_SLOT_NUM ( SLOT_CAP_PHYSICAL_SLOT_NUM ),
.SLOT_CAP_POWER_CONTROLLER_PRESENT ( SLOT_CAP_POWER_CONTROLLER_PRESENT ),
.SLOT_CAP_POWER_INDICATOR_PRESENT ( SLOT_CAP_POWER_INDICATOR_PRESENT ),
.SLOT_CAP_SLOT_POWER_LIMIT_SCALE ( SLOT_CAP_SLOT_POWER_LIMIT_SCALE ),
.SLOT_CAP_SLOT_POWER_LIMIT_VALUE ( SLOT_CAP_SLOT_POWER_LIMIT_VALUE ),
.SPARE_BIT0 ( SPARE_BIT0 ),
.SPARE_BIT1 ( SPARE_BIT1 ),
.SPARE_BIT2 ( SPARE_BIT2 ),
.SPARE_BIT3 ( SPARE_BIT3 ),
.SPARE_BIT4 ( SPARE_BIT4 ),
.SPARE_BIT5 ( SPARE_BIT5 ),
.SPARE_BIT6 ( SPARE_BIT6 ),
.SPARE_BIT7 ( SPARE_BIT7 ),
.SPARE_BIT8 ( SPARE_BIT8 ),
.SPARE_BYTE0 ( SPARE_BYTE0 ),
.SPARE_BYTE1 ( SPARE_BYTE1 ),
.SPARE_BYTE2 ( SPARE_BYTE2 ),
.SPARE_BYTE3 ( SPARE_BYTE3 ),
.SPARE_WORD0 ( SPARE_WORD0 ),
.SPARE_WORD1 ( SPARE_WORD1 ),
.SPARE_WORD2 ( SPARE_WORD2 ),
.SPARE_WORD3 ( SPARE_WORD3 ),
.SSL_MESSAGE_AUTO ( SSL_MESSAGE_AUTO ),
.TECRC_EP_INV ( TECRC_EP_INV ),
.TL_RBYPASS ( TL_RBYPASS ),
.TL_RX_RAM_RADDR_LATENCY ( TL_RX_RAM_RADDR_LATENCY ),
.TL_RX_RAM_RDATA_LATENCY ( TL_RX_RAM_RDATA_LATENCY ),
.TL_RX_RAM_WRITE_LATENCY ( TL_RX_RAM_WRITE_LATENCY ),
.TL_TFC_DISABLE ( TL_TFC_DISABLE ),
.TL_TX_CHECKS_DISABLE ( TL_TX_CHECKS_DISABLE ),
.TL_TX_RAM_RADDR_LATENCY ( TL_TX_RAM_RADDR_LATENCY ),
.TL_TX_RAM_RDATA_LATENCY ( TL_TX_RAM_RDATA_LATENCY ),
.TL_TX_RAM_WRITE_LATENCY ( TL_TX_RAM_WRITE_LATENCY ),
.TRN_DW ( TRN_DW ),
.TRN_NP_FC ( TRN_NP_FC ),
.UPCONFIG_CAPABLE ( UPCONFIG_CAPABLE ),
.UPSTREAM_FACING ( UPSTREAM_FACING ),
.UR_ATOMIC ( UR_ATOMIC ),
.UR_CFG1 ( UR_CFG1 ),
.UR_INV_REQ ( UR_INV_REQ ),
.UR_PRS_RESPONSE ( UR_PRS_RESPONSE ),
.USE_RID_PINS ( USE_RID_PINS ),
.USER_CLK_FREQ ( USER_CLK_FREQ ),
.USER_CLK2_DIV2 ( USER_CLK2_DIV2 ),
.VC_BASE_PTR ( VC_BASE_PTR ),
.VC_CAP_ID ( VC_CAP_ID ),
.VC_CAP_NEXTPTR ( VC_CAP_NEXTPTR ),
.VC_CAP_ON ( VC_CAP_ON ),
.VC_CAP_REJECT_SNOOP_TRANSACTIONS ( VC_CAP_REJECT_SNOOP_TRANSACTIONS ),
.VC_CAP_VERSION ( VC_CAP_VERSION ),
.VC0_CPL_INFINITE ( VC0_CPL_INFINITE ),
.VC0_RX_RAM_LIMIT ( VC0_RX_RAM_LIMIT ),
.VC0_TOTAL_CREDITS_CD ( VC0_TOTAL_CREDITS_CD ),
.VC0_TOTAL_CREDITS_CH ( VC0_TOTAL_CREDITS_CH ),
.VC0_TOTAL_CREDITS_NPD ( VC0_TOTAL_CREDITS_NPD ),
.VC0_TOTAL_CREDITS_NPH ( VC0_TOTAL_CREDITS_NPH ),
.VC0_TOTAL_CREDITS_PD ( VC0_TOTAL_CREDITS_PD ),
.VC0_TOTAL_CREDITS_PH ( VC0_TOTAL_CREDITS_PH ),
.VC0_TX_LASTPACKET ( VC0_TX_LASTPACKET ),
.VSEC_BASE_PTR ( VSEC_BASE_PTR ),
.VSEC_CAP_HDR_ID ( VSEC_CAP_HDR_ID ),
.VSEC_CAP_HDR_REVISION ( VSEC_CAP_HDR_REVISION ),
.VSEC_CAP_ID ( VSEC_CAP_ID ),
.VSEC_CAP_IS_LINK_VISIBLE ( VSEC_CAP_IS_LINK_VISIBLE ),
.VSEC_CAP_NEXTPTR ( VSEC_CAP_NEXTPTR ),
.VSEC_CAP_ON ( VSEC_CAP_ON ),
.VSEC_CAP_VERSION ( VSEC_CAP_VERSION )
`ifdef B_TESTMODE
,
.TEST_MODE_PIN_CHAR ( TEST_MODE_PIN_CHAR )
`endif
)
pcie_block_i (
.TRNTD (trn_td ),
.TRNTREM (trn_trem ),
.TRNTSOF (trn_tsof ),
.TRNTEOF (trn_teof ),
.TRNTSRCRDY (trn_tsrc_rdy ),
.TRNTSRCDSC (trn_tsrc_dsc ),
.TRNTERRFWD (trn_terrfwd ),
.TRNTECRCGEN (trn_tecrc_gen ),
.TRNTSTR (trn_tstr ),
.TRNTCFGGNT (trn_tcfg_gnt ),
.TRNRDSTRDY (trn_rdst_rdy ),
.TRNRNPREQ (trn_rnp_req ),
.TRNRFCPRET (trn_rfcp_ret ),
.TRNRNPOK (trn_rnp_ok ),
.TRNFCSEL (trn_fc_sel ),
.MIMTXRDATA (mim_tx_rdata ),
.MIMRXRDATA (mim_rx_rdata ),
.TRNTDLLPDATA (trn_tdllp_data ),
.TRNTDLLPSRCRDY (trn_tdllp_src_rdy ),
.LL2TLPRCV (ll2_tlp_rcv ),
.LL2SENDENTERL1 (ll2_send_enter_l1 ),
.LL2SENDENTERL23 (ll2_send_enter_l23 ),
.LL2SENDASREQL1 (ll2_send_as_req_l1 ),
.LL2SENDPMACK (ll2_send_pm_ack ),
.PL2DIRECTEDLSTATE (pl2_directed_lstate ),
.LL2SUSPENDNOW (ll2_suspend_now ),
.TL2PPMSUSPENDREQ (tl2_ppm_suspend_req ),
.TL2ASPMSUSPENDCREDITCHECK (tl2_aspm_suspend_credit_check ),
.PLDIRECTEDLINKCHANGE (pl_directed_link_change ),
.PLDIRECTEDLINKWIDTH (pl_directed_link_width ),
.PLDIRECTEDLINKSPEED (pl_directed_link_speed ),
.PLDIRECTEDLINKAUTON (pl_directed_link_auton ),
.PLUPSTREAMPREFERDEEMPH (pl_upstream_prefer_deemph ),
.PLDOWNSTREAMDEEMPHSOURCE (pl_downstream_deemph_source ),
.PLDIRECTEDLTSSMNEW (pl_directed_ltssm_new ),
.PLDIRECTEDLTSSMNEWVLD (pl_directed_ltssm_new_vld ),
.PLDIRECTEDLTSSMSTALL (pl_directed_ltssm_stall ),
.PIPERX0CHARISK (pipe_rx0_char_is_k ),
.PIPERX1CHARISK (pipe_rx1_char_is_k ),
.PIPERX2CHARISK (pipe_rx2_char_is_k ),
.PIPERX3CHARISK (pipe_rx3_char_is_k ),
.PIPERX4CHARISK (pipe_rx4_char_is_k ),
.PIPERX5CHARISK (pipe_rx5_char_is_k ),
.PIPERX6CHARISK (pipe_rx6_char_is_k ),
.PIPERX7CHARISK (pipe_rx7_char_is_k ),
.PIPERX0VALID (pipe_rx0_valid ),
.PIPERX1VALID (pipe_rx1_valid ),
.PIPERX2VALID (pipe_rx2_valid ),
.PIPERX3VALID (pipe_rx3_valid ),
.PIPERX4VALID (pipe_rx4_valid ),
.PIPERX5VALID (pipe_rx5_valid ),
.PIPERX6VALID (pipe_rx6_valid ),
.PIPERX7VALID (pipe_rx7_valid ),
.PIPERX0DATA (pipe_rx0_data ),
.PIPERX1DATA (pipe_rx1_data ),
.PIPERX2DATA (pipe_rx2_data ),
.PIPERX3DATA (pipe_rx3_data ),
.PIPERX4DATA (pipe_rx4_data ),
.PIPERX5DATA (pipe_rx5_data ),
.PIPERX6DATA (pipe_rx6_data ),
.PIPERX7DATA (pipe_rx7_data ),
.PIPERX0CHANISALIGNED (pipe_rx0_chanisaligned ),
.PIPERX1CHANISALIGNED (pipe_rx1_chanisaligned ),
.PIPERX2CHANISALIGNED (pipe_rx2_chanisaligned ),
.PIPERX3CHANISALIGNED (pipe_rx3_chanisaligned ),
.PIPERX4CHANISALIGNED (pipe_rx4_chanisaligned ),
.PIPERX5CHANISALIGNED (pipe_rx5_chanisaligned ),
.PIPERX6CHANISALIGNED (pipe_rx6_chanisaligned ),
.PIPERX7CHANISALIGNED (pipe_rx7_chanisaligned ),
.PIPERX0STATUS (pipe_rx0_status ),
.PIPERX1STATUS (pipe_rx1_status ),
.PIPERX2STATUS (pipe_rx2_status ),
.PIPERX3STATUS (pipe_rx3_status ),
.PIPERX4STATUS (pipe_rx4_status ),
.PIPERX5STATUS (pipe_rx5_status ),
.PIPERX6STATUS (pipe_rx6_status ),
.PIPERX7STATUS (pipe_rx7_status ),
.PIPERX0PHYSTATUS (pipe_rx0_phy_status ),
.PIPERX1PHYSTATUS (pipe_rx1_phy_status ),
.PIPERX2PHYSTATUS (pipe_rx2_phy_status ),
.PIPERX3PHYSTATUS (pipe_rx3_phy_status ),
.PIPERX4PHYSTATUS (pipe_rx4_phy_status ),
.PIPERX5PHYSTATUS (pipe_rx5_phy_status ),
.PIPERX6PHYSTATUS (pipe_rx6_phy_status ),
.PIPERX7PHYSTATUS (pipe_rx7_phy_status ),
.PIPERX0ELECIDLE (pipe_rx0_elec_idle ),
.PIPERX1ELECIDLE (pipe_rx1_elec_idle ),
.PIPERX2ELECIDLE (pipe_rx2_elec_idle ),
.PIPERX3ELECIDLE (pipe_rx3_elec_idle ),
.PIPERX4ELECIDLE (pipe_rx4_elec_idle ),
.PIPERX5ELECIDLE (pipe_rx5_elec_idle ),
.PIPERX6ELECIDLE (pipe_rx6_elec_idle ),
.PIPERX7ELECIDLE (pipe_rx7_elec_idle ),
.PIPECLK (pipe_clk ),
.USERCLK (user_clk ),
.USERCLK2 (user_clk2 ),
`ifdef VALIDATION
.USERCLKPREBUF (user_clk_prebuf ),
.USERCLKPREBUFEN (user_clk_prebuf_en ),
`endif
`ifdef B_TESTMODE
.USERCLKPREBUF (user_clk_prebuf ),
.USERCLKPREBUFEN (user_clk_prebuf_en ),
.SCANMODEN (scanmode_n ),
.SCANENABLEN (scanenable_n ),
.EDTCLK (edt_clk ),
.EDTUPDATE (edt_update ),
.EDTBYPASS (edt_bypass ),
.EDTCONFIGURATION (edt_configuration ),
.EDTSINGLEBYPASSCHAIN (edt_single_bypass_chain ),
.EDTCHANNELSIN1 (edt_channels_in1 ),
.EDTCHANNELSIN2 (edt_channels_in2 ),
.EDTCHANNELSIN3 (edt_channels_in3 ),
.EDTCHANNELSIN4 (edt_channels_in4 ),
.EDTCHANNELSIN5 (edt_channels_in5 ),
.EDTCHANNELSIN6 (edt_channels_in6 ),
.EDTCHANNELSIN7 (edt_channels_in7 ),
.EDTCHANNELSIN8 (edt_channels_in8 ),
.PMVENABLEN (pmv_enable_n ),
.PMVSELECT (pmv_select ),
.PMVDIVIDE (pmv_divide ),
`endif
//`ifdef SECUREIP
// .GSR (gsr ),
//`endif
.SYSRSTN (sys_rst_n ),
.CMRSTN (cm_rst_n ),
.CMSTICKYRSTN (cm_sticky_rst_n ),
.FUNCLVLRSTN (func_lvl_rst_n ),
.TLRSTN (tl_rst_n ),
.DLRSTN (dl_rst_n ),
.PLRSTN (pl_rst_n ),
.PLTRANSMITHOTRST (pl_transmit_hot_rst ),
// Global pins not on Holistic model
//.CFGRESET (cfg_reset ),
//.GWE (gwe ),
//.GRESTORE (grestore ),
//.GHIGHB (ghigh_b ),
.CFGMGMTDI (cfg_mgmt_di ),
.CFGMGMTBYTEENN (cfg_mgmt_byte_en_n ),
.CFGMGMTDWADDR (cfg_mgmt_dwaddr ),
.CFGMGMTWRRW1CASRWN (cfg_mgmt_wr_rw1c_as_rw_n ),
.CFGMGMTWRREADONLYN (cfg_mgmt_wr_readonly_n ),
.CFGMGMTWRENN (cfg_mgmt_wr_en_n ),
.CFGMGMTRDENN (cfg_mgmt_rd_en_n ),
.CFGERRMALFORMEDN (cfg_err_malformed_n ),
.CFGERRCORN (cfg_err_cor_n ),
.CFGERRURN (cfg_err_ur_n ),
.CFGERRECRCN (cfg_err_ecrc_n ),
.CFGERRCPLTIMEOUTN (cfg_err_cpl_timeout_n ),
.CFGERRCPLABORTN (cfg_err_cpl_abort_n ),
.CFGERRCPLUNEXPECTN (cfg_err_cpl_unexpect_n ),
.CFGERRPOISONEDN (cfg_err_poisoned_n ),
.CFGERRACSN (cfg_err_acs_n ),
.CFGERRATOMICEGRESSBLOCKEDN (cfg_err_atomic_egress_blocked_n ),
.CFGERRMCBLOCKEDN (cfg_err_mc_blocked_n ),
.CFGERRINTERNALUNCORN (cfg_err_internal_uncor_n ),
.CFGERRINTERNALCORN (cfg_err_internal_cor_n ),
.CFGERRPOSTEDN (cfg_err_posted_n ),
.CFGERRLOCKEDN (cfg_err_locked_n ),
.CFGERRNORECOVERYN (cfg_err_norecovery_n ),
.CFGERRAERHEADERLOG (cfg_err_aer_headerlog ),
.CFGERRTLPCPLHEADER (cfg_err_tlp_cpl_header ),
.CFGINTERRUPTN (cfg_interrupt_n ),
.CFGINTERRUPTDI (cfg_interrupt_di ),
.CFGINTERRUPTASSERTN (cfg_interrupt_assert_n ),
.CFGINTERRUPTSTATN (cfg_interrupt_stat_n ),
.CFGDSBUSNUMBER (cfg_ds_bus_number ),
.CFGDSDEVICENUMBER (cfg_ds_device_number ),
.CFGDSFUNCTIONNUMBER (cfg_ds_function_number ),
.CFGPORTNUMBER (cfg_port_number ),
.CFGPMHALTASPML0SN (cfg_pm_halt_aspm_l0s_n ),
.CFGPMHALTASPML1N (cfg_pm_halt_aspm_l1_n ),
.CFGPMFORCESTATEENN (cfg_pm_force_state_en_n ),
.CFGPMFORCESTATE (cfg_pm_force_state ),
.CFGPMWAKEN (cfg_pm_wake_n ),
.CFGPMTURNOFFOKN (cfg_pm_turnoff_ok_n ),
.CFGPMSENDPMETON (cfg_pm_send_pme_to_n ),
.CFGPCIECAPINTERRUPTMSGNUM (cfg_pciecap_interrupt_msgnum ),
.CFGTRNPENDINGN (cfg_trn_pending_n ),
.CFGFORCEMPS (cfg_force_mps ),
.CFGFORCECOMMONCLOCKOFF (cfg_force_common_clock_off ),
.CFGFORCEEXTENDEDSYNCON (cfg_force_extended_sync_on ),
.CFGDSN (cfg_dsn ),
.CFGDEVID (cfg_dev_id ),
.CFGVENDID (cfg_vend_id ),
.CFGREVID (cfg_rev_id ),
.CFGSUBSYSID (cfg_subsys_id ),
.CFGSUBSYSVENDID (cfg_subsys_vend_id ),
.CFGAERINTERRUPTMSGNUM (cfg_aer_interrupt_msgnum ),
.DRPCLK (drp_clk ),
.DRPEN (drp_en ),
.DRPWE (drp_we ),
.DRPADDR (drp_addr ),
.DRPDI (drp_di ),
//.DRPREADPORT0 (drp_read_port_0 ),
//.DRPREADPORT1 (drp_read_port_1 ),
//.DRPREADPORT2 (drp_read_port_2 ),
//.DRPREADPORT3 (drp_read_port_3 ),
//.DRPREADPORT4 (drp_read_port_4 ),
//.DRPREADPORT5 (drp_read_port_5 ),
//.DRPREADPORT6 (drp_read_port_6 ),
//.DRPREADPORT7 (drp_read_port_7 ),
//.DRPREADPORT8 (drp_read_port_8 ),
//.DRPREADPORT9 (drp_read_port_9 ),
//.DRPREADPORT10 (drp_read_port_10 ),
//.DRPREADPORT11 (drp_read_port_11 ),
//.DRPREADPORT12 (drp_read_port_12 ),
.DBGMODE (dbg_mode ),
.DBGSUBMODE (dbg_sub_mode ),
.PLDBGMODE (pl_dbg_mode ),
.TRNTDSTRDY (trn_tdst_rdy_bus ),
.TRNTERRDROP (trn_terr_drop ),
.TRNTBUFAV (trn_tbuf_av ),
.TRNTCFGREQ (trn_tcfg_req ),
.TRNRD (trn_rd ),
.TRNRREM (trn_rrem ),
.TRNRSOF (trn_rsof ),
.TRNREOF (trn_reof ),
.TRNRSRCRDY (trn_rsrc_rdy ),
.TRNRSRCDSC (trn_rsrc_dsc ),
.TRNRECRCERR (trn_recrc_err ),
.TRNRERRFWD (trn_rerrfwd ),
.TRNRBARHIT (trn_rbar_hit ),
.TRNLNKUP (trn_lnk_up ),
.TRNFCPH (trn_fc_ph ),
.TRNFCPD (trn_fc_pd ),
.TRNFCNPH (trn_fc_nph ),
.TRNFCNPD (trn_fc_npd ),
.TRNFCCPLH (trn_fc_cplh ),
.TRNFCCPLD (trn_fc_cpld ),
.MIMTXWDATA (mim_tx_wdata ),
.MIMTXWADDR (mim_tx_waddr ),
.MIMTXWEN (mim_tx_wen ),
.MIMTXRADDR (mim_tx_raddr ),
.MIMTXREN (mim_tx_ren ),
.MIMRXWDATA (mim_rx_wdata ),
.MIMRXWADDR (mim_rx_waddr ),
.MIMRXWEN (mim_rx_wen ),
.MIMRXRADDR (mim_rx_raddr ),
.MIMRXREN (mim_rx_ren ),
.TRNTDLLPDSTRDY (trn_tdllp_dst_rdy ),
.TRNRDLLPDATA (trn_rdllp_data ),
.TRNRDLLPSRCRDY (trn_rdllp_src_rdy ),
.LL2TFCINIT1SEQ (ll2_tfc_init1_seq ),
.LL2TFCINIT2SEQ (ll2_tfc_init2_seq ),
.PL2SUSPENDOK (pl2_suspend_ok ),
.PL2RECOVERY (pl2_recovery ),
.PL2RXELECIDLE (pl2_rx_elec_idle ),
.PL2RXPMSTATE (pl2_rx_pm_state ),
.PL2L0REQ (pl2_l0_req ),
.LL2SUSPENDOK (ll2_suspend_ok ),
.LL2TXIDLE (ll2_tx_idle ),
.LL2LINKSTATUS (ll2_link_status ),
.TL2PPMSUSPENDOK (tl2_ppm_suspend_ok ),
.TL2ASPMSUSPENDREQ (tl2_aspm_suspend_req ),
.TL2ASPMSUSPENDCREDITCHECKOK (tl2_aspm_suspend_credit_check_ok ),
.PL2LINKUP (pl2_link_up ),
.PL2RECEIVERERR (pl2_receiver_err ),
.LL2RECEIVERERR (ll2_receiver_err ),
.LL2PROTOCOLERR (ll2_protocol_err ),
.LL2BADTLPERR (ll2_bad_tlp_err ),
.LL2BADDLLPERR (ll2_bad_dllp_err ),
.LL2REPLAYROERR (ll2_replay_ro_err ),
.LL2REPLAYTOERR (ll2_replay_to_err ),
.TL2ERRHDR (tl2_err_hdr ),
.TL2ERRMALFORMED (tl2_err_malformed ),
.TL2ERRRXOVERFLOW (tl2_err_rxoverflow ),
.TL2ERRFCPE (tl2_err_fcpe ),
.PLSELLNKRATE (pl_sel_lnk_rate ),
.PLSELLNKWIDTH (pl_sel_lnk_width ),
.PLLTSSMSTATE (pl_ltssm_state ),
.PLLANEREVERSALMODE (pl_lane_reversal_mode ),
.PLPHYLNKUPN (pl_phy_lnk_up_n ),
.PLTXPMSTATE (pl_tx_pm_state ),
.PLRXPMSTATE (pl_rx_pm_state ),
.PLLINKUPCFGCAP (pl_link_upcfg_cap ),
.PLLINKGEN2CAP (pl_link_gen2_cap ),
.PLLINKPARTNERGEN2SUPPORTED (pl_link_partner_gen2_supported ),
.PLINITIALLINKWIDTH (pl_initial_link_width ),
.PLDIRECTEDCHANGEDONE (pl_directed_change_done ),
.PIPETXRCVRDET (pipe_tx_rcvr_det ),
.PIPETXRESET (pipe_tx_reset ),
.PIPETXRATE (pipe_tx_rate ),
.PIPETXDEEMPH (pipe_tx_deemph ),
.PIPETXMARGIN (pipe_tx_margin ),
.PIPERX0POLARITY (pipe_rx0_polarity ),
.PIPERX1POLARITY (pipe_rx1_polarity ),
.PIPERX2POLARITY (pipe_rx2_polarity ),
.PIPERX3POLARITY (pipe_rx3_polarity ),
.PIPERX4POLARITY (pipe_rx4_polarity ),
.PIPERX5POLARITY (pipe_rx5_polarity ),
.PIPERX6POLARITY (pipe_rx6_polarity ),
.PIPERX7POLARITY (pipe_rx7_polarity ),
.PIPETX0COMPLIANCE (pipe_tx0_compliance ),
.PIPETX1COMPLIANCE (pipe_tx1_compliance ),
.PIPETX2COMPLIANCE (pipe_tx2_compliance ),
.PIPETX3COMPLIANCE (pipe_tx3_compliance ),
.PIPETX4COMPLIANCE (pipe_tx4_compliance ),
.PIPETX5COMPLIANCE (pipe_tx5_compliance ),
.PIPETX6COMPLIANCE (pipe_tx6_compliance ),
.PIPETX7COMPLIANCE (pipe_tx7_compliance ),
.PIPETX0CHARISK (pipe_tx0_char_is_k ),
.PIPETX1CHARISK (pipe_tx1_char_is_k ),
.PIPETX2CHARISK (pipe_tx2_char_is_k ),
.PIPETX3CHARISK (pipe_tx3_char_is_k ),
.PIPETX4CHARISK (pipe_tx4_char_is_k ),
.PIPETX5CHARISK (pipe_tx5_char_is_k ),
.PIPETX6CHARISK (pipe_tx6_char_is_k ),
.PIPETX7CHARISK (pipe_tx7_char_is_k ),
.PIPETX0DATA (pipe_tx0_data ),
.PIPETX1DATA (pipe_tx1_data ),
.PIPETX2DATA (pipe_tx2_data ),
.PIPETX3DATA (pipe_tx3_data ),
.PIPETX4DATA (pipe_tx4_data ),
.PIPETX5DATA (pipe_tx5_data ),
.PIPETX6DATA (pipe_tx6_data ),
.PIPETX7DATA (pipe_tx7_data ),
.PIPETX0ELECIDLE (pipe_tx0_elec_idle ),
.PIPETX1ELECIDLE (pipe_tx1_elec_idle ),
.PIPETX2ELECIDLE (pipe_tx2_elec_idle ),
.PIPETX3ELECIDLE (pipe_tx3_elec_idle ),
.PIPETX4ELECIDLE (pipe_tx4_elec_idle ),
.PIPETX5ELECIDLE (pipe_tx5_elec_idle ),
.PIPETX6ELECIDLE (pipe_tx6_elec_idle ),
.PIPETX7ELECIDLE (pipe_tx7_elec_idle ),
.PIPETX0POWERDOWN (pipe_tx0_powerdown ),
.PIPETX1POWERDOWN (pipe_tx1_powerdown ),
.PIPETX2POWERDOWN (pipe_tx2_powerdown ),
.PIPETX3POWERDOWN (pipe_tx3_powerdown ),
.PIPETX4POWERDOWN (pipe_tx4_powerdown ),
.PIPETX5POWERDOWN (pipe_tx5_powerdown ),
.PIPETX6POWERDOWN (pipe_tx6_powerdown ),
.PIPETX7POWERDOWN (pipe_tx7_powerdown ),
`ifdef B_TESTMODE
.PMVOUT (pmv_out ),
.SCANOUT (scanout ),
`endif
.USERRSTN (user_rst_n ),
.PLRECEIVEDHOTRST (pl_received_hot_rst ),
.RECEIVEDFUNCLVLRSTN (received_func_lvl_rst_n ),
.LNKCLKEN (lnk_clk_en ),
.CFGMGMTDO (cfg_mgmt_do ),
.CFGMGMTRDWRDONEN (cfg_mgmt_rd_wr_done_n ),
.CFGERRAERHEADERLOGSETN (cfg_err_aer_headerlog_set_n ),
.CFGERRCPLRDYN (cfg_err_cpl_rdy_n ),
.CFGINTERRUPTRDYN (cfg_interrupt_rdy_n ),
.CFGINTERRUPTMMENABLE (cfg_interrupt_mmenable ),
.CFGINTERRUPTMSIENABLE (cfg_interrupt_msienable ),
.CFGINTERRUPTDO (cfg_interrupt_do ),
.CFGINTERRUPTMSIXENABLE (cfg_interrupt_msixenable ),
.CFGINTERRUPTMSIXFM (cfg_interrupt_msixfm ),
.CFGMSGRECEIVED (cfg_msg_received ),
.CFGMSGDATA (cfg_msg_data ),
.CFGMSGRECEIVEDERRCOR (cfg_msg_received_err_cor ),
.CFGMSGRECEIVEDERRNONFATAL (cfg_msg_received_err_non_fatal ),
.CFGMSGRECEIVEDERRFATAL (cfg_msg_received_err_fatal ),
.CFGMSGRECEIVEDASSERTINTA (cfg_msg_received_assert_int_a ),
.CFGMSGRECEIVEDDEASSERTINTA (cfg_msg_received_deassert_int_a ),
.CFGMSGRECEIVEDASSERTINTB (cfg_msg_received_assert_int_b ),
.CFGMSGRECEIVEDDEASSERTINTB (cfg_msg_received_deassert_int_b ),
.CFGMSGRECEIVEDASSERTINTC (cfg_msg_received_assert_int_c ),
.CFGMSGRECEIVEDDEASSERTINTC (cfg_msg_received_deassert_int_c ),
.CFGMSGRECEIVEDASSERTINTD (cfg_msg_received_assert_int_d ),
.CFGMSGRECEIVEDDEASSERTINTD (cfg_msg_received_deassert_int_d ),
.CFGMSGRECEIVEDPMPME (cfg_msg_received_pm_pme ),
.CFGMSGRECEIVEDPMETOACK (cfg_msg_received_pme_to_ack ),
.CFGMSGRECEIVEDPMETO (cfg_msg_received_pme_to ),
.CFGMSGRECEIVEDSETSLOTPOWERLIMIT (cfg_msg_received_setslotpowerlimit ),
.CFGMSGRECEIVEDUNLOCK (cfg_msg_received_unlock ),
.CFGMSGRECEIVEDPMASNAK (cfg_msg_received_pm_as_nak ),
.CFGPCIELINKSTATE (cfg_pcie_link_state ),
.CFGPMRCVASREQL1N (cfg_pm_rcv_as_req_l1_n ),
.CFGPMRCVREQACKN (cfg_pm_rcv_req_ack_n ),
.CFGPMRCVENTERL1N (cfg_pm_rcv_enter_l1_n ),
.CFGPMRCVENTERL23N (cfg_pm_rcv_enter_l23_n ),
.CFGPMCSRPOWERSTATE (cfg_pmcsr_powerstate ),
.CFGPMCSRPMEEN (cfg_pmcsr_pme_en ),
.CFGPMCSRPMESTATUS (cfg_pmcsr_pme_status ),
.CFGTRANSACTION (cfg_transaction ),
.CFGTRANSACTIONTYPE (cfg_transaction_type ),
.CFGTRANSACTIONADDR (cfg_transaction_addr ),
.CFGCOMMANDIOENABLE (cfg_command_io_enable ),
.CFGCOMMANDMEMENABLE (cfg_command_mem_enable ),
.CFGCOMMANDBUSMASTERENABLE (cfg_command_bus_master_enable ),
.CFGCOMMANDINTERRUPTDISABLE (cfg_command_interrupt_disable ),
.CFGCOMMANDSERREN (cfg_command_serr_en ),
.CFGBRIDGESERREN (cfg_bridge_serr_en ),
.CFGDEVSTATUSCORRERRDETECTED (cfg_dev_status_corr_err_detected ),
.CFGDEVSTATUSNONFATALERRDETECTED (cfg_dev_status_non_fatal_err_detected ),
.CFGDEVSTATUSFATALERRDETECTED (cfg_dev_status_fatal_err_detected ),
.CFGDEVSTATUSURDETECTED (cfg_dev_status_ur_detected ),
.CFGDEVCONTROLCORRERRREPORTINGEN (cfg_dev_control_corr_err_reporting_en ),
.CFGDEVCONTROLNONFATALREPORTINGEN (cfg_dev_control_non_fatal_reporting_en ),
.CFGDEVCONTROLFATALERRREPORTINGEN (cfg_dev_control_fatal_err_reporting_en ),
.CFGDEVCONTROLURERRREPORTINGEN (cfg_dev_control_ur_err_reporting_en ),
.CFGDEVCONTROLENABLERO (cfg_dev_control_enable_ro ),
.CFGDEVCONTROLMAXPAYLOAD (cfg_dev_control_max_payload ),
.CFGDEVCONTROLEXTTAGEN (cfg_dev_control_ext_tag_en ),
.CFGDEVCONTROLPHANTOMEN (cfg_dev_control_phantom_en ),
.CFGDEVCONTROLAUXPOWEREN (cfg_dev_control_aux_power_en ),
.CFGDEVCONTROLNOSNOOPEN (cfg_dev_control_no_snoop_en ),
.CFGDEVCONTROLMAXREADREQ (cfg_dev_control_max_read_req ),
.CFGLINKSTATUSCURRENTSPEED (cfg_link_status_current_speed ),
.CFGLINKSTATUSNEGOTIATEDWIDTH (cfg_link_status_negotiated_width ),
.CFGLINKSTATUSLINKTRAINING (cfg_link_status_link_training ),
.CFGLINKSTATUSDLLACTIVE (cfg_link_status_dll_active ),
.CFGLINKSTATUSBANDWIDTHSTATUS (cfg_link_status_bandwidth_status ),
.CFGLINKSTATUSAUTOBANDWIDTHSTATUS (cfg_link_status_auto_bandwidth_status ),
.CFGLINKCONTROLASPMCONTROL (cfg_link_control_aspm_control ),
.CFGLINKCONTROLRCB (cfg_link_control_rcb ),
.CFGLINKCONTROLLINKDISABLE (cfg_link_control_link_disable ),
.CFGLINKCONTROLRETRAINLINK (cfg_link_control_retrain_link ),
.CFGLINKCONTROLCOMMONCLOCK (cfg_link_control_common_clock ),
.CFGLINKCONTROLEXTENDEDSYNC (cfg_link_control_extended_sync ),
.CFGLINKCONTROLCLOCKPMEN (cfg_link_control_clock_pm_en ),
.CFGLINKCONTROLHWAUTOWIDTHDIS (cfg_link_control_hw_auto_width_dis ),
.CFGLINKCONTROLBANDWIDTHINTEN (cfg_link_control_bandwidth_int_en ),
.CFGLINKCONTROLAUTOBANDWIDTHINTEN (cfg_link_control_auto_bandwidth_int_en ),
.CFGDEVCONTROL2CPLTIMEOUTVAL (cfg_dev_control2_cpl_timeout_val ),
.CFGDEVCONTROL2CPLTIMEOUTDIS (cfg_dev_control2_cpl_timeout_dis ),
.CFGDEVCONTROL2ARIFORWARDEN (cfg_dev_control2_ari_forward_en ),
.CFGDEVCONTROL2ATOMICREQUESTEREN (cfg_dev_control2_atomic_requester_en ),
.CFGDEVCONTROL2ATOMICEGRESSBLOCK (cfg_dev_control2_atomic_egress_block ),
.CFGDEVCONTROL2IDOREQEN (cfg_dev_control2_ido_req_en ),
.CFGDEVCONTROL2IDOCPLEN (cfg_dev_control2_ido_cpl_en ),
.CFGDEVCONTROL2LTREN (cfg_dev_control2_ltr_en ),
.CFGDEVCONTROL2TLPPREFIXBLOCK (cfg_dev_control2_tlp_prefix_block ),
.CFGSLOTCONTROLELECTROMECHILCTLPULSE (cfg_slot_control_electromech_il_ctl_pulse ),
.CFGROOTCONTROLSYSERRCORRERREN (cfg_root_control_syserr_corr_err_en ),
.CFGROOTCONTROLSYSERRNONFATALERREN (cfg_root_control_syserr_non_fatal_err_en ),
.CFGROOTCONTROLSYSERRFATALERREN (cfg_root_control_syserr_fatal_err_en ),
.CFGROOTCONTROLPMEINTEN (cfg_root_control_pme_int_en ),
.CFGAERECRCCHECKEN (cfg_aer_ecrc_check_en ),
.CFGAERECRCGENEN (cfg_aer_ecrc_gen_en ),
.CFGAERROOTERRCORRERRREPORTINGEN (cfg_aer_rooterr_corr_err_reporting_en ),
.CFGAERROOTERRNONFATALERRREPORTINGEN (cfg_aer_rooterr_non_fatal_err_reporting_en ),
.CFGAERROOTERRFATALERRREPORTINGEN (cfg_aer_rooterr_fatal_err_reporting_en ),
.CFGAERROOTERRCORRERRRECEIVED (cfg_aer_rooterr_corr_err_received ),
.CFGAERROOTERRNONFATALERRRECEIVED (cfg_aer_rooterr_non_fatal_err_received ),
.CFGAERROOTERRFATALERRRECEIVED (cfg_aer_rooterr_fatal_err_received ),
.CFGVCTCVCMAP (cfg_vc_tcvc_map ),
.DRPRDY (drp_rdy ),
.DRPDO (drp_do ),
//.DRPWRITEEN (drp_write_en ),
//.DRPWRITEPORT0 (drp_write_port_0 ),
//.DRPWRITEPORT1 (drp_write_port_1 ),
//.DRPWRITEPORT2 (drp_write_port_2 ),
//.DRPWRITEPORT3 (drp_write_port_3 ),
//.DRPWRITEPORT4 (drp_write_port_4 ),
//.DRPWRITEPORT5 (drp_write_port_5 ),
//.DRPWRITEPORT6 (drp_write_port_6 ),
//.DRPWRITEPORT7 (drp_write_port_7 ),
//.DRPWRITEPORT8 (drp_write_port_8 ),
//.DRPWRITEPORT9 (drp_write_port_9 ),
//.DRPWRITEPORT10 (drp_write_port_10 ),
//.DRPWRITEPORT11 (drp_write_port_11 ),
//.DRPWRITEPORT12 (drp_write_port_12 ),
//.DRPREADADDR (drp_read_addr ),
.DBGVECA (dbg_vec_a ),
.DBGVECB (dbg_vec_b ),
.DBGVECC (dbg_vec_c ),
.DBGSCLRA (dbg_sclr_a ),
.DBGSCLRB (dbg_sclr_b ),
.DBGSCLRC (dbg_sclr_c ),
.DBGSCLRD (dbg_sclr_d ),
.DBGSCLRE (dbg_sclr_e ),
.DBGSCLRF (dbg_sclr_f ),
.DBGSCLRG (dbg_sclr_g ),
.DBGSCLRH (dbg_sclr_h ),
.DBGSCLRI (dbg_sclr_i ),
.DBGSCLRJ (dbg_sclr_j ),
.DBGSCLRK (dbg_sclr_k ),
.PLDBGVEC (pl_dbg_vec )
//.XILUNCONNOUT (xil_unconn_out )
);
endmodule
`endif // PCIE_2LM
|
/*
Copyright (c) 2014-2017 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1 ns / 1 ps
module fpga_core (
/*
* Clock: 125MHz
* Synchronous reset
*/
input wire clk,
input wire rst,
/*
* GPIO
*/
input wire btnu,
input wire btnl,
input wire btnd,
input wire btnr,
input wire btnc,
input wire [7:0] sw,
output wire [7:0] led,
/*
* UART: 9600 bps, 8N1
*/
input wire uart_rxd,
output wire uart_txd
);
reg [7:0] uart_tx_axis_tdata;
reg uart_tx_axis_tvalid;
wire uart_tx_axis_tready;
wire [7:0] uart_rx_axis_tdata;
wire uart_rx_axis_tvalid;
reg uart_rx_axis_tready;
uart
uart_inst (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(uart_tx_axis_tdata),
.s_axis_tvalid(uart_tx_axis_tvalid),
.s_axis_tready(uart_tx_axis_tready),
// AXI output
.m_axis_tdata(uart_rx_axis_tdata),
.m_axis_tvalid(uart_rx_axis_tvalid),
.m_axis_tready(uart_rx_axis_tready),
// uart
.rxd(uart_rxd),
.txd(uart_txd),
// status
.tx_busy(),
.rx_busy(),
.rx_overrun_error(),
.rx_frame_error(),
// configuration
.prescale(125000000/(9600*8))
);
//assign led = sw;
assign led = uart_tx_axis_tdata;
always @(posedge clk or posedge rst) begin
if (rst) begin
uart_tx_axis_tdata <= 0;
uart_tx_axis_tvalid <= 0;
uart_rx_axis_tready <= 0;
end else begin
if (uart_tx_axis_tvalid) begin
// attempting to transmit a byte
// so can't receive one at the moment
uart_rx_axis_tready <= 0;
// if it has been received, then clear the valid flag
if (uart_tx_axis_tready) begin
uart_tx_axis_tvalid <= 0;
end
end else begin
// ready to receive byte
uart_rx_axis_tready <= 1;
if (uart_rx_axis_tvalid) begin
// got one, so make sure it gets the correct ready signal
// (either clear it if it was set or set it if we just got a
// byte out of waiting for the transmitter to send one)
uart_rx_axis_tready <= ~uart_rx_axis_tready;
// send byte back out
uart_tx_axis_tdata <= uart_rx_axis_tdata;
uart_tx_axis_tvalid <= 1;
end
end
end
end
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2010 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.1
// \ \ Description : Xilinx Timing Simulation Library Component
// / / 3-State Output Buffer
// /___/ /\ Filename : OBUFT_DCIEN.v
// \ \ / \ Timestamp : Thu Apr 29 14:59:30 PDT 2010
// \___\/\___\
//
// Revision:
// 04/29/10 - Initial version.
// 12/20/10 - CR 587760 -- For backend support only, no corresponding unisim
// 09/20/11 - CR 625725 -- Removed attribute CAPACITANCE
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module OBUFT_DCIEN (O, DCITERMDISABLE, I, T);
parameter integer DRIVE = 12;
parameter IOSTANDARD = "DEFAULT";
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif // `ifdef XIL_TIMING
parameter SLEW = "SLOW";
output O;
input DCITERMDISABLE;
input I;
input T;
wire ts;
tri0 GTS = glbl.GTS;
or O1 (ts, GTS, T);
bufif0 T1 (O, I, ts);
`ifdef XIL_TIMING
specify
(DCITERMDISABLE => O) = (0:0:0, 0:0:0);
(I => O) = (0:0:0, 0:0:0);
(T => O) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif // `ifdef XIL_TIMING
endmodule
`endcelldefine
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: dram_ddr_rptr.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module dram_ddr_rptr( /*AUTOARG*/
// Outputs
io_dram_data_valid_buf, io_dram_ecc_in_buf, io_dram_data_in_buf,
dram_io_cas_l_buf, dram_io_channel_disabled_buf, dram_io_cke_buf,
dram_io_clk_enable_buf, dram_io_drive_data_buf,
dram_io_drive_enable_buf, dram_io_pad_clk_inv_buf,
dram_io_pad_enable_buf, dram_io_ras_l_buf, dram_io_write_en_l_buf,
dram_io_addr_buf, dram_io_bank_buf, dram_io_cs_l_buf,
dram_io_data_out_buf, dram_io_ptr_clk_inv_buf,
// Inputs
io_dram_data_valid, io_dram_ecc_in, io_dram_data_in,
dram_io_cas_l, dram_io_channel_disabled, dram_io_cke,
dram_io_clk_enable, dram_io_drive_data, dram_io_drive_enable,
dram_io_pad_clk_inv, dram_io_pad_enable, dram_io_ras_l,
dram_io_write_en_l, dram_io_addr, dram_io_bank, dram_io_cs_l,
dram_io_data_out, dram_io_ptr_clk_inv
);
/*OUTPUTS*/
output io_dram_data_valid_buf;
output [31:0] io_dram_ecc_in_buf;
output [255:0] io_dram_data_in_buf;
output dram_io_cas_l_buf;
output dram_io_channel_disabled_buf;
output dram_io_cke_buf;
output dram_io_clk_enable_buf;
output dram_io_drive_data_buf;
output dram_io_drive_enable_buf;
output dram_io_pad_clk_inv_buf;
output dram_io_pad_enable_buf;
output dram_io_ras_l_buf;
output dram_io_write_en_l_buf;
output [14:0] dram_io_addr_buf;
output [2:0] dram_io_bank_buf;
output [3:0] dram_io_cs_l_buf;
output [287:0] dram_io_data_out_buf;
output [4:0] dram_io_ptr_clk_inv_buf;
/*INPUTS*/
input io_dram_data_valid;
input [31:0] io_dram_ecc_in;
input [255:0] io_dram_data_in;
input dram_io_cas_l;
input dram_io_channel_disabled;
input dram_io_cke;
input dram_io_clk_enable;
input dram_io_drive_data;
input dram_io_drive_enable;
input dram_io_pad_clk_inv;
input dram_io_pad_enable;
input dram_io_ras_l;
input dram_io_write_en_l;
input [14:0] dram_io_addr;
input [2:0] dram_io_bank;
input [3:0] dram_io_cs_l;
input [287:0] dram_io_data_out;
input [4:0] dram_io_ptr_clk_inv;
/************************* CODE *********************************/
assign io_dram_data_in_buf = io_dram_data_in[255:0];
assign io_dram_data_valid_buf = io_dram_data_valid;
assign io_dram_ecc_in_buf = io_dram_ecc_in[31:0];
assign dram_io_addr_buf = dram_io_addr[14:0];
assign dram_io_bank_buf = dram_io_bank[2:0];
assign dram_io_cas_l_buf = dram_io_cas_l;
assign dram_io_channel_disabled_buf = dram_io_channel_disabled;
assign dram_io_cke_buf = dram_io_cke;
assign dram_io_clk_enable_buf = dram_io_clk_enable;
assign dram_io_cs_l_buf = dram_io_cs_l[3:0];
assign dram_io_data_out_buf = dram_io_data_out[287:0];
assign dram_io_drive_data_buf = dram_io_drive_data;
assign dram_io_drive_enable_buf = dram_io_drive_enable;
assign dram_io_pad_clk_inv_buf = dram_io_pad_clk_inv;
assign dram_io_pad_enable_buf = dram_io_pad_enable;
assign dram_io_ptr_clk_inv_buf = dram_io_ptr_clk_inv[4:0];
assign dram_io_ras_l_buf = dram_io_ras_l;
assign dram_io_write_en_l_buf = dram_io_write_en_l;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
parameter ONE = 1;
wire [17:10] bitout;
reg [7:0] allbits;
reg [15:0] onebit;
sub sub [7:0] (allbits, onebit, bitout);
integer x;
always @ (posedge clk) begin
//$write("%x\n", bitout);
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
allbits <= 8'hac;
onebit <= 16'hc01a;
end
if (cyc==2) begin
if (bitout !== 8'h07) $stop;
allbits <= 8'hca;
onebit <= 16'h1f01;
end
if (cyc==3) begin
if (bitout !== 8'h41) $stop;
if (sub[0].bitout !== 1'b1) $stop;
if (sub[1].bitout !== 1'b0) $stop;
`ifndef verilator // Hacky array subscripting
if (sub[ONE].bitout !== 1'b0) $stop;
`endif
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
`ifdef USE_INLINE
`define INLINE_MODULE /*verilator inline_module*/
`else
`define INLINE_MODULE /*verilator public_module*/
`endif
module sub (input [7:0] allbits, input [1:0] onebit, output bitout);
`INLINE_MODULE
wire bitout = (^ onebit) ^ (^ allbits);
endmodule
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
// Sign extension "macro"
// bits_out should be greater than bits_in
module sign_extend (in,out);
parameter bits_in=0; // FIXME Quartus insists on a default
parameter bits_out=0;
input [bits_in-1:0] in;
output [bits_out-1:0] out;
assign out = {{(bits_out-bits_in){in[bits_in-1]}},in};
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : ddr_mc_phy_wrapper.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Oct 10 2010
// \___\/\___\
//
//Device : 7 Series
//Design Name : DDR3 SDRAM
//Purpose : Wrapper file that encompasses the MC_PHY module
// instantiation and handles the vector remapping between
// the MC_PHY ports and the user's DDR3 ports. Vector
// remapping affects DDR3 control, address, and DQ/DQS/DM.
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1 ps / 1 ps
module mig_7series_v2_3_ddr_mc_phy_wrapper #
(
parameter TCQ = 100, // Register delay (simulation only)
parameter tCK = 2500, // ps
parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO"
parameter DATA_IO_PRIM_TYPE = "DEFAULT", // # = "HP_LP", "HR_LP", "DEFAULT"
parameter DATA_IO_IDLE_PWRDWN = "ON", // "ON" or "OFF"
parameter IODELAY_GRP = "IODELAY_MIG",
parameter FPGA_SPEED_GRADE = 1,
parameter nCK_PER_CLK = 4, // Memory:Logic clock ratio
parameter nCS_PER_RANK = 1, // # of unique CS outputs per rank
parameter BANK_WIDTH = 3, // # of bank address
parameter CKE_WIDTH = 1, // # of clock enable outputs
parameter CS_WIDTH = 1, // # of chip select
parameter CK_WIDTH = 1, // # of CK
parameter CWL = 5, // CAS Write latency
parameter DDR2_DQSN_ENABLE = "YES", // Enable differential DQS for DDR2
parameter DM_WIDTH = 8, // # of data mask
parameter DQ_WIDTH = 16, // # of data bits
parameter DQS_CNT_WIDTH = 3, // ceil(log2(DQS_WIDTH))
parameter DQS_WIDTH = 8, // # of strobe pairs
parameter DRAM_TYPE = "DDR3", // DRAM type (DDR2, DDR3)
parameter RANKS = 4, // # of ranks
parameter ODT_WIDTH = 1, // # of ODT outputs
parameter POC_USE_METASTABLE_SAMP = "FALSE",
parameter REG_CTRL = "OFF", // "ON" for registered DIMM
parameter ROW_WIDTH = 16, // # of row/column address
parameter USE_CS_PORT = 1, // Support chip select output
parameter USE_DM_PORT = 1, // Support data mask output
parameter USE_ODT_PORT = 1, // Support ODT output
parameter IBUF_LPWR_MODE = "OFF", // input buffer low power option
parameter LP_DDR_CK_WIDTH = 2,
// Hard PHY parameters
parameter PHYCTL_CMD_FIFO = "FALSE",
parameter DATA_CTL_B0 = 4'hc,
parameter DATA_CTL_B1 = 4'hf,
parameter DATA_CTL_B2 = 4'hf,
parameter DATA_CTL_B3 = 4'hf,
parameter DATA_CTL_B4 = 4'hf,
parameter BYTE_LANES_B0 = 4'b1111,
parameter BYTE_LANES_B1 = 4'b0000,
parameter BYTE_LANES_B2 = 4'b0000,
parameter BYTE_LANES_B3 = 4'b0000,
parameter BYTE_LANES_B4 = 4'b0000,
parameter PHY_0_BITLANES = 48'h0000_0000_0000,
parameter PHY_1_BITLANES = 48'h0000_0000_0000,
parameter PHY_2_BITLANES = 48'h0000_0000_0000,
// Parameters calculated outside of this block
parameter HIGHEST_BANK = 3, // Highest I/O bank index
parameter HIGHEST_LANE = 12, // Highest byte lane index
// ** Pin mapping parameters
// Parameters for mapping between hard PHY and physical DDR3 signals
// There are 2 classes of parameters:
// - DQS_BYTE_MAP, CK_BYTE_MAP, CKE_ODT_BYTE_MAP: These consist of
// 8-bit elements. Each element indicates the bank and byte lane
// location of that particular signal. The bit lane in this case
// doesn't need to be specified, either because there's only one
// pin pair in each byte lane that the DQS or CK pair can be
// located at, or in the case of CKE_ODT_BYTE_MAP, only the byte
// lane needs to be specified in order to determine which byte
// lane generates the RCLK (Note that CKE, and ODT must be located
// in the same bank, thus only one element in CKE_ODT_BYTE_MAP)
// [7:4] = bank # (0-4)
// [3:0] = byte lane # (0-3)
// - All other MAP parameters: These consist of 12-bit elements. Each
// element indicates the bank, byte lane, and bit lane location of
// that particular signal:
// [11:8] = bank # (0-4)
// [7:4] = byte lane # (0-3)
// [3:0] = bit lane # (0-11)
// Note that not all elements in all parameters will be used - it
// depends on the actual widths of the DDR3 buses. The parameters are
// structured to support a maximum of:
// - DQS groups: 18
// - data mask bits: 18
// In addition, the default parameter size of some of the parameters will
// support a certain number of bits, however, this can be expanded at
// compile time by expanding the width of the vector passed into this
// parameter
// - chip selects: 10
// - bank bits: 3
// - address bits: 16
parameter CK_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,
parameter ADDR_MAP
= 192'h000_000_000_000_000_000_000_000_000_000_000_000_000_000_000_000,
parameter BANK_MAP = 36'h000_000_000,
parameter CAS_MAP = 12'h000,
parameter CKE_ODT_BYTE_MAP = 8'h00,
parameter CKE_MAP = 96'h000_000_000_000_000_000_000_000,
parameter ODT_MAP = 96'h000_000_000_000_000_000_000_000,
parameter CKE_ODT_AUX = "FALSE",
parameter CS_MAP = 120'h000_000_000_000_000_000_000_000_000_000,
parameter PARITY_MAP = 12'h000,
parameter RAS_MAP = 12'h000,
parameter WE_MAP = 12'h000,
parameter DQS_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,
// DATAx_MAP parameter is used for byte lane X in the design
parameter DATA0_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA1_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA2_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA3_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA4_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA5_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA6_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA7_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA8_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA9_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA10_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA11_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA12_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA13_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA14_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA15_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA16_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA17_MAP = 96'h000_000_000_000_000_000_000_000,
// MASK0_MAP used for bytes [8:0], MASK1_MAP for bytes [17:9]
parameter MASK0_MAP = 108'h000_000_000_000_000_000_000_000_000,
parameter MASK1_MAP = 108'h000_000_000_000_000_000_000_000_000,
// Simulation options
parameter SIM_CAL_OPTION = "NONE",
// The PHY_CONTROL primitive in the bank where PLL exists is declared
// as the Master PHY_CONTROL.
parameter MASTER_PHY_CTL = 1,
parameter DRAM_WIDTH = 8
)
(
input rst,
input iddr_rst,
input clk,
input freq_refclk,
input mem_refclk,
input pll_lock,
input sync_pulse,
input mmcm_ps_clk,
input idelayctrl_refclk,
input phy_cmd_wr_en,
input phy_data_wr_en,
input [31:0] phy_ctl_wd,
input phy_ctl_wr,
input phy_if_empty_def,
input phy_if_reset,
input [5:0] data_offset_1,
input [5:0] data_offset_2,
input [3:0] aux_in_1,
input [3:0] aux_in_2,
output [4:0] idelaye2_init_val,
output [5:0] oclkdelay_init_val,
output if_empty,
output phy_ctl_full,
output phy_cmd_full,
output phy_data_full,
output phy_pre_data_a_full,
output [(CK_WIDTH * LP_DDR_CK_WIDTH)-1:0] ddr_clk,
output phy_mc_go,
input phy_write_calib,
input phy_read_calib,
input calib_in_common,
input [5:0] calib_sel,
input [DQS_CNT_WIDTH:0] byte_sel_cnt,
input [DRAM_WIDTH-1:0] fine_delay_incdec_pb,
input fine_delay_sel,
input [HIGHEST_BANK-1:0] calib_zero_inputs,
input [HIGHEST_BANK-1:0] calib_zero_ctrl,
input [2:0] po_fine_enable,
input [2:0] po_coarse_enable,
input [2:0] po_fine_inc,
input [2:0] po_coarse_inc,
input po_counter_load_en,
input po_counter_read_en,
input [2:0] po_sel_fine_oclk_delay,
input [8:0] po_counter_load_val,
output [8:0] po_counter_read_val,
output [5:0] pi_counter_read_val,
input [HIGHEST_BANK-1:0] pi_rst_dqs_find,
input pi_fine_enable,
input pi_fine_inc,
input pi_counter_load_en,
input [5:0] pi_counter_load_val,
input idelay_ce,
input idelay_inc,
input idelay_ld,
input idle,
output pi_phase_locked,
output pi_phase_locked_all,
output pi_dqs_found,
output pi_dqs_found_all,
output pi_dqs_out_of_range,
// From/to calibration logic/soft PHY
input phy_init_data_sel,
input [nCK_PER_CLK*ROW_WIDTH-1:0] mux_address,
input [nCK_PER_CLK*BANK_WIDTH-1:0] mux_bank,
input [nCK_PER_CLK-1:0] mux_cas_n,
input [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mux_cs_n,
input [nCK_PER_CLK-1:0] mux_ras_n,
input [1:0] mux_odt,
input [nCK_PER_CLK-1:0] mux_cke,
input [nCK_PER_CLK-1:0] mux_we_n,
input [nCK_PER_CLK-1:0] parity_in,
input [2*nCK_PER_CLK*DQ_WIDTH-1:0] mux_wrdata,
input [2*nCK_PER_CLK*(DQ_WIDTH/8)-1:0] mux_wrdata_mask,
input mux_reset_n,
output [2*nCK_PER_CLK*DQ_WIDTH-1:0] rd_data,
// Memory I/F
output [ROW_WIDTH-1:0] ddr_addr,
output [BANK_WIDTH-1:0] ddr_ba,
output ddr_cas_n,
output [CKE_WIDTH-1:0] ddr_cke,
output [CS_WIDTH*nCS_PER_RANK-1:0] ddr_cs_n,
output [DM_WIDTH-1:0] ddr_dm,
output [ODT_WIDTH-1:0] ddr_odt,
output ddr_parity,
output ddr_ras_n,
output ddr_we_n,
output ddr_reset_n,
inout [DQ_WIDTH-1:0] ddr_dq,
inout [DQS_WIDTH-1:0] ddr_dqs,
inout [DQS_WIDTH-1:0] ddr_dqs_n,
//output iodelay_ctrl_rdy,
output pd_out
,input dbg_pi_counter_read_en
,output ref_dll_lock
,input rst_phaser_ref
,output [11:0] dbg_pi_phase_locked_phy4lanes
,output [11:0] dbg_pi_dqs_found_lanes_phy4lanes
);
function [71:0] generate_bytelanes_ddr_ck;
input [143:0] ck_byte_map;
integer v ;
begin
generate_bytelanes_ddr_ck = 'b0 ;
for (v = 0; v < CK_WIDTH; v = v + 1) begin
if ((CK_BYTE_MAP[((v*8)+4)+:4]) == 2)
generate_bytelanes_ddr_ck[48+(4*v)+1*(CK_BYTE_MAP[(v*8)+:4])] = 1'b1;
else if ((CK_BYTE_MAP[((v*8)+4)+:4]) == 1)
generate_bytelanes_ddr_ck[24+(4*v)+1*(CK_BYTE_MAP[(v*8)+:4])] = 1'b1;
else
generate_bytelanes_ddr_ck[4*v+1*(CK_BYTE_MAP[(v*8)+:4])] = 1'b1;
end
end
endfunction
function [(2*CK_WIDTH*8)-1:0] generate_ddr_ck_map;
input [143:0] ck_byte_map;
integer g;
begin
generate_ddr_ck_map = 'b0 ;
for(g = 0 ; g < CK_WIDTH ; g= g + 1) begin
generate_ddr_ck_map[(g*2*8)+:8] = (ck_byte_map[(g*8)+:4] == 4'd0) ? "A" :
(ck_byte_map[(g*8)+:4] == 4'd1) ? "B" :
(ck_byte_map[(g*8)+:4] == 4'd2) ? "C" : "D" ;
generate_ddr_ck_map[(((g*2)+1)*8)+:8] = (ck_byte_map[((g*8)+4)+:4] == 4'd0) ? "0" :
(ck_byte_map[((g*8)+4)+:4] == 4'd1) ? "1" : "2" ; //each STRING charater takes 0 location
end
end
endfunction
// Enable low power mode for input buffer
localparam IBUF_LOW_PWR
= (IBUF_LPWR_MODE == "OFF") ? "FALSE" :
((IBUF_LPWR_MODE == "ON") ? "TRUE" : "ILLEGAL");
// Ratio of data to strobe
localparam DQ_PER_DQS = DQ_WIDTH / DQS_WIDTH;
// number of data phases per internal clock
localparam PHASE_PER_CLK = 2*nCK_PER_CLK;
// used to determine routing to OUT_FIFO for control/address for 2:1
// vs. 4:1 memory:internal clock ratio modes
localparam PHASE_DIV = 4 / nCK_PER_CLK;
localparam CLK_PERIOD = tCK * nCK_PER_CLK;
// Create an aggregate parameters for data mapping to reduce # of generate
// statements required in remapping code. Need to account for the case
// when the DQ:DQS ratio is not 8:1 - in this case, each DATAx_MAP
// parameter will have fewer than 8 elements used
localparam FULL_DATA_MAP = {DATA17_MAP[12*DQ_PER_DQS-1:0],
DATA16_MAP[12*DQ_PER_DQS-1:0],
DATA15_MAP[12*DQ_PER_DQS-1:0],
DATA14_MAP[12*DQ_PER_DQS-1:0],
DATA13_MAP[12*DQ_PER_DQS-1:0],
DATA12_MAP[12*DQ_PER_DQS-1:0],
DATA11_MAP[12*DQ_PER_DQS-1:0],
DATA10_MAP[12*DQ_PER_DQS-1:0],
DATA9_MAP[12*DQ_PER_DQS-1:0],
DATA8_MAP[12*DQ_PER_DQS-1:0],
DATA7_MAP[12*DQ_PER_DQS-1:0],
DATA6_MAP[12*DQ_PER_DQS-1:0],
DATA5_MAP[12*DQ_PER_DQS-1:0],
DATA4_MAP[12*DQ_PER_DQS-1:0],
DATA3_MAP[12*DQ_PER_DQS-1:0],
DATA2_MAP[12*DQ_PER_DQS-1:0],
DATA1_MAP[12*DQ_PER_DQS-1:0],
DATA0_MAP[12*DQ_PER_DQS-1:0]};
// Same deal, but for data mask mapping
localparam FULL_MASK_MAP = {MASK1_MAP, MASK0_MAP};
localparam TMP_BYTELANES_DDR_CK = generate_bytelanes_ddr_ck(CK_BYTE_MAP) ;
localparam TMP_GENERATE_DDR_CK_MAP = generate_ddr_ck_map(CK_BYTE_MAP) ;
// Temporary parameters to determine which bank is outputting the CK/CK#
// Eventually there will be support for multiple CK/CK# output
//localparam TMP_DDR_CLK_SELECT_BANK = (CK_BYTE_MAP[7:4]);
//// Temporary method to force MC_PHY to generate ODDR associated with
//// CK/CK# output only for a single byte lane in the design. All banks
//// that won't be generating the CK/CK# will have "UNUSED" as their
//// PHY_GENERATE_DDR_CK parameter
//localparam TMP_PHY_0_GENERATE_DDR_CK
// = (TMP_DDR_CLK_SELECT_BANK != 0) ? "UNUSED" :
// ((CK_BYTE_MAP[1:0] == 2'b00) ? "A" :
// ((CK_BYTE_MAP[1:0] == 2'b01) ? "B" :
// ((CK_BYTE_MAP[1:0] == 2'b10) ? "C" : "D")));
//localparam TMP_PHY_1_GENERATE_DDR_CK
// = (TMP_DDR_CLK_SELECT_BANK != 1) ? "UNUSED" :
// ((CK_BYTE_MAP[1:0] == 2'b00) ? "A" :
// ((CK_BYTE_MAP[1:0] == 2'b01) ? "B" :
// ((CK_BYTE_MAP[1:0] == 2'b10) ? "C" : "D")));
//localparam TMP_PHY_2_GENERATE_DDR_CK
// = (TMP_DDR_CLK_SELECT_BANK != 2) ? "UNUSED" :
// ((CK_BYTE_MAP[1:0] == 2'b00) ? "A" :
// ((CK_BYTE_MAP[1:0] == 2'b01) ? "B" :
// ((CK_BYTE_MAP[1:0] == 2'b10) ? "C" : "D")));
// Function to generate MC_PHY parameters PHY_BITLANES_OUTONLYx
// which indicates which bit lanes in data byte lanes are
// output-only bitlanes (e.g. used specifically for data mask outputs)
function [143:0] calc_phy_bitlanes_outonly;
input [215:0] data_mask_in;
integer z;
begin
calc_phy_bitlanes_outonly = 'b0;
// Only enable BITLANES parameters for data masks if, well, if
// the data masks are actually enabled
if (USE_DM_PORT == 1)
for (z = 0; z < DM_WIDTH; z = z + 1)
calc_phy_bitlanes_outonly[48*data_mask_in[(12*z+8)+:3] +
12*data_mask_in[(12*z+4)+:2] +
data_mask_in[12*z+:4]] = 1'b1;
end
endfunction
localparam PHY_BITLANES_OUTONLY = calc_phy_bitlanes_outonly(FULL_MASK_MAP);
localparam PHY_0_BITLANES_OUTONLY = PHY_BITLANES_OUTONLY[47:0];
localparam PHY_1_BITLANES_OUTONLY = PHY_BITLANES_OUTONLY[95:48];
localparam PHY_2_BITLANES_OUTONLY = PHY_BITLANES_OUTONLY[143:96];
// Determine which bank and byte lane generates the RCLK used to clock
// out the auxilliary (ODT, CKE) outputs
localparam CKE_ODT_RCLK_SELECT_BANK_AUX_ON
= (CKE_ODT_BYTE_MAP[7:4] == 4'h0) ? 0 :
((CKE_ODT_BYTE_MAP[7:4] == 4'h1) ? 1 :
((CKE_ODT_BYTE_MAP[7:4] == 4'h2) ? 2 :
((CKE_ODT_BYTE_MAP[7:4] == 4'h3) ? 3 :
((CKE_ODT_BYTE_MAP[7:4] == 4'h4) ? 4 : -1))));
localparam CKE_ODT_RCLK_SELECT_LANE_AUX_ON
= (CKE_ODT_BYTE_MAP[3:0] == 4'h0) ? "A" :
((CKE_ODT_BYTE_MAP[3:0] == 4'h1) ? "B" :
((CKE_ODT_BYTE_MAP[3:0] == 4'h2) ? "C" :
((CKE_ODT_BYTE_MAP[3:0] == 4'h3) ? "D" : "ILLEGAL")));
localparam CKE_ODT_RCLK_SELECT_BANK_AUX_OFF
= (CKE_MAP[11:8] == 4'h0) ? 0 :
((CKE_MAP[11:8] == 4'h1) ? 1 :
((CKE_MAP[11:8] == 4'h2) ? 2 :
((CKE_MAP[11:8] == 4'h3) ? 3 :
((CKE_MAP[11:8] == 4'h4) ? 4 : -1))));
localparam CKE_ODT_RCLK_SELECT_LANE_AUX_OFF
= (CKE_MAP[7:4] == 4'h0) ? "A" :
((CKE_MAP[7:4] == 4'h1) ? "B" :
((CKE_MAP[7:4] == 4'h2) ? "C" :
((CKE_MAP[7:4] == 4'h3) ? "D" : "ILLEGAL")));
localparam CKE_ODT_RCLK_SELECT_BANK = (CKE_ODT_AUX == "TRUE") ? CKE_ODT_RCLK_SELECT_BANK_AUX_ON : CKE_ODT_RCLK_SELECT_BANK_AUX_OFF ;
localparam CKE_ODT_RCLK_SELECT_LANE = (CKE_ODT_AUX == "TRUE") ? CKE_ODT_RCLK_SELECT_LANE_AUX_ON : CKE_ODT_RCLK_SELECT_LANE_AUX_OFF ;
//***************************************************************************
// OCLKDELAYED tap setting calculation:
// Parameters for calculating amount of phase shifting output clock to
// achieve 90 degree offset between DQS and DQ on writes
//***************************************************************************
//90 deg equivalent to 0.25 for MEM_RefClk <= 300 MHz
// and 1.25 for Mem_RefClk > 300 MHz
localparam PO_OCLKDELAY_INV = (((SIM_CAL_OPTION == "NONE") && (tCK > 2500)) || (tCK >= 3333)) ? "FALSE" : "TRUE";
//DIV1: MemRefClk >= 400 MHz, DIV2: 200 <= MemRefClk < 400,
//DIV4: MemRefClk < 200 MHz
localparam PHY_0_A_PI_FREQ_REF_DIV = tCK > 5000 ? "DIV4" :
tCK > 2500 ? "DIV2": "NONE";
localparam FREQ_REF_DIV = (PHY_0_A_PI_FREQ_REF_DIV == "DIV4" ? 4 :
PHY_0_A_PI_FREQ_REF_DIV == "DIV2" ? 2 : 1);
// Intrinsic delay between OCLK and OCLK_DELAYED Phaser Output
localparam real INT_DELAY = 0.4392/FREQ_REF_DIV + 100.0/tCK;
// Whether OCLK_DELAY output comes inverted or not
localparam real HALF_CYCLE_DELAY = 0.5*(PO_OCLKDELAY_INV == "TRUE" ? 1 : 0);
// Phaser-Out Stage3 Tap delay for 90 deg shift.
// Maximum tap delay is FreqRefClk period distributed over 64 taps
// localparam real TAP_DELAY = MC_OCLK_DELAY/64/FREQ_REF_DIV;
localparam real MC_OCLK_DELAY = ((PO_OCLKDELAY_INV == "TRUE" ? 1.25 : 0.25) -
(INT_DELAY + HALF_CYCLE_DELAY))
* 63 * FREQ_REF_DIV;
//localparam integer PHY_0_A_PO_OCLK_DELAY = MC_OCLK_DELAY;
localparam integer PHY_0_A_PO_OCLK_DELAY_HW
= (tCK > 2273) ? 34 :
(tCK > 2000) ? 33 :
(tCK > 1724) ? 32 :
(tCK > 1515) ? 31 :
(tCK > 1315) ? 30 :
(tCK > 1136) ? 29 :
(tCK > 1021) ? 28 : 27;
// Note that simulation requires a different value than in H/W because of the
// difference in the way delays are modeled
localparam integer PHY_0_A_PO_OCLK_DELAY = (SIM_CAL_OPTION == "NONE") ?
((tCK > 2500) ? 8 :
(DRAM_TYPE == "DDR3") ? PHY_0_A_PO_OCLK_DELAY_HW : 30) :
MC_OCLK_DELAY;
// Initial DQ IDELAY value
localparam PHY_0_A_IDELAYE2_IDELAY_VALUE = (SIM_CAL_OPTION != "FAST_CAL") ? 0 :
(tCK < 1000) ? 0 :
(tCK < 1330) ? 0 :
(tCK < 2300) ? 0 :
(tCK < 2500) ? 2 : 0;
//localparam PHY_0_A_IDELAYE2_IDELAY_VALUE = 0;
// Aux_out parameters RD_CMD_OFFSET = CL+2? and WR_CMD_OFFSET = CWL+3?
localparam PHY_0_RD_CMD_OFFSET_0 = 10;
localparam PHY_0_RD_CMD_OFFSET_1 = 10;
localparam PHY_0_RD_CMD_OFFSET_2 = 10;
localparam PHY_0_RD_CMD_OFFSET_3 = 10;
// 4:1 and 2:1 have WR_CMD_OFFSET values for ODT timing
localparam PHY_0_WR_CMD_OFFSET_0 = (nCK_PER_CLK == 4) ? 8 : 4;
localparam PHY_0_WR_CMD_OFFSET_1 = (nCK_PER_CLK == 4) ? 8 : 4;
localparam PHY_0_WR_CMD_OFFSET_2 = (nCK_PER_CLK == 4) ? 8 : 4;
localparam PHY_0_WR_CMD_OFFSET_3 = (nCK_PER_CLK == 4) ? 8 : 4;
// 4:1 and 2:1 have different values
localparam PHY_0_WR_DURATION_0 = 7;
localparam PHY_0_WR_DURATION_1 = 7;
localparam PHY_0_WR_DURATION_2 = 7;
localparam PHY_0_WR_DURATION_3 = 7;
// Aux_out parameters for toggle mode (CKE)
localparam CWL_M = (REG_CTRL == "ON") ? CWL + 1 : CWL;
localparam PHY_0_CMD_OFFSET = (nCK_PER_CLK == 4) ? (CWL_M % 2) ? 8 : 9 :
(CWL < 7) ?
4 + ((CWL_M % 2) ? 0 : 1) :
5 + ((CWL_M % 2) ? 0 : 1);
// temporary parameter to enable/disable PHY PC counters. In both 4:1 and
// 2:1 cases, this should be disabled. For now, enable for 4:1 mode to
// avoid making too many changes at once.
localparam PHY_COUNT_EN = (nCK_PER_CLK == 4) ? "TRUE" : "FALSE";
wire [((HIGHEST_LANE+3)/4)*4-1:0] aux_out;
wire [HIGHEST_LANE-1:0] mem_dqs_in;
wire [HIGHEST_LANE-1:0] mem_dqs_out;
wire [HIGHEST_LANE-1:0] mem_dqs_ts;
wire [HIGHEST_LANE*10-1:0] mem_dq_in;
wire [HIGHEST_LANE*12-1:0] mem_dq_out;
wire [HIGHEST_LANE*12-1:0] mem_dq_ts;
wire [DQ_WIDTH-1:0] in_dq;
wire [DQS_WIDTH-1:0] in_dqs;
wire [ROW_WIDTH-1:0] out_addr;
wire [BANK_WIDTH-1:0] out_ba;
wire out_cas_n;
wire [CS_WIDTH*nCS_PER_RANK-1:0] out_cs_n;
wire [DM_WIDTH-1:0] out_dm;
wire [ODT_WIDTH -1:0] out_odt;
wire [CKE_WIDTH -1 :0] out_cke ;
wire [DQ_WIDTH-1:0] out_dq;
wire [DQS_WIDTH-1:0] out_dqs;
wire out_parity;
wire out_ras_n;
wire out_we_n;
wire [HIGHEST_LANE*80-1:0] phy_din;
wire [HIGHEST_LANE*80-1:0] phy_dout;
wire phy_rd_en;
wire [DM_WIDTH-1:0] ts_dm;
wire [DQ_WIDTH-1:0] ts_dq;
wire [DQS_WIDTH-1:0] ts_dqs;
wire [DQS_WIDTH-1:0] in_dqs_lpbk_to_iddr;
wire [DQS_WIDTH-1:0] pd_out_pre;
//wire metaQ;
reg [31:0] phy_ctl_wd_i1;
reg [31:0] phy_ctl_wd_i2;
reg phy_ctl_wr_i1;
reg phy_ctl_wr_i2;
reg [5:0] data_offset_1_i1;
reg [5:0] data_offset_1_i2;
reg [5:0] data_offset_2_i1;
reg [5:0] data_offset_2_i2;
wire [31:0] phy_ctl_wd_temp;
wire phy_ctl_wr_temp;
wire [5:0] data_offset_1_temp;
wire [5:0] data_offset_2_temp;
wire [5:0] data_offset_1_of;
wire [5:0] data_offset_2_of;
wire [31:0] phy_ctl_wd_of;
wire phy_ctl_wr_of /* synthesis syn_maxfan = 1 */;
wire [3:0] phy_ctl_full_temp;
wire data_io_idle_pwrdwn;
reg [29:0] fine_delay_mod; //3 bit per DQ
reg fine_delay_sel_r; //timing adj with fine_delay_incdec_pb
(* use_dsp48 = "no" *) wire [DQS_CNT_WIDTH:0] byte_sel_cnt_w1;
// Always read from input data FIFOs when not empty
assign phy_rd_en = !if_empty;
// IDELAYE2 initial value
assign idelaye2_init_val = PHY_0_A_IDELAYE2_IDELAY_VALUE;
assign oclkdelay_init_val = PHY_0_A_PO_OCLK_DELAY;
// Idle powerdown when there are no pending reads in the MC
assign data_io_idle_pwrdwn = DATA_IO_IDLE_PWRDWN == "ON" ? idle : 1'b0;
//***************************************************************************
// Auxiliary output steering
//***************************************************************************
// For a 4 rank I/F the aux_out[3:0] from the addr/ctl bank will be
// mapped to ddr_odt and the aux_out[7:4] from one of the data banks
// will map to ddr_cke. For I/Fs less than 4 the aux_out[3:0] from the
// addr/ctl bank would bank would map to both ddr_odt and ddr_cke.
generate
if(CKE_ODT_AUX == "TRUE")begin:cke_thru_auxpins
if (CKE_WIDTH == 1) begin : gen_cke
// Explicitly instantiate OBUF to ensure that these are present
// in the netlist. Typically this is not required since NGDBUILD
// at the top-level knows to infer an I/O/IOBUF and therefore a
// top-level LOC constraint can be attached to that pin. This does
// not work when a hierarchical flow is used and the LOC is applied
// at the individual core-level UCF
OBUF u_cke_obuf
(
.I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK]),
.O (ddr_cke)
);
end else begin: gen_2rank_cke
OBUF u_cke0_obuf
(
.I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK]),
.O (ddr_cke[0])
);
OBUF u_cke1_obuf
(
.I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+2]),
.O (ddr_cke[1])
);
end
end
endgenerate
generate
if(CKE_ODT_AUX == "TRUE")begin:odt_thru_auxpins
if (USE_ODT_PORT == 1) begin : gen_use_odt
// Explicitly instantiate OBUF to ensure that these are present
// in the netlist. Typically this is not required since NGDBUILD
// at the top-level knows to infer an I/O/IOBUF and therefore a
// top-level LOC constraint can be attached to that pin. This does
// not work when a hierarchical flow is used and the LOC is applied
// at the individual core-level UCF
OBUF u_odt_obuf
(
.I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+1]),
.O (ddr_odt[0])
);
if (ODT_WIDTH == 2 && RANKS == 1) begin: gen_2port_odt
OBUF u_odt1_obuf
(
.I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+2]),
.O (ddr_odt[1])
);
end else if (ODT_WIDTH == 2 && RANKS == 2) begin: gen_2rank_odt
OBUF u_odt1_obuf
(
.I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+3]),
.O (ddr_odt[1])
);
end else if (ODT_WIDTH == 3 && RANKS == 1) begin: gen_3port_odt
OBUF u_odt1_obuf
(
.I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+2]),
.O (ddr_odt[1])
);
OBUF u_odt2_obuf
(
.I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+3]),
.O (ddr_odt[2])
);
end
end else begin
assign ddr_odt = 'b0;
end
end
endgenerate
//***************************************************************************
// Read data bit steering
//***************************************************************************
// Transpose elements of rd_data_map to form final read data output:
// phy_din elements are grouped according to "physical bit" - e.g.
// for nCK_PER_CLK = 4, there are 8 data phases transfered per physical
// bit per clock cycle:
// = {dq0_fall3, dq0_rise3, dq0_fall2, dq0_rise2,
// dq0_fall1, dq0_rise1, dq0_fall0, dq0_rise0}
// whereas rd_data is are grouped according to "phase" - e.g.
// = {dq7_rise0, dq6_rise0, dq5_rise0, dq4_rise0,
// dq3_rise0, dq2_rise0, dq1_rise0, dq0_rise0}
// therefore rd_data is formed by transposing phy_din - e.g.
// for nCK_PER_CLK = 4, and DQ_WIDTH = 16, and assuming MC_PHY
// bit_lane[0] maps to DQ[0], and bit_lane[1] maps to DQ[1], then
// the assignments for bits of rd_data corresponding to DQ[1:0]
// would be:
// {rd_data[112], rd_data[96], rd_data[80], rd_data[64],
// rd_data[48], rd_data[32], rd_data[16], rd_data[0]} = phy_din[7:0]
// {rd_data[113], rd_data[97], rd_data[81], rd_data[65],
// rd_data[49], rd_data[33], rd_data[17], rd_data[1]} = phy_din[15:8]
generate
genvar i, j;
for (i = 0; i < DQ_WIDTH; i = i + 1) begin: gen_loop_rd_data_1
for (j = 0; j < PHASE_PER_CLK; j = j + 1) begin: gen_loop_rd_data_2
assign rd_data[DQ_WIDTH*j + i]
= phy_din[(320*FULL_DATA_MAP[(12*i+8)+:3]+
80*FULL_DATA_MAP[(12*i+4)+:2] +
8*FULL_DATA_MAP[12*i+:4]) + j];
end
end
endgenerate
//generage idelay_inc per bits
reg [11:0] cal_tmp;
reg [95:0] byte_sel_data_map;
assign byte_sel_cnt_w1 = byte_sel_cnt;
always @ (posedge clk) begin
byte_sel_data_map <= #TCQ FULL_DATA_MAP[12*DQ_PER_DQS*byte_sel_cnt_w1+:96];
end
always @ (posedge clk) begin
fine_delay_mod[((byte_sel_data_map[3:0])*3)+:3] <= #TCQ {fine_delay_incdec_pb[0],2'b00};
fine_delay_mod[((byte_sel_data_map[12+3:12])*3)+:3] <= #TCQ {fine_delay_incdec_pb[1],2'b00};
fine_delay_mod[((byte_sel_data_map[24+3:24])*3)+:3] <= #TCQ {fine_delay_incdec_pb[2],2'b00};
fine_delay_mod[((byte_sel_data_map[36+3:36])*3)+:3] <= #TCQ {fine_delay_incdec_pb[3],2'b00};
fine_delay_mod[((byte_sel_data_map[48+3:48])*3)+:3] <= #TCQ {fine_delay_incdec_pb[4],2'b00};
fine_delay_mod[((byte_sel_data_map[60+3:60])*3)+:3] <= #TCQ {fine_delay_incdec_pb[5],2'b00};
fine_delay_mod[((byte_sel_data_map[72+3:72])*3)+:3] <= #TCQ {fine_delay_incdec_pb[6],2'b00};
fine_delay_mod[((byte_sel_data_map[84+3:84])*3)+:3] <= #TCQ {fine_delay_incdec_pb[7],2'b00};
fine_delay_sel_r <= #TCQ fine_delay_sel;
end
//***************************************************************************
// Control/address
//***************************************************************************
assign out_cas_n
= mem_dq_out[48*CAS_MAP[10:8] + 12*CAS_MAP[5:4] + CAS_MAP[3:0]];
generate
// if signal placed on bit lanes [0-9]
if (CAS_MAP[3:0] < 4'hA) begin: gen_cas_lt10
// Determine routing based on clock ratio mode. If running in 4:1
// mode, then all four bits from logic are used. If 2:1 mode, only
// 2-bits are provided by logic, and each bit is repeated 2x to form
// 4-bit input to IN_FIFO, e.g.
// 4:1 mode: phy_dout[] = {in[3], in[2], in[1], in[0]}
// 2:1 mode: phy_dout[] = {in[1], in[1], in[0], in[0]}
assign phy_dout[(320*CAS_MAP[10:8] + 80*CAS_MAP[5:4] +
8*CAS_MAP[3:0])+:4]
= {mux_cas_n[3/PHASE_DIV], mux_cas_n[2/PHASE_DIV],
mux_cas_n[1/PHASE_DIV], mux_cas_n[0]};
end else begin: gen_cas_ge10
// If signal is placed in bit lane [10] or [11], route to upper
// nibble of phy_dout lane [5] or [6] respectively (in this case
// phy_dout lane [5, 6] are multiplexed to take input for two
// different SDR signals - this is how bits[10,11] need to be
// provided to the OUT_FIFO
assign phy_dout[(320*CAS_MAP[10:8] + 80*CAS_MAP[5:4] +
8*(CAS_MAP[3:0]-5) + 4)+:4]
= {mux_cas_n[3/PHASE_DIV], mux_cas_n[2/PHASE_DIV],
mux_cas_n[1/PHASE_DIV], mux_cas_n[0]};
end
endgenerate
assign out_ras_n
= mem_dq_out[48*RAS_MAP[10:8] + 12*RAS_MAP[5:4] + RAS_MAP[3:0]];
generate
if (RAS_MAP[3:0] < 4'hA) begin: gen_ras_lt10
assign phy_dout[(320*RAS_MAP[10:8] + 80*RAS_MAP[5:4] +
8*RAS_MAP[3:0])+:4]
= {mux_ras_n[3/PHASE_DIV], mux_ras_n[2/PHASE_DIV],
mux_ras_n[1/PHASE_DIV], mux_ras_n[0]};
end else begin: gen_ras_ge10
assign phy_dout[(320*RAS_MAP[10:8] + 80*RAS_MAP[5:4] +
8*(RAS_MAP[3:0]-5) + 4)+:4]
= {mux_ras_n[3/PHASE_DIV], mux_ras_n[2/PHASE_DIV],
mux_ras_n[1/PHASE_DIV], mux_ras_n[0]};
end
endgenerate
assign out_we_n
= mem_dq_out[48*WE_MAP[10:8] + 12*WE_MAP[5:4] + WE_MAP[3:0]];
generate
if (WE_MAP[3:0] < 4'hA) begin: gen_we_lt10
assign phy_dout[(320*WE_MAP[10:8] + 80*WE_MAP[5:4] +
8*WE_MAP[3:0])+:4]
= {mux_we_n[3/PHASE_DIV], mux_we_n[2/PHASE_DIV],
mux_we_n[1/PHASE_DIV], mux_we_n[0]};
end else begin: gen_we_ge10
assign phy_dout[(320*WE_MAP[10:8] + 80*WE_MAP[5:4] +
8*(WE_MAP[3:0]-5) + 4)+:4]
= {mux_we_n[3/PHASE_DIV], mux_we_n[2/PHASE_DIV],
mux_we_n[1/PHASE_DIV], mux_we_n[0]};
end
endgenerate
generate
if (REG_CTRL == "ON") begin: gen_parity_out
// Generate addr/ctrl parity output only for DDR3 and DDR2 registered DIMMs
assign out_parity
= mem_dq_out[48*PARITY_MAP[10:8] + 12*PARITY_MAP[5:4] +
PARITY_MAP[3:0]];
if (PARITY_MAP[3:0] < 4'hA) begin: gen_lt10
assign phy_dout[(320*PARITY_MAP[10:8] + 80*PARITY_MAP[5:4] +
8*PARITY_MAP[3:0])+:4]
= {parity_in[3/PHASE_DIV], parity_in[2/PHASE_DIV],
parity_in[1/PHASE_DIV], parity_in[0]};
end else begin: gen_ge10
assign phy_dout[(320*PARITY_MAP[10:8] + 80*PARITY_MAP[5:4] +
8*(PARITY_MAP[3:0]-5) + 4)+:4]
= {parity_in[3/PHASE_DIV], parity_in[2/PHASE_DIV],
parity_in[1/PHASE_DIV], parity_in[0]};
end
end
endgenerate
//*****************************************************************
generate
genvar m, n,x;
//*****************************************************************
// Control/address (multi-bit) buses
//*****************************************************************
// Row/Column address
for (m = 0; m < ROW_WIDTH; m = m + 1) begin: gen_addr_out
assign out_addr[m]
= mem_dq_out[48*ADDR_MAP[(12*m+8)+:3] +
12*ADDR_MAP[(12*m+4)+:2] +
ADDR_MAP[12*m+:4]];
if (ADDR_MAP[12*m+:4] < 4'hA) begin: gen_lt10
// For multi-bit buses, we also have to deal with transposition
// when going from the logic-side control bus to phy_dout
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*ADDR_MAP[(12*m+8)+:3] +
80*ADDR_MAP[(12*m+4)+:2] +
8*ADDR_MAP[12*m+:4] + n]
= mux_address[ROW_WIDTH*(n/PHASE_DIV) + m];
end
end else begin: gen_ge10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*ADDR_MAP[(12*m+8)+:3] +
80*ADDR_MAP[(12*m+4)+:2] +
8*(ADDR_MAP[12*m+:4]-5) + 4 + n]
= mux_address[ROW_WIDTH*(n/PHASE_DIV) + m];
end
end
end
// Bank address
for (m = 0; m < BANK_WIDTH; m = m + 1) begin: gen_ba_out
assign out_ba[m]
= mem_dq_out[48*BANK_MAP[(12*m+8)+:3] +
12*BANK_MAP[(12*m+4)+:2] +
BANK_MAP[12*m+:4]];
if (BANK_MAP[12*m+:4] < 4'hA) begin: gen_lt10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*BANK_MAP[(12*m+8)+:3] +
80*BANK_MAP[(12*m+4)+:2] +
8*BANK_MAP[12*m+:4] + n]
= mux_bank[BANK_WIDTH*(n/PHASE_DIV) + m];
end
end else begin: gen_ge10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*BANK_MAP[(12*m+8)+:3] +
80*BANK_MAP[(12*m+4)+:2] +
8*(BANK_MAP[12*m+:4]-5) + 4 + n]
= mux_bank[BANK_WIDTH*(n/PHASE_DIV) + m];
end
end
end
// Chip select
if (USE_CS_PORT == 1) begin: gen_cs_n_out
for (m = 0; m < CS_WIDTH*nCS_PER_RANK; m = m + 1) begin: gen_cs_out
assign out_cs_n[m]
= mem_dq_out[48*CS_MAP[(12*m+8)+:3] +
12*CS_MAP[(12*m+4)+:2] +
CS_MAP[12*m+:4]];
if (CS_MAP[12*m+:4] < 4'hA) begin: gen_lt10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*CS_MAP[(12*m+8)+:3] +
80*CS_MAP[(12*m+4)+:2] +
8*CS_MAP[12*m+:4] + n]
= mux_cs_n[CS_WIDTH*nCS_PER_RANK*(n/PHASE_DIV) + m];
end
end else begin: gen_ge10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*CS_MAP[(12*m+8)+:3] +
80*CS_MAP[(12*m+4)+:2] +
8*(CS_MAP[12*m+:4]-5) + 4 + n]
= mux_cs_n[CS_WIDTH*nCS_PER_RANK*(n/PHASE_DIV) + m];
end
end
end
end
if(CKE_ODT_AUX == "FALSE") begin
// ODT_ports
wire [ODT_WIDTH*nCK_PER_CLK -1 :0] mux_odt_remap ;
if(RANKS == 1) begin
for(x =0 ; x < nCK_PER_CLK ; x = x+1) begin
assign mux_odt_remap[(x*ODT_WIDTH)+:ODT_WIDTH] = {ODT_WIDTH{mux_odt[0]}} ;
end
end else begin
for(x =0 ; x < 2*nCK_PER_CLK ; x = x+2) begin
assign mux_odt_remap[(x*ODT_WIDTH/RANKS)+:ODT_WIDTH/RANKS] = {ODT_WIDTH/RANKS{mux_odt[0]}} ;
assign mux_odt_remap[((x*ODT_WIDTH/RANKS)+(ODT_WIDTH/RANKS))+:ODT_WIDTH/RANKS] = {ODT_WIDTH/RANKS{mux_odt[1]}} ;
end
end
if (USE_ODT_PORT == 1) begin: gen_odt_out
for (m = 0; m < ODT_WIDTH; m = m + 1) begin: gen_odt_out_1
assign out_odt[m]
= mem_dq_out[48*ODT_MAP[(12*m+8)+:3] +
12*ODT_MAP[(12*m+4)+:2] +
ODT_MAP[12*m+:4]];
if (ODT_MAP[12*m+:4] < 4'hA) begin: gen_lt10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*ODT_MAP[(12*m+8)+:3] +
80*ODT_MAP[(12*m+4)+:2] +
8*ODT_MAP[12*m+:4] + n]
= mux_odt_remap[ODT_WIDTH*(n/PHASE_DIV) + m];
end
end else begin: gen_ge10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*ODT_MAP[(12*m+8)+:3] +
80*ODT_MAP[(12*m+4)+:2] +
8*(ODT_MAP[12*m+:4]-5) + 4 + n]
= mux_odt_remap[ODT_WIDTH*(n/PHASE_DIV) + m];
end
end
end
end
wire [CKE_WIDTH*nCK_PER_CLK -1:0] mux_cke_remap ;
for(x = 0 ; x < nCK_PER_CLK ; x = x +1) begin
assign mux_cke_remap[(x*CKE_WIDTH)+:CKE_WIDTH] = {CKE_WIDTH{mux_cke[x]}} ;
end
for (m = 0; m < CKE_WIDTH; m = m + 1) begin: gen_cke_out
assign out_cke[m]
= mem_dq_out[48*CKE_MAP[(12*m+8)+:3] +
12*CKE_MAP[(12*m+4)+:2] +
CKE_MAP[12*m+:4]];
if (CKE_MAP[12*m+:4] < 4'hA) begin: gen_lt10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*CKE_MAP[(12*m+8)+:3] +
80*CKE_MAP[(12*m+4)+:2] +
8*CKE_MAP[12*m+:4] + n]
= mux_cke_remap[CKE_WIDTH*(n/PHASE_DIV) + m];
end
end else begin: gen_ge10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*CKE_MAP[(12*m+8)+:3] +
80*CKE_MAP[(12*m+4)+:2] +
8*(CKE_MAP[12*m+:4]-5) + 4 + n]
= mux_cke_remap[CKE_WIDTH*(n/PHASE_DIV) + m];
end
end
end
end
//*****************************************************************
// Data mask
//*****************************************************************
if (USE_DM_PORT == 1) begin: gen_dm_out
for (m = 0; m < DM_WIDTH; m = m + 1) begin: gen_dm_out
assign out_dm[m]
= mem_dq_out[48*FULL_MASK_MAP[(12*m+8)+:3] +
12*FULL_MASK_MAP[(12*m+4)+:2] +
FULL_MASK_MAP[12*m+:4]];
assign ts_dm[m]
= mem_dq_ts[48*FULL_MASK_MAP[(12*m+8)+:3] +
12*FULL_MASK_MAP[(12*m+4)+:2] +
FULL_MASK_MAP[12*m+:4]];
for (n = 0; n < PHASE_PER_CLK; n = n + 1) begin: loop_xpose
assign phy_dout[320*FULL_MASK_MAP[(12*m+8)+:3] +
80*FULL_MASK_MAP[(12*m+4)+:2] +
8*FULL_MASK_MAP[12*m+:4] + n]
= mux_wrdata_mask[DM_WIDTH*n + m];
end
end
end
//*****************************************************************
// Input and output DQ
//*****************************************************************
for (m = 0; m < DQ_WIDTH; m = m + 1) begin: gen_dq_inout
// to MC_PHY
assign mem_dq_in[40*FULL_DATA_MAP[(12*m+8)+:3] +
10*FULL_DATA_MAP[(12*m+4)+:2] +
FULL_DATA_MAP[12*m+:4]]
= in_dq[m];
// to I/O buffers
assign out_dq[m]
= mem_dq_out[48*FULL_DATA_MAP[(12*m+8)+:3] +
12*FULL_DATA_MAP[(12*m+4)+:2] +
FULL_DATA_MAP[12*m+:4]];
assign ts_dq[m]
= mem_dq_ts[48*FULL_DATA_MAP[(12*m+8)+:3] +
12*FULL_DATA_MAP[(12*m+4)+:2] +
FULL_DATA_MAP[12*m+:4]];
for (n = 0; n < PHASE_PER_CLK; n = n + 1) begin: loop_xpose
assign phy_dout[320*FULL_DATA_MAP[(12*m+8)+:3] +
80*FULL_DATA_MAP[(12*m+4)+:2] +
8*FULL_DATA_MAP[12*m+:4] + n]
= mux_wrdata[DQ_WIDTH*n + m];
end
end
//*****************************************************************
// Input and output DQS
//*****************************************************************
for (m = 0; m < DQS_WIDTH; m = m + 1) begin: gen_dqs_inout
// to MC_PHY
assign mem_dqs_in[4*DQS_BYTE_MAP[(8*m+4)+:3] + DQS_BYTE_MAP[(8*m)+:2]]
= in_dqs[m];
// to I/O buffers
assign out_dqs[m]
= mem_dqs_out[4*DQS_BYTE_MAP[(8*m+4)+:3] + DQS_BYTE_MAP[(8*m)+:2]];
assign ts_dqs[m]
= mem_dqs_ts[4*DQS_BYTE_MAP[(8*m+4)+:3] + DQS_BYTE_MAP[(8*m)+:2]];
end
endgenerate
assign pd_out = pd_out_pre[byte_sel_cnt_w1];
//***************************************************************************
// Memory I/F output and I/O buffer instantiation
//***************************************************************************
// Note on instantiation - generally at the minimum, it's not required to
// instantiate the output buffers - they can be inferred by the synthesis
// tool, and there aren't any attributes that need to be associated with
// them. Consider as a future option to take out the OBUF instantiations
OBUF u_cas_n_obuf
(
.I (out_cas_n),
.O (ddr_cas_n)
);
OBUF u_ras_n_obuf
(
.I (out_ras_n),
.O (ddr_ras_n)
);
OBUF u_we_n_obuf
(
.I (out_we_n),
.O (ddr_we_n)
);
generate
genvar p;
for (p = 0; p < ROW_WIDTH; p = p + 1) begin: gen_addr_obuf
OBUF u_addr_obuf
(
.I (out_addr[p]),
.O (ddr_addr[p])
);
end
for (p = 0; p < BANK_WIDTH; p = p + 1) begin: gen_bank_obuf
OBUF u_bank_obuf
(
.I (out_ba[p]),
.O (ddr_ba[p])
);
end
if (USE_CS_PORT == 1) begin: gen_cs_n_obuf
for (p = 0; p < CS_WIDTH*nCS_PER_RANK; p = p + 1) begin: gen_cs_obuf
OBUF u_cs_n_obuf
(
.I (out_cs_n[p]),
.O (ddr_cs_n[p])
);
end
end
if(CKE_ODT_AUX == "FALSE")begin:cke_odt_thru_outfifo
if (USE_ODT_PORT== 1) begin: gen_odt_obuf
for (p = 0; p < ODT_WIDTH; p = p + 1) begin: gen_odt_obuf
OBUF u_cs_n_obuf
(
.I (out_odt[p]),
.O (ddr_odt[p])
);
end
end
for (p = 0; p < CKE_WIDTH; p = p + 1) begin: gen_cke_obuf
OBUF u_cs_n_obuf
(
.I (out_cke[p]),
.O (ddr_cke[p])
);
end
end
if (REG_CTRL == "ON") begin: gen_parity_obuf
// Generate addr/ctrl parity output only for DDR3 registered DIMMs
OBUF u_parity_obuf
(
.I (out_parity),
.O (ddr_parity)
);
end else begin: gen_parity_tieoff
assign ddr_parity = 1'b0;
end
if ((DRAM_TYPE == "DDR3") || (REG_CTRL == "ON")) begin: gen_reset_obuf
// Generate reset output only for DDR3 and DDR2 RDIMMs
OBUF u_reset_obuf
(
.I (mux_reset_n),
.O (ddr_reset_n)
);
end else begin: gen_reset_tieoff
assign ddr_reset_n = 1'b1;
end
if (USE_DM_PORT == 1) begin: gen_dm_obuf
for (p = 0; p < DM_WIDTH; p = p + 1) begin: loop_dm
OBUFT u_dm_obuf
(
.I (out_dm[p]),
.T (ts_dm[p]),
.O (ddr_dm[p])
);
end
end else begin: gen_dm_tieoff
assign ddr_dm = 'b0;
end
if (DATA_IO_PRIM_TYPE == "HP_LP") begin: gen_dq_iobuf_HP
for (p = 0; p < DQ_WIDTH; p = p + 1) begin: gen_dq_iobuf
IOBUF_DCIEN #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR)
)
u_iobuf_dq
(
.DCITERMDISABLE (data_io_idle_pwrdwn),
.IBUFDISABLE (data_io_idle_pwrdwn),
.I (out_dq[p]),
.T (ts_dq[p]),
.O (in_dq[p]),
.IO (ddr_dq[p])
);
end
end else if (DATA_IO_PRIM_TYPE == "HR_LP") begin: gen_dq_iobuf_HR
for (p = 0; p < DQ_WIDTH; p = p + 1) begin: gen_dq_iobuf
IOBUF_INTERMDISABLE #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR)
)
u_iobuf_dq
(
.INTERMDISABLE (data_io_idle_pwrdwn),
.IBUFDISABLE (data_io_idle_pwrdwn),
.I (out_dq[p]),
.T (ts_dq[p]),
.O (in_dq[p]),
.IO (ddr_dq[p])
);
end
end else begin: gen_dq_iobuf_default
for (p = 0; p < DQ_WIDTH; p = p + 1) begin: gen_dq_iobuf
IOBUF #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR)
)
u_iobuf_dq
(
.I (out_dq[p]),
.T (ts_dq[p]),
.O (in_dq[p]),
.IO (ddr_dq[p])
);
end
end
//if (DATA_IO_PRIM_TYPE == "HP_LP") begin: gen_dqs_iobuf_HP
if ((BANK_TYPE == "HP_IO") || (BANK_TYPE == "HPL_IO")) begin: gen_dqs_iobuf_HP
for (p = 0; p < DQS_WIDTH; p = p + 1) begin: gen_dqs_iobuf
if ((DRAM_TYPE == "DDR2") &&
(DDR2_DQSN_ENABLE != "YES")) begin: gen_ddr2_dqs_se
IOBUF_DCIEN #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR)
)
u_iobuf_dqs
(
.DCITERMDISABLE (data_io_idle_pwrdwn),
.IBUFDISABLE (data_io_idle_pwrdwn),
.I (out_dqs[p]),
.T (ts_dqs[p]),
.O (in_dqs[p]),
.IO (ddr_dqs[p])
);
assign ddr_dqs_n[p] = 1'b0;
assign pd_out_pre[p] = 1'b0;
end else if ((DRAM_TYPE == "DDR2") ||
(tCK > 2500)) begin : gen_ddr2_or_low_dqs_diff
IOBUFDS_DCIEN #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR),
.DQS_BIAS ("TRUE")
)
u_iobuf_dqs
(
.DCITERMDISABLE (data_io_idle_pwrdwn),
.IBUFDISABLE (data_io_idle_pwrdwn),
.I (out_dqs[p]),
.T (ts_dqs[p]),
.O (in_dqs[p]),
.IO (ddr_dqs[p]),
.IOB (ddr_dqs_n[p])
);
assign pd_out_pre[p] = 1'b0;
end else begin: gen_dqs_diff
IOBUFDS_DIFF_OUT_DCIEN #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR),
.DQS_BIAS ("TRUE"),
.SIM_DEVICE ("7SERIES"),
.USE_IBUFDISABLE ("FALSE")
)
u_iobuf_dqs
(
.DCITERMDISABLE (data_io_idle_pwrdwn),
.I (out_dqs[p]),
.TM (ts_dqs[p]),
.TS (ts_dqs[p]),
.OB (in_dqs_lpbk_to_iddr[p]),
.O (in_dqs[p]),
.IO (ddr_dqs[p]),
.IOB (ddr_dqs_n[p])
);
mig_7series_v2_3_poc_pd #
(
.TCQ (TCQ),
.POC_USE_METASTABLE_SAMP (POC_USE_METASTABLE_SAMP)
)
u_iddr_edge_det
(
.clk (clk),
.iddr_rst (iddr_rst),
.kclk (in_dqs_lpbk_to_iddr[p]),
.mmcm_ps_clk (mmcm_ps_clk),
.pd_out (pd_out_pre[p])
);
end
end
//end else if (DATA_IO_PRIM_TYPE == "HR_LP") begin: gen_dqs_iobuf_HR
end else if ((BANK_TYPE == "HR_IO") || (BANK_TYPE == "HRL_IO")) begin: gen_dqs_iobuf_HR
for (p = 0; p < DQS_WIDTH; p = p + 1) begin: gen_dqs_iobuf
if ((DRAM_TYPE == "DDR2") &&
(DDR2_DQSN_ENABLE != "YES")) begin: gen_ddr2_dqs_se
IOBUF_INTERMDISABLE #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR)
)
u_iobuf_dqs
(
.INTERMDISABLE (data_io_idle_pwrdwn),
.IBUFDISABLE (data_io_idle_pwrdwn),
.I (out_dqs[p]),
.T (ts_dqs[p]),
.O (in_dqs[p]),
.IO (ddr_dqs[p])
);
assign ddr_dqs_n[p] = 1'b0;
assign pd_out_pre[p] = 1'b0;
end else if ((DRAM_TYPE == "DDR2") ||
(tCK > 2500)) begin: gen_ddr2_or_low_dqs_diff
IOBUFDS_INTERMDISABLE #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR),
.DQS_BIAS ("TRUE")
)
u_iobuf_dqs
(
.INTERMDISABLE (data_io_idle_pwrdwn),
.IBUFDISABLE (data_io_idle_pwrdwn),
.I (out_dqs[p]),
.T (ts_dqs[p]),
.O (in_dqs[p]),
.IO (ddr_dqs[p]),
.IOB (ddr_dqs_n[p])
);
assign pd_out_pre[p] = 1'b0;
end else begin: gen_dqs_diff
IOBUFDS_DIFF_OUT_INTERMDISABLE #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR),
.DQS_BIAS ("TRUE"),
.SIM_DEVICE ("7SERIES"),
.USE_IBUFDISABLE ("FALSE")
)
u_iobuf_dqs
(
.INTERMDISABLE (data_io_idle_pwrdwn),
//.IBUFDISABLE (data_io_idle_pwrdwn),
.I (out_dqs[p]),
.TM (ts_dqs[p]),
.TS (ts_dqs[p]),
.OB (in_dqs_lpbk_to_iddr[p]),
.O (in_dqs[p]),
.IO (ddr_dqs[p]),
.IOB (ddr_dqs_n[p])
);
mig_7series_v2_3_poc_pd #
(
.TCQ (TCQ),
.POC_USE_METASTABLE_SAMP (POC_USE_METASTABLE_SAMP)
)
u_iddr_edge_det
(
.clk (clk),
.iddr_rst (iddr_rst),
.kclk (in_dqs_lpbk_to_iddr[p]),
.mmcm_ps_clk (mmcm_ps_clk),
.pd_out (pd_out_pre[p])
);
end
end
end else begin: gen_dqs_iobuf_default
for (p = 0; p < DQS_WIDTH; p = p + 1) begin: gen_dqs_iobuf
if ((DRAM_TYPE == "DDR2") &&
(DDR2_DQSN_ENABLE != "YES")) begin: gen_ddr2_dqs_se
IOBUF #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR)
)
u_iobuf_dqs
(
.I (out_dqs[p]),
.T (ts_dqs[p]),
.O (in_dqs[p]),
.IO (ddr_dqs[p])
);
assign ddr_dqs_n[p] = 1'b0;
assign pd_out_pre[p] = 1'b0;
end else begin: gen_dqs_diff
IOBUFDS #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR),
.DQS_BIAS ("TRUE")
)
u_iobuf_dqs
(
.I (out_dqs[p]),
.T (ts_dqs[p]),
.O (in_dqs[p]),
.IO (ddr_dqs[p]),
.IOB (ddr_dqs_n[p])
);
assign pd_out_pre[p] = 1'b0;
end
end
end
endgenerate
always @(posedge clk) begin
phy_ctl_wd_i1 <= #TCQ phy_ctl_wd;
phy_ctl_wr_i1 <= #TCQ phy_ctl_wr;
phy_ctl_wd_i2 <= #TCQ phy_ctl_wd_i1;
phy_ctl_wr_i2 <= #TCQ phy_ctl_wr_i1;
data_offset_1_i1 <= #TCQ data_offset_1;
data_offset_1_i2 <= #TCQ data_offset_1_i1;
data_offset_2_i1 <= #TCQ data_offset_2;
data_offset_2_i2 <= #TCQ data_offset_2_i1;
end
// 2 cycles of command delay needed for 4;1 mode. 2:1 mode does not need it.
// 2:1 mode the command goes through pre fifo
assign phy_ctl_wd_temp = (nCK_PER_CLK == 4) ? phy_ctl_wd_i2 : phy_ctl_wd_of;
assign phy_ctl_wr_temp = (nCK_PER_CLK == 4) ? phy_ctl_wr_i2 : phy_ctl_wr_of;
assign data_offset_1_temp = (nCK_PER_CLK == 4) ? data_offset_1_i2 : data_offset_1_of;
assign data_offset_2_temp = (nCK_PER_CLK == 4) ? data_offset_2_i2 : data_offset_2_of;
generate
begin
mig_7series_v2_3_ddr_of_pre_fifo #
(
.TCQ (25),
.DEPTH (8),
.WIDTH (32)
)
phy_ctl_pre_fifo_0
(
.clk (clk),
.rst (rst),
.full_in (phy_ctl_full_temp[1]),
.wr_en_in (phy_ctl_wr),
.d_in (phy_ctl_wd),
.wr_en_out (phy_ctl_wr_of),
.d_out (phy_ctl_wd_of)
);
mig_7series_v2_3_ddr_of_pre_fifo #
(
.TCQ (25),
.DEPTH (8),
.WIDTH (6)
)
phy_ctl_pre_fifo_1
(
.clk (clk),
.rst (rst),
.full_in (phy_ctl_full_temp[2]),
.wr_en_in (phy_ctl_wr),
.d_in (data_offset_1),
.wr_en_out (),
.d_out (data_offset_1_of)
);
mig_7series_v2_3_ddr_of_pre_fifo #
(
.TCQ (25),
.DEPTH (8),
.WIDTH (6)
)
phy_ctl_pre_fifo_2
(
.clk (clk),
.rst (rst),
.full_in (phy_ctl_full_temp[3]),
.wr_en_in (phy_ctl_wr),
.d_in (data_offset_2),
.wr_en_out (),
.d_out (data_offset_2_of)
);
end
endgenerate
//***************************************************************************
// Hard PHY instantiation
//***************************************************************************
assign phy_ctl_full = phy_ctl_full_temp[0];
mig_7series_v2_3_ddr_mc_phy #
(
.BYTE_LANES_B0 (BYTE_LANES_B0),
.BYTE_LANES_B1 (BYTE_LANES_B1),
.BYTE_LANES_B2 (BYTE_LANES_B2),
.BYTE_LANES_B3 (BYTE_LANES_B3),
.BYTE_LANES_B4 (BYTE_LANES_B4),
.DATA_CTL_B0 (DATA_CTL_B0),
.DATA_CTL_B1 (DATA_CTL_B1),
.DATA_CTL_B2 (DATA_CTL_B2),
.DATA_CTL_B3 (DATA_CTL_B3),
.DATA_CTL_B4 (DATA_CTL_B4),
.PHY_0_BITLANES (PHY_0_BITLANES),
.PHY_1_BITLANES (PHY_1_BITLANES),
.PHY_2_BITLANES (PHY_2_BITLANES),
.PHY_0_BITLANES_OUTONLY (PHY_0_BITLANES_OUTONLY),
.PHY_1_BITLANES_OUTONLY (PHY_1_BITLANES_OUTONLY),
.PHY_2_BITLANES_OUTONLY (PHY_2_BITLANES_OUTONLY),
.RCLK_SELECT_BANK (CKE_ODT_RCLK_SELECT_BANK),
.RCLK_SELECT_LANE (CKE_ODT_RCLK_SELECT_LANE),
//.CKE_ODT_AUX (CKE_ODT_AUX),
.GENERATE_DDR_CK_MAP (TMP_GENERATE_DDR_CK_MAP),
.BYTELANES_DDR_CK (TMP_BYTELANES_DDR_CK),
.NUM_DDR_CK (CK_WIDTH),
.LP_DDR_CK_WIDTH (LP_DDR_CK_WIDTH),
.PO_CTL_COARSE_BYPASS ("FALSE"),
.PHYCTL_CMD_FIFO ("FALSE"),
.PHY_CLK_RATIO (nCK_PER_CLK),
.MASTER_PHY_CTL (MASTER_PHY_CTL),
.PHY_FOUR_WINDOW_CLOCKS (63),
.PHY_EVENTS_DELAY (18),
.PHY_COUNT_EN ("FALSE"), //PHY_COUNT_EN
.PHY_SYNC_MODE ("FALSE"),
.SYNTHESIS ((SIM_CAL_OPTION == "NONE") ? "TRUE" : "FALSE"),
.PHY_DISABLE_SEQ_MATCH ("TRUE"), //"TRUE"
.PHY_0_GENERATE_IDELAYCTRL ("FALSE"),
.PHY_0_A_PI_FREQ_REF_DIV (PHY_0_A_PI_FREQ_REF_DIV),
.PHY_0_CMD_OFFSET (PHY_0_CMD_OFFSET), //for CKE
.PHY_0_RD_CMD_OFFSET_0 (PHY_0_RD_CMD_OFFSET_0),
.PHY_0_RD_CMD_OFFSET_1 (PHY_0_RD_CMD_OFFSET_1),
.PHY_0_RD_CMD_OFFSET_2 (PHY_0_RD_CMD_OFFSET_2),
.PHY_0_RD_CMD_OFFSET_3 (PHY_0_RD_CMD_OFFSET_3),
.PHY_0_RD_DURATION_0 (6),
.PHY_0_RD_DURATION_1 (6),
.PHY_0_RD_DURATION_2 (6),
.PHY_0_RD_DURATION_3 (6),
.PHY_0_WR_CMD_OFFSET_0 (PHY_0_WR_CMD_OFFSET_0),
.PHY_0_WR_CMD_OFFSET_1 (PHY_0_WR_CMD_OFFSET_1),
.PHY_0_WR_CMD_OFFSET_2 (PHY_0_WR_CMD_OFFSET_2),
.PHY_0_WR_CMD_OFFSET_3 (PHY_0_WR_CMD_OFFSET_3),
.PHY_0_WR_DURATION_0 (PHY_0_WR_DURATION_0),
.PHY_0_WR_DURATION_1 (PHY_0_WR_DURATION_1),
.PHY_0_WR_DURATION_2 (PHY_0_WR_DURATION_2),
.PHY_0_WR_DURATION_3 (PHY_0_WR_DURATION_3),
.PHY_0_AO_TOGGLE ((RANKS == 1) ? 1 : 5),
.PHY_0_A_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_0_B_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_0_C_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_0_D_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_0_A_PO_OCLKDELAY_INV (PO_OCLKDELAY_INV),
.PHY_0_A_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_0_B_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_0_C_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_0_D_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_1_GENERATE_IDELAYCTRL ("FALSE"),
//.PHY_1_GENERATE_DDR_CK (TMP_PHY_1_GENERATE_DDR_CK),
//.PHY_1_NUM_DDR_CK (1),
.PHY_1_A_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_1_B_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_1_C_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_1_D_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_1_A_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_1_B_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_1_C_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_1_D_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_2_GENERATE_IDELAYCTRL ("FALSE"),
//.PHY_2_GENERATE_DDR_CK (TMP_PHY_2_GENERATE_DDR_CK),
//.PHY_2_NUM_DDR_CK (1),
.PHY_2_A_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_2_B_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_2_C_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_2_D_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_2_A_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_2_B_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_2_C_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_2_D_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.TCK (tCK),
.PHY_0_IODELAY_GRP (IODELAY_GRP),
.PHY_1_IODELAY_GRP (IODELAY_GRP),
.PHY_2_IODELAY_GRP (IODELAY_GRP),
.FPGA_SPEED_GRADE (FPGA_SPEED_GRADE),
.BANK_TYPE (BANK_TYPE),
.CKE_ODT_AUX (CKE_ODT_AUX)
)
u_ddr_mc_phy
(
.rst (rst),
// Don't use MC_PHY to generate DDR_RESET_N output. Instead
// generate this output outside of MC_PHY (and synchronous to CLK)
.ddr_rst_in_n (1'b1),
.phy_clk (clk),
.freq_refclk (freq_refclk),
.mem_refclk (mem_refclk),
// Remove later - always same connection as phy_clk port
.mem_refclk_div4 (clk),
.pll_lock (pll_lock),
.auxout_clk (),
.sync_pulse (sync_pulse),
// IDELAYCTRL instantiated outside of mc_phy module
.idelayctrl_refclk (),
.phy_dout (phy_dout),
.phy_cmd_wr_en (phy_cmd_wr_en),
.phy_data_wr_en (phy_data_wr_en),
.phy_rd_en (phy_rd_en),
.phy_ctl_wd (phy_ctl_wd_temp),
.phy_ctl_wr (phy_ctl_wr_temp),
.if_empty_def (phy_if_empty_def),
.if_rst (phy_if_reset),
.phyGo ('b1),
.aux_in_1 (aux_in_1),
.aux_in_2 (aux_in_2),
// No support yet for different data offsets for different I/O banks
// (possible use in supporting wider range of skew among bytes)
.data_offset_1 (data_offset_1_temp),
.data_offset_2 (data_offset_2_temp),
.cke_in (),
.if_a_empty (),
.if_empty (if_empty),
.if_empty_or (),
.if_empty_and (),
.of_ctl_a_full (),
// .of_data_a_full (phy_data_full),
.of_ctl_full (phy_cmd_full),
.of_data_full (),
.pre_data_a_full (phy_pre_data_a_full),
.idelay_ld (idelay_ld),
.idelay_ce (idelay_ce),
.idelay_inc (idelay_inc),
.input_sink (),
.phy_din (phy_din),
.phy_ctl_a_full (),
.phy_ctl_full (phy_ctl_full_temp),
.mem_dq_out (mem_dq_out),
.mem_dq_ts (mem_dq_ts),
.mem_dq_in (mem_dq_in),
.mem_dqs_out (mem_dqs_out),
.mem_dqs_ts (mem_dqs_ts),
.mem_dqs_in (mem_dqs_in),
.aux_out (aux_out),
.phy_ctl_ready (),
.rst_out (),
.ddr_clk (ddr_clk),
//.rclk (),
.mcGo (phy_mc_go),
.phy_write_calib (phy_write_calib),
.phy_read_calib (phy_read_calib),
.calib_sel (calib_sel),
.calib_in_common (calib_in_common),
.calib_zero_inputs (calib_zero_inputs),
.calib_zero_ctrl (calib_zero_ctrl),
.calib_zero_lanes ('b0),
.po_fine_enable (po_fine_enable),
.po_coarse_enable (po_coarse_enable),
.po_fine_inc (po_fine_inc),
.po_coarse_inc (po_coarse_inc),
.po_counter_load_en (po_counter_load_en),
.po_sel_fine_oclk_delay (po_sel_fine_oclk_delay),
.po_counter_load_val (po_counter_load_val),
.po_counter_read_en (po_counter_read_en),
.po_coarse_overflow (),
.po_fine_overflow (),
.po_counter_read_val (po_counter_read_val),
.pi_rst_dqs_find (pi_rst_dqs_find),
.pi_fine_enable (pi_fine_enable),
.pi_fine_inc (pi_fine_inc),
.pi_counter_load_en (pi_counter_load_en),
.pi_counter_read_en (dbg_pi_counter_read_en),
.pi_counter_load_val (pi_counter_load_val),
.pi_fine_overflow (),
.pi_counter_read_val (pi_counter_read_val),
.pi_phase_locked (pi_phase_locked),
.pi_phase_locked_all (pi_phase_locked_all),
.pi_dqs_found (),
.pi_dqs_found_any (pi_dqs_found),
.pi_dqs_found_all (pi_dqs_found_all),
.pi_dqs_found_lanes (dbg_pi_dqs_found_lanes_phy4lanes),
// Currently not being used. May be used in future if periodic
// reads become a requirement. This output could be used to signal
// a catastrophic failure in read capture and the need for
// re-calibration.
.pi_dqs_out_of_range (pi_dqs_out_of_range)
,.ref_dll_lock (ref_dll_lock)
,.pi_phase_locked_lanes (dbg_pi_phase_locked_phy4lanes)
,.fine_delay (fine_delay_mod)
,.fine_delay_sel (fine_delay_sel_r)
// ,.rst_phaser_ref (rst_phaser_ref)
);
endmodule
|
//////////////////////////////////////////////////////////////////
// //
// Wishbone Arbiter //
// //
// This file is part of the Amber project //
// http://www.opencores.org/project,amber //
// //
// Description //
// Arbitrates between two wishbone masters and 13 wishbone //
// slave modules. The ethernet MAC wishbone master is given //
// priority over the Amber core. //
// //
// Author(s): //
// - Conor Santifort, [email protected] //
// //
//////////////////////////////////////////////////////////////////
// //
// Copyright (C) 2010 Authors and OPENCORES.ORG //
// //
// This source file may be used and distributed without //
// restriction provided that this copyright statement is not //
// removed from the file and that any derivative work contains //
// the original copyright notice and the associated disclaimer. //
// //
// This source file is free software; you can redistribute it //
// and/or modify it under the terms of the GNU Lesser General //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any //
// later version. //
// //
// This source is distributed in the hope that it will be //
// useful, but WITHOUT ANY WARRANTY; without even the implied //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
// PURPOSE. See the GNU Lesser General Public License for more //
// details. //
// //
// You should have received a copy of the GNU Lesser General //
// Public License along with this source; if not, download it //
// from http://www.opencores.org/lgpl.shtml //
// //
//////////////////////////////////////////////////////////////////
// TODO add module to switch endianess of ethmac i/f
module wishbone_arbiter #(
parameter WB_DWIDTH = 32,
parameter WB_SWIDTH = 4
)(
input i_wb_clk, // WISHBONE clock
// WISHBONE master 0 - Ethmac
input [31:0] i_m0_wb_adr,
input [WB_SWIDTH-1:0] i_m0_wb_sel,
input i_m0_wb_we,
output [WB_DWIDTH-1:0] o_m0_wb_dat,
input [WB_DWIDTH-1:0] i_m0_wb_dat,
input i_m0_wb_cyc,
input i_m0_wb_stb,
output o_m0_wb_ack,
output o_m0_wb_err,
// WISHBONE master 1 - Amber
input [31:0] i_m1_wb_adr,
input [WB_SWIDTH-1:0] i_m1_wb_sel,
input i_m1_wb_we,
output [WB_DWIDTH-1:0] o_m1_wb_dat,
input [WB_DWIDTH-1:0] i_m1_wb_dat,
input i_m1_wb_cyc,
input i_m1_wb_stb,
output o_m1_wb_ack,
output o_m1_wb_err,
// WISHBONE slave 0 - Ethmac
output [31:0] o_s0_wb_adr,
output [WB_SWIDTH-1:0] o_s0_wb_sel,
output o_s0_wb_we,
input [WB_DWIDTH-1:0] i_s0_wb_dat,
output [WB_DWIDTH-1:0] o_s0_wb_dat,
output o_s0_wb_cyc,
output o_s0_wb_stb,
input i_s0_wb_ack,
input i_s0_wb_err,
// WISHBONE slave 1 - Boot Memory
output [31:0] o_s1_wb_adr,
output [WB_SWIDTH-1:0] o_s1_wb_sel,
output o_s1_wb_we,
input [WB_DWIDTH-1:0] i_s1_wb_dat,
output [WB_DWIDTH-1:0] o_s1_wb_dat,
output o_s1_wb_cyc,
output o_s1_wb_stb,
input i_s1_wb_ack,
input i_s1_wb_err,
// WISHBONE slave 2 - Main Memory
output [31:0] o_s2_wb_adr,
output [WB_SWIDTH-1:0] o_s2_wb_sel,
output o_s2_wb_we,
input [WB_DWIDTH-1:0] i_s2_wb_dat,
output [WB_DWIDTH-1:0] o_s2_wb_dat,
output o_s2_wb_cyc,
output o_s2_wb_stb,
input i_s2_wb_ack,
input i_s2_wb_err,
// WISHBONE slave 3 - UART 0
output [31:0] o_s3_wb_adr,
output [WB_SWIDTH-1:0] o_s3_wb_sel,
output o_s3_wb_we,
input [WB_DWIDTH-1:0] i_s3_wb_dat,
output [WB_DWIDTH-1:0] o_s3_wb_dat,
output o_s3_wb_cyc,
output o_s3_wb_stb,
input i_s3_wb_ack,
input i_s3_wb_err,
// WISHBONE slave 4 - UART 1
output [31:0] o_s4_wb_adr,
output [WB_SWIDTH-1:0] o_s4_wb_sel,
output o_s4_wb_we,
input [WB_DWIDTH-1:0] i_s4_wb_dat,
output [WB_DWIDTH-1:0] o_s4_wb_dat,
output o_s4_wb_cyc,
output o_s4_wb_stb,
input i_s4_wb_ack,
input i_s4_wb_err,
// WISHBONE slave 5 - Test Module
output [31:0] o_s5_wb_adr,
output [WB_SWIDTH-1:0] o_s5_wb_sel,
output o_s5_wb_we,
input [WB_DWIDTH-1:0] i_s5_wb_dat,
output [WB_DWIDTH-1:0] o_s5_wb_dat,
output o_s5_wb_cyc,
output o_s5_wb_stb,
input i_s5_wb_ack,
input i_s5_wb_err,
// WISHBONE slave 6 - Timer Module
output [31:0] o_s6_wb_adr,
output [WB_SWIDTH-1:0] o_s6_wb_sel,
output o_s6_wb_we,
input [WB_DWIDTH-1:0] i_s6_wb_dat,
output [WB_DWIDTH-1:0] o_s6_wb_dat,
output o_s6_wb_cyc,
output o_s6_wb_stb,
input i_s6_wb_ack,
input i_s6_wb_err,
// WISHBONE slave 7 - Interrupt Controller
output [31:0] o_s7_wb_adr,
output [WB_SWIDTH-1:0] o_s7_wb_sel,
output o_s7_wb_we,
input [WB_DWIDTH-1:0] i_s7_wb_dat,
output [WB_DWIDTH-1:0] o_s7_wb_dat,
output o_s7_wb_cyc,
output o_s7_wb_stb,
input i_s7_wb_ack,
input i_s7_wb_err
);
`include "memory_configuration.v"
reg m0_wb_hold_r = 'd0;
reg m1_wb_hold_r = 'd0;
// wire m0_in_cycle;
// wire m1_in_cycle;
wire current_master;
reg current_master_r = 'd0;
wire next_master;
wire select_master;
wire [3:0] current_slave;
wire [31:0] master_adr;
wire [WB_SWIDTH-1:0] master_sel;
wire master_we;
wire [WB_DWIDTH-1:0] master_wdat;
wire master_cyc;
wire master_stb;
wire [WB_DWIDTH-1:0] master_rdat;
wire master_ack;
wire master_err;
reg status_set = 'd0; // used to terminate tests
// Arbitrate between m0 and m1. Ethmac (m0) always gets priority
assign next_master = i_m0_wb_cyc ? 1'd0 : 1'd1;
// Use cyc signal for arbitration so block accesses are not split up
// assign m0_in_cycle = m0_wb_hold_r && !master_ack;
// assign m1_in_cycle = m1_wb_hold_r && !master_ack;
// only select a new bus master when the current bus master
// daccess ends
assign select_master = current_master_r ? !m1_wb_hold_r : !m0_wb_hold_r;
assign current_master = select_master ? next_master : current_master_r;
always @( posedge i_wb_clk )
begin
current_master_r <= current_master;
m0_wb_hold_r <= i_m0_wb_stb && !o_m0_wb_ack;
m1_wb_hold_r <= i_m1_wb_stb && !o_m1_wb_ack;
end
// Arbitrate between slaves
assign current_slave = in_ethmac ( master_adr ) ? 4'd0 : // Ethmac
in_boot_mem ( master_adr ) ? 4'd1 : // Boot memory
in_main_mem ( master_adr ) ? 4'd2 : // Main memory
in_uart0 ( master_adr ) ? 4'd3 : // UART 0
in_uart1 ( master_adr ) ? 4'd4 : // UART 1
in_test ( master_adr ) ? 4'd5 : // Test Module
in_tm ( master_adr ) ? 4'd6 : // Timer Module
in_ic ( master_adr ) ? 4'd7 : // Interrupt Controller
4'd2 ; // default to main memory
assign master_adr = current_master ? i_m1_wb_adr : i_m0_wb_adr ;
assign master_sel = current_master ? i_m1_wb_sel : i_m0_wb_sel ;
assign master_wdat = current_master ? i_m1_wb_dat : i_m0_wb_dat ;
assign master_we = current_master ? i_m1_wb_we : i_m0_wb_we ;
assign master_cyc = current_master ? i_m1_wb_cyc : i_m0_wb_cyc ;
assign master_stb = current_master ? i_m1_wb_stb : i_m0_wb_stb ;
// Ethmac Slave outputs
assign o_s0_wb_adr = master_adr;
assign o_s0_wb_dat = master_wdat;
assign o_s0_wb_sel = master_sel;
assign o_s0_wb_we = current_slave == 4'd0 ? master_we : 1'd0;
assign o_s0_wb_cyc = current_slave == 4'd0 ? master_cyc : 1'd0;
assign o_s0_wb_stb = current_slave == 4'd0 ? master_stb : 1'd0;
// Boot Memory outputs
assign o_s1_wb_adr = master_adr;
assign o_s1_wb_dat = master_wdat;
assign o_s1_wb_sel = master_sel;
assign o_s1_wb_we = current_slave == 4'd1 ? master_we : 1'd0;
assign o_s1_wb_cyc = current_slave == 4'd1 ? master_cyc : 1'd0;
assign o_s1_wb_stb = current_slave == 4'd1 ? master_stb : 1'd0;
// Main Memory Outputs
assign o_s2_wb_adr = master_adr;
assign o_s2_wb_dat = master_wdat;
assign o_s2_wb_sel = master_sel;
assign o_s2_wb_we = current_slave == 4'd2 ? master_we : 1'd0;
assign o_s2_wb_cyc = current_slave == 4'd2 ? master_cyc : 1'd0;
assign o_s2_wb_stb = current_slave == 4'd2 ? master_stb : 1'd0;
// UART0 Outputs
assign o_s3_wb_adr = master_adr;
assign o_s3_wb_dat = master_wdat;
assign o_s3_wb_sel = master_sel;
assign o_s3_wb_we = current_slave == 4'd3 ? master_we : 1'd0;
assign o_s3_wb_cyc = current_slave == 4'd3 ? master_cyc : 1'd0;
assign o_s3_wb_stb = current_slave == 4'd3 ? master_stb : 1'd0;
// UART1 Outputs
assign o_s4_wb_adr = master_adr;
assign o_s4_wb_dat = master_wdat;
assign o_s4_wb_sel = master_sel;
assign o_s4_wb_we = current_slave == 4'd4 ? master_we : 1'd0;
assign o_s4_wb_cyc = current_slave == 4'd4 ? master_cyc : 1'd0;
assign o_s4_wb_stb = current_slave == 4'd4 ? master_stb : 1'd0;
// Test Module Outputs
assign o_s5_wb_adr = master_adr;
assign o_s5_wb_dat = master_wdat;
assign o_s5_wb_sel = master_sel;
assign o_s5_wb_we = current_slave == 5'd5 ? master_we : 1'd0;
assign o_s5_wb_cyc = current_slave == 5'd5 ? master_cyc : 1'd0;
assign o_s5_wb_stb = current_slave == 5'd5 ? master_stb : 1'd0;
// Timers Outputs
assign o_s6_wb_adr = master_adr;
assign o_s6_wb_dat = master_wdat;
assign o_s6_wb_sel = master_sel;
assign o_s6_wb_we = current_slave == 6'd6 ? master_we : 1'd0;
assign o_s6_wb_cyc = current_slave == 6'd6 ? master_cyc : 1'd0;
assign o_s6_wb_stb = current_slave == 6'd6 ? master_stb : 1'd0;
// Interrupt Controller
assign o_s7_wb_adr = master_adr;
assign o_s7_wb_dat = master_wdat;
assign o_s7_wb_sel = master_sel;
assign o_s7_wb_we = current_slave == 4'd7 ? master_we : 1'd0;
assign o_s7_wb_cyc = current_slave == 4'd7 ? master_cyc : 1'd0;
assign o_s7_wb_stb = current_slave == 4'd7 ? master_stb : 1'd0;
// Master Outputs
assign master_rdat = current_slave == 4'd0 ? i_s0_wb_dat :
current_slave == 4'd1 ? i_s1_wb_dat :
current_slave == 4'd2 ? i_s2_wb_dat :
current_slave == 4'd3 ? i_s3_wb_dat :
current_slave == 4'd4 ? i_s4_wb_dat :
current_slave == 4'd5 ? i_s5_wb_dat :
current_slave == 4'd6 ? i_s6_wb_dat :
current_slave == 4'd7 ? i_s7_wb_dat :
i_s2_wb_dat ;
assign master_ack = current_slave == 4'd0 ? i_s0_wb_ack :
current_slave == 4'd1 ? i_s1_wb_ack :
current_slave == 4'd2 ? i_s2_wb_ack :
current_slave == 4'd3 ? i_s3_wb_ack :
current_slave == 4'd4 ? i_s4_wb_ack :
current_slave == 4'd5 ? i_s5_wb_ack :
current_slave == 4'd6 ? i_s6_wb_ack :
current_slave == 4'd7 ? i_s7_wb_ack :
i_s2_wb_ack ;
assign master_err = current_slave == 4'd0 ? i_s0_wb_err :
current_slave == 4'd1 ? i_s1_wb_err :
current_slave == 4'd2 ? i_s2_wb_err :
current_slave == 4'd3 ? i_s3_wb_err :
current_slave == 4'd4 ? i_s4_wb_err :
current_slave == 4'd5 ? i_s5_wb_err :
current_slave == 4'd6 ? i_s6_wb_err :
current_slave == 4'd7 ? i_s7_wb_err :
i_s2_wb_err ;
// Ethmac Master Outputs
assign o_m0_wb_dat = master_rdat;
assign o_m0_wb_ack = current_master ? 1'd0 : master_ack ;
assign o_m0_wb_err = current_master ? 1'd0 : master_err ;
// Amber Master Outputs
assign o_m1_wb_dat = master_rdat;
assign o_m1_wb_ack = current_master ? master_ack : 1'd0 ;
assign o_m1_wb_err = current_master ? master_err : 1'd0 ;
// ======================================
// Status Write
// ======================================
always @( posedge i_wb_clk )
if ( o_m1_wb_err )
status_set <= 1'd1;
endmodule
|
//Legal Notice: (C)2018 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module ulight_fifo_data_info (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 1: 0] address;
input clk;
input [ 13: 0] in_port;
input reset_n;
wire clk_en;
wire [ 13: 0] data_in;
wire [ 13: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {14 {(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
endmodule
|
`define INPUTS_P 4
/***************** TEST RATIONALE **********************
1. STATE SPACE
The UUT is tested with every possible reqs_i. Each reqs_i
is maintained for 2*INPUTS_P cycles and the grant_count,
no. of times a given input line is granted, of each line
is checked to verify the fairness of the arbitrer.
2. PARAMETERIZATION
The no. of inputs is the parameter of this test module.
A reasonable set of tests would include INPUTS_P = 1 2 3,
to check corner cases, and INPUTS_P = 4 10, which include
a power of 2 and a non power of 2.
********************************************************/
module test_bsg;
localparam cycle_time_lp = 20;
localparam inputs_lp = `INPUTS_P;
localparam case_num_lp = 4;
// Clock and reset generation
wire clk;
wire reset;
bsg_nonsynth_clock_gen #( .cycle_time_p(cycle_time_lp)
) clock_gen
( .o(clk)
);
bsg_nonsynth_reset_gen #( .num_clocks_p (1)
, .reset_cycles_lo_p(1)
, .reset_cycles_hi_p(5)
) reset_gen
( .clk_i (clk)
, .async_reset_o(reset)
);
initial
begin
$display("\n\n\n");
$display("===========================================================");
$display("testing with ...");
$display("INPUTS_P: %d\n", inputs_lp);
end
logic test_input_ready;
logic [inputs_lp-1:0] test_input_reqs_v [case_num_lp];
logic [inputs_lp-1:0] test_output_grants_v [case_num_lp];
logic [inputs_lp-1:0] test_input_reqs ;
logic [inputs_lp-1:0] test_output_grants;
//assign the test cases
initial begin
test_input_reqs_v[ 0 ] = 4'b0000 ; test_output_grants_v[ 0 ] = 4'b0000;
test_input_reqs_v[ 1 ] = 4'b0100 ; test_output_grants_v[ 1 ] = 4'b0100; //single request,
test_input_reqs_v[ 2 ] = 4'b1010 ; test_output_grants_v[ 2 ] = 4'b1000; //
test_input_reqs_v[ 3 ] = 4'b1110 ; test_output_grants_v[ 3 ] = 4'b0010; //
end
integer case_num;
// test input generation
always_ff @(posedge clk) begin
if(reset) begin
case_num <= 0;
test_input_reqs <= (inputs_lp)'(0);
test_input_ready <= 1'b1;
end else begin
case_num <= (case_num + 1)%case_num_lp ;
test_input_reqs <= test_input_reqs_v [ ( case_num +1) % case_num_lp ];
end
end
//instantiate the instance
wire v;
bsg_round_robin_arb #(.inputs_p(inputs_lp)
,.reset_on_sr_p( 1'b1 )
) UUT
( .clk_i (clk)
,.reset_i (reset)
,.grants_en_i (test_input_ready)
,.reqs_i (test_input_reqs)
,.grants_o(test_output_grants)
,.v_o (v)
,.tag_o ( )
,.yumi_i(v)
);
// check the result
always_ff @(negedge clk) begin
if(v) begin
$display("\n case num = %d, requests = %b", case_num, test_input_reqs ); if( test_output_grants_v [ case_num ] == test_output_grants )
$display("grants =%b, last_n=%b, last_r=%b, ==>Pass", test_output_grants, UUT.last_n, UUT.last_r);
else
$display("grants =%b, expect=%b, last_n=%b, last_r=%b,==>fail", test_output_grants,test_output_grants_v[ case_num ], UUT.last_n, UUT.last_r );
end
end
// finish
always@(negedge clk)
if( case_num == (case_num_lp -1) ) begin
$display("==========================================================");
#20 $finish;
end
endmodule
|
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// Quartus II 13.1.0 Build 162 10/23/2013
// START_FILE_HEADER -----------------------------------------------------------
// Filename : altera_primitives.v
//
// Description : Contains the behavioral models for Altera primitives.
//
// Limitation : None
//
// Owner : Wuei Hong Lai
//
// Copyright (c) Altera Corporation 1997-2005
// All rights reserved
//
// END_FILE_HEADER -------------------------------------------------------------
//if simulator dees not support begin_keywords/end_keywords pragmas then define macro SKIP_KEYWORDS_PRAGMA to skip them.
//pragmas are required to prevent "global" from being treated as a systemverilog 1800-2009 keyword
`ifndef SKIP_KEYWORDS_PRAGMA
`begin_keywords "1364-1995"
`endif
`timescale 1 ps / 1 ps
module global (in, out);
input in;
output out;
assign out = in;
endmodule
`ifndef SKIP_KEYWORDS_PRAGMA
`end_keywords
`endif
`timescale 1 ps / 1 ps
module carry (in, out);
input in;
output out;
assign out = in;
endmodule
`timescale 1 ps / 1 ps
module cascade (in, out);
input in;
output out;
assign out = in;
endmodule
`timescale 1 ps / 1 ps
module carry_sum (sin, cin, sout, cout);
input sin;
input cin;
output sout;
output cout;
assign sout = sin;
assign cout = cin;
endmodule
`timescale 1 ps / 1 ps
module exp (in, out);
input in;
output out;
assign out = ~in;
endmodule
`timescale 1 ps / 1 ps
`ifndef SKIP_KEYWORDS_PRAGMA
`begin_keywords "1364-1995"
`endif
module soft (in, out);
input in;
output out;
assign out = in;
endmodule
`ifndef SKIP_KEYWORDS_PRAGMA
`end_keywords
`endif
`timescale 1 ps / 1 ps
module opndrn (in, out);
input in;
output out;
bufif0 (out, in, in);
endmodule
`timescale 1 ps / 1 ps
module row_global (in, out);
input in;
output out;
assign out = in;
endmodule
`timescale 1 ps / 1 ps
module TRI (in, oe, out);
input in;
input oe;
output out;
bufif1 (out, in, oe);
endmodule
`timescale 1 ps / 1 ps
module lut_input (in, out);
input in;
output out;
assign out = in;
endmodule
`timescale 1 ps / 1 ps
module lut_output (in, out);
input in;
output out;
assign out = in;
endmodule
`timescale 1 ps / 1 ps
module latch (d, ena, q);
input d, ena;
output q;
reg q;
initial q = 1'b0;
always@ (d or ena)
begin
if (ena)
q <= d;
end
endmodule
`timescale 1 ps / 1 ps
module dlatch (d, ena, clrn, prn, q);
input d, ena, clrn, prn;
output q;
reg q;
initial q = 1'b0;
always@ (d or ena or clrn or prn)
begin
if (clrn == 1'b0)
q <= 1'b0;
else if (prn == 1'b0)
q <= 1'b1;
else if (ena)
q <= d;
end
endmodule
`timescale 1 ps / 1 ps
module prim_gdff (q, d, clk, ena, clr, pre, ald, adt, sclr, sload );
input d,clk,ena,clr,pre,ald,adt,sclr,sload;
output q;
reg q;
reg clk_pre;
initial q = 1'b0;
always@ (clk or clr or pre or ald or adt)
begin
if (clr == 1'b1)
q <= 1'b0;
else if (pre == 1'b1)
q <= 1'b1;
else if (ald == 1'b1)
q <= adt;
else if ((clk == 1'b1) && (clk_pre == 1'b0))
begin
if (ena == 1'b1)
begin
if (sclr == 1'b1)
q <= 1'b0;
else if (sload == 1'b1)
q <= adt;
else
q <= d;
end
end
clk_pre <= clk;
end
endmodule
`timescale 1 ps / 1 ps
module dff (d, clk, clrn, prn, q );
input d,clk,clrn,prn;
output q;
wire q;
tri1 prn, clrn;
prim_gdff inst (q, d, clk, 1'b1, !clrn, !prn, 1'b0, 1'b0, 1'b0, 1'b0);
endmodule
`timescale 1 ps / 1 ps
module dffe (d, clk, ena, clrn, prn,q );
input d,clk,ena,clrn,prn;
output q;
wire q;
tri1 prn, clrn, ena;
prim_gdff inst (q, d, clk, ena, !clrn, !prn, 1'b0, 1'b0, 1'b0, 1'b0);
endmodule
`timescale 1 ps / 1 ps
module dffea (d, clk, ena, clrn, prn, aload, adata,q );
input d,clk,ena,clrn,prn,aload,adata;
output q;
wire q;
tri0 aload;
tri1 prn, clrn, ena;
reg stalled_adata;
initial
begin
stalled_adata = adata;
end
always @(adata) begin
#1 stalled_adata = adata;
end
prim_gdff inst (q, d, clk, ena, !clrn, !prn, aload, stalled_adata, 1'b0, 1'b0);
endmodule
`timescale 1 ps / 1 ps
module dffeas (d, clk, ena, clrn, prn, aload, asdata, sclr, sload, devclrn, devpor, q );
parameter power_up = "DONT_CARE";
parameter is_wysiwyg = "false";
parameter dont_touch = "false";
parameter x_on_violation = "on";
parameter lpm_type = "dffeas";
input d,clk,ena,clrn,prn,aload,asdata,sclr,sload,devclrn,devpor;
output q;
wire q, q_high, q_low;
tri0 aload_in, sclr_in, sload_in, asdata_in;
tri1 prn_in, clrn_in, ena_in, devclrn_in, devpor_in;
assign aload_in = aload;
assign sclr_in = sclr;
assign sload_in = sload;
assign asdata_in = asdata;
assign prn_in = prn;
assign clrn_in = clrn;
assign ena_in = ena;
assign devclrn_in = devclrn;
assign devpor_in = devpor;
wire q_tmp;
reg viol;
reg q_tmp_dly;
wire reset;
wire nosloadsclr;
wire sloaddata;
assign reset = devpor_in && devclrn_in && clrn_in && prn_in && ena_in;
assign nosloadsclr = reset && (!sload_in && !sclr_in);
assign sloaddata = reset && sload_in;
assign q = q_tmp_dly;
specify
$setuphold (posedge clk &&& nosloadsclr, d, 0, 0, viol) ;
$setuphold (posedge clk &&& reset, sclr, 0, 0, viol) ;
$setuphold (posedge clk &&& reset, sload, 0, 0, viol) ;
$setuphold (posedge clk &&& sloaddata, asdata, 0, 0, viol) ;
$setuphold (posedge clk &&& reset, ena, 0, 0, viol) ;
(posedge clk => (q +: q_tmp)) = 0 ;
(negedge clrn => (q +: 1'b0)) = (0, 0) ;
(negedge prn => (q +: 1'b1)) = (0, 0) ;
(posedge aload => (q +: q_tmp)) = (0, 0) ;
(asdata => q) = (0, 0) ;
endspecify
initial
begin
if (power_up == "high")
q_tmp_dly = 1'b1;
else
q_tmp_dly = 1'b0;
end
always @(q_tmp)
begin
q_tmp_dly <= q_tmp;
end
generate
if (power_up != "high") begin
PRIM_GDFF_LOW (q_tmp,d,clk,ena_in, !clrn_in || !devpor_in || !devclrn_in,!prn_in,aload_in,asdata_in,sclr_in,sload_in,viol);
end
endgenerate
generate
if (power_up == "high") begin
PRIM_GDFF_HIGH (q_tmp,d,clk,ena_in,!clrn_in || !devpor_in || !devclrn_in,!prn_in,aload_in,asdata_in,sclr_in,sload_in,viol);
end
endgenerate
endmodule
`timescale 1 ps / 1 ps
module prim_gtff (q, t, clk, ena, clr, pre );
input t,clk,ena,clr,pre;
output q;
reg q;
reg clk_pre;
initial q = 1'b0;
always@ (clk or clr or pre)
begin
if (clr == 1'b1)
q <= 1'b0;
else if (pre == 1'b1)
q <= 1'b1;
else if ((clk == 1'b1) && (clk_pre == 1'b0))
begin
if (ena == 1'b1)
begin
if (t == 1'b1)
q <= ~q;
end
end
clk_pre <= clk;
end
endmodule
`timescale 1 ps / 1 ps
module tff (t, clk, clrn, prn, q );
input t,clk,clrn,prn;
output q;
wire q;
tri1 prn, clrn;
prim_gtff inst (q, t, clk, 1'b1, !clrn, !prn);
endmodule
`timescale 1 ps / 1 ps
module tffe (t, clk, ena, clrn, prn,q );
input t,clk,ena,clrn,prn;
output q;
wire q;
tri1 prn, clrn, ena;
prim_gtff inst (q, t, clk, ena, !clrn, !prn);
endmodule
`timescale 1 ps / 1 ps
module prim_gjkff (q, j, k, clk, ena, clr, pre );
input j,k,clk,ena,clr,pre;
output q;
reg q;
reg clk_pre;
initial q = 1'b0;
always@ (clk or clr or pre)
begin
if (clr)
q <= 1'b0;
else if (pre)
q <= 1'b1;
else if ((clk == 1'b1) && (clk_pre == 1'b0))
begin
if (ena == 1'b1)
begin
if (j && !k)
q <= 1'b1;
else if (!j && k)
q <= 1'b0;
else if (k && j)
q <= ~q;
end
end
clk_pre <= clk;
end
endmodule
`timescale 1 ps / 1 ps
module jkff (j, k, clk, clrn, prn, q );
input j,k,clk,clrn,prn;
output q;
wire q;
tri1 prn, clrn;
prim_gjkff inst (q, j, k, clk, 1'b1, !clrn, !prn);
endmodule
`timescale 1 ps / 1 ps
module jkffe (j, k, clk, ena, clrn, prn,q );
input j,k,clk,ena,clrn,prn;
output q;
wire q;
tri1 prn, clrn, ena;
prim_gjkff inst (q, j, k, clk, ena, !clrn, !prn);
endmodule
`timescale 1 ps / 1 ps
module prim_gsrff (q, s, r, clk, ena, clr, pre );
input s,r,clk,ena,clr,pre;
output q;
reg q;
reg clk_pre;
initial q = 1'b0;
always@ (clk or clr or pre)
begin
if (clr)
q <= 1'b0;
else if (pre)
q <= 1'b1;
else if ((clk == 1'b1) && (clk_pre == 1'b0))
begin
if (ena == 1'b1)
begin
if (s && !r)
q <= 1'b1;
else if (!s && r)
q <= 1'b0;
else if (s && r)
q <= ~q;
end
end
clk_pre <= clk;
end
endmodule
`timescale 1 ps / 1 ps
module srff (s, r, clk, clrn, prn, q );
input s,r,clk,clrn,prn;
output q;
wire q;
tri1 prn, clrn;
prim_gsrff inst (q, s, r, clk, 1'b1, !clrn, !prn);
endmodule
`timescale 1 ps / 1 ps
module srffe (s, r, clk, ena, clrn, prn,q );
input s,r,clk,ena,clrn,prn;
output q;
wire q;
tri1 prn, clrn, ena;
prim_gsrff inst (q, s, r, clk, ena, !clrn, !prn);
endmodule
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module clklock (
inclk, // input reference clock
outclk // output clock
);
// GLOBAL PARAMETER DECLARATION
parameter input_frequency = 10000; // units in ps
parameter clockboost = 1;
// INTERNAL PARAMETER DECLARATION
parameter valid_lock_cycles = 1;
parameter invalid_lock_cycles = 2;
// INPUT PORT DECLARATION
input inclk;
// OUTPUT PORT DECLARATION
output outclk;
// INTERNAL VARIABLE/REGISTER DECLARATION
reg outclk;
reg start_outclk;
reg outclk_tmp;
reg pll_lock;
reg clk_last_value;
reg violation;
reg clk_check;
reg [1:0] next_clk_check;
reg init;
real pll_last_rising_edge;
real pll_last_falling_edge;
real actual_clk_cycle;
real expected_clk_cycle;
real pll_duty_cycle;
real inclk_period;
real expected_next_clk_edge;
integer pll_rising_edge_count;
integer stop_lock_count;
integer start_lock_count;
integer clk_per_tolerance;
// variables for clock synchronizing
time last_synchronizing_rising_edge_for_outclk;
time outclk_synchronizing_period;
integer input_cycles_per_outclk;
integer outclk_cycles_per_sync_period;
integer input_cycle_count_to_sync0;
// variables for shedule_outclk
reg schedule_outclk;
reg output_value0;
time sched_time0;
integer rem0;
integer tmp_rem0;
integer clk_cnt0;
integer cyc0;
integer inc0;
integer cycle_to_adjust0;
time tmp_per0;
time ori_per0;
time high_time0;
time low_time0;
// INITIAL BLOCK
initial
begin
// check for invalid parameters
if (input_frequency <= 0)
begin
$display("ERROR: The period of the input clock (input_frequency) must be greater than 0");
$stop;
end
if ((clockboost != 1) && (clockboost != 2))
begin
$display("ERROR: The clock multiplication factor (clockboost) must be a value of 1 or 2.");
$stop;
end
stop_lock_count = 0;
violation = 0;
// clock synchronizing variables
last_synchronizing_rising_edge_for_outclk = 0;
outclk_synchronizing_period = 0;
input_cycles_per_outclk = 1;
outclk_cycles_per_sync_period = clockboost;
input_cycle_count_to_sync0 = 0;
inc0 = 1;
cycle_to_adjust0 = 0;
outclk_cycles_per_sync_period = clockboost;
input_cycles_per_outclk = 1;
clk_per_tolerance = 0.1 * input_frequency;
end
always @(next_clk_check)
begin
if (next_clk_check == 1)
begin
if ((clk_check === 1'b1) || (clk_check === 1'b0))
#((inclk_period+clk_per_tolerance)/2) clk_check = ~clk_check;
else
#((inclk_period+clk_per_tolerance)/2) clk_check = 1'b1;
end
else if (next_clk_check == 2)
begin
if ((clk_check === 1'b1) || (clk_check === 1'b0))
#(expected_next_clk_edge - $realtime) clk_check = ~clk_check;
else
#(expected_next_clk_edge - $realtime) clk_check = 1'b1;
end
next_clk_check = 0;
end
always @(inclk or clk_check)
begin
if(init !== 1'b1)
begin
start_lock_count = 0;
pll_rising_edge_count = 0;
pll_last_rising_edge = 0;
pll_last_falling_edge = 0;
pll_lock = 0;
init = 1'b1;
end
if ((inclk == 1'b1) && (clk_last_value !== inclk))
begin
if (pll_lock === 1)
next_clk_check = 1;
if (pll_rising_edge_count == 0) // this is first rising edge
begin
inclk_period = input_frequency;
pll_duty_cycle = inclk_period/2;
start_outclk = 0;
end
else if (pll_rising_edge_count == 1) // this is second rising edge
begin
expected_clk_cycle = inclk_period;
actual_clk_cycle = $realtime - pll_last_rising_edge;
if (actual_clk_cycle < (expected_clk_cycle - clk_per_tolerance) ||
actual_clk_cycle > (expected_clk_cycle + clk_per_tolerance))
begin
$display($realtime, "ps Warning: Inclock_Period Violation");
$display ("Instance: %m");
violation = 1;
if (pll_lock == 1'b1)
begin
stop_lock_count = stop_lock_count + 1;
if ((pll_lock == 1'b1) && (stop_lock_count == invalid_lock_cycles))
begin
pll_lock = 0;
$display ($realtime, "ps Warning: altclklock out of lock.");
$display ("Instance: %m");
start_lock_count = 1;
stop_lock_count = 0;
outclk_tmp = 1'bx;
end
end
else begin
start_lock_count = 1;
end
end
else
begin
if (($realtime - pll_last_falling_edge) < (pll_duty_cycle - clk_per_tolerance/2) ||
($realtime - pll_last_falling_edge) > (pll_duty_cycle + clk_per_tolerance/2))
begin
$display($realtime, "ps Warning: Duty Cycle Violation");
$display ("Instance: %m");
violation = 1;
end
else
violation = 0;
end
end
else if (($realtime - pll_last_rising_edge) < (expected_clk_cycle - clk_per_tolerance) ||
($realtime - pll_last_rising_edge) > (expected_clk_cycle + clk_per_tolerance))
begin
$display($realtime, "ps Warning: Cycle Violation");
$display ("Instance: %m");
violation = 1;
if (pll_lock == 1'b1)
begin
stop_lock_count = stop_lock_count + 1;
if (stop_lock_count == invalid_lock_cycles)
begin
pll_lock = 0;
$display ($realtime, "ps Warning: altclklock out of lock.");
$display ("Instance: %m");
start_lock_count = 1;
stop_lock_count = 0;
outclk_tmp = 1'bx;
end
end
else
begin
start_lock_count = 1;
end
end
else
begin
violation = 0;
actual_clk_cycle = $realtime - pll_last_rising_edge;
end
pll_last_rising_edge = $realtime;
pll_rising_edge_count = pll_rising_edge_count + 1;
if (!violation)
begin
if (pll_lock == 1'b1)
begin
input_cycle_count_to_sync0 = input_cycle_count_to_sync0 + 1;
if (input_cycle_count_to_sync0 == input_cycles_per_outclk)
begin
outclk_synchronizing_period = $realtime - last_synchronizing_rising_edge_for_outclk;
last_synchronizing_rising_edge_for_outclk = $realtime;
schedule_outclk = 1;
input_cycle_count_to_sync0 = 0;
end
end
else
begin
start_lock_count = start_lock_count + 1;
if (start_lock_count >= valid_lock_cycles)
begin
pll_lock = 1;
input_cycle_count_to_sync0 = 0;
outclk_synchronizing_period = actual_clk_cycle * input_cycles_per_outclk;
last_synchronizing_rising_edge_for_outclk = $realtime;
schedule_outclk = 1;
end
end
end
else
start_lock_count = 1;
end
else if ((inclk == 1'b0) && (clk_last_value !== inclk))
begin
if (pll_lock == 1)
begin
next_clk_check = 1;
if (($realtime - pll_last_rising_edge) < (pll_duty_cycle - clk_per_tolerance/2) ||
($realtime - pll_last_rising_edge) > (pll_duty_cycle + clk_per_tolerance/2))
begin
$display($realtime, "ps Warning: Duty Cycle Violation");
$display ("Instance: %m");
violation = 1;
if (pll_lock == 1'b1)
begin
stop_lock_count = stop_lock_count + 1;
if (stop_lock_count == invalid_lock_cycles)
begin
pll_lock = 0;
$display ($realtime, "ps Warning: clklock out of lock.");
$display ("Instance: %m");
start_lock_count = 0;
stop_lock_count = 0;
outclk_tmp = 1'bx;
end
end
end
else
violation = 0;
end
pll_last_falling_edge = $realtime;
end
else if (pll_lock == 1)
begin
if (inclk == 1'b1)
expected_next_clk_edge = pll_last_rising_edge + (inclk_period+clk_per_tolerance)/2;
else if (inclk == 'b0)
expected_next_clk_edge = pll_last_falling_edge + (inclk_period+clk_per_tolerance)/2;
else
expected_next_clk_edge = 0;
violation = 0;
if ($realtime < expected_next_clk_edge)
next_clk_check = 2;
else if ($realtime == expected_next_clk_edge)
next_clk_check = 1;
else
begin
$display($realtime, "ps Warning: Inclock_Period Violation");
$display ("Instance: %m");
violation = 1;
if (pll_lock == 1'b1)
begin
stop_lock_count = stop_lock_count + 1;
expected_next_clk_edge = $realtime + (inclk_period/2);
if (stop_lock_count == invalid_lock_cycles)
begin
pll_lock = 0;
$display ($realtime, "ps Warning: altclklock out of lock.");
$display ("Instance: %m");
start_lock_count = 1;
stop_lock_count = 0;
outclk_tmp = 1'bx;
end
else
next_clk_check = 2;
end
end
end
clk_last_value = inclk;
end
// outclk output
always @(posedge schedule_outclk)
begin
// initialise variables
inc0 = 1;
cycle_to_adjust0 = 0;
output_value0 = 1'b1;
sched_time0 = 0;
rem0 = outclk_synchronizing_period % outclk_cycles_per_sync_period;
ori_per0 = outclk_synchronizing_period / outclk_cycles_per_sync_period;
// schedule <outclk_cycles_per_sync_period> number of outclk cycles in this
// loop - in order to synchronize the output clock always to the input clock
// to get rid of clock drift for cases where the input clock period is
// not evenly divisible
for (clk_cnt0 = 1; clk_cnt0 <= outclk_cycles_per_sync_period;
clk_cnt0 = clk_cnt0 + 1)
begin
tmp_per0 = ori_per0;
if ((rem0 != 0) && (inc0 <= rem0))
begin
tmp_rem0 = (outclk_cycles_per_sync_period * inc0) % rem0;
cycle_to_adjust0 = (outclk_cycles_per_sync_period * inc0) / rem0;
if (tmp_rem0 != 0)
cycle_to_adjust0 = cycle_to_adjust0 + 1;
end
// if this cycle is the one to adjust the output clock period, then
// increment the period by 1 unit
if (cycle_to_adjust0 == clk_cnt0)
begin
tmp_per0 = tmp_per0 + 1;
inc0 = inc0 + 1;
end
// adjust the high and low cycle period
high_time0 = tmp_per0 / 2;
if ((tmp_per0 % 2) != 0)
high_time0 = high_time0 + 1;
low_time0 = tmp_per0 - high_time0;
// schedule the high and low cycle of 1 output clock period
for (cyc0 = 0; cyc0 <= 1; cyc0 = cyc0 + 1)
begin
// Avoid glitch in vcs when high_time0 and low_time0 is 0
// (due to outclk_synchronizing_period is 0)
if (outclk_synchronizing_period != 0)
outclk_tmp = #(sched_time0) output_value0;
else
outclk_tmp = #(sched_time0) 1'b0;
output_value0 = ~output_value0;
if (output_value0 == 1'b0)
begin
sched_time0 = high_time0;
end
else if (output_value0 == 1'b1)
begin
sched_time0 = low_time0;
end
end
end
// drop the schedule_outclk to 0 so that the "always@(inclk)" block can
// trigger this block again when the correct time comes
schedule_outclk = #1 1'b0;
end
always @(outclk_tmp)
begin
outclk <= outclk_tmp;
end
endmodule // clklock
// END OF MODULE CLKLOCK
`timescale 1 ps / 1 ps
module alt_inbuf (i, o);
input i;
output o;
parameter io_standard = "NONE";
parameter location = "NONE";
parameter enable_bus_hold = "NONE";
parameter weak_pull_up_resistor = "NONE";
parameter termination = "NONE";
parameter lpm_type = "alt_inbuf";
assign o = i;
endmodule
`timescale 1 ps / 1 ps
module alt_outbuf (i, o);
input i;
output o;
parameter io_standard = "NONE";
parameter current_strength = "NONE";
parameter current_strength_new = "NONE";
parameter slew_rate = -1;
parameter slow_slew_rate = "NONE";
parameter location = "NONE";
parameter enable_bus_hold = "NONE";
parameter weak_pull_up_resistor = "NONE";
parameter termination = "NONE";
parameter lpm_type = "alt_outbuf";
assign o = i;
endmodule
`timescale 1 ps / 1 ps
module alt_outbuf_tri (i, oe, o);
input i;
input oe;
output o;
parameter io_standard = "NONE";
parameter current_strength = "NONE";
parameter current_strength_new = "NONE";
parameter slew_rate = -1;
parameter slow_slew_rate = "NONE";
parameter location = "NONE";
parameter enable_bus_hold = "NONE";
parameter weak_pull_up_resistor = "NONE";
parameter termination = "NONE";
parameter lpm_type = "alt_outbuf_tri";
bufif1 (o, i, oe);
endmodule
`timescale 1 ps / 1 ps
module alt_iobuf (i, oe, io, o);
input i;
input oe;
inout io;
output o;
reg o;
parameter io_standard = "NONE";
parameter current_strength = "NONE";
parameter current_strength_new = "NONE";
parameter slew_rate = -1;
parameter slow_slew_rate = "NONE";
parameter location = "NONE";
parameter enable_bus_hold = "NONE";
parameter weak_pull_up_resistor = "NONE";
parameter termination = "NONE";
parameter input_termination = "NONE";
parameter output_termination = "NONE";
parameter lpm_type = "alt_iobuf";
always @(io)
begin
o = io;
end
assign io = (oe == 1) ? i : 1'bz;
endmodule
`timescale 1 ps / 1 ps
module alt_inbuf_diff (i, ibar, o);
input i;
input ibar;
output o;
parameter io_standard = "NONE";
parameter location = "NONE";
parameter enable_bus_hold = "NONE";
parameter weak_pull_up_resistor = "NONE";
parameter termination = "NONE";
parameter lpm_type = "alt_inbuf_diff";
reg out_tmp;
always@(i or ibar)
begin
casex({i,ibar})
2'b00: out_tmp = 1'bx;
2'b01: out_tmp = 1'b0;
2'b10: out_tmp = 1'b1;
2'b11: out_tmp = 1'bx;
default: out_tmp = 1'bx;
endcase
end
assign o = out_tmp;
endmodule
`timescale 1 ps / 1 ps
module alt_outbuf_diff (i, o, obar);
input i;
output o;
output obar;
parameter io_standard = "NONE";
parameter current_strength = "NONE";
parameter current_strength_new = "NONE";
parameter slew_rate = -1;
parameter location = "NONE";
parameter enable_bus_hold = "NONE";
parameter weak_pull_up_resistor = "NONE";
parameter termination = "NONE";
parameter lpm_type = "alt_outbuf_diff";
assign o = i;
assign obar = !i;
endmodule
`timescale 1 ps / 1 ps
module alt_outbuf_tri_diff (i, oe, o, obar);
input i;
input oe;
output o;
output obar;
parameter io_standard = "NONE";
parameter current_strength = "NONE";
parameter current_strength_new = "NONE";
parameter slew_rate = -1;
parameter location = "NONE";
parameter enable_bus_hold = "NONE";
parameter weak_pull_up_resistor = "NONE";
parameter termination = "NONE";
parameter lpm_type = "alt_outbuf_tri_diff";
bufif1 (o, i, oe);
bufif1 (obar, !i, oe);
endmodule
`timescale 1 ps / 1 ps
module alt_iobuf_diff (i, oe, io, iobar, o);
input i;
input oe;
inout io;
inout iobar;
output o;
parameter io_standard = "NONE";
parameter current_strength = "NONE";
parameter current_strength_new = "NONE";
parameter slew_rate = -1;
parameter location = "NONE";
parameter enable_bus_hold = "NONE";
parameter weak_pull_up_resistor = "NONE";
parameter termination = "NONE";
parameter input_termination = "NONE";
parameter output_termination = "NONE";
parameter lpm_type = "alt_iobuf_diff";
reg out_tmp;
always @(io or iobar)
begin
casex({io,iobar})
2'b00: out_tmp = 1'bx;
2'b01: out_tmp = 1'b0;
2'b10: out_tmp = 1'b1;
2'b11: out_tmp = 1'bx;
default: out_tmp = 1'bx;
endcase
end
assign o = out_tmp;
assign io = (oe === 1'b1) ? i : (oe === 1'b0) ? 1'bz : 1'bx;
assign iobar = (oe == 1'b1) ? !i : (oe == 1'b0) ? 1'bz : 1'bx;
endmodule
`timescale 1 ps / 1 ps
module alt_bidir_diff (oe, bidirin, io, iobar);
input oe;
inout bidirin;
inout io;
inout iobar;
parameter io_standard = "NONE";
parameter current_strength = "NONE";
parameter current_strength_new = "NONE";
parameter slew_rate = -1;
parameter location = "NONE";
parameter enable_bus_hold = "NONE";
parameter weak_pull_up_resistor = "NONE";
parameter termination = "NONE";
parameter input_termination = "NONE";
parameter output_termination = "NONE";
parameter lpm_type = "alt_bidir_diff";
reg out_tmp;
always @(io or iobar)
begin
casex({io,iobar})
2'b00: out_tmp = 1'bx;
2'b01: out_tmp = 1'b0;
2'b10: out_tmp = 1'b1;
2'b11: out_tmp = 1'bx;
default: out_tmp = 1'bx;
endcase
end
assign bidirin = (oe === 1'b0) ? out_tmp : (oe === 1'b1) ? 1'bz : 1'bx;
assign io = (oe === 1'b1) ? bidirin : (oe === 1'b0) ? 1'bz : 1'bx;
assign iobar = (oe == 1'b1) ? !bidirin : (oe == 1'b0) ? 1'bz : 1'bx;
endmodule
`timescale 1 ps / 1 ps
module alt_bidir_buf (oe, bidirin, io);
input oe;
inout bidirin;
inout io;
parameter io_standard = "NONE";
parameter current_strength = "NONE";
parameter current_strength_new = "NONE";
parameter slew_rate = -1;
parameter location = "NONE";
parameter enable_bus_hold = "NONE";
parameter weak_pull_up_resistor = "NONE";
parameter termination = "NONE";
parameter input_termination = "NONE";
parameter output_termination = "NONE";
parameter lpm_type = "alt_bidir_diff";
reg out_tmp;
always @(io)
begin
casex(io)
1'b0: out_tmp = 1'b0;
1'b1: out_tmp = 1'b1;
default: out_tmp = 1'bx;
endcase
end
assign bidirin = (oe === 1'b0) ? out_tmp : (oe === 1'b1) ? 1'bz : 1'bx;
assign io = (oe === 1'b1) ? bidirin : (oe === 1'b0) ? 1'bz : 1'bx;
endmodule
primitive PRIM_GDFF_LOW (q, d, clk, ena, clr, pre, ald, adt, sclr, sload, notifier );
input d,clk,ena,clr,pre,ald,adt,sclr,sload,notifier;
output q;
reg q;
initial q = 1'b0;
table
////d,clk, ena,clr,pre,ald,adt,sclr,sload,notifier : q : q'
? ? ? 1 ? ? ? ? ? ? : ? : 0; // aclr
? ? ? 0 1 ? ? ? ? ? : ? : 1; // apre
? ? ? 0 0 1 0 ? ? ? : ? : 0; // aload 0
? ? ? 0 0 1 1 ? ? ? : ? : 1; // aload 1
0 (01) 1 0 0 0 ? 0 0 ? : ? : 0; // din 0
1 (01) 1 0 0 0 ? 0 0 ? : ? : 1; // din 1
? (01) 1 0 0 0 ? 1 ? ? : ? : 0; // sclr
? (01) 1 0 0 0 0 0 1 ? : ? : 0; // sload 0
? (01) 1 0 0 0 1 0 1 ? : ? : 1; // sload 1
? ? 0 0 0 0 ? ? ? ? : ? : -; // no asy no ena
* ? ? ? ? ? ? ? ? ? : ? : -; // data edges
? (?0) ? ? ? ? ? ? ? ? : ? : -; // ignore falling clk
? ? * ? ? ? ? ? ? ? : ? : -; // enable edges
? ? ? (?0)? ? ? ? ? ? : ? : -; // falling asynchs
? ? ? ? (?0) ? ? ? ? ? : ? : -;
? ? ? ? ? (?0) ? ? ? ? : ? : -;
? ? ? ? ? 0 * ? ? ? : ? : -; // ignore adata edges when not aloading
? ? ? ? ? ? ? * ? ? : ? : -; // sclr edges
? ? ? ? ? ? ? ? * ? : ? : -; // sload edges
? (x?) 1 0 0 0 ? ? ? ? : ? : -; // ignore x transition of clock
? (?x) 1 0 0 0 ? ? ? ? : ? : -; // ignore x transition of clock
? ? ? x ? ? ? ? ? ? : ? : -; // ignore x input of clrn
? ? ? 0 x ? ? ? ? ? : ? : -; // ignore x input of pre
? ? ? 0 0 x ? ? ? ? : ? : -; // ignore x input of aload
? ? x 0 0 0 ? ? ? ? : ? : -; // ignore x input of ena
? (01) 1 0 0 0 ? x ? ? : ? : -; // ignore x input of sclr
? (01) 1 0 0 0 ? 0 x ? : ? : -; // ignore x input of sload
? ? ? 0 0 ? ? ? ? * : ? : x; // at any notifier event, output x
endtable
endprimitive
primitive PRIM_GDFF_HIGH (q, d, clk, ena, clr, pre, ald, adt, sclr, sload, notifier );
input d,clk,ena,clr,pre,ald,adt,sclr,sload,notifier;
output q;
reg q;
initial q = 1'b1;
table
////d,clk, ena,clr,pre,ald,adt,sclr,sload,notifier : q : q'
? ? ? 1 ? ? ? ? ? ? : ? : 0; // aclr
? ? ? 0 1 ? ? ? ? ? : ? : 1; // apre
? ? ? 0 0 1 0 ? ? ? : ? : 0; // aload 0
? ? ? 0 0 1 1 ? ? ? : ? : 1; // aload 1
0 (01) 1 0 0 0 ? 0 0 ? : ? : 0; // din 0
1 (01) 1 0 0 0 ? 0 0 ? : ? : 1; // din 1
? (01) 1 0 0 0 ? 1 ? ? : ? : 0; // sclr
? (01) 1 0 0 0 0 0 1 ? : ? : 0; // sload 0
? (01) 1 0 0 0 1 0 1 ? : ? : 1; // sload 1
? ? 0 0 0 0 ? ? ? ? : ? : -; // no asy no ena
* ? ? ? ? ? ? ? ? ? : ? : -; // data edges
? (?0) ? ? ? ? ? ? ? ? : ? : -; // ignore falling clk
? ? * ? ? ? ? ? ? ? : ? : -; // enable edges
? ? ? (?0)? ? ? ? ? ? : ? : -; // falling asynchs
? ? ? ? (?0) ? ? ? ? ? : ? : -;
? ? ? ? ? (?0) ? ? ? ? : ? : -;
? ? ? ? ? 0 * ? ? ? : ? : -; // ignore adata edges when not aloading
? ? ? ? ? ? ? * ? ? : ? : -; // sclr edges
? ? ? ? ? ? ? ? * ? : ? : -; // sload edges
? (x?) 1 0 0 0 ? ? ? ? : ? : -; // ignore x transition of clock
? (?x) 1 0 0 0 ? ? ? ? : ? : -; // ignore x transition of clock
? ? ? x ? ? ? ? ? ? : ? : -; // ignore x input of clrn
? ? ? 0 x ? ? ? ? ? : ? : -; // ignore x input of pre
? ? ? 0 0 x ? ? ? ? : ? : -; // ignore x input of aload
? ? x 0 0 0 ? ? ? ? : ? : -; // ignore x input of ena
? (01) 1 0 0 0 ? x ? ? : ? : -; // ignore x input of sclr
? (01) 1 0 0 0 ? 0 x ? : ? : -; // ignore x input of sload
? ? ? 0 0 ? ? ? ? * : ? : x; // at any notifier event, output x
endtable
endprimitive
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate casex/endcase w/ null_statement as default
module main ();
reg error;
reg [2:0] val1,val2;
reg [2:0] result ;
always @( val1 or val2)
casex (val1 & val2 )
3'b000,3'b001: result = 0;
3'b11x: result = 2;
3'b001: result = 1;
default result = 3;
endcase
initial
begin
error = 0;
val1 = 3'b0;
val2 = 3'b0;
if(result !=0)
begin
$display("FAILED casex 3.9E - default: ");
error = 1;
end
val1 = 3'b001;
val2 = 3'b011;
if(result !=1)
begin
$display("FAILED casex 3.9E - default: ");
error = 1;
end
val1 = 3'b111; // Should get no-action - expr = 3'b010
val2 = 3'b010;
if(result !=3)
begin
$display("FAILED casex 3.9E - default: ");
error = 1;
end
if(error == 0)
$display("PASSED");
end
endmodule // main
|
//-----------------------------------------------------------------------------
// Jonathan Westhues, March 2006
// iZsh <izsh at fail0verflow.com>, June 2014
//-----------------------------------------------------------------------------
`include "lo_read.v"
`include "lo_passthru.v"
`include "lo_edge_detect.v"
`include "util.v"
`include "clk_divider.v"
module fpga_lf(
input spck, output miso, input mosi, input ncs,
input pck0, input ck_1356meg, input ck_1356megb,
output pwr_lo, output pwr_hi,
output pwr_oe1, output pwr_oe2, output pwr_oe3, output pwr_oe4,
input [7:0] adc_d, output adc_clk, output adc_noe,
output ssp_frame, output ssp_din, input ssp_dout, output ssp_clk,
input cross_hi, input cross_lo,
output dbg
);
//-----------------------------------------------------------------------------
// The SPI receiver. This sets up the configuration word, which the rest of
// the logic looks at to determine how to connect the A/D and the coil
// drivers (i.e., which section gets it). Also assign some symbolic names
// to the configuration bits, for use below.
//-----------------------------------------------------------------------------
reg [15:0] shift_reg;
reg [7:0] divisor;
reg [7:0] conf_word;
reg [7:0] user_byte1;
always @(posedge ncs)
begin
case(shift_reg[15:12])
4'b0001:
begin
conf_word <= shift_reg[7:0];
if (shift_reg[7:0] == 8'b00000001) begin // LF edge detect
user_byte1 <= 127; // default threshold
end
end
4'b0010: divisor <= shift_reg[7:0]; // FPGA_CMD_SET_DIVISOR
4'b0011: user_byte1 <= shift_reg[7:0]; // FPGA_CMD_SET_USER_BYTE1
endcase
end
always @(posedge spck)
begin
if(~ncs)
begin
shift_reg[15:1] <= shift_reg[14:0];
shift_reg[0] <= mosi;
end
end
wire [2:0] major_mode = conf_word[7:5];
// For the low-frequency configuration:
wire lf_field = conf_word[0];
wire lf_ed_toggle_mode = conf_word[1]; // for lo_edge_detect
wire [7:0] lf_ed_threshold = user_byte1;
//-----------------------------------------------------------------------------
// And then we instantiate the modules corresponding to each of the FPGA's
// major modes, and use muxes to connect the outputs of the active mode to
// the output pins.
//-----------------------------------------------------------------------------
wire [7:0] pck_cnt;
wire pck_divclk;
clk_divider div_clk(pck0, divisor, pck_cnt, pck_divclk);
lo_read lr(
pck0, pck_cnt, pck_divclk,
lr_pwr_lo, lr_pwr_hi, lr_pwr_oe1, lr_pwr_oe2, lr_pwr_oe3, lr_pwr_oe4,
adc_d, lr_adc_clk,
lr_ssp_frame, lr_ssp_din, lr_ssp_clk,
lr_dbg, lf_field
);
lo_passthru lp(
pck_divclk,
lp_pwr_lo, lp_pwr_hi, lp_pwr_oe1, lp_pwr_oe2, lp_pwr_oe3, lp_pwr_oe4,
lp_adc_clk,
lp_ssp_din, ssp_dout,
cross_lo,
lp_dbg
);
lo_edge_detect le(
pck0, pck_divclk,
le_pwr_lo, le_pwr_hi, le_pwr_oe1, le_pwr_oe2, le_pwr_oe3, le_pwr_oe4,
adc_d, le_adc_clk,
le_ssp_frame, ssp_dout, le_ssp_clk,
cross_lo,
le_dbg,
lf_field,
lf_ed_toggle_mode, lf_ed_threshold
);
// Major modes:
// 000 -- LF reader (generic)
// 001 -- LF edge detect (generic)
// 010 -- LF passthrough
mux8 mux_ssp_clk (major_mode, ssp_clk, lr_ssp_clk, le_ssp_clk, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
mux8 mux_ssp_din (major_mode, ssp_din, lr_ssp_din, 1'b0, lp_ssp_din, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
mux8 mux_ssp_frame (major_mode, ssp_frame, lr_ssp_frame, le_ssp_frame, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
mux8 mux_pwr_oe1 (major_mode, pwr_oe1, lr_pwr_oe1, le_pwr_oe1, lp_pwr_oe1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
mux8 mux_pwr_oe2 (major_mode, pwr_oe2, lr_pwr_oe2, le_pwr_oe2, lp_pwr_oe2, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
mux8 mux_pwr_oe3 (major_mode, pwr_oe3, lr_pwr_oe3, le_pwr_oe3, lp_pwr_oe3, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
mux8 mux_pwr_oe4 (major_mode, pwr_oe4, lr_pwr_oe4, le_pwr_oe4, lp_pwr_oe4, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
mux8 mux_pwr_lo (major_mode, pwr_lo, lr_pwr_lo, le_pwr_lo, lp_pwr_lo, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
mux8 mux_pwr_hi (major_mode, pwr_hi, lr_pwr_hi, le_pwr_hi, lp_pwr_hi, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
mux8 mux_adc_clk (major_mode, adc_clk, lr_adc_clk, le_adc_clk, lp_adc_clk, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
mux8 mux_dbg (major_mode, dbg, lr_dbg, le_dbg, lp_dbg, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
// In all modes, let the ADC's outputs be enabled.
assign adc_noe = 1'b0;
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module alt_mem_ddrx_ecc_decoder #
( parameter
CFG_DATA_WIDTH = 40,
CFG_ECC_CODE_WIDTH = 8,
CFG_ECC_DEC_REG = 1,
CFG_ECC_RDATA_REG = 0,
CFG_MMR_DRAM_DATA_WIDTH = 7,
CFG_MMR_LOCAL_DATA_WIDTH = 7,
CFG_PORT_WIDTH_ENABLE_ECC = 1
)
(
ctl_clk,
ctl_reset_n,
cfg_local_data_width,
cfg_dram_data_width,
cfg_enable_ecc,
input_data,
input_data_valid,
output_data,
output_data_valid,
output_ecc_code,
err_corrected,
err_detected,
err_fatal
);
localparam CFG_ECC_DATA_WIDTH = (CFG_DATA_WIDTH > 8) ? (CFG_DATA_WIDTH - CFG_ECC_CODE_WIDTH) : (CFG_DATA_WIDTH);
input ctl_clk;
input ctl_reset_n;
input [CFG_MMR_DRAM_DATA_WIDTH - 1 : 0] cfg_local_data_width;
input [CFG_MMR_LOCAL_DATA_WIDTH - 1 : 0] cfg_dram_data_width;
input [CFG_PORT_WIDTH_ENABLE_ECC - 1 : 0] cfg_enable_ecc;
input [CFG_DATA_WIDTH - 1 : 0] input_data;
input input_data_valid;
output [CFG_DATA_WIDTH - 1 : 0] output_data;
output output_data_valid;
output [CFG_ECC_CODE_WIDTH - 1 : 0] output_ecc_code;
output err_corrected;
output err_detected;
output err_fatal;
//--------------------------------------------------------------------------------------------------------
//
// [START] Register & Wires
//
//--------------------------------------------------------------------------------------------------------
reg [CFG_DATA_WIDTH - 1 : 0] int_decoder_input;
reg [CFG_DATA_WIDTH - 1 : 0] int_decoder_input_data;
reg [CFG_DATA_WIDTH - 1 : 0] int_decoder_input_ecc_code;
reg [CFG_DATA_WIDTH - 1 : 0] or_int_decoder_input_ecc_code;
reg [CFG_DATA_WIDTH - 1 : 0] output_data;
reg output_data_valid;
reg [CFG_ECC_CODE_WIDTH - 1 : 0] output_ecc_code;
reg err_corrected;
reg err_detected;
reg err_fatal;
wire int_err_corrected;
wire int_err_detected;
wire int_err_fatal;
reg [CFG_ECC_CODE_WIDTH - 1 : 0] int_output_ecc_code;
wire [CFG_DATA_WIDTH - 1 : 0] decoder_input;
wire [CFG_ECC_DATA_WIDTH - 1 : 0] decoder_output;
reg decoder_output_valid;
reg [CFG_ECC_DATA_WIDTH - 1 : 0] decoder_output_r;
reg decoder_output_valid_r;
reg int_err_corrected_r;
reg int_err_detected_r;
reg int_err_fatal_r;
reg [CFG_ECC_CODE_WIDTH - 1 : 0] int_output_ecc_code_r;
wire zero = 1'b0;
//--------------------------------------------------------------------------------------------------------
//
// [END] Register & Wires
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Common Logic
//
//--------------------------------------------------------------------------------------------------------
// Input data splitting/masking logic:
// change
// <Empty data> - <ECC code> - <Data>
// into
// <ECC code> - <Empty data> - <Data>
generate
genvar i_data;
for (i_data = 0;i_data < CFG_DATA_WIDTH;i_data = i_data + 1)
begin : decoder_input_per_data_width
always @ (*)
begin
int_decoder_input_data [i_data] = input_data [i_data];
end
end
endgenerate
generate
if (CFG_ECC_RDATA_REG)
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_decoder_input <= 0;
end
else
begin
int_decoder_input <= int_decoder_input_data;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
decoder_output_valid <= 0;
end
else
begin
decoder_output_valid <= input_data_valid;
end
end
end
else
begin
always @ (*)
begin
int_decoder_input = int_decoder_input_data;
end
always @ (*)
begin
decoder_output_valid = input_data_valid;
end
end
endgenerate
// Decoder input assignment
assign decoder_input = int_decoder_input;
// Decoder output, registered
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
decoder_output_r <= {CFG_ECC_DATA_WIDTH{1'b0}};
decoder_output_valid_r <= 1'b0;
int_err_corrected_r <= 1'b0;
int_err_detected_r <= 1'b0;
int_err_fatal_r <= 1'b0;
int_output_ecc_code_r <= {CFG_ECC_CODE_WIDTH{1'b0}};
end
else
begin
decoder_output_r <= decoder_output;
decoder_output_valid_r <= decoder_output_valid;
int_err_corrected_r <= int_err_corrected;
int_err_detected_r <= int_err_detected;
int_err_fatal_r <= int_err_fatal;
int_output_ecc_code_r <= int_output_ecc_code;
end
end
// Decoder output ecc code
generate
if (CFG_DATA_WIDTH <= 8)
begin
// No support for ECC case
always @ (*)
begin
int_output_ecc_code = {CFG_ECC_CODE_WIDTH{zero}};
end
end
else
begin
always @ (*)
begin
if (cfg_enable_ecc)
int_output_ecc_code = int_decoder_input_data [CFG_DATA_WIDTH - 1 : CFG_ECC_DATA_WIDTH];
else
int_output_ecc_code = 0;
end
end
endgenerate
// Decoder wrapper output assignment
generate
begin : gen_decoder_output_reg_select
if (CFG_ECC_DEC_REG)
begin
always @ (*)
begin
if (cfg_enable_ecc)
begin
output_data = {{CFG_ECC_CODE_WIDTH{1'b0}}, decoder_output_r}; // Assign '0' to ECC code portions
output_data_valid = decoder_output_valid_r;
err_corrected = int_err_corrected_r;
err_detected = int_err_detected_r;
err_fatal = int_err_fatal_r;
output_ecc_code = int_output_ecc_code_r;
end
else
begin
output_data = input_data;
output_data_valid = input_data_valid;
err_corrected = 1'b0;
err_detected = 1'b0;
err_fatal = 1'b0;
output_ecc_code = int_output_ecc_code;
end
end
end
else
begin
always @ (*)
begin
if (cfg_enable_ecc)
begin
output_data = {{CFG_ECC_CODE_WIDTH{1'b0}}, decoder_output}; // Assign '0' to ECC code portions
output_data_valid = decoder_output_valid;
err_corrected = int_err_corrected;
err_detected = int_err_detected;
err_fatal = int_err_fatal;
output_ecc_code = int_output_ecc_code;
end
else
begin
output_data = input_data;
output_data_valid = input_data_valid;
err_corrected = 1'b0;
err_detected = 1'b0;
err_fatal = 1'b0;
output_ecc_code = int_output_ecc_code;
end
end
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Common Logic
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Instantiation
//
//--------------------------------------------------------------------------------------------------------
generate
begin
if (CFG_ECC_DATA_WIDTH == 8 && CFG_DATA_WIDTH > 8) // Make sure this is an ECC case else it will cause compilation error
begin
wire [39 : 0] int_decoder_input;
wire [32 : 0] int_decoder_output;
// Assign decoder output
assign int_decoder_input = {decoder_input [CFG_DATA_WIDTH - 1 : CFG_ECC_DATA_WIDTH], 24'd0, decoder_input [CFG_ECC_DATA_WIDTH - 1 : 0]};
// Assign decoder output
assign decoder_output = int_decoder_output [CFG_ECC_DATA_WIDTH - 1 : 0];
// 32/39 bit decoder instantiation
alt_mem_ddrx_ecc_decoder_32 decoder_inst
(
.data (int_decoder_input [38 : 0]),
.err_corrected (int_err_corrected ),
.err_detected (int_err_detected ),
.err_fatal (int_err_fatal ),
.q (int_decoder_output )
);
end
else if (CFG_ECC_DATA_WIDTH == 16)
begin
wire [39 : 0] int_decoder_input;
wire [32 : 0] int_decoder_output;
// Assign decoder output
assign int_decoder_input = {decoder_input [CFG_DATA_WIDTH - 1 : CFG_ECC_DATA_WIDTH], 16'd0, decoder_input [CFG_ECC_DATA_WIDTH - 1 : 0]};
// Assign decoder output
assign decoder_output = int_decoder_output [CFG_ECC_DATA_WIDTH - 1 : 0];
// 32/39 bit decoder instantiation
alt_mem_ddrx_ecc_decoder_32 decoder_inst
(
.data (int_decoder_input [38 : 0]),
.err_corrected (int_err_corrected ),
.err_detected (int_err_detected ),
.err_fatal (int_err_fatal ),
.q (int_decoder_output )
);
end
else if (CFG_ECC_DATA_WIDTH == 32)
begin
// 32/39 bit decoder instantiation
alt_mem_ddrx_ecc_decoder_32 decoder_inst
(
.data (decoder_input [38 : 0]),
.err_corrected (int_err_corrected ),
.err_detected (int_err_detected ),
.err_fatal (int_err_fatal ),
.q (decoder_output )
);
end
else if (CFG_ECC_DATA_WIDTH == 64)
begin
// 32/39 bit decoder instantiation
alt_mem_ddrx_ecc_decoder_64 decoder_inst
(
.data (decoder_input ),
.err_corrected (int_err_corrected),
.err_detected (int_err_detected ),
.err_fatal (int_err_fatal ),
.q (decoder_output )
);
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Instantiation
//
//--------------------------------------------------------------------------------------------------------
endmodule
|
/*+--------------------------------------------------------------------------
Copyright (c) 2015, Microsoft Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
//////////////////////////////////////////////////////////////////////////////////
// Company: Microsoft Research Asia
// Engineer: Jiansong Zhang
//
// Create Date: 21:39:39 06/01/2009
// Design Name:
// Module Name: tx_trn_sm
// Project Name: Sora
// Target Devices: Virtex5 LX50T
// Tool versions: ISE10.1.03
// Description:
// Purpose: Transmit TRN State Machine module. Interfaces to the Endpoint
// Block Plus and transmits packtets out of the TRN interface. Drains the
// packets out of FIFOs.
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// Modified by jiansong zhang, 2009-6-18
// (1) delete dma write done generation logic -------------- done
// (2) modification on scheduling
// (3) register/memory read logic -------------------------- done
//
// semiduplex scheduling to slove possible interlock problem on
// north-bridge/memory-controller
// (1) add np_tx_cnt logic --------------------------------- done
// (2) add np_rx_cnt input
// (3) scheduling: if ( (np_tx_cnt == np_rx_cnt) && (p_hdr_fifo != empty) )
// send p packets;
// else if (np_hdr_fifo != empty)
// send np packets;
// else if (cmp_hdr_fifo != empty)
// send cmp packets;
// else
// IDLE;
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
`include "Sora_config.v"
module tx_trn_sm(
input clk,
input rst_in,
input hostreset_in,
output rst_out,
//interface to the header fifos
input [63:0] posted_hdr_fifo,
output posted_hdr_fifo_rden,
input posted_hdr_fifo_empty,
input [63:0] nonposted_hdr_fifo,
output nonposted_hdr_fifo_rden,
input nonposted_hdr_fifo_empty,
input [63:0] comp_hdr_fifo,
input comp_hdr_fifo_empty,
output comp_hdr_fifo_rden,
/// Jiansong: posted_data_fifo interface
output reg posted_data_fifo_rden,
input [63:0] posted_data_fifo_data,
// it's used, data fifo should not be empty when it is read
input posted_data_fifo_empty,
/// Jiansong: interface for Mrd, connect to dma control wrapper, don't need request/ack handshake
output reg[11:0] Mrd_data_addr, /// Jiansong: 12 bits register address
input [31:0] Mrd_data_in,
//interface to PCIe Endpoint Block Plus TX TRN
output reg [63:0] trn_td,
output reg [7:0] trn_trem_n,
output reg trn_tsof_n,
output reg trn_teof_n,
output trn_tsrc_rdy_n,
output trn_tsrc_dsc_n,
input trn_tdst_rdy_n,//if this signal is deasserted (high) must pause all
//activity to the TX TRN interface. This signal is
//used as a clock enable to much of the circuitry
//in this module
input trn_tdst_dsc_n,//destination should not discontinue - Endpoint Block
//Plus V1.6.1 does not support this signal
output trn_terrfwd_n,
input [2:0] trn_tbuf_av,
/// Jiansong: input from rx_monitor
input [9:0] np_rx_cnt_qw,
input transferstart,
input Wait_for_TX_desc,
input rd_dma_start, //indicates the start of a read dma xfer
input [12:3] dmarxs, //size of the complete transfer
// debug interface
output reg [31:0] Debug21RX2,
output reg [31:0] Debug25RX6
);
//state machine state definitions for state[19:0]
localparam IDLE = 21'b0_0000_0000_0000_0000_0000;
localparam GET_P_HD = 21'b0_0000_0000_0000_0000_0001;
localparam GET_NP_HD = 21'b0_0000_0000_0000_0000_0010;
localparam GET_COMP_HD = 21'b0_0000_0000_0000_0000_0100;
localparam SETUP_P_DATA = 21'b0_0000_0000_0000_0000_1000;
//// localparam WAIT_FOR_DATA_RDY = 20'b0000_0000_0000_0010_0000;
localparam P_WAIT_STATE = 21'b0_0000_0000_0000_0001_0000;
localparam P_WAIT_STATE1 = 21'b0_0000_0000_0000_0010_0000;
localparam HD1_P_XFER = 21'b0_0000_0000_0000_0100_0000;
localparam HD2_P_XFER = 21'b0_0000_0000_0000_1000_0000;
localparam DATA_P_XFER = 21'b0_0000_0000_0001_0000_0000;
localparam LAST_P_XFER = 21'b0_0000_0000_0010_0000_0000;
localparam SETUP_NP = 21'b0_0000_0000_0100_0000_0000;
localparam SETUP_COMP_DATA = 21'b0_0000_0000_1000_0000_0000;
localparam SETUP_COMP_DATA_WAIT1 = 21'b0_0000_0001_0000_0000_0000;
localparam SETUP_COMP_DATA_WAIT2 = 21'b0_0000_0010_0000_0000_0000;
localparam HD1_NP_XFER = 21'b0_0000_0100_0000_0000_0000;
localparam HD2_NP_XFER = 21'b0_0000_1000_0000_0000_0000;
localparam NP_WAIT_STATE = 21'b0_0001_0000_0000_0000_0000;
localparam WAIT_FOR_COMP_DATA_RDY = 21'b0_0010_0000_0000_0000_0000;
localparam HD1_COMP_XFER = 21'b0_0100_0000_0000_0000_0000;
localparam HD2_COMP_XFER = 21'b0_1000_0000_0000_0000_0000;
localparam NP_XFER_WAIT = 21'b1_0000_0000_0000_0000_0000;
//states for addsub_state
localparam AS_IDLE = 2'b00;
localparam REGISTER_CALC = 2'b01;
localparam WAIT_FOR_REG = 2'b10;
reg [1:0] addsub_state;
//header fifo signals
reg read_posted_header_fifo, read_posted_header_fifo_d1,
read_posted_header_fifo_d2;
reg read_non_posted_header_fifo, read_non_posted_header_fifo_d1,
read_non_posted_header_fifo_d2;
reg read_comp_header_fifo, read_comp_header_fifo_d1,
read_comp_header_fifo_d2;
wire p_trn_fifo_rdy, np_trn_fifo_rdy;
//holding registers for TLP headers
reg [63:0] p_hd1, p_hd2; //posted headers 1 and 2
reg [63:0] np_hd1, np_hd2; //non-posted headers 1 and 2
reg [63:0] comp_hd1, comp_hd2; //completer headers 1 and 2
//datapath registers
reg [31:0] data_reg;
reg [9:0] length_countdown;
wire [63:0] data_swap;
/// Jiansong: swap register data
wire [31:0] Mrd_data_swap;
//decoded TLP signals - mainly used for code comprehension
wire [1:0] p_fmt;
wire [2:0] p_tc;
wire [9:0] p_length;
wire [1:0] np_fmt;
wire [2:0] np_tc;
wire [9:0] np_length;
////reg p_hd_valid; /// Jiansong: no longer needed
//main state machine signals
reg [20:0] state;
////reg posted; //asserted when the state machine is in the posted flow
//// //used to qualify the data_stall signal as a CE for many of
//// //the blocks that aren't related to the DDR2
reg [1:0] data_src_mux;
reg trn_tsrc_rdy_n_reg;
reg [3:0] priority_count = 4'b1111;
wire posted_priority;
/// Jiansong: pipeline register for a complicated problem when trn_tdst_rdy_n is asserted
reg trn_tdst_rdy_n_r2;
reg [63:0] data_reg_tdst_problem;
reg trn_tdst_rdy_n_r;
reg rst_reg;
/// Jiansong: non_posted_length_counter
reg add_calc = 0;
reg sub_calc = 0;
reg add_complete;
reg sub_complete;
reg [9:0] np_tx_cnt_qw;
reg [9:0] np_tx_cnt_qw_new;
reg [9:0] np_tx_cnt_qw_add;
reg update_np_tx_cnt_qw;
reg stay_2x;
/// Jiansong:
wire rd_dma_start_one;
reg rd_dma_start_reg;
rising_edge_detect rd_dma_start_one_inst(
.clk(clk),
.rst(rst_reg),
.in(rd_dma_start_reg),
.one_shot_out(rd_dma_start_one)
);
//pipe line register for timing purposes
always@(posedge clk)
rd_dma_start_reg <= rd_dma_start;
`ifdef sora_simulation
always@(posedge clk) rst_reg <= rst_in;
`else
always@(posedge clk) begin
if(state == IDLE)
rst_reg <= rst_in | hostreset_in;
else
rst_reg <= 1'b0;
end
`endif
assign rst_out = rst_reg;
// debug register
always@(posedge clk)begin
Debug21RX2[19:0] <= state[19:0];
Debug21RX2[29:20] <= length_countdown[9:0];
Debug21RX2[31:30] <= 2'b00;
end
always@(posedge clk)begin
if (rst_reg)
Debug25RX6 <= 32'h0000_0000;
else if (posted_data_fifo_rden)
Debug25RX6 <= Debug25RX6 + 32'h0000_0001;
else
Debug25RX6 <= Debug25RX6;
end
//tie off to pcie trn tx
assign trn_tsrc_dsc_n = 1'b1; /// Jiansong: transmit source discontinue
assign trn_terrfwd_n = 1'b1; /// Jiansong: error?
//if there is a data_stall need to pause the TX TRN interface
////assign trn_tsrc_rdy_n = (data_stall & posted) | trn_tsrc_rdy_n_reg;
assign trn_tsrc_rdy_n = trn_tsrc_rdy_n_reg;
/// Jiansong: need modification? big-endian for 64 bit data? Don't modify
// swap byte ordering of data to big-endian per PCIe Base spec
////assign data_swap[63:0] = {data[7:0],data[15:8],
//// data[23:16],data[31:24],
//// data[39:32],data[47:40],
//// data[55:48],data[63:56]};
assign data_swap[63:0] = {posted_data_fifo_data[7:0],posted_data_fifo_data[15:8],
posted_data_fifo_data[23:16],posted_data_fifo_data[31:24],
posted_data_fifo_data[39:32],posted_data_fifo_data[47:40],
posted_data_fifo_data[55:48],posted_data_fifo_data[63:56]};
////assign data_swap[63:0] = {posted_data_fifo_data[39:32],posted_data_fifo_data[47:40],
//// posted_data_fifo_data[55:48],posted_data_fifo_data[63:56],
//// posted_data_fifo_data[7:0],posted_data_fifo_data[15:8],
//// posted_data_fifo_data[23:16],posted_data_fifo_data[31:24]};
/// Jiansong: swap register read / memory read data
assign Mrd_data_swap[31:0] = {Mrd_data_in[7:0],Mrd_data_in[15:8],
Mrd_data_in[23:16],Mrd_data_in[31:24]};
// output logic from statemachine that controls read of the posted packet fifo
// read the two headers from the posted fifo and store in registers
// the signal that kicks off the read is a single-cycle signal from
// the state machine
// read_posted_header_fifo
always@(posedge clk)begin
if(rst_reg)begin
read_posted_header_fifo_d1 <= 1'b0;
read_posted_header_fifo_d2 <= 1'b0;
//// end else if(~trn_tdst_rdy_n & ~data_stall)begin
// end else if(~trn_tdst_rdy_n)begin
end else begin
/// Jiansong: pipeline the fifo rden signal
read_posted_header_fifo_d1 <= read_posted_header_fifo;
read_posted_header_fifo_d2 <= read_posted_header_fifo_d1;
end
end
//stretch read enable to two clocks and qualify with trn_tdst_rdy_n
assign posted_hdr_fifo_rden = (read_posted_header_fifo_d1
| read_posted_header_fifo);
// & ~trn_tdst_rdy_n;
//// & ~trn_tdst_rdy_n
//// & ~data_stall;
// use the read enable signals to enable registers p_hd1 and p_hd2
always@(posedge clk)begin
if(rst_reg)begin
p_hd1[63:0] <= 64'h0000000000000000;
//// end else if(~trn_tdst_rdy_n & ~data_stall)begin
// end else if(~trn_tdst_rdy_n) begin
end else begin
if(read_posted_header_fifo_d1)begin
p_hd1 <= posted_hdr_fifo;
end else begin
p_hd1 <= p_hd1;
end
end
end
always@(posedge clk)begin
if(rst_reg)begin
p_hd2[63:0] <= 64'h0000000000000000;
//// end else if(~trn_tdst_rdy_n & ~data_stall)begin
// end else if(~trn_tdst_rdy_n)begin
end else begin
if(read_posted_header_fifo_d2)begin
p_hd2 <= posted_hdr_fifo;
end else begin
p_hd2 <= p_hd2;
end
end
end
//assign signals for reading clarity
assign p_fmt[1:0] = p_hd1[62:61]; //format field
assign p_tc[2:0] = p_hd1[54:52]; //traffic class field
assign p_length[9:0] = p_hd1[41:32]; //DW length field
assign p_trn_fifo_rdy = trn_tbuf_av[1];
// output logic from statemachine that controls read of the
// non_posted packet fifo
// read the two headers from the non posted fifo and store in registers
// the signal that kicks off the read is a single-cycle signal from the
// state machine
// read_posted_header_fifo
always@(posedge clk)begin
if(rst_reg)begin
read_non_posted_header_fifo_d1 <= 1'b0;
read_non_posted_header_fifo_d2 <= 1'b0;
// end else if(~trn_tdst_rdy_n) begin
end else begin
/// Jiansong: pipeline the fifo rden signal
read_non_posted_header_fifo_d1 <= read_non_posted_header_fifo;
read_non_posted_header_fifo_d2 <= read_non_posted_header_fifo_d1;
end
end
//stretch read enable to two clocks and qualify with trn_tdst_rdy_n
assign nonposted_hdr_fifo_rden = (read_non_posted_header_fifo_d1
| read_non_posted_header_fifo);
// & ~trn_tdst_rdy_n;
// use the read enable signals to enable registers np_hd1 and np_hd2
always@(posedge clk)begin
if(rst_reg)begin
np_hd1[63:0] <= 64'h0000000000000000;
// end else if(~trn_tdst_rdy_n)begin
end else begin
if(read_non_posted_header_fifo_d1)begin
np_hd1 <= nonposted_hdr_fifo;
end else begin
np_hd1 <= np_hd1;
end
end
end
always@(posedge clk)begin
if(rst_reg)begin
np_hd2[63:0] <= 64'h0000000000000000;
// end else if(~trn_tdst_rdy_n)begin
end else begin
if(read_non_posted_header_fifo_d2)begin
np_hd2 <= nonposted_hdr_fifo;
end else begin
np_hd2 <= np_hd2;
end
end
end
//assign signals for reading clarity
assign np_fmt[1:0] = np_hd1[62:61]; //format field
assign np_tc[2:0] = np_hd1[54:52]; //traffic class field
assign np_length[9:0] = np_hd1[41:32]; //DW length field
assign np_trn_fifo_rdy = trn_tbuf_av[0];
// output logic from statemachine that controls read of the comp packet fifo
// read the two headers from the comp fifo and store in registers
// the signal that kicks off the read is a single-cycle signal from
// the state machine
// read_comp_header_fifo
always@(posedge clk)begin
if(rst_reg)begin
read_comp_header_fifo_d1 <= 1'b0;
read_comp_header_fifo_d2 <= 1'b0;
//// end else if(~trn_tdst_rdy_n & (~data_stall | ~posted))begin
// end else if(~trn_tdst_rdy_n)begin /// pending
end else begin
read_comp_header_fifo_d1 <= read_comp_header_fifo;
read_comp_header_fifo_d2 <= read_comp_header_fifo_d1;
end
end
//stretch read enable to two clocks and qualify with trn_tdst_rdy_n
assign comp_hdr_fifo_rden = (read_comp_header_fifo_d1
| read_comp_header_fifo);
// & ~trn_tdst_rdy_n;
// use the read enable signals to enable registers comp_hd1 and comp_hd2
always@(posedge clk)begin
if(rst_reg)begin
comp_hd1[63:0] <= 64'h0000000000000000;
//// end else if(~trn_tdst_rdy_n & (~data_stall | ~posted))begin
// end else if(~trn_tdst_rdy_n)begin /// pending
end else begin
if(read_comp_header_fifo_d1)begin
comp_hd1 <= comp_hdr_fifo;
end else begin
comp_hd1 <= comp_hd1;
end
end
end
always@(posedge clk)begin
if(rst_reg)begin
comp_hd2[63:0] <= 64'h0000000000000000;
//// end else if(~trn_tdst_rdy_n & (~data_stall | ~posted))begin
// end else if(~trn_tdst_rdy_n)begin /// pending
end else begin
if(read_comp_header_fifo_d2)begin
comp_hd2 <= comp_hdr_fifo;
end else begin
comp_hd2 <= comp_hd2;
end
end
end
assign comp_trn_fifo_rdy = trn_tbuf_av[2];
//encode data_src
//reg_file = BAR_HIT[6:0] = 0000001 -> 01
//ROM_BAR = BAR_HIT[6:0] = 1000000 -> 10
//DDR2 -> 00 no need to decode as DDR2 not supported as a PCIe target
always@(*)begin //// Jiansong: no clock driven, or whatever clock driven
case(comp_hd1[63:57])
7'b0000001: data_src_mux[1:0] <= 2'b01;
7'b1000000: data_src_mux[1:0] <= 2'b10;
//// default: data_src_mux[1:0] <= 2'b00;
default: data_src_mux[1:0] <= 2'b01;
endcase
end
/// Jiansong: pending
//countdown to control amount of data tranfer in state machine
//count in quadwords since trn_td is 64-bits
always@(posedge clk)begin
if(rst_reg)
length_countdown <= 10'b00_0000_0000;
//// else if (~trn_tdst_rdy_n & ~data_stall)begin
else if (~trn_tdst_rdy_n)begin
if(state == HD1_P_XFER)
length_countdown <= p_length>>1; //count in quadwords
else if(length_countdown != 0)
length_countdown <= length_countdown - 1;
end else
length_countdown <= length_countdown;
end
//data_xfer is a state machine output that tells the egress_data_presenter
// to transfer data; every clock cycle it is asserted one 64-bit data
// is valid on the next cycle - unless data_stall is asserted
////assign data_xfer = data_xfer_reg;
// data steering logic
always@(posedge clk)begin
if(rst_reg)begin
// data_reg <= 64'h0000000000000000;
data_reg[31:0] <= 32'h0000_0000;
//// end else if(~trn_tdst_rdy_n & (~data_stall | ~posted)) begin
end else if(~trn_tdst_rdy_n) begin
data_reg[31:0] <= data_swap[31:0];
end
end
/// Jiansong: this register is added the rden delay problem when trn_tdst_rdy_n is deasserted
always@(posedge clk)begin
if(rst_reg)begin
data_reg_tdst_problem <= 64'h0000000000000000;
end else if(~trn_tdst_rdy_n_r)begin
data_reg_tdst_problem <= data_swap;
end
end
//mux the trn_td[63:0] - dependent on what state the main state machine is in
always@(posedge clk)begin
if(rst_reg)
trn_td <= 0;
//// else if(~trn_tdst_rdy_n & (~data_stall | ~posted))begin
else if(~trn_tdst_rdy_n)begin
casex({state,p_fmt[0]})
{HD1_P_XFER,1'bx}: begin
trn_td <= p_hd1;
end
{HD2_P_XFER,1'b0}: begin
if(trn_tdst_rdy_n_r) /// Jiansong:
trn_td <= {p_hd2[63:32],data_reg_tdst_problem[63:32]};
else
trn_td <= {p_hd2[63:32],data_swap[63:32]};
end
{HD2_P_XFER,1'b1}: begin
trn_td <= p_hd2[63:0];
end
{DATA_P_XFER,1'b0},{LAST_P_XFER,1'b0}: begin
if(trn_tdst_rdy_n_r) /// Jiansong:
trn_td[63:0] <= {data_reg[31:0],data_reg_tdst_problem[63:32]};
else if(trn_tdst_rdy_n_r2)
trn_td[63:0] <= {data_reg_tdst_problem[31:0],data_swap[63:32]};
else
trn_td[63:0] <= {data_reg[31:0],data_swap[63:32]};
end
{DATA_P_XFER,1'b1},{LAST_P_XFER,1'b1}: begin
if(trn_tdst_rdy_n_r) /// Jiansong:
trn_td[63:0] <= data_reg_tdst_problem[63:0];
else
trn_td[63:0] <= data_swap[63:0];
end
{HD1_NP_XFER,1'bx}: begin
trn_td <= np_hd1;
end
{HD2_NP_XFER,1'bx}: begin
trn_td <= np_hd2;
end
{HD1_COMP_XFER,1'bx}: begin
trn_td <= {comp_hd1[31:0],comp_hd2[63:32]};
end
{HD2_COMP_XFER,1'bx}: begin
//// trn_td <= {comp_hd2[31:0],data_reg[63:32]};
/// Jiansong: rom_bar, keep the old design, but don't know what's it for
if (data_src_mux[1:0] == 2'b10) begin
trn_td <= {comp_hd2[31:0],32'h00000000};
end else if (data_src_mux[1:0] == 2'b01) begin
trn_td <= {comp_hd2[31:0],Mrd_data_swap};
end else begin
trn_td <= {comp_hd2[31:0],Mrd_data_swap};
end
end
default: begin
trn_td <= 0;
end
endcase
end
end
/// Jiansong: priority is modified
/// in sora, round-robin will be used for posted, non-posted
/// and completion scheduling
//////Priority signal for posted and non-posted requests
//////When operating in full duplex mode the state machine
//////will do 8 posted requests followed by 8 non-posted requests
//////Note: this ordering assumes that the posted and non-posted
//////requests do not depend on each other.
//////Once inside the V-5 PCIe Block, strict ordering will be
//////followed. Also, note that completions are given
//////lowest priority. In order to avoid completion time-outs,
//////read requests from the host should not occur during a DMA
//////transaction.
//////If this is not possible, than the completion queue may need
//////higher priority.
/// Jiansong: pipeline registers
always@(posedge clk)begin
trn_tdst_rdy_n_r2 <= trn_tdst_rdy_n_r;
trn_tdst_rdy_n_r <= trn_tdst_rdy_n;
end
// bulk of TX TRN state machine
always@(posedge clk)begin
// if(rst_in)begin
if(rst_reg)begin
trn_tsrc_rdy_n_reg <= 1'b1;
trn_tsof_n <= 1'b1;
trn_teof_n <= 1'b1;
trn_trem_n[7:0] <= 8'b11111111;
posted_data_fifo_rden <= 1'b0;
read_posted_header_fifo <= 1'b0;
read_non_posted_header_fifo <= 1'b0;
read_comp_header_fifo <= 1'b0;
state <= IDLE;
//// //use trn_tdst_rdy_n and data_stall as clock enable - for data_stall
//// //only CE if in the posted flow
//// end else if(~trn_tdst_rdy_n & (~data_stall | ~posted))begin
// use trn_tdst_rdy_n as clock enable
end else if(trn_tdst_rdy_n)begin
// if(trn_tdst_rdy_n)begin
/// Jiansong: deassert the rden, write enable signals if PCIe core is not ready
posted_data_fifo_rden <= 1'b0;
read_posted_header_fifo <= 1'b0;
read_non_posted_header_fifo <= 1'b0;
read_comp_header_fifo <= 1'b0;
//// end else if(~trn_tdst_rdy_n)begin
end else begin
case(state)
IDLE: begin
if (hostreset_in) begin
trn_tsrc_rdy_n_reg <= 1'b1;
trn_tsof_n <= 1'b1;
trn_teof_n <= 1'b1;
trn_trem_n[7:0] <= 8'b11111111;
posted_data_fifo_rden <= 1'b0;
read_posted_header_fifo <= 1'b0;
read_non_posted_header_fifo <= 1'b0;
read_comp_header_fifo <= 1'b0;
state <= IDLE;
end else begin
trn_tsrc_rdy_n_reg <= 1'b1;
trn_tsof_n <= 1'b1;
trn_teof_n <= 1'b1;
trn_trem_n[7:0] <= 8'b11111111;
posted_data_fifo_rden <= 1'b0;
read_posted_header_fifo <= 1'b0;
read_non_posted_header_fifo <= 1'b0;
read_comp_header_fifo <= 1'b0;
if ( (np_rx_cnt_qw == np_tx_cnt_qw) && (~posted_hdr_fifo_empty) && ~Wait_for_TX_desc)
state <= GET_P_HD;
else if (~nonposted_hdr_fifo_empty)
state <= GET_NP_HD;
else if (~comp_hdr_fifo_empty)
state <= GET_COMP_HD;
else
state <= IDLE;
end
end
GET_P_HD: begin
read_posted_header_fifo <= 1'b1; //get the headers ready
trn_tsrc_rdy_n_reg <= 1'b1;
trn_trem_n[7:0] <= 8'b11111111;
trn_teof_n <= 1'b1;
state <= SETUP_P_DATA;
end
GET_NP_HD: begin
read_non_posted_header_fifo <= 1'b1; //get the headers ready
trn_tsrc_rdy_n_reg <= 1'b1;
trn_trem_n[7:0] <= 8'b11111111;
trn_teof_n <= 1'b1;
state <= SETUP_NP;
end
GET_COMP_HD: begin
read_comp_header_fifo <= 1'b1; //get the headers ready
trn_tsrc_rdy_n_reg <= 1'b1;
trn_trem_n[7:0] <= 8'b11111111;
trn_teof_n <= 1'b1;
state <= SETUP_COMP_DATA_WAIT1;
end
/// Jiansong: pending, make it simpler
//start of completer transaction flow
SETUP_COMP_DATA_WAIT1: begin //wait state for comp_hd1
read_comp_header_fifo <= 1'b0;
state <= SETUP_COMP_DATA_WAIT2;
end
SETUP_COMP_DATA_WAIT2: begin //wait state for comp_hd2
state <= SETUP_COMP_DATA;
end
SETUP_COMP_DATA: begin
Mrd_data_addr[11:0] <= {comp_hd1[41:32],2'b00};
if(comp_trn_fifo_rdy)//make sure the completion fifo in the PCIe
//block is ready
state <= WAIT_FOR_COMP_DATA_RDY;
else
state <= SETUP_COMP_DATA;
end
/// Jiansong: wait one more cycle for reg data ready, maybe not necessary
WAIT_FOR_COMP_DATA_RDY: begin
state <= HD1_COMP_XFER;
end
HD1_COMP_XFER: begin //transfer first header
trn_tsof_n <= 1'b0;
trn_tsrc_rdy_n_reg <= 1'b0;
trn_trem_n[7:0] <= 8'b00000000;
state <= HD2_COMP_XFER;
end
HD2_COMP_XFER: begin //transfer second header + 1 DW of data
trn_tsrc_rdy_n_reg <= 1'b0;
trn_tsof_n <= 1'b1;
trn_teof_n <= 1'b0;
state <= IDLE;
end
//start of posted transaction flow
SETUP_P_DATA: begin
read_posted_header_fifo <= 1'b0;
posted_data_fifo_rden <= 1'b0;
state <= P_WAIT_STATE;
end
P_WAIT_STATE : begin /// Jiansong: wait one more cycle for hdr ready
read_posted_header_fifo <= 1'b0;
posted_data_fifo_rden <= 1'b0;
state <= P_WAIT_STATE1;
end
P_WAIT_STATE1 : begin
//wait for the egress data_presenter to have data ready then start
//transmitting the first posted header
trn_teof_n <= 1'b1;
if(p_trn_fifo_rdy & ~posted_data_fifo_empty) begin //make sure posted fifo in PCIe block is ready
/// Jiansong: read data fifo?
if(p_fmt[0] == 0)begin //3DW
posted_data_fifo_rden <= 1'b1;
end else begin //4DW
posted_data_fifo_rden <= 1'b0;
end
state <= HD1_P_XFER;
end else begin
posted_data_fifo_rden <= 1'b0;
state <= P_WAIT_STATE1;
end
end
HD1_P_XFER: begin //transfer first header
trn_tsof_n <= 1'b0; //assert SOF
trn_teof_n <= 1'b1;
trn_tsrc_rdy_n_reg <= 1'b0;
trn_trem_n[7:0] <= 8'b00000000;
posted_data_fifo_rden <= 1'b1;
state <= HD2_P_XFER;
end
HD2_P_XFER: begin //transfer second header (+1 DW of data for 3DW)
trn_tsrc_rdy_n_reg <= 1'b0;
trn_tsof_n <= 1'b1; //deassert SOF
/// Jiansong: RX desc is so short (2 cycles) that we need specially consider it
if (p_fmt[0] == 0 && p_length <= 10'h004)
posted_data_fifo_rden <= 1'b0;
else
posted_data_fifo_rden <= 1'b1;
state <= DATA_P_XFER;
end
// DATA_P_XFER state for packets with more than 1 DW
// for this design the next step up will always be 128B or 32DW
DATA_P_XFER: begin
trn_tsrc_rdy_n_reg <= 1'b0;
//use a counter to figure out when we are almost done and
//jump to LAST_P_XFER when we reach the penultimate data cycle
if(length_countdown != 1)begin
state <= DATA_P_XFER;
end else begin
state <= LAST_P_XFER;
end
//figure out when to deassert data_xfer_reg based on whether
//this a 3DW or 4DW header posted TLP
if(p_fmt[0] == 0)begin //3DW case
if(length_countdown <=2)
posted_data_fifo_rden <= 1'b0;
else
posted_data_fifo_rden <= 1'b1;
end else begin //4DW case
if(length_countdown <=1)
posted_data_fifo_rden <= 1'b0;
else
posted_data_fifo_rden <= 1'b1;
end
end
LAST_P_XFER: begin
trn_tsrc_rdy_n_reg <= 1'b0;
trn_teof_n <= 1'b0;//assert EOF
posted_data_fifo_rden <= 1'b0;
read_posted_header_fifo <= 1'b0;
//assert the correct remainder bits dependent on 3DW or 4DW TLP
//headers
if(p_fmt[0] == 0) //0 for 3dw, 1 for 4dw header
trn_trem_n[7:0] <= 8'b00001111;
else
trn_trem_n[7:0] <= 8'b00000000;
state <= IDLE;
end
//start of the non-posted transaction flow
SETUP_NP: begin
read_non_posted_header_fifo <= 1'b0;
state <= NP_WAIT_STATE;
end
//NP_WAIT_STATE state needed to let np_hd1 and np_hd2 to catch up
NP_WAIT_STATE:begin
if(np_trn_fifo_rdy)
state <= HD1_NP_XFER;
else
state <= NP_WAIT_STATE;
end
HD1_NP_XFER: begin //transfer first header
trn_tsof_n <= 1'b0; //assert SOF
trn_tsrc_rdy_n_reg <= 1'b0;
trn_trem_n[7:0] <= 8'b00000000;
state <= HD2_NP_XFER;
end
HD2_NP_XFER: begin //transfer second header + 1 DW of data
trn_tsrc_rdy_n_reg <= 1'b0;
trn_tsof_n <= 1'b1; //deassert EOF
trn_teof_n <= 1'b0; //assert EOF
if(np_fmt[0] == 0) //0 for 3dw, 1 for 4dw header
trn_trem_n[7:0] <= 8'b00001111;
else
trn_trem_n[7:0] <= 8'b00000000;
state <= NP_XFER_WAIT;
end
NP_XFER_WAIT : begin /// Jiansong: add one cycle into NP xfer to support
state <= IDLE; /// semiduplex scheduling
end
endcase
end
end
/// Jiansong: logic to maintain np_tx_cnt_qw
always@(posedge clk)begin
if (rst_reg | (~transferstart))
add_calc <= 1'b0;
else if(rd_dma_start_one) //set the bit
add_calc <= 1'b1;
else if (add_complete) //reset the bit
add_calc <= 1'b0;
end
always@(posedge clk)begin
if (rst_reg | (~transferstart) | Wait_for_TX_desc)
sub_calc <= 1'b0;
else if(read_non_posted_header_fifo_d1) //set the bit, fliter out TX des
sub_calc <= 1'b1;
else if (sub_complete) //reset the bit
sub_calc <= 1'b0;
end
always@(posedge clk) np_tx_cnt_qw_add[9:0] <= dmarxs[12:3];
always@(posedge clk)begin
if(rst_reg | (~transferstart) | Wait_for_TX_desc)begin
np_tx_cnt_qw[9:0] <= 0;
end else if(update_np_tx_cnt_qw)begin
np_tx_cnt_qw[9:0] <= np_tx_cnt_qw_new[9:0];
end
end
always@(posedge clk)begin
if(rst_reg | (~transferstart) | Wait_for_TX_desc)begin
np_tx_cnt_qw_new[9:0] <= 0;
update_np_tx_cnt_qw <= 1'b0;
add_complete <= 1'b0;
sub_complete <= 1'b0;
stay_2x <= 1'b0;
addsub_state <= AS_IDLE;
end else begin
case(addsub_state)
AS_IDLE: begin
update_np_tx_cnt_qw <= 1'b0;
if(add_calc)begin
//if add_calc is asserted then add the current value (*_now) to
//the incoming dma xfer size (*_reg)
np_tx_cnt_qw_new[9:0] <= np_tx_cnt_qw[9:0]
+ np_tx_cnt_qw_add[9:0];
//make sure to stay in this state for two clock cycles
if(~stay_2x)begin
addsub_state <= AS_IDLE;
add_complete <= 1'b0;
update_np_tx_cnt_qw <= 1'b0;
stay_2x <= 1'b1;
//then update the current value (dmawxs_div8_now)
end else begin
addsub_state <= REGISTER_CALC;
add_complete <= 1'b1;//clear add_calc
update_np_tx_cnt_qw <= 1'b1;
stay_2x <= 1'b0;
end
end else if (sub_calc)begin
//if sub_calc is asserted then subtract the dw_length field
//from the incoming completion packet from the current value
np_tx_cnt_qw_new[9:0] <= np_tx_cnt_qw[9:0]
- {1'b0, np_length[9:1]};
//likewise make sure to stat in this state for two clocks
if(~stay_2x)begin
addsub_state <= AS_IDLE;
sub_complete <= 1'b0;
update_np_tx_cnt_qw <= 1'b0;
stay_2x <= 1'b1;
//then update the current value (dmawxs_div8_now)
end else begin
addsub_state <= REGISTER_CALC;
sub_complete <= 1'b1;//clear sub_calc
update_np_tx_cnt_qw <= 1'b1;
stay_2x <= 1'b0;
end
end else begin
np_tx_cnt_qw_new[9:0] <= np_tx_cnt_qw[9:0];
addsub_state <= AS_IDLE;
sub_complete <= 1'b0;
add_complete <= 1'b0;
stay_2x <= 1'b0;
end
end
REGISTER_CALC:begin
sub_complete <= 1'b0;
add_complete <= 1'b0;
addsub_state <= WAIT_FOR_REG;
update_np_tx_cnt_qw <= 1'b1;
stay_2x <= 1'b0;
end
WAIT_FOR_REG:begin
update_np_tx_cnt_qw <= 1'b0;
stay_2x <= 1'b0;
addsub_state <= AS_IDLE;
end
default:begin
np_tx_cnt_qw_new[9:0] <= 0;
update_np_tx_cnt_qw <= 1'b0;
add_complete <= 1'b0;
sub_complete <= 1'b0;
stay_2x <= 1'b0;
addsub_state <= AS_IDLE;
end
endcase
end
end
endmodule
|
`define ADDER_WIDTH 009
`define DUMMY_WIDTH 128
`define 2_LEVEL_ADDER
module adder_tree_top (
clk,
isum0_0_0_0, isum0_0_0_1, isum0_0_1_0, isum0_0_1_1, isum0_1_0_0, isum0_1_0_1, isum0_1_1_0, isum0_1_1_1,
sum,
);
input clk;
input [`ADDER_WIDTH+0-1:0] isum0_0_0_0, isum0_0_0_1, isum0_0_1_0, isum0_0_1_1, isum0_1_0_0, isum0_1_0_1, isum0_1_1_0, isum0_1_1_1;
output [`ADDER_WIDTH :0] sum;
reg [`ADDER_WIDTH :0] sum;
wire [`ADDER_WIDTH+3-1:0] sum0;
wire [`ADDER_WIDTH+2-1:0] sum0_0, sum0_1;
wire [`ADDER_WIDTH+1-1:0] sum0_0_0, sum0_0_1, sum0_1_0, sum0_1_1;
reg [`ADDER_WIDTH+0-1:0] sum0_0_0_0, sum0_0_0_1, sum0_0_1_0, sum0_0_1_1, sum0_1_0_0, sum0_1_0_1, sum0_1_1_0, sum0_1_1_1;
adder_tree_branch L1_0(sum0_0, sum0_1, sum0 );
defparam L1_0.EXTRA_BITS = 2;
adder_tree_branch L2_0(sum0_0_0, sum0_0_1, sum0_0 );
adder_tree_branch L2_1(sum0_1_0, sum0_1_1, sum0_1 );
defparam L2_0.EXTRA_BITS = 1;
defparam L2_1.EXTRA_BITS = 1;
adder_tree_branch L3_0(sum0_0_0_0, sum0_0_0_1, sum0_0_0);
adder_tree_branch L3_1(sum0_0_1_0, sum0_0_1_1, sum0_0_1);
adder_tree_branch L3_2(sum0_1_0_0, sum0_1_0_1, sum0_1_0);
adder_tree_branch L3_3(sum0_1_1_0, sum0_1_1_1, sum0_1_1);
defparam L3_0.EXTRA_BITS = 0;
defparam L3_1.EXTRA_BITS = 0;
defparam L3_2.EXTRA_BITS = 0;
defparam L3_3.EXTRA_BITS = 0;
always @(posedge clk) begin
sum0_0_0_0 <= isum0_0_0_0;
sum0_0_0_1 <= isum0_0_0_1;
sum0_0_1_0 <= isum0_0_1_0;
sum0_0_1_1 <= isum0_0_1_1;
sum0_1_0_0 <= isum0_1_0_0;
sum0_1_0_1 <= isum0_1_0_1;
sum0_1_1_0 <= isum0_1_1_0;
sum0_1_1_1 <= isum0_1_1_1;
`ifdef 3_LEVEL_ADDER
sum <= sum0;
`endif
`ifdef 2_LEVEL_ADDER
sum <= sum0_0;
`endif
end
endmodule
module adder_tree_branch(a,b,sum);
parameter EXTRA_BITS = 0;
input [`ADDER_WIDTH+EXTRA_BITS-1:0] a;
input [`ADDER_WIDTH+EXTRA_BITS-1:0] b;
output [`ADDER_WIDTH+EXTRA_BITS:0] sum;
assign sum = a + b;
endmodule |
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2007 Corgan Enterprises LLC
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
`include "../top/config.vh"
module dac_interface(clk_i,rst_i,ena_i,strobe_i,tx_i_i,tx_q_i,tx_data_o,tx_sync_o);
input clk_i;
input rst_i;
input ena_i;
input strobe_i;
input [13:0] tx_i_i;
input [13:0] tx_q_i;
output [13:0] tx_data_o;
output tx_sync_o;
`ifdef TX_RATE_MAX
wire clk128;
reg clk64_d;
reg [13:0] tx_data_o;
// Create a 128 MHz clock
dacpll pll128(.areset(rst_i),.inclk0(clk_i),.c0(clk128));
// Register the clk64 clock in the clk128 domain
always @(posedge clk128)
clk64_d <= clk_i;
// Register the tx data in the clk128 domain
always @(posedge clk128)
tx_data_o <= clk64_d ? tx_i_i : tx_q_i;
assign tx_sync_o = clk64_d;
`else // !`ifdef TX_RATE_MAX
assign tx_data_o = strobe_i ? tx_i_i : tx_q_i;
assign tx_sync_o = strobe_i;
`endif // !`ifdef TX_RATE_MAX
endmodule // dac_interface
|
// DESCRIPTION: Verilator: Verilog Test module
//
// Copyright 2010 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
wire monclk = ~clk;
int in;
int fr_a;
int fr_b;
int fr_chk;
sub sub (.*);
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d in=%x fr_a=%x b=%x fr_chk=%x\n", $time, cyc, in, fr_a, fr_b, fr_chk);
`endif
cyc <= cyc + 1;
in <= {in[30:0], in[31]^in[2]^in[0]};
if (cyc==0) begin
// Setup
in <= 32'hd70a4497;
end
else if (cyc<3) begin
end
else if (cyc<10) begin
if (fr_chk != fr_a) $stop;
if (fr_chk != fr_b) $stop;
end
else if (cyc==10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
always @(posedge t.monclk) begin
mon_eval();
end
endmodule
`ifdef ATTRIBUTES
import "DPI-C" context function void mon_scope_name (input string formatted /*verilator sformat*/ );
`else
import "DPI-C" context function void mon_scope_name (input string formatted);
`endif
import "DPI-C" context function void mon_register_b(string name, int isOut);
import "DPI-C" context function void mon_register_done();
import "DPI-C" context function void mon_eval();
module sub (/*AUTOARG*/
// Outputs
fr_a, fr_b, fr_chk,
// Inputs
in
);
`systemc_imp_header
void mon_class_name(const char* namep);
void mon_register_a(const char* namep, void* sigp, bool isOut);
`verilog
`ifdef ATTRIBUTES
input int in /*verilator public_flat_rd*/;
output int fr_a /*verilator public_flat_rw @(posedge t.monclk)*/;
output int fr_b /*verilator public_flat_rw @(posedge t.monclk)*/;
`else
input int in;
output int fr_a;
output int fr_b;
`endif
output int fr_chk;
always @* fr_chk = in + 1;
initial begin
// Test the naming
$c("mon_class_name(this->name());");
mon_scope_name("%m");
// Scheme A - pass pointer directly
$c("mon_register_a(\"in\", &", in, ", false);");
$c("mon_register_a(\"fr_a\", &", fr_a, ", true);");
// Scheme B - use VPIish callbacks to see what signals exist
mon_register_b("in", 0);
mon_register_b("fr_b", 1);
mon_register_done();
end
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_fp_custom_add_op( clock, resetn, left_mantissa, right_mantissa, left_sign, right_sign, common_exponent,
resulting_mantissa, resulting_exponent, resulting_sign,
valid_in, valid_out, stall_in, stall_out, enable);
parameter HIGH_CAPACITY = 1;
// Latency = 1 cycle.
input clock, resetn, left_sign, right_sign;
input [26:0] left_mantissa;
input [26:0] right_mantissa;
input [8:0] common_exponent;
input valid_in, stall_in, enable;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) output reg [27:0] resulting_mantissa;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) output reg [8:0] resulting_exponent;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) output reg resulting_sign;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) output reg valid_out;
output stall_out;
wire enable_add = (HIGH_CAPACITY==1) ? (~valid_out | ~stall_in) : enable;
wire do_subtraction = right_sign ^ left_sign;
assign stall_out = valid_out & stall_in;
wire [27:0] op_ab = left_mantissa + ({28{do_subtraction}} ^ right_mantissa) + do_subtraction;
always@(posedge clock or negedge resetn)
begin
if (~resetn)
begin
resulting_mantissa <= 28'bxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
resulting_exponent <= 9'bxxxxxxxx;
resulting_sign <= 1'bx;
valid_out <= 1'b0;
end
else if (enable_add)
begin
valid_out <= valid_in;
resulting_mantissa <= op_ab;
resulting_exponent <= common_exponent;
resulting_sign <= left_sign;
end
end
endmodule
|
(** * Prop: Propositions and Evidence *)
(* $Date: 2012-07-23 16:26:25 -0400 (Mon, 23 Jul 2012) $ *)
Require Export Poly.
(** In previous chapters, we have seen many examples of factual
claims (_propositions_) and ways of presenting evidence of their
truth (_proofs_). In particular, we have worked extensively with
_equality propositions_ of the form [e1 = e2], with
implications ([P -> Q]), and with quantified propositions
([forall x, P]).
In this chapter we take a deeper look at the way propositions are
expressed in Coq and at the structure of the logical evidence that
we construct when we carry out proofs.
Some of the concepts in this chapter may seem a bit abstract on a
first encounter. We've included a _lot_ of exercises, most of
which should be quite approachable even if you're still working on
understanding the details of the text. Try to work as many of
them as you can, especially the one-starred exercises. *)
(* ##################################################### *)
(** * Inductively Defined Propositions *)
(** As a running example for the first part of the chapter, let's
consider a simple property of natural numbers, and let's say that
the numbers possessing this property are "beautiful." *)
(** Informally, a number is _beautiful_ if it is [0], [3], [5], or the
sum of two beautiful numbers. More pedantically, we can define
beautiful numbers by giving four rules:
- Rule [b_0]: The number [0] is beautiful.
- Rule [b_3]: The number [3] is beautiful.
- Rule [b_5]: The number [5] is beautiful.
- Rule [b_sum]: If [n] and [m] are both beautiful, then so is
their sum. *)
(** We will see many definitions like this one during the rest of the
course, and for purposes of informal discussions, it is helpful to
have a lightweight notation that makes them easy to read and
write. _Inference rules_ are one such notation: *)
(**
----------- (b_0)
beautiful 0
------------ (b_3)
beautiful 3
------------ (b_5)
beautiful 5
beautiful n beautiful m
--------------------------- (b_sum)
beautiful (n+m)
*)
(** Each of the textual rules above is reformatted here as an
inference rule; the intended reading is that, if the _premises_
above the line all hold, then the _conclusion_ below the line
follows. For example, the rule [b_sum] says that, if [n] and [m]
are both beautiful numbers, then it follows that [n+m] is
beautiful too. The rules with no premises above the line are
called _axioms_.
These rules _define_ the property [beautiful]. That is, if we
want to convince someone that some particular number is beautiful,
our argument must be based on these rules. For a simple example,
suppose we claim that the number [5] is beautiful. To support
this claim, we just need to point out that rule [b_5] says it is.
Or, if we want to claim that [8] is beautiful, we can support our
claim by first observing that [3] and [5] are both beautiful (by
rules [b_3] and [b_5]) and then pointing out that their sum, [8],
is therefore beautiful by rule [b_sum]. This argument can be
expressed graphically with the following _proof tree_:
----------- (b_3) ----------- (b_5)
beautiful 3 beautiful 5
------------------------------- (b_sum)
beautiful 8
Of course, there are other ways of using these rules to argue that
[8] is beautiful -- for instance:
----------- (b_5) ----------- (b_3)
beautiful 5 beautiful 3
------------------------------- (b_sum)
beautiful 8
*)
(** **** Exercise: 1 star (varieties_of_beauty) *)
(** How many different ways are there to show that [8] is beautiful? *)
(* FILL IN HERE *)
(** [] *)
(** In Coq, we can express the definition of [beautiful] as
follows: *)
Inductive beautiful : nat -> Prop :=
b_0 : beautiful 0
| b_3 : beautiful 3
| b_5 : beautiful 5
| b_sum : forall n m, beautiful n -> beautiful m -> beautiful (n+m).
(** The first line declares that [beautiful] is a proposition -- or,
more formally, a family of propositions "indexed by" natural
numbers. (For each number [n], the claim that "[n] is
[beautiful]" is a proposition.) Such a family of propositions is
often called a _property_ of numbers.
Each of the remaining lines embodies one of the rules for
beautiful numbers.
We can use Coq's tactic scripting facility to assemble proofs that
particular numbers are beautiful. *)
Theorem three_is_beautiful: beautiful 3.
Proof.
(* This simply follows from the axiom [b_3]. *)
apply b_3.
Qed.
Theorem eight_is_beautiful: beautiful 8.
Proof.
(* First we use the rule [b_sum], telling Coq how to
instantiate [n] and [m]. *)
apply b_sum with (n:=3) (m:=5).
(* To solve the subgoals generated by [b_sum], we must provide
evidence of [beautiful 3] and [beautiful 5]. Fortunately we
have axioms for both. *)
apply b_3.
apply b_5.
Qed.
(* ##################################################### *)
(** * Proof Objects *)
(** Look again at the formal definition of the [beautiful] property.
The opening keyword, [Inductive], has been used up to this point
to declare new types of _data_, such as numbers and lists. Does
this interpretation also make sense for the Inductive definition
of [beautiful]? That is, can we view evidence of beauty as some
kind of data structure? Yes, we can!
The trick is to introduce an alternative pronunciation of "[:]".
Instead of "has type," we can also say "is a proof of." For
example, the second line in the definition of [beautiful] declares
that [b_0 : beautiful 0]. Instead of "[b_0] has type
[beautiful 0]," we can say that "[b_0] is a proof of [beautiful 0]."
Similarly for [b_3] and [b_5].
This pun between "[:]" as "has type" and [:] as "is a proof of" is
called the _Curry-Howard correspondence_ (or sometimes
_Curry-Howard isomorphism_). It proposes a deep connection
between the world of logic and the world of computation.
<<
propositions ~ types
evidence ~ data
>>
Many useful things follow from this connection. To begin with, it
gives us a natural interpretation of the [b_sum] constructor: *)
(**
b_sum : forall n m,
beautiful n -> beautiful m -> beautiful (n+m).
*)
(** If we read [:] as "has type," this says that [b_sum] is a data
constructor that takes four arguments: two numbers, [n] and [m],
and two values of type [beautiful n] and [beautiful m]. That is,
[b_sum] can be viewed as a _function_ that, given evidence for the
propositions [beautiful n] and [beautiful m], gives us evidence
for the proposition that [beautiful (n+m)]. *)
(** In view of this, we might wonder whether we can write an
expression of type [beautiful 8] by applying [b_sum] to
appropriate arguments. Indeed, we can: *)
Check (b_sum 3 5 b_3 b_5).
(** The expression [b_sum 3 5 b_3 b_5] can be thought of as
instantiating the parameterized constructor [b_sum] with the
specific arguments [3] [5] and the corresponding proof objects for
its premises [beautiful 3] and [beautiful 5] (Coq is smart enough
to figure out that 3+5=8). Alternatively, we can think of [b_sum]
as a primitive "evidence constructor" that, when applied to two
particular numbers, wants to be further applied to evidence that
those two numbers are beautiful; its type,
[[
forall n m, beautiful n -> beautiful m -> beautiful (n+m),
expresses this functionality, in the same way that the polymorphic
type [forall X, list X] in the previous chapter expressed the fact
that the constructor [nil] can be thought of as a function from
types to empty lists with elements of that type. *)
(** This gives us an alternative way to write the proof that [8] is
beautiful: *)
Theorem eight_is_beautiful': beautiful 8.
Proof.
apply (b_sum 3 5 b_3 b_5).
Qed.
(** Notice that we're using [apply] here in a new way: instead of just
supplying the _name_ of a hypothesis or previously proved theorem
whose type matches the current goal, we are supplying an
_expression_ that directly builds evidence with the required
type. *)
(* ##################################################### *)
(** ** Proof Scripts and Proof Objects *)
(** These proof objects lie at the core of how Coq operates.
When Coq is following a proof script, what is happening internally
is that it is gradually constructing a proof object -- a term
whose type is the proposition being proved. The tactics between
the [Proof] command and the [Qed] instruct Coq how to build up a
term of the required type. To see this process in action, let's
use the [Show Proof] command to display the current state of the
proof tree at various points in the following tactic proof. *)
Theorem eight_is_beautiful'': beautiful 8.
Proof.
apply b_sum with (n:=3) (m:=5).
Show Proof.
apply b_3.
Show Proof.
apply b_5.
Show Proof.
Qed.
(** At any given moment, Coq has constructed a term with some
"holes" (indicated by [?1], [?2], and so on), and it knows what
type of evidence is needed at each hole. In the [Show Proof]
output, lines of the form [?1 -> beautiful n] record these
requirements. (The [->] here has nothing to do with either
implication or function types -- it is just an unfortunate choice
of concrete syntax for the output!)
Each of the holes corresponds to a subgoal, and the proof is
finished when there are no more subgoals. At this point, the
[Theorem] command gives a name to the evidence we've built and
stores it in the global context. *)
(** Tactic proofs are useful and convenient because they avoid
building proof trees by hand, but they are not essential: in
principle, we can always construct the required evidence by hand.
Indeed, we don't even need the [Theorem] command: we can use
[Definition] instead, to directly give a global name to a piece of
evidence. *)
Definition eight_is_beautiful''' : beautiful 8 :=
b_sum 3 5 b_3 b_5.
(** All these different ways of building the proof lead to exactly the
same evidence being saved in the global environment. *)
Print eight_is_beautiful.
(* ===> eight_is_beautiful = b_sum 3 5 b_3 b_5 : beautiful 8 *)
Print eight_is_beautiful'.
(* ===> eight_is_beautiful' = b_sum 3 5 b_3 b_5 : beautiful 8 *)
Print eight_is_beautiful''.
(* ===> eight_is_beautiful'' = b_sum 3 5 b_3 b_5 : beautiful 8 *)
Print eight_is_beautiful'''.
(* ===> eight_is_beautiful''' = b_sum 3 5 b_3 b_5 : beautiful 8 *)
(** **** Exercise: 1 star (six_is_beautiful) *)
(** Give a tactic proof and a proof object showing that [6] is [beautiful]. *)
Theorem six_is_beautiful :
beautiful 6.
Proof.
(* FILL IN HERE *) Admitted.
Definition six_is_beautiful' : beautiful 6 :=
(* FILL IN HERE *) admit.
(** [] *)
(** **** Exercise: 1 star (nine_is_beautiful) *)
(** Give a tactic proof and a proof object showing that [9] is [beautiful]. *)
Theorem nine_is_beautiful :
beautiful 9.
Proof.
(* FILL IN HERE *) Admitted.
Definition nine_is_beautiful' : beautiful 9 :=
(* FILL IN HERE *) admit.
(** [] *)
(* ##################################################### *)
(** ** Implications and Functions *)
(** If we want to substantiate the claim that [P -> Q], what sort of
proof object should count as evidence?
We've seen one case above: the [b_sum] constructor, which is
_primitive_ evidence for an implication proposition -- it is part
of the very meaning of the word "beautiful" in this context. But
what about other implications that we might want to prove?
For example, consider this statement: *)
Theorem b_plus3: forall n, beautiful n -> beautiful (3+n).
Proof.
intros n H.
apply b_sum.
apply b_3.
apply H.
Qed.
(** What is the proof object corresponding to [b_plus3]?
We've made a notational pun between [->] as implication and [->]
as the type of functions. If we take this pun seriously, then
what we're looking for is an expression whose _type_ is
[forall n, beautiful n -> beautiful (3+n)] -- that is, a
_function_ that takes two arguments (one number and a piece of
evidence) and returns a piece of evidence! Here it is: *)
Definition b_plus3' : forall n, beautiful n -> beautiful (3+n) :=
fun n => fun H : beautiful n =>
b_sum 3 n b_3 H.
Check b_plus3'.
(* ===> b_plus3' : forall n, beautiful n -> beautiful (3+n) *)
(** Recall that [fun n => blah] means "the function that, given [n],
yields [blah]." Another equivalent way to write this definition is: *)
Definition b_plus3'' (n : nat) (H : beautiful n) : beautiful (3+n) :=
b_sum 3 n b_3 H.
Check b_plus3''.
(* ===> b_plus3'' : forall n, beautiful n -> beautiful (3+n) *)
(** **** Exercise: 2 stars (b_times2) *)
Theorem b_times2: forall n, beautiful n -> beautiful (2*n).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, optional (b_times2') *)
(** Write a proof object corresponding to [b_times2] above *)
Definition b_times2': forall n, beautiful n -> beautiful (2*n) :=
(* FILL IN HERE *) admit.
(** **** Exercise: 2 stars (b_timesm) *)
Theorem b_timesm: forall n m, beautiful n -> beautiful (m*n).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ####################################################### *)
(** ** Induction Over Proof Objects *)
(** Since we use the keyword [Induction] to define primitive
propositions together with their evidence, we might wonder whether
there are some sort of induction principles associated with these
definitions. Indeed there are, and in this section we'll take a
look at how they can be used. *)
(** Besides _constructing_ evidence that numbers are beautiful, we can
also _reason about_ such evidence. The fact that we introduced
[beautiful] with an [Inductive] declaration tells us not only that
the constructors [b_0], [b_3], [b_5] and [b_sum] are ways to build
evidence, but also that these two constructors are the _only_ ways
to build evidence that numbers are beautiful. *)
(** In other words, if someone gives us evidence [E] justifying the
assertion [beautiful n], then we know that [E] can only have one
of four forms: either [E] is [b_0] (and [n] is [O]) or [E] is
[b_3] (and [n] is [3]), or [E] is [b_5] (and [n] is [5]), or [E]
is [b_sum n1 n2 E1 E2] (and [n] is [(n1+n2)], and [E1] is evidence
that [n1] is beauiful and [E2] is evidence that [n2] is
beautiful). *)
(** Thus, it makes sense to use the tactics that we have already seen
for inductively defined _data_ to reason instead about inductively
defined _evidence_.
Let's introduce a new property of numbers to help illustrate the
role of induction. *)
Inductive gorgeous : nat -> Prop :=
g_0 : gorgeous 0
| g_plus3 : forall n, gorgeous n -> gorgeous (3+n)
| g_plus5 : forall n, gorgeous n -> gorgeous (5+n).
(** **** Exercise: 1 star (gorgeous_tree) *)
(** Write out the definition of gorgeous numbers using the _inference
rule_ notation.
(* FILL IN HERE *)
[]
*)
(** It seems intuitively obvious that, although [gorgeous] and
[beautiful] are presented using slightly different rules, they are
actually the same property in the sense that they are true of the
same numbers. Indeed, we can prove this. *)
Theorem gorgeous__beautiful : forall n,
gorgeous n -> beautiful n.
Proof.
intros.
(* The argument proceeds by induction on the evidence H! *)
induction H as [|n'|n'].
Case "g_0".
apply b_0.
Case "g_plus3".
apply b_sum. apply b_3.
apply IHgorgeous.
Case "g_plus5".
apply b_sum. apply b_5. apply IHgorgeous.
Qed.
(** Let's see what happens if we try to prove this by induction on [n]
instead of induction on the evidence [H]. *)
Theorem gorgeous__beautiful_FAILED : forall n,
gorgeous n -> beautiful n.
Proof.
intros. induction n as [| n'].
Case "n = 0". apply b_0.
Case "n = S n'". (* We are stuck! *)
Admitted.
(** **** Exercise: 1 star (gorgeous_plus13) *)
Theorem gorgeous_plus13: forall n,
gorgeous n -> gorgeous (13+n).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars (gorgeous_plus13_po):
Give the proof object for theorem [gorgeous_plus13] above. *)
Definition gorgeous_plus13_po: forall n, gorgeous n -> gorgeous (13+n):=
(* FILL IN HERE *) admit.
(** [] *)
(** **** Exercise: 2 stars (gorgeous_sum) *)
Theorem gorgeous_sum : forall n m,
gorgeous n -> gorgeous m -> gorgeous (n + m).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars (beautiful__gorgeous) *)
Theorem beautiful__gorgeous : forall n, beautiful n -> gorgeous n.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, optional (b_times2) *)
(** Prove the [g_times2] theorem below without using [gorgeous__beautiful].
You might find the following helper lemma useful. *)
Lemma helper_g_times2 : forall x y z, x + (z + y)= z + x + y.
Proof.
(* FILL IN HERE *) Admitted.
Theorem g_times2: forall n, gorgeous n -> gorgeous (2*n).
Proof.
intros n H. simpl.
induction H.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ####################################################### *)
(** ** Evenness *)
(** In chapter [Basics] we defined a _function_ [evenb] that tests a number
for evenness, yielding [true] if so. This gives us an obvious way
of defining the _concept_ of evenness: *)
Definition even (n:nat) : Prop :=
evenb n = true.
(** That is, we can define "[n] is even" to mean "the function
[evenb] returns [true] when applied to [n]."
Another alternative is to define the concept of evenness directly.
Instead of going via the [evenb] function ("a number is even if a
certain computation yields [true]"), we can say what the concept
of evenness means by giving two different ways of presenting
_evidence_ that a number is even. *)
Inductive ev : nat -> Prop :=
| ev_0 : ev O
| ev_SS : forall n:nat, ev n -> ev (S (S n)).
(** This definition says that there are two ways to give
evidence that a number [m] is even. First, [0] is even, and
[ev_0] is evidence for this. Second, if [m = S (S n)] for some
[n] and we can give evidence [e] that [n] is even, then [m] is
also even, and [ev_SS n e] is the evidence. *)
(** **** Exercise: 1 star (double_even) *)
(** Construct a tactic proof of the following proposition. *)
Theorem double_even : forall n,
ev (double n).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 4 stars, optional (double_even_pfobj) *)
(** Try to predict what proof object is constructed by the above
tactic proof. (Before checking your answer, you'll want to
strip out any uses of [Case], as these will make the proof
object look a bit cluttered.) *)
(** [] *)
(** *** Discussion: Computational vs. Inductive Definitions *)
(** We have seen that the proposition "some number is even" can
be phrased in two different ways -- indirectly, via a boolean
testing function [evenb], or directly, by inductively describing
what constitutes evidence for evenness. These two ways of
defining evenness are about equally easy to state and work with.
Which we choose is basically a question of taste.
However, for many other properties of interest, the direct
inductive definition is preferable, since writing a testing
function may be awkward or even impossible.
One such property is [beautiful]. This is a perfectly sensible
definition of a set of numbers, but we cannot translate its
definition directly as a Coq Fixpoint (or translate it directly
into a recursive function in any other programming language). We
might be able to find a clever way of testing this property using
a [Fixpoint] (indeed, it is not too hard to find one in this
case), but in general this could require arbitrarily deep
thinking. In fact, if the property we are interested in is
uncomputable, then we cannot define it as a [Fixpoint] no matter
how hard we try, because Coq requires that all [Fixpoint]s
correspond to terminating computations.
On the other hand, writing an inductive definition of what it
means to give evidence for the property [beautiful] is
straightforward. *)
(* ####################################################### *)
(** ** Inverting Evidence *)
(** Besides induction, we can use the other tactics in our toolkit
with evidence. For example, this proof uses [destruct] on
evidence. *)
Theorem ev_minus2: forall n,
ev n -> ev (pred (pred n)).
Proof.
intros n E.
destruct E as [| n' E'].
Case "E = ev_0". simpl. apply ev_0.
Case "E = ev_SS n' E'". simpl. apply E'. Qed.
(** **** Exercise: 1 star, optional (ev_minus2_n) *)
(** What happens if we try to [destruct] on [n] instead of [E]? *)
(** [] *)
(** **** Exercise: 1 star, recommended (ev__even) *)
(** Here is a proof that the inductive definition of evenness implies
the computational one. *)
Theorem ev__even : forall n,
ev n -> even n.
Proof.
intros n E. induction E as [| n' E'].
Case "E = ev_0".
unfold even. reflexivity.
Case "E = ev_SS n' E'".
unfold even. apply IHE'.
Qed.
(** Could this proof also be carried out by induction on [n] instead
of [E]? If not, why not? *)
(* FILL IN HERE *)
(** [] *)
(** The induction principle for inductively defined propositions does
not follow quite the same form as that of inductively defined
sets. For now, you can take the intuitive view that induction on
evidence [ev n] is similar to induction on [n], but restricts our
attention to only those numbers for which evidence [ev n] could be
generated. We'll look at the induction principle of [ev] in more
depth below, to explain what's really going on. *)
(** **** Exercise: 1 star (l_fails) *)
(** The following proof attempt will not succeed.
Theorem l : forall n,
ev n.
Proof.
intros n. induction n.
Case "O". simpl. apply ev_0.
Case "S".
...
Briefly explain why.
(* FILL IN HERE *)
*)
(** [] *)
(** **** Exercise: 2 stars (ev_sum) *)
(** Here's another exercise requiring induction. *)
Theorem ev_sum : forall n m,
ev n -> ev m -> ev (n+m).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** Here's another situation where we want to analyze evidence for
evenness: proving that if [n+2] is even, then [n] is. Our first
idea might be to use [destruct] for this kind of case analysis: *)
Theorem SSev_ev_firsttry : forall n,
ev (S (S n)) -> ev n.
Proof.
intros n E.
destruct E as [| n' E'].
(* Stuck: [destruct] gives us un-provable subgoal here! *)
Admitted.
(** In the first sub-goal, we've lost the information that [n] is [0].
We could have used [remember], but then we still need [inversion]
on both cases. *)
Theorem SSev_ev_secondtry : forall n,
ev (S (S n)) -> ev n.
Proof.
intros n E. remember (S (S n)) as n2.
destruct E as [| n' E'].
Case "n = 0". inversion Heqn2.
Case "n = S n'". inversion Heqn2. rewrite <- H0. apply E'.
Qed.
(** There is a much simpler way to this: we can use [inversion] directly
on the inductively defined proposition [ev (S (S n))]. *)
Theorem SSev__even : forall n,
ev (S (S n)) -> ev n.
Proof.
intros n E. inversion E as [| n' E']. apply E'. Qed.
(* Print SSev__even. *)
(** This use of [inversion] may seem a bit mysterious at first.
Until now, we've only used [inversion] on equality
propositions, to utilize injectivity of constructors or to
discriminate between different constructors. But we see here
that [inversion] can also be applied to analyzing evidence
for inductively defined propositions.
Here's how [inversion] works in general. Suppose the name
[I] refers to an assumption [P] in the current context, where
[P] has been defined by an [Inductive] declaration. Then,
for each of the constructors of [P], [inversion I] generates
a subgoal in which [I] has been replaced by the exact,
specific conditions under which this constructor could have
been used to prove [P]. Some of these subgoals will be
self-contradictory; [inversion] throws these away. The ones
that are left represent the cases that must be proved to
establish the original goal.
In this particular case, the [inversion] analyzed the construction
[ev (S (S n))], determined that this could only have been
constructed using [ev_SS], and generated a new subgoal with the
arguments of that constructor as new hypotheses. (It also
produced an auxiliary equality, which happens to be useless here.)
We'll begin exploring this more general behavior of inversion in
what follows. *)
(** **** Exercise: 1 star (inversion_practice) *)
Theorem SSSSev__even : forall n,
ev (S (S (S (S n)))) -> ev n.
Proof.
(* FILL IN HERE *) Admitted.
(** The [inversion] tactic can also be used to derive goals by showing
the absurdity of a hypothesis. *)
Theorem even5_nonsense :
ev 5 -> 2 + 2 = 9.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** We can generally use [inversion] on inductive propositions.
This illustrates that in general, we get one case for each
possible constructor. Again, we also get some auxiliary
equalities that are rewritten in the goal but not in the other
hypotheses. *)
Theorem ev_minus2': forall n,
ev n -> ev (pred (pred n)).
Proof.
intros n E. inversion E as [| n' E'].
Case "E = ev_0". simpl. apply ev_0.
Case "E = ev_SS n' E'". simpl. apply E'. Qed.
(** **** Exercise: 3 stars, recommended (ev_ev__ev) *)
(** Finding the appropriate thing to do induction on is a
bit tricky here: *)
Theorem ev_ev__ev : forall n m,
ev (n+m) -> ev n -> ev m.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, optional (ev_plus_plus) *)
(** Here's an exercise that just requires applying existing lemmas. No
induction or even case analysis is needed, but some of the rewriting
may be tedious. You'll want the [replace] tactic used for [plus_swap']
in Basics.v *)
Theorem ev_plus_plus : forall n m p,
ev (n+m) -> ev (n+p) -> ev (m+p).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ##################################################### *)
(* ##################################################### *)
(** * Programming with Propositions *)
(** A _proposition_ is a statement expressing a factual claim,
like "two plus two equals four." In Coq, propositions are written
as expressions of type [Prop]. Although we haven't mentioned it
explicitly, we have already seen numerous examples. *)
Check (2 + 2 = 4).
(* ===> 2 + 2 = 4 : Prop *)
Check (ble_nat 3 2 = false).
(* ===> ble_nat 3 2 = false : Prop *)
Check (beautiful 8).
(* ===> beautiful 8 : Prop *)
(** Both provable and unprovable claims are perfectly good
propositions. Simply _being_ a proposition is one thing; being
_provable_ is something else! *)
Check (2 + 2 = 5).
(* ===> 2 + 2 = 5 : Prop *)
Check (beautiful 4).
(* ===> beautiful 4 : Prop *)
(** Both [2 + 2 = 4] and [2 + 2 = 5] are legal expressions
of type [Prop]. *)
(** We've seen one way that propositions can be used in Coq: in
[Theorem] (and [Lemma] and [Example]) declarations. *)
Theorem plus_2_2_is_4 :
2 + 2 = 4.
Proof. reflexivity. Qed.
(** But they can be used in many other ways. For example, we
can give a name to a proposition using a [Definition], just as we
have given names to expressions of other sorts (numbers,
functions, types, type functions, ...). *)
Definition plus_fact : Prop := 2 + 2 = 4.
Check plus_fact.
(* ===> plus_fact : Prop *)
(** Now we can use this name in any situation where a proposition is
expected -- for example, as the claim in a [Theorem]
declaration. *)
Theorem plus_fact_is_true :
plus_fact.
Proof. reflexivity. Qed.
(** There are many ways of constructing propositions. We can define a
new proposition primitively using [Inductive], we can form an
equality proposition from two computational expressions, and we
can build up a new proposition from existing ones using
implication and quantification. *)
Definition strange_prop1 : Prop :=
(2 + 2 = 5) -> (99 + 26 = 42).
(** Also, given a proposition [P] with a free variable [n], we can
form the proposition [forall n, P]. *)
Definition strange_prop2 :=
forall n, (ble_nat n 17 = true) -> (ble_nat n 99 = true).
(** We can also define _parameterized propositions_, such as
the property of being even. *)
Check even.
(* ===> even : nat -> Prop *)
Check (even 4).
(* ===> even 4 : Prop *)
Check (even 3).
(* ===> even 3 : Prop *)
(** The type of [even], [nat->Prop], can be pronounced in three
equivalent ways: (1) "[even] is a _function_ from numbers to
propositions," (2) "[even] is a _family_ of propositions, indexed
by a number [n]," or (3) "[even] is a _property_ of numbers." *)
(** Propositions -- including parameterized propositions -- are
first-class citizens in Coq. For example, we can define them to
take multiple arguments... *)
Definition between (n m o: nat) : Prop :=
andb (ble_nat n o) (ble_nat o m) = true.
(** ... and then partially apply them: *)
Definition teen : nat->Prop := between 13 19.
(** We can even pass propositions -- including parameterized
propositions -- as arguments to functions: *)
Definition true_for_zero (P:nat->Prop) : Prop :=
P 0.
(** Here are two more examples of passing parameterized propositions
as arguments to a function. The first takes a proposition [P] as
argument and builds the proposition that [P] is true for all
natural numbers. The second takes [P] and builds the proposition
that, if [P] is true for some natural number [n'], then it is also
true by the successor of [n'] -- i.e. that [P] is _preserved by
successor_:*)
Definition true_for_all_numbers (P:nat->Prop) : Prop :=
forall n, P n.
Definition preserved_by_S (P:nat->Prop) : Prop :=
forall n', P n' -> P (S n').
(* ##################################################### *)
(** * Induction Principles *)
(** This is a good point to pause and take a deeper look at induction
principles in general. *)
(* ##################################################### *)
(** ** Induction Principles for Inductively Defined Types *)
(** Every time we declare a new [Inductive] datatype, Coq
automatically generates an axiom that embodies an _induction
principle_ for this type.
The induction principle for a type [t] is called [t_ind]. Here is
the one for natural numbers: *)
Check nat_ind.
(* ===> nat_ind :
forall P : nat -> Prop,
P 0 ->
(forall n : nat, P n -> P (S n)) ->
forall n : nat, P n *)
(** The [induction] tactic is a straightforward wrapper that, at
its core, simply performs [apply t_ind]. To see this more
clearly, let's experiment a little with using [apply nat_ind]
directly, instead of the [induction] tactic, to carry out some
proofs. Here, for example, is an alternate proof of a theorem
that we saw in the [Basics] chapter. *)
Theorem mult_0_r' : forall n:nat,
n * 0 = 0.
Proof.
apply nat_ind.
Case "O". reflexivity.
Case "S". simpl. intros n IHn. rewrite -> IHn.
reflexivity. Qed.
(** This proof is basically the same as the earlier one, but a
few minor differences are worth noting. First, in the induction
step of the proof (the ["S"] case), we have to do a little
bookkeeping manually (the [intros]) that [induction] does
automatically.
Second, we do not introduce [n] into the context before applying
[nat_ind] -- the conclusion of [nat_ind] is a quantified formula,
and [apply] needs this conclusion to exactly match the shape of
the goal state, including the quantifier. The [induction] tactic
works either with a variable in the context or a quantified
variable in the goal.
Third, the [apply] tactic automatically chooses variable names for
us (in the second subgoal, here), whereas [induction] lets us
specify (with the [as...] clause) what names should be used. The
automatic choice is actually a little unfortunate, since it
re-uses the name [n] for a variable that is different from the [n]
in the original theorem. This is why the [Case] annotation is
just [S] -- if we tried to write it out in the more explicit form
that we've been using for most proofs, we'd have to write [n = S
n], which doesn't make a lot of sense! All of these conveniences
make [induction] nicer to use in practice than applying induction
principles like [nat_ind] directly. But it is important to
realize that, modulo this little bit of bookkeeping, applying
[nat_ind] is what we are really doing. *)
(** **** Exercise: 2 stars, optional (plus_one_r') *)
(** Complete this proof as we did [mult_0_r'] above, without using
the [induction] tactic. *)
Theorem plus_one_r' : forall n:nat,
n + 1 = S n.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** The induction principles that Coq generates for other datatypes
defined with [Inductive] follow a similar pattern. If we define a
type [t] with constructors [c1] ... [cn], Coq generates a theorem
with this shape:
t_ind :
forall P : t -> Prop,
... case for c1 ... ->
... case for c2 ... ->
... ->
... case for cn ... ->
forall n : t, P n
The specific shape of each case depends on the arguments to the
corresponding constructor. Before trying to write down a general
rule, let's look at some more examples. First, an example where
the constructors take no arguments: *)
Inductive yesno : Type :=
| yes : yesno
| no : yesno.
Check yesno_ind.
(* ===> yesno_ind : forall P : yesno -> Prop,
P yes ->
P no ->
forall y : yesno, P y *)
(** **** Exercise: 1 star (rgb) *)
(** Write out the induction principle that Coq will generate for
the following datatype. Write down your answer on paper, and
then compare it with what Coq prints. *)
Inductive rgb : Type :=
| red : rgb
| green : rgb
| blue : rgb.
Check rgb_ind.
(** [] *)
(** Here's another example, this time with one of the constructors
taking some arguments. *)
Inductive natlist : Type :=
| nnil : natlist
| ncons : nat -> natlist -> natlist.
Check natlist_ind.
(* ===> (modulo a little tidying)
natlist_ind :
forall P : natlist -> Prop,
P nnil ->
(forall (n : nat) (l : natlist), P l -> P (ncons n l)) ->
forall n : natlist, P n *)
(** **** Exercise: 1 star (natlist1) *)
(** Suppose we had written the above definition a little
differently: *)
Inductive natlist1 : Type :=
| nnil1 : natlist1
| nsnoc1 : natlist1 -> nat -> natlist1.
(** Now what will the induction principle look like? *)
(** [] *)
(** From these examples, we can extract this general rule:
- The type declaration gives several constructors; each
corresponds to one clause of the induction principle.
- Each constructor [c] takes argument types [a1]...[an].
- Each [ai] can be either [t] (the datatype we are defining) or
some other type [s].
- The corresponding case of the induction principle
says (in English):
- "for all values [x1]...[xn] of types [a1]...[an], if
[P] holds for each of the [x]s of type [t], then [P]
holds for [c x1 ... xn]". *)
(** **** Exercise: 1 star (ex_set) *)
(** Here is an induction principle for an inductively defined
set.
ExSet_ind :
forall P : ExSet -> Prop,
(forall b : bool, P (con1 b)) ->
(forall (n : nat) (e : ExSet), P e -> P (con2 n e)) ->
forall e : ExSet, P e
Give an [Inductive] definition of [ExSet]: *)
Inductive ExSet : Type :=
(* FILL IN HERE *)
.
(** [] *)
(** What about polymorphic datatypes?
The inductive definition of polymorphic lists
Inductive list (X:Type) : Type :=
| nil : list X
| cons : X -> list X -> list X.
is very similar to that of [natlist]. The main difference is
that, here, the whole definition is _parameterized_ on a set [X]:
that is, we are defining a _family_ of inductive types [list X],
one for each [X]. (Note that, wherever [list] appears in the body
of the declaration, it is always applied to the parameter [X].)
The induction principle is likewise parameterized on [X]:
list_ind :
forall (X : Type) (P : list X -> Prop),
P [] ->
(forall (x : X) (l : list X), P l -> P (x :: l)) ->
forall l : list X, P l
Note the wording here (and, accordingly, the form of [list_ind]):
The _whole_ induction principle is parameterized on [X]. That is,
[list_ind] can be thought of as a polymorphic function that, when
applied to a type [X], gives us back an induction principle
specialized to the type [list X]. *)
(** **** Exercise: 1 star (tree) *)
(** Write out the induction principle that Coq will generate for
the following datatype. Compare your answer with what Coq
prints. *)
Inductive tree (X:Type) : Type :=
| leaf : X -> tree X
| node : tree X -> tree X -> tree X.
Check tree_ind.
(** [] *)
(** **** Exercise: 1 star (mytype) *)
(** Find an inductive definition that gives rise to the
following induction principle:
mytype_ind :
forall (X : Type) (P : mytype X -> Prop),
(forall x : X, P (constr1 X x)) ->
(forall n : nat, P (constr2 X n)) ->
(forall m : mytype X, P m ->
forall n : nat, P (constr3 X m n)) ->
forall m : mytype X, P m
*)
(** [] *)
(** **** Exercise: 1 star, optional (foo) *)
(** Find an inductive definition that gives rise to the
following induction principle:
foo_ind :
forall (X Y : Type) (P : foo X Y -> Prop),
(forall x : X, P (bar X Y x)) ->
(forall y : Y, P (baz X Y y)) ->
(forall f1 : nat -> foo X Y,
(forall n : nat, P (f1 n)) -> P (quux X Y f1)) ->
forall f2 : foo X Y, P f2
*)
(** [] *)
(** **** Exercise: 1 star, optional (foo') *)
(** Consider the following inductive definition: *)
Inductive foo' (X:Type) : Type :=
| C1 : list X -> foo' X -> foo' X
| C2 : foo' X.
(** What induction principle will Coq generate for [foo']? Fill
in the blanks, then check your answer with Coq.)
foo'_ind :
forall (X : Type) (P : foo' X -> Prop),
(forall (l : list X) (f : foo' X),
_______________________ ->
_______________________ ) ->
___________________________________________ ->
forall f : foo' X, ________________________
*)
(** [] *)
(* ##################################################### *)
(** ** Induction Hypotheses *)
(** Where does the phrase "induction hypothesis" fit into this story?
The induction principle for numbers
forall P : nat -> Prop,
P 0 ->
(forall n : nat, P n -> P (S n)) ->
forall n : nat, P n
is a generic statement that holds for all propositions
[P] (strictly speaking, for all families of propositions [P]
indexed by a number [n]). Each time we use this principle, we
are choosing [P] to be a particular expression of type
[nat->Prop].
We can make the proof more explicit by giving this expression a
name. For example, instead of stating the theorem [mult_0_r] as
"[forall n, n * 0 = 0]," we can write it as "[forall n, P_m0r
n]", where [P_m0r] is defined as... *)
Definition P_m0r (n:nat) : Prop :=
n * 0 = 0.
(** ... or equivalently... *)
Definition P_m0r' : nat->Prop :=
fun n => n * 0 = 0.
(** Now when we do the proof it is easier to see where [P_m0r]
appears. *)
Theorem mult_0_r'' : forall n:nat,
P_m0r n.
Proof.
apply nat_ind.
Case "n = O". reflexivity.
Case "n = S n'".
(* Note the proof state at this point! *)
unfold P_m0r. simpl. intros n' IHn'.
apply IHn'. Qed.
(** This extra naming step isn't something that we'll do in
normal proofs, but it is useful to do it explicitly for an example
or two, because it allows us to see exactly what the induction
hypothesis is. If we prove [forall n, P_m0r n] by induction on
[n] (using either [induction] or [apply nat_ind]), we see that the
first subgoal requires us to prove [P_m0r 0] ("[P] holds for
zero"), while the second subgoal requires us to prove [forall n',
P_m0r n' -> P_m0r n' (S n')] (that is "[P] holds of [S n'] if it
holds of [n']" or, more elegantly, "[P] is preserved by [S]").
The _induction hypothesis_ is the premise of this latter
implication -- the assumption that [P] holds of [n'], which we are
allowed to use in proving that [P] holds for [S n']. *)
(* ##################################################### *)
(** * Optional Material *)
(** This section offers some additional details on how induction works
in Coq and the process of building proof trees. It can safely be
skimmed on a first reading. (We recommend skimming rather than
skipping over it outright: it answers some questions that occur to
many Coq users at some point, so it is useful to have a rough idea
of what's here.) *)
(* ##################################################### *)
(** ** Induction Principles in [Prop] *)
(** Earlier, we looked in detail at the induction principles that Coq
generates for inductively defined _sets_. The induction
principles for inductively defined _propositions_ like [gorgeous]
are a tiny bit more complicated. As with all induction
principles, we want to use the induction principle on [gorgeous]
to prove things by inductively considering the possible shapes
that something in [gorgeous] can have -- either it is evidence
that [0] is gorgeous, or it is evidence that, for some [n], [3+n]
is gorgeous, or it is evidence that, for some [n], [5+n] is
gorgeous and it includes evidence that [n] itself is. Intuitively
speaking, however, what we want to prove are not statements about
_evidence_ but statements about _numbers_. So we want an
induction principle that lets us prove properties of numbers by
induction on evidence.
For example, from what we've said so far, you might expect the
inductive definition of [gorgeous]...
Inductive gorgeous : nat -> Prop :=
g_0 : gorgeous 0
| g_plus3 : forall n, gorgeous n -> gorgeous (3+m)
| g_plus5 : forall n, gorgeous n -> gorgeous (5+m).
...to give rise to an induction principle that looks like this...
gorgeous_ind_max :
forall P : (forall n : nat, gorgeous n -> Prop),
P O g_0 ->
(forall (m : nat) (e : gorgeous m),
P m e -> P (3+m) (g_plus3 m e) ->
(forall (m : nat) (e : gorgeous m),
P m e -> P (5+m) (g_plus5 m e) ->
forall (n : nat) (e : gorgeous n), P n e
... because:
- Since [gorgeous] is indexed by a number [n] (every [gorgeous]
object [e] is a piece of evidence that some particular number
[n] is gorgeous), the proposition [P] is parameterized by both
[n] and [e] -- that is, the induction principle can be used to
prove assertions involving both a gorgeous number and the
evidence that it is gorgeous.
- Since there are three ways of giving evidence of gorgeousness
([gorgeous] has three constructors), applying the induction
principle generates three subgoals:
- We must prove that [P] holds for [O] and [b_0].
- We must prove that, whenever [n] is a gorgeous
number and [e] is an evidence of its gorgeousness,
if [P] holds of [n] and [e],
then it also holds of [3+m] and [g_plus3 n e].
- We must prove that, whenever [n] is a gorgeous
number and [e] is an evidence of its gorgeousness,
if [P] holds of [n] and [e],
then it also holds of [5+m] and [g_plus5 n e].
- If these subgoals can be proved, then the induction principle
tells us that [P] is true for _all_ gorgeous numbers [n] and
evidence [e] of their gorgeousness.
But this is a little more flexibility than we actually need or
want: it is giving us a way to prove logical assertions where the
assertion involves properties of some piece of _evidence_ of
gorgeousness, while all we really care about is proving
properties of _numbers_ that are gorgeous -- we are interested in
assertions about numbers, not about evidence. It would therefore
be more convenient to have an induction principle for proving
propositions [P] that are parameterized just by [n] and whose
conclusion establishes [P] for all gorgeous numbers [n]:
forall P : nat -> Prop,
... ->
forall n : nat, gorgeous n -> P n
For this reason, Coq actually generates the following simplified
induction principle for [gorgeous]: *)
Check gorgeous_ind.
(* ===> gorgeous_ind
: forall P : nat -> Prop,
P 0 ->
(forall n : nat, gorgeous n -> P n -> P (3 + n)) ->
(forall n : nat, gorgeous n -> P n -> P (5 + n)) ->
forall n : nat, gorgeous n -> P n *)
(** In particular, Coq has dropped the evidence term [e] as a
parameter of the the proposition [P], and consequently has
rewritten the assumption [forall (n : nat) (e: gorgeous n), ...]
to be [forall (n : nat), gorgeous n -> ...]; i.e., we no longer
require explicit evidence of the provability of [gorgeous n]. *)
(** In English, [gorgeous_ind] says:
- Suppose, [P] is a property of natural numbers (that is, [P n] is
a [Prop] for every [n]). To show that [P n] holds whenever [n]
is gorgeous, it suffices to show:
- [P] holds for [0],
- for any [n], if [n] is gorgeous and [P] holds for
[n], then [P] holds for [3+n],
- for any [n], if [n] is gorgeous and [P] holds for
[n], then [P] holds for [5+n]. *)
(** We can apply [gorgeous_ind] directly instead of using [induction]. *)
Theorem gorgeous__beautiful' : forall n, gorgeous n -> beautiful n.
Proof.
intros.
apply gorgeous_ind.
Case "g_0".
apply b_0.
Case "g_plus3".
intros.
apply b_sum. apply b_3.
apply H1.
Case "g_plus5".
intros.
apply b_sum. apply b_5.
apply H1.
apply H.
Qed.
Module P.
(** **** Exercise: 3 stars, optional (p_provability) *)
(** Consider the following inductively defined proposition: *)
Inductive p : (tree nat) -> nat -> Prop :=
| c1 : forall n, p (leaf _ n) 1
| c2 : forall t1 t2 n1 n2,
p t1 n1 -> p t2 n2 -> p (node _ t1 t2) (n1 + n2)
| c3 : forall t n, p t n -> p t (S n).
(** Describe, in English, the conditions under which the
proposition [p t n] is provable.
(* FILL IN HERE *)
*)
(** [] *)
End P.
(* ##################################################### *)
(** ** More on the [induction] Tactic *)
(** The [induction] tactic actually does even more low-level
bookkeeping for us than we discussed above.
Recall the informal statement of the induction principle for
natural numbers:
- If [P n] is some proposition involving a natural number n, and
we want to show that P holds for _all_ numbers n, we can
reason like this:
- show that [P O] holds
- show that, if [P n'] holds, then so does [P (S n')]
- conclude that [P n] holds for all n.
So, when we begin a proof with [intros n] and then [induction n],
we are first telling Coq to consider a _particular_ [n] (by
introducing it into the context) and then telling it to prove
something about _all_ numbers (by using induction).
What Coq actually does in this situation, internally, is to
"re-generalize" the variable we perform induction on. For
example, in the proof above that [plus] is associative...
*)
Theorem plus_assoc' : forall n m p : nat,
n + (m + p) = (n + m) + p.
Proof.
(* ...we first introduce all 3 variables into the context,
which amounts to saying "Consider an arbitrary [n], [m], and
[p]..." *)
intros n m p.
(* ...We now use the [induction] tactic to prove [P n] (that
is, [n + (m + p) = (n + m) + p]) for _all_ [n],
and hence also for the particular [n] that is in the context
at the moment. *)
induction n as [| n'].
Case "n = O". reflexivity.
Case "n = S n'".
(* In the second subgoal generated by [induction] -- the
"inductive step" -- we must prove that [P n'] implies
[P (S n')] for all [n']. The [induction] tactic
automatically introduces [n'] and [P n'] into the context
for us, leaving just [P (S n')] as the goal. *)
simpl. rewrite -> IHn'. reflexivity. Qed.
(** It also works to apply [induction] to a variable that is
quantified in the goal. *)
Theorem plus_comm' : forall n m : nat,
n + m = m + n.
Proof.
induction n as [| n'].
Case "n = O". intros m. rewrite -> plus_0_r. reflexivity.
Case "n = S n'". intros m. simpl. rewrite -> IHn'.
rewrite <- plus_n_Sm. reflexivity. Qed.
(** Note that [induction n] leaves [m] still bound in the goal --
i.e., what we are proving inductively is a statement beginning
with [forall m].
If we do [induction] on a variable that is quantified in the goal
_after_ some other quantifiers, the [induction] tactic will
automatically introduce the variables bound by these quantifiers
into the context. *)
Theorem plus_comm'' : forall n m : nat,
n + m = m + n.
Proof.
(* Let's do induction on [m] this time, instead of [n]... *)
induction m as [| m'].
Case "m = O". simpl. rewrite -> plus_0_r. reflexivity.
Case "m = S m'". simpl. rewrite <- IHm'.
rewrite <- plus_n_Sm. reflexivity. Qed.
(** **** Exercise: 1 star, optional (plus_explicit_prop) *)
(** Rewrite both [plus_assoc'] and [plus_comm'] and their proofs in
the same style as [mult_0_r''] above -- that is, for each theorem,
give an explicit [Definition] of the proposition being proved by
induction, and state the theorem and proof in terms of this
defined proposition. *)
(* FILL IN HERE *)
(** [] *)
(* ##################################################### *)
(** One more quick digression, for adventurous souls: if we can define
parameterized propositions using [Definition], then can we also
define them using [Fixpoint]? Of course we can! However, this
kind of "recursive parameterization" doesn't correspond to
anything very familiar from everyday mathematics. The following
exercise gives a slightly contrived example. *)
(** **** Exercise: 4 stars, optional (true_upto_n__true_everywhere) *)
(** Define a recursive function
[true_upto_n__true_everywhere] that makes
[true_upto_n_example] work. *)
(*
Fixpoint true_upto_n__true_everywhere
(* FILL IN HERE *)
Example true_upto_n_example :
(true_upto_n__true_everywhere 3 (fun n => even n))
= (even 3 -> even 2 -> even 1 -> forall m : nat, even m).
Proof. reflexivity. Qed.
*)
(** [] *)
(* ####################################################### *)
(** ** Building Proof Objects Incrementally *)
(** As you probably noticed while solving the exercises earlier in the
chapter, constructing proof objects is more involved than
constructing the corresponding tactic proofs. Fortunately, there
is a bit of syntactic sugar that we've already introduced to help
in the construction: the [admit] term, which we've sometimes used
to force Coq into accepting incomplete exercies. As an example,
let's walk through the process of constructing a proof object
demonstrating the beauty of [16]. *)
Definition b_16_atmpt_1 : beautiful 16 := admit.
(** Maybe we can use [b_sum] to construct a term of type [beautiful 16]?
Recall that [b_sum] is of type
forall n m : nat, beautiful n -> beautiful m -> beautiful (n + m)
If we can demonstrate the beauty of [5] and [11], we should
be done. *)
Definition b_16_atmpt_2 : beautiful 16 := b_sum 5 11 admit admit.
(** In the attempt above, we've omitted the proofs of the propositions
that [5] and [11] are beautiful. But the first of these is already
axiomatized in [b_5]: *)
Definition b_16_atmpt_3 : beautiful 16 := b_sum 5 11 b_5 admit.
(** What remains is to show that [11] is beautiful. We repeat the
procedure: *)
Definition b_16_atmpt_4 : beautiful 16 :=
b_sum 5 11 b_5 (b_sum 5 6 admit admit).
Definition b_16_atmpt_5 : beautiful 16 :=
b_sum 5 11 b_5 (b_sum 5 6 b_5 admit).
Definition b_16_atmpt_6 : beautiful 16 :=
b_sum 5 11 b_5 (b_sum 5 6 b_5 (b_sum 3 3 admit admit)).
(** And finally, we can complete the proof object: *)
Definition b_16 : beautiful 16 :=
b_sum 5 11 b_5 (b_sum 5 6 b_5 (b_sum 3 3 b_3 b_3)).
(** To recap, we've been guided by an informal proof that we have in
our minds, and we check the high level details before completing
the intricacies of the proof. The [admit] term allows us to do
this. *)
(* ####################################################### *)
(** * Additional Exercises *)
(** **** Exercise: 4 stars, recommended (palindromes) *)
(** A palindrome is a sequence that reads the same backwards as
forwards.
- Define an inductive proposition [pal] on [list X] that
captures what it means to be a palindrome. (Hint: You'll need
three cases. Your definition should be based on the structure
of the list; just having a single constructor
c : forall l, l = rev l -> pal l
may seem obvious, but will not work very well.)
- Prove that
forall l, pal (l ++ rev l).
- Prove that
forall l, pal l -> l = rev l.
*)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 5 stars, optional (palindrome_converse) *)
(** Using your definition of [pal] from the previous exercise, prove
that
forall l, l = rev l -> pal l.
*)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 4 stars (subsequence) *)
(** A list is a _subsequence_ of another list if all of the elements
in the first list occur in the same order in the second list,
possibly with some extra elements in between. For example,
[1,2,3]
is a subsequence of each of the lists
[1,2,3]
[1,1,1,2,2,3]
[1,2,7,3]
[5,6,1,9,9,2,7,3,8]
but it is _not_ a subsequence of any of the lists
[1,2]
[1,3]
[5,6,2,1,7,3,8]
- Define an inductive proposition [subseq] on [list nat] that
captures what it means to be a subsequence. (Hint: You'll need
three cases.)
- Prove that subsequence is reflexive, that is, any list is a
subsequence of itself.
- Prove that for any lists [l1], [l2], and [l3], if [l1] is a
subsequence of [l2], then [l1] is also a subsequence of [l2 ++
l3].
- (Optional, harder) Prove that subsequence is transitive -- that
is, if [l1] is a subsequence of [l2] and [l2] is a subsequence
of [l3], then [l1] is a subsequence of [l3]. Hint: choose your
induction carefully!
*)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 2 stars, optional (foo_ind_principle) *)
(** Suppose we make the following inductive definition:
Inductive foo (X : Set) (Y : Set) : Set :=
| foo1 : X -> foo X Y
| foo2 : Y -> foo X Y
| foo3 : foo X Y -> foo X Y.
Fill in the blanks to complete the induction principle that will be
generated by Coq.
foo_ind
: forall (X Y : Set) (P : foo X Y -> Prop),
(forall x : X, __________________________________) ->
(forall y : Y, __________________________________) ->
(________________________________________________) ->
________________________________________________
*)
(** [] *)
(** **** Exercise: 2 stars, optional (bar_ind_principle) *)
(** Consider the following induction principle:
bar_ind
: forall P : bar -> Prop,
(forall n : nat, P (bar1 n)) ->
(forall b : bar, P b -> P (bar2 b)) ->
(forall (b : bool) (b0 : bar), P b0 -> P (bar3 b b0)) ->
forall b : bar, P b
Write out the corresponding inductive set definition.
Inductive bar : Set :=
| bar1 : ________________________________________
| bar2 : ________________________________________
| bar3 : ________________________________________.
*)
(** [] *)
(** **** Exercise: 2 stars, optional (no_longer_than_ind) *)
(** Given the following inductively defined proposition:
Inductive no_longer_than (X : Set) : (list X) -> nat -> Prop :=
| nlt_nil : forall n, no_longer_than X [] n
| nlt_cons : forall x l n, no_longer_than X l n ->
no_longer_than X (x::l) (S n)
| nlt_succ : forall l n, no_longer_than X l n ->
no_longer_than X l (S n).
write the induction principle generated by Coq.
no_longer_than_ind
: forall (X : Set) (P : list X -> nat -> Prop),
(forall n : nat, ____________________) ->
(forall (x : X) (l : list X) (n : nat),
no_longer_than X l n -> ____________________ ->
_____________________________ ->
(forall (l : list X) (n : nat),
no_longer_than X l n -> ____________________ ->
_____________________________ ->
forall (l : list X) (n : nat), no_longer_than X l n ->
____________________
*)
(** [] *)
(** **** Exercise: 2 stars, optional (R_provability) *)
(** Suppose we give Coq the following definition:
Inductive R : nat -> list nat -> Prop :=
| c1 : R 0 []
| c2 : forall n l, R n l -> R (S n) (n :: l)
| c3 : forall n l, R (S n) l -> R n l.
Which of the following propositions are provable?
- [R 2 [1,0]]
- [R 1 [1,2,1,0]]
- [R 6 [3,2,1,0]]
*)
(** [] *)
(* ##################################################### *)
(* ##################################################### *)
(* ##################################################### *)
(* ##################################################### *)
|
`timescale 1 ns / 1 ps
// Simple counter for BRAM addressing
//
// Write enable is set to 1 for one cycle
// after a rising edge is detected on the trigger
module address_counter #
(
parameter integer COUNT_WIDTH = 13
)
(
input wire clken, // Clock enable
input wire trig, // Trigger
input wire clk,
output wire [31:0] address,
output wire [3:0] wen // Write enable
);
localparam count_max = (1 << COUNT_WIDTH) - 1;
reg trig_reg;
reg trig_detected;
reg wen_reg;
reg [COUNT_WIDTH-1:0] count;
initial count = 0;
initial trig_detected = 0;
initial wen_reg = 0;
always @(posedge clk) begin
trig_reg <= trig;
// Rising edge detection
if (trig & ~trig_reg) begin
trig_detected <= 1;
end else if (count == count_max) begin
trig_detected <= 0;
end
end
always @(posedge clk) begin
if (clken) begin
count <= count + 1;
if (count == count_max) begin
wen_reg <= trig_detected;
end
end
end
assign address = count << 2;
assign wen = {4{wen_reg}};
endmodule
|
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//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosII_system_nios2_0_oci_test_bench (
// inputs:
dct_buffer,
dct_count,
test_ending,
test_has_ended
)
;
input [ 29: 0] dct_buffer;
input [ 3: 0] dct_count;
input test_ending;
input test_has_ended;
endmodule
|
// --------------------------------------------------------------------------------
//| Avalon ST Idle Remover
// --------------------------------------------------------------------------------
`timescale 1ns / 100ps
module altera_avalon_st_idle_remover (
// Interface: clk
input clk,
input reset_n,
// Interface: ST in
output reg in_ready,
input in_valid,
input [7: 0] in_data,
// Interface: ST out
input out_ready,
output reg out_valid,
output reg [7: 0] out_data
);
// ---------------------------------------------------------------------
//| Signal Declarations
// ---------------------------------------------------------------------
reg received_esc;
wire escape_char, idle_char;
// ---------------------------------------------------------------------
//| Thingofamagick
// ---------------------------------------------------------------------
assign idle_char = (in_data == 8'h4a);
assign escape_char = (in_data == 8'h4d);
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
received_esc <= 0;
end else begin
if (in_valid & in_ready) begin
if (escape_char & ~received_esc) begin
received_esc <= 1;
end else if (out_valid) begin
received_esc <= 0;
end
end
end
end
always @* begin
in_ready = out_ready;
//out valid when in_valid. Except when we get idle or escape
//however, if we have received an escape character, then we are valid
out_valid = in_valid & ~idle_char & (received_esc | ~escape_char);
out_data = received_esc ? (in_data ^ 8'h20) : in_data;
end
endmodule
|
module serial_tx #(
parameter CLK_PER_BIT = 50
)(
input clk,
input rst,
output tx,
input block,
output busy,
input [7:0] data,
input new_data
);
// clog2 is 'ceiling of log base 2' which gives you the number of bits needed to store a value
parameter CTR_SIZE = $clog2(CLK_PER_BIT);
localparam STATE_SIZE = 2;
localparam IDLE = 2'd0,
START_BIT = 2'd1,
DATA = 2'd2,
STOP_BIT = 2'd3;
reg [CTR_SIZE-1:0] ctr_d, ctr_q;
reg [2:0] bit_ctr_d, bit_ctr_q;
reg [7:0] data_d, data_q;
reg [STATE_SIZE-1:0] state_d, state_q = IDLE;
reg tx_d, tx_q;
reg busy_d, busy_q;
reg block_d, block_q;
assign tx = tx_q;
assign busy = busy_q;
always @(*) begin
block_d = block;
ctr_d = ctr_q;
bit_ctr_d = bit_ctr_q;
data_d = data_q;
state_d = state_q;
busy_d = busy_q;
case (state_q)
IDLE: begin
if (block_q) begin
busy_d = 1'b1;
tx_d = 1'b1;
end else begin
busy_d = 1'b0;
tx_d = 1'b1;
bit_ctr_d = 3'b0;
ctr_d = 1'b0;
if (new_data) begin
data_d = data;
state_d = START_BIT;
busy_d = 1'b1;
end
end
end
START_BIT: begin
busy_d = 1'b1;
ctr_d = ctr_q + 1'b1;
tx_d = 1'b0;
if (ctr_q == CLK_PER_BIT - 1) begin
ctr_d = 1'b0;
state_d = DATA;
end
end
DATA: begin
busy_d = 1'b1;
tx_d = data_q[bit_ctr_q];
ctr_d = ctr_q + 1'b1;
if (ctr_q == CLK_PER_BIT - 1) begin
ctr_d = 1'b0;
bit_ctr_d = bit_ctr_q + 1'b1;
if (bit_ctr_q == 7) begin
state_d = STOP_BIT;
end
end
end
STOP_BIT: begin
busy_d = 1'b1;
tx_d = 1'b1;
ctr_d = ctr_q + 1'b1;
if (ctr_q == CLK_PER_BIT - 1) begin
state_d = IDLE;
end
end
default: begin
state_d = IDLE;
end
endcase
end
always @(posedge clk) begin
if (rst) begin
state_q <= IDLE;
tx_q <= 1'b1;
end else begin
state_q <= state_d;
tx_q <= tx_d;
end
block_q <= block_d;
data_q <= data_d;
bit_ctr_q <= bit_ctr_d;
ctr_q <= ctr_d;
busy_q <= busy_d;
end
endmodule |
/*main function
1)parsing packet header
2)fetch the keys from packet header include l3_protocol ,tos,l4_protocol,source ip,derection ip,source port derection port ,tcp_flag icmp layer_type and icmp code
3)combine keys to prepad
*/
/******************************* the prepad format********************************************/
/*
four pats prepad format:
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-++-+-+-+-+-+-+-+-+-+-+-+-++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-++-+-+-+-+-+-+-+-+-+-+-+-++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-++-+-+-+-+-+
ipv4_uc|ipv4_mc|umknown|arp|rarp|mpls_uc|ttl 0or1|option|ppp_ctrl|ipv6_mc|fragment|subsequent|isis|ipv6_link_local|drop|out_vlan|in_vlan|L3infhandle|local__port_port_index|l2_stake|pad2|l3_stake|net_diagnosis|pad|timestamp_2B
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-++-+-+-+-+-+-+-+-+-+-+-+-++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-++-+-+-+-+-+-+-+-+-+-+-+-++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-++-+-+-+-+-+
timestamp_6B|L3_protocol|Tos|L4_protocol|source ip|derection ip_2B
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-++-+-+-+-+-+-+-+-+-+-+-+-++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-++-+-+-+-+-+-+-+-+-+-+-+-++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-++-+-+-+-+-+
derection ip_2B|source port|derection port|tcp_flag|pad_9B
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-++-+-+-+-+-+-+-+-+-+-+-+-++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-++-+-+-+-+-+-+-+-+-+-+-+-++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-++-+-+-+-+-+
pad_16B
*/
//*********************the structure of packet parsing******************************************/
/*
|--->TCP
| --->IP----
| |----ICMP
ethernet----
|
| --->unknown
*/
`timescale 1 ps / 1 ps
module CLASSIFY(
input clk,
input reset,
input in_ingress_key_wr,// the key write request of inputctrl to classfy
input [133:0] in_ingress_key,// the key of inputctrl to classfy
input in_ingress_valid_wr,//the valid flag write request of inputctrl to classfy
input in_ingress_valid,//the valid flag of inputctrl to classfy
output out_ingress_key_almostfull,//the valid fifo almostfull signal of classfy to inputctrl
output reg out_offset_key_wr,// the key write request of classfy to inputctrl
output reg [133:0] out_offset_key,// the key of classfy to inputctrl
output reg out_offset_valid,// the valid flag of classfy to inputctrl
output reg out_offset_valid_wr,//the valid flag write request of classfy to inputctrl
input in_offset_key_almostfull//the valid fifo almostfull signal of inputctrl to classfy
);
reg [2:0] state;
wire in_ingress_valid_q; //the output valid flag from the valid flag fifo
wire in_ingress_valid_empty;//the empty signal of the valid flag fifo
reg out_ingress_valid_rd; //the read request of the valid flag fifo
wire [7:0] out_ingress_key_usedw;//the usedw signal of the key fifo
assign out_ingress_key_almostfull = out_ingress_key_usedw[7];
reg out_ingress_key_rd;//the read request of the key fifo
wire [133:0]in_ingress_key_q;//the output key from the valid flag fifo
reg is_unknown;
reg [7:0]tos;
reg [15:0]l3_protocol;
reg [7:0]l4_protocol;
reg [31:0]sip;
reg [31:0]dip;
reg [15:0]sport;
reg [15:0]dport;
reg [7:0]tcp_flag;
reg [7:0]layer_type;
reg [7:0]code;
reg tcp_icmp;
parameter idle=3'd0,
l2=3'd1,
l3=3'd2,
l4=3'd3,
prepad1=3'd4,
prepad2=3'd5,
prepad3=3'd6,
prepad4=3'd7;
always @(posedge clk or negedge reset) begin
if(!reset)begin
out_offset_key_wr<=1'b0;
out_offset_key<=134'b0;
out_offset_valid<=1'b0;
out_offset_valid_wr<=1'b0;
out_ingress_key_rd<=1'b0;
out_ingress_valid_rd<=1'b0;
is_unknown<=1'b0;
tos<=8'b0;
l3_protocol<=16'b0;
l4_protocol<=8'b0;
sip<=32'b0;
dip<=32'b0;
sport<=16'b0;
dport<=16'b0;
tcp_flag<=8'b0;
layer_type<=8'b0;
code<=8'b0;
tcp_icmp<=1'b0;
state<=idle;
end
else begin
case(state)
idle:begin// according to the in_offset_key_almostfull and in_ingress_valid_empty signals to judge whether or not the classfy module can receive packet from inputctrl
out_offset_key_wr<=1'b0;
out_offset_key<=134'b0;
out_offset_valid<=1'b0;
out_offset_valid_wr<=1'b0;
out_ingress_key_rd<=1'b0;
out_ingress_valid_rd<=1'b0;
is_unknown<=1'b0;
tos<=8'b0;
l3_protocol<=16'b0;
l4_protocol<=8'b0;
sip<=32'b0;
dip<=32'b0;
sport<=16'b0;
dport<=16'b0;
tcp_flag<=8'b0;
layer_type<=8'b0;
code<=8'b0;
tcp_icmp<=1'b0;
if(in_offset_key_almostfull==1'b0 && in_ingress_valid_empty==1'b0 )begin
out_ingress_key_rd<=1'b1;
out_ingress_valid_rd<=1'b1;
state<=l2;
end
else begin
state<=idle;
end
end
l2: begin//according to the layer_type field of the ethrnet hearder to parsing packet
out_ingress_key_rd<=1'b1;
out_ingress_valid_rd<=1'b0;
state<=l3;
if(in_ingress_key_q[31:16]==16'h0800 &&in_ingress_key_q[11:8] ==4'd5)//judge the packet whether or not a IP packet and its header length equal the 20bytes
begin
l3_protocol<=in_ingress_key_q[31:16];
tos<=in_ingress_key_q[7:0];
end
else
begin
is_unknown<=1'b1;
end
end
l3:begin//according to the protocol field of the IP hearder to judge the packet whether or not a TCP packet or ICMP packet
out_ingress_key_rd<=1'b1;
out_ingress_valid_rd<=1'b0;
if(is_unknown==1'b1)
begin
state<=l4;
end
else if(in_ingress_key_q[71:64]==8'd6|| in_ingress_key_q[71:64]==8'd1)//judge the packet whether or not a TCP packet or ICMP packet
begin
l4_protocol<=in_ingress_key_q[71:64];
sip<=in_ingress_key_q[47:16];
dip[31:16]<=in_ingress_key_q[15:0];
end
else
begin
is_unknown<=1'b1;
end
state<=l4;
end
l4:begin
out_ingress_key_rd<=1'b1;
out_ingress_valid_rd<=1'b0;
if(is_unknown==1'b1)
begin
state<=prepad1;
end
else if(l4_protocol==8'd6)
begin
dip[15:0]<=in_ingress_key_q[127:112];
sport<=in_ingress_key_q[111:96];
dport<=in_ingress_key_q[95:80];
tcp_flag<=in_ingress_key_q[7:0];
state<=prepad1;
end
else if(l4_protocol==8'd1)
begin
dip[15:0]<=in_ingress_key_q[127:112];
layer_type<=in_ingress_key_q[111:104];
code<=in_ingress_key_q[103:96];
tcp_flag<=8'b0;
end
else
begin
is_unknown<=1'b1;
end
state<=prepad1;
end
prepad1:begin//to structure the first pat prepad
out_ingress_key_rd<=1'b0;
out_ingress_valid_rd<=1'b0;
out_offset_key_wr<=1'b1;
out_offset_key<={6'b010000,3'b001,125'b0};
state<=prepad2;
end
prepad2:begin//to structure the second pat prepad
out_ingress_key_rd<=1'b0;
out_ingress_valid_rd<=1'b0;
out_offset_key_wr<=1'b1;
out_offset_key<={6'b110000,48'b0,l3_protocol,tos,l4_protocol,sip,dip[31:16]};
state<=prepad3;
end
prepad3:begin//to structure the third pat prepad
out_ingress_key_rd<=1'b0;
out_ingress_valid_rd<=1'b0;
out_offset_key_wr<=1'b1;
if(tcp_icmp==1'b0)
begin
out_offset_key<={6'b110000,dip[15:0],sport,dport,tcp_flag,72'b0};
end
else
begin
out_offset_key<={6'b110000,dip[15:0],layer_type,code,96'b0};
end
state<=prepad4;
end
prepad4:begin//to structure the fourth pat prepad
out_ingress_key_rd<=1'b0;
out_ingress_valid_rd<=1'b0;
out_offset_key_wr<=1'b1;
out_offset_key<={6'b100000,128'b0};
out_offset_valid<=1'b1;
out_offset_valid_wr<=1'b1;
state<=idle;
end
endcase
end
end
fifo_64_1 FIFO_VALID_input (
.aclr(!reset),
.data(in_ingress_valid),
.clock(clk),
.rdreq(out_ingress_valid_rd),
.wrreq(in_ingress_valid_wr),
.q(in_ingress_valid_q),
.empty(in_ingress_valid_empty)
);
fifo_256_134 FIFO_key_input (
.aclr(!reset),
.data(in_ingress_key),
.clock(clk),
.rdreq(out_ingress_key_rd),
.wrreq(in_ingress_key_wr),
.q(in_ingress_key_q),
.usedw(out_ingress_key_usedw)
);
endmodule |
//Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module cpu_0_jtag_debug_module (
// inputs:
MonDReg,
break_readreg,
clk,
clrn,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
ena,
ir_in,
jtag_state_udr,
monitor_error,
monitor_ready,
raw_tck,
reset_n,
resetlatch,
rti,
shift,
tdi,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
update,
usr1,
// outputs:
ir_out,
irq,
jdo,
jrst_n,
st_ready_test_idle,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a,
take_no_action_tracemem_a,
tdo
)
;
parameter SLD_NODE_INFO = 286279168;
output [ 1: 0] ir_out;
output irq;
output [ 37: 0] jdo;
output jrst_n;
output st_ready_test_idle;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_action_tracemem_a;
output take_action_tracemem_b;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
output take_no_action_tracemem_a;
output tdo;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input clk;
input clrn;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input ena;
input [ 1: 0] ir_in;
input jtag_state_udr;
input monitor_error;
input monitor_ready;
input raw_tck;
input reset_n;
input resetlatch;
input rti;
input shift;
input tdi;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
input update;
input usr1;
reg [ 2: 0] DRsize;
reg dr_update1;
reg dr_update2;
reg in_between_shiftdr_and_updatedr;
reg [ 1: 0] ir;
reg [ 1: 0] ir_out;
wire irq;
reg [ 37: 0] jdo;
wire jrst_n;
reg jxdr;
reg [ 37: 0] sr;
wire st_ready_test_idle;
reg st_shiftdr;
reg st_updatedr;
reg st_updateir;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_action_tracemem_a;
wire take_action_tracemem_b;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire take_no_action_tracemem_a;
wire tdo;
always @(posedge clk)
begin
dr_update1 <= st_updatedr;
dr_update2 <= dr_update1;
jxdr <= ~dr_update1 & dr_update2;
end
assign take_action_ocimem_a = jxdr && (ir == 2'b00) &&
~jdo[35] && jdo[34];
assign take_no_action_ocimem_a = jxdr && (ir == 2'b00) &&
~jdo[35] && ~jdo[34];
assign take_action_ocimem_b = jxdr && (ir == 2'b00) &&
jdo[35];
assign take_action_tracemem_a = jxdr && (ir == 2'b01) &&
~jdo[37] &&
jdo[36];
assign take_no_action_tracemem_a = jxdr && (ir == 2'b01) &&
~jdo[37] &&
~jdo[36];
assign take_action_tracemem_b = jxdr && (ir == 2'b01) &&
jdo[37];
assign take_action_break_a = jxdr && (ir == 2'b10) &&
~jdo[36] &&
jdo[37];
assign take_no_action_break_a = jxdr && (ir == 2'b10) &&
~jdo[36] &&
~jdo[37];
assign take_action_break_b = jxdr && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
jdo[37];
assign take_no_action_break_b = jxdr && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
~jdo[37];
assign take_action_break_c = jxdr && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
jdo[37];
assign take_no_action_break_c = jxdr && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
~jdo[37];
assign take_action_tracectrl = jxdr && (ir == 2'b11) &&
jdo[15];
always @(posedge raw_tck or negedge jrst_n)
begin
if (jrst_n == 0)
ir_out <= 2'b0;
else
ir_out <= {debugack, monitor_ready};
end
always @(posedge raw_tck or negedge jrst_n)
begin
if (jrst_n == 0)
begin
sr <= 0;
DRsize <= 3'b000;
end
else if (st_updateir)
begin
case (ir_in)
2'b00: begin
DRsize <= 3'b100;
end // 2'b00
2'b01: begin
DRsize <= 3'b101;
end // 2'b01
2'b10: begin
DRsize <= 3'b101;
end // 2'b10
2'b11: begin
DRsize <= 3'b010;
end // 2'b11
endcase // ir_in
ir <= ir_in;
end
else if (~shift & ~usr1 & ena & ~in_between_shiftdr_and_updatedr)
case (ir)
2'b00: begin
sr[35] <= debugack;
sr[34] <= monitor_error;
sr[33] <= resetlatch;
sr[32 : 1] <= MonDReg;
sr[0] <= monitor_ready;
end // 2'b00
2'b01: begin
sr[35 : 0] <= tracemem_trcdata;
sr[37] <= tracemem_tw;
sr[36] <= tracemem_on;
end // 2'b01
2'b10: begin
sr[37] <= trigger_state_1;
sr[36] <= dbrk_hit3_latch;
sr[35] <= dbrk_hit2_latch;
sr[34] <= dbrk_hit1_latch;
sr[33] <= dbrk_hit0_latch;
sr[32 : 1] <= break_readreg;
sr[0] <= trigbrktype;
end // 2'b10
2'b11: begin
sr[15 : 12] <= 1'b0;
sr[11 : 2] <= trc_im_addr;
sr[1] <= trc_wrap;
sr[0] <= trc_on;
end // 2'b11
endcase // ir
else if (shift & ~usr1 & ena)
case (DRsize)
3'b000: begin
sr <= {tdi, sr[37 : 2], tdi};
end // 3'b000
3'b001: begin
sr <= {tdi, sr[37 : 9], tdi, sr[7 : 1]};
end // 3'b001
3'b010: begin
sr <= {tdi, sr[37 : 17], tdi, sr[15 : 1]};
end // 3'b010
3'b011: begin
sr <= {tdi, sr[37 : 33], tdi, sr[31 : 1]};
end // 3'b011
3'b100: begin
sr <= {tdi, sr[37], tdi, sr[35 : 1]};
end // 3'b100
3'b101: begin
sr <= {tdi, sr[37 : 1]};
end // 3'b101
default: begin
sr <= {tdi, sr[37 : 2], tdi};
end // default
endcase // DRsize
end
assign tdo = sr[0];
assign st_ready_test_idle = rti;
always @(posedge raw_tck)
begin
if (~usr1 & ena & jtag_state_udr)
jdo <= sr;
end
always @(posedge raw_tck or posedge update)
begin
if (update == 1)
begin
st_shiftdr <= 1'b0;
if (usr1 & ena)
begin
st_updateir <= 1'b1;
st_updatedr <= 1'b0;
end
else if (~usr1 & ena)
begin
st_updateir <= 1'b0;
st_updatedr <= 1'b1;
end
else
begin
st_updateir <= 1'b0;
st_updatedr <= 1'b0;
end
end
else if (shift & ~usr1 & ena)
begin
st_updateir <= 1'b0;
st_updatedr <= 1'b0;
st_shiftdr <= 1'b1;
end
else
begin
st_updateir <= 1'b0;
st_updatedr <= 1'b0;
st_shiftdr <= 1'b0;
end
end
always @(posedge raw_tck or negedge jrst_n)
begin
if (jrst_n == 0)
in_between_shiftdr_and_updatedr <= 1'b0;
else if (st_shiftdr)
in_between_shiftdr_and_updatedr <= 1'b1;
else if (st_updatedr)
in_between_shiftdr_and_updatedr <= 1'b0;
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign jrst_n = reset_n;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// assign jrst_n = clrn;
//synthesis read_comments_as_HDL off
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: ddr_phy_v4_0_phy_ocd_samp.v
// /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $
// \ \ / \ Date Created: Aug 03 2009
// \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose: Controls the number of samples and generates an aggregate
//sampling result.
//
// The following shows the nesting of the sampling loop. Nominally built
// to accomodate the "complex" sampling protocol. Adapted for use with
// "simple" samplng.
//
// simple complex
//
// samples OCAL_SIMPLE_SCAN_SAMPS 1 or 50 Depends on SIM_CAL_OPTION
// rd_victim_sel 0 0 to 7
// data_cnt 1 157
//
// First it collects comparison results provided on the
// two bit "match" bus. A particular phaser tap setting may be recorded one
// or many times depending on various parameter settings.
// The two bit match bus corresponds to comparisons for the
// zero or rising phase, and the oneeighty or falling phase. The "aggregate"
// starts out as NULL and then begins collecting comparison results
// when phy_rddata_en_1 is high. The first result is always set into
// the aggregate result. Subsequent results that match aggregate, don't
// make any change. Subsequent compare results that don't match cause the aggregate
// to turn to FUZZ.
//
// A "sample" is defined as a single DRAM burst for the simple step, and
// an entire 157 DRAM data bursts across the 8 victim bits for complex.
//
// Once all samples have been taken, the samp_result is computed by
// comparing the number of successful compares against the threshold.
//
// The second function is to track and control the number of samples. For
// "simple" data, the number of samples is set by OCAL_SIMPLE_SCAN_SAMPS.
// For "complex" data, nominally
// the complex data pattern consists of a sequence of 157 DRAM chunks. This
// sequence is run with each bit in the byte designated as the "victim". This sequence
// is repeated 50 times, although when SIM_CAL_OPTION is set to none "NONE", it is only
// repeated once.
//
// This block generates oclk_calib_resume. For the simple pattern, a single DRAM
// burst is returned For complex its 157 which indicates the start of the 157*50
// sequence for a bit. samp_done is pulsed.
//
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v4_0_ddr_phy_ocd_samp #
(parameter nCK_PER_CLK = 4,
parameter OCAL_SIMPLE_SCAN_SAMPS = 2,
parameter SCAN_PCT_SAMPS_SOLID = 95,
parameter TCQ = 100,
parameter SIM_CAL_OPTION = "NONE")
(/*AUTOARG*/
// Outputs
samp_done, oclk_calib_resume, rd_victim_sel, samp_result,
// Inputs
complex_oclkdelay_calib_start, clk, rst, reset_scan,
ocal_num_samples_inc, match, phy_rddata_en_1, taps_set,
phy_rddata_en_2
);
function integer clogb2 (input integer size); // ceiling logb2
begin
size = size - 1;
for (clogb2=1; size>1; clogb2=clogb2+1)
size = size >> 1;
end
endfunction // clogb2
localparam ONE = 1;
localparam CMPLX_DATA_CNT = nCK_PER_CLK == 2 ? 157 * 2 : 157;
localparam SIMP_DATA_CNT = nCK_PER_CLK == 2 ? 2 : 1;
localparam DATA_CNT_WIDTH = nCK_PER_CLK == 2 ? 9 : 8;
localparam CMPLX_SAMPS = SIM_CAL_OPTION == "NONE" ? 50 : 1;
// Plus one because were counting in natural numbers.
localparam SAMP_CNT_WIDTH = clogb2(OCAL_SIMPLE_SCAN_SAMPS > CMPLX_SAMPS
? OCAL_SIMPLE_SCAN_SAMPS : CMPLX_SAMPS) + 1;
// Remember SAMPLES is natural number counting. One corresponds to one sample.
localparam integer SIMP_SAMPS_SOLID_THRESH = OCAL_SIMPLE_SCAN_SAMPS * SCAN_PCT_SAMPS_SOLID * 0.01;
localparam integer SIMP_SAMPS_HALF_THRESH = SIMP_SAMPS_SOLID_THRESH/2;
localparam integer CMPLX_SAMPS_SOLID_THRESH = CMPLX_SAMPS * SCAN_PCT_SAMPS_SOLID * 0.01;
localparam integer CMPLX_SAMPS_HALF_THRESH = CMPLX_SAMPS_SOLID_THRESH/2;
input complex_oclkdelay_calib_start;
wire [SAMP_CNT_WIDTH-1:0] samples = complex_oclkdelay_calib_start
? CMPLX_SAMPS[SAMP_CNT_WIDTH-1:0]
: OCAL_SIMPLE_SCAN_SAMPS[SAMP_CNT_WIDTH-1:0];
localparam [1:0] NULL = 2'b11,
FUZZ = 2'b00,
ONEEIGHTY = 2'b10,
ZERO = 2'b01;
input clk;
input rst;
input reset_scan;
// Given the need to count phy_data_en, this is not useful.
input ocal_num_samples_inc;
input [1:0] match;
input phy_rddata_en_1;
input taps_set;
reg samp_done_ns, samp_done_r;
always @(posedge clk) samp_done_r <= #TCQ samp_done_ns;
output samp_done;
assign samp_done = samp_done_r;
input phy_rddata_en_2;
wire samp_valid = samp_done_r && phy_rddata_en_2;
reg [1:0] agg_samp_ns, agg_samp_r;
always @(posedge clk) agg_samp_r <= #TCQ agg_samp_ns;
reg oclk_calib_resume_ns, oclk_calib_resume_r;
always @(posedge clk) oclk_calib_resume_r <= #TCQ oclk_calib_resume_ns;
output oclk_calib_resume;
assign oclk_calib_resume = oclk_calib_resume_r;
// Complex data counting.
// Inner most loop. 157 phy_data_en.
reg [DATA_CNT_WIDTH-1:0] data_cnt_ns, data_cnt_r;
always @(posedge clk) data_cnt_r <= #TCQ data_cnt_ns;
// Nominally, 50 samples of the above 157 phy_data_en.
reg [SAMP_CNT_WIDTH-1:0] samps_ns, samps_r;
always @(posedge clk) samps_r <= #TCQ samps_ns;
// Step through the 8 bits in the byte.
reg [2:0] rd_victim_sel_ns, rd_victim_sel_r;
always @(posedge clk) rd_victim_sel_r <= #TCQ rd_victim_sel_ns;
output [2:0] rd_victim_sel;
assign rd_victim_sel = rd_victim_sel_r;
reg [SAMP_CNT_WIDTH-1:0] zero_ns, zero_r, oneeighty_ns, oneeighty_r;
always @(posedge clk) zero_r <= #TCQ zero_ns;
always @(posedge clk) oneeighty_r <= #TCQ oneeighty_ns;
wire [SAMP_CNT_WIDTH-1:0] samp_thresh = (complex_oclkdelay_calib_start
? CMPLX_SAMPS_SOLID_THRESH[SAMP_CNT_WIDTH-1:0]
: SIMP_SAMPS_SOLID_THRESH[SAMP_CNT_WIDTH-1:0]);
wire [SAMP_CNT_WIDTH-1:0] samp_half_thresh = (complex_oclkdelay_calib_start
? CMPLX_SAMPS_HALF_THRESH[SAMP_CNT_WIDTH-1:0]
: SIMP_SAMPS_HALF_THRESH[SAMP_CNT_WIDTH-1:0]);
wire zero_ge_thresh = zero_r >= samp_thresh;
wire zero_le_half_thresh = zero_r <= samp_half_thresh;
wire oneeighty_ge_thresh = oneeighty_r >= samp_thresh;
wire oneeighty_le_half_thresh = oneeighty_r <= samp_half_thresh;
reg [1:0] samp_result_ns, samp_result_r;
always @(posedge clk) samp_result_r <= #TCQ samp_result_ns;
always @(*)
if (rst) samp_result_ns = 'b0;
else begin
samp_result_ns = samp_result_r;
if (samp_valid) begin
if (~samp_result_r[0] && zero_ge_thresh) samp_result_ns[0] = 'b1;
if (samp_result_r[0] && zero_le_half_thresh) samp_result_ns[0] = 'b0;
if (~samp_result_r[1] && oneeighty_ge_thresh) samp_result_ns[1] = 'b1;
if (samp_result_r[1] && oneeighty_le_half_thresh) samp_result_ns[1] = 'b0;
end
end
output [1:0] samp_result;
assign samp_result = samp_result_ns;
reg [0:0] sm_ns, sm_r;
always @(posedge clk) sm_r <= #TCQ sm_ns;
wire [DATA_CNT_WIDTH-1:0] data_cnt = complex_oclkdelay_calib_start
? CMPLX_DATA_CNT[DATA_CNT_WIDTH-1:0]
: SIMP_DATA_CNT[DATA_CNT_WIDTH-1:0];
wire [2:0] rd_victim_end = complex_oclkdelay_calib_start ? 3'h7 : 3'h0;
wire data_end = data_cnt_r == ONE[DATA_CNT_WIDTH-1:0];
wire samp_end = samps_r == ONE[SAMP_CNT_WIDTH-1:0];
// Primary state machine.
always @(*) begin
// Default next state assignments.
agg_samp_ns = agg_samp_r;
data_cnt_ns = data_cnt_r;
oclk_calib_resume_ns = 1'b0;
oneeighty_ns = oneeighty_r;
rd_victim_sel_ns = rd_victim_sel_r;
samp_done_ns = samp_done_r;
samps_ns = samps_r;
sm_ns = sm_r;
zero_ns = zero_r;
if (rst == 1'b1) begin
// RESET next states
sm_ns = /*AK("READY")*/1'd0;
end else
// State based actions and next states.
case (sm_r)
/*AL("READY")*/1'd0:begin
agg_samp_ns = NULL;
data_cnt_ns = data_cnt;
oneeighty_ns = 'b0;
zero_ns = 'b0;
rd_victim_sel_ns = 3'b0;
samps_ns = complex_oclkdelay_calib_start ? CMPLX_SAMPS[SAMP_CNT_WIDTH-1:0]
: OCAL_SIMPLE_SCAN_SAMPS[SAMP_CNT_WIDTH-1:0];
if (taps_set) begin
samp_done_ns = 1'b0;
sm_ns = /*AK("AWAITING_DATA")*/1'd1;
oclk_calib_resume_ns = 1'b1;
end
end
/*AL("AWAITING_DATA")*/1'd1:begin
if (phy_rddata_en_1) begin
case (agg_samp_r)
NULL : if (~&match) agg_samp_ns = match;
ZERO, ONEEIGHTY : if (~(agg_samp_r == match || &match)) agg_samp_ns = FUZZ;
FUZZ : ;
endcase // case (agg_samp_r)
if (~data_end) data_cnt_ns = data_cnt_r - ONE[DATA_CNT_WIDTH-1:0];
else begin
data_cnt_ns = data_cnt;
if (rd_victim_end != rd_victim_sel_r) rd_victim_sel_ns = rd_victim_sel_r + 3'h1;
else begin
rd_victim_sel_ns = 3'h0;
if (agg_samp_ns == ZERO) zero_ns = zero_r + ONE[SAMP_CNT_WIDTH-1:0];
if (agg_samp_ns == ONEEIGHTY) oneeighty_ns = oneeighty_r + ONE[SAMP_CNT_WIDTH-1:0];
agg_samp_ns = NULL;
if (~samp_end) samps_ns = samps_r - ONE[SAMP_CNT_WIDTH-1:0];
else samp_done_ns = 1'b1;
end
end
if (samp_done_ns) sm_ns = /*AK("READY")*/1'd0;
else oclk_calib_resume_ns = ~complex_oclkdelay_calib_start && data_end;
end
end
endcase // case (sm_r)
end // always @ begin
endmodule // mig_7series_v4_0_ddr_phy_ocd_samp
// Local Variables:
// verilog-autolabel-prefix: "1'd"
// End:
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosII_system_nios2_qsys_0_mult_cell (
// inputs:
A_mul_src1,
A_mul_src2,
clk,
reset_n,
// outputs:
A_mul_cell_result
)
;
output [ 31: 0] A_mul_cell_result;
input [ 31: 0] A_mul_src1;
input [ 31: 0] A_mul_src2;
input clk;
input reset_n;
wire [ 31: 0] A_mul_cell_result;
wire [ 31: 0] A_mul_cell_result_part_1;
wire [ 15: 0] A_mul_cell_result_part_2;
wire mul_clr;
assign mul_clr = ~reset_n;
altera_mult_add the_altmult_add_part_1
(
.aclr0 (mul_clr),
.clock0 (clk),
.dataa (A_mul_src1[15 : 0]),
.datab (A_mul_src2[15 : 0]),
.ena0 (1'b1),
.result (A_mul_cell_result_part_1)
);
defparam the_altmult_add_part_1.addnsub_multiplier_pipeline_aclr1 = "ACLR0",
the_altmult_add_part_1.addnsub_multiplier_pipeline_register1 = "CLOCK0",
the_altmult_add_part_1.addnsub_multiplier_register1 = "UNREGISTERED",
the_altmult_add_part_1.dedicated_multiplier_circuitry = "YES",
the_altmult_add_part_1.input_register_a0 = "UNREGISTERED",
the_altmult_add_part_1.input_register_b0 = "UNREGISTERED",
the_altmult_add_part_1.input_source_a0 = "DATAA",
the_altmult_add_part_1.input_source_b0 = "DATAB",
the_altmult_add_part_1.lpm_type = "altera_mult_add",
the_altmult_add_part_1.multiplier1_direction = "ADD",
the_altmult_add_part_1.multiplier_aclr0 = "ACLR0",
the_altmult_add_part_1.multiplier_register0 = "CLOCK0",
the_altmult_add_part_1.number_of_multipliers = 1,
the_altmult_add_part_1.output_register = "UNREGISTERED",
the_altmult_add_part_1.port_addnsub1 = "PORT_UNUSED",
the_altmult_add_part_1.port_addnsub3 = "PORT_UNUSED",
the_altmult_add_part_1.port_signa = "PORT_UNUSED",
the_altmult_add_part_1.port_signb = "PORT_UNUSED",
the_altmult_add_part_1.representation_a = "UNSIGNED",
the_altmult_add_part_1.representation_b = "UNSIGNED",
the_altmult_add_part_1.selected_device_family = "CYCLONEII",
the_altmult_add_part_1.signed_pipeline_aclr_a = "ACLR0",
the_altmult_add_part_1.signed_pipeline_aclr_b = "ACLR0",
the_altmult_add_part_1.signed_pipeline_register_a = "CLOCK0",
the_altmult_add_part_1.signed_pipeline_register_b = "CLOCK0",
the_altmult_add_part_1.signed_register_a = "UNREGISTERED",
the_altmult_add_part_1.signed_register_b = "UNREGISTERED",
the_altmult_add_part_1.width_a = 16,
the_altmult_add_part_1.width_b = 16,
the_altmult_add_part_1.width_result = 32;
altera_mult_add the_altmult_add_part_2
(
.aclr0 (mul_clr),
.clock0 (clk),
.dataa (A_mul_src1[31 : 16]),
.datab (A_mul_src2[15 : 0]),
.ena0 (1'b1),
.result (A_mul_cell_result_part_2)
);
defparam the_altmult_add_part_2.addnsub_multiplier_pipeline_aclr1 = "ACLR0",
the_altmult_add_part_2.addnsub_multiplier_pipeline_register1 = "CLOCK0",
the_altmult_add_part_2.addnsub_multiplier_register1 = "UNREGISTERED",
the_altmult_add_part_2.dedicated_multiplier_circuitry = "YES",
the_altmult_add_part_2.input_register_a0 = "UNREGISTERED",
the_altmult_add_part_2.input_register_b0 = "UNREGISTERED",
the_altmult_add_part_2.input_source_a0 = "DATAA",
the_altmult_add_part_2.input_source_b0 = "DATAB",
the_altmult_add_part_2.lpm_type = "altera_mult_add",
the_altmult_add_part_2.multiplier1_direction = "ADD",
the_altmult_add_part_2.multiplier_aclr0 = "ACLR0",
the_altmult_add_part_2.multiplier_register0 = "CLOCK0",
the_altmult_add_part_2.number_of_multipliers = 1,
the_altmult_add_part_2.output_register = "UNREGISTERED",
the_altmult_add_part_2.port_addnsub1 = "PORT_UNUSED",
the_altmult_add_part_2.port_addnsub3 = "PORT_UNUSED",
the_altmult_add_part_2.port_signa = "PORT_UNUSED",
the_altmult_add_part_2.port_signb = "PORT_UNUSED",
the_altmult_add_part_2.representation_a = "UNSIGNED",
the_altmult_add_part_2.representation_b = "UNSIGNED",
the_altmult_add_part_2.selected_device_family = "CYCLONEII",
the_altmult_add_part_2.signed_pipeline_aclr_a = "ACLR0",
the_altmult_add_part_2.signed_pipeline_aclr_b = "ACLR0",
the_altmult_add_part_2.signed_pipeline_register_a = "CLOCK0",
the_altmult_add_part_2.signed_pipeline_register_b = "CLOCK0",
the_altmult_add_part_2.signed_register_a = "UNREGISTERED",
the_altmult_add_part_2.signed_register_b = "UNREGISTERED",
the_altmult_add_part_2.width_a = 16,
the_altmult_add_part_2.width_b = 16,
the_altmult_add_part_2.width_result = 16;
assign A_mul_cell_result = {A_mul_cell_result_part_1[31 : 16] +
A_mul_cell_result_part_2,
A_mul_cell_result_part_1[15 : 0]};
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2018 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file upd77c25_datrom.v when simulating
// the core, upd77c25_datrom. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module upd77c25_datrom(
clka,
wea,
addra,
dina,
clkb,
addrb,
doutb
);
input clka;
input [0 : 0] wea;
input [10 : 0] addra;
input [15 : 0] dina;
input clkb;
input [10 : 0] addrb;
output [15 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(11),
.C_ADDRB_WIDTH(11),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(1),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("spartan3"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(1),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(1536),
.C_READ_DEPTH_B(1536),
.C_READ_WIDTH_A(16),
.C_READ_WIDTH_B(16),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(1536),
.C_WRITE_DEPTH_B(1536),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(16),
.C_WRITE_WIDTH_B(16),
.C_XDEVICEFAMILY("spartan3")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.CLKB(clkb),
.ADDRB(addrb),
.DOUTB(doutb),
.RSTA(),
.ENA(),
.REGCEA(),
.DOUTA(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.DINB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_arb_hp2_3.v
*
* Date : 2012-11
*
* Description : Module that arbitrates between RD/WR requests from 2 ports.
* Used for modelling the Top_Interconnect switch.
*****************************************************************************/
module processing_system7_bfm_v2_0_arb_hp2_3(
sw_clk,
rstn,
w_qos_hp2,
r_qos_hp2,
w_qos_hp3,
r_qos_hp3,
wr_ack_ddr_hp2,
wr_data_hp2,
wr_addr_hp2,
wr_bytes_hp2,
wr_dv_ddr_hp2,
rd_req_ddr_hp2,
rd_addr_hp2,
rd_bytes_hp2,
rd_data_ddr_hp2,
rd_dv_ddr_hp2,
wr_ack_ddr_hp3,
wr_data_hp3,
wr_addr_hp3,
wr_bytes_hp3,
wr_dv_ddr_hp3,
rd_req_ddr_hp3,
rd_addr_hp3,
rd_bytes_hp3,
rd_data_ddr_hp3,
rd_dv_ddr_hp3,
ddr_wr_ack,
ddr_wr_dv,
ddr_rd_req,
ddr_rd_dv,
ddr_rd_qos,
ddr_wr_qos,
ddr_wr_addr,
ddr_wr_data,
ddr_wr_bytes,
ddr_rd_addr,
ddr_rd_data,
ddr_rd_bytes
);
`include "processing_system7_bfm_v2_0_local_params.v"
input sw_clk;
input rstn;
input [axi_qos_width-1:0] w_qos_hp2;
input [axi_qos_width-1:0] r_qos_hp2;
input [axi_qos_width-1:0] w_qos_hp3;
input [axi_qos_width-1:0] r_qos_hp3;
input [axi_qos_width-1:0] ddr_rd_qos;
input [axi_qos_width-1:0] ddr_wr_qos;
output wr_ack_ddr_hp2;
input [max_burst_bits-1:0] wr_data_hp2;
input [addr_width-1:0] wr_addr_hp2;
input [max_burst_bytes_width:0] wr_bytes_hp2;
output wr_dv_ddr_hp2;
input rd_req_ddr_hp2;
input [addr_width-1:0] rd_addr_hp2;
input [max_burst_bytes_width:0] rd_bytes_hp2;
output [max_burst_bits-1:0] rd_data_ddr_hp2;
output rd_dv_ddr_hp2;
output wr_ack_ddr_hp3;
input [max_burst_bits-1:0] wr_data_hp3;
input [addr_width-1:0] wr_addr_hp3;
input [max_burst_bytes_width:0] wr_bytes_hp3;
output wr_dv_ddr_hp3;
input rd_req_ddr_hp3;
input [addr_width-1:0] rd_addr_hp3;
input [max_burst_bytes_width:0] rd_bytes_hp3;
output [max_burst_bits-1:0] rd_data_ddr_hp3;
output rd_dv_ddr_hp3;
input ddr_wr_ack;
output ddr_wr_dv;
output [addr_width-1:0]ddr_wr_addr;
output [max_burst_bits-1:0]ddr_wr_data;
output [max_burst_bytes_width:0]ddr_wr_bytes;
input ddr_rd_dv;
input [max_burst_bits-1:0] ddr_rd_data;
output ddr_rd_req;
output [addr_width-1:0] ddr_rd_addr;
output [max_burst_bytes_width:0] ddr_rd_bytes;
processing_system7_bfm_v2_0_arb_wr ddr_hp_wr(
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(w_qos_hp2),
.qos2(w_qos_hp3),
.prt_dv1(wr_dv_ddr_hp2),
.prt_dv2(wr_dv_ddr_hp3),
.prt_data1(wr_data_hp2),
.prt_data2(wr_data_hp3),
.prt_addr1(wr_addr_hp2),
.prt_addr2(wr_addr_hp3),
.prt_bytes1(wr_bytes_hp2),
.prt_bytes2(wr_bytes_hp3),
.prt_ack1(wr_ack_ddr_hp2),
.prt_ack2(wr_ack_ddr_hp3),
.prt_req(ddr_wr_dv),
.prt_qos(ddr_wr_qos),
.prt_data(ddr_wr_data),
.prt_addr(ddr_wr_addr),
.prt_bytes(ddr_wr_bytes),
.prt_ack(ddr_wr_ack)
);
processing_system7_bfm_v2_0_arb_rd ddr_hp_rd(
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(r_qos_hp2),
.qos2(r_qos_hp3),
.prt_req1(rd_req_ddr_hp2),
.prt_req2(rd_req_ddr_hp3),
.prt_data1(rd_data_ddr_hp2),
.prt_data2(rd_data_ddr_hp3),
.prt_addr1(rd_addr_hp2),
.prt_addr2(rd_addr_hp3),
.prt_bytes1(rd_bytes_hp2),
.prt_bytes2(rd_bytes_hp3),
.prt_dv1(rd_dv_ddr_hp2),
.prt_dv2(rd_dv_ddr_hp3),
.prt_req(ddr_rd_req),
.prt_qos(ddr_rd_qos),
.prt_data(ddr_rd_data),
.prt_addr(ddr_rd_addr),
.prt_bytes(ddr_rd_bytes),
.prt_dv(ddr_rd_dv)
);
endmodule
|
// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:dist_mem_gen:8.0
// IP Revision: 8
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module GALAGA_DROM (
a,
d,
clk,
we,
spo
);
input wire [14 : 0] a;
input wire [7 : 0] d;
input wire clk;
input wire we;
output wire [7 : 0] spo;
dist_mem_gen_v8_0 #(
.C_FAMILY("zynq"),
.C_ADDR_WIDTH(15),
.C_DEFAULT_DATA("0"),
.C_DEPTH(32768),
.C_HAS_CLK(1),
.C_HAS_D(1),
.C_HAS_DPO(0),
.C_HAS_DPRA(0),
.C_HAS_I_CE(0),
.C_HAS_QDPO(0),
.C_HAS_QDPO_CE(0),
.C_HAS_QDPO_CLK(0),
.C_HAS_QDPO_RST(0),
.C_HAS_QDPO_SRST(0),
.C_HAS_QSPO(0),
.C_HAS_QSPO_CE(0),
.C_HAS_QSPO_RST(0),
.C_HAS_QSPO_SRST(0),
.C_HAS_SPO(1),
.C_HAS_WE(1),
.C_MEM_INIT_FILE("no_coe_file_loaded"),
.C_ELABORATION_DIR("./"),
.C_MEM_TYPE(1),
.C_PIPELINE_STAGES(0),
.C_QCE_JOINED(0),
.C_QUALIFY_WE(0),
.C_READ_MIF(0),
.C_REG_A_D_INPUTS(0),
.C_REG_DPRA_INPUT(0),
.C_SYNC_ENABLE(1),
.C_WIDTH(8),
.C_PARSER_TYPE(1)
) inst (
.a(a),
.d(d),
.dpra(15'B0),
.clk(clk),
.we(we),
.i_ce(1'D1),
.qspo_ce(1'D1),
.qdpo_ce(1'D1),
.qdpo_clk(1'D0),
.qspo_rst(1'D0),
.qdpo_rst(1'D0),
.qspo_srst(1'D0),
.qdpo_srst(1'D0),
.spo(spo),
.dpo(),
.qspo(),
.qdpo()
);
endmodule
|
/*
Legal Notice: (C)2009 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details.
*/
/*
Author: JCJB
Date: 06/29/2009
This block is used to breakout the 256 bit streaming ports to and from the write master.
The information sent through the streaming ports is a bundle of wires and buses so it's
fairly inconvenient to constantly refer to them by their position amungst the 256 lines.
This block also provides a layer of abstraction since the descriptor buffers block has
no clue what format the descriptors are in except that the 'go' bit is written to. This
means that using this block you could move descriptor information around without affecting
the top level dispatcher logic.
1.0 06/29/2009 - First version of this block of wires
1.1 02/15/2011 - Added read_early_done_enable to the wire breakout
1.2 11/15/2012 - Added in an additional 32 bits of address for extended descriptors
*/
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module read_signal_breakout (
read_command_data_in, // descriptor from the read FIFO
read_command_data_out, // reformated descriptor to the read master
// breakout of command information
read_address,
read_length,
read_transmit_channel,
read_generate_sop,
read_generate_eop,
read_park,
read_transfer_complete_IRQ_mask,
read_burst_count, // when 'ENHANCED_FEATURES' is 0 this will be driven to ground
read_stride, // when 'ENHANCED_FEATURES' is 0 this will be driven to ground
read_sequence_number, // when 'ENHANCED_FEATURES' is 0 this will be driven to ground
read_transmit_error,
read_early_done_enable,
// additional control information that needs to go out asynchronously with the command data
read_stop,
read_sw_reset
);
parameter DATA_WIDTH = 256; // 256 bits when enhanced settings are enabled otherwise 128 bits
input [DATA_WIDTH-1:0] read_command_data_in;
output wire [255:0] read_command_data_out;
output wire [63:0] read_address;
output wire [31:0] read_length;
output wire [7:0] read_transmit_channel;
output wire read_generate_sop;
output wire read_generate_eop;
output wire read_park;
output wire read_transfer_complete_IRQ_mask;
output wire [7:0] read_burst_count;
output wire [15:0] read_stride;
output wire [15:0] read_sequence_number;
output wire [7:0] read_transmit_error;
output wire read_early_done_enable;
input read_stop;
input read_sw_reset;
assign read_address[31:0] = read_command_data_in[31:0];
assign read_length = read_command_data_in[95:64];
generate
if (DATA_WIDTH == 256)
begin
assign read_early_done_enable = read_command_data_in[248];
assign read_transmit_error = read_command_data_in[247:240];
assign read_transmit_channel = read_command_data_in[231:224];
assign read_generate_sop = read_command_data_in[232];
assign read_generate_eop = read_command_data_in[233];
assign read_park = read_command_data_in[234];
assign read_transfer_complete_IRQ_mask = read_command_data_in[238];
assign read_burst_count = read_command_data_in[119:112];
assign read_stride = read_command_data_in[143:128];
assign read_sequence_number = read_command_data_in[111:96];
assign read_address[63:32] = read_command_data_in[191:160];
end
else
begin
assign read_early_done_enable = read_command_data_in[120];
assign read_transmit_error = read_command_data_in[119:112];
assign read_transmit_channel = read_command_data_in[103:96];
assign read_generate_sop = read_command_data_in[104];
assign read_generate_eop = read_command_data_in[105];
assign read_park = read_command_data_in[106];
assign read_transfer_complete_IRQ_mask = read_command_data_in[110];
assign read_burst_count = 8'h00;
assign read_stride = 16'h0000;
assign read_sequence_number = 16'h0000;
assign read_address[63:32] = 32'h00000000;
end
endgenerate
// big concat statement to glue all the signals back together to go out to the read master (MSBs to LSBs)
assign read_command_data_out = {{115{1'b0}}, // zero pad the upper 115 bits
read_address[63:32],
read_early_done_enable,
read_transmit_error,
read_stride,
read_burst_count,
read_sw_reset,
read_stop,
read_generate_eop,
read_generate_sop,
read_transmit_channel,
read_length,
read_address[31:0]};
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module cf_adc_8c (
// adc interface
adc_clk_in_p,
adc_clk_in_n,
adc_data_in_p,
adc_data_in_n,
adc_frame_p,
adc_frame_n,
// dma interface
dma_clk,
dma_valid,
dma_data,
dma_be,
dma_last,
dma_ready,
// processor interface
up_rstn,
up_clk,
up_sel,
up_rwn,
up_addr,
up_wdata,
up_rdata,
up_ack,
// delay clock (200MHz)
delay_clk,
// debug interface
dma_dbg_data,
dma_dbg_trigger,
// debug interface
adc_dbg_data,
adc_dbg_trigger,
// monitor signals
adc_clk,
adc_mon_valid,
adc_mon_data);
// adc interface
input adc_clk_in_p;
input adc_clk_in_n;
input [ 7:0] adc_data_in_p;
input [ 7:0] adc_data_in_n;
input adc_frame_p;
input adc_frame_n;
// dma interface
input dma_clk;
output dma_valid;
output [63:0] dma_data;
output [ 7:0] dma_be;
output dma_last;
input dma_ready;
// processor interface
input up_rstn;
input up_clk;
input up_sel;
input up_rwn;
input [ 4:0] up_addr;
input [31:0] up_wdata;
output [31:0] up_rdata;
output up_ack;
// delay clock (200MHz)
input delay_clk;
// debug interface
output [63:0] dma_dbg_data;
output [ 7:0] dma_dbg_trigger;
// debug interface
output [63:0] adc_dbg_data;
output [ 7:0] adc_dbg_trigger;
// monitor signals
output adc_clk;
output adc_mon_valid;
output [143:0] adc_mon_data;
reg up_capture = 'd0;
reg [15:0] up_capture_count = 'd0;
reg up_dma_unf_hold = 'd0;
reg up_dma_ovf_hold = 'd0;
reg up_dma_status = 'd0;
reg [ 7:0] up_adc_pn_oos_hold = 'd0;
reg [ 7:0] up_adc_pn_err_hold = 'd0;
reg up_adc_err_hold = 'd0;
reg [ 7:0] up_pn_type = 'd0;
reg [31:0] up_rdata = 'd0;
reg up_sel_d = 'd0;
reg up_sel_2d = 'd0;
reg up_ack = 'd0;
reg up_dma_ovf_m1 = 'd0;
reg up_dma_ovf_m2 = 'd0;
reg up_dma_ovf = 'd0;
reg up_dma_unf_m1 = 'd0;
reg up_dma_unf_m2 = 'd0;
reg up_dma_unf = 'd0;
reg up_dma_complete_m1 = 'd0;
reg up_dma_complete_m2 = 'd0;
reg up_dma_complete_m3 = 'd0;
reg up_dma_complete = 'd0;
reg up_serdes_preset = 'd0;
reg up_adc_err_m1 = 'd0;
reg up_adc_err_m2 = 'd0;
reg up_adc_err = 'd0;
reg [ 7:0] up_adc_pn_oos_m1 = 'd0;
reg [ 7:0] up_adc_pn_oos_m2 = 'd0;
reg [ 7:0] up_adc_pn_oos = 'd0;
reg [ 7:0] up_adc_pn_err_m1 = 'd0;
reg [ 7:0] up_adc_pn_err_m2 = 'd0;
reg [ 7:0] up_adc_pn_err = 'd0;
wire up_wr_s;
wire up_ack_s;
wire dma_ovf_s;
wire dma_unf_s;
wire dma_complete_s;
wire adc_valid_s;
wire [63:0] adc_data_s;
wire adc_err_s;
wire [ 7:0] adc_pn_oos_s;
wire [ 7:0] adc_pn_err_s;
// processor control signals
assign up_wr_s = up_sel & ~up_rwn;
assign up_ack_s = up_sel_d & ~up_sel_2d;
// processor write interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_capture <= 'd0;
up_capture_count <= 'd0;
up_dma_unf_hold <= 'd0;
up_dma_ovf_hold <= 'd0;
up_dma_status <= 'd0;
up_adc_pn_oos_hold <= 'd0;
up_adc_pn_err_hold <= 'd0;
up_adc_err_hold <= 'd0;
up_pn_type <= 'd0;
end else begin
if ((up_addr == 5'h03) && (up_wr_s == 1'b1)) begin
up_capture <= up_wdata[16];
up_capture_count <= up_wdata[15:0];
end
if (up_dma_unf == 1'b1) begin
up_dma_unf_hold <= 1'b1;
end else if ((up_addr == 5'h04) && (up_wr_s == 1'b1)) begin
up_dma_unf_hold <= up_dma_unf_hold & ~up_wdata[2];
end
if (up_dma_ovf == 1'b1) begin
up_dma_ovf_hold <= 1'b1;
end else if ((up_addr == 5'h04) && (up_wr_s == 1'b1)) begin
up_dma_ovf_hold <= up_dma_ovf_hold & ~up_wdata[2];
end
if (up_dma_complete == 1'b1) begin
up_dma_status <= 1'b0;
end else if ((up_addr == 5'h03) && (up_wr_s == 1'b1) && (up_dma_status == 1'b0)) begin
up_dma_status <= up_wdata[16];
end
if ((up_addr == 5'h05) && (up_wr_s == 1'b1)) begin
up_adc_pn_oos_hold <= up_adc_pn_oos_hold & ~up_wdata[7:0];
end else begin
up_adc_pn_oos_hold <= up_adc_pn_oos_hold | up_adc_pn_oos;
end
if ((up_addr == 5'h05) && (up_wr_s == 1'b1)) begin
up_adc_pn_err_hold <= up_adc_pn_err_hold & ~up_wdata[15:8];
end else begin
up_adc_pn_err_hold <= up_adc_pn_err_hold | up_adc_pn_err;
end
if (up_adc_err == 1'b1) begin
up_adc_err_hold <= 1'b1;
end else if ((up_addr == 5'h05) && (up_wr_s == 1'b1)) begin
up_adc_err_hold <= up_adc_err_hold & ~up_wdata[0];
end
if ((up_addr == 5'h09) && (up_wr_s == 1'b1)) begin
up_pn_type <= up_wdata[7:0];
end
end
end
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rdata <= 'd0;
up_sel_d <= 'd0;
up_sel_2d <= 'd0;
up_ack <= 'd0;
end else begin
case (up_addr)
5'h00: up_rdata <= 32'h00010062;
5'h03: up_rdata <= {15'd0, up_capture, up_capture_count};
5'h04: up_rdata <= {29'd0, up_dma_unf_hold, up_dma_ovf_hold, up_dma_status};
5'h05: up_rdata <= {15'd0, up_adc_err_hold, up_adc_pn_err_hold, up_adc_pn_oos_hold};
5'h09: up_rdata <= {24'd0, up_pn_type};
default: up_rdata <= 0;
endcase
up_sel_d <= up_sel;
up_sel_2d <= up_sel_d;
up_ack <= up_ack_s;
end
end
// transfer status signals to processor clock domain
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_dma_ovf_m1 <= 'd0;
up_dma_ovf_m2 <= 'd0;
up_dma_ovf <= 'd0;
up_dma_unf_m1 <= 'd0;
up_dma_unf_m2 <= 'd0;
up_dma_unf <= 'd0;
up_dma_complete_m1 <= 'd0;
up_dma_complete_m2 <= 'd0;
up_dma_complete_m3 <= 'd0;
up_dma_complete <= 'd0;
end else begin
up_dma_ovf_m1 <= dma_ovf_s;
up_dma_ovf_m2 <= up_dma_ovf_m1;
up_dma_ovf <= up_dma_ovf_m2;
up_dma_unf_m1 <= dma_unf_s;
up_dma_unf_m2 <= up_dma_unf_m1;
up_dma_unf <= up_dma_unf_m2;
up_dma_complete_m1 <= dma_complete_s;
up_dma_complete_m2 <= up_dma_complete_m1;
up_dma_complete_m3 <= up_dma_complete_m2;
up_dma_complete <= up_dma_complete_m3 ^ up_dma_complete_m2;
end
end
// transfer status signals to processor clock domain
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_serdes_preset <= 'd1;
up_adc_err_m1 <= 'd0;
up_adc_err_m2 <= 'd0;
up_adc_err <= 'd0;
up_adc_pn_oos_m1 <= 'd0;
up_adc_pn_oos_m2 <= 'd0;
up_adc_pn_oos <= 'd0;
up_adc_pn_err_m1 <= 'd0;
up_adc_pn_err_m2 <= 'd0;
up_adc_pn_err <= 'd0;
end else begin
up_serdes_preset <= 'd0;
up_adc_err_m1 <= adc_err_s;
up_adc_err_m2 <= up_adc_err_m1;
up_adc_err <= up_adc_err_m2;
up_adc_pn_oos_m1 <= adc_pn_oos_s;
up_adc_pn_oos_m2 <= up_adc_pn_oos_m1;
up_adc_pn_oos <= up_adc_pn_oos_m2;
up_adc_pn_err_m1 <= adc_pn_err_s;
up_adc_pn_err_m2 <= up_adc_pn_err_m1;
up_adc_pn_err <= up_adc_pn_err_m2;
end
end
// dma write interface
cf_dma_wr i_dma_wr (
.adc_clk (adc_clk),
.adc_valid (adc_valid_s),
.adc_data (adc_data_s),
.adc_master_capture (up_capture),
.dma_clk (dma_clk),
.dma_valid (dma_valid),
.dma_data (dma_data),
.dma_be (dma_be),
.dma_last (dma_last),
.dma_ready (dma_ready),
.dma_ovf (dma_ovf_s),
.dma_unf (dma_unf_s),
.dma_complete (dma_complete_s),
.up_capture_count (up_capture_count),
.dma_dbg_data (dma_dbg_data),
.dma_dbg_trigger (dma_dbg_trigger),
.adc_dbg_data (adc_dbg_data),
.adc_dbg_trigger (adc_dbg_trigger));
// adc capture interface
cf_adc_if i_adc_if (
.adc_clk_in_p (adc_clk_in_p),
.adc_clk_in_n (adc_clk_in_n),
.adc_data_in_p (adc_data_in_p),
.adc_data_in_n (adc_data_in_n),
.adc_frame_p (adc_frame_p),
.adc_frame_n (adc_frame_n),
.adc_clk (adc_clk),
.adc_valid (adc_valid_s),
.adc_data (adc_data_s),
.adc_err (adc_err_s),
.adc_pn_oos (adc_pn_oos_s),
.adc_pn_err (adc_pn_err_s),
.up_serdes_preset (up_serdes_preset),
.up_pn_type (up_pn_type),
.adc_mon_valid (adc_mon_valid),
.adc_mon_data (adc_mon_data));
endmodule
// ***************************************************************************
// ***************************************************************************
|
/*
* Copyright (c) 2001 Stephan Boettcher <[email protected]>
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
// $Id: task_port_size.v,v 1.1 2001/07/24 04:13:49 sib4 Exp $
// PR#205
module main;
function f;
input a;
begin
f = a;
end
endfunction
reg r;
initial
begin
r <= f(32'b 101);
$display("PASSED");
end
endmodule
|
// This module will display the input values on the DE0 GPIO BOARD
// It requires the DE0 CLOCK_50 signal to be connected to it's clock input
// all other inputs can just use whatever data should be displayed.
// The one output, GPIO_0, should be connected to GPIO0_D (all 32 bits are used)
// This module works by selecting 1 of eight rows/7-seg displays at a time
// and multiplexing through the desired output signals.
module GPIO_Board(
clock_50,
R0, R1, R2, R3, R4, R5, R6, R7,
HEX0, HEX0_DP, HEX1, HEX1_DP,
HEX2, HEX2_DP, HEX3, HEX3_DP,
HEX4, HEX4_DP, HEX5, HEX5_DP,
HEX6, HEX6_DP, HEX7, HEX7_DP, GPIO_0);
input [15:0] R0, R1, R2, R3, R4, R5, R6, R7;
input [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7;
input HEX0_DP, HEX1_DP, HEX2_DP, HEX3_DP, HEX4_DP, HEX5_DP, HEX6_DP, HEX7_DP;
input clock_50;
output [31:0]GPIO_0;
// create a 17 bit counter to manage the timing of displaying the information
// bits 16:14 will be used at the 3 bit row counter / signal multiplexer select
// bits 13:11 will be used to disable the row output right before and right after
// the counter changes. This is to avoid ghosting on the display caused by hardware
// switching delay
reg [16:0]count;
wire [2:0]count3bit;
// 17 bit counter
initial
count <= 17'b0;
always @(posedge clock_50)
count <= count + 1'b1;
// create a logic circuit which will output a 0 when count[13:11] are 000 or 111
// this signal will be ANDed with the row output in order to disable the row output
// when the count3bit is close to changing.
wire row_gate;
// comment out this line and uncomment the next line to see what ghosting looks like
assign row_gate = (count[13:11] == 3'b0 || count[13:11] == 3'b111) ? 1'b0 : 1'b1;
//assign row_gate = 1'b1;
assign count3bit = count[16:14];
// use a 16 bit 8:1 MUX to select between the row input signals (R0 to R7)
wire [15:0] matrix_columns2, matrix_columns;
// output the mux to matrix_columns2 and then flip the order of the bits to display the
// binary value with the LSb on the right
mux_8to1_16bit matrix_mux(matrix_columns2, count3bit, R0, R1, R2, R3, R4, R5, R6, R7);
// flip the bits
assign matrix_columns = {matrix_columns2[0], matrix_columns2[1], matrix_columns2[2], matrix_columns2[3]
, matrix_columns2[4], matrix_columns2[5], matrix_columns2[6], matrix_columns2[7]
, matrix_columns2[8], matrix_columns2[9], matrix_columns2[10], matrix_columns2[11]
, matrix_columns2[12], matrix_columns2[13], matrix_columns2[14], matrix_columns2[15]};
// use a 8-bit 8:1 MUX to select between hex input signals (HEX0 to HEX7)
// concatenate the decimal point input with the 7-segment signal to make a 8-bit signal
wire [7:0] hex_segments;
mux8to1_8bit hex_mux(hex_segments, count3bit,
{HEX0_DP, HEX0}, {HEX1_DP, HEX1},
{HEX2_DP, HEX2}, {HEX3_DP, HEX3},
{HEX4_DP, HEX4}, {HEX5_DP, HEX5},
{HEX6_DP, HEX6}, {HEX7_DP, HEX7},
);
// use a 3-to-8 decoder to select which row to power based on the count3bit value
wire [7:0]rowa;
decoder3to8 row_dec(count3bit, rowa[0], rowa[1], rowa[2], rowa[3], rowa[4], rowa[5], rowa[6], rowa[7]);
// AND the row output of the decoder with the row_gate signal to disable the row output when close
// to switching
wire [7:0]row;
assign row = row_gate ? rowa : 8'b0;
// connect the signals to the GPIO0 output
assign GPIO_0 = {hex_segments, matrix_columns, row};
endmodule
|
//////////////////////////////////////////////////////////////////////////////////
// EncWidthConverter16to32.v for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Jinwoo Jeong <[email protected]>
// Ilyong Jung <[email protected]>
// Yong Ho Song <[email protected]>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Jinwoo Jeong <[email protected]>
// Ilyong Jung <[email protected]>
//
// Project Name: Cosmos OpenSSD
// Design Name: Data width up converter
// Module Name: EncWidthConverter16to32
// File Name: EncWidthConverter16to32.v
//
// Version: v1.0.0
//
// Description: Data width up converting unit for encoder
//
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module EncWidthConverter16to32
#
(
parameter InputDataWidth = 16,
parameter OutputDataWidth = 32
)
(
iClock ,
iReset ,
iCurLoopCount ,
iCmdType ,
iSrcDataValid ,
iSrcDataLast ,
iSrcParityLast ,
iSrcData ,
oConverterReady ,
oConvertedDataValid ,
oConvertedDataLast ,
oConvertedParityLast,
oConvertedData ,
iDstReady
);
input iClock ;
input iReset ;
input iCurLoopCount ;
input [1:0] iCmdType ;
input iSrcDataValid ;
input iSrcDataLast ;
input iSrcParityLast ;
input [InputDataWidth - 1:0] iSrcData ;
output oConverterReady ;
output oConvertedDataValid ;
output oConvertedDataLast ;
output oConvertedParityLast;
output [OutputDataWidth - 1:0] oConvertedData ;
input iDstReady ;
reg [InputDataWidth - 1:0] rShiftRegister ;
reg [InputDataWidth - 1:0] rInputRegister ;
reg rConvertedDataValid ;
reg rConvertedDataLast ;
reg rConvertedParityLast;
localparam State_Idle = 5'b00001;
localparam State_Input = 5'b00010;
localparam State_Shift = 5'b00100;
localparam State_InPause = 5'b01000;
localparam State_OutPause = 5'b10000;
reg [4:0] rCurState;
reg [4:0] rNextState;
always @ (posedge iClock)
if (iReset)
rCurState <= State_Idle;
else
rCurState <= rNextState;
always @ (*)
case (rCurState)
State_Idle:
rNextState <= (iSrcDataValid) ? State_Input : State_Idle;
State_Input:
rNextState <= (iSrcDataValid) || ((iCmdType == 2'b10) && (rConvertedParityLast)) ? State_Shift : State_InPause;
State_Shift:
if (iDstReady)
begin
if (iSrcDataValid)
rNextState <= State_Input;
else
rNextState <= State_Idle;
end
else
rNextState <= State_OutPause;
State_InPause:
rNextState <= (iSrcDataValid) ? State_Shift : State_InPause;
State_OutPause:
if (iDstReady)
begin
if (iSrcDataValid)
rNextState <= State_Input;
else
rNextState <= State_Idle;
end
else
rNextState <= State_OutPause;
endcase
always @ (posedge iClock)
if (iReset)
begin
rInputRegister <= 0;
rShiftRegister <= 0;
end
else
case (rNextState)
State_Input:
begin
rInputRegister <= iSrcData;
rShiftRegister <= 0;
end
State_Shift:
begin
rInputRegister <= iSrcData;
rShiftRegister <= rInputRegister;
end
State_InPause:
begin
rInputRegister <= rInputRegister;
rShiftRegister <= rShiftRegister;
end
State_OutPause:
begin
rInputRegister <= rInputRegister;
rShiftRegister <= rShiftRegister;
end
default:
begin
rInputRegister <= 0;
rShiftRegister <= 0;
end
endcase
always @ (posedge iClock)
if (iReset)
rConvertedDataValid <= 0;
else
case (rNextState)
State_Shift:
rConvertedDataValid <= 1'b1;
State_OutPause:
rConvertedDataValid <= 1'b1;
default:
rConvertedDataValid <= 1'b0;
endcase
always @ (posedge iClock)
if (iReset)
rConvertedParityLast <= 0;
else
if (iSrcParityLast)
rConvertedParityLast <= 1'b1;
else if (rConvertedParityLast & iDstReady & oConvertedDataValid)
rConvertedParityLast <= 1'b0;
always @ (posedge iClock)
if (iReset)
rConvertedDataLast <= 0;
else
rConvertedDataLast <= iSrcDataLast;
assign oConvertedData = {rShiftRegister, rInputRegister};
assign oConvertedDataValid = rConvertedDataValid;
assign oConverterReady = !(rNextState == State_OutPause);
assign oConvertedParityLast = (iCmdType == 2'b10) ? rConvertedParityLast & iDstReady & oConvertedDataValid :
(iCurLoopCount) ? rConvertedParityLast : iSrcParityLast;
assign oConvertedDataLast = rConvertedDataLast;
endmodule |
//
// Generated by Bluespec Compiler (build 0fccbb13)
//
//
// Ports:
// Name I/O size props
// RDY_hart0_server_reset_request_put O 1 reg
// hart0_server_reset_response_get O 1 reg
// RDY_hart0_server_reset_response_get O 1 reg
// imem_master_awvalid O 1 reg
// imem_master_awid O 4 reg
// imem_master_awaddr O 64 reg
// imem_master_awlen O 8 reg
// imem_master_awsize O 3 reg
// imem_master_awburst O 2 reg
// imem_master_awlock O 1 reg
// imem_master_awcache O 4 reg
// imem_master_awprot O 3 reg
// imem_master_awqos O 4 reg
// imem_master_awregion O 4 reg
// imem_master_wvalid O 1 reg
// imem_master_wdata O 64 reg
// imem_master_wstrb O 8 reg
// imem_master_wlast O 1 reg
// imem_master_bready O 1 reg
// imem_master_arvalid O 1 reg
// imem_master_arid O 4 reg
// imem_master_araddr O 64 reg
// imem_master_arlen O 8 reg
// imem_master_arsize O 3 reg
// imem_master_arburst O 2 reg
// imem_master_arlock O 1 reg
// imem_master_arcache O 4 reg
// imem_master_arprot O 3 reg
// imem_master_arqos O 4 reg
// imem_master_arregion O 4 reg
// imem_master_rready O 1 reg
// mem_master_awvalid O 1 reg
// mem_master_awid O 4 reg
// mem_master_awaddr O 64 reg
// mem_master_awlen O 8 reg
// mem_master_awsize O 3 reg
// mem_master_awburst O 2 reg
// mem_master_awlock O 1 reg
// mem_master_awcache O 4 reg
// mem_master_awprot O 3 reg
// mem_master_awqos O 4 reg
// mem_master_awregion O 4 reg
// mem_master_wvalid O 1 reg
// mem_master_wdata O 64 reg
// mem_master_wstrb O 8 reg
// mem_master_wlast O 1 reg
// mem_master_bready O 1 reg
// mem_master_arvalid O 1 reg
// mem_master_arid O 4 reg
// mem_master_araddr O 64 reg
// mem_master_arlen O 8 reg
// mem_master_arsize O 3 reg
// mem_master_arburst O 2 reg
// mem_master_arlock O 1 reg
// mem_master_arcache O 4 reg
// mem_master_arprot O 3 reg
// mem_master_arqos O 4 reg
// mem_master_arregion O 4 reg
// mem_master_rready O 1 reg
// dma_server_awready O 1 const
// dma_server_wready O 1 const
// dma_server_bvalid O 1 const
// dma_server_bid O 16 const
// dma_server_bresp O 2 const
// dma_server_arready O 1 const
// dma_server_rvalid O 1 const
// dma_server_rid O 16 const
// dma_server_rdata O 512 const
// dma_server_rresp O 2 const
// dma_server_rlast O 1 const
// RDY_set_verbosity O 1 const
// RDY_set_watch_tohost O 1 const
// mv_tohost_value O 64 reg
// RDY_mv_tohost_value O 1 const
// RDY_ma_ddr4_ready O 1 const
// mv_status O 8
// CLK I 1 clock
// RST_N I 1 reset
// hart0_server_reset_request_put I 1 reg
// imem_master_awready I 1
// imem_master_wready I 1
// imem_master_bvalid I 1
// imem_master_bid I 4 reg
// imem_master_bresp I 2 reg
// imem_master_arready I 1
// imem_master_rvalid I 1
// imem_master_rid I 4 reg
// imem_master_rdata I 64 reg
// imem_master_rresp I 2 reg
// imem_master_rlast I 1 reg
// mem_master_awready I 1
// mem_master_wready I 1
// mem_master_bvalid I 1
// mem_master_bid I 4 reg
// mem_master_bresp I 2 reg
// mem_master_arready I 1
// mem_master_rvalid I 1
// mem_master_rid I 4 reg
// mem_master_rdata I 64 reg
// mem_master_rresp I 2 reg
// mem_master_rlast I 1 reg
// dma_server_awvalid I 1 unused
// dma_server_awid I 16 unused
// dma_server_awaddr I 64 unused
// dma_server_awlen I 8 unused
// dma_server_awsize I 3 unused
// dma_server_awburst I 2 unused
// dma_server_awlock I 1 unused
// dma_server_awcache I 4 unused
// dma_server_awprot I 3 unused
// dma_server_awqos I 4 unused
// dma_server_awregion I 4 unused
// dma_server_wvalid I 1 unused
// dma_server_wdata I 512 unused
// dma_server_wstrb I 64 unused
// dma_server_wlast I 1 unused
// dma_server_bready I 1 unused
// dma_server_arvalid I 1 unused
// dma_server_arid I 16 unused
// dma_server_araddr I 64 unused
// dma_server_arlen I 8 unused
// dma_server_arsize I 3 unused
// dma_server_arburst I 2 unused
// dma_server_arlock I 1 unused
// dma_server_arcache I 4 unused
// dma_server_arprot I 3 unused
// dma_server_arqos I 4 unused
// dma_server_arregion I 4 unused
// dma_server_rready I 1 unused
// m_external_interrupt_req_set_not_clear I 1 reg
// s_external_interrupt_req_set_not_clear I 1 reg
// software_interrupt_req_set_not_clear I 1 reg
// timer_interrupt_req_set_not_clear I 1 reg
// nmi_req_set_not_clear I 1
// set_verbosity_verbosity I 4 reg
// set_verbosity_logdelay I 64 reg
// set_watch_tohost_watch_tohost I 1 reg
// set_watch_tohost_tohost_addr I 64 reg
// EN_hart0_server_reset_request_put I 1
// EN_set_verbosity I 1
// EN_set_watch_tohost I 1
// EN_ma_ddr4_ready I 1
// EN_hart0_server_reset_response_get I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkCPU(CLK,
RST_N,
hart0_server_reset_request_put,
EN_hart0_server_reset_request_put,
RDY_hart0_server_reset_request_put,
EN_hart0_server_reset_response_get,
hart0_server_reset_response_get,
RDY_hart0_server_reset_response_get,
imem_master_awvalid,
imem_master_awid,
imem_master_awaddr,
imem_master_awlen,
imem_master_awsize,
imem_master_awburst,
imem_master_awlock,
imem_master_awcache,
imem_master_awprot,
imem_master_awqos,
imem_master_awregion,
imem_master_awready,
imem_master_wvalid,
imem_master_wdata,
imem_master_wstrb,
imem_master_wlast,
imem_master_wready,
imem_master_bvalid,
imem_master_bid,
imem_master_bresp,
imem_master_bready,
imem_master_arvalid,
imem_master_arid,
imem_master_araddr,
imem_master_arlen,
imem_master_arsize,
imem_master_arburst,
imem_master_arlock,
imem_master_arcache,
imem_master_arprot,
imem_master_arqos,
imem_master_arregion,
imem_master_arready,
imem_master_rvalid,
imem_master_rid,
imem_master_rdata,
imem_master_rresp,
imem_master_rlast,
imem_master_rready,
mem_master_awvalid,
mem_master_awid,
mem_master_awaddr,
mem_master_awlen,
mem_master_awsize,
mem_master_awburst,
mem_master_awlock,
mem_master_awcache,
mem_master_awprot,
mem_master_awqos,
mem_master_awregion,
mem_master_awready,
mem_master_wvalid,
mem_master_wdata,
mem_master_wstrb,
mem_master_wlast,
mem_master_wready,
mem_master_bvalid,
mem_master_bid,
mem_master_bresp,
mem_master_bready,
mem_master_arvalid,
mem_master_arid,
mem_master_araddr,
mem_master_arlen,
mem_master_arsize,
mem_master_arburst,
mem_master_arlock,
mem_master_arcache,
mem_master_arprot,
mem_master_arqos,
mem_master_arregion,
mem_master_arready,
mem_master_rvalid,
mem_master_rid,
mem_master_rdata,
mem_master_rresp,
mem_master_rlast,
mem_master_rready,
dma_server_awvalid,
dma_server_awid,
dma_server_awaddr,
dma_server_awlen,
dma_server_awsize,
dma_server_awburst,
dma_server_awlock,
dma_server_awcache,
dma_server_awprot,
dma_server_awqos,
dma_server_awregion,
dma_server_awready,
dma_server_wvalid,
dma_server_wdata,
dma_server_wstrb,
dma_server_wlast,
dma_server_wready,
dma_server_bvalid,
dma_server_bid,
dma_server_bresp,
dma_server_bready,
dma_server_arvalid,
dma_server_arid,
dma_server_araddr,
dma_server_arlen,
dma_server_arsize,
dma_server_arburst,
dma_server_arlock,
dma_server_arcache,
dma_server_arprot,
dma_server_arqos,
dma_server_arregion,
dma_server_arready,
dma_server_rvalid,
dma_server_rid,
dma_server_rdata,
dma_server_rresp,
dma_server_rlast,
dma_server_rready,
m_external_interrupt_req_set_not_clear,
s_external_interrupt_req_set_not_clear,
software_interrupt_req_set_not_clear,
timer_interrupt_req_set_not_clear,
nmi_req_set_not_clear,
set_verbosity_verbosity,
set_verbosity_logdelay,
EN_set_verbosity,
RDY_set_verbosity,
set_watch_tohost_watch_tohost,
set_watch_tohost_tohost_addr,
EN_set_watch_tohost,
RDY_set_watch_tohost,
mv_tohost_value,
RDY_mv_tohost_value,
EN_ma_ddr4_ready,
RDY_ma_ddr4_ready,
mv_status);
input CLK;
input RST_N;
// action method hart0_server_reset_request_put
input hart0_server_reset_request_put;
input EN_hart0_server_reset_request_put;
output RDY_hart0_server_reset_request_put;
// actionvalue method hart0_server_reset_response_get
input EN_hart0_server_reset_response_get;
output hart0_server_reset_response_get;
output RDY_hart0_server_reset_response_get;
// value method imem_master_m_awvalid
output imem_master_awvalid;
// value method imem_master_m_awid
output [3 : 0] imem_master_awid;
// value method imem_master_m_awaddr
output [63 : 0] imem_master_awaddr;
// value method imem_master_m_awlen
output [7 : 0] imem_master_awlen;
// value method imem_master_m_awsize
output [2 : 0] imem_master_awsize;
// value method imem_master_m_awburst
output [1 : 0] imem_master_awburst;
// value method imem_master_m_awlock
output imem_master_awlock;
// value method imem_master_m_awcache
output [3 : 0] imem_master_awcache;
// value method imem_master_m_awprot
output [2 : 0] imem_master_awprot;
// value method imem_master_m_awqos
output [3 : 0] imem_master_awqos;
// value method imem_master_m_awregion
output [3 : 0] imem_master_awregion;
// value method imem_master_m_awuser
// action method imem_master_m_awready
input imem_master_awready;
// value method imem_master_m_wvalid
output imem_master_wvalid;
// value method imem_master_m_wdata
output [63 : 0] imem_master_wdata;
// value method imem_master_m_wstrb
output [7 : 0] imem_master_wstrb;
// value method imem_master_m_wlast
output imem_master_wlast;
// value method imem_master_m_wuser
// action method imem_master_m_wready
input imem_master_wready;
// action method imem_master_m_bvalid
input imem_master_bvalid;
input [3 : 0] imem_master_bid;
input [1 : 0] imem_master_bresp;
// value method imem_master_m_bready
output imem_master_bready;
// value method imem_master_m_arvalid
output imem_master_arvalid;
// value method imem_master_m_arid
output [3 : 0] imem_master_arid;
// value method imem_master_m_araddr
output [63 : 0] imem_master_araddr;
// value method imem_master_m_arlen
output [7 : 0] imem_master_arlen;
// value method imem_master_m_arsize
output [2 : 0] imem_master_arsize;
// value method imem_master_m_arburst
output [1 : 0] imem_master_arburst;
// value method imem_master_m_arlock
output imem_master_arlock;
// value method imem_master_m_arcache
output [3 : 0] imem_master_arcache;
// value method imem_master_m_arprot
output [2 : 0] imem_master_arprot;
// value method imem_master_m_arqos
output [3 : 0] imem_master_arqos;
// value method imem_master_m_arregion
output [3 : 0] imem_master_arregion;
// value method imem_master_m_aruser
// action method imem_master_m_arready
input imem_master_arready;
// action method imem_master_m_rvalid
input imem_master_rvalid;
input [3 : 0] imem_master_rid;
input [63 : 0] imem_master_rdata;
input [1 : 0] imem_master_rresp;
input imem_master_rlast;
// value method imem_master_m_rready
output imem_master_rready;
// value method mem_master_m_awvalid
output mem_master_awvalid;
// value method mem_master_m_awid
output [3 : 0] mem_master_awid;
// value method mem_master_m_awaddr
output [63 : 0] mem_master_awaddr;
// value method mem_master_m_awlen
output [7 : 0] mem_master_awlen;
// value method mem_master_m_awsize
output [2 : 0] mem_master_awsize;
// value method mem_master_m_awburst
output [1 : 0] mem_master_awburst;
// value method mem_master_m_awlock
output mem_master_awlock;
// value method mem_master_m_awcache
output [3 : 0] mem_master_awcache;
// value method mem_master_m_awprot
output [2 : 0] mem_master_awprot;
// value method mem_master_m_awqos
output [3 : 0] mem_master_awqos;
// value method mem_master_m_awregion
output [3 : 0] mem_master_awregion;
// value method mem_master_m_awuser
// action method mem_master_m_awready
input mem_master_awready;
// value method mem_master_m_wvalid
output mem_master_wvalid;
// value method mem_master_m_wdata
output [63 : 0] mem_master_wdata;
// value method mem_master_m_wstrb
output [7 : 0] mem_master_wstrb;
// value method mem_master_m_wlast
output mem_master_wlast;
// value method mem_master_m_wuser
// action method mem_master_m_wready
input mem_master_wready;
// action method mem_master_m_bvalid
input mem_master_bvalid;
input [3 : 0] mem_master_bid;
input [1 : 0] mem_master_bresp;
// value method mem_master_m_bready
output mem_master_bready;
// value method mem_master_m_arvalid
output mem_master_arvalid;
// value method mem_master_m_arid
output [3 : 0] mem_master_arid;
// value method mem_master_m_araddr
output [63 : 0] mem_master_araddr;
// value method mem_master_m_arlen
output [7 : 0] mem_master_arlen;
// value method mem_master_m_arsize
output [2 : 0] mem_master_arsize;
// value method mem_master_m_arburst
output [1 : 0] mem_master_arburst;
// value method mem_master_m_arlock
output mem_master_arlock;
// value method mem_master_m_arcache
output [3 : 0] mem_master_arcache;
// value method mem_master_m_arprot
output [2 : 0] mem_master_arprot;
// value method mem_master_m_arqos
output [3 : 0] mem_master_arqos;
// value method mem_master_m_arregion
output [3 : 0] mem_master_arregion;
// value method mem_master_m_aruser
// action method mem_master_m_arready
input mem_master_arready;
// action method mem_master_m_rvalid
input mem_master_rvalid;
input [3 : 0] mem_master_rid;
input [63 : 0] mem_master_rdata;
input [1 : 0] mem_master_rresp;
input mem_master_rlast;
// value method mem_master_m_rready
output mem_master_rready;
// action method dma_server_m_awvalid
input dma_server_awvalid;
input [15 : 0] dma_server_awid;
input [63 : 0] dma_server_awaddr;
input [7 : 0] dma_server_awlen;
input [2 : 0] dma_server_awsize;
input [1 : 0] dma_server_awburst;
input dma_server_awlock;
input [3 : 0] dma_server_awcache;
input [2 : 0] dma_server_awprot;
input [3 : 0] dma_server_awqos;
input [3 : 0] dma_server_awregion;
// value method dma_server_m_awready
output dma_server_awready;
// action method dma_server_m_wvalid
input dma_server_wvalid;
input [511 : 0] dma_server_wdata;
input [63 : 0] dma_server_wstrb;
input dma_server_wlast;
// value method dma_server_m_wready
output dma_server_wready;
// value method dma_server_m_bvalid
output dma_server_bvalid;
// value method dma_server_m_bid
output [15 : 0] dma_server_bid;
// value method dma_server_m_bresp
output [1 : 0] dma_server_bresp;
// value method dma_server_m_buser
// action method dma_server_m_bready
input dma_server_bready;
// action method dma_server_m_arvalid
input dma_server_arvalid;
input [15 : 0] dma_server_arid;
input [63 : 0] dma_server_araddr;
input [7 : 0] dma_server_arlen;
input [2 : 0] dma_server_arsize;
input [1 : 0] dma_server_arburst;
input dma_server_arlock;
input [3 : 0] dma_server_arcache;
input [2 : 0] dma_server_arprot;
input [3 : 0] dma_server_arqos;
input [3 : 0] dma_server_arregion;
// value method dma_server_m_arready
output dma_server_arready;
// value method dma_server_m_rvalid
output dma_server_rvalid;
// value method dma_server_m_rid
output [15 : 0] dma_server_rid;
// value method dma_server_m_rdata
output [511 : 0] dma_server_rdata;
// value method dma_server_m_rresp
output [1 : 0] dma_server_rresp;
// value method dma_server_m_rlast
output dma_server_rlast;
// value method dma_server_m_ruser
// action method dma_server_m_rready
input dma_server_rready;
// action method m_external_interrupt_req
input m_external_interrupt_req_set_not_clear;
// action method s_external_interrupt_req
input s_external_interrupt_req_set_not_clear;
// action method software_interrupt_req
input software_interrupt_req_set_not_clear;
// action method timer_interrupt_req
input timer_interrupt_req_set_not_clear;
// action method nmi_req
input nmi_req_set_not_clear;
// action method set_verbosity
input [3 : 0] set_verbosity_verbosity;
input [63 : 0] set_verbosity_logdelay;
input EN_set_verbosity;
output RDY_set_verbosity;
// action method set_watch_tohost
input set_watch_tohost_watch_tohost;
input [63 : 0] set_watch_tohost_tohost_addr;
input EN_set_watch_tohost;
output RDY_set_watch_tohost;
// value method mv_tohost_value
output [63 : 0] mv_tohost_value;
output RDY_mv_tohost_value;
// action method ma_ddr4_ready
input EN_ma_ddr4_ready;
output RDY_ma_ddr4_ready;
// value method mv_status
output [7 : 0] mv_status;
// signals for module outputs
wire [511 : 0] dma_server_rdata;
wire [63 : 0] imem_master_araddr,
imem_master_awaddr,
imem_master_wdata,
mem_master_araddr,
mem_master_awaddr,
mem_master_wdata,
mv_tohost_value;
wire [15 : 0] dma_server_bid, dma_server_rid;
wire [7 : 0] imem_master_arlen,
imem_master_awlen,
imem_master_wstrb,
mem_master_arlen,
mem_master_awlen,
mem_master_wstrb,
mv_status;
wire [3 : 0] imem_master_arcache,
imem_master_arid,
imem_master_arqos,
imem_master_arregion,
imem_master_awcache,
imem_master_awid,
imem_master_awqos,
imem_master_awregion,
mem_master_arcache,
mem_master_arid,
mem_master_arqos,
mem_master_arregion,
mem_master_awcache,
mem_master_awid,
mem_master_awqos,
mem_master_awregion;
wire [2 : 0] imem_master_arprot,
imem_master_arsize,
imem_master_awprot,
imem_master_awsize,
mem_master_arprot,
mem_master_arsize,
mem_master_awprot,
mem_master_awsize;
wire [1 : 0] dma_server_bresp,
dma_server_rresp,
imem_master_arburst,
imem_master_awburst,
mem_master_arburst,
mem_master_awburst;
wire RDY_hart0_server_reset_request_put,
RDY_hart0_server_reset_response_get,
RDY_ma_ddr4_ready,
RDY_mv_tohost_value,
RDY_set_verbosity,
RDY_set_watch_tohost,
dma_server_arready,
dma_server_awready,
dma_server_bvalid,
dma_server_rlast,
dma_server_rvalid,
dma_server_wready,
hart0_server_reset_response_get,
imem_master_arlock,
imem_master_arvalid,
imem_master_awlock,
imem_master_awvalid,
imem_master_bready,
imem_master_rready,
imem_master_wlast,
imem_master_wvalid,
mem_master_arlock,
mem_master_arvalid,
mem_master_awlock,
mem_master_awvalid,
mem_master_bready,
mem_master_rready,
mem_master_wlast,
mem_master_wvalid;
// register cfg_logdelay
reg [63 : 0] cfg_logdelay;
wire [63 : 0] cfg_logdelay$D_IN;
wire cfg_logdelay$EN;
// register cfg_verbosity
reg [3 : 0] cfg_verbosity;
wire [3 : 0] cfg_verbosity$D_IN;
wire cfg_verbosity$EN;
// register imem_rg_cache_addr
reg [63 : 0] imem_rg_cache_addr;
reg [63 : 0] imem_rg_cache_addr$D_IN;
wire imem_rg_cache_addr$EN;
// register imem_rg_cache_b16
reg [15 : 0] imem_rg_cache_b16;
wire [15 : 0] imem_rg_cache_b16$D_IN;
wire imem_rg_cache_b16$EN;
// register imem_rg_f3
reg [2 : 0] imem_rg_f3;
wire [2 : 0] imem_rg_f3$D_IN;
wire imem_rg_f3$EN;
// register imem_rg_mstatus_MXR
reg imem_rg_mstatus_MXR;
wire imem_rg_mstatus_MXR$D_IN, imem_rg_mstatus_MXR$EN;
// register imem_rg_pc
reg [63 : 0] imem_rg_pc;
reg [63 : 0] imem_rg_pc$D_IN;
wire imem_rg_pc$EN;
// register imem_rg_priv
reg [1 : 0] imem_rg_priv;
wire [1 : 0] imem_rg_priv$D_IN;
wire imem_rg_priv$EN;
// register imem_rg_satp
reg [63 : 0] imem_rg_satp;
wire [63 : 0] imem_rg_satp$D_IN;
wire imem_rg_satp$EN;
// register imem_rg_sstatus_SUM
reg imem_rg_sstatus_SUM;
wire imem_rg_sstatus_SUM$D_IN, imem_rg_sstatus_SUM$EN;
// register imem_rg_tval
reg [63 : 0] imem_rg_tval;
reg [63 : 0] imem_rg_tval$D_IN;
wire imem_rg_tval$EN;
// register rg_csr_pc
reg [63 : 0] rg_csr_pc;
wire [63 : 0] rg_csr_pc$D_IN;
wire rg_csr_pc$EN;
// register rg_csr_val1
reg [63 : 0] rg_csr_val1;
wire [63 : 0] rg_csr_val1$D_IN;
wire rg_csr_val1$EN;
// register rg_cur_priv
reg [1 : 0] rg_cur_priv;
reg [1 : 0] rg_cur_priv$D_IN;
wire rg_cur_priv$EN;
// register rg_epoch
reg [1 : 0] rg_epoch;
reg [1 : 0] rg_epoch$D_IN;
wire rg_epoch$EN;
// register rg_mstatus_MXR
reg rg_mstatus_MXR;
wire rg_mstatus_MXR$D_IN, rg_mstatus_MXR$EN;
// register rg_next_pc
reg [63 : 0] rg_next_pc;
reg [63 : 0] rg_next_pc$D_IN;
wire rg_next_pc$EN;
// register rg_run_on_reset
reg rg_run_on_reset;
wire rg_run_on_reset$D_IN, rg_run_on_reset$EN;
// register rg_sstatus_SUM
reg rg_sstatus_SUM;
wire rg_sstatus_SUM$D_IN, rg_sstatus_SUM$EN;
// register rg_start_CPI_cycles
reg [63 : 0] rg_start_CPI_cycles;
wire [63 : 0] rg_start_CPI_cycles$D_IN;
wire rg_start_CPI_cycles$EN;
// register rg_start_CPI_instrs
reg [63 : 0] rg_start_CPI_instrs;
wire [63 : 0] rg_start_CPI_instrs$D_IN;
wire rg_start_CPI_instrs$EN;
// register rg_state
reg [3 : 0] rg_state;
reg [3 : 0] rg_state$D_IN;
wire rg_state$EN;
// register rg_trap_info
reg [131 : 0] rg_trap_info;
reg [131 : 0] rg_trap_info$D_IN;
wire rg_trap_info$EN;
// register rg_trap_instr
reg [31 : 0] rg_trap_instr;
wire [31 : 0] rg_trap_instr$D_IN;
wire rg_trap_instr$EN;
// register rg_trap_interrupt
reg rg_trap_interrupt;
wire rg_trap_interrupt$D_IN, rg_trap_interrupt$EN;
// register stage1_rg_full
reg stage1_rg_full;
reg stage1_rg_full$D_IN;
wire stage1_rg_full$EN;
// register stage1_rg_stage_input
reg [401 : 0] stage1_rg_stage_input;
wire [401 : 0] stage1_rg_stage_input$D_IN;
wire stage1_rg_stage_input$EN;
// register stage2_rg_full
reg stage2_rg_full;
reg stage2_rg_full$D_IN;
wire stage2_rg_full$EN;
// register stage2_rg_resetting
reg stage2_rg_resetting;
wire stage2_rg_resetting$D_IN, stage2_rg_resetting$EN;
// register stage2_rg_stage2
reg [495 : 0] stage2_rg_stage2;
wire [495 : 0] stage2_rg_stage2$D_IN;
wire stage2_rg_stage2$EN;
// register stage3_rg_full
reg stage3_rg_full;
reg stage3_rg_full$D_IN;
wire stage3_rg_full$EN;
// register stage3_rg_stage3
reg [238 : 0] stage3_rg_stage3;
wire [238 : 0] stage3_rg_stage3$D_IN;
wire stage3_rg_stage3$EN;
// register stageD_rg_data
reg [233 : 0] stageD_rg_data;
wire [233 : 0] stageD_rg_data$D_IN;
wire stageD_rg_data$EN;
// register stageD_rg_full
reg stageD_rg_full;
reg stageD_rg_full$D_IN;
wire stageD_rg_full$EN;
// register stageF_rg_epoch
reg [1 : 0] stageF_rg_epoch;
reg [1 : 0] stageF_rg_epoch$D_IN;
wire stageF_rg_epoch$EN;
// register stageF_rg_full
reg stageF_rg_full;
reg stageF_rg_full$D_IN;
wire stageF_rg_full$EN;
// register stageF_rg_priv
reg [1 : 0] stageF_rg_priv;
wire [1 : 0] stageF_rg_priv$D_IN;
wire stageF_rg_priv$EN;
// ports of submodule csr_regfile
wire [193 : 0] csr_regfile$csr_trap_actions;
wire [129 : 0] csr_regfile$csr_ret_actions;
wire [64 : 0] csr_regfile$read_csr;
wire [63 : 0] csr_regfile$csr_trap_actions_pc,
csr_regfile$csr_trap_actions_xtval,
csr_regfile$mav_csr_write_word,
csr_regfile$read_csr_mcycle,
csr_regfile$read_csr_minstret,
csr_regfile$read_mstatus,
csr_regfile$read_satp,
csr_regfile$read_sstatus;
wire [27 : 0] csr_regfile$read_misa;
wire [11 : 0] csr_regfile$access_permitted_1_csr_addr,
csr_regfile$access_permitted_2_csr_addr,
csr_regfile$csr_counter_read_fault_csr_addr,
csr_regfile$mav_csr_write_csr_addr,
csr_regfile$mav_read_csr_csr_addr,
csr_regfile$read_csr_csr_addr,
csr_regfile$read_csr_port2_csr_addr;
wire [4 : 0] csr_regfile$interrupt_pending,
csr_regfile$ma_update_fcsr_fflags_flags,
csr_regfile$mv_update_fcsr_fflags_flags;
wire [3 : 0] csr_regfile$csr_trap_actions_exc_code;
wire [2 : 0] csr_regfile$read_frm;
wire [1 : 0] csr_regfile$access_permitted_1_priv,
csr_regfile$access_permitted_2_priv,
csr_regfile$csr_counter_read_fault_priv,
csr_regfile$csr_ret_actions_from_priv,
csr_regfile$csr_trap_actions_from_priv,
csr_regfile$interrupt_pending_cur_priv,
csr_regfile$ma_update_mstatus_fs_fs,
csr_regfile$mv_update_mstatus_fs_fs;
wire csr_regfile$EN_csr_minstret_incr,
csr_regfile$EN_csr_ret_actions,
csr_regfile$EN_csr_trap_actions,
csr_regfile$EN_debug,
csr_regfile$EN_ma_update_fcsr_fflags,
csr_regfile$EN_ma_update_mstatus_fs,
csr_regfile$EN_mav_csr_write,
csr_regfile$EN_mav_read_csr,
csr_regfile$EN_server_reset_request_put,
csr_regfile$EN_server_reset_response_get,
csr_regfile$RDY_server_reset_request_put,
csr_regfile$RDY_server_reset_response_get,
csr_regfile$access_permitted_1,
csr_regfile$access_permitted_1_read_not_write,
csr_regfile$access_permitted_2,
csr_regfile$access_permitted_2_read_not_write,
csr_regfile$csr_trap_actions_interrupt,
csr_regfile$csr_trap_actions_nmi,
csr_regfile$m_external_interrupt_req_set_not_clear,
csr_regfile$nmi_pending,
csr_regfile$nmi_req_set_not_clear,
csr_regfile$s_external_interrupt_req_set_not_clear,
csr_regfile$software_interrupt_req_set_not_clear,
csr_regfile$timer_interrupt_req_set_not_clear,
csr_regfile$wfi_resume;
// ports of submodule f_reset_reqs
wire f_reset_reqs$CLR,
f_reset_reqs$DEQ,
f_reset_reqs$D_IN,
f_reset_reqs$D_OUT,
f_reset_reqs$EMPTY_N,
f_reset_reqs$ENQ,
f_reset_reqs$FULL_N;
// ports of submodule f_reset_rsps
wire f_reset_rsps$CLR,
f_reset_rsps$DEQ,
f_reset_rsps$D_IN,
f_reset_rsps$D_OUT,
f_reset_rsps$EMPTY_N,
f_reset_rsps$ENQ,
f_reset_rsps$FULL_N;
// ports of submodule fpr_regfile
wire [63 : 0] fpr_regfile$read_rs1,
fpr_regfile$read_rs2,
fpr_regfile$read_rs3,
fpr_regfile$write_rd_rd_val;
wire [4 : 0] fpr_regfile$read_rs1_port2_rs1,
fpr_regfile$read_rs1_rs1,
fpr_regfile$read_rs2_rs2,
fpr_regfile$read_rs3_rs3,
fpr_regfile$write_rd_rd;
wire fpr_regfile$EN_server_reset_request_put,
fpr_regfile$EN_server_reset_response_get,
fpr_regfile$EN_write_rd,
fpr_regfile$RDY_server_reset_request_put,
fpr_regfile$RDY_server_reset_response_get;
// ports of submodule gpr_regfile
wire [63 : 0] gpr_regfile$read_rs1,
gpr_regfile$read_rs2,
gpr_regfile$write_rd_rd_val;
wire [4 : 0] gpr_regfile$read_rs1_port2_rs1,
gpr_regfile$read_rs1_rs1,
gpr_regfile$read_rs2_rs2,
gpr_regfile$write_rd_rd;
wire gpr_regfile$EN_server_reset_request_put,
gpr_regfile$EN_server_reset_response_get,
gpr_regfile$EN_write_rd,
gpr_regfile$RDY_server_reset_request_put,
gpr_regfile$RDY_server_reset_response_get;
// ports of submodule near_mem
reg [63 : 0] near_mem$dmem_req_store_value, near_mem$imem_req_addr;
wire [511 : 0] near_mem$dma_server_rdata, near_mem$dma_server_wdata;
wire [63 : 0] near_mem$dma_server_araddr,
near_mem$dma_server_awaddr,
near_mem$dma_server_wstrb,
near_mem$dmem_req_addr,
near_mem$dmem_req_satp,
near_mem$dmem_word64,
near_mem$imem_master_araddr,
near_mem$imem_master_awaddr,
near_mem$imem_master_rdata,
near_mem$imem_master_wdata,
near_mem$imem_pc,
near_mem$imem_req_satp,
near_mem$mem_master_araddr,
near_mem$mem_master_awaddr,
near_mem$mem_master_rdata,
near_mem$mem_master_wdata,
near_mem$mv_tohost_value,
near_mem$set_watch_tohost_tohost_addr;
wire [31 : 0] near_mem$imem_instr;
wire [15 : 0] near_mem$dma_server_arid,
near_mem$dma_server_awid,
near_mem$dma_server_bid,
near_mem$dma_server_rid;
wire [7 : 0] near_mem$dma_server_arlen,
near_mem$dma_server_awlen,
near_mem$imem_master_arlen,
near_mem$imem_master_awlen,
near_mem$imem_master_wstrb,
near_mem$mem_master_arlen,
near_mem$mem_master_awlen,
near_mem$mem_master_wstrb,
near_mem$mv_status,
near_mem$server_fence_request_put;
wire [6 : 0] near_mem$dmem_req_amo_funct7;
wire [3 : 0] near_mem$dma_server_arcache,
near_mem$dma_server_arqos,
near_mem$dma_server_arregion,
near_mem$dma_server_awcache,
near_mem$dma_server_awqos,
near_mem$dma_server_awregion,
near_mem$dmem_exc_code,
near_mem$imem_exc_code,
near_mem$imem_master_arcache,
near_mem$imem_master_arid,
near_mem$imem_master_arqos,
near_mem$imem_master_arregion,
near_mem$imem_master_awcache,
near_mem$imem_master_awid,
near_mem$imem_master_awqos,
near_mem$imem_master_awregion,
near_mem$imem_master_bid,
near_mem$imem_master_rid,
near_mem$mem_master_arcache,
near_mem$mem_master_arid,
near_mem$mem_master_arqos,
near_mem$mem_master_arregion,
near_mem$mem_master_awcache,
near_mem$mem_master_awid,
near_mem$mem_master_awqos,
near_mem$mem_master_awregion,
near_mem$mem_master_bid,
near_mem$mem_master_rid;
wire [2 : 0] near_mem$dma_server_arprot,
near_mem$dma_server_arsize,
near_mem$dma_server_awprot,
near_mem$dma_server_awsize,
near_mem$dmem_req_f3,
near_mem$imem_master_arprot,
near_mem$imem_master_arsize,
near_mem$imem_master_awprot,
near_mem$imem_master_awsize,
near_mem$imem_req_f3,
near_mem$mem_master_arprot,
near_mem$mem_master_arsize,
near_mem$mem_master_awprot,
near_mem$mem_master_awsize;
wire [1 : 0] near_mem$dma_server_arburst,
near_mem$dma_server_awburst,
near_mem$dma_server_bresp,
near_mem$dma_server_rresp,
near_mem$dmem_req_op,
near_mem$dmem_req_priv,
near_mem$imem_master_arburst,
near_mem$imem_master_awburst,
near_mem$imem_master_bresp,
near_mem$imem_master_rresp,
near_mem$imem_req_priv,
near_mem$mem_master_arburst,
near_mem$mem_master_awburst,
near_mem$mem_master_bresp,
near_mem$mem_master_rresp;
wire near_mem$EN_dmem_req,
near_mem$EN_imem_req,
near_mem$EN_ma_ddr4_ready,
near_mem$EN_server_fence_i_request_put,
near_mem$EN_server_fence_i_response_get,
near_mem$EN_server_fence_request_put,
near_mem$EN_server_fence_response_get,
near_mem$EN_server_reset_request_put,
near_mem$EN_server_reset_response_get,
near_mem$EN_set_watch_tohost,
near_mem$EN_sfence_vma_server_request_put,
near_mem$EN_sfence_vma_server_response_get,
near_mem$RDY_server_fence_i_request_put,
near_mem$RDY_server_fence_i_response_get,
near_mem$RDY_server_fence_request_put,
near_mem$RDY_server_fence_response_get,
near_mem$RDY_server_reset_request_put,
near_mem$RDY_server_reset_response_get,
near_mem$RDY_sfence_vma_server_request_put,
near_mem$RDY_sfence_vma_server_response_get,
near_mem$dma_server_arlock,
near_mem$dma_server_arready,
near_mem$dma_server_arvalid,
near_mem$dma_server_awlock,
near_mem$dma_server_awready,
near_mem$dma_server_awvalid,
near_mem$dma_server_bready,
near_mem$dma_server_bvalid,
near_mem$dma_server_rlast,
near_mem$dma_server_rready,
near_mem$dma_server_rvalid,
near_mem$dma_server_wlast,
near_mem$dma_server_wready,
near_mem$dma_server_wvalid,
near_mem$dmem_exc,
near_mem$dmem_req_mstatus_MXR,
near_mem$dmem_req_sstatus_SUM,
near_mem$dmem_valid,
near_mem$imem_exc,
near_mem$imem_is_i32_not_i16,
near_mem$imem_master_arlock,
near_mem$imem_master_arready,
near_mem$imem_master_arvalid,
near_mem$imem_master_awlock,
near_mem$imem_master_awready,
near_mem$imem_master_awvalid,
near_mem$imem_master_bready,
near_mem$imem_master_bvalid,
near_mem$imem_master_rlast,
near_mem$imem_master_rready,
near_mem$imem_master_rvalid,
near_mem$imem_master_wlast,
near_mem$imem_master_wready,
near_mem$imem_master_wvalid,
near_mem$imem_req_mstatus_MXR,
near_mem$imem_req_sstatus_SUM,
near_mem$imem_valid,
near_mem$mem_master_arlock,
near_mem$mem_master_arready,
near_mem$mem_master_arvalid,
near_mem$mem_master_awlock,
near_mem$mem_master_awready,
near_mem$mem_master_awvalid,
near_mem$mem_master_bready,
near_mem$mem_master_bvalid,
near_mem$mem_master_rlast,
near_mem$mem_master_rready,
near_mem$mem_master_rvalid,
near_mem$mem_master_wlast,
near_mem$mem_master_wready,
near_mem$mem_master_wvalid,
near_mem$set_watch_tohost_watch_tohost;
// ports of submodule soc_map
wire [63 : 0] soc_map$m_is_IO_addr_addr,
soc_map$m_is_mem_addr_addr,
soc_map$m_is_near_mem_IO_addr_addr,
soc_map$m_pc_reset_value;
// ports of submodule stage1_f_reset_reqs
wire stage1_f_reset_reqs$CLR,
stage1_f_reset_reqs$DEQ,
stage1_f_reset_reqs$EMPTY_N,
stage1_f_reset_reqs$ENQ,
stage1_f_reset_reqs$FULL_N;
// ports of submodule stage1_f_reset_rsps
wire stage1_f_reset_rsps$CLR,
stage1_f_reset_rsps$DEQ,
stage1_f_reset_rsps$EMPTY_N,
stage1_f_reset_rsps$ENQ,
stage1_f_reset_rsps$FULL_N;
// ports of submodule stage2_f_reset_reqs
wire stage2_f_reset_reqs$CLR,
stage2_f_reset_reqs$DEQ,
stage2_f_reset_reqs$EMPTY_N,
stage2_f_reset_reqs$ENQ,
stage2_f_reset_reqs$FULL_N;
// ports of submodule stage2_f_reset_rsps
wire stage2_f_reset_rsps$CLR,
stage2_f_reset_rsps$DEQ,
stage2_f_reset_rsps$EMPTY_N,
stage2_f_reset_rsps$ENQ,
stage2_f_reset_rsps$FULL_N;
// ports of submodule stage2_fbox
wire [63 : 0] stage2_fbox$req_v1,
stage2_fbox$req_v2,
stage2_fbox$req_v3,
stage2_fbox$word_fst;
wire [6 : 0] stage2_fbox$req_f7, stage2_fbox$req_opcode;
wire [4 : 0] stage2_fbox$req_rs2, stage2_fbox$word_snd;
wire [2 : 0] stage2_fbox$req_rm;
wire stage2_fbox$EN_req,
stage2_fbox$EN_server_reset_request_put,
stage2_fbox$EN_server_reset_response_get,
stage2_fbox$RDY_server_reset_request_put,
stage2_fbox$RDY_server_reset_response_get,
stage2_fbox$valid;
// ports of submodule stage2_mbox
wire [63 : 0] stage2_mbox$req_v1, stage2_mbox$req_v2, stage2_mbox$word;
wire [3 : 0] stage2_mbox$set_verbosity_verbosity;
wire [2 : 0] stage2_mbox$req_f3;
wire stage2_mbox$EN_req,
stage2_mbox$EN_req_reset,
stage2_mbox$EN_rsp_reset,
stage2_mbox$EN_set_verbosity,
stage2_mbox$req_is_OP_not_OP_32,
stage2_mbox$valid;
// ports of submodule stage3_f_reset_reqs
wire stage3_f_reset_reqs$CLR,
stage3_f_reset_reqs$DEQ,
stage3_f_reset_reqs$EMPTY_N,
stage3_f_reset_reqs$ENQ,
stage3_f_reset_reqs$FULL_N;
// ports of submodule stage3_f_reset_rsps
wire stage3_f_reset_rsps$CLR,
stage3_f_reset_rsps$DEQ,
stage3_f_reset_rsps$EMPTY_N,
stage3_f_reset_rsps$ENQ,
stage3_f_reset_rsps$FULL_N;
// ports of submodule stageD_f_reset_reqs
wire stageD_f_reset_reqs$CLR,
stageD_f_reset_reqs$DEQ,
stageD_f_reset_reqs$EMPTY_N,
stageD_f_reset_reqs$ENQ,
stageD_f_reset_reqs$FULL_N;
// ports of submodule stageD_f_reset_rsps
wire stageD_f_reset_rsps$CLR,
stageD_f_reset_rsps$DEQ,
stageD_f_reset_rsps$EMPTY_N,
stageD_f_reset_rsps$ENQ,
stageD_f_reset_rsps$FULL_N;
// ports of submodule stageF_branch_predictor
reg [63 : 0] stageF_branch_predictor$predict_req_pc;
wire [194 : 0] stageF_branch_predictor$bp_train_cf_info;
wire [63 : 0] stageF_branch_predictor$bp_train_pc,
stageF_branch_predictor$predict_rsp;
wire [31 : 0] stageF_branch_predictor$bp_train_instr,
stageF_branch_predictor$predict_rsp_instr;
wire stageF_branch_predictor$EN_bp_train,
stageF_branch_predictor$EN_predict_req,
stageF_branch_predictor$EN_reset,
stageF_branch_predictor$RDY_predict_req,
stageF_branch_predictor$bp_train_is_i32_not_i16,
stageF_branch_predictor$predict_rsp_is_i32_not_i16;
// ports of submodule stageF_f_reset_reqs
wire stageF_f_reset_reqs$CLR,
stageF_f_reset_reqs$DEQ,
stageF_f_reset_reqs$EMPTY_N,
stageF_f_reset_reqs$ENQ,
stageF_f_reset_reqs$FULL_N;
// ports of submodule stageF_f_reset_rsps
wire stageF_f_reset_rsps$CLR,
stageF_f_reset_rsps$DEQ,
stageF_f_reset_rsps$EMPTY_N,
stageF_f_reset_rsps$ENQ,
stageF_f_reset_rsps$FULL_N;
// rule scheduling signals
wire CAN_FIRE_RL_imem_rl_assert_fail,
CAN_FIRE_RL_imem_rl_fetch_next_32b,
CAN_FIRE_RL_rl_WFI_resume,
CAN_FIRE_RL_rl_finish_FENCE,
CAN_FIRE_RL_rl_finish_FENCE_I,
CAN_FIRE_RL_rl_finish_SFENCE_VMA,
CAN_FIRE_RL_rl_pipe,
CAN_FIRE_RL_rl_reset_complete,
CAN_FIRE_RL_rl_reset_from_WFI,
CAN_FIRE_RL_rl_reset_start,
CAN_FIRE_RL_rl_show_pipe,
CAN_FIRE_RL_rl_stage1_CSRR_S_or_C,
CAN_FIRE_RL_rl_stage1_CSRR_S_or_C_2,
CAN_FIRE_RL_rl_stage1_CSRR_W,
CAN_FIRE_RL_rl_stage1_CSRR_W_2,
CAN_FIRE_RL_rl_stage1_FENCE,
CAN_FIRE_RL_rl_stage1_FENCE_I,
CAN_FIRE_RL_rl_stage1_SFENCE_VMA,
CAN_FIRE_RL_rl_stage1_WFI,
CAN_FIRE_RL_rl_stage1_interrupt,
CAN_FIRE_RL_rl_stage1_restart_after_csrrx,
CAN_FIRE_RL_rl_stage1_trap,
CAN_FIRE_RL_rl_stage1_xRET,
CAN_FIRE_RL_rl_stage2_nonpipe,
CAN_FIRE_RL_rl_trap,
CAN_FIRE_RL_rl_trap_fetch,
CAN_FIRE_RL_stage1_rl_reset,
CAN_FIRE_RL_stage2_rl_reset_begin,
CAN_FIRE_RL_stage2_rl_reset_end,
CAN_FIRE_RL_stage3_rl_reset,
CAN_FIRE_RL_stageD_rl_reset,
CAN_FIRE_RL_stageF_rl_reset,
CAN_FIRE_dma_server_m_arvalid,
CAN_FIRE_dma_server_m_awvalid,
CAN_FIRE_dma_server_m_bready,
CAN_FIRE_dma_server_m_rready,
CAN_FIRE_dma_server_m_wvalid,
CAN_FIRE_hart0_server_reset_request_put,
CAN_FIRE_hart0_server_reset_response_get,
CAN_FIRE_imem_master_m_arready,
CAN_FIRE_imem_master_m_awready,
CAN_FIRE_imem_master_m_bvalid,
CAN_FIRE_imem_master_m_rvalid,
CAN_FIRE_imem_master_m_wready,
CAN_FIRE_m_external_interrupt_req,
CAN_FIRE_ma_ddr4_ready,
CAN_FIRE_mem_master_m_arready,
CAN_FIRE_mem_master_m_awready,
CAN_FIRE_mem_master_m_bvalid,
CAN_FIRE_mem_master_m_rvalid,
CAN_FIRE_mem_master_m_wready,
CAN_FIRE_nmi_req,
CAN_FIRE_s_external_interrupt_req,
CAN_FIRE_set_verbosity,
CAN_FIRE_set_watch_tohost,
CAN_FIRE_software_interrupt_req,
CAN_FIRE_timer_interrupt_req,
WILL_FIRE_RL_imem_rl_assert_fail,
WILL_FIRE_RL_imem_rl_fetch_next_32b,
WILL_FIRE_RL_rl_WFI_resume,
WILL_FIRE_RL_rl_finish_FENCE,
WILL_FIRE_RL_rl_finish_FENCE_I,
WILL_FIRE_RL_rl_finish_SFENCE_VMA,
WILL_FIRE_RL_rl_pipe,
WILL_FIRE_RL_rl_reset_complete,
WILL_FIRE_RL_rl_reset_from_WFI,
WILL_FIRE_RL_rl_reset_start,
WILL_FIRE_RL_rl_show_pipe,
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C,
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2,
WILL_FIRE_RL_rl_stage1_CSRR_W,
WILL_FIRE_RL_rl_stage1_CSRR_W_2,
WILL_FIRE_RL_rl_stage1_FENCE,
WILL_FIRE_RL_rl_stage1_FENCE_I,
WILL_FIRE_RL_rl_stage1_SFENCE_VMA,
WILL_FIRE_RL_rl_stage1_WFI,
WILL_FIRE_RL_rl_stage1_interrupt,
WILL_FIRE_RL_rl_stage1_restart_after_csrrx,
WILL_FIRE_RL_rl_stage1_trap,
WILL_FIRE_RL_rl_stage1_xRET,
WILL_FIRE_RL_rl_stage2_nonpipe,
WILL_FIRE_RL_rl_trap,
WILL_FIRE_RL_rl_trap_fetch,
WILL_FIRE_RL_stage1_rl_reset,
WILL_FIRE_RL_stage2_rl_reset_begin,
WILL_FIRE_RL_stage2_rl_reset_end,
WILL_FIRE_RL_stage3_rl_reset,
WILL_FIRE_RL_stageD_rl_reset,
WILL_FIRE_RL_stageF_rl_reset,
WILL_FIRE_dma_server_m_arvalid,
WILL_FIRE_dma_server_m_awvalid,
WILL_FIRE_dma_server_m_bready,
WILL_FIRE_dma_server_m_rready,
WILL_FIRE_dma_server_m_wvalid,
WILL_FIRE_hart0_server_reset_request_put,
WILL_FIRE_hart0_server_reset_response_get,
WILL_FIRE_imem_master_m_arready,
WILL_FIRE_imem_master_m_awready,
WILL_FIRE_imem_master_m_bvalid,
WILL_FIRE_imem_master_m_rvalid,
WILL_FIRE_imem_master_m_wready,
WILL_FIRE_m_external_interrupt_req,
WILL_FIRE_ma_ddr4_ready,
WILL_FIRE_mem_master_m_arready,
WILL_FIRE_mem_master_m_awready,
WILL_FIRE_mem_master_m_bvalid,
WILL_FIRE_mem_master_m_rvalid,
WILL_FIRE_mem_master_m_wready,
WILL_FIRE_nmi_req,
WILL_FIRE_s_external_interrupt_req,
WILL_FIRE_set_verbosity,
WILL_FIRE_set_watch_tohost,
WILL_FIRE_software_interrupt_req,
WILL_FIRE_timer_interrupt_req;
// inputs to muxes for submodule ports
reg [63 : 0] MUX_csr_regfile$mav_csr_write_2__VAL_2;
wire [131 : 0] MUX_rg_trap_info$write_1__VAL_1,
MUX_rg_trap_info$write_1__VAL_2,
MUX_rg_trap_info$write_1__VAL_3,
MUX_rg_trap_info$write_1__VAL_4;
wire [63 : 0] MUX_imem_rg_cache_addr$write_1__VAL_1,
MUX_imem_rg_cache_addr$write_1__VAL_2,
MUX_imem_rg_tval$write_1__VAL_1,
MUX_imem_rg_tval$write_1__VAL_2,
MUX_imem_rg_tval$write_1__VAL_3,
MUX_imem_rg_tval$write_1__VAL_4,
MUX_near_mem$imem_req_2__VAL_1,
MUX_near_mem$imem_req_2__VAL_2,
MUX_near_mem$imem_req_2__VAL_4;
wire [31 : 0] MUX_rg_trap_instr$write_1__VAL_1;
wire [3 : 0] MUX_rg_state$write_1__VAL_2,
MUX_rg_state$write_1__VAL_3,
MUX_rg_state$write_1__VAL_4;
wire MUX_csr_regfile$mav_csr_write_1__SEL_1,
MUX_gpr_regfile$write_rd_1__SEL_2,
MUX_imem_rg_cache_addr$write_1__SEL_1,
MUX_imem_rg_cache_addr$write_1__SEL_2,
MUX_rg_next_pc$write_1__SEL_1,
MUX_rg_next_pc$write_1__SEL_2,
MUX_rg_state$write_1__SEL_1,
MUX_rg_state$write_1__SEL_10,
MUX_rg_state$write_1__SEL_11,
MUX_rg_state$write_1__SEL_12,
MUX_rg_state$write_1__SEL_13,
MUX_rg_state$write_1__SEL_14,
MUX_rg_state$write_1__SEL_15,
MUX_rg_state$write_1__SEL_2,
MUX_rg_state$write_1__SEL_5,
MUX_rg_state$write_1__SEL_7,
MUX_rg_state$write_1__SEL_8,
MUX_rg_state$write_1__SEL_9,
MUX_rg_trap_info$write_1__SEL_1,
MUX_rg_trap_instr$write_1__SEL_1,
MUX_rg_trap_interrupt$write_1__SEL_1,
MUX_stage1_rg_full$write_1__VAL_2,
MUX_stage2_rg_full$write_1__VAL_2,
MUX_stage3_rg_full$write_1__VAL_2,
MUX_stageD_rg_full$write_1__VAL_2,
MUX_stageF_rg_full$write_1__VAL_2;
// declarations used by system tasks
// synopsys translate_off
reg [31 : 0] v__h2667;
reg [31 : 0] v__h2661;
// synopsys translate_on
// remaining internal signals
reg [63 : 0] CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q19,
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q20,
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d1520,
_theResult_____1_fst__h12542,
alu_outputs___1_val1__h10598,
rs1_val__h35329,
value__h8670,
value__h8884,
x_out_bypass_rd_val__h9272,
x_out_cf_info_taken_PC__h16275,
x_out_data_to_stage2_addr__h10120,
x_out_data_to_stage2_val1__h10121,
x_out_data_to_stage3_frd_val__h8345,
x_out_data_to_stage3_rd_val__h8341,
x_out_fbypass_rd_val__h9454;
reg [4 : 0] data_to_stage2_rd__h10102,
x_out_bypass_rd__h9271,
x_out_data_to_stage3_fpr_flags__h8344,
x_out_data_to_stage3_rd__h8340,
x_out_fbypass_rd__h9453;
reg [3 : 0] CASE_rg_cur_priv_0b0_8_0b1_9_11__q15,
CASE_stage1_rg_stage_input_BITS_87_TO_76_0b0_C_ETC__q16,
alu_outputs_exc_code__h11737,
x_out_trap_info_exc_code__h8780;
reg [2 : 0] CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q21,
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q22;
reg [1 : 0] CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q23;
reg CASE_stage1_rg_stage_input_BITS_112_TO_110_0b1_ETC__q11,
CASE_stage1_rg_stage_input_BITS_112_TO_110_0b1_ETC__q13,
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q12,
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q14,
CASE_stage2_rg_stage2_BITS_397_TO_395_1_NOT_ne_ETC__q3,
CASE_stage2_rg_stage2_BITS_397_TO_395_1_NOT_st_ETC__q5,
CASE_stage2_rg_stage2_BITS_397_TO_395_1_stage2_ETC__q4,
IF_stage1_rg_stage_input_32_BITS_112_TO_110_80_ETC___d432,
IF_stage1_rg_stage_input_32_BITS_112_TO_110_80_ETC___d769,
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d2768,
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d2772,
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d750,
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d758,
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d952,
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d960,
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152,
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d175,
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d184,
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d2299,
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d2686,
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d273,
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d279,
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d290,
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d297,
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d305,
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d310,
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d319,
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d324;
wire [429 : 0] IF_stage1_rg_stage_input_32_BITS_335_TO_334_33_ETC___d2511;
wire [127 : 0] csr_regfile_read_csr_mcycle__7_MINUS_rg_start__ETC___d2801;
wire [63 : 0] IF_csr_regfile_read_csr_rg_trap_instr_798_BITS_ETC___d2856,
IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d1260,
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d1521,
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d1522,
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d1531,
SEXT_stage1_rg_stage_input_32_BITS_87_TO_76_047___d1259,
_theResult_____1_fst__h12535,
_theResult_____1_fst__h12570,
_theResult____h33877,
_theResult___fst__h12706,
_theResult___fst__h12713,
_theResult___fst__h12794,
_theResult___snd_fst_rd_val__h9435,
_theResult___snd_snd__h16701,
_theResult___snd_snd_rd_val__h8290,
addr_of_b32___1__h27521,
addr_of_b32___1__h32461,
addr_of_b32___1__h44012,
addr_of_b32__h27393,
addr_of_b32__h32333,
addr_of_b32__h43884,
alu_outputs___1_addr__h10323,
alu_outputs___1_addr__h10697,
alu_outputs___1_fval1__h11709,
alu_outputs___1_fval2__h10701,
alu_outputs___1_fval3__h11711,
alu_outputs___1_val1__h10496,
alu_outputs___1_val1__h10541,
alu_outputs___1_val1__h10570,
alu_outputs___1_val1__h10983,
alu_outputs___1_val1__h11011,
alu_outputs_cf_info_taken_PC__h16267,
branch_target__h10301,
cpi__h33879,
cpifrac__h33880,
data_to_stage2_addr__h10103,
data_to_stage2_val2__h10105,
delta_CPI_cycles__h33875,
delta_CPI_instrs___1__h33921,
delta_CPI_instrs__h33876,
fall_through_pc__h9846,
next_pc___1__h13967,
next_pc__h10336,
next_pc__h10371,
next_pc__h13964,
next_pc__h9847,
output_stage2___1_data_to_stage3_frd_val__h8219,
rd_val___1__h12450,
rd_val___1__h12531,
rd_val___1__h12538,
rd_val___1__h12545,
rd_val___1__h12552,
rd_val___1__h12559,
rd_val___1__h16730,
rd_val___1__h16761,
rd_val___1__h16793,
rd_val___1__h16822,
rd_val___1__h16874,
rd_val___1__h16922,
rd_val___1__h16928,
rd_val___1__h16973,
rd_val__h10612,
rd_val__h10633,
rd_val__h16602,
rd_val__h16653,
rd_val__h16675,
rd_val__h9684,
rd_val__h9717,
rd_val__h9750,
rd_val__h9781,
rd_val__h9815,
rs1_val__h34495,
rs1_val_bypassed__h5597,
rs2_val_bypassed__h5603,
trap_info_tval__h15117,
val__h9686,
val__h9719,
value__h15187,
x__h33878,
x_out_cf_info_fallthru_PC__h16274,
x_out_data_to_stage2_fval1__h10123,
x_out_data_to_stage2_fval3__h10125,
x_out_data_to_stage2_val2__h10122,
x_out_next_pc__h9864,
y__h35607;
wire [31 : 0] IF_NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem__ETC___d2089,
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1930,
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1931,
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1932,
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1933,
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1934,
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1935,
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1936,
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1938,
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1940,
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1942,
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1944,
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1945,
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1946,
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1948,
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1949,
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1950,
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1952,
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1954,
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1955,
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1957,
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1958,
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1959,
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1960,
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1961,
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1962,
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1963,
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1964,
IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg_p_ETC___d2090,
IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC__q18,
_theResult____h5881,
d_instr__h25360,
instr___1__h17725,
instr__h17902,
instr__h18047,
instr__h18239,
instr__h18434,
instr__h18663,
instr__h19116,
instr__h19232,
instr__h19297,
instr__h19614,
instr__h19952,
instr__h20136,
instr__h20265,
instr__h20492,
instr__h20747,
instr__h20919,
instr__h21088,
instr__h21277,
instr__h21466,
instr__h21583,
instr__h21761,
instr__h21880,
instr__h21975,
instr__h22111,
instr__h22247,
instr__h22383,
instr__h22521,
instr__h22659,
instr__h22817,
instr__h22913,
instr__h23066,
instr__h23265,
instr__h23416,
instr__h23621,
instr__h24421,
instr__h24586,
instr__h24785,
instr__h24936,
instr_out___1__h25362,
instr_out___1__h25384,
rs1_val_bypassed597_BITS_31_TO_0_MINUS_rs2_val_ETC__q10,
rs1_val_bypassed597_BITS_31_TO_0_PLUS_rs2_val__ETC__q9,
rs1_val_bypassed597_BITS_31_TO_0_SRL_rs2_val_b_ETC__q8,
rs1_val_bypassed597_BITS_31_TO_0__q7,
tmp__h16821,
v32__h10610,
x__h16764,
x__h16796,
x__h16931,
x__h16976,
x_out_data_to_stage1_instr__h17651;
wire [20 : 0] SEXT_stageD_rg_data_667_BIT_76_684_CONCAT_stag_ETC___d1737,
decoded_instr_imm21_UJ__h30758,
stage1_rg_stage_input_BITS_30_TO_10__q1;
wire [19 : 0] imm20__h20004;
wire [12 : 0] SEXT_stageD_rg_data_667_BIT_76_684_CONCAT_stag_ETC___d1762,
decoded_instr_imm13_SB__h30756,
stage1_rg_stage_input_BITS_63_TO_51__q2;
wire [11 : 0] decoded_instr_imm12_S__h30755,
imm12__h17903,
imm12__h18240,
imm12__h19876,
imm12__h20545,
imm12__h20760,
imm12__h20956,
imm12__h21293,
imm12__h22914,
imm12__h23266,
offset__h18610,
stage1_rg_stage_input_BITS_75_TO_64__q6,
stage1_rg_stage_input_BITS_87_TO_76__q17;
wire [9 : 0] decoded_instr_funct10__h30753,
nzimm10__h20543,
nzimm10__h20758;
wire [8 : 0] offset__h19241, offset__h22828;
wire [7 : 0] offset__h17775, offset__h23200;
wire [6 : 0] offset__h18182;
wire [5 : 0] imm6__h19874, shamt__h10483;
wire [4 : 0] offset_BITS_4_TO_0___h18171,
offset_BITS_4_TO_0___h18602,
offset_BITS_4_TO_0___h23541,
rd__h18242,
rs1__h18241,
x_out_data_to_stage2_rd__h10119;
wire [3 : 0] alu_outputs___1_exc_code__h10979,
cur_verbosity__h3946,
x_exc_code__h44308,
x_out_trap_info_exc_code__h15122;
wire [2 : 0] rm__h10284;
wire [1 : 0] new_epoch__h26813, sxl__h6937, uxl__h6938;
wire IF_IF_stage1_rg_stage_input_32_BITS_151_TO_145_ETC___d1657,
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2310,
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2313,
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2325,
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2634,
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2675,
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2728,
IF_NOT_stage1_rg_full_31_76_OR_NOT_stage1_rg_s_ETC___d2347,
IF_NOT_stage1_rg_full_31_76_OR_NOT_stage1_rg_s_ETC___d2405,
IF_NOT_stage1_rg_full_31_76_OR_NOT_stage1_rg_s_ETC___d2589,
IF_NOT_stage2_rg_full_14_71_OR_stage2_rg_stage_ETC___d343,
IF_NOT_stage2_rg_full_14_71_OR_stage2_rg_stage_ETC___d344,
IF_NOT_stage2_rg_full_14_71_OR_stage2_rg_stage_ETC___d347,
IF_stage1_rg_full_31_THEN_stage1_rg_stage_inpu_ETC___d2897,
IF_stage1_rg_stage_input_32_BITS_112_TO_110_80_ETC___d2764,
IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d421,
IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d423,
IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d425,
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d763,
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d775,
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d965,
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d969,
IF_stage2_rg_full_14_THEN_IF_stage2_rg_stage2__ETC___d337,
IF_stage2_rg_full_14_THEN_IF_stage2_rg_stage2__ETC___d339,
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56,
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2298,
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2306,
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2315,
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2319,
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2342,
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2346,
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2401,
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2407,
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2541,
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2575,
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2591,
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2601,
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2605,
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2609,
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2613,
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2618,
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2622,
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2630,
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2750,
NOT_csr_regfile_read_mstatus__9_BITS_14_TO_13__ETC___d2461,
NOT_csr_regfile_read_mstatus__9_BITS_14_TO_13__ETC___d2505,
NOT_csr_regfile_read_mstatus__9_BITS_14_TO_13__ETC___d851,
NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d2072,
NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d2086,
NOT_near_mem_imem_exc__1_2_AND_imem_rg_pc_BITS_ETC___d2105,
NOT_near_mem_imem_exc__1_2_AND_imem_rg_pc_BITS_ETC___d2112,
NOT_rg_cur_priv_8_EQ_0b11_059_091_AND_NOT_rg_c_ETC___d1104,
NOT_rg_cur_priv_8_EQ_0b11_059_091_AND_NOT_rg_c_ETC___d1126,
NOT_rg_cur_priv_8_EQ_0b11_059_091_AND_NOT_rg_c_ETC___d1201,
NOT_rg_cur_priv_8_EQ_0b11_059_091_AND_NOT_rg_c_ETC___d1645,
NOT_rg_cur_priv_8_EQ_0b11_059_091_AND_NOT_rg_c_ETC___d2758,
NOT_rg_next_pc_867_BITS_1_TO_0_868_EQ_0b0_869__ETC___d2875,
NOT_rg_run_on_reset_247_248_OR_imem_rg_pc_BITS_ETC___d2255,
NOT_soc_map_m_pc_reset_value__268_BITS_1_TO_0__ETC___d2284,
NOT_stage1_rg_stage_input_32_BITS_104_TO_98_38_ETC___d746,
NOT_stage1_rg_stage_input_32_BITS_109_TO_105_2_ETC___d559,
NOT_stage1_rg_stage_input_32_BITS_112_TO_110_8_ETC___d1157,
NOT_stage1_rg_stage_input_32_BITS_112_TO_110_8_ETC___d1164,
NOT_stage1_rg_stage_input_32_BITS_112_TO_110_8_ETC___d479,
NOT_stage1_rg_stage_input_32_BITS_144_TO_140_0_ETC___d1169,
NOT_stage1_rg_stage_input_32_BITS_151_TO_145_7_ETC___d2774,
NOT_stage1_rg_stage_input_32_BITS_151_TO_145_7_ETC___d449,
NOT_stage1_rg_stage_input_32_BITS_151_TO_145_7_ETC___d760,
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1230,
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1238,
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1243,
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1249,
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1300,
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1660,
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1664,
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d2334,
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d2948,
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d2950,
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d974,
NOT_stage1_rg_stage_input_32_BITS_99_TO_98_74__ETC___d734,
NOT_stage1_rg_stage_input_32_BIT_332_77_83_AND_ETC___d1004,
NOT_stage1_rg_stage_input_32_BIT_332_77_83_AND_ETC___d1019,
NOT_stage1_rg_stage_input_32_BIT_332_77_83_AND_ETC___d1068,
NOT_stage1_rg_stage_input_32_BIT_332_77_83_AND_ETC___d1129,
NOT_stage1_rg_stage_input_32_BIT_332_77_83_AND_ETC___d2884,
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d1219,
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d1297,
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d1335,
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d2303,
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368,
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375,
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d778,
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d985,
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d148,
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d156,
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d177,
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d289,
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d402,
NOT_stageF_branch_predictor_predict_rsp_NOT_im_ETC___d2707,
_0_OR_stage1_rg_stage_input_32_BITS_104_TO_98_3_ETC___d2484,
csr_regfile_RDY_server_reset_request_put__219__ETC___d2231,
csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2685,
csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2693,
csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2735,
csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2739,
csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2953,
csr_regfile_read_misa__6_BIT_2_672_AND_stageD__ETC___d1747,
csr_regfile_read_misa__6_BIT_2_672_AND_stageD__ETC___d1753,
csr_regfile_read_mstatus__9_BITS_14_TO_13_1_EQ_ETC___d573,
imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d2109,
imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_near_mem__ETC___d2251,
imem_rg_pc_BITS_63_TO_2_4_EQ_imem_rg_cache_add_ETC___d2064,
imem_rg_pc_BITS_63_TO_2_4_EQ_near_mem_imem_pc__ETC___d17,
near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d2117,
near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d2119,
near_mem_imem_pc__5_EQ_imem_rg_pc_PLUS_2_066___d2067,
near_mem_imem_valid_AND_near_mem_imem_exc__1_A_ETC___d2214,
rg_cur_priv_8_EQ_0b11_059_OR_rg_cur_priv_8_EQ__ETC___d1124,
rg_cur_priv_8_EQ_0b11_059_OR_rg_cur_priv_8_EQ__ETC___d1189,
rg_cur_priv_8_EQ_0b11_059_OR_rg_cur_priv_8_EQ__ETC___d1203,
rg_cur_priv_8_EQ_0b11_059_OR_rg_cur_priv_8_EQ__ETC___d1635,
rg_state_7_EQ_12_4_AND_csr_regfile_wfi_resume__ETC___d2937,
rg_state_7_EQ_3_326_AND_NOT_csr_regfile_interr_ETC___d2753,
rg_state_7_EQ_3_326_AND_NOT_csr_regfile_interr_ETC___d2779,
rg_state_7_EQ_3_326_AND_NOT_csr_regfile_interr_ETC___d2814,
rg_state_7_EQ_3_326_AND_NOT_csr_regfile_interr_ETC___d2817,
rg_state_7_EQ_3_326_AND_NOT_csr_regfile_interr_ETC___d2908,
rg_state_7_EQ_3_326_AND_NOT_csr_regfile_interr_ETC___d2917,
rg_state_7_EQ_3_326_AND_NOT_csr_regfile_interr_ETC___d2926,
rg_state_7_EQ_3_326_AND_stage3_rg_full_8_OR_st_ETC___d2338,
rg_state_7_EQ_5_941_AND_NOT_stageF_rg_full_094_ETC___d2942,
rg_state_7_EQ_8_864_AND_NOT_stageF_rg_full_094_ETC___d2865,
rg_trap_info_787_BITS_131_TO_68_788_EQ_csr_reg_ETC___d2797,
stage1_rg_full_31_AND_NOT_stage2_rg_full_14_71_ETC___d1317,
stage1_rg_full_31_AND_NOT_stage2_rg_full_14_71_ETC___d1375,
stage1_rg_full_31_AND_NOT_stage2_rg_full_14_71_ETC___d1401,
stage1_rg_full_31_AND_NOT_stage2_rg_full_14_71_ETC___d990,
stage1_rg_full_31_AND_NOT_stage2_rg_full_14_71_ETC___d998,
stage1_rg_full_31_AND_stage1_rg_stage_input_32_ETC___d363,
stage1_rg_stage_input_32_BITS_104_TO_98_38_EQ__ETC___d2427,
stage1_rg_stage_input_32_BITS_104_TO_98_38_EQ__ETC___d869,
stage1_rg_stage_input_32_BITS_104_TO_98_38_EQ__ETC___d878,
stage1_rg_stage_input_32_BITS_104_TO_98_38_EQ__ETC___d886,
stage1_rg_stage_input_32_BITS_104_TO_98_38_EQ__ETC___d893,
stage1_rg_stage_input_32_BITS_104_TO_98_38_EQ__ETC___d918,
stage1_rg_stage_input_32_BITS_104_TO_98_38_EQ__ETC___d929,
stage1_rg_stage_input_32_BITS_104_TO_98_38_EQ__ETC___d935,
stage1_rg_stage_input_32_BITS_112_TO_110_80_EQ_ETC___d1035,
stage1_rg_stage_input_32_BITS_112_TO_110_80_EQ_ETC___d1049,
stage1_rg_stage_input_32_BITS_112_TO_110_80_EQ_ETC___d806,
stage1_rg_stage_input_32_BITS_144_TO_140_027_E_ETC___d1065,
stage1_rg_stage_input_32_BITS_144_TO_140_027_E_ETC___d1103,
stage1_rg_stage_input_32_BITS_151_TO_145_78_EQ_ETC___d1341,
stage1_rg_stage_input_32_BITS_151_TO_145_78_EQ_ETC___d2892,
stage1_rg_stage_input_32_BITS_151_TO_145_78_EQ_ETC___d794,
stage1_rg_stage_input_32_BITS_151_TO_145_78_EQ_ETC___d962,
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d1398,
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d1588,
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d2343,
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d2626,
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334,
stage1_rg_stage_input_32_BITS_99_TO_98_74_EQ_0_ETC___d2440,
stage1_rg_stage_input_32_BITS_99_TO_98_74_EQ_0_ETC___d938,
stage1_rg_stage_input_32_BIT_332_77_OR_NOT_rg__ETC___d1096,
stage2_rg_full_14_AND_IF_stage2_rg_stage2_15_B_ETC___d2379,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1006,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1007,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1009,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1021,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1022,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1024,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1039,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1040,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1042,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1053,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1054,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1056,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1070,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1071,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1073,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1085,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1086,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1088,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1109,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1110,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1111,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1113,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1131,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1132,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1133,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1135,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1208,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1209,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1210,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1213,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1214,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1215,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1216,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1278,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1332,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1350,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1360,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1365,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1368,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1379,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1395,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1555,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d2295,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d2614,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d972,
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d995,
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d170,
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d2376,
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d2381,
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d2383,
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d2385,
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d2387,
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d2389,
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d2395,
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d405,
stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_0_17_ETC___d168,
stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_0_17_ETC___d215,
stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_0_17_ETC___d244,
stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_2_21_ETC___d296,
stage3_rg_full_8_OR_NOT_stage2_rg_full_14_71_O_ETC___d2337,
stage3_rg_stage3_00_BITS_139_TO_135_09_EQ_stag_ETC___d407,
stage3_rg_stage3_00_BITS_139_TO_135_09_EQ_stag_ETC___d415,
stageF_f_reset_rsps_i_notEmpty__241_AND_stageD_ETC___d2261,
stageF_rg_full_094_AND_near_mem_imem_valid_AND_ETC___d2126;
// action method hart0_server_reset_request_put
assign RDY_hart0_server_reset_request_put = f_reset_reqs$FULL_N ;
assign CAN_FIRE_hart0_server_reset_request_put = f_reset_reqs$FULL_N ;
assign WILL_FIRE_hart0_server_reset_request_put =
EN_hart0_server_reset_request_put ;
// actionvalue method hart0_server_reset_response_get
assign hart0_server_reset_response_get = f_reset_rsps$D_OUT ;
assign RDY_hart0_server_reset_response_get = f_reset_rsps$EMPTY_N ;
assign CAN_FIRE_hart0_server_reset_response_get = f_reset_rsps$EMPTY_N ;
assign WILL_FIRE_hart0_server_reset_response_get =
EN_hart0_server_reset_response_get ;
// value method imem_master_m_awvalid
assign imem_master_awvalid = near_mem$imem_master_awvalid ;
// value method imem_master_m_awid
assign imem_master_awid = near_mem$imem_master_awid ;
// value method imem_master_m_awaddr
assign imem_master_awaddr = near_mem$imem_master_awaddr ;
// value method imem_master_m_awlen
assign imem_master_awlen = near_mem$imem_master_awlen ;
// value method imem_master_m_awsize
assign imem_master_awsize = near_mem$imem_master_awsize ;
// value method imem_master_m_awburst
assign imem_master_awburst = near_mem$imem_master_awburst ;
// value method imem_master_m_awlock
assign imem_master_awlock = near_mem$imem_master_awlock ;
// value method imem_master_m_awcache
assign imem_master_awcache = near_mem$imem_master_awcache ;
// value method imem_master_m_awprot
assign imem_master_awprot = near_mem$imem_master_awprot ;
// value method imem_master_m_awqos
assign imem_master_awqos = near_mem$imem_master_awqos ;
// value method imem_master_m_awregion
assign imem_master_awregion = near_mem$imem_master_awregion ;
// action method imem_master_m_awready
assign CAN_FIRE_imem_master_m_awready = 1'd1 ;
assign WILL_FIRE_imem_master_m_awready = 1'd1 ;
// value method imem_master_m_wvalid
assign imem_master_wvalid = near_mem$imem_master_wvalid ;
// value method imem_master_m_wdata
assign imem_master_wdata = near_mem$imem_master_wdata ;
// value method imem_master_m_wstrb
assign imem_master_wstrb = near_mem$imem_master_wstrb ;
// value method imem_master_m_wlast
assign imem_master_wlast = near_mem$imem_master_wlast ;
// action method imem_master_m_wready
assign CAN_FIRE_imem_master_m_wready = 1'd1 ;
assign WILL_FIRE_imem_master_m_wready = 1'd1 ;
// action method imem_master_m_bvalid
assign CAN_FIRE_imem_master_m_bvalid = 1'd1 ;
assign WILL_FIRE_imem_master_m_bvalid = 1'd1 ;
// value method imem_master_m_bready
assign imem_master_bready = near_mem$imem_master_bready ;
// value method imem_master_m_arvalid
assign imem_master_arvalid = near_mem$imem_master_arvalid ;
// value method imem_master_m_arid
assign imem_master_arid = near_mem$imem_master_arid ;
// value method imem_master_m_araddr
assign imem_master_araddr = near_mem$imem_master_araddr ;
// value method imem_master_m_arlen
assign imem_master_arlen = near_mem$imem_master_arlen ;
// value method imem_master_m_arsize
assign imem_master_arsize = near_mem$imem_master_arsize ;
// value method imem_master_m_arburst
assign imem_master_arburst = near_mem$imem_master_arburst ;
// value method imem_master_m_arlock
assign imem_master_arlock = near_mem$imem_master_arlock ;
// value method imem_master_m_arcache
assign imem_master_arcache = near_mem$imem_master_arcache ;
// value method imem_master_m_arprot
assign imem_master_arprot = near_mem$imem_master_arprot ;
// value method imem_master_m_arqos
assign imem_master_arqos = near_mem$imem_master_arqos ;
// value method imem_master_m_arregion
assign imem_master_arregion = near_mem$imem_master_arregion ;
// action method imem_master_m_arready
assign CAN_FIRE_imem_master_m_arready = 1'd1 ;
assign WILL_FIRE_imem_master_m_arready = 1'd1 ;
// action method imem_master_m_rvalid
assign CAN_FIRE_imem_master_m_rvalid = 1'd1 ;
assign WILL_FIRE_imem_master_m_rvalid = 1'd1 ;
// value method imem_master_m_rready
assign imem_master_rready = near_mem$imem_master_rready ;
// value method mem_master_m_awvalid
assign mem_master_awvalid = near_mem$mem_master_awvalid ;
// value method mem_master_m_awid
assign mem_master_awid = near_mem$mem_master_awid ;
// value method mem_master_m_awaddr
assign mem_master_awaddr = near_mem$mem_master_awaddr ;
// value method mem_master_m_awlen
assign mem_master_awlen = near_mem$mem_master_awlen ;
// value method mem_master_m_awsize
assign mem_master_awsize = near_mem$mem_master_awsize ;
// value method mem_master_m_awburst
assign mem_master_awburst = near_mem$mem_master_awburst ;
// value method mem_master_m_awlock
assign mem_master_awlock = near_mem$mem_master_awlock ;
// value method mem_master_m_awcache
assign mem_master_awcache = near_mem$mem_master_awcache ;
// value method mem_master_m_awprot
assign mem_master_awprot = near_mem$mem_master_awprot ;
// value method mem_master_m_awqos
assign mem_master_awqos = near_mem$mem_master_awqos ;
// value method mem_master_m_awregion
assign mem_master_awregion = near_mem$mem_master_awregion ;
// action method mem_master_m_awready
assign CAN_FIRE_mem_master_m_awready = 1'd1 ;
assign WILL_FIRE_mem_master_m_awready = 1'd1 ;
// value method mem_master_m_wvalid
assign mem_master_wvalid = near_mem$mem_master_wvalid ;
// value method mem_master_m_wdata
assign mem_master_wdata = near_mem$mem_master_wdata ;
// value method mem_master_m_wstrb
assign mem_master_wstrb = near_mem$mem_master_wstrb ;
// value method mem_master_m_wlast
assign mem_master_wlast = near_mem$mem_master_wlast ;
// action method mem_master_m_wready
assign CAN_FIRE_mem_master_m_wready = 1'd1 ;
assign WILL_FIRE_mem_master_m_wready = 1'd1 ;
// action method mem_master_m_bvalid
assign CAN_FIRE_mem_master_m_bvalid = 1'd1 ;
assign WILL_FIRE_mem_master_m_bvalid = 1'd1 ;
// value method mem_master_m_bready
assign mem_master_bready = near_mem$mem_master_bready ;
// value method mem_master_m_arvalid
assign mem_master_arvalid = near_mem$mem_master_arvalid ;
// value method mem_master_m_arid
assign mem_master_arid = near_mem$mem_master_arid ;
// value method mem_master_m_araddr
assign mem_master_araddr = near_mem$mem_master_araddr ;
// value method mem_master_m_arlen
assign mem_master_arlen = near_mem$mem_master_arlen ;
// value method mem_master_m_arsize
assign mem_master_arsize = near_mem$mem_master_arsize ;
// value method mem_master_m_arburst
assign mem_master_arburst = near_mem$mem_master_arburst ;
// value method mem_master_m_arlock
assign mem_master_arlock = near_mem$mem_master_arlock ;
// value method mem_master_m_arcache
assign mem_master_arcache = near_mem$mem_master_arcache ;
// value method mem_master_m_arprot
assign mem_master_arprot = near_mem$mem_master_arprot ;
// value method mem_master_m_arqos
assign mem_master_arqos = near_mem$mem_master_arqos ;
// value method mem_master_m_arregion
assign mem_master_arregion = near_mem$mem_master_arregion ;
// action method mem_master_m_arready
assign CAN_FIRE_mem_master_m_arready = 1'd1 ;
assign WILL_FIRE_mem_master_m_arready = 1'd1 ;
// action method mem_master_m_rvalid
assign CAN_FIRE_mem_master_m_rvalid = 1'd1 ;
assign WILL_FIRE_mem_master_m_rvalid = 1'd1 ;
// value method mem_master_m_rready
assign mem_master_rready = near_mem$mem_master_rready ;
// action method dma_server_m_awvalid
assign CAN_FIRE_dma_server_m_awvalid = 1'd1 ;
assign WILL_FIRE_dma_server_m_awvalid = 1'd1 ;
// value method dma_server_m_awready
assign dma_server_awready = near_mem$dma_server_awready ;
// action method dma_server_m_wvalid
assign CAN_FIRE_dma_server_m_wvalid = 1'd1 ;
assign WILL_FIRE_dma_server_m_wvalid = 1'd1 ;
// value method dma_server_m_wready
assign dma_server_wready = near_mem$dma_server_wready ;
// value method dma_server_m_bvalid
assign dma_server_bvalid = near_mem$dma_server_bvalid ;
// value method dma_server_m_bid
assign dma_server_bid = near_mem$dma_server_bid ;
// value method dma_server_m_bresp
assign dma_server_bresp = near_mem$dma_server_bresp ;
// action method dma_server_m_bready
assign CAN_FIRE_dma_server_m_bready = 1'd1 ;
assign WILL_FIRE_dma_server_m_bready = 1'd1 ;
// action method dma_server_m_arvalid
assign CAN_FIRE_dma_server_m_arvalid = 1'd1 ;
assign WILL_FIRE_dma_server_m_arvalid = 1'd1 ;
// value method dma_server_m_arready
assign dma_server_arready = near_mem$dma_server_arready ;
// value method dma_server_m_rvalid
assign dma_server_rvalid = near_mem$dma_server_rvalid ;
// value method dma_server_m_rid
assign dma_server_rid = near_mem$dma_server_rid ;
// value method dma_server_m_rdata
assign dma_server_rdata = near_mem$dma_server_rdata ;
// value method dma_server_m_rresp
assign dma_server_rresp = near_mem$dma_server_rresp ;
// value method dma_server_m_rlast
assign dma_server_rlast = near_mem$dma_server_rlast ;
// action method dma_server_m_rready
assign CAN_FIRE_dma_server_m_rready = 1'd1 ;
assign WILL_FIRE_dma_server_m_rready = 1'd1 ;
// action method m_external_interrupt_req
assign CAN_FIRE_m_external_interrupt_req = 1'd1 ;
assign WILL_FIRE_m_external_interrupt_req = 1'd1 ;
// action method s_external_interrupt_req
assign CAN_FIRE_s_external_interrupt_req = 1'd1 ;
assign WILL_FIRE_s_external_interrupt_req = 1'd1 ;
// action method software_interrupt_req
assign CAN_FIRE_software_interrupt_req = 1'd1 ;
assign WILL_FIRE_software_interrupt_req = 1'd1 ;
// action method timer_interrupt_req
assign CAN_FIRE_timer_interrupt_req = 1'd1 ;
assign WILL_FIRE_timer_interrupt_req = 1'd1 ;
// action method nmi_req
assign CAN_FIRE_nmi_req = 1'd1 ;
assign WILL_FIRE_nmi_req = 1'd1 ;
// action method set_verbosity
assign RDY_set_verbosity = 1'd1 ;
assign CAN_FIRE_set_verbosity = 1'd1 ;
assign WILL_FIRE_set_verbosity = EN_set_verbosity ;
// action method set_watch_tohost
assign RDY_set_watch_tohost = 1'd1 ;
assign CAN_FIRE_set_watch_tohost = 1'd1 ;
assign WILL_FIRE_set_watch_tohost = EN_set_watch_tohost ;
// value method mv_tohost_value
assign mv_tohost_value = near_mem$mv_tohost_value ;
assign RDY_mv_tohost_value = 1'd1 ;
// action method ma_ddr4_ready
assign RDY_ma_ddr4_ready = 1'd1 ;
assign CAN_FIRE_ma_ddr4_ready = 1'd1 ;
assign WILL_FIRE_ma_ddr4_ready = EN_ma_ddr4_ready ;
// value method mv_status
assign mv_status = near_mem$mv_status ;
// submodule csr_regfile
mkCSR_RegFile csr_regfile(.CLK(CLK),
.RST_N(RST_N),
.access_permitted_1_csr_addr(csr_regfile$access_permitted_1_csr_addr),
.access_permitted_1_priv(csr_regfile$access_permitted_1_priv),
.access_permitted_1_read_not_write(csr_regfile$access_permitted_1_read_not_write),
.access_permitted_2_csr_addr(csr_regfile$access_permitted_2_csr_addr),
.access_permitted_2_priv(csr_regfile$access_permitted_2_priv),
.access_permitted_2_read_not_write(csr_regfile$access_permitted_2_read_not_write),
.csr_counter_read_fault_csr_addr(csr_regfile$csr_counter_read_fault_csr_addr),
.csr_counter_read_fault_priv(csr_regfile$csr_counter_read_fault_priv),
.csr_ret_actions_from_priv(csr_regfile$csr_ret_actions_from_priv),
.csr_trap_actions_exc_code(csr_regfile$csr_trap_actions_exc_code),
.csr_trap_actions_from_priv(csr_regfile$csr_trap_actions_from_priv),
.csr_trap_actions_interrupt(csr_regfile$csr_trap_actions_interrupt),
.csr_trap_actions_nmi(csr_regfile$csr_trap_actions_nmi),
.csr_trap_actions_pc(csr_regfile$csr_trap_actions_pc),
.csr_trap_actions_xtval(csr_regfile$csr_trap_actions_xtval),
.interrupt_pending_cur_priv(csr_regfile$interrupt_pending_cur_priv),
.m_external_interrupt_req_set_not_clear(csr_regfile$m_external_interrupt_req_set_not_clear),
.ma_update_fcsr_fflags_flags(csr_regfile$ma_update_fcsr_fflags_flags),
.ma_update_mstatus_fs_fs(csr_regfile$ma_update_mstatus_fs_fs),
.mav_csr_write_csr_addr(csr_regfile$mav_csr_write_csr_addr),
.mav_csr_write_word(csr_regfile$mav_csr_write_word),
.mav_read_csr_csr_addr(csr_regfile$mav_read_csr_csr_addr),
.mv_update_fcsr_fflags_flags(csr_regfile$mv_update_fcsr_fflags_flags),
.mv_update_mstatus_fs_fs(csr_regfile$mv_update_mstatus_fs_fs),
.nmi_req_set_not_clear(csr_regfile$nmi_req_set_not_clear),
.read_csr_csr_addr(csr_regfile$read_csr_csr_addr),
.read_csr_port2_csr_addr(csr_regfile$read_csr_port2_csr_addr),
.s_external_interrupt_req_set_not_clear(csr_regfile$s_external_interrupt_req_set_not_clear),
.software_interrupt_req_set_not_clear(csr_regfile$software_interrupt_req_set_not_clear),
.timer_interrupt_req_set_not_clear(csr_regfile$timer_interrupt_req_set_not_clear),
.EN_server_reset_request_put(csr_regfile$EN_server_reset_request_put),
.EN_server_reset_response_get(csr_regfile$EN_server_reset_response_get),
.EN_mav_read_csr(csr_regfile$EN_mav_read_csr),
.EN_mav_csr_write(csr_regfile$EN_mav_csr_write),
.EN_ma_update_fcsr_fflags(csr_regfile$EN_ma_update_fcsr_fflags),
.EN_ma_update_mstatus_fs(csr_regfile$EN_ma_update_mstatus_fs),
.EN_csr_trap_actions(csr_regfile$EN_csr_trap_actions),
.EN_csr_ret_actions(csr_regfile$EN_csr_ret_actions),
.EN_csr_minstret_incr(csr_regfile$EN_csr_minstret_incr),
.EN_debug(csr_regfile$EN_debug),
.RDY_server_reset_request_put(csr_regfile$RDY_server_reset_request_put),
.RDY_server_reset_response_get(csr_regfile$RDY_server_reset_response_get),
.read_csr(csr_regfile$read_csr),
.read_csr_port2(),
.mav_read_csr(),
.mav_csr_write(),
.read_frm(csr_regfile$read_frm),
.read_fflags(),
.mv_update_fcsr_fflags(),
.mv_update_mstatus_fs(),
.read_misa(csr_regfile$read_misa),
.read_mstatus(csr_regfile$read_mstatus),
.read_sstatus(csr_regfile$read_sstatus),
.read_ustatus(),
.read_satp(csr_regfile$read_satp),
.csr_trap_actions(csr_regfile$csr_trap_actions),
.RDY_csr_trap_actions(),
.csr_ret_actions(csr_regfile$csr_ret_actions),
.RDY_csr_ret_actions(),
.read_csr_minstret(csr_regfile$read_csr_minstret),
.read_csr_mcycle(csr_regfile$read_csr_mcycle),
.read_csr_mtime(),
.access_permitted_1(csr_regfile$access_permitted_1),
.access_permitted_2(csr_regfile$access_permitted_2),
.csr_counter_read_fault(),
.csr_mip_read(),
.interrupt_pending(csr_regfile$interrupt_pending),
.wfi_resume(csr_regfile$wfi_resume),
.nmi_pending(csr_regfile$nmi_pending),
.RDY_debug());
// submodule f_reset_reqs
FIFO2 #(.width(32'd1), .guarded(1'd1)) f_reset_reqs(.RST(RST_N),
.CLK(CLK),
.D_IN(f_reset_reqs$D_IN),
.ENQ(f_reset_reqs$ENQ),
.DEQ(f_reset_reqs$DEQ),
.CLR(f_reset_reqs$CLR),
.D_OUT(f_reset_reqs$D_OUT),
.FULL_N(f_reset_reqs$FULL_N),
.EMPTY_N(f_reset_reqs$EMPTY_N));
// submodule f_reset_rsps
FIFO2 #(.width(32'd1), .guarded(1'd1)) f_reset_rsps(.RST(RST_N),
.CLK(CLK),
.D_IN(f_reset_rsps$D_IN),
.ENQ(f_reset_rsps$ENQ),
.DEQ(f_reset_rsps$DEQ),
.CLR(f_reset_rsps$CLR),
.D_OUT(f_reset_rsps$D_OUT),
.FULL_N(f_reset_rsps$FULL_N),
.EMPTY_N(f_reset_rsps$EMPTY_N));
// submodule fpr_regfile
mkFPR_RegFile fpr_regfile(.CLK(CLK),
.RST_N(RST_N),
.read_rs1_port2_rs1(fpr_regfile$read_rs1_port2_rs1),
.read_rs1_rs1(fpr_regfile$read_rs1_rs1),
.read_rs2_rs2(fpr_regfile$read_rs2_rs2),
.read_rs3_rs3(fpr_regfile$read_rs3_rs3),
.write_rd_rd(fpr_regfile$write_rd_rd),
.write_rd_rd_val(fpr_regfile$write_rd_rd_val),
.EN_server_reset_request_put(fpr_regfile$EN_server_reset_request_put),
.EN_server_reset_response_get(fpr_regfile$EN_server_reset_response_get),
.EN_write_rd(fpr_regfile$EN_write_rd),
.RDY_server_reset_request_put(fpr_regfile$RDY_server_reset_request_put),
.RDY_server_reset_response_get(fpr_regfile$RDY_server_reset_response_get),
.read_rs1(fpr_regfile$read_rs1),
.read_rs1_port2(),
.read_rs2(fpr_regfile$read_rs2),
.read_rs3(fpr_regfile$read_rs3));
// submodule gpr_regfile
mkGPR_RegFile gpr_regfile(.CLK(CLK),
.RST_N(RST_N),
.read_rs1_port2_rs1(gpr_regfile$read_rs1_port2_rs1),
.read_rs1_rs1(gpr_regfile$read_rs1_rs1),
.read_rs2_rs2(gpr_regfile$read_rs2_rs2),
.write_rd_rd(gpr_regfile$write_rd_rd),
.write_rd_rd_val(gpr_regfile$write_rd_rd_val),
.EN_server_reset_request_put(gpr_regfile$EN_server_reset_request_put),
.EN_server_reset_response_get(gpr_regfile$EN_server_reset_response_get),
.EN_write_rd(gpr_regfile$EN_write_rd),
.RDY_server_reset_request_put(gpr_regfile$RDY_server_reset_request_put),
.RDY_server_reset_response_get(gpr_regfile$RDY_server_reset_response_get),
.read_rs1(gpr_regfile$read_rs1),
.read_rs1_port2(),
.read_rs2(gpr_regfile$read_rs2));
// submodule near_mem
mkNear_Mem near_mem(.CLK(CLK),
.RST_N(RST_N),
.dma_server_araddr(near_mem$dma_server_araddr),
.dma_server_arburst(near_mem$dma_server_arburst),
.dma_server_arcache(near_mem$dma_server_arcache),
.dma_server_arid(near_mem$dma_server_arid),
.dma_server_arlen(near_mem$dma_server_arlen),
.dma_server_arlock(near_mem$dma_server_arlock),
.dma_server_arprot(near_mem$dma_server_arprot),
.dma_server_arqos(near_mem$dma_server_arqos),
.dma_server_arregion(near_mem$dma_server_arregion),
.dma_server_arsize(near_mem$dma_server_arsize),
.dma_server_arvalid(near_mem$dma_server_arvalid),
.dma_server_awaddr(near_mem$dma_server_awaddr),
.dma_server_awburst(near_mem$dma_server_awburst),
.dma_server_awcache(near_mem$dma_server_awcache),
.dma_server_awid(near_mem$dma_server_awid),
.dma_server_awlen(near_mem$dma_server_awlen),
.dma_server_awlock(near_mem$dma_server_awlock),
.dma_server_awprot(near_mem$dma_server_awprot),
.dma_server_awqos(near_mem$dma_server_awqos),
.dma_server_awregion(near_mem$dma_server_awregion),
.dma_server_awsize(near_mem$dma_server_awsize),
.dma_server_awvalid(near_mem$dma_server_awvalid),
.dma_server_bready(near_mem$dma_server_bready),
.dma_server_rready(near_mem$dma_server_rready),
.dma_server_wdata(near_mem$dma_server_wdata),
.dma_server_wlast(near_mem$dma_server_wlast),
.dma_server_wstrb(near_mem$dma_server_wstrb),
.dma_server_wvalid(near_mem$dma_server_wvalid),
.dmem_req_addr(near_mem$dmem_req_addr),
.dmem_req_amo_funct7(near_mem$dmem_req_amo_funct7),
.dmem_req_f3(near_mem$dmem_req_f3),
.dmem_req_mstatus_MXR(near_mem$dmem_req_mstatus_MXR),
.dmem_req_op(near_mem$dmem_req_op),
.dmem_req_priv(near_mem$dmem_req_priv),
.dmem_req_satp(near_mem$dmem_req_satp),
.dmem_req_sstatus_SUM(near_mem$dmem_req_sstatus_SUM),
.dmem_req_store_value(near_mem$dmem_req_store_value),
.imem_master_arready(near_mem$imem_master_arready),
.imem_master_awready(near_mem$imem_master_awready),
.imem_master_bid(near_mem$imem_master_bid),
.imem_master_bresp(near_mem$imem_master_bresp),
.imem_master_bvalid(near_mem$imem_master_bvalid),
.imem_master_rdata(near_mem$imem_master_rdata),
.imem_master_rid(near_mem$imem_master_rid),
.imem_master_rlast(near_mem$imem_master_rlast),
.imem_master_rresp(near_mem$imem_master_rresp),
.imem_master_rvalid(near_mem$imem_master_rvalid),
.imem_master_wready(near_mem$imem_master_wready),
.imem_req_addr(near_mem$imem_req_addr),
.imem_req_f3(near_mem$imem_req_f3),
.imem_req_mstatus_MXR(near_mem$imem_req_mstatus_MXR),
.imem_req_priv(near_mem$imem_req_priv),
.imem_req_satp(near_mem$imem_req_satp),
.imem_req_sstatus_SUM(near_mem$imem_req_sstatus_SUM),
.mem_master_arready(near_mem$mem_master_arready),
.mem_master_awready(near_mem$mem_master_awready),
.mem_master_bid(near_mem$mem_master_bid),
.mem_master_bresp(near_mem$mem_master_bresp),
.mem_master_bvalid(near_mem$mem_master_bvalid),
.mem_master_rdata(near_mem$mem_master_rdata),
.mem_master_rid(near_mem$mem_master_rid),
.mem_master_rlast(near_mem$mem_master_rlast),
.mem_master_rresp(near_mem$mem_master_rresp),
.mem_master_rvalid(near_mem$mem_master_rvalid),
.mem_master_wready(near_mem$mem_master_wready),
.server_fence_request_put(near_mem$server_fence_request_put),
.set_watch_tohost_tohost_addr(near_mem$set_watch_tohost_tohost_addr),
.set_watch_tohost_watch_tohost(near_mem$set_watch_tohost_watch_tohost),
.EN_server_reset_request_put(near_mem$EN_server_reset_request_put),
.EN_server_reset_response_get(near_mem$EN_server_reset_response_get),
.EN_imem_req(near_mem$EN_imem_req),
.EN_dmem_req(near_mem$EN_dmem_req),
.EN_server_fence_i_request_put(near_mem$EN_server_fence_i_request_put),
.EN_server_fence_i_response_get(near_mem$EN_server_fence_i_response_get),
.EN_server_fence_request_put(near_mem$EN_server_fence_request_put),
.EN_server_fence_response_get(near_mem$EN_server_fence_response_get),
.EN_sfence_vma_server_request_put(near_mem$EN_sfence_vma_server_request_put),
.EN_sfence_vma_server_response_get(near_mem$EN_sfence_vma_server_response_get),
.EN_set_watch_tohost(near_mem$EN_set_watch_tohost),
.EN_ma_ddr4_ready(near_mem$EN_ma_ddr4_ready),
.RDY_server_reset_request_put(near_mem$RDY_server_reset_request_put),
.RDY_server_reset_response_get(near_mem$RDY_server_reset_response_get),
.imem_valid(near_mem$imem_valid),
.imem_is_i32_not_i16(near_mem$imem_is_i32_not_i16),
.imem_pc(near_mem$imem_pc),
.imem_instr(near_mem$imem_instr),
.imem_exc(near_mem$imem_exc),
.imem_exc_code(near_mem$imem_exc_code),
.imem_tval(),
.imem_master_awvalid(near_mem$imem_master_awvalid),
.imem_master_awid(near_mem$imem_master_awid),
.imem_master_awaddr(near_mem$imem_master_awaddr),
.imem_master_awlen(near_mem$imem_master_awlen),
.imem_master_awsize(near_mem$imem_master_awsize),
.imem_master_awburst(near_mem$imem_master_awburst),
.imem_master_awlock(near_mem$imem_master_awlock),
.imem_master_awcache(near_mem$imem_master_awcache),
.imem_master_awprot(near_mem$imem_master_awprot),
.imem_master_awqos(near_mem$imem_master_awqos),
.imem_master_awregion(near_mem$imem_master_awregion),
.imem_master_wvalid(near_mem$imem_master_wvalid),
.imem_master_wdata(near_mem$imem_master_wdata),
.imem_master_wstrb(near_mem$imem_master_wstrb),
.imem_master_wlast(near_mem$imem_master_wlast),
.imem_master_bready(near_mem$imem_master_bready),
.imem_master_arvalid(near_mem$imem_master_arvalid),
.imem_master_arid(near_mem$imem_master_arid),
.imem_master_araddr(near_mem$imem_master_araddr),
.imem_master_arlen(near_mem$imem_master_arlen),
.imem_master_arsize(near_mem$imem_master_arsize),
.imem_master_arburst(near_mem$imem_master_arburst),
.imem_master_arlock(near_mem$imem_master_arlock),
.imem_master_arcache(near_mem$imem_master_arcache),
.imem_master_arprot(near_mem$imem_master_arprot),
.imem_master_arqos(near_mem$imem_master_arqos),
.imem_master_arregion(near_mem$imem_master_arregion),
.imem_master_rready(near_mem$imem_master_rready),
.dmem_valid(near_mem$dmem_valid),
.dmem_word64(near_mem$dmem_word64),
.dmem_st_amo_val(),
.dmem_exc(near_mem$dmem_exc),
.dmem_exc_code(near_mem$dmem_exc_code),
.mem_master_awvalid(near_mem$mem_master_awvalid),
.mem_master_awid(near_mem$mem_master_awid),
.mem_master_awaddr(near_mem$mem_master_awaddr),
.mem_master_awlen(near_mem$mem_master_awlen),
.mem_master_awsize(near_mem$mem_master_awsize),
.mem_master_awburst(near_mem$mem_master_awburst),
.mem_master_awlock(near_mem$mem_master_awlock),
.mem_master_awcache(near_mem$mem_master_awcache),
.mem_master_awprot(near_mem$mem_master_awprot),
.mem_master_awqos(near_mem$mem_master_awqos),
.mem_master_awregion(near_mem$mem_master_awregion),
.mem_master_wvalid(near_mem$mem_master_wvalid),
.mem_master_wdata(near_mem$mem_master_wdata),
.mem_master_wstrb(near_mem$mem_master_wstrb),
.mem_master_wlast(near_mem$mem_master_wlast),
.mem_master_bready(near_mem$mem_master_bready),
.mem_master_arvalid(near_mem$mem_master_arvalid),
.mem_master_arid(near_mem$mem_master_arid),
.mem_master_araddr(near_mem$mem_master_araddr),
.mem_master_arlen(near_mem$mem_master_arlen),
.mem_master_arsize(near_mem$mem_master_arsize),
.mem_master_arburst(near_mem$mem_master_arburst),
.mem_master_arlock(near_mem$mem_master_arlock),
.mem_master_arcache(near_mem$mem_master_arcache),
.mem_master_arprot(near_mem$mem_master_arprot),
.mem_master_arqos(near_mem$mem_master_arqos),
.mem_master_arregion(near_mem$mem_master_arregion),
.mem_master_rready(near_mem$mem_master_rready),
.RDY_server_fence_i_request_put(near_mem$RDY_server_fence_i_request_put),
.RDY_server_fence_i_response_get(near_mem$RDY_server_fence_i_response_get),
.RDY_server_fence_request_put(near_mem$RDY_server_fence_request_put),
.RDY_server_fence_response_get(near_mem$RDY_server_fence_response_get),
.RDY_sfence_vma_server_request_put(near_mem$RDY_sfence_vma_server_request_put),
.RDY_sfence_vma_server_response_get(near_mem$RDY_sfence_vma_server_response_get),
.dma_server_awready(near_mem$dma_server_awready),
.dma_server_wready(near_mem$dma_server_wready),
.dma_server_bvalid(near_mem$dma_server_bvalid),
.dma_server_bid(near_mem$dma_server_bid),
.dma_server_bresp(near_mem$dma_server_bresp),
.dma_server_arready(near_mem$dma_server_arready),
.dma_server_rvalid(near_mem$dma_server_rvalid),
.dma_server_rid(near_mem$dma_server_rid),
.dma_server_rdata(near_mem$dma_server_rdata),
.dma_server_rresp(near_mem$dma_server_rresp),
.dma_server_rlast(near_mem$dma_server_rlast),
.RDY_set_watch_tohost(),
.mv_tohost_value(near_mem$mv_tohost_value),
.RDY_mv_tohost_value(),
.RDY_ma_ddr4_ready(),
.mv_status(near_mem$mv_status));
// submodule soc_map
mkSoC_Map soc_map(.CLK(CLK),
.RST_N(RST_N),
.m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr),
.m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr),
.m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr),
.m_near_mem_io_addr_base(),
.m_near_mem_io_addr_size(),
.m_near_mem_io_addr_lim(),
.m_plic_addr_base(),
.m_plic_addr_size(),
.m_plic_addr_lim(),
.m_uart0_addr_base(),
.m_uart0_addr_size(),
.m_uart0_addr_lim(),
.m_boot_rom_addr_base(),
.m_boot_rom_addr_size(),
.m_boot_rom_addr_lim(),
.m_mem0_controller_addr_base(),
.m_mem0_controller_addr_size(),
.m_mem0_controller_addr_lim(),
.m_tcm_addr_base(),
.m_tcm_addr_size(),
.m_tcm_addr_lim(),
.m_is_mem_addr(),
.m_is_IO_addr(),
.m_is_near_mem_IO_addr(),
.m_pc_reset_value(soc_map$m_pc_reset_value),
.m_mtvec_reset_value(),
.m_nmivec_reset_value());
// submodule stage1_f_reset_reqs
FIFO20 #(.guarded(1'd1)) stage1_f_reset_reqs(.RST(RST_N),
.CLK(CLK),
.ENQ(stage1_f_reset_reqs$ENQ),
.DEQ(stage1_f_reset_reqs$DEQ),
.CLR(stage1_f_reset_reqs$CLR),
.FULL_N(stage1_f_reset_reqs$FULL_N),
.EMPTY_N(stage1_f_reset_reqs$EMPTY_N));
// submodule stage1_f_reset_rsps
FIFO20 #(.guarded(1'd1)) stage1_f_reset_rsps(.RST(RST_N),
.CLK(CLK),
.ENQ(stage1_f_reset_rsps$ENQ),
.DEQ(stage1_f_reset_rsps$DEQ),
.CLR(stage1_f_reset_rsps$CLR),
.FULL_N(stage1_f_reset_rsps$FULL_N),
.EMPTY_N(stage1_f_reset_rsps$EMPTY_N));
// submodule stage2_f_reset_reqs
FIFO20 #(.guarded(1'd1)) stage2_f_reset_reqs(.RST(RST_N),
.CLK(CLK),
.ENQ(stage2_f_reset_reqs$ENQ),
.DEQ(stage2_f_reset_reqs$DEQ),
.CLR(stage2_f_reset_reqs$CLR),
.FULL_N(stage2_f_reset_reqs$FULL_N),
.EMPTY_N(stage2_f_reset_reqs$EMPTY_N));
// submodule stage2_f_reset_rsps
FIFO20 #(.guarded(1'd1)) stage2_f_reset_rsps(.RST(RST_N),
.CLK(CLK),
.ENQ(stage2_f_reset_rsps$ENQ),
.DEQ(stage2_f_reset_rsps$DEQ),
.CLR(stage2_f_reset_rsps$CLR),
.FULL_N(stage2_f_reset_rsps$FULL_N),
.EMPTY_N(stage2_f_reset_rsps$EMPTY_N));
// submodule stage2_fbox
mkFBox_Top stage2_fbox(.verbosity(4'd0),
.CLK(CLK),
.RST_N(RST_N),
.req_f7(stage2_fbox$req_f7),
.req_opcode(stage2_fbox$req_opcode),
.req_rm(stage2_fbox$req_rm),
.req_rs2(stage2_fbox$req_rs2),
.req_v1(stage2_fbox$req_v1),
.req_v2(stage2_fbox$req_v2),
.req_v3(stage2_fbox$req_v3),
.EN_server_reset_request_put(stage2_fbox$EN_server_reset_request_put),
.EN_server_reset_response_get(stage2_fbox$EN_server_reset_response_get),
.EN_req(stage2_fbox$EN_req),
.RDY_server_reset_request_put(stage2_fbox$RDY_server_reset_request_put),
.RDY_server_reset_response_get(stage2_fbox$RDY_server_reset_response_get),
.valid(stage2_fbox$valid),
.word_fst(stage2_fbox$word_fst),
.word_snd(stage2_fbox$word_snd));
// submodule stage2_mbox
mkRISCV_MBox stage2_mbox(.CLK(CLK),
.RST_N(RST_N),
.req_f3(stage2_mbox$req_f3),
.req_is_OP_not_OP_32(stage2_mbox$req_is_OP_not_OP_32),
.req_v1(stage2_mbox$req_v1),
.req_v2(stage2_mbox$req_v2),
.set_verbosity_verbosity(stage2_mbox$set_verbosity_verbosity),
.EN_set_verbosity(stage2_mbox$EN_set_verbosity),
.EN_req_reset(stage2_mbox$EN_req_reset),
.EN_rsp_reset(stage2_mbox$EN_rsp_reset),
.EN_req(stage2_mbox$EN_req),
.RDY_set_verbosity(),
.RDY_req_reset(),
.RDY_rsp_reset(),
.valid(stage2_mbox$valid),
.word(stage2_mbox$word));
// submodule stage3_f_reset_reqs
FIFO20 #(.guarded(1'd1)) stage3_f_reset_reqs(.RST(RST_N),
.CLK(CLK),
.ENQ(stage3_f_reset_reqs$ENQ),
.DEQ(stage3_f_reset_reqs$DEQ),
.CLR(stage3_f_reset_reqs$CLR),
.FULL_N(stage3_f_reset_reqs$FULL_N),
.EMPTY_N(stage3_f_reset_reqs$EMPTY_N));
// submodule stage3_f_reset_rsps
FIFO20 #(.guarded(1'd1)) stage3_f_reset_rsps(.RST(RST_N),
.CLK(CLK),
.ENQ(stage3_f_reset_rsps$ENQ),
.DEQ(stage3_f_reset_rsps$DEQ),
.CLR(stage3_f_reset_rsps$CLR),
.FULL_N(stage3_f_reset_rsps$FULL_N),
.EMPTY_N(stage3_f_reset_rsps$EMPTY_N));
// submodule stageD_f_reset_reqs
FIFO20 #(.guarded(1'd1)) stageD_f_reset_reqs(.RST(RST_N),
.CLK(CLK),
.ENQ(stageD_f_reset_reqs$ENQ),
.DEQ(stageD_f_reset_reqs$DEQ),
.CLR(stageD_f_reset_reqs$CLR),
.FULL_N(stageD_f_reset_reqs$FULL_N),
.EMPTY_N(stageD_f_reset_reqs$EMPTY_N));
// submodule stageD_f_reset_rsps
FIFO20 #(.guarded(1'd1)) stageD_f_reset_rsps(.RST(RST_N),
.CLK(CLK),
.ENQ(stageD_f_reset_rsps$ENQ),
.DEQ(stageD_f_reset_rsps$DEQ),
.CLR(stageD_f_reset_rsps$CLR),
.FULL_N(stageD_f_reset_rsps$FULL_N),
.EMPTY_N(stageD_f_reset_rsps$EMPTY_N));
// submodule stageF_branch_predictor
mkBranch_Predictor stageF_branch_predictor(.CLK(CLK),
.RST_N(RST_N),
.bp_train_cf_info(stageF_branch_predictor$bp_train_cf_info),
.bp_train_instr(stageF_branch_predictor$bp_train_instr),
.bp_train_is_i32_not_i16(stageF_branch_predictor$bp_train_is_i32_not_i16),
.bp_train_pc(stageF_branch_predictor$bp_train_pc),
.predict_req_pc(stageF_branch_predictor$predict_req_pc),
.predict_rsp_instr(stageF_branch_predictor$predict_rsp_instr),
.predict_rsp_is_i32_not_i16(stageF_branch_predictor$predict_rsp_is_i32_not_i16),
.EN_reset(stageF_branch_predictor$EN_reset),
.EN_predict_req(stageF_branch_predictor$EN_predict_req),
.EN_bp_train(stageF_branch_predictor$EN_bp_train),
.RDY_reset(),
.RDY_predict_req(stageF_branch_predictor$RDY_predict_req),
.predict_rsp(stageF_branch_predictor$predict_rsp),
.RDY_bp_train());
// submodule stageF_f_reset_reqs
FIFO20 #(.guarded(1'd1)) stageF_f_reset_reqs(.RST(RST_N),
.CLK(CLK),
.ENQ(stageF_f_reset_reqs$ENQ),
.DEQ(stageF_f_reset_reqs$DEQ),
.CLR(stageF_f_reset_reqs$CLR),
.FULL_N(stageF_f_reset_reqs$FULL_N),
.EMPTY_N(stageF_f_reset_reqs$EMPTY_N));
// submodule stageF_f_reset_rsps
FIFO20 #(.guarded(1'd1)) stageF_f_reset_rsps(.RST(RST_N),
.CLK(CLK),
.ENQ(stageF_f_reset_rsps$ENQ),
.DEQ(stageF_f_reset_rsps$DEQ),
.CLR(stageF_f_reset_rsps$CLR),
.FULL_N(stageF_f_reset_rsps$FULL_N),
.EMPTY_N(stageF_f_reset_rsps$EMPTY_N));
// rule RL_rl_show_pipe
assign CAN_FIRE_RL_rl_show_pipe =
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56 &&
rg_state != 4'd0 &&
rg_state != 4'd1 &&
rg_state != 4'd12 ;
assign WILL_FIRE_RL_rl_show_pipe = CAN_FIRE_RL_rl_show_pipe ;
// rule RL_rl_stage2_nonpipe
assign CAN_FIRE_RL_rl_stage2_nonpipe =
rg_state == 4'd3 && !stage3_rg_full && stage2_rg_full &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d156 ;
assign WILL_FIRE_RL_rl_stage2_nonpipe = CAN_FIRE_RL_rl_stage2_nonpipe ;
// rule RL_rl_stage1_trap
assign CAN_FIRE_RL_rl_stage1_trap =
rg_state_7_EQ_3_326_AND_NOT_csr_regfile_interr_ETC___d2779 &&
(!stageF_rg_full ||
near_mem$imem_valid &&
near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d2119) ;
assign WILL_FIRE_RL_rl_stage1_trap = CAN_FIRE_RL_rl_stage1_trap ;
// rule RL_rl_trap
assign CAN_FIRE_RL_rl_trap =
rg_state == 4'd4 &&
(!stageF_rg_full ||
near_mem$imem_valid &&
near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d2119) ;
assign WILL_FIRE_RL_rl_trap = CAN_FIRE_RL_rl_trap ;
// rule RL_rl_stage1_CSRR_W
assign CAN_FIRE_RL_rl_stage1_CSRR_W = MUX_rg_state$write_1__SEL_10 ;
assign WILL_FIRE_RL_rl_stage1_CSRR_W = MUX_rg_state$write_1__SEL_10 ;
// rule RL_rl_stage1_CSRR_W_2
assign CAN_FIRE_RL_rl_stage1_CSRR_W_2 = rg_state == 4'd6 ;
assign WILL_FIRE_RL_rl_stage1_CSRR_W_2 = rg_state == 4'd6 ;
// rule RL_rl_stage1_CSRR_S_or_C
assign CAN_FIRE_RL_rl_stage1_CSRR_S_or_C = MUX_rg_state$write_1__SEL_11 ;
assign WILL_FIRE_RL_rl_stage1_CSRR_S_or_C = MUX_rg_state$write_1__SEL_11 ;
// rule RL_rl_stage1_CSRR_S_or_C_2
assign CAN_FIRE_RL_rl_stage1_CSRR_S_or_C_2 = rg_state == 4'd7 ;
assign WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 = rg_state == 4'd7 ;
// rule RL_rl_stage1_restart_after_csrrx
assign CAN_FIRE_RL_rl_stage1_restart_after_csrrx =
(imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_near_mem__ETC___d2251 ||
near_mem$imem_instr[17:16] != 2'b11) &&
stageF_branch_predictor$RDY_predict_req &&
rg_state_7_EQ_8_864_AND_NOT_stageF_rg_full_094_ETC___d2865 ;
assign WILL_FIRE_RL_rl_stage1_restart_after_csrrx =
CAN_FIRE_RL_rl_stage1_restart_after_csrrx ;
// rule RL_rl_stage1_xRET
assign CAN_FIRE_RL_rl_stage1_xRET =
rg_state_7_EQ_3_326_AND_NOT_csr_regfile_interr_ETC___d2753 &&
stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d2343 &&
IF_stage1_rg_full_31_THEN_stage1_rg_stage_inpu_ETC___d2897 &&
(!stageF_rg_full ||
near_mem$imem_valid &&
near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d2119) ;
assign WILL_FIRE_RL_rl_stage1_xRET = CAN_FIRE_RL_rl_stage1_xRET ;
// rule RL_rl_stage1_FENCE_I
assign CAN_FIRE_RL_rl_stage1_FENCE_I = MUX_rg_state$write_1__SEL_12 ;
assign WILL_FIRE_RL_rl_stage1_FENCE_I = MUX_rg_state$write_1__SEL_12 ;
// rule RL_rl_finish_FENCE_I
assign CAN_FIRE_RL_rl_finish_FENCE_I =
(imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_near_mem__ETC___d2251 ||
near_mem$imem_instr[17:16] != 2'b11) &&
stageF_branch_predictor$RDY_predict_req &&
near_mem$RDY_server_fence_i_response_get &&
rg_state == 4'd9 ;
assign WILL_FIRE_RL_rl_finish_FENCE_I = CAN_FIRE_RL_rl_finish_FENCE_I ;
// rule RL_rl_stage1_FENCE
assign CAN_FIRE_RL_rl_stage1_FENCE = MUX_rg_state$write_1__SEL_13 ;
assign WILL_FIRE_RL_rl_stage1_FENCE = MUX_rg_state$write_1__SEL_13 ;
// rule RL_rl_finish_FENCE
assign CAN_FIRE_RL_rl_finish_FENCE =
(imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_near_mem__ETC___d2251 ||
near_mem$imem_instr[17:16] != 2'b11) &&
stageF_branch_predictor$RDY_predict_req &&
near_mem$RDY_server_fence_response_get &&
rg_state == 4'd10 ;
assign WILL_FIRE_RL_rl_finish_FENCE = CAN_FIRE_RL_rl_finish_FENCE ;
// rule RL_rl_stage1_SFENCE_VMA
assign CAN_FIRE_RL_rl_stage1_SFENCE_VMA = MUX_rg_state$write_1__SEL_14 ;
assign WILL_FIRE_RL_rl_stage1_SFENCE_VMA = MUX_rg_state$write_1__SEL_14 ;
// rule RL_rl_finish_SFENCE_VMA
assign CAN_FIRE_RL_rl_finish_SFENCE_VMA =
(imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_near_mem__ETC___d2251 ||
near_mem$imem_instr[17:16] != 2'b11) &&
stageF_branch_predictor$RDY_predict_req &&
near_mem$RDY_sfence_vma_server_response_get &&
rg_state == 4'd11 ;
assign WILL_FIRE_RL_rl_finish_SFENCE_VMA =
CAN_FIRE_RL_rl_finish_SFENCE_VMA ;
// rule RL_rl_stage1_WFI
assign CAN_FIRE_RL_rl_stage1_WFI = MUX_rg_state$write_1__SEL_15 ;
assign WILL_FIRE_RL_rl_stage1_WFI = MUX_rg_state$write_1__SEL_15 ;
// rule RL_rl_WFI_resume
assign CAN_FIRE_RL_rl_WFI_resume =
(imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_near_mem__ETC___d2251 ||
near_mem$imem_instr[17:16] != 2'b11) &&
stageF_branch_predictor$RDY_predict_req &&
rg_state_7_EQ_12_4_AND_csr_regfile_wfi_resume__ETC___d2937 ;
assign WILL_FIRE_RL_rl_WFI_resume = CAN_FIRE_RL_rl_WFI_resume ;
// rule RL_rl_reset_from_WFI
assign CAN_FIRE_RL_rl_reset_from_WFI =
rg_state == 4'd12 && f_reset_reqs$EMPTY_N ;
assign WILL_FIRE_RL_rl_reset_from_WFI = MUX_rg_state$write_1__SEL_5 ;
// rule RL_rl_trap_fetch
assign CAN_FIRE_RL_rl_trap_fetch =
(imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_near_mem__ETC___d2251 ||
near_mem$imem_instr[17:16] != 2'b11) &&
stageF_branch_predictor$RDY_predict_req &&
rg_state_7_EQ_5_941_AND_NOT_stageF_rg_full_094_ETC___d2942 ;
assign WILL_FIRE_RL_rl_trap_fetch = CAN_FIRE_RL_rl_trap_fetch ;
// rule RL_rl_stage1_interrupt
assign CAN_FIRE_RL_rl_stage1_interrupt =
csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2953 &&
(!stageF_rg_full ||
near_mem$imem_valid &&
near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d2119) ;
assign WILL_FIRE_RL_rl_stage1_interrupt = CAN_FIRE_RL_rl_stage1_interrupt ;
// rule RL_imem_rl_assert_fail
assign CAN_FIRE_RL_imem_rl_assert_fail = !near_mem$imem_is_i32_not_i16 ;
assign WILL_FIRE_RL_imem_rl_assert_fail = CAN_FIRE_RL_imem_rl_assert_fail ;
// rule RL_rl_reset_complete
assign CAN_FIRE_RL_rl_reset_complete =
gpr_regfile$RDY_server_reset_response_get &&
fpr_regfile$RDY_server_reset_response_get &&
near_mem$RDY_server_reset_response_get &&
csr_regfile$RDY_server_reset_response_get &&
stageF_f_reset_rsps_i_notEmpty__241_AND_stageD_ETC___d2261 &&
rg_state == 4'd1 ;
assign WILL_FIRE_RL_rl_reset_complete = MUX_rg_state$write_1__SEL_2 ;
// rule RL_rl_pipe
assign CAN_FIRE_RL_rl_pipe =
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2325 &&
rg_state_7_EQ_3_326_AND_stage3_rg_full_8_OR_st_ETC___d2338 &&
(NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2346 ||
IF_NOT_stage1_rg_full_31_76_OR_NOT_stage1_rg_s_ETC___d2347 ||
stage2_rg_full ||
stage3_rg_full) ;
assign WILL_FIRE_RL_rl_pipe =
CAN_FIRE_RL_rl_pipe && !WILL_FIRE_RL_imem_rl_fetch_next_32b ;
// rule RL_rl_reset_start
assign CAN_FIRE_RL_rl_reset_start =
gpr_regfile$RDY_server_reset_request_put &&
fpr_regfile$RDY_server_reset_request_put &&
near_mem$RDY_server_reset_request_put &&
csr_regfile_RDY_server_reset_request_put__219__ETC___d2231 &&
rg_state == 4'd0 ;
assign WILL_FIRE_RL_rl_reset_start = CAN_FIRE_RL_rl_reset_start ;
// rule RL_imem_rl_fetch_next_32b
assign CAN_FIRE_RL_imem_rl_fetch_next_32b =
imem_rg_pc[1:0] != 2'b0 && near_mem$imem_valid &&
!near_mem$imem_exc &&
imem_rg_pc_BITS_63_TO_2_4_EQ_near_mem_imem_pc__ETC___d17 &&
near_mem$imem_instr[17:16] == 2'b11 ;
assign WILL_FIRE_RL_imem_rl_fetch_next_32b =
CAN_FIRE_RL_imem_rl_fetch_next_32b ;
// rule RL_stage3_rl_reset
assign CAN_FIRE_RL_stage3_rl_reset =
stage3_f_reset_reqs$EMPTY_N && stage3_f_reset_rsps$FULL_N ;
assign WILL_FIRE_RL_stage3_rl_reset = CAN_FIRE_RL_stage3_rl_reset ;
// rule RL_stage2_rl_reset_end
assign CAN_FIRE_RL_stage2_rl_reset_end =
stage2_fbox$RDY_server_reset_response_get &&
stage2_f_reset_rsps$FULL_N &&
stage2_rg_resetting ;
assign WILL_FIRE_RL_stage2_rl_reset_end = CAN_FIRE_RL_stage2_rl_reset_end ;
// rule RL_stage2_rl_reset_begin
assign CAN_FIRE_RL_stage2_rl_reset_begin =
stage2_fbox$RDY_server_reset_request_put &&
stage2_f_reset_reqs$EMPTY_N ;
assign WILL_FIRE_RL_stage2_rl_reset_begin =
CAN_FIRE_RL_stage2_rl_reset_begin ;
// rule RL_stage1_rl_reset
assign CAN_FIRE_RL_stage1_rl_reset =
stage1_f_reset_reqs$EMPTY_N && stage1_f_reset_rsps$FULL_N ;
assign WILL_FIRE_RL_stage1_rl_reset = CAN_FIRE_RL_stage1_rl_reset ;
// rule RL_stageD_rl_reset
assign CAN_FIRE_RL_stageD_rl_reset =
stageD_f_reset_reqs$EMPTY_N && stageD_f_reset_rsps$FULL_N ;
assign WILL_FIRE_RL_stageD_rl_reset = CAN_FIRE_RL_stageD_rl_reset ;
// rule RL_stageF_rl_reset
assign CAN_FIRE_RL_stageF_rl_reset =
stageF_f_reset_reqs$EMPTY_N && stageF_f_reset_rsps$FULL_N ;
assign WILL_FIRE_RL_stageF_rl_reset = CAN_FIRE_RL_stageF_rl_reset ;
// inputs to muxes for submodule ports
assign MUX_csr_regfile$mav_csr_write_1__SEL_1 =
WILL_FIRE_RL_rl_stage1_CSRR_W_2 &&
csr_regfile$access_permitted_1 ;
assign MUX_gpr_regfile$write_rd_1__SEL_2 =
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 &&
csr_regfile$access_permitted_2 ;
assign MUX_imem_rg_cache_addr$write_1__SEL_1 =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ;
assign MUX_imem_rg_cache_addr$write_1__SEL_2 =
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2675 &&
csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2693 ;
assign MUX_rg_next_pc$write_1__SEL_1 =
WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2630 ;
assign MUX_rg_next_pc$write_1__SEL_2 =
WILL_FIRE_RL_rl_stage1_WFI || WILL_FIRE_RL_rl_stage1_FENCE ||
WILL_FIRE_RL_rl_stage1_FENCE_I ||
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ||
WILL_FIRE_RL_rl_stage1_CSRR_W ||
WILL_FIRE_RL_rl_stage1_SFENCE_VMA ;
assign MUX_rg_state$write_1__SEL_1 =
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2675 &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2319 ;
assign MUX_rg_state$write_1__SEL_2 =
CAN_FIRE_RL_rl_reset_complete &&
!WILL_FIRE_RL_imem_rl_fetch_next_32b ;
assign MUX_rg_state$write_1__SEL_5 =
CAN_FIRE_RL_rl_reset_from_WFI && !WILL_FIRE_RL_rl_WFI_resume ;
assign MUX_rg_state$write_1__SEL_7 =
WILL_FIRE_RL_rl_trap_fetch || WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;
assign MUX_rg_state$write_1__SEL_8 =
WILL_FIRE_RL_rl_stage1_interrupt ||
WILL_FIRE_RL_rl_stage1_trap ||
WILL_FIRE_RL_rl_stage2_nonpipe ;
assign MUX_rg_state$write_1__SEL_9 =
WILL_FIRE_RL_rl_stage1_xRET || WILL_FIRE_RL_rl_trap ;
assign MUX_rg_state$write_1__SEL_10 =
rg_state_7_EQ_3_326_AND_NOT_csr_regfile_interr_ETC___d2817 &&
NOT_stage1_rg_stage_input_32_BIT_332_77_83_AND_ETC___d1004 ;
assign MUX_rg_state$write_1__SEL_11 =
rg_state_7_EQ_3_326_AND_NOT_csr_regfile_interr_ETC___d2817 &&
NOT_stage1_rg_stage_input_32_BIT_332_77_83_AND_ETC___d1019 ;
assign MUX_rg_state$write_1__SEL_12 =
near_mem$RDY_server_fence_i_request_put &&
rg_state_7_EQ_3_326_AND_NOT_csr_regfile_interr_ETC___d2908 ;
assign MUX_rg_state$write_1__SEL_13 =
near_mem$RDY_server_fence_request_put &&
rg_state_7_EQ_3_326_AND_NOT_csr_regfile_interr_ETC___d2917 ;
assign MUX_rg_state$write_1__SEL_14 =
near_mem$RDY_sfence_vma_server_request_put &&
rg_state_7_EQ_3_326_AND_NOT_csr_regfile_interr_ETC___d2926 ;
assign MUX_rg_state$write_1__SEL_15 =
rg_state_7_EQ_3_326_AND_NOT_csr_regfile_interr_ETC___d2817 &&
NOT_stage1_rg_stage_input_32_BIT_332_77_83_AND_ETC___d1129 &&
(!stageF_rg_full ||
near_mem$imem_valid &&
near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d2119) ;
assign MUX_rg_trap_info$write_1__SEL_1 =
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ||
WILL_FIRE_RL_rl_stage1_CSRR_W ;
assign MUX_rg_trap_instr$write_1__SEL_1 =
WILL_FIRE_RL_rl_stage1_interrupt ||
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ||
WILL_FIRE_RL_rl_stage1_CSRR_W ||
WILL_FIRE_RL_rl_stage1_trap ;
assign MUX_rg_trap_interrupt$write_1__SEL_1 =
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ||
WILL_FIRE_RL_rl_stage1_CSRR_W ||
WILL_FIRE_RL_rl_stage1_trap ||
WILL_FIRE_RL_rl_stage2_nonpipe ;
always@(rg_trap_instr or
csr_regfile$read_csr or
y__h35607 or
IF_csr_regfile_read_csr_rg_trap_instr_798_BITS_ETC___d2856)
begin
case (rg_trap_instr[14:12])
3'b010, 3'b110:
MUX_csr_regfile$mav_csr_write_2__VAL_2 =
IF_csr_regfile_read_csr_rg_trap_instr_798_BITS_ETC___d2856;
default: MUX_csr_regfile$mav_csr_write_2__VAL_2 =
csr_regfile$read_csr[63:0] & y__h35607;
endcase
end
assign MUX_imem_rg_cache_addr$write_1__VAL_1 =
(near_mem$imem_valid && !near_mem$imem_exc) ?
near_mem$imem_pc :
64'h0000000000000001 ;
assign MUX_imem_rg_cache_addr$write_1__VAL_2 =
near_mem$imem_exc ? 64'h0000000000000001 : near_mem$imem_pc ;
assign MUX_imem_rg_tval$write_1__VAL_1 =
(NOT_soc_map_m_pc_reset_value__268_BITS_1_TO_0__ETC___d2284 &&
near_mem$imem_instr[17:16] == 2'b11) ?
addr_of_b32___1__h27521 :
soc_map$m_pc_reset_value ;
assign MUX_imem_rg_tval$write_1__VAL_2 =
(NOT_stageF_branch_predictor_predict_rsp_NOT_im_ETC___d2707 &&
near_mem$imem_instr[17:16] == 2'b11) ?
addr_of_b32___1__h32461 :
stageF_branch_predictor$predict_rsp ;
assign MUX_imem_rg_tval$write_1__VAL_3 =
(NOT_rg_next_pc_867_BITS_1_TO_0_868_EQ_0b0_869__ETC___d2875 &&
near_mem$imem_instr[17:16] == 2'b11) ?
addr_of_b32___1__h44012 :
rg_next_pc ;
assign MUX_imem_rg_tval$write_1__VAL_4 = near_mem$imem_pc + 64'd4 ;
assign MUX_near_mem$imem_req_2__VAL_1 =
(NOT_soc_map_m_pc_reset_value__268_BITS_1_TO_0__ETC___d2284 &&
near_mem$imem_instr[17:16] == 2'b11) ?
addr_of_b32___1__h27521 :
addr_of_b32__h27393 ;
assign MUX_near_mem$imem_req_2__VAL_2 =
(NOT_stageF_branch_predictor_predict_rsp_NOT_im_ETC___d2707 &&
near_mem$imem_instr[17:16] == 2'b11) ?
addr_of_b32___1__h32461 :
addr_of_b32__h32333 ;
assign MUX_near_mem$imem_req_2__VAL_4 =
(NOT_rg_next_pc_867_BITS_1_TO_0_868_EQ_0b0_869__ETC___d2875 &&
near_mem$imem_instr[17:16] == 2'b11) ?
addr_of_b32___1__h44012 :
addr_of_b32__h43884 ;
assign MUX_rg_state$write_1__VAL_2 = rg_run_on_reset ? 4'd3 : 4'd2 ;
assign MUX_rg_state$write_1__VAL_3 =
csr_regfile$access_permitted_1 ? 4'd8 : 4'd4 ;
assign MUX_rg_state$write_1__VAL_4 =
csr_regfile$access_permitted_2 ? 4'd8 : 4'd4 ;
assign MUX_rg_trap_info$write_1__VAL_1 =
{ stage1_rg_stage_input[401:338],
4'd2,
stage1_rg_stage_input[332] ?
stage1_rg_stage_input[327:264] :
trap_info_tval__h15117 } ;
assign MUX_rg_trap_info$write_1__VAL_2 =
{ value__h8670,
near_mem$dmem_exc_code,
stage2_rg_stage2[389:326] } ;
assign MUX_rg_trap_info$write_1__VAL_3 =
{ stage1_rg_stage_input[401:338],
stage1_rg_stage_input[332] ?
stage1_rg_stage_input[331:264] :
{ alu_outputs_exc_code__h11737, trap_info_tval__h15117 } } ;
assign MUX_rg_trap_info$write_1__VAL_4 =
{ stage1_rg_stage_input[401:338], x_exc_code__h44308, 64'd0 } ;
assign MUX_rg_trap_instr$write_1__VAL_1 = stage1_rg_stage_input[263:232] ;
assign MUX_stage1_rg_full$write_1__VAL_2 =
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2634 &&
stageD_rg_full ||
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2728 ;
assign MUX_stage2_rg_full$write_1__VAL_2 =
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2306 ?
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
(IF_NOT_stage1_rg_full_31_76_OR_NOT_stage1_rg_s_ETC___d2405 ||
stage2_rg_stage2[397:395] != 3'd0 &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d2686 &&
stage2_rg_full) :
stage2_rg_stage2[397:395] != 3'd0 &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d2686 &&
stage2_rg_full ;
assign MUX_stage3_rg_full$write_1__VAL_2 =
stage2_rg_full &&
(stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d2299) ;
assign MUX_stageD_rg_full$write_1__VAL_2 =
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2675 ||
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2310 &&
stageD_rg_full ;
assign MUX_stageF_rg_full$write_1__VAL_2 =
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2675 ?
csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2739 ||
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2310 &&
stageD_rg_full :
(IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2310 &&
stageD_rg_full ||
!near_mem$imem_valid ||
NOT_near_mem_imem_exc__1_2_AND_imem_rg_pc_BITS_ETC___d2112) &&
stageF_rg_full ;
// register cfg_logdelay
assign cfg_logdelay$D_IN = set_verbosity_logdelay ;
assign cfg_logdelay$EN = EN_set_verbosity ;
// register cfg_verbosity
assign cfg_verbosity$D_IN = set_verbosity_verbosity ;
assign cfg_verbosity$EN = EN_set_verbosity ;
// register imem_rg_cache_addr
always@(MUX_imem_rg_cache_addr$write_1__SEL_1 or
MUX_imem_rg_cache_addr$write_1__VAL_1 or
MUX_imem_rg_cache_addr$write_1__SEL_2 or
MUX_imem_rg_cache_addr$write_1__VAL_2 or
WILL_FIRE_RL_imem_rl_fetch_next_32b or
near_mem$imem_pc or MUX_rg_state$write_1__SEL_7)
begin
case (1'b1) // synopsys parallel_case
MUX_imem_rg_cache_addr$write_1__SEL_1:
imem_rg_cache_addr$D_IN = MUX_imem_rg_cache_addr$write_1__VAL_1;
MUX_imem_rg_cache_addr$write_1__SEL_2:
imem_rg_cache_addr$D_IN = MUX_imem_rg_cache_addr$write_1__VAL_2;
WILL_FIRE_RL_imem_rl_fetch_next_32b:
imem_rg_cache_addr$D_IN = near_mem$imem_pc;
MUX_rg_state$write_1__SEL_7:
imem_rg_cache_addr$D_IN = MUX_imem_rg_cache_addr$write_1__VAL_1;
default: imem_rg_cache_addr$D_IN =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign imem_rg_cache_addr$EN =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2675 &&
csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2693 ||
WILL_FIRE_RL_imem_rl_fetch_next_32b ||
WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;
// register imem_rg_cache_b16
assign imem_rg_cache_b16$D_IN = near_mem$imem_instr[31:16] ;
assign imem_rg_cache_b16$EN =
MUX_rg_state$write_1__SEL_7 && near_mem$imem_valid &&
!near_mem$imem_exc ||
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset &&
near_mem$imem_valid &&
!near_mem$imem_exc ||
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2675 &&
csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2693 &&
!near_mem$imem_exc ||
WILL_FIRE_RL_imem_rl_fetch_next_32b ;
// register imem_rg_f3
assign imem_rg_f3$D_IN = 3'b010 ;
assign imem_rg_f3$EN =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2675 &&
csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2693 ||
WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;
// register imem_rg_mstatus_MXR
assign imem_rg_mstatus_MXR$D_IN = csr_regfile$read_mstatus[19] ;
assign imem_rg_mstatus_MXR$EN =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2675 &&
csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2693 ||
WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;
// register imem_rg_pc
always@(MUX_imem_rg_cache_addr$write_1__SEL_1 or
soc_map$m_pc_reset_value or
MUX_imem_rg_cache_addr$write_1__SEL_2 or
stageF_branch_predictor$predict_rsp or
MUX_rg_state$write_1__SEL_7 or rg_next_pc)
begin
case (1'b1) // synopsys parallel_case
MUX_imem_rg_cache_addr$write_1__SEL_1:
imem_rg_pc$D_IN = soc_map$m_pc_reset_value;
MUX_imem_rg_cache_addr$write_1__SEL_2:
imem_rg_pc$D_IN = stageF_branch_predictor$predict_rsp;
MUX_rg_state$write_1__SEL_7: imem_rg_pc$D_IN = rg_next_pc;
default: imem_rg_pc$D_IN =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign imem_rg_pc$EN =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2675 &&
csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2693 ||
WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;
// register imem_rg_priv
assign imem_rg_priv$D_IN = rg_cur_priv ;
assign imem_rg_priv$EN =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2675 &&
csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2693 ||
WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;
// register imem_rg_satp
assign imem_rg_satp$D_IN = csr_regfile$read_satp ;
assign imem_rg_satp$EN =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2675 &&
csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2693 ||
WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;
// register imem_rg_sstatus_SUM
assign imem_rg_sstatus_SUM$D_IN = csr_regfile$read_sstatus[18] ;
assign imem_rg_sstatus_SUM$EN =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2675 &&
csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2693 ||
WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;
// register imem_rg_tval
always@(MUX_imem_rg_cache_addr$write_1__SEL_1 or
MUX_imem_rg_tval$write_1__VAL_1 or
MUX_imem_rg_cache_addr$write_1__SEL_2 or
MUX_imem_rg_tval$write_1__VAL_2 or
MUX_rg_state$write_1__SEL_7 or
MUX_imem_rg_tval$write_1__VAL_3 or
WILL_FIRE_RL_imem_rl_fetch_next_32b or
MUX_imem_rg_tval$write_1__VAL_4)
begin
case (1'b1) // synopsys parallel_case
MUX_imem_rg_cache_addr$write_1__SEL_1:
imem_rg_tval$D_IN = MUX_imem_rg_tval$write_1__VAL_1;
MUX_imem_rg_cache_addr$write_1__SEL_2:
imem_rg_tval$D_IN = MUX_imem_rg_tval$write_1__VAL_2;
MUX_rg_state$write_1__SEL_7:
imem_rg_tval$D_IN = MUX_imem_rg_tval$write_1__VAL_3;
WILL_FIRE_RL_imem_rl_fetch_next_32b:
imem_rg_tval$D_IN = MUX_imem_rg_tval$write_1__VAL_4;
default: imem_rg_tval$D_IN =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign imem_rg_tval$EN =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2675 &&
csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2693 ||
WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ||
WILL_FIRE_RL_imem_rl_fetch_next_32b ;
// register rg_csr_pc
assign rg_csr_pc$D_IN = stage1_rg_stage_input[401:338] ;
assign rg_csr_pc$EN = MUX_rg_trap_info$write_1__SEL_1 ;
// register rg_csr_val1
assign rg_csr_val1$D_IN = x_out_data_to_stage2_val1__h10121 ;
assign rg_csr_val1$EN = MUX_rg_trap_info$write_1__SEL_1 ;
// register rg_cur_priv
always@(WILL_FIRE_RL_rl_trap or
csr_regfile$csr_trap_actions or
WILL_FIRE_RL_rl_stage1_xRET or
csr_regfile$csr_ret_actions or WILL_FIRE_RL_rl_reset_start)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_rl_trap:
rg_cur_priv$D_IN = csr_regfile$csr_trap_actions[1:0];
WILL_FIRE_RL_rl_stage1_xRET:
rg_cur_priv$D_IN = csr_regfile$csr_ret_actions[65:64];
WILL_FIRE_RL_rl_reset_start: rg_cur_priv$D_IN = 2'b11;
default: rg_cur_priv$D_IN = 2'b10 /* unspecified value */ ;
endcase
end
assign rg_cur_priv$EN =
WILL_FIRE_RL_rl_trap || WILL_FIRE_RL_rl_stage1_xRET ||
WILL_FIRE_RL_rl_reset_start ;
// register rg_epoch
always@(MUX_imem_rg_cache_addr$write_1__SEL_1 or
new_epoch__h26813 or
MUX_rg_state$write_1__SEL_7 or WILL_FIRE_RL_rl_reset_start)
begin
case (1'b1) // synopsys parallel_case
MUX_imem_rg_cache_addr$write_1__SEL_1:
rg_epoch$D_IN = new_epoch__h26813;
MUX_rg_state$write_1__SEL_7: rg_epoch$D_IN = new_epoch__h26813;
WILL_FIRE_RL_rl_reset_start: rg_epoch$D_IN = 2'd0;
default: rg_epoch$D_IN = 2'b10 /* unspecified value */ ;
endcase
end
assign rg_epoch$EN =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ||
WILL_FIRE_RL_rl_reset_start ;
// register rg_mstatus_MXR
assign rg_mstatus_MXR$D_IN = csr_regfile$read_mstatus[19] ;
assign rg_mstatus_MXR$EN = MUX_rg_state$write_1__SEL_9 ;
// register rg_next_pc
always@(MUX_rg_next_pc$write_1__SEL_1 or
x_out_next_pc__h9864 or
MUX_rg_next_pc$write_1__SEL_2 or
WILL_FIRE_RL_rl_trap or
csr_regfile$csr_trap_actions or
WILL_FIRE_RL_rl_stage1_xRET or csr_regfile$csr_ret_actions)
begin
case (1'b1) // synopsys parallel_case
MUX_rg_next_pc$write_1__SEL_1: rg_next_pc$D_IN = x_out_next_pc__h9864;
MUX_rg_next_pc$write_1__SEL_2: rg_next_pc$D_IN = x_out_next_pc__h9864;
WILL_FIRE_RL_rl_trap:
rg_next_pc$D_IN = csr_regfile$csr_trap_actions[193:130];
WILL_FIRE_RL_rl_stage1_xRET:
rg_next_pc$D_IN = csr_regfile$csr_ret_actions[129:66];
default: rg_next_pc$D_IN =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign rg_next_pc$EN =
WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2630 ||
WILL_FIRE_RL_rl_stage1_WFI ||
WILL_FIRE_RL_rl_stage1_FENCE ||
WILL_FIRE_RL_rl_stage1_FENCE_I ||
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ||
WILL_FIRE_RL_rl_stage1_CSRR_W ||
WILL_FIRE_RL_rl_stage1_SFENCE_VMA ||
WILL_FIRE_RL_rl_trap ||
WILL_FIRE_RL_rl_stage1_xRET ;
// register rg_run_on_reset
assign rg_run_on_reset$D_IN = f_reset_reqs$D_OUT ;
assign rg_run_on_reset$EN = CAN_FIRE_RL_rl_reset_start ;
// register rg_sstatus_SUM
assign rg_sstatus_SUM$D_IN = csr_regfile$read_sstatus[18] ;
assign rg_sstatus_SUM$EN = MUX_rg_state$write_1__SEL_9 ;
// register rg_start_CPI_cycles
assign rg_start_CPI_cycles$D_IN = csr_regfile$read_csr_mcycle ;
assign rg_start_CPI_cycles$EN = MUX_imem_rg_cache_addr$write_1__SEL_1 ;
// register rg_start_CPI_instrs
assign rg_start_CPI_instrs$D_IN = csr_regfile$read_csr_minstret ;
assign rg_start_CPI_instrs$EN = MUX_imem_rg_cache_addr$write_1__SEL_1 ;
// register rg_state
always@(WILL_FIRE_RL_rl_reset_complete or
MUX_rg_state$write_1__VAL_2 or
WILL_FIRE_RL_rl_stage1_CSRR_W_2 or
MUX_rg_state$write_1__VAL_3 or
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 or
MUX_rg_state$write_1__VAL_4 or
WILL_FIRE_RL_rl_reset_from_WFI or
WILL_FIRE_RL_rl_reset_start or
MUX_rg_state$write_1__SEL_7 or
MUX_rg_state$write_1__SEL_8 or
MUX_rg_state$write_1__SEL_1 or
MUX_rg_state$write_1__SEL_9 or
WILL_FIRE_RL_rl_stage1_CSRR_W or
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C or
WILL_FIRE_RL_rl_stage1_FENCE_I or
WILL_FIRE_RL_rl_stage1_FENCE or
WILL_FIRE_RL_rl_stage1_SFENCE_VMA or WILL_FIRE_RL_rl_stage1_WFI)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_rl_reset_complete:
rg_state$D_IN = MUX_rg_state$write_1__VAL_2;
WILL_FIRE_RL_rl_stage1_CSRR_W_2:
rg_state$D_IN = MUX_rg_state$write_1__VAL_3;
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2:
rg_state$D_IN = MUX_rg_state$write_1__VAL_4;
WILL_FIRE_RL_rl_reset_from_WFI: rg_state$D_IN = 4'd0;
WILL_FIRE_RL_rl_reset_start: rg_state$D_IN = 4'd1;
MUX_rg_state$write_1__SEL_7: rg_state$D_IN = 4'd3;
MUX_rg_state$write_1__SEL_8: rg_state$D_IN = 4'd4;
MUX_rg_state$write_1__SEL_1 || MUX_rg_state$write_1__SEL_9:
rg_state$D_IN = 4'd5;
WILL_FIRE_RL_rl_stage1_CSRR_W: rg_state$D_IN = 4'd6;
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C: rg_state$D_IN = 4'd7;
WILL_FIRE_RL_rl_stage1_FENCE_I: rg_state$D_IN = 4'd9;
WILL_FIRE_RL_rl_stage1_FENCE: rg_state$D_IN = 4'd10;
WILL_FIRE_RL_rl_stage1_SFENCE_VMA: rg_state$D_IN = 4'd11;
WILL_FIRE_RL_rl_stage1_WFI: rg_state$D_IN = 4'd12;
default: rg_state$D_IN = 4'b1010 /* unspecified value */ ;
endcase
end
assign rg_state$EN =
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2675 &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2319 ||
WILL_FIRE_RL_rl_reset_complete ||
WILL_FIRE_RL_rl_stage1_CSRR_W_2 ||
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 ||
WILL_FIRE_RL_rl_reset_from_WFI ||
WILL_FIRE_RL_rl_reset_start ||
WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ||
WILL_FIRE_RL_rl_stage1_interrupt ||
WILL_FIRE_RL_rl_stage1_trap ||
WILL_FIRE_RL_rl_stage2_nonpipe ||
WILL_FIRE_RL_rl_stage1_xRET ||
WILL_FIRE_RL_rl_trap ||
WILL_FIRE_RL_rl_stage1_CSRR_W ||
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ||
WILL_FIRE_RL_rl_stage1_FENCE_I ||
WILL_FIRE_RL_rl_stage1_FENCE ||
WILL_FIRE_RL_rl_stage1_SFENCE_VMA ||
WILL_FIRE_RL_rl_stage1_WFI ;
// register rg_trap_info
always@(MUX_rg_trap_info$write_1__SEL_1 or
MUX_rg_trap_info$write_1__VAL_1 or
WILL_FIRE_RL_rl_stage2_nonpipe or
MUX_rg_trap_info$write_1__VAL_2 or
WILL_FIRE_RL_rl_stage1_trap or
MUX_rg_trap_info$write_1__VAL_3 or
WILL_FIRE_RL_rl_stage1_interrupt or MUX_rg_trap_info$write_1__VAL_4)
begin
case (1'b1) // synopsys parallel_case
MUX_rg_trap_info$write_1__SEL_1:
rg_trap_info$D_IN = MUX_rg_trap_info$write_1__VAL_1;
WILL_FIRE_RL_rl_stage2_nonpipe:
rg_trap_info$D_IN = MUX_rg_trap_info$write_1__VAL_2;
WILL_FIRE_RL_rl_stage1_trap:
rg_trap_info$D_IN = MUX_rg_trap_info$write_1__VAL_3;
WILL_FIRE_RL_rl_stage1_interrupt:
rg_trap_info$D_IN = MUX_rg_trap_info$write_1__VAL_4;
default: rg_trap_info$D_IN =
132'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign rg_trap_info$EN =
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ||
WILL_FIRE_RL_rl_stage1_CSRR_W ||
WILL_FIRE_RL_rl_stage2_nonpipe ||
WILL_FIRE_RL_rl_stage1_trap ||
WILL_FIRE_RL_rl_stage1_interrupt ;
// register rg_trap_instr
assign rg_trap_instr$D_IN =
MUX_rg_trap_instr$write_1__SEL_1 ?
stage1_rg_stage_input[263:232] :
stage2_rg_stage2[429:398] ;
assign rg_trap_instr$EN =
WILL_FIRE_RL_rl_stage1_interrupt ||
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ||
WILL_FIRE_RL_rl_stage1_CSRR_W ||
WILL_FIRE_RL_rl_stage1_trap ||
WILL_FIRE_RL_rl_stage2_nonpipe ;
// register rg_trap_interrupt
assign rg_trap_interrupt$D_IN = !MUX_rg_trap_interrupt$write_1__SEL_1 ;
assign rg_trap_interrupt$EN =
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ||
WILL_FIRE_RL_rl_stage1_CSRR_W ||
WILL_FIRE_RL_rl_stage1_trap ||
WILL_FIRE_RL_rl_stage2_nonpipe ||
WILL_FIRE_RL_rl_stage1_interrupt ;
// register stage1_rg_full
always@(WILL_FIRE_RL_stage1_rl_reset or
WILL_FIRE_RL_rl_pipe or
MUX_stage1_rg_full$write_1__VAL_2 or
MUX_imem_rg_cache_addr$write_1__SEL_1 or
WILL_FIRE_RL_rl_stage1_WFI or
WILL_FIRE_RL_rl_finish_SFENCE_VMA or
WILL_FIRE_RL_rl_finish_FENCE or
WILL_FIRE_RL_rl_finish_FENCE_I or
WILL_FIRE_RL_rl_stage1_xRET or
WILL_FIRE_RL_rl_stage1_restart_after_csrrx or WILL_FIRE_RL_rl_trap)
case (1'b1)
WILL_FIRE_RL_stage1_rl_reset: stage1_rg_full$D_IN = 1'd0;
WILL_FIRE_RL_rl_pipe:
stage1_rg_full$D_IN = MUX_stage1_rg_full$write_1__VAL_2;
MUX_imem_rg_cache_addr$write_1__SEL_1 || WILL_FIRE_RL_rl_stage1_WFI ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_xRET ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ||
WILL_FIRE_RL_rl_trap:
stage1_rg_full$D_IN = 1'd0;
default: stage1_rg_full$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign stage1_rg_full$EN =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_pipe ||
WILL_FIRE_RL_rl_stage1_WFI ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_xRET ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ||
WILL_FIRE_RL_rl_trap ||
WILL_FIRE_RL_stage1_rl_reset ;
// register stage1_rg_stage_input
assign stage1_rg_stage_input$D_IN =
{ stageD_rg_data[233:170],
stageD_rg_data[167:166],
stageD_rg_data[169:168],
stageD_rg_data[165:96],
_theResult____h5881,
stageD_rg_data[79:0],
_theResult____h5881[6:0],
_theResult____h5881[11:7],
_theResult____h5881[19:15],
_theResult____h5881[24:20],
_theResult____h5881[31:27],
_theResult____h5881[31:20],
_theResult____h5881[14:12],
_theResult____h5881[31:27],
_theResult____h5881[31:25],
decoded_instr_funct10__h30753,
_theResult____h5881[31:20],
decoded_instr_imm12_S__h30755,
decoded_instr_imm13_SB__h30756,
_theResult____h5881[31:12],
decoded_instr_imm21_UJ__h30758,
_theResult____h5881[27:20],
_theResult____h5881[26:25] } ;
assign stage1_rg_stage_input$EN =
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2634 &&
stageD_rg_full ;
// register stage2_rg_full
always@(WILL_FIRE_RL_stage2_rl_reset_begin or
WILL_FIRE_RL_rl_pipe or
MUX_stage2_rg_full$write_1__VAL_2 or
MUX_imem_rg_cache_addr$write_1__SEL_1 or WILL_FIRE_RL_rl_trap)
case (1'b1)
WILL_FIRE_RL_stage2_rl_reset_begin: stage2_rg_full$D_IN = 1'd0;
WILL_FIRE_RL_rl_pipe:
stage2_rg_full$D_IN = MUX_stage2_rg_full$write_1__VAL_2;
MUX_imem_rg_cache_addr$write_1__SEL_1 || WILL_FIRE_RL_rl_trap:
stage2_rg_full$D_IN = 1'd0;
default: stage2_rg_full$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign stage2_rg_full$EN =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_pipe ||
WILL_FIRE_RL_rl_trap ||
WILL_FIRE_RL_stage2_rl_reset_begin ;
// register stage2_rg_resetting
assign stage2_rg_resetting$D_IN = WILL_FIRE_RL_stage2_rl_reset_begin ;
assign stage2_rg_resetting$EN =
WILL_FIRE_RL_stage2_rl_reset_end ||
WILL_FIRE_RL_stage2_rl_reset_begin ;
// register stage2_rg_stage2
assign stage2_rg_stage2$D_IN =
{ rg_cur_priv,
stage1_rg_stage_input[401:338],
IF_stage1_rg_stage_input_32_BITS_335_TO_334_33_ETC___d2511 } ;
assign stage2_rg_stage2$EN =
WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2407 ;
// register stage3_rg_full
always@(WILL_FIRE_RL_stage3_rl_reset or
WILL_FIRE_RL_rl_pipe or
MUX_stage3_rg_full$write_1__VAL_2 or
MUX_imem_rg_cache_addr$write_1__SEL_1)
case (1'b1)
WILL_FIRE_RL_stage3_rl_reset: stage3_rg_full$D_IN = 1'd0;
WILL_FIRE_RL_rl_pipe:
stage3_rg_full$D_IN = MUX_stage3_rg_full$write_1__VAL_2;
MUX_imem_rg_cache_addr$write_1__SEL_1: stage3_rg_full$D_IN = 1'd0;
default: stage3_rg_full$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign stage3_rg_full$EN =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_pipe ||
WILL_FIRE_RL_stage3_rl_reset ;
// register stage3_rg_stage3
assign stage3_rg_stage3$D_IN =
{ stage2_rg_stage2[493:398],
stage2_rg_stage2[495:494],
1'd1,
x_out_data_to_stage3_rd__h8340,
x_out_data_to_stage3_rd_val__h8341,
stage2_rg_stage2[397:395] != 3'd0 &&
stage2_rg_stage2[397:395] != 3'd1 &&
stage2_rg_stage2[397:395] != 3'd4 &&
stage2_rg_stage2[397:395] != 3'd2 &&
stage2_rg_stage2[397:395] != 3'd3,
stage2_rg_stage2[397:395] != 3'd0 &&
CASE_stage2_rg_stage2_BITS_397_TO_395_1_stage2_ETC__q4,
x_out_data_to_stage3_fpr_flags__h8344,
x_out_data_to_stage3_frd_val__h8345 } ;
assign stage3_rg_stage3$EN =
WILL_FIRE_RL_rl_pipe && stage2_rg_full &&
(stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d2299) ;
// register stageD_rg_data
assign stageD_rg_data$D_IN =
{ imem_rg_pc,
stageF_rg_epoch,
stageF_rg_priv,
NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d2072 ||
imem_rg_pc[1:0] == 2'b0 &&
imem_rg_pc_BITS_63_TO_2_4_EQ_near_mem_imem_pc__ETC___d17 &&
near_mem$imem_instr[1:0] == 2'b11,
near_mem$imem_exc,
near_mem$imem_exc_code,
imem_rg_tval,
d_instr__h25360,
stageF_branch_predictor$predict_rsp } ;
assign stageD_rg_data$EN =
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2675 ;
// register stageD_rg_full
always@(WILL_FIRE_RL_stageD_rl_reset or
WILL_FIRE_RL_rl_pipe or
MUX_stageD_rg_full$write_1__VAL_2 or
MUX_imem_rg_cache_addr$write_1__SEL_1 or
WILL_FIRE_RL_rl_trap_fetch or
WILL_FIRE_RL_rl_WFI_resume or
WILL_FIRE_RL_rl_stage1_WFI or
WILL_FIRE_RL_rl_finish_SFENCE_VMA or
WILL_FIRE_RL_rl_finish_FENCE or
WILL_FIRE_RL_rl_finish_FENCE_I or
WILL_FIRE_RL_rl_stage1_xRET or
WILL_FIRE_RL_rl_stage1_restart_after_csrrx or WILL_FIRE_RL_rl_trap)
case (1'b1)
WILL_FIRE_RL_stageD_rl_reset: stageD_rg_full$D_IN = 1'd0;
WILL_FIRE_RL_rl_pipe:
stageD_rg_full$D_IN = MUX_stageD_rg_full$write_1__VAL_2;
MUX_imem_rg_cache_addr$write_1__SEL_1 || WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_stage1_WFI ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_xRET ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ||
WILL_FIRE_RL_rl_trap:
stageD_rg_full$D_IN = 1'd0;
default: stageD_rg_full$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign stageD_rg_full$EN =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_pipe ||
WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_stage1_WFI ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_xRET ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ||
WILL_FIRE_RL_rl_trap ||
WILL_FIRE_RL_stageD_rl_reset ;
// register stageF_rg_epoch
always@(WILL_FIRE_RL_stageF_rl_reset or
MUX_imem_rg_cache_addr$write_1__SEL_2 or
stageF_rg_epoch or
MUX_imem_rg_cache_addr$write_1__SEL_1 or
new_epoch__h26813 or
WILL_FIRE_RL_rl_trap_fetch or
WILL_FIRE_RL_rl_WFI_resume or
WILL_FIRE_RL_rl_finish_SFENCE_VMA or
WILL_FIRE_RL_rl_finish_FENCE or
WILL_FIRE_RL_rl_finish_FENCE_I or
WILL_FIRE_RL_rl_stage1_restart_after_csrrx)
case (1'b1)
WILL_FIRE_RL_stageF_rl_reset: stageF_rg_epoch$D_IN = 2'd0;
MUX_imem_rg_cache_addr$write_1__SEL_2:
stageF_rg_epoch$D_IN = stageF_rg_epoch;
MUX_imem_rg_cache_addr$write_1__SEL_1:
stageF_rg_epoch$D_IN = new_epoch__h26813;
WILL_FIRE_RL_rl_trap_fetch: stageF_rg_epoch$D_IN = new_epoch__h26813;
WILL_FIRE_RL_rl_WFI_resume: stageF_rg_epoch$D_IN = new_epoch__h26813;
WILL_FIRE_RL_rl_finish_SFENCE_VMA:
stageF_rg_epoch$D_IN = new_epoch__h26813;
WILL_FIRE_RL_rl_finish_FENCE: stageF_rg_epoch$D_IN = new_epoch__h26813;
WILL_FIRE_RL_rl_finish_FENCE_I: stageF_rg_epoch$D_IN = new_epoch__h26813;
WILL_FIRE_RL_rl_stage1_restart_after_csrrx:
stageF_rg_epoch$D_IN = new_epoch__h26813;
default: stageF_rg_epoch$D_IN = 2'b10 /* unspecified value */ ;
endcase
assign stageF_rg_epoch$EN =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2675 &&
csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2693 ||
WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ||
WILL_FIRE_RL_stageF_rl_reset ;
// register stageF_rg_full
always@(WILL_FIRE_RL_stageF_rl_reset or
WILL_FIRE_RL_rl_pipe or
MUX_stageF_rg_full$write_1__VAL_2 or
MUX_imem_rg_cache_addr$write_1__SEL_1 or
WILL_FIRE_RL_rl_trap_fetch or
WILL_FIRE_RL_rl_WFI_resume or
WILL_FIRE_RL_rl_finish_SFENCE_VMA or
WILL_FIRE_RL_rl_finish_FENCE or
WILL_FIRE_RL_rl_finish_FENCE_I or
WILL_FIRE_RL_rl_stage1_restart_after_csrrx)
case (1'b1)
WILL_FIRE_RL_stageF_rl_reset: stageF_rg_full$D_IN = 1'd0;
WILL_FIRE_RL_rl_pipe:
stageF_rg_full$D_IN = MUX_stageF_rg_full$write_1__VAL_2;
MUX_imem_rg_cache_addr$write_1__SEL_1 || WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx:
stageF_rg_full$D_IN = 1'd1;
default: stageF_rg_full$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign stageF_rg_full$EN =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_pipe ||
WILL_FIRE_RL_stageF_rl_reset ||
WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;
// register stageF_rg_priv
assign stageF_rg_priv$D_IN = rg_cur_priv ;
assign stageF_rg_priv$EN =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2675 &&
csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2693 ||
WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;
// submodule csr_regfile
assign csr_regfile$access_permitted_1_csr_addr = rg_trap_instr[31:20] ;
assign csr_regfile$access_permitted_1_priv = rg_cur_priv ;
assign csr_regfile$access_permitted_1_read_not_write = 1'd0 ;
assign csr_regfile$access_permitted_2_csr_addr = rg_trap_instr[31:20] ;
assign csr_regfile$access_permitted_2_priv = rg_cur_priv ;
assign csr_regfile$access_permitted_2_read_not_write =
rs1_val__h35329 == 64'd0 ;
assign csr_regfile$csr_counter_read_fault_csr_addr = 12'h0 ;
assign csr_regfile$csr_counter_read_fault_priv = 2'h0 ;
assign csr_regfile$csr_ret_actions_from_priv =
(stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage1_rg_stage_input_32_BIT_332_77_83_AND_ETC___d2884) ?
2'b11 :
((stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
!stage1_rg_stage_input[332] &&
stage1_rg_stage_input_32_BITS_151_TO_145_78_EQ_ETC___d2892) ?
2'b01 :
2'b0) ;
assign csr_regfile$csr_trap_actions_exc_code = rg_trap_info[67:64] ;
assign csr_regfile$csr_trap_actions_from_priv = rg_cur_priv ;
assign csr_regfile$csr_trap_actions_interrupt =
rg_trap_interrupt && !csr_regfile$nmi_pending ;
assign csr_regfile$csr_trap_actions_nmi =
rg_trap_interrupt && csr_regfile$nmi_pending ;
assign csr_regfile$csr_trap_actions_pc = rg_trap_info[131:68] ;
assign csr_regfile$csr_trap_actions_xtval = rg_trap_info[63:0] ;
assign csr_regfile$interrupt_pending_cur_priv = rg_cur_priv ;
assign csr_regfile$m_external_interrupt_req_set_not_clear =
m_external_interrupt_req_set_not_clear ;
assign csr_regfile$ma_update_fcsr_fflags_flags = stage3_rg_stage3[68:64] ;
assign csr_regfile$ma_update_mstatus_fs_fs = 2'h3 ;
assign csr_regfile$mav_csr_write_csr_addr = rg_trap_instr[31:20] ;
assign csr_regfile$mav_csr_write_word =
MUX_csr_regfile$mav_csr_write_1__SEL_1 ?
rs1_val__h34495 :
MUX_csr_regfile$mav_csr_write_2__VAL_2 ;
assign csr_regfile$mav_read_csr_csr_addr = 12'h0 ;
assign csr_regfile$mv_update_fcsr_fflags_flags = 5'h0 ;
assign csr_regfile$mv_update_mstatus_fs_fs = 2'h0 ;
assign csr_regfile$nmi_req_set_not_clear = nmi_req_set_not_clear ;
assign csr_regfile$read_csr_csr_addr = rg_trap_instr[31:20] ;
assign csr_regfile$read_csr_port2_csr_addr = 12'h0 ;
assign csr_regfile$s_external_interrupt_req_set_not_clear =
s_external_interrupt_req_set_not_clear ;
assign csr_regfile$software_interrupt_req_set_not_clear =
software_interrupt_req_set_not_clear ;
assign csr_regfile$timer_interrupt_req_set_not_clear =
timer_interrupt_req_set_not_clear ;
assign csr_regfile$EN_server_reset_request_put =
CAN_FIRE_RL_rl_reset_start ;
assign csr_regfile$EN_server_reset_response_get =
MUX_rg_state$write_1__SEL_2 ;
assign csr_regfile$EN_mav_read_csr = 1'b0 ;
assign csr_regfile$EN_mav_csr_write =
WILL_FIRE_RL_rl_stage1_CSRR_W_2 &&
csr_regfile$access_permitted_1 ||
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 &&
csr_regfile$access_permitted_2 &&
rg_trap_instr[19:15] != 5'd0 ;
assign csr_regfile$EN_ma_update_fcsr_fflags =
WILL_FIRE_RL_rl_pipe && stage3_rg_full &&
stage3_rg_stage3[140] &&
stage3_rg_stage3[70] ;
assign csr_regfile$EN_ma_update_mstatus_fs =
WILL_FIRE_RL_rl_pipe && stage3_rg_full &&
stage3_rg_stage3[140] &&
(stage3_rg_stage3[70] || stage3_rg_stage3[69]) ;
assign csr_regfile$EN_csr_trap_actions = CAN_FIRE_RL_rl_trap ;
assign csr_regfile$EN_csr_ret_actions = CAN_FIRE_RL_rl_stage1_xRET ;
assign csr_regfile$EN_csr_minstret_incr =
WILL_FIRE_RL_rl_pipe && stage2_rg_full &&
(stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d2299) ||
WILL_FIRE_RL_rl_stage1_CSRR_W_2 &&
csr_regfile$access_permitted_1 ||
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 &&
csr_regfile$access_permitted_2 ||
WILL_FIRE_RL_rl_stage1_WFI ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_xRET ;
assign csr_regfile$EN_debug = 1'b0 ;
// submodule f_reset_reqs
assign f_reset_reqs$D_IN = hart0_server_reset_request_put ;
assign f_reset_reqs$ENQ = EN_hart0_server_reset_request_put ;
assign f_reset_reqs$DEQ = CAN_FIRE_RL_rl_reset_start ;
assign f_reset_reqs$CLR = 1'b0 ;
// submodule f_reset_rsps
assign f_reset_rsps$D_IN = rg_run_on_reset ;
assign f_reset_rsps$ENQ = MUX_rg_state$write_1__SEL_2 ;
assign f_reset_rsps$DEQ = EN_hart0_server_reset_response_get ;
assign f_reset_rsps$CLR = 1'b0 ;
// submodule fpr_regfile
assign fpr_regfile$read_rs1_port2_rs1 = 5'h0 ;
assign fpr_regfile$read_rs1_rs1 = stage1_rg_stage_input[139:135] ;
assign fpr_regfile$read_rs2_rs2 = stage1_rg_stage_input[134:130] ;
assign fpr_regfile$read_rs3_rs3 = stage1_rg_stage_input[129:125] ;
assign fpr_regfile$write_rd_rd = stage3_rg_stage3[139:135] ;
assign fpr_regfile$write_rd_rd_val = stage3_rg_stage3[63:0] ;
assign fpr_regfile$EN_server_reset_request_put =
CAN_FIRE_RL_rl_reset_start ;
assign fpr_regfile$EN_server_reset_response_get =
MUX_rg_state$write_1__SEL_2 ;
assign fpr_regfile$EN_write_rd =
WILL_FIRE_RL_rl_pipe && stage3_rg_full &&
stage3_rg_stage3[140] &&
stage3_rg_stage3[69] ;
// submodule gpr_regfile
assign gpr_regfile$read_rs1_port2_rs1 = 5'h0 ;
assign gpr_regfile$read_rs1_rs1 = stage1_rg_stage_input[139:135] ;
assign gpr_regfile$read_rs2_rs2 = stage1_rg_stage_input[134:130] ;
assign gpr_regfile$write_rd_rd =
(MUX_csr_regfile$mav_csr_write_1__SEL_1 ||
MUX_gpr_regfile$write_rd_1__SEL_2) ?
rg_trap_instr[11:7] :
stage3_rg_stage3[139:135] ;
assign gpr_regfile$write_rd_rd_val =
(MUX_csr_regfile$mav_csr_write_1__SEL_1 ||
MUX_gpr_regfile$write_rd_1__SEL_2) ?
csr_regfile$read_csr[63:0] :
stage3_rg_stage3[134:71] ;
assign gpr_regfile$EN_server_reset_request_put =
CAN_FIRE_RL_rl_reset_start ;
assign gpr_regfile$EN_server_reset_response_get =
MUX_rg_state$write_1__SEL_2 ;
assign gpr_regfile$EN_write_rd =
WILL_FIRE_RL_rl_stage1_CSRR_W_2 &&
csr_regfile$access_permitted_1 ||
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 &&
csr_regfile$access_permitted_2 ||
WILL_FIRE_RL_rl_pipe && stage3_rg_full &&
stage3_rg_stage3[140] &&
!stage3_rg_stage3[69] ;
// submodule near_mem
assign near_mem$dma_server_araddr = dma_server_araddr ;
assign near_mem$dma_server_arburst = dma_server_arburst ;
assign near_mem$dma_server_arcache = dma_server_arcache ;
assign near_mem$dma_server_arid = dma_server_arid ;
assign near_mem$dma_server_arlen = dma_server_arlen ;
assign near_mem$dma_server_arlock = dma_server_arlock ;
assign near_mem$dma_server_arprot = dma_server_arprot ;
assign near_mem$dma_server_arqos = dma_server_arqos ;
assign near_mem$dma_server_arregion = dma_server_arregion ;
assign near_mem$dma_server_arsize = dma_server_arsize ;
assign near_mem$dma_server_arvalid = dma_server_arvalid ;
assign near_mem$dma_server_awaddr = dma_server_awaddr ;
assign near_mem$dma_server_awburst = dma_server_awburst ;
assign near_mem$dma_server_awcache = dma_server_awcache ;
assign near_mem$dma_server_awid = dma_server_awid ;
assign near_mem$dma_server_awlen = dma_server_awlen ;
assign near_mem$dma_server_awlock = dma_server_awlock ;
assign near_mem$dma_server_awprot = dma_server_awprot ;
assign near_mem$dma_server_awqos = dma_server_awqos ;
assign near_mem$dma_server_awregion = dma_server_awregion ;
assign near_mem$dma_server_awsize = dma_server_awsize ;
assign near_mem$dma_server_awvalid = dma_server_awvalid ;
assign near_mem$dma_server_bready = dma_server_bready ;
assign near_mem$dma_server_rready = dma_server_rready ;
assign near_mem$dma_server_wdata = dma_server_wdata ;
assign near_mem$dma_server_wlast = dma_server_wlast ;
assign near_mem$dma_server_wstrb = dma_server_wstrb ;
assign near_mem$dma_server_wvalid = dma_server_wvalid ;
assign near_mem$dmem_req_addr = x_out_data_to_stage2_addr__h10120 ;
assign near_mem$dmem_req_amo_funct7 =
x_out_data_to_stage2_val1__h10121[6:0] ;
assign near_mem$dmem_req_f3 = MUX_rg_trap_instr$write_1__VAL_1[14:12] ;
assign near_mem$dmem_req_mstatus_MXR = csr_regfile$read_mstatus[19] ;
assign near_mem$dmem_req_op =
(stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
(stage1_rg_stage_input[151:145] == 7'b0000011 ||
stage1_rg_stage_input[151:145] == 7'b0000111)) ?
2'd0 :
((stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
(stage1_rg_stage_input[151:145] == 7'b0100011 ||
stage1_rg_stage_input[151:145] == 7'b0100111)) ?
2'd1 :
2'd2) ;
assign near_mem$dmem_req_priv =
csr_regfile$read_mstatus[17] ?
csr_regfile$read_mstatus[12:11] :
rg_cur_priv ;
assign near_mem$dmem_req_satp = csr_regfile$read_satp ;
assign near_mem$dmem_req_sstatus_SUM = csr_regfile$read_sstatus[18] ;
always@(stage1_rg_stage_input or
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d1531 or
alu_outputs___1_fval2__h10701 or branch_target__h10301)
begin
case (stage1_rg_stage_input[151:145])
7'b0100111:
near_mem$dmem_req_store_value = alu_outputs___1_fval2__h10701;
7'b1100011: near_mem$dmem_req_store_value = branch_target__h10301;
default: near_mem$dmem_req_store_value =
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d1531;
endcase
end
assign near_mem$imem_master_arready = imem_master_arready ;
assign near_mem$imem_master_awready = imem_master_awready ;
assign near_mem$imem_master_bid = imem_master_bid ;
assign near_mem$imem_master_bresp = imem_master_bresp ;
assign near_mem$imem_master_bvalid = imem_master_bvalid ;
assign near_mem$imem_master_rdata = imem_master_rdata ;
assign near_mem$imem_master_rid = imem_master_rid ;
assign near_mem$imem_master_rlast = imem_master_rlast ;
assign near_mem$imem_master_rresp = imem_master_rresp ;
assign near_mem$imem_master_rvalid = imem_master_rvalid ;
assign near_mem$imem_master_wready = imem_master_wready ;
always@(MUX_imem_rg_cache_addr$write_1__SEL_1 or
MUX_near_mem$imem_req_2__VAL_1 or
MUX_imem_rg_cache_addr$write_1__SEL_2 or
MUX_near_mem$imem_req_2__VAL_2 or
WILL_FIRE_RL_imem_rl_fetch_next_32b or
MUX_imem_rg_tval$write_1__VAL_4 or
MUX_rg_state$write_1__SEL_7 or MUX_near_mem$imem_req_2__VAL_4)
begin
case (1'b1) // synopsys parallel_case
MUX_imem_rg_cache_addr$write_1__SEL_1:
near_mem$imem_req_addr = MUX_near_mem$imem_req_2__VAL_1;
MUX_imem_rg_cache_addr$write_1__SEL_2:
near_mem$imem_req_addr = MUX_near_mem$imem_req_2__VAL_2;
WILL_FIRE_RL_imem_rl_fetch_next_32b:
near_mem$imem_req_addr = MUX_imem_rg_tval$write_1__VAL_4;
MUX_rg_state$write_1__SEL_7:
near_mem$imem_req_addr = MUX_near_mem$imem_req_2__VAL_4;
default: near_mem$imem_req_addr =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign near_mem$imem_req_f3 =
WILL_FIRE_RL_imem_rl_fetch_next_32b ? imem_rg_f3 : 3'b010 ;
assign near_mem$imem_req_mstatus_MXR =
(MUX_imem_rg_cache_addr$write_1__SEL_1 ||
MUX_imem_rg_cache_addr$write_1__SEL_2 ||
MUX_rg_state$write_1__SEL_7) ?
csr_regfile$read_mstatus[19] :
imem_rg_mstatus_MXR ;
assign near_mem$imem_req_priv =
(MUX_imem_rg_cache_addr$write_1__SEL_1 ||
MUX_imem_rg_cache_addr$write_1__SEL_2 ||
MUX_rg_state$write_1__SEL_7) ?
rg_cur_priv :
imem_rg_priv ;
assign near_mem$imem_req_satp =
WILL_FIRE_RL_imem_rl_fetch_next_32b ?
imem_rg_satp :
csr_regfile$read_satp ;
assign near_mem$imem_req_sstatus_SUM =
(MUX_imem_rg_cache_addr$write_1__SEL_1 ||
MUX_imem_rg_cache_addr$write_1__SEL_2 ||
MUX_rg_state$write_1__SEL_7) ?
csr_regfile$read_sstatus[18] :
imem_rg_sstatus_SUM ;
assign near_mem$mem_master_arready = mem_master_arready ;
assign near_mem$mem_master_awready = mem_master_awready ;
assign near_mem$mem_master_bid = mem_master_bid ;
assign near_mem$mem_master_bresp = mem_master_bresp ;
assign near_mem$mem_master_bvalid = mem_master_bvalid ;
assign near_mem$mem_master_rdata = mem_master_rdata ;
assign near_mem$mem_master_rid = mem_master_rid ;
assign near_mem$mem_master_rlast = mem_master_rlast ;
assign near_mem$mem_master_rresp = mem_master_rresp ;
assign near_mem$mem_master_rvalid = mem_master_rvalid ;
assign near_mem$mem_master_wready = mem_master_wready ;
assign near_mem$server_fence_request_put =
8'b10101010 /* unspecified value */ ;
assign near_mem$set_watch_tohost_tohost_addr =
set_watch_tohost_tohost_addr ;
assign near_mem$set_watch_tohost_watch_tohost =
set_watch_tohost_watch_tohost ;
assign near_mem$EN_server_reset_request_put = CAN_FIRE_RL_rl_reset_start ;
assign near_mem$EN_server_reset_response_get = MUX_rg_state$write_1__SEL_2 ;
assign near_mem$EN_imem_req =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2675 &&
csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2693 ||
WILL_FIRE_RL_imem_rl_fetch_next_32b ||
WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;
assign near_mem$EN_dmem_req =
WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2541 ;
assign near_mem$EN_server_fence_i_request_put =
MUX_rg_state$write_1__SEL_12 ;
assign near_mem$EN_server_fence_i_response_get =
CAN_FIRE_RL_rl_finish_FENCE_I ;
assign near_mem$EN_server_fence_request_put = MUX_rg_state$write_1__SEL_13 ;
assign near_mem$EN_server_fence_response_get = CAN_FIRE_RL_rl_finish_FENCE ;
assign near_mem$EN_sfence_vma_server_request_put =
MUX_rg_state$write_1__SEL_14 ;
assign near_mem$EN_sfence_vma_server_response_get =
CAN_FIRE_RL_rl_finish_SFENCE_VMA ;
assign near_mem$EN_set_watch_tohost = EN_set_watch_tohost ;
assign near_mem$EN_ma_ddr4_ready = EN_ma_ddr4_ready ;
// submodule soc_map
assign soc_map$m_is_IO_addr_addr = 64'h0 ;
assign soc_map$m_is_mem_addr_addr = 64'h0 ;
assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ;
// submodule stage1_f_reset_reqs
assign stage1_f_reset_reqs$ENQ = CAN_FIRE_RL_rl_reset_start ;
assign stage1_f_reset_reqs$DEQ = CAN_FIRE_RL_stage1_rl_reset ;
assign stage1_f_reset_reqs$CLR = 1'b0 ;
// submodule stage1_f_reset_rsps
assign stage1_f_reset_rsps$ENQ = CAN_FIRE_RL_stage1_rl_reset ;
assign stage1_f_reset_rsps$DEQ = MUX_rg_state$write_1__SEL_2 ;
assign stage1_f_reset_rsps$CLR = 1'b0 ;
// submodule stage2_f_reset_reqs
assign stage2_f_reset_reqs$ENQ = CAN_FIRE_RL_rl_reset_start ;
assign stage2_f_reset_reqs$DEQ = CAN_FIRE_RL_stage2_rl_reset_begin ;
assign stage2_f_reset_reqs$CLR = 1'b0 ;
// submodule stage2_f_reset_rsps
assign stage2_f_reset_rsps$ENQ = CAN_FIRE_RL_stage2_rl_reset_end ;
assign stage2_f_reset_rsps$DEQ = MUX_rg_state$write_1__SEL_2 ;
assign stage2_f_reset_rsps$CLR = 1'b0 ;
// submodule stage2_fbox
assign stage2_fbox$req_f7 = MUX_rg_trap_instr$write_1__VAL_1[31:25] ;
assign stage2_fbox$req_opcode = MUX_rg_trap_instr$write_1__VAL_1[6:0] ;
assign stage2_fbox$req_rm = rm__h10284 ;
assign stage2_fbox$req_rs2 = MUX_rg_trap_instr$write_1__VAL_1[24:20] ;
assign stage2_fbox$req_v1 =
NOT_csr_regfile_read_mstatus__9_BITS_14_TO_13__ETC___d2505 ?
x_out_data_to_stage2_val1__h10121 :
x_out_data_to_stage2_fval1__h10123 ;
assign stage2_fbox$req_v2 = alu_outputs___1_fval2__h10701 ;
assign stage2_fbox$req_v3 = x_out_data_to_stage2_fval3__h10125 ;
assign stage2_fbox$EN_server_reset_request_put =
CAN_FIRE_RL_stage2_rl_reset_begin ;
assign stage2_fbox$EN_server_reset_response_get =
CAN_FIRE_RL_stage2_rl_reset_end ;
assign stage2_fbox$EN_req =
WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2591 ;
// submodule stage2_mbox
assign stage2_mbox$req_f3 = MUX_rg_trap_instr$write_1__VAL_1[14:12] ;
assign stage2_mbox$req_is_OP_not_OP_32 =
!MUX_rg_trap_instr$write_1__VAL_1[3] ;
assign stage2_mbox$req_v1 = x_out_data_to_stage2_val1__h10121 ;
assign stage2_mbox$req_v2 = x_out_data_to_stage2_val2__h10122 ;
assign stage2_mbox$set_verbosity_verbosity = 4'h0 ;
assign stage2_mbox$EN_set_verbosity = 1'b0 ;
assign stage2_mbox$EN_req_reset = 1'b0 ;
assign stage2_mbox$EN_rsp_reset = 1'b0 ;
assign stage2_mbox$EN_req =
WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2575 ;
// submodule stage3_f_reset_reqs
assign stage3_f_reset_reqs$ENQ = CAN_FIRE_RL_rl_reset_start ;
assign stage3_f_reset_reqs$DEQ = CAN_FIRE_RL_stage3_rl_reset ;
assign stage3_f_reset_reqs$CLR = 1'b0 ;
// submodule stage3_f_reset_rsps
assign stage3_f_reset_rsps$ENQ = CAN_FIRE_RL_stage3_rl_reset ;
assign stage3_f_reset_rsps$DEQ = MUX_rg_state$write_1__SEL_2 ;
assign stage3_f_reset_rsps$CLR = 1'b0 ;
// submodule stageD_f_reset_reqs
assign stageD_f_reset_reqs$ENQ = CAN_FIRE_RL_rl_reset_start ;
assign stageD_f_reset_reqs$DEQ = CAN_FIRE_RL_stageD_rl_reset ;
assign stageD_f_reset_reqs$CLR = 1'b0 ;
// submodule stageD_f_reset_rsps
assign stageD_f_reset_rsps$ENQ = CAN_FIRE_RL_stageD_rl_reset ;
assign stageD_f_reset_rsps$DEQ = MUX_rg_state$write_1__SEL_2 ;
assign stageD_f_reset_rsps$CLR = 1'b0 ;
// submodule stageF_branch_predictor
assign stageF_branch_predictor$bp_train_cf_info =
(stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d2303 &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334) ?
{ CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q23,
stage1_rg_stage_input[401:338],
stage1_rg_stage_input[151:145] != 7'b1100011 ||
IF_stage1_rg_stage_input_32_BITS_112_TO_110_80_ETC___d432,
x_out_cf_info_fallthru_PC__h16274,
alu_outputs_cf_info_taken_PC__h16267 } :
195'h6AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ;
assign stageF_branch_predictor$bp_train_instr = d_instr__h25360 ;
assign stageF_branch_predictor$bp_train_is_i32_not_i16 =
NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d2072 ||
imem_rg_pc[1:0] == 2'b0 &&
imem_rg_pc_BITS_63_TO_2_4_EQ_near_mem_imem_pc__ETC___d17 &&
near_mem$imem_instr[1:0] == 2'b11 ;
assign stageF_branch_predictor$bp_train_pc = imem_rg_pc ;
always@(MUX_imem_rg_cache_addr$write_1__SEL_1 or
soc_map$m_pc_reset_value or
MUX_imem_rg_cache_addr$write_1__SEL_2 or
stageF_branch_predictor$predict_rsp or
MUX_rg_state$write_1__SEL_7 or rg_next_pc)
begin
case (1'b1) // synopsys parallel_case
MUX_imem_rg_cache_addr$write_1__SEL_1:
stageF_branch_predictor$predict_req_pc = soc_map$m_pc_reset_value;
MUX_imem_rg_cache_addr$write_1__SEL_2:
stageF_branch_predictor$predict_req_pc =
stageF_branch_predictor$predict_rsp;
MUX_rg_state$write_1__SEL_7:
stageF_branch_predictor$predict_req_pc = rg_next_pc;
default: stageF_branch_predictor$predict_req_pc =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign stageF_branch_predictor$predict_rsp_instr = d_instr__h25360 ;
assign stageF_branch_predictor$predict_rsp_is_i32_not_i16 =
NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d2072 ||
imem_rg_pc[1:0] == 2'b0 &&
imem_rg_pc_BITS_63_TO_2_4_EQ_near_mem_imem_pc__ETC___d17 &&
near_mem$imem_instr[1:0] == 2'b11 ;
assign stageF_branch_predictor$EN_reset = 1'b0 ;
assign stageF_branch_predictor$EN_predict_req =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2675 &&
csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2693 ||
WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;
assign stageF_branch_predictor$EN_bp_train =
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2675 ;
// submodule stageF_f_reset_reqs
assign stageF_f_reset_reqs$ENQ = CAN_FIRE_RL_rl_reset_start ;
assign stageF_f_reset_reqs$DEQ = CAN_FIRE_RL_stageF_rl_reset ;
assign stageF_f_reset_reqs$CLR = 1'b0 ;
// submodule stageF_f_reset_rsps
assign stageF_f_reset_rsps$ENQ = CAN_FIRE_RL_stageF_rl_reset ;
assign stageF_f_reset_rsps$DEQ = MUX_rg_state$write_1__SEL_2 ;
assign stageF_f_reset_rsps$CLR = 1'b0 ;
// remaining internal signals
assign IF_IF_stage1_rg_stage_input_32_BITS_151_TO_145_ETC___d1657 =
next_pc__h9847 == stage1_rg_stage_input[215:152] ;
assign IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2310 =
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2306 ?
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
!IF_IF_stage1_rg_stage_input_32_BITS_151_TO_145_ETC___d1657 &&
stageF_rg_full &&
(!near_mem$imem_valid ||
NOT_near_mem_imem_exc__1_2_AND_imem_rg_pc_BITS_ETC___d2112) :
stage1_rg_full ;
assign IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2313 =
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2310 &&
stageD_rg_full ||
!stageF_rg_full ||
!near_mem$imem_valid ||
NOT_near_mem_imem_exc__1_2_AND_imem_rg_pc_BITS_ETC___d2112 ;
assign IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2325 =
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2313 ||
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2319 ||
(imem_rg_pc[1:0] == 2'b0 || near_mem$imem_exc ||
!imem_rg_pc_BITS_63_TO_2_4_EQ_near_mem_imem_pc__ETC___d17 ||
near_mem$imem_instr[17:16] != 2'b11) &&
stageF_branch_predictor$RDY_predict_req ;
assign IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2634 =
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2306 ?
!stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 ||
IF_IF_stage1_rg_stage_input_32_BITS_151_TO_145_ETC___d1657 ||
!stageF_rg_full ||
near_mem$imem_valid &&
near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d2119 :
!stage1_rg_full ;
assign IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2675 =
(IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2634 ||
!stageD_rg_full) &&
stageF_rg_full &&
near_mem$imem_valid &&
near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d2119 ;
assign IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2728 =
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2306 ?
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
IF_NOT_stage1_rg_full_31_76_OR_NOT_stage1_rg_s_ETC___d2347 :
stage1_rg_full ;
assign IF_NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem__ETC___d2089 =
NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d2086 ?
{ 16'b0,
imem_rg_pc_BITS_63_TO_2_4_EQ_near_mem_imem_pc__ETC___d17 ?
near_mem$imem_instr[31:16] :
imem_rg_cache_b16 } :
near_mem$imem_instr ;
assign IF_NOT_stage1_rg_full_31_76_OR_NOT_stage1_rg_s_ETC___d2347 =
!IF_IF_stage1_rg_stage_input_32_BITS_151_TO_145_ETC___d1657 &&
stageF_rg_full &&
(!near_mem$imem_valid ||
NOT_near_mem_imem_exc__1_2_AND_imem_rg_pc_BITS_ETC___d2112) ;
assign IF_NOT_stage1_rg_full_31_76_OR_NOT_stage1_rg_s_ETC___d2405 =
IF_IF_stage1_rg_stage_input_32_BITS_151_TO_145_ETC___d1657 ||
!stageF_rg_full ||
near_mem$imem_valid &&
near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d2119 ;
assign IF_NOT_stage1_rg_full_31_76_OR_NOT_stage1_rg_s_ETC___d2589 =
IF_NOT_stage1_rg_full_31_76_OR_NOT_stage1_rg_s_ETC___d2405 &&
NOT_stage1_rg_stage_input_32_BITS_151_TO_145_7_ETC___d449 &&
stage1_rg_stage_input[151:145] != 7'b1100011 &&
stage1_rg_stage_input[151:145] != 7'b1101111 &&
stage1_rg_stage_input[151:145] != 7'b1100111 &&
stage1_rg_stage_input[151:145] != 7'b0010011 &&
stage1_rg_stage_input[151:145] != 7'b0110011 &&
stage1_rg_stage_input[151:145] != 7'b0011011 &&
stage1_rg_stage_input[151:145] != 7'b0111011 &&
stage1_rg_stage_input[151:145] != 7'b0110111 &&
stage1_rg_stage_input[151:145] != 7'b0010111 &&
stage1_rg_stage_input[151:145] != 7'b0000011 &&
stage1_rg_stage_input[151:145] != 7'b0100011 &&
stage1_rg_stage_input[151:145] != 7'b0101111 &&
stage1_rg_stage_input[151:145] != 7'b0000111 &&
stage1_rg_stage_input[151:145] != 7'b0100111 ;
assign IF_NOT_stage2_rg_full_14_71_OR_stage2_rg_stage_ETC___d343 =
x_out_fbypass_rd__h9453 == stage1_rg_stage_input[139:135] ;
assign IF_NOT_stage2_rg_full_14_71_OR_stage2_rg_stage_ETC___d344 =
x_out_fbypass_rd__h9453 == stage1_rg_stage_input[134:130] ;
assign IF_NOT_stage2_rg_full_14_71_OR_stage2_rg_stage_ETC___d347 =
x_out_fbypass_rd__h9453 == stage1_rg_stage_input[129:125] ;
assign IF_csr_regfile_read_csr_rg_trap_instr_798_BITS_ETC___d2856 =
csr_regfile$read_csr[63:0] | rs1_val__h35329 ;
assign IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1930 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b0 &&
stageD_rg_data[79:77] == 3'b001) ?
instr__h24785 :
((csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b0 &&
stageD_rg_data[79:77] == 3'b101) ?
instr__h24936 :
32'h0) ;
assign IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1931 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b10 &&
stageD_rg_data[79:77] == 3'b101) ?
instr__h24586 :
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1930 ;
assign IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1932 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b10 &&
stageD_rg_data[79:77] == 3'b001 &&
csr_regfile$read_misa[3]) ?
instr__h24421 :
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1931 ;
assign IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1933 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b10 &&
stageD_rg_data[79:77] == 3'b011 &&
csr_regfile$read_misa[5]) ?
instr__h23621 :
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1932 ;
assign IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1934 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b0 &&
stageD_rg_data[79:77] == 3'b111) ?
instr__h23416 :
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1933 ;
assign IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1935 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b0 &&
stageD_rg_data[79:77] == 3'b011) ?
instr__h23265 :
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1934 ;
assign IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1936 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b10 &&
stageD_rg_data[79:77] == 3'b111) ?
instr__h23066 :
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1935 ;
assign IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1938 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b10 &&
stageD_rg_data[79:76] == 4'b1001 &&
stageD_rg_data[75:71] == 5'd0 &&
stageD_rg_data[70:66] == 5'd0) ?
instr__h22817 :
((csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b10 &&
stageD_rg_data[75:71] != 5'd0 &&
stageD_rg_data[79:77] == 3'b011) ?
instr__h22913 :
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1936) ;
assign IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1940 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
stageD_rg_data[79:74] == 6'b100111 &&
stageD_rg_data[70:69] == 2'b01) ?
instr__h22521 :
((csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
stageD_rg_data[79:74] == 6'b100111 &&
stageD_rg_data[70:69] == 2'b0) ?
instr__h22659 :
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1938) ;
assign IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1942 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
stageD_rg_data[79:74] == 6'b100011 &&
stageD_rg_data[70:69] == 2'b01) ?
instr__h22247 :
((csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
stageD_rg_data[79:74] == 6'b100011 &&
stageD_rg_data[70:69] == 2'b0) ?
instr__h22383 :
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1940) ;
assign IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1944 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
stageD_rg_data[79:74] == 6'b100011 &&
stageD_rg_data[70:69] == 2'b11) ?
instr__h21975 :
((csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
stageD_rg_data[79:74] == 6'b100011 &&
stageD_rg_data[70:69] == 2'b10) ?
instr__h22111 :
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1942) ;
assign IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1945 =
(csr_regfile_read_misa__6_BIT_2_672_AND_stageD__ETC___d1753 &&
stageD_rg_data[70:66] != 5'd0) ?
instr__h21880 :
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1944 ;
assign IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1946 =
(csr_regfile_read_misa__6_BIT_2_672_AND_stageD__ETC___d1747 &&
stageD_rg_data[70:66] != 5'd0) ?
instr__h21761 :
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1945 ;
assign IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1948 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
stageD_rg_data[79:77] == 3'b100 &&
stageD_rg_data[75:74] == 2'b01 &&
imm6__h19874 != 6'd0) ?
instr__h21466 :
((csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
stageD_rg_data[79:77] == 3'b100 &&
stageD_rg_data[75:74] == 2'b10) ?
instr__h21583 :
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1946) ;
assign IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1949 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
stageD_rg_data[79:77] == 3'b100 &&
stageD_rg_data[75:74] == 2'b0 &&
imm6__h19874 != 6'd0) ?
instr__h21277 :
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1948 ;
assign IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1950 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b10 &&
stageD_rg_data[79:77] == 3'b0 &&
stageD_rg_data[75:71] != 5'd0 &&
imm6__h19874 != 6'd0) ?
instr__h21088 :
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1949 ;
assign IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1952 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
stageD_rg_data[79:77] == 3'b011 &&
stageD_rg_data[75:71] == 5'd2 &&
nzimm10__h20543 != 10'd0) ?
instr__h20747 :
((csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b0 &&
stageD_rg_data[79:77] == 3'b0 &&
nzimm10__h20758 != 10'd0) ?
instr__h20919 :
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1950) ;
assign IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1954 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
stageD_rg_data[79:77] == 3'b0 &&
stageD_rg_data[75:71] != 5'd0 &&
imm6__h19874 != 6'd0 ||
csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
stageD_rg_data[79:77] == 3'b0 &&
stageD_rg_data[75:71] == 5'd0 &&
imm6__h19874 == 6'd0) ?
instr__h20265 :
((csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
stageD_rg_data[79:77] == 3'b001 &&
stageD_rg_data[75:71] != 5'd0) ?
instr__h20492 :
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1952) ;
assign IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1955 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
stageD_rg_data[79:77] == 3'b011 &&
stageD_rg_data[75:71] != 5'd0 &&
stageD_rg_data[75:71] != 5'd2 &&
imm6__h19874 != 6'd0) ?
instr__h20136 :
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1954 ;
assign IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1957 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
stageD_rg_data[79:77] == 3'b111) ?
instr__h19614 :
((csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
stageD_rg_data[79:77] == 3'b010 &&
stageD_rg_data[75:71] != 5'd0) ?
instr__h19952 :
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1955) ;
assign IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1958 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
stageD_rg_data[79:77] == 3'b110) ?
instr__h19297 :
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1957 ;
assign IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1959 =
(csr_regfile_read_misa__6_BIT_2_672_AND_stageD__ETC___d1753 &&
stageD_rg_data[70:66] == 5'd0) ?
instr__h19232 :
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1958 ;
assign IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1960 =
(csr_regfile_read_misa__6_BIT_2_672_AND_stageD__ETC___d1747 &&
stageD_rg_data[70:66] == 5'd0) ?
instr__h19116 :
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1959 ;
assign IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1961 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
stageD_rg_data[79:77] == 3'b101) ?
instr__h18663 :
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1960 ;
assign IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1962 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b0 &&
stageD_rg_data[79:77] == 3'b110) ?
instr__h18434 :
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1961 ;
assign IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1963 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b0 &&
stageD_rg_data[79:77] == 3'b010) ?
instr__h18239 :
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1962 ;
assign IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1964 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b10 &&
stageD_rg_data[79:77] == 3'b110) ?
instr__h18047 :
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1963 ;
assign IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg_p_ETC___d2090 =
(imem_rg_pc[1:0] == 2'b0 &&
imem_rg_pc_BITS_63_TO_2_4_EQ_near_mem_imem_pc__ETC___d17 &&
near_mem$imem_instr[1:0] != 2'b11) ?
instr_out___1__h25384 :
IF_NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem__ETC___d2089 ;
assign IF_stage1_rg_full_31_THEN_stage1_rg_stage_inpu_ETC___d2897 =
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
(NOT_stage1_rg_stage_input_32_BIT_332_77_83_AND_ETC___d2884 ||
!stage1_rg_stage_input[332] &&
stage1_rg_stage_input_32_BITS_151_TO_145_78_EQ_ETC___d2892) ;
assign IF_stage1_rg_stage_input_32_BITS_112_TO_110_80_ETC___d2764 =
(stage1_rg_stage_input[112:110] == 3'd0) ?
NOT_stage1_rg_stage_input_32_BITS_144_TO_140_0_ETC___d1169 &&
(stage1_rg_stage_input[144:140] != 5'd0 ||
stage1_rg_stage_input[139:135] != 5'd0 ||
stage1_rg_stage_input[87:76] == 12'b0 ||
stage1_rg_stage_input[87:76] == 12'b000000000001 ||
(rg_cur_priv != 2'b11 ||
stage1_rg_stage_input[87:76] != 12'b001100000010) &&
NOT_rg_cur_priv_8_EQ_0b11_059_091_AND_NOT_rg_c_ETC___d2758) :
stage1_rg_stage_input[112:110] != 3'b001 &&
stage1_rg_stage_input[112:110] != 3'b101 &&
stage1_rg_stage_input[112:110] != 3'b010 &&
stage1_rg_stage_input[112:110] != 3'b110 &&
stage1_rg_stage_input[112:110] != 3'b011 &&
stage1_rg_stage_input[112:110] != 3'b111 ;
assign IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d1260 =
rs1_val_bypassed__h5597 +
SEXT_stage1_rg_stage_input_32_BITS_87_TO_76_047___d1259 ;
assign IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d421 =
rs1_val_bypassed__h5597 == rs2_val_bypassed__h5603 ;
assign IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d423 =
(rs1_val_bypassed__h5597 ^ 64'h8000000000000000) <
(rs2_val_bypassed__h5603 ^ 64'h8000000000000000) ;
assign IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d425 =
rs1_val_bypassed__h5597 < rs2_val_bypassed__h5603 ;
assign IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC__q18 =
IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d1260[31:0] ;
assign IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d1521 =
((stage1_rg_stage_input[151:145] == 7'b0010011 ||
stage1_rg_stage_input[151:145] == 7'b0110011) &&
(stage1_rg_stage_input[112:110] == 3'b001 ||
stage1_rg_stage_input[112:110] == 3'b101)) ?
alu_outputs___1_val1__h10496 :
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d1520 ;
assign IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d1522 =
(stage1_rg_stage_input[151:145] == 7'b0110011 &&
stage1_rg_stage_input[104:98] == 7'b0000001 ||
stage1_rg_stage_input_32_BITS_151_TO_145_78_EQ_ETC___d794) ?
rs1_val_bypassed__h5597 :
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d1521 ;
assign IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d1531 =
(stage1_rg_stage_input[151:145] == 7'b0110011 &&
stage1_rg_stage_input[104:98] == 7'b0000001 ||
stage1_rg_stage_input_32_BITS_151_TO_145_78_EQ_ETC___d794) ?
rs2_val_bypassed__h5603 :
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q19 ;
assign IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d763 =
(stage1_rg_stage_input[151:145] == 7'b1100011) ?
stage1_rg_stage_input[112:110] != 3'd0 &&
stage1_rg_stage_input[112:110] != 3'b001 &&
stage1_rg_stage_input[112:110] != 3'b100 &&
stage1_rg_stage_input[112:110] != 3'b101 &&
stage1_rg_stage_input[112:110] != 3'b110 &&
stage1_rg_stage_input[112:110] != 3'b111 ||
IF_stage1_rg_stage_input_32_BITS_112_TO_110_80_ETC___d432 :
stage1_rg_stage_input[151:145] == 7'b1101111 ||
stage1_rg_stage_input[151:145] == 7'b1100111 ||
NOT_stage1_rg_stage_input_32_BITS_151_TO_145_7_ETC___d760 ;
assign IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d775 =
(stage1_rg_stage_input[151:145] == 7'b1100011) ?
stage1_rg_stage_input[112:110] != 3'd0 &&
stage1_rg_stage_input[112:110] != 3'b001 &&
stage1_rg_stage_input[112:110] != 3'b100 &&
stage1_rg_stage_input[112:110] != 3'b101 &&
stage1_rg_stage_input[112:110] != 3'b110 &&
stage1_rg_stage_input[112:110] != 3'b111 ||
IF_stage1_rg_stage_input_32_BITS_112_TO_110_80_ETC___d769 :
stage1_rg_stage_input[151:145] != 7'b1101111 &&
(stage1_rg_stage_input[151:145] != 7'b1100111 ||
stage1_rg_stage_input[112:110] != 3'd0) ;
assign IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d965 =
(stage1_rg_stage_input[151:145] == 7'b1100011) ?
(stage1_rg_stage_input[112:110] == 3'd0 ||
stage1_rg_stage_input[112:110] == 3'b001 ||
stage1_rg_stage_input[112:110] == 3'b100 ||
stage1_rg_stage_input[112:110] == 3'b101 ||
stage1_rg_stage_input[112:110] == 3'b110 ||
stage1_rg_stage_input[112:110] == 3'b111) &&
IF_stage1_rg_stage_input_32_BITS_112_TO_110_80_ETC___d769 :
stage1_rg_stage_input[151:145] != 7'b1101111 &&
stage1_rg_stage_input[151:145] != 7'b1100111 &&
stage1_rg_stage_input_32_BITS_151_TO_145_78_EQ_ETC___d962 ;
assign IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d969 =
(stage1_rg_stage_input[151:145] == 7'b1100011) ?
(stage1_rg_stage_input[112:110] == 3'd0 ||
stage1_rg_stage_input[112:110] == 3'b001 ||
stage1_rg_stage_input[112:110] == 3'b100 ||
stage1_rg_stage_input[112:110] == 3'b101 ||
stage1_rg_stage_input[112:110] == 3'b110 ||
stage1_rg_stage_input[112:110] == 3'b111) &&
IF_stage1_rg_stage_input_32_BITS_112_TO_110_80_ETC___d432 :
stage1_rg_stage_input[151:145] == 7'b1101111 ||
stage1_rg_stage_input[151:145] == 7'b1100111 &&
stage1_rg_stage_input[112:110] == 3'd0 ;
assign IF_stage1_rg_stage_input_32_BITS_335_TO_334_33_ETC___d2511 =
{ stage1_rg_stage_input[263:232],
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q22,
data_to_stage2_rd__h10102,
data_to_stage2_addr__h10103,
x_out_data_to_stage2_val1__h10121,
data_to_stage2_val2__h10105,
alu_outputs___1_fval1__h11709,
alu_outputs___1_fval2__h10701,
alu_outputs___1_fval3__h11711,
stage1_rg_stage_input[151:145] != 7'b1100011 &&
stage1_rg_stage_input[151:145] != 7'b1101111 &&
stage1_rg_stage_input[151:145] != 7'b1100111 &&
stage1_rg_stage_input[151:145] != 7'b0010011 &&
stage1_rg_stage_input[151:145] != 7'b0110011 &&
stage1_rg_stage_input[151:145] != 7'b0011011 &&
stage1_rg_stage_input[151:145] != 7'b0111011 &&
stage1_rg_stage_input[151:145] != 7'b0110111 &&
stage1_rg_stage_input[151:145] != 7'b0010111 &&
stage1_rg_stage_input[151:145] != 7'b0000011 &&
stage1_rg_stage_input[151:145] != 7'b0100011 &&
stage1_rg_stage_input[151:145] != 7'b0001111 &&
stage1_rg_stage_input[151:145] != 7'b1110011 &&
stage1_rg_stage_input[151:145] != 7'b0101111 &&
(stage1_rg_stage_input[151:145] == 7'b0000111 ||
stage1_rg_stage_input[151:145] != 7'b0100111 &&
NOT_csr_regfile_read_mstatus__9_BITS_14_TO_13__ETC___d2461),
stage1_rg_stage_input[151:145] == 7'b0100111,
NOT_csr_regfile_read_mstatus__9_BITS_14_TO_13__ETC___d2505,
rm__h10284 } ;
assign IF_stage2_rg_full_14_THEN_IF_stage2_rg_stage2__ETC___d337 =
x_out_bypass_rd__h9271 == stage1_rg_stage_input[139:135] ;
assign IF_stage2_rg_full_14_THEN_IF_stage2_rg_stage2__ETC___d339 =
x_out_bypass_rd__h9271 == stage1_rg_stage_input[134:130] ;
assign NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56 =
cur_verbosity__h3946 > 4'd1 ;
assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2298 =
!csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending ||
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d2295 ||
!stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334) &&
(!stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d972) ;
assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2306 =
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2298 &&
(stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d2299 ||
!stage2_rg_full) &&
stage1_rg_full &&
(!stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 ||
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d2303) ;
assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2315 =
(!csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d2295) &&
(stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d2299 ||
!stage2_rg_full) ;
assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2319 =
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2315 &&
stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d2303 &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
!IF_IF_stage1_rg_stage_input_32_BITS_151_TO_145_ETC___d1657 ;
assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2342 =
!csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending ||
(!stage1_rg_full || stage1_rg_stage_input[332] ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d763 &&
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d775 ||
!stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334) &&
(!stage1_rg_full ||
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d2334) ;
assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2346 =
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2342 ||
(!stage1_rg_full ||
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d2343) &&
(!stage1_rg_full ||
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d2334) ;
assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2401 =
(!csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d2295 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d972) &&
(stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d2299 ||
!stage2_rg_full) ;
assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2407 =
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2401 &&
stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d2303 &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
IF_NOT_stage1_rg_full_31_76_OR_NOT_stage1_rg_s_ETC___d2405 ;
assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2541 =
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2401 &&
stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d2303 &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
IF_NOT_stage1_rg_full_31_76_OR_NOT_stage1_rg_s_ETC___d2405 &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
(stage1_rg_stage_input[151:145] == 7'b0000011 ||
stage1_rg_stage_input[151:145] == 7'b0000111 ||
stage1_rg_stage_input[151:145] == 7'b0100011 ||
stage1_rg_stage_input[151:145] == 7'b0100111 ||
stage1_rg_stage_input[151:145] == 7'b0101111) ;
assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2575 =
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2401 &&
stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d2303 &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
IF_NOT_stage1_rg_full_31_76_OR_NOT_stage1_rg_s_ETC___d2405 &&
stage1_rg_stage_input[151:145] != 7'b0000011 &&
stage1_rg_stage_input[151:145] != 7'b0000111 &&
stage1_rg_stage_input[151:145] != 7'b0100011 &&
stage1_rg_stage_input[151:145] != 7'b0100111 &&
stage1_rg_stage_input[151:145] != 7'b0101111 &&
stage1_rg_stage_input[151:145] != 7'b1100011 &&
stage1_rg_stage_input[151:145] != 7'b1101111 &&
stage1_rg_stage_input[151:145] != 7'b1100111 &&
(stage1_rg_stage_input[151:145] == 7'b0110011 &&
stage1_rg_stage_input[104:98] == 7'b0000001 ||
stage1_rg_stage_input_32_BITS_151_TO_145_78_EQ_ETC___d794) ;
assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2591 =
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2401 &&
stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d2303 &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
IF_NOT_stage1_rg_full_31_76_OR_NOT_stage1_rg_s_ETC___d2589 ;
assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2601 =
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2401 &&
stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d2303 &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
IF_NOT_stage1_rg_full_31_76_OR_NOT_stage1_rg_s_ETC___d2405 &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56 ;
assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2605 =
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2401 &&
stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d2303 &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
IF_NOT_stage1_rg_full_31_76_OR_NOT_stage1_rg_s_ETC___d2405 &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d1297 ;
assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2609 =
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2401 &&
stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d2303 &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
IF_NOT_stage1_rg_full_31_76_OR_NOT_stage1_rg_s_ETC___d2405 &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d985 &&
(stage1_rg_stage_input[151:145] == 7'b0000011 ||
stage1_rg_stage_input[151:145] == 7'b0000111) ;
assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2613 =
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2401 &&
stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d2303 &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
IF_NOT_stage1_rg_full_31_76_OR_NOT_stage1_rg_s_ETC___d2405 &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1332 ;
assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2618 =
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2401 &&
stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d2303 &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
IF_NOT_stage1_rg_full_31_76_OR_NOT_stage1_rg_s_ETC___d2405 &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d2614 ;
assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2622 =
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2401 &&
stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d2303 &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
IF_NOT_stage1_rg_full_31_76_OR_NOT_stage1_rg_s_ETC___d2405 &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d985 &&
stage1_rg_stage_input[151:145] == 7'b0101111 ;
assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2630 =
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2401 &&
stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d2303 &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
IF_NOT_stage1_rg_full_31_76_OR_NOT_stage1_rg_s_ETC___d2405 &&
!IF_IF_stage1_rg_stage_input_32_BITS_151_TO_145_ETC___d1657 ;
assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2750 =
!csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending ||
!stage1_rg_stage_input[332] &&
(IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d965 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d969) ;
assign NOT_csr_regfile_read_mstatus__9_BITS_14_TO_13__ETC___d2461 =
NOT_csr_regfile_read_mstatus__9_BITS_14_TO_13__ETC___d851 &&
(stage1_rg_stage_input_32_BITS_99_TO_98_74_EQ_0_ETC___d2440 ||
stage1_rg_stage_input[104:98] == 7'h69 &&
(stage1_rg_stage_input[134:130] == 5'b00010 ||
stage1_rg_stage_input[134:130] == 5'b00011) ||
stage1_rg_stage_input[104:98] == 7'h79 &&
stage1_rg_stage_input[134:130] == 5'd0 &&
rm__h10284 == 3'b0) &&
(stage1_rg_stage_input[104:98] != 7'h61 ||
stage1_rg_stage_input[134:130] != 5'd0) &&
(stage1_rg_stage_input[104:98] != 7'h61 ||
stage1_rg_stage_input[134:130] != 5'b00001) &&
(stage1_rg_stage_input[104:98] != 7'h61 ||
stage1_rg_stage_input[134:130] != 5'b00010) &&
(stage1_rg_stage_input[104:98] != 7'h61 ||
stage1_rg_stage_input[134:130] != 5'b00011) &&
stage1_rg_stage_input[104:98] != 7'h71 &&
stage1_rg_stage_input[104:98] != 7'h51 &&
(stage1_rg_stage_input[104:98] != 7'h60 ||
stage1_rg_stage_input[134:130] != 5'b00010) &&
(stage1_rg_stage_input[104:98] != 7'h60 ||
stage1_rg_stage_input[134:130] != 5'b00011) &&
(stage1_rg_stage_input[104:98] != 7'h60 ||
stage1_rg_stage_input[134:130] != 5'd0) &&
(stage1_rg_stage_input[104:98] != 7'h60 ||
stage1_rg_stage_input[134:130] != 5'b00001) &&
stage1_rg_stage_input[104:98] != 7'h70 &&
stage1_rg_stage_input[104:98] != 7'h50 ;
assign NOT_csr_regfile_read_mstatus__9_BITS_14_TO_13__ETC___d2505 =
NOT_csr_regfile_read_mstatus__9_BITS_14_TO_13__ETC___d851 &&
(_0_OR_stage1_rg_stage_input_32_BITS_104_TO_98_3_ETC___d2484 ||
stage1_rg_stage_input[104:98] == 7'h61 &&
(stage1_rg_stage_input[134:130] == 5'b00010 ||
stage1_rg_stage_input[134:130] == 5'b00011) ||
stage1_rg_stage_input[104:98] == 7'h71 &&
stage1_rg_stage_input[134:130] == 5'd0 &&
rm__h10284 == 3'b0 ||
stage1_rg_stage_input[104:98] == 7'h69 &&
stage1_rg_stage_input[134:130] == 5'b00010 ||
stage1_rg_stage_input[104:98] == 7'h69 &&
stage1_rg_stage_input[134:130] == 5'b00011 ||
stage1_rg_stage_input[104:98] == 7'h79 &&
stage1_rg_stage_input[134:130] == 5'd0 &&
rm__h10284 == 3'b0) &&
stage1_rg_stage_input[151:145] == 7'b1010011 &&
(stage1_rg_stage_input[104:98] == 7'h69 &&
(stage1_rg_stage_input[134:130] == 5'd0 ||
stage1_rg_stage_input[134:130] == 5'b00001 ||
stage1_rg_stage_input[134:130] == 5'b00010 ||
stage1_rg_stage_input[134:130] == 5'b00011) ||
stage1_rg_stage_input[104:98] == 7'h79 ||
stage1_rg_stage_input[104:98] == 7'h68 &&
(stage1_rg_stage_input[134:130] == 5'd0 ||
stage1_rg_stage_input[134:130] == 5'b00001 ||
stage1_rg_stage_input[134:130] == 5'b00010 ||
stage1_rg_stage_input[134:130] == 5'b00011) ||
stage1_rg_stage_input[104:98] == 7'h78) ;
assign NOT_csr_regfile_read_mstatus__9_BITS_14_TO_13__ETC___d851 =
csr_regfile$read_mstatus[14:13] != 2'h0 &&
((stage1_rg_stage_input[112:110] == 3'b111) ?
csr_regfile$read_frm != 3'b101 &&
csr_regfile$read_frm != 3'b110 &&
csr_regfile$read_frm != 3'b111 :
stage1_rg_stage_input[112:110] != 3'b101 &&
stage1_rg_stage_input[112:110] != 3'b110) ;
assign NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d2072 =
imem_rg_pc[1:0] != 2'b0 &&
imem_rg_pc_BITS_63_TO_2_4_EQ_imem_rg_cache_add_ETC___d2064 &&
near_mem_imem_pc__5_EQ_imem_rg_pc_PLUS_2_066___d2067 &&
imem_rg_cache_b16[1:0] == 2'b11 ;
assign NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d2086 =
imem_rg_pc[1:0] != 2'b0 &&
(imem_rg_pc_BITS_63_TO_2_4_EQ_near_mem_imem_pc__ETC___d17 &&
near_mem$imem_instr[17:16] != 2'b11 ||
imem_rg_pc_BITS_63_TO_2_4_EQ_imem_rg_cache_add_ETC___d2064 &&
imem_rg_cache_b16[1:0] != 2'b11) ;
assign NOT_near_mem_imem_exc__1_2_AND_imem_rg_pc_BITS_ETC___d2105 =
!near_mem$imem_exc &&
(imem_rg_pc[1:0] == 2'b0 ||
!imem_rg_pc_BITS_63_TO_2_4_EQ_imem_rg_cache_add_ETC___d2064 ||
!near_mem_imem_pc__5_EQ_imem_rg_pc_PLUS_2_066___d2067 ||
imem_rg_cache_b16[1:0] != 2'b11) &&
(imem_rg_pc[1:0] != 2'b0 ||
!imem_rg_pc_BITS_63_TO_2_4_EQ_near_mem_imem_pc__ETC___d17 ||
near_mem$imem_instr[1:0] != 2'b11) ;
assign NOT_near_mem_imem_exc__1_2_AND_imem_rg_pc_BITS_ETC___d2112 =
NOT_near_mem_imem_exc__1_2_AND_imem_rg_pc_BITS_ETC___d2105 &&
imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d2109 &&
(imem_rg_pc[1:0] != 2'b0 ||
!imem_rg_pc_BITS_63_TO_2_4_EQ_near_mem_imem_pc__ETC___d17 ||
near_mem$imem_instr[1:0] == 2'b11) ;
assign NOT_rg_cur_priv_8_EQ_0b11_059_091_AND_NOT_rg_c_ETC___d1104 =
(rg_cur_priv != 2'b11 &&
(rg_cur_priv != 2'b01 || csr_regfile$read_mstatus[20]) ||
stage1_rg_stage_input[104:98] != 7'b0001001) &&
stage1_rg_stage_input_32_BITS_144_TO_140_027_E_ETC___d1103 ;
assign NOT_rg_cur_priv_8_EQ_0b11_059_091_AND_NOT_rg_c_ETC___d1126 =
(rg_cur_priv != 2'b11 &&
(rg_cur_priv != 2'b01 || csr_regfile$read_mstatus[20]) ||
stage1_rg_stage_input[104:98] != 7'b0001001) &&
stage1_rg_stage_input[144:140] == 5'd0 &&
stage1_rg_stage_input[139:135] == 5'd0 &&
rg_cur_priv_8_EQ_0b11_059_OR_rg_cur_priv_8_EQ__ETC___d1124 ;
assign NOT_rg_cur_priv_8_EQ_0b11_059_091_AND_NOT_rg_c_ETC___d1201 =
rg_cur_priv != 2'b11 &&
(rg_cur_priv != 2'b01 || csr_regfile$read_mstatus[21]) &&
(rg_cur_priv != 2'b0 || !csr_regfile$read_misa[13]) ||
stage1_rg_stage_input[87:76] != 12'b000100000101 ;
assign NOT_rg_cur_priv_8_EQ_0b11_059_091_AND_NOT_rg_c_ETC___d1645 =
(rg_cur_priv != 2'b11 &&
(rg_cur_priv != 2'b01 || csr_regfile$read_mstatus[20]) ||
stage1_rg_stage_input[104:98] != 7'b0001001) &&
stage1_rg_stage_input[144:140] == 5'd0 &&
stage1_rg_stage_input[139:135] == 5'd0 &&
stage1_rg_stage_input[87:76] == 12'b000000000001 ;
assign NOT_rg_cur_priv_8_EQ_0b11_059_091_AND_NOT_rg_c_ETC___d2758 =
(rg_cur_priv != 2'b11 &&
(rg_cur_priv != 2'b01 || csr_regfile$read_mstatus[22]) ||
stage1_rg_stage_input[87:76] != 12'b000100000010) &&
NOT_rg_cur_priv_8_EQ_0b11_059_091_AND_NOT_rg_c_ETC___d1201 ;
assign NOT_rg_next_pc_867_BITS_1_TO_0_868_EQ_0b0_869__ETC___d2875 =
rg_next_pc[1:0] != 2'b0 && near_mem$imem_valid &&
!near_mem$imem_exc &&
addr_of_b32__h43884 == near_mem$imem_pc ;
assign NOT_rg_run_on_reset_247_248_OR_imem_rg_pc_BITS_ETC___d2255 =
!rg_run_on_reset ||
(imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_near_mem__ETC___d2251 ||
near_mem$imem_instr[17:16] != 2'b11) &&
stageF_branch_predictor$RDY_predict_req ;
assign NOT_soc_map_m_pc_reset_value__268_BITS_1_TO_0__ETC___d2284 =
soc_map$m_pc_reset_value[1:0] != 2'b0 && near_mem$imem_valid &&
!near_mem$imem_exc &&
addr_of_b32__h27393 == near_mem$imem_pc ;
assign NOT_stage1_rg_stage_input_32_BITS_104_TO_98_38_ETC___d746 =
(stage1_rg_stage_input[104:98] != 7'h61 ||
stage1_rg_stage_input[134:130] != 5'b00010 &&
stage1_rg_stage_input[134:130] != 5'b00011) &&
(stage1_rg_stage_input[104:98] != 7'h71 ||
stage1_rg_stage_input[134:130] != 5'd0 ||
rm__h10284 != 3'b0) &&
(stage1_rg_stage_input[104:98] != 7'h69 ||
stage1_rg_stage_input[134:130] != 5'b00010) &&
(stage1_rg_stage_input[104:98] != 7'h69 ||
stage1_rg_stage_input[134:130] != 5'b00011) &&
(stage1_rg_stage_input[104:98] != 7'h79 ||
stage1_rg_stage_input[134:130] != 5'd0 ||
rm__h10284 != 3'b0) ;
assign NOT_stage1_rg_stage_input_32_BITS_109_TO_105_2_ETC___d559 =
(stage1_rg_stage_input[109:105] != 5'b00010 ||
stage1_rg_stage_input[134:130] != 5'd0) &&
stage1_rg_stage_input[109:105] != 5'b00011 &&
stage1_rg_stage_input[109:105] != 5'b0 &&
stage1_rg_stage_input[109:105] != 5'b00001 &&
stage1_rg_stage_input[109:105] != 5'b01100 &&
stage1_rg_stage_input[109:105] != 5'b01000 &&
stage1_rg_stage_input[109:105] != 5'b00100 &&
stage1_rg_stage_input[109:105] != 5'b10000 &&
stage1_rg_stage_input[109:105] != 5'b11000 &&
stage1_rg_stage_input[109:105] != 5'b10100 &&
stage1_rg_stage_input[109:105] != 5'b11100 ||
stage1_rg_stage_input[112:110] != 3'b010 &&
stage1_rg_stage_input[112:110] != 3'b011 ;
assign NOT_stage1_rg_stage_input_32_BITS_112_TO_110_8_ETC___d1157 =
stage1_rg_stage_input[112:110] != 3'd0 ||
stage1_rg_stage_input[144:140] != 5'd0 ||
stage1_rg_stage_input[139:135] != 5'd0 ||
stage1_rg_stage_input[263:260] != 4'b0 &&
stage1_rg_stage_input[263:260] != 4'b1000 ;
assign NOT_stage1_rg_stage_input_32_BITS_112_TO_110_8_ETC___d1164 =
stage1_rg_stage_input[112:110] != 3'b001 ||
stage1_rg_stage_input[144:140] != 5'd0 ||
stage1_rg_stage_input[139:135] != 5'd0 ||
stage1_rg_stage_input[87:76] != 12'b0 ;
assign NOT_stage1_rg_stage_input_32_BITS_112_TO_110_8_ETC___d479 =
(stage1_rg_stage_input[112:110] != 3'd0 ||
stage1_rg_stage_input[151:145] == 7'b0110011 &&
stage1_rg_stage_input[262]) &&
(stage1_rg_stage_input[112:110] != 3'd0 ||
stage1_rg_stage_input[151:145] != 7'b0110011 ||
!stage1_rg_stage_input[262]) &&
CASE_stage1_rg_stage_input_BITS_112_TO_110_0b1_ETC__q11 ;
assign NOT_stage1_rg_stage_input_32_BITS_144_TO_140_0_ETC___d1169 =
stage1_rg_stage_input[144:140] != 5'd0 ||
rg_cur_priv != 2'b11 &&
(rg_cur_priv != 2'b01 || csr_regfile$read_mstatus[20]) ||
stage1_rg_stage_input[104:98] != 7'b0001001 ;
assign NOT_stage1_rg_stage_input_32_BITS_151_TO_145_7_ETC___d2774 =
(stage1_rg_stage_input[151:145] != 7'b0110011 ||
stage1_rg_stage_input[104:98] != 7'b0000001) &&
NOT_stage1_rg_stage_input_32_BITS_151_TO_145_7_ETC___d449 &&
(((stage1_rg_stage_input[151:145] == 7'b0010011 ||
stage1_rg_stage_input[151:145] == 7'b0110011) &&
(stage1_rg_stage_input[112:110] == 3'b001 ||
stage1_rg_stage_input[112:110] == 3'b101)) ?
stage1_rg_stage_input[263] ||
stage1_rg_stage_input[261:258] != 4'b0 :
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d2772) ;
assign NOT_stage1_rg_stage_input_32_BITS_151_TO_145_7_ETC___d449 =
stage1_rg_stage_input[151:145] != 7'b0111011 ||
stage1_rg_stage_input[104:98] != 7'b0000001 ||
stage1_rg_stage_input[112:110] == 3'b001 ||
stage1_rg_stage_input[112:110] == 3'b010 ||
stage1_rg_stage_input[112:110] == 3'b011 ;
assign NOT_stage1_rg_stage_input_32_BITS_151_TO_145_7_ETC___d760 =
(stage1_rg_stage_input[151:145] != 7'b0110011 ||
stage1_rg_stage_input[104:98] != 7'b0000001) &&
NOT_stage1_rg_stage_input_32_BITS_151_TO_145_7_ETC___d449 &&
(((stage1_rg_stage_input[151:145] == 7'b0010011 ||
stage1_rg_stage_input[151:145] == 7'b0110011) &&
(stage1_rg_stage_input[112:110] == 3'b001 ||
stage1_rg_stage_input[112:110] == 3'b101)) ?
stage1_rg_stage_input[263] ||
stage1_rg_stage_input[261:258] != 4'b0 :
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d758) ;
assign NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1230 =
(!stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 ||
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375) &&
(!stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d972) &&
stage1_rg_stage_input[151:145] != 7'b1100011 &&
stage1_rg_stage_input[151:145] != 7'b1101111 &&
stage1_rg_stage_input[151:145] != 7'b1100111 ;
assign NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1238 =
(!stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 ||
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375) &&
(!stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d972) &&
stage1_rg_stage_input[151:145] == 7'b1100011 ;
assign NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1243 =
(!stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 ||
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375) &&
(!stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d972) &&
(stage1_rg_stage_input[151:145] == 7'b1101111 ||
stage1_rg_stage_input[151:145] == 7'b1100111) ;
assign NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1249 =
(!stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 ||
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375) &&
(!stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d972) &&
stage1_rg_stage_input[151:145] == 7'b1101111 ;
assign NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1300 =
(!stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 ||
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375) &&
(!stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d972) &&
(!stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 ||
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d1297) ;
assign NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1660 =
(!stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 ||
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375) &&
!IF_IF_stage1_rg_stage_input_32_BITS_151_TO_145_ETC___d1657 ;
assign NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1664 =
(!stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 ||
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375) &&
IF_IF_stage1_rg_stage_input_32_BITS_151_TO_145_ETC___d1657 ;
assign NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d2334 =
!stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 ||
!stage1_rg_stage_input[332] &&
(IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d965 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d969) ;
assign NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d2948 =
!stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d965 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d969 ||
stage1_rg_stage_input[332] ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d763 &&
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d775 ;
assign NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d2950 =
(NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d2334 &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 ||
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d2343) &&
stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d2948 ;
assign NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d974 =
(!stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 ||
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375) &&
(!stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d972) ;
assign NOT_stage1_rg_stage_input_32_BITS_99_TO_98_74__ETC___d734 =
(stage1_rg_stage_input[99:98] != 2'b0 &&
stage1_rg_stage_input[99:98] != 2'b01 ||
stage1_rg_stage_input[151:145] != 7'b1000011 &&
stage1_rg_stage_input[151:145] != 7'b1000111 &&
stage1_rg_stage_input[151:145] != 7'b1001111 &&
stage1_rg_stage_input[151:145] != 7'b1001011) &&
stage1_rg_stage_input[104:98] != 7'h0 &&
stage1_rg_stage_input[104:98] != 7'h04 &&
stage1_rg_stage_input[104:98] != 7'h08 &&
stage1_rg_stage_input[104:98] != 7'h0C &&
(stage1_rg_stage_input[104:98] != 7'h2C ||
stage1_rg_stage_input[134:130] != 5'd0) &&
(stage1_rg_stage_input[104:98] != 7'h10 || rm__h10284 != 3'b0) &&
(stage1_rg_stage_input[104:98] != 7'h10 ||
rm__h10284 != 3'b001) &&
(stage1_rg_stage_input[104:98] != 7'h10 ||
rm__h10284 != 3'b010) &&
(stage1_rg_stage_input[104:98] != 7'h14 || rm__h10284 != 3'b0) &&
(stage1_rg_stage_input[104:98] != 7'h14 ||
rm__h10284 != 3'b001) &&
(stage1_rg_stage_input[104:98] != 7'h60 ||
stage1_rg_stage_input[134:130] != 5'd0) &&
(stage1_rg_stage_input[104:98] != 7'h60 ||
stage1_rg_stage_input[134:130] != 5'b00001) &&
(stage1_rg_stage_input[104:98] != 7'h70 ||
stage1_rg_stage_input[134:130] != 5'd0 ||
rm__h10284 != 3'b0) &&
(stage1_rg_stage_input[104:98] != 7'h50 ||
rm__h10284 != 3'b010) &&
(stage1_rg_stage_input[104:98] != 7'h50 ||
rm__h10284 != 3'b001) &&
(stage1_rg_stage_input[104:98] != 7'h50 || rm__h10284 != 3'b0) &&
(stage1_rg_stage_input[104:98] != 7'h70 ||
stage1_rg_stage_input[134:130] != 5'd0 ||
rm__h10284 != 3'b001) &&
(stage1_rg_stage_input[104:98] != 7'h68 ||
stage1_rg_stage_input[134:130] != 5'd0) &&
(stage1_rg_stage_input[104:98] != 7'h68 ||
stage1_rg_stage_input[134:130] != 5'b00001) &&
(stage1_rg_stage_input[104:98] != 7'h78 ||
stage1_rg_stage_input[134:130] != 5'd0 ||
rm__h10284 != 3'b0) &&
(stage1_rg_stage_input[104:98] != 7'h60 ||
stage1_rg_stage_input[134:130] != 5'b00010 &&
stage1_rg_stage_input[134:130] != 5'b00011) &&
(stage1_rg_stage_input[104:98] != 7'h68 ||
stage1_rg_stage_input[134:130] != 5'b00010) &&
(stage1_rg_stage_input[104:98] != 7'h68 ||
stage1_rg_stage_input[134:130] != 5'b00011) &&
stage1_rg_stage_input[104:98] != 7'b0000001 &&
stage1_rg_stage_input[104:98] != 7'h05 &&
stage1_rg_stage_input[104:98] != 7'b0001001 &&
stage1_rg_stage_input[104:98] != 7'h0D &&
(stage1_rg_stage_input[104:98] != 7'h2D ||
stage1_rg_stage_input[134:130] != 5'd0) &&
(stage1_rg_stage_input[104:98] != 7'h11 || rm__h10284 != 3'b0) &&
(stage1_rg_stage_input[104:98] != 7'h11 ||
rm__h10284 != 3'b001) &&
(stage1_rg_stage_input[104:98] != 7'h11 ||
rm__h10284 != 3'b010) &&
(stage1_rg_stage_input[104:98] != 7'h15 || rm__h10284 != 3'b0) &&
(stage1_rg_stage_input[104:98] != 7'h15 ||
rm__h10284 != 3'b001) &&
(stage1_rg_stage_input[104:98] != 7'h20 ||
stage1_rg_stage_input[134:130] != 5'b00001) &&
(stage1_rg_stage_input[104:98] != 7'h21 ||
stage1_rg_stage_input[134:130] != 5'd0) &&
(stage1_rg_stage_input[104:98] != 7'h51 ||
rm__h10284 != 3'b010) &&
(stage1_rg_stage_input[104:98] != 7'h51 ||
rm__h10284 != 3'b001) &&
(stage1_rg_stage_input[104:98] != 7'h51 || rm__h10284 != 3'b0) &&
(stage1_rg_stage_input[104:98] != 7'h71 ||
stage1_rg_stage_input[134:130] != 5'd0 ||
rm__h10284 != 3'b001) &&
(stage1_rg_stage_input[104:98] != 7'h61 ||
stage1_rg_stage_input[134:130] != 5'd0) &&
(stage1_rg_stage_input[104:98] != 7'h61 ||
stage1_rg_stage_input[134:130] != 5'b00001) &&
(stage1_rg_stage_input[104:98] != 7'h69 ||
stage1_rg_stage_input[134:130] != 5'd0) &&
(stage1_rg_stage_input[104:98] != 7'h69 ||
stage1_rg_stage_input[134:130] != 5'b00001) ;
assign NOT_stage1_rg_stage_input_32_BIT_332_77_83_AND_ETC___d1004 =
!stage1_rg_stage_input[332] &&
stage1_rg_stage_input[151:145] == 7'b1110011 &&
(stage1_rg_stage_input[112:110] == 3'b001 ||
stage1_rg_stage_input[112:110] == 3'b101) ;
assign NOT_stage1_rg_stage_input_32_BIT_332_77_83_AND_ETC___d1019 =
!stage1_rg_stage_input[332] &&
stage1_rg_stage_input[151:145] == 7'b1110011 &&
(stage1_rg_stage_input[112:110] == 3'b010 ||
stage1_rg_stage_input[112:110] == 3'b110 ||
stage1_rg_stage_input[112:110] == 3'b011 ||
stage1_rg_stage_input[112:110] == 3'b111) ;
assign NOT_stage1_rg_stage_input_32_BIT_332_77_83_AND_ETC___d1068 =
!stage1_rg_stage_input[332] &&
stage1_rg_stage_input[151:145] == 7'b1110011 &&
stage1_rg_stage_input[112:110] == 3'd0 &&
stage1_rg_stage_input_32_BITS_144_TO_140_027_E_ETC___d1065 ;
assign NOT_stage1_rg_stage_input_32_BIT_332_77_83_AND_ETC___d1129 =
!stage1_rg_stage_input[332] &&
stage1_rg_stage_input[151:145] == 7'b1110011 &&
stage1_rg_stage_input[112:110] == 3'd0 &&
NOT_rg_cur_priv_8_EQ_0b11_059_091_AND_NOT_rg_c_ETC___d1126 ;
assign NOT_stage1_rg_stage_input_32_BIT_332_77_83_AND_ETC___d2884 =
!stage1_rg_stage_input[332] &&
stage1_rg_stage_input[151:145] == 7'b1110011 &&
stage1_rg_stage_input[112:110] == 3'd0 &&
stage1_rg_stage_input[104:98] != 7'b0001001 &&
stage1_rg_stage_input[144:140] == 5'd0 &&
stage1_rg_stage_input[139:135] == 5'd0 &&
rg_cur_priv == 2'b11 &&
stage1_rg_stage_input[87:76] == 12'b001100000010 ;
assign NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d1219 =
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d972 &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1216 ;
assign NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d1297 =
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d985 &&
(stage1_rg_stage_input[151:145] == 7'b1100011 ||
stage1_rg_stage_input[151:145] == 7'b1101111 ||
stage1_rg_stage_input[151:145] == 7'b1100111 ||
(stage1_rg_stage_input[151:145] != 7'b0110011 ||
stage1_rg_stage_input[104:98] != 7'b0000001) &&
NOT_stage1_rg_stage_input_32_BITS_151_TO_145_7_ETC___d449 &&
(stage1_rg_stage_input[151:145] == 7'b0010011 ||
stage1_rg_stage_input[151:145] == 7'b0110011 ||
stage1_rg_stage_input[151:145] == 7'b0011011 ||
stage1_rg_stage_input[151:145] == 7'b0111011 ||
stage1_rg_stage_input[151:145] == 7'b0110111 ||
stage1_rg_stage_input[151:145] == 7'b0010111)) ;
assign NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d1335 =
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d972 &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1332 ;
assign NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d2303 =
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375 &&
!stage1_rg_stage_input[332] &&
(IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d965 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d969) ;
assign NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 =
!stage2_rg_full || stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d297 ||
!IF_stage2_rg_full_14_THEN_IF_stage2_rg_stage2__ETC___d337 &&
!IF_stage2_rg_full_14_THEN_IF_stage2_rg_stage2__ETC___d339 ;
assign NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375 =
!stage2_rg_full || stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d324 ||
!IF_NOT_stage2_rg_full_14_71_OR_stage2_rg_stage_ETC___d343 &&
!IF_NOT_stage2_rg_full_14_71_OR_stage2_rg_stage_ETC___d344 &&
!IF_NOT_stage2_rg_full_14_71_OR_stage2_rg_stage_ETC___d347 ;
assign NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d778 =
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375 &&
(stage1_rg_stage_input[332] ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d763 &&
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d775) ;
assign NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d985 =
(!stage2_rg_full || stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d297 ||
!IF_stage2_rg_full_14_THEN_IF_stage2_rg_stage2__ETC___d337) &&
(!stage2_rg_full || stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d297 ||
!IF_stage2_rg_full_14_THEN_IF_stage2_rg_stage2__ETC___d339) &&
(!stage2_rg_full || stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d324 ||
!IF_NOT_stage2_rg_full_14_71_OR_stage2_rg_stage_ETC___d343) &&
(!stage2_rg_full || stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d324 ||
!IF_NOT_stage2_rg_full_14_71_OR_stage2_rg_stage_ETC___d344) &&
(!stage2_rg_full || stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d324 ||
!IF_NOT_stage2_rg_full_14_71_OR_stage2_rg_stage_ETC___d347) ;
assign NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d148 =
stage2_rg_stage2[397:395] != 3'd0 &&
CASE_stage2_rg_stage2_BITS_397_TO_395_1_NOT_ne_ETC__q3 ;
assign NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d156 =
(stage2_rg_stage2[397:395] == 3'd1 ||
stage2_rg_stage2[397:395] == 3'd4 ||
stage2_rg_stage2[397:395] == 3'd2) &&
near_mem$dmem_valid &&
near_mem$dmem_exc ;
assign NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d177 =
(stage2_rg_stage2[397:395] != 3'd1 &&
stage2_rg_stage2[397:395] != 3'd4 &&
stage2_rg_stage2[397:395] != 3'd2 ||
!near_mem$dmem_valid ||
!near_mem$dmem_exc) &&
stage2_rg_stage2[397:395] != 3'd0 &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d175 ;
assign NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d289 =
stage2_rg_stage2[397:395] != 3'd2 &&
((stage2_rg_stage2[397:395] == 3'd3) ?
!stage2_mbox$valid :
!stage2_rg_stage2[5] && !stage2_fbox$valid) ;
assign NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d402 =
stage2_rg_stage2[397:395] != 3'd2 &&
((stage2_rg_stage2[397:395] == 3'd3) ?
stage2_mbox$valid :
!stage2_rg_stage2[5] && stage2_fbox$valid) ;
assign NOT_stageF_branch_predictor_predict_rsp_NOT_im_ETC___d2707 =
stageF_branch_predictor$predict_rsp[1:0] != 2'b0 &&
near_mem$imem_valid &&
!near_mem$imem_exc &&
addr_of_b32__h32333 == near_mem$imem_pc ;
assign SEXT_stage1_rg_stage_input_32_BITS_87_TO_76_047___d1259 =
{ {52{stage1_rg_stage_input_BITS_87_TO_76__q17[11]}},
stage1_rg_stage_input_BITS_87_TO_76__q17 } ;
assign SEXT_stageD_rg_data_667_BIT_76_684_CONCAT_stag_ETC___d1737 =
{ {9{offset__h18610[11]}}, offset__h18610 } ;
assign SEXT_stageD_rg_data_667_BIT_76_684_CONCAT_stag_ETC___d1762 =
{ {4{offset__h19241[8]}}, offset__h19241 } ;
assign _0_OR_stage1_rg_stage_input_32_BITS_104_TO_98_3_ETC___d2484 =
stage1_rg_stage_input_32_BITS_104_TO_98_38_EQ__ETC___d893 ||
(stage1_rg_stage_input[104:98] == 7'h60 ||
stage1_rg_stage_input[104:98] == 7'h68) &&
(stage1_rg_stage_input[134:130] == 5'b00010 ||
stage1_rg_stage_input[134:130] == 5'b00011) ||
stage1_rg_stage_input_32_BITS_104_TO_98_38_EQ__ETC___d935 ||
stage1_rg_stage_input[104:98] == 7'h69 &&
stage1_rg_stage_input[134:130] == 5'b00001 ;
assign _theResult_____1_fst__h12535 =
(stage1_rg_stage_input[112:110] == 3'd0 &&
stage1_rg_stage_input[151:145] == 7'b0110011 &&
stage1_rg_stage_input[262]) ?
rd_val___1__h12531 :
_theResult_____1_fst__h12542 ;
assign _theResult_____1_fst__h12570 =
rs1_val_bypassed__h5597 & _theResult___snd_snd__h16701 ;
assign _theResult____h33877 =
(delta_CPI_instrs__h33876 == 64'd0) ?
delta_CPI_instrs___1__h33921 :
delta_CPI_instrs__h33876 ;
assign _theResult____h5881 = x_out_data_to_stage1_instr__h17651 ;
assign _theResult___fst__h12706 =
(stage1_rg_stage_input[112:110] == 3'b001 &&
!stage1_rg_stage_input[263] &&
stage1_rg_stage_input[261:257] == 5'b0 &&
!stage1_rg_stage_input[262]) ?
rd_val___1__h16761 :
_theResult___fst__h12713 ;
assign _theResult___fst__h12713 =
stage1_rg_stage_input[262] ?
rd_val___1__h16822 :
rd_val___1__h16793 ;
assign _theResult___fst__h12794 =
{ {32{rs1_val_bypassed597_BITS_31_TO_0_SRL_rs2_val_b_ETC__q8[31]}},
rs1_val_bypassed597_BITS_31_TO_0_SRL_rs2_val_b_ETC__q8 } ;
assign _theResult___snd_fst_rd_val__h9435 =
stage2_rg_stage2[5] ?
stage2_fbox$word_fst :
stage2_rg_stage2[197:134] ;
assign _theResult___snd_snd__h16701 =
(stage1_rg_stage_input[151:145] == 7'b0010011) ?
SEXT_stage1_rg_stage_input_32_BITS_87_TO_76_047___d1259 :
rs2_val_bypassed__h5603 ;
assign _theResult___snd_snd_rd_val__h8290 =
stage2_rg_stage2[5] ?
stage2_rg_stage2[325:262] :
stage2_fbox$word_fst ;
assign addr_of_b32___1__h27521 = addr_of_b32__h27393 + 64'd4 ;
assign addr_of_b32___1__h32461 = addr_of_b32__h32333 + 64'd4 ;
assign addr_of_b32___1__h44012 = addr_of_b32__h43884 + 64'd4 ;
assign addr_of_b32__h27393 = { soc_map$m_pc_reset_value[63:2], 2'd0 } ;
assign addr_of_b32__h32333 =
{ stageF_branch_predictor$predict_rsp[63:2], 2'd0 } ;
assign addr_of_b32__h43884 = { rg_next_pc[63:2], 2'd0 } ;
assign alu_outputs___1_addr__h10323 =
IF_stage1_rg_stage_input_32_BITS_112_TO_110_80_ETC___d432 ?
branch_target__h10301 :
x_out_cf_info_fallthru_PC__h16274 ;
assign alu_outputs___1_addr__h10697 =
rs1_val_bypassed__h5597 +
{ {52{stage1_rg_stage_input_BITS_75_TO_64__q6[11]}},
stage1_rg_stage_input_BITS_75_TO_64__q6 } ;
assign alu_outputs___1_exc_code__h10979 =
(stage1_rg_stage_input[112:110] == 3'd0) ?
(stage1_rg_stage_input_32_BITS_144_TO_140_027_E_ETC___d1065 ?
4'd2 :
((stage1_rg_stage_input[144:140] == 5'd0 &&
stage1_rg_stage_input[139:135] == 5'd0) ?
CASE_stage1_rg_stage_input_BITS_87_TO_76_0b0_C_ETC__q16 :
4'd2)) :
4'd2 ;
assign alu_outputs___1_fval1__h11709 = x_out_data_to_stage2_fval1__h10123 ;
assign alu_outputs___1_fval2__h10701 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1555 &&
IF_NOT_stage2_rg_full_14_71_OR_stage2_rg_stage_ETC___d344) ?
x_out_fbypass_rd_val__h9454 :
rd_val__h9781 ;
assign alu_outputs___1_fval3__h11711 = x_out_data_to_stage2_fval3__h10125 ;
assign alu_outputs___1_val1__h10496 =
(stage1_rg_stage_input[112:110] == 3'b001) ?
rd_val__h16602 :
(stage1_rg_stage_input[262] ?
rd_val__h16675 :
rd_val__h16653) ;
assign alu_outputs___1_val1__h10541 =
(stage1_rg_stage_input[112:110] == 3'd0 &&
(stage1_rg_stage_input[151:145] != 7'b0110011 ||
!stage1_rg_stage_input[262])) ?
rd_val___1__h12450 :
_theResult_____1_fst__h12535 ;
assign alu_outputs___1_val1__h10570 =
(stage1_rg_stage_input[112:110] == 3'd0) ?
rd_val___1__h16730 :
_theResult___fst__h12706 ;
assign alu_outputs___1_val1__h10983 =
stage1_rg_stage_input[112] ?
{ 59'd0, stage1_rg_stage_input[139:135] } :
rs1_val_bypassed__h5597 ;
assign alu_outputs___1_val1__h11011 =
{ 57'd0, stage1_rg_stage_input[104:98] } ;
assign alu_outputs_cf_info_taken_PC__h16267 =
x_out_cf_info_taken_PC__h16275 ;
assign branch_target__h10301 =
stage1_rg_stage_input[401:338] +
{ {51{stage1_rg_stage_input_BITS_63_TO_51__q2[12]}},
stage1_rg_stage_input_BITS_63_TO_51__q2 } ;
assign cpi__h33879 = x__h33878 / 64'd10 ;
assign cpifrac__h33880 = x__h33878 % 64'd10 ;
assign csr_regfile_RDY_server_reset_request_put__219__ETC___d2231 =
csr_regfile$RDY_server_reset_request_put &&
f_reset_reqs$EMPTY_N &&
stageF_f_reset_reqs$FULL_N &&
stageD_f_reset_reqs$FULL_N &&
stage1_f_reset_reqs$FULL_N &&
stage2_f_reset_reqs$FULL_N &&
stage3_f_reset_reqs$FULL_N ;
assign csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2685 =
(csr_regfile$interrupt_pending[4] || csr_regfile$nmi_pending) &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375 &&
(IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d965 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d969) ;
assign csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2693 =
csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2685 ||
stage2_rg_stage2[397:395] != 3'd0 &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d2686 &&
stage2_rg_full ||
!stage1_rg_full ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d2295 ||
!stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 ||
IF_IF_stage1_rg_stage_input_32_BITS_151_TO_145_ETC___d1657 ;
assign csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2735 =
(csr_regfile$interrupt_pending[4] || csr_regfile$nmi_pending) &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375 &&
(IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d965 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d969) ||
stage2_rg_stage2[397:395] != 3'd0 &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d2686 &&
stage2_rg_full ;
assign csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2739 =
csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2735 ||
!stage1_rg_full ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d2295 ||
!stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 ||
IF_IF_stage1_rg_stage_input_32_BITS_151_TO_145_ETC___d1657 ;
assign csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2953 =
(csr_regfile$interrupt_pending[4] || csr_regfile$nmi_pending) &&
rg_state == 4'd3 &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d2950 &&
!stage2_rg_full &&
!stage3_rg_full ;
assign csr_regfile_read_csr_mcycle__7_MINUS_rg_start__ETC___d2801 =
delta_CPI_cycles__h33875 * 64'd10 ;
assign csr_regfile_read_misa__6_BIT_2_672_AND_stageD__ETC___d1747 =
csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b10 &&
stageD_rg_data[79:76] == 4'b1000 &&
stageD_rg_data[75:71] != 5'd0 ;
assign csr_regfile_read_misa__6_BIT_2_672_AND_stageD__ETC___d1753 =
csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b10 &&
stageD_rg_data[79:76] == 4'b1001 &&
stageD_rg_data[75:71] != 5'd0 ;
assign csr_regfile_read_mstatus__9_BITS_14_TO_13_1_EQ_ETC___d573 =
csr_regfile$read_mstatus[14:13] == 2'h0 ||
((stage1_rg_stage_input[112:110] == 3'b111) ?
csr_regfile$read_frm == 3'b101 ||
csr_regfile$read_frm == 3'b110 ||
csr_regfile$read_frm == 3'b111 :
stage1_rg_stage_input[112:110] == 3'b101 ||
stage1_rg_stage_input[112:110] == 3'b110) ;
assign cur_verbosity__h3946 =
(csr_regfile$read_csr_minstret < cfg_logdelay) ?
4'd0 :
cfg_verbosity ;
assign d_instr__h25360 =
NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d2072 ?
instr_out___1__h25362 :
IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg_p_ETC___d2090 ;
assign data_to_stage2_addr__h10103 = x_out_data_to_stage2_addr__h10120 ;
assign data_to_stage2_val2__h10105 = x_out_data_to_stage2_val2__h10122 ;
assign decoded_instr_funct10__h30753 =
{ _theResult____h5881[31:25], _theResult____h5881[14:12] } ;
assign decoded_instr_imm12_S__h30755 =
{ _theResult____h5881[31:25], _theResult____h5881[11:7] } ;
assign decoded_instr_imm13_SB__h30756 =
{ _theResult____h5881[31],
_theResult____h5881[7],
_theResult____h5881[30:25],
_theResult____h5881[11:8],
1'b0 } ;
assign decoded_instr_imm21_UJ__h30758 =
{ _theResult____h5881[31],
_theResult____h5881[19:12],
_theResult____h5881[20],
_theResult____h5881[30:21],
1'b0 } ;
assign delta_CPI_cycles__h33875 =
csr_regfile$read_csr_mcycle - rg_start_CPI_cycles ;
assign delta_CPI_instrs___1__h33921 = delta_CPI_instrs__h33876 + 64'd1 ;
assign delta_CPI_instrs__h33876 =
csr_regfile$read_csr_minstret - rg_start_CPI_instrs ;
assign fall_through_pc__h9846 =
stage1_rg_stage_input[401:338] +
(stage1_rg_stage_input[333] ? 64'd4 : 64'd2) ;
assign imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d2109 =
imem_rg_pc[1:0] == 2'b0 ||
(!imem_rg_pc_BITS_63_TO_2_4_EQ_near_mem_imem_pc__ETC___d17 ||
near_mem$imem_instr[17:16] == 2'b11) &&
(!imem_rg_pc_BITS_63_TO_2_4_EQ_imem_rg_cache_add_ETC___d2064 ||
imem_rg_cache_b16[1:0] == 2'b11) ;
assign imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_near_mem__ETC___d2251 =
imem_rg_pc[1:0] == 2'b0 || !near_mem$imem_valid ||
near_mem$imem_exc ||
!imem_rg_pc_BITS_63_TO_2_4_EQ_near_mem_imem_pc__ETC___d17 ;
assign imem_rg_pc_BITS_63_TO_2_4_EQ_imem_rg_cache_add_ETC___d2064 =
imem_rg_pc[63:2] == imem_rg_cache_addr[63:2] ;
assign imem_rg_pc_BITS_63_TO_2_4_EQ_near_mem_imem_pc__ETC___d17 =
imem_rg_pc[63:2] == near_mem$imem_pc[63:2] ;
assign imm12__h17903 = { 4'd0, offset__h17775 } ;
assign imm12__h18240 = { 5'd0, offset__h18182 } ;
assign imm12__h19876 = { {6{imm6__h19874[5]}}, imm6__h19874 } ;
assign imm12__h20545 = { {2{nzimm10__h20543[9]}}, nzimm10__h20543 } ;
assign imm12__h20760 = { 2'd0, nzimm10__h20758 } ;
assign imm12__h20956 = { 6'b0, imm6__h19874 } ;
assign imm12__h21293 = { 6'b010000, imm6__h19874 } ;
assign imm12__h22914 = { 3'd0, offset__h22828 } ;
assign imm12__h23266 = { 4'd0, offset__h23200 } ;
assign imm20__h20004 = { {14{imm6__h19874[5]}}, imm6__h19874 } ;
assign imm6__h19874 = { stageD_rg_data[76], stageD_rg_data[70:66] } ;
assign instr___1__h17725 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b10 &&
stageD_rg_data[75:71] != 5'd0 &&
stageD_rg_data[79:77] == 3'b010) ?
instr__h17902 :
IF_csr_regfile_read_misa__6_BIT_2_672_AND_stag_ETC___d1964 ;
assign instr__h17902 =
{ imm12__h17903, 8'd18, stageD_rg_data[75:71], 7'b0000011 } ;
assign instr__h18047 =
{ 4'd0,
stageD_rg_data[72:71],
stageD_rg_data[76],
stageD_rg_data[70:66],
8'd18,
offset_BITS_4_TO_0___h18171,
7'b0100011 } ;
assign instr__h18239 =
{ imm12__h18240, rs1__h18241, 3'b010, rd__h18242, 7'b0000011 } ;
assign instr__h18434 =
{ 5'd0,
stageD_rg_data[69],
stageD_rg_data[76],
rd__h18242,
rs1__h18241,
3'b010,
offset_BITS_4_TO_0___h18602,
7'b0100011 } ;
assign instr__h18663 =
{ SEXT_stageD_rg_data_667_BIT_76_684_CONCAT_stag_ETC___d1737[20],
SEXT_stageD_rg_data_667_BIT_76_684_CONCAT_stag_ETC___d1737[10:1],
SEXT_stageD_rg_data_667_BIT_76_684_CONCAT_stag_ETC___d1737[11],
SEXT_stageD_rg_data_667_BIT_76_684_CONCAT_stag_ETC___d1737[19:12],
12'd111 } ;
assign instr__h19116 = { 12'd0, stageD_rg_data[75:71], 15'd103 } ;
assign instr__h19232 = { 12'd0, stageD_rg_data[75:71], 15'd231 } ;
assign instr__h19297 =
{ SEXT_stageD_rg_data_667_BIT_76_684_CONCAT_stag_ETC___d1762[12],
SEXT_stageD_rg_data_667_BIT_76_684_CONCAT_stag_ETC___d1762[10:5],
5'd0,
rs1__h18241,
3'b0,
SEXT_stageD_rg_data_667_BIT_76_684_CONCAT_stag_ETC___d1762[4:1],
SEXT_stageD_rg_data_667_BIT_76_684_CONCAT_stag_ETC___d1762[11],
7'b1100011 } ;
assign instr__h19614 =
{ SEXT_stageD_rg_data_667_BIT_76_684_CONCAT_stag_ETC___d1762[12],
SEXT_stageD_rg_data_667_BIT_76_684_CONCAT_stag_ETC___d1762[10:5],
5'd0,
rs1__h18241,
3'b001,
SEXT_stageD_rg_data_667_BIT_76_684_CONCAT_stag_ETC___d1762[4:1],
SEXT_stageD_rg_data_667_BIT_76_684_CONCAT_stag_ETC___d1762[11],
7'b1100011 } ;
assign instr__h19952 =
{ imm12__h19876, 8'd0, stageD_rg_data[75:71], 7'b0010011 } ;
assign instr__h20136 =
{ imm20__h20004, stageD_rg_data[75:71], 7'b0110111 } ;
assign instr__h20265 =
{ imm12__h19876,
stageD_rg_data[75:71],
3'b0,
stageD_rg_data[75:71],
7'b0010011 } ;
assign instr__h20492 =
{ imm12__h19876,
stageD_rg_data[75:71],
3'b0,
stageD_rg_data[75:71],
7'b0011011 } ;
assign instr__h20747 =
{ imm12__h20545,
stageD_rg_data[75:71],
3'b0,
stageD_rg_data[75:71],
7'b0010011 } ;
assign instr__h20919 = { imm12__h20760, 8'd16, rd__h18242, 7'b0010011 } ;
assign instr__h21088 =
{ imm12__h20956,
stageD_rg_data[75:71],
3'b001,
stageD_rg_data[75:71],
7'b0010011 } ;
assign instr__h21277 =
{ imm12__h20956, rs1__h18241, 3'b101, rs1__h18241, 7'b0010011 } ;
assign instr__h21466 =
{ imm12__h21293, rs1__h18241, 3'b101, rs1__h18241, 7'b0010011 } ;
assign instr__h21583 =
{ imm12__h19876, rs1__h18241, 3'b111, rs1__h18241, 7'b0010011 } ;
assign instr__h21761 =
{ 7'b0,
stageD_rg_data[70:66],
8'd0,
stageD_rg_data[75:71],
7'b0110011 } ;
assign instr__h21880 =
{ 7'b0,
stageD_rg_data[70:66],
stageD_rg_data[75:71],
3'b0,
stageD_rg_data[75:71],
7'b0110011 } ;
assign instr__h21975 =
{ 7'b0,
rd__h18242,
rs1__h18241,
3'b111,
rs1__h18241,
7'b0110011 } ;
assign instr__h22111 =
{ 7'b0,
rd__h18242,
rs1__h18241,
3'b110,
rs1__h18241,
7'b0110011 } ;
assign instr__h22247 =
{ 7'b0,
rd__h18242,
rs1__h18241,
3'b100,
rs1__h18241,
7'b0110011 } ;
assign instr__h22383 =
{ 7'b0100000,
rd__h18242,
rs1__h18241,
3'b0,
rs1__h18241,
7'b0110011 } ;
assign instr__h22521 =
{ 7'b0,
rd__h18242,
rs1__h18241,
3'b0,
rs1__h18241,
7'b0111011 } ;
assign instr__h22659 =
{ 7'b0100000,
rd__h18242,
rs1__h18241,
3'b0,
rs1__h18241,
7'b0111011 } ;
assign instr__h22817 =
{ 12'b000000000001,
stageD_rg_data[75:71],
3'b0,
stageD_rg_data[75:71],
7'b1110011 } ;
assign instr__h22913 =
{ imm12__h22914, 8'd19, stageD_rg_data[75:71], 7'b0000011 } ;
assign instr__h23066 =
{ 3'd0,
stageD_rg_data[73:71],
stageD_rg_data[76],
stageD_rg_data[70:66],
8'd19,
offset_BITS_4_TO_0___h23541,
7'b0100011 } ;
assign instr__h23265 =
{ imm12__h23266, rs1__h18241, 3'b011, rd__h18242, 7'b0000011 } ;
assign instr__h23416 =
{ 4'd0,
stageD_rg_data[70:69],
stageD_rg_data[76],
rd__h18242,
rs1__h18241,
3'b011,
offset_BITS_4_TO_0___h23541,
7'b0100011 } ;
assign instr__h23621 =
{ imm12__h17903, 8'd18, stageD_rg_data[75:71], 7'b0000111 } ;
assign instr__h24421 =
{ imm12__h22914, 8'd19, stageD_rg_data[75:71], 7'b0000111 } ;
assign instr__h24586 =
{ 3'd0,
stageD_rg_data[73:71],
stageD_rg_data[76],
stageD_rg_data[70:66],
8'd19,
offset_BITS_4_TO_0___h23541,
7'b0100111 } ;
assign instr__h24785 =
{ imm12__h23266, rs1__h18241, 3'b011, rd__h18242, 7'b0000111 } ;
assign instr__h24936 =
{ 4'd0,
stageD_rg_data[70:69],
stageD_rg_data[76],
rd__h18242,
rs1__h18241,
3'b011,
offset_BITS_4_TO_0___h23541,
7'b0100111 } ;
assign instr_out___1__h25362 =
{ near_mem$imem_instr[15:0], imem_rg_cache_b16 } ;
assign instr_out___1__h25384 = { 16'b0, near_mem$imem_instr[15:0] } ;
assign near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d2117 =
near_mem$imem_exc ||
NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d2072 ||
imem_rg_pc[1:0] == 2'b0 &&
imem_rg_pc_BITS_63_TO_2_4_EQ_near_mem_imem_pc__ETC___d17 &&
near_mem$imem_instr[1:0] == 2'b11 ;
assign near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d2119 =
near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d2117 ||
NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d2086 ||
imem_rg_pc[1:0] == 2'b0 &&
imem_rg_pc_BITS_63_TO_2_4_EQ_near_mem_imem_pc__ETC___d17 &&
near_mem$imem_instr[1:0] != 2'b11 ;
assign near_mem_imem_pc__5_EQ_imem_rg_pc_PLUS_2_066___d2067 =
near_mem$imem_pc == imem_rg_pc + 64'd2 ;
assign near_mem_imem_valid_AND_near_mem_imem_exc__1_A_ETC___d2214 =
near_mem$imem_valid && near_mem$imem_exc &&
near_mem$imem_exc_code != 4'd0 &&
near_mem$imem_exc_code != 4'd1 &&
near_mem$imem_exc_code != 4'd2 &&
near_mem$imem_exc_code != 4'd3 &&
near_mem$imem_exc_code != 4'd4 &&
near_mem$imem_exc_code != 4'd5 &&
near_mem$imem_exc_code != 4'd6 &&
near_mem$imem_exc_code != 4'd7 &&
near_mem$imem_exc_code != 4'd8 &&
near_mem$imem_exc_code != 4'd9 &&
near_mem$imem_exc_code != 4'd11 &&
near_mem$imem_exc_code != 4'd12 &&
near_mem$imem_exc_code != 4'd13 &&
near_mem$imem_exc_code != 4'd15 ;
assign new_epoch__h26813 = rg_epoch + 2'd1 ;
assign next_pc___1__h13967 = stage1_rg_stage_input[401:338] + 64'd2 ;
assign next_pc__h10336 =
stage1_rg_stage_input[401:338] +
{ {43{stage1_rg_stage_input_BITS_30_TO_10__q1[20]}},
stage1_rg_stage_input_BITS_30_TO_10__q1 } ;
assign next_pc__h10371 =
{ IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d1260[63:1],
1'd0 } ;
assign next_pc__h13964 = stage1_rg_stage_input[401:338] + 64'd4 ;
assign next_pc__h9847 = x_out_next_pc__h9864 ;
assign nzimm10__h20543 =
{ stageD_rg_data[76],
stageD_rg_data[68:67],
stageD_rg_data[69],
stageD_rg_data[66],
stageD_rg_data[70],
4'b0 } ;
assign nzimm10__h20758 =
{ stageD_rg_data[74:71],
stageD_rg_data[76:75],
stageD_rg_data[69],
stageD_rg_data[70],
2'b0 } ;
assign offset_BITS_4_TO_0___h18171 = { stageD_rg_data[75:73], 2'b0 } ;
assign offset_BITS_4_TO_0___h18602 =
{ stageD_rg_data[75:74], stageD_rg_data[70], 2'b0 } ;
assign offset_BITS_4_TO_0___h23541 = { stageD_rg_data[75:74], 3'b0 } ;
assign offset__h17775 =
{ stageD_rg_data[67:66],
stageD_rg_data[76],
stageD_rg_data[70:68],
2'b0 } ;
assign offset__h18182 =
{ stageD_rg_data[69],
stageD_rg_data[76:74],
stageD_rg_data[70],
2'b0 } ;
assign offset__h18610 =
{ stageD_rg_data[76],
stageD_rg_data[72],
stageD_rg_data[74:73],
stageD_rg_data[70],
stageD_rg_data[71],
stageD_rg_data[66],
stageD_rg_data[75],
stageD_rg_data[69:67],
1'b0 } ;
assign offset__h19241 =
{ stageD_rg_data[76],
stageD_rg_data[70:69],
stageD_rg_data[66],
stageD_rg_data[75:74],
stageD_rg_data[68:67],
1'b0 } ;
assign offset__h22828 =
{ stageD_rg_data[68:66],
stageD_rg_data[76],
stageD_rg_data[70:69],
3'b0 } ;
assign offset__h23200 =
{ stageD_rg_data[70:69], stageD_rg_data[76:74], 3'b0 } ;
assign output_stage2___1_data_to_stage3_frd_val__h8219 =
stage2_rg_stage2[5] ?
((stage2_rg_stage2[412:410] == 3'b010) ?
{ 32'hFFFFFFFF, near_mem$dmem_word64[31:0] } :
near_mem$dmem_word64) :
stage2_rg_stage2[197:134] ;
assign rd__h18242 = { 2'b01, stageD_rg_data[68:66] } ;
assign rd_val___1__h12450 =
rs1_val_bypassed__h5597 + _theResult___snd_snd__h16701 ;
assign rd_val___1__h12531 =
rs1_val_bypassed__h5597 - _theResult___snd_snd__h16701 ;
assign rd_val___1__h12538 =
((rs1_val_bypassed__h5597 ^ 64'h8000000000000000) <
(_theResult___snd_snd__h16701 ^ 64'h8000000000000000)) ?
64'd1 :
64'd0 ;
assign rd_val___1__h12545 =
(rs1_val_bypassed__h5597 < _theResult___snd_snd__h16701) ?
64'd1 :
64'd0 ;
assign rd_val___1__h12552 =
rs1_val_bypassed__h5597 ^ _theResult___snd_snd__h16701 ;
assign rd_val___1__h12559 =
rs1_val_bypassed__h5597 | _theResult___snd_snd__h16701 ;
assign rd_val___1__h16730 =
{ {32{IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC__q18[31]}},
IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC__q18 } ;
assign rd_val___1__h16761 = { {32{x__h16764[31]}}, x__h16764 } ;
assign rd_val___1__h16793 = { {32{x__h16796[31]}}, x__h16796 } ;
assign rd_val___1__h16822 = { {32{tmp__h16821[31]}}, tmp__h16821 } ;
assign rd_val___1__h16874 =
{ {32{rs1_val_bypassed597_BITS_31_TO_0_PLUS_rs2_val__ETC__q9[31]}},
rs1_val_bypassed597_BITS_31_TO_0_PLUS_rs2_val__ETC__q9 } ;
assign rd_val___1__h16922 =
{ {32{rs1_val_bypassed597_BITS_31_TO_0_MINUS_rs2_val_ETC__q10[31]}},
rs1_val_bypassed597_BITS_31_TO_0_MINUS_rs2_val_ETC__q10 } ;
assign rd_val___1__h16928 = { {32{x__h16931[31]}}, x__h16931 } ;
assign rd_val___1__h16973 = { {32{x__h16976[31]}}, x__h16976 } ;
assign rd_val__h10612 = { {32{v32__h10610[31]}}, v32__h10610 } ;
assign rd_val__h10633 = stage1_rg_stage_input[401:338] + rd_val__h10612 ;
assign rd_val__h16602 = rs1_val_bypassed__h5597 << shamt__h10483 ;
assign rd_val__h16653 = rs1_val_bypassed__h5597 >> shamt__h10483 ;
assign rd_val__h16675 =
rs1_val_bypassed__h5597 >> shamt__h10483 |
~(64'hFFFFFFFFFFFFFFFF >> shamt__h10483) &
{64{rs1_val_bypassed__h5597[63]}} ;
assign rd_val__h9684 =
(!stage3_rg_stage3[69] && stage3_rg_full &&
stage3_rg_stage3[140] &&
stage3_rg_stage3_00_BITS_139_TO_135_09_EQ_stag_ETC___d407) ?
stage3_rg_stage3[134:71] :
gpr_regfile$read_rs1 ;
assign rd_val__h9717 =
(!stage3_rg_stage3[69] && stage3_rg_full &&
stage3_rg_stage3[140] &&
stage3_rg_stage3_00_BITS_139_TO_135_09_EQ_stag_ETC___d415) ?
stage3_rg_stage3[134:71] :
gpr_regfile$read_rs2 ;
assign rd_val__h9750 =
(stage3_rg_stage3[69] && stage3_rg_full &&
stage3_rg_stage3[140] &&
stage3_rg_stage3_00_BITS_139_TO_135_09_EQ_stag_ETC___d407) ?
stage3_rg_stage3[63:0] :
fpr_regfile$read_rs1 ;
assign rd_val__h9781 =
(stage3_rg_stage3[69] && stage3_rg_full &&
stage3_rg_stage3[140] &&
stage3_rg_stage3_00_BITS_139_TO_135_09_EQ_stag_ETC___d415) ?
stage3_rg_stage3[63:0] :
fpr_regfile$read_rs2 ;
assign rd_val__h9815 =
(stage3_rg_stage3[69] && stage3_rg_full &&
stage3_rg_stage3[140] &&
stage3_rg_stage3[139:135] == stage1_rg_stage_input[129:125]) ?
stage3_rg_stage3[63:0] :
fpr_regfile$read_rs3 ;
assign rg_cur_priv_8_EQ_0b11_059_OR_rg_cur_priv_8_EQ__ETC___d1124 =
(rg_cur_priv == 2'b11 ||
rg_cur_priv == 2'b01 && !csr_regfile$read_mstatus[21] ||
rg_cur_priv == 2'b0 && csr_regfile$read_misa[13]) &&
stage1_rg_stage_input[87:76] == 12'b000100000101 ;
assign rg_cur_priv_8_EQ_0b11_059_OR_rg_cur_priv_8_EQ__ETC___d1189 =
(rg_cur_priv == 2'b11 ||
rg_cur_priv == 2'b01 && !csr_regfile$read_mstatus[20]) &&
stage1_rg_stage_input[104:98] == 7'b0001001 ||
stage1_rg_stage_input[144:140] != 5'd0 ||
stage1_rg_stage_input[139:135] != 5'd0 ||
rg_cur_priv != 2'b11 &&
(rg_cur_priv != 2'b01 || csr_regfile$read_mstatus[22]) ||
stage1_rg_stage_input[87:76] != 12'b000100000010 ;
assign rg_cur_priv_8_EQ_0b11_059_OR_rg_cur_priv_8_EQ__ETC___d1203 =
(rg_cur_priv == 2'b11 ||
rg_cur_priv == 2'b01 && !csr_regfile$read_mstatus[20]) &&
stage1_rg_stage_input[104:98] == 7'b0001001 ||
stage1_rg_stage_input[144:140] != 5'd0 ||
stage1_rg_stage_input[139:135] != 5'd0 ||
NOT_rg_cur_priv_8_EQ_0b11_059_091_AND_NOT_rg_c_ETC___d1201 ;
assign rg_cur_priv_8_EQ_0b11_059_OR_rg_cur_priv_8_EQ__ETC___d1635 =
(rg_cur_priv == 2'b11 ||
rg_cur_priv == 2'b01 && !csr_regfile$read_mstatus[20]) &&
stage1_rg_stage_input[104:98] == 7'b0001001 ||
stage1_rg_stage_input[144:140] != 5'd0 ||
stage1_rg_stage_input[139:135] != 5'd0 ||
stage1_rg_stage_input[87:76] != 12'b0 &&
stage1_rg_stage_input[87:76] != 12'b000000000001 ;
assign rg_state_7_EQ_12_4_AND_csr_regfile_wfi_resume__ETC___d2937 =
rg_state == 4'd12 && csr_regfile$wfi_resume &&
(!stageF_rg_full ||
near_mem$imem_valid &&
near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d2119) ;
assign rg_state_7_EQ_3_326_AND_NOT_csr_regfile_interr_ETC___d2753 =
rg_state == 4'd3 &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2750 &&
!stage3_rg_full &&
!stage2_rg_full ;
assign rg_state_7_EQ_3_326_AND_NOT_csr_regfile_interr_ETC___d2779 =
rg_state_7_EQ_3_326_AND_NOT_csr_regfile_interr_ETC___d2753 &&
stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d2343 &&
(stage1_rg_stage_input[332] ||
((stage1_rg_stage_input[151:145] == 7'b1100011) ?
stage1_rg_stage_input[112:110] != 3'd0 &&
stage1_rg_stage_input[112:110] != 3'b001 &&
stage1_rg_stage_input[112:110] != 3'b100 &&
stage1_rg_stage_input[112:110] != 3'b101 &&
stage1_rg_stage_input[112:110] != 3'b110 &&
stage1_rg_stage_input[112:110] != 3'b111 :
stage1_rg_stage_input[151:145] != 7'b1101111 &&
((stage1_rg_stage_input[151:145] == 7'b1100111) ?
stage1_rg_stage_input[112:110] != 3'd0 :
NOT_stage1_rg_stage_input_32_BITS_151_TO_145_7_ETC___d2774))) ;
assign rg_state_7_EQ_3_326_AND_NOT_csr_regfile_interr_ETC___d2814 =
rg_state == 4'd3 &&
(!csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d965 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d969) ;
assign rg_state_7_EQ_3_326_AND_NOT_csr_regfile_interr_ETC___d2817 =
rg_state_7_EQ_3_326_AND_NOT_csr_regfile_interr_ETC___d2814 &&
!stage3_rg_full &&
!stage2_rg_full &&
stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d2343 ;
assign rg_state_7_EQ_3_326_AND_NOT_csr_regfile_interr_ETC___d2908 =
rg_state_7_EQ_3_326_AND_NOT_csr_regfile_interr_ETC___d2817 &&
!stage1_rg_stage_input[332] &&
stage1_rg_stage_input[151:145] == 7'b0001111 &&
stage1_rg_stage_input_32_BITS_112_TO_110_80_EQ_ETC___d1049 &&
(!stageF_rg_full ||
near_mem$imem_valid &&
near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d2119) ;
assign rg_state_7_EQ_3_326_AND_NOT_csr_regfile_interr_ETC___d2917 =
rg_state_7_EQ_3_326_AND_NOT_csr_regfile_interr_ETC___d2817 &&
!stage1_rg_stage_input[332] &&
stage1_rg_stage_input[151:145] == 7'b0001111 &&
stage1_rg_stage_input_32_BITS_112_TO_110_80_EQ_ETC___d1035 &&
(!stageF_rg_full ||
near_mem$imem_valid &&
near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d2119) ;
assign rg_state_7_EQ_3_326_AND_NOT_csr_regfile_interr_ETC___d2926 =
rg_state_7_EQ_3_326_AND_NOT_csr_regfile_interr_ETC___d2817 &&
NOT_stage1_rg_stage_input_32_BIT_332_77_83_AND_ETC___d1068 &&
(!stageF_rg_full ||
near_mem$imem_valid &&
near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d2119) ;
assign rg_state_7_EQ_3_326_AND_stage3_rg_full_8_OR_st_ETC___d2338 =
rg_state == 4'd3 &&
(stage3_rg_full || stage2_rg_full || stage1_rg_full ||
stageD_rg_full ||
stageF_rg_full) &&
stage3_rg_full_8_OR_NOT_stage2_rg_full_14_71_O_ETC___d2337 ;
assign rg_state_7_EQ_5_941_AND_NOT_stageF_rg_full_094_ETC___d2942 =
rg_state == 4'd5 &&
(!stageF_rg_full ||
near_mem$imem_valid &&
near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d2119) ;
assign rg_state_7_EQ_8_864_AND_NOT_stageF_rg_full_094_ETC___d2865 =
rg_state == 4'd8 &&
(!stageF_rg_full ||
near_mem$imem_valid &&
near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d2119) ;
assign rg_trap_info_787_BITS_131_TO_68_788_EQ_csr_reg_ETC___d2797 =
rg_trap_info[131:68] == csr_regfile$csr_trap_actions[193:130] ;
assign rm__h10284 =
(stage1_rg_stage_input[112:110] == 3'b111) ?
csr_regfile$read_frm :
stage1_rg_stage_input[112:110] ;
assign rs1__h18241 = { 2'b01, stageD_rg_data[73:71] } ;
assign rs1_val__h34495 =
(rg_trap_instr[14:12] == 3'b001) ?
rg_csr_val1 :
{ 59'd0, rg_trap_instr[19:15] } ;
assign rs1_val_bypassed597_BITS_31_TO_0_MINUS_rs2_val_ETC__q10 =
rs1_val_bypassed__h5597[31:0] - rs2_val_bypassed__h5603[31:0] ;
assign rs1_val_bypassed597_BITS_31_TO_0_PLUS_rs2_val__ETC__q9 =
rs1_val_bypassed__h5597[31:0] + rs2_val_bypassed__h5603[31:0] ;
assign rs1_val_bypassed597_BITS_31_TO_0_SRL_rs2_val_b_ETC__q8 =
rs1_val_bypassed__h5597[31:0] >> rs2_val_bypassed__h5603[4:0] |
~(32'hFFFFFFFF >> rs2_val_bypassed__h5603[4:0]) &
{32{rs1_val_bypassed597_BITS_31_TO_0__q7[31]}} ;
assign rs1_val_bypassed597_BITS_31_TO_0__q7 =
rs1_val_bypassed__h5597[31:0] ;
assign rs1_val_bypassed__h5597 =
(stage1_rg_stage_input[139:135] == 5'd0) ? 64'd0 : val__h9686 ;
assign rs2_val_bypassed__h5603 =
(stage1_rg_stage_input[134:130] == 5'd0) ? 64'd0 : val__h9719 ;
assign shamt__h10483 =
(stage1_rg_stage_input[151:145] == 7'b0010011) ?
stage1_rg_stage_input[81:76] :
rs2_val_bypassed__h5603[5:0] ;
assign stage1_rg_full_31_AND_NOT_stage2_rg_full_14_71_ETC___d1317 =
stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d972 &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d985 &&
(stage1_rg_stage_input[151:145] == 7'b0000011 ||
stage1_rg_stage_input[151:145] == 7'b0000111) ;
assign stage1_rg_full_31_AND_NOT_stage2_rg_full_14_71_ETC___d1375 =
stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d972 &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d985 &&
stage1_rg_stage_input[151:145] == 7'b0101111 ;
assign stage1_rg_full_31_AND_NOT_stage2_rg_full_14_71_ETC___d1401 =
stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d972 &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d1398 ;
assign stage1_rg_full_31_AND_NOT_stage2_rg_full_14_71_ETC___d990 =
stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375 &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d985 &&
!stage1_rg_stage_input[332] &&
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d965 ;
assign stage1_rg_full_31_AND_NOT_stage2_rg_full_14_71_ETC___d998 =
stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375 &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d995 ;
assign stage1_rg_full_31_AND_stage1_rg_stage_input_32_ETC___d363 =
stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349) ;
assign stage1_rg_stage_input_32_BITS_104_TO_98_38_EQ__ETC___d2427 =
stage1_rg_stage_input_32_BITS_104_TO_98_38_EQ__ETC___d869 ||
stage1_rg_stage_input[104:98] == 7'h14 && rm__h10284 == 3'b001 ||
stage1_rg_stage_input[104:98] == 7'h68 &&
stage1_rg_stage_input[134:130] == 5'd0 ||
stage1_rg_stage_input[104:98] == 7'h68 &&
stage1_rg_stage_input[134:130] == 5'b00001 ||
stage1_rg_stage_input[104:98] == 7'h78 &&
stage1_rg_stage_input[134:130] == 5'd0 &&
rm__h10284 == 3'b0 ;
assign stage1_rg_stage_input_32_BITS_104_TO_98_38_EQ__ETC___d869 =
stage1_rg_stage_input[104:98] == 7'h0 ||
stage1_rg_stage_input[104:98] == 7'h04 ||
stage1_rg_stage_input[104:98] == 7'h08 ||
stage1_rg_stage_input[104:98] == 7'h0C ||
stage1_rg_stage_input[104:98] == 7'h2C &&
stage1_rg_stage_input[134:130] == 5'd0 ||
stage1_rg_stage_input[104:98] == 7'h10 && rm__h10284 == 3'b0 ||
stage1_rg_stage_input[104:98] == 7'h10 &&
(rm__h10284 == 3'b001 || rm__h10284 == 3'b010) ||
stage1_rg_stage_input[104:98] == 7'h14 && rm__h10284 == 3'b0 ;
assign stage1_rg_stage_input_32_BITS_104_TO_98_38_EQ__ETC___d878 =
stage1_rg_stage_input_32_BITS_104_TO_98_38_EQ__ETC___d869 ||
stage1_rg_stage_input[104:98] == 7'h14 && rm__h10284 == 3'b001 ||
stage1_rg_stage_input[104:98] == 7'h60 &&
stage1_rg_stage_input[134:130] == 5'd0 ||
stage1_rg_stage_input[104:98] == 7'h60 &&
stage1_rg_stage_input[134:130] == 5'b00001 ||
stage1_rg_stage_input[104:98] == 7'h70 &&
stage1_rg_stage_input[134:130] == 5'd0 &&
rm__h10284 == 3'b0 ;
assign stage1_rg_stage_input_32_BITS_104_TO_98_38_EQ__ETC___d886 =
stage1_rg_stage_input_32_BITS_104_TO_98_38_EQ__ETC___d878 ||
stage1_rg_stage_input[104:98] == 7'h50 &&
(rm__h10284 == 3'b010 || rm__h10284 == 3'b001 ||
rm__h10284 == 3'b0) ||
stage1_rg_stage_input[104:98] == 7'h70 &&
stage1_rg_stage_input[134:130] == 5'd0 &&
rm__h10284 == 3'b001 ;
assign stage1_rg_stage_input_32_BITS_104_TO_98_38_EQ__ETC___d893 =
stage1_rg_stage_input_32_BITS_104_TO_98_38_EQ__ETC___d886 ||
stage1_rg_stage_input[104:98] == 7'h68 &&
(stage1_rg_stage_input[134:130] == 5'd0 ||
stage1_rg_stage_input[134:130] == 5'b00001) ||
stage1_rg_stage_input[104:98] == 7'h78 &&
stage1_rg_stage_input[134:130] == 5'd0 &&
rm__h10284 == 3'b0 ;
assign stage1_rg_stage_input_32_BITS_104_TO_98_38_EQ__ETC___d918 =
stage1_rg_stage_input[104:98] == 7'b0000001 ||
stage1_rg_stage_input[104:98] == 7'h05 ||
stage1_rg_stage_input[104:98] == 7'b0001001 ||
stage1_rg_stage_input[104:98] == 7'h0D ||
stage1_rg_stage_input[104:98] == 7'h2D &&
stage1_rg_stage_input[134:130] == 5'd0 ||
stage1_rg_stage_input[104:98] == 7'h11 && rm__h10284 == 3'b0 ||
stage1_rg_stage_input[104:98] == 7'h11 &&
(rm__h10284 == 3'b001 || rm__h10284 == 3'b010) ||
stage1_rg_stage_input[104:98] == 7'h15 && rm__h10284 == 3'b0 ||
stage1_rg_stage_input[104:98] == 7'h15 && rm__h10284 == 3'b001 ||
stage1_rg_stage_input[104:98] == 7'h20 &&
stage1_rg_stage_input[134:130] == 5'b00001 ;
assign stage1_rg_stage_input_32_BITS_104_TO_98_38_EQ__ETC___d929 =
stage1_rg_stage_input_32_BITS_104_TO_98_38_EQ__ETC___d918 ||
stage1_rg_stage_input[104:98] == 7'h21 &&
stage1_rg_stage_input[134:130] == 5'd0 ||
stage1_rg_stage_input[104:98] == 7'h51 && rm__h10284 == 3'b010 ||
stage1_rg_stage_input[104:98] == 7'h51 &&
(rm__h10284 == 3'b001 || rm__h10284 == 3'b0) ||
stage1_rg_stage_input[104:98] == 7'h71 &&
stage1_rg_stage_input[134:130] == 5'd0 &&
rm__h10284 == 3'b001 ;
assign stage1_rg_stage_input_32_BITS_104_TO_98_38_EQ__ETC___d935 =
stage1_rg_stage_input_32_BITS_104_TO_98_38_EQ__ETC___d929 ||
stage1_rg_stage_input[104:98] == 7'h61 &&
(stage1_rg_stage_input[134:130] == 5'd0 ||
stage1_rg_stage_input[134:130] == 5'b00001) ||
stage1_rg_stage_input[104:98] == 7'h69 &&
stage1_rg_stage_input[134:130] == 5'd0 ;
assign stage1_rg_stage_input_32_BITS_112_TO_110_80_EQ_ETC___d1035 =
stage1_rg_stage_input[112:110] == 3'd0 &&
stage1_rg_stage_input[144:140] == 5'd0 &&
stage1_rg_stage_input[139:135] == 5'd0 &&
(stage1_rg_stage_input[263:260] == 4'b0 ||
stage1_rg_stage_input[263:260] == 4'b1000) ;
assign stage1_rg_stage_input_32_BITS_112_TO_110_80_EQ_ETC___d1049 =
stage1_rg_stage_input[112:110] == 3'b001 &&
stage1_rg_stage_input[144:140] == 5'd0 &&
stage1_rg_stage_input[139:135] == 5'd0 &&
stage1_rg_stage_input[87:76] == 12'b0 ;
assign stage1_rg_stage_input_32_BITS_112_TO_110_80_EQ_ETC___d806 =
stage1_rg_stage_input[112:110] == 3'd0 &&
(stage1_rg_stage_input[151:145] != 7'b0110011 ||
!stage1_rg_stage_input[262]) ||
stage1_rg_stage_input[112:110] == 3'd0 &&
stage1_rg_stage_input[151:145] == 7'b0110011 &&
stage1_rg_stage_input[262] ||
CASE_stage1_rg_stage_input_BITS_112_TO_110_0b1_ETC__q13 ;
assign stage1_rg_stage_input_32_BITS_144_TO_140_027_E_ETC___d1065 =
stage1_rg_stage_input[144:140] == 5'd0 &&
(rg_cur_priv == 2'b11 ||
rg_cur_priv == 2'b01 && !csr_regfile$read_mstatus[20]) &&
stage1_rg_stage_input[104:98] == 7'b0001001 ;
assign stage1_rg_stage_input_32_BITS_144_TO_140_027_E_ETC___d1103 =
stage1_rg_stage_input[144:140] == 5'd0 &&
stage1_rg_stage_input[139:135] == 5'd0 &&
(rg_cur_priv == 2'b11 ||
rg_cur_priv == 2'b01 && !csr_regfile$read_mstatus[22]) &&
stage1_rg_stage_input[87:76] == 12'b000100000010 ;
assign stage1_rg_stage_input_32_BITS_151_TO_145_78_EQ_ETC___d1341 =
stage1_rg_stage_input[151:145] == 7'b0110011 &&
stage1_rg_stage_input[104:98] == 7'b0000001 ||
stage1_rg_stage_input_32_BITS_151_TO_145_78_EQ_ETC___d794 ||
stage1_rg_stage_input[151:145] != 7'b0010011 &&
stage1_rg_stage_input[151:145] != 7'b0110011 &&
stage1_rg_stage_input[151:145] != 7'b0011011 &&
stage1_rg_stage_input[151:145] != 7'b0111011 &&
stage1_rg_stage_input[151:145] != 7'b0110111 &&
stage1_rg_stage_input[151:145] != 7'b0010111 ;
assign stage1_rg_stage_input_32_BITS_151_TO_145_78_EQ_ETC___d2892 =
stage1_rg_stage_input[151:145] == 7'b1110011 &&
stage1_rg_stage_input[112:110] == 3'd0 &&
(rg_cur_priv != 2'b11 &&
(rg_cur_priv != 2'b01 || csr_regfile$read_mstatus[20]) ||
stage1_rg_stage_input[104:98] != 7'b0001001) &&
stage1_rg_stage_input_32_BITS_144_TO_140_027_E_ETC___d1103 ;
assign stage1_rg_stage_input_32_BITS_151_TO_145_78_EQ_ETC___d794 =
stage1_rg_stage_input[151:145] == 7'b0111011 &&
stage1_rg_stage_input[104:98] == 7'b0000001 &&
stage1_rg_stage_input[112:110] != 3'b001 &&
stage1_rg_stage_input[112:110] != 3'b010 &&
stage1_rg_stage_input[112:110] != 3'b011 ;
assign stage1_rg_stage_input_32_BITS_151_TO_145_78_EQ_ETC___d962 =
stage1_rg_stage_input[151:145] == 7'b0110011 &&
stage1_rg_stage_input[104:98] == 7'b0000001 ||
stage1_rg_stage_input_32_BITS_151_TO_145_78_EQ_ETC___d794 ||
(((stage1_rg_stage_input[151:145] == 7'b0010011 ||
stage1_rg_stage_input[151:145] == 7'b0110011) &&
(stage1_rg_stage_input[112:110] == 3'b001 ||
stage1_rg_stage_input[112:110] == 3'b101)) ?
!stage1_rg_stage_input[263] &&
stage1_rg_stage_input[261:258] == 4'b0 :
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d960) ;
assign stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d1398 =
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1379 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1350 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1360 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1395 ;
assign stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d1588 =
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d778 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d985 &&
!stage1_rg_stage_input[332] &&
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d965 ;
assign stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d2343 =
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
(stage1_rg_stage_input[332] ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d763 &&
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d775) ;
assign stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d2626 =
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
IF_NOT_stage1_rg_full_31_76_OR_NOT_stage1_rg_s_ETC___d2405 &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1379 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1350 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1360 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1395 ;
assign stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 =
stage1_rg_stage_input[335:334] == rg_epoch ;
assign stage1_rg_stage_input_32_BITS_99_TO_98_74_EQ_0_ETC___d2440 =
(stage1_rg_stage_input[99:98] == 2'b0 ||
stage1_rg_stage_input[99:98] == 2'b01) &&
(stage1_rg_stage_input[151:145] == 7'b1000011 ||
stage1_rg_stage_input[151:145] == 7'b1000111 ||
stage1_rg_stage_input[151:145] == 7'b1001111 ||
stage1_rg_stage_input[151:145] == 7'b1001011) ||
stage1_rg_stage_input_32_BITS_104_TO_98_38_EQ__ETC___d2427 ||
stage1_rg_stage_input[104:98] == 7'h68 &&
(stage1_rg_stage_input[134:130] == 5'b00010 ||
stage1_rg_stage_input[134:130] == 5'b00011) ||
stage1_rg_stage_input_32_BITS_104_TO_98_38_EQ__ETC___d918 ||
stage1_rg_stage_input[104:98] == 7'h21 &&
stage1_rg_stage_input[134:130] == 5'd0 ||
stage1_rg_stage_input[104:98] == 7'h69 &&
stage1_rg_stage_input[134:130] == 5'd0 ||
stage1_rg_stage_input[104:98] == 7'h69 &&
stage1_rg_stage_input[134:130] == 5'b00001 ;
assign stage1_rg_stage_input_32_BITS_99_TO_98_74_EQ_0_ETC___d938 =
(stage1_rg_stage_input[99:98] == 2'b0 ||
stage1_rg_stage_input[99:98] == 2'b01) &&
(stage1_rg_stage_input[151:145] == 7'b1000011 ||
stage1_rg_stage_input[151:145] == 7'b1000111 ||
stage1_rg_stage_input[151:145] == 7'b1001111 ||
stage1_rg_stage_input[151:145] == 7'b1001011) ||
stage1_rg_stage_input_32_BITS_104_TO_98_38_EQ__ETC___d893 ||
(stage1_rg_stage_input[104:98] == 7'h60 ||
stage1_rg_stage_input[104:98] == 7'h68) &&
(stage1_rg_stage_input[134:130] == 5'b00010 ||
stage1_rg_stage_input[134:130] == 5'b00011) ||
stage1_rg_stage_input_32_BITS_104_TO_98_38_EQ__ETC___d935 ||
stage1_rg_stage_input[104:98] == 7'h69 &&
stage1_rg_stage_input[134:130] == 5'b00001 ;
assign stage1_rg_stage_input_32_BIT_332_77_OR_NOT_rg__ETC___d1096 =
stage1_rg_stage_input[332] ||
rg_cur_priv != 2'b11 &&
(rg_cur_priv != 2'b01 || csr_regfile$read_mstatus[20]) ||
stage1_rg_stage_input[104:98] != 7'b0001001 ;
assign stage1_rg_stage_input_BITS_30_TO_10__q1 =
stage1_rg_stage_input[30:10] ;
assign stage1_rg_stage_input_BITS_63_TO_51__q2 =
stage1_rg_stage_input[63:51] ;
assign stage1_rg_stage_input_BITS_75_TO_64__q6 =
stage1_rg_stage_input[75:64] ;
assign stage1_rg_stage_input_BITS_87_TO_76__q17 =
stage1_rg_stage_input[87:76] ;
assign stage2_rg_full_14_AND_IF_stage2_rg_stage2_15_B_ETC___d2379 =
stage2_rg_full &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d2299 &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56 &&
stage2_rg_stage2[397:395] != 3'd0 &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d175 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1006 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[332] ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d775) &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d985 &&
NOT_stage1_rg_stage_input_32_BIT_332_77_83_AND_ETC___d1004 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1007 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[332] ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d763) &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1006 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1009 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d965 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d969) &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1007 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1021 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[332] ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d775) &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d985 &&
NOT_stage1_rg_stage_input_32_BIT_332_77_83_AND_ETC___d1019 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1022 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[332] ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d763) &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1021 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1024 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d965 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d969) &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1022 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1039 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[332] ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d775) &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d985 &&
!stage1_rg_stage_input[332] &&
stage1_rg_stage_input[151:145] == 7'b0001111 &&
stage1_rg_stage_input_32_BITS_112_TO_110_80_EQ_ETC___d1035 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1040 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[332] ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d763) &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1039 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1042 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d965 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d969) &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1040 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1053 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[332] ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d775) &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d985 &&
!stage1_rg_stage_input[332] &&
stage1_rg_stage_input[151:145] == 7'b0001111 &&
stage1_rg_stage_input_32_BITS_112_TO_110_80_EQ_ETC___d1049 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1054 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[332] ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d763) &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1053 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1056 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d965 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d969) &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1054 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1070 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[332] ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d775) &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d985 &&
NOT_stage1_rg_stage_input_32_BIT_332_77_83_AND_ETC___d1068 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1071 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[332] ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d763) &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1070 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1073 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d965 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d969) &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1071 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1085 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[332] ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d775) &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d985 &&
!stage1_rg_stage_input[332] &&
stage1_rg_stage_input[151:145] == 7'b1110011 &&
stage1_rg_stage_input[112:110] == 3'd0 &&
stage1_rg_stage_input[104:98] != 7'b0001001 &&
stage1_rg_stage_input[144:140] == 5'd0 &&
stage1_rg_stage_input[139:135] == 5'd0 &&
rg_cur_priv == 2'b11 &&
stage1_rg_stage_input[87:76] == 12'b001100000010 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1086 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[332] ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d763) &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1085 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1088 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d965 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d969) &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1086 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1109 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input_32_BIT_332_77_OR_NOT_rg__ETC___d1096) &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d985 &&
!stage1_rg_stage_input[332] &&
stage1_rg_stage_input[151:145] == 7'b1110011 &&
stage1_rg_stage_input[112:110] == 3'd0 &&
NOT_rg_cur_priv_8_EQ_0b11_059_091_AND_NOT_rg_c_ETC___d1104 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1110 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[332] ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d775) &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1109 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1111 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[332] ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d763) &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1110 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1113 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d965 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d969) &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1111 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1131 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input_32_BIT_332_77_OR_NOT_rg__ETC___d1096) &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d985 &&
NOT_stage1_rg_stage_input_32_BIT_332_77_83_AND_ETC___d1129 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1132 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[332] ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d775) &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1131 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1133 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[332] ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d763) &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1132 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1135 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d965 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d969) &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1133 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1208 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[332] ||
stage1_rg_stage_input[151:145] != 7'b1110011 ||
stage1_rg_stage_input[112:110] != 3'd0 ||
rg_cur_priv_8_EQ_0b11_059_OR_rg_cur_priv_8_EQ__ETC___d1189) &&
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[332] ||
stage1_rg_stage_input[151:145] != 7'b1110011 ||
stage1_rg_stage_input[112:110] != 3'd0 ||
rg_cur_priv_8_EQ_0b11_059_OR_rg_cur_priv_8_EQ__ETC___d1203) ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1209 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[332] ||
stage1_rg_stage_input[151:145] != 7'b1110011 ||
stage1_rg_stage_input[112:110] != 3'd0 ||
stage1_rg_stage_input[104:98] == 7'b0001001 ||
stage1_rg_stage_input[144:140] != 5'd0 ||
stage1_rg_stage_input[139:135] != 5'd0 ||
rg_cur_priv != 2'b11 ||
stage1_rg_stage_input[87:76] != 12'b001100000010) &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1208 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1210 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[332] ||
stage1_rg_stage_input[151:145] != 7'b1110011 ||
stage1_rg_stage_input[112:110] != 3'd0 ||
NOT_stage1_rg_stage_input_32_BITS_144_TO_140_0_ETC___d1169) &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1209 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1213 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[332] ||
stage1_rg_stage_input[151:145] != 7'b1110011 ||
stage1_rg_stage_input[112:110] != 3'b010 &&
stage1_rg_stage_input[112:110] != 3'b110 &&
stage1_rg_stage_input[112:110] != 3'b011 &&
stage1_rg_stage_input[112:110] != 3'b111) &&
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[332] ||
stage1_rg_stage_input[151:145] != 7'b0001111 ||
NOT_stage1_rg_stage_input_32_BITS_112_TO_110_8_ETC___d1157) &&
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[332] ||
stage1_rg_stage_input[151:145] != 7'b0001111 ||
NOT_stage1_rg_stage_input_32_BITS_112_TO_110_8_ETC___d1164) &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1210 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1214 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[332] ||
stage1_rg_stage_input[151:145] != 7'b1110011 ||
stage1_rg_stage_input[112:110] != 3'b001 &&
stage1_rg_stage_input[112:110] != 3'b101) &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1213 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1215 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[332] ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d775) &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1214 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1216 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[332] ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d763) &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1215 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1278 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d965 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d969) &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375 &&
!stage1_rg_stage_input[332] &&
stage1_rg_stage_input[151:145] == 7'b1100111 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1332 =
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d985 &&
(stage1_rg_stage_input[151:145] == 7'b0100011 ||
stage1_rg_stage_input[151:145] == 7'b0100111) ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1350 =
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[151:145] != 7'b0000011 &&
stage1_rg_stage_input[151:145] != 7'b0000111 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1360 =
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[151:145] != 7'b0100011 &&
stage1_rg_stage_input[151:145] != 7'b0100111 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1365 =
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1360 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d985 &&
stage1_rg_stage_input[151:145] != 7'b1100011 &&
stage1_rg_stage_input[151:145] != 7'b1101111 &&
stage1_rg_stage_input[151:145] != 7'b1100111 &&
(stage1_rg_stage_input[151:145] == 7'b0110011 &&
stage1_rg_stage_input[104:98] == 7'b0000001 ||
stage1_rg_stage_input_32_BITS_151_TO_145_78_EQ_ETC___d794) ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1368 =
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d972 &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input_32_BITS_151_TO_145_78_EQ_ETC___d1341) &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1350 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1365 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1379 =
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[151:145] != 7'b1100011 &&
stage1_rg_stage_input[151:145] != 7'b1101111 &&
stage1_rg_stage_input[151:145] != 7'b1100111 &&
stage1_rg_stage_input_32_BITS_151_TO_145_78_EQ_ETC___d1341 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1395 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[151:145] == 7'b1100011 ||
stage1_rg_stage_input[151:145] == 7'b1101111 ||
stage1_rg_stage_input[151:145] == 7'b1100111 ||
(stage1_rg_stage_input[151:145] != 7'b0110011 ||
stage1_rg_stage_input[104:98] != 7'b0000001) &&
NOT_stage1_rg_stage_input_32_BITS_151_TO_145_7_ETC___d449) &&
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[151:145] != 7'b0101111) ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1555 =
stage2_rg_full && stage2_rg_stage2[397:395] != 3'd0 &&
stage2_rg_stage2[397:395] != 3'd1 &&
stage2_rg_stage2[397:395] != 3'd4 &&
stage2_rg_stage2[397:395] != 3'd2 &&
stage2_rg_stage2[397:395] != 3'd3 &&
stage2_rg_stage2[5] &&
stage2_fbox$valid ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d2295 =
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input[332] ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d763 &&
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d775 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d2614 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
stage1_rg_stage_input_32_BITS_151_TO_145_78_EQ_ETC___d1341) &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1350 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1365 ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 =
stage2_rg_full && stage2_rg_stage2[397:395] != 3'd0 &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d290 &&
(IF_stage2_rg_full_14_THEN_IF_stage2_rg_stage2__ETC___d337 ||
IF_stage2_rg_full_14_THEN_IF_stage2_rg_stage2__ETC___d339) ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 =
stage2_rg_full && stage2_rg_stage2[397:395] != 3'd0 &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d319 &&
(IF_NOT_stage2_rg_full_14_71_OR_stage2_rg_stage_ETC___d343 ||
IF_NOT_stage2_rg_full_14_71_OR_stage2_rg_stage_ETC___d344 ||
IF_NOT_stage2_rg_full_14_71_OR_stage2_rg_stage_ETC___d347) ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d972 =
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
!stage1_rg_stage_input[332] &&
(IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d965 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d969) ;
assign stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d995 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d341 ||
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d349 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d763) &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d985 &&
!stage1_rg_stage_input[332] &&
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d969 ;
assign stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d170 =
stage2_rg_full &&
(stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152) &&
stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_0_17_ETC___d168 ;
assign stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d2376 =
stage2_rg_full &&
(stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d2299) &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56 ;
assign stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d2381 =
stage2_rg_full &&
(stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d2299) &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56 &&
(stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d184) ;
assign stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d2383 =
stage2_rg_full &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d2299 &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56 &&
stage2_rg_stage2[397:395] != 3'd0 &&
stage2_rg_stage2[397:395] != 3'd1 &&
stage2_rg_stage2[397:395] != 3'd4 &&
stage2_rg_stage2[397:395] != 3'd2 &&
stage2_rg_stage2[397:395] != 3'd3 ;
assign stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d2385 =
stage2_rg_full &&
(stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d2299) &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56 &&
(stage2_rg_stage2[397:395] == 3'd0 ||
stage2_rg_stage2[397:395] == 3'd1 ||
stage2_rg_stage2[397:395] == 3'd4 ||
stage2_rg_stage2[397:395] == 3'd2 ||
stage2_rg_stage2[397:395] == 3'd3) ;
assign stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d2387 =
stage2_rg_full &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d2299 &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56 &&
stage2_rg_stage2[397:395] != 3'd0 &&
CASE_stage2_rg_stage2_BITS_397_TO_395_1_stage2_ETC__q4 ;
assign stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d2389 =
stage2_rg_full &&
(stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d2299) &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56 &&
(stage2_rg_stage2[397:395] == 3'd0 ||
CASE_stage2_rg_stage2_BITS_397_TO_395_1_NOT_st_ETC__q5) ;
assign stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d2395 =
stage2_rg_full &&
(stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d2299) &&
(cur_verbosity__h3946 != 4'd0 ||
csr_regfile$read_csr_minstret[19:0] == 20'd0) ;
assign stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d405 =
stage2_rg_full &&
(stage2_rg_stage2[397:395] == 3'd0 ||
stage2_rg_stage2[397:395] != 3'd1 &&
stage2_rg_stage2[397:395] != 3'd4 &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d402) ;
assign stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_0_17_ETC___d168 =
stage2_rg_stage2[397:395] != 3'd1 &&
stage2_rg_stage2[397:395] != 3'd4 &&
stage2_rg_stage2[397:395] != 3'd2 ||
!near_mem$dmem_valid ||
!near_mem$dmem_exc ;
assign stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_0_17_ETC___d215 =
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152 &&
stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_0_17_ETC___d168 &&
stage2_rg_stage2[397:395] != 3'd0 &&
CASE_stage2_rg_stage2_BITS_397_TO_395_1_stage2_ETC__q4 ;
assign stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_0_17_ETC___d244 =
(stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152) &&
stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_0_17_ETC___d168 &&
(stage2_rg_stage2[397:395] == 3'd0 ||
CASE_stage2_rg_stage2_BITS_397_TO_395_1_NOT_st_ETC__q5) ;
assign stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_2_21_ETC___d296 =
stage2_rg_stage2[397:395] == 3'd2 ||
((stage2_rg_stage2[397:395] == 3'd3) ?
stage2_mbox$valid :
stage2_rg_stage2[5] || stage2_fbox$valid) ;
assign stage3_rg_full_8_OR_NOT_stage2_rg_full_14_71_O_ETC___d2337 =
(stage3_rg_full || !stage2_rg_full ||
stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_0_17_ETC___d168) &&
(stage3_rg_full || stage2_rg_full || !stage1_rg_full ||
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d2334) ;
assign stage3_rg_stage3_00_BITS_139_TO_135_09_EQ_stag_ETC___d407 =
stage3_rg_stage3[139:135] == stage1_rg_stage_input[139:135] ;
assign stage3_rg_stage3_00_BITS_139_TO_135_09_EQ_stag_ETC___d415 =
stage3_rg_stage3[139:135] == stage1_rg_stage_input[134:130] ;
assign stageF_f_reset_rsps_i_notEmpty__241_AND_stageD_ETC___d2261 =
stageF_f_reset_rsps$EMPTY_N && stageD_f_reset_rsps$EMPTY_N &&
stage1_f_reset_rsps$EMPTY_N &&
stage2_f_reset_rsps$EMPTY_N &&
stage3_f_reset_rsps$EMPTY_N &&
f_reset_rsps$FULL_N &&
NOT_rg_run_on_reset_247_248_OR_imem_rg_pc_BITS_ETC___d2255 ;
assign stageF_rg_full_094_AND_near_mem_imem_valid_AND_ETC___d2126 =
stageF_rg_full && near_mem$imem_valid &&
near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d2119 &&
!near_mem$imem_exc ;
assign sxl__h6937 =
(csr_regfile$read_misa[27:26] == 2'd2) ?
csr_regfile$read_mstatus[35:34] :
2'd0 ;
assign tmp__h16821 =
rs1_val_bypassed__h5597[31:0] >> stage1_rg_stage_input[80:76] |
~(32'hFFFFFFFF >> stage1_rg_stage_input[80:76]) &
{32{rs1_val_bypassed597_BITS_31_TO_0__q7[31]}} ;
assign trap_info_tval__h15117 =
(stage1_rg_stage_input[151:145] != 7'b1101111 &&
stage1_rg_stage_input[151:145] != 7'b1100111 &&
(stage1_rg_stage_input[151:145] != 7'b1110011 ||
stage1_rg_stage_input[112:110] != 3'd0 ||
rg_cur_priv_8_EQ_0b11_059_OR_rg_cur_priv_8_EQ__ETC___d1635)) ?
(stage1_rg_stage_input[333] ?
{ 32'd0, stage1_rg_stage_input[263:232] } :
{ 48'd0, stage1_rg_stage_input[231:216] }) :
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q20 ;
assign uxl__h6938 =
(csr_regfile$read_misa[27:26] == 2'd2) ?
csr_regfile$read_mstatus[33:32] :
2'd0 ;
assign v32__h10610 = { stage1_rg_stage_input[50:31], 12'h0 } ;
assign val__h9686 =
(stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d405 &&
IF_stage2_rg_full_14_THEN_IF_stage2_rg_stage2__ETC___d337) ?
x_out_bypass_rd_val__h9272 :
rd_val__h9684 ;
assign val__h9719 =
(stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d405 &&
IF_stage2_rg_full_14_THEN_IF_stage2_rg_stage2__ETC___d339) ?
x_out_bypass_rd_val__h9272 :
rd_val__h9717 ;
assign value__h15187 =
stage1_rg_stage_input[332] ?
stage1_rg_stage_input[327:264] :
trap_info_tval__h15117 ;
assign x__h16764 =
rs1_val_bypassed__h5597[31:0] << stage1_rg_stage_input[80:76] ;
assign x__h16796 =
rs1_val_bypassed__h5597[31:0] >> stage1_rg_stage_input[80:76] ;
assign x__h16931 =
rs1_val_bypassed__h5597[31:0] << rs2_val_bypassed__h5603[4:0] ;
assign x__h16976 =
rs1_val_bypassed__h5597[31:0] >> rs2_val_bypassed__h5603[4:0] ;
assign x__h33878 =
csr_regfile_read_csr_mcycle__7_MINUS_rg_start__ETC___d2801[63:0] /
_theResult____h33877 ;
assign x_exc_code__h44308 =
(csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending) ?
csr_regfile$interrupt_pending[3:0] :
4'd0 ;
assign x_out_cf_info_fallthru_PC__h16274 =
stage1_rg_stage_input[333] ?
next_pc__h13964 :
next_pc___1__h13967 ;
assign x_out_data_to_stage1_instr__h17651 =
stageD_rg_data[165] ? stageD_rg_data[95:64] : instr___1__h17725 ;
assign x_out_data_to_stage2_fval1__h10123 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1555 &&
IF_NOT_stage2_rg_full_14_71_OR_stage2_rg_stage_ETC___d343) ?
x_out_fbypass_rd_val__h9454 :
rd_val__h9750 ;
assign x_out_data_to_stage2_fval3__h10125 =
(stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1555 &&
IF_NOT_stage2_rg_full_14_71_OR_stage2_rg_stage_ETC___d347) ?
x_out_fbypass_rd_val__h9454 :
rd_val__h9815 ;
assign x_out_data_to_stage2_rd__h10119 =
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 ?
data_to_stage2_rd__h10102 :
5'd0 ;
assign x_out_data_to_stage2_val2__h10122 =
(stage1_rg_stage_input[151:145] == 7'b1100011) ?
branch_target__h10301 :
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d1531 ;
assign x_out_next_pc__h9864 =
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d969 ?
data_to_stage2_addr__h10103 :
fall_through_pc__h9846 ;
assign x_out_trap_info_exc_code__h15122 =
stage1_rg_stage_input[332] ?
stage1_rg_stage_input[331:328] :
alu_outputs_exc_code__h11737 ;
assign y__h35607 = ~rs1_val__h35329 ;
always@(stage2_rg_stage2)
begin
case (stage2_rg_stage2[397:395])
3'd1, 3'd2, 3'd4: value__h8670 = stage2_rg_stage2[493:430];
default: value__h8670 = stage2_rg_stage2[493:430];
endcase
end
always@(stage2_rg_stage2 or near_mem$dmem_exc_code)
begin
case (stage2_rg_stage2[397:395])
3'd1, 3'd2, 3'd4:
x_out_trap_info_exc_code__h8780 = near_mem$dmem_exc_code;
default: x_out_trap_info_exc_code__h8780 = 4'd2;
endcase
end
always@(stage2_rg_stage2)
begin
case (stage2_rg_stage2[397:395])
3'd1, 3'd2, 3'd4: value__h8884 = stage2_rg_stage2[389:326];
default: value__h8884 = 64'd0;
endcase
end
always@(stage2_rg_stage2 or stage2_fbox$word_snd)
begin
case (stage2_rg_stage2[397:395])
3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
x_out_data_to_stage3_fpr_flags__h8344 = 5'd0;
default: x_out_data_to_stage3_fpr_flags__h8344 = stage2_fbox$word_snd;
endcase
end
always@(stage2_rg_stage2)
begin
case (stage2_rg_stage2[397:395])
3'd0, 3'd1, 3'd4:
x_out_data_to_stage3_rd__h8340 = stage2_rg_stage2[394:390];
3'd2: x_out_data_to_stage3_rd__h8340 = 5'd0;
default: x_out_data_to_stage3_rd__h8340 = stage2_rg_stage2[394:390];
endcase
end
always@(stage2_rg_stage2)
begin
case (stage2_rg_stage2[397:395])
3'd0, 3'd1, 3'd4: x_out_bypass_rd__h9271 = stage2_rg_stage2[394:390];
default: x_out_bypass_rd__h9271 = stage2_rg_stage2[394:390];
endcase
end
always@(stage2_rg_stage2)
begin
case (stage2_rg_stage2[397:395])
3'd1, 3'd4: x_out_fbypass_rd__h9453 = stage2_rg_stage2[394:390];
default: x_out_fbypass_rd__h9453 = stage2_rg_stage2[394:390];
endcase
end
always@(rg_trap_instr or rg_csr_val1)
begin
case (rg_trap_instr[14:12])
3'b010, 3'b011: rs1_val__h35329 = rg_csr_val1;
default: rs1_val__h35329 = { 59'd0, rg_trap_instr[19:15] };
endcase
end
always@(stage2_rg_stage2 or
stage2_fbox$word_fst or
output_stage2___1_data_to_stage3_frd_val__h8219)
begin
case (stage2_rg_stage2[397:395])
3'd0, 3'd2, 3'd3:
x_out_data_to_stage3_frd_val__h8345 = stage2_rg_stage2[197:134];
3'd1, 3'd4:
x_out_data_to_stage3_frd_val__h8345 =
output_stage2___1_data_to_stage3_frd_val__h8219;
default: x_out_data_to_stage3_frd_val__h8345 = stage2_fbox$word_fst;
endcase
end
always@(stage2_rg_stage2 or
_theResult___snd_snd_rd_val__h8290 or
near_mem$dmem_word64 or stage2_mbox$word)
begin
case (stage2_rg_stage2[397:395])
3'd0, 3'd2:
x_out_data_to_stage3_rd_val__h8341 = stage2_rg_stage2[325:262];
3'd1, 3'd4: x_out_data_to_stage3_rd_val__h8341 = near_mem$dmem_word64;
3'd3: x_out_data_to_stage3_rd_val__h8341 = stage2_mbox$word;
default: x_out_data_to_stage3_rd_val__h8341 =
_theResult___snd_snd_rd_val__h8290;
endcase
end
always@(stage2_rg_stage2 or
_theResult___snd_snd_rd_val__h8290 or stage2_mbox$word)
begin
case (stage2_rg_stage2[397:395])
3'd0, 3'd1, 3'd4:
x_out_bypass_rd_val__h9272 = stage2_rg_stage2[325:262];
3'd3: x_out_bypass_rd_val__h9272 = stage2_mbox$word;
default: x_out_bypass_rd_val__h9272 =
_theResult___snd_snd_rd_val__h8290;
endcase
end
always@(stage2_rg_stage2 or _theResult___snd_fst_rd_val__h9435)
begin
case (stage2_rg_stage2[397:395])
3'd1, 3'd4: x_out_fbypass_rd_val__h9454 = stage2_rg_stage2[197:134];
default: x_out_fbypass_rd_val__h9454 =
_theResult___snd_fst_rd_val__h9435;
endcase
end
always@(stage1_rg_stage_input)
begin
case (stage1_rg_stage_input[151:145])
7'b0000011,
7'b0000111,
7'b0010011,
7'b0010111,
7'b0011011,
7'b0110011,
7'b0110111,
7'b0111011,
7'b1100111,
7'b1101111:
data_to_stage2_rd__h10102 = stage1_rg_stage_input[144:140];
7'b1100011: data_to_stage2_rd__h10102 = 5'd0;
default: data_to_stage2_rd__h10102 = stage1_rg_stage_input[144:140];
endcase
end
always@(stage2_rg_stage2 or
stage2_fbox$valid or near_mem$dmem_valid or stage2_mbox$valid)
begin
case (stage2_rg_stage2[397:395])
3'd1, 3'd2, 3'd4:
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152 =
near_mem$dmem_valid;
3'd3:
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152 =
stage2_mbox$valid;
default: IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152 =
stage2_fbox$valid;
endcase
end
always@(stage2_rg_stage2 or
stage2_fbox$valid or near_mem$dmem_valid or stage2_mbox$valid)
begin
case (stage2_rg_stage2[397:395])
3'd1, 3'd2, 3'd4:
CASE_stage2_rg_stage2_BITS_397_TO_395_1_NOT_ne_ETC__q3 =
!near_mem$dmem_valid;
3'd3:
CASE_stage2_rg_stage2_BITS_397_TO_395_1_NOT_ne_ETC__q3 =
!stage2_mbox$valid;
default: CASE_stage2_rg_stage2_BITS_397_TO_395_1_NOT_ne_ETC__q3 =
!stage2_fbox$valid;
endcase
end
always@(stage2_rg_stage2 or
stage2_fbox$valid or
near_mem$dmem_valid or near_mem$dmem_exc or stage2_mbox$valid)
begin
case (stage2_rg_stage2[397:395])
3'd1, 3'd2, 3'd4:
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d175 =
!near_mem$dmem_valid || near_mem$dmem_exc;
3'd3:
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d175 =
!stage2_mbox$valid;
default: IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d175 =
stage2_rg_stage2[397:395] == 3'd5 && !stage2_fbox$valid;
endcase
end
always@(stage2_rg_stage2 or
stage2_fbox$valid or
near_mem$dmem_valid or near_mem$dmem_exc or stage2_mbox$valid)
begin
case (stage2_rg_stage2[397:395])
3'd1, 3'd2, 3'd4:
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d184 =
near_mem$dmem_valid && !near_mem$dmem_exc;
3'd3:
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d184 =
stage2_mbox$valid;
default: IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d184 =
stage2_rg_stage2[397:395] != 3'd5 || stage2_fbox$valid;
endcase
end
always@(stage2_rg_stage2)
begin
case (stage2_rg_stage2[397:395])
3'd1, 3'd4:
CASE_stage2_rg_stage2_BITS_397_TO_395_1_stage2_ETC__q4 =
stage2_rg_stage2[5];
default: CASE_stage2_rg_stage2_BITS_397_TO_395_1_stage2_ETC__q4 =
stage2_rg_stage2[397:395] != 3'd2 &&
stage2_rg_stage2[397:395] != 3'd3 &&
stage2_rg_stage2[5];
endcase
end
always@(stage2_rg_stage2)
begin
case (stage2_rg_stage2[397:395])
3'd1, 3'd4:
CASE_stage2_rg_stage2_BITS_397_TO_395_1_NOT_st_ETC__q5 =
!stage2_rg_stage2[5];
default: CASE_stage2_rg_stage2_BITS_397_TO_395_1_NOT_st_ETC__q5 =
stage2_rg_stage2[397:395] == 3'd2 ||
stage2_rg_stage2[397:395] == 3'd3 ||
!stage2_rg_stage2[5];
endcase
end
always@(stage2_rg_stage2 or near_mem$dmem_valid or near_mem$dmem_exc)
begin
case (stage2_rg_stage2[397:395])
3'd1, 3'd4:
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d273 =
near_mem$dmem_valid && near_mem$dmem_exc ||
stage2_rg_stage2[394:390] == 5'd0;
default: IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d273 =
stage2_rg_stage2[397:395] == 3'd2 ||
stage2_rg_stage2[397:395] != 3'd3 && stage2_rg_stage2[5];
endcase
end
always@(stage2_rg_stage2 or near_mem$dmem_valid or near_mem$dmem_exc)
begin
case (stage2_rg_stage2[397:395])
3'd1, 3'd4:
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d279 =
(!near_mem$dmem_valid || !near_mem$dmem_exc) &&
stage2_rg_stage2[394:390] != 5'd0;
default: IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d279 =
stage2_rg_stage2[397:395] != 3'd2 &&
(stage2_rg_stage2[397:395] == 3'd3 ||
!stage2_rg_stage2[5]);
endcase
end
always@(stage2_rg_stage2 or
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d289 or
near_mem$dmem_valid or near_mem$dmem_exc)
begin
case (stage2_rg_stage2[397:395])
3'd1, 3'd4:
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d290 =
(!near_mem$dmem_valid || !near_mem$dmem_exc) &&
stage2_rg_stage2[394:390] != 5'd0;
default: IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d290 =
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d289;
endcase
end
always@(stage2_rg_stage2 or
stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_2_21_ETC___d296 or
near_mem$dmem_valid or near_mem$dmem_exc)
begin
case (stage2_rg_stage2[397:395])
3'd1, 3'd4:
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d297 =
near_mem$dmem_valid && near_mem$dmem_exc ||
stage2_rg_stage2[394:390] == 5'd0;
default: IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d297 =
stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_2_21_ETC___d296;
endcase
end
always@(stage2_rg_stage2 or near_mem$dmem_valid or near_mem$dmem_exc)
begin
case (stage2_rg_stage2[397:395])
3'd1, 3'd4:
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d305 =
near_mem$dmem_valid && near_mem$dmem_exc ||
!stage2_rg_stage2[5];
default: IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d305 =
stage2_rg_stage2[397:395] == 3'd2 ||
stage2_rg_stage2[397:395] == 3'd3 ||
!stage2_rg_stage2[5];
endcase
end
always@(stage2_rg_stage2 or near_mem$dmem_valid or near_mem$dmem_exc)
begin
case (stage2_rg_stage2[397:395])
3'd1, 3'd4:
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d310 =
(!near_mem$dmem_valid || !near_mem$dmem_exc) &&
stage2_rg_stage2[5];
default: IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d310 =
stage2_rg_stage2[397:395] != 3'd2 &&
stage2_rg_stage2[397:395] != 3'd3 &&
stage2_rg_stage2[5];
endcase
end
always@(stage2_rg_stage2 or
stage2_fbox$valid or near_mem$dmem_valid or near_mem$dmem_exc)
begin
case (stage2_rg_stage2[397:395])
3'd1, 3'd4:
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d324 =
near_mem$dmem_valid && near_mem$dmem_exc ||
!stage2_rg_stage2[5];
default: IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d324 =
stage2_rg_stage2[397:395] == 3'd2 ||
stage2_rg_stage2[397:395] == 3'd3 ||
!stage2_rg_stage2[5] ||
stage2_fbox$valid;
endcase
end
always@(stage2_rg_stage2 or
stage2_fbox$valid or near_mem$dmem_valid or near_mem$dmem_exc)
begin
case (stage2_rg_stage2[397:395])
3'd1, 3'd4:
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d319 =
(!near_mem$dmem_valid || !near_mem$dmem_exc) &&
stage2_rg_stage2[5];
default: IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d319 =
stage2_rg_stage2[397:395] != 3'd2 &&
stage2_rg_stage2[397:395] != 3'd3 &&
stage2_rg_stage2[5] &&
!stage2_fbox$valid;
endcase
end
always@(stage1_rg_stage_input or
_theResult___fst__h12794 or
rd_val___1__h16874 or
rd_val___1__h16928 or rd_val___1__h16973 or rd_val___1__h16922)
begin
case (stage1_rg_stage_input[97:88])
10'b0: alu_outputs___1_val1__h10598 = rd_val___1__h16874;
10'b0000000001: alu_outputs___1_val1__h10598 = rd_val___1__h16928;
10'b0000000101: alu_outputs___1_val1__h10598 = rd_val___1__h16973;
10'b0100000000: alu_outputs___1_val1__h10598 = rd_val___1__h16922;
default: alu_outputs___1_val1__h10598 = _theResult___fst__h12794;
endcase
end
always@(stage1_rg_stage_input or
IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d425 or
IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d421 or
IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d423)
begin
case (stage1_rg_stage_input[112:110])
3'd0:
IF_stage1_rg_stage_input_32_BITS_112_TO_110_80_ETC___d769 =
!IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d421;
3'b001:
IF_stage1_rg_stage_input_32_BITS_112_TO_110_80_ETC___d769 =
IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d421;
3'b100:
IF_stage1_rg_stage_input_32_BITS_112_TO_110_80_ETC___d769 =
!IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d423;
3'b101:
IF_stage1_rg_stage_input_32_BITS_112_TO_110_80_ETC___d769 =
IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d423;
3'b110:
IF_stage1_rg_stage_input_32_BITS_112_TO_110_80_ETC___d769 =
!IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d425;
default: IF_stage1_rg_stage_input_32_BITS_112_TO_110_80_ETC___d769 =
stage1_rg_stage_input[112:110] != 3'b111 ||
IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d425;
endcase
end
always@(stage1_rg_stage_input or
IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d425 or
IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d421 or
IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d423)
begin
case (stage1_rg_stage_input[112:110])
3'd0:
IF_stage1_rg_stage_input_32_BITS_112_TO_110_80_ETC___d432 =
IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d421;
3'b001:
IF_stage1_rg_stage_input_32_BITS_112_TO_110_80_ETC___d432 =
!IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d421;
3'b100:
IF_stage1_rg_stage_input_32_BITS_112_TO_110_80_ETC___d432 =
IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d423;
3'b101:
IF_stage1_rg_stage_input_32_BITS_112_TO_110_80_ETC___d432 =
!IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d423;
3'b110:
IF_stage1_rg_stage_input_32_BITS_112_TO_110_80_ETC___d432 =
IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d425;
default: IF_stage1_rg_stage_input_32_BITS_112_TO_110_80_ETC___d432 =
stage1_rg_stage_input[112:110] == 3'b111 &&
!IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d425;
endcase
end
always@(stage1_rg_stage_input)
begin
case (stage1_rg_stage_input[112:110])
3'b010, 3'b011, 3'b100, 3'b110:
CASE_stage1_rg_stage_input_BITS_112_TO_110_0b1_ETC__q11 =
stage1_rg_stage_input[151:145] != 7'b0010011 &&
stage1_rg_stage_input[263] &&
stage1_rg_stage_input[262] &&
stage1_rg_stage_input[261:257] != 5'b0;
default: CASE_stage1_rg_stage_input_BITS_112_TO_110_0b1_ETC__q11 =
stage1_rg_stage_input[112:110] != 3'b111 ||
stage1_rg_stage_input[151:145] != 7'b0010011 &&
stage1_rg_stage_input[263] &&
stage1_rg_stage_input[262] &&
stage1_rg_stage_input[261:257] != 5'b0;
endcase
end
always@(stage1_rg_stage_input or
csr_regfile_read_mstatus__9_BITS_14_TO_13_1_EQ_ETC___d573 or
NOT_stage1_rg_stage_input_32_BITS_99_TO_98_74__ETC___d734 or
NOT_stage1_rg_stage_input_32_BITS_104_TO_98_38_ETC___d746 or
csr_regfile$read_mstatus or
NOT_stage1_rg_stage_input_32_BITS_109_TO_105_2_ETC___d559)
begin
case (stage1_rg_stage_input[151:145])
7'b0000111, 7'b0100111:
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d750 =
csr_regfile$read_mstatus[14:13] == 2'h0 ||
stage1_rg_stage_input[112:110] != 3'b010 &&
stage1_rg_stage_input[112:110] != 3'b011;
7'b0101111:
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d750 =
NOT_stage1_rg_stage_input_32_BITS_109_TO_105_2_ETC___d559;
default: IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d750 =
csr_regfile_read_mstatus__9_BITS_14_TO_13_1_EQ_ETC___d573 ||
NOT_stage1_rg_stage_input_32_BITS_99_TO_98_74__ETC___d734 &&
NOT_stage1_rg_stage_input_32_BITS_104_TO_98_38_ETC___d746;
endcase
end
always@(stage1_rg_stage_input or
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d750)
begin
case (stage1_rg_stage_input[151:145])
7'b0000011:
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q12 =
stage1_rg_stage_input[112:110] != 3'd0 &&
stage1_rg_stage_input[112:110] != 3'b100 &&
stage1_rg_stage_input[112:110] != 3'b001 &&
stage1_rg_stage_input[112:110] != 3'b101 &&
stage1_rg_stage_input[112:110] != 3'b010 &&
stage1_rg_stage_input[112:110] != 3'b110 &&
stage1_rg_stage_input[112:110] != 3'b011;
7'b0100011:
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q12 =
stage1_rg_stage_input[112:110] != 3'd0 &&
stage1_rg_stage_input[112:110] != 3'b001 &&
stage1_rg_stage_input[112:110] != 3'b010 &&
stage1_rg_stage_input[112:110] != 3'b011;
default: CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q12 =
stage1_rg_stage_input[151:145] == 7'b0001111 ||
stage1_rg_stage_input[151:145] == 7'b1110011 ||
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d750;
endcase
end
always@(stage1_rg_stage_input or
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q12 or
NOT_stage1_rg_stage_input_32_BITS_112_TO_110_8_ETC___d479)
begin
case (stage1_rg_stage_input[151:145])
7'b0010011, 7'b0110011:
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d758 =
NOT_stage1_rg_stage_input_32_BITS_112_TO_110_8_ETC___d479;
7'b0011011:
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d758 =
stage1_rg_stage_input[112:110] != 3'd0 &&
(stage1_rg_stage_input[112:110] != 3'b001 ||
stage1_rg_stage_input[263] ||
stage1_rg_stage_input[261:257] != 5'b0 ||
stage1_rg_stage_input[262]) &&
(stage1_rg_stage_input[112:110] != 3'b101 ||
stage1_rg_stage_input[263] ||
stage1_rg_stage_input[261:257] != 5'b0);
7'b0111011:
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d758 =
stage1_rg_stage_input[97:88] != 10'b0 &&
stage1_rg_stage_input[97:88] != 10'b0100000000 &&
stage1_rg_stage_input[97:88] != 10'b0000000001 &&
stage1_rg_stage_input[97:88] != 10'b0000000101 &&
stage1_rg_stage_input[97:88] != 10'b0100000101;
default: IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d758 =
stage1_rg_stage_input[151:145] != 7'b0110111 &&
stage1_rg_stage_input[151:145] != 7'b0010111 &&
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q12;
endcase
end
always@(stage1_rg_stage_input)
begin
case (stage1_rg_stage_input[112:110])
3'b010, 3'b011, 3'b100, 3'b110:
CASE_stage1_rg_stage_input_BITS_112_TO_110_0b1_ETC__q13 =
stage1_rg_stage_input[151:145] == 7'b0010011 ||
!stage1_rg_stage_input[263] ||
!stage1_rg_stage_input[262] ||
stage1_rg_stage_input[261:257] == 5'b0;
default: CASE_stage1_rg_stage_input_BITS_112_TO_110_0b1_ETC__q13 =
stage1_rg_stage_input[112:110] == 3'b111 &&
(stage1_rg_stage_input[151:145] == 7'b0010011 ||
!stage1_rg_stage_input[263] ||
!stage1_rg_stage_input[262] ||
stage1_rg_stage_input[261:257] == 5'b0);
endcase
end
always@(stage1_rg_stage_input or
NOT_csr_regfile_read_mstatus__9_BITS_14_TO_13__ETC___d851 or
stage1_rg_stage_input_32_BITS_99_TO_98_74_EQ_0_ETC___d938 or
rm__h10284 or csr_regfile$read_mstatus)
begin
case (stage1_rg_stage_input[151:145])
7'b0000111, 7'b0100111:
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d952 =
csr_regfile$read_mstatus[14:13] != 2'h0 &&
(stage1_rg_stage_input[112:110] == 3'b010 ||
stage1_rg_stage_input[112:110] == 3'b011);
7'b0101111:
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d952 =
(stage1_rg_stage_input[109:105] == 5'b00010 &&
stage1_rg_stage_input[134:130] == 5'd0 ||
stage1_rg_stage_input[109:105] == 5'b00011 ||
stage1_rg_stage_input[109:105] == 5'b0 ||
stage1_rg_stage_input[109:105] == 5'b00001 ||
stage1_rg_stage_input[109:105] == 5'b01100 ||
stage1_rg_stage_input[109:105] == 5'b01000 ||
stage1_rg_stage_input[109:105] == 5'b00100 ||
stage1_rg_stage_input[109:105] == 5'b10000 ||
stage1_rg_stage_input[109:105] == 5'b11000 ||
stage1_rg_stage_input[109:105] == 5'b10100 ||
stage1_rg_stage_input[109:105] == 5'b11100) &&
(stage1_rg_stage_input[112:110] == 3'b010 ||
stage1_rg_stage_input[112:110] == 3'b011);
default: IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d952 =
NOT_csr_regfile_read_mstatus__9_BITS_14_TO_13__ETC___d851 &&
(stage1_rg_stage_input_32_BITS_99_TO_98_74_EQ_0_ETC___d938 ||
stage1_rg_stage_input[104:98] == 7'h61 &&
(stage1_rg_stage_input[134:130] == 5'b00010 ||
stage1_rg_stage_input[134:130] == 5'b00011) ||
stage1_rg_stage_input[104:98] == 7'h71 &&
stage1_rg_stage_input[134:130] == 5'd0 &&
rm__h10284 == 3'b0 ||
stage1_rg_stage_input[104:98] == 7'h69 &&
stage1_rg_stage_input[134:130] == 5'b00010 ||
stage1_rg_stage_input[104:98] == 7'h69 &&
stage1_rg_stage_input[134:130] == 5'b00011 ||
stage1_rg_stage_input[104:98] == 7'h79 &&
stage1_rg_stage_input[134:130] == 5'd0 &&
rm__h10284 == 3'b0);
endcase
end
always@(stage1_rg_stage_input or
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d952)
begin
case (stage1_rg_stage_input[151:145])
7'b0000011:
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q14 =
stage1_rg_stage_input[112:110] == 3'd0 ||
stage1_rg_stage_input[112:110] == 3'b100 ||
stage1_rg_stage_input[112:110] == 3'b001 ||
stage1_rg_stage_input[112:110] == 3'b101 ||
stage1_rg_stage_input[112:110] == 3'b010 ||
stage1_rg_stage_input[112:110] == 3'b110 ||
stage1_rg_stage_input[112:110] == 3'b011;
7'b0100011:
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q14 =
stage1_rg_stage_input[112:110] == 3'd0 ||
stage1_rg_stage_input[112:110] == 3'b001 ||
stage1_rg_stage_input[112:110] == 3'b010 ||
stage1_rg_stage_input[112:110] == 3'b011;
default: CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q14 =
stage1_rg_stage_input[151:145] != 7'b0001111 &&
stage1_rg_stage_input[151:145] != 7'b1110011 &&
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d952;
endcase
end
always@(stage1_rg_stage_input or
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q14 or
stage1_rg_stage_input_32_BITS_112_TO_110_80_EQ_ETC___d806)
begin
case (stage1_rg_stage_input[151:145])
7'b0010011, 7'b0110011:
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d960 =
stage1_rg_stage_input_32_BITS_112_TO_110_80_EQ_ETC___d806;
7'b0011011:
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d960 =
stage1_rg_stage_input[112:110] == 3'd0 ||
stage1_rg_stage_input[112:110] == 3'b001 &&
!stage1_rg_stage_input[263] &&
stage1_rg_stage_input[261:257] == 5'b0 &&
!stage1_rg_stage_input[262] ||
stage1_rg_stage_input[112:110] == 3'b101 &&
!stage1_rg_stage_input[263] &&
stage1_rg_stage_input[261:257] == 5'b0;
7'b0111011:
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d960 =
stage1_rg_stage_input[97:88] == 10'b0 ||
stage1_rg_stage_input[97:88] == 10'b0100000000 ||
stage1_rg_stage_input[97:88] == 10'b0000000001 ||
stage1_rg_stage_input[97:88] == 10'b0000000101 ||
stage1_rg_stage_input[97:88] == 10'b0100000101;
default: IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d960 =
stage1_rg_stage_input[151:145] == 7'b0110111 ||
stage1_rg_stage_input[151:145] == 7'b0010111 ||
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q14;
endcase
end
always@(rg_cur_priv)
begin
case (rg_cur_priv)
2'b0: CASE_rg_cur_priv_0b0_8_0b1_9_11__q15 = 4'd8;
2'b01: CASE_rg_cur_priv_0b0_8_0b1_9_11__q15 = 4'd9;
default: CASE_rg_cur_priv_0b0_8_0b1_9_11__q15 = 4'd11;
endcase
end
always@(stage1_rg_stage_input or CASE_rg_cur_priv_0b0_8_0b1_9_11__q15)
begin
case (stage1_rg_stage_input[87:76])
12'b0:
CASE_stage1_rg_stage_input_BITS_87_TO_76_0b0_C_ETC__q16 =
CASE_rg_cur_priv_0b0_8_0b1_9_11__q15;
12'b000000000001:
CASE_stage1_rg_stage_input_BITS_87_TO_76_0b0_C_ETC__q16 = 4'd3;
default: CASE_stage1_rg_stage_input_BITS_87_TO_76_0b0_C_ETC__q16 = 4'd2;
endcase
end
always@(stage1_rg_stage_input or alu_outputs___1_exc_code__h10979)
begin
case (stage1_rg_stage_input[151:145])
7'b0000011,
7'b0001111,
7'b0010011,
7'b0010111,
7'b0011011,
7'b0100011,
7'b0110011,
7'b0110111,
7'b0111011,
7'b1100011:
alu_outputs_exc_code__h11737 = 4'd2;
7'b1100111, 7'b1101111: alu_outputs_exc_code__h11737 = 4'd0;
7'b1110011:
alu_outputs_exc_code__h11737 = alu_outputs___1_exc_code__h10979;
default: alu_outputs_exc_code__h11737 = 4'd2;
endcase
end
always@(stage1_rg_stage_input or
_theResult_____1_fst__h12570 or
rd_val___1__h12538 or
rd_val___1__h12545 or rd_val___1__h12552 or rd_val___1__h12559)
begin
case (stage1_rg_stage_input[112:110])
3'b010: _theResult_____1_fst__h12542 = rd_val___1__h12538;
3'b011: _theResult_____1_fst__h12542 = rd_val___1__h12545;
3'b100: _theResult_____1_fst__h12542 = rd_val___1__h12552;
3'b110: _theResult_____1_fst__h12542 = rd_val___1__h12559;
default: _theResult_____1_fst__h12542 = _theResult_____1_fst__h12570;
endcase
end
always@(stage1_rg_stage_input or
alu_outputs___1_addr__h10697 or
IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d1260 or
rs1_val_bypassed__h5597 or
alu_outputs___1_addr__h10323 or next_pc__h10371 or next_pc__h10336)
begin
case (stage1_rg_stage_input[151:145])
7'b0000011, 7'b0000111:
x_out_data_to_stage2_addr__h10120 =
IF_stage1_rg_stage_input_32_BITS_139_TO_135_36_ETC___d1260;
7'b0100011:
x_out_data_to_stage2_addr__h10120 = alu_outputs___1_addr__h10697;
7'b0101111: x_out_data_to_stage2_addr__h10120 = rs1_val_bypassed__h5597;
7'b1100011:
x_out_data_to_stage2_addr__h10120 = alu_outputs___1_addr__h10323;
7'b1100111: x_out_data_to_stage2_addr__h10120 = next_pc__h10371;
7'b1101111: x_out_data_to_stage2_addr__h10120 = next_pc__h10336;
default: x_out_data_to_stage2_addr__h10120 =
alu_outputs___1_addr__h10697;
endcase
end
always@(stage1_rg_stage_input or
next_pc__h10371 or branch_target__h10301 or next_pc__h10336)
begin
case (stage1_rg_stage_input[151:145])
7'b1100011: x_out_cf_info_taken_PC__h16275 = branch_target__h10301;
7'b1101111: x_out_cf_info_taken_PC__h16275 = next_pc__h10336;
default: x_out_cf_info_taken_PC__h16275 = next_pc__h10371;
endcase
end
always@(stage1_rg_stage_input or rs2_val_bypassed__h5603)
begin
case (stage1_rg_stage_input[151:145])
7'b0100011, 7'b0101111:
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q19 =
rs2_val_bypassed__h5603;
default: CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q19 =
rs2_val_bypassed__h5603;
endcase
end
always@(stage1_rg_stage_input or
NOT_rg_cur_priv_8_EQ_0b11_059_091_AND_NOT_rg_c_ETC___d1645 or
data_to_stage2_addr__h10103)
begin
case (stage1_rg_stage_input[151:145])
7'b1100111, 7'b1101111:
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q20 =
data_to_stage2_addr__h10103;
default: CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q20 =
(stage1_rg_stage_input[151:145] == 7'b1110011 &&
stage1_rg_stage_input[112:110] == 3'd0 &&
NOT_rg_cur_priv_8_EQ_0b11_059_091_AND_NOT_rg_c_ETC___d1645) ?
stage1_rg_stage_input[401:338] :
64'd0;
endcase
end
always@(stage2_rg_stage2 or
stage2_fbox$valid or
near_mem$dmem_valid or near_mem$dmem_exc or stage2_mbox$valid)
begin
case (stage2_rg_stage2[397:395])
3'd1, 3'd2, 3'd4:
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d2299 =
near_mem$dmem_valid && !near_mem$dmem_exc;
3'd3:
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d2299 =
stage2_mbox$valid;
default: IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d2299 =
stage2_fbox$valid;
endcase
end
always@(stage2_rg_stage2 or
stage2_fbox$valid or
near_mem$dmem_valid or near_mem$dmem_exc or stage2_mbox$valid)
begin
case (stage2_rg_stage2[397:395])
3'd1, 3'd2, 3'd4:
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d2686 =
!near_mem$dmem_valid || near_mem$dmem_exc;
3'd3:
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d2686 =
!stage2_mbox$valid;
default: IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d2686 =
!stage2_fbox$valid;
endcase
end
always@(stage1_rg_stage_input or
csr_regfile_read_mstatus__9_BITS_14_TO_13_1_EQ_ETC___d573 or
NOT_stage1_rg_stage_input_32_BITS_99_TO_98_74__ETC___d734 or
NOT_stage1_rg_stage_input_32_BITS_104_TO_98_38_ETC___d746 or
csr_regfile$read_mstatus or
NOT_stage1_rg_stage_input_32_BITS_112_TO_110_8_ETC___d1164 or
NOT_stage1_rg_stage_input_32_BITS_112_TO_110_8_ETC___d1157 or
NOT_stage1_rg_stage_input_32_BITS_109_TO_105_2_ETC___d559 or
IF_stage1_rg_stage_input_32_BITS_112_TO_110_80_ETC___d2764)
begin
case (stage1_rg_stage_input[151:145])
7'b0000011:
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d2768 =
stage1_rg_stage_input[112:110] != 3'd0 &&
stage1_rg_stage_input[112:110] != 3'b100 &&
stage1_rg_stage_input[112:110] != 3'b001 &&
stage1_rg_stage_input[112:110] != 3'b101 &&
stage1_rg_stage_input[112:110] != 3'b010 &&
stage1_rg_stage_input[112:110] != 3'b110 &&
stage1_rg_stage_input[112:110] != 3'b011;
7'b0000111, 7'b0100111:
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d2768 =
csr_regfile$read_mstatus[14:13] == 2'h0 ||
stage1_rg_stage_input[112:110] != 3'b010 &&
stage1_rg_stage_input[112:110] != 3'b011;
7'b0001111:
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d2768 =
NOT_stage1_rg_stage_input_32_BITS_112_TO_110_8_ETC___d1164 &&
NOT_stage1_rg_stage_input_32_BITS_112_TO_110_8_ETC___d1157;
7'b0100011:
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d2768 =
stage1_rg_stage_input[112:110] != 3'd0 &&
stage1_rg_stage_input[112:110] != 3'b001 &&
stage1_rg_stage_input[112:110] != 3'b010 &&
stage1_rg_stage_input[112:110] != 3'b011;
7'b0101111:
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d2768 =
NOT_stage1_rg_stage_input_32_BITS_109_TO_105_2_ETC___d559;
7'b1110011:
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d2768 =
IF_stage1_rg_stage_input_32_BITS_112_TO_110_80_ETC___d2764;
default: IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d2768 =
csr_regfile_read_mstatus__9_BITS_14_TO_13_1_EQ_ETC___d573 ||
NOT_stage1_rg_stage_input_32_BITS_99_TO_98_74__ETC___d734 &&
NOT_stage1_rg_stage_input_32_BITS_104_TO_98_38_ETC___d746;
endcase
end
always@(stage1_rg_stage_input or
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d2768 or
NOT_stage1_rg_stage_input_32_BITS_112_TO_110_8_ETC___d479)
begin
case (stage1_rg_stage_input[151:145])
7'b0010011, 7'b0110011:
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d2772 =
NOT_stage1_rg_stage_input_32_BITS_112_TO_110_8_ETC___d479;
7'b0011011:
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d2772 =
stage1_rg_stage_input[112:110] != 3'd0 &&
(stage1_rg_stage_input[112:110] != 3'b001 ||
stage1_rg_stage_input[263] ||
stage1_rg_stage_input[261:257] != 5'b0 ||
stage1_rg_stage_input[262]) &&
(stage1_rg_stage_input[112:110] != 3'b101 ||
stage1_rg_stage_input[263] ||
stage1_rg_stage_input[261:257] != 5'b0);
7'b0111011:
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d2772 =
stage1_rg_stage_input[97:88] != 10'b0 &&
stage1_rg_stage_input[97:88] != 10'b0100000000 &&
stage1_rg_stage_input[97:88] != 10'b0000000001 &&
stage1_rg_stage_input[97:88] != 10'b0000000101 &&
stage1_rg_stage_input[97:88] != 10'b0100000101;
default: IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d2772 =
stage1_rg_stage_input[151:145] != 7'b0110111 &&
stage1_rg_stage_input[151:145] != 7'b0010111 &&
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d2768;
endcase
end
always@(stage1_rg_stage_input or
rs1_val_bypassed__h5597 or
alu_outputs___1_val1__h10541 or
rd_val__h10633 or
alu_outputs___1_val1__h10570 or
alu_outputs___1_val1__h11011 or
rd_val__h10612 or
alu_outputs___1_val1__h10598 or alu_outputs___1_val1__h10983)
begin
case (stage1_rg_stage_input[151:145])
7'b0010011, 7'b0110011:
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d1520 =
alu_outputs___1_val1__h10541;
7'b0010111:
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d1520 =
rd_val__h10633;
7'b0011011:
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d1520 =
alu_outputs___1_val1__h10570;
7'b0101111:
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d1520 =
alu_outputs___1_val1__h11011;
7'b0110111:
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d1520 =
rd_val__h10612;
7'b0111011:
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d1520 =
alu_outputs___1_val1__h10598;
7'b1110011:
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d1520 =
alu_outputs___1_val1__h10983;
default: IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d1520 =
rs1_val_bypassed__h5597;
endcase
end
always@(stage1_rg_stage_input or
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d1522 or
x_out_cf_info_fallthru_PC__h16274)
begin
case (stage1_rg_stage_input[151:145])
7'b1100111, 7'b1101111:
x_out_data_to_stage2_val1__h10121 =
x_out_cf_info_fallthru_PC__h16274;
default: x_out_data_to_stage2_val1__h10121 =
IF_stage1_rg_stage_input_32_BITS_151_TO_145_78_ETC___d1522;
endcase
end
always@(stage1_rg_stage_input)
begin
case (stage1_rg_stage_input[151:145])
7'b0000011, 7'b0000111:
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q21 = 3'd1;
7'b0010011, 7'b0010111, 7'b0011011, 7'b0110011, 7'b0110111, 7'b0111011:
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q21 = 3'd0;
7'b0100011, 7'b0100111:
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q21 = 3'd2;
7'b0101111:
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q21 = 3'd4;
default: CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q21 = 3'd5;
endcase
end
always@(stage1_rg_stage_input or
stage1_rg_stage_input_32_BITS_151_TO_145_78_EQ_ETC___d794 or
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q21)
begin
case (stage1_rg_stage_input[151:145])
7'b1100011, 7'b1100111, 7'b1101111:
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q22 = 3'd0;
default: CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q22 =
(stage1_rg_stage_input[151:145] == 7'b0110011 &&
stage1_rg_stage_input[104:98] == 7'b0000001 ||
stage1_rg_stage_input_32_BITS_151_TO_145_78_EQ_ETC___d794) ?
3'd3 :
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q21;
endcase
end
always@(stage1_rg_stage_input)
begin
case (stage1_rg_stage_input[151:145])
7'b1100011:
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q23 = 2'd0;
7'b1100111:
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q23 = 2'd2;
7'b1101111:
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q23 = 2'd1;
default: CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q23 = 2'd3;
endcase
end
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
cfg_logdelay <= `BSV_ASSIGNMENT_DELAY 64'd0;
cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0;
imem_rg_cache_addr <= `BSV_ASSIGNMENT_DELAY 64'hFFFFFFFFFFFFFFFF;
rg_cur_priv <= `BSV_ASSIGNMENT_DELAY 2'b11;
rg_run_on_reset <= `BSV_ASSIGNMENT_DELAY 1'd0;
rg_state <= `BSV_ASSIGNMENT_DELAY 4'd0;
stage1_rg_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
stage2_rg_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
stage2_rg_resetting <= `BSV_ASSIGNMENT_DELAY 1'd0;
stage3_rg_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
stageD_rg_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
stageF_rg_epoch <= `BSV_ASSIGNMENT_DELAY 2'd0;
stageF_rg_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
end
else
begin
if (cfg_logdelay$EN)
cfg_logdelay <= `BSV_ASSIGNMENT_DELAY cfg_logdelay$D_IN;
if (cfg_verbosity$EN)
cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN;
if (imem_rg_cache_addr$EN)
imem_rg_cache_addr <= `BSV_ASSIGNMENT_DELAY imem_rg_cache_addr$D_IN;
if (rg_cur_priv$EN)
rg_cur_priv <= `BSV_ASSIGNMENT_DELAY rg_cur_priv$D_IN;
if (rg_run_on_reset$EN)
rg_run_on_reset <= `BSV_ASSIGNMENT_DELAY rg_run_on_reset$D_IN;
if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN;
if (stage1_rg_full$EN)
stage1_rg_full <= `BSV_ASSIGNMENT_DELAY stage1_rg_full$D_IN;
if (stage2_rg_full$EN)
stage2_rg_full <= `BSV_ASSIGNMENT_DELAY stage2_rg_full$D_IN;
if (stage2_rg_resetting$EN)
stage2_rg_resetting <= `BSV_ASSIGNMENT_DELAY
stage2_rg_resetting$D_IN;
if (stage3_rg_full$EN)
stage3_rg_full <= `BSV_ASSIGNMENT_DELAY stage3_rg_full$D_IN;
if (stageD_rg_full$EN)
stageD_rg_full <= `BSV_ASSIGNMENT_DELAY stageD_rg_full$D_IN;
if (stageF_rg_epoch$EN)
stageF_rg_epoch <= `BSV_ASSIGNMENT_DELAY stageF_rg_epoch$D_IN;
if (stageF_rg_full$EN)
stageF_rg_full <= `BSV_ASSIGNMENT_DELAY stageF_rg_full$D_IN;
end
if (imem_rg_cache_b16$EN)
imem_rg_cache_b16 <= `BSV_ASSIGNMENT_DELAY imem_rg_cache_b16$D_IN;
if (imem_rg_f3$EN) imem_rg_f3 <= `BSV_ASSIGNMENT_DELAY imem_rg_f3$D_IN;
if (imem_rg_mstatus_MXR$EN)
imem_rg_mstatus_MXR <= `BSV_ASSIGNMENT_DELAY imem_rg_mstatus_MXR$D_IN;
if (imem_rg_pc$EN) imem_rg_pc <= `BSV_ASSIGNMENT_DELAY imem_rg_pc$D_IN;
if (imem_rg_priv$EN)
imem_rg_priv <= `BSV_ASSIGNMENT_DELAY imem_rg_priv$D_IN;
if (imem_rg_satp$EN)
imem_rg_satp <= `BSV_ASSIGNMENT_DELAY imem_rg_satp$D_IN;
if (imem_rg_sstatus_SUM$EN)
imem_rg_sstatus_SUM <= `BSV_ASSIGNMENT_DELAY imem_rg_sstatus_SUM$D_IN;
if (imem_rg_tval$EN)
imem_rg_tval <= `BSV_ASSIGNMENT_DELAY imem_rg_tval$D_IN;
if (rg_csr_pc$EN) rg_csr_pc <= `BSV_ASSIGNMENT_DELAY rg_csr_pc$D_IN;
if (rg_csr_val1$EN) rg_csr_val1 <= `BSV_ASSIGNMENT_DELAY rg_csr_val1$D_IN;
if (rg_epoch$EN) rg_epoch <= `BSV_ASSIGNMENT_DELAY rg_epoch$D_IN;
if (rg_mstatus_MXR$EN)
rg_mstatus_MXR <= `BSV_ASSIGNMENT_DELAY rg_mstatus_MXR$D_IN;
if (rg_next_pc$EN) rg_next_pc <= `BSV_ASSIGNMENT_DELAY rg_next_pc$D_IN;
if (rg_sstatus_SUM$EN)
rg_sstatus_SUM <= `BSV_ASSIGNMENT_DELAY rg_sstatus_SUM$D_IN;
if (rg_start_CPI_cycles$EN)
rg_start_CPI_cycles <= `BSV_ASSIGNMENT_DELAY rg_start_CPI_cycles$D_IN;
if (rg_start_CPI_instrs$EN)
rg_start_CPI_instrs <= `BSV_ASSIGNMENT_DELAY rg_start_CPI_instrs$D_IN;
if (rg_trap_info$EN)
rg_trap_info <= `BSV_ASSIGNMENT_DELAY rg_trap_info$D_IN;
if (rg_trap_instr$EN)
rg_trap_instr <= `BSV_ASSIGNMENT_DELAY rg_trap_instr$D_IN;
if (rg_trap_interrupt$EN)
rg_trap_interrupt <= `BSV_ASSIGNMENT_DELAY rg_trap_interrupt$D_IN;
if (stage1_rg_stage_input$EN)
stage1_rg_stage_input <= `BSV_ASSIGNMENT_DELAY
stage1_rg_stage_input$D_IN;
if (stage2_rg_stage2$EN)
stage2_rg_stage2 <= `BSV_ASSIGNMENT_DELAY stage2_rg_stage2$D_IN;
if (stage3_rg_stage3$EN)
stage3_rg_stage3 <= `BSV_ASSIGNMENT_DELAY stage3_rg_stage3$D_IN;
if (stageD_rg_data$EN)
stageD_rg_data <= `BSV_ASSIGNMENT_DELAY stageD_rg_data$D_IN;
if (stageF_rg_priv$EN)
stageF_rg_priv <= `BSV_ASSIGNMENT_DELAY stageF_rg_priv$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
cfg_logdelay = 64'hAAAAAAAAAAAAAAAA;
cfg_verbosity = 4'hA;
imem_rg_cache_addr = 64'hAAAAAAAAAAAAAAAA;
imem_rg_cache_b16 = 16'hAAAA;
imem_rg_f3 = 3'h2;
imem_rg_mstatus_MXR = 1'h0;
imem_rg_pc = 64'hAAAAAAAAAAAAAAAA;
imem_rg_priv = 2'h2;
imem_rg_satp = 64'hAAAAAAAAAAAAAAAA;
imem_rg_sstatus_SUM = 1'h0;
imem_rg_tval = 64'hAAAAAAAAAAAAAAAA;
rg_csr_pc = 64'hAAAAAAAAAAAAAAAA;
rg_csr_val1 = 64'hAAAAAAAAAAAAAAAA;
rg_cur_priv = 2'h2;
rg_epoch = 2'h2;
rg_mstatus_MXR = 1'h0;
rg_next_pc = 64'hAAAAAAAAAAAAAAAA;
rg_run_on_reset = 1'h0;
rg_sstatus_SUM = 1'h0;
rg_start_CPI_cycles = 64'hAAAAAAAAAAAAAAAA;
rg_start_CPI_instrs = 64'hAAAAAAAAAAAAAAAA;
rg_state = 4'hA;
rg_trap_info = 132'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
rg_trap_instr = 32'hAAAAAAAA;
rg_trap_interrupt = 1'h0;
stage1_rg_full = 1'h0;
stage1_rg_stage_input =
402'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
stage2_rg_full = 1'h0;
stage2_rg_resetting = 1'h0;
stage2_rg_stage2 =
496'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
stage3_rg_full = 1'h0;
stage3_rg_stage3 =
239'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
stageD_rg_data =
234'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
stageD_rg_full = 1'h0;
stageF_rg_epoch = 2'h2;
stageF_rg_full = 1'h0;
stageF_rg_priv = 2'h2;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$display("================================================================");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$display("%0d: Pipeline State: minstret:%0d cur_priv:%0d mstatus:%0x epoch:%0d",
csr_regfile$read_csr_mcycle,
csr_regfile$read_csr_minstret,
rg_cur_priv,
csr_regfile$read_mstatus,
rg_epoch);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$write("MStatus{",
"sd:%0d",
csr_regfile$read_mstatus[14:13] == 2'h3 ||
csr_regfile$read_mstatus[16:15] == 2'h3);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && csr_regfile$read_misa[27:26] == 2'd2)
$write(" sxl:%0d uxl:%0d", sxl__h6937, uxl__h6938);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && csr_regfile$read_misa[27:26] != 2'd2)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$write(" tsr:%0d", csr_regfile$read_mstatus[22]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$write(" tw:%0d", csr_regfile$read_mstatus[21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$write(" tvm:%0d", csr_regfile$read_mstatus[20]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$write(" mxr:%0d", csr_regfile$read_mstatus[19]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$write(" sum:%0d", csr_regfile$read_mstatus[18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$write(" mprv:%0d", csr_regfile$read_mstatus[17]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$write(" xs:%0d", csr_regfile$read_mstatus[16:15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$write(" fs:%0d", csr_regfile$read_mstatus[14:13]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$write(" mpp:%0d", csr_regfile$read_mstatus[12:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$write(" spp:%0d", csr_regfile$read_mstatus[8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$write(" pies:%0d_%0d%0d",
csr_regfile$read_mstatus[7],
csr_regfile$read_mstatus[5],
csr_regfile$read_mstatus[4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$write(" ies:%0d_%0d%0d",
csr_regfile$read_mstatus[3],
csr_regfile$read_mstatus[1],
csr_regfile$read_mstatus[0]);
if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe) $write("}");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write(" Stage3: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write("Output_Stage3");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage3_rg_full) $write(" PIPE");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage3_rg_full) $write(" EMPTY");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write(" Bypass to Stage1: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write("Bypass {");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
(stage3_rg_stage3[69] || !stage3_rg_full || !stage3_rg_stage3[140]))
$write("Rd -");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage3_rg_stage3[69] &&
stage3_rg_full &&
stage3_rg_stage3[140])
$write("Rd %0d ", stage3_rg_stage3[139:135]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
(stage3_rg_stage3[69] || !stage3_rg_full || !stage3_rg_stage3[140]))
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage3_rg_stage3[69] &&
stage3_rg_full &&
stage3_rg_stage3[140])
$write("rd_val:%h", stage3_rg_stage3[134:71]);
if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe) $write("}");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write(" FBypass to Stage1: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write("FBypass {");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
(!stage3_rg_stage3[69] || !stage3_rg_full ||
!stage3_rg_stage3[140]))
$write("FRd -");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage3_rg_stage3[69] &&
stage3_rg_full &&
stage3_rg_stage3[140])
$write("FRd %0d ", stage3_rg_stage3[139:135]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
(!stage3_rg_stage3[69] || !stage3_rg_full ||
!stage3_rg_stage3[140]))
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage3_rg_stage3[69] &&
stage3_rg_full &&
stage3_rg_stage3[140])
$write("frd_val:%h", stage3_rg_stage3[63:0]);
if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe) $write("}");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$display(" Stage2: pc 0x%08h instr 0x%08h priv %0d",
stage2_rg_stage2[493:430],
stage2_rg_stage2[429:398],
stage2_rg_stage2[495:494]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d148)
$write("Output_Stage2", " BUSY: pc:%0h", stage2_rg_stage2[493:430]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152 &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d156)
$write("Output_Stage2", " NONPIPE: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d170)
$write("Output_Stage2", " PIPE: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage2_rg_full)
$write("Output_Stage2", " EMPTY");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d148)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152 &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d156)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d170)
$write("data_to_Stage3 {pc:%h instr:%h priv:%0d\n",
stage2_rg_stage2[493:430],
stage2_rg_stage2[429:398],
stage2_rg_stage2[495:494]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage2_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d148)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152 &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d156)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d170)
$write(" rd_valid:");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage2_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d148)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152 &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d156)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152 &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d177)
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
(stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152) &&
stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_0_17_ETC___d168 &&
(stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d184))
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage2_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d148)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152 &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d156)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152 &&
stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_0_17_ETC___d168 &&
stage2_rg_stage2[397:395] != 3'd0 &&
stage2_rg_stage2[397:395] != 3'd1 &&
stage2_rg_stage2[397:395] != 3'd4 &&
stage2_rg_stage2[397:395] != 3'd2 &&
stage2_rg_stage2[397:395] != 3'd3)
$write(" fflags: %05b",
"'h%h",
x_out_data_to_stage3_fpr_flags__h8344);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
(stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152) &&
stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_0_17_ETC___d168 &&
(stage2_rg_stage2[397:395] == 3'd0 ||
stage2_rg_stage2[397:395] == 3'd1 ||
stage2_rg_stage2[397:395] == 3'd4 ||
stage2_rg_stage2[397:395] == 3'd2 ||
stage2_rg_stage2[397:395] == 3'd3))
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage2_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d148)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152 &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d156)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_0_17_ETC___d215)
$write(" frd:%0d rd_val:%h\n",
x_out_data_to_stage3_rd__h8340,
x_out_data_to_stage3_frd_val__h8345);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_0_17_ETC___d244)
$write(" grd:%0d rd_val:%h\n",
x_out_data_to_stage3_rd__h8340,
x_out_data_to_stage3_rd_val__h8341);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage2_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d148)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152 &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d156)
$write("Trap_Info { ", "epc: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d170)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage2_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d148)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152 &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d156)
$write("'h%h", value__h8670);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d170)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage2_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d148)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152 &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d156)
$write(", ", "exc_code: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d170)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage2_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d148)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152 &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d156)
$write("'h%h", x_out_trap_info_exc_code__h8780);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d170)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage2_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d148)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152 &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d156)
$write(", ", "tval: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d170)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage2_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d148)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152 &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d156)
$write("'h%h", value__h8884, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d170)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage2_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d148)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152 &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d156)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d170)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage2_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d148)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152 &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d156)
$write("Trap_Info { ", "epc: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d170)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage2_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d148)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152 &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d156)
$write("'h%h", value__h8670);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d170)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage2_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d148)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152 &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d156)
$write(", ", "exc_code: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d170)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage2_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d148)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152 &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d156)
$write("'h%h", x_out_trap_info_exc_code__h8780);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d170)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage2_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d148)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152 &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d156)
$write(", ", "tval: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d170)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage2_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d148)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d152 &&
NOT_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ__ETC___d156)
$write("'h%h", value__h8884, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d170)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage2_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write(" Bypass to Stage1: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write("Bypass {");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
(!stage2_rg_full ||
stage2_rg_stage2[397:395] != 3'd0 &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d273))
$write("Rd -");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
(stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d279))
$write("Rd %0d ", x_out_bypass_rd__h9271);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
(!stage2_rg_full ||
stage2_rg_stage2[397:395] != 3'd0 &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d273))
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d279 &&
stage2_rg_stage2[397:395] != 3'd0 &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d290)
$write("-");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
(stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d279) &&
(stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d297))
$write("rd_val:%h", x_out_bypass_rd_val__h9272);
if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe) $write("}");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write(" FBypass to Stage1: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write("FBypass {");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
(!stage2_rg_full || stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d305))
$write("FRd -");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
stage2_rg_stage2[397:395] != 3'd0 &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d310)
$write("FRd %0d ", x_out_fbypass_rd__h9453);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
(!stage2_rg_full || stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d305))
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
stage2_rg_stage2[397:395] != 3'd0 &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d310 &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d319)
$write("-");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage2_rg_full &&
stage2_rg_stage2[397:395] != 3'd0 &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d310 &&
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d324)
$write("frd_val:%h", x_out_fbypass_rd_val__h9454);
if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe) $write("}");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$display(" Stage1: pc 0x%08h instr 0x%08h priv %0d",
stage1_rg_stage_input[401:338],
stage1_rg_stage_input[263:232],
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_stage1_rg_stage_input_32_ETC___d363)
$write("Output_Stage1",
" BUSY pc:%h",
stage1_rg_stage_input[401:338]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d778)
$write("Output_Stage1",
" NONPIPE: pc:%h",
stage1_rg_stage_input[401:338]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d974)
$write("Output_Stage1");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full)
$write("Output_Stage1", " EMPTY");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_stage1_rg_stage_input_32_ETC___d363)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d778)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d974)
$write(" PIPE: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_stage1_rg_stage_input_32_ETC___d363)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d778)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_NOT_stage2_rg_full_14_71_ETC___d990)
$write("CONTROL_STRAIGHT");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_NOT_stage2_rg_full_14_71_ETC___d998)
$write("CONTROL_BRANCH");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1009)
$write("CONTROL_CSRR_W");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1024)
$write("CONTROL_CSRR_S_or_C");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1042)
$write("CONTROL_FENCE");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1056)
$write("CONTROL_FENCE_I");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1073)
$write("CONTROL_SFENCE_VMA");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1088)
$write("CONTROL_MRET");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1113)
$write("CONTROL_SRET");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1135)
$write("CONTROL_WFI");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d1219)
$write("CONTROL_TRAP");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
!stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334)
$write("CONTROL_DISCARD");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_stage1_rg_stage_input_32_ETC___d363)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d778)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d974)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_stage1_rg_stage_input_32_ETC___d363)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d778)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1230)
$write("{", "CF_None");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1238)
$write("{", "BR ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1243)
$write("{");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_stage1_rg_stage_input_32_ETC___d363)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d778)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1230)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1238)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1249)
$write("JAL [%h->%h/%h]",
stage1_rg_stage_input[401:338],
x_out_cf_info_taken_PC__h16275,
x_out_cf_info_fallthru_PC__h16274);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1278)
$write("JALR [%h->%h/%h]",
stage1_rg_stage_input[401:338],
x_out_cf_info_taken_PC__h16275,
x_out_cf_info_fallthru_PC__h16274);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_stage1_rg_stage_input_32_ETC___d363)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d778)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1230)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1238)
if (stage1_rg_stage_input[151:145] != 7'b1100011 ||
IF_stage1_rg_stage_input_32_BITS_112_TO_110_80_ETC___d432)
$write("taken ");
else
$write("fallthru ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1243)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_stage1_rg_stage_input_32_ETC___d363)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d778)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1230)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1238)
$write("[%h->%h %h]",
stage1_rg_stage_input[401:338],
x_out_cf_info_fallthru_PC__h16274,
x_out_cf_info_taken_PC__h16275);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1243)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_stage1_rg_stage_input_32_ETC___d363)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d778)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d974)
$write("}");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_stage1_rg_stage_input_32_ETC___d363)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d778)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d974)
$write("data_to_Stage 2 {pc:%h instr:%h priv:%0d\n",
stage1_rg_stage_input[401:338],
stage1_rg_stage_input[263:232],
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_stage1_rg_stage_input_32_ETC___d363)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d778)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d974)
$write(" op_stage2:");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_stage1_rg_stage_input_32_ETC___d363)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d778)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1300)
$write("OP_Stage2_ALU");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_NOT_stage2_rg_full_14_71_ETC___d1317)
$write("OP_Stage2_LD");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d1335)
$write("OP_Stage2_ST");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d368 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d375 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1368)
$write("OP_Stage2_M");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_NOT_stage2_rg_full_14_71_ETC___d1375)
$write("OP_Stage2_AMO");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_NOT_stage2_rg_full_14_71_ETC___d1401)
$write("OP_Stage2_FD");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_stage1_rg_stage_input_32_ETC___d363)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d778)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d974)
$write(" rd:%0d\n", x_out_data_to_stage2_rd__h10119);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_stage1_rg_stage_input_32_ETC___d363)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d778)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d974)
$write(" addr:%h val1:%h val2:%h}",
x_out_data_to_stage2_addr__h10120,
x_out_data_to_stage2_val1__h10121,
x_out_data_to_stage2_val2__h10122);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_stage1_rg_stage_input_32_ETC___d363)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d778)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d974)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_stage1_rg_stage_input_32_ETC___d363)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d778)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d974)
$write(" fval1:%h fval2:%h fval3:%h}",
x_out_data_to_stage2_fval1__h10123,
alu_outputs___1_fval2__h10701,
x_out_data_to_stage2_fval3__h10125);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_stage1_rg_stage_input_32_ETC___d363)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d778)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d974)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_stage1_rg_stage_input_32_ETC___d363)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d1588)
$write("CONTROL_STRAIGHT");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d778 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d995)
$write("CONTROL_BRANCH");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d778 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1007)
$write("CONTROL_CSRR_W");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d778 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1022)
$write("CONTROL_CSRR_S_or_C");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d778 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1040)
$write("CONTROL_FENCE");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d778 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1054)
$write("CONTROL_FENCE_I");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d778 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1071)
$write("CONTROL_SFENCE_VMA");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d778 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1086)
$write("CONTROL_MRET");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d778 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1111)
$write("CONTROL_SRET");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d778 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1133)
$write("CONTROL_WFI");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d778 &&
stage2_rg_full_14_AND_NOT_stage2_rg_stage2_15__ETC___d1216)
$write("CONTROL_TRAP");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d974)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_stage1_rg_stage_input_32_ETC___d363)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d778)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d974)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_stage1_rg_stage_input_32_ETC___d363)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d778)
$write("Trap_Info { ", "epc: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d974)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_stage1_rg_stage_input_32_ETC___d363)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d778)
$write("'h%h", stage1_rg_stage_input[401:338]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d974)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_stage1_rg_stage_input_32_ETC___d363)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d778)
$write(", ", "exc_code: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d974)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_stage1_rg_stage_input_32_ETC___d363)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d778)
$write("'h%h", x_out_trap_info_exc_code__h15122);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d974)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_stage1_rg_stage_input_32_ETC___d363)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d778)
$write(", ", "tval: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d974)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_stage1_rg_stage_input_32_ETC___d363)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d778)
$write("'h%h", value__h15187, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d974)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_31_AND_stage1_rg_stage_input_32_ETC___d363)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1660)
$write("\n redirect next_pc:%h", x_out_next_pc__h9864);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_32_BITS_335_TO_334_3_ETC___d1664)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$display(" StageD: pc 0x%08h instr 0x%08h priv %0d epoch %0d",
stageD_rg_data[233:170],
x_out_data_to_stage1_instr__h17651,
stageD_rg_data[167:166],
stageD_rg_data[169:168]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write("Output_StageD");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full) $write(" PIPE: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stageD_rg_full) $write(" EMPTY");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full && stageD_rg_data[164])
$write("data_to_Stage1 {pc:%0h priv:%0d epoch:%0d",
stageD_rg_data[233:170],
stageD_rg_data[167:166],
stageD_rg_data[169:168]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full && !stageD_rg_data[164])
$write("data_to_Stage1 {pc:%0h priv:%0d epoch:%0d",
stageD_rg_data[233:170],
stageD_rg_data[167:166],
stageD_rg_data[169:168]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stageD_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full && stageD_rg_data[164])
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
!stageD_rg_data[164] &&
stageD_rg_data[165])
$write(" instr_C:%0h", stageD_rg_data[79:64]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
!stageD_rg_data[164] &&
!stageD_rg_data[165])
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stageD_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full && stageD_rg_data[164])
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full && !stageD_rg_data[164])
$write(" instr:%0h pred_pc:%0h",
x_out_data_to_stage1_instr__h17651,
stageD_rg_data[63:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stageD_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full && stageD_rg_data[164])
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full && !stageD_rg_data[164])
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stageD_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
stageD_rg_data[164] &&
stageD_rg_data[163:160] == 4'd0)
$write("INSTRUCTION_ADDR_MISALIGNED");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
stageD_rg_data[164] &&
stageD_rg_data[163:160] == 4'd1)
$write("INSTRUCTION_ACCESS_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
stageD_rg_data[164] &&
stageD_rg_data[163:160] == 4'd2)
$write("ILLEGAL_INSTRUCTION");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
stageD_rg_data[164] &&
stageD_rg_data[163:160] == 4'd3)
$write("BREAKPOINT");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
stageD_rg_data[164] &&
stageD_rg_data[163:160] == 4'd4)
$write("LOAD_ADDR_MISALIGNED");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
stageD_rg_data[164] &&
stageD_rg_data[163:160] == 4'd5)
$write("LOAD_ACCESS_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
stageD_rg_data[164] &&
stageD_rg_data[163:160] == 4'd6)
$write("STORE_AMO_ADDR_MISALIGNED");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
stageD_rg_data[164] &&
stageD_rg_data[163:160] == 4'd7)
$write("STORE_AMO_ACCESS_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
stageD_rg_data[164] &&
stageD_rg_data[163:160] == 4'd8)
$write("ECALL_FROM_U");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
stageD_rg_data[164] &&
stageD_rg_data[163:160] == 4'd9)
$write("ECALL_FROM_S");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
stageD_rg_data[164] &&
stageD_rg_data[163:160] == 4'd11)
$write("ECALL_FROM_M");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
stageD_rg_data[164] &&
stageD_rg_data[163:160] == 4'd12)
$write("INSTRUCTION_PAGE_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
stageD_rg_data[164] &&
stageD_rg_data[163:160] == 4'd13)
$write("LOAD_PAGE_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
stageD_rg_data[164] &&
stageD_rg_data[163:160] == 4'd15)
$write("STORE_AMO_PAGE_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
stageD_rg_data[164] &&
stageD_rg_data[163:160] != 4'd0 &&
stageD_rg_data[163:160] != 4'd1 &&
stageD_rg_data[163:160] != 4'd2 &&
stageD_rg_data[163:160] != 4'd3 &&
stageD_rg_data[163:160] != 4'd4 &&
stageD_rg_data[163:160] != 4'd5 &&
stageD_rg_data[163:160] != 4'd6 &&
stageD_rg_data[163:160] != 4'd7 &&
stageD_rg_data[163:160] != 4'd8 &&
stageD_rg_data[163:160] != 4'd9 &&
stageD_rg_data[163:160] != 4'd11 &&
stageD_rg_data[163:160] != 4'd12 &&
stageD_rg_data[163:160] != 4'd13 &&
stageD_rg_data[163:160] != 4'd15)
$write("unknown trap Exc_Code %d", stageD_rg_data[163:160]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full && !stageD_rg_data[164])
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stageD_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full && stageD_rg_data[164])
$write(" tval %0h", stageD_rg_data[159:96]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full && !stageD_rg_data[164])
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stageD_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full) $write("}");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stageD_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$display(" StageF: pc 0x%08h instr 0x%08h priv %0d epoch %0d",
imem_rg_pc,
d_instr__h25360,
stageF_rg_priv,
stageF_rg_epoch);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write("Output_StageF");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
(!near_mem$imem_valid ||
NOT_near_mem_imem_exc__1_2_AND_imem_rg_pc_BITS_ETC___d2112))
$write(" BUSY: pc:%h", imem_rg_pc);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
near_mem$imem_valid &&
near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d2119)
$write(" PIPE: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stageF_rg_full) $write(" EMPTY");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
(!near_mem$imem_valid ||
NOT_near_mem_imem_exc__1_2_AND_imem_rg_pc_BITS_ETC___d2112))
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
near_mem$imem_valid &&
near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d2119)
$write("data_to_StageD {pc:%h priv:%0d epoch:%0d",
imem_rg_pc,
stageF_rg_priv,
stageF_rg_epoch);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stageF_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
(!near_mem$imem_valid ||
NOT_near_mem_imem_exc__1_2_AND_imem_rg_pc_BITS_ETC___d2112))
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
near_mem$imem_valid &&
near_mem$imem_exc)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stageF_rg_full_094_AND_near_mem_imem_valid_AND_ETC___d2126)
$write(" instr:%h pred_pc:%h",
d_instr__h25360,
stageF_branch_predictor$predict_rsp);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stageF_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
(!near_mem$imem_valid ||
NOT_near_mem_imem_exc__1_2_AND_imem_rg_pc_BITS_ETC___d2112))
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
near_mem$imem_valid &&
near_mem$imem_exc &&
near_mem$imem_exc_code == 4'd0)
$write("INSTRUCTION_ADDR_MISALIGNED");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
near_mem$imem_valid &&
near_mem$imem_exc &&
near_mem$imem_exc_code == 4'd1)
$write("INSTRUCTION_ACCESS_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
near_mem$imem_valid &&
near_mem$imem_exc &&
near_mem$imem_exc_code == 4'd2)
$write("ILLEGAL_INSTRUCTION");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
near_mem$imem_valid &&
near_mem$imem_exc &&
near_mem$imem_exc_code == 4'd3)
$write("BREAKPOINT");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
near_mem$imem_valid &&
near_mem$imem_exc &&
near_mem$imem_exc_code == 4'd4)
$write("LOAD_ADDR_MISALIGNED");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
near_mem$imem_valid &&
near_mem$imem_exc &&
near_mem$imem_exc_code == 4'd5)
$write("LOAD_ACCESS_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
near_mem$imem_valid &&
near_mem$imem_exc &&
near_mem$imem_exc_code == 4'd6)
$write("STORE_AMO_ADDR_MISALIGNED");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
near_mem$imem_valid &&
near_mem$imem_exc &&
near_mem$imem_exc_code == 4'd7)
$write("STORE_AMO_ACCESS_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
near_mem$imem_valid &&
near_mem$imem_exc &&
near_mem$imem_exc_code == 4'd8)
$write("ECALL_FROM_U");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
near_mem$imem_valid &&
near_mem$imem_exc &&
near_mem$imem_exc_code == 4'd9)
$write("ECALL_FROM_S");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
near_mem$imem_valid &&
near_mem$imem_exc &&
near_mem$imem_exc_code == 4'd11)
$write("ECALL_FROM_M");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
near_mem$imem_valid &&
near_mem$imem_exc &&
near_mem$imem_exc_code == 4'd12)
$write("INSTRUCTION_PAGE_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
near_mem$imem_valid &&
near_mem$imem_exc &&
near_mem$imem_exc_code == 4'd13)
$write("LOAD_PAGE_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
near_mem$imem_valid &&
near_mem$imem_exc &&
near_mem$imem_exc_code == 4'd15)
$write("STORE_AMO_PAGE_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
near_mem_imem_valid_AND_near_mem_imem_exc__1_A_ETC___d2214)
$write("unknown trap Exc_Code %d", near_mem$imem_exc_code);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stageF_rg_full_094_AND_near_mem_imem_valid_AND_ETC___d2126)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stageF_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
(!near_mem$imem_valid ||
NOT_near_mem_imem_exc__1_2_AND_imem_rg_pc_BITS_ETC___d2112))
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
near_mem$imem_valid &&
near_mem_imem_exc__1_OR_NOT_imem_rg_pc_BITS_1__ETC___d2119)
$write("}");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stageF_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $display("----------------");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage2_nonpipe &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display("%0d: %m.rl_stage2_nonpipe -> CPU_TRAP",
csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_trap &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display("%0d: %m.rl_stage1_trap", csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_trap &&
rg_trap_info_787_BITS_131_TO_68_788_EQ_csr_reg_ETC___d2797)
$display("%0d: %m.rl_stage1_trap: Tight infinite trap loop: pc 0x%0x instr 0x%08x",
csr_regfile$read_csr_mcycle,
csr_regfile$csr_trap_actions[193:130],
rg_trap_instr);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_trap &&
rg_trap_info_787_BITS_131_TO_68_788_EQ_csr_reg_ETC___d2797)
$display("CPI: %0d.%0d = (%0d/%0d) since last 'continue'",
cpi__h33879,
cpifrac__h33880,
delta_CPI_cycles__h33875,
_theResult____h33877);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_trap &&
rg_trap_info_787_BITS_131_TO_68_788_EQ_csr_reg_ETC___d2797)
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_trap &&
(cur_verbosity__h3946 != 4'd0 ||
csr_regfile$read_csr_minstret[19:0] == 20'd0))
$display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d",
csr_regfile$read_csr_minstret,
rg_trap_info[131:68],
rg_trap_instr,
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_trap && cur_verbosity__h3946 != 4'd0)
$display(" mcause:0x%0h epc 0x%0h tval:0x%0h next_pc 0x%0h, new_priv %0d new_mstatus 0x%0h",
csr_regfile$csr_trap_actions[65:2],
rg_trap_info[131:68],
rg_trap_info[63:0],
csr_regfile$csr_trap_actions[193:130],
csr_regfile$csr_trap_actions[1:0],
csr_regfile$csr_trap_actions[129:66]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_CSRR_W &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display("%0d: %m.rl_stage1_CSRR_W", csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_CSRR_W_2 &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display("%0d: %m.rl_stage1_CSRR_W_2", csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_CSRR_W_2 && csr_regfile$access_permitted_1 &&
(cur_verbosity__h3946 != 4'd0 ||
csr_regfile$read_csr_minstret[19:0] == 20'd0))
$display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d",
csr_regfile$read_csr_minstret,
rg_csr_pc,
rg_trap_instr,
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_CSRR_W_2 && csr_regfile$access_permitted_1 &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display(" S1: write CSRRW/CSRRWI Rs1 %0d Rs1_val 0x%0h csr 0x%0h csr_val 0x%0h Rd %0d",
rg_trap_instr[19:15],
rs1_val__h34495,
rg_trap_instr[31:20],
csr_regfile$read_csr[63:0],
rg_trap_instr[11:7]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_CSRR_W_2 &&
!csr_regfile$access_permitted_1 &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display(" Trap on CSR permissions: Rs1 %0d Rs1_val 0x%0h csr 0x%0h Rd %0d",
rg_trap_instr[19:15],
rs1_val__h34495,
rg_trap_instr[31:20],
rg_trap_instr[11:7]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display("%0d: %m.rl_stage1_CSRR_S_or_C",
csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display("%0d: %m.rl_stage1_CSRR_S_or_C_2",
csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 &&
csr_regfile$access_permitted_2 &&
(cur_verbosity__h3946 != 4'd0 ||
csr_regfile$read_csr_minstret[19:0] == 20'd0))
$display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d",
csr_regfile$read_csr_minstret,
rg_csr_pc,
rg_trap_instr,
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 &&
csr_regfile$access_permitted_2 &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display(" S1: write CSRR_S_or_C: Rs1 %0d Rs1_val 0x%0h csr 0x%0h csr_val 0x%0h Rd %0d",
rg_trap_instr[19:15],
rs1_val__h35329,
rg_trap_instr[31:20],
csr_regfile$read_csr[63:0],
rg_trap_instr[11:7]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 &&
!csr_regfile$access_permitted_2 &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display(" Trap on CSR permissions: Rs1 %0d Rs1_val 0x%0h csr 0x%0h Rd %0d",
rg_trap_instr[19:15],
rs1_val__h35329,
rg_trap_instr[31:20],
rg_trap_instr[11:7]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_restart_after_csrrx &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display("%0d: %m.rl_stage1_restart_after_csrrx",
csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_restart_after_csrrx &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$write(" %m.CPU_StageF.ma_enq: pc:0x%0h epoch:%0d priv:%0d",
rg_next_pc,
new_epoch__h26813,
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_restart_after_csrrx &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$write(" sstatus_SUM:%0d mstatus_MXR:%0d satp:0x%0h",
csr_regfile$read_sstatus[18],
csr_regfile$read_mstatus[19],
csr_regfile$read_satp);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_restart_after_csrrx &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_restart_after_csrrx &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display(" fa_stageF_redirect: minstret:%0d new_pc:%0x cur_priv:%0d, epoch %0d->%0d",
csr_regfile$read_csr_minstret,
rg_next_pc,
rg_cur_priv,
rg_epoch,
new_epoch__h26813);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_xRET &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display("%0d: %m.rl_stage1_xRET", csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_xRET &&
(cur_verbosity__h3946 != 4'd0 ||
csr_regfile$read_csr_minstret[19:0] == 20'd0))
$display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d",
csr_regfile$read_csr_minstret,
stage1_rg_stage_input[401:338],
stage1_rg_stage_input[263:232],
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_xRET && cur_verbosity__h3946 != 4'd0)
$display(" xRET: next_pc:0x%0h new mstatus:0x%0h new priv:%0d",
csr_regfile$csr_ret_actions[129:66],
csr_regfile$csr_ret_actions[63:0],
csr_regfile$csr_ret_actions[65:64]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_FENCE_I &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display("%0d: %m.rl_stage1_FENCE_I", csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_finish_FENCE_I &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display("%0d: %m.rl_finish_FENCE_I", csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_finish_FENCE_I &&
(cur_verbosity__h3946 != 4'd0 ||
csr_regfile$read_csr_minstret[19:0] == 20'd0))
$display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d",
csr_regfile$read_csr_minstret,
stage1_rg_stage_input[401:338],
stage1_rg_stage_input[263:232],
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_finish_FENCE_I &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$write(" %m.CPU_StageF.ma_enq: pc:0x%0h epoch:%0d priv:%0d",
rg_next_pc,
new_epoch__h26813,
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_finish_FENCE_I &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$write(" sstatus_SUM:%0d mstatus_MXR:%0d satp:0x%0h",
csr_regfile$read_sstatus[18],
csr_regfile$read_mstatus[19],
csr_regfile$read_satp);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_finish_FENCE_I &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_finish_FENCE_I &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display(" fa_stageF_redirect: minstret:%0d new_pc:%0x cur_priv:%0d, epoch %0d->%0d",
csr_regfile$read_csr_minstret,
rg_next_pc,
rg_cur_priv,
rg_epoch,
new_epoch__h26813);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_FENCE &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display("%0d: %m.rl_stage1_FENCE", csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_finish_FENCE &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display("%0d: %m.rl_finish_FENCE", csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_finish_FENCE &&
(cur_verbosity__h3946 != 4'd0 ||
csr_regfile$read_csr_minstret[19:0] == 20'd0))
$display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d",
csr_regfile$read_csr_minstret,
stage1_rg_stage_input[401:338],
stage1_rg_stage_input[263:232],
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_finish_FENCE &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$write(" %m.CPU_StageF.ma_enq: pc:0x%0h epoch:%0d priv:%0d",
rg_next_pc,
new_epoch__h26813,
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_finish_FENCE &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$write(" sstatus_SUM:%0d mstatus_MXR:%0d satp:0x%0h",
csr_regfile$read_sstatus[18],
csr_regfile$read_mstatus[19],
csr_regfile$read_satp);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_finish_FENCE &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_finish_FENCE &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display(" fa_stageF_redirect: minstret:%0d new_pc:%0x cur_priv:%0d, epoch %0d->%0d",
csr_regfile$read_csr_minstret,
rg_next_pc,
rg_cur_priv,
rg_epoch,
new_epoch__h26813);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_SFENCE_VMA &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display("%0d: %m.rl_stage1_SFENCE_VMA", csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_finish_SFENCE_VMA &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display("%0d: %m.rl_finish_SFENCE_VMA", csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_finish_SFENCE_VMA &&
(cur_verbosity__h3946 != 4'd0 ||
csr_regfile$read_csr_minstret[19:0] == 20'd0))
$display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d",
csr_regfile$read_csr_minstret,
stage1_rg_stage_input[401:338],
stage1_rg_stage_input[263:232],
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_finish_SFENCE_VMA &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$write(" %m.CPU_StageF.ma_enq: pc:0x%0h epoch:%0d priv:%0d",
rg_next_pc,
new_epoch__h26813,
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_finish_SFENCE_VMA &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$write(" sstatus_SUM:%0d mstatus_MXR:%0d satp:0x%0h",
csr_regfile$read_sstatus[18],
csr_regfile$read_mstatus[19],
csr_regfile$read_satp);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_finish_SFENCE_VMA &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_finish_SFENCE_VMA &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display(" fa_stageF_redirect: minstret:%0d new_pc:%0x cur_priv:%0d, epoch %0d->%0d",
csr_regfile$read_csr_minstret,
rg_next_pc,
rg_cur_priv,
rg_epoch,
new_epoch__h26813);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_WFI &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display("%0d: %m.rl_stage1_WFI", csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_WFI &&
(cur_verbosity__h3946 != 4'd0 ||
csr_regfile$read_csr_minstret[19:0] == 20'd0))
$display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d",
csr_regfile$read_csr_minstret,
stage1_rg_stage_input[401:338],
stage1_rg_stage_input[263:232],
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_WFI &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display(" CPU.rl_stage1_WFI");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_WFI_resume &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display("%0d: %m.rl_WFI_resume", csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_WFI_resume &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$write(" %m.CPU_StageF.ma_enq: pc:0x%0h epoch:%0d priv:%0d",
rg_next_pc,
new_epoch__h26813,
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_WFI_resume &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$write(" sstatus_SUM:%0d mstatus_MXR:%0d satp:0x%0h",
csr_regfile$read_sstatus[18],
csr_regfile$read_mstatus[19],
csr_regfile$read_satp);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_WFI_resume &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_WFI_resume &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display(" fa_stageF_redirect: minstret:%0d new_pc:%0x cur_priv:%0d, epoch %0d->%0d",
csr_regfile$read_csr_minstret,
rg_next_pc,
rg_cur_priv,
rg_epoch,
new_epoch__h26813);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset_from_WFI &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display("%0d: %m.rl_reset_from_WFI", csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_trap_fetch &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$write(" %m.CPU_StageF.ma_enq: pc:0x%0h epoch:%0d priv:%0d",
rg_next_pc,
new_epoch__h26813,
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_trap_fetch &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$write(" sstatus_SUM:%0d mstatus_MXR:%0d satp:0x%0h",
csr_regfile$read_sstatus[18],
csr_regfile$read_mstatus[19],
csr_regfile$read_satp);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_trap_fetch &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_trap_fetch &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display(" fa_stageF_redirect: minstret:%0d new_pc:%0x cur_priv:%0d, epoch %0d->%0d",
csr_regfile$read_csr_minstret,
rg_next_pc,
rg_cur_priv,
rg_epoch,
new_epoch__h26813);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_interrupt &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display("%0d: %m.rl_stage1_interrupt", csr_regfile$read_csr_mcycle);
if (WILL_FIRE_RL_imem_rl_assert_fail)
begin
v__h2667 = $stime;
#0;
end
v__h2661 = v__h2667 / 32'd10;
if (WILL_FIRE_RL_imem_rl_assert_fail)
$display("%0d: ERROR: CPU_Fetch_C: imem32.is_i32_not_i16 is False",
v__h2661);
if (WILL_FIRE_RL_imem_rl_assert_fail) $finish(32'd1);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset)
$display("%0d: %m.rl_reset_complete: restart at PC = 0x%0h",
csr_regfile$read_csr_mcycle,
soc_map$m_pc_reset_value);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$write(" %m.CPU_StageF.ma_enq: pc:0x%0h epoch:%0d priv:%0d",
soc_map$m_pc_reset_value,
new_epoch__h26813,
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$write(" sstatus_SUM:%0d mstatus_MXR:%0d satp:0x%0h",
csr_regfile$read_sstatus[18],
csr_regfile$read_mstatus[19],
csr_regfile$read_satp);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display(" fa_stageF_redirect: minstret:%0d new_pc:%0x cur_priv:%0d, epoch %0d->%0d",
csr_regfile$read_csr_minstret,
soc_map$m_pc_reset_value,
rg_cur_priv,
rg_epoch,
new_epoch__h26813);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset_complete && !rg_run_on_reset)
$display("%0d: %m.rl_reset_complete: entering DEBUG_MODE",
csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display("%0d: %m.rl_pipe", csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe && stage3_rg_full && stage3_rg_stage3[140] &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56 &&
stage3_rg_stage3[69])
$display(" S3.fa_deq: write FRd 0x%0h, rd_val 0x%0h",
stage3_rg_stage3[139:135],
stage3_rg_stage3[63:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe && stage3_rg_full && stage3_rg_stage3[140] &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56 &&
!stage3_rg_stage3[69])
$display(" S3.fa_deq: write GRd 0x%0h, rd_val 0x%0h",
stage3_rg_stage3[139:135],
stage3_rg_stage3[134:71]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d2376)
$write(" S3.enq: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d2376)
$write("data_to_Stage3 {pc:%h instr:%h priv:%0d\n",
stage2_rg_stage2[493:430],
stage2_rg_stage2[429:398],
stage2_rg_stage2[495:494]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d2376)
$write(" rd_valid:");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
stage2_rg_full_14_AND_IF_stage2_rg_stage2_15_B_ETC___d2379)
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d2381)
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d2383)
$write(" fflags: %05b",
"'h%h",
x_out_data_to_stage3_fpr_flags__h8344);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d2385)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d2387)
$write(" frd:%0d rd_val:%h\n",
x_out_data_to_stage3_rd__h8340,
x_out_data_to_stage3_frd_val__h8345);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d2389)
$write(" grd:%0d rd_val:%h\n",
x_out_data_to_stage3_rd__h8340,
x_out_data_to_stage3_rd_val__h8341);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d2376)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
stage2_rg_full_14_AND_stage2_rg_stage2_15_BITS_ETC___d2395)
$display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d",
csr_regfile$read_csr_minstret,
stage2_rg_stage2[493:430],
stage2_rg_stage2[429:398],
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
(stage2_rg_stage2[397:395] == 3'd0 ||
IF_stage2_rg_stage2_15_BITS_397_TO_395_16_EQ_1_ETC___d2299 ||
!stage2_rg_full) &&
stage1_rg_full &&
!stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d334 &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display(" rl_pipe: Discarding stage1 due to redirection");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2601)
$write(" CPU_Stage2.enq (Data_Stage1_to_Stage2) ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2601)
$write("data_to_Stage 2 {pc:%h instr:%h priv:%0d\n",
stage1_rg_stage_input[401:338],
stage1_rg_stage_input[263:232],
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2601)
$write(" op_stage2:");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2605)
$write("OP_Stage2_ALU");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2609)
$write("OP_Stage2_LD");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2613)
$write("OP_Stage2_ST");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2618)
$write("OP_Stage2_M");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2622)
$write("OP_Stage2_AMO");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2401 &&
stage1_rg_full &&
NOT_stage2_rg_full_14_71_OR_stage2_rg_stage2_1_ETC___d2303 &&
stage1_rg_stage_input_32_BITS_335_TO_334_33_EQ_ETC___d2626)
$write("OP_Stage2_FD");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2601)
$write(" rd:%0d\n", x_out_data_to_stage2_rd__h10119);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2601)
$write(" addr:%h val1:%h val2:%h}",
x_out_data_to_stage2_addr__h10120,
x_out_data_to_stage2_val1__h10121,
x_out_data_to_stage2_val2__h10122);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2601)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2601)
$write(" fval1:%h fval2:%h fval3:%h}",
x_out_data_to_stage2_fval1__h10123,
alu_outputs___1_fval2__h10701,
x_out_data_to_stage2_fval3__h10125);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2601)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2634 &&
stageD_rg_full &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display(" CPU_Stage1.enq: 0x%08h", stageD_rg_data[233:170]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2675 &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display(" CPU_StageD.enq (Data_StageF_to_StageD)");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2675 &&
csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2693 &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$write(" %m.CPU_StageF.ma_enq: pc:0x%0h epoch:%0d priv:%0d",
stageF_branch_predictor$predict_rsp,
stageF_rg_epoch,
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2675 &&
csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2693 &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$write(" sstatus_SUM:%0d mstatus_MXR:%0d satp:0x%0h",
csr_regfile$read_sstatus[18],
csr_regfile$read_mstatus[19],
csr_regfile$read_satp);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d2675 &&
csr_regfile_interrupt_pending_rg_cur_priv_8_28_ETC___d2693 &&
NOT_IF_csr_regfile_read_csr_minstret__0_ULT_cf_ETC___d56)
$display("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset_start)
$display("================================================================");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset_start)
$write("CPU: Bluespec RISC-V Flute v3.0");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset_start) $display(" (RV64)");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset_start)
$display("Copyright (c) 2016-2020 Bluespec, Inc. All Rights Reserved.");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset_start)
$display("================================================================");
end
// synopsys translate_on
endmodule // mkCPU
|
module hi_sniffer(
ck_1356meg,
pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
adc_d, adc_clk,
ssp_frame, ssp_din, ssp_clk
);
input ck_1356meg;
output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
input [7:0] adc_d;
output adc_clk;
output ssp_frame, ssp_din, ssp_clk;
// We are only snooping, all off.
assign pwr_hi = 1'b0;
assign pwr_lo = 1'b0;
assign pwr_oe1 = 1'b0;
assign pwr_oe2 = 1'b0;
assign pwr_oe3 = 1'b0;
assign pwr_oe4 = 1'b0;
reg ssp_frame;
reg [7:0] adc_d_out = 8'd0;
reg [2:0] ssp_cnt = 3'd0;
assign adc_clk = ck_1356meg;
assign ssp_clk = ~ck_1356meg;
always @(posedge ssp_clk)
begin
if(ssp_cnt[2:0] == 3'd7)
ssp_cnt[2:0] <= 3'd0;
else
ssp_cnt <= ssp_cnt + 1;
if(ssp_cnt[2:0] == 3'b000) // set frame length
begin
adc_d_out[7:0] <= adc_d;
ssp_frame <= 1'b1;
end
else
begin
adc_d_out[7:0] <= {1'b0, adc_d_out[7:1]};
ssp_frame <= 1'b0;
end
end
assign ssp_din = adc_d_out[0];
endmodule
|
/*
* Copyright (c) 2015, Ziliang Guo
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Wisconsin Robotics nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL WISCONSIN ROBOTICS BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
`define IDLE_STATE 3'b000
`define PREPAD_STATE 3'b001
`define PRELINE_STATE 3'b010
`define POSTLINE_STATE 3'b011
`define PIXEL_CAPTURE_STATE 3'b100
`define POSTPAD_STATE 3'b101
module cameralink_parser
(
take_photo,
reset_state,
xdata,
cl_clk,
sys_clk,
rst,
pixel_rd_addr,
pixel_rd_data,
capture_state_debug
);
input take_photo;
input reset_state;
input [27:0] xdata;
input cl_clk;
input sys_clk;
input rst;
input [9:0] pixel_rd_addr;
output [15:0] pixel_rd_data;
output [2:0] capture_state_debug;
wire [15:0] pixel_wr_data;
reg [9:0] pixel_wr_addr;
reg [9:0] pixel_wr_addr_next;
wire frame_valid;
wire line_valid;
wire data_valid;
wire pixel_valid;
reg take_photo_reg;
reg [2:0] capture_state;
reg [2:0] capture_state_next;
reg [15:0] counter;
reg [15:0] counter_next;
reg data_wr_en;
wire [3:0] data_bank_wr;
reg [6:0] line_counter;
reg [6:0] line_counter_next;
assign pixel_wr_data[4:0] = xdata[4:0];
assign pixel_wr_data[5] = xdata[6];
assign pixel_wr_data[6] = xdata[27];
assign pixel_wr_data[7] = xdata[5];
assign pixel_wr_data[10:8] = xdata[9:7];
assign pixel_wr_data[13:11] = xdata[14:12];
assign pixel_wr_data[15:14] = xdata[11:10];
assign line_valid = xdata[24];
assign frame_valid = xdata[25];
assign data_valid = xdata[26];
assign pixel_valid = line_valid & frame_valid & data_valid;
assign capture_state_debug = capture_state;
always@(posedge cl_clk) begin
if(reset_state) begin
take_photo_reg <= 1'b0;
counter <= 16'd0;
capture_state <= `IDLE_STATE;
line_counter <= 7'd0;
pixel_wr_addr <= 10'd0;
end
else begin
take_photo_reg <= take_photo;
counter <= counter_next;
capture_state <= capture_state_next;
line_counter <= line_counter_next;
pixel_wr_addr <= pixel_wr_addr_next;
end
end
always@(*) begin
capture_state_next <= capture_state;
counter_next <= counter;
data_wr_en <= 1'b0;
pixel_wr_addr_next <= pixel_wr_addr;
line_counter_next <= line_counter;
case(capture_state)
`IDLE_STATE: begin
counter_next <= 16'd0;
pixel_wr_addr_next <= 12'd0;
line_counter_next <= 7'd0;
if(~take_photo_reg & take_photo) begin
capture_state_next <= `PREPAD_STATE;
end
end
`PREPAD_STATE: begin
if(pixel_valid) begin
counter_next <= counter + 16'd1;
if(counter == 114687) begin
capture_state_next <= `PRELINE_STATE;
counter_next <= 16'd0;
end
end
end
`PRELINE_STATE: begin
if(pixel_valid) begin
counter_next <= counter + 16'd1;
if(counter == 223) begin
capture_state_next <= `PIXEL_CAPTURE_STATE;
counter_next <= 15'd0;
end
end
end
`PIXEL_CAPTURE_STATE: begin
if(pixel_valid) begin
pixel_wr_addr_next <= pixel_wr_addr + 10'd1;
counter_next <= counter + 16'd1;
data_wr_en <= 1'b1;
if(counter == 63) begin
capture_state_next <= `POSTLINE_STATE;
counter_next <= 15'd0;
line_counter_next <= line_counter + 7'd1;
end
end
end
`POSTLINE_STATE: begin
if(pixel_valid) begin
counter_next <= counter + 16'd1;
if(counter == 16'd223) begin
if(line_counter == 7'd64) begin
capture_state_next <= `POSTPAD_STATE;
end
else begin
capture_state_next <= `PRELINE_STATE;
end
counter_next <= 15'd0;
end
end
end
`POSTPAD_STATE: begin
if(pixel_valid) begin
counter_next <= counter + 16'd1;
if(counter == 114687) begin
capture_state_next <= `IDLE_STATE;
counter_next <= 16'd0;
end
end
end
endcase
end
blk_mem blk_mem_inst (
.clka(cl_clk), // input clka
.wea(data_wr_en), // input [0 : 0] wea
.addra(pixel_wr_addr), // input [9 : 0] addra
.dina(pixel_wr_data), // input [15 : 0] dina
.clkb(sys_clk), // input clkb
.addrb(pixel_rd_addr), // input [11 : 0] addrb
.doutb(pixel_rd_data) // output [15 : 0] doutb
);
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O32AI_4_V
`define SKY130_FD_SC_HDLL__O32AI_4_V
/**
* o32ai: 3-input OR and 2-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & (B1 | B2))
*
* Verilog wrapper for o32ai with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__o32ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__o32ai_4 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__o32ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__o32ai_4 (
Y ,
A1,
A2,
A3,
B1,
B2
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__o32ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O32AI_4_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:19:08 12/01/2010
// Design Name:
// Module Name: sd_dma
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module sd_dma(
input [3:0] SD_DAT,
inout SD_CLK,
input CLK,
input SD_DMA_EN,
output SD_DMA_STATUS,
output SD_DMA_SRAM_WE,
output SD_DMA_NEXTADDR,
output [7:0] SD_DMA_SRAM_DATA,
input SD_DMA_PARTIAL,
input [10:0] SD_DMA_PARTIAL_START,
input [10:0] SD_DMA_PARTIAL_END,
input SD_DMA_START_MID_BLOCK,
input SD_DMA_END_MID_BLOCK,
output [10:0] DBG_cyclecnt,
output [2:0] DBG_clkcnt
);
reg [10:0] SD_DMA_STARTr;
reg [10:0] SD_DMA_ENDr;
reg SD_DMA_PARTIALr;
always @(posedge CLK) SD_DMA_PARTIALr <= SD_DMA_PARTIAL;
reg SD_DMA_DONEr;
reg[1:0] SD_DMA_DONEr2;
initial begin
SD_DMA_DONEr2 = 2'b00;
SD_DMA_DONEr = 1'b0;
end
always @(posedge CLK) SD_DMA_DONEr2 <= {SD_DMA_DONEr2[0], SD_DMA_DONEr};
wire SD_DMA_DONE_rising = (SD_DMA_DONEr2[1:0] == 2'b01);
reg [1:0] SD_DMA_ENr;
initial SD_DMA_ENr = 2'b00;
always @(posedge CLK) SD_DMA_ENr <= {SD_DMA_ENr[0], SD_DMA_EN};
wire SD_DMA_EN_rising = (SD_DMA_ENr [1:0] == 2'b01);
reg SD_DMA_STATUSr;
assign SD_DMA_STATUS = SD_DMA_STATUSr;
reg SD_DMA_CLKMASKr = 1'b1;
// we need 1042 cycles (startbit + 1024 nibbles + 16 crc + stopbit)
reg [10:0] cyclecnt;
initial cyclecnt = 11'd0;
reg SD_DMA_SRAM_WEr;
initial SD_DMA_SRAM_WEr = 1'b1;
assign SD_DMA_SRAM_WE = (cyclecnt < 1025 && SD_DMA_STATUSr) ? SD_DMA_SRAM_WEr : 1'b1;
reg SD_DMA_NEXTADDRr;
assign SD_DMA_NEXTADDR = (cyclecnt < 1025 && SD_DMA_STATUSr) ? SD_DMA_NEXTADDRr : 1'b0;
reg[7:0] SD_DMA_SRAM_DATAr;
assign SD_DMA_SRAM_DATA = SD_DMA_SRAM_DATAr;
// we have 4 internal cycles per SD clock, 8 per RAM byte write
reg [2:0] clkcnt;
initial clkcnt = 3'b000;
reg [1:0] SD_CLKr;
initial SD_CLKr = 3'b111;
always @(posedge CLK)
if(SD_DMA_EN_rising) SD_CLKr <= 3'b111;
else SD_CLKr <= {SD_CLKr[0], clkcnt[1]};
assign SD_CLK = SD_DMA_CLKMASKr ? 1'bZ : SD_CLKr[1];
always @(posedge CLK) begin
if(SD_DMA_EN_rising) begin
SD_DMA_STATUSr <= 1'b1;
SD_DMA_STARTr <= (SD_DMA_PARTIALr ? SD_DMA_PARTIAL_START : 11'h0);
SD_DMA_ENDr <= (SD_DMA_PARTIALr ? SD_DMA_PARTIAL_END : 11'd1024);
end
else if (SD_DMA_DONE_rising) SD_DMA_STATUSr <= 1'b0;
end
always @(posedge CLK) begin
if(SD_DMA_EN_rising) begin
SD_DMA_CLKMASKr <= 1'b0;
end
else if (SD_DMA_DONEr) begin
SD_DMA_CLKMASKr <= 1'b1;
end
end
always @(posedge CLK) begin
if(cyclecnt == 1042
|| ((SD_DMA_END_MID_BLOCK & SD_DMA_PARTIALr) && cyclecnt == SD_DMA_PARTIAL_END))
SD_DMA_DONEr <= 1;
else SD_DMA_DONEr <= 0;
end
always @(posedge CLK) begin
if(SD_DMA_EN_rising || !SD_DMA_STATUSr) begin
clkcnt <= 0;
end else begin
if(SD_DMA_STATUSr) begin
clkcnt <= clkcnt + 1;
end
end
end
always @(posedge CLK) begin
if(SD_DMA_EN_rising)
cyclecnt <= (SD_DMA_PARTIALr && SD_DMA_START_MID_BLOCK) ? SD_DMA_PARTIAL_START : 0;
else if(!SD_DMA_STATUSr) cyclecnt <= 0;
else if(clkcnt[1:0] == 2'b10) cyclecnt <= cyclecnt + 1;
end
// we have 8 clk cycles to complete one RAM write
// (4 clk cycles per SD_CLK; 2 SD_CLK cycles per byte)
always @(posedge CLK) begin
if(SD_DMA_STATUSr) begin
case(clkcnt[2:0])
3'h0: begin
SD_DMA_SRAM_DATAr[7:4] <= SD_DAT;
if(cyclecnt>SD_DMA_STARTr && cyclecnt <= SD_DMA_ENDr) SD_DMA_NEXTADDRr <= 1'b1;
end
3'h1: begin
SD_DMA_NEXTADDRr <= 1'b0;
end
3'h2: if(cyclecnt>=SD_DMA_STARTr && cyclecnt < SD_DMA_ENDr) SD_DMA_SRAM_WEr <= 1'b0;
// 3'h3:
3'h4:
SD_DMA_SRAM_DATAr[3:0] <= SD_DAT;
// 3'h5:
// 3'h6:
3'h7:
SD_DMA_SRAM_WEr <= 1'b1;
endcase
end
end
endmodule
|
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