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`default_nettype none
/***********************************************************************************************************************
* Copyright (C) 2016-2017 Andrew Zonenberg and contributors *
* *
* This program is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser General *
* Public License as published by the Free Software Foundation; either version 2.1 of the License, or (at your option) *
* any later version. *
* *
* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied *
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for *
* more details. *
* *
* You should have received a copy of the GNU Lesser General Public License along with this program; if not, you may *
* find one here: *
* https://www.gnu.org/licenses/old-licenses/lgpl-2.1.txt *
* or you may search the http://www.gnu.org website for the version 2.1 license, or you may write to the Free Software *
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA *
**********************************************************************************************************************/
/**
@brief JTAG stuff for an XC2C-series device
*/
module XC2CJTAG(
tdi, tms, tck, tdo,
config_erase,
config_read_en, config_read_addr, config_read_data,
config_write_en, config_write_addr, config_write_data,
config_done, config_done_rst);
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Device configuration
parameter MACROCELLS = 32; //A variant implied for 32/64, no support for base version
parameter PACKAGE = "QFG32"; //Package code (lead-free G assumed)
parameter SHREG_WIDTH = 1; //ISC shift register width
parameter ADDR_BITS = 1; //Bits in ISC address shift register
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// I/Os
input wire tdi;
input wire tms;
input wire tck;
output reg tdo;
//Status signals to the configuration memory
output reg config_erase = 0; //Erases all config memory
//This takes 100 ms IRL but for now we'll model it instantly
output reg config_read_en = 0;
output reg[ADDR_BITS-1:0] config_read_addr = 0; //Address for reading the bitstream (real, not gray code)
input wire[SHREG_WIDTH-1:0] config_read_data;
output reg config_write_en = 0;
output reg[ADDR_BITS-1:0] config_write_addr = 0;
output reg[SHREG_WIDTH-1:0] config_write_data = 0;
output wire config_done;
output reg config_done_rst = 0;
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// The core JTAG state machine
localparam STATE_TEST_LOGIC_RESET = 4'h0;
localparam STATE_RUN_TEST_IDLE = 4'h1;
localparam STATE_SELECT_DR_SCAN = 4'h2;
localparam STATE_SELECT_IR_SCAN = 4'h3;
localparam STATE_CAPTURE_DR = 4'h4;
localparam STATE_CAPTURE_IR = 4'h5;
localparam STATE_SHIFT_DR = 4'h6;
localparam STATE_SHIFT_IR = 4'h7;
localparam STATE_EXIT1_DR = 4'h8;
localparam STATE_EXIT1_IR = 4'h9;
localparam STATE_PAUSE_DR = 4'ha;
localparam STATE_PAUSE_IR = 4'hb;
localparam STATE_EXIT2_DR = 4'hc;
localparam STATE_EXIT2_IR = 4'hd;
localparam STATE_UPDATE_DR = 4'he;
localparam STATE_UPDATE_IR = 4'hf;
reg[3:0] state = STATE_TEST_LOGIC_RESET;
always @(posedge tck) begin
case(state)
STATE_TEST_LOGIC_RESET: begin
if(!tms)
state <= STATE_RUN_TEST_IDLE;
end //end STATE_TEST_LOGIC_RESET
STATE_RUN_TEST_IDLE: begin
if(tms)
state <= STATE_SELECT_DR_SCAN;
end //end STATE_RUN_TEST_IDLE
STATE_SELECT_DR_SCAN: begin
if(tms)
state <= STATE_SELECT_IR_SCAN;
else
state <= STATE_CAPTURE_DR;
end //end STATE_SELECT_DR_SCAN
STATE_SELECT_IR_SCAN: begin
if(tms)
state <= STATE_TEST_LOGIC_RESET;
else
state <= STATE_CAPTURE_IR;
end //end STATE_SELECT_IR_SCAN
STATE_CAPTURE_DR: begin
if(tms)
state <= STATE_EXIT1_DR;
else
state <= STATE_SHIFT_DR;
end //end STATE_CAPTURE_DR
STATE_CAPTURE_IR: begin
if(tms)
state <= STATE_EXIT1_IR;
else
state <= STATE_SHIFT_IR;
end //end STATE_CAPTURE_IR
STATE_SHIFT_DR: begin
if(tms)
state <= STATE_EXIT1_DR;
end //end STATE_SHIFT_DR
STATE_SHIFT_IR: begin
if(tms)
state <= STATE_EXIT1_IR;
end //end STATE_SHIFT_IR
STATE_EXIT1_DR: begin
if(tms)
state <= STATE_UPDATE_DR;
else
state <= STATE_PAUSE_DR;
end //end STATE_EXIT1_DR
STATE_EXIT1_IR: begin
if(tms)
state <= STATE_UPDATE_IR;
else
state <= STATE_PAUSE_IR;
end //end STATE_EXIT1_IR
STATE_PAUSE_DR: begin
if(tms)
state <= STATE_EXIT2_DR;
end //end STATE_PAUSE_DR
STATE_PAUSE_IR: begin
if(tms)
state <= STATE_EXIT2_IR;
end //end STATE_PAUSE_IR
STATE_EXIT2_DR: begin
if(tms)
state <= STATE_UPDATE_DR;
else
state <= STATE_SHIFT_DR;
end //end STATE_EXIT2_DR
STATE_EXIT2_IR: begin
if(tms)
state <= STATE_UPDATE_IR;
else
state <= STATE_SHIFT_IR;
end //end STATE_EXIT2_IR
STATE_UPDATE_DR: begin
if(tms)
state <= STATE_SELECT_DR_SCAN;
else
state <= STATE_RUN_TEST_IDLE;
end //end STATE_UPDATE_DR
STATE_UPDATE_IR: begin
if(tms)
state <= STATE_SELECT_IR_SCAN;
else
state <= STATE_RUN_TEST_IDLE;
end //end STATE_UPDATE_IR
endcase
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Device configuration states
reg isc_enabled = 0;
reg isc_disabled = 0;
reg configured = 0;
reg read_locked = 0;
assign config_done = configured;
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// The instruction register
//see XC2C programmer qualification spec v1.3 p25-26
localparam INST_EXTEST = 8'h00;
localparam INST_IDCODE = 8'h01;
localparam INST_INTEST = 8'h02;
localparam INST_SAMPLE_PRELOAD = 8'h03;
localparam INST_TEST_ENABLE = 8'h11; //Private1, got this info from BSDL
localparam INST_BULKPROG = 8'h12; //Private2, got this info from BSDL
//Guessing this programs the IDCODE memory etc
localparam INST_MVERIFY = 8'h13; //Private3, got this info from BSDL
//Guessing this is a full read including IDCODE.
//May bypass protection?
localparam INST_ERASE_ALL = 8'h14; //Private4, got this info from BSDL
//Probably wipes IDCODE too
localparam INST_TEST_DISABLE = 8'h15; //Private5, got this info from BSDL
localparam INST_STCTEST = 8'h16; //Private6, got this info from BSDL.
//Note, it was commented out there! Wonder why...
localparam INST_ISC_DISABLE = 8'hc0;
localparam INST_ISC_NOOP = 8'he0;
localparam INST_ISC_ENABLEOTF = 8'he4;
localparam INST_ISC_SRAM_WRITE = 8'he6;
localparam INST_ISC_SRAM_READ = 8'he7;
localparam INST_ISC_ENABLE = 8'he8;
localparam INST_ISC_ENABLE_CLAMP = 8'he9;
localparam INST_ISC_PROGRAM = 8'hea;
localparam INST_ISC_ERASE = 8'hed;
localparam INST_ISC_READ = 8'hee;
localparam INST_ISC_INIT = 8'hf0;
localparam INST_CLAMP = 8'hfa;
localparam INST_HIGHZ = 8'hfc;
localparam INST_USERCODE = 8'hfd;
localparam INST_BYPASS = 8'hff;
reg[7:0] ir = INST_IDCODE;
reg[7:0] ir_shreg = 0;
reg programming = 0;
//Instruction loading and capture
always @(posedge tck) begin
config_erase <= 0;
config_done_rst <= 0;
case(state)
//Reset instruction to IDCODE upon reset
STATE_TEST_LOGIC_RESET: begin
ir <= INST_IDCODE;
end //end STATE_TEST_LOGIC_RESET
//Instruction capture, per XC2C programming spec figure 12 (p. 21)
STATE_CAPTURE_IR: begin
ir_shreg[7:6] <= 2'b00;
ir_shreg[5] <= isc_disabled;
ir_shreg[4] <= isc_enabled;
ir_shreg[3] <= read_locked;
ir_shreg[2] <= configured;
ir_shreg[1:0] <= 2'b01;
end //end STATE_CAPTURE_IR
//Loading a new IR
STATE_SHIFT_IR: begin
ir_shreg <= {tdi, ir_shreg[7:1]};
end //end STATE_SHIFT_IR
//Done, save the new IR
STATE_UPDATE_IR: begin
ir <= ir_shreg;
//If we're entering/exiting ISC mode, set the ISC bits appropriately
//TODO: support OTF mode
if(ir_shreg == INST_ISC_ENABLE)
isc_enabled <= 1;
if(ir_shreg == INST_ISC_DISABLE) begin
programming <= 0;
isc_enabled <= 0;
end
//Wipe config memory when we get an ERASE instruction
if(ir_shreg == INST_ISC_ERASE) begin
config_erase <= 1;
configured <= 0;
end
//Declare us to be programming when we load ISC_PROGRAM
//TODO: check DONE / transfer bits first
if(ir_shreg == INST_ISC_PROGRAM) begin
programming <= 1;
end
//If we leave programming mode after programming, set us to be done and reset everything
if(ir_shreg == INST_ISC_DISABLE && programming) begin
configured <= 1;
config_done_rst <= 1;
`ifdef XILINX_ISIM
$display("Configuration complete");
`endif
end
//TODO: copy EEPROM to RAM when we get an ISC_INIT command
end //end STATE_UPDATE_IR
endcase
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// BYPASS DR
reg bypass_shreg = 0;
always @(posedge tck) begin
case(state)
STATE_SHIFT_DR: begin
bypass_shreg <= tdi;
end //end STATE_SHIFT_DR
endcase
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// IDCODE DR
reg[31:0] idcode;
initial begin
idcode[31:28] <= 4'hf; //stepping 0xF, this hopefully doesn't exist IRL
idcode[27:25] <= 3'h3; //CoolRunner-II
idcode[24:22] <= 3'h3; //CoolRunner-II
//Macrocell count
case(MACROCELLS)
32: idcode[21:16] <= 6'h21; //01 = xc2c32, not supported
64: idcode[21:16] <= 6'h25; //05 = xc2c64, not supported
128: idcode[21:16] <= 6'h18;
256: idcode[21:16] <= 6'h14;
384: idcode[21:16] <= 6'h15;
512: idcode[21:16] <= 6'h17;
default: idcode[21:16] <= 0;
endcase
idcode[15] <= 1'h1; //always 1
//Package identifier
case(MACROCELLS)
32: begin
if(PACKAGE == "QFG32")
idcode[14:12] <= 3'h1;
else if(PACKAGE == "CPG56")
idcode[14:12] <= 3'h3;
else if(PACKAGE == "VQG44")
idcode[14:12] <= 3'h4;
else begin
$display("Invalid package %s for 32 macrocells", PACKAGE);
$finish;
end
end
64: begin
if(PACKAGE == "VQG44")
idcode[14:12] <= 3'h6;
else if(PACKAGE == "QFG48")
idcode[14:12] <= 3'h1;
else if(PACKAGE == "CPG56")
idcode[14:12] <= 3'h5;
else if(PACKAGE == "VQG100")
idcode[14:12] <= 3'h4;
else if(PACKAGE == "CPG132")
idcode[14:12] <= 3'h3;
else begin
$display("Invalid package %s for 64 macrocells", PACKAGE);
$finish;
end
end
128: begin
if(PACKAGE == "VQG100")
idcode[14:12] <= 3'h2;
else if(PACKAGE == "CPG132")
idcode[14:12] <= 3'h3;
else if(PACKAGE == "TQG144")
idcode[14:12] <= 3'h4;
else if(PACKAGE == "FTG256")
idcode[14:12] <= 3'h6;
else begin
$display("Invalid package %s for 128 macrocells", PACKAGE);
$finish;
end
end
256: begin
if(PACKAGE == "VQG100")
idcode[14:12] <= 3'h2;
else if(PACKAGE == "CPG132")
idcode[14:12] <= 3'h3;
else if(PACKAGE == "TQG144")
idcode[14:12] <= 3'h4;
else if(PACKAGE == "PQG208")
idcode[14:12] <= 3'h5;
else if(PACKAGE == "FTG256")
idcode[14:12] <= 3'h6;
else begin
$display("Invalid package %s for 256 macrocells", PACKAGE);
$finish;
end
end
384: begin
if(PACKAGE == "TQG144")
idcode[14:12] <= 3'h4;
else if(PACKAGE == "PQG208")
idcode[14:12] <= 3'h5;
else if(PACKAGE == "FTG256")
idcode[14:12] <= 3'h7;
else if(PACKAGE == "FGG324")
idcode[14:12] <= 3'h2;
else begin
$display("Invalid package %s for 384 macrocells", PACKAGE);
$finish;
end
end
512: begin
if(PACKAGE == "PQG208")
idcode[14:12] <= 3'h4;
else if(PACKAGE == "FTG256")
idcode[14:12] <= 3'h6;
else if(PACKAGE == "FGG324")
idcode[14:12] <= 3'h2;
else begin
$display("Invalid package %s for 512 macrocells", PACKAGE);
$finish;
end
end
default: begin
$display("Don't have package IDs coded up for other densities yet\n");
$finish;
end
endcase
idcode[11:0] <= 12'h093; //Xilinx vendor code
end
reg[31:0] idcode_shreg = 0;
always @(posedge tck) begin
case(state)
//IDCODE capture
STATE_CAPTURE_DR: begin
idcode_shreg <= idcode;
end //end STATE_CAPTURE_DR
//Read the IDCODE
STATE_SHIFT_DR: begin
idcode_shreg <= {tdi, idcode_shreg[31:1]};
end //end STATE_SHIFT_DR
//no update, writes to IDCODE are ignored
endcase
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Gray code decode ROM
reg[7:0] gray_to_bin[255:0];
integer i;
initial begin
for(i=0; i<256; i=i+1)
gray_to_bin[i ^ (i >> 1)] <= i[7:0];
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Config memory read
reg[SHREG_WIDTH-1:0] isc_read_shreg = 0;
//New value for the read shreg
wire[SHREG_WIDTH-1:0] isc_read_shreg_adv = {tdi, isc_read_shreg[SHREG_WIDTH-1:1]};
//Gray coded read address: left N bits of the shift register
wire[ADDR_BITS-1:0] isc_read_addr_gray = isc_read_shreg[SHREG_WIDTH-1 : SHREG_WIDTH-ADDR_BITS];
//Invert the bit ordering of the address since the protocol is weird and has MSB at right
reg[ADDR_BITS-1:0] isc_read_addr_gray_flipped;
always @(*) begin
for(i=0; i<ADDR_BITS; i=i+1)
isc_read_addr_gray_flipped[i] <= isc_read_addr_gray[ADDR_BITS - 1 - i];
end
reg config_read_real = 0;
always @(posedge tck) begin
config_read_en <= 0;
if(ir == INST_ISC_READ) begin
case(state)
//Load the data that we read
STATE_CAPTURE_DR: begin
isc_read_shreg <= config_read_data;
end //end STATE_CAPTURE_DR
//Actual readout happens here
STATE_SHIFT_DR: begin
isc_read_shreg <= isc_read_shreg_adv;
end //end STATE_SHIFT_DR
//Update: save the de-Gray-ified read address
STATE_UPDATE_DR: begin
config_read_en <= 1;
config_read_addr <= gray_to_bin[isc_read_addr_gray_flipped][ADDR_BITS-1:0];
end //end STATE_UPDATE_DR
endcase
end
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Config memory writes
localparam WRITE_WIDTH = SHREG_WIDTH + ADDR_BITS;
reg[WRITE_WIDTH - 1 : 0] isc_write_shreg = 0;
//Gray coded write address: left N bits of the shift register
wire[ADDR_BITS-1:0] isc_write_addr_gray = isc_write_shreg[SHREG_WIDTH +: ADDR_BITS];
//Invert the bit ordering of the address since the protocol is weird and has MSB at right
reg[ADDR_BITS-1:0] isc_write_addr_gray_flipped;
always @(*) begin
for(i=0; i<ADDR_BITS; i=i+1)
isc_write_addr_gray_flipped[i] <= isc_write_addr_gray[ADDR_BITS - 1 - i];
end
always @(posedge tck) begin
config_write_en <= 0;
if(ir == INST_ISC_PROGRAM) begin
case(state)
//Capture data is ignored
STATE_CAPTURE_DR: begin
isc_write_shreg <= 0;
end //end STATE_CAPTURE_DR
//Read the new bitstream
STATE_SHIFT_DR: begin
isc_write_shreg <= {tdi, isc_write_shreg[WRITE_WIDTH - 1 : 1]};
end //end STATE_SHIFT_DR
//Update: commit the write to bitstream
STATE_UPDATE_DR: begin
config_write_en <= 1;
config_write_addr <= gray_to_bin[isc_write_addr_gray_flipped][ADDR_BITS-1:0];
config_write_data <= isc_write_shreg[SHREG_WIDTH-1 : 0];
end //end STATE_UPDATE_DR
endcase
end
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// TDO muxing
always @(*) begin
tdo <= 0;
//IR stuff
if(state == STATE_SHIFT_IR)
tdo <= ir_shreg[0];
//DR stuff
else if(state == STATE_SHIFT_DR) begin
case(ir)
INST_BYPASS: tdo <= bypass_shreg;
INST_IDCODE: tdo <= idcode_shreg[0];
INST_ISC_READ: tdo <= isc_read_shreg[0];
INST_ISC_PROGRAM: tdo <= isc_write_shreg[0];
endcase
end
end
endmodule
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.4 (win64) Build 1071353 Tue Nov 18 18:29:27 MST 2014
// Date : Mon May 25 17:58:01 2015
// Host : Dtysky running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// b:/Complex_Mind/FPGA-Imaging-Library/Master/Generator/FrameController2/HDL/FrameController2.srcs/sources_1/ip/Multiplier12x12FR2/Multiplier12x12FR2_funcsim.v
// Design : Multiplier12x12FR2
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "mult_gen_v12_0,Vivado 2014.4" *) (* CHECK_LICENSE_TYPE = "Multiplier12x12FR2,mult_gen_v12_0,{}" *)
(* core_generation_info = "Multiplier12x12FR2,mult_gen_v12_0,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=mult_gen,x_ipVersion=12.0,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_VERBOSITY=0,C_MODEL_TYPE=0,C_OPTIMIZE_GOAL=1,C_XDEVICEFAMILY=zynq,C_HAS_CE=0,C_HAS_SCLR=1,C_LATENCY=3,C_A_WIDTH=12,C_A_TYPE=1,C_B_WIDTH=12,C_B_TYPE=1,C_OUT_HIGH=23,C_OUT_LOW=0,C_MULT_TYPE=1,C_CE_OVERRIDES_SCLR=0,C_CCM_IMP=0,C_B_VALUE=10000001,C_HAS_ZERO_DETECT=0,C_ROUND_OUTPUT=0,C_ROUND_PT=0}" *)
(* NotValidForBitStream *)
module Multiplier12x12FR2
(CLK,
A,
B,
SCLR,
P);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk_intf CLK" *) input CLK;
input [11:0]A;
input [11:0]B;
(* x_interface_info = "xilinx.com:signal:reset:1.0 sclr_intf RST" *) input SCLR;
output [23:0]P;
wire [11:0]A;
wire [11:0]B;
wire CLK;
wire [23:0]P;
wire SCLR;
wire [47:0]NLW_U0_PCASC_UNCONNECTED;
wire [1:0]NLW_U0_ZERO_DETECT_UNCONNECTED;
(* C_A_TYPE = "1" *)
(* C_A_WIDTH = "12" *)
(* C_B_TYPE = "1" *)
(* C_B_VALUE = "10000001" *)
(* C_B_WIDTH = "12" *)
(* C_CCM_IMP = "0" *)
(* C_CE_OVERRIDES_SCLR = "0" *)
(* C_HAS_CE = "0" *)
(* C_HAS_SCLR = "1" *)
(* C_HAS_ZERO_DETECT = "0" *)
(* C_LATENCY = "3" *)
(* C_MODEL_TYPE = "0" *)
(* C_MULT_TYPE = "1" *)
(* C_OPTIMIZE_GOAL = "1" *)
(* C_OUT_HIGH = "23" *)
(* C_OUT_LOW = "0" *)
(* C_ROUND_OUTPUT = "0" *)
(* C_ROUND_PT = "0" *)
(* C_VERBOSITY = "0" *)
(* C_XDEVICEFAMILY = "zynq" *)
(* DONT_TOUCH *)
(* downgradeipidentifiedwarnings = "yes" *)
Multiplier12x12FR2_mult_gen_v12_0__parameterized0 U0
(.A(A),
.B(B),
.CE(1'b1),
.CLK(CLK),
.P(P),
.PCASC(NLW_U0_PCASC_UNCONNECTED[47:0]),
.SCLR(SCLR),
.ZERO_DETECT(NLW_U0_ZERO_DETECT_UNCONNECTED[1:0]));
endmodule
(* ORIG_REF_NAME = "mult_gen_v12_0" *) (* C_VERBOSITY = "0" *) (* C_MODEL_TYPE = "0" *)
(* C_OPTIMIZE_GOAL = "1" *) (* C_XDEVICEFAMILY = "zynq" *) (* C_HAS_CE = "0" *)
(* C_HAS_SCLR = "1" *) (* C_LATENCY = "3" *) (* C_A_WIDTH = "12" *)
(* C_A_TYPE = "1" *) (* C_B_WIDTH = "12" *) (* C_B_TYPE = "1" *)
(* C_OUT_HIGH = "23" *) (* C_OUT_LOW = "0" *) (* C_MULT_TYPE = "1" *)
(* C_CE_OVERRIDES_SCLR = "0" *) (* C_CCM_IMP = "0" *) (* C_B_VALUE = "10000001" *)
(* C_HAS_ZERO_DETECT = "0" *) (* C_ROUND_OUTPUT = "0" *) (* C_ROUND_PT = "0" *)
(* downgradeipidentifiedwarnings = "yes" *)
module Multiplier12x12FR2_mult_gen_v12_0__parameterized0
(CLK,
A,
B,
CE,
SCLR,
ZERO_DETECT,
P,
PCASC);
input CLK;
input [11:0]A;
input [11:0]B;
input CE;
input SCLR;
output [1:0]ZERO_DETECT;
output [23:0]P;
output [47:0]PCASC;
wire [11:0]A;
wire [11:0]B;
wire CE;
wire CLK;
wire [23:0]P;
wire [47:0]PCASC;
wire SCLR;
wire [1:0]ZERO_DETECT;
(* C_A_TYPE = "1" *)
(* C_A_WIDTH = "12" *)
(* C_B_TYPE = "1" *)
(* C_B_VALUE = "10000001" *)
(* C_B_WIDTH = "12" *)
(* C_CCM_IMP = "0" *)
(* C_CE_OVERRIDES_SCLR = "0" *)
(* C_HAS_CE = "0" *)
(* C_HAS_SCLR = "1" *)
(* C_HAS_ZERO_DETECT = "0" *)
(* C_LATENCY = "3" *)
(* C_MODEL_TYPE = "0" *)
(* C_MULT_TYPE = "1" *)
(* C_OPTIMIZE_GOAL = "1" *)
(* C_OUT_HIGH = "23" *)
(* C_OUT_LOW = "0" *)
(* C_ROUND_OUTPUT = "0" *)
(* C_ROUND_PT = "0" *)
(* C_VERBOSITY = "0" *)
(* C_XDEVICEFAMILY = "zynq" *)
(* downgradeipidentifiedwarnings = "yes" *)
Multiplier12x12FR2_mult_gen_v12_0_viv__parameterized0 i_mult
(.A(A),
.B(B),
.CE(CE),
.CLK(CLK),
.P(P),
.PCASC(PCASC),
.SCLR(SCLR),
.ZERO_DETECT(ZERO_DETECT));
endmodule
`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "XILINX"
`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`pragma protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`pragma protect key_block
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`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`pragma protect key_block
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oTd41gw6CHpypaHAd88=
`pragma protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
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bJafuR2HkqxTvqwCTed3PqEy4xVdmr/ecywIlw==
`pragma protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`pragma protect key_block
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`pragma protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
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`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-PREC-RSA", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
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DAazbkQr6F8mRVFAdDPN33HbTi2PEVrcASQmYw==
`pragma protect key_keyowner = "Synplicity", key_keyname= "SYNP05_001", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
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`pragma protect data_method = "AES128-CBC"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 7328)
`pragma protect data_block
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mJGQWGtDNwh7udiFtcXfpAANZVOadg1Z2/oYtZK43PQ=
`pragma protect end_protected
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
//---------------------------------------------------------------------------
//-- Copyright 2015 - 2017 Systems Group, ETH Zurich
//--
//-- This hardware module is free software: you can redistribute it and/or
//-- modify it under the terms of the GNU General Public License as published
//-- by the Free Software Foundation, either version 3 of the License, or
//-- (at your option) any later version.
//--
//-- This program is distributed in the hope that it will be useful,
//-- but WITHOUT ANY WARRANTY; without even the implied warranty of
//-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
//-- GNU General Public License for more details.
//--
//-- You should have received a copy of the GNU General Public License
//-- along with this program. If not, see <http://www.gnu.org/licenses/>.
//---------------------------------------------------------------------------
module nukv_Feedback #(
parameter KEY_WIDTH = 128,
parameter META_WIDTH = 96
)
(
// Clock
input wire clk,
input wire rst,
input wire [KEY_WIDTH+META_WIDTH-1:0] fb_in_data,
input wire fb_in_valid,
output wire fb_in_ready,
output wire [KEY_WIDTH+META_WIDTH-1:0] fb_out_data,
output wire fb_out_valid,
input wire fb_out_ready,
input wire [KEY_WIDTH+META_WIDTH-1:0] reg_in_data,
input wire reg_in_valid,
output wire reg_in_ready,
output wire [KEY_WIDTH+META_WIDTH-1:0] reg_out_data,
output wire reg_out_valid,
input wire reg_out_ready
);
endmodule |
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's Instruction MMU top level ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Instantiation of all IMMU blocks. ////
//// ////
//// To Do: ////
//// - cache inhibit ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.14 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.12.4.2 2003/12/09 11:46:48 simons
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
//
// Revision 1.12.4.1 2003/07/08 15:36:37 lampret
// Added embedded memory QMEM.
//
// Revision 1.12 2003/06/06 02:54:47 lampret
// When OR1200_NO_IMMU and OR1200_NO_IC are not both defined or undefined at the same time, results in a IC bug. Fixed.
//
// Revision 1.11 2002/10/17 20:04:40 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.10 2002/09/16 03:08:56 lampret
// Disabled cache inhibit atttribute.
//
// Revision 1.9 2002/08/18 19:54:17 lampret
// Added store buffer.
//
// Revision 1.8 2002/08/14 06:23:50 lampret
// Disabled ITLB translation when 1) doing access to ITLB SPRs or 2) crossing page. This modification was tested only with parts of IMMU test - remaining test cases needs to be run.
//
// Revision 1.7 2002/08/12 05:31:30 lampret
// Delayed external access at page crossing.
//
// Revision 1.6 2002/03/29 15:16:56 lampret
// Some of the warnings fixed.
//
// Revision 1.5 2002/02/11 04:33:17 lampret
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
//
// Revision 1.4 2002/02/01 19:56:54 lampret
// Fixed combinational loops.
//
// Revision 1.3 2002/01/28 01:16:00 lampret
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
//
// Revision 1.2 2002/01/14 06:18:22 lampret
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.6 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.5 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
// no message
//
// Revision 1.1 2001/08/17 08:03:35 lampret
// *** empty log message ***
//
// Revision 1.2 2001/07/22 03:31:53 lampret
// Fixed RAM's oen bug. Cache bypass under development.
//
// Revision 1.1 2001/07/20 00:46:03 lampret
// Development version of RTL. Libraries are missing.
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
//
// Insn MMU
//
module or1200_immu_top(
// Rst and clk
clk, rst,
// CPU i/f
ic_en, immu_en, supv, icpu_adr_i, icpu_cycstb_i,
icpu_adr_o, icpu_tag_o, icpu_rty_o, icpu_err_o,
// SPR access
spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// QMEM i/f
qmemimmu_rty_i, qmemimmu_err_i, qmemimmu_tag_i, qmemimmu_adr_o, qmemimmu_cycstb_o, qmemimmu_ci_o
);
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_OPERAND_WIDTH;
//
// I/O
//
//
// Clock and reset
//
input clk;
input rst;
//
// CPU I/F
//
input ic_en;
input immu_en;
input supv;
input [aw-1:0] icpu_adr_i;
input icpu_cycstb_i;
output [aw-1:0] icpu_adr_o;
output [3:0] icpu_tag_o;
output icpu_rty_o;
output icpu_err_o;
//
// SPR access
//
input spr_cs;
input spr_write;
input [aw-1:0] spr_addr;
input [31:0] spr_dat_i;
output [31:0] spr_dat_o;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
//
// IC I/F
//
input qmemimmu_rty_i;
input qmemimmu_err_i;
input [3:0] qmemimmu_tag_i;
output [aw-1:0] qmemimmu_adr_o;
output qmemimmu_cycstb_o;
output qmemimmu_ci_o;
//
// Internal wires and regs
//
wire itlb_spr_access;
wire [31:`OR1200_IMMU_PS] itlb_ppn;
wire itlb_hit;
wire itlb_uxe;
wire itlb_sxe;
wire [31:0] itlb_dat_o;
wire itlb_en;
wire itlb_ci;
wire itlb_done;
wire fault;
wire miss;
wire page_cross;
reg [31:0] icpu_adr_o;
reg [31:`OR1200_IMMU_PS] icpu_vpn_r;
`ifdef OR1200_NO_IMMU
`else
reg itlb_en_r;
reg dis_spr_access;
`endif
//
// Implemented bits inside match and translate registers
//
// itlbwYmrX: vpn 31-10 v 0
// itlbwYtrX: ppn 31-10 uxe 7 sxe 6
//
// itlb memory width:
// 19 bits for ppn
// 13 bits for vpn
// 1 bit for valid
// 2 bits for protection
// 1 bit for cache inhibit
//
// icpu_adr_o
//
`ifdef OR1200_REGISTERED_OUTPUTS
always @(posedge rst or posedge clk)
if (rst)
icpu_adr_o <= #1 32'h0000_0100;
else
icpu_adr_o <= #1 icpu_adr_i;
`else
Unsupported !!!
`endif
//
// Page cross
//
// Asserted when CPU address crosses page boundary. Most of the time it is zero.
//
assign page_cross = icpu_adr_i[31:`OR1200_IMMU_PS] != icpu_vpn_r;
//
// Register icpu_adr_i's VPN for use when IMMU is not enabled but PPN is expected to come
// one clock cycle after offset part.
//
always @(posedge clk or posedge rst)
if (rst)
icpu_vpn_r <= #1 {32-`OR1200_IMMU_PS{1'b0}};
else
icpu_vpn_r <= #1 icpu_adr_i[31:`OR1200_IMMU_PS];
`ifdef OR1200_NO_IMMU
//
// Put all outputs in inactive state
//
assign spr_dat_o = 32'h00000000;
assign qmemimmu_adr_o = icpu_adr_i;
assign icpu_tag_o = qmemimmu_tag_i;
assign qmemimmu_cycstb_o = icpu_cycstb_i & ~page_cross;
assign icpu_rty_o = qmemimmu_rty_i;
assign icpu_err_o = qmemimmu_err_i;
assign qmemimmu_ci_o = `OR1200_IMMU_CI;
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
`else
//
// ITLB SPR access
//
// 1200 - 12FF itlbmr w0
// 1200 - 123F itlbmr w0 [63:0]
//
// 1300 - 13FF itlbtr w0
// 1300 - 133F itlbtr w0 [63:0]
//
assign itlb_spr_access = spr_cs & ~dis_spr_access;
//
// Disable ITLB SPR access
//
// This flop is used to mask ITLB miss/fault exception
// during first clock cycle of accessing ITLB SPR. In
// subsequent clock cycles it is assumed that ITLB SPR
// access was accomplished and that normal instruction fetching
// can proceed.
//
// spr_cs sets dis_spr_access and icpu_rty_o clears it.
//
always @(posedge clk or posedge rst)
if (rst)
dis_spr_access <= #1 1'b0;
else if (!icpu_rty_o)
dis_spr_access <= #1 1'b0;
else if (spr_cs)
dis_spr_access <= #1 1'b1;
//
// Tags:
//
// OR1200_DTAG_TE - TLB miss Exception
// OR1200_DTAG_PE - Page fault Exception
//
assign icpu_tag_o = miss ? `OR1200_DTAG_TE : fault ? `OR1200_DTAG_PE : qmemimmu_tag_i;
//
// icpu_rty_o
//
// assign icpu_rty_o = !icpu_err_o & qmemimmu_rty_i;
assign icpu_rty_o = qmemimmu_rty_i | itlb_spr_access & immu_en;
//
// icpu_err_o
//
assign icpu_err_o = miss | fault | qmemimmu_err_i;
//
// Assert itlb_en_r after one clock cycle and when there is no
// ITLB SPR access
//
always @(posedge clk or posedge rst)
if (rst)
itlb_en_r <= #1 1'b0;
else
itlb_en_r <= #1 itlb_en & ~itlb_spr_access;
//
// ITLB lookup successful
//
assign itlb_done = itlb_en_r & ~page_cross;
//
// Cut transfer if something goes wrong with translation. If IC is disabled,
// use delayed signals.
//
// assign qmemimmu_cycstb_o = (!ic_en & immu_en) ? ~(miss | fault) & icpu_cycstb_i & ~page_cross : (miss | fault) ? 1'b0 : icpu_cycstb_i & ~page_cross; // DL
assign qmemimmu_cycstb_o = immu_en ? ~(miss | fault) & icpu_cycstb_i & ~page_cross & itlb_done : icpu_cycstb_i & ~page_cross;
//
// Cache Inhibit
//
// Cache inhibit is not really needed for instruction memory subsystem.
// If we would doq it, we would doq it like this.
// assign qmemimmu_ci_o = immu_en ? itlb_done & itlb_ci : `OR1200_IMMU_CI;
// However this causes a async combinational loop so we stick to
// no cache inhibit.
assign qmemimmu_ci_o = `OR1200_IMMU_CI;
//
// Physical address is either translated virtual address or
// simply equal when IMMU is disabled
//
assign qmemimmu_adr_o = itlb_done ? {itlb_ppn, icpu_adr_i[`OR1200_IMMU_PS-1:0]} : {icpu_vpn_r, icpu_adr_i[`OR1200_IMMU_PS-1:0]}; // DL: immu_en
//
// Output to SPRS unit
//
assign spr_dat_o = spr_cs ? itlb_dat_o : 32'h00000000;
//
// Page fault exception logic
//
assign fault = itlb_done &
( (!supv & !itlb_uxe) // Execute in user mode not enabled
|| (supv & !itlb_sxe)); // Execute in supv mode not enabled
//
// TLB Miss exception logic
//
assign miss = itlb_done & !itlb_hit;
//
// ITLB Enable
//
assign itlb_en = immu_en & icpu_cycstb_i;
//
// Instantiation of ITLB
//
or1200_immu_tlb or1200_immu_tlb(
// Rst and clk
.clk(clk),
.rst(rst),
// I/F for translation
.tlb_en(itlb_en),
.vaddr(icpu_adr_i),
.hit(itlb_hit),
.ppn(itlb_ppn),
.uxe(itlb_uxe),
.sxe(itlb_sxe),
.ci(itlb_ci),
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
// SPR access
.spr_cs(itlb_spr_access),
.spr_write(spr_write),
.spr_addr(spr_addr),
.spr_dat_i(spr_dat_i),
.spr_dat_o(itlb_dat_o)
);
`endif
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:50:10 11/03/2014
// Design Name:
// Module Name: Output_2_Disp
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Multi_8CH32(input clk,
input rst,
input EN, //Write EN
input[2:0]Test, //ALU&Clock,SW[7:5]
input[63:0]point_in, //Õë¶Ô8λÏÔʾÊäÈë¸÷8¸öСÊýµã
input[63:0]LES, //Õë¶Ô8λÏÔʾÊäÈë¸÷8¸öÉÁ˸λ
input[31:0] Data0, //disp_cpudata
input[31:0] data1,
input[31:0] data2,
input[31:0] data3,
input[31:0] data4,
input[31:0] data5,
input[31:0] data6,
input[31:0] data7,
output [7:0] point_out,
output [7:0] LE_out,
output [31:0]Disp_num
);
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// File name: axi_protocol_converter_v2_1_b2s_b_channel.v
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_b2s_b_channel #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of ID signals.
// Range: >= 1.
parameter integer C_ID_WIDTH = 4
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire clk,
input wire reset,
// AXI signals
output wire [C_ID_WIDTH-1:0] s_bid,
output wire [1:0] s_bresp,
output wire s_bvalid,
input wire s_bready,
input wire [1:0] m_bresp,
input wire m_bvalid,
output wire m_bready,
// Signals to/from the axi_protocol_converter_v2_1_b2s_aw_channel modules
input wire b_push,
input wire [C_ID_WIDTH-1:0] b_awid,
input wire [7:0] b_awlen,
input wire b_resp_rdy,
output wire b_full
);
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
// AXI protocol responses:
localparam [1:0] LP_RESP_OKAY = 2'b00;
localparam [1:0] LP_RESP_EXOKAY = 2'b01;
localparam [1:0] LP_RESP_SLVERROR = 2'b10;
localparam [1:0] LP_RESP_DECERR = 2'b11;
// FIFO settings
localparam P_WIDTH = C_ID_WIDTH + 8;
localparam P_DEPTH = 4;
localparam P_AWIDTH = 2;
localparam P_RWIDTH = 2;
localparam P_RDEPTH = 4;
localparam P_RAWIDTH = 2;
////////////////////////////////////////////////////////////////////////////////
// Wire and register declarations
////////////////////////////////////////////////////////////////////////////////
reg bvalid_i;
wire [C_ID_WIDTH-1:0] bid_i;
wire shandshake;
reg shandshake_r;
wire mhandshake;
reg mhandshake_r;
wire b_empty;
wire bresp_full;
wire bresp_empty;
wire [7:0] b_awlen_i;
reg [7:0] bresp_cnt;
reg [1:0] s_bresp_acc;
wire [1:0] s_bresp_acc_r;
reg [1:0] s_bresp_i;
wire need_to_update_bresp;
wire bresp_push;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// assign AXI outputs
assign s_bid = bid_i;
assign s_bresp = s_bresp_acc_r;
assign s_bvalid = bvalid_i;
assign shandshake = s_bvalid & s_bready;
assign mhandshake = m_bvalid & m_bready;
always @(posedge clk) begin
if (reset | shandshake) begin
bvalid_i <= 1'b0;
end else if (~b_empty & ~shandshake_r & ~bresp_empty) begin
bvalid_i <= 1'b1;
end
end
always @(posedge clk) begin
shandshake_r <= shandshake;
mhandshake_r <= mhandshake;
end
axi_protocol_converter_v2_1_b2s_simple_fifo #(
.C_WIDTH (P_WIDTH),
.C_AWIDTH (P_AWIDTH),
.C_DEPTH (P_DEPTH)
)
bid_fifo_0
(
.clk ( clk ) ,
.rst ( reset ) ,
.wr_en ( b_push ) ,
.rd_en ( shandshake_r ) ,
.din ( {b_awid, b_awlen} ) ,
.dout ( {bid_i, b_awlen_i}) ,
.a_full ( ) ,
.full ( b_full ) ,
.a_empty ( ) ,
.empty ( b_empty )
);
assign m_bready = ~mhandshake_r & bresp_empty;
/////////////////////////////////////////////////////////////////////////////
// Update if more critical.
assign need_to_update_bresp = ( m_bresp > s_bresp_acc );
// Select accumultated or direct depending on setting.
always @( * ) begin
if ( need_to_update_bresp ) begin
s_bresp_i = m_bresp;
end else begin
s_bresp_i = s_bresp_acc;
end
end
/////////////////////////////////////////////////////////////////////////////
// Accumulate MI-side BRESP.
always @ (posedge clk) begin
if (reset | bresp_push ) begin
s_bresp_acc <= LP_RESP_OKAY;
end else if ( mhandshake ) begin
s_bresp_acc <= s_bresp_i;
end
end
assign bresp_push = ( mhandshake_r ) & (bresp_cnt == b_awlen_i) & ~b_empty;
always @ (posedge clk) begin
if (reset | bresp_push ) begin
bresp_cnt <= 8'h00;
end else if ( mhandshake_r ) begin
bresp_cnt <= bresp_cnt + 1'b1;
end
end
axi_protocol_converter_v2_1_b2s_simple_fifo #(
.C_WIDTH (P_RWIDTH),
.C_AWIDTH (P_RAWIDTH),
.C_DEPTH (P_RDEPTH)
)
bresp_fifo_0
(
.clk ( clk ) ,
.rst ( reset ) ,
.wr_en ( bresp_push ) ,
.rd_en ( shandshake_r ) ,
.din ( s_bresp_acc ) ,
.dout ( s_bresp_acc_r) ,
.a_full ( ) ,
.full ( bresp_full ) ,
.a_empty ( ) ,
.empty ( bresp_empty )
);
endmodule
`default_nettype wire
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Address AXI3 Slave Converter
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// a_axi3_conv
// axic_fifo
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_a_axi3_conv #
(
parameter C_FAMILY = "none",
parameter integer C_AXI_ID_WIDTH = 1,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_AUSER_WIDTH = 1,
parameter integer C_AXI_CHANNEL = 0,
// 0 = AXI AW Channel.
// 1 = AXI AR Channel.
parameter integer C_SUPPORT_SPLITTING = 1,
// Implement transaction splitting logic.
// Disabled whan all connected masters are AXI3 and have same or narrower data width.
parameter integer C_SUPPORT_BURSTS = 1,
// Disabled when all connected masters are AxiLite,
// allowing logic to be simplified.
parameter integer C_SINGLE_THREAD = 1
// 0 = Ignore ID when propagating transactions (assume all responses are in order).
// 1 = Enforce single-threading (one ID at a time) when any outstanding or
// requested transaction requires splitting.
// While no split is ongoing any new non-split transaction will pass immediately regardless
// off ID.
// A split transaction will stall if there are multiple ID (non-split) transactions
// ongoing, once it has been forwarded only transactions with the same ID is allowed
// (split or not) until all ongoing split transactios has been completed.
)
(
// System Signals
input wire ACLK,
input wire ARESET,
// Command Interface (W/R)
output wire cmd_valid,
output wire cmd_split,
output wire [C_AXI_ID_WIDTH-1:0] cmd_id,
output wire [4-1:0] cmd_length,
input wire cmd_ready,
// Command Interface (B)
output wire cmd_b_valid,
output wire cmd_b_split,
output wire [4-1:0] cmd_b_repeat,
input wire cmd_b_ready,
// Slave Interface Write Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_AID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AADDR,
input wire [8-1:0] S_AXI_ALEN,
input wire [3-1:0] S_AXI_ASIZE,
input wire [2-1:0] S_AXI_ABURST,
input wire [1-1:0] S_AXI_ALOCK,
input wire [4-1:0] S_AXI_ACACHE,
input wire [3-1:0] S_AXI_APROT,
input wire [4-1:0] S_AXI_AQOS,
input wire [C_AXI_AUSER_WIDTH-1:0] S_AXI_AUSER,
input wire S_AXI_AVALID,
output wire S_AXI_AREADY,
// Master Interface Write Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_AID,
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AADDR,
output wire [4-1:0] M_AXI_ALEN,
output wire [3-1:0] M_AXI_ASIZE,
output wire [2-1:0] M_AXI_ABURST,
output wire [2-1:0] M_AXI_ALOCK,
output wire [4-1:0] M_AXI_ACACHE,
output wire [3-1:0] M_AXI_APROT,
output wire [4-1:0] M_AXI_AQOS,
output wire [C_AXI_AUSER_WIDTH-1:0] M_AXI_AUSER,
output wire M_AXI_AVALID,
input wire M_AXI_AREADY
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for burst types.
localparam [2-1:0] C_FIX_BURST = 2'b00;
localparam [2-1:0] C_INCR_BURST = 2'b01;
localparam [2-1:0] C_WRAP_BURST = 2'b10;
// Depth for command FIFO.
localparam integer C_FIFO_DEPTH_LOG = 5;
// Constants used to generate size mask.
localparam [C_AXI_ADDR_WIDTH+8-1:0] C_SIZE_MASK = {{C_AXI_ADDR_WIDTH{1'b1}}, 8'b0000_0000};
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Access decoding related signals.
wire access_is_incr;
wire [4-1:0] num_transactions;
wire incr_need_to_split;
reg [C_AXI_ADDR_WIDTH-1:0] next_mi_addr;
reg split_ongoing;
reg [4-1:0] pushed_commands;
reg [16-1:0] addr_step;
reg [16-1:0] first_step;
wire [8-1:0] first_beats;
reg [C_AXI_ADDR_WIDTH-1:0] size_mask;
// Access decoding related signals for internal pipestage.
reg access_is_incr_q;
reg incr_need_to_split_q;
wire need_to_split_q;
reg [4-1:0] num_transactions_q;
reg [16-1:0] addr_step_q;
reg [16-1:0] first_step_q;
reg [C_AXI_ADDR_WIDTH-1:0] size_mask_q;
// Command buffer help signals.
reg [C_FIFO_DEPTH_LOG:0] cmd_depth;
reg cmd_empty;
reg [C_AXI_ID_WIDTH-1:0] queue_id;
wire id_match;
wire cmd_id_check;
wire s_ready;
wire cmd_full;
wire allow_this_cmd;
wire allow_new_cmd;
wire cmd_push;
reg cmd_push_block;
reg [C_FIFO_DEPTH_LOG:0] cmd_b_depth;
reg cmd_b_empty;
wire cmd_b_full;
wire cmd_b_push;
reg cmd_b_push_block;
wire pushed_new_cmd;
wire last_incr_split;
wire last_split;
wire first_split;
wire no_cmd;
wire allow_split_cmd;
wire almost_empty;
wire no_b_cmd;
wire allow_non_split_cmd;
wire almost_b_empty;
reg multiple_id_non_split;
reg split_in_progress;
// Internal Command Interface signals (W/R).
wire cmd_split_i;
wire [C_AXI_ID_WIDTH-1:0] cmd_id_i;
reg [4-1:0] cmd_length_i;
// Internal Command Interface signals (B).
wire cmd_b_split_i;
wire [4-1:0] cmd_b_repeat_i;
// Throttling help signals.
wire mi_stalling;
reg command_ongoing;
// Internal SI-side signals.
reg [C_AXI_ID_WIDTH-1:0] S_AXI_AID_Q;
reg [C_AXI_ADDR_WIDTH-1:0] S_AXI_AADDR_Q;
reg [8-1:0] S_AXI_ALEN_Q;
reg [3-1:0] S_AXI_ASIZE_Q;
reg [2-1:0] S_AXI_ABURST_Q;
reg [2-1:0] S_AXI_ALOCK_Q;
reg [4-1:0] S_AXI_ACACHE_Q;
reg [3-1:0] S_AXI_APROT_Q;
reg [4-1:0] S_AXI_AQOS_Q;
reg [C_AXI_AUSER_WIDTH-1:0] S_AXI_AUSER_Q;
reg S_AXI_AREADY_I;
// Internal MI-side signals.
wire [C_AXI_ID_WIDTH-1:0] M_AXI_AID_I;
reg [C_AXI_ADDR_WIDTH-1:0] M_AXI_AADDR_I;
reg [8-1:0] M_AXI_ALEN_I;
wire [3-1:0] M_AXI_ASIZE_I;
wire [2-1:0] M_AXI_ABURST_I;
reg [2-1:0] M_AXI_ALOCK_I;
wire [4-1:0] M_AXI_ACACHE_I;
wire [3-1:0] M_AXI_APROT_I;
wire [4-1:0] M_AXI_AQOS_I;
wire [C_AXI_AUSER_WIDTH-1:0] M_AXI_AUSER_I;
wire M_AXI_AVALID_I;
wire M_AXI_AREADY_I;
reg [1:0] areset_d; // Reset delay register
always @(posedge ACLK) begin
areset_d <= {areset_d[0], ARESET};
end
/////////////////////////////////////////////////////////////////////////////
// Capture SI-Side signals.
//
/////////////////////////////////////////////////////////////////////////////
// Register SI-Side signals.
always @ (posedge ACLK) begin
if ( ARESET ) begin
S_AXI_AID_Q <= {C_AXI_ID_WIDTH{1'b0}};
S_AXI_AADDR_Q <= {C_AXI_ADDR_WIDTH{1'b0}};
S_AXI_ALEN_Q <= 8'b0;
S_AXI_ASIZE_Q <= 3'b0;
S_AXI_ABURST_Q <= 2'b0;
S_AXI_ALOCK_Q <= 2'b0;
S_AXI_ACACHE_Q <= 4'b0;
S_AXI_APROT_Q <= 3'b0;
S_AXI_AQOS_Q <= 4'b0;
S_AXI_AUSER_Q <= {C_AXI_AUSER_WIDTH{1'b0}};
end else begin
if ( S_AXI_AREADY_I ) begin
S_AXI_AID_Q <= S_AXI_AID;
S_AXI_AADDR_Q <= S_AXI_AADDR;
S_AXI_ALEN_Q <= S_AXI_ALEN;
S_AXI_ASIZE_Q <= S_AXI_ASIZE;
S_AXI_ABURST_Q <= S_AXI_ABURST;
S_AXI_ALOCK_Q <= S_AXI_ALOCK;
S_AXI_ACACHE_Q <= S_AXI_ACACHE;
S_AXI_APROT_Q <= S_AXI_APROT;
S_AXI_AQOS_Q <= S_AXI_AQOS;
S_AXI_AUSER_Q <= S_AXI_AUSER;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Decode the Incoming Transaction.
//
// Extract transaction type and the number of splits that may be needed.
//
// Calculate the step size so that the address for each part of a split can
// can be calculated.
//
/////////////////////////////////////////////////////////////////////////////
// Transaction burst type.
assign access_is_incr = ( S_AXI_ABURST == C_INCR_BURST );
// Get number of transactions for split INCR.
assign num_transactions = S_AXI_ALEN[4 +: 4];
assign first_beats = {3'b0, S_AXI_ALEN[0 +: 4]} + 7'b01;
// Generate address increment of first split transaction.
always @ *
begin
case (S_AXI_ASIZE)
3'b000: first_step = first_beats << 0;
3'b001: first_step = first_beats << 1;
3'b010: first_step = first_beats << 2;
3'b011: first_step = first_beats << 3;
3'b100: first_step = first_beats << 4;
3'b101: first_step = first_beats << 5;
3'b110: first_step = first_beats << 6;
3'b111: first_step = first_beats << 7;
endcase
end
// Generate address increment for remaining split transactions.
always @ *
begin
case (S_AXI_ASIZE)
3'b000: addr_step = 16'h0010;
3'b001: addr_step = 16'h0020;
3'b010: addr_step = 16'h0040;
3'b011: addr_step = 16'h0080;
3'b100: addr_step = 16'h0100;
3'b101: addr_step = 16'h0200;
3'b110: addr_step = 16'h0400;
3'b111: addr_step = 16'h0800;
endcase
end
// Generate address mask bits to remove split transaction unalignment.
always @ *
begin
case (S_AXI_ASIZE)
3'b000: size_mask = C_SIZE_MASK[8 +: C_AXI_ADDR_WIDTH];
3'b001: size_mask = C_SIZE_MASK[7 +: C_AXI_ADDR_WIDTH];
3'b010: size_mask = C_SIZE_MASK[6 +: C_AXI_ADDR_WIDTH];
3'b011: size_mask = C_SIZE_MASK[5 +: C_AXI_ADDR_WIDTH];
3'b100: size_mask = C_SIZE_MASK[4 +: C_AXI_ADDR_WIDTH];
3'b101: size_mask = C_SIZE_MASK[3 +: C_AXI_ADDR_WIDTH];
3'b110: size_mask = C_SIZE_MASK[2 +: C_AXI_ADDR_WIDTH];
3'b111: size_mask = C_SIZE_MASK[1 +: C_AXI_ADDR_WIDTH];
endcase
end
/////////////////////////////////////////////////////////////////////////////
// Transfer SI-Side signals to internal Pipeline Stage.
//
/////////////////////////////////////////////////////////////////////////////
always @ (posedge ACLK) begin
if ( ARESET ) begin
access_is_incr_q <= 1'b0;
incr_need_to_split_q <= 1'b0;
num_transactions_q <= 4'b0;
addr_step_q <= 16'b0;
first_step_q <= 16'b0;
size_mask_q <= {C_AXI_ADDR_WIDTH{1'b0}};
end else begin
if ( S_AXI_AREADY_I ) begin
access_is_incr_q <= access_is_incr;
incr_need_to_split_q <= incr_need_to_split;
num_transactions_q <= num_transactions;
addr_step_q <= addr_step;
first_step_q <= first_step;
size_mask_q <= size_mask;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Generate Command Information.
//
// Detect if current transation needs to be split, and keep track of all
// the generated split transactions.
//
//
/////////////////////////////////////////////////////////////////////////////
// Detect when INCR must be split.
assign incr_need_to_split = access_is_incr & ( num_transactions != 0 ) &
( C_SUPPORT_SPLITTING == 1 ) &
( C_SUPPORT_BURSTS == 1 );
// Detect when a command has to be split.
assign need_to_split_q = incr_need_to_split_q;
// Handle progress of split transactions.
always @ (posedge ACLK) begin
if ( ARESET ) begin
split_ongoing <= 1'b0;
end else begin
if ( pushed_new_cmd ) begin
split_ongoing <= need_to_split_q & ~last_split;
end
end
end
// Keep track of number of transactions generated.
always @ (posedge ACLK) begin
if ( ARESET ) begin
pushed_commands <= 4'b0;
end else begin
if ( S_AXI_AREADY_I ) begin
pushed_commands <= 4'b0;
end else if ( pushed_new_cmd ) begin
pushed_commands <= pushed_commands + 4'b1;
end
end
end
// Detect last part of a command, split or not.
assign last_incr_split = access_is_incr_q & ( num_transactions_q == pushed_commands );
assign last_split = last_incr_split | ~access_is_incr_q |
( C_SUPPORT_SPLITTING == 0 ) |
( C_SUPPORT_BURSTS == 0 );
assign first_split = (pushed_commands == 4'b0);
// Calculate base for next address.
always @ (posedge ACLK) begin
if ( ARESET ) begin
next_mi_addr = {C_AXI_ADDR_WIDTH{1'b0}};
end else if ( pushed_new_cmd ) begin
next_mi_addr = M_AXI_AADDR_I + (first_split ? first_step_q : addr_step_q);
end
end
/////////////////////////////////////////////////////////////////////////////
// Translating Transaction.
//
// Set Split transaction information on all part except last for a transaction
// that needs splitting.
// The B Channel will only get one command for a Split transaction and in
// the Split bflag will be set in that case.
//
// The AWID is extracted and applied to all commands generated for the current
// incomming SI-Side transaction.
//
// The address is increased for each part of a Split transaction, the amount
// depends on the siSIZE for the transaction.
//
// The length has to be changed for Split transactions. All part except tha
// last one will have 0xF, the last one uses the 4 lsb bits from the SI-side
// transaction as length.
//
// Non-Split has untouched address and length information.
//
// Exclusive access are diasabled for a Split transaction because it is not
// possible to guarantee concistency between all the parts.
//
/////////////////////////////////////////////////////////////////////////////
// Assign Split signals.
assign cmd_split_i = need_to_split_q & ~last_split;
assign cmd_b_split_i = need_to_split_q & ~last_split;
// Copy AW ID to W.
assign cmd_id_i = S_AXI_AID_Q;
// Set B Responses to merge.
assign cmd_b_repeat_i = num_transactions_q;
// Select new size or remaining size.
always @ *
begin
if ( split_ongoing & access_is_incr_q ) begin
M_AXI_AADDR_I = next_mi_addr & size_mask_q;
end else begin
M_AXI_AADDR_I = S_AXI_AADDR_Q;
end
end
// Generate the base length for each transaction.
always @ *
begin
if ( first_split | ~need_to_split_q ) begin
M_AXI_ALEN_I = S_AXI_ALEN_Q[0 +: 4];
cmd_length_i = S_AXI_ALEN_Q[0 +: 4];
end else begin
M_AXI_ALEN_I = 4'hF;
cmd_length_i = 4'hF;
end
end
// Kill Exclusive for Split transactions.
always @ *
begin
if ( need_to_split_q ) begin
M_AXI_ALOCK_I = 2'b00;
end else begin
M_AXI_ALOCK_I = {1'b0, S_AXI_ALOCK_Q};
end
end
/////////////////////////////////////////////////////////////////////////////
// Forward the command to the MI-side interface.
//
// It is determined that this is an allowed command/access when there is
// room in the command queue (and it passes ID and Split checks as required).
//
/////////////////////////////////////////////////////////////////////////////
// Move SI-side transaction to internal pipe stage.
always @ (posedge ACLK) begin
if (ARESET) begin
command_ongoing <= 1'b0;
S_AXI_AREADY_I <= 1'b0;
end else begin
if (areset_d == 2'b10) begin
S_AXI_AREADY_I <= 1'b1;
end else begin
if ( S_AXI_AVALID & S_AXI_AREADY_I ) begin
command_ongoing <= 1'b1;
S_AXI_AREADY_I <= 1'b0;
end else if ( pushed_new_cmd & last_split ) begin
command_ongoing <= 1'b0;
S_AXI_AREADY_I <= 1'b1;
end
end
end
end
// Generate ready signal.
assign S_AXI_AREADY = S_AXI_AREADY_I;
// Only allowed to forward translated command when command queue is ok with it.
assign M_AXI_AVALID_I = allow_new_cmd & command_ongoing;
// Detect when MI-side is stalling.
assign mi_stalling = M_AXI_AVALID_I & ~M_AXI_AREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Simple transfer of paramters that doesn't need to be adjusted.
//
// ID - Transaction still recognized with the same ID.
// CACHE - No need to change the chache features. Even if the modyfiable
// bit is overridden (forcefully) there is no need to let downstream
// component beleive it is ok to modify it further.
// PROT - Security level of access is not changed when upsizing.
// QOS - Quality of Service is static 0.
// USER - User bits remains the same.
//
/////////////////////////////////////////////////////////////////////////////
assign M_AXI_AID_I = S_AXI_AID_Q;
assign M_AXI_ASIZE_I = S_AXI_ASIZE_Q;
assign M_AXI_ABURST_I = S_AXI_ABURST_Q;
assign M_AXI_ACACHE_I = S_AXI_ACACHE_Q;
assign M_AXI_APROT_I = S_AXI_APROT_Q;
assign M_AXI_AQOS_I = S_AXI_AQOS_Q;
assign M_AXI_AUSER_I = ( C_AXI_SUPPORTS_USER_SIGNALS ) ? S_AXI_AUSER_Q : {C_AXI_AUSER_WIDTH{1'b0}};
/////////////////////////////////////////////////////////////////////////////
// Control command queue to W/R channel.
//
// Commands can be pushed into the Cmd FIFO even if MI-side is stalling.
// A flag is set if MI-side is stalling when Command is pushed to the
// Cmd FIFO. This will prevent multiple push of the same Command as well as
// keeping the MI-side Valid signal if the Allow Cmd requirement has been
// updated to disable furter Commands (I.e. it is made sure that the SI-side
// Command has been forwarded to both Cmd FIFO and MI-side).
//
// It is allowed to continue pushing new commands as long as
// * There is room in the queue(s)
// * The ID is the same as previously queued. Since data is not reordered
// for the same ID it is always OK to let them proceed.
// Or, if no split transaction is ongoing any ID can be allowed.
//
/////////////////////////////////////////////////////////////////////////////
// Keep track of current ID in queue.
always @ (posedge ACLK) begin
if (ARESET) begin
queue_id <= {C_AXI_ID_WIDTH{1'b0}};
multiple_id_non_split <= 1'b0;
split_in_progress <= 1'b0;
end else begin
if ( cmd_push ) begin
// Store ID (it will be matching ID or a "new beginning").
queue_id <= S_AXI_AID_Q;
end
if ( no_cmd & no_b_cmd ) begin
multiple_id_non_split <= 1'b0;
end else if ( cmd_push & allow_non_split_cmd & ~id_match ) begin
multiple_id_non_split <= 1'b1;
end
if ( no_cmd & no_b_cmd ) begin
split_in_progress <= 1'b0;
end else if ( cmd_push & allow_split_cmd ) begin
split_in_progress <= 1'b1;
end
end
end
// Determine if the command FIFOs are empty.
assign no_cmd = almost_empty & cmd_ready | cmd_empty;
assign no_b_cmd = almost_b_empty & cmd_b_ready | cmd_b_empty;
// Check ID to make sure this command is allowed.
assign id_match = ( C_SINGLE_THREAD == 0 ) | ( queue_id == S_AXI_AID_Q);
assign cmd_id_check = (cmd_empty & cmd_b_empty) | ( id_match & (~cmd_empty | ~cmd_b_empty) );
// Command type affects possibility to push immediately or wait.
assign allow_split_cmd = need_to_split_q & cmd_id_check & ~multiple_id_non_split;
assign allow_non_split_cmd = ~need_to_split_q & (cmd_id_check | ~split_in_progress);
assign allow_this_cmd = allow_split_cmd | allow_non_split_cmd | ( C_SINGLE_THREAD == 0 );
// Check if it is allowed to push more commands.
assign allow_new_cmd = (~cmd_full & ~cmd_b_full & allow_this_cmd) |
cmd_push_block;
// Push new command when allowed and MI-side is able to receive the command.
assign cmd_push = M_AXI_AVALID_I & ~cmd_push_block;
assign cmd_b_push = M_AXI_AVALID_I & ~cmd_b_push_block & (C_AXI_CHANNEL == 0);
// Block furter push until command has been forwarded to MI-side.
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_push_block <= 1'b0;
end else begin
if ( pushed_new_cmd ) begin
cmd_push_block <= 1'b0;
end else if ( cmd_push & mi_stalling ) begin
cmd_push_block <= 1'b1;
end
end
end
// Block furter push until command has been forwarded to MI-side.
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_b_push_block <= 1'b0;
end else begin
if ( S_AXI_AREADY_I ) begin
cmd_b_push_block <= 1'b0;
end else if ( cmd_b_push ) begin
cmd_b_push_block <= 1'b1;
end
end
end
// Acknowledge command when we can push it into queue (and forward it).
assign pushed_new_cmd = M_AXI_AVALID_I & M_AXI_AREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Command Queue (W/R):
//
// Instantiate a FIFO as the queue and adjust the control signals.
//
// The features from Command FIFO can be reduced depending on configuration:
// Read Channel only need the split information.
// Write Channel always require ID information. When bursts are supported
// Split and Length information is also used.
//
/////////////////////////////////////////////////////////////////////////////
// Instantiated queue.
generate
if ( C_AXI_CHANNEL == 1 && C_SUPPORT_SPLITTING == 1 && C_SUPPORT_BURSTS == 1 ) begin : USE_R_CHANNEL
axi_data_fifo_v2_1_axic_fifo #
(
.C_FAMILY(C_FAMILY),
.C_FIFO_DEPTH_LOG(C_FIFO_DEPTH_LOG),
.C_FIFO_WIDTH(1),
.C_FIFO_TYPE("lut")
)
cmd_queue
(
.ACLK(ACLK),
.ARESET(ARESET),
.S_MESG({cmd_split_i}),
.S_VALID(cmd_push),
.S_READY(s_ready),
.M_MESG({cmd_split}),
.M_VALID(cmd_valid),
.M_READY(cmd_ready)
);
assign cmd_id = {C_AXI_ID_WIDTH{1'b0}};
assign cmd_length = 4'b0;
end else if (C_SUPPORT_BURSTS == 1) begin : USE_BURSTS
axi_data_fifo_v2_1_axic_fifo #
(
.C_FAMILY(C_FAMILY),
.C_FIFO_DEPTH_LOG(C_FIFO_DEPTH_LOG),
.C_FIFO_WIDTH(C_AXI_ID_WIDTH+4),
.C_FIFO_TYPE("lut")
)
cmd_queue
(
.ACLK(ACLK),
.ARESET(ARESET),
.S_MESG({cmd_id_i, cmd_length_i}),
.S_VALID(cmd_push),
.S_READY(s_ready),
.M_MESG({cmd_id, cmd_length}),
.M_VALID(cmd_valid),
.M_READY(cmd_ready)
);
assign cmd_split = 1'b0;
end else begin : NO_BURSTS
axi_data_fifo_v2_1_axic_fifo #
(
.C_FAMILY(C_FAMILY),
.C_FIFO_DEPTH_LOG(C_FIFO_DEPTH_LOG),
.C_FIFO_WIDTH(C_AXI_ID_WIDTH),
.C_FIFO_TYPE("lut")
)
cmd_queue
(
.ACLK(ACLK),
.ARESET(ARESET),
.S_MESG({cmd_id_i}),
.S_VALID(cmd_push),
.S_READY(s_ready),
.M_MESG({cmd_id}),
.M_VALID(cmd_valid),
.M_READY(cmd_ready)
);
assign cmd_split = 1'b0;
assign cmd_length = 4'b0;
end
endgenerate
// Queue is concidered full when not ready.
assign cmd_full = ~s_ready;
// Queue is empty when no data at output port.
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_empty <= 1'b1;
cmd_depth <= {C_FIFO_DEPTH_LOG+1{1'b0}};
end else begin
if ( cmd_push & ~cmd_ready ) begin
// Push only => Increase depth.
cmd_depth <= cmd_depth + 1'b1;
cmd_empty <= 1'b0;
end else if ( ~cmd_push & cmd_ready ) begin
// Pop only => Decrease depth.
cmd_depth <= cmd_depth - 1'b1;
cmd_empty <= almost_empty;
end
end
end
assign almost_empty = ( cmd_depth == 1 );
/////////////////////////////////////////////////////////////////////////////
// Command Queue (B):
//
// Add command queue for B channel only when it is AW channel and both burst
// and splitting is supported.
//
// When turned off the command appears always empty.
//
/////////////////////////////////////////////////////////////////////////////
// Instantiated queue.
generate
if ( C_AXI_CHANNEL == 0 && C_SUPPORT_SPLITTING == 1 && C_SUPPORT_BURSTS == 1 ) begin : USE_B_CHANNEL
wire cmd_b_valid_i;
wire s_b_ready;
axi_data_fifo_v2_1_axic_fifo #
(
.C_FAMILY(C_FAMILY),
.C_FIFO_DEPTH_LOG(C_FIFO_DEPTH_LOG),
.C_FIFO_WIDTH(1+4),
.C_FIFO_TYPE("lut")
)
cmd_b_queue
(
.ACLK(ACLK),
.ARESET(ARESET),
.S_MESG({cmd_b_split_i, cmd_b_repeat_i}),
.S_VALID(cmd_b_push),
.S_READY(s_b_ready),
.M_MESG({cmd_b_split, cmd_b_repeat}),
.M_VALID(cmd_b_valid_i),
.M_READY(cmd_b_ready)
);
// Queue is concidered full when not ready.
assign cmd_b_full = ~s_b_ready;
// Queue is empty when no data at output port.
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_b_empty <= 1'b1;
cmd_b_depth <= {C_FIFO_DEPTH_LOG+1{1'b0}};
end else begin
if ( cmd_b_push & ~cmd_b_ready ) begin
// Push only => Increase depth.
cmd_b_depth <= cmd_b_depth + 1'b1;
cmd_b_empty <= 1'b0;
end else if ( ~cmd_b_push & cmd_b_ready ) begin
// Pop only => Decrease depth.
cmd_b_depth <= cmd_b_depth - 1'b1;
cmd_b_empty <= ( cmd_b_depth == 1 );
end
end
end
assign almost_b_empty = ( cmd_b_depth == 1 );
// Assign external signal.
assign cmd_b_valid = cmd_b_valid_i;
end else begin : NO_B_CHANNEL
// Assign external command signals.
assign cmd_b_valid = 1'b0;
assign cmd_b_split = 1'b0;
assign cmd_b_repeat = 4'b0;
// Assign internal command FIFO signals.
assign cmd_b_full = 1'b0;
assign almost_b_empty = 1'b0;
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_b_empty <= 1'b1;
cmd_b_depth <= {C_FIFO_DEPTH_LOG+1{1'b0}};
end else begin
// Constant FF due to ModelSim behavior.
cmd_b_empty <= 1'b1;
cmd_b_depth <= {C_FIFO_DEPTH_LOG+1{1'b0}};
end
end
end
endgenerate
/////////////////////////////////////////////////////////////////////////////
// MI-side output handling
//
/////////////////////////////////////////////////////////////////////////////
assign M_AXI_AID = M_AXI_AID_I;
assign M_AXI_AADDR = M_AXI_AADDR_I;
assign M_AXI_ALEN = M_AXI_ALEN_I;
assign M_AXI_ASIZE = M_AXI_ASIZE_I;
assign M_AXI_ABURST = M_AXI_ABURST_I;
assign M_AXI_ALOCK = M_AXI_ALOCK_I;
assign M_AXI_ACACHE = M_AXI_ACACHE_I;
assign M_AXI_APROT = M_AXI_APROT_I;
assign M_AXI_AQOS = M_AXI_AQOS_I;
assign M_AXI_AUSER = M_AXI_AUSER_I;
assign M_AXI_AVALID = M_AXI_AVALID_I;
assign M_AXI_AREADY_I = M_AXI_AREADY;
endmodule
|
module mem_wait
(/*AUTOARG*/
// Outputs
mem_wait_arry,
// Inputs
clk, rst, lsu_valid, f_sgpr_lsu_instr_done, f_vgpr_lsu_wr_done,
lsu_wfid, f_sgpr_lsu_instr_done_wfid, f_vgpr_lsu_wr_done_wfid
);
input clk,rst;
input lsu_valid, f_sgpr_lsu_instr_done, f_vgpr_lsu_wr_done;
input [5:0] lsu_wfid, f_sgpr_lsu_instr_done_wfid, f_vgpr_lsu_wr_done_wfid;
output [`WF_PER_CU-1:0] mem_wait_arry;
wire [`WF_PER_CU-1:0] decoded_issue_value, decoded_sgpr_retire_value,
decoded_vgpr_retire_value,
mem_wait_reg_wr_en, mem_waiting_wf;
decoder_6b_40b_en issue_value_decoder
(
.addr_in(lsu_wfid),
.out(decoded_issue_value),
.en(lsu_valid)
);
decoder_6b_40b_en retire_sgpr_value_decoder
(
.addr_in(f_sgpr_lsu_instr_done_wfid),
.out(decoded_sgpr_retire_value),
.en(f_sgpr_lsu_instr_done)
);
decoder_6b_40b_en retire_vgpr_value_decoder
(
.addr_in(f_vgpr_lsu_wr_done_wfid),
.out(decoded_vgpr_retire_value),
.en(f_vgpr_lsu_wr_done)
);
dff_set_en_rst mem_wait[`WF_PER_CU-1:0]
(
.q(mem_waiting_wf),
.d(40'b0),
.en(mem_wait_reg_wr_en),
.clk(clk),
.set(decoded_issue_value),
.rst(rst)
);
assign mem_wait_reg_wr_en = decoded_vgpr_retire_value | decoded_sgpr_retire_value | decoded_issue_value;
assign mem_wait_arry = mem_waiting_wf;
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2016 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file upd77c25_datram.v when simulating
// the core, upd77c25_datram. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module upd77c25_datram(
clka,
wea,
addra,
dina,
douta,
clkb,
web,
addrb,
dinb,
doutb
);
input clka;
input [0 : 0] wea;
input [9 : 0] addra;
input [15 : 0] dina;
output [15 : 0] douta;
input clkb;
input [0 : 0] web;
input [10 : 0] addrb;
input [7 : 0] dinb;
output [7 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(10),
.C_ADDRB_WIDTH(11),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(1),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("spartan3"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(2),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(1024),
.C_READ_DEPTH_B(2048),
.C_READ_WIDTH_A(16),
.C_READ_WIDTH_B(8),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(1024),
.C_WRITE_DEPTH_B(2048),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(16),
.C_WRITE_WIDTH_B(8),
.C_XDEVICEFAMILY("spartan3")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.CLKB(clkb),
.WEB(web),
.ADDRB(addrb),
.DINB(dinb),
.DOUTB(doutb),
.RSTA(),
.ENA(),
.REGCEA(),
.RSTB(),
.ENB(),
.REGCEB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
reg reset;
reg enable;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] out; // From test of Test.v
// End of automatics
// Take CRC data and apply to testblock inputs
wire [31:0] in = crc[31:0];
Test test (/*AUTOINST*/
// Outputs
.out (out[31:0]),
// Inputs
.clk (clk),
.reset (reset),
.enable (enable),
.in (in[31:0]));
wire [63:0] result = {32'h0, out};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
reset <= (cyc < 5);
enable <= cyc[4] || (cyc < 2);
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
`define EXPECTED_SUM 64'h01e1553da1dcf3af
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
out,
// Inputs
clk, reset, enable, in
);
input clk;
input reset;
input enable;
input [31:0] in;
output [31:0] out;
// No gating
reg [31:0] d10;
always @(posedge clk) begin
d10 <= in;
end
reg displayit;
`ifdef VERILATOR // Harder test
initial displayit = $c1("0"); // Something that won't optimize away
`else
initial displayit = '0;
`endif
// Obvious gating + PLI
reg [31:0] d20;
always @(posedge clk) begin
if (enable) begin
d20 <= d10; // Obvious gating
if (displayit) begin
$display("hello!"); // Must glob with other PLI statements
end
end
end
// Reset means second-level gating
reg [31:0] d30, d31a, d31b, d32;
always @(posedge clk) begin
d32 <= d31b;
if (reset) begin
d30 <= 32'h0;
d31a <= 32'h0;
d31b <= 32'h0;
d32 <= 32'h0; // Overlaps above, just to make things interesting
end
else begin
// Mix two outputs
d30 <= d20;
if (enable) begin
d31a <= d30;
d31b <= d31a;
end
end
end
// Multiple ORs for gater
reg [31:0] d40a,d40b;
always @(posedge clk) begin
if (reset) begin
d40a <= 32'h0;
d40b <= 32'h0;
end
if (enable) begin
d40a <= d32;
d40b <= d40a;
end
end
// Non-optimizable
reg [31:0] d91, d92;
reg [31:0] inverted;
always @(posedge clk) begin
inverted = ~d40b;
if (reset) begin
d91 <= 32'h0;
end
else begin
if (enable) begin
d91 <= inverted;
end
else begin
d92 <= inverted ^ 32'h12341234; // Inverted gating condition
end
end
end
wire [31:0] out = d91 ^ d92;
endmodule
|
// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// File name: si_transactor.v
//
// Description:
// This module manages multi-threaded transactions for one SI-slot.
// The module interface consists of a 1-slave to 1-master address channel, plus a
// (M+1)-master (from M MI-slots plus error handler) to 1-slave response channel.
// The module maintains transaction thread control registers that count the
// number of outstanding transations for each thread and the target MI-slot.
// On the address channel, the module decodes addresses to select among MI-slots
// accessible to the SI-slot where it is instantiated.
// It then qualifies whether each received transaction
// should be propagated as a request to the address channel arbiter.
// Transactions are blocked while there is any outstanding transaction to a
// different slave (MI-slot) for the requested ID thread (for deadlock avoidance).
// On the response channel, the module mulitplexes transfers from each of the
// MI-slots whenever a transfer targets the ID of an active thread,
// arbitrating between MI-slots if multiple threads respond concurrently.
//
//--------------------------------------------------------------------------
//
// Structure:
// si_transactor
// addr_decoder
// comparator_static
// mux_enc
// axic_srl_fifo
// arbiter_resp
//
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_crossbar_v2_1_si_transactor #
(
parameter C_FAMILY = "none",
parameter integer C_SI = 0, // SI-slot number of current instance.
parameter integer C_DIR = 0, // Direction: 0 = Write; 1 = Read.
parameter integer C_NUM_ADDR_RANGES = 1,
parameter integer C_NUM_M = 2,
parameter integer C_NUM_M_LOG = 1,
parameter integer C_ACCEPTANCE = 1, // Acceptance limit of this SI-slot.
parameter integer C_ACCEPTANCE_LOG = 0, // Width of acceptance counter for this SI-slot.
parameter integer C_ID_WIDTH = 1,
parameter integer C_THREAD_ID_WIDTH = 0,
parameter integer C_ADDR_WIDTH = 32,
parameter integer C_AMESG_WIDTH = 1, // Used for AW or AR channel payload, depending on instantiation.
parameter integer C_RMESG_WIDTH = 1, // Used for B or R channel payload, depending on instantiation.
parameter [C_ID_WIDTH-1:0] C_BASE_ID = {C_ID_WIDTH{1'b0}},
parameter [C_ID_WIDTH-1:0] C_HIGH_ID = {C_ID_WIDTH{1'b0}},
parameter [C_NUM_M*C_NUM_ADDR_RANGES*64-1:0] C_BASE_ADDR = {C_NUM_M*C_NUM_ADDR_RANGES*64{1'b1}},
parameter [C_NUM_M*C_NUM_ADDR_RANGES*64-1:0] C_HIGH_ADDR = {C_NUM_M*C_NUM_ADDR_RANGES*64{1'b0}},
parameter integer C_SINGLE_THREAD = 0,
parameter [C_NUM_M-1:0] C_TARGET_QUAL = {C_NUM_M{1'b1}},
parameter [C_NUM_M*32-1:0] C_M_AXI_SECURE = {C_NUM_M{32'h00000000}},
parameter integer C_RANGE_CHECK = 0,
parameter integer C_ADDR_DECODE =0,
parameter [C_NUM_M*32-1:0] C_ERR_MODE = {C_NUM_M{32'h00000000}},
parameter integer C_DEBUG = 1
)
(
// Global Signals
input wire ACLK,
input wire ARESET,
// Slave Address Channel Interface Ports
input wire [C_ID_WIDTH-1:0] S_AID,
input wire [C_ADDR_WIDTH-1:0] S_AADDR,
input wire [8-1:0] S_ALEN,
input wire [3-1:0] S_ASIZE,
input wire [2-1:0] S_ABURST,
input wire [2-1:0] S_ALOCK,
input wire [3-1:0] S_APROT,
// input wire [4-1:0] S_AREGION,
input wire [C_AMESG_WIDTH-1:0] S_AMESG,
input wire S_AVALID,
output wire S_AREADY,
// Master Address Channel Interface Ports
output wire [C_ID_WIDTH-1:0] M_AID,
output wire [C_ADDR_WIDTH-1:0] M_AADDR,
output wire [8-1:0] M_ALEN,
output wire [3-1:0] M_ASIZE,
output wire [2-1:0] M_ALOCK,
output wire [3-1:0] M_APROT,
output wire [4-1:0] M_AREGION,
output wire [C_AMESG_WIDTH-1:0] M_AMESG,
output wire [(C_NUM_M+1)-1:0] M_ATARGET_HOT,
output wire [(C_NUM_M_LOG+1)-1:0] M_ATARGET_ENC,
output wire [7:0] M_AERROR,
output wire M_AVALID_QUAL,
output wire M_AVALID,
input wire M_AREADY,
// Slave Response Channel Interface Ports
output wire [C_ID_WIDTH-1:0] S_RID,
output wire [C_RMESG_WIDTH-1:0] S_RMESG,
output wire S_RLAST,
output wire S_RVALID,
input wire S_RREADY,
// Master Response Channel Interface Ports
input wire [(C_NUM_M+1)*C_ID_WIDTH-1:0] M_RID,
input wire [(C_NUM_M+1)*C_RMESG_WIDTH-1:0] M_RMESG,
input wire [(C_NUM_M+1)-1:0] M_RLAST,
input wire [(C_NUM_M+1)-1:0] M_RVALID,
output wire [(C_NUM_M+1)-1:0] M_RREADY,
input wire [(C_NUM_M+1)-1:0] M_RTARGET, // Does response ID from each MI-slot target this SI slot?
input wire [8-1:0] DEBUG_A_TRANS_SEQ
);
localparam integer P_WRITE = 0;
localparam integer P_READ = 1;
localparam integer P_RMUX_MESG_WIDTH = C_ID_WIDTH + C_RMESG_WIDTH + 1;
localparam [31:0] P_AXILITE_ERRMODE = 32'h00000001;
localparam integer P_NONSECURE_BIT = 1;
localparam integer P_NUM_M_LOG_M1 = C_NUM_M_LOG ? C_NUM_M_LOG : 1;
localparam [C_NUM_M-1:0] P_M_AXILITE = f_m_axilite(0); // Mask of AxiLite MI-slots
localparam [1:0] P_FIXED = 2'b00;
localparam integer P_NUM_M_DE_LOG = f_ceil_log2(C_NUM_M+1);
localparam integer P_THREAD_ID_WIDTH_M1 = (C_THREAD_ID_WIDTH > 0) ? C_THREAD_ID_WIDTH : 1;
localparam integer P_NUM_ID_VAL = 2**C_THREAD_ID_WIDTH;
localparam integer P_NUM_THREADS = (P_NUM_ID_VAL < C_ACCEPTANCE) ? P_NUM_ID_VAL : C_ACCEPTANCE;
localparam [C_NUM_M-1:0] P_M_SECURE_MASK = f_bit32to1_mi(C_M_AXI_SECURE); // Mask of secure MI-slots
// Ceiling of log2(x)
function integer f_ceil_log2
(
input integer x
);
integer acc;
begin
acc=0;
while ((2**acc) < x)
acc = acc + 1;
f_ceil_log2 = acc;
end
endfunction
// AxiLite protocol flag vector
function [C_NUM_M-1:0] f_m_axilite
(
input integer null_arg
);
integer mi;
begin
for (mi=0; mi<C_NUM_M; mi=mi+1) begin
f_m_axilite[mi] = (C_ERR_MODE[mi*32+:32] == P_AXILITE_ERRMODE);
end
end
endfunction
// Convert Bit32 vector of range [0,1] to Bit1 vector on MI
function [C_NUM_M-1:0] f_bit32to1_mi
(input [C_NUM_M*32-1:0] vec32);
integer mi;
begin
for (mi=0; mi<C_NUM_M; mi=mi+1) begin
f_bit32to1_mi[mi] = vec32[mi*32];
end
end
endfunction
wire [C_NUM_M-1:0] target_mi_hot;
wire [P_NUM_M_LOG_M1-1:0] target_mi_enc;
wire [(C_NUM_M+1)-1:0] m_atarget_hot_i;
wire [(P_NUM_M_DE_LOG)-1:0] m_atarget_enc_i;
wire match;
wire [3:0] target_region;
wire [3:0] m_aregion_i;
wire m_avalid_i;
wire s_aready_i;
wire any_error;
wire s_rvalid_i;
wire [C_ID_WIDTH-1:0] s_rid_i;
wire s_rlast_i;
wire [P_RMUX_MESG_WIDTH-1:0] si_rmux_mesg;
wire [(C_NUM_M+1)*P_RMUX_MESG_WIDTH-1:0] mi_rmux_mesg;
wire [(C_NUM_M+1)-1:0] m_rvalid_qual;
wire [(C_NUM_M+1)-1:0] m_rready_arb;
wire [(C_NUM_M+1)-1:0] m_rready_i;
wire target_secure;
wire target_axilite;
wire m_avalid_qual_i;
wire [7:0] m_aerror_i;
genvar gen_mi;
genvar gen_thread;
generate
if (C_ADDR_DECODE) begin : gen_addr_decoder
axi_crossbar_v2_1_addr_decoder #
(
.C_FAMILY (C_FAMILY),
.C_NUM_TARGETS (C_NUM_M),
.C_NUM_TARGETS_LOG (P_NUM_M_LOG_M1),
.C_NUM_RANGES (C_NUM_ADDR_RANGES),
.C_ADDR_WIDTH (C_ADDR_WIDTH),
.C_TARGET_ENC (1),
.C_TARGET_HOT (1),
.C_REGION_ENC (1),
.C_BASE_ADDR (C_BASE_ADDR),
.C_HIGH_ADDR (C_HIGH_ADDR),
.C_TARGET_QUAL (C_TARGET_QUAL),
.C_RESOLUTION (2)
)
addr_decoder_inst
(
.ADDR (S_AADDR),
.TARGET_HOT (target_mi_hot),
.TARGET_ENC (target_mi_enc),
.MATCH (match),
.REGION (target_region)
);
end else begin : gen_no_addr_decoder
assign target_mi_hot = 1;
assign target_mi_enc = 0;
assign match = 1'b1;
assign target_region = 4'b0000;
end
endgenerate
assign target_secure = |(target_mi_hot & P_M_SECURE_MASK);
assign target_axilite = |(target_mi_hot & P_M_AXILITE);
assign any_error = C_RANGE_CHECK && (m_aerror_i != 0); // DECERR if error-detection enabled and any error condition.
assign m_aerror_i[0] = ~match; // Invalid target address
assign m_aerror_i[1] = target_secure && S_APROT[P_NONSECURE_BIT]; // TrustZone violation
assign m_aerror_i[2] = target_axilite && ((S_ALEN != 0) ||
(S_ASIZE[1:0] == 2'b11) || (S_ASIZE[2] == 1'b1)); // AxiLite access violation
assign m_aerror_i[7:3] = 5'b00000; // Reserved
assign M_ATARGET_HOT = m_atarget_hot_i;
assign m_atarget_hot_i = (any_error ? {1'b1, {C_NUM_M{1'b0}}} : {1'b0, target_mi_hot});
assign m_atarget_enc_i = (any_error ? C_NUM_M : target_mi_enc);
assign M_AVALID = m_avalid_i;
assign m_avalid_i = S_AVALID;
assign M_AVALID_QUAL = m_avalid_qual_i;
assign S_AREADY = s_aready_i;
assign s_aready_i = M_AREADY;
assign M_AERROR = m_aerror_i;
assign M_ATARGET_ENC = m_atarget_enc_i;
assign m_aregion_i = any_error ? 4'b0000 : (C_ADDR_DECODE != 0) ? target_region : 4'b0000;
// assign m_aregion_i = any_error ? 4'b0000 : (C_ADDR_DECODE != 0) ? target_region : S_AREGION;
assign M_AREGION = m_aregion_i;
assign M_AID = S_AID;
assign M_AADDR = S_AADDR;
assign M_ALEN = S_ALEN;
assign M_ASIZE = S_ASIZE;
assign M_ALOCK = S_ALOCK;
assign M_APROT = S_APROT;
assign M_AMESG = S_AMESG;
assign S_RVALID = s_rvalid_i;
assign M_RREADY = m_rready_i;
assign s_rid_i = si_rmux_mesg[0+:C_ID_WIDTH];
assign S_RMESG = si_rmux_mesg[C_ID_WIDTH+:C_RMESG_WIDTH];
assign s_rlast_i = si_rmux_mesg[C_ID_WIDTH+C_RMESG_WIDTH+:1];
assign S_RID = s_rid_i;
assign S_RLAST = s_rlast_i;
assign m_rvalid_qual = M_RVALID & M_RTARGET;
assign m_rready_i = m_rready_arb & M_RTARGET;
generate
for (gen_mi=0; gen_mi<(C_NUM_M+1); gen_mi=gen_mi+1) begin : gen_rmesg_mi
// Note: Concatenation of mesg signals is from MSB to LSB; assignments that chop mesg signals appear in opposite order.
assign mi_rmux_mesg[gen_mi*P_RMUX_MESG_WIDTH+:P_RMUX_MESG_WIDTH] = {
M_RLAST[gen_mi],
M_RMESG[gen_mi*C_RMESG_WIDTH+:C_RMESG_WIDTH],
M_RID[gen_mi*C_ID_WIDTH+:C_ID_WIDTH]
};
end // gen_rmesg_mi
if (C_ACCEPTANCE == 1) begin : gen_single_issue
wire cmd_push;
wire cmd_pop;
reg [(C_NUM_M+1)-1:0] active_target_hot;
reg [P_NUM_M_DE_LOG-1:0] active_target_enc;
reg accept_cnt;
reg [8-1:0] debug_r_beat_cnt_i;
wire [8-1:0] debug_r_trans_seq_i;
assign cmd_push = M_AREADY;
assign cmd_pop = s_rvalid_i && S_RREADY && s_rlast_i; // Pop command queue if end of read burst
assign m_avalid_qual_i = ~accept_cnt | cmd_pop; // Ready for arbitration if no outstanding transaction or transaction being completed
always @(posedge ACLK) begin
if (ARESET) begin
accept_cnt <= 1'b0;
active_target_enc <= 0;
active_target_hot <= 0;
end else begin
if (cmd_push) begin
active_target_enc <= m_atarget_enc_i;
active_target_hot <= m_atarget_hot_i;
accept_cnt <= 1'b1;
end else if (cmd_pop) begin
accept_cnt <= 1'b0;
end
end
end // Clocked process
assign m_rready_arb = active_target_hot & {(C_NUM_M+1){S_RREADY}};
assign s_rvalid_i = |(active_target_hot & m_rvalid_qual);
generic_baseblocks_v2_1_mux_enc #
(
.C_FAMILY (C_FAMILY),
.C_RATIO (C_NUM_M+1),
.C_SEL_WIDTH (P_NUM_M_DE_LOG),
.C_DATA_WIDTH (P_RMUX_MESG_WIDTH)
) mux_resp_single_issue
(
.S (active_target_enc),
.A (mi_rmux_mesg),
.O (si_rmux_mesg),
.OE (1'b1)
);
if (C_DEBUG) begin : gen_debug_r_single_issue
// DEBUG READ BEAT COUNTER (only meaningful for R-channel)
always @(posedge ACLK) begin
if (ARESET) begin
debug_r_beat_cnt_i <= 0;
end else if (C_DIR == P_READ) begin
if (s_rvalid_i && S_RREADY) begin
if (s_rlast_i) begin
debug_r_beat_cnt_i <= 0;
end else begin
debug_r_beat_cnt_i <= debug_r_beat_cnt_i + 1;
end
end
end else begin
debug_r_beat_cnt_i <= 0;
end
end // Clocked process
// DEBUG R-CHANNEL TRANSACTION SEQUENCE FIFO
axi_data_fifo_v2_1_axic_srl_fifo #
(
.C_FAMILY (C_FAMILY),
.C_FIFO_WIDTH (8),
.C_FIFO_DEPTH_LOG (C_ACCEPTANCE_LOG+1),
.C_USE_FULL (0)
)
debug_r_seq_fifo_single_issue
(
.ACLK (ACLK),
.ARESET (ARESET),
.S_MESG (DEBUG_A_TRANS_SEQ),
.S_VALID (cmd_push),
.S_READY (),
.M_MESG (debug_r_trans_seq_i),
.M_VALID (),
.M_READY (cmd_pop)
);
end // gen_debug_r
end else if (C_SINGLE_THREAD || (P_NUM_ID_VAL==1)) begin : gen_single_thread
wire s_avalid_en;
wire cmd_push;
wire cmd_pop;
reg [C_ID_WIDTH-1:0] active_id;
reg [(C_NUM_M+1)-1:0] active_target_hot;
reg [P_NUM_M_DE_LOG-1:0] active_target_enc;
reg [4-1:0] active_region;
reg [(C_ACCEPTANCE_LOG+1)-1:0] accept_cnt;
reg [8-1:0] debug_r_beat_cnt_i;
wire [8-1:0] debug_r_trans_seq_i;
wire accept_limit ;
// Implement single-region-per-ID cyclic dependency avoidance method.
assign s_avalid_en = // This transaction is qualified to request arbitration if ...
(accept_cnt == 0) || // Either there are no outstanding transactions, or ...
(((P_NUM_ID_VAL==1) || (S_AID[P_THREAD_ID_WIDTH_M1-1:0] == active_id[P_THREAD_ID_WIDTH_M1-1:0])) && // the current transaction ID matches the previous, and ...
(active_target_enc == m_atarget_enc_i) && // all outstanding transactions are to the same target MI ...
(active_region == m_aregion_i)); // and to the same REGION.
assign cmd_push = M_AREADY;
assign cmd_pop = s_rvalid_i && S_RREADY && s_rlast_i; // Pop command queue if end of read burst
assign accept_limit = (accept_cnt == C_ACCEPTANCE) & ~cmd_pop; // Allow next push if a transaction is currently being completed
assign m_avalid_qual_i = s_avalid_en & ~accept_limit;
always @(posedge ACLK) begin
if (ARESET) begin
accept_cnt <= 0;
active_id <= 0;
active_target_enc <= 0;
active_target_hot <= 0;
active_region <= 0;
end else begin
if (cmd_push) begin
active_id <= S_AID[P_THREAD_ID_WIDTH_M1-1:0];
active_target_enc <= m_atarget_enc_i;
active_target_hot <= m_atarget_hot_i;
active_region <= m_aregion_i;
if (~cmd_pop) begin
accept_cnt <= accept_cnt + 1;
end
end else begin
if (cmd_pop & (accept_cnt != 0)) begin
accept_cnt <= accept_cnt - 1;
end
end
end
end // Clocked process
assign m_rready_arb = active_target_hot & {(C_NUM_M+1){S_RREADY}};
assign s_rvalid_i = |(active_target_hot & m_rvalid_qual);
generic_baseblocks_v2_1_mux_enc #
(
.C_FAMILY (C_FAMILY),
.C_RATIO (C_NUM_M+1),
.C_SEL_WIDTH (P_NUM_M_DE_LOG),
.C_DATA_WIDTH (P_RMUX_MESG_WIDTH)
) mux_resp_single_thread
(
.S (active_target_enc),
.A (mi_rmux_mesg),
.O (si_rmux_mesg),
.OE (1'b1)
);
if (C_DEBUG) begin : gen_debug_r_single_thread
// DEBUG READ BEAT COUNTER (only meaningful for R-channel)
always @(posedge ACLK) begin
if (ARESET) begin
debug_r_beat_cnt_i <= 0;
end else if (C_DIR == P_READ) begin
if (s_rvalid_i && S_RREADY) begin
if (s_rlast_i) begin
debug_r_beat_cnt_i <= 0;
end else begin
debug_r_beat_cnt_i <= debug_r_beat_cnt_i + 1;
end
end
end else begin
debug_r_beat_cnt_i <= 0;
end
end // Clocked process
// DEBUG R-CHANNEL TRANSACTION SEQUENCE FIFO
axi_data_fifo_v2_1_axic_srl_fifo #
(
.C_FAMILY (C_FAMILY),
.C_FIFO_WIDTH (8),
.C_FIFO_DEPTH_LOG (C_ACCEPTANCE_LOG+1),
.C_USE_FULL (0)
)
debug_r_seq_fifo_single_thread
(
.ACLK (ACLK),
.ARESET (ARESET),
.S_MESG (DEBUG_A_TRANS_SEQ),
.S_VALID (cmd_push),
.S_READY (),
.M_MESG (debug_r_trans_seq_i),
.M_VALID (),
.M_READY (cmd_pop)
);
end // gen_debug_r
end else begin : gen_multi_thread
wire [(P_NUM_M_DE_LOG)-1:0] resp_select;
reg [(C_ACCEPTANCE_LOG+1)-1:0] accept_cnt;
wire [P_NUM_THREADS-1:0] s_avalid_en;
wire [P_NUM_THREADS-1:0] thread_valid;
wire [P_NUM_THREADS-1:0] aid_match;
wire [P_NUM_THREADS-1:0] rid_match;
wire [P_NUM_THREADS-1:0] cmd_push;
wire [P_NUM_THREADS-1:0] cmd_pop;
wire [P_NUM_THREADS:0] accum_push;
reg [P_NUM_THREADS*C_ID_WIDTH-1:0] active_id;
reg [P_NUM_THREADS*8-1:0] active_target;
reg [P_NUM_THREADS*8-1:0] active_region;
reg [P_NUM_THREADS*8-1:0] active_cnt;
reg [P_NUM_THREADS*8-1:0] debug_r_beat_cnt_i;
wire [P_NUM_THREADS*8-1:0] debug_r_trans_seq_i;
wire any_aid_match;
wire any_rid_match;
wire accept_limit;
wire any_push;
wire any_pop;
axi_crossbar_v2_1_arbiter_resp # // Multi-thread response arbiter
(
.C_FAMILY (C_FAMILY),
.C_NUM_S (C_NUM_M+1),
.C_NUM_S_LOG (P_NUM_M_DE_LOG),
.C_GRANT_ENC (1),
.C_GRANT_HOT (0)
)
arbiter_resp_inst
(
.ACLK (ACLK),
.ARESET (ARESET),
.S_VALID (m_rvalid_qual),
.S_READY (m_rready_arb),
.M_GRANT_HOT (),
.M_GRANT_ENC (resp_select),
.M_VALID (s_rvalid_i),
.M_READY (S_RREADY)
);
generic_baseblocks_v2_1_mux_enc #
(
.C_FAMILY (C_FAMILY),
.C_RATIO (C_NUM_M+1),
.C_SEL_WIDTH (P_NUM_M_DE_LOG),
.C_DATA_WIDTH (P_RMUX_MESG_WIDTH)
) mux_resp_multi_thread
(
.S (resp_select),
.A (mi_rmux_mesg),
.O (si_rmux_mesg),
.OE (1'b1)
);
assign any_push = M_AREADY;
assign any_pop = s_rvalid_i & S_RREADY & s_rlast_i;
assign accept_limit = (accept_cnt == C_ACCEPTANCE) & ~any_pop; // Allow next push if a transaction is currently being completed
assign m_avalid_qual_i = (&s_avalid_en) & ~accept_limit; // The current request is qualified for arbitration when it is qualified against all outstanding transaction threads.
assign any_aid_match = |aid_match;
assign any_rid_match = |rid_match;
assign accum_push[0] = 1'b0;
always @(posedge ACLK) begin
if (ARESET) begin
accept_cnt <= 0;
end else begin
if (any_push & ~any_pop) begin
accept_cnt <= accept_cnt + 1;
end else if (any_pop & ~any_push & (accept_cnt != 0)) begin
accept_cnt <= accept_cnt - 1;
end
end
end // Clocked process
for (gen_thread=0; gen_thread<P_NUM_THREADS; gen_thread=gen_thread+1) begin : gen_thread_loop
assign thread_valid[gen_thread] = (active_cnt[gen_thread*8 +: C_ACCEPTANCE_LOG+1] != 0);
assign aid_match[gen_thread] = // The currect thread is active for the requested transaction if
thread_valid[gen_thread] && // this thread slot is not vacant, and
((S_AID[P_THREAD_ID_WIDTH_M1-1:0]) == active_id[gen_thread*C_ID_WIDTH+:P_THREAD_ID_WIDTH_M1]); // the requested ID matches the active ID for this thread.
assign s_avalid_en[gen_thread] = // The current request is qualified against this thread slot if
(~aid_match[gen_thread]) || // This thread slot is not active for the requested ID, or
((m_atarget_enc_i == active_target[gen_thread*8+:P_NUM_M_DE_LOG]) && // this outstanding transaction was to the same target and
(m_aregion_i == active_region[gen_thread*8+:4])); // to the same region.
// cmd_push points to the position of either the active thread for the requested ID or the lowest vacant thread slot.
assign accum_push[gen_thread+1] = accum_push[gen_thread] | ~thread_valid[gen_thread];
assign cmd_push[gen_thread] = any_push & (aid_match[gen_thread] | ((~any_aid_match) & ~thread_valid[gen_thread] & ~accum_push[gen_thread]));
// cmd_pop points to the position of the active thread that matches the current RID.
assign rid_match[gen_thread] = thread_valid[gen_thread] & ((s_rid_i[P_THREAD_ID_WIDTH_M1-1:0]) == active_id[gen_thread*C_ID_WIDTH+:P_THREAD_ID_WIDTH_M1]);
assign cmd_pop[gen_thread] = any_pop & rid_match[gen_thread];
always @(posedge ACLK) begin
if (ARESET) begin
active_id[gen_thread*C_ID_WIDTH+:C_ID_WIDTH] <= 0;
active_target[gen_thread*8+:8] <= 0;
active_region[gen_thread*8+:8] <= 0;
active_cnt[gen_thread*8+:8] <= 0;
end else begin
if (cmd_push[gen_thread]) begin
active_id[gen_thread*C_ID_WIDTH+:P_THREAD_ID_WIDTH_M1] <= S_AID[P_THREAD_ID_WIDTH_M1-1:0];
active_target[gen_thread*8+:P_NUM_M_DE_LOG] <= m_atarget_enc_i;
active_region[gen_thread*8+:4] <= m_aregion_i;
if (~cmd_pop[gen_thread]) begin
active_cnt[gen_thread*8+:C_ACCEPTANCE_LOG+1] <= active_cnt[gen_thread*8+:C_ACCEPTANCE_LOG+1] + 1;
end
end else if (cmd_pop[gen_thread]) begin
active_cnt[gen_thread*8+:C_ACCEPTANCE_LOG+1] <= active_cnt[gen_thread*8+:C_ACCEPTANCE_LOG+1] - 1;
end
end
end // Clocked process
if (C_DEBUG) begin : gen_debug_r_multi_thread
// DEBUG READ BEAT COUNTER (only meaningful for R-channel)
always @(posedge ACLK) begin
if (ARESET) begin
debug_r_beat_cnt_i[gen_thread*8+:8] <= 0;
end else if (C_DIR == P_READ) begin
if (s_rvalid_i & S_RREADY & rid_match[gen_thread]) begin
if (s_rlast_i) begin
debug_r_beat_cnt_i[gen_thread*8+:8] <= 0;
end else begin
debug_r_beat_cnt_i[gen_thread*8+:8] <= debug_r_beat_cnt_i[gen_thread*8+:8] + 1;
end
end
end else begin
debug_r_beat_cnt_i[gen_thread*8+:8] <= 0;
end
end // Clocked process
// DEBUG R-CHANNEL TRANSACTION SEQUENCE FIFO
axi_data_fifo_v2_1_axic_srl_fifo #
(
.C_FAMILY (C_FAMILY),
.C_FIFO_WIDTH (8),
.C_FIFO_DEPTH_LOG (C_ACCEPTANCE_LOG+1),
.C_USE_FULL (0)
)
debug_r_seq_fifo_multi_thread
(
.ACLK (ACLK),
.ARESET (ARESET),
.S_MESG (DEBUG_A_TRANS_SEQ),
.S_VALID (cmd_push[gen_thread]),
.S_READY (),
.M_MESG (debug_r_trans_seq_i[gen_thread*8+:8]),
.M_VALID (),
.M_READY (cmd_pop[gen_thread])
);
end // gen_debug_r_multi_thread
end // Next gen_thread_loop
end // thread control
endgenerate
endmodule
`default_nettype wire
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Tecnológico de Costa Rica
// Engineer: Juan José Rojas Salazar
//
// Create Date: 30.07.2016 10:22:05
// Design Name:
// Module Name: LINEALIZADOR_NORMALIZADOR
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
//////////////////////////////////////////////////////////////////////////////////
module LINEALIZADOR_NORMALIZADOR(
//INPUTS
input wire CLK,
input wire [31:0] I,
input wire [31:0] V,
input wire RST_LN_FF,
input wire Begin_FSM_I,
input wire Begin_FSM_V,
//OUTPUTS
output wire ACK_I,
output wire ACK_V,
output wire [31:0] RESULT_I,
output wire [31:0] RESULT_V
);
wire ACK_LN;
wire ACK_FF;
wire [31:0] LINEAL;
LINEALIZADOR #(.P(32)) LINEALIZADOR_FLOAT (
.CLK(CLK), //system clock
.T(I), //VALOR DEL ARGUMENTO DEL LOGARITMO QUE SE DESEA CALCULAR
.RST_LN(RST_LN_FF), //system reset
.Begin_FSM_LN(Begin_FSM_I), //INICIAL EL CALCULO
.ACK_LN(ACK_LN), //INDICA QUE EL CALCULO FUE REALIZADO
.O_FX(), //BANDERA DE OVER FLOW X
.O_FY(), //BANDERA DE OVER FLOW Y
.O_FZ(), //BANDERA DE OVER FLOW Z
.U_FX(), //BANDERA DE UNDER FLOW X
.U_FY(), //BANDERA DE UNDER FLOW Y
.U_FZ(), //BANDERA DE UNDER FLOW Z
.RESULT(LINEAL) //RESULTADO FINAL
);
I_NORM_FLOAT_TO_FIXED NORM_I_FLOAT_FIXED(
.CLK(CLK), //system clock
.F(LINEAL), //VALOR BINARIO EN COMA FLOTANTE
.RST_FF(RST_LN_FF), //system reset
.Begin_FSM_FF(ACK_LN), //INICIA LA CONVERSION
.ACK_FF(ACK_I), //INDICA QUE LA CONVERSION FUE REALIZADA
.RESULT(RESULT_I) //RESULTADO FINAL
);
/*V_NORM_FLOAT_TO_FIXED NORM_V_FLOAT_FIXED(
.CLK(CLK), //system clock
.F(V), //VALOR BINARIO EN COMA FLOTANTE
.RST_FF(RST_LN_FF), //system reset
.Begin_FSM_FF(Begin_FSM_V), //INICIA LA CONVERSION
.ACK_FF(ACK_V), //INDICA QUE LA CONVERSION FUE REALIZADA
.RESULT(RESULT_V) //RESULTADO FINAL
);*/
endmodule
|
//////////////////////////////////////////////////////////////////////////////////
// d_SC_deviders_s_lfs_XOR.v for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Jinwoo Jeong <[email protected]>
// Ilyong Jung <[email protected]>
// Yong Ho Song <[email protected]>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Jinwoo Jeong <[email protected]>
// Ilyong Jung <[email protected]>
//
// Project Name: Cosmos OpenSSD
// Design Name: BCH Page Decoder
// Module Name: d_SC_serial_lfs_XOR_***
// File Name: d_SC_deviders_s_lfs_XOR.v
//
// Version: v1.0.1-256B_T14
//
// Description: Serial linear feedback shift XOR for data area
//
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.0.1
// - minor modification for releasing
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`include "d_SC_parameters.vh"
`timescale 1ns / 1ps
module d_SC_serial_lfs_XOR_001(i_message, i_cur_remainder, o_nxt_remainder);
parameter [0:12] MIN_POLY = 13'b1001100100001;
input wire i_message;
input wire [`D_SC_GF_ORDER-1:0] i_cur_remainder;
output wire [`D_SC_GF_ORDER-1:0] o_nxt_remainder;
wire w_FB_term;
assign w_FB_term = i_cur_remainder[`D_SC_GF_ORDER-1];
assign o_nxt_remainder[0] = i_message ^ w_FB_term;
genvar i;
generate
for (i=1; i<`D_SC_GF_ORDER; i=i+1)
begin: linear_function
if (MIN_POLY[i] == 1)
begin
assign o_nxt_remainder[i] = i_cur_remainder[i-1] ^ w_FB_term;
end
else
begin
assign o_nxt_remainder[i] = i_cur_remainder[i-1];
end
end
endgenerate
endmodule
module d_SC_serial_lfs_XOR_003(i_message, i_cur_remainder, o_nxt_remainder);
parameter [0:12] MIN_POLY = 13'b1111010111001;
input wire i_message;
input wire [`D_SC_GF_ORDER-1:0] i_cur_remainder;
output wire [`D_SC_GF_ORDER-1:0] o_nxt_remainder;
wire w_FB_term;
assign w_FB_term = i_cur_remainder[`D_SC_GF_ORDER-1];
assign o_nxt_remainder[0] = i_message ^ w_FB_term;
genvar i;
generate
for (i=1; i<`D_SC_GF_ORDER; i=i+1)
begin: linear_function
if (MIN_POLY[i] == 1)
begin
assign o_nxt_remainder[i] = i_cur_remainder[i-1] ^ w_FB_term;
end
else
begin
assign o_nxt_remainder[i] = i_cur_remainder[i-1];
end
end
endgenerate
endmodule
module d_SC_serial_lfs_XOR_005(i_message, i_cur_remainder, o_nxt_remainder);
parameter [0:12] MIN_POLY = 13'b1000010100011;
input wire i_message;
input wire [`D_SC_GF_ORDER-1:0] i_cur_remainder;
output wire [`D_SC_GF_ORDER-1:0] o_nxt_remainder;
wire w_FB_term;
assign w_FB_term = i_cur_remainder[`D_SC_GF_ORDER-1];
assign o_nxt_remainder[0] = i_message ^ w_FB_term;
genvar i;
generate
for (i=1; i<`D_SC_GF_ORDER; i=i+1)
begin: linear_function
if (MIN_POLY[i] == 1)
begin
assign o_nxt_remainder[i] = i_cur_remainder[i-1] ^ w_FB_term;
end
else
begin
assign o_nxt_remainder[i] = i_cur_remainder[i-1];
end
end
endgenerate
endmodule
module d_SC_serial_lfs_XOR_007(i_message, i_cur_remainder, o_nxt_remainder);
parameter [0:12] MIN_POLY = 13'b1000010100101;
input wire i_message;
input wire [`D_SC_GF_ORDER-1:0] i_cur_remainder;
output wire [`D_SC_GF_ORDER-1:0] o_nxt_remainder;
wire w_FB_term;
assign w_FB_term = i_cur_remainder[`D_SC_GF_ORDER-1];
assign o_nxt_remainder[0] = i_message ^ w_FB_term;
genvar i;
generate
for (i=1; i<`D_SC_GF_ORDER; i=i+1)
begin: linear_function
if (MIN_POLY[i] == 1)
begin
assign o_nxt_remainder[i] = i_cur_remainder[i-1] ^ w_FB_term;
end
else
begin
assign o_nxt_remainder[i] = i_cur_remainder[i-1];
end
end
endgenerate
endmodule
module d_SC_serial_lfs_XOR_009(i_message, i_cur_remainder, o_nxt_remainder);
parameter [0:12] MIN_POLY = 13'b1101110001111;
input wire i_message;
input wire [`D_SC_GF_ORDER-1:0] i_cur_remainder;
output wire [`D_SC_GF_ORDER-1:0] o_nxt_remainder;
wire w_FB_term;
assign w_FB_term = i_cur_remainder[`D_SC_GF_ORDER-1];
assign o_nxt_remainder[0] = i_message ^ w_FB_term;
genvar i;
generate
for (i=1; i<`D_SC_GF_ORDER; i=i+1)
begin: linear_function
if (MIN_POLY[i] == 1)
begin
assign o_nxt_remainder[i] = i_cur_remainder[i-1] ^ w_FB_term;
end
else
begin
assign o_nxt_remainder[i] = i_cur_remainder[i-1];
end
end
endgenerate
endmodule
module d_SC_serial_lfs_XOR_011(i_message, i_cur_remainder, o_nxt_remainder);
parameter [0:12] MIN_POLY = 13'b1011100010101;
input wire i_message;
input wire [`D_SC_GF_ORDER-1:0] i_cur_remainder;
output wire [`D_SC_GF_ORDER-1:0] o_nxt_remainder;
wire w_FB_term;
assign w_FB_term = i_cur_remainder[`D_SC_GF_ORDER-1];
assign o_nxt_remainder[0] = i_message ^ w_FB_term;
genvar i;
generate
for (i=1; i<`D_SC_GF_ORDER; i=i+1)
begin: linear_function
if (MIN_POLY[i] == 1)
begin
assign o_nxt_remainder[i] = i_cur_remainder[i-1] ^ w_FB_term;
end
else
begin
assign o_nxt_remainder[i] = i_cur_remainder[i-1];
end
end
endgenerate
endmodule
module d_SC_serial_lfs_XOR_013(i_message, i_cur_remainder, o_nxt_remainder);
parameter [0:12] MIN_POLY = 13'b1010101001011;
input wire i_message;
input wire [`D_SC_GF_ORDER-1:0] i_cur_remainder;
output wire [`D_SC_GF_ORDER-1:0] o_nxt_remainder;
wire w_FB_term;
assign w_FB_term = i_cur_remainder[`D_SC_GF_ORDER-1];
assign o_nxt_remainder[0] = i_message ^ w_FB_term;
genvar i;
generate
for (i=1; i<`D_SC_GF_ORDER; i=i+1)
begin: linear_function
if (MIN_POLY[i] == 1)
begin
assign o_nxt_remainder[i] = i_cur_remainder[i-1] ^ w_FB_term;
end
else
begin
assign o_nxt_remainder[i] = i_cur_remainder[i-1];
end
end
endgenerate
endmodule
module d_SC_serial_lfs_XOR_015(i_message, i_cur_remainder, o_nxt_remainder);
parameter [0:12] MIN_POLY = 13'b1000011001111;
input wire i_message;
input wire [`D_SC_GF_ORDER-1:0] i_cur_remainder;
output wire [`D_SC_GF_ORDER-1:0] o_nxt_remainder;
wire w_FB_term;
assign w_FB_term = i_cur_remainder[`D_SC_GF_ORDER-1];
assign o_nxt_remainder[0] = i_message ^ w_FB_term;
genvar i;
generate
for (i=1; i<`D_SC_GF_ORDER; i=i+1)
begin: linear_function
if (MIN_POLY[i] == 1)
begin
assign o_nxt_remainder[i] = i_cur_remainder[i-1] ^ w_FB_term;
end
else
begin
assign o_nxt_remainder[i] = i_cur_remainder[i-1];
end
end
endgenerate
endmodule
module d_SC_serial_lfs_XOR_017(i_message, i_cur_remainder, o_nxt_remainder);
parameter [0:12] MIN_POLY = 13'b1011111000001;
input wire i_message;
input wire [`D_SC_GF_ORDER-1:0] i_cur_remainder;
output wire [`D_SC_GF_ORDER-1:0] o_nxt_remainder;
wire w_FB_term;
assign w_FB_term = i_cur_remainder[`D_SC_GF_ORDER-1];
assign o_nxt_remainder[0] = i_message ^ w_FB_term;
genvar i;
generate
for (i=1; i<`D_SC_GF_ORDER; i=i+1)
begin: linear_function
if (MIN_POLY[i] == 1)
begin
assign o_nxt_remainder[i] = i_cur_remainder[i-1] ^ w_FB_term;
end
else
begin
assign o_nxt_remainder[i] = i_cur_remainder[i-1];
end
end
endgenerate
endmodule
module d_SC_serial_lfs_XOR_019(i_message, i_cur_remainder, o_nxt_remainder);
parameter [0:12] MIN_POLY = 13'b1110010111011;
input wire i_message;
input wire [`D_SC_GF_ORDER-1:0] i_cur_remainder;
output wire [`D_SC_GF_ORDER-1:0] o_nxt_remainder;
wire w_FB_term;
assign w_FB_term = i_cur_remainder[`D_SC_GF_ORDER-1];
assign o_nxt_remainder[0] = i_message ^ w_FB_term;
genvar i;
generate
for (i=1; i<`D_SC_GF_ORDER; i=i+1)
begin: linear_function
if (MIN_POLY[i] == 1)
begin
assign o_nxt_remainder[i] = i_cur_remainder[i-1] ^ w_FB_term;
end
else
begin
assign o_nxt_remainder[i] = i_cur_remainder[i-1];
end
end
endgenerate
endmodule
module d_SC_serial_lfs_XOR_021(i_message, i_cur_remainder, o_nxt_remainder);
parameter [0:12] MIN_POLY = 13'b1000000110101;
input wire i_message;
input wire [`D_SC_GF_ORDER-1:0] i_cur_remainder;
output wire [`D_SC_GF_ORDER-1:0] o_nxt_remainder;
wire w_FB_term;
assign w_FB_term = i_cur_remainder[`D_SC_GF_ORDER-1];
assign o_nxt_remainder[0] = i_message ^ w_FB_term;
genvar i;
generate
for (i=1; i<`D_SC_GF_ORDER; i=i+1)
begin: linear_function
if (MIN_POLY[i] == 1)
begin
assign o_nxt_remainder[i] = i_cur_remainder[i-1] ^ w_FB_term;
end
else
begin
assign o_nxt_remainder[i] = i_cur_remainder[i-1];
end
end
endgenerate
endmodule
module d_SC_serial_lfs_XOR_023(i_message, i_cur_remainder, o_nxt_remainder);
parameter [0:12] MIN_POLY = 13'b1100111001001;
input wire i_message;
input wire [`D_SC_GF_ORDER-1:0] i_cur_remainder;
output wire [`D_SC_GF_ORDER-1:0] o_nxt_remainder;
wire w_FB_term;
assign w_FB_term = i_cur_remainder[`D_SC_GF_ORDER-1];
assign o_nxt_remainder[0] = i_message ^ w_FB_term;
genvar i;
generate
for (i=1; i<`D_SC_GF_ORDER; i=i+1)
begin: linear_function
if (MIN_POLY[i] == 1)
begin
assign o_nxt_remainder[i] = i_cur_remainder[i-1] ^ w_FB_term;
end
else
begin
assign o_nxt_remainder[i] = i_cur_remainder[i-1];
end
end
endgenerate
endmodule
module d_SC_serial_lfs_XOR_025(i_message, i_cur_remainder, o_nxt_remainder);
parameter [0:12] MIN_POLY = 13'b1100100101101;
input wire i_message;
input wire [`D_SC_GF_ORDER-1:0] i_cur_remainder;
output wire [`D_SC_GF_ORDER-1:0] o_nxt_remainder;
wire w_FB_term;
assign w_FB_term = i_cur_remainder[`D_SC_GF_ORDER-1];
assign o_nxt_remainder[0] = i_message ^ w_FB_term;
genvar i;
generate
for (i=1; i<`D_SC_GF_ORDER; i=i+1)
begin: linear_function
if (MIN_POLY[i] == 1)
begin
assign o_nxt_remainder[i] = i_cur_remainder[i-1] ^ w_FB_term;
end
else
begin
assign o_nxt_remainder[i] = i_cur_remainder[i-1];
end
end
endgenerate
endmodule
module d_SC_serial_lfs_XOR_027(i_message, i_cur_remainder, o_nxt_remainder);
parameter [0:12] MIN_POLY = 13'b1011101001111;
input wire i_message;
input wire [`D_SC_GF_ORDER-1:0] i_cur_remainder;
output wire [`D_SC_GF_ORDER-1:0] o_nxt_remainder;
wire w_FB_term;
assign w_FB_term = i_cur_remainder[`D_SC_GF_ORDER-1];
assign o_nxt_remainder[0] = i_message ^ w_FB_term;
genvar i;
generate
for (i=1; i<`D_SC_GF_ORDER; i=i+1)
begin: linear_function
if (MIN_POLY[i] == 1)
begin
assign o_nxt_remainder[i] = i_cur_remainder[i-1] ^ w_FB_term;
end
else
begin
assign o_nxt_remainder[i] = i_cur_remainder[i-1];
end
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A211O_1_V
`define SKY130_FD_SC_HDLL__A211O_1_V
/**
* a211o: 2-input AND into first input of 3-input OR.
*
* X = ((A1 & A2) | B1 | C1)
*
* Verilog wrapper for a211o with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__a211o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a211o_1 (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__a211o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a211o_1 (
X ,
A1,
A2,
B1,
C1
);
output X ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__a211o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A211O_1_V
|
/*
* .--------------. .----------------. .------------.
* | .------------. | .--------------. | .----------. |
* | | ____ ____ | | | ____ ____ | | | ______ | |
* | ||_ || _|| | ||_ \ / _|| | | .' ___ || |
* ___ _ __ ___ _ __ | | | |__| | | | | | \/ | | | |/ .' \_|| |
* / _ \| '_ \ / _ \ '_ \ | | | __ | | | | | |\ /| | | | || | | |
* (_) | |_) | __/ | | || | _| | | |_ | | | _| |_\/_| |_ | | |\ `.___.'\| |
* \___/| .__/ \___|_| |_|| ||____||____|| | ||_____||_____|| | | `._____.'| |
* | | | | | | | | | | | |
* |_| | '------------' | '--------------' | '----------' |
* '--------------' '----------------' '------------'
*
* openHMC - An Open Source Hybrid Memory Cube Controller
* (C) Copyright 2014 Computer Architecture Group - University of Heidelberg
* www.ziti.uni-heidelberg.de
* B6, 26
* 68159 Mannheim
* Germany
*
* Contact: [email protected]
* http://ra.ziti.uni-heidelberg.de/openhmc
*
* This source file is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This source file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this source file. If not, see <http://www.gnu.org/licenses/>.
*
*
*/
module deserializer #(
parameter LOG_DWIDTH=7,
parameter DWIDTH=64
)
(
input wire clk,
input wire res_n,
input wire fast_clk,
input wire bit_slip,
input wire data_in,
output wire [DWIDTH-1:0]data_out,
input wire lane_polarity
);
reg [DWIDTH-1:0] tmp_buffer;
reg [DWIDTH-1:0] buffer;
reg [DWIDTH-1:0] buffer2;
reg [DWIDTH-1:0] data_out_temp;
reg [LOG_DWIDTH-1:0]curr_bit = 'h0;
reg [5:0] bit_slip_cnt;
reg bit_slip_done = 1'b0;
reg d_in_dly;
assign data_out = lane_polarity ? data_out_temp^{DWIDTH{1'b1}} : data_out_temp;
// SEQUENTIAL PROCESS
always @ (posedge fast_clk) begin
if(!res_n) begin
curr_bit <= {LOG_DWIDTH{1'b0}};
bit_slip_done <= 1'b0;
end else begin
#1ps d_in_dly <= data_in;
if (!bit_slip || bit_slip_done) begin
if(curr_bit == DWIDTH-1) begin
curr_bit <= 0;
end else begin
curr_bit <= curr_bit + 1;
end
end
if (bit_slip && !bit_slip_done)
bit_slip_done <= 1'b1;
if (bit_slip_done && !bit_slip)
bit_slip_done <= 1'b0;
if (|curr_bit == 1'b0) begin
buffer <= tmp_buffer;
end
tmp_buffer[curr_bit] <= d_in_dly;
end
end
always @ (posedge clk) begin
if(!res_n) begin
bit_slip_cnt <= 6'h0;
end else begin
if(bit_slip)
bit_slip_cnt <= bit_slip_cnt + 1;
buffer2 <= buffer;
if(bit_slip_cnt < DWIDTH-1) begin
data_out_temp <= buffer2;
end else begin
data_out_temp <= buffer;
end
end
end
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized COMPARATOR with generic_baseblocks_v2_1_0_carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_0_comparator #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] B,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar bit_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 3;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = B;
end
// Instantiate one generic_baseblocks_v2_1_0_carry and per level.
for (bit_cnt = 0; bit_cnt < C_NUM_LUT ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[bit_cnt] = ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] );
// Instantiate each LUT level.
generic_baseblocks_v2_1_0_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[bit_cnt+1]),
.CIN (carry_local[bit_cnt]),
.S (sel[bit_cnt])
);
end // end for bit_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for eth_axis_tx
*/
module test_eth_axis_tx_64;
// Parameters
parameter DATA_WIDTH = 64;
parameter KEEP_ENABLE = (DATA_WIDTH>8);
parameter KEEP_WIDTH = (DATA_WIDTH/8);
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg s_eth_hdr_valid = 0;
reg [47:0] s_eth_dest_mac = 0;
reg [47:0] s_eth_src_mac = 0;
reg [15:0] s_eth_type = 0;
reg [DATA_WIDTH-1:0] s_eth_payload_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] s_eth_payload_axis_tkeep = 0;
reg s_eth_payload_axis_tvalid = 0;
reg s_eth_payload_axis_tlast = 0;
reg s_eth_payload_axis_tuser = 0;
reg m_axis_tready = 0;
// Outputs
wire s_eth_payload_axis_tready;
wire s_eth_hdr_ready;
wire [DATA_WIDTH-1:0] m_axis_tdata;
wire [KEEP_WIDTH-1:0] m_axis_tkeep;
wire m_axis_tvalid;
wire m_axis_tlast;
wire m_axis_tuser;
wire busy;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
s_eth_hdr_valid,
s_eth_dest_mac,
s_eth_src_mac,
s_eth_type,
s_eth_payload_axis_tdata,
s_eth_payload_axis_tkeep,
s_eth_payload_axis_tvalid,
s_eth_payload_axis_tlast,
s_eth_payload_axis_tuser,
m_axis_tready
);
$to_myhdl(
s_eth_hdr_ready,
s_eth_payload_axis_tready,
m_axis_tdata,
m_axis_tkeep,
m_axis_tvalid,
m_axis_tlast,
m_axis_tuser,
busy
);
// dump file
$dumpfile("test_eth_axis_tx_64.lxt");
$dumpvars(0, test_eth_axis_tx_64);
end
eth_axis_tx #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH)
)
UUT (
.clk(clk),
.rst(rst),
// Ethernet frame input
.s_eth_hdr_valid(s_eth_hdr_valid),
.s_eth_hdr_ready(s_eth_hdr_ready),
.s_eth_dest_mac(s_eth_dest_mac),
.s_eth_src_mac(s_eth_src_mac),
.s_eth_type(s_eth_type),
.s_eth_payload_axis_tdata(s_eth_payload_axis_tdata),
.s_eth_payload_axis_tkeep(s_eth_payload_axis_tkeep),
.s_eth_payload_axis_tvalid(s_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(s_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(s_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(s_eth_payload_axis_tuser),
// AXI output
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tuser(m_axis_tuser),
// Status signals
.busy(busy)
);
endmodule
|
module ds8dac1(clk, PWM_in, PWM_out);
input clk;
input [7:0] PWM_in;
output reg PWM_out;
reg [8:0] PWM_accumulator;
reg [7:0] PWM_add;
initial
begin
PWM_accumulator <= 0;
PWM_add <=0;
end
always @(posedge clk) begin
PWM_accumulator <= PWM_accumulator[7:0] + PWM_add;
PWM_add <= PWM_in;
end
always @(negedge clk) begin
PWM_out <= PWM_accumulator[8];
end
endmodule
/*
// Delta-Sigma DAC
module ds8dac1(clk, DACin, DACout);
output DACout; // This is the average output that feeds low pass filter
reg DACout; // for optimum performance, ensure that this ff is in IOB
input [7:0] DACin; // DAC input
input clk;
reg [9:0] DeltaAdder; // Output of Delta adder
reg [9:0] SigmaAdder; // Output of Sigma adder
reg [9:0] SigmaLatch; // Latches output of Sigma adder
reg [9:0] DeltaB; // B input of Delta adder
initial
begin
DeltaAdder = 10'd0;
SigmaAdder = 10'd0;
SigmaLatch = 10'd0;
DeltaB = 10'd0;
end
always @(SigmaLatch) DeltaB = {SigmaLatch[9], SigmaLatch[9]} << (8);
always @(DACin or DeltaB) DeltaAdder = DACin + DeltaB;
always @(DeltaAdder or SigmaLatch) SigmaAdder = DeltaAdder + SigmaLatch;
always @(posedge clk)
begin
SigmaLatch <= SigmaAdder;
DACout <= SigmaLatch[9];
end
endmodule*/ |
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
// IP Revision: 3
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_blk_mem_gen_0_0 (
clka,
rsta,
ena,
wea,
addra,
dina,
douta
);
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
input wire clka;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA RST" *)
input wire rsta;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *)
input wire ena;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *)
input wire [3 : 0] wea;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
input wire [31 : 0] addra;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *)
input wire [31 : 0] dina;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *)
output wire [31 : 0] douta;
blk_mem_gen_v8_2 #(
.C_FAMILY("zynq"),
.C_XDEVICEFAMILY("zynq"),
.C_ELABORATION_DIR("./"),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_AXI_SLAVE_TYPE(0),
.C_USE_BRAM_BLOCK(1),
.C_ENABLE_32BIT_ADDRESS(1),
.C_CTRL_ECC_ALGO("NONE"),
.C_HAS_AXI_ID(0),
.C_AXI_ID_WIDTH(4),
.C_MEM_TYPE(0),
.C_BYTE_SIZE(8),
.C_ALGORITHM(1),
.C_PRIM_TYPE(1),
.C_LOAD_INIT_FILE(0),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INIT_FILE("NONE"),
.C_USE_DEFAULT_DATA(0),
.C_DEFAULT_DATA("0"),
.C_HAS_RSTA(1),
.C_RST_PRIORITY_A("CE"),
.C_RSTRAM_A(0),
.C_INITA_VAL("0"),
.C_HAS_ENA(1),
.C_HAS_REGCEA(0),
.C_USE_BYTE_WEA(1),
.C_WEA_WIDTH(4),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_WIDTH_A(32),
.C_READ_WIDTH_A(32),
.C_WRITE_DEPTH_A(16384),
.C_READ_DEPTH_A(16384),
.C_ADDRA_WIDTH(32),
.C_HAS_RSTB(0),
.C_RST_PRIORITY_B("CE"),
.C_RSTRAM_B(0),
.C_INITB_VAL("0"),
.C_HAS_ENB(0),
.C_HAS_REGCEB(0),
.C_USE_BYTE_WEB(1),
.C_WEB_WIDTH(4),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_B(32),
.C_READ_WIDTH_B(32),
.C_WRITE_DEPTH_B(16384),
.C_READ_DEPTH_B(16384),
.C_ADDRB_WIDTH(32),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_MUX_PIPELINE_STAGES(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_USE_SOFTECC(0),
.C_USE_ECC(0),
.C_EN_ECC_PIPE(0),
.C_HAS_INJECTERR(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_COMMON_CLK(0),
.C_DISABLE_WARN_BHV_COLL(0),
.C_EN_SLEEP_PIN(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_COUNT_36K_BRAM("16"),
.C_COUNT_18K_BRAM("0"),
.C_EST_POWER_SUMMARY("Estimated Power for IP : 10.194 mW")
) inst (
.clka(clka),
.rsta(rsta),
.ena(ena),
.regcea(1'D0),
.wea(wea),
.addra(addra),
.dina(dina),
.douta(douta),
.clkb(1'D0),
.rstb(1'D0),
.enb(1'D0),
.regceb(1'D0),
.web(4'B0),
.addrb(32'B0),
.dinb(32'B0),
.doutb(),
.injectsbiterr(1'D0),
.injectdbiterr(1'D0),
.eccpipece(1'D0),
.sbiterr(),
.dbiterr(),
.rdaddrecc(),
.sleep(1'D0),
.s_aclk(1'H0),
.s_aresetn(1'D0),
.s_axi_awid(4'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wdata(32'B0),
.s_axi_wstrb(4'B0),
.s_axi_wlast(1'D0),
.s_axi_wvalid(1'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_bvalid(),
.s_axi_bready(1'D0),
.s_axi_arid(4'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arvalid(1'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_rvalid(),
.s_axi_rready(1'D0),
.s_axi_injectsbiterr(1'D0),
.s_axi_injectdbiterr(1'D0),
.s_axi_sbiterr(),
.s_axi_dbiterr(),
.s_axi_rdaddrecc()
);
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Original Author: Schuyler Eldridge
// Contact Point: Schuyler Eldridge ([email protected])
// div_pipelined.v
// Created: 4.3.2012
// Modified: 4.5.2012
//
// Testbench for div_pipelined.v
//
// Copyright (C) 2012 Schuyler Eldridge, Boston University
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module t_div_pipelined();
reg clk, start, reset_n;
reg [7:0] dividend, divisor;
wire data_valid, div_by_zero;
wire [7:0] quotient, quotient_correct;
parameter
BITS = 8;
div_pipelined
#(
.BITS(BITS)
)
div_pipelined
(
.clk(clk),
.reset_n(reset_n),
.dividend(dividend),
.divisor(divisor),
.quotient(quotient),
.div_by_zero(div_by_zero),
// .quotient_correct(quotient_correct),
.start(start),
.data_valid(data_valid)
);
initial begin
#10 reset_n = 0;
#50 reset_n = 1;
#1
clk = 0;
dividend = -1;
divisor = 127;
#1000 $finish;
end
// always
// #20 dividend = dividend + 1;
always begin
#10 divisor = divisor - 1; start = 1;
#10 start = 0;
end
always
#5 clk = ~clk;
endmodule
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: Apod.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.0 Build 132 02/25/2009 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module Apod (
address,
clock,
q);
input [10:0] address;
input clock;
output [63:0] q;
wire [63:0] sub_wire0;
wire [63:0] q = sub_wire0[63:0];
altsyncram altsyncram_component (
.clock0 (clock),
.address_a (address),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({64{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "Apod.mif",
altsyncram_component.intended_device_family = "Cyclone III",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=apod",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 2048,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.widthad_a = 11,
altsyncram_component.width_a = 64,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
// Retrieval info: PRIVATE: JTAG_ID STRING "apod"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "Apod.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "2048"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "11"
// Retrieval info: PRIVATE: WidthData NUMERIC "64"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "Apod.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=apod"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "64"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 11 0 INPUT NODEFVAL address[10..0]
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: q 0 0 64 0 OUTPUT NODEFVAL q[63..0]
// Retrieval info: CONNECT: @address_a 0 0 11 0 address 0 0 11 0
// Retrieval info: CONNECT: q 0 0 64 0 @q_a 0 0 64 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL Apod.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Apod.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Apod.cmp TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Apod.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Apod_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Apod_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Apod_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Apod_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
/******************************************************************************
-- (c) Copyright 2006 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
*****************************************************************************
*
* Filename: BLK_MEM_GEN_v8_2.v
*
* Description:
* This file is the Verilog behvarial model for the
* Block Memory Generator Core.
*
*****************************************************************************
* Author: Xilinx
*
* History: Jan 11, 2006 Initial revision
* Jun 11, 2007 Added independent register stages for
* Port A and Port B (IP1_Jm/v2.5)
* Aug 28, 2007 Added mux pipeline stages feature (IP2_Jm/v2.6)
* Mar 13, 2008 Behavioral model optimizations
* April 07, 2009 : Added support for Spartan-6 and Virtex-6
* features, including the following:
* (i) error injection, detection and/or correction
* (ii) reset priority
* (iii) special reset behavior
*
*****************************************************************************/
`timescale 1ps/1ps
module STATE_LOGIC_v8_2 (O, I0, I1, I2, I3, I4, I5);
parameter INIT = 64'h0000000000000000;
input I0, I1, I2, I3, I4, I5;
output O;
reg O;
reg tmp;
always @( I5 or I4 or I3 or I2 or I1 or I0 ) begin
tmp = I0 ^ I1 ^ I2 ^ I3 ^ I4 ^ I5;
if ( tmp == 0 || tmp == 1)
O = INIT[{I5, I4, I3, I2, I1, I0}];
end
endmodule
module beh_vlog_muxf7_v8_2 (O, I0, I1, S);
output O;
reg O;
input I0, I1, S;
always @(I0 or I1 or S)
if (S)
O = I1;
else
O = I0;
endmodule
module beh_vlog_ff_clr_v8_2 (Q, C, CLR, D);
parameter INIT = 0;
localparam FLOP_DELAY = 100;
output Q;
input C, CLR, D;
reg Q;
initial Q= 1'b0;
always @(posedge C )
if (CLR)
Q<= 1'b0;
else
Q<= #FLOP_DELAY D;
endmodule
module beh_vlog_ff_pre_v8_2 (Q, C, D, PRE);
parameter INIT = 0;
localparam FLOP_DELAY = 100;
output Q;
input C, D, PRE;
reg Q;
initial Q= 1'b0;
always @(posedge C )
if (PRE)
Q <= 1'b1;
else
Q <= #FLOP_DELAY D;
endmodule
module beh_vlog_ff_ce_clr_v8_2 (Q, C, CE, CLR, D);
parameter INIT = 0;
localparam FLOP_DELAY = 100;
output Q;
input C, CE, CLR, D;
reg Q;
initial Q= 1'b0;
always @(posedge C )
if (CLR)
Q <= 1'b0;
else if (CE)
Q <= #FLOP_DELAY D;
endmodule
module write_netlist_v8_2
#(
parameter C_AXI_TYPE = 0
)
(
S_ACLK, S_ARESETN, S_AXI_AWVALID, S_AXI_WVALID, S_AXI_BREADY,
w_last_c, bready_timeout_c, aw_ready_r, S_AXI_WREADY, S_AXI_BVALID,
S_AXI_WR_EN, addr_en_c, incr_addr_c, bvalid_c
);
input S_ACLK;
input S_ARESETN;
input S_AXI_AWVALID;
input S_AXI_WVALID;
input S_AXI_BREADY;
input w_last_c;
input bready_timeout_c;
output aw_ready_r;
output S_AXI_WREADY;
output S_AXI_BVALID;
output S_AXI_WR_EN;
output addr_en_c;
output incr_addr_c;
output bvalid_c;
//-------------------------------------------------------------------------
//AXI LITE
//-------------------------------------------------------------------------
generate if (C_AXI_TYPE == 0 ) begin : gbeh_axi_lite_sm
wire w_ready_r_7;
wire w_ready_c;
wire aw_ready_c;
wire NlwRenamedSignal_bvalid_c;
wire NlwRenamedSignal_incr_addr_c;
wire present_state_FSM_FFd3_13;
wire present_state_FSM_FFd2_14;
wire present_state_FSM_FFd1_15;
wire present_state_FSM_FFd4_16;
wire present_state_FSM_FFd4_In;
wire present_state_FSM_FFd3_In;
wire present_state_FSM_FFd2_In;
wire present_state_FSM_FFd1_In;
wire present_state_FSM_FFd4_In1_21;
wire [0:0] Mmux_aw_ready_c ;
begin
assign
S_AXI_WREADY = w_ready_r_7,
S_AXI_BVALID = NlwRenamedSignal_incr_addr_c,
S_AXI_WR_EN = NlwRenamedSignal_bvalid_c,
incr_addr_c = NlwRenamedSignal_incr_addr_c,
bvalid_c = NlwRenamedSignal_bvalid_c;
assign NlwRenamedSignal_incr_addr_c = 1'b0;
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
aw_ready_r_2 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( aw_ready_c),
.Q ( aw_ready_r)
);
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
w_ready_r (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( w_ready_c),
.Q ( w_ready_r_7)
);
beh_vlog_ff_pre_v8_2 #(
.INIT (1'b1))
present_state_FSM_FFd4 (
.C ( S_ACLK),
.D ( present_state_FSM_FFd4_In),
.PRE ( S_ARESETN),
.Q ( present_state_FSM_FFd4_16)
);
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
present_state_FSM_FFd3 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd3_In),
.Q ( present_state_FSM_FFd3_13)
);
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
present_state_FSM_FFd2 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd2_In),
.Q ( present_state_FSM_FFd2_14)
);
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
present_state_FSM_FFd1 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd1_In),
.Q ( present_state_FSM_FFd1_15)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000055554440))
present_state_FSM_FFd3_In1 (
.I0 ( S_AXI_WVALID),
.I1 ( S_AXI_AWVALID),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( present_state_FSM_FFd4_16),
.I4 ( present_state_FSM_FFd3_13),
.I5 (1'b0),
.O ( present_state_FSM_FFd3_In)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000088880800))
present_state_FSM_FFd2_In1 (
.I0 ( S_AXI_AWVALID),
.I1 ( S_AXI_WVALID),
.I2 ( bready_timeout_c),
.I3 ( present_state_FSM_FFd2_14),
.I4 ( present_state_FSM_FFd4_16),
.I5 (1'b0),
.O ( present_state_FSM_FFd2_In)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h00000000AAAA2000))
Mmux_addr_en_c_0_1 (
.I0 ( S_AXI_AWVALID),
.I1 ( bready_timeout_c),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( S_AXI_WVALID),
.I4 ( present_state_FSM_FFd4_16),
.I5 (1'b0),
.O ( addr_en_c)
);
STATE_LOGIC_v8_2 #(
.INIT (64'hF5F07570F5F05500))
Mmux_w_ready_c_0_1 (
.I0 ( S_AXI_WVALID),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd3_13),
.I4 ( present_state_FSM_FFd4_16),
.I5 ( present_state_FSM_FFd2_14),
.O ( w_ready_c)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h88808880FFFF8880))
present_state_FSM_FFd1_In1 (
.I0 ( S_AXI_WVALID),
.I1 ( bready_timeout_c),
.I2 ( present_state_FSM_FFd3_13),
.I3 ( present_state_FSM_FFd2_14),
.I4 ( present_state_FSM_FFd1_15),
.I5 ( S_AXI_BREADY),
.O ( present_state_FSM_FFd1_In)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h00000000000000A8))
Mmux_S_AXI_WR_EN_0_1 (
.I0 ( S_AXI_WVALID),
.I1 ( present_state_FSM_FFd2_14),
.I2 ( present_state_FSM_FFd3_13),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( NlwRenamedSignal_bvalid_c)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h2F0F27072F0F2200))
present_state_FSM_FFd4_In1 (
.I0 ( S_AXI_WVALID),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd3_13),
.I4 ( present_state_FSM_FFd4_16),
.I5 ( present_state_FSM_FFd2_14),
.O ( present_state_FSM_FFd4_In1_21)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h00000000000000F8))
present_state_FSM_FFd4_In2 (
.I0 ( present_state_FSM_FFd1_15),
.I1 ( S_AXI_BREADY),
.I2 ( present_state_FSM_FFd4_In1_21),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( present_state_FSM_FFd4_In)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h7535753575305500))
Mmux_aw_ready_c_0_1 (
.I0 ( S_AXI_AWVALID),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_WVALID),
.I3 ( present_state_FSM_FFd4_16),
.I4 ( present_state_FSM_FFd3_13),
.I5 ( present_state_FSM_FFd2_14),
.O ( Mmux_aw_ready_c[0])
);
STATE_LOGIC_v8_2 #(
.INIT (64'h00000000000000F8))
Mmux_aw_ready_c_0_2 (
.I0 ( present_state_FSM_FFd1_15),
.I1 ( S_AXI_BREADY),
.I2 ( Mmux_aw_ready_c[0]),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( aw_ready_c)
);
end
end
endgenerate
//---------------------------------------------------------------------
// AXI FULL
//---------------------------------------------------------------------
generate if (C_AXI_TYPE == 1 ) begin : gbeh_axi_full_sm
wire w_ready_r_8;
wire w_ready_c;
wire aw_ready_c;
wire NlwRenamedSig_OI_bvalid_c;
wire present_state_FSM_FFd1_16;
wire present_state_FSM_FFd4_17;
wire present_state_FSM_FFd3_18;
wire present_state_FSM_FFd2_19;
wire present_state_FSM_FFd4_In;
wire present_state_FSM_FFd3_In;
wire present_state_FSM_FFd2_In;
wire present_state_FSM_FFd1_In;
wire present_state_FSM_FFd2_In1_24;
wire present_state_FSM_FFd4_In1_25;
wire N2;
wire N4;
begin
assign
S_AXI_WREADY = w_ready_r_8,
bvalid_c = NlwRenamedSig_OI_bvalid_c,
S_AXI_BVALID = 1'b0;
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
aw_ready_r_2
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( aw_ready_c),
.Q ( aw_ready_r)
);
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
w_ready_r
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( w_ready_c),
.Q ( w_ready_r_8)
);
beh_vlog_ff_pre_v8_2 #(
.INIT (1'b1))
present_state_FSM_FFd4
(
.C ( S_ACLK),
.D ( present_state_FSM_FFd4_In),
.PRE ( S_ARESETN),
.Q ( present_state_FSM_FFd4_17)
);
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
present_state_FSM_FFd3
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd3_In),
.Q ( present_state_FSM_FFd3_18)
);
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
present_state_FSM_FFd2
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd2_In),
.Q ( present_state_FSM_FFd2_19)
);
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
present_state_FSM_FFd1
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd1_In),
.Q ( present_state_FSM_FFd1_16)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000000005540))
present_state_FSM_FFd3_In1
(
.I0 ( S_AXI_WVALID),
.I1 ( present_state_FSM_FFd4_17),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd3_18),
.I4 (1'b0),
.I5 (1'b0),
.O ( present_state_FSM_FFd3_In)
);
STATE_LOGIC_v8_2 #(
.INIT (64'hBF3FBB33AF0FAA00))
Mmux_aw_ready_c_0_2
(
.I0 ( S_AXI_BREADY),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd1_16),
.I4 ( present_state_FSM_FFd4_17),
.I5 ( NlwRenamedSig_OI_bvalid_c),
.O ( aw_ready_c)
);
STATE_LOGIC_v8_2 #(
.INIT (64'hAAAAAAAA20000000))
Mmux_addr_en_c_0_1
(
.I0 ( S_AXI_AWVALID),
.I1 ( bready_timeout_c),
.I2 ( present_state_FSM_FFd2_19),
.I3 ( S_AXI_WVALID),
.I4 ( w_last_c),
.I5 ( present_state_FSM_FFd4_17),
.O ( addr_en_c)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h00000000000000A8))
Mmux_S_AXI_WR_EN_0_1
(
.I0 ( S_AXI_WVALID),
.I1 ( present_state_FSM_FFd2_19),
.I2 ( present_state_FSM_FFd3_18),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( S_AXI_WR_EN)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000000002220))
Mmux_incr_addr_c_0_1
(
.I0 ( S_AXI_WVALID),
.I1 ( w_last_c),
.I2 ( present_state_FSM_FFd2_19),
.I3 ( present_state_FSM_FFd3_18),
.I4 (1'b0),
.I5 (1'b0),
.O ( incr_addr_c)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000000008880))
Mmux_aw_ready_c_0_11
(
.I0 ( S_AXI_WVALID),
.I1 ( w_last_c),
.I2 ( present_state_FSM_FFd2_19),
.I3 ( present_state_FSM_FFd3_18),
.I4 (1'b0),
.I5 (1'b0),
.O ( NlwRenamedSig_OI_bvalid_c)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h000000000000D5C0))
present_state_FSM_FFd2_In1
(
.I0 ( w_last_c),
.I1 ( S_AXI_AWVALID),
.I2 ( present_state_FSM_FFd4_17),
.I3 ( present_state_FSM_FFd3_18),
.I4 (1'b0),
.I5 (1'b0),
.O ( present_state_FSM_FFd2_In1_24)
);
STATE_LOGIC_v8_2 #(
.INIT (64'hFFFFAAAA08AAAAAA))
present_state_FSM_FFd2_In2
(
.I0 ( present_state_FSM_FFd2_19),
.I1 ( S_AXI_AWVALID),
.I2 ( bready_timeout_c),
.I3 ( w_last_c),
.I4 ( S_AXI_WVALID),
.I5 ( present_state_FSM_FFd2_In1_24),
.O ( present_state_FSM_FFd2_In)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h00C0004000C00000))
present_state_FSM_FFd4_In1
(
.I0 ( S_AXI_AWVALID),
.I1 ( w_last_c),
.I2 ( S_AXI_WVALID),
.I3 ( bready_timeout_c),
.I4 ( present_state_FSM_FFd3_18),
.I5 ( present_state_FSM_FFd2_19),
.O ( present_state_FSM_FFd4_In1_25)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h00000000FFFF88F8))
present_state_FSM_FFd4_In2
(
.I0 ( present_state_FSM_FFd1_16),
.I1 ( S_AXI_BREADY),
.I2 ( present_state_FSM_FFd4_17),
.I3 ( S_AXI_AWVALID),
.I4 ( present_state_FSM_FFd4_In1_25),
.I5 (1'b0),
.O ( present_state_FSM_FFd4_In)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000000000007))
Mmux_w_ready_c_0_SW0
(
.I0 ( w_last_c),
.I1 ( S_AXI_WVALID),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( N2)
);
STATE_LOGIC_v8_2 #(
.INIT (64'hFABAFABAFAAAF000))
Mmux_w_ready_c_0_Q
(
.I0 ( N2),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd4_17),
.I4 ( present_state_FSM_FFd3_18),
.I5 ( present_state_FSM_FFd2_19),
.O ( w_ready_c)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000000000008))
Mmux_aw_ready_c_0_11_SW0
(
.I0 ( bready_timeout_c),
.I1 ( S_AXI_WVALID),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( N4)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h88808880FFFF8880))
present_state_FSM_FFd1_In1
(
.I0 ( w_last_c),
.I1 ( N4),
.I2 ( present_state_FSM_FFd2_19),
.I3 ( present_state_FSM_FFd3_18),
.I4 ( present_state_FSM_FFd1_16),
.I5 ( S_AXI_BREADY),
.O ( present_state_FSM_FFd1_In)
);
end
end
endgenerate
endmodule
module read_netlist_v8_2 #(
parameter C_AXI_TYPE = 1,
parameter C_ADDRB_WIDTH = 12
) ( S_AXI_R_LAST_INT, S_ACLK, S_ARESETN, S_AXI_ARVALID,
S_AXI_RREADY,S_AXI_INCR_ADDR,S_AXI_ADDR_EN,
S_AXI_SINGLE_TRANS,S_AXI_MUX_SEL, S_AXI_R_LAST, S_AXI_ARREADY,
S_AXI_RLAST, S_AXI_RVALID, S_AXI_RD_EN, S_AXI_ARLEN);
input S_AXI_R_LAST_INT;
input S_ACLK;
input S_ARESETN;
input S_AXI_ARVALID;
input S_AXI_RREADY;
output S_AXI_INCR_ADDR;
output S_AXI_ADDR_EN;
output S_AXI_SINGLE_TRANS;
output S_AXI_MUX_SEL;
output S_AXI_R_LAST;
output S_AXI_ARREADY;
output S_AXI_RLAST;
output S_AXI_RVALID;
output S_AXI_RD_EN;
input [7:0] S_AXI_ARLEN;
wire present_state_FSM_FFd1_13 ;
wire present_state_FSM_FFd2_14 ;
wire gaxi_full_sm_outstanding_read_r_15 ;
wire gaxi_full_sm_ar_ready_r_16 ;
wire gaxi_full_sm_r_last_r_17 ;
wire NlwRenamedSig_OI_gaxi_full_sm_r_valid_r ;
wire gaxi_full_sm_r_valid_c ;
wire S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o ;
wire gaxi_full_sm_ar_ready_c ;
wire gaxi_full_sm_outstanding_read_c ;
wire NlwRenamedSig_OI_S_AXI_R_LAST ;
wire S_AXI_ARLEN_7_GND_8_o_equal_1_o ;
wire present_state_FSM_FFd2_In ;
wire present_state_FSM_FFd1_In ;
wire Mmux_S_AXI_R_LAST13 ;
wire N01 ;
wire N2 ;
wire Mmux_gaxi_full_sm_ar_ready_c11 ;
wire N4 ;
wire N8 ;
wire N9 ;
wire N10 ;
wire N11 ;
wire N12 ;
wire N13 ;
assign
S_AXI_R_LAST = NlwRenamedSig_OI_S_AXI_R_LAST,
S_AXI_ARREADY = gaxi_full_sm_ar_ready_r_16,
S_AXI_RLAST = gaxi_full_sm_r_last_r_17,
S_AXI_RVALID = NlwRenamedSig_OI_gaxi_full_sm_r_valid_r;
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
gaxi_full_sm_outstanding_read_r (
.C (S_ACLK),
.CLR(S_ARESETN),
.D(gaxi_full_sm_outstanding_read_c),
.Q(gaxi_full_sm_outstanding_read_r_15)
);
beh_vlog_ff_ce_clr_v8_2 #(
.INIT (1'b0))
gaxi_full_sm_r_valid_r (
.C (S_ACLK),
.CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
.CLR (S_ARESETN),
.D (gaxi_full_sm_r_valid_c),
.Q (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r)
);
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
gaxi_full_sm_ar_ready_r (
.C (S_ACLK),
.CLR (S_ARESETN),
.D (gaxi_full_sm_ar_ready_c),
.Q (gaxi_full_sm_ar_ready_r_16)
);
beh_vlog_ff_ce_clr_v8_2 #(
.INIT(1'b0))
gaxi_full_sm_r_last_r (
.C (S_ACLK),
.CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
.CLR (S_ARESETN),
.D (NlwRenamedSig_OI_S_AXI_R_LAST),
.Q (gaxi_full_sm_r_last_r_17)
);
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
present_state_FSM_FFd2 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd2_In),
.Q ( present_state_FSM_FFd2_14)
);
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
present_state_FSM_FFd1 (
.C (S_ACLK),
.CLR (S_ARESETN),
.D (present_state_FSM_FFd1_In),
.Q (present_state_FSM_FFd1_13)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h000000000000000B))
S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o1 (
.I0 ( S_AXI_RREADY),
.I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000000000008))
Mmux_S_AXI_SINGLE_TRANS11 (
.I0 (S_AXI_ARVALID),
.I1 (S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O (S_AXI_SINGLE_TRANS)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000000000004))
Mmux_S_AXI_ADDR_EN11 (
.I0 (present_state_FSM_FFd1_13),
.I1 (S_AXI_ARVALID),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O (S_AXI_ADDR_EN)
);
STATE_LOGIC_v8_2 #(
.INIT (64'hECEE2022EEEE2022))
present_state_FSM_FFd2_In1 (
.I0 ( S_AXI_ARVALID),
.I1 ( present_state_FSM_FFd1_13),
.I2 ( S_AXI_RREADY),
.I3 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I4 ( present_state_FSM_FFd2_14),
.I5 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.O ( present_state_FSM_FFd2_In)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000044440444))
Mmux_S_AXI_R_LAST131 (
.I0 ( present_state_FSM_FFd1_13),
.I1 ( S_AXI_ARVALID),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I4 ( S_AXI_RREADY),
.I5 (1'b0),
.O ( Mmux_S_AXI_R_LAST13)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h4000FFFF40004000))
Mmux_S_AXI_INCR_ADDR11 (
.I0 ( S_AXI_R_LAST_INT),
.I1 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( present_state_FSM_FFd1_13),
.I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I5 ( Mmux_S_AXI_R_LAST13),
.O ( S_AXI_INCR_ADDR)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h00000000000000FE))
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_SW0 (
.I0 ( S_AXI_ARLEN[2]),
.I1 ( S_AXI_ARLEN[1]),
.I2 ( S_AXI_ARLEN[0]),
.I3 ( 1'b0),
.I4 ( 1'b0),
.I5 ( 1'b0),
.O ( N01)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000000000001))
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_Q (
.I0 ( S_AXI_ARLEN[7]),
.I1 ( S_AXI_ARLEN[6]),
.I2 ( S_AXI_ARLEN[5]),
.I3 ( S_AXI_ARLEN[4]),
.I4 ( S_AXI_ARLEN[3]),
.I5 ( N01),
.O ( S_AXI_ARLEN_7_GND_8_o_equal_1_o)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000000000007))
Mmux_gaxi_full_sm_outstanding_read_c1_SW0 (
.I0 ( S_AXI_ARVALID),
.I1 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I2 ( 1'b0),
.I3 ( 1'b0),
.I4 ( 1'b0),
.I5 ( 1'b0),
.O ( N2)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0020000002200200))
Mmux_gaxi_full_sm_outstanding_read_c1 (
.I0 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I1 ( S_AXI_RREADY),
.I2 ( present_state_FSM_FFd1_13),
.I3 ( present_state_FSM_FFd2_14),
.I4 ( gaxi_full_sm_outstanding_read_r_15),
.I5 ( N2),
.O ( gaxi_full_sm_outstanding_read_c)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000000004555))
Mmux_gaxi_full_sm_ar_ready_c12 (
.I0 ( S_AXI_ARVALID),
.I1 ( S_AXI_RREADY),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I4 ( 1'b0),
.I5 ( 1'b0),
.O ( Mmux_gaxi_full_sm_ar_ready_c11)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h00000000000000EF))
Mmux_S_AXI_R_LAST11_SW0 (
.I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I1 ( S_AXI_RREADY),
.I2 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I3 ( 1'b0),
.I4 ( 1'b0),
.I5 ( 1'b0),
.O ( N4)
);
STATE_LOGIC_v8_2 #(
.INIT (64'hFCAAFC0A00AA000A))
Mmux_S_AXI_R_LAST11 (
.I0 ( S_AXI_ARVALID),
.I1 ( gaxi_full_sm_outstanding_read_r_15),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( present_state_FSM_FFd1_13),
.I4 ( N4),
.I5 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
.O ( gaxi_full_sm_r_valid_c)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h00000000AAAAAA08))
S_AXI_MUX_SEL1 (
.I0 (present_state_FSM_FFd1_13),
.I1 (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I2 (S_AXI_RREADY),
.I3 (present_state_FSM_FFd2_14),
.I4 (gaxi_full_sm_outstanding_read_r_15),
.I5 (1'b0),
.O (S_AXI_MUX_SEL)
);
STATE_LOGIC_v8_2 #(
.INIT (64'hF3F3F755A2A2A200))
Mmux_S_AXI_RD_EN11 (
.I0 ( present_state_FSM_FFd1_13),
.I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I2 ( S_AXI_RREADY),
.I3 ( gaxi_full_sm_outstanding_read_r_15),
.I4 ( present_state_FSM_FFd2_14),
.I5 ( S_AXI_ARVALID),
.O ( S_AXI_RD_EN)
);
beh_vlog_muxf7_v8_2 present_state_FSM_FFd1_In3 (
.I0 ( N8),
.I1 ( N9),
.S ( present_state_FSM_FFd1_13),
.O ( present_state_FSM_FFd1_In)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h000000005410F4F0))
present_state_FSM_FFd1_In3_F (
.I0 ( S_AXI_RREADY),
.I1 ( present_state_FSM_FFd2_14),
.I2 ( S_AXI_ARVALID),
.I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I5 ( 1'b0),
.O ( N8)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000072FF7272))
present_state_FSM_FFd1_In3_G (
.I0 ( present_state_FSM_FFd2_14),
.I1 ( S_AXI_R_LAST_INT),
.I2 ( gaxi_full_sm_outstanding_read_r_15),
.I3 ( S_AXI_RREADY),
.I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I5 ( 1'b0),
.O ( N9)
);
beh_vlog_muxf7_v8_2 Mmux_gaxi_full_sm_ar_ready_c14 (
.I0 ( N10),
.I1 ( N11),
.S ( present_state_FSM_FFd1_13),
.O ( gaxi_full_sm_ar_ready_c)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h00000000FFFF88A8))
Mmux_gaxi_full_sm_ar_ready_c14_F (
.I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I1 ( S_AXI_RREADY),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I4 ( Mmux_gaxi_full_sm_ar_ready_c11),
.I5 ( 1'b0),
.O ( N10)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h000000008D008D8D))
Mmux_gaxi_full_sm_ar_ready_c14_G (
.I0 ( present_state_FSM_FFd2_14),
.I1 ( S_AXI_R_LAST_INT),
.I2 ( gaxi_full_sm_outstanding_read_r_15),
.I3 ( S_AXI_RREADY),
.I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I5 ( 1'b0),
.O ( N11)
);
beh_vlog_muxf7_v8_2 Mmux_S_AXI_R_LAST1 (
.I0 ( N12),
.I1 ( N13),
.S ( present_state_FSM_FFd1_13),
.O ( NlwRenamedSig_OI_S_AXI_R_LAST)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000088088888))
Mmux_S_AXI_R_LAST1_F (
.I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I1 ( S_AXI_ARVALID),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( S_AXI_RREADY),
.I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I5 ( 1'b0),
.O ( N12)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h00000000E400E4E4))
Mmux_S_AXI_R_LAST1_G (
.I0 ( present_state_FSM_FFd2_14),
.I1 ( gaxi_full_sm_outstanding_read_r_15),
.I2 ( S_AXI_R_LAST_INT),
.I3 ( S_AXI_RREADY),
.I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I5 ( 1'b0),
.O ( N13)
);
endmodule
module blk_mem_axi_write_wrapper_beh_v8_2
# (
// AXI Interface related parameters start here
parameter C_INTERFACE_TYPE = 0, // 0: Native Interface; 1: AXI Interface
parameter C_AXI_TYPE = 0, // 0: AXI Lite; 1: AXI Full;
parameter C_AXI_SLAVE_TYPE = 0, // 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;
parameter C_MEMORY_TYPE = 0, // 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;
parameter C_WRITE_DEPTH_A = 0,
parameter C_AXI_AWADDR_WIDTH = 32,
parameter C_ADDRA_WIDTH = 12,
parameter C_AXI_WDATA_WIDTH = 32,
parameter C_HAS_AXI_ID = 0,
parameter C_AXI_ID_WIDTH = 4,
// AXI OUTSTANDING WRITES
parameter C_AXI_OS_WR = 2
)
(
// AXI Global Signals
input S_ACLK,
input S_ARESETN,
// AXI Full/Lite Slave Write Channel (write side)
input [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
input [C_AXI_AWADDR_WIDTH-1:0] S_AXI_AWADDR,
input [8-1:0] S_AXI_AWLEN,
input [2:0] S_AXI_AWSIZE,
input [1:0] S_AXI_AWBURST,
input S_AXI_AWVALID,
output S_AXI_AWREADY,
input S_AXI_WVALID,
output S_AXI_WREADY,
output reg [C_AXI_ID_WIDTH-1:0] S_AXI_BID = 0,
output S_AXI_BVALID,
input S_AXI_BREADY,
// Signals for BMG interface
output [C_ADDRA_WIDTH-1:0] S_AXI_AWADDR_OUT,
output S_AXI_WR_EN
);
localparam FLOP_DELAY = 100; // 100 ps
localparam C_RANGE = ((C_AXI_WDATA_WIDTH == 8)?0:
((C_AXI_WDATA_WIDTH==16)?1:
((C_AXI_WDATA_WIDTH==32)?2:
((C_AXI_WDATA_WIDTH==64)?3:
((C_AXI_WDATA_WIDTH==128)?4:
((C_AXI_WDATA_WIDTH==256)?5:0))))));
wire bvalid_c ;
reg bready_timeout_c = 0;
wire [1:0] bvalid_rd_cnt_c;
reg bvalid_r = 0;
reg [2:0] bvalid_count_r = 0;
reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?
C_AXI_AWADDR_WIDTH:C_ADDRA_WIDTH)-1:0] awaddr_reg = 0;
reg [1:0] bvalid_wr_cnt_r = 0;
reg [1:0] bvalid_rd_cnt_r = 0;
wire w_last_c ;
wire addr_en_c ;
wire incr_addr_c ;
wire aw_ready_r ;
wire dec_alen_c ;
reg bvalid_d1_c = 0;
reg [7:0] awlen_cntr_r = 0;
reg [7:0] awlen_int = 0;
reg [1:0] awburst_int = 0;
integer total_bytes = 0;
integer wrap_boundary = 0;
integer wrap_base_addr = 0;
integer num_of_bytes_c = 0;
integer num_of_bytes_r = 0;
// Array to store BIDs
reg [C_AXI_ID_WIDTH-1:0] axi_bid_array[3:0] ;
wire S_AXI_BVALID_axi_wr_fsm;
//-------------------------------------
//AXI WRITE FSM COMPONENT INSTANTIATION
//-------------------------------------
write_netlist_v8_2 #(.C_AXI_TYPE(C_AXI_TYPE)) axi_wr_fsm
(
.S_ACLK(S_ACLK),
.S_ARESETN(S_ARESETN),
.S_AXI_AWVALID(S_AXI_AWVALID),
.aw_ready_r(aw_ready_r),
.S_AXI_WVALID(S_AXI_WVALID),
.S_AXI_WREADY(S_AXI_WREADY),
.S_AXI_BREADY(S_AXI_BREADY),
.S_AXI_WR_EN(S_AXI_WR_EN),
.w_last_c(w_last_c),
.bready_timeout_c(bready_timeout_c),
.addr_en_c(addr_en_c),
.incr_addr_c(incr_addr_c),
.bvalid_c(bvalid_c),
.S_AXI_BVALID (S_AXI_BVALID_axi_wr_fsm)
);
//Wrap Address boundary calculation
always@(*) begin
num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWSIZE:0);
total_bytes = (num_of_bytes_r)*(awlen_int+1);
wrap_base_addr = ((awaddr_reg)/((total_bytes==0)?1:total_bytes))*(total_bytes);
wrap_boundary = wrap_base_addr+total_bytes;
end
//-------------------------------------------------------------------------
// BMG address generation
//-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
awaddr_reg <= 0;
num_of_bytes_r <= 0;
awburst_int <= 0;
end else begin
if (addr_en_c == 1'b1) begin
awaddr_reg <= #FLOP_DELAY S_AXI_AWADDR ;
num_of_bytes_r <= num_of_bytes_c;
awburst_int <= ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWBURST:2'b01);
end else if (incr_addr_c == 1'b1) begin
if (awburst_int == 2'b10) begin
if(awaddr_reg == (wrap_boundary-num_of_bytes_r)) begin
awaddr_reg <= wrap_base_addr;
end else begin
awaddr_reg <= awaddr_reg + num_of_bytes_r;
end
end else if (awburst_int == 2'b01 || awburst_int == 2'b11) begin
awaddr_reg <= awaddr_reg + num_of_bytes_r;
end
end
end
end
assign S_AXI_AWADDR_OUT = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?
awaddr_reg[C_AXI_AWADDR_WIDTH-1:C_RANGE]:awaddr_reg);
//-------------------------------------------------------------------------
// AXI wlast generation
//-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
awlen_cntr_r <= 0;
awlen_int <= 0;
end else begin
if (addr_en_c == 1'b1) begin
awlen_int <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;
awlen_cntr_r <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;
end else if (dec_alen_c == 1'b1) begin
awlen_cntr_r <= #FLOP_DELAY awlen_cntr_r - 1 ;
end
end
end
assign w_last_c = (awlen_cntr_r == 0 && S_AXI_WVALID == 1'b1)?1'b1:1'b0;
assign dec_alen_c = (incr_addr_c | w_last_c);
//-------------------------------------------------------------------------
// Generation of bvalid counter for outstanding transactions
//-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
bvalid_count_r <= 0;
end else begin
// bvalid_count_r generation
if (bvalid_c == 1'b1 && bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1) begin
bvalid_count_r <= #FLOP_DELAY bvalid_count_r ;
end else if (bvalid_c == 1'b1) begin
bvalid_count_r <= #FLOP_DELAY bvalid_count_r + 1 ;
end else if (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1 && bvalid_count_r != 0) begin
bvalid_count_r <= #FLOP_DELAY bvalid_count_r - 1 ;
end
end
end
//-------------------------------------------------------------------------
// Generation of bvalid when BID is used
//-------------------------------------------------------------------------
generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
bvalid_r <= 0;
bvalid_d1_c <= 0;
end else begin
// Delay the generation o bvalid_r for generation for BID
bvalid_d1_c <= bvalid_c;
//external bvalid signal generation
if (bvalid_d1_c == 1'b1) begin
bvalid_r <= #FLOP_DELAY 1'b1 ;
end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin
bvalid_r <= #FLOP_DELAY 0 ;
end
end
end
end
endgenerate
//-------------------------------------------------------------------------
// Generation of bvalid when BID is not used
//-------------------------------------------------------------------------
generate if(C_HAS_AXI_ID == 0) begin:gaxi_bvalid_noid_r
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
bvalid_r <= 0;
end else begin
//external bvalid signal generation
if (bvalid_c == 1'b1) begin
bvalid_r <= #FLOP_DELAY 1'b1 ;
end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin
bvalid_r <= #FLOP_DELAY 0 ;
end
end
end
end
endgenerate
//-------------------------------------------------------------------------
// Generation of Bready timeout
//-------------------------------------------------------------------------
always @(bvalid_count_r) begin
// bready_timeout_c generation
if(bvalid_count_r == C_AXI_OS_WR-1) begin
bready_timeout_c <= 1'b1;
end else begin
bready_timeout_c <= 1'b0;
end
end
//-------------------------------------------------------------------------
// Generation of BID
//-------------------------------------------------------------------------
generate if(C_HAS_AXI_ID == 1) begin:gaxi_bid_gen
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
bvalid_wr_cnt_r <= 0;
bvalid_rd_cnt_r <= 0;
end else begin
// STORE AWID IN AN ARRAY
if(bvalid_c == 1'b1) begin
bvalid_wr_cnt_r <= bvalid_wr_cnt_r + 1;
end
// generate BID FROM AWID ARRAY
bvalid_rd_cnt_r <= #FLOP_DELAY bvalid_rd_cnt_c ;
S_AXI_BID <= axi_bid_array[bvalid_rd_cnt_c];
end
end
assign bvalid_rd_cnt_c = (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1)?bvalid_rd_cnt_r+1:bvalid_rd_cnt_r;
//-------------------------------------------------------------------------
// Storing AWID for generation of BID
//-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if(S_ARESETN == 1'b1) begin
axi_bid_array[0] = 0;
axi_bid_array[1] = 0;
axi_bid_array[2] = 0;
axi_bid_array[3] = 0;
end else if(aw_ready_r == 1'b1 && S_AXI_AWVALID == 1'b1) begin
axi_bid_array[bvalid_wr_cnt_r] <= S_AXI_AWID;
end
end
end
endgenerate
assign S_AXI_BVALID = bvalid_r;
assign S_AXI_AWREADY = aw_ready_r;
endmodule
module blk_mem_axi_read_wrapper_beh_v8_2
# (
//// AXI Interface related parameters start here
parameter C_INTERFACE_TYPE = 0,
parameter C_AXI_TYPE = 0,
parameter C_AXI_SLAVE_TYPE = 0,
parameter C_MEMORY_TYPE = 0,
parameter C_WRITE_WIDTH_A = 4,
parameter C_WRITE_DEPTH_A = 32,
parameter C_ADDRA_WIDTH = 12,
parameter C_AXI_PIPELINE_STAGES = 0,
parameter C_AXI_ARADDR_WIDTH = 12,
parameter C_HAS_AXI_ID = 0,
parameter C_AXI_ID_WIDTH = 4,
parameter C_ADDRB_WIDTH = 12
)
(
//// AXI Global Signals
input S_ACLK,
input S_ARESETN,
//// AXI Full/Lite Slave Read (Read side)
input [C_AXI_ARADDR_WIDTH-1:0] S_AXI_ARADDR,
input [7:0] S_AXI_ARLEN,
input [2:0] S_AXI_ARSIZE,
input [1:0] S_AXI_ARBURST,
input S_AXI_ARVALID,
output S_AXI_ARREADY,
output S_AXI_RLAST,
output S_AXI_RVALID,
input S_AXI_RREADY,
input [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,
output reg [C_AXI_ID_WIDTH-1:0] S_AXI_RID = 0,
//// AXI Full/Lite Read Address Signals to BRAM
output [C_ADDRB_WIDTH-1:0] S_AXI_ARADDR_OUT,
output S_AXI_RD_EN
);
localparam FLOP_DELAY = 100; // 100 ps
localparam C_RANGE = ((C_WRITE_WIDTH_A == 8)?0:
((C_WRITE_WIDTH_A==16)?1:
((C_WRITE_WIDTH_A==32)?2:
((C_WRITE_WIDTH_A==64)?3:
((C_WRITE_WIDTH_A==128)?4:
((C_WRITE_WIDTH_A==256)?5:0))))));
reg [C_AXI_ID_WIDTH-1:0] ar_id_r=0;
wire addr_en_c;
wire rd_en_c;
wire incr_addr_c;
wire single_trans_c;
wire dec_alen_c;
wire mux_sel_c;
wire r_last_c;
wire r_last_int_c;
wire [C_ADDRB_WIDTH-1 : 0] araddr_out;
reg [7:0] arlen_int_r=0;
reg [7:0] arlen_cntr=8'h01;
reg [1:0] arburst_int_c=0;
reg [1:0] arburst_int_r=0;
reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?
C_AXI_ARADDR_WIDTH:C_ADDRA_WIDTH)-1:0] araddr_reg =0;
integer num_of_bytes_c = 0;
integer total_bytes = 0;
integer num_of_bytes_r = 0;
integer wrap_base_addr_r = 0;
integer wrap_boundary_r = 0;
reg [7:0] arlen_int_c=0;
integer total_bytes_c = 0;
integer wrap_base_addr_c = 0;
integer wrap_boundary_c = 0;
assign dec_alen_c = incr_addr_c | r_last_int_c;
read_netlist_v8_2
#(.C_AXI_TYPE (1),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH))
axi_read_fsm (
.S_AXI_INCR_ADDR(incr_addr_c),
.S_AXI_ADDR_EN(addr_en_c),
.S_AXI_SINGLE_TRANS(single_trans_c),
.S_AXI_MUX_SEL(mux_sel_c),
.S_AXI_R_LAST(r_last_c),
.S_AXI_R_LAST_INT(r_last_int_c),
//// AXI Global Signals
.S_ACLK(S_ACLK),
.S_ARESETN(S_ARESETN),
//// AXI Full/Lite Slave Read (Read side)
.S_AXI_ARLEN(S_AXI_ARLEN),
.S_AXI_ARVALID(S_AXI_ARVALID),
.S_AXI_ARREADY(S_AXI_ARREADY),
.S_AXI_RLAST(S_AXI_RLAST),
.S_AXI_RVALID(S_AXI_RVALID),
.S_AXI_RREADY(S_AXI_RREADY),
//// AXI Full/Lite Read Address Signals to BRAM
.S_AXI_RD_EN(rd_en_c)
);
always@(*) begin
num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARSIZE:0);
total_bytes = (num_of_bytes_r)*(arlen_int_r+1);
wrap_base_addr_r = ((araddr_reg)/(total_bytes==0?1:total_bytes))*(total_bytes);
wrap_boundary_r = wrap_base_addr_r+total_bytes;
//////// combinatorial from interface
arlen_int_c = (C_AXI_TYPE == 0?0:S_AXI_ARLEN);
total_bytes_c = (num_of_bytes_c)*(arlen_int_c+1);
wrap_base_addr_c = ((S_AXI_ARADDR)/(total_bytes_c==0?1:total_bytes_c))*(total_bytes_c);
wrap_boundary_c = wrap_base_addr_c+total_bytes_c;
arburst_int_c = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARBURST:1);
end
////-------------------------------------------------------------------------
//// BMG address generation
////-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
araddr_reg <= 0;
arburst_int_r <= 0;
num_of_bytes_r <= 0;
end else begin
if (incr_addr_c == 1'b1 && addr_en_c == 1'b1 && single_trans_c == 1'b0) begin
arburst_int_r <= arburst_int_c;
num_of_bytes_r <= num_of_bytes_c;
if (arburst_int_c == 2'b10) begin
if(S_AXI_ARADDR == (wrap_boundary_c-num_of_bytes_c)) begin
araddr_reg <= wrap_base_addr_c;
end else begin
araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
end
end else if (arburst_int_c == 2'b01 || arburst_int_c == 2'b11) begin
araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
end
end else if (addr_en_c == 1'b1) begin
araddr_reg <= S_AXI_ARADDR;
num_of_bytes_r <= num_of_bytes_c;
arburst_int_r <= arburst_int_c;
end else if (incr_addr_c == 1'b1) begin
if (arburst_int_r == 2'b10) begin
if(araddr_reg == (wrap_boundary_r-num_of_bytes_r)) begin
araddr_reg <= wrap_base_addr_r;
end else begin
araddr_reg <= araddr_reg + num_of_bytes_r;
end
end else if (arburst_int_r == 2'b01 || arburst_int_r == 2'b11) begin
araddr_reg <= araddr_reg + num_of_bytes_r;
end
end
end
end
assign araddr_out = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?araddr_reg[C_AXI_ARADDR_WIDTH-1:C_RANGE]:araddr_reg);
////-----------------------------------------------------------------------
//// Counter to generate r_last_int_c from registered ARLEN - AXI FULL FSM
////-----------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
arlen_cntr <= 8'h01;
arlen_int_r <= 0;
end else begin
if (addr_en_c == 1'b1 && dec_alen_c == 1'b1 && single_trans_c == 1'b0) begin
arlen_int_r <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;
arlen_cntr <= S_AXI_ARLEN - 1'b1;
end else if (addr_en_c == 1'b1) begin
arlen_int_r <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;
arlen_cntr <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;
end else if (dec_alen_c == 1'b1) begin
arlen_cntr <= arlen_cntr - 1'b1 ;
end
else begin
arlen_cntr <= arlen_cntr;
end
end
end
assign r_last_int_c = (arlen_cntr == 0 && S_AXI_RREADY == 1'b1)?1'b1:1'b0;
////------------------------------------------------------------------------
//// AXI FULL FSM
//// Mux Selection of ARADDR
//// ARADDR is driven out from the read fsm based on the mux_sel_c
//// Based on mux_sel either ARADDR is given out or the latched ARADDR is
//// given out to BRAM
////------------------------------------------------------------------------
assign S_AXI_ARADDR_OUT = (mux_sel_c == 1'b0)?((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARADDR[C_AXI_ARADDR_WIDTH-1:C_RANGE]:S_AXI_ARADDR):araddr_out;
////------------------------------------------------------------------------
//// Assign output signals - AXI FULL FSM
////------------------------------------------------------------------------
assign S_AXI_RD_EN = rd_en_c;
generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
S_AXI_RID <= 0;
ar_id_r <= 0;
end else begin
if (addr_en_c == 1'b1 && rd_en_c == 1'b1) begin
S_AXI_RID <= S_AXI_ARID;
ar_id_r <= S_AXI_ARID;
end else if (addr_en_c == 1'b1 && rd_en_c == 1'b0) begin
ar_id_r <= S_AXI_ARID;
end else if (rd_en_c == 1'b1) begin
S_AXI_RID <= ar_id_r;
end
end
end
end
endgenerate
endmodule
module blk_mem_axi_regs_fwd_v8_2
#(parameter C_DATA_WIDTH = 8
)(
input ACLK,
input ARESET,
input S_VALID,
output S_READY,
input [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
output M_VALID,
input M_READY,
output reg [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA
);
reg [C_DATA_WIDTH-1:0] STORAGE_DATA;
wire S_READY_I;
reg M_VALID_I;
reg [1:0] ARESET_D;
//assign local signal to its output signal
assign S_READY = S_READY_I;
assign M_VALID = M_VALID_I;
always @(posedge ACLK) begin
ARESET_D <= {ARESET_D[0], ARESET};
end
//Save payload data whenever we have a transaction on the slave side
always @(posedge ACLK or ARESET) begin
if (ARESET == 1'b1) begin
STORAGE_DATA <= 0;
end else begin
if(S_VALID == 1'b1 && S_READY_I == 1'b1 ) begin
STORAGE_DATA <= S_PAYLOAD_DATA;
end
end
end
always @(posedge ACLK) begin
M_PAYLOAD_DATA = STORAGE_DATA;
end
//M_Valid set to high when we have a completed transfer on slave side
//Is removed on a M_READY except if we have a new transfer on the slave side
always @(posedge ACLK or ARESET_D) begin
if (ARESET_D != 2'b00) begin
M_VALID_I <= 1'b0;
end else begin
if (S_VALID == 1'b1) begin
//Always set M_VALID_I when slave side is valid
M_VALID_I <= 1'b1;
end else if (M_READY == 1'b1 ) begin
//Clear (or keep) when no slave side is valid but master side is ready
M_VALID_I <= 1'b0;
end
end
end
//Slave Ready is either when Master side drives M_READY or we have space in our storage data
assign S_READY_I = (M_READY || (!M_VALID_I)) && !(|(ARESET_D));
endmodule
//*****************************************************************************
// Output Register Stage module
//
// This module builds the output register stages of the memory. This module is
// instantiated in the main memory module (BLK_MEM_GEN_v8_2) which is
// declared/implemented further down in this file.
//*****************************************************************************
module BLK_MEM_GEN_v8_2_output_stage
#(parameter C_FAMILY = "virtex7",
parameter C_XDEVICEFAMILY = "virtex7",
parameter C_RST_TYPE = "SYNC",
parameter C_HAS_RST = 0,
parameter C_RSTRAM = 0,
parameter C_RST_PRIORITY = "CE",
parameter C_INIT_VAL = "0",
parameter C_HAS_EN = 0,
parameter C_HAS_REGCE = 0,
parameter C_DATA_WIDTH = 32,
parameter C_ADDRB_WIDTH = 10,
parameter C_HAS_MEM_OUTPUT_REGS = 0,
parameter C_USE_SOFTECC = 0,
parameter C_USE_ECC = 0,
parameter NUM_STAGES = 1,
parameter C_EN_ECC_PIPE = 0,
parameter FLOP_DELAY = 100
)
(
input CLK,
input RST,
input EN,
input REGCE,
input [C_DATA_WIDTH-1:0] DIN_I,
output reg [C_DATA_WIDTH-1:0] DOUT,
input SBITERR_IN_I,
input DBITERR_IN_I,
output reg SBITERR,
output reg DBITERR,
input [C_ADDRB_WIDTH-1:0] RDADDRECC_IN_I,
input ECCPIPECE,
output reg [C_ADDRB_WIDTH-1:0] RDADDRECC
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
// options are available - "spartan3", "spartan6",
// "virtex4", "virtex5", "virtex6" and "virtex6l".
// C_RST_TYPE : Type of reset - Synchronous or Asynchronous
// C_HAS_RST : Determines the presence of the RST port
// C_RSTRAM : Determines if special reset behavior is used
// C_RST_PRIORITY : Determines the priority between CE and SR
// C_INIT_VAL : Initialization value
// C_HAS_EN : Determines the presence of the EN port
// C_HAS_REGCE : Determines the presence of the REGCE port
// C_DATA_WIDTH : Memory write/read width
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_MEM_OUTPUT_REGS : Designates the use of a register at the output
// of the RAM primitive
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// C_USE_ECC : Determines if the ECC feature is used or
// not. Only applicable for V5 and V6
// NUM_STAGES : Determines the number of output stages
// FLOP_DELAY : Constant delay for register assignments
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLK : Clock to synchronize all read and write operations
// RST : Reset input to reset memory outputs to a user-defined
// reset state
// EN : Enable all read and write operations
// REGCE : Register Clock Enable to control each pipeline output
// register stages
// DIN : Data input to the Output stage.
// DOUT : Final Data output
// SBITERR_IN : SBITERR input signal to the Output stage.
// SBITERR : Final SBITERR Output signal.
// DBITERR_IN : DBITERR input signal to the Output stage.
// DBITERR : Final DBITERR Output signal.
// RDADDRECC_IN : RDADDRECC input signal to the Output stage.
// RDADDRECC : Final RDADDRECC Output signal.
//////////////////////////////////////////////////////////////////////////
// Fix for CR-509792
localparam REG_STAGES = (NUM_STAGES < 2) ? 1 : NUM_STAGES-1;
// Declare the pipeline registers
// (includes mem output reg, mux pipeline stages, and mux output reg)
reg [C_DATA_WIDTH*REG_STAGES-1:0] out_regs;
reg [C_ADDRB_WIDTH*REG_STAGES-1:0] rdaddrecc_regs;
reg [REG_STAGES-1:0] sbiterr_regs;
reg [REG_STAGES-1:0] dbiterr_regs;
reg [C_DATA_WIDTH*8-1:0] init_str = C_INIT_VAL;
reg [C_DATA_WIDTH-1:0] init_val ;
//*********************************************
// Wire off optional inputs based on parameters
//*********************************************
wire en_i;
wire regce_i;
wire rst_i;
// Internal signals
reg [C_DATA_WIDTH-1:0] DIN;
reg [C_ADDRB_WIDTH-1:0] RDADDRECC_IN;
reg SBITERR_IN;
reg DBITERR_IN;
// Internal enable for output registers is tied to user EN or '1' depending
// on parameters
assign en_i = (C_HAS_EN==0 || EN);
// Internal register enable for output registers is tied to user REGCE, EN or
// '1' depending on parameters
// For V4 ECC, REGCE is always 1
// Virtex-4 ECC Not Yet Supported
assign regce_i = ((C_HAS_REGCE==1) && REGCE) ||
((C_HAS_REGCE==0) && (C_HAS_EN==0 || EN));
//Internal SRR is tied to user RST or '0' depending on parameters
assign rst_i = (C_HAS_RST==1) && RST;
//****************************************************
// Power on: load up the output registers and latches
//****************************************************
initial begin
if (!($sscanf(init_str, "%h", init_val))) begin
init_val = 0;
end
DOUT = init_val;
RDADDRECC = 0;
SBITERR = 1'b0;
DBITERR = 1'b0;
DIN = {(C_DATA_WIDTH){1'b0}};
RDADDRECC_IN = 0;
SBITERR_IN = 0;
DBITERR_IN = 0;
// This will be one wider than need, but 0 is an error
out_regs = {(REG_STAGES+1){init_val}};
rdaddrecc_regs = 0;
sbiterr_regs = {(REG_STAGES+1){1'b0}};
dbiterr_regs = {(REG_STAGES+1){1'b0}};
end
//***********************************************
// NUM_STAGES = 0 (No output registers. RAM only)
//***********************************************
generate if (NUM_STAGES == 0) begin : zero_stages
always @* begin
DOUT = DIN;
RDADDRECC = RDADDRECC_IN;
SBITERR = SBITERR_IN;
DBITERR = DBITERR_IN;
end
end
endgenerate
generate if (C_EN_ECC_PIPE == 0) begin : no_ecc_pipe_reg
always @* begin
DIN = DIN_I;
SBITERR_IN = SBITERR_IN_I;
DBITERR_IN = DBITERR_IN_I;
RDADDRECC_IN = RDADDRECC_IN_I;
end
end
endgenerate
generate if (C_EN_ECC_PIPE == 1) begin : with_ecc_pipe_reg
always @(posedge CLK) begin
if(ECCPIPECE == 1) begin
DIN <= #FLOP_DELAY DIN_I;
SBITERR_IN <= #FLOP_DELAY SBITERR_IN_I;
DBITERR_IN <= #FLOP_DELAY DBITERR_IN_I;
RDADDRECC_IN <= #FLOP_DELAY RDADDRECC_IN_I;
end
end
end
endgenerate
//***********************************************
// NUM_STAGES = 1
// (Mem Output Reg only or Mux Output Reg only)
//***********************************************
// Possible valid combinations:
// Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1)
// +-----------------------------------------+
// | C_RSTRAM_* | Reset Behavior |
// +----------------+------------------------+
// | 0 | Normal Behavior |
// +----------------+------------------------+
// | 1 | Special Behavior |
// +----------------+------------------------+
//
// Normal = REGCE gates reset, as in the case of all families except S3ADSP.
// Special = EN gates reset, as in the case of S3ADSP.
generate if (NUM_STAGES == 1 &&
(C_RSTRAM == 0 || (C_RSTRAM == 1 && (C_XDEVICEFAMILY != "spartan3adsp" && C_XDEVICEFAMILY != "aspartan3adsp" )) ||
C_HAS_MEM_OUTPUT_REGS == 0 || C_HAS_RST == 0))
begin : one_stages_norm
always @(posedge CLK) begin
if (C_RST_PRIORITY == "CE") begin //REGCE has priority
if (regce_i && rst_i) begin
DOUT <= #FLOP_DELAY init_val;
RDADDRECC <= #FLOP_DELAY 0;
SBITERR <= #FLOP_DELAY 1'b0;
DBITERR <= #FLOP_DELAY 1'b0;
end else if (regce_i) begin
DOUT <= #FLOP_DELAY DIN;
RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;
SBITERR <= #FLOP_DELAY SBITERR_IN;
DBITERR <= #FLOP_DELAY DBITERR_IN;
end //Output signal assignments
end else begin //RST has priority
if (rst_i) begin
DOUT <= #FLOP_DELAY init_val;
RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;
SBITERR <= #FLOP_DELAY 1'b0;
DBITERR <= #FLOP_DELAY 1'b0;
end else if (regce_i) begin
DOUT <= #FLOP_DELAY DIN;
RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;
SBITERR <= #FLOP_DELAY SBITERR_IN;
DBITERR <= #FLOP_DELAY DBITERR_IN;
end //Output signal assignments
end //end Priority conditions
end //end RST Type conditions
end //end one_stages_norm generate statement
endgenerate
// Special Reset Behavior for S3ADSP
generate if (NUM_STAGES == 1 && C_RSTRAM == 1 && (C_XDEVICEFAMILY =="spartan3adsp" || C_XDEVICEFAMILY =="aspartan3adsp"))
begin : one_stage_splbhv
always @(posedge CLK) begin
if (en_i && rst_i) begin
DOUT <= #FLOP_DELAY init_val;
end else if (regce_i && !rst_i) begin
DOUT <= #FLOP_DELAY DIN;
end //Output signal assignments
end //end CLK
end //end one_stage_splbhv generate statement
endgenerate
//************************************************************
// NUM_STAGES > 1
// Mem Output Reg + Mux Output Reg
// or
// Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg
// or
// Mux Pipeline Stages (>0) + Mux Output Reg
//*************************************************************
generate if (NUM_STAGES > 1) begin : multi_stage
//Asynchronous Reset
always @(posedge CLK) begin
if (C_RST_PRIORITY == "CE") begin //REGCE has priority
if (regce_i && rst_i) begin
DOUT <= #FLOP_DELAY init_val;
RDADDRECC <= #FLOP_DELAY 0;
SBITERR <= #FLOP_DELAY 1'b0;
DBITERR <= #FLOP_DELAY 1'b0;
end else if (regce_i) begin
DOUT <= #FLOP_DELAY
out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];
RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];
SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];
DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];
end //Output signal assignments
end else begin //RST has priority
if (rst_i) begin
DOUT <= #FLOP_DELAY init_val;
RDADDRECC <= #FLOP_DELAY 0;
SBITERR <= #FLOP_DELAY 1'b0;
DBITERR <= #FLOP_DELAY 1'b0;
end else if (regce_i) begin
DOUT <= #FLOP_DELAY
out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];
RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];
SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];
DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];
end //Output signal assignments
end //end Priority conditions
// Shift the data through the output stages
if (en_i) begin
out_regs <= #FLOP_DELAY (out_regs << C_DATA_WIDTH) | DIN;
rdaddrecc_regs <= #FLOP_DELAY (rdaddrecc_regs << C_ADDRB_WIDTH) | RDADDRECC_IN;
sbiterr_regs <= #FLOP_DELAY (sbiterr_regs << 1) | SBITERR_IN;
dbiterr_regs <= #FLOP_DELAY (dbiterr_regs << 1) | DBITERR_IN;
end
end //end CLK
end //end multi_stage generate statement
endgenerate
endmodule
module BLK_MEM_GEN_v8_2_softecc_output_reg_stage
#(parameter C_DATA_WIDTH = 32,
parameter C_ADDRB_WIDTH = 10,
parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,
parameter C_USE_SOFTECC = 0,
parameter FLOP_DELAY = 100
)
(
input CLK,
input [C_DATA_WIDTH-1:0] DIN,
output reg [C_DATA_WIDTH-1:0] DOUT,
input SBITERR_IN,
input DBITERR_IN,
output reg SBITERR,
output reg DBITERR,
input [C_ADDRB_WIDTH-1:0] RDADDRECC_IN,
output reg [C_ADDRB_WIDTH-1:0] RDADDRECC
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_DATA_WIDTH : Memory write/read width
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_SOFTECC_OUTPUT_REGS_B : Designates the use of a register at the output
// of the RAM primitive
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// FLOP_DELAY : Constant delay for register assignments
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLK : Clock to synchronize all read and write operations
// DIN : Data input to the Output stage.
// DOUT : Final Data output
// SBITERR_IN : SBITERR input signal to the Output stage.
// SBITERR : Final SBITERR Output signal.
// DBITERR_IN : DBITERR input signal to the Output stage.
// DBITERR : Final DBITERR Output signal.
// RDADDRECC_IN : RDADDRECC input signal to the Output stage.
// RDADDRECC : Final RDADDRECC Output signal.
//////////////////////////////////////////////////////////////////////////
reg [C_DATA_WIDTH-1:0] dout_i = 0;
reg sbiterr_i = 0;
reg dbiterr_i = 0;
reg [C_ADDRB_WIDTH-1:0] rdaddrecc_i = 0;
//***********************************************
// NO OUTPUT REGISTERS.
//***********************************************
generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==0) begin : no_output_stage
always @* begin
DOUT = DIN;
RDADDRECC = RDADDRECC_IN;
SBITERR = SBITERR_IN;
DBITERR = DBITERR_IN;
end
end
endgenerate
//***********************************************
// WITH OUTPUT REGISTERS.
//***********************************************
generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==1) begin : has_output_stage
always @(posedge CLK) begin
dout_i <= #FLOP_DELAY DIN;
rdaddrecc_i <= #FLOP_DELAY RDADDRECC_IN;
sbiterr_i <= #FLOP_DELAY SBITERR_IN;
dbiterr_i <= #FLOP_DELAY DBITERR_IN;
end
always @* begin
DOUT = dout_i;
RDADDRECC = rdaddrecc_i;
SBITERR = sbiterr_i;
DBITERR = dbiterr_i;
end //end always
end //end in_or_out_stage generate statement
endgenerate
endmodule
//*****************************************************************************
// Main Memory module
//
// This module is the top-level behavioral model and this implements the RAM
//*****************************************************************************
module BLK_MEM_GEN_v8_2_mem_module
#(parameter C_CORENAME = "blk_mem_gen_v8_2",
parameter C_FAMILY = "virtex7",
parameter C_XDEVICEFAMILY = "virtex7",
parameter C_MEM_TYPE = 2,
parameter C_BYTE_SIZE = 9,
parameter C_USE_BRAM_BLOCK = 0,
parameter C_ALGORITHM = 1,
parameter C_PRIM_TYPE = 3,
parameter C_LOAD_INIT_FILE = 0,
parameter C_INIT_FILE_NAME = "",
parameter C_INIT_FILE = "",
parameter C_USE_DEFAULT_DATA = 0,
parameter C_DEFAULT_DATA = "0",
parameter C_RST_TYPE = "SYNC",
parameter C_HAS_RSTA = 0,
parameter C_RST_PRIORITY_A = "CE",
parameter C_RSTRAM_A = 0,
parameter C_INITA_VAL = "0",
parameter C_HAS_ENA = 1,
parameter C_HAS_REGCEA = 0,
parameter C_USE_BYTE_WEA = 0,
parameter C_WEA_WIDTH = 1,
parameter C_WRITE_MODE_A = "WRITE_FIRST",
parameter C_WRITE_WIDTH_A = 32,
parameter C_READ_WIDTH_A = 32,
parameter C_WRITE_DEPTH_A = 64,
parameter C_READ_DEPTH_A = 64,
parameter C_ADDRA_WIDTH = 5,
parameter C_HAS_RSTB = 0,
parameter C_RST_PRIORITY_B = "CE",
parameter C_RSTRAM_B = 0,
parameter C_INITB_VAL = "",
parameter C_HAS_ENB = 1,
parameter C_HAS_REGCEB = 0,
parameter C_USE_BYTE_WEB = 0,
parameter C_WEB_WIDTH = 1,
parameter C_WRITE_MODE_B = "WRITE_FIRST",
parameter C_WRITE_WIDTH_B = 32,
parameter C_READ_WIDTH_B = 32,
parameter C_WRITE_DEPTH_B = 64,
parameter C_READ_DEPTH_B = 64,
parameter C_ADDRB_WIDTH = 5,
parameter C_HAS_MEM_OUTPUT_REGS_A = 0,
parameter C_HAS_MEM_OUTPUT_REGS_B = 0,
parameter C_HAS_MUX_OUTPUT_REGS_A = 0,
parameter C_HAS_MUX_OUTPUT_REGS_B = 0,
parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,
parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,
parameter C_MUX_PIPELINE_STAGES = 0,
parameter C_USE_SOFTECC = 0,
parameter C_USE_ECC = 0,
parameter C_HAS_INJECTERR = 0,
parameter C_SIM_COLLISION_CHECK = "NONE",
parameter C_COMMON_CLK = 1,
parameter FLOP_DELAY = 100,
parameter C_DISABLE_WARN_BHV_COLL = 0,
parameter C_EN_ECC_PIPE = 0,
parameter C_DISABLE_WARN_BHV_RANGE = 0
)
(input CLKA,
input RSTA,
input ENA,
input REGCEA,
input [C_WEA_WIDTH-1:0] WEA,
input [C_ADDRA_WIDTH-1:0] ADDRA,
input [C_WRITE_WIDTH_A-1:0] DINA,
output [C_READ_WIDTH_A-1:0] DOUTA,
input CLKB,
input RSTB,
input ENB,
input REGCEB,
input [C_WEB_WIDTH-1:0] WEB,
input [C_ADDRB_WIDTH-1:0] ADDRB,
input [C_WRITE_WIDTH_B-1:0] DINB,
output [C_READ_WIDTH_B-1:0] DOUTB,
input INJECTSBITERR,
input INJECTDBITERR,
input ECCPIPECE,
input SLEEP,
output SBITERR,
output DBITERR,
output [C_ADDRB_WIDTH-1:0] RDADDRECC
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_CORENAME : Instance name of the Block Memory Generator core
// C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
// options are available - "spartan3", "spartan6",
// "virtex4", "virtex5", "virtex6" and "virtex6l".
// C_MEM_TYPE : Designates memory type.
// It can be
// 0 - Single Port Memory
// 1 - Simple Dual Port Memory
// 2 - True Dual Port Memory
// 3 - Single Port Read Only Memory
// 4 - Dual Port Read Only Memory
// C_BYTE_SIZE : Size of a byte (8 or 9 bits)
// C_ALGORITHM : Designates the algorithm method used
// for constructing the memory.
// It can be Fixed_Primitives, Minimum_Area or
// Low_Power
// C_PRIM_TYPE : Designates the user selected primitive used to
// construct the memory.
//
// C_LOAD_INIT_FILE : Designates the use of an initialization file to
// initialize memory contents.
// C_INIT_FILE_NAME : Memory initialization file name.
// C_USE_DEFAULT_DATA : Designates whether to fill remaining
// initialization space with default data
// C_DEFAULT_DATA : Default value of all memory locations
// not initialized by the memory
// initialization file.
// C_RST_TYPE : Type of reset - Synchronous or Asynchronous
// C_HAS_RSTA : Determines the presence of the RSTA port
// C_RST_PRIORITY_A : Determines the priority between CE and SR for
// Port A.
// C_RSTRAM_A : Determines if special reset behavior is used for
// Port A
// C_INITA_VAL : The initialization value for Port A
// C_HAS_ENA : Determines the presence of the ENA port
// C_HAS_REGCEA : Determines the presence of the REGCEA port
// C_USE_BYTE_WEA : Determines if the Byte Write is used or not.
// C_WEA_WIDTH : The width of the WEA port
// C_WRITE_MODE_A : Configurable write mode for Port A. It can be
// WRITE_FIRST, READ_FIRST or NO_CHANGE.
// C_WRITE_WIDTH_A : Memory write width for Port A.
// C_READ_WIDTH_A : Memory read width for Port A.
// C_WRITE_DEPTH_A : Memory write depth for Port A.
// C_READ_DEPTH_A : Memory read depth for Port A.
// C_ADDRA_WIDTH : Width of the ADDRA input port
// C_HAS_RSTB : Determines the presence of the RSTB port
// C_RST_PRIORITY_B : Determines the priority between CE and SR for
// Port B.
// C_RSTRAM_B : Determines if special reset behavior is used for
// Port B
// C_INITB_VAL : The initialization value for Port B
// C_HAS_ENB : Determines the presence of the ENB port
// C_HAS_REGCEB : Determines the presence of the REGCEB port
// C_USE_BYTE_WEB : Determines if the Byte Write is used or not.
// C_WEB_WIDTH : The width of the WEB port
// C_WRITE_MODE_B : Configurable write mode for Port B. It can be
// WRITE_FIRST, READ_FIRST or NO_CHANGE.
// C_WRITE_WIDTH_B : Memory write width for Port B.
// C_READ_WIDTH_B : Memory read width for Port B.
// C_WRITE_DEPTH_B : Memory write depth for Port B.
// C_READ_DEPTH_B : Memory read depth for Port B.
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output
// of the RAM primitive for Port A.
// C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output
// of the RAM primitive for Port B.
// C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
// of the MUX for Port A.
// C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
// of the MUX for Port B.
// C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in
// between the muxes.
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// C_USE_ECC : Determines if the ECC feature is used or
// not. Only applicable for V5 and V6
// C_HAS_INJECTERR : Determines if the error injection pins
// are present or not. If the ECC feature
// is not used, this value is defaulted to
// 0, else the following are the allowed
// values:
// 0 : No INJECTSBITERR or INJECTDBITERR pins
// 1 : Only INJECTSBITERR pin exists
// 2 : Only INJECTDBITERR pin exists
// 3 : Both INJECTSBITERR and INJECTDBITERR pins exist
// C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision
// warnings. It can be "ALL", "NONE",
// "Warnings_Only" or "Generate_X_Only".
// C_COMMON_CLK : Determins if the core has a single CLK input.
// C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
// C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range
// warnings
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLKA : Clock to synchronize all read and write operations of Port A.
// RSTA : Reset input to reset memory outputs to a user-defined
// reset state for Port A.
// ENA : Enable all read and write operations of Port A.
// REGCEA : Register Clock Enable to control each pipeline output
// register stages for Port A.
// WEA : Write Enable to enable all write operations of Port A.
// ADDRA : Address of Port A.
// DINA : Data input of Port A.
// DOUTA : Data output of Port A.
// CLKB : Clock to synchronize all read and write operations of Port B.
// RSTB : Reset input to reset memory outputs to a user-defined
// reset state for Port B.
// ENB : Enable all read and write operations of Port B.
// REGCEB : Register Clock Enable to control each pipeline output
// register stages for Port B.
// WEB : Write Enable to enable all write operations of Port B.
// ADDRB : Address of Port B.
// DINB : Data input of Port B.
// DOUTB : Data output of Port B.
// INJECTSBITERR : Single Bit ECC Error Injection Pin.
// INJECTDBITERR : Double Bit ECC Error Injection Pin.
// SBITERR : Output signal indicating that a Single Bit ECC Error has been
// detected and corrected.
// DBITERR : Output signal indicating that a Double Bit ECC Error has been
// detected.
// RDADDRECC : Read Address Output signal indicating address at which an
// ECC error has occurred.
//////////////////////////////////////////////////////////////////////////
// Note: C_CORENAME parameter is hard-coded to "blk_mem_gen_v8_2" and it is
// only used by this module to print warning messages. It is neither passed
// down from blk_mem_gen_v8_2_xst.v nor present in the instantiation template
// coregen generates
//***************************************************************************
// constants for the core behavior
//***************************************************************************
// file handles for logging
//--------------------------------------------------
localparam ADDRFILE = 32'h8000_0001; //stdout for addr out of range
localparam COLLFILE = 32'h8000_0001; //stdout for coll detection
localparam ERRFILE = 32'h8000_0001; //stdout for file I/O errors
// other constants
//--------------------------------------------------
localparam COLL_DELAY = 100; // 100 ps
// locally derived parameters to determine memory shape
//-----------------------------------------------------
localparam CHKBIT_WIDTH = (C_WRITE_WIDTH_A>57 ? 8 : (C_WRITE_WIDTH_A>26 ? 7 : (C_WRITE_WIDTH_A>11 ? 6 : (C_WRITE_WIDTH_A>4 ? 5 : (C_WRITE_WIDTH_A<5 ? 4 :0)))));
localparam MIN_WIDTH_A = (C_WRITE_WIDTH_A < C_READ_WIDTH_A) ?
C_WRITE_WIDTH_A : C_READ_WIDTH_A;
localparam MIN_WIDTH_B = (C_WRITE_WIDTH_B < C_READ_WIDTH_B) ?
C_WRITE_WIDTH_B : C_READ_WIDTH_B;
localparam MIN_WIDTH = (MIN_WIDTH_A < MIN_WIDTH_B) ?
MIN_WIDTH_A : MIN_WIDTH_B;
localparam MAX_DEPTH_A = (C_WRITE_DEPTH_A > C_READ_DEPTH_A) ?
C_WRITE_DEPTH_A : C_READ_DEPTH_A;
localparam MAX_DEPTH_B = (C_WRITE_DEPTH_B > C_READ_DEPTH_B) ?
C_WRITE_DEPTH_B : C_READ_DEPTH_B;
localparam MAX_DEPTH = (MAX_DEPTH_A > MAX_DEPTH_B) ?
MAX_DEPTH_A : MAX_DEPTH_B;
// locally derived parameters to assist memory access
//----------------------------------------------------
// Calculate the width ratios of each port with respect to the narrowest
// port
localparam WRITE_WIDTH_RATIO_A = C_WRITE_WIDTH_A/MIN_WIDTH;
localparam READ_WIDTH_RATIO_A = C_READ_WIDTH_A/MIN_WIDTH;
localparam WRITE_WIDTH_RATIO_B = C_WRITE_WIDTH_B/MIN_WIDTH;
localparam READ_WIDTH_RATIO_B = C_READ_WIDTH_B/MIN_WIDTH;
// To modify the LSBs of the 'wider' data to the actual
// address value
//----------------------------------------------------
localparam WRITE_ADDR_A_DIV = C_WRITE_WIDTH_A/MIN_WIDTH_A;
localparam READ_ADDR_A_DIV = C_READ_WIDTH_A/MIN_WIDTH_A;
localparam WRITE_ADDR_B_DIV = C_WRITE_WIDTH_B/MIN_WIDTH_B;
localparam READ_ADDR_B_DIV = C_READ_WIDTH_B/MIN_WIDTH_B;
// If byte writes aren't being used, make sure BYTE_SIZE is not
// wider than the memory elements to avoid compilation warnings
localparam BYTE_SIZE = (C_BYTE_SIZE < MIN_WIDTH) ? C_BYTE_SIZE : MIN_WIDTH;
// The memory
reg [MIN_WIDTH-1:0] memory [0:MAX_DEPTH-1];
reg [MIN_WIDTH-1:0] temp_mem_array [0:MAX_DEPTH-1];
reg [C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:0] doublebit_error = 3;
// ECC error arrays
reg sbiterr_arr [0:MAX_DEPTH-1];
reg dbiterr_arr [0:MAX_DEPTH-1];
reg softecc_sbiterr_arr [0:MAX_DEPTH-1];
reg softecc_dbiterr_arr [0:MAX_DEPTH-1];
// Memory output 'latches'
reg [C_READ_WIDTH_A-1:0] memory_out_a;
reg [C_READ_WIDTH_B-1:0] memory_out_b;
// ECC error inputs and outputs from output_stage module:
reg sbiterr_in;
wire sbiterr_sdp;
reg dbiterr_in;
wire dbiterr_sdp;
wire [C_READ_WIDTH_B-1:0] dout_i;
wire dbiterr_i;
wire sbiterr_i;
wire [C_ADDRB_WIDTH-1:0] rdaddrecc_i;
reg [C_ADDRB_WIDTH-1:0] rdaddrecc_in;
wire [C_ADDRB_WIDTH-1:0] rdaddrecc_sdp;
// Reset values
reg [C_READ_WIDTH_A-1:0] inita_val;
reg [C_READ_WIDTH_B-1:0] initb_val;
// Collision detect
reg is_collision;
reg is_collision_a, is_collision_delay_a;
reg is_collision_b, is_collision_delay_b;
// Temporary variables for initialization
//---------------------------------------
integer status;
integer initfile;
integer meminitfile;
// data input buffer
reg [C_WRITE_WIDTH_A-1:0] mif_data;
reg [C_WRITE_WIDTH_A-1:0] mem_data;
// string values in hex
reg [C_READ_WIDTH_A*8-1:0] inita_str = C_INITA_VAL;
reg [C_READ_WIDTH_B*8-1:0] initb_str = C_INITB_VAL;
reg [C_WRITE_WIDTH_A*8-1:0] default_data_str = C_DEFAULT_DATA;
// initialization filename
reg [1023*8-1:0] init_file_str = C_INIT_FILE_NAME;
reg [1023*8-1:0] mem_init_file_str = C_INIT_FILE;
//Constants used to calculate the effective address widths for each of the
//four ports.
integer cnt = 1;
integer write_addr_a_width, read_addr_a_width;
integer write_addr_b_width, read_addr_b_width;
localparam C_FAMILY_LOCALPARAM = (C_FAMILY=="virtexu"?"virtex7":(C_FAMILY=="kintexu" ? "virtex7":(C_FAMILY=="virtex7" ? "virtex7" : (C_FAMILY=="virtex7l" ? "virtex7" : (C_FAMILY=="qvirtex7" ? "virtex7" : (C_FAMILY=="qvirtex7l" ? "virtex7" : (C_FAMILY=="kintex7" ? "virtex7" : (C_FAMILY=="kintex7l" ? "virtex7" : (C_FAMILY=="qkintex7" ? "virtex7" : (C_FAMILY=="qkintex7l" ? "virtex7" : (C_FAMILY=="artix7" ? "virtex7" : (C_FAMILY=="artix7l" ? "virtex7" : (C_FAMILY=="qartix7" ? "virtex7" : (C_FAMILY=="qartix7l" ? "virtex7" : (C_FAMILY=="aartix7" ? "virtex7" : (C_FAMILY=="zynq" ? "virtex7" : (C_FAMILY=="azynq" ? "virtex7" : (C_FAMILY=="qzynq" ? "virtex7" : C_FAMILY))))))))))))))))));
// Internal configuration parameters
//---------------------------------------------
localparam SINGLE_PORT = (C_MEM_TYPE==0 || C_MEM_TYPE==3);
localparam IS_ROM = (C_MEM_TYPE==3 || C_MEM_TYPE==4);
localparam HAS_A_WRITE = (!IS_ROM);
localparam HAS_B_WRITE = (C_MEM_TYPE==2);
localparam HAS_A_READ = (C_MEM_TYPE!=1);
localparam HAS_B_READ = (!SINGLE_PORT);
localparam HAS_B_PORT = (HAS_B_READ || HAS_B_WRITE);
// Calculate the mux pipeline register stages for Port A and Port B
//------------------------------------------------------------------
localparam MUX_PIPELINE_STAGES_A = (C_HAS_MUX_OUTPUT_REGS_A) ?
C_MUX_PIPELINE_STAGES : 0;
localparam MUX_PIPELINE_STAGES_B = (C_HAS_MUX_OUTPUT_REGS_B) ?
C_MUX_PIPELINE_STAGES : 0;
// Calculate total number of register stages in the core
// -----------------------------------------------------
localparam NUM_OUTPUT_STAGES_A = (C_HAS_MEM_OUTPUT_REGS_A+MUX_PIPELINE_STAGES_A+C_HAS_MUX_OUTPUT_REGS_A);
localparam NUM_OUTPUT_STAGES_B = (C_HAS_MEM_OUTPUT_REGS_B+MUX_PIPELINE_STAGES_B+C_HAS_MUX_OUTPUT_REGS_B);
wire ena_i;
wire enb_i;
wire reseta_i;
wire resetb_i;
wire [C_WEA_WIDTH-1:0] wea_i;
wire [C_WEB_WIDTH-1:0] web_i;
wire rea_i;
wire reb_i;
wire rsta_outp_stage;
wire rstb_outp_stage;
// ECC SBITERR/DBITERR Outputs
// The ECC Behavior is modeled by the behavioral models only for Virtex-6.
// For Virtex-5, these outputs will be tied to 0.
assign SBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?sbiterr_sdp:0;
assign DBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?dbiterr_sdp:0;
assign RDADDRECC = (((C_FAMILY_LOCALPARAM == "virtex7") && C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?rdaddrecc_sdp:0;
// This effectively wires off optional inputs
assign ena_i = (C_HAS_ENA==0) || ENA;
assign enb_i = ((C_HAS_ENB==0) || ENB) && HAS_B_PORT;
assign wea_i = (HAS_A_WRITE && ena_i) ? WEA : 'b0;
assign web_i = (HAS_B_WRITE && enb_i) ? WEB : 'b0;
assign rea_i = (HAS_A_READ) ? ena_i : 'b0;
assign reb_i = (HAS_B_READ) ? enb_i : 'b0;
// These signals reset the memory latches
assign reseta_i =
((C_HAS_RSTA==1 && RSTA && NUM_OUTPUT_STAGES_A==0) ||
(C_HAS_RSTA==1 && RSTA && C_RSTRAM_A==1));
assign resetb_i =
((C_HAS_RSTB==1 && RSTB && NUM_OUTPUT_STAGES_B==0) ||
(C_HAS_RSTB==1 && RSTB && C_RSTRAM_B==1));
// Tasks to access the memory
//---------------------------
//**************
// write_a
//**************
task write_a
(input reg [C_ADDRA_WIDTH-1:0] addr,
input reg [C_WEA_WIDTH-1:0] byte_en,
input reg [C_WRITE_WIDTH_A-1:0] data,
input inj_sbiterr,
input inj_dbiterr);
reg [C_WRITE_WIDTH_A-1:0] current_contents;
reg [C_ADDRA_WIDTH-1:0] address;
integer i;
begin
// Shift the address by the ratio
address = (addr/WRITE_ADDR_A_DIV);
if (address >= C_WRITE_DEPTH_A) begin
if (!C_DISABLE_WARN_BHV_RANGE) begin
$fdisplay(ADDRFILE,
"%0s WARNING: Address %0h is outside range for A Write",
C_CORENAME, addr);
end
// valid address
end else begin
// Combine w/ byte writes
if (C_USE_BYTE_WEA) begin
// Get the current memory contents
if (WRITE_WIDTH_RATIO_A == 1) begin
// Workaround for IUS 5.5 part-select issue
current_contents = memory[address];
end else begin
for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin
current_contents[MIN_WIDTH*i+:MIN_WIDTH]
= memory[address*WRITE_WIDTH_RATIO_A + i];
end
end
// Apply incoming bytes
if (C_WEA_WIDTH == 1) begin
// Workaround for IUS 5.5 part-select issue
if (byte_en[0]) begin
current_contents = data;
end
end else begin
for (i = 0; i < C_WEA_WIDTH; i = i + 1) begin
if (byte_en[i]) begin
current_contents[BYTE_SIZE*i+:BYTE_SIZE]
= data[BYTE_SIZE*i+:BYTE_SIZE];
end
end
end
// No byte-writes, overwrite the whole word
end else begin
current_contents = data;
end
// Insert double bit errors:
if (C_USE_ECC == 1) begin
if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin
current_contents[0] = !(current_contents[0]);
current_contents[1] = !(current_contents[1]);
end
end
// Insert softecc double bit errors:
if (C_USE_SOFTECC == 1) begin
if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin
doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:2] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-3:0];
doublebit_error[0] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1];
doublebit_error[1] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-2];
current_contents = current_contents ^ doublebit_error[C_WRITE_WIDTH_A-1:0];
end
end
// Write data to memory
if (WRITE_WIDTH_RATIO_A == 1) begin
// Workaround for IUS 5.5 part-select issue
memory[address*WRITE_WIDTH_RATIO_A] = current_contents;
end else begin
for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin
memory[address*WRITE_WIDTH_RATIO_A + i]
= current_contents[MIN_WIDTH*i+:MIN_WIDTH];
end
end
// Store the address at which error is injected:
if ((C_FAMILY_LOCALPARAM == "virtex7") && C_USE_ECC == 1) begin
if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) ||
(C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))
begin
sbiterr_arr[addr] = 1;
end else begin
sbiterr_arr[addr] = 0;
end
if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin
dbiterr_arr[addr] = 1;
end else begin
dbiterr_arr[addr] = 0;
end
end
// Store the address at which softecc error is injected:
if (C_USE_SOFTECC == 1) begin
if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) ||
(C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))
begin
softecc_sbiterr_arr[addr] = 1;
end else begin
softecc_sbiterr_arr[addr] = 0;
end
if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin
softecc_dbiterr_arr[addr] = 1;
end else begin
softecc_dbiterr_arr[addr] = 0;
end
end
end
end
endtask
//**************
// write_b
//**************
task write_b
(input reg [C_ADDRB_WIDTH-1:0] addr,
input reg [C_WEB_WIDTH-1:0] byte_en,
input reg [C_WRITE_WIDTH_B-1:0] data);
reg [C_WRITE_WIDTH_B-1:0] current_contents;
reg [C_ADDRB_WIDTH-1:0] address;
integer i;
begin
// Shift the address by the ratio
address = (addr/WRITE_ADDR_B_DIV);
if (address >= C_WRITE_DEPTH_B) begin
if (!C_DISABLE_WARN_BHV_RANGE) begin
$fdisplay(ADDRFILE,
"%0s WARNING: Address %0h is outside range for B Write",
C_CORENAME, addr);
end
// valid address
end else begin
// Combine w/ byte writes
if (C_USE_BYTE_WEB) begin
// Get the current memory contents
if (WRITE_WIDTH_RATIO_B == 1) begin
// Workaround for IUS 5.5 part-select issue
current_contents = memory[address];
end else begin
for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin
current_contents[MIN_WIDTH*i+:MIN_WIDTH]
= memory[address*WRITE_WIDTH_RATIO_B + i];
end
end
// Apply incoming bytes
if (C_WEB_WIDTH == 1) begin
// Workaround for IUS 5.5 part-select issue
if (byte_en[0]) begin
current_contents = data;
end
end else begin
for (i = 0; i < C_WEB_WIDTH; i = i + 1) begin
if (byte_en[i]) begin
current_contents[BYTE_SIZE*i+:BYTE_SIZE]
= data[BYTE_SIZE*i+:BYTE_SIZE];
end
end
end
// No byte-writes, overwrite the whole word
end else begin
current_contents = data;
end
// Write data to memory
if (WRITE_WIDTH_RATIO_B == 1) begin
// Workaround for IUS 5.5 part-select issue
memory[address*WRITE_WIDTH_RATIO_B] = current_contents;
end else begin
for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin
memory[address*WRITE_WIDTH_RATIO_B + i]
= current_contents[MIN_WIDTH*i+:MIN_WIDTH];
end
end
end
end
endtask
//**************
// read_a
//**************
task read_a
(input reg [C_ADDRA_WIDTH-1:0] addr,
input reg reset);
reg [C_ADDRA_WIDTH-1:0] address;
integer i;
begin
if (reset) begin
memory_out_a <= #FLOP_DELAY inita_val;
end else begin
// Shift the address by the ratio
address = (addr/READ_ADDR_A_DIV);
if (address >= C_READ_DEPTH_A) begin
if (!C_DISABLE_WARN_BHV_RANGE) begin
$fdisplay(ADDRFILE,
"%0s WARNING: Address %0h is outside range for A Read",
C_CORENAME, addr);
end
memory_out_a <= #FLOP_DELAY 'bX;
// valid address
end else begin
if (READ_WIDTH_RATIO_A==1) begin
memory_out_a <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A];
end else begin
// Increment through the 'partial' words in the memory
for (i = 0; i < READ_WIDTH_RATIO_A; i = i + 1) begin
memory_out_a[MIN_WIDTH*i+:MIN_WIDTH]
<= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A + i];
end
end //end READ_WIDTH_RATIO_A==1 loop
end //end valid address loop
end //end reset-data assignment loops
end
endtask
//**************
// read_b
//**************
task read_b
(input reg [C_ADDRB_WIDTH-1:0] addr,
input reg reset);
reg [C_ADDRB_WIDTH-1:0] address;
integer i;
begin
if (reset) begin
memory_out_b <= #FLOP_DELAY initb_val;
sbiterr_in <= #FLOP_DELAY 1'b0;
dbiterr_in <= #FLOP_DELAY 1'b0;
rdaddrecc_in <= #FLOP_DELAY 0;
end else begin
// Shift the address
address = (addr/READ_ADDR_B_DIV);
if (address >= C_READ_DEPTH_B) begin
if (!C_DISABLE_WARN_BHV_RANGE) begin
$fdisplay(ADDRFILE,
"%0s WARNING: Address %0h is outside range for B Read",
C_CORENAME, addr);
end
memory_out_b <= #FLOP_DELAY 'bX;
sbiterr_in <= #FLOP_DELAY 1'bX;
dbiterr_in <= #FLOP_DELAY 1'bX;
rdaddrecc_in <= #FLOP_DELAY 'bX;
// valid address
end else begin
if (READ_WIDTH_RATIO_B==1) begin
memory_out_b <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B];
end else begin
// Increment through the 'partial' words in the memory
for (i = 0; i < READ_WIDTH_RATIO_B; i = i + 1) begin
memory_out_b[MIN_WIDTH*i+:MIN_WIDTH]
<= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B + i];
end
end
if ((C_FAMILY_LOCALPARAM == "virtex7") && C_USE_ECC == 1) begin
rdaddrecc_in <= #FLOP_DELAY addr;
if (sbiterr_arr[addr] == 1) begin
sbiterr_in <= #FLOP_DELAY 1'b1;
end else begin
sbiterr_in <= #FLOP_DELAY 1'b0;
end
if (dbiterr_arr[addr] == 1) begin
dbiterr_in <= #FLOP_DELAY 1'b1;
end else begin
dbiterr_in <= #FLOP_DELAY 1'b0;
end
end else if (C_USE_SOFTECC == 1) begin
rdaddrecc_in <= #FLOP_DELAY addr;
if (softecc_sbiterr_arr[addr] == 1) begin
sbiterr_in <= #FLOP_DELAY 1'b1;
end else begin
sbiterr_in <= #FLOP_DELAY 1'b0;
end
if (softecc_dbiterr_arr[addr] == 1) begin
dbiterr_in <= #FLOP_DELAY 1'b1;
end else begin
dbiterr_in <= #FLOP_DELAY 1'b0;
end
end else begin
rdaddrecc_in <= #FLOP_DELAY 0;
dbiterr_in <= #FLOP_DELAY 1'b0;
sbiterr_in <= #FLOP_DELAY 1'b0;
end //end SOFTECC Loop
end //end Valid address loop
end //end reset-data assignment loops
end
endtask
//**************
// reset_a
//**************
task reset_a (input reg reset);
begin
if (reset) memory_out_a <= #FLOP_DELAY inita_val;
end
endtask
//**************
// reset_b
//**************
task reset_b (input reg reset);
begin
if (reset) memory_out_b <= #FLOP_DELAY initb_val;
end
endtask
//**************
// init_memory
//**************
task init_memory;
integer i, j, addr_step;
integer status;
reg [C_WRITE_WIDTH_A-1:0] default_data;
begin
default_data = 0;
//Display output message indicating that the behavioral model is being
//initialized
if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) $display(" Block Memory Generator module loading initial data...");
// Convert the default to hex
if (C_USE_DEFAULT_DATA) begin
if (default_data_str == "") begin
$fdisplay(ERRFILE, "%0s ERROR: C_DEFAULT_DATA is empty!", C_CORENAME);
$finish;
end else begin
status = $sscanf(default_data_str, "%h", default_data);
if (status == 0) begin
$fdisplay(ERRFILE, {"%0s ERROR: Unsuccessful hexadecimal read",
"from C_DEFAULT_DATA: %0s"},
C_CORENAME, C_DEFAULT_DATA);
$finish;
end
end
end
// Step by WRITE_ADDR_A_DIV through the memory via the
// Port A write interface to hit every location once
addr_step = WRITE_ADDR_A_DIV;
// 'write' to every location with default (or 0)
for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin
write_a(i, {C_WEA_WIDTH{1'b1}}, default_data, 1'b0, 1'b0);
end
// Get specialized data from the MIF file
if (C_LOAD_INIT_FILE) begin
if (init_file_str == "") begin
$fdisplay(ERRFILE, "%0s ERROR: C_INIT_FILE_NAME is empty!",
C_CORENAME);
$finish;
end else begin
initfile = $fopen(init_file_str, "r");
if (initfile == 0) begin
$fdisplay(ERRFILE, {"%0s, ERROR: Problem opening",
"C_INIT_FILE_NAME: %0s!"},
C_CORENAME, init_file_str);
$finish;
end else begin
// loop through the mif file, loading in the data
for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin
status = $fscanf(initfile, "%b", mif_data);
if (status > 0) begin
write_a(i, {C_WEA_WIDTH{1'b1}}, mif_data, 1'b0, 1'b0);
end
end
$fclose(initfile);
end //initfile
end //init_file_str
end //C_LOAD_INIT_FILE
if (C_USE_BRAM_BLOCK) begin
// Get specialized data from the MIF file
if (C_INIT_FILE != "NONE") begin
if (mem_init_file_str == "") begin
$fdisplay(ERRFILE, "%0s ERROR: C_INIT_FILE is empty!",
C_CORENAME);
$finish;
end else begin
meminitfile = $fopen(mem_init_file_str, "r");
if (meminitfile == 0) begin
$fdisplay(ERRFILE, {"%0s, ERROR: Problem opening",
"C_INIT_FILE: %0s!"},
C_CORENAME, mem_init_file_str);
$finish;
end else begin
// loop through the mif file, loading in the data
$readmemh(mem_init_file_str, memory );
for (j = 0; j < MAX_DEPTH-1 ; j = j + 1) begin
end
$fclose(meminitfile);
end //meminitfile
end //mem_init_file_str
end //C_INIT_FILE
end //C_USE_BRAM_BLOCK
//Display output message indicating that the behavioral model is done
//initializing
if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE)
$display(" Block Memory Generator data initialization complete.");
end
endtask
//**************
// log2roundup
//**************
function integer log2roundup (input integer data_value);
integer width;
integer cnt;
begin
width = 0;
if (data_value > 1) begin
for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin
width = width + 1;
end //loop
end //if
log2roundup = width;
end //log2roundup
endfunction
//*******************
// collision_check
//*******************
function integer collision_check (input reg [C_ADDRA_WIDTH-1:0] addr_a,
input integer iswrite_a,
input reg [C_ADDRB_WIDTH-1:0] addr_b,
input integer iswrite_b);
reg c_aw_bw, c_aw_br, c_ar_bw;
integer scaled_addra_to_waddrb_width;
integer scaled_addrb_to_waddrb_width;
integer scaled_addra_to_waddra_width;
integer scaled_addrb_to_waddra_width;
integer scaled_addra_to_raddrb_width;
integer scaled_addrb_to_raddrb_width;
integer scaled_addra_to_raddra_width;
integer scaled_addrb_to_raddra_width;
begin
c_aw_bw = 0;
c_aw_br = 0;
c_ar_bw = 0;
//If write_addr_b_width is smaller, scale both addresses to that width for
//comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,
//scale it down to write_addr_b_width. addr_b starts as C_ADDRB_WIDTH,
//scale it down to write_addr_b_width. Once both are scaled to
//write_addr_b_width, compare.
scaled_addra_to_waddrb_width = ((addr_a)/
2**(C_ADDRA_WIDTH-write_addr_b_width));
scaled_addrb_to_waddrb_width = ((addr_b)/
2**(C_ADDRB_WIDTH-write_addr_b_width));
//If write_addr_a_width is smaller, scale both addresses to that width for
//comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,
//scale it down to write_addr_a_width. addr_b starts as C_ADDRB_WIDTH,
//scale it down to write_addr_a_width. Once both are scaled to
//write_addr_a_width, compare.
scaled_addra_to_waddra_width = ((addr_a)/
2**(C_ADDRA_WIDTH-write_addr_a_width));
scaled_addrb_to_waddra_width = ((addr_b)/
2**(C_ADDRB_WIDTH-write_addr_a_width));
//If read_addr_b_width is smaller, scale both addresses to that width for
//comparing write_addr_a and read_addr_b; addr_a starts as C_ADDRA_WIDTH,
//scale it down to read_addr_b_width. addr_b starts as C_ADDRB_WIDTH,
//scale it down to read_addr_b_width. Once both are scaled to
//read_addr_b_width, compare.
scaled_addra_to_raddrb_width = ((addr_a)/
2**(C_ADDRA_WIDTH-read_addr_b_width));
scaled_addrb_to_raddrb_width = ((addr_b)/
2**(C_ADDRB_WIDTH-read_addr_b_width));
//If read_addr_a_width is smaller, scale both addresses to that width for
//comparing read_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,
//scale it down to read_addr_a_width. addr_b starts as C_ADDRB_WIDTH,
//scale it down to read_addr_a_width. Once both are scaled to
//read_addr_a_width, compare.
scaled_addra_to_raddra_width = ((addr_a)/
2**(C_ADDRA_WIDTH-read_addr_a_width));
scaled_addrb_to_raddra_width = ((addr_b)/
2**(C_ADDRB_WIDTH-read_addr_a_width));
//Look for a write-write collision. In order for a write-write
//collision to exist, both ports must have a write transaction.
if (iswrite_a && iswrite_b) begin
if (write_addr_a_width > write_addr_b_width) begin
if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin
c_aw_bw = 1;
end else begin
c_aw_bw = 0;
end
end else begin
if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin
c_aw_bw = 1;
end else begin
c_aw_bw = 0;
end
end //width
end //iswrite_a and iswrite_b
//If the B port is reading (which means it is enabled - so could be
//a TX_WRITE or TX_READ), then check for a write-read collision).
//This could happen whether or not a write-write collision exists due
//to asymmetric write/read ports.
if (iswrite_a) begin
if (write_addr_a_width > read_addr_b_width) begin
if (scaled_addra_to_raddrb_width == scaled_addrb_to_raddrb_width) begin
c_aw_br = 1;
end else begin
c_aw_br = 0;
end
end else begin
if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin
c_aw_br = 1;
end else begin
c_aw_br = 0;
end
end //width
end //iswrite_a
//If the A port is reading (which means it is enabled - so could be
// a TX_WRITE or TX_READ), then check for a write-read collision).
//This could happen whether or not a write-write collision exists due
// to asymmetric write/read ports.
if (iswrite_b) begin
if (read_addr_a_width > write_addr_b_width) begin
if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin
c_ar_bw = 1;
end else begin
c_ar_bw = 0;
end
end else begin
if (scaled_addrb_to_raddra_width == scaled_addra_to_raddra_width) begin
c_ar_bw = 1;
end else begin
c_ar_bw = 0;
end
end //width
end //iswrite_b
collision_check = c_aw_bw | c_aw_br | c_ar_bw;
end
endfunction
//*******************************
// power on values
//*******************************
initial begin
// Load up the memory
init_memory;
// Load up the output registers and latches
if ($sscanf(inita_str, "%h", inita_val)) begin
memory_out_a = inita_val;
end else begin
memory_out_a = 0;
end
if ($sscanf(initb_str, "%h", initb_val)) begin
memory_out_b = initb_val;
end else begin
memory_out_b = 0;
end
sbiterr_in = 1'b0;
dbiterr_in = 1'b0;
rdaddrecc_in = 0;
// Determine the effective address widths for each of the 4 ports
write_addr_a_width = C_ADDRA_WIDTH - log2roundup(WRITE_ADDR_A_DIV);
read_addr_a_width = C_ADDRA_WIDTH - log2roundup(READ_ADDR_A_DIV);
write_addr_b_width = C_ADDRB_WIDTH - log2roundup(WRITE_ADDR_B_DIV);
read_addr_b_width = C_ADDRB_WIDTH - log2roundup(READ_ADDR_B_DIV);
$display("Block Memory Generator module %m is using a behavioral model for simulation which will not precisely model memory collision behavior.");
end
//***************************************************************************
// These are the main blocks which schedule read and write operations
// Note that the reset priority feature at the latch stage is only supported
// for Spartan-6. For other families, the default priority at the latch stage
// is "CE"
//***************************************************************************
// Synchronous clocks: schedule port operations with respect to
// both write operating modes
generate
if(C_COMMON_CLK && (C_WRITE_MODE_A == "WRITE_FIRST") && (C_WRITE_MODE_B ==
"WRITE_FIRST")) begin : com_clk_sched_wf_wf
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
end
end
else
if(C_COMMON_CLK && (C_WRITE_MODE_A == "READ_FIRST") && (C_WRITE_MODE_B ==
"WRITE_FIRST")) begin : com_clk_sched_rf_wf
always @(posedge CLKA) begin
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
end
end
else
if(C_COMMON_CLK && (C_WRITE_MODE_A == "WRITE_FIRST") && (C_WRITE_MODE_B ==
"READ_FIRST")) begin : com_clk_sched_wf_rf
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else
if(C_COMMON_CLK && (C_WRITE_MODE_A == "READ_FIRST") && (C_WRITE_MODE_B ==
"READ_FIRST")) begin : com_clk_sched_rf_rf
always @(posedge CLKA) begin
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="WRITE_FIRST") && (C_WRITE_MODE_B ==
"NO_CHANGE")) begin : com_clk_sched_wf_nc
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="READ_FIRST") && (C_WRITE_MODE_B ==
"NO_CHANGE")) begin : com_clk_sched_rf_nc
always @(posedge CLKA) begin
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B ==
"WRITE_FIRST")) begin : com_clk_sched_nc_wf
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read A
if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B ==
"READ_FIRST")) begin : com_clk_sched_nc_rf
always @(posedge CLKA) begin
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Read A
if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B ==
"NO_CHANGE")) begin : com_clk_sched_nc_nc
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read A
if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);
//Read B
if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);
end
end
else if(C_COMMON_CLK) begin: com_clk_sched_default
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
end
end
endgenerate
// Asynchronous clocks: port operation is independent
generate
if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "WRITE_FIRST")) begin : async_clk_sched_clka_wf
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
end
end
else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "READ_FIRST")) begin : async_clk_sched_clka_rf
always @(posedge CLKA) begin
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
end
end
else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "NO_CHANGE")) begin : async_clk_sched_clka_nc
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Read A
if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);
end
end
endgenerate
generate
if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "WRITE_FIRST")) begin: async_clk_sched_clkb_wf
always @(posedge CLKB) begin
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
end
end
else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "READ_FIRST")) begin: async_clk_sched_clkb_rf
always @(posedge CLKB) begin
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "NO_CHANGE")) begin: async_clk_sched_clkb_nc
always @(posedge CLKB) begin
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read B
if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);
end
end
endgenerate
//***************************************************************
// Instantiate the variable depth output register stage module
//***************************************************************
// Port A
assign rsta_outp_stage = RSTA & (~SLEEP);
BLK_MEM_GEN_v8_2_output_stage
#(.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_RST_TYPE ("SYNC"),
.C_HAS_RST (C_HAS_RSTA),
.C_RSTRAM (C_RSTRAM_A),
.C_RST_PRIORITY (C_RST_PRIORITY_A),
.C_INIT_VAL (C_INITA_VAL),
.C_HAS_EN (C_HAS_ENA),
.C_HAS_REGCE (C_HAS_REGCEA),
.C_DATA_WIDTH (C_READ_WIDTH_A),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_MEM_OUTPUT_REGS (C_HAS_MEM_OUTPUT_REGS_A),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.NUM_STAGES (NUM_OUTPUT_STAGES_A),
.C_EN_ECC_PIPE (0),
.FLOP_DELAY (FLOP_DELAY))
reg_a
(.CLK (CLKA),
.RST (rsta_outp_stage),//(RSTA),
.EN (ENA),
.REGCE (REGCEA),
.DIN_I (memory_out_a),
.DOUT (DOUTA),
.SBITERR_IN_I (1'b0),
.DBITERR_IN_I (1'b0),
.SBITERR (),
.DBITERR (),
.RDADDRECC_IN_I ({C_ADDRB_WIDTH{1'b0}}),
.ECCPIPECE (1'b0),
.RDADDRECC ()
);
assign rstb_outp_stage = RSTB & (~SLEEP);
// Port B
BLK_MEM_GEN_v8_2_output_stage
#(.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_RST_TYPE ("SYNC"),
.C_HAS_RST (C_HAS_RSTB),
.C_RSTRAM (C_RSTRAM_B),
.C_RST_PRIORITY (C_RST_PRIORITY_B),
.C_INIT_VAL (C_INITB_VAL),
.C_HAS_EN (C_HAS_ENB),
.C_HAS_REGCE (C_HAS_REGCEB),
.C_DATA_WIDTH (C_READ_WIDTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_MEM_OUTPUT_REGS (C_HAS_MEM_OUTPUT_REGS_B),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.NUM_STAGES (NUM_OUTPUT_STAGES_B),
.C_EN_ECC_PIPE (C_EN_ECC_PIPE),
.FLOP_DELAY (FLOP_DELAY))
reg_b
(.CLK (CLKB),
.RST (rstb_outp_stage),//(RSTB),
.EN (ENB),
.REGCE (REGCEB),
.DIN_I (memory_out_b),
.DOUT (dout_i),
.SBITERR_IN_I (sbiterr_in),
.DBITERR_IN_I (dbiterr_in),
.SBITERR (sbiterr_i),
.DBITERR (dbiterr_i),
.RDADDRECC_IN_I (rdaddrecc_in),
.ECCPIPECE (ECCPIPECE),
.RDADDRECC (rdaddrecc_i)
);
//***************************************************************
// Instantiate the Input and Output register stages
//***************************************************************
BLK_MEM_GEN_v8_2_softecc_output_reg_stage
#(.C_DATA_WIDTH (C_READ_WIDTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),
.C_USE_SOFTECC (C_USE_SOFTECC),
.FLOP_DELAY (FLOP_DELAY))
has_softecc_output_reg_stage
(.CLK (CLKB),
.DIN (dout_i),
.DOUT (DOUTB),
.SBITERR_IN (sbiterr_i),
.DBITERR_IN (dbiterr_i),
.SBITERR (sbiterr_sdp),
.DBITERR (dbiterr_sdp),
.RDADDRECC_IN (rdaddrecc_i),
.RDADDRECC (rdaddrecc_sdp)
);
//****************************************************
// Synchronous collision checks
//****************************************************
// CR 780544 : To make verilog model's collison warnings in consistant with
// vhdl model, the non-blocking assignments are replaced with blocking
// assignments.
generate if (!C_DISABLE_WARN_BHV_COLL && C_COMMON_CLK) begin : sync_coll
always @(posedge CLKA) begin
// Possible collision if both are enabled and the addresses match
if (ena_i && enb_i) begin
if (wea_i || web_i) begin
is_collision = collision_check(ADDRA, wea_i, ADDRB, web_i);
end else begin
is_collision = 0;
end
end else begin
is_collision = 0;
end
// If the write port is in READ_FIRST mode, there is no collision
if (C_WRITE_MODE_A=="READ_FIRST" && wea_i && !web_i) begin
is_collision = 0;
end
if (C_WRITE_MODE_B=="READ_FIRST" && web_i && !wea_i) begin
is_collision = 0;
end
// Only flag if one of the accesses is a write
if (is_collision && (wea_i || web_i)) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A %0s address: %0h, B %0s address: %0h\n",
wea_i ? "write" : "read", ADDRA,
web_i ? "write" : "read", ADDRB);
end
end
//****************************************************
// Asynchronous collision checks
//****************************************************
end else if (!C_DISABLE_WARN_BHV_COLL && !C_COMMON_CLK) begin : async_coll
// Delay A and B addresses in order to mimic setup/hold times
wire [C_ADDRA_WIDTH-1:0] #COLL_DELAY addra_delay = ADDRA;
wire [0:0] #COLL_DELAY wea_delay = wea_i;
wire #COLL_DELAY ena_delay = ena_i;
wire [C_ADDRB_WIDTH-1:0] #COLL_DELAY addrb_delay = ADDRB;
wire [0:0] #COLL_DELAY web_delay = web_i;
wire #COLL_DELAY enb_delay = enb_i;
// Do the checks w/rt A
always @(posedge CLKA) begin
// Possible collision if both are enabled and the addresses match
if (ena_i && enb_i) begin
if (wea_i || web_i) begin
is_collision_a = collision_check(ADDRA, wea_i, ADDRB, web_i);
end else begin
is_collision_a = 0;
end
end else begin
is_collision_a = 0;
end
if (ena_i && enb_delay) begin
if(wea_i || web_delay) begin
is_collision_delay_a = collision_check(ADDRA, wea_i, addrb_delay,
web_delay);
end else begin
is_collision_delay_a = 0;
end
end else begin
is_collision_delay_a = 0;
end
// Only flag if B access is a write
if (is_collision_a && web_i) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A %0s address: %0h, B write address: %0h\n",
wea_i ? "write" : "read", ADDRA, ADDRB);
end else if (is_collision_delay_a && web_delay) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A %0s address: %0h, B write address: %0h\n",
wea_i ? "write" : "read", ADDRA, addrb_delay);
end
end
// Do the checks w/rt B
always @(posedge CLKB) begin
// Possible collision if both are enabled and the addresses match
if (ena_i && enb_i) begin
if (wea_i || web_i) begin
is_collision_b = collision_check(ADDRA, wea_i, ADDRB, web_i);
end else begin
is_collision_b = 0;
end
end else begin
is_collision_b = 0;
end
if (ena_delay && enb_i) begin
if (wea_delay || web_i) begin
is_collision_delay_b = collision_check(addra_delay, wea_delay, ADDRB,
web_i);
end else begin
is_collision_delay_b = 0;
end
end else begin
is_collision_delay_b = 0;
end
// Only flag if A access is a write
if (is_collision_b && wea_i) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A write address: %0h, B %s address: %0h\n",
ADDRA, web_i ? "write" : "read", ADDRB);
end else if (is_collision_delay_b && wea_delay) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A write address: %0h, B %s address: %0h\n",
addra_delay, web_i ? "write" : "read", ADDRB);
end
end
end
endgenerate
endmodule
//*****************************************************************************
// Top module wraps Input register and Memory module
//
// This module is the top-level behavioral model and this implements the memory
// module and the input registers
//*****************************************************************************
module blk_mem_gen_v8_2
#(parameter C_CORENAME = "blk_mem_gen_v8_2",
parameter C_FAMILY = "virtex7",
parameter C_XDEVICEFAMILY = "virtex7",
parameter C_ELABORATION_DIR = "",
parameter C_INTERFACE_TYPE = 0,
parameter C_USE_BRAM_BLOCK = 0,
parameter C_CTRL_ECC_ALGO = "NONE",
parameter C_ENABLE_32BIT_ADDRESS = 0,
parameter C_AXI_TYPE = 0,
parameter C_AXI_SLAVE_TYPE = 0,
parameter C_HAS_AXI_ID = 0,
parameter C_AXI_ID_WIDTH = 4,
parameter C_MEM_TYPE = 2,
parameter C_BYTE_SIZE = 9,
parameter C_ALGORITHM = 1,
parameter C_PRIM_TYPE = 3,
parameter C_LOAD_INIT_FILE = 0,
parameter C_INIT_FILE_NAME = "",
parameter C_INIT_FILE = "",
parameter C_USE_DEFAULT_DATA = 0,
parameter C_DEFAULT_DATA = "0",
//parameter C_RST_TYPE = "SYNC",
parameter C_HAS_RSTA = 0,
parameter C_RST_PRIORITY_A = "CE",
parameter C_RSTRAM_A = 0,
parameter C_INITA_VAL = "0",
parameter C_HAS_ENA = 1,
parameter C_HAS_REGCEA = 0,
parameter C_USE_BYTE_WEA = 0,
parameter C_WEA_WIDTH = 1,
parameter C_WRITE_MODE_A = "WRITE_FIRST",
parameter C_WRITE_WIDTH_A = 32,
parameter C_READ_WIDTH_A = 32,
parameter C_WRITE_DEPTH_A = 64,
parameter C_READ_DEPTH_A = 64,
parameter C_ADDRA_WIDTH = 5,
parameter C_HAS_RSTB = 0,
parameter C_RST_PRIORITY_B = "CE",
parameter C_RSTRAM_B = 0,
parameter C_INITB_VAL = "",
parameter C_HAS_ENB = 1,
parameter C_HAS_REGCEB = 0,
parameter C_USE_BYTE_WEB = 0,
parameter C_WEB_WIDTH = 1,
parameter C_WRITE_MODE_B = "WRITE_FIRST",
parameter C_WRITE_WIDTH_B = 32,
parameter C_READ_WIDTH_B = 32,
parameter C_WRITE_DEPTH_B = 64,
parameter C_READ_DEPTH_B = 64,
parameter C_ADDRB_WIDTH = 5,
parameter C_HAS_MEM_OUTPUT_REGS_A = 0,
parameter C_HAS_MEM_OUTPUT_REGS_B = 0,
parameter C_HAS_MUX_OUTPUT_REGS_A = 0,
parameter C_HAS_MUX_OUTPUT_REGS_B = 0,
parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,
parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,
parameter C_MUX_PIPELINE_STAGES = 0,
parameter C_USE_SOFTECC = 0,
parameter C_USE_ECC = 0,
parameter C_EN_ECC_PIPE = 0,
parameter C_HAS_INJECTERR = 0,
parameter C_SIM_COLLISION_CHECK = "NONE",
parameter C_COMMON_CLK = 1,
parameter C_DISABLE_WARN_BHV_COLL = 0,
parameter C_EN_SLEEP_PIN = 0,
parameter C_DISABLE_WARN_BHV_RANGE = 0,
parameter C_COUNT_36K_BRAM = "",
parameter C_COUNT_18K_BRAM = "",
parameter C_EST_POWER_SUMMARY = ""
)
(input clka,
input rsta,
input ena,
input regcea,
input [C_WEA_WIDTH-1:0] wea,
input [C_ADDRA_WIDTH-1:0] addra,
input [C_WRITE_WIDTH_A-1:0] dina,
output [C_READ_WIDTH_A-1:0] douta,
input clkb,
input rstb,
input enb,
input regceb,
input [C_WEB_WIDTH-1:0] web,
input [C_ADDRB_WIDTH-1:0] addrb,
input [C_WRITE_WIDTH_B-1:0] dinb,
output [C_READ_WIDTH_B-1:0] doutb,
input injectsbiterr,
input injectdbiterr,
output sbiterr,
output dbiterr,
output [C_ADDRB_WIDTH-1:0] rdaddrecc,
input eccpipece,
input sleep,
//AXI BMG Input and Output Port Declarations
//AXI Global Signals
input s_aclk,
input s_aresetn,
//AXI Full/lite slave write (write side)
input [C_AXI_ID_WIDTH-1:0] s_axi_awid,
input [31:0] s_axi_awaddr,
input [7:0] s_axi_awlen,
input [2:0] s_axi_awsize,
input [1:0] s_axi_awburst,
input s_axi_awvalid,
output s_axi_awready,
input [C_WRITE_WIDTH_A-1:0] s_axi_wdata,
input [C_WEA_WIDTH-1:0] s_axi_wstrb,
input s_axi_wlast,
input s_axi_wvalid,
output s_axi_wready,
output [C_AXI_ID_WIDTH-1:0] s_axi_bid,
output [1:0] s_axi_bresp,
output s_axi_bvalid,
input s_axi_bready,
//AXI Full/lite slave read (write side)
input [C_AXI_ID_WIDTH-1:0] s_axi_arid,
input [31:0] s_axi_araddr,
input [7:0] s_axi_arlen,
input [2:0] s_axi_arsize,
input [1:0] s_axi_arburst,
input s_axi_arvalid,
output s_axi_arready,
output [C_AXI_ID_WIDTH-1:0] s_axi_rid,
output [C_WRITE_WIDTH_B-1:0] s_axi_rdata,
output [1:0] s_axi_rresp,
output s_axi_rlast,
output s_axi_rvalid,
input s_axi_rready,
//AXI Full/lite sideband signals
input s_axi_injectsbiterr,
input s_axi_injectdbiterr,
output s_axi_sbiterr,
output s_axi_dbiterr,
output [C_ADDRB_WIDTH-1:0] s_axi_rdaddrecc
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_CORENAME : Instance name of the Block Memory Generator core
// C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
// options are available - "spartan3", "spartan6",
// "virtex4", "virtex5", "virtex6" and "virtex6l".
// C_MEM_TYPE : Designates memory type.
// It can be
// 0 - Single Port Memory
// 1 - Simple Dual Port Memory
// 2 - True Dual Port Memory
// 3 - Single Port Read Only Memory
// 4 - Dual Port Read Only Memory
// C_BYTE_SIZE : Size of a byte (8 or 9 bits)
// C_ALGORITHM : Designates the algorithm method used
// for constructing the memory.
// It can be Fixed_Primitives, Minimum_Area or
// Low_Power
// C_PRIM_TYPE : Designates the user selected primitive used to
// construct the memory.
//
// C_LOAD_INIT_FILE : Designates the use of an initialization file to
// initialize memory contents.
// C_INIT_FILE_NAME : Memory initialization file name.
// C_USE_DEFAULT_DATA : Designates whether to fill remaining
// initialization space with default data
// C_DEFAULT_DATA : Default value of all memory locations
// not initialized by the memory
// initialization file.
// C_RST_TYPE : Type of reset - Synchronous or Asynchronous
// C_HAS_RSTA : Determines the presence of the RSTA port
// C_RST_PRIORITY_A : Determines the priority between CE and SR for
// Port A.
// C_RSTRAM_A : Determines if special reset behavior is used for
// Port A
// C_INITA_VAL : The initialization value for Port A
// C_HAS_ENA : Determines the presence of the ENA port
// C_HAS_REGCEA : Determines the presence of the REGCEA port
// C_USE_BYTE_WEA : Determines if the Byte Write is used or not.
// C_WEA_WIDTH : The width of the WEA port
// C_WRITE_MODE_A : Configurable write mode for Port A. It can be
// WRITE_FIRST, READ_FIRST or NO_CHANGE.
// C_WRITE_WIDTH_A : Memory write width for Port A.
// C_READ_WIDTH_A : Memory read width for Port A.
// C_WRITE_DEPTH_A : Memory write depth for Port A.
// C_READ_DEPTH_A : Memory read depth for Port A.
// C_ADDRA_WIDTH : Width of the ADDRA input port
// C_HAS_RSTB : Determines the presence of the RSTB port
// C_RST_PRIORITY_B : Determines the priority between CE and SR for
// Port B.
// C_RSTRAM_B : Determines if special reset behavior is used for
// Port B
// C_INITB_VAL : The initialization value for Port B
// C_HAS_ENB : Determines the presence of the ENB port
// C_HAS_REGCEB : Determines the presence of the REGCEB port
// C_USE_BYTE_WEB : Determines if the Byte Write is used or not.
// C_WEB_WIDTH : The width of the WEB port
// C_WRITE_MODE_B : Configurable write mode for Port B. It can be
// WRITE_FIRST, READ_FIRST or NO_CHANGE.
// C_WRITE_WIDTH_B : Memory write width for Port B.
// C_READ_WIDTH_B : Memory read width for Port B.
// C_WRITE_DEPTH_B : Memory write depth for Port B.
// C_READ_DEPTH_B : Memory read depth for Port B.
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output
// of the RAM primitive for Port A.
// C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output
// of the RAM primitive for Port B.
// C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
// of the MUX for Port A.
// C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
// of the MUX for Port B.
// C_HAS_SOFTECC_INPUT_REGS_A :
// C_HAS_SOFTECC_OUTPUT_REGS_B :
// C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in
// between the muxes.
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// C_USE_ECC : Determines if the ECC feature is used or
// not. Only applicable for V5 and V6
// C_HAS_INJECTERR : Determines if the error injection pins
// are present or not. If the ECC feature
// is not used, this value is defaulted to
// 0, else the following are the allowed
// values:
// 0 : No INJECTSBITERR or INJECTDBITERR pins
// 1 : Only INJECTSBITERR pin exists
// 2 : Only INJECTDBITERR pin exists
// 3 : Both INJECTSBITERR and INJECTDBITERR pins exist
// C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision
// warnings. It can be "ALL", "NONE",
// "Warnings_Only" or "Generate_X_Only".
// C_COMMON_CLK : Determins if the core has a single CLK input.
// C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
// C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range
// warnings
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLKA : Clock to synchronize all read and write operations of Port A.
// RSTA : Reset input to reset memory outputs to a user-defined
// reset state for Port A.
// ENA : Enable all read and write operations of Port A.
// REGCEA : Register Clock Enable to control each pipeline output
// register stages for Port A.
// WEA : Write Enable to enable all write operations of Port A.
// ADDRA : Address of Port A.
// DINA : Data input of Port A.
// DOUTA : Data output of Port A.
// CLKB : Clock to synchronize all read and write operations of Port B.
// RSTB : Reset input to reset memory outputs to a user-defined
// reset state for Port B.
// ENB : Enable all read and write operations of Port B.
// REGCEB : Register Clock Enable to control each pipeline output
// register stages for Port B.
// WEB : Write Enable to enable all write operations of Port B.
// ADDRB : Address of Port B.
// DINB : Data input of Port B.
// DOUTB : Data output of Port B.
// INJECTSBITERR : Single Bit ECC Error Injection Pin.
// INJECTDBITERR : Double Bit ECC Error Injection Pin.
// SBITERR : Output signal indicating that a Single Bit ECC Error has been
// detected and corrected.
// DBITERR : Output signal indicating that a Double Bit ECC Error has been
// detected.
// RDADDRECC : Read Address Output signal indicating address at which an
// ECC error has occurred.
//////////////////////////////////////////////////////////////////////////
wire SBITERR;
wire DBITERR;
wire S_AXI_AWREADY;
wire S_AXI_WREADY;
wire S_AXI_BVALID;
wire S_AXI_ARREADY;
wire S_AXI_RLAST;
wire S_AXI_RVALID;
wire S_AXI_SBITERR;
wire S_AXI_DBITERR;
wire [C_WEA_WIDTH-1:0] WEA = wea;
wire [C_ADDRA_WIDTH-1:0] ADDRA = addra;
wire [C_WRITE_WIDTH_A-1:0] DINA = dina;
wire [C_READ_WIDTH_A-1:0] DOUTA;
wire [C_WEB_WIDTH-1:0] WEB = web;
wire [C_ADDRB_WIDTH-1:0] ADDRB = addrb;
wire [C_WRITE_WIDTH_B-1:0] DINB = dinb;
wire [C_READ_WIDTH_B-1:0] DOUTB;
wire [C_ADDRB_WIDTH-1:0] RDADDRECC;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID = s_axi_awid;
wire [31:0] S_AXI_AWADDR = s_axi_awaddr;
wire [7:0] S_AXI_AWLEN = s_axi_awlen;
wire [2:0] S_AXI_AWSIZE = s_axi_awsize;
wire [1:0] S_AXI_AWBURST = s_axi_awburst;
wire [C_WRITE_WIDTH_A-1:0] S_AXI_WDATA = s_axi_wdata;
wire [C_WEA_WIDTH-1:0] S_AXI_WSTRB = s_axi_wstrb;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID;
wire [1:0] S_AXI_BRESP;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID = s_axi_arid;
wire [31:0] S_AXI_ARADDR = s_axi_araddr;
wire [7:0] S_AXI_ARLEN = s_axi_arlen;
wire [2:0] S_AXI_ARSIZE = s_axi_arsize;
wire [1:0] S_AXI_ARBURST = s_axi_arburst;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID;
wire [C_WRITE_WIDTH_B-1:0] S_AXI_RDATA;
wire [1:0] S_AXI_RRESP;
wire [C_ADDRB_WIDTH-1:0] S_AXI_RDADDRECC;
// Added to fix the simulation warning #CR731605
wire [C_WEB_WIDTH-1:0] WEB_parameterized = 0;
wire ECCPIPECE;
wire SLEEP;
assign CLKA = clka;
assign RSTA = rsta;
assign ENA = ena;
assign REGCEA = regcea;
assign CLKB = clkb;
assign RSTB = rstb;
assign ENB = enb;
assign REGCEB = regceb;
assign INJECTSBITERR = injectsbiterr;
assign INJECTDBITERR = injectdbiterr;
assign ECCPIPECE = eccpipece;
assign SLEEP = sleep;
assign sbiterr = SBITERR;
assign dbiterr = DBITERR;
assign S_ACLK = s_aclk;
assign S_ARESETN = s_aresetn;
assign S_AXI_AWVALID = s_axi_awvalid;
assign s_axi_awready = S_AXI_AWREADY;
assign S_AXI_WLAST = s_axi_wlast;
assign S_AXI_WVALID = s_axi_wvalid;
assign s_axi_wready = S_AXI_WREADY;
assign s_axi_bvalid = S_AXI_BVALID;
assign S_AXI_BREADY = s_axi_bready;
assign S_AXI_ARVALID = s_axi_arvalid;
assign s_axi_arready = S_AXI_ARREADY;
assign s_axi_rlast = S_AXI_RLAST;
assign s_axi_rvalid = S_AXI_RVALID;
assign S_AXI_RREADY = s_axi_rready;
assign S_AXI_INJECTSBITERR = s_axi_injectsbiterr;
assign S_AXI_INJECTDBITERR = s_axi_injectdbiterr;
assign s_axi_sbiterr = S_AXI_SBITERR;
assign s_axi_dbiterr = S_AXI_DBITERR;
assign doutb = DOUTB;
assign douta = DOUTA;
assign rdaddrecc = RDADDRECC;
assign s_axi_bid = S_AXI_BID;
assign s_axi_bresp = S_AXI_BRESP;
assign s_axi_rid = S_AXI_RID;
assign s_axi_rdata = S_AXI_RDATA;
assign s_axi_rresp = S_AXI_RRESP;
assign s_axi_rdaddrecc = S_AXI_RDADDRECC;
localparam FLOP_DELAY = 100; // 100 ps
reg injectsbiterr_in;
reg injectdbiterr_in;
reg rsta_in;
reg ena_in;
reg regcea_in;
reg [C_WEA_WIDTH-1:0] wea_in;
reg [C_ADDRA_WIDTH-1:0] addra_in;
reg [C_WRITE_WIDTH_A-1:0] dina_in;
wire [C_ADDRA_WIDTH-1:0] s_axi_awaddr_out_c;
wire [C_ADDRB_WIDTH-1:0] s_axi_araddr_out_c;
wire s_axi_wr_en_c;
wire s_axi_rd_en_c;
wire s_aresetn_a_c;
wire [7:0] s_axi_arlen_c ;
wire [C_AXI_ID_WIDTH-1 : 0] s_axi_rid_c;
wire [C_WRITE_WIDTH_B-1 : 0] s_axi_rdata_c;
wire [1:0] s_axi_rresp_c;
wire s_axi_rlast_c;
wire s_axi_rvalid_c;
wire s_axi_rready_c;
wire regceb_c;
localparam C_AXI_PAYLOAD = (C_HAS_MUX_OUTPUT_REGS_B == 1)?C_WRITE_WIDTH_B+C_AXI_ID_WIDTH+3:C_AXI_ID_WIDTH+3;
wire [C_AXI_PAYLOAD-1 : 0] s_axi_payload_c;
wire [C_AXI_PAYLOAD-1 : 0] m_axi_payload_c;
//**************
// log2roundup
//**************
function integer log2roundup (input integer data_value);
integer width;
integer cnt;
begin
width = 0;
if (data_value > 1) begin
for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin
width = width + 1;
end //loop
end //if
log2roundup = width;
end //log2roundup
endfunction
//**************
// log2int
//**************
function integer log2int (input integer data_value);
integer width;
integer cnt;
begin
width = 0;
cnt= data_value;
for(cnt=data_value ; cnt >1 ; cnt = cnt / 2) begin
width = width + 1;
end //loop
log2int = width;
end //log2int
endfunction
//**************************************************************************
// FUNCTION : divroundup
// Returns the ceiling value of the division
// Data_value - the quantity to be divided, dividend
// Divisor - the value to divide the data_value by
//**************************************************************************
function integer divroundup (input integer data_value,input integer divisor);
integer div;
begin
div = data_value/divisor;
if ((data_value % divisor) != 0) begin
div = div+1;
end //if
divroundup = div;
end //if
endfunction
localparam AXI_FULL_MEMORY_SLAVE = ((C_AXI_SLAVE_TYPE == 0 && C_AXI_TYPE == 1)?1:0);
localparam C_AXI_ADDR_WIDTH_MSB = C_ADDRA_WIDTH+log2roundup(C_WRITE_WIDTH_A/8);
localparam C_AXI_ADDR_WIDTH = C_AXI_ADDR_WIDTH_MSB;
//Data Width Number of LSB address bits to be discarded
//1 to 16 1
//17 to 32 2
//33 to 64 3
//65 to 128 4
//129 to 256 5
//257 to 512 6
//513 to 1024 7
// The following two constants determine this.
localparam LOWER_BOUND_VAL = (log2roundup(divroundup(C_WRITE_WIDTH_A,8) == 0))?0:(log2roundup(divroundup(C_WRITE_WIDTH_A,8)));
localparam C_AXI_ADDR_WIDTH_LSB = ((AXI_FULL_MEMORY_SLAVE == 1)?0:LOWER_BOUND_VAL);
localparam C_AXI_OS_WR = 2;
//***********************************************
// INPUT REGISTERS.
//***********************************************
generate if (C_HAS_SOFTECC_INPUT_REGS_A==0) begin : no_softecc_input_reg_stage
always @* begin
injectsbiterr_in = INJECTSBITERR;
injectdbiterr_in = INJECTDBITERR;
rsta_in = RSTA;
ena_in = ENA;
regcea_in = REGCEA;
wea_in = WEA;
addra_in = ADDRA;
dina_in = DINA;
end //end always
end //end no_softecc_input_reg_stage
endgenerate
generate if (C_HAS_SOFTECC_INPUT_REGS_A==1) begin : has_softecc_input_reg_stage
always @(posedge CLKA) begin
injectsbiterr_in <= #FLOP_DELAY INJECTSBITERR;
injectdbiterr_in <= #FLOP_DELAY INJECTDBITERR;
rsta_in <= #FLOP_DELAY RSTA;
ena_in <= #FLOP_DELAY ENA;
regcea_in <= #FLOP_DELAY REGCEA;
wea_in <= #FLOP_DELAY WEA;
addra_in <= #FLOP_DELAY ADDRA;
dina_in <= #FLOP_DELAY DINA;
end //end always
end //end input_reg_stages generate statement
endgenerate
generate if ((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 0)) begin : native_mem_module
BLK_MEM_GEN_v8_2_mem_module
#(.C_CORENAME (C_CORENAME),
.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_MEM_TYPE (C_MEM_TYPE),
.C_BYTE_SIZE (C_BYTE_SIZE),
.C_ALGORITHM (C_ALGORITHM),
.C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK),
.C_PRIM_TYPE (C_PRIM_TYPE),
.C_LOAD_INIT_FILE (C_LOAD_INIT_FILE),
.C_INIT_FILE_NAME (C_INIT_FILE_NAME),
.C_INIT_FILE (C_INIT_FILE),
.C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA),
.C_DEFAULT_DATA (C_DEFAULT_DATA),
.C_RST_TYPE ("SYNC"),
.C_HAS_RSTA (C_HAS_RSTA),
.C_RST_PRIORITY_A (C_RST_PRIORITY_A),
.C_RSTRAM_A (C_RSTRAM_A),
.C_INITA_VAL (C_INITA_VAL),
.C_HAS_ENA (C_HAS_ENA),
.C_HAS_REGCEA (C_HAS_REGCEA),
.C_USE_BYTE_WEA (C_USE_BYTE_WEA),
.C_WEA_WIDTH (C_WEA_WIDTH),
.C_WRITE_MODE_A (C_WRITE_MODE_A),
.C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),
.C_READ_WIDTH_A (C_READ_WIDTH_A),
.C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),
.C_READ_DEPTH_A (C_READ_DEPTH_A),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH),
.C_HAS_RSTB (C_HAS_RSTB),
.C_RST_PRIORITY_B (C_RST_PRIORITY_B),
.C_RSTRAM_B (C_RSTRAM_B),
.C_INITB_VAL (C_INITB_VAL),
.C_HAS_ENB (C_HAS_ENB),
.C_HAS_REGCEB (C_HAS_REGCEB),
.C_USE_BYTE_WEB (C_USE_BYTE_WEB),
.C_WEB_WIDTH (C_WEB_WIDTH),
.C_WRITE_MODE_B (C_WRITE_MODE_B),
.C_WRITE_WIDTH_B (C_WRITE_WIDTH_B),
.C_READ_WIDTH_B (C_READ_WIDTH_B),
.C_WRITE_DEPTH_B (C_WRITE_DEPTH_B),
.C_READ_DEPTH_B (C_READ_DEPTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_MEM_OUTPUT_REGS_A (C_HAS_MEM_OUTPUT_REGS_A),
.C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B),
.C_HAS_MUX_OUTPUT_REGS_A (C_HAS_MUX_OUTPUT_REGS_A),
.C_HAS_MUX_OUTPUT_REGS_B (C_HAS_MUX_OUTPUT_REGS_B),
.C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A),
.C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),
.C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.C_HAS_INJECTERR (C_HAS_INJECTERR),
.C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK),
.C_COMMON_CLK (C_COMMON_CLK),
.FLOP_DELAY (FLOP_DELAY),
.C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL),
.C_EN_ECC_PIPE (C_EN_ECC_PIPE),
.C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE))
blk_mem_gen_v8_2_inst
(.CLKA (CLKA),
.RSTA (rsta_in),
.ENA (ena_in),
.REGCEA (regcea_in),
.WEA (wea_in),
.ADDRA (addra_in),
.DINA (dina_in),
.DOUTA (DOUTA),
.CLKB (CLKB),
.RSTB (RSTB),
.ENB (ENB),
.REGCEB (REGCEB),
.WEB (WEB),
.ADDRB (ADDRB),
.DINB (DINB),
.DOUTB (DOUTB),
.INJECTSBITERR (injectsbiterr_in),
.INJECTDBITERR (injectdbiterr_in),
.ECCPIPECE (ECCPIPECE),
.SLEEP (SLEEP),
.SBITERR (SBITERR),
.DBITERR (DBITERR),
.RDADDRECC (RDADDRECC)
);
end
endgenerate
generate if((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 1)) begin : native_mem_mapped_module
localparam C_ADDRA_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_A);
localparam C_ADDRB_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_B);
localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_A/8);
localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_B/8);
// localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_A/8);
// localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_B/8);
localparam C_MEM_MAP_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_MSB;
localparam C_MEM_MAP_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_MSB;
// Data Width Number of LSB address bits to be discarded
// 1 to 16 1
// 17 to 32 2
// 33 to 64 3
// 65 to 128 4
// 129 to 256 5
// 257 to 512 6
// 513 to 1024 7
// The following two constants determine this.
localparam MEM_MAP_LOWER_BOUND_VAL_A = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8)));
localparam MEM_MAP_LOWER_BOUND_VAL_B = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8)));
localparam C_MEM_MAP_ADDRA_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_A;
localparam C_MEM_MAP_ADDRB_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_B;
wire [C_ADDRB_WIDTH_ACTUAL-1 :0] rdaddrecc_i;
wire [C_ADDRB_WIDTH-1:C_MEM_MAP_ADDRB_WIDTH_MSB] msb_zero_i;
wire [C_MEM_MAP_ADDRB_WIDTH_LSB-1:0] lsb_zero_i;
assign msb_zero_i = 0;
assign lsb_zero_i = 0;
assign RDADDRECC = {msb_zero_i,rdaddrecc_i,lsb_zero_i};
BLK_MEM_GEN_v8_2_mem_module
#(.C_CORENAME (C_CORENAME),
.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_MEM_TYPE (C_MEM_TYPE),
.C_BYTE_SIZE (C_BYTE_SIZE),
.C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK),
.C_ALGORITHM (C_ALGORITHM),
.C_PRIM_TYPE (C_PRIM_TYPE),
.C_LOAD_INIT_FILE (C_LOAD_INIT_FILE),
.C_INIT_FILE_NAME (C_INIT_FILE_NAME),
.C_INIT_FILE (C_INIT_FILE),
.C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA),
.C_DEFAULT_DATA (C_DEFAULT_DATA),
.C_RST_TYPE ("SYNC"),
.C_HAS_RSTA (C_HAS_RSTA),
.C_RST_PRIORITY_A (C_RST_PRIORITY_A),
.C_RSTRAM_A (C_RSTRAM_A),
.C_INITA_VAL (C_INITA_VAL),
.C_HAS_ENA (C_HAS_ENA),
.C_HAS_REGCEA (C_HAS_REGCEA),
.C_USE_BYTE_WEA (C_USE_BYTE_WEA),
.C_WEA_WIDTH (C_WEA_WIDTH),
.C_WRITE_MODE_A (C_WRITE_MODE_A),
.C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),
.C_READ_WIDTH_A (C_READ_WIDTH_A),
.C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),
.C_READ_DEPTH_A (C_READ_DEPTH_A),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH_ACTUAL),
.C_HAS_RSTB (C_HAS_RSTB),
.C_RST_PRIORITY_B (C_RST_PRIORITY_B),
.C_RSTRAM_B (C_RSTRAM_B),
.C_INITB_VAL (C_INITB_VAL),
.C_HAS_ENB (C_HAS_ENB),
.C_HAS_REGCEB (C_HAS_REGCEB),
.C_USE_BYTE_WEB (C_USE_BYTE_WEB),
.C_WEB_WIDTH (C_WEB_WIDTH),
.C_WRITE_MODE_B (C_WRITE_MODE_B),
.C_WRITE_WIDTH_B (C_WRITE_WIDTH_B),
.C_READ_WIDTH_B (C_READ_WIDTH_B),
.C_WRITE_DEPTH_B (C_WRITE_DEPTH_B),
.C_READ_DEPTH_B (C_READ_DEPTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH_ACTUAL),
.C_HAS_MEM_OUTPUT_REGS_A (C_HAS_MEM_OUTPUT_REGS_A),
.C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B),
.C_HAS_MUX_OUTPUT_REGS_A (C_HAS_MUX_OUTPUT_REGS_A),
.C_HAS_MUX_OUTPUT_REGS_B (C_HAS_MUX_OUTPUT_REGS_B),
.C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A),
.C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),
.C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.C_HAS_INJECTERR (C_HAS_INJECTERR),
.C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK),
.C_COMMON_CLK (C_COMMON_CLK),
.FLOP_DELAY (FLOP_DELAY),
.C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL),
.C_EN_ECC_PIPE (C_EN_ECC_PIPE),
.C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE))
blk_mem_gen_v8_2_inst
(.CLKA (CLKA),
.RSTA (rsta_in),
.ENA (ena_in),
.REGCEA (regcea_in),
.WEA (wea_in),
.ADDRA (addra_in[C_MEM_MAP_ADDRA_WIDTH_MSB-1:C_MEM_MAP_ADDRA_WIDTH_LSB]),
.DINA (dina_in),
.DOUTA (DOUTA),
.CLKB (CLKB),
.RSTB (RSTB),
.ENB (ENB),
.REGCEB (REGCEB),
.WEB (WEB),
.ADDRB (ADDRB[C_MEM_MAP_ADDRB_WIDTH_MSB-1:C_MEM_MAP_ADDRB_WIDTH_LSB]),
.DINB (DINB),
.DOUTB (DOUTB),
.INJECTSBITERR (injectsbiterr_in),
.INJECTDBITERR (injectdbiterr_in),
.ECCPIPECE (ECCPIPECE),
.SLEEP (SLEEP),
.SBITERR (SBITERR),
.DBITERR (DBITERR),
.RDADDRECC (rdaddrecc_i)
);
end
endgenerate
generate if (C_HAS_MEM_OUTPUT_REGS_B == 0 && C_HAS_MUX_OUTPUT_REGS_B == 0 ) begin : no_regs
assign S_AXI_RDATA = s_axi_rdata_c;
assign S_AXI_RLAST = s_axi_rlast_c;
assign S_AXI_RVALID = s_axi_rvalid_c;
assign S_AXI_RID = s_axi_rid_c;
assign S_AXI_RRESP = s_axi_rresp_c;
assign s_axi_rready_c = S_AXI_RREADY;
end
endgenerate
generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regceb
assign regceb_c = s_axi_rvalid_c && s_axi_rready_c;
end
endgenerate
generate if (C_HAS_MEM_OUTPUT_REGS_B == 0) begin : no_regceb
assign regceb_c = REGCEB;
end
endgenerate
generate if (C_HAS_MUX_OUTPUT_REGS_B == 1) begin : only_core_op_regs
assign s_axi_payload_c = {s_axi_rid_c,s_axi_rdata_c,s_axi_rresp_c,s_axi_rlast_c};
assign S_AXI_RID = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];
assign S_AXI_RDATA = m_axi_payload_c[C_AXI_PAYLOAD-C_AXI_ID_WIDTH-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH-C_WRITE_WIDTH_B];
assign S_AXI_RRESP = m_axi_payload_c[2:1];
assign S_AXI_RLAST = m_axi_payload_c[0];
end
endgenerate
generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : only_emb_op_regs
assign s_axi_payload_c = {s_axi_rid_c,s_axi_rresp_c,s_axi_rlast_c};
assign S_AXI_RDATA = s_axi_rdata_c;
assign S_AXI_RID = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];
assign S_AXI_RRESP = m_axi_payload_c[2:1];
assign S_AXI_RLAST = m_axi_payload_c[0];
end
endgenerate
generate if (C_HAS_MUX_OUTPUT_REGS_B == 1 || C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regs_fwd
blk_mem_axi_regs_fwd_v8_2
#(.C_DATA_WIDTH (C_AXI_PAYLOAD))
axi_regs_inst (
.ACLK (S_ACLK),
.ARESET (s_aresetn_a_c),
.S_VALID (s_axi_rvalid_c),
.S_READY (s_axi_rready_c),
.S_PAYLOAD_DATA (s_axi_payload_c),
.M_VALID (S_AXI_RVALID),
.M_READY (S_AXI_RREADY),
.M_PAYLOAD_DATA (m_axi_payload_c)
);
end
endgenerate
generate if (C_INTERFACE_TYPE == 1) begin : axi_mem_module
assign s_aresetn_a_c = !S_ARESETN;
assign S_AXI_BRESP = 2'b00;
assign s_axi_rresp_c = 2'b00;
assign s_axi_arlen_c = (C_AXI_TYPE == 1)?S_AXI_ARLEN:8'h0;
blk_mem_axi_write_wrapper_beh_v8_2
#(.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_AXI_TYPE (C_AXI_TYPE),
.C_AXI_SLAVE_TYPE (C_AXI_SLAVE_TYPE),
.C_MEMORY_TYPE (C_MEM_TYPE),
.C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),
.C_AXI_AWADDR_WIDTH ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
.C_HAS_AXI_ID (C_HAS_AXI_ID),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH),
.C_AXI_WDATA_WIDTH (C_WRITE_WIDTH_A),
.C_AXI_OS_WR (C_AXI_OS_WR))
axi_wr_fsm (
// AXI Global Signals
.S_ACLK (S_ACLK),
.S_ARESETN (s_aresetn_a_c),
// AXI Full/Lite Slave Write interface
.S_AXI_AWADDR (S_AXI_AWADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),
.S_AXI_AWLEN (S_AXI_AWLEN),
.S_AXI_AWID (S_AXI_AWID),
.S_AXI_AWSIZE (S_AXI_AWSIZE),
.S_AXI_AWBURST (S_AXI_AWBURST),
.S_AXI_AWVALID (S_AXI_AWVALID),
.S_AXI_AWREADY (S_AXI_AWREADY),
.S_AXI_WVALID (S_AXI_WVALID),
.S_AXI_WREADY (S_AXI_WREADY),
.S_AXI_BVALID (S_AXI_BVALID),
.S_AXI_BREADY (S_AXI_BREADY),
.S_AXI_BID (S_AXI_BID),
// Signals for BRAM interfac(
.S_AXI_AWADDR_OUT (s_axi_awaddr_out_c),
.S_AXI_WR_EN (s_axi_wr_en_c)
);
blk_mem_axi_read_wrapper_beh_v8_2
#(.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_AXI_TYPE (C_AXI_TYPE),
.C_AXI_SLAVE_TYPE (C_AXI_SLAVE_TYPE),
.C_MEMORY_TYPE (C_MEM_TYPE),
.C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH),
.C_AXI_PIPELINE_STAGES (1),
.C_AXI_ARADDR_WIDTH ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
.C_HAS_AXI_ID (C_HAS_AXI_ID),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH))
axi_rd_sm(
//AXI Global Signals
.S_ACLK (S_ACLK),
.S_ARESETN (s_aresetn_a_c),
//AXI Full/Lite Read Side
.S_AXI_ARADDR (S_AXI_ARADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),
.S_AXI_ARLEN (s_axi_arlen_c),
.S_AXI_ARSIZE (S_AXI_ARSIZE),
.S_AXI_ARBURST (S_AXI_ARBURST),
.S_AXI_ARVALID (S_AXI_ARVALID),
.S_AXI_ARREADY (S_AXI_ARREADY),
.S_AXI_RLAST (s_axi_rlast_c),
.S_AXI_RVALID (s_axi_rvalid_c),
.S_AXI_RREADY (s_axi_rready_c),
.S_AXI_ARID (S_AXI_ARID),
.S_AXI_RID (s_axi_rid_c),
//AXI Full/Lite Read FSM Outputs
.S_AXI_ARADDR_OUT (s_axi_araddr_out_c),
.S_AXI_RD_EN (s_axi_rd_en_c)
);
BLK_MEM_GEN_v8_2_mem_module
#(.C_CORENAME (C_CORENAME),
.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_MEM_TYPE (C_MEM_TYPE),
.C_BYTE_SIZE (C_BYTE_SIZE),
.C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK),
.C_ALGORITHM (C_ALGORITHM),
.C_PRIM_TYPE (C_PRIM_TYPE),
.C_LOAD_INIT_FILE (C_LOAD_INIT_FILE),
.C_INIT_FILE_NAME (C_INIT_FILE_NAME),
.C_INIT_FILE (C_INIT_FILE),
.C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA),
.C_DEFAULT_DATA (C_DEFAULT_DATA),
.C_RST_TYPE ("SYNC"),
.C_HAS_RSTA (C_HAS_RSTA),
.C_RST_PRIORITY_A (C_RST_PRIORITY_A),
.C_RSTRAM_A (C_RSTRAM_A),
.C_INITA_VAL (C_INITA_VAL),
.C_HAS_ENA (1),
.C_HAS_REGCEA (C_HAS_REGCEA),
.C_USE_BYTE_WEA (1),
.C_WEA_WIDTH (C_WEA_WIDTH),
.C_WRITE_MODE_A (C_WRITE_MODE_A),
.C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),
.C_READ_WIDTH_A (C_READ_WIDTH_A),
.C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),
.C_READ_DEPTH_A (C_READ_DEPTH_A),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH),
.C_HAS_RSTB (C_HAS_RSTB),
.C_RST_PRIORITY_B (C_RST_PRIORITY_B),
.C_RSTRAM_B (C_RSTRAM_B),
.C_INITB_VAL (C_INITB_VAL),
.C_HAS_ENB (1),
.C_HAS_REGCEB (C_HAS_MEM_OUTPUT_REGS_B),
.C_USE_BYTE_WEB (1),
.C_WEB_WIDTH (C_WEB_WIDTH),
.C_WRITE_MODE_B (C_WRITE_MODE_B),
.C_WRITE_WIDTH_B (C_WRITE_WIDTH_B),
.C_READ_WIDTH_B (C_READ_WIDTH_B),
.C_WRITE_DEPTH_B (C_WRITE_DEPTH_B),
.C_READ_DEPTH_B (C_READ_DEPTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_MEM_OUTPUT_REGS_A (0),
.C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B),
.C_HAS_MUX_OUTPUT_REGS_A (0),
.C_HAS_MUX_OUTPUT_REGS_B (0),
.C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A),
.C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),
.C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.C_HAS_INJECTERR (C_HAS_INJECTERR),
.C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK),
.C_COMMON_CLK (C_COMMON_CLK),
.FLOP_DELAY (FLOP_DELAY),
.C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL),
.C_EN_ECC_PIPE (0),
.C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE))
blk_mem_gen_v8_2_inst
(.CLKA (S_ACLK),
.RSTA (s_aresetn_a_c),
.ENA (s_axi_wr_en_c),
.REGCEA (regcea_in),
.WEA (S_AXI_WSTRB),
.ADDRA (s_axi_awaddr_out_c),
.DINA (S_AXI_WDATA),
.DOUTA (DOUTA),
.CLKB (S_ACLK),
.RSTB (s_aresetn_a_c),
.ENB (s_axi_rd_en_c),
.REGCEB (regceb_c),
.WEB (WEB_parameterized),
.ADDRB (s_axi_araddr_out_c),
.DINB (DINB),
.DOUTB (s_axi_rdata_c),
.INJECTSBITERR (injectsbiterr_in),
.INJECTDBITERR (injectdbiterr_in),
.SBITERR (SBITERR),
.DBITERR (DBITERR),
.ECCPIPECE (1'b0),
.SLEEP (1'b0),
.RDADDRECC (RDADDRECC)
);
end
endgenerate
endmodule
|
// This is a component of pluto_step, a hardware step waveform generator
// Copyright 2007 Jeff Epler <[email protected]>
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
module stepgen(clk, enable, position, velocity, dirtime, steptime, step, dir, tap);
`define STATE_STEP 0
`define STATE_DIRCHANGE 1
`define STATE_DIRWAIT 2
parameter W=12;
parameter F=10;
parameter T=5;
input clk, enable;
output [W+F-1:0] position; reg [W+F-1:0] position;
input [F:0] velocity;
input [T-1:0] dirtime, steptime;
input [1:0] tap;
output step, dir;
reg step, dir;
reg [T-1:0] timer;
reg [1:0] state;
reg ones;
wire dbit = velocity[F];
wire pbit = (tap == 0 ? position[F]
: (tap == 1 ? position[F+1]
: (tap == 2 ? position[F+2]
: position[F+3])));
wire [W+F-1:0] xvelocity = {{W{velocity[F]}}, {1{velocity[F-1:0]}}};
`ifdef TESTING
// for testing:
initial position = 1'b0;
initial state = `STATE_STEP;
initial timer = 0;
initial dir = 0;
initial ones = 0;
`endif
always @(posedge clk) begin
if(enable) begin
// $display("state=%d timer=%d position=%h velocity=%h dir=%d dbit=%d pbit=%d ones=%d", state, timer, position, xvelocity, dir, dbit, pbit, ones);
if((dir != dbit) && (pbit == ones)) begin
if(state == `STATE_DIRCHANGE) begin
if(timer == 0) begin
dir <= dbit;
timer <= dirtime;
state <= `STATE_DIRWAIT;
end else begin
timer <= timer - 1'd1;
end
end else begin
if(timer == 0) begin
step <= 0;
timer <= dirtime;
state <= `STATE_DIRCHANGE;
end else begin
timer <= timer - 1'd1;
end
end
end else if(state == `STATE_DIRWAIT) begin
if(timer == 0) begin
state <= `STATE_STEP;
end else begin
timer <= timer - 1'd1;
end
end else begin
if(timer == 0) begin
if(pbit != ones) begin
ones <= pbit;
step <= 1'd1;
timer <= steptime;
end else begin
step <= 0;
end
end else begin
timer <= timer - 1'd1;
end
if(dir == dbit)
position <= position + xvelocity;
end
end
end
endmodule
|
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: linebuf.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 14.1.1 Build 190 01/19/2015 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module linebuf (
data,
rdaddress,
rdclock,
wraddress,
wrclock,
wren,
q);
input [23:0] data;
input [11:0] rdaddress;
input rdclock;
input [11:0] wraddress;
input wrclock;
input wren;
output [23:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 wrclock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [23:0] sub_wire0;
wire [23:0] q = sub_wire0[23:0];
altsyncram altsyncram_component (
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (wrclock),
.clock1 (rdclock),
.data_a (data),
.wren_a (wren),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({24{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK1",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.numwords_b = 4096,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "CLOCK1",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.widthad_a = 12,
altsyncram_component.widthad_b = 12,
altsyncram_component.width_a = 24,
altsyncram_component.width_b = 24,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "1"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "98304"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "24"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "24"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "24"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "24"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "24"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "24"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: data 0 0 24 0 INPUT NODEFVAL "data[23..0]"
// Retrieval info: USED_PORT: q 0 0 24 0 OUTPUT NODEFVAL "q[23..0]"
// Retrieval info: USED_PORT: rdaddress 0 0 12 0 INPUT NODEFVAL "rdaddress[11..0]"
// Retrieval info: USED_PORT: rdclock 0 0 0 0 INPUT NODEFVAL "rdclock"
// Retrieval info: USED_PORT: wraddress 0 0 12 0 INPUT NODEFVAL "wraddress[11..0]"
// Retrieval info: USED_PORT: wrclock 0 0 0 0 INPUT VCC "wrclock"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
// Retrieval info: CONNECT: @address_a 0 0 12 0 wraddress 0 0 12 0
// Retrieval info: CONNECT: @address_b 0 0 12 0 rdaddress 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 wrclock 0 0 0 0
// Retrieval info: CONNECT: @clock1 0 0 0 0 rdclock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 24 0 data 0 0 24 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 24 0 @q_b 0 0 24 0
// Retrieval info: GEN_FILE: TYPE_NORMAL linebuf.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL linebuf.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL linebuf.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL linebuf.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL linebuf_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL linebuf_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/*
Distributed under the MIT license.
Copyright (c) 2016 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
* Author:
* Description:
*
* Changes:
*/
`timescale 1ps / 1ps
`define DATA_SIZE 32
module ft245_host_interface (
input clk,
input rst,
//FT245 Interface
input i_ft245_clk,
inout [7:0] io_ft245_data,
input i_ft245_txe_n,
output o_ft245_wr_n,
input i_ft245_rde_n,
output o_ft245_rd_n,
output o_ft245_oe_n,
output o_ft245_siwu,
//Ingress
output ingress_clk,
input [1:0] ingress_rdy,
output reg [1:0] ingress_act,
output reg ingress_stb,
input [23:0] ingress_size,
output reg [`DATA_SIZE - 1: 0] ingress_data,
//Egress
output egress_clk,
input egress_rdy,
output reg egress_act,
output reg egress_stb,
input [23:0] egress_size,
input [`DATA_SIZE - 1: 0] egress_data,
output [31:0] ftdi_debug
);
//local parameters
localparam BYTE_COUNT = `DATA_SIZE / 8;
localparam IDLE = 0;
localparam INGRESS_READ = 1;
localparam EGRESS_PREPARE = 2;
localparam EGRESS_SEND = 3;
localparam EGRESS_SEND_TEMP_DATA = 4;
localparam EGRESS_SEND_IMMEDIATELY = 5;
//registes/wires
reg [3:0]state = IDLE;
reg [23:0] count = 0;
reg [7:0] byte_count = 0;
reg [`DATA_SIZE - 1: 0] r_ft245_ingress_data_dword;
reg [`DATA_SIZE - 1: 0] r_ft245_egress_data_dword;
reg [7:0] r_ft245_egress_data = 8'h0;
reg [7:0] r_ft245_egress_tmp_data = 8'h0;
reg r_ft245_read_tmp_data;
wire w_ft245_ingress_avail;
reg r_ft245_ingress_stb = 0;
reg r_ft245_output_enable = 0;
wire w_ft245_egress_avail;
reg r_ft245_egress_stb = 0;
reg r_ft245_egress_send_now = 0;
wire w_ingress_ready;
wire ft245_clk;
//submodules
//asynchronous logic
assign ft245_clk = i_ft245_clk;
//IBUFG ft245_clock_buf(.I(i_ft245_clk), .O(ft245_clk));
assign ingress_clk = ft245_clk;
assign egress_clk = ft245_clk;
assign w_ft245_ingress_avail = !i_ft245_rde_n;
assign w_ft245_egress_avail = !i_ft245_txe_n;
assign o_ft245_wr_n = !r_ft245_egress_stb;
assign o_ft245_rd_n = !r_ft245_ingress_stb;
assign o_ft245_oe_n = !r_ft245_output_enable;
assign o_ft245_siwu = !r_ft245_egress_send_now;
assign io_ft245_data = r_ft245_output_enable ? 8'hZZ : (r_ft245_read_tmp_data) ? r_ft245_egress_tmp_data: r_ft245_egress_data;
assign w_ingress_ready = (count < ingress_size) && !((count + 1 == ingress_size) && (byte_count == 3));
//assign ftdi_debug = 32'h0;
assign ftdi_debug[3:0] = state;
assign ftdi_debug[5:4] = ingress_rdy;
assign ftdi_debug[7:6] = ingress_act;
assign ftdi_debug[8] = ingress_stb;
assign ftdi_debug[9] = egress_rdy;
assign ftdi_debug[10] = egress_act;
assign ftdi_debug[11] = w_ingress_ready;
assign ftdi_debug[13:12] = ingress_data[1:0];
assign ftdi_debug[15:14] = egress_data[1:0];
assign ftdi_debug[31:16] = 16'h0;
//synchronous logic
always @ (posedge i_ft245_clk) begin
r_ft245_egress_stb <= 0;
r_ft245_ingress_stb <= 0;
r_ft245_egress_send_now <= 0;
ingress_stb <= 0;
egress_stb <= 0;
if (rst) begin
state <= IDLE;
count <= 0;
byte_count <= 0;
ingress_data <= 0;
r_ft245_output_enable <= 0;
r_ft245_egress_data <= 0;
r_ft245_egress_data_dword <= 0;
r_ft245_ingress_data_dword <= 0;
r_ft245_egress_tmp_data <= 0;
r_ft245_read_tmp_data <= 0;
ingress_act <= 0;
egress_act <= 0;
end
else begin
case (state)
IDLE: begin
count <= 0;
byte_count <= 0;
egress_act <= 1'b0;
r_ft245_output_enable <= 1'b0;
r_ft245_read_tmp_data <= 0;
//If you can grab an incomming FIFO get one
if ((ingress_rdy > 0) && (ingress_act == 2'b00)) begin
if (ingress_rdy[0]) begin
ingress_act[0] <= 1;
end
else begin
ingress_act[1] <= 1;
end
end
//Incomming Data and we have room for it
if (w_ft245_ingress_avail && (ingress_act > 0)) begin
r_ft245_output_enable <= 1;
state <= INGRESS_READ;
end
//Outgoing Data
else if (egress_rdy && !egress_act) begin //Will the chip lock up when it wants to send and I want to send?
egress_act <= 1;
state <= EGRESS_PREPARE;
end
end
INGRESS_READ: begin
if (count < ingress_size) begin
if (r_ft245_ingress_stb && w_ft245_ingress_avail) begin
byte_count <= byte_count + 1;
r_ft245_ingress_data_dword <= {r_ft245_ingress_data_dword[23:0], io_ft245_data};
if (byte_count >= (BYTE_COUNT - 1)) begin
ingress_data <= {r_ft245_ingress_data_dword[23:0], io_ft245_data};
byte_count <= 0;
count <= count + 1;
ingress_stb <= 1;
end
end
if (w_ft245_ingress_avail && !(((count + 1) == ingress_size) && (byte_count == 3))) begin
r_ft245_ingress_stb <= 1;
end
end
else begin
ingress_act <= 0;
state <= IDLE;
end
if (!w_ft245_ingress_avail && (byte_count == 0)) begin
ingress_act <= 0;
state <= IDLE;
end
end
EGRESS_PREPARE: begin
r_ft245_egress_data_dword <= egress_data;
//count <= count + 1;
byte_count <= 0;
if (w_ft245_egress_avail) begin
state <= EGRESS_SEND;
egress_stb <= 1;
end
end
EGRESS_SEND: begin
r_ft245_read_tmp_data <= 0;
r_ft245_egress_data <= r_ft245_egress_data_dword[31:24];
if (w_ft245_egress_avail) begin
if (byte_count < (BYTE_COUNT - 1)) begin
r_ft245_egress_stb <= 1;
r_ft245_egress_data_dword <= {r_ft245_egress_data_dword[23:0], 8'h00};
byte_count <= byte_count + 1;
end
else if (count < egress_size) begin
//Last get the next piece of data
if (count == (egress_size - 1)) begin
egress_act <= 0;
state <= EGRESS_SEND_IMMEDIATELY;
end
r_ft245_egress_data_dword <= egress_data;
count <= count + 1;
byte_count <= 0;
egress_stb <= 1;
r_ft245_egress_stb <= 1;
end
end
else if (!r_ft245_read_tmp_data && egress_act && r_ft245_egress_stb) begin
r_ft245_read_tmp_data <= 1;
r_ft245_egress_tmp_data <= r_ft245_egress_data;
state <= EGRESS_SEND_TEMP_DATA;
end
if (count >= egress_size) begin
egress_act <= 0;
byte_count <= 0;
r_ft245_egress_stb <= 1;
state <= EGRESS_SEND_IMMEDIATELY;
end
end
EGRESS_SEND_TEMP_DATA: begin
if (w_ft245_egress_avail) begin
r_ft245_egress_stb <= 1;
state <= EGRESS_SEND;
end
end
EGRESS_SEND_IMMEDIATELY: begin
if (w_ft245_egress_avail) begin
r_ft245_egress_send_now <= 1;
end
state <= IDLE;
end
default: begin
state <= IDLE;
end
endcase
end
end
endmodule
|
// file: clk_wiz_v3_2.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// "Output Output Phase Duty Pk-to-Pk Phase"
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
//----------------------------------------------------------------------------
// CLK_OUT1___200.000______0.000_______N/A______220.000________N/A
//
//----------------------------------------------------------------------------
// "Input Clock Freq (MHz) Input Jitter (UI)"
//----------------------------------------------------------------------------
// __primary_________100.000_____________0.01
`timescale 1ps/1ps
// Please set INPUT_FREQUENCY to the MHz of the incoming clock!!
// WARNING: This module will currently NOT handle anything other than a 100MHz
// clock because the CLKIN_PERIOD is not properly calculated.
//
// SYNTHESIS_FREQUENCY is used to determine at what frequency the design is
// synthesized for.
//
//
// NOTE: Internally, the divider is set to half of
// INPUT_FREQUENCY. This allows a greater range of output frequencies.
// So when you look at the COMM code, you'll see that it takes the requested
// frequency and divides by 2 to get the proper multiplier.
module dynamic_clock # (
parameter INPUT_FREQUENCY = 100,
parameter SYNTHESIS_FREQUENCY = 200
) (
input CLK_IN1,
output CLK_OUT1,
input PROGCLK,
input PROGDATA,
input PROGEN,
output PROGDONE
);
// Input buffering
//------------------------------------
/*IBUFG clkin1_buf
(.O (clkin1),
.I (CLK_IN1));*/
// Clocking primitive
//------------------------------------
// Instantiation of the DCM primitive
// * Unused inputs are tied off
wire clkfx;
DCM_CLKGEN
#(.CLKFXDV_DIVIDE (2),
.CLKFX_DIVIDE (INPUT_FREQUENCY >> 1),
.CLKFX_MULTIPLY (SYNTHESIS_FREQUENCY >> 1),
.SPREAD_SPECTRUM ("NONE"),
.STARTUP_WAIT ("FALSE"),
.CLKIN_PERIOD (10.0),
.CLKFX_MD_MAX (0.000))
dcm_clkgen_inst
// Input clock
(.CLKIN (CLK_IN1),
// Output clocks
.CLKFX (clkfx),
.CLKFX180 (),
.CLKFXDV (),
// Ports for dynamic reconfiguration
.PROGCLK (PROGCLK),
.PROGDATA (PROGDATA),
.PROGEN (PROGEN),
.PROGDONE (PROGDONE),
// Other control and status signals
.FREEZEDCM (1'b0),
.LOCKED (),
.STATUS (),
.RST (1'b0));
// Output buffering
//-----------------------------------
BUFG clkout1_buf
(.O (CLK_OUT1),
.I (clkfx));
endmodule
|
/*
* Copyright (c) 2001 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module main;
reg [7:0] x, y;
initial begin
x = -4;
if (x !== 8'hfc) begin
$display("FAILED -- x = -4 --> %b", x);
$finish;
end
x = 4;
if (x !== 8'h04) begin
$display("FAILED");
$finish;
end
y = -x;
if (y !== 8'hfc) begin
$display("FAILED -- y = -%b --> %b", x, y);
$finish;
end
$display("PASSED");
end // initial begin
endmodule // main
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__AND4BB_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__AND4BB_BEHAVIORAL_PP_V
/**
* and4bb: 4-input AND, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__and4bb (
X ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
nor nor0 (nor0_out , A_N, B_N );
and and0 (and0_out_X , nor0_out, C, D );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__AND4BB_BEHAVIORAL_PP_V |
// (C) 2001-2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module store and retrieves video frames to and from memory. *
* *
******************************************************************************/
`undef USE_TO_MEMORY
`define USE_32BIT_MASTER
module Computer_System_Video_In_Subsystem_Video_In_DMA (
// Inputs
clk,
reset,
stream_data,
stream_startofpacket,
stream_endofpacket,
stream_empty,
stream_valid,
master_waitrequest,
slave_address,
slave_byteenable,
slave_read,
slave_write,
slave_writedata,
// Bidirectional
// Outputs
stream_ready,
master_address,
master_write,
master_writedata,
slave_readdata
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter DW = 15; // Frame's datawidth
parameter EW = 0; // Frame's empty width
parameter WIDTH = 320; // Frame's width in pixels
parameter HEIGHT = 240; // Frame's height in lines
parameter AW = 16; // Frame's address width
parameter WW = 8; // Frame width's address width
parameter HW = 7; // Frame height's address width
parameter MDW = 15; // Avalon master's datawidth
parameter DEFAULT_BUFFER_ADDRESS = 32'd134217728;
parameter DEFAULT_BACK_BUF_ADDRESS = 32'd134217728;
parameter ADDRESSING_BITS = 16'd2057;
parameter COLOR_BITS = 4'd15;
parameter COLOR_PLANES = 2'd0;
parameter DEFAULT_DMA_ENABLED = 1'b0; // 0: OFF or 1: ON
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [DW: 0] stream_data;
input stream_startofpacket;
input stream_endofpacket;
input [EW: 0] stream_empty;
input stream_valid;
input master_waitrequest;
input [ 1: 0] slave_address;
input [ 3: 0] slave_byteenable;
input slave_read;
input slave_write;
input [31: 0] slave_writedata;
// Bidirectional
// Outputs
output stream_ready;
output [31: 0] master_address;
output master_write;
output [MDW:0] master_writedata;
output [31: 0] slave_readdata;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire inc_address;
wire reset_address;
wire [31: 0] buffer_start_address;
wire dma_enabled;
// Internal Registers
reg [WW: 0] w_address; // Frame's width address
reg [HW: 0] h_address; // Frame's height address
// State Machine Registers
// Integers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
// Internal Registers
always @(posedge clk)
begin
if (reset)
begin
w_address <= 'h0;
h_address <= 'h0;
end
else if (reset_address)
begin
w_address <= 'h0;
h_address <= 'h0;
end
else if (inc_address)
begin
if (w_address == (WIDTH - 1))
begin
w_address <= 'h0;
h_address <= h_address + 1;
end
else
w_address <= w_address + 1;
end
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign master_address = buffer_start_address +
{h_address, w_address, 1'b0};
// Internal Assignments
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_video_dma_control_slave DMA_Control_Slave (
// Inputs
.clk (clk),
.reset (reset),
.address (slave_address),
.byteenable (slave_byteenable),
.read (slave_read),
.write (slave_write),
.writedata (slave_writedata),
.swap_addresses_enable (reset_address),
// Bi-Directional
// Outputs
.readdata (slave_readdata),
.current_start_address (buffer_start_address),
.dma_enabled (dma_enabled)
);
defparam
DMA_Control_Slave.DEFAULT_BUFFER_ADDRESS = DEFAULT_BUFFER_ADDRESS,
DMA_Control_Slave.DEFAULT_BACK_BUF_ADDRESS = DEFAULT_BACK_BUF_ADDRESS,
DMA_Control_Slave.WIDTH = WIDTH,
DMA_Control_Slave.HEIGHT = HEIGHT,
DMA_Control_Slave.ADDRESSING_BITS = ADDRESSING_BITS,
DMA_Control_Slave.COLOR_BITS = COLOR_BITS,
DMA_Control_Slave.COLOR_PLANES = COLOR_PLANES,
DMA_Control_Slave.ADDRESSING_MODE = 1'b0,
DMA_Control_Slave.DEFAULT_DMA_ENABLED = DEFAULT_DMA_ENABLED;
altera_up_video_dma_to_memory From_Stream_to_Memory (
// Inputs
.clk (clk),
.reset (reset | ~dma_enabled),
.stream_data (stream_data),
.stream_startofpacket (stream_startofpacket),
.stream_endofpacket (stream_endofpacket),
.stream_empty (stream_empty),
.stream_valid (stream_valid),
.master_waitrequest (master_waitrequest),
// Bidirectional
// Outputs
.stream_ready (stream_ready),
.master_write (master_write),
.master_writedata (master_writedata),
.inc_address (inc_address),
.reset_address (reset_address)
);
defparam
From_Stream_to_Memory.DW = DW,
From_Stream_to_Memory.EW = EW,
From_Stream_to_Memory.MDW = MDW;
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: ddr_phy_ck_addr_cmd_delay.v
// /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $
// \ \ / \ Date Created: Aug 03 2009
// \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose: Shift CK/Address/Commands/Controls
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v2_3_ddr_phy_ck_addr_cmd_delay #
(
parameter TCQ = 100,
parameter tCK = 3636,
parameter DQS_CNT_WIDTH = 3,
parameter N_CTL_LANES = 3,
parameter SIM_CAL_OPTION = "NONE"
)
(
input clk,
input rst,
// Start only after PO_CIRC_BUF_DELAY decremented
input cmd_delay_start,
// Control lane being shifted using Phaser_Out fine delay taps
output reg [N_CTL_LANES-1:0] ctl_lane_cnt,
// Inc/dec Phaser_Out fine delay line
output reg po_stg2_f_incdec,
output reg po_en_stg2_f,
output reg po_stg2_c_incdec,
output reg po_en_stg2_c,
// Completed delaying CK/Address/Commands/Controls
output po_ck_addr_cmd_delay_done
);
localparam TAP_CNT_LIMIT = 63;
//Calculate the tap resolution of the PHASER based on the clock period
localparam FREQ_REF_DIV = (tCK > 5000 ? 4 :
tCK > 2500 ? 2 : 1);
localparam integer PHASER_TAP_RES = ((tCK/2)/64);
// Determine whether 300 ps or 350 ps delay required
localparam CALC_TAP_CNT = (tCK >= 1250) ? 350 : 300;
// Determine the number of Phaser_Out taps required to delay by 300 ps
// 300 ps is the PCB trace uncertainty between CK and DQS byte groups
// Increment control byte lanes
localparam TAP_CNT = 0;
//localparam TAP_CNT = (CALC_TAP_CNT + PHASER_TAP_RES - 1)/PHASER_TAP_RES;
//Decrement control byte lanes
localparam TAP_DEC = (SIM_CAL_OPTION == "FAST_CAL") ? 0 : 29;
reg delay_dec_done;
reg delay_done_r1;
reg delay_done_r2;
reg delay_done_r3;
reg delay_done_r4 /* synthesis syn_maxfan = 10 */;
reg [5:0] delay_cnt_r;
reg [5:0] delaydec_cnt_r;
reg po_cnt_inc;
reg po_cnt_dec;
reg [3:0] wait_cnt_r;
assign po_ck_addr_cmd_delay_done = ((TAP_CNT == 0) && (TAP_DEC == 0)) ? 1'b1 : delay_done_r4;
always @(posedge clk) begin
if (rst || po_cnt_dec || po_cnt_inc)
wait_cnt_r <= #TCQ 'd8;
else if (cmd_delay_start && (wait_cnt_r > 'd0))
wait_cnt_r <= #TCQ wait_cnt_r - 1;
end
always @(posedge clk) begin
if (rst || (delaydec_cnt_r > 6'd0) || (delay_cnt_r == 'd0) || (TAP_DEC == 0))
po_cnt_inc <= #TCQ 1'b0;
else if ((delay_cnt_r > 'd0) && (wait_cnt_r == 'd1))
po_cnt_inc <= #TCQ 1'b1;
else
po_cnt_inc <= #TCQ 1'b0;
end
//Tap decrement
always @(posedge clk) begin
if (rst || (delaydec_cnt_r == 'd0))
po_cnt_dec <= #TCQ 1'b0;
else if (cmd_delay_start && (delaydec_cnt_r > 'd0) && (wait_cnt_r == 'd1))
po_cnt_dec <= #TCQ 1'b1;
else
po_cnt_dec <= #TCQ 1'b0;
end
//po_stg2_f_incdec and po_en_stg2_f stay asserted HIGH for TAP_COUNT cycles for every control byte lane
//the alignment is started once the
always @(posedge clk) begin
if (rst) begin
po_stg2_f_incdec <= #TCQ 1'b0;
po_en_stg2_f <= #TCQ 1'b0;
po_stg2_c_incdec <= #TCQ 1'b0;
po_en_stg2_c <= #TCQ 1'b0;
end else begin
if (po_cnt_dec) begin
po_stg2_f_incdec <= #TCQ 1'b0;
po_en_stg2_f <= #TCQ 1'b1;
end else begin
po_stg2_f_incdec <= #TCQ 1'b0;
po_en_stg2_f <= #TCQ 1'b0;
end
if (po_cnt_inc) begin
po_stg2_c_incdec <= #TCQ 1'b1;
po_en_stg2_c <= #TCQ 1'b1;
end else begin
po_stg2_c_incdec <= #TCQ 1'b0;
po_en_stg2_c <= #TCQ 1'b0;
end
end
end
// delay counter to count 2 cycles
// Increment coarse taps by 2 for all control byte lanes
// to mitigate late writes
always @(posedge clk) begin
// load delay counter with init value
if (rst || (tCK > 2500) || (SIM_CAL_OPTION == "FAST_CAL"))
delay_cnt_r <= #TCQ 'd0;
else if ((delaydec_cnt_r > 6'd0) ||((delay_cnt_r == 6'd0) && (ctl_lane_cnt != N_CTL_LANES-1)))
delay_cnt_r <= #TCQ 'd1;
else if (po_cnt_inc && (delay_cnt_r > 6'd0))
delay_cnt_r <= #TCQ delay_cnt_r - 1;
end
// delay counter to count TAP_DEC cycles
always @(posedge clk) begin
// load delay counter with init value of TAP_DEC
if (rst || ~cmd_delay_start ||((delaydec_cnt_r == 6'd0) && (delay_cnt_r == 6'd0) && (ctl_lane_cnt != N_CTL_LANES-1)))
delaydec_cnt_r <= #TCQ TAP_DEC;
else if (po_cnt_dec && (delaydec_cnt_r > 6'd0))
delaydec_cnt_r <= #TCQ delaydec_cnt_r - 1;
end
//ctl_lane_cnt is used to count the number of CTL_LANES or byte lanes that have the address/command phase shifted by 1/4 mem. cycle
//This ensures all ctrl byte lanes have had their output phase shifted.
always @(posedge clk) begin
if (rst || ~cmd_delay_start )
ctl_lane_cnt <= #TCQ 6'b0;
else if (~delay_dec_done && (ctl_lane_cnt == N_CTL_LANES-1) && (delaydec_cnt_r == 6'd1))
ctl_lane_cnt <= #TCQ ctl_lane_cnt;
else if ((ctl_lane_cnt != N_CTL_LANES-1) && (delaydec_cnt_r == 6'd0) && (delay_cnt_r == 'd0))
ctl_lane_cnt <= #TCQ ctl_lane_cnt + 1;
end
// All control lanes have decremented to 31 fine taps from 46
always @(posedge clk) begin
if (rst || ~cmd_delay_start) begin
delay_dec_done <= #TCQ 1'b0;
end else if (((TAP_CNT == 0) && (TAP_DEC == 0)) ||
((delaydec_cnt_r == 6'd0) && (delay_cnt_r == 'd0) && (ctl_lane_cnt == N_CTL_LANES-1))) begin
delay_dec_done <= #TCQ 1'b1;
end
end
always @(posedge clk) begin
delay_done_r1 <= #TCQ delay_dec_done;
delay_done_r2 <= #TCQ delay_done_r1;
delay_done_r3 <= #TCQ delay_done_r2;
delay_done_r4 <= #TCQ delay_done_r3;
end
endmodule
|
(***********************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA-Rocquencourt & LRI-CNRS-Orsay *)
(* \VV/ *************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(***********************************************************************)
(** * MSetRBT : Implementation of MSetInterface via Red-Black trees *)
(** Initial author: Andrew W. Appel, 2011.
Extra modifications by: Pierre Letouzey
The design decisions behind this implementation are described here:
- Efficient Verified Red-Black Trees, by Andrew W. Appel, September 2011.
http://www.cs.princeton.edu/~appel/papers/redblack.pdf
Additional suggested reading:
- Red-Black Trees in a Functional Setting by Chris Okasaki.
Journal of Functional Programming, 9(4):471-477, July 1999.
http://www.eecs.usma.edu/webs/people/okasaki/jfp99redblack.pdf
- Red-black trees with types, by Stefan Kahrs.
Journal of Functional Programming, 11(4), 425-432, 2001.
- Functors for Proofs and Programs, by J.-C. Filliatre and P. Letouzey.
ESOP'04: European Symposium on Programming, pp. 370-384, 2004.
http://www.lri.fr/~filliatr/ftp/publis/fpp.ps.gz
*)
Require MSetGenTree.
Require Import Bool List BinPos Pnat Setoid SetoidList NPeano.
Local Open Scope list_scope.
(* For nicer extraction, we create induction principles
only when needed *)
Local Unset Elimination Schemes.
Local Unset Case Analysis Schemes.
(** An extra function not (yet?) in MSetInterface.S *)
Module Type MSetRemoveMin (Import M:MSetInterface.S).
Parameter remove_min : t -> option (elt * t).
Axiom remove_min_spec1 : forall s k s',
remove_min s = Some (k,s') ->
min_elt s = Some k /\ remove k s [=] s'.
Axiom remove_min_spec2 : forall s, remove_min s = None -> Empty s.
End MSetRemoveMin.
(** The type of color annotation. *)
Inductive color := Red | Black.
Module Color.
Definition t := color.
End Color.
(** * Ops : the pure functions *)
Module Ops (X:Orders.OrderedType) <: MSetInterface.Ops X.
(** ** Generic trees instantiated with color *)
(** We reuse a generic definition of trees where the information
parameter is a color. Functions like mem or fold are also
provided by this generic functor. *)
Include MSetGenTree.Ops X Color.
Definition t := tree.
Local Notation Rd := (Node Red).
Local Notation Bk := (Node Black).
(** ** Basic tree *)
Definition singleton (k: elt) : tree := Bk Leaf k Leaf.
(** ** Changing root color *)
Definition makeBlack t :=
match t with
| Leaf => Leaf
| Node _ a x b => Bk a x b
end.
Definition makeRed t :=
match t with
| Leaf => Leaf
| Node _ a x b => Rd a x b
end.
(** ** Balancing *)
(** We adapt when one side is not a true red-black tree.
Both sides have the same black depth. *)
Definition lbal l k r :=
match l with
| Rd (Rd a x b) y c => Rd (Bk a x b) y (Bk c k r)
| Rd a x (Rd b y c) => Rd (Bk a x b) y (Bk c k r)
| _ => Bk l k r
end.
Definition rbal l k r :=
match r with
| Rd (Rd b y c) z d => Rd (Bk l k b) y (Bk c z d)
| Rd b y (Rd c z d) => Rd (Bk l k b) y (Bk c z d)
| _ => Bk l k r
end.
(** A variant of [rbal], with reverse pattern order.
Is it really useful ? Should we always use it ? *)
Definition rbal' l k r :=
match r with
| Rd b y (Rd c z d) => Rd (Bk l k b) y (Bk c z d)
| Rd (Rd b y c) z d => Rd (Bk l k b) y (Bk c z d)
| _ => Bk l k r
end.
(** Balancing with different black depth.
One side is almost a red-black tree, while the other is
a true red-black tree, but with black depth + 1.
Used in deletion. *)
Definition lbalS l k r :=
match l with
| Rd a x b => Rd (Bk a x b) k r
| _ =>
match r with
| Bk a y b => rbal' l k (Rd a y b)
| Rd (Bk a y b) z c => Rd (Bk l k a) y (rbal' b z (makeRed c))
| _ => Rd l k r (* impossible *)
end
end.
Definition rbalS l k r :=
match r with
| Rd b y c => Rd l k (Bk b y c)
| _ =>
match l with
| Bk a x b => lbal (Rd a x b) k r
| Rd a x (Bk b y c) => Rd (lbal (makeRed a) x b) y (Bk c k r)
| _ => Rd l k r (* impossible *)
end
end.
(** ** Insertion *)
Fixpoint ins x s :=
match s with
| Leaf => Rd Leaf x Leaf
| Node c l y r =>
match X.compare x y with
| Eq => s
| Lt =>
match c with
| Red => Rd (ins x l) y r
| Black => lbal (ins x l) y r
end
| Gt =>
match c with
| Red => Rd l y (ins x r)
| Black => rbal l y (ins x r)
end
end
end.
Definition add x s := makeBlack (ins x s).
(** ** Deletion *)
Fixpoint append (l:tree) : tree -> tree :=
match l with
| Leaf => fun r => r
| Node lc ll lx lr =>
fix append_l (r:tree) : tree :=
match r with
| Leaf => l
| Node rc rl rx rr =>
match lc, rc with
| Red, Red =>
let lrl := append lr rl in
match lrl with
| Rd lr' x rl' => Rd (Rd ll lx lr') x (Rd rl' rx rr)
| _ => Rd ll lx (Rd lrl rx rr)
end
| Black, Black =>
let lrl := append lr rl in
match lrl with
| Rd lr' x rl' => Rd (Bk ll lx lr') x (Bk rl' rx rr)
| _ => lbalS ll lx (Bk lrl rx rr)
end
| Black, Red => Rd (append_l rl) rx rr
| Red, Black => Rd ll lx (append lr r)
end
end
end.
Fixpoint del x t :=
match t with
| Leaf => Leaf
| Node _ a y b =>
match X.compare x y with
| Eq => append a b
| Lt =>
match a with
| Bk _ _ _ => lbalS (del x a) y b
| _ => Rd (del x a) y b
end
| Gt =>
match b with
| Bk _ _ _ => rbalS a y (del x b)
| _ => Rd a y (del x b)
end
end
end.
Definition remove x t := makeBlack (del x t).
(** ** Removing minimal element *)
Fixpoint delmin l x r : (elt * tree) :=
match l with
| Leaf => (x,r)
| Node lc ll lx lr =>
let (k,l') := delmin ll lx lr in
match lc with
| Black => (k, lbalS l' x r)
| Red => (k, Rd l' x r)
end
end.
Definition remove_min t : option (elt * tree) :=
match t with
| Leaf => None
| Node _ l x r =>
let (k,t) := delmin l x r in
Some (k, makeBlack t)
end.
(** ** Tree-ification
We rebuild a tree of size [if pred then n-1 else n] as soon
as the list [l] has enough elements *)
Definition bogus : tree * list elt := (Leaf, nil).
Notation treeify_t := (list elt -> tree * list elt).
Definition treeify_zero : treeify_t :=
fun acc => (Leaf,acc).
Definition treeify_one : treeify_t :=
fun acc => match acc with
| x::acc => (Rd Leaf x Leaf, acc)
| _ => bogus
end.
Definition treeify_cont (f g : treeify_t) : treeify_t :=
fun acc =>
match f acc with
| (l, x::acc) =>
match g acc with
| (r, acc) => (Bk l x r, acc)
end
| _ => bogus
end.
Fixpoint treeify_aux (pred:bool)(n: positive) : treeify_t :=
match n with
| xH => if pred then treeify_zero else treeify_one
| xO n => treeify_cont (treeify_aux pred n) (treeify_aux true n)
| xI n => treeify_cont (treeify_aux false n) (treeify_aux pred n)
end.
Fixpoint plength_aux (l:list elt)(p:positive) := match l with
| nil => p
| _::l => plength_aux l (Pos.succ p)
end.
Definition plength l := plength_aux l 1.
Definition treeify (l:list elt) :=
fst (treeify_aux true (plength l) l).
(** ** Filtering *)
Fixpoint filter_aux (f: elt -> bool) s acc :=
match s with
| Leaf => acc
| Node _ l k r =>
let acc := filter_aux f r acc in
if f k then filter_aux f l (k::acc)
else filter_aux f l acc
end.
Definition filter (f: elt -> bool) (s: t) : t :=
treeify (filter_aux f s nil).
Fixpoint partition_aux (f: elt -> bool) s acc1 acc2 :=
match s with
| Leaf => (acc1,acc2)
| Node _ sl k sr =>
let (acc1, acc2) := partition_aux f sr acc1 acc2 in
if f k then partition_aux f sl (k::acc1) acc2
else partition_aux f sl acc1 (k::acc2)
end.
Definition partition (f: elt -> bool) (s:t) : t*t :=
let (ok,ko) := partition_aux f s nil nil in
(treeify ok, treeify ko).
(** ** Union, intersection, difference *)
(** union of the elements of [l1] and [l2] into a third [acc] list. *)
Fixpoint union_list l1 : list elt -> list elt -> list elt :=
match l1 with
| nil => @rev_append _
| x::l1' =>
fix union_l1 l2 acc :=
match l2 with
| nil => rev_append l1 acc
| y::l2' =>
match X.compare x y with
| Eq => union_list l1' l2' (x::acc)
| Lt => union_l1 l2' (y::acc)
| Gt => union_list l1' l2 (x::acc)
end
end
end.
Definition linear_union s1 s2 :=
treeify (union_list (rev_elements s1) (rev_elements s2) nil).
Fixpoint inter_list l1 : list elt -> list elt -> list elt :=
match l1 with
| nil => fun _ acc => acc
| x::l1' =>
fix inter_l1 l2 acc :=
match l2 with
| nil => acc
| y::l2' =>
match X.compare x y with
| Eq => inter_list l1' l2' (x::acc)
| Lt => inter_l1 l2' acc
| Gt => inter_list l1' l2 acc
end
end
end.
Definition linear_inter s1 s2 :=
treeify (inter_list (rev_elements s1) (rev_elements s2) nil).
Fixpoint diff_list l1 : list elt -> list elt -> list elt :=
match l1 with
| nil => fun _ acc => acc
| x::l1' =>
fix diff_l1 l2 acc :=
match l2 with
| nil => rev_append l1 acc
| y::l2' =>
match X.compare x y with
| Eq => diff_list l1' l2' acc
| Lt => diff_l1 l2' acc
| Gt => diff_list l1' l2 (x::acc)
end
end
end.
Definition linear_diff s1 s2 :=
treeify (diff_list (rev_elements s1) (rev_elements s2) nil).
(** [compare_height] returns:
- [Lt] if [height s2] is at least twice [height s1];
- [Gt] if [height s1] is at least twice [height s2];
- [Eq] if heights are approximately equal.
Warning: this is not an equivalence relation! but who cares.... *)
Definition skip_red t :=
match t with
| Rd t' _ _ => t'
| _ => t
end.
Definition skip_black t :=
match skip_red t with
| Bk t' _ _ => t'
| t' => t'
end.
Fixpoint compare_height (s1x s1 s2 s2x: tree) : comparison :=
match skip_red s1x, skip_red s1, skip_red s2, skip_red s2x with
| Node _ s1x' _ _, Node _ s1' _ _, Node _ s2' _ _, Node _ s2x' _ _ =>
compare_height (skip_black s2x') s1' s2' (skip_black s2x')
| _, Leaf, _, Node _ _ _ _ => Lt
| Node _ _ _ _, _, Leaf, _ => Gt
| Node _ s1x' _ _, Node _ s1' _ _, Node _ s2' _ _, Leaf =>
compare_height (skip_black s1x') s1' s2' Leaf
| Leaf, Node _ s1' _ _, Node _ s2' _ _, Node _ s2x' _ _ =>
compare_height Leaf s1' s2' (skip_black s2x')
| _, _, _, _ => Eq
end.
(** When one tree is quite smaller than the other, we simply
adds repeatively all its elements in the big one.
For trees of comparable height, we rather use [linear_union]. *)
Definition union (t1 t2: t) : t :=
match compare_height t1 t1 t2 t2 with
| Lt => fold add t1 t2
| Gt => fold add t2 t1
| Eq => linear_union t1 t2
end.
Definition diff (t1 t2: t) : t :=
match compare_height t1 t1 t2 t2 with
| Lt => filter (fun k => negb (mem k t2)) t1
| Gt => fold remove t2 t1
| Eq => linear_diff t1 t2
end.
Definition inter (t1 t2: t) : t :=
match compare_height t1 t1 t2 t2 with
| Lt => filter (fun k => mem k t2) t1
| Gt => filter (fun k => mem k t1) t2
| Eq => linear_inter t1 t2
end.
End Ops.
(** * MakeRaw : the pure functions and their specifications *)
Module Type MakeRaw (X:Orders.OrderedType) <: MSetInterface.RawSets X.
Include Ops X.
(** Generic definition of binary-search-trees and proofs of
specifications for generic functions such as mem or fold. *)
Include MSetGenTree.Props X Color.
Local Notation Rd := (Node Red).
Local Notation Bk := (Node Black).
Local Hint Immediate MX.eq_sym.
Local Hint Unfold In lt_tree gt_tree Ok.
Local Hint Constructors InT bst.
Local Hint Resolve MX.eq_refl MX.eq_trans MX.lt_trans ok.
Local Hint Resolve lt_leaf gt_leaf lt_tree_node gt_tree_node.
Local Hint Resolve lt_tree_not_in lt_tree_trans gt_tree_not_in gt_tree_trans.
Local Hint Resolve elements_spec2.
(** ** Singleton set *)
Lemma singleton_spec x y : InT y (singleton x) <-> X.eq y x.
Proof.
unfold singleton; intuition_in.
Qed.
Instance singleton_ok x : Ok (singleton x).
Proof.
unfold singleton; auto.
Qed.
(** ** makeBlack, MakeRed *)
Lemma makeBlack_spec s x : InT x (makeBlack s) <-> InT x s.
Proof.
destruct s; simpl; intuition_in.
Qed.
Lemma makeRed_spec s x : InT x (makeRed s) <-> InT x s.
Proof.
destruct s; simpl; intuition_in.
Qed.
Instance makeBlack_ok s `{Ok s} : Ok (makeBlack s).
Proof.
destruct s; simpl; ok.
Qed.
Instance makeRed_ok s `{Ok s} : Ok (makeRed s).
Proof.
destruct s; simpl; ok.
Qed.
(** ** Generic handling for red-matching and red-red-matching *)
Definition isblack t :=
match t with Bk _ _ _ => True | _ => False end.
Definition notblack t :=
match t with Bk _ _ _ => False | _ => True end.
Definition notred t :=
match t with Rd _ _ _ => False | _ => True end.
Definition rcase {A} f g t : A :=
match t with
| Rd a x b => f a x b
| _ => g t
end.
Inductive rspec {A} f g : tree -> A -> Prop :=
| rred a x b : rspec f g (Rd a x b) (f a x b)
| relse t : notred t -> rspec f g t (g t).
Fact rmatch {A} f g t : rspec (A:=A) f g t (rcase f g t).
Proof.
destruct t as [|[|] l x r]; simpl; now constructor.
Qed.
Definition rrcase {A} f g t : A :=
match t with
| Rd (Rd a x b) y c => f a x b y c
| Rd a x (Rd b y c) => f a x b y c
| _ => g t
end.
Notation notredred := (rrcase (fun _ _ _ _ _ => False) (fun _ => True)).
Inductive rrspec {A} f g : tree -> A -> Prop :=
| rrleft a x b y c : rrspec f g (Rd (Rd a x b) y c) (f a x b y c)
| rrright a x b y c : rrspec f g (Rd a x (Rd b y c)) (f a x b y c)
| rrelse t : notredred t -> rrspec f g t (g t).
Fact rrmatch {A} f g t : rrspec (A:=A) f g t (rrcase f g t).
Proof.
destruct t as [|[|] l x r]; simpl; try now constructor.
destruct l as [|[|] ll lx lr], r as [|[|] rl rx rr]; now constructor.
Qed.
Definition rrcase' {A} f g t : A :=
match t with
| Rd a x (Rd b y c) => f a x b y c
| Rd (Rd a x b) y c => f a x b y c
| _ => g t
end.
Fact rrmatch' {A} f g t : rrspec (A:=A) f g t (rrcase' f g t).
Proof.
destruct t as [|[|] l x r]; simpl; try now constructor.
destruct l as [|[|] ll lx lr], r as [|[|] rl rx rr]; now constructor.
Qed.
(** Balancing operations are instances of generic match *)
Fact lbal_match l k r :
rrspec
(fun a x b y c => Rd (Bk a x b) y (Bk c k r))
(fun l => Bk l k r)
l
(lbal l k r).
Proof.
exact (rrmatch _ _ _).
Qed.
Fact rbal_match l k r :
rrspec
(fun a x b y c => Rd (Bk l k a) x (Bk b y c))
(fun r => Bk l k r)
r
(rbal l k r).
Proof.
exact (rrmatch _ _ _).
Qed.
Fact rbal'_match l k r :
rrspec
(fun a x b y c => Rd (Bk l k a) x (Bk b y c))
(fun r => Bk l k r)
r
(rbal' l k r).
Proof.
exact (rrmatch' _ _ _).
Qed.
Fact lbalS_match l x r :
rspec
(fun a y b => Rd (Bk a y b) x r)
(fun l =>
match r with
| Bk a y b => rbal' l x (Rd a y b)
| Rd (Bk a y b) z c => Rd (Bk l x a) y (rbal' b z (makeRed c))
| _ => Rd l x r
end)
l
(lbalS l x r).
Proof.
exact (rmatch _ _ _).
Qed.
Fact rbalS_match l x r :
rspec
(fun a y b => Rd l x (Bk a y b))
(fun r =>
match l with
| Bk a y b => lbal (Rd a y b) x r
| Rd a y (Bk b z c) => Rd (lbal (makeRed a) y b) z (Bk c x r)
| _ => Rd l x r
end)
r
(rbalS l x r).
Proof.
exact (rmatch _ _ _).
Qed.
(** ** Balancing for insertion *)
Lemma lbal_spec l x r y :
InT y (lbal l x r) <-> X.eq y x \/ InT y l \/ InT y r.
Proof.
case lbal_match; intuition_in.
Qed.
Instance lbal_ok l x r `(Ok l, Ok r, lt_tree x l, gt_tree x r) :
Ok (lbal l x r).
Proof.
destruct (lbal_match l x r); ok.
Qed.
Lemma rbal_spec l x r y :
InT y (rbal l x r) <-> X.eq y x \/ InT y l \/ InT y r.
Proof.
case rbal_match; intuition_in.
Qed.
Instance rbal_ok l x r `(Ok l, Ok r, lt_tree x l, gt_tree x r) :
Ok (rbal l x r).
Proof.
destruct (rbal_match l x r); ok.
Qed.
Lemma rbal'_spec l x r y :
InT y (rbal' l x r) <-> X.eq y x \/ InT y l \/ InT y r.
Proof.
case rbal'_match; intuition_in.
Qed.
Instance rbal'_ok l x r `(Ok l, Ok r, lt_tree x l, gt_tree x r) :
Ok (rbal' l x r).
Proof.
destruct (rbal'_match l x r); ok.
Qed.
Hint Rewrite In_node_iff In_leaf_iff
makeRed_spec makeBlack_spec lbal_spec rbal_spec rbal'_spec : rb.
Ltac descolor := destruct_all Color.t.
Ltac destree t := destruct t as [|[|] ? ? ?].
Ltac autorew := autorewrite with rb.
Tactic Notation "autorew" "in" ident(H) := autorewrite with rb in H.
(** ** Insertion *)
Lemma ins_spec : forall s x y,
InT y (ins x s) <-> X.eq y x \/ InT y s.
Proof.
induct s x.
- intuition_in.
- intuition_in. setoid_replace y with x; eauto.
- descolor; autorew; rewrite IHl; intuition_in.
- descolor; autorew; rewrite IHr; intuition_in.
Qed.
Hint Rewrite ins_spec : rb.
Instance ins_ok s x `{Ok s} : Ok (ins x s).
Proof.
induct s x; auto; descolor;
(apply lbal_ok || apply rbal_ok || ok); auto;
intros y; autorew; intuition; order.
Qed.
Lemma add_spec' s x y :
InT y (add x s) <-> X.eq y x \/ InT y s.
Proof.
unfold add. now autorew.
Qed.
Hint Rewrite add_spec' : rb.
Lemma add_spec s x y `{Ok s} :
InT y (add x s) <-> X.eq y x \/ InT y s.
Proof.
apply add_spec'.
Qed.
Instance add_ok s x `{Ok s} : Ok (add x s).
Proof.
unfold add; auto_tc.
Qed.
(** ** Balancing for deletion *)
Lemma lbalS_spec l x r y :
InT y (lbalS l x r) <-> X.eq y x \/ InT y l \/ InT y r.
Proof.
case lbalS_match.
- intros; autorew; intuition_in.
- clear l. intros l _.
destruct r as [|[|] rl rx rr].
* autorew. intuition_in.
* destree rl; autorew; intuition_in.
* autorew. intuition_in.
Qed.
Instance lbalS_ok l x r :
forall `(Ok l, Ok r, lt_tree x l, gt_tree x r), Ok (lbalS l x r).
Proof.
case lbalS_match; intros.
- ok.
- destruct r as [|[|] rl rx rr].
* ok.
* destruct rl as [|[|] rll rlx rlr]; intros; ok.
+ apply rbal'_ok; ok.
intros w; autorew; auto.
+ intros w; autorew.
destruct 1 as [Hw|[Hw|Hw]]; try rewrite Hw; eauto.
* ok. autorew. apply rbal'_ok; ok.
Qed.
Lemma rbalS_spec l x r y :
InT y (rbalS l x r) <-> X.eq y x \/ InT y l \/ InT y r.
Proof.
case rbalS_match.
- intros; autorew; intuition_in.
- intros t _.
destruct l as [|[|] ll lx lr].
* autorew. intuition_in.
* destruct lr as [|[|] lrl lrx lrr]; autorew; intuition_in.
* autorew. intuition_in.
Qed.
Instance rbalS_ok l x r :
forall `(Ok l, Ok r, lt_tree x l, gt_tree x r), Ok (rbalS l x r).
Proof.
case rbalS_match; intros.
- ok.
- destruct l as [|[|] ll lx lr].
* ok.
* destruct lr as [|[|] lrl lrx lrr]; intros; ok.
+ apply lbal_ok; ok.
intros w; autorew; auto.
+ intros w; autorew.
destruct 1 as [Hw|[Hw|Hw]]; try rewrite Hw; eauto.
* ok. apply lbal_ok; ok.
Qed.
Hint Rewrite lbalS_spec rbalS_spec : rb.
(** ** Append for deletion *)
Ltac append_tac l r :=
induction l as [| lc ll _ lx lr IHlr];
[intro r; simpl
|induction r as [| rc rl IHrl rx rr _];
[simpl
|destruct lc, rc;
[specialize (IHlr rl); clear IHrl
|simpl;
assert (Hr:notred (Bk rl rx rr)) by (simpl; trivial);
set (r:=Bk rl rx rr) in *; clearbody r; clear IHrl rl rx rr;
specialize (IHlr r)
|change (append _ _) with (Rd (append (Bk ll lx lr) rl) rx rr);
assert (Hl:notred (Bk ll lx lr)) by (simpl; trivial);
set (l:=Bk ll lx lr) in *; clearbody l; clear IHlr ll lx lr
|specialize (IHlr rl); clear IHrl]]].
Fact append_rr_match ll lx lr rl rx rr :
rspec
(fun a x b => Rd (Rd ll lx a) x (Rd b rx rr))
(fun t => Rd ll lx (Rd t rx rr))
(append lr rl)
(append (Rd ll lx lr) (Rd rl rx rr)).
Proof.
exact (rmatch _ _ _).
Qed.
Fact append_bb_match ll lx lr rl rx rr :
rspec
(fun a x b => Rd (Bk ll lx a) x (Bk b rx rr))
(fun t => lbalS ll lx (Bk t rx rr))
(append lr rl)
(append (Bk ll lx lr) (Bk rl rx rr)).
Proof.
exact (rmatch _ _ _).
Qed.
Lemma append_spec l r x :
InT x (append l r) <-> InT x l \/ InT x r.
Proof.
revert r.
append_tac l r; autorew; try tauto.
- (* Red / Red *)
revert IHlr; case append_rr_match;
[intros a y b | intros t Ht]; autorew; tauto.
- (* Black / Black *)
revert IHlr; case append_bb_match;
[intros a y b | intros t Ht]; autorew; tauto.
Qed.
Hint Rewrite append_spec : rb.
Lemma append_ok : forall x l r `{Ok l, Ok r},
lt_tree x l -> gt_tree x r -> Ok (append l r).
Proof.
append_tac l r.
- (* Leaf / _ *)
trivial.
- (* _ / Leaf *)
trivial.
- (* Red / Red *)
intros; inv.
assert (IH : Ok (append lr rl)) by (apply IHlr; eauto). clear IHlr.
assert (X.lt lx rx) by (transitivity x; eauto).
assert (G : gt_tree lx (append lr rl)).
{ intros w. autorew. destruct 1; [|transitivity x]; eauto. }
assert (L : lt_tree rx (append lr rl)).
{ intros w. autorew. destruct 1; [transitivity x|]; eauto. }
revert IH G L; case append_rr_match; intros; ok.
- (* Red / Black *)
intros; ok.
intros w; autorew; destruct 1; eauto.
- (* Black / Red *)
intros; ok.
intros w; autorew; destruct 1; eauto.
- (* Black / Black *)
intros; inv.
assert (IH : Ok (append lr rl)) by (apply IHlr; eauto). clear IHlr.
assert (X.lt lx rx) by (transitivity x; eauto).
assert (G : gt_tree lx (append lr rl)).
{ intros w. autorew. destruct 1; [|transitivity x]; eauto. }
assert (L : lt_tree rx (append lr rl)).
{ intros w. autorew. destruct 1; [transitivity x|]; eauto. }
revert IH G L; case append_bb_match; intros; ok.
apply lbalS_ok; ok.
Qed.
(** ** Deletion *)
Lemma del_spec : forall s x y `{Ok s},
InT y (del x s) <-> InT y s /\ ~X.eq y x.
Proof.
induct s x.
- intuition_in.
- autorew; intuition_in.
assert (X.lt y x') by eauto. order.
assert (X.lt x' y) by eauto. order.
order.
- destruct l as [|[|] ll lx lr]; autorew;
rewrite ?IHl by trivial; intuition_in; order.
- destruct r as [|[|] rl rx rr]; autorew;
rewrite ?IHr by trivial; intuition_in; order.
Qed.
Hint Rewrite del_spec : rb.
Instance del_ok s x `{Ok s} : Ok (del x s).
Proof.
induct s x.
- trivial.
- eapply append_ok; eauto.
- assert (lt_tree x' (del x l)).
{ intro w. autorew; trivial. destruct 1. eauto. }
destruct l as [|[|] ll lx lr]; auto_tc.
- assert (gt_tree x' (del x r)).
{ intro w. autorew; trivial. destruct 1. eauto. }
destruct r as [|[|] rl rx rr]; auto_tc.
Qed.
Lemma remove_spec s x y `{Ok s} :
InT y (remove x s) <-> InT y s /\ ~X.eq y x.
Proof.
unfold remove. now autorew.
Qed.
Hint Rewrite remove_spec : rb.
Instance remove_ok s x `{Ok s} : Ok (remove x s).
Proof.
unfold remove; auto_tc.
Qed.
(** ** Removing the minimal element *)
Lemma delmin_spec l y r c x s' `{O : Ok (Node c l y r)} :
delmin l y r = (x,s') ->
min_elt (Node c l y r) = Some x /\ del x (Node c l y r) = s'.
Proof.
revert y r c x s' O.
induction l as [|lc ll IH ly lr _].
- simpl. intros y r _ x s' _. injection 1; intros; subst.
now rewrite MX.compare_refl.
- intros y r c x s' O.
simpl delmin.
specialize (IH ly lr). destruct delmin as (x0,s0).
destruct (IH lc x0 s0); clear IH; [ok|trivial|].
remember (Node lc ll ly lr) as l.
simpl min_elt in *.
intros E.
replace x0 with x in * by (destruct lc; now injection E).
split.
* subst l; intuition.
* assert (X.lt x y).
{ inversion_clear O.
assert (InT x l) by now apply min_elt_spec1. auto. }
simpl. case X.compare_spec; try order.
destruct lc; injection E; clear E; intros; subst l s0; auto.
Qed.
Lemma remove_min_spec1 s x s' `{Ok s}:
remove_min s = Some (x,s') ->
min_elt s = Some x /\ remove x s = s'.
Proof.
unfold remove_min.
destruct s as [|c l y r]; try easy.
generalize (delmin_spec l y r c).
destruct delmin as (x0,s0). intros D.
destruct (D x0 s0) as (->,<-); auto.
fold (remove x0 (Node c l y r)).
inversion_clear 1; auto.
Qed.
Lemma remove_min_spec2 s : remove_min s = None -> Empty s.
Proof.
unfold remove_min.
destruct s as [|c l y r].
- easy.
- now destruct delmin.
Qed.
Lemma remove_min_ok (s:t) `{Ok s}:
match remove_min s with
| Some (_,s') => Ok s'
| None => True
end.
Proof.
generalize (remove_min_spec1 s).
destruct remove_min as [(x0,s0)|]; auto.
intros R. destruct (R x0 s0); auto. subst s0. auto_tc.
Qed.
(** ** Treeify *)
Notation ifpred p n := (if p then pred n else n%nat).
Definition treeify_invariant size (f:treeify_t) :=
forall acc,
size <= length acc ->
let (t,acc') := f acc in
cardinal t = size /\ acc = elements t ++ acc'.
Lemma treeify_zero_spec : treeify_invariant 0 treeify_zero.
Proof.
intro. simpl. auto.
Qed.
Lemma treeify_one_spec : treeify_invariant 1 treeify_one.
Proof.
intros [|x acc]; simpl; auto; inversion 1.
Qed.
Lemma treeify_cont_spec f g size1 size2 size :
treeify_invariant size1 f ->
treeify_invariant size2 g ->
size = S (size1 + size2) ->
treeify_invariant size (treeify_cont f g).
Proof.
intros Hf Hg EQ acc LE. unfold treeify_cont.
specialize (Hf acc).
destruct (f acc) as (t1,acc1).
destruct Hf as (Hf1,Hf2).
{ transitivity size; trivial. subst. auto with arith. }
destruct acc1 as [|x acc1].
{ exfalso. revert LE. apply Nat.lt_nge. subst.
rewrite <- app_nil_end, <- elements_cardinal; auto with arith. }
specialize (Hg acc1).
destruct (g acc1) as (t2,acc2).
destruct Hg as (Hg1,Hg2).
{ revert LE. subst.
rewrite app_length, <- elements_cardinal. simpl.
rewrite Nat.add_succ_r, <- Nat.succ_le_mono.
apply Nat.add_le_mono_l. }
simpl. rewrite elements_node, app_ass. now subst.
Qed.
Lemma treeify_aux_spec n (p:bool) :
treeify_invariant (ifpred p (Pos.to_nat n)) (treeify_aux p n).
Proof.
revert p.
induction n as [n|n|]; intros p; simpl treeify_aux.
- eapply treeify_cont_spec; [ apply (IHn false) | apply (IHn p) | ].
rewrite Pos2Nat.inj_xI.
assert (H := Pos2Nat.is_pos n). apply Nat.neq_0_lt_0 in H.
destruct p; simpl; intros; rewrite Nat.add_0_r; trivial.
now rewrite <- Nat.add_succ_r, Nat.succ_pred; trivial.
- eapply treeify_cont_spec; [ apply (IHn p) | apply (IHn true) | ].
rewrite Pos2Nat.inj_xO.
assert (H := Pos2Nat.is_pos n). apply Nat.neq_0_lt_0 in H.
rewrite <- Nat.add_succ_r, Nat.succ_pred by trivial.
destruct p; simpl; intros; rewrite Nat.add_0_r; trivial.
symmetry. now apply Nat.add_pred_l.
- destruct p; [ apply treeify_zero_spec | apply treeify_one_spec ].
Qed.
Lemma plength_aux_spec l p :
Pos.to_nat (plength_aux l p) = length l + Pos.to_nat p.
Proof.
revert p. induction l; simpl; trivial.
intros. now rewrite IHl, Pos2Nat.inj_succ, Nat.add_succ_r.
Qed.
Lemma plength_spec l : Pos.to_nat (plength l) = S (length l).
Proof.
unfold plength. rewrite plength_aux_spec. apply Nat.add_1_r.
Qed.
Lemma treeify_elements l : elements (treeify l) = l.
Proof.
assert (H := treeify_aux_spec (plength l) true l).
unfold treeify. destruct treeify_aux as (t,acc); simpl in *.
destruct H as (H,H'). { now rewrite plength_spec. }
subst l. rewrite plength_spec, app_length, <- elements_cardinal in *.
destruct acc.
* now rewrite app_nil_r.
* exfalso. revert H. simpl.
rewrite Nat.add_succ_r, Nat.add_comm.
apply Nat.succ_add_discr.
Qed.
Lemma treeify_spec x l : InT x (treeify l) <-> InA X.eq x l.
Proof.
intros. now rewrite <- elements_spec1, treeify_elements.
Qed.
Lemma treeify_ok l : sort X.lt l -> Ok (treeify l).
Proof.
intros. apply elements_sort_ok. rewrite treeify_elements; auto.
Qed.
(** ** Filter *)
Lemma filter_app A f (l l':list A) :
List.filter f (l ++ l') = List.filter f l ++ List.filter f l'.
Proof.
induction l as [|x l IH]; simpl; trivial.
destruct (f x); simpl; now rewrite IH.
Qed.
Lemma filter_aux_elements s f acc :
filter_aux f s acc = List.filter f (elements s) ++ acc.
Proof.
revert acc.
induction s as [|c l IHl x r IHr]; simpl; trivial.
intros acc.
rewrite elements_node, filter_app. simpl.
destruct (f x); now rewrite IHl, IHr, app_ass.
Qed.
Lemma filter_elements s f :
elements (filter f s) = List.filter f (elements s).
Proof.
unfold filter.
now rewrite treeify_elements, filter_aux_elements, app_nil_r.
Qed.
Lemma filter_spec s x f :
Proper (X.eq==>Logic.eq) f ->
(InT x (filter f s) <-> InT x s /\ f x = true).
Proof.
intros Hf.
rewrite <- elements_spec1, filter_elements, filter_InA, elements_spec1;
now auto_tc.
Qed.
Instance filter_ok s f `(Ok s) : Ok (filter f s).
Proof.
apply elements_sort_ok.
rewrite filter_elements.
apply filter_sort with X.eq; auto_tc.
Qed.
(** ** Partition *)
Lemma partition_aux_spec s f acc1 acc2 :
partition_aux f s acc1 acc2 =
(filter_aux f s acc1, filter_aux (fun x => negb (f x)) s acc2).
Proof.
revert acc1 acc2.
induction s as [ | c l Hl x r Hr ]; simpl.
- trivial.
- intros acc1 acc2.
destruct (f x); simpl; now rewrite Hr, Hl.
Qed.
Lemma partition_spec s f :
partition f s = (filter f s, filter (fun x => negb (f x)) s).
Proof.
unfold partition, filter. now rewrite partition_aux_spec.
Qed.
Lemma partition_spec1 s f :
Proper (X.eq==>Logic.eq) f ->
Equal (fst (partition f s)) (filter f s).
Proof. now rewrite partition_spec. Qed.
Lemma partition_spec2 s f :
Proper (X.eq==>Logic.eq) f ->
Equal (snd (partition f s)) (filter (fun x => negb (f x)) s).
Proof. now rewrite partition_spec. Qed.
Instance partition_ok1 s f `(Ok s) : Ok (fst (partition f s)).
Proof. rewrite partition_spec; now apply filter_ok. Qed.
Instance partition_ok2 s f `(Ok s) : Ok (snd (partition f s)).
Proof. rewrite partition_spec; now apply filter_ok. Qed.
(** ** An invariant for binary list functions with accumulator. *)
Ltac inA :=
rewrite ?InA_app_iff, ?InA_cons, ?InA_nil, ?InA_rev in *; auto_tc.
Record INV l1 l2 acc : Prop := {
l1_sorted : sort X.lt (rev l1);
l2_sorted : sort X.lt (rev l2);
acc_sorted : sort X.lt acc;
l1_lt_acc x y : InA X.eq x l1 -> InA X.eq y acc -> X.lt x y;
l2_lt_acc x y : InA X.eq x l2 -> InA X.eq y acc -> X.lt x y}.
Local Hint Resolve l1_sorted l2_sorted acc_sorted.
Lemma INV_init s1 s2 `(Ok s1, Ok s2) :
INV (rev_elements s1) (rev_elements s2) nil.
Proof.
rewrite !rev_elements_rev.
split; rewrite ?rev_involutive; auto; intros; now inA.
Qed.
Lemma INV_sym l1 l2 acc : INV l1 l2 acc -> INV l2 l1 acc.
Proof.
destruct 1; now split.
Qed.
Lemma INV_drop x1 l1 l2 acc :
INV (x1 :: l1) l2 acc -> INV l1 l2 acc.
Proof.
intros (l1s,l2s,accs,l1a,l2a). simpl in *.
destruct (sorted_app_inv _ _ l1s) as (U & V & W); auto.
split; auto.
Qed.
Lemma INV_eq x1 x2 l1 l2 acc :
INV (x1 :: l1) (x2 :: l2) acc -> X.eq x1 x2 ->
INV l1 l2 (x1 :: acc).
Proof.
intros (U,V,W,X,Y) EQ. simpl in *.
destruct (sorted_app_inv _ _ U) as (U1 & U2 & U3); auto.
destruct (sorted_app_inv _ _ V) as (V1 & V2 & V3); auto.
split; auto.
- constructor; auto. apply InA_InfA with X.eq; auto_tc.
- intros x y; inA; intros Hx [Hy|Hy].
+ apply U3; inA.
+ apply X; inA.
- intros x y; inA; intros Hx [Hy|Hy].
+ rewrite Hy, EQ; apply V3; inA.
+ apply Y; inA.
Qed.
Lemma INV_lt x1 x2 l1 l2 acc :
INV (x1 :: l1) (x2 :: l2) acc -> X.lt x1 x2 ->
INV (x1 :: l1) l2 (x2 :: acc).
Proof.
intros (U,V,W,X,Y) EQ. simpl in *.
destruct (sorted_app_inv _ _ U) as (U1 & U2 & U3); auto.
destruct (sorted_app_inv _ _ V) as (V1 & V2 & V3); auto.
split; auto.
- constructor; auto. apply InA_InfA with X.eq; auto_tc.
- intros x y; inA; intros Hx [Hy|Hy].
+ rewrite Hy; clear Hy. destruct Hx; [order|].
transitivity x1; auto. apply U3; inA.
+ apply X; inA.
- intros x y; inA; intros Hx [Hy|Hy].
+ rewrite Hy. apply V3; inA.
+ apply Y; inA.
Qed.
Lemma INV_rev l1 l2 acc :
INV l1 l2 acc -> Sorted X.lt (rev_append l1 acc).
Proof.
intros. rewrite rev_append_rev.
apply SortA_app with X.eq; eauto with *.
intros x y. inA. eapply l1_lt_acc; eauto.
Qed.
(** ** union *)
Lemma union_list_ok l1 l2 acc :
INV l1 l2 acc -> sort X.lt (union_list l1 l2 acc).
Proof.
revert l2 acc.
induction l1 as [|x1 l1 IH1];
[intro l2|induction l2 as [|x2 l2 IH2]];
intros acc inv.
- eapply INV_rev, INV_sym; eauto.
- eapply INV_rev; eauto.
- simpl. case X.compare_spec; intro C.
* apply IH1. eapply INV_eq; eauto.
* apply (IH2 (x2::acc)). eapply INV_lt; eauto.
* apply IH1. eapply INV_sym, INV_lt; eauto. now apply INV_sym.
Qed.
Instance linear_union_ok s1 s2 `(Ok s1, Ok s2) :
Ok (linear_union s1 s2).
Proof.
unfold linear_union. now apply treeify_ok, union_list_ok, INV_init.
Qed.
Instance fold_add_ok s1 s2 `(Ok s1, Ok s2) :
Ok (fold add s1 s2).
Proof.
rewrite fold_spec, <- fold_left_rev_right.
unfold elt in *.
induction (rev (elements s1)); simpl; unfold flip in *; auto_tc.
Qed.
Instance union_ok s1 s2 `(Ok s1, Ok s2) : Ok (union s1 s2).
Proof.
unfold union. destruct compare_height; auto_tc.
Qed.
Lemma union_list_spec x l1 l2 acc :
InA X.eq x (union_list l1 l2 acc) <->
InA X.eq x l1 \/ InA X.eq x l2 \/ InA X.eq x acc.
Proof.
revert l2 acc.
induction l1 as [|x1 l1 IH1].
- intros l2 acc; simpl. rewrite rev_append_rev. inA. tauto.
- induction l2 as [|x2 l2 IH2]; intros acc; simpl.
* rewrite rev_append_rev. inA. tauto.
* case X.compare_spec; intro C.
+ rewrite IH1, !InA_cons, C; tauto.
+ rewrite (IH2 (x2::acc)), !InA_cons. tauto.
+ rewrite IH1, !InA_cons; tauto.
Qed.
Lemma linear_union_spec s1 s2 x :
InT x (linear_union s1 s2) <-> InT x s1 \/ InT x s2.
Proof.
unfold linear_union.
rewrite treeify_spec, union_list_spec, !rev_elements_rev.
rewrite !InA_rev, InA_nil, !elements_spec1 by auto_tc.
tauto.
Qed.
Lemma fold_add_spec s1 s2 x :
InT x (fold add s1 s2) <-> InT x s1 \/ InT x s2.
Proof.
rewrite fold_spec, <- fold_left_rev_right.
rewrite <- (elements_spec1 s1), <- InA_rev by auto_tc.
unfold elt in *.
induction (rev (elements s1)); simpl.
- rewrite InA_nil. tauto.
- unfold flip. rewrite add_spec', IHl, InA_cons. tauto.
Qed.
Lemma union_spec' s1 s2 x :
InT x (union s1 s2) <-> InT x s1 \/ InT x s2.
Proof.
unfold union. destruct compare_height.
- apply linear_union_spec.
- apply fold_add_spec.
- rewrite fold_add_spec. tauto.
Qed.
Lemma union_spec : forall s1 s2 y `{Ok s1, Ok s2},
(InT y (union s1 s2) <-> InT y s1 \/ InT y s2).
Proof.
intros; apply union_spec'.
Qed.
(** ** inter *)
Lemma inter_list_ok l1 l2 acc :
INV l1 l2 acc -> sort X.lt (inter_list l1 l2 acc).
Proof.
revert l2 acc.
induction l1 as [|x1 l1 IH1]; [|induction l2 as [|x2 l2 IH2]]; simpl.
- eauto.
- eauto.
- intros acc inv.
case X.compare_spec; intro C.
* apply IH1. eapply INV_eq; eauto.
* apply (IH2 acc). eapply INV_sym, INV_drop, INV_sym; eauto.
* apply IH1. eapply INV_drop; eauto.
Qed.
Instance linear_inter_ok s1 s2 `(Ok s1, Ok s2) :
Ok (linear_inter s1 s2).
Proof.
unfold linear_inter. now apply treeify_ok, inter_list_ok, INV_init.
Qed.
Instance inter_ok s1 s2 `(Ok s1, Ok s2) : Ok (inter s1 s2).
Proof.
unfold inter. destruct compare_height; auto_tc.
Qed.
Lemma inter_list_spec x l1 l2 acc :
sort X.lt (rev l1) ->
sort X.lt (rev l2) ->
(InA X.eq x (inter_list l1 l2 acc) <->
(InA X.eq x l1 /\ InA X.eq x l2) \/ InA X.eq x acc).
Proof.
revert l2 acc.
induction l1 as [|x1 l1 IH1].
- intros l2 acc; simpl. inA. tauto.
- induction l2 as [|x2 l2 IH2]; intros acc.
* simpl. inA. tauto.
* simpl. intros U V.
destruct (sorted_app_inv _ _ U) as (U1 & U2 & U3); auto.
destruct (sorted_app_inv _ _ V) as (V1 & V2 & V3); auto.
case X.compare_spec; intro C.
+ rewrite IH1, !InA_cons, C; tauto.
+ rewrite (IH2 acc); auto. inA. intuition; try order.
assert (X.lt x x1) by (apply U3; inA). order.
+ rewrite IH1; auto. inA. intuition; try order.
assert (X.lt x x2) by (apply V3; inA). order.
Qed.
Lemma linear_inter_spec s1 s2 x `(Ok s1, Ok s2) :
InT x (linear_inter s1 s2) <-> InT x s1 /\ InT x s2.
Proof.
unfold linear_inter.
rewrite !rev_elements_rev, treeify_spec, inter_list_spec
by (rewrite rev_involutive; auto_tc).
rewrite !InA_rev, InA_nil, !elements_spec1 by auto_tc. tauto.
Qed.
Local Instance mem_proper s `(Ok s) :
Proper (X.eq ==> Logic.eq) (fun k => mem k s).
Proof.
intros x y EQ. apply Bool.eq_iff_eq_true; rewrite !mem_spec; auto.
now rewrite EQ.
Qed.
Lemma inter_spec s1 s2 y `{Ok s1, Ok s2} :
InT y (inter s1 s2) <-> InT y s1 /\ InT y s2.
Proof.
unfold inter. destruct compare_height.
- now apply linear_inter_spec.
- rewrite filter_spec, mem_spec by auto_tc; tauto.
- rewrite filter_spec, mem_spec by auto_tc; tauto.
Qed.
(** ** difference *)
Lemma diff_list_ok l1 l2 acc :
INV l1 l2 acc -> sort X.lt (diff_list l1 l2 acc).
Proof.
revert l2 acc.
induction l1 as [|x1 l1 IH1];
[intro l2|induction l2 as [|x2 l2 IH2]];
intros acc inv.
- eauto.
- unfold diff_list. eapply INV_rev; eauto.
- simpl. case X.compare_spec; intro C.
* apply IH1. eapply INV_drop, INV_sym, INV_drop, INV_sym; eauto.
* apply (IH2 acc). eapply INV_sym, INV_drop, INV_sym; eauto.
* apply IH1. eapply INV_sym, INV_lt; eauto. now apply INV_sym.
Qed.
Instance diff_inter_ok s1 s2 `(Ok s1, Ok s2) :
Ok (linear_diff s1 s2).
Proof.
unfold linear_inter. now apply treeify_ok, diff_list_ok, INV_init.
Qed.
Instance fold_remove_ok s1 s2 `(Ok s2) :
Ok (fold remove s1 s2).
Proof.
rewrite fold_spec, <- fold_left_rev_right.
unfold elt in *.
induction (rev (elements s1)); simpl; unfold flip in *; auto_tc.
Qed.
Instance diff_ok s1 s2 `(Ok s1, Ok s2) : Ok (diff s1 s2).
Proof.
unfold diff. destruct compare_height; auto_tc.
Qed.
Lemma diff_list_spec x l1 l2 acc :
sort X.lt (rev l1) ->
sort X.lt (rev l2) ->
(InA X.eq x (diff_list l1 l2 acc) <->
(InA X.eq x l1 /\ ~InA X.eq x l2) \/ InA X.eq x acc).
Proof.
revert l2 acc.
induction l1 as [|x1 l1 IH1].
- intros l2 acc; simpl. inA. tauto.
- induction l2 as [|x2 l2 IH2]; intros acc.
* intros; simpl. rewrite rev_append_rev. inA. tauto.
* simpl. intros U V.
destruct (sorted_app_inv _ _ U) as (U1 & U2 & U3); auto.
destruct (sorted_app_inv _ _ V) as (V1 & V2 & V3); auto.
case X.compare_spec; intro C.
+ rewrite IH1; auto. f_equiv. inA. intuition; try order.
assert (X.lt x x1) by (apply U3; inA). order.
+ rewrite (IH2 acc); auto. f_equiv. inA. intuition; try order.
assert (X.lt x x1) by (apply U3; inA). order.
+ rewrite IH1; auto. inA. intuition; try order.
left; split; auto. destruct 1. order.
assert (X.lt x x2) by (apply V3; inA). order.
Qed.
Lemma linear_diff_spec s1 s2 x `(Ok s1, Ok s2) :
InT x (linear_diff s1 s2) <-> InT x s1 /\ ~InT x s2.
Proof.
unfold linear_diff.
rewrite !rev_elements_rev, treeify_spec, diff_list_spec
by (rewrite rev_involutive; auto_tc).
rewrite !InA_rev, InA_nil, !elements_spec1 by auto_tc. tauto.
Qed.
Lemma fold_remove_spec s1 s2 x `(Ok s2) :
InT x (fold remove s1 s2) <-> InT x s2 /\ ~InT x s1.
Proof.
rewrite fold_spec, <- fold_left_rev_right.
rewrite <- (elements_spec1 s1), <- InA_rev by auto_tc.
unfold elt in *.
induction (rev (elements s1)); simpl; intros.
- rewrite InA_nil. intuition.
- unfold flip in *. rewrite remove_spec, IHl, InA_cons. tauto.
clear IHl. induction l; simpl; auto_tc.
Qed.
Lemma diff_spec s1 s2 y `{Ok s1, Ok s2} :
InT y (diff s1 s2) <-> InT y s1 /\ ~InT y s2.
Proof.
unfold diff. destruct compare_height.
- now apply linear_diff_spec.
- rewrite filter_spec, Bool.negb_true_iff,
<- Bool.not_true_iff_false, mem_spec;
intuition.
intros x1 x2 EQ. f_equal. now apply mem_proper.
- now apply fold_remove_spec.
Qed.
End MakeRaw.
(** * Balancing properties
We now prove that all operations preserve a red-black invariant,
and that trees have hence a logarithmic depth.
*)
Module BalanceProps(X:Orders.OrderedType)(Import M : MakeRaw X).
Local Notation Rd := (Node Red).
Local Notation Bk := (Node Black).
Import M.MX.
(** ** Red-Black invariants *)
(** In a red-black tree :
- a red node has no red children
- the black depth at each node is the same along all paths.
The black depth is here an argument of the predicate. *)
Inductive rbt : nat -> tree -> Prop :=
| RB_Leaf : rbt 0 Leaf
| RB_Rd n l k r :
notred l -> notred r -> rbt n l -> rbt n r -> rbt n (Rd l k r)
| RB_Bk n l k r : rbt n l -> rbt n r -> rbt (S n) (Bk l k r).
(** A red-red tree is almost a red-black tree, except that it has
a _red_ root node which _may_ have red children. Note that a
red-red tree is hence non-empty, and all its strict subtrees
are red-black. *)
Inductive rrt (n:nat) : tree -> Prop :=
| RR_Rd l k r : rbt n l -> rbt n r -> rrt n (Rd l k r).
(** An almost-red-black tree is almost a red-black tree, except that
it's permitted to have two red nodes in a row at the very root (only).
We implement this notion by saying that a quasi-red-black tree
is either a red-black tree or a red-red tree. *)
Inductive arbt (n:nat)(t:tree) : Prop :=
| ARB_RB : rbt n t -> arbt n t
| ARB_RR : rrt n t -> arbt n t.
(** The main exported invariant : being a red-black tree for some
black depth. *)
Class Rbt (t:tree) := RBT : exists d, rbt d t.
(** ** Basic tactics and results about red-black *)
Scheme rbt_ind := Induction for rbt Sort Prop.
Local Hint Constructors rbt rrt arbt.
Local Hint Extern 0 (notred _) => (exact I).
Ltac invrb := intros; invtree rrt; invtree rbt; try contradiction.
Ltac desarb := match goal with H:arbt _ _ |- _ => destruct H end.
Ltac nonzero n := destruct n as [|n]; [try split; invrb|].
Lemma rr_nrr_rb n t :
rrt n t -> notredred t -> rbt n t.
Proof.
destruct 1 as [l x r Hl Hr].
destruct l, r; descolor; invrb; auto.
Qed.
Local Hint Resolve rr_nrr_rb.
Lemma arb_nrr_rb n t :
arbt n t -> notredred t -> rbt n t.
Proof.
destruct 1; auto.
Qed.
Lemma arb_nr_rb n t :
arbt n t -> notred t -> rbt n t.
Proof.
destruct 1; destruct t; descolor; invrb; auto.
Qed.
Local Hint Resolve arb_nrr_rb arb_nr_rb.
(** ** A Red-Black tree has indeed a logarithmic depth *)
Definition redcarac s := rcase (fun _ _ _ => 1) (fun _ => 0) s.
Lemma rb_maxdepth s n : rbt n s -> maxdepth s <= 2*n + redcarac s.
Proof.
induction 1.
- simpl; auto.
- replace (redcarac l) with 0 in * by now destree l.
replace (redcarac r) with 0 in * by now destree r.
simpl maxdepth. simpl redcarac.
rewrite Nat.add_succ_r, <- Nat.succ_le_mono.
now apply Nat.max_lub.
- simpl. rewrite <- Nat.succ_le_mono.
apply Nat.max_lub; eapply Nat.le_trans; eauto;
[destree l | destree r]; simpl;
rewrite !Nat.add_0_r, ?Nat.add_1_r; auto with arith.
Qed.
Lemma rb_mindepth s n : rbt n s -> n + redcarac s <= mindepth s.
Proof.
induction 1; simpl.
- trivial.
- rewrite Nat.add_succ_r.
apply -> Nat.succ_le_mono.
replace (redcarac l) with 0 in * by now destree l.
replace (redcarac r) with 0 in * by now destree r.
now apply Nat.min_glb.
- apply -> Nat.succ_le_mono. rewrite Nat.add_0_r.
apply Nat.min_glb; eauto with arith.
Qed.
Lemma maxdepth_upperbound s : Rbt s ->
maxdepth s <= 2 * log2 (S (cardinal s)).
Proof.
intros (n,H).
eapply Nat.le_trans; [eapply rb_maxdepth; eauto|].
transitivity (2*(n+redcarac s)).
- rewrite Nat.mul_add_distr_l. apply Nat.add_le_mono_l.
rewrite <- Nat.mul_1_l at 1. apply Nat.mul_le_mono_r.
auto with arith.
- apply Nat.mul_le_mono_l.
transitivity (mindepth s).
+ now apply rb_mindepth.
+ apply mindepth_log_cardinal.
Qed.
Lemma maxdepth_lowerbound s : s<>Leaf ->
log2 (cardinal s) < maxdepth s.
Proof.
apply maxdepth_log_cardinal.
Qed.
(** ** Singleton *)
Lemma singleton_rb x : Rbt (singleton x).
Proof.
unfold singleton. exists 1; auto.
Qed.
(** ** [makeBlack] and [makeRed] *)
Lemma makeBlack_rb n t : arbt n t -> Rbt (makeBlack t).
Proof.
destruct t as [|[|] l x r].
- exists 0; auto.
- destruct 1; invrb; exists (S n); simpl; auto.
- exists n; auto.
Qed.
Lemma makeRed_rr t n :
rbt (S n) t -> notred t -> rrt n (makeRed t).
Proof.
destruct t as [|[|] l x r]; invrb; simpl; auto.
Qed.
(** ** Balancing *)
Lemma lbal_rb n l k r :
arbt n l -> rbt n r -> rbt (S n) (lbal l k r).
Proof.
case lbal_match; intros; desarb; invrb; auto.
Qed.
Lemma rbal_rb n l k r :
rbt n l -> arbt n r -> rbt (S n) (rbal l k r).
Proof.
case rbal_match; intros; desarb; invrb; auto.
Qed.
Lemma rbal'_rb n l k r :
rbt n l -> arbt n r -> rbt (S n) (rbal' l k r).
Proof.
case rbal'_match; intros; desarb; invrb; auto.
Qed.
Lemma lbalS_rb n l x r :
arbt n l -> rbt (S n) r -> notred r -> rbt (S n) (lbalS l x r).
Proof.
intros Hl Hr Hr'.
destruct r as [|[|] rl rx rr]; invrb. clear Hr'.
revert Hl.
case lbalS_match.
- destruct 1; invrb; auto.
- intros. apply rbal'_rb; auto.
Qed.
Lemma lbalS_arb n l x r :
arbt n l -> rbt (S n) r -> arbt (S n) (lbalS l x r).
Proof.
case lbalS_match.
- destruct 1; invrb; auto.
- clear l. intros l Hl Hl' Hr.
destruct r as [|[|] rl rx rr]; invrb.
* destruct rl as [|[|] rll rlx rlr]; invrb.
right; auto using rbal'_rb, makeRed_rr.
* left; apply rbal'_rb; auto.
Qed.
Lemma rbalS_rb n l x r :
rbt (S n) l -> notred l -> arbt n r -> rbt (S n) (rbalS l x r).
Proof.
intros Hl Hl' Hr.
destruct l as [|[|] ll lx lr]; invrb. clear Hl'.
revert Hr.
case rbalS_match.
- destruct 1; invrb; auto.
- intros. apply lbal_rb; auto.
Qed.
Lemma rbalS_arb n l x r :
rbt (S n) l -> arbt n r -> arbt (S n) (rbalS l x r).
Proof.
case rbalS_match.
- destruct 2; invrb; auto.
- clear r. intros r Hr Hr' Hl.
destruct l as [|[|] ll lx lr]; invrb.
* destruct lr as [|[|] lrl lrx lrr]; invrb.
right; auto using lbal_rb, makeRed_rr.
* left; apply lbal_rb; auto.
Qed.
(** ** Insertion *)
(** The next lemmas combine simultaneous results about rbt and arbt.
A first solution here: statement with [if ... then ... else] *)
Definition ifred s (A B:Prop) := rcase (fun _ _ _ => A) (fun _ => B) s.
Lemma ifred_notred s A B : notred s -> (ifred s A B <-> B).
Proof.
destruct s; descolor; simpl; intuition.
Qed.
Lemma ifred_or s A B : ifred s A B -> A\/B.
Proof.
destruct s; descolor; simpl; intuition.
Qed.
Lemma ins_rr_rb x s n : rbt n s ->
ifred s (rrt n (ins x s)) (rbt n (ins x s)).
Proof.
induction 1 as [ | n l k r | n l k r Hl IHl Hr IHr ].
- simpl; auto.
- simpl. rewrite ifred_notred in * by trivial.
elim_compare x k; auto.
- rewrite ifred_notred by trivial.
unfold ins; fold ins. (* simpl is too much here ... *)
elim_compare x k.
* auto.
* apply lbal_rb; trivial. apply ifred_or in IHl; intuition.
* apply rbal_rb; trivial. apply ifred_or in IHr; intuition.
Qed.
Lemma ins_arb x s n : rbt n s -> arbt n (ins x s).
Proof.
intros H. apply (ins_rr_rb x), ifred_or in H. intuition.
Qed.
Instance add_rb x s : Rbt s -> Rbt (add x s).
Proof.
intros (n,H). unfold add. now apply (makeBlack_rb n), ins_arb.
Qed.
(** ** Deletion *)
(** A second approach here: statement with ... /\ ... *)
Lemma append_arb_rb n l r : rbt n l -> rbt n r ->
(arbt n (append l r)) /\
(notred l -> notred r -> rbt n (append l r)).
Proof.
revert r n.
append_tac l r.
- split; auto.
- split; auto.
- (* Red / Red *)
intros n. invrb.
case (IHlr n); auto; clear IHlr.
case append_rr_match.
+ intros a x b _ H; split; invrb.
assert (rbt n (Rd a x b)) by auto. invrb. auto.
+ split; invrb; auto.
- (* Red / Black *)
split; invrb. destruct (IHlr n) as (_,IH); auto.
- (* Black / Red *)
split; invrb. destruct (IHrl n) as (_,IH); auto.
- (* Black / Black *)
nonzero n.
invrb.
destruct (IHlr n) as (IH,_); auto; clear IHlr.
revert IH.
case append_bb_match.
+ intros a x b IH; split; destruct IH; invrb; auto.
+ split; [left | invrb]; auto using lbalS_rb.
Qed.
(** A third approach : Lemma ... with ... *)
Lemma del_arb s x n : rbt (S n) s -> isblack s -> arbt n (del x s)
with del_rb s x n : rbt n s -> notblack s -> rbt n (del x s).
Proof.
{ revert n.
induct s x; try destruct c; try contradiction; invrb.
- apply append_arb_rb; assumption.
- assert (IHl' := del_rb l x). clear IHr del_arb del_rb.
destruct l as [|[|] ll lx lr]; auto.
nonzero n. apply lbalS_arb; auto.
- assert (IHr' := del_rb r x). clear IHl del_arb del_rb.
destruct r as [|[|] rl rx rr]; auto.
nonzero n. apply rbalS_arb; auto. }
{ revert n.
induct s x; try assumption; try destruct c; try contradiction; invrb.
- apply append_arb_rb; assumption.
- assert (IHl' := del_arb l x). clear IHr del_arb del_rb.
destruct l as [|[|] ll lx lr]; auto.
nonzero n. destruct n as [|n]; [invrb|]; apply lbalS_rb; auto.
- assert (IHr' := del_arb r x). clear IHl del_arb del_rb.
destruct r as [|[|] rl rx rr]; auto.
nonzero n. apply rbalS_rb; auto. }
Qed.
Instance remove_rb s x : Rbt s -> Rbt (remove x s).
Proof.
intros (n,H). unfold remove.
destruct s as [|[|] l y r].
- apply (makeBlack_rb n). auto.
- apply (makeBlack_rb n). left. apply del_rb; simpl; auto.
- nonzero n. apply (makeBlack_rb n). apply del_arb; simpl; auto.
Qed.
(** ** Treeify *)
Definition treeify_rb_invariant size depth (f:treeify_t) :=
forall acc,
size <= length acc ->
rbt depth (fst (f acc)) /\
size + length (snd (f acc)) = length acc.
Lemma treeify_zero_rb : treeify_rb_invariant 0 0 treeify_zero.
Proof.
intros acc _; simpl; auto.
Qed.
Lemma treeify_one_rb : treeify_rb_invariant 1 0 treeify_one.
Proof.
intros [|x acc]; simpl; auto; inversion 1.
Qed.
Lemma treeify_cont_rb f g size1 size2 size d :
treeify_rb_invariant size1 d f ->
treeify_rb_invariant size2 d g ->
size = S (size1 + size2) ->
treeify_rb_invariant size (S d) (treeify_cont f g).
Proof.
intros Hf Hg H acc Hacc.
unfold treeify_cont.
specialize (Hf acc).
destruct (f acc) as (l, acc1). simpl in *.
destruct Hf as (Hf1, Hf2). { subst. eauto with arith. }
destruct acc1 as [|x acc2]; simpl in *.
- exfalso. revert Hacc. apply Nat.lt_nge. rewrite H, <- Hf2.
auto with arith.
- specialize (Hg acc2).
destruct (g acc2) as (r, acc3). simpl in *.
destruct Hg as (Hg1, Hg2).
{ revert Hacc.
rewrite H, <- Hf2, Nat.add_succ_r, <- Nat.succ_le_mono.
apply Nat.add_le_mono_l. }
split; auto.
now rewrite H, <- Hf2, <- Hg2, Nat.add_succ_r, Nat.add_assoc.
Qed.
Lemma treeify_aux_rb n :
exists d, forall (b:bool),
treeify_rb_invariant (ifpred b (Pos.to_nat n)) d (treeify_aux b n).
Proof.
induction n as [n (d,IHn)|n (d,IHn)| ].
- exists (S d). intros b.
eapply treeify_cont_rb; [ apply (IHn false) | apply (IHn b) | ].
rewrite Pos2Nat.inj_xI.
assert (H := Pos2Nat.is_pos n). apply Nat.neq_0_lt_0 in H.
destruct b; simpl; intros; rewrite Nat.add_0_r; trivial.
now rewrite <- Nat.add_succ_r, Nat.succ_pred; trivial.
- exists (S d). intros b.
eapply treeify_cont_rb; [ apply (IHn b) | apply (IHn true) | ].
rewrite Pos2Nat.inj_xO.
assert (H := Pos2Nat.is_pos n). apply Nat.neq_0_lt_0 in H.
rewrite <- Nat.add_succ_r, Nat.succ_pred by trivial.
destruct b; simpl; intros; rewrite Nat.add_0_r; trivial.
symmetry. now apply Nat.add_pred_l.
- exists 0; destruct b;
[ apply treeify_zero_rb | apply treeify_one_rb ].
Qed.
(** The black depth of [treeify l] is actually a log2, but
we don't need to mention that. *)
Instance treeify_rb l : Rbt (treeify l).
Proof.
unfold treeify.
destruct (treeify_aux_rb (plength l)) as (d,H).
exists d.
apply H.
now rewrite plength_spec.
Qed.
(** ** Filtering *)
Instance filter_rb f s : Rbt (filter f s).
Proof.
unfold filter; auto_tc.
Qed.
Instance partition_rb1 f s : Rbt (fst (partition f s)).
Proof.
unfold partition. destruct partition_aux. simpl. auto_tc.
Qed.
Instance partition_rb2 f s : Rbt (snd (partition f s)).
Proof.
unfold partition. destruct partition_aux. simpl. auto_tc.
Qed.
(** ** Union, intersection, difference *)
Instance fold_add_rb s1 s2 : Rbt s2 -> Rbt (fold add s1 s2).
Proof.
intros. rewrite fold_spec, <- fold_left_rev_right. unfold elt in *.
induction (rev (elements s1)); simpl; unfold flip in *; auto_tc.
Qed.
Instance fold_remove_rb s1 s2 : Rbt s2 -> Rbt (fold remove s1 s2).
Proof.
intros. rewrite fold_spec, <- fold_left_rev_right. unfold elt in *.
induction (rev (elements s1)); simpl; unfold flip in *; auto_tc.
Qed.
Lemma union_rb s1 s2 : Rbt s1 -> Rbt s2 -> Rbt (union s1 s2).
Proof.
intros. unfold union, linear_union. destruct compare_height; auto_tc.
Qed.
Lemma inter_rb s1 s2 : Rbt s1 -> Rbt s2 -> Rbt (inter s1 s2).
Proof.
intros. unfold inter, linear_inter. destruct compare_height; auto_tc.
Qed.
Lemma diff_rb s1 s2 : Rbt s1 -> Rbt s2 -> Rbt (diff s1 s2).
Proof.
intros. unfold diff, linear_diff. destruct compare_height; auto_tc.
Qed.
End BalanceProps.
(** * Final Encapsulation
Now, in order to really provide a functor implementing [S], we
need to encapsulate everything into a type of binary search trees.
They also happen to be well-balanced, but this has no influence
on the correctness of operations, so we won't state this here,
see [BalanceProps] if you need more than just the MSet interface.
*)
Module Type MSetInterface_S_Ext := MSetInterface.S <+ MSetRemoveMin.
Module Make (X: Orders.OrderedType) <:
MSetInterface_S_Ext with Module E := X.
Module Raw. Include MakeRaw X. End Raw.
Include MSetInterface.Raw2Sets X Raw.
Definition opt_ok (x:option (elt * Raw.t)) :=
match x with Some (_,s) => Raw.Ok s | None => True end.
Definition mk_opt_t (x: option (elt * Raw.t))(P: opt_ok x) :
option (elt * t) :=
match x as o return opt_ok o -> option (elt * t) with
| Some (k,s') => fun P : Raw.Ok s' => Some (k, Mkt s')
| None => fun _ => None
end P.
Definition remove_min s : option (elt * t) :=
mk_opt_t (Raw.remove_min (this s)) (Raw.remove_min_ok s).
Lemma remove_min_spec1 s x s' :
remove_min s = Some (x,s') ->
min_elt s = Some x /\ Equal (remove x s) s'.
Proof.
destruct s as (s,Hs).
unfold remove_min, mk_opt_t, min_elt, remove, Equal, In; simpl.
generalize (fun x s' => @Raw.remove_min_spec1 s x s' Hs).
set (P := Raw.remove_min_ok s). clearbody P.
destruct (Raw.remove_min s) as [(x0,s0)|]; try easy.
intros H U. injection U. clear U; intros; subst. simpl.
destruct (H x s0); auto. subst; intuition.
Qed.
Lemma remove_min_spec2 s : remove_min s = None -> Empty s.
Proof.
destruct s as (s,Hs).
unfold remove_min, mk_opt_t, Empty, In; simpl.
generalize (Raw.remove_min_spec2 s).
set (P := Raw.remove_min_ok s). clearbody P.
destruct (Raw.remove_min s) as [(x0,s0)|]; now intuition.
Qed.
End Make.
|
/**********************************************************************
* $my_monitor example -- Verilog HDL test bench.
*
* Verilog test bench to test the $my_monitor PLI application.
*
* For the book, "The Verilog PLI Handbook" by Stuart Sutherland
* Copyright 1999 & 2001, Kluwer Academic Publishers, Norwell, MA, USA
* Contact: www.wkap.il
* Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
* Contact: www.sutherland-hdl.com
*********************************************************************/
`timescale 1ns / 1ns
module test;
reg a, b, ci, clk;
wire sum, co;
addbit i1 (a, b, ci, sum, co);
initial
$my_monitor(i1);
initial
begin
#0 a = 0;
#0 b = 0;
#0 ci = 0;
#10 a = 1;
#10 a = 0;
#10 b = 1;
#10 a = 1;
#10 $finish(0);
end
endmodule
/*** A gate level 1 bit adder model ***/
`timescale 1ns / 1ns
module addbit (a, b, ci, sum, co);
input a, b, ci;
output sum, co;
wire a, b, ci, sum, co,
n1, n2, n3;
/*
assign n1 = a ^ b;
assign sum = n1 ^ ci;
assign n2 = a & b;
assign n3 = n1 & ci;
assign co = n2 | n3;
*/
// Gate delays are used to ensure the signal changes occur in a
// defined order.
xor #1 (n1, a, b);
and #2 (n2, a, b);
and #3 (n3, n1, ci);
xor #4 (sum, n1, ci);
or #4 (co, n2, n3);
endmodule
/*********************************************************************/
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DLRTN_4_V
`define SKY130_FD_SC_HDLL__DLRTN_4_V
/**
* dlrtn: Delay latch, inverted reset, inverted enable, single output.
*
* Verilog wrapper for dlrtn with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__dlrtn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__dlrtn_4 (
Q ,
RESET_B,
D ,
GATE_N ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input RESET_B;
input D ;
input GATE_N ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__dlrtn base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE_N(GATE_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__dlrtn_4 (
Q ,
RESET_B,
D ,
GATE_N
);
output Q ;
input RESET_B;
input D ;
input GATE_N ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__dlrtn base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE_N(GATE_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DLRTN_4_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__OR2_BLACKBOX_V
`define SKY130_FD_SC_HVL__OR2_BLACKBOX_V
/**
* or2: 2-input OR.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__or2 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__OR2_BLACKBOX_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2013(c) Analog Devices, Inc.
// Author: Lars-Peter Clausen <[email protected]>
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
module util_axis_resize (
input clk,
input resetn,
input s_valid,
output s_ready,
input [C_S_DATA_WIDTH-1:0] s_data,
output m_valid,
input m_ready,
output [C_M_DATA_WIDTH-1:0] m_data
);
parameter C_M_DATA_WIDTH = 64;
parameter C_S_DATA_WIDTH = 64;
parameter C_BIG_ENDIAN = 0;
generate if (C_S_DATA_WIDTH == C_M_DATA_WIDTH) begin
assign m_valid = s_valid;
assign s_ready = m_ready;
assign m_data = s_data;
end else if (C_S_DATA_WIDTH < C_M_DATA_WIDTH) begin
localparam RATIO = C_M_DATA_WIDTH / C_S_DATA_WIDTH;
reg [C_M_DATA_WIDTH-1:0] data;
reg [$clog2(RATIO)-1:0] count;
reg valid;
always @(posedge clk)
begin
if (resetn == 1'b0) begin
count <= RATIO - 1;
valid <= 1'b0;
end else begin
if (count == 'h00 && s_ready == 1'b1 && s_valid == 1'b1)
valid <= 1'b1;
else if (m_ready == 1'b1)
valid <= 1'b0;
if (s_ready == 1'b1 && s_valid == 1'b1) begin
if (count == 'h00)
count <= RATIO - 1;
else
count <= count - 1'b1;
end
end
end
always @(posedge clk)
begin
if (s_ready == 1'b1 && s_valid == 1'b1)
if (C_BIG_ENDIAN == 1) begin
data <= {data[C_M_DATA_WIDTH-C_S_DATA_WIDTH-1:0], s_data};
end else begin
data <= {s_data, data[C_M_DATA_WIDTH-1:C_S_DATA_WIDTH]};
end
end
assign s_ready = ~valid || m_ready;
assign m_valid = valid;
assign m_data = data;
end else begin
localparam RATIO = C_S_DATA_WIDTH / C_M_DATA_WIDTH;
reg [C_S_DATA_WIDTH-1:0] data;
reg [$clog2(RATIO)-1:0] count;
reg valid;
always @(posedge clk)
begin
if (resetn == 1'b0) begin
count <= RATIO - 1;
valid <= 1'b0;
end else begin
if (s_valid == 1'b1 && s_ready == 1'b1)
valid <= 1'b1;
else if (count == 'h0 && m_ready == 1'b1 && m_valid == 1'b1)
valid <= 1'b0;
if (m_ready == 1'b1 && m_valid == 1'b1) begin
if (count == 'h00)
count <= RATIO - 1;
else
count <= count - 1'b1;
end
end
end
always @(posedge clk)
begin
if (s_ready == 1'b1 && s_valid == 1'b1) begin
data <= s_data;
end else if (m_ready == 1'b1 && m_valid == 1'b1) begin
if (C_BIG_ENDIAN == 1) begin
data[C_S_DATA_WIDTH-1:C_M_DATA_WIDTH] <= data[C_S_DATA_WIDTH-C_M_DATA_WIDTH-1:0];
end else begin
data[C_S_DATA_WIDTH-C_M_DATA_WIDTH-1:0] <= data[C_S_DATA_WIDTH-1:C_M_DATA_WIDTH];
end
end
end
assign s_ready = ~valid || (m_ready && count == 'h0);
assign m_valid = valid;
assign m_data = C_BIG_ENDIAN == 1 ?
data[C_S_DATA_WIDTH-1:C_S_DATA_WIDTH-C_M_DATA_WIDTH] :
data[C_M_DATA_WIDTH-1:0];
end
endgenerate
endmodule
|
//Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
module I2C_AV_Config ( //Host Side
iCLK,
iRST_N,
// I2C Side
oI2C_SCLK,
oI2C_SDAT
);
// Host Side
input iCLK;
input iRST_N;
// I2C Side
output oI2C_SCLK;
inout oI2C_SDAT;
// Internal Registers/Wires
reg [15:0] mI2C_CLK_DIV;
reg [23:0] mI2C_DATA;
reg mI2C_CTRL_CLK;
reg mI2C_GO;
wire mI2C_END;
wire mI2C_ACK;
reg [15:0] LUT_DATA;
reg [3:0] LUT_INDEX;
reg [1:0] mSetup_ST;
// Clock Setting
parameter CLK_Freq = 24000000; // 24 MHz
parameter I2C_Freq = 20000; // 20 KHz
// LUT Data Number
parameter LUT_SIZE = 11;
// Audio Data Index
parameter Dummy_DATA = 0;
parameter SET_LIN_L = 1;
parameter SET_LIN_R = 2;
parameter SET_HEAD_L = 3;
parameter SET_HEAD_R = 4;
parameter A_PATH_CTRL = 5;
parameter D_PATH_CTRL = 6;
parameter POWER_ON = 7;
parameter SET_FORMAT = 8;
parameter SAMPLE_CTRL = 9;
parameter SET_ACTIVE = 10;
///////////////////// I2C Control Clock ////////////////////////
always@(posedge iCLK or negedge iRST_N) begin
if(!iRST_N) begin
mI2C_CTRL_CLK <= 1'd0;
mI2C_CLK_DIV <= 16'd0;
end else begin
if (mI2C_CLK_DIV < (CLK_Freq/I2C_Freq))
mI2C_CLK_DIV <= mI2C_CLK_DIV + 16'd1;
else begin
mI2C_CLK_DIV <= 16'd0;
mI2C_CTRL_CLK <= ~mI2C_CTRL_CLK;
end
end
end
////////////////////////////////////////////////////////////////////
I2C_Controller u0 (
.CLOCK(mI2C_CTRL_CLK), // Controller Work Clock
.I2C_SCLK(oI2C_SCLK), // I2C CLOCK
.I2C_SDAT(oI2C_SDAT), // I2C DATA
.I2C_DATA(mI2C_DATA), // DATA:[SLAVE_ADDR,SUB_ADDR,DATA]
.GO(mI2C_GO), // GO transfor
.END(mI2C_END), // END transfor
.ACK(mI2C_ACK), // ACK
.RESET(iRST_N)
);
////////////////////////////////////////////////////////////////////
////////////////////// Config Control ////////////////////////////
always@(posedge mI2C_CTRL_CLK or negedge iRST_N) begin
if(!iRST_N) begin
LUT_INDEX <= 4'd0;
mSetup_ST <= 2'd0;
mI2C_GO <= 1'd0;
end else begin
if(LUT_INDEX < LUT_SIZE) begin
case(mSetup_ST)
0: begin
mI2C_DATA <= {8'h34,LUT_DATA};
mI2C_GO <= 1'd1;
mSetup_ST <= 2'd1;
end
1: begin
if(mI2C_END) begin
if(!mI2C_ACK)
mSetup_ST <= 2'd2;
else
mSetup_ST <= 2'd0;
mI2C_GO <= 1'd0;
end
end
2: begin
LUT_INDEX <= LUT_INDEX + 4'd1;
mSetup_ST <= 2'd0;
end
endcase
end
end
end
////////////////////////////////////////////////////////////////////
///////////////////// Config Data LUT //////////////////////////
always @ (*)
begin
case(LUT_INDEX)
// Audio Config Data
Dummy_DATA : LUT_DATA <= 16'h0000;
SET_LIN_L : LUT_DATA <= 16'h009A;//16'h001A; //R0 LINVOL = 1Ah (+4.5bB)
SET_LIN_R : LUT_DATA <= 16'h029A;//16'h021A; //R1 RINVOL = 1Ah (+4.5bB)
SET_HEAD_L : LUT_DATA <= 16'h0479; //R2 LHPVOL = 7Bh (+2dB)
SET_HEAD_R : LUT_DATA <= 16'h0679; //R3 RHPVOL = 7Bh (+2dB)
A_PATH_CTRL : LUT_DATA <= 16'h08D2;//16'h08F8; //R4 DACSEL = 1
D_PATH_CTRL : LUT_DATA <= 16'h0A06; //R5 DEEMP = 11 (48 KHz)
POWER_ON : LUT_DATA <= 16'h0C00; //R6
SET_FORMAT : LUT_DATA <= 16'h0E01; //R7 FORMAT=01,16 bit
SAMPLE_CTRL : LUT_DATA <= 16'h1009; //R8 48KHz,USB-mode
SET_ACTIVE : LUT_DATA <= 16'h1201; //R9 ACTIVE
default : LUT_DATA <= 16'h0000;
endcase
end
////////////////////////////////////////////////////////////////////
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2013(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/1ns
module prcfg_dac(
clk,
// control ports
control,
status,
// FIFO interface
src_dac_enable,
src_dac_data,
src_dac_valid,
dst_dac_enable,
dst_dac_data,
dst_dac_valid
);
parameter CHANNEL_ID = 0;
parameter DATA_WIDTH = 16;
localparam SYMBOL_WIDTH = 2;
localparam RP_ID = 8'hA2;
input clk;
input [31:0] control;
output [31:0] status;
output src_dac_enable;
input [(DATA_WIDTH-1):0] src_dac_data;
output src_dac_valid;
input dst_dac_enable;
output [(DATA_WIDTH-1):0] dst_dac_data;
input dst_dac_valid;
// output register to improve timing
reg [(DATA_WIDTH-1):0] dst_dac_data = 'h0;
reg src_dac_valid = 'h0;
reg src_dac_enable = 'h0;
// internal registers
reg [ 7:0] pn_data = 'hF2;
reg [31:0] status = 'h0;
reg [ 3:0] mode = 'h0;
// internal wires
wire [(SYMBOL_WIDTH-1):0] mod_data;
wire [15:0] dac_data_fltr_i;
wire [15:0] dac_data_fltr_q;
// prbs function
function [ 7:0] pn;
input [ 7:0] din;
reg [ 7:0] dout;
begin
dout[7] = din[6];
dout[6] = din[5];
dout[5] = din[4];
dout[4] = din[3];
dout[3] = din[2];
dout[2] = din[1];
dout[1] = din[7] ^ din[4];
dout[0] = din[6] ^ din[3];
pn = dout;
end
endfunction
// update control and status registers
always @(posedge clk) begin
status <= { 24'h0, RP_ID };
mode <= control[ 7:4];
end
// prbs generation
always @(posedge clk) begin
if((dst_dac_en == 1) && (dst_dac_enable == 1)) begin
pn_data <= pn(pn_data);
end
end
// data for the modulator (prbs or dma)
assign mod_data = (mode == 1) ? pn_data[ 1:0] : src_dac_data[ 1:0];
// qpsk modulator
qpsk_mod i_qpsk_mod (
.clk(clk),
.data_input(mod_data),
.data_valid(dst_dac_en),
.data_qpsk_i(dac_data_fltr_i),
.data_qpsk_q(dac_data_fltr_q)
);
// output logic
always @(posedge clk) begin
src_dac_enable <= dst_dac_en;
src_dac_valid <= dst_dac_valid;
case(mode)
4'h0 : begin
dst_dac_data <= src_dac_data;
end
4'h1 : begin
dst_dac_data <= { dac_data_fltr_q, dac_data_fltr_i };
end
4'h2 : begin
dst_dac_data <= { dac_data_fltr_q, dac_data_fltr_i };
end
default : begin
end
endcase
end
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : rank_mach.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// Top level rank machine structural block. This block
// instantiates a configurable number of rank controller blocks.
`timescale 1ps/1ps
module rank_mach #
(
parameter BURST_MODE = "8",
parameter CS_WIDTH = 4,
parameter DRAM_TYPE = "DDR3",
parameter MAINT_PRESCALER_DIV = 40,
parameter nBANK_MACHS = 4,
parameter nCK_PER_CLK = 2,
parameter CL = 5,
parameter nFAW = 30,
parameter nREFRESH_BANK = 8,
parameter nRRD = 4,
parameter nWTR = 4,
parameter PERIODIC_RD_TIMER_DIV = 20,
parameter RANK_BM_BV_WIDTH = 16,
parameter RANK_WIDTH = 2,
parameter RANKS = 4,
parameter REFRESH_TIMER_DIV = 39,
parameter ZQ_TIMER_DIV = 640000
)
(/*AUTOARG*/
// Outputs
periodic_rd_rank_r, periodic_rd_r, maint_req_r, inhbt_act_faw_r,
inhbt_rd_r, wtr_inhbt_config_r, maint_rank_r, maint_zq_r,
// Inputs
wr_this_rank_r, slot_1_present, slot_0_present, sending_row,
sending_col, rst, rd_this_rank_r, rank_busy_r, periodic_rd_ack_r,
maint_wip_r, insert_maint_r1, init_calib_complete, clk, app_zq_req,
app_ref_req, app_periodic_rd_req, act_this_rank_r
);
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input [RANK_BM_BV_WIDTH-1:0] act_this_rank_r; // To rank_cntrl0 of rank_cntrl.v
input app_periodic_rd_req; // To rank_cntrl0 of rank_cntrl.v
input app_ref_req; // To rank_cntrl0 of rank_cntrl.v
input app_zq_req; // To rank_common0 of rank_common.v
input clk; // To rank_cntrl0 of rank_cntrl.v, ...
input init_calib_complete; // To rank_cntrl0 of rank_cntrl.v, ...
input insert_maint_r1; // To rank_cntrl0 of rank_cntrl.v, ...
input maint_wip_r; // To rank_common0 of rank_common.v
input periodic_rd_ack_r; // To rank_common0 of rank_common.v
input [(RANKS*nBANK_MACHS)-1:0] rank_busy_r; // To rank_cntrl0 of rank_cntrl.v
input [RANK_BM_BV_WIDTH-1:0] rd_this_rank_r; // To rank_cntrl0 of rank_cntrl.v
input rst; // To rank_cntrl0 of rank_cntrl.v, ...
input [nBANK_MACHS-1:0] sending_col; // To rank_cntrl0 of rank_cntrl.v
input [nBANK_MACHS-1:0] sending_row; // To rank_cntrl0 of rank_cntrl.v
input [7:0] slot_0_present; // To rank_common0 of rank_common.v
input [7:0] slot_1_present; // To rank_common0 of rank_common.v
input [RANK_BM_BV_WIDTH-1:0] wr_this_rank_r; // To rank_cntrl0 of rank_cntrl.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output maint_req_r; // From rank_common0 of rank_common.v
output periodic_rd_r; // From rank_common0 of rank_common.v
output [RANK_WIDTH-1:0] periodic_rd_rank_r; // From rank_common0 of rank_common.v
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire maint_prescaler_tick_r; // From rank_common0 of rank_common.v
wire refresh_tick; // From rank_common0 of rank_common.v
// End of automatics
output [RANKS-1:0] inhbt_act_faw_r;
output [RANKS-1:0] inhbt_rd_r;
output [RANKS-1:0] wtr_inhbt_config_r;
output [RANK_WIDTH-1:0] maint_rank_r;
output maint_zq_r;
wire [RANKS-1:0] refresh_request;
wire [RANKS-1:0] periodic_rd_request;
wire [RANKS-1:0] clear_periodic_rd_request;
genvar ID;
generate
for (ID=0; ID<RANKS; ID=ID+1) begin:rank_cntrl
rank_cntrl#
(/*AUTOINSTPARAM*/
// Parameters
.BURST_MODE (BURST_MODE),
.ID (ID),
.nBANK_MACHS (nBANK_MACHS),
.nCK_PER_CLK (nCK_PER_CLK),
.CL (CL),
.nFAW (nFAW),
.nREFRESH_BANK (nREFRESH_BANK),
.nRRD (nRRD),
.nWTR (nWTR),
.PERIODIC_RD_TIMER_DIV (PERIODIC_RD_TIMER_DIV),
.RANK_BM_BV_WIDTH (RANK_BM_BV_WIDTH),
.RANK_WIDTH (RANK_WIDTH),
.RANKS (RANKS),
.REFRESH_TIMER_DIV (REFRESH_TIMER_DIV))
rank_cntrl0
(.clear_periodic_rd_request (clear_periodic_rd_request[ID]),
.inhbt_act_faw_r (inhbt_act_faw_r[ID]),
.inhbt_rd_r (inhbt_rd_r[ID]),
.periodic_rd_request (periodic_rd_request[ID]),
.refresh_request (refresh_request[ID]),
.wtr_inhbt_config_r (wtr_inhbt_config_r[ID]),
/*AUTOINST*/
// Inputs
.clk (clk),
.rst (rst),
.sending_row (sending_row[nBANK_MACHS-1:0]),
.act_this_rank_r (act_this_rank_r[RANK_BM_BV_WIDTH-1:0]),
.sending_col (sending_col[nBANK_MACHS-1:0]),
.wr_this_rank_r (wr_this_rank_r[RANK_BM_BV_WIDTH-1:0]),
.app_ref_req (app_ref_req),
.init_calib_complete (init_calib_complete),
.rank_busy_r (rank_busy_r[(RANKS*nBANK_MACHS)-1:0]),
.refresh_tick (refresh_tick),
.insert_maint_r1 (insert_maint_r1),
.maint_zq_r (maint_zq_r),
.maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]),
.app_periodic_rd_req (app_periodic_rd_req),
.maint_prescaler_tick_r (maint_prescaler_tick_r),
.rd_this_rank_r (rd_this_rank_r[RANK_BM_BV_WIDTH-1:0]));
end
endgenerate
rank_common#
(/*AUTOINSTPARAM*/
// Parameters
.DRAM_TYPE (DRAM_TYPE),
.MAINT_PRESCALER_DIV (MAINT_PRESCALER_DIV),
.nBANK_MACHS (nBANK_MACHS),
.PERIODIC_RD_TIMER_DIV (PERIODIC_RD_TIMER_DIV),
.RANK_WIDTH (RANK_WIDTH),
.RANKS (RANKS),
.REFRESH_TIMER_DIV (REFRESH_TIMER_DIV),
.ZQ_TIMER_DIV (ZQ_TIMER_DIV))
rank_common0
(.clear_periodic_rd_request (clear_periodic_rd_request[RANKS-1:0]),
/*AUTOINST*/
// Outputs
.maint_prescaler_tick_r (maint_prescaler_tick_r),
.refresh_tick (refresh_tick),
.maint_zq_r (maint_zq_r),
.maint_req_r (maint_req_r),
.maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]),
.periodic_rd_r (periodic_rd_r),
.periodic_rd_rank_r (periodic_rd_rank_r[RANK_WIDTH-1:0]),
// Inputs
.clk (clk),
.rst (rst),
.init_calib_complete (init_calib_complete),
.app_zq_req (app_zq_req),
.insert_maint_r1 (insert_maint_r1),
.refresh_request (refresh_request[RANKS-1:0]),
.maint_wip_r (maint_wip_r),
.slot_0_present (slot_0_present[7:0]),
.slot_1_present (slot_1_present[7:0]),
.periodic_rd_request (periodic_rd_request[RANKS-1:0]),
.periodic_rd_ack_r (periodic_rd_ack_r));
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// Listens to signals from a kernel to detect when
// all required items are processed.
module acl_kernel_done_detector
#(
parameter WIDTH = 32 // width of all the counters
)
(
input clock,
input resetn,
input start, // Assert to restart the iterators
// listen to kernel's stall/valid signals
input kernel_stall_out,
input kernel_valid_in,
input kernel_stall_in,
input kernel_valid_out,
// high when it looks like the kernel is done
// only is true if all the groups were also dispatched
output kernel_done
);
// counter for number of items inside the kernel
reg [WIDTH-1:0] items_not_done;
// Valid_in to kernel will go low when the fifo inside the acl_id_iterator
// becomes empty. This means there is no more groups to dispatch.
assign all_items_sent = ~kernel_valid_in & ~kernel_stall_out;
assign kernel_done = (items_not_done == {WIDTH{1'b0}});
always @(posedge clock or negedge resetn)
begin
if ( ~resetn )
items_not_done <= {WIDTH{1'b0}};
else if ( start )
items_not_done <= {WIDTH{1'b0}};
else begin
if (kernel_valid_in & ~kernel_stall_out & (~kernel_valid_out | kernel_stall_in))
items_not_done <= (items_not_done + 2'b01);
else
if (kernel_valid_out & ~kernel_stall_in & (~kernel_valid_in | kernel_stall_out))
items_not_done <= (items_not_done - 2'b01);
end
end
endmodule
// Produces finish signal when all kernel copies are done.
module acl_all_done_detector
#(
parameter NUM_COPIES = 1 // number of kernel instance copies
)
(
input clock,
input resetn,
input start,
input dispatched_all_groups,
input [NUM_COPIES-1:0] kernel_done,
output reg finish
);
// Need to know if sent at least one work item into any of the kernel
// copies (some kernel copies can never be used if don't have enough
// work-groups). Allow upto 5 cycles for the effect of the first item
// to propagate to kernel_done signals.
localparam MAX_CYCLE_COUNTER_VALUE = 5;
reg [3:0] cycles_since_sent_first_item;
wire sent_first_item = (cycles_since_sent_first_item == MAX_CYCLE_COUNTER_VALUE);
// used to bring down 'finish' after it being high for one cycle.
reg not_finished;
always @(posedge clock or negedge resetn)
begin
if ( ~resetn )
finish <= 1'b0;
else if ( start )
finish <= 1'b0;
else
finish <= not_finished &
dispatched_all_groups &
sent_first_item &
(kernel_done == {NUM_COPIES{1'b1}});
end
always @(posedge clock or negedge resetn)
begin
if ( ~resetn )
not_finished <= 1'b1;
else if ( start )
not_finished <= 1'b1;
else if ( finish )
not_finished <= 1'b0;
else
not_finished <= not_finished;
end
// Assuming that if dispatched all groups, sent at least one
// item into at least one kernel.
always @(posedge clock or negedge resetn)
begin
if ( ~resetn )
cycles_since_sent_first_item <= 0;
else if ( start )
cycles_since_sent_first_item <= 0;
else if ( cycles_since_sent_first_item == MAX_CYCLE_COUNTER_VALUE )
cycles_since_sent_first_item <= MAX_CYCLE_COUNTER_VALUE;
else if ( dispatched_all_groups | (cycles_since_sent_first_item > 0) )
cycles_since_sent_first_item <= cycles_since_sent_first_item + 1;
end
endmodule
|
module channel_ram
( // System
input txclk, input reset,
// USB side
input [31:0] datain, input WR, input WR_done, output have_space,
// Reader side
output [31:0] dataout, input RD, input RD_done, output packet_waiting);
reg [6:0] wr_addr, rd_addr;
reg [1:0] which_ram_wr, which_ram_rd;
reg [2:0] nb_packets;
reg [31:0] ram0 [0:127];
reg [31:0] ram1 [0:127];
reg [31:0] ram2 [0:127];
reg [31:0] ram3 [0:127];
reg [31:0] dataout0;
reg [31:0] dataout1;
reg [31:0] dataout2;
reg [31:0] dataout3;
wire wr_done_int;
wire rd_done_int;
wire [6:0] rd_addr_final;
wire [1:0] which_ram_rd_final;
// USB side
always @(posedge txclk)
if(WR & (which_ram_wr == 2'd0)) ram0[wr_addr] <= datain;
always @(posedge txclk)
if(WR & (which_ram_wr == 2'd1)) ram1[wr_addr] <= datain;
always @(posedge txclk)
if(WR & (which_ram_wr == 2'd2)) ram2[wr_addr] <= datain;
always @(posedge txclk)
if(WR & (which_ram_wr == 2'd3)) ram3[wr_addr] <= datain;
assign wr_done_int = ((WR && (wr_addr == 7'd127)) || WR_done);
always @(posedge txclk)
if(reset)
wr_addr <= 0;
else if (WR_done)
wr_addr <= 0;
else if (WR)
wr_addr <= wr_addr + 7'd1;
always @(posedge txclk)
if(reset)
which_ram_wr <= 0;
else if (wr_done_int)
which_ram_wr <= which_ram_wr + 2'd1;
assign have_space = (nb_packets < 3'd3);
// Reader side
// short hand fifo
// rd_addr_final is what rd_addr is going to be next clock cycle
// which_ram_rd_final is what which_ram_rd is going to be next clock cycle
always @(posedge txclk) dataout0 <= ram0[rd_addr_final];
always @(posedge txclk) dataout1 <= ram1[rd_addr_final];
always @(posedge txclk) dataout2 <= ram2[rd_addr_final];
always @(posedge txclk) dataout3 <= ram3[rd_addr_final];
assign dataout = (which_ram_rd_final[1]) ?
(which_ram_rd_final[0] ? dataout3 : dataout2) :
(which_ram_rd_final[0] ? dataout1 : dataout0);
//RD_done is the only way to signal the end of one packet
assign rd_done_int = RD_done;
always @(posedge txclk)
if (reset)
rd_addr <= 0;
else if (RD_done)
rd_addr <= 0;
else if (RD)
rd_addr <= rd_addr + 7'd1;
assign rd_addr_final = (reset|RD_done) ? (6'd0) :
((RD)?(rd_addr+7'd1):rd_addr);
always @(posedge txclk)
if (reset)
which_ram_rd <= 0;
else if (rd_done_int)
which_ram_rd <= which_ram_rd + 2'd1;
assign which_ram_rd_final = (reset) ? (2'd0):
((rd_done_int) ? (which_ram_rd + 2'd1) : which_ram_rd);
//packet_waiting is set to zero if rd_done_int is high
//because there is no guarantee that nb_packets will be pos.
assign packet_waiting = (nb_packets > 1) | ((nb_packets == 1)&(~rd_done_int));
always @(posedge txclk)
if (reset)
nb_packets <= 0;
else if (wr_done_int & ~rd_done_int)
nb_packets <= nb_packets + 3'd1;
else if (rd_done_int & ~wr_done_int)
nb_packets <= nb_packets - 3'd1;
endmodule
|
(* An example showing that prop-extensionality is incompatible with
powerful extensions of the guard condition.
Unlike the example in guard2, it is not exploiting the fact that
the elimination of False always produces a subterm.
Example due to Cristobal Camarero on Coq-Club.
Adapted to nested types by Bruno Barras.
*)
Axiom prop_ext: forall P Q, (P<->Q)->P=Q.
Module Unboxed.
Inductive True2:Prop:= I2: (False->True2)->True2.
Theorem Heq: (False->True2)=True2.
Proof.
apply prop_ext. split.
- intros. constructor. exact H.
- intros. exact H.
Qed.
Fail Fixpoint con (x:True2) :False :=
match x with
I2 f => con (match Heq in _=T return T with eq_refl => f end)
end.
End Unboxed.
(* This boxed example shows that it is not enough to just require
that the return type of the match on Heq is an inductive type
*)
Module Boxed.
Inductive box (T:Type) := Box (_:T).
Definition unbox {T} (b:box T) : T := let (x) := b in x.
Inductive True2:Prop:= I2: box(False->True2)->True2.
Definition Heq: (False->True2) <-> True2 :=
conj (fun f => I2 (Box _ f)) (fun x _ => x).
Fail Fixpoint con (x:True2) :False :=
match x with
I2 f => con (unbox(match prop_ext _ _ Heq in _=T return box T with eq_refl => f end))
end.
End Boxed.
|
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <[email protected]>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* ---
*
* The Simulation Library.
*
* This Verilog library contains simple simulation models for the internal
* cells ($not, ...) generated by the frontends and used in most passes.
*
* This library can be used to verify the internal netlists as generated
* by the different frontends and passes.
*
* Note that memory can only be simulated when all $memrd and $memwr cells
* have been merged to stand-alone $mem cells (this is what the "memory_collect"
* pass is doing).
*
*/
// --------------------------------------------------------
module \$not (A, Y);
parameter A_SIGNED = 0;
parameter A_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
output [Y_WIDTH-1:0] Y;
generate
if (A_SIGNED) begin:BLOCK1
assign Y = ~$signed(A);
end else begin:BLOCK2
assign Y = ~A;
end
endgenerate
endmodule
// --------------------------------------------------------
module \$pos (A, Y);
parameter A_SIGNED = 0;
parameter A_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
output [Y_WIDTH-1:0] Y;
generate
if (A_SIGNED) begin:BLOCK1
assign Y = $signed(A);
end else begin:BLOCK2
assign Y = A;
end
endgenerate
endmodule
// --------------------------------------------------------
module \$neg (A, Y);
parameter A_SIGNED = 0;
parameter A_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
output [Y_WIDTH-1:0] Y;
generate
if (A_SIGNED) begin:BLOCK1
assign Y = -$signed(A);
end else begin:BLOCK2
assign Y = -A;
end
endgenerate
endmodule
// --------------------------------------------------------
module \$and (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
generate
if (A_SIGNED && B_SIGNED) begin:BLOCK1
assign Y = $signed(A) & $signed(B);
end else begin:BLOCK2
assign Y = A & B;
end
endgenerate
endmodule
// --------------------------------------------------------
module \$or (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
generate
if (A_SIGNED && B_SIGNED) begin:BLOCK1
assign Y = $signed(A) | $signed(B);
end else begin:BLOCK2
assign Y = A | B;
end
endgenerate
endmodule
// --------------------------------------------------------
module \$xor (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
generate
if (A_SIGNED && B_SIGNED) begin:BLOCK1
assign Y = $signed(A) ^ $signed(B);
end else begin:BLOCK2
assign Y = A ^ B;
end
endgenerate
endmodule
// --------------------------------------------------------
module \$xnor (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
generate
if (A_SIGNED && B_SIGNED) begin:BLOCK1
assign Y = $signed(A) ~^ $signed(B);
end else begin:BLOCK2
assign Y = A ~^ B;
end
endgenerate
endmodule
// --------------------------------------------------------
module \$reduce_and (A, Y);
parameter A_SIGNED = 0;
parameter A_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
output [Y_WIDTH-1:0] Y;
generate
if (A_SIGNED) begin:BLOCK1
assign Y = &$signed(A);
end else begin:BLOCK2
assign Y = &A;
end
endgenerate
endmodule
// --------------------------------------------------------
module \$reduce_or (A, Y);
parameter A_SIGNED = 0;
parameter A_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
output [Y_WIDTH-1:0] Y;
generate
if (A_SIGNED) begin:BLOCK1
assign Y = |$signed(A);
end else begin:BLOCK2
assign Y = |A;
end
endgenerate
endmodule
// --------------------------------------------------------
module \$reduce_xor (A, Y);
parameter A_SIGNED = 0;
parameter A_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
output [Y_WIDTH-1:0] Y;
generate
if (A_SIGNED) begin:BLOCK1
assign Y = ^$signed(A);
end else begin:BLOCK2
assign Y = ^A;
end
endgenerate
endmodule
// --------------------------------------------------------
module \$reduce_xnor (A, Y);
parameter A_SIGNED = 0;
parameter A_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
output [Y_WIDTH-1:0] Y;
generate
if (A_SIGNED) begin:BLOCK1
assign Y = ~^$signed(A);
end else begin:BLOCK2
assign Y = ~^A;
end
endgenerate
endmodule
// --------------------------------------------------------
module \$reduce_bool (A, Y);
parameter A_SIGNED = 0;
parameter A_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
output [Y_WIDTH-1:0] Y;
generate
if (A_SIGNED) begin:BLOCK1
assign Y = !(!$signed(A));
end else begin:BLOCK2
assign Y = !(!A);
end
endgenerate
endmodule
// --------------------------------------------------------
module \$shl (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
generate
if (A_SIGNED) begin:BLOCK1
assign Y = $signed(A) << B;
end else begin:BLOCK2
assign Y = A << B;
end
endgenerate
endmodule
// --------------------------------------------------------
module \$shr (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
generate
if (A_SIGNED) begin:BLOCK1
assign Y = $signed(A) >> B;
end else begin:BLOCK2
assign Y = A >> B;
end
endgenerate
endmodule
// --------------------------------------------------------
module \$sshl (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
generate
if (A_SIGNED) begin:BLOCK1
assign Y = $signed(A) <<< B;
end else begin:BLOCK2
assign Y = A <<< B;
end
endgenerate
endmodule
// --------------------------------------------------------
module \$sshr (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
generate
if (A_SIGNED) begin:BLOCK1
assign Y = $signed(A) >>> B;
end else begin:BLOCK2
assign Y = A >>> B;
end
endgenerate
endmodule
// --------------------------------------------------------
module \$shift (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
generate
if (B_SIGNED) begin:BLOCK1
assign Y = $signed(B) < 0 ? A << -B : A >> B;
end else begin:BLOCK2
assign Y = A >> B;
end
endgenerate
endmodule
// --------------------------------------------------------
module \$shiftx (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
generate
if (Y_WIDTH > 0)
if (B_SIGNED) begin:BLOCK1
assign Y = A[$signed(B) +: Y_WIDTH];
end else begin:BLOCK2
assign Y = A[B +: Y_WIDTH];
end
endgenerate
endmodule
// --------------------------------------------------------
module \$fa (A, B, C, X, Y);
parameter WIDTH = 1;
input [WIDTH-1:0] A, B, C;
output [WIDTH-1:0] X, Y;
wire [WIDTH-1:0] t1, t2, t3;
assign t1 = A ^ B, t2 = A & B, t3 = C & t1;
assign Y = t1 ^ C, X = (t2 | t3) ^ (Y ^ Y);
endmodule
// --------------------------------------------------------
module \$lcu (P, G, CI, CO);
parameter WIDTH = 1;
input [WIDTH-1:0] P, G;
input CI;
output reg [WIDTH-1:0] CO;
integer i;
always @* begin
CO = 'bx;
if (^{P, G, CI} !== 1'bx) begin
CO[0] = G[0] || (P[0] && CI);
for (i = 1; i < WIDTH; i = i+1)
CO[i] = G[i] || (P[i] && CO[i-1]);
end
end
endmodule
// --------------------------------------------------------
module \$alu (A, B, CI, BI, X, Y, CO);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] X, Y;
input CI, BI;
output [Y_WIDTH-1:0] CO;
wire [Y_WIDTH-1:0] AA, BB;
generate
if (A_SIGNED && B_SIGNED) begin:BLOCK1
assign AA = $signed(A), BB = BI ? ~$signed(B) : $signed(B);
end else begin:BLOCK2
assign AA = $unsigned(A), BB = BI ? ~$unsigned(B) : $unsigned(B);
end
endgenerate
// this is 'x' if Y and CO should be all 'x', and '0' otherwise
wire y_co_undef = ^{A, A, B, B, CI, CI, BI, BI};
assign X = AA ^ BB;
assign Y = (AA + BB + CI) ^ {Y_WIDTH{y_co_undef}};
function get_carry;
input a, b, c;
get_carry = (a&b) | (a&c) | (b&c);
endfunction
genvar i;
generate
assign CO[0] = get_carry(AA[0], BB[0], CI) ^ y_co_undef;
for (i = 1; i < Y_WIDTH; i = i+1) begin:BLOCK3
assign CO[i] = get_carry(AA[i], BB[i], CO[i-1]) ^ y_co_undef;
end
endgenerate
endmodule
// --------------------------------------------------------
module \$lt (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
generate
if (A_SIGNED && B_SIGNED) begin:BLOCK1
assign Y = $signed(A) < $signed(B);
end else begin:BLOCK2
assign Y = A < B;
end
endgenerate
endmodule
// --------------------------------------------------------
module \$le (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
generate
if (A_SIGNED && B_SIGNED) begin:BLOCK1
assign Y = $signed(A) <= $signed(B);
end else begin:BLOCK2
assign Y = A <= B;
end
endgenerate
endmodule
// --------------------------------------------------------
module \$eq (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
generate
if (A_SIGNED && B_SIGNED) begin:BLOCK1
assign Y = $signed(A) == $signed(B);
end else begin:BLOCK2
assign Y = A == B;
end
endgenerate
endmodule
// --------------------------------------------------------
module \$ne (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
generate
if (A_SIGNED && B_SIGNED) begin:BLOCK1
assign Y = $signed(A) != $signed(B);
end else begin:BLOCK2
assign Y = A != B;
end
endgenerate
endmodule
// --------------------------------------------------------
module \$eqx (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
generate
if (A_SIGNED && B_SIGNED) begin:BLOCK1
assign Y = $signed(A) === $signed(B);
end else begin:BLOCK2
assign Y = A === B;
end
endgenerate
endmodule
// --------------------------------------------------------
module \$nex (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
generate
if (A_SIGNED && B_SIGNED) begin:BLOCK1
assign Y = $signed(A) !== $signed(B);
end else begin:BLOCK2
assign Y = A !== B;
end
endgenerate
endmodule
// --------------------------------------------------------
module \$ge (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
generate
if (A_SIGNED && B_SIGNED) begin:BLOCK1
assign Y = $signed(A) >= $signed(B);
end else begin:BLOCK2
assign Y = A >= B;
end
endgenerate
endmodule
// --------------------------------------------------------
module \$gt (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
generate
if (A_SIGNED && B_SIGNED) begin:BLOCK1
assign Y = $signed(A) > $signed(B);
end else begin:BLOCK2
assign Y = A > B;
end
endgenerate
endmodule
// --------------------------------------------------------
module \$add (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
generate
if (A_SIGNED && B_SIGNED) begin:BLOCK1
assign Y = $signed(A) + $signed(B);
end else begin:BLOCK2
assign Y = A + B;
end
endgenerate
endmodule
// --------------------------------------------------------
module \$sub (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
generate
if (A_SIGNED && B_SIGNED) begin:BLOCK1
assign Y = $signed(A) - $signed(B);
end else begin:BLOCK2
assign Y = A - B;
end
endgenerate
endmodule
// --------------------------------------------------------
module \$mul (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
generate
if (A_SIGNED && B_SIGNED) begin:BLOCK1
assign Y = $signed(A) * $signed(B);
end else begin:BLOCK2
assign Y = A * B;
end
endgenerate
endmodule
// --------------------------------------------------------
module \$macc (A, B, Y);
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
parameter CONFIG = 4'b0000;
parameter CONFIG_WIDTH = 4;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output reg [Y_WIDTH-1:0] Y;
// Xilinx XSIM does not like $clog2() below..
function integer my_clog2;
input integer v;
begin
if (v > 0)
v = v - 1;
my_clog2 = 0;
while (v) begin
v = v >> 1;
my_clog2 = my_clog2 + 1;
end
end
endfunction
localparam integer num_bits = CONFIG[3:0] > 0 ? CONFIG[3:0] : 1;
localparam integer num_ports = (CONFIG_WIDTH-4) / (2 + 2*num_bits);
localparam integer num_abits = my_clog2(A_WIDTH) > 0 ? my_clog2(A_WIDTH) : 1;
function [2*num_ports*num_abits-1:0] get_port_offsets;
input [CONFIG_WIDTH-1:0] cfg;
integer i, cursor;
begin
cursor = 0;
get_port_offsets = 0;
for (i = 0; i < num_ports; i = i+1) begin
get_port_offsets[(2*i + 0)*num_abits +: num_abits] = cursor;
cursor = cursor + cfg[4 + i*(2 + 2*num_bits) + 2 +: num_bits];
get_port_offsets[(2*i + 1)*num_abits +: num_abits] = cursor;
cursor = cursor + cfg[4 + i*(2 + 2*num_bits) + 2 + num_bits +: num_bits];
end
end
endfunction
localparam [2*num_ports*num_abits-1:0] port_offsets = get_port_offsets(CONFIG);
`define PORT_IS_SIGNED (0 + CONFIG[4 + i*(2 + 2*num_bits)])
`define PORT_DO_SUBTRACT (0 + CONFIG[4 + i*(2 + 2*num_bits) + 1])
`define PORT_SIZE_A (0 + CONFIG[4 + i*(2 + 2*num_bits) + 2 +: num_bits])
`define PORT_SIZE_B (0 + CONFIG[4 + i*(2 + 2*num_bits) + 2 + num_bits +: num_bits])
`define PORT_OFFSET_A (0 + port_offsets[2*i*num_abits +: num_abits])
`define PORT_OFFSET_B (0 + port_offsets[2*i*num_abits + num_abits +: num_abits])
integer i, j;
reg [Y_WIDTH-1:0] tmp_a, tmp_b;
always @* begin
Y = 0;
for (i = 0; i < num_ports; i = i+1)
begin
tmp_a = 0;
tmp_b = 0;
for (j = 0; j < `PORT_SIZE_A; j = j+1)
tmp_a[j] = A[`PORT_OFFSET_A + j];
if (`PORT_IS_SIGNED && `PORT_SIZE_A > 0)
for (j = `PORT_SIZE_A; j < Y_WIDTH; j = j+1)
tmp_a[j] = tmp_a[`PORT_SIZE_A-1];
for (j = 0; j < `PORT_SIZE_B; j = j+1)
tmp_b[j] = A[`PORT_OFFSET_B + j];
if (`PORT_IS_SIGNED && `PORT_SIZE_B > 0)
for (j = `PORT_SIZE_B; j < Y_WIDTH; j = j+1)
tmp_b[j] = tmp_b[`PORT_SIZE_B-1];
if (`PORT_SIZE_B > 0)
tmp_a = tmp_a * tmp_b;
if (`PORT_DO_SUBTRACT)
Y = Y - tmp_a;
else
Y = Y + tmp_a;
end
for (i = 0; i < B_WIDTH; i = i+1) begin
Y = Y + B[i];
end
end
`undef PORT_IS_SIGNED
`undef PORT_DO_SUBTRACT
`undef PORT_SIZE_A
`undef PORT_SIZE_B
`undef PORT_OFFSET_A
`undef PORT_OFFSET_B
endmodule
// --------------------------------------------------------
module \$div (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
generate
if (A_SIGNED && B_SIGNED) begin:BLOCK1
assign Y = $signed(A) / $signed(B);
end else begin:BLOCK2
assign Y = A / B;
end
endgenerate
endmodule
// --------------------------------------------------------
module \$mod (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
generate
if (A_SIGNED && B_SIGNED) begin:BLOCK1
assign Y = $signed(A) % $signed(B);
end else begin:BLOCK2
assign Y = A % B;
end
endgenerate
endmodule
// --------------------------------------------------------
`ifndef SIMLIB_NOPOW
module \$pow (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
generate
if (A_SIGNED && B_SIGNED) begin:BLOCK1
assign Y = $signed(A) ** $signed(B);
end else if (A_SIGNED) begin:BLOCK2
assign Y = $signed(A) ** B;
end else if (B_SIGNED) begin:BLOCK3
assign Y = A ** $signed(B);
end else begin:BLOCK4
assign Y = A ** B;
end
endgenerate
endmodule
`endif
// --------------------------------------------------------
module \$logic_not (A, Y);
parameter A_SIGNED = 0;
parameter A_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
output [Y_WIDTH-1:0] Y;
generate
if (A_SIGNED) begin:BLOCK1
assign Y = !$signed(A);
end else begin:BLOCK2
assign Y = !A;
end
endgenerate
endmodule
// --------------------------------------------------------
module \$logic_and (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
generate
if (A_SIGNED && B_SIGNED) begin:BLOCK1
assign Y = $signed(A) && $signed(B);
end else begin:BLOCK2
assign Y = A && B;
end
endgenerate
endmodule
// --------------------------------------------------------
module \$logic_or (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
generate
if (A_SIGNED && B_SIGNED) begin:BLOCK1
assign Y = $signed(A) || $signed(B);
end else begin:BLOCK2
assign Y = A || B;
end
endgenerate
endmodule
// --------------------------------------------------------
module \$slice (A, Y);
parameter OFFSET = 0;
parameter A_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
output [Y_WIDTH-1:0] Y;
assign Y = A >> OFFSET;
endmodule
// --------------------------------------------------------
module \$concat (A, B, Y);
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [A_WIDTH+B_WIDTH-1:0] Y;
assign Y = {B, A};
endmodule
// --------------------------------------------------------
module \$mux (A, B, S, Y);
parameter WIDTH = 0;
input [WIDTH-1:0] A, B;
input S;
output reg [WIDTH-1:0] Y;
always @* begin
if (S)
Y = B;
else
Y = A;
end
endmodule
// --------------------------------------------------------
module \$pmux (A, B, S, Y);
parameter WIDTH = 0;
parameter S_WIDTH = 0;
input [WIDTH-1:0] A;
input [WIDTH*S_WIDTH-1:0] B;
input [S_WIDTH-1:0] S;
output reg [WIDTH-1:0] Y;
integer i;
reg found_active_sel_bit;
always @* begin
Y = A;
found_active_sel_bit = 0;
for (i = 0; i < S_WIDTH; i = i+1)
if (S[i]) begin
Y = found_active_sel_bit ? 'bx : B >> (WIDTH*i);
found_active_sel_bit = 1;
end
end
endmodule
// --------------------------------------------------------
`ifndef SIMLIB_NOLUT
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
input [WIDTH-1:0] A;
output reg Y;
wire lut0_out, lut1_out;
generate
if (WIDTH <= 1) begin:simple
assign {lut1_out, lut0_out} = LUT;
end else begin:complex
\$lut #( .WIDTH(WIDTH-1), .LUT(LUT ) ) lut0 ( .A(A[WIDTH-2:0]), .Y(lut0_out) );
\$lut #( .WIDTH(WIDTH-1), .LUT(LUT >> (2**(WIDTH-1))) ) lut1 ( .A(A[WIDTH-2:0]), .Y(lut1_out) );
end
if (WIDTH > 0) begin:lutlogic
always @* begin
casez ({A[WIDTH-1], lut0_out, lut1_out})
3'b?11: Y = 1'b1;
3'b?00: Y = 1'b0;
3'b0??: Y = lut0_out;
3'b1??: Y = lut1_out;
default: Y = 1'bx;
endcase
end
end
endgenerate
endmodule
`endif
// --------------------------------------------------------
module \$tribuf (A, EN, Y);
parameter WIDTH = 0;
input [WIDTH-1:0] A;
input EN;
output [WIDTH-1:0] Y;
assign Y = EN ? A : 'bz;
endmodule
// --------------------------------------------------------
module \$assert (A, EN);
input A, EN;
`ifndef SIMLIB_NOCHECKS
always @* begin
if (A !== 1'b1 && EN === 1'b1) begin
$display("Assertion %m failed!");
$stop;
end
end
`endif
endmodule
// --------------------------------------------------------
module \$assume (A, EN);
input A, EN;
`ifndef SIMLIB_NOCHECKS
always @* begin
if (A !== 1'b1 && EN === 1'b1) begin
$display("Assumption %m failed!");
$stop;
end
end
`endif
endmodule
// --------------------------------------------------------
module \$equiv (A, B, Y);
input A, B;
output Y;
assign Y = (A !== 1'bx && A !== B) ? 1'bx : A;
`ifndef SIMLIB_NOCHECKS
always @* begin
if (A !== 1'bx && A !== B) begin
$display("Equivalence failed!");
$stop;
end
end
`endif
endmodule
// --------------------------------------------------------
`ifndef SIMLIB_NOSR
module \$sr (SET, CLR, Q);
parameter WIDTH = 0;
parameter SET_POLARITY = 1'b1;
parameter CLR_POLARITY = 1'b1;
input [WIDTH-1:0] SET, CLR;
output reg [WIDTH-1:0] Q;
wire [WIDTH-1:0] pos_set = SET_POLARITY ? SET : ~SET;
wire [WIDTH-1:0] pos_clr = CLR_POLARITY ? CLR : ~CLR;
genvar i;
generate
for (i = 0; i < WIDTH; i = i+1) begin:bit
always @(posedge pos_set[i], posedge pos_clr[i])
if (pos_clr[i])
Q[i] <= 0;
else if (pos_set[i])
Q[i] <= 1;
end
endgenerate
endmodule
`endif
// --------------------------------------------------------
module \$dff (CLK, D, Q);
parameter WIDTH = 0;
parameter CLK_POLARITY = 1'b1;
input CLK;
input [WIDTH-1:0] D;
output reg [WIDTH-1:0] Q;
wire pos_clk = CLK == CLK_POLARITY;
always @(posedge pos_clk) begin
Q <= D;
end
endmodule
// --------------------------------------------------------
module \$dffe (CLK, EN, D, Q);
parameter WIDTH = 0;
parameter CLK_POLARITY = 1'b1;
parameter EN_POLARITY = 1'b1;
input CLK, EN;
input [WIDTH-1:0] D;
output reg [WIDTH-1:0] Q;
wire pos_clk = CLK == CLK_POLARITY;
always @(posedge pos_clk) begin
if (EN == EN_POLARITY) Q <= D;
end
endmodule
// --------------------------------------------------------
`ifndef SIMLIB_NOSR
module \$dffsr (CLK, SET, CLR, D, Q);
parameter WIDTH = 0;
parameter CLK_POLARITY = 1'b1;
parameter SET_POLARITY = 1'b1;
parameter CLR_POLARITY = 1'b1;
input CLK;
input [WIDTH-1:0] SET, CLR, D;
output reg [WIDTH-1:0] Q;
wire pos_clk = CLK == CLK_POLARITY;
wire [WIDTH-1:0] pos_set = SET_POLARITY ? SET : ~SET;
wire [WIDTH-1:0] pos_clr = CLR_POLARITY ? CLR : ~CLR;
genvar i;
generate
for (i = 0; i < WIDTH; i = i+1) begin:bit
always @(posedge pos_set[i], posedge pos_clr[i], posedge pos_clk)
if (pos_clr[i])
Q[i] <= 0;
else if (pos_set[i])
Q[i] <= 1;
else
Q[i] <= D[i];
end
endgenerate
endmodule
`endif
// --------------------------------------------------------
module \$adff (CLK, ARST, D, Q);
parameter WIDTH = 0;
parameter CLK_POLARITY = 1'b1;
parameter ARST_POLARITY = 1'b1;
parameter ARST_VALUE = 0;
input CLK, ARST;
input [WIDTH-1:0] D;
output reg [WIDTH-1:0] Q;
wire pos_clk = CLK == CLK_POLARITY;
wire pos_arst = ARST == ARST_POLARITY;
always @(posedge pos_clk, posedge pos_arst) begin
if (pos_arst)
Q <= ARST_VALUE;
else
Q <= D;
end
endmodule
// --------------------------------------------------------
module \$dlatch (EN, D, Q);
parameter WIDTH = 0;
parameter EN_POLARITY = 1'b1;
input EN;
input [WIDTH-1:0] D;
output reg [WIDTH-1:0] Q;
always @* begin
if (EN == EN_POLARITY)
Q = D;
end
endmodule
// --------------------------------------------------------
`ifndef SIMLIB_NOSR
module \$dlatchsr (EN, SET, CLR, D, Q);
parameter WIDTH = 0;
parameter EN_POLARITY = 1'b1;
parameter SET_POLARITY = 1'b1;
parameter CLR_POLARITY = 1'b1;
input EN;
input [WIDTH-1:0] SET, CLR, D;
output reg [WIDTH-1:0] Q;
wire pos_en = EN == EN_POLARITY;
wire [WIDTH-1:0] pos_set = SET_POLARITY ? SET : ~SET;
wire [WIDTH-1:0] pos_clr = CLR_POLARITY ? CLR : ~CLR;
genvar i;
generate
for (i = 0; i < WIDTH; i = i+1) begin:bit
always @*
if (pos_clr[i])
Q[i] = 0;
else if (pos_set[i])
Q[i] = 1;
else if (pos_en)
Q[i] = D[i];
end
endgenerate
endmodule
`endif
// --------------------------------------------------------
module \$fsm (CLK, ARST, CTRL_IN, CTRL_OUT);
parameter NAME = "";
parameter CLK_POLARITY = 1'b1;
parameter ARST_POLARITY = 1'b1;
parameter CTRL_IN_WIDTH = 1;
parameter CTRL_OUT_WIDTH = 1;
parameter STATE_BITS = 1;
parameter STATE_NUM = 1;
parameter STATE_NUM_LOG2 = 1;
parameter STATE_RST = 0;
parameter STATE_TABLE = 1'b0;
parameter TRANS_NUM = 1;
parameter TRANS_TABLE = 4'b0x0x;
input CLK, ARST;
input [CTRL_IN_WIDTH-1:0] CTRL_IN;
output reg [CTRL_OUT_WIDTH-1:0] CTRL_OUT;
wire pos_clk = CLK == CLK_POLARITY;
wire pos_arst = ARST == ARST_POLARITY;
reg [STATE_BITS-1:0] state;
reg [STATE_BITS-1:0] state_tmp;
reg [STATE_BITS-1:0] next_state;
reg [STATE_BITS-1:0] tr_state_in;
reg [STATE_BITS-1:0] tr_state_out;
reg [CTRL_IN_WIDTH-1:0] tr_ctrl_in;
reg [CTRL_OUT_WIDTH-1:0] tr_ctrl_out;
integer i;
task tr_fetch;
input [31:0] tr_num;
reg [31:0] tr_pos;
reg [STATE_NUM_LOG2-1:0] state_num;
begin
tr_pos = (2*STATE_NUM_LOG2+CTRL_IN_WIDTH+CTRL_OUT_WIDTH)*tr_num;
tr_ctrl_out = TRANS_TABLE >> tr_pos;
tr_pos = tr_pos + CTRL_OUT_WIDTH;
state_num = TRANS_TABLE >> tr_pos;
tr_state_out = STATE_TABLE >> (STATE_BITS*state_num);
tr_pos = tr_pos + STATE_NUM_LOG2;
tr_ctrl_in = TRANS_TABLE >> tr_pos;
tr_pos = tr_pos + CTRL_IN_WIDTH;
state_num = TRANS_TABLE >> tr_pos;
tr_state_in = STATE_TABLE >> (STATE_BITS*state_num);
tr_pos = tr_pos + STATE_NUM_LOG2;
end
endtask
always @(posedge pos_clk, posedge pos_arst) begin
if (pos_arst) begin
state_tmp = STATE_TABLE[STATE_BITS*(STATE_RST+1)-1:STATE_BITS*STATE_RST];
for (i = 0; i < STATE_BITS; i = i+1)
if (state_tmp[i] === 1'bz)
state_tmp[i] = 0;
state <= state_tmp;
end else begin
state_tmp = next_state;
for (i = 0; i < STATE_BITS; i = i+1)
if (state_tmp[i] === 1'bz)
state_tmp[i] = 0;
state <= state_tmp;
end
end
always @(state, CTRL_IN) begin
next_state <= STATE_TABLE[STATE_BITS*(STATE_RST+1)-1:STATE_BITS*STATE_RST];
CTRL_OUT <= 'bx;
// $display("---");
// $display("Q: %b %b", state, CTRL_IN);
for (i = 0; i < TRANS_NUM; i = i+1) begin
tr_fetch(i);
// $display("T: %b %b -> %b %b [%d]", tr_state_in, tr_ctrl_in, tr_state_out, tr_ctrl_out, i);
casez ({state, CTRL_IN})
{tr_state_in, tr_ctrl_in}: begin
// $display("-> %b %b <- MATCH", state, CTRL_IN);
{next_state, CTRL_OUT} <= {tr_state_out, tr_ctrl_out};
end
endcase
end
end
endmodule
// --------------------------------------------------------
`ifndef SIMLIB_NOMEM
module \$memrd (CLK, EN, ADDR, DATA);
parameter MEMID = "";
parameter ABITS = 8;
parameter WIDTH = 8;
parameter CLK_ENABLE = 0;
parameter CLK_POLARITY = 0;
parameter TRANSPARENT = 0;
input CLK, EN;
input [ABITS-1:0] ADDR;
output [WIDTH-1:0] DATA;
initial begin
if (MEMID != "") begin
$display("ERROR: Found non-simulatable instance of $memrd!");
$finish;
end
end
endmodule
// --------------------------------------------------------
module \$memwr (CLK, EN, ADDR, DATA);
parameter MEMID = "";
parameter ABITS = 8;
parameter WIDTH = 8;
parameter CLK_ENABLE = 0;
parameter CLK_POLARITY = 0;
parameter PRIORITY = 0;
input CLK;
input [WIDTH-1:0] EN;
input [ABITS-1:0] ADDR;
input [WIDTH-1:0] DATA;
initial begin
if (MEMID != "") begin
$display("ERROR: Found non-simulatable instance of $memwr!");
$finish;
end
end
endmodule
// --------------------------------------------------------
module \$meminit (ADDR, DATA);
parameter MEMID = "";
parameter ABITS = 8;
parameter WIDTH = 8;
parameter WORDS = 1;
parameter PRIORITY = 0;
input [ABITS-1:0] ADDR;
input [WORDS*WIDTH-1:0] DATA;
initial begin
if (MEMID != "") begin
$display("ERROR: Found non-simulatable instance of $meminit!");
$finish;
end
end
endmodule
// --------------------------------------------------------
module \$mem (RD_CLK, RD_EN, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA);
parameter MEMID = "";
parameter signed SIZE = 4;
parameter signed OFFSET = 0;
parameter signed ABITS = 2;
parameter signed WIDTH = 8;
parameter signed INIT = 1'bx;
parameter signed RD_PORTS = 1;
parameter RD_CLK_ENABLE = 1'b1;
parameter RD_CLK_POLARITY = 1'b1;
parameter RD_TRANSPARENT = 1'b1;
parameter signed WR_PORTS = 1;
parameter WR_CLK_ENABLE = 1'b1;
parameter WR_CLK_POLARITY = 1'b1;
input [RD_PORTS-1:0] RD_CLK;
input [RD_PORTS-1:0] RD_EN;
input [RD_PORTS*ABITS-1:0] RD_ADDR;
output reg [RD_PORTS*WIDTH-1:0] RD_DATA;
input [WR_PORTS-1:0] WR_CLK;
input [WR_PORTS*WIDTH-1:0] WR_EN;
input [WR_PORTS*ABITS-1:0] WR_ADDR;
input [WR_PORTS*WIDTH-1:0] WR_DATA;
reg [WIDTH-1:0] memory [SIZE-1:0];
integer i, j;
reg [WR_PORTS-1:0] LAST_WR_CLK;
reg [RD_PORTS-1:0] LAST_RD_CLK;
function port_active;
input clk_enable;
input clk_polarity;
input last_clk;
input this_clk;
begin
casez ({clk_enable, clk_polarity, last_clk, this_clk})
4'b0???: port_active = 1;
4'b1101: port_active = 1;
4'b1010: port_active = 1;
default: port_active = 0;
endcase
end
endfunction
initial begin
for (i = 0; i < SIZE; i = i+1)
memory[i] = INIT >>> (i*WIDTH);
end
always @(RD_CLK, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA) begin
`ifdef SIMLIB_MEMDELAY
#`SIMLIB_MEMDELAY;
`endif
for (i = 0; i < RD_PORTS; i = i+1) begin
if (!RD_TRANSPARENT[i] && RD_CLK_ENABLE[i] && RD_EN[i] && port_active(RD_CLK_ENABLE[i], RD_CLK_POLARITY[i], LAST_RD_CLK[i], RD_CLK[i])) begin
// $display("Read from %s: addr=%b data=%b", MEMID, RD_ADDR[i*ABITS +: ABITS], memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET]);
RD_DATA[i*WIDTH +: WIDTH] <= memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET];
end
end
for (i = 0; i < WR_PORTS; i = i+1) begin
if (port_active(WR_CLK_ENABLE[i], WR_CLK_POLARITY[i], LAST_WR_CLK[i], WR_CLK[i]))
for (j = 0; j < WIDTH; j = j+1)
if (WR_EN[i*WIDTH+j]) begin
// $display("Write to %s: addr=%b data=%b", MEMID, WR_ADDR[i*ABITS +: ABITS], WR_DATA[i*WIDTH+j]);
memory[WR_ADDR[i*ABITS +: ABITS] - OFFSET][j] = WR_DATA[i*WIDTH+j];
end
end
for (i = 0; i < RD_PORTS; i = i+1) begin
if ((RD_TRANSPARENT[i] || !RD_CLK_ENABLE[i]) && port_active(RD_CLK_ENABLE[i], RD_CLK_POLARITY[i], LAST_RD_CLK[i], RD_CLK[i])) begin
// $display("Transparent read from %s: addr=%b data=%b", MEMID, RD_ADDR[i*ABITS +: ABITS], memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET]);
RD_DATA[i*WIDTH +: WIDTH] <= memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET];
end
end
LAST_RD_CLK <= RD_CLK;
LAST_WR_CLK <= WR_CLK;
end
endmodule
`endif
// --------------------------------------------------------
|
/******************************************************************************
-- (c) Copyright 2006 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
*****************************************************************************
*
* Filename: BLK_MEM_GEN_v8_2.v
*
* Description:
* This file is the Verilog behvarial model for the
* Block Memory Generator Core.
*
*****************************************************************************
* Author: Xilinx
*
* History: Jan 11, 2006 Initial revision
* Jun 11, 2007 Added independent register stages for
* Port A and Port B (IP1_Jm/v2.5)
* Aug 28, 2007 Added mux pipeline stages feature (IP2_Jm/v2.6)
* Mar 13, 2008 Behavioral model optimizations
* April 07, 2009 : Added support for Spartan-6 and Virtex-6
* features, including the following:
* (i) error injection, detection and/or correction
* (ii) reset priority
* (iii) special reset behavior
*
*****************************************************************************/
`timescale 1ps/1ps
module STATE_LOGIC_v8_2 (O, I0, I1, I2, I3, I4, I5);
parameter INIT = 64'h0000000000000000;
input I0, I1, I2, I3, I4, I5;
output O;
reg O;
reg tmp;
always @( I5 or I4 or I3 or I2 or I1 or I0 ) begin
tmp = I0 ^ I1 ^ I2 ^ I3 ^ I4 ^ I5;
if ( tmp == 0 || tmp == 1)
O = INIT[{I5, I4, I3, I2, I1, I0}];
end
endmodule
module beh_vlog_muxf7_v8_2 (O, I0, I1, S);
output O;
reg O;
input I0, I1, S;
always @(I0 or I1 or S)
if (S)
O = I1;
else
O = I0;
endmodule
module beh_vlog_ff_clr_v8_2 (Q, C, CLR, D);
parameter INIT = 0;
localparam FLOP_DELAY = 100;
output Q;
input C, CLR, D;
reg Q;
initial Q= 1'b0;
always @(posedge C )
if (CLR)
Q<= 1'b0;
else
Q<= #FLOP_DELAY D;
endmodule
module beh_vlog_ff_pre_v8_2 (Q, C, D, PRE);
parameter INIT = 0;
localparam FLOP_DELAY = 100;
output Q;
input C, D, PRE;
reg Q;
initial Q= 1'b0;
always @(posedge C )
if (PRE)
Q <= 1'b1;
else
Q <= #FLOP_DELAY D;
endmodule
module beh_vlog_ff_ce_clr_v8_2 (Q, C, CE, CLR, D);
parameter INIT = 0;
localparam FLOP_DELAY = 100;
output Q;
input C, CE, CLR, D;
reg Q;
initial Q= 1'b0;
always @(posedge C )
if (CLR)
Q <= 1'b0;
else if (CE)
Q <= #FLOP_DELAY D;
endmodule
module write_netlist_v8_2
#(
parameter C_AXI_TYPE = 0
)
(
S_ACLK, S_ARESETN, S_AXI_AWVALID, S_AXI_WVALID, S_AXI_BREADY,
w_last_c, bready_timeout_c, aw_ready_r, S_AXI_WREADY, S_AXI_BVALID,
S_AXI_WR_EN, addr_en_c, incr_addr_c, bvalid_c
);
input S_ACLK;
input S_ARESETN;
input S_AXI_AWVALID;
input S_AXI_WVALID;
input S_AXI_BREADY;
input w_last_c;
input bready_timeout_c;
output aw_ready_r;
output S_AXI_WREADY;
output S_AXI_BVALID;
output S_AXI_WR_EN;
output addr_en_c;
output incr_addr_c;
output bvalid_c;
//-------------------------------------------------------------------------
//AXI LITE
//-------------------------------------------------------------------------
generate if (C_AXI_TYPE == 0 ) begin : gbeh_axi_lite_sm
wire w_ready_r_7;
wire w_ready_c;
wire aw_ready_c;
wire NlwRenamedSignal_bvalid_c;
wire NlwRenamedSignal_incr_addr_c;
wire present_state_FSM_FFd3_13;
wire present_state_FSM_FFd2_14;
wire present_state_FSM_FFd1_15;
wire present_state_FSM_FFd4_16;
wire present_state_FSM_FFd4_In;
wire present_state_FSM_FFd3_In;
wire present_state_FSM_FFd2_In;
wire present_state_FSM_FFd1_In;
wire present_state_FSM_FFd4_In1_21;
wire [0:0] Mmux_aw_ready_c ;
begin
assign
S_AXI_WREADY = w_ready_r_7,
S_AXI_BVALID = NlwRenamedSignal_incr_addr_c,
S_AXI_WR_EN = NlwRenamedSignal_bvalid_c,
incr_addr_c = NlwRenamedSignal_incr_addr_c,
bvalid_c = NlwRenamedSignal_bvalid_c;
assign NlwRenamedSignal_incr_addr_c = 1'b0;
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
aw_ready_r_2 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( aw_ready_c),
.Q ( aw_ready_r)
);
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
w_ready_r (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( w_ready_c),
.Q ( w_ready_r_7)
);
beh_vlog_ff_pre_v8_2 #(
.INIT (1'b1))
present_state_FSM_FFd4 (
.C ( S_ACLK),
.D ( present_state_FSM_FFd4_In),
.PRE ( S_ARESETN),
.Q ( present_state_FSM_FFd4_16)
);
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
present_state_FSM_FFd3 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd3_In),
.Q ( present_state_FSM_FFd3_13)
);
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
present_state_FSM_FFd2 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd2_In),
.Q ( present_state_FSM_FFd2_14)
);
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
present_state_FSM_FFd1 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd1_In),
.Q ( present_state_FSM_FFd1_15)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000055554440))
present_state_FSM_FFd3_In1 (
.I0 ( S_AXI_WVALID),
.I1 ( S_AXI_AWVALID),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( present_state_FSM_FFd4_16),
.I4 ( present_state_FSM_FFd3_13),
.I5 (1'b0),
.O ( present_state_FSM_FFd3_In)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000088880800))
present_state_FSM_FFd2_In1 (
.I0 ( S_AXI_AWVALID),
.I1 ( S_AXI_WVALID),
.I2 ( bready_timeout_c),
.I3 ( present_state_FSM_FFd2_14),
.I4 ( present_state_FSM_FFd4_16),
.I5 (1'b0),
.O ( present_state_FSM_FFd2_In)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h00000000AAAA2000))
Mmux_addr_en_c_0_1 (
.I0 ( S_AXI_AWVALID),
.I1 ( bready_timeout_c),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( S_AXI_WVALID),
.I4 ( present_state_FSM_FFd4_16),
.I5 (1'b0),
.O ( addr_en_c)
);
STATE_LOGIC_v8_2 #(
.INIT (64'hF5F07570F5F05500))
Mmux_w_ready_c_0_1 (
.I0 ( S_AXI_WVALID),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd3_13),
.I4 ( present_state_FSM_FFd4_16),
.I5 ( present_state_FSM_FFd2_14),
.O ( w_ready_c)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h88808880FFFF8880))
present_state_FSM_FFd1_In1 (
.I0 ( S_AXI_WVALID),
.I1 ( bready_timeout_c),
.I2 ( present_state_FSM_FFd3_13),
.I3 ( present_state_FSM_FFd2_14),
.I4 ( present_state_FSM_FFd1_15),
.I5 ( S_AXI_BREADY),
.O ( present_state_FSM_FFd1_In)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h00000000000000A8))
Mmux_S_AXI_WR_EN_0_1 (
.I0 ( S_AXI_WVALID),
.I1 ( present_state_FSM_FFd2_14),
.I2 ( present_state_FSM_FFd3_13),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( NlwRenamedSignal_bvalid_c)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h2F0F27072F0F2200))
present_state_FSM_FFd4_In1 (
.I0 ( S_AXI_WVALID),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd3_13),
.I4 ( present_state_FSM_FFd4_16),
.I5 ( present_state_FSM_FFd2_14),
.O ( present_state_FSM_FFd4_In1_21)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h00000000000000F8))
present_state_FSM_FFd4_In2 (
.I0 ( present_state_FSM_FFd1_15),
.I1 ( S_AXI_BREADY),
.I2 ( present_state_FSM_FFd4_In1_21),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( present_state_FSM_FFd4_In)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h7535753575305500))
Mmux_aw_ready_c_0_1 (
.I0 ( S_AXI_AWVALID),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_WVALID),
.I3 ( present_state_FSM_FFd4_16),
.I4 ( present_state_FSM_FFd3_13),
.I5 ( present_state_FSM_FFd2_14),
.O ( Mmux_aw_ready_c[0])
);
STATE_LOGIC_v8_2 #(
.INIT (64'h00000000000000F8))
Mmux_aw_ready_c_0_2 (
.I0 ( present_state_FSM_FFd1_15),
.I1 ( S_AXI_BREADY),
.I2 ( Mmux_aw_ready_c[0]),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( aw_ready_c)
);
end
end
endgenerate
//---------------------------------------------------------------------
// AXI FULL
//---------------------------------------------------------------------
generate if (C_AXI_TYPE == 1 ) begin : gbeh_axi_full_sm
wire w_ready_r_8;
wire w_ready_c;
wire aw_ready_c;
wire NlwRenamedSig_OI_bvalid_c;
wire present_state_FSM_FFd1_16;
wire present_state_FSM_FFd4_17;
wire present_state_FSM_FFd3_18;
wire present_state_FSM_FFd2_19;
wire present_state_FSM_FFd4_In;
wire present_state_FSM_FFd3_In;
wire present_state_FSM_FFd2_In;
wire present_state_FSM_FFd1_In;
wire present_state_FSM_FFd2_In1_24;
wire present_state_FSM_FFd4_In1_25;
wire N2;
wire N4;
begin
assign
S_AXI_WREADY = w_ready_r_8,
bvalid_c = NlwRenamedSig_OI_bvalid_c,
S_AXI_BVALID = 1'b0;
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
aw_ready_r_2
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( aw_ready_c),
.Q ( aw_ready_r)
);
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
w_ready_r
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( w_ready_c),
.Q ( w_ready_r_8)
);
beh_vlog_ff_pre_v8_2 #(
.INIT (1'b1))
present_state_FSM_FFd4
(
.C ( S_ACLK),
.D ( present_state_FSM_FFd4_In),
.PRE ( S_ARESETN),
.Q ( present_state_FSM_FFd4_17)
);
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
present_state_FSM_FFd3
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd3_In),
.Q ( present_state_FSM_FFd3_18)
);
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
present_state_FSM_FFd2
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd2_In),
.Q ( present_state_FSM_FFd2_19)
);
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
present_state_FSM_FFd1
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd1_In),
.Q ( present_state_FSM_FFd1_16)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000000005540))
present_state_FSM_FFd3_In1
(
.I0 ( S_AXI_WVALID),
.I1 ( present_state_FSM_FFd4_17),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd3_18),
.I4 (1'b0),
.I5 (1'b0),
.O ( present_state_FSM_FFd3_In)
);
STATE_LOGIC_v8_2 #(
.INIT (64'hBF3FBB33AF0FAA00))
Mmux_aw_ready_c_0_2
(
.I0 ( S_AXI_BREADY),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd1_16),
.I4 ( present_state_FSM_FFd4_17),
.I5 ( NlwRenamedSig_OI_bvalid_c),
.O ( aw_ready_c)
);
STATE_LOGIC_v8_2 #(
.INIT (64'hAAAAAAAA20000000))
Mmux_addr_en_c_0_1
(
.I0 ( S_AXI_AWVALID),
.I1 ( bready_timeout_c),
.I2 ( present_state_FSM_FFd2_19),
.I3 ( S_AXI_WVALID),
.I4 ( w_last_c),
.I5 ( present_state_FSM_FFd4_17),
.O ( addr_en_c)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h00000000000000A8))
Mmux_S_AXI_WR_EN_0_1
(
.I0 ( S_AXI_WVALID),
.I1 ( present_state_FSM_FFd2_19),
.I2 ( present_state_FSM_FFd3_18),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( S_AXI_WR_EN)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000000002220))
Mmux_incr_addr_c_0_1
(
.I0 ( S_AXI_WVALID),
.I1 ( w_last_c),
.I2 ( present_state_FSM_FFd2_19),
.I3 ( present_state_FSM_FFd3_18),
.I4 (1'b0),
.I5 (1'b0),
.O ( incr_addr_c)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000000008880))
Mmux_aw_ready_c_0_11
(
.I0 ( S_AXI_WVALID),
.I1 ( w_last_c),
.I2 ( present_state_FSM_FFd2_19),
.I3 ( present_state_FSM_FFd3_18),
.I4 (1'b0),
.I5 (1'b0),
.O ( NlwRenamedSig_OI_bvalid_c)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h000000000000D5C0))
present_state_FSM_FFd2_In1
(
.I0 ( w_last_c),
.I1 ( S_AXI_AWVALID),
.I2 ( present_state_FSM_FFd4_17),
.I3 ( present_state_FSM_FFd3_18),
.I4 (1'b0),
.I5 (1'b0),
.O ( present_state_FSM_FFd2_In1_24)
);
STATE_LOGIC_v8_2 #(
.INIT (64'hFFFFAAAA08AAAAAA))
present_state_FSM_FFd2_In2
(
.I0 ( present_state_FSM_FFd2_19),
.I1 ( S_AXI_AWVALID),
.I2 ( bready_timeout_c),
.I3 ( w_last_c),
.I4 ( S_AXI_WVALID),
.I5 ( present_state_FSM_FFd2_In1_24),
.O ( present_state_FSM_FFd2_In)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h00C0004000C00000))
present_state_FSM_FFd4_In1
(
.I0 ( S_AXI_AWVALID),
.I1 ( w_last_c),
.I2 ( S_AXI_WVALID),
.I3 ( bready_timeout_c),
.I4 ( present_state_FSM_FFd3_18),
.I5 ( present_state_FSM_FFd2_19),
.O ( present_state_FSM_FFd4_In1_25)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h00000000FFFF88F8))
present_state_FSM_FFd4_In2
(
.I0 ( present_state_FSM_FFd1_16),
.I1 ( S_AXI_BREADY),
.I2 ( present_state_FSM_FFd4_17),
.I3 ( S_AXI_AWVALID),
.I4 ( present_state_FSM_FFd4_In1_25),
.I5 (1'b0),
.O ( present_state_FSM_FFd4_In)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000000000007))
Mmux_w_ready_c_0_SW0
(
.I0 ( w_last_c),
.I1 ( S_AXI_WVALID),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( N2)
);
STATE_LOGIC_v8_2 #(
.INIT (64'hFABAFABAFAAAF000))
Mmux_w_ready_c_0_Q
(
.I0 ( N2),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd4_17),
.I4 ( present_state_FSM_FFd3_18),
.I5 ( present_state_FSM_FFd2_19),
.O ( w_ready_c)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000000000008))
Mmux_aw_ready_c_0_11_SW0
(
.I0 ( bready_timeout_c),
.I1 ( S_AXI_WVALID),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( N4)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h88808880FFFF8880))
present_state_FSM_FFd1_In1
(
.I0 ( w_last_c),
.I1 ( N4),
.I2 ( present_state_FSM_FFd2_19),
.I3 ( present_state_FSM_FFd3_18),
.I4 ( present_state_FSM_FFd1_16),
.I5 ( S_AXI_BREADY),
.O ( present_state_FSM_FFd1_In)
);
end
end
endgenerate
endmodule
module read_netlist_v8_2 #(
parameter C_AXI_TYPE = 1,
parameter C_ADDRB_WIDTH = 12
) ( S_AXI_R_LAST_INT, S_ACLK, S_ARESETN, S_AXI_ARVALID,
S_AXI_RREADY,S_AXI_INCR_ADDR,S_AXI_ADDR_EN,
S_AXI_SINGLE_TRANS,S_AXI_MUX_SEL, S_AXI_R_LAST, S_AXI_ARREADY,
S_AXI_RLAST, S_AXI_RVALID, S_AXI_RD_EN, S_AXI_ARLEN);
input S_AXI_R_LAST_INT;
input S_ACLK;
input S_ARESETN;
input S_AXI_ARVALID;
input S_AXI_RREADY;
output S_AXI_INCR_ADDR;
output S_AXI_ADDR_EN;
output S_AXI_SINGLE_TRANS;
output S_AXI_MUX_SEL;
output S_AXI_R_LAST;
output S_AXI_ARREADY;
output S_AXI_RLAST;
output S_AXI_RVALID;
output S_AXI_RD_EN;
input [7:0] S_AXI_ARLEN;
wire present_state_FSM_FFd1_13 ;
wire present_state_FSM_FFd2_14 ;
wire gaxi_full_sm_outstanding_read_r_15 ;
wire gaxi_full_sm_ar_ready_r_16 ;
wire gaxi_full_sm_r_last_r_17 ;
wire NlwRenamedSig_OI_gaxi_full_sm_r_valid_r ;
wire gaxi_full_sm_r_valid_c ;
wire S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o ;
wire gaxi_full_sm_ar_ready_c ;
wire gaxi_full_sm_outstanding_read_c ;
wire NlwRenamedSig_OI_S_AXI_R_LAST ;
wire S_AXI_ARLEN_7_GND_8_o_equal_1_o ;
wire present_state_FSM_FFd2_In ;
wire present_state_FSM_FFd1_In ;
wire Mmux_S_AXI_R_LAST13 ;
wire N01 ;
wire N2 ;
wire Mmux_gaxi_full_sm_ar_ready_c11 ;
wire N4 ;
wire N8 ;
wire N9 ;
wire N10 ;
wire N11 ;
wire N12 ;
wire N13 ;
assign
S_AXI_R_LAST = NlwRenamedSig_OI_S_AXI_R_LAST,
S_AXI_ARREADY = gaxi_full_sm_ar_ready_r_16,
S_AXI_RLAST = gaxi_full_sm_r_last_r_17,
S_AXI_RVALID = NlwRenamedSig_OI_gaxi_full_sm_r_valid_r;
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
gaxi_full_sm_outstanding_read_r (
.C (S_ACLK),
.CLR(S_ARESETN),
.D(gaxi_full_sm_outstanding_read_c),
.Q(gaxi_full_sm_outstanding_read_r_15)
);
beh_vlog_ff_ce_clr_v8_2 #(
.INIT (1'b0))
gaxi_full_sm_r_valid_r (
.C (S_ACLK),
.CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
.CLR (S_ARESETN),
.D (gaxi_full_sm_r_valid_c),
.Q (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r)
);
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
gaxi_full_sm_ar_ready_r (
.C (S_ACLK),
.CLR (S_ARESETN),
.D (gaxi_full_sm_ar_ready_c),
.Q (gaxi_full_sm_ar_ready_r_16)
);
beh_vlog_ff_ce_clr_v8_2 #(
.INIT(1'b0))
gaxi_full_sm_r_last_r (
.C (S_ACLK),
.CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
.CLR (S_ARESETN),
.D (NlwRenamedSig_OI_S_AXI_R_LAST),
.Q (gaxi_full_sm_r_last_r_17)
);
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
present_state_FSM_FFd2 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd2_In),
.Q ( present_state_FSM_FFd2_14)
);
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
present_state_FSM_FFd1 (
.C (S_ACLK),
.CLR (S_ARESETN),
.D (present_state_FSM_FFd1_In),
.Q (present_state_FSM_FFd1_13)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h000000000000000B))
S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o1 (
.I0 ( S_AXI_RREADY),
.I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000000000008))
Mmux_S_AXI_SINGLE_TRANS11 (
.I0 (S_AXI_ARVALID),
.I1 (S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O (S_AXI_SINGLE_TRANS)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000000000004))
Mmux_S_AXI_ADDR_EN11 (
.I0 (present_state_FSM_FFd1_13),
.I1 (S_AXI_ARVALID),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O (S_AXI_ADDR_EN)
);
STATE_LOGIC_v8_2 #(
.INIT (64'hECEE2022EEEE2022))
present_state_FSM_FFd2_In1 (
.I0 ( S_AXI_ARVALID),
.I1 ( present_state_FSM_FFd1_13),
.I2 ( S_AXI_RREADY),
.I3 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I4 ( present_state_FSM_FFd2_14),
.I5 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.O ( present_state_FSM_FFd2_In)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000044440444))
Mmux_S_AXI_R_LAST131 (
.I0 ( present_state_FSM_FFd1_13),
.I1 ( S_AXI_ARVALID),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I4 ( S_AXI_RREADY),
.I5 (1'b0),
.O ( Mmux_S_AXI_R_LAST13)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h4000FFFF40004000))
Mmux_S_AXI_INCR_ADDR11 (
.I0 ( S_AXI_R_LAST_INT),
.I1 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( present_state_FSM_FFd1_13),
.I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I5 ( Mmux_S_AXI_R_LAST13),
.O ( S_AXI_INCR_ADDR)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h00000000000000FE))
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_SW0 (
.I0 ( S_AXI_ARLEN[2]),
.I1 ( S_AXI_ARLEN[1]),
.I2 ( S_AXI_ARLEN[0]),
.I3 ( 1'b0),
.I4 ( 1'b0),
.I5 ( 1'b0),
.O ( N01)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000000000001))
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_Q (
.I0 ( S_AXI_ARLEN[7]),
.I1 ( S_AXI_ARLEN[6]),
.I2 ( S_AXI_ARLEN[5]),
.I3 ( S_AXI_ARLEN[4]),
.I4 ( S_AXI_ARLEN[3]),
.I5 ( N01),
.O ( S_AXI_ARLEN_7_GND_8_o_equal_1_o)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000000000007))
Mmux_gaxi_full_sm_outstanding_read_c1_SW0 (
.I0 ( S_AXI_ARVALID),
.I1 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I2 ( 1'b0),
.I3 ( 1'b0),
.I4 ( 1'b0),
.I5 ( 1'b0),
.O ( N2)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0020000002200200))
Mmux_gaxi_full_sm_outstanding_read_c1 (
.I0 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I1 ( S_AXI_RREADY),
.I2 ( present_state_FSM_FFd1_13),
.I3 ( present_state_FSM_FFd2_14),
.I4 ( gaxi_full_sm_outstanding_read_r_15),
.I5 ( N2),
.O ( gaxi_full_sm_outstanding_read_c)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000000004555))
Mmux_gaxi_full_sm_ar_ready_c12 (
.I0 ( S_AXI_ARVALID),
.I1 ( S_AXI_RREADY),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I4 ( 1'b0),
.I5 ( 1'b0),
.O ( Mmux_gaxi_full_sm_ar_ready_c11)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h00000000000000EF))
Mmux_S_AXI_R_LAST11_SW0 (
.I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I1 ( S_AXI_RREADY),
.I2 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I3 ( 1'b0),
.I4 ( 1'b0),
.I5 ( 1'b0),
.O ( N4)
);
STATE_LOGIC_v8_2 #(
.INIT (64'hFCAAFC0A00AA000A))
Mmux_S_AXI_R_LAST11 (
.I0 ( S_AXI_ARVALID),
.I1 ( gaxi_full_sm_outstanding_read_r_15),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( present_state_FSM_FFd1_13),
.I4 ( N4),
.I5 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
.O ( gaxi_full_sm_r_valid_c)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h00000000AAAAAA08))
S_AXI_MUX_SEL1 (
.I0 (present_state_FSM_FFd1_13),
.I1 (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I2 (S_AXI_RREADY),
.I3 (present_state_FSM_FFd2_14),
.I4 (gaxi_full_sm_outstanding_read_r_15),
.I5 (1'b0),
.O (S_AXI_MUX_SEL)
);
STATE_LOGIC_v8_2 #(
.INIT (64'hF3F3F755A2A2A200))
Mmux_S_AXI_RD_EN11 (
.I0 ( present_state_FSM_FFd1_13),
.I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I2 ( S_AXI_RREADY),
.I3 ( gaxi_full_sm_outstanding_read_r_15),
.I4 ( present_state_FSM_FFd2_14),
.I5 ( S_AXI_ARVALID),
.O ( S_AXI_RD_EN)
);
beh_vlog_muxf7_v8_2 present_state_FSM_FFd1_In3 (
.I0 ( N8),
.I1 ( N9),
.S ( present_state_FSM_FFd1_13),
.O ( present_state_FSM_FFd1_In)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h000000005410F4F0))
present_state_FSM_FFd1_In3_F (
.I0 ( S_AXI_RREADY),
.I1 ( present_state_FSM_FFd2_14),
.I2 ( S_AXI_ARVALID),
.I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I5 ( 1'b0),
.O ( N8)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000072FF7272))
present_state_FSM_FFd1_In3_G (
.I0 ( present_state_FSM_FFd2_14),
.I1 ( S_AXI_R_LAST_INT),
.I2 ( gaxi_full_sm_outstanding_read_r_15),
.I3 ( S_AXI_RREADY),
.I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I5 ( 1'b0),
.O ( N9)
);
beh_vlog_muxf7_v8_2 Mmux_gaxi_full_sm_ar_ready_c14 (
.I0 ( N10),
.I1 ( N11),
.S ( present_state_FSM_FFd1_13),
.O ( gaxi_full_sm_ar_ready_c)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h00000000FFFF88A8))
Mmux_gaxi_full_sm_ar_ready_c14_F (
.I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I1 ( S_AXI_RREADY),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I4 ( Mmux_gaxi_full_sm_ar_ready_c11),
.I5 ( 1'b0),
.O ( N10)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h000000008D008D8D))
Mmux_gaxi_full_sm_ar_ready_c14_G (
.I0 ( present_state_FSM_FFd2_14),
.I1 ( S_AXI_R_LAST_INT),
.I2 ( gaxi_full_sm_outstanding_read_r_15),
.I3 ( S_AXI_RREADY),
.I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I5 ( 1'b0),
.O ( N11)
);
beh_vlog_muxf7_v8_2 Mmux_S_AXI_R_LAST1 (
.I0 ( N12),
.I1 ( N13),
.S ( present_state_FSM_FFd1_13),
.O ( NlwRenamedSig_OI_S_AXI_R_LAST)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000088088888))
Mmux_S_AXI_R_LAST1_F (
.I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I1 ( S_AXI_ARVALID),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( S_AXI_RREADY),
.I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I5 ( 1'b0),
.O ( N12)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h00000000E400E4E4))
Mmux_S_AXI_R_LAST1_G (
.I0 ( present_state_FSM_FFd2_14),
.I1 ( gaxi_full_sm_outstanding_read_r_15),
.I2 ( S_AXI_R_LAST_INT),
.I3 ( S_AXI_RREADY),
.I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I5 ( 1'b0),
.O ( N13)
);
endmodule
module blk_mem_axi_write_wrapper_beh_v8_2
# (
// AXI Interface related parameters start here
parameter C_INTERFACE_TYPE = 0, // 0: Native Interface; 1: AXI Interface
parameter C_AXI_TYPE = 0, // 0: AXI Lite; 1: AXI Full;
parameter C_AXI_SLAVE_TYPE = 0, // 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;
parameter C_MEMORY_TYPE = 0, // 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;
parameter C_WRITE_DEPTH_A = 0,
parameter C_AXI_AWADDR_WIDTH = 32,
parameter C_ADDRA_WIDTH = 12,
parameter C_AXI_WDATA_WIDTH = 32,
parameter C_HAS_AXI_ID = 0,
parameter C_AXI_ID_WIDTH = 4,
// AXI OUTSTANDING WRITES
parameter C_AXI_OS_WR = 2
)
(
// AXI Global Signals
input S_ACLK,
input S_ARESETN,
// AXI Full/Lite Slave Write Channel (write side)
input [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
input [C_AXI_AWADDR_WIDTH-1:0] S_AXI_AWADDR,
input [8-1:0] S_AXI_AWLEN,
input [2:0] S_AXI_AWSIZE,
input [1:0] S_AXI_AWBURST,
input S_AXI_AWVALID,
output S_AXI_AWREADY,
input S_AXI_WVALID,
output S_AXI_WREADY,
output reg [C_AXI_ID_WIDTH-1:0] S_AXI_BID = 0,
output S_AXI_BVALID,
input S_AXI_BREADY,
// Signals for BMG interface
output [C_ADDRA_WIDTH-1:0] S_AXI_AWADDR_OUT,
output S_AXI_WR_EN
);
localparam FLOP_DELAY = 100; // 100 ps
localparam C_RANGE = ((C_AXI_WDATA_WIDTH == 8)?0:
((C_AXI_WDATA_WIDTH==16)?1:
((C_AXI_WDATA_WIDTH==32)?2:
((C_AXI_WDATA_WIDTH==64)?3:
((C_AXI_WDATA_WIDTH==128)?4:
((C_AXI_WDATA_WIDTH==256)?5:0))))));
wire bvalid_c ;
reg bready_timeout_c = 0;
wire [1:0] bvalid_rd_cnt_c;
reg bvalid_r = 0;
reg [2:0] bvalid_count_r = 0;
reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?
C_AXI_AWADDR_WIDTH:C_ADDRA_WIDTH)-1:0] awaddr_reg = 0;
reg [1:0] bvalid_wr_cnt_r = 0;
reg [1:0] bvalid_rd_cnt_r = 0;
wire w_last_c ;
wire addr_en_c ;
wire incr_addr_c ;
wire aw_ready_r ;
wire dec_alen_c ;
reg bvalid_d1_c = 0;
reg [7:0] awlen_cntr_r = 0;
reg [7:0] awlen_int = 0;
reg [1:0] awburst_int = 0;
integer total_bytes = 0;
integer wrap_boundary = 0;
integer wrap_base_addr = 0;
integer num_of_bytes_c = 0;
integer num_of_bytes_r = 0;
// Array to store BIDs
reg [C_AXI_ID_WIDTH-1:0] axi_bid_array[3:0] ;
wire S_AXI_BVALID_axi_wr_fsm;
//-------------------------------------
//AXI WRITE FSM COMPONENT INSTANTIATION
//-------------------------------------
write_netlist_v8_2 #(.C_AXI_TYPE(C_AXI_TYPE)) axi_wr_fsm
(
.S_ACLK(S_ACLK),
.S_ARESETN(S_ARESETN),
.S_AXI_AWVALID(S_AXI_AWVALID),
.aw_ready_r(aw_ready_r),
.S_AXI_WVALID(S_AXI_WVALID),
.S_AXI_WREADY(S_AXI_WREADY),
.S_AXI_BREADY(S_AXI_BREADY),
.S_AXI_WR_EN(S_AXI_WR_EN),
.w_last_c(w_last_c),
.bready_timeout_c(bready_timeout_c),
.addr_en_c(addr_en_c),
.incr_addr_c(incr_addr_c),
.bvalid_c(bvalid_c),
.S_AXI_BVALID (S_AXI_BVALID_axi_wr_fsm)
);
//Wrap Address boundary calculation
always@(*) begin
num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWSIZE:0);
total_bytes = (num_of_bytes_r)*(awlen_int+1);
wrap_base_addr = ((awaddr_reg)/((total_bytes==0)?1:total_bytes))*(total_bytes);
wrap_boundary = wrap_base_addr+total_bytes;
end
//-------------------------------------------------------------------------
// BMG address generation
//-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
awaddr_reg <= 0;
num_of_bytes_r <= 0;
awburst_int <= 0;
end else begin
if (addr_en_c == 1'b1) begin
awaddr_reg <= #FLOP_DELAY S_AXI_AWADDR ;
num_of_bytes_r <= num_of_bytes_c;
awburst_int <= ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWBURST:2'b01);
end else if (incr_addr_c == 1'b1) begin
if (awburst_int == 2'b10) begin
if(awaddr_reg == (wrap_boundary-num_of_bytes_r)) begin
awaddr_reg <= wrap_base_addr;
end else begin
awaddr_reg <= awaddr_reg + num_of_bytes_r;
end
end else if (awburst_int == 2'b01 || awburst_int == 2'b11) begin
awaddr_reg <= awaddr_reg + num_of_bytes_r;
end
end
end
end
assign S_AXI_AWADDR_OUT = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?
awaddr_reg[C_AXI_AWADDR_WIDTH-1:C_RANGE]:awaddr_reg);
//-------------------------------------------------------------------------
// AXI wlast generation
//-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
awlen_cntr_r <= 0;
awlen_int <= 0;
end else begin
if (addr_en_c == 1'b1) begin
awlen_int <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;
awlen_cntr_r <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;
end else if (dec_alen_c == 1'b1) begin
awlen_cntr_r <= #FLOP_DELAY awlen_cntr_r - 1 ;
end
end
end
assign w_last_c = (awlen_cntr_r == 0 && S_AXI_WVALID == 1'b1)?1'b1:1'b0;
assign dec_alen_c = (incr_addr_c | w_last_c);
//-------------------------------------------------------------------------
// Generation of bvalid counter for outstanding transactions
//-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
bvalid_count_r <= 0;
end else begin
// bvalid_count_r generation
if (bvalid_c == 1'b1 && bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1) begin
bvalid_count_r <= #FLOP_DELAY bvalid_count_r ;
end else if (bvalid_c == 1'b1) begin
bvalid_count_r <= #FLOP_DELAY bvalid_count_r + 1 ;
end else if (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1 && bvalid_count_r != 0) begin
bvalid_count_r <= #FLOP_DELAY bvalid_count_r - 1 ;
end
end
end
//-------------------------------------------------------------------------
// Generation of bvalid when BID is used
//-------------------------------------------------------------------------
generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
bvalid_r <= 0;
bvalid_d1_c <= 0;
end else begin
// Delay the generation o bvalid_r for generation for BID
bvalid_d1_c <= bvalid_c;
//external bvalid signal generation
if (bvalid_d1_c == 1'b1) begin
bvalid_r <= #FLOP_DELAY 1'b1 ;
end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin
bvalid_r <= #FLOP_DELAY 0 ;
end
end
end
end
endgenerate
//-------------------------------------------------------------------------
// Generation of bvalid when BID is not used
//-------------------------------------------------------------------------
generate if(C_HAS_AXI_ID == 0) begin:gaxi_bvalid_noid_r
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
bvalid_r <= 0;
end else begin
//external bvalid signal generation
if (bvalid_c == 1'b1) begin
bvalid_r <= #FLOP_DELAY 1'b1 ;
end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin
bvalid_r <= #FLOP_DELAY 0 ;
end
end
end
end
endgenerate
//-------------------------------------------------------------------------
// Generation of Bready timeout
//-------------------------------------------------------------------------
always @(bvalid_count_r) begin
// bready_timeout_c generation
if(bvalid_count_r == C_AXI_OS_WR-1) begin
bready_timeout_c <= 1'b1;
end else begin
bready_timeout_c <= 1'b0;
end
end
//-------------------------------------------------------------------------
// Generation of BID
//-------------------------------------------------------------------------
generate if(C_HAS_AXI_ID == 1) begin:gaxi_bid_gen
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
bvalid_wr_cnt_r <= 0;
bvalid_rd_cnt_r <= 0;
end else begin
// STORE AWID IN AN ARRAY
if(bvalid_c == 1'b1) begin
bvalid_wr_cnt_r <= bvalid_wr_cnt_r + 1;
end
// generate BID FROM AWID ARRAY
bvalid_rd_cnt_r <= #FLOP_DELAY bvalid_rd_cnt_c ;
S_AXI_BID <= axi_bid_array[bvalid_rd_cnt_c];
end
end
assign bvalid_rd_cnt_c = (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1)?bvalid_rd_cnt_r+1:bvalid_rd_cnt_r;
//-------------------------------------------------------------------------
// Storing AWID for generation of BID
//-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if(S_ARESETN == 1'b1) begin
axi_bid_array[0] = 0;
axi_bid_array[1] = 0;
axi_bid_array[2] = 0;
axi_bid_array[3] = 0;
end else if(aw_ready_r == 1'b1 && S_AXI_AWVALID == 1'b1) begin
axi_bid_array[bvalid_wr_cnt_r] <= S_AXI_AWID;
end
end
end
endgenerate
assign S_AXI_BVALID = bvalid_r;
assign S_AXI_AWREADY = aw_ready_r;
endmodule
module blk_mem_axi_read_wrapper_beh_v8_2
# (
//// AXI Interface related parameters start here
parameter C_INTERFACE_TYPE = 0,
parameter C_AXI_TYPE = 0,
parameter C_AXI_SLAVE_TYPE = 0,
parameter C_MEMORY_TYPE = 0,
parameter C_WRITE_WIDTH_A = 4,
parameter C_WRITE_DEPTH_A = 32,
parameter C_ADDRA_WIDTH = 12,
parameter C_AXI_PIPELINE_STAGES = 0,
parameter C_AXI_ARADDR_WIDTH = 12,
parameter C_HAS_AXI_ID = 0,
parameter C_AXI_ID_WIDTH = 4,
parameter C_ADDRB_WIDTH = 12
)
(
//// AXI Global Signals
input S_ACLK,
input S_ARESETN,
//// AXI Full/Lite Slave Read (Read side)
input [C_AXI_ARADDR_WIDTH-1:0] S_AXI_ARADDR,
input [7:0] S_AXI_ARLEN,
input [2:0] S_AXI_ARSIZE,
input [1:0] S_AXI_ARBURST,
input S_AXI_ARVALID,
output S_AXI_ARREADY,
output S_AXI_RLAST,
output S_AXI_RVALID,
input S_AXI_RREADY,
input [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,
output reg [C_AXI_ID_WIDTH-1:0] S_AXI_RID = 0,
//// AXI Full/Lite Read Address Signals to BRAM
output [C_ADDRB_WIDTH-1:0] S_AXI_ARADDR_OUT,
output S_AXI_RD_EN
);
localparam FLOP_DELAY = 100; // 100 ps
localparam C_RANGE = ((C_WRITE_WIDTH_A == 8)?0:
((C_WRITE_WIDTH_A==16)?1:
((C_WRITE_WIDTH_A==32)?2:
((C_WRITE_WIDTH_A==64)?3:
((C_WRITE_WIDTH_A==128)?4:
((C_WRITE_WIDTH_A==256)?5:0))))));
reg [C_AXI_ID_WIDTH-1:0] ar_id_r=0;
wire addr_en_c;
wire rd_en_c;
wire incr_addr_c;
wire single_trans_c;
wire dec_alen_c;
wire mux_sel_c;
wire r_last_c;
wire r_last_int_c;
wire [C_ADDRB_WIDTH-1 : 0] araddr_out;
reg [7:0] arlen_int_r=0;
reg [7:0] arlen_cntr=8'h01;
reg [1:0] arburst_int_c=0;
reg [1:0] arburst_int_r=0;
reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?
C_AXI_ARADDR_WIDTH:C_ADDRA_WIDTH)-1:0] araddr_reg =0;
integer num_of_bytes_c = 0;
integer total_bytes = 0;
integer num_of_bytes_r = 0;
integer wrap_base_addr_r = 0;
integer wrap_boundary_r = 0;
reg [7:0] arlen_int_c=0;
integer total_bytes_c = 0;
integer wrap_base_addr_c = 0;
integer wrap_boundary_c = 0;
assign dec_alen_c = incr_addr_c | r_last_int_c;
read_netlist_v8_2
#(.C_AXI_TYPE (1),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH))
axi_read_fsm (
.S_AXI_INCR_ADDR(incr_addr_c),
.S_AXI_ADDR_EN(addr_en_c),
.S_AXI_SINGLE_TRANS(single_trans_c),
.S_AXI_MUX_SEL(mux_sel_c),
.S_AXI_R_LAST(r_last_c),
.S_AXI_R_LAST_INT(r_last_int_c),
//// AXI Global Signals
.S_ACLK(S_ACLK),
.S_ARESETN(S_ARESETN),
//// AXI Full/Lite Slave Read (Read side)
.S_AXI_ARLEN(S_AXI_ARLEN),
.S_AXI_ARVALID(S_AXI_ARVALID),
.S_AXI_ARREADY(S_AXI_ARREADY),
.S_AXI_RLAST(S_AXI_RLAST),
.S_AXI_RVALID(S_AXI_RVALID),
.S_AXI_RREADY(S_AXI_RREADY),
//// AXI Full/Lite Read Address Signals to BRAM
.S_AXI_RD_EN(rd_en_c)
);
always@(*) begin
num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARSIZE:0);
total_bytes = (num_of_bytes_r)*(arlen_int_r+1);
wrap_base_addr_r = ((araddr_reg)/(total_bytes==0?1:total_bytes))*(total_bytes);
wrap_boundary_r = wrap_base_addr_r+total_bytes;
//////// combinatorial from interface
arlen_int_c = (C_AXI_TYPE == 0?0:S_AXI_ARLEN);
total_bytes_c = (num_of_bytes_c)*(arlen_int_c+1);
wrap_base_addr_c = ((S_AXI_ARADDR)/(total_bytes_c==0?1:total_bytes_c))*(total_bytes_c);
wrap_boundary_c = wrap_base_addr_c+total_bytes_c;
arburst_int_c = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARBURST:1);
end
////-------------------------------------------------------------------------
//// BMG address generation
////-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
araddr_reg <= 0;
arburst_int_r <= 0;
num_of_bytes_r <= 0;
end else begin
if (incr_addr_c == 1'b1 && addr_en_c == 1'b1 && single_trans_c == 1'b0) begin
arburst_int_r <= arburst_int_c;
num_of_bytes_r <= num_of_bytes_c;
if (arburst_int_c == 2'b10) begin
if(S_AXI_ARADDR == (wrap_boundary_c-num_of_bytes_c)) begin
araddr_reg <= wrap_base_addr_c;
end else begin
araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
end
end else if (arburst_int_c == 2'b01 || arburst_int_c == 2'b11) begin
araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
end
end else if (addr_en_c == 1'b1) begin
araddr_reg <= S_AXI_ARADDR;
num_of_bytes_r <= num_of_bytes_c;
arburst_int_r <= arburst_int_c;
end else if (incr_addr_c == 1'b1) begin
if (arburst_int_r == 2'b10) begin
if(araddr_reg == (wrap_boundary_r-num_of_bytes_r)) begin
araddr_reg <= wrap_base_addr_r;
end else begin
araddr_reg <= araddr_reg + num_of_bytes_r;
end
end else if (arburst_int_r == 2'b01 || arburst_int_r == 2'b11) begin
araddr_reg <= araddr_reg + num_of_bytes_r;
end
end
end
end
assign araddr_out = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?araddr_reg[C_AXI_ARADDR_WIDTH-1:C_RANGE]:araddr_reg);
////-----------------------------------------------------------------------
//// Counter to generate r_last_int_c from registered ARLEN - AXI FULL FSM
////-----------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
arlen_cntr <= 8'h01;
arlen_int_r <= 0;
end else begin
if (addr_en_c == 1'b1 && dec_alen_c == 1'b1 && single_trans_c == 1'b0) begin
arlen_int_r <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;
arlen_cntr <= S_AXI_ARLEN - 1'b1;
end else if (addr_en_c == 1'b1) begin
arlen_int_r <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;
arlen_cntr <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;
end else if (dec_alen_c == 1'b1) begin
arlen_cntr <= arlen_cntr - 1'b1 ;
end
else begin
arlen_cntr <= arlen_cntr;
end
end
end
assign r_last_int_c = (arlen_cntr == 0 && S_AXI_RREADY == 1'b1)?1'b1:1'b0;
////------------------------------------------------------------------------
//// AXI FULL FSM
//// Mux Selection of ARADDR
//// ARADDR is driven out from the read fsm based on the mux_sel_c
//// Based on mux_sel either ARADDR is given out or the latched ARADDR is
//// given out to BRAM
////------------------------------------------------------------------------
assign S_AXI_ARADDR_OUT = (mux_sel_c == 1'b0)?((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARADDR[C_AXI_ARADDR_WIDTH-1:C_RANGE]:S_AXI_ARADDR):araddr_out;
////------------------------------------------------------------------------
//// Assign output signals - AXI FULL FSM
////------------------------------------------------------------------------
assign S_AXI_RD_EN = rd_en_c;
generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
S_AXI_RID <= 0;
ar_id_r <= 0;
end else begin
if (addr_en_c == 1'b1 && rd_en_c == 1'b1) begin
S_AXI_RID <= S_AXI_ARID;
ar_id_r <= S_AXI_ARID;
end else if (addr_en_c == 1'b1 && rd_en_c == 1'b0) begin
ar_id_r <= S_AXI_ARID;
end else if (rd_en_c == 1'b1) begin
S_AXI_RID <= ar_id_r;
end
end
end
end
endgenerate
endmodule
module blk_mem_axi_regs_fwd_v8_2
#(parameter C_DATA_WIDTH = 8
)(
input ACLK,
input ARESET,
input S_VALID,
output S_READY,
input [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
output M_VALID,
input M_READY,
output reg [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA
);
reg [C_DATA_WIDTH-1:0] STORAGE_DATA;
wire S_READY_I;
reg M_VALID_I;
reg [1:0] ARESET_D;
//assign local signal to its output signal
assign S_READY = S_READY_I;
assign M_VALID = M_VALID_I;
always @(posedge ACLK) begin
ARESET_D <= {ARESET_D[0], ARESET};
end
//Save payload data whenever we have a transaction on the slave side
always @(posedge ACLK or ARESET) begin
if (ARESET == 1'b1) begin
STORAGE_DATA <= 0;
end else begin
if(S_VALID == 1'b1 && S_READY_I == 1'b1 ) begin
STORAGE_DATA <= S_PAYLOAD_DATA;
end
end
end
always @(posedge ACLK) begin
M_PAYLOAD_DATA = STORAGE_DATA;
end
//M_Valid set to high when we have a completed transfer on slave side
//Is removed on a M_READY except if we have a new transfer on the slave side
always @(posedge ACLK or ARESET_D) begin
if (ARESET_D != 2'b00) begin
M_VALID_I <= 1'b0;
end else begin
if (S_VALID == 1'b1) begin
//Always set M_VALID_I when slave side is valid
M_VALID_I <= 1'b1;
end else if (M_READY == 1'b1 ) begin
//Clear (or keep) when no slave side is valid but master side is ready
M_VALID_I <= 1'b0;
end
end
end
//Slave Ready is either when Master side drives M_READY or we have space in our storage data
assign S_READY_I = (M_READY || (!M_VALID_I)) && !(|(ARESET_D));
endmodule
//*****************************************************************************
// Output Register Stage module
//
// This module builds the output register stages of the memory. This module is
// instantiated in the main memory module (BLK_MEM_GEN_v8_2) which is
// declared/implemented further down in this file.
//*****************************************************************************
module BLK_MEM_GEN_v8_2_output_stage
#(parameter C_FAMILY = "virtex7",
parameter C_XDEVICEFAMILY = "virtex7",
parameter C_RST_TYPE = "SYNC",
parameter C_HAS_RST = 0,
parameter C_RSTRAM = 0,
parameter C_RST_PRIORITY = "CE",
parameter C_INIT_VAL = "0",
parameter C_HAS_EN = 0,
parameter C_HAS_REGCE = 0,
parameter C_DATA_WIDTH = 32,
parameter C_ADDRB_WIDTH = 10,
parameter C_HAS_MEM_OUTPUT_REGS = 0,
parameter C_USE_SOFTECC = 0,
parameter C_USE_ECC = 0,
parameter NUM_STAGES = 1,
parameter C_EN_ECC_PIPE = 0,
parameter FLOP_DELAY = 100
)
(
input CLK,
input RST,
input EN,
input REGCE,
input [C_DATA_WIDTH-1:0] DIN_I,
output reg [C_DATA_WIDTH-1:0] DOUT,
input SBITERR_IN_I,
input DBITERR_IN_I,
output reg SBITERR,
output reg DBITERR,
input [C_ADDRB_WIDTH-1:0] RDADDRECC_IN_I,
input ECCPIPECE,
output reg [C_ADDRB_WIDTH-1:0] RDADDRECC
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
// options are available - "spartan3", "spartan6",
// "virtex4", "virtex5", "virtex6" and "virtex6l".
// C_RST_TYPE : Type of reset - Synchronous or Asynchronous
// C_HAS_RST : Determines the presence of the RST port
// C_RSTRAM : Determines if special reset behavior is used
// C_RST_PRIORITY : Determines the priority between CE and SR
// C_INIT_VAL : Initialization value
// C_HAS_EN : Determines the presence of the EN port
// C_HAS_REGCE : Determines the presence of the REGCE port
// C_DATA_WIDTH : Memory write/read width
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_MEM_OUTPUT_REGS : Designates the use of a register at the output
// of the RAM primitive
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// C_USE_ECC : Determines if the ECC feature is used or
// not. Only applicable for V5 and V6
// NUM_STAGES : Determines the number of output stages
// FLOP_DELAY : Constant delay for register assignments
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLK : Clock to synchronize all read and write operations
// RST : Reset input to reset memory outputs to a user-defined
// reset state
// EN : Enable all read and write operations
// REGCE : Register Clock Enable to control each pipeline output
// register stages
// DIN : Data input to the Output stage.
// DOUT : Final Data output
// SBITERR_IN : SBITERR input signal to the Output stage.
// SBITERR : Final SBITERR Output signal.
// DBITERR_IN : DBITERR input signal to the Output stage.
// DBITERR : Final DBITERR Output signal.
// RDADDRECC_IN : RDADDRECC input signal to the Output stage.
// RDADDRECC : Final RDADDRECC Output signal.
//////////////////////////////////////////////////////////////////////////
// Fix for CR-509792
localparam REG_STAGES = (NUM_STAGES < 2) ? 1 : NUM_STAGES-1;
// Declare the pipeline registers
// (includes mem output reg, mux pipeline stages, and mux output reg)
reg [C_DATA_WIDTH*REG_STAGES-1:0] out_regs;
reg [C_ADDRB_WIDTH*REG_STAGES-1:0] rdaddrecc_regs;
reg [REG_STAGES-1:0] sbiterr_regs;
reg [REG_STAGES-1:0] dbiterr_regs;
reg [C_DATA_WIDTH*8-1:0] init_str = C_INIT_VAL;
reg [C_DATA_WIDTH-1:0] init_val ;
//*********************************************
// Wire off optional inputs based on parameters
//*********************************************
wire en_i;
wire regce_i;
wire rst_i;
// Internal signals
reg [C_DATA_WIDTH-1:0] DIN;
reg [C_ADDRB_WIDTH-1:0] RDADDRECC_IN;
reg SBITERR_IN;
reg DBITERR_IN;
// Internal enable for output registers is tied to user EN or '1' depending
// on parameters
assign en_i = (C_HAS_EN==0 || EN);
// Internal register enable for output registers is tied to user REGCE, EN or
// '1' depending on parameters
// For V4 ECC, REGCE is always 1
// Virtex-4 ECC Not Yet Supported
assign regce_i = ((C_HAS_REGCE==1) && REGCE) ||
((C_HAS_REGCE==0) && (C_HAS_EN==0 || EN));
//Internal SRR is tied to user RST or '0' depending on parameters
assign rst_i = (C_HAS_RST==1) && RST;
//****************************************************
// Power on: load up the output registers and latches
//****************************************************
initial begin
if (!($sscanf(init_str, "%h", init_val))) begin
init_val = 0;
end
DOUT = init_val;
RDADDRECC = 0;
SBITERR = 1'b0;
DBITERR = 1'b0;
DIN = {(C_DATA_WIDTH){1'b0}};
RDADDRECC_IN = 0;
SBITERR_IN = 0;
DBITERR_IN = 0;
// This will be one wider than need, but 0 is an error
out_regs = {(REG_STAGES+1){init_val}};
rdaddrecc_regs = 0;
sbiterr_regs = {(REG_STAGES+1){1'b0}};
dbiterr_regs = {(REG_STAGES+1){1'b0}};
end
//***********************************************
// NUM_STAGES = 0 (No output registers. RAM only)
//***********************************************
generate if (NUM_STAGES == 0) begin : zero_stages
always @* begin
DOUT = DIN;
RDADDRECC = RDADDRECC_IN;
SBITERR = SBITERR_IN;
DBITERR = DBITERR_IN;
end
end
endgenerate
generate if (C_EN_ECC_PIPE == 0) begin : no_ecc_pipe_reg
always @* begin
DIN = DIN_I;
SBITERR_IN = SBITERR_IN_I;
DBITERR_IN = DBITERR_IN_I;
RDADDRECC_IN = RDADDRECC_IN_I;
end
end
endgenerate
generate if (C_EN_ECC_PIPE == 1) begin : with_ecc_pipe_reg
always @(posedge CLK) begin
if(ECCPIPECE == 1) begin
DIN <= #FLOP_DELAY DIN_I;
SBITERR_IN <= #FLOP_DELAY SBITERR_IN_I;
DBITERR_IN <= #FLOP_DELAY DBITERR_IN_I;
RDADDRECC_IN <= #FLOP_DELAY RDADDRECC_IN_I;
end
end
end
endgenerate
//***********************************************
// NUM_STAGES = 1
// (Mem Output Reg only or Mux Output Reg only)
//***********************************************
// Possible valid combinations:
// Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1)
// +-----------------------------------------+
// | C_RSTRAM_* | Reset Behavior |
// +----------------+------------------------+
// | 0 | Normal Behavior |
// +----------------+------------------------+
// | 1 | Special Behavior |
// +----------------+------------------------+
//
// Normal = REGCE gates reset, as in the case of all families except S3ADSP.
// Special = EN gates reset, as in the case of S3ADSP.
generate if (NUM_STAGES == 1 &&
(C_RSTRAM == 0 || (C_RSTRAM == 1 && (C_XDEVICEFAMILY != "spartan3adsp" && C_XDEVICEFAMILY != "aspartan3adsp" )) ||
C_HAS_MEM_OUTPUT_REGS == 0 || C_HAS_RST == 0))
begin : one_stages_norm
always @(posedge CLK) begin
if (C_RST_PRIORITY == "CE") begin //REGCE has priority
if (regce_i && rst_i) begin
DOUT <= #FLOP_DELAY init_val;
RDADDRECC <= #FLOP_DELAY 0;
SBITERR <= #FLOP_DELAY 1'b0;
DBITERR <= #FLOP_DELAY 1'b0;
end else if (regce_i) begin
DOUT <= #FLOP_DELAY DIN;
RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;
SBITERR <= #FLOP_DELAY SBITERR_IN;
DBITERR <= #FLOP_DELAY DBITERR_IN;
end //Output signal assignments
end else begin //RST has priority
if (rst_i) begin
DOUT <= #FLOP_DELAY init_val;
RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;
SBITERR <= #FLOP_DELAY 1'b0;
DBITERR <= #FLOP_DELAY 1'b0;
end else if (regce_i) begin
DOUT <= #FLOP_DELAY DIN;
RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;
SBITERR <= #FLOP_DELAY SBITERR_IN;
DBITERR <= #FLOP_DELAY DBITERR_IN;
end //Output signal assignments
end //end Priority conditions
end //end RST Type conditions
end //end one_stages_norm generate statement
endgenerate
// Special Reset Behavior for S3ADSP
generate if (NUM_STAGES == 1 && C_RSTRAM == 1 && (C_XDEVICEFAMILY =="spartan3adsp" || C_XDEVICEFAMILY =="aspartan3adsp"))
begin : one_stage_splbhv
always @(posedge CLK) begin
if (en_i && rst_i) begin
DOUT <= #FLOP_DELAY init_val;
end else if (regce_i && !rst_i) begin
DOUT <= #FLOP_DELAY DIN;
end //Output signal assignments
end //end CLK
end //end one_stage_splbhv generate statement
endgenerate
//************************************************************
// NUM_STAGES > 1
// Mem Output Reg + Mux Output Reg
// or
// Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg
// or
// Mux Pipeline Stages (>0) + Mux Output Reg
//*************************************************************
generate if (NUM_STAGES > 1) begin : multi_stage
//Asynchronous Reset
always @(posedge CLK) begin
if (C_RST_PRIORITY == "CE") begin //REGCE has priority
if (regce_i && rst_i) begin
DOUT <= #FLOP_DELAY init_val;
RDADDRECC <= #FLOP_DELAY 0;
SBITERR <= #FLOP_DELAY 1'b0;
DBITERR <= #FLOP_DELAY 1'b0;
end else if (regce_i) begin
DOUT <= #FLOP_DELAY
out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];
RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];
SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];
DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];
end //Output signal assignments
end else begin //RST has priority
if (rst_i) begin
DOUT <= #FLOP_DELAY init_val;
RDADDRECC <= #FLOP_DELAY 0;
SBITERR <= #FLOP_DELAY 1'b0;
DBITERR <= #FLOP_DELAY 1'b0;
end else if (regce_i) begin
DOUT <= #FLOP_DELAY
out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];
RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];
SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];
DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];
end //Output signal assignments
end //end Priority conditions
// Shift the data through the output stages
if (en_i) begin
out_regs <= #FLOP_DELAY (out_regs << C_DATA_WIDTH) | DIN;
rdaddrecc_regs <= #FLOP_DELAY (rdaddrecc_regs << C_ADDRB_WIDTH) | RDADDRECC_IN;
sbiterr_regs <= #FLOP_DELAY (sbiterr_regs << 1) | SBITERR_IN;
dbiterr_regs <= #FLOP_DELAY (dbiterr_regs << 1) | DBITERR_IN;
end
end //end CLK
end //end multi_stage generate statement
endgenerate
endmodule
module BLK_MEM_GEN_v8_2_softecc_output_reg_stage
#(parameter C_DATA_WIDTH = 32,
parameter C_ADDRB_WIDTH = 10,
parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,
parameter C_USE_SOFTECC = 0,
parameter FLOP_DELAY = 100
)
(
input CLK,
input [C_DATA_WIDTH-1:0] DIN,
output reg [C_DATA_WIDTH-1:0] DOUT,
input SBITERR_IN,
input DBITERR_IN,
output reg SBITERR,
output reg DBITERR,
input [C_ADDRB_WIDTH-1:0] RDADDRECC_IN,
output reg [C_ADDRB_WIDTH-1:0] RDADDRECC
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_DATA_WIDTH : Memory write/read width
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_SOFTECC_OUTPUT_REGS_B : Designates the use of a register at the output
// of the RAM primitive
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// FLOP_DELAY : Constant delay for register assignments
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLK : Clock to synchronize all read and write operations
// DIN : Data input to the Output stage.
// DOUT : Final Data output
// SBITERR_IN : SBITERR input signal to the Output stage.
// SBITERR : Final SBITERR Output signal.
// DBITERR_IN : DBITERR input signal to the Output stage.
// DBITERR : Final DBITERR Output signal.
// RDADDRECC_IN : RDADDRECC input signal to the Output stage.
// RDADDRECC : Final RDADDRECC Output signal.
//////////////////////////////////////////////////////////////////////////
reg [C_DATA_WIDTH-1:0] dout_i = 0;
reg sbiterr_i = 0;
reg dbiterr_i = 0;
reg [C_ADDRB_WIDTH-1:0] rdaddrecc_i = 0;
//***********************************************
// NO OUTPUT REGISTERS.
//***********************************************
generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==0) begin : no_output_stage
always @* begin
DOUT = DIN;
RDADDRECC = RDADDRECC_IN;
SBITERR = SBITERR_IN;
DBITERR = DBITERR_IN;
end
end
endgenerate
//***********************************************
// WITH OUTPUT REGISTERS.
//***********************************************
generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==1) begin : has_output_stage
always @(posedge CLK) begin
dout_i <= #FLOP_DELAY DIN;
rdaddrecc_i <= #FLOP_DELAY RDADDRECC_IN;
sbiterr_i <= #FLOP_DELAY SBITERR_IN;
dbiterr_i <= #FLOP_DELAY DBITERR_IN;
end
always @* begin
DOUT = dout_i;
RDADDRECC = rdaddrecc_i;
SBITERR = sbiterr_i;
DBITERR = dbiterr_i;
end //end always
end //end in_or_out_stage generate statement
endgenerate
endmodule
//*****************************************************************************
// Main Memory module
//
// This module is the top-level behavioral model and this implements the RAM
//*****************************************************************************
module BLK_MEM_GEN_v8_2_mem_module
#(parameter C_CORENAME = "blk_mem_gen_v8_2",
parameter C_FAMILY = "virtex7",
parameter C_XDEVICEFAMILY = "virtex7",
parameter C_MEM_TYPE = 2,
parameter C_BYTE_SIZE = 9,
parameter C_USE_BRAM_BLOCK = 0,
parameter C_ALGORITHM = 1,
parameter C_PRIM_TYPE = 3,
parameter C_LOAD_INIT_FILE = 0,
parameter C_INIT_FILE_NAME = "",
parameter C_INIT_FILE = "",
parameter C_USE_DEFAULT_DATA = 0,
parameter C_DEFAULT_DATA = "0",
parameter C_RST_TYPE = "SYNC",
parameter C_HAS_RSTA = 0,
parameter C_RST_PRIORITY_A = "CE",
parameter C_RSTRAM_A = 0,
parameter C_INITA_VAL = "0",
parameter C_HAS_ENA = 1,
parameter C_HAS_REGCEA = 0,
parameter C_USE_BYTE_WEA = 0,
parameter C_WEA_WIDTH = 1,
parameter C_WRITE_MODE_A = "WRITE_FIRST",
parameter C_WRITE_WIDTH_A = 32,
parameter C_READ_WIDTH_A = 32,
parameter C_WRITE_DEPTH_A = 64,
parameter C_READ_DEPTH_A = 64,
parameter C_ADDRA_WIDTH = 5,
parameter C_HAS_RSTB = 0,
parameter C_RST_PRIORITY_B = "CE",
parameter C_RSTRAM_B = 0,
parameter C_INITB_VAL = "",
parameter C_HAS_ENB = 1,
parameter C_HAS_REGCEB = 0,
parameter C_USE_BYTE_WEB = 0,
parameter C_WEB_WIDTH = 1,
parameter C_WRITE_MODE_B = "WRITE_FIRST",
parameter C_WRITE_WIDTH_B = 32,
parameter C_READ_WIDTH_B = 32,
parameter C_WRITE_DEPTH_B = 64,
parameter C_READ_DEPTH_B = 64,
parameter C_ADDRB_WIDTH = 5,
parameter C_HAS_MEM_OUTPUT_REGS_A = 0,
parameter C_HAS_MEM_OUTPUT_REGS_B = 0,
parameter C_HAS_MUX_OUTPUT_REGS_A = 0,
parameter C_HAS_MUX_OUTPUT_REGS_B = 0,
parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,
parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,
parameter C_MUX_PIPELINE_STAGES = 0,
parameter C_USE_SOFTECC = 0,
parameter C_USE_ECC = 0,
parameter C_HAS_INJECTERR = 0,
parameter C_SIM_COLLISION_CHECK = "NONE",
parameter C_COMMON_CLK = 1,
parameter FLOP_DELAY = 100,
parameter C_DISABLE_WARN_BHV_COLL = 0,
parameter C_EN_ECC_PIPE = 0,
parameter C_DISABLE_WARN_BHV_RANGE = 0
)
(input CLKA,
input RSTA,
input ENA,
input REGCEA,
input [C_WEA_WIDTH-1:0] WEA,
input [C_ADDRA_WIDTH-1:0] ADDRA,
input [C_WRITE_WIDTH_A-1:0] DINA,
output [C_READ_WIDTH_A-1:0] DOUTA,
input CLKB,
input RSTB,
input ENB,
input REGCEB,
input [C_WEB_WIDTH-1:0] WEB,
input [C_ADDRB_WIDTH-1:0] ADDRB,
input [C_WRITE_WIDTH_B-1:0] DINB,
output [C_READ_WIDTH_B-1:0] DOUTB,
input INJECTSBITERR,
input INJECTDBITERR,
input ECCPIPECE,
input SLEEP,
output SBITERR,
output DBITERR,
output [C_ADDRB_WIDTH-1:0] RDADDRECC
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_CORENAME : Instance name of the Block Memory Generator core
// C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
// options are available - "spartan3", "spartan6",
// "virtex4", "virtex5", "virtex6" and "virtex6l".
// C_MEM_TYPE : Designates memory type.
// It can be
// 0 - Single Port Memory
// 1 - Simple Dual Port Memory
// 2 - True Dual Port Memory
// 3 - Single Port Read Only Memory
// 4 - Dual Port Read Only Memory
// C_BYTE_SIZE : Size of a byte (8 or 9 bits)
// C_ALGORITHM : Designates the algorithm method used
// for constructing the memory.
// It can be Fixed_Primitives, Minimum_Area or
// Low_Power
// C_PRIM_TYPE : Designates the user selected primitive used to
// construct the memory.
//
// C_LOAD_INIT_FILE : Designates the use of an initialization file to
// initialize memory contents.
// C_INIT_FILE_NAME : Memory initialization file name.
// C_USE_DEFAULT_DATA : Designates whether to fill remaining
// initialization space with default data
// C_DEFAULT_DATA : Default value of all memory locations
// not initialized by the memory
// initialization file.
// C_RST_TYPE : Type of reset - Synchronous or Asynchronous
// C_HAS_RSTA : Determines the presence of the RSTA port
// C_RST_PRIORITY_A : Determines the priority between CE and SR for
// Port A.
// C_RSTRAM_A : Determines if special reset behavior is used for
// Port A
// C_INITA_VAL : The initialization value for Port A
// C_HAS_ENA : Determines the presence of the ENA port
// C_HAS_REGCEA : Determines the presence of the REGCEA port
// C_USE_BYTE_WEA : Determines if the Byte Write is used or not.
// C_WEA_WIDTH : The width of the WEA port
// C_WRITE_MODE_A : Configurable write mode for Port A. It can be
// WRITE_FIRST, READ_FIRST or NO_CHANGE.
// C_WRITE_WIDTH_A : Memory write width for Port A.
// C_READ_WIDTH_A : Memory read width for Port A.
// C_WRITE_DEPTH_A : Memory write depth for Port A.
// C_READ_DEPTH_A : Memory read depth for Port A.
// C_ADDRA_WIDTH : Width of the ADDRA input port
// C_HAS_RSTB : Determines the presence of the RSTB port
// C_RST_PRIORITY_B : Determines the priority between CE and SR for
// Port B.
// C_RSTRAM_B : Determines if special reset behavior is used for
// Port B
// C_INITB_VAL : The initialization value for Port B
// C_HAS_ENB : Determines the presence of the ENB port
// C_HAS_REGCEB : Determines the presence of the REGCEB port
// C_USE_BYTE_WEB : Determines if the Byte Write is used or not.
// C_WEB_WIDTH : The width of the WEB port
// C_WRITE_MODE_B : Configurable write mode for Port B. It can be
// WRITE_FIRST, READ_FIRST or NO_CHANGE.
// C_WRITE_WIDTH_B : Memory write width for Port B.
// C_READ_WIDTH_B : Memory read width for Port B.
// C_WRITE_DEPTH_B : Memory write depth for Port B.
// C_READ_DEPTH_B : Memory read depth for Port B.
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output
// of the RAM primitive for Port A.
// C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output
// of the RAM primitive for Port B.
// C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
// of the MUX for Port A.
// C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
// of the MUX for Port B.
// C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in
// between the muxes.
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// C_USE_ECC : Determines if the ECC feature is used or
// not. Only applicable for V5 and V6
// C_HAS_INJECTERR : Determines if the error injection pins
// are present or not. If the ECC feature
// is not used, this value is defaulted to
// 0, else the following are the allowed
// values:
// 0 : No INJECTSBITERR or INJECTDBITERR pins
// 1 : Only INJECTSBITERR pin exists
// 2 : Only INJECTDBITERR pin exists
// 3 : Both INJECTSBITERR and INJECTDBITERR pins exist
// C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision
// warnings. It can be "ALL", "NONE",
// "Warnings_Only" or "Generate_X_Only".
// C_COMMON_CLK : Determins if the core has a single CLK input.
// C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
// C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range
// warnings
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLKA : Clock to synchronize all read and write operations of Port A.
// RSTA : Reset input to reset memory outputs to a user-defined
// reset state for Port A.
// ENA : Enable all read and write operations of Port A.
// REGCEA : Register Clock Enable to control each pipeline output
// register stages for Port A.
// WEA : Write Enable to enable all write operations of Port A.
// ADDRA : Address of Port A.
// DINA : Data input of Port A.
// DOUTA : Data output of Port A.
// CLKB : Clock to synchronize all read and write operations of Port B.
// RSTB : Reset input to reset memory outputs to a user-defined
// reset state for Port B.
// ENB : Enable all read and write operations of Port B.
// REGCEB : Register Clock Enable to control each pipeline output
// register stages for Port B.
// WEB : Write Enable to enable all write operations of Port B.
// ADDRB : Address of Port B.
// DINB : Data input of Port B.
// DOUTB : Data output of Port B.
// INJECTSBITERR : Single Bit ECC Error Injection Pin.
// INJECTDBITERR : Double Bit ECC Error Injection Pin.
// SBITERR : Output signal indicating that a Single Bit ECC Error has been
// detected and corrected.
// DBITERR : Output signal indicating that a Double Bit ECC Error has been
// detected.
// RDADDRECC : Read Address Output signal indicating address at which an
// ECC error has occurred.
//////////////////////////////////////////////////////////////////////////
// Note: C_CORENAME parameter is hard-coded to "blk_mem_gen_v8_2" and it is
// only used by this module to print warning messages. It is neither passed
// down from blk_mem_gen_v8_2_xst.v nor present in the instantiation template
// coregen generates
//***************************************************************************
// constants for the core behavior
//***************************************************************************
// file handles for logging
//--------------------------------------------------
localparam ADDRFILE = 32'h8000_0001; //stdout for addr out of range
localparam COLLFILE = 32'h8000_0001; //stdout for coll detection
localparam ERRFILE = 32'h8000_0001; //stdout for file I/O errors
// other constants
//--------------------------------------------------
localparam COLL_DELAY = 100; // 100 ps
// locally derived parameters to determine memory shape
//-----------------------------------------------------
localparam CHKBIT_WIDTH = (C_WRITE_WIDTH_A>57 ? 8 : (C_WRITE_WIDTH_A>26 ? 7 : (C_WRITE_WIDTH_A>11 ? 6 : (C_WRITE_WIDTH_A>4 ? 5 : (C_WRITE_WIDTH_A<5 ? 4 :0)))));
localparam MIN_WIDTH_A = (C_WRITE_WIDTH_A < C_READ_WIDTH_A) ?
C_WRITE_WIDTH_A : C_READ_WIDTH_A;
localparam MIN_WIDTH_B = (C_WRITE_WIDTH_B < C_READ_WIDTH_B) ?
C_WRITE_WIDTH_B : C_READ_WIDTH_B;
localparam MIN_WIDTH = (MIN_WIDTH_A < MIN_WIDTH_B) ?
MIN_WIDTH_A : MIN_WIDTH_B;
localparam MAX_DEPTH_A = (C_WRITE_DEPTH_A > C_READ_DEPTH_A) ?
C_WRITE_DEPTH_A : C_READ_DEPTH_A;
localparam MAX_DEPTH_B = (C_WRITE_DEPTH_B > C_READ_DEPTH_B) ?
C_WRITE_DEPTH_B : C_READ_DEPTH_B;
localparam MAX_DEPTH = (MAX_DEPTH_A > MAX_DEPTH_B) ?
MAX_DEPTH_A : MAX_DEPTH_B;
// locally derived parameters to assist memory access
//----------------------------------------------------
// Calculate the width ratios of each port with respect to the narrowest
// port
localparam WRITE_WIDTH_RATIO_A = C_WRITE_WIDTH_A/MIN_WIDTH;
localparam READ_WIDTH_RATIO_A = C_READ_WIDTH_A/MIN_WIDTH;
localparam WRITE_WIDTH_RATIO_B = C_WRITE_WIDTH_B/MIN_WIDTH;
localparam READ_WIDTH_RATIO_B = C_READ_WIDTH_B/MIN_WIDTH;
// To modify the LSBs of the 'wider' data to the actual
// address value
//----------------------------------------------------
localparam WRITE_ADDR_A_DIV = C_WRITE_WIDTH_A/MIN_WIDTH_A;
localparam READ_ADDR_A_DIV = C_READ_WIDTH_A/MIN_WIDTH_A;
localparam WRITE_ADDR_B_DIV = C_WRITE_WIDTH_B/MIN_WIDTH_B;
localparam READ_ADDR_B_DIV = C_READ_WIDTH_B/MIN_WIDTH_B;
// If byte writes aren't being used, make sure BYTE_SIZE is not
// wider than the memory elements to avoid compilation warnings
localparam BYTE_SIZE = (C_BYTE_SIZE < MIN_WIDTH) ? C_BYTE_SIZE : MIN_WIDTH;
// The memory
reg [MIN_WIDTH-1:0] memory [0:MAX_DEPTH-1];
reg [MIN_WIDTH-1:0] temp_mem_array [0:MAX_DEPTH-1];
reg [C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:0] doublebit_error = 3;
// ECC error arrays
reg sbiterr_arr [0:MAX_DEPTH-1];
reg dbiterr_arr [0:MAX_DEPTH-1];
reg softecc_sbiterr_arr [0:MAX_DEPTH-1];
reg softecc_dbiterr_arr [0:MAX_DEPTH-1];
// Memory output 'latches'
reg [C_READ_WIDTH_A-1:0] memory_out_a;
reg [C_READ_WIDTH_B-1:0] memory_out_b;
// ECC error inputs and outputs from output_stage module:
reg sbiterr_in;
wire sbiterr_sdp;
reg dbiterr_in;
wire dbiterr_sdp;
wire [C_READ_WIDTH_B-1:0] dout_i;
wire dbiterr_i;
wire sbiterr_i;
wire [C_ADDRB_WIDTH-1:0] rdaddrecc_i;
reg [C_ADDRB_WIDTH-1:0] rdaddrecc_in;
wire [C_ADDRB_WIDTH-1:0] rdaddrecc_sdp;
// Reset values
reg [C_READ_WIDTH_A-1:0] inita_val;
reg [C_READ_WIDTH_B-1:0] initb_val;
// Collision detect
reg is_collision;
reg is_collision_a, is_collision_delay_a;
reg is_collision_b, is_collision_delay_b;
// Temporary variables for initialization
//---------------------------------------
integer status;
integer initfile;
integer meminitfile;
// data input buffer
reg [C_WRITE_WIDTH_A-1:0] mif_data;
reg [C_WRITE_WIDTH_A-1:0] mem_data;
// string values in hex
reg [C_READ_WIDTH_A*8-1:0] inita_str = C_INITA_VAL;
reg [C_READ_WIDTH_B*8-1:0] initb_str = C_INITB_VAL;
reg [C_WRITE_WIDTH_A*8-1:0] default_data_str = C_DEFAULT_DATA;
// initialization filename
reg [1023*8-1:0] init_file_str = C_INIT_FILE_NAME;
reg [1023*8-1:0] mem_init_file_str = C_INIT_FILE;
//Constants used to calculate the effective address widths for each of the
//four ports.
integer cnt = 1;
integer write_addr_a_width, read_addr_a_width;
integer write_addr_b_width, read_addr_b_width;
localparam C_FAMILY_LOCALPARAM = (C_FAMILY=="virtexu"?"virtex7":(C_FAMILY=="kintexu" ? "virtex7":(C_FAMILY=="virtex7" ? "virtex7" : (C_FAMILY=="virtex7l" ? "virtex7" : (C_FAMILY=="qvirtex7" ? "virtex7" : (C_FAMILY=="qvirtex7l" ? "virtex7" : (C_FAMILY=="kintex7" ? "virtex7" : (C_FAMILY=="kintex7l" ? "virtex7" : (C_FAMILY=="qkintex7" ? "virtex7" : (C_FAMILY=="qkintex7l" ? "virtex7" : (C_FAMILY=="artix7" ? "virtex7" : (C_FAMILY=="artix7l" ? "virtex7" : (C_FAMILY=="qartix7" ? "virtex7" : (C_FAMILY=="qartix7l" ? "virtex7" : (C_FAMILY=="aartix7" ? "virtex7" : (C_FAMILY=="zynq" ? "virtex7" : (C_FAMILY=="azynq" ? "virtex7" : (C_FAMILY=="qzynq" ? "virtex7" : C_FAMILY))))))))))))))))));
// Internal configuration parameters
//---------------------------------------------
localparam SINGLE_PORT = (C_MEM_TYPE==0 || C_MEM_TYPE==3);
localparam IS_ROM = (C_MEM_TYPE==3 || C_MEM_TYPE==4);
localparam HAS_A_WRITE = (!IS_ROM);
localparam HAS_B_WRITE = (C_MEM_TYPE==2);
localparam HAS_A_READ = (C_MEM_TYPE!=1);
localparam HAS_B_READ = (!SINGLE_PORT);
localparam HAS_B_PORT = (HAS_B_READ || HAS_B_WRITE);
// Calculate the mux pipeline register stages for Port A and Port B
//------------------------------------------------------------------
localparam MUX_PIPELINE_STAGES_A = (C_HAS_MUX_OUTPUT_REGS_A) ?
C_MUX_PIPELINE_STAGES : 0;
localparam MUX_PIPELINE_STAGES_B = (C_HAS_MUX_OUTPUT_REGS_B) ?
C_MUX_PIPELINE_STAGES : 0;
// Calculate total number of register stages in the core
// -----------------------------------------------------
localparam NUM_OUTPUT_STAGES_A = (C_HAS_MEM_OUTPUT_REGS_A+MUX_PIPELINE_STAGES_A+C_HAS_MUX_OUTPUT_REGS_A);
localparam NUM_OUTPUT_STAGES_B = (C_HAS_MEM_OUTPUT_REGS_B+MUX_PIPELINE_STAGES_B+C_HAS_MUX_OUTPUT_REGS_B);
wire ena_i;
wire enb_i;
wire reseta_i;
wire resetb_i;
wire [C_WEA_WIDTH-1:0] wea_i;
wire [C_WEB_WIDTH-1:0] web_i;
wire rea_i;
wire reb_i;
wire rsta_outp_stage;
wire rstb_outp_stage;
// ECC SBITERR/DBITERR Outputs
// The ECC Behavior is modeled by the behavioral models only for Virtex-6.
// For Virtex-5, these outputs will be tied to 0.
assign SBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?sbiterr_sdp:0;
assign DBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?dbiterr_sdp:0;
assign RDADDRECC = (((C_FAMILY_LOCALPARAM == "virtex7") && C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?rdaddrecc_sdp:0;
// This effectively wires off optional inputs
assign ena_i = (C_HAS_ENA==0) || ENA;
assign enb_i = ((C_HAS_ENB==0) || ENB) && HAS_B_PORT;
assign wea_i = (HAS_A_WRITE && ena_i) ? WEA : 'b0;
assign web_i = (HAS_B_WRITE && enb_i) ? WEB : 'b0;
assign rea_i = (HAS_A_READ) ? ena_i : 'b0;
assign reb_i = (HAS_B_READ) ? enb_i : 'b0;
// These signals reset the memory latches
assign reseta_i =
((C_HAS_RSTA==1 && RSTA && NUM_OUTPUT_STAGES_A==0) ||
(C_HAS_RSTA==1 && RSTA && C_RSTRAM_A==1));
assign resetb_i =
((C_HAS_RSTB==1 && RSTB && NUM_OUTPUT_STAGES_B==0) ||
(C_HAS_RSTB==1 && RSTB && C_RSTRAM_B==1));
// Tasks to access the memory
//---------------------------
//**************
// write_a
//**************
task write_a
(input reg [C_ADDRA_WIDTH-1:0] addr,
input reg [C_WEA_WIDTH-1:0] byte_en,
input reg [C_WRITE_WIDTH_A-1:0] data,
input inj_sbiterr,
input inj_dbiterr);
reg [C_WRITE_WIDTH_A-1:0] current_contents;
reg [C_ADDRA_WIDTH-1:0] address;
integer i;
begin
// Shift the address by the ratio
address = (addr/WRITE_ADDR_A_DIV);
if (address >= C_WRITE_DEPTH_A) begin
if (!C_DISABLE_WARN_BHV_RANGE) begin
$fdisplay(ADDRFILE,
"%0s WARNING: Address %0h is outside range for A Write",
C_CORENAME, addr);
end
// valid address
end else begin
// Combine w/ byte writes
if (C_USE_BYTE_WEA) begin
// Get the current memory contents
if (WRITE_WIDTH_RATIO_A == 1) begin
// Workaround for IUS 5.5 part-select issue
current_contents = memory[address];
end else begin
for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin
current_contents[MIN_WIDTH*i+:MIN_WIDTH]
= memory[address*WRITE_WIDTH_RATIO_A + i];
end
end
// Apply incoming bytes
if (C_WEA_WIDTH == 1) begin
// Workaround for IUS 5.5 part-select issue
if (byte_en[0]) begin
current_contents = data;
end
end else begin
for (i = 0; i < C_WEA_WIDTH; i = i + 1) begin
if (byte_en[i]) begin
current_contents[BYTE_SIZE*i+:BYTE_SIZE]
= data[BYTE_SIZE*i+:BYTE_SIZE];
end
end
end
// No byte-writes, overwrite the whole word
end else begin
current_contents = data;
end
// Insert double bit errors:
if (C_USE_ECC == 1) begin
if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin
current_contents[0] = !(current_contents[0]);
current_contents[1] = !(current_contents[1]);
end
end
// Insert softecc double bit errors:
if (C_USE_SOFTECC == 1) begin
if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin
doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:2] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-3:0];
doublebit_error[0] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1];
doublebit_error[1] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-2];
current_contents = current_contents ^ doublebit_error[C_WRITE_WIDTH_A-1:0];
end
end
// Write data to memory
if (WRITE_WIDTH_RATIO_A == 1) begin
// Workaround for IUS 5.5 part-select issue
memory[address*WRITE_WIDTH_RATIO_A] = current_contents;
end else begin
for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin
memory[address*WRITE_WIDTH_RATIO_A + i]
= current_contents[MIN_WIDTH*i+:MIN_WIDTH];
end
end
// Store the address at which error is injected:
if ((C_FAMILY_LOCALPARAM == "virtex7") && C_USE_ECC == 1) begin
if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) ||
(C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))
begin
sbiterr_arr[addr] = 1;
end else begin
sbiterr_arr[addr] = 0;
end
if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin
dbiterr_arr[addr] = 1;
end else begin
dbiterr_arr[addr] = 0;
end
end
// Store the address at which softecc error is injected:
if (C_USE_SOFTECC == 1) begin
if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) ||
(C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))
begin
softecc_sbiterr_arr[addr] = 1;
end else begin
softecc_sbiterr_arr[addr] = 0;
end
if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin
softecc_dbiterr_arr[addr] = 1;
end else begin
softecc_dbiterr_arr[addr] = 0;
end
end
end
end
endtask
//**************
// write_b
//**************
task write_b
(input reg [C_ADDRB_WIDTH-1:0] addr,
input reg [C_WEB_WIDTH-1:0] byte_en,
input reg [C_WRITE_WIDTH_B-1:0] data);
reg [C_WRITE_WIDTH_B-1:0] current_contents;
reg [C_ADDRB_WIDTH-1:0] address;
integer i;
begin
// Shift the address by the ratio
address = (addr/WRITE_ADDR_B_DIV);
if (address >= C_WRITE_DEPTH_B) begin
if (!C_DISABLE_WARN_BHV_RANGE) begin
$fdisplay(ADDRFILE,
"%0s WARNING: Address %0h is outside range for B Write",
C_CORENAME, addr);
end
// valid address
end else begin
// Combine w/ byte writes
if (C_USE_BYTE_WEB) begin
// Get the current memory contents
if (WRITE_WIDTH_RATIO_B == 1) begin
// Workaround for IUS 5.5 part-select issue
current_contents = memory[address];
end else begin
for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin
current_contents[MIN_WIDTH*i+:MIN_WIDTH]
= memory[address*WRITE_WIDTH_RATIO_B + i];
end
end
// Apply incoming bytes
if (C_WEB_WIDTH == 1) begin
// Workaround for IUS 5.5 part-select issue
if (byte_en[0]) begin
current_contents = data;
end
end else begin
for (i = 0; i < C_WEB_WIDTH; i = i + 1) begin
if (byte_en[i]) begin
current_contents[BYTE_SIZE*i+:BYTE_SIZE]
= data[BYTE_SIZE*i+:BYTE_SIZE];
end
end
end
// No byte-writes, overwrite the whole word
end else begin
current_contents = data;
end
// Write data to memory
if (WRITE_WIDTH_RATIO_B == 1) begin
// Workaround for IUS 5.5 part-select issue
memory[address*WRITE_WIDTH_RATIO_B] = current_contents;
end else begin
for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin
memory[address*WRITE_WIDTH_RATIO_B + i]
= current_contents[MIN_WIDTH*i+:MIN_WIDTH];
end
end
end
end
endtask
//**************
// read_a
//**************
task read_a
(input reg [C_ADDRA_WIDTH-1:0] addr,
input reg reset);
reg [C_ADDRA_WIDTH-1:0] address;
integer i;
begin
if (reset) begin
memory_out_a <= #FLOP_DELAY inita_val;
end else begin
// Shift the address by the ratio
address = (addr/READ_ADDR_A_DIV);
if (address >= C_READ_DEPTH_A) begin
if (!C_DISABLE_WARN_BHV_RANGE) begin
$fdisplay(ADDRFILE,
"%0s WARNING: Address %0h is outside range for A Read",
C_CORENAME, addr);
end
memory_out_a <= #FLOP_DELAY 'bX;
// valid address
end else begin
if (READ_WIDTH_RATIO_A==1) begin
memory_out_a <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A];
end else begin
// Increment through the 'partial' words in the memory
for (i = 0; i < READ_WIDTH_RATIO_A; i = i + 1) begin
memory_out_a[MIN_WIDTH*i+:MIN_WIDTH]
<= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A + i];
end
end //end READ_WIDTH_RATIO_A==1 loop
end //end valid address loop
end //end reset-data assignment loops
end
endtask
//**************
// read_b
//**************
task read_b
(input reg [C_ADDRB_WIDTH-1:0] addr,
input reg reset);
reg [C_ADDRB_WIDTH-1:0] address;
integer i;
begin
if (reset) begin
memory_out_b <= #FLOP_DELAY initb_val;
sbiterr_in <= #FLOP_DELAY 1'b0;
dbiterr_in <= #FLOP_DELAY 1'b0;
rdaddrecc_in <= #FLOP_DELAY 0;
end else begin
// Shift the address
address = (addr/READ_ADDR_B_DIV);
if (address >= C_READ_DEPTH_B) begin
if (!C_DISABLE_WARN_BHV_RANGE) begin
$fdisplay(ADDRFILE,
"%0s WARNING: Address %0h is outside range for B Read",
C_CORENAME, addr);
end
memory_out_b <= #FLOP_DELAY 'bX;
sbiterr_in <= #FLOP_DELAY 1'bX;
dbiterr_in <= #FLOP_DELAY 1'bX;
rdaddrecc_in <= #FLOP_DELAY 'bX;
// valid address
end else begin
if (READ_WIDTH_RATIO_B==1) begin
memory_out_b <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B];
end else begin
// Increment through the 'partial' words in the memory
for (i = 0; i < READ_WIDTH_RATIO_B; i = i + 1) begin
memory_out_b[MIN_WIDTH*i+:MIN_WIDTH]
<= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B + i];
end
end
if ((C_FAMILY_LOCALPARAM == "virtex7") && C_USE_ECC == 1) begin
rdaddrecc_in <= #FLOP_DELAY addr;
if (sbiterr_arr[addr] == 1) begin
sbiterr_in <= #FLOP_DELAY 1'b1;
end else begin
sbiterr_in <= #FLOP_DELAY 1'b0;
end
if (dbiterr_arr[addr] == 1) begin
dbiterr_in <= #FLOP_DELAY 1'b1;
end else begin
dbiterr_in <= #FLOP_DELAY 1'b0;
end
end else if (C_USE_SOFTECC == 1) begin
rdaddrecc_in <= #FLOP_DELAY addr;
if (softecc_sbiterr_arr[addr] == 1) begin
sbiterr_in <= #FLOP_DELAY 1'b1;
end else begin
sbiterr_in <= #FLOP_DELAY 1'b0;
end
if (softecc_dbiterr_arr[addr] == 1) begin
dbiterr_in <= #FLOP_DELAY 1'b1;
end else begin
dbiterr_in <= #FLOP_DELAY 1'b0;
end
end else begin
rdaddrecc_in <= #FLOP_DELAY 0;
dbiterr_in <= #FLOP_DELAY 1'b0;
sbiterr_in <= #FLOP_DELAY 1'b0;
end //end SOFTECC Loop
end //end Valid address loop
end //end reset-data assignment loops
end
endtask
//**************
// reset_a
//**************
task reset_a (input reg reset);
begin
if (reset) memory_out_a <= #FLOP_DELAY inita_val;
end
endtask
//**************
// reset_b
//**************
task reset_b (input reg reset);
begin
if (reset) memory_out_b <= #FLOP_DELAY initb_val;
end
endtask
//**************
// init_memory
//**************
task init_memory;
integer i, j, addr_step;
integer status;
reg [C_WRITE_WIDTH_A-1:0] default_data;
begin
default_data = 0;
//Display output message indicating that the behavioral model is being
//initialized
if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) $display(" Block Memory Generator module loading initial data...");
// Convert the default to hex
if (C_USE_DEFAULT_DATA) begin
if (default_data_str == "") begin
$fdisplay(ERRFILE, "%0s ERROR: C_DEFAULT_DATA is empty!", C_CORENAME);
$finish;
end else begin
status = $sscanf(default_data_str, "%h", default_data);
if (status == 0) begin
$fdisplay(ERRFILE, {"%0s ERROR: Unsuccessful hexadecimal read",
"from C_DEFAULT_DATA: %0s"},
C_CORENAME, C_DEFAULT_DATA);
$finish;
end
end
end
// Step by WRITE_ADDR_A_DIV through the memory via the
// Port A write interface to hit every location once
addr_step = WRITE_ADDR_A_DIV;
// 'write' to every location with default (or 0)
for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin
write_a(i, {C_WEA_WIDTH{1'b1}}, default_data, 1'b0, 1'b0);
end
// Get specialized data from the MIF file
if (C_LOAD_INIT_FILE) begin
if (init_file_str == "") begin
$fdisplay(ERRFILE, "%0s ERROR: C_INIT_FILE_NAME is empty!",
C_CORENAME);
$finish;
end else begin
initfile = $fopen(init_file_str, "r");
if (initfile == 0) begin
$fdisplay(ERRFILE, {"%0s, ERROR: Problem opening",
"C_INIT_FILE_NAME: %0s!"},
C_CORENAME, init_file_str);
$finish;
end else begin
// loop through the mif file, loading in the data
for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin
status = $fscanf(initfile, "%b", mif_data);
if (status > 0) begin
write_a(i, {C_WEA_WIDTH{1'b1}}, mif_data, 1'b0, 1'b0);
end
end
$fclose(initfile);
end //initfile
end //init_file_str
end //C_LOAD_INIT_FILE
if (C_USE_BRAM_BLOCK) begin
// Get specialized data from the MIF file
if (C_INIT_FILE != "NONE") begin
if (mem_init_file_str == "") begin
$fdisplay(ERRFILE, "%0s ERROR: C_INIT_FILE is empty!",
C_CORENAME);
$finish;
end else begin
meminitfile = $fopen(mem_init_file_str, "r");
if (meminitfile == 0) begin
$fdisplay(ERRFILE, {"%0s, ERROR: Problem opening",
"C_INIT_FILE: %0s!"},
C_CORENAME, mem_init_file_str);
$finish;
end else begin
// loop through the mif file, loading in the data
$readmemh(mem_init_file_str, memory );
for (j = 0; j < MAX_DEPTH-1 ; j = j + 1) begin
end
$fclose(meminitfile);
end //meminitfile
end //mem_init_file_str
end //C_INIT_FILE
end //C_USE_BRAM_BLOCK
//Display output message indicating that the behavioral model is done
//initializing
if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE)
$display(" Block Memory Generator data initialization complete.");
end
endtask
//**************
// log2roundup
//**************
function integer log2roundup (input integer data_value);
integer width;
integer cnt;
begin
width = 0;
if (data_value > 1) begin
for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin
width = width + 1;
end //loop
end //if
log2roundup = width;
end //log2roundup
endfunction
//*******************
// collision_check
//*******************
function integer collision_check (input reg [C_ADDRA_WIDTH-1:0] addr_a,
input integer iswrite_a,
input reg [C_ADDRB_WIDTH-1:0] addr_b,
input integer iswrite_b);
reg c_aw_bw, c_aw_br, c_ar_bw;
integer scaled_addra_to_waddrb_width;
integer scaled_addrb_to_waddrb_width;
integer scaled_addra_to_waddra_width;
integer scaled_addrb_to_waddra_width;
integer scaled_addra_to_raddrb_width;
integer scaled_addrb_to_raddrb_width;
integer scaled_addra_to_raddra_width;
integer scaled_addrb_to_raddra_width;
begin
c_aw_bw = 0;
c_aw_br = 0;
c_ar_bw = 0;
//If write_addr_b_width is smaller, scale both addresses to that width for
//comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,
//scale it down to write_addr_b_width. addr_b starts as C_ADDRB_WIDTH,
//scale it down to write_addr_b_width. Once both are scaled to
//write_addr_b_width, compare.
scaled_addra_to_waddrb_width = ((addr_a)/
2**(C_ADDRA_WIDTH-write_addr_b_width));
scaled_addrb_to_waddrb_width = ((addr_b)/
2**(C_ADDRB_WIDTH-write_addr_b_width));
//If write_addr_a_width is smaller, scale both addresses to that width for
//comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,
//scale it down to write_addr_a_width. addr_b starts as C_ADDRB_WIDTH,
//scale it down to write_addr_a_width. Once both are scaled to
//write_addr_a_width, compare.
scaled_addra_to_waddra_width = ((addr_a)/
2**(C_ADDRA_WIDTH-write_addr_a_width));
scaled_addrb_to_waddra_width = ((addr_b)/
2**(C_ADDRB_WIDTH-write_addr_a_width));
//If read_addr_b_width is smaller, scale both addresses to that width for
//comparing write_addr_a and read_addr_b; addr_a starts as C_ADDRA_WIDTH,
//scale it down to read_addr_b_width. addr_b starts as C_ADDRB_WIDTH,
//scale it down to read_addr_b_width. Once both are scaled to
//read_addr_b_width, compare.
scaled_addra_to_raddrb_width = ((addr_a)/
2**(C_ADDRA_WIDTH-read_addr_b_width));
scaled_addrb_to_raddrb_width = ((addr_b)/
2**(C_ADDRB_WIDTH-read_addr_b_width));
//If read_addr_a_width is smaller, scale both addresses to that width for
//comparing read_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,
//scale it down to read_addr_a_width. addr_b starts as C_ADDRB_WIDTH,
//scale it down to read_addr_a_width. Once both are scaled to
//read_addr_a_width, compare.
scaled_addra_to_raddra_width = ((addr_a)/
2**(C_ADDRA_WIDTH-read_addr_a_width));
scaled_addrb_to_raddra_width = ((addr_b)/
2**(C_ADDRB_WIDTH-read_addr_a_width));
//Look for a write-write collision. In order for a write-write
//collision to exist, both ports must have a write transaction.
if (iswrite_a && iswrite_b) begin
if (write_addr_a_width > write_addr_b_width) begin
if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin
c_aw_bw = 1;
end else begin
c_aw_bw = 0;
end
end else begin
if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin
c_aw_bw = 1;
end else begin
c_aw_bw = 0;
end
end //width
end //iswrite_a and iswrite_b
//If the B port is reading (which means it is enabled - so could be
//a TX_WRITE or TX_READ), then check for a write-read collision).
//This could happen whether or not a write-write collision exists due
//to asymmetric write/read ports.
if (iswrite_a) begin
if (write_addr_a_width > read_addr_b_width) begin
if (scaled_addra_to_raddrb_width == scaled_addrb_to_raddrb_width) begin
c_aw_br = 1;
end else begin
c_aw_br = 0;
end
end else begin
if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin
c_aw_br = 1;
end else begin
c_aw_br = 0;
end
end //width
end //iswrite_a
//If the A port is reading (which means it is enabled - so could be
// a TX_WRITE or TX_READ), then check for a write-read collision).
//This could happen whether or not a write-write collision exists due
// to asymmetric write/read ports.
if (iswrite_b) begin
if (read_addr_a_width > write_addr_b_width) begin
if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin
c_ar_bw = 1;
end else begin
c_ar_bw = 0;
end
end else begin
if (scaled_addrb_to_raddra_width == scaled_addra_to_raddra_width) begin
c_ar_bw = 1;
end else begin
c_ar_bw = 0;
end
end //width
end //iswrite_b
collision_check = c_aw_bw | c_aw_br | c_ar_bw;
end
endfunction
//*******************************
// power on values
//*******************************
initial begin
// Load up the memory
init_memory;
// Load up the output registers and latches
if ($sscanf(inita_str, "%h", inita_val)) begin
memory_out_a = inita_val;
end else begin
memory_out_a = 0;
end
if ($sscanf(initb_str, "%h", initb_val)) begin
memory_out_b = initb_val;
end else begin
memory_out_b = 0;
end
sbiterr_in = 1'b0;
dbiterr_in = 1'b0;
rdaddrecc_in = 0;
// Determine the effective address widths for each of the 4 ports
write_addr_a_width = C_ADDRA_WIDTH - log2roundup(WRITE_ADDR_A_DIV);
read_addr_a_width = C_ADDRA_WIDTH - log2roundup(READ_ADDR_A_DIV);
write_addr_b_width = C_ADDRB_WIDTH - log2roundup(WRITE_ADDR_B_DIV);
read_addr_b_width = C_ADDRB_WIDTH - log2roundup(READ_ADDR_B_DIV);
$display("Block Memory Generator module %m is using a behavioral model for simulation which will not precisely model memory collision behavior.");
end
//***************************************************************************
// These are the main blocks which schedule read and write operations
// Note that the reset priority feature at the latch stage is only supported
// for Spartan-6. For other families, the default priority at the latch stage
// is "CE"
//***************************************************************************
// Synchronous clocks: schedule port operations with respect to
// both write operating modes
generate
if(C_COMMON_CLK && (C_WRITE_MODE_A == "WRITE_FIRST") && (C_WRITE_MODE_B ==
"WRITE_FIRST")) begin : com_clk_sched_wf_wf
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
end
end
else
if(C_COMMON_CLK && (C_WRITE_MODE_A == "READ_FIRST") && (C_WRITE_MODE_B ==
"WRITE_FIRST")) begin : com_clk_sched_rf_wf
always @(posedge CLKA) begin
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
end
end
else
if(C_COMMON_CLK && (C_WRITE_MODE_A == "WRITE_FIRST") && (C_WRITE_MODE_B ==
"READ_FIRST")) begin : com_clk_sched_wf_rf
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else
if(C_COMMON_CLK && (C_WRITE_MODE_A == "READ_FIRST") && (C_WRITE_MODE_B ==
"READ_FIRST")) begin : com_clk_sched_rf_rf
always @(posedge CLKA) begin
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="WRITE_FIRST") && (C_WRITE_MODE_B ==
"NO_CHANGE")) begin : com_clk_sched_wf_nc
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="READ_FIRST") && (C_WRITE_MODE_B ==
"NO_CHANGE")) begin : com_clk_sched_rf_nc
always @(posedge CLKA) begin
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B ==
"WRITE_FIRST")) begin : com_clk_sched_nc_wf
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read A
if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B ==
"READ_FIRST")) begin : com_clk_sched_nc_rf
always @(posedge CLKA) begin
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Read A
if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B ==
"NO_CHANGE")) begin : com_clk_sched_nc_nc
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read A
if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);
//Read B
if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);
end
end
else if(C_COMMON_CLK) begin: com_clk_sched_default
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
end
end
endgenerate
// Asynchronous clocks: port operation is independent
generate
if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "WRITE_FIRST")) begin : async_clk_sched_clka_wf
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
end
end
else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "READ_FIRST")) begin : async_clk_sched_clka_rf
always @(posedge CLKA) begin
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
end
end
else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "NO_CHANGE")) begin : async_clk_sched_clka_nc
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Read A
if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);
end
end
endgenerate
generate
if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "WRITE_FIRST")) begin: async_clk_sched_clkb_wf
always @(posedge CLKB) begin
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
end
end
else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "READ_FIRST")) begin: async_clk_sched_clkb_rf
always @(posedge CLKB) begin
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "NO_CHANGE")) begin: async_clk_sched_clkb_nc
always @(posedge CLKB) begin
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read B
if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);
end
end
endgenerate
//***************************************************************
// Instantiate the variable depth output register stage module
//***************************************************************
// Port A
assign rsta_outp_stage = RSTA & (~SLEEP);
BLK_MEM_GEN_v8_2_output_stage
#(.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_RST_TYPE ("SYNC"),
.C_HAS_RST (C_HAS_RSTA),
.C_RSTRAM (C_RSTRAM_A),
.C_RST_PRIORITY (C_RST_PRIORITY_A),
.C_INIT_VAL (C_INITA_VAL),
.C_HAS_EN (C_HAS_ENA),
.C_HAS_REGCE (C_HAS_REGCEA),
.C_DATA_WIDTH (C_READ_WIDTH_A),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_MEM_OUTPUT_REGS (C_HAS_MEM_OUTPUT_REGS_A),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.NUM_STAGES (NUM_OUTPUT_STAGES_A),
.C_EN_ECC_PIPE (0),
.FLOP_DELAY (FLOP_DELAY))
reg_a
(.CLK (CLKA),
.RST (rsta_outp_stage),//(RSTA),
.EN (ENA),
.REGCE (REGCEA),
.DIN_I (memory_out_a),
.DOUT (DOUTA),
.SBITERR_IN_I (1'b0),
.DBITERR_IN_I (1'b0),
.SBITERR (),
.DBITERR (),
.RDADDRECC_IN_I ({C_ADDRB_WIDTH{1'b0}}),
.ECCPIPECE (1'b0),
.RDADDRECC ()
);
assign rstb_outp_stage = RSTB & (~SLEEP);
// Port B
BLK_MEM_GEN_v8_2_output_stage
#(.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_RST_TYPE ("SYNC"),
.C_HAS_RST (C_HAS_RSTB),
.C_RSTRAM (C_RSTRAM_B),
.C_RST_PRIORITY (C_RST_PRIORITY_B),
.C_INIT_VAL (C_INITB_VAL),
.C_HAS_EN (C_HAS_ENB),
.C_HAS_REGCE (C_HAS_REGCEB),
.C_DATA_WIDTH (C_READ_WIDTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_MEM_OUTPUT_REGS (C_HAS_MEM_OUTPUT_REGS_B),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.NUM_STAGES (NUM_OUTPUT_STAGES_B),
.C_EN_ECC_PIPE (C_EN_ECC_PIPE),
.FLOP_DELAY (FLOP_DELAY))
reg_b
(.CLK (CLKB),
.RST (rstb_outp_stage),//(RSTB),
.EN (ENB),
.REGCE (REGCEB),
.DIN_I (memory_out_b),
.DOUT (dout_i),
.SBITERR_IN_I (sbiterr_in),
.DBITERR_IN_I (dbiterr_in),
.SBITERR (sbiterr_i),
.DBITERR (dbiterr_i),
.RDADDRECC_IN_I (rdaddrecc_in),
.ECCPIPECE (ECCPIPECE),
.RDADDRECC (rdaddrecc_i)
);
//***************************************************************
// Instantiate the Input and Output register stages
//***************************************************************
BLK_MEM_GEN_v8_2_softecc_output_reg_stage
#(.C_DATA_WIDTH (C_READ_WIDTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),
.C_USE_SOFTECC (C_USE_SOFTECC),
.FLOP_DELAY (FLOP_DELAY))
has_softecc_output_reg_stage
(.CLK (CLKB),
.DIN (dout_i),
.DOUT (DOUTB),
.SBITERR_IN (sbiterr_i),
.DBITERR_IN (dbiterr_i),
.SBITERR (sbiterr_sdp),
.DBITERR (dbiterr_sdp),
.RDADDRECC_IN (rdaddrecc_i),
.RDADDRECC (rdaddrecc_sdp)
);
//****************************************************
// Synchronous collision checks
//****************************************************
// CR 780544 : To make verilog model's collison warnings in consistant with
// vhdl model, the non-blocking assignments are replaced with blocking
// assignments.
generate if (!C_DISABLE_WARN_BHV_COLL && C_COMMON_CLK) begin : sync_coll
always @(posedge CLKA) begin
// Possible collision if both are enabled and the addresses match
if (ena_i && enb_i) begin
if (wea_i || web_i) begin
is_collision = collision_check(ADDRA, wea_i, ADDRB, web_i);
end else begin
is_collision = 0;
end
end else begin
is_collision = 0;
end
// If the write port is in READ_FIRST mode, there is no collision
if (C_WRITE_MODE_A=="READ_FIRST" && wea_i && !web_i) begin
is_collision = 0;
end
if (C_WRITE_MODE_B=="READ_FIRST" && web_i && !wea_i) begin
is_collision = 0;
end
// Only flag if one of the accesses is a write
if (is_collision && (wea_i || web_i)) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A %0s address: %0h, B %0s address: %0h\n",
wea_i ? "write" : "read", ADDRA,
web_i ? "write" : "read", ADDRB);
end
end
//****************************************************
// Asynchronous collision checks
//****************************************************
end else if (!C_DISABLE_WARN_BHV_COLL && !C_COMMON_CLK) begin : async_coll
// Delay A and B addresses in order to mimic setup/hold times
wire [C_ADDRA_WIDTH-1:0] #COLL_DELAY addra_delay = ADDRA;
wire [0:0] #COLL_DELAY wea_delay = wea_i;
wire #COLL_DELAY ena_delay = ena_i;
wire [C_ADDRB_WIDTH-1:0] #COLL_DELAY addrb_delay = ADDRB;
wire [0:0] #COLL_DELAY web_delay = web_i;
wire #COLL_DELAY enb_delay = enb_i;
// Do the checks w/rt A
always @(posedge CLKA) begin
// Possible collision if both are enabled and the addresses match
if (ena_i && enb_i) begin
if (wea_i || web_i) begin
is_collision_a = collision_check(ADDRA, wea_i, ADDRB, web_i);
end else begin
is_collision_a = 0;
end
end else begin
is_collision_a = 0;
end
if (ena_i && enb_delay) begin
if(wea_i || web_delay) begin
is_collision_delay_a = collision_check(ADDRA, wea_i, addrb_delay,
web_delay);
end else begin
is_collision_delay_a = 0;
end
end else begin
is_collision_delay_a = 0;
end
// Only flag if B access is a write
if (is_collision_a && web_i) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A %0s address: %0h, B write address: %0h\n",
wea_i ? "write" : "read", ADDRA, ADDRB);
end else if (is_collision_delay_a && web_delay) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A %0s address: %0h, B write address: %0h\n",
wea_i ? "write" : "read", ADDRA, addrb_delay);
end
end
// Do the checks w/rt B
always @(posedge CLKB) begin
// Possible collision if both are enabled and the addresses match
if (ena_i && enb_i) begin
if (wea_i || web_i) begin
is_collision_b = collision_check(ADDRA, wea_i, ADDRB, web_i);
end else begin
is_collision_b = 0;
end
end else begin
is_collision_b = 0;
end
if (ena_delay && enb_i) begin
if (wea_delay || web_i) begin
is_collision_delay_b = collision_check(addra_delay, wea_delay, ADDRB,
web_i);
end else begin
is_collision_delay_b = 0;
end
end else begin
is_collision_delay_b = 0;
end
// Only flag if A access is a write
if (is_collision_b && wea_i) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A write address: %0h, B %s address: %0h\n",
ADDRA, web_i ? "write" : "read", ADDRB);
end else if (is_collision_delay_b && wea_delay) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A write address: %0h, B %s address: %0h\n",
addra_delay, web_i ? "write" : "read", ADDRB);
end
end
end
endgenerate
endmodule
//*****************************************************************************
// Top module wraps Input register and Memory module
//
// This module is the top-level behavioral model and this implements the memory
// module and the input registers
//*****************************************************************************
module blk_mem_gen_v8_2
#(parameter C_CORENAME = "blk_mem_gen_v8_2",
parameter C_FAMILY = "virtex7",
parameter C_XDEVICEFAMILY = "virtex7",
parameter C_ELABORATION_DIR = "",
parameter C_INTERFACE_TYPE = 0,
parameter C_USE_BRAM_BLOCK = 0,
parameter C_CTRL_ECC_ALGO = "NONE",
parameter C_ENABLE_32BIT_ADDRESS = 0,
parameter C_AXI_TYPE = 0,
parameter C_AXI_SLAVE_TYPE = 0,
parameter C_HAS_AXI_ID = 0,
parameter C_AXI_ID_WIDTH = 4,
parameter C_MEM_TYPE = 2,
parameter C_BYTE_SIZE = 9,
parameter C_ALGORITHM = 1,
parameter C_PRIM_TYPE = 3,
parameter C_LOAD_INIT_FILE = 0,
parameter C_INIT_FILE_NAME = "",
parameter C_INIT_FILE = "",
parameter C_USE_DEFAULT_DATA = 0,
parameter C_DEFAULT_DATA = "0",
//parameter C_RST_TYPE = "SYNC",
parameter C_HAS_RSTA = 0,
parameter C_RST_PRIORITY_A = "CE",
parameter C_RSTRAM_A = 0,
parameter C_INITA_VAL = "0",
parameter C_HAS_ENA = 1,
parameter C_HAS_REGCEA = 0,
parameter C_USE_BYTE_WEA = 0,
parameter C_WEA_WIDTH = 1,
parameter C_WRITE_MODE_A = "WRITE_FIRST",
parameter C_WRITE_WIDTH_A = 32,
parameter C_READ_WIDTH_A = 32,
parameter C_WRITE_DEPTH_A = 64,
parameter C_READ_DEPTH_A = 64,
parameter C_ADDRA_WIDTH = 5,
parameter C_HAS_RSTB = 0,
parameter C_RST_PRIORITY_B = "CE",
parameter C_RSTRAM_B = 0,
parameter C_INITB_VAL = "",
parameter C_HAS_ENB = 1,
parameter C_HAS_REGCEB = 0,
parameter C_USE_BYTE_WEB = 0,
parameter C_WEB_WIDTH = 1,
parameter C_WRITE_MODE_B = "WRITE_FIRST",
parameter C_WRITE_WIDTH_B = 32,
parameter C_READ_WIDTH_B = 32,
parameter C_WRITE_DEPTH_B = 64,
parameter C_READ_DEPTH_B = 64,
parameter C_ADDRB_WIDTH = 5,
parameter C_HAS_MEM_OUTPUT_REGS_A = 0,
parameter C_HAS_MEM_OUTPUT_REGS_B = 0,
parameter C_HAS_MUX_OUTPUT_REGS_A = 0,
parameter C_HAS_MUX_OUTPUT_REGS_B = 0,
parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,
parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,
parameter C_MUX_PIPELINE_STAGES = 0,
parameter C_USE_SOFTECC = 0,
parameter C_USE_ECC = 0,
parameter C_EN_ECC_PIPE = 0,
parameter C_HAS_INJECTERR = 0,
parameter C_SIM_COLLISION_CHECK = "NONE",
parameter C_COMMON_CLK = 1,
parameter C_DISABLE_WARN_BHV_COLL = 0,
parameter C_EN_SLEEP_PIN = 0,
parameter C_USE_URAM = 0,
parameter C_EN_RDADDRA_CHG = 0,
parameter C_EN_RDADDRB_CHG = 0,
parameter C_EN_DEEPSLEEP_PIN = 0,
parameter C_EN_SHUTDOWN_PIN = 0,
parameter C_DISABLE_WARN_BHV_RANGE = 0,
parameter C_COUNT_36K_BRAM = "",
parameter C_COUNT_18K_BRAM = "",
parameter C_EST_POWER_SUMMARY = ""
)
(input clka,
input rsta,
input ena,
input regcea,
input [C_WEA_WIDTH-1:0] wea,
input [C_ADDRA_WIDTH-1:0] addra,
input [C_WRITE_WIDTH_A-1:0] dina,
output [C_READ_WIDTH_A-1:0] douta,
input clkb,
input rstb,
input enb,
input regceb,
input [C_WEB_WIDTH-1:0] web,
input [C_ADDRB_WIDTH-1:0] addrb,
input [C_WRITE_WIDTH_B-1:0] dinb,
output [C_READ_WIDTH_B-1:0] doutb,
input injectsbiterr,
input injectdbiterr,
output sbiterr,
output dbiterr,
output [C_ADDRB_WIDTH-1:0] rdaddrecc,
input eccpipece,
input sleep,
input deepsleep,
input shutdown,
//AXI BMG Input and Output Port Declarations
//AXI Global Signals
input s_aclk,
input s_aresetn,
//AXI Full/lite slave write (write side)
input [C_AXI_ID_WIDTH-1:0] s_axi_awid,
input [31:0] s_axi_awaddr,
input [7:0] s_axi_awlen,
input [2:0] s_axi_awsize,
input [1:0] s_axi_awburst,
input s_axi_awvalid,
output s_axi_awready,
input [C_WRITE_WIDTH_A-1:0] s_axi_wdata,
input [C_WEA_WIDTH-1:0] s_axi_wstrb,
input s_axi_wlast,
input s_axi_wvalid,
output s_axi_wready,
output [C_AXI_ID_WIDTH-1:0] s_axi_bid,
output [1:0] s_axi_bresp,
output s_axi_bvalid,
input s_axi_bready,
//AXI Full/lite slave read (write side)
input [C_AXI_ID_WIDTH-1:0] s_axi_arid,
input [31:0] s_axi_araddr,
input [7:0] s_axi_arlen,
input [2:0] s_axi_arsize,
input [1:0] s_axi_arburst,
input s_axi_arvalid,
output s_axi_arready,
output [C_AXI_ID_WIDTH-1:0] s_axi_rid,
output [C_WRITE_WIDTH_B-1:0] s_axi_rdata,
output [1:0] s_axi_rresp,
output s_axi_rlast,
output s_axi_rvalid,
input s_axi_rready,
//AXI Full/lite sideband signals
input s_axi_injectsbiterr,
input s_axi_injectdbiterr,
output s_axi_sbiterr,
output s_axi_dbiterr,
output [C_ADDRB_WIDTH-1:0] s_axi_rdaddrecc
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_CORENAME : Instance name of the Block Memory Generator core
// C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
// options are available - "spartan3", "spartan6",
// "virtex4", "virtex5", "virtex6" and "virtex6l".
// C_MEM_TYPE : Designates memory type.
// It can be
// 0 - Single Port Memory
// 1 - Simple Dual Port Memory
// 2 - True Dual Port Memory
// 3 - Single Port Read Only Memory
// 4 - Dual Port Read Only Memory
// C_BYTE_SIZE : Size of a byte (8 or 9 bits)
// C_ALGORITHM : Designates the algorithm method used
// for constructing the memory.
// It can be Fixed_Primitives, Minimum_Area or
// Low_Power
// C_PRIM_TYPE : Designates the user selected primitive used to
// construct the memory.
//
// C_LOAD_INIT_FILE : Designates the use of an initialization file to
// initialize memory contents.
// C_INIT_FILE_NAME : Memory initialization file name.
// C_USE_DEFAULT_DATA : Designates whether to fill remaining
// initialization space with default data
// C_DEFAULT_DATA : Default value of all memory locations
// not initialized by the memory
// initialization file.
// C_RST_TYPE : Type of reset - Synchronous or Asynchronous
// C_HAS_RSTA : Determines the presence of the RSTA port
// C_RST_PRIORITY_A : Determines the priority between CE and SR for
// Port A.
// C_RSTRAM_A : Determines if special reset behavior is used for
// Port A
// C_INITA_VAL : The initialization value for Port A
// C_HAS_ENA : Determines the presence of the ENA port
// C_HAS_REGCEA : Determines the presence of the REGCEA port
// C_USE_BYTE_WEA : Determines if the Byte Write is used or not.
// C_WEA_WIDTH : The width of the WEA port
// C_WRITE_MODE_A : Configurable write mode for Port A. It can be
// WRITE_FIRST, READ_FIRST or NO_CHANGE.
// C_WRITE_WIDTH_A : Memory write width for Port A.
// C_READ_WIDTH_A : Memory read width for Port A.
// C_WRITE_DEPTH_A : Memory write depth for Port A.
// C_READ_DEPTH_A : Memory read depth for Port A.
// C_ADDRA_WIDTH : Width of the ADDRA input port
// C_HAS_RSTB : Determines the presence of the RSTB port
// C_RST_PRIORITY_B : Determines the priority between CE and SR for
// Port B.
// C_RSTRAM_B : Determines if special reset behavior is used for
// Port B
// C_INITB_VAL : The initialization value for Port B
// C_HAS_ENB : Determines the presence of the ENB port
// C_HAS_REGCEB : Determines the presence of the REGCEB port
// C_USE_BYTE_WEB : Determines if the Byte Write is used or not.
// C_WEB_WIDTH : The width of the WEB port
// C_WRITE_MODE_B : Configurable write mode for Port B. It can be
// WRITE_FIRST, READ_FIRST or NO_CHANGE.
// C_WRITE_WIDTH_B : Memory write width for Port B.
// C_READ_WIDTH_B : Memory read width for Port B.
// C_WRITE_DEPTH_B : Memory write depth for Port B.
// C_READ_DEPTH_B : Memory read depth for Port B.
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output
// of the RAM primitive for Port A.
// C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output
// of the RAM primitive for Port B.
// C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
// of the MUX for Port A.
// C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
// of the MUX for Port B.
// C_HAS_SOFTECC_INPUT_REGS_A :
// C_HAS_SOFTECC_OUTPUT_REGS_B :
// C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in
// between the muxes.
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// C_USE_ECC : Determines if the ECC feature is used or
// not. Only applicable for V5 and V6
// C_HAS_INJECTERR : Determines if the error injection pins
// are present or not. If the ECC feature
// is not used, this value is defaulted to
// 0, else the following are the allowed
// values:
// 0 : No INJECTSBITERR or INJECTDBITERR pins
// 1 : Only INJECTSBITERR pin exists
// 2 : Only INJECTDBITERR pin exists
// 3 : Both INJECTSBITERR and INJECTDBITERR pins exist
// C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision
// warnings. It can be "ALL", "NONE",
// "Warnings_Only" or "Generate_X_Only".
// C_COMMON_CLK : Determins if the core has a single CLK input.
// C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
// C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range
// warnings
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLKA : Clock to synchronize all read and write operations of Port A.
// RSTA : Reset input to reset memory outputs to a user-defined
// reset state for Port A.
// ENA : Enable all read and write operations of Port A.
// REGCEA : Register Clock Enable to control each pipeline output
// register stages for Port A.
// WEA : Write Enable to enable all write operations of Port A.
// ADDRA : Address of Port A.
// DINA : Data input of Port A.
// DOUTA : Data output of Port A.
// CLKB : Clock to synchronize all read and write operations of Port B.
// RSTB : Reset input to reset memory outputs to a user-defined
// reset state for Port B.
// ENB : Enable all read and write operations of Port B.
// REGCEB : Register Clock Enable to control each pipeline output
// register stages for Port B.
// WEB : Write Enable to enable all write operations of Port B.
// ADDRB : Address of Port B.
// DINB : Data input of Port B.
// DOUTB : Data output of Port B.
// INJECTSBITERR : Single Bit ECC Error Injection Pin.
// INJECTDBITERR : Double Bit ECC Error Injection Pin.
// SBITERR : Output signal indicating that a Single Bit ECC Error has been
// detected and corrected.
// DBITERR : Output signal indicating that a Double Bit ECC Error has been
// detected.
// RDADDRECC : Read Address Output signal indicating address at which an
// ECC error has occurred.
//////////////////////////////////////////////////////////////////////////
wire SBITERR;
wire DBITERR;
wire S_AXI_AWREADY;
wire S_AXI_WREADY;
wire S_AXI_BVALID;
wire S_AXI_ARREADY;
wire S_AXI_RLAST;
wire S_AXI_RVALID;
wire S_AXI_SBITERR;
wire S_AXI_DBITERR;
wire [C_WEA_WIDTH-1:0] WEA = wea;
wire [C_ADDRA_WIDTH-1:0] ADDRA = addra;
wire [C_WRITE_WIDTH_A-1:0] DINA = dina;
wire [C_READ_WIDTH_A-1:0] DOUTA;
wire [C_WEB_WIDTH-1:0] WEB = web;
wire [C_ADDRB_WIDTH-1:0] ADDRB = addrb;
wire [C_WRITE_WIDTH_B-1:0] DINB = dinb;
wire [C_READ_WIDTH_B-1:0] DOUTB;
wire [C_ADDRB_WIDTH-1:0] RDADDRECC;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID = s_axi_awid;
wire [31:0] S_AXI_AWADDR = s_axi_awaddr;
wire [7:0] S_AXI_AWLEN = s_axi_awlen;
wire [2:0] S_AXI_AWSIZE = s_axi_awsize;
wire [1:0] S_AXI_AWBURST = s_axi_awburst;
wire [C_WRITE_WIDTH_A-1:0] S_AXI_WDATA = s_axi_wdata;
wire [C_WEA_WIDTH-1:0] S_AXI_WSTRB = s_axi_wstrb;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID;
wire [1:0] S_AXI_BRESP;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID = s_axi_arid;
wire [31:0] S_AXI_ARADDR = s_axi_araddr;
wire [7:0] S_AXI_ARLEN = s_axi_arlen;
wire [2:0] S_AXI_ARSIZE = s_axi_arsize;
wire [1:0] S_AXI_ARBURST = s_axi_arburst;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID;
wire [C_WRITE_WIDTH_B-1:0] S_AXI_RDATA;
wire [1:0] S_AXI_RRESP;
wire [C_ADDRB_WIDTH-1:0] S_AXI_RDADDRECC;
// Added to fix the simulation warning #CR731605
wire [C_WEB_WIDTH-1:0] WEB_parameterized = 0;
wire ECCPIPECE;
wire SLEEP;
assign CLKA = clka;
assign RSTA = rsta;
assign ENA = ena;
assign REGCEA = regcea;
assign CLKB = clkb;
assign RSTB = rstb;
assign ENB = enb;
assign REGCEB = regceb;
assign INJECTSBITERR = injectsbiterr;
assign INJECTDBITERR = injectdbiterr;
assign ECCPIPECE = eccpipece;
assign SLEEP = sleep;
assign sbiterr = SBITERR;
assign dbiterr = DBITERR;
assign S_ACLK = s_aclk;
assign S_ARESETN = s_aresetn;
assign S_AXI_AWVALID = s_axi_awvalid;
assign s_axi_awready = S_AXI_AWREADY;
assign S_AXI_WLAST = s_axi_wlast;
assign S_AXI_WVALID = s_axi_wvalid;
assign s_axi_wready = S_AXI_WREADY;
assign s_axi_bvalid = S_AXI_BVALID;
assign S_AXI_BREADY = s_axi_bready;
assign S_AXI_ARVALID = s_axi_arvalid;
assign s_axi_arready = S_AXI_ARREADY;
assign s_axi_rlast = S_AXI_RLAST;
assign s_axi_rvalid = S_AXI_RVALID;
assign S_AXI_RREADY = s_axi_rready;
assign S_AXI_INJECTSBITERR = s_axi_injectsbiterr;
assign S_AXI_INJECTDBITERR = s_axi_injectdbiterr;
assign s_axi_sbiterr = S_AXI_SBITERR;
assign s_axi_dbiterr = S_AXI_DBITERR;
assign doutb = DOUTB;
assign douta = DOUTA;
assign rdaddrecc = RDADDRECC;
assign s_axi_bid = S_AXI_BID;
assign s_axi_bresp = S_AXI_BRESP;
assign s_axi_rid = S_AXI_RID;
assign s_axi_rdata = S_AXI_RDATA;
assign s_axi_rresp = S_AXI_RRESP;
assign s_axi_rdaddrecc = S_AXI_RDADDRECC;
localparam FLOP_DELAY = 100; // 100 ps
reg injectsbiterr_in;
reg injectdbiterr_in;
reg rsta_in;
reg ena_in;
reg regcea_in;
reg [C_WEA_WIDTH-1:0] wea_in;
reg [C_ADDRA_WIDTH-1:0] addra_in;
reg [C_WRITE_WIDTH_A-1:0] dina_in;
wire [C_ADDRA_WIDTH-1:0] s_axi_awaddr_out_c;
wire [C_ADDRB_WIDTH-1:0] s_axi_araddr_out_c;
wire s_axi_wr_en_c;
wire s_axi_rd_en_c;
wire s_aresetn_a_c;
wire [7:0] s_axi_arlen_c ;
wire [C_AXI_ID_WIDTH-1 : 0] s_axi_rid_c;
wire [C_WRITE_WIDTH_B-1 : 0] s_axi_rdata_c;
wire [1:0] s_axi_rresp_c;
wire s_axi_rlast_c;
wire s_axi_rvalid_c;
wire s_axi_rready_c;
wire regceb_c;
localparam C_AXI_PAYLOAD = (C_HAS_MUX_OUTPUT_REGS_B == 1)?C_WRITE_WIDTH_B+C_AXI_ID_WIDTH+3:C_AXI_ID_WIDTH+3;
wire [C_AXI_PAYLOAD-1 : 0] s_axi_payload_c;
wire [C_AXI_PAYLOAD-1 : 0] m_axi_payload_c;
//**************
// log2roundup
//**************
function integer log2roundup (input integer data_value);
integer width;
integer cnt;
begin
width = 0;
if (data_value > 1) begin
for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin
width = width + 1;
end //loop
end //if
log2roundup = width;
end //log2roundup
endfunction
//**************
// log2int
//**************
function integer log2int (input integer data_value);
integer width;
integer cnt;
begin
width = 0;
cnt= data_value;
for(cnt=data_value ; cnt >1 ; cnt = cnt / 2) begin
width = width + 1;
end //loop
log2int = width;
end //log2int
endfunction
//**************************************************************************
// FUNCTION : divroundup
// Returns the ceiling value of the division
// Data_value - the quantity to be divided, dividend
// Divisor - the value to divide the data_value by
//**************************************************************************
function integer divroundup (input integer data_value,input integer divisor);
integer div;
begin
div = data_value/divisor;
if ((data_value % divisor) != 0) begin
div = div+1;
end //if
divroundup = div;
end //if
endfunction
localparam AXI_FULL_MEMORY_SLAVE = ((C_AXI_SLAVE_TYPE == 0 && C_AXI_TYPE == 1)?1:0);
localparam C_AXI_ADDR_WIDTH_MSB = C_ADDRA_WIDTH+log2roundup(C_WRITE_WIDTH_A/8);
localparam C_AXI_ADDR_WIDTH = C_AXI_ADDR_WIDTH_MSB;
//Data Width Number of LSB address bits to be discarded
//1 to 16 1
//17 to 32 2
//33 to 64 3
//65 to 128 4
//129 to 256 5
//257 to 512 6
//513 to 1024 7
// The following two constants determine this.
localparam LOWER_BOUND_VAL = (log2roundup(divroundup(C_WRITE_WIDTH_A,8) == 0))?0:(log2roundup(divroundup(C_WRITE_WIDTH_A,8)));
localparam C_AXI_ADDR_WIDTH_LSB = ((AXI_FULL_MEMORY_SLAVE == 1)?0:LOWER_BOUND_VAL);
localparam C_AXI_OS_WR = 2;
//***********************************************
// INPUT REGISTERS.
//***********************************************
generate if (C_HAS_SOFTECC_INPUT_REGS_A==0) begin : no_softecc_input_reg_stage
always @* begin
injectsbiterr_in = INJECTSBITERR;
injectdbiterr_in = INJECTDBITERR;
rsta_in = RSTA;
ena_in = ENA;
regcea_in = REGCEA;
wea_in = WEA;
addra_in = ADDRA;
dina_in = DINA;
end //end always
end //end no_softecc_input_reg_stage
endgenerate
generate if (C_HAS_SOFTECC_INPUT_REGS_A==1) begin : has_softecc_input_reg_stage
always @(posedge CLKA) begin
injectsbiterr_in <= #FLOP_DELAY INJECTSBITERR;
injectdbiterr_in <= #FLOP_DELAY INJECTDBITERR;
rsta_in <= #FLOP_DELAY RSTA;
ena_in <= #FLOP_DELAY ENA;
regcea_in <= #FLOP_DELAY REGCEA;
wea_in <= #FLOP_DELAY WEA;
addra_in <= #FLOP_DELAY ADDRA;
dina_in <= #FLOP_DELAY DINA;
end //end always
end //end input_reg_stages generate statement
endgenerate
generate if ((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 0)) begin : native_mem_module
BLK_MEM_GEN_v8_2_mem_module
#(.C_CORENAME (C_CORENAME),
.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_MEM_TYPE (C_MEM_TYPE),
.C_BYTE_SIZE (C_BYTE_SIZE),
.C_ALGORITHM (C_ALGORITHM),
.C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK),
.C_PRIM_TYPE (C_PRIM_TYPE),
.C_LOAD_INIT_FILE (C_LOAD_INIT_FILE),
.C_INIT_FILE_NAME (C_INIT_FILE_NAME),
.C_INIT_FILE (C_INIT_FILE),
.C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA),
.C_DEFAULT_DATA (C_DEFAULT_DATA),
.C_RST_TYPE ("SYNC"),
.C_HAS_RSTA (C_HAS_RSTA),
.C_RST_PRIORITY_A (C_RST_PRIORITY_A),
.C_RSTRAM_A (C_RSTRAM_A),
.C_INITA_VAL (C_INITA_VAL),
.C_HAS_ENA (C_HAS_ENA),
.C_HAS_REGCEA (C_HAS_REGCEA),
.C_USE_BYTE_WEA (C_USE_BYTE_WEA),
.C_WEA_WIDTH (C_WEA_WIDTH),
.C_WRITE_MODE_A (C_WRITE_MODE_A),
.C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),
.C_READ_WIDTH_A (C_READ_WIDTH_A),
.C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),
.C_READ_DEPTH_A (C_READ_DEPTH_A),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH),
.C_HAS_RSTB (C_HAS_RSTB),
.C_RST_PRIORITY_B (C_RST_PRIORITY_B),
.C_RSTRAM_B (C_RSTRAM_B),
.C_INITB_VAL (C_INITB_VAL),
.C_HAS_ENB (C_HAS_ENB),
.C_HAS_REGCEB (C_HAS_REGCEB),
.C_USE_BYTE_WEB (C_USE_BYTE_WEB),
.C_WEB_WIDTH (C_WEB_WIDTH),
.C_WRITE_MODE_B (C_WRITE_MODE_B),
.C_WRITE_WIDTH_B (C_WRITE_WIDTH_B),
.C_READ_WIDTH_B (C_READ_WIDTH_B),
.C_WRITE_DEPTH_B (C_WRITE_DEPTH_B),
.C_READ_DEPTH_B (C_READ_DEPTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_MEM_OUTPUT_REGS_A (C_HAS_MEM_OUTPUT_REGS_A),
.C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B),
.C_HAS_MUX_OUTPUT_REGS_A (C_HAS_MUX_OUTPUT_REGS_A),
.C_HAS_MUX_OUTPUT_REGS_B (C_HAS_MUX_OUTPUT_REGS_B),
.C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A),
.C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),
.C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.C_HAS_INJECTERR (C_HAS_INJECTERR),
.C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK),
.C_COMMON_CLK (C_COMMON_CLK),
.FLOP_DELAY (FLOP_DELAY),
.C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL),
.C_EN_ECC_PIPE (C_EN_ECC_PIPE),
.C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE))
blk_mem_gen_v8_2_inst
(.CLKA (CLKA),
.RSTA (rsta_in),
.ENA (ena_in),
.REGCEA (regcea_in),
.WEA (wea_in),
.ADDRA (addra_in),
.DINA (dina_in),
.DOUTA (DOUTA),
.CLKB (CLKB),
.RSTB (RSTB),
.ENB (ENB),
.REGCEB (REGCEB),
.WEB (WEB),
.ADDRB (ADDRB),
.DINB (DINB),
.DOUTB (DOUTB),
.INJECTSBITERR (injectsbiterr_in),
.INJECTDBITERR (injectdbiterr_in),
.ECCPIPECE (ECCPIPECE),
.SLEEP (SLEEP),
.SBITERR (SBITERR),
.DBITERR (DBITERR),
.RDADDRECC (RDADDRECC)
);
end
endgenerate
generate if((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 1)) begin : native_mem_mapped_module
localparam C_ADDRA_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_A);
localparam C_ADDRB_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_B);
localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_A/8);
localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_B/8);
// localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_A/8);
// localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_B/8);
localparam C_MEM_MAP_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_MSB;
localparam C_MEM_MAP_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_MSB;
// Data Width Number of LSB address bits to be discarded
// 1 to 16 1
// 17 to 32 2
// 33 to 64 3
// 65 to 128 4
// 129 to 256 5
// 257 to 512 6
// 513 to 1024 7
// The following two constants determine this.
localparam MEM_MAP_LOWER_BOUND_VAL_A = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8)));
localparam MEM_MAP_LOWER_BOUND_VAL_B = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8)));
localparam C_MEM_MAP_ADDRA_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_A;
localparam C_MEM_MAP_ADDRB_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_B;
wire [C_ADDRB_WIDTH_ACTUAL-1 :0] rdaddrecc_i;
wire [C_ADDRB_WIDTH-1:C_MEM_MAP_ADDRB_WIDTH_MSB] msb_zero_i;
wire [C_MEM_MAP_ADDRB_WIDTH_LSB-1:0] lsb_zero_i;
assign msb_zero_i = 0;
assign lsb_zero_i = 0;
assign RDADDRECC = {msb_zero_i,rdaddrecc_i,lsb_zero_i};
BLK_MEM_GEN_v8_2_mem_module
#(.C_CORENAME (C_CORENAME),
.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_MEM_TYPE (C_MEM_TYPE),
.C_BYTE_SIZE (C_BYTE_SIZE),
.C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK),
.C_ALGORITHM (C_ALGORITHM),
.C_PRIM_TYPE (C_PRIM_TYPE),
.C_LOAD_INIT_FILE (C_LOAD_INIT_FILE),
.C_INIT_FILE_NAME (C_INIT_FILE_NAME),
.C_INIT_FILE (C_INIT_FILE),
.C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA),
.C_DEFAULT_DATA (C_DEFAULT_DATA),
.C_RST_TYPE ("SYNC"),
.C_HAS_RSTA (C_HAS_RSTA),
.C_RST_PRIORITY_A (C_RST_PRIORITY_A),
.C_RSTRAM_A (C_RSTRAM_A),
.C_INITA_VAL (C_INITA_VAL),
.C_HAS_ENA (C_HAS_ENA),
.C_HAS_REGCEA (C_HAS_REGCEA),
.C_USE_BYTE_WEA (C_USE_BYTE_WEA),
.C_WEA_WIDTH (C_WEA_WIDTH),
.C_WRITE_MODE_A (C_WRITE_MODE_A),
.C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),
.C_READ_WIDTH_A (C_READ_WIDTH_A),
.C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),
.C_READ_DEPTH_A (C_READ_DEPTH_A),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH_ACTUAL),
.C_HAS_RSTB (C_HAS_RSTB),
.C_RST_PRIORITY_B (C_RST_PRIORITY_B),
.C_RSTRAM_B (C_RSTRAM_B),
.C_INITB_VAL (C_INITB_VAL),
.C_HAS_ENB (C_HAS_ENB),
.C_HAS_REGCEB (C_HAS_REGCEB),
.C_USE_BYTE_WEB (C_USE_BYTE_WEB),
.C_WEB_WIDTH (C_WEB_WIDTH),
.C_WRITE_MODE_B (C_WRITE_MODE_B),
.C_WRITE_WIDTH_B (C_WRITE_WIDTH_B),
.C_READ_WIDTH_B (C_READ_WIDTH_B),
.C_WRITE_DEPTH_B (C_WRITE_DEPTH_B),
.C_READ_DEPTH_B (C_READ_DEPTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH_ACTUAL),
.C_HAS_MEM_OUTPUT_REGS_A (C_HAS_MEM_OUTPUT_REGS_A),
.C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B),
.C_HAS_MUX_OUTPUT_REGS_A (C_HAS_MUX_OUTPUT_REGS_A),
.C_HAS_MUX_OUTPUT_REGS_B (C_HAS_MUX_OUTPUT_REGS_B),
.C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A),
.C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),
.C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.C_HAS_INJECTERR (C_HAS_INJECTERR),
.C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK),
.C_COMMON_CLK (C_COMMON_CLK),
.FLOP_DELAY (FLOP_DELAY),
.C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL),
.C_EN_ECC_PIPE (C_EN_ECC_PIPE),
.C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE))
blk_mem_gen_v8_2_inst
(.CLKA (CLKA),
.RSTA (rsta_in),
.ENA (ena_in),
.REGCEA (regcea_in),
.WEA (wea_in),
.ADDRA (addra_in[C_MEM_MAP_ADDRA_WIDTH_MSB-1:C_MEM_MAP_ADDRA_WIDTH_LSB]),
.DINA (dina_in),
.DOUTA (DOUTA),
.CLKB (CLKB),
.RSTB (RSTB),
.ENB (ENB),
.REGCEB (REGCEB),
.WEB (WEB),
.ADDRB (ADDRB[C_MEM_MAP_ADDRB_WIDTH_MSB-1:C_MEM_MAP_ADDRB_WIDTH_LSB]),
.DINB (DINB),
.DOUTB (DOUTB),
.INJECTSBITERR (injectsbiterr_in),
.INJECTDBITERR (injectdbiterr_in),
.ECCPIPECE (ECCPIPECE),
.SLEEP (SLEEP),
.SBITERR (SBITERR),
.DBITERR (DBITERR),
.RDADDRECC (rdaddrecc_i)
);
end
endgenerate
generate if (C_HAS_MEM_OUTPUT_REGS_B == 0 && C_HAS_MUX_OUTPUT_REGS_B == 0 ) begin : no_regs
assign S_AXI_RDATA = s_axi_rdata_c;
assign S_AXI_RLAST = s_axi_rlast_c;
assign S_AXI_RVALID = s_axi_rvalid_c;
assign S_AXI_RID = s_axi_rid_c;
assign S_AXI_RRESP = s_axi_rresp_c;
assign s_axi_rready_c = S_AXI_RREADY;
end
endgenerate
generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regceb
assign regceb_c = s_axi_rvalid_c && s_axi_rready_c;
end
endgenerate
generate if (C_HAS_MEM_OUTPUT_REGS_B == 0) begin : no_regceb
assign regceb_c = REGCEB;
end
endgenerate
generate if (C_HAS_MUX_OUTPUT_REGS_B == 1) begin : only_core_op_regs
assign s_axi_payload_c = {s_axi_rid_c,s_axi_rdata_c,s_axi_rresp_c,s_axi_rlast_c};
assign S_AXI_RID = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];
assign S_AXI_RDATA = m_axi_payload_c[C_AXI_PAYLOAD-C_AXI_ID_WIDTH-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH-C_WRITE_WIDTH_B];
assign S_AXI_RRESP = m_axi_payload_c[2:1];
assign S_AXI_RLAST = m_axi_payload_c[0];
end
endgenerate
generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : only_emb_op_regs
assign s_axi_payload_c = {s_axi_rid_c,s_axi_rresp_c,s_axi_rlast_c};
assign S_AXI_RDATA = s_axi_rdata_c;
assign S_AXI_RID = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];
assign S_AXI_RRESP = m_axi_payload_c[2:1];
assign S_AXI_RLAST = m_axi_payload_c[0];
end
endgenerate
generate if (C_HAS_MUX_OUTPUT_REGS_B == 1 || C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regs_fwd
blk_mem_axi_regs_fwd_v8_2
#(.C_DATA_WIDTH (C_AXI_PAYLOAD))
axi_regs_inst (
.ACLK (S_ACLK),
.ARESET (s_aresetn_a_c),
.S_VALID (s_axi_rvalid_c),
.S_READY (s_axi_rready_c),
.S_PAYLOAD_DATA (s_axi_payload_c),
.M_VALID (S_AXI_RVALID),
.M_READY (S_AXI_RREADY),
.M_PAYLOAD_DATA (m_axi_payload_c)
);
end
endgenerate
generate if (C_INTERFACE_TYPE == 1) begin : axi_mem_module
assign s_aresetn_a_c = !S_ARESETN;
assign S_AXI_BRESP = 2'b00;
assign s_axi_rresp_c = 2'b00;
assign s_axi_arlen_c = (C_AXI_TYPE == 1)?S_AXI_ARLEN:8'h0;
blk_mem_axi_write_wrapper_beh_v8_2
#(.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_AXI_TYPE (C_AXI_TYPE),
.C_AXI_SLAVE_TYPE (C_AXI_SLAVE_TYPE),
.C_MEMORY_TYPE (C_MEM_TYPE),
.C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),
.C_AXI_AWADDR_WIDTH ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
.C_HAS_AXI_ID (C_HAS_AXI_ID),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH),
.C_AXI_WDATA_WIDTH (C_WRITE_WIDTH_A),
.C_AXI_OS_WR (C_AXI_OS_WR))
axi_wr_fsm (
// AXI Global Signals
.S_ACLK (S_ACLK),
.S_ARESETN (s_aresetn_a_c),
// AXI Full/Lite Slave Write interface
.S_AXI_AWADDR (S_AXI_AWADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),
.S_AXI_AWLEN (S_AXI_AWLEN),
.S_AXI_AWID (S_AXI_AWID),
.S_AXI_AWSIZE (S_AXI_AWSIZE),
.S_AXI_AWBURST (S_AXI_AWBURST),
.S_AXI_AWVALID (S_AXI_AWVALID),
.S_AXI_AWREADY (S_AXI_AWREADY),
.S_AXI_WVALID (S_AXI_WVALID),
.S_AXI_WREADY (S_AXI_WREADY),
.S_AXI_BVALID (S_AXI_BVALID),
.S_AXI_BREADY (S_AXI_BREADY),
.S_AXI_BID (S_AXI_BID),
// Signals for BRAM interfac(
.S_AXI_AWADDR_OUT (s_axi_awaddr_out_c),
.S_AXI_WR_EN (s_axi_wr_en_c)
);
blk_mem_axi_read_wrapper_beh_v8_2
#(.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_AXI_TYPE (C_AXI_TYPE),
.C_AXI_SLAVE_TYPE (C_AXI_SLAVE_TYPE),
.C_MEMORY_TYPE (C_MEM_TYPE),
.C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH),
.C_AXI_PIPELINE_STAGES (1),
.C_AXI_ARADDR_WIDTH ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
.C_HAS_AXI_ID (C_HAS_AXI_ID),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH))
axi_rd_sm(
//AXI Global Signals
.S_ACLK (S_ACLK),
.S_ARESETN (s_aresetn_a_c),
//AXI Full/Lite Read Side
.S_AXI_ARADDR (S_AXI_ARADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),
.S_AXI_ARLEN (s_axi_arlen_c),
.S_AXI_ARSIZE (S_AXI_ARSIZE),
.S_AXI_ARBURST (S_AXI_ARBURST),
.S_AXI_ARVALID (S_AXI_ARVALID),
.S_AXI_ARREADY (S_AXI_ARREADY),
.S_AXI_RLAST (s_axi_rlast_c),
.S_AXI_RVALID (s_axi_rvalid_c),
.S_AXI_RREADY (s_axi_rready_c),
.S_AXI_ARID (S_AXI_ARID),
.S_AXI_RID (s_axi_rid_c),
//AXI Full/Lite Read FSM Outputs
.S_AXI_ARADDR_OUT (s_axi_araddr_out_c),
.S_AXI_RD_EN (s_axi_rd_en_c)
);
BLK_MEM_GEN_v8_2_mem_module
#(.C_CORENAME (C_CORENAME),
.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_MEM_TYPE (C_MEM_TYPE),
.C_BYTE_SIZE (C_BYTE_SIZE),
.C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK),
.C_ALGORITHM (C_ALGORITHM),
.C_PRIM_TYPE (C_PRIM_TYPE),
.C_LOAD_INIT_FILE (C_LOAD_INIT_FILE),
.C_INIT_FILE_NAME (C_INIT_FILE_NAME),
.C_INIT_FILE (C_INIT_FILE),
.C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA),
.C_DEFAULT_DATA (C_DEFAULT_DATA),
.C_RST_TYPE ("SYNC"),
.C_HAS_RSTA (C_HAS_RSTA),
.C_RST_PRIORITY_A (C_RST_PRIORITY_A),
.C_RSTRAM_A (C_RSTRAM_A),
.C_INITA_VAL (C_INITA_VAL),
.C_HAS_ENA (1),
.C_HAS_REGCEA (C_HAS_REGCEA),
.C_USE_BYTE_WEA (1),
.C_WEA_WIDTH (C_WEA_WIDTH),
.C_WRITE_MODE_A (C_WRITE_MODE_A),
.C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),
.C_READ_WIDTH_A (C_READ_WIDTH_A),
.C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),
.C_READ_DEPTH_A (C_READ_DEPTH_A),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH),
.C_HAS_RSTB (C_HAS_RSTB),
.C_RST_PRIORITY_B (C_RST_PRIORITY_B),
.C_RSTRAM_B (C_RSTRAM_B),
.C_INITB_VAL (C_INITB_VAL),
.C_HAS_ENB (1),
.C_HAS_REGCEB (C_HAS_MEM_OUTPUT_REGS_B),
.C_USE_BYTE_WEB (1),
.C_WEB_WIDTH (C_WEB_WIDTH),
.C_WRITE_MODE_B (C_WRITE_MODE_B),
.C_WRITE_WIDTH_B (C_WRITE_WIDTH_B),
.C_READ_WIDTH_B (C_READ_WIDTH_B),
.C_WRITE_DEPTH_B (C_WRITE_DEPTH_B),
.C_READ_DEPTH_B (C_READ_DEPTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_MEM_OUTPUT_REGS_A (0),
.C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B),
.C_HAS_MUX_OUTPUT_REGS_A (0),
.C_HAS_MUX_OUTPUT_REGS_B (0),
.C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A),
.C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),
.C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.C_HAS_INJECTERR (C_HAS_INJECTERR),
.C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK),
.C_COMMON_CLK (C_COMMON_CLK),
.FLOP_DELAY (FLOP_DELAY),
.C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL),
.C_EN_ECC_PIPE (0),
.C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE))
blk_mem_gen_v8_2_inst
(.CLKA (S_ACLK),
.RSTA (s_aresetn_a_c),
.ENA (s_axi_wr_en_c),
.REGCEA (regcea_in),
.WEA (S_AXI_WSTRB),
.ADDRA (s_axi_awaddr_out_c),
.DINA (S_AXI_WDATA),
.DOUTA (DOUTA),
.CLKB (S_ACLK),
.RSTB (s_aresetn_a_c),
.ENB (s_axi_rd_en_c),
.REGCEB (regceb_c),
.WEB (WEB_parameterized),
.ADDRB (s_axi_araddr_out_c),
.DINB (DINB),
.DOUTB (s_axi_rdata_c),
.INJECTSBITERR (injectsbiterr_in),
.INJECTDBITERR (injectdbiterr_in),
.SBITERR (SBITERR),
.DBITERR (DBITERR),
.ECCPIPECE (1'b0),
.SLEEP (1'b0),
.RDADDRECC (RDADDRECC)
);
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__BUF_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__BUF_PP_SYMBOL_V
/**
* buf: Buffer.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__buf (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__BUF_PP_SYMBOL_V
|
//======================================================================
//
// blockmem2r1wptr.v
// -----------------
// Synchronous block memory with two read ports and one write port.
// For port 1 the address is implicit and instead given by the
// internal pointer. But write address is explicitly given.
//
// The memory is used in the modexp core.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2015, NORDUnet A/S All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
// - Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// - Neither the name of the NORDUnet nor the names of its contributors may
// be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module blockmem2rptr1w(
input wire clk,
input wire reset_n,
input wire [07 : 0] read_addr0,
output wire [31 : 0] read_data0,
output wire [31 : 0] read_data1,
input wire rst,
input wire cs,
input wire wr,
input wire [07 : 0] write_addr,
input wire [31 : 0] write_data
);
//----------------------------------------------------------------
// Memories and regs including update variables and write enable.
//----------------------------------------------------------------
reg [31 : 0] mem [0 : 255];
reg [31 : 0] tmp_read_data0;
reg [31 : 0] tmp_read_data1;
reg [7 : 0] ptr_reg;
reg [7 : 0] ptr_new;
reg ptr_we;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign read_data0 = tmp_read_data0;
assign read_data1 = tmp_read_data1;
//----------------------------------------------------------------
// mem_update
//
// Clocked update of memory This should cause
// the memory to be implemented as a block memory.
//----------------------------------------------------------------
always @ (posedge clk)
begin : mem_update
if (wr)
mem[write_addr] <= write_data;
tmp_read_data0 <= mem[read_addr0];
tmp_read_data1 <= mem[ptr_reg];
end
//----------------------------------------------------------------
// reg_update
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin : reg_mem_update
if (!reset_n)
ptr_reg <= 8'h00;
else
if (ptr_we)
ptr_reg <= ptr_new;
end
//----------------------------------------------------------------
// ptr_logic
//----------------------------------------------------------------
always @*
begin : ptr_logic
ptr_new = 8'h00;
ptr_we = 1'b0;
if (rst)
begin
ptr_new = 8'h00;
ptr_we = 1'b1;
end
if (cs)
begin
ptr_new = ptr_reg + 1'b1;
ptr_we = 1'b1;
end
end
endmodule // blockmem2r1wptr
//======================================================================
// EOF blockmem2r1wptr.v
//======================================================================
|
module sketch(
CLOCK_50, // On Board 50 MHz
LEDG,
LEDR,
KEY, // Push Button[3:0]
SW, // DPDT Switch[17:0]
VGA_CLK, // VGA Clock
VGA_HS, // VGA H_SYNC
VGA_VS, // VGA V_SYNC
VGA_BLANK, // VGA BLANK
VGA_SYNC, // VGA SYNC
VGA_R, // VGA Red[9:0]
VGA_G, // VGA Green[9:0]
VGA_B // VGA Blue[9:0]
);
input CLOCK_50; // 50 MHz
input [3:0] KEY; // Button[3:0]
input [17:0] SW; // Switches[0:0]
output VGA_CLK; // VGA Clock
output VGA_HS; // VGA H_SYNC
output VGA_VS; // VGA V_SYNC
output VGA_BLANK; // VGA BLANK
output VGA_SYNC; // VGA SYNC
output [9:0] VGA_R; // VGA Red[9:0]
output [9:0] VGA_G; // VGA Green[9:0]
output [9:0] VGA_B; // VGA Blue[9:0]
output [6:0] LEDG;
output [17:0] LEDR;
reg [17:0] LEDR_;
assign LEDR = LEDR_;
reg [6:0] LEDG_;
assign LEDG = LEDG_;
// Create the color, x, y and writeEn wires that are inputs to the controller.
wire [2:0] colour, colourIn;
wire [7:0] x;
wire [6:0] y;
wire writeEn;
wire rEnable,lEnable, dropEnable;
wire resetn;
//assign xIn = SW[7:0];
//assign yIn = SW[14:8];
//assign colourIn = SW[17:15];
assign resetn = KEY[0];
assign rEnable = KEY[1];
assign lEnable = KEY[2];
assign dropEnable = KEY[3];
//Reg
reg writeEn_,writeEn2_;
reg [7:0]x_,x_next,x_prev=0,xIn,x_prev2=0,xIn2; //x_ is the iterated value to be drawn; xIn is the top left coordinate
reg [6:0]y_,y_next,y_prev=0,yIn, y_prev2=0,yIn2;
reg [2:0] colour_;
wire [2:0]q_sig,q_sig_grid,q_sig_Gameover,q_sig_player1,q_sig_player2,q_sig_redDiskWin;
assign writeEn = writeEn_ | writeEn2_;
assign x = x_;
assign y = y_;
assign colour = colour_;
player1 player1_inst (
.address ( count ),
.clock ( CLOCK_50 ),
.q ( q_sig_player1 )
);
player2 player2_inst (
.address ( count ),
.clock ( CLOCK_50 ),
.q ( q_sig_player2 )
);
redDiskWin redDiskWin_inst (
.address ( count ),
.clock ( CLOCK_50 ),
.q ( q_sig_redDiskWin )
);
redDiskModule redDiskModule_inst (
.address (count+1),
.clock ( CLOCK_50 ),
.q ( q_sig )
);
Grid Grid_inst (
.address ( count ),
.clock ( CLOCK_50 ),
.q ( q_sig_grid )
);
Gameover Gameover_inst (
.address ( count ),
.clock ( CLOCK_50 ),
.q ( q_sig_Gameover )
);
// Create an Instance of a VGA controller - there can be only one!
// Define the number of colours as well as the initial background
// image file (.MIF) for the controller.
vga_adapter VGA(
.resetn(resetn),
.clock(CLOCK_50),
.colour(colour),
.x(x),
.y(y),
.plot(writeEn),
// Signals for the DAC to drive the monitor.
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B),
.VGA_HS(VGA_HS),
.VGA_VS(VGA_VS),
.VGA_BLANK(VGA_BLANK),
.VGA_SYNC(VGA_SYNC),
.VGA_CLK(VGA_CLK));
defparam VGA.RESOLUTION = "160x120";
defparam VGA.MONOCHROME = "FALSE";
defparam VGA.BITS_PER_COLOUR_CHANNEL = 1;
defparam VGA.BACKGROUND_IMAGE = "Grid.mif";
// Put your code here. Your code should produce signals x,y,color and writeEn
// for the VGA controller, in addition to any other functionality your design may require.
//parameter rightLimit = 130, leftLimit = 4;
reg [3:0]Yp = Reset,Yn, Yg,Yh;
reg drawDone,resetDone,eraseDone,waitDone,DoneD, DoneS, prevState, donePlayer, doneDrawWin;
//FSM to draw next or erase
//module fsm1(input Yp,input resetDone,input waitDone,input DoneD, input ,output reg DoneS)
parameter Idle = 0, Draw = 1, Reset = 2, Erase = 3, RIGHT = 4, LEFT = 5, WAIT=6, Drop=7, ultReset=8, drawPlayer = 9;
always@(*) begin
case(Yp)
ultReset: begin
LEDR_[0] = 1;
LEDR_[1] = 1;
//DRAW GRID FROM ROM
writeEn_ = 1;
if(resetDone == 1)
Yn = Reset;
else Yn = ultReset;
end
Reset: begin
DoneS=0;
writeEn_ = 1;
//set default x and y values
Yn = drawPlayer;
end
drawPlayer: begin
if(donePlayer == 1)
Yn = Draw;
else
Yn = drawPlayer;
end
Idle: begin
writeEn_ = 0;
if(resetn && !rEnable && (xIn != 133) ) begin
Yn = RIGHT; end
else if(resetn && !dropEnable) begin
Yn = Drop; end
else if(resetn && !lEnable && (x_prev != 7)) begin
LEDR_[0] = 0;
LEDR_[1] = 1;
Yn = LEFT; end
else begin
Yn = Idle; end
end
RIGHT: begin
LEDR_[0] = 1;
LEDR_[1] = 0;
//set xIn for Right
Yn = WAIT;
end
LEFT: begin
LEDR_[0] = 0;
LEDR_[1] = 1;
//set xIn for Left
Yn = WAIT;
end
Erase: begin
writeEn_= 1;
if(eraseDone==1)
Yn = Draw;
else Yn = Erase;
end
Draw: begin
writeEn_ = 1;
if(drawDone==1) begin
//set x and y prev
Yn = Idle;
end
else Yn = Draw;
end
WAIT: begin
if(waitDone == 1)
Yn = Erase;
else
Yn = WAIT;
end
Drop: begin
DoneS=1;
if(DoneD==1) //NEEDS TO BE CHANGED TO "DoneG"
Yn=Reset;
else
Yn=Drop;
end
endcase
end //end always FSM
//reset
always@(posedge CLOCK_50 or negedge resetn) begin
if(resetn==0)
Yp <= ultReset;//ultReset;
else
Yp <= Yn;
end
///////////second fsm///////////
reg WIN = 0;
reg [2:0] xt,yt;
reg [41:0] dropped=42'b0, colorn=42'b0,addr=42'b0;
reg [6:0] Ymin1=102,Ymin2=102,Ymin3=102,Ymin4=102,Ymin5=102,Ymin6=102,Ymin7=102;
parameter IDLE2=0 ,DROP2=1, DoneDrop=2, WAIT2=3, Draw2 = 4, Erase2 = 5, Check4 = 6, Gameover = 7, assignVal = 8, Verify = 9, drawWin = 10;
always@(*) begin
case(Yg)
IDLE2: begin
LEDR_[8:5] = 4'b0000;
writeEn2_ = 0;
if(DoneS==1)
begin
DoneD=0;
Yh=DROP2;
end
else
Yh = IDLE2;
end
DROP2: begin
if(xIn == 7)
yIn2=Ymin1;
else if(xIn == 28)
yIn2=Ymin2;
else if(xIn == 49)
yIn2=Ymin3;
else if(xIn == 70)
yIn2=Ymin4;
else if(xIn == 91)
yIn2=Ymin5;
else if(xIn == 112)
yIn2=Ymin6;
else if(xIn == 133)
yIn2=Ymin7;
Yh=Erase2;
end
Erase2: begin
writeEn2_ = 1;
if(eraseDone==1)
Yh = Draw2;
else
Yh = Erase2;
end
Draw2: begin
if(drawDone==1) begin
Yh=WAIT2;
end
else
Yh = Draw2;
end
WAIT2: begin
if(waitDone == 1)
Yh = DoneDrop;
else
Yh = WAIT2;
end
DoneDrop: begin
writeEn2_ = 0;
// if(DoneG == 1 && DoneS ==0) NEEDS TO BE UNCOMMMENTED WHEN IMPLEMENTING GAME FSM
Yh=assignVal;
// else
// Yh=DoneDrop;
end
assignVal: begin
Yh=Check4;
end
Check4: begin
Yh = Verify;
end
Verify: begin
if(WIN==1) begin
DoneD = 0;
Yh=drawWin;
end
else begin
DoneD = 1;
Yh=IDLE2;
end
end
drawWin: begin
if(doneDrawWin==1)
Yh = Gameover;
else
Yh = drawWin;
end
Gameover: begin
writeEn2_ = 1;
LEDR_[8:5] = 4'b1111;
Yh=Gameover; //Stay
end
default: Yh = IDLE2;
endcase
end //end of fsm2
//Reset for fsm2
always@(posedge CLOCK_50 or negedge resetn) begin
if(resetn==0)
Yg <= IDLE2;
else
Yg <= Yh;
end
reg [25:0] count, count_next;
//Arithmetic
always@(*) begin
if(Yp == ultReset) begin
count_next = count + 1;
x_next = count - 160*y;
y_next = count/160;
end
else if(Yp == drawPlayer) begin
count_next = count + 1; // up to 1190
x_next = 151 + count%10;
y_next = count/10;
end
else if(Yp == Draw) begin
count_next = count+1;
x_next = xIn + count%15;
y_next = yIn + count/15;
end
else if(Yp == Erase) begin
count_next = count+1;
x_next = x_prev + count%15;
y_next = y_prev + count/15;
end
else if(Yg == Erase2) begin
count_next = count+1;
x_next = x_prev + count%15;
y_next = y_prev + count/15;
end
else if(Yp == WAIT) begin
count_next = count+1;
end
if(Yg == WAIT2)
begin
count_next = count+1;
end
else if(Yg == Draw2) begin
count_next = count+1;
x_next = xIn + count%15;
y_next = yIn2 + count/15;
end
else if(Yg == drawWin) begin
count_next = count+1;
x_next = xIn + count%15;
y_next = yIn2 + count/15;
end
else if(Yg == Gameover) begin
count_next = count+1;
x_next = count - 149*y;
y_next = count/149;
end
end //end always
//Datapath to control draw input
reg changePlayer=1;
always@(posedge CLOCK_50) begin
if(Yp == ultReset) begin
colour_ <= q_sig_grid;
if(count < 19200) begin
resetDone <= 0;
x_ <= x_next;
y_ <= y_next;
count <= count_next;
end
else begin
Ymin1 <= 102;
Ymin2 <= 102;
Ymin3 <= 102;
Ymin4 <= 102;
Ymin5 <= 102;
Ymin6 <= 102;
Ymin7 <= 102;
dropped <= 42'b0;
colorn <= 42'b0;
addr <= 42'b0;
//x_ <= 0;
//y_ <= 0;
resetDone <= 1;
count <=0;
end
end
else if(Yp == Reset) begin
//set default x and y values for the disk location
xIn <= 133;
yIn <= 0;
end
else if(Yp == drawPlayer) begin
if(changePlayer==1)
colour_ <=q_sig_player1;
else
colour_ <=q_sig_player2;
if(count < 1190) begin
donePlayer <= 0;
x_ <= x_next;
y_ <= y_next;
count <= count_next;
end
else begin
colour_ <= 3'b000;
donePlayer <= 1;
count <=4; //reset cnt
end
end
else if(Yp == RIGHT) begin
xIn <= x_prev + 21;
end
else if(Yp == LEFT) begin
xIn <= x_prev - 21;
end
else if((Yp == Draw)||(Yg==Draw2)) begin
if(changePlayer==1)
colour_ <=q_sig;
else begin
if(q_sig == 3'b000)
colour_ <= q_sig; //q_sig2 - if black keep it black;
else
colour_ <= q_sig-3'b011; //q_sig2 - if red make it blue;
end
if(count < 225) begin
drawDone <= 0;
x_ <= x_next;
y_ <= y_next;
count <= count_next;
end
else begin
drawDone <= 1;
x_prev <= xIn;
y_prev <= yIn;
/*x_ <= xIn;
y_ <= yIn;*/
count <=0; //reset cnt
end
end
else if((Yp == Erase)||(Yg==Erase2)) begin
colour_ <= 3'b000;
if(count < 225) begin
eraseDone <= 0;
x_ <= x_next;
y_ <= y_next;
count <= count_next;
end
else begin
eraseDone <= 1;
/*x_ <= xIn;
y_ <= yIn;*/
count <=0;
end
end
else if((Yp == WAIT)||(Yg==WAIT2))
begin
if(count < 25000000) begin
waitDone <= 0;
count <= count_next;
end
else begin
waitDone <= 1;
count <= 0;
end
end
if (Yg == DoneDrop) begin
changePlayer <= !changePlayer;
if(xIn == 7 && Ymin1!= 0) begin
Ymin1 <= Ymin1-17;
yt<=((Ymin1)/17)-1;
xt<=0;
end
else if(xIn == 28 && Ymin2!= 0) begin
Ymin2 <= Ymin2-17;
yt<=((Ymin2)/17)-1;
xt<=1;
end
else if(xIn == 49 && Ymin3!= 0) begin
Ymin3 <= Ymin3-17;
yt<=((Ymin3)/17)-1;
xt<=2;
end
else if(xIn == 70 && Ymin4!= 0)begin
Ymin4 <= Ymin4-17;
yt<=((Ymin4)/17)-1 ;
xt<=3;
end
else if(xIn == 91 && Ymin5!= 0) begin
Ymin5 <= Ymin5-17;
yt<=((Ymin5)/17)-1;
xt<=4;
end
else if(xIn == 112 && Ymin6!= 0) begin
Ymin6 <= Ymin6-17;
yt<=((Ymin6)/17)-1;
xt<=5;
end
else if(xIn == 133 && Ymin7!= 0) begin
Ymin7 <= Ymin7-17;
yt<=((Ymin7)/17)-1;
xt<=6;
end
end
else if (Yg == Check4) begin
if(yt < 3 && (dropped[addr+7] == 1 && colorn[addr+7] == changePlayer) && (dropped[addr+14] == 1 && colorn[addr+14] == changePlayer) && (dropped[addr+21] == 1 && colorn[addr+21] == changePlayer) ) //CHECK down
WIN<=1;
else if((xt < 4) && (dropped[addr+1] == 1 && colorn[addr+1] == changePlayer) && (dropped[addr+2] == 1 && colorn[addr+2] == changePlayer) && (dropped[addr+3] == 1 && colorn[addr+3] == changePlayer) ) //CHECK side to side
WIN<=1;
else if((xt < 5 && xt > 0) && (dropped[addr+1] == 1 && colorn[addr+1] == changePlayer) && (dropped[addr+2] == 1 && colorn[addr+2] == changePlayer) && (dropped[addr-1] == 1 && colorn[addr-1] == changePlayer) )
WIN<=1;
else if((xt < 6 && xt > 1) &&(dropped[addr+1] == 1 && colorn[addr+1] == changePlayer) && (dropped[addr-1] == 1 && colorn[addr-1] == changePlayer) && (dropped[addr-2] == 1 && colorn[addr-2] == changePlayer) )
WIN<=1;
// else if((xt > 2) && (dropped[addr-1] == 1 && colorn[addr-1] == changePlayer) && (dropped[addr-2] == 1 && colorn[addr-2] == changePlayer) && (dropped[addr-3] == 1 && colorn[addr-3] == changePlayer) )
// WIN<=1; //NOT WORKING FOR SOME REASON
else if((xt > 2) && (yt < 3) && (dropped[addr+6] == 1 && colorn[addr+6] == changePlayer) && (dropped[addr+12] == 1 && colorn[addr+12] == changePlayer) && (dropped[addr+18] == 1 && colorn[addr+18] == changePlayer) ) //CHECK Diagonal LD to RU
WIN<=1;
else if((xt > 1 && xt < 6) && (yt < 4 && yt > 0) && (dropped[addr+6] == 1 && colorn[addr+6] == changePlayer) && (dropped[addr+12] == 1 && colorn[addr+12] == changePlayer) && (dropped[addr-6] == 1 && colorn[addr-6] == changePlayer) )
WIN<=1;
else if((xt > 0 && xt < 5) && (yt < 5 && yt > 1) && (dropped[addr-6] == 1 && colorn[addr-6] == changePlayer) && (dropped[addr-12] == 1 && colorn[addr-12] == changePlayer) && (dropped[addr+6] == 1 && colorn[addr+6] == changePlayer) )
WIN<=1;
else if((xt < 4) && (yt > 2) && (dropped[addr-6] == 1 && colorn[addr-6] == changePlayer) && (dropped[addr-12] == 1 && colorn[addr-12] == changePlayer) && (dropped[addr-18] == 1 && colorn[addr-18] == changePlayer) )
WIN<=1;
else if((xt > 2) && (yt > 2) && (dropped[addr-8] == 1 && colorn[addr-8] == changePlayer) && (dropped[addr-16] == 1 && colorn[addr-16] == changePlayer) && (dropped[addr-24] == 1 && colorn[addr-24] == changePlayer) ) //CHECK Diagonal LU to RD
WIN<=1;
else if((xt > 1 && xt < 6) && (yt > 1 && yt < 5) && (dropped[addr-8] == 1 && colorn[addr-8] == changePlayer) && (dropped[addr-16] == 1 && colorn[addr-16] == changePlayer) && (dropped[addr+8] == 1 && colorn[addr+8] == changePlayer) )
WIN<=1;
else if((xt > 0 && xt < 5) && (yt > 0 && yt < 4) && (dropped[addr-8] == 1 && colorn[addr-8] == changePlayer) && (dropped[addr+16] == 1 && colorn[addr+16] == changePlayer) && (dropped[addr+8] == 1 && colorn[addr+8] == changePlayer) )
WIN<=1;
else if((xt < 4) && (yt < 3) && (dropped[addr+8] == 1 && colorn[addr+8] == changePlayer) && (dropped[addr+16] == 1 && colorn[addr+16] == changePlayer) && (dropped[addr+24] == 1 && colorn[addr+24] == changePlayer) )
WIN<=1;
else
WIN<=0;
end
else if(Yg == assignVal) begin
colorn[(yt*7)+xt] <= changePlayer;
dropped[(yt*7)+xt] <= 1;
addr <= (yt*7)+xt;
end
else if(Yg == drawWin) begin
if(q_sig_redDiskWin == 3'b000 || q_sig_redDiskWin == 3'b111)
colour_ <= q_sig_redDiskWin; //if black/white keep it black/white;
else if(changePlayer==0)
colour_ <= q_sig_redDiskWin;
else
colour_ <= q_sig_redDiskWin-3'b011; //if red make it blue;
if(count < 225) begin
doneDrawWin <= 0;
x_ <= x_next;
y_ <= y_next;
count <= count_next;
end
else begin
doneDrawWin <= 1;
count <=0; //unsure
end
end
else if(Yg == Gameover) begin
if(q_sig_Gameover == 3'b000)
colour_ <= q_sig_Gameover;
else if(changePlayer == 0)
colour_ <= q_sig_Gameover + 3'b101;
else
colour_ <= q_sig_Gameover + 3'b010;
if(count < 2260) begin
x_ <= x_next;
y_ <= y_next;
count <= count_next;
end
end
end //end always
endmodule |
///////////////////////////////////////////////////////////////////////////////
// vim:set shiftwidth=3 softtabstop=3 expandtab:
// $Id: udp_reg_master.v 1965 2007-07-18 01:24:21Z grg $
//
// Module: udp_reg_master.v
// Project: NetFPGA
// Description: User data path register master
//
// Note: Set TIMEOUT_RESULT to specify the return value on timeout.
// This can be used to identify broken rings.
//
// Result: ack_in -> data_in
// timeout -> TIMEOUT_RESULT
// loop complete && !ack_in -> deadbeef
//
///////////////////////////////////////////////////////////////////////////////
module udp_reg_master
#(
parameter TABLE_NUM = 1
)
(
input reg_req_in ,
input reg_rd_wr_L_in ,
input [31:0] reg_addr_in ,
input [31:0] reg_data_in ,
output reg [31:0] reg_rd_data ,
output reg reg_ack ,
input clk ,
input reset ,
output [31:0] data_output_port_lookup_o ,
/*output [31:0] data_output_port_lookup_1_o ,
output [31:0] data_output_port_lookup_2_o ,*/
output [31:0] data_meter_o ,
output [31:0] data_output_queues_o ,
output [31:0] data_config_o ,
output [31:0] addr_output_port_lookup_o ,
/*output [31:0] addr_output_port_lookup_1_o ,
output [31:0] addr_output_port_lookup_2_o ,*/
output [31:0] addr_meter_o ,
output [31:0] addr_output_queues_o ,
output [31:0] addr_config_o ,
output req_output_port_lookup_o ,
/*output req_output_port_lookup_1_o ,
output req_output_port_lookup_2_o ,*/
output req_meter_o ,
output req_output_queues_o ,
output req_config_o ,
output rw_output_port_lookup_o ,
/*output rw_output_port_lookup_1_o ,
output rw_output_port_lookup_2_o ,*/
output rw_meter_o ,
output rw_output_queues_o ,
output rw_config_o ,
input ack_output_port_lookup_i ,
/*input ack_output_port_lookup_1_i ,
input ack_output_port_lookup_2_i ,*/
input ack_meter_i ,
input ack_output_queues_i ,
input ack_config_i ,
input [31:0] data_output_port_lookup_i ,
/*input [31:0] data_output_port_lookup_1_i ,
input [31:0] data_output_port_lookup_2_i ,*/
input [31:0] data_meter_i ,
input [31:0] data_output_queues_i ,
input [31:0] data_config_i
);
assign data_output_port_lookup_o = reg_data_in ;
/*assign data_output_port_lookup_1_o = reg_data_in ;
assign data_output_port_lookup_2_o = reg_data_in ;*/
assign data_meter_o = reg_data_in ;
assign data_output_queues_o = reg_data_in ;
assign data_config_o = reg_data_in ;
assign addr_output_port_lookup_o = reg_addr_in ;
/*assign addr_output_port_lookup_1_o = reg_addr_in ;
assign addr_output_port_lookup_2_o = reg_addr_in ;*/
assign addr_meter_o = reg_addr_in;
assign addr_output_queues_o = reg_addr_in;
assign addr_config_o = reg_addr_in ;
assign req_output_port_lookup_o = (reg_addr_in[`MODULE_ID_POS+`MODULE_ID_WIDTH-1:`MODULE_ID_POS]==`OUTPUT_PORT_LOOKUP_TAG && reg_addr_in[`TABLE_ID_POS+`TABLE_ID_WIDTH-1:`TABLE_ID_POS]<=TABLE_NUM) ? reg_req_in : 0;
/*assign req_output_port_lookup_1_o = (reg_addr_in[`MODULE_ID_POS+`MODULE_ID_WIDTH-1:`MODULE_ID_POS]==`OUTPUT_PORT_LOOKUP_TAG && reg_addr_in[`TABLE_ID_POS+`TABLE_ID_WIDTH-1:`TABLE_ID_POS]==1) ? reg_req_in : 0;
assign req_output_port_lookup_2_o = (reg_addr_in[`MODULE_ID_POS+`MODULE_ID_WIDTH-1:`MODULE_ID_POS]==`OUTPUT_PORT_LOOKUP_TAG && reg_addr_in[`TABLE_ID_POS+`TABLE_ID_WIDTH-1:`TABLE_ID_POS]==2) ? reg_req_in : 0; */
assign req_meter_o = (reg_addr_in[`MODULE_ID_POS+`MODULE_ID_WIDTH-1:`MODULE_ID_POS]==`METER_TAG) ? reg_req_in : 0;
assign req_output_queues_o = (reg_addr_in[`MODULE_ID_POS+`MODULE_ID_WIDTH-1:`MODULE_ID_POS]==`QOS_TAG) ? reg_req_in : 0;
assign req_config_o = (reg_addr_in[`MODULE_ID_POS+`MODULE_ID_WIDTH-1:`MODULE_ID_POS]==`CONFIG) ? reg_req_in : 0;
assign rw_output_port_lookup_o = reg_rd_wr_L_in;
/*assign rw_output_port_lookup_1_o = reg_rd_wr_L_in;
assign rw_output_port_lookup_2_o = reg_rd_wr_L_in; */
assign rw_meter_o = reg_rd_wr_L_in;
assign rw_output_queues_o = reg_rd_wr_L_in;
assign rw_config_o = reg_rd_wr_L_in;
reg [2:0]ack_state;
always@(posedge clk)
if(reset)
ack_state<=0;
else case(ack_state)
0:if(req_output_port_lookup_o | req_meter_o | req_output_queues_o | req_config_o) ack_state<=1;//| req_output_port_lookup_1_o | req_output_port_lookup_2_o
else if(reg_req_in) ack_state<=3;
1:if(ack_output_port_lookup_i | ack_meter_i | ack_output_queues_i | ack_config_i) ack_state<=2;
2:ack_state<=0;
3:ack_state<=0;
default:ack_state<=0;
endcase
always@(posedge clk)
if(reset)
reg_ack <= 0;
else if(ack_state==2 | ack_state==3)
reg_ack<=1;
else reg_ack<=0;
always@(posedge clk)
if(reset)
reg_rd_data<=0;
else if(ack_state==1)
begin
if(ack_output_port_lookup_i) reg_rd_data <= data_output_port_lookup_i;
/*else if(ack_output_port_lookup_1_i) reg_rd_data <= data_output_port_lookup_1_i;
else if(ack_output_port_lookup_2_i) reg_rd_data <= data_output_port_lookup_2_i;*/
else if(ack_meter_i) reg_rd_data <= data_meter_i;
else if(ack_output_queues_i) reg_rd_data <= data_output_queues_i;
else if(ack_config_i) reg_rd_data <= data_config_i;
end
else if(ack_state==3) reg_rd_data<=32'hdeadbeef;
endmodule // unused_reg |
//*****************************************************************************
// (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2.3
// \ \ Application : MIG
// / / Filename : dram.v
// /___/ /\ Date Last Modified : $Date: 2011/06/02 08:35:03 $
// \ \ / \ Date Created : Wed Feb 01 2012
// \___\/\___\
//
// Device : 7 Series
// Design Name : DDR3 SDRAM
// Purpose :
// Wrapper module for the user design top level file. This module can be
// instantiated in the system and interconnect as shown in example design
// (example_top module).
// Revision History :
//*****************************************************************************
`timescale 1ps/1ps
module dram (
// Inouts
inout [63:0] ddr3_dq,
inout [7:0] ddr3_dqs_n,
inout [7:0] ddr3_dqs_p,
// Outputs
output [15:0] ddr3_addr,
output [2:0] ddr3_ba,
output ddr3_ras_n,
output ddr3_cas_n,
output ddr3_we_n,
output ddr3_reset_n,
output [0:0] ddr3_ck_p,
output [0:0] ddr3_ck_n,
output [0:0] ddr3_cke,
output [0:0] ddr3_cs_n,
output [7:0] ddr3_dm,
output [0:0] ddr3_odt,
// Inputs
// Differential system clocks
input sys_clk_p,
input sys_clk_n,
// user interface signals
input [29:0] app_addr,
input [2:0] app_cmd,
input app_en,
input [511:0] app_wdf_data,
input app_wdf_end,
input [63:0] app_wdf_mask,
input app_wdf_wren,
output [511:0] app_rd_data,
output app_rd_data_end,
output app_rd_data_valid,
output app_rdy,
output app_wdf_rdy,
input app_sr_req,
input app_ref_req,
input app_zq_req,
output app_sr_active,
output app_ref_ack,
output app_zq_ack,
output ui_clk,
output ui_clk_sync_rst,
output init_calib_complete,
input sys_rst
);
// Start of IP top instance
dram_mig u_dram_mig (
// Memory interface ports
.ddr3_addr (ddr3_addr),
.ddr3_ba (ddr3_ba),
.ddr3_cas_n (ddr3_cas_n),
.ddr3_ck_n (ddr3_ck_n),
.ddr3_ck_p (ddr3_ck_p),
.ddr3_cke (ddr3_cke),
.ddr3_ras_n (ddr3_ras_n),
.ddr3_reset_n (ddr3_reset_n),
.ddr3_we_n (ddr3_we_n),
.ddr3_dq (ddr3_dq),
.ddr3_dqs_n (ddr3_dqs_n),
.ddr3_dqs_p (ddr3_dqs_p),
.init_calib_complete (init_calib_complete),
.ddr3_cs_n (ddr3_cs_n),
.ddr3_dm (ddr3_dm),
.ddr3_odt (ddr3_odt),
// Application interface ports
.app_addr (app_addr),
.app_cmd (app_cmd),
.app_en (app_en),
.app_wdf_data (app_wdf_data),
.app_wdf_end (app_wdf_end),
.app_wdf_wren (app_wdf_wren),
.app_rd_data (app_rd_data),
.app_rd_data_end (app_rd_data_end),
.app_rd_data_valid (app_rd_data_valid),
.app_rdy (app_rdy),
.app_wdf_rdy (app_wdf_rdy),
.app_sr_req (app_sr_req),
.app_ref_req (app_ref_req),
.app_zq_req (app_zq_req),
.app_sr_active (app_sr_active),
.app_ref_ack (app_ref_ack),
.app_zq_ack (app_zq_ack),
.ui_clk (ui_clk),
.ui_clk_sync_rst (ui_clk_sync_rst),
.app_wdf_mask (app_wdf_mask),
// System Clock Ports
.sys_clk_p (sys_clk_p),
.sys_clk_n (sys_clk_n),
.sys_rst (sys_rst)
);
// End of IP top instance
endmodule
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module tmu2_fetchvertex(
input sys_clk,
input sys_rst,
input start,
output reg busy,
output [31:0] wbm_adr_o,
output [2:0] wbm_cti_o,
output wbm_cyc_o,
output reg wbm_stb_o,
input wbm_ack_i,
input [31:0] wbm_dat_i,
input [6:0] vertex_hlast,
input [6:0] vertex_vlast,
input [28:0] vertex_adr,
input signed [11:0] dst_hoffset,
input signed [11:0] dst_voffset,
input [10:0] dst_squarew,
input [10:0] dst_squareh,
output reg pipe_stb_o,
input pipe_ack_i,
/* Texture coordinates */
output reg signed [17:0] ax,
output reg signed [17:0] ay,
output reg signed [17:0] bx,
output reg signed [17:0] by,
output reg signed [17:0] cx,
output reg signed [17:0] cy,
output reg signed [17:0] dx,
output reg signed [17:0] dy,
/* Upper-left corner of the destination rectangle */
output reg signed [11:0] drx,
output reg signed [11:0] dry
);
assign wbm_cti_o = 3'd0;
assign wbm_cyc_o = wbm_stb_o;
/*
* A B
* C D
*/
/* Fetch Engine */
/* control signals */
reg [28:0] fetch_base;
reg [1:0] fetch_target;
reg fetch_strobe;
reg fetch_done;
reg shift_points;
/* */
parameter TARGET_A = 2'd0;
parameter TARGET_B = 2'd1;
parameter TARGET_C = 2'd2;
parameter TARGET_D = 2'd3;
reg is_y;
assign wbm_adr_o = {fetch_base, is_y, 2'b00};
always @(posedge sys_clk) begin
if(wbm_ack_i) begin
if(is_y) begin
case(fetch_target)
TARGET_A: ay <= wbm_dat_i[17:0];
TARGET_B: by <= wbm_dat_i[17:0];
TARGET_C: cy <= wbm_dat_i[17:0];
TARGET_D: dy <= wbm_dat_i[17:0];
endcase
end else begin
case(fetch_target)
TARGET_A: ax <= wbm_dat_i[17:0];
TARGET_B: bx <= wbm_dat_i[17:0];
TARGET_C: cx <= wbm_dat_i[17:0];
TARGET_D: dx <= wbm_dat_i[17:0];
endcase
end
end
if(shift_points) begin
/*
* A <- B
* C <- D
*/
ax <= bx;
ay <= by;
cx <= dx;
cy <= dy;
end
end
always @(posedge sys_clk) begin
if(sys_rst) begin
wbm_stb_o <= 1'b0;
fetch_done <= 1'b0;
is_y <= 1'b0;
end else begin
wbm_stb_o <= 1'b0;
fetch_done <= 1'b0;
if(fetch_strobe & ~fetch_done) begin
wbm_stb_o <= 1'b1;
if(wbm_ack_i) begin
is_y <= ~is_y;
if(is_y) begin
fetch_done <= 1'b1;
wbm_stb_o <= 1'b0;
end
end
end
end
end
/* Address & Destination coordinates generator */
/* control signals */
reg move_reset;
reg move_x_right;
reg move_x_startline;
reg move_y_down;
reg move_y_up;
/* */
reg [6:0] x;
reg [6:0] y;
always @(posedge sys_clk) begin
if(move_reset) begin
/* subtract the square dimensions,
* as we are at point D when sending the vertex down the pipeline
*/
drx = dst_hoffset - {1'b0, dst_squarew};
dry = dst_voffset - {1'b0, dst_squareh};
x = 7'd0;
y = 7'd0;
end else begin
case({move_x_right, move_x_startline})
2'b10: begin
drx = drx + {1'b0, dst_squarew};
x = x + 7'd1;
end
2'b01: begin
drx = dst_hoffset - {1'b0, dst_squarew};
x = 7'd0;
end
default:;
endcase
case({move_y_down, move_y_up})
2'b10: begin
dry = dry + {1'b0, dst_squareh};
y = y + 7'd1;
end
2'b01: begin
dry = dry - {1'b0, dst_squareh};
y = y - 7'd1;
end
default:;
endcase
end
fetch_base = vertex_adr + {y, x};
end
/* Controller */
reg [2:0] state;
reg [2:0] next_state;
parameter IDLE = 3'd0;
parameter FETCH_A = 3'd1;
parameter FETCH_B = 3'd2;
parameter FETCH_C = 3'd3;
parameter FETCH_D = 3'd4;
parameter PIPEOUT = 3'd5;
parameter NEXT_SQUARE = 3'd6;
always @(posedge sys_clk) begin
if(sys_rst)
state <= IDLE;
else
state <= next_state;
end
wire last_col = x == vertex_hlast;
wire last_row = y == vertex_vlast;
always @(*) begin
fetch_target = 2'bxx;
fetch_strobe = 1'b0;
shift_points = 1'b0;
move_reset = 1'b0;
move_x_right = 1'b0;
move_x_startline = 1'b0;
move_y_down = 1'b0;
move_y_up = 1'b0;
busy = 1'b1;
pipe_stb_o = 1'b0;
next_state = state;
case(state)
IDLE: begin
busy = 1'b0;
move_reset = 1'b1;
if(start)
next_state = FETCH_A;
end
FETCH_A: begin
fetch_target = TARGET_A;
fetch_strobe = 1'b1;
if(fetch_done) begin
move_y_down = 1'b1;
next_state = FETCH_C;
end
end
FETCH_C: begin
fetch_target = TARGET_C;
fetch_strobe = 1'b1;
if(fetch_done) begin
move_x_right = 1'b1;
move_y_up = 1'b1;
next_state = FETCH_B;
end
end
FETCH_B: begin
fetch_target = TARGET_B;
fetch_strobe = 1'b1;
if(fetch_done) begin
move_y_down = 1'b1;
next_state = FETCH_D;
end
end
FETCH_D: begin
fetch_target = TARGET_D;
fetch_strobe = 1'b1;
if(fetch_done)
next_state = PIPEOUT;
end
PIPEOUT: begin
pipe_stb_o = 1'b1;
if(pipe_ack_i)
next_state = NEXT_SQUARE;
end
NEXT_SQUARE: begin /* assumes we are on point D */
if(last_col) begin
if(last_row)
next_state = IDLE;
else begin
move_x_startline = 1'b1;
next_state = FETCH_A;
end
end else begin
move_x_right = 1'b1;
move_y_up = 1'b1;
shift_points = 1'b1;
next_state = FETCH_B;
end
end
endcase
end
endmodule
|
module acl_fp_dot_product_64(clock, resetn, enable, valid_in, valid_out,
datain_a_00,
datain_a_01,
datain_a_02,
datain_a_03,
datain_a_04,
datain_a_05,
datain_a_06,
datain_a_07,
datain_a_08,
datain_a_09,
datain_a_10,
datain_a_11,
datain_a_12,
datain_a_13,
datain_a_14,
datain_a_15,
datain_a_16,
datain_a_17,
datain_a_18,
datain_a_19,
datain_a_20,
datain_a_21,
datain_a_22,
datain_a_23,
datain_a_24,
datain_a_25,
datain_a_26,
datain_a_27,
datain_a_28,
datain_a_29,
datain_a_30,
datain_a_31,
datain_a_32,
datain_a_33,
datain_a_34,
datain_a_35,
datain_a_36,
datain_a_37,
datain_a_38,
datain_a_39,
datain_a_40,
datain_a_41,
datain_a_42,
datain_a_43,
datain_a_44,
datain_a_45,
datain_a_46,
datain_a_47,
datain_a_48,
datain_a_49,
datain_a_50,
datain_a_51,
datain_a_52,
datain_a_53,
datain_a_54,
datain_a_55,
datain_a_56,
datain_a_57,
datain_a_58,
datain_a_59,
datain_a_60,
datain_a_61,
datain_a_62,
datain_a_63,
datain_b_00,
datain_b_01,
datain_b_02,
datain_b_03,
datain_b_04,
datain_b_05,
datain_b_06,
datain_b_07,
datain_b_08,
datain_b_09,
datain_b_10,
datain_b_11,
datain_b_12,
datain_b_13,
datain_b_14,
datain_b_15,
datain_b_16,
datain_b_17,
datain_b_18,
datain_b_19,
datain_b_20,
datain_b_21,
datain_b_22,
datain_b_23,
datain_b_24,
datain_b_25,
datain_b_26,
datain_b_27,
datain_b_28,
datain_b_29,
datain_b_30,
datain_b_31,
datain_b_32,
datain_b_33,
datain_b_34,
datain_b_35,
datain_b_36,
datain_b_37,
datain_b_38,
datain_b_39,
datain_b_40,
datain_b_41,
datain_b_42,
datain_b_43,
datain_b_44,
datain_b_45,
datain_b_46,
datain_b_47,
datain_b_48,
datain_b_49,
datain_b_50,
datain_b_51,
datain_b_52,
datain_b_53,
datain_b_54,
datain_b_55,
datain_b_56,
datain_b_57,
datain_b_58,
datain_b_59,
datain_b_60,
datain_b_61,
datain_b_62,
datain_b_63,
result
);
input clock, resetn, enable, valid_in;
output valid_out;
input [31:0] datain_a_00,
datain_a_01,
datain_a_02,
datain_a_03,
datain_a_04,
datain_a_05,
datain_a_06,
datain_a_07,
datain_a_08,
datain_a_09,
datain_a_10,
datain_a_11,
datain_a_12,
datain_a_13,
datain_a_14,
datain_a_15,
datain_a_16,
datain_a_17,
datain_a_18,
datain_a_19,
datain_a_20,
datain_a_21,
datain_a_22,
datain_a_23,
datain_a_24,
datain_a_25,
datain_a_26,
datain_a_27,
datain_a_28,
datain_a_29,
datain_a_30,
datain_a_31,
datain_a_32,
datain_a_33,
datain_a_34,
datain_a_35,
datain_a_36,
datain_a_37,
datain_a_38,
datain_a_39,
datain_a_40,
datain_a_41,
datain_a_42,
datain_a_43,
datain_a_44,
datain_a_45,
datain_a_46,
datain_a_47,
datain_a_48,
datain_a_49,
datain_a_50,
datain_a_51,
datain_a_52,
datain_a_53,
datain_a_54,
datain_a_55,
datain_a_56,
datain_a_57,
datain_a_58,
datain_a_59,
datain_a_60,
datain_a_61,
datain_a_62,
datain_a_63,
datain_b_00,
datain_b_01,
datain_b_02,
datain_b_03,
datain_b_04,
datain_b_05,
datain_b_06,
datain_b_07,
datain_b_08,
datain_b_09,
datain_b_10,
datain_b_11,
datain_b_12,
datain_b_13,
datain_b_14,
datain_b_15,
datain_b_16,
datain_b_17,
datain_b_18,
datain_b_19,
datain_b_20,
datain_b_21,
datain_b_22,
datain_b_23,
datain_b_24,
datain_b_25,
datain_b_26,
datain_b_27,
datain_b_28,
datain_b_29,
datain_b_30,
datain_b_31,
datain_b_32,
datain_b_33,
datain_b_34,
datain_b_35,
datain_b_36,
datain_b_37,
datain_b_38,
datain_b_39,
datain_b_40,
datain_b_41,
datain_b_42,
datain_b_43,
datain_b_44,
datain_b_45,
datain_b_46,
datain_b_47,
datain_b_48,
datain_b_49,
datain_b_50,
datain_b_51,
datain_b_52,
datain_b_53,
datain_b_54,
datain_b_55,
datain_b_56,
datain_b_57,
datain_b_58,
datain_b_59,
datain_b_60,
datain_b_61,
datain_b_62,
datain_b_63;
output [31:0] result;
wire [31:0] inputs_a[0:63];
wire [31:0] inputs_b[0:63];
assign inputs_a[0] = datain_a_00;
assign inputs_a[1] = datain_a_01;
assign inputs_a[2] = datain_a_02;
assign inputs_a[3] = datain_a_03;
assign inputs_a[4] = datain_a_04;
assign inputs_a[5] = datain_a_05;
assign inputs_a[6] = datain_a_06;
assign inputs_a[7] = datain_a_07;
assign inputs_a[8] = datain_a_08;
assign inputs_a[9] = datain_a_09;
assign inputs_a[10] = datain_a_10;
assign inputs_a[11] = datain_a_11;
assign inputs_a[12] = datain_a_12;
assign inputs_a[13] = datain_a_13;
assign inputs_a[14] = datain_a_14;
assign inputs_a[15] = datain_a_15;
assign inputs_a[16] = datain_a_16;
assign inputs_a[17] = datain_a_17;
assign inputs_a[18] = datain_a_18;
assign inputs_a[19] = datain_a_19;
assign inputs_a[20] = datain_a_20;
assign inputs_a[21] = datain_a_21;
assign inputs_a[22] = datain_a_22;
assign inputs_a[23] = datain_a_23;
assign inputs_a[24] = datain_a_24;
assign inputs_a[25] = datain_a_25;
assign inputs_a[26] = datain_a_26;
assign inputs_a[27] = datain_a_27;
assign inputs_a[28] = datain_a_28;
assign inputs_a[29] = datain_a_29;
assign inputs_a[30] = datain_a_30;
assign inputs_a[31] = datain_a_31;
assign inputs_a[32] = datain_a_32;
assign inputs_a[33] = datain_a_33;
assign inputs_a[34] = datain_a_34;
assign inputs_a[35] = datain_a_35;
assign inputs_a[36] = datain_a_36;
assign inputs_a[37] = datain_a_37;
assign inputs_a[38] = datain_a_38;
assign inputs_a[39] = datain_a_39;
assign inputs_a[40] = datain_a_40;
assign inputs_a[41] = datain_a_41;
assign inputs_a[42] = datain_a_42;
assign inputs_a[43] = datain_a_43;
assign inputs_a[44] = datain_a_44;
assign inputs_a[45] = datain_a_45;
assign inputs_a[46] = datain_a_46;
assign inputs_a[47] = datain_a_47;
assign inputs_a[48] = datain_a_48;
assign inputs_a[49] = datain_a_49;
assign inputs_a[50] = datain_a_50;
assign inputs_a[51] = datain_a_51;
assign inputs_a[52] = datain_a_52;
assign inputs_a[53] = datain_a_53;
assign inputs_a[54] = datain_a_54;
assign inputs_a[55] = datain_a_55;
assign inputs_a[56] = datain_a_56;
assign inputs_a[57] = datain_a_57;
assign inputs_a[58] = datain_a_58;
assign inputs_a[59] = datain_a_59;
assign inputs_a[60] = datain_a_60;
assign inputs_a[61] = datain_a_61;
assign inputs_a[62] = datain_a_62;
assign inputs_a[63] = datain_a_63;
assign inputs_b[0] = datain_b_00;
assign inputs_b[1] = datain_b_01;
assign inputs_b[2] = datain_b_02;
assign inputs_b[3] = datain_b_03;
assign inputs_b[4] = datain_b_04;
assign inputs_b[5] = datain_b_05;
assign inputs_b[6] = datain_b_06;
assign inputs_b[7] = datain_b_07;
assign inputs_b[8] = datain_b_08;
assign inputs_b[9] = datain_b_09;
assign inputs_b[10] = datain_b_10;
assign inputs_b[11] = datain_b_11;
assign inputs_b[12] = datain_b_12;
assign inputs_b[13] = datain_b_13;
assign inputs_b[14] = datain_b_14;
assign inputs_b[15] = datain_b_15;
assign inputs_b[16] = datain_b_16;
assign inputs_b[17] = datain_b_17;
assign inputs_b[18] = datain_b_18;
assign inputs_b[19] = datain_b_19;
assign inputs_b[20] = datain_b_20;
assign inputs_b[21] = datain_b_21;
assign inputs_b[22] = datain_b_22;
assign inputs_b[23] = datain_b_23;
assign inputs_b[24] = datain_b_24;
assign inputs_b[25] = datain_b_25;
assign inputs_b[26] = datain_b_26;
assign inputs_b[27] = datain_b_27;
assign inputs_b[28] = datain_b_28;
assign inputs_b[29] = datain_b_29;
assign inputs_b[30] = datain_b_30;
assign inputs_b[31] = datain_b_31;
assign inputs_b[32] = datain_b_32;
assign inputs_b[33] = datain_b_33;
assign inputs_b[34] = datain_b_34;
assign inputs_b[35] = datain_b_35;
assign inputs_b[36] = datain_b_36;
assign inputs_b[37] = datain_b_37;
assign inputs_b[38] = datain_b_38;
assign inputs_b[39] = datain_b_39;
assign inputs_b[40] = datain_b_40;
assign inputs_b[41] = datain_b_41;
assign inputs_b[42] = datain_b_42;
assign inputs_b[43] = datain_b_43;
assign inputs_b[44] = datain_b_44;
assign inputs_b[45] = datain_b_45;
assign inputs_b[46] = datain_b_46;
assign inputs_b[47] = datain_b_47;
assign inputs_b[48] = datain_b_48;
assign inputs_b[49] = datain_b_49;
assign inputs_b[50] = datain_b_50;
assign inputs_b[51] = datain_b_51;
assign inputs_b[52] = datain_b_52;
assign inputs_b[53] = datain_b_53;
assign inputs_b[54] = datain_b_54;
assign inputs_b[55] = datain_b_55;
assign inputs_b[56] = datain_b_56;
assign inputs_b[57] = datain_b_57;
assign inputs_b[58] = datain_b_58;
assign inputs_b[59] = datain_b_59;
assign inputs_b[60] = datain_b_60;
assign inputs_b[61] = datain_b_61;
assign inputs_b[62] = datain_b_62;
assign inputs_b[63] = datain_b_63;
wire [36:0] mult_result [0:63];
wire [63:0] mult_valid_out;
wire [63:0] mult_stall_out;
wire [37:0] add_result_1 [0:31];
wire [31:0] add_valid_out_1;
wire [31:0] add_stall_out_1;
wire [37:0] add_result_2 [0:15];
wire [15:0] add_valid_out_2;
wire [15:0] add_stall_out_2;
wire [37:0] add_result_3 [0:7];
wire [7:0] add_valid_out_3;
wire [7:0] add_stall_out_3;
wire [37:0] add_result_4 [0:3];
wire [3:0] add_valid_out_4;
wire [3:0] add_stall_out_4;
wire [37:0] add_result_5 [0:1];
wire [1:0] add_valid_out_5;
wire [1:0] add_stall_out_5;
wire [37:0] add_result_6;
wire add_valid_out_6;
wire [0:0] add_stall_out_6;
// stage 0
genvar i;
generate
for(i=0; i < 64; i = i + 1)
begin: mult_stage
acl_fp_custom_mul_wrapper m0(
.clock(clock),
.resetn(resetn),
.dataa(inputs_a[i]),
.datab(inputs_b[i]),
.result(mult_result[i]),
.valid_in((i==0) ? valid_in : 1'b0),
.valid_out(mult_valid_out[i]),
.enable(enable));
end
endgenerate
// stage 1
generate
for(i=0; i < 32; i = i + 1)
begin: add_stage_1
acl_fp_custom_add_wrapper a1(
.clock(clock),
.resetn(resetn),
.dataa(mult_result[2*i]),
.datab(mult_result[2*i+1]),
.result(add_result_1[i]),
.valid_in((i==0) ? mult_valid_out[2*i] : 1'b0),
.valid_out(add_valid_out_1[i]),
.enable(enable));
end
endgenerate
// stage 2
generate
for(i=0; i < 16; i = i + 1)
begin: add_stage_2
acl_fp_custom_dynamic_align a2(
.clock(clock),
.resetn(resetn),
.dataa(add_result_1[2*i]),
.datab(add_result_1[2*i+1]),
.result(add_result_2[i]),
.valid_in((i==0) ? add_valid_out_1[2*i] : 1'b0),
.valid_out(add_valid_out_2[i]),
.enable(enable));
end
endgenerate
// stage 3
generate
for(i=0; i < 8; i = i + 1)
begin: add_stage_3
acl_fp_custom_dynamic_align a3(
.clock(clock),
.resetn(resetn),
.dataa(add_result_2[2*i]),
.datab(add_result_2[2*i+1]),
.result(add_result_3[i]),
.valid_in((i==0) ? add_valid_out_2[2*i] :1'b0),
.valid_out(add_valid_out_3[i]),
.enable(enable));
end
endgenerate
// stage 4
generate
for(i=0; i < 4; i = i + 1)
begin: add_stage_4
acl_fp_custom_dynamic_align a4(
.clock(clock),
.resetn(resetn),
.dataa(add_result_3[2*i]),
.datab(add_result_3[2*i+1]),
.result(add_result_4[i]),
.valid_in((i==0) ? add_valid_out_3[2*i] : 1'b0),
.valid_out(add_valid_out_4[i]),
.enable(enable));
end
endgenerate
// stage 5
generate
for(i=0; i < 2; i = i + 1)
begin: add_stage_5
acl_fp_custom_dynamic_align a5(
.clock(clock),
.resetn(resetn),
.dataa(add_result_4[2*i]),
.datab(add_result_4[2*i+1]),
.result(add_result_5[i]),
.valid_in((i==0) ? add_valid_out_4[2*i] : 1'b0),
.valid_out(add_valid_out_5[i]),
.enable(enable));
end
endgenerate
wire add_conv_stall_out;
acl_fp_custom_dynamic_align a6(
.clock(clock),
.resetn(resetn),
.dataa(add_result_5[0]),
.datab(add_result_5[1]),
.result(add_result_6),
.valid_in(add_valid_out_5[0]),
.valid_out(add_valid_out_6),
.enable(enable));
wire [26:0] norm_man;
wire [8:0] norm_exp;
wire norm_sign;
wire norm_valid;
acl_fp_custom_reduced_normalize norm(
.clock(clock),
.resetn(resetn),
.mantissa(add_result_6[27:0]), .exponent(add_result_6[36:28]), .sign(add_result_6[37]),
.valid_in(add_valid_out_6), .valid_out(norm_valid),
.enable(enable),
.mantissa_out(norm_man), .exponent_out(norm_exp), .sign_out(norm_sign));
defparam norm.HIGH_CAPACITY = 0;
defparam norm.FLUSH_DENORMS = 0;
defparam norm.HIGH_LATENCY = 1;
defparam norm.REMOVE_STICKY = 1;
defparam norm.FINITE_MATH_ONLY = 1;
acl_fp_convert_to_ieee cie(
.clock(clock),
.resetn(resetn),
.mantissa(norm_man),
.exponent(norm_exp),
.sign(norm_sign),
.result(result),
.valid_in(norm_valid),
.valid_out(valid_out),
.enable(enable));
defparam cie.FINITE_MATH_ONLY = 1;
endmodule
|
// Double pumped single precision floating point multiply
// Latency = 6 kernel clocks
// // (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// !!! WARNING !!!
// This core no longer works because the core is no longer fully high-capacity
// (and has a single staging register, which messes up things in the 2x clock
// domain). See acl_fp_custom_mul_hc.v and acl_fp_custom_mul_hc_core.v for
// details.
// !!! WARNING !!!
module acl_fp_custom_mul_hc_dbl_pumped
#( parameter WIDTH = 32 )
(
input logic clock,
input logic clock2x,
input logic resetn,
input logic valid_in,
input logic stall_in,
output logic valid_out,
output logic stall_out,
input logic [WIDTH-1:0] a1,
input logic [WIDTH-1:0] b1,
input logic [WIDTH-1:0] a2,
input logic [WIDTH-1:0] b2,
output logic [WIDTH-1:0] y1,
output logic [WIDTH-1:0] y2
);
localparam LATENCY = 6; // in "clock" cycles
// Prevent sharing of these registers across different instances
// (and even kernels!). The sharing may cause very long paths
// across the chip, which limits fmax of clock2x.
logic sel2x /* synthesis preserve */;
// This is for simulation purposes. Matches physical behavior where
// registers power up to zero.
initial
begin
sel2x = 1'b0;
end
always@(posedge clock2x)
sel2x <= ~sel2x; // either the same as clock or ~clock
// The block is high-capacity. Here are all of the
// valid_in/out, stall_in/out signals for all "clock" cycles.
//
// Index 1 corresponds to the first cycle.
typedef struct packed {
logic valid_in, valid_out;
logic stall_in, stall_out;
} stage_flow_control;
stage_flow_control s [1:LATENCY];
genvar i;
generate
for( i = 1; i <= LATENCY; i = i + 1 )
begin:stage
// valid_in
if( i == 1 )
assign s[i].valid_in = valid_in;
else
assign s[i].valid_in = s[i-1].valid_out;
// valid_out
always @(posedge clock or negedge resetn)
if( ~resetn )
s[i].valid_out <= 1'b0;
else if( ~s[i].stall_out )
s[i].valid_out <= s[i].valid_in;
// stall_in
if( i == LATENCY )
assign s[i].stall_in = stall_in;
else
assign s[i].stall_in = s[i+1].stall_out;
// stall_out
assign s[i].stall_out = s[i].valid_out & s[i].stall_in;
end
endgenerate
assign valid_out = s[LATENCY].valid_out;
assign stall_out = s[1].stall_out;
// Register before double pumping
logic [WIDTH-1:0] a1_reg;
logic [WIDTH-1:0] b1_reg;
logic [WIDTH-1:0] a2_reg;
logic [WIDTH-1:0] b2_reg;
always @(posedge clock)
if( ~s[1].stall_out )
begin
a1_reg <= a1;
a2_reg <= a2;
b1_reg <= b1;
b2_reg <= b2;
end
// Clock domain transfer
logic [WIDTH-1:0] a1_reg_2x;
logic [WIDTH-1:0] a2_reg_2x;
logic [WIDTH-1:0] b1_reg_2x;
logic [WIDTH-1:0] b2_reg_2x;
logic valid_out_2x;
always @(posedge clock2x)
if( ~s[2].stall_out )
begin
a1_reg_2x <= a1_reg;
a2_reg_2x <= a2_reg;
b1_reg_2x <= b1_reg;
b2_reg_2x <= b2_reg;
valid_out_2x <= s[1].valid_out;
end
// The multipler. Takes six "clock2x" cycles to complete
// (so takes 3 "clock" cycles to complete).
logic [WIDTH-1:0] fp_mul_inp_a;
logic [WIDTH-1:0] fp_mul_inp_b;
logic [WIDTH-1:0] fp_mul_res;
logic fp_mul_valid_out, fp_mul_stall_out;
assign fp_mul_inp_a = (sel2x) ? a2_reg_2x : a1_reg_2x;
assign fp_mul_inp_b = (sel2x) ? b2_reg_2x : b1_reg_2x;
acl_fp_custom_mul_hc the_mul(
.resetn(resetn),
.clock(clock2x),
.valid_in(valid_out_2x),
.stall_in(s[5].stall_out),
.valid_out(fp_mul_valid_out),
.stall_out(fp_mul_stall_out),
.dataa(fp_mul_inp_a),
.datab(fp_mul_inp_b),
.result(fp_mul_res));
// Track which set of inputs was selected in parallel with the
// multipler's pipeline. Track in the "clock2x" domain.
//
// There are six stages in this pipeline to correspond with the
// six stages in acl_fp_custom_mul_hc's pipeline.
logic sel_21, sel_22, sel_31, sel_32, sel_41, sel_42;
always @(posedge clock2x)
begin
if( ~s[2].stall_out ) // clock -> clock2x
begin
sel_21 <= sel2x;
sel_22 <= sel_21;
end
if( ~s[3].stall_out ) // clock -> clock2x
begin
sel_31 <= sel_22;
sel_32 <= sel_31;
end
if( ~s[4].stall_out ) // clock -> clock2x
begin
sel_41 <= sel_32;
sel_42 <= sel_41;
end
end
// Additional clock2x pipeline register to even things out
// and separate the results from the two inputs in preparation
// for the clock transfer back to the "clock" domain.
logic [31:0] res1_5, res2_5;
always @(posedge clock2x)
if( ~s[5].stall_out ) // clock -> clock2x
begin
if( sel_42 )
begin
// This is the result from the 2nd set of inputs.
res2_5 <= fp_mul_res;
end
else
begin
// This is the result from the 1st set of inputs.
res1_5 <= fp_mul_res;
end
end
// Output registers. Cross-clock path from clock2x -> clock.
always @(posedge clock)
begin
if( ~s[6].stall_out )
begin
y1 <= res1_5;
y2 <= res2_5;
end
end
endmodule
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module hps_sdram_p0_altdqdqs (
core_clock_in,
reset_n_core_clock_in,
fr_clock_in,
hr_clock_in,
write_strobe_clock_in,
write_strobe,
strobe_ena_hr_clock_in,
capture_strobe_tracking,
read_write_data_io,
write_oe_in,
strobe_io,
output_strobe_ena,
strobe_n_io,
oct_ena_in,
read_data_out,
capture_strobe_out,
write_data_in,
extra_write_data_in,
extra_write_data_out,
parallelterminationcontrol_in,
seriesterminationcontrol_in,
config_data_in,
config_update,
config_dqs_ena,
config_io_ena,
config_extra_io_ena,
config_dqs_io_ena,
config_clock_in,
lfifo_rdata_en,
lfifo_rdata_en_full,
lfifo_rd_latency,
lfifo_reset_n,
lfifo_rdata_valid,
vfifo_qvld,
vfifo_inc_wr_ptr,
vfifo_reset_n,
rfifo_reset_n,
dll_delayctrl_in
);
input [7-1:0] dll_delayctrl_in;
input core_clock_in;
input reset_n_core_clock_in;
input fr_clock_in;
input hr_clock_in;
input write_strobe_clock_in;
input [3:0] write_strobe;
input strobe_ena_hr_clock_in;
output capture_strobe_tracking;
inout [8-1:0] read_write_data_io;
input [2*8-1:0] write_oe_in;
inout strobe_io;
input [2-1:0] output_strobe_ena;
inout strobe_n_io;
input [2-1:0] oct_ena_in;
output [2 * 2 * 8-1:0] read_data_out;
output capture_strobe_out;
input [2 * 2 * 8-1:0] write_data_in;
input [2 * 2 * 1-1:0] extra_write_data_in;
output [1-1:0] extra_write_data_out;
input [16-1:0] parallelterminationcontrol_in;
input [16-1:0] seriesterminationcontrol_in;
input config_data_in;
input config_update;
input config_dqs_ena;
input [8-1:0] config_io_ena;
input [1-1:0] config_extra_io_ena;
input config_dqs_io_ena;
input config_clock_in;
input [2-1:0] lfifo_rdata_en;
input [2-1:0] lfifo_rdata_en_full;
input [4:0] lfifo_rd_latency;
input lfifo_reset_n;
output lfifo_rdata_valid;
input [2-1:0] vfifo_qvld;
input [2-1:0] vfifo_inc_wr_ptr;
input vfifo_reset_n;
input rfifo_reset_n;
parameter ALTERA_ALTDQ_DQS2_FAST_SIM_MODEL = "";
altdq_dqs2_acv_connect_to_hard_phy_cyclonev altdq_dqs2_inst (
.core_clock_in( core_clock_in),
.reset_n_core_clock_in (reset_n_core_clock_in),
.fr_clock_in( fr_clock_in),
.hr_clock_in( hr_clock_in),
.write_strobe_clock_in (write_strobe_clock_in),
.write_strobe(write_strobe),
.strobe_ena_hr_clock_in( strobe_ena_hr_clock_in),
.capture_strobe_tracking (capture_strobe_tracking),
.read_write_data_io( read_write_data_io),
.write_oe_in( write_oe_in),
.strobe_io( strobe_io),
.output_strobe_ena( output_strobe_ena),
.strobe_n_io( strobe_n_io),
.oct_ena_in( oct_ena_in),
.read_data_out( read_data_out),
.capture_strobe_out( capture_strobe_out),
.write_data_in( write_data_in),
.extra_write_data_in( extra_write_data_in),
.extra_write_data_out( extra_write_data_out),
.parallelterminationcontrol_in( parallelterminationcontrol_in),
.seriesterminationcontrol_in( seriesterminationcontrol_in),
.config_data_in( config_data_in),
.config_update( config_update),
.config_dqs_ena( config_dqs_ena),
.config_io_ena( config_io_ena),
.config_extra_io_ena( config_extra_io_ena),
.config_dqs_io_ena( config_dqs_io_ena),
.config_clock_in( config_clock_in),
.lfifo_rdata_en(lfifo_rdata_en),
.lfifo_rdata_en_full(lfifo_rdata_en_full),
.lfifo_rd_latency(lfifo_rd_latency),
.lfifo_reset_n(lfifo_reset_n),
.lfifo_rdata_valid(lfifo_rdata_valid),
.vfifo_qvld(vfifo_qvld),
.vfifo_inc_wr_ptr(vfifo_inc_wr_ptr),
.vfifo_reset_n(vfifo_reset_n),
.rfifo_reset_n(rfifo_reset_n),
.dll_delayctrl_in(dll_delayctrl_in)
);
defparam altdq_dqs2_inst.PIN_WIDTH = 8;
defparam altdq_dqs2_inst.PIN_TYPE = "bidir";
defparam altdq_dqs2_inst.USE_INPUT_PHASE_ALIGNMENT = "false";
defparam altdq_dqs2_inst.USE_OUTPUT_PHASE_ALIGNMENT = "false";
defparam altdq_dqs2_inst.USE_LDC_AS_LOW_SKEW_CLOCK = "false";
defparam altdq_dqs2_inst.USE_HALF_RATE_INPUT = "false";
defparam altdq_dqs2_inst.USE_HALF_RATE_OUTPUT = "true";
defparam altdq_dqs2_inst.DIFFERENTIAL_CAPTURE_STROBE = "true";
defparam altdq_dqs2_inst.SEPARATE_CAPTURE_STROBE = "false";
defparam altdq_dqs2_inst.INPUT_FREQ = 400.0;
defparam altdq_dqs2_inst.INPUT_FREQ_PS = "2500 ps";
defparam altdq_dqs2_inst.DELAY_CHAIN_BUFFER_MODE = "high";
defparam altdq_dqs2_inst.DQS_PHASE_SETTING = 0;
defparam altdq_dqs2_inst.DQS_PHASE_SHIFT = 0;
defparam altdq_dqs2_inst.DQS_ENABLE_PHASE_SETTING = 3;
defparam altdq_dqs2_inst.USE_DYNAMIC_CONFIG = "true";
defparam altdq_dqs2_inst.INVERT_CAPTURE_STROBE = "true";
defparam altdq_dqs2_inst.SWAP_CAPTURE_STROBE_POLARITY = "false";
defparam altdq_dqs2_inst.USE_TERMINATION_CONTROL = "true";
defparam altdq_dqs2_inst.USE_DQS_ENABLE = "true";
defparam altdq_dqs2_inst.USE_OUTPUT_STROBE = "true";
defparam altdq_dqs2_inst.USE_OUTPUT_STROBE_RESET = "false";
defparam altdq_dqs2_inst.DIFFERENTIAL_OUTPUT_STROBE = "true";
defparam altdq_dqs2_inst.USE_BIDIR_STROBE = "true";
defparam altdq_dqs2_inst.REVERSE_READ_WORDS = "false";
defparam altdq_dqs2_inst.EXTRA_OUTPUT_WIDTH = 1;
defparam altdq_dqs2_inst.DYNAMIC_MODE = "dynamic";
defparam altdq_dqs2_inst.OCT_SERIES_TERM_CONTROL_WIDTH = 16;
defparam altdq_dqs2_inst.OCT_PARALLEL_TERM_CONTROL_WIDTH = 16;
defparam altdq_dqs2_inst.DLL_WIDTH = 7;
defparam altdq_dqs2_inst.USE_DATA_OE_FOR_OCT = "false";
defparam altdq_dqs2_inst.DQS_ENABLE_WIDTH = 1;
defparam altdq_dqs2_inst.USE_OCT_ENA_IN_FOR_OCT = "true";
defparam altdq_dqs2_inst.PREAMBLE_TYPE = "high";
defparam altdq_dqs2_inst.EMIF_UNALIGNED_PREAMBLE_SUPPORT = "false";
defparam altdq_dqs2_inst.EMIF_BYPASS_OCT_DDIO = "false";
defparam altdq_dqs2_inst.USE_OFFSET_CTRL = "false";
defparam altdq_dqs2_inst.HR_DDIO_OUT_HAS_THREE_REGS = "false";
defparam altdq_dqs2_inst.DQS_ENABLE_PHASECTRL = "true";
defparam altdq_dqs2_inst.USE_2X_FF = "false";
defparam altdq_dqs2_inst.DLL_USE_2X_CLK = "false";
defparam altdq_dqs2_inst.USE_DQS_TRACKING = "true";
defparam altdq_dqs2_inst.USE_HARD_FIFOS = "true";
defparam altdq_dqs2_inst.USE_DQSIN_FOR_VFIFO_READ = "false";
defparam altdq_dqs2_inst.CALIBRATION_SUPPORT = "false";
defparam altdq_dqs2_inst.NATURAL_ALIGNMENT = "true";
defparam altdq_dqs2_inst.SEPERATE_LDC_FOR_WRITE_STROBE = "false";
defparam altdq_dqs2_inst.HHP_HPS = "true";
endmodule
|
/***********************************************************************************************************************
* Copyright (C) 2016 Andrew Zonenberg and contributors *
* *
* This program is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser General *
* Public License as published by the Free Software Foundation; either version 2.1 of the License, or (at your option) *
* any later version. *
* *
* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied *
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for *
* more details. *
* *
* You should have received a copy of the GNU Lesser General Public License along with this program; if not, you may *
* find one here: *
* https://www.gnu.org/licenses/old-licenses/lgpl-2.1.txt *
* or you may search the http://www.gnu.org website for the version 2.1 license, or you may write to the Free Software *
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA *
**********************************************************************************************************************/
`default_nettype none
/**
OUTPUTS:
Pin 8: Power-on reset flag
Pin 9: Always high
Pin 10: Power-on reset flag
TEST PROCEDURE:
Verify pins 8, 9, and 10 all go high after the device is programmed.
TODO: is there a good way to characterize timing?
*/
module POR(rst_out1, one, rst_out2);
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// I/O declarations
(* LOC = "P8" *)
output wire rst_out1;
(* LOC = "P9" *)
output wire one;
(* LOC = "P10" *)
output wire rst_out2;
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Reset logic
//Power-on reset
wire por_done;
GP_POR #(
.POR_TIME(500)
) por (
.RST_DONE(por_done)
);
assign one = 1'b1;
assign rst_out1 = por_done;
assign rst_out2 = por_done;
endmodule
|
//--------------------------------------------------------------------------------
// Project : SWITCH
// File : tx_client_fifo_8.v
// Version : 0.2
// Author : Shreejith S
//
// Description: 8-bit Transmitter FIFO with AxiStream interfaces - XILINX
//
//--------------------------------------------------------------------------------
//
// (c) Copyright 2004-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//------------------------------------------------------------------------------
// Description: This is a transmitter side FIFO for the design example
// of the core. AxiStream interfaces are used.
//
// The FIFO is created from 2 Block RAMs of size 2048
// words of 8-bits per word, giving a total frame memory capacity
// of 4096 bytes.
//
// Valid frame data received from the user interface is written
// into the Block RAM on the tx_fifo_aclkk. The FIFO will store
// frames up to 4kbytes in length. If larger frames are written
// to the FIFO, the AxiStream interface will accept the rest of the
// frame, but that frame will be dropped by the FIFO and the
// overflow signal will be asserted.
//
// The FIFO is designed to work with a minimum frame length of 14
// bytes.
//
// When there is at least one complete frame in the FIFO, the MAC
// transmitter AxiStream interface will be driven to request frame
// transmission by placing the first byte of the frame onto
// tx_axis_mac_tdata and by asserting tx_axis_mac_tvalid. The MAC will later
// respond by asserting tx_axis_mac_tready. At this point the remaining
// frame data is read out of the FIFO subject to tx_axis_mac_tready.
// Data is read out of the FIFO on the tx_mac_aclk.
//
// If the generic FULL_DUPLEX_ONLY is set to false, the FIFO will
// requeue and retransmit frames as requested by the MAC. Once a
// frame has been transmitted by the FIFO it is stored until the
// possible retransmit window for that frame has expired.
//
// The FIFO has been designed to operate with different clocks
// on the write and read sides. The write clock (user-side
// AxiStream clock) can be an equal or faster frequency than the
// read clock (MAC-side AxiStream clock). The minimum write clock
// frequency is the read clock frequency divided by 2.
//
// The FIFO memory size can be increased by expanding the rd_addr
// and wr_addr signal widths, to address further BRAMs.
//
//------------------------------------------------------------------------------
`timescale 1ps / 1ps
//------------------------------------------------------------------------------
// The module declaration for the Transmitter FIFO
//------------------------------------------------------------------------------
module tx_client_fifo_8 #
(
parameter FULL_DUPLEX_ONLY = 0
)
(
// User-side (write-side) AxiStream interface
input tx_fifo_aclk,
input tx_fifo_resetn,
input [7:0] tx_axis_fifo_tdata,
input tx_axis_fifo_tvalid,
input tx_axis_fifo_tlast,
output tx_axis_fifo_tready,
// MAC-side (read-side) AxiStream interface
input tx_mac_aclk,
input tx_mac_resetn,
output [7:0] tx_axis_mac_tdata,
output reg tx_axis_mac_tvalid,
output reg tx_axis_mac_tlast,
input tx_axis_mac_tready,
output reg tx_axis_mac_tuser,
// FIFO status and overflow indication,
// synchronous to write-side (tx_user_aclk) interface
output fifo_overflow,
output [3:0] fifo_status,
// FIFO collision and retransmission requests from MAC
input tx_collision,
input tx_retransmit
);
//----------------------------------------------------------------------------
// Define internal signals
//----------------------------------------------------------------------------
wire GND;
wire VCC;
wire [8:0] GND_BUS;
// Binary encoded read state machine states.
parameter IDLE_s = 4'b0000;
parameter QUEUE1_s = 4'b0001;
parameter QUEUE2_s = 4'b0010;
parameter QUEUE3_s = 4'b0011;
parameter QUEUE_ACK_s = 4'b0100;
parameter WAIT_ACK_s = 4'b0101;
parameter FRAME_s = 4'b0110;
parameter HANDSHAKE_s = 4'b0111;
parameter FINISH_s = 4'b1000;
parameter DROP_ERROR_s = 4'b1001;
parameter DROP_s = 4'b1010;
parameter RETRANSMIT_ERROR_s = 4'b1011;
parameter RETRANSMIT_s = 4'b1100;
reg [3:0] rd_state;
reg [3:0] rd_nxt_state;
// Binary encoded write state machine states.
parameter WAIT_s = 2'b00;
parameter DATA_s = 2'b01;
parameter EOF_s = 2'b10;
parameter OVFLOW_s = 2'b11;
reg [1:0] wr_state;
reg [1:0] wr_nxt_state;
wire [8:0] wr_eof_data_bram;
reg [7:0] wr_data_bram;
reg [7:0] wr_data_pipe[0:1];
reg wr_sof_pipe[0:1];
reg wr_eof_pipe[0:1];
reg wr_accept_pipe[0:1];
reg wr_accept_bram;
wire wr_sof_int;
reg [0:0] wr_eof_bram;
reg wr_eof_reg;
reg [11:0] wr_addr;
wire wr_addr_inc;
wire wr_start_addr_load;
wire wr_addr_reload;
reg [11:0] wr_start_addr;
reg wr_fifo_full;
wire wr_en;
wire wr_en_u;
wire [0:0] wr_en_u_bram;
wire wr_en_l;
wire [0:0] wr_en_l_bram;
reg wr_ovflow_dst_rdy;
wire tx_axis_fifo_tready_int_n;
wire frame_in_fifo;
reg rd_eof;
reg rd_eof_reg;
reg rd_eof_pipe;
reg [11:0] rd_addr;
wire rd_addr_inc;
wire rd_addr_reload;
wire [8:0] rd_bram_u_unused;
wire [8:0] rd_bram_l_unused;
wire [8:0] rd_eof_data_bram_u;
wire [8:0] rd_eof_data_bram_l;
wire [7:0] rd_data_bram_u;
wire [7:0] rd_data_bram_l;
reg [7:0] rd_data_pipe_u;
reg [7:0] rd_data_pipe_l;
reg [7:0] rd_data_pipe;
wire [0:0] rd_eof_bram_u;
wire [0:0] rd_eof_bram_l;
wire rd_en;
reg rd_bram_u;
reg rd_bram_u_reg;
(* INIT = "0" *)
reg rd_tran_frame_tog = 1'b0;
wire wr_tran_frame_sync;
(* INIT = "0" *)
reg wr_tran_frame_delay = 1'b0;
(* INIT = "0" *)
reg rd_retran_frame_tog = 1'b0;
wire wr_retran_frame_sync;
(* INIT = "0" *)
reg wr_retran_frame_delay = 1'b0;
wire wr_store_frame;
reg wr_transmit_frame;
reg wr_retransmit_frame;
reg [8:0] wr_frames;
reg wr_frame_in_fifo;
reg [3:0] rd_16_count;
wire rd_txfer_en;
reg [11:0] rd_addr_txfer;
(* INIT = "0" *)
reg rd_txfer_tog = 1'b0;
wire wr_txfer_tog_sync;
(* INIT = "0" *)
reg wr_txfer_tog_delay = 1'b0;
wire wr_txfer_en;
(* ASYNC_REG = "TRUE" *)
reg [11:0] wr_rd_addr;
reg [11:0] wr_addr_diff;
reg [3:0] wr_fifo_status;
reg rd_drop_frame;
reg rd_retransmit;
reg [11:0] rd_start_addr;
wire rd_start_addr_load;
wire rd_start_addr_reload;
reg [11:0] rd_dec_addr;
wire rd_transmit_frame;
wire rd_retransmit_frame;
reg rd_col_window_expire;
reg rd_col_window_pipe[0:1];
(* ASYNC_REG = "TRUE" *)
reg wr_col_window_pipe[0:1];
wire wr_eof_state;
reg wr_eof_state_reg;
wire wr_fifo_overflow;
reg [9:0] rd_slot_timer;
reg wr_col_window_expire;
wire rd_idle_state;
wire [7:0] tx_axis_mac_tdata_int_frame;
wire [7:0] tx_axis_mac_tdata_int_handshake;
reg [7:0] tx_axis_mac_tdata_int;
wire tx_axis_mac_tvalid_int_finish;
wire tx_axis_mac_tvalid_int_droperror;
wire tx_axis_mac_tvalid_int_retransmiterror;
wire tx_axis_mac_tlast_int_frame_handshake;
wire tx_axis_mac_tlast_int_finish;
wire tx_axis_mac_tlast_int_droperror;
wire tx_axis_mac_tlast_int_retransmiterror;
wire tx_axis_mac_tuser_int_droperror;
wire tx_axis_mac_tuser_int_retransmit;
wire tx_fifo_reset;
wire tx_mac_reset;
// invert reset sense as architecture is optimized for active high resets
assign tx_fifo_reset = !tx_fifo_resetn;
assign tx_mac_reset = !tx_mac_resetn;
//----------------------------------------------------------------------------
// Begin FIFO architecture
//----------------------------------------------------------------------------
assign GND = 1'b0;
assign VCC = 1'b1;
assign GND_BUS = 9'b0;
//----------------------------------------------------------------------------
// Write state machine and control
//----------------------------------------------------------------------------
// Write state machine.
// States are WAIT, DATA, EOF, OVFLOW.
// Clock state to next state.
always @(posedge tx_fifo_aclk)
begin
if (tx_fifo_reset == 1'b1) begin
wr_state <= WAIT_s;
end
else begin
wr_state <= wr_nxt_state;
end
end
// Decode next state, combinatorial.
always @(wr_state, wr_sof_pipe[1], wr_eof_pipe[0], wr_eof_pipe[1],
wr_eof_bram[0], wr_fifo_overflow)
begin
case (wr_state)
WAIT_s : begin
if (wr_sof_pipe[1] == 1'b1 && wr_eof_pipe[1] == 1'b0) begin
wr_nxt_state <= DATA_s;
end
else begin
wr_nxt_state <= WAIT_s;
end
end
DATA_s : begin
// Wait for the end of frame to be detected.
if (wr_fifo_overflow == 1'b1 && wr_eof_pipe[0] == 1'b0
&& wr_eof_pipe[1] == 1'b0) begin
wr_nxt_state <= OVFLOW_s;
end
else if (wr_eof_pipe[1] == 1'b1) begin
wr_nxt_state <= EOF_s;
end
else begin
wr_nxt_state <= DATA_s;
end
end
EOF_s : begin
// If the start of frame is already in the pipe, a back-to-back frame
// transmission has occured. Move straight back to frame state.
if (wr_sof_pipe[1] == 1'b1 && wr_eof_pipe[1] == 1'b0) begin
wr_nxt_state <= DATA_s;
end
else if (wr_eof_bram[0] == 1'b1) begin
wr_nxt_state <= WAIT_s;
end
else begin
wr_nxt_state <= EOF_s;
end
end
OVFLOW_s : begin
// Wait until the end of frame is reached before clearing the overflow.
if (wr_eof_bram[0] == 1'b1) begin
wr_nxt_state <= WAIT_s;
end
else begin
wr_nxt_state <= OVFLOW_s;
end
end
default : begin
wr_nxt_state <= WAIT_s;
end
endcase
end
// Decode output signals.
// wr_en is used to enable the BRAM write and the address to increment.
assign wr_en = (wr_state == OVFLOW_s) ? 1'b0 : wr_accept_bram;
// The upper and lower signals are used to distinguish between the upper and
// lower BRAMs.
assign wr_en_l = wr_en & !wr_addr[11];
assign wr_en_u = wr_en & wr_addr[11];
assign wr_en_l_bram[0] = wr_en_l;
assign wr_en_u_bram[0] = wr_en_u;
assign wr_addr_inc = wr_en;
assign wr_addr_reload = (wr_state == OVFLOW_s) ? 1'b1 : 1'b0;
assign wr_start_addr_load = (wr_state == EOF_s && wr_nxt_state == WAIT_s)
? 1'b1 :
(wr_state == EOF_s && wr_nxt_state == DATA_s)
? 1'b1 : 1'b0;
// Pause the AxiStream handshake when the FIFO is full.
assign tx_axis_fifo_tready_int_n = (wr_state == OVFLOW_s) ?
wr_ovflow_dst_rdy : wr_fifo_full;
assign tx_axis_fifo_tready = !tx_axis_fifo_tready_int_n;
// Generate user overflow indicator.
assign fifo_overflow = (wr_state == OVFLOW_s) ? 1'b1 : 1'b0;
// When in overflow and have captured ovflow EOF, set tx_axis_fifo_tready again.
always @(posedge tx_fifo_aclk)
begin
if (tx_fifo_reset == 1'b1) begin
wr_ovflow_dst_rdy <= 1'b0;
end
else begin
if (wr_fifo_overflow == 1'b1 && wr_state == DATA_s) begin
wr_ovflow_dst_rdy <= 1'b0;
end
else if (tx_axis_fifo_tvalid == 1'b1 && tx_axis_fifo_tlast == 1'b1) begin
wr_ovflow_dst_rdy <= 1'b1;
end
end
end
// EOF signals for use in overflow logic.
assign wr_eof_state = (wr_state == EOF_s) ? 1'b1 : 1'b0;
always @(posedge tx_fifo_aclk)
begin
if (tx_fifo_reset == 1'b1) begin
wr_eof_state_reg <= 1'b0;
end
else begin
wr_eof_state_reg <= wr_eof_state;
end
end
//----------------------------------------------------------------------------
// Read state machine and control
//----------------------------------------------------------------------------
// Read state machine.
// States are IDLE, QUEUE1, QUEUE2, QUEUE3, QUEUE_ACK, WAIT_ACK, FRAME,
// HANDSHAKE, FINISH, DROP_ERROR, DROP, RETRANSMIT_ERROR, RETRANSMIT.
// Clock state to next state.
always @(posedge tx_mac_aclk)
begin
if (tx_mac_reset == 1'b1) begin
rd_state <= IDLE_s;
end
else begin
rd_state <= rd_nxt_state;
end
end
//----------------------------------------------------------------------------
// Full duplex-only state machine.
generate if (FULL_DUPLEX_ONLY == 1) begin : gen_fd_sm
// Decode next state, combinatorial.
always @(rd_state, frame_in_fifo, rd_eof, rd_eof_reg, tx_axis_mac_tready)
begin
case (rd_state)
IDLE_s : begin
// If there is a frame in the FIFO, start to queue the new frame
// to the output.
if (frame_in_fifo == 1'b1) begin
rd_nxt_state <= QUEUE1_s;
end
else begin
rd_nxt_state <= IDLE_s;
end
end
// Load the output pipeline, which takes three clock cycles.
QUEUE1_s : begin
rd_nxt_state <= QUEUE2_s;
end
QUEUE2_s : begin
rd_nxt_state <= QUEUE3_s;
end
QUEUE3_s : begin
rd_nxt_state <= QUEUE_ACK_s;
end
QUEUE_ACK_s : begin
// The pipeline is full and the frame output starts now.
rd_nxt_state <= WAIT_ACK_s;
end
WAIT_ACK_s : begin
// Await the tx_axis_mac_tready acknowledge before moving on.
if (tx_axis_mac_tready == 1'b1) begin
rd_nxt_state <= FRAME_s;
end
else begin
rd_nxt_state <= WAIT_ACK_s;
end
end
FRAME_s : begin
// Read the frame out of the FIFO. If the MAC deasserts
// tx_axis_mac_tready, stall in the handshake state. If the EOF
// flag is encountered, move to the finish state.
if (tx_axis_mac_tready == 1'b0)
begin
rd_nxt_state <= HANDSHAKE_s;
end
else if (rd_eof == 1'b1) begin
rd_nxt_state <= FINISH_s;
end
else begin
rd_nxt_state <= FRAME_s;
end
end
HANDSHAKE_s : begin
// Await tx_axis_mac_tready before continuing frame transmission.
// If the EOF flag is encountered, move to the finish state.
if (tx_axis_mac_tready == 1'b1 && rd_eof_reg == 1'b1) begin
rd_nxt_state <= FINISH_s;
end
else if (tx_axis_mac_tready == 1'b1 && rd_eof_reg == 1'b0) begin
rd_nxt_state <= FRAME_s;
end
else begin
rd_nxt_state <= HANDSHAKE_s;
end
end
FINISH_s : begin
// Frame has finished. Assure that the MAC has accepted the final
// byte by transitioning to idle only when tx_axis_mac_tready is high.
if (tx_axis_mac_tready == 1'b1) begin
rd_nxt_state <= IDLE_s;
end
else begin
rd_nxt_state <= FINISH_s;
end
end
default : begin
rd_nxt_state <= IDLE_s;
end
endcase
end
end
endgenerate
//----------------------------------------------------------------------------
// Full and half duplex state machine.
generate if (FULL_DUPLEX_ONLY != 1) begin : gen_hd_sm
// Decode the next state, combinatorial.
always @(rd_state, frame_in_fifo, rd_eof_reg, tx_axis_mac_tready, rd_drop_frame,
rd_retransmit)
begin
case (rd_state)
IDLE_s : begin
// If a retransmit request is detected then prepare to retransmit.
if (rd_retransmit == 1'b1) begin
rd_nxt_state <= RETRANSMIT_ERROR_s;
end
// If there is a frame in the FIFO, then queue the new frame to
// the output.
else if (frame_in_fifo == 1'b1) begin
rd_nxt_state <= QUEUE1_s;
end
else begin
rd_nxt_state <= IDLE_s;
end
end
// Load the output pipeline, which takes three clock cycles.
QUEUE1_s : begin
if (rd_retransmit == 1'b1) begin
rd_nxt_state <= RETRANSMIT_ERROR_s;
end
else begin
rd_nxt_state <= QUEUE2_s;
end
end
QUEUE2_s : begin
if (rd_retransmit == 1'b1) begin
rd_nxt_state <= RETRANSMIT_ERROR_s;
end
else begin
rd_nxt_state <= QUEUE3_s;
end
end
QUEUE3_s : begin
if (rd_retransmit == 1'b1) begin
rd_nxt_state <= RETRANSMIT_ERROR_s;
end
else begin
rd_nxt_state <= QUEUE_ACK_s;
end
end
QUEUE_ACK_s : begin
// The pipeline is full and the frame output starts now.
if (rd_retransmit == 1'b1) begin
rd_nxt_state <= RETRANSMIT_ERROR_s;
end
else begin
rd_nxt_state <= WAIT_ACK_s;
end
end
WAIT_ACK_s : begin
// Await the tx_axis_mac_tready acknowledge before moving on.
if (rd_retransmit == 1'b1) begin
rd_nxt_state <= RETRANSMIT_ERROR_s;
end
else if (tx_axis_mac_tready == 1'b1) begin
rd_nxt_state <= FRAME_s;
end
else begin
rd_nxt_state <= WAIT_ACK_s;
end
end
FRAME_s : begin
// If a collision-only request, then must drop the rest of the
// current frame. If collision and retransmit, then prepare
// to retransmit the frame.
if (rd_drop_frame == 1'b1) begin
rd_nxt_state <= DROP_ERROR_s;
end
else if (rd_retransmit == 1'b1) begin
rd_nxt_state <= RETRANSMIT_ERROR_s;
end
// Read the frame out of the FIFO. If the MAC deasserts
// tx_axis_mac_tready, stall in the handshake state. If the EOF
// flag is encountered, move to the finish state.
else if (tx_axis_mac_tready == 1'b0) begin
rd_nxt_state <= HANDSHAKE_s;
end
else if (rd_eof_reg == 1'b1) begin
rd_nxt_state <= FINISH_s;
end
else begin
rd_nxt_state <= FRAME_s;
end
end
HANDSHAKE_s : begin
// Await tx_axis_mac_tready before continuing frame transmission.
// If the EOF flag is encountered, move to the finish state.
if (rd_retransmit == 1'b1) begin
rd_nxt_state <= RETRANSMIT_ERROR_s;
end
else if (tx_axis_mac_tready == 1'b1 && rd_eof_reg == 1'b1) begin
rd_nxt_state <= FINISH_s;
end
else if (tx_axis_mac_tready == 1'b1 && rd_eof_reg == 1'b0) begin
rd_nxt_state <= FRAME_s;
end
else begin
rd_nxt_state <= HANDSHAKE_s;
end
end
FINISH_s : begin
// Frame has finished. Assure that the MAC has accepted the final
// byte by transitioning to idle only when tx_axis_mac_tready is high.
if (rd_retransmit == 1'b1) begin
rd_nxt_state <= RETRANSMIT_ERROR_s;
end
if (tx_axis_mac_tready == 1'b1) begin
rd_nxt_state <= IDLE_s;
end
else begin
rd_nxt_state <= FINISH_s;
end
end
DROP_ERROR_s : begin
// FIFO is ready to drop the frame. Assure that the MAC has
// accepted the final byte and error signal before dropping.
if (tx_axis_mac_tready == 1'b1) begin
rd_nxt_state <= DROP_s;
end
else begin
rd_nxt_state <= DROP_ERROR_s;
end
end
DROP_s : begin
// Wait until rest of frame has been cleared.
if (rd_eof_reg == 1'b1) begin
rd_nxt_state <= IDLE_s;
end
else begin
rd_nxt_state <= DROP_s;
end
end
RETRANSMIT_ERROR_s : begin
// FIFO is ready to retransmit the frame. Assure that the MAC has
// accepted the final byte and error signal before retransmitting.
if (tx_axis_mac_tready == 1'b1) begin
rd_nxt_state <= RETRANSMIT_s;
end
else begin
rd_nxt_state <= RETRANSMIT_ERROR_s;
end
end
RETRANSMIT_s : begin
// Reload the data pipeline from the start of the frame.
rd_nxt_state <= QUEUE1_s;
end
default : begin
rd_nxt_state <= IDLE_s;
end
endcase
end
end
endgenerate
// Combinatorially select tdata candidates.
assign tx_axis_mac_tdata_int_frame = (rd_nxt_state == HANDSHAKE_s) ?
tx_axis_mac_tdata_int : rd_data_pipe;
assign tx_axis_mac_tdata_int_handshake = (rd_nxt_state == FINISH_s) ?
rd_data_pipe : tx_axis_mac_tdata_int;
assign tx_axis_mac_tdata = tx_axis_mac_tdata_int;
// Decode output tdata based on current and next read state.
always @(posedge tx_mac_aclk)
begin
if (rd_nxt_state == FRAME_s)
tx_axis_mac_tdata_int <= rd_data_pipe;
else if (rd_nxt_state == RETRANSMIT_ERROR_s || rd_nxt_state == DROP_ERROR_s)
tx_axis_mac_tdata_int <= tx_axis_mac_tdata_int;
else begin
case (rd_state)
QUEUE_ACK_s :
tx_axis_mac_tdata_int <= rd_data_pipe;
FRAME_s :
tx_axis_mac_tdata_int <= tx_axis_mac_tdata_int_frame;
HANDSHAKE_s :
tx_axis_mac_tdata_int <= tx_axis_mac_tdata_int_handshake;
default :
tx_axis_mac_tdata_int <= tx_axis_mac_tdata_int;
endcase
end
end
// Combinatorially select tvalid candidates.
assign tx_axis_mac_tvalid_int_finish = (rd_nxt_state == IDLE_s) ?
1'b0 : 1'b1;
assign tx_axis_mac_tvalid_int_droperror = (rd_nxt_state == DROP_s) ?
1'b0 : 1'b1;
assign tx_axis_mac_tvalid_int_retransmiterror = (rd_nxt_state == RETRANSMIT_s) ?
1'b0 : 1'b1;
// Decode output tvalid based on current and next read state.
always @(posedge tx_mac_aclk)
begin
if (rd_nxt_state == FRAME_s)
tx_axis_mac_tvalid <= 1'b1;
else if (rd_nxt_state == RETRANSMIT_ERROR_s || rd_nxt_state == DROP_ERROR_s)
tx_axis_mac_tvalid <= 1'b1;
else
begin
case (rd_state)
QUEUE_ACK_s :
tx_axis_mac_tvalid <= 1'b1;
WAIT_ACK_s :
tx_axis_mac_tvalid <= 1'b1;
FRAME_s :
tx_axis_mac_tvalid <= 1'b1;
HANDSHAKE_s :
tx_axis_mac_tvalid <= 1'b1;
FINISH_s :
tx_axis_mac_tvalid <= tx_axis_mac_tvalid_int_finish;
DROP_ERROR_s :
tx_axis_mac_tvalid <= tx_axis_mac_tvalid_int_droperror;
RETRANSMIT_ERROR_s :
tx_axis_mac_tvalid <= tx_axis_mac_tvalid_int_retransmiterror;
default :
tx_axis_mac_tvalid <= 1'b0;
endcase
end
end
// Combinatorially select tlast candidates.
assign tx_axis_mac_tlast_int_frame_handshake = (rd_nxt_state == FINISH_s) ?
rd_eof_reg : 1'b0;
assign tx_axis_mac_tlast_int_finish = (rd_nxt_state == IDLE_s) ?
1'b0 : rd_eof_reg;
assign tx_axis_mac_tlast_int_droperror = (rd_nxt_state == DROP_s) ?
1'b0 : 1'b1;
assign tx_axis_mac_tlast_int_retransmiterror = (rd_nxt_state == RETRANSMIT_s) ?
1'b0 : 1'b1;
// Decode output tlast based on current and next read state.
always @(posedge tx_mac_aclk)
begin
if (rd_nxt_state == FRAME_s)
tx_axis_mac_tlast <= rd_eof;
else if (rd_nxt_state == RETRANSMIT_ERROR_s || rd_nxt_state == DROP_ERROR_s)
tx_axis_mac_tlast <= 1'b1;
else
begin
case (rd_state)
WAIT_ACK_s :
tx_axis_mac_tlast <= rd_eof;
FRAME_s :
tx_axis_mac_tlast <= tx_axis_mac_tlast_int_frame_handshake;
HANDSHAKE_s :
tx_axis_mac_tlast <= tx_axis_mac_tlast_int_frame_handshake;
FINISH_s :
tx_axis_mac_tlast <= tx_axis_mac_tlast_int_finish;
DROP_ERROR_s :
tx_axis_mac_tlast <= tx_axis_mac_tlast_int_droperror;
RETRANSMIT_ERROR_s :
tx_axis_mac_tlast <= tx_axis_mac_tlast_int_retransmiterror;
default :
tx_axis_mac_tlast <= 1'b0;
endcase
end
end
// Combinatorially select tuser candidates.
assign tx_axis_mac_tuser_int_droperror = (rd_nxt_state == DROP_s) ?
1'b0 : 1'b1;
assign tx_axis_mac_tuser_int_retransmit = (rd_nxt_state == RETRANSMIT_s) ?
1'b0 : 1'b1;
// Decode output tuser based on current and next read state.
always @(posedge tx_mac_aclk)
begin
if (rd_nxt_state == RETRANSMIT_ERROR_s || rd_nxt_state == DROP_ERROR_s)
tx_axis_mac_tuser <= 1'b1;
else
begin
case (rd_state)
DROP_ERROR_s :
tx_axis_mac_tuser <= tx_axis_mac_tuser_int_droperror;
RETRANSMIT_ERROR_s :
tx_axis_mac_tuser <= tx_axis_mac_tuser_int_retransmit;
default :
tx_axis_mac_tuser <= 1'b0;
endcase
end
end
//----------------------------------------------------------------------------
// Decode full duplex-only control signals.
generate if (FULL_DUPLEX_ONLY == 1) begin : gen_fd_decode
// rd_en is used to enable the BRAM read and load the output pipeline.
assign rd_en = (rd_state == IDLE_s) ? 1'b0 :
(rd_nxt_state == FRAME_s) ? 1'b1 :
(rd_state == FRAME_s && rd_nxt_state == HANDSHAKE_s) ? 1'b0 :
(rd_nxt_state == HANDSHAKE_s) ? 1'b0 :
(rd_state == FINISH_s) ? 1'b0 :
(rd_state == WAIT_ACK_s) ? 1'b0 : 1'b1;
// When the BRAM is being read, enable the read address to be incremented.
assign rd_addr_inc = rd_en;
assign rd_addr_reload = (rd_state != FINISH_s && rd_nxt_state == FINISH_s)
? 1'b1 : 1'b0;
// Transmit frame pulse must never be more frequent than once per 64 clocks to
// allow toggle to cross clock domain.
assign rd_transmit_frame = (rd_state == WAIT_ACK_s && rd_nxt_state == FRAME_s)
? 1'b1 : 1'b0;
// Unused for full duplex only.
assign rd_start_addr_reload = 1'b0;
assign rd_start_addr_load = 1'b0;
assign rd_retransmit_frame = 1'b0;
end
endgenerate
//----------------------------------------------------------------------------
// Decode full and half duplex control signals.
generate if (FULL_DUPLEX_ONLY != 1) begin : gen_hd_decode
// rd_en is used to enable the BRAM read and load the output pipeline.
assign rd_en = (rd_state == IDLE_s) ? 1'b0 :
(rd_nxt_state == DROP_ERROR_s) ? 1'b0 :
(rd_nxt_state == DROP_s && rd_eof == 1'b1) ? 1'b0 :
(rd_nxt_state == FRAME_s) ? 1'b1 :
(rd_state == FRAME_s && rd_nxt_state == HANDSHAKE_s) ? 1'b0 :
(rd_nxt_state == HANDSHAKE_s) ? 1'b0 :
(rd_state == FINISH_s) ? 1'b0 :
(rd_state == RETRANSMIT_ERROR_s) ? 1'b0 :
(rd_state == RETRANSMIT_s) ? 1'b0 :
(rd_state == WAIT_ACK_s) ? 1'b0 : 1'b1;
// When the BRAM is being read, enable the read address to be incremented.
assign rd_addr_inc = rd_en;
assign rd_addr_reload = (rd_state != FINISH_s && rd_nxt_state == FINISH_s)
? 1'b1 :
(rd_state == DROP_s && rd_nxt_state == IDLE_s)
? 1'b1 : 1'b0;
// Assertion indicates that the starting address must be reloaded to enable
// the current frame to be retransmitted.
assign rd_start_addr_reload = (rd_state == RETRANSMIT_s) ? 1'b1 : 1'b0;
assign rd_start_addr_load = (rd_state== WAIT_ACK_s && rd_nxt_state == FRAME_s)
? 1'b1 :
(rd_col_window_expire == 1'b1) ? 1'b1 : 1'b0;
// Transmit frame pulse must never be more frequent than once per 64 clocks to
// allow toggle to cross clock domain.
assign rd_transmit_frame = (rd_state == WAIT_ACK_s && rd_nxt_state == FRAME_s)
? 1'b1 : 1'b0;
// Retransmit frame pulse must never be more frequent than once per 16 clocks
// to allow toggle to cross clock domain.
assign rd_retransmit_frame = (rd_state == RETRANSMIT_s) ? 1'b1 : 1'b0;
end
endgenerate
//----------------------------------------------------------------------------
// Frame count
// We need to maintain a count of frames in the FIFO, so that we know when a
// frame is available for transmission. The counter must be held on the write
// clock domain as this is the faster clock if they differ.
//----------------------------------------------------------------------------
// A frame has been written to the FIFO.
assign wr_store_frame = (wr_state == EOF_s && wr_nxt_state != EOF_s)
? 1'b1 : 1'b0;
// Generate a toggle to indicate when a frame has been transmitted by the FIFO.
always @(posedge tx_mac_aclk)
begin
if (rd_transmit_frame == 1'b1) begin
rd_tran_frame_tog <= !rd_tran_frame_tog;
end
end
// Synchronize the read transmit frame signal into the write clock domain.
sync_block resync_rd_tran_frame_tog
(
.clk (tx_fifo_aclk),
.data_in (rd_tran_frame_tog),
.data_out (wr_tran_frame_sync)
);
// Edge-detect of the resynchronized transmit frame signal.
always @(posedge tx_fifo_aclk)
begin
wr_tran_frame_delay <= wr_tran_frame_sync;
end
always @(posedge tx_fifo_aclk)
begin
if (tx_fifo_reset == 1'b1) begin
wr_transmit_frame <= 1'b0;
end
else begin
// Edge detector
if ((wr_tran_frame_delay ^ wr_tran_frame_sync) == 1'b1) begin
wr_transmit_frame <= 1'b1;
end
else begin
wr_transmit_frame <= 1'b0;
end
end
end
//----------------------------------------------------------------------------
// Full duplex-only frame count.
generate if (FULL_DUPLEX_ONLY == 1) begin : gen_fd_count
// Count the number of frames in the FIFO. The counter is incremented when a
// frame is stored and decremented when a frame is transmitted. Need to keep
// the counter on the write clock as this is the fastest clock if they differ.
always @(posedge tx_fifo_aclk)
begin
if (tx_fifo_reset == 1'b1) begin
wr_frames <= 9'b0;
end
else begin
if ((wr_store_frame & !wr_transmit_frame) == 1'b1) begin
wr_frames <= wr_frames + 9'b1;
end
else if ((!wr_store_frame & wr_transmit_frame) == 1'b1) begin
wr_frames <= wr_frames - 9'b1;
end
end
end
end
endgenerate
//----------------------------------------------------------------------------
// Full and half duplex frame count.
generate if (FULL_DUPLEX_ONLY != 1) begin : gen_hd_count
// Generate a toggle to indicate when a frame has been retransmitted by
// the FIFO.
always @(posedge tx_mac_aclk)
begin // process
if (rd_retransmit_frame == 1'b1) begin
rd_retran_frame_tog <= !rd_retran_frame_tog;
end
end
// Synchronize the read retransmit frame signal into the write clock domain.
sync_block resync_rd_tran_frame_tog
(
.clk (tx_fifo_aclk),
.data_in (rd_retran_frame_tog),
.data_out (wr_retran_frame_sync)
);
// Edge detect of the resynchronized retransmit frame signal.
always @(posedge tx_fifo_aclk)
begin
wr_retran_frame_delay <= wr_retran_frame_sync;
end
always @(posedge tx_fifo_aclk)
begin
if (tx_fifo_reset == 1'b1) begin
wr_retransmit_frame <= 1'b0;
end
else begin
// Edge detector
if ((wr_retran_frame_delay ^ wr_retran_frame_sync) == 1'b1) begin
wr_retransmit_frame <= 1'b1;
end
else begin
wr_retransmit_frame <= 1'b0;
end
end
end
// Count the number of frames in the FIFO. The counter is incremented when a
// frame is stored or retransmitted and decremented when a frame is
// transmitted. Need to keep the counter on the write clock as this is the
// fastest clock if they differ. Logic assumes transmit and retransmit cannot
// happen at same time.
always @(posedge tx_fifo_aclk)
begin
if (tx_fifo_reset == 1'b1) begin
wr_frames <= 9'd0;
end
else begin
if ((wr_store_frame & wr_retransmit_frame) == 1'b1) begin
wr_frames <= wr_frames + 9'd2;
end
else if (((wr_store_frame | wr_retransmit_frame)
& !wr_transmit_frame) == 1'b1) begin
wr_frames <= wr_frames + 9'd1;
end
else if (wr_transmit_frame == 1'b1 & !wr_store_frame) begin
wr_frames <= wr_frames - 9'd1;
end
end
end
end
endgenerate
// Generate a frame in FIFO signal for use in control logic.
always @(posedge tx_fifo_aclk)
begin
if (tx_fifo_reset == 1'b1) begin
wr_frame_in_fifo <= 1'b0;
end
else begin
if (wr_frames != 9'b0) begin
wr_frame_in_fifo <= 1'b1;
end
else begin
wr_frame_in_fifo <= 1'b0;
end
end
end
// Synchronize it back onto read domain for use in the read logic.
sync_block resync_wr_frame_in_fifo
(
.clk (tx_mac_aclk),
.data_in (wr_frame_in_fifo),
.data_out (frame_in_fifo)
);
//----------------------------------------------------------------------------
// Address counters
//----------------------------------------------------------------------------
// Write address is incremented when write enable signal has been asserted.
always @(posedge tx_fifo_aclk)
begin
if (tx_fifo_reset == 1'b1) begin
wr_addr <= 12'b0;
end
else if (wr_addr_reload == 1'b1) begin
wr_addr <= wr_start_addr;
end
else if (wr_addr_inc == 1'b1) begin
wr_addr <= wr_addr + 12'b1;
end
end
// Store the start address in case the address must be reset.
always @(posedge tx_fifo_aclk)
begin
if (tx_fifo_reset == 1'b1) begin
wr_start_addr <= 12'b0;
end
else if (wr_start_addr_load == 1'b1) begin
wr_start_addr <= wr_addr + 12'b1;
end
end
//----------------------------------------------------------------------------
// Half duplex-only read address counters.
generate if (FULL_DUPLEX_ONLY == 1) begin : gen_fd_addr
// Read address is incremented when read enable signal has been asserted.
always @(posedge tx_mac_aclk)
begin
if (tx_mac_reset == 1'b1) begin
rd_addr <= 12'b0;
end
else begin
if (rd_addr_reload == 1'b1) begin
rd_addr <= rd_dec_addr;
end
else if (rd_addr_inc == 1'b1) begin
rd_addr <= rd_addr + 12'b1;
end
end
end
// Do not need to keep a start address, but the address is needed to
// calculate FIFO occupancy.
always @(posedge tx_mac_aclk)
begin
if (tx_mac_reset == 1'b1) begin
rd_start_addr <= 12'b0;
end
else begin
rd_start_addr <= rd_addr;
end
end
end
endgenerate
//----------------------------------------------------------------------------
// Full and half duplex read address counters.
generate if (FULL_DUPLEX_ONLY != 1) begin : gen_hd_addr
// Read address is incremented when read enable signal has been asserted.
always @(posedge tx_mac_aclk)
begin
if (tx_mac_reset == 1'b1) begin
rd_addr <= 12'b0;
end
else begin
if (rd_addr_reload == 1'b1) begin
rd_addr <= rd_dec_addr;
end
else if (rd_start_addr_reload == 1'b1) begin
rd_addr <= rd_start_addr;
end
else if (rd_addr_inc == 1'b1) begin
rd_addr <= rd_addr + 12'b1;
end
end
end
always @(posedge tx_mac_aclk)
begin
if (tx_mac_reset == 1'b1) begin
rd_start_addr <= 12'd0;
end
else begin
if (rd_start_addr_load == 1'b1) begin
rd_start_addr <= rd_addr - 12'd4;
end
end
end
// Collision window expires after MAC has been transmitting for required slot
// time. This is 512 clock cycles at 1Gbps. Also if the end of frame has fully
// been transmitted by the MAC then a collision cannot occur. This collision
// expiration signal goes high at 768 cycles from the start of the frame.
// This is inefficient for short frames, however it should be enough to
// prevent the FIFO from locking up.
always @(posedge tx_mac_aclk)
begin
if (tx_mac_reset == 1'b1) begin
rd_col_window_expire <= 1'b0;
end
else begin
if (rd_transmit_frame == 1'b1) begin
rd_col_window_expire <= 1'b0;
end
else if (rd_slot_timer[9:8] == 2'b11) begin
rd_col_window_expire <= 1'b1;
end
end
end
assign rd_idle_state = (rd_state == IDLE_s) ? 1'b1 : 1'b0;
always @(posedge tx_mac_aclk)
begin
rd_col_window_pipe[0] <= rd_col_window_expire & rd_idle_state;
if (rd_txfer_en == 1'b1) begin
rd_col_window_pipe[1] <= rd_col_window_pipe[0];
end
end
always @(posedge tx_mac_aclk)
begin
// Will not count until after the first frame is sent.
if (tx_mac_reset == 1'b1) begin
rd_slot_timer <= 10'b0;
end
else begin
// Reset counter.
if (rd_transmit_frame == 1'b1) begin
rd_slot_timer <= 10'b0;
end
// Do not allow counter to roll over, and
// only count when frame is being transmitted.
else if (rd_slot_timer != 10'b1111111111) begin
rd_slot_timer <= rd_slot_timer + 10'b1;
end
end
end
end
endgenerate
// Read address generation.
always @(posedge tx_mac_aclk)
begin
if (tx_mac_reset == 1'b1) begin
rd_dec_addr <= 12'b0;
end
else begin
if (rd_addr_inc == 1'b1) begin
rd_dec_addr <= rd_addr - 12'b1;
end
end
end
// Which BRAM is read from is dependent on the upper bit of the address
// space. This needs to be registered to give the correct timing.
always @(posedge tx_mac_aclk)
begin
if (tx_mac_reset == 1'b1) begin
rd_bram_u <= 1'b0;
rd_bram_u_reg <= 1'b0;
end
else begin
if (rd_addr_inc == 1'b1) begin
rd_bram_u <= rd_addr[11];
rd_bram_u_reg <= rd_bram_u;
end
end
end
//----------------------------------------------------------------------------
// Data pipelines
//----------------------------------------------------------------------------
// Register data inputs to BRAM.
// No resets to allow for SRL16 target.
always @(posedge tx_fifo_aclk)
begin
wr_data_pipe[0] <= tx_axis_fifo_tdata;
if (wr_accept_pipe[0] == 1'b1) begin
wr_data_pipe[1] <= wr_data_pipe[0];
end
if (wr_accept_pipe[1] == 1'b1) begin
wr_data_bram <= wr_data_pipe[1];
end
end
// Start of frame set when tvalid is asserted and previous frame has ended.
assign wr_sof_int = tx_axis_fifo_tvalid & wr_eof_reg;
// Set end of frame flag when tlast and tvalid are asserted together.
// Reset to logic 1 to enable first frame's start of frame flag.
always @(posedge tx_fifo_aclk)
begin
if (tx_fifo_reset == 1'b1) begin
wr_eof_reg <= 1'b1;
end
else begin
if (tx_axis_fifo_tvalid == 1'b1 & tx_axis_fifo_tready_int_n == 1'b0) begin
wr_eof_reg <= tx_axis_fifo_tlast;
end
end
end
// Pipeline the start of frame flag when the pipe is enabled.
always @(posedge tx_fifo_aclk)
begin
wr_sof_pipe[0] <= wr_sof_int;
if (wr_accept_pipe[0] == 1'b1) begin
wr_sof_pipe[1] <= wr_sof_pipe[0];
end
end
// Pipeline the pipeline enable signal, which is derived from simultaneous
// assertion of tvalid and tready.
always @(posedge tx_fifo_aclk)
begin
if (tx_fifo_reset == 1'b1) begin
wr_accept_pipe[0] <= 1'b0;
wr_accept_pipe[1] <= 1'b0;
wr_accept_bram <= 1'b0;
end
else begin
wr_accept_pipe[0] <= tx_axis_fifo_tvalid & !tx_axis_fifo_tready_int_n;
wr_accept_pipe[1] <= wr_accept_pipe[0];
wr_accept_bram <= wr_accept_pipe[1];
end
end
// Pipeline the end of frame flag when the pipe is enabled.
always @(posedge tx_fifo_aclk)
begin
wr_eof_pipe[0] <= tx_axis_fifo_tvalid & tx_axis_fifo_tlast;
if (wr_accept_pipe[0] == 1'b1) begin
wr_eof_pipe[1] <= wr_eof_pipe[0];
end
if (wr_accept_pipe[1] == 1'b1) begin
wr_eof_bram[0] <= wr_eof_pipe[1];
end
end
// Register data outputs from BRAM.
// No resets to allow for SRL16 target.
always @(posedge tx_mac_aclk)
begin
if (rd_en == 1'b1) begin
rd_data_pipe_u <= rd_data_bram_u;
rd_data_pipe_l <= rd_data_bram_l;
if (rd_bram_u_reg == 1'b1) begin
rd_data_pipe <= rd_data_pipe_u;
end
else begin
rd_data_pipe <= rd_data_pipe_l;
end
end
end
always @(posedge tx_mac_aclk)
begin
if (rd_en == 1'b1) begin
if (rd_bram_u == 1'b1) begin
rd_eof_pipe <= rd_eof_bram_u[0];
end
else begin
rd_eof_pipe <= rd_eof_bram_l[0];
end
rd_eof <= rd_eof_pipe;
rd_eof_reg <= rd_eof | rd_eof_pipe;
end
end
//----------------------------------------------------------------------------
// Half duplex-only drop and retransmission controls.
generate if (FULL_DUPLEX_ONLY != 1) begin : gen_hd_input
// Register the collision without retransmit signal, which is a pulse that
// causes the FIFO to drop the frame.
always @(posedge tx_mac_aclk)
begin
rd_drop_frame <= tx_collision & !tx_retransmit;
end
// Register the collision with retransmit signal, which is a pulse that
// causes the FIFO to retransmit the frame.
always @(posedge tx_mac_aclk)
begin
rd_retransmit <= tx_collision & tx_retransmit;
end
end
endgenerate
//----------------------------------------------------------------------------
// FIFO full functionality
//----------------------------------------------------------------------------
// Full functionality is the difference between read and write addresses.
// We cannot use gray code this time as the read address and read start
// addresses jump by more than 1.
// We generate an enable pulse for the read side every 16 read clocks. This
// provides for the worst-case situation where the write clock is 20MHz and
// read clock is 125MHz.
always @(posedge tx_mac_aclk)
begin
if (tx_mac_reset == 1'b1) begin
rd_16_count <= 4'b0;
end
else begin
rd_16_count <= rd_16_count + 4'b1;
end
end
assign rd_txfer_en = (rd_16_count == 4'b1111) ? 1'b1 : 1'b0;
// Register the start address on the enable pulse.
always @(posedge tx_mac_aclk)
begin
if (tx_mac_reset == 1'b1) begin
rd_addr_txfer <= 12'b0;
end
else begin
if (rd_txfer_en == 1'b1) begin
rd_addr_txfer <= rd_start_addr;
end
end
end
// Generate a toggle to indicate that the address has been loaded.
always @(posedge tx_mac_aclk)
begin
if (rd_txfer_en == 1'b1) begin
rd_txfer_tog <= !rd_txfer_tog;
end
end
// Synchronize the toggle to the write side.
sync_block resync_rd_txfer_tog
(
.clk (tx_fifo_aclk),
.data_in (rd_txfer_tog),
.data_out (wr_txfer_tog_sync)
);
// Delay the synchronized toggle by one cycle.
always @(posedge tx_fifo_aclk)
begin
wr_txfer_tog_delay <= wr_txfer_tog_sync;
end
// Generate an enable pulse from the toggle. The address should have been
// steady on the wr clock input for at least one clock.
assign wr_txfer_en = wr_txfer_tog_delay ^ wr_txfer_tog_sync;
// Capture the address on the write clock when the enable pulse is high.
always @(posedge tx_fifo_aclk)
begin
if (tx_fifo_reset == 1'b1) begin
wr_rd_addr <= 12'b0;
end
else if (wr_txfer_en == 1'b1) begin
wr_rd_addr <= rd_addr_txfer;
end
end
// Obtain the difference between write and read pointers.
always @(posedge tx_fifo_aclk)
begin
if (tx_fifo_reset == 1'b1) begin
wr_addr_diff <= 12'b0;
end
else begin
wr_addr_diff <= wr_rd_addr - wr_addr;
end
end
// Detect when the FIFO is full.
// The FIFO is considered to be full if the write address pointer is
// within 0 to 3 of the read address pointer.
always @(posedge tx_fifo_aclk)
begin
if (tx_fifo_reset == 1'b1) begin
wr_fifo_full <= 1'b0;
end
else begin
if (wr_addr_diff[11:4] == 8'b0 && wr_addr_diff[3:2] != 2'b0) begin
wr_fifo_full <= 1'b1;
end
else begin
wr_fifo_full <= 1'b0;
end
end
end
// Memory overflow occurs when the FIFO is full and there are no frames
// available in the FIFO for transmission. If the collision window has
// expired and there are no frames in the FIFO and the FIFO is full, then the
// FIFO is in an overflow state. We must accept the rest of the incoming
// frame in overflow condition.
generate if (FULL_DUPLEX_ONLY == 1) begin : gen_fd_ovflow
// In full duplex mode, the FIFO memory can only overflow if the FIFO goes
// full but there is no frame available to be retranmsitted. Therefore,
// prevent signal from being asserted when store_frame signal is high, as
// frame count is being updated.
assign wr_fifo_overflow = (wr_fifo_full == 1'b1 && wr_frame_in_fifo == 1'b0
&& wr_eof_state == 1'b0
&& wr_eof_state_reg == 1'b0)
? 1'b1 : 1'b0;
end
endgenerate
generate if (FULL_DUPLEX_ONLY != 1) begin : gen_hd_ovflow
// In half duplex mode, register write collision window to give address
// counter sufficient time to update. This will prevent the signal from
// being asserted when the store_frame signal is high, as the frame count
// is being updated.
assign wr_fifo_overflow = (wr_fifo_full == 1'b1 && wr_frame_in_fifo == 1'b0
&& wr_eof_state == 1'b0
&& wr_eof_state_reg == 1'b0
&& wr_col_window_expire == 1'b1)
? 1'b1 : 1'b0;
// Register rd_col_window signal.
// This signal is long, and will remain high until overflow functionality
// has finished, so save just to register once.
always @(posedge tx_fifo_aclk)
begin
if (tx_fifo_reset == 1'b1) begin
wr_col_window_pipe[0] <= 1'b0;
wr_col_window_pipe[1] <= 1'b0;
wr_col_window_expire <= 1'b0;
end
else begin
if (wr_txfer_en == 1'b1) begin
wr_col_window_pipe[0] <= rd_col_window_pipe[1];
end
wr_col_window_pipe[1] <= wr_col_window_pipe[0];
wr_col_window_expire <= wr_col_window_pipe[1];
end
end
end
endgenerate
//----------------------------------------------------------------------------
// FIFO status signals
//----------------------------------------------------------------------------
// The FIFO status is four bits which represents the occupancy of the FIFO
// in sixteenths. To generate this signal we therefore only need to compare
// the 4 most significant bits of the write address pointer with the 4 most
// significant bits of the read address pointer.
always @(posedge tx_fifo_aclk)
begin
if (tx_fifo_reset == 1'b1) begin
wr_fifo_status <= 4'b0;
end
else begin
if (wr_addr_diff == 12'b0) begin
wr_fifo_status <= 4'b0;
end
else begin
wr_fifo_status[3] <= !wr_addr_diff[11];
wr_fifo_status[2] <= !wr_addr_diff[10];
wr_fifo_status[1] <= !wr_addr_diff[9];
wr_fifo_status[0] <= !wr_addr_diff[8];
end
end
end
assign fifo_status = wr_fifo_status;
//----------------------------------------------------------------------------
// Instantiate FIFO block memory
//----------------------------------------------------------------------------
assign wr_eof_data_bram[8] = wr_eof_bram[0];
assign wr_eof_data_bram[7:0] = wr_data_bram;
// Block RAM for lower address space (rd_addr[11] = 1'b0)
assign rd_eof_bram_l[0] = rd_eof_data_bram_l[8];
assign rd_data_bram_l = rd_eof_data_bram_l[7:0];
BRAM_TDP_MACRO #
(
.DEVICE ("VIRTEX6"),
.BRAM_SIZE ("18Kb"),
.WRITE_WIDTH_A (9),
.WRITE_WIDTH_B (9),
.READ_WIDTH_A (9),
.READ_WIDTH_B (9)
)
ramgen_l (
.DOA (rd_bram_l_unused),
.DOB (rd_eof_data_bram_l),
.ADDRA (wr_addr[10:0]),
.ADDRB (rd_addr[10:0]),
.CLKA (tx_fifo_aclk),
.CLKB (tx_mac_aclk),
.DIA (wr_eof_data_bram),
.DIB (GND_BUS[8:0]),
.ENA (VCC),
.ENB (rd_en),
.REGCEA (VCC),
.REGCEB (VCC),
.RSTA (tx_fifo_reset),
.RSTB (tx_mac_reset),
.WEA (wr_en_l_bram),
.WEB (GND)
);
// Block RAM for upper address space (rd_addr[11] = 1'b1)
assign rd_eof_bram_u[0] = rd_eof_data_bram_u[8];
assign rd_data_bram_u = rd_eof_data_bram_u[7:0];
BRAM_TDP_MACRO #
(
.DEVICE ("VIRTEX6"),
.BRAM_SIZE ("18Kb"),
.WRITE_WIDTH_A (9),
.WRITE_WIDTH_B (9),
.READ_WIDTH_A (9),
.READ_WIDTH_B (9)
)
ramgen_u (
.DOA (rd_bram_u_unused),
.DOB (rd_eof_data_bram_u),
.ADDRA (wr_addr[10:0]),
.ADDRB (rd_addr[10:0]),
.CLKA (tx_fifo_aclk),
.CLKB (tx_mac_aclk),
.DIA (wr_eof_data_bram),
.DIB (GND_BUS[8:0]),
.ENA (VCC),
.ENB (rd_en),
.REGCEA (VCC),
.REGCEB (VCC),
.RSTA (tx_fifo_reset),
.RSTB (tx_mac_reset),
.WEA (wr_en_u_bram),
.WEB (GND)
);
endmodule
|
/*
* Copyright (C) 2007 Onno Kortmann <[email protected]>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*
*/
/* SimulavrXX glue code on the verilog side. */
/* FIXME: Some parts are still unfinished!
FIXME: Output-pullups are not implemented yet - find a good way to do that!
*/
module avr_pin(conn);
parameter name="UNSPECIFIED";
inout conn;
wire out;
integer val;
wire output_active;
assign output_active = (val<=2);
assign conn = output_active ? out : 1'bz;
function a2v;
input apin;
if (apin==0) // low
a2v=0;
else if (apin==1) // high
a2v=1;
else if (apin==2) // shorted
a2v=1'bx;
else if (apin==3) // pull-up
a2v=1;
else if (apin==4) // tristate
a2v=1'bz;
else if (apin==5) // pull-down
a2v=0;
else if (apin==6) // analog
a2v=1'bx;
else if (apin==7) // analog, shorted
a2v=1'bx;
endfunction // a2v
function v2a;
input vpin;
if (vpin==1'bz)
v2a=4; // tristate
else if (vpin==1'bx)
v2a=2; // approximate as shorted
else if (vpin==1)
v2a=1; // high
else if (vpin==0)
v2a=0; // low
endfunction // v2a
assign out=a2v(val);
always @(posedge core.clk) begin
val<=$avr_get_pin(core.handle, name);
$avr_set_pin(core.handle, name, v2a(conn));
end
endmodule // avr_pin
module avr_clock(clk);
output clk;
reg clk;
parameter FREQ=4_000_000;
initial begin
clk<=0;
end
always @(clk) begin
#(1_000_000_000/FREQ/2) clk<=~clk; //125000 -> 4MHz clock
end
endmodule // avr_clock
module AVRCORE(clk);
parameter progfile="UNSPECIFIED";
parameter name="UNSPECIFIED";
input clk;
integer handle;
integer PCw; // word-wise PC as it comes from simulavrxx
wire [16:0] PCb; // byte-wise PC as used in output from avr-objdump!
assign PCb=2*PCw;
initial begin
$display("Creating an AVR device.");
handle=$avr_create(name, progfile);
//$avr_reset(handle);
end
always @(posedge clk) begin
$avr_set_time($time);
$avr_tick(handle);
PCw=$avr_get_pc(handle);
end
endmodule // AVRCORE
|
// megafunction wizard: %ALTFP_DIV%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altfp_div
// ============================================================
// File Name: acl_fp_div_double.v
// Megafunction Name(s):
// altfp_div
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.0 Build 157 04/27/2011 SJ Full Version
// ************************************************************
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//altfp_div CBX_AUTO_BLACKBOX="ALL" DENORMAL_SUPPORT="NO" DEVICE_FAMILY="Stratix IV" OPTIMIZE="SPEED" PIPELINE=24 REDUCED_FUNCTIONALITY="NO" WIDTH_EXP=11 WIDTH_MAN=52 clk_en clock dataa datab result
//VERSION_BEGIN 11.0 cbx_altbarrel_shift 2011:04:27:21:07:19:SJ cbx_altfp_div 2011:04:27:21:07:19:SJ cbx_altsyncram 2011:04:27:21:07:19:SJ cbx_cycloneii 2011:04:27:21:07:19:SJ cbx_lpm_abs 2011:04:27:21:07:19:SJ cbx_lpm_add_sub 2011:04:27:21:07:19:SJ cbx_lpm_compare 2011:04:27:21:07:19:SJ cbx_lpm_decode 2011:04:27:21:07:19:SJ cbx_lpm_divide 2011:04:27:21:07:19:SJ cbx_lpm_mult 2011:04:27:21:07:19:SJ cbx_lpm_mux 2011:04:27:21:07:19:SJ cbx_mgl 2011:04:27:21:11:03:SJ cbx_padd 2011:04:27:21:07:19:SJ cbx_stratix 2011:04:27:21:07:19:SJ cbx_stratixii 2011:04:27:21:07:19:SJ cbx_stratixiii 2011:04:27:21:07:19:SJ cbx_stratixv 2011:04:27:21:07:19:SJ cbx_util_mgl 2011:04:27:21:07:19:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//altfp_div_pst CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix IV" FILE_NAME="acl_fp_div_double.v:a" PIPELINE=24 WIDTH_EXP=11 WIDTH_MAN=52 aclr clk_en clock dataa datab result
//VERSION_BEGIN 11.0 cbx_altbarrel_shift 2011:04:27:21:07:19:SJ cbx_altfp_div 2011:04:27:21:07:19:SJ cbx_altsyncram 2011:04:27:21:07:19:SJ cbx_cycloneii 2011:04:27:21:07:19:SJ cbx_lpm_abs 2011:04:27:21:07:19:SJ cbx_lpm_add_sub 2011:04:27:21:07:19:SJ cbx_lpm_compare 2011:04:27:21:07:19:SJ cbx_lpm_decode 2011:04:27:21:07:19:SJ cbx_lpm_divide 2011:04:27:21:07:19:SJ cbx_lpm_mult 2011:04:27:21:07:19:SJ cbx_lpm_mux 2011:04:27:21:07:19:SJ cbx_mgl 2011:04:27:21:11:03:SJ cbx_padd 2011:04:27:21:07:19:SJ cbx_stratix 2011:04:27:21:07:19:SJ cbx_stratixii 2011:04:27:21:07:19:SJ cbx_stratixiii 2011:04:27:21:07:19:SJ cbx_stratixv 2011:04:27:21:07:19:SJ cbx_util_mgl 2011:04:27:21:07:19:SJ VERSION_END
//synthesis_resources = altsyncram 1 lpm_add_sub 8 lpm_compare 1 lpm_mult 9 mux21 141 reg 3551
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_div_double_altfp_div_pst_npf
(
aclr,
clk_en,
clock,
dataa,
datab,
result) ;
input aclr;
input clk_en;
input clock;
input [63:0] dataa;
input [63:0] datab;
output [63:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clk_en;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [8:0] wire_altsyncram3_q_a;
reg a_is_infinity_dffe_0;
reg a_is_infinity_dffe_1;
reg a_is_infinity_dffe_10;
reg a_is_infinity_dffe_11;
reg a_is_infinity_dffe_12;
reg a_is_infinity_dffe_13;
reg a_is_infinity_dffe_14;
reg a_is_infinity_dffe_15;
reg a_is_infinity_dffe_16;
reg a_is_infinity_dffe_17;
reg a_is_infinity_dffe_18;
reg a_is_infinity_dffe_19;
reg a_is_infinity_dffe_2;
reg a_is_infinity_dffe_20;
reg a_is_infinity_dffe_21;
reg a_is_infinity_dffe_22;
reg a_is_infinity_dffe_3;
reg a_is_infinity_dffe_4;
reg a_is_infinity_dffe_5;
reg a_is_infinity_dffe_6;
reg a_is_infinity_dffe_7;
reg a_is_infinity_dffe_8;
reg a_is_infinity_dffe_9;
reg a_zero_b_not_dffe_0;
reg a_zero_b_not_dffe_1;
reg a_zero_b_not_dffe_10;
reg a_zero_b_not_dffe_11;
reg a_zero_b_not_dffe_12;
reg a_zero_b_not_dffe_13;
reg a_zero_b_not_dffe_14;
reg a_zero_b_not_dffe_15;
reg a_zero_b_not_dffe_16;
reg a_zero_b_not_dffe_17;
reg a_zero_b_not_dffe_18;
reg a_zero_b_not_dffe_19;
reg a_zero_b_not_dffe_2;
reg a_zero_b_not_dffe_20;
reg a_zero_b_not_dffe_21;
reg a_zero_b_not_dffe_22;
reg a_zero_b_not_dffe_3;
reg a_zero_b_not_dffe_4;
reg a_zero_b_not_dffe_5;
reg a_zero_b_not_dffe_6;
reg a_zero_b_not_dffe_7;
reg a_zero_b_not_dffe_8;
reg a_zero_b_not_dffe_9;
reg [62:0] b1_dffe_0;
reg [62:0] b1_dffe_1;
reg [62:0] b1_dffe_10;
reg [62:0] b1_dffe_11;
reg [62:0] b1_dffe_12;
reg [62:0] b1_dffe_13;
reg [62:0] b1_dffe_2;
reg [62:0] b1_dffe_3;
reg [62:0] b1_dffe_4;
reg [62:0] b1_dffe_5;
reg [62:0] b1_dffe_6;
reg [62:0] b1_dffe_7;
reg [62:0] b1_dffe_8;
reg [62:0] b1_dffe_9;
reg b_is_infinity_dffe_0;
reg b_is_infinity_dffe_1;
reg b_is_infinity_dffe_10;
reg b_is_infinity_dffe_11;
reg b_is_infinity_dffe_12;
reg b_is_infinity_dffe_13;
reg b_is_infinity_dffe_14;
reg b_is_infinity_dffe_15;
reg b_is_infinity_dffe_16;
reg b_is_infinity_dffe_17;
reg b_is_infinity_dffe_18;
reg b_is_infinity_dffe_19;
reg b_is_infinity_dffe_2;
reg b_is_infinity_dffe_20;
reg b_is_infinity_dffe_21;
reg b_is_infinity_dffe_22;
reg b_is_infinity_dffe_3;
reg b_is_infinity_dffe_4;
reg b_is_infinity_dffe_5;
reg b_is_infinity_dffe_6;
reg b_is_infinity_dffe_7;
reg b_is_infinity_dffe_8;
reg b_is_infinity_dffe_9;
reg both_exp_zeros_dffe;
reg divbyzero_pipe_dffe_0;
reg divbyzero_pipe_dffe_1;
reg divbyzero_pipe_dffe_10;
reg divbyzero_pipe_dffe_11;
reg divbyzero_pipe_dffe_12;
reg divbyzero_pipe_dffe_13;
reg divbyzero_pipe_dffe_14;
reg divbyzero_pipe_dffe_15;
reg divbyzero_pipe_dffe_16;
reg divbyzero_pipe_dffe_17;
reg divbyzero_pipe_dffe_18;
reg divbyzero_pipe_dffe_19;
reg divbyzero_pipe_dffe_2;
reg divbyzero_pipe_dffe_20;
reg divbyzero_pipe_dffe_21;
reg divbyzero_pipe_dffe_22;
reg divbyzero_pipe_dffe_3;
reg divbyzero_pipe_dffe_4;
reg divbyzero_pipe_dffe_5;
reg divbyzero_pipe_dffe_6;
reg divbyzero_pipe_dffe_7;
reg divbyzero_pipe_dffe_8;
reg divbyzero_pipe_dffe_9;
reg [16:0] e1_dffe_0;
reg [16:0] e1_dffe_1;
reg [16:0] e1_dffe_2;
reg [16:0] e1_dffe_3;
reg [16:0] e1_dffe_4;
reg [16:0] e1_dffe_5;
reg [16:0] e1_dffe_perf_0;
reg [16:0] e1_dffe_perf_1;
reg [16:0] e1_dffe_perf_10;
reg [16:0] e1_dffe_perf_11;
reg [16:0] e1_dffe_perf_2;
reg [16:0] e1_dffe_perf_3;
reg [16:0] e1_dffe_perf_4;
reg [16:0] e1_dffe_perf_5;
reg [16:0] e1_dffe_perf_6;
reg [16:0] e1_dffe_perf_7;
reg [16:0] e1_dffe_perf_8;
reg [16:0] e1_dffe_perf_9;
reg [10:0] exp_result_dffe_0;
reg [10:0] exp_result_dffe_1;
reg [10:0] exp_result_dffe_10;
reg [10:0] exp_result_dffe_11;
reg [10:0] exp_result_dffe_12;
reg [10:0] exp_result_dffe_13;
reg [10:0] exp_result_dffe_14;
reg [10:0] exp_result_dffe_15;
reg [10:0] exp_result_dffe_16;
reg [10:0] exp_result_dffe_17;
reg [10:0] exp_result_dffe_18;
reg [10:0] exp_result_dffe_19;
reg [10:0] exp_result_dffe_2;
reg [10:0] exp_result_dffe_20;
reg [10:0] exp_result_dffe_21;
reg [10:0] exp_result_dffe_3;
reg [10:0] exp_result_dffe_4;
reg [10:0] exp_result_dffe_5;
reg [10:0] exp_result_dffe_6;
reg [10:0] exp_result_dffe_7;
reg [10:0] exp_result_dffe_8;
reg [10:0] exp_result_dffe_9;
reg frac_a_smaller_dffe1;
reg [51:0] man_a_dffe1_dffe1;
reg [51:0] man_b_dffe1_dffe1;
reg [51:0] man_result_dffe;
reg nan_pipe_dffe_0;
reg nan_pipe_dffe_1;
reg nan_pipe_dffe_10;
reg nan_pipe_dffe_11;
reg nan_pipe_dffe_12;
reg nan_pipe_dffe_13;
reg nan_pipe_dffe_14;
reg nan_pipe_dffe_15;
reg nan_pipe_dffe_16;
reg nan_pipe_dffe_17;
reg nan_pipe_dffe_18;
reg nan_pipe_dffe_19;
reg nan_pipe_dffe_2;
reg nan_pipe_dffe_20;
reg nan_pipe_dffe_21;
reg nan_pipe_dffe_22;
reg nan_pipe_dffe_3;
reg nan_pipe_dffe_4;
reg nan_pipe_dffe_5;
reg nan_pipe_dffe_6;
reg nan_pipe_dffe_7;
reg nan_pipe_dffe_8;
reg nan_pipe_dffe_9;
reg over_under_dffe_0;
reg over_under_dffe_1;
reg over_under_dffe_10;
reg over_under_dffe_11;
reg over_under_dffe_12;
reg over_under_dffe_13;
reg over_under_dffe_14;
reg over_under_dffe_15;
reg over_under_dffe_16;
reg over_under_dffe_17;
reg over_under_dffe_18;
reg over_under_dffe_19;
reg over_under_dffe_2;
reg over_under_dffe_20;
reg over_under_dffe_3;
reg over_under_dffe_4;
reg over_under_dffe_5;
reg over_under_dffe_6;
reg over_under_dffe_7;
reg over_under_dffe_8;
reg over_under_dffe_9;
reg [33:0] q_partial_perf_dffe_0;
reg [33:0] q_partial_perf_dffe_1;
reg [33:0] q_partial_perf_dffe_2;
reg [33:0] q_partial_perf_dffe_3;
reg [16:0] quotient_j_dffe;
reg [16:0] quotient_k_dffe_0;
reg [30:0] quotient_k_dffe_1;
reg [44:0] quotient_k_dffe_2;
reg [16:0] quotient_k_dffe_perf_0;
reg [16:0] quotient_k_dffe_perf_1;
reg [44:0] quotient_k_dffe_perf_10;
reg [44:0] quotient_k_dffe_perf_11;
reg [16:0] quotient_k_dffe_perf_2;
reg [16:0] quotient_k_dffe_perf_3;
reg [30:0] quotient_k_dffe_perf_4;
reg [30:0] quotient_k_dffe_perf_5;
reg [30:0] quotient_k_dffe_perf_6;
reg [30:0] quotient_k_dffe_perf_7;
reg [44:0] quotient_k_dffe_perf_8;
reg [44:0] quotient_k_dffe_perf_9;
reg [78:0] remainder_j_dffe_0;
reg [78:0] remainder_j_dffe_1;
reg [78:0] remainder_j_dffe_2;
reg [78:0] remainder_j_dffe_3;
reg [78:0] remainder_j_dffe_4;
reg [78:0] remainder_j_dffe_5;
reg [78:0] remainder_j_dffe_perf_0;
reg [78:0] remainder_j_dffe_perf_1;
reg [78:0] remainder_j_dffe_perf_2;
reg [78:0] remainder_j_dffe_perf_3;
reg [78:0] remainder_j_dffe_perf_4;
reg [78:0] remainder_j_dffe_perf_5;
reg [78:0] remainder_j_dffe_perf_6;
reg [78:0] remainder_j_dffe_perf_7;
reg [78:0] remainder_j_dffe_perf_8;
reg sign_pipe_dffe_0;
reg sign_pipe_dffe_1;
reg sign_pipe_dffe_10;
reg sign_pipe_dffe_11;
reg sign_pipe_dffe_12;
reg sign_pipe_dffe_13;
reg sign_pipe_dffe_14;
reg sign_pipe_dffe_15;
reg sign_pipe_dffe_16;
reg sign_pipe_dffe_17;
reg sign_pipe_dffe_18;
reg sign_pipe_dffe_19;
reg sign_pipe_dffe_2;
reg sign_pipe_dffe_20;
reg sign_pipe_dffe_21;
reg sign_pipe_dffe_22;
reg sign_pipe_dffe_23;
reg sign_pipe_dffe_3;
reg sign_pipe_dffe_4;
reg sign_pipe_dffe_5;
reg sign_pipe_dffe_6;
reg sign_pipe_dffe_7;
reg sign_pipe_dffe_8;
reg sign_pipe_dffe_9;
wire wire_bias_addition_overflow;
wire [11:0] wire_bias_addition_result;
wire [11:0] wire_exp_sub_result;
wire [30:0] wire_quotient_accumulate_0_result;
wire [44:0] wire_quotient_accumulate_1_result;
wire [58:0] wire_quotient_process_result;
wire [78:0] wire_remainder_sub_0_result;
wire [78:0] wire_remainder_sub_1_result;
wire [78:0] wire_remainder_sub_2_result;
wire wire_cmpr2_alb;
wire [63:0] wire_a1_prod_result;
wire [62:0] wire_b1_prod_result;
wire [33:0] wire_q_partial_0_result;
wire [33:0] wire_q_partial_1_result;
wire [33:0] wire_q_partial_2_result;
wire [33:0] wire_q_partial_3_result;
wire [79:0] wire_remainder_mult_0_result;
wire [79:0] wire_remainder_mult_1_result;
wire [79:0] wire_remainder_mult_2_result;
wire [10:0]wire_exp_result_muxa_dataout;
wire [53:0]wire_man_a_adjusteda_dataout;
wire [51:0]wire_man_result_muxa_dataout;
wire [11:0]wire_select_bias_2a_dataout;
wire [11:0]wire_select_biasa_dataout;
wire a_is_infinity_w;
wire a_is_nan_w;
wire a_zero_b_not;
wire [188:0] b1_dffe_w;
wire b_is_infinity_w;
wire b_is_nan_w;
wire bias_addition_overf_w;
wire [10:0] bias_addition_w;
wire both_exp_zeros;
wire [8:0] e0_dffe1_wo;
wire [8:0] e0_w;
wire [118:0] e1_w;
wire [10:0] exp_a_all_one_w;
wire [10:0] exp_a_not_zero_w;
wire [10:0] exp_add_output_all_one;
wire [10:0] exp_add_output_not_zero;
wire [10:0] exp_b_all_one_w;
wire [10:0] exp_b_not_zero_w;
wire [10:0] exp_result_mux_out;
wire exp_result_mux_sel_w;
wire [10:0] exp_result_w;
wire exp_sign_w;
wire [11:0] exp_sub_a_w;
wire [11:0] exp_sub_b_w;
wire [11:0] exp_sub_w;
wire frac_a_smaller_dffe1_wi;
wire frac_a_smaller_dffe1_wo;
wire frac_a_smaller_w;
wire guard_bit;
wire [53:0] man_a_adjusted_w;
wire [51:0] man_a_dffe1_wi;
wire [51:0] man_a_dffe1_wo;
wire [51:0] man_a_not_zero_w;
wire [52:0] man_b_adjusted_w;
wire [51:0] man_b_dffe1_wi;
wire [51:0] man_b_dffe1_wo;
wire [51:0] man_b_not_zero_w;
wire [51:0] man_result_dffe_wi;
wire [51:0] man_result_dffe_wo;
wire man_result_mux_select;
wire [51:0] man_result_w;
wire [51:0] man_zeros_w;
wire [10:0] overflow_ones_w;
wire overflow_underflow;
wire overflow_w;
wire [235:0] quotient_accumulate_w;
wire quotient_process_cin_w;
wire [315:0] remainder_j_w;
wire round_bit;
wire [11:0] select_bias_out_2_w;
wire [11:0] select_bias_out_w;
wire [3:0] sticky_bits;
wire underflow_w;
wire [10:0] underflow_zeros_w;
wire [11:0] value_add_one_w;
wire [11:0] value_normal_w;
wire [11:0] value_zero_w;
altsyncram altsyncram3
(
.address_a(datab[51:43]),
.clock0(clock),
.clocken0(clk_en),
.eccstatus(),
.q_a(wire_altsyncram3_q_a),
.q_b()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr0(1'b0),
.aclr1(1'b0),
.address_b({1{1'b1}}),
.addressstall_a(1'b0),
.addressstall_b(1'b0),
.byteena_a({1{1'b1}}),
.byteena_b({1{1'b1}}),
.clock1(1'b1),
.clocken1(1'b1),
.clocken2(1'b1),
.clocken3(1'b1),
.data_a({9{1'b1}}),
.data_b({1{1'b1}}),
.rden_a(1'b1),
.rden_b(1'b1),
.wren_a(1'b0),
.wren_b(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
altsyncram3.init_file = "acl_fp_div_double.hex",
altsyncram3.operation_mode = "ROM",
altsyncram3.width_a = 9,
altsyncram3.widthad_a = 9,
altsyncram3.intended_device_family = "Stratix IV",
altsyncram3.lpm_type = "altsyncram";
// synopsys translate_off
initial
a_is_infinity_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_0 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_0 <= a_is_infinity_w;
// synopsys translate_off
initial
a_is_infinity_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_1 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_1 <= a_is_infinity_dffe_0;
// synopsys translate_off
initial
a_is_infinity_dffe_10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_10 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_10 <= a_is_infinity_dffe_9;
// synopsys translate_off
initial
a_is_infinity_dffe_11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_11 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_11 <= a_is_infinity_dffe_10;
// synopsys translate_off
initial
a_is_infinity_dffe_12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_12 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_12 <= a_is_infinity_dffe_11;
// synopsys translate_off
initial
a_is_infinity_dffe_13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_13 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_13 <= a_is_infinity_dffe_12;
// synopsys translate_off
initial
a_is_infinity_dffe_14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_14 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_14 <= a_is_infinity_dffe_13;
// synopsys translate_off
initial
a_is_infinity_dffe_15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_15 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_15 <= a_is_infinity_dffe_14;
// synopsys translate_off
initial
a_is_infinity_dffe_16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_16 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_16 <= a_is_infinity_dffe_15;
// synopsys translate_off
initial
a_is_infinity_dffe_17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_17 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_17 <= a_is_infinity_dffe_16;
// synopsys translate_off
initial
a_is_infinity_dffe_18 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_18 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_18 <= a_is_infinity_dffe_17;
// synopsys translate_off
initial
a_is_infinity_dffe_19 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_19 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_19 <= a_is_infinity_dffe_18;
// synopsys translate_off
initial
a_is_infinity_dffe_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_2 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_2 <= a_is_infinity_dffe_1;
// synopsys translate_off
initial
a_is_infinity_dffe_20 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_20 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_20 <= a_is_infinity_dffe_19;
// synopsys translate_off
initial
a_is_infinity_dffe_21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_21 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_21 <= a_is_infinity_dffe_20;
// synopsys translate_off
initial
a_is_infinity_dffe_22 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_22 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_22 <= a_is_infinity_dffe_21;
// synopsys translate_off
initial
a_is_infinity_dffe_3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_3 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_3 <= a_is_infinity_dffe_2;
// synopsys translate_off
initial
a_is_infinity_dffe_4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_4 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_4 <= a_is_infinity_dffe_3;
// synopsys translate_off
initial
a_is_infinity_dffe_5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_5 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_5 <= a_is_infinity_dffe_4;
// synopsys translate_off
initial
a_is_infinity_dffe_6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_6 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_6 <= a_is_infinity_dffe_5;
// synopsys translate_off
initial
a_is_infinity_dffe_7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_7 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_7 <= a_is_infinity_dffe_6;
// synopsys translate_off
initial
a_is_infinity_dffe_8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_8 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_8 <= a_is_infinity_dffe_7;
// synopsys translate_off
initial
a_is_infinity_dffe_9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_9 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_9 <= a_is_infinity_dffe_8;
// synopsys translate_off
initial
a_zero_b_not_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_0 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_0 <= a_zero_b_not;
// synopsys translate_off
initial
a_zero_b_not_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_1 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_1 <= a_zero_b_not_dffe_0;
// synopsys translate_off
initial
a_zero_b_not_dffe_10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_10 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_10 <= a_zero_b_not_dffe_9;
// synopsys translate_off
initial
a_zero_b_not_dffe_11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_11 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_11 <= a_zero_b_not_dffe_10;
// synopsys translate_off
initial
a_zero_b_not_dffe_12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_12 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_12 <= a_zero_b_not_dffe_11;
// synopsys translate_off
initial
a_zero_b_not_dffe_13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_13 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_13 <= a_zero_b_not_dffe_12;
// synopsys translate_off
initial
a_zero_b_not_dffe_14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_14 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_14 <= a_zero_b_not_dffe_13;
// synopsys translate_off
initial
a_zero_b_not_dffe_15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_15 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_15 <= a_zero_b_not_dffe_14;
// synopsys translate_off
initial
a_zero_b_not_dffe_16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_16 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_16 <= a_zero_b_not_dffe_15;
// synopsys translate_off
initial
a_zero_b_not_dffe_17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_17 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_17 <= a_zero_b_not_dffe_16;
// synopsys translate_off
initial
a_zero_b_not_dffe_18 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_18 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_18 <= a_zero_b_not_dffe_17;
// synopsys translate_off
initial
a_zero_b_not_dffe_19 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_19 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_19 <= a_zero_b_not_dffe_18;
// synopsys translate_off
initial
a_zero_b_not_dffe_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_2 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_2 <= a_zero_b_not_dffe_1;
// synopsys translate_off
initial
a_zero_b_not_dffe_20 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_20 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_20 <= a_zero_b_not_dffe_19;
// synopsys translate_off
initial
a_zero_b_not_dffe_21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_21 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_21 <= a_zero_b_not_dffe_20;
// synopsys translate_off
initial
a_zero_b_not_dffe_22 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_22 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_22 <= a_zero_b_not_dffe_21;
// synopsys translate_off
initial
a_zero_b_not_dffe_3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_3 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_3 <= a_zero_b_not_dffe_2;
// synopsys translate_off
initial
a_zero_b_not_dffe_4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_4 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_4 <= a_zero_b_not_dffe_3;
// synopsys translate_off
initial
a_zero_b_not_dffe_5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_5 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_5 <= a_zero_b_not_dffe_4;
// synopsys translate_off
initial
a_zero_b_not_dffe_6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_6 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_6 <= a_zero_b_not_dffe_5;
// synopsys translate_off
initial
a_zero_b_not_dffe_7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_7 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_7 <= a_zero_b_not_dffe_6;
// synopsys translate_off
initial
a_zero_b_not_dffe_8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_8 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_8 <= a_zero_b_not_dffe_7;
// synopsys translate_off
initial
a_zero_b_not_dffe_9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_9 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_9 <= a_zero_b_not_dffe_8;
// synopsys translate_off
initial
b1_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b1_dffe_0 <= 63'b0;
else if (clk_en == 1'b1) b1_dffe_0 <= wire_b1_prod_result;
// synopsys translate_off
initial
b1_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b1_dffe_1 <= 63'b0;
else if (clk_en == 1'b1) b1_dffe_1 <= b1_dffe_0;
// synopsys translate_off
initial
b1_dffe_10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b1_dffe_10 <= 63'b0;
else if (clk_en == 1'b1) b1_dffe_10 <= b1_dffe_9;
// synopsys translate_off
initial
b1_dffe_11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b1_dffe_11 <= 63'b0;
else if (clk_en == 1'b1) b1_dffe_11 <= b1_dffe_10;
// synopsys translate_off
initial
b1_dffe_12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b1_dffe_12 <= 63'b0;
else if (clk_en == 1'b1) b1_dffe_12 <= b1_dffe_11;
// synopsys translate_off
initial
b1_dffe_13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b1_dffe_13 <= 63'b0;
else if (clk_en == 1'b1) b1_dffe_13 <= b1_dffe_12;
// synopsys translate_off
initial
b1_dffe_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b1_dffe_2 <= 63'b0;
else if (clk_en == 1'b1) b1_dffe_2 <= b1_dffe_1;
// synopsys translate_off
initial
b1_dffe_3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b1_dffe_3 <= 63'b0;
else if (clk_en == 1'b1) b1_dffe_3 <= b1_dffe_2;
// synopsys translate_off
initial
b1_dffe_4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b1_dffe_4 <= 63'b0;
else if (clk_en == 1'b1) b1_dffe_4 <= b1_dffe_3;
// synopsys translate_off
initial
b1_dffe_5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b1_dffe_5 <= 63'b0;
else if (clk_en == 1'b1) b1_dffe_5 <= b1_dffe_4;
// synopsys translate_off
initial
b1_dffe_6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b1_dffe_6 <= 63'b0;
else if (clk_en == 1'b1) b1_dffe_6 <= b1_dffe_5;
// synopsys translate_off
initial
b1_dffe_7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b1_dffe_7 <= 63'b0;
else if (clk_en == 1'b1) b1_dffe_7 <= b1_dffe_6;
// synopsys translate_off
initial
b1_dffe_8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b1_dffe_8 <= 63'b0;
else if (clk_en == 1'b1) b1_dffe_8 <= b1_dffe_7;
// synopsys translate_off
initial
b1_dffe_9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b1_dffe_9 <= 63'b0;
else if (clk_en == 1'b1) b1_dffe_9 <= b1_dffe_8;
// synopsys translate_off
initial
b_is_infinity_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_0 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_0 <= b_is_infinity_w;
// synopsys translate_off
initial
b_is_infinity_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_1 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_1 <= b_is_infinity_dffe_0;
// synopsys translate_off
initial
b_is_infinity_dffe_10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_10 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_10 <= b_is_infinity_dffe_9;
// synopsys translate_off
initial
b_is_infinity_dffe_11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_11 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_11 <= b_is_infinity_dffe_10;
// synopsys translate_off
initial
b_is_infinity_dffe_12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_12 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_12 <= b_is_infinity_dffe_11;
// synopsys translate_off
initial
b_is_infinity_dffe_13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_13 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_13 <= b_is_infinity_dffe_12;
// synopsys translate_off
initial
b_is_infinity_dffe_14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_14 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_14 <= b_is_infinity_dffe_13;
// synopsys translate_off
initial
b_is_infinity_dffe_15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_15 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_15 <= b_is_infinity_dffe_14;
// synopsys translate_off
initial
b_is_infinity_dffe_16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_16 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_16 <= b_is_infinity_dffe_15;
// synopsys translate_off
initial
b_is_infinity_dffe_17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_17 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_17 <= b_is_infinity_dffe_16;
// synopsys translate_off
initial
b_is_infinity_dffe_18 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_18 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_18 <= b_is_infinity_dffe_17;
// synopsys translate_off
initial
b_is_infinity_dffe_19 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_19 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_19 <= b_is_infinity_dffe_18;
// synopsys translate_off
initial
b_is_infinity_dffe_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_2 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_2 <= b_is_infinity_dffe_1;
// synopsys translate_off
initial
b_is_infinity_dffe_20 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_20 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_20 <= b_is_infinity_dffe_19;
// synopsys translate_off
initial
b_is_infinity_dffe_21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_21 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_21 <= b_is_infinity_dffe_20;
// synopsys translate_off
initial
b_is_infinity_dffe_22 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_22 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_22 <= b_is_infinity_dffe_21;
// synopsys translate_off
initial
b_is_infinity_dffe_3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_3 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_3 <= b_is_infinity_dffe_2;
// synopsys translate_off
initial
b_is_infinity_dffe_4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_4 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_4 <= b_is_infinity_dffe_3;
// synopsys translate_off
initial
b_is_infinity_dffe_5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_5 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_5 <= b_is_infinity_dffe_4;
// synopsys translate_off
initial
b_is_infinity_dffe_6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_6 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_6 <= b_is_infinity_dffe_5;
// synopsys translate_off
initial
b_is_infinity_dffe_7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_7 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_7 <= b_is_infinity_dffe_6;
// synopsys translate_off
initial
b_is_infinity_dffe_8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_8 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_8 <= b_is_infinity_dffe_7;
// synopsys translate_off
initial
b_is_infinity_dffe_9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_9 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_9 <= b_is_infinity_dffe_8;
// synopsys translate_off
initial
both_exp_zeros_dffe = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) both_exp_zeros_dffe <= 1'b0;
else if (clk_en == 1'b1) both_exp_zeros_dffe <= ((~ exp_b_not_zero_w[10]) & (~ exp_a_not_zero_w[10]));
// synopsys translate_off
initial
divbyzero_pipe_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_0 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_0 <= ((((~ exp_b_not_zero_w[10]) & (~ a_is_nan_w)) & exp_a_not_zero_w[10]) & (~ a_is_infinity_w));
// synopsys translate_off
initial
divbyzero_pipe_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_1 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_1 <= divbyzero_pipe_dffe_0;
// synopsys translate_off
initial
divbyzero_pipe_dffe_10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_10 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_10 <= divbyzero_pipe_dffe_9;
// synopsys translate_off
initial
divbyzero_pipe_dffe_11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_11 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_11 <= divbyzero_pipe_dffe_10;
// synopsys translate_off
initial
divbyzero_pipe_dffe_12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_12 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_12 <= divbyzero_pipe_dffe_11;
// synopsys translate_off
initial
divbyzero_pipe_dffe_13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_13 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_13 <= divbyzero_pipe_dffe_12;
// synopsys translate_off
initial
divbyzero_pipe_dffe_14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_14 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_14 <= divbyzero_pipe_dffe_13;
// synopsys translate_off
initial
divbyzero_pipe_dffe_15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_15 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_15 <= divbyzero_pipe_dffe_14;
// synopsys translate_off
initial
divbyzero_pipe_dffe_16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_16 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_16 <= divbyzero_pipe_dffe_15;
// synopsys translate_off
initial
divbyzero_pipe_dffe_17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_17 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_17 <= divbyzero_pipe_dffe_16;
// synopsys translate_off
initial
divbyzero_pipe_dffe_18 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_18 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_18 <= divbyzero_pipe_dffe_17;
// synopsys translate_off
initial
divbyzero_pipe_dffe_19 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_19 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_19 <= divbyzero_pipe_dffe_18;
// synopsys translate_off
initial
divbyzero_pipe_dffe_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_2 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_2 <= divbyzero_pipe_dffe_1;
// synopsys translate_off
initial
divbyzero_pipe_dffe_20 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_20 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_20 <= divbyzero_pipe_dffe_19;
// synopsys translate_off
initial
divbyzero_pipe_dffe_21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_21 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_21 <= divbyzero_pipe_dffe_20;
// synopsys translate_off
initial
divbyzero_pipe_dffe_22 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_22 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_22 <= divbyzero_pipe_dffe_21;
// synopsys translate_off
initial
divbyzero_pipe_dffe_3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_3 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_3 <= divbyzero_pipe_dffe_2;
// synopsys translate_off
initial
divbyzero_pipe_dffe_4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_4 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_4 <= divbyzero_pipe_dffe_3;
// synopsys translate_off
initial
divbyzero_pipe_dffe_5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_5 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_5 <= divbyzero_pipe_dffe_4;
// synopsys translate_off
initial
divbyzero_pipe_dffe_6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_6 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_6 <= divbyzero_pipe_dffe_5;
// synopsys translate_off
initial
divbyzero_pipe_dffe_7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_7 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_7 <= divbyzero_pipe_dffe_6;
// synopsys translate_off
initial
divbyzero_pipe_dffe_8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_8 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_8 <= divbyzero_pipe_dffe_7;
// synopsys translate_off
initial
divbyzero_pipe_dffe_9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_9 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_9 <= divbyzero_pipe_dffe_8;
// synopsys translate_off
initial
e1_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) e1_dffe_0 <= 17'b0;
else if (clk_en == 1'b1) e1_dffe_0 <= e1_w[16:0];
// synopsys translate_off
initial
e1_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) e1_dffe_1 <= 17'b0;
else if (clk_en == 1'b1) e1_dffe_1 <= e1_w[33:17];
// synopsys translate_off
initial
e1_dffe_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) e1_dffe_2 <= 17'b0;
else if (clk_en == 1'b1) e1_dffe_2 <= e1_w[50:34];
// synopsys translate_off
initial
e1_dffe_3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) e1_dffe_3 <= 17'b0;
else if (clk_en == 1'b1) e1_dffe_3 <= e1_w[67:51];
// synopsys translate_off
initial
e1_dffe_4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) e1_dffe_4 <= 17'b0;
else if (clk_en == 1'b1) e1_dffe_4 <= e1_w[84:68];
// synopsys translate_off
initial
e1_dffe_5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) e1_dffe_5 <= 17'b0;
else if (clk_en == 1'b1) e1_dffe_5 <= e1_w[101:85];
// synopsys translate_off
initial
e1_dffe_perf_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) e1_dffe_perf_0 <= 17'b0;
else if (clk_en == 1'b1) e1_dffe_perf_0 <= e1_dffe_0;
// synopsys translate_off
initial
e1_dffe_perf_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) e1_dffe_perf_1 <= 17'b0;
else if (clk_en == 1'b1) e1_dffe_perf_1 <= e1_dffe_perf_0;
// synopsys translate_off
initial
e1_dffe_perf_10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) e1_dffe_perf_10 <= 17'b0;
else if (clk_en == 1'b1) e1_dffe_perf_10 <= e1_dffe_perf_9;
// synopsys translate_off
initial
e1_dffe_perf_11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) e1_dffe_perf_11 <= 17'b0;
else if (clk_en == 1'b1) e1_dffe_perf_11 <= e1_dffe_perf_10;
// synopsys translate_off
initial
e1_dffe_perf_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) e1_dffe_perf_2 <= 17'b0;
else if (clk_en == 1'b1) e1_dffe_perf_2 <= e1_dffe_perf_1;
// synopsys translate_off
initial
e1_dffe_perf_3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) e1_dffe_perf_3 <= 17'b0;
else if (clk_en == 1'b1) e1_dffe_perf_3 <= e1_dffe_perf_2;
// synopsys translate_off
initial
e1_dffe_perf_4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) e1_dffe_perf_4 <= 17'b0;
else if (clk_en == 1'b1) e1_dffe_perf_4 <= e1_dffe_2;
// synopsys translate_off
initial
e1_dffe_perf_5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) e1_dffe_perf_5 <= 17'b0;
else if (clk_en == 1'b1) e1_dffe_perf_5 <= e1_dffe_perf_4;
// synopsys translate_off
initial
e1_dffe_perf_6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) e1_dffe_perf_6 <= 17'b0;
else if (clk_en == 1'b1) e1_dffe_perf_6 <= e1_dffe_perf_5;
// synopsys translate_off
initial
e1_dffe_perf_7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) e1_dffe_perf_7 <= 17'b0;
else if (clk_en == 1'b1) e1_dffe_perf_7 <= e1_dffe_perf_6;
// synopsys translate_off
initial
e1_dffe_perf_8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) e1_dffe_perf_8 <= 17'b0;
else if (clk_en == 1'b1) e1_dffe_perf_8 <= e1_dffe_4;
// synopsys translate_off
initial
e1_dffe_perf_9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) e1_dffe_perf_9 <= 17'b0;
else if (clk_en == 1'b1) e1_dffe_perf_9 <= e1_dffe_perf_8;
// synopsys translate_off
initial
exp_result_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_dffe_0 <= 11'b0;
else if (clk_en == 1'b1) exp_result_dffe_0 <= exp_result_mux_out;
// synopsys translate_off
initial
exp_result_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_dffe_1 <= 11'b0;
else if (clk_en == 1'b1) exp_result_dffe_1 <= exp_result_dffe_0;
// synopsys translate_off
initial
exp_result_dffe_10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_dffe_10 <= 11'b0;
else if (clk_en == 1'b1) exp_result_dffe_10 <= exp_result_dffe_9;
// synopsys translate_off
initial
exp_result_dffe_11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_dffe_11 <= 11'b0;
else if (clk_en == 1'b1) exp_result_dffe_11 <= exp_result_dffe_10;
// synopsys translate_off
initial
exp_result_dffe_12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_dffe_12 <= 11'b0;
else if (clk_en == 1'b1) exp_result_dffe_12 <= exp_result_dffe_11;
// synopsys translate_off
initial
exp_result_dffe_13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_dffe_13 <= 11'b0;
else if (clk_en == 1'b1) exp_result_dffe_13 <= exp_result_dffe_12;
// synopsys translate_off
initial
exp_result_dffe_14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_dffe_14 <= 11'b0;
else if (clk_en == 1'b1) exp_result_dffe_14 <= exp_result_dffe_13;
// synopsys translate_off
initial
exp_result_dffe_15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_dffe_15 <= 11'b0;
else if (clk_en == 1'b1) exp_result_dffe_15 <= exp_result_dffe_14;
// synopsys translate_off
initial
exp_result_dffe_16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_dffe_16 <= 11'b0;
else if (clk_en == 1'b1) exp_result_dffe_16 <= exp_result_dffe_15;
// synopsys translate_off
initial
exp_result_dffe_17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_dffe_17 <= 11'b0;
else if (clk_en == 1'b1) exp_result_dffe_17 <= exp_result_dffe_16;
// synopsys translate_off
initial
exp_result_dffe_18 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_dffe_18 <= 11'b0;
else if (clk_en == 1'b1) exp_result_dffe_18 <= exp_result_dffe_17;
// synopsys translate_off
initial
exp_result_dffe_19 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_dffe_19 <= 11'b0;
else if (clk_en == 1'b1) exp_result_dffe_19 <= exp_result_dffe_18;
// synopsys translate_off
initial
exp_result_dffe_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_dffe_2 <= 11'b0;
else if (clk_en == 1'b1) exp_result_dffe_2 <= exp_result_dffe_1;
// synopsys translate_off
initial
exp_result_dffe_20 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_dffe_20 <= 11'b0;
else if (clk_en == 1'b1) exp_result_dffe_20 <= exp_result_dffe_19;
// synopsys translate_off
initial
exp_result_dffe_21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_dffe_21 <= 11'b0;
else if (clk_en == 1'b1) exp_result_dffe_21 <= exp_result_dffe_20;
// synopsys translate_off
initial
exp_result_dffe_3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_dffe_3 <= 11'b0;
else if (clk_en == 1'b1) exp_result_dffe_3 <= exp_result_dffe_2;
// synopsys translate_off
initial
exp_result_dffe_4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_dffe_4 <= 11'b0;
else if (clk_en == 1'b1) exp_result_dffe_4 <= exp_result_dffe_3;
// synopsys translate_off
initial
exp_result_dffe_5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_dffe_5 <= 11'b0;
else if (clk_en == 1'b1) exp_result_dffe_5 <= exp_result_dffe_4;
// synopsys translate_off
initial
exp_result_dffe_6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_dffe_6 <= 11'b0;
else if (clk_en == 1'b1) exp_result_dffe_6 <= exp_result_dffe_5;
// synopsys translate_off
initial
exp_result_dffe_7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_dffe_7 <= 11'b0;
else if (clk_en == 1'b1) exp_result_dffe_7 <= exp_result_dffe_6;
// synopsys translate_off
initial
exp_result_dffe_8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_dffe_8 <= 11'b0;
else if (clk_en == 1'b1) exp_result_dffe_8 <= exp_result_dffe_7;
// synopsys translate_off
initial
exp_result_dffe_9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_dffe_9 <= 11'b0;
else if (clk_en == 1'b1) exp_result_dffe_9 <= exp_result_dffe_8;
// synopsys translate_off
initial
frac_a_smaller_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) frac_a_smaller_dffe1 <= 1'b0;
else if (clk_en == 1'b1) frac_a_smaller_dffe1 <= frac_a_smaller_dffe1_wi;
// synopsys translate_off
initial
man_a_dffe1_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_a_dffe1_dffe1 <= 52'b0;
else if (clk_en == 1'b1) man_a_dffe1_dffe1 <= man_a_dffe1_wi;
// synopsys translate_off
initial
man_b_dffe1_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_b_dffe1_dffe1 <= 52'b0;
else if (clk_en == 1'b1) man_b_dffe1_dffe1 <= man_b_dffe1_wi;
// synopsys translate_off
initial
man_result_dffe = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_result_dffe <= 52'b0;
else if (clk_en == 1'b1) man_result_dffe <= man_result_dffe_wi;
// synopsys translate_off
initial
nan_pipe_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_0 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_0 <= (((a_is_nan_w | b_is_nan_w) | (a_is_infinity_w & b_is_infinity_w)) | ((~ exp_a_not_zero_w[10]) & (~ exp_b_not_zero_w[10])));
// synopsys translate_off
initial
nan_pipe_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_1 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_1 <= nan_pipe_dffe_0;
// synopsys translate_off
initial
nan_pipe_dffe_10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_10 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_10 <= nan_pipe_dffe_9;
// synopsys translate_off
initial
nan_pipe_dffe_11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_11 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_11 <= nan_pipe_dffe_10;
// synopsys translate_off
initial
nan_pipe_dffe_12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_12 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_12 <= nan_pipe_dffe_11;
// synopsys translate_off
initial
nan_pipe_dffe_13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_13 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_13 <= nan_pipe_dffe_12;
// synopsys translate_off
initial
nan_pipe_dffe_14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_14 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_14 <= nan_pipe_dffe_13;
// synopsys translate_off
initial
nan_pipe_dffe_15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_15 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_15 <= nan_pipe_dffe_14;
// synopsys translate_off
initial
nan_pipe_dffe_16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_16 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_16 <= nan_pipe_dffe_15;
// synopsys translate_off
initial
nan_pipe_dffe_17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_17 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_17 <= nan_pipe_dffe_16;
// synopsys translate_off
initial
nan_pipe_dffe_18 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_18 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_18 <= nan_pipe_dffe_17;
// synopsys translate_off
initial
nan_pipe_dffe_19 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_19 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_19 <= nan_pipe_dffe_18;
// synopsys translate_off
initial
nan_pipe_dffe_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_2 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_2 <= nan_pipe_dffe_1;
// synopsys translate_off
initial
nan_pipe_dffe_20 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_20 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_20 <= nan_pipe_dffe_19;
// synopsys translate_off
initial
nan_pipe_dffe_21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_21 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_21 <= nan_pipe_dffe_20;
// synopsys translate_off
initial
nan_pipe_dffe_22 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_22 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_22 <= nan_pipe_dffe_21;
// synopsys translate_off
initial
nan_pipe_dffe_3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_3 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_3 <= nan_pipe_dffe_2;
// synopsys translate_off
initial
nan_pipe_dffe_4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_4 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_4 <= nan_pipe_dffe_3;
// synopsys translate_off
initial
nan_pipe_dffe_5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_5 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_5 <= nan_pipe_dffe_4;
// synopsys translate_off
initial
nan_pipe_dffe_6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_6 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_6 <= nan_pipe_dffe_5;
// synopsys translate_off
initial
nan_pipe_dffe_7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_7 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_7 <= nan_pipe_dffe_6;
// synopsys translate_off
initial
nan_pipe_dffe_8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_8 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_8 <= nan_pipe_dffe_7;
// synopsys translate_off
initial
nan_pipe_dffe_9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_9 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_9 <= nan_pipe_dffe_8;
// synopsys translate_off
initial
over_under_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) over_under_dffe_0 <= 1'b0;
else if (clk_en == 1'b1) over_under_dffe_0 <= overflow_underflow;
// synopsys translate_off
initial
over_under_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) over_under_dffe_1 <= 1'b0;
else if (clk_en == 1'b1) over_under_dffe_1 <= over_under_dffe_0;
// synopsys translate_off
initial
over_under_dffe_10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) over_under_dffe_10 <= 1'b0;
else if (clk_en == 1'b1) over_under_dffe_10 <= over_under_dffe_9;
// synopsys translate_off
initial
over_under_dffe_11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) over_under_dffe_11 <= 1'b0;
else if (clk_en == 1'b1) over_under_dffe_11 <= over_under_dffe_10;
// synopsys translate_off
initial
over_under_dffe_12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) over_under_dffe_12 <= 1'b0;
else if (clk_en == 1'b1) over_under_dffe_12 <= over_under_dffe_11;
// synopsys translate_off
initial
over_under_dffe_13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) over_under_dffe_13 <= 1'b0;
else if (clk_en == 1'b1) over_under_dffe_13 <= over_under_dffe_12;
// synopsys translate_off
initial
over_under_dffe_14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) over_under_dffe_14 <= 1'b0;
else if (clk_en == 1'b1) over_under_dffe_14 <= over_under_dffe_13;
// synopsys translate_off
initial
over_under_dffe_15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) over_under_dffe_15 <= 1'b0;
else if (clk_en == 1'b1) over_under_dffe_15 <= over_under_dffe_14;
// synopsys translate_off
initial
over_under_dffe_16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) over_under_dffe_16 <= 1'b0;
else if (clk_en == 1'b1) over_under_dffe_16 <= over_under_dffe_15;
// synopsys translate_off
initial
over_under_dffe_17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) over_under_dffe_17 <= 1'b0;
else if (clk_en == 1'b1) over_under_dffe_17 <= over_under_dffe_16;
// synopsys translate_off
initial
over_under_dffe_18 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) over_under_dffe_18 <= 1'b0;
else if (clk_en == 1'b1) over_under_dffe_18 <= over_under_dffe_17;
// synopsys translate_off
initial
over_under_dffe_19 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) over_under_dffe_19 <= 1'b0;
else if (clk_en == 1'b1) over_under_dffe_19 <= over_under_dffe_18;
// synopsys translate_off
initial
over_under_dffe_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) over_under_dffe_2 <= 1'b0;
else if (clk_en == 1'b1) over_under_dffe_2 <= over_under_dffe_1;
// synopsys translate_off
initial
over_under_dffe_20 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) over_under_dffe_20 <= 1'b0;
else if (clk_en == 1'b1) over_under_dffe_20 <= over_under_dffe_19;
// synopsys translate_off
initial
over_under_dffe_3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) over_under_dffe_3 <= 1'b0;
else if (clk_en == 1'b1) over_under_dffe_3 <= over_under_dffe_2;
// synopsys translate_off
initial
over_under_dffe_4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) over_under_dffe_4 <= 1'b0;
else if (clk_en == 1'b1) over_under_dffe_4 <= over_under_dffe_3;
// synopsys translate_off
initial
over_under_dffe_5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) over_under_dffe_5 <= 1'b0;
else if (clk_en == 1'b1) over_under_dffe_5 <= over_under_dffe_4;
// synopsys translate_off
initial
over_under_dffe_6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) over_under_dffe_6 <= 1'b0;
else if (clk_en == 1'b1) over_under_dffe_6 <= over_under_dffe_5;
// synopsys translate_off
initial
over_under_dffe_7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) over_under_dffe_7 <= 1'b0;
else if (clk_en == 1'b1) over_under_dffe_7 <= over_under_dffe_6;
// synopsys translate_off
initial
over_under_dffe_8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) over_under_dffe_8 <= 1'b0;
else if (clk_en == 1'b1) over_under_dffe_8 <= over_under_dffe_7;
// synopsys translate_off
initial
over_under_dffe_9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) over_under_dffe_9 <= 1'b0;
else if (clk_en == 1'b1) over_under_dffe_9 <= over_under_dffe_8;
// synopsys translate_off
initial
q_partial_perf_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_partial_perf_dffe_0 <= 34'b0;
else if (clk_en == 1'b1) q_partial_perf_dffe_0 <= wire_q_partial_0_result;
// synopsys translate_off
initial
q_partial_perf_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_partial_perf_dffe_1 <= 34'b0;
else if (clk_en == 1'b1) q_partial_perf_dffe_1 <= wire_q_partial_1_result;
// synopsys translate_off
initial
q_partial_perf_dffe_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_partial_perf_dffe_2 <= 34'b0;
else if (clk_en == 1'b1) q_partial_perf_dffe_2 <= wire_q_partial_2_result;
// synopsys translate_off
initial
q_partial_perf_dffe_3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_partial_perf_dffe_3 <= 34'b0;
else if (clk_en == 1'b1) q_partial_perf_dffe_3 <= wire_q_partial_3_result;
// synopsys translate_off
initial
quotient_j_dffe = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) quotient_j_dffe <= 17'b0;
else if (clk_en == 1'b1) quotient_j_dffe <= q_partial_perf_dffe_0[32:16];
// synopsys translate_off
initial
quotient_k_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) quotient_k_dffe_0 <= 17'b0;
else if (clk_en == 1'b1) quotient_k_dffe_0 <= quotient_k_dffe_perf_3;
// synopsys translate_off
initial
quotient_k_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) quotient_k_dffe_1 <= 31'b0;
else if (clk_en == 1'b1) quotient_k_dffe_1 <= quotient_k_dffe_perf_7;
// synopsys translate_off
initial
quotient_k_dffe_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) quotient_k_dffe_2 <= 45'b0;
else if (clk_en == 1'b1) quotient_k_dffe_2 <= quotient_k_dffe_perf_11;
// synopsys translate_off
initial
quotient_k_dffe_perf_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) quotient_k_dffe_perf_0 <= 17'b0;
else if (clk_en == 1'b1) quotient_k_dffe_perf_0 <= quotient_accumulate_w[58:42];
// synopsys translate_off
initial
quotient_k_dffe_perf_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) quotient_k_dffe_perf_1 <= 17'b0;
else if (clk_en == 1'b1) quotient_k_dffe_perf_1 <= quotient_k_dffe_perf_0;
// synopsys translate_off
initial
quotient_k_dffe_perf_10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) quotient_k_dffe_perf_10 <= 45'b0;
else if (clk_en == 1'b1) quotient_k_dffe_perf_10 <= quotient_k_dffe_perf_9;
// synopsys translate_off
initial
quotient_k_dffe_perf_11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) quotient_k_dffe_perf_11 <= 45'b0;
else if (clk_en == 1'b1) quotient_k_dffe_perf_11 <= quotient_k_dffe_perf_10;
// synopsys translate_off
initial
quotient_k_dffe_perf_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) quotient_k_dffe_perf_2 <= 17'b0;
else if (clk_en == 1'b1) quotient_k_dffe_perf_2 <= quotient_k_dffe_perf_1;
// synopsys translate_off
initial
quotient_k_dffe_perf_3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) quotient_k_dffe_perf_3 <= 17'b0;
else if (clk_en == 1'b1) quotient_k_dffe_perf_3 <= quotient_k_dffe_perf_2;
// synopsys translate_off
initial
quotient_k_dffe_perf_4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) quotient_k_dffe_perf_4 <= 31'b0;
else if (clk_en == 1'b1) quotient_k_dffe_perf_4 <= wire_quotient_accumulate_0_result;
// synopsys translate_off
initial
quotient_k_dffe_perf_5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) quotient_k_dffe_perf_5 <= 31'b0;
else if (clk_en == 1'b1) quotient_k_dffe_perf_5 <= quotient_k_dffe_perf_4;
// synopsys translate_off
initial
quotient_k_dffe_perf_6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) quotient_k_dffe_perf_6 <= 31'b0;
else if (clk_en == 1'b1) quotient_k_dffe_perf_6 <= quotient_k_dffe_perf_5;
// synopsys translate_off
initial
quotient_k_dffe_perf_7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) quotient_k_dffe_perf_7 <= 31'b0;
else if (clk_en == 1'b1) quotient_k_dffe_perf_7 <= quotient_k_dffe_perf_6;
// synopsys translate_off
initial
quotient_k_dffe_perf_8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) quotient_k_dffe_perf_8 <= 45'b0;
else if (clk_en == 1'b1) quotient_k_dffe_perf_8 <= wire_quotient_accumulate_1_result;
// synopsys translate_off
initial
quotient_k_dffe_perf_9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) quotient_k_dffe_perf_9 <= 45'b0;
else if (clk_en == 1'b1) quotient_k_dffe_perf_9 <= quotient_k_dffe_perf_8;
// synopsys translate_off
initial
remainder_j_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) remainder_j_dffe_0 <= 79'b0;
else if (clk_en == 1'b1) remainder_j_dffe_0 <= remainder_j_w[78:0];
// synopsys translate_off
initial
remainder_j_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) remainder_j_dffe_1 <= 79'b0;
else if (clk_en == 1'b1) remainder_j_dffe_1 <= remainder_j_dffe_perf_2;
// synopsys translate_off
initial
remainder_j_dffe_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) remainder_j_dffe_2 <= 79'b0;
else if (clk_en == 1'b1) remainder_j_dffe_2 <= remainder_j_w[157:79];
// synopsys translate_off
initial
remainder_j_dffe_3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) remainder_j_dffe_3 <= 79'b0;
else if (clk_en == 1'b1) remainder_j_dffe_3 <= remainder_j_dffe_perf_5;
// synopsys translate_off
initial
remainder_j_dffe_4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) remainder_j_dffe_4 <= 79'b0;
else if (clk_en == 1'b1) remainder_j_dffe_4 <= remainder_j_w[236:158];
// synopsys translate_off
initial
remainder_j_dffe_5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) remainder_j_dffe_5 <= 79'b0;
else if (clk_en == 1'b1) remainder_j_dffe_5 <= remainder_j_dffe_perf_8;
// synopsys translate_off
initial
remainder_j_dffe_perf_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) remainder_j_dffe_perf_0 <= 79'b0;
else if (clk_en == 1'b1) remainder_j_dffe_perf_0 <= remainder_j_dffe_0;
// synopsys translate_off
initial
remainder_j_dffe_perf_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) remainder_j_dffe_perf_1 <= 79'b0;
else if (clk_en == 1'b1) remainder_j_dffe_perf_1 <= remainder_j_dffe_perf_0;
// synopsys translate_off
initial
remainder_j_dffe_perf_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) remainder_j_dffe_perf_2 <= 79'b0;
else if (clk_en == 1'b1) remainder_j_dffe_perf_2 <= remainder_j_dffe_perf_1;
// synopsys translate_off
initial
remainder_j_dffe_perf_3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) remainder_j_dffe_perf_3 <= 79'b0;
else if (clk_en == 1'b1) remainder_j_dffe_perf_3 <= remainder_j_dffe_2;
// synopsys translate_off
initial
remainder_j_dffe_perf_4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) remainder_j_dffe_perf_4 <= 79'b0;
else if (clk_en == 1'b1) remainder_j_dffe_perf_4 <= remainder_j_dffe_perf_3;
// synopsys translate_off
initial
remainder_j_dffe_perf_5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) remainder_j_dffe_perf_5 <= 79'b0;
else if (clk_en == 1'b1) remainder_j_dffe_perf_5 <= remainder_j_dffe_perf_4;
// synopsys translate_off
initial
remainder_j_dffe_perf_6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) remainder_j_dffe_perf_6 <= 79'b0;
else if (clk_en == 1'b1) remainder_j_dffe_perf_6 <= remainder_j_dffe_4;
// synopsys translate_off
initial
remainder_j_dffe_perf_7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) remainder_j_dffe_perf_7 <= 79'b0;
else if (clk_en == 1'b1) remainder_j_dffe_perf_7 <= remainder_j_dffe_perf_6;
// synopsys translate_off
initial
remainder_j_dffe_perf_8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) remainder_j_dffe_perf_8 <= 79'b0;
else if (clk_en == 1'b1) remainder_j_dffe_perf_8 <= remainder_j_dffe_perf_7;
// synopsys translate_off
initial
sign_pipe_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_0 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_0 <= (dataa[63] ^ datab[63]);
// synopsys translate_off
initial
sign_pipe_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_1 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_1 <= sign_pipe_dffe_0;
// synopsys translate_off
initial
sign_pipe_dffe_10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_10 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_10 <= sign_pipe_dffe_9;
// synopsys translate_off
initial
sign_pipe_dffe_11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_11 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_11 <= sign_pipe_dffe_10;
// synopsys translate_off
initial
sign_pipe_dffe_12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_12 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_12 <= sign_pipe_dffe_11;
// synopsys translate_off
initial
sign_pipe_dffe_13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_13 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_13 <= sign_pipe_dffe_12;
// synopsys translate_off
initial
sign_pipe_dffe_14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_14 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_14 <= sign_pipe_dffe_13;
// synopsys translate_off
initial
sign_pipe_dffe_15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_15 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_15 <= sign_pipe_dffe_14;
// synopsys translate_off
initial
sign_pipe_dffe_16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_16 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_16 <= sign_pipe_dffe_15;
// synopsys translate_off
initial
sign_pipe_dffe_17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_17 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_17 <= sign_pipe_dffe_16;
// synopsys translate_off
initial
sign_pipe_dffe_18 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_18 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_18 <= sign_pipe_dffe_17;
// synopsys translate_off
initial
sign_pipe_dffe_19 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_19 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_19 <= sign_pipe_dffe_18;
// synopsys translate_off
initial
sign_pipe_dffe_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_2 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_2 <= sign_pipe_dffe_1;
// synopsys translate_off
initial
sign_pipe_dffe_20 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_20 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_20 <= sign_pipe_dffe_19;
// synopsys translate_off
initial
sign_pipe_dffe_21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_21 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_21 <= sign_pipe_dffe_20;
// synopsys translate_off
initial
sign_pipe_dffe_22 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_22 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_22 <= sign_pipe_dffe_21;
// synopsys translate_off
initial
sign_pipe_dffe_23 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_23 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_23 <= sign_pipe_dffe_22;
// synopsys translate_off
initial
sign_pipe_dffe_3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_3 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_3 <= sign_pipe_dffe_2;
// synopsys translate_off
initial
sign_pipe_dffe_4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_4 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_4 <= sign_pipe_dffe_3;
// synopsys translate_off
initial
sign_pipe_dffe_5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_5 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_5 <= sign_pipe_dffe_4;
// synopsys translate_off
initial
sign_pipe_dffe_6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_6 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_6 <= sign_pipe_dffe_5;
// synopsys translate_off
initial
sign_pipe_dffe_7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_7 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_7 <= sign_pipe_dffe_6;
// synopsys translate_off
initial
sign_pipe_dffe_8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_8 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_8 <= sign_pipe_dffe_7;
// synopsys translate_off
initial
sign_pipe_dffe_9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_9 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_9 <= sign_pipe_dffe_8;
lpm_add_sub bias_addition
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.cout(),
.dataa(exp_sub_w),
.datab(select_bias_out_2_w),
.overflow(wire_bias_addition_overflow),
.result(wire_bias_addition_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
bias_addition.lpm_direction = "ADD",
bias_addition.lpm_pipeline = 1,
bias_addition.lpm_representation = "SIGNED",
bias_addition.lpm_width = 12,
bias_addition.lpm_type = "lpm_add_sub";
lpm_add_sub exp_sub
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.cout(),
.dataa(exp_sub_a_w),
.datab(exp_sub_b_w),
.overflow(),
.result(wire_exp_sub_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
exp_sub.lpm_direction = "SUB",
exp_sub.lpm_pipeline = 1,
exp_sub.lpm_representation = "SIGNED",
exp_sub.lpm_width = 12,
exp_sub.lpm_type = "lpm_add_sub";
lpm_add_sub quotient_accumulate_0
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.cout(),
.dataa({quotient_accumulate_w[117:101], {14{1'b0}}}),
.datab({{14{1'b0}}, q_partial_perf_dffe_1[32:16]}),
.overflow(),
.result(wire_quotient_accumulate_0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
quotient_accumulate_0.lpm_direction = "ADD",
quotient_accumulate_0.lpm_pipeline = 1,
quotient_accumulate_0.lpm_representation = "UNSIGNED",
quotient_accumulate_0.lpm_width = 31,
quotient_accumulate_0.lpm_type = "lpm_add_sub";
lpm_add_sub quotient_accumulate_1
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.cout(),
.dataa({quotient_accumulate_w[176:146], {14{1'b0}}}),
.datab({{28{1'b0}}, q_partial_perf_dffe_2[32:16]}),
.overflow(),
.result(wire_quotient_accumulate_1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
quotient_accumulate_1.lpm_direction = "ADD",
quotient_accumulate_1.lpm_pipeline = 1,
quotient_accumulate_1.lpm_representation = "UNSIGNED",
quotient_accumulate_1.lpm_width = 45,
quotient_accumulate_1.lpm_type = "lpm_add_sub";
lpm_add_sub quotient_process
(
.cin(quotient_process_cin_w),
.cout(),
.dataa({quotient_accumulate_w[235:191], {14{1'b0}}}),
.datab({{42{1'b0}}, q_partial_perf_dffe_3[32:21], {5{1'b1}}}),
.overflow(),
.result(wire_quotient_process_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
quotient_process.lpm_direction = "ADD",
quotient_process.lpm_representation = "UNSIGNED",
quotient_process.lpm_width = 59,
quotient_process.lpm_type = "lpm_add_sub";
lpm_add_sub remainder_sub_0
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.cout(),
.dataa({remainder_j_dffe_1[78:15], {15{1'b0}}}),
.datab(wire_remainder_mult_0_result[78:0]),
.overflow(),
.result(wire_remainder_sub_0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
remainder_sub_0.lpm_direction = "SUB",
remainder_sub_0.lpm_pipeline = 1,
remainder_sub_0.lpm_representation = "UNSIGNED",
remainder_sub_0.lpm_width = 79,
remainder_sub_0.lpm_type = "lpm_add_sub";
lpm_add_sub remainder_sub_1
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.cout(),
.dataa({remainder_j_dffe_3[78:15], {15{1'b0}}}),
.datab(wire_remainder_mult_1_result[78:0]),
.overflow(),
.result(wire_remainder_sub_1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
remainder_sub_1.lpm_direction = "SUB",
remainder_sub_1.lpm_pipeline = 1,
remainder_sub_1.lpm_representation = "UNSIGNED",
remainder_sub_1.lpm_width = 79,
remainder_sub_1.lpm_type = "lpm_add_sub";
lpm_add_sub remainder_sub_2
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.cout(),
.dataa({remainder_j_dffe_5[78:15], {15{1'b0}}}),
.datab(wire_remainder_mult_2_result[78:0]),
.overflow(),
.result(wire_remainder_sub_2_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
remainder_sub_2.lpm_direction = "SUB",
remainder_sub_2.lpm_pipeline = 1,
remainder_sub_2.lpm_representation = "UNSIGNED",
remainder_sub_2.lpm_width = 79,
remainder_sub_2.lpm_type = "lpm_add_sub";
lpm_compare cmpr2
(
.aeb(),
.agb(),
.ageb(),
.alb(wire_cmpr2_alb),
.aleb(),
.aneb(),
.dataa(dataa[51:0]),
.datab(datab[51:0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
cmpr2.lpm_representation = "UNSIGNED",
cmpr2.lpm_width = 52,
cmpr2.lpm_type = "lpm_compare";
lpm_mult a1_prod
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(man_a_adjusted_w),
.datab({1'b1, e0_dffe1_wo}),
.result(wire_a1_prod_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
a1_prod.lpm_pipeline = 2,
a1_prod.lpm_representation = "UNSIGNED",
a1_prod.lpm_widtha = 54,
a1_prod.lpm_widthb = 10,
a1_prod.lpm_widthp = 64,
a1_prod.lpm_type = "lpm_mult",
a1_prod.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES";
lpm_mult b1_prod
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(man_b_adjusted_w),
.datab({1'b1, e0_dffe1_wo}),
.result(wire_b1_prod_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
b1_prod.lpm_pipeline = 2,
b1_prod.lpm_representation = "UNSIGNED",
b1_prod.lpm_widtha = 53,
b1_prod.lpm_widthb = 10,
b1_prod.lpm_widthp = 63,
b1_prod.lpm_type = "lpm_mult",
b1_prod.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES";
lpm_mult q_partial_0
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(remainder_j_w[78:62]),
.datab(e1_w[16:0]),
.result(wire_q_partial_0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
q_partial_0.lpm_pipeline = 1,
q_partial_0.lpm_representation = "UNSIGNED",
q_partial_0.lpm_widtha = 17,
q_partial_0.lpm_widthb = 17,
q_partial_0.lpm_widthp = 34,
q_partial_0.lpm_type = "lpm_mult",
q_partial_0.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES";
lpm_mult q_partial_1
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(remainder_j_w[157:141]),
.datab(e1_w[50:34]),
.result(wire_q_partial_1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
q_partial_1.lpm_pipeline = 1,
q_partial_1.lpm_representation = "UNSIGNED",
q_partial_1.lpm_widtha = 17,
q_partial_1.lpm_widthb = 17,
q_partial_1.lpm_widthp = 34,
q_partial_1.lpm_type = "lpm_mult",
q_partial_1.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES";
lpm_mult q_partial_2
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(remainder_j_w[236:220]),
.datab(e1_w[84:68]),
.result(wire_q_partial_2_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
q_partial_2.lpm_pipeline = 1,
q_partial_2.lpm_representation = "UNSIGNED",
q_partial_2.lpm_widtha = 17,
q_partial_2.lpm_widthb = 17,
q_partial_2.lpm_widthp = 34,
q_partial_2.lpm_type = "lpm_mult",
q_partial_2.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES";
lpm_mult q_partial_3
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(remainder_j_w[315:299]),
.datab(e1_w[118:102]),
.result(wire_q_partial_3_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
q_partial_3.lpm_pipeline = 1,
q_partial_3.lpm_representation = "UNSIGNED",
q_partial_3.lpm_widtha = 17,
q_partial_3.lpm_widthb = 17,
q_partial_3.lpm_widthp = 34,
q_partial_3.lpm_type = "lpm_mult",
q_partial_3.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES";
lpm_mult remainder_mult_0
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(b1_dffe_w[62:0]),
.datab(q_partial_perf_dffe_0[32:16]),
.result(wire_remainder_mult_0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
remainder_mult_0.lpm_pipeline = 3,
remainder_mult_0.lpm_representation = "UNSIGNED",
remainder_mult_0.lpm_widtha = 63,
remainder_mult_0.lpm_widthb = 17,
remainder_mult_0.lpm_widthp = 80,
remainder_mult_0.lpm_type = "lpm_mult",
remainder_mult_0.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES";
lpm_mult remainder_mult_1
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(b1_dffe_w[125:63]),
.datab(q_partial_perf_dffe_1[32:16]),
.result(wire_remainder_mult_1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
remainder_mult_1.lpm_pipeline = 3,
remainder_mult_1.lpm_representation = "UNSIGNED",
remainder_mult_1.lpm_widtha = 63,
remainder_mult_1.lpm_widthb = 17,
remainder_mult_1.lpm_widthp = 80,
remainder_mult_1.lpm_type = "lpm_mult",
remainder_mult_1.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES";
lpm_mult remainder_mult_2
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(b1_dffe_w[188:126]),
.datab(q_partial_perf_dffe_2[32:16]),
.result(wire_remainder_mult_2_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
remainder_mult_2.lpm_pipeline = 3,
remainder_mult_2.lpm_representation = "UNSIGNED",
remainder_mult_2.lpm_widtha = 63,
remainder_mult_2.lpm_widthb = 17,
remainder_mult_2.lpm_widthp = 80,
remainder_mult_2.lpm_type = "lpm_mult",
remainder_mult_2.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES";
assign wire_exp_result_muxa_dataout = (exp_result_mux_sel_w === 1'b1) ? underflow_zeros_w : exp_result_w;
assign wire_man_a_adjusteda_dataout = (frac_a_smaller_dffe1_wo === 1'b1) ? {1'b1, man_a_dffe1_wo, 1'b0} : {1'b0, 1'b1, man_a_dffe1_wo};
assign wire_man_result_muxa_dataout = (man_result_mux_select === 1'b1) ? {nan_pipe_dffe_22, man_zeros_w[50:0]} : wire_quotient_process_result[56:5];
assign wire_select_bias_2a_dataout = (both_exp_zeros === 1'b1) ? value_zero_w : select_bias_out_w;
assign wire_select_biasa_dataout = (frac_a_smaller_dffe1_wo === 1'b1) ? value_normal_w : value_add_one_w;
assign
a_is_infinity_w = (exp_a_all_one_w[10] & (~ man_a_not_zero_w[51])),
a_is_nan_w = (exp_a_all_one_w[10] & man_a_not_zero_w[51]),
a_zero_b_not = (exp_b_not_zero_w[10] & (~ exp_a_not_zero_w[10])),
b1_dffe_w = {b1_dffe_13, b1_dffe_7, b1_dffe_1},
b_is_infinity_w = (exp_b_all_one_w[10] & (~ man_b_not_zero_w[51])),
b_is_nan_w = (exp_b_all_one_w[10] & man_b_not_zero_w[51]),
bias_addition_overf_w = wire_bias_addition_overflow,
bias_addition_w = wire_bias_addition_result[10:0],
both_exp_zeros = both_exp_zeros_dffe,
e0_dffe1_wo = e0_w,
e0_w = wire_altsyncram3_q_a,
e1_w = {e1_dffe_5, e1_dffe_perf_11, e1_dffe_3, e1_dffe_perf_7, e1_dffe_1, e1_dffe_perf_3, (~ wire_b1_prod_result[62:46])},
exp_a_all_one_w = {(dataa[62] & exp_a_all_one_w[9]), (dataa[61] & exp_a_all_one_w[8]), (dataa[60] & exp_a_all_one_w[7]), (dataa[59] & exp_a_all_one_w[6]), (dataa[58] & exp_a_all_one_w[5]), (dataa[57] & exp_a_all_one_w[4]), (dataa[56] & exp_a_all_one_w[3]), (dataa[55] & exp_a_all_one_w[2]), (dataa[54] & exp_a_all_one_w[1]), (dataa[53] & exp_a_all_one_w[0]), dataa[52]},
exp_a_not_zero_w = {(dataa[62] | exp_a_not_zero_w[9]), (dataa[61] | exp_a_not_zero_w[8]), (dataa[60] | exp_a_not_zero_w[7]), (dataa[59] | exp_a_not_zero_w[6]), (dataa[58] | exp_a_not_zero_w[5]), (dataa[57] | exp_a_not_zero_w[4]), (dataa[56] | exp_a_not_zero_w[3]), (dataa[55] | exp_a_not_zero_w[2]), (dataa[54] | exp_a_not_zero_w[1]), (dataa[53] | exp_a_not_zero_w[0]), dataa[52]},
exp_add_output_all_one = {(bias_addition_w[10] & exp_add_output_all_one[9]), (bias_addition_w[9] & exp_add_output_all_one[8]), (bias_addition_w[8] & exp_add_output_all_one[7]), (bias_addition_w[7] & exp_add_output_all_one[6]), (bias_addition_w[6] & exp_add_output_all_one[5]), (bias_addition_w[5] & exp_add_output_all_one[4]), (bias_addition_w[4] & exp_add_output_all_one[3]), (bias_addition_w[3] & exp_add_output_all_one[2]), (bias_addition_w[2] & exp_add_output_all_one[1]), (bias_addition_w[1] & exp_add_output_all_one[0]), bias_addition_w[0]},
exp_add_output_not_zero = {(bias_addition_w[10] | exp_add_output_not_zero[9]), (bias_addition_w[9] | exp_add_output_not_zero[8]), (bias_addition_w[8] | exp_add_output_not_zero[7]), (bias_addition_w[7] | exp_add_output_not_zero[6]), (bias_addition_w[6] | exp_add_output_not_zero[5]), (bias_addition_w[5] | exp_add_output_not_zero[4]), (bias_addition_w[4] | exp_add_output_not_zero[3]), (bias_addition_w[3] | exp_add_output_not_zero[2]), (bias_addition_w[2] | exp_add_output_not_zero[1]), (bias_addition_w[1] | exp_add_output_not_zero[0]), bias_addition_w[0]},
exp_b_all_one_w = {(datab[62] & exp_b_all_one_w[9]), (datab[61] & exp_b_all_one_w[8]), (datab[60] & exp_b_all_one_w[7]), (datab[59] & exp_b_all_one_w[6]), (datab[58] & exp_b_all_one_w[5]), (datab[57] & exp_b_all_one_w[4]), (datab[56] & exp_b_all_one_w[3]), (datab[55] & exp_b_all_one_w[2]), (datab[54] & exp_b_all_one_w[1]), (datab[53] & exp_b_all_one_w[0]), datab[52]},
exp_b_not_zero_w = {(datab[62] | exp_b_not_zero_w[9]), (datab[61] | exp_b_not_zero_w[8]), (datab[60] | exp_b_not_zero_w[7]), (datab[59] | exp_b_not_zero_w[6]), (datab[58] | exp_b_not_zero_w[5]), (datab[57] | exp_b_not_zero_w[4]), (datab[56] | exp_b_not_zero_w[3]), (datab[55] | exp_b_not_zero_w[2]), (datab[54] | exp_b_not_zero_w[1]), (datab[53] | exp_b_not_zero_w[0]), datab[52]},
exp_result_mux_out = wire_exp_result_muxa_dataout,
exp_result_mux_sel_w = ((((a_zero_b_not_dffe_1 | b_is_infinity_dffe_1) | ((~ bias_addition_overf_w) & exp_sign_w)) | (((~ exp_add_output_not_zero[10]) & (~ bias_addition_overf_w)) & (~ exp_sign_w))) & (~ nan_pipe_dffe_1)),
exp_result_w = (({11{((~ bias_addition_overf_w) & (~ exp_sign_w))}} & bias_addition_w) | ({11{(((bias_addition_overf_w | divbyzero_pipe_dffe_1) | nan_pipe_dffe_1) | a_is_infinity_dffe_1)}} & overflow_ones_w)),
exp_sign_w = wire_bias_addition_result[11],
exp_sub_a_w = {1'b0, dataa[62:52]},
exp_sub_b_w = {1'b0, datab[62:52]},
exp_sub_w = wire_exp_sub_result,
frac_a_smaller_dffe1_wi = frac_a_smaller_w,
frac_a_smaller_dffe1_wo = frac_a_smaller_dffe1,
frac_a_smaller_w = wire_cmpr2_alb,
guard_bit = q_partial_perf_dffe_3[21],
man_a_adjusted_w = wire_man_a_adjusteda_dataout,
man_a_dffe1_wi = dataa[51:0],
man_a_dffe1_wo = man_a_dffe1_dffe1,
man_a_not_zero_w = {(dataa[51] | man_a_not_zero_w[50]), (dataa[50] | man_a_not_zero_w[49]), (dataa[49] | man_a_not_zero_w[48]), (dataa[48] | man_a_not_zero_w[47]), (dataa[47] | man_a_not_zero_w[46]), (dataa[46] | man_a_not_zero_w[45]), (dataa[45] | man_a_not_zero_w[44]), (dataa[44] | man_a_not_zero_w[43]), (dataa[43] | man_a_not_zero_w[42]), (dataa[42] | man_a_not_zero_w[41]), (dataa[41] | man_a_not_zero_w[40]), (dataa[40] | man_a_not_zero_w[39]), (dataa[39] | man_a_not_zero_w[38]), (dataa[38] | man_a_not_zero_w[37]), (dataa[37] | man_a_not_zero_w[36]), (dataa[36] | man_a_not_zero_w[35]), (dataa[35] | man_a_not_zero_w[34]), (dataa[34] | man_a_not_zero_w[33]), (dataa[33] | man_a_not_zero_w[32]), (dataa[32] | man_a_not_zero_w[31]), (dataa[31] | man_a_not_zero_w[30]), (dataa[30] | man_a_not_zero_w[29]), (dataa[29] | man_a_not_zero_w[28]), (dataa[28] | man_a_not_zero_w[27]), (dataa[27] | man_a_not_zero_w[26]), (dataa[26] | man_a_not_zero_w[25]), (dataa[25] | man_a_not_zero_w[24]), (dataa[24] | man_a_not_zero_w[23]), (dataa[23] | man_a_not_zero_w[22]), (dataa[22] | man_a_not_zero_w[21]), (dataa[21] | man_a_not_zero_w[20]), (dataa[20] | man_a_not_zero_w[19]), (dataa[19] | man_a_not_zero_w[18]), (dataa[18] | man_a_not_zero_w[17]), (dataa[17] | man_a_not_zero_w[16]), (dataa[16] | man_a_not_zero_w[15]), (dataa[15] | man_a_not_zero_w[14]), (dataa[14] | man_a_not_zero_w[13]), (dataa[13] | man_a_not_zero_w[12]), (dataa[12] | man_a_not_zero_w[11]), (dataa[11] | man_a_not_zero_w[10]), (dataa[10] | man_a_not_zero_w[9]), (dataa[9] | man_a_not_zero_w[8]), (dataa[8] | man_a_not_zero_w[7]), (dataa[7] | man_a_not_zero_w[6]), (dataa[6] | man_a_not_zero_w[5]), (dataa[5] | man_a_not_zero_w[4]), (dataa[4] | man_a_not_zero_w[3]), (dataa[3] | man_a_not_zero_w[2]), (dataa[2] | man_a_not_zero_w[1]), (dataa[1] | man_a_not_zero_w[0]), dataa[0]},
man_b_adjusted_w = {1'b1, man_b_dffe1_wo},
man_b_dffe1_wi = datab[51:0],
man_b_dffe1_wo = man_b_dffe1_dffe1,
man_b_not_zero_w = {(datab[51] | man_b_not_zero_w[50]), (datab[50] | man_b_not_zero_w[49]), (datab[49] | man_b_not_zero_w[48]), (datab[48] | man_b_not_zero_w[47]), (datab[47] | man_b_not_zero_w[46]), (datab[46] | man_b_not_zero_w[45]), (datab[45] | man_b_not_zero_w[44]), (datab[44] | man_b_not_zero_w[43]), (datab[43] | man_b_not_zero_w[42]), (datab[42] | man_b_not_zero_w[41]), (datab[41] | man_b_not_zero_w[40]), (datab[40] | man_b_not_zero_w[39]), (datab[39] | man_b_not_zero_w[38]), (datab[38] | man_b_not_zero_w[37]), (datab[37] | man_b_not_zero_w[36]), (datab[36] | man_b_not_zero_w[35]), (datab[35] | man_b_not_zero_w[34]), (datab[34] | man_b_not_zero_w[33]), (datab[33] | man_b_not_zero_w[32]), (datab[32] | man_b_not_zero_w[31]), (datab[31] | man_b_not_zero_w[30]), (datab[30] | man_b_not_zero_w[29]), (datab[29] | man_b_not_zero_w[28]), (datab[28] | man_b_not_zero_w[27]), (datab[27] | man_b_not_zero_w[26]), (datab[26] | man_b_not_zero_w[25]), (datab[25] | man_b_not_zero_w[24]), (datab[24] | man_b_not_zero_w[23]), (datab[23] | man_b_not_zero_w[22]), (datab[22] | man_b_not_zero_w[21]), (datab[21] | man_b_not_zero_w[20]), (datab[20] | man_b_not_zero_w[19]), (datab[19] | man_b_not_zero_w[18]), (datab[18] | man_b_not_zero_w[17]), (datab[17] | man_b_not_zero_w[16]), (datab[16] | man_b_not_zero_w[15]), (datab[15] | man_b_not_zero_w[14]), (datab[14] | man_b_not_zero_w[13]), (datab[13] | man_b_not_zero_w[12]), (datab[12] | man_b_not_zero_w[11]), (datab[11] | man_b_not_zero_w[10]), (datab[10] | man_b_not_zero_w[9]), (datab[9] | man_b_not_zero_w[8]), (datab[8] | man_b_not_zero_w[7]), (datab[7] | man_b_not_zero_w[6]), (datab[6] | man_b_not_zero_w[5]), (datab[5] | man_b_not_zero_w[4]), (datab[4] | man_b_not_zero_w[3]), (datab[3] | man_b_not_zero_w[2]), (datab[2] | man_b_not_zero_w[1]), (datab[1] | man_b_not_zero_w[0]), datab[0]},
man_result_dffe_wi = man_result_w,
man_result_dffe_wo = man_result_dffe,
man_result_mux_select = (((((over_under_dffe_20 | a_zero_b_not_dffe_22) | nan_pipe_dffe_22) | b_is_infinity_dffe_22) | a_is_infinity_dffe_22) | divbyzero_pipe_dffe_22),
man_result_w = wire_man_result_muxa_dataout,
man_zeros_w = {52{1'b0}},
overflow_ones_w = {11{1'b1}},
overflow_underflow = (overflow_w | underflow_w),
overflow_w = ((bias_addition_overf_w | ((exp_add_output_all_one[10] & (~ bias_addition_overf_w)) & (~ exp_sign_w))) & (((~ nan_pipe_dffe_1) & (~ a_is_infinity_dffe_1)) & (~ divbyzero_pipe_dffe_1))),
quotient_accumulate_w = {quotient_k_dffe_2, {14{1'b0}}, quotient_k_dffe_1, {28{1'b0}}, quotient_k_dffe_0, {42{1'b0}}, quotient_j_dffe, {42{1'b0}}},
quotient_process_cin_w = (round_bit & (guard_bit | sticky_bits[3])),
remainder_j_w = {wire_remainder_sub_2_result[64:0], {14{1'b0}}, wire_remainder_sub_1_result[64:0], {14{1'b0}}, wire_remainder_sub_0_result[64:0], {14{1'b0}}, wire_a1_prod_result[63:0], {15{1'b0}}},
result = {sign_pipe_dffe_23, exp_result_dffe_21, man_result_dffe_wo},
round_bit = q_partial_perf_dffe_3[20],
select_bias_out_2_w = wire_select_bias_2a_dataout,
select_bias_out_w = wire_select_biasa_dataout,
sticky_bits = {(q_partial_perf_dffe_3[19] | sticky_bits[2]), (q_partial_perf_dffe_3[18] | sticky_bits[1]), (q_partial_perf_dffe_3[17] | sticky_bits[0]), q_partial_perf_dffe_3[16]},
underflow_w = ((((((~ bias_addition_overf_w) & exp_sign_w) | (((~ exp_add_output_not_zero[10]) & (~ bias_addition_overf_w)) & (~ exp_sign_w))) & (~ nan_pipe_dffe_1)) & (~ a_zero_b_not_dffe_1)) & (~ b_is_infinity_dffe_1)),
underflow_zeros_w = {11{1'b0}},
value_add_one_w = 12'b001111111111,
value_normal_w = 12'b001111111110,
value_zero_w = {12{1'b0}};
endmodule //acl_fp_div_double_altfp_div_pst_npf
//synthesis_resources = altsyncram 1 lpm_add_sub 8 lpm_compare 1 lpm_mult 9 mux21 141 reg 3551
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_div_double_altfp_div_f0i
(
clk_en,
clock,
dataa,
datab,
result) ;
input clk_en;
input clock;
input [63:0] dataa;
input [63:0] datab;
output [63:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clk_en;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [63:0] wire_altfp_div_pst1_result;
wire aclr;
acl_fp_div_double_altfp_div_pst_npf altfp_div_pst1
(
.aclr(aclr),
.clk_en(clk_en),
.clock(clock),
.dataa(dataa),
.datab(datab),
.result(wire_altfp_div_pst1_result));
assign
aclr = 1'b0,
result = wire_altfp_div_pst1_result;
endmodule //acl_fp_div_double_altfp_div_f0i
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module acl_fp_div_double (
enable,
clock,
dataa,
datab,
result);
input enable;
input clock;
input [63:0] dataa;
input [63:0] datab;
output [63:0] result;
wire [63:0] sub_wire0;
wire [63:0] result = sub_wire0[63:0];
acl_fp_div_double_altfp_div_f0i acl_fp_div_double_altfp_div_f0i_component (
.clk_en (enable),
.clock (clock),
.datab (datab),
.dataa (dataa),
.result (sub_wire0));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: DENORMAL_SUPPORT STRING "NO"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: OPTIMIZE STRING "SPEED"
// Retrieval info: CONSTANT: PIPELINE NUMERIC "24"
// Retrieval info: CONSTANT: REDUCED_FUNCTIONALITY STRING "NO"
// Retrieval info: CONSTANT: WIDTH_EXP NUMERIC "11"
// Retrieval info: CONSTANT: WIDTH_MAN NUMERIC "52"
// Retrieval info: USED_PORT: clk_en 0 0 0 0 INPUT NODEFVAL "clk_en"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: dataa 0 0 64 0 INPUT NODEFVAL "dataa[63..0]"
// Retrieval info: USED_PORT: datab 0 0 64 0 INPUT NODEFVAL "datab[63..0]"
// Retrieval info: USED_PORT: result 0 0 64 0 OUTPUT NODEFVAL "result[63..0]"
// Retrieval info: CONNECT: @clk_en 0 0 0 0 clk_en 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @dataa 0 0 64 0 dataa 0 0 64 0
// Retrieval info: CONNECT: @datab 0 0 64 0 datab 0 0 64 0
// Retrieval info: CONNECT: result 0 0 64 0 @result 0 0 64 0
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_div_double.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_div_double.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_div_double.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_div_double.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_div_double_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_div_double_bb.v TRUE
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module vfabric_up_converter(clock, resetn, i_start,
i_datain, i_datain_valid, o_datain_stall,
o_dataout, i_dataout_stall, o_dataout_valid);
parameter DATAIN_WIDTH = 8;
parameter DATAOUT_WIDTH = 32;
input clock, resetn, i_start;
input [DATAIN_WIDTH-1:0] i_datain;
input i_datain_valid;
output o_datain_stall;
output [DATAOUT_WIDTH-1:0] o_dataout;
input i_dataout_stall;
output o_dataout_valid;
// Specify state machine states.
parameter s_IDLE = 2'b00;
parameter s_RECEIVED_B1 = 2'b01;
parameter s_RECEIVED_B2 = 2'b10;
parameter s_RECEIVED_B3 = 2'b11;
// State and next_state variables
reg [1:0] present_state, next_state;
reg [DATAOUT_WIDTH-1:0] data_received;
// Simple state machine to store 1 byte per cycle, for 4 cycles,
// then output it downstream
always@(*)
begin
case (present_state)
s_IDLE: if (i_datain_valid)
next_state <= s_RECEIVED_B1;
else
next_state <= s_IDLE;
s_RECEIVED_B1: if (i_datain_valid)
next_state <= s_RECEIVED_B2;
else
next_state <= s_RECEIVED_B1;
s_RECEIVED_B2: if (i_datain_valid)
next_state <= s_RECEIVED_B3;
else
next_state <= s_RECEIVED_B2;
s_RECEIVED_B3: if (i_datain_valid)
next_state <= s_IDLE;
else
next_state <= s_RECEIVED_B3;
default: next_state <= 3'bxxx;
endcase
end
// Simple state machine to save 1 byte per cycle
always@(posedge clock or negedge resetn)
begin
if (~resetn)
data_received <= {DATAOUT_WIDTH{1'b0}};
else
begin
if ((present_state == s_IDLE) & i_datain_valid)
data_received <= {data_received[4*DATAIN_WIDTH-1:DATAIN_WIDTH], i_datain};
else if ((present_state == s_RECEIVED_B1) & i_datain_valid)
data_received <= {data_received[4*DATAIN_WIDTH-1:2*DATAIN_WIDTH], i_datain, data_received[DATAIN_WIDTH-1:0] };
else if ((present_state == s_RECEIVED_B2) & i_datain_valid)
data_received <= {data_received[4*DATAIN_WIDTH-1:3*DATAIN_WIDTH], i_datain, data_received[2*DATAIN_WIDTH-1:0] };
else if ((present_state == s_RECEIVED_B3) & i_datain_valid)
data_received <= {i_datain, data_received[3*DATAIN_WIDTH-1:0] };
else
data_received <= data_received;
end
end
always@(posedge clock or negedge resetn)
begin
if (~resetn)
o_dataout_valid <= 1'b0;
else
begin
o_dataout_valid <= (present_state == s_RECEIVED_B3) & i_datain_valid;
end
end
// State assignment
always@(posedge clock or negedge resetn)
begin
if (~resetn)
present_state <= s_IDLE;
else
present_state <= (i_start) ? next_state : s_IDLE;
end
assign o_dataout = data_received;
assign o_datain_stall = (i_start) ? i_dataout_stall : 1'b0;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSDRIVERNOVLP_BEHAVIORAL_V
`define SKY130_FD_SC_LP__BUSDRIVERNOVLP_BEHAVIORAL_V
/**
* busdrivernovlp: Bus driver, enable gates pulldown only (pmoshvt
* devices).
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__busdrivernovlp (
Z ,
A ,
TE_B
);
// Module ports
output Z ;
input A ;
input TE_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Name Output Other arguments
bufif0 bufif00 (Z , A, TE_B );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSDRIVERNOVLP_BEHAVIORAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A32O_LP_V
`define SKY130_FD_SC_LP__A32O_LP_V
/**
* a32o: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input OR.
*
* X = ((A1 & A2 & A3) | (B1 & B2))
*
* Verilog wrapper for a32o with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a32o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a32o_lp (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a32o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a32o_lp (
X ,
A1,
A2,
A3,
B1,
B2
);
output X ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a32o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A32O_LP_V
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : ecc_buf.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v2_3_ecc_buf
#(
parameter TCQ = 100,
parameter PAYLOAD_WIDTH = 64,
parameter DATA_BUF_ADDR_WIDTH = 4,
parameter DATA_BUF_OFFSET_WIDTH = 1,
parameter DATA_WIDTH = 64,
parameter nCK_PER_CLK = 4
)
(
/*AUTOARG*/
// Outputs
rd_merge_data,
// Inputs
clk, rst, rd_data_addr, rd_data_offset, wr_data_addr,
wr_data_offset, rd_data, wr_ecc_buf
);
input clk;
input rst;
// RMW architecture supports only 16 data buffer entries.
// Allow DATA_BUF_ADDR_WIDTH to be greater than 4, but
// assume the upper bits are used for tagging.
input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr;
input [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset;
wire [4:0] buf_wr_addr;
input [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr;
input [DATA_BUF_OFFSET_WIDTH-1:0] wr_data_offset;
reg [4:0] buf_rd_addr_r;
generate
if (DATA_BUF_ADDR_WIDTH >= 4) begin : ge_4_addr_bits
always @(posedge clk)
buf_rd_addr_r <= #TCQ{wr_data_addr[3:0], wr_data_offset};
assign buf_wr_addr = {rd_data_addr[3:0], rd_data_offset};
end
else begin : lt_4_addr_bits
always @(posedge clk)
buf_rd_addr_r <= #TCQ{{4-DATA_BUF_ADDR_WIDTH{1'b0}},
wr_data_addr[DATA_BUF_ADDR_WIDTH-1:0],
wr_data_offset};
assign buf_wr_addr = {{4-DATA_BUF_ADDR_WIDTH{1'b0}},
rd_data_addr[DATA_BUF_ADDR_WIDTH-1:0],
rd_data_offset};
end
endgenerate
input [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] rd_data;
reg [2*nCK_PER_CLK*DATA_WIDTH-1:0] payload;
integer h;
always @(/*AS*/rd_data)
for (h=0; h<2*nCK_PER_CLK; h=h+1)
payload[h*DATA_WIDTH+:DATA_WIDTH] =
rd_data[h*PAYLOAD_WIDTH+:DATA_WIDTH];
input wr_ecc_buf;
localparam BUF_WIDTH = 2*nCK_PER_CLK*DATA_WIDTH;
localparam FULL_RAM_CNT = (BUF_WIDTH/6);
localparam REMAINDER = BUF_WIDTH % 6;
localparam RAM_CNT = FULL_RAM_CNT + ((REMAINDER == 0 ) ? 0 : 1);
localparam RAM_WIDTH = (RAM_CNT*6);
wire [RAM_WIDTH-1:0] buf_out_data;
generate
begin : ram_buf
wire [RAM_WIDTH-1:0] buf_in_data;
if (REMAINDER == 0)
assign buf_in_data = payload;
else
assign buf_in_data = {{6-REMAINDER{1'b0}}, payload};
genvar i;
for (i=0; i<RAM_CNT; i=i+1) begin : rd_buffer_ram
RAM32M
#(.INIT_A(64'h0000000000000000),
.INIT_B(64'h0000000000000000),
.INIT_C(64'h0000000000000000),
.INIT_D(64'h0000000000000000)
) RAM32M0 (
.DOA(buf_out_data[((i*6)+4)+:2]),
.DOB(buf_out_data[((i*6)+2)+:2]),
.DOC(buf_out_data[((i*6)+0)+:2]),
.DOD(),
.DIA(buf_in_data[((i*6)+4)+:2]),
.DIB(buf_in_data[((i*6)+2)+:2]),
.DIC(buf_in_data[((i*6)+0)+:2]),
.DID(2'b0),
.ADDRA(buf_rd_addr_r),
.ADDRB(buf_rd_addr_r),
.ADDRC(buf_rd_addr_r),
.ADDRD(buf_wr_addr),
.WE(wr_ecc_buf),
.WCLK(clk)
);
end // block: rd_buffer_ram
end
endgenerate
output wire [2*nCK_PER_CLK*DATA_WIDTH-1:0] rd_merge_data;
assign rd_merge_data = buf_out_data[2*nCK_PER_CLK*DATA_WIDTH-1:0];
endmodule
|
// This top level module chooses between the original Altera-ST JTAG Interface
// component in ACDS version 8.1 and before, and the new one with the PLI
// Simulation mode turned on, which adds a wrapper over the original component.
`timescale 1 ns / 1 ns
module altera_avalon_st_jtag_interface (
clk,
reset_n,
source_ready,
source_data,
source_valid,
sink_data,
sink_valid,
sink_ready,
resetrequest,
debug_reset,
mgmt_valid,
mgmt_channel,
mgmt_data
);
input clk;
input reset_n;
output [7:0] source_data;
input source_ready;
output source_valid;
input [7:0] sink_data;
input sink_valid;
output sink_ready;
output resetrequest;
output debug_reset;
output mgmt_valid;
output mgmt_data;
parameter PURPOSE = 0; // for discovery of services behind this JTAG Phy - 0
// for JTAG Phy, 1 for Packets to Master
parameter UPSTREAM_FIFO_SIZE = 0;
parameter DOWNSTREAM_FIFO_SIZE = 0;
parameter MGMT_CHANNEL_WIDTH = -1;
parameter USE_PLI = 0; // set to 1 enable PLI Simulation Mode
parameter PLI_PORT = 50000; // PLI Simulation Port
output [(MGMT_CHANNEL_WIDTH>0?MGMT_CHANNEL_WIDTH:1)-1:0] mgmt_channel;
wire clk;
wire resetrequest;
wire [7:0] source_data;
wire source_ready;
wire source_valid;
wire [7:0] sink_data;
wire sink_valid;
wire sink_ready;
generate
if (USE_PLI == 0)
begin : normal
altera_jtag_dc_streaming #(
.PURPOSE(PURPOSE),
.UPSTREAM_FIFO_SIZE(UPSTREAM_FIFO_SIZE),
.DOWNSTREAM_FIFO_SIZE(DOWNSTREAM_FIFO_SIZE),
.MGMT_CHANNEL_WIDTH(MGMT_CHANNEL_WIDTH)
) jtag_dc_streaming (
.clk(clk),
.reset_n(reset_n),
.source_data(source_data),
.source_valid(source_valid),
.sink_data(sink_data),
.sink_valid(sink_valid),
.sink_ready(sink_ready),
.resetrequest(resetrequest),
.debug_reset(debug_reset),
.mgmt_valid(mgmt_valid),
.mgmt_channel(mgmt_channel),
.mgmt_data(mgmt_data)
);
end
else
begin : pli_mode
altera_pli_streaming #(.PURPOSE(PURPOSE), .PLI_PORT(PLI_PORT)) pli_streaming (
.clk(clk),
.reset_n(reset_n),
.source_data(source_data),
.source_valid(source_valid),
.source_ready(source_ready),
.sink_data(sink_data),
.sink_valid(sink_valid),
.sink_ready(sink_ready),
.resetrequest(resetrequest)
);
end
endgenerate
endmodule
|
// TOOL: vlog2tf
// DATE: Tue May 13 00:00:57 2014
// TITLE: Lattice Semiconductor Corporation
// MODULE: Lolhi
// DESIGN: Lolhi
// FILENAME: Lolhi_tf.v
// PROJECT: Unknown
// VERSION: 2.0
// This file is auto generated by the Diamond
`timescale 1 ns / 1 ns
// Define Module for Test Fixture
module Lolhi_tf();
// Inputs
reg A;
reg B;
reg C;
reg AnalogLDir;
reg AnalogRDir;
// Outputs
wire Len;
wire Ldir;
wire Ren;
wire Rdir;
// Bidirs
// Instantiate the UUT
// Please check and add your parameters manually
Lolhi UUT (
.A(A),
.B(B),
.C(C),
.AnalogLDir(AnalogLDir),
.AnalogRDir(AnalogRDir),
.Len(Len),
.Ldir(Ldir),
.Ren(Ren),
.Rdir(Rdir)
);
// Initialize Inputs
// You can add your stimulus here
initial begin
A = 0; B = 0; C = 0; AnalogLDir = 0; AnalogRDir = 0;
#10 A = 0; B = 0; C = 0; AnalogLDir = 0; AnalogRDir = 1;
#10 A = 0; B = 0; C = 0; AnalogLDir = 1; AnalogRDir = 0;
#10 A = 0; B = 0; C = 0; AnalogLDir = 1; AnalogRDir = 1;
#10 A = 0; B = 0; C = 1; AnalogLDir = 1; AnalogRDir = 1;
#10 A = 0; B = 1; C = 0; AnalogLDir = 1; AnalogRDir = 1;
#10 A = 0; B = 1; C = 1; AnalogLDir = 1; AnalogRDir = 1;
#10 A = 1; B = 0; C = 0; AnalogLDir = 1; AnalogRDir = 1;
#10 A = 1; B = 0; C = 1; AnalogLDir = 1; AnalogRDir = 1;
#10 A = 1; B = 1; C = 0; AnalogLDir = 1; AnalogRDir = 1;
#10 A = 1; B = 1; C = 1; AnalogLDir = 1; AnalogRDir = 1;
end
endmodule // Lolhi_tf |
/*+--------------------------------------------------------------------------
Copyright (c) 2015, Microsoft Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
//////////////////////////////////////////////////////////////////////////////////
// Company: Microsoft Research Asia
// Engineer: Jiansong Zhang
//
// Create Date: 21:39:39 06/01/2009
// Design Name:
// Module Name: tx_trn_sm
// Project Name: Sora
// Target Devices: Virtex5 LX50T
// Tool versions: ISE10.1.03
// Description:
// Purpose: Transmit TRN State Machine module. Interfaces to the Endpoint
// Block Plus and transmits packtets out of the TRN interface. Drains the
// packets out of FIFOs.
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// Modified by jiansong zhang, 2009-6-18
// (1) delete dma write done generation logic -------------- done
// (2) modification on scheduling
// (3) register/memory read logic -------------------------- done
//
// semiduplex scheduling to slove possible interlock problem on
// north-bridge/memory-controller
// (1) add np_tx_cnt logic --------------------------------- done
// (2) add np_rx_cnt input
// (3) scheduling: if ( (np_tx_cnt == np_rx_cnt) && (p_hdr_fifo != empty) )
// send p packets;
// else if (np_hdr_fifo != empty)
// send np packets;
// else if (cmp_hdr_fifo != empty)
// send cmp packets;
// else
// IDLE;
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
`include "Sora_config.v"
module tx_trn_sm(
input clk,
input rst_in,
input hostreset_in,
output rst_out,
//interface to the header fifos
input [63:0] posted_hdr_fifo,
output posted_hdr_fifo_rden,
input posted_hdr_fifo_empty,
input [63:0] nonposted_hdr_fifo,
output nonposted_hdr_fifo_rden,
input nonposted_hdr_fifo_empty,
input [63:0] comp_hdr_fifo,
input comp_hdr_fifo_empty,
output comp_hdr_fifo_rden,
/// Jiansong: posted_data_fifo interface
output reg posted_data_fifo_rden,
input [63:0] posted_data_fifo_data,
// it's used, data fifo should not be empty when it is read
input posted_data_fifo_empty,
/// Jiansong: interface for Mrd, connect to dma control wrapper, don't need request/ack handshake
output reg[11:0] Mrd_data_addr, /// Jiansong: 12 bits register address
input [31:0] Mrd_data_in,
//interface to PCIe Endpoint Block Plus TX TRN
output reg [63:0] trn_td,
output reg [7:0] trn_trem_n,
output reg trn_tsof_n,
output reg trn_teof_n,
output trn_tsrc_rdy_n,
output trn_tsrc_dsc_n,
input trn_tdst_rdy_n,//if this signal is deasserted (high) must pause all
//activity to the TX TRN interface. This signal is
//used as a clock enable to much of the circuitry
//in this module
input trn_tdst_dsc_n,//destination should not discontinue - Endpoint Block
//Plus V1.6.1 does not support this signal
output trn_terrfwd_n,
input [2:0] trn_tbuf_av,
/// Jiansong: input from rx_monitor
input [9:0] np_rx_cnt_qw,
input transferstart,
input Wait_for_TX_desc,
input rd_dma_start, //indicates the start of a read dma xfer
input [12:3] dmarxs, //size of the complete transfer
// debug interface
output reg [31:0] Debug21RX2,
output reg [31:0] Debug25RX6
);
//state machine state definitions for state[19:0]
localparam IDLE = 21'b0_0000_0000_0000_0000_0000;
localparam GET_P_HD = 21'b0_0000_0000_0000_0000_0001;
localparam GET_NP_HD = 21'b0_0000_0000_0000_0000_0010;
localparam GET_COMP_HD = 21'b0_0000_0000_0000_0000_0100;
localparam SETUP_P_DATA = 21'b0_0000_0000_0000_0000_1000;
//// localparam WAIT_FOR_DATA_RDY = 20'b0000_0000_0000_0010_0000;
localparam P_WAIT_STATE = 21'b0_0000_0000_0000_0001_0000;
localparam P_WAIT_STATE1 = 21'b0_0000_0000_0000_0010_0000;
localparam HD1_P_XFER = 21'b0_0000_0000_0000_0100_0000;
localparam HD2_P_XFER = 21'b0_0000_0000_0000_1000_0000;
localparam DATA_P_XFER = 21'b0_0000_0000_0001_0000_0000;
localparam LAST_P_XFER = 21'b0_0000_0000_0010_0000_0000;
localparam SETUP_NP = 21'b0_0000_0000_0100_0000_0000;
localparam SETUP_COMP_DATA = 21'b0_0000_0000_1000_0000_0000;
localparam SETUP_COMP_DATA_WAIT1 = 21'b0_0000_0001_0000_0000_0000;
localparam SETUP_COMP_DATA_WAIT2 = 21'b0_0000_0010_0000_0000_0000;
localparam HD1_NP_XFER = 21'b0_0000_0100_0000_0000_0000;
localparam HD2_NP_XFER = 21'b0_0000_1000_0000_0000_0000;
localparam NP_WAIT_STATE = 21'b0_0001_0000_0000_0000_0000;
localparam WAIT_FOR_COMP_DATA_RDY = 21'b0_0010_0000_0000_0000_0000;
localparam HD1_COMP_XFER = 21'b0_0100_0000_0000_0000_0000;
localparam HD2_COMP_XFER = 21'b0_1000_0000_0000_0000_0000;
localparam NP_XFER_WAIT = 21'b1_0000_0000_0000_0000_0000;
//states for addsub_state
localparam AS_IDLE = 2'b00;
localparam REGISTER_CALC = 2'b01;
localparam WAIT_FOR_REG = 2'b10;
reg [1:0] addsub_state;
//header fifo signals
reg read_posted_header_fifo, read_posted_header_fifo_d1,
read_posted_header_fifo_d2;
reg read_non_posted_header_fifo, read_non_posted_header_fifo_d1,
read_non_posted_header_fifo_d2;
reg read_comp_header_fifo, read_comp_header_fifo_d1,
read_comp_header_fifo_d2;
wire p_trn_fifo_rdy, np_trn_fifo_rdy;
//holding registers for TLP headers
reg [63:0] p_hd1, p_hd2; //posted headers 1 and 2
reg [63:0] np_hd1, np_hd2; //non-posted headers 1 and 2
reg [63:0] comp_hd1, comp_hd2; //completer headers 1 and 2
//datapath registers
reg [31:0] data_reg;
reg [9:0] length_countdown;
wire [63:0] data_swap;
/// Jiansong: swap register data
wire [31:0] Mrd_data_swap;
//decoded TLP signals - mainly used for code comprehension
wire [1:0] p_fmt;
wire [2:0] p_tc;
wire [9:0] p_length;
wire [1:0] np_fmt;
wire [2:0] np_tc;
wire [9:0] np_length;
////reg p_hd_valid; /// Jiansong: no longer needed
//main state machine signals
reg [20:0] state;
////reg posted; //asserted when the state machine is in the posted flow
//// //used to qualify the data_stall signal as a CE for many of
//// //the blocks that aren't related to the DDR2
reg [1:0] data_src_mux;
reg trn_tsrc_rdy_n_reg;
reg [3:0] priority_count = 4'b1111;
wire posted_priority;
/// Jiansong: pipeline register for a complicated problem when trn_tdst_rdy_n is asserted
reg trn_tdst_rdy_n_r2;
reg [63:0] data_reg_tdst_problem;
reg trn_tdst_rdy_n_r;
reg rst_reg;
/// Jiansong: non_posted_length_counter
reg add_calc = 0;
reg sub_calc = 0;
reg add_complete;
reg sub_complete;
reg [9:0] np_tx_cnt_qw;
reg [9:0] np_tx_cnt_qw_new;
reg [9:0] np_tx_cnt_qw_add;
reg update_np_tx_cnt_qw;
reg stay_2x;
/// Jiansong:
wire rd_dma_start_one;
reg rd_dma_start_reg;
rising_edge_detect rd_dma_start_one_inst(
.clk(clk),
.rst(rst_reg),
.in(rd_dma_start_reg),
.one_shot_out(rd_dma_start_one)
);
//pipe line register for timing purposes
always@(posedge clk)
rd_dma_start_reg <= rd_dma_start;
`ifdef sora_simulation
always@(posedge clk) rst_reg <= rst_in;
`else
always@(posedge clk) begin
if(state == IDLE)
rst_reg <= rst_in | hostreset_in;
else
rst_reg <= 1'b0;
end
`endif
assign rst_out = rst_reg;
// debug register
always@(posedge clk)begin
Debug21RX2[19:0] <= state[19:0];
Debug21RX2[29:20] <= length_countdown[9:0];
Debug21RX2[31:30] <= 2'b00;
end
always@(posedge clk)begin
if (rst_reg)
Debug25RX6 <= 32'h0000_0000;
else if (posted_data_fifo_rden)
Debug25RX6 <= Debug25RX6 + 32'h0000_0001;
else
Debug25RX6 <= Debug25RX6;
end
//tie off to pcie trn tx
assign trn_tsrc_dsc_n = 1'b1; /// Jiansong: transmit source discontinue
assign trn_terrfwd_n = 1'b1; /// Jiansong: error?
//if there is a data_stall need to pause the TX TRN interface
////assign trn_tsrc_rdy_n = (data_stall & posted) | trn_tsrc_rdy_n_reg;
assign trn_tsrc_rdy_n = trn_tsrc_rdy_n_reg;
/// Jiansong: need modification? big-endian for 64 bit data? Don't modify
// swap byte ordering of data to big-endian per PCIe Base spec
////assign data_swap[63:0] = {data[7:0],data[15:8],
//// data[23:16],data[31:24],
//// data[39:32],data[47:40],
//// data[55:48],data[63:56]};
assign data_swap[63:0] = {posted_data_fifo_data[7:0],posted_data_fifo_data[15:8],
posted_data_fifo_data[23:16],posted_data_fifo_data[31:24],
posted_data_fifo_data[39:32],posted_data_fifo_data[47:40],
posted_data_fifo_data[55:48],posted_data_fifo_data[63:56]};
////assign data_swap[63:0] = {posted_data_fifo_data[39:32],posted_data_fifo_data[47:40],
//// posted_data_fifo_data[55:48],posted_data_fifo_data[63:56],
//// posted_data_fifo_data[7:0],posted_data_fifo_data[15:8],
//// posted_data_fifo_data[23:16],posted_data_fifo_data[31:24]};
/// Jiansong: swap register read / memory read data
assign Mrd_data_swap[31:0] = {Mrd_data_in[7:0],Mrd_data_in[15:8],
Mrd_data_in[23:16],Mrd_data_in[31:24]};
// output logic from statemachine that controls read of the posted packet fifo
// read the two headers from the posted fifo and store in registers
// the signal that kicks off the read is a single-cycle signal from
// the state machine
// read_posted_header_fifo
always@(posedge clk)begin
if(rst_reg)begin
read_posted_header_fifo_d1 <= 1'b0;
read_posted_header_fifo_d2 <= 1'b0;
//// end else if(~trn_tdst_rdy_n & ~data_stall)begin
// end else if(~trn_tdst_rdy_n)begin
end else begin
/// Jiansong: pipeline the fifo rden signal
read_posted_header_fifo_d1 <= read_posted_header_fifo;
read_posted_header_fifo_d2 <= read_posted_header_fifo_d1;
end
end
//stretch read enable to two clocks and qualify with trn_tdst_rdy_n
assign posted_hdr_fifo_rden = (read_posted_header_fifo_d1
| read_posted_header_fifo);
// & ~trn_tdst_rdy_n;
//// & ~trn_tdst_rdy_n
//// & ~data_stall;
// use the read enable signals to enable registers p_hd1 and p_hd2
always@(posedge clk)begin
if(rst_reg)begin
p_hd1[63:0] <= 64'h0000000000000000;
//// end else if(~trn_tdst_rdy_n & ~data_stall)begin
// end else if(~trn_tdst_rdy_n) begin
end else begin
if(read_posted_header_fifo_d1)begin
p_hd1 <= posted_hdr_fifo;
end else begin
p_hd1 <= p_hd1;
end
end
end
always@(posedge clk)begin
if(rst_reg)begin
p_hd2[63:0] <= 64'h0000000000000000;
//// end else if(~trn_tdst_rdy_n & ~data_stall)begin
// end else if(~trn_tdst_rdy_n)begin
end else begin
if(read_posted_header_fifo_d2)begin
p_hd2 <= posted_hdr_fifo;
end else begin
p_hd2 <= p_hd2;
end
end
end
//assign signals for reading clarity
assign p_fmt[1:0] = p_hd1[62:61]; //format field
assign p_tc[2:0] = p_hd1[54:52]; //traffic class field
assign p_length[9:0] = p_hd1[41:32]; //DW length field
assign p_trn_fifo_rdy = trn_tbuf_av[1];
// output logic from statemachine that controls read of the
// non_posted packet fifo
// read the two headers from the non posted fifo and store in registers
// the signal that kicks off the read is a single-cycle signal from the
// state machine
// read_posted_header_fifo
always@(posedge clk)begin
if(rst_reg)begin
read_non_posted_header_fifo_d1 <= 1'b0;
read_non_posted_header_fifo_d2 <= 1'b0;
// end else if(~trn_tdst_rdy_n) begin
end else begin
/// Jiansong: pipeline the fifo rden signal
read_non_posted_header_fifo_d1 <= read_non_posted_header_fifo;
read_non_posted_header_fifo_d2 <= read_non_posted_header_fifo_d1;
end
end
//stretch read enable to two clocks and qualify with trn_tdst_rdy_n
assign nonposted_hdr_fifo_rden = (read_non_posted_header_fifo_d1
| read_non_posted_header_fifo);
// & ~trn_tdst_rdy_n;
// use the read enable signals to enable registers np_hd1 and np_hd2
always@(posedge clk)begin
if(rst_reg)begin
np_hd1[63:0] <= 64'h0000000000000000;
// end else if(~trn_tdst_rdy_n)begin
end else begin
if(read_non_posted_header_fifo_d1)begin
np_hd1 <= nonposted_hdr_fifo;
end else begin
np_hd1 <= np_hd1;
end
end
end
always@(posedge clk)begin
if(rst_reg)begin
np_hd2[63:0] <= 64'h0000000000000000;
// end else if(~trn_tdst_rdy_n)begin
end else begin
if(read_non_posted_header_fifo_d2)begin
np_hd2 <= nonposted_hdr_fifo;
end else begin
np_hd2 <= np_hd2;
end
end
end
//assign signals for reading clarity
assign np_fmt[1:0] = np_hd1[62:61]; //format field
assign np_tc[2:0] = np_hd1[54:52]; //traffic class field
assign np_length[9:0] = np_hd1[41:32]; //DW length field
assign np_trn_fifo_rdy = trn_tbuf_av[0];
// output logic from statemachine that controls read of the comp packet fifo
// read the two headers from the comp fifo and store in registers
// the signal that kicks off the read is a single-cycle signal from
// the state machine
// read_comp_header_fifo
always@(posedge clk)begin
if(rst_reg)begin
read_comp_header_fifo_d1 <= 1'b0;
read_comp_header_fifo_d2 <= 1'b0;
//// end else if(~trn_tdst_rdy_n & (~data_stall | ~posted))begin
// end else if(~trn_tdst_rdy_n)begin /// pending
end else begin
read_comp_header_fifo_d1 <= read_comp_header_fifo;
read_comp_header_fifo_d2 <= read_comp_header_fifo_d1;
end
end
//stretch read enable to two clocks and qualify with trn_tdst_rdy_n
assign comp_hdr_fifo_rden = (read_comp_header_fifo_d1
| read_comp_header_fifo);
// & ~trn_tdst_rdy_n;
// use the read enable signals to enable registers comp_hd1 and comp_hd2
always@(posedge clk)begin
if(rst_reg)begin
comp_hd1[63:0] <= 64'h0000000000000000;
//// end else if(~trn_tdst_rdy_n & (~data_stall | ~posted))begin
// end else if(~trn_tdst_rdy_n)begin /// pending
end else begin
if(read_comp_header_fifo_d1)begin
comp_hd1 <= comp_hdr_fifo;
end else begin
comp_hd1 <= comp_hd1;
end
end
end
always@(posedge clk)begin
if(rst_reg)begin
comp_hd2[63:0] <= 64'h0000000000000000;
//// end else if(~trn_tdst_rdy_n & (~data_stall | ~posted))begin
// end else if(~trn_tdst_rdy_n)begin /// pending
end else begin
if(read_comp_header_fifo_d2)begin
comp_hd2 <= comp_hdr_fifo;
end else begin
comp_hd2 <= comp_hd2;
end
end
end
assign comp_trn_fifo_rdy = trn_tbuf_av[2];
//encode data_src
//reg_file = BAR_HIT[6:0] = 0000001 -> 01
//ROM_BAR = BAR_HIT[6:0] = 1000000 -> 10
//DDR2 -> 00 no need to decode as DDR2 not supported as a PCIe target
always@(*)begin //// Jiansong: no clock driven, or whatever clock driven
case(comp_hd1[63:57])
7'b0000001: data_src_mux[1:0] <= 2'b01;
7'b1000000: data_src_mux[1:0] <= 2'b10;
//// default: data_src_mux[1:0] <= 2'b00;
default: data_src_mux[1:0] <= 2'b01;
endcase
end
/// Jiansong: pending
//countdown to control amount of data tranfer in state machine
//count in quadwords since trn_td is 64-bits
always@(posedge clk)begin
if(rst_reg)
length_countdown <= 10'b00_0000_0000;
//// else if (~trn_tdst_rdy_n & ~data_stall)begin
else if (~trn_tdst_rdy_n)begin
if(state == HD1_P_XFER)
length_countdown <= p_length>>1; //count in quadwords
else if(length_countdown != 0)
length_countdown <= length_countdown - 1;
end else
length_countdown <= length_countdown;
end
//data_xfer is a state machine output that tells the egress_data_presenter
// to transfer data; every clock cycle it is asserted one 64-bit data
// is valid on the next cycle - unless data_stall is asserted
////assign data_xfer = data_xfer_reg;
// data steering logic
always@(posedge clk)begin
if(rst_reg)begin
// data_reg <= 64'h0000000000000000;
data_reg[31:0] <= 32'h0000_0000;
//// end else if(~trn_tdst_rdy_n & (~data_stall | ~posted)) begin
end else if(~trn_tdst_rdy_n) begin
data_reg[31:0] <= data_swap[31:0];
end
end
/// Jiansong: this register is added the rden delay problem when trn_tdst_rdy_n is deasserted
always@(posedge clk)begin
if(rst_reg)begin
data_reg_tdst_problem <= 64'h0000000000000000;
end else if(~trn_tdst_rdy_n_r)begin
data_reg_tdst_problem <= data_swap;
end
end
//mux the trn_td[63:0] - dependent on what state the main state machine is in
always@(posedge clk)begin
if(rst_reg)
trn_td <= 0;
//// else if(~trn_tdst_rdy_n & (~data_stall | ~posted))begin
else if(~trn_tdst_rdy_n)begin
casex({state,p_fmt[0]})
{HD1_P_XFER,1'bx}: begin
trn_td <= p_hd1;
end
{HD2_P_XFER,1'b0}: begin
if(trn_tdst_rdy_n_r) /// Jiansong:
trn_td <= {p_hd2[63:32],data_reg_tdst_problem[63:32]};
else
trn_td <= {p_hd2[63:32],data_swap[63:32]};
end
{HD2_P_XFER,1'b1}: begin
trn_td <= p_hd2[63:0];
end
{DATA_P_XFER,1'b0},{LAST_P_XFER,1'b0}: begin
if(trn_tdst_rdy_n_r) /// Jiansong:
trn_td[63:0] <= {data_reg[31:0],data_reg_tdst_problem[63:32]};
else if(trn_tdst_rdy_n_r2)
trn_td[63:0] <= {data_reg_tdst_problem[31:0],data_swap[63:32]};
else
trn_td[63:0] <= {data_reg[31:0],data_swap[63:32]};
end
{DATA_P_XFER,1'b1},{LAST_P_XFER,1'b1}: begin
if(trn_tdst_rdy_n_r) /// Jiansong:
trn_td[63:0] <= data_reg_tdst_problem[63:0];
else
trn_td[63:0] <= data_swap[63:0];
end
{HD1_NP_XFER,1'bx}: begin
trn_td <= np_hd1;
end
{HD2_NP_XFER,1'bx}: begin
trn_td <= np_hd2;
end
{HD1_COMP_XFER,1'bx}: begin
trn_td <= {comp_hd1[31:0],comp_hd2[63:32]};
end
{HD2_COMP_XFER,1'bx}: begin
//// trn_td <= {comp_hd2[31:0],data_reg[63:32]};
/// Jiansong: rom_bar, keep the old design, but don't know what's it for
if (data_src_mux[1:0] == 2'b10) begin
trn_td <= {comp_hd2[31:0],32'h00000000};
end else if (data_src_mux[1:0] == 2'b01) begin
trn_td <= {comp_hd2[31:0],Mrd_data_swap};
end else begin
trn_td <= {comp_hd2[31:0],Mrd_data_swap};
end
end
default: begin
trn_td <= 0;
end
endcase
end
end
/// Jiansong: priority is modified
/// in sora, round-robin will be used for posted, non-posted
/// and completion scheduling
//////Priority signal for posted and non-posted requests
//////When operating in full duplex mode the state machine
//////will do 8 posted requests followed by 8 non-posted requests
//////Note: this ordering assumes that the posted and non-posted
//////requests do not depend on each other.
//////Once inside the V-5 PCIe Block, strict ordering will be
//////followed. Also, note that completions are given
//////lowest priority. In order to avoid completion time-outs,
//////read requests from the host should not occur during a DMA
//////transaction.
//////If this is not possible, than the completion queue may need
//////higher priority.
/// Jiansong: pipeline registers
always@(posedge clk)begin
trn_tdst_rdy_n_r2 <= trn_tdst_rdy_n_r;
trn_tdst_rdy_n_r <= trn_tdst_rdy_n;
end
// bulk of TX TRN state machine
always@(posedge clk)begin
// if(rst_in)begin
if(rst_reg)begin
trn_tsrc_rdy_n_reg <= 1'b1;
trn_tsof_n <= 1'b1;
trn_teof_n <= 1'b1;
trn_trem_n[7:0] <= 8'b11111111;
posted_data_fifo_rden <= 1'b0;
read_posted_header_fifo <= 1'b0;
read_non_posted_header_fifo <= 1'b0;
read_comp_header_fifo <= 1'b0;
state <= IDLE;
//// //use trn_tdst_rdy_n and data_stall as clock enable - for data_stall
//// //only CE if in the posted flow
//// end else if(~trn_tdst_rdy_n & (~data_stall | ~posted))begin
// use trn_tdst_rdy_n as clock enable
end else if(trn_tdst_rdy_n)begin
// if(trn_tdst_rdy_n)begin
/// Jiansong: deassert the rden, write enable signals if PCIe core is not ready
posted_data_fifo_rden <= 1'b0;
read_posted_header_fifo <= 1'b0;
read_non_posted_header_fifo <= 1'b0;
read_comp_header_fifo <= 1'b0;
//// end else if(~trn_tdst_rdy_n)begin
end else begin
case(state)
IDLE: begin
if (hostreset_in) begin
trn_tsrc_rdy_n_reg <= 1'b1;
trn_tsof_n <= 1'b1;
trn_teof_n <= 1'b1;
trn_trem_n[7:0] <= 8'b11111111;
posted_data_fifo_rden <= 1'b0;
read_posted_header_fifo <= 1'b0;
read_non_posted_header_fifo <= 1'b0;
read_comp_header_fifo <= 1'b0;
state <= IDLE;
end else begin
trn_tsrc_rdy_n_reg <= 1'b1;
trn_tsof_n <= 1'b1;
trn_teof_n <= 1'b1;
trn_trem_n[7:0] <= 8'b11111111;
posted_data_fifo_rden <= 1'b0;
read_posted_header_fifo <= 1'b0;
read_non_posted_header_fifo <= 1'b0;
read_comp_header_fifo <= 1'b0;
if ( (np_rx_cnt_qw == np_tx_cnt_qw) && (~posted_hdr_fifo_empty) && ~Wait_for_TX_desc)
state <= GET_P_HD;
else if (~nonposted_hdr_fifo_empty)
state <= GET_NP_HD;
else if (~comp_hdr_fifo_empty)
state <= GET_COMP_HD;
else
state <= IDLE;
end
end
GET_P_HD: begin
read_posted_header_fifo <= 1'b1; //get the headers ready
trn_tsrc_rdy_n_reg <= 1'b1;
trn_trem_n[7:0] <= 8'b11111111;
trn_teof_n <= 1'b1;
state <= SETUP_P_DATA;
end
GET_NP_HD: begin
read_non_posted_header_fifo <= 1'b1; //get the headers ready
trn_tsrc_rdy_n_reg <= 1'b1;
trn_trem_n[7:0] <= 8'b11111111;
trn_teof_n <= 1'b1;
state <= SETUP_NP;
end
GET_COMP_HD: begin
read_comp_header_fifo <= 1'b1; //get the headers ready
trn_tsrc_rdy_n_reg <= 1'b1;
trn_trem_n[7:0] <= 8'b11111111;
trn_teof_n <= 1'b1;
state <= SETUP_COMP_DATA_WAIT1;
end
/// Jiansong: pending, make it simpler
//start of completer transaction flow
SETUP_COMP_DATA_WAIT1: begin //wait state for comp_hd1
read_comp_header_fifo <= 1'b0;
state <= SETUP_COMP_DATA_WAIT2;
end
SETUP_COMP_DATA_WAIT2: begin //wait state for comp_hd2
state <= SETUP_COMP_DATA;
end
SETUP_COMP_DATA: begin
Mrd_data_addr[11:0] <= {comp_hd1[41:32],2'b00};
if(comp_trn_fifo_rdy)//make sure the completion fifo in the PCIe
//block is ready
state <= WAIT_FOR_COMP_DATA_RDY;
else
state <= SETUP_COMP_DATA;
end
/// Jiansong: wait one more cycle for reg data ready, maybe not necessary
WAIT_FOR_COMP_DATA_RDY: begin
state <= HD1_COMP_XFER;
end
HD1_COMP_XFER: begin //transfer first header
trn_tsof_n <= 1'b0;
trn_tsrc_rdy_n_reg <= 1'b0;
trn_trem_n[7:0] <= 8'b00000000;
state <= HD2_COMP_XFER;
end
HD2_COMP_XFER: begin //transfer second header + 1 DW of data
trn_tsrc_rdy_n_reg <= 1'b0;
trn_tsof_n <= 1'b1;
trn_teof_n <= 1'b0;
state <= IDLE;
end
//start of posted transaction flow
SETUP_P_DATA: begin
read_posted_header_fifo <= 1'b0;
posted_data_fifo_rden <= 1'b0;
state <= P_WAIT_STATE;
end
P_WAIT_STATE : begin /// Jiansong: wait one more cycle for hdr ready
read_posted_header_fifo <= 1'b0;
posted_data_fifo_rden <= 1'b0;
state <= P_WAIT_STATE1;
end
P_WAIT_STATE1 : begin
//wait for the egress data_presenter to have data ready then start
//transmitting the first posted header
trn_teof_n <= 1'b1;
if(p_trn_fifo_rdy & ~posted_data_fifo_empty) begin //make sure posted fifo in PCIe block is ready
/// Jiansong: read data fifo?
if(p_fmt[0] == 0)begin //3DW
posted_data_fifo_rden <= 1'b1;
end else begin //4DW
posted_data_fifo_rden <= 1'b0;
end
state <= HD1_P_XFER;
end else begin
posted_data_fifo_rden <= 1'b0;
state <= P_WAIT_STATE1;
end
end
HD1_P_XFER: begin //transfer first header
trn_tsof_n <= 1'b0; //assert SOF
trn_teof_n <= 1'b1;
trn_tsrc_rdy_n_reg <= 1'b0;
trn_trem_n[7:0] <= 8'b00000000;
posted_data_fifo_rden <= 1'b1;
state <= HD2_P_XFER;
end
HD2_P_XFER: begin //transfer second header (+1 DW of data for 3DW)
trn_tsrc_rdy_n_reg <= 1'b0;
trn_tsof_n <= 1'b1; //deassert SOF
/// Jiansong: RX desc is so short (2 cycles) that we need specially consider it
if (p_fmt[0] == 0 && p_length <= 10'h004)
posted_data_fifo_rden <= 1'b0;
else
posted_data_fifo_rden <= 1'b1;
state <= DATA_P_XFER;
end
// DATA_P_XFER state for packets with more than 1 DW
// for this design the next step up will always be 128B or 32DW
DATA_P_XFER: begin
trn_tsrc_rdy_n_reg <= 1'b0;
//use a counter to figure out when we are almost done and
//jump to LAST_P_XFER when we reach the penultimate data cycle
if(length_countdown != 1)begin
state <= DATA_P_XFER;
end else begin
state <= LAST_P_XFER;
end
//figure out when to deassert data_xfer_reg based on whether
//this a 3DW or 4DW header posted TLP
if(p_fmt[0] == 0)begin //3DW case
if(length_countdown <=2)
posted_data_fifo_rden <= 1'b0;
else
posted_data_fifo_rden <= 1'b1;
end else begin //4DW case
if(length_countdown <=1)
posted_data_fifo_rden <= 1'b0;
else
posted_data_fifo_rden <= 1'b1;
end
end
LAST_P_XFER: begin
trn_tsrc_rdy_n_reg <= 1'b0;
trn_teof_n <= 1'b0;//assert EOF
posted_data_fifo_rden <= 1'b0;
read_posted_header_fifo <= 1'b0;
//assert the correct remainder bits dependent on 3DW or 4DW TLP
//headers
if(p_fmt[0] == 0) //0 for 3dw, 1 for 4dw header
trn_trem_n[7:0] <= 8'b00001111;
else
trn_trem_n[7:0] <= 8'b00000000;
state <= IDLE;
end
//start of the non-posted transaction flow
SETUP_NP: begin
read_non_posted_header_fifo <= 1'b0;
state <= NP_WAIT_STATE;
end
//NP_WAIT_STATE state needed to let np_hd1 and np_hd2 to catch up
NP_WAIT_STATE:begin
if(np_trn_fifo_rdy)
state <= HD1_NP_XFER;
else
state <= NP_WAIT_STATE;
end
HD1_NP_XFER: begin //transfer first header
trn_tsof_n <= 1'b0; //assert SOF
trn_tsrc_rdy_n_reg <= 1'b0;
trn_trem_n[7:0] <= 8'b00000000;
state <= HD2_NP_XFER;
end
HD2_NP_XFER: begin //transfer second header + 1 DW of data
trn_tsrc_rdy_n_reg <= 1'b0;
trn_tsof_n <= 1'b1; //deassert EOF
trn_teof_n <= 1'b0; //assert EOF
if(np_fmt[0] == 0) //0 for 3dw, 1 for 4dw header
trn_trem_n[7:0] <= 8'b00001111;
else
trn_trem_n[7:0] <= 8'b00000000;
state <= NP_XFER_WAIT;
end
NP_XFER_WAIT : begin /// Jiansong: add one cycle into NP xfer to support
state <= IDLE; /// semiduplex scheduling
end
endcase
end
end
/// Jiansong: logic to maintain np_tx_cnt_qw
always@(posedge clk)begin
if (rst_reg | (~transferstart))
add_calc <= 1'b0;
else if(rd_dma_start_one) //set the bit
add_calc <= 1'b1;
else if (add_complete) //reset the bit
add_calc <= 1'b0;
end
always@(posedge clk)begin
if (rst_reg | (~transferstart) | Wait_for_TX_desc)
sub_calc <= 1'b0;
else if(read_non_posted_header_fifo_d1) //set the bit, fliter out TX des
sub_calc <= 1'b1;
else if (sub_complete) //reset the bit
sub_calc <= 1'b0;
end
always@(posedge clk) np_tx_cnt_qw_add[9:0] <= dmarxs[12:3];
always@(posedge clk)begin
if(rst_reg | (~transferstart) | Wait_for_TX_desc)begin
np_tx_cnt_qw[9:0] <= 0;
end else if(update_np_tx_cnt_qw)begin
np_tx_cnt_qw[9:0] <= np_tx_cnt_qw_new[9:0];
end
end
always@(posedge clk)begin
if(rst_reg | (~transferstart) | Wait_for_TX_desc)begin
np_tx_cnt_qw_new[9:0] <= 0;
update_np_tx_cnt_qw <= 1'b0;
add_complete <= 1'b0;
sub_complete <= 1'b0;
stay_2x <= 1'b0;
addsub_state <= AS_IDLE;
end else begin
case(addsub_state)
AS_IDLE: begin
update_np_tx_cnt_qw <= 1'b0;
if(add_calc)begin
//if add_calc is asserted then add the current value (*_now) to
//the incoming dma xfer size (*_reg)
np_tx_cnt_qw_new[9:0] <= np_tx_cnt_qw[9:0]
+ np_tx_cnt_qw_add[9:0];
//make sure to stay in this state for two clock cycles
if(~stay_2x)begin
addsub_state <= AS_IDLE;
add_complete <= 1'b0;
update_np_tx_cnt_qw <= 1'b0;
stay_2x <= 1'b1;
//then update the current value (dmawxs_div8_now)
end else begin
addsub_state <= REGISTER_CALC;
add_complete <= 1'b1;//clear add_calc
update_np_tx_cnt_qw <= 1'b1;
stay_2x <= 1'b0;
end
end else if (sub_calc)begin
//if sub_calc is asserted then subtract the dw_length field
//from the incoming completion packet from the current value
np_tx_cnt_qw_new[9:0] <= np_tx_cnt_qw[9:0]
- {1'b0, np_length[9:1]};
//likewise make sure to stat in this state for two clocks
if(~stay_2x)begin
addsub_state <= AS_IDLE;
sub_complete <= 1'b0;
update_np_tx_cnt_qw <= 1'b0;
stay_2x <= 1'b1;
//then update the current value (dmawxs_div8_now)
end else begin
addsub_state <= REGISTER_CALC;
sub_complete <= 1'b1;//clear sub_calc
update_np_tx_cnt_qw <= 1'b1;
stay_2x <= 1'b0;
end
end else begin
np_tx_cnt_qw_new[9:0] <= np_tx_cnt_qw[9:0];
addsub_state <= AS_IDLE;
sub_complete <= 1'b0;
add_complete <= 1'b0;
stay_2x <= 1'b0;
end
end
REGISTER_CALC:begin
sub_complete <= 1'b0;
add_complete <= 1'b0;
addsub_state <= WAIT_FOR_REG;
update_np_tx_cnt_qw <= 1'b1;
stay_2x <= 1'b0;
end
WAIT_FOR_REG:begin
update_np_tx_cnt_qw <= 1'b0;
stay_2x <= 1'b0;
addsub_state <= AS_IDLE;
end
default:begin
np_tx_cnt_qw_new[9:0] <= 0;
update_np_tx_cnt_qw <= 1'b0;
add_complete <= 1'b0;
sub_complete <= 1'b0;
stay_2x <= 1'b0;
addsub_state <= AS_IDLE;
end
endcase
end
end
endmodule
|
// Copyright (c) 2015 CERN
// @author Maciej Suminski <[email protected]>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
// Test for variable initialization.
module vhdl_var_init_test;
logic init;
logic [7:0] slv;
bit b;
int i;
vhdl_var_init dut(init, slv, b, i);
initial begin
init = 0;
#1 init = 1;
#1;
if(slv !== 8'b01000010) begin
$display("FAILED 1");
$finish();
end
if(b !== false) begin
$display("FAILED 2");
$finish();
end
if(i !== 42) begin
$display("FAILED 3");
$finish();
end
$display("PASSED");
end
endmodule
|
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2012 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
Require Import ZAxioms ZMulOrder ZSgnAbs NZDiv.
(** * Euclidean Division for integers (Trunc convention)
We use here the convention known as Trunc, or Round-Toward-Zero,
where [a/b] is the integer with the largest absolute value to
be between zero and the exact fraction. It can be summarized by:
[a = bq+r /\ 0 <= |r| < |b| /\ Sign(r) = Sign(a)]
This is the convention of Ocaml and many other systems (C, ASM, ...).
This convention is named "T" in the following paper:
R. Boute, "The Euclidean definition of the functions div and mod",
ACM Transactions on Programming Languages and Systems,
Vol. 14, No.2, pp. 127-144, April 1992.
See files [ZDivFloor] and [ZDivEucl] for others conventions.
*)
Module Type ZQuotProp
(Import A : ZAxiomsSig')
(Import B : ZMulOrderProp A)
(Import C : ZSgnAbsProp A B).
(** We benefit from what already exists for NZ *)
Module Import Private_Div.
Module Quot2Div <: NZDiv A.
Definition div := quot.
Definition modulo := A.rem.
Definition div_wd := quot_wd.
Definition mod_wd := rem_wd.
Definition div_mod := quot_rem.
Definition mod_bound_pos := rem_bound_pos.
End Quot2Div.
Module NZQuot := Nop <+ NZDivProp A Quot2Div B.
End Private_Div.
Ltac pos_or_neg a :=
let LT := fresh "LT" in
let LE := fresh "LE" in
destruct (le_gt_cases 0 a) as [LE|LT]; [|rewrite <- opp_pos_neg in LT].
(** Another formulation of the main equation *)
Lemma rem_eq :
forall a b, b~=0 -> a rem b == a - b*(a÷b).
Proof.
intros.
rewrite <- add_move_l.
symmetry. now apply quot_rem.
Qed.
(** A few sign rules (simple ones) *)
Lemma rem_opp_opp : forall a b, b ~= 0 -> (-a) rem (-b) == - (a rem b).
Proof. intros. now rewrite rem_opp_r, rem_opp_l. Qed.
Lemma quot_opp_l : forall a b, b ~= 0 -> (-a)÷b == -(a÷b).
Proof.
intros.
rewrite <- (mul_cancel_l _ _ b) by trivial.
rewrite <- (add_cancel_r _ _ ((-a) rem b)).
now rewrite <- quot_rem, rem_opp_l, mul_opp_r, <- opp_add_distr, <- quot_rem.
Qed.
Lemma quot_opp_r : forall a b, b ~= 0 -> a÷(-b) == -(a÷b).
Proof.
intros.
assert (-b ~= 0) by (now rewrite eq_opp_l, opp_0).
rewrite <- (mul_cancel_l _ _ (-b)) by trivial.
rewrite <- (add_cancel_r _ _ (a rem (-b))).
now rewrite <- quot_rem, rem_opp_r, mul_opp_opp, <- quot_rem.
Qed.
Lemma quot_opp_opp : forall a b, b ~= 0 -> (-a)÷(-b) == a÷b.
Proof. intros. now rewrite quot_opp_r, quot_opp_l, opp_involutive. Qed.
(** Uniqueness theorems *)
Theorem quot_rem_unique : forall b q1 q2 r1 r2 : t,
(0<=r1<b \/ b<r1<=0) -> (0<=r2<b \/ b<r2<=0) ->
b*q1+r1 == b*q2+r2 -> q1 == q2 /\ r1 == r2.
Proof.
intros b q1 q2 r1 r2 Hr1 Hr2 EQ.
destruct Hr1; destruct Hr2; try (intuition; order).
apply NZQuot.div_mod_unique with b; trivial.
rewrite <- (opp_inj_wd r1 r2).
apply NZQuot.div_mod_unique with (-b); trivial.
rewrite <- opp_lt_mono, opp_nonneg_nonpos; tauto.
rewrite <- opp_lt_mono, opp_nonneg_nonpos; tauto.
now rewrite 2 mul_opp_l, <- 2 opp_add_distr, opp_inj_wd.
Qed.
Theorem quot_unique:
forall a b q r, 0<=a -> 0<=r<b -> a == b*q + r -> q == a÷b.
Proof. intros; now apply NZQuot.div_unique with r. Qed.
Theorem rem_unique:
forall a b q r, 0<=a -> 0<=r<b -> a == b*q + r -> r == a rem b.
Proof. intros; now apply NZQuot.mod_unique with q. Qed.
(** A division by itself returns 1 *)
Lemma quot_same : forall a, a~=0 -> a÷a == 1.
Proof.
intros. pos_or_neg a. apply NZQuot.div_same; order.
rewrite <- quot_opp_opp by trivial. now apply NZQuot.div_same.
Qed.
Lemma rem_same : forall a, a~=0 -> a rem a == 0.
Proof.
intros. rewrite rem_eq, quot_same by trivial. nzsimpl. apply sub_diag.
Qed.
(** A division of a small number by a bigger one yields zero. *)
Theorem quot_small: forall a b, 0<=a<b -> a÷b == 0.
Proof. exact NZQuot.div_small. Qed.
(** Same situation, in term of remulo: *)
Theorem rem_small: forall a b, 0<=a<b -> a rem b == a.
Proof. exact NZQuot.mod_small. Qed.
(** * Basic values of divisions and modulo. *)
Lemma quot_0_l: forall a, a~=0 -> 0÷a == 0.
Proof.
intros. pos_or_neg a. apply NZQuot.div_0_l; order.
rewrite <- quot_opp_opp, opp_0 by trivial. now apply NZQuot.div_0_l.
Qed.
Lemma rem_0_l: forall a, a~=0 -> 0 rem a == 0.
Proof.
intros; rewrite rem_eq, quot_0_l; now nzsimpl.
Qed.
Lemma quot_1_r: forall a, a÷1 == a.
Proof.
intros. pos_or_neg a. now apply NZQuot.div_1_r.
apply opp_inj. rewrite <- quot_opp_l. apply NZQuot.div_1_r; order.
intro EQ; symmetry in EQ; revert EQ; apply lt_neq, lt_0_1.
Qed.
Lemma rem_1_r: forall a, a rem 1 == 0.
Proof.
intros. rewrite rem_eq, quot_1_r; nzsimpl; auto using sub_diag.
intro EQ; symmetry in EQ; revert EQ; apply lt_neq; apply lt_0_1.
Qed.
Lemma quot_1_l: forall a, 1<a -> 1÷a == 0.
Proof. exact NZQuot.div_1_l. Qed.
Lemma rem_1_l: forall a, 1<a -> 1 rem a == 1.
Proof. exact NZQuot.mod_1_l. Qed.
Lemma quot_mul : forall a b, b~=0 -> (a*b)÷b == a.
Proof.
intros. pos_or_neg a; pos_or_neg b. apply NZQuot.div_mul; order.
rewrite <- quot_opp_opp, <- mul_opp_r by order. apply NZQuot.div_mul; order.
rewrite <- opp_inj_wd, <- quot_opp_l, <- mul_opp_l by order.
apply NZQuot.div_mul; order.
rewrite <- opp_inj_wd, <- quot_opp_r, <- mul_opp_opp by order.
apply NZQuot.div_mul; order.
Qed.
Lemma rem_mul : forall a b, b~=0 -> (a*b) rem b == 0.
Proof.
intros. rewrite rem_eq, quot_mul by trivial. rewrite mul_comm; apply sub_diag.
Qed.
Theorem quot_unique_exact a b q: b~=0 -> a == b*q -> q == a÷b.
Proof.
intros Hb H. rewrite H, mul_comm. symmetry. now apply quot_mul.
Qed.
(** The sign of [a rem b] is the one of [a] (when it's not null) *)
Lemma rem_nonneg : forall a b, b~=0 -> 0 <= a -> 0 <= a rem b.
Proof.
intros. pos_or_neg b. destruct (rem_bound_pos a b); order.
rewrite <- rem_opp_r; trivial.
destruct (rem_bound_pos a (-b)); trivial.
Qed.
Lemma rem_nonpos : forall a b, b~=0 -> a <= 0 -> a rem b <= 0.
Proof.
intros a b Hb Ha.
apply opp_nonneg_nonpos. apply opp_nonneg_nonpos in Ha.
rewrite <- rem_opp_l by trivial. now apply rem_nonneg.
Qed.
Lemma rem_sign_mul : forall a b, b~=0 -> 0 <= (a rem b) * a.
Proof.
intros a b Hb. destruct (le_ge_cases 0 a).
apply mul_nonneg_nonneg; trivial. now apply rem_nonneg.
apply mul_nonpos_nonpos; trivial. now apply rem_nonpos.
Qed.
Lemma rem_sign_nz : forall a b, b~=0 -> a rem b ~= 0 ->
sgn (a rem b) == sgn a.
Proof.
intros a b Hb H. destruct (lt_trichotomy 0 a) as [LT|[EQ|LT]].
rewrite 2 sgn_pos; try easy.
generalize (rem_nonneg a b Hb (lt_le_incl _ _ LT)). order.
now rewrite <- EQ, rem_0_l, sgn_0.
rewrite 2 sgn_neg; try easy.
generalize (rem_nonpos a b Hb (lt_le_incl _ _ LT)). order.
Qed.
Lemma rem_sign : forall a b, a~=0 -> b~=0 -> sgn (a rem b) ~= -sgn a.
Proof.
intros a b Ha Hb H.
destruct (eq_decidable (a rem b) 0) as [EQ|NEQ].
apply Ha, sgn_null_iff, opp_inj. now rewrite <- H, opp_0, EQ, sgn_0.
apply Ha, sgn_null_iff. apply eq_mul_0_l with 2; try order'. nzsimpl'.
apply add_move_0_l. rewrite <- H. symmetry. now apply rem_sign_nz.
Qed.
(** Operations and absolute value *)
Lemma rem_abs_l : forall a b, b ~= 0 -> (abs a) rem b == abs (a rem b).
Proof.
intros a b Hb. destruct (le_ge_cases 0 a) as [LE|LE].
rewrite 2 abs_eq; try easy. now apply rem_nonneg.
rewrite 2 abs_neq, rem_opp_l; try easy. now apply rem_nonpos.
Qed.
Lemma rem_abs_r : forall a b, b ~= 0 -> a rem (abs b) == a rem b.
Proof.
intros a b Hb. destruct (le_ge_cases 0 b).
now rewrite abs_eq. now rewrite abs_neq, ?rem_opp_r.
Qed.
Lemma rem_abs : forall a b, b ~= 0 -> (abs a) rem (abs b) == abs (a rem b).
Proof.
intros. now rewrite rem_abs_r, rem_abs_l.
Qed.
Lemma quot_abs_l : forall a b, b ~= 0 -> (abs a)÷b == (sgn a)*(a÷b).
Proof.
intros a b Hb. destruct (lt_trichotomy 0 a) as [LT|[EQ|LT]].
rewrite abs_eq, sgn_pos by order. now nzsimpl.
rewrite <- EQ, abs_0, quot_0_l; trivial. now nzsimpl.
rewrite abs_neq, quot_opp_l, sgn_neg by order.
rewrite mul_opp_l. now nzsimpl.
Qed.
Lemma quot_abs_r : forall a b, b ~= 0 -> a÷(abs b) == (sgn b)*(a÷b).
Proof.
intros a b Hb. destruct (lt_trichotomy 0 b) as [LT|[EQ|LT]].
rewrite abs_eq, sgn_pos by order. now nzsimpl.
order.
rewrite abs_neq, quot_opp_r, sgn_neg by order.
rewrite mul_opp_l. now nzsimpl.
Qed.
Lemma quot_abs : forall a b, b ~= 0 -> (abs a)÷(abs b) == abs (a÷b).
Proof.
intros a b Hb.
pos_or_neg a; [rewrite (abs_eq a)|rewrite (abs_neq a)];
try apply opp_nonneg_nonpos; try order.
pos_or_neg b; [rewrite (abs_eq b)|rewrite (abs_neq b)];
try apply opp_nonneg_nonpos; try order.
rewrite abs_eq; try easy. apply NZQuot.div_pos; order.
rewrite <- abs_opp, <- quot_opp_r, abs_eq; try easy.
apply NZQuot.div_pos; order.
pos_or_neg b; [rewrite (abs_eq b)|rewrite (abs_neq b)];
try apply opp_nonneg_nonpos; try order.
rewrite <- (abs_opp (_÷_)), <- quot_opp_l, abs_eq; try easy.
apply NZQuot.div_pos; order.
rewrite <- (quot_opp_opp a b), abs_eq; try easy.
apply NZQuot.div_pos; order.
Qed.
(** We have a general bound for absolute values *)
Lemma rem_bound_abs :
forall a b, b~=0 -> abs (a rem b) < abs b.
Proof.
intros. rewrite <- rem_abs; trivial.
apply rem_bound_pos. apply abs_nonneg. now apply abs_pos.
Qed.
(** * Order results about rem and quot *)
(** A modulo cannot grow beyond its starting point. *)
Theorem rem_le: forall a b, 0<=a -> 0<b -> a rem b <= a.
Proof. exact NZQuot.mod_le. Qed.
Theorem quot_pos : forall a b, 0<=a -> 0<b -> 0<= a÷b.
Proof. exact NZQuot.div_pos. Qed.
Lemma quot_str_pos : forall a b, 0<b<=a -> 0 < a÷b.
Proof. exact NZQuot.div_str_pos. Qed.
Lemma quot_small_iff : forall a b, b~=0 -> (a÷b==0 <-> abs a < abs b).
Proof.
intros. pos_or_neg a; pos_or_neg b.
rewrite NZQuot.div_small_iff; try order. rewrite 2 abs_eq; intuition; order.
rewrite <- opp_inj_wd, opp_0, <- quot_opp_r, NZQuot.div_small_iff by order.
rewrite (abs_eq a), (abs_neq' b); intuition; order.
rewrite <- opp_inj_wd, opp_0, <- quot_opp_l, NZQuot.div_small_iff by order.
rewrite (abs_neq' a), (abs_eq b); intuition; order.
rewrite <- quot_opp_opp, NZQuot.div_small_iff by order.
rewrite (abs_neq' a), (abs_neq' b); intuition; order.
Qed.
Lemma rem_small_iff : forall a b, b~=0 -> (a rem b == a <-> abs a < abs b).
Proof.
intros. rewrite rem_eq, <- quot_small_iff by order.
rewrite sub_move_r, <- (add_0_r a) at 1. rewrite add_cancel_l.
rewrite eq_sym_iff, eq_mul_0. tauto.
Qed.
(** As soon as the divisor is strictly greater than 1,
the division is strictly decreasing. *)
Lemma quot_lt : forall a b, 0<a -> 1<b -> a÷b < a.
Proof. exact NZQuot.div_lt. Qed.
(** [le] is compatible with a positive division. *)
Lemma quot_le_mono : forall a b c, 0<c -> a<=b -> a÷c <= b÷c.
Proof.
intros. pos_or_neg a. apply NZQuot.div_le_mono; auto.
pos_or_neg b. apply le_trans with 0.
rewrite <- opp_nonneg_nonpos, <- quot_opp_l by order.
apply quot_pos; order.
apply quot_pos; order.
rewrite opp_le_mono in *. rewrite <- 2 quot_opp_l by order.
apply NZQuot.div_le_mono; intuition; order.
Qed.
(** With this choice of division,
rounding of quot is always done toward zero: *)
Lemma mul_quot_le : forall a b, 0<=a -> b~=0 -> 0 <= b*(a÷b) <= a.
Proof.
intros. pos_or_neg b.
split.
apply mul_nonneg_nonneg; [|apply quot_pos]; order.
apply NZQuot.mul_div_le; order.
rewrite <- mul_opp_opp, <- quot_opp_r by order.
split.
apply mul_nonneg_nonneg; [|apply quot_pos]; order.
apply NZQuot.mul_div_le; order.
Qed.
Lemma mul_quot_ge : forall a b, a<=0 -> b~=0 -> a <= b*(a÷b) <= 0.
Proof.
intros.
rewrite <- opp_nonneg_nonpos, opp_le_mono, <-mul_opp_r, <-quot_opp_l by order.
rewrite <- opp_nonneg_nonpos in *.
destruct (mul_quot_le (-a) b); tauto.
Qed.
(** For positive numbers, considering [S (a÷b)] leads to an upper bound for [a] *)
Lemma mul_succ_quot_gt: forall a b, 0<=a -> 0<b -> a < b*(S (a÷b)).
Proof. exact NZQuot.mul_succ_div_gt. Qed.
(** Similar results with negative numbers *)
Lemma mul_pred_quot_lt: forall a b, a<=0 -> 0<b -> b*(P (a÷b)) < a.
Proof.
intros.
rewrite opp_lt_mono, <- mul_opp_r, opp_pred, <- quot_opp_l by order.
rewrite <- opp_nonneg_nonpos in *.
now apply mul_succ_quot_gt.
Qed.
Lemma mul_pred_quot_gt: forall a b, 0<=a -> b<0 -> a < b*(P (a÷b)).
Proof.
intros.
rewrite <- mul_opp_opp, opp_pred, <- quot_opp_r by order.
rewrite <- opp_pos_neg in *.
now apply mul_succ_quot_gt.
Qed.
Lemma mul_succ_quot_lt: forall a b, a<=0 -> b<0 -> b*(S (a÷b)) < a.
Proof.
intros.
rewrite opp_lt_mono, <- mul_opp_l, <- quot_opp_opp by order.
rewrite <- opp_nonneg_nonpos, <- opp_pos_neg in *.
now apply mul_succ_quot_gt.
Qed.
(** Inequality [mul_quot_le] is exact iff the modulo is zero. *)
Lemma quot_exact : forall a b, b~=0 -> (a == b*(a÷b) <-> a rem b == 0).
Proof.
intros. rewrite rem_eq by order. rewrite sub_move_r; nzsimpl; tauto.
Qed.
(** Some additionnal inequalities about quot. *)
Theorem quot_lt_upper_bound:
forall a b q, 0<=a -> 0<b -> a < b*q -> a÷b < q.
Proof. exact NZQuot.div_lt_upper_bound. Qed.
Theorem quot_le_upper_bound:
forall a b q, 0<b -> a <= b*q -> a÷b <= q.
Proof.
intros.
rewrite <- (quot_mul q b) by order.
apply quot_le_mono; trivial. now rewrite mul_comm.
Qed.
Theorem quot_le_lower_bound:
forall a b q, 0<b -> b*q <= a -> q <= a÷b.
Proof.
intros.
rewrite <- (quot_mul q b) by order.
apply quot_le_mono; trivial. now rewrite mul_comm.
Qed.
(** A division respects opposite monotonicity for the divisor *)
Lemma quot_le_compat_l: forall p q r, 0<=p -> 0<q<=r -> p÷r <= p÷q.
Proof. exact NZQuot.div_le_compat_l. Qed.
(** * Relations between usual operations and rem and quot *)
(** Unlike with other division conventions, some results here aren't
always valid, and need to be restricted. For instance
[(a+b*c) rem c <> a rem c] for [a=9,b=-5,c=2] *)
Lemma rem_add : forall a b c, c~=0 -> 0 <= (a+b*c)*a ->
(a + b * c) rem c == a rem c.
Proof.
assert (forall a b c, c~=0 -> 0<=a -> 0<=a+b*c -> (a+b*c) rem c == a rem c).
intros. pos_or_neg c. apply NZQuot.mod_add; order.
rewrite <- (rem_opp_r a), <- (rem_opp_r (a+b*c)) by order.
rewrite <- mul_opp_opp in *.
apply NZQuot.mod_add; order.
intros a b c Hc Habc.
destruct (le_0_mul _ _ Habc) as [(Habc',Ha)|(Habc',Ha)]. auto.
apply opp_inj. revert Ha Habc'.
rewrite <- 2 opp_nonneg_nonpos.
rewrite <- 2 rem_opp_l, opp_add_distr, <- mul_opp_l by order. auto.
Qed.
Lemma quot_add : forall a b c, c~=0 -> 0 <= (a+b*c)*a ->
(a + b * c) ÷ c == a ÷ c + b.
Proof.
intros.
rewrite <- (mul_cancel_l _ _ c) by trivial.
rewrite <- (add_cancel_r _ _ ((a+b*c) rem c)).
rewrite <- quot_rem, rem_add by trivial.
now rewrite mul_add_distr_l, add_shuffle0, <-quot_rem, mul_comm.
Qed.
Lemma quot_add_l: forall a b c, b~=0 -> 0 <= (a*b+c)*c ->
(a * b + c) ÷ b == a + c ÷ b.
Proof.
intros a b c. rewrite add_comm, (add_comm a). now apply quot_add.
Qed.
(** Cancellations. *)
Lemma quot_mul_cancel_r : forall a b c, b~=0 -> c~=0 ->
(a*c)÷(b*c) == a÷b.
Proof.
assert (Aux1 : forall a b c, 0<=a -> 0<b -> c~=0 -> (a*c)÷(b*c) == a÷b).
intros. pos_or_neg c. apply NZQuot.div_mul_cancel_r; order.
rewrite <- quot_opp_opp, <- 2 mul_opp_r. apply NZQuot.div_mul_cancel_r; order.
rewrite <- neq_mul_0; intuition order.
assert (Aux2 : forall a b c, 0<=a -> b~=0 -> c~=0 -> (a*c)÷(b*c) == a÷b).
intros. pos_or_neg b. apply Aux1; order.
apply opp_inj. rewrite <- 2 quot_opp_r, <- mul_opp_l; try order. apply Aux1; order.
rewrite <- neq_mul_0; intuition order.
intros. pos_or_neg a. apply Aux2; order.
apply opp_inj. rewrite <- 2 quot_opp_l, <- mul_opp_l; try order. apply Aux2; order.
rewrite <- neq_mul_0; intuition order.
Qed.
Lemma quot_mul_cancel_l : forall a b c, b~=0 -> c~=0 ->
(c*a)÷(c*b) == a÷b.
Proof.
intros. rewrite !(mul_comm c); now apply quot_mul_cancel_r.
Qed.
Lemma mul_rem_distr_r: forall a b c, b~=0 -> c~=0 ->
(a*c) rem (b*c) == (a rem b) * c.
Proof.
intros.
assert (b*c ~= 0) by (rewrite <- neq_mul_0; tauto).
rewrite ! rem_eq by trivial.
rewrite quot_mul_cancel_r by order.
now rewrite mul_sub_distr_r, <- !mul_assoc, (mul_comm (a÷b) c).
Qed.
Lemma mul_rem_distr_l: forall a b c, b~=0 -> c~=0 ->
(c*a) rem (c*b) == c * (a rem b).
Proof.
intros; rewrite !(mul_comm c); now apply mul_rem_distr_r.
Qed.
(** Operations modulo. *)
Theorem rem_rem: forall a n, n~=0 ->
(a rem n) rem n == a rem n.
Proof.
intros. pos_or_neg a; pos_or_neg n. apply NZQuot.mod_mod; order.
rewrite <- ! (rem_opp_r _ n) by trivial. apply NZQuot.mod_mod; order.
apply opp_inj. rewrite <- !rem_opp_l by order. apply NZQuot.mod_mod; order.
apply opp_inj. rewrite <- !rem_opp_opp by order. apply NZQuot.mod_mod; order.
Qed.
Lemma mul_rem_idemp_l : forall a b n, n~=0 ->
((a rem n)*b) rem n == (a*b) rem n.
Proof.
assert (Aux1 : forall a b n, 0<=a -> 0<=b -> n~=0 ->
((a rem n)*b) rem n == (a*b) rem n).
intros. pos_or_neg n. apply NZQuot.mul_mod_idemp_l; order.
rewrite <- ! (rem_opp_r _ n) by order. apply NZQuot.mul_mod_idemp_l; order.
assert (Aux2 : forall a b n, 0<=a -> n~=0 ->
((a rem n)*b) rem n == (a*b) rem n).
intros. pos_or_neg b. now apply Aux1.
apply opp_inj. rewrite <-2 rem_opp_l, <-2 mul_opp_r by order.
apply Aux1; order.
intros a b n Hn. pos_or_neg a. now apply Aux2.
apply opp_inj. rewrite <-2 rem_opp_l, <-2 mul_opp_l, <-rem_opp_l by order.
apply Aux2; order.
Qed.
Lemma mul_rem_idemp_r : forall a b n, n~=0 ->
(a*(b rem n)) rem n == (a*b) rem n.
Proof.
intros. rewrite !(mul_comm a). now apply mul_rem_idemp_l.
Qed.
Theorem mul_rem: forall a b n, n~=0 ->
(a * b) rem n == ((a rem n) * (b rem n)) rem n.
Proof.
intros. now rewrite mul_rem_idemp_l, mul_rem_idemp_r.
Qed.
(** addition and modulo
Generally speaking, unlike with other conventions, we don't have
[(a+b) rem n = (a rem n + b rem n) rem n]
for any a and b.
For instance, take (8 + (-10)) rem 3 = -2 whereas
(8 rem 3 + (-10 rem 3)) rem 3 = 1.
*)
Lemma add_rem_idemp_l : forall a b n, n~=0 -> 0 <= a*b ->
((a rem n)+b) rem n == (a+b) rem n.
Proof.
assert (Aux : forall a b n, 0<=a -> 0<=b -> n~=0 ->
((a rem n)+b) rem n == (a+b) rem n).
intros. pos_or_neg n. apply NZQuot.add_mod_idemp_l; order.
rewrite <- ! (rem_opp_r _ n) by order. apply NZQuot.add_mod_idemp_l; order.
intros a b n Hn Hab. destruct (le_0_mul _ _ Hab) as [(Ha,Hb)|(Ha,Hb)].
now apply Aux.
apply opp_inj. rewrite <-2 rem_opp_l, 2 opp_add_distr, <-rem_opp_l by order.
rewrite <- opp_nonneg_nonpos in *.
now apply Aux.
Qed.
Lemma add_rem_idemp_r : forall a b n, n~=0 -> 0 <= a*b ->
(a+(b rem n)) rem n == (a+b) rem n.
Proof.
intros. rewrite !(add_comm a). apply add_rem_idemp_l; trivial.
now rewrite mul_comm.
Qed.
Theorem add_rem: forall a b n, n~=0 -> 0 <= a*b ->
(a+b) rem n == (a rem n + b rem n) rem n.
Proof.
intros a b n Hn Hab. rewrite add_rem_idemp_l, add_rem_idemp_r; trivial.
reflexivity.
destruct (le_0_mul _ _ Hab) as [(Ha,Hb)|(Ha,Hb)];
destruct (le_0_mul _ _ (rem_sign_mul b n Hn)) as [(Hb',Hm)|(Hb',Hm)];
auto using mul_nonneg_nonneg, mul_nonpos_nonpos.
setoid_replace b with 0 by order. rewrite rem_0_l by order. nzsimpl; order.
setoid_replace b with 0 by order. rewrite rem_0_l by order. nzsimpl; order.
Qed.
(** Conversely, the following results need less restrictions here. *)
Lemma quot_quot : forall a b c, b~=0 -> c~=0 ->
(a÷b)÷c == a÷(b*c).
Proof.
assert (Aux1 : forall a b c, 0<=a -> 0<b -> c~=0 -> (a÷b)÷c == a÷(b*c)).
intros. pos_or_neg c. apply NZQuot.div_div; order.
apply opp_inj. rewrite <- 2 quot_opp_r, <- mul_opp_r; trivial.
apply NZQuot.div_div; order.
rewrite <- neq_mul_0; intuition order.
assert (Aux2 : forall a b c, 0<=a -> b~=0 -> c~=0 -> (a÷b)÷c == a÷(b*c)).
intros. pos_or_neg b. apply Aux1; order.
apply opp_inj. rewrite <- quot_opp_l, <- 2 quot_opp_r, <- mul_opp_l; trivial.
apply Aux1; trivial.
rewrite <- neq_mul_0; intuition order.
intros. pos_or_neg a. apply Aux2; order.
apply opp_inj. rewrite <- 3 quot_opp_l; try order. apply Aux2; order.
rewrite <- neq_mul_0. tauto.
Qed.
Lemma mod_mul_r : forall a b c, b~=0 -> c~=0 ->
a rem (b*c) == a rem b + b*((a÷b) rem c).
Proof.
intros a b c Hb Hc.
apply add_cancel_l with (b*c*(a÷(b*c))).
rewrite <- quot_rem by (apply neq_mul_0; split; order).
rewrite <- quot_quot by trivial.
rewrite add_assoc, add_shuffle0, <- mul_assoc, <- mul_add_distr_l.
rewrite <- quot_rem by order.
apply quot_rem; order.
Qed.
(** A last inequality: *)
Theorem quot_mul_le:
forall a b c, 0<=a -> 0<b -> 0<=c -> c*(a÷b) <= (c*a)÷b.
Proof. exact NZQuot.div_mul_le. Qed.
End ZQuotProp.
|
// (C) 2001-2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module store and retrieves video frames to and from memory. *
* *
******************************************************************************/
`undef USE_TO_MEMORY
`define USE_32BIT_MASTER
module Raster_Laser_Projector_Video_In_video_dma_controller_0 (
// Inputs
clk,
reset,
stream_data,
stream_startofpacket,
stream_endofpacket,
stream_empty,
stream_valid,
master_waitrequest,
slave_address,
slave_byteenable,
slave_read,
slave_write,
slave_writedata,
// Bidirectional
// Outputs
stream_ready,
master_address,
master_write,
master_writedata,
slave_readdata
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter DW = 7; // Frame's datawidth
parameter EW = 0; // Frame's empty width
parameter WIDTH = 640; // Frame's width in pixels
parameter HEIGHT = 480; // Frame's height in lines
parameter AW = 18; // Frame's address width
parameter WW = 9; // Frame width's address width
parameter HW = 8; // Frame height's address width
parameter MDW = 7; // Avalon master's datawidth
parameter DEFAULT_BUFFER_ADDRESS = 32'd9437184;
parameter DEFAULT_BACK_BUF_ADDRESS = 32'd0;
parameter ADDRESSING_BITS = 16'd19;
parameter COLOR_BITS = 4'd7;
parameter COLOR_PLANES = 2'd0;
parameter DEFAULT_DMA_ENABLED = 1'b1; // 0: OFF or 1: ON
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [DW: 0] stream_data;
input stream_startofpacket;
input stream_endofpacket;
input [EW: 0] stream_empty;
input stream_valid;
input master_waitrequest;
input [ 1: 0] slave_address;
input [ 3: 0] slave_byteenable;
input slave_read;
input slave_write;
input [31: 0] slave_writedata;
// Bidirectional
// Outputs
output stream_ready;
output [31: 0] master_address;
output master_write;
output [MDW:0] master_writedata;
output [31: 0] slave_readdata;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire inc_address;
wire reset_address;
wire [31: 0] buffer_start_address;
wire dma_enabled;
// Internal Registers
reg [AW: 0] pixel_address;
// State Machine Registers
// Integers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
// Internal Registers
always @(posedge clk)
begin
if (reset | ~dma_enabled)
pixel_address <= 'h0;
else if (reset_address)
pixel_address <= 'h0;
else if (inc_address)
pixel_address <= pixel_address + 1;
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign master_address = buffer_start_address +
pixel_address;
// Internal Assignments
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_video_dma_control_slave DMA_Control_Slave (
// Inputs
.clk (clk),
.reset (reset),
.address (slave_address),
.byteenable (slave_byteenable),
.read (slave_read),
.write (slave_write),
.writedata (slave_writedata),
.swap_addresses_enable (reset_address),
// Bi-Directional
// Outputs
.readdata (slave_readdata),
.current_start_address (buffer_start_address),
.dma_enabled (dma_enabled)
);
defparam
DMA_Control_Slave.DEFAULT_BUFFER_ADDRESS = DEFAULT_BUFFER_ADDRESS,
DMA_Control_Slave.DEFAULT_BACK_BUF_ADDRESS = DEFAULT_BACK_BUF_ADDRESS,
DMA_Control_Slave.WIDTH = WIDTH,
DMA_Control_Slave.HEIGHT = HEIGHT,
DMA_Control_Slave.ADDRESSING_BITS = ADDRESSING_BITS,
DMA_Control_Slave.COLOR_BITS = COLOR_BITS,
DMA_Control_Slave.COLOR_PLANES = COLOR_PLANES,
DMA_Control_Slave.ADDRESSING_MODE = 1'b1,
DMA_Control_Slave.DEFAULT_DMA_ENABLED = DEFAULT_DMA_ENABLED;
altera_up_video_dma_to_memory From_Stream_to_Memory (
// Inputs
.clk (clk),
.reset (reset | ~dma_enabled),
.stream_data (stream_data),
.stream_startofpacket (stream_startofpacket),
.stream_endofpacket (stream_endofpacket),
.stream_empty (stream_empty),
.stream_valid (stream_valid),
.master_waitrequest (master_waitrequest),
// Bidirectional
// Outputs
.stream_ready (stream_ready),
.master_write (master_write),
.master_writedata (master_writedata),
.inc_address (inc_address),
.reset_address (reset_address)
);
defparam
From_Stream_to_Memory.DW = DW,
From_Stream_to_Memory.EW = EW,
From_Stream_to_Memory.MDW = MDW;
endmodule
|
module top;
reg [24*8-1:0] str;
real rval;
reg [7:0] array [0:7];
reg [7:0] array2 [8:15];
reg [7:0] array3 [-1:7];
integer idx, istr;
task clear_array;
for (idx = 0; idx < 8; idx = idx + 1) begin
array[idx] = 0;
array2[idx+8] = 0;
end
endtask
initial begin
// An invalid string.
$readmemb(str, array);
$readmemb(istr, array);
// Check a valid string.
str = "ivltests/readmemb.txt";
$readmemb(str, array);
for (idx = 0; idx < 8; idx = idx + 1) begin
if (array[idx] !== idx + 1) begin
$display("Failed: for index %0d of readmemb 1, expected %0d, got %0d",
idx, idx+1, array[idx]);
end
end
// Check a string with a non-printing character.
str[7:0] = 'd2;
$readmemb(str, array);
// This should load, but will print a warning about the real.
rval = 0.0;
clear_array;
$readmemb("ivltests/readmemb.txt", array, rval);
for (idx = 0; idx < 8; idx = idx + 1) begin
if (array[idx] !== idx + 1) begin
$display("Failed: for index %0d of readmemb 2, expected %0d, got %0d",
idx, idx+1, array[idx]);
end
end
// This should load, but will print a warning about the real.
rval = 7.0;
clear_array;
$readmemb("ivltests/readmemb.txt", array, 0, rval);
for (idx = 0; idx < 8; idx = idx + 1) begin
if (array[idx] !== idx + 1) begin
$display("Failed: for index %0d of readmemb 3, expected %0d, got %0d",
idx, idx+1, array[idx]);
end
end
// These should not load the array.
clear_array;
$readmemb("ivltests/readmemb.txt", array, -1, 7);
for (idx = 0; idx < 8; idx = idx + 1) begin
if (array[idx] !== 0) begin
$display("Failed: for index %0d of readmemb 4, expected 0, got %0d",
idx, array[idx]);
end
end
$readmemb("ivltests/readmemb.txt", array2, 7, 15);
for (idx = 8; idx < 16; idx = idx + 1) begin
if (array2[idx] !== 0) begin
$display("Failed: for index %0d of readmemb 5, expected 0, got %0d",
idx, array2[idx]);
end
end
$readmemb("ivltests/readmemb.txt", array, 0, 8);
for (idx = 0; idx < 8; idx = idx + 1) begin
if (array[idx] !== 0) begin
$display("Failed: for index %0d of readmemb 6, expected 0, got %0d",
idx, array[idx]);
end
end
$readmemb("ivltests/readmemb.txt", array2, 8, 16);
for (idx = 8; idx < 16; idx = idx + 1) begin
if (array2[idx] !== 0) begin
$display("Failed: for index %0d of readmemb 7, expected 0, got %0d",
idx, array2[idx]);
end
end
// Check that a warning is printed if we have the wrong number of values.
clear_array;
$readmemb("ivltests/readmemb.txt", array, 0, 6);
for (idx = 0; idx < 7; idx = idx + 1) begin
if (array[idx] !== idx + 1) begin
$display("Failed: for index %0d of readmemb 8, expected %0d, got %0d",
idx, idx+1, array[idx]);
end
end
if (array[7] !== 0) begin
$display("Failed: for index 7 of readmemb 8, expected 0, got %0d",
array[7]);
end
$readmemb("ivltests/readmemb.txt", array3, -1, 7);
for (idx = -1; idx < 7; idx = idx + 1) begin
if ($signed(array3[idx]) !== idx + 2) begin
$display("Failed: for index %0d of readmemb 9, expected %0d, got %0d",
idx, idx+2, array3[idx]);
end
end
if (array3[7] !== 8'bx) begin
$display("Failed: for index 7 of readmemb 9, expected 'dx, got %0d",
array3[7]);
end
// Check what an invalid token returns.
$readmemb("ivltests/readmem-error.txt", array);
// An invalid string.
str = 'bx;
$readmemh(str, array);
$readmemh(istr, array);
// Check a valid string.
str = "ivltests/readmemh.txt";
$readmemh(str, array);
for (idx = 0; idx < 8; idx = idx + 1) begin
if (array[idx] !== idx + 1) begin
$display("Failed: for index %0d of readmemh 1, expected %0d, got %0d",
idx, idx+1, array[idx]);
end
end
// Check a string with a non-printing character.
str[7:0] = 'd2;
$readmemh(str, array);
// This should load, but will print a warning about the real.
rval = 0.0;
clear_array;
$readmemh("ivltests/readmemh.txt", array, rval);
for (idx = 0; idx < 8; idx = idx + 1) begin
if (array[idx] !== idx + 1) begin
$display("Failed: for index %0d of readmemh 2, expected %0d, got %0d",
idx, idx+1, array[idx]);
end
end
// This should load, but will print a warning about the real.
rval = 7.0;
clear_array;
$readmemh("ivltests/readmemh.txt", array, 0, rval);
for (idx = 0; idx < 8; idx = idx + 1) begin
if (array[idx] !== idx + 1) begin
$display("Failed: for index %0d of readmemh 3, expected %0d, got %0d",
idx, idx+1, array[idx]);
end
end
// These should not load the array.
clear_array;
$readmemh("ivltests/readmemh.txt", array, -1, 7);
for (idx = 0; idx < 8; idx = idx + 1) begin
if (array[idx] !== 0) begin
$display("Failed: for index %0d of readmemh 4, expected 0, got %0d",
idx, array[idx]);
end
end
$readmemh("ivltests/readmemh.txt", array2, 7, 15);
for (idx = 8; idx < 16; idx = idx + 1) begin
if (array2[idx] !== 0) begin
$display("Failed: for index %0d of readmemh 5, expected 0, got %0d",
idx, array2[idx]);
end
end
$readmemh("ivltests/readmemh.txt", array, 0, 8);
for (idx = 0; idx < 8; idx = idx + 1) begin
if (array[idx] !== 0) begin
$display("Failed: for index %0d of readmemh 6, expected 0, got %0d",
idx, array[idx]);
end
end
$readmemh("ivltests/readmemh.txt", array2, 8, 16);
for (idx = 8; idx < 16; idx = idx + 1) begin
if (array2[idx] !== 0) begin
$display("Failed: for index %0d of readmemh 7, expected 0, got %0d",
idx, array2[idx]);
end
end
// Check that a warning is printed if we have the wrong number of values.
clear_array;
$readmemh("ivltests/readmemh.txt", array, 0, 6);
for (idx = 0; idx < 7; idx = idx + 1) begin
if (array[idx] !== idx + 1) begin
$display("Failed: for index %0d of readmemh 8, expected %0d, got %0d",
idx, idx+1, array[idx]);
end
end
if (array[7] !== 0) begin
$display("Failed: for index 7 of readmemh 8, expected 0, got %0d",
array[7]);
end
$readmemh("ivltests/readmemh.txt", array3, -1, 7);
for (idx = -1; idx < 7; idx = idx + 1) begin
if ($signed(array3[idx]) !== idx + 2) begin
$display("Failed: for index %0d of readmemh 9, expected %0d, got %0d",
idx, idx+2, array3[idx]);
end
end
if (array3[7] !== 8'bx) begin
$display("Failed: for index 7 of readmemh 9, expected 'dx, got %0d",
array3[7]);
end
// Check what an invalid token returns.
$readmemh("ivltests/readmem-error.txt", array);
end
endmodule
|
//----------------------------------------------------------------------------
// Title : Testbench for BPM Interlock
//----------------------------------------------------------------------------
// Author : Lucas Maziero Russo
// Company : CNPEM LNLS-DIG
// Created : 2020-06-15
// Platform : FPGA-generic
//-----------------------------------------------------------------------------
// Description: Simulation of the BPM Interlock
//-----------------------------------------------------------------------------
// Copyright (c) 2020 CNPEM
// Licensed under GNU Lesser General Public License (LGPL) v3.0
//-----------------------------------------------------------------------------
// Revisions :
// Date Version Author Description
// 2020-06-15 1.0 lucas.russo Created
//-----------------------------------------------------------------------------
// Simulation timescale
`include "timescale.v"
// Common definitions
`include "defines.v"
// Wishbone Master
`include "wishbone_test_master.v"
// bpm swap Register definitions
`include "regs/wb_orbit_intlk_regs.vh"
module wb_orbit_intlk_tb;
// Local definitions
localparam c_ADC_WIDTH = 16;
localparam c_DECIM_WIDTH = 32;
localparam c_INTLK_LMT_WIDTH = 32;
//**************************************************************************
// Clock generation and reset
//**************************************************************************
wire sys_clk;
wire sys_rstn;
wire sys_rst;
clk_rst cmp_clk_rst(
.clk_sys_o(sys_clk),
.sys_rstn_o(sys_rstn)
);
assign sys_rst = ~sys_rstn;
//**************************************************************************
// Wishbone Master
//**************************************************************************
WB_TEST_MASTER WB0(
.wb_clk (sys_clk)
);
//**************************************************************************
// DUT
//**************************************************************************
reg intlk_en;
reg intlk_clr;
reg intlk_min_sum_en;
reg [c_INTLK_LMT_WIDTH-1:0] intlk_min_sum;
reg intlk_trans_en;
reg intlk_trans_clr;
reg [c_INTLK_LMT_WIDTH-1:0] intlk_trans_max_x;
reg [c_INTLK_LMT_WIDTH-1:0] intlk_trans_max_y;
reg intlk_ang_en;
reg intlk_ang_clr;
reg [c_INTLK_LMT_WIDTH-1:0] intlk_ang_max_x;
reg [c_INTLK_LMT_WIDTH-1:0] intlk_ang_max_y;
reg [c_ADC_WIDTH-1:0] adc_ds_ch0_swap;
reg [c_ADC_WIDTH-1:0] adc_ds_ch1_swap;
reg [c_ADC_WIDTH-1:0] adc_ds_ch2_swap;
reg [c_ADC_WIDTH-1:0] adc_ds_ch3_swap;
reg [0:0] adc_ds_tag;
reg adc_ds_swap_valid;
reg [c_DECIM_WIDTH-1:0] decim_ds_pos_x;
reg [c_DECIM_WIDTH-1:0] decim_ds_pos_y;
reg [c_DECIM_WIDTH-1:0] decim_ds_pos_q;
reg [c_DECIM_WIDTH-1:0] decim_ds_pos_sum;
reg decim_ds_pos_valid;
reg [c_ADC_WIDTH-1:0] adc_us_ch0_swap;
reg [c_ADC_WIDTH-1:0] adc_us_ch1_swap;
reg [c_ADC_WIDTH-1:0] adc_us_ch2_swap;
reg [c_ADC_WIDTH-1:0] adc_us_ch3_swap;
reg [0:0] adc_us_tag;
reg adc_us_swap_valid;
reg [c_DECIM_WIDTH-1:0] decim_us_pos_x;
reg [c_DECIM_WIDTH-1:0] decim_us_pos_y;
reg [c_DECIM_WIDTH-1:0] decim_us_pos_q;
reg [c_DECIM_WIDTH-1:0] decim_us_pos_sum;
reg decim_us_pos_valid;
wire intlk_trans_bigger_x;
wire intlk_trans_bigger_y;
wire intlk_trans_bigger_ltc_x;
wire intlk_trans_bigger_ltc_y;
wire intlk_trans_bigger_any;
wire intlk_trans_bigger_ltc;
wire intlk_trans_bigger;
wire intlk_ang_bigger_x;
wire intlk_ang_bigger_y;
wire intlk_ang_bigger_ltc_x;
wire intlk_ang_bigger_ltc_y;
wire intlk_ang_bigger_any;
wire intlk_ang_bigger_ltc;
wire intlk_ang_bigger;
wire intlk_ltc;
wire intlk;
wb_orbit_intlk #(
.g_ADC_WIDTH (16),
.g_DECIM_WIDTH (32)
)
DUT (
.rst_n_i (sys_rstn),
.clk_i (sys_clk),
.ref_rst_n_i (sys_rstn),
.ref_clk_i (sys_clk),
.wb_adr_i (WB0.wb_addr),
.wb_dat_i (WB0.wb_data_o),
.wb_dat_o (WB0.wb_data_i),
.wb_cyc_i (WB0.wb_cyc),
.wb_sel_i (WB0.wb_bwsel),
.wb_stb_i (WB0.wb_stb),
.wb_we_i (WB0.wb_we),
.wb_ack_o (WB0.wb_ack_i),
.wb_stall_o (),
.fs_clk_ds_i (sys_clk),
.adc_ds_ch0_swap_i (adc_ds_ch0_swap),
.adc_ds_ch1_swap_i (adc_ds_ch1_swap),
.adc_ds_ch2_swap_i (adc_ds_ch2_swap),
.adc_ds_ch3_swap_i (adc_ds_ch3_swap),
.adc_ds_tag_i (adc_ds_tag),
.adc_ds_swap_valid_i (adc_ds_swap_valid),
.decim_ds_pos_x_i (decim_ds_pos_x),
.decim_ds_pos_y_i (decim_ds_pos_y),
.decim_ds_pos_q_i (decim_ds_pos_q),
.decim_ds_pos_sum_i (decim_ds_pos_sum),
.decim_ds_pos_valid_i (decim_ds_pos_valid),
.fs_clk_us_i (sys_clk),
.adc_us_ch0_swap_i (adc_us_ch0_swap),
.adc_us_ch1_swap_i (adc_us_ch1_swap),
.adc_us_ch2_swap_i (adc_us_ch2_swap),
.adc_us_ch3_swap_i (adc_us_ch3_swap),
.adc_us_tag_i (adc_us_tag),
.adc_us_swap_valid_i (adc_us_swap_valid),
.decim_us_pos_x_i (decim_us_pos_x),
.decim_us_pos_y_i (decim_us_pos_y),
.decim_us_pos_q_i (decim_us_pos_q),
.decim_us_pos_sum_i (decim_us_pos_sum),
.decim_us_pos_valid_i (decim_us_pos_valid),
.intlk_trans_bigger_x_o (intlk_trans_bigger_x),
.intlk_trans_bigger_y_o (intlk_trans_bigger_y),
.intlk_trans_bigger_ltc_x_o (intlk_trans_bigger_ltc_x),
.intlk_trans_bigger_ltc_y_o (intlk_trans_bigger_ltc_y),
.intlk_trans_bigger_any_o (intlk_trans_bigger_any),
.intlk_trans_bigger_ltc_o (intlk_trans_bigger_ltc),
.intlk_trans_bigger_o (intlk_trans_bigger),
.intlk_ang_bigger_x_o (intlk_ang_bigger_x),
.intlk_ang_bigger_y_o (intlk_ang_bigger_y),
.intlk_ang_bigger_ltc_x_o (intlk_ang_bigger_ltc_x),
.intlk_ang_bigger_ltc_y_o (intlk_ang_bigger_ltc_y),
.intlk_ang_bigger_any_o (intlk_ang_bigger_any),
.intlk_ang_bigger_ltc_o (intlk_ang_bigger_ltc),
.intlk_ang_bigger_o (intlk_ang_bigger),
.intlk_ltc_o (intlk_ltc),
.intlk_o (intlk)
);
//**************************************************************************
// Interlock test signals
//**************************************************************************
integer test_id;
reg test_in_progress;
reg test_intlk_en;
reg test_intlk_min_sum_en;
reg [c_INTLK_LMT_WIDTH-1:0] test_intlk_min_sum;
reg test_intlk_trans_en;
reg [c_INTLK_LMT_WIDTH-1:0] test_intlk_trans_max_x;
reg [c_INTLK_LMT_WIDTH-1:0] test_intlk_trans_max_y;
reg test_intlk_ang_en;
reg [c_INTLK_LMT_WIDTH-1:0] test_intlk_ang_max_x;
reg [c_INTLK_LMT_WIDTH-1:0] test_intlk_ang_max_y;
reg [c_DECIM_WIDTH-1:0] test_decim_ds_pos_x;
reg [c_DECIM_WIDTH-1:0] test_decim_ds_pos_y;
reg [c_DECIM_WIDTH-1:0] test_decim_ds_pos_q;
reg [c_DECIM_WIDTH-1:0] test_decim_ds_pos_sum;
reg [c_DECIM_WIDTH-1:0] test_decim_us_pos_x;
reg [c_DECIM_WIDTH-1:0] test_decim_us_pos_y;
reg [c_DECIM_WIDTH-1:0] test_decim_us_pos_q;
reg [c_DECIM_WIDTH-1:0] test_decim_us_pos_sum;
reg test_intlk_status;
//**************************************************************************
// Stimulus to DUT
//**************************************************************************
initial begin
intlk_en = 1'b1;
intlk_clr = 1'b0;
intlk_min_sum_en = 1'b0;
intlk_min_sum = 'h0;
intlk_trans_en = 1'b1;
intlk_trans_clr = 1'b0;
// 1mm = 1000000 nm = F4240h
intlk_trans_max_x = 'h10_0000;
intlk_trans_max_y = 'h10_0000;
intlk_ang_en = 1'b1;
intlk_ang_clr = 1'b0;
// 200 urad * 7m (distance between BPMs) = 1_400_000 nm = 155CC0h
intlk_ang_max_x = 'h1_55CC0;
intlk_ang_max_y = 'h1_55CC0;
adc_ds_ch0_swap = 'h0;
adc_ds_ch1_swap = 'h0;
adc_ds_ch2_swap = 'h0;
adc_ds_ch3_swap = 'h0;
adc_ds_tag = 'h0;
adc_ds_swap_valid = 1'b0;
decim_ds_pos_x = 'h0;
decim_ds_pos_y = 'h0;
decim_ds_pos_q = 'h0;
decim_ds_pos_sum = 'h0;
decim_ds_pos_valid = 1'b0;
adc_us_ch0_swap = 'h0;
adc_us_ch1_swap = 'h0;
adc_us_ch2_swap = 'h0;
adc_us_ch3_swap = 'h0;
adc_us_tag = 'h0;
adc_us_swap_valid = 1'b0;
decim_us_pos_x = 'h0;
decim_us_pos_y = 'h0;
decim_us_pos_q = 'h0;
decim_us_pos_sum = 'h0;
decim_us_pos_valid = 1'b0;
$display("-----------------------------------");
$display("@%0d: Simulation of BPM Interlock starting!", $time);
$display("-----------------------------------");
$display("-----------------------------------");
$display("@%0d: Initialization Begin", $time);
$display("-----------------------------------");
$display("-----------------------------------");
$display("@%0d: Waiting for all resets...", $time);
$display("-----------------------------------");
wait (WB0.ready);
wait (sys_rstn);
$display("@%0d: Reset done!", $time);
@(posedge sys_clk);
$display("-------------------------------------");
$display("@%0d: Waiting for interlock clear...", $time);
$display("-------------------------------------");
intlk_clr = 1'b0;
intlk_trans_clr = 1'b0;
intlk_ang_clr = 1'b0;
@(posedge sys_clk);
$display("@%0d: Interlock clear done!", $time);
$display("-------------------------------------");
$display("@%0d: Initialization Done!", $time);
$display("-------------------------------------");
@(posedge sys_clk);
////////////////////////
// TEST #1
// Translation interlock:
// smaller than threshold X
////////////////////////
test_id = 1;
test_intlk_en = 1'b1;
test_intlk_min_sum_en = 1'b0;
test_intlk_min_sum = 'h0;
test_intlk_trans_en = 1'b1;
test_intlk_trans_max_x = 'h10_0000;
test_intlk_trans_max_y = 'h10_0000;
test_intlk_ang_en = 1'b0;
test_intlk_ang_max_x = 'h1_55CC0;
test_intlk_ang_max_y = 'h1_55CC0;
test_decim_ds_pos_x = 'h100;
test_decim_ds_pos_y = 'h0001_0000;
test_decim_ds_pos_q = 'h0;
test_decim_ds_pos_sum = 'h0;
test_decim_us_pos_x = 'h100;
test_decim_us_pos_y = 'h0001_0000;
test_decim_us_pos_q = 'h0;
test_decim_us_pos_sum = 'h0;
test_intlk_status = 1'b0;
wb_intlk_transaction(
test_id,
test_intlk_en,
test_intlk_min_sum_en,
test_intlk_min_sum,
test_intlk_trans_en ,
test_intlk_trans_max_x,
test_intlk_trans_max_y,
test_intlk_ang_en ,
test_intlk_ang_max_x,
test_intlk_ang_max_y,
test_decim_ds_pos_x,
test_decim_ds_pos_y,
test_decim_ds_pos_q,
test_decim_ds_pos_sum,
test_decim_us_pos_x,
test_decim_us_pos_y,
test_decim_us_pos_q,
test_decim_us_pos_sum,
test_intlk_status
);
////////////////////////
// TEST #2
// Translation interlock:
// bigger than threshold X
////////////////////////
test_id = 2;
test_intlk_en = 1'b1;
test_intlk_min_sum_en = 1'b0;
test_intlk_min_sum = 'h0;
test_intlk_trans_en = 1'b1;
test_intlk_trans_max_x = 'h10_0000;
test_intlk_trans_max_y = 'h10_0000;
test_intlk_ang_en = 1'b0;
test_intlk_ang_max_x = 'h1_55CC0;
test_intlk_ang_max_y = 'h1_55CC0;
test_decim_ds_pos_x = 'h0100_0000;
test_decim_ds_pos_y = 'h0001_0000;
test_decim_ds_pos_q = 'h0;
test_decim_ds_pos_sum = 'h0;
test_decim_us_pos_x = 'h0100_0000;
test_decim_us_pos_y = 'h0001_0000;
test_decim_us_pos_q = 'h0;
test_decim_us_pos_sum = 'h0;
test_intlk_status = 1'b1;
wb_intlk_transaction(
test_id,
test_intlk_en,
test_intlk_min_sum_en,
test_intlk_min_sum,
test_intlk_trans_en ,
test_intlk_trans_max_x,
test_intlk_trans_max_y,
test_intlk_ang_en ,
test_intlk_ang_max_x,
test_intlk_ang_max_y,
test_decim_ds_pos_x,
test_decim_ds_pos_y,
test_decim_ds_pos_q,
test_decim_ds_pos_sum,
test_decim_us_pos_x,
test_decim_us_pos_y,
test_decim_us_pos_q,
test_decim_us_pos_sum,
test_intlk_status
);
////////////////////////
// TEST #3
// Translation interlock:
// equal than threshold X
////////////////////////
test_id = 3;
test_intlk_en = 1'b1;
test_intlk_min_sum_en = 1'b0;
test_intlk_min_sum = 'h0;
test_intlk_trans_en = 1'b1;
test_intlk_trans_max_x = 'h10_0000;
test_intlk_trans_max_y = 'h10_0000;
test_intlk_ang_en = 1'b0;
test_intlk_ang_max_x = 'h1_55CC0;
test_intlk_ang_max_y = 'h1_55CC0;
test_decim_ds_pos_x = 'h0020_0000;
test_decim_ds_pos_y = 'h0001_0000;
test_decim_ds_pos_q = 'h0;
test_decim_ds_pos_sum = 'h0;
test_decim_us_pos_x = 'h0008_0000;
test_decim_us_pos_y = 'h0001_0000;
test_decim_us_pos_q = 'h0;
test_decim_us_pos_sum = 'h0;
test_intlk_status = 1'b1;
wb_intlk_transaction(
test_id,
test_intlk_en,
test_intlk_min_sum_en,
test_intlk_min_sum,
test_intlk_trans_en ,
test_intlk_trans_max_x,
test_intlk_trans_max_y,
test_intlk_ang_en ,
test_intlk_ang_max_x,
test_intlk_ang_max_y,
test_decim_ds_pos_x,
test_decim_ds_pos_y,
test_decim_ds_pos_q,
test_decim_ds_pos_sum,
test_decim_us_pos_x,
test_decim_us_pos_y,
test_decim_us_pos_q,
test_decim_us_pos_sum,
test_intlk_status
);
////////////////////////
// TEST #4
// No translation interlock:
// X/Y within limits
////////////////////////
test_id = 4;
test_intlk_en = 1'b1;
test_intlk_min_sum_en = 1'b0;
test_intlk_min_sum = 'h0;
test_intlk_trans_en = 1'b1;
test_intlk_trans_max_x = 'h10_0000;
test_intlk_trans_max_y = 'h10_0000;
test_intlk_ang_en = 1'b0;
test_intlk_ang_max_x = 'h1_55CC0;
test_intlk_ang_max_y = 'h1_55CC0;
test_decim_ds_pos_x = 'h0002_0000;
test_decim_ds_pos_y = 'h0003_0000;
test_decim_ds_pos_q = 'h0;
test_decim_ds_pos_sum = 'h0;
test_decim_us_pos_x = 'h0004_0000;
test_decim_us_pos_y = 'h0008_0000;
test_decim_us_pos_q = 'h0;
test_decim_us_pos_sum = 'h0;
test_intlk_status = 1'b0;
wb_intlk_transaction(
test_id,
test_intlk_en,
test_intlk_min_sum_en,
test_intlk_min_sum,
test_intlk_trans_en ,
test_intlk_trans_max_x,
test_intlk_trans_max_y,
test_intlk_ang_en ,
test_intlk_ang_max_x,
test_intlk_ang_max_y,
test_decim_ds_pos_x,
test_decim_ds_pos_y,
test_decim_ds_pos_q,
test_decim_ds_pos_sum,
test_decim_us_pos_x,
test_decim_us_pos_y,
test_decim_us_pos_q,
test_decim_us_pos_sum,
test_intlk_status
);
////////////////////////
// TEST #5
// Minimum sum interlock:
// X/Y outside limits., but sum too small
////////////////////////
test_id = 5;
test_intlk_en = 1'b1;
test_intlk_min_sum_en = 1'b1;
test_intlk_min_sum = 'h0_1000;
test_intlk_trans_en = 1'b1;
test_intlk_trans_max_x = 'h10_0000;
test_intlk_trans_max_y = 'h10_0000;
test_intlk_ang_en = 1'b0;
test_intlk_ang_max_x = 'h1_55CC0;
test_intlk_ang_max_y = 'h1_55CC0;
test_decim_ds_pos_x = 'h0100_0000;
test_decim_ds_pos_y = 'h0100_0000;
test_decim_ds_pos_q = 'h0;
test_decim_ds_pos_sum = 'h0000_0100;
test_decim_us_pos_x = 'h0100_0000;
test_decim_us_pos_y = 'h0100_0000;
test_decim_us_pos_q = 'h0;
test_decim_us_pos_sum = 'h0000_0500;
test_intlk_status = 1'b0;
wb_intlk_transaction(
test_id,
test_intlk_en,
test_intlk_min_sum_en,
test_intlk_min_sum,
test_intlk_trans_en ,
test_intlk_trans_max_x,
test_intlk_trans_max_y,
test_intlk_ang_en ,
test_intlk_ang_max_x,
test_intlk_ang_max_y,
test_decim_ds_pos_x,
test_decim_ds_pos_y,
test_decim_ds_pos_q,
test_decim_ds_pos_sum,
test_decim_us_pos_x,
test_decim_us_pos_y,
test_decim_us_pos_q,
test_decim_us_pos_sum,
test_intlk_status
);
////////////////////////
// TEST #6
// Negative position
// X/Y within limits.
////////////////////////
test_id = 6;
test_intlk_en = 1'b1;
test_intlk_min_sum_en = 1'b1;
test_intlk_min_sum = 'h0_1000;
test_intlk_trans_en = 1'b1;
test_intlk_trans_max_x = 'h10_0000;
test_intlk_trans_max_y = 'h10_0000;
test_intlk_ang_en = 1'b0;
test_intlk_ang_max_x = 'h1_55CC0;
test_intlk_ang_max_y = 'h1_55CC0;
test_decim_ds_pos_x = 'h0010_0000;
test_decim_ds_pos_y = 'h0010_0000;
test_decim_ds_pos_q = 'h0;
test_decim_ds_pos_sum = 'h0001_0000;
test_decim_us_pos_x = 'hFFFF_FF00;
test_decim_us_pos_y = 'hFFFF_FF00;
test_decim_us_pos_q = 'h0;
test_decim_us_pos_sum = 'h0001_0000;
test_intlk_status = 1'b0;
wb_intlk_transaction(
test_id,
test_intlk_en,
test_intlk_min_sum_en,
test_intlk_min_sum,
test_intlk_trans_en ,
test_intlk_trans_max_x,
test_intlk_trans_max_y,
test_intlk_ang_en ,
test_intlk_ang_max_x,
test_intlk_ang_max_y,
test_decim_ds_pos_x,
test_decim_ds_pos_y,
test_decim_ds_pos_q,
test_decim_ds_pos_sum,
test_decim_us_pos_x,
test_decim_us_pos_y,
test_decim_us_pos_q,
test_decim_us_pos_sum,
test_intlk_status
);
////////////////////////
// TEST #7
// Negative position
// X/Y within limits.
////////////////////////
test_id = 7;
test_intlk_en = 1'b1;
test_intlk_min_sum_en = 1'b1;
test_intlk_min_sum = 'h0_1000;
test_intlk_trans_en = 1'b1;
test_intlk_trans_max_x = 'h0000_0000;
test_intlk_trans_max_y = 'h0000_0000;
test_intlk_ang_en = 1'b0;
test_intlk_ang_max_x = 'h1_55CC0;
test_intlk_ang_max_y = 'h1_55CC0;
test_decim_ds_pos_x = 'hFFFF_FF00;
test_decim_ds_pos_y = 'hFFFF_FF00;
test_decim_ds_pos_q = 'h0;
test_decim_ds_pos_sum = 'h0001_0000;
test_decim_us_pos_x = 'hFFFF_FF00;
test_decim_us_pos_y = 'hFFFF_FF00;
test_decim_us_pos_q = 'h0;
test_decim_us_pos_sum = 'h0001_0000;
test_intlk_status = 1'b0;
wb_intlk_transaction(
test_id,
test_intlk_en,
test_intlk_min_sum_en,
test_intlk_min_sum,
test_intlk_trans_en ,
test_intlk_trans_max_x,
test_intlk_trans_max_y,
test_intlk_ang_en ,
test_intlk_ang_max_x,
test_intlk_ang_max_y,
test_decim_ds_pos_x,
test_decim_ds_pos_y,
test_decim_ds_pos_q,
test_decim_ds_pos_sum,
test_decim_us_pos_x,
test_decim_us_pos_y,
test_decim_us_pos_q,
test_decim_us_pos_sum,
test_intlk_status
);
$display("Simulation Done!");
$display("All Tests Passed!");
$display("---------------------------------------------");
$finish;
end
///////////////////////////////////////////////////////////////////////////
// Functions
///////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Tasks
/////////////////////////////////////////////////////////////////////////////
task wb_busy_wait;
input [`WB_ADDRESS_BUS_WIDTH-1:0] addr;
input [`WB_DATA_BUS_WIDTH-1:0] mask;
input [`WB_DATA_BUS_WIDTH-1:0] offset;
input verbose;
reg [`WB_DATA_BUS_WIDTH-1:0] tmp_reg0;
begin
WB0.monitor_bus(1'b0);
WB0.verbose(1'b0);
WB0.read32(addr, tmp_reg0);
while (((tmp_reg0 & mask) >> offset) != 'h1) begin
if (verbose)
$write(".");
@(posedge sys_clk);
WB0.read32(addr, tmp_reg0);
end
WB0.monitor_bus(1'b1);
WB0.verbose(1'b1);
end
endtask
task wb_intlk_transaction;
input integer test_id;
input test_intlk_en;
input test_intlk_min_sum_en;
input [c_INTLK_LMT_WIDTH-1:0] test_intlk_min_sum;
input test_intlk_trans_en;
input [c_INTLK_LMT_WIDTH-1:0] test_intlk_trans_max_x;
input [c_INTLK_LMT_WIDTH-1:0] test_intlk_trans_max_y;
input test_intlk_ang_en;
input [c_INTLK_LMT_WIDTH-1:0] test_intlk_ang_max_x;
input [c_INTLK_LMT_WIDTH-1:0] test_intlk_ang_max_y;
input [c_DECIM_WIDTH-1:0] test_decim_ds_pos_x;
input [c_DECIM_WIDTH-1:0] test_decim_ds_pos_y;
input [c_DECIM_WIDTH-1:0] test_decim_ds_pos_q;
input [c_DECIM_WIDTH-1:0] test_decim_ds_pos_sum;
input [c_DECIM_WIDTH-1:0] test_decim_us_pos_x;
input [c_DECIM_WIDTH-1:0] test_decim_us_pos_y;
input [c_DECIM_WIDTH-1:0] test_decim_us_pos_q;
input [c_DECIM_WIDTH-1:0] test_decim_us_pos_sum;
input test_intlk_status;
reg [`WB_DATA_BUS_WIDTH:0] wb_reg;
reg [`WB_DATA_BUS_WIDTH:0] intlk_wb;
integer err;
integer err_intlk;
integer err_wb;
begin
$display("#############################");
$display("######## TEST #%03d ######", test_id);
$display("#############################");
$display("## Interlock enable = %d", test_intlk_en);
$display("## Interlock minimum sum enable = %d", test_intlk_min_sum_en);
$display("## Interlock minimum sum threshold = %03d", test_intlk_min_sum);
$display("## Interlock translation enable = %d", test_intlk_trans_en);
$display("## Interlock translation MAX X = %03d", test_intlk_trans_max_x);
$display("## Interlock translation MAX Y = %03d", test_intlk_trans_max_y);
$display("## Interlock angular enable = %d", test_intlk_ang_en);
$display("## Interlock angular MAX X = %03d", test_intlk_ang_max_x);
$display("## Interlock angular MAX Y = %03d", test_intlk_ang_max_y);
$display("Setting interlock parameters scenario");
$display("Setting minimum sum threshold");
@(posedge sys_clk);
WB0.write32(`ADDR_ORBIT_INTLK_MIN_SUM >> `WB_WORD_ACC, test_intlk_min_sum);
$display("Setting minimum sum enable");
@(posedge sys_clk);
WB0.read32(`ADDR_ORBIT_INTLK_CTRL, wb_reg);
WB0.write32(`ADDR_ORBIT_INTLK_CTRL >> `WB_WORD_ACC, wb_reg | (test_intlk_min_sum_en << `ORBIT_INTLK_CTRL_MIN_SUM_EN_OFFSET));
$display("Setting translation threshold X");
@(posedge sys_clk);
WB0.write32(`ADDR_ORBIT_INTLK_TRANS_MAX_X >> `WB_WORD_ACC, test_intlk_trans_max_x);
$display("Setting translation threshold Y");
@(posedge sys_clk);
WB0.write32(`ADDR_ORBIT_INTLK_TRANS_MAX_Y >> `WB_WORD_ACC, test_intlk_trans_max_y);
$display("Setting translation threshold enable");
@(posedge sys_clk);
WB0.read32(`ADDR_ORBIT_INTLK_CTRL, wb_reg);
WB0.write32(`ADDR_ORBIT_INTLK_CTRL >> `WB_WORD_ACC, wb_reg | (test_intlk_trans_en << `ORBIT_INTLK_CTRL_TRANS_EN_OFFSET));
$display("Setting angular threshold X");
@(posedge sys_clk);
WB0.write32(`ADDR_ORBIT_INTLK_ANG_MAX_X >> `WB_WORD_ACC, test_intlk_ang_max_x);
$display("Setting angular threshold Y");
@(posedge sys_clk);
WB0.write32(`ADDR_ORBIT_INTLK_ANG_MAX_Y >> `WB_WORD_ACC, test_intlk_ang_max_y);
$display("Setting angular threshold enable");
@(posedge sys_clk);
WB0.read32(`ADDR_ORBIT_INTLK_CTRL, wb_reg);
WB0.write32(`ADDR_ORBIT_INTLK_CTRL >> `WB_WORD_ACC, wb_reg | (test_intlk_ang_en << `ORBIT_INTLK_CTRL_ANG_EN_OFFSET));
$display("Setting interlock enable");
@(posedge sys_clk);
WB0.read32(`ADDR_ORBIT_INTLK_CTRL, wb_reg);
WB0.write32(`ADDR_ORBIT_INTLK_CTRL >> `WB_WORD_ACC, wb_reg | (test_intlk_en << `ORBIT_INTLK_CTRL_EN_OFFSET));
test_in_progress = 1'b1;
$display("Setting DECIM downstream/upstream positions");
@(posedge sys_clk);
decim_ds_pos_x = test_decim_ds_pos_x;
decim_ds_pos_y = test_decim_ds_pos_y;
decim_ds_pos_q = test_decim_ds_pos_q;
decim_ds_pos_sum = test_decim_ds_pos_sum;
decim_ds_pos_valid = 1'b1;
decim_us_pos_x = test_decim_us_pos_x;
decim_us_pos_y = test_decim_us_pos_y;
decim_us_pos_q = test_decim_us_pos_q;
decim_us_pos_sum = test_decim_us_pos_sum;
decim_us_pos_valid = 1'b1;
$display("Setting DECIM downstream/upstream positions back to zero");
@(posedge sys_clk);
decim_ds_pos_x = 'h0;
decim_ds_pos_y = 'h0;
decim_ds_pos_q = 'h0;
decim_ds_pos_sum = 'h0;
decim_ds_pos_valid = 1'b0;
decim_us_pos_x = 'h0;
decim_us_pos_y = 'h0;
decim_us_pos_q = 'h0;
decim_us_pos_sum = 'h0;
decim_us_pos_valid = 1'b0;
$display("Waiting 20 clock cycles so we have time to detect the trip");
@(posedge sys_clk);
repeat (20) begin
@(posedge sys_clk);
$write(".");
end
err = 0;
err_intlk = 0;
err_wb = 0;
$display("\n");
$display("Reading interlock register");
WB0.read32(`ADDR_ORBIT_INTLK_STS >> `WB_WORD_ACC, wb_reg);
@(posedge sys_clk);
if (test_intlk_status == intlk_ltc) begin
$display("Interlock module correctly identified a condition: expected %d/ got %d", test_intlk_status, intlk_ltc);
end else begin
$display("Interlock module DID NOT correctly identified a condition: expected %d/ got %d", test_intlk_status, intlk_ltc);
err = 1;
err_intlk = 1;
end
intlk_wb = (wb_reg & `ORBIT_INTLK_STS_INTLK_LTC) >> `ORBIT_INTLK_STS_INTLK_LTC_OFFSET;
if (test_intlk_status == intlk_wb) begin
$display("Wishbone register correctly identified a condition: expected %d/ got %d", test_intlk_status, intlk_wb);
end else begin
$display("Wishbone register DID NOT correctly identified a condition: expected %d/ got %d", test_intlk_status, intlk_wb);
err = 1;
err_wb = 1;
end
if (err) begin
$display("TEST #%03d: FAIL!", test_id);
$finish;
end else begin
$display("TEST #%03d: PASS!", test_id);
end
@(posedge sys_clk);
test_in_progress = 1'b0;
$display("Clearing interlock flags");
$display("Clearing translation interlock flag");
@(posedge sys_clk);
WB0.write32(`ADDR_ORBIT_INTLK_CTRL >> `WB_WORD_ACC, `ORBIT_INTLK_CTRL_TRANS_CLR);
$display("Clearing angular interlock flag");
@(posedge sys_clk);
WB0.write32(`ADDR_ORBIT_INTLK_CTRL >> `WB_WORD_ACC, `ORBIT_INTLK_CTRL_ANG_CLR);
$display("Clearing interlock flag");
@(posedge sys_clk);
WB0.write32(`ADDR_ORBIT_INTLK_CTRL >> `WB_WORD_ACC, `ORBIT_INTLK_CTRL_CLR);
// give some time for all the modules that need a reset between tests
repeat (2) begin
@(posedge sys_clk);
end
$display("\n");
end
endtask
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Mon Feb 27 15:46:56 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// c:/ZyboIP/examples/ov7670_passthrough/ov7670_passthrough.srcs/sources_1/bd/system/ip/system_zybo_hdmi_0_0/system_zybo_hdmi_0_0_sim_netlist.v
// Design : system_zybo_hdmi_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_zybo_hdmi_0_0,zybo_hdmi,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "zybo_hdmi,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_zybo_hdmi_0_0
(clk_125,
clk_25,
hsync,
vsync,
active,
rgb,
tmds,
tmdsb,
hdmi_cec,
hdmi_hpd,
hdmi_out_en);
input clk_125;
input clk_25;
input hsync;
input vsync;
input active;
input [23:0]rgb;
output [3:0]tmds;
output [3:0]tmdsb;
input hdmi_cec;
input hdmi_hpd;
output hdmi_out_en;
wire \<const1> ;
wire active;
wire clk_125;
wire clk_25;
wire hsync;
wire [23:0]rgb;
(* SLEW = "SLOW" *) wire [3:0]tmds;
(* SLEW = "SLOW" *) wire [3:0]tmdsb;
wire vsync;
assign hdmi_out_en = \<const1> ;
system_zybo_hdmi_0_0_zybo_hdmi U0
(.active(active),
.clk_125(clk_125),
.clk_25(clk_25),
.hsync(hsync),
.rgb(rgb),
.tmds(tmds),
.tmdsb(tmdsb),
.vsync(vsync));
VCC VCC
(.P(\<const1> ));
endmodule
(* ORIG_REF_NAME = "TMDS_encoder" *)
module system_zybo_hdmi_0_0_TMDS_encoder
(SR,
D,
Q,
rgb,
active,
hsync,
vsync,
shift_blue,
\shift_clock_reg[5] ,
clk_25);
output [0:0]SR;
output [7:0]D;
output [1:0]Q;
input [7:0]rgb;
input active;
input hsync;
input vsync;
input [7:0]shift_blue;
input \shift_clock_reg[5] ;
input clk_25;
wire [7:0]D;
wire [1:0]Q;
wire [0:0]SR;
wire active;
wire clk_25;
wire \dc_bias[0]_i_1__1_n_0 ;
wire \dc_bias[0]_i_2__1_n_0 ;
wire \dc_bias[0]_i_3__1_n_0 ;
wire \dc_bias[0]_i_4__1_n_0 ;
wire \dc_bias[0]_i_5__0_n_0 ;
wire \dc_bias[1]_i_1__0_n_0 ;
wire \dc_bias[1]_i_2__1_n_0 ;
wire \dc_bias[1]_i_3__1_n_0 ;
wire \dc_bias[1]_i_4__1_n_0 ;
wire \dc_bias[1]_i_5__1_n_0 ;
wire \dc_bias[1]_i_6__0_n_0 ;
wire \dc_bias[1]_i_7__1_n_0 ;
wire \dc_bias[1]_i_8_n_0 ;
wire \dc_bias[1]_i_9__0_n_0 ;
wire \dc_bias[2]_i_10_n_0 ;
wire \dc_bias[2]_i_11__1_n_0 ;
wire \dc_bias[2]_i_12__0_n_0 ;
wire \dc_bias[2]_i_13__0_n_0 ;
wire \dc_bias[2]_i_14__0_n_0 ;
wire \dc_bias[2]_i_15__0_n_0 ;
wire \dc_bias[2]_i_1__1_n_0 ;
wire \dc_bias[2]_i_2__0_n_0 ;
wire \dc_bias[2]_i_3__1_n_0 ;
wire \dc_bias[2]_i_4__1_n_0 ;
wire \dc_bias[2]_i_5__1_n_0 ;
wire \dc_bias[2]_i_6__1_n_0 ;
wire \dc_bias[2]_i_7__0_n_0 ;
wire \dc_bias[2]_i_8__1_n_0 ;
wire \dc_bias[2]_i_9__0_n_0 ;
wire \dc_bias[3]_i_10__1_n_0 ;
wire \dc_bias[3]_i_11__1_n_0 ;
wire \dc_bias[3]_i_12__1_n_0 ;
wire \dc_bias[3]_i_13__0_n_0 ;
wire \dc_bias[3]_i_14__0_n_0 ;
wire \dc_bias[3]_i_15__1_n_0 ;
wire \dc_bias[3]_i_16__0_n_0 ;
wire \dc_bias[3]_i_17__0_n_0 ;
wire \dc_bias[3]_i_18__0_n_0 ;
wire \dc_bias[3]_i_19__1_n_0 ;
wire \dc_bias[3]_i_1__1_n_0 ;
wire \dc_bias[3]_i_20__0_n_0 ;
wire \dc_bias[3]_i_21_n_0 ;
wire \dc_bias[3]_i_22__1_n_0 ;
wire \dc_bias[3]_i_23__0_n_0 ;
wire \dc_bias[3]_i_24__1_n_0 ;
wire \dc_bias[3]_i_25__1_n_0 ;
wire \dc_bias[3]_i_26__1_n_0 ;
wire \dc_bias[3]_i_27__1_n_0 ;
wire \dc_bias[3]_i_28__0_n_0 ;
wire \dc_bias[3]_i_29__0_n_0 ;
wire \dc_bias[3]_i_2__1_n_0 ;
wire \dc_bias[3]_i_30__0_n_0 ;
wire \dc_bias[3]_i_31__0_n_0 ;
wire \dc_bias[3]_i_32__0_n_0 ;
wire \dc_bias[3]_i_33__0_n_0 ;
wire \dc_bias[3]_i_3__1_n_0 ;
wire \dc_bias[3]_i_4__1_n_0 ;
wire \dc_bias[3]_i_5_n_0 ;
wire \dc_bias[3]_i_6__1_n_0 ;
wire \dc_bias[3]_i_7__1_n_0 ;
wire \dc_bias[3]_i_8__1_n_0 ;
wire \dc_bias[3]_i_9__1_n_0 ;
wire \dc_bias_reg_n_0_[0] ;
wire \dc_bias_reg_n_0_[1] ;
wire \dc_bias_reg_n_0_[2] ;
wire \encoded[0]_i_1__1_n_0 ;
wire \encoded[1]_i_1__1_n_0 ;
wire \encoded[1]_i_2_n_0 ;
wire \encoded[2]_i_1__1_n_0 ;
wire \encoded[2]_i_2_n_0 ;
wire \encoded[3]_i_1__1_n_0 ;
wire \encoded[3]_i_2_n_0 ;
wire \encoded[4]_i_1__1_n_0 ;
wire \encoded[4]_i_2_n_0 ;
wire \encoded[5]_i_1__1_n_0 ;
wire \encoded[5]_i_2_n_0 ;
wire \encoded[6]_i_1__1_n_0 ;
wire \encoded[6]_i_2__1_n_0 ;
wire \encoded[7]_i_1__1_n_0 ;
wire \encoded[7]_i_2__1_n_0 ;
wire \encoded[8]_i_1__1_n_0 ;
wire \encoded[9]_i_1__1_n_0 ;
wire \encoded_reg_n_0_[0] ;
wire \encoded_reg_n_0_[1] ;
wire \encoded_reg_n_0_[2] ;
wire \encoded_reg_n_0_[3] ;
wire \encoded_reg_n_0_[4] ;
wire \encoded_reg_n_0_[5] ;
wire \encoded_reg_n_0_[6] ;
wire \encoded_reg_n_0_[7] ;
wire hsync;
wire p_1_in;
wire [7:0]rgb;
wire [7:0]shift_blue;
wire \shift_clock_reg[5] ;
wire vsync;
LUT6 #(
.INIT(64'h9F90909F909F9F90))
\dc_bias[0]_i_1__1
(.I0(\dc_bias_reg_n_0_[0] ),
.I1(\dc_bias[0]_i_2__1_n_0 ),
.I2(\dc_bias[3]_i_5_n_0 ),
.I3(\dc_bias[2]_i_2__0_n_0 ),
.I4(\dc_bias[0]_i_3__1_n_0 ),
.I5(\dc_bias[0]_i_4__1_n_0 ),
.O(\dc_bias[0]_i_1__1_n_0 ));
LUT5 #(
.INIT(32'h69969669))
\dc_bias[0]_i_2__1
(.I0(\dc_bias[3]_i_3__1_n_0 ),
.I1(\encoded[7]_i_2__1_n_0 ),
.I2(\dc_bias[0]_i_5__0_n_0 ),
.I3(rgb[1]),
.I4(rgb[3]),
.O(\dc_bias[0]_i_2__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT5 #(
.INIT(32'h69969669))
\dc_bias[0]_i_3__1
(.I0(\encoded[3]_i_2_n_0 ),
.I1(rgb[5]),
.I2(rgb[0]),
.I3(\dc_bias_reg_n_0_[0] ),
.I4(rgb[7]),
.O(\dc_bias[0]_i_3__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT2 #(
.INIT(4'h9))
\dc_bias[0]_i_4__1
(.I0(rgb[2]),
.I1(\dc_bias[3]_i_3__1_n_0 ),
.O(\dc_bias[0]_i_4__1_n_0 ));
LUT6 #(
.INIT(64'h6696969999696966))
\dc_bias[0]_i_5__0
(.I0(rgb[6]),
.I1(rgb[4]),
.I2(\dc_bias[2]_i_13__0_n_0 ),
.I3(\dc_bias[3]_i_13__0_n_0 ),
.I4(\dc_bias[2]_i_12__0_n_0 ),
.I5(\encoded[3]_i_2_n_0 ),
.O(\dc_bias[0]_i_5__0_n_0 ));
LUT6 #(
.INIT(64'hC5C0CFCACFCAC5C0))
\dc_bias[1]_i_1__0
(.I0(\dc_bias[2]_i_2__0_n_0 ),
.I1(\dc_bias[1]_i_2__1_n_0 ),
.I2(\dc_bias[3]_i_5_n_0 ),
.I3(\dc_bias[1]_i_3__1_n_0 ),
.I4(\dc_bias[1]_i_4__1_n_0 ),
.I5(\dc_bias[1]_i_5__1_n_0 ),
.O(\dc_bias[1]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'h6F60606F606F6F60))
\dc_bias[1]_i_2__1
(.I0(\dc_bias[1]_i_6__0_n_0 ),
.I1(\dc_bias[1]_i_7__1_n_0 ),
.I2(\dc_bias[3]_i_3__1_n_0 ),
.I3(\dc_bias[1]_i_8_n_0 ),
.I4(\dc_bias[1]_i_9__0_n_0 ),
.I5(\dc_bias[3]_i_17__0_n_0 ),
.O(\dc_bias[1]_i_2__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT4 #(
.INIT(16'h5695))
\dc_bias[1]_i_3__1
(.I0(\dc_bias[1]_i_7__1_n_0 ),
.I1(\dc_bias[0]_i_2__1_n_0 ),
.I2(\dc_bias_reg_n_0_[0] ),
.I3(\dc_bias[3]_i_3__1_n_0 ),
.O(\dc_bias[1]_i_3__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'hD7BE2841))
\dc_bias[1]_i_4__1
(.I0(rgb[2]),
.I1(rgb[1]),
.I2(rgb[0]),
.I3(\dc_bias[3]_i_3__1_n_0 ),
.I4(\dc_bias[2]_i_10_n_0 ),
.O(\dc_bias[1]_i_4__1_n_0 ));
LUT6 #(
.INIT(64'hEB7D7DEB7D14147D))
\dc_bias[1]_i_5__1
(.I0(rgb[7]),
.I1(\dc_bias_reg_n_0_[0] ),
.I2(rgb[0]),
.I3(rgb[5]),
.I4(\encoded[3]_i_2_n_0 ),
.I5(\dc_bias[0]_i_4__1_n_0 ),
.O(\dc_bias[1]_i_5__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT2 #(
.INIT(4'hE))
\dc_bias[1]_i_6__0
(.I0(\dc_bias_reg_n_0_[0] ),
.I1(\dc_bias[0]_i_2__1_n_0 ),
.O(\dc_bias[1]_i_6__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT2 #(
.INIT(4'h9))
\dc_bias[1]_i_7__1
(.I0(\dc_bias_reg_n_0_[1] ),
.I1(\dc_bias[3]_i_25__1_n_0 ),
.O(\dc_bias[1]_i_7__1_n_0 ));
LUT6 #(
.INIT(64'h14D782BE82BE14D7))
\dc_bias[1]_i_8
(.I0(rgb[0]),
.I1(\dc_bias_reg_n_0_[0] ),
.I2(\dc_bias[3]_i_31__0_n_0 ),
.I3(\dc_bias[0]_i_5__0_n_0 ),
.I4(rgb[3]),
.I5(rgb[1]),
.O(\dc_bias[1]_i_8_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT5 #(
.INIT(32'h6A56566A))
\dc_bias[1]_i_9__0
(.I0(\dc_bias_reg_n_0_[1] ),
.I1(rgb[0]),
.I2(\dc_bias_reg_n_0_[0] ),
.I3(\dc_bias[3]_i_3__1_n_0 ),
.I4(\encoded[7]_i_2__1_n_0 ),
.O(\dc_bias[1]_i_9__0_n_0 ));
LUT6 #(
.INIT(64'h9A5965A665A69A59))
\dc_bias[2]_i_10
(.I0(\dc_bias[2]_i_8__1_n_0 ),
.I1(\dc_bias[3]_i_3__1_n_0 ),
.I2(rgb[7]),
.I3(\encoded[6]_i_2__1_n_0 ),
.I4(\dc_bias_reg_n_0_[1] ),
.I5(\dc_bias[2]_i_14__0_n_0 ),
.O(\dc_bias[2]_i_10_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT5 #(
.INIT(32'h82EBEB82))
\dc_bias[2]_i_11__1
(.I0(rgb[7]),
.I1(\dc_bias_reg_n_0_[0] ),
.I2(rgb[0]),
.I3(rgb[5]),
.I4(\encoded[3]_i_2_n_0 ),
.O(\dc_bias[2]_i_11__1_n_0 ));
LUT5 #(
.INIT(32'h022BBFFF))
\dc_bias[2]_i_12__0
(.I0(\dc_bias[2]_i_15__0_n_0 ),
.I1(rgb[0]),
.I2(rgb[7]),
.I3(\dc_bias[3]_i_29__0_n_0 ),
.I4(\dc_bias[3]_i_12__1_n_0 ),
.O(\dc_bias[2]_i_12__0_n_0 ));
LUT6 #(
.INIT(64'h79E9EF7FFFFFFFFF))
\dc_bias[2]_i_13__0
(.I0(rgb[7]),
.I1(\dc_bias[3]_i_29__0_n_0 ),
.I2(\encoded[3]_i_2_n_0 ),
.I3(\dc_bias[2]_i_15__0_n_0 ),
.I4(\dc_bias[3]_i_12__1_n_0 ),
.I5(rgb[0]),
.O(\dc_bias[2]_i_13__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT2 #(
.INIT(4'h8))
\dc_bias[2]_i_14__0
(.I0(rgb[0]),
.I1(\dc_bias_reg_n_0_[0] ),
.O(\dc_bias[2]_i_14__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'h69))
\dc_bias[2]_i_15__0
(.I0(rgb[3]),
.I1(rgb[2]),
.I2(rgb[1]),
.O(\dc_bias[2]_i_15__0_n_0 ));
LUT6 #(
.INIT(64'hC5C0CFCACFCAC5C0))
\dc_bias[2]_i_1__1
(.I0(\dc_bias[2]_i_2__0_n_0 ),
.I1(\dc_bias[2]_i_3__1_n_0 ),
.I2(\dc_bias[3]_i_5_n_0 ),
.I3(\dc_bias[2]_i_4__1_n_0 ),
.I4(\dc_bias[2]_i_5__1_n_0 ),
.I5(\dc_bias[2]_i_6__1_n_0 ),
.O(\dc_bias[2]_i_1__1_n_0 ));
LUT6 #(
.INIT(64'h999999A999A9AAAA))
\dc_bias[2]_i_2__0
(.I0(p_1_in),
.I1(\dc_bias[3]_i_21_n_0 ),
.I2(\dc_bias[3]_i_20__0_n_0 ),
.I3(\dc_bias[3]_i_19__1_n_0 ),
.I4(\dc_bias[3]_i_18__0_n_0 ),
.I5(\dc_bias[3]_i_17__0_n_0 ),
.O(\dc_bias[2]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'h6699A5A566995A5A))
\dc_bias[2]_i_3__1
(.I0(\dc_bias_reg_n_0_[2] ),
.I1(\dc_bias[3]_i_14__0_n_0 ),
.I2(\dc_bias[3]_i_9__1_n_0 ),
.I3(\dc_bias[3]_i_15__1_n_0 ),
.I4(\dc_bias[3]_i_3__1_n_0 ),
.I5(\dc_bias[3]_i_8__1_n_0 ),
.O(\dc_bias[2]_i_3__1_n_0 ));
LUT5 #(
.INIT(32'h4BB4B44B))
\dc_bias[2]_i_4__1
(.I0(\dc_bias[3]_i_25__1_n_0 ),
.I1(\dc_bias_reg_n_0_[1] ),
.I2(\dc_bias_reg_n_0_[2] ),
.I3(\dc_bias[3]_i_14__0_n_0 ),
.I4(\dc_bias[3]_i_26__1_n_0 ),
.O(\dc_bias[2]_i_4__1_n_0 ));
LUT6 #(
.INIT(64'h75F710518A08EFAE))
\dc_bias[2]_i_5__1
(.I0(\dc_bias[2]_i_7__0_n_0 ),
.I1(\dc_bias[3]_i_3__1_n_0 ),
.I2(rgb[7]),
.I3(\encoded[6]_i_2__1_n_0 ),
.I4(\dc_bias[2]_i_8__1_n_0 ),
.I5(\dc_bias[2]_i_9__0_n_0 ),
.O(\dc_bias[2]_i_5__1_n_0 ));
LUT6 #(
.INIT(64'h177E777777777E17))
\dc_bias[2]_i_6__1
(.I0(\dc_bias[2]_i_10_n_0 ),
.I1(\dc_bias[2]_i_11__1_n_0 ),
.I2(\dc_bias[0]_i_3__1_n_0 ),
.I3(\encoded[1]_i_2_n_0 ),
.I4(\dc_bias[3]_i_3__1_n_0 ),
.I5(rgb[2]),
.O(\dc_bias[2]_i_6__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT3 #(
.INIT(8'h6A))
\dc_bias[2]_i_7__0
(.I0(\dc_bias_reg_n_0_[1] ),
.I1(\dc_bias_reg_n_0_[0] ),
.I2(rgb[0]),
.O(\dc_bias[2]_i_7__0_n_0 ));
LUT6 #(
.INIT(64'h2DB4B4B42D2D2DB4))
\dc_bias[2]_i_8__1
(.I0(rgb[4]),
.I1(rgb[5]),
.I2(\encoded[3]_i_2_n_0 ),
.I3(\dc_bias[2]_i_12__0_n_0 ),
.I4(\dc_bias[3]_i_13__0_n_0 ),
.I5(\dc_bias[2]_i_13__0_n_0 ),
.O(\dc_bias[2]_i_8__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT4 #(
.INIT(16'hAA95))
\dc_bias[2]_i_9__0
(.I0(\dc_bias_reg_n_0_[2] ),
.I1(rgb[0]),
.I2(\dc_bias_reg_n_0_[0] ),
.I3(\dc_bias_reg_n_0_[1] ),
.O(\dc_bias[2]_i_9__0_n_0 ));
LUT1 #(
.INIT(2'h1))
\dc_bias[3]_i_1
(.I0(active),
.O(SR));
LUT6 #(
.INIT(64'h69FFFF69FF6969FF))
\dc_bias[3]_i_10__1
(.I0(rgb[1]),
.I1(rgb[2]),
.I2(rgb[3]),
.I3(rgb[0]),
.I4(rgb[7]),
.I5(\dc_bias[3]_i_29__0_n_0 ),
.O(\dc_bias[3]_i_10__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT5 #(
.INIT(32'h17717117))
\dc_bias[3]_i_11__1
(.I0(rgb[0]),
.I1(rgb[7]),
.I2(rgb[6]),
.I3(rgb[5]),
.I4(rgb[4]),
.O(\dc_bias[3]_i_11__1_n_0 ));
LUT6 #(
.INIT(64'h171717E817E8E8E8))
\dc_bias[3]_i_12__1
(.I0(rgb[3]),
.I1(rgb[2]),
.I2(rgb[1]),
.I3(rgb[5]),
.I4(rgb[4]),
.I5(rgb[6]),
.O(\dc_bias[3]_i_12__1_n_0 ));
LUT6 #(
.INIT(64'h171717FF17FFFFFF))
\dc_bias[3]_i_13__0
(.I0(rgb[3]),
.I1(rgb[2]),
.I2(rgb[1]),
.I3(rgb[5]),
.I4(rgb[4]),
.I5(rgb[6]),
.O(\dc_bias[3]_i_13__0_n_0 ));
LUT6 #(
.INIT(64'h4DDD444D444D2444))
\dc_bias[3]_i_14__0
(.I0(\dc_bias[3]_i_28__0_n_0 ),
.I1(\dc_bias[3]_i_30__0_n_0 ),
.I2(\dc_bias[0]_i_5__0_n_0 ),
.I3(rgb[0]),
.I4(\dc_bias[3]_i_31__0_n_0 ),
.I5(\dc_bias[3]_i_19__1_n_0 ),
.O(\dc_bias[3]_i_14__0_n_0 ));
LUT6 #(
.INIT(64'hECFE8FC88FC8ECFE))
\dc_bias[3]_i_15__1
(.I0(\dc_bias_reg_n_0_[0] ),
.I1(\dc_bias_reg_n_0_[1] ),
.I2(\dc_bias[3]_i_19__1_n_0 ),
.I3(\dc_bias[3]_i_20__0_n_0 ),
.I4(\dc_bias[3]_i_18__0_n_0 ),
.I5(\dc_bias[3]_i_17__0_n_0 ),
.O(\dc_bias[3]_i_15__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT4 #(
.INIT(16'h0001))
\dc_bias[3]_i_16__0
(.I0(\dc_bias_reg_n_0_[1] ),
.I1(\dc_bias_reg_n_0_[2] ),
.I2(\dc_bias_reg_n_0_[0] ),
.I3(p_1_in),
.O(\dc_bias[3]_i_16__0_n_0 ));
LUT6 #(
.INIT(64'hD22D4BB42DD2B44B))
\dc_bias[3]_i_17__0
(.I0(rgb[3]),
.I1(rgb[2]),
.I2(rgb[1]),
.I3(rgb[0]),
.I4(\dc_bias[3]_i_3__1_n_0 ),
.I5(\dc_bias[3]_i_28__0_n_0 ),
.O(\dc_bias[3]_i_17__0_n_0 ));
LUT6 #(
.INIT(64'h1D8B8B1D8B1D1D8B))
\dc_bias[3]_i_18__0
(.I0(\dc_bias[3]_i_3__1_n_0 ),
.I1(\encoded[7]_i_2__1_n_0 ),
.I2(rgb[0]),
.I3(rgb[6]),
.I4(rgb[4]),
.I5(\encoded[3]_i_2_n_0 ),
.O(\dc_bias[3]_i_18__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'h69))
\dc_bias[3]_i_19__1
(.I0(rgb[3]),
.I1(rgb[1]),
.I2(rgb[0]),
.O(\dc_bias[3]_i_19__1_n_0 ));
LUT6 #(
.INIT(64'h1DFF1D001DFF1DFF))
\dc_bias[3]_i_1__1
(.I0(\dc_bias[3]_i_2__1_n_0 ),
.I1(\dc_bias[3]_i_3__1_n_0 ),
.I2(\dc_bias[3]_i_4__1_n_0 ),
.I3(\dc_bias[3]_i_5_n_0 ),
.I4(\dc_bias[3]_i_6__1_n_0 ),
.I5(\dc_bias[3]_i_7__1_n_0 ),
.O(\dc_bias[3]_i_1__1_n_0 ));
LUT5 #(
.INIT(32'h69969669))
\dc_bias[3]_i_20__0
(.I0(\encoded[3]_i_2_n_0 ),
.I1(rgb[4]),
.I2(rgb[6]),
.I3(\encoded[7]_i_2__1_n_0 ),
.I4(rgb[0]),
.O(\dc_bias[3]_i_20__0_n_0 ));
LUT6 #(
.INIT(64'hA20808A2208A8A20))
\dc_bias[3]_i_21
(.I0(\dc_bias[3]_i_28__0_n_0 ),
.I1(rgb[3]),
.I2(rgb[2]),
.I3(rgb[1]),
.I4(rgb[0]),
.I5(\dc_bias[3]_i_3__1_n_0 ),
.O(\dc_bias[3]_i_21_n_0 ));
LUT6 #(
.INIT(64'hBBBABA22BA22BA22))
\dc_bias[3]_i_22__1
(.I0(\dc_bias_reg_n_0_[2] ),
.I1(\dc_bias[3]_i_32__0_n_0 ),
.I2(\dc_bias[3]_i_33__0_n_0 ),
.I3(\dc_bias_reg_n_0_[1] ),
.I4(\dc_bias_reg_n_0_[0] ),
.I5(rgb[0]),
.O(\dc_bias[3]_i_22__1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFEFFFFEF))
\dc_bias[3]_i_23__0
(.I0(\dc_bias[2]_i_10_n_0 ),
.I1(\dc_bias[0]_i_3__1_n_0 ),
.I2(\encoded[1]_i_2_n_0 ),
.I3(\dc_bias[3]_i_3__1_n_0 ),
.I4(rgb[2]),
.I5(\dc_bias[2]_i_11__1_n_0 ),
.O(\dc_bias[3]_i_23__0_n_0 ));
LUT6 #(
.INIT(64'hFFE7810081000000))
\dc_bias[3]_i_24__1
(.I0(rgb[2]),
.I1(\dc_bias[3]_i_3__1_n_0 ),
.I2(\encoded[1]_i_2_n_0 ),
.I3(\dc_bias[0]_i_3__1_n_0 ),
.I4(\dc_bias[2]_i_11__1_n_0 ),
.I5(\dc_bias[2]_i_10_n_0 ),
.O(\dc_bias[3]_i_24__1_n_0 ));
LUT6 #(
.INIT(64'h188EE771E771188E))
\dc_bias[3]_i_25__1
(.I0(\dc_bias[3]_i_19__1_n_0 ),
.I1(\dc_bias[3]_i_31__0_n_0 ),
.I2(rgb[0]),
.I3(\dc_bias[0]_i_5__0_n_0 ),
.I4(\dc_bias[3]_i_30__0_n_0 ),
.I5(\dc_bias[3]_i_28__0_n_0 ),
.O(\dc_bias[3]_i_25__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT5 #(
.INIT(32'h9990F999))
\dc_bias[3]_i_26__1
(.I0(\dc_bias_reg_n_0_[1] ),
.I1(\dc_bias[3]_i_25__1_n_0 ),
.I2(\dc_bias_reg_n_0_[0] ),
.I3(\dc_bias[0]_i_2__1_n_0 ),
.I4(\dc_bias[3]_i_3__1_n_0 ),
.O(\dc_bias[3]_i_26__1_n_0 ));
LUT6 #(
.INIT(64'hAA696955559696AA))
\dc_bias[3]_i_27__1
(.I0(\dc_bias[3]_i_28__0_n_0 ),
.I1(\encoded[7]_i_2__1_n_0 ),
.I2(\dc_bias[3]_i_3__1_n_0 ),
.I3(\dc_bias_reg_n_0_[0] ),
.I4(rgb[0]),
.I5(\dc_bias_reg_n_0_[1] ),
.O(\dc_bias[3]_i_27__1_n_0 ));
LUT6 #(
.INIT(64'h28882228BEEEBBBE))
\dc_bias[3]_i_28__0
(.I0(\encoded[4]_i_2_n_0 ),
.I1(\encoded[5]_i_2_n_0 ),
.I2(\dc_bias[2]_i_12__0_n_0 ),
.I3(\dc_bias[3]_i_13__0_n_0 ),
.I4(\dc_bias[2]_i_13__0_n_0 ),
.I5(\encoded[6]_i_2__1_n_0 ),
.O(\dc_bias[3]_i_28__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'h96))
\dc_bias[3]_i_29__0
(.I0(rgb[6]),
.I1(rgb[5]),
.I2(rgb[4]),
.O(\dc_bias[3]_i_29__0_n_0 ));
LUT4 #(
.INIT(16'h24DB))
\dc_bias[3]_i_2__1
(.I0(\dc_bias[3]_i_8__1_n_0 ),
.I1(\dc_bias[3]_i_9__1_n_0 ),
.I2(\dc_bias_reg_n_0_[2] ),
.I3(p_1_in),
.O(\dc_bias[3]_i_2__1_n_0 ));
LUT6 #(
.INIT(64'h2BD400FFFF002BD4))
\dc_bias[3]_i_30__0
(.I0(\dc_bias[2]_i_13__0_n_0 ),
.I1(\dc_bias[3]_i_13__0_n_0 ),
.I2(\dc_bias[2]_i_12__0_n_0 ),
.I3(\encoded[1]_i_2_n_0 ),
.I4(rgb[2]),
.I5(rgb[3]),
.O(\dc_bias[3]_i_30__0_n_0 ));
LUT6 #(
.INIT(64'h55F5F5FFAE8A8A08))
\dc_bias[3]_i_31__0
(.I0(\dc_bias[3]_i_13__0_n_0 ),
.I1(rgb[0]),
.I2(\dc_bias[3]_i_12__1_n_0 ),
.I3(\dc_bias[3]_i_11__1_n_0 ),
.I4(\dc_bias[3]_i_10__1_n_0 ),
.I5(\encoded[7]_i_2__1_n_0 ),
.O(\dc_bias[3]_i_31__0_n_0 ));
LUT6 #(
.INIT(64'h01B00071B20001B0))
\dc_bias[3]_i_32__0
(.I0(rgb[6]),
.I1(rgb[7]),
.I2(\dc_bias[3]_i_3__1_n_0 ),
.I3(\encoded[3]_i_2_n_0 ),
.I4(rgb[5]),
.I5(rgb[4]),
.O(\dc_bias[3]_i_32__0_n_0 ));
LUT6 #(
.INIT(64'h9208000059591049))
\dc_bias[3]_i_33__0
(.I0(\encoded[3]_i_2_n_0 ),
.I1(rgb[4]),
.I2(rgb[5]),
.I3(rgb[6]),
.I4(rgb[7]),
.I5(\dc_bias[3]_i_3__1_n_0 ),
.O(\dc_bias[3]_i_33__0_n_0 ));
LUT6 #(
.INIT(64'h2B023F03FFBFFFFF))
\dc_bias[3]_i_3__1
(.I0(\encoded[7]_i_2__1_n_0 ),
.I1(\dc_bias[3]_i_10__1_n_0 ),
.I2(\dc_bias[3]_i_11__1_n_0 ),
.I3(\dc_bias[3]_i_12__1_n_0 ),
.I4(rgb[0]),
.I5(\dc_bias[3]_i_13__0_n_0 ),
.O(\dc_bias[3]_i_3__1_n_0 ));
LUT4 #(
.INIT(16'h65A6))
\dc_bias[3]_i_4__1
(.I0(\dc_bias[2]_i_2__0_n_0 ),
.I1(\dc_bias_reg_n_0_[2] ),
.I2(\dc_bias[3]_i_14__0_n_0 ),
.I3(\dc_bias[3]_i_15__1_n_0 ),
.O(\dc_bias[3]_i_4__1_n_0 ));
LUT6 #(
.INIT(64'hAAAAEAAAAABEABAA))
\dc_bias[3]_i_5
(.I0(\dc_bias[3]_i_16__0_n_0 ),
.I1(\dc_bias[3]_i_17__0_n_0 ),
.I2(\dc_bias[3]_i_18__0_n_0 ),
.I3(\dc_bias[3]_i_19__1_n_0 ),
.I4(\dc_bias[3]_i_20__0_n_0 ),
.I5(\dc_bias[3]_i_21_n_0 ),
.O(\dc_bias[3]_i_5_n_0 ));
LUT6 #(
.INIT(64'h8228822828288228))
\dc_bias[3]_i_6__1
(.I0(\dc_bias[2]_i_2__0_n_0 ),
.I1(p_1_in),
.I2(\dc_bias[3]_i_22__1_n_0 ),
.I3(\dc_bias[3]_i_23__0_n_0 ),
.I4(\dc_bias[2]_i_5__1_n_0 ),
.I5(\dc_bias[3]_i_24__1_n_0 ),
.O(\dc_bias[3]_i_6__1_n_0 ));
LUT6 #(
.INIT(64'hFFF4F4F0FBFFFFF4))
\dc_bias[3]_i_7__1
(.I0(\dc_bias[3]_i_25__1_n_0 ),
.I1(\dc_bias_reg_n_0_[1] ),
.I2(\dc_bias[2]_i_2__0_n_0 ),
.I3(\dc_bias[3]_i_26__1_n_0 ),
.I4(\dc_bias_reg_n_0_[2] ),
.I5(\dc_bias[3]_i_14__0_n_0 ),
.O(\dc_bias[3]_i_7__1_n_0 ));
LUT6 #(
.INIT(64'h08A28A20AEFBEFBA))
\dc_bias[3]_i_8__1
(.I0(\dc_bias[3]_i_27__1_n_0 ),
.I1(rgb[3]),
.I2(rgb[2]),
.I3(\encoded[1]_i_2_n_0 ),
.I4(\dc_bias[3]_i_3__1_n_0 ),
.I5(\dc_bias[1]_i_8_n_0 ),
.O(\dc_bias[3]_i_8__1_n_0 ));
LUT6 #(
.INIT(64'h0000099F099FFFFF))
\dc_bias[3]_i_9__1
(.I0(\encoded[7]_i_2__1_n_0 ),
.I1(\dc_bias[3]_i_3__1_n_0 ),
.I2(rgb[0]),
.I3(\dc_bias_reg_n_0_[0] ),
.I4(\dc_bias_reg_n_0_[1] ),
.I5(\dc_bias[3]_i_28__0_n_0 ),
.O(\dc_bias[3]_i_9__1_n_0 ));
FDRE #(
.INIT(1'b0))
\dc_bias_reg[0]
(.C(clk_25),
.CE(1'b1),
.D(\dc_bias[0]_i_1__1_n_0 ),
.Q(\dc_bias_reg_n_0_[0] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\dc_bias_reg[1]
(.C(clk_25),
.CE(1'b1),
.D(\dc_bias[1]_i_1__0_n_0 ),
.Q(\dc_bias_reg_n_0_[1] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\dc_bias_reg[2]
(.C(clk_25),
.CE(1'b1),
.D(\dc_bias[2]_i_1__1_n_0 ),
.Q(\dc_bias_reg_n_0_[2] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\dc_bias_reg[3]
(.C(clk_25),
.CE(1'b1),
.D(\dc_bias[3]_i_1__1_n_0 ),
.Q(p_1_in),
.R(SR));
LUT6 #(
.INIT(64'h6F6FAF5F6060A050))
\encoded[0]_i_1__1
(.I0(rgb[0]),
.I1(\dc_bias[3]_i_3__1_n_0 ),
.I2(active),
.I3(\dc_bias[2]_i_2__0_n_0 ),
.I4(\dc_bias[3]_i_5_n_0 ),
.I5(hsync),
.O(\encoded[0]_i_1__1_n_0 ));
LUT6 #(
.INIT(64'hFF7B33B7CC480084))
\encoded[1]_i_1__1
(.I0(\dc_bias[3]_i_3__1_n_0 ),
.I1(active),
.I2(\dc_bias[2]_i_2__0_n_0 ),
.I3(\dc_bias[3]_i_5_n_0 ),
.I4(\encoded[1]_i_2_n_0 ),
.I5(hsync),
.O(\encoded[1]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT2 #(
.INIT(4'h6))
\encoded[1]_i_2
(.I0(rgb[0]),
.I1(rgb[1]),
.O(\encoded[1]_i_2_n_0 ));
LUT6 #(
.INIT(64'h880C44C0BB3F77F3))
\encoded[2]_i_1__1
(.I0(\dc_bias[3]_i_3__1_n_0 ),
.I1(active),
.I2(\dc_bias[2]_i_2__0_n_0 ),
.I3(\dc_bias[3]_i_5_n_0 ),
.I4(\encoded[2]_i_2_n_0 ),
.I5(hsync),
.O(\encoded[2]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'h69))
\encoded[2]_i_2
(.I0(rgb[2]),
.I1(rgb[1]),
.I2(rgb[0]),
.O(\encoded[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'h33B7FF7B0084CC48))
\encoded[3]_i_1__1
(.I0(\dc_bias[3]_i_3__1_n_0 ),
.I1(active),
.I2(\dc_bias[2]_i_2__0_n_0 ),
.I3(\dc_bias[3]_i_5_n_0 ),
.I4(\encoded[3]_i_2_n_0 ),
.I5(hsync),
.O(\encoded[3]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'h9669))
\encoded[3]_i_2
(.I0(rgb[3]),
.I1(rgb[0]),
.I2(rgb[1]),
.I3(rgb[2]),
.O(\encoded[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'h44C0880C77F3BB3F))
\encoded[4]_i_1__1
(.I0(\dc_bias[3]_i_3__1_n_0 ),
.I1(active),
.I2(\dc_bias[2]_i_2__0_n_0 ),
.I3(\dc_bias[3]_i_5_n_0 ),
.I4(\encoded[4]_i_2_n_0 ),
.I5(hsync),
.O(\encoded[4]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT5 #(
.INIT(32'h96696996))
\encoded[4]_i_2
(.I0(rgb[4]),
.I1(rgb[2]),
.I2(rgb[1]),
.I3(rgb[0]),
.I4(rgb[3]),
.O(\encoded[4]_i_2_n_0 ));
LUT6 #(
.INIT(64'h33B7FF7B0084CC48))
\encoded[5]_i_1__1
(.I0(\dc_bias[3]_i_3__1_n_0 ),
.I1(active),
.I2(\dc_bias[2]_i_2__0_n_0 ),
.I3(\dc_bias[3]_i_5_n_0 ),
.I4(\encoded[5]_i_2_n_0 ),
.I5(hsync),
.O(\encoded[5]_i_1__1_n_0 ));
LUT6 #(
.INIT(64'h9669699669969669))
\encoded[5]_i_2
(.I0(rgb[2]),
.I1(rgb[1]),
.I2(rgb[0]),
.I3(rgb[3]),
.I4(rgb[5]),
.I5(rgb[4]),
.O(\encoded[5]_i_2_n_0 ));
LUT6 #(
.INIT(64'h880C44C0BB3F77F3))
\encoded[6]_i_1__1
(.I0(\dc_bias[3]_i_3__1_n_0 ),
.I1(active),
.I2(\dc_bias[2]_i_2__0_n_0 ),
.I3(\dc_bias[3]_i_5_n_0 ),
.I4(\encoded[6]_i_2__1_n_0 ),
.I5(hsync),
.O(\encoded[6]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'h6996))
\encoded[6]_i_2__1
(.I0(\encoded[3]_i_2_n_0 ),
.I1(rgb[4]),
.I2(rgb[5]),
.I3(rgb[6]),
.O(\encoded[6]_i_2__1_n_0 ));
LUT6 #(
.INIT(64'hFF337BB7CC004884))
\encoded[7]_i_1__1
(.I0(\dc_bias[3]_i_3__1_n_0 ),
.I1(active),
.I2(\dc_bias[2]_i_2__0_n_0 ),
.I3(\encoded[7]_i_2__1_n_0 ),
.I4(\dc_bias[3]_i_5_n_0 ),
.I5(hsync),
.O(\encoded[7]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h69969669))
\encoded[7]_i_2__1
(.I0(rgb[7]),
.I1(rgb[6]),
.I2(rgb[5]),
.I3(rgb[4]),
.I4(\encoded[3]_i_2_n_0 ),
.O(\encoded[7]_i_2__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'h47))
\encoded[8]_i_1__1
(.I0(\dc_bias[3]_i_3__1_n_0 ),
.I1(active),
.I2(hsync),
.O(\encoded[8]_i_1__1_n_0 ));
LUT6 #(
.INIT(64'hC5FFC500C500C5FF))
\encoded[9]_i_1__1
(.I0(\dc_bias[2]_i_2__0_n_0 ),
.I1(\dc_bias[3]_i_3__1_n_0 ),
.I2(\dc_bias[3]_i_5_n_0 ),
.I3(active),
.I4(hsync),
.I5(vsync),
.O(\encoded[9]_i_1__1_n_0 ));
FDRE \encoded_reg[0]
(.C(clk_25),
.CE(1'b1),
.D(\encoded[0]_i_1__1_n_0 ),
.Q(\encoded_reg_n_0_[0] ),
.R(1'b0));
FDRE \encoded_reg[1]
(.C(clk_25),
.CE(1'b1),
.D(\encoded[1]_i_1__1_n_0 ),
.Q(\encoded_reg_n_0_[1] ),
.R(1'b0));
FDRE \encoded_reg[2]
(.C(clk_25),
.CE(1'b1),
.D(\encoded[2]_i_1__1_n_0 ),
.Q(\encoded_reg_n_0_[2] ),
.R(1'b0));
FDRE \encoded_reg[3]
(.C(clk_25),
.CE(1'b1),
.D(\encoded[3]_i_1__1_n_0 ),
.Q(\encoded_reg_n_0_[3] ),
.R(1'b0));
FDRE \encoded_reg[4]
(.C(clk_25),
.CE(1'b1),
.D(\encoded[4]_i_1__1_n_0 ),
.Q(\encoded_reg_n_0_[4] ),
.R(1'b0));
FDRE \encoded_reg[5]
(.C(clk_25),
.CE(1'b1),
.D(\encoded[5]_i_1__1_n_0 ),
.Q(\encoded_reg_n_0_[5] ),
.R(1'b0));
FDRE \encoded_reg[6]
(.C(clk_25),
.CE(1'b1),
.D(\encoded[6]_i_1__1_n_0 ),
.Q(\encoded_reg_n_0_[6] ),
.R(1'b0));
FDRE \encoded_reg[7]
(.C(clk_25),
.CE(1'b1),
.D(\encoded[7]_i_1__1_n_0 ),
.Q(\encoded_reg_n_0_[7] ),
.R(1'b0));
FDRE \encoded_reg[8]
(.C(clk_25),
.CE(1'b1),
.D(\encoded[8]_i_1__1_n_0 ),
.Q(Q[0]),
.R(1'b0));
FDRE \encoded_reg[9]
(.C(clk_25),
.CE(1'b1),
.D(\encoded[9]_i_1__1_n_0 ),
.Q(Q[1]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'hB8))
\shift_blue[0]_i_1
(.I0(shift_blue[0]),
.I1(\shift_clock_reg[5] ),
.I2(\encoded_reg_n_0_[0] ),
.O(D[0]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'hB8))
\shift_blue[1]_i_1
(.I0(shift_blue[1]),
.I1(\shift_clock_reg[5] ),
.I2(\encoded_reg_n_0_[1] ),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'hB8))
\shift_blue[2]_i_1
(.I0(shift_blue[2]),
.I1(\shift_clock_reg[5] ),
.I2(\encoded_reg_n_0_[2] ),
.O(D[2]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'hB8))
\shift_blue[3]_i_1
(.I0(shift_blue[3]),
.I1(\shift_clock_reg[5] ),
.I2(\encoded_reg_n_0_[3] ),
.O(D[3]));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'hB8))
\shift_blue[4]_i_1
(.I0(shift_blue[4]),
.I1(\shift_clock_reg[5] ),
.I2(\encoded_reg_n_0_[4] ),
.O(D[4]));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'hB8))
\shift_blue[5]_i_1
(.I0(shift_blue[5]),
.I1(\shift_clock_reg[5] ),
.I2(\encoded_reg_n_0_[5] ),
.O(D[5]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'hB8))
\shift_blue[6]_i_1
(.I0(shift_blue[6]),
.I1(\shift_clock_reg[5] ),
.I2(\encoded_reg_n_0_[6] ),
.O(D[6]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'hB8))
\shift_blue[7]_i_1
(.I0(shift_blue[7]),
.I1(\shift_clock_reg[5] ),
.I2(\encoded_reg_n_0_[7] ),
.O(D[7]));
endmodule
(* ORIG_REF_NAME = "TMDS_encoder" *)
module system_zybo_hdmi_0_0_TMDS_encoder_0
(D,
Q,
rgb,
active,
shift_green,
\shift_clock_reg[5] ,
SR,
clk_25);
output [7:0]D;
output [1:0]Q;
input [7:0]rgb;
input active;
input [7:0]shift_green;
input \shift_clock_reg[5] ;
input [0:0]SR;
input clk_25;
wire [7:0]D;
wire [1:0]Q;
wire [0:0]SR;
wire active;
wire clk_25;
wire \dc_bias[0]_i_1__0_n_0 ;
wire \dc_bias[0]_i_2__0_n_0 ;
wire \dc_bias[0]_i_3__0_n_0 ;
wire \dc_bias[0]_i_4__0_n_0 ;
wire \dc_bias[0]_i_5__1_n_0 ;
wire \dc_bias[0]_i_6_n_0 ;
wire \dc_bias[0]_i_7_n_0 ;
wire \dc_bias[1]_i_1_n_0 ;
wire \dc_bias[1]_i_2__0_n_0 ;
wire \dc_bias[1]_i_3__0_n_0 ;
wire \dc_bias[1]_i_4__0_n_0 ;
wire \dc_bias[1]_i_5_n_0 ;
wire \dc_bias[1]_i_6__1_n_0 ;
wire \dc_bias[1]_i_7__0_n_0 ;
wire \dc_bias[1]_i_8__0_n_0 ;
wire \dc_bias[1]_i_9_n_0 ;
wire \dc_bias[2]_i_10__1_n_0 ;
wire \dc_bias[2]_i_11__0_n_0 ;
wire \dc_bias[2]_i_1__0_n_0 ;
wire \dc_bias[2]_i_2__1_n_0 ;
wire \dc_bias[2]_i_3__0_n_0 ;
wire \dc_bias[2]_i_4_n_0 ;
wire \dc_bias[2]_i_5__0_n_0 ;
wire \dc_bias[2]_i_6__0_n_0 ;
wire \dc_bias[2]_i_7_n_0 ;
wire \dc_bias[2]_i_8__0_n_0 ;
wire \dc_bias[2]_i_9_n_0 ;
wire \dc_bias[3]_i_10__0_n_0 ;
wire \dc_bias[3]_i_11__0_n_0 ;
wire \dc_bias[3]_i_12__0_n_0 ;
wire \dc_bias[3]_i_13__1_n_0 ;
wire \dc_bias[3]_i_14__1_n_0 ;
wire \dc_bias[3]_i_15__0_n_0 ;
wire \dc_bias[3]_i_16_n_0 ;
wire \dc_bias[3]_i_17_n_0 ;
wire \dc_bias[3]_i_18__1_n_0 ;
wire \dc_bias[3]_i_19__0_n_0 ;
wire \dc_bias[3]_i_1__0_n_0 ;
wire \dc_bias[3]_i_20_n_0 ;
wire \dc_bias[3]_i_21__1_n_0 ;
wire \dc_bias[3]_i_22__0_n_0 ;
wire \dc_bias[3]_i_23__1_n_0 ;
wire \dc_bias[3]_i_24__0_n_0 ;
wire \dc_bias[3]_i_25__0_n_0 ;
wire \dc_bias[3]_i_26__0_n_0 ;
wire \dc_bias[3]_i_27__0_n_0 ;
wire \dc_bias[3]_i_28_n_0 ;
wire \dc_bias[3]_i_29_n_0 ;
wire \dc_bias[3]_i_2__0_n_0 ;
wire \dc_bias[3]_i_30_n_0 ;
wire \dc_bias[3]_i_31_n_0 ;
wire \dc_bias[3]_i_32_n_0 ;
wire \dc_bias[3]_i_33_n_0 ;
wire \dc_bias[3]_i_34_n_0 ;
wire \dc_bias[3]_i_3__0_n_0 ;
wire \dc_bias[3]_i_4__0_n_0 ;
wire \dc_bias[3]_i_5__1_n_0 ;
wire \dc_bias[3]_i_6__0_n_0 ;
wire \dc_bias[3]_i_7__0_n_0 ;
wire \dc_bias[3]_i_8__0_n_0 ;
wire \dc_bias[3]_i_9__0_n_0 ;
wire \dc_bias_reg_n_0_[0] ;
wire \dc_bias_reg_n_0_[1] ;
wire \dc_bias_reg_n_0_[2] ;
wire \encoded[0]_i_1__0_n_0 ;
wire \encoded[1]_i_1__0_n_0 ;
wire \encoded[2]_i_1__0_n_0 ;
wire \encoded[3]_i_1__0_n_0 ;
wire \encoded[4]_i_1__0_n_0 ;
wire \encoded[5]_i_1__0_n_0 ;
wire \encoded[6]_i_1__0_n_0 ;
wire \encoded[6]_i_2__0_n_0 ;
wire \encoded[7]_i_1__0_n_0 ;
wire \encoded[7]_i_2_n_0 ;
wire \encoded[7]_i_3__0_n_0 ;
wire \encoded[8]_i_1__0_n_0 ;
wire \encoded[8]_i_2_n_0 ;
wire \encoded[8]_i_3_n_0 ;
wire \encoded[8]_i_4_n_0 ;
wire \encoded[8]_i_5_n_0 ;
wire \encoded[8]_i_6_n_0 ;
wire \encoded[8]_i_7_n_0 ;
wire \encoded[9]_i_1_n_0 ;
wire \encoded[9]_i_2__0_n_0 ;
wire \encoded_reg_n_0_[0] ;
wire \encoded_reg_n_0_[1] ;
wire \encoded_reg_n_0_[2] ;
wire \encoded_reg_n_0_[3] ;
wire \encoded_reg_n_0_[4] ;
wire \encoded_reg_n_0_[5] ;
wire \encoded_reg_n_0_[6] ;
wire \encoded_reg_n_0_[7] ;
wire p_1_in;
wire [7:0]rgb;
wire \shift_clock_reg[5] ;
wire [7:0]shift_green;
LUT6 #(
.INIT(64'h6F60606F606F6F60))
\dc_bias[0]_i_1__0
(.I0(\dc_bias_reg_n_0_[0] ),
.I1(\dc_bias[0]_i_2__0_n_0 ),
.I2(\dc_bias[3]_i_2__0_n_0 ),
.I3(\dc_bias[3]_i_5__1_n_0 ),
.I4(\dc_bias[0]_i_3__0_n_0 ),
.I5(\dc_bias[0]_i_4__0_n_0 ),
.O(\dc_bias[0]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT5 #(
.INIT(32'h69969669))
\dc_bias[0]_i_2__0
(.I0(\dc_bias[0]_i_5__1_n_0 ),
.I1(rgb[0]),
.I2(\dc_bias[0]_i_6_n_0 ),
.I3(\dc_bias[0]_i_7_n_0 ),
.I4(rgb[6]),
.O(\dc_bias[0]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT5 #(
.INIT(32'h69969669))
\dc_bias[0]_i_3__0
(.I0(\encoded[6]_i_2__0_n_0 ),
.I1(rgb[5]),
.I2(rgb[0]),
.I3(\dc_bias_reg_n_0_[0] ),
.I4(rgb[7]),
.O(\dc_bias[0]_i_3__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT2 #(
.INIT(4'h9))
\dc_bias[0]_i_4__0
(.I0(rgb[2]),
.I1(\encoded[8]_i_2_n_0 ),
.O(\dc_bias[0]_i_4__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'h69))
\dc_bias[0]_i_5__1
(.I0(rgb[3]),
.I1(rgb[1]),
.I2(rgb[0]),
.O(\dc_bias[0]_i_5__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT5 #(
.INIT(32'h69969669))
\dc_bias[0]_i_6
(.I0(rgb[7]),
.I1(\encoded[6]_i_2__0_n_0 ),
.I2(rgb[6]),
.I3(rgb[5]),
.I4(rgb[4]),
.O(\dc_bias[0]_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT5 #(
.INIT(32'h96696996))
\dc_bias[0]_i_7
(.I0(rgb[4]),
.I1(rgb[2]),
.I2(rgb[1]),
.I3(rgb[0]),
.I4(rgb[3]),
.O(\dc_bias[0]_i_7_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\dc_bias[1]_i_1
(.I0(\dc_bias[1]_i_2__0_n_0 ),
.I1(\dc_bias[3]_i_2__0_n_0 ),
.I2(\dc_bias[1]_i_3__0_n_0 ),
.I3(\dc_bias[3]_i_5__1_n_0 ),
.I4(\dc_bias[1]_i_4__0_n_0 ),
.O(\dc_bias[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'h960096FF96FF9600))
\dc_bias[1]_i_2__0
(.I0(\dc_bias[1]_i_5_n_0 ),
.I1(\dc_bias[1]_i_6__1_n_0 ),
.I2(\dc_bias[1]_i_7__0_n_0 ),
.I3(\encoded[8]_i_2_n_0 ),
.I4(\dc_bias[1]_i_8__0_n_0 ),
.I5(\dc_bias[2]_i_10__1_n_0 ),
.O(\dc_bias[1]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT4 #(
.INIT(16'h5965))
\dc_bias[1]_i_3__0
(.I0(\dc_bias[2]_i_10__1_n_0 ),
.I1(\encoded[8]_i_2_n_0 ),
.I2(\dc_bias[0]_i_2__0_n_0 ),
.I3(\dc_bias_reg_n_0_[0] ),
.O(\dc_bias[1]_i_3__0_n_0 ));
LUT6 #(
.INIT(64'h56955965A96AA69A))
\dc_bias[1]_i_4__0
(.I0(\dc_bias[3]_i_11__0_n_0 ),
.I1(\dc_bias[0]_i_3__0_n_0 ),
.I2(rgb[2]),
.I3(\encoded[8]_i_2_n_0 ),
.I4(\dc_bias[2]_i_11__0_n_0 ),
.I5(\dc_bias[3]_i_12__0_n_0 ),
.O(\dc_bias[1]_i_4__0_n_0 ));
LUT6 #(
.INIT(64'h066090096FF6F99F))
\dc_bias[1]_i_5
(.I0(rgb[6]),
.I1(\dc_bias[0]_i_7_n_0 ),
.I2(\dc_bias[1]_i_9_n_0 ),
.I3(\dc_bias[0]_i_6_n_0 ),
.I4(\encoded[8]_i_2_n_0 ),
.I5(\dc_bias[0]_i_5__1_n_0 ),
.O(\dc_bias[1]_i_5_n_0 ));
LUT6 #(
.INIT(64'h556969AAAA969655))
\dc_bias[1]_i_6__1
(.I0(\dc_bias[3]_i_27__0_n_0 ),
.I1(\dc_bias[0]_i_6_n_0 ),
.I2(\encoded[8]_i_2_n_0 ),
.I3(\dc_bias_reg_n_0_[0] ),
.I4(rgb[0]),
.I5(\dc_bias_reg_n_0_[1] ),
.O(\dc_bias[1]_i_6__1_n_0 ));
LUT6 #(
.INIT(64'h9C3939399C9C9C39))
\dc_bias[1]_i_7__0
(.I0(rgb[2]),
.I1(\dc_bias[2]_i_11__0_n_0 ),
.I2(rgb[3]),
.I3(\dc_bias[3]_i_30_n_0 ),
.I4(\encoded[8]_i_6_n_0 ),
.I5(\dc_bias[3]_i_31_n_0 ),
.O(\dc_bias[1]_i_7__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT2 #(
.INIT(4'hB))
\dc_bias[1]_i_8__0
(.I0(\dc_bias_reg_n_0_[0] ),
.I1(\dc_bias[0]_i_2__0_n_0 ),
.O(\dc_bias[1]_i_8__0_n_0 ));
LUT2 #(
.INIT(4'h6))
\dc_bias[1]_i_9
(.I0(rgb[0]),
.I1(\dc_bias_reg_n_0_[0] ),
.O(\dc_bias[1]_i_9_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT2 #(
.INIT(4'h9))
\dc_bias[2]_i_10__1
(.I0(\dc_bias_reg_n_0_[1] ),
.I1(\dc_bias[3]_i_10__0_n_0 ),
.O(\dc_bias[2]_i_10__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT2 #(
.INIT(4'h6))
\dc_bias[2]_i_11__0
(.I0(rgb[0]),
.I1(rgb[1]),
.O(\dc_bias[2]_i_11__0_n_0 ));
LUT6 #(
.INIT(64'hB888B8BBB8BBB888))
\dc_bias[2]_i_1__0
(.I0(\dc_bias[2]_i_2__1_n_0 ),
.I1(\dc_bias[3]_i_2__0_n_0 ),
.I2(\dc_bias[2]_i_3__0_n_0 ),
.I3(\dc_bias[3]_i_5__1_n_0 ),
.I4(\dc_bias[2]_i_4_n_0 ),
.I5(\dc_bias[2]_i_5__0_n_0 ),
.O(\dc_bias[2]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'h96FF9600960096FF))
\dc_bias[2]_i_2__1
(.I0(\dc_bias_reg_n_0_[2] ),
.I1(\dc_bias[2]_i_6__0_n_0 ),
.I2(\dc_bias[2]_i_7_n_0 ),
.I3(\encoded[8]_i_2_n_0 ),
.I4(\dc_bias[2]_i_8__0_n_0 ),
.I5(\dc_bias[2]_i_9_n_0 ),
.O(\dc_bias[2]_i_2__1_n_0 ));
LUT6 #(
.INIT(64'h04DFFB20FB2004DF))
\dc_bias[2]_i_3__0
(.I0(\dc_bias_reg_n_0_[0] ),
.I1(\dc_bias[0]_i_2__0_n_0 ),
.I2(\encoded[8]_i_2_n_0 ),
.I3(\dc_bias[2]_i_10__1_n_0 ),
.I4(\dc_bias[3]_i_23__1_n_0 ),
.I5(\dc_bias[2]_i_8__0_n_0 ),
.O(\dc_bias[2]_i_3__0_n_0 ));
LUT6 #(
.INIT(64'h711818188EE7E7E7))
\dc_bias[2]_i_4
(.I0(\dc_bias[3]_i_16_n_0 ),
.I1(\dc_bias[3]_i_17_n_0 ),
.I2(\dc_bias_reg_n_0_[1] ),
.I3(\dc_bias_reg_n_0_[0] ),
.I4(rgb[0]),
.I5(\dc_bias_reg_n_0_[2] ),
.O(\dc_bias[2]_i_4_n_0 ));
LUT6 #(
.INIT(64'hBB2BB2BBBBBDDBBB))
\dc_bias[2]_i_5__0
(.I0(\dc_bias[3]_i_11__0_n_0 ),
.I1(\dc_bias[3]_i_12__0_n_0 ),
.I2(\dc_bias[2]_i_11__0_n_0 ),
.I3(\encoded[8]_i_2_n_0 ),
.I4(rgb[2]),
.I5(\dc_bias[0]_i_3__0_n_0 ),
.O(\dc_bias[2]_i_5__0_n_0 ));
LUT6 #(
.INIT(64'h01151501577F7F57))
\dc_bias[2]_i_6__0
(.I0(\dc_bias_reg_n_0_[1] ),
.I1(rgb[0]),
.I2(\dc_bias_reg_n_0_[0] ),
.I3(\dc_bias[0]_i_6_n_0 ),
.I4(\encoded[8]_i_2_n_0 ),
.I5(\dc_bias[3]_i_27__0_n_0 ),
.O(\dc_bias[2]_i_6__0_n_0 ));
LUT6 #(
.INIT(64'h802AA802EABFFEAB))
\dc_bias[2]_i_7
(.I0(\dc_bias[1]_i_5_n_0 ),
.I1(\encoded[8]_i_2_n_0 ),
.I2(rgb[3]),
.I3(\dc_bias[2]_i_11__0_n_0 ),
.I4(rgb[2]),
.I5(\dc_bias[1]_i_6__1_n_0 ),
.O(\dc_bias[2]_i_7_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT2 #(
.INIT(4'h6))
\dc_bias[2]_i_8__0
(.I0(\dc_bias_reg_n_0_[2] ),
.I1(\dc_bias[3]_i_9__0_n_0 ),
.O(\dc_bias[2]_i_8__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT4 #(
.INIT(16'h2B22))
\dc_bias[2]_i_9
(.I0(\dc_bias[3]_i_10__0_n_0 ),
.I1(\dc_bias_reg_n_0_[1] ),
.I2(\dc_bias_reg_n_0_[0] ),
.I3(\dc_bias[0]_i_2__0_n_0 ),
.O(\dc_bias[2]_i_9_n_0 ));
LUT6 #(
.INIT(64'h188EE771E771188E))
\dc_bias[3]_i_10__0
(.I0(\dc_bias[0]_i_5__1_n_0 ),
.I1(\dc_bias[3]_i_29_n_0 ),
.I2(rgb[0]),
.I3(\dc_bias[3]_i_28_n_0 ),
.I4(\dc_bias[3]_i_27__0_n_0 ),
.I5(\dc_bias[1]_i_7__0_n_0 ),
.O(\dc_bias[3]_i_10__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT5 #(
.INIT(32'h96696969))
\dc_bias[3]_i_11__0
(.I0(\dc_bias[3]_i_16_n_0 ),
.I1(\dc_bias[3]_i_17_n_0 ),
.I2(\dc_bias_reg_n_0_[1] ),
.I3(\dc_bias_reg_n_0_[0] ),
.I4(rgb[0]),
.O(\dc_bias[3]_i_11__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT5 #(
.INIT(32'h82EBEB82))
\dc_bias[3]_i_12__0
(.I0(rgb[7]),
.I1(\dc_bias_reg_n_0_[0] ),
.I2(rgb[0]),
.I3(rgb[5]),
.I4(\encoded[6]_i_2__0_n_0 ),
.O(\dc_bias[3]_i_12__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT5 #(
.INIT(32'h96669996))
\dc_bias[3]_i_13__1
(.I0(rgb[1]),
.I1(rgb[0]),
.I2(\dc_bias[3]_i_30_n_0 ),
.I3(\encoded[8]_i_6_n_0 ),
.I4(\dc_bias[3]_i_31_n_0 ),
.O(\dc_bias[3]_i_13__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'h69))
\dc_bias[3]_i_14__1
(.I0(rgb[2]),
.I1(rgb[1]),
.I2(rgb[0]),
.O(\dc_bias[3]_i_14__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT2 #(
.INIT(4'h8))
\dc_bias[3]_i_15__0
(.I0(rgb[0]),
.I1(\dc_bias_reg_n_0_[0] ),
.O(\dc_bias[3]_i_15__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT4 #(
.INIT(16'hB42D))
\dc_bias[3]_i_16
(.I0(\encoded[8]_i_2_n_0 ),
.I1(rgb[4]),
.I2(\encoded[6]_i_2__0_n_0 ),
.I3(rgb[5]),
.O(\dc_bias[3]_i_16_n_0 ));
LUT6 #(
.INIT(64'h1771711771171771))
\dc_bias[3]_i_17
(.I0(\encoded[8]_i_2_n_0 ),
.I1(rgb[7]),
.I2(\encoded[6]_i_2__0_n_0 ),
.I3(rgb[6]),
.I4(rgb[5]),
.I5(rgb[4]),
.O(\dc_bias[3]_i_17_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT5 #(
.INIT(32'h14414114))
\dc_bias[3]_i_18__1
(.I0(\dc_bias[0]_i_5__1_n_0 ),
.I1(rgb[0]),
.I2(\dc_bias[0]_i_6_n_0 ),
.I3(\dc_bias[0]_i_7_n_0 ),
.I4(rgb[6]),
.O(\dc_bias[3]_i_18__1_n_0 ));
LUT6 #(
.INIT(64'h82BE14D714D782BE))
\dc_bias[3]_i_19__0
(.I0(\encoded[8]_i_2_n_0 ),
.I1(rgb[7]),
.I2(\encoded[7]_i_2_n_0 ),
.I3(rgb[0]),
.I4(\dc_bias[0]_i_7_n_0 ),
.I5(rgb[6]),
.O(\dc_bias[3]_i_19__0_n_0 ));
LUT6 #(
.INIT(64'h00000000FFFFAAEB))
\dc_bias[3]_i_1__0
(.I0(\dc_bias[3]_i_2__0_n_0 ),
.I1(\dc_bias[3]_i_3__0_n_0 ),
.I2(\dc_bias[3]_i_4__0_n_0 ),
.I3(\dc_bias[3]_i_5__1_n_0 ),
.I4(\dc_bias[3]_i_6__0_n_0 ),
.I5(\dc_bias[3]_i_7__0_n_0 ),
.O(\dc_bias[3]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'h42BDBD42BD4242BD))
\dc_bias[3]_i_20
(.I0(rgb[6]),
.I1(\encoded[8]_i_2_n_0 ),
.I2(rgb[5]),
.I3(rgb[4]),
.I4(\encoded[6]_i_2__0_n_0 ),
.I5(\dc_bias[1]_i_7__0_n_0 ),
.O(\dc_bias[3]_i_20_n_0 ));
LUT6 #(
.INIT(64'hBAAEEFFBEFFBBAAE))
\dc_bias[3]_i_21__1
(.I0(\dc_bias[1]_i_7__0_n_0 ),
.I1(rgb[6]),
.I2(\encoded[8]_i_2_n_0 ),
.I3(rgb[5]),
.I4(rgb[4]),
.I5(\encoded[6]_i_2__0_n_0 ),
.O(\dc_bias[3]_i_21__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT5 #(
.INIT(32'h99F99099))
\dc_bias[3]_i_22__0
(.I0(\dc_bias_reg_n_0_[1] ),
.I1(\dc_bias[3]_i_10__0_n_0 ),
.I2(\encoded[8]_i_2_n_0 ),
.I3(\dc_bias[0]_i_2__0_n_0 ),
.I4(\dc_bias_reg_n_0_[0] ),
.O(\dc_bias[3]_i_22__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT2 #(
.INIT(4'hB))
\dc_bias[3]_i_23__1
(.I0(\dc_bias[3]_i_10__0_n_0 ),
.I1(\dc_bias_reg_n_0_[1] ),
.O(\dc_bias[3]_i_23__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hDF))
\dc_bias[3]_i_24__0
(.I0(\dc_bias_reg_n_0_[0] ),
.I1(\dc_bias[0]_i_2__0_n_0 ),
.I2(\encoded[8]_i_2_n_0 ),
.O(\dc_bias[3]_i_24__0_n_0 ));
LUT6 #(
.INIT(64'h002BD400FFD42BFF))
\dc_bias[3]_i_25__0
(.I0(\dc_bias[1]_i_5_n_0 ),
.I1(\dc_bias[1]_i_7__0_n_0 ),
.I2(\dc_bias[1]_i_6__1_n_0 ),
.I3(\dc_bias[2]_i_6__0_n_0 ),
.I4(\dc_bias_reg_n_0_[2] ),
.I5(p_1_in),
.O(\dc_bias[3]_i_25__0_n_0 ));
LUT6 #(
.INIT(64'hFFFFD4DDD4DD0000))
\dc_bias[3]_i_26__0
(.I0(\dc_bias[3]_i_10__0_n_0 ),
.I1(\dc_bias_reg_n_0_[1] ),
.I2(\dc_bias_reg_n_0_[0] ),
.I3(\dc_bias[0]_i_2__0_n_0 ),
.I4(\dc_bias_reg_n_0_[2] ),
.I5(\dc_bias[3]_i_9__0_n_0 ),
.O(\dc_bias[3]_i_26__0_n_0 ));
LUT6 #(
.INIT(64'hEBBBEEEB82228882))
\dc_bias[3]_i_27__0
(.I0(\dc_bias[0]_i_7_n_0 ),
.I1(\dc_bias[3]_i_32_n_0 ),
.I2(\dc_bias[3]_i_30_n_0 ),
.I3(\encoded[8]_i_6_n_0 ),
.I4(\dc_bias[3]_i_31_n_0 ),
.I5(\encoded[7]_i_2_n_0 ),
.O(\dc_bias[3]_i_27__0_n_0 ));
LUT6 #(
.INIT(64'h8E71718E718E8E71))
\dc_bias[3]_i_28
(.I0(\dc_bias[3]_i_30_n_0 ),
.I1(\encoded[8]_i_6_n_0 ),
.I2(\dc_bias[3]_i_31_n_0 ),
.I3(rgb[4]),
.I4(\encoded[6]_i_2__0_n_0 ),
.I5(rgb[6]),
.O(\dc_bias[3]_i_28_n_0 ));
LUT6 #(
.INIT(64'hBAFB5D45BAFB4504))
\dc_bias[3]_i_29
(.I0(\encoded[8]_i_6_n_0 ),
.I1(\encoded[8]_i_5_n_0 ),
.I2(\encoded[8]_i_4_n_0 ),
.I3(\encoded[8]_i_3_n_0 ),
.I4(\dc_bias[0]_i_6_n_0 ),
.I5(rgb[0]),
.O(\dc_bias[3]_i_29_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT4 #(
.INIT(16'hAAAE))
\dc_bias[3]_i_2__0
(.I0(\dc_bias[3]_i_8__0_n_0 ),
.I1(\dc_bias[3]_i_9__0_n_0 ),
.I2(\dc_bias[3]_i_10__0_n_0 ),
.I3(\dc_bias[0]_i_2__0_n_0 ),
.O(\dc_bias[3]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'h0000F6606000FFF6))
\dc_bias[3]_i_30
(.I0(\dc_bias[3]_i_33_n_0 ),
.I1(rgb[6]),
.I2(rgb[7]),
.I3(rgb[0]),
.I4(\encoded[8]_i_5_n_0 ),
.I5(\dc_bias[3]_i_34_n_0 ),
.O(\dc_bias[3]_i_30_n_0 ));
LUT6 #(
.INIT(64'h4008000029610000))
\dc_bias[3]_i_31
(.I0(rgb[7]),
.I1(\encoded[6]_i_2__0_n_0 ),
.I2(\encoded[8]_i_7_n_0 ),
.I3(\dc_bias[3]_i_34_n_0 ),
.I4(rgb[0]),
.I5(\encoded[8]_i_5_n_0 ),
.O(\dc_bias[3]_i_31_n_0 ));
LUT6 #(
.INIT(64'h9669699669969669))
\dc_bias[3]_i_32
(.I0(rgb[5]),
.I1(rgb[4]),
.I2(rgb[2]),
.I3(rgb[1]),
.I4(rgb[0]),
.I5(rgb[3]),
.O(\dc_bias[3]_i_32_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT2 #(
.INIT(4'h6))
\dc_bias[3]_i_33
(.I0(rgb[4]),
.I1(rgb[5]),
.O(\dc_bias[3]_i_33_n_0 ));
LUT3 #(
.INIT(8'h69))
\dc_bias[3]_i_34
(.I0(rgb[3]),
.I1(rgb[2]),
.I2(rgb[1]),
.O(\dc_bias[3]_i_34_n_0 ));
LUT6 #(
.INIT(64'h8A088A8A8A8AAE8A))
\dc_bias[3]_i_3__0
(.I0(\dc_bias[2]_i_4_n_0 ),
.I1(\dc_bias[3]_i_11__0_n_0 ),
.I2(\dc_bias[3]_i_12__0_n_0 ),
.I3(\dc_bias[3]_i_13__1_n_0 ),
.I4(\dc_bias[3]_i_14__1_n_0 ),
.I5(\dc_bias[0]_i_3__0_n_0 ),
.O(\dc_bias[3]_i_3__0_n_0 ));
LUT6 #(
.INIT(64'h56555555AA6A6A56))
\dc_bias[3]_i_4__0
(.I0(p_1_in),
.I1(\dc_bias[3]_i_15__0_n_0 ),
.I2(\dc_bias_reg_n_0_[1] ),
.I3(\dc_bias[3]_i_16_n_0 ),
.I4(\dc_bias[3]_i_17_n_0 ),
.I5(\dc_bias_reg_n_0_[2] ),
.O(\dc_bias[3]_i_4__0_n_0 ));
LUT5 #(
.INIT(32'hA6655555))
\dc_bias[3]_i_5__1
(.I0(p_1_in),
.I1(\dc_bias[3]_i_18__1_n_0 ),
.I2(\dc_bias[3]_i_19__0_n_0 ),
.I3(\dc_bias[3]_i_20_n_0 ),
.I4(\dc_bias[3]_i_21__1_n_0 ),
.O(\dc_bias[3]_i_5__1_n_0 ));
LUT6 #(
.INIT(64'h000C40404040CCC0))
\dc_bias[3]_i_6__0
(.I0(\dc_bias[3]_i_22__0_n_0 ),
.I1(\dc_bias[3]_i_5__1_n_0 ),
.I2(\dc_bias[3]_i_23__1_n_0 ),
.I3(\dc_bias[3]_i_24__0_n_0 ),
.I4(\dc_bias[3]_i_9__0_n_0 ),
.I5(\dc_bias_reg_n_0_[2] ),
.O(\dc_bias[3]_i_6__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT5 #(
.INIT(32'hB08080B0))
\dc_bias[3]_i_7__0
(.I0(\dc_bias[3]_i_25__0_n_0 ),
.I1(\encoded[8]_i_2_n_0 ),
.I2(\dc_bias[3]_i_2__0_n_0 ),
.I3(\dc_bias[3]_i_26__0_n_0 ),
.I4(\dc_bias[3]_i_5__1_n_0 ),
.O(\dc_bias[3]_i_7__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT4 #(
.INIT(16'h0001))
\dc_bias[3]_i_8__0
(.I0(\dc_bias_reg_n_0_[0] ),
.I1(\dc_bias_reg_n_0_[2] ),
.I2(p_1_in),
.I3(\dc_bias_reg_n_0_[1] ),
.O(\dc_bias[3]_i_8__0_n_0 ));
LUT6 #(
.INIT(64'hD444DDD4DDD4BDDD))
\dc_bias[3]_i_9__0
(.I0(\dc_bias[1]_i_7__0_n_0 ),
.I1(\dc_bias[3]_i_27__0_n_0 ),
.I2(\dc_bias[3]_i_28_n_0 ),
.I3(rgb[0]),
.I4(\dc_bias[3]_i_29_n_0 ),
.I5(\dc_bias[0]_i_5__1_n_0 ),
.O(\dc_bias[3]_i_9__0_n_0 ));
FDRE #(
.INIT(1'b0))
\dc_bias_reg[0]
(.C(clk_25),
.CE(1'b1),
.D(\dc_bias[0]_i_1__0_n_0 ),
.Q(\dc_bias_reg_n_0_[0] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\dc_bias_reg[1]
(.C(clk_25),
.CE(1'b1),
.D(\dc_bias[1]_i_1_n_0 ),
.Q(\dc_bias_reg_n_0_[1] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\dc_bias_reg[2]
(.C(clk_25),
.CE(1'b1),
.D(\dc_bias[2]_i_1__0_n_0 ),
.Q(\dc_bias_reg_n_0_[2] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\dc_bias_reg[3]
(.C(clk_25),
.CE(1'b1),
.D(\dc_bias[3]_i_1__0_n_0 ),
.Q(p_1_in),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'h82))
\encoded[0]_i_1__0
(.I0(active),
.I1(rgb[0]),
.I2(\encoded[9]_i_2__0_n_0 ),
.O(\encoded[0]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT4 #(
.INIT(16'h2882))
\encoded[1]_i_1__0
(.I0(active),
.I1(rgb[1]),
.I2(rgb[0]),
.I3(\encoded[7]_i_3__0_n_0 ),
.O(\encoded[1]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT5 #(
.INIT(32'hD77D7DD7))
\encoded[2]_i_1__0
(.I0(active),
.I1(rgb[0]),
.I2(rgb[1]),
.I3(rgb[2]),
.I4(\encoded[9]_i_2__0_n_0 ),
.O(\encoded[2]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'h2882822882282882))
\encoded[3]_i_1__0
(.I0(active),
.I1(rgb[2]),
.I2(rgb[1]),
.I3(rgb[0]),
.I4(rgb[3]),
.I5(\encoded[7]_i_3__0_n_0 ),
.O(\encoded[3]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT4 #(
.INIT(16'hD77D))
\encoded[4]_i_1__0
(.I0(active),
.I1(\encoded[6]_i_2__0_n_0 ),
.I2(rgb[4]),
.I3(\encoded[9]_i_2__0_n_0 ),
.O(\encoded[4]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT5 #(
.INIT(32'h28828228))
\encoded[5]_i_1__0
(.I0(active),
.I1(\encoded[6]_i_2__0_n_0 ),
.I2(rgb[4]),
.I3(rgb[5]),
.I4(\encoded[7]_i_3__0_n_0 ),
.O(\encoded[5]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hD77D7DD77DD7D77D))
\encoded[6]_i_1__0
(.I0(active),
.I1(\encoded[6]_i_2__0_n_0 ),
.I2(rgb[6]),
.I3(rgb[5]),
.I4(rgb[4]),
.I5(\encoded[9]_i_2__0_n_0 ),
.O(\encoded[6]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT4 #(
.INIT(16'h9669))
\encoded[6]_i_2__0
(.I0(rgb[3]),
.I1(rgb[0]),
.I2(rgb[1]),
.I3(rgb[2]),
.O(\encoded[6]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT4 #(
.INIT(16'h2882))
\encoded[7]_i_1__0
(.I0(active),
.I1(\encoded[7]_i_2_n_0 ),
.I2(rgb[7]),
.I3(\encoded[7]_i_3__0_n_0 ),
.O(\encoded[7]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT4 #(
.INIT(16'h9669))
\encoded[7]_i_2
(.I0(rgb[4]),
.I1(rgb[5]),
.I2(rgb[6]),
.I3(\encoded[6]_i_2__0_n_0 ),
.O(\encoded[7]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT3 #(
.INIT(8'hBE))
\encoded[7]_i_3__0
(.I0(\dc_bias[3]_i_2__0_n_0 ),
.I1(\dc_bias[3]_i_5__1_n_0 ),
.I2(\encoded[8]_i_2_n_0 ),
.O(\encoded[7]_i_3__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT2 #(
.INIT(4'hB))
\encoded[8]_i_1__0
(.I0(\encoded[8]_i_2_n_0 ),
.I1(active),
.O(\encoded[8]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'h00200000F2FF20F2))
\encoded[8]_i_2
(.I0(rgb[0]),
.I1(\dc_bias[0]_i_6_n_0 ),
.I2(\encoded[8]_i_3_n_0 ),
.I3(\encoded[8]_i_4_n_0 ),
.I4(\encoded[8]_i_5_n_0 ),
.I5(\encoded[8]_i_6_n_0 ),
.O(\encoded[8]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFF6969FF69FFFF69))
\encoded[8]_i_3
(.I0(rgb[1]),
.I1(rgb[2]),
.I2(rgb[3]),
.I3(rgb[0]),
.I4(rgb[7]),
.I5(\encoded[8]_i_7_n_0 ),
.O(\encoded[8]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT5 #(
.INIT(32'hE88E8EE8))
\encoded[8]_i_4
(.I0(rgb[0]),
.I1(rgb[7]),
.I2(rgb[6]),
.I3(rgb[5]),
.I4(rgb[4]),
.O(\encoded[8]_i_4_n_0 ));
LUT6 #(
.INIT(64'hE8E8E817E8171717))
\encoded[8]_i_5
(.I0(rgb[2]),
.I1(rgb[3]),
.I2(rgb[1]),
.I3(rgb[6]),
.I4(rgb[5]),
.I5(rgb[4]),
.O(\encoded[8]_i_5_n_0 ));
LUT6 #(
.INIT(64'hE8E8E800E8000000))
\encoded[8]_i_6
(.I0(rgb[6]),
.I1(rgb[5]),
.I2(rgb[4]),
.I3(rgb[2]),
.I4(rgb[3]),
.I5(rgb[1]),
.O(\encoded[8]_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT3 #(
.INIT(8'h69))
\encoded[8]_i_7
(.I0(rgb[6]),
.I1(rgb[5]),
.I2(rgb[4]),
.O(\encoded[8]_i_7_n_0 ));
LUT2 #(
.INIT(4'h7))
\encoded[9]_i_1
(.I0(active),
.I1(\encoded[9]_i_2__0_n_0 ),
.O(\encoded[9]_i_1_n_0 ));
LUT3 #(
.INIT(8'h8B))
\encoded[9]_i_2__0
(.I0(\encoded[8]_i_2_n_0 ),
.I1(\dc_bias[3]_i_2__0_n_0 ),
.I2(\dc_bias[3]_i_5__1_n_0 ),
.O(\encoded[9]_i_2__0_n_0 ));
FDRE \encoded_reg[0]
(.C(clk_25),
.CE(1'b1),
.D(\encoded[0]_i_1__0_n_0 ),
.Q(\encoded_reg_n_0_[0] ),
.R(1'b0));
FDRE \encoded_reg[1]
(.C(clk_25),
.CE(1'b1),
.D(\encoded[1]_i_1__0_n_0 ),
.Q(\encoded_reg_n_0_[1] ),
.R(1'b0));
FDRE \encoded_reg[2]
(.C(clk_25),
.CE(1'b1),
.D(\encoded[2]_i_1__0_n_0 ),
.Q(\encoded_reg_n_0_[2] ),
.R(1'b0));
FDRE \encoded_reg[3]
(.C(clk_25),
.CE(1'b1),
.D(\encoded[3]_i_1__0_n_0 ),
.Q(\encoded_reg_n_0_[3] ),
.R(1'b0));
FDRE \encoded_reg[4]
(.C(clk_25),
.CE(1'b1),
.D(\encoded[4]_i_1__0_n_0 ),
.Q(\encoded_reg_n_0_[4] ),
.R(1'b0));
FDRE \encoded_reg[5]
(.C(clk_25),
.CE(1'b1),
.D(\encoded[5]_i_1__0_n_0 ),
.Q(\encoded_reg_n_0_[5] ),
.R(1'b0));
FDRE \encoded_reg[6]
(.C(clk_25),
.CE(1'b1),
.D(\encoded[6]_i_1__0_n_0 ),
.Q(\encoded_reg_n_0_[6] ),
.R(1'b0));
FDRE \encoded_reg[7]
(.C(clk_25),
.CE(1'b1),
.D(\encoded[7]_i_1__0_n_0 ),
.Q(\encoded_reg_n_0_[7] ),
.R(1'b0));
FDRE \encoded_reg[8]
(.C(clk_25),
.CE(1'b1),
.D(\encoded[8]_i_1__0_n_0 ),
.Q(Q[0]),
.R(1'b0));
FDRE \encoded_reg[9]
(.C(clk_25),
.CE(1'b1),
.D(\encoded[9]_i_1_n_0 ),
.Q(Q[1]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT3 #(
.INIT(8'hB8))
\shift_green[0]_i_1
(.I0(shift_green[0]),
.I1(\shift_clock_reg[5] ),
.I2(\encoded_reg_n_0_[0] ),
.O(D[0]));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hB8))
\shift_green[1]_i_1
(.I0(shift_green[1]),
.I1(\shift_clock_reg[5] ),
.I2(\encoded_reg_n_0_[1] ),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hB8))
\shift_green[2]_i_1
(.I0(shift_green[2]),
.I1(\shift_clock_reg[5] ),
.I2(\encoded_reg_n_0_[2] ),
.O(D[2]));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hB8))
\shift_green[3]_i_1
(.I0(shift_green[3]),
.I1(\shift_clock_reg[5] ),
.I2(\encoded_reg_n_0_[3] ),
.O(D[3]));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hB8))
\shift_green[4]_i_1
(.I0(shift_green[4]),
.I1(\shift_clock_reg[5] ),
.I2(\encoded_reg_n_0_[4] ),
.O(D[4]));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hB8))
\shift_green[5]_i_1
(.I0(shift_green[5]),
.I1(\shift_clock_reg[5] ),
.I2(\encoded_reg_n_0_[5] ),
.O(D[5]));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hB8))
\shift_green[6]_i_1
(.I0(shift_green[6]),
.I1(\shift_clock_reg[5] ),
.I2(\encoded_reg_n_0_[6] ),
.O(D[6]));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT3 #(
.INIT(8'hB8))
\shift_green[7]_i_1
(.I0(shift_green[7]),
.I1(\shift_clock_reg[5] ),
.I2(\encoded_reg_n_0_[7] ),
.O(D[7]));
endmodule
(* ORIG_REF_NAME = "TMDS_encoder" *)
module system_zybo_hdmi_0_0_TMDS_encoder_1
(D,
Q,
rgb,
active,
data1,
\shift_clock_reg[5] ,
SR,
clk_25);
output [7:0]D;
output [1:0]Q;
input [7:0]rgb;
input active;
input [7:0]data1;
input \shift_clock_reg[5] ;
input [0:0]SR;
input clk_25;
wire [7:0]D;
wire [1:0]Q;
wire [0:0]SR;
wire active;
wire clk_25;
wire [7:0]data1;
wire \dc_bias[0]_i_1_n_0 ;
wire \dc_bias[0]_i_2_n_0 ;
wire \dc_bias[0]_i_3_n_0 ;
wire \dc_bias[0]_i_4_n_0 ;
wire \dc_bias[0]_i_5_n_0 ;
wire \dc_bias[0]_i_6__0_n_0 ;
wire \dc_bias[1]_i_2_n_0 ;
wire \dc_bias[1]_i_3_n_0 ;
wire \dc_bias[1]_i_4_n_0 ;
wire \dc_bias[1]_i_5__0_n_0 ;
wire \dc_bias[1]_i_6_n_0 ;
wire \dc_bias[1]_i_7_n_0 ;
wire \dc_bias[2]_i_10__0_n_0 ;
wire \dc_bias[2]_i_11_n_0 ;
wire \dc_bias[2]_i_12_n_0 ;
wire \dc_bias[2]_i_13_n_0 ;
wire \dc_bias[2]_i_14_n_0 ;
wire \dc_bias[2]_i_15_n_0 ;
wire \dc_bias[2]_i_16_n_0 ;
wire \dc_bias[2]_i_17_n_0 ;
wire \dc_bias[2]_i_18_n_0 ;
wire \dc_bias[2]_i_19_n_0 ;
wire \dc_bias[2]_i_1_n_0 ;
wire \dc_bias[2]_i_20_n_0 ;
wire \dc_bias[2]_i_21_n_0 ;
wire \dc_bias[2]_i_22_n_0 ;
wire \dc_bias[2]_i_2_n_0 ;
wire \dc_bias[2]_i_3_n_0 ;
wire \dc_bias[2]_i_4__0_n_0 ;
wire \dc_bias[2]_i_5_n_0 ;
wire \dc_bias[2]_i_6_n_0 ;
wire \dc_bias[2]_i_7__1_n_0 ;
wire \dc_bias[2]_i_8_n_0 ;
wire \dc_bias[2]_i_9__1_n_0 ;
wire \dc_bias[3]_i_10_n_0 ;
wire \dc_bias[3]_i_11_n_0 ;
wire \dc_bias[3]_i_12_n_0 ;
wire \dc_bias[3]_i_13_n_0 ;
wire \dc_bias[3]_i_14_n_0 ;
wire \dc_bias[3]_i_15_n_0 ;
wire \dc_bias[3]_i_16__1_n_0 ;
wire \dc_bias[3]_i_17__1_n_0 ;
wire \dc_bias[3]_i_18_n_0 ;
wire \dc_bias[3]_i_19_n_0 ;
wire \dc_bias[3]_i_20__1_n_0 ;
wire \dc_bias[3]_i_21__0_n_0 ;
wire \dc_bias[3]_i_22_n_0 ;
wire \dc_bias[3]_i_23_n_0 ;
wire \dc_bias[3]_i_24_n_0 ;
wire \dc_bias[3]_i_25_n_0 ;
wire \dc_bias[3]_i_26_n_0 ;
wire \dc_bias[3]_i_27_n_0 ;
wire \dc_bias[3]_i_2_n_0 ;
wire \dc_bias[3]_i_3_n_0 ;
wire \dc_bias[3]_i_4_n_0 ;
wire \dc_bias[3]_i_5__0_n_0 ;
wire \dc_bias[3]_i_6_n_0 ;
wire \dc_bias[3]_i_7_n_0 ;
wire \dc_bias[3]_i_8_n_0 ;
wire \dc_bias[3]_i_9_n_0 ;
wire \dc_bias_reg[1]_i_1_n_0 ;
wire \dc_bias_reg_n_0_[0] ;
wire \dc_bias_reg_n_0_[1] ;
wire \dc_bias_reg_n_0_[2] ;
wire [7:0]encoded;
wire \encoded[6]_i_2_n_0 ;
wire \encoded[7]_i_2__0_n_0 ;
wire \encoded[7]_i_3_n_0 ;
wire \encoded[8]_i_1_n_0 ;
wire \encoded[9]_i_1__0_n_0 ;
wire \encoded[9]_i_2_n_0 ;
wire \encoded_reg_n_0_[0] ;
wire \encoded_reg_n_0_[1] ;
wire \encoded_reg_n_0_[2] ;
wire \encoded_reg_n_0_[3] ;
wire \encoded_reg_n_0_[4] ;
wire \encoded_reg_n_0_[5] ;
wire \encoded_reg_n_0_[6] ;
wire \encoded_reg_n_0_[7] ;
wire p_1_in;
wire [7:0]rgb;
wire \shift_clock_reg[5] ;
LUT6 #(
.INIT(64'h6F60606F606F6F60))
\dc_bias[0]_i_1
(.I0(\dc_bias_reg_n_0_[0] ),
.I1(\dc_bias[0]_i_2_n_0 ),
.I2(\dc_bias[3]_i_6_n_0 ),
.I3(\dc_bias[2]_i_4__0_n_0 ),
.I4(\dc_bias[0]_i_3_n_0 ),
.I5(\dc_bias[0]_i_4_n_0 ),
.O(\dc_bias[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT4 #(
.INIT(16'h6996))
\dc_bias[0]_i_2
(.I0(rgb[1]),
.I1(rgb[3]),
.I2(\dc_bias[0]_i_5_n_0 ),
.I3(\dc_bias[0]_i_6__0_n_0 ),
.O(\dc_bias[0]_i_2_n_0 ));
LUT5 #(
.INIT(32'h69969669))
\dc_bias[0]_i_3
(.I0(\encoded[6]_i_2_n_0 ),
.I1(rgb[5]),
.I2(rgb[0]),
.I3(\dc_bias_reg_n_0_[0] ),
.I4(rgb[7]),
.O(\dc_bias[0]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT2 #(
.INIT(4'h9))
\dc_bias[0]_i_4
(.I0(rgb[2]),
.I1(\dc_bias[3]_i_4_n_0 ),
.O(\dc_bias[0]_i_4_n_0 ));
LUT6 #(
.INIT(64'h9669699669969669))
\dc_bias[0]_i_5
(.I0(\encoded[6]_i_2_n_0 ),
.I1(rgb[4]),
.I2(rgb[5]),
.I3(rgb[6]),
.I4(rgb[7]),
.I5(\dc_bias[3]_i_4_n_0 ),
.O(\dc_bias[0]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT4 #(
.INIT(16'h9669))
\dc_bias[0]_i_6__0
(.I0(\dc_bias[3]_i_4_n_0 ),
.I1(rgb[4]),
.I2(\encoded[6]_i_2_n_0 ),
.I3(rgb[6]),
.O(\dc_bias[0]_i_6__0_n_0 ));
LUT6 #(
.INIT(64'hCC3CC3CC55555555))
\dc_bias[1]_i_2
(.I0(\dc_bias[1]_i_4_n_0 ),
.I1(\dc_bias[1]_i_5__0_n_0 ),
.I2(\dc_bias[3]_i_4_n_0 ),
.I3(\dc_bias[0]_i_2_n_0 ),
.I4(\dc_bias_reg_n_0_[0] ),
.I5(\dc_bias[2]_i_4__0_n_0 ),
.O(\dc_bias[1]_i_2_n_0 ));
LUT6 #(
.INIT(64'hF00F0FF099999999))
\dc_bias[1]_i_3
(.I0(\dc_bias[3]_i_16__1_n_0 ),
.I1(\dc_bias[1]_i_5__0_n_0 ),
.I2(\dc_bias[1]_i_6_n_0 ),
.I3(\dc_bias[1]_i_7_n_0 ),
.I4(\dc_bias[2]_i_12_n_0 ),
.I5(\dc_bias[3]_i_4_n_0 ),
.O(\dc_bias[1]_i_3_n_0 ));
LUT6 #(
.INIT(64'h95A9A96A569595A9))
\dc_bias[1]_i_4
(.I0(\dc_bias[2]_i_18_n_0 ),
.I1(\dc_bias[2]_i_16_n_0 ),
.I2(\dc_bias[2]_i_17_n_0 ),
.I3(\dc_bias[2]_i_19_n_0 ),
.I4(\dc_bias[2]_i_20_n_0 ),
.I5(rgb[7]),
.O(\dc_bias[1]_i_4_n_0 ));
LUT6 #(
.INIT(64'h9996699969996669))
\dc_bias[1]_i_5__0
(.I0(\dc_bias_reg_n_0_[1] ),
.I1(\dc_bias[3]_i_26_n_0 ),
.I2(\dc_bias[0]_i_6__0_n_0 ),
.I3(\dc_bias[0]_i_5_n_0 ),
.I4(rgb[0]),
.I5(\dc_bias[3]_i_25_n_0 ),
.O(\dc_bias[1]_i_5__0_n_0 ));
LUT6 #(
.INIT(64'h5CC5355335535CC5))
\dc_bias[1]_i_6
(.I0(\dc_bias[0]_i_6__0_n_0 ),
.I1(rgb[0]),
.I2(\dc_bias_reg_n_0_[0] ),
.I3(\dc_bias[0]_i_5_n_0 ),
.I4(rgb[3]),
.I5(rgb[1]),
.O(\dc_bias[1]_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT5 #(
.INIT(32'hA665599A))
\dc_bias[1]_i_7
(.I0(\dc_bias[2]_i_13_n_0 ),
.I1(\dc_bias[0]_i_5_n_0 ),
.I2(\dc_bias_reg_n_0_[0] ),
.I3(rgb[0]),
.I4(\dc_bias_reg_n_0_[1] ),
.O(\dc_bias[1]_i_7_n_0 ));
LUT6 #(
.INIT(64'hB888B8BBB8BBB888))
\dc_bias[2]_i_1
(.I0(\dc_bias[2]_i_2_n_0 ),
.I1(\dc_bias[3]_i_6_n_0 ),
.I2(\dc_bias[2]_i_3_n_0 ),
.I3(\dc_bias[2]_i_4__0_n_0 ),
.I4(\dc_bias[2]_i_5_n_0 ),
.I5(\dc_bias[2]_i_6_n_0 ),
.O(\dc_bias[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT5 #(
.INIT(32'h90060690))
\dc_bias[2]_i_10__0
(.I0(\dc_bias[0]_i_5_n_0 ),
.I1(\dc_bias[0]_i_6__0_n_0 ),
.I2(rgb[0]),
.I3(rgb[1]),
.I4(rgb[3]),
.O(\dc_bias[2]_i_10__0_n_0 ));
LUT6 #(
.INIT(64'h3AA3ACCAACCA3AA3))
\dc_bias[2]_i_11
(.I0(rgb[0]),
.I1(\dc_bias[3]_i_4_n_0 ),
.I2(rgb[7]),
.I3(\encoded[7]_i_2__0_n_0 ),
.I4(\dc_bias[2]_i_22_n_0 ),
.I5(rgb[6]),
.O(\dc_bias[2]_i_11_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT5 #(
.INIT(32'h2DD2B44B))
\dc_bias[2]_i_12
(.I0(rgb[2]),
.I1(\dc_bias[3]_i_4_n_0 ),
.I2(rgb[0]),
.I3(rgb[1]),
.I4(rgb[3]),
.O(\dc_bias[2]_i_12_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT5 #(
.INIT(32'hA59669A5))
\dc_bias[2]_i_13
(.I0(rgb[4]),
.I1(rgb[5]),
.I2(\encoded[6]_i_2_n_0 ),
.I3(\dc_bias[3]_i_4_n_0 ),
.I4(rgb[6]),
.O(\dc_bias[2]_i_13_n_0 ));
LUT6 #(
.INIT(64'h1771711771171771))
\dc_bias[2]_i_14
(.I0(\dc_bias[3]_i_4_n_0 ),
.I1(rgb[7]),
.I2(rgb[6]),
.I3(rgb[5]),
.I4(rgb[4]),
.I5(\encoded[6]_i_2_n_0 ),
.O(\dc_bias[2]_i_14_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT4 #(
.INIT(16'h4BD2))
\dc_bias[2]_i_15
(.I0(\dc_bias[3]_i_4_n_0 ),
.I1(rgb[4]),
.I2(\encoded[6]_i_2_n_0 ),
.I3(rgb[5]),
.O(\dc_bias[2]_i_15_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT3 #(
.INIT(8'h69))
\dc_bias[2]_i_16
(.I0(rgb[2]),
.I1(rgb[1]),
.I2(rgb[0]),
.O(\dc_bias[2]_i_16_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT3 #(
.INIT(8'h96))
\dc_bias[2]_i_17
(.I0(rgb[1]),
.I1(rgb[0]),
.I2(\dc_bias[3]_i_4_n_0 ),
.O(\dc_bias[2]_i_17_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT5 #(
.INIT(32'h69969696))
\dc_bias[2]_i_18
(.I0(\dc_bias[2]_i_15_n_0 ),
.I1(\dc_bias[2]_i_14_n_0 ),
.I2(\dc_bias_reg_n_0_[1] ),
.I3(\dc_bias_reg_n_0_[0] ),
.I4(rgb[0]),
.O(\dc_bias[2]_i_18_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT5 #(
.INIT(32'h96696996))
\dc_bias[2]_i_19
(.I0(rgb[5]),
.I1(rgb[2]),
.I2(rgb[1]),
.I3(rgb[0]),
.I4(rgb[3]),
.O(\dc_bias[2]_i_19_n_0 ));
LUT5 #(
.INIT(32'h6F60606F))
\dc_bias[2]_i_2
(.I0(\dc_bias[2]_i_7__1_n_0 ),
.I1(\dc_bias[3]_i_9_n_0 ),
.I2(\dc_bias[3]_i_4_n_0 ),
.I3(\dc_bias[2]_i_8_n_0 ),
.I4(\dc_bias[2]_i_9__1_n_0 ),
.O(\dc_bias[2]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT2 #(
.INIT(4'h6))
\dc_bias[2]_i_20
(.I0(rgb[0]),
.I1(\dc_bias_reg_n_0_[0] ),
.O(\dc_bias[2]_i_20_n_0 ));
LUT5 #(
.INIT(32'h96696996))
\dc_bias[2]_i_21
(.I0(rgb[6]),
.I1(\dc_bias[2]_i_22_n_0 ),
.I2(\encoded[7]_i_2__0_n_0 ),
.I3(rgb[7]),
.I4(rgb[0]),
.O(\dc_bias[2]_i_21_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT5 #(
.INIT(32'h96696996))
\dc_bias[2]_i_22
(.I0(rgb[4]),
.I1(rgb[2]),
.I2(rgb[1]),
.I3(rgb[0]),
.I4(rgb[3]),
.O(\dc_bias[2]_i_22_n_0 ));
LUT6 #(
.INIT(64'h56569556566A5656))
\dc_bias[2]_i_3
(.I0(\dc_bias[2]_i_8_n_0 ),
.I1(\dc_bias_reg_n_0_[1] ),
.I2(\dc_bias[3]_i_17__1_n_0 ),
.I3(\dc_bias[3]_i_4_n_0 ),
.I4(\dc_bias[0]_i_2_n_0 ),
.I5(\dc_bias_reg_n_0_[0] ),
.O(\dc_bias[2]_i_3_n_0 ));
LUT5 #(
.INIT(32'h5556566A))
\dc_bias[2]_i_4__0
(.I0(p_1_in),
.I1(\dc_bias[2]_i_10__0_n_0 ),
.I2(\dc_bias[2]_i_11_n_0 ),
.I3(\dc_bias[2]_i_12_n_0 ),
.I4(\dc_bias[2]_i_13_n_0 ),
.O(\dc_bias[2]_i_4__0_n_0 ));
LUT6 #(
.INIT(64'hD44242422BBDBDBD))
\dc_bias[2]_i_5
(.I0(\dc_bias[2]_i_14_n_0 ),
.I1(\dc_bias[2]_i_15_n_0 ),
.I2(\dc_bias_reg_n_0_[1] ),
.I3(\dc_bias_reg_n_0_[0] ),
.I4(rgb[0]),
.I5(\dc_bias_reg_n_0_[2] ),
.O(\dc_bias[2]_i_5_n_0 ));
LUT6 #(
.INIT(64'hF7F1F170EFF7F7F1))
\dc_bias[2]_i_6
(.I0(\dc_bias[2]_i_16_n_0 ),
.I1(\dc_bias[2]_i_17_n_0 ),
.I2(\dc_bias[2]_i_18_n_0 ),
.I3(\dc_bias[2]_i_19_n_0 ),
.I4(\dc_bias[2]_i_20_n_0 ),
.I5(rgb[7]),
.O(\dc_bias[2]_i_6_n_0 ));
LUT6 #(
.INIT(64'h5565656666A6A6AA))
\dc_bias[2]_i_7__1
(.I0(\dc_bias_reg_n_0_[2] ),
.I1(\dc_bias[2]_i_13_n_0 ),
.I2(\dc_bias[0]_i_5_n_0 ),
.I3(\dc_bias_reg_n_0_[0] ),
.I4(rgb[0]),
.I5(\dc_bias_reg_n_0_[1] ),
.O(\dc_bias[2]_i_7__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT2 #(
.INIT(4'h6))
\dc_bias[2]_i_8
(.I0(\dc_bias_reg_n_0_[2] ),
.I1(\dc_bias[3]_i_15_n_0 ),
.O(\dc_bias[2]_i_8_n_0 ));
LUT6 #(
.INIT(64'h41141414417D7D14))
\dc_bias[2]_i_9__1
(.I0(\dc_bias_reg_n_0_[1] ),
.I1(\dc_bias[3]_i_26_n_0 ),
.I2(\dc_bias[2]_i_11_n_0 ),
.I3(\dc_bias[2]_i_21_n_0 ),
.I4(\dc_bias[3]_i_25_n_0 ),
.I5(\dc_bias_reg_n_0_[0] ),
.O(\dc_bias[2]_i_9__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT5 #(
.INIT(32'h15017F57))
\dc_bias[3]_i_10
(.I0(\dc_bias_reg_n_0_[1] ),
.I1(rgb[0]),
.I2(\dc_bias_reg_n_0_[0] ),
.I3(\dc_bias[0]_i_5_n_0 ),
.I4(\dc_bias[2]_i_13_n_0 ),
.O(\dc_bias[3]_i_10_n_0 ));
LUT6 #(
.INIT(64'h171717FF17FFFFFF))
\dc_bias[3]_i_11
(.I0(rgb[1]),
.I1(rgb[3]),
.I2(rgb[2]),
.I3(rgb[6]),
.I4(rgb[5]),
.I5(rgb[4]),
.O(\dc_bias[3]_i_11_n_0 ));
LUT3 #(
.INIT(8'h96))
\dc_bias[3]_i_12
(.I0(rgb[6]),
.I1(rgb[5]),
.I2(rgb[4]),
.O(\dc_bias[3]_i_12_n_0 ));
LUT6 #(
.INIT(64'h171717E817E8E8E8))
\dc_bias[3]_i_13
(.I0(rgb[1]),
.I1(rgb[3]),
.I2(rgb[2]),
.I3(rgb[6]),
.I4(rgb[5]),
.I5(rgb[4]),
.O(\dc_bias[3]_i_13_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT3 #(
.INIT(8'h96))
\dc_bias[3]_i_14
(.I0(rgb[3]),
.I1(rgb[2]),
.I2(rgb[1]),
.O(\dc_bias[3]_i_14_n_0 ));
LUT6 #(
.INIT(64'hEEE78EEE8EEE888E))
\dc_bias[3]_i_15
(.I0(\dc_bias[2]_i_13_n_0 ),
.I1(\dc_bias[2]_i_12_n_0 ),
.I2(\dc_bias[0]_i_6__0_n_0 ),
.I3(\dc_bias[0]_i_5_n_0 ),
.I4(rgb[0]),
.I5(\dc_bias[3]_i_25_n_0 ),
.O(\dc_bias[3]_i_15_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT5 #(
.INIT(32'hEBBEBEEB))
\dc_bias[3]_i_16__1
(.I0(\dc_bias_reg_n_0_[0] ),
.I1(\dc_bias[0]_i_6__0_n_0 ),
.I2(\dc_bias[0]_i_5_n_0 ),
.I3(rgb[3]),
.I4(rgb[1]),
.O(\dc_bias[3]_i_16__1_n_0 ));
LUT6 #(
.INIT(64'h90F6F66F6F090990))
\dc_bias[3]_i_17__1
(.I0(rgb[3]),
.I1(rgb[1]),
.I2(rgb[0]),
.I3(\dc_bias[0]_i_5_n_0 ),
.I4(\dc_bias[0]_i_6__0_n_0 ),
.I5(\dc_bias[3]_i_26_n_0 ),
.O(\dc_bias[3]_i_17__1_n_0 ));
LUT6 #(
.INIT(64'hEFFF799E799EFFF7))
\dc_bias[3]_i_18
(.I0(\dc_bias[3]_i_25_n_0 ),
.I1(rgb[0]),
.I2(\dc_bias[0]_i_5_n_0 ),
.I3(\dc_bias[0]_i_6__0_n_0 ),
.I4(\dc_bias[2]_i_12_n_0 ),
.I5(\dc_bias[2]_i_13_n_0 ),
.O(\dc_bias[3]_i_18_n_0 ));
LUT6 #(
.INIT(64'hE00E0EE00EE0E00E))
\dc_bias[3]_i_19
(.I0(\dc_bias[3]_i_16__1_n_0 ),
.I1(\dc_bias[3]_i_4_n_0 ),
.I2(\dc_bias[2]_i_10__0_n_0 ),
.I3(\dc_bias[2]_i_11_n_0 ),
.I4(\dc_bias[3]_i_26_n_0 ),
.I5(\dc_bias_reg_n_0_[1] ),
.O(\dc_bias[3]_i_19_n_0 ));
LUT6 #(
.INIT(64'hB8FFB8FFB8FFB800))
\dc_bias[3]_i_2
(.I0(\dc_bias[3]_i_3_n_0 ),
.I1(\dc_bias[3]_i_4_n_0 ),
.I2(\dc_bias[3]_i_5__0_n_0 ),
.I3(\dc_bias[3]_i_6_n_0 ),
.I4(\dc_bias[3]_i_7_n_0 ),
.I5(\dc_bias[3]_i_8_n_0 ),
.O(\dc_bias[3]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT3 #(
.INIT(8'hDF))
\dc_bias[3]_i_20__1
(.I0(\dc_bias_reg_n_0_[0] ),
.I1(\dc_bias[0]_i_2_n_0 ),
.I2(\dc_bias[3]_i_4_n_0 ),
.O(\dc_bias[3]_i_20__1_n_0 ));
LUT6 #(
.INIT(64'hA96A6A5600000000))
\dc_bias[3]_i_21__0
(.I0(\dc_bias[3]_i_26_n_0 ),
.I1(\dc_bias[0]_i_6__0_n_0 ),
.I2(\dc_bias[0]_i_5_n_0 ),
.I3(rgb[0]),
.I4(\dc_bias[3]_i_25_n_0 ),
.I5(\dc_bias_reg_n_0_[1] ),
.O(\dc_bias[3]_i_21__0_n_0 ));
LUT6 #(
.INIT(64'hEFAEAE8AAE8AAE8A))
\dc_bias[3]_i_22
(.I0(\dc_bias_reg_n_0_[2] ),
.I1(\dc_bias[2]_i_15_n_0 ),
.I2(\dc_bias[2]_i_14_n_0 ),
.I3(\dc_bias_reg_n_0_[1] ),
.I4(\dc_bias_reg_n_0_[0] ),
.I5(rgb[0]),
.O(\dc_bias[3]_i_22_n_0 ));
LUT6 #(
.INIT(64'h02BF002B002B0002))
\dc_bias[3]_i_23
(.I0(rgb[7]),
.I1(\dc_bias[2]_i_20_n_0 ),
.I2(\dc_bias[2]_i_19_n_0 ),
.I3(\dc_bias[2]_i_18_n_0 ),
.I4(\dc_bias[2]_i_17_n_0 ),
.I5(\dc_bias[2]_i_16_n_0 ),
.O(\dc_bias[3]_i_23_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF5775D55D))
\dc_bias[3]_i_24
(.I0(\dc_bias[2]_i_18_n_0 ),
.I1(\dc_bias[3]_i_4_n_0 ),
.I2(rgb[0]),
.I3(rgb[1]),
.I4(rgb[2]),
.I5(\dc_bias[3]_i_27_n_0 ),
.O(\dc_bias[3]_i_24_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT3 #(
.INIT(8'h96))
\dc_bias[3]_i_25
(.I0(rgb[3]),
.I1(rgb[1]),
.I2(rgb[0]),
.O(\dc_bias[3]_i_25_n_0 ));
LUT6 #(
.INIT(64'h963CC39669C33C69))
\dc_bias[3]_i_26
(.I0(rgb[3]),
.I1(rgb[1]),
.I2(rgb[0]),
.I3(\dc_bias[3]_i_4_n_0 ),
.I4(rgb[2]),
.I5(\dc_bias[2]_i_13_n_0 ),
.O(\dc_bias[3]_i_26_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFBEBEFF))
\dc_bias[3]_i_27
(.I0(\dc_bias[0]_i_4_n_0 ),
.I1(\encoded[6]_i_2_n_0 ),
.I2(rgb[5]),
.I3(rgb[0]),
.I4(\dc_bias_reg_n_0_[0] ),
.I5(rgb[7]),
.O(\dc_bias[3]_i_27_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT4 #(
.INIT(16'hE718))
\dc_bias[3]_i_3
(.I0(\dc_bias[3]_i_9_n_0 ),
.I1(\dc_bias[3]_i_10_n_0 ),
.I2(\dc_bias_reg_n_0_[2] ),
.I3(p_1_in),
.O(\dc_bias[3]_i_3_n_0 ));
LUT6 #(
.INIT(64'h0022AAAA32EAAAAA))
\dc_bias[3]_i_4
(.I0(\dc_bias[3]_i_11_n_0 ),
.I1(\dc_bias[3]_i_12_n_0 ),
.I2(rgb[0]),
.I3(rgb[7]),
.I4(\dc_bias[3]_i_13_n_0 ),
.I5(\dc_bias[3]_i_14_n_0 ),
.O(\dc_bias[3]_i_4_n_0 ));
LUT6 #(
.INIT(64'h5656566A566A6A6A))
\dc_bias[3]_i_5__0
(.I0(\dc_bias[2]_i_4__0_n_0 ),
.I1(\dc_bias[3]_i_15_n_0 ),
.I2(\dc_bias_reg_n_0_[2] ),
.I3(\dc_bias[3]_i_16__1_n_0 ),
.I4(\dc_bias[3]_i_17__1_n_0 ),
.I5(\dc_bias_reg_n_0_[1] ),
.O(\dc_bias[3]_i_5__0_n_0 ));
LUT5 #(
.INIT(32'h0001FFFF))
\dc_bias[3]_i_6
(.I0(\dc_bias_reg_n_0_[1] ),
.I1(p_1_in),
.I2(\dc_bias_reg_n_0_[2] ),
.I3(\dc_bias_reg_n_0_[0] ),
.I4(\dc_bias[3]_i_18_n_0 ),
.O(\dc_bias[3]_i_6_n_0 ));
LUT6 #(
.INIT(64'h0C0000400040C0CC))
\dc_bias[3]_i_7
(.I0(\dc_bias[3]_i_19_n_0 ),
.I1(\dc_bias[2]_i_4__0_n_0 ),
.I2(\dc_bias[3]_i_20__1_n_0 ),
.I3(\dc_bias[3]_i_21__0_n_0 ),
.I4(\dc_bias_reg_n_0_[2] ),
.I5(\dc_bias[3]_i_15_n_0 ),
.O(\dc_bias[3]_i_7_n_0 ));
LUT6 #(
.INIT(64'h0000000096969996))
\dc_bias[3]_i_8
(.I0(p_1_in),
.I1(\dc_bias[3]_i_22_n_0 ),
.I2(\dc_bias[3]_i_23_n_0 ),
.I3(\dc_bias[3]_i_24_n_0 ),
.I4(\dc_bias[2]_i_5_n_0 ),
.I5(\dc_bias[2]_i_4__0_n_0 ),
.O(\dc_bias[3]_i_8_n_0 ));
LUT3 #(
.INIT(8'h17))
\dc_bias[3]_i_9
(.I0(\dc_bias[1]_i_6_n_0 ),
.I1(\dc_bias[2]_i_12_n_0 ),
.I2(\dc_bias[1]_i_7_n_0 ),
.O(\dc_bias[3]_i_9_n_0 ));
FDRE #(
.INIT(1'b0))
\dc_bias_reg[0]
(.C(clk_25),
.CE(1'b1),
.D(\dc_bias[0]_i_1_n_0 ),
.Q(\dc_bias_reg_n_0_[0] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\dc_bias_reg[1]
(.C(clk_25),
.CE(1'b1),
.D(\dc_bias_reg[1]_i_1_n_0 ),
.Q(\dc_bias_reg_n_0_[1] ),
.R(SR));
MUXF7 \dc_bias_reg[1]_i_1
(.I0(\dc_bias[1]_i_2_n_0 ),
.I1(\dc_bias[1]_i_3_n_0 ),
.O(\dc_bias_reg[1]_i_1_n_0 ),
.S(\dc_bias[3]_i_6_n_0 ));
FDRE #(
.INIT(1'b0))
\dc_bias_reg[2]
(.C(clk_25),
.CE(1'b1),
.D(\dc_bias[2]_i_1_n_0 ),
.Q(\dc_bias_reg_n_0_[2] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\dc_bias_reg[3]
(.C(clk_25),
.CE(1'b1),
.D(\dc_bias[3]_i_2_n_0 ),
.Q(p_1_in),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT3 #(
.INIT(8'h28))
\encoded[0]_i_1
(.I0(active),
.I1(rgb[0]),
.I2(\encoded[9]_i_2_n_0 ),
.O(encoded[0]));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT4 #(
.INIT(16'h8228))
\encoded[1]_i_1
(.I0(active),
.I1(\encoded[7]_i_3_n_0 ),
.I2(rgb[1]),
.I3(rgb[0]),
.O(encoded[1]));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT5 #(
.INIT(32'h7DD7D77D))
\encoded[2]_i_1
(.I0(active),
.I1(rgb[0]),
.I2(rgb[1]),
.I3(rgb[2]),
.I4(\encoded[9]_i_2_n_0 ),
.O(encoded[2]));
LUT6 #(
.INIT(64'h8228288228828228))
\encoded[3]_i_1
(.I0(active),
.I1(rgb[2]),
.I2(rgb[1]),
.I3(rgb[0]),
.I4(rgb[3]),
.I5(\encoded[7]_i_3_n_0 ),
.O(encoded[3]));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT4 #(
.INIT(16'h7DD7))
\encoded[4]_i_1
(.I0(active),
.I1(\encoded[6]_i_2_n_0 ),
.I2(rgb[4]),
.I3(\encoded[9]_i_2_n_0 ),
.O(encoded[4]));
LUT5 #(
.INIT(32'h82282882))
\encoded[5]_i_1
(.I0(active),
.I1(rgb[4]),
.I2(rgb[5]),
.I3(\encoded[6]_i_2_n_0 ),
.I4(\encoded[7]_i_3_n_0 ),
.O(encoded[5]));
LUT6 #(
.INIT(64'h7DD7D77DD77D7DD7))
\encoded[6]_i_1
(.I0(active),
.I1(rgb[6]),
.I2(rgb[5]),
.I3(rgb[4]),
.I4(\encoded[6]_i_2_n_0 ),
.I5(\encoded[9]_i_2_n_0 ),
.O(encoded[6]));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT4 #(
.INIT(16'h9669))
\encoded[6]_i_2
(.I0(rgb[3]),
.I1(rgb[0]),
.I2(rgb[1]),
.I3(rgb[2]),
.O(\encoded[6]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT4 #(
.INIT(16'h8228))
\encoded[7]_i_1
(.I0(active),
.I1(\encoded[7]_i_2__0_n_0 ),
.I2(rgb[7]),
.I3(\encoded[7]_i_3_n_0 ),
.O(encoded[7]));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT4 #(
.INIT(16'h9669))
\encoded[7]_i_2__0
(.I0(\encoded[6]_i_2_n_0 ),
.I1(rgb[4]),
.I2(rgb[5]),
.I3(rgb[6]),
.O(\encoded[7]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT3 #(
.INIT(8'h41))
\encoded[7]_i_3
(.I0(\dc_bias[3]_i_6_n_0 ),
.I1(\dc_bias[2]_i_4__0_n_0 ),
.I2(\dc_bias[3]_i_4_n_0 ),
.O(\encoded[7]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT2 #(
.INIT(4'hB))
\encoded[8]_i_1
(.I0(\dc_bias[3]_i_4_n_0 ),
.I1(active),
.O(\encoded[8]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT2 #(
.INIT(4'hB))
\encoded[9]_i_1__0
(.I0(\encoded[9]_i_2_n_0 ),
.I1(active),
.O(\encoded[9]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT3 #(
.INIT(8'h74))
\encoded[9]_i_2
(.I0(\dc_bias[3]_i_4_n_0 ),
.I1(\dc_bias[3]_i_6_n_0 ),
.I2(\dc_bias[2]_i_4__0_n_0 ),
.O(\encoded[9]_i_2_n_0 ));
FDRE \encoded_reg[0]
(.C(clk_25),
.CE(1'b1),
.D(encoded[0]),
.Q(\encoded_reg_n_0_[0] ),
.R(1'b0));
FDRE \encoded_reg[1]
(.C(clk_25),
.CE(1'b1),
.D(encoded[1]),
.Q(\encoded_reg_n_0_[1] ),
.R(1'b0));
FDRE \encoded_reg[2]
(.C(clk_25),
.CE(1'b1),
.D(encoded[2]),
.Q(\encoded_reg_n_0_[2] ),
.R(1'b0));
FDRE \encoded_reg[3]
(.C(clk_25),
.CE(1'b1),
.D(encoded[3]),
.Q(\encoded_reg_n_0_[3] ),
.R(1'b0));
FDRE \encoded_reg[4]
(.C(clk_25),
.CE(1'b1),
.D(encoded[4]),
.Q(\encoded_reg_n_0_[4] ),
.R(1'b0));
FDRE \encoded_reg[5]
(.C(clk_25),
.CE(1'b1),
.D(encoded[5]),
.Q(\encoded_reg_n_0_[5] ),
.R(1'b0));
FDRE \encoded_reg[6]
(.C(clk_25),
.CE(1'b1),
.D(encoded[6]),
.Q(\encoded_reg_n_0_[6] ),
.R(1'b0));
FDRE \encoded_reg[7]
(.C(clk_25),
.CE(1'b1),
.D(encoded[7]),
.Q(\encoded_reg_n_0_[7] ),
.R(1'b0));
FDRE \encoded_reg[8]
(.C(clk_25),
.CE(1'b1),
.D(\encoded[8]_i_1_n_0 ),
.Q(Q[0]),
.R(1'b0));
FDRE \encoded_reg[9]
(.C(clk_25),
.CE(1'b1),
.D(\encoded[9]_i_1__0_n_0 ),
.Q(Q[1]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT3 #(
.INIT(8'hB8))
\shift_red[0]_i_1
(.I0(data1[0]),
.I1(\shift_clock_reg[5] ),
.I2(\encoded_reg_n_0_[0] ),
.O(D[0]));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT3 #(
.INIT(8'hB8))
\shift_red[1]_i_1
(.I0(data1[1]),
.I1(\shift_clock_reg[5] ),
.I2(\encoded_reg_n_0_[1] ),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT3 #(
.INIT(8'hB8))
\shift_red[2]_i_1
(.I0(data1[2]),
.I1(\shift_clock_reg[5] ),
.I2(\encoded_reg_n_0_[2] ),
.O(D[2]));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT3 #(
.INIT(8'hB8))
\shift_red[3]_i_1
(.I0(data1[3]),
.I1(\shift_clock_reg[5] ),
.I2(\encoded_reg_n_0_[3] ),
.O(D[3]));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT3 #(
.INIT(8'hB8))
\shift_red[4]_i_1
(.I0(data1[4]),
.I1(\shift_clock_reg[5] ),
.I2(\encoded_reg_n_0_[4] ),
.O(D[4]));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT3 #(
.INIT(8'hB8))
\shift_red[5]_i_1
(.I0(data1[5]),
.I1(\shift_clock_reg[5] ),
.I2(\encoded_reg_n_0_[5] ),
.O(D[5]));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT3 #(
.INIT(8'hB8))
\shift_red[6]_i_1
(.I0(data1[6]),
.I1(\shift_clock_reg[5] ),
.I2(\encoded_reg_n_0_[6] ),
.O(D[6]));
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT3 #(
.INIT(8'hB8))
\shift_red[7]_i_1
(.I0(data1[7]),
.I1(\shift_clock_reg[5] ),
.I2(\encoded_reg_n_0_[7] ),
.O(D[7]));
endmodule
(* ORIG_REF_NAME = "dvid" *)
module system_zybo_hdmi_0_0_dvid
(red_s,
green_s,
blue_s,
clock_s,
clk_125,
rgb,
active,
hsync,
vsync,
clk_25);
output red_s;
output green_s;
output blue_s;
output clock_s;
input clk_125;
input [23:0]rgb;
input active;
input hsync;
input vsync;
input clk_25;
wire D0;
wire D1;
wire TMDS_encoder_BLUE_n_0;
wire TMDS_encoder_BLUE_n_10;
wire TMDS_encoder_BLUE_n_9;
wire TMDS_encoder_GREEN_n_8;
wire TMDS_encoder_GREEN_n_9;
wire TMDS_encoder_RED_n_8;
wire TMDS_encoder_RED_n_9;
wire active;
wire blue_s;
wire clk_125;
wire clk_25;
wire clk_dvin;
wire clock_s;
wire [7:0]data1;
wire green_s;
wire hsync;
wire red_s;
wire [23:0]rgb;
wire [9:2]shift_blue;
wire [7:0]shift_blue_0;
wire \shift_blue_reg_n_0_[0] ;
wire \shift_blue_reg_n_0_[1] ;
wire [1:0]shift_clock;
wire \shift_clock_reg_n_0_[2] ;
wire \shift_clock_reg_n_0_[3] ;
wire \shift_clock_reg_n_0_[4] ;
wire \shift_clock_reg_n_0_[5] ;
wire \shift_clock_reg_n_0_[6] ;
wire \shift_clock_reg_n_0_[7] ;
wire \shift_clock_reg_n_0_[8] ;
wire \shift_clock_reg_n_0_[9] ;
wire [9:2]shift_green;
wire [7:0]shift_green_1;
wire \shift_green_reg_n_0_[0] ;
wire \shift_green_reg_n_0_[1] ;
wire [7:0]shift_red;
wire \shift_red[9]_i_1_n_0 ;
wire \shift_red[9]_i_2_n_0 ;
wire vsync;
wire NLW_ODDR2_BLUE_R_UNCONNECTED;
wire NLW_ODDR2_BLUE_S_UNCONNECTED;
wire NLW_ODDR2_CLK_R_UNCONNECTED;
wire NLW_ODDR2_CLK_S_UNCONNECTED;
wire NLW_ODDR2_GREEN_R_UNCONNECTED;
wire NLW_ODDR2_GREEN_S_UNCONNECTED;
wire NLW_ODDR2_RED_R_UNCONNECTED;
wire NLW_ODDR2_RED_S_UNCONNECTED;
(* XILINX_LEGACY_PRIM = "ODDR2" *)
(* XILINX_TRANSFORM_PINMAP = "D0:D1 D1:D2 C0:C" *)
(* __SRVAL = "TRUE" *)
(* box_type = "PRIMITIVE" *)
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE"),
.INIT(1'b0),
.SRTYPE("ASYNC"))
ODDR2_BLUE
(.C(clk_125),
.CE(1'b1),
.D1(\shift_blue_reg_n_0_[0] ),
.D2(\shift_blue_reg_n_0_[1] ),
.Q(blue_s),
.R(NLW_ODDR2_BLUE_R_UNCONNECTED),
.S(NLW_ODDR2_BLUE_S_UNCONNECTED));
(* XILINX_LEGACY_PRIM = "ODDR2" *)
(* XILINX_TRANSFORM_PINMAP = "D0:D1 D1:D2 C0:C" *)
(* __SRVAL = "TRUE" *)
(* box_type = "PRIMITIVE" *)
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE"),
.INIT(1'b0),
.SRTYPE("ASYNC"))
ODDR2_CLK
(.C(clk_125),
.CE(1'b1),
.D1(shift_clock[0]),
.D2(shift_clock[1]),
.Q(clock_s),
.R(NLW_ODDR2_CLK_R_UNCONNECTED),
.S(NLW_ODDR2_CLK_S_UNCONNECTED));
(* XILINX_LEGACY_PRIM = "ODDR2" *)
(* XILINX_TRANSFORM_PINMAP = "D0:D1 D1:D2 C0:C" *)
(* __SRVAL = "TRUE" *)
(* box_type = "PRIMITIVE" *)
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE"),
.INIT(1'b0),
.SRTYPE("ASYNC"))
ODDR2_GREEN
(.C(clk_125),
.CE(1'b1),
.D1(\shift_green_reg_n_0_[0] ),
.D2(\shift_green_reg_n_0_[1] ),
.Q(green_s),
.R(NLW_ODDR2_GREEN_R_UNCONNECTED),
.S(NLW_ODDR2_GREEN_S_UNCONNECTED));
(* XILINX_LEGACY_PRIM = "ODDR2" *)
(* XILINX_TRANSFORM_PINMAP = "D0:D1 D1:D2 C0:C" *)
(* __SRVAL = "TRUE" *)
(* box_type = "PRIMITIVE" *)
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE"),
.INIT(1'b0),
.SRTYPE("ASYNC"))
ODDR2_RED
(.C(clk_125),
.CE(1'b1),
.D1(D0),
.D2(D1),
.Q(red_s),
.R(NLW_ODDR2_RED_R_UNCONNECTED),
.S(NLW_ODDR2_RED_S_UNCONNECTED));
LUT1 #(
.INIT(2'h1))
ODDR2_RED_i_1
(.I0(clk_125),
.O(clk_dvin));
system_zybo_hdmi_0_0_TMDS_encoder TMDS_encoder_BLUE
(.D(shift_blue_0),
.Q({TMDS_encoder_BLUE_n_9,TMDS_encoder_BLUE_n_10}),
.SR(TMDS_encoder_BLUE_n_0),
.active(active),
.clk_25(clk_25),
.hsync(hsync),
.rgb(rgb[7:0]),
.shift_blue(shift_blue),
.\shift_clock_reg[5] (\shift_red[9]_i_1_n_0 ),
.vsync(vsync));
system_zybo_hdmi_0_0_TMDS_encoder_0 TMDS_encoder_GREEN
(.D(shift_green_1),
.Q({TMDS_encoder_GREEN_n_8,TMDS_encoder_GREEN_n_9}),
.SR(TMDS_encoder_BLUE_n_0),
.active(active),
.clk_25(clk_25),
.rgb(rgb[15:8]),
.\shift_clock_reg[5] (\shift_red[9]_i_1_n_0 ),
.shift_green(shift_green));
system_zybo_hdmi_0_0_TMDS_encoder_1 TMDS_encoder_RED
(.D(shift_red),
.Q({TMDS_encoder_RED_n_8,TMDS_encoder_RED_n_9}),
.SR(TMDS_encoder_BLUE_n_0),
.active(active),
.clk_25(clk_25),
.data1(data1),
.rgb(rgb[23:16]),
.\shift_clock_reg[5] (\shift_red[9]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\shift_blue_reg[0]
(.C(clk_125),
.CE(1'b1),
.D(shift_blue_0[0]),
.Q(\shift_blue_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shift_blue_reg[1]
(.C(clk_125),
.CE(1'b1),
.D(shift_blue_0[1]),
.Q(\shift_blue_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shift_blue_reg[2]
(.C(clk_125),
.CE(1'b1),
.D(shift_blue_0[2]),
.Q(shift_blue[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shift_blue_reg[3]
(.C(clk_125),
.CE(1'b1),
.D(shift_blue_0[3]),
.Q(shift_blue[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shift_blue_reg[4]
(.C(clk_125),
.CE(1'b1),
.D(shift_blue_0[4]),
.Q(shift_blue[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shift_blue_reg[5]
(.C(clk_125),
.CE(1'b1),
.D(shift_blue_0[5]),
.Q(shift_blue[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shift_blue_reg[6]
(.C(clk_125),
.CE(1'b1),
.D(shift_blue_0[6]),
.Q(shift_blue[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shift_blue_reg[7]
(.C(clk_125),
.CE(1'b1),
.D(shift_blue_0[7]),
.Q(shift_blue[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shift_blue_reg[8]
(.C(clk_125),
.CE(1'b1),
.D(TMDS_encoder_BLUE_n_10),
.Q(shift_blue[8]),
.R(\shift_red[9]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\shift_blue_reg[9]
(.C(clk_125),
.CE(1'b1),
.D(TMDS_encoder_BLUE_n_9),
.Q(shift_blue[9]),
.R(\shift_red[9]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\shift_clock_reg[0]
(.C(clk_125),
.CE(1'b1),
.D(\shift_clock_reg_n_0_[2] ),
.Q(shift_clock[0]),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\shift_clock_reg[1]
(.C(clk_125),
.CE(1'b1),
.D(\shift_clock_reg_n_0_[3] ),
.Q(shift_clock[1]),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\shift_clock_reg[2]
(.C(clk_125),
.CE(1'b1),
.D(\shift_clock_reg_n_0_[4] ),
.Q(\shift_clock_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\shift_clock_reg[3]
(.C(clk_125),
.CE(1'b1),
.D(\shift_clock_reg_n_0_[5] ),
.Q(\shift_clock_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\shift_clock_reg[4]
(.C(clk_125),
.CE(1'b1),
.D(\shift_clock_reg_n_0_[6] ),
.Q(\shift_clock_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shift_clock_reg[5]
(.C(clk_125),
.CE(1'b1),
.D(\shift_clock_reg_n_0_[7] ),
.Q(\shift_clock_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shift_clock_reg[6]
(.C(clk_125),
.CE(1'b1),
.D(\shift_clock_reg_n_0_[8] ),
.Q(\shift_clock_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shift_clock_reg[7]
(.C(clk_125),
.CE(1'b1),
.D(\shift_clock_reg_n_0_[9] ),
.Q(\shift_clock_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shift_clock_reg[8]
(.C(clk_125),
.CE(1'b1),
.D(shift_clock[0]),
.Q(\shift_clock_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shift_clock_reg[9]
(.C(clk_125),
.CE(1'b1),
.D(shift_clock[1]),
.Q(\shift_clock_reg_n_0_[9] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shift_green_reg[0]
(.C(clk_125),
.CE(1'b1),
.D(shift_green_1[0]),
.Q(\shift_green_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shift_green_reg[1]
(.C(clk_125),
.CE(1'b1),
.D(shift_green_1[1]),
.Q(\shift_green_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shift_green_reg[2]
(.C(clk_125),
.CE(1'b1),
.D(shift_green_1[2]),
.Q(shift_green[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shift_green_reg[3]
(.C(clk_125),
.CE(1'b1),
.D(shift_green_1[3]),
.Q(shift_green[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shift_green_reg[4]
(.C(clk_125),
.CE(1'b1),
.D(shift_green_1[4]),
.Q(shift_green[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shift_green_reg[5]
(.C(clk_125),
.CE(1'b1),
.D(shift_green_1[5]),
.Q(shift_green[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shift_green_reg[6]
(.C(clk_125),
.CE(1'b1),
.D(shift_green_1[6]),
.Q(shift_green[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shift_green_reg[7]
(.C(clk_125),
.CE(1'b1),
.D(shift_green_1[7]),
.Q(shift_green[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shift_green_reg[8]
(.C(clk_125),
.CE(1'b1),
.D(TMDS_encoder_GREEN_n_9),
.Q(shift_green[8]),
.R(\shift_red[9]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\shift_green_reg[9]
(.C(clk_125),
.CE(1'b1),
.D(TMDS_encoder_GREEN_n_8),
.Q(shift_green[9]),
.R(\shift_red[9]_i_1_n_0 ));
LUT5 #(
.INIT(32'hEFFFFFFF))
\shift_red[9]_i_1
(.I0(\shift_red[9]_i_2_n_0 ),
.I1(\shift_clock_reg_n_0_[5] ),
.I2(\shift_clock_reg_n_0_[4] ),
.I3(\shift_clock_reg_n_0_[2] ),
.I4(\shift_clock_reg_n_0_[3] ),
.O(\shift_red[9]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFEFFFFFFFFFFFF))
\shift_red[9]_i_2
(.I0(\shift_clock_reg_n_0_[8] ),
.I1(\shift_clock_reg_n_0_[9] ),
.I2(\shift_clock_reg_n_0_[6] ),
.I3(\shift_clock_reg_n_0_[7] ),
.I4(shift_clock[1]),
.I5(shift_clock[0]),
.O(\shift_red[9]_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\shift_red_reg[0]
(.C(clk_125),
.CE(1'b1),
.D(shift_red[0]),
.Q(D0),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shift_red_reg[1]
(.C(clk_125),
.CE(1'b1),
.D(shift_red[1]),
.Q(D1),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shift_red_reg[2]
(.C(clk_125),
.CE(1'b1),
.D(shift_red[2]),
.Q(data1[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shift_red_reg[3]
(.C(clk_125),
.CE(1'b1),
.D(shift_red[3]),
.Q(data1[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shift_red_reg[4]
(.C(clk_125),
.CE(1'b1),
.D(shift_red[4]),
.Q(data1[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shift_red_reg[5]
(.C(clk_125),
.CE(1'b1),
.D(shift_red[5]),
.Q(data1[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shift_red_reg[6]
(.C(clk_125),
.CE(1'b1),
.D(shift_red[6]),
.Q(data1[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shift_red_reg[7]
(.C(clk_125),
.CE(1'b1),
.D(shift_red[7]),
.Q(data1[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shift_red_reg[8]
(.C(clk_125),
.CE(1'b1),
.D(TMDS_encoder_RED_n_9),
.Q(data1[6]),
.R(\shift_red[9]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\shift_red_reg[9]
(.C(clk_125),
.CE(1'b1),
.D(TMDS_encoder_RED_n_8),
.Q(data1[7]),
.R(\shift_red[9]_i_1_n_0 ));
endmodule
(* ORIG_REF_NAME = "zybo_hdmi" *)
module system_zybo_hdmi_0_0_zybo_hdmi
(tmds,
tmdsb,
rgb,
active,
hsync,
vsync,
clk_125,
clk_25);
output [3:0]tmds;
output [3:0]tmdsb;
input [23:0]rgb;
input active;
input hsync;
input vsync;
input clk_125;
input clk_25;
wire active;
wire blue_s;
wire clk_125;
wire clk_25;
wire clock_s;
wire green_s;
wire hsync;
wire red_s;
wire [23:0]rgb;
wire [3:0]tmds;
wire [3:0]tmdsb;
wire vsync;
system_zybo_hdmi_0_0_dvid DVID
(.active(active),
.blue_s(blue_s),
.clk_125(clk_125),
.clk_25(clk_25),
.clock_s(clock_s),
.green_s(green_s),
.hsync(hsync),
.red_s(red_s),
.rgb(rgb),
.vsync(vsync));
(* CAPACITANCE = "DONT_CARE" *)
(* XILINX_LEGACY_PRIM = "OBUFDS" *)
(* box_type = "PRIMITIVE" *)
OBUFDS #(
.IOSTANDARD("DEFAULT"))
OBUFDS_blue
(.I(blue_s),
.O(tmds[0]),
.OB(tmdsb[0]));
(* CAPACITANCE = "DONT_CARE" *)
(* XILINX_LEGACY_PRIM = "OBUFDS" *)
(* box_type = "PRIMITIVE" *)
OBUFDS #(
.IOSTANDARD("DEFAULT"))
OBUFDS_clock
(.I(clock_s),
.O(tmds[3]),
.OB(tmdsb[3]));
(* CAPACITANCE = "DONT_CARE" *)
(* XILINX_LEGACY_PRIM = "OBUFDS" *)
(* box_type = "PRIMITIVE" *)
OBUFDS #(
.IOSTANDARD("DEFAULT"))
OBUFDS_green
(.I(red_s),
.O(tmds[2]),
.OB(tmdsb[2]));
(* CAPACITANCE = "DONT_CARE" *)
(* XILINX_LEGACY_PRIM = "OBUFDS" *)
(* box_type = "PRIMITIVE" *)
OBUFDS #(
.IOSTANDARD("DEFAULT"))
OBUFDS_red
(.I(green_s),
.O(tmds[1]),
.OB(tmdsb[1]));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// generated by gen_VerilogEHR.py using VerilogEHR.mako
// Copyright (c) 2019 Massachusetts Institute of Technology
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies
// of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
// SOFTWARE.
module EHR_7 (
CLK,
RST_N,
read_0,
write_0,
EN_write_0,
read_1,
write_1,
EN_write_1,
read_2,
write_2,
EN_write_2,
read_3,
write_3,
EN_write_3,
read_4,
write_4,
EN_write_4,
read_5,
write_5,
EN_write_5,
read_6,
write_6,
EN_write_6
);
parameter DATA_SZ = 1;
parameter RESET_VAL = 0;
input CLK;
input RST_N;
output [DATA_SZ-1:0] read_0;
input [DATA_SZ-1:0] write_0;
input EN_write_0;
output [DATA_SZ-1:0] read_1;
input [DATA_SZ-1:0] write_1;
input EN_write_1;
output [DATA_SZ-1:0] read_2;
input [DATA_SZ-1:0] write_2;
input EN_write_2;
output [DATA_SZ-1:0] read_3;
input [DATA_SZ-1:0] write_3;
input EN_write_3;
output [DATA_SZ-1:0] read_4;
input [DATA_SZ-1:0] write_4;
input EN_write_4;
output [DATA_SZ-1:0] read_5;
input [DATA_SZ-1:0] write_5;
input EN_write_5;
output [DATA_SZ-1:0] read_6;
input [DATA_SZ-1:0] write_6;
input EN_write_6;
reg [DATA_SZ-1:0] r;
wire [DATA_SZ-1:0] wire_0;
wire [DATA_SZ-1:0] wire_1;
wire [DATA_SZ-1:0] wire_2;
wire [DATA_SZ-1:0] wire_3;
wire [DATA_SZ-1:0] wire_4;
wire [DATA_SZ-1:0] wire_5;
wire [DATA_SZ-1:0] wire_6;
wire [DATA_SZ-1:0] wire_7;
assign wire_0 = r;
assign wire_1 = EN_write_0 ? write_0 : wire_0;
assign wire_2 = EN_write_1 ? write_1 : wire_1;
assign wire_3 = EN_write_2 ? write_2 : wire_2;
assign wire_4 = EN_write_3 ? write_3 : wire_3;
assign wire_5 = EN_write_4 ? write_4 : wire_4;
assign wire_6 = EN_write_5 ? write_5 : wire_5;
assign wire_7 = EN_write_6 ? write_6 : wire_6;
assign read_0 = wire_0;
assign read_1 = wire_1;
assign read_2 = wire_2;
assign read_3 = wire_3;
assign read_4 = wire_4;
assign read_5 = wire_5;
assign read_6 = wire_6;
always @(posedge CLK) begin
if (RST_N == 0) begin
r <= RESET_VAL;
end else begin
r <= wire_7;
end
end
endmodule
|
// (c) Copyright 2011-2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// axis to vector
// A generic module to unmerge all axis 'data' signals from payload.
// This is strictly wires, so no clk, reset, aclken, valid/ready are required.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// axis_infrastructure_v1_0_util_vector2axis
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_vdma_v6_2_8_axis_infrastructure_v1_0_util_vector2axis #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter integer C_TDATA_WIDTH = 32,
parameter integer C_TID_WIDTH = 1,
parameter integer C_TDEST_WIDTH = 1,
parameter integer C_TUSER_WIDTH = 1,
parameter integer C_TPAYLOAD_WIDTH = 44,
parameter [31:0] C_SIGNAL_SET = 32'hFF
// C_AXIS_SIGNAL_SET: each bit if enabled specifies which axis optional signals are present
// [0] => TREADY present
// [1] => TDATA present
// [2] => TSTRB present, TDATA must be present
// [3] => TKEEP present, TDATA must be present
// [4] => TLAST present
// [5] => TID present
// [6] => TDEST present
// [7] => TUSER present
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// outputs
input wire [C_TPAYLOAD_WIDTH-1:0] TPAYLOAD,
// inputs
output wire [C_TDATA_WIDTH-1:0] TDATA,
output wire [C_TDATA_WIDTH/8-1:0] TSTRB,
output wire [C_TDATA_WIDTH/8-1:0] TKEEP,
output wire TLAST,
output wire [C_TID_WIDTH-1:0] TID,
output wire [C_TDEST_WIDTH-1:0] TDEST,
output wire [C_TUSER_WIDTH-1:0] TUSER
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
`include "axi_vdma_v6_2_8_axis_infrastructure_v1_0_axis_infrastructure.vh"
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
localparam P_TDATA_INDX = f_get_tdata_indx(C_TDATA_WIDTH, C_TID_WIDTH,
C_TDEST_WIDTH, C_TUSER_WIDTH,
C_SIGNAL_SET);
localparam P_TSTRB_INDX = f_get_tstrb_indx(C_TDATA_WIDTH, C_TID_WIDTH,
C_TDEST_WIDTH, C_TUSER_WIDTH,
C_SIGNAL_SET);
localparam P_TKEEP_INDX = f_get_tkeep_indx(C_TDATA_WIDTH, C_TID_WIDTH,
C_TDEST_WIDTH, C_TUSER_WIDTH,
C_SIGNAL_SET);
localparam P_TLAST_INDX = f_get_tlast_indx(C_TDATA_WIDTH, C_TID_WIDTH,
C_TDEST_WIDTH, C_TUSER_WIDTH,
C_SIGNAL_SET);
localparam P_TID_INDX = f_get_tid_indx (C_TDATA_WIDTH, C_TID_WIDTH,
C_TDEST_WIDTH, C_TUSER_WIDTH,
C_SIGNAL_SET);
localparam P_TDEST_INDX = f_get_tdest_indx(C_TDATA_WIDTH, C_TID_WIDTH,
C_TDEST_WIDTH, C_TUSER_WIDTH,
C_SIGNAL_SET);
localparam P_TUSER_INDX = f_get_tuser_indx(C_TDATA_WIDTH, C_TID_WIDTH,
C_TDEST_WIDTH, C_TUSER_WIDTH,
C_SIGNAL_SET);
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
generate
if (C_SIGNAL_SET[G_INDX_SS_TDATA]) begin : gen_tdata
assign TDATA = TPAYLOAD[P_TDATA_INDX+:C_TDATA_WIDTH] ;
end
if (C_SIGNAL_SET[G_INDX_SS_TSTRB]) begin : gen_tstrb
assign TSTRB = TPAYLOAD[P_TSTRB_INDX+:C_TDATA_WIDTH/8];
end
if (C_SIGNAL_SET[G_INDX_SS_TKEEP]) begin : gen_tkeep
assign TKEEP = TPAYLOAD[P_TKEEP_INDX+:C_TDATA_WIDTH/8];
end
if (C_SIGNAL_SET[G_INDX_SS_TLAST]) begin : gen_tlast
assign TLAST = TPAYLOAD[P_TLAST_INDX+:1] ;
end
if (C_SIGNAL_SET[G_INDX_SS_TID]) begin : gen_tid
assign TID = TPAYLOAD[P_TID_INDX+:C_TID_WIDTH] ;
end
if (C_SIGNAL_SET[G_INDX_SS_TDEST]) begin : gen_tdest
assign TDEST = TPAYLOAD[P_TDEST_INDX+:C_TDEST_WIDTH] ;
end
if (C_SIGNAL_SET[G_INDX_SS_TUSER]) begin : gen_tuser
assign TUSER = TPAYLOAD[P_TUSER_INDX+:C_TUSER_WIDTH] ;
end
endgenerate
endmodule
`default_nettype wire
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_fp_custom_add_core(clock, resetn, dataa, datab, result, valid_in, valid_out, stall_in, stall_out, enable);
input clock, resetn;
input valid_in, stall_in;
output valid_out, stall_out;
input enable;
input [31:0] dataa;
input [31:0] datab;
output [31:0] result;
parameter HIGH_CAPACITY = 1;
parameter FLUSH_DENORMS = 0;
parameter HIGH_LATENCY = 1;
parameter ROUNDING_MODE = 0;
parameter FINITE_MATH_ONLY = 0;
parameter REMOVE_STICKY = 0;
// Total Latency = 12-7.
wire [26:0] input_a_mantissa;
wire [26:0] input_b_mantissa;
wire input_a_sign, input_b_sign;
wire [8:0] input_a_exponent;
wire [8:0] input_b_exponent;
wire [26:0] left_mantissa;
wire [26:0] right_mantissa;
wire left_sign, right_sign, align_valid_out;
wire [8:0] align_exponent;
wire stall_align;
wire conversion_valid, alignment_stall;
acl_fp_convert_to_internal left(
.clock(clock),
.resetn(resetn),
.data(dataa),
.mantissa(input_a_mantissa),
.exponent(input_a_exponent),
.sign(input_a_sign),
.valid_in(valid_in),
.valid_out(conversion_valid),
.stall_in(alignment_stall),
.stall_out(stall_out),
.enable(enable));
defparam left.HIGH_CAPACITY = HIGH_CAPACITY;
defparam left.FLUSH_DENORMS = FLUSH_DENORMS;
defparam left.FINITE_MATH_ONLY = FINITE_MATH_ONLY;
acl_fp_convert_to_internal right(
.clock(clock),
.resetn(resetn),
.data(datab),
.mantissa(input_b_mantissa),
.exponent(input_b_exponent),
.sign(input_b_sign),
.valid_in(valid_in),
.valid_out(),
.stall_in(alignment_stall),
.stall_out(),
.enable(enable));
defparam right.HIGH_CAPACITY = HIGH_CAPACITY;
defparam right.FLUSH_DENORMS = FLUSH_DENORMS;
defparam right.FINITE_MATH_ONLY = FINITE_MATH_ONLY;
acl_fp_custom_align alignment(
.clock(clock),
.resetn(resetn),
.input_a_mantissa(input_a_mantissa),
.input_a_exponent(input_a_exponent),
.input_a_sign(input_a_sign),
.input_b_mantissa(input_b_mantissa),
.input_b_exponent(input_b_exponent),
.input_b_sign(input_b_sign),
.left_mantissa(left_mantissa),
.left_exponent(align_exponent),
.left_sign(left_sign),
.right_mantissa(right_mantissa),
.right_exponent(),
.right_sign(right_sign),
.valid_in(conversion_valid),
.valid_out(align_valid_out),
.stall_in(stall_align),
.stall_out(alignment_stall),
.enable(enable));
defparam alignment.HIGH_CAPACITY = HIGH_CAPACITY;
defparam alignment.FLUSH_DENORMS = FLUSH_DENORMS;
defparam alignment.HIGH_LATENCY = HIGH_LATENCY;
defparam alignment.ROUNDING_MODE = ROUNDING_MODE;
defparam alignment.FINITE_MATH_ONLY = FINITE_MATH_ONLY;
defparam alignment.REMOVE_STICKY = REMOVE_STICKY;
wire [27:0] resulting_mantissa;
wire [8:0] resulting_exponent;
wire resulting_sign;
wire valid_sum;
wire stall_sum;
acl_fp_custom_add_op op(
.clock(clock),
.resetn(resetn),
.left_mantissa(left_mantissa),
.right_mantissa(right_mantissa),
.left_sign(left_sign),
.right_sign(right_sign),
.common_exponent(align_exponent),
.resulting_mantissa(resulting_mantissa),
.resulting_exponent(resulting_exponent),
.resulting_sign(resulting_sign),
.valid_in(align_valid_out),
.valid_out(valid_sum),
.stall_in(stall_sum),
.stall_out(stall_align),
.enable(enable));
defparam op.HIGH_CAPACITY = HIGH_CAPACITY;
wire stall_from_norm;
wire [27:0] new_mantissa;
wire [8:0] new_exponent;
wire new_sign, new_valid;
generate
if ((HIGH_CAPACITY==1) && (HIGH_LATENCY==1))
begin
// Staging register.
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [27:0] mantissa_str;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [7:0] exponent_str;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg sign_str;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg staging_valid;
always@(posedge clock or negedge resetn)
begin
if (~resetn)
begin
staging_valid <= 1'b0;
mantissa_str <= 28'bxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
exponent_str <= 8'bxxxxxxxx;
sign_str <= 1'bx;
end
else
begin
if (~stall_from_norm)
staging_valid <= 1'b0;
else if (~staging_valid)
staging_valid <= valid_sum;
if (~staging_valid)
begin
mantissa_str <= resulting_mantissa;
exponent_str <= resulting_exponent;
sign_str <= resulting_sign;
end
end
end
assign new_mantissa = staging_valid ? mantissa_str : resulting_mantissa;
assign new_exponent = staging_valid ? exponent_str : resulting_exponent;
assign new_sign = staging_valid ? sign_str : resulting_sign;
assign new_valid = valid_sum | staging_valid;
assign stall_sum = staging_valid;
end
else
begin
assign new_mantissa = resulting_mantissa;
assign new_exponent = resulting_exponent;
assign new_sign = resulting_sign;
assign new_valid = valid_sum;
assign stall_sum = stall_from_norm;
end
endgenerate
wire rednorm_valid_out, stall_from_round;
wire [26:0] mantissa_norm;
wire [8:0] exponent_norm;
wire sign_norm;
acl_fp_custom_reduced_normalize rednorm(
.clock(clock),
.resetn(resetn),
.mantissa(new_mantissa),
.exponent(new_exponent),
.sign(new_sign),
.stall_in(stall_from_round),
.valid_in(new_valid),
.stall_out(stall_from_norm),
.valid_out(rednorm_valid_out),
.enable(enable),
.mantissa_out(mantissa_norm),
.exponent_out(exponent_norm),
.sign_out(sign_norm));
defparam rednorm.HIGH_CAPACITY = HIGH_CAPACITY;
defparam rednorm.FLUSH_DENORMS = FLUSH_DENORMS;
defparam rednorm.HIGH_LATENCY = HIGH_LATENCY;
defparam rednorm.REMOVE_STICKY = REMOVE_STICKY;
defparam rednorm.FINITE_MATH_ONLY = FINITE_MATH_ONLY;
wire round_valid_out, stall_from_ieee;
wire [26:0] mantissa_round;
wire [8:0] exponent_round;
wire sign_round;
acl_fp_custom_round_post round(
.clock(clock),
.resetn(resetn),
.mantissa(mantissa_norm),
.exponent(exponent_norm),
.sign(sign_norm),
.mantissa_out(mantissa_round),
.exponent_out(exponent_round),
.sign_out(sign_round),
.valid_in(rednorm_valid_out),
.valid_out(round_valid_out),
.stall_in(stall_from_ieee),
.stall_out(stall_from_round),
.enable(enable));
defparam round.HIGH_CAPACITY = HIGH_CAPACITY;
defparam round.FLUSH_DENORMS = FLUSH_DENORMS;
defparam round.HIGH_LATENCY = HIGH_LATENCY;
defparam round.ROUNDING_MODE = ROUNDING_MODE;
defparam round.REMOVE_STICKY = REMOVE_STICKY;
defparam round.FINITE_MATH_ONLY = FINITE_MATH_ONLY;
acl_fp_convert_to_ieee toieee(
.clock(clock),
.resetn(resetn),
.mantissa(mantissa_round),
.exponent(exponent_round),
.sign(sign_round),
.result(result),
.valid_in(round_valid_out),
.valid_out(valid_out),
.stall_in(stall_in),
.stall_out(stall_from_ieee),
.enable(enable));
defparam toieee.FINITE_MATH_ONLY = FINITE_MATH_ONLY;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2006 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=0;
reg [63:0] crc;
reg [31:0] sum;
wire [15:0] out0;
wire [15:0] out1;
wire [15:0] inData = crc[15:0];
wire wr0a = crc[16];
wire wr0b = crc[17];
wire wr1a = crc[18];
wire wr1b = crc[19];
fifo fifo (
// Outputs
.out0 (out0[15:0]),
.out1 (out1[15:0]),
// Inputs
.clk (clk),
.wr0a (wr0a),
.wr0b (wr0b),
.wr1a (wr1a),
.wr1b (wr1b),
.inData (inData[15:0]));
always @ (posedge clk) begin
//$write("[%0t] cyc==%0d crc=%x q=%x\n",$time, cyc, crc, sum);
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 32'h0;
end
else if (cyc>10 && cyc<90) begin
sum <= {sum[30:0],sum[31]} ^ {out1, out0};
end
else if (cyc==99) begin
if (sum !== 32'he8bbd130) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module fifo (/*AUTOARG*/
// Outputs
out0, out1,
// Inputs
clk, wr0a, wr0b, wr1a, wr1b, inData
);
input clk;
input wr0a;
input wr0b;
input wr1a;
input wr1b;
input [15:0] inData;
output [15:0] out0;
output [15:0] out1;
reg [15:0] mem [1:0];
reg [15:0] memtemp2 [1:0];
reg [15:0] memtemp3 [1:0];
assign out0 = {mem[0] ^ memtemp2[0]};
assign out1 = {mem[1] ^ memtemp3[1]};
always @(posedge clk) begin
// These mem assignments must be done in order after processing
if (wr0a) begin
memtemp2[0] <= inData;
mem[0] <= inData;
end
if (wr0b) begin
memtemp3[0] <= inData;
mem[0] <= ~inData;
end
if (wr1a) begin
memtemp3[1] <= inData;
mem[1] <= inData;
end
if (wr1b) begin
memtemp2[1] <= inData;
mem[1] <= ~inData;
end
end
endmodule
|
`timescale 1ns/10ps
module tb_mathsop;
reg clock, reset;
reg [15:0] x;
wire [15:0] ym1, ym2, yb1, yb2, yc1, yc2;
initial begin
$dumpfile("vcd/mathsop.vcd");
$dumpvars(0, tb_mathsop);
end
initial begin
$from_myhdl(clock, reset, x);
$to_myhdl(ym1, ym2, yb1, yb2, yc1, yc2);
end
/** the myhdl verilog */
mm_sop1 dut_myhdl1(.clock(clock), .reset(reset),
.x(x), .y(ym1));
mm_sop2 dut_myhdl2(.clock(clock), .reset(reset),
.x(x), .y(ym2));
/** the bluespec verilog (wrapper) */
mkSOP1 dut_bsv1(.CLK(clock), .RST_N(reset),
.write_x(x), .read(yb1));
mkSOP2 dut_bsv2(.CLK(clock), .RST_N(reset),
.write_x(x), .read(yb2));
/** the chisel verilog */
// chisel use active high reset
wire mc_reset = ~reset;
mc_sop1 dut_chisel1(.clk(clock), .reset(mc_reset),
.io_x(x), .io_y(yc1));
//mc_sop2 dut_chisel2(.clk(clock), .reset(mc_reset),
// .io_x(x), .io_y(yc1));
endmodule
|
// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// File name: si_transactor.v
//
// Description:
// This module manages multi-threaded transactions for one SI-slot.
// The module interface consists of a 1-slave to 1-master address channel, plus a
// (M+1)-master (from M MI-slots plus error handler) to 1-slave response channel.
// The module maintains transaction thread control registers that count the
// number of outstanding transations for each thread and the target MI-slot.
// On the address channel, the module decodes addresses to select among MI-slots
// accessible to the SI-slot where it is instantiated.
// It then qualifies whether each received transaction
// should be propagated as a request to the address channel arbiter.
// Transactions are blocked while there is any outstanding transaction to a
// different slave (MI-slot) for the requested ID thread (for deadlock avoidance).
// On the response channel, the module mulitplexes transfers from each of the
// MI-slots whenever a transfer targets the ID of an active thread,
// arbitrating between MI-slots if multiple threads respond concurrently.
//
//--------------------------------------------------------------------------
//
// Structure:
// si_transactor
// addr_decoder
// comparator_static
// mux_enc
// axic_srl_fifo
// arbiter_resp
//
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_crossbar_v2_1_si_transactor #
(
parameter C_FAMILY = "none",
parameter integer C_SI = 0, // SI-slot number of current instance.
parameter integer C_DIR = 0, // Direction: 0 = Write; 1 = Read.
parameter integer C_NUM_ADDR_RANGES = 1,
parameter integer C_NUM_M = 2,
parameter integer C_NUM_M_LOG = 1,
parameter integer C_ACCEPTANCE = 1, // Acceptance limit of this SI-slot.
parameter integer C_ACCEPTANCE_LOG = 0, // Width of acceptance counter for this SI-slot.
parameter integer C_ID_WIDTH = 1,
parameter integer C_THREAD_ID_WIDTH = 0,
parameter integer C_ADDR_WIDTH = 32,
parameter integer C_AMESG_WIDTH = 1, // Used for AW or AR channel payload, depending on instantiation.
parameter integer C_RMESG_WIDTH = 1, // Used for B or R channel payload, depending on instantiation.
parameter [C_ID_WIDTH-1:0] C_BASE_ID = {C_ID_WIDTH{1'b0}},
parameter [C_ID_WIDTH-1:0] C_HIGH_ID = {C_ID_WIDTH{1'b0}},
parameter [C_NUM_M*C_NUM_ADDR_RANGES*64-1:0] C_BASE_ADDR = {C_NUM_M*C_NUM_ADDR_RANGES*64{1'b1}},
parameter [C_NUM_M*C_NUM_ADDR_RANGES*64-1:0] C_HIGH_ADDR = {C_NUM_M*C_NUM_ADDR_RANGES*64{1'b0}},
parameter integer C_SINGLE_THREAD = 0,
parameter [C_NUM_M-1:0] C_TARGET_QUAL = {C_NUM_M{1'b1}},
parameter [C_NUM_M*32-1:0] C_M_AXI_SECURE = {C_NUM_M{32'h00000000}},
parameter integer C_RANGE_CHECK = 0,
parameter integer C_ADDR_DECODE =0,
parameter [C_NUM_M*32-1:0] C_ERR_MODE = {C_NUM_M{32'h00000000}},
parameter integer C_DEBUG = 1
)
(
// Global Signals
input wire ACLK,
input wire ARESET,
// Slave Address Channel Interface Ports
input wire [C_ID_WIDTH-1:0] S_AID,
input wire [C_ADDR_WIDTH-1:0] S_AADDR,
input wire [8-1:0] S_ALEN,
input wire [3-1:0] S_ASIZE,
input wire [2-1:0] S_ABURST,
input wire [2-1:0] S_ALOCK,
input wire [3-1:0] S_APROT,
// input wire [4-1:0] S_AREGION,
input wire [C_AMESG_WIDTH-1:0] S_AMESG,
input wire S_AVALID,
output wire S_AREADY,
// Master Address Channel Interface Ports
output wire [C_ID_WIDTH-1:0] M_AID,
output wire [C_ADDR_WIDTH-1:0] M_AADDR,
output wire [8-1:0] M_ALEN,
output wire [3-1:0] M_ASIZE,
output wire [2-1:0] M_ALOCK,
output wire [3-1:0] M_APROT,
output wire [4-1:0] M_AREGION,
output wire [C_AMESG_WIDTH-1:0] M_AMESG,
output wire [(C_NUM_M+1)-1:0] M_ATARGET_HOT,
output wire [(C_NUM_M_LOG+1)-1:0] M_ATARGET_ENC,
output wire [7:0] M_AERROR,
output wire M_AVALID_QUAL,
output wire M_AVALID,
input wire M_AREADY,
// Slave Response Channel Interface Ports
output wire [C_ID_WIDTH-1:0] S_RID,
output wire [C_RMESG_WIDTH-1:0] S_RMESG,
output wire S_RLAST,
output wire S_RVALID,
input wire S_RREADY,
// Master Response Channel Interface Ports
input wire [(C_NUM_M+1)*C_ID_WIDTH-1:0] M_RID,
input wire [(C_NUM_M+1)*C_RMESG_WIDTH-1:0] M_RMESG,
input wire [(C_NUM_M+1)-1:0] M_RLAST,
input wire [(C_NUM_M+1)-1:0] M_RVALID,
output wire [(C_NUM_M+1)-1:0] M_RREADY,
input wire [(C_NUM_M+1)-1:0] M_RTARGET, // Does response ID from each MI-slot target this SI slot?
input wire [8-1:0] DEBUG_A_TRANS_SEQ
);
localparam integer P_WRITE = 0;
localparam integer P_READ = 1;
localparam integer P_RMUX_MESG_WIDTH = C_ID_WIDTH + C_RMESG_WIDTH + 1;
localparam [31:0] P_AXILITE_ERRMODE = 32'h00000001;
localparam integer P_NONSECURE_BIT = 1;
localparam integer P_NUM_M_LOG_M1 = C_NUM_M_LOG ? C_NUM_M_LOG : 1;
localparam [C_NUM_M-1:0] P_M_AXILITE = f_m_axilite(0); // Mask of AxiLite MI-slots
localparam [1:0] P_FIXED = 2'b00;
localparam integer P_NUM_M_DE_LOG = f_ceil_log2(C_NUM_M+1);
localparam integer P_THREAD_ID_WIDTH_M1 = (C_THREAD_ID_WIDTH > 0) ? C_THREAD_ID_WIDTH : 1;
localparam integer P_NUM_ID_VAL = 2**C_THREAD_ID_WIDTH;
localparam integer P_NUM_THREADS = (P_NUM_ID_VAL < C_ACCEPTANCE) ? P_NUM_ID_VAL : C_ACCEPTANCE;
localparam [C_NUM_M-1:0] P_M_SECURE_MASK = f_bit32to1_mi(C_M_AXI_SECURE); // Mask of secure MI-slots
// Ceiling of log2(x)
function integer f_ceil_log2
(
input integer x
);
integer acc;
begin
acc=0;
while ((2**acc) < x)
acc = acc + 1;
f_ceil_log2 = acc;
end
endfunction
// AxiLite protocol flag vector
function [C_NUM_M-1:0] f_m_axilite
(
input integer null_arg
);
integer mi;
begin
for (mi=0; mi<C_NUM_M; mi=mi+1) begin
f_m_axilite[mi] = (C_ERR_MODE[mi*32+:32] == P_AXILITE_ERRMODE);
end
end
endfunction
// Convert Bit32 vector of range [0,1] to Bit1 vector on MI
function [C_NUM_M-1:0] f_bit32to1_mi
(input [C_NUM_M*32-1:0] vec32);
integer mi;
begin
for (mi=0; mi<C_NUM_M; mi=mi+1) begin
f_bit32to1_mi[mi] = vec32[mi*32];
end
end
endfunction
wire [C_NUM_M-1:0] target_mi_hot;
wire [P_NUM_M_LOG_M1-1:0] target_mi_enc;
wire [(C_NUM_M+1)-1:0] m_atarget_hot_i;
wire [(P_NUM_M_DE_LOG)-1:0] m_atarget_enc_i;
wire match;
wire [3:0] target_region;
wire [3:0] m_aregion_i;
wire m_avalid_i;
wire s_aready_i;
wire any_error;
wire s_rvalid_i;
wire [C_ID_WIDTH-1:0] s_rid_i;
wire s_rlast_i;
wire [P_RMUX_MESG_WIDTH-1:0] si_rmux_mesg;
wire [(C_NUM_M+1)*P_RMUX_MESG_WIDTH-1:0] mi_rmux_mesg;
wire [(C_NUM_M+1)-1:0] m_rvalid_qual;
wire [(C_NUM_M+1)-1:0] m_rready_arb;
wire [(C_NUM_M+1)-1:0] m_rready_i;
wire target_secure;
wire target_axilite;
wire m_avalid_qual_i;
wire [7:0] m_aerror_i;
genvar gen_mi;
genvar gen_thread;
generate
if (C_ADDR_DECODE) begin : gen_addr_decoder
axi_crossbar_v2_1_addr_decoder #
(
.C_FAMILY (C_FAMILY),
.C_NUM_TARGETS (C_NUM_M),
.C_NUM_TARGETS_LOG (P_NUM_M_LOG_M1),
.C_NUM_RANGES (C_NUM_ADDR_RANGES),
.C_ADDR_WIDTH (C_ADDR_WIDTH),
.C_TARGET_ENC (1),
.C_TARGET_HOT (1),
.C_REGION_ENC (1),
.C_BASE_ADDR (C_BASE_ADDR),
.C_HIGH_ADDR (C_HIGH_ADDR),
.C_TARGET_QUAL (C_TARGET_QUAL),
.C_RESOLUTION (2)
)
addr_decoder_inst
(
.ADDR (S_AADDR),
.TARGET_HOT (target_mi_hot),
.TARGET_ENC (target_mi_enc),
.MATCH (match),
.REGION (target_region)
);
end else begin : gen_no_addr_decoder
assign target_mi_hot = 1;
assign target_mi_enc = 0;
assign match = 1'b1;
assign target_region = 4'b0000;
end
endgenerate
assign target_secure = |(target_mi_hot & P_M_SECURE_MASK);
assign target_axilite = |(target_mi_hot & P_M_AXILITE);
assign any_error = C_RANGE_CHECK && (m_aerror_i != 0); // DECERR if error-detection enabled and any error condition.
assign m_aerror_i[0] = ~match; // Invalid target address
assign m_aerror_i[1] = target_secure && S_APROT[P_NONSECURE_BIT]; // TrustZone violation
assign m_aerror_i[2] = target_axilite && ((S_ALEN != 0) ||
(S_ASIZE[1:0] == 2'b11) || (S_ASIZE[2] == 1'b1)); // AxiLite access violation
assign m_aerror_i[7:3] = 5'b00000; // Reserved
assign M_ATARGET_HOT = m_atarget_hot_i;
assign m_atarget_hot_i = (any_error ? {1'b1, {C_NUM_M{1'b0}}} : {1'b0, target_mi_hot});
assign m_atarget_enc_i = (any_error ? C_NUM_M : target_mi_enc);
assign M_AVALID = m_avalid_i;
assign m_avalid_i = S_AVALID;
assign M_AVALID_QUAL = m_avalid_qual_i;
assign S_AREADY = s_aready_i;
assign s_aready_i = M_AREADY;
assign M_AERROR = m_aerror_i;
assign M_ATARGET_ENC = m_atarget_enc_i;
assign m_aregion_i = any_error ? 4'b0000 : (C_ADDR_DECODE != 0) ? target_region : 4'b0000;
// assign m_aregion_i = any_error ? 4'b0000 : (C_ADDR_DECODE != 0) ? target_region : S_AREGION;
assign M_AREGION = m_aregion_i;
assign M_AID = S_AID;
assign M_AADDR = S_AADDR;
assign M_ALEN = S_ALEN;
assign M_ASIZE = S_ASIZE;
assign M_ALOCK = S_ALOCK;
assign M_APROT = S_APROT;
assign M_AMESG = S_AMESG;
assign S_RVALID = s_rvalid_i;
assign M_RREADY = m_rready_i;
assign s_rid_i = si_rmux_mesg[0+:C_ID_WIDTH];
assign S_RMESG = si_rmux_mesg[C_ID_WIDTH+:C_RMESG_WIDTH];
assign s_rlast_i = si_rmux_mesg[C_ID_WIDTH+C_RMESG_WIDTH+:1];
assign S_RID = s_rid_i;
assign S_RLAST = s_rlast_i;
assign m_rvalid_qual = M_RVALID & M_RTARGET;
assign m_rready_i = m_rready_arb & M_RTARGET;
generate
for (gen_mi=0; gen_mi<(C_NUM_M+1); gen_mi=gen_mi+1) begin : gen_rmesg_mi
// Note: Concatenation of mesg signals is from MSB to LSB; assignments that chop mesg signals appear in opposite order.
assign mi_rmux_mesg[gen_mi*P_RMUX_MESG_WIDTH+:P_RMUX_MESG_WIDTH] = {
M_RLAST[gen_mi],
M_RMESG[gen_mi*C_RMESG_WIDTH+:C_RMESG_WIDTH],
M_RID[gen_mi*C_ID_WIDTH+:C_ID_WIDTH]
};
end // gen_rmesg_mi
if (C_ACCEPTANCE == 1) begin : gen_single_issue
wire cmd_push;
wire cmd_pop;
reg [(C_NUM_M+1)-1:0] active_target_hot;
reg [P_NUM_M_DE_LOG-1:0] active_target_enc;
reg accept_cnt;
reg [8-1:0] debug_r_beat_cnt_i;
wire [8-1:0] debug_r_trans_seq_i;
assign cmd_push = M_AREADY;
assign cmd_pop = s_rvalid_i && S_RREADY && s_rlast_i; // Pop command queue if end of read burst
assign m_avalid_qual_i = ~accept_cnt | cmd_pop; // Ready for arbitration if no outstanding transaction or transaction being completed
always @(posedge ACLK) begin
if (ARESET) begin
accept_cnt <= 1'b0;
active_target_enc <= 0;
active_target_hot <= 0;
end else begin
if (cmd_push) begin
active_target_enc <= m_atarget_enc_i;
active_target_hot <= m_atarget_hot_i;
accept_cnt <= 1'b1;
end else if (cmd_pop) begin
accept_cnt <= 1'b0;
end
end
end // Clocked process
assign m_rready_arb = active_target_hot & {(C_NUM_M+1){S_RREADY}};
assign s_rvalid_i = |(active_target_hot & m_rvalid_qual);
generic_baseblocks_v2_1_mux_enc #
(
.C_FAMILY (C_FAMILY),
.C_RATIO (C_NUM_M+1),
.C_SEL_WIDTH (P_NUM_M_DE_LOG),
.C_DATA_WIDTH (P_RMUX_MESG_WIDTH)
) mux_resp_single_issue
(
.S (active_target_enc),
.A (mi_rmux_mesg),
.O (si_rmux_mesg),
.OE (1'b1)
);
if (C_DEBUG) begin : gen_debug_r_single_issue
// DEBUG READ BEAT COUNTER (only meaningful for R-channel)
always @(posedge ACLK) begin
if (ARESET) begin
debug_r_beat_cnt_i <= 0;
end else if (C_DIR == P_READ) begin
if (s_rvalid_i && S_RREADY) begin
if (s_rlast_i) begin
debug_r_beat_cnt_i <= 0;
end else begin
debug_r_beat_cnt_i <= debug_r_beat_cnt_i + 1;
end
end
end else begin
debug_r_beat_cnt_i <= 0;
end
end // Clocked process
// DEBUG R-CHANNEL TRANSACTION SEQUENCE FIFO
axi_data_fifo_v2_1_axic_srl_fifo #
(
.C_FAMILY (C_FAMILY),
.C_FIFO_WIDTH (8),
.C_FIFO_DEPTH_LOG (C_ACCEPTANCE_LOG+1),
.C_USE_FULL (0)
)
debug_r_seq_fifo_single_issue
(
.ACLK (ACLK),
.ARESET (ARESET),
.S_MESG (DEBUG_A_TRANS_SEQ),
.S_VALID (cmd_push),
.S_READY (),
.M_MESG (debug_r_trans_seq_i),
.M_VALID (),
.M_READY (cmd_pop)
);
end // gen_debug_r
end else if (C_SINGLE_THREAD || (P_NUM_ID_VAL==1)) begin : gen_single_thread
wire s_avalid_en;
wire cmd_push;
wire cmd_pop;
reg [C_ID_WIDTH-1:0] active_id;
reg [(C_NUM_M+1)-1:0] active_target_hot;
reg [P_NUM_M_DE_LOG-1:0] active_target_enc;
reg [4-1:0] active_region;
reg [(C_ACCEPTANCE_LOG+1)-1:0] accept_cnt;
reg [8-1:0] debug_r_beat_cnt_i;
wire [8-1:0] debug_r_trans_seq_i;
wire accept_limit ;
// Implement single-region-per-ID cyclic dependency avoidance method.
assign s_avalid_en = // This transaction is qualified to request arbitration if ...
(accept_cnt == 0) || // Either there are no outstanding transactions, or ...
(((P_NUM_ID_VAL==1) || (S_AID[P_THREAD_ID_WIDTH_M1-1:0] == active_id[P_THREAD_ID_WIDTH_M1-1:0])) && // the current transaction ID matches the previous, and ...
(active_target_enc == m_atarget_enc_i) && // all outstanding transactions are to the same target MI ...
(active_region == m_aregion_i)); // and to the same REGION.
assign cmd_push = M_AREADY;
assign cmd_pop = s_rvalid_i && S_RREADY && s_rlast_i; // Pop command queue if end of read burst
assign accept_limit = (accept_cnt == C_ACCEPTANCE) & ~cmd_pop; // Allow next push if a transaction is currently being completed
assign m_avalid_qual_i = s_avalid_en & ~accept_limit;
always @(posedge ACLK) begin
if (ARESET) begin
accept_cnt <= 0;
active_id <= 0;
active_target_enc <= 0;
active_target_hot <= 0;
active_region <= 0;
end else begin
if (cmd_push) begin
active_id <= S_AID[P_THREAD_ID_WIDTH_M1-1:0];
active_target_enc <= m_atarget_enc_i;
active_target_hot <= m_atarget_hot_i;
active_region <= m_aregion_i;
if (~cmd_pop) begin
accept_cnt <= accept_cnt + 1;
end
end else begin
if (cmd_pop & (accept_cnt != 0)) begin
accept_cnt <= accept_cnt - 1;
end
end
end
end // Clocked process
assign m_rready_arb = active_target_hot & {(C_NUM_M+1){S_RREADY}};
assign s_rvalid_i = |(active_target_hot & m_rvalid_qual);
generic_baseblocks_v2_1_mux_enc #
(
.C_FAMILY (C_FAMILY),
.C_RATIO (C_NUM_M+1),
.C_SEL_WIDTH (P_NUM_M_DE_LOG),
.C_DATA_WIDTH (P_RMUX_MESG_WIDTH)
) mux_resp_single_thread
(
.S (active_target_enc),
.A (mi_rmux_mesg),
.O (si_rmux_mesg),
.OE (1'b1)
);
if (C_DEBUG) begin : gen_debug_r_single_thread
// DEBUG READ BEAT COUNTER (only meaningful for R-channel)
always @(posedge ACLK) begin
if (ARESET) begin
debug_r_beat_cnt_i <= 0;
end else if (C_DIR == P_READ) begin
if (s_rvalid_i && S_RREADY) begin
if (s_rlast_i) begin
debug_r_beat_cnt_i <= 0;
end else begin
debug_r_beat_cnt_i <= debug_r_beat_cnt_i + 1;
end
end
end else begin
debug_r_beat_cnt_i <= 0;
end
end // Clocked process
// DEBUG R-CHANNEL TRANSACTION SEQUENCE FIFO
axi_data_fifo_v2_1_axic_srl_fifo #
(
.C_FAMILY (C_FAMILY),
.C_FIFO_WIDTH (8),
.C_FIFO_DEPTH_LOG (C_ACCEPTANCE_LOG+1),
.C_USE_FULL (0)
)
debug_r_seq_fifo_single_thread
(
.ACLK (ACLK),
.ARESET (ARESET),
.S_MESG (DEBUG_A_TRANS_SEQ),
.S_VALID (cmd_push),
.S_READY (),
.M_MESG (debug_r_trans_seq_i),
.M_VALID (),
.M_READY (cmd_pop)
);
end // gen_debug_r
end else begin : gen_multi_thread
wire [(P_NUM_M_DE_LOG)-1:0] resp_select;
reg [(C_ACCEPTANCE_LOG+1)-1:0] accept_cnt;
wire [P_NUM_THREADS-1:0] s_avalid_en;
wire [P_NUM_THREADS-1:0] thread_valid;
wire [P_NUM_THREADS-1:0] aid_match;
wire [P_NUM_THREADS-1:0] rid_match;
wire [P_NUM_THREADS-1:0] cmd_push;
wire [P_NUM_THREADS-1:0] cmd_pop;
wire [P_NUM_THREADS:0] accum_push;
reg [P_NUM_THREADS*C_ID_WIDTH-1:0] active_id;
reg [P_NUM_THREADS*8-1:0] active_target;
reg [P_NUM_THREADS*8-1:0] active_region;
reg [P_NUM_THREADS*8-1:0] active_cnt;
reg [P_NUM_THREADS*8-1:0] debug_r_beat_cnt_i;
wire [P_NUM_THREADS*8-1:0] debug_r_trans_seq_i;
wire any_aid_match;
wire any_rid_match;
wire accept_limit;
wire any_push;
wire any_pop;
axi_crossbar_v2_1_arbiter_resp # // Multi-thread response arbiter
(
.C_FAMILY (C_FAMILY),
.C_NUM_S (C_NUM_M+1),
.C_NUM_S_LOG (P_NUM_M_DE_LOG),
.C_GRANT_ENC (1),
.C_GRANT_HOT (0)
)
arbiter_resp_inst
(
.ACLK (ACLK),
.ARESET (ARESET),
.S_VALID (m_rvalid_qual),
.S_READY (m_rready_arb),
.M_GRANT_HOT (),
.M_GRANT_ENC (resp_select),
.M_VALID (s_rvalid_i),
.M_READY (S_RREADY)
);
generic_baseblocks_v2_1_mux_enc #
(
.C_FAMILY (C_FAMILY),
.C_RATIO (C_NUM_M+1),
.C_SEL_WIDTH (P_NUM_M_DE_LOG),
.C_DATA_WIDTH (P_RMUX_MESG_WIDTH)
) mux_resp_multi_thread
(
.S (resp_select),
.A (mi_rmux_mesg),
.O (si_rmux_mesg),
.OE (1'b1)
);
assign any_push = M_AREADY;
assign any_pop = s_rvalid_i & S_RREADY & s_rlast_i;
assign accept_limit = (accept_cnt == C_ACCEPTANCE) & ~any_pop; // Allow next push if a transaction is currently being completed
assign m_avalid_qual_i = (&s_avalid_en) & ~accept_limit; // The current request is qualified for arbitration when it is qualified against all outstanding transaction threads.
assign any_aid_match = |aid_match;
assign any_rid_match = |rid_match;
assign accum_push[0] = 1'b0;
always @(posedge ACLK) begin
if (ARESET) begin
accept_cnt <= 0;
end else begin
if (any_push & ~any_pop) begin
accept_cnt <= accept_cnt + 1;
end else if (any_pop & ~any_push & (accept_cnt != 0)) begin
accept_cnt <= accept_cnt - 1;
end
end
end // Clocked process
for (gen_thread=0; gen_thread<P_NUM_THREADS; gen_thread=gen_thread+1) begin : gen_thread_loop
assign thread_valid[gen_thread] = (active_cnt[gen_thread*8 +: C_ACCEPTANCE_LOG+1] != 0);
assign aid_match[gen_thread] = // The currect thread is active for the requested transaction if
thread_valid[gen_thread] && // this thread slot is not vacant, and
((S_AID[P_THREAD_ID_WIDTH_M1-1:0]) == active_id[gen_thread*C_ID_WIDTH+:P_THREAD_ID_WIDTH_M1]); // the requested ID matches the active ID for this thread.
assign s_avalid_en[gen_thread] = // The current request is qualified against this thread slot if
(~aid_match[gen_thread]) || // This thread slot is not active for the requested ID, or
((m_atarget_enc_i == active_target[gen_thread*8+:P_NUM_M_DE_LOG]) && // this outstanding transaction was to the same target and
(m_aregion_i == active_region[gen_thread*8+:4])); // to the same region.
// cmd_push points to the position of either the active thread for the requested ID or the lowest vacant thread slot.
assign accum_push[gen_thread+1] = accum_push[gen_thread] | ~thread_valid[gen_thread];
assign cmd_push[gen_thread] = any_push & (aid_match[gen_thread] | ((~any_aid_match) & ~thread_valid[gen_thread] & ~accum_push[gen_thread]));
// cmd_pop points to the position of the active thread that matches the current RID.
assign rid_match[gen_thread] = thread_valid[gen_thread] & ((s_rid_i[P_THREAD_ID_WIDTH_M1-1:0]) == active_id[gen_thread*C_ID_WIDTH+:P_THREAD_ID_WIDTH_M1]);
assign cmd_pop[gen_thread] = any_pop & rid_match[gen_thread];
always @(posedge ACLK) begin
if (ARESET) begin
active_id[gen_thread*C_ID_WIDTH+:C_ID_WIDTH] <= 0;
active_target[gen_thread*8+:8] <= 0;
active_region[gen_thread*8+:8] <= 0;
active_cnt[gen_thread*8+:8] <= 0;
end else begin
if (cmd_push[gen_thread]) begin
active_id[gen_thread*C_ID_WIDTH+:P_THREAD_ID_WIDTH_M1] <= S_AID[P_THREAD_ID_WIDTH_M1-1:0];
active_target[gen_thread*8+:P_NUM_M_DE_LOG] <= m_atarget_enc_i;
active_region[gen_thread*8+:4] <= m_aregion_i;
if (~cmd_pop[gen_thread]) begin
active_cnt[gen_thread*8+:C_ACCEPTANCE_LOG+1] <= active_cnt[gen_thread*8+:C_ACCEPTANCE_LOG+1] + 1;
end
end else if (cmd_pop[gen_thread]) begin
active_cnt[gen_thread*8+:C_ACCEPTANCE_LOG+1] <= active_cnt[gen_thread*8+:C_ACCEPTANCE_LOG+1] - 1;
end
end
end // Clocked process
if (C_DEBUG) begin : gen_debug_r_multi_thread
// DEBUG READ BEAT COUNTER (only meaningful for R-channel)
always @(posedge ACLK) begin
if (ARESET) begin
debug_r_beat_cnt_i[gen_thread*8+:8] <= 0;
end else if (C_DIR == P_READ) begin
if (s_rvalid_i & S_RREADY & rid_match[gen_thread]) begin
if (s_rlast_i) begin
debug_r_beat_cnt_i[gen_thread*8+:8] <= 0;
end else begin
debug_r_beat_cnt_i[gen_thread*8+:8] <= debug_r_beat_cnt_i[gen_thread*8+:8] + 1;
end
end
end else begin
debug_r_beat_cnt_i[gen_thread*8+:8] <= 0;
end
end // Clocked process
// DEBUG R-CHANNEL TRANSACTION SEQUENCE FIFO
axi_data_fifo_v2_1_axic_srl_fifo #
(
.C_FAMILY (C_FAMILY),
.C_FIFO_WIDTH (8),
.C_FIFO_DEPTH_LOG (C_ACCEPTANCE_LOG+1),
.C_USE_FULL (0)
)
debug_r_seq_fifo_multi_thread
(
.ACLK (ACLK),
.ARESET (ARESET),
.S_MESG (DEBUG_A_TRANS_SEQ),
.S_VALID (cmd_push[gen_thread]),
.S_READY (),
.M_MESG (debug_r_trans_seq_i[gen_thread*8+:8]),
.M_VALID (),
.M_READY (cmd_pop[gen_thread])
);
end // gen_debug_r_multi_thread
end // Next gen_thread_loop
end // thread control
endgenerate
endmodule
`default_nettype wire
|
module xillyvga_core
(
input S_AXI_ACLK,
input [31:0] S_AXI_ARADDR,
input S_AXI_ARESETN,
input S_AXI_ARVALID,
input [31:0] S_AXI_AWADDR,
input S_AXI_AWVALID,
input S_AXI_BREADY,
input S_AXI_RREADY,
input [31:0] S_AXI_WDATA,
input [3:0] S_AXI_WSTRB,
input S_AXI_WVALID,
input clk_in,
input m_axi_aclk,
input m_axi_aresetn,
input m_axi_arready,
input m_axi_awready,
input [1:0] m_axi_bresp,
input m_axi_bvalid,
input [31:0] m_axi_rdata,
input m_axi_rlast,
input [1:0] m_axi_rresp,
input m_axi_rvalid,
input m_axi_wready,
output S_AXI_ARREADY,
output S_AXI_AWREADY,
output [1:0] S_AXI_BRESP,
output S_AXI_BVALID,
output [31:0] S_AXI_RDATA,
output [1:0] S_AXI_RRESP,
output S_AXI_RVALID,
output S_AXI_WREADY,
output [31:0] m_axi_araddr,
output [1:0] m_axi_arburst,
output [3:0] m_axi_arcache,
output [3:0] m_axi_arlen,
output [2:0] m_axi_arprot,
output [2:0] m_axi_arsize,
output m_axi_arvalid,
output [31:0] m_axi_awaddr,
output [1:0] m_axi_awburst,
output [3:0] m_axi_awcache,
output [3:0] m_axi_awlen,
output [2:0] m_axi_awprot,
output [2:0] m_axi_awsize,
output m_axi_awvalid,
output m_axi_bready,
output m_axi_rready,
output [31:0] m_axi_wdata,
output m_axi_wlast,
output [3:0] m_axi_wstrb,
output m_axi_wvalid,
output vga_clk,
output [7:0] vga_blue,
output [7:0] vga_green,
output vga_hsync,
output [7:0] vga_red,
output vga_de,
output vga_vsync
);
endmodule
|
/*
Copyright (c) 2019 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for eth_mac_phy_10g_fifo
*/
module test_eth_mac_phy_10g_fifo;
// Parameters
parameter DATA_WIDTH = 64;
parameter HDR_WIDTH = (DATA_WIDTH/32);
parameter AXIS_DATA_WIDTH = DATA_WIDTH;
parameter AXIS_KEEP_ENABLE = (AXIS_DATA_WIDTH>8);
parameter AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH/8);
parameter ENABLE_PADDING = 1;
parameter ENABLE_DIC = 1;
parameter MIN_FRAME_LENGTH = 64;
parameter BIT_REVERSE = 0;
parameter SCRAMBLER_DISABLE = 0;
parameter PRBS31_ENABLE = 1;
parameter TX_SERDES_PIPELINE = 2;
parameter RX_SERDES_PIPELINE = 2;
parameter BITSLIP_HIGH_CYCLES = 1;
parameter BITSLIP_LOW_CYCLES = 8;
parameter COUNT_125US = 125000/6.4;
parameter TX_FIFO_DEPTH = 4096;
parameter TX_FIFO_PIPELINE_OUTPUT = 2;
parameter TX_FRAME_FIFO = 1;
parameter TX_DROP_BAD_FRAME = TX_FRAME_FIFO;
parameter TX_DROP_WHEN_FULL = 0;
parameter RX_FIFO_DEPTH = 4096;
parameter RX_FIFO_PIPELINE_OUTPUT = 2;
parameter RX_FRAME_FIFO = 1;
parameter RX_DROP_BAD_FRAME = RX_FRAME_FIFO;
parameter RX_DROP_WHEN_FULL = RX_FRAME_FIFO;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg rx_clk = 0;
reg rx_rst = 0;
reg tx_clk = 0;
reg tx_rst = 0;
reg logic_clk = 0;
reg logic_rst = 0;
reg [AXIS_DATA_WIDTH-1:0] tx_axis_tdata = 0;
reg [AXIS_KEEP_WIDTH-1:0] tx_axis_tkeep = 0;
reg tx_axis_tvalid = 0;
reg tx_axis_tlast = 0;
reg tx_axis_tuser = 0;
reg rx_axis_tready = 0;
reg [DATA_WIDTH-1:0] serdes_rx_data = 0;
reg [HDR_WIDTH-1:0] serdes_rx_hdr = 1;
reg [7:0] ifg_delay = 0;
reg tx_prbs31_enable = 0;
reg rx_prbs31_enable = 0;
// Outputs
wire tx_axis_tready;
wire [AXIS_DATA_WIDTH-1:0] rx_axis_tdata;
wire [AXIS_KEEP_WIDTH-1:0] rx_axis_tkeep;
wire rx_axis_tvalid;
wire rx_axis_tlast;
wire rx_axis_tuser;
wire [DATA_WIDTH-1:0] serdes_tx_data;
wire [HDR_WIDTH-1:0] serdes_tx_hdr;
wire serdes_rx_bitslip;
wire tx_error_underflow;
wire tx_fifo_overflow;
wire tx_fifo_bad_frame;
wire tx_fifo_good_frame;
wire rx_error_bad_frame;
wire rx_error_bad_fcs;
wire rx_bad_block;
wire rx_block_lock;
wire rx_high_ber;
wire rx_fifo_overflow;
wire rx_fifo_bad_frame;
wire rx_fifo_good_frame;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
rx_clk,
rx_rst,
tx_clk,
tx_rst,
logic_clk,
logic_rst,
tx_axis_tdata,
tx_axis_tkeep,
tx_axis_tvalid,
tx_axis_tlast,
tx_axis_tuser,
rx_axis_tready,
serdes_rx_data,
serdes_rx_hdr,
ifg_delay,
tx_prbs31_enable,
rx_prbs31_enable
);
$to_myhdl(
tx_axis_tready,
rx_axis_tdata,
rx_axis_tkeep,
rx_axis_tvalid,
rx_axis_tlast,
rx_axis_tuser,
serdes_tx_data,
serdes_tx_hdr,
serdes_rx_bitslip,
tx_error_underflow,
tx_fifo_overflow,
tx_fifo_bad_frame,
tx_fifo_good_frame,
rx_error_bad_frame,
rx_error_bad_fcs,
rx_bad_block,
rx_block_lock,
rx_high_ber,
rx_fifo_overflow,
rx_fifo_bad_frame,
rx_fifo_good_frame
);
// dump file
$dumpfile("test_eth_mac_phy_10g_fifo.lxt");
$dumpvars(0, test_eth_mac_phy_10g_fifo);
end
eth_mac_phy_10g_fifo #(
.DATA_WIDTH(DATA_WIDTH),
.HDR_WIDTH(HDR_WIDTH),
.AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
.AXIS_KEEP_ENABLE(AXIS_KEEP_ENABLE),
.AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.ENABLE_PADDING(ENABLE_PADDING),
.ENABLE_DIC(ENABLE_DIC),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
.BIT_REVERSE(BIT_REVERSE),
.SCRAMBLER_DISABLE(SCRAMBLER_DISABLE),
.PRBS31_ENABLE(PRBS31_ENABLE),
.TX_SERDES_PIPELINE(TX_SERDES_PIPELINE),
.RX_SERDES_PIPELINE(RX_SERDES_PIPELINE),
.BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
.BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES),
.COUNT_125US(COUNT_125US),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),
.TX_FIFO_PIPELINE_OUTPUT(TX_FIFO_PIPELINE_OUTPUT),
.TX_FRAME_FIFO(TX_FRAME_FIFO),
.TX_DROP_BAD_FRAME(TX_DROP_BAD_FRAME),
.TX_DROP_WHEN_FULL(TX_DROP_WHEN_FULL),
.RX_FIFO_DEPTH(RX_FIFO_DEPTH),
.RX_FIFO_PIPELINE_OUTPUT(RX_FIFO_PIPELINE_OUTPUT),
.RX_FRAME_FIFO(RX_FRAME_FIFO),
.RX_DROP_BAD_FRAME(RX_DROP_BAD_FRAME),
.RX_DROP_WHEN_FULL(RX_DROP_WHEN_FULL)
)
UUT (
.rx_clk(rx_clk),
.rx_rst(rx_rst),
.tx_clk(tx_clk),
.tx_rst(tx_rst),
.logic_clk(logic_clk),
.logic_rst(logic_rst),
.tx_axis_tdata(tx_axis_tdata),
.tx_axis_tkeep(tx_axis_tkeep),
.tx_axis_tvalid(tx_axis_tvalid),
.tx_axis_tready(tx_axis_tready),
.tx_axis_tlast(tx_axis_tlast),
.tx_axis_tuser(tx_axis_tuser),
.rx_axis_tdata(rx_axis_tdata),
.rx_axis_tkeep(rx_axis_tkeep),
.rx_axis_tvalid(rx_axis_tvalid),
.rx_axis_tready(rx_axis_tready),
.rx_axis_tlast(rx_axis_tlast),
.rx_axis_tuser(rx_axis_tuser),
.serdes_tx_data(serdes_tx_data),
.serdes_tx_hdr(serdes_tx_hdr),
.serdes_rx_data(serdes_rx_data),
.serdes_rx_hdr(serdes_rx_hdr),
.serdes_rx_bitslip(serdes_rx_bitslip),
.tx_error_underflow(tx_error_underflow),
.tx_fifo_overflow(tx_fifo_overflow),
.tx_fifo_bad_frame(tx_fifo_bad_frame),
.tx_fifo_good_frame(tx_fifo_good_frame),
.rx_error_bad_frame(rx_error_bad_frame),
.rx_error_bad_fcs(rx_error_bad_fcs),
.rx_bad_block(rx_bad_block),
.rx_block_lock(rx_block_lock),
.rx_high_ber(rx_high_ber),
.rx_fifo_overflow(rx_fifo_overflow),
.rx_fifo_bad_frame(rx_fifo_bad_frame),
.rx_fifo_good_frame(rx_fifo_good_frame),
.ifg_delay(ifg_delay),
.tx_prbs31_enable(tx_prbs31_enable),
.rx_prbs31_enable(rx_prbs31_enable)
);
endmodule
|
module spi_controller(
//CLK
input clk,
//RST
input RST_N,
//IRQ to AXI master
output o_IRQ,
//Signals towards AXI interface:
input wire [31:0] i_data_to_registers,
input wire i_wr_controll_reg, // Offset: 0x00
input wire i_wr_data_reg, // Offset: 0x08
input wire i_read_status_reg,
output wire [31:0] o_controll_reg,
output wire [31:0] o_status_reg,
output wire [31:0] o_data_reg,
//SPI interface
input i_miso,
output o_mosi,
output o_sclk
);
///////////////////////////////////////////////////////////////////////////////
// Signal declaration:
// The registers of rhis SPI peripheral.
reg [31:0] q_controll_reg;
wire [31:0] w_status_reg;
reg [7:0] q_data_reg;
// clock and reset:
// SPI controller resister:
reg [7:0] q_spi_bit_cntr;
//Do not use in first implementation. This is a future feature...
reg [2:0] q_spi_byte_cntr;
//IRQ flag
reg q_irq_flag;
//collision flag
reg q_collision_flag;
reg [7:0] q_spi_mosi_shr;
reg [7:0] q_spi_miso_shr;
wire w_setup_spi_data;
wire w_sample_spi_data;
wire w_active_spi_transaction;
wire w_sclk_reset;
wire w_reset;
wire w_dword;
wire w_cpol;
wire w_cpha;
wire w_spr1;
wire w_spr0;
// Concurrent assignments.
assign o_controll_reg = q_controll_reg;
assign o_status_reg = w_status_reg;
assign o_data_reg = q_spi_miso_shr;
assign w_reset = ~RST_N;
assign w_irq_en = q_controll_reg[7];
assign w_spie = q_controll_reg[6];
assign w_dword = q_controll_reg[5];
// assign w_spie = q_controll_reg[4];
assign w_cpol = q_controll_reg[3];
assign w_cpha = q_controll_reg[2];
assign w_spr1 = q_controll_reg[1];
assign w_spr0 = q_controll_reg[0];
assign w_sclk_reset = w_reset | ~w_active_spi_transaction;
// Instance of the Clock generator
spi_clock_generator spi_clock_generator_inst(
//CLK
// i_clk is the system clock (10-200MHz)
.i_clk(clk),
//RST
// i_reset is the system reset. This is a active high signal.
// '1' : reset is active
.i_reset(w_sclk_reset),
//Controll inputs from registers
.i_spr0(w_spr0),
.i_spr1(w_spr1),
.i_cpol(w_cpol),
.i_cpha(w_cpha),
.i_mstr(1'b1),
// Controll output to other logic
// o_sclk: This is the SPI clock. The polarity based on the i_cpol
// The frequency is derived by i_spr0 and i_spr1
.o_sclk(o_sclk),
// o_sclk_rising_edge: is active one sys clk long at the rising edge of
// the sclk.
.o_sclk_rising_edge(),
// o_sclk_falling_edge: is active one sys clk long at the falling edge of
// the sclk.
.o_sclk_falling_edge(),
// o_sample_spi_data: is active one sys clk long at an edge of the spi slck
// i_cpha and i_cpol describe if it is the rising or the falling edge.
.o_sample_spi_data(w_sample_spi_data),
// o_setup_spi_data: is active one sys clk long at an edge of the spi slck
// i_cpha and i_cpol describe if it is the rising or the falling edge.
// Note that this is the alter edge than o_sample_spi_data
.o_setup_spi_data(w_setup_spi_data)
);
///////////////////////////////////////////////////////////////////////////
// The internal register interface. The following blocks drive all internal
// registers.
// Status register:
assign w_status_reg = {q_irq_flag, q_collision_flag, 6'b0};
// control register
always @(posedge clk) begin
if(w_reset)
q_controll_reg <= '0;
if(i_wr_controll_reg) begin
q_controll_reg <= i_data_to_registers;
end
end
//data register
always @(posedge clk) begin
if (w_reset)
q_data_reg <= '0;
else if(i_wr_data_reg) begin
q_data_reg <= i_data_to_registers;
end
if(w_active_spi_transaction) begin
if(w_setup_spi_data) begin
if(w_dword) begin
q_data_reg <= {1'b0, q_data_reg[7:1]};
end else begin
q_data_reg <= {q_data_reg[6:0], 1'b0};
end
end
end
// else begin
// q_data_reg <= q_spi_miso_shr;
// end
end
///////////////////////////////////////////////////////////////////////////
// SPI controller blocks:
// bit_counter
always @(posedge clk) begin
if(w_reset) begin
q_spi_bit_cntr <= 8;
end else begin
if (i_wr_data_reg) begin
q_spi_bit_cntr <= 0;
end else begin
if(w_setup_spi_data) begin
if(w_active_spi_transaction)
q_spi_bit_cntr <= q_spi_bit_cntr + 1;
end
end
end
end
assign w_active_spi_transaction = q_spi_bit_cntr <8;
//interrupt flag
always @(posedge clk) begin
if (w_reset)
q_irq_flag <= 1'b0;
else if(q_spi_bit_cntr == 7 && w_sample_spi_data) begin
q_irq_flag <= 1'b1;
end else begin
if(i_read_status_reg)
q_irq_flag <= 1'b0;
end
end
assign o_IRQ = q_irq_flag;
//collision flag
always @(posedge clk) begin
if(w_reset) begin
q_collision_flag <= 1'b0;
end else begin
if(w_active_spi_transaction) begin
if(i_wr_controll_reg | i_wr_data_reg)
q_collision_flag <= 1'b1;
end else begin
if(i_read_status_reg)
q_collision_flag <= 1'b0;
end
end
end
//miso shr
always @(posedge clk) begin
if(w_sample_spi_data) begin
if(w_dword) begin
q_spi_miso_shr <= {i_miso, q_spi_miso_shr[7:1]};
end else begin
q_spi_miso_shr <= {q_spi_miso_shr[6:0], i_miso};
end
end
end
assign o_mosi = w_dword ? (q_data_reg[0]) : q_data_reg[7];
endmodule |
// =============================================================================
// COPYRIGHT NOTICE
// Copyright 2006 (c) Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// This confidential and proprietary software may be used only as authorised by
// a licensing agreement from Lattice Semiconductor Corporation.
// The entire notice above must be reproduced on all authorized copies and
// copies may only be made to the extent permitted by a licensing agreement from
// Lattice Semiconductor Corporation.
//
// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
// 5555 NE Moore Court 408-826-6000 (other locations)
// Hillsboro, OR 97124 web : http://www.latticesemi.com/
// U.S.A email: [email protected]
// =============================================================================/
// FILE DETAILS
// Project : LatticeMico32
// File : lm32_addsub.v
// Title : PMI adder/subtractor.
// Version : 6.1.17
// : Initial Release
// Version : 7.0SP2, 3.0
// : No Change
// Version : 3.1
// : No Change
// =============================================================================
`include "lm32_include.v"
/////////////////////////////////////////////////////
// Module interface
/////////////////////////////////////////////////////
module lm32_addsub (
// ----- Inputs -------
DataA,
DataB,
Cin,
Add_Sub,
// ----- Outputs -------
Result,
Cout
);
/////////////////////////////////////////////////////
// Inputs
/////////////////////////////////////////////////////
input [31:0] DataA;
input [31:0] DataB;
input Cin;
input Add_Sub;
/////////////////////////////////////////////////////
// Outputs
/////////////////////////////////////////////////////
output [31:0] Result;
wire [31:0] Result;
output Cout;
wire Cout;
/////////////////////////////////////////////////////
// Instantiations
/////////////////////////////////////////////////////
// Modified for Milkymist: removed non-portable instantiated block
wire [32:0] tmp_addResult = DataA + DataB + Cin;
wire [32:0] tmp_subResult = DataA - DataB - !Cin;
assign Result = (Add_Sub == 1) ? tmp_addResult[31:0] : tmp_subResult[31:0];
assign Cout = (Add_Sub == 1) ? tmp_addResult[32] : !tmp_subResult[32];
endmodule
|
/***************************************************************************************************
** fpga_nes/hw/src/cmn/vga_sync/vga_sync.v
*
* Copyright (c) 2012, Brian Bennett
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification, are permitted
* provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of conditions
* and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY
* WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Outputs HSYNC and VSYNC signals to control 640x480@60Hz VGA output. x/y outputs indicates the
* current {x, y} pixel position being displayed.
*
* Note: VSYNC/HSYNC signals are latched for stability, introducing a 1 CLK delay. The RGB
* generation circuit must be aware of this, and should latch its output as well.
***************************************************************************************************/
module vga_sync
(
input wire clk, // 100Mhz clock signal
output wire hsync, // HSYNC VGA control output
output wire vsync, // VSYNC VGA control output
output wire en, // Indicates when RGB generation circuit should enable (x,y valid)
output wire [9:0] x, // Current X position being displayed
output wire [9:0] y, // Current Y position being displayed (top = 0)
output wire [9:0] x_next, // Next X position to be displayed next clock
output wire [9:0] y_next // Next Y position to be displayed
);
//
// VGA signal timing parameters. Taken from http://tinyvga.com/vga-timing/640x480@60Hz. Note
// that this circuit uses a 25MHz clock instead of specified 25.175MHz clock. Most displays can
// cope with this out of spec behavior.
//
localparam H_DISP = 640; // Number of displayable columns
localparam H_FP = 16; // Horizontal front porch in pixel clocks
localparam H_RT = 96; // Horizontal retrace (hsync pulse) in pixel clocks
localparam H_BP = 48; // Horizontal back porch in pixel clocks
localparam V_DISP = 480; // Number of displayable rows
localparam V_FP = 10; // Vertical front porch in lines
localparam V_RT = 2; // Vertical retrace (vsync pulse) in lines
localparam V_BP = 29; // Vertical back porch in lines
// FF for mod-4 counter. Used to generate a 25MHz pixel enable signal.
reg [1:0] q_mod4_cnt;
wire [1:0] d_mod4_cnt;
// Horizontal and vertical counters. Used relative to timings specified in pixels or lines, above.
// Equivalent to x,y position when in the displayable region.
reg [9:0] q_hcnt, q_vcnt;
wire [9:0] d_hcnt, d_vcnt;
// Output signal FFs.
reg q_hsync, q_vsync, q_en;
wire d_hsync, d_vsync, d_en;
// FF update logic.
always @(posedge clk)
begin
q_mod4_cnt <= d_mod4_cnt;
q_hcnt <= d_hcnt;
q_vcnt <= d_vcnt;
q_hsync <= d_hsync;
q_vsync <= d_vsync;
q_en <= d_en;
end
wire pix_pulse; // 1 clk tick per-pixel
wire line_pulse; // 1 clk tick per-line (reset to h-pos 0)
wire screen_pulse; // 1 clk tick per-screen (reset to v-pos 0)
assign d_mod4_cnt = q_mod4_cnt + 2'h1;
assign pix_pulse = (q_mod4_cnt == 0);
assign line_pulse = pix_pulse && (q_hcnt == (H_DISP + H_FP + H_RT + H_BP - 1));
assign screen_pulse = line_pulse && (q_vcnt == (V_DISP + V_FP + V_RT + V_BP - 1));
assign d_hcnt = (line_pulse) ? 10'h000 : ((pix_pulse) ? q_hcnt + 10'h001 : q_hcnt);
assign d_vcnt = (screen_pulse) ? 10'h000 : ((line_pulse) ? q_vcnt + 10'h001 : q_vcnt);
assign d_hsync = (q_hcnt >= (H_DISP + H_FP)) && (q_hcnt < (H_DISP + H_FP + H_RT));
assign d_vsync = (q_vcnt >= (V_DISP + V_FP)) && (q_vcnt < (V_DISP + V_FP + V_RT));
assign d_en = (q_hcnt < H_DISP) && (q_vcnt < V_DISP);
// Assign output wires to appropriate FFs.
assign hsync = q_hsync;
assign vsync = q_vsync;
assign x = q_hcnt;
assign y = q_vcnt;
assign x_next = d_hcnt;
assign y_next = (y == (V_DISP + V_FP + V_RT + V_BP - 10'h001)) ? 10'h000 : (q_vcnt + 10'h001);
assign en = q_en;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:12:45 05/24/2016
// Design Name:
// Module Name: PICOBLAZE
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module PICOBLAZE(
input interrupt,
input sleep,
input clk,
input [7:0]in_port,
input rst,
output write_strobe,
output k_write_strobe,
output read_strobe,
output [7:0]out_port,
output [7:0]port_id,
output interrupt_ack
);
wire bram_enable;
wire [7:0] Dir,Dato;
wire [11:0] address;
wire rdl;
wire [17:0] instruction;
wire reset;
assign reset= rdl || rst;
kcpsm6 kcpsm6 (
.address(address),
.instruction(instruction),
.bram_enable(bram_enable),
.in_port(in_port),
.out_port(out_port),
.port_id(port_id),
.write_strobe(write_strobe),
.k_write_strobe(k_write_strobe),
.read_strobe(read_strobe),
.interrupt(interrupt),
.interrupt_ack(interrupt_ack),
.sleep(sleep),
.reset(reset),
.clk(clk)
);
hhh pBlaze (
.address(address),
.instruction(instruction),
.enable(bram_enable),
.rdl(rdl),
.clk(clk)
);
endmodule
|
//altera message_off 10230
module alt_mem_ddrx_burst_tracking
# (
// module parameter port list
parameter
CFG_BURSTCOUNT_TRACKING_WIDTH = 7,
CFG_BUFFER_ADDR_WIDTH = 6,
CFG_INT_SIZE_WIDTH = 4
)
(
// port list
ctl_clk,
ctl_reset_n,
// data burst interface
burst_ready,
burst_valid,
// burstcount counter sent to data_id_manager
burst_pending_burstcount,
burst_next_pending_burstcount,
// burstcount consumed by data_id_manager
burst_consumed_valid,
burst_counsumed_burstcount
);
// -----------------------------
// local parameter declarations
// -----------------------------
// -----------------------------
// port declaration
// -----------------------------
input ctl_clk;
input ctl_reset_n;
// data burst interface
input burst_ready;
input burst_valid;
// burstcount counter sent to data_id_manager
output [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] burst_pending_burstcount;
output [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] burst_next_pending_burstcount;
// burstcount consumed by data_id_manager
input burst_consumed_valid;
input [CFG_INT_SIZE_WIDTH-1:0] burst_counsumed_burstcount;
// -----------------------------
// port type declaration
// -----------------------------
wire ctl_clk;
wire ctl_reset_n;
// data burst interface
wire burst_ready;
wire burst_valid;
// burstcount counter sent to data_id_manager
wire [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] burst_pending_burstcount;
wire [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] burst_next_pending_burstcount;
//wire [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] burst_count_accepted;
// burstcount consumed by data_id_manager
wire burst_consumed_valid;
wire [CFG_INT_SIZE_WIDTH-1:0] burst_counsumed_burstcount;
// -----------------------------
// signal declaration
// -----------------------------
reg [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] burst_counter;
reg [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] burst_counter_next;
wire burst_accepted;
// -----------------------------
// module definition
// -----------------------------
assign burst_pending_burstcount = burst_counter;
assign burst_next_pending_burstcount = burst_counter_next;
assign burst_accepted = burst_ready & burst_valid;
always @ (*)
begin
if (burst_accepted & burst_consumed_valid)
begin
burst_counter_next = burst_counter + 1 - burst_counsumed_burstcount;
end
else if (burst_accepted)
begin
burst_counter_next = burst_counter + 1;
end
else if (burst_consumed_valid)
begin
burst_counter_next = burst_counter - burst_counsumed_burstcount;
end
else
begin
burst_counter_next = burst_counter;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
burst_counter <= 0;
end
else
begin
burst_counter <= burst_counter_next;
end
end
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_7x_v1_3_axi_basic_rx.v
// Version : 1.3
// //
// Description: //
// TRN to AXI RX module. Instantiates pipeline and null generator RX //
// submodules. //
// //
// Notes: //
// Optional notes section. //
// //
// Hierarchical: //
// axi_basic_top //
// axi_basic_rx //
// //
//----------------------------------------------------------------------------//
`timescale 1ps/1ps
module pcie_7x_v1_3_axi_basic_rx #(
parameter C_DATA_WIDTH = 128, // RX/TX interface data width
parameter C_FAMILY = "X7", // Targeted FPGA family
parameter C_ROOT_PORT = "FALSE", // PCIe block is in root port mode
parameter C_PM_PRIORITY = "FALSE", // Disable TX packet boundary thrtl
parameter TCQ = 1, // Clock to Q time
// Do not override parameters below this line
parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1, // trem/rrem width
parameter KEEP_WIDTH = C_DATA_WIDTH / 8 // KEEP width
) (
//---------------------------------------------//
// User Design I/O //
//---------------------------------------------//
// AXI RX
//-----------
output [C_DATA_WIDTH-1:0] m_axis_rx_tdata, // RX data to user
output m_axis_rx_tvalid, // RX data is valid
input m_axis_rx_tready, // RX ready for data
output [KEEP_WIDTH-1:0] m_axis_rx_tkeep, // RX strobe byte enables
output m_axis_rx_tlast, // RX data is last
output [21:0] m_axis_rx_tuser, // RX user signals
//---------------------------------------------//
// PCIe Block I/O //
//---------------------------------------------//
// TRN RX
//-----------
input [C_DATA_WIDTH-1:0] trn_rd, // RX data from block
input trn_rsof, // RX start of packet
input trn_reof, // RX end of packet
input trn_rsrc_rdy, // RX source ready
output trn_rdst_rdy, // RX destination ready
input trn_rsrc_dsc, // RX source discontinue
input [REM_WIDTH-1:0] trn_rrem, // RX remainder
input trn_rerrfwd, // RX error forward
input [6:0] trn_rbar_hit, // RX BAR hit
input trn_recrc_err, // RX ECRC error
// System
//-----------
output [2:0] np_counter, // Non-posted counter
input user_clk, // user clock from block
input user_rst // user reset from block
);
// Wires
wire null_rx_tvalid;
wire null_rx_tlast;
wire [KEEP_WIDTH-1:0] null_rx_tkeep;
wire null_rdst_rdy;
wire [4:0] null_is_eof;
//---------------------------------------------//
// RX Data Pipeline //
//---------------------------------------------//
pcie_7x_v1_3_axi_basic_rx_pipeline #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.C_FAMILY( C_FAMILY ),
.TCQ( TCQ ),
.REM_WIDTH( REM_WIDTH ),
.KEEP_WIDTH( KEEP_WIDTH )
) rx_pipeline_inst (
// Outgoing AXI TX
//-----------
.m_axis_rx_tdata( m_axis_rx_tdata ),
.m_axis_rx_tvalid( m_axis_rx_tvalid ),
.m_axis_rx_tready( m_axis_rx_tready ),
.m_axis_rx_tkeep( m_axis_rx_tkeep ),
.m_axis_rx_tlast( m_axis_rx_tlast ),
.m_axis_rx_tuser( m_axis_rx_tuser ),
// Incoming TRN RX
//-----------
.trn_rd( trn_rd ),
.trn_rsof( trn_rsof ),
.trn_reof( trn_reof ),
.trn_rsrc_rdy( trn_rsrc_rdy ),
.trn_rdst_rdy( trn_rdst_rdy ),
.trn_rsrc_dsc( trn_rsrc_dsc ),
.trn_rrem( trn_rrem ),
.trn_rerrfwd( trn_rerrfwd ),
.trn_rbar_hit( trn_rbar_hit ),
.trn_recrc_err( trn_recrc_err ),
// Null Inputs
//-----------
.null_rx_tvalid( null_rx_tvalid ),
.null_rx_tlast( null_rx_tlast ),
.null_rx_tkeep( null_rx_tkeep ),
.null_rdst_rdy( null_rdst_rdy ),
.null_is_eof( null_is_eof ),
// System
//-----------
.np_counter( np_counter ),
.user_clk( user_clk ),
.user_rst( user_rst )
);
//---------------------------------------------//
// RX Null Packet Generator //
//---------------------------------------------//
pcie_7x_v1_3_axi_basic_rx_null_gen #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.TCQ( TCQ ),
.KEEP_WIDTH( KEEP_WIDTH )
) rx_null_gen_inst (
// Inputs
//-----------
.m_axis_rx_tdata( m_axis_rx_tdata ),
.m_axis_rx_tvalid( m_axis_rx_tvalid ),
.m_axis_rx_tready( m_axis_rx_tready ),
.m_axis_rx_tlast( m_axis_rx_tlast ),
.m_axis_rx_tuser( m_axis_rx_tuser ),
// Null Outputs
//-----------
.null_rx_tvalid( null_rx_tvalid ),
.null_rx_tlast( null_rx_tlast ),
.null_rx_tkeep( null_rx_tkeep ),
.null_rdst_rdy( null_rdst_rdy ),
.null_is_eof( null_is_eof ),
// System
//-----------
.user_clk( user_clk ),
.user_rst( user_rst )
);
endmodule
|
//-----------------------------------------------------------------------------
// Copyright (c) 2013 Potential Ventures Ltd
// Copyright (c) 2013 SolarFlare Communications Inc
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of Potential Ventures Ltd,
// Copyright (c) 2013 SolarFlare Communications Inc nor the
// names of its contributors may be used to endorse or promote products
// derived from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
// DISCLAIMED. IN NO EVENT SHALL POTENTIAL VENTURES LTD BE LIABLE FOR ANY
// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//-----------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module sample_module (
input clk,
output reg stream_in_ready,
input stream_in_valid,
input [7:0] stream_in_data,
input [63:0] stream_in_data_wide,
input stream_out_ready,
output reg [7:0] stream_out_data_comb,
output reg [7:0] stream_out_data_registered
);
always @(posedge clk)
stream_out_data_registered <= stream_in_data;
always @(stream_in_data)
stream_out_data_comb = stream_in_data;
always @(stream_out_ready)
stream_in_ready = stream_out_ready;
initial begin
$dumpfile("waveform.vcd");
$dumpvars(0,sample_module);
// TODO: Move into a separate test
// #500000 $fail_test("Test timed out, failing...");
end
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : PCIeGen2x8If128_axi_basic_tx_thrtl_ctl.v
// Version : 3.2
// //
// Description: //
// TX throttle controller. Anticipates back-pressure from PCIe block and //
// preemptively back-pressures user design (packet boundary throttling). //
// //
// Notes: //
// Optional notes section. //
// //
// Hierarchical: //
// axi_basic_top //
// axi_basic_tx //
// axi_basic_tx_thrtl_ctl //
// //
//----------------------------------------------------------------------------//
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module PCIeGen2x8If128_axi_basic_tx_thrtl_ctl #(
parameter C_DATA_WIDTH = 128, // RX/TX interface data width
parameter C_FAMILY = "X7", // Targeted FPGA family
parameter C_ROOT_PORT = "FALSE", // PCIe block is in root port mode
parameter TCQ = 1 // Clock to Q time
) (
// AXI TX
//-----------
input [C_DATA_WIDTH-1:0] s_axis_tx_tdata, // TX data from user
input s_axis_tx_tvalid, // TX data is valid
input [3:0] s_axis_tx_tuser, // TX user signals
input s_axis_tx_tlast, // TX data is last
// User Misc.
//-----------
input user_turnoff_ok, // Turnoff OK from user
input user_tcfg_gnt, // Send cfg OK from user
// TRN TX
//-----------
input [5:0] trn_tbuf_av, // TX buffers available
input trn_tdst_rdy, // TX destination ready
// TRN Misc.
//-----------
input trn_tcfg_req, // TX config request
output trn_tcfg_gnt, // TX config grant
input trn_lnk_up, // PCIe link up
// 7 Series/Virtex6 PM
//-----------
input [2:0] cfg_pcie_link_state, // Encoded PCIe link state
// Virtex6 PM
//-----------
input cfg_pm_send_pme_to, // PM send PME turnoff msg
input [1:0] cfg_pmcsr_powerstate, // PMCSR power state
input [31:0] trn_rdllp_data, // RX DLLP data
input trn_rdllp_src_rdy, // RX DLLP source ready
// Virtex6/Spartan6 PM
//-----------
input cfg_to_turnoff, // Turnoff request
output reg cfg_turnoff_ok, // Turnoff grant
// System
//-----------
output reg tready_thrtl, // TREADY to pipeline
input user_clk, // user clock from block
input user_rst // user reset from block
);
// Thrtl user when TBUF hits this val
localparam TBUF_AV_MIN = (C_DATA_WIDTH == 128) ? 5 :
(C_DATA_WIDTH == 64) ? 1 : 0;
// Pause user when TBUF hits this val
localparam TBUF_AV_GAP = TBUF_AV_MIN + 1;
// GAP pause time - the latency from the time a packet is accepted on the TRN
// interface to the time trn_tbuf_av from the Block will decrement.
localparam TBUF_GAP_TIME = (C_DATA_WIDTH == 128) ? 4 : 1;
// Latency time from when tcfg_gnt is asserted to when PCIe block will throttle
localparam TCFG_LATENCY_TIME = 2'd2;
// Number of pipeline stages to delay trn_tcfg_gnt. For V6 128-bit only
localparam TCFG_GNT_PIPE_STAGES = 3;
// Throttle condition registers and constants
reg lnk_up_thrtl;
wire lnk_up_trig;
wire lnk_up_exit;
reg tbuf_av_min_thrtl;
wire tbuf_av_min_trig;
reg tbuf_av_gap_thrtl;
reg [2:0] tbuf_gap_cnt;
wire tbuf_av_gap_trig;
wire tbuf_av_gap_exit;
wire gap_trig_tlast;
wire gap_trig_decr;
reg [5:0] tbuf_av_d;
reg tcfg_req_thrtl;
reg [1:0] tcfg_req_cnt;
reg trn_tdst_rdy_d;
wire tcfg_req_trig;
wire tcfg_req_exit;
reg tcfg_gnt_log;
wire pre_throttle;
wire reg_throttle;
wire exit_crit;
reg reg_tcfg_gnt;
reg trn_tcfg_req_d;
reg tcfg_gnt_pending;
wire wire_to_turnoff;
reg reg_turnoff_ok;
reg tready_thrtl_mux;
localparam LINKSTATE_L0 = 3'b000;
localparam LINKSTATE_PPM_L1 = 3'b001;
localparam LINKSTATE_PPM_L1_TRANS = 3'b101;
localparam LINKSTATE_PPM_L23R_TRANS = 3'b110;
localparam PM_ENTER_L1 = 8'h20;
localparam POWERSTATE_D0 = 2'b00;
reg ppm_L1_thrtl;
wire ppm_L1_trig;
wire ppm_L1_exit;
reg [2:0] cfg_pcie_link_state_d;
reg trn_rdllp_src_rdy_d;
reg ppm_L23_thrtl;
wire ppm_L23_trig;
reg cfg_turnoff_ok_pending;
reg reg_tlast;
// Throttle control state machine states and registers
localparam IDLE = 0;
localparam THROTTLE = 1;
reg cur_state;
reg next_state;
reg reg_axi_in_pkt;
wire axi_in_pkt;
wire axi_pkt_ending;
wire axi_throttled;
wire axi_thrtl_ok;
wire tx_ecrc_pause;
//----------------------------------------------------------------------------//
// THROTTLE REASON: PCIe link is down //
// - When to throttle: trn_lnk_up deasserted //
// - When to stop: trn_tdst_rdy assesrted //
//----------------------------------------------------------------------------//
assign lnk_up_trig = !trn_lnk_up;
assign lnk_up_exit = trn_tdst_rdy;
always @(posedge user_clk) begin
if(user_rst) begin
lnk_up_thrtl <= #TCQ 1'b1;
end
else begin
if(lnk_up_trig) begin
lnk_up_thrtl <= #TCQ 1'b1;
end
else if(lnk_up_exit) begin
lnk_up_thrtl <= #TCQ 1'b0;
end
end
end
//----------------------------------------------------------------------------//
// THROTTLE REASON: Transmit buffers depleted //
// - When to throttle: trn_tbuf_av falls to 0 //
// - When to stop: trn_tbuf_av rises above 0 again //
//----------------------------------------------------------------------------//
assign tbuf_av_min_trig = (trn_tbuf_av <= TBUF_AV_MIN);
always @(posedge user_clk) begin
if(user_rst) begin
tbuf_av_min_thrtl <= #TCQ 1'b0;
end
else begin
if(tbuf_av_min_trig) begin
tbuf_av_min_thrtl <= #TCQ 1'b1;
end
// The exit condition for tbuf_av_min_thrtl is !tbuf_av_min_trig
else begin
tbuf_av_min_thrtl <= #TCQ 1'b0;
end
end
end
//----------------------------------------------------------------------------//
// THROTTLE REASON: Transmit buffers getting low //
// - When to throttle: trn_tbuf_av falls below "gap" threshold TBUF_AV_GAP //
// - When to stop: after TBUF_GAP_TIME cycles elapse //
// //
// If we're about to run out of transmit buffers, throttle the user for a //
// few clock cycles to give the PCIe block time to catch up. This is //
// needed to compensate for latency in decrementing trn_tbuf_av in the PCIe //
// Block transmit path. //
//----------------------------------------------------------------------------//
// Detect two different scenarios for buffers getting low:
// 1) If we see a TLAST. a new packet has been inserted into the buffer, and
// we need to pause and let that packet "soak in"
assign gap_trig_tlast = (trn_tbuf_av <= TBUF_AV_GAP) &&
s_axis_tx_tvalid && tready_thrtl && s_axis_tx_tlast;
// 2) Any time tbug_avail decrements to the TBUF_AV_GAP threshold, we need to
// pause and make sure no other packets are about to soak in and cause the
// buffer availability to drop further.
assign gap_trig_decr = (trn_tbuf_av == (TBUF_AV_GAP)) &&
(tbuf_av_d == (TBUF_AV_GAP+1));
assign gap_trig_tcfg = (tcfg_req_thrtl && tcfg_req_exit);
assign tbuf_av_gap_trig = gap_trig_tlast || gap_trig_decr || gap_trig_tcfg;
assign tbuf_av_gap_exit = (tbuf_gap_cnt == 0);
always @(posedge user_clk) begin
if(user_rst) begin
tbuf_av_gap_thrtl <= #TCQ 1'b0;
tbuf_gap_cnt <= #TCQ 3'h0;
tbuf_av_d <= #TCQ 6'h00;
end
else begin
if(tbuf_av_gap_trig) begin
tbuf_av_gap_thrtl <= #TCQ 1'b1;
end
else if(tbuf_av_gap_exit) begin
tbuf_av_gap_thrtl <= #TCQ 1'b0;
end
// tbuf gap counter:
// This logic controls the length of the throttle condition when tbufs are
// getting low.
if(tbuf_av_gap_thrtl && (cur_state == THROTTLE)) begin
if(tbuf_gap_cnt > 0) begin
tbuf_gap_cnt <= #TCQ tbuf_gap_cnt - 3'd1;
end
end
else begin
tbuf_gap_cnt <= #TCQ TBUF_GAP_TIME;
end
tbuf_av_d <= #TCQ trn_tbuf_av;
end
end
//----------------------------------------------------------------------------//
// THROTTLE REASON: Block needs to send a CFG response //
// - When to throttle: trn_tcfg_req and user_tcfg_gnt asserted //
// - When to stop: after trn_tdst_rdy transitions to unasserted //
// //
// If the block needs to send a response to a CFG packet, this will cause //
// the subsequent deassertion of trn_tdst_rdy. When the user design permits, //
// grant permission to the block to service request and throttle the user. //
//----------------------------------------------------------------------------//
assign tcfg_req_trig = trn_tcfg_req && reg_tcfg_gnt;
assign tcfg_req_exit = (tcfg_req_cnt == 2'd0) && !trn_tdst_rdy_d &&
trn_tdst_rdy;
always @(posedge user_clk) begin
if(user_rst) begin
tcfg_req_thrtl <= #TCQ 1'b0;
trn_tcfg_req_d <= #TCQ 1'b0;
trn_tdst_rdy_d <= #TCQ 1'b1;
reg_tcfg_gnt <= #TCQ 1'b0;
tcfg_req_cnt <= #TCQ 2'd0;
tcfg_gnt_pending <= #TCQ 1'b0;
end
else begin
if(tcfg_req_trig) begin
tcfg_req_thrtl <= #TCQ 1'b1;
end
else if(tcfg_req_exit) begin
tcfg_req_thrtl <= #TCQ 1'b0;
end
// We need to wait the appropriate amount of time for the tcfg_gnt to
// "sink in" to the PCIe block. After that, we know that the PCIe block will
// not reassert trn_tdst_rdy until the CFG request has been serviced. If a
// new request is being service (tcfg_gnt_log == 1), then reset the timer.
if((trn_tcfg_req && !trn_tcfg_req_d) || tcfg_gnt_pending) begin
tcfg_req_cnt <= #TCQ TCFG_LATENCY_TIME;
end
else begin
if(tcfg_req_cnt > 0) begin
tcfg_req_cnt <= #TCQ tcfg_req_cnt - 2'd1;
end
end
// Make sure tcfg_gnt_log pulses once for one clock cycle for every
// cfg packet request.
if(trn_tcfg_req && !trn_tcfg_req_d) begin
tcfg_gnt_pending <= #TCQ 1'b1;
end
else if(tcfg_gnt_log) begin
tcfg_gnt_pending <= #TCQ 1'b0;
end
trn_tcfg_req_d <= #TCQ trn_tcfg_req;
trn_tdst_rdy_d <= #TCQ trn_tdst_rdy;
reg_tcfg_gnt <= #TCQ user_tcfg_gnt;
end
end
//----------------------------------------------------------------------------//
// THROTTLE REASON: Block needs to transition to low power state PPM L1 //
// - When to throttle: appropriate low power state signal asserted //
// (architecture dependent) //
// - When to stop: cfg_pcie_link_state goes to proper value (C_ROOT_PORT //
// dependent) //
// //
// If the block needs to transition to PM state PPM L1, we need to finish //
// up what we're doing and throttle immediately. //
//----------------------------------------------------------------------------//
generate
// PPM L1 signals for 7 Series in RC mode
if((C_FAMILY == "X7") && (C_ROOT_PORT == "TRUE")) begin : x7_L1_thrtl_rp
assign ppm_L1_trig = (cfg_pcie_link_state_d == LINKSTATE_L0) &&
(cfg_pcie_link_state == LINKSTATE_PPM_L1_TRANS);
assign ppm_L1_exit = cfg_pcie_link_state == LINKSTATE_PPM_L1;
end
// PPM L1 signals for 7 Series in EP mode
else if((C_FAMILY == "X7") && (C_ROOT_PORT == "FALSE")) begin : x7_L1_thrtl_ep
assign ppm_L1_trig = (cfg_pcie_link_state_d == LINKSTATE_L0) &&
(cfg_pcie_link_state == LINKSTATE_PPM_L1_TRANS);
assign ppm_L1_exit = cfg_pcie_link_state == LINKSTATE_L0;
end
// PPM L1 signals for V6 in RC mode
else if((C_FAMILY == "V6") && (C_ROOT_PORT == "TRUE")) begin : v6_L1_thrtl_rp
assign ppm_L1_trig = (trn_rdllp_data[31:24] == PM_ENTER_L1) &&
trn_rdllp_src_rdy && !trn_rdllp_src_rdy_d;
assign ppm_L1_exit = cfg_pcie_link_state == LINKSTATE_PPM_L1;
end
// PPM L1 signals for V6 in EP mode
else if((C_FAMILY == "V6") && (C_ROOT_PORT == "FALSE")) begin : v6_L1_thrtl_ep
assign ppm_L1_trig = (cfg_pmcsr_powerstate != POWERSTATE_D0);
assign ppm_L1_exit = cfg_pcie_link_state == LINKSTATE_L0;
end
// PPM L1 detection not supported for S6
else begin : s6_L1_thrtl
assign ppm_L1_trig = 1'b0;
assign ppm_L1_exit = 1'b1;
end
endgenerate
always @(posedge user_clk) begin
if(user_rst) begin
ppm_L1_thrtl <= #TCQ 1'b0;
cfg_pcie_link_state_d <= #TCQ 3'b0;
trn_rdllp_src_rdy_d <= #TCQ 1'b0;
end
else begin
if(ppm_L1_trig) begin
ppm_L1_thrtl <= #TCQ 1'b1;
end
else if(ppm_L1_exit) begin
ppm_L1_thrtl <= #TCQ 1'b0;
end
cfg_pcie_link_state_d <= #TCQ cfg_pcie_link_state;
trn_rdllp_src_rdy_d <= #TCQ trn_rdllp_src_rdy;
end
end
//----------------------------------------------------------------------------//
// THROTTLE REASON: Block needs to transition to low power state PPM L2/3 //
// - When to throttle: appropriate PM signal indicates a transition to //
// L2/3 is pending or in progress (family and role dependent) //
// - When to stop: never (the only path out of L2/3 is a full reset) //
// //
// If the block needs to transition to PM state PPM L2/3, we need to finish //
// up what we're doing and throttle when the user gives permission. //
//----------------------------------------------------------------------------//
generate
// PPM L2/3 signals for 7 Series in RC mode
if((C_FAMILY == "X7") && (C_ROOT_PORT == "TRUE")) begin : x7_L23_thrtl_rp
assign ppm_L23_trig = (cfg_pcie_link_state_d == LINKSTATE_PPM_L23R_TRANS);
assign wire_to_turnoff = 1'b0;
end
// PPM L2/3 signals for V6 in RC mode
else if((C_FAMILY == "V6") && (C_ROOT_PORT == "TRUE")) begin : v6_L23_thrtl_rp
assign ppm_L23_trig = cfg_pm_send_pme_to;
assign wire_to_turnoff = 1'b0;
end
// PPM L2/3 signals in EP mode
else begin : L23_thrtl_ep
assign ppm_L23_trig = wire_to_turnoff && reg_turnoff_ok;
// PPM L2/3 signals for 7 Series in EP mode
// For 7 Series, cfg_to_turnoff pulses once when a turnoff request is
// outstanding, so we need a "sticky" register that grabs the request.
if(C_FAMILY == "X7") begin : x7_L23_thrtl_ep
reg reg_to_turnoff;
always @(posedge user_clk) begin
if(user_rst) begin
reg_to_turnoff <= #TCQ 1'b0;
end
else begin
if(cfg_to_turnoff) begin
reg_to_turnoff <= #TCQ 1'b1;
end
end
end
assign wire_to_turnoff = reg_to_turnoff;
end
// PPM L2/3 signals for V6/S6 in EP mode
// In V6 and S6, the to_turnoff signal asserts and remains asserted until
// turnoff_ok is asserted, so a sticky reg is not necessary.
else begin : v6_s6_L23_thrtl_ep
assign wire_to_turnoff = cfg_to_turnoff;
end
always @(posedge user_clk) begin
if(user_rst) begin
reg_turnoff_ok <= #TCQ 1'b0;
end
else begin
reg_turnoff_ok <= #TCQ user_turnoff_ok;
end
end
end
endgenerate
always @(posedge user_clk) begin
if(user_rst) begin
ppm_L23_thrtl <= #TCQ 1'b0;
cfg_turnoff_ok_pending <= #TCQ 1'b0;
end
else begin
if(ppm_L23_trig) begin
ppm_L23_thrtl <= #TCQ 1'b1;
end
// Make sure cfg_turnoff_ok pulses once for one clock cycle for every
// turnoff request.
if(ppm_L23_trig && !ppm_L23_thrtl) begin
cfg_turnoff_ok_pending <= #TCQ 1'b1;
end
else if(cfg_turnoff_ok) begin
cfg_turnoff_ok_pending <= #TCQ 1'b0;
end
end
end
//----------------------------------------------------------------------------//
// Create axi_thrtl_ok. This signal determines if it's OK to throttle the //
// user design on the AXI interface. Since TREADY is registered, this signal //
// needs to assert on the cycle ~before~ we actually intend to throttle. //
// The only time it's OK to throttle when TVALID is asserted is on the first //
// beat of a new packet. Therefore, assert axi_thrtl_ok if one of the //
// is true: //
// 1) The user is not in a packet and is not starting one //
// 2) The user is just finishing a packet //
// 3) We're already throttled, so it's OK to continue throttling //
//----------------------------------------------------------------------------//
always @(posedge user_clk) begin
if(user_rst) begin
reg_axi_in_pkt <= #TCQ 1'b0;
end
else begin
if(s_axis_tx_tvalid && s_axis_tx_tlast) begin
reg_axi_in_pkt <= #TCQ 1'b0;
end
else if(tready_thrtl && s_axis_tx_tvalid) begin
reg_axi_in_pkt <= #TCQ 1'b1;
end
end
end
assign axi_in_pkt = s_axis_tx_tvalid || reg_axi_in_pkt;
assign axi_pkt_ending = s_axis_tx_tvalid && s_axis_tx_tlast;
assign axi_throttled = !tready_thrtl;
assign axi_thrtl_ok = !axi_in_pkt || axi_pkt_ending || axi_throttled;
//----------------------------------------------------------------------------//
// Throttle CTL State Machine: //
// Throttle user design when a throttle trigger (or triggers) occur. //
// Keep user throttled until all exit criteria have been met. //
//----------------------------------------------------------------------------//
// Immediate throttle signal. Used to "pounce" on a throttle opportunity when
// we're seeking one
assign pre_throttle = tbuf_av_min_trig || tbuf_av_gap_trig || lnk_up_trig
|| tcfg_req_trig || ppm_L1_trig || ppm_L23_trig;
// Registered throttle signals. Used to control throttle state machine
assign reg_throttle = tbuf_av_min_thrtl || tbuf_av_gap_thrtl || lnk_up_thrtl
|| tcfg_req_thrtl || ppm_L1_thrtl || ppm_L23_thrtl;
assign exit_crit = !tbuf_av_min_thrtl && !tbuf_av_gap_thrtl && !lnk_up_thrtl
&& !tcfg_req_thrtl && !ppm_L1_thrtl && !ppm_L23_thrtl;
always @(*) begin
case(cur_state)
// IDLE: in this state we're waiting for a trigger event to occur. As
// soon as an event occurs and the user isn't transmitting a packet, we
// throttle the PCIe block and the user and next state is THROTTLE.
IDLE: begin
if(reg_throttle && axi_thrtl_ok) begin
// Throttle user
tready_thrtl_mux = 1'b0;
next_state = THROTTLE;
// Assert appropriate grant signal depending on the throttle type.
if(tcfg_req_thrtl) begin
tcfg_gnt_log = 1'b1; // For cfg request, grant the request
cfg_turnoff_ok = 1'b0; //
end
else if(ppm_L23_thrtl) begin
tcfg_gnt_log = 1'b0; //
cfg_turnoff_ok = 1'b1; // For PM request, permit transition
end
else begin
tcfg_gnt_log = 1'b0; // Otherwise do nothing
cfg_turnoff_ok = 1'b0; //
end
end
// If there's not throttle event, do nothing
else begin
// Throttle user as soon as possible
tready_thrtl_mux = !(axi_thrtl_ok && pre_throttle);
next_state = IDLE;
tcfg_gnt_log = 1'b0;
cfg_turnoff_ok = 1'b0;
end
end
// THROTTLE: in this state the user is throttle and we're waiting for
// exit criteria, which tells us that the throttle event is over. When
// the exit criteria is satisfied, de-throttle the user and next state
// is IDLE.
THROTTLE: begin
if(exit_crit) begin
// Dethrottle user
tready_thrtl_mux = !pre_throttle;
next_state = IDLE;
end
else begin
// Throttle user
tready_thrtl_mux = 1'b0;
next_state = THROTTLE;
end
// Assert appropriate grant signal depending on the throttle type.
if(tcfg_req_thrtl && tcfg_gnt_pending) begin
tcfg_gnt_log = 1'b1; // For cfg request, grant the request
cfg_turnoff_ok = 1'b0; //
end
else if(cfg_turnoff_ok_pending) begin
tcfg_gnt_log = 1'b0; //
cfg_turnoff_ok = 1'b1; // For PM request, permit transition
end
else begin
tcfg_gnt_log = 1'b0; // Otherwise do nothing
cfg_turnoff_ok = 1'b0; //
end
end
default: begin
tready_thrtl_mux = 1'b0;
next_state = IDLE;
tcfg_gnt_log = 1'b0;
cfg_turnoff_ok = 1'b0;
end
endcase
end
// Synchronous logic
always @(posedge user_clk) begin
if(user_rst) begin
// Throttle user by default until link comes up
cur_state <= #TCQ THROTTLE;
reg_tlast <= #TCQ 1'b0;
tready_thrtl <= #TCQ 1'b0;
end
else begin
cur_state <= #TCQ next_state;
tready_thrtl <= #TCQ tready_thrtl_mux && !tx_ecrc_pause;
reg_tlast <= #TCQ s_axis_tx_tlast;
end
end
// For X7, the PCIe block will generate the ECRC for a packet if trn_tecrc_gen
// is asserted at SOF. In this case, the Block needs an extra data beat to
// calculate the ECRC, but only if the following conditions are met:
// 1) there is no empty DWORDS at the end of the packet
// (i.e. packet length % C_DATA_WIDTH == 0)
//
// 2) There isn't a ECRC in the TLP already, as indicated by the TD bit in the
// TLP header
//
// If both conditions are met, the Block will stall the TRN interface for one
// data beat after EOF. We need to predict this stall and preemptively stall the
// User for one beat.
generate
if(C_FAMILY == "X7") begin : ecrc_pause_enabled
wire tx_ecrc_pkt;
reg reg_tx_ecrc_pkt;
wire [1:0] packet_fmt;
wire packet_td;
wire [2:0] header_len;
wire [9:0] payload_len;
wire [13:0] packet_len;
wire pause_needed;
// Grab necessary packet fields
assign packet_fmt = s_axis_tx_tdata[30:29];
assign packet_td = s_axis_tx_tdata[15];
// Calculate total packet length
assign header_len = packet_fmt[0] ? 3'd4 : 3'd3;
assign payload_len = packet_fmt[1] ? s_axis_tx_tdata[9:0] : 10'h0;
assign packet_len = {10'h000, header_len} + {4'h0, payload_len};
// Determine if packet a ECRC pause is needed
if(C_DATA_WIDTH == 128) begin : packet_len_check_128
assign pause_needed = (packet_len[1:0] == 2'b00) && !packet_td;
end
else begin : packet_len_check_64
assign pause_needed = (packet_len[0] == 1'b0) && !packet_td;
end
// Create flag to alert TX pipeline to insert a stall
assign tx_ecrc_pkt = s_axis_tx_tuser[0] && pause_needed &&
tready_thrtl && s_axis_tx_tvalid && !reg_axi_in_pkt;
always @(posedge user_clk) begin
if(user_rst) begin
reg_tx_ecrc_pkt <= #TCQ 1'b0;
end
else begin
if(tx_ecrc_pkt && !s_axis_tx_tlast) begin
reg_tx_ecrc_pkt <= #TCQ 1'b1;
end
else if(tready_thrtl && s_axis_tx_tvalid && s_axis_tx_tlast) begin
reg_tx_ecrc_pkt <= #TCQ 1'b0;
end
end
end
// Insert the stall now
assign tx_ecrc_pause = ((tx_ecrc_pkt || reg_tx_ecrc_pkt) &&
s_axis_tx_tlast && s_axis_tx_tvalid && tready_thrtl);
end
else begin : ecrc_pause_disabled
assign tx_ecrc_pause = 1'b0;
end
endgenerate
// Logic for 128-bit single cycle bug fix.
// This tcfg_gnt pipeline addresses an issue with 128-bit V6 designs where a
// single cycle packet transmitted simultaneously with an assertion of tcfg_gnt
// from AXI Basic causes the packet to be dropped. The packet drop occurs
// because the 128-bit shim doesn't know about the tcfg_req/gnt, and therefor
// isn't expecting trn_tdst_rdy to go low. Since the 128-bit shim does throttle
// prediction just as we do, it ignores the value of trn_tdst_rdy, and
// ultimately drops the packet when transmitting the packet to the block.
generate
if(C_DATA_WIDTH == 128 && C_FAMILY == "V6") begin : tcfg_gnt_pipeline
genvar stage;
reg tcfg_gnt_pipe [TCFG_GNT_PIPE_STAGES:0];
// Create a configurable depth FF delay pipeline
for(stage = 0; stage < TCFG_GNT_PIPE_STAGES; stage = stage + 1)
begin : tcfg_gnt_pipeline_stage
always @(posedge user_clk) begin
if(user_rst) begin
tcfg_gnt_pipe[stage] <= #TCQ 1'b0;
end
else begin
// For stage 0, insert the actual tcfg_gnt signal from logic
if(stage == 0) begin
tcfg_gnt_pipe[stage] <= #TCQ tcfg_gnt_log;
end
// For stages 1+, chain together
else begin
tcfg_gnt_pipe[stage] <= #TCQ tcfg_gnt_pipe[stage - 1];
end
end
end
// tcfg_gnt output to block assigned the last pipeline stage
assign trn_tcfg_gnt = tcfg_gnt_pipe[TCFG_GNT_PIPE_STAGES-1];
end
end
else begin : tcfg_gnt_no_pipeline
// For all other architectures, no pipeline delay needed for tcfg_gnt
assign trn_tcfg_gnt = tcfg_gnt_log;
end
endgenerate
endmodule
|
module test();
localparam signed snv1 = 4'd1;
localparam signed [2:0] s3v1 = 4'd1;
localparam signed [3:0] s4v1 = 4'd1;
localparam signed [4:0] s5v1 = 4'd1;
localparam signed snv15 = 4'd15;
localparam signed [2:0] s3v15 = 4'd15;
localparam signed [3:0] s4v15 = 4'd15;
localparam signed [4:0] s5v15 = 4'd15;
localparam signed snvm1 = -4'sd1;
localparam signed [2:0] s3vm1 = -4'sd1;
localparam signed [3:0] s4vm1 = -4'sd1;
localparam signed [4:0] s5vm1 = -4'sd1;
localparam signed snrm1 = -1.0;
localparam signed [2:0] s3rm1 = -1.0;
localparam signed [3:0] s4rm1 = -1.0;
localparam signed [4:0] s5rm1 = -1.0;
localparam nnv1 = 4'd1;
localparam [2:0] u3v1 = 4'd1;
localparam [3:0] u4v1 = 4'd1;
localparam [4:0] u5v1 = 4'd1;
localparam nnv15 = 4'd15;
localparam [2:0] u3v15 = 4'd15;
localparam [3:0] u4v15 = 4'd15;
localparam [4:0] u5v15 = 4'd15;
localparam nnvm1 = -4'sd1;
localparam [2:0] u3vm1 = -4'sd1;
localparam [3:0] u4vm1 = -4'sd1;
localparam [4:0] u5vm1 = -4'sd1;
localparam nnrm1 = -1.0;
localparam [2:0] u3rm1 = -1.0;
localparam [3:0] u4rm1 = -1.0;
localparam [4:0] u5rm1 = -1.0;
reg fail = 0;
reg match;
initial begin
match = ($bits(snv1) == 4) && (snv1 === 1);
$display("snv1 : %2d (%0d`b%b) %c", snv1, $bits(snv1), snv1, match ? " " : "*");
fail = fail || !match;
match = ($bits(s3v1) == 3) && (s3v1 === 1);
$display("s3v1 : %2d (%0d`b%b) %c", s3v1 , $bits(s3v1), s3v1, match ? " " : "*");
fail = fail || !match;
match = ($bits(s4v1) == 4) && (s4v1 === 1);
$display("s4v1 : %2d (%0d`b%b) %c", s4v1 , $bits(s4v1), s4v1, match ? " " : "*");
fail = fail || !match;
match = ($bits(s5v1) == 5) && (s5v1 === 1);
$display("s5v1 : %2d (%0d`b%b) %c", s5v1 , $bits(s5v1), s5v1, match ? " " : "*");
fail = fail || !match;
match = ($bits(snv15) == 4) && (snv15 === -1);
$display("snv15 : %2d (%0d`b%b) %c", snv15, $bits(snv15), snv15, match ? " " : "*");
fail = fail || !match;
match = ($bits(s3v15) == 3) && (s3v15 === -1);
$display("s3v15 : %2d (%0d`b%b) %c", s3v15, $bits(s3v15), s3v15, match ? " " : "*");
fail = fail || !match;
match = ($bits(s4v15) == 4) && (s4v15 === -1);
$display("s4v15 : %2d (%0d`b%b) %c", s4v15, $bits(s4v15), s4v15, match ? " " : "*");
fail = fail || !match;
match = ($bits(s5v15) == 5) && (s5v15 === 15);
$display("s5v15 : %2d (%0d`b%b) %c", s5v15, $bits(s5v15), s5v15, match ? " " : "*");
fail = fail || !match;
match = ($bits(snvm1) == 4) && (snvm1 === -1);
$display("snvm1 : %2d (%0d`b%b) %c", snvm1, $bits(snvm1), snvm1, match ? " " : "*");
fail = fail || !match;
match = ($bits(s3vm1) == 3) && (s3vm1 === -1);
$display("s3vm1 : %2d (%0d`b%b) %c", s3vm1, $bits(s3vm1), s3vm1, match ? " " : "*");
fail = fail || !match;
match = ($bits(s4vm1) == 4) && (s4vm1 === -1);
$display("s4vm1 : %2d (%0d`b%b) %c", s4vm1, $bits(s4vm1), s4vm1, match ? " " : "*");
fail = fail || !match;
match = ($bits(s5vm1) == 5) && (s5vm1 === -1);
$display("s5vm1 : %2d (%0d`b%b) %c", s5vm1, $bits(s5vm1), s5vm1, match ? " " : "*");
fail = fail || !match;
match = (snrm1 == -1);
$display("snrm1 : %4.1f %c", snrm1, match ? " " : "*");
fail = fail || !match;
match = ($bits(s3rm1) == 3) && (s3rm1 === -1);
$display("s3rm1 : %2d (%0d`b%b) %c", s3rm1, $bits(s3rm1), s3rm1, match ? " " : "*");
fail = fail || !match;
match = ($bits(s4rm1) == 4) && (s4rm1 === -1);
$display("s4rm1 : %2d (%0d`b%b) %c", s4rm1, $bits(s4rm1), s4rm1, match ? " " : "*");
fail = fail || !match;
match = ($bits(s5rm1) == 5) && (s5rm1 === -1);
$display("s5rm1 : %2d (%0d`b%b) %c", s5rm1, $bits(s5rm1), s5rm1, match ? " " : "*");
fail = fail || !match;
match = ($bits(nnv1) == 4) && (nnv1 === 1);
$display("nnv1 : %2d (%0d`b%b) %c", nnv1, $bits(nnv1), nnv1, match ? " " : "*");
fail = fail || !match;
match = ($bits(u3v1) == 3) && (u3v1 === 1);
$display("u3v1 : %2d (%0d`b%b) %c", u3v1 , $bits(u3v1), u3v1, match ? " " : "*");
fail = fail || !match;
match = ($bits(u4v1) == 4) && (u4v1 === 1);
$display("u4v1 : %2d (%0d`b%b) %c", u4v1 , $bits(u4v1), u4v1, match ? " " : "*");
fail = fail || !match;
match = ($bits(u5v1) == 5) && (u5v1 === 1);
$display("u5v1 : %2d (%0d`b%b) %c", u5v1 , $bits(u5v1), u5v1, match ? " " : "*");
fail = fail || !match;
match = ($bits(nnv15) == 4) && (nnv15 === 15);
$display("nnv15 : %2d (%0d`b%b) %c", nnv15, $bits(nnv15), nnv15, match ? " " : "*");
fail = fail || !match;
match = ($bits(u3v15) == 3) && (u3v15 === 7);
$display("u3v15 : %2d (%0d`b%b) %c", u3v15, $bits(u3v15), u3v15, match ? " " : "*");
fail = fail || !match;
match = ($bits(u4v15) == 4) && (u4v15 === 15);
$display("u4v15 : %2d (%0d`b%b) %c", u4v15, $bits(u4v15), u4v15, match ? " " : "*");
fail = fail || !match;
match = ($bits(u5v15) == 5) && (u5v15 === 15);
$display("u5v15 : %2d (%0d`b%b) %c", u5v15, $bits(u5v15), u5v15, match ? " " : "*");
fail = fail || !match;
match = ($bits(nnvm1) == 4) && (nnvm1 === -1);
$display("nnvm1 : %2d (%0d`b%b) %c", nnvm1, $bits(nnvm1), nnvm1, match ? " " : "*");
fail = fail || !match;
match = ($bits(u3vm1) == 3) && (u3vm1 === 7);
$display("u3vm1 : %2d (%0d`b%b) %c", u3vm1, $bits(u3vm1), u3vm1, match ? " " : "*");
fail = fail || !match;
match = ($bits(u4vm1) == 4) && (u4vm1 === 15);
$display("u4vm1 : %2d (%0d`b%b) %c", u4vm1, $bits(u4vm1), u4vm1, match ? " " : "*");
fail = fail || !match;
match = ($bits(u5vm1) == 5) && (u5vm1 === 31);
$display("u5vm1 : %2d (%0d`b%b) %c", u5vm1, $bits(u5vm1), u5vm1, match ? " " : "*");
fail = fail || !match;
match = (nnrm1 == -1.0);
$display("nnrm1 : %4.1f %c", nnrm1, match ? " " : "*");
fail = fail || !match;
match = ($bits(u3rm1) == 3) && (u3rm1 === 7);
$display("u3rm1 : %2d (%0d`b%b) %c", u3rm1, $bits(u3rm1), u3rm1, match ? " " : "*");
fail = fail || !match;
match = ($bits(u4rm1) == 4) && (u4rm1 === 15);
$display("u4rm1 : %2d (%0d`b%b) %c", u4rm1, $bits(u4rm1), u4rm1, match ? " " : "*");
fail = fail || !match;
match = ($bits(u5rm1) == 5) && (u5rm1 === 31);
$display("u5rm1 : %2d (%0d`b%b) %c", u5rm1, $bits(u5rm1), u5rm1, match ? " " : "*");
fail = fail || !match;
if (fail)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
// part of NeoGS project
//
// (c) NedoPC 2007-2008
//
// modelling is in tb_dma2.*
module dma_sequencer(
clk,
rst_n,
addr,
wd,
rd,
req,
rnw,
ack,
done,
dma_req,
dma_addr,
dma_rnw,
dma_wd,
dma_rd,
dma_ack,
dma_end
);
parameter DEVNUM = 4;
input clk;
input rst_n;
input [20:0] addr [1:DEVNUM];
input [7:0] wd [1:DEVNUM];
output reg [7:0] rd;
input [DEVNUM:1] req;
input [DEVNUM:1] rnw;
output reg dma_req;
output reg dma_rnw;
output reg [20:0] dma_addr;
output reg [7:0] dma_wd;
input [7:0] dma_rd;
input dma_ack;
input dma_end;
output reg [DEVNUM:1] ack;
output reg [DEVNUM:1] done;
reg [DEVNUM:1] muxbeg;
reg [DEVNUM:1] muxend;
reg [DEVNUM:1] muxend_in;
reg [DEVNUM:1] pri_in;
reg [DEVNUM:1] pri_out;
integer i;
always @*
for(i=1;i<=DEVNUM;i=i+1)
begin
pri_in[i] = (i==1) ? pri_out[DEVNUM] : pri_out[i-1];
pri_out[i] = ( pri_in[i] & (~req[i]) ) | muxend[i];
muxbeg[i] = pri_in[i] & req[i];
muxend_in[i] = muxbeg[i] & dma_ack;
end
always @(posedge clk, negedge rst_n)
begin
if( !rst_n )
begin
muxend[1] <= 1'b1;
for(i=2;i<=DEVNUM;i=i+1)
muxend[i] <= 1'b0;
end
else if( dma_ack )
begin
for(i=1;i<=DEVNUM;i=i+1)
muxend[i] <= muxend_in[i];
end
end
always @*
begin
rd = dma_rd;
dma_req = 1'b0;
for(i=1;i<=DEVNUM;i=i+1)
dma_req = dma_req | req[i];
dma_wd = 8'd0;
for(i=1;i<=DEVNUM;i=i+1)
dma_wd = dma_wd | ( (muxbeg[i]==1'b1) ? wd[i] : 8'd0 );
dma_addr = 21'd0;
for(i=1;i<=DEVNUM;i=i+1)
dma_addr = dma_addr | ( (muxbeg[i]==1'b1) ? addr[i] : 21'd0 );
dma_rnw = 1'b0;
for(i=1;i<=DEVNUM;i=i+1)
dma_rnw = dma_rnw | ( (muxbeg[i]==1'b1) ? rnw[i] : 1'b0 );
for(i=1;i<=DEVNUM;i=i+1)
ack[i] = (muxbeg[i]==1'b1) ? dma_ack : 1'b0;
for(i=1;i<=DEVNUM;i=i+1)
done[i] = (muxend[i]==1'b1) ? dma_end : 1'b0;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Wilson Snyder.
// bug511
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
wire [7:0] au;
wire [7:0] as;
Test1 test1 (.au);
Test2 test2 (.as);
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] result=%x %x\n",$time, au, as);
`endif
if (au != 'h12) $stop;
if (as != 'h02) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
module Test1 (output [7:0] au);
wire [7:0] b;
wire signed [3:0] c;
// verilator lint_off WIDTH
assign c=-1; // 'hf
assign b=3; // 'h3
assign au=b+c; // 'h12
// verilator lint_on WIDTH
endmodule
module Test2 (output [7:0] as);
wire signed [7:0] b;
wire signed [3:0] c;
// verilator lint_off WIDTH
assign c=-1; // 'hf
assign b=3; // 'h3
assign as=b+c; // 'h12
// verilator lint_on WIDTH
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 04/26/2016 09:14:57 AM
// Design Name:
// Module Name: FSM_test
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module FSM_test
(
input wire clk,
input wire rst,
input wire ready_op,
input wire max_tick_address,
input wire max_tick_ch,
input wire TX_DONE,
output reg beg_op,
output reg ack_op,
output reg load_address,
output reg enab_address,
output reg enab_ch,
output reg load_ch,
output reg TX_START
);
//symbolic state declaration
localparam [3:0] est0 = 4'b0000,
est1 = 4'b0001,
est2 = 4'b0010,
est3 = 4'b0011,
est4 = 4'b0100,
est5 = 4'b0101,
est6 = 4'b0110,
est7 = 4'b0111,
est8 = 4'b1000,
est9 = 4'b1001,
est10 = 4'b1010,
est11 = 4'b1011;
//signal declaration
reg [3:0] state_reg, state_next; // Guardan el estado actual y el estado futuro, respectivamente.
//state register
always @( posedge clk, posedge rst)
begin
if(rst) // Si hay reset, el estado actual es el estado inicial.
state_reg <= est0;
else //Si no hay reset el estado actual es igual al estado siguiente.
state_reg <= state_next;
end
//next-state logic and output logic
always @*
begin
state_next = state_reg; // default state : the same
//declaration of default outputs.
beg_op = 1'b0;
ack_op = 1'b0;
load_address = 1'b0;
enab_address = 1'b0;
enab_ch = 1'b0;
load_ch = 1'b0;
TX_START = 1'b0;
case(state_reg)
est0:
begin
state_next = est1;
end
est1:
begin
load_address = 1'b1;
enab_address = 1'b1;
state_next = est2;
end
est2:
begin
beg_op = 1'b1;
state_next=est3;
end
est3:
begin
beg_op = 1'b1;
enab_ch = 1'b1;
load_ch = 1'b1;
state_next=est4;
end
est4:
begin
if(ready_op)
state_next=est5;
else
state_next=est4;
end
est5:
begin
state_next=est6;
end
est6:
begin
TX_START = 1'b1;
state_next=est7;
end
est7:
begin
if(TX_DONE)
if(max_tick_ch)
state_next=est9;
else
begin
state_next=est8;
end
else
state_next=est7;
end
est8:
begin
enab_ch = 1'b1;
state_next=est5;
end
est9:
begin
if(max_tick_address)
state_next=est11;
else
begin
state_next=est10;
end
end
est10:
begin
enab_address = 1'b1;
ack_op = 1'b1;
state_next=est2;
end
est11:
begin
state_next=est11;
end
default:
state_next=est0;
endcase
end
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module mult_wide (
input wire CLK,
input wire [ 8:0] A0,
input wire [ 8:0] A1,
input wire [ 8:0] A2,
input wire [ 8:0] A3,
input wire [ 8:0] B0,
input wire [ 8:0] B1,
input wire [ 8:0] B2,
input wire [ 8:0] B3,
input wire [53:0] C,
output wire [53:0] Z
);
reg [8:0] ra0;
always @(posedge CLK)
ra0 <= A0;
reg [8:0] rb0;
always @(posedge CLK)
rb0 <= B0;
reg [8:0] rb2;
always @(posedge CLK)
rb2 <= B2;
MULTADDSUB9X9WIDE # (
.REGINPUTAB0("BYPASS"),
.REGINPUTAB1("BYPASS"),
.REGINPUTAB2("BYPASS"),
.REGINPUTAB3("BYPASS"),
.REGINPUTC("BYPASS"),
.REGADDSUB("BYPASS"),
.REGLOADC("BYPASS"),
.REGLOADC2("BYPASS"),
.REGPIPELINE("BYPASS"),
.REGOUTPUT("REGISTER")
) mult (
.A0 (ra0),
.A1 (A1),
.A2 (A2),
.A3 (A3),
.B0 (rb0),
.B1 (B1),
.B2 (rb2),
.B3 (B3),
.C (C),
.Z (Z),
.LOADC (1'b0),
.ADDSUB (4'hF),
.SIGNED (1'b1),
);
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008-2008 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
wire [9:0] I1 = crc[9:0];
wire [9:0] I2 = crc[19:10];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [9:0] S; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.S (S[9:0]),
// Inputs
.I1 (I1[9:0]),
.I2 (I2[9:0]));
wire [63:0] result = {32'h0, 22'h0, S};
`define EXPECTED_SUM 64'h24c38b77b0fcc2e7
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
S,
// Inputs
I1, I2
);
input [9:0] I1/*verilator public*/;
input [9:0] I2/*verilator public*/;
output reg [9:0] S/*verilator public*/;
always @(I1 or I2)
t2(I1,I2,S);
task t1;
input In1,In2;
output Sum;
Sum = In1 ^ In2;
endtask
task t2;
input[9:0] In1,In2;
output [9:0] Sum;
integer I;
begin
for (I=0;I<10;I=I+1)
t1(In1[I],In2[I],Sum[I]);
end
endtask
endmodule
|
module global_resource_table
(/*AUTOARG*/
// Outputs
grt_cam_up_valid, grt_cam_up_wg_count, grt_cam_up_cu_id,
grt_cam_up_vgpr_strt, grt_cam_up_vgpr_size, grt_cam_up_sgpr_strt,
grt_cam_up_sgpr_size, grt_cam_up_lds_strt, grt_cam_up_lds_size,
grt_cam_up_gds_strt, grt_cam_up_gds_size, grt_wg_alloc_done,
grt_wg_alloc_wgid, grt_wg_alloc_cu_id, grt_wg_dealloc_done,
grt_wg_dealloc_wgid, grt_wg_dealloc_cu_id,
// Inputs
clk, rst, gpu_interface_cu_id, gpu_interface_dealloc_wg_id,
dis_controller_wg_alloc_valid, dis_controller_wg_dealloc_valid,
allocator_wg_id_out, allocator_wf_count, allocator_cu_id_out,
allocator_vgpr_start_out, allocator_sgpr_start_out,
allocator_lds_start_out, allocator_gds_start_out,
allocator_vgpr_size_out, allocator_sgpr_size_out,
allocator_lds_size_out, allocator_gds_size_out
);
parameter NUMBER_CU = 64;
parameter CU_ID_WIDTH = 6;
parameter RES_TABLE_ADDR_WIDTH = 3;
parameter VGPR_ID_WIDTH = 10;
parameter NUMBER_VGPR_SLOTS = 1024;
parameter SGPR_ID_WIDTH = 10;
parameter NUMBER_SGPR_SLOTS = 1024;
parameter LDS_ID_WIDTH = 10;
parameter NUMBER_LDS_SLOTS = 1024;
parameter WG_ID_WIDTH = 10;
parameter WF_COUNT_WIDTH = 4;
parameter WG_SLOT_ID_WIDTH = 6;
parameter NUMBER_WF_SLOTS = 40;
parameter GDS_ID_WIDTH = 10;
parameter GDS_SIZE = 1024;
localparam NUMBER_RES_TABLES = 2**RES_TABLE_ADDR_WIDTH;
localparam CU_PER_RES_TABLES = NUMBER_CU/NUMBER_RES_TABLES;
// width of all parameters same for start and size
input clk, rst;
input [CU_ID_WIDTH-1:0] gpu_interface_cu_id;
input [WG_ID_WIDTH-1:0] gpu_interface_dealloc_wg_id;
input dis_controller_wg_alloc_valid;
input dis_controller_wg_dealloc_valid;
input [WG_ID_WIDTH-1:0] allocator_wg_id_out;
input [WF_COUNT_WIDTH-1:0] allocator_wf_count;
input [CU_ID_WIDTH-1 :0] allocator_cu_id_out;
input [VGPR_ID_WIDTH-1 :0] allocator_vgpr_start_out;
input [SGPR_ID_WIDTH-1 :0] allocator_sgpr_start_out;
input [LDS_ID_WIDTH-1 :0] allocator_lds_start_out;
input [GDS_ID_WIDTH-1 :0] allocator_gds_start_out;
input [VGPR_ID_WIDTH :0] allocator_vgpr_size_out;
input [SGPR_ID_WIDTH :0] allocator_sgpr_size_out;
input [LDS_ID_WIDTH :0] allocator_lds_size_out;
input [GDS_ID_WIDTH :0] allocator_gds_size_out;
output grt_cam_up_valid;
output [WG_SLOT_ID_WIDTH:0] grt_cam_up_wg_count;
output [CU_ID_WIDTH-1 :0] grt_cam_up_cu_id;
output [VGPR_ID_WIDTH-1 :0] grt_cam_up_vgpr_strt;
output [VGPR_ID_WIDTH :0] grt_cam_up_vgpr_size;
output [SGPR_ID_WIDTH-1 :0] grt_cam_up_sgpr_strt;
output [SGPR_ID_WIDTH :0] grt_cam_up_sgpr_size;
output [LDS_ID_WIDTH-1 :0] grt_cam_up_lds_strt;
output [LDS_ID_WIDTH :0] grt_cam_up_lds_size;
output [GDS_ID_WIDTH-1 :0] grt_cam_up_gds_strt;
output [GDS_ID_WIDTH :0] grt_cam_up_gds_size;
// Outputs to controller - allocated wf
output grt_wg_alloc_done;
output [WG_ID_WIDTH-1:0] grt_wg_alloc_wgid;
output [CU_ID_WIDTH-1 :0] grt_wg_alloc_cu_id;
output grt_wg_dealloc_done;
output [WG_ID_WIDTH-1:0] grt_wg_dealloc_wgid;
output [CU_ID_WIDTH-1 :0] grt_wg_dealloc_cu_id;
// Input flop
reg [CU_ID_WIDTH-1:0] gpu_interface_cu_id_i;
reg [WG_ID_WIDTH-1:0] gpu_interface_dealloc_wg_id_i;
reg dis_controller_wg_alloc_valid_i;
reg dis_controller_wg_dealloc_valid_i;
reg [WF_COUNT_WIDTH-1:0] allocator_wf_count_i;
reg [WG_ID_WIDTH-1:0] allocator_wg_id_out_i;
reg [CU_ID_WIDTH-1 :0] allocator_cu_id_out_i;
reg [VGPR_ID_WIDTH-1 :0] allocator_vgpr_start_out_i;
reg [SGPR_ID_WIDTH-1 :0] allocator_sgpr_start_out_i;
reg [LDS_ID_WIDTH-1 :0] allocator_lds_start_out_i;
reg [GDS_ID_WIDTH-1 :0] allocator_gds_start_out_i;
reg [VGPR_ID_WIDTH :0] allocator_vgpr_size_out_i;
reg [SGPR_ID_WIDTH :0] allocator_sgpr_size_out_i;
reg [LDS_ID_WIDTH :0] allocator_lds_size_out_i;
reg [GDS_ID_WIDTH :0] allocator_gds_size_out_i;
reg alloc_res_en_dec;
reg dealloc_res_en_dec;
reg [CU_ID_WIDTH-RES_TABLE_ADDR_WIDTH-1:0] cu_id_dec,
cu_id_dec_comb;
reg [WG_ID_WIDTH-1:0] wg_id_dec,
wg_id_dec_comb;
reg [WF_COUNT_WIDTH-1:0] allocator_wf_count_dec;
reg [VGPR_ID_WIDTH-1 :0] allocator_vgpr_start_out_dec;
reg [SGPR_ID_WIDTH-1 :0] allocator_sgpr_start_out_dec;
reg [LDS_ID_WIDTH-1 :0] allocator_lds_start_out_dec;
reg [GDS_ID_WIDTH-1 :0] allocator_gds_start_out_dec;
reg [VGPR_ID_WIDTH :0] allocator_vgpr_size_out_dec;
reg [SGPR_ID_WIDTH :0] allocator_sgpr_size_out_dec;
reg [LDS_ID_WIDTH :0] allocator_lds_size_out_dec;
reg [GDS_ID_WIDTH :0] allocator_gds_size_out_dec;
reg [RES_TABLE_ADDR_WIDTH-1:0] res_tbl_selected_addr,
res_tbl_selected_addr_comb;
reg [NUMBER_RES_TABLES-1:0] res_tbl_selected_dec;
reg [NUMBER_RES_TABLES-1:0] res_tbl_selected_dec_comb;
// stage for wg_slot_id calculation
reg res_tbl_in_is_allocating, res_tbl_in_is_deallocating;
reg [NUMBER_RES_TABLES-1:0] res_tbl_in_alloc_res_en,
res_tbl_in_dealloc_res_en;
reg [RES_TABLE_ADDR_WIDTH-1:0] res_tbl_in_tbl_addr;
reg [CU_ID_WIDTH-RES_TABLE_ADDR_WIDTH-1:0] res_tbl_in_cu_id;
wire [WG_SLOT_ID_WIDTH-1:0] res_tbl_in_wg_slot_id;
reg [VGPR_ID_WIDTH-1 :0] res_tbl_in_vgpr_start_out;
reg [SGPR_ID_WIDTH-1 :0] res_tbl_in_sgpr_start_out;
reg [LDS_ID_WIDTH-1 :0] res_tbl_in_lds_start_out;
reg [VGPR_ID_WIDTH :0] res_tbl_in_vgpr_size_out;
reg [SGPR_ID_WIDTH :0] res_tbl_in_sgpr_size_out;
reg [LDS_ID_WIDTH :0] res_tbl_in_lds_size_out;
reg [GDS_ID_WIDTH :0] res_tbl_in_gds_size_out;
// Output from res table/pri encoder
wire [NUMBER_RES_TABLES-1:0] vgpr_res_table_done,
vgpr_res_table_waiting;
wire [(VGPR_ID_WIDTH+1)*NUMBER_RES_TABLES-1:0] vgpr_biggest_space_size;
wire [VGPR_ID_WIDTH*NUMBER_RES_TABLES-1:0] vgpr_biggest_space_addr;
wire [NUMBER_RES_TABLES-1:0] sgpr_res_table_done,
sgpr_res_table_waiting;
wire [(SGPR_ID_WIDTH+1)*NUMBER_RES_TABLES-1:0] sgpr_biggest_space_size;
wire [SGPR_ID_WIDTH*NUMBER_RES_TABLES-1:0] sgpr_biggest_space_addr;
wire [NUMBER_RES_TABLES-1:0] lds_res_table_done,
lds_res_table_waiting;
wire [(LDS_ID_WIDTH+1)*NUMBER_RES_TABLES-1:0] lds_biggest_space_size;
wire [LDS_ID_WIDTH*NUMBER_RES_TABLES-1:0] lds_biggest_space_addr;
reg [NUMBER_RES_TABLES-1:0] all_res_done_array,
res_done_array_select_comb,
res_done_array_select;
reg res_done_valid,
res_done_valid_comb,
res_done_valid_final;
reg [RES_TABLE_ADDR_WIDTH-1:0] res_done_tbl_addr,
res_done_tbl_addr_comb;
// output of the res_tbl mux
wire [WG_SLOT_ID_WIDTH-1:0] mux_tbl_wg_slot_id;
wire [WG_SLOT_ID_WIDTH:0] mux_tbl_wf_count;
wire [VGPR_ID_WIDTH:0] mux_tbl_vgpr_biggest_space_size;
wire [VGPR_ID_WIDTH-1:0] mux_tbl_vgpr_biggest_space_addr;
wire [SGPR_ID_WIDTH:0] mux_tbl_sgpr_biggest_space_size;
wire [SGPR_ID_WIDTH-1:0] mux_tbl_sgpr_biggest_space_addr;
wire [LDS_ID_WIDTH:0] mux_tbl_lds_biggest_space_size;
wire [LDS_ID_WIDTH-1:0] mux_tbl_lds_biggest_space_addr;
wire [GDS_ID_WIDTH:0] mux_tbl_gds_biggest_space_size;
reg [RES_TABLE_ADDR_WIDTH-1:0] mux_tbl_tbl_addr;
// inflight info
localparam INFLIGHT_OP_WIDTH = CU_ID_WIDTH-RES_TABLE_ADDR_WIDTH+WG_ID_WIDTH+2;
wire inflight_alloc_en, inflight_dealloc_en;
wire [CU_ID_WIDTH-RES_TABLE_ADDR_WIDTH-1:0] inflight_cu_id;
wire [WG_ID_WIDTH-1:0] inflight_wg_id;
/////////////////////////////////////////////////////////////////////////////////
// Output assignments
/////////////////////////////////////////////////////////////////////////////////
assign grt_cam_up_valid = (inflight_alloc_en | inflight_dealloc_en) &
res_done_valid_final;
assign grt_cam_up_wg_count = mux_tbl_wf_count;
assign grt_cam_up_cu_id = {mux_tbl_tbl_addr,inflight_cu_id};
assign grt_cam_up_vgpr_strt = mux_tbl_vgpr_biggest_space_addr;
assign grt_cam_up_vgpr_size = mux_tbl_vgpr_biggest_space_size;
assign grt_cam_up_sgpr_strt = mux_tbl_sgpr_biggest_space_addr;
assign grt_cam_up_sgpr_size = mux_tbl_sgpr_biggest_space_size;
assign grt_cam_up_lds_strt = mux_tbl_lds_biggest_space_addr;
assign grt_cam_up_lds_size = mux_tbl_lds_biggest_space_size;
assign grt_cam_up_gds_size = mux_tbl_gds_biggest_space_size;
// Assigns to controller - allocated wf
assign grt_wg_alloc_done = inflight_alloc_en & res_done_valid_final;
assign grt_wg_alloc_wgid = inflight_wg_id;
assign grt_wg_alloc_cu_id = {mux_tbl_tbl_addr,inflight_cu_id};
assign grt_wg_dealloc_done = inflight_dealloc_en & res_done_valid_final ;
assign grt_wg_dealloc_wgid = inflight_wg_id;
assign grt_wg_dealloc_cu_id = {mux_tbl_tbl_addr,inflight_cu_id};
/////////////////////////////////////////////////////////////////////////////////
// inflight op table
/////////////////////////////////////////////////////////////////////////////////
ram_2_port
#(
// Parameters
.WORD_SIZE (INFLIGHT_OP_WIDTH),
.ADDR_SIZE (RES_TABLE_ADDR_WIDTH),
.NUM_WORDS (NUMBER_RES_TABLES))
inflight_op_table
(
// Outputs
.rd_word ({inflight_cu_id,inflight_wg_id,
inflight_alloc_en,inflight_dealloc_en}),
// Inputs
.rst (rst),
.clk (clk),
.wr_en (alloc_res_en_dec |
dealloc_res_en_dec),
.wr_addr (res_tbl_selected_addr),
.wr_word ({cu_id_dec,wg_id_dec,
alloc_res_en_dec,
dealloc_res_en_dec} ),
.rd_en (1'b1),
.rd_addr (res_done_tbl_addr));
/////////////////////////////////////////////////////////////////////////////////
// tables for each resource
/////////////////////////////////////////////////////////////////////////////////
wg_resource_table
#(
// Parameters
.NUMBER_CU (NUMBER_CU),
.CU_ID_WIDTH (CU_ID_WIDTH),
.WG_ID_WIDTH (WG_ID_WIDTH),
.WG_SLOT_ID_WIDTH (WG_SLOT_ID_WIDTH),
.NUMBER_WF_SLOTS (NUMBER_WF_SLOTS),
.RES_TABLE_ADDR_WIDTH (RES_TABLE_ADDR_WIDTH))
wg_res_tbl
(
// Outputs
.wg_res_tbl_wg_slot_id (res_tbl_in_wg_slot_id),
.wg_res_tbl_wg_count_out (mux_tbl_wf_count),
// Inputs
.rst (rst),
.clk (clk),
.wg_res_tbl_alloc_en (alloc_res_en_dec),
.wg_res_tbl_dealloc_en (dealloc_res_en_dec),
.wg_res_tbl_cu_id ({res_tbl_selected_addr,
cu_id_dec}),
.wg_res_tbl_wg_id (wg_id_dec),
.wg_res_tbl_alloc_wg_wf_count (allocator_wf_count_dec),
.wg_res_tbl_inflight_res_tbl_id (res_done_tbl_addr));
gds_resource_table
#(
// Parameters
.NUMBER_CU (NUMBER_CU),
.CU_ID_WIDTH (CU_ID_WIDTH),
.RES_TABLE_ADDR_WIDTH (RES_TABLE_ADDR_WIDTH),
.WG_SLOT_ID_WIDTH (WG_SLOT_ID_WIDTH),
.NUMBER_WF_SLOTS (NUMBER_WF_SLOTS),
.GDS_ID_WIDTH (GDS_ID_WIDTH),
.GDS_SIZE (GDS_SIZE))
gds_res_tbl
(
// Outputs
.gds_res_tbl_wg_gds_size (mux_tbl_gds_biggest_space_size),
// Inputs
.rst (rst),
.clk (clk),
.gds_res_tbl_alloc_en (|res_tbl_in_alloc_res_en),
.gds_res_tbl_dealloc_en (|res_tbl_in_dealloc_res_en),
.gds_res_tbl_cu_id ({res_tbl_in_tbl_addr,res_tbl_in_cu_id}),
.gds_res_tbl_wg_id (res_tbl_in_wg_slot_id),
.gds_res_tbl_alloc_gds_size (res_tbl_in_gds_size_out),
.gds_res_tbl_inflight_res_tbl_id (res_done_tbl_addr));
resource_table
#(
// Parameters
.CU_ID_WIDTH (CU_ID_WIDTH-RES_TABLE_ADDR_WIDTH),
.NUMBER_CU (CU_PER_RES_TABLES),
.WG_SLOT_ID_WIDTH (WG_SLOT_ID_WIDTH),
.NUMBER_WF_SLOTS_PER_CU (NUMBER_WF_SLOTS),
.RES_ID_WIDTH (VGPR_ID_WIDTH),
.NUMBER_RES_SLOTS (NUMBER_VGPR_SLOTS))
vgpr_table [NUMBER_RES_TABLES-1:0]
(
// Outputs
.res_table_done (vgpr_res_table_done),
.cam_biggest_space_size (vgpr_biggest_space_size),
.cam_biggest_space_addr (vgpr_biggest_space_addr),
// Inputs
.clk (clk),
.rst (rst),
.alloc_res_en (res_tbl_in_alloc_res_en),
.dealloc_res_en (res_tbl_in_dealloc_res_en),
.alloc_cu_id (res_tbl_in_cu_id),
.dealloc_cu_id (res_tbl_in_cu_id),
.alloc_wg_slot_id (res_tbl_in_wg_slot_id),
.dealloc_wg_slot_id (res_tbl_in_wg_slot_id),
.alloc_res_size (res_tbl_in_vgpr_size_out),
.alloc_res_start (res_tbl_in_vgpr_start_out));
resource_update_buffer
#(
// Parameters
.RES_ID_WIDTH (VGPR_ID_WIDTH),
.RES_TABLE_ADDR_WIDTH (RES_TABLE_ADDR_WIDTH),
.NUMBER_RES_TABLES (NUMBER_RES_TABLES))
vgpr_up_buffer
(
// Outputs
.res_table_waiting (vgpr_res_table_waiting),
.serviced_cam_biggest_space_size (mux_tbl_vgpr_biggest_space_size),
.serviced_cam_biggest_space_addr (mux_tbl_vgpr_biggest_space_addr),
// Inputs
.clk (clk),
.rst (rst),
.res_table_done (vgpr_res_table_done),
.res_tbl_cam_biggest_space_size (vgpr_biggest_space_size),
.res_tbl_cam_biggest_space_addr (vgpr_biggest_space_addr),
.serviced_table (res_done_array_select));
resource_table
#(
// Parameters
.CU_ID_WIDTH (CU_ID_WIDTH-RES_TABLE_ADDR_WIDTH),
.NUMBER_CU (CU_PER_RES_TABLES),
.WG_SLOT_ID_WIDTH (WG_SLOT_ID_WIDTH),
.NUMBER_WF_SLOTS_PER_CU (NUMBER_WF_SLOTS),
.RES_ID_WIDTH (SGPR_ID_WIDTH),
.NUMBER_RES_SLOTS (NUMBER_SGPR_SLOTS))
sgpr_table [NUMBER_RES_TABLES-1:0]
(
// Outputs
.res_table_done (sgpr_res_table_done),
.cam_biggest_space_size (sgpr_biggest_space_size),
.cam_biggest_space_addr (sgpr_biggest_space_addr),
// Inputs
.clk (clk),
.rst (rst),
.alloc_res_en (res_tbl_in_alloc_res_en),
.dealloc_res_en (res_tbl_in_dealloc_res_en),
.alloc_cu_id (res_tbl_in_cu_id),
.dealloc_cu_id (res_tbl_in_cu_id),
.alloc_wg_slot_id (res_tbl_in_wg_slot_id),
.dealloc_wg_slot_id (res_tbl_in_wg_slot_id),
.alloc_res_size (res_tbl_in_sgpr_size_out),
.alloc_res_start (res_tbl_in_sgpr_start_out));
resource_update_buffer
#(
// Parameters
.RES_ID_WIDTH (SGPR_ID_WIDTH),
.RES_TABLE_ADDR_WIDTH (RES_TABLE_ADDR_WIDTH),
.NUMBER_RES_TABLES (NUMBER_RES_TABLES))
sgpr_up_buffer
(
// Outputs
.res_table_waiting (sgpr_res_table_waiting),
.serviced_cam_biggest_space_size (mux_tbl_sgpr_biggest_space_size),
.serviced_cam_biggest_space_addr (mux_tbl_sgpr_biggest_space_addr),
// Inputs
.clk (clk),
.rst (rst),
.res_table_done (sgpr_res_table_done),
.res_tbl_cam_biggest_space_size (sgpr_biggest_space_size),
.res_tbl_cam_biggest_space_addr (sgpr_biggest_space_addr),
.serviced_table (res_done_array_select));
resource_table
#(
// Parameters
.CU_ID_WIDTH (CU_ID_WIDTH-RES_TABLE_ADDR_WIDTH),
.NUMBER_CU (CU_PER_RES_TABLES),
.WG_SLOT_ID_WIDTH (WG_SLOT_ID_WIDTH),
.NUMBER_WF_SLOTS_PER_CU (NUMBER_WF_SLOTS),
.RES_ID_WIDTH (LDS_ID_WIDTH),
.NUMBER_RES_SLOTS (NUMBER_LDS_SLOTS))
lds_table [NUMBER_RES_TABLES-1:0]
(
// Outputs
.res_table_done (lds_res_table_done),
.cam_biggest_space_size (lds_biggest_space_size),
.cam_biggest_space_addr (lds_biggest_space_addr),
// Inputs
.clk (clk),
.rst (rst),
.alloc_res_en (res_tbl_in_alloc_res_en),
.dealloc_res_en (res_tbl_in_dealloc_res_en),
.alloc_cu_id (res_tbl_in_cu_id),
.dealloc_cu_id (res_tbl_in_cu_id),
.alloc_wg_slot_id (res_tbl_in_wg_slot_id),
.dealloc_wg_slot_id (res_tbl_in_wg_slot_id),
.alloc_res_size (res_tbl_in_lds_size_out),
.alloc_res_start (res_tbl_in_lds_start_out));
resource_update_buffer
#(
// Parameters
.RES_ID_WIDTH (LDS_ID_WIDTH),
.RES_TABLE_ADDR_WIDTH (RES_TABLE_ADDR_WIDTH),
.NUMBER_RES_TABLES (NUMBER_RES_TABLES))
lds_up_buffer
(
// Outputs
.res_table_waiting (lds_res_table_waiting),
.serviced_cam_biggest_space_size (mux_tbl_lds_biggest_space_size),
.serviced_cam_biggest_space_addr (mux_tbl_lds_biggest_space_addr),
// Inputs
.clk (clk),
.rst (rst),
.res_table_done (lds_res_table_done),
.res_tbl_cam_biggest_space_size (lds_biggest_space_size),
.res_tbl_cam_biggest_space_addr (lds_biggest_space_addr),
.serviced_table (res_done_array_select));
always @( posedge clk or posedge rst ) begin
if (rst) begin
// Input flops
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
all_res_done_array <= {NUMBER_RES_TABLES{1'b0}};
alloc_res_en_dec <= 1'h0;
allocator_cu_id_out_i <= {CU_ID_WIDTH{1'b0}};
allocator_gds_size_out_dec <= {(1+(GDS_ID_WIDTH)){1'b0}};
allocator_gds_size_out_i <= {(1+(GDS_ID_WIDTH)){1'b0}};
allocator_gds_start_out_dec <= {GDS_ID_WIDTH{1'b0}};
allocator_gds_start_out_i <= {GDS_ID_WIDTH{1'b0}};
allocator_lds_size_out_dec <= {(1+(LDS_ID_WIDTH)){1'b0}};
allocator_lds_size_out_i <= {(1+(LDS_ID_WIDTH)){1'b0}};
allocator_lds_start_out_dec <= {LDS_ID_WIDTH{1'b0}};
allocator_lds_start_out_i <= {LDS_ID_WIDTH{1'b0}};
allocator_sgpr_size_out_dec <= {(1+(SGPR_ID_WIDTH)){1'b0}};
allocator_sgpr_size_out_i <= {(1+(SGPR_ID_WIDTH)){1'b0}};
allocator_sgpr_start_out_dec <= {SGPR_ID_WIDTH{1'b0}};
allocator_sgpr_start_out_i <= {SGPR_ID_WIDTH{1'b0}};
allocator_vgpr_size_out_dec <= {(1+(VGPR_ID_WIDTH)){1'b0}};
allocator_vgpr_size_out_i <= {(1+(VGPR_ID_WIDTH)){1'b0}};
allocator_vgpr_start_out_dec <= {VGPR_ID_WIDTH{1'b0}};
allocator_vgpr_start_out_i <= {VGPR_ID_WIDTH{1'b0}};
allocator_wf_count_dec <= {(1+(WG_SLOT_ID_WIDTH)){1'b0}};
allocator_wf_count_i <= {(1+(WG_SLOT_ID_WIDTH)){1'b0}};
allocator_wg_id_out_i <= {WG_ID_WIDTH{1'b0}};
cu_id_dec <= {(1+(CU_ID_WIDTH-RES_TABLE_ADDR_WIDTH-1)){1'b0}};
dealloc_res_en_dec <= 1'h0;
dis_controller_wg_alloc_valid_i <= 1'h0;
dis_controller_wg_dealloc_valid_i <= 1'h0;
gpu_interface_cu_id_i <= {CU_ID_WIDTH{1'b0}};
gpu_interface_dealloc_wg_id_i <= {WG_ID_WIDTH{1'b0}};
mux_tbl_tbl_addr <= {RES_TABLE_ADDR_WIDTH{1'b0}};
res_done_array_select <= {NUMBER_RES_TABLES{1'b0}};
res_done_tbl_addr <= {RES_TABLE_ADDR_WIDTH{1'b0}};
res_done_valid <= 1'h0;
res_done_valid_final <= 1'h0;
res_tbl_in_alloc_res_en <= {NUMBER_RES_TABLES{1'b0}};
res_tbl_in_cu_id <= {(1+(CU_ID_WIDTH-RES_TABLE_ADDR_WIDTH-1)){1'b0}};
res_tbl_in_dealloc_res_en <= {NUMBER_RES_TABLES{1'b0}};
res_tbl_in_gds_size_out <= {(1+(GDS_ID_WIDTH)){1'b0}};
res_tbl_in_lds_size_out <= {(1+(LDS_ID_WIDTH)){1'b0}};
res_tbl_in_lds_start_out <= {LDS_ID_WIDTH{1'b0}};
res_tbl_in_sgpr_size_out <= {(1+(SGPR_ID_WIDTH)){1'b0}};
res_tbl_in_sgpr_start_out <= {SGPR_ID_WIDTH{1'b0}};
res_tbl_in_tbl_addr <= {RES_TABLE_ADDR_WIDTH{1'b0}};
res_tbl_in_vgpr_size_out <= {(1+(VGPR_ID_WIDTH)){1'b0}};
res_tbl_in_vgpr_start_out <= {VGPR_ID_WIDTH{1'b0}};
res_tbl_selected_addr <= {RES_TABLE_ADDR_WIDTH{1'b0}};
res_tbl_selected_dec <= {NUMBER_RES_TABLES{1'b0}};
wg_id_dec <= {WG_ID_WIDTH{1'b0}};
// End of automatics
end
else begin
///////////////////////////////
// Input flop
///////////////////////////////
gpu_interface_cu_id_i <= gpu_interface_cu_id;
gpu_interface_dealloc_wg_id_i <= gpu_interface_dealloc_wg_id;
dis_controller_wg_alloc_valid_i <= dis_controller_wg_alloc_valid;
dis_controller_wg_dealloc_valid_i <= dis_controller_wg_dealloc_valid;
allocator_wg_id_out_i <= allocator_wg_id_out;
allocator_cu_id_out_i <= allocator_cu_id_out;
allocator_wf_count_i <= allocator_wf_count;
allocator_vgpr_start_out_i <= allocator_vgpr_start_out;
allocator_sgpr_start_out_i <= allocator_sgpr_start_out;
allocator_lds_start_out_i <= allocator_lds_start_out;
allocator_gds_start_out_i <= allocator_gds_start_out;
allocator_vgpr_size_out_i <= allocator_vgpr_size_out;
allocator_sgpr_size_out_i <= allocator_sgpr_size_out;
allocator_lds_size_out_i <= allocator_lds_size_out;
allocator_gds_size_out_i <= allocator_gds_size_out;
// decoder flops
alloc_res_en_dec <= dis_controller_wg_alloc_valid_i;
dealloc_res_en_dec <= dis_controller_wg_dealloc_valid_i;
cu_id_dec <= cu_id_dec_comb;
wg_id_dec <= wg_id_dec_comb;
allocator_wf_count_dec <= allocator_wf_count_i;
allocator_vgpr_start_out_dec <= allocator_vgpr_start_out_i;
allocator_sgpr_start_out_dec <= allocator_sgpr_start_out_i;
allocator_lds_start_out_dec <= allocator_lds_start_out_i;
allocator_gds_start_out_dec <= allocator_gds_start_out_i;
allocator_vgpr_size_out_dec <= allocator_vgpr_size_out_i;
allocator_sgpr_size_out_dec <= allocator_sgpr_size_out_i;
allocator_lds_size_out_dec <= allocator_lds_size_out_i;
allocator_gds_size_out_dec <= allocator_gds_size_out_i;
res_tbl_selected_dec <= res_tbl_selected_dec_comb;
res_tbl_selected_addr <= res_tbl_selected_addr_comb;
// Inputs for the resource tables
res_tbl_in_alloc_res_en <= {NUMBER_RES_TABLES{alloc_res_en_dec}} & res_tbl_selected_dec;
res_tbl_in_dealloc_res_en <= {NUMBER_RES_TABLES{dealloc_res_en_dec}} & res_tbl_selected_dec;
res_tbl_in_cu_id <= cu_id_dec;
res_tbl_in_tbl_addr <= res_tbl_selected_addr;
res_tbl_in_vgpr_start_out <= allocator_vgpr_start_out_dec;
res_tbl_in_sgpr_start_out <= allocator_sgpr_start_out_dec;
res_tbl_in_lds_start_out <= allocator_lds_start_out_dec;
res_tbl_in_vgpr_size_out <= allocator_vgpr_size_out_dec;
res_tbl_in_sgpr_size_out <= allocator_sgpr_size_out_dec;
res_tbl_in_lds_size_out <= allocator_lds_size_out_dec;
res_tbl_in_gds_size_out <= allocator_gds_size_out_dec;
///////////////////////////////////////
// resource_tables output
///////////////////////////////////////
// All that are waiting except the one that we selected last
all_res_done_array <= vgpr_res_table_waiting & sgpr_res_table_waiting &
lds_res_table_waiting & (~res_done_array_select);
res_done_tbl_addr <= res_done_tbl_addr_comb;
res_done_array_select <= res_done_array_select_comb;
res_done_valid <= res_done_valid_comb;
// Last stage
res_done_valid_final <= res_done_valid;
// used to reconstruct the cuid
mux_tbl_tbl_addr <= res_done_tbl_addr;
end // else: !if(rst)
end // always @ ( posedge clk or posedge rst )
// Several always blocks for a faster simulation
//////////////////////////////////////////////////////////
// CU id decoder for the resource table en
//////////////////////////////////////////////////////////
always @ ( /*AUTOSENSE*/allocator_cu_id_out_i
or allocator_wg_id_out_i
or dis_controller_wg_alloc_valid_i
or dis_controller_wg_dealloc_valid_i
or gpu_interface_cu_id_i or gpu_interface_dealloc_wg_id_i) begin : CU_DECODER_TABLE_IN
reg [RES_TABLE_ADDR_WIDTH-1:0] tbl_addr_dec_comb;
tbl_addr_dec_comb = 0;
cu_id_dec_comb = 0;
wg_id_dec_comb = 0;
res_tbl_selected_dec_comb = 0;
if(dis_controller_wg_alloc_valid_i) begin
cu_id_dec_comb = allocator_cu_id_out_i[CU_ID_WIDTH-
RES_TABLE_ADDR_WIDTH-1:0];
tbl_addr_dec_comb = allocator_cu_id_out_i[CU_ID_WIDTH-1:
CU_ID_WIDTH-RES_TABLE_ADDR_WIDTH];
wg_id_dec_comb = allocator_wg_id_out_i;
res_tbl_selected_dec_comb[tbl_addr_dec_comb] = 1'b1;
res_tbl_selected_addr_comb = tbl_addr_dec_comb;
end
else if(dis_controller_wg_dealloc_valid_i) begin
cu_id_dec_comb = gpu_interface_cu_id_i[CU_ID_WIDTH-
RES_TABLE_ADDR_WIDTH-1:0];
tbl_addr_dec_comb = gpu_interface_cu_id_i[CU_ID_WIDTH-1:
CU_ID_WIDTH-RES_TABLE_ADDR_WIDTH];
wg_id_dec_comb = gpu_interface_dealloc_wg_id_i;
res_tbl_selected_dec_comb[tbl_addr_dec_comb] = 1'b1;
res_tbl_selected_addr_comb = tbl_addr_dec_comb;
end
else begin
cu_id_dec_comb = 0;
wg_id_dec_comb = 0;
res_tbl_selected_dec_comb = 0;
res_tbl_selected_addr_comb = 0;
end
end // always @ (...
//////////////////////////////////////////////////////////
// priority encoder that selects the res table to service
//////////////////////////////////////////////////////////
always @ ( /*AUTOSENSE*/all_res_done_array or res_done_array_select) begin : PRI_ENC_SERVICED_TABLE
integer res_done_pri_enc_i;
reg [RES_TABLE_ADDR_WIDTH-1:0] res_done_found_tbl;
reg res_done_found_tbl_valid;
res_done_array_select_comb = 0;
res_done_tbl_addr_comb = 0;
res_done_valid_comb = 1'b0;
res_done_found_tbl_valid = 1'b0;
res_done_found_tbl = 0;
// priority encoder to to select the serviced table and
// encoder to calculate the cu_id
for (res_done_pri_enc_i=0; res_done_pri_enc_i<NUMBER_RES_TABLES;
res_done_pri_enc_i = res_done_pri_enc_i + 1) begin
if(all_res_done_array[res_done_pri_enc_i] &
!res_done_array_select[res_done_pri_enc_i]) begin
if(!res_done_found_tbl_valid) begin
res_done_found_tbl = res_done_pri_enc_i;
res_done_found_tbl_valid = 1'b1;
end
end
end // for (res_done_pri_enc_i=; res_done_pri_enc_i<NUMBER_RES_TABLES;...
res_done_valid_comb = res_done_found_tbl_valid;
if( res_done_found_tbl_valid ) begin
res_done_tbl_addr_comb = res_done_found_tbl;
res_done_array_select_comb[res_done_found_tbl] = 1'b1;
end
end // always @ (...
endmodule // global_resource_table
|
// test_parse2synthtrans_behavopt_1_test.v
module f1_test(in, out, clk, reset);
input in, reset;
output reg out;
input clk;
reg signed [3:0] a;
reg signed [3:0] b;
reg signed [3:0] c;
reg [5:0] d;
reg [5:0] e;
always @(clk or reset) begin
a = -4;
b = 2;
c = a + b;
d = a + b + c;
d = d*d;
if(b)
e = d*d;
else
e = d + d;
end
endmodule
// test_parse2synthtrans_case_1_test.v
module f2_demultiplexer1_to_4 (out0, out1, out2, out3, in, s1, s0);
output out0, out1, out2, out3;
reg out0, out1, out2, out3;
input in;
input s1, s0;
reg [3:0] encoding;
reg [1:0] state;
always @(encoding) begin
case (encoding)
4'bxx11: state = 1;
4'bx0xx: state = 3;
4'b11xx: state = 4;
4'bx1xx: state = 2;
4'bxx1x: state = 1;
4'bxxx1: state = 0;
default: state = 0;
endcase
end
always @(encoding) begin
case (encoding)
4'b0000: state = 1;
default: state = 0;
endcase
end
endmodule
// test_parse2synthtrans_contassign_1_test.v
module f3_test(in, out);
input wire in;
output out;
assign out = (in+in);
assign out = 74;
endmodule
// test_parse2synthtrans_module_basic0_test.v
module f4_test;
endmodule
// test_parse2synthtrans_operators_1_test.v
module f5_test(in, out);
input in;
output out;
parameter p1 = 10;
parameter p2 = 5;
assign out = +p1;
assign out = -p2;
assign out = p1 + p2;
assign out = p1 - p2;
endmodule
// test_parse2synthtrans_param_1_test.v
module f6_test(in, out);
input in;
output out;
parameter p = 10;
assign out = p;
endmodule
// test_parse2synthtrans_port_scalar_1_test.v
module f7_test(in, out, io);
inout io;
output out;
input in;
endmodule
// test_parse2synthtrans_port_vector_1_test.v
module f8_test(in1, in2, out1, out2, io1, io2);
inout [1:0] io1;
inout [0:1] io2;
output [1:0] out1;
output [0:1] out2;
input [1:0] in1;
input [0:1] in2;
endmodule
// test_parse2synthtrans_v2k_comb_logic_sens_list_test.v
module f9_test(q, d, clk, reset);
output reg q;
input d, clk, reset;
always @ (posedge clk, negedge reset)
if(!reset) q <= 0;
else q <= d;
endmodule
|
(** * Hoare2: Hoare Logic, Part II *)
Require Export Hoare.
(* ####################################################### *)
(** * Decorated Programs *)
(** The beauty of Hoare Logic is that it is _compositional_ --
the structure of proofs exactly follows the structure of programs.
This suggests that we can record the essential ideas of a proof
informally (leaving out some low-level calculational details) by
decorating programs with appropriate assertions around each
statement. Such a _decorated program_ carries with it
an (informal) proof of its own correctness. *)
(** For example, here is a complete decorated program: *)
(**
{{ True }} ->>
{{ m = m }}
X ::= m;;
{{ X = m }} ->>
{{ X = m /\ p = p }}
Z ::= p;
{{ X = m /\ Z = p }} ->>
{{ Z - X = p - m }}
WHILE X <> 0 DO
{{ Z - X = p - m /\ X <> 0 }} ->>
{{ (Z - 1) - (X - 1) = p - m }}
Z ::= Z - 1;;
{{ Z - (X - 1) = p - m }}
X ::= X - 1
{{ Z - X = p - m }}
END;
{{ Z - X = p - m /\ ~ (X <> 0) }} ->>
{{ Z = p - m }}
*)
(** Concretely, a decorated program consists of the program text
interleaved with assertions. To check that a decorated program
represents a valid proof, we check that each individual command is
_locally consistent_ with its accompanying assertions in the
following sense: *)
(**
- [SKIP] is locally consistent if its precondition and
postcondition are the same:
{{ P }}
SKIP
{{ P }}
*)
(**
- The sequential composition of [c1] and [c2] is locally
consistent (with respect to assertions [P] and [R]) if [c1] is
locally consistent (with respect to [P] and [Q]) and [c2] is
locally consistent (with respect to [Q] and [R]):
{{ P }}
c1;;
{{ Q }}
c2
{{ R }}
*)
(**
- An assignment is locally consistent if its precondition is
the appropriate substitution of its postcondition:
{{ P [X |-> a] }}
X ::= a
{{ P }}
*)
(**
- A conditional is locally consistent (with respect to assertions
[P] and [Q]) if the assertions at the top of its "then" and
"else" branches are exactly [P /\ b] and [P /\ ~b] and if its "then"
branch is locally consistent (with respect to [P /\ b] and [Q])
and its "else" branch is locally consistent (with respect to
[P /\ ~b] and [Q]):
{{ P }}
IFB b THEN
{{ P /\ b }}
c1
{{ Q }}
ELSE
{{ P /\ ~b }}
c2
{{ Q }}
FI
{{ Q }}
*)
(**
- A while loop with precondition [P] is locally consistent if its
postcondition is [P /\ ~b] and if the pre- and postconditions of
its body are exactly [P /\ b] and [P]:
{{ P }}
WHILE b DO
{{ P /\ b }}
c1
{{ P }}
END
{{ P /\ ~b }}
*)
(**
- A pair of assertions separated by [->>] is locally consistent if
the first implies the second (in all states):
{{ P }} ->>
{{ P' }}
This corresponds to the application of [hoare_consequence] and
is the only place in a decorated program where checking if
decorations are correct is not fully mechanical and syntactic,
but involves logical and/or arithmetic reasoning.
*)
(** We have seen above how _verifying_ the correctness of a
given proof involves checking that every single command is locally
consistent with the accompanying assertions. If we are instead
interested in _finding_ a proof for a given specification we need
to discover the right assertions. This can be done in an almost
automatic way, with the exception of finding loop invariants,
which is the subject of in the next section. In the reminder of
this section we explain in detail how to construct decorations for
several simple programs that don't involve non-trivial loop
invariants. *)
(* ####################################################### *)
(** ** Example: Swapping Using Addition and Subtraction *)
(** Here is a program that swaps the values of two variables using
addition and subtraction (instead of by assigning to a temporary
variable).
X ::= X + Y;;
Y ::= X - Y;;
X ::= X - Y
We can prove using decorations that this program is correct --
i.e., it always swaps the values of variables [X] and [Y]. *)
(**
(1) {{ X = m /\ Y = n }} ->>
(2) {{ (X + Y) - ((X + Y) - Y) = n /\ (X + Y) - Y = m }}
X ::= X + Y;;
(3) {{ X - (X - Y) = n /\ X - Y = m }}
Y ::= X - Y;;
(4) {{ X - Y = n /\ Y = m }}
X ::= X - Y
(5) {{ X = n /\ Y = m }}
The decorations were constructed as follows:
- We begin with the undecorated program (the unnumbered lines).
- We then add the specification -- i.e., the outer
precondition (1) and postcondition (5). In the precondition we
use auxiliary variables (parameters) [m] and [n] to remember
the initial values of variables [X] and respectively [Y], so
that we can refer to them in the postcondition (5).
- We work backwards mechanically starting from (5) all the way
to (2). At each step, we obtain the precondition of the
assignment from its postcondition by substituting the assigned
variable with the right-hand-side of the assignment. For
instance, we obtain (4) by substituting [X] with [X - Y]
in (5), and (3) by substituting [Y] with [X - Y] in (4).
- Finally, we verify that (1) logically implies (2) -- i.e.,
that the step from (1) to (2) is a valid use of the law of
consequence. For this we substitute [X] by [m] and [Y] by [n]
and calculate as follows:
(m + n) - ((m + n) - n) = n /\ (m + n) - n = m
(m + n) - m = n /\ m = m
n = n /\ m = m
(Note that, since we are working with natural numbers, not
fixed-size machine integers, we don't need to worry about the
possibility of arithmetic overflow anywhere in this argument.)
*)
(* ####################################################### *)
(** ** Example: Simple Conditionals *)
(** Here is a simple decorated program using conditionals:
(1) {{True}}
IFB X <= Y THEN
(2) {{True /\ X <= Y}} ->>
(3) {{(Y - X) + X = Y \/ (Y - X) + Y = X}}
Z ::= Y - X
(4) {{Z + X = Y \/ Z + Y = X}}
ELSE
(5) {{True /\ ~(X <= Y) }} ->>
(6) {{(X - Y) + X = Y \/ (X - Y) + Y = X}}
Z ::= X - Y
(7) {{Z + X = Y \/ Z + Y = X}}
FI
(8) {{Z + X = Y \/ Z + Y = X}}
These decorations were constructed as follows:
- We start with the outer precondition (1) and postcondition (8).
- We follow the format dictated by the [hoare_if] rule and copy the
postcondition (8) to (4) and (7). We conjoin the precondition (1)
with the guard of the conditional to obtain (2). We conjoin (1)
with the negated guard of the conditional to obtain (5).
- In order to use the assignment rule and obtain (3), we substitute
[Z] by [Y - X] in (4). To obtain (6) we substitute [Z] by [X - Y]
in (7).
- Finally, we verify that (2) implies (3) and (5) implies (6). Both
of these implications crucially depend on the ordering of [X] and
[Y] obtained from the guard. For instance, knowing that [X <= Y]
ensures that subtracting [X] from [Y] and then adding back [X]
produces [Y], as required by the first disjunct of (3). Similarly,
knowing that [~(X <= Y)] ensures that subtracting [Y] from [X] and
then adding back [Y] produces [X], as needed by the second
disjunct of (6). Note that [n - m + m = n] does _not_ hold for
arbitrary natural numbers [n] and [m] (for example, [3 - 5 + 5 =
5]). *)
(** **** Exercise: 2 stars (if_minus_plus_reloaded) *)
(** Fill in valid decorations for the following program:
{{ True }}
IFB X <= Y THEN
{{ }} ->>
{{ }}
Z ::= Y - X
{{ }}
ELSE
{{ }} ->>
{{ }}
Y ::= X + Z
{{ }}
FI
{{ Y = X + Z }}
*)
(** [] *)
(* ####################################################### *)
(** ** Example: Reduce to Zero (Trivial Loop) *)
(** Here is a [WHILE] loop that is so simple it needs no
invariant (i.e., the invariant [True] will do the job).
(1) {{ True }}
WHILE X <> 0 DO
(2) {{ True /\ X <> 0 }} ->>
(3) {{ True }}
X ::= X - 1
(4) {{ True }}
END
(5) {{ True /\ X = 0 }} ->>
(6) {{ X = 0 }}
The decorations can be constructed as follows:
- Start with the outer precondition (1) and postcondition (6).
- Following the format dictated by the [hoare_while] rule, we copy
(1) to (4). We conjoin (1) with the guard to obtain (2) and with
the negation of the guard to obtain (5). Note that, because the
outer postcondition (6) does not syntactically match (5), we need a
trivial use of the consequence rule from (5) to (6).
- Assertion (3) is the same as (4), because [X] does not appear in
[4], so the substitution in the assignment rule is trivial.
- Finally, the implication between (2) and (3) is also trivial.
*)
(** From this informal proof, it is easy to read off a formal proof
using the Coq versions of the Hoare rules. Note that we do _not_
unfold the definition of [hoare_triple] anywhere in this proof --
the idea is to use the Hoare rules as a "self-contained" logic for
reasoning about programs. *)
Definition reduce_to_zero' : com :=
WHILE BNot (BEq (AId X) (ANum 0)) DO
X ::= AMinus (AId X) (ANum 1)
END.
Theorem reduce_to_zero_correct' :
{{fun st => True}}
reduce_to_zero'
{{fun st => st X = 0}}.
Proof.
unfold reduce_to_zero'.
(* First we need to transform the postcondition so
that hoare_while will apply. *)
eapply hoare_consequence_post.
apply hoare_while.
Case "Loop body preserves invariant".
(* Need to massage precondition before [hoare_asgn] applies *)
eapply hoare_consequence_pre. apply hoare_asgn.
(* Proving trivial implication (2) ->> (3) *)
intros st [HT Hbp]. unfold assn_sub. apply I.
Case "Invariant and negated guard imply postcondition".
intros st [Inv GuardFalse].
unfold bassn in GuardFalse. simpl in GuardFalse.
(* SearchAbout helps to find the right lemmas *)
SearchAbout [not true].
rewrite not_true_iff_false in GuardFalse.
SearchAbout [negb false].
rewrite negb_false_iff in GuardFalse.
SearchAbout [beq_nat true].
apply beq_nat_true in GuardFalse.
apply GuardFalse. Qed.
(* ####################################################### *)
(** ** Example: Division *)
(** The following Imp program calculates the integer division and
remainder of two numbers [m] and [n] that are arbitrary constants
in the program.
X ::= m;;
Y ::= 0;;
WHILE n <= X DO
X ::= X - n;;
Y ::= Y + 1
END;
In other words, if we replace [m] and [n] by concrete numbers and
execute the program, it will terminate with the variable [X] set
to the remainder when [m] is divided by [n] and [Y] set to the
quotient. *)
(** In order to give a specification to this program we need to
remember that dividing [m] by [n] produces a reminder [X] and a
quotient [Y] so that [n * Y + X = m /\ X < n].
It turns out that we get lucky with this program and don't have to
think very hard about the loop invariant: the invariant is the
just first conjunct [n * Y + X = m], so we use that to decorate
the program.
(1) {{ True }} ->>
(2) {{ n * 0 + m = m }}
X ::= m;;
(3) {{ n * 0 + X = m }}
Y ::= 0;;
(4) {{ n * Y + X = m }}
WHILE n <= X DO
(5) {{ n * Y + X = m /\ n <= X }} ->>
(6) {{ n * (Y + 1) + (X - n) = m }}
X ::= X - n;;
(7) {{ n * (Y + 1) + X = m }}
Y ::= Y + 1
(8) {{ n * Y + X = m }}
END
(9) {{ n * Y + X = m /\ X < n }}
Assertions (4), (5), (8), and (9) are derived mechanically from
the invariant and the loop's guard. Assertions (8), (7), and (6)
are derived using the assignment rule going backwards from (8) to
(6). Assertions (4), (3), and (2) are again backwards applications
of the assignment rule.
Now that we've decorated the program it only remains to check that
the two uses of the consequence rule are correct -- i.e., that (1)
implies (2) and that (5) implies (6). This is indeed the case, so
we have a valid decorated program.
*)
(* ####################################################### *)
(** * Finding Loop Invariants *)
(** Once the outermost precondition and postcondition are chosen, the
only creative part in verifying programs with Hoare Logic is
finding the right loop invariants. The reason this is difficult
is the same as the reason that doing inductive mathematical proofs
requires creativity: strengthening the loop invariant (or the
induction hypothesis) means that you have a stronger assumption to
work with when trying to establish the postcondition of the loop
body (complete the induction step of the proof), but it also means
that the loop body postcondition itself is harder to prove!
This section is dedicated to teaching you how to approach the
challenge of finding loop invariants using a series of examples
and exercises. *)
(** ** Example: Slow Subtraction *)
(** The following program subtracts the value of [X] from the value of
[Y] by repeatedly decrementing both [X] and [Y]. We want to verify its
correctness with respect to the following specification:
{{ X = m /\ Y = n }}
WHILE X <> 0 DO
Y ::= Y - 1;;
X ::= X - 1
END
{{ Y = n - m }}
To verify this program we need to find an invariant [I] for the
loop. As a first step we can leave [I] as an unknown and build a
_skeleton_ for the proof by applying backward the rules for local
consistency. This process leads to the following skeleton:
(1) {{ X = m /\ Y = n }} ->> (a)
(2) {{ I }}
WHILE X <> 0 DO
(3) {{ I /\ X <> 0 }} ->> (c)
(4) {{ I[X |-> X-1][Y |-> Y-1] }}
Y ::= Y - 1;;
(5) {{ I[X |-> X-1] }}
X ::= X - 1
(6) {{ I }}
END
(7) {{ I /\ ~(X <> 0) }} ->> (b)
(8) {{ Y = n - m }}
By examining this skeleton, we can see that any valid [I] will
have to respect three conditions:
- (a) it must be weak enough to be implied by the loop's
precondition, i.e. (1) must imply (2);
- (b) it must be strong enough to imply the loop's postcondition,
i.e. (7) must imply (8);
- (c) it must be preserved by one iteration of the loop, i.e. (3)
must imply (4). *)
(** These conditions are actually independent of the particular
program and specification we are considering. Indeed, every loop
invariant has to satisfy them. One way to find an invariant that
simultaneously satisfies these three conditions is by using an
iterative process: start with a "candidate" invariant (e.g. a
guess or a heuristic choice) and check the three conditions above;
if any of the checks fails, try to use the information that we get
from the failure to produce another (hopefully better) candidate
invariant, and repeat the process.
For instance, in the reduce-to-zero example above, we saw that,
for a very simple loop, choosing [True] as an invariant did the
job. So let's try it again here! I.e., let's instantiate [I] with
[True] in the skeleton above see what we get...
(1) {{ X = m /\ Y = n }} ->> (a - OK)
(2) {{ True }}
WHILE X <> 0 DO
(3) {{ True /\ X <> 0 }} ->> (c - OK)
(4) {{ True }}
Y ::= Y - 1;;
(5) {{ True }}
X ::= X - 1
(6) {{ True }}
END
(7) {{ True /\ X = 0 }} ->> (b - WRONG!)
(8) {{ Y = n - m }}
While conditions (a) and (c) are trivially satisfied,
condition (b) is wrong, i.e. it is not the case that (7) [True /\
X = 0] implies (8) [Y = n - m]. In fact, the two assertions are
completely unrelated and it is easy to find a counterexample (say,
[Y = X = m = 0] and [n = 1]).
If we want (b) to hold, we need to strengthen the invariant so
that it implies the postcondition (8). One very simple way to do
this is to let the invariant _be_ the postcondition. So let's
return to our skeleton, instantiate [I] with [Y = n - m], and
check conditions (a) to (c) again.
(1) {{ X = m /\ Y = n }} ->> (a - WRONG!)
(2) {{ Y = n - m }}
WHILE X <> 0 DO
(3) {{ Y = n - m /\ X <> 0 }} ->> (c - WRONG!)
(4) {{ Y - 1 = n - m }}
Y ::= Y - 1;;
(5) {{ Y = n - m }}
X ::= X - 1
(6) {{ Y = n - m }}
END
(7) {{ Y = n - m /\ X = 0 }} ->> (b - OK)
(8) {{ Y = n - m }}
This time, condition (b) holds trivially, but (a) and (c) are
broken. Condition (a) requires that (1) [X = m /\ Y = n]
implies (2) [Y = n - m]. If we substitute [Y] by [n] we have to
show that [n = n - m] for arbitrary [m] and [n], which does not
hold (for instance, when [m = n = 1]). Condition (c) requires that
[n - m - 1 = n - m], which fails, for instance, for [n = 1] and [m =
0]. So, although [Y = n - m] holds at the end of the loop, it does
not hold from the start, and it doesn't hold on each iteration;
it is not a correct invariant.
This failure is not very surprising: the variable [Y] changes
during the loop, while [m] and [n] are constant, so the assertion
we chose didn't have much chance of being an invariant!
To do better, we need to generalize (8) to some statement that is
equivalent to (8) when [X] is [0], since this will be the case
when the loop terminates, and that "fills the gap" in some
appropriate way when [X] is nonzero. Looking at how the loop
works, we can observe that [X] and [Y] are decremented together
until [X] reaches [0]. So, if [X = 2] and [Y = 5] initially,
after one iteration of the loop we obtain [X = 1] and [Y = 4];
after two iterations [X = 0] and [Y = 3]; and then the loop stops.
Notice that the difference between [Y] and [X] stays constant
between iterations; initially, [Y = n] and [X = m], so this
difference is always [n - m]. So let's try instantiating [I] in
the skeleton above with [Y - X = n - m].
(1) {{ X = m /\ Y = n }} ->> (a - OK)
(2) {{ Y - X = n - m }}
WHILE X <> 0 DO
(3) {{ Y - X = n - m /\ X <> 0 }} ->> (c - OK)
(4) {{ (Y - 1) - (X - 1) = n - m }}
Y ::= Y - 1;;
(5) {{ Y - (X - 1) = n - m }}
X ::= X - 1
(6) {{ Y - X = n - m }}
END
(7) {{ Y - X = n - m /\ X = 0 }} ->> (b - OK)
(8) {{ Y = n - m }}
Success! Conditions (a), (b) and (c) all hold now. (To
verify (c), we need to check that, under the assumption that [X <>
0], we have [Y - X = (Y - 1) - (X - 1)]; this holds for all
natural numbers [X] and [Y].) *)
(* ####################################################### *)
(** ** Exercise: Slow Assignment *)
(** **** Exercise: 2 stars (slow_assignment) *)
(** A roundabout way of assigning a number currently stored in [X] to
the variable [Y] is to start [Y] at [0], then decrement [X] until
it hits [0], incrementing [Y] at each step. Here is a program that
implements this idea:
{{ X = m }}
Y ::= 0;;
WHILE X <> 0 DO
X ::= X - 1;;
Y ::= Y + 1
END
{{ Y = m }}
Write an informal decorated program showing that this is correct. *)
(* FILL IN HERE *)
(** [] *)
(* ####################################################### *)
(** ** Exercise: Slow Addition *)
(** **** Exercise: 3 stars, optional (add_slowly_decoration) *)
(** The following program adds the variable X into the variable Z
by repeatedly decrementing X and incrementing Z.
WHILE X <> 0 DO
Z ::= Z + 1;;
X ::= X - 1
END
Following the pattern of the [subtract_slowly] example above, pick
a precondition and postcondition that give an appropriate
specification of [add_slowly]; then (informally) decorate the
program accordingly. *)
(* FILL IN HERE *)
(** [] *)
(* ####################################################### *)
(** ** Example: Parity *)
(** Here is a cute little program for computing the parity of the
value initially stored in [X] (due to Daniel Cristofani).
{{ X = m }}
WHILE 2 <= X DO
X ::= X - 2
END
{{ X = parity m }}
The mathematical [parity] function used in the specification is
defined in Coq as follows: *)
Fixpoint parity x :=
match x with
| 0 => 0
| 1 => 1
| S (S x') => parity x'
end.
(** The postcondition does not hold at the beginning of the loop,
since [m = parity m] does not hold for an arbitrary [m], so we
cannot use that as an invariant. To find an invariant that works,
let's think a bit about what this loop does. On each iteration it
decrements [X] by [2], which preserves the parity of [X]. So the
parity of [X] does not change, i.e. it is invariant. The initial
value of [X] is [m], so the parity of [X] is always equal to the
parity of [m]. Using [parity X = parity m] as an invariant we
obtain the following decorated program:
{{ X = m }} ->> (a - OK)
{{ parity X = parity m }}
WHILE 2 <= X DO
{{ parity X = parity m /\ 2 <= X }} ->> (c - OK)
{{ parity (X-2) = parity m }}
X ::= X - 2
{{ parity X = parity m }}
END
{{ parity X = parity m /\ X < 2 }} ->> (b - OK)
{{ X = parity m }}
With this invariant, conditions (a), (b), and (c) are all
satisfied. For verifying (b), we observe that, when [X < 2], we
have [parity X = X] (we can easily see this in the definition of
[parity]). For verifying (c), we observe that, when [2 <= X], we
have [parity X = parity (X-2)]. *)
(** **** Exercise: 3 stars, optional (parity_formal) *)
(** Translate this proof to Coq. Refer to the reduce-to-zero example
for ideas. You may find the following two lemmas useful: *)
Lemma parity_ge_2 : forall x,
2 <= x ->
parity (x - 2) = parity x.
Proof.
induction x; intro. reflexivity.
destruct x. inversion H. inversion H1.
simpl. rewrite <- minus_n_O. reflexivity.
Qed.
Lemma parity_lt_2 : forall x,
~ 2 <= x ->
parity (x) = x.
Proof.
intros. induction x. reflexivity. destruct x. reflexivity.
apply ex_falso_quodlibet. apply H. omega.
Qed.
Theorem parity_correct : forall m,
{{ fun st => st X = m }}
WHILE BLe (ANum 2) (AId X) DO
X ::= AMinus (AId X) (ANum 2)
END
{{ fun st => st X = parity m }}.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ####################################################### *)
(** ** Example: Finding Square Roots *)
(** The following program computes the square root of [X]
by naive iteration:
{{ X=m }}
Z ::= 0;;
WHILE (Z+1)*(Z+1) <= X DO
Z ::= Z+1
END
{{ Z*Z<=m /\ m<(Z+1)*(Z+1) }}
*)
(** As above, we can try to use the postcondition as a candidate
invariant, obtaining the following decorated program:
(1) {{ X=m }} ->> (a - second conjunct of (2) WRONG!)
(2) {{ 0*0 <= m /\ m<1*1 }}
Z ::= 0;;
(3) {{ Z*Z <= m /\ m<(Z+1)*(Z+1) }}
WHILE (Z+1)*(Z+1) <= X DO
(4) {{ Z*Z<=m /\ (Z+1)*(Z+1)<=X }} ->> (c - WRONG!)
(5) {{ (Z+1)*(Z+1)<=m /\ m<(Z+2)*(Z+2) }}
Z ::= Z+1
(6) {{ Z*Z<=m /\ m<(Z+1)*(Z+1) }}
END
(7) {{ Z*Z<=m /\ m<(Z+1)*(Z+1) /\ X<(Z+1)*(Z+1) }} ->> (b - OK)
(8) {{ Z*Z<=m /\ m<(Z+1)*(Z+1) }}
This didn't work very well: both conditions (a) and (c) failed.
Looking at condition (c), we see that the second conjunct of (4)
is almost the same as the first conjunct of (5), except that (4)
mentions [X] while (5) mentions [m]. But note that [X] is never
assigned in this program, so we should have [X=m], but we didn't
propagate this information from (1) into the loop invariant.
Also, looking at the second conjunct of (8), it seems quite
hopeless as an invariant -- and we don't even need it, since we
can obtain it from the negation of the guard (third conjunct
in (7)), again under the assumption that [X=m].
So we now try [X=m /\ Z*Z <= m] as the loop invariant:
{{ X=m }} ->> (a - OK)
{{ X=m /\ 0*0 <= m }}
Z ::= 0;
{{ X=m /\ Z*Z <= m }}
WHILE (Z+1)*(Z+1) <= X DO
{{ X=m /\ Z*Z<=m /\ (Z+1)*(Z+1)<=X }} ->> (c - OK)
{{ X=m /\ (Z+1)*(Z+1)<=m }}
Z ::= Z+1
{{ X=m /\ Z*Z<=m }}
END
{{ X=m /\ Z*Z<=m /\ X<(Z+1)*(Z+1) }} ->> (b - OK)
{{ Z*Z<=m /\ m<(Z+1)*(Z+1) }}
This works, since conditions (a), (b), and (c) are now all
trivially satisfied.
Very often, if a variable is used in a loop in a read-only
fashion (i.e., it is referred to by the program or by the
specification and it is not changed by the loop) it is necessary
to add the fact that it doesn't change to the loop invariant. *)
(* ####################################################### *)
(** ** Example: Squaring *)
(** Here is a program that squares [X] by repeated addition:
{{ X = m }}
Y ::= 0;;
Z ::= 0;;
WHILE Y <> X DO
Z ::= Z + X;;
Y ::= Y + 1
END
{{ Z = m*m }}
*)
(** The first thing to note is that the loop reads [X] but doesn't
change its value. As we saw in the previous example, in such cases
it is a good idea to add [X = m] to the invariant. The other thing
we often use in the invariant is the postcondition, so let's add
that too, leading to the invariant candidate [Z = m * m /\ X = m].
{{ X = m }} ->> (a - WRONG)
{{ 0 = m*m /\ X = m }}
Y ::= 0;;
{{ 0 = m*m /\ X = m }}
Z ::= 0;;
{{ Z = m*m /\ X = m }}
WHILE Y <> X DO
{{ Z = Y*m /\ X = m /\ Y <> X }} ->> (c - WRONG)
{{ Z+X = m*m /\ X = m }}
Z ::= Z + X;;
{{ Z = m*m /\ X = m }}
Y ::= Y + 1
{{ Z = m*m /\ X = m }}
END
{{ Z = m*m /\ X = m /\ Y = X }} ->> (b - OK)
{{ Z = m*m }}
Conditions (a) and (c) fail because of the [Z = m*m] part. While
[Z] starts at [0] and works itself up to [m*m], we can't expect
[Z] to be [m*m] from the start. If we look at how [Z] progesses
in the loop, after the 1st iteration [Z = m], after the 2nd
iteration [Z = 2*m], and at the end [Z = m*m]. Since the variable
[Y] tracks how many times we go through the loop, we derive the
new invariant candidate [Z = Y*m /\ X = m].
{{ X = m }} ->> (a - OK)
{{ 0 = 0*m /\ X = m }}
Y ::= 0;;
{{ 0 = Y*m /\ X = m }}
Z ::= 0;;
{{ Z = Y*m /\ X = m }}
WHILE Y <> X DO
{{ Z = Y*m /\ X = m /\ Y <> X }} ->> (c - OK)
{{ Z+X = (Y+1)*m /\ X = m }}
Z ::= Z + X;
{{ Z = (Y+1)*m /\ X = m }}
Y ::= Y + 1
{{ Z = Y*m /\ X = m }}
END
{{ Z = Y*m /\ X = m /\ Y = X }} ->> (b - OK)
{{ Z = m*m }}
This new invariant makes the proof go through: all three
conditions are easy to check.
It is worth comparing the postcondition [Z = m*m] and the [Z =
Y*m] conjunct of the invariant. It is often the case that one has
to replace auxiliary variabes (parameters) with variables -- or
with expressions involving both variables and parameters (like
[m - Y]) -- when going from postconditions to invariants. *)
(* ####################################################### *)
(** ** Exercise: Factorial *)
(** **** Exercise: 3 stars (factorial) *)
(** Recall that [n!] denotes the factorial of [n] (i.e. [n! =
1*2*...*n]). Here is an Imp program that calculates the factorial
of the number initially stored in the variable [X] and puts it in
the variable [Y]:
{{ X = m }}
Y ::= 1 ;;
WHILE X <> 0
DO
Y ::= Y * X ;;
X ::= X - 1
END
{{ Y = m! }}
Fill in the blanks in following decorated program:
{{ X = m }} ->>
{{ }}
Y ::= 1;;
{{ }}
WHILE X <> 0
DO {{ }} ->>
{{ }}
Y ::= Y * X;;
{{ }}
X ::= X - 1
{{ }}
END
{{ }} ->>
{{ Y = m! }}
*)
(** [] *)
(* ####################################################### *)
(** ** Exercise: Min *)
(** **** Exercise: 3 stars (Min_Hoare) *)
(** Fill in valid decorations for the following program.
For the => steps in your annotations, you may rely (silently) on the
following facts about min
Lemma lemma1 : forall x y,
(x=0 \/ y=0) -> min x y = 0.
Lemma lemma2 : forall x y,
min (x-1) (y-1) = (min x y) - 1.
plus, as usual, standard high-school algebra.
{{ True }} ->>
{{ }}
X ::= a;;
{{ }}
Y ::= b;;
{{ }}
Z ::= 0;;
{{ }}
WHILE (X <> 0 /\ Y <> 0) DO
{{ }} ->>
{{ }}
X := X - 1;;
{{ }}
Y := Y - 1;;
{{ }}
Z := Z + 1
{{ }}
END
{{ }} ->>
{{ Z = min a b }}
*)
(** [] *)
(** **** Exercise: 3 stars (two_loops) *)
(** Here is a very inefficient way of adding 3 numbers:
X ::= 0;;
Y ::= 0;;
Z ::= c;;
WHILE X <> a DO
X ::= X + 1;;
Z ::= Z + 1
END;;
WHILE Y <> b DO
Y ::= Y + 1;;
Z ::= Z + 1
END
Show that it does what it should by filling in the blanks in the
following decorated program.
{{ True }} ->>
{{ }}
X ::= 0;;
{{ }}
Y ::= 0;;
{{ }}
Z ::= c;;
{{ }}
WHILE X <> a DO
{{ }} ->>
{{ }}
X ::= X + 1;;
{{ }}
Z ::= Z + 1
{{ }}
END;;
{{ }} ->>
{{ }}
WHILE Y <> b DO
{{ }} ->>
{{ }}
Y ::= Y + 1;;
{{ }}
Z ::= Z + 1
{{ }}
END
{{ }} ->>
{{ Z = a + b + c }}
*)
(** [] *)
(* ####################################################### *)
(** ** Exercise: Power Series *)
(** **** Exercise: 4 stars, optional (dpow2_down) *)
(** Here is a program that computes the series:
[1 + 2 + 2^2 + ... + 2^m = 2^(m+1) - 1]
X ::= 0;;
Y ::= 1;;
Z ::= 1;;
WHILE X <> m DO
Z ::= 2 * Z;;
Y ::= Y + Z;;
X ::= X + 1
END
Write a decorated program for this. *)
(* FILL IN HERE *)
(* ####################################################### *)
(** * Weakest Preconditions (Advanced) *)
(** Some Hoare triples are more interesting than others.
For example,
{{ False }} X ::= Y + 1 {{ X <= 5 }}
is _not_ very interesting: although it is perfectly valid, it
tells us nothing useful. Since the precondition isn't satisfied
by any state, it doesn't describe any situations where we can use
the command [X ::= Y + 1] to achieve the postcondition [X <= 5].
By contrast,
{{ Y <= 4 /\ Z = 0 }} X ::= Y + 1 {{ X <= 5 }}
is useful: it tells us that, if we can somehow create a situation
in which we know that [Y <= 4 /\ Z = 0], then running this command
will produce a state satisfying the postcondition. However, this
triple is still not as useful as it could be, because the [Z = 0]
clause in the precondition actually has nothing to do with the
postcondition [X <= 5]. The _most_ useful triple (for a given
command and postcondition) is this one:
{{ Y <= 4 }} X ::= Y + 1 {{ X <= 5 }}
In other words, [Y <= 4] is the _weakest_ valid precondition of
the command [X ::= Y + 1] for the postcondition [X <= 5]. *)
(** In general, we say that "[P] is the weakest precondition of
command [c] for postcondition [Q]" if [{{P}} c {{Q}}] and if,
whenever [P'] is an assertion such that [{{P'}} c {{Q}}], we have
[P' st] implies [P st] for all states [st]. *)
Definition is_wp P c Q :=
{{P}} c {{Q}} /\
forall P', {{P'}} c {{Q}} -> (P' ->> P).
(** That is, [P] is the weakest precondition of [c] for [Q]
if (a) [P] _is_ a precondition for [Q] and [c], and (b) [P] is the
_weakest_ (easiest to satisfy) assertion that guarantees [Q] after
executing [c]. *)
(** **** Exercise: 1 star, optional (wp) *)
(** What are the weakest preconditions of the following commands
for the following postconditions?
1) {{ ? }} SKIP {{ X = 5 }}
2) {{ ? }} X ::= Y + Z {{ X = 5 }}
3) {{ ? }} X ::= Y {{ X = Y }}
4) {{ ? }}
IFB X == 0 THEN Y ::= Z + 1 ELSE Y ::= W + 2 FI
{{ Y = 5 }}
5) {{ ? }}
X ::= 5
{{ X = 0 }}
6) {{ ? }}
WHILE True DO X ::= 0 END
{{ X = 0 }}
*)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 3 stars, advanced, optional (is_wp_formal) *)
(** Prove formally using the definition of [hoare_triple] that [Y <= 4]
is indeed the weakest precondition of [X ::= Y + 1] with respect to
postcondition [X <= 5]. *)
Theorem is_wp_example :
is_wp (fun st => st Y <= 4)
(X ::= APlus (AId Y) (ANum 1)) (fun st => st X <= 5).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, advanced (hoare_asgn_weakest) *)
(** Show that the precondition in the rule [hoare_asgn] is in fact the
weakest precondition. *)
Theorem hoare_asgn_weakest : forall Q X a,
is_wp (Q [X |-> a]) (X ::= a) Q.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, advanced, optional (hoare_havoc_weakest) *)
(** Show that your [havoc_pre] rule from the [himp_hoare] exercise
in the [Hoare] chapter returns the weakest precondition. *)
Module Himp2.
Import Himp.
Lemma hoare_havoc_weakest : forall (P Q : Assertion) (X : id),
{{ P }} HAVOC X {{ Q }} ->
P ->> havoc_pre X Q.
Proof.
(* FILL IN HERE *) Admitted.
End Himp2.
(** [] *)
(* ####################################################### *)
(** * Formal Decorated Programs (Advanced) *)
(** The informal conventions for decorated programs amount to a way of
displaying Hoare triples in which commands are annotated with
enough embedded assertions that checking the validity of the
triple is reduced to simple logical and algebraic calculations
showing that some assertions imply others. In this section, we
show that this informal presentation style can actually be made
completely formal and indeed that checking the validity of
decorated programs can mostly be automated. *)
(** ** Syntax *)
(** The first thing we need to do is to formalize a variant of the
syntax of commands with embedded assertions. We call the new
commands _decorated commands_, or [dcom]s. *)
Inductive dcom : Type :=
| DCSkip : Assertion -> dcom
| DCSeq : dcom -> dcom -> dcom
| DCAsgn : id -> aexp -> Assertion -> dcom
| DCIf : bexp -> Assertion -> dcom -> Assertion -> dcom
-> Assertion-> dcom
| DCWhile : bexp -> Assertion -> dcom -> Assertion -> dcom
| DCPre : Assertion -> dcom -> dcom
| DCPost : dcom -> Assertion -> dcom.
Tactic Notation "dcom_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "Skip" | Case_aux c "Seq" | Case_aux c "Asgn"
| Case_aux c "If" | Case_aux c "While"
| Case_aux c "Pre" | Case_aux c "Post" ].
Notation "'SKIP' {{ P }}"
:= (DCSkip P)
(at level 10) : dcom_scope.
Notation "l '::=' a {{ P }}"
:= (DCAsgn l a P)
(at level 60, a at next level) : dcom_scope.
Notation "'WHILE' b 'DO' {{ Pbody }} d 'END' {{ Ppost }}"
:= (DCWhile b Pbody d Ppost)
(at level 80, right associativity) : dcom_scope.
Notation "'IFB' b 'THEN' {{ P }} d 'ELSE' {{ P' }} d' 'FI' {{ Q }}"
:= (DCIf b P d P' d' Q)
(at level 80, right associativity) : dcom_scope.
Notation "'->>' {{ P }} d"
:= (DCPre P d)
(at level 90, right associativity) : dcom_scope.
Notation "{{ P }} d"
:= (DCPre P d)
(at level 90) : dcom_scope.
Notation "d '->>' {{ P }}"
:= (DCPost d P)
(at level 80, right associativity) : dcom_scope.
Notation " d ;; d' "
:= (DCSeq d d')
(at level 80, right associativity) : dcom_scope.
Delimit Scope dcom_scope with dcom.
(** To avoid clashing with the existing [Notation] definitions
for ordinary [com]mands, we introduce these notations in a special
scope called [dcom_scope], and we wrap examples with the
declaration [% dcom] to signal that we want the notations to be
interpreted in this scope.
Careful readers will note that we've defined two notations for the
[DCPre] constructor, one with and one without a [->>]. The
"without" version is intended to be used to supply the initial
precondition at the very top of the program. *)
Example dec_while : dcom := (
{{ fun st => True }}
WHILE (BNot (BEq (AId X) (ANum 0)))
DO
{{ fun st => True /\ st X <> 0}}
X ::= (AMinus (AId X) (ANum 1))
{{ fun _ => True }}
END
{{ fun st => True /\ st X = 0}} ->>
{{ fun st => st X = 0 }}
) % dcom.
(** It is easy to go from a [dcom] to a [com] by erasing all
annotations. *)
Fixpoint extract (d:dcom) : com :=
match d with
| DCSkip _ => SKIP
| DCSeq d1 d2 => (extract d1 ;; extract d2)
| DCAsgn X a _ => X ::= a
| DCIf b _ d1 _ d2 _ => IFB b THEN extract d1 ELSE extract d2 FI
| DCWhile b _ d _ => WHILE b DO extract d END
| DCPre _ d => extract d
| DCPost d _ => extract d
end.
(** The choice of exactly where to put assertions in the definition of
[dcom] is a bit subtle. The simplest thing to do would be to
annotate every [dcom] with a precondition and postcondition. But
this would result in very verbose programs with a lot of repeated
annotations: for example, a program like [SKIP;SKIP] would have to
be annotated as
{{P}} ({{P}} SKIP {{P}}) ;; ({{P}} SKIP {{P}}) {{P}},
with pre- and post-conditions on each [SKIP], plus identical pre-
and post-conditions on the semicolon!
Instead, the rule we've followed is this:
- The _post_-condition expected by each [dcom] [d] is embedded in [d]
- The _pre_-condition is supplied by the context. *)
(** In other words, the invariant of the representation is that a
[dcom] [d] together with a precondition [P] determines a Hoare
triple [{{P}} (extract d) {{post d}}], where [post] is defined as
follows: *)
Fixpoint post (d:dcom) : Assertion :=
match d with
| DCSkip P => P
| DCSeq d1 d2 => post d2
| DCAsgn X a Q => Q
| DCIf _ _ d1 _ d2 Q => Q
| DCWhile b Pbody c Ppost => Ppost
| DCPre _ d => post d
| DCPost c Q => Q
end.
(** Similarly, we can extract the "initial precondition" from a
decorated program. *)
Fixpoint pre (d:dcom) : Assertion :=
match d with
| DCSkip P => fun st => True
| DCSeq c1 c2 => pre c1
| DCAsgn X a Q => fun st => True
| DCIf _ _ t _ e _ => fun st => True
| DCWhile b Pbody c Ppost => fun st => True
| DCPre P c => P
| DCPost c Q => pre c
end.
(** This function is not doing anything sophisticated like calculating
a weakest precondition; it just recursively searches for an
explicit annotation at the very beginning of the program,
returning default answers for programs that lack an explicit
precondition (like a bare assignment or [SKIP]). *)
(** Using [pre] and [post], and assuming that we adopt the convention
of always supplying an explicit precondition annotation at the
very beginning of our decorated programs, we can express what it
means for a decorated program to be correct as follows: *)
Definition dec_correct (d:dcom) :=
{{pre d}} (extract d) {{post d}}.
(** To check whether this Hoare triple is _valid_, we need a way to
extract the "proof obligations" from a decorated program. These
obligations are often called _verification conditions_, because
they are the facts that must be verified to see that the
decorations are logically consistent and thus add up to a complete
proof of correctness. *)
(** ** Extracting Verification Conditions *)
(** The function [verification_conditions] takes a [dcom] [d] together
with a precondition [P] and returns a _proposition_ that, if it
can be proved, implies that the triple [{{P}} (extract d) {{post d}}]
is valid. *)
(** It does this by walking over [d] and generating a big
conjunction including all the "local checks" that we listed when
we described the informal rules for decorated programs. (Strictly
speaking, we need to massage the informal rules a little bit to
add some uses of the rule of consequence, but the correspondence
should be clear.) *)
Fixpoint verification_conditions (P : Assertion) (d:dcom) : Prop :=
match d with
| DCSkip Q =>
(P ->> Q)
| DCSeq d1 d2 =>
verification_conditions P d1
/\ verification_conditions (post d1) d2
| DCAsgn X a Q =>
(P ->> Q [X |-> a])
| DCIf b P1 d1 P2 d2 Q =>
((fun st => P st /\ bassn b st) ->> P1)
/\ ((fun st => P st /\ ~ (bassn b st)) ->> P2)
/\ (Q <<->> post d1) /\ (Q <<->> post d2)
/\ verification_conditions P1 d1
/\ verification_conditions P2 d2
| DCWhile b Pbody d Ppost =>
(* post d is the loop invariant and the initial precondition *)
(P ->> post d)
/\ (Pbody <<->> (fun st => post d st /\ bassn b st))
/\ (Ppost <<->> (fun st => post d st /\ ~(bassn b st)))
/\ verification_conditions Pbody d
| DCPre P' d =>
(P ->> P') /\ verification_conditions P' d
| DCPost d Q =>
verification_conditions P d /\ (post d ->> Q)
end.
(** And now, the key theorem, which states that
[verification_conditions] does its job correctly. Not
surprisingly, we need to use each of the Hoare Logic rules at some
point in the proof. *)
(** We have used _in_ variants of several tactics before to
apply them to values in the context rather than the goal. An
extension of this idea is the syntax [tactic in *], which applies
[tactic] in the goal and every hypothesis in the context. We most
commonly use this facility in conjunction with the [simpl] tactic,
as below. *)
Theorem verification_correct : forall d P,
verification_conditions P d -> {{P}} (extract d) {{post d}}.
Proof.
dcom_cases (induction d) Case; intros P H; simpl in *.
Case "Skip".
eapply hoare_consequence_pre.
apply hoare_skip.
assumption.
Case "Seq".
inversion H as [H1 H2]. clear H.
eapply hoare_seq.
apply IHd2. apply H2.
apply IHd1. apply H1.
Case "Asgn".
eapply hoare_consequence_pre.
apply hoare_asgn.
assumption.
Case "If".
inversion H as [HPre1 [HPre2 [[Hd11 Hd12]
[[Hd21 Hd22] [HThen HElse]]]]].
clear H.
apply IHd1 in HThen. clear IHd1.
apply IHd2 in HElse. clear IHd2.
apply hoare_if.
eapply hoare_consequence_pre; eauto.
eapply hoare_consequence_post; eauto.
eapply hoare_consequence_pre; eauto.
eapply hoare_consequence_post; eauto.
Case "While".
inversion H as [Hpre [[Hbody1 Hbody2] [[Hpost1 Hpost2] Hd]]];
subst; clear H.
eapply hoare_consequence_pre; eauto.
eapply hoare_consequence_post; eauto.
apply hoare_while.
eapply hoare_consequence_pre; eauto.
Case "Pre".
inversion H as [HP Hd]; clear H.
eapply hoare_consequence_pre. apply IHd. apply Hd. assumption.
Case "Post".
inversion H as [Hd HQ]; clear H.
eapply hoare_consequence_post. apply IHd. apply Hd. assumption.
Qed.
(** ** Examples *)
(** The propositions generated by [verification_conditions] are fairly
big, and they contain many conjuncts that are essentially trivial. *)
Eval simpl in (verification_conditions (fun st => True) dec_while).
(**
==>
(((fun _ : state => True) ->> (fun _ : state => True)) /\
((fun _ : state => True) ->> (fun _ : state => True)) /\
(fun st : state => True /\ bassn (BNot (BEq (AId X) (ANum 0))) st) =
(fun st : state => True /\ bassn (BNot (BEq (AId X) (ANum 0))) st) /\
(fun st : state => True /\ ~ bassn (BNot (BEq (AId X) (ANum 0))) st) =
(fun st : state => True /\ ~ bassn (BNot (BEq (AId X) (ANum 0))) st) /\
(fun st : state => True /\ bassn (BNot (BEq (AId X) (ANum 0))) st) ->>
(fun _ : state => True) [X |-> AMinus (AId X) (ANum 1)]) /\
(fun st : state => True /\ ~ bassn (BNot (BEq (AId X) (ANum 0))) st) ->>
(fun st : state => st X = 0)
*)
(** In principle, we could certainly work with them using just the
tactics we have so far, but we can make things much smoother with
a bit of automation. We first define a custom [verify] tactic
that applies splitting repeatedly to turn all the conjunctions
into separate subgoals and then uses [omega] and [eauto] (a handy
general-purpose automation tactic that we'll discuss in detail
later) to deal with as many of them as possible. *)
Lemma ble_nat_true_iff : forall n m : nat,
ble_nat n m = true <-> n <= m.
Proof.
intros n m. split. apply ble_nat_true.
generalize dependent m. induction n; intros m H. reflexivity.
simpl. destruct m. inversion H.
apply le_S_n in H. apply IHn. assumption.
Qed.
Lemma ble_nat_false_iff : forall n m : nat,
ble_nat n m = false <-> ~(n <= m).
Proof.
intros n m. split. apply ble_nat_false.
generalize dependent m. induction n; intros m H.
apply ex_falso_quodlibet. apply H. apply le_0_n.
simpl. destruct m. reflexivity.
apply IHn. intro Hc. apply H. apply le_n_S. assumption.
Qed.
Tactic Notation "verify" :=
apply verification_correct;
repeat split;
simpl; unfold assert_implies;
unfold bassn in *; unfold beval in *; unfold aeval in *;
unfold assn_sub; intros;
repeat rewrite update_eq;
repeat (rewrite update_neq; [| (intro X; inversion X)]);
simpl in *;
repeat match goal with [H : _ /\ _ |- _] => destruct H end;
repeat rewrite not_true_iff_false in *;
repeat rewrite not_false_iff_true in *;
repeat rewrite negb_true_iff in *;
repeat rewrite negb_false_iff in *;
repeat rewrite beq_nat_true_iff in *;
repeat rewrite beq_nat_false_iff in *;
repeat rewrite ble_nat_true_iff in *;
repeat rewrite ble_nat_false_iff in *;
try subst;
repeat
match goal with
[st : state |- _] =>
match goal with
[H : st _ = _ |- _] => rewrite -> H in *; clear H
| [H : _ = st _ |- _] => rewrite <- H in *; clear H
end
end;
try eauto; try omega.
(** What's left after [verify] does its thing is "just the interesting
parts" of checking that the decorations are correct. For very
simple examples [verify] immediately solves the goal (provided
that the annotations are correct). *)
Theorem dec_while_correct :
dec_correct dec_while.
Proof. verify. Qed.
(** Another example (formalizing a decorated program we've seen
before): *)
Example subtract_slowly_dec (m:nat) (p:nat) : dcom := (
{{ fun st => st X = m /\ st Z = p }} ->>
{{ fun st => st Z - st X = p - m }}
WHILE BNot (BEq (AId X) (ANum 0))
DO {{ fun st => st Z - st X = p - m /\ st X <> 0 }} ->>
{{ fun st => (st Z - 1) - (st X - 1) = p - m }}
Z ::= AMinus (AId Z) (ANum 1)
{{ fun st => st Z - (st X - 1) = p - m }} ;;
X ::= AMinus (AId X) (ANum 1)
{{ fun st => st Z - st X = p - m }}
END
{{ fun st => st Z - st X = p - m /\ st X = 0 }} ->>
{{ fun st => st Z = p - m }}
) % dcom.
Theorem subtract_slowly_dec_correct : forall m p,
dec_correct (subtract_slowly_dec m p).
Proof. intros m p. verify. (* this grinds for a bit! *) Qed.
(** **** Exercise: 3 stars, advanced (slow_assignment_dec) *)
(** In the [slow_assignment] exercise above, we saw a roundabout way
of assigning a number currently stored in [X] to the variable [Y]:
start [Y] at [0], then decrement [X] until it hits [0],
incrementing [Y] at each step.
Write a _formal_ version of this decorated program and prove it
correct. *)
Example slow_assignment_dec (m:nat) : dcom :=
(* FILL IN HERE *) admit.
Theorem slow_assignment_dec_correct : forall m,
dec_correct (slow_assignment_dec m).
Proof. (* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 4 stars, advanced (factorial_dec) *)
(** Remember the factorial function we worked with before: *)
Fixpoint real_fact (n:nat) : nat :=
match n with
| O => 1
| S n' => n * (real_fact n')
end.
(** Following the pattern of [subtract_slowly_dec], write a decorated
program [factorial_dec] that implements the factorial function and
prove it correct as [factorial_dec_correct]. *)
(* FILL IN HERE *)
(** [] *)
(** $Date: 2014-12-31 11:17:56 -0500 (Wed, 31 Dec 2014) $ *)
|
// // (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// Single-precision floating-point multiply core.
//
// Higher latency: 6 cycles
// Intended for high fmax operation.
//
// !!! BEWARE !!!
// WHEN IN HIGH-CAPACITY MODE:
// This core has less capacity than latency because two of the
// pipeline stages share the same enable signal. This is
// because the multiplier block has three pipeline stages,
// but only two clock enables, thus one of the stages has to use
// the same clock enable as another.
//
// To compensate, there is a staging register at the output
// to provide one additional capacity slot.
// !!! BEWARE !!!
//
// Supports two "stall" modes based on the HIGH_CAPACITY parameter:
// 1. HIGH_CAPACITY=0: single enable for all stages
// 2. HIGH_CAPACITY=1: each stage is independently controlled
module acl_fp_custom_mul_hc_core #(
parameter integer HIGH_CAPACITY = 1 // 0|1
)
(
input logic clock,
input logic resetn,
// only used if HIGH_CAPACITY == 1
input logic valid_in,
input logic stall_in,
output logic valid_out,
output logic stall_out,
// only used if HIGH_CAPACITY == 0
input logic enable,
input logic [31:0] dataa,
input logic [31:0] datab,
output logic [31:0] result
);
struct packed
{
logic sign_a, sign_b;
logic [7:0] exponent_a, exponent_b;
logic [22:0] mantissa_a, mantissa_b;
} s0;
assign {s0.sign_a, s0.exponent_a, s0.mantissa_a} = dataa;
assign {s0.sign_b, s0.exponent_b, s0.mantissa_b} = datab;
// Stage 1: Register inputs.
typedef struct packed
{
logic valid;
logic sign_a, sign_b;
logic [7:0] exponent_a, exponent_b;
logic mantissa_a_0s, mantissa_b_0s;
logic [10:0] top_mantissa_a, top_mantissa_b;
} stage1_regs;
stage1_regs s1 /* synthesis preserve */;
logic stall_in_1, stall_out_1;
logic valid_in_1, valid_out_1;
assign valid_in_1 = valid_in;
assign valid_out_1 = s1.valid;
assign stall_out_1 = HIGH_CAPACITY ? (valid_out_1 & stall_in_1) : ~enable;
assign stall_out = stall_out_1;
always @(posedge clock or negedge resetn)
begin
if (~resetn)
begin
s1 <= 'x;
s1.valid <= 1'b0;
end
else if (~stall_out_1)
begin
s1.valid <= valid_in_1;
s1.sign_a <= s0.sign_a;
s1.exponent_a <= s0.exponent_a;
s1.sign_b <= s0.sign_b;
s1.exponent_b <= s0.exponent_b;
// Use unregistered mantissa input because the mantissa
// is registered directly in the multiplier.
//
// If this becomes critical, split the "equal to zero" check
// into multiple chunks.
s1.mantissa_a_0s <= (s0.mantissa_a[11:0] == '0);
s1.mantissa_b_0s <= (s0.mantissa_b[11:0] == '0);
s1.top_mantissa_a <= s0.mantissa_a[22:12];
s1.top_mantissa_b <= s0.mantissa_b[22:12];
end
end
// Stage 2
// NOTE: Stage 2 is NOT a high-capacity stage. It is enabled
// by stall_out_3. This is to match the multiplier, which uses
// the same enable signal for stage 2 and stage 3. See the
// comments on the multiplier for why.
typedef struct packed
{
logic valid;
logic sign;
logic [8:0] exponent; // 0 - 508 (254+254); double-bias not removed
logic exponent_a_0s, exponent_b_0s;
logic exponent_a_1s, exponent_b_1s;
logic mantissa_a_0s, mantissa_b_0s;
} stage2_regs;
stage2_regs s2 /* synthesis preserve */;
logic stall_in_2, stall_out_2, stall_out_3;
logic valid_in_2, valid_out_2;
assign valid_in_2 = valid_out_1;
assign valid_out_2 = s2.valid;
//assign stall_out_2 = HIGH_CAPACITY ? (valid_out_2 & stall_in_2) : ~enable;
assign stall_out_2 = HIGH_CAPACITY ? stall_out_3 : ~enable;
assign stall_in_1 = stall_out_2;
always @(posedge clock or negedge resetn)
begin
if (~resetn)
begin
s2 <= 'x;
s2.valid <= 1'b0;
end
else if (~stall_out_2)
begin
s2.valid <= valid_in_2;
s2.sign <= s1.sign_a ^ s1.sign_b;
s2.exponent <= {1'b0, s1.exponent_a} + {1'b0, s1.exponent_b};
s2.exponent_a_0s <= (s1.exponent_a == '0);
s2.exponent_b_0s <= (s1.exponent_b == '0);
s2.exponent_a_1s <= (s1.exponent_a == '1);
s2.exponent_b_1s <= (s1.exponent_b == '1);
s2.mantissa_a_0s <= s1.mantissa_a_0s & (s1.top_mantissa_a == '0);
s2.mantissa_b_0s <= s1.mantissa_b_0s & (s1.top_mantissa_b == '0);
end
end
// Stage 3.
typedef struct packed
{
logic valid;
logic sign;
logic [7:0] exponent; // double bias removed
logic exponent_ge_254; // final flag (takes into account inf and zero)
logic exponent_gt_254; // final flag (takes into account inf and zero)
logic exponent_ge_0; // final flag (takes into account inf and zero)
logic exponent_gt_0; // final flag (takes into account inf and zero)
logic nan;
} stage3_regs;
struct packed
{
logic [47:0] mantissa; // m47m46.m45m44...
} s3mult;
stage3_regs s3 /* synthesis preserve */;
logic stall_in_3; // stall_out_3 is declared in stage 2
logic valid_in_3, valid_out_3;
assign valid_in_3 = valid_out_2;
assign valid_out_3 = s3.valid;
assign stall_out_3 = HIGH_CAPACITY ? (valid_out_3 & stall_in_3) : ~enable;
assign stall_in_2 = stall_out_3;
// Special numbers.
logic a_is_inf_3, b_is_inf_3;
logic a_is_nan_3, b_is_nan_3;
logic a_is_zero_3, b_is_zero_3;
assign a_is_inf_3 = (s2.exponent_a_1s & s2.mantissa_a_0s);
assign b_is_inf_3 = (s2.exponent_b_1s & s2.mantissa_b_0s);
assign a_is_nan_3 = (s2.exponent_a_1s & ~s2.mantissa_a_0s);
assign b_is_nan_3 = (s2.exponent_b_1s & ~s2.mantissa_b_0s);
assign a_is_zero_3 = (s2.exponent_a_0s & s2.mantissa_a_0s);
assign b_is_zero_3 = (s2.exponent_b_0s & s2.mantissa_b_0s);
logic inf_times_zero_3, inf_times_non_zero_3;
assign inf_times_zero_3 = (a_is_inf_3 & b_is_zero_3) | (b_is_inf_3 & a_is_zero_3);
assign inf_times_non_zero_3 = (a_is_inf_3 & ~b_is_zero_3) | (b_is_inf_3 & ~a_is_zero_3);
logic one_input_is_denorm_3;
assign one_input_is_denorm_3 = s2.exponent_a_0s | s2.exponent_b_0s;
logic one_input_is_nan_3;
assign one_input_is_nan_3 = a_is_nan_3 | b_is_nan_3;
always @(posedge clock or negedge resetn)
begin
if (~resetn)
begin
s3 <= 'x;
s3.valid <= 1'b0;
end
else if (~stall_out_3)
begin
s3.valid <= valid_in_3;
s3.sign <= s2.sign;
// Remove double bias from exponent sum.
s3.exponent <= s2.exponent - 9'd127;
// Update exponent flags to account for guaranteed overflow (inf)
// or guaranteed underflow (zero).
if( inf_times_non_zero_3 )
begin
// Result is infinity. Set flags to trigger overflow check
// later.
s3.exponent_ge_254 <= 1'b1;
s3.exponent_gt_254 <= 1'b1;
s3.exponent_ge_0 <= 1'b1;
s3.exponent_gt_0 <= 1'b1;
end
else if( one_input_is_denorm_3 )
begin
// Result is zero.
// TODO Denormalized numbers are rounded to zero. If any operand
// is zero, then the multiplication result is zero. Enforce this
// by setting the exponent to zero which will trigger the
// underflow check later.
s3.exponent_ge_254 <= 1'b0;
s3.exponent_gt_254 <= 1'b0;
s3.exponent_ge_0 <= 1'b0;
s3.exponent_gt_0 <= 1'b0;
end
else
begin
s3.exponent_ge_254 <= (s2.exponent >= (9'd254 + 9'd127));
s3.exponent_gt_254 <= (s2.exponent > (9'd254 + 9'd127));
s3.exponent_ge_0 <= (s2.exponent >= (9'd0 + 9'd127));
s3.exponent_gt_0 <= (s2.exponent > (9'd0 + 9'd127));
end
// Detect NaN.
if( one_input_is_nan_3 | inf_times_zero_3 )
s3.nan <= 1'b1;
else
s3.nan <= 1'b0;
end
end
// Mantissa multiplier. Inputs and outputs are registered in
// the multiplier itself.
// Input is registered at stage 1. Output is registered at stage 3.
// Stage 2 is registered in the MAC's first-adder register.
//
// The mantissa inputs are assumed to be for normalized numbers.
// Multiplication involving denormalized numbers will be treated
// as a multiplication by zero (handled by the exponent flags).
logic [23:0] man_mult_dataa, man_mult_datab;
assign man_mult_dataa = {1'b1, s0.mantissa_a};
assign man_mult_datab = {1'b1, s0.mantissa_b};
acl_fp_custom_mul_hc_core_mult man_mult(
.clock(clock),
.resetn(1'b1), // don't need to reset
.input_enable(~stall_out_1),
//.pipe_enable(~stall_out_2),
.output_enable(~stall_out_3),
.dataa(man_mult_dataa),
.datab(man_mult_datab),
.result(s3mult.mantissa)
);
// Stage 4.
typedef struct packed
{
logic valid;
logic sign;
logic [7:0] exponent; // double bias removed
logic exponent_ge_254; // final flag (takes into account inf and zero)
logic exponent_gt_254; // final flag (takes into account inf and zero)
logic exponent_ge_0; // final flag (takes into account inf and zero)
logic exponent_gt_0; // final flag (takes into account inf and zero)
logic nan;
logic [24:0] mantissa; // truncated mantissa; m24m23.m22m21...
logic [1:0] round_amount; // rounding amount
logic [1:0] round; // flags indicating if rounding should be done
} stage4_regs;
stage4_regs s4 /* synthesis preserve */;
logic stall_in_4, stall_out_4;
logic valid_in_4, valid_out_4;
assign valid_in_4 = valid_out_3;
assign valid_out_4 = s4.valid;
assign stall_out_4 = HIGH_CAPACITY ? (valid_out_4 & stall_in_4) : ~enable;
assign stall_in_3 = stall_out_4;
always @(posedge clock or negedge resetn)
begin
if (~resetn)
begin
s4 <= 'x;
s4.valid <= 1'b0;
end
else if (~stall_out_4)
begin
s4.valid <= valid_in_4;
s4.sign <= s3.sign;
s4.exponent <= s3.exponent;
s4.exponent_ge_254 <= s3.exponent_ge_254;
s4.exponent_gt_254 <= s3.exponent_gt_254;
s4.exponent_ge_0 <= s3.exponent_ge_0;
s4.exponent_gt_0 <= s3.exponent_gt_0;
s4.nan <= s3.nan;
// Truncate mantissa to bits necessary to form the final mantissa
// (taking into account potential rounding as well).
s4.mantissa <= s3mult.mantissa[47 -: 25];
// Determine the amount that needs to be added to the mantissa to
// perform round-to-nearest-even rounding.
//
// First, there are two ways to round the mantissa because the
// current mantissa has two bits to the left of the decimal point.
// If the MSB=1, then the mantissa will have to be shifted by
// one to the right to normalize. Note that a mantissa that has
// MSB=0 can end up with MSB=1 after rounding is applied. In any
// case, regardless if MSB=0 or MSB=1, determining if rounding
// should occur uses the same methodology but slightly different
// set of bits determining on the MSB.
//
// For simplicity, consider the case where MSB=1. To check if
// rounding needs to be applied, break the mantissa into:
// {A[23:0], B[x:0]}
// where A represents the final mantissa (23-bits + MSB for
// implied 1) and B represents the rest of the lower bits of the
// mantissa.
//
// Round-to-nearest-even says round (add 1 to A) if:
// 1) B > "0.5", OR
// 2) B = "0.5" AND A[0]=1 (i.e. A is odd)
// can be converted into B >= "0.5" AND A[0]=1
// B="0.5" is B[x]=1 and B[x-1:0]=0 and likewise,
// B>"0.5" is B[x]=1 and B[x-1:0]!=0.
//
// Rounding is controlled by the "round" field, which indicates
// rounding if any bit is set. The goal of having multiple bits
// is to have each round bit depend on only a subset of the bits
// that need to be considered.
// round[0]: dependent on B[15:0] and B[x]
// round[1]: dependent on the rest and B[x]
s4.round <= '0;
if( s3mult.mantissa[47] )
begin
// form: 1m46.m45m44...m24|m23...m0
// If rounding needs to occur, add 1 to m24, which is the 2nd
// LSB of the 25-bit truncated mantissa. Note that adding
// 1 will not cause the mantissa to overflow (even though
// MSB=1) because the mantissa 1m46...m24 cannot be all 1s
// (it's not mathematically possible to get a multiplication
// result that large from the inputs).
//
// Alternatively, add 1 to m23! If rounding needs to happen,
// m23=1 and so adding 1 effectively adds 1 to m24 as well.
// Also, m23 is not part of the final mantissa in this
// scenario so it doesn't matter if that bit becomes
// "incorrect". This simplifies the logic for round_amount
// (see other places where round_amount is set).
s4.round_amount <= 2'd1;
if( s3mult.mantissa[23] ) // B>=0.5
begin
// Scenario 2 (B>=0.5 and A[0]=1)
if( s3mult.mantissa[24] )
s4.round[1] <= 1'b1;
// Partial scenario 1 (upper bits)
if( |s3mult.mantissa[22:16] )
s4.round[1] <= 1'b1;
// Partial scenario 1 (lower bits)
if( |s3mult.mantissa[15:0] )
s4.round[0] <= 1'b1;
end
end
else
begin
// form: 01.m45m44...m23|m22...m0
if( s3.exponent_ge_0 & ~s3.exponent_gt_0 ) // exponent=0
begin
// As it is, the current result will become a denormalized number (or possibly inf or zero as
// those checks are done in the same cycle - these cases are handled by the
// exponent flags update in this cycle and take priority later over
// any rounding determined here).
//
// Rounding may push result into the normalized range
// though. If the rounding does not push the
// number into the normalized range, the exponent flags
// will force the value to zero.
//
// For the purposes of determining if rounding should
// occur, consider the number in its denormal form
// is: 0.1m45m44...m24|m23...m0 (x 2^(1-127))
// If rounding needs to occur, add 1 to m24, which is the 2nd
// LSB of the 25-bit truncated mantissa.
//
// Alternatively, add 1 to m23! If rounding needs to happen,
// m23=1 and so adding 1 effectively adds 1 to m24 as well.
// Also, m23 is not part of the final mantissa in this
// scenario so it doesn't matter if that bit becomes
// "incorrect". This simplifies the logic for round_amount
// (see other places where round_amount is set).
s4.round_amount <= 2'd1;
if( s3mult.mantissa[23] ) // B>=0.5
begin
// Scenario 2 (B>=0.5 and A[0]=1)
if( s3mult.mantissa[24] )
s4.round[1] <= 1'b1;
// Partial scenario 1 (upper bits)
if( |s3mult.mantissa[22:16] )
s4.round[1] <= 1'b1;
// Partial scenario 1 (lower bits)
if( |s3mult.mantissa[15:0] )
s4.round[0] <= 1'b1;
end
end
else
begin
// form: 01.m45m44...m23|m22...m0
// If rounding needs to occur, add 1 to m23, which is the LSB
// of the 25-bit truncated mantissa.
s4.round_amount <= 2'd1;
if( s3mult.mantissa[22] ) // B>=0.5
begin
// Scenario 2 (B>=0.5 and A[0]=1)
if( s3mult.mantissa[23] )
s4.round[1] <= 1'b1;
// Partial scenario 1 (upper bits)
if( |s3mult.mantissa[21:16] )
s4.round[1] <= 1'b1;
// Partial scenario 1 (lower bits)
if( |s3mult.mantissa[15:0] )
s4.round[0] <= 1'b1;
end
end
end
end
end
// Stage 5.
typedef struct packed
{
logic valid;
logic sign;
logic [7:0] exponent; // double bias removed
logic exponent_ge_254; // final flag (takes into account inf and zero)
logic exponent_gt_254; // final flag (takes into account inf and zero)
logic exponent_ge_0; // final flag (takes into account inf and zero)
logic exponent_gt_0; // final flag (takes into account inf and zero)
logic nan;
logic [24:0] mantissa; // rounded mantissa; m24m23.m22m21...
} stage5_regs;
stage5_regs s5 /* synthesis preserve */;
logic stall_in_5, stall_out_5;
logic valid_in_5, valid_out_5;
assign valid_in_5 = valid_out_4;
assign valid_out_5 = s5.valid;
assign stall_out_5 = HIGH_CAPACITY ? (valid_out_5 & stall_in_5) : ~enable;
assign stall_in_4 = stall_out_5;
always @(posedge clock or negedge resetn)
begin
if (~resetn)
begin
s5 <= 'x;
s5.valid <= 1'b0;
end
else if (~stall_out_5)
begin
s5.valid <= valid_in_5;
s5.sign <= s4.sign;
s5.exponent <= s4.exponent;
s5.exponent_ge_254 <= s4.exponent_ge_254;
s5.exponent_gt_254 <= s4.exponent_gt_254;
s5.exponent_ge_0 <= s4.exponent_ge_0;
s5.exponent_gt_0 <= s4.exponent_gt_0;
s5.nan <= s4.nan;
// Perform rounding on mantissa.
s5.mantissa <= s4.mantissa + (|s4.round ? s4.round_amount : '0);
end
end
// Stage 6.
typedef struct packed
{
logic valid;
logic sign;
logic [7:0] exponent;
logic [24:0] mantissa; // m23.m22m21...
} stage6_regs;
stage6_regs s6 /* synthesis preserve */;
logic stall_in_6, stall_out_6;
logic valid_in_6, valid_out_6;
assign valid_in_6 = valid_out_5;
assign valid_out_6 = s6.valid;
assign stall_out_6 = HIGH_CAPACITY ? (valid_out_6 & stall_in_6) : ~enable;
assign stall_in_5 = stall_out_6;
always @(posedge clock or negedge resetn)
begin
if (~resetn)
begin
s6 <= 'x;
s6.valid <= 1'b0;
end
else if (~stall_out_6)
begin
s6.valid <= valid_in_6;
s6.sign <= s5.sign;
if( s5.nan )
begin
// QNaN
s6.exponent <= '1;
s6.mantissa <= '1;
end
else
begin
// Handle all remaining cases of underflow and overflow here.
if( s5.mantissa[24] )
begin
// form: 1m23.m22m21...
// shift right by one bit to get: 1.m23m22m21...
// and add one to exponent
if( s5.exponent_ge_254 )
begin
// Overflow to infinity.
s6.exponent <= '1;
s6.mantissa <= '0;
end
else if( s5.exponent_ge_0 )
begin
// Normal number.
s6.exponent <= s5.exponent + 8'd1;
s6.mantissa <= s5.mantissa[24:1];
end
if( ~s5.exponent_ge_0 )
begin
// Underflow to zero (TODO no denormals)
s6.exponent <= '0;
s6.mantissa <= '0;
end
end
else
begin
// form: 01.m22m21...
if( s5.exponent_gt_254 )
begin
// Overflow to infinity.
s6.exponent <= '1;
s6.mantissa <= '0;
end
else if( s5.exponent_gt_0 )
begin
// Normal number.
s6.exponent <= s5.exponent;
s6.mantissa <= s5.mantissa[23:0];
end
if( ~s5.exponent_gt_0 )
begin
// Underflow to zero (TODO no denormals)
s6.exponent <= '0;
s6.mantissa <= '0;
end
end
end
end
end
// Output.
generate
if( HIGH_CAPACITY )
begin
// Add a staging register to compensate for the one missing
// capacity slot.
acl_staging_reg #(
.WIDTH(32)
)
output_sr(
.clk(clock),
.reset(~resetn),
.i_valid(s6.valid),
.i_data({s6.sign, s6.exponent, s6.mantissa[22:0]}),
.o_stall(stall_in_6),
.o_valid(valid_out),
.o_data(result),
.i_stall(stall_in)
);
end
else
begin
assign valid_out = s6.valid;
assign result = {s6.sign, s6.exponent, s6.mantissa[22:0]};
assign stall_in_6 = stall_in;
end
endgenerate
endmodule
module acl_fp_custom_mul_hc_core_mult(
input logic clock,
input logic resetn,
input logic input_enable,
// The enable for the pipeline stage (first-adder) is the same
// as the output stage. It is this way because if we want to pack
// two 36x36 DSP blocks into the same physical SIV DSP block,
// there are only four clk/clkena pairs available and so each
// 36x36 DSP can only use two unique clk/clkena pairs.
//input logic pipe_enable,
input logic output_enable,
input logic [23:0] dataa,
input logic [23:0] datab,
output logic [47:0] result
);
// Multiplier configuration:
// 36x36 mode
// input, pipeline and output registers
logic [35:0] mult_a_result, mult_b_result, mult_c_result, mult_d_result;
logic [71:0] mac_result;
logic [35:0] dataa_ext, datab_ext;
assign dataa_ext = {dataa, 12'd0}; // inputs are placed starting from MSB
assign datab_ext = {datab, 12'd0}; // inputs are placed starting from MSB
assign result = mac_result[71 -: 48];
// MAC blocks
// MAC mults are configured with an input register
// MAC out is configured with first-adder reigster and output register
stratixiv_mac_mult #(
.dataa_width(18),
.datab_width(18),
.dataa_clock("0"),
.datab_clock("0"),
.dataa_clear("0"),
.datab_clear("0"),
.signa_internally_grounded("false"),
.signb_internally_grounded("false")
)
mac_mult_a(
.signa(1'b0),
.signb(1'b0),
.dataa(dataa_ext[35:18]),
.datab(datab_ext[35:18]),
.dataout(mult_a_result),
.clk({3'b000, clock}),
.ena({3'b000, input_enable}),
.aclr({3'b000, ~resetn})
);
stratixiv_mac_mult #(
.dataa_width(18),
.datab_width(18),
.dataa_clock("0"),
.datab_clock("0"),
.dataa_clear("0"),
.datab_clear("0"),
.signa_internally_grounded("true"),
.signb_internally_grounded("false")
)
mac_mult_b(
.signa(1'b0),
.signb(1'b0),
.dataa(dataa_ext[17:0]),
.datab(datab_ext[35:18]),
.dataout(mult_b_result),
.clk({3'b000, clock}),
.ena({3'b000, input_enable}),
.aclr({3'b000, ~resetn})
);
stratixiv_mac_mult #(
.dataa_width(18),
.datab_width(18),
.dataa_clock("0"),
.datab_clock("0"),
.dataa_clear("0"),
.datab_clear("0"),
.signa_internally_grounded("false"),
.signb_internally_grounded("true")
)
mac_mult_c(
.signa(1'b0),
.signb(1'b0),
.dataa(dataa_ext[35:18]),
.datab(datab_ext[17:0]),
.dataout(mult_c_result),
.clk({3'b000, clock}),
.ena({3'b000, input_enable}),
.aclr({3'b000, ~resetn})
);
stratixiv_mac_mult #(
.dataa_width(18),
.datab_width(18),
.dataa_clock("0"),
.datab_clock("0"),
.dataa_clear("0"),
.datab_clear("0"),
.signa_internally_grounded("true"),
.signb_internally_grounded("true")
)
mac_mult_d(
.signa(1'b0),
.signb(1'b0),
.dataa(dataa_ext[17:0]),
.datab(datab_ext[17:0]),
.dataout(mult_d_result),
.clk({3'b000, clock}),
.ena({3'b000, input_enable}),
.aclr({3'b000, ~resetn})
);
stratixiv_mac_out #(
.dataa_width(36),
.datab_width(36),
.datac_width(36),
.datad_width(36),
.first_adder0_clock("0"),
.first_adder1_clock("0"),
.first_adder0_clear("0"),
.first_adder1_clear("0"),
.output_clock("0"),
.output_clear("0"),
.operation_mode("36_bit_multiply")
)
mac_out(
.signa(1'b0),
.signb(1'b0),
.dataa(mult_a_result),
.datab(mult_b_result),
.datac(mult_c_result),
.datad(mult_d_result),
.dataout(mac_result),
.clk({3'b000, clock}),
.ena({3'b000, output_enable}),
.aclr({3'b000, ~resetn})
);
endmodule
|
/* Generated by Yosys 0.3.0+ (git sha1 3b52121) */
(* src = "../../verilog/max6682.v:133" *)
module MAX6682(Reset_n_i, Clk_i, Enable_i, CpuIntr_o, MAX6682CS_n_o, SPI_Data_i, SPI_Write_o, SPI_ReadNext_o, SPI_Data_o, SPI_FIFOFull_i, SPI_FIFOEmpty_i, SPI_Transmission_i, PeriodCounterPresetH_i, PeriodCounterPresetL_i, SensorValue_o, Threshold_i, SPI_CPOL_o, SPI_CPHA_o, SPI_LSBFE_o);
(* src = "../../verilog/max6682.v:297" *)
wire [31:0] \$0\SensorFSM_Timer[31:0] ;
(* src = "../../verilog/max6682.v:327" *)
wire [15:0] \$0\Word0[15:0] ;
(* src = "../../verilog/max6682.v:231" *)
wire \$2\SPI_FSM_Start[0:0] ;
(* src = "../../verilog/max6682.v:231" *)
wire \$2\SensorFSM_StoreNewValue[0:0] ;
(* src = "../../verilog/max6682.v:231" *)
wire \$2\SensorFSM_TimerPreset[0:0] ;
(* src = "../../verilog/max6682.v:231" *)
wire \$3\SensorFSM_TimerPreset[0:0] ;
(* src = "../../verilog/max6682.v:231" *)
wire \$4\SensorFSM_TimerPreset[0:0] ;
wire \$auto$opt_reduce.cc:126:opt_mux$732 ;
wire \$procmux$118_CMP ;
wire \$procmux$123_CMP ;
wire \$procmux$126_CMP ;
wire [31:0] \$procmux$449_Y ;
(* src = "../../verilog/max6682.v:311" *)
wire [31:0] \$sub$../../verilog/max6682.v:311$18_Y ;
(* src = "../../verilog/max6682.v:323" *)
wire [15:0] AbsDiffResult;
(* src = "../../verilog/max6682.v:184" *)
wire [7:0] Byte0;
(* src = "../../verilog/max6682.v:185" *)
wire [7:0] Byte1;
(* intersynth_port = "Clk_i" *)
(* src = "../../verilog/max6682.v:137" *)
input Clk_i;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "ReconfModuleIRQs_s" *)
(* src = "../../verilog/max6682.v:141" *)
output CpuIntr_o;
(* src = "../../verilog/max6682.v:342" *)
wire [16:0] DiffAB;
(* src = "../../verilog/max6682.v:343" *)
wire [15:0] DiffBA;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "ReconfModuleIn_s" *)
(* src = "../../verilog/max6682.v:139" *)
input Enable_i;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "Outputs_o" *)
(* src = "../../verilog/max6682.v:143" *)
output MAX6682CS_n_o;
(* intersynth_conntype = "Word" *)
(* intersynth_param = "PeriodCounterPresetH_i" *)
(* src = "../../verilog/max6682.v:159" *)
input [15:0] PeriodCounterPresetH_i;
(* intersynth_conntype = "Word" *)
(* intersynth_param = "PeriodCounterPresetL_i" *)
(* src = "../../verilog/max6682.v:161" *)
input [15:0] PeriodCounterPresetL_i;
(* intersynth_port = "Reset_n_i" *)
(* src = "../../verilog/max6682.v:135" *)
input Reset_n_i;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "SPI_CPHA" *)
(* src = "../../verilog/max6682.v:169" *)
output SPI_CPHA_o;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "SPI_CPOL" *)
(* src = "../../verilog/max6682.v:167" *)
output SPI_CPOL_o;
(* intersynth_conntype = "Byte" *)
(* intersynth_port = "SPI_DataOut" *)
(* src = "../../verilog/max6682.v:145" *)
input [7:0] SPI_Data_i;
(* intersynth_conntype = "Byte" *)
(* intersynth_port = "SPI_DataIn" *)
(* src = "../../verilog/max6682.v:151" *)
output [7:0] SPI_Data_o;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "SPI_FIFOEmpty" *)
(* src = "../../verilog/max6682.v:155" *)
input SPI_FIFOEmpty_i;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "SPI_FIFOFull" *)
(* src = "../../verilog/max6682.v:153" *)
input SPI_FIFOFull_i;
(* src = "../../verilog/max6682.v:183" *)
wire SPI_FSM_Done;
(* src = "../../verilog/max6682.v:182" *)
wire SPI_FSM_Start;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "SPI_LSBFE" *)
(* src = "../../verilog/max6682.v:171" *)
output SPI_LSBFE_o;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "SPI_ReadNext" *)
(* src = "../../verilog/max6682.v:149" *)
output SPI_ReadNext_o;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "SPI_Transmission" *)
(* src = "../../verilog/max6682.v:157" *)
input SPI_Transmission_i;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "SPI_Write" *)
(* src = "../../verilog/max6682.v:147" *)
output SPI_Write_o;
(* src = "../../verilog/max6682.v:215" *)
wire SensorFSM_DiffTooLarge;
(* src = "../../verilog/max6682.v:216" *)
wire SensorFSM_StoreNewValue;
(* src = "../../verilog/max6682.v:295" *)
wire [31:0] SensorFSM_Timer;
(* src = "../../verilog/max6682.v:214" *)
wire SensorFSM_TimerEnable;
(* src = "../../verilog/max6682.v:212" *)
wire SensorFSM_TimerOvfl;
(* src = "../../verilog/max6682.v:213" *)
wire SensorFSM_TimerPreset;
(* src = "../../verilog/max6682.v:321" *)
wire [15:0] SensorValue;
(* intersynth_conntype = "Word" *)
(* intersynth_param = "SensorValue_o" *)
(* src = "../../verilog/max6682.v:163" *)
output [15:0] SensorValue_o;
(* intersynth_conntype = "Word" *)
(* intersynth_param = "Threshold_i" *)
(* src = "../../verilog/max6682.v:165" *)
input [15:0] Threshold_i;
(* src = "../../verilog/max6682.v:322" *)
wire [15:0] Word0;
\$reduce_or #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000011),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$auto$opt_reduce.cc:130:opt_mux$733 (
.A({ \$procmux$126_CMP , \$procmux$123_CMP , \$procmux$118_CMP }),
.Y(\$auto$opt_reduce.cc:126:opt_mux$732 )
);
(* src = "../../verilog/max6682.v:316" *)
\$eq #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000100000),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000100000),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$eq$../../verilog/max6682.v:316$19 (
.A(SensorFSM_Timer),
.B(0),
.Y(SensorFSM_TimerOvfl)
);
(* fsm_encoding = "auto" *)
(* src = "../../verilog/max6682.v:210" *)
\$fsm #(
.ARST_POLARITY(1'b0),
.CLK_POLARITY(1'b1),
.CTRL_IN_WIDTH(32'b00000000000000000000000000000100),
.CTRL_OUT_WIDTH(32'b00000000000000000000000000000011),
.NAME("\\SensorFSM_State"),
.STATE_BITS(32'b00000000000000000000000000000010),
.STATE_NUM(32'b00000000000000000000000000000100),
.STATE_NUM_LOG2(32'b00000000000000000000000000000011),
.STATE_RST(32'b00000000000000000000000000000000),
.STATE_TABLE(8'b11011000),
.TRANS_NUM(32'b00000000000000000000000000001001),
.TRANS_TABLE(117'b011zzzz0100000100zz10100100101zz1001010010zzz0000010001z11z011001001z01z010001001zz0z001001000zzz1010100000zzz0000100)
) \$fsm$\SensorFSM_State$738 (
.ARST(Reset_n_i),
.CLK(Clk_i),
.CTRL_IN({ SensorFSM_TimerOvfl, SensorFSM_DiffTooLarge, SPI_FSM_Done, Enable_i }),
.CTRL_OUT({ \$procmux$126_CMP , \$procmux$123_CMP , \$procmux$118_CMP })
);
(* src = "../../verilog/max6682.v:348" *)
\$gt #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000010000),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000010000),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$gt$../../verilog/max6682.v:348$26 (
.A(AbsDiffResult),
.B(Threshold_i),
.Y(SensorFSM_DiffTooLarge)
);
(* src = "../../verilog/max6682.v:297" *)
\$adff #(
.ARST_POLARITY(1'b0),
.ARST_VALUE(32'b00000000000000000000000000000000),
.CLK_POLARITY(1'b1),
.WIDTH(32'b00000000000000000000000000100000)
) \$procdff$727 (
.ARST(Reset_n_i),
.CLK(Clk_i),
.D(\$0\SensorFSM_Timer[31:0] ),
.Q(SensorFSM_Timer)
);
(* src = "../../verilog/max6682.v:327" *)
\$adff #(
.ARST_POLARITY(1'b0),
.ARST_VALUE(16'b0000000000000000),
.CLK_POLARITY(1'b1),
.WIDTH(32'b00000000000000000000000000010000)
) \$procdff$728 (
.ARST(Reset_n_i),
.CLK(Clk_i),
.D(\$0\Word0[15:0] ),
.Q(Word0)
);
\$not #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$117 (
.A(\$auto$opt_reduce.cc:126:opt_mux$732 ),
.Y(CpuIntr_o)
);
\$and #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$137 (
.A(\$procmux$123_CMP ),
.B(\$2\SPI_FSM_Start[0:0] ),
.Y(SPI_FSM_Start)
);
\$and #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$147 (
.A(\$procmux$118_CMP ),
.B(\$2\SensorFSM_StoreNewValue[0:0] ),
.Y(SensorFSM_StoreNewValue)
);
\$pmux #(
.S_WIDTH(32'b00000000000000000000000000000011),
.WIDTH(32'b00000000000000000000000000000001)
) \$procmux$177 (
.A(1'b0),
.B({ Enable_i, 1'b1, \$2\SensorFSM_StoreNewValue[0:0] }),
.S({ \$procmux$126_CMP , \$procmux$123_CMP , \$procmux$118_CMP }),
.Y(SensorFSM_TimerEnable)
);
\$pmux #(
.S_WIDTH(32'b00000000000000000000000000000011),
.WIDTH(32'b00000000000000000000000000000001)
) \$procmux$192 (
.A(1'b1),
.B({ \$2\SensorFSM_TimerPreset[0:0] , 1'b0, \$3\SensorFSM_TimerPreset[0:0] }),
.S({ \$procmux$126_CMP , \$procmux$123_CMP , \$procmux$118_CMP }),
.Y(SensorFSM_TimerPreset)
);
\$not #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$230 (
.A(Enable_i),
.Y(\$2\SensorFSM_TimerPreset[0:0] )
);
\$and #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$259 (
.A(Enable_i),
.B(SensorFSM_TimerOvfl),
.Y(\$2\SPI_FSM_Start[0:0] )
);
\$and #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$336 (
.A(SPI_FSM_Done),
.B(SensorFSM_DiffTooLarge),
.Y(\$2\SensorFSM_StoreNewValue[0:0] )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000000001)
) \$procmux$368 (
.A(1'b1),
.B(\$4\SensorFSM_TimerPreset[0:0] ),
.S(SPI_FSM_Done),
.Y(\$3\SensorFSM_TimerPreset[0:0] )
);
\$not #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$400 (
.A(SensorFSM_DiffTooLarge),
.Y(\$4\SensorFSM_TimerPreset[0:0] )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000100000)
) \$procmux$449 (
.A(SensorFSM_Timer),
.B(\$sub$../../verilog/max6682.v:311$18_Y ),
.S(SensorFSM_TimerEnable),
.Y(\$procmux$449_Y )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000100000)
) \$procmux$452 (
.A(\$procmux$449_Y ),
.B({ PeriodCounterPresetH_i, PeriodCounterPresetL_i }),
.S(SensorFSM_TimerPreset),
.Y(\$0\SensorFSM_Timer[31:0] )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000010000)
) \$procmux$455 (
.A(Word0),
.B({ 5'b00000, Byte1, Byte0[7:5] }),
.S(SensorFSM_StoreNewValue),
.Y(\$0\Word0[15:0] )
);
(* src = "../../verilog/max6682.v:311" *)
\$sub #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000100000),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000100000)
) \$sub$../../verilog/max6682.v:311$18 (
.A(SensorFSM_Timer),
.B(1'b1),
.Y(\$sub$../../verilog/max6682.v:311$18_Y )
);
(* src = "../../verilog/max6682.v:344" *)
\$sub #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000010001),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000010001),
.Y_WIDTH(32'b00000000000000000000000000010001)
) \$sub$../../verilog/max6682.v:344$23 (
.A({ 6'b000000, Byte1, Byte0[7:5] }),
.B({ 1'b0, Word0 }),
.Y(DiffAB)
);
(* src = "../../verilog/max6682.v:345" *)
\$sub #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000010000),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000010000),
.Y_WIDTH(32'b00000000000000000000000000010000)
) \$sub$../../verilog/max6682.v:345$24 (
.A(Word0),
.B({ 5'b00000, Byte1, Byte0[7:5] }),
.Y(DiffBA)
);
(* src = "../../verilog/max6682.v:346" *)
\$mux #(
.WIDTH(32'b00000000000000000000000000010000)
) \$ternary$../../verilog/max6682.v:346$25 (
.A(DiffAB[15:0]),
.B(DiffBA),
.S(DiffAB[16]),
.Y(AbsDiffResult)
);
(* src = "../../verilog/max6682.v:187" *)
MAX6682_SPI_FSM MAX6682_SPI_FSM_1 (
.Byte0(Byte0),
.Byte1(Byte1),
.Clk_i(Clk_i),
.MAX6682CS_n_o(MAX6682CS_n_o),
.Reset_n_i(Reset_n_i),
.SPI_Data_i(SPI_Data_i),
.SPI_FSM_Done(SPI_FSM_Done),
.SPI_FSM_Start(SPI_FSM_Start),
.SPI_ReadNext_o(SPI_ReadNext_o),
.SPI_Transmission_i(SPI_Transmission_i),
.SPI_Write_o(SPI_Write_o)
);
assign SPI_CPHA_o = 1'b0;
assign SPI_CPOL_o = 1'b0;
assign SPI_Data_o = 8'b00000000;
assign SPI_LSBFE_o = 1'b0;
assign SensorValue = { 5'b00000, Byte1, Byte0[7:5] };
assign SensorValue_o = Word0;
endmodule
(* src = "../../verilog/max6682.v:1" *)
module MAX6682_SPI_FSM(Reset_n_i, Clk_i, SPI_FSM_Start, SPI_Transmission_i, MAX6682CS_n_o, SPI_Write_o, SPI_ReadNext_o, SPI_FSM_Done, SPI_Data_i, Byte0, Byte1);
(* src = "../../verilog/max6682.v:111" *)
wire [7:0] \$0\Byte0[7:0] ;
(* src = "../../verilog/max6682.v:111" *)
wire [7:0] \$0\Byte1[7:0] ;
(* src = "../../verilog/max6682.v:50" *)
wire \$2\MAX6682CS_n_o[0:0] ;
(* src = "../../verilog/max6682.v:50" *)
wire \$2\SPI_FSM_Wr1[0:0] ;
wire \$auto$opt_reduce.cc:126:opt_mux$736 ;
wire \$procmux$553_CMP ;
wire \$procmux$554_CMP ;
wire \$procmux$558_CMP ;
wire \$procmux$559_CMP ;
wire \$procmux$560_CMP ;
wire \$procmux$563_CMP ;
(* src = "../../verilog/max6682.v:11" *)
output [7:0] Byte0;
(* src = "../../verilog/max6682.v:12" *)
output [7:0] Byte1;
(* src = "../../verilog/max6682.v:3" *)
input Clk_i;
(* src = "../../verilog/max6682.v:6" *)
output MAX6682CS_n_o;
(* src = "../../verilog/max6682.v:2" *)
input Reset_n_i;
(* src = "../../verilog/max6682.v:10" *)
input [7:0] SPI_Data_i;
(* src = "../../verilog/max6682.v:9" *)
output SPI_FSM_Done;
(* src = "../../verilog/max6682.v:4" *)
input SPI_FSM_Start;
(* src = "../../verilog/max6682.v:24" *)
wire SPI_FSM_Wr0;
(* src = "../../verilog/max6682.v:23" *)
wire SPI_FSM_Wr1;
(* src = "../../verilog/max6682.v:8" *)
output SPI_ReadNext_o;
(* src = "../../verilog/max6682.v:5" *)
input SPI_Transmission_i;
(* src = "../../verilog/max6682.v:7" *)
output SPI_Write_o;
\$reduce_or #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000010),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$auto$opt_reduce.cc:130:opt_mux$735 (
.A({ \$procmux$554_CMP , \$procmux$553_CMP }),
.Y(SPI_FSM_Done)
);
\$reduce_or #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000100),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$auto$opt_reduce.cc:130:opt_mux$737 (
.A({ SPI_FSM_Wr0, \$procmux$560_CMP , \$procmux$559_CMP , \$procmux$558_CMP }),
.Y(\$auto$opt_reduce.cc:126:opt_mux$736 )
);
(* fsm_encoding = "auto" *)
(* src = "../../verilog/max6682.v:21" *)
\$fsm #(
.ARST_POLARITY(1'b0),
.CLK_POLARITY(1'b1),
.CTRL_IN_WIDTH(32'b00000000000000000000000000000010),
.CTRL_OUT_WIDTH(32'b00000000000000000000000000000111),
.NAME("\\SPI_FSM_State"),
.STATE_BITS(32'b00000000000000000000000000000011),
.STATE_NUM(32'b00000000000000000000000000000111),
.STATE_NUM_LOG2(32'b00000000000000000000000000000011),
.STATE_RST(32'b00000000000000000000000000000000),
.STATE_TABLE(21'b011101001110010100000),
.TRANS_NUM(32'b00000000000000000000000000001001),
.TRANS_TABLE(135'b1101z11000001001100z0010000100101zz0110000010100zz0100010000011zz0000000001010zz1100001000001zz1011000000000z11000100000000z00000100000)
) \$fsm$\SPI_FSM_State$743 (
.ARST(Reset_n_i),
.CLK(Clk_i),
.CTRL_IN({ SPI_Transmission_i, SPI_FSM_Start }),
.CTRL_OUT({ SPI_FSM_Wr0, \$procmux$563_CMP , \$procmux$560_CMP , \$procmux$559_CMP , \$procmux$558_CMP , \$procmux$554_CMP , \$procmux$553_CMP })
);
(* src = "../../verilog/max6682.v:111" *)
\$adff #(
.ARST_POLARITY(1'b0),
.ARST_VALUE(8'b00000000),
.CLK_POLARITY(1'b1),
.WIDTH(32'b00000000000000000000000000001000)
) \$procdff$729 (
.ARST(Reset_n_i),
.CLK(Clk_i),
.D(\$0\Byte0[7:0] ),
.Q(Byte0)
);
(* src = "../../verilog/max6682.v:111" *)
\$adff #(
.ARST_POLARITY(1'b0),
.ARST_VALUE(8'b00000000),
.CLK_POLARITY(1'b1),
.WIDTH(32'b00000000000000000000000000001000)
) \$procdff$730 (
.ARST(Reset_n_i),
.CLK(Clk_i),
.D(\$0\Byte1[7:0] ),
.Q(Byte1)
);
\$mux #(
.WIDTH(32'b00000000000000000000000000001000)
) \$procmux$458 (
.A(Byte0),
.B(SPI_Data_i),
.S(SPI_FSM_Wr0),
.Y(\$0\Byte0[7:0] )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000001000)
) \$procmux$465 (
.A(Byte1),
.B(SPI_Data_i),
.S(SPI_FSM_Wr1),
.Y(\$0\Byte1[7:0] )
);
\$and #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$583 (
.A(\$procmux$558_CMP ),
.B(\$2\SPI_FSM_Wr1[0:0] ),
.Y(SPI_FSM_Wr1)
);
\$pmux #(
.S_WIDTH(32'b00000000000000000000000000000010),
.WIDTH(32'b00000000000000000000000000000001)
) \$procmux$593 (
.A(1'b0),
.B({ \$2\SPI_FSM_Wr1[0:0] , 1'b1 }),
.S({ \$procmux$558_CMP , SPI_FSM_Wr0 }),
.Y(SPI_ReadNext_o)
);
\$pmux #(
.S_WIDTH(32'b00000000000000000000000000000010),
.WIDTH(32'b00000000000000000000000000000001)
) \$procmux$606 (
.A(1'b1),
.B({ \$2\MAX6682CS_n_o[0:0] , 1'b0 }),
.S({ \$procmux$563_CMP , \$auto$opt_reduce.cc:126:opt_mux$736 }),
.Y(MAX6682CS_n_o)
);
\$pmux #(
.S_WIDTH(32'b00000000000000000000000000000010),
.WIDTH(32'b00000000000000000000000000000001)
) \$procmux$637 (
.A(1'b0),
.B({ SPI_FSM_Start, 1'b1 }),
.S({ \$procmux$563_CMP , \$procmux$560_CMP }),
.Y(SPI_Write_o)
);
\$not #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$666 (
.A(SPI_FSM_Start),
.Y(\$2\MAX6682CS_n_o[0:0] )
);
\$not #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$703 (
.A(SPI_Transmission_i),
.Y(\$2\SPI_FSM_Wr1[0:0] )
);
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: ddr_phy_oclkdelay_cal.v
// /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $
// \ \ / \ Date Created: Aug 03 2009
// \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose: Center write DQS in write DQ valid window using Phaser_Out Stage3
// delay
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v4_0_ddr_phy_ocd_lim #
(parameter TAPCNTRWIDTH = 7,
parameter DQS_CNT_WIDTH = 3,
parameter DQS_WIDTH = 9,
parameter TCQ = 100,
parameter TAPSPERKCLK = 56,
parameter TDQSS_DEGREES = 60,
parameter BYPASS_COMPLEX_OCAL = "FALSE")
(/*AUTOARG*/
// Outputs
lim2init_write_request, lim2init_prech_req, lim2poc_rdy, lim2poc_ktap_right,
lim2stg3_inc, lim2stg3_dec, lim2stg2_inc, lim2stg2_dec, lim_done,
lim2ocal_stg3_right_lim, lim2ocal_stg3_left_lim, dbg_ocd_lim,
// Inputs
clk, rst, lim_start, po_rdy, poc2lim_rise_align_taps_lead,
poc2lim_rise_align_taps_trail, poc2lim_fall_align_taps_lead,
poc2lim_fall_align_taps_trail, oclkdelay_init_val, wl_po_fine_cnt,
simp_stg3_final_sel, oclkdelay_calib_done, poc2lim_detect_done,
prech_done, oclkdelay_calib_cnt
);
function [TAPCNTRWIDTH:0] mod_sub (input [TAPCNTRWIDTH-1:0] a,
input [TAPCNTRWIDTH-1:0] b,
input integer base);
begin
mod_sub = (a>=b) ? a-b : a+base[TAPCNTRWIDTH-1:0]-b;
end
endfunction // mod_sub
input clk;
input rst;
input lim_start;
input po_rdy;
input [TAPCNTRWIDTH-1:0] poc2lim_rise_align_taps_lead;
input [TAPCNTRWIDTH-1:0] poc2lim_rise_align_taps_trail;
input [TAPCNTRWIDTH-1:0] poc2lim_fall_align_taps_lead;
input [TAPCNTRWIDTH-1:0] poc2lim_fall_align_taps_trail;
input [5:0] oclkdelay_init_val;
input [5:0] wl_po_fine_cnt;
input [5:0] simp_stg3_final_sel;
input oclkdelay_calib_done;
input poc2lim_detect_done;
input prech_done;
input [DQS_CNT_WIDTH:0] oclkdelay_calib_cnt;
output lim2init_write_request;
output lim2init_prech_req;
output lim2poc_rdy;
output lim2poc_ktap_right; // I think this can be defaulted.
output lim2stg3_inc;
output lim2stg3_dec;
output lim2stg2_inc;
output lim2stg2_dec;
output lim_done;
output [5:0] lim2ocal_stg3_right_lim;
output [5:0] lim2ocal_stg3_left_lim;
output [255:0] dbg_ocd_lim;
// Stage 3 taps can move an additional + or - 60 degrees from the write level position
// Convert 60 degrees to MMCM taps. 360/60=6.
//localparam real DIV_FACTOR = 360/TDQSS_DEGREES;
//localparam real TDQSS_LIM_MMCM_TAPS = TAPSPERKCLK/DIV_FACTOR;
localparam DIV_FACTOR = 360/TDQSS_DEGREES;
localparam TDQSS_LIM_MMCM_TAPS = TAPSPERKCLK/DIV_FACTOR;
localparam WAIT_CNT = 15;
localparam IDLE = 14'b00_0000_0000_0001;
localparam INIT = 14'b00_0000_0000_0010;
localparam WAIT_WR_REQ = 14'b00_0000_0000_0100;
localparam WAIT_POC_DONE = 14'b00_0000_0000_1000;
localparam WAIT_STG3 = 14'b00_0000_0001_0000;
localparam STAGE3_INC = 14'b00_0000_0010_0000;
localparam STAGE3_DEC = 14'b00_0000_0100_0000;
localparam STAGE2_INC = 14'b00_0000_1000_0000;
localparam STAGE2_DEC = 14'b00_0001_0000_0000;
localparam STG3_INCDEC_WAIT = 14'b00_0010_0000_0000;
localparam STG2_INCDEC_WAIT = 14'b00_0100_0000_0000;
localparam STAGE2_TAP_CHK = 14'b00_1000_0000_0000;
localparam PRECH_REQUEST = 14'b01_0000_0000_0000;
localparam LIMIT_DONE = 14'b10_0000_0000_0000;
// Flip-flops
reg [5:0] stg3_init_val;
reg [13:0] lim_state;
reg lim_start_r;
reg ktap_right_r;
reg write_request_r;
reg prech_req_r;
reg poc_ready_r;
reg wait_cnt_en_r;
reg wait_cnt_done;
reg [3:0] wait_cnt_r;
reg [5:0] stg3_tap_cnt;
reg [5:0] stg2_tap_cnt;
reg [5:0] stg3_left_lim;
reg [5:0] stg3_right_lim;
reg [DQS_WIDTH*6-1:0] cmplx_stg3_left_lim;
reg [DQS_WIDTH*6-1:0] simp_stg3_left_lim;
reg [DQS_WIDTH*6-1:0] cmplx_stg3_right_lim;
reg [DQS_WIDTH*6-1:0] simp_stg3_right_lim;
reg [5:0] stg3_dec_val;
reg [5:0] stg3_inc_val;
reg detect_done_r;
reg stg3_dec_r;
reg stg2_inc_r;
reg stg3_inc2init_val_r;
reg stg3_inc2init_val_r1;
reg stg3_dec2init_val_r;
reg stg3_dec2init_val_r1;
reg stg3_dec_req_r;
reg stg3_inc_req_r;
reg stg2_dec_req_r;
reg stg2_inc_req_r;
reg stg3_init_dec_r;
reg [TAPCNTRWIDTH:0] mmcm_current;
reg [TAPCNTRWIDTH:0] mmcm_init_trail;
reg [TAPCNTRWIDTH:0] mmcm_init_lead;
reg done_r;
reg [13:0] lim_nxt_state;
reg ktap_right;
reg write_request;
reg prech_req;
reg poc_ready;
reg stg3_dec;
reg stg2_inc;
reg stg3_inc2init_val;
reg stg3_dec2init_val;
reg stg3_dec_req;
reg stg3_inc_req;
reg stg2_dec_req;
reg stg2_inc_req;
reg stg3_init_dec;
reg done;
reg oclkdelay_calib_done_r;
wire [TAPCNTRWIDTH:0] mmcm_sub_dec = mod_sub (mmcm_init_trail, mmcm_current, TAPSPERKCLK);
wire [TAPCNTRWIDTH:0] mmcm_sub_inc = mod_sub (mmcm_current, mmcm_init_lead, TAPSPERKCLK);
/***************************************************************************/
// Debug signals
/***************************************************************************/
assign dbg_ocd_lim[0+:DQS_WIDTH*6] = simp_stg3_left_lim[DQS_WIDTH*6-1:0];
assign dbg_ocd_lim[54+:DQS_WIDTH*6] = simp_stg3_right_lim[DQS_WIDTH*6-1:0];
assign dbg_ocd_lim[255:108] = 'd0;
assign lim2init_write_request = write_request_r;
assign lim2init_prech_req = prech_req_r;
assign lim2poc_ktap_right = ktap_right_r;
assign lim2poc_rdy = poc_ready_r;
assign lim2ocal_stg3_left_lim = stg3_left_lim;
assign lim2ocal_stg3_right_lim = stg3_right_lim;
assign lim2stg3_dec = stg3_dec_req_r;
assign lim2stg3_inc = stg3_inc_req_r;
assign lim2stg2_dec = stg2_dec_req_r;
assign lim2stg2_inc = stg2_inc_req_r;
assign lim_done = done_r;
/**************************Wait Counter Start*********************************/
// Wait counter enable for wait states WAIT_WR_REQ and WAIT_STG3
// To avoid DQS toggling when stage2 and 3 taps are moving
always @(posedge clk) begin
if ((lim_state == WAIT_WR_REQ) ||
(lim_state == WAIT_STG3) ||
(lim_state == INIT))
wait_cnt_en_r <= #TCQ 1'b1;
else
wait_cnt_en_r <= #TCQ 1'b0;
end
// Wait counter for wait states WAIT_WR_REQ and WAIT_STG3
// To avoid DQS toggling when stage2 and 3 taps are moving
always @(posedge clk) begin
if (!wait_cnt_en_r) begin
wait_cnt_r <= #TCQ 'b0;
wait_cnt_done <= #TCQ 1'b0;
end else begin
if (wait_cnt_r != WAIT_CNT - 1) begin
wait_cnt_r <= #TCQ wait_cnt_r + 1;
wait_cnt_done <= #TCQ 1'b0;
end else begin
wait_cnt_r <= #TCQ 'b0;
wait_cnt_done <= #TCQ 1'b1;
end
end
end
/**************************Wait Counter End***********************************/
// Flip-flops
always @(posedge clk) begin
if (rst)
oclkdelay_calib_done_r <= #TCQ 1'b0;
else
oclkdelay_calib_done_r <= #TCQ oclkdelay_calib_done;
end
always @(posedge clk) begin
if (rst)
stg3_init_val <= #TCQ oclkdelay_init_val;
else if (oclkdelay_calib_done)
stg3_init_val <= #TCQ simp_stg3_final_sel;
else
stg3_init_val <= #TCQ oclkdelay_init_val;
end
always @(posedge clk) begin
if (rst) begin
lim_state <= #TCQ IDLE;
lim_start_r <= #TCQ 1'b0;
ktap_right_r <= #TCQ 1'b0;
write_request_r <= #TCQ 1'b0;
prech_req_r <= #TCQ 1'b0;
poc_ready_r <= #TCQ 1'b0;
detect_done_r <= #TCQ 1'b0;
stg3_dec_r <= #TCQ 1'b0;
stg2_inc_r <= #TCQ 1'b0;
stg3_inc2init_val_r <= #TCQ 1'b0;
stg3_inc2init_val_r1<= #TCQ 1'b0;
stg3_dec2init_val_r <= #TCQ 1'b0;
stg3_dec2init_val_r1<= #TCQ 1'b0;
stg3_dec_req_r <= #TCQ 1'b0;
stg3_inc_req_r <= #TCQ 1'b0;
stg2_dec_req_r <= #TCQ 1'b0;
stg2_inc_req_r <= #TCQ 1'b0;
done_r <= #TCQ 1'b0;
stg3_dec_val <= #TCQ 'd0;
stg3_inc_val <= #TCQ 'd0;
stg3_init_dec_r <= #TCQ 1'b0;
end else begin
lim_state <= #TCQ lim_nxt_state;
lim_start_r <= #TCQ lim_start;
ktap_right_r <= #TCQ ktap_right;
write_request_r <= #TCQ write_request;
prech_req_r <= #TCQ prech_req;
poc_ready_r <= #TCQ poc_ready;
detect_done_r <= #TCQ poc2lim_detect_done;
stg3_dec_r <= #TCQ stg3_dec;
stg2_inc_r <= #TCQ stg2_inc;
stg3_inc2init_val_r <= #TCQ stg3_inc2init_val;
stg3_inc2init_val_r1<= #TCQ stg3_inc2init_val_r;
stg3_dec2init_val_r <= #TCQ stg3_dec2init_val;
stg3_dec2init_val_r1<= #TCQ stg3_dec2init_val_r;
stg3_dec_req_r <= #TCQ stg3_dec_req;
stg3_inc_req_r <= #TCQ stg3_inc_req;
stg2_dec_req_r <= #TCQ stg2_dec_req;
stg2_inc_req_r <= #TCQ stg2_inc_req;
stg3_init_dec_r <= #TCQ stg3_init_dec;
done_r <= #TCQ done;
if (stg3_init_val > (('d63 - wl_po_fine_cnt)/2))
stg3_dec_val <= #TCQ (stg3_init_val - ('d63 - wl_po_fine_cnt)/2);
else
stg3_dec_val <= #TCQ 'd0;
if (stg3_init_val < 'd63 - ((wl_po_fine_cnt)/2))
stg3_inc_val <= #TCQ (stg3_init_val + (wl_po_fine_cnt)/2);
else
stg3_inc_val <= #TCQ 'd63;
end
end
// Keeping track of stage 3 tap count
always @(posedge clk) begin
if (rst)
stg3_tap_cnt <= #TCQ stg3_init_val;
else if ((lim_state == IDLE) || (lim_state == INIT))
stg3_tap_cnt <= #TCQ stg3_init_val;
else if (lim_state == STAGE3_INC)
stg3_tap_cnt <= #TCQ stg3_tap_cnt + 1;
else if (lim_state == STAGE3_DEC)
stg3_tap_cnt <= #TCQ stg3_tap_cnt - 1;
end
// Keeping track of stage 2 tap count
always @(posedge clk) begin
if (rst)
stg2_tap_cnt <= #TCQ 'd0;
else if ((lim_state == IDLE) || (lim_state == INIT))
stg2_tap_cnt <= #TCQ wl_po_fine_cnt;
else if (lim_state == STAGE2_INC)
stg2_tap_cnt <= #TCQ stg2_tap_cnt + 1;
else if (lim_state == STAGE2_DEC)
stg2_tap_cnt <= #TCQ stg2_tap_cnt - 1;
end
// Keeping track of MMCM tap count
always @(posedge clk) begin
if (rst) begin
mmcm_init_trail <= #TCQ 'd0;
mmcm_init_lead <= #TCQ 'd0;
end else if (poc2lim_detect_done && !detect_done_r) begin
if (stg3_tap_cnt == stg3_dec_val)
mmcm_init_trail <= #TCQ poc2lim_rise_align_taps_trail;
if (stg3_tap_cnt == stg3_inc_val)
mmcm_init_lead <= #TCQ poc2lim_rise_align_taps_lead;
end
end
always @(posedge clk) begin
if (rst) begin
mmcm_current <= #TCQ 'd0;
end else if (stg3_dec_r) begin
if (stg3_tap_cnt == stg3_dec_val)
mmcm_current <= #TCQ mmcm_init_trail;
else
mmcm_current <= #TCQ poc2lim_rise_align_taps_lead;
end else begin
if (stg3_tap_cnt == stg3_inc_val)
mmcm_current <= #TCQ mmcm_init_lead;
else
mmcm_current <= #TCQ poc2lim_rise_align_taps_trail;
end
end
// Record Stage3 Left Limit
always @(posedge clk) begin
if (rst) begin
stg3_left_lim <= #TCQ 'd0;
simp_stg3_left_lim <= #TCQ 'd0;
cmplx_stg3_left_lim <= #TCQ 'd0;
end else if (stg3_inc2init_val_r && !stg3_inc2init_val_r1) begin
stg3_left_lim <= #TCQ stg3_tap_cnt;
if (oclkdelay_calib_done)
cmplx_stg3_left_lim[oclkdelay_calib_cnt*6+:6] <= #TCQ stg3_tap_cnt;
else
simp_stg3_left_lim[oclkdelay_calib_cnt*6+:6] <= #TCQ stg3_tap_cnt;
end else if (lim_start && !lim_start_r)
stg3_left_lim <= #TCQ 'd0;
end
// Record Stage3 Right Limit
always @(posedge clk) begin
if (rst) begin
stg3_right_lim <= #TCQ 'd0;
cmplx_stg3_right_lim <= #TCQ 'd0;
simp_stg3_right_lim <= #TCQ 'd0;
end else if (stg3_dec2init_val_r && !stg3_dec2init_val_r1) begin
stg3_right_lim <= #TCQ stg3_tap_cnt;
if (oclkdelay_calib_done)
cmplx_stg3_right_lim[oclkdelay_calib_cnt*6+:6] <= #TCQ stg3_tap_cnt;
else
simp_stg3_right_lim[oclkdelay_calib_cnt*6+:6] <= #TCQ stg3_tap_cnt;
end else if (lim_start && !lim_start_r)
stg3_right_lim <= #TCQ 'd0;
end
always @(*) begin
lim_nxt_state = lim_state;
ktap_right = ktap_right_r;
write_request = write_request_r;
prech_req = prech_req_r;
poc_ready = poc_ready_r;
stg3_dec = stg3_dec_r;
stg2_inc = stg2_inc_r;
stg3_inc2init_val = stg3_inc2init_val_r;
stg3_dec2init_val = stg3_dec2init_val_r;
stg3_dec_req = stg3_dec_req_r;
stg3_inc_req = stg3_inc_req_r;
stg2_inc_req = stg2_inc_req_r;
stg2_dec_req = stg2_dec_req_r;
stg3_init_dec = stg3_init_dec_r;
done = done_r;
case(lim_state)
IDLE: begin
if (lim_start && !lim_start_r) begin
lim_nxt_state = INIT;
stg3_dec = 1'b1;
stg2_inc = 1'b1;
stg3_init_dec = 1'b1;
done = 1'b0;
end
//New start of limit module for complex oclkdelay calib
else if (oclkdelay_calib_done && !oclkdelay_calib_done_r && (BYPASS_COMPLEX_OCAL == "FALSE")) begin
done = 1'b0;
end
end
INIT: begin
ktap_right = 1'b1;
// Initial stage 2 increment to 63 for left limit
if (wait_cnt_done)
lim_nxt_state = STAGE2_TAP_CHK;
end
// Wait for DQS to toggle before asserting poc_ready
WAIT_WR_REQ: begin
write_request = 1'b1;
if (wait_cnt_done) begin
poc_ready = 1'b1;
lim_nxt_state = WAIT_POC_DONE;
end
end
// Wait for POC detect done signal
WAIT_POC_DONE: begin
if (poc2lim_detect_done) begin
write_request = 1'b0;
poc_ready = 1'b0;
lim_nxt_state = WAIT_STG3;
end
end
// Wait for DQS to stop toggling before stage3 inc/dec
WAIT_STG3: begin
if (wait_cnt_done) begin
if (stg3_dec_r) begin
// Check for Stage 3 underflow and MMCM tap limit
if ((stg3_tap_cnt > 'd0) && (mmcm_sub_dec < TDQSS_LIM_MMCM_TAPS))
lim_nxt_state = STAGE3_DEC;
else begin
stg3_dec = 1'b0;
stg3_inc2init_val = 1'b1;
lim_nxt_state = STAGE3_INC;
end
end else begin // Stage 3 being incremented
// Check for Stage 3 overflow and MMCM tap limit
if ((stg3_tap_cnt < 'd63) && (mmcm_sub_inc < TDQSS_LIM_MMCM_TAPS))
lim_nxt_state = STAGE3_INC;
else begin
stg3_dec2init_val = 1'b1;
lim_nxt_state = STAGE3_DEC;
end
end
end
end
STAGE3_INC: begin
stg3_inc_req = 1'b1;
lim_nxt_state = STG3_INCDEC_WAIT;
end
STAGE3_DEC: begin
stg3_dec_req = 1'b1;
lim_nxt_state = STG3_INCDEC_WAIT;
end
// Wait for stage3 inc/dec to complete (po_rdy)
STG3_INCDEC_WAIT: begin
stg3_dec_req = 1'b0;
stg3_inc_req = 1'b0;
if (!stg3_dec_req_r && !stg3_inc_req_r && po_rdy) begin
if (stg3_init_dec_r) begin
// Initial decrement of stage 3
if (stg3_tap_cnt > stg3_dec_val)
lim_nxt_state = STAGE3_DEC;
else begin
lim_nxt_state = WAIT_WR_REQ;
stg3_init_dec = 1'b0;
end
end else if (stg3_dec2init_val_r) begin
if (stg3_tap_cnt > stg3_init_val)
lim_nxt_state = STAGE3_DEC;
else
lim_nxt_state = STAGE2_TAP_CHK;
end else if (stg3_inc2init_val_r) begin
if (stg3_tap_cnt < stg3_inc_val)
lim_nxt_state = STAGE3_INC;
else
lim_nxt_state = STAGE2_TAP_CHK;
end else begin
lim_nxt_state = WAIT_WR_REQ;
end
end
end
// Check for overflow and underflow of stage2 taps
STAGE2_TAP_CHK: begin
if (stg3_dec2init_val_r) begin
// Increment stage 2 to write level tap value at the end of limit detection
if (stg2_tap_cnt < wl_po_fine_cnt)
lim_nxt_state = STAGE2_INC;
else begin
lim_nxt_state = PRECH_REQUEST;
end
end else if (stg3_inc2init_val_r) begin
// Decrement stage 2 to '0' to determine right limit
if (stg2_tap_cnt > 'd0)
lim_nxt_state = STAGE2_DEC;
else begin
lim_nxt_state = PRECH_REQUEST;
stg3_inc2init_val = 1'b0;
end
end else if (stg2_inc_r && (stg2_tap_cnt < 'd63)) begin
// Initial increment to 63
lim_nxt_state = STAGE2_INC;
end else begin
lim_nxt_state = STG3_INCDEC_WAIT;
stg2_inc = 1'b0;
end
end
STAGE2_INC: begin
stg2_inc_req = 1'b1;
lim_nxt_state = STG2_INCDEC_WAIT;
end
STAGE2_DEC: begin
stg2_dec_req = 1'b1;
lim_nxt_state = STG2_INCDEC_WAIT;
end
// Wait for stage3 inc/dec to complete (po_rdy)
STG2_INCDEC_WAIT: begin
stg2_inc_req = 1'b0;
stg2_dec_req = 1'b0;
if (!stg2_inc_req_r && !stg2_dec_req_r && po_rdy)
lim_nxt_state = STAGE2_TAP_CHK;
end
PRECH_REQUEST: begin
prech_req = 1'b1;
if (prech_done) begin
prech_req = 1'b0;
if (stg3_dec2init_val_r)
lim_nxt_state = LIMIT_DONE;
else
lim_nxt_state = WAIT_WR_REQ;
end
end
LIMIT_DONE: begin
done = 1'b1;
ktap_right = 1'b0;
stg3_dec2init_val = 1'b0;
lim_nxt_state = IDLE;
end
default: begin
lim_nxt_state = IDLE;
end
endcase
end
endmodule //mig_7_series_v4_0_ddr_phy_ocd_lim
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2013 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file data_fifo.v when simulating
// the core, data_fifo. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module data_fifo(
rst,
wr_clk,
rd_clk,
din,
wr_en,
rd_en,
dout,
full,
empty
);
input rst;
input wr_clk;
input rd_clk;
input [63 : 0] din;
input wr_en;
input rd_en;
output [255 : 0] dout;
output full;
output empty;
// synthesis translate_off
FIFO_GENERATOR_V8_4 #(
.C_ADD_NGC_CONSTRAINT(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_DATA_WIDTH(64),
.C_AXI_ID_WIDTH(4),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_TYPE(0),
.C_AXI_WUSER_WIDTH(1),
.C_AXIS_TDATA_WIDTH(64),
.C_AXIS_TDEST_WIDTH(4),
.C_AXIS_TID_WIDTH(8),
.C_AXIS_TKEEP_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(4),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TYPE(0),
.C_COMMON_CLOCK(0),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(10),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(64),
.C_DIN_WIDTH_AXIS(1),
.C_DIN_WIDTH_RACH(32),
.C_DIN_WIDTH_RDCH(64),
.C_DIN_WIDTH_WACH(32),
.C_DIN_WIDTH_WDCH(64),
.C_DIN_WIDTH_WRCH(2),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(256),
.C_ENABLE_RLOCS(0),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_FAMILY("virtex6"),
.C_FULL_FLAGS_RST_VAL(0),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_RD_CHANNEL(0),
.C_HAS_AXI_RUSER(0),
.C_HAS_AXI_WR_CHANNEL(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXIS_TDATA(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TKEEP(0),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TUSER(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_INT_CLK(0),
.C_HAS_MASTER_CE(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SLAVE_CE(0),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(2),
.C_IMPLEMENTATION_TYPE_AXIS(11),
.C_IMPLEMENTATION_TYPE_RACH(12),
.C_IMPLEMENTATION_TYPE_RDCH(11),
.C_IMPLEMENTATION_TYPE_WACH(12),
.C_IMPLEMENTATION_TYPE_WDCH(11),
.C_IMPLEMENTATION_TYPE_WRCH(12),
.C_INIT_WR_PNTR_VAL(0),
.C_INTERFACE_TYPE(0),
.C_MEMORY_TYPE(1),
.C_MIF_FILE_NAME("BlankString"),
.C_MSGON_VAL(1),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(0),
.C_PRELOAD_REGS(1),
.C_PRIM_FIFO_TYPE("1kx36"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_EMPTY_TYPE_AXIS(5),
.C_PROG_EMPTY_TYPE_RACH(5),
.C_PROG_EMPTY_TYPE_RDCH(5),
.C_PROG_EMPTY_TYPE_WACH(5),
.C_PROG_EMPTY_TYPE_WDCH(5),
.C_PROG_EMPTY_TYPE_WRCH(5),
.C_PROG_FULL_THRESH_ASSERT_VAL(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
.C_PROG_FULL_THRESH_NEGATE_VAL(1022),
.C_PROG_FULL_TYPE(0),
.C_PROG_FULL_TYPE_AXIS(5),
.C_PROG_FULL_TYPE_RACH(5),
.C_PROG_FULL_TYPE_RDCH(5),
.C_PROG_FULL_TYPE_WACH(5),
.C_PROG_FULL_TYPE_WDCH(5),
.C_PROG_FULL_TYPE_WRCH(5),
.C_RACH_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(8),
.C_RD_DEPTH(256),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(8),
.C_RDCH_TYPE(0),
.C_REG_SLICE_MODE_AXIS(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_SYNCHRONIZER_STAGE(2),
.C_UNDERFLOW_LOW(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_ECC_AXIS(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(0),
.C_VALID_LOW(0),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(10),
.C_WR_DEPTH(1024),
.C_WR_DEPTH_AXIS(1024),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(10),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_RESPONSE_LATENCY(1),
.C_WRCH_TYPE(0)
)
inst (
.RST(rst),
.WR_CLK(wr_clk),
.RD_CLK(rd_clk),
.DIN(din),
.WR_EN(wr_en),
.RD_EN(rd_en),
.DOUT(dout),
.FULL(full),
.EMPTY(empty),
.BACKUP(),
.BACKUP_MARKER(),
.CLK(),
.SRST(),
.WR_RST(),
.RD_RST(),
.PROG_EMPTY_THRESH(),
.PROG_EMPTY_THRESH_ASSERT(),
.PROG_EMPTY_THRESH_NEGATE(),
.PROG_FULL_THRESH(),
.PROG_FULL_THRESH_ASSERT(),
.PROG_FULL_THRESH_NEGATE(),
.INT_CLK(),
.INJECTDBITERR(),
.INJECTSBITERR(),
.ALMOST_FULL(),
.WR_ACK(),
.OVERFLOW(),
.ALMOST_EMPTY(),
.VALID(),
.UNDERFLOW(),
.DATA_COUNT(),
.RD_DATA_COUNT(),
.WR_DATA_COUNT(),
.PROG_FULL(),
.PROG_EMPTY(),
.SBITERR(),
.DBITERR(),
.M_ACLK(),
.S_ACLK(),
.S_ARESETN(),
.M_ACLK_EN(),
.S_ACLK_EN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWLOCK(),
.S_AXI_AWCACHE(),
.S_AXI_AWPROT(),
.S_AXI_AWQOS(),
.S_AXI_AWREGION(),
.S_AXI_AWUSER(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WID(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WUSER(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BUSER(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.M_AXI_AWID(),
.M_AXI_AWADDR(),
.M_AXI_AWLEN(),
.M_AXI_AWSIZE(),
.M_AXI_AWBURST(),
.M_AXI_AWLOCK(),
.M_AXI_AWCACHE(),
.M_AXI_AWPROT(),
.M_AXI_AWQOS(),
.M_AXI_AWREGION(),
.M_AXI_AWUSER(),
.M_AXI_AWVALID(),
.M_AXI_AWREADY(),
.M_AXI_WID(),
.M_AXI_WDATA(),
.M_AXI_WSTRB(),
.M_AXI_WLAST(),
.M_AXI_WUSER(),
.M_AXI_WVALID(),
.M_AXI_WREADY(),
.M_AXI_BID(),
.M_AXI_BRESP(),
.M_AXI_BUSER(),
.M_AXI_BVALID(),
.M_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARLOCK(),
.S_AXI_ARCACHE(),
.S_AXI_ARPROT(),
.S_AXI_ARQOS(),
.S_AXI_ARREGION(),
.S_AXI_ARUSER(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RUSER(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.M_AXI_ARID(),
.M_AXI_ARADDR(),
.M_AXI_ARLEN(),
.M_AXI_ARSIZE(),
.M_AXI_ARBURST(),
.M_AXI_ARLOCK(),
.M_AXI_ARCACHE(),
.M_AXI_ARPROT(),
.M_AXI_ARQOS(),
.M_AXI_ARREGION(),
.M_AXI_ARUSER(),
.M_AXI_ARVALID(),
.M_AXI_ARREADY(),
.M_AXI_RID(),
.M_AXI_RDATA(),
.M_AXI_RRESP(),
.M_AXI_RLAST(),
.M_AXI_RUSER(),
.M_AXI_RVALID(),
.M_AXI_RREADY(),
.S_AXIS_TVALID(),
.S_AXIS_TREADY(),
.S_AXIS_TDATA(),
.S_AXIS_TSTRB(),
.S_AXIS_TKEEP(),
.S_AXIS_TLAST(),
.S_AXIS_TID(),
.S_AXIS_TDEST(),
.S_AXIS_TUSER(),
.M_AXIS_TVALID(),
.M_AXIS_TREADY(),
.M_AXIS_TDATA(),
.M_AXIS_TSTRB(),
.M_AXIS_TKEEP(),
.M_AXIS_TLAST(),
.M_AXIS_TID(),
.M_AXIS_TDEST(),
.M_AXIS_TUSER(),
.AXI_AW_INJECTSBITERR(),
.AXI_AW_INJECTDBITERR(),
.AXI_AW_PROG_FULL_THRESH(),
.AXI_AW_PROG_EMPTY_THRESH(),
.AXI_AW_DATA_COUNT(),
.AXI_AW_WR_DATA_COUNT(),
.AXI_AW_RD_DATA_COUNT(),
.AXI_AW_SBITERR(),
.AXI_AW_DBITERR(),
.AXI_AW_OVERFLOW(),
.AXI_AW_UNDERFLOW(),
.AXI_W_INJECTSBITERR(),
.AXI_W_INJECTDBITERR(),
.AXI_W_PROG_FULL_THRESH(),
.AXI_W_PROG_EMPTY_THRESH(),
.AXI_W_DATA_COUNT(),
.AXI_W_WR_DATA_COUNT(),
.AXI_W_RD_DATA_COUNT(),
.AXI_W_SBITERR(),
.AXI_W_DBITERR(),
.AXI_W_OVERFLOW(),
.AXI_W_UNDERFLOW(),
.AXI_B_INJECTSBITERR(),
.AXI_B_INJECTDBITERR(),
.AXI_B_PROG_FULL_THRESH(),
.AXI_B_PROG_EMPTY_THRESH(),
.AXI_B_DATA_COUNT(),
.AXI_B_WR_DATA_COUNT(),
.AXI_B_RD_DATA_COUNT(),
.AXI_B_SBITERR(),
.AXI_B_DBITERR(),
.AXI_B_OVERFLOW(),
.AXI_B_UNDERFLOW(),
.AXI_AR_INJECTSBITERR(),
.AXI_AR_INJECTDBITERR(),
.AXI_AR_PROG_FULL_THRESH(),
.AXI_AR_PROG_EMPTY_THRESH(),
.AXI_AR_DATA_COUNT(),
.AXI_AR_WR_DATA_COUNT(),
.AXI_AR_RD_DATA_COUNT(),
.AXI_AR_SBITERR(),
.AXI_AR_DBITERR(),
.AXI_AR_OVERFLOW(),
.AXI_AR_UNDERFLOW(),
.AXI_R_INJECTSBITERR(),
.AXI_R_INJECTDBITERR(),
.AXI_R_PROG_FULL_THRESH(),
.AXI_R_PROG_EMPTY_THRESH(),
.AXI_R_DATA_COUNT(),
.AXI_R_WR_DATA_COUNT(),
.AXI_R_RD_DATA_COUNT(),
.AXI_R_SBITERR(),
.AXI_R_DBITERR(),
.AXI_R_OVERFLOW(),
.AXI_R_UNDERFLOW(),
.AXIS_INJECTSBITERR(),
.AXIS_INJECTDBITERR(),
.AXIS_PROG_FULL_THRESH(),
.AXIS_PROG_EMPTY_THRESH(),
.AXIS_DATA_COUNT(),
.AXIS_WR_DATA_COUNT(),
.AXIS_RD_DATA_COUNT(),
.AXIS_SBITERR(),
.AXIS_DBITERR(),
.AXIS_OVERFLOW(),
.AXIS_UNDERFLOW()
);
// synthesis translate_on
endmodule
|
//-----------------------------------------------------------------------------
// The way that we connect things when transmitting a command to an ISO
// 15693 tag, using 100% modulation only for now.
//
// Jonathan Westhues, April 2006
//-----------------------------------------------------------------------------
module hi_read_tx(
pck0, ck_1356meg, ck_1356megb,
pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
adc_d, adc_clk,
ssp_frame, ssp_din, ssp_dout, ssp_clk,
cross_hi, cross_lo,
dbg,
shallow_modulation
);
input pck0, ck_1356meg, ck_1356megb;
output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
input [7:0] adc_d;
output adc_clk;
input ssp_dout;
output ssp_frame, ssp_din, ssp_clk;
input cross_hi, cross_lo;
output dbg;
input shallow_modulation;
// The high-frequency stuff. For now, for testing, just bring out the carrier,
// and allow the ARM to modulate it over the SSP.
reg pwr_hi;
reg pwr_oe1;
reg pwr_oe2;
reg pwr_oe3;
reg pwr_oe4;
always @(ck_1356megb or ssp_dout or shallow_modulation)
begin
if(shallow_modulation)
begin
pwr_hi <= ck_1356megb;
pwr_oe1 <= ~ssp_dout;
pwr_oe2 <= ~ssp_dout;
pwr_oe3 <= ~ssp_dout;
pwr_oe4 <= 1'b0;
end
else
begin
pwr_hi <= ck_1356megb & ssp_dout;
pwr_oe1 <= 1'b0;
pwr_oe2 <= 1'b0;
pwr_oe3 <= 1'b0;
pwr_oe4 <= 1'b0;
end
end
// Then just divide the 13.56 MHz clock down to produce appropriate clocks
// for the synchronous serial port.
reg [6:0] hi_div_by_128;
always @(posedge ck_1356meg)
hi_div_by_128 <= hi_div_by_128 + 1;
assign ssp_clk = hi_div_by_128[6];
reg [2:0] hi_byte_div;
always @(negedge ssp_clk)
hi_byte_div <= hi_byte_div + 1;
assign ssp_frame = (hi_byte_div == 3'b000);
// Implement a hysteresis to give out the received signal on
// ssp_din. Sample at fc.
assign adc_clk = ck_1356meg;
// ADC data appears on the rising edge, so sample it on the falling edge
reg after_hysteresis;
always @(negedge adc_clk)
begin
if(& adc_d[7:0]) after_hysteresis <= 1'b1;
else if(~(| adc_d[7:0])) after_hysteresis <= 1'b0;
end
assign ssp_din = after_hysteresis;
assign pwr_lo = 1'b0;
assign dbg = ssp_din;
endmodule
|
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